1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <acpi/video.h> 28 #include <linux/i2c.h> 29 #include <linux/input.h> 30 #include <linux/intel-iommu.h> 31 #include <linux/kernel.h> 32 #include <linux/module.h> 33 #include <linux/dma-resv.h> 34 #include <linux/slab.h> 35 #include <linux/string_helpers.h> 36 #include <linux/vga_switcheroo.h> 37 38 #include <drm/drm_atomic.h> 39 #include <drm/drm_atomic_helper.h> 40 #include <drm/drm_atomic_uapi.h> 41 #include <drm/drm_damage_helper.h> 42 #include <drm/dp/drm_dp_helper.h> 43 #include <drm/drm_edid.h> 44 #include <drm/drm_fourcc.h> 45 #include <drm/drm_plane_helper.h> 46 #include <drm/drm_privacy_screen_consumer.h> 47 #include <drm/drm_probe_helper.h> 48 #include <drm/drm_rect.h> 49 50 #include "display/intel_audio.h" 51 #include "display/intel_crt.h" 52 #include "display/intel_ddi.h" 53 #include "display/intel_display_debugfs.h" 54 #include "display/intel_display_power.h" 55 #include "display/intel_dp.h" 56 #include "display/intel_dp_mst.h" 57 #include "display/intel_dpll.h" 58 #include "display/intel_dpll_mgr.h" 59 #include "display/intel_drrs.h" 60 #include "display/intel_dsi.h" 61 #include "display/intel_dvo.h" 62 #include "display/intel_fb.h" 63 #include "display/intel_gmbus.h" 64 #include "display/intel_hdmi.h" 65 #include "display/intel_lvds.h" 66 #include "display/intel_sdvo.h" 67 #include "display/intel_snps_phy.h" 68 #include "display/intel_tv.h" 69 #include "display/intel_vdsc.h" 70 #include "display/intel_vrr.h" 71 72 #include "gem/i915_gem_lmem.h" 73 #include "gem/i915_gem_object.h" 74 75 #include "gt/gen8_ppgtt.h" 76 77 #include "g4x_dp.h" 78 #include "g4x_hdmi.h" 79 #include "hsw_ips.h" 80 #include "i915_drv.h" 81 #include "i915_utils.h" 82 #include "icl_dsi.h" 83 #include "intel_acpi.h" 84 #include "intel_atomic.h" 85 #include "intel_atomic_plane.h" 86 #include "intel_bw.h" 87 #include "intel_cdclk.h" 88 #include "intel_color.h" 89 #include "intel_crtc.h" 90 #include "intel_de.h" 91 #include "intel_display_types.h" 92 #include "intel_dmc.h" 93 #include "intel_dp_link_training.h" 94 #include "intel_dpt.h" 95 #include "intel_fbc.h" 96 #include "intel_fbdev.h" 97 #include "intel_fdi.h" 98 #include "intel_fifo_underrun.h" 99 #include "intel_frontbuffer.h" 100 #include "intel_hdcp.h" 101 #include "intel_hotplug.h" 102 #include "intel_overlay.h" 103 #include "intel_panel.h" 104 #include "intel_pch_display.h" 105 #include "intel_pch_refclk.h" 106 #include "intel_pcode.h" 107 #include "intel_pipe_crc.h" 108 #include "intel_plane_initial.h" 109 #include "intel_pm.h" 110 #include "intel_pps.h" 111 #include "intel_psr.h" 112 #include "intel_quirks.h" 113 #include "intel_sprite.h" 114 #include "intel_tc.h" 115 #include "intel_vga.h" 116 #include "i9xx_plane.h" 117 #include "skl_scaler.h" 118 #include "skl_universal_plane.h" 119 #include "vlv_dsi.h" 120 #include "vlv_dsi_pll.h" 121 #include "vlv_dsi_regs.h" 122 #include "vlv_sideband.h" 123 124 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state); 125 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state); 126 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state); 127 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state); 128 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state); 129 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state); 130 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state); 131 static void intel_modeset_setup_hw_state(struct drm_device *dev, 132 struct drm_modeset_acquire_ctx *ctx); 133 134 /** 135 * intel_update_watermarks - update FIFO watermark values based on current modes 136 * @dev_priv: i915 device 137 * 138 * Calculate watermark values for the various WM regs based on current mode 139 * and plane configuration. 140 * 141 * There are several cases to deal with here: 142 * - normal (i.e. non-self-refresh) 143 * - self-refresh (SR) mode 144 * - lines are large relative to FIFO size (buffer can hold up to 2) 145 * - lines are small relative to FIFO size (buffer can hold more than 2 146 * lines), so need to account for TLB latency 147 * 148 * The normal calculation is: 149 * watermark = dotclock * bytes per pixel * latency 150 * where latency is platform & configuration dependent (we assume pessimal 151 * values here). 152 * 153 * The SR calculation is: 154 * watermark = (trunc(latency/line time)+1) * surface width * 155 * bytes per pixel 156 * where 157 * line time = htotal / dotclock 158 * surface width = hdisplay for normal plane and 64 for cursor 159 * and latency is assumed to be high, as above. 160 * 161 * The final value programmed to the register should always be rounded up, 162 * and include an extra 2 entries to account for clock crossings. 163 * 164 * We don't use the sprite, so we can ignore that. And on Crestline we have 165 * to set the non-SR watermarks to 8. 166 */ 167 static void intel_update_watermarks(struct drm_i915_private *dev_priv) 168 { 169 if (dev_priv->wm_disp->update_wm) 170 dev_priv->wm_disp->update_wm(dev_priv); 171 } 172 173 static int intel_compute_pipe_wm(struct intel_atomic_state *state, 174 struct intel_crtc *crtc) 175 { 176 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 177 if (dev_priv->wm_disp->compute_pipe_wm) 178 return dev_priv->wm_disp->compute_pipe_wm(state, crtc); 179 return 0; 180 } 181 182 static int intel_compute_intermediate_wm(struct intel_atomic_state *state, 183 struct intel_crtc *crtc) 184 { 185 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 186 if (!dev_priv->wm_disp->compute_intermediate_wm) 187 return 0; 188 if (drm_WARN_ON(&dev_priv->drm, 189 !dev_priv->wm_disp->compute_pipe_wm)) 190 return 0; 191 return dev_priv->wm_disp->compute_intermediate_wm(state, crtc); 192 } 193 194 static bool intel_initial_watermarks(struct intel_atomic_state *state, 195 struct intel_crtc *crtc) 196 { 197 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 198 if (dev_priv->wm_disp->initial_watermarks) { 199 dev_priv->wm_disp->initial_watermarks(state, crtc); 200 return true; 201 } 202 return false; 203 } 204 205 static void intel_atomic_update_watermarks(struct intel_atomic_state *state, 206 struct intel_crtc *crtc) 207 { 208 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 209 if (dev_priv->wm_disp->atomic_update_watermarks) 210 dev_priv->wm_disp->atomic_update_watermarks(state, crtc); 211 } 212 213 static void intel_optimize_watermarks(struct intel_atomic_state *state, 214 struct intel_crtc *crtc) 215 { 216 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 217 if (dev_priv->wm_disp->optimize_watermarks) 218 dev_priv->wm_disp->optimize_watermarks(state, crtc); 219 } 220 221 static int intel_compute_global_watermarks(struct intel_atomic_state *state) 222 { 223 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 224 if (dev_priv->wm_disp->compute_global_watermarks) 225 return dev_priv->wm_disp->compute_global_watermarks(state); 226 return 0; 227 } 228 229 /* returns HPLL frequency in kHz */ 230 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) 231 { 232 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; 233 234 /* Obtain SKU information */ 235 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & 236 CCK_FUSE_HPLL_FREQ_MASK; 237 238 return vco_freq[hpll_freq] * 1000; 239 } 240 241 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 242 const char *name, u32 reg, int ref_freq) 243 { 244 u32 val; 245 int divider; 246 247 val = vlv_cck_read(dev_priv, reg); 248 divider = val & CCK_FREQUENCY_VALUES; 249 250 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != 251 (divider << CCK_FREQUENCY_STATUS_SHIFT), 252 "%s change in progress\n", name); 253 254 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); 255 } 256 257 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 258 const char *name, u32 reg) 259 { 260 int hpll; 261 262 vlv_cck_get(dev_priv); 263 264 if (dev_priv->hpll_freq == 0) 265 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); 266 267 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); 268 269 vlv_cck_put(dev_priv); 270 271 return hpll; 272 } 273 274 static void intel_update_czclk(struct drm_i915_private *dev_priv) 275 { 276 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) 277 return; 278 279 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", 280 CCK_CZ_CLOCK_CONTROL); 281 282 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", 283 dev_priv->czclk_freq); 284 } 285 286 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state) 287 { 288 return (crtc_state->active_planes & 289 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0; 290 } 291 292 /* WA Display #0827: Gen9:all */ 293 static void 294 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) 295 { 296 if (enable) 297 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 298 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS); 299 else 300 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 301 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS)); 302 } 303 304 /* Wa_2006604312:icl,ehl */ 305 static void 306 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 307 bool enable) 308 { 309 if (enable) 310 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 311 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS); 312 else 313 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 314 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS); 315 } 316 317 /* Wa_1604331009:icl,jsl,ehl */ 318 static void 319 icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 320 bool enable) 321 { 322 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), CURSOR_GATING_DIS, 323 enable ? CURSOR_GATING_DIS : 0); 324 } 325 326 static bool 327 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state) 328 { 329 return crtc_state->master_transcoder != INVALID_TRANSCODER; 330 } 331 332 static bool 333 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state) 334 { 335 return crtc_state->sync_mode_slaves_mask != 0; 336 } 337 338 bool 339 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state) 340 { 341 return is_trans_port_sync_master(crtc_state) || 342 is_trans_port_sync_slave(crtc_state); 343 } 344 345 static enum pipe bigjoiner_master_pipe(const struct intel_crtc_state *crtc_state) 346 { 347 return ffs(crtc_state->bigjoiner_pipes) - 1; 348 } 349 350 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state) 351 { 352 if (crtc_state->bigjoiner_pipes) 353 return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state)); 354 else 355 return 0; 356 } 357 358 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state) 359 { 360 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 361 362 return crtc_state->bigjoiner_pipes && 363 crtc->pipe != bigjoiner_master_pipe(crtc_state); 364 } 365 366 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state) 367 { 368 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 369 370 return crtc_state->bigjoiner_pipes && 371 crtc->pipe == bigjoiner_master_pipe(crtc_state); 372 } 373 374 static int intel_bigjoiner_num_pipes(const struct intel_crtc_state *crtc_state) 375 { 376 return hweight8(crtc_state->bigjoiner_pipes); 377 } 378 379 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state) 380 { 381 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 382 383 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 384 return intel_crtc_for_pipe(i915, bigjoiner_master_pipe(crtc_state)); 385 else 386 return to_intel_crtc(crtc_state->uapi.crtc); 387 } 388 389 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv, 390 enum pipe pipe) 391 { 392 i915_reg_t reg = PIPEDSL(pipe); 393 u32 line1, line2; 394 395 line1 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK; 396 msleep(5); 397 line2 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK; 398 399 return line1 != line2; 400 } 401 402 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state) 403 { 404 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 405 enum pipe pipe = crtc->pipe; 406 407 /* Wait for the display line to settle/start moving */ 408 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100)) 409 drm_err(&dev_priv->drm, 410 "pipe %c scanline %s wait timed out\n", 411 pipe_name(pipe), str_on_off(state)); 412 } 413 414 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc) 415 { 416 wait_for_pipe_scanline_moving(crtc, false); 417 } 418 419 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc) 420 { 421 wait_for_pipe_scanline_moving(crtc, true); 422 } 423 424 static void 425 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) 426 { 427 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 428 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 429 430 if (DISPLAY_VER(dev_priv) >= 4) { 431 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 432 433 /* Wait for the Pipe State to go off */ 434 if (intel_de_wait_for_clear(dev_priv, PIPECONF(cpu_transcoder), 435 PIPECONF_STATE_ENABLE, 100)) 436 drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n"); 437 } else { 438 intel_wait_for_pipe_scanline_stopped(crtc); 439 } 440 } 441 442 void assert_transcoder(struct drm_i915_private *dev_priv, 443 enum transcoder cpu_transcoder, bool state) 444 { 445 bool cur_state; 446 enum intel_display_power_domain power_domain; 447 intel_wakeref_t wakeref; 448 449 /* we keep both pipes enabled on 830 */ 450 if (IS_I830(dev_priv)) 451 state = true; 452 453 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 454 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 455 if (wakeref) { 456 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); 457 cur_state = !!(val & PIPECONF_ENABLE); 458 459 intel_display_power_put(dev_priv, power_domain, wakeref); 460 } else { 461 cur_state = false; 462 } 463 464 I915_STATE_WARN(cur_state != state, 465 "transcoder %s assertion failure (expected %s, current %s)\n", 466 transcoder_name(cpu_transcoder), 467 str_on_off(state), str_on_off(cur_state)); 468 } 469 470 static void assert_plane(struct intel_plane *plane, bool state) 471 { 472 enum pipe pipe; 473 bool cur_state; 474 475 cur_state = plane->get_hw_state(plane, &pipe); 476 477 I915_STATE_WARN(cur_state != state, 478 "%s assertion failure (expected %s, current %s)\n", 479 plane->base.name, str_on_off(state), 480 str_on_off(cur_state)); 481 } 482 483 #define assert_plane_enabled(p) assert_plane(p, true) 484 #define assert_plane_disabled(p) assert_plane(p, false) 485 486 static void assert_planes_disabled(struct intel_crtc *crtc) 487 { 488 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 489 struct intel_plane *plane; 490 491 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) 492 assert_plane_disabled(plane); 493 } 494 495 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 496 struct intel_digital_port *dig_port, 497 unsigned int expected_mask) 498 { 499 u32 port_mask; 500 i915_reg_t dpll_reg; 501 502 switch (dig_port->base.port) { 503 case PORT_B: 504 port_mask = DPLL_PORTB_READY_MASK; 505 dpll_reg = DPLL(0); 506 break; 507 case PORT_C: 508 port_mask = DPLL_PORTC_READY_MASK; 509 dpll_reg = DPLL(0); 510 expected_mask <<= 4; 511 break; 512 case PORT_D: 513 port_mask = DPLL_PORTD_READY_MASK; 514 dpll_reg = DPIO_PHY_STATUS; 515 break; 516 default: 517 BUG(); 518 } 519 520 if (intel_de_wait_for_register(dev_priv, dpll_reg, 521 port_mask, expected_mask, 1000)) 522 drm_WARN(&dev_priv->drm, 1, 523 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", 524 dig_port->base.base.base.id, dig_port->base.base.name, 525 intel_de_read(dev_priv, dpll_reg) & port_mask, 526 expected_mask); 527 } 528 529 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) 530 { 531 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 532 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 533 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 534 enum pipe pipe = crtc->pipe; 535 i915_reg_t reg; 536 u32 val; 537 538 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe)); 539 540 assert_planes_disabled(crtc); 541 542 /* 543 * A pipe without a PLL won't actually be able to drive bits from 544 * a plane. On ILK+ the pipe PLLs are integrated, so we don't 545 * need the check. 546 */ 547 if (HAS_GMCH(dev_priv)) { 548 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI)) 549 assert_dsi_pll_enabled(dev_priv); 550 else 551 assert_pll_enabled(dev_priv, pipe); 552 } else { 553 if (new_crtc_state->has_pch_encoder) { 554 /* if driving the PCH, we need FDI enabled */ 555 assert_fdi_rx_pll_enabled(dev_priv, 556 intel_crtc_pch_transcoder(crtc)); 557 assert_fdi_tx_pll_enabled(dev_priv, 558 (enum pipe) cpu_transcoder); 559 } 560 /* FIXME: assert CPU port conditions for SNB+ */ 561 } 562 563 /* Wa_22012358565:adl-p */ 564 if (DISPLAY_VER(dev_priv) == 13) 565 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe), 566 0, PIPE_ARB_USE_PROG_SLOTS); 567 568 reg = PIPECONF(cpu_transcoder); 569 val = intel_de_read(dev_priv, reg); 570 if (val & PIPECONF_ENABLE) { 571 /* we keep both pipes enabled on 830 */ 572 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv)); 573 return; 574 } 575 576 intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE); 577 intel_de_posting_read(dev_priv, reg); 578 579 /* 580 * Until the pipe starts PIPEDSL reads will return a stale value, 581 * which causes an apparent vblank timestamp jump when PIPEDSL 582 * resets to its proper value. That also messes up the frame count 583 * when it's derived from the timestamps. So let's wait for the 584 * pipe to start properly before we call drm_crtc_vblank_on() 585 */ 586 if (intel_crtc_max_vblank_count(new_crtc_state) == 0) 587 intel_wait_for_pipe_scanline_moving(crtc); 588 } 589 590 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) 591 { 592 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 593 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 594 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 595 enum pipe pipe = crtc->pipe; 596 i915_reg_t reg; 597 u32 val; 598 599 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe)); 600 601 /* 602 * Make sure planes won't keep trying to pump pixels to us, 603 * or we might hang the display. 604 */ 605 assert_planes_disabled(crtc); 606 607 reg = PIPECONF(cpu_transcoder); 608 val = intel_de_read(dev_priv, reg); 609 if ((val & PIPECONF_ENABLE) == 0) 610 return; 611 612 /* 613 * Double wide has implications for planes 614 * so best keep it disabled when not needed. 615 */ 616 if (old_crtc_state->double_wide) 617 val &= ~PIPECONF_DOUBLE_WIDE; 618 619 /* Don't disable pipe or pipe PLLs if needed */ 620 if (!IS_I830(dev_priv)) 621 val &= ~PIPECONF_ENABLE; 622 623 if (DISPLAY_VER(dev_priv) >= 12) 624 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 625 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 626 627 intel_de_write(dev_priv, reg, val); 628 if ((val & PIPECONF_ENABLE) == 0) 629 intel_wait_for_pipe_off(old_crtc_state); 630 } 631 632 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) 633 { 634 unsigned int size = 0; 635 int i; 636 637 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) 638 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width; 639 640 return size; 641 } 642 643 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info) 644 { 645 unsigned int size = 0; 646 int i; 647 648 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) { 649 unsigned int plane_size; 650 651 if (rem_info->plane[i].linear) 652 plane_size = rem_info->plane[i].size; 653 else 654 plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height; 655 656 if (plane_size == 0) 657 continue; 658 659 if (rem_info->plane_alignment) 660 size = ALIGN(size, rem_info->plane_alignment); 661 662 size += plane_size; 663 } 664 665 return size; 666 } 667 668 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) 669 { 670 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 671 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 672 673 return DISPLAY_VER(dev_priv) < 4 || 674 (plane->fbc && 675 plane_state->view.gtt.type == I915_GGTT_VIEW_NORMAL); 676 } 677 678 /* 679 * Convert the x/y offsets into a linear offset. 680 * Only valid with 0/180 degree rotation, which is fine since linear 681 * offset is only used with linear buffers on pre-hsw and tiled buffers 682 * with gen2/3, and 90/270 degree rotations isn't supported on any of them. 683 */ 684 u32 intel_fb_xy_to_linear(int x, int y, 685 const struct intel_plane_state *state, 686 int color_plane) 687 { 688 const struct drm_framebuffer *fb = state->hw.fb; 689 unsigned int cpp = fb->format->cpp[color_plane]; 690 unsigned int pitch = state->view.color_plane[color_plane].mapping_stride; 691 692 return y * pitch + x * cpp; 693 } 694 695 /* 696 * Add the x/y offsets derived from fb->offsets[] to the user 697 * specified plane src x/y offsets. The resulting x/y offsets 698 * specify the start of scanout from the beginning of the gtt mapping. 699 */ 700 void intel_add_fb_offsets(int *x, int *y, 701 const struct intel_plane_state *state, 702 int color_plane) 703 704 { 705 *x += state->view.color_plane[color_plane].x; 706 *y += state->view.color_plane[color_plane].y; 707 } 708 709 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 710 u32 pixel_format, u64 modifier) 711 { 712 struct intel_crtc *crtc; 713 struct intel_plane *plane; 714 715 if (!HAS_DISPLAY(dev_priv)) 716 return 0; 717 718 /* 719 * We assume the primary plane for pipe A has 720 * the highest stride limits of them all, 721 * if in case pipe A is disabled, use the first pipe from pipe_mask. 722 */ 723 crtc = intel_first_crtc(dev_priv); 724 if (!crtc) 725 return 0; 726 727 plane = to_intel_plane(crtc->base.primary); 728 729 return plane->max_stride(plane, pixel_format, modifier, 730 DRM_MODE_ROTATE_0); 731 } 732 733 static void 734 intel_set_plane_visible(struct intel_crtc_state *crtc_state, 735 struct intel_plane_state *plane_state, 736 bool visible) 737 { 738 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 739 740 plane_state->uapi.visible = visible; 741 742 if (visible) 743 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base); 744 else 745 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base); 746 } 747 748 static void fixup_plane_bitmasks(struct intel_crtc_state *crtc_state) 749 { 750 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 751 struct drm_plane *plane; 752 753 /* 754 * Active_planes aliases if multiple "primary" or cursor planes 755 * have been used on the same (or wrong) pipe. plane_mask uses 756 * unique ids, hence we can use that to reconstruct active_planes. 757 */ 758 crtc_state->enabled_planes = 0; 759 crtc_state->active_planes = 0; 760 761 drm_for_each_plane_mask(plane, &dev_priv->drm, 762 crtc_state->uapi.plane_mask) { 763 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id); 764 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id); 765 } 766 } 767 768 void intel_plane_disable_noatomic(struct intel_crtc *crtc, 769 struct intel_plane *plane) 770 { 771 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 772 struct intel_crtc_state *crtc_state = 773 to_intel_crtc_state(crtc->base.state); 774 struct intel_plane_state *plane_state = 775 to_intel_plane_state(plane->base.state); 776 777 drm_dbg_kms(&dev_priv->drm, 778 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n", 779 plane->base.base.id, plane->base.name, 780 crtc->base.base.id, crtc->base.name); 781 782 intel_set_plane_visible(crtc_state, plane_state, false); 783 fixup_plane_bitmasks(crtc_state); 784 crtc_state->data_rate[plane->id] = 0; 785 crtc_state->data_rate_y[plane->id] = 0; 786 crtc_state->rel_data_rate[plane->id] = 0; 787 crtc_state->rel_data_rate_y[plane->id] = 0; 788 crtc_state->min_cdclk[plane->id] = 0; 789 790 if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 && 791 hsw_ips_disable(crtc_state)) { 792 crtc_state->ips_enabled = false; 793 intel_crtc_wait_for_next_vblank(crtc); 794 } 795 796 /* 797 * Vblank time updates from the shadow to live plane control register 798 * are blocked if the memory self-refresh mode is active at that 799 * moment. So to make sure the plane gets truly disabled, disable 800 * first the self-refresh mode. The self-refresh enable bit in turn 801 * will be checked/applied by the HW only at the next frame start 802 * event which is after the vblank start event, so we need to have a 803 * wait-for-vblank between disabling the plane and the pipe. 804 */ 805 if (HAS_GMCH(dev_priv) && 806 intel_set_memory_cxsr(dev_priv, false)) 807 intel_crtc_wait_for_next_vblank(crtc); 808 809 /* 810 * Gen2 reports pipe underruns whenever all planes are disabled. 811 * So disable underrun reporting before all the planes get disabled. 812 */ 813 if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes) 814 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); 815 816 intel_plane_disable_arm(plane, crtc_state); 817 intel_crtc_wait_for_next_vblank(crtc); 818 } 819 820 unsigned int 821 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state) 822 { 823 int x = 0, y = 0; 824 825 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, 826 plane_state->view.color_plane[0].offset, 0); 827 828 return y; 829 } 830 831 static int 832 __intel_display_resume(struct drm_device *dev, 833 struct drm_atomic_state *state, 834 struct drm_modeset_acquire_ctx *ctx) 835 { 836 struct drm_crtc_state *crtc_state; 837 struct drm_crtc *crtc; 838 int i, ret; 839 840 intel_modeset_setup_hw_state(dev, ctx); 841 intel_vga_redisable(to_i915(dev)); 842 843 if (!state) 844 return 0; 845 846 /* 847 * We've duplicated the state, pointers to the old state are invalid. 848 * 849 * Don't attempt to use the old state until we commit the duplicated state. 850 */ 851 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 852 /* 853 * Force recalculation even if we restore 854 * current state. With fast modeset this may not result 855 * in a modeset when the state is compatible. 856 */ 857 crtc_state->mode_changed = true; 858 } 859 860 /* ignore any reset values/BIOS leftovers in the WM registers */ 861 if (!HAS_GMCH(to_i915(dev))) 862 to_intel_atomic_state(state)->skip_intermediate_wm = true; 863 864 ret = drm_atomic_helper_commit_duplicated_state(state, ctx); 865 866 drm_WARN_ON(dev, ret == -EDEADLK); 867 return ret; 868 } 869 870 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) 871 { 872 return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display && 873 intel_has_gpu_reset(to_gt(dev_priv))); 874 } 875 876 void intel_display_prepare_reset(struct drm_i915_private *dev_priv) 877 { 878 struct drm_device *dev = &dev_priv->drm; 879 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; 880 struct drm_atomic_state *state; 881 int ret; 882 883 if (!HAS_DISPLAY(dev_priv)) 884 return; 885 886 /* reset doesn't touch the display */ 887 if (!dev_priv->params.force_reset_modeset_test && 888 !gpu_reset_clobbers_display(dev_priv)) 889 return; 890 891 /* We have a modeset vs reset deadlock, defensively unbreak it. */ 892 set_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags); 893 smp_mb__after_atomic(); 894 wake_up_bit(&to_gt(dev_priv)->reset.flags, I915_RESET_MODESET); 895 896 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) { 897 drm_dbg_kms(&dev_priv->drm, 898 "Modeset potentially stuck, unbreaking through wedging\n"); 899 intel_gt_set_wedged(to_gt(dev_priv)); 900 } 901 902 /* 903 * Need mode_config.mutex so that we don't 904 * trample ongoing ->detect() and whatnot. 905 */ 906 mutex_lock(&dev->mode_config.mutex); 907 drm_modeset_acquire_init(ctx, 0); 908 while (1) { 909 ret = drm_modeset_lock_all_ctx(dev, ctx); 910 if (ret != -EDEADLK) 911 break; 912 913 drm_modeset_backoff(ctx); 914 } 915 /* 916 * Disabling the crtcs gracefully seems nicer. Also the 917 * g33 docs say we should at least disable all the planes. 918 */ 919 state = drm_atomic_helper_duplicate_state(dev, ctx); 920 if (IS_ERR(state)) { 921 ret = PTR_ERR(state); 922 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n", 923 ret); 924 return; 925 } 926 927 ret = drm_atomic_helper_disable_all(dev, ctx); 928 if (ret) { 929 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", 930 ret); 931 drm_atomic_state_put(state); 932 return; 933 } 934 935 dev_priv->modeset_restore_state = state; 936 state->acquire_ctx = ctx; 937 } 938 939 void intel_display_finish_reset(struct drm_i915_private *dev_priv) 940 { 941 struct drm_device *dev = &dev_priv->drm; 942 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; 943 struct drm_atomic_state *state; 944 int ret; 945 946 if (!HAS_DISPLAY(dev_priv)) 947 return; 948 949 /* reset doesn't touch the display */ 950 if (!test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags)) 951 return; 952 953 state = fetch_and_zero(&dev_priv->modeset_restore_state); 954 if (!state) 955 goto unlock; 956 957 /* reset doesn't touch the display */ 958 if (!gpu_reset_clobbers_display(dev_priv)) { 959 /* for testing only restore the display */ 960 ret = __intel_display_resume(dev, state, ctx); 961 if (ret) 962 drm_err(&dev_priv->drm, 963 "Restoring old state failed with %i\n", ret); 964 } else { 965 /* 966 * The display has been reset as well, 967 * so need a full re-initialization. 968 */ 969 intel_pps_unlock_regs_wa(dev_priv); 970 intel_modeset_init_hw(dev_priv); 971 intel_init_clock_gating(dev_priv); 972 intel_hpd_init(dev_priv); 973 974 ret = __intel_display_resume(dev, state, ctx); 975 if (ret) 976 drm_err(&dev_priv->drm, 977 "Restoring old state failed with %i\n", ret); 978 979 intel_hpd_poll_disable(dev_priv); 980 } 981 982 drm_atomic_state_put(state); 983 unlock: 984 drm_modeset_drop_locks(ctx); 985 drm_modeset_acquire_fini(ctx); 986 mutex_unlock(&dev->mode_config.mutex); 987 988 clear_bit_unlock(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags); 989 } 990 991 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) 992 { 993 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 994 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 995 enum pipe pipe = crtc->pipe; 996 u32 tmp; 997 998 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe)); 999 1000 /* 1001 * Display WA #1153: icl 1002 * enable hardware to bypass the alpha math 1003 * and rounding for per-pixel values 00 and 0xff 1004 */ 1005 tmp |= PER_PIXEL_ALPHA_BYPASS_EN; 1006 /* 1007 * Display WA # 1605353570: icl 1008 * Set the pixel rounding bit to 1 for allowing 1009 * passthrough of Frame buffer pixels unmodified 1010 * across pipe 1011 */ 1012 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU; 1013 1014 /* 1015 * Underrun recovery must always be disabled on display 13+. 1016 * DG2 chicken bit meaning is inverted compared to other platforms. 1017 */ 1018 if (IS_DG2(dev_priv)) 1019 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2; 1020 else if (DISPLAY_VER(dev_priv) >= 13) 1021 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP; 1022 1023 /* Wa_14010547955:dg2 */ 1024 if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER)) 1025 tmp |= DG2_RENDER_CCSTAG_4_3_EN; 1026 1027 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp); 1028 } 1029 1030 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) 1031 { 1032 struct drm_crtc *crtc; 1033 bool cleanup_done; 1034 1035 drm_for_each_crtc(crtc, &dev_priv->drm) { 1036 struct drm_crtc_commit *commit; 1037 spin_lock(&crtc->commit_lock); 1038 commit = list_first_entry_or_null(&crtc->commit_list, 1039 struct drm_crtc_commit, commit_entry); 1040 cleanup_done = commit ? 1041 try_wait_for_completion(&commit->cleanup_done) : true; 1042 spin_unlock(&crtc->commit_lock); 1043 1044 if (cleanup_done) 1045 continue; 1046 1047 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc)); 1048 1049 return true; 1050 } 1051 1052 return false; 1053 } 1054 1055 /* 1056 * Finds the encoder associated with the given CRTC. This can only be 1057 * used when we know that the CRTC isn't feeding multiple encoders! 1058 */ 1059 struct intel_encoder * 1060 intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 1061 const struct intel_crtc_state *crtc_state) 1062 { 1063 const struct drm_connector_state *connector_state; 1064 const struct drm_connector *connector; 1065 struct intel_encoder *encoder = NULL; 1066 struct intel_crtc *master_crtc; 1067 int num_encoders = 0; 1068 int i; 1069 1070 master_crtc = intel_master_crtc(crtc_state); 1071 1072 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 1073 if (connector_state->crtc != &master_crtc->base) 1074 continue; 1075 1076 encoder = to_intel_encoder(connector_state->best_encoder); 1077 num_encoders++; 1078 } 1079 1080 drm_WARN(encoder->base.dev, num_encoders != 1, 1081 "%d encoders for pipe %c\n", 1082 num_encoders, pipe_name(master_crtc->pipe)); 1083 1084 return encoder; 1085 } 1086 1087 static void cpt_verify_modeset(struct drm_i915_private *dev_priv, 1088 enum pipe pipe) 1089 { 1090 i915_reg_t dslreg = PIPEDSL(pipe); 1091 u32 temp; 1092 1093 temp = intel_de_read(dev_priv, dslreg); 1094 udelay(500); 1095 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) { 1096 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) 1097 drm_err(&dev_priv->drm, 1098 "mode set failed: pipe %c stuck\n", 1099 pipe_name(pipe)); 1100 } 1101 } 1102 1103 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state) 1104 { 1105 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1106 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1107 const struct drm_rect *dst = &crtc_state->pch_pfit.dst; 1108 enum pipe pipe = crtc->pipe; 1109 int width = drm_rect_width(dst); 1110 int height = drm_rect_height(dst); 1111 int x = dst->x1; 1112 int y = dst->y1; 1113 1114 if (!crtc_state->pch_pfit.enabled) 1115 return; 1116 1117 /* Force use of hard-coded filter coefficients 1118 * as some pre-programmed values are broken, 1119 * e.g. x201. 1120 */ 1121 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) 1122 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 1123 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe)); 1124 else 1125 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 1126 PF_FILTER_MED_3x3); 1127 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), x << 16 | y); 1128 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), width << 16 | height); 1129 } 1130 1131 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc) 1132 { 1133 if (crtc->overlay) 1134 (void) intel_overlay_switch_off(crtc->overlay); 1135 1136 /* Let userspace switch the overlay on again. In most cases userspace 1137 * has to recompute where to put it anyway. 1138 */ 1139 } 1140 1141 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state) 1142 { 1143 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1144 1145 if (!crtc_state->nv12_planes) 1146 return false; 1147 1148 /* WA Display #0827: Gen9:all */ 1149 if (DISPLAY_VER(dev_priv) == 9) 1150 return true; 1151 1152 return false; 1153 } 1154 1155 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state) 1156 { 1157 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1158 1159 /* Wa_2006604312:icl,ehl */ 1160 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11) 1161 return true; 1162 1163 return false; 1164 } 1165 1166 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state) 1167 { 1168 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1169 1170 /* Wa_1604331009:icl,jsl,ehl */ 1171 if (is_hdr_mode(crtc_state) && 1172 crtc_state->active_planes & BIT(PLANE_CURSOR) && 1173 DISPLAY_VER(dev_priv) == 11) 1174 return true; 1175 1176 return false; 1177 } 1178 1179 static void intel_async_flip_vtd_wa(struct drm_i915_private *i915, 1180 enum pipe pipe, bool enable) 1181 { 1182 if (DISPLAY_VER(i915) == 9) { 1183 /* 1184 * "Plane N strech max must be programmed to 11b (x1) 1185 * when Async flips are enabled on that plane." 1186 */ 1187 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 1188 SKL_PLANE1_STRETCH_MAX_MASK, 1189 enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8); 1190 } else { 1191 /* Also needed on HSW/BDW albeit undocumented */ 1192 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 1193 HSW_PRI_STRETCH_MAX_MASK, 1194 enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8); 1195 } 1196 } 1197 1198 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state) 1199 { 1200 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1201 1202 return crtc_state->uapi.async_flip && i915_vtd_active(i915) && 1203 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915)); 1204 } 1205 1206 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state, 1207 const struct intel_crtc_state *new_crtc_state) 1208 { 1209 return (!old_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)) && 1210 new_crtc_state->active_planes; 1211 } 1212 1213 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state, 1214 const struct intel_crtc_state *new_crtc_state) 1215 { 1216 return old_crtc_state->active_planes && 1217 (!new_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)); 1218 } 1219 1220 static void intel_post_plane_update(struct intel_atomic_state *state, 1221 struct intel_crtc *crtc) 1222 { 1223 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1224 const struct intel_crtc_state *old_crtc_state = 1225 intel_atomic_get_old_crtc_state(state, crtc); 1226 const struct intel_crtc_state *new_crtc_state = 1227 intel_atomic_get_new_crtc_state(state, crtc); 1228 enum pipe pipe = crtc->pipe; 1229 1230 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); 1231 1232 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) 1233 intel_update_watermarks(dev_priv); 1234 1235 hsw_ips_post_update(state, crtc); 1236 intel_fbc_post_update(state, crtc); 1237 1238 if (needs_async_flip_vtd_wa(old_crtc_state) && 1239 !needs_async_flip_vtd_wa(new_crtc_state)) 1240 intel_async_flip_vtd_wa(dev_priv, pipe, false); 1241 1242 if (needs_nv12_wa(old_crtc_state) && 1243 !needs_nv12_wa(new_crtc_state)) 1244 skl_wa_827(dev_priv, pipe, false); 1245 1246 if (needs_scalerclk_wa(old_crtc_state) && 1247 !needs_scalerclk_wa(new_crtc_state)) 1248 icl_wa_scalerclkgating(dev_priv, pipe, false); 1249 1250 if (needs_cursorclk_wa(old_crtc_state) && 1251 !needs_cursorclk_wa(new_crtc_state)) 1252 icl_wa_cursorclkgating(dev_priv, pipe, false); 1253 1254 intel_drrs_activate(new_crtc_state); 1255 } 1256 1257 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state, 1258 struct intel_crtc *crtc) 1259 { 1260 const struct intel_crtc_state *crtc_state = 1261 intel_atomic_get_new_crtc_state(state, crtc); 1262 u8 update_planes = crtc_state->update_planes; 1263 const struct intel_plane_state *plane_state; 1264 struct intel_plane *plane; 1265 int i; 1266 1267 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1268 if (plane->pipe == crtc->pipe && 1269 update_planes & BIT(plane->id)) 1270 plane->enable_flip_done(plane); 1271 } 1272 } 1273 1274 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state, 1275 struct intel_crtc *crtc) 1276 { 1277 const struct intel_crtc_state *crtc_state = 1278 intel_atomic_get_new_crtc_state(state, crtc); 1279 u8 update_planes = crtc_state->update_planes; 1280 const struct intel_plane_state *plane_state; 1281 struct intel_plane *plane; 1282 int i; 1283 1284 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1285 if (plane->pipe == crtc->pipe && 1286 update_planes & BIT(plane->id)) 1287 plane->disable_flip_done(plane); 1288 } 1289 } 1290 1291 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state, 1292 struct intel_crtc *crtc) 1293 { 1294 const struct intel_crtc_state *old_crtc_state = 1295 intel_atomic_get_old_crtc_state(state, crtc); 1296 const struct intel_crtc_state *new_crtc_state = 1297 intel_atomic_get_new_crtc_state(state, crtc); 1298 u8 update_planes = new_crtc_state->update_planes; 1299 const struct intel_plane_state *old_plane_state; 1300 struct intel_plane *plane; 1301 bool need_vbl_wait = false; 1302 int i; 1303 1304 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1305 if (plane->need_async_flip_disable_wa && 1306 plane->pipe == crtc->pipe && 1307 update_planes & BIT(plane->id)) { 1308 /* 1309 * Apart from the async flip bit we want to 1310 * preserve the old state for the plane. 1311 */ 1312 plane->async_flip(plane, old_crtc_state, 1313 old_plane_state, false); 1314 need_vbl_wait = true; 1315 } 1316 } 1317 1318 if (need_vbl_wait) 1319 intel_crtc_wait_for_next_vblank(crtc); 1320 } 1321 1322 static void intel_pre_plane_update(struct intel_atomic_state *state, 1323 struct intel_crtc *crtc) 1324 { 1325 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1326 const struct intel_crtc_state *old_crtc_state = 1327 intel_atomic_get_old_crtc_state(state, crtc); 1328 const struct intel_crtc_state *new_crtc_state = 1329 intel_atomic_get_new_crtc_state(state, crtc); 1330 enum pipe pipe = crtc->pipe; 1331 1332 intel_drrs_deactivate(old_crtc_state); 1333 1334 intel_psr_pre_plane_update(state, crtc); 1335 1336 if (hsw_ips_pre_update(state, crtc)) 1337 intel_crtc_wait_for_next_vblank(crtc); 1338 1339 if (intel_fbc_pre_update(state, crtc)) 1340 intel_crtc_wait_for_next_vblank(crtc); 1341 1342 if (!needs_async_flip_vtd_wa(old_crtc_state) && 1343 needs_async_flip_vtd_wa(new_crtc_state)) 1344 intel_async_flip_vtd_wa(dev_priv, pipe, true); 1345 1346 /* Display WA 827 */ 1347 if (!needs_nv12_wa(old_crtc_state) && 1348 needs_nv12_wa(new_crtc_state)) 1349 skl_wa_827(dev_priv, pipe, true); 1350 1351 /* Wa_2006604312:icl,ehl */ 1352 if (!needs_scalerclk_wa(old_crtc_state) && 1353 needs_scalerclk_wa(new_crtc_state)) 1354 icl_wa_scalerclkgating(dev_priv, pipe, true); 1355 1356 /* Wa_1604331009:icl,jsl,ehl */ 1357 if (!needs_cursorclk_wa(old_crtc_state) && 1358 needs_cursorclk_wa(new_crtc_state)) 1359 icl_wa_cursorclkgating(dev_priv, pipe, true); 1360 1361 /* 1362 * Vblank time updates from the shadow to live plane control register 1363 * are blocked if the memory self-refresh mode is active at that 1364 * moment. So to make sure the plane gets truly disabled, disable 1365 * first the self-refresh mode. The self-refresh enable bit in turn 1366 * will be checked/applied by the HW only at the next frame start 1367 * event which is after the vblank start event, so we need to have a 1368 * wait-for-vblank between disabling the plane and the pipe. 1369 */ 1370 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active && 1371 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) 1372 intel_crtc_wait_for_next_vblank(crtc); 1373 1374 /* 1375 * IVB workaround: must disable low power watermarks for at least 1376 * one frame before enabling scaling. LP watermarks can be re-enabled 1377 * when scaling is disabled. 1378 * 1379 * WaCxSRDisabledForSpriteScaling:ivb 1380 */ 1381 if (old_crtc_state->hw.active && 1382 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv)) 1383 intel_crtc_wait_for_next_vblank(crtc); 1384 1385 /* 1386 * If we're doing a modeset we don't need to do any 1387 * pre-vblank watermark programming here. 1388 */ 1389 if (!intel_crtc_needs_modeset(new_crtc_state)) { 1390 /* 1391 * For platforms that support atomic watermarks, program the 1392 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these 1393 * will be the intermediate values that are safe for both pre- and 1394 * post- vblank; when vblank happens, the 'active' values will be set 1395 * to the final 'target' values and we'll do this again to get the 1396 * optimal watermarks. For gen9+ platforms, the values we program here 1397 * will be the final target values which will get automatically latched 1398 * at vblank time; no further programming will be necessary. 1399 * 1400 * If a platform hasn't been transitioned to atomic watermarks yet, 1401 * we'll continue to update watermarks the old way, if flags tell 1402 * us to. 1403 */ 1404 if (!intel_initial_watermarks(state, crtc)) 1405 if (new_crtc_state->update_wm_pre) 1406 intel_update_watermarks(dev_priv); 1407 } 1408 1409 /* 1410 * Gen2 reports pipe underruns whenever all planes are disabled. 1411 * So disable underrun reporting before all the planes get disabled. 1412 * 1413 * We do this after .initial_watermarks() so that we have a 1414 * chance of catching underruns with the intermediate watermarks 1415 * vs. the old plane configuration. 1416 */ 1417 if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state)) 1418 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1419 1420 /* 1421 * WA for platforms where async address update enable bit 1422 * is double buffered and only latched at start of vblank. 1423 */ 1424 if (old_crtc_state->uapi.async_flip && !new_crtc_state->uapi.async_flip) 1425 intel_crtc_async_flip_disable_wa(state, crtc); 1426 } 1427 1428 static void intel_crtc_disable_planes(struct intel_atomic_state *state, 1429 struct intel_crtc *crtc) 1430 { 1431 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1432 const struct intel_crtc_state *new_crtc_state = 1433 intel_atomic_get_new_crtc_state(state, crtc); 1434 unsigned int update_mask = new_crtc_state->update_planes; 1435 const struct intel_plane_state *old_plane_state; 1436 struct intel_plane *plane; 1437 unsigned fb_bits = 0; 1438 int i; 1439 1440 intel_crtc_dpms_overlay_disable(crtc); 1441 1442 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1443 if (crtc->pipe != plane->pipe || 1444 !(update_mask & BIT(plane->id))) 1445 continue; 1446 1447 intel_plane_disable_arm(plane, new_crtc_state); 1448 1449 if (old_plane_state->uapi.visible) 1450 fb_bits |= plane->frontbuffer_bit; 1451 } 1452 1453 intel_frontbuffer_flip(dev_priv, fb_bits); 1454 } 1455 1456 /* 1457 * intel_connector_primary_encoder - get the primary encoder for a connector 1458 * @connector: connector for which to return the encoder 1459 * 1460 * Returns the primary encoder for a connector. There is a 1:1 mapping from 1461 * all connectors to their encoder, except for DP-MST connectors which have 1462 * both a virtual and a primary encoder. These DP-MST primary encoders can be 1463 * pointed to by as many DP-MST connectors as there are pipes. 1464 */ 1465 static struct intel_encoder * 1466 intel_connector_primary_encoder(struct intel_connector *connector) 1467 { 1468 struct intel_encoder *encoder; 1469 1470 if (connector->mst_port) 1471 return &dp_to_dig_port(connector->mst_port)->base; 1472 1473 encoder = intel_attached_encoder(connector); 1474 drm_WARN_ON(connector->base.dev, !encoder); 1475 1476 return encoder; 1477 } 1478 1479 static void intel_encoders_update_prepare(struct intel_atomic_state *state) 1480 { 1481 struct drm_i915_private *i915 = to_i915(state->base.dev); 1482 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 1483 struct intel_crtc *crtc; 1484 struct drm_connector_state *new_conn_state; 1485 struct drm_connector *connector; 1486 int i; 1487 1488 /* 1489 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits. 1490 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook. 1491 */ 1492 if (i915->dpll.mgr) { 1493 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1494 if (intel_crtc_needs_modeset(new_crtc_state)) 1495 continue; 1496 1497 new_crtc_state->shared_dpll = old_crtc_state->shared_dpll; 1498 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state; 1499 } 1500 } 1501 1502 if (!state->modeset) 1503 return; 1504 1505 for_each_new_connector_in_state(&state->base, connector, new_conn_state, 1506 i) { 1507 struct intel_connector *intel_connector; 1508 struct intel_encoder *encoder; 1509 struct intel_crtc *crtc; 1510 1511 if (!intel_connector_needs_modeset(state, connector)) 1512 continue; 1513 1514 intel_connector = to_intel_connector(connector); 1515 encoder = intel_connector_primary_encoder(intel_connector); 1516 if (!encoder->update_prepare) 1517 continue; 1518 1519 crtc = new_conn_state->crtc ? 1520 to_intel_crtc(new_conn_state->crtc) : NULL; 1521 encoder->update_prepare(state, encoder, crtc); 1522 } 1523 } 1524 1525 static void intel_encoders_update_complete(struct intel_atomic_state *state) 1526 { 1527 struct drm_connector_state *new_conn_state; 1528 struct drm_connector *connector; 1529 int i; 1530 1531 if (!state->modeset) 1532 return; 1533 1534 for_each_new_connector_in_state(&state->base, connector, new_conn_state, 1535 i) { 1536 struct intel_connector *intel_connector; 1537 struct intel_encoder *encoder; 1538 struct intel_crtc *crtc; 1539 1540 if (!intel_connector_needs_modeset(state, connector)) 1541 continue; 1542 1543 intel_connector = to_intel_connector(connector); 1544 encoder = intel_connector_primary_encoder(intel_connector); 1545 if (!encoder->update_complete) 1546 continue; 1547 1548 crtc = new_conn_state->crtc ? 1549 to_intel_crtc(new_conn_state->crtc) : NULL; 1550 encoder->update_complete(state, encoder, crtc); 1551 } 1552 } 1553 1554 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state, 1555 struct intel_crtc *crtc) 1556 { 1557 const struct intel_crtc_state *crtc_state = 1558 intel_atomic_get_new_crtc_state(state, crtc); 1559 const struct drm_connector_state *conn_state; 1560 struct drm_connector *conn; 1561 int i; 1562 1563 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1564 struct intel_encoder *encoder = 1565 to_intel_encoder(conn_state->best_encoder); 1566 1567 if (conn_state->crtc != &crtc->base) 1568 continue; 1569 1570 if (encoder->pre_pll_enable) 1571 encoder->pre_pll_enable(state, encoder, 1572 crtc_state, conn_state); 1573 } 1574 } 1575 1576 static void intel_encoders_pre_enable(struct intel_atomic_state *state, 1577 struct intel_crtc *crtc) 1578 { 1579 const struct intel_crtc_state *crtc_state = 1580 intel_atomic_get_new_crtc_state(state, crtc); 1581 const struct drm_connector_state *conn_state; 1582 struct drm_connector *conn; 1583 int i; 1584 1585 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1586 struct intel_encoder *encoder = 1587 to_intel_encoder(conn_state->best_encoder); 1588 1589 if (conn_state->crtc != &crtc->base) 1590 continue; 1591 1592 if (encoder->pre_enable) 1593 encoder->pre_enable(state, encoder, 1594 crtc_state, conn_state); 1595 } 1596 } 1597 1598 static void intel_encoders_enable(struct intel_atomic_state *state, 1599 struct intel_crtc *crtc) 1600 { 1601 const struct intel_crtc_state *crtc_state = 1602 intel_atomic_get_new_crtc_state(state, crtc); 1603 const struct drm_connector_state *conn_state; 1604 struct drm_connector *conn; 1605 int i; 1606 1607 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1608 struct intel_encoder *encoder = 1609 to_intel_encoder(conn_state->best_encoder); 1610 1611 if (conn_state->crtc != &crtc->base) 1612 continue; 1613 1614 if (encoder->enable) 1615 encoder->enable(state, encoder, 1616 crtc_state, conn_state); 1617 intel_opregion_notify_encoder(encoder, true); 1618 } 1619 } 1620 1621 static void intel_encoders_disable(struct intel_atomic_state *state, 1622 struct intel_crtc *crtc) 1623 { 1624 const struct intel_crtc_state *old_crtc_state = 1625 intel_atomic_get_old_crtc_state(state, crtc); 1626 const struct drm_connector_state *old_conn_state; 1627 struct drm_connector *conn; 1628 int i; 1629 1630 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1631 struct intel_encoder *encoder = 1632 to_intel_encoder(old_conn_state->best_encoder); 1633 1634 if (old_conn_state->crtc != &crtc->base) 1635 continue; 1636 1637 intel_opregion_notify_encoder(encoder, false); 1638 if (encoder->disable) 1639 encoder->disable(state, encoder, 1640 old_crtc_state, old_conn_state); 1641 } 1642 } 1643 1644 static void intel_encoders_post_disable(struct intel_atomic_state *state, 1645 struct intel_crtc *crtc) 1646 { 1647 const struct intel_crtc_state *old_crtc_state = 1648 intel_atomic_get_old_crtc_state(state, crtc); 1649 const struct drm_connector_state *old_conn_state; 1650 struct drm_connector *conn; 1651 int i; 1652 1653 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1654 struct intel_encoder *encoder = 1655 to_intel_encoder(old_conn_state->best_encoder); 1656 1657 if (old_conn_state->crtc != &crtc->base) 1658 continue; 1659 1660 if (encoder->post_disable) 1661 encoder->post_disable(state, encoder, 1662 old_crtc_state, old_conn_state); 1663 } 1664 } 1665 1666 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state, 1667 struct intel_crtc *crtc) 1668 { 1669 const struct intel_crtc_state *old_crtc_state = 1670 intel_atomic_get_old_crtc_state(state, crtc); 1671 const struct drm_connector_state *old_conn_state; 1672 struct drm_connector *conn; 1673 int i; 1674 1675 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1676 struct intel_encoder *encoder = 1677 to_intel_encoder(old_conn_state->best_encoder); 1678 1679 if (old_conn_state->crtc != &crtc->base) 1680 continue; 1681 1682 if (encoder->post_pll_disable) 1683 encoder->post_pll_disable(state, encoder, 1684 old_crtc_state, old_conn_state); 1685 } 1686 } 1687 1688 static void intel_encoders_update_pipe(struct intel_atomic_state *state, 1689 struct intel_crtc *crtc) 1690 { 1691 const struct intel_crtc_state *crtc_state = 1692 intel_atomic_get_new_crtc_state(state, crtc); 1693 const struct drm_connector_state *conn_state; 1694 struct drm_connector *conn; 1695 int i; 1696 1697 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1698 struct intel_encoder *encoder = 1699 to_intel_encoder(conn_state->best_encoder); 1700 1701 if (conn_state->crtc != &crtc->base) 1702 continue; 1703 1704 if (encoder->update_pipe) 1705 encoder->update_pipe(state, encoder, 1706 crtc_state, conn_state); 1707 } 1708 } 1709 1710 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state) 1711 { 1712 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1713 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 1714 1715 plane->disable_arm(plane, crtc_state); 1716 } 1717 1718 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1719 { 1720 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1721 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1722 1723 if (crtc_state->has_pch_encoder) { 1724 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1725 &crtc_state->fdi_m_n); 1726 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1727 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1728 &crtc_state->dp_m_n); 1729 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1730 &crtc_state->dp_m2_n2); 1731 } 1732 1733 intel_set_transcoder_timings(crtc_state); 1734 1735 ilk_set_pipeconf(crtc_state); 1736 } 1737 1738 static void ilk_crtc_enable(struct intel_atomic_state *state, 1739 struct intel_crtc *crtc) 1740 { 1741 const struct intel_crtc_state *new_crtc_state = 1742 intel_atomic_get_new_crtc_state(state, crtc); 1743 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1744 enum pipe pipe = crtc->pipe; 1745 1746 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1747 return; 1748 1749 /* 1750 * Sometimes spurious CPU pipe underruns happen during FDI 1751 * training, at least with VGA+HDMI cloning. Suppress them. 1752 * 1753 * On ILK we get an occasional spurious CPU pipe underruns 1754 * between eDP port A enable and vdd enable. Also PCH port 1755 * enable seems to result in the occasional CPU pipe underrun. 1756 * 1757 * Spurious PCH underruns also occur during PCH enabling. 1758 */ 1759 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1760 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 1761 1762 ilk_configure_cpu_transcoder(new_crtc_state); 1763 1764 intel_set_pipe_src_size(new_crtc_state); 1765 1766 crtc->active = true; 1767 1768 intel_encoders_pre_enable(state, crtc); 1769 1770 if (new_crtc_state->has_pch_encoder) { 1771 ilk_pch_pre_enable(state, crtc); 1772 } else { 1773 assert_fdi_tx_disabled(dev_priv, pipe); 1774 assert_fdi_rx_disabled(dev_priv, pipe); 1775 } 1776 1777 ilk_pfit_enable(new_crtc_state); 1778 1779 /* 1780 * On ILK+ LUT must be loaded before the pipe is running but with 1781 * clocks enabled 1782 */ 1783 intel_color_load_luts(new_crtc_state); 1784 intel_color_commit_noarm(new_crtc_state); 1785 intel_color_commit_arm(new_crtc_state); 1786 /* update DSPCNTR to configure gamma for pipe bottom color */ 1787 intel_disable_primary_plane(new_crtc_state); 1788 1789 intel_initial_watermarks(state, crtc); 1790 intel_enable_transcoder(new_crtc_state); 1791 1792 if (new_crtc_state->has_pch_encoder) 1793 ilk_pch_enable(state, crtc); 1794 1795 intel_crtc_vblank_on(new_crtc_state); 1796 1797 intel_encoders_enable(state, crtc); 1798 1799 if (HAS_PCH_CPT(dev_priv)) 1800 cpt_verify_modeset(dev_priv, pipe); 1801 1802 /* 1803 * Must wait for vblank to avoid spurious PCH FIFO underruns. 1804 * And a second vblank wait is needed at least on ILK with 1805 * some interlaced HDMI modes. Let's do the double wait always 1806 * in case there are more corner cases we don't know about. 1807 */ 1808 if (new_crtc_state->has_pch_encoder) { 1809 intel_crtc_wait_for_next_vblank(crtc); 1810 intel_crtc_wait_for_next_vblank(crtc); 1811 } 1812 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1813 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 1814 } 1815 1816 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, 1817 enum pipe pipe, bool apply) 1818 { 1819 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)); 1820 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS; 1821 1822 if (apply) 1823 val |= mask; 1824 else 1825 val &= ~mask; 1826 1827 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val); 1828 } 1829 1830 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state) 1831 { 1832 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1833 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1834 1835 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe), 1836 HSW_LINETIME(crtc_state->linetime) | 1837 HSW_IPS_LINETIME(crtc_state->ips_linetime)); 1838 } 1839 1840 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) 1841 { 1842 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1843 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1844 i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder); 1845 u32 val; 1846 1847 val = intel_de_read(dev_priv, reg); 1848 val &= ~HSW_FRAME_START_DELAY_MASK; 1849 val |= HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 1850 intel_de_write(dev_priv, reg, val); 1851 } 1852 1853 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state, 1854 const struct intel_crtc_state *crtc_state) 1855 { 1856 struct intel_crtc *master_crtc = intel_master_crtc(crtc_state); 1857 1858 /* 1859 * Enable sequence steps 1-7 on bigjoiner master 1860 */ 1861 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1862 intel_encoders_pre_pll_enable(state, master_crtc); 1863 1864 if (crtc_state->shared_dpll) 1865 intel_enable_shared_dpll(crtc_state); 1866 1867 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1868 intel_encoders_pre_enable(state, master_crtc); 1869 } 1870 1871 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1872 { 1873 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1874 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1875 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1876 1877 if (crtc_state->has_pch_encoder) { 1878 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1879 &crtc_state->fdi_m_n); 1880 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1881 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1882 &crtc_state->dp_m_n); 1883 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1884 &crtc_state->dp_m2_n2); 1885 } 1886 1887 intel_set_transcoder_timings(crtc_state); 1888 1889 if (cpu_transcoder != TRANSCODER_EDP) 1890 intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder), 1891 crtc_state->pixel_multiplier - 1); 1892 1893 hsw_set_frame_start_delay(crtc_state); 1894 1895 hsw_set_transconf(crtc_state); 1896 } 1897 1898 static void hsw_crtc_enable(struct intel_atomic_state *state, 1899 struct intel_crtc *crtc) 1900 { 1901 const struct intel_crtc_state *new_crtc_state = 1902 intel_atomic_get_new_crtc_state(state, crtc); 1903 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1904 enum pipe pipe = crtc->pipe, hsw_workaround_pipe; 1905 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 1906 bool psl_clkgate_wa; 1907 1908 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1909 return; 1910 1911 if (!new_crtc_state->bigjoiner_pipes) { 1912 intel_encoders_pre_pll_enable(state, crtc); 1913 1914 if (new_crtc_state->shared_dpll) 1915 intel_enable_shared_dpll(new_crtc_state); 1916 1917 intel_encoders_pre_enable(state, crtc); 1918 } else { 1919 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state); 1920 } 1921 1922 intel_dsc_enable(new_crtc_state); 1923 1924 if (DISPLAY_VER(dev_priv) >= 13) 1925 intel_uncompressed_joiner_enable(new_crtc_state); 1926 1927 intel_set_pipe_src_size(new_crtc_state); 1928 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 1929 bdw_set_pipemisc(new_crtc_state); 1930 1931 if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) && 1932 !transcoder_is_dsi(cpu_transcoder)) 1933 hsw_configure_cpu_transcoder(new_crtc_state); 1934 1935 crtc->active = true; 1936 1937 /* Display WA #1180: WaDisableScalarClockGating: glk */ 1938 psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 && 1939 new_crtc_state->pch_pfit.enabled; 1940 if (psl_clkgate_wa) 1941 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true); 1942 1943 if (DISPLAY_VER(dev_priv) >= 9) 1944 skl_pfit_enable(new_crtc_state); 1945 else 1946 ilk_pfit_enable(new_crtc_state); 1947 1948 /* 1949 * On ILK+ LUT must be loaded before the pipe is running but with 1950 * clocks enabled 1951 */ 1952 intel_color_load_luts(new_crtc_state); 1953 intel_color_commit_noarm(new_crtc_state); 1954 intel_color_commit_arm(new_crtc_state); 1955 /* update DSPCNTR to configure gamma/csc for pipe bottom color */ 1956 if (DISPLAY_VER(dev_priv) < 9) 1957 intel_disable_primary_plane(new_crtc_state); 1958 1959 hsw_set_linetime_wm(new_crtc_state); 1960 1961 if (DISPLAY_VER(dev_priv) >= 11) 1962 icl_set_pipe_chicken(new_crtc_state); 1963 1964 intel_initial_watermarks(state, crtc); 1965 1966 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 1967 intel_crtc_vblank_on(new_crtc_state); 1968 1969 intel_encoders_enable(state, crtc); 1970 1971 if (psl_clkgate_wa) { 1972 intel_crtc_wait_for_next_vblank(crtc); 1973 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false); 1974 } 1975 1976 /* If we change the relative order between pipe/planes enabling, we need 1977 * to change the workaround. */ 1978 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe; 1979 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { 1980 struct intel_crtc *wa_crtc; 1981 1982 wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe); 1983 1984 intel_crtc_wait_for_next_vblank(wa_crtc); 1985 intel_crtc_wait_for_next_vblank(wa_crtc); 1986 } 1987 } 1988 1989 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state) 1990 { 1991 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1992 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1993 enum pipe pipe = crtc->pipe; 1994 1995 /* To avoid upsetting the power well on haswell only disable the pfit if 1996 * it's in use. The hw state code will make sure we get this right. */ 1997 if (!old_crtc_state->pch_pfit.enabled) 1998 return; 1999 2000 intel_de_write_fw(dev_priv, PF_CTL(pipe), 0); 2001 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0); 2002 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0); 2003 } 2004 2005 static void ilk_crtc_disable(struct intel_atomic_state *state, 2006 struct intel_crtc *crtc) 2007 { 2008 const struct intel_crtc_state *old_crtc_state = 2009 intel_atomic_get_old_crtc_state(state, crtc); 2010 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2011 enum pipe pipe = crtc->pipe; 2012 2013 /* 2014 * Sometimes spurious CPU pipe underruns happen when the 2015 * pipe is already disabled, but FDI RX/TX is still enabled. 2016 * Happens at least with VGA+HDMI cloning. Suppress them. 2017 */ 2018 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 2019 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 2020 2021 intel_encoders_disable(state, crtc); 2022 2023 intel_crtc_vblank_off(old_crtc_state); 2024 2025 intel_disable_transcoder(old_crtc_state); 2026 2027 ilk_pfit_disable(old_crtc_state); 2028 2029 if (old_crtc_state->has_pch_encoder) 2030 ilk_pch_disable(state, crtc); 2031 2032 intel_encoders_post_disable(state, crtc); 2033 2034 if (old_crtc_state->has_pch_encoder) 2035 ilk_pch_post_disable(state, crtc); 2036 2037 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2038 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 2039 } 2040 2041 static void hsw_crtc_disable(struct intel_atomic_state *state, 2042 struct intel_crtc *crtc) 2043 { 2044 const struct intel_crtc_state *old_crtc_state = 2045 intel_atomic_get_old_crtc_state(state, crtc); 2046 2047 /* 2048 * FIXME collapse everything to one hook. 2049 * Need care with mst->ddi interactions. 2050 */ 2051 if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) { 2052 intel_encoders_disable(state, crtc); 2053 intel_encoders_post_disable(state, crtc); 2054 } 2055 } 2056 2057 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) 2058 { 2059 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2060 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2061 2062 if (!crtc_state->gmch_pfit.control) 2063 return; 2064 2065 /* 2066 * The panel fitter should only be adjusted whilst the pipe is disabled, 2067 * according to register description and PRM. 2068 */ 2069 drm_WARN_ON(&dev_priv->drm, 2070 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE); 2071 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 2072 2073 intel_de_write(dev_priv, PFIT_PGM_RATIOS, 2074 crtc_state->gmch_pfit.pgm_ratios); 2075 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control); 2076 2077 /* Border color in case we don't scale up to the full screen. Black by 2078 * default, change to something else for debugging. */ 2079 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); 2080 } 2081 2082 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) 2083 { 2084 if (phy == PHY_NONE) 2085 return false; 2086 else if (IS_DG2(dev_priv)) 2087 /* 2088 * DG2 outputs labelled as "combo PHY" in the bspec use 2089 * SNPS PHYs with completely different programming, 2090 * hence we always return false here. 2091 */ 2092 return false; 2093 else if (IS_ALDERLAKE_S(dev_priv)) 2094 return phy <= PHY_E; 2095 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) 2096 return phy <= PHY_D; 2097 else if (IS_JSL_EHL(dev_priv)) 2098 return phy <= PHY_C; 2099 else if (DISPLAY_VER(dev_priv) >= 11) 2100 return phy <= PHY_B; 2101 else 2102 return false; 2103 } 2104 2105 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) 2106 { 2107 if (IS_DG2(dev_priv)) 2108 /* DG2's "TC1" output uses a SNPS PHY */ 2109 return false; 2110 else if (IS_ALDERLAKE_P(dev_priv)) 2111 return phy >= PHY_F && phy <= PHY_I; 2112 else if (IS_TIGERLAKE(dev_priv)) 2113 return phy >= PHY_D && phy <= PHY_I; 2114 else if (IS_ICELAKE(dev_priv)) 2115 return phy >= PHY_C && phy <= PHY_F; 2116 else 2117 return false; 2118 } 2119 2120 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy) 2121 { 2122 if (phy == PHY_NONE) 2123 return false; 2124 else if (IS_DG2(dev_priv)) 2125 /* 2126 * All four "combo" ports and the TC1 port (PHY E) use 2127 * Synopsis PHYs. 2128 */ 2129 return phy <= PHY_E; 2130 2131 return false; 2132 } 2133 2134 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) 2135 { 2136 if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD) 2137 return PHY_D + port - PORT_D_XELPD; 2138 else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1) 2139 return PHY_F + port - PORT_TC1; 2140 else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1) 2141 return PHY_B + port - PORT_TC1; 2142 else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1) 2143 return PHY_C + port - PORT_TC1; 2144 else if (IS_JSL_EHL(i915) && port == PORT_D) 2145 return PHY_A; 2146 2147 return PHY_A + port - PORT_A; 2148 } 2149 2150 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) 2151 { 2152 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port))) 2153 return TC_PORT_NONE; 2154 2155 if (DISPLAY_VER(dev_priv) >= 12) 2156 return TC_PORT_1 + port - PORT_TC1; 2157 else 2158 return TC_PORT_1 + port - PORT_C; 2159 } 2160 2161 enum intel_display_power_domain 2162 intel_aux_power_domain(struct intel_digital_port *dig_port) 2163 { 2164 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 2165 2166 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 2167 return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch); 2168 2169 return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch); 2170 } 2171 2172 static void get_crtc_power_domains(struct intel_crtc_state *crtc_state, 2173 struct intel_power_domain_mask *mask) 2174 { 2175 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2176 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2177 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2178 struct drm_encoder *encoder; 2179 enum pipe pipe = crtc->pipe; 2180 2181 bitmap_zero(mask->bits, POWER_DOMAIN_NUM); 2182 2183 if (!crtc_state->hw.active) 2184 return; 2185 2186 set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits); 2187 set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits); 2188 if (crtc_state->pch_pfit.enabled || 2189 crtc_state->pch_pfit.force_thru) 2190 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits); 2191 2192 drm_for_each_encoder_mask(encoder, &dev_priv->drm, 2193 crtc_state->uapi.encoder_mask) { 2194 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2195 2196 set_bit(intel_encoder->power_domain, mask->bits); 2197 } 2198 2199 if (HAS_DDI(dev_priv) && crtc_state->has_audio) 2200 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits); 2201 2202 if (crtc_state->shared_dpll) 2203 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits); 2204 2205 if (crtc_state->dsc.compression_enable) 2206 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits); 2207 } 2208 2209 static void 2210 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, 2211 struct intel_power_domain_mask *old_domains) 2212 { 2213 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2214 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2215 enum intel_display_power_domain domain; 2216 struct intel_power_domain_mask domains, new_domains; 2217 2218 get_crtc_power_domains(crtc_state, &domains); 2219 2220 bitmap_andnot(new_domains.bits, 2221 domains.bits, 2222 crtc->enabled_power_domains.mask.bits, 2223 POWER_DOMAIN_NUM); 2224 bitmap_andnot(old_domains->bits, 2225 crtc->enabled_power_domains.mask.bits, 2226 domains.bits, 2227 POWER_DOMAIN_NUM); 2228 2229 for_each_power_domain(domain, &new_domains) 2230 intel_display_power_get_in_set(dev_priv, 2231 &crtc->enabled_power_domains, 2232 domain); 2233 } 2234 2235 static void modeset_put_crtc_power_domains(struct intel_crtc *crtc, 2236 struct intel_power_domain_mask *domains) 2237 { 2238 intel_display_power_put_mask_in_set(to_i915(crtc->base.dev), 2239 &crtc->enabled_power_domains, 2240 domains); 2241 } 2242 2243 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 2244 { 2245 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2246 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2247 2248 if (intel_crtc_has_dp_encoder(crtc_state)) { 2249 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 2250 &crtc_state->dp_m_n); 2251 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 2252 &crtc_state->dp_m2_n2); 2253 } 2254 2255 intel_set_transcoder_timings(crtc_state); 2256 2257 i9xx_set_pipeconf(crtc_state); 2258 } 2259 2260 static void valleyview_crtc_enable(struct intel_atomic_state *state, 2261 struct intel_crtc *crtc) 2262 { 2263 const struct intel_crtc_state *new_crtc_state = 2264 intel_atomic_get_new_crtc_state(state, crtc); 2265 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2266 enum pipe pipe = crtc->pipe; 2267 2268 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 2269 return; 2270 2271 i9xx_configure_cpu_transcoder(new_crtc_state); 2272 2273 intel_set_pipe_src_size(new_crtc_state); 2274 2275 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 2276 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY); 2277 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0); 2278 } 2279 2280 crtc->active = true; 2281 2282 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2283 2284 intel_encoders_pre_pll_enable(state, crtc); 2285 2286 if (IS_CHERRYVIEW(dev_priv)) 2287 chv_enable_pll(new_crtc_state); 2288 else 2289 vlv_enable_pll(new_crtc_state); 2290 2291 intel_encoders_pre_enable(state, crtc); 2292 2293 i9xx_pfit_enable(new_crtc_state); 2294 2295 intel_color_load_luts(new_crtc_state); 2296 intel_color_commit_noarm(new_crtc_state); 2297 intel_color_commit_arm(new_crtc_state); 2298 /* update DSPCNTR to configure gamma for pipe bottom color */ 2299 intel_disable_primary_plane(new_crtc_state); 2300 2301 intel_initial_watermarks(state, crtc); 2302 intel_enable_transcoder(new_crtc_state); 2303 2304 intel_crtc_vblank_on(new_crtc_state); 2305 2306 intel_encoders_enable(state, crtc); 2307 } 2308 2309 static void i9xx_crtc_enable(struct intel_atomic_state *state, 2310 struct intel_crtc *crtc) 2311 { 2312 const struct intel_crtc_state *new_crtc_state = 2313 intel_atomic_get_new_crtc_state(state, crtc); 2314 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2315 enum pipe pipe = crtc->pipe; 2316 2317 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 2318 return; 2319 2320 i9xx_configure_cpu_transcoder(new_crtc_state); 2321 2322 intel_set_pipe_src_size(new_crtc_state); 2323 2324 crtc->active = true; 2325 2326 if (DISPLAY_VER(dev_priv) != 2) 2327 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2328 2329 intel_encoders_pre_enable(state, crtc); 2330 2331 i9xx_enable_pll(new_crtc_state); 2332 2333 i9xx_pfit_enable(new_crtc_state); 2334 2335 intel_color_load_luts(new_crtc_state); 2336 intel_color_commit_noarm(new_crtc_state); 2337 intel_color_commit_arm(new_crtc_state); 2338 /* update DSPCNTR to configure gamma for pipe bottom color */ 2339 intel_disable_primary_plane(new_crtc_state); 2340 2341 if (!intel_initial_watermarks(state, crtc)) 2342 intel_update_watermarks(dev_priv); 2343 intel_enable_transcoder(new_crtc_state); 2344 2345 intel_crtc_vblank_on(new_crtc_state); 2346 2347 intel_encoders_enable(state, crtc); 2348 2349 /* prevents spurious underruns */ 2350 if (DISPLAY_VER(dev_priv) == 2) 2351 intel_crtc_wait_for_next_vblank(crtc); 2352 } 2353 2354 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) 2355 { 2356 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 2357 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2358 2359 if (!old_crtc_state->gmch_pfit.control) 2360 return; 2361 2362 assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder); 2363 2364 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n", 2365 intel_de_read(dev_priv, PFIT_CONTROL)); 2366 intel_de_write(dev_priv, PFIT_CONTROL, 0); 2367 } 2368 2369 static void i9xx_crtc_disable(struct intel_atomic_state *state, 2370 struct intel_crtc *crtc) 2371 { 2372 struct intel_crtc_state *old_crtc_state = 2373 intel_atomic_get_old_crtc_state(state, crtc); 2374 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2375 enum pipe pipe = crtc->pipe; 2376 2377 /* 2378 * On gen2 planes are double buffered but the pipe isn't, so we must 2379 * wait for planes to fully turn off before disabling the pipe. 2380 */ 2381 if (DISPLAY_VER(dev_priv) == 2) 2382 intel_crtc_wait_for_next_vblank(crtc); 2383 2384 intel_encoders_disable(state, crtc); 2385 2386 intel_crtc_vblank_off(old_crtc_state); 2387 2388 intel_disable_transcoder(old_crtc_state); 2389 2390 i9xx_pfit_disable(old_crtc_state); 2391 2392 intel_encoders_post_disable(state, crtc); 2393 2394 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) { 2395 if (IS_CHERRYVIEW(dev_priv)) 2396 chv_disable_pll(dev_priv, pipe); 2397 else if (IS_VALLEYVIEW(dev_priv)) 2398 vlv_disable_pll(dev_priv, pipe); 2399 else 2400 i9xx_disable_pll(old_crtc_state); 2401 } 2402 2403 intel_encoders_post_pll_disable(state, crtc); 2404 2405 if (DISPLAY_VER(dev_priv) != 2) 2406 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 2407 2408 if (!dev_priv->wm_disp->initial_watermarks) 2409 intel_update_watermarks(dev_priv); 2410 2411 /* clock the pipe down to 640x480@60 to potentially save power */ 2412 if (IS_I830(dev_priv)) 2413 i830_enable_pipe(dev_priv, pipe); 2414 } 2415 2416 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, 2417 struct drm_modeset_acquire_ctx *ctx) 2418 { 2419 struct intel_encoder *encoder; 2420 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2421 struct intel_bw_state *bw_state = 2422 to_intel_bw_state(dev_priv->bw_obj.state); 2423 struct intel_cdclk_state *cdclk_state = 2424 to_intel_cdclk_state(dev_priv->cdclk.obj.state); 2425 struct intel_dbuf_state *dbuf_state = 2426 to_intel_dbuf_state(dev_priv->dbuf.obj.state); 2427 struct intel_crtc_state *crtc_state = 2428 to_intel_crtc_state(crtc->base.state); 2429 struct intel_plane *plane; 2430 struct drm_atomic_state *state; 2431 struct intel_crtc_state *temp_crtc_state; 2432 enum pipe pipe = crtc->pipe; 2433 int ret; 2434 2435 if (!crtc_state->hw.active) 2436 return; 2437 2438 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 2439 const struct intel_plane_state *plane_state = 2440 to_intel_plane_state(plane->base.state); 2441 2442 if (plane_state->uapi.visible) 2443 intel_plane_disable_noatomic(crtc, plane); 2444 } 2445 2446 state = drm_atomic_state_alloc(&dev_priv->drm); 2447 if (!state) { 2448 drm_dbg_kms(&dev_priv->drm, 2449 "failed to disable [CRTC:%d:%s], out of memory", 2450 crtc->base.base.id, crtc->base.name); 2451 return; 2452 } 2453 2454 state->acquire_ctx = ctx; 2455 2456 /* Everything's already locked, -EDEADLK can't happen. */ 2457 temp_crtc_state = intel_atomic_get_crtc_state(state, crtc); 2458 ret = drm_atomic_add_affected_connectors(state, &crtc->base); 2459 2460 drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret); 2461 2462 dev_priv->display->crtc_disable(to_intel_atomic_state(state), crtc); 2463 2464 drm_atomic_state_put(state); 2465 2466 drm_dbg_kms(&dev_priv->drm, 2467 "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", 2468 crtc->base.base.id, crtc->base.name); 2469 2470 crtc->active = false; 2471 crtc->base.enabled = false; 2472 2473 drm_WARN_ON(&dev_priv->drm, 2474 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0); 2475 crtc_state->uapi.active = false; 2476 crtc_state->uapi.connector_mask = 0; 2477 crtc_state->uapi.encoder_mask = 0; 2478 intel_crtc_free_hw_state(crtc_state); 2479 memset(&crtc_state->hw, 0, sizeof(crtc_state->hw)); 2480 2481 for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder) 2482 encoder->base.crtc = NULL; 2483 2484 intel_fbc_disable(crtc); 2485 intel_update_watermarks(dev_priv); 2486 intel_disable_shared_dpll(crtc_state); 2487 2488 intel_display_power_put_all_in_set(dev_priv, &crtc->enabled_power_domains); 2489 2490 cdclk_state->min_cdclk[pipe] = 0; 2491 cdclk_state->min_voltage_level[pipe] = 0; 2492 cdclk_state->active_pipes &= ~BIT(pipe); 2493 2494 dbuf_state->active_pipes &= ~BIT(pipe); 2495 2496 bw_state->data_rate[pipe] = 0; 2497 bw_state->num_active_planes[pipe] = 0; 2498 } 2499 2500 /* 2501 * turn all crtc's off, but do not adjust state 2502 * This has to be paired with a call to intel_modeset_setup_hw_state. 2503 */ 2504 int intel_display_suspend(struct drm_device *dev) 2505 { 2506 struct drm_i915_private *dev_priv = to_i915(dev); 2507 struct drm_atomic_state *state; 2508 int ret; 2509 2510 if (!HAS_DISPLAY(dev_priv)) 2511 return 0; 2512 2513 state = drm_atomic_helper_suspend(dev); 2514 ret = PTR_ERR_OR_ZERO(state); 2515 if (ret) 2516 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", 2517 ret); 2518 else 2519 dev_priv->modeset_restore_state = state; 2520 return ret; 2521 } 2522 2523 void intel_encoder_destroy(struct drm_encoder *encoder) 2524 { 2525 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2526 2527 drm_encoder_cleanup(encoder); 2528 kfree(intel_encoder); 2529 } 2530 2531 /* Cross check the actual hw state with our own modeset state tracking (and it's 2532 * internal consistency). */ 2533 static void intel_connector_verify_state(struct intel_crtc_state *crtc_state, 2534 struct drm_connector_state *conn_state) 2535 { 2536 struct intel_connector *connector = to_intel_connector(conn_state->connector); 2537 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2538 2539 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", 2540 connector->base.base.id, connector->base.name); 2541 2542 if (connector->get_hw_state(connector)) { 2543 struct intel_encoder *encoder = intel_attached_encoder(connector); 2544 2545 I915_STATE_WARN(!crtc_state, 2546 "connector enabled without attached crtc\n"); 2547 2548 if (!crtc_state) 2549 return; 2550 2551 I915_STATE_WARN(!crtc_state->hw.active, 2552 "connector is active, but attached crtc isn't\n"); 2553 2554 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) 2555 return; 2556 2557 I915_STATE_WARN(conn_state->best_encoder != &encoder->base, 2558 "atomic encoder doesn't match attached encoder\n"); 2559 2560 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, 2561 "attached encoder crtc differs from connector crtc\n"); 2562 } else { 2563 I915_STATE_WARN(crtc_state && crtc_state->hw.active, 2564 "attached crtc is active, but connector isn't\n"); 2565 I915_STATE_WARN(!crtc_state && conn_state->best_encoder, 2566 "best encoder set without crtc!\n"); 2567 } 2568 } 2569 2570 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) 2571 { 2572 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2573 2574 /* GDG double wide on either pipe, otherwise pipe A only */ 2575 return DISPLAY_VER(dev_priv) < 4 && 2576 (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); 2577 } 2578 2579 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) 2580 { 2581 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock; 2582 struct drm_rect src; 2583 2584 /* 2585 * We only use IF-ID interlacing. If we ever use 2586 * PF-ID we'll need to adjust the pixel_rate here. 2587 */ 2588 2589 if (!crtc_state->pch_pfit.enabled) 2590 return pixel_rate; 2591 2592 drm_rect_init(&src, 0, 0, 2593 drm_rect_width(&crtc_state->pipe_src) << 16, 2594 drm_rect_height(&crtc_state->pipe_src) << 16); 2595 2596 return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst, 2597 pixel_rate); 2598 } 2599 2600 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode, 2601 const struct drm_display_mode *timings) 2602 { 2603 mode->hdisplay = timings->crtc_hdisplay; 2604 mode->htotal = timings->crtc_htotal; 2605 mode->hsync_start = timings->crtc_hsync_start; 2606 mode->hsync_end = timings->crtc_hsync_end; 2607 2608 mode->vdisplay = timings->crtc_vdisplay; 2609 mode->vtotal = timings->crtc_vtotal; 2610 mode->vsync_start = timings->crtc_vsync_start; 2611 mode->vsync_end = timings->crtc_vsync_end; 2612 2613 mode->flags = timings->flags; 2614 mode->type = DRM_MODE_TYPE_DRIVER; 2615 2616 mode->clock = timings->crtc_clock; 2617 2618 drm_mode_set_name(mode); 2619 } 2620 2621 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) 2622 { 2623 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2624 2625 if (HAS_GMCH(dev_priv)) 2626 /* FIXME calculate proper pipe pixel rate for GMCH pfit */ 2627 crtc_state->pixel_rate = 2628 crtc_state->hw.pipe_mode.crtc_clock; 2629 else 2630 crtc_state->pixel_rate = 2631 ilk_pipe_pixel_rate(crtc_state); 2632 } 2633 2634 static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state *crtc_state, 2635 struct drm_display_mode *mode) 2636 { 2637 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2638 2639 if (num_pipes < 2) 2640 return; 2641 2642 mode->crtc_clock /= num_pipes; 2643 mode->crtc_hdisplay /= num_pipes; 2644 mode->crtc_hblank_start /= num_pipes; 2645 mode->crtc_hblank_end /= num_pipes; 2646 mode->crtc_hsync_start /= num_pipes; 2647 mode->crtc_hsync_end /= num_pipes; 2648 mode->crtc_htotal /= num_pipes; 2649 } 2650 2651 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state, 2652 struct drm_display_mode *mode) 2653 { 2654 int overlap = crtc_state->splitter.pixel_overlap; 2655 int n = crtc_state->splitter.link_count; 2656 2657 if (!crtc_state->splitter.enable) 2658 return; 2659 2660 /* 2661 * eDP MSO uses segment timings from EDID for transcoder 2662 * timings, but full mode for everything else. 2663 * 2664 * h_full = (h_segment - pixel_overlap) * link_count 2665 */ 2666 mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n; 2667 mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n; 2668 mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n; 2669 mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n; 2670 mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n; 2671 mode->crtc_htotal = (mode->crtc_htotal - overlap) * n; 2672 mode->crtc_clock *= n; 2673 } 2674 2675 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state) 2676 { 2677 struct drm_display_mode *mode = &crtc_state->hw.mode; 2678 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2679 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2680 2681 /* 2682 * Start with the adjusted_mode crtc timings, which 2683 * have been filled with the transcoder timings. 2684 */ 2685 drm_mode_copy(pipe_mode, adjusted_mode); 2686 2687 /* Expand MSO per-segment transcoder timings to full */ 2688 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2689 2690 /* 2691 * We want the full numbers in adjusted_mode normal timings, 2692 * adjusted_mode crtc timings are left with the raw transcoder 2693 * timings. 2694 */ 2695 intel_mode_from_crtc_timings(adjusted_mode, pipe_mode); 2696 2697 /* Populate the "user" mode with full numbers */ 2698 drm_mode_copy(mode, pipe_mode); 2699 intel_mode_from_crtc_timings(mode, mode); 2700 mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) * 2701 (intel_bigjoiner_num_pipes(crtc_state) ?: 1); 2702 mode->vdisplay = drm_rect_height(&crtc_state->pipe_src); 2703 2704 /* Derive per-pipe timings in case bigjoiner is used */ 2705 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2706 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2707 2708 intel_crtc_compute_pixel_rate(crtc_state); 2709 } 2710 2711 static void intel_encoder_get_config(struct intel_encoder *encoder, 2712 struct intel_crtc_state *crtc_state) 2713 { 2714 encoder->get_config(encoder, crtc_state); 2715 2716 intel_crtc_readout_derived_state(crtc_state); 2717 } 2718 2719 static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state *crtc_state) 2720 { 2721 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2722 int width, height; 2723 2724 if (num_pipes < 2) 2725 return; 2726 2727 width = drm_rect_width(&crtc_state->pipe_src); 2728 height = drm_rect_height(&crtc_state->pipe_src); 2729 2730 drm_rect_init(&crtc_state->pipe_src, 0, 0, 2731 width / num_pipes, height); 2732 } 2733 2734 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state) 2735 { 2736 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2737 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2738 2739 intel_bigjoiner_compute_pipe_src(crtc_state); 2740 2741 /* 2742 * Pipe horizontal size must be even in: 2743 * - DVO ganged mode 2744 * - LVDS dual channel mode 2745 * - Double wide pipe 2746 */ 2747 if (drm_rect_width(&crtc_state->pipe_src) & 1) { 2748 if (crtc_state->double_wide) { 2749 drm_dbg_kms(&i915->drm, 2750 "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n", 2751 crtc->base.base.id, crtc->base.name); 2752 return -EINVAL; 2753 } 2754 2755 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 2756 intel_is_dual_link_lvds(i915)) { 2757 drm_dbg_kms(&i915->drm, 2758 "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n", 2759 crtc->base.base.id, crtc->base.name); 2760 return -EINVAL; 2761 } 2762 } 2763 2764 return 0; 2765 } 2766 2767 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state) 2768 { 2769 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2770 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2771 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2772 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2773 int clock_limit = i915->max_dotclk_freq; 2774 2775 /* 2776 * Start with the adjusted_mode crtc timings, which 2777 * have been filled with the transcoder timings. 2778 */ 2779 drm_mode_copy(pipe_mode, adjusted_mode); 2780 2781 /* Expand MSO per-segment transcoder timings to full */ 2782 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2783 2784 /* Derive per-pipe timings in case bigjoiner is used */ 2785 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2786 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2787 2788 if (DISPLAY_VER(i915) < 4) { 2789 clock_limit = i915->max_cdclk_freq * 9 / 10; 2790 2791 /* 2792 * Enable double wide mode when the dot clock 2793 * is > 90% of the (display) core speed. 2794 */ 2795 if (intel_crtc_supports_double_wide(crtc) && 2796 pipe_mode->crtc_clock > clock_limit) { 2797 clock_limit = i915->max_dotclk_freq; 2798 crtc_state->double_wide = true; 2799 } 2800 } 2801 2802 if (pipe_mode->crtc_clock > clock_limit) { 2803 drm_dbg_kms(&i915->drm, 2804 "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", 2805 crtc->base.base.id, crtc->base.name, 2806 pipe_mode->crtc_clock, clock_limit, 2807 str_yes_no(crtc_state->double_wide)); 2808 return -EINVAL; 2809 } 2810 2811 return 0; 2812 } 2813 2814 static int intel_crtc_compute_config(struct intel_atomic_state *state, 2815 struct intel_crtc *crtc) 2816 { 2817 struct intel_crtc_state *crtc_state = 2818 intel_atomic_get_new_crtc_state(state, crtc); 2819 int ret; 2820 2821 ret = intel_crtc_compute_pipe_src(crtc_state); 2822 if (ret) 2823 return ret; 2824 2825 ret = intel_crtc_compute_pipe_mode(crtc_state); 2826 if (ret) 2827 return ret; 2828 2829 intel_crtc_compute_pixel_rate(crtc_state); 2830 2831 if (crtc_state->has_pch_encoder) 2832 return ilk_fdi_compute_config(crtc, crtc_state); 2833 2834 return 0; 2835 } 2836 2837 static void 2838 intel_reduce_m_n_ratio(u32 *num, u32 *den) 2839 { 2840 while (*num > DATA_LINK_M_N_MASK || 2841 *den > DATA_LINK_M_N_MASK) { 2842 *num >>= 1; 2843 *den >>= 1; 2844 } 2845 } 2846 2847 static void compute_m_n(unsigned int m, unsigned int n, 2848 u32 *ret_m, u32 *ret_n, 2849 bool constant_n) 2850 { 2851 /* 2852 * Several DP dongles in particular seem to be fussy about 2853 * too large link M/N values. Give N value as 0x8000 that 2854 * should be acceptable by specific devices. 0x8000 is the 2855 * specified fixed N value for asynchronous clock mode, 2856 * which the devices expect also in synchronous clock mode. 2857 */ 2858 if (constant_n) 2859 *ret_n = DP_LINK_CONSTANT_N_VALUE; 2860 else 2861 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); 2862 2863 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n); 2864 intel_reduce_m_n_ratio(ret_m, ret_n); 2865 } 2866 2867 void 2868 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes, 2869 int pixel_clock, int link_clock, 2870 struct intel_link_m_n *m_n, 2871 bool constant_n, bool fec_enable) 2872 { 2873 u32 data_clock = bits_per_pixel * pixel_clock; 2874 2875 if (fec_enable) 2876 data_clock = intel_dp_mode_to_fec_clock(data_clock); 2877 2878 m_n->tu = 64; 2879 compute_m_n(data_clock, 2880 link_clock * nlanes * 8, 2881 &m_n->data_m, &m_n->data_n, 2882 constant_n); 2883 2884 compute_m_n(pixel_clock, link_clock, 2885 &m_n->link_m, &m_n->link_n, 2886 constant_n); 2887 } 2888 2889 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv) 2890 { 2891 /* 2892 * There may be no VBT; and if the BIOS enabled SSC we can 2893 * just keep using it to avoid unnecessary flicker. Whereas if the 2894 * BIOS isn't using it, don't assume it will work even if the VBT 2895 * indicates as much. 2896 */ 2897 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { 2898 bool bios_lvds_use_ssc = intel_de_read(dev_priv, 2899 PCH_DREF_CONTROL) & 2900 DREF_SSC1_ENABLE; 2901 2902 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { 2903 drm_dbg_kms(&dev_priv->drm, 2904 "SSC %s by BIOS, overriding VBT which says %s\n", 2905 str_enabled_disabled(bios_lvds_use_ssc), 2906 str_enabled_disabled(dev_priv->vbt.lvds_use_ssc)); 2907 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; 2908 } 2909 } 2910 } 2911 2912 void intel_zero_m_n(struct intel_link_m_n *m_n) 2913 { 2914 /* corresponds to 0 register value */ 2915 memset(m_n, 0, sizeof(*m_n)); 2916 m_n->tu = 1; 2917 } 2918 2919 void intel_set_m_n(struct drm_i915_private *i915, 2920 const struct intel_link_m_n *m_n, 2921 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 2922 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 2923 { 2924 intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); 2925 intel_de_write(i915, data_n_reg, m_n->data_n); 2926 intel_de_write(i915, link_m_reg, m_n->link_m); 2927 /* 2928 * On BDW+ writing LINK_N arms the double buffered update 2929 * of all the M/N registers, so it must be written last. 2930 */ 2931 intel_de_write(i915, link_n_reg, m_n->link_n); 2932 } 2933 2934 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, 2935 enum transcoder transcoder) 2936 { 2937 if (IS_HASWELL(dev_priv)) 2938 return transcoder == TRANSCODER_EDP; 2939 2940 return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv); 2941 } 2942 2943 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, 2944 enum transcoder transcoder, 2945 const struct intel_link_m_n *m_n) 2946 { 2947 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2948 enum pipe pipe = crtc->pipe; 2949 2950 if (DISPLAY_VER(dev_priv) >= 5) 2951 intel_set_m_n(dev_priv, m_n, 2952 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 2953 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 2954 else 2955 intel_set_m_n(dev_priv, m_n, 2956 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 2957 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 2958 } 2959 2960 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, 2961 enum transcoder transcoder, 2962 const struct intel_link_m_n *m_n) 2963 { 2964 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2965 2966 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 2967 return; 2968 2969 intel_set_m_n(dev_priv, m_n, 2970 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 2971 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 2972 } 2973 2974 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) 2975 { 2976 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2977 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2978 enum pipe pipe = crtc->pipe; 2979 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2980 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2981 u32 crtc_vtotal, crtc_vblank_end; 2982 int vsyncshift = 0; 2983 2984 /* We need to be careful not to changed the adjusted mode, for otherwise 2985 * the hw state checker will get angry at the mismatch. */ 2986 crtc_vtotal = adjusted_mode->crtc_vtotal; 2987 crtc_vblank_end = adjusted_mode->crtc_vblank_end; 2988 2989 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 2990 /* the chip adds 2 halflines automatically */ 2991 crtc_vtotal -= 1; 2992 crtc_vblank_end -= 1; 2993 2994 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 2995 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; 2996 else 2997 vsyncshift = adjusted_mode->crtc_hsync_start - 2998 adjusted_mode->crtc_htotal / 2; 2999 if (vsyncshift < 0) 3000 vsyncshift += adjusted_mode->crtc_htotal; 3001 } 3002 3003 if (DISPLAY_VER(dev_priv) > 3) 3004 intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder), 3005 vsyncshift); 3006 3007 intel_de_write(dev_priv, HTOTAL(cpu_transcoder), 3008 (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16)); 3009 intel_de_write(dev_priv, HBLANK(cpu_transcoder), 3010 (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16)); 3011 intel_de_write(dev_priv, HSYNC(cpu_transcoder), 3012 (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16)); 3013 3014 intel_de_write(dev_priv, VTOTAL(cpu_transcoder), 3015 (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16)); 3016 intel_de_write(dev_priv, VBLANK(cpu_transcoder), 3017 (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16)); 3018 intel_de_write(dev_priv, VSYNC(cpu_transcoder), 3019 (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16)); 3020 3021 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be 3022 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is 3023 * documented on the DDI_FUNC_CTL register description, EDP Input Select 3024 * bits. */ 3025 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && 3026 (pipe == PIPE_B || pipe == PIPE_C)) 3027 intel_de_write(dev_priv, VTOTAL(pipe), 3028 intel_de_read(dev_priv, VTOTAL(cpu_transcoder))); 3029 3030 } 3031 3032 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) 3033 { 3034 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3035 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3036 int width = drm_rect_width(&crtc_state->pipe_src); 3037 int height = drm_rect_height(&crtc_state->pipe_src); 3038 enum pipe pipe = crtc->pipe; 3039 3040 /* pipesrc controls the size that is scaled from, which should 3041 * always be the user's requested size. 3042 */ 3043 intel_de_write(dev_priv, PIPESRC(pipe), 3044 PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1)); 3045 } 3046 3047 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) 3048 { 3049 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3050 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3051 3052 if (DISPLAY_VER(dev_priv) == 2) 3053 return false; 3054 3055 if (DISPLAY_VER(dev_priv) >= 9 || 3056 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 3057 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW; 3058 else 3059 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK; 3060 } 3061 3062 static void intel_get_transcoder_timings(struct intel_crtc *crtc, 3063 struct intel_crtc_state *pipe_config) 3064 { 3065 struct drm_device *dev = crtc->base.dev; 3066 struct drm_i915_private *dev_priv = to_i915(dev); 3067 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3068 u32 tmp; 3069 3070 tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder)); 3071 pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; 3072 pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; 3073 3074 if (!transcoder_is_dsi(cpu_transcoder)) { 3075 tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder)); 3076 pipe_config->hw.adjusted_mode.crtc_hblank_start = 3077 (tmp & 0xffff) + 1; 3078 pipe_config->hw.adjusted_mode.crtc_hblank_end = 3079 ((tmp >> 16) & 0xffff) + 1; 3080 } 3081 tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder)); 3082 pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; 3083 pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; 3084 3085 tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder)); 3086 pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; 3087 pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; 3088 3089 if (!transcoder_is_dsi(cpu_transcoder)) { 3090 tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder)); 3091 pipe_config->hw.adjusted_mode.crtc_vblank_start = 3092 (tmp & 0xffff) + 1; 3093 pipe_config->hw.adjusted_mode.crtc_vblank_end = 3094 ((tmp >> 16) & 0xffff) + 1; 3095 } 3096 tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder)); 3097 pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; 3098 pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; 3099 3100 if (intel_pipe_is_interlaced(pipe_config)) { 3101 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; 3102 pipe_config->hw.adjusted_mode.crtc_vtotal += 1; 3103 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1; 3104 } 3105 } 3106 3107 static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state) 3108 { 3109 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3110 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 3111 enum pipe master_pipe, pipe = crtc->pipe; 3112 int width; 3113 3114 if (num_pipes < 2) 3115 return; 3116 3117 master_pipe = bigjoiner_master_pipe(crtc_state); 3118 width = drm_rect_width(&crtc_state->pipe_src); 3119 3120 drm_rect_translate_to(&crtc_state->pipe_src, 3121 (pipe - master_pipe) * width, 0); 3122 } 3123 3124 static void intel_get_pipe_src_size(struct intel_crtc *crtc, 3125 struct intel_crtc_state *pipe_config) 3126 { 3127 struct drm_device *dev = crtc->base.dev; 3128 struct drm_i915_private *dev_priv = to_i915(dev); 3129 u32 tmp; 3130 3131 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe)); 3132 3133 drm_rect_init(&pipe_config->pipe_src, 0, 0, 3134 REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1, 3135 REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1); 3136 3137 intel_bigjoiner_adjust_pipe_src(pipe_config); 3138 } 3139 3140 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) 3141 { 3142 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3143 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3144 u32 pipeconf = 0; 3145 3146 /* we keep both pipes enabled on 830 */ 3147 if (IS_I830(dev_priv)) 3148 pipeconf |= PIPECONF_ENABLE; 3149 3150 if (crtc_state->double_wide) 3151 pipeconf |= PIPECONF_DOUBLE_WIDE; 3152 3153 /* only g4x and later have fancy bpc/dither controls */ 3154 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 3155 IS_CHERRYVIEW(dev_priv)) { 3156 /* Bspec claims that we can't use dithering for 30bpp pipes. */ 3157 if (crtc_state->dither && crtc_state->pipe_bpp != 30) 3158 pipeconf |= PIPECONF_DITHER_EN | 3159 PIPECONF_DITHER_TYPE_SP; 3160 3161 switch (crtc_state->pipe_bpp) { 3162 case 18: 3163 pipeconf |= PIPECONF_BPC_6; 3164 break; 3165 case 24: 3166 pipeconf |= PIPECONF_BPC_8; 3167 break; 3168 case 30: 3169 pipeconf |= PIPECONF_BPC_10; 3170 break; 3171 default: 3172 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3173 BUG(); 3174 } 3175 } 3176 3177 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 3178 if (DISPLAY_VER(dev_priv) < 4 || 3179 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3180 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; 3181 else 3182 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; 3183 } else { 3184 pipeconf |= PIPECONF_INTERLACE_PROGRESSIVE; 3185 } 3186 3187 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 3188 crtc_state->limited_color_range) 3189 pipeconf |= PIPECONF_COLOR_RANGE_SELECT; 3190 3191 pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); 3192 3193 pipeconf |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3194 3195 intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf); 3196 intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe)); 3197 } 3198 3199 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv) 3200 { 3201 if (IS_I830(dev_priv)) 3202 return false; 3203 3204 return DISPLAY_VER(dev_priv) >= 4 || 3205 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); 3206 } 3207 3208 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state) 3209 { 3210 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3211 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3212 u32 tmp; 3213 3214 if (!i9xx_has_pfit(dev_priv)) 3215 return; 3216 3217 tmp = intel_de_read(dev_priv, PFIT_CONTROL); 3218 if (!(tmp & PFIT_ENABLE)) 3219 return; 3220 3221 /* Check whether the pfit is attached to our pipe. */ 3222 if (DISPLAY_VER(dev_priv) < 4) { 3223 if (crtc->pipe != PIPE_B) 3224 return; 3225 } else { 3226 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) 3227 return; 3228 } 3229 3230 crtc_state->gmch_pfit.control = tmp; 3231 crtc_state->gmch_pfit.pgm_ratios = 3232 intel_de_read(dev_priv, PFIT_PGM_RATIOS); 3233 } 3234 3235 static void vlv_crtc_clock_get(struct intel_crtc *crtc, 3236 struct intel_crtc_state *pipe_config) 3237 { 3238 struct drm_device *dev = crtc->base.dev; 3239 struct drm_i915_private *dev_priv = to_i915(dev); 3240 enum pipe pipe = crtc->pipe; 3241 struct dpll clock; 3242 u32 mdiv; 3243 int refclk = 100000; 3244 3245 /* In case of DSI, DPLL will not be used */ 3246 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 3247 return; 3248 3249 vlv_dpio_get(dev_priv); 3250 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); 3251 vlv_dpio_put(dev_priv); 3252 3253 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; 3254 clock.m2 = mdiv & DPIO_M2DIV_MASK; 3255 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; 3256 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; 3257 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; 3258 3259 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); 3260 } 3261 3262 static void chv_crtc_clock_get(struct intel_crtc *crtc, 3263 struct intel_crtc_state *pipe_config) 3264 { 3265 struct drm_device *dev = crtc->base.dev; 3266 struct drm_i915_private *dev_priv = to_i915(dev); 3267 enum pipe pipe = crtc->pipe; 3268 enum dpio_channel port = vlv_pipe_to_channel(pipe); 3269 struct dpll clock; 3270 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; 3271 int refclk = 100000; 3272 3273 /* In case of DSI, DPLL will not be used */ 3274 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 3275 return; 3276 3277 vlv_dpio_get(dev_priv); 3278 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); 3279 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); 3280 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); 3281 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); 3282 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); 3283 vlv_dpio_put(dev_priv); 3284 3285 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; 3286 clock.m2 = (pll_dw0 & 0xff) << 22; 3287 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) 3288 clock.m2 |= pll_dw2 & 0x3fffff; 3289 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; 3290 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; 3291 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; 3292 3293 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); 3294 } 3295 3296 static enum intel_output_format 3297 bdw_get_pipemisc_output_format(struct intel_crtc *crtc) 3298 { 3299 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3300 u32 tmp; 3301 3302 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); 3303 3304 if (tmp & PIPEMISC_YUV420_ENABLE) { 3305 /* We support 4:2:0 in full blend mode only */ 3306 drm_WARN_ON(&dev_priv->drm, 3307 (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0); 3308 3309 return INTEL_OUTPUT_FORMAT_YCBCR420; 3310 } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) { 3311 return INTEL_OUTPUT_FORMAT_YCBCR444; 3312 } else { 3313 return INTEL_OUTPUT_FORMAT_RGB; 3314 } 3315 } 3316 3317 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state) 3318 { 3319 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3320 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 3321 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3322 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 3323 u32 tmp; 3324 3325 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); 3326 3327 if (tmp & DISP_PIPE_GAMMA_ENABLE) 3328 crtc_state->gamma_enable = true; 3329 3330 if (!HAS_GMCH(dev_priv) && 3331 tmp & DISP_PIPE_CSC_ENABLE) 3332 crtc_state->csc_enable = true; 3333 } 3334 3335 static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 3336 struct intel_crtc_state *pipe_config) 3337 { 3338 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3339 enum intel_display_power_domain power_domain; 3340 intel_wakeref_t wakeref; 3341 u32 tmp; 3342 bool ret; 3343 3344 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3345 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3346 if (!wakeref) 3347 return false; 3348 3349 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3350 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3351 pipe_config->shared_dpll = NULL; 3352 3353 ret = false; 3354 3355 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); 3356 if (!(tmp & PIPECONF_ENABLE)) 3357 goto out; 3358 3359 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 3360 IS_CHERRYVIEW(dev_priv)) { 3361 switch (tmp & PIPECONF_BPC_MASK) { 3362 case PIPECONF_BPC_6: 3363 pipe_config->pipe_bpp = 18; 3364 break; 3365 case PIPECONF_BPC_8: 3366 pipe_config->pipe_bpp = 24; 3367 break; 3368 case PIPECONF_BPC_10: 3369 pipe_config->pipe_bpp = 30; 3370 break; 3371 default: 3372 MISSING_CASE(tmp); 3373 break; 3374 } 3375 } 3376 3377 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 3378 (tmp & PIPECONF_COLOR_RANGE_SELECT)) 3379 pipe_config->limited_color_range = true; 3380 3381 pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_I9XX, tmp); 3382 3383 pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1; 3384 3385 if (IS_CHERRYVIEW(dev_priv)) 3386 pipe_config->cgm_mode = intel_de_read(dev_priv, 3387 CGM_PIPE_MODE(crtc->pipe)); 3388 3389 i9xx_get_pipe_color_config(pipe_config); 3390 intel_color_get_config(pipe_config); 3391 3392 if (DISPLAY_VER(dev_priv) < 4) 3393 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; 3394 3395 intel_get_transcoder_timings(crtc, pipe_config); 3396 intel_get_pipe_src_size(crtc, pipe_config); 3397 3398 i9xx_get_pfit_config(pipe_config); 3399 3400 if (DISPLAY_VER(dev_priv) >= 4) { 3401 /* No way to read it out on pipes B and C */ 3402 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) 3403 tmp = dev_priv->chv_dpll_md[crtc->pipe]; 3404 else 3405 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe)); 3406 pipe_config->pixel_multiplier = 3407 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) 3408 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; 3409 pipe_config->dpll_hw_state.dpll_md = tmp; 3410 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 3411 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 3412 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe)); 3413 pipe_config->pixel_multiplier = 3414 ((tmp & SDVO_MULTIPLIER_MASK) 3415 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; 3416 } else { 3417 /* Note that on i915G/GM the pixel multiplier is in the sdvo 3418 * port and will be fixed up in the encoder->get_config 3419 * function. */ 3420 pipe_config->pixel_multiplier = 1; 3421 } 3422 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv, 3423 DPLL(crtc->pipe)); 3424 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 3425 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv, 3426 FP0(crtc->pipe)); 3427 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv, 3428 FP1(crtc->pipe)); 3429 } else { 3430 /* Mask out read-only status bits. */ 3431 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | 3432 DPLL_PORTC_READY_MASK | 3433 DPLL_PORTB_READY_MASK); 3434 } 3435 3436 if (IS_CHERRYVIEW(dev_priv)) 3437 chv_crtc_clock_get(crtc, pipe_config); 3438 else if (IS_VALLEYVIEW(dev_priv)) 3439 vlv_crtc_clock_get(crtc, pipe_config); 3440 else 3441 i9xx_crtc_clock_get(crtc, pipe_config); 3442 3443 /* 3444 * Normally the dotclock is filled in by the encoder .get_config() 3445 * but in case the pipe is enabled w/o any ports we need a sane 3446 * default. 3447 */ 3448 pipe_config->hw.adjusted_mode.crtc_clock = 3449 pipe_config->port_clock / pipe_config->pixel_multiplier; 3450 3451 ret = true; 3452 3453 out: 3454 intel_display_power_put(dev_priv, power_domain, wakeref); 3455 3456 return ret; 3457 } 3458 3459 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) 3460 { 3461 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3462 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3463 enum pipe pipe = crtc->pipe; 3464 u32 val; 3465 3466 val = 0; 3467 3468 switch (crtc_state->pipe_bpp) { 3469 case 18: 3470 val |= PIPECONF_BPC_6; 3471 break; 3472 case 24: 3473 val |= PIPECONF_BPC_8; 3474 break; 3475 case 30: 3476 val |= PIPECONF_BPC_10; 3477 break; 3478 case 36: 3479 val |= PIPECONF_BPC_12; 3480 break; 3481 default: 3482 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3483 BUG(); 3484 } 3485 3486 if (crtc_state->dither) 3487 val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP; 3488 3489 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3490 val |= PIPECONF_INTERLACE_IF_ID_ILK; 3491 else 3492 val |= PIPECONF_INTERLACE_PF_PD_ILK; 3493 3494 /* 3495 * This would end up with an odd purple hue over 3496 * the entire display. Make sure we don't do it. 3497 */ 3498 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 3499 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 3500 3501 if (crtc_state->limited_color_range && 3502 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3503 val |= PIPECONF_COLOR_RANGE_SELECT; 3504 3505 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3506 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709; 3507 3508 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); 3509 3510 val |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3511 val |= PIPECONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay); 3512 3513 intel_de_write(dev_priv, PIPECONF(pipe), val); 3514 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 3515 } 3516 3517 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) 3518 { 3519 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3520 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3521 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3522 u32 val = 0; 3523 3524 if (IS_HASWELL(dev_priv) && crtc_state->dither) 3525 val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP; 3526 3527 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3528 val |= PIPECONF_INTERLACE_IF_ID_ILK; 3529 else 3530 val |= PIPECONF_INTERLACE_PF_PD_ILK; 3531 3532 if (IS_HASWELL(dev_priv) && 3533 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3534 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW; 3535 3536 intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val); 3537 intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder)); 3538 } 3539 3540 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) 3541 { 3542 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3543 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3544 u32 val = 0; 3545 3546 switch (crtc_state->pipe_bpp) { 3547 case 18: 3548 val |= PIPEMISC_BPC_6; 3549 break; 3550 case 24: 3551 val |= PIPEMISC_BPC_8; 3552 break; 3553 case 30: 3554 val |= PIPEMISC_BPC_10; 3555 break; 3556 case 36: 3557 /* Port output 12BPC defined for ADLP+ */ 3558 if (DISPLAY_VER(dev_priv) > 12) 3559 val |= PIPEMISC_BPC_12_ADLP; 3560 break; 3561 default: 3562 MISSING_CASE(crtc_state->pipe_bpp); 3563 break; 3564 } 3565 3566 if (crtc_state->dither) 3567 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; 3568 3569 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 3570 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 3571 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV; 3572 3573 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 3574 val |= PIPEMISC_YUV420_ENABLE | 3575 PIPEMISC_YUV420_MODE_FULL_BLEND; 3576 3577 if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state)) 3578 val |= PIPEMISC_HDR_MODE_PRECISION; 3579 3580 if (DISPLAY_VER(dev_priv) >= 12) 3581 val |= PIPEMISC_PIXEL_ROUNDING_TRUNC; 3582 3583 intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val); 3584 } 3585 3586 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) 3587 { 3588 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3589 u32 tmp; 3590 3591 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); 3592 3593 switch (tmp & PIPEMISC_BPC_MASK) { 3594 case PIPEMISC_BPC_6: 3595 return 18; 3596 case PIPEMISC_BPC_8: 3597 return 24; 3598 case PIPEMISC_BPC_10: 3599 return 30; 3600 /* 3601 * PORT OUTPUT 12 BPC defined for ADLP+. 3602 * 3603 * TODO: 3604 * For previous platforms with DSI interface, bits 5:7 3605 * are used for storing pipe_bpp irrespective of dithering. 3606 * Since the value of 12 BPC is not defined for these bits 3607 * on older platforms, need to find a workaround for 12 BPC 3608 * MIPI DSI HW readout. 3609 */ 3610 case PIPEMISC_BPC_12_ADLP: 3611 if (DISPLAY_VER(dev_priv) > 12) 3612 return 36; 3613 fallthrough; 3614 default: 3615 MISSING_CASE(tmp); 3616 return 0; 3617 } 3618 } 3619 3620 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) 3621 { 3622 /* 3623 * Account for spread spectrum to avoid 3624 * oversubscribing the link. Max center spread 3625 * is 2.5%; use 5% for safety's sake. 3626 */ 3627 u32 bps = target_clock * bpp * 21 / 20; 3628 return DIV_ROUND_UP(bps, link_bw * 8); 3629 } 3630 3631 void intel_get_m_n(struct drm_i915_private *i915, 3632 struct intel_link_m_n *m_n, 3633 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 3634 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 3635 { 3636 m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK; 3637 m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK; 3638 m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK; 3639 m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK; 3640 m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1; 3641 } 3642 3643 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, 3644 enum transcoder transcoder, 3645 struct intel_link_m_n *m_n) 3646 { 3647 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3648 enum pipe pipe = crtc->pipe; 3649 3650 if (DISPLAY_VER(dev_priv) >= 5) 3651 intel_get_m_n(dev_priv, m_n, 3652 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 3653 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 3654 else 3655 intel_get_m_n(dev_priv, m_n, 3656 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 3657 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 3658 } 3659 3660 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, 3661 enum transcoder transcoder, 3662 struct intel_link_m_n *m_n) 3663 { 3664 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3665 3666 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 3667 return; 3668 3669 intel_get_m_n(dev_priv, m_n, 3670 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 3671 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 3672 } 3673 3674 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state, 3675 u32 pos, u32 size) 3676 { 3677 drm_rect_init(&crtc_state->pch_pfit.dst, 3678 pos >> 16, pos & 0xffff, 3679 size >> 16, size & 0xffff); 3680 } 3681 3682 static void skl_get_pfit_config(struct intel_crtc_state *crtc_state) 3683 { 3684 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3685 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3686 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; 3687 int id = -1; 3688 int i; 3689 3690 /* find scaler attached to this pipe */ 3691 for (i = 0; i < crtc->num_scalers; i++) { 3692 u32 ctl, pos, size; 3693 3694 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i)); 3695 if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN) 3696 continue; 3697 3698 id = i; 3699 crtc_state->pch_pfit.enabled = true; 3700 3701 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i)); 3702 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i)); 3703 3704 ilk_get_pfit_pos_size(crtc_state, pos, size); 3705 3706 scaler_state->scalers[i].in_use = true; 3707 break; 3708 } 3709 3710 scaler_state->scaler_id = id; 3711 if (id >= 0) 3712 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); 3713 else 3714 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); 3715 } 3716 3717 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state) 3718 { 3719 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3720 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3721 u32 ctl, pos, size; 3722 3723 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe)); 3724 if ((ctl & PF_ENABLE) == 0) 3725 return; 3726 3727 crtc_state->pch_pfit.enabled = true; 3728 3729 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe)); 3730 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe)); 3731 3732 ilk_get_pfit_pos_size(crtc_state, pos, size); 3733 3734 /* 3735 * We currently do not free assignements of panel fitters on 3736 * ivb/hsw (since we don't use the higher upscaling modes which 3737 * differentiates them) so just WARN about this case for now. 3738 */ 3739 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 7 && 3740 (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe)); 3741 } 3742 3743 static bool ilk_get_pipe_config(struct intel_crtc *crtc, 3744 struct intel_crtc_state *pipe_config) 3745 { 3746 struct drm_device *dev = crtc->base.dev; 3747 struct drm_i915_private *dev_priv = to_i915(dev); 3748 enum intel_display_power_domain power_domain; 3749 intel_wakeref_t wakeref; 3750 u32 tmp; 3751 bool ret; 3752 3753 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3754 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3755 if (!wakeref) 3756 return false; 3757 3758 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3759 pipe_config->shared_dpll = NULL; 3760 3761 ret = false; 3762 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); 3763 if (!(tmp & PIPECONF_ENABLE)) 3764 goto out; 3765 3766 switch (tmp & PIPECONF_BPC_MASK) { 3767 case PIPECONF_BPC_6: 3768 pipe_config->pipe_bpp = 18; 3769 break; 3770 case PIPECONF_BPC_8: 3771 pipe_config->pipe_bpp = 24; 3772 break; 3773 case PIPECONF_BPC_10: 3774 pipe_config->pipe_bpp = 30; 3775 break; 3776 case PIPECONF_BPC_12: 3777 pipe_config->pipe_bpp = 36; 3778 break; 3779 default: 3780 break; 3781 } 3782 3783 if (tmp & PIPECONF_COLOR_RANGE_SELECT) 3784 pipe_config->limited_color_range = true; 3785 3786 switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) { 3787 case PIPECONF_OUTPUT_COLORSPACE_YUV601: 3788 case PIPECONF_OUTPUT_COLORSPACE_YUV709: 3789 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3790 break; 3791 default: 3792 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3793 break; 3794 } 3795 3796 pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_ILK, tmp); 3797 3798 pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1; 3799 3800 pipe_config->msa_timing_delay = REG_FIELD_GET(PIPECONF_MSA_TIMING_DELAY_MASK, tmp); 3801 3802 pipe_config->csc_mode = intel_de_read(dev_priv, 3803 PIPE_CSC_MODE(crtc->pipe)); 3804 3805 i9xx_get_pipe_color_config(pipe_config); 3806 intel_color_get_config(pipe_config); 3807 3808 pipe_config->pixel_multiplier = 1; 3809 3810 ilk_pch_get_config(pipe_config); 3811 3812 intel_get_transcoder_timings(crtc, pipe_config); 3813 intel_get_pipe_src_size(crtc, pipe_config); 3814 3815 ilk_get_pfit_config(pipe_config); 3816 3817 ret = true; 3818 3819 out: 3820 intel_display_power_put(dev_priv, power_domain, wakeref); 3821 3822 return ret; 3823 } 3824 3825 static u8 bigjoiner_pipes(struct drm_i915_private *i915) 3826 { 3827 if (DISPLAY_VER(i915) >= 12) 3828 return BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D); 3829 else if (DISPLAY_VER(i915) >= 11) 3830 return BIT(PIPE_B) | BIT(PIPE_C); 3831 else 3832 return 0; 3833 } 3834 3835 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv, 3836 enum transcoder cpu_transcoder) 3837 { 3838 enum intel_display_power_domain power_domain; 3839 intel_wakeref_t wakeref; 3840 u32 tmp = 0; 3841 3842 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3843 3844 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3845 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3846 3847 return tmp & TRANS_DDI_FUNC_ENABLE; 3848 } 3849 3850 static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv, 3851 u8 *master_pipes, u8 *slave_pipes) 3852 { 3853 struct intel_crtc *crtc; 3854 3855 *master_pipes = 0; 3856 *slave_pipes = 0; 3857 3858 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, 3859 bigjoiner_pipes(dev_priv)) { 3860 enum intel_display_power_domain power_domain; 3861 enum pipe pipe = crtc->pipe; 3862 intel_wakeref_t wakeref; 3863 3864 power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe); 3865 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3866 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3867 3868 if (!(tmp & BIG_JOINER_ENABLE)) 3869 continue; 3870 3871 if (tmp & MASTER_BIG_JOINER_ENABLE) 3872 *master_pipes |= BIT(pipe); 3873 else 3874 *slave_pipes |= BIT(pipe); 3875 } 3876 3877 if (DISPLAY_VER(dev_priv) < 13) 3878 continue; 3879 3880 power_domain = POWER_DOMAIN_PIPE(pipe); 3881 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3882 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3883 3884 if (tmp & UNCOMPRESSED_JOINER_MASTER) 3885 *master_pipes |= BIT(pipe); 3886 if (tmp & UNCOMPRESSED_JOINER_SLAVE) 3887 *slave_pipes |= BIT(pipe); 3888 } 3889 } 3890 3891 /* Bigjoiner pipes should always be consecutive master and slave */ 3892 drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1, 3893 "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n", 3894 *master_pipes, *slave_pipes); 3895 } 3896 3897 static enum pipe get_bigjoiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3898 { 3899 if ((slave_pipes & BIT(pipe)) == 0) 3900 return pipe; 3901 3902 /* ignore everything above our pipe */ 3903 master_pipes &= ~GENMASK(7, pipe); 3904 3905 /* highest remaining bit should be our master pipe */ 3906 return fls(master_pipes) - 1; 3907 } 3908 3909 static u8 get_bigjoiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3910 { 3911 enum pipe master_pipe, next_master_pipe; 3912 3913 master_pipe = get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes); 3914 3915 if ((master_pipes & BIT(master_pipe)) == 0) 3916 return 0; 3917 3918 /* ignore our master pipe and everything below it */ 3919 master_pipes &= ~GENMASK(master_pipe, 0); 3920 /* make sure a high bit is set for the ffs() */ 3921 master_pipes |= BIT(7); 3922 /* lowest remaining bit should be the next master pipe */ 3923 next_master_pipe = ffs(master_pipes) - 1; 3924 3925 return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe); 3926 } 3927 3928 static u8 hsw_panel_transcoders(struct drm_i915_private *i915) 3929 { 3930 u8 panel_transcoder_mask = BIT(TRANSCODER_EDP); 3931 3932 if (DISPLAY_VER(i915) >= 11) 3933 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); 3934 3935 return panel_transcoder_mask; 3936 } 3937 3938 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) 3939 { 3940 struct drm_device *dev = crtc->base.dev; 3941 struct drm_i915_private *dev_priv = to_i915(dev); 3942 u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv); 3943 enum transcoder cpu_transcoder; 3944 u8 master_pipes, slave_pipes; 3945 u8 enabled_transcoders = 0; 3946 3947 /* 3948 * XXX: Do intel_display_power_get_if_enabled before reading this (for 3949 * consistency and less surprising code; it's in always on power). 3950 */ 3951 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, 3952 panel_transcoder_mask) { 3953 enum intel_display_power_domain power_domain; 3954 intel_wakeref_t wakeref; 3955 enum pipe trans_pipe; 3956 u32 tmp = 0; 3957 3958 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3959 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3960 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3961 3962 if (!(tmp & TRANS_DDI_FUNC_ENABLE)) 3963 continue; 3964 3965 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 3966 default: 3967 drm_WARN(dev, 1, 3968 "unknown pipe linked to transcoder %s\n", 3969 transcoder_name(cpu_transcoder)); 3970 fallthrough; 3971 case TRANS_DDI_EDP_INPUT_A_ONOFF: 3972 case TRANS_DDI_EDP_INPUT_A_ON: 3973 trans_pipe = PIPE_A; 3974 break; 3975 case TRANS_DDI_EDP_INPUT_B_ONOFF: 3976 trans_pipe = PIPE_B; 3977 break; 3978 case TRANS_DDI_EDP_INPUT_C_ONOFF: 3979 trans_pipe = PIPE_C; 3980 break; 3981 case TRANS_DDI_EDP_INPUT_D_ONOFF: 3982 trans_pipe = PIPE_D; 3983 break; 3984 } 3985 3986 if (trans_pipe == crtc->pipe) 3987 enabled_transcoders |= BIT(cpu_transcoder); 3988 } 3989 3990 /* single pipe or bigjoiner master */ 3991 cpu_transcoder = (enum transcoder) crtc->pipe; 3992 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 3993 enabled_transcoders |= BIT(cpu_transcoder); 3994 3995 /* bigjoiner slave -> consider the master pipe's transcoder as well */ 3996 enabled_bigjoiner_pipes(dev_priv, &master_pipes, &slave_pipes); 3997 if (slave_pipes & BIT(crtc->pipe)) { 3998 cpu_transcoder = (enum transcoder) 3999 get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes); 4000 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 4001 enabled_transcoders |= BIT(cpu_transcoder); 4002 } 4003 4004 return enabled_transcoders; 4005 } 4006 4007 static bool has_edp_transcoders(u8 enabled_transcoders) 4008 { 4009 return enabled_transcoders & BIT(TRANSCODER_EDP); 4010 } 4011 4012 static bool has_dsi_transcoders(u8 enabled_transcoders) 4013 { 4014 return enabled_transcoders & (BIT(TRANSCODER_DSI_0) | 4015 BIT(TRANSCODER_DSI_1)); 4016 } 4017 4018 static bool has_pipe_transcoders(u8 enabled_transcoders) 4019 { 4020 return enabled_transcoders & ~(BIT(TRANSCODER_EDP) | 4021 BIT(TRANSCODER_DSI_0) | 4022 BIT(TRANSCODER_DSI_1)); 4023 } 4024 4025 static void assert_enabled_transcoders(struct drm_i915_private *i915, 4026 u8 enabled_transcoders) 4027 { 4028 /* Only one type of transcoder please */ 4029 drm_WARN_ON(&i915->drm, 4030 has_edp_transcoders(enabled_transcoders) + 4031 has_dsi_transcoders(enabled_transcoders) + 4032 has_pipe_transcoders(enabled_transcoders) > 1); 4033 4034 /* Only DSI transcoders can be ganged */ 4035 drm_WARN_ON(&i915->drm, 4036 !has_dsi_transcoders(enabled_transcoders) && 4037 !is_power_of_2(enabled_transcoders)); 4038 } 4039 4040 static bool hsw_get_transcoder_state(struct intel_crtc *crtc, 4041 struct intel_crtc_state *pipe_config, 4042 struct intel_display_power_domain_set *power_domain_set) 4043 { 4044 struct drm_device *dev = crtc->base.dev; 4045 struct drm_i915_private *dev_priv = to_i915(dev); 4046 unsigned long enabled_transcoders; 4047 u32 tmp; 4048 4049 enabled_transcoders = hsw_enabled_transcoders(crtc); 4050 if (!enabled_transcoders) 4051 return false; 4052 4053 assert_enabled_transcoders(dev_priv, enabled_transcoders); 4054 4055 /* 4056 * With the exception of DSI we should only ever have 4057 * a single enabled transcoder. With DSI let's just 4058 * pick the first one. 4059 */ 4060 pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1; 4061 4062 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 4063 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) 4064 return false; 4065 4066 if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) { 4067 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); 4068 4069 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF) 4070 pipe_config->pch_pfit.force_thru = true; 4071 } 4072 4073 tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder)); 4074 4075 return tmp & PIPECONF_ENABLE; 4076 } 4077 4078 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, 4079 struct intel_crtc_state *pipe_config, 4080 struct intel_display_power_domain_set *power_domain_set) 4081 { 4082 struct drm_device *dev = crtc->base.dev; 4083 struct drm_i915_private *dev_priv = to_i915(dev); 4084 enum transcoder cpu_transcoder; 4085 enum port port; 4086 u32 tmp; 4087 4088 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { 4089 if (port == PORT_A) 4090 cpu_transcoder = TRANSCODER_DSI_A; 4091 else 4092 cpu_transcoder = TRANSCODER_DSI_C; 4093 4094 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 4095 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) 4096 continue; 4097 4098 /* 4099 * The PLL needs to be enabled with a valid divider 4100 * configuration, otherwise accessing DSI registers will hang 4101 * the machine. See BSpec North Display Engine 4102 * registers/MIPI[BXT]. We can break out here early, since we 4103 * need the same DSI PLL to be enabled for both DSI ports. 4104 */ 4105 if (!bxt_dsi_pll_is_enabled(dev_priv)) 4106 break; 4107 4108 /* XXX: this works for video mode only */ 4109 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); 4110 if (!(tmp & DPI_ENABLE)) 4111 continue; 4112 4113 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 4114 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) 4115 continue; 4116 4117 pipe_config->cpu_transcoder = cpu_transcoder; 4118 break; 4119 } 4120 4121 return transcoder_is_dsi(pipe_config->cpu_transcoder); 4122 } 4123 4124 static void intel_bigjoiner_get_config(struct intel_crtc_state *crtc_state) 4125 { 4126 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4127 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4128 u8 master_pipes, slave_pipes; 4129 enum pipe pipe = crtc->pipe; 4130 4131 enabled_bigjoiner_pipes(i915, &master_pipes, &slave_pipes); 4132 4133 if (((master_pipes | slave_pipes) & BIT(pipe)) == 0) 4134 return; 4135 4136 crtc_state->bigjoiner_pipes = 4137 BIT(get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes)) | 4138 get_bigjoiner_slave_pipes(pipe, master_pipes, slave_pipes); 4139 } 4140 4141 static bool hsw_get_pipe_config(struct intel_crtc *crtc, 4142 struct intel_crtc_state *pipe_config) 4143 { 4144 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4145 struct intel_display_power_domain_set power_domain_set = { }; 4146 bool active; 4147 u32 tmp; 4148 4149 if (!intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set, 4150 POWER_DOMAIN_PIPE(crtc->pipe))) 4151 return false; 4152 4153 pipe_config->shared_dpll = NULL; 4154 4155 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_set); 4156 4157 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 4158 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_set)) { 4159 drm_WARN_ON(&dev_priv->drm, active); 4160 active = true; 4161 } 4162 4163 if (!active) 4164 goto out; 4165 4166 intel_dsc_get_config(pipe_config); 4167 intel_bigjoiner_get_config(pipe_config); 4168 4169 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || 4170 DISPLAY_VER(dev_priv) >= 11) 4171 intel_get_transcoder_timings(crtc, pipe_config); 4172 4173 if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder)) 4174 intel_vrr_get_config(crtc, pipe_config); 4175 4176 intel_get_pipe_src_size(crtc, pipe_config); 4177 4178 if (IS_HASWELL(dev_priv)) { 4179 u32 tmp = intel_de_read(dev_priv, 4180 PIPECONF(pipe_config->cpu_transcoder)); 4181 4182 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW) 4183 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 4184 else 4185 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 4186 } else { 4187 pipe_config->output_format = 4188 bdw_get_pipemisc_output_format(crtc); 4189 } 4190 4191 pipe_config->gamma_mode = intel_de_read(dev_priv, 4192 GAMMA_MODE(crtc->pipe)); 4193 4194 pipe_config->csc_mode = intel_de_read(dev_priv, 4195 PIPE_CSC_MODE(crtc->pipe)); 4196 4197 if (DISPLAY_VER(dev_priv) >= 9) { 4198 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe)); 4199 4200 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE) 4201 pipe_config->gamma_enable = true; 4202 4203 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE) 4204 pipe_config->csc_enable = true; 4205 } else { 4206 i9xx_get_pipe_color_config(pipe_config); 4207 } 4208 4209 intel_color_get_config(pipe_config); 4210 4211 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe)); 4212 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); 4213 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 4214 pipe_config->ips_linetime = 4215 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); 4216 4217 if (intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set, 4218 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) { 4219 if (DISPLAY_VER(dev_priv) >= 9) 4220 skl_get_pfit_config(pipe_config); 4221 else 4222 ilk_get_pfit_config(pipe_config); 4223 } 4224 4225 hsw_ips_get_config(pipe_config); 4226 4227 if (pipe_config->cpu_transcoder != TRANSCODER_EDP && 4228 !transcoder_is_dsi(pipe_config->cpu_transcoder)) { 4229 pipe_config->pixel_multiplier = 4230 intel_de_read(dev_priv, 4231 PIPE_MULT(pipe_config->cpu_transcoder)) + 1; 4232 } else { 4233 pipe_config->pixel_multiplier = 1; 4234 } 4235 4236 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { 4237 tmp = intel_de_read(dev_priv, CHICKEN_TRANS(pipe_config->cpu_transcoder)); 4238 4239 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1; 4240 } else { 4241 /* no idea if this is correct */ 4242 pipe_config->framestart_delay = 1; 4243 } 4244 4245 out: 4246 intel_display_power_put_all_in_set(dev_priv, &power_domain_set); 4247 4248 return active; 4249 } 4250 4251 static bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state) 4252 { 4253 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4254 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4255 4256 if (!i915->display->get_pipe_config(crtc, crtc_state)) 4257 return false; 4258 4259 crtc_state->hw.active = true; 4260 4261 intel_crtc_readout_derived_state(crtc_state); 4262 4263 return true; 4264 } 4265 4266 /* VESA 640x480x72Hz mode to set on the pipe */ 4267 static const struct drm_display_mode load_detect_mode = { 4268 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, 4269 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 4270 }; 4271 4272 static int intel_modeset_disable_planes(struct drm_atomic_state *state, 4273 struct drm_crtc *crtc) 4274 { 4275 struct drm_plane *plane; 4276 struct drm_plane_state *plane_state; 4277 int ret, i; 4278 4279 ret = drm_atomic_add_affected_planes(state, crtc); 4280 if (ret) 4281 return ret; 4282 4283 for_each_new_plane_in_state(state, plane, plane_state, i) { 4284 if (plane_state->crtc != crtc) 4285 continue; 4286 4287 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL); 4288 if (ret) 4289 return ret; 4290 4291 drm_atomic_set_fb_for_plane(plane_state, NULL); 4292 } 4293 4294 return 0; 4295 } 4296 4297 int intel_get_load_detect_pipe(struct drm_connector *connector, 4298 struct intel_load_detect_pipe *old, 4299 struct drm_modeset_acquire_ctx *ctx) 4300 { 4301 struct intel_encoder *encoder = 4302 intel_attached_encoder(to_intel_connector(connector)); 4303 struct intel_crtc *possible_crtc; 4304 struct intel_crtc *crtc = NULL; 4305 struct drm_device *dev = encoder->base.dev; 4306 struct drm_i915_private *dev_priv = to_i915(dev); 4307 struct drm_mode_config *config = &dev->mode_config; 4308 struct drm_atomic_state *state = NULL, *restore_state = NULL; 4309 struct drm_connector_state *connector_state; 4310 struct intel_crtc_state *crtc_state; 4311 int ret; 4312 4313 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 4314 connector->base.id, connector->name, 4315 encoder->base.base.id, encoder->base.name); 4316 4317 old->restore_state = NULL; 4318 4319 drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex)); 4320 4321 /* 4322 * Algorithm gets a little messy: 4323 * 4324 * - if the connector already has an assigned crtc, use it (but make 4325 * sure it's on first) 4326 * 4327 * - try to find the first unused crtc that can drive this connector, 4328 * and use that if we find one 4329 */ 4330 4331 /* See if we already have a CRTC for this connector */ 4332 if (connector->state->crtc) { 4333 crtc = to_intel_crtc(connector->state->crtc); 4334 4335 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4336 if (ret) 4337 goto fail; 4338 4339 /* Make sure the crtc and connector are running */ 4340 goto found; 4341 } 4342 4343 /* Find an unused one (if possible) */ 4344 for_each_intel_crtc(dev, possible_crtc) { 4345 if (!(encoder->base.possible_crtcs & 4346 drm_crtc_mask(&possible_crtc->base))) 4347 continue; 4348 4349 ret = drm_modeset_lock(&possible_crtc->base.mutex, ctx); 4350 if (ret) 4351 goto fail; 4352 4353 if (possible_crtc->base.state->enable) { 4354 drm_modeset_unlock(&possible_crtc->base.mutex); 4355 continue; 4356 } 4357 4358 crtc = possible_crtc; 4359 break; 4360 } 4361 4362 /* 4363 * If we didn't find an unused CRTC, don't use any. 4364 */ 4365 if (!crtc) { 4366 drm_dbg_kms(&dev_priv->drm, 4367 "no pipe available for load-detect\n"); 4368 ret = -ENODEV; 4369 goto fail; 4370 } 4371 4372 found: 4373 state = drm_atomic_state_alloc(dev); 4374 restore_state = drm_atomic_state_alloc(dev); 4375 if (!state || !restore_state) { 4376 ret = -ENOMEM; 4377 goto fail; 4378 } 4379 4380 state->acquire_ctx = ctx; 4381 restore_state->acquire_ctx = ctx; 4382 4383 connector_state = drm_atomic_get_connector_state(state, connector); 4384 if (IS_ERR(connector_state)) { 4385 ret = PTR_ERR(connector_state); 4386 goto fail; 4387 } 4388 4389 ret = drm_atomic_set_crtc_for_connector(connector_state, &crtc->base); 4390 if (ret) 4391 goto fail; 4392 4393 crtc_state = intel_atomic_get_crtc_state(state, crtc); 4394 if (IS_ERR(crtc_state)) { 4395 ret = PTR_ERR(crtc_state); 4396 goto fail; 4397 } 4398 4399 crtc_state->uapi.active = true; 4400 4401 ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi, 4402 &load_detect_mode); 4403 if (ret) 4404 goto fail; 4405 4406 ret = intel_modeset_disable_planes(state, &crtc->base); 4407 if (ret) 4408 goto fail; 4409 4410 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); 4411 if (!ret) 4412 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, &crtc->base)); 4413 if (!ret) 4414 ret = drm_atomic_add_affected_planes(restore_state, &crtc->base); 4415 if (ret) { 4416 drm_dbg_kms(&dev_priv->drm, 4417 "Failed to create a copy of old state to restore: %i\n", 4418 ret); 4419 goto fail; 4420 } 4421 4422 ret = drm_atomic_commit(state); 4423 if (ret) { 4424 drm_dbg_kms(&dev_priv->drm, 4425 "failed to set mode on load-detect pipe\n"); 4426 goto fail; 4427 } 4428 4429 old->restore_state = restore_state; 4430 drm_atomic_state_put(state); 4431 4432 /* let the connector get through one full cycle before testing */ 4433 intel_crtc_wait_for_next_vblank(crtc); 4434 4435 return true; 4436 4437 fail: 4438 if (state) { 4439 drm_atomic_state_put(state); 4440 state = NULL; 4441 } 4442 if (restore_state) { 4443 drm_atomic_state_put(restore_state); 4444 restore_state = NULL; 4445 } 4446 4447 if (ret == -EDEADLK) 4448 return ret; 4449 4450 return false; 4451 } 4452 4453 void intel_release_load_detect_pipe(struct drm_connector *connector, 4454 struct intel_load_detect_pipe *old, 4455 struct drm_modeset_acquire_ctx *ctx) 4456 { 4457 struct intel_encoder *intel_encoder = 4458 intel_attached_encoder(to_intel_connector(connector)); 4459 struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev); 4460 struct drm_encoder *encoder = &intel_encoder->base; 4461 struct drm_atomic_state *state = old->restore_state; 4462 int ret; 4463 4464 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 4465 connector->base.id, connector->name, 4466 encoder->base.id, encoder->name); 4467 4468 if (!state) 4469 return; 4470 4471 ret = drm_atomic_helper_commit_duplicated_state(state, ctx); 4472 if (ret) 4473 drm_dbg_kms(&i915->drm, 4474 "Couldn't release load detect pipe: %i\n", ret); 4475 drm_atomic_state_put(state); 4476 } 4477 4478 static int i9xx_pll_refclk(struct drm_device *dev, 4479 const struct intel_crtc_state *pipe_config) 4480 { 4481 struct drm_i915_private *dev_priv = to_i915(dev); 4482 u32 dpll = pipe_config->dpll_hw_state.dpll; 4483 4484 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) 4485 return dev_priv->vbt.lvds_ssc_freq; 4486 else if (HAS_PCH_SPLIT(dev_priv)) 4487 return 120000; 4488 else if (DISPLAY_VER(dev_priv) != 2) 4489 return 96000; 4490 else 4491 return 48000; 4492 } 4493 4494 /* Returns the clock of the currently programmed mode of the given pipe. */ 4495 void i9xx_crtc_clock_get(struct intel_crtc *crtc, 4496 struct intel_crtc_state *pipe_config) 4497 { 4498 struct drm_device *dev = crtc->base.dev; 4499 struct drm_i915_private *dev_priv = to_i915(dev); 4500 u32 dpll = pipe_config->dpll_hw_state.dpll; 4501 u32 fp; 4502 struct dpll clock; 4503 int port_clock; 4504 int refclk = i9xx_pll_refclk(dev, pipe_config); 4505 4506 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 4507 fp = pipe_config->dpll_hw_state.fp0; 4508 else 4509 fp = pipe_config->dpll_hw_state.fp1; 4510 4511 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 4512 if (IS_PINEVIEW(dev_priv)) { 4513 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; 4514 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; 4515 } else { 4516 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 4517 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 4518 } 4519 4520 if (DISPLAY_VER(dev_priv) != 2) { 4521 if (IS_PINEVIEW(dev_priv)) 4522 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> 4523 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); 4524 else 4525 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> 4526 DPLL_FPA01_P1_POST_DIV_SHIFT); 4527 4528 switch (dpll & DPLL_MODE_MASK) { 4529 case DPLLB_MODE_DAC_SERIAL: 4530 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 4531 5 : 10; 4532 break; 4533 case DPLLB_MODE_LVDS: 4534 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 4535 7 : 14; 4536 break; 4537 default: 4538 drm_dbg_kms(&dev_priv->drm, 4539 "Unknown DPLL mode %08x in programmed " 4540 "mode\n", (int)(dpll & DPLL_MODE_MASK)); 4541 return; 4542 } 4543 4544 if (IS_PINEVIEW(dev_priv)) 4545 port_clock = pnv_calc_dpll_params(refclk, &clock); 4546 else 4547 port_clock = i9xx_calc_dpll_params(refclk, &clock); 4548 } else { 4549 enum pipe lvds_pipe; 4550 4551 if (IS_I85X(dev_priv) && 4552 intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) && 4553 lvds_pipe == crtc->pipe) { 4554 u32 lvds = intel_de_read(dev_priv, LVDS); 4555 4556 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 4557 DPLL_FPA01_P1_POST_DIV_SHIFT); 4558 4559 if (lvds & LVDS_CLKB_POWER_UP) 4560 clock.p2 = 7; 4561 else 4562 clock.p2 = 14; 4563 } else { 4564 if (dpll & PLL_P1_DIVIDE_BY_TWO) 4565 clock.p1 = 2; 4566 else { 4567 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 4568 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 4569 } 4570 if (dpll & PLL_P2_DIVIDE_BY_4) 4571 clock.p2 = 4; 4572 else 4573 clock.p2 = 2; 4574 } 4575 4576 port_clock = i9xx_calc_dpll_params(refclk, &clock); 4577 } 4578 4579 /* 4580 * This value includes pixel_multiplier. We will use 4581 * port_clock to compute adjusted_mode.crtc_clock in the 4582 * encoder's get_config() function. 4583 */ 4584 pipe_config->port_clock = port_clock; 4585 } 4586 4587 int intel_dotclock_calculate(int link_freq, 4588 const struct intel_link_m_n *m_n) 4589 { 4590 /* 4591 * The calculation for the data clock is: 4592 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp 4593 * But we want to avoid losing precison if possible, so: 4594 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) 4595 * 4596 * and the link clock is simpler: 4597 * link_clock = (m * link_clock) / n 4598 */ 4599 4600 if (!m_n->link_n) 4601 return 0; 4602 4603 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n); 4604 } 4605 4606 /* Returns the currently programmed mode of the given encoder. */ 4607 struct drm_display_mode * 4608 intel_encoder_current_mode(struct intel_encoder *encoder) 4609 { 4610 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4611 struct intel_crtc_state *crtc_state; 4612 struct drm_display_mode *mode; 4613 struct intel_crtc *crtc; 4614 enum pipe pipe; 4615 4616 if (!encoder->get_hw_state(encoder, &pipe)) 4617 return NULL; 4618 4619 crtc = intel_crtc_for_pipe(dev_priv, pipe); 4620 4621 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 4622 if (!mode) 4623 return NULL; 4624 4625 crtc_state = intel_crtc_state_alloc(crtc); 4626 if (!crtc_state) { 4627 kfree(mode); 4628 return NULL; 4629 } 4630 4631 if (!intel_crtc_get_pipe_config(crtc_state)) { 4632 kfree(crtc_state); 4633 kfree(mode); 4634 return NULL; 4635 } 4636 4637 intel_encoder_get_config(encoder, crtc_state); 4638 4639 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode); 4640 4641 kfree(crtc_state); 4642 4643 return mode; 4644 } 4645 4646 static bool encoders_cloneable(const struct intel_encoder *a, 4647 const struct intel_encoder *b) 4648 { 4649 /* masks could be asymmetric, so check both ways */ 4650 return a == b || (a->cloneable & (1 << b->type) && 4651 b->cloneable & (1 << a->type)); 4652 } 4653 4654 static bool check_single_encoder_cloning(struct intel_atomic_state *state, 4655 struct intel_crtc *crtc, 4656 struct intel_encoder *encoder) 4657 { 4658 struct intel_encoder *source_encoder; 4659 struct drm_connector *connector; 4660 struct drm_connector_state *connector_state; 4661 int i; 4662 4663 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4664 if (connector_state->crtc != &crtc->base) 4665 continue; 4666 4667 source_encoder = 4668 to_intel_encoder(connector_state->best_encoder); 4669 if (!encoders_cloneable(encoder, source_encoder)) 4670 return false; 4671 } 4672 4673 return true; 4674 } 4675 4676 static int icl_add_linked_planes(struct intel_atomic_state *state) 4677 { 4678 struct intel_plane *plane, *linked; 4679 struct intel_plane_state *plane_state, *linked_plane_state; 4680 int i; 4681 4682 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4683 linked = plane_state->planar_linked_plane; 4684 4685 if (!linked) 4686 continue; 4687 4688 linked_plane_state = intel_atomic_get_plane_state(state, linked); 4689 if (IS_ERR(linked_plane_state)) 4690 return PTR_ERR(linked_plane_state); 4691 4692 drm_WARN_ON(state->base.dev, 4693 linked_plane_state->planar_linked_plane != plane); 4694 drm_WARN_ON(state->base.dev, 4695 linked_plane_state->planar_slave == plane_state->planar_slave); 4696 } 4697 4698 return 0; 4699 } 4700 4701 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state) 4702 { 4703 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4704 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4705 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 4706 struct intel_plane *plane, *linked; 4707 struct intel_plane_state *plane_state; 4708 int i; 4709 4710 if (DISPLAY_VER(dev_priv) < 11) 4711 return 0; 4712 4713 /* 4714 * Destroy all old plane links and make the slave plane invisible 4715 * in the crtc_state->active_planes mask. 4716 */ 4717 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4718 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane) 4719 continue; 4720 4721 plane_state->planar_linked_plane = NULL; 4722 if (plane_state->planar_slave && !plane_state->uapi.visible) { 4723 crtc_state->enabled_planes &= ~BIT(plane->id); 4724 crtc_state->active_planes &= ~BIT(plane->id); 4725 crtc_state->update_planes |= BIT(plane->id); 4726 crtc_state->data_rate[plane->id] = 0; 4727 crtc_state->rel_data_rate[plane->id] = 0; 4728 } 4729 4730 plane_state->planar_slave = false; 4731 } 4732 4733 if (!crtc_state->nv12_planes) 4734 return 0; 4735 4736 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4737 struct intel_plane_state *linked_state = NULL; 4738 4739 if (plane->pipe != crtc->pipe || 4740 !(crtc_state->nv12_planes & BIT(plane->id))) 4741 continue; 4742 4743 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) { 4744 if (!icl_is_nv12_y_plane(dev_priv, linked->id)) 4745 continue; 4746 4747 if (crtc_state->active_planes & BIT(linked->id)) 4748 continue; 4749 4750 linked_state = intel_atomic_get_plane_state(state, linked); 4751 if (IS_ERR(linked_state)) 4752 return PTR_ERR(linked_state); 4753 4754 break; 4755 } 4756 4757 if (!linked_state) { 4758 drm_dbg_kms(&dev_priv->drm, 4759 "Need %d free Y planes for planar YUV\n", 4760 hweight8(crtc_state->nv12_planes)); 4761 4762 return -EINVAL; 4763 } 4764 4765 plane_state->planar_linked_plane = linked; 4766 4767 linked_state->planar_slave = true; 4768 linked_state->planar_linked_plane = plane; 4769 crtc_state->enabled_planes |= BIT(linked->id); 4770 crtc_state->active_planes |= BIT(linked->id); 4771 crtc_state->update_planes |= BIT(linked->id); 4772 crtc_state->data_rate[linked->id] = 4773 crtc_state->data_rate_y[plane->id]; 4774 crtc_state->rel_data_rate[linked->id] = 4775 crtc_state->rel_data_rate_y[plane->id]; 4776 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n", 4777 linked->base.name, plane->base.name); 4778 4779 /* Copy parameters to slave plane */ 4780 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE; 4781 linked_state->color_ctl = plane_state->color_ctl; 4782 linked_state->view = plane_state->view; 4783 linked_state->decrypt = plane_state->decrypt; 4784 4785 intel_plane_copy_hw_state(linked_state, plane_state); 4786 linked_state->uapi.src = plane_state->uapi.src; 4787 linked_state->uapi.dst = plane_state->uapi.dst; 4788 4789 if (icl_is_hdr_plane(dev_priv, plane->id)) { 4790 if (linked->id == PLANE_SPRITE5) 4791 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL; 4792 else if (linked->id == PLANE_SPRITE4) 4793 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL; 4794 else if (linked->id == PLANE_SPRITE3) 4795 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL; 4796 else if (linked->id == PLANE_SPRITE2) 4797 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL; 4798 else 4799 MISSING_CASE(linked->id); 4800 } 4801 } 4802 4803 return 0; 4804 } 4805 4806 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state) 4807 { 4808 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 4809 struct intel_atomic_state *state = 4810 to_intel_atomic_state(new_crtc_state->uapi.state); 4811 const struct intel_crtc_state *old_crtc_state = 4812 intel_atomic_get_old_crtc_state(state, crtc); 4813 4814 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes; 4815 } 4816 4817 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) 4818 { 4819 const struct drm_display_mode *pipe_mode = 4820 &crtc_state->hw.pipe_mode; 4821 int linetime_wm; 4822 4823 if (!crtc_state->hw.enable) 4824 return 0; 4825 4826 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4827 pipe_mode->crtc_clock); 4828 4829 return min(linetime_wm, 0x1ff); 4830 } 4831 4832 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, 4833 const struct intel_cdclk_state *cdclk_state) 4834 { 4835 const struct drm_display_mode *pipe_mode = 4836 &crtc_state->hw.pipe_mode; 4837 int linetime_wm; 4838 4839 if (!crtc_state->hw.enable) 4840 return 0; 4841 4842 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4843 cdclk_state->logical.cdclk); 4844 4845 return min(linetime_wm, 0x1ff); 4846 } 4847 4848 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) 4849 { 4850 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4851 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4852 const struct drm_display_mode *pipe_mode = 4853 &crtc_state->hw.pipe_mode; 4854 int linetime_wm; 4855 4856 if (!crtc_state->hw.enable) 4857 return 0; 4858 4859 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8, 4860 crtc_state->pixel_rate); 4861 4862 /* Display WA #1135: BXT:ALL GLK:ALL */ 4863 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 4864 dev_priv->ipc_enabled) 4865 linetime_wm /= 2; 4866 4867 return min(linetime_wm, 0x1ff); 4868 } 4869 4870 static int hsw_compute_linetime_wm(struct intel_atomic_state *state, 4871 struct intel_crtc *crtc) 4872 { 4873 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4874 struct intel_crtc_state *crtc_state = 4875 intel_atomic_get_new_crtc_state(state, crtc); 4876 const struct intel_cdclk_state *cdclk_state; 4877 4878 if (DISPLAY_VER(dev_priv) >= 9) 4879 crtc_state->linetime = skl_linetime_wm(crtc_state); 4880 else 4881 crtc_state->linetime = hsw_linetime_wm(crtc_state); 4882 4883 if (!hsw_crtc_supports_ips(crtc)) 4884 return 0; 4885 4886 cdclk_state = intel_atomic_get_cdclk_state(state); 4887 if (IS_ERR(cdclk_state)) 4888 return PTR_ERR(cdclk_state); 4889 4890 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state, 4891 cdclk_state); 4892 4893 return 0; 4894 } 4895 4896 static int intel_crtc_atomic_check(struct intel_atomic_state *state, 4897 struct intel_crtc *crtc) 4898 { 4899 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4900 struct intel_crtc_state *crtc_state = 4901 intel_atomic_get_new_crtc_state(state, crtc); 4902 bool mode_changed = intel_crtc_needs_modeset(crtc_state); 4903 int ret; 4904 4905 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) && 4906 mode_changed && !crtc_state->hw.active) 4907 crtc_state->update_wm_post = true; 4908 4909 if (mode_changed) { 4910 ret = intel_dpll_crtc_compute_clock(state, crtc); 4911 if (ret) 4912 return ret; 4913 4914 ret = intel_dpll_crtc_get_shared_dpll(state, crtc); 4915 if (ret) 4916 return ret; 4917 } 4918 4919 /* 4920 * May need to update pipe gamma enable bits 4921 * when C8 planes are getting enabled/disabled. 4922 */ 4923 if (c8_planes_changed(crtc_state)) 4924 crtc_state->uapi.color_mgmt_changed = true; 4925 4926 if (mode_changed || crtc_state->update_pipe || 4927 crtc_state->uapi.color_mgmt_changed) { 4928 ret = intel_color_check(crtc_state); 4929 if (ret) 4930 return ret; 4931 } 4932 4933 ret = intel_compute_pipe_wm(state, crtc); 4934 if (ret) { 4935 drm_dbg_kms(&dev_priv->drm, 4936 "Target pipe watermarks are invalid\n"); 4937 return ret; 4938 } 4939 4940 /* 4941 * Calculate 'intermediate' watermarks that satisfy both the 4942 * old state and the new state. We can program these 4943 * immediately. 4944 */ 4945 ret = intel_compute_intermediate_wm(state, crtc); 4946 if (ret) { 4947 drm_dbg_kms(&dev_priv->drm, 4948 "No valid intermediate pipe watermarks are possible\n"); 4949 return ret; 4950 } 4951 4952 if (DISPLAY_VER(dev_priv) >= 9) { 4953 if (mode_changed || crtc_state->update_pipe) { 4954 ret = skl_update_scaler_crtc(crtc_state); 4955 if (ret) 4956 return ret; 4957 } 4958 4959 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state); 4960 if (ret) 4961 return ret; 4962 } 4963 4964 if (HAS_IPS(dev_priv)) { 4965 ret = hsw_ips_compute_config(state, crtc); 4966 if (ret) 4967 return ret; 4968 } 4969 4970 if (DISPLAY_VER(dev_priv) >= 9 || 4971 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 4972 ret = hsw_compute_linetime_wm(state, crtc); 4973 if (ret) 4974 return ret; 4975 4976 } 4977 4978 ret = intel_psr2_sel_fetch_update(state, crtc); 4979 if (ret) 4980 return ret; 4981 4982 return 0; 4983 } 4984 4985 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) 4986 { 4987 struct intel_connector *connector; 4988 struct drm_connector_list_iter conn_iter; 4989 4990 drm_connector_list_iter_begin(dev, &conn_iter); 4991 for_each_intel_connector_iter(connector, &conn_iter) { 4992 struct drm_connector_state *conn_state = connector->base.state; 4993 struct intel_encoder *encoder = 4994 to_intel_encoder(connector->base.encoder); 4995 4996 if (conn_state->crtc) 4997 drm_connector_put(&connector->base); 4998 4999 if (encoder) { 5000 struct intel_crtc *crtc = 5001 to_intel_crtc(encoder->base.crtc); 5002 const struct intel_crtc_state *crtc_state = 5003 to_intel_crtc_state(crtc->base.state); 5004 5005 conn_state->best_encoder = &encoder->base; 5006 conn_state->crtc = &crtc->base; 5007 conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3; 5008 5009 drm_connector_get(&connector->base); 5010 } else { 5011 conn_state->best_encoder = NULL; 5012 conn_state->crtc = NULL; 5013 } 5014 } 5015 drm_connector_list_iter_end(&conn_iter); 5016 } 5017 5018 static int 5019 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state, 5020 struct intel_crtc_state *crtc_state) 5021 { 5022 struct drm_connector *connector = conn_state->connector; 5023 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 5024 const struct drm_display_info *info = &connector->display_info; 5025 int bpp; 5026 5027 switch (conn_state->max_bpc) { 5028 case 6 ... 7: 5029 bpp = 6 * 3; 5030 break; 5031 case 8 ... 9: 5032 bpp = 8 * 3; 5033 break; 5034 case 10 ... 11: 5035 bpp = 10 * 3; 5036 break; 5037 case 12 ... 16: 5038 bpp = 12 * 3; 5039 break; 5040 default: 5041 MISSING_CASE(conn_state->max_bpc); 5042 return -EINVAL; 5043 } 5044 5045 if (bpp < crtc_state->pipe_bpp) { 5046 drm_dbg_kms(&i915->drm, 5047 "[CONNECTOR:%d:%s] Limiting display bpp to %d " 5048 "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n", 5049 connector->base.id, connector->name, 5050 bpp, 3 * info->bpc, 5051 3 * conn_state->max_requested_bpc, 5052 crtc_state->pipe_bpp); 5053 5054 crtc_state->pipe_bpp = bpp; 5055 } 5056 5057 return 0; 5058 } 5059 5060 static int 5061 compute_baseline_pipe_bpp(struct intel_atomic_state *state, 5062 struct intel_crtc *crtc) 5063 { 5064 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5065 struct intel_crtc_state *crtc_state = 5066 intel_atomic_get_new_crtc_state(state, crtc); 5067 struct drm_connector *connector; 5068 struct drm_connector_state *connector_state; 5069 int bpp, i; 5070 5071 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 5072 IS_CHERRYVIEW(dev_priv))) 5073 bpp = 10*3; 5074 else if (DISPLAY_VER(dev_priv) >= 5) 5075 bpp = 12*3; 5076 else 5077 bpp = 8*3; 5078 5079 crtc_state->pipe_bpp = bpp; 5080 5081 /* Clamp display bpp to connector max bpp */ 5082 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5083 int ret; 5084 5085 if (connector_state->crtc != &crtc->base) 5086 continue; 5087 5088 ret = compute_sink_pipe_bpp(connector_state, crtc_state); 5089 if (ret) 5090 return ret; 5091 } 5092 5093 return 0; 5094 } 5095 5096 static void intel_dump_crtc_timings(struct drm_i915_private *i915, 5097 const struct drm_display_mode *mode) 5098 { 5099 drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, " 5100 "type: 0x%x flags: 0x%x\n", 5101 mode->crtc_clock, 5102 mode->crtc_hdisplay, mode->crtc_hsync_start, 5103 mode->crtc_hsync_end, mode->crtc_htotal, 5104 mode->crtc_vdisplay, mode->crtc_vsync_start, 5105 mode->crtc_vsync_end, mode->crtc_vtotal, 5106 mode->type, mode->flags); 5107 } 5108 5109 static void 5110 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config, 5111 const char *id, unsigned int lane_count, 5112 const struct intel_link_m_n *m_n) 5113 { 5114 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); 5115 5116 drm_dbg_kms(&i915->drm, 5117 "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n", 5118 id, lane_count, 5119 m_n->data_m, m_n->data_n, 5120 m_n->link_m, m_n->link_n, m_n->tu); 5121 } 5122 5123 static void 5124 intel_dump_infoframe(struct drm_i915_private *dev_priv, 5125 const union hdmi_infoframe *frame) 5126 { 5127 if (!drm_debug_enabled(DRM_UT_KMS)) 5128 return; 5129 5130 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame); 5131 } 5132 5133 static void 5134 intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv, 5135 const struct drm_dp_vsc_sdp *vsc) 5136 { 5137 if (!drm_debug_enabled(DRM_UT_KMS)) 5138 return; 5139 5140 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc); 5141 } 5142 5143 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x 5144 5145 static const char * const output_type_str[] = { 5146 OUTPUT_TYPE(UNUSED), 5147 OUTPUT_TYPE(ANALOG), 5148 OUTPUT_TYPE(DVO), 5149 OUTPUT_TYPE(SDVO), 5150 OUTPUT_TYPE(LVDS), 5151 OUTPUT_TYPE(TVOUT), 5152 OUTPUT_TYPE(HDMI), 5153 OUTPUT_TYPE(DP), 5154 OUTPUT_TYPE(EDP), 5155 OUTPUT_TYPE(DSI), 5156 OUTPUT_TYPE(DDI), 5157 OUTPUT_TYPE(DP_MST), 5158 }; 5159 5160 #undef OUTPUT_TYPE 5161 5162 static void snprintf_output_types(char *buf, size_t len, 5163 unsigned int output_types) 5164 { 5165 char *str = buf; 5166 int i; 5167 5168 str[0] = '\0'; 5169 5170 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) { 5171 int r; 5172 5173 if ((output_types & BIT(i)) == 0) 5174 continue; 5175 5176 r = snprintf(str, len, "%s%s", 5177 str != buf ? "," : "", output_type_str[i]); 5178 if (r >= len) 5179 break; 5180 str += r; 5181 len -= r; 5182 5183 output_types &= ~BIT(i); 5184 } 5185 5186 WARN_ON_ONCE(output_types != 0); 5187 } 5188 5189 static const char * const output_format_str[] = { 5190 [INTEL_OUTPUT_FORMAT_RGB] = "RGB", 5191 [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0", 5192 [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4", 5193 }; 5194 5195 static const char *output_formats(enum intel_output_format format) 5196 { 5197 if (format >= ARRAY_SIZE(output_format_str)) 5198 return "invalid"; 5199 return output_format_str[format]; 5200 } 5201 5202 static void intel_dump_plane_state(const struct intel_plane_state *plane_state) 5203 { 5204 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 5205 struct drm_i915_private *i915 = to_i915(plane->base.dev); 5206 const struct drm_framebuffer *fb = plane_state->hw.fb; 5207 5208 if (!fb) { 5209 drm_dbg_kms(&i915->drm, 5210 "[PLANE:%d:%s] fb: [NOFB], visible: %s\n", 5211 plane->base.base.id, plane->base.name, 5212 str_yes_no(plane_state->uapi.visible)); 5213 return; 5214 } 5215 5216 drm_dbg_kms(&i915->drm, 5217 "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %p4cc modifier = 0x%llx, visible: %s\n", 5218 plane->base.base.id, plane->base.name, 5219 fb->base.id, fb->width, fb->height, &fb->format->format, 5220 fb->modifier, str_yes_no(plane_state->uapi.visible)); 5221 drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n", 5222 plane_state->hw.rotation, plane_state->scaler_id); 5223 if (plane_state->uapi.visible) 5224 drm_dbg_kms(&i915->drm, 5225 "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n", 5226 DRM_RECT_FP_ARG(&plane_state->uapi.src), 5227 DRM_RECT_ARG(&plane_state->uapi.dst)); 5228 } 5229 5230 static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, 5231 struct intel_atomic_state *state, 5232 const char *context) 5233 { 5234 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 5235 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5236 const struct intel_plane_state *plane_state; 5237 struct intel_plane *plane; 5238 char buf[64]; 5239 int i; 5240 5241 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n", 5242 crtc->base.base.id, crtc->base.name, 5243 str_yes_no(pipe_config->hw.enable), context); 5244 5245 if (!pipe_config->hw.enable) 5246 goto dump_planes; 5247 5248 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types); 5249 drm_dbg_kms(&dev_priv->drm, 5250 "active: %s, output_types: %s (0x%x), output format: %s\n", 5251 str_yes_no(pipe_config->hw.active), 5252 buf, pipe_config->output_types, 5253 output_formats(pipe_config->output_format)); 5254 5255 drm_dbg_kms(&dev_priv->drm, 5256 "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", 5257 transcoder_name(pipe_config->cpu_transcoder), 5258 pipe_config->pipe_bpp, pipe_config->dither); 5259 5260 drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n", 5261 transcoder_name(pipe_config->mst_master_transcoder)); 5262 5263 drm_dbg_kms(&dev_priv->drm, 5264 "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n", 5265 transcoder_name(pipe_config->master_transcoder), 5266 pipe_config->sync_mode_slaves_mask); 5267 5268 drm_dbg_kms(&dev_priv->drm, "bigjoiner: %s, pipes: 0x%x\n", 5269 intel_crtc_is_bigjoiner_slave(pipe_config) ? "slave" : 5270 intel_crtc_is_bigjoiner_master(pipe_config) ? "master" : "no", 5271 pipe_config->bigjoiner_pipes); 5272 5273 drm_dbg_kms(&dev_priv->drm, "splitter: %s, link count %d, overlap %d\n", 5274 str_enabled_disabled(pipe_config->splitter.enable), 5275 pipe_config->splitter.link_count, 5276 pipe_config->splitter.pixel_overlap); 5277 5278 if (pipe_config->has_pch_encoder) 5279 intel_dump_m_n_config(pipe_config, "fdi", 5280 pipe_config->fdi_lanes, 5281 &pipe_config->fdi_m_n); 5282 5283 if (intel_crtc_has_dp_encoder(pipe_config)) { 5284 intel_dump_m_n_config(pipe_config, "dp m_n", 5285 pipe_config->lane_count, 5286 &pipe_config->dp_m_n); 5287 intel_dump_m_n_config(pipe_config, "dp m2_n2", 5288 pipe_config->lane_count, 5289 &pipe_config->dp_m2_n2); 5290 } 5291 5292 drm_dbg_kms(&dev_priv->drm, "framestart delay: %d, MSA timing delay: %d\n", 5293 pipe_config->framestart_delay, pipe_config->msa_timing_delay); 5294 5295 drm_dbg_kms(&dev_priv->drm, 5296 "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n", 5297 pipe_config->has_audio, pipe_config->has_infoframe, 5298 pipe_config->infoframes.enable); 5299 5300 if (pipe_config->infoframes.enable & 5301 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) 5302 drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n", 5303 pipe_config->infoframes.gcp); 5304 if (pipe_config->infoframes.enable & 5305 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) 5306 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi); 5307 if (pipe_config->infoframes.enable & 5308 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD)) 5309 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd); 5310 if (pipe_config->infoframes.enable & 5311 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR)) 5312 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi); 5313 if (pipe_config->infoframes.enable & 5314 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) 5315 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); 5316 if (pipe_config->infoframes.enable & 5317 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA)) 5318 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); 5319 if (pipe_config->infoframes.enable & 5320 intel_hdmi_infoframe_enable(DP_SDP_VSC)) 5321 intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc); 5322 5323 drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n", 5324 str_yes_no(pipe_config->vrr.enable), 5325 pipe_config->vrr.vmin, pipe_config->vrr.vmax, 5326 pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband, 5327 pipe_config->vrr.flipline, 5328 intel_vrr_vmin_vblank_start(pipe_config), 5329 intel_vrr_vmax_vblank_start(pipe_config)); 5330 5331 drm_dbg_kms(&dev_priv->drm, "requested mode: " DRM_MODE_FMT "\n", 5332 DRM_MODE_ARG(&pipe_config->hw.mode)); 5333 drm_dbg_kms(&dev_priv->drm, "adjusted mode: " DRM_MODE_FMT "\n", 5334 DRM_MODE_ARG(&pipe_config->hw.adjusted_mode)); 5335 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode); 5336 drm_dbg_kms(&dev_priv->drm, "pipe mode: " DRM_MODE_FMT "\n", 5337 DRM_MODE_ARG(&pipe_config->hw.pipe_mode)); 5338 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode); 5339 drm_dbg_kms(&dev_priv->drm, 5340 "port clock: %d, pipe src: " DRM_RECT_FMT ", pixel rate %d\n", 5341 pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src), 5342 pipe_config->pixel_rate); 5343 5344 drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n", 5345 pipe_config->linetime, pipe_config->ips_linetime); 5346 5347 if (DISPLAY_VER(dev_priv) >= 9) 5348 drm_dbg_kms(&dev_priv->drm, 5349 "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", 5350 crtc->num_scalers, 5351 pipe_config->scaler_state.scaler_users, 5352 pipe_config->scaler_state.scaler_id); 5353 5354 if (HAS_GMCH(dev_priv)) 5355 drm_dbg_kms(&dev_priv->drm, 5356 "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", 5357 pipe_config->gmch_pfit.control, 5358 pipe_config->gmch_pfit.pgm_ratios, 5359 pipe_config->gmch_pfit.lvds_border_bits); 5360 else 5361 drm_dbg_kms(&dev_priv->drm, 5362 "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n", 5363 DRM_RECT_ARG(&pipe_config->pch_pfit.dst), 5364 str_enabled_disabled(pipe_config->pch_pfit.enabled), 5365 str_yes_no(pipe_config->pch_pfit.force_thru)); 5366 5367 drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i, drrs: %i\n", 5368 pipe_config->ips_enabled, pipe_config->double_wide, 5369 pipe_config->has_drrs); 5370 5371 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state); 5372 5373 if (IS_CHERRYVIEW(dev_priv)) 5374 drm_dbg_kms(&dev_priv->drm, 5375 "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", 5376 pipe_config->cgm_mode, pipe_config->gamma_mode, 5377 pipe_config->gamma_enable, pipe_config->csc_enable); 5378 else 5379 drm_dbg_kms(&dev_priv->drm, 5380 "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", 5381 pipe_config->csc_mode, pipe_config->gamma_mode, 5382 pipe_config->gamma_enable, pipe_config->csc_enable); 5383 5384 drm_dbg_kms(&dev_priv->drm, "degamma lut: %d entries, gamma lut: %d entries\n", 5385 pipe_config->hw.degamma_lut ? 5386 drm_color_lut_size(pipe_config->hw.degamma_lut) : 0, 5387 pipe_config->hw.gamma_lut ? 5388 drm_color_lut_size(pipe_config->hw.gamma_lut) : 0); 5389 5390 dump_planes: 5391 if (!state) 5392 return; 5393 5394 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 5395 if (plane->pipe == crtc->pipe) 5396 intel_dump_plane_state(plane_state); 5397 } 5398 } 5399 5400 static bool check_digital_port_conflicts(struct intel_atomic_state *state) 5401 { 5402 struct drm_device *dev = state->base.dev; 5403 struct drm_connector *connector; 5404 struct drm_connector_list_iter conn_iter; 5405 unsigned int used_ports = 0; 5406 unsigned int used_mst_ports = 0; 5407 bool ret = true; 5408 5409 /* 5410 * We're going to peek into connector->state, 5411 * hence connection_mutex must be held. 5412 */ 5413 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex); 5414 5415 /* 5416 * Walk the connector list instead of the encoder 5417 * list to detect the problem on ddi platforms 5418 * where there's just one encoder per digital port. 5419 */ 5420 drm_connector_list_iter_begin(dev, &conn_iter); 5421 drm_for_each_connector_iter(connector, &conn_iter) { 5422 struct drm_connector_state *connector_state; 5423 struct intel_encoder *encoder; 5424 5425 connector_state = 5426 drm_atomic_get_new_connector_state(&state->base, 5427 connector); 5428 if (!connector_state) 5429 connector_state = connector->state; 5430 5431 if (!connector_state->best_encoder) 5432 continue; 5433 5434 encoder = to_intel_encoder(connector_state->best_encoder); 5435 5436 drm_WARN_ON(dev, !connector_state->crtc); 5437 5438 switch (encoder->type) { 5439 case INTEL_OUTPUT_DDI: 5440 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev)))) 5441 break; 5442 fallthrough; 5443 case INTEL_OUTPUT_DP: 5444 case INTEL_OUTPUT_HDMI: 5445 case INTEL_OUTPUT_EDP: 5446 /* the same port mustn't appear more than once */ 5447 if (used_ports & BIT(encoder->port)) 5448 ret = false; 5449 5450 used_ports |= BIT(encoder->port); 5451 break; 5452 case INTEL_OUTPUT_DP_MST: 5453 used_mst_ports |= 5454 1 << encoder->port; 5455 break; 5456 default: 5457 break; 5458 } 5459 } 5460 drm_connector_list_iter_end(&conn_iter); 5461 5462 /* can't mix MST and SST/HDMI on the same port */ 5463 if (used_ports & used_mst_ports) 5464 return false; 5465 5466 return ret; 5467 } 5468 5469 static void 5470 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state, 5471 struct intel_crtc *crtc) 5472 { 5473 struct intel_crtc_state *crtc_state = 5474 intel_atomic_get_new_crtc_state(state, crtc); 5475 5476 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 5477 5478 drm_property_replace_blob(&crtc_state->hw.degamma_lut, 5479 crtc_state->uapi.degamma_lut); 5480 drm_property_replace_blob(&crtc_state->hw.gamma_lut, 5481 crtc_state->uapi.gamma_lut); 5482 drm_property_replace_blob(&crtc_state->hw.ctm, 5483 crtc_state->uapi.ctm); 5484 } 5485 5486 static void 5487 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state, 5488 struct intel_crtc *crtc) 5489 { 5490 struct intel_crtc_state *crtc_state = 5491 intel_atomic_get_new_crtc_state(state, crtc); 5492 5493 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 5494 5495 crtc_state->hw.enable = crtc_state->uapi.enable; 5496 crtc_state->hw.active = crtc_state->uapi.active; 5497 drm_mode_copy(&crtc_state->hw.mode, 5498 &crtc_state->uapi.mode); 5499 drm_mode_copy(&crtc_state->hw.adjusted_mode, 5500 &crtc_state->uapi.adjusted_mode); 5501 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter; 5502 5503 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 5504 } 5505 5506 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state) 5507 { 5508 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 5509 return; 5510 5511 crtc_state->uapi.enable = crtc_state->hw.enable; 5512 crtc_state->uapi.active = crtc_state->hw.active; 5513 drm_WARN_ON(crtc_state->uapi.crtc->dev, 5514 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0); 5515 5516 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode; 5517 crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter; 5518 5519 drm_property_replace_blob(&crtc_state->uapi.degamma_lut, 5520 crtc_state->hw.degamma_lut); 5521 drm_property_replace_blob(&crtc_state->uapi.gamma_lut, 5522 crtc_state->hw.gamma_lut); 5523 drm_property_replace_blob(&crtc_state->uapi.ctm, 5524 crtc_state->hw.ctm); 5525 } 5526 5527 static void 5528 copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state, 5529 struct intel_crtc *slave_crtc) 5530 { 5531 struct intel_crtc_state *slave_crtc_state = 5532 intel_atomic_get_new_crtc_state(state, slave_crtc); 5533 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 5534 const struct intel_crtc_state *master_crtc_state = 5535 intel_atomic_get_new_crtc_state(state, master_crtc); 5536 5537 drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut, 5538 master_crtc_state->hw.degamma_lut); 5539 drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut, 5540 master_crtc_state->hw.gamma_lut); 5541 drm_property_replace_blob(&slave_crtc_state->hw.ctm, 5542 master_crtc_state->hw.ctm); 5543 5544 slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed; 5545 } 5546 5547 static int 5548 copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state, 5549 struct intel_crtc *slave_crtc) 5550 { 5551 struct intel_crtc_state *slave_crtc_state = 5552 intel_atomic_get_new_crtc_state(state, slave_crtc); 5553 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 5554 const struct intel_crtc_state *master_crtc_state = 5555 intel_atomic_get_new_crtc_state(state, master_crtc); 5556 struct intel_crtc_state *saved_state; 5557 5558 WARN_ON(master_crtc_state->bigjoiner_pipes != 5559 slave_crtc_state->bigjoiner_pipes); 5560 5561 saved_state = kmemdup(master_crtc_state, sizeof(*saved_state), GFP_KERNEL); 5562 if (!saved_state) 5563 return -ENOMEM; 5564 5565 /* preserve some things from the slave's original crtc state */ 5566 saved_state->uapi = slave_crtc_state->uapi; 5567 saved_state->scaler_state = slave_crtc_state->scaler_state; 5568 saved_state->shared_dpll = slave_crtc_state->shared_dpll; 5569 saved_state->dpll_hw_state = slave_crtc_state->dpll_hw_state; 5570 saved_state->crc_enabled = slave_crtc_state->crc_enabled; 5571 5572 intel_crtc_free_hw_state(slave_crtc_state); 5573 memcpy(slave_crtc_state, saved_state, sizeof(*slave_crtc_state)); 5574 kfree(saved_state); 5575 5576 /* Re-init hw state */ 5577 memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw)); 5578 slave_crtc_state->hw.enable = master_crtc_state->hw.enable; 5579 slave_crtc_state->hw.active = master_crtc_state->hw.active; 5580 drm_mode_copy(&slave_crtc_state->hw.mode, 5581 &master_crtc_state->hw.mode); 5582 drm_mode_copy(&slave_crtc_state->hw.pipe_mode, 5583 &master_crtc_state->hw.pipe_mode); 5584 drm_mode_copy(&slave_crtc_state->hw.adjusted_mode, 5585 &master_crtc_state->hw.adjusted_mode); 5586 slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter; 5587 5588 copy_bigjoiner_crtc_state_nomodeset(state, slave_crtc); 5589 5590 slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed; 5591 slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed; 5592 slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed; 5593 5594 WARN_ON(master_crtc_state->bigjoiner_pipes != 5595 slave_crtc_state->bigjoiner_pipes); 5596 5597 return 0; 5598 } 5599 5600 static int 5601 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state, 5602 struct intel_crtc *crtc) 5603 { 5604 struct intel_crtc_state *crtc_state = 5605 intel_atomic_get_new_crtc_state(state, crtc); 5606 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5607 struct intel_crtc_state *saved_state; 5608 5609 saved_state = intel_crtc_state_alloc(crtc); 5610 if (!saved_state) 5611 return -ENOMEM; 5612 5613 /* free the old crtc_state->hw members */ 5614 intel_crtc_free_hw_state(crtc_state); 5615 5616 /* FIXME: before the switch to atomic started, a new pipe_config was 5617 * kzalloc'd. Code that depends on any field being zero should be 5618 * fixed, so that the crtc_state can be safely duplicated. For now, 5619 * only fields that are know to not cause problems are preserved. */ 5620 5621 saved_state->uapi = crtc_state->uapi; 5622 saved_state->scaler_state = crtc_state->scaler_state; 5623 saved_state->shared_dpll = crtc_state->shared_dpll; 5624 saved_state->dpll_hw_state = crtc_state->dpll_hw_state; 5625 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, 5626 sizeof(saved_state->icl_port_dplls)); 5627 saved_state->crc_enabled = crtc_state->crc_enabled; 5628 if (IS_G4X(dev_priv) || 5629 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5630 saved_state->wm = crtc_state->wm; 5631 5632 memcpy(crtc_state, saved_state, sizeof(*crtc_state)); 5633 kfree(saved_state); 5634 5635 intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc); 5636 5637 return 0; 5638 } 5639 5640 static int 5641 intel_modeset_pipe_config(struct intel_atomic_state *state, 5642 struct intel_crtc *crtc) 5643 { 5644 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 5645 struct intel_crtc_state *crtc_state = 5646 intel_atomic_get_new_crtc_state(state, crtc); 5647 struct drm_connector *connector; 5648 struct drm_connector_state *connector_state; 5649 int pipe_src_w, pipe_src_h; 5650 int base_bpp, ret, i; 5651 bool retry = true; 5652 5653 crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe; 5654 5655 crtc_state->framestart_delay = 1; 5656 5657 /* 5658 * Sanitize sync polarity flags based on requested ones. If neither 5659 * positive or negative polarity is requested, treat this as meaning 5660 * negative polarity. 5661 */ 5662 if (!(crtc_state->hw.adjusted_mode.flags & 5663 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) 5664 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; 5665 5666 if (!(crtc_state->hw.adjusted_mode.flags & 5667 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 5668 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; 5669 5670 ret = compute_baseline_pipe_bpp(state, crtc); 5671 if (ret) 5672 return ret; 5673 5674 base_bpp = crtc_state->pipe_bpp; 5675 5676 /* 5677 * Determine the real pipe dimensions. Note that stereo modes can 5678 * increase the actual pipe size due to the frame doubling and 5679 * insertion of additional space for blanks between the frame. This 5680 * is stored in the crtc timings. We use the requested mode to do this 5681 * computation to clearly distinguish it from the adjusted mode, which 5682 * can be changed by the connectors in the below retry loop. 5683 */ 5684 drm_mode_get_hv_timing(&crtc_state->hw.mode, 5685 &pipe_src_w, &pipe_src_h); 5686 drm_rect_init(&crtc_state->pipe_src, 0, 0, 5687 pipe_src_w, pipe_src_h); 5688 5689 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5690 struct intel_encoder *encoder = 5691 to_intel_encoder(connector_state->best_encoder); 5692 5693 if (connector_state->crtc != &crtc->base) 5694 continue; 5695 5696 if (!check_single_encoder_cloning(state, crtc, encoder)) { 5697 drm_dbg_kms(&i915->drm, 5698 "[ENCODER:%d:%s] rejecting invalid cloning configuration\n", 5699 encoder->base.base.id, encoder->base.name); 5700 return -EINVAL; 5701 } 5702 5703 /* 5704 * Determine output_types before calling the .compute_config() 5705 * hooks so that the hooks can use this information safely. 5706 */ 5707 if (encoder->compute_output_type) 5708 crtc_state->output_types |= 5709 BIT(encoder->compute_output_type(encoder, crtc_state, 5710 connector_state)); 5711 else 5712 crtc_state->output_types |= BIT(encoder->type); 5713 } 5714 5715 encoder_retry: 5716 /* Ensure the port clock defaults are reset when retrying. */ 5717 crtc_state->port_clock = 0; 5718 crtc_state->pixel_multiplier = 1; 5719 5720 /* Fill in default crtc timings, allow encoders to overwrite them. */ 5721 drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode, 5722 CRTC_STEREO_DOUBLE); 5723 5724 /* Pass our mode to the connectors and the CRTC to give them a chance to 5725 * adjust it according to limitations or connector properties, and also 5726 * a chance to reject the mode entirely. 5727 */ 5728 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5729 struct intel_encoder *encoder = 5730 to_intel_encoder(connector_state->best_encoder); 5731 5732 if (connector_state->crtc != &crtc->base) 5733 continue; 5734 5735 ret = encoder->compute_config(encoder, crtc_state, 5736 connector_state); 5737 if (ret == -EDEADLK) 5738 return ret; 5739 if (ret < 0) { 5740 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n", 5741 encoder->base.base.id, encoder->base.name, ret); 5742 return ret; 5743 } 5744 } 5745 5746 /* Set default port clock if not overwritten by the encoder. Needs to be 5747 * done afterwards in case the encoder adjusts the mode. */ 5748 if (!crtc_state->port_clock) 5749 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock 5750 * crtc_state->pixel_multiplier; 5751 5752 ret = intel_crtc_compute_config(state, crtc); 5753 if (ret == -EDEADLK) 5754 return ret; 5755 if (ret == -EAGAIN) { 5756 if (drm_WARN(&i915->drm, !retry, 5757 "[CRTC:%d:%s] loop in pipe configuration computation\n", 5758 crtc->base.base.id, crtc->base.name)) 5759 return -EINVAL; 5760 5761 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] bw constrained, retrying\n", 5762 crtc->base.base.id, crtc->base.name); 5763 retry = false; 5764 goto encoder_retry; 5765 } 5766 if (ret < 0) { 5767 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n", 5768 crtc->base.base.id, crtc->base.name, ret); 5769 return ret; 5770 } 5771 5772 /* Dithering seems to not pass-through bits correctly when it should, so 5773 * only enable it on 6bpc panels and when its not a compliance 5774 * test requesting 6bpc video pattern. 5775 */ 5776 crtc_state->dither = (crtc_state->pipe_bpp == 6*3) && 5777 !crtc_state->dither_force_disable; 5778 drm_dbg_kms(&i915->drm, 5779 "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n", 5780 crtc->base.base.id, crtc->base.name, 5781 base_bpp, crtc_state->pipe_bpp, crtc_state->dither); 5782 5783 return 0; 5784 } 5785 5786 static int 5787 intel_modeset_pipe_config_late(struct intel_atomic_state *state, 5788 struct intel_crtc *crtc) 5789 { 5790 struct intel_crtc_state *crtc_state = 5791 intel_atomic_get_new_crtc_state(state, crtc); 5792 struct drm_connector_state *conn_state; 5793 struct drm_connector *connector; 5794 int i; 5795 5796 intel_bigjoiner_adjust_pipe_src(crtc_state); 5797 5798 for_each_new_connector_in_state(&state->base, connector, 5799 conn_state, i) { 5800 struct intel_encoder *encoder = 5801 to_intel_encoder(conn_state->best_encoder); 5802 int ret; 5803 5804 if (conn_state->crtc != &crtc->base || 5805 !encoder->compute_config_late) 5806 continue; 5807 5808 ret = encoder->compute_config_late(encoder, crtc_state, 5809 conn_state); 5810 if (ret) 5811 return ret; 5812 } 5813 5814 return 0; 5815 } 5816 5817 bool intel_fuzzy_clock_check(int clock1, int clock2) 5818 { 5819 int diff; 5820 5821 if (clock1 == clock2) 5822 return true; 5823 5824 if (!clock1 || !clock2) 5825 return false; 5826 5827 diff = abs(clock1 - clock2); 5828 5829 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) 5830 return true; 5831 5832 return false; 5833 } 5834 5835 static bool 5836 intel_compare_m_n(unsigned int m, unsigned int n, 5837 unsigned int m2, unsigned int n2, 5838 bool exact) 5839 { 5840 if (m == m2 && n == n2) 5841 return true; 5842 5843 if (exact || !m || !n || !m2 || !n2) 5844 return false; 5845 5846 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); 5847 5848 if (n > n2) { 5849 while (n > n2) { 5850 m2 <<= 1; 5851 n2 <<= 1; 5852 } 5853 } else if (n < n2) { 5854 while (n < n2) { 5855 m <<= 1; 5856 n <<= 1; 5857 } 5858 } 5859 5860 if (n != n2) 5861 return false; 5862 5863 return intel_fuzzy_clock_check(m, m2); 5864 } 5865 5866 static bool 5867 intel_compare_link_m_n(const struct intel_link_m_n *m_n, 5868 const struct intel_link_m_n *m2_n2, 5869 bool exact) 5870 { 5871 return m_n->tu == m2_n2->tu && 5872 intel_compare_m_n(m_n->data_m, m_n->data_n, 5873 m2_n2->data_m, m2_n2->data_n, exact) && 5874 intel_compare_m_n(m_n->link_m, m_n->link_n, 5875 m2_n2->link_m, m2_n2->link_n, exact); 5876 } 5877 5878 static bool 5879 intel_compare_infoframe(const union hdmi_infoframe *a, 5880 const union hdmi_infoframe *b) 5881 { 5882 return memcmp(a, b, sizeof(*a)) == 0; 5883 } 5884 5885 static bool 5886 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a, 5887 const struct drm_dp_vsc_sdp *b) 5888 { 5889 return memcmp(a, b, sizeof(*a)) == 0; 5890 } 5891 5892 static void 5893 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv, 5894 bool fastset, const char *name, 5895 const union hdmi_infoframe *a, 5896 const union hdmi_infoframe *b) 5897 { 5898 if (fastset) { 5899 if (!drm_debug_enabled(DRM_UT_KMS)) 5900 return; 5901 5902 drm_dbg_kms(&dev_priv->drm, 5903 "fastset mismatch in %s infoframe\n", name); 5904 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 5905 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a); 5906 drm_dbg_kms(&dev_priv->drm, "found:\n"); 5907 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b); 5908 } else { 5909 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name); 5910 drm_err(&dev_priv->drm, "expected:\n"); 5911 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a); 5912 drm_err(&dev_priv->drm, "found:\n"); 5913 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b); 5914 } 5915 } 5916 5917 static void 5918 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv, 5919 bool fastset, const char *name, 5920 const struct drm_dp_vsc_sdp *a, 5921 const struct drm_dp_vsc_sdp *b) 5922 { 5923 if (fastset) { 5924 if (!drm_debug_enabled(DRM_UT_KMS)) 5925 return; 5926 5927 drm_dbg_kms(&dev_priv->drm, 5928 "fastset mismatch in %s dp sdp\n", name); 5929 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 5930 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a); 5931 drm_dbg_kms(&dev_priv->drm, "found:\n"); 5932 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b); 5933 } else { 5934 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name); 5935 drm_err(&dev_priv->drm, "expected:\n"); 5936 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a); 5937 drm_err(&dev_priv->drm, "found:\n"); 5938 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b); 5939 } 5940 } 5941 5942 static void __printf(4, 5) 5943 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc, 5944 const char *name, const char *format, ...) 5945 { 5946 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 5947 struct va_format vaf; 5948 va_list args; 5949 5950 va_start(args, format); 5951 vaf.fmt = format; 5952 vaf.va = &args; 5953 5954 if (fastset) 5955 drm_dbg_kms(&i915->drm, 5956 "[CRTC:%d:%s] fastset mismatch in %s %pV\n", 5957 crtc->base.base.id, crtc->base.name, name, &vaf); 5958 else 5959 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n", 5960 crtc->base.base.id, crtc->base.name, name, &vaf); 5961 5962 va_end(args); 5963 } 5964 5965 static bool fastboot_enabled(struct drm_i915_private *dev_priv) 5966 { 5967 if (dev_priv->params.fastboot != -1) 5968 return dev_priv->params.fastboot; 5969 5970 /* Enable fastboot by default on Skylake and newer */ 5971 if (DISPLAY_VER(dev_priv) >= 9) 5972 return true; 5973 5974 /* Enable fastboot by default on VLV and CHV */ 5975 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5976 return true; 5977 5978 /* Disabled by default on all others */ 5979 return false; 5980 } 5981 5982 static bool 5983 intel_pipe_config_compare(const struct intel_crtc_state *current_config, 5984 const struct intel_crtc_state *pipe_config, 5985 bool fastset) 5986 { 5987 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev); 5988 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 5989 bool ret = true; 5990 u32 bp_gamma = 0; 5991 bool fixup_inherited = fastset && 5992 current_config->inherited && !pipe_config->inherited; 5993 5994 if (fixup_inherited && !fastboot_enabled(dev_priv)) { 5995 drm_dbg_kms(&dev_priv->drm, 5996 "initial modeset and fastboot not set\n"); 5997 ret = false; 5998 } 5999 6000 #define PIPE_CONF_CHECK_X(name) do { \ 6001 if (current_config->name != pipe_config->name) { \ 6002 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6003 "(expected 0x%08x, found 0x%08x)", \ 6004 current_config->name, \ 6005 pipe_config->name); \ 6006 ret = false; \ 6007 } \ 6008 } while (0) 6009 6010 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \ 6011 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \ 6012 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6013 "(expected 0x%08x, found 0x%08x)", \ 6014 current_config->name & (mask), \ 6015 pipe_config->name & (mask)); \ 6016 ret = false; \ 6017 } \ 6018 } while (0) 6019 6020 #define PIPE_CONF_CHECK_I(name) do { \ 6021 if (current_config->name != pipe_config->name) { \ 6022 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6023 "(expected %i, found %i)", \ 6024 current_config->name, \ 6025 pipe_config->name); \ 6026 ret = false; \ 6027 } \ 6028 } while (0) 6029 6030 #define PIPE_CONF_CHECK_BOOL(name) do { \ 6031 if (current_config->name != pipe_config->name) { \ 6032 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6033 "(expected %s, found %s)", \ 6034 str_yes_no(current_config->name), \ 6035 str_yes_no(pipe_config->name)); \ 6036 ret = false; \ 6037 } \ 6038 } while (0) 6039 6040 /* 6041 * Checks state where we only read out the enabling, but not the entire 6042 * state itself (like full infoframes or ELD for audio). These states 6043 * require a full modeset on bootup to fix up. 6044 */ 6045 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \ 6046 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \ 6047 PIPE_CONF_CHECK_BOOL(name); \ 6048 } else { \ 6049 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6050 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \ 6051 str_yes_no(current_config->name), \ 6052 str_yes_no(pipe_config->name)); \ 6053 ret = false; \ 6054 } \ 6055 } while (0) 6056 6057 #define PIPE_CONF_CHECK_P(name) do { \ 6058 if (current_config->name != pipe_config->name) { \ 6059 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6060 "(expected %p, found %p)", \ 6061 current_config->name, \ 6062 pipe_config->name); \ 6063 ret = false; \ 6064 } \ 6065 } while (0) 6066 6067 #define PIPE_CONF_CHECK_M_N(name) do { \ 6068 if (!intel_compare_link_m_n(¤t_config->name, \ 6069 &pipe_config->name,\ 6070 !fastset)) { \ 6071 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6072 "(expected tu %i data %i/%i link %i/%i, " \ 6073 "found tu %i, data %i/%i link %i/%i)", \ 6074 current_config->name.tu, \ 6075 current_config->name.data_m, \ 6076 current_config->name.data_n, \ 6077 current_config->name.link_m, \ 6078 current_config->name.link_n, \ 6079 pipe_config->name.tu, \ 6080 pipe_config->name.data_m, \ 6081 pipe_config->name.data_n, \ 6082 pipe_config->name.link_m, \ 6083 pipe_config->name.link_n); \ 6084 ret = false; \ 6085 } \ 6086 } while (0) 6087 6088 #define PIPE_CONF_CHECK_TIMINGS(name) do { \ 6089 PIPE_CONF_CHECK_I(name.crtc_hdisplay); \ 6090 PIPE_CONF_CHECK_I(name.crtc_htotal); \ 6091 PIPE_CONF_CHECK_I(name.crtc_hblank_start); \ 6092 PIPE_CONF_CHECK_I(name.crtc_hblank_end); \ 6093 PIPE_CONF_CHECK_I(name.crtc_hsync_start); \ 6094 PIPE_CONF_CHECK_I(name.crtc_hsync_end); \ 6095 PIPE_CONF_CHECK_I(name.crtc_vdisplay); \ 6096 PIPE_CONF_CHECK_I(name.crtc_vtotal); \ 6097 PIPE_CONF_CHECK_I(name.crtc_vblank_start); \ 6098 PIPE_CONF_CHECK_I(name.crtc_vblank_end); \ 6099 PIPE_CONF_CHECK_I(name.crtc_vsync_start); \ 6100 PIPE_CONF_CHECK_I(name.crtc_vsync_end); \ 6101 } while (0) 6102 6103 #define PIPE_CONF_CHECK_RECT(name) do { \ 6104 PIPE_CONF_CHECK_I(name.x1); \ 6105 PIPE_CONF_CHECK_I(name.x2); \ 6106 PIPE_CONF_CHECK_I(name.y1); \ 6107 PIPE_CONF_CHECK_I(name.y2); \ 6108 } while (0) 6109 6110 /* This is required for BDW+ where there is only one set of registers for 6111 * switching between high and low RR. 6112 * This macro can be used whenever a comparison has to be made between one 6113 * hw state and multiple sw state variables. 6114 */ 6115 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \ 6116 if (!intel_compare_link_m_n(¤t_config->name, \ 6117 &pipe_config->name, !fastset) && \ 6118 !intel_compare_link_m_n(¤t_config->alt_name, \ 6119 &pipe_config->name, !fastset)) { \ 6120 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6121 "(expected tu %i data %i/%i link %i/%i, " \ 6122 "or tu %i data %i/%i link %i/%i, " \ 6123 "found tu %i, data %i/%i link %i/%i)", \ 6124 current_config->name.tu, \ 6125 current_config->name.data_m, \ 6126 current_config->name.data_n, \ 6127 current_config->name.link_m, \ 6128 current_config->name.link_n, \ 6129 current_config->alt_name.tu, \ 6130 current_config->alt_name.data_m, \ 6131 current_config->alt_name.data_n, \ 6132 current_config->alt_name.link_m, \ 6133 current_config->alt_name.link_n, \ 6134 pipe_config->name.tu, \ 6135 pipe_config->name.data_m, \ 6136 pipe_config->name.data_n, \ 6137 pipe_config->name.link_m, \ 6138 pipe_config->name.link_n); \ 6139 ret = false; \ 6140 } \ 6141 } while (0) 6142 6143 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \ 6144 if ((current_config->name ^ pipe_config->name) & (mask)) { \ 6145 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6146 "(%x) (expected %i, found %i)", \ 6147 (mask), \ 6148 current_config->name & (mask), \ 6149 pipe_config->name & (mask)); \ 6150 ret = false; \ 6151 } \ 6152 } while (0) 6153 6154 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \ 6155 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ 6156 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6157 "(expected %i, found %i)", \ 6158 current_config->name, \ 6159 pipe_config->name); \ 6160 ret = false; \ 6161 } \ 6162 } while (0) 6163 6164 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \ 6165 if (!intel_compare_infoframe(¤t_config->infoframes.name, \ 6166 &pipe_config->infoframes.name)) { \ 6167 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \ 6168 ¤t_config->infoframes.name, \ 6169 &pipe_config->infoframes.name); \ 6170 ret = false; \ 6171 } \ 6172 } while (0) 6173 6174 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \ 6175 if (!current_config->has_psr && !pipe_config->has_psr && \ 6176 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \ 6177 &pipe_config->infoframes.name)) { \ 6178 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \ 6179 ¤t_config->infoframes.name, \ 6180 &pipe_config->infoframes.name); \ 6181 ret = false; \ 6182 } \ 6183 } while (0) 6184 6185 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \ 6186 if (current_config->name1 != pipe_config->name1) { \ 6187 pipe_config_mismatch(fastset, crtc, __stringify(name1), \ 6188 "(expected %i, found %i, won't compare lut values)", \ 6189 current_config->name1, \ 6190 pipe_config->name1); \ 6191 ret = false;\ 6192 } else { \ 6193 if (!intel_color_lut_equal(current_config->name2, \ 6194 pipe_config->name2, pipe_config->name1, \ 6195 bit_precision)) { \ 6196 pipe_config_mismatch(fastset, crtc, __stringify(name2), \ 6197 "hw_state doesn't match sw_state"); \ 6198 ret = false; \ 6199 } \ 6200 } \ 6201 } while (0) 6202 6203 #define PIPE_CONF_QUIRK(quirk) \ 6204 ((current_config->quirks | pipe_config->quirks) & (quirk)) 6205 6206 PIPE_CONF_CHECK_I(hw.enable); 6207 PIPE_CONF_CHECK_I(hw.active); 6208 6209 PIPE_CONF_CHECK_I(cpu_transcoder); 6210 PIPE_CONF_CHECK_I(mst_master_transcoder); 6211 6212 PIPE_CONF_CHECK_BOOL(has_pch_encoder); 6213 PIPE_CONF_CHECK_I(fdi_lanes); 6214 PIPE_CONF_CHECK_M_N(fdi_m_n); 6215 6216 PIPE_CONF_CHECK_I(lane_count); 6217 PIPE_CONF_CHECK_X(lane_lat_optim_mask); 6218 6219 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) { 6220 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); 6221 } else { 6222 PIPE_CONF_CHECK_M_N(dp_m_n); 6223 PIPE_CONF_CHECK_M_N(dp_m2_n2); 6224 } 6225 6226 PIPE_CONF_CHECK_X(output_types); 6227 6228 PIPE_CONF_CHECK_I(framestart_delay); 6229 PIPE_CONF_CHECK_I(msa_timing_delay); 6230 6231 PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode); 6232 PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode); 6233 6234 PIPE_CONF_CHECK_I(pixel_multiplier); 6235 6236 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6237 DRM_MODE_FLAG_INTERLACE); 6238 6239 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { 6240 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6241 DRM_MODE_FLAG_PHSYNC); 6242 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6243 DRM_MODE_FLAG_NHSYNC); 6244 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6245 DRM_MODE_FLAG_PVSYNC); 6246 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6247 DRM_MODE_FLAG_NVSYNC); 6248 } 6249 6250 PIPE_CONF_CHECK_I(output_format); 6251 PIPE_CONF_CHECK_BOOL(has_hdmi_sink); 6252 if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || 6253 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 6254 PIPE_CONF_CHECK_BOOL(limited_color_range); 6255 6256 PIPE_CONF_CHECK_BOOL(hdmi_scrambling); 6257 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio); 6258 PIPE_CONF_CHECK_BOOL(has_infoframe); 6259 PIPE_CONF_CHECK_BOOL(fec_enable); 6260 6261 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio); 6262 6263 PIPE_CONF_CHECK_X(gmch_pfit.control); 6264 /* pfit ratios are autocomputed by the hw on gen4+ */ 6265 if (DISPLAY_VER(dev_priv) < 4) 6266 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); 6267 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); 6268 6269 /* 6270 * Changing the EDP transcoder input mux 6271 * (A_ONOFF vs. A_ON) requires a full modeset. 6272 */ 6273 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru); 6274 6275 if (!fastset) { 6276 PIPE_CONF_CHECK_RECT(pipe_src); 6277 6278 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled); 6279 PIPE_CONF_CHECK_RECT(pch_pfit.dst); 6280 6281 PIPE_CONF_CHECK_I(scaler_state.scaler_id); 6282 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate); 6283 6284 PIPE_CONF_CHECK_X(gamma_mode); 6285 if (IS_CHERRYVIEW(dev_priv)) 6286 PIPE_CONF_CHECK_X(cgm_mode); 6287 else 6288 PIPE_CONF_CHECK_X(csc_mode); 6289 PIPE_CONF_CHECK_BOOL(gamma_enable); 6290 PIPE_CONF_CHECK_BOOL(csc_enable); 6291 6292 PIPE_CONF_CHECK_I(linetime); 6293 PIPE_CONF_CHECK_I(ips_linetime); 6294 6295 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config); 6296 if (bp_gamma) 6297 PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma); 6298 6299 if (current_config->active_planes) { 6300 PIPE_CONF_CHECK_BOOL(has_psr); 6301 PIPE_CONF_CHECK_BOOL(has_psr2); 6302 PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); 6303 PIPE_CONF_CHECK_I(dc3co_exitline); 6304 } 6305 } 6306 6307 PIPE_CONF_CHECK_BOOL(double_wide); 6308 6309 if (dev_priv->dpll.mgr) { 6310 PIPE_CONF_CHECK_P(shared_dpll); 6311 6312 PIPE_CONF_CHECK_X(dpll_hw_state.dpll); 6313 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); 6314 PIPE_CONF_CHECK_X(dpll_hw_state.fp0); 6315 PIPE_CONF_CHECK_X(dpll_hw_state.fp1); 6316 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); 6317 PIPE_CONF_CHECK_X(dpll_hw_state.spll); 6318 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); 6319 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); 6320 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); 6321 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); 6322 PIPE_CONF_CHECK_X(dpll_hw_state.div0); 6323 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); 6324 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); 6325 PIPE_CONF_CHECK_X(dpll_hw_state.pll0); 6326 PIPE_CONF_CHECK_X(dpll_hw_state.pll1); 6327 PIPE_CONF_CHECK_X(dpll_hw_state.pll2); 6328 PIPE_CONF_CHECK_X(dpll_hw_state.pll3); 6329 PIPE_CONF_CHECK_X(dpll_hw_state.pll6); 6330 PIPE_CONF_CHECK_X(dpll_hw_state.pll8); 6331 PIPE_CONF_CHECK_X(dpll_hw_state.pll9); 6332 PIPE_CONF_CHECK_X(dpll_hw_state.pll10); 6333 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); 6334 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl); 6335 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1); 6336 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl); 6337 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0); 6338 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1); 6339 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf); 6340 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock); 6341 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc); 6342 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias); 6343 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias); 6344 } 6345 6346 PIPE_CONF_CHECK_X(dsi_pll.ctrl); 6347 PIPE_CONF_CHECK_X(dsi_pll.div); 6348 6349 if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5) 6350 PIPE_CONF_CHECK_I(pipe_bpp); 6351 6352 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock); 6353 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock); 6354 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); 6355 6356 PIPE_CONF_CHECK_I(min_voltage_level); 6357 6358 if (current_config->has_psr || pipe_config->has_psr) 6359 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable, 6360 ~intel_hdmi_infoframe_enable(DP_SDP_VSC)); 6361 else 6362 PIPE_CONF_CHECK_X(infoframes.enable); 6363 6364 PIPE_CONF_CHECK_X(infoframes.gcp); 6365 PIPE_CONF_CHECK_INFOFRAME(avi); 6366 PIPE_CONF_CHECK_INFOFRAME(spd); 6367 PIPE_CONF_CHECK_INFOFRAME(hdmi); 6368 PIPE_CONF_CHECK_INFOFRAME(drm); 6369 PIPE_CONF_CHECK_DP_VSC_SDP(vsc); 6370 6371 PIPE_CONF_CHECK_X(sync_mode_slaves_mask); 6372 PIPE_CONF_CHECK_I(master_transcoder); 6373 PIPE_CONF_CHECK_X(bigjoiner_pipes); 6374 6375 PIPE_CONF_CHECK_I(dsc.compression_enable); 6376 PIPE_CONF_CHECK_I(dsc.dsc_split); 6377 PIPE_CONF_CHECK_I(dsc.compressed_bpp); 6378 6379 PIPE_CONF_CHECK_BOOL(splitter.enable); 6380 PIPE_CONF_CHECK_I(splitter.link_count); 6381 PIPE_CONF_CHECK_I(splitter.pixel_overlap); 6382 6383 PIPE_CONF_CHECK_BOOL(vrr.enable); 6384 PIPE_CONF_CHECK_I(vrr.vmin); 6385 PIPE_CONF_CHECK_I(vrr.vmax); 6386 PIPE_CONF_CHECK_I(vrr.flipline); 6387 PIPE_CONF_CHECK_I(vrr.pipeline_full); 6388 PIPE_CONF_CHECK_I(vrr.guardband); 6389 6390 #undef PIPE_CONF_CHECK_X 6391 #undef PIPE_CONF_CHECK_I 6392 #undef PIPE_CONF_CHECK_BOOL 6393 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE 6394 #undef PIPE_CONF_CHECK_P 6395 #undef PIPE_CONF_CHECK_FLAGS 6396 #undef PIPE_CONF_CHECK_CLOCK_FUZZY 6397 #undef PIPE_CONF_CHECK_COLOR_LUT 6398 #undef PIPE_CONF_CHECK_TIMINGS 6399 #undef PIPE_CONF_CHECK_RECT 6400 #undef PIPE_CONF_QUIRK 6401 6402 return ret; 6403 } 6404 6405 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, 6406 const struct intel_crtc_state *pipe_config) 6407 { 6408 if (pipe_config->has_pch_encoder) { 6409 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), 6410 &pipe_config->fdi_m_n); 6411 int dotclock = pipe_config->hw.adjusted_mode.crtc_clock; 6412 6413 /* 6414 * FDI already provided one idea for the dotclock. 6415 * Yell if the encoder disagrees. 6416 */ 6417 drm_WARN(&dev_priv->drm, 6418 !intel_fuzzy_clock_check(fdi_dotclock, dotclock), 6419 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", 6420 fdi_dotclock, dotclock); 6421 } 6422 } 6423 6424 static void verify_wm_state(struct intel_crtc *crtc, 6425 struct intel_crtc_state *new_crtc_state) 6426 { 6427 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6428 struct skl_hw_state { 6429 struct skl_ddb_entry ddb[I915_MAX_PLANES]; 6430 struct skl_ddb_entry ddb_y[I915_MAX_PLANES]; 6431 struct skl_pipe_wm wm; 6432 } *hw; 6433 const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal; 6434 int level, max_level = ilk_wm_max_level(dev_priv); 6435 struct intel_plane *plane; 6436 u8 hw_enabled_slices; 6437 6438 if (DISPLAY_VER(dev_priv) < 9 || !new_crtc_state->hw.active) 6439 return; 6440 6441 hw = kzalloc(sizeof(*hw), GFP_KERNEL); 6442 if (!hw) 6443 return; 6444 6445 skl_pipe_wm_get_hw_state(crtc, &hw->wm); 6446 6447 skl_pipe_ddb_get_hw_state(crtc, hw->ddb, hw->ddb_y); 6448 6449 hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv); 6450 6451 if (DISPLAY_VER(dev_priv) >= 11 && 6452 hw_enabled_slices != dev_priv->dbuf.enabled_slices) 6453 drm_err(&dev_priv->drm, 6454 "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n", 6455 dev_priv->dbuf.enabled_slices, 6456 hw_enabled_slices); 6457 6458 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 6459 const struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; 6460 const struct skl_wm_level *hw_wm_level, *sw_wm_level; 6461 6462 /* Watermarks */ 6463 for (level = 0; level <= max_level; level++) { 6464 hw_wm_level = &hw->wm.planes[plane->id].wm[level]; 6465 sw_wm_level = skl_plane_wm_level(sw_wm, plane->id, level); 6466 6467 if (skl_wm_level_equals(hw_wm_level, sw_wm_level)) 6468 continue; 6469 6470 drm_err(&dev_priv->drm, 6471 "[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 6472 plane->base.base.id, plane->base.name, level, 6473 sw_wm_level->enable, 6474 sw_wm_level->blocks, 6475 sw_wm_level->lines, 6476 hw_wm_level->enable, 6477 hw_wm_level->blocks, 6478 hw_wm_level->lines); 6479 } 6480 6481 hw_wm_level = &hw->wm.planes[plane->id].trans_wm; 6482 sw_wm_level = skl_plane_trans_wm(sw_wm, plane->id); 6483 6484 if (!skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 6485 drm_err(&dev_priv->drm, 6486 "[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 6487 plane->base.base.id, plane->base.name, 6488 sw_wm_level->enable, 6489 sw_wm_level->blocks, 6490 sw_wm_level->lines, 6491 hw_wm_level->enable, 6492 hw_wm_level->blocks, 6493 hw_wm_level->lines); 6494 } 6495 6496 hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0; 6497 sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0; 6498 6499 if (HAS_HW_SAGV_WM(dev_priv) && 6500 !skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 6501 drm_err(&dev_priv->drm, 6502 "[PLANE:%d:%s] mismatch in SAGV WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 6503 plane->base.base.id, plane->base.name, 6504 sw_wm_level->enable, 6505 sw_wm_level->blocks, 6506 sw_wm_level->lines, 6507 hw_wm_level->enable, 6508 hw_wm_level->blocks, 6509 hw_wm_level->lines); 6510 } 6511 6512 hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm; 6513 sw_wm_level = &sw_wm->planes[plane->id].sagv.trans_wm; 6514 6515 if (HAS_HW_SAGV_WM(dev_priv) && 6516 !skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 6517 drm_err(&dev_priv->drm, 6518 "[PLANE:%d:%s] mismatch in SAGV trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 6519 plane->base.base.id, plane->base.name, 6520 sw_wm_level->enable, 6521 sw_wm_level->blocks, 6522 sw_wm_level->lines, 6523 hw_wm_level->enable, 6524 hw_wm_level->blocks, 6525 hw_wm_level->lines); 6526 } 6527 6528 /* DDB */ 6529 hw_ddb_entry = &hw->ddb[PLANE_CURSOR]; 6530 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[PLANE_CURSOR]; 6531 6532 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { 6533 drm_err(&dev_priv->drm, 6534 "[PLANE:%d:%s] mismatch in DDB (expected (%u,%u), found (%u,%u))\n", 6535 plane->base.base.id, plane->base.name, 6536 sw_ddb_entry->start, sw_ddb_entry->end, 6537 hw_ddb_entry->start, hw_ddb_entry->end); 6538 } 6539 } 6540 6541 kfree(hw); 6542 } 6543 6544 static void 6545 verify_connector_state(struct intel_atomic_state *state, 6546 struct intel_crtc *crtc) 6547 { 6548 struct drm_connector *connector; 6549 struct drm_connector_state *new_conn_state; 6550 int i; 6551 6552 for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) { 6553 struct drm_encoder *encoder = connector->encoder; 6554 struct intel_crtc_state *crtc_state = NULL; 6555 6556 if (new_conn_state->crtc != &crtc->base) 6557 continue; 6558 6559 if (crtc) 6560 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6561 6562 intel_connector_verify_state(crtc_state, new_conn_state); 6563 6564 I915_STATE_WARN(new_conn_state->best_encoder != encoder, 6565 "connector's atomic encoder doesn't match legacy encoder\n"); 6566 } 6567 } 6568 6569 static void 6570 verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state) 6571 { 6572 struct intel_encoder *encoder; 6573 struct drm_connector *connector; 6574 struct drm_connector_state *old_conn_state, *new_conn_state; 6575 int i; 6576 6577 for_each_intel_encoder(&dev_priv->drm, encoder) { 6578 bool enabled = false, found = false; 6579 enum pipe pipe; 6580 6581 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n", 6582 encoder->base.base.id, 6583 encoder->base.name); 6584 6585 for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state, 6586 new_conn_state, i) { 6587 if (old_conn_state->best_encoder == &encoder->base) 6588 found = true; 6589 6590 if (new_conn_state->best_encoder != &encoder->base) 6591 continue; 6592 found = enabled = true; 6593 6594 I915_STATE_WARN(new_conn_state->crtc != 6595 encoder->base.crtc, 6596 "connector's crtc doesn't match encoder crtc\n"); 6597 } 6598 6599 if (!found) 6600 continue; 6601 6602 I915_STATE_WARN(!!encoder->base.crtc != enabled, 6603 "encoder's enabled state mismatch " 6604 "(expected %i, found %i)\n", 6605 !!encoder->base.crtc, enabled); 6606 6607 if (!encoder->base.crtc) { 6608 bool active; 6609 6610 active = encoder->get_hw_state(encoder, &pipe); 6611 I915_STATE_WARN(active, 6612 "encoder detached but still enabled on pipe %c.\n", 6613 pipe_name(pipe)); 6614 } 6615 } 6616 } 6617 6618 static void 6619 verify_crtc_state(struct intel_crtc *crtc, 6620 struct intel_crtc_state *old_crtc_state, 6621 struct intel_crtc_state *new_crtc_state) 6622 { 6623 struct drm_device *dev = crtc->base.dev; 6624 struct drm_i915_private *dev_priv = to_i915(dev); 6625 struct intel_encoder *encoder; 6626 struct intel_crtc_state *pipe_config = old_crtc_state; 6627 struct drm_atomic_state *state = old_crtc_state->uapi.state; 6628 struct intel_crtc *master_crtc; 6629 6630 __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi); 6631 intel_crtc_free_hw_state(old_crtc_state); 6632 intel_crtc_state_reset(old_crtc_state, crtc); 6633 old_crtc_state->uapi.state = state; 6634 6635 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id, 6636 crtc->base.name); 6637 6638 pipe_config->hw.enable = new_crtc_state->hw.enable; 6639 6640 intel_crtc_get_pipe_config(pipe_config); 6641 6642 /* we keep both pipes enabled on 830 */ 6643 if (IS_I830(dev_priv) && pipe_config->hw.active) 6644 pipe_config->hw.active = new_crtc_state->hw.active; 6645 6646 I915_STATE_WARN(new_crtc_state->hw.active != pipe_config->hw.active, 6647 "crtc active state doesn't match with hw state " 6648 "(expected %i, found %i)\n", 6649 new_crtc_state->hw.active, pipe_config->hw.active); 6650 6651 I915_STATE_WARN(crtc->active != new_crtc_state->hw.active, 6652 "transitional active state does not match atomic hw state " 6653 "(expected %i, found %i)\n", 6654 new_crtc_state->hw.active, crtc->active); 6655 6656 master_crtc = intel_master_crtc(new_crtc_state); 6657 6658 for_each_encoder_on_crtc(dev, &master_crtc->base, encoder) { 6659 enum pipe pipe; 6660 bool active; 6661 6662 active = encoder->get_hw_state(encoder, &pipe); 6663 I915_STATE_WARN(active != new_crtc_state->hw.active, 6664 "[ENCODER:%i] active %i with crtc active %i\n", 6665 encoder->base.base.id, active, 6666 new_crtc_state->hw.active); 6667 6668 I915_STATE_WARN(active && master_crtc->pipe != pipe, 6669 "Encoder connected to wrong pipe %c\n", 6670 pipe_name(pipe)); 6671 6672 if (active) 6673 intel_encoder_get_config(encoder, pipe_config); 6674 } 6675 6676 if (!new_crtc_state->hw.active) 6677 return; 6678 6679 intel_pipe_config_sanity_check(dev_priv, pipe_config); 6680 6681 if (!intel_pipe_config_compare(new_crtc_state, 6682 pipe_config, false)) { 6683 I915_STATE_WARN(1, "pipe state doesn't match!\n"); 6684 intel_dump_pipe_config(pipe_config, NULL, "[hw state]"); 6685 intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]"); 6686 } 6687 } 6688 6689 static void 6690 intel_verify_planes(struct intel_atomic_state *state) 6691 { 6692 struct intel_plane *plane; 6693 const struct intel_plane_state *plane_state; 6694 int i; 6695 6696 for_each_new_intel_plane_in_state(state, plane, 6697 plane_state, i) 6698 assert_plane(plane, plane_state->planar_slave || 6699 plane_state->uapi.visible); 6700 } 6701 6702 static void 6703 verify_single_dpll_state(struct drm_i915_private *dev_priv, 6704 struct intel_shared_dpll *pll, 6705 struct intel_crtc *crtc, 6706 struct intel_crtc_state *new_crtc_state) 6707 { 6708 struct intel_dpll_hw_state dpll_hw_state; 6709 u8 pipe_mask; 6710 bool active; 6711 6712 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); 6713 6714 drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name); 6715 6716 active = intel_dpll_get_hw_state(dev_priv, pll, &dpll_hw_state); 6717 6718 if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) { 6719 I915_STATE_WARN(!pll->on && pll->active_mask, 6720 "pll in active use but not on in sw tracking\n"); 6721 I915_STATE_WARN(pll->on && !pll->active_mask, 6722 "pll is on but not used by any active pipe\n"); 6723 I915_STATE_WARN(pll->on != active, 6724 "pll on state mismatch (expected %i, found %i)\n", 6725 pll->on, active); 6726 } 6727 6728 if (!crtc) { 6729 I915_STATE_WARN(pll->active_mask & ~pll->state.pipe_mask, 6730 "more active pll users than references: 0x%x vs 0x%x\n", 6731 pll->active_mask, pll->state.pipe_mask); 6732 6733 return; 6734 } 6735 6736 pipe_mask = BIT(crtc->pipe); 6737 6738 if (new_crtc_state->hw.active) 6739 I915_STATE_WARN(!(pll->active_mask & pipe_mask), 6740 "pll active mismatch (expected pipe %c in active mask 0x%x)\n", 6741 pipe_name(crtc->pipe), pll->active_mask); 6742 else 6743 I915_STATE_WARN(pll->active_mask & pipe_mask, 6744 "pll active mismatch (didn't expect pipe %c in active mask 0x%x)\n", 6745 pipe_name(crtc->pipe), pll->active_mask); 6746 6747 I915_STATE_WARN(!(pll->state.pipe_mask & pipe_mask), 6748 "pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n", 6749 pipe_mask, pll->state.pipe_mask); 6750 6751 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state, 6752 &dpll_hw_state, 6753 sizeof(dpll_hw_state)), 6754 "pll hw state mismatch\n"); 6755 } 6756 6757 static void 6758 verify_shared_dpll_state(struct intel_crtc *crtc, 6759 struct intel_crtc_state *old_crtc_state, 6760 struct intel_crtc_state *new_crtc_state) 6761 { 6762 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6763 6764 if (new_crtc_state->shared_dpll) 6765 verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state); 6766 6767 if (old_crtc_state->shared_dpll && 6768 old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) { 6769 u8 pipe_mask = BIT(crtc->pipe); 6770 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll; 6771 6772 I915_STATE_WARN(pll->active_mask & pipe_mask, 6773 "pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n", 6774 pipe_name(crtc->pipe), pll->active_mask); 6775 I915_STATE_WARN(pll->state.pipe_mask & pipe_mask, 6776 "pll enabled crtcs mismatch (found %x in enabled mask (0x%x))\n", 6777 pipe_name(crtc->pipe), pll->state.pipe_mask); 6778 } 6779 } 6780 6781 static void 6782 verify_mpllb_state(struct intel_atomic_state *state, 6783 struct intel_crtc_state *new_crtc_state) 6784 { 6785 struct drm_i915_private *i915 = to_i915(state->base.dev); 6786 struct intel_mpllb_state mpllb_hw_state = { 0 }; 6787 struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->mpllb_state; 6788 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 6789 struct intel_encoder *encoder; 6790 6791 if (!IS_DG2(i915)) 6792 return; 6793 6794 if (!new_crtc_state->hw.active) 6795 return; 6796 6797 encoder = intel_get_crtc_new_encoder(state, new_crtc_state); 6798 intel_mpllb_readout_hw_state(encoder, &mpllb_hw_state); 6799 6800 #define MPLLB_CHECK(name) do { \ 6801 if (mpllb_sw_state->name != mpllb_hw_state.name) { \ 6802 pipe_config_mismatch(false, crtc, "MPLLB:" __stringify(name), \ 6803 "(expected 0x%08x, found 0x%08x)", \ 6804 mpllb_sw_state->name, \ 6805 mpllb_hw_state.name); \ 6806 } \ 6807 } while (0) 6808 6809 MPLLB_CHECK(mpllb_cp); 6810 MPLLB_CHECK(mpllb_div); 6811 MPLLB_CHECK(mpllb_div2); 6812 MPLLB_CHECK(mpllb_fracn1); 6813 MPLLB_CHECK(mpllb_fracn2); 6814 MPLLB_CHECK(mpllb_sscen); 6815 MPLLB_CHECK(mpllb_sscstep); 6816 6817 /* 6818 * ref_control is handled by the hardware/firemware and never 6819 * programmed by the software, but the proper values are supplied 6820 * in the bspec for verification purposes. 6821 */ 6822 MPLLB_CHECK(ref_control); 6823 6824 #undef MPLLB_CHECK 6825 } 6826 6827 static void 6828 intel_modeset_verify_crtc(struct intel_crtc *crtc, 6829 struct intel_atomic_state *state, 6830 struct intel_crtc_state *old_crtc_state, 6831 struct intel_crtc_state *new_crtc_state) 6832 { 6833 if (!intel_crtc_needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe) 6834 return; 6835 6836 verify_wm_state(crtc, new_crtc_state); 6837 verify_connector_state(state, crtc); 6838 verify_crtc_state(crtc, old_crtc_state, new_crtc_state); 6839 verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state); 6840 verify_mpllb_state(state, new_crtc_state); 6841 } 6842 6843 static void 6844 verify_disabled_dpll_state(struct drm_i915_private *dev_priv) 6845 { 6846 int i; 6847 6848 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) 6849 verify_single_dpll_state(dev_priv, 6850 &dev_priv->dpll.shared_dplls[i], 6851 NULL, NULL); 6852 } 6853 6854 static void 6855 intel_modeset_verify_disabled(struct drm_i915_private *dev_priv, 6856 struct intel_atomic_state *state) 6857 { 6858 verify_encoder_state(dev_priv, state); 6859 verify_connector_state(state, NULL); 6860 verify_disabled_dpll_state(dev_priv); 6861 } 6862 6863 int intel_modeset_all_pipes(struct intel_atomic_state *state) 6864 { 6865 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6866 struct intel_crtc *crtc; 6867 6868 /* 6869 * Add all pipes to the state, and force 6870 * a modeset on all the active ones. 6871 */ 6872 for_each_intel_crtc(&dev_priv->drm, crtc) { 6873 struct intel_crtc_state *crtc_state; 6874 int ret; 6875 6876 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6877 if (IS_ERR(crtc_state)) 6878 return PTR_ERR(crtc_state); 6879 6880 if (!crtc_state->hw.active || 6881 drm_atomic_crtc_needs_modeset(&crtc_state->uapi)) 6882 continue; 6883 6884 crtc_state->uapi.mode_changed = true; 6885 6886 ret = drm_atomic_add_affected_connectors(&state->base, 6887 &crtc->base); 6888 if (ret) 6889 return ret; 6890 6891 ret = intel_atomic_add_affected_planes(state, crtc); 6892 if (ret) 6893 return ret; 6894 6895 crtc_state->update_planes |= crtc_state->active_planes; 6896 } 6897 6898 return 0; 6899 } 6900 6901 static void 6902 intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state) 6903 { 6904 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 6905 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6906 struct drm_display_mode adjusted_mode; 6907 6908 drm_mode_init(&adjusted_mode, &crtc_state->hw.adjusted_mode); 6909 6910 if (crtc_state->vrr.enable) { 6911 adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax; 6912 adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax; 6913 adjusted_mode.crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state); 6914 crtc->vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state); 6915 } 6916 6917 drm_calc_timestamping_constants(&crtc->base, &adjusted_mode); 6918 6919 crtc->mode_flags = crtc_state->mode_flags; 6920 6921 /* 6922 * The scanline counter increments at the leading edge of hsync. 6923 * 6924 * On most platforms it starts counting from vtotal-1 on the 6925 * first active line. That means the scanline counter value is 6926 * always one less than what we would expect. Ie. just after 6927 * start of vblank, which also occurs at start of hsync (on the 6928 * last active line), the scanline counter will read vblank_start-1. 6929 * 6930 * On gen2 the scanline counter starts counting from 1 instead 6931 * of vtotal-1, so we have to subtract one (or rather add vtotal-1 6932 * to keep the value positive), instead of adding one. 6933 * 6934 * On HSW+ the behaviour of the scanline counter depends on the output 6935 * type. For DP ports it behaves like most other platforms, but on HDMI 6936 * there's an extra 1 line difference. So we need to add two instead of 6937 * one to the value. 6938 * 6939 * On VLV/CHV DSI the scanline counter would appear to increment 6940 * approx. 1/3 of a scanline before start of vblank. Unfortunately 6941 * that means we can't tell whether we're in vblank or not while 6942 * we're on that particular line. We must still set scanline_offset 6943 * to 1 so that the vblank timestamps come out correct when we query 6944 * the scanline counter from within the vblank interrupt handler. 6945 * However if queried just before the start of vblank we'll get an 6946 * answer that's slightly in the future. 6947 */ 6948 if (DISPLAY_VER(dev_priv) == 2) { 6949 int vtotal; 6950 6951 vtotal = adjusted_mode.crtc_vtotal; 6952 if (adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 6953 vtotal /= 2; 6954 6955 crtc->scanline_offset = vtotal - 1; 6956 } else if (HAS_DDI(dev_priv) && 6957 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 6958 crtc->scanline_offset = 2; 6959 } else { 6960 crtc->scanline_offset = 1; 6961 } 6962 } 6963 6964 static void intel_modeset_clear_plls(struct intel_atomic_state *state) 6965 { 6966 struct intel_crtc_state *new_crtc_state; 6967 struct intel_crtc *crtc; 6968 int i; 6969 6970 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6971 if (!intel_crtc_needs_modeset(new_crtc_state)) 6972 continue; 6973 6974 intel_release_shared_dplls(state, crtc); 6975 } 6976 } 6977 6978 /* 6979 * This implements the workaround described in the "notes" section of the mode 6980 * set sequence documentation. When going from no pipes or single pipe to 6981 * multiple pipes, and planes are enabled after the pipe, we need to wait at 6982 * least 2 vblanks on the first pipe before enabling planes on the second pipe. 6983 */ 6984 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state) 6985 { 6986 struct intel_crtc_state *crtc_state; 6987 struct intel_crtc *crtc; 6988 struct intel_crtc_state *first_crtc_state = NULL; 6989 struct intel_crtc_state *other_crtc_state = NULL; 6990 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; 6991 int i; 6992 6993 /* look at all crtc's that are going to be enabled in during modeset */ 6994 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6995 if (!crtc_state->hw.active || 6996 !intel_crtc_needs_modeset(crtc_state)) 6997 continue; 6998 6999 if (first_crtc_state) { 7000 other_crtc_state = crtc_state; 7001 break; 7002 } else { 7003 first_crtc_state = crtc_state; 7004 first_pipe = crtc->pipe; 7005 } 7006 } 7007 7008 /* No workaround needed? */ 7009 if (!first_crtc_state) 7010 return 0; 7011 7012 /* w/a possibly needed, check how many crtc's are already enabled. */ 7013 for_each_intel_crtc(state->base.dev, crtc) { 7014 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 7015 if (IS_ERR(crtc_state)) 7016 return PTR_ERR(crtc_state); 7017 7018 crtc_state->hsw_workaround_pipe = INVALID_PIPE; 7019 7020 if (!crtc_state->hw.active || 7021 intel_crtc_needs_modeset(crtc_state)) 7022 continue; 7023 7024 /* 2 or more enabled crtcs means no need for w/a */ 7025 if (enabled_pipe != INVALID_PIPE) 7026 return 0; 7027 7028 enabled_pipe = crtc->pipe; 7029 } 7030 7031 if (enabled_pipe != INVALID_PIPE) 7032 first_crtc_state->hsw_workaround_pipe = enabled_pipe; 7033 else if (other_crtc_state) 7034 other_crtc_state->hsw_workaround_pipe = first_pipe; 7035 7036 return 0; 7037 } 7038 7039 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 7040 u8 active_pipes) 7041 { 7042 const struct intel_crtc_state *crtc_state; 7043 struct intel_crtc *crtc; 7044 int i; 7045 7046 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7047 if (crtc_state->hw.active) 7048 active_pipes |= BIT(crtc->pipe); 7049 else 7050 active_pipes &= ~BIT(crtc->pipe); 7051 } 7052 7053 return active_pipes; 7054 } 7055 7056 static int intel_modeset_checks(struct intel_atomic_state *state) 7057 { 7058 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7059 7060 state->modeset = true; 7061 7062 if (IS_HASWELL(dev_priv)) 7063 return hsw_mode_set_planes_workaround(state); 7064 7065 return 0; 7066 } 7067 7068 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state, 7069 struct intel_crtc_state *new_crtc_state) 7070 { 7071 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) 7072 return; 7073 7074 new_crtc_state->uapi.mode_changed = false; 7075 new_crtc_state->update_pipe = true; 7076 } 7077 7078 static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state, 7079 struct intel_crtc_state *new_crtc_state) 7080 { 7081 /* 7082 * If we're not doing the full modeset we want to 7083 * keep the current M/N values as they may be 7084 * sufficiently different to the computed values 7085 * to cause problems. 7086 * 7087 * FIXME: should really copy more fuzzy state here 7088 */ 7089 new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n; 7090 new_crtc_state->dp_m_n = old_crtc_state->dp_m_n; 7091 new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2; 7092 new_crtc_state->has_drrs = old_crtc_state->has_drrs; 7093 } 7094 7095 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state, 7096 struct intel_crtc *crtc, 7097 u8 plane_ids_mask) 7098 { 7099 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7100 struct intel_plane *plane; 7101 7102 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 7103 struct intel_plane_state *plane_state; 7104 7105 if ((plane_ids_mask & BIT(plane->id)) == 0) 7106 continue; 7107 7108 plane_state = intel_atomic_get_plane_state(state, plane); 7109 if (IS_ERR(plane_state)) 7110 return PTR_ERR(plane_state); 7111 } 7112 7113 return 0; 7114 } 7115 7116 int intel_atomic_add_affected_planes(struct intel_atomic_state *state, 7117 struct intel_crtc *crtc) 7118 { 7119 const struct intel_crtc_state *old_crtc_state = 7120 intel_atomic_get_old_crtc_state(state, crtc); 7121 const struct intel_crtc_state *new_crtc_state = 7122 intel_atomic_get_new_crtc_state(state, crtc); 7123 7124 return intel_crtc_add_planes_to_state(state, crtc, 7125 old_crtc_state->enabled_planes | 7126 new_crtc_state->enabled_planes); 7127 } 7128 7129 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv) 7130 { 7131 /* See {hsw,vlv,ivb}_plane_ratio() */ 7132 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) || 7133 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) || 7134 IS_IVYBRIDGE(dev_priv); 7135 } 7136 7137 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state, 7138 struct intel_crtc *crtc, 7139 struct intel_crtc *other) 7140 { 7141 const struct intel_plane_state *plane_state; 7142 struct intel_plane *plane; 7143 u8 plane_ids = 0; 7144 int i; 7145 7146 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 7147 if (plane->pipe == crtc->pipe) 7148 plane_ids |= BIT(plane->id); 7149 } 7150 7151 return intel_crtc_add_planes_to_state(state, other, plane_ids); 7152 } 7153 7154 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state) 7155 { 7156 struct drm_i915_private *i915 = to_i915(state->base.dev); 7157 const struct intel_crtc_state *crtc_state; 7158 struct intel_crtc *crtc; 7159 int i; 7160 7161 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7162 struct intel_crtc *other; 7163 7164 for_each_intel_crtc_in_pipe_mask(&i915->drm, other, 7165 crtc_state->bigjoiner_pipes) { 7166 int ret; 7167 7168 if (crtc == other) 7169 continue; 7170 7171 ret = intel_crtc_add_bigjoiner_planes(state, crtc, other); 7172 if (ret) 7173 return ret; 7174 } 7175 } 7176 7177 return 0; 7178 } 7179 7180 static int intel_atomic_check_planes(struct intel_atomic_state *state) 7181 { 7182 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7183 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7184 struct intel_plane_state *plane_state; 7185 struct intel_plane *plane; 7186 struct intel_crtc *crtc; 7187 int i, ret; 7188 7189 ret = icl_add_linked_planes(state); 7190 if (ret) 7191 return ret; 7192 7193 ret = intel_bigjoiner_add_affected_planes(state); 7194 if (ret) 7195 return ret; 7196 7197 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 7198 ret = intel_plane_atomic_check(state, plane); 7199 if (ret) { 7200 drm_dbg_atomic(&dev_priv->drm, 7201 "[PLANE:%d:%s] atomic driver check failed\n", 7202 plane->base.base.id, plane->base.name); 7203 return ret; 7204 } 7205 } 7206 7207 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7208 new_crtc_state, i) { 7209 u8 old_active_planes, new_active_planes; 7210 7211 ret = icl_check_nv12_planes(new_crtc_state); 7212 if (ret) 7213 return ret; 7214 7215 /* 7216 * On some platforms the number of active planes affects 7217 * the planes' minimum cdclk calculation. Add such planes 7218 * to the state before we compute the minimum cdclk. 7219 */ 7220 if (!active_planes_affects_min_cdclk(dev_priv)) 7221 continue; 7222 7223 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 7224 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 7225 7226 if (hweight8(old_active_planes) == hweight8(new_active_planes)) 7227 continue; 7228 7229 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes); 7230 if (ret) 7231 return ret; 7232 } 7233 7234 return 0; 7235 } 7236 7237 static int intel_atomic_check_crtcs(struct intel_atomic_state *state) 7238 { 7239 struct intel_crtc_state *crtc_state; 7240 struct intel_crtc *crtc; 7241 int i; 7242 7243 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7244 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 7245 int ret; 7246 7247 ret = intel_crtc_atomic_check(state, crtc); 7248 if (ret) { 7249 drm_dbg_atomic(&i915->drm, 7250 "[CRTC:%d:%s] atomic driver check failed\n", 7251 crtc->base.base.id, crtc->base.name); 7252 return ret; 7253 } 7254 } 7255 7256 return 0; 7257 } 7258 7259 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, 7260 u8 transcoders) 7261 { 7262 const struct intel_crtc_state *new_crtc_state; 7263 struct intel_crtc *crtc; 7264 int i; 7265 7266 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7267 if (new_crtc_state->hw.enable && 7268 transcoders & BIT(new_crtc_state->cpu_transcoder) && 7269 intel_crtc_needs_modeset(new_crtc_state)) 7270 return true; 7271 } 7272 7273 return false; 7274 } 7275 7276 static bool intel_pipes_need_modeset(struct intel_atomic_state *state, 7277 u8 pipes) 7278 { 7279 const struct intel_crtc_state *new_crtc_state; 7280 struct intel_crtc *crtc; 7281 int i; 7282 7283 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7284 if (new_crtc_state->hw.enable && 7285 pipes & BIT(crtc->pipe) && 7286 intel_crtc_needs_modeset(new_crtc_state)) 7287 return true; 7288 } 7289 7290 return false; 7291 } 7292 7293 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state, 7294 struct intel_crtc *master_crtc) 7295 { 7296 struct drm_i915_private *i915 = to_i915(state->base.dev); 7297 struct intel_crtc_state *master_crtc_state = 7298 intel_atomic_get_new_crtc_state(state, master_crtc); 7299 struct intel_crtc *slave_crtc; 7300 7301 if (!master_crtc_state->bigjoiner_pipes) 7302 return 0; 7303 7304 /* sanity check */ 7305 if (drm_WARN_ON(&i915->drm, 7306 master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state))) 7307 return -EINVAL; 7308 7309 if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) { 7310 drm_dbg_kms(&i915->drm, 7311 "[CRTC:%d:%s] Cannot act as big joiner master " 7312 "(need 0x%x as pipes, only 0x%x possible)\n", 7313 master_crtc->base.base.id, master_crtc->base.name, 7314 master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915)); 7315 return -EINVAL; 7316 } 7317 7318 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 7319 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 7320 struct intel_crtc_state *slave_crtc_state; 7321 int ret; 7322 7323 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc); 7324 if (IS_ERR(slave_crtc_state)) 7325 return PTR_ERR(slave_crtc_state); 7326 7327 /* master being enabled, slave was already configured? */ 7328 if (slave_crtc_state->uapi.enable) { 7329 drm_dbg_kms(&i915->drm, 7330 "[CRTC:%d:%s] Slave is enabled as normal CRTC, but " 7331 "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n", 7332 slave_crtc->base.base.id, slave_crtc->base.name, 7333 master_crtc->base.base.id, master_crtc->base.name); 7334 return -EINVAL; 7335 } 7336 7337 /* 7338 * The state copy logic assumes the master crtc gets processed 7339 * before the slave crtc during the main compute_config loop. 7340 * This works because the crtcs are created in pipe order, 7341 * and the hardware requires master pipe < slave pipe as well. 7342 * Should that change we need to rethink the logic. 7343 */ 7344 if (WARN_ON(drm_crtc_index(&master_crtc->base) > 7345 drm_crtc_index(&slave_crtc->base))) 7346 return -EINVAL; 7347 7348 drm_dbg_kms(&i915->drm, 7349 "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n", 7350 slave_crtc->base.base.id, slave_crtc->base.name, 7351 master_crtc->base.base.id, master_crtc->base.name); 7352 7353 slave_crtc_state->bigjoiner_pipes = 7354 master_crtc_state->bigjoiner_pipes; 7355 7356 ret = copy_bigjoiner_crtc_state_modeset(state, slave_crtc); 7357 if (ret) 7358 return ret; 7359 } 7360 7361 return 0; 7362 } 7363 7364 static void kill_bigjoiner_slave(struct intel_atomic_state *state, 7365 struct intel_crtc *master_crtc) 7366 { 7367 struct drm_i915_private *i915 = to_i915(state->base.dev); 7368 struct intel_crtc_state *master_crtc_state = 7369 intel_atomic_get_new_crtc_state(state, master_crtc); 7370 struct intel_crtc *slave_crtc; 7371 7372 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 7373 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 7374 struct intel_crtc_state *slave_crtc_state = 7375 intel_atomic_get_new_crtc_state(state, slave_crtc); 7376 7377 slave_crtc_state->bigjoiner_pipes = 0; 7378 7379 intel_crtc_copy_uapi_to_hw_state_modeset(state, slave_crtc); 7380 } 7381 7382 master_crtc_state->bigjoiner_pipes = 0; 7383 } 7384 7385 /** 7386 * DOC: asynchronous flip implementation 7387 * 7388 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC 7389 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL. 7390 * Correspondingly, support is currently added for primary plane only. 7391 * 7392 * Async flip can only change the plane surface address, so anything else 7393 * changing is rejected from the intel_async_flip_check_hw() function. 7394 * Once this check is cleared, flip done interrupt is enabled using 7395 * the intel_crtc_enable_flip_done() function. 7396 * 7397 * As soon as the surface address register is written, flip done interrupt is 7398 * generated and the requested events are sent to the usersapce in the interrupt 7399 * handler itself. The timestamp and sequence sent during the flip done event 7400 * correspond to the last vblank and have no relation to the actual time when 7401 * the flip done event was sent. 7402 */ 7403 static int intel_async_flip_check_uapi(struct intel_atomic_state *state, 7404 struct intel_crtc *crtc) 7405 { 7406 struct drm_i915_private *i915 = to_i915(state->base.dev); 7407 const struct intel_crtc_state *new_crtc_state = 7408 intel_atomic_get_new_crtc_state(state, crtc); 7409 const struct intel_plane_state *old_plane_state; 7410 struct intel_plane_state *new_plane_state; 7411 struct intel_plane *plane; 7412 int i; 7413 7414 if (!new_crtc_state->uapi.async_flip) 7415 return 0; 7416 7417 if (!new_crtc_state->uapi.active) { 7418 drm_dbg_kms(&i915->drm, 7419 "[CRTC:%d:%s] not active\n", 7420 crtc->base.base.id, crtc->base.name); 7421 return -EINVAL; 7422 } 7423 7424 if (intel_crtc_needs_modeset(new_crtc_state)) { 7425 drm_dbg_kms(&i915->drm, 7426 "[CRTC:%d:%s] modeset required\n", 7427 crtc->base.base.id, crtc->base.name); 7428 return -EINVAL; 7429 } 7430 7431 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 7432 new_plane_state, i) { 7433 if (plane->pipe != crtc->pipe) 7434 continue; 7435 7436 /* 7437 * TODO: Async flip is only supported through the page flip IOCTL 7438 * as of now. So support currently added for primary plane only. 7439 * Support for other planes on platforms on which supports 7440 * this(vlv/chv and icl+) should be added when async flip is 7441 * enabled in the atomic IOCTL path. 7442 */ 7443 if (!plane->async_flip) { 7444 drm_dbg_kms(&i915->drm, 7445 "[PLANE:%d:%s] async flip not supported\n", 7446 plane->base.base.id, plane->base.name); 7447 return -EINVAL; 7448 } 7449 7450 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) { 7451 drm_dbg_kms(&i915->drm, 7452 "[PLANE:%d:%s] no old or new framebuffer\n", 7453 plane->base.base.id, plane->base.name); 7454 return -EINVAL; 7455 } 7456 } 7457 7458 return 0; 7459 } 7460 7461 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc) 7462 { 7463 struct drm_i915_private *i915 = to_i915(state->base.dev); 7464 const struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7465 const struct intel_plane_state *new_plane_state, *old_plane_state; 7466 struct intel_plane *plane; 7467 int i; 7468 7469 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 7470 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 7471 7472 if (!new_crtc_state->uapi.async_flip) 7473 return 0; 7474 7475 if (!new_crtc_state->hw.active) { 7476 drm_dbg_kms(&i915->drm, 7477 "[CRTC:%d:%s] not active\n", 7478 crtc->base.base.id, crtc->base.name); 7479 return -EINVAL; 7480 } 7481 7482 if (intel_crtc_needs_modeset(new_crtc_state)) { 7483 drm_dbg_kms(&i915->drm, 7484 "[CRTC:%d:%s] modeset required\n", 7485 crtc->base.base.id, crtc->base.name); 7486 return -EINVAL; 7487 } 7488 7489 if (old_crtc_state->active_planes != new_crtc_state->active_planes) { 7490 drm_dbg_kms(&i915->drm, 7491 "[CRTC:%d:%s] Active planes cannot be in async flip\n", 7492 crtc->base.base.id, crtc->base.name); 7493 return -EINVAL; 7494 } 7495 7496 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 7497 new_plane_state, i) { 7498 if (plane->pipe != crtc->pipe) 7499 continue; 7500 7501 /* 7502 * Only async flip capable planes should be in the state 7503 * if we're really about to ask the hardware to perform 7504 * an async flip. We should never get this far otherwise. 7505 */ 7506 if (drm_WARN_ON(&i915->drm, 7507 new_crtc_state->do_async_flip && !plane->async_flip)) 7508 return -EINVAL; 7509 7510 /* 7511 * Only check async flip capable planes other planes 7512 * may be involved in the initial commit due to 7513 * the wm0/ddb optimization. 7514 * 7515 * TODO maybe should track which planes actually 7516 * were requested to do the async flip... 7517 */ 7518 if (!plane->async_flip) 7519 continue; 7520 7521 /* 7522 * FIXME: This check is kept generic for all platforms. 7523 * Need to verify this for all gen9 platforms to enable 7524 * this selectively if required. 7525 */ 7526 switch (new_plane_state->hw.fb->modifier) { 7527 case I915_FORMAT_MOD_X_TILED: 7528 case I915_FORMAT_MOD_Y_TILED: 7529 case I915_FORMAT_MOD_Yf_TILED: 7530 case I915_FORMAT_MOD_4_TILED: 7531 break; 7532 default: 7533 drm_dbg_kms(&i915->drm, 7534 "[PLANE:%d:%s] Modifier does not support async flips\n", 7535 plane->base.base.id, plane->base.name); 7536 return -EINVAL; 7537 } 7538 7539 if (new_plane_state->hw.fb->format->num_planes > 1) { 7540 drm_dbg_kms(&i915->drm, 7541 "[PLANE:%d:%s] Planar formats do not support async flips\n", 7542 plane->base.base.id, plane->base.name); 7543 return -EINVAL; 7544 } 7545 7546 if (old_plane_state->view.color_plane[0].mapping_stride != 7547 new_plane_state->view.color_plane[0].mapping_stride) { 7548 drm_dbg_kms(&i915->drm, 7549 "[PLANE:%d:%s] Stride cannot be changed in async flip\n", 7550 plane->base.base.id, plane->base.name); 7551 return -EINVAL; 7552 } 7553 7554 if (old_plane_state->hw.fb->modifier != 7555 new_plane_state->hw.fb->modifier) { 7556 drm_dbg_kms(&i915->drm, 7557 "[PLANE:%d:%s] Modifier cannot be changed in async flip\n", 7558 plane->base.base.id, plane->base.name); 7559 return -EINVAL; 7560 } 7561 7562 if (old_plane_state->hw.fb->format != 7563 new_plane_state->hw.fb->format) { 7564 drm_dbg_kms(&i915->drm, 7565 "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n", 7566 plane->base.base.id, plane->base.name); 7567 return -EINVAL; 7568 } 7569 7570 if (old_plane_state->hw.rotation != 7571 new_plane_state->hw.rotation) { 7572 drm_dbg_kms(&i915->drm, 7573 "[PLANE:%d:%s] Rotation cannot be changed in async flip\n", 7574 plane->base.base.id, plane->base.name); 7575 return -EINVAL; 7576 } 7577 7578 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) || 7579 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) { 7580 drm_dbg_kms(&i915->drm, 7581 "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n", 7582 plane->base.base.id, plane->base.name); 7583 return -EINVAL; 7584 } 7585 7586 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) { 7587 drm_dbg_kms(&i915->drm, 7588 "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n", 7589 plane->base.base.id, plane->base.name); 7590 return -EINVAL; 7591 } 7592 7593 if (old_plane_state->hw.pixel_blend_mode != 7594 new_plane_state->hw.pixel_blend_mode) { 7595 drm_dbg_kms(&i915->drm, 7596 "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n", 7597 plane->base.base.id, plane->base.name); 7598 return -EINVAL; 7599 } 7600 7601 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) { 7602 drm_dbg_kms(&i915->drm, 7603 "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n", 7604 plane->base.base.id, plane->base.name); 7605 return -EINVAL; 7606 } 7607 7608 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) { 7609 drm_dbg_kms(&i915->drm, 7610 "[PLANE:%d:%s] Color range cannot be changed in async flip\n", 7611 plane->base.base.id, plane->base.name); 7612 return -EINVAL; 7613 } 7614 7615 /* plane decryption is allow to change only in synchronous flips */ 7616 if (old_plane_state->decrypt != new_plane_state->decrypt) { 7617 drm_dbg_kms(&i915->drm, 7618 "[PLANE:%d:%s] Decryption cannot be changed in async flip\n", 7619 plane->base.base.id, plane->base.name); 7620 return -EINVAL; 7621 } 7622 } 7623 7624 return 0; 7625 } 7626 7627 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state) 7628 { 7629 struct drm_i915_private *i915 = to_i915(state->base.dev); 7630 struct intel_crtc_state *crtc_state; 7631 struct intel_crtc *crtc; 7632 u8 affected_pipes = 0; 7633 u8 modeset_pipes = 0; 7634 int i; 7635 7636 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7637 affected_pipes |= crtc_state->bigjoiner_pipes; 7638 if (intel_crtc_needs_modeset(crtc_state)) 7639 modeset_pipes |= crtc_state->bigjoiner_pipes; 7640 } 7641 7642 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) { 7643 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 7644 if (IS_ERR(crtc_state)) 7645 return PTR_ERR(crtc_state); 7646 } 7647 7648 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) { 7649 int ret; 7650 7651 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 7652 7653 crtc_state->uapi.mode_changed = true; 7654 7655 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); 7656 if (ret) 7657 return ret; 7658 7659 ret = intel_atomic_add_affected_planes(state, crtc); 7660 if (ret) 7661 return ret; 7662 } 7663 7664 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7665 /* Kill old bigjoiner link, we may re-establish afterwards */ 7666 if (intel_crtc_needs_modeset(crtc_state) && 7667 intel_crtc_is_bigjoiner_master(crtc_state)) 7668 kill_bigjoiner_slave(state, crtc); 7669 } 7670 7671 return 0; 7672 } 7673 7674 /** 7675 * intel_atomic_check - validate state object 7676 * @dev: drm device 7677 * @_state: state to validate 7678 */ 7679 static int intel_atomic_check(struct drm_device *dev, 7680 struct drm_atomic_state *_state) 7681 { 7682 struct drm_i915_private *dev_priv = to_i915(dev); 7683 struct intel_atomic_state *state = to_intel_atomic_state(_state); 7684 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7685 struct intel_crtc *crtc; 7686 int ret, i; 7687 bool any_ms = false; 7688 7689 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7690 new_crtc_state, i) { 7691 if (new_crtc_state->inherited != old_crtc_state->inherited) 7692 new_crtc_state->uapi.mode_changed = true; 7693 7694 if (new_crtc_state->uapi.scaling_filter != 7695 old_crtc_state->uapi.scaling_filter) 7696 new_crtc_state->uapi.mode_changed = true; 7697 } 7698 7699 intel_vrr_check_modeset(state); 7700 7701 ret = drm_atomic_helper_check_modeset(dev, &state->base); 7702 if (ret) 7703 goto fail; 7704 7705 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7706 ret = intel_async_flip_check_uapi(state, crtc); 7707 if (ret) 7708 return ret; 7709 } 7710 7711 ret = intel_bigjoiner_add_affected_crtcs(state); 7712 if (ret) 7713 goto fail; 7714 7715 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7716 new_crtc_state, i) { 7717 if (!intel_crtc_needs_modeset(new_crtc_state)) { 7718 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 7719 copy_bigjoiner_crtc_state_nomodeset(state, crtc); 7720 else 7721 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 7722 continue; 7723 } 7724 7725 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) { 7726 drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable); 7727 continue; 7728 } 7729 7730 ret = intel_crtc_prepare_cleared_state(state, crtc); 7731 if (ret) 7732 goto fail; 7733 7734 if (!new_crtc_state->hw.enable) 7735 continue; 7736 7737 ret = intel_modeset_pipe_config(state, crtc); 7738 if (ret) 7739 goto fail; 7740 7741 ret = intel_atomic_check_bigjoiner(state, crtc); 7742 if (ret) 7743 goto fail; 7744 } 7745 7746 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7747 new_crtc_state, i) { 7748 if (!intel_crtc_needs_modeset(new_crtc_state)) 7749 continue; 7750 7751 ret = intel_modeset_pipe_config_late(state, crtc); 7752 if (ret) 7753 goto fail; 7754 7755 intel_crtc_check_fastset(old_crtc_state, new_crtc_state); 7756 } 7757 7758 /** 7759 * Check if fastset is allowed by external dependencies like other 7760 * pipes and transcoders. 7761 * 7762 * Right now it only forces a fullmodeset when the MST master 7763 * transcoder did not changed but the pipe of the master transcoder 7764 * needs a fullmodeset so all slaves also needs to do a fullmodeset or 7765 * in case of port synced crtcs, if one of the synced crtcs 7766 * needs a full modeset, all other synced crtcs should be 7767 * forced a full modeset. 7768 */ 7769 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7770 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state)) 7771 continue; 7772 7773 if (intel_dp_mst_is_slave_trans(new_crtc_state)) { 7774 enum transcoder master = new_crtc_state->mst_master_transcoder; 7775 7776 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) { 7777 new_crtc_state->uapi.mode_changed = true; 7778 new_crtc_state->update_pipe = false; 7779 } 7780 } 7781 7782 if (is_trans_port_sync_mode(new_crtc_state)) { 7783 u8 trans = new_crtc_state->sync_mode_slaves_mask; 7784 7785 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER) 7786 trans |= BIT(new_crtc_state->master_transcoder); 7787 7788 if (intel_cpu_transcoders_need_modeset(state, trans)) { 7789 new_crtc_state->uapi.mode_changed = true; 7790 new_crtc_state->update_pipe = false; 7791 } 7792 } 7793 7794 if (new_crtc_state->bigjoiner_pipes) { 7795 if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) { 7796 new_crtc_state->uapi.mode_changed = true; 7797 new_crtc_state->update_pipe = false; 7798 } 7799 } 7800 } 7801 7802 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7803 new_crtc_state, i) { 7804 if (intel_crtc_needs_modeset(new_crtc_state)) { 7805 any_ms = true; 7806 continue; 7807 } 7808 7809 if (!new_crtc_state->update_pipe) 7810 continue; 7811 7812 intel_crtc_copy_fastset(old_crtc_state, new_crtc_state); 7813 } 7814 7815 if (any_ms && !check_digital_port_conflicts(state)) { 7816 drm_dbg_kms(&dev_priv->drm, 7817 "rejecting conflicting digital port configuration\n"); 7818 ret = -EINVAL; 7819 goto fail; 7820 } 7821 7822 ret = drm_dp_mst_atomic_check(&state->base); 7823 if (ret) 7824 goto fail; 7825 7826 ret = intel_atomic_check_planes(state); 7827 if (ret) 7828 goto fail; 7829 7830 ret = intel_compute_global_watermarks(state); 7831 if (ret) 7832 goto fail; 7833 7834 ret = intel_bw_atomic_check(state); 7835 if (ret) 7836 goto fail; 7837 7838 ret = intel_cdclk_atomic_check(state, &any_ms); 7839 if (ret) 7840 goto fail; 7841 7842 if (intel_any_crtc_needs_modeset(state)) 7843 any_ms = true; 7844 7845 if (any_ms) { 7846 ret = intel_modeset_checks(state); 7847 if (ret) 7848 goto fail; 7849 7850 ret = intel_modeset_calc_cdclk(state); 7851 if (ret) 7852 return ret; 7853 7854 intel_modeset_clear_plls(state); 7855 } 7856 7857 ret = intel_atomic_check_crtcs(state); 7858 if (ret) 7859 goto fail; 7860 7861 ret = intel_fbc_atomic_check(state); 7862 if (ret) 7863 goto fail; 7864 7865 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7866 new_crtc_state, i) { 7867 ret = intel_async_flip_check_hw(state, crtc); 7868 if (ret) 7869 goto fail; 7870 7871 if (!intel_crtc_needs_modeset(new_crtc_state) && 7872 !new_crtc_state->update_pipe) 7873 continue; 7874 7875 intel_dump_pipe_config(new_crtc_state, state, 7876 intel_crtc_needs_modeset(new_crtc_state) ? 7877 "[modeset]" : "[fastset]"); 7878 } 7879 7880 return 0; 7881 7882 fail: 7883 if (ret == -EDEADLK) 7884 return ret; 7885 7886 /* 7887 * FIXME would probably be nice to know which crtc specifically 7888 * caused the failure, in cases where we can pinpoint it. 7889 */ 7890 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7891 new_crtc_state, i) 7892 intel_dump_pipe_config(new_crtc_state, state, "[failed]"); 7893 7894 return ret; 7895 } 7896 7897 static int intel_atomic_prepare_commit(struct intel_atomic_state *state) 7898 { 7899 struct intel_crtc_state *crtc_state; 7900 struct intel_crtc *crtc; 7901 int i, ret; 7902 7903 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base); 7904 if (ret < 0) 7905 return ret; 7906 7907 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7908 bool mode_changed = intel_crtc_needs_modeset(crtc_state); 7909 7910 if (mode_changed || crtc_state->update_pipe || 7911 crtc_state->uapi.color_mgmt_changed) { 7912 intel_dsb_prepare(crtc_state); 7913 } 7914 } 7915 7916 return 0; 7917 } 7918 7919 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 7920 struct intel_crtc_state *crtc_state) 7921 { 7922 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 7923 7924 if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes) 7925 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 7926 7927 if (crtc_state->has_pch_encoder) { 7928 enum pipe pch_transcoder = 7929 intel_crtc_pch_transcoder(crtc); 7930 7931 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true); 7932 } 7933 } 7934 7935 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, 7936 const struct intel_crtc_state *new_crtc_state) 7937 { 7938 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 7939 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 7940 7941 /* 7942 * Update pipe size and adjust fitter if needed: the reason for this is 7943 * that in compute_mode_changes we check the native mode (not the pfit 7944 * mode) to see if we can flip rather than do a full mode set. In the 7945 * fastboot case, we'll flip, but if we don't update the pipesrc and 7946 * pfit state, we'll end up with a big fb scanned out into the wrong 7947 * sized surface. 7948 */ 7949 intel_set_pipe_src_size(new_crtc_state); 7950 7951 /* on skylake this is done by detaching scalers */ 7952 if (DISPLAY_VER(dev_priv) >= 9) { 7953 if (new_crtc_state->pch_pfit.enabled) 7954 skl_pfit_enable(new_crtc_state); 7955 } else if (HAS_PCH_SPLIT(dev_priv)) { 7956 if (new_crtc_state->pch_pfit.enabled) 7957 ilk_pfit_enable(new_crtc_state); 7958 else if (old_crtc_state->pch_pfit.enabled) 7959 ilk_pfit_disable(old_crtc_state); 7960 } 7961 7962 /* 7963 * The register is supposedly single buffered so perhaps 7964 * not 100% correct to do this here. But SKL+ calculate 7965 * this based on the adjust pixel rate so pfit changes do 7966 * affect it and so it must be updated for fastsets. 7967 * HSW/BDW only really need this here for fastboot, after 7968 * that the value should not change without a full modeset. 7969 */ 7970 if (DISPLAY_VER(dev_priv) >= 9 || 7971 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 7972 hsw_set_linetime_wm(new_crtc_state); 7973 } 7974 7975 static void commit_pipe_pre_planes(struct intel_atomic_state *state, 7976 struct intel_crtc *crtc) 7977 { 7978 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7979 const struct intel_crtc_state *old_crtc_state = 7980 intel_atomic_get_old_crtc_state(state, crtc); 7981 const struct intel_crtc_state *new_crtc_state = 7982 intel_atomic_get_new_crtc_state(state, crtc); 7983 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 7984 7985 /* 7986 * During modesets pipe configuration was programmed as the 7987 * CRTC was enabled. 7988 */ 7989 if (!modeset) { 7990 if (new_crtc_state->uapi.color_mgmt_changed || 7991 new_crtc_state->update_pipe) 7992 intel_color_commit_arm(new_crtc_state); 7993 7994 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 7995 bdw_set_pipemisc(new_crtc_state); 7996 7997 if (new_crtc_state->update_pipe) 7998 intel_pipe_fastset(old_crtc_state, new_crtc_state); 7999 } 8000 8001 intel_psr2_program_trans_man_trk_ctl(new_crtc_state); 8002 8003 intel_atomic_update_watermarks(state, crtc); 8004 } 8005 8006 static void commit_pipe_post_planes(struct intel_atomic_state *state, 8007 struct intel_crtc *crtc) 8008 { 8009 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8010 const struct intel_crtc_state *new_crtc_state = 8011 intel_atomic_get_new_crtc_state(state, crtc); 8012 8013 /* 8014 * Disable the scaler(s) after the plane(s) so that we don't 8015 * get a catastrophic underrun even if the two operations 8016 * end up happening in two different frames. 8017 */ 8018 if (DISPLAY_VER(dev_priv) >= 9 && 8019 !intel_crtc_needs_modeset(new_crtc_state)) 8020 skl_detach_scalers(new_crtc_state); 8021 } 8022 8023 static void intel_enable_crtc(struct intel_atomic_state *state, 8024 struct intel_crtc *crtc) 8025 { 8026 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8027 const struct intel_crtc_state *new_crtc_state = 8028 intel_atomic_get_new_crtc_state(state, crtc); 8029 8030 if (!intel_crtc_needs_modeset(new_crtc_state)) 8031 return; 8032 8033 intel_crtc_update_active_timings(new_crtc_state); 8034 8035 dev_priv->display->crtc_enable(state, crtc); 8036 8037 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 8038 return; 8039 8040 /* vblanks work again, re-enable pipe CRC. */ 8041 intel_crtc_enable_pipe_crc(crtc); 8042 } 8043 8044 static void intel_update_crtc(struct intel_atomic_state *state, 8045 struct intel_crtc *crtc) 8046 { 8047 struct drm_i915_private *i915 = to_i915(state->base.dev); 8048 const struct intel_crtc_state *old_crtc_state = 8049 intel_atomic_get_old_crtc_state(state, crtc); 8050 struct intel_crtc_state *new_crtc_state = 8051 intel_atomic_get_new_crtc_state(state, crtc); 8052 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 8053 8054 if (!modeset) { 8055 if (new_crtc_state->preload_luts && 8056 (new_crtc_state->uapi.color_mgmt_changed || 8057 new_crtc_state->update_pipe)) 8058 intel_color_load_luts(new_crtc_state); 8059 8060 intel_pre_plane_update(state, crtc); 8061 8062 if (new_crtc_state->update_pipe) 8063 intel_encoders_update_pipe(state, crtc); 8064 8065 if (DISPLAY_VER(i915) >= 11 && 8066 new_crtc_state->update_pipe) 8067 icl_set_pipe_chicken(new_crtc_state); 8068 } 8069 8070 intel_fbc_update(state, crtc); 8071 8072 if (!modeset && 8073 (new_crtc_state->uapi.color_mgmt_changed || 8074 new_crtc_state->update_pipe)) 8075 intel_color_commit_noarm(new_crtc_state); 8076 8077 intel_crtc_planes_update_noarm(state, crtc); 8078 8079 /* Perform vblank evasion around commit operation */ 8080 intel_pipe_update_start(new_crtc_state); 8081 8082 commit_pipe_pre_planes(state, crtc); 8083 8084 intel_crtc_planes_update_arm(state, crtc); 8085 8086 commit_pipe_post_planes(state, crtc); 8087 8088 intel_pipe_update_end(new_crtc_state); 8089 8090 /* 8091 * We usually enable FIFO underrun interrupts as part of the 8092 * CRTC enable sequence during modesets. But when we inherit a 8093 * valid pipe configuration from the BIOS we need to take care 8094 * of enabling them on the CRTC's first fastset. 8095 */ 8096 if (new_crtc_state->update_pipe && !modeset && 8097 old_crtc_state->inherited) 8098 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state); 8099 } 8100 8101 static void intel_old_crtc_state_disables(struct intel_atomic_state *state, 8102 struct intel_crtc_state *old_crtc_state, 8103 struct intel_crtc_state *new_crtc_state, 8104 struct intel_crtc *crtc) 8105 { 8106 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8107 8108 /* 8109 * We need to disable pipe CRC before disabling the pipe, 8110 * or we race against vblank off. 8111 */ 8112 intel_crtc_disable_pipe_crc(crtc); 8113 8114 dev_priv->display->crtc_disable(state, crtc); 8115 crtc->active = false; 8116 intel_fbc_disable(crtc); 8117 intel_disable_shared_dpll(old_crtc_state); 8118 8119 /* FIXME unify this for all platforms */ 8120 if (!new_crtc_state->hw.active && 8121 !HAS_GMCH(dev_priv)) 8122 intel_initial_watermarks(state, crtc); 8123 } 8124 8125 static void intel_commit_modeset_disables(struct intel_atomic_state *state) 8126 { 8127 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 8128 struct intel_crtc *crtc; 8129 u32 handled = 0; 8130 int i; 8131 8132 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8133 new_crtc_state, i) { 8134 if (!intel_crtc_needs_modeset(new_crtc_state)) 8135 continue; 8136 8137 if (!old_crtc_state->hw.active) 8138 continue; 8139 8140 intel_pre_plane_update(state, crtc); 8141 intel_crtc_disable_planes(state, crtc); 8142 } 8143 8144 /* Only disable port sync and MST slaves */ 8145 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8146 new_crtc_state, i) { 8147 if (!intel_crtc_needs_modeset(new_crtc_state)) 8148 continue; 8149 8150 if (!old_crtc_state->hw.active) 8151 continue; 8152 8153 /* In case of Transcoder port Sync master slave CRTCs can be 8154 * assigned in any order and we need to make sure that 8155 * slave CRTCs are disabled first and then master CRTC since 8156 * Slave vblanks are masked till Master Vblanks. 8157 */ 8158 if (!is_trans_port_sync_slave(old_crtc_state) && 8159 !intel_dp_mst_is_slave_trans(old_crtc_state) && 8160 !intel_crtc_is_bigjoiner_slave(old_crtc_state)) 8161 continue; 8162 8163 intel_old_crtc_state_disables(state, old_crtc_state, 8164 new_crtc_state, crtc); 8165 handled |= BIT(crtc->pipe); 8166 } 8167 8168 /* Disable everything else left on */ 8169 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8170 new_crtc_state, i) { 8171 if (!intel_crtc_needs_modeset(new_crtc_state) || 8172 (handled & BIT(crtc->pipe))) 8173 continue; 8174 8175 if (!old_crtc_state->hw.active) 8176 continue; 8177 8178 intel_old_crtc_state_disables(state, old_crtc_state, 8179 new_crtc_state, crtc); 8180 } 8181 } 8182 8183 static void intel_commit_modeset_enables(struct intel_atomic_state *state) 8184 { 8185 struct intel_crtc_state *new_crtc_state; 8186 struct intel_crtc *crtc; 8187 int i; 8188 8189 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8190 if (!new_crtc_state->hw.active) 8191 continue; 8192 8193 intel_enable_crtc(state, crtc); 8194 intel_update_crtc(state, crtc); 8195 } 8196 } 8197 8198 static void skl_commit_modeset_enables(struct intel_atomic_state *state) 8199 { 8200 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8201 struct intel_crtc *crtc; 8202 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 8203 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; 8204 u8 update_pipes = 0, modeset_pipes = 0; 8205 int i; 8206 8207 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 8208 enum pipe pipe = crtc->pipe; 8209 8210 if (!new_crtc_state->hw.active) 8211 continue; 8212 8213 /* ignore allocations for crtc's that have been turned off. */ 8214 if (!intel_crtc_needs_modeset(new_crtc_state)) { 8215 entries[pipe] = old_crtc_state->wm.skl.ddb; 8216 update_pipes |= BIT(pipe); 8217 } else { 8218 modeset_pipes |= BIT(pipe); 8219 } 8220 } 8221 8222 /* 8223 * Whenever the number of active pipes changes, we need to make sure we 8224 * update the pipes in the right order so that their ddb allocations 8225 * never overlap with each other between CRTC updates. Otherwise we'll 8226 * cause pipe underruns and other bad stuff. 8227 * 8228 * So first lets enable all pipes that do not need a fullmodeset as 8229 * those don't have any external dependency. 8230 */ 8231 while (update_pipes) { 8232 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8233 new_crtc_state, i) { 8234 enum pipe pipe = crtc->pipe; 8235 8236 if ((update_pipes & BIT(pipe)) == 0) 8237 continue; 8238 8239 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 8240 entries, I915_MAX_PIPES, pipe)) 8241 continue; 8242 8243 entries[pipe] = new_crtc_state->wm.skl.ddb; 8244 update_pipes &= ~BIT(pipe); 8245 8246 intel_update_crtc(state, crtc); 8247 8248 /* 8249 * If this is an already active pipe, it's DDB changed, 8250 * and this isn't the last pipe that needs updating 8251 * then we need to wait for a vblank to pass for the 8252 * new ddb allocation to take effect. 8253 */ 8254 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, 8255 &old_crtc_state->wm.skl.ddb) && 8256 (update_pipes | modeset_pipes)) 8257 intel_crtc_wait_for_next_vblank(crtc); 8258 } 8259 } 8260 8261 update_pipes = modeset_pipes; 8262 8263 /* 8264 * Enable all pipes that needs a modeset and do not depends on other 8265 * pipes 8266 */ 8267 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8268 enum pipe pipe = crtc->pipe; 8269 8270 if ((modeset_pipes & BIT(pipe)) == 0) 8271 continue; 8272 8273 if (intel_dp_mst_is_slave_trans(new_crtc_state) || 8274 is_trans_port_sync_master(new_crtc_state) || 8275 intel_crtc_is_bigjoiner_master(new_crtc_state)) 8276 continue; 8277 8278 modeset_pipes &= ~BIT(pipe); 8279 8280 intel_enable_crtc(state, crtc); 8281 } 8282 8283 /* 8284 * Then we enable all remaining pipes that depend on other 8285 * pipes: MST slaves and port sync masters, big joiner master 8286 */ 8287 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8288 enum pipe pipe = crtc->pipe; 8289 8290 if ((modeset_pipes & BIT(pipe)) == 0) 8291 continue; 8292 8293 modeset_pipes &= ~BIT(pipe); 8294 8295 intel_enable_crtc(state, crtc); 8296 } 8297 8298 /* 8299 * Finally we do the plane updates/etc. for all pipes that got enabled. 8300 */ 8301 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8302 enum pipe pipe = crtc->pipe; 8303 8304 if ((update_pipes & BIT(pipe)) == 0) 8305 continue; 8306 8307 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 8308 entries, I915_MAX_PIPES, pipe)); 8309 8310 entries[pipe] = new_crtc_state->wm.skl.ddb; 8311 update_pipes &= ~BIT(pipe); 8312 8313 intel_update_crtc(state, crtc); 8314 } 8315 8316 drm_WARN_ON(&dev_priv->drm, modeset_pipes); 8317 drm_WARN_ON(&dev_priv->drm, update_pipes); 8318 } 8319 8320 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) 8321 { 8322 struct intel_atomic_state *state, *next; 8323 struct llist_node *freed; 8324 8325 freed = llist_del_all(&dev_priv->atomic_helper.free_list); 8326 llist_for_each_entry_safe(state, next, freed, freed) 8327 drm_atomic_state_put(&state->base); 8328 } 8329 8330 static void intel_atomic_helper_free_state_worker(struct work_struct *work) 8331 { 8332 struct drm_i915_private *dev_priv = 8333 container_of(work, typeof(*dev_priv), atomic_helper.free_work); 8334 8335 intel_atomic_helper_free_state(dev_priv); 8336 } 8337 8338 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) 8339 { 8340 struct wait_queue_entry wait_fence, wait_reset; 8341 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); 8342 8343 init_wait_entry(&wait_fence, 0); 8344 init_wait_entry(&wait_reset, 0); 8345 for (;;) { 8346 prepare_to_wait(&intel_state->commit_ready.wait, 8347 &wait_fence, TASK_UNINTERRUPTIBLE); 8348 prepare_to_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 8349 I915_RESET_MODESET), 8350 &wait_reset, TASK_UNINTERRUPTIBLE); 8351 8352 8353 if (i915_sw_fence_done(&intel_state->commit_ready) || 8354 test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags)) 8355 break; 8356 8357 schedule(); 8358 } 8359 finish_wait(&intel_state->commit_ready.wait, &wait_fence); 8360 finish_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 8361 I915_RESET_MODESET), 8362 &wait_reset); 8363 } 8364 8365 static void intel_cleanup_dsbs(struct intel_atomic_state *state) 8366 { 8367 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 8368 struct intel_crtc *crtc; 8369 int i; 8370 8371 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8372 new_crtc_state, i) 8373 intel_dsb_cleanup(old_crtc_state); 8374 } 8375 8376 static void intel_atomic_cleanup_work(struct work_struct *work) 8377 { 8378 struct intel_atomic_state *state = 8379 container_of(work, struct intel_atomic_state, base.commit_work); 8380 struct drm_i915_private *i915 = to_i915(state->base.dev); 8381 8382 intel_cleanup_dsbs(state); 8383 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base); 8384 drm_atomic_helper_commit_cleanup_done(&state->base); 8385 drm_atomic_state_put(&state->base); 8386 8387 intel_atomic_helper_free_state(i915); 8388 } 8389 8390 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state) 8391 { 8392 struct drm_i915_private *i915 = to_i915(state->base.dev); 8393 struct intel_plane *plane; 8394 struct intel_plane_state *plane_state; 8395 int i; 8396 8397 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 8398 struct drm_framebuffer *fb = plane_state->hw.fb; 8399 int cc_plane; 8400 int ret; 8401 8402 if (!fb) 8403 continue; 8404 8405 cc_plane = intel_fb_rc_ccs_cc_plane(fb); 8406 if (cc_plane < 0) 8407 continue; 8408 8409 /* 8410 * The layout of the fast clear color value expected by HW 8411 * (the DRM ABI requiring this value to be located in fb at 8412 * offset 0 of cc plane, plane #2 previous generations or 8413 * plane #1 for flat ccs): 8414 * - 4 x 4 bytes per-channel value 8415 * (in surface type specific float/int format provided by the fb user) 8416 * - 8 bytes native color value used by the display 8417 * (converted/written by GPU during a fast clear operation using the 8418 * above per-channel values) 8419 * 8420 * The commit's FB prepare hook already ensured that FB obj is pinned and the 8421 * caller made sure that the object is synced wrt. the related color clear value 8422 * GPU write on it. 8423 */ 8424 ret = i915_gem_object_read_from_page(intel_fb_obj(fb), 8425 fb->offsets[cc_plane] + 16, 8426 &plane_state->ccval, 8427 sizeof(plane_state->ccval)); 8428 /* The above could only fail if the FB obj has an unexpected backing store type. */ 8429 drm_WARN_ON(&i915->drm, ret); 8430 } 8431 } 8432 8433 static void intel_atomic_commit_tail(struct intel_atomic_state *state) 8434 { 8435 struct drm_device *dev = state->base.dev; 8436 struct drm_i915_private *dev_priv = to_i915(dev); 8437 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 8438 struct intel_crtc *crtc; 8439 struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {}; 8440 intel_wakeref_t wakeref = 0; 8441 int i; 8442 8443 intel_atomic_commit_fence_wait(state); 8444 8445 drm_atomic_helper_wait_for_dependencies(&state->base); 8446 8447 if (state->modeset) 8448 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); 8449 8450 intel_atomic_prepare_plane_clear_colors(state); 8451 8452 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8453 new_crtc_state, i) { 8454 if (intel_crtc_needs_modeset(new_crtc_state) || 8455 new_crtc_state->update_pipe) { 8456 modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]); 8457 } 8458 } 8459 8460 intel_commit_modeset_disables(state); 8461 8462 /* FIXME: Eventually get rid of our crtc->config pointer */ 8463 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 8464 crtc->config = new_crtc_state; 8465 8466 if (state->modeset) { 8467 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base); 8468 8469 intel_set_cdclk_pre_plane_update(state); 8470 8471 intel_modeset_verify_disabled(dev_priv, state); 8472 } 8473 8474 intel_sagv_pre_plane_update(state); 8475 8476 /* Complete the events for pipes that have now been disabled */ 8477 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8478 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 8479 8480 /* Complete events for now disable pipes here. */ 8481 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) { 8482 spin_lock_irq(&dev->event_lock); 8483 drm_crtc_send_vblank_event(&crtc->base, 8484 new_crtc_state->uapi.event); 8485 spin_unlock_irq(&dev->event_lock); 8486 8487 new_crtc_state->uapi.event = NULL; 8488 } 8489 } 8490 8491 intel_encoders_update_prepare(state); 8492 8493 intel_dbuf_pre_plane_update(state); 8494 intel_mbus_dbox_update(state); 8495 8496 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8497 if (new_crtc_state->do_async_flip) 8498 intel_crtc_enable_flip_done(state, crtc); 8499 } 8500 8501 /* Now enable the clocks, plane, pipe, and connectors that we set up. */ 8502 dev_priv->display->commit_modeset_enables(state); 8503 8504 intel_encoders_update_complete(state); 8505 8506 if (state->modeset) 8507 intel_set_cdclk_post_plane_update(state); 8508 8509 intel_wait_for_vblank_workers(state); 8510 8511 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here 8512 * already, but still need the state for the delayed optimization. To 8513 * fix this: 8514 * - wrap the optimization/post_plane_update stuff into a per-crtc work. 8515 * - schedule that vblank worker _before_ calling hw_done 8516 * - at the start of commit_tail, cancel it _synchrously 8517 * - switch over to the vblank wait helper in the core after that since 8518 * we don't need out special handling any more. 8519 */ 8520 drm_atomic_helper_wait_for_flip_done(dev, &state->base); 8521 8522 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8523 if (new_crtc_state->do_async_flip) 8524 intel_crtc_disable_flip_done(state, crtc); 8525 } 8526 8527 /* 8528 * Now that the vblank has passed, we can go ahead and program the 8529 * optimal watermarks on platforms that need two-step watermark 8530 * programming. 8531 * 8532 * TODO: Move this (and other cleanup) to an async worker eventually. 8533 */ 8534 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8535 new_crtc_state, i) { 8536 /* 8537 * Gen2 reports pipe underruns whenever all planes are disabled. 8538 * So re-enable underrun reporting after some planes get enabled. 8539 * 8540 * We do this before .optimize_watermarks() so that we have a 8541 * chance of catching underruns with the intermediate watermarks 8542 * vs. the new plane configuration. 8543 */ 8544 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state)) 8545 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 8546 8547 intel_optimize_watermarks(state, crtc); 8548 } 8549 8550 intel_dbuf_post_plane_update(state); 8551 intel_psr_post_plane_update(state); 8552 8553 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 8554 intel_post_plane_update(state, crtc); 8555 8556 modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]); 8557 8558 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state); 8559 8560 /* 8561 * DSB cleanup is done in cleanup_work aligning with framebuffer 8562 * cleanup. So copy and reset the dsb structure to sync with 8563 * commit_done and later do dsb cleanup in cleanup_work. 8564 */ 8565 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb); 8566 } 8567 8568 /* Underruns don't always raise interrupts, so check manually */ 8569 intel_check_cpu_fifo_underruns(dev_priv); 8570 intel_check_pch_fifo_underruns(dev_priv); 8571 8572 if (state->modeset) 8573 intel_verify_planes(state); 8574 8575 intel_sagv_post_plane_update(state); 8576 8577 drm_atomic_helper_commit_hw_done(&state->base); 8578 8579 if (state->modeset) { 8580 /* As one of the primary mmio accessors, KMS has a high 8581 * likelihood of triggering bugs in unclaimed access. After we 8582 * finish modesetting, see if an error has been flagged, and if 8583 * so enable debugging for the next modeset - and hope we catch 8584 * the culprit. 8585 */ 8586 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); 8587 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref); 8588 } 8589 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 8590 8591 /* 8592 * Defer the cleanup of the old state to a separate worker to not 8593 * impede the current task (userspace for blocking modesets) that 8594 * are executed inline. For out-of-line asynchronous modesets/flips, 8595 * deferring to a new worker seems overkill, but we would place a 8596 * schedule point (cond_resched()) here anyway to keep latencies 8597 * down. 8598 */ 8599 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work); 8600 queue_work(system_highpri_wq, &state->base.commit_work); 8601 } 8602 8603 static void intel_atomic_commit_work(struct work_struct *work) 8604 { 8605 struct intel_atomic_state *state = 8606 container_of(work, struct intel_atomic_state, base.commit_work); 8607 8608 intel_atomic_commit_tail(state); 8609 } 8610 8611 static int 8612 intel_atomic_commit_ready(struct i915_sw_fence *fence, 8613 enum i915_sw_fence_notify notify) 8614 { 8615 struct intel_atomic_state *state = 8616 container_of(fence, struct intel_atomic_state, commit_ready); 8617 8618 switch (notify) { 8619 case FENCE_COMPLETE: 8620 /* we do blocking waits in the worker, nothing to do here */ 8621 break; 8622 case FENCE_FREE: 8623 { 8624 struct intel_atomic_helper *helper = 8625 &to_i915(state->base.dev)->atomic_helper; 8626 8627 if (llist_add(&state->freed, &helper->free_list)) 8628 schedule_work(&helper->free_work); 8629 break; 8630 } 8631 } 8632 8633 return NOTIFY_DONE; 8634 } 8635 8636 static void intel_atomic_track_fbs(struct intel_atomic_state *state) 8637 { 8638 struct intel_plane_state *old_plane_state, *new_plane_state; 8639 struct intel_plane *plane; 8640 int i; 8641 8642 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 8643 new_plane_state, i) 8644 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), 8645 to_intel_frontbuffer(new_plane_state->hw.fb), 8646 plane->frontbuffer_bit); 8647 } 8648 8649 static int intel_atomic_commit(struct drm_device *dev, 8650 struct drm_atomic_state *_state, 8651 bool nonblock) 8652 { 8653 struct intel_atomic_state *state = to_intel_atomic_state(_state); 8654 struct drm_i915_private *dev_priv = to_i915(dev); 8655 int ret = 0; 8656 8657 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 8658 8659 drm_atomic_state_get(&state->base); 8660 i915_sw_fence_init(&state->commit_ready, 8661 intel_atomic_commit_ready); 8662 8663 /* 8664 * The intel_legacy_cursor_update() fast path takes care 8665 * of avoiding the vblank waits for simple cursor 8666 * movement and flips. For cursor on/off and size changes, 8667 * we want to perform the vblank waits so that watermark 8668 * updates happen during the correct frames. Gen9+ have 8669 * double buffered watermarks and so shouldn't need this. 8670 * 8671 * Unset state->legacy_cursor_update before the call to 8672 * drm_atomic_helper_setup_commit() because otherwise 8673 * drm_atomic_helper_wait_for_flip_done() is a noop and 8674 * we get FIFO underruns because we didn't wait 8675 * for vblank. 8676 * 8677 * FIXME doing watermarks and fb cleanup from a vblank worker 8678 * (assuming we had any) would solve these problems. 8679 */ 8680 if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) { 8681 struct intel_crtc_state *new_crtc_state; 8682 struct intel_crtc *crtc; 8683 int i; 8684 8685 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 8686 if (new_crtc_state->wm.need_postvbl_update || 8687 new_crtc_state->update_wm_post) 8688 state->base.legacy_cursor_update = false; 8689 } 8690 8691 ret = intel_atomic_prepare_commit(state); 8692 if (ret) { 8693 drm_dbg_atomic(&dev_priv->drm, 8694 "Preparing state failed with %i\n", ret); 8695 i915_sw_fence_commit(&state->commit_ready); 8696 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 8697 return ret; 8698 } 8699 8700 ret = drm_atomic_helper_setup_commit(&state->base, nonblock); 8701 if (!ret) 8702 ret = drm_atomic_helper_swap_state(&state->base, true); 8703 if (!ret) 8704 intel_atomic_swap_global_state(state); 8705 8706 if (ret) { 8707 struct intel_crtc_state *new_crtc_state; 8708 struct intel_crtc *crtc; 8709 int i; 8710 8711 i915_sw_fence_commit(&state->commit_ready); 8712 8713 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 8714 intel_dsb_cleanup(new_crtc_state); 8715 8716 drm_atomic_helper_cleanup_planes(dev, &state->base); 8717 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 8718 return ret; 8719 } 8720 intel_shared_dpll_swap_state(state); 8721 intel_atomic_track_fbs(state); 8722 8723 drm_atomic_state_get(&state->base); 8724 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work); 8725 8726 i915_sw_fence_commit(&state->commit_ready); 8727 if (nonblock && state->modeset) { 8728 queue_work(dev_priv->modeset_wq, &state->base.commit_work); 8729 } else if (nonblock) { 8730 queue_work(dev_priv->flip_wq, &state->base.commit_work); 8731 } else { 8732 if (state->modeset) 8733 flush_workqueue(dev_priv->modeset_wq); 8734 intel_atomic_commit_tail(state); 8735 } 8736 8737 return 0; 8738 } 8739 8740 /** 8741 * intel_plane_destroy - destroy a plane 8742 * @plane: plane to destroy 8743 * 8744 * Common destruction function for all types of planes (primary, cursor, 8745 * sprite). 8746 */ 8747 void intel_plane_destroy(struct drm_plane *plane) 8748 { 8749 drm_plane_cleanup(plane); 8750 kfree(to_intel_plane(plane)); 8751 } 8752 8753 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv) 8754 { 8755 struct intel_plane *plane; 8756 8757 for_each_intel_plane(&dev_priv->drm, plane) { 8758 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, 8759 plane->pipe); 8760 8761 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base); 8762 } 8763 } 8764 8765 8766 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 8767 struct drm_file *file) 8768 { 8769 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; 8770 struct drm_crtc *drmmode_crtc; 8771 struct intel_crtc *crtc; 8772 8773 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id); 8774 if (!drmmode_crtc) 8775 return -ENOENT; 8776 8777 crtc = to_intel_crtc(drmmode_crtc); 8778 pipe_from_crtc_id->pipe = crtc->pipe; 8779 8780 return 0; 8781 } 8782 8783 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder) 8784 { 8785 struct drm_device *dev = encoder->base.dev; 8786 struct intel_encoder *source_encoder; 8787 u32 possible_clones = 0; 8788 8789 for_each_intel_encoder(dev, source_encoder) { 8790 if (encoders_cloneable(encoder, source_encoder)) 8791 possible_clones |= drm_encoder_mask(&source_encoder->base); 8792 } 8793 8794 return possible_clones; 8795 } 8796 8797 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder) 8798 { 8799 struct drm_device *dev = encoder->base.dev; 8800 struct intel_crtc *crtc; 8801 u32 possible_crtcs = 0; 8802 8803 for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask) 8804 possible_crtcs |= drm_crtc_mask(&crtc->base); 8805 8806 return possible_crtcs; 8807 } 8808 8809 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv) 8810 { 8811 if (!IS_MOBILE(dev_priv)) 8812 return false; 8813 8814 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0) 8815 return false; 8816 8817 if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE)) 8818 return false; 8819 8820 return true; 8821 } 8822 8823 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv) 8824 { 8825 if (DISPLAY_VER(dev_priv) >= 9) 8826 return false; 8827 8828 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) 8829 return false; 8830 8831 if (HAS_PCH_LPT_H(dev_priv) && 8832 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) 8833 return false; 8834 8835 /* DDI E can't be used if DDI A requires 4 lanes */ 8836 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 8837 return false; 8838 8839 if (!dev_priv->vbt.int_crt_support) 8840 return false; 8841 8842 return true; 8843 } 8844 8845 static void intel_setup_outputs(struct drm_i915_private *dev_priv) 8846 { 8847 struct intel_encoder *encoder; 8848 bool dpd_is_edp = false; 8849 8850 intel_pps_unlock_regs_wa(dev_priv); 8851 8852 if (!HAS_DISPLAY(dev_priv)) 8853 return; 8854 8855 if (IS_DG2(dev_priv)) { 8856 intel_ddi_init(dev_priv, PORT_A); 8857 intel_ddi_init(dev_priv, PORT_B); 8858 intel_ddi_init(dev_priv, PORT_C); 8859 intel_ddi_init(dev_priv, PORT_D_XELPD); 8860 intel_ddi_init(dev_priv, PORT_TC1); 8861 } else if (IS_ALDERLAKE_P(dev_priv)) { 8862 intel_ddi_init(dev_priv, PORT_A); 8863 intel_ddi_init(dev_priv, PORT_B); 8864 intel_ddi_init(dev_priv, PORT_TC1); 8865 intel_ddi_init(dev_priv, PORT_TC2); 8866 intel_ddi_init(dev_priv, PORT_TC3); 8867 intel_ddi_init(dev_priv, PORT_TC4); 8868 icl_dsi_init(dev_priv); 8869 } else if (IS_ALDERLAKE_S(dev_priv)) { 8870 intel_ddi_init(dev_priv, PORT_A); 8871 intel_ddi_init(dev_priv, PORT_TC1); 8872 intel_ddi_init(dev_priv, PORT_TC2); 8873 intel_ddi_init(dev_priv, PORT_TC3); 8874 intel_ddi_init(dev_priv, PORT_TC4); 8875 } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) { 8876 intel_ddi_init(dev_priv, PORT_A); 8877 intel_ddi_init(dev_priv, PORT_B); 8878 intel_ddi_init(dev_priv, PORT_TC1); 8879 intel_ddi_init(dev_priv, PORT_TC2); 8880 } else if (DISPLAY_VER(dev_priv) >= 12) { 8881 intel_ddi_init(dev_priv, PORT_A); 8882 intel_ddi_init(dev_priv, PORT_B); 8883 intel_ddi_init(dev_priv, PORT_TC1); 8884 intel_ddi_init(dev_priv, PORT_TC2); 8885 intel_ddi_init(dev_priv, PORT_TC3); 8886 intel_ddi_init(dev_priv, PORT_TC4); 8887 intel_ddi_init(dev_priv, PORT_TC5); 8888 intel_ddi_init(dev_priv, PORT_TC6); 8889 icl_dsi_init(dev_priv); 8890 } else if (IS_JSL_EHL(dev_priv)) { 8891 intel_ddi_init(dev_priv, PORT_A); 8892 intel_ddi_init(dev_priv, PORT_B); 8893 intel_ddi_init(dev_priv, PORT_C); 8894 intel_ddi_init(dev_priv, PORT_D); 8895 icl_dsi_init(dev_priv); 8896 } else if (DISPLAY_VER(dev_priv) == 11) { 8897 intel_ddi_init(dev_priv, PORT_A); 8898 intel_ddi_init(dev_priv, PORT_B); 8899 intel_ddi_init(dev_priv, PORT_C); 8900 intel_ddi_init(dev_priv, PORT_D); 8901 intel_ddi_init(dev_priv, PORT_E); 8902 intel_ddi_init(dev_priv, PORT_F); 8903 icl_dsi_init(dev_priv); 8904 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 8905 intel_ddi_init(dev_priv, PORT_A); 8906 intel_ddi_init(dev_priv, PORT_B); 8907 intel_ddi_init(dev_priv, PORT_C); 8908 vlv_dsi_init(dev_priv); 8909 } else if (DISPLAY_VER(dev_priv) >= 9) { 8910 intel_ddi_init(dev_priv, PORT_A); 8911 intel_ddi_init(dev_priv, PORT_B); 8912 intel_ddi_init(dev_priv, PORT_C); 8913 intel_ddi_init(dev_priv, PORT_D); 8914 intel_ddi_init(dev_priv, PORT_E); 8915 } else if (HAS_DDI(dev_priv)) { 8916 u32 found; 8917 8918 if (intel_ddi_crt_present(dev_priv)) 8919 intel_crt_init(dev_priv); 8920 8921 /* Haswell uses DDI functions to detect digital outputs. */ 8922 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 8923 if (found) 8924 intel_ddi_init(dev_priv, PORT_A); 8925 8926 found = intel_de_read(dev_priv, SFUSE_STRAP); 8927 if (found & SFUSE_STRAP_DDIB_DETECTED) 8928 intel_ddi_init(dev_priv, PORT_B); 8929 if (found & SFUSE_STRAP_DDIC_DETECTED) 8930 intel_ddi_init(dev_priv, PORT_C); 8931 if (found & SFUSE_STRAP_DDID_DETECTED) 8932 intel_ddi_init(dev_priv, PORT_D); 8933 if (found & SFUSE_STRAP_DDIF_DETECTED) 8934 intel_ddi_init(dev_priv, PORT_F); 8935 } else if (HAS_PCH_SPLIT(dev_priv)) { 8936 int found; 8937 8938 /* 8939 * intel_edp_init_connector() depends on this completing first, 8940 * to prevent the registration of both eDP and LVDS and the 8941 * incorrect sharing of the PPS. 8942 */ 8943 intel_lvds_init(dev_priv); 8944 intel_crt_init(dev_priv); 8945 8946 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D); 8947 8948 if (ilk_has_edp_a(dev_priv)) 8949 g4x_dp_init(dev_priv, DP_A, PORT_A); 8950 8951 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) { 8952 /* PCH SDVOB multiplex with HDMIB */ 8953 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); 8954 if (!found) 8955 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); 8956 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED)) 8957 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B); 8958 } 8959 8960 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED) 8961 g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); 8962 8963 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED) 8964 g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D); 8965 8966 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED) 8967 g4x_dp_init(dev_priv, PCH_DP_C, PORT_C); 8968 8969 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED) 8970 g4x_dp_init(dev_priv, PCH_DP_D, PORT_D); 8971 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 8972 bool has_edp, has_port; 8973 8974 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support) 8975 intel_crt_init(dev_priv); 8976 8977 /* 8978 * The DP_DETECTED bit is the latched state of the DDC 8979 * SDA pin at boot. However since eDP doesn't require DDC 8980 * (no way to plug in a DP->HDMI dongle) the DDC pins for 8981 * eDP ports may have been muxed to an alternate function. 8982 * Thus we can't rely on the DP_DETECTED bit alone to detect 8983 * eDP ports. Consult the VBT as well as DP_DETECTED to 8984 * detect eDP ports. 8985 * 8986 * Sadly the straps seem to be missing sometimes even for HDMI 8987 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap 8988 * and VBT for the presence of the port. Additionally we can't 8989 * trust the port type the VBT declares as we've seen at least 8990 * HDMI ports that the VBT claim are DP or eDP. 8991 */ 8992 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B); 8993 has_port = intel_bios_is_port_present(dev_priv, PORT_B); 8994 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port) 8995 has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B); 8996 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) 8997 g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); 8998 8999 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C); 9000 has_port = intel_bios_is_port_present(dev_priv, PORT_C); 9001 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port) 9002 has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C); 9003 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) 9004 g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); 9005 9006 if (IS_CHERRYVIEW(dev_priv)) { 9007 /* 9008 * eDP not supported on port D, 9009 * so no need to worry about it 9010 */ 9011 has_port = intel_bios_is_port_present(dev_priv, PORT_D); 9012 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port) 9013 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D); 9014 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port) 9015 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D); 9016 } 9017 9018 vlv_dsi_init(dev_priv); 9019 } else if (IS_PINEVIEW(dev_priv)) { 9020 intel_lvds_init(dev_priv); 9021 intel_crt_init(dev_priv); 9022 } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) { 9023 bool found = false; 9024 9025 if (IS_MOBILE(dev_priv)) 9026 intel_lvds_init(dev_priv); 9027 9028 intel_crt_init(dev_priv); 9029 9030 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 9031 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n"); 9032 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); 9033 if (!found && IS_G4X(dev_priv)) { 9034 drm_dbg_kms(&dev_priv->drm, 9035 "probing HDMI on SDVOB\n"); 9036 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); 9037 } 9038 9039 if (!found && IS_G4X(dev_priv)) 9040 g4x_dp_init(dev_priv, DP_B, PORT_B); 9041 } 9042 9043 /* Before G4X SDVOC doesn't have its own detect register */ 9044 9045 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 9046 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n"); 9047 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); 9048 } 9049 9050 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) { 9051 9052 if (IS_G4X(dev_priv)) { 9053 drm_dbg_kms(&dev_priv->drm, 9054 "probing HDMI on SDVOC\n"); 9055 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); 9056 } 9057 if (IS_G4X(dev_priv)) 9058 g4x_dp_init(dev_priv, DP_C, PORT_C); 9059 } 9060 9061 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED)) 9062 g4x_dp_init(dev_priv, DP_D, PORT_D); 9063 9064 if (SUPPORTS_TV(dev_priv)) 9065 intel_tv_init(dev_priv); 9066 } else if (DISPLAY_VER(dev_priv) == 2) { 9067 if (IS_I85X(dev_priv)) 9068 intel_lvds_init(dev_priv); 9069 9070 intel_crt_init(dev_priv); 9071 intel_dvo_init(dev_priv); 9072 } 9073 9074 for_each_intel_encoder(&dev_priv->drm, encoder) { 9075 encoder->base.possible_crtcs = 9076 intel_encoder_possible_crtcs(encoder); 9077 encoder->base.possible_clones = 9078 intel_encoder_possible_clones(encoder); 9079 } 9080 9081 intel_init_pch_refclk(dev_priv); 9082 9083 drm_helper_move_panel_connectors_to_head(&dev_priv->drm); 9084 } 9085 9086 static enum drm_mode_status 9087 intel_mode_valid(struct drm_device *dev, 9088 const struct drm_display_mode *mode) 9089 { 9090 struct drm_i915_private *dev_priv = to_i915(dev); 9091 int hdisplay_max, htotal_max; 9092 int vdisplay_max, vtotal_max; 9093 9094 /* 9095 * Can't reject DBLSCAN here because Xorg ddxen can add piles 9096 * of DBLSCAN modes to the output's mode list when they detect 9097 * the scaling mode property on the connector. And they don't 9098 * ask the kernel to validate those modes in any way until 9099 * modeset time at which point the client gets a protocol error. 9100 * So in order to not upset those clients we silently ignore the 9101 * DBLSCAN flag on such connectors. For other connectors we will 9102 * reject modes with the DBLSCAN flag in encoder->compute_config(). 9103 * And we always reject DBLSCAN modes in connector->mode_valid() 9104 * as we never want such modes on the connector's mode list. 9105 */ 9106 9107 if (mode->vscan > 1) 9108 return MODE_NO_VSCAN; 9109 9110 if (mode->flags & DRM_MODE_FLAG_HSKEW) 9111 return MODE_H_ILLEGAL; 9112 9113 if (mode->flags & (DRM_MODE_FLAG_CSYNC | 9114 DRM_MODE_FLAG_NCSYNC | 9115 DRM_MODE_FLAG_PCSYNC)) 9116 return MODE_HSYNC; 9117 9118 if (mode->flags & (DRM_MODE_FLAG_BCAST | 9119 DRM_MODE_FLAG_PIXMUX | 9120 DRM_MODE_FLAG_CLKDIV2)) 9121 return MODE_BAD; 9122 9123 /* Transcoder timing limits */ 9124 if (DISPLAY_VER(dev_priv) >= 11) { 9125 hdisplay_max = 16384; 9126 vdisplay_max = 8192; 9127 htotal_max = 16384; 9128 vtotal_max = 8192; 9129 } else if (DISPLAY_VER(dev_priv) >= 9 || 9130 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 9131 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ 9132 vdisplay_max = 4096; 9133 htotal_max = 8192; 9134 vtotal_max = 8192; 9135 } else if (DISPLAY_VER(dev_priv) >= 3) { 9136 hdisplay_max = 4096; 9137 vdisplay_max = 4096; 9138 htotal_max = 8192; 9139 vtotal_max = 8192; 9140 } else { 9141 hdisplay_max = 2048; 9142 vdisplay_max = 2048; 9143 htotal_max = 4096; 9144 vtotal_max = 4096; 9145 } 9146 9147 if (mode->hdisplay > hdisplay_max || 9148 mode->hsync_start > htotal_max || 9149 mode->hsync_end > htotal_max || 9150 mode->htotal > htotal_max) 9151 return MODE_H_ILLEGAL; 9152 9153 if (mode->vdisplay > vdisplay_max || 9154 mode->vsync_start > vtotal_max || 9155 mode->vsync_end > vtotal_max || 9156 mode->vtotal > vtotal_max) 9157 return MODE_V_ILLEGAL; 9158 9159 if (DISPLAY_VER(dev_priv) >= 5) { 9160 if (mode->hdisplay < 64 || 9161 mode->htotal - mode->hdisplay < 32) 9162 return MODE_H_ILLEGAL; 9163 9164 if (mode->vtotal - mode->vdisplay < 5) 9165 return MODE_V_ILLEGAL; 9166 } else { 9167 if (mode->htotal - mode->hdisplay < 32) 9168 return MODE_H_ILLEGAL; 9169 9170 if (mode->vtotal - mode->vdisplay < 3) 9171 return MODE_V_ILLEGAL; 9172 } 9173 9174 /* 9175 * Cantiga+ cannot handle modes with a hsync front porch of 0. 9176 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. 9177 */ 9178 if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) && 9179 mode->hsync_start == mode->hdisplay) 9180 return MODE_H_ILLEGAL; 9181 9182 return MODE_OK; 9183 } 9184 9185 enum drm_mode_status 9186 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 9187 const struct drm_display_mode *mode, 9188 bool bigjoiner) 9189 { 9190 int plane_width_max, plane_height_max; 9191 9192 /* 9193 * intel_mode_valid() should be 9194 * sufficient on older platforms. 9195 */ 9196 if (DISPLAY_VER(dev_priv) < 9) 9197 return MODE_OK; 9198 9199 /* 9200 * Most people will probably want a fullscreen 9201 * plane so let's not advertize modes that are 9202 * too big for that. 9203 */ 9204 if (DISPLAY_VER(dev_priv) >= 11) { 9205 plane_width_max = 5120 << bigjoiner; 9206 plane_height_max = 4320; 9207 } else { 9208 plane_width_max = 5120; 9209 plane_height_max = 4096; 9210 } 9211 9212 if (mode->hdisplay > plane_width_max) 9213 return MODE_H_ILLEGAL; 9214 9215 if (mode->vdisplay > plane_height_max) 9216 return MODE_V_ILLEGAL; 9217 9218 return MODE_OK; 9219 } 9220 9221 static const struct drm_mode_config_funcs intel_mode_funcs = { 9222 .fb_create = intel_user_framebuffer_create, 9223 .get_format_info = intel_fb_get_format_info, 9224 .output_poll_changed = intel_fbdev_output_poll_changed, 9225 .mode_valid = intel_mode_valid, 9226 .atomic_check = intel_atomic_check, 9227 .atomic_commit = intel_atomic_commit, 9228 .atomic_state_alloc = intel_atomic_state_alloc, 9229 .atomic_state_clear = intel_atomic_state_clear, 9230 .atomic_state_free = intel_atomic_state_free, 9231 }; 9232 9233 static const struct drm_i915_display_funcs skl_display_funcs = { 9234 .get_pipe_config = hsw_get_pipe_config, 9235 .crtc_enable = hsw_crtc_enable, 9236 .crtc_disable = hsw_crtc_disable, 9237 .commit_modeset_enables = skl_commit_modeset_enables, 9238 .get_initial_plane_config = skl_get_initial_plane_config, 9239 }; 9240 9241 static const struct drm_i915_display_funcs ddi_display_funcs = { 9242 .get_pipe_config = hsw_get_pipe_config, 9243 .crtc_enable = hsw_crtc_enable, 9244 .crtc_disable = hsw_crtc_disable, 9245 .commit_modeset_enables = intel_commit_modeset_enables, 9246 .get_initial_plane_config = i9xx_get_initial_plane_config, 9247 }; 9248 9249 static const struct drm_i915_display_funcs pch_split_display_funcs = { 9250 .get_pipe_config = ilk_get_pipe_config, 9251 .crtc_enable = ilk_crtc_enable, 9252 .crtc_disable = ilk_crtc_disable, 9253 .commit_modeset_enables = intel_commit_modeset_enables, 9254 .get_initial_plane_config = i9xx_get_initial_plane_config, 9255 }; 9256 9257 static const struct drm_i915_display_funcs vlv_display_funcs = { 9258 .get_pipe_config = i9xx_get_pipe_config, 9259 .crtc_enable = valleyview_crtc_enable, 9260 .crtc_disable = i9xx_crtc_disable, 9261 .commit_modeset_enables = intel_commit_modeset_enables, 9262 .get_initial_plane_config = i9xx_get_initial_plane_config, 9263 }; 9264 9265 static const struct drm_i915_display_funcs i9xx_display_funcs = { 9266 .get_pipe_config = i9xx_get_pipe_config, 9267 .crtc_enable = i9xx_crtc_enable, 9268 .crtc_disable = i9xx_crtc_disable, 9269 .commit_modeset_enables = intel_commit_modeset_enables, 9270 .get_initial_plane_config = i9xx_get_initial_plane_config, 9271 }; 9272 9273 /** 9274 * intel_init_display_hooks - initialize the display modesetting hooks 9275 * @dev_priv: device private 9276 */ 9277 void intel_init_display_hooks(struct drm_i915_private *dev_priv) 9278 { 9279 if (!HAS_DISPLAY(dev_priv)) 9280 return; 9281 9282 intel_init_cdclk_hooks(dev_priv); 9283 intel_audio_hooks_init(dev_priv); 9284 9285 intel_dpll_init_clock_hook(dev_priv); 9286 9287 if (DISPLAY_VER(dev_priv) >= 9) { 9288 dev_priv->display = &skl_display_funcs; 9289 } else if (HAS_DDI(dev_priv)) { 9290 dev_priv->display = &ddi_display_funcs; 9291 } else if (HAS_PCH_SPLIT(dev_priv)) { 9292 dev_priv->display = &pch_split_display_funcs; 9293 } else if (IS_CHERRYVIEW(dev_priv) || 9294 IS_VALLEYVIEW(dev_priv)) { 9295 dev_priv->display = &vlv_display_funcs; 9296 } else { 9297 dev_priv->display = &i9xx_display_funcs; 9298 } 9299 9300 intel_fdi_init_hook(dev_priv); 9301 } 9302 9303 void intel_modeset_init_hw(struct drm_i915_private *i915) 9304 { 9305 struct intel_cdclk_state *cdclk_state; 9306 9307 if (!HAS_DISPLAY(i915)) 9308 return; 9309 9310 cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state); 9311 9312 intel_update_cdclk(i915); 9313 intel_cdclk_dump_config(i915, &i915->cdclk.hw, "Current CDCLK"); 9314 cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw; 9315 } 9316 9317 static int sanitize_watermarks_add_affected(struct drm_atomic_state *state) 9318 { 9319 struct drm_plane *plane; 9320 struct intel_crtc *crtc; 9321 9322 for_each_intel_crtc(state->dev, crtc) { 9323 struct intel_crtc_state *crtc_state; 9324 9325 crtc_state = intel_atomic_get_crtc_state(state, crtc); 9326 if (IS_ERR(crtc_state)) 9327 return PTR_ERR(crtc_state); 9328 9329 if (crtc_state->hw.active) { 9330 /* 9331 * Preserve the inherited flag to avoid 9332 * taking the full modeset path. 9333 */ 9334 crtc_state->inherited = true; 9335 } 9336 } 9337 9338 drm_for_each_plane(plane, state->dev) { 9339 struct drm_plane_state *plane_state; 9340 9341 plane_state = drm_atomic_get_plane_state(state, plane); 9342 if (IS_ERR(plane_state)) 9343 return PTR_ERR(plane_state); 9344 } 9345 9346 return 0; 9347 } 9348 9349 /* 9350 * Calculate what we think the watermarks should be for the state we've read 9351 * out of the hardware and then immediately program those watermarks so that 9352 * we ensure the hardware settings match our internal state. 9353 * 9354 * We can calculate what we think WM's should be by creating a duplicate of the 9355 * current state (which was constructed during hardware readout) and running it 9356 * through the atomic check code to calculate new watermark values in the 9357 * state object. 9358 */ 9359 static void sanitize_watermarks(struct drm_i915_private *dev_priv) 9360 { 9361 struct drm_atomic_state *state; 9362 struct intel_atomic_state *intel_state; 9363 struct intel_crtc *crtc; 9364 struct intel_crtc_state *crtc_state; 9365 struct drm_modeset_acquire_ctx ctx; 9366 int ret; 9367 int i; 9368 9369 /* Only supported on platforms that use atomic watermark design */ 9370 if (!dev_priv->wm_disp->optimize_watermarks) 9371 return; 9372 9373 state = drm_atomic_state_alloc(&dev_priv->drm); 9374 if (drm_WARN_ON(&dev_priv->drm, !state)) 9375 return; 9376 9377 intel_state = to_intel_atomic_state(state); 9378 9379 drm_modeset_acquire_init(&ctx, 0); 9380 9381 retry: 9382 state->acquire_ctx = &ctx; 9383 9384 /* 9385 * Hardware readout is the only time we don't want to calculate 9386 * intermediate watermarks (since we don't trust the current 9387 * watermarks). 9388 */ 9389 if (!HAS_GMCH(dev_priv)) 9390 intel_state->skip_intermediate_wm = true; 9391 9392 ret = sanitize_watermarks_add_affected(state); 9393 if (ret) 9394 goto fail; 9395 9396 ret = intel_atomic_check(&dev_priv->drm, state); 9397 if (ret) 9398 goto fail; 9399 9400 /* Write calculated watermark values back */ 9401 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) { 9402 crtc_state->wm.need_postvbl_update = true; 9403 intel_optimize_watermarks(intel_state, crtc); 9404 9405 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm; 9406 } 9407 9408 fail: 9409 if (ret == -EDEADLK) { 9410 drm_atomic_state_clear(state); 9411 drm_modeset_backoff(&ctx); 9412 goto retry; 9413 } 9414 9415 /* 9416 * If we fail here, it means that the hardware appears to be 9417 * programmed in a way that shouldn't be possible, given our 9418 * understanding of watermark requirements. This might mean a 9419 * mistake in the hardware readout code or a mistake in the 9420 * watermark calculations for a given platform. Raise a WARN 9421 * so that this is noticeable. 9422 * 9423 * If this actually happens, we'll have to just leave the 9424 * BIOS-programmed watermarks untouched and hope for the best. 9425 */ 9426 drm_WARN(&dev_priv->drm, ret, 9427 "Could not determine valid watermarks for inherited state\n"); 9428 9429 drm_atomic_state_put(state); 9430 9431 drm_modeset_drop_locks(&ctx); 9432 drm_modeset_acquire_fini(&ctx); 9433 } 9434 9435 static int intel_initial_commit(struct drm_device *dev) 9436 { 9437 struct drm_atomic_state *state = NULL; 9438 struct drm_modeset_acquire_ctx ctx; 9439 struct intel_crtc *crtc; 9440 int ret = 0; 9441 9442 state = drm_atomic_state_alloc(dev); 9443 if (!state) 9444 return -ENOMEM; 9445 9446 drm_modeset_acquire_init(&ctx, 0); 9447 9448 retry: 9449 state->acquire_ctx = &ctx; 9450 9451 for_each_intel_crtc(dev, crtc) { 9452 struct intel_crtc_state *crtc_state = 9453 intel_atomic_get_crtc_state(state, crtc); 9454 9455 if (IS_ERR(crtc_state)) { 9456 ret = PTR_ERR(crtc_state); 9457 goto out; 9458 } 9459 9460 if (crtc_state->hw.active) { 9461 struct intel_encoder *encoder; 9462 9463 /* 9464 * We've not yet detected sink capabilities 9465 * (audio,infoframes,etc.) and thus we don't want to 9466 * force a full state recomputation yet. We want that to 9467 * happen only for the first real commit from userspace. 9468 * So preserve the inherited flag for the time being. 9469 */ 9470 crtc_state->inherited = true; 9471 9472 ret = drm_atomic_add_affected_planes(state, &crtc->base); 9473 if (ret) 9474 goto out; 9475 9476 /* 9477 * FIXME hack to force a LUT update to avoid the 9478 * plane update forcing the pipe gamma on without 9479 * having a proper LUT loaded. Remove once we 9480 * have readout for pipe gamma enable. 9481 */ 9482 crtc_state->uapi.color_mgmt_changed = true; 9483 9484 for_each_intel_encoder_mask(dev, encoder, 9485 crtc_state->uapi.encoder_mask) { 9486 if (encoder->initial_fastset_check && 9487 !encoder->initial_fastset_check(encoder, crtc_state)) { 9488 ret = drm_atomic_add_affected_connectors(state, 9489 &crtc->base); 9490 if (ret) 9491 goto out; 9492 } 9493 } 9494 } 9495 } 9496 9497 ret = drm_atomic_commit(state); 9498 9499 out: 9500 if (ret == -EDEADLK) { 9501 drm_atomic_state_clear(state); 9502 drm_modeset_backoff(&ctx); 9503 goto retry; 9504 } 9505 9506 drm_atomic_state_put(state); 9507 9508 drm_modeset_drop_locks(&ctx); 9509 drm_modeset_acquire_fini(&ctx); 9510 9511 return ret; 9512 } 9513 9514 static void intel_mode_config_init(struct drm_i915_private *i915) 9515 { 9516 struct drm_mode_config *mode_config = &i915->drm.mode_config; 9517 9518 drm_mode_config_init(&i915->drm); 9519 INIT_LIST_HEAD(&i915->global_obj_list); 9520 9521 mode_config->min_width = 0; 9522 mode_config->min_height = 0; 9523 9524 mode_config->preferred_depth = 24; 9525 mode_config->prefer_shadow = 1; 9526 9527 mode_config->funcs = &intel_mode_funcs; 9528 9529 mode_config->async_page_flip = HAS_ASYNC_FLIPS(i915); 9530 9531 /* 9532 * Maximum framebuffer dimensions, chosen to match 9533 * the maximum render engine surface size on gen4+. 9534 */ 9535 if (DISPLAY_VER(i915) >= 7) { 9536 mode_config->max_width = 16384; 9537 mode_config->max_height = 16384; 9538 } else if (DISPLAY_VER(i915) >= 4) { 9539 mode_config->max_width = 8192; 9540 mode_config->max_height = 8192; 9541 } else if (DISPLAY_VER(i915) == 3) { 9542 mode_config->max_width = 4096; 9543 mode_config->max_height = 4096; 9544 } else { 9545 mode_config->max_width = 2048; 9546 mode_config->max_height = 2048; 9547 } 9548 9549 if (IS_I845G(i915) || IS_I865G(i915)) { 9550 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512; 9551 mode_config->cursor_height = 1023; 9552 } else if (IS_I830(i915) || IS_I85X(i915) || 9553 IS_I915G(i915) || IS_I915GM(i915)) { 9554 mode_config->cursor_width = 64; 9555 mode_config->cursor_height = 64; 9556 } else { 9557 mode_config->cursor_width = 256; 9558 mode_config->cursor_height = 256; 9559 } 9560 } 9561 9562 static void intel_mode_config_cleanup(struct drm_i915_private *i915) 9563 { 9564 intel_atomic_global_obj_cleanup(i915); 9565 drm_mode_config_cleanup(&i915->drm); 9566 } 9567 9568 /* part #1: call before irq install */ 9569 int intel_modeset_init_noirq(struct drm_i915_private *i915) 9570 { 9571 int ret; 9572 9573 if (i915_inject_probe_failure(i915)) 9574 return -ENODEV; 9575 9576 if (HAS_DISPLAY(i915)) { 9577 ret = drm_vblank_init(&i915->drm, 9578 INTEL_NUM_PIPES(i915)); 9579 if (ret) 9580 return ret; 9581 } 9582 9583 intel_bios_init(i915); 9584 9585 ret = intel_vga_register(i915); 9586 if (ret) 9587 goto cleanup_bios; 9588 9589 /* FIXME: completely on the wrong abstraction layer */ 9590 intel_power_domains_init_hw(i915, false); 9591 9592 if (!HAS_DISPLAY(i915)) 9593 return 0; 9594 9595 intel_dmc_ucode_init(i915); 9596 9597 i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0); 9598 i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI | 9599 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE); 9600 9601 i915->window2_delay = 0; /* No DSB so no window2 delay */ 9602 9603 intel_mode_config_init(i915); 9604 9605 ret = intel_cdclk_init(i915); 9606 if (ret) 9607 goto cleanup_vga_client_pw_domain_dmc; 9608 9609 ret = intel_dbuf_init(i915); 9610 if (ret) 9611 goto cleanup_vga_client_pw_domain_dmc; 9612 9613 ret = intel_bw_init(i915); 9614 if (ret) 9615 goto cleanup_vga_client_pw_domain_dmc; 9616 9617 init_llist_head(&i915->atomic_helper.free_list); 9618 INIT_WORK(&i915->atomic_helper.free_work, 9619 intel_atomic_helper_free_state_worker); 9620 9621 intel_init_quirks(i915); 9622 9623 intel_fbc_init(i915); 9624 9625 return 0; 9626 9627 cleanup_vga_client_pw_domain_dmc: 9628 intel_dmc_ucode_fini(i915); 9629 intel_power_domains_driver_remove(i915); 9630 intel_vga_unregister(i915); 9631 cleanup_bios: 9632 intel_bios_driver_remove(i915); 9633 9634 return ret; 9635 } 9636 9637 /* part #2: call after irq install, but before gem init */ 9638 int intel_modeset_init_nogem(struct drm_i915_private *i915) 9639 { 9640 struct drm_device *dev = &i915->drm; 9641 enum pipe pipe; 9642 struct intel_crtc *crtc; 9643 int ret; 9644 9645 if (!HAS_DISPLAY(i915)) 9646 return 0; 9647 9648 intel_init_pm(i915); 9649 9650 intel_panel_sanitize_ssc(i915); 9651 9652 intel_pps_setup(i915); 9653 9654 intel_gmbus_setup(i915); 9655 9656 drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n", 9657 INTEL_NUM_PIPES(i915), 9658 INTEL_NUM_PIPES(i915) > 1 ? "s" : ""); 9659 9660 for_each_pipe(i915, pipe) { 9661 ret = intel_crtc_init(i915, pipe); 9662 if (ret) { 9663 intel_mode_config_cleanup(i915); 9664 return ret; 9665 } 9666 } 9667 9668 intel_plane_possible_crtcs_init(i915); 9669 intel_shared_dpll_init(i915); 9670 intel_fdi_pll_freq_update(i915); 9671 9672 intel_update_czclk(i915); 9673 intel_modeset_init_hw(i915); 9674 intel_dpll_update_ref_clks(i915); 9675 9676 intel_hdcp_component_init(i915); 9677 9678 if (i915->max_cdclk_freq == 0) 9679 intel_update_max_cdclk(i915); 9680 9681 /* 9682 * If the platform has HTI, we need to find out whether it has reserved 9683 * any display resources before we create our display outputs. 9684 */ 9685 if (INTEL_INFO(i915)->display.has_hti) 9686 i915->hti_state = intel_de_read(i915, HDPORT_STATE); 9687 9688 /* Just disable it once at startup */ 9689 intel_vga_disable(i915); 9690 intel_setup_outputs(i915); 9691 9692 drm_modeset_lock_all(dev); 9693 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx); 9694 intel_acpi_assign_connector_fwnodes(i915); 9695 drm_modeset_unlock_all(dev); 9696 9697 for_each_intel_crtc(dev, crtc) { 9698 if (!to_intel_crtc_state(crtc->base.state)->uapi.active) 9699 continue; 9700 intel_crtc_initial_plane_config(crtc); 9701 } 9702 9703 /* 9704 * Make sure hardware watermarks really match the state we read out. 9705 * Note that we need to do this after reconstructing the BIOS fb's 9706 * since the watermark calculation done here will use pstate->fb. 9707 */ 9708 if (!HAS_GMCH(i915)) 9709 sanitize_watermarks(i915); 9710 9711 return 0; 9712 } 9713 9714 /* part #3: call after gem init */ 9715 int intel_modeset_init(struct drm_i915_private *i915) 9716 { 9717 int ret; 9718 9719 if (!HAS_DISPLAY(i915)) 9720 return 0; 9721 9722 /* 9723 * Force all active planes to recompute their states. So that on 9724 * mode_setcrtc after probe, all the intel_plane_state variables 9725 * are already calculated and there is no assert_plane warnings 9726 * during bootup. 9727 */ 9728 ret = intel_initial_commit(&i915->drm); 9729 if (ret) 9730 drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret); 9731 9732 intel_overlay_setup(i915); 9733 9734 ret = intel_fbdev_init(&i915->drm); 9735 if (ret) 9736 return ret; 9737 9738 /* Only enable hotplug handling once the fbdev is fully set up. */ 9739 intel_hpd_init(i915); 9740 intel_hpd_poll_disable(i915); 9741 9742 intel_init_ipc(i915); 9743 9744 return 0; 9745 } 9746 9747 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 9748 { 9749 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 9750 /* 640x480@60Hz, ~25175 kHz */ 9751 struct dpll clock = { 9752 .m1 = 18, 9753 .m2 = 7, 9754 .p1 = 13, 9755 .p2 = 4, 9756 .n = 2, 9757 }; 9758 u32 dpll, fp; 9759 int i; 9760 9761 drm_WARN_ON(&dev_priv->drm, 9762 i9xx_calc_dpll_params(48000, &clock) != 25154); 9763 9764 drm_dbg_kms(&dev_priv->drm, 9765 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n", 9766 pipe_name(pipe), clock.vco, clock.dot); 9767 9768 fp = i9xx_dpll_compute_fp(&clock); 9769 dpll = DPLL_DVO_2X_MODE | 9770 DPLL_VGA_MODE_DIS | 9771 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | 9772 PLL_P2_DIVIDE_BY_4 | 9773 PLL_REF_INPUT_DREFCLK | 9774 DPLL_VCO_ENABLE; 9775 9776 intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16)); 9777 intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16)); 9778 intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16)); 9779 intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16)); 9780 intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16)); 9781 intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16)); 9782 intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1)); 9783 9784 intel_de_write(dev_priv, FP0(pipe), fp); 9785 intel_de_write(dev_priv, FP1(pipe), fp); 9786 9787 /* 9788 * Apparently we need to have VGA mode enabled prior to changing 9789 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 9790 * dividers, even though the register value does change. 9791 */ 9792 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); 9793 intel_de_write(dev_priv, DPLL(pipe), dpll); 9794 9795 /* Wait for the clocks to stabilize. */ 9796 intel_de_posting_read(dev_priv, DPLL(pipe)); 9797 udelay(150); 9798 9799 /* The pixel multiplier can only be updated once the 9800 * DPLL is enabled and the clocks are stable. 9801 * 9802 * So write it again. 9803 */ 9804 intel_de_write(dev_priv, DPLL(pipe), dpll); 9805 9806 /* We do this three times for luck */ 9807 for (i = 0; i < 3 ; i++) { 9808 intel_de_write(dev_priv, DPLL(pipe), dpll); 9809 intel_de_posting_read(dev_priv, DPLL(pipe)); 9810 udelay(150); /* wait for warmup */ 9811 } 9812 9813 intel_de_write(dev_priv, PIPECONF(pipe), PIPECONF_ENABLE); 9814 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 9815 9816 intel_wait_for_pipe_scanline_moving(crtc); 9817 } 9818 9819 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 9820 { 9821 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 9822 9823 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n", 9824 pipe_name(pipe)); 9825 9826 drm_WARN_ON(&dev_priv->drm, 9827 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE); 9828 drm_WARN_ON(&dev_priv->drm, 9829 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE); 9830 drm_WARN_ON(&dev_priv->drm, 9831 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE); 9832 drm_WARN_ON(&dev_priv->drm, 9833 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK); 9834 drm_WARN_ON(&dev_priv->drm, 9835 intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK); 9836 9837 intel_de_write(dev_priv, PIPECONF(pipe), 0); 9838 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 9839 9840 intel_wait_for_pipe_scanline_stopped(crtc); 9841 9842 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); 9843 intel_de_posting_read(dev_priv, DPLL(pipe)); 9844 } 9845 9846 static void 9847 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv) 9848 { 9849 struct intel_crtc *crtc; 9850 9851 if (DISPLAY_VER(dev_priv) >= 4) 9852 return; 9853 9854 for_each_intel_crtc(&dev_priv->drm, crtc) { 9855 struct intel_plane *plane = 9856 to_intel_plane(crtc->base.primary); 9857 struct intel_crtc *plane_crtc; 9858 enum pipe pipe; 9859 9860 if (!plane->get_hw_state(plane, &pipe)) 9861 continue; 9862 9863 if (pipe == crtc->pipe) 9864 continue; 9865 9866 drm_dbg_kms(&dev_priv->drm, 9867 "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n", 9868 plane->base.base.id, plane->base.name); 9869 9870 plane_crtc = intel_crtc_for_pipe(dev_priv, pipe); 9871 intel_plane_disable_noatomic(plane_crtc, plane); 9872 } 9873 } 9874 9875 static bool intel_crtc_has_encoders(struct intel_crtc *crtc) 9876 { 9877 struct drm_device *dev = crtc->base.dev; 9878 struct intel_encoder *encoder; 9879 9880 for_each_encoder_on_crtc(dev, &crtc->base, encoder) 9881 return true; 9882 9883 return false; 9884 } 9885 9886 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) 9887 { 9888 struct drm_device *dev = encoder->base.dev; 9889 struct intel_connector *connector; 9890 9891 for_each_connector_on_encoder(dev, &encoder->base, connector) 9892 return connector; 9893 9894 return NULL; 9895 } 9896 9897 static void intel_sanitize_crtc(struct intel_crtc *crtc, 9898 struct drm_modeset_acquire_ctx *ctx) 9899 { 9900 struct drm_device *dev = crtc->base.dev; 9901 struct drm_i915_private *dev_priv = to_i915(dev); 9902 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); 9903 9904 if (crtc_state->hw.active) { 9905 struct intel_plane *plane; 9906 9907 /* Disable everything but the primary plane */ 9908 for_each_intel_plane_on_crtc(dev, crtc, plane) { 9909 const struct intel_plane_state *plane_state = 9910 to_intel_plane_state(plane->base.state); 9911 9912 if (plane_state->uapi.visible && 9913 plane->base.type != DRM_PLANE_TYPE_PRIMARY) 9914 intel_plane_disable_noatomic(crtc, plane); 9915 } 9916 9917 /* Disable any background color/etc. set by the BIOS */ 9918 intel_color_commit_noarm(crtc_state); 9919 intel_color_commit_arm(crtc_state); 9920 } 9921 9922 /* Adjust the state of the output pipe according to whether we 9923 * have active connectors/encoders. */ 9924 if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) && 9925 !intel_crtc_is_bigjoiner_slave(crtc_state)) 9926 intel_crtc_disable_noatomic(crtc, ctx); 9927 9928 if (crtc_state->hw.active || HAS_GMCH(dev_priv)) { 9929 /* 9930 * We start out with underrun reporting disabled to avoid races. 9931 * For correct bookkeeping mark this on active crtcs. 9932 * 9933 * Also on gmch platforms we dont have any hardware bits to 9934 * disable the underrun reporting. Which means we need to start 9935 * out with underrun reporting disabled also on inactive pipes, 9936 * since otherwise we'll complain about the garbage we read when 9937 * e.g. coming up after runtime pm. 9938 * 9939 * No protection against concurrent access is required - at 9940 * worst a fifo underrun happens which also sets this to false. 9941 */ 9942 crtc->cpu_fifo_underrun_disabled = true; 9943 /* 9944 * We track the PCH trancoder underrun reporting state 9945 * within the crtc. With crtc for pipe A housing the underrun 9946 * reporting state for PCH transcoder A, crtc for pipe B housing 9947 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, 9948 * and marking underrun reporting as disabled for the non-existing 9949 * PCH transcoders B and C would prevent enabling the south 9950 * error interrupt (see cpt_can_enable_serr_int()). 9951 */ 9952 if (intel_has_pch_trancoder(dev_priv, crtc->pipe)) 9953 crtc->pch_fifo_underrun_disabled = true; 9954 } 9955 } 9956 9957 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state) 9958 { 9959 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 9960 9961 /* 9962 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram 9963 * the hardware when a high res displays plugged in. DPLL P 9964 * divider is zero, and the pipe timings are bonkers. We'll 9965 * try to disable everything in that case. 9966 * 9967 * FIXME would be nice to be able to sanitize this state 9968 * without several WARNs, but for now let's take the easy 9969 * road. 9970 */ 9971 return IS_SANDYBRIDGE(dev_priv) && 9972 crtc_state->hw.active && 9973 crtc_state->shared_dpll && 9974 crtc_state->port_clock == 0; 9975 } 9976 9977 static void intel_sanitize_encoder(struct intel_encoder *encoder) 9978 { 9979 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 9980 struct intel_connector *connector; 9981 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 9982 struct intel_crtc_state *crtc_state = crtc ? 9983 to_intel_crtc_state(crtc->base.state) : NULL; 9984 9985 /* We need to check both for a crtc link (meaning that the 9986 * encoder is active and trying to read from a pipe) and the 9987 * pipe itself being active. */ 9988 bool has_active_crtc = crtc_state && 9989 crtc_state->hw.active; 9990 9991 if (crtc_state && has_bogus_dpll_config(crtc_state)) { 9992 drm_dbg_kms(&dev_priv->drm, 9993 "BIOS has misprogrammed the hardware. Disabling pipe %c\n", 9994 pipe_name(crtc->pipe)); 9995 has_active_crtc = false; 9996 } 9997 9998 connector = intel_encoder_find_connector(encoder); 9999 if (connector && !has_active_crtc) { 10000 drm_dbg_kms(&dev_priv->drm, 10001 "[ENCODER:%d:%s] has active connectors but no active pipe!\n", 10002 encoder->base.base.id, 10003 encoder->base.name); 10004 10005 /* Connector is active, but has no active pipe. This is 10006 * fallout from our resume register restoring. Disable 10007 * the encoder manually again. */ 10008 if (crtc_state) { 10009 struct drm_encoder *best_encoder; 10010 10011 drm_dbg_kms(&dev_priv->drm, 10012 "[ENCODER:%d:%s] manually disabled\n", 10013 encoder->base.base.id, 10014 encoder->base.name); 10015 10016 /* avoid oopsing in case the hooks consult best_encoder */ 10017 best_encoder = connector->base.state->best_encoder; 10018 connector->base.state->best_encoder = &encoder->base; 10019 10020 /* FIXME NULL atomic state passed! */ 10021 if (encoder->disable) 10022 encoder->disable(NULL, encoder, crtc_state, 10023 connector->base.state); 10024 if (encoder->post_disable) 10025 encoder->post_disable(NULL, encoder, crtc_state, 10026 connector->base.state); 10027 10028 connector->base.state->best_encoder = best_encoder; 10029 } 10030 encoder->base.crtc = NULL; 10031 10032 /* Inconsistent output/port/pipe state happens presumably due to 10033 * a bug in one of the get_hw_state functions. Or someplace else 10034 * in our code, like the register restore mess on resume. Clamp 10035 * things to off as a safer default. */ 10036 10037 connector->base.dpms = DRM_MODE_DPMS_OFF; 10038 connector->base.encoder = NULL; 10039 } 10040 10041 /* notify opregion of the sanitized encoder state */ 10042 intel_opregion_notify_encoder(encoder, connector && has_active_crtc); 10043 10044 if (HAS_DDI(dev_priv)) 10045 intel_ddi_sanitize_encoder_pll_mapping(encoder); 10046 } 10047 10048 /* FIXME read out full plane state for all planes */ 10049 static void readout_plane_state(struct drm_i915_private *dev_priv) 10050 { 10051 struct intel_plane *plane; 10052 struct intel_crtc *crtc; 10053 10054 for_each_intel_plane(&dev_priv->drm, plane) { 10055 struct intel_plane_state *plane_state = 10056 to_intel_plane_state(plane->base.state); 10057 struct intel_crtc_state *crtc_state; 10058 enum pipe pipe = PIPE_A; 10059 bool visible; 10060 10061 visible = plane->get_hw_state(plane, &pipe); 10062 10063 crtc = intel_crtc_for_pipe(dev_priv, pipe); 10064 crtc_state = to_intel_crtc_state(crtc->base.state); 10065 10066 intel_set_plane_visible(crtc_state, plane_state, visible); 10067 10068 drm_dbg_kms(&dev_priv->drm, 10069 "[PLANE:%d:%s] hw state readout: %s, pipe %c\n", 10070 plane->base.base.id, plane->base.name, 10071 str_enabled_disabled(visible), pipe_name(pipe)); 10072 } 10073 10074 for_each_intel_crtc(&dev_priv->drm, crtc) { 10075 struct intel_crtc_state *crtc_state = 10076 to_intel_crtc_state(crtc->base.state); 10077 10078 fixup_plane_bitmasks(crtc_state); 10079 } 10080 } 10081 10082 static void intel_modeset_readout_hw_state(struct drm_device *dev) 10083 { 10084 struct drm_i915_private *dev_priv = to_i915(dev); 10085 struct intel_cdclk_state *cdclk_state = 10086 to_intel_cdclk_state(dev_priv->cdclk.obj.state); 10087 struct intel_dbuf_state *dbuf_state = 10088 to_intel_dbuf_state(dev_priv->dbuf.obj.state); 10089 enum pipe pipe; 10090 struct intel_crtc *crtc; 10091 struct intel_encoder *encoder; 10092 struct intel_connector *connector; 10093 struct drm_connector_list_iter conn_iter; 10094 u8 active_pipes = 0; 10095 10096 for_each_intel_crtc(dev, crtc) { 10097 struct intel_crtc_state *crtc_state = 10098 to_intel_crtc_state(crtc->base.state); 10099 10100 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi); 10101 intel_crtc_free_hw_state(crtc_state); 10102 intel_crtc_state_reset(crtc_state, crtc); 10103 10104 intel_crtc_get_pipe_config(crtc_state); 10105 10106 crtc_state->hw.enable = crtc_state->hw.active; 10107 10108 crtc->base.enabled = crtc_state->hw.enable; 10109 crtc->active = crtc_state->hw.active; 10110 10111 if (crtc_state->hw.active) 10112 active_pipes |= BIT(crtc->pipe); 10113 10114 drm_dbg_kms(&dev_priv->drm, 10115 "[CRTC:%d:%s] hw state readout: %s\n", 10116 crtc->base.base.id, crtc->base.name, 10117 str_enabled_disabled(crtc_state->hw.active)); 10118 } 10119 10120 cdclk_state->active_pipes = dbuf_state->active_pipes = active_pipes; 10121 10122 readout_plane_state(dev_priv); 10123 10124 for_each_intel_encoder(dev, encoder) { 10125 struct intel_crtc_state *crtc_state = NULL; 10126 10127 pipe = 0; 10128 10129 if (encoder->get_hw_state(encoder, &pipe)) { 10130 crtc = intel_crtc_for_pipe(dev_priv, pipe); 10131 crtc_state = to_intel_crtc_state(crtc->base.state); 10132 10133 encoder->base.crtc = &crtc->base; 10134 intel_encoder_get_config(encoder, crtc_state); 10135 10136 /* read out to slave crtc as well for bigjoiner */ 10137 if (crtc_state->bigjoiner_pipes) { 10138 struct intel_crtc *slave_crtc; 10139 10140 /* encoder should read be linked to bigjoiner master */ 10141 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 10142 10143 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc, 10144 intel_crtc_bigjoiner_slave_pipes(crtc_state)) { 10145 struct intel_crtc_state *slave_crtc_state; 10146 10147 slave_crtc_state = to_intel_crtc_state(slave_crtc->base.state); 10148 intel_encoder_get_config(encoder, slave_crtc_state); 10149 } 10150 } 10151 } else { 10152 encoder->base.crtc = NULL; 10153 } 10154 10155 if (encoder->sync_state) 10156 encoder->sync_state(encoder, crtc_state); 10157 10158 drm_dbg_kms(&dev_priv->drm, 10159 "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", 10160 encoder->base.base.id, encoder->base.name, 10161 str_enabled_disabled(encoder->base.crtc), 10162 pipe_name(pipe)); 10163 } 10164 10165 intel_dpll_readout_hw_state(dev_priv); 10166 10167 drm_connector_list_iter_begin(dev, &conn_iter); 10168 for_each_intel_connector_iter(connector, &conn_iter) { 10169 if (connector->get_hw_state(connector)) { 10170 struct intel_crtc_state *crtc_state; 10171 struct intel_crtc *crtc; 10172 10173 connector->base.dpms = DRM_MODE_DPMS_ON; 10174 10175 encoder = intel_attached_encoder(connector); 10176 connector->base.encoder = &encoder->base; 10177 10178 crtc = to_intel_crtc(encoder->base.crtc); 10179 crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL; 10180 10181 if (crtc_state && crtc_state->hw.active) { 10182 /* 10183 * This has to be done during hardware readout 10184 * because anything calling .crtc_disable may 10185 * rely on the connector_mask being accurate. 10186 */ 10187 crtc_state->uapi.connector_mask |= 10188 drm_connector_mask(&connector->base); 10189 crtc_state->uapi.encoder_mask |= 10190 drm_encoder_mask(&encoder->base); 10191 } 10192 } else { 10193 connector->base.dpms = DRM_MODE_DPMS_OFF; 10194 connector->base.encoder = NULL; 10195 } 10196 drm_dbg_kms(&dev_priv->drm, 10197 "[CONNECTOR:%d:%s] hw state readout: %s\n", 10198 connector->base.base.id, connector->base.name, 10199 str_enabled_disabled(connector->base.encoder)); 10200 } 10201 drm_connector_list_iter_end(&conn_iter); 10202 10203 for_each_intel_crtc(dev, crtc) { 10204 struct intel_bw_state *bw_state = 10205 to_intel_bw_state(dev_priv->bw_obj.state); 10206 struct intel_crtc_state *crtc_state = 10207 to_intel_crtc_state(crtc->base.state); 10208 struct intel_plane *plane; 10209 int min_cdclk = 0; 10210 10211 if (crtc_state->hw.active) { 10212 /* 10213 * The initial mode needs to be set in order to keep 10214 * the atomic core happy. It wants a valid mode if the 10215 * crtc's enabled, so we do the above call. 10216 * 10217 * But we don't set all the derived state fully, hence 10218 * set a flag to indicate that a full recalculation is 10219 * needed on the next commit. 10220 */ 10221 crtc_state->inherited = true; 10222 10223 intel_crtc_update_active_timings(crtc_state); 10224 10225 intel_crtc_copy_hw_to_uapi_state(crtc_state); 10226 } 10227 10228 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 10229 const struct intel_plane_state *plane_state = 10230 to_intel_plane_state(plane->base.state); 10231 10232 /* 10233 * FIXME don't have the fb yet, so can't 10234 * use intel_plane_data_rate() :( 10235 */ 10236 if (plane_state->uapi.visible) 10237 crtc_state->data_rate[plane->id] = 10238 4 * crtc_state->pixel_rate; 10239 /* 10240 * FIXME don't have the fb yet, so can't 10241 * use plane->min_cdclk() :( 10242 */ 10243 if (plane_state->uapi.visible && plane->min_cdclk) { 10244 if (crtc_state->double_wide || DISPLAY_VER(dev_priv) >= 10) 10245 crtc_state->min_cdclk[plane->id] = 10246 DIV_ROUND_UP(crtc_state->pixel_rate, 2); 10247 else 10248 crtc_state->min_cdclk[plane->id] = 10249 crtc_state->pixel_rate; 10250 } 10251 drm_dbg_kms(&dev_priv->drm, 10252 "[PLANE:%d:%s] min_cdclk %d kHz\n", 10253 plane->base.base.id, plane->base.name, 10254 crtc_state->min_cdclk[plane->id]); 10255 } 10256 10257 if (crtc_state->hw.active) { 10258 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); 10259 if (drm_WARN_ON(dev, min_cdclk < 0)) 10260 min_cdclk = 0; 10261 } 10262 10263 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; 10264 cdclk_state->min_voltage_level[crtc->pipe] = 10265 crtc_state->min_voltage_level; 10266 10267 intel_bw_crtc_update(bw_state, crtc_state); 10268 10269 intel_pipe_config_sanity_check(dev_priv, crtc_state); 10270 } 10271 } 10272 10273 static void 10274 get_encoder_power_domains(struct drm_i915_private *dev_priv) 10275 { 10276 struct intel_encoder *encoder; 10277 10278 for_each_intel_encoder(&dev_priv->drm, encoder) { 10279 struct intel_crtc_state *crtc_state; 10280 10281 if (!encoder->get_power_domains) 10282 continue; 10283 10284 /* 10285 * MST-primary and inactive encoders don't have a crtc state 10286 * and neither of these require any power domain references. 10287 */ 10288 if (!encoder->base.crtc) 10289 continue; 10290 10291 crtc_state = to_intel_crtc_state(encoder->base.crtc->state); 10292 encoder->get_power_domains(encoder, crtc_state); 10293 } 10294 } 10295 10296 static void intel_early_display_was(struct drm_i915_private *dev_priv) 10297 { 10298 /* 10299 * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl 10300 * Also known as Wa_14010480278. 10301 */ 10302 if (IS_DISPLAY_VER(dev_priv, 10, 12)) 10303 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0, 10304 intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS); 10305 10306 if (IS_HASWELL(dev_priv)) { 10307 /* 10308 * WaRsPkgCStateDisplayPMReq:hsw 10309 * System hang if this isn't done before disabling all planes! 10310 */ 10311 intel_de_write(dev_priv, CHICKEN_PAR1_1, 10312 intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); 10313 } 10314 10315 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) { 10316 /* Display WA #1142:kbl,cfl,cml */ 10317 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 10318 KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22); 10319 intel_de_rmw(dev_priv, CHICKEN_MISC_2, 10320 KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14, 10321 KBL_ARB_FILL_SPARE_14); 10322 } 10323 } 10324 10325 10326 /* Scan out the current hw modeset state, 10327 * and sanitizes it to the current state 10328 */ 10329 static void 10330 intel_modeset_setup_hw_state(struct drm_device *dev, 10331 struct drm_modeset_acquire_ctx *ctx) 10332 { 10333 struct drm_i915_private *dev_priv = to_i915(dev); 10334 struct intel_encoder *encoder; 10335 struct intel_crtc *crtc; 10336 intel_wakeref_t wakeref; 10337 10338 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 10339 10340 intel_early_display_was(dev_priv); 10341 intel_modeset_readout_hw_state(dev); 10342 10343 /* HW state is read out, now we need to sanitize this mess. */ 10344 get_encoder_power_domains(dev_priv); 10345 10346 intel_pch_sanitize(dev_priv); 10347 10348 /* 10349 * intel_sanitize_plane_mapping() may need to do vblank 10350 * waits, so we need vblank interrupts restored beforehand. 10351 */ 10352 for_each_intel_crtc(&dev_priv->drm, crtc) { 10353 struct intel_crtc_state *crtc_state = 10354 to_intel_crtc_state(crtc->base.state); 10355 10356 drm_crtc_vblank_reset(&crtc->base); 10357 10358 if (crtc_state->hw.active) 10359 intel_crtc_vblank_on(crtc_state); 10360 } 10361 10362 intel_fbc_sanitize(dev_priv); 10363 10364 intel_sanitize_plane_mapping(dev_priv); 10365 10366 for_each_intel_encoder(dev, encoder) 10367 intel_sanitize_encoder(encoder); 10368 10369 for_each_intel_crtc(&dev_priv->drm, crtc) { 10370 struct intel_crtc_state *crtc_state = 10371 to_intel_crtc_state(crtc->base.state); 10372 10373 intel_sanitize_crtc(crtc, ctx); 10374 intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]"); 10375 } 10376 10377 intel_modeset_update_connector_atomic_state(dev); 10378 10379 intel_dpll_sanitize_state(dev_priv); 10380 10381 if (IS_G4X(dev_priv)) { 10382 g4x_wm_get_hw_state(dev_priv); 10383 g4x_wm_sanitize(dev_priv); 10384 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 10385 vlv_wm_get_hw_state(dev_priv); 10386 vlv_wm_sanitize(dev_priv); 10387 } else if (DISPLAY_VER(dev_priv) >= 9) { 10388 skl_wm_get_hw_state(dev_priv); 10389 skl_wm_sanitize(dev_priv); 10390 } else if (HAS_PCH_SPLIT(dev_priv)) { 10391 ilk_wm_get_hw_state(dev_priv); 10392 } 10393 10394 for_each_intel_crtc(dev, crtc) { 10395 struct intel_crtc_state *crtc_state = 10396 to_intel_crtc_state(crtc->base.state); 10397 struct intel_power_domain_mask put_domains; 10398 10399 modeset_get_crtc_power_domains(crtc_state, &put_domains); 10400 if (drm_WARN_ON(dev, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM))) 10401 modeset_put_crtc_power_domains(crtc, &put_domains); 10402 } 10403 10404 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref); 10405 10406 intel_power_domains_sanitize_state(dev_priv); 10407 } 10408 10409 void intel_display_resume(struct drm_device *dev) 10410 { 10411 struct drm_i915_private *dev_priv = to_i915(dev); 10412 struct drm_atomic_state *state = dev_priv->modeset_restore_state; 10413 struct drm_modeset_acquire_ctx ctx; 10414 int ret; 10415 10416 if (!HAS_DISPLAY(dev_priv)) 10417 return; 10418 10419 dev_priv->modeset_restore_state = NULL; 10420 if (state) 10421 state->acquire_ctx = &ctx; 10422 10423 drm_modeset_acquire_init(&ctx, 0); 10424 10425 while (1) { 10426 ret = drm_modeset_lock_all_ctx(dev, &ctx); 10427 if (ret != -EDEADLK) 10428 break; 10429 10430 drm_modeset_backoff(&ctx); 10431 } 10432 10433 if (!ret) 10434 ret = __intel_display_resume(dev, state, &ctx); 10435 10436 intel_enable_ipc(dev_priv); 10437 drm_modeset_drop_locks(&ctx); 10438 drm_modeset_acquire_fini(&ctx); 10439 10440 if (ret) 10441 drm_err(&dev_priv->drm, 10442 "Restoring old state failed with %i\n", ret); 10443 if (state) 10444 drm_atomic_state_put(state); 10445 } 10446 10447 static void intel_hpd_poll_fini(struct drm_i915_private *i915) 10448 { 10449 struct intel_connector *connector; 10450 struct drm_connector_list_iter conn_iter; 10451 10452 /* Kill all the work that may have been queued by hpd. */ 10453 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 10454 for_each_intel_connector_iter(connector, &conn_iter) { 10455 if (connector->modeset_retry_work.func) 10456 cancel_work_sync(&connector->modeset_retry_work); 10457 if (connector->hdcp.shim) { 10458 cancel_delayed_work_sync(&connector->hdcp.check_work); 10459 cancel_work_sync(&connector->hdcp.prop_work); 10460 } 10461 } 10462 drm_connector_list_iter_end(&conn_iter); 10463 } 10464 10465 /* part #1: call before irq uninstall */ 10466 void intel_modeset_driver_remove(struct drm_i915_private *i915) 10467 { 10468 if (!HAS_DISPLAY(i915)) 10469 return; 10470 10471 flush_workqueue(i915->flip_wq); 10472 flush_workqueue(i915->modeset_wq); 10473 10474 flush_work(&i915->atomic_helper.free_work); 10475 drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list)); 10476 } 10477 10478 /* part #2: call after irq uninstall */ 10479 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915) 10480 { 10481 if (!HAS_DISPLAY(i915)) 10482 return; 10483 10484 /* 10485 * Due to the hpd irq storm handling the hotplug work can re-arm the 10486 * poll handlers. Hence disable polling after hpd handling is shut down. 10487 */ 10488 intel_hpd_poll_fini(i915); 10489 10490 /* 10491 * MST topology needs to be suspended so we don't have any calls to 10492 * fbdev after it's finalized. MST will be destroyed later as part of 10493 * drm_mode_config_cleanup() 10494 */ 10495 intel_dp_mst_suspend(i915); 10496 10497 /* poll work can call into fbdev, hence clean that up afterwards */ 10498 intel_fbdev_fini(i915); 10499 10500 intel_unregister_dsm_handler(); 10501 10502 /* flush any delayed tasks or pending work */ 10503 flush_scheduled_work(); 10504 10505 intel_hdcp_component_fini(i915); 10506 10507 intel_mode_config_cleanup(i915); 10508 10509 intel_overlay_cleanup(i915); 10510 10511 intel_gmbus_teardown(i915); 10512 10513 destroy_workqueue(i915->flip_wq); 10514 destroy_workqueue(i915->modeset_wq); 10515 10516 intel_fbc_cleanup(i915); 10517 } 10518 10519 /* part #3: call after gem init */ 10520 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915) 10521 { 10522 intel_dmc_ucode_fini(i915); 10523 10524 intel_power_domains_driver_remove(i915); 10525 10526 intel_vga_unregister(i915); 10527 10528 intel_bios_driver_remove(i915); 10529 } 10530 10531 bool intel_modeset_probe_defer(struct pci_dev *pdev) 10532 { 10533 struct drm_privacy_screen *privacy_screen; 10534 10535 /* 10536 * apple-gmux is needed on dual GPU MacBook Pro 10537 * to probe the panel if we're the inactive GPU. 10538 */ 10539 if (vga_switcheroo_client_probe_defer(pdev)) 10540 return true; 10541 10542 /* If the LCD panel has a privacy-screen, wait for it */ 10543 privacy_screen = drm_privacy_screen_get(&pdev->dev, NULL); 10544 if (IS_ERR(privacy_screen) && PTR_ERR(privacy_screen) == -EPROBE_DEFER) 10545 return true; 10546 10547 drm_privacy_screen_put(privacy_screen); 10548 10549 return false; 10550 } 10551 10552 void intel_display_driver_register(struct drm_i915_private *i915) 10553 { 10554 if (!HAS_DISPLAY(i915)) 10555 return; 10556 10557 intel_display_debugfs_register(i915); 10558 10559 /* Must be done after probing outputs */ 10560 intel_opregion_register(i915); 10561 acpi_video_register(); 10562 10563 intel_audio_init(i915); 10564 10565 /* 10566 * Some ports require correctly set-up hpd registers for 10567 * detection to work properly (leading to ghost connected 10568 * connector status), e.g. VGA on gm45. Hence we can only set 10569 * up the initial fbdev config after hpd irqs are fully 10570 * enabled. We do it last so that the async config cannot run 10571 * before the connectors are registered. 10572 */ 10573 intel_fbdev_initial_config_async(&i915->drm); 10574 10575 /* 10576 * We need to coordinate the hotplugs with the asynchronous 10577 * fbdev configuration, for which we use the 10578 * fbdev->async_cookie. 10579 */ 10580 drm_kms_helper_poll_init(&i915->drm); 10581 } 10582 10583 void intel_display_driver_unregister(struct drm_i915_private *i915) 10584 { 10585 if (!HAS_DISPLAY(i915)) 10586 return; 10587 10588 intel_fbdev_unregister(i915); 10589 intel_audio_deinit(i915); 10590 10591 /* 10592 * After flushing the fbdev (incl. a late async config which 10593 * will have delayed queuing of a hotplug event), then flush 10594 * the hotplug events. 10595 */ 10596 drm_kms_helper_poll_fini(&i915->drm); 10597 drm_atomic_helper_shutdown(&i915->drm); 10598 10599 acpi_video_unregister(); 10600 intel_opregion_unregister(i915); 10601 } 10602 10603 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915) 10604 { 10605 return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915); 10606 } 10607