1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <acpi/video.h> 28 #include <linux/i2c.h> 29 #include <linux/input.h> 30 #include <linux/intel-iommu.h> 31 #include <linux/kernel.h> 32 #include <linux/module.h> 33 #include <linux/dma-resv.h> 34 #include <linux/slab.h> 35 #include <linux/string_helpers.h> 36 #include <linux/vga_switcheroo.h> 37 38 #include <drm/drm_atomic.h> 39 #include <drm/drm_atomic_helper.h> 40 #include <drm/drm_atomic_uapi.h> 41 #include <drm/drm_damage_helper.h> 42 #include <drm/dp/drm_dp_helper.h> 43 #include <drm/drm_edid.h> 44 #include <drm/drm_fourcc.h> 45 #include <drm/drm_plane_helper.h> 46 #include <drm/drm_privacy_screen_consumer.h> 47 #include <drm/drm_probe_helper.h> 48 #include <drm/drm_rect.h> 49 50 #include "display/intel_audio.h" 51 #include "display/intel_crt.h" 52 #include "display/intel_ddi.h" 53 #include "display/intel_display_debugfs.h" 54 #include "display/intel_dp.h" 55 #include "display/intel_dp_mst.h" 56 #include "display/intel_dpll.h" 57 #include "display/intel_dpll_mgr.h" 58 #include "display/intel_drrs.h" 59 #include "display/intel_dsi.h" 60 #include "display/intel_dvo.h" 61 #include "display/intel_fb.h" 62 #include "display/intel_gmbus.h" 63 #include "display/intel_hdmi.h" 64 #include "display/intel_lvds.h" 65 #include "display/intel_sdvo.h" 66 #include "display/intel_snps_phy.h" 67 #include "display/intel_tv.h" 68 #include "display/intel_vdsc.h" 69 #include "display/intel_vrr.h" 70 71 #include "gem/i915_gem_lmem.h" 72 #include "gem/i915_gem_object.h" 73 74 #include "gt/gen8_ppgtt.h" 75 76 #include "g4x_dp.h" 77 #include "g4x_hdmi.h" 78 #include "hsw_ips.h" 79 #include "i915_drv.h" 80 #include "icl_dsi.h" 81 #include "intel_acpi.h" 82 #include "intel_atomic.h" 83 #include "intel_atomic_plane.h" 84 #include "intel_bw.h" 85 #include "intel_cdclk.h" 86 #include "intel_color.h" 87 #include "intel_crtc.h" 88 #include "intel_de.h" 89 #include "intel_display_types.h" 90 #include "intel_dmc.h" 91 #include "intel_dp_link_training.h" 92 #include "intel_dpt.h" 93 #include "intel_fbc.h" 94 #include "intel_fbdev.h" 95 #include "intel_fdi.h" 96 #include "intel_fifo_underrun.h" 97 #include "intel_frontbuffer.h" 98 #include "intel_hdcp.h" 99 #include "intel_hotplug.h" 100 #include "intel_overlay.h" 101 #include "intel_panel.h" 102 #include "intel_pch_display.h" 103 #include "intel_pch_refclk.h" 104 #include "intel_pcode.h" 105 #include "intel_pipe_crc.h" 106 #include "intel_plane_initial.h" 107 #include "intel_pm.h" 108 #include "intel_pps.h" 109 #include "intel_psr.h" 110 #include "intel_quirks.h" 111 #include "intel_sprite.h" 112 #include "intel_tc.h" 113 #include "intel_vga.h" 114 #include "i9xx_plane.h" 115 #include "skl_scaler.h" 116 #include "skl_universal_plane.h" 117 #include "vlv_dsi.h" 118 #include "vlv_dsi_pll.h" 119 #include "vlv_dsi_regs.h" 120 #include "vlv_sideband.h" 121 122 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state); 123 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state); 124 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state); 125 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state); 126 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state); 127 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state); 128 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state); 129 static void intel_modeset_setup_hw_state(struct drm_device *dev, 130 struct drm_modeset_acquire_ctx *ctx); 131 132 /** 133 * intel_update_watermarks - update FIFO watermark values based on current modes 134 * @dev_priv: i915 device 135 * 136 * Calculate watermark values for the various WM regs based on current mode 137 * and plane configuration. 138 * 139 * There are several cases to deal with here: 140 * - normal (i.e. non-self-refresh) 141 * - self-refresh (SR) mode 142 * - lines are large relative to FIFO size (buffer can hold up to 2) 143 * - lines are small relative to FIFO size (buffer can hold more than 2 144 * lines), so need to account for TLB latency 145 * 146 * The normal calculation is: 147 * watermark = dotclock * bytes per pixel * latency 148 * where latency is platform & configuration dependent (we assume pessimal 149 * values here). 150 * 151 * The SR calculation is: 152 * watermark = (trunc(latency/line time)+1) * surface width * 153 * bytes per pixel 154 * where 155 * line time = htotal / dotclock 156 * surface width = hdisplay for normal plane and 64 for cursor 157 * and latency is assumed to be high, as above. 158 * 159 * The final value programmed to the register should always be rounded up, 160 * and include an extra 2 entries to account for clock crossings. 161 * 162 * We don't use the sprite, so we can ignore that. And on Crestline we have 163 * to set the non-SR watermarks to 8. 164 */ 165 static void intel_update_watermarks(struct drm_i915_private *dev_priv) 166 { 167 if (dev_priv->wm_disp->update_wm) 168 dev_priv->wm_disp->update_wm(dev_priv); 169 } 170 171 static int intel_compute_pipe_wm(struct intel_atomic_state *state, 172 struct intel_crtc *crtc) 173 { 174 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 175 if (dev_priv->wm_disp->compute_pipe_wm) 176 return dev_priv->wm_disp->compute_pipe_wm(state, crtc); 177 return 0; 178 } 179 180 static int intel_compute_intermediate_wm(struct intel_atomic_state *state, 181 struct intel_crtc *crtc) 182 { 183 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 184 if (!dev_priv->wm_disp->compute_intermediate_wm) 185 return 0; 186 if (drm_WARN_ON(&dev_priv->drm, 187 !dev_priv->wm_disp->compute_pipe_wm)) 188 return 0; 189 return dev_priv->wm_disp->compute_intermediate_wm(state, crtc); 190 } 191 192 static bool intel_initial_watermarks(struct intel_atomic_state *state, 193 struct intel_crtc *crtc) 194 { 195 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 196 if (dev_priv->wm_disp->initial_watermarks) { 197 dev_priv->wm_disp->initial_watermarks(state, crtc); 198 return true; 199 } 200 return false; 201 } 202 203 static void intel_atomic_update_watermarks(struct intel_atomic_state *state, 204 struct intel_crtc *crtc) 205 { 206 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 207 if (dev_priv->wm_disp->atomic_update_watermarks) 208 dev_priv->wm_disp->atomic_update_watermarks(state, crtc); 209 } 210 211 static void intel_optimize_watermarks(struct intel_atomic_state *state, 212 struct intel_crtc *crtc) 213 { 214 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 215 if (dev_priv->wm_disp->optimize_watermarks) 216 dev_priv->wm_disp->optimize_watermarks(state, crtc); 217 } 218 219 static int intel_compute_global_watermarks(struct intel_atomic_state *state) 220 { 221 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 222 if (dev_priv->wm_disp->compute_global_watermarks) 223 return dev_priv->wm_disp->compute_global_watermarks(state); 224 return 0; 225 } 226 227 /* returns HPLL frequency in kHz */ 228 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) 229 { 230 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; 231 232 /* Obtain SKU information */ 233 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & 234 CCK_FUSE_HPLL_FREQ_MASK; 235 236 return vco_freq[hpll_freq] * 1000; 237 } 238 239 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 240 const char *name, u32 reg, int ref_freq) 241 { 242 u32 val; 243 int divider; 244 245 val = vlv_cck_read(dev_priv, reg); 246 divider = val & CCK_FREQUENCY_VALUES; 247 248 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != 249 (divider << CCK_FREQUENCY_STATUS_SHIFT), 250 "%s change in progress\n", name); 251 252 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); 253 } 254 255 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 256 const char *name, u32 reg) 257 { 258 int hpll; 259 260 vlv_cck_get(dev_priv); 261 262 if (dev_priv->hpll_freq == 0) 263 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); 264 265 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); 266 267 vlv_cck_put(dev_priv); 268 269 return hpll; 270 } 271 272 static void intel_update_czclk(struct drm_i915_private *dev_priv) 273 { 274 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) 275 return; 276 277 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", 278 CCK_CZ_CLOCK_CONTROL); 279 280 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", 281 dev_priv->czclk_freq); 282 } 283 284 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state) 285 { 286 return (crtc_state->active_planes & 287 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0; 288 } 289 290 /* WA Display #0827: Gen9:all */ 291 static void 292 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) 293 { 294 if (enable) 295 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 296 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS); 297 else 298 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 299 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS)); 300 } 301 302 /* Wa_2006604312:icl,ehl */ 303 static void 304 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 305 bool enable) 306 { 307 if (enable) 308 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 309 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS); 310 else 311 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 312 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS); 313 } 314 315 /* Wa_1604331009:icl,jsl,ehl */ 316 static void 317 icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 318 bool enable) 319 { 320 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), CURSOR_GATING_DIS, 321 enable ? CURSOR_GATING_DIS : 0); 322 } 323 324 static bool 325 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state) 326 { 327 return crtc_state->master_transcoder != INVALID_TRANSCODER; 328 } 329 330 static bool 331 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state) 332 { 333 return crtc_state->sync_mode_slaves_mask != 0; 334 } 335 336 bool 337 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state) 338 { 339 return is_trans_port_sync_master(crtc_state) || 340 is_trans_port_sync_slave(crtc_state); 341 } 342 343 static enum pipe bigjoiner_master_pipe(const struct intel_crtc_state *crtc_state) 344 { 345 return ffs(crtc_state->bigjoiner_pipes) - 1; 346 } 347 348 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state) 349 { 350 if (crtc_state->bigjoiner_pipes) 351 return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state)); 352 else 353 return 0; 354 } 355 356 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state) 357 { 358 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 359 360 return crtc_state->bigjoiner_pipes && 361 crtc->pipe != bigjoiner_master_pipe(crtc_state); 362 } 363 364 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state) 365 { 366 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 367 368 return crtc_state->bigjoiner_pipes && 369 crtc->pipe == bigjoiner_master_pipe(crtc_state); 370 } 371 372 static int intel_bigjoiner_num_pipes(const struct intel_crtc_state *crtc_state) 373 { 374 return hweight8(crtc_state->bigjoiner_pipes); 375 } 376 377 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state) 378 { 379 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 380 381 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 382 return intel_crtc_for_pipe(i915, bigjoiner_master_pipe(crtc_state)); 383 else 384 return to_intel_crtc(crtc_state->uapi.crtc); 385 } 386 387 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv, 388 enum pipe pipe) 389 { 390 i915_reg_t reg = PIPEDSL(pipe); 391 u32 line1, line2; 392 393 line1 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK; 394 msleep(5); 395 line2 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK; 396 397 return line1 != line2; 398 } 399 400 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state) 401 { 402 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 403 enum pipe pipe = crtc->pipe; 404 405 /* Wait for the display line to settle/start moving */ 406 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100)) 407 drm_err(&dev_priv->drm, 408 "pipe %c scanline %s wait timed out\n", 409 pipe_name(pipe), str_on_off(state)); 410 } 411 412 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc) 413 { 414 wait_for_pipe_scanline_moving(crtc, false); 415 } 416 417 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc) 418 { 419 wait_for_pipe_scanline_moving(crtc, true); 420 } 421 422 static void 423 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) 424 { 425 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 426 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 427 428 if (DISPLAY_VER(dev_priv) >= 4) { 429 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 430 431 /* Wait for the Pipe State to go off */ 432 if (intel_de_wait_for_clear(dev_priv, PIPECONF(cpu_transcoder), 433 PIPECONF_STATE_ENABLE, 100)) 434 drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n"); 435 } else { 436 intel_wait_for_pipe_scanline_stopped(crtc); 437 } 438 } 439 440 void assert_transcoder(struct drm_i915_private *dev_priv, 441 enum transcoder cpu_transcoder, bool state) 442 { 443 bool cur_state; 444 enum intel_display_power_domain power_domain; 445 intel_wakeref_t wakeref; 446 447 /* we keep both pipes enabled on 830 */ 448 if (IS_I830(dev_priv)) 449 state = true; 450 451 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 452 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 453 if (wakeref) { 454 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); 455 cur_state = !!(val & PIPECONF_ENABLE); 456 457 intel_display_power_put(dev_priv, power_domain, wakeref); 458 } else { 459 cur_state = false; 460 } 461 462 I915_STATE_WARN(cur_state != state, 463 "transcoder %s assertion failure (expected %s, current %s)\n", 464 transcoder_name(cpu_transcoder), 465 str_on_off(state), str_on_off(cur_state)); 466 } 467 468 static void assert_plane(struct intel_plane *plane, bool state) 469 { 470 enum pipe pipe; 471 bool cur_state; 472 473 cur_state = plane->get_hw_state(plane, &pipe); 474 475 I915_STATE_WARN(cur_state != state, 476 "%s assertion failure (expected %s, current %s)\n", 477 plane->base.name, str_on_off(state), 478 str_on_off(cur_state)); 479 } 480 481 #define assert_plane_enabled(p) assert_plane(p, true) 482 #define assert_plane_disabled(p) assert_plane(p, false) 483 484 static void assert_planes_disabled(struct intel_crtc *crtc) 485 { 486 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 487 struct intel_plane *plane; 488 489 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) 490 assert_plane_disabled(plane); 491 } 492 493 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 494 struct intel_digital_port *dig_port, 495 unsigned int expected_mask) 496 { 497 u32 port_mask; 498 i915_reg_t dpll_reg; 499 500 switch (dig_port->base.port) { 501 case PORT_B: 502 port_mask = DPLL_PORTB_READY_MASK; 503 dpll_reg = DPLL(0); 504 break; 505 case PORT_C: 506 port_mask = DPLL_PORTC_READY_MASK; 507 dpll_reg = DPLL(0); 508 expected_mask <<= 4; 509 break; 510 case PORT_D: 511 port_mask = DPLL_PORTD_READY_MASK; 512 dpll_reg = DPIO_PHY_STATUS; 513 break; 514 default: 515 BUG(); 516 } 517 518 if (intel_de_wait_for_register(dev_priv, dpll_reg, 519 port_mask, expected_mask, 1000)) 520 drm_WARN(&dev_priv->drm, 1, 521 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", 522 dig_port->base.base.base.id, dig_port->base.base.name, 523 intel_de_read(dev_priv, dpll_reg) & port_mask, 524 expected_mask); 525 } 526 527 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) 528 { 529 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 530 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 531 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 532 enum pipe pipe = crtc->pipe; 533 i915_reg_t reg; 534 u32 val; 535 536 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe)); 537 538 assert_planes_disabled(crtc); 539 540 /* 541 * A pipe without a PLL won't actually be able to drive bits from 542 * a plane. On ILK+ the pipe PLLs are integrated, so we don't 543 * need the check. 544 */ 545 if (HAS_GMCH(dev_priv)) { 546 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI)) 547 assert_dsi_pll_enabled(dev_priv); 548 else 549 assert_pll_enabled(dev_priv, pipe); 550 } else { 551 if (new_crtc_state->has_pch_encoder) { 552 /* if driving the PCH, we need FDI enabled */ 553 assert_fdi_rx_pll_enabled(dev_priv, 554 intel_crtc_pch_transcoder(crtc)); 555 assert_fdi_tx_pll_enabled(dev_priv, 556 (enum pipe) cpu_transcoder); 557 } 558 /* FIXME: assert CPU port conditions for SNB+ */ 559 } 560 561 /* Wa_22012358565:adl-p */ 562 if (DISPLAY_VER(dev_priv) == 13) 563 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe), 564 0, PIPE_ARB_USE_PROG_SLOTS); 565 566 reg = PIPECONF(cpu_transcoder); 567 val = intel_de_read(dev_priv, reg); 568 if (val & PIPECONF_ENABLE) { 569 /* we keep both pipes enabled on 830 */ 570 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv)); 571 return; 572 } 573 574 intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE); 575 intel_de_posting_read(dev_priv, reg); 576 577 /* 578 * Until the pipe starts PIPEDSL reads will return a stale value, 579 * which causes an apparent vblank timestamp jump when PIPEDSL 580 * resets to its proper value. That also messes up the frame count 581 * when it's derived from the timestamps. So let's wait for the 582 * pipe to start properly before we call drm_crtc_vblank_on() 583 */ 584 if (intel_crtc_max_vblank_count(new_crtc_state) == 0) 585 intel_wait_for_pipe_scanline_moving(crtc); 586 } 587 588 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) 589 { 590 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 591 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 592 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 593 enum pipe pipe = crtc->pipe; 594 i915_reg_t reg; 595 u32 val; 596 597 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe)); 598 599 /* 600 * Make sure planes won't keep trying to pump pixels to us, 601 * or we might hang the display. 602 */ 603 assert_planes_disabled(crtc); 604 605 reg = PIPECONF(cpu_transcoder); 606 val = intel_de_read(dev_priv, reg); 607 if ((val & PIPECONF_ENABLE) == 0) 608 return; 609 610 /* 611 * Double wide has implications for planes 612 * so best keep it disabled when not needed. 613 */ 614 if (old_crtc_state->double_wide) 615 val &= ~PIPECONF_DOUBLE_WIDE; 616 617 /* Don't disable pipe or pipe PLLs if needed */ 618 if (!IS_I830(dev_priv)) 619 val &= ~PIPECONF_ENABLE; 620 621 if (DISPLAY_VER(dev_priv) >= 12) 622 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 623 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 624 625 intel_de_write(dev_priv, reg, val); 626 if ((val & PIPECONF_ENABLE) == 0) 627 intel_wait_for_pipe_off(old_crtc_state); 628 } 629 630 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) 631 { 632 unsigned int size = 0; 633 int i; 634 635 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) 636 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width; 637 638 return size; 639 } 640 641 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info) 642 { 643 unsigned int size = 0; 644 int i; 645 646 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) { 647 unsigned int plane_size; 648 649 if (rem_info->plane[i].linear) 650 plane_size = rem_info->plane[i].size; 651 else 652 plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height; 653 654 if (plane_size == 0) 655 continue; 656 657 if (rem_info->plane_alignment) 658 size = ALIGN(size, rem_info->plane_alignment); 659 660 size += plane_size; 661 } 662 663 return size; 664 } 665 666 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) 667 { 668 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 669 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 670 671 return DISPLAY_VER(dev_priv) < 4 || 672 (plane->fbc && 673 plane_state->view.gtt.type == I915_GGTT_VIEW_NORMAL); 674 } 675 676 /* 677 * Convert the x/y offsets into a linear offset. 678 * Only valid with 0/180 degree rotation, which is fine since linear 679 * offset is only used with linear buffers on pre-hsw and tiled buffers 680 * with gen2/3, and 90/270 degree rotations isn't supported on any of them. 681 */ 682 u32 intel_fb_xy_to_linear(int x, int y, 683 const struct intel_plane_state *state, 684 int color_plane) 685 { 686 const struct drm_framebuffer *fb = state->hw.fb; 687 unsigned int cpp = fb->format->cpp[color_plane]; 688 unsigned int pitch = state->view.color_plane[color_plane].mapping_stride; 689 690 return y * pitch + x * cpp; 691 } 692 693 /* 694 * Add the x/y offsets derived from fb->offsets[] to the user 695 * specified plane src x/y offsets. The resulting x/y offsets 696 * specify the start of scanout from the beginning of the gtt mapping. 697 */ 698 void intel_add_fb_offsets(int *x, int *y, 699 const struct intel_plane_state *state, 700 int color_plane) 701 702 { 703 *x += state->view.color_plane[color_plane].x; 704 *y += state->view.color_plane[color_plane].y; 705 } 706 707 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 708 u32 pixel_format, u64 modifier) 709 { 710 struct intel_crtc *crtc; 711 struct intel_plane *plane; 712 713 if (!HAS_DISPLAY(dev_priv)) 714 return 0; 715 716 /* 717 * We assume the primary plane for pipe A has 718 * the highest stride limits of them all, 719 * if in case pipe A is disabled, use the first pipe from pipe_mask. 720 */ 721 crtc = intel_first_crtc(dev_priv); 722 if (!crtc) 723 return 0; 724 725 plane = to_intel_plane(crtc->base.primary); 726 727 return plane->max_stride(plane, pixel_format, modifier, 728 DRM_MODE_ROTATE_0); 729 } 730 731 static void 732 intel_set_plane_visible(struct intel_crtc_state *crtc_state, 733 struct intel_plane_state *plane_state, 734 bool visible) 735 { 736 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 737 738 plane_state->uapi.visible = visible; 739 740 if (visible) 741 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base); 742 else 743 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base); 744 } 745 746 static void fixup_plane_bitmasks(struct intel_crtc_state *crtc_state) 747 { 748 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 749 struct drm_plane *plane; 750 751 /* 752 * Active_planes aliases if multiple "primary" or cursor planes 753 * have been used on the same (or wrong) pipe. plane_mask uses 754 * unique ids, hence we can use that to reconstruct active_planes. 755 */ 756 crtc_state->enabled_planes = 0; 757 crtc_state->active_planes = 0; 758 759 drm_for_each_plane_mask(plane, &dev_priv->drm, 760 crtc_state->uapi.plane_mask) { 761 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id); 762 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id); 763 } 764 } 765 766 void intel_plane_disable_noatomic(struct intel_crtc *crtc, 767 struct intel_plane *plane) 768 { 769 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 770 struct intel_crtc_state *crtc_state = 771 to_intel_crtc_state(crtc->base.state); 772 struct intel_plane_state *plane_state = 773 to_intel_plane_state(plane->base.state); 774 775 drm_dbg_kms(&dev_priv->drm, 776 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n", 777 plane->base.base.id, plane->base.name, 778 crtc->base.base.id, crtc->base.name); 779 780 intel_set_plane_visible(crtc_state, plane_state, false); 781 fixup_plane_bitmasks(crtc_state); 782 crtc_state->data_rate[plane->id] = 0; 783 crtc_state->data_rate_y[plane->id] = 0; 784 crtc_state->rel_data_rate[plane->id] = 0; 785 crtc_state->rel_data_rate_y[plane->id] = 0; 786 crtc_state->min_cdclk[plane->id] = 0; 787 788 if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 && 789 hsw_ips_disable(crtc_state)) { 790 crtc_state->ips_enabled = false; 791 intel_crtc_wait_for_next_vblank(crtc); 792 } 793 794 /* 795 * Vblank time updates from the shadow to live plane control register 796 * are blocked if the memory self-refresh mode is active at that 797 * moment. So to make sure the plane gets truly disabled, disable 798 * first the self-refresh mode. The self-refresh enable bit in turn 799 * will be checked/applied by the HW only at the next frame start 800 * event which is after the vblank start event, so we need to have a 801 * wait-for-vblank between disabling the plane and the pipe. 802 */ 803 if (HAS_GMCH(dev_priv) && 804 intel_set_memory_cxsr(dev_priv, false)) 805 intel_crtc_wait_for_next_vblank(crtc); 806 807 /* 808 * Gen2 reports pipe underruns whenever all planes are disabled. 809 * So disable underrun reporting before all the planes get disabled. 810 */ 811 if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes) 812 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); 813 814 intel_plane_disable_arm(plane, crtc_state); 815 intel_crtc_wait_for_next_vblank(crtc); 816 } 817 818 unsigned int 819 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state) 820 { 821 int x = 0, y = 0; 822 823 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, 824 plane_state->view.color_plane[0].offset, 0); 825 826 return y; 827 } 828 829 static int 830 __intel_display_resume(struct drm_device *dev, 831 struct drm_atomic_state *state, 832 struct drm_modeset_acquire_ctx *ctx) 833 { 834 struct drm_crtc_state *crtc_state; 835 struct drm_crtc *crtc; 836 int i, ret; 837 838 intel_modeset_setup_hw_state(dev, ctx); 839 intel_vga_redisable(to_i915(dev)); 840 841 if (!state) 842 return 0; 843 844 /* 845 * We've duplicated the state, pointers to the old state are invalid. 846 * 847 * Don't attempt to use the old state until we commit the duplicated state. 848 */ 849 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 850 /* 851 * Force recalculation even if we restore 852 * current state. With fast modeset this may not result 853 * in a modeset when the state is compatible. 854 */ 855 crtc_state->mode_changed = true; 856 } 857 858 /* ignore any reset values/BIOS leftovers in the WM registers */ 859 if (!HAS_GMCH(to_i915(dev))) 860 to_intel_atomic_state(state)->skip_intermediate_wm = true; 861 862 ret = drm_atomic_helper_commit_duplicated_state(state, ctx); 863 864 drm_WARN_ON(dev, ret == -EDEADLK); 865 return ret; 866 } 867 868 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) 869 { 870 return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display && 871 intel_has_gpu_reset(to_gt(dev_priv))); 872 } 873 874 void intel_display_prepare_reset(struct drm_i915_private *dev_priv) 875 { 876 struct drm_device *dev = &dev_priv->drm; 877 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; 878 struct drm_atomic_state *state; 879 int ret; 880 881 if (!HAS_DISPLAY(dev_priv)) 882 return; 883 884 /* reset doesn't touch the display */ 885 if (!dev_priv->params.force_reset_modeset_test && 886 !gpu_reset_clobbers_display(dev_priv)) 887 return; 888 889 /* We have a modeset vs reset deadlock, defensively unbreak it. */ 890 set_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags); 891 smp_mb__after_atomic(); 892 wake_up_bit(&to_gt(dev_priv)->reset.flags, I915_RESET_MODESET); 893 894 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) { 895 drm_dbg_kms(&dev_priv->drm, 896 "Modeset potentially stuck, unbreaking through wedging\n"); 897 intel_gt_set_wedged(to_gt(dev_priv)); 898 } 899 900 /* 901 * Need mode_config.mutex so that we don't 902 * trample ongoing ->detect() and whatnot. 903 */ 904 mutex_lock(&dev->mode_config.mutex); 905 drm_modeset_acquire_init(ctx, 0); 906 while (1) { 907 ret = drm_modeset_lock_all_ctx(dev, ctx); 908 if (ret != -EDEADLK) 909 break; 910 911 drm_modeset_backoff(ctx); 912 } 913 /* 914 * Disabling the crtcs gracefully seems nicer. Also the 915 * g33 docs say we should at least disable all the planes. 916 */ 917 state = drm_atomic_helper_duplicate_state(dev, ctx); 918 if (IS_ERR(state)) { 919 ret = PTR_ERR(state); 920 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n", 921 ret); 922 return; 923 } 924 925 ret = drm_atomic_helper_disable_all(dev, ctx); 926 if (ret) { 927 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", 928 ret); 929 drm_atomic_state_put(state); 930 return; 931 } 932 933 dev_priv->modeset_restore_state = state; 934 state->acquire_ctx = ctx; 935 } 936 937 void intel_display_finish_reset(struct drm_i915_private *dev_priv) 938 { 939 struct drm_device *dev = &dev_priv->drm; 940 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; 941 struct drm_atomic_state *state; 942 int ret; 943 944 if (!HAS_DISPLAY(dev_priv)) 945 return; 946 947 /* reset doesn't touch the display */ 948 if (!test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags)) 949 return; 950 951 state = fetch_and_zero(&dev_priv->modeset_restore_state); 952 if (!state) 953 goto unlock; 954 955 /* reset doesn't touch the display */ 956 if (!gpu_reset_clobbers_display(dev_priv)) { 957 /* for testing only restore the display */ 958 ret = __intel_display_resume(dev, state, ctx); 959 if (ret) 960 drm_err(&dev_priv->drm, 961 "Restoring old state failed with %i\n", ret); 962 } else { 963 /* 964 * The display has been reset as well, 965 * so need a full re-initialization. 966 */ 967 intel_pps_unlock_regs_wa(dev_priv); 968 intel_modeset_init_hw(dev_priv); 969 intel_init_clock_gating(dev_priv); 970 intel_hpd_init(dev_priv); 971 972 ret = __intel_display_resume(dev, state, ctx); 973 if (ret) 974 drm_err(&dev_priv->drm, 975 "Restoring old state failed with %i\n", ret); 976 977 intel_hpd_poll_disable(dev_priv); 978 } 979 980 drm_atomic_state_put(state); 981 unlock: 982 drm_modeset_drop_locks(ctx); 983 drm_modeset_acquire_fini(ctx); 984 mutex_unlock(&dev->mode_config.mutex); 985 986 clear_bit_unlock(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags); 987 } 988 989 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) 990 { 991 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 992 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 993 enum pipe pipe = crtc->pipe; 994 u32 tmp; 995 996 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe)); 997 998 /* 999 * Display WA #1153: icl 1000 * enable hardware to bypass the alpha math 1001 * and rounding for per-pixel values 00 and 0xff 1002 */ 1003 tmp |= PER_PIXEL_ALPHA_BYPASS_EN; 1004 /* 1005 * Display WA # 1605353570: icl 1006 * Set the pixel rounding bit to 1 for allowing 1007 * passthrough of Frame buffer pixels unmodified 1008 * across pipe 1009 */ 1010 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU; 1011 1012 /* 1013 * Underrun recovery must always be disabled on display 13+. 1014 * DG2 chicken bit meaning is inverted compared to other platforms. 1015 */ 1016 if (IS_DG2(dev_priv)) 1017 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2; 1018 else if (DISPLAY_VER(dev_priv) >= 13) 1019 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP; 1020 1021 /* Wa_14010547955:dg2 */ 1022 if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER)) 1023 tmp |= DG2_RENDER_CCSTAG_4_3_EN; 1024 1025 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp); 1026 } 1027 1028 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) 1029 { 1030 struct drm_crtc *crtc; 1031 bool cleanup_done; 1032 1033 drm_for_each_crtc(crtc, &dev_priv->drm) { 1034 struct drm_crtc_commit *commit; 1035 spin_lock(&crtc->commit_lock); 1036 commit = list_first_entry_or_null(&crtc->commit_list, 1037 struct drm_crtc_commit, commit_entry); 1038 cleanup_done = commit ? 1039 try_wait_for_completion(&commit->cleanup_done) : true; 1040 spin_unlock(&crtc->commit_lock); 1041 1042 if (cleanup_done) 1043 continue; 1044 1045 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc)); 1046 1047 return true; 1048 } 1049 1050 return false; 1051 } 1052 1053 /* 1054 * Finds the encoder associated with the given CRTC. This can only be 1055 * used when we know that the CRTC isn't feeding multiple encoders! 1056 */ 1057 struct intel_encoder * 1058 intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 1059 const struct intel_crtc_state *crtc_state) 1060 { 1061 const struct drm_connector_state *connector_state; 1062 const struct drm_connector *connector; 1063 struct intel_encoder *encoder = NULL; 1064 struct intel_crtc *master_crtc; 1065 int num_encoders = 0; 1066 int i; 1067 1068 master_crtc = intel_master_crtc(crtc_state); 1069 1070 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 1071 if (connector_state->crtc != &master_crtc->base) 1072 continue; 1073 1074 encoder = to_intel_encoder(connector_state->best_encoder); 1075 num_encoders++; 1076 } 1077 1078 drm_WARN(encoder->base.dev, num_encoders != 1, 1079 "%d encoders for pipe %c\n", 1080 num_encoders, pipe_name(master_crtc->pipe)); 1081 1082 return encoder; 1083 } 1084 1085 static void cpt_verify_modeset(struct drm_i915_private *dev_priv, 1086 enum pipe pipe) 1087 { 1088 i915_reg_t dslreg = PIPEDSL(pipe); 1089 u32 temp; 1090 1091 temp = intel_de_read(dev_priv, dslreg); 1092 udelay(500); 1093 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) { 1094 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) 1095 drm_err(&dev_priv->drm, 1096 "mode set failed: pipe %c stuck\n", 1097 pipe_name(pipe)); 1098 } 1099 } 1100 1101 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state) 1102 { 1103 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1104 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1105 const struct drm_rect *dst = &crtc_state->pch_pfit.dst; 1106 enum pipe pipe = crtc->pipe; 1107 int width = drm_rect_width(dst); 1108 int height = drm_rect_height(dst); 1109 int x = dst->x1; 1110 int y = dst->y1; 1111 1112 if (!crtc_state->pch_pfit.enabled) 1113 return; 1114 1115 /* Force use of hard-coded filter coefficients 1116 * as some pre-programmed values are broken, 1117 * e.g. x201. 1118 */ 1119 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) 1120 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 1121 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe)); 1122 else 1123 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 1124 PF_FILTER_MED_3x3); 1125 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), x << 16 | y); 1126 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), width << 16 | height); 1127 } 1128 1129 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc) 1130 { 1131 if (crtc->overlay) 1132 (void) intel_overlay_switch_off(crtc->overlay); 1133 1134 /* Let userspace switch the overlay on again. In most cases userspace 1135 * has to recompute where to put it anyway. 1136 */ 1137 } 1138 1139 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state) 1140 { 1141 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1142 1143 if (!crtc_state->nv12_planes) 1144 return false; 1145 1146 /* WA Display #0827: Gen9:all */ 1147 if (DISPLAY_VER(dev_priv) == 9) 1148 return true; 1149 1150 return false; 1151 } 1152 1153 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state) 1154 { 1155 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1156 1157 /* Wa_2006604312:icl,ehl */ 1158 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11) 1159 return true; 1160 1161 return false; 1162 } 1163 1164 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state) 1165 { 1166 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1167 1168 /* Wa_1604331009:icl,jsl,ehl */ 1169 if (is_hdr_mode(crtc_state) && 1170 crtc_state->active_planes & BIT(PLANE_CURSOR) && 1171 DISPLAY_VER(dev_priv) == 11) 1172 return true; 1173 1174 return false; 1175 } 1176 1177 static void intel_async_flip_vtd_wa(struct drm_i915_private *i915, 1178 enum pipe pipe, bool enable) 1179 { 1180 if (DISPLAY_VER(i915) == 9) { 1181 /* 1182 * "Plane N strech max must be programmed to 11b (x1) 1183 * when Async flips are enabled on that plane." 1184 */ 1185 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 1186 SKL_PLANE1_STRETCH_MAX_MASK, 1187 enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8); 1188 } else { 1189 /* Also needed on HSW/BDW albeit undocumented */ 1190 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 1191 HSW_PRI_STRETCH_MAX_MASK, 1192 enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8); 1193 } 1194 } 1195 1196 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state) 1197 { 1198 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1199 1200 return crtc_state->uapi.async_flip && intel_vtd_active(i915) && 1201 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915)); 1202 } 1203 1204 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state, 1205 const struct intel_crtc_state *new_crtc_state) 1206 { 1207 return (!old_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)) && 1208 new_crtc_state->active_planes; 1209 } 1210 1211 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state, 1212 const struct intel_crtc_state *new_crtc_state) 1213 { 1214 return old_crtc_state->active_planes && 1215 (!new_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)); 1216 } 1217 1218 static void intel_post_plane_update(struct intel_atomic_state *state, 1219 struct intel_crtc *crtc) 1220 { 1221 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1222 const struct intel_crtc_state *old_crtc_state = 1223 intel_atomic_get_old_crtc_state(state, crtc); 1224 const struct intel_crtc_state *new_crtc_state = 1225 intel_atomic_get_new_crtc_state(state, crtc); 1226 enum pipe pipe = crtc->pipe; 1227 1228 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); 1229 1230 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) 1231 intel_update_watermarks(dev_priv); 1232 1233 hsw_ips_post_update(state, crtc); 1234 intel_fbc_post_update(state, crtc); 1235 1236 if (needs_async_flip_vtd_wa(old_crtc_state) && 1237 !needs_async_flip_vtd_wa(new_crtc_state)) 1238 intel_async_flip_vtd_wa(dev_priv, pipe, false); 1239 1240 if (needs_nv12_wa(old_crtc_state) && 1241 !needs_nv12_wa(new_crtc_state)) 1242 skl_wa_827(dev_priv, pipe, false); 1243 1244 if (needs_scalerclk_wa(old_crtc_state) && 1245 !needs_scalerclk_wa(new_crtc_state)) 1246 icl_wa_scalerclkgating(dev_priv, pipe, false); 1247 1248 if (needs_cursorclk_wa(old_crtc_state) && 1249 !needs_cursorclk_wa(new_crtc_state)) 1250 icl_wa_cursorclkgating(dev_priv, pipe, false); 1251 1252 intel_drrs_activate(new_crtc_state); 1253 } 1254 1255 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state, 1256 struct intel_crtc *crtc) 1257 { 1258 const struct intel_crtc_state *crtc_state = 1259 intel_atomic_get_new_crtc_state(state, crtc); 1260 u8 update_planes = crtc_state->update_planes; 1261 const struct intel_plane_state *plane_state; 1262 struct intel_plane *plane; 1263 int i; 1264 1265 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1266 if (plane->pipe == crtc->pipe && 1267 update_planes & BIT(plane->id)) 1268 plane->enable_flip_done(plane); 1269 } 1270 } 1271 1272 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state, 1273 struct intel_crtc *crtc) 1274 { 1275 const struct intel_crtc_state *crtc_state = 1276 intel_atomic_get_new_crtc_state(state, crtc); 1277 u8 update_planes = crtc_state->update_planes; 1278 const struct intel_plane_state *plane_state; 1279 struct intel_plane *plane; 1280 int i; 1281 1282 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1283 if (plane->pipe == crtc->pipe && 1284 update_planes & BIT(plane->id)) 1285 plane->disable_flip_done(plane); 1286 } 1287 } 1288 1289 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state, 1290 struct intel_crtc *crtc) 1291 { 1292 const struct intel_crtc_state *old_crtc_state = 1293 intel_atomic_get_old_crtc_state(state, crtc); 1294 const struct intel_crtc_state *new_crtc_state = 1295 intel_atomic_get_new_crtc_state(state, crtc); 1296 u8 update_planes = new_crtc_state->update_planes; 1297 const struct intel_plane_state *old_plane_state; 1298 struct intel_plane *plane; 1299 bool need_vbl_wait = false; 1300 int i; 1301 1302 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1303 if (plane->need_async_flip_disable_wa && 1304 plane->pipe == crtc->pipe && 1305 update_planes & BIT(plane->id)) { 1306 /* 1307 * Apart from the async flip bit we want to 1308 * preserve the old state for the plane. 1309 */ 1310 plane->async_flip(plane, old_crtc_state, 1311 old_plane_state, false); 1312 need_vbl_wait = true; 1313 } 1314 } 1315 1316 if (need_vbl_wait) 1317 intel_crtc_wait_for_next_vblank(crtc); 1318 } 1319 1320 static void intel_pre_plane_update(struct intel_atomic_state *state, 1321 struct intel_crtc *crtc) 1322 { 1323 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1324 const struct intel_crtc_state *old_crtc_state = 1325 intel_atomic_get_old_crtc_state(state, crtc); 1326 const struct intel_crtc_state *new_crtc_state = 1327 intel_atomic_get_new_crtc_state(state, crtc); 1328 enum pipe pipe = crtc->pipe; 1329 1330 intel_drrs_deactivate(old_crtc_state); 1331 1332 intel_psr_pre_plane_update(state, crtc); 1333 1334 if (hsw_ips_pre_update(state, crtc)) 1335 intel_crtc_wait_for_next_vblank(crtc); 1336 1337 if (intel_fbc_pre_update(state, crtc)) 1338 intel_crtc_wait_for_next_vblank(crtc); 1339 1340 if (!needs_async_flip_vtd_wa(old_crtc_state) && 1341 needs_async_flip_vtd_wa(new_crtc_state)) 1342 intel_async_flip_vtd_wa(dev_priv, pipe, true); 1343 1344 /* Display WA 827 */ 1345 if (!needs_nv12_wa(old_crtc_state) && 1346 needs_nv12_wa(new_crtc_state)) 1347 skl_wa_827(dev_priv, pipe, true); 1348 1349 /* Wa_2006604312:icl,ehl */ 1350 if (!needs_scalerclk_wa(old_crtc_state) && 1351 needs_scalerclk_wa(new_crtc_state)) 1352 icl_wa_scalerclkgating(dev_priv, pipe, true); 1353 1354 /* Wa_1604331009:icl,jsl,ehl */ 1355 if (!needs_cursorclk_wa(old_crtc_state) && 1356 needs_cursorclk_wa(new_crtc_state)) 1357 icl_wa_cursorclkgating(dev_priv, pipe, true); 1358 1359 /* 1360 * Vblank time updates from the shadow to live plane control register 1361 * are blocked if the memory self-refresh mode is active at that 1362 * moment. So to make sure the plane gets truly disabled, disable 1363 * first the self-refresh mode. The self-refresh enable bit in turn 1364 * will be checked/applied by the HW only at the next frame start 1365 * event which is after the vblank start event, so we need to have a 1366 * wait-for-vblank between disabling the plane and the pipe. 1367 */ 1368 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active && 1369 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) 1370 intel_crtc_wait_for_next_vblank(crtc); 1371 1372 /* 1373 * IVB workaround: must disable low power watermarks for at least 1374 * one frame before enabling scaling. LP watermarks can be re-enabled 1375 * when scaling is disabled. 1376 * 1377 * WaCxSRDisabledForSpriteScaling:ivb 1378 */ 1379 if (old_crtc_state->hw.active && 1380 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv)) 1381 intel_crtc_wait_for_next_vblank(crtc); 1382 1383 /* 1384 * If we're doing a modeset we don't need to do any 1385 * pre-vblank watermark programming here. 1386 */ 1387 if (!intel_crtc_needs_modeset(new_crtc_state)) { 1388 /* 1389 * For platforms that support atomic watermarks, program the 1390 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these 1391 * will be the intermediate values that are safe for both pre- and 1392 * post- vblank; when vblank happens, the 'active' values will be set 1393 * to the final 'target' values and we'll do this again to get the 1394 * optimal watermarks. For gen9+ platforms, the values we program here 1395 * will be the final target values which will get automatically latched 1396 * at vblank time; no further programming will be necessary. 1397 * 1398 * If a platform hasn't been transitioned to atomic watermarks yet, 1399 * we'll continue to update watermarks the old way, if flags tell 1400 * us to. 1401 */ 1402 if (!intel_initial_watermarks(state, crtc)) 1403 if (new_crtc_state->update_wm_pre) 1404 intel_update_watermarks(dev_priv); 1405 } 1406 1407 /* 1408 * Gen2 reports pipe underruns whenever all planes are disabled. 1409 * So disable underrun reporting before all the planes get disabled. 1410 * 1411 * We do this after .initial_watermarks() so that we have a 1412 * chance of catching underruns with the intermediate watermarks 1413 * vs. the old plane configuration. 1414 */ 1415 if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state)) 1416 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1417 1418 /* 1419 * WA for platforms where async address update enable bit 1420 * is double buffered and only latched at start of vblank. 1421 */ 1422 if (old_crtc_state->uapi.async_flip && !new_crtc_state->uapi.async_flip) 1423 intel_crtc_async_flip_disable_wa(state, crtc); 1424 } 1425 1426 static void intel_crtc_disable_planes(struct intel_atomic_state *state, 1427 struct intel_crtc *crtc) 1428 { 1429 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1430 const struct intel_crtc_state *new_crtc_state = 1431 intel_atomic_get_new_crtc_state(state, crtc); 1432 unsigned int update_mask = new_crtc_state->update_planes; 1433 const struct intel_plane_state *old_plane_state; 1434 struct intel_plane *plane; 1435 unsigned fb_bits = 0; 1436 int i; 1437 1438 intel_crtc_dpms_overlay_disable(crtc); 1439 1440 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1441 if (crtc->pipe != plane->pipe || 1442 !(update_mask & BIT(plane->id))) 1443 continue; 1444 1445 intel_plane_disable_arm(plane, new_crtc_state); 1446 1447 if (old_plane_state->uapi.visible) 1448 fb_bits |= plane->frontbuffer_bit; 1449 } 1450 1451 intel_frontbuffer_flip(dev_priv, fb_bits); 1452 } 1453 1454 /* 1455 * intel_connector_primary_encoder - get the primary encoder for a connector 1456 * @connector: connector for which to return the encoder 1457 * 1458 * Returns the primary encoder for a connector. There is a 1:1 mapping from 1459 * all connectors to their encoder, except for DP-MST connectors which have 1460 * both a virtual and a primary encoder. These DP-MST primary encoders can be 1461 * pointed to by as many DP-MST connectors as there are pipes. 1462 */ 1463 static struct intel_encoder * 1464 intel_connector_primary_encoder(struct intel_connector *connector) 1465 { 1466 struct intel_encoder *encoder; 1467 1468 if (connector->mst_port) 1469 return &dp_to_dig_port(connector->mst_port)->base; 1470 1471 encoder = intel_attached_encoder(connector); 1472 drm_WARN_ON(connector->base.dev, !encoder); 1473 1474 return encoder; 1475 } 1476 1477 static void intel_encoders_update_prepare(struct intel_atomic_state *state) 1478 { 1479 struct drm_i915_private *i915 = to_i915(state->base.dev); 1480 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 1481 struct intel_crtc *crtc; 1482 struct drm_connector_state *new_conn_state; 1483 struct drm_connector *connector; 1484 int i; 1485 1486 /* 1487 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits. 1488 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook. 1489 */ 1490 if (i915->dpll.mgr) { 1491 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1492 if (intel_crtc_needs_modeset(new_crtc_state)) 1493 continue; 1494 1495 new_crtc_state->shared_dpll = old_crtc_state->shared_dpll; 1496 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state; 1497 } 1498 } 1499 1500 if (!state->modeset) 1501 return; 1502 1503 for_each_new_connector_in_state(&state->base, connector, new_conn_state, 1504 i) { 1505 struct intel_connector *intel_connector; 1506 struct intel_encoder *encoder; 1507 struct intel_crtc *crtc; 1508 1509 if (!intel_connector_needs_modeset(state, connector)) 1510 continue; 1511 1512 intel_connector = to_intel_connector(connector); 1513 encoder = intel_connector_primary_encoder(intel_connector); 1514 if (!encoder->update_prepare) 1515 continue; 1516 1517 crtc = new_conn_state->crtc ? 1518 to_intel_crtc(new_conn_state->crtc) : NULL; 1519 encoder->update_prepare(state, encoder, crtc); 1520 } 1521 } 1522 1523 static void intel_encoders_update_complete(struct intel_atomic_state *state) 1524 { 1525 struct drm_connector_state *new_conn_state; 1526 struct drm_connector *connector; 1527 int i; 1528 1529 if (!state->modeset) 1530 return; 1531 1532 for_each_new_connector_in_state(&state->base, connector, new_conn_state, 1533 i) { 1534 struct intel_connector *intel_connector; 1535 struct intel_encoder *encoder; 1536 struct intel_crtc *crtc; 1537 1538 if (!intel_connector_needs_modeset(state, connector)) 1539 continue; 1540 1541 intel_connector = to_intel_connector(connector); 1542 encoder = intel_connector_primary_encoder(intel_connector); 1543 if (!encoder->update_complete) 1544 continue; 1545 1546 crtc = new_conn_state->crtc ? 1547 to_intel_crtc(new_conn_state->crtc) : NULL; 1548 encoder->update_complete(state, encoder, crtc); 1549 } 1550 } 1551 1552 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state, 1553 struct intel_crtc *crtc) 1554 { 1555 const struct intel_crtc_state *crtc_state = 1556 intel_atomic_get_new_crtc_state(state, crtc); 1557 const struct drm_connector_state *conn_state; 1558 struct drm_connector *conn; 1559 int i; 1560 1561 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1562 struct intel_encoder *encoder = 1563 to_intel_encoder(conn_state->best_encoder); 1564 1565 if (conn_state->crtc != &crtc->base) 1566 continue; 1567 1568 if (encoder->pre_pll_enable) 1569 encoder->pre_pll_enable(state, encoder, 1570 crtc_state, conn_state); 1571 } 1572 } 1573 1574 static void intel_encoders_pre_enable(struct intel_atomic_state *state, 1575 struct intel_crtc *crtc) 1576 { 1577 const struct intel_crtc_state *crtc_state = 1578 intel_atomic_get_new_crtc_state(state, crtc); 1579 const struct drm_connector_state *conn_state; 1580 struct drm_connector *conn; 1581 int i; 1582 1583 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1584 struct intel_encoder *encoder = 1585 to_intel_encoder(conn_state->best_encoder); 1586 1587 if (conn_state->crtc != &crtc->base) 1588 continue; 1589 1590 if (encoder->pre_enable) 1591 encoder->pre_enable(state, encoder, 1592 crtc_state, conn_state); 1593 } 1594 } 1595 1596 static void intel_encoders_enable(struct intel_atomic_state *state, 1597 struct intel_crtc *crtc) 1598 { 1599 const struct intel_crtc_state *crtc_state = 1600 intel_atomic_get_new_crtc_state(state, crtc); 1601 const struct drm_connector_state *conn_state; 1602 struct drm_connector *conn; 1603 int i; 1604 1605 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1606 struct intel_encoder *encoder = 1607 to_intel_encoder(conn_state->best_encoder); 1608 1609 if (conn_state->crtc != &crtc->base) 1610 continue; 1611 1612 if (encoder->enable) 1613 encoder->enable(state, encoder, 1614 crtc_state, conn_state); 1615 intel_opregion_notify_encoder(encoder, true); 1616 } 1617 } 1618 1619 static void intel_encoders_disable(struct intel_atomic_state *state, 1620 struct intel_crtc *crtc) 1621 { 1622 const struct intel_crtc_state *old_crtc_state = 1623 intel_atomic_get_old_crtc_state(state, crtc); 1624 const struct drm_connector_state *old_conn_state; 1625 struct drm_connector *conn; 1626 int i; 1627 1628 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1629 struct intel_encoder *encoder = 1630 to_intel_encoder(old_conn_state->best_encoder); 1631 1632 if (old_conn_state->crtc != &crtc->base) 1633 continue; 1634 1635 intel_opregion_notify_encoder(encoder, false); 1636 if (encoder->disable) 1637 encoder->disable(state, encoder, 1638 old_crtc_state, old_conn_state); 1639 } 1640 } 1641 1642 static void intel_encoders_post_disable(struct intel_atomic_state *state, 1643 struct intel_crtc *crtc) 1644 { 1645 const struct intel_crtc_state *old_crtc_state = 1646 intel_atomic_get_old_crtc_state(state, crtc); 1647 const struct drm_connector_state *old_conn_state; 1648 struct drm_connector *conn; 1649 int i; 1650 1651 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1652 struct intel_encoder *encoder = 1653 to_intel_encoder(old_conn_state->best_encoder); 1654 1655 if (old_conn_state->crtc != &crtc->base) 1656 continue; 1657 1658 if (encoder->post_disable) 1659 encoder->post_disable(state, encoder, 1660 old_crtc_state, old_conn_state); 1661 } 1662 } 1663 1664 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state, 1665 struct intel_crtc *crtc) 1666 { 1667 const struct intel_crtc_state *old_crtc_state = 1668 intel_atomic_get_old_crtc_state(state, crtc); 1669 const struct drm_connector_state *old_conn_state; 1670 struct drm_connector *conn; 1671 int i; 1672 1673 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1674 struct intel_encoder *encoder = 1675 to_intel_encoder(old_conn_state->best_encoder); 1676 1677 if (old_conn_state->crtc != &crtc->base) 1678 continue; 1679 1680 if (encoder->post_pll_disable) 1681 encoder->post_pll_disable(state, encoder, 1682 old_crtc_state, old_conn_state); 1683 } 1684 } 1685 1686 static void intel_encoders_update_pipe(struct intel_atomic_state *state, 1687 struct intel_crtc *crtc) 1688 { 1689 const struct intel_crtc_state *crtc_state = 1690 intel_atomic_get_new_crtc_state(state, crtc); 1691 const struct drm_connector_state *conn_state; 1692 struct drm_connector *conn; 1693 int i; 1694 1695 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1696 struct intel_encoder *encoder = 1697 to_intel_encoder(conn_state->best_encoder); 1698 1699 if (conn_state->crtc != &crtc->base) 1700 continue; 1701 1702 if (encoder->update_pipe) 1703 encoder->update_pipe(state, encoder, 1704 crtc_state, conn_state); 1705 } 1706 } 1707 1708 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state) 1709 { 1710 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1711 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 1712 1713 plane->disable_arm(plane, crtc_state); 1714 } 1715 1716 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1717 { 1718 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1719 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1720 1721 if (crtc_state->has_pch_encoder) { 1722 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1723 &crtc_state->fdi_m_n); 1724 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1725 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1726 &crtc_state->dp_m_n); 1727 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1728 &crtc_state->dp_m2_n2); 1729 } 1730 1731 intel_set_transcoder_timings(crtc_state); 1732 1733 ilk_set_pipeconf(crtc_state); 1734 } 1735 1736 static void ilk_crtc_enable(struct intel_atomic_state *state, 1737 struct intel_crtc *crtc) 1738 { 1739 const struct intel_crtc_state *new_crtc_state = 1740 intel_atomic_get_new_crtc_state(state, crtc); 1741 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1742 enum pipe pipe = crtc->pipe; 1743 1744 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1745 return; 1746 1747 /* 1748 * Sometimes spurious CPU pipe underruns happen during FDI 1749 * training, at least with VGA+HDMI cloning. Suppress them. 1750 * 1751 * On ILK we get an occasional spurious CPU pipe underruns 1752 * between eDP port A enable and vdd enable. Also PCH port 1753 * enable seems to result in the occasional CPU pipe underrun. 1754 * 1755 * Spurious PCH underruns also occur during PCH enabling. 1756 */ 1757 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1758 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 1759 1760 ilk_configure_cpu_transcoder(new_crtc_state); 1761 1762 intel_set_pipe_src_size(new_crtc_state); 1763 1764 crtc->active = true; 1765 1766 intel_encoders_pre_enable(state, crtc); 1767 1768 if (new_crtc_state->has_pch_encoder) { 1769 ilk_pch_pre_enable(state, crtc); 1770 } else { 1771 assert_fdi_tx_disabled(dev_priv, pipe); 1772 assert_fdi_rx_disabled(dev_priv, pipe); 1773 } 1774 1775 ilk_pfit_enable(new_crtc_state); 1776 1777 /* 1778 * On ILK+ LUT must be loaded before the pipe is running but with 1779 * clocks enabled 1780 */ 1781 intel_color_load_luts(new_crtc_state); 1782 intel_color_commit_noarm(new_crtc_state); 1783 intel_color_commit_arm(new_crtc_state); 1784 /* update DSPCNTR to configure gamma for pipe bottom color */ 1785 intel_disable_primary_plane(new_crtc_state); 1786 1787 intel_initial_watermarks(state, crtc); 1788 intel_enable_transcoder(new_crtc_state); 1789 1790 if (new_crtc_state->has_pch_encoder) 1791 ilk_pch_enable(state, crtc); 1792 1793 intel_crtc_vblank_on(new_crtc_state); 1794 1795 intel_encoders_enable(state, crtc); 1796 1797 if (HAS_PCH_CPT(dev_priv)) 1798 cpt_verify_modeset(dev_priv, pipe); 1799 1800 /* 1801 * Must wait for vblank to avoid spurious PCH FIFO underruns. 1802 * And a second vblank wait is needed at least on ILK with 1803 * some interlaced HDMI modes. Let's do the double wait always 1804 * in case there are more corner cases we don't know about. 1805 */ 1806 if (new_crtc_state->has_pch_encoder) { 1807 intel_crtc_wait_for_next_vblank(crtc); 1808 intel_crtc_wait_for_next_vblank(crtc); 1809 } 1810 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1811 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 1812 } 1813 1814 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, 1815 enum pipe pipe, bool apply) 1816 { 1817 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)); 1818 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS; 1819 1820 if (apply) 1821 val |= mask; 1822 else 1823 val &= ~mask; 1824 1825 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val); 1826 } 1827 1828 static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool joined_mbus) 1829 { 1830 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1831 enum pipe pipe = crtc->pipe; 1832 u32 val; 1833 1834 /* Wa_22010947358:adl-p */ 1835 if (IS_ALDERLAKE_P(dev_priv)) 1836 val = joined_mbus ? MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4); 1837 else 1838 val = MBUS_DBOX_A_CREDIT(2); 1839 1840 if (DISPLAY_VER(dev_priv) >= 12) { 1841 val |= MBUS_DBOX_BW_CREDIT(2); 1842 val |= MBUS_DBOX_B_CREDIT(12); 1843 } else { 1844 val |= MBUS_DBOX_BW_CREDIT(1); 1845 val |= MBUS_DBOX_B_CREDIT(8); 1846 } 1847 1848 intel_de_write(dev_priv, PIPE_MBUS_DBOX_CTL(pipe), val); 1849 } 1850 1851 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state) 1852 { 1853 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1854 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1855 1856 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe), 1857 HSW_LINETIME(crtc_state->linetime) | 1858 HSW_IPS_LINETIME(crtc_state->ips_linetime)); 1859 } 1860 1861 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) 1862 { 1863 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1864 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1865 i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder); 1866 u32 val; 1867 1868 val = intel_de_read(dev_priv, reg); 1869 val &= ~HSW_FRAME_START_DELAY_MASK; 1870 val |= HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 1871 intel_de_write(dev_priv, reg, val); 1872 } 1873 1874 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state, 1875 const struct intel_crtc_state *crtc_state) 1876 { 1877 struct intel_crtc *master_crtc = intel_master_crtc(crtc_state); 1878 1879 /* 1880 * Enable sequence steps 1-7 on bigjoiner master 1881 */ 1882 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1883 intel_encoders_pre_pll_enable(state, master_crtc); 1884 1885 if (crtc_state->shared_dpll) 1886 intel_enable_shared_dpll(crtc_state); 1887 1888 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1889 intel_encoders_pre_enable(state, master_crtc); 1890 } 1891 1892 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1893 { 1894 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1895 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1896 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1897 1898 if (crtc_state->has_pch_encoder) { 1899 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1900 &crtc_state->fdi_m_n); 1901 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1902 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1903 &crtc_state->dp_m_n); 1904 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1905 &crtc_state->dp_m2_n2); 1906 } 1907 1908 intel_set_transcoder_timings(crtc_state); 1909 1910 if (cpu_transcoder != TRANSCODER_EDP) 1911 intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder), 1912 crtc_state->pixel_multiplier - 1); 1913 1914 hsw_set_frame_start_delay(crtc_state); 1915 1916 hsw_set_transconf(crtc_state); 1917 } 1918 1919 static void hsw_crtc_enable(struct intel_atomic_state *state, 1920 struct intel_crtc *crtc) 1921 { 1922 const struct intel_crtc_state *new_crtc_state = 1923 intel_atomic_get_new_crtc_state(state, crtc); 1924 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1925 enum pipe pipe = crtc->pipe, hsw_workaround_pipe; 1926 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 1927 bool psl_clkgate_wa; 1928 1929 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1930 return; 1931 1932 if (!new_crtc_state->bigjoiner_pipes) { 1933 intel_encoders_pre_pll_enable(state, crtc); 1934 1935 if (new_crtc_state->shared_dpll) 1936 intel_enable_shared_dpll(new_crtc_state); 1937 1938 intel_encoders_pre_enable(state, crtc); 1939 } else { 1940 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state); 1941 } 1942 1943 intel_dsc_enable(new_crtc_state); 1944 1945 if (DISPLAY_VER(dev_priv) >= 13) 1946 intel_uncompressed_joiner_enable(new_crtc_state); 1947 1948 intel_set_pipe_src_size(new_crtc_state); 1949 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 1950 bdw_set_pipemisc(new_crtc_state); 1951 1952 if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) && 1953 !transcoder_is_dsi(cpu_transcoder)) 1954 hsw_configure_cpu_transcoder(new_crtc_state); 1955 1956 crtc->active = true; 1957 1958 /* Display WA #1180: WaDisableScalarClockGating: glk */ 1959 psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 && 1960 new_crtc_state->pch_pfit.enabled; 1961 if (psl_clkgate_wa) 1962 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true); 1963 1964 if (DISPLAY_VER(dev_priv) >= 9) 1965 skl_pfit_enable(new_crtc_state); 1966 else 1967 ilk_pfit_enable(new_crtc_state); 1968 1969 /* 1970 * On ILK+ LUT must be loaded before the pipe is running but with 1971 * clocks enabled 1972 */ 1973 intel_color_load_luts(new_crtc_state); 1974 intel_color_commit_noarm(new_crtc_state); 1975 intel_color_commit_arm(new_crtc_state); 1976 /* update DSPCNTR to configure gamma/csc for pipe bottom color */ 1977 if (DISPLAY_VER(dev_priv) < 9) 1978 intel_disable_primary_plane(new_crtc_state); 1979 1980 hsw_set_linetime_wm(new_crtc_state); 1981 1982 if (DISPLAY_VER(dev_priv) >= 11) 1983 icl_set_pipe_chicken(new_crtc_state); 1984 1985 intel_initial_watermarks(state, crtc); 1986 1987 if (DISPLAY_VER(dev_priv) >= 11) { 1988 const struct intel_dbuf_state *dbuf_state = 1989 intel_atomic_get_new_dbuf_state(state); 1990 1991 icl_pipe_mbus_enable(crtc, dbuf_state->joined_mbus); 1992 } 1993 1994 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 1995 intel_crtc_vblank_on(new_crtc_state); 1996 1997 intel_encoders_enable(state, crtc); 1998 1999 if (psl_clkgate_wa) { 2000 intel_crtc_wait_for_next_vblank(crtc); 2001 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false); 2002 } 2003 2004 /* If we change the relative order between pipe/planes enabling, we need 2005 * to change the workaround. */ 2006 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe; 2007 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { 2008 struct intel_crtc *wa_crtc; 2009 2010 wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe); 2011 2012 intel_crtc_wait_for_next_vblank(wa_crtc); 2013 intel_crtc_wait_for_next_vblank(wa_crtc); 2014 } 2015 } 2016 2017 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state) 2018 { 2019 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 2020 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2021 enum pipe pipe = crtc->pipe; 2022 2023 /* To avoid upsetting the power well on haswell only disable the pfit if 2024 * it's in use. The hw state code will make sure we get this right. */ 2025 if (!old_crtc_state->pch_pfit.enabled) 2026 return; 2027 2028 intel_de_write_fw(dev_priv, PF_CTL(pipe), 0); 2029 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0); 2030 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0); 2031 } 2032 2033 static void ilk_crtc_disable(struct intel_atomic_state *state, 2034 struct intel_crtc *crtc) 2035 { 2036 const struct intel_crtc_state *old_crtc_state = 2037 intel_atomic_get_old_crtc_state(state, crtc); 2038 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2039 enum pipe pipe = crtc->pipe; 2040 2041 /* 2042 * Sometimes spurious CPU pipe underruns happen when the 2043 * pipe is already disabled, but FDI RX/TX is still enabled. 2044 * Happens at least with VGA+HDMI cloning. Suppress them. 2045 */ 2046 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 2047 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 2048 2049 intel_encoders_disable(state, crtc); 2050 2051 intel_crtc_vblank_off(old_crtc_state); 2052 2053 intel_disable_transcoder(old_crtc_state); 2054 2055 ilk_pfit_disable(old_crtc_state); 2056 2057 if (old_crtc_state->has_pch_encoder) 2058 ilk_pch_disable(state, crtc); 2059 2060 intel_encoders_post_disable(state, crtc); 2061 2062 if (old_crtc_state->has_pch_encoder) 2063 ilk_pch_post_disable(state, crtc); 2064 2065 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2066 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 2067 } 2068 2069 static void hsw_crtc_disable(struct intel_atomic_state *state, 2070 struct intel_crtc *crtc) 2071 { 2072 const struct intel_crtc_state *old_crtc_state = 2073 intel_atomic_get_old_crtc_state(state, crtc); 2074 2075 /* 2076 * FIXME collapse everything to one hook. 2077 * Need care with mst->ddi interactions. 2078 */ 2079 if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) { 2080 intel_encoders_disable(state, crtc); 2081 intel_encoders_post_disable(state, crtc); 2082 } 2083 } 2084 2085 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) 2086 { 2087 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2088 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2089 2090 if (!crtc_state->gmch_pfit.control) 2091 return; 2092 2093 /* 2094 * The panel fitter should only be adjusted whilst the pipe is disabled, 2095 * according to register description and PRM. 2096 */ 2097 drm_WARN_ON(&dev_priv->drm, 2098 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE); 2099 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 2100 2101 intel_de_write(dev_priv, PFIT_PGM_RATIOS, 2102 crtc_state->gmch_pfit.pgm_ratios); 2103 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control); 2104 2105 /* Border color in case we don't scale up to the full screen. Black by 2106 * default, change to something else for debugging. */ 2107 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); 2108 } 2109 2110 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) 2111 { 2112 if (phy == PHY_NONE) 2113 return false; 2114 else if (IS_DG2(dev_priv)) 2115 /* 2116 * DG2 outputs labelled as "combo PHY" in the bspec use 2117 * SNPS PHYs with completely different programming, 2118 * hence we always return false here. 2119 */ 2120 return false; 2121 else if (IS_ALDERLAKE_S(dev_priv)) 2122 return phy <= PHY_E; 2123 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) 2124 return phy <= PHY_D; 2125 else if (IS_JSL_EHL(dev_priv)) 2126 return phy <= PHY_C; 2127 else if (DISPLAY_VER(dev_priv) >= 11) 2128 return phy <= PHY_B; 2129 else 2130 return false; 2131 } 2132 2133 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) 2134 { 2135 if (IS_DG2(dev_priv)) 2136 /* DG2's "TC1" output uses a SNPS PHY */ 2137 return false; 2138 else if (IS_ALDERLAKE_P(dev_priv)) 2139 return phy >= PHY_F && phy <= PHY_I; 2140 else if (IS_TIGERLAKE(dev_priv)) 2141 return phy >= PHY_D && phy <= PHY_I; 2142 else if (IS_ICELAKE(dev_priv)) 2143 return phy >= PHY_C && phy <= PHY_F; 2144 else 2145 return false; 2146 } 2147 2148 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy) 2149 { 2150 if (phy == PHY_NONE) 2151 return false; 2152 else if (IS_DG2(dev_priv)) 2153 /* 2154 * All four "combo" ports and the TC1 port (PHY E) use 2155 * Synopsis PHYs. 2156 */ 2157 return phy <= PHY_E; 2158 2159 return false; 2160 } 2161 2162 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) 2163 { 2164 if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD) 2165 return PHY_D + port - PORT_D_XELPD; 2166 else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1) 2167 return PHY_F + port - PORT_TC1; 2168 else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1) 2169 return PHY_B + port - PORT_TC1; 2170 else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1) 2171 return PHY_C + port - PORT_TC1; 2172 else if (IS_JSL_EHL(i915) && port == PORT_D) 2173 return PHY_A; 2174 2175 return PHY_A + port - PORT_A; 2176 } 2177 2178 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) 2179 { 2180 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port))) 2181 return TC_PORT_NONE; 2182 2183 if (DISPLAY_VER(dev_priv) >= 12) 2184 return TC_PORT_1 + port - PORT_TC1; 2185 else 2186 return TC_PORT_1 + port - PORT_C; 2187 } 2188 2189 enum intel_display_power_domain intel_port_to_power_domain(enum port port) 2190 { 2191 switch (port) { 2192 case PORT_A: 2193 return POWER_DOMAIN_PORT_DDI_A_LANES; 2194 case PORT_B: 2195 return POWER_DOMAIN_PORT_DDI_B_LANES; 2196 case PORT_C: 2197 return POWER_DOMAIN_PORT_DDI_C_LANES; 2198 case PORT_D: 2199 return POWER_DOMAIN_PORT_DDI_D_LANES; 2200 case PORT_E: 2201 return POWER_DOMAIN_PORT_DDI_E_LANES; 2202 case PORT_F: 2203 return POWER_DOMAIN_PORT_DDI_F_LANES; 2204 case PORT_G: 2205 return POWER_DOMAIN_PORT_DDI_G_LANES; 2206 case PORT_H: 2207 return POWER_DOMAIN_PORT_DDI_H_LANES; 2208 case PORT_I: 2209 return POWER_DOMAIN_PORT_DDI_I_LANES; 2210 default: 2211 MISSING_CASE(port); 2212 return POWER_DOMAIN_PORT_OTHER; 2213 } 2214 } 2215 2216 enum intel_display_power_domain 2217 intel_aux_power_domain(struct intel_digital_port *dig_port) 2218 { 2219 if (intel_tc_port_in_tbt_alt_mode(dig_port)) { 2220 switch (dig_port->aux_ch) { 2221 case AUX_CH_C: 2222 return POWER_DOMAIN_AUX_C_TBT; 2223 case AUX_CH_D: 2224 return POWER_DOMAIN_AUX_D_TBT; 2225 case AUX_CH_E: 2226 return POWER_DOMAIN_AUX_E_TBT; 2227 case AUX_CH_F: 2228 return POWER_DOMAIN_AUX_F_TBT; 2229 case AUX_CH_G: 2230 return POWER_DOMAIN_AUX_G_TBT; 2231 case AUX_CH_H: 2232 return POWER_DOMAIN_AUX_H_TBT; 2233 case AUX_CH_I: 2234 return POWER_DOMAIN_AUX_I_TBT; 2235 default: 2236 MISSING_CASE(dig_port->aux_ch); 2237 return POWER_DOMAIN_AUX_C_TBT; 2238 } 2239 } 2240 2241 return intel_legacy_aux_to_power_domain(dig_port->aux_ch); 2242 } 2243 2244 /* 2245 * Converts aux_ch to power_domain without caring about TBT ports for that use 2246 * intel_aux_power_domain() 2247 */ 2248 enum intel_display_power_domain 2249 intel_legacy_aux_to_power_domain(enum aux_ch aux_ch) 2250 { 2251 switch (aux_ch) { 2252 case AUX_CH_A: 2253 return POWER_DOMAIN_AUX_A; 2254 case AUX_CH_B: 2255 return POWER_DOMAIN_AUX_B; 2256 case AUX_CH_C: 2257 return POWER_DOMAIN_AUX_C; 2258 case AUX_CH_D: 2259 return POWER_DOMAIN_AUX_D; 2260 case AUX_CH_E: 2261 return POWER_DOMAIN_AUX_E; 2262 case AUX_CH_F: 2263 return POWER_DOMAIN_AUX_F; 2264 case AUX_CH_G: 2265 return POWER_DOMAIN_AUX_G; 2266 case AUX_CH_H: 2267 return POWER_DOMAIN_AUX_H; 2268 case AUX_CH_I: 2269 return POWER_DOMAIN_AUX_I; 2270 default: 2271 MISSING_CASE(aux_ch); 2272 return POWER_DOMAIN_AUX_A; 2273 } 2274 } 2275 2276 static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state) 2277 { 2278 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2279 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2280 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2281 struct drm_encoder *encoder; 2282 enum pipe pipe = crtc->pipe; 2283 u64 mask; 2284 2285 if (!crtc_state->hw.active) 2286 return 0; 2287 2288 mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe)); 2289 mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 2290 if (crtc_state->pch_pfit.enabled || 2291 crtc_state->pch_pfit.force_thru) 2292 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); 2293 2294 drm_for_each_encoder_mask(encoder, &dev_priv->drm, 2295 crtc_state->uapi.encoder_mask) { 2296 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2297 2298 mask |= BIT_ULL(intel_encoder->power_domain); 2299 } 2300 2301 if (HAS_DDI(dev_priv) && crtc_state->has_audio) 2302 mask |= BIT_ULL(POWER_DOMAIN_AUDIO_MMIO); 2303 2304 if (crtc_state->shared_dpll) 2305 mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE); 2306 2307 if (crtc_state->dsc.compression_enable) 2308 mask |= BIT_ULL(intel_dsc_power_domain(crtc, cpu_transcoder)); 2309 2310 return mask; 2311 } 2312 2313 static u64 2314 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state) 2315 { 2316 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2317 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2318 enum intel_display_power_domain domain; 2319 u64 domains, new_domains, old_domains; 2320 2321 domains = get_crtc_power_domains(crtc_state); 2322 2323 new_domains = domains & ~crtc->enabled_power_domains.mask; 2324 old_domains = crtc->enabled_power_domains.mask & ~domains; 2325 2326 for_each_power_domain(domain, new_domains) 2327 intel_display_power_get_in_set(dev_priv, 2328 &crtc->enabled_power_domains, 2329 domain); 2330 2331 return old_domains; 2332 } 2333 2334 static void modeset_put_crtc_power_domains(struct intel_crtc *crtc, 2335 u64 domains) 2336 { 2337 intel_display_power_put_mask_in_set(to_i915(crtc->base.dev), 2338 &crtc->enabled_power_domains, 2339 domains); 2340 } 2341 2342 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 2343 { 2344 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2345 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2346 2347 if (intel_crtc_has_dp_encoder(crtc_state)) { 2348 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 2349 &crtc_state->dp_m_n); 2350 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 2351 &crtc_state->dp_m2_n2); 2352 } 2353 2354 intel_set_transcoder_timings(crtc_state); 2355 2356 i9xx_set_pipeconf(crtc_state); 2357 } 2358 2359 static void valleyview_crtc_enable(struct intel_atomic_state *state, 2360 struct intel_crtc *crtc) 2361 { 2362 const struct intel_crtc_state *new_crtc_state = 2363 intel_atomic_get_new_crtc_state(state, crtc); 2364 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2365 enum pipe pipe = crtc->pipe; 2366 2367 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 2368 return; 2369 2370 i9xx_configure_cpu_transcoder(new_crtc_state); 2371 2372 intel_set_pipe_src_size(new_crtc_state); 2373 2374 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 2375 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY); 2376 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0); 2377 } 2378 2379 crtc->active = true; 2380 2381 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2382 2383 intel_encoders_pre_pll_enable(state, crtc); 2384 2385 if (IS_CHERRYVIEW(dev_priv)) 2386 chv_enable_pll(new_crtc_state); 2387 else 2388 vlv_enable_pll(new_crtc_state); 2389 2390 intel_encoders_pre_enable(state, crtc); 2391 2392 i9xx_pfit_enable(new_crtc_state); 2393 2394 intel_color_load_luts(new_crtc_state); 2395 intel_color_commit_noarm(new_crtc_state); 2396 intel_color_commit_arm(new_crtc_state); 2397 /* update DSPCNTR to configure gamma for pipe bottom color */ 2398 intel_disable_primary_plane(new_crtc_state); 2399 2400 intel_initial_watermarks(state, crtc); 2401 intel_enable_transcoder(new_crtc_state); 2402 2403 intel_crtc_vblank_on(new_crtc_state); 2404 2405 intel_encoders_enable(state, crtc); 2406 } 2407 2408 static void i9xx_crtc_enable(struct intel_atomic_state *state, 2409 struct intel_crtc *crtc) 2410 { 2411 const struct intel_crtc_state *new_crtc_state = 2412 intel_atomic_get_new_crtc_state(state, crtc); 2413 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2414 enum pipe pipe = crtc->pipe; 2415 2416 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 2417 return; 2418 2419 i9xx_configure_cpu_transcoder(new_crtc_state); 2420 2421 intel_set_pipe_src_size(new_crtc_state); 2422 2423 crtc->active = true; 2424 2425 if (DISPLAY_VER(dev_priv) != 2) 2426 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2427 2428 intel_encoders_pre_enable(state, crtc); 2429 2430 i9xx_enable_pll(new_crtc_state); 2431 2432 i9xx_pfit_enable(new_crtc_state); 2433 2434 intel_color_load_luts(new_crtc_state); 2435 intel_color_commit_noarm(new_crtc_state); 2436 intel_color_commit_arm(new_crtc_state); 2437 /* update DSPCNTR to configure gamma for pipe bottom color */ 2438 intel_disable_primary_plane(new_crtc_state); 2439 2440 if (!intel_initial_watermarks(state, crtc)) 2441 intel_update_watermarks(dev_priv); 2442 intel_enable_transcoder(new_crtc_state); 2443 2444 intel_crtc_vblank_on(new_crtc_state); 2445 2446 intel_encoders_enable(state, crtc); 2447 2448 /* prevents spurious underruns */ 2449 if (DISPLAY_VER(dev_priv) == 2) 2450 intel_crtc_wait_for_next_vblank(crtc); 2451 } 2452 2453 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) 2454 { 2455 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 2456 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2457 2458 if (!old_crtc_state->gmch_pfit.control) 2459 return; 2460 2461 assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder); 2462 2463 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n", 2464 intel_de_read(dev_priv, PFIT_CONTROL)); 2465 intel_de_write(dev_priv, PFIT_CONTROL, 0); 2466 } 2467 2468 static void i9xx_crtc_disable(struct intel_atomic_state *state, 2469 struct intel_crtc *crtc) 2470 { 2471 struct intel_crtc_state *old_crtc_state = 2472 intel_atomic_get_old_crtc_state(state, crtc); 2473 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2474 enum pipe pipe = crtc->pipe; 2475 2476 /* 2477 * On gen2 planes are double buffered but the pipe isn't, so we must 2478 * wait for planes to fully turn off before disabling the pipe. 2479 */ 2480 if (DISPLAY_VER(dev_priv) == 2) 2481 intel_crtc_wait_for_next_vblank(crtc); 2482 2483 intel_encoders_disable(state, crtc); 2484 2485 intel_crtc_vblank_off(old_crtc_state); 2486 2487 intel_disable_transcoder(old_crtc_state); 2488 2489 i9xx_pfit_disable(old_crtc_state); 2490 2491 intel_encoders_post_disable(state, crtc); 2492 2493 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) { 2494 if (IS_CHERRYVIEW(dev_priv)) 2495 chv_disable_pll(dev_priv, pipe); 2496 else if (IS_VALLEYVIEW(dev_priv)) 2497 vlv_disable_pll(dev_priv, pipe); 2498 else 2499 i9xx_disable_pll(old_crtc_state); 2500 } 2501 2502 intel_encoders_post_pll_disable(state, crtc); 2503 2504 if (DISPLAY_VER(dev_priv) != 2) 2505 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 2506 2507 if (!dev_priv->wm_disp->initial_watermarks) 2508 intel_update_watermarks(dev_priv); 2509 2510 /* clock the pipe down to 640x480@60 to potentially save power */ 2511 if (IS_I830(dev_priv)) 2512 i830_enable_pipe(dev_priv, pipe); 2513 } 2514 2515 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, 2516 struct drm_modeset_acquire_ctx *ctx) 2517 { 2518 struct intel_encoder *encoder; 2519 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2520 struct intel_bw_state *bw_state = 2521 to_intel_bw_state(dev_priv->bw_obj.state); 2522 struct intel_cdclk_state *cdclk_state = 2523 to_intel_cdclk_state(dev_priv->cdclk.obj.state); 2524 struct intel_dbuf_state *dbuf_state = 2525 to_intel_dbuf_state(dev_priv->dbuf.obj.state); 2526 struct intel_crtc_state *crtc_state = 2527 to_intel_crtc_state(crtc->base.state); 2528 struct intel_plane *plane; 2529 struct drm_atomic_state *state; 2530 struct intel_crtc_state *temp_crtc_state; 2531 enum pipe pipe = crtc->pipe; 2532 int ret; 2533 2534 if (!crtc_state->hw.active) 2535 return; 2536 2537 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 2538 const struct intel_plane_state *plane_state = 2539 to_intel_plane_state(plane->base.state); 2540 2541 if (plane_state->uapi.visible) 2542 intel_plane_disable_noatomic(crtc, plane); 2543 } 2544 2545 state = drm_atomic_state_alloc(&dev_priv->drm); 2546 if (!state) { 2547 drm_dbg_kms(&dev_priv->drm, 2548 "failed to disable [CRTC:%d:%s], out of memory", 2549 crtc->base.base.id, crtc->base.name); 2550 return; 2551 } 2552 2553 state->acquire_ctx = ctx; 2554 2555 /* Everything's already locked, -EDEADLK can't happen. */ 2556 temp_crtc_state = intel_atomic_get_crtc_state(state, crtc); 2557 ret = drm_atomic_add_affected_connectors(state, &crtc->base); 2558 2559 drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret); 2560 2561 dev_priv->display->crtc_disable(to_intel_atomic_state(state), crtc); 2562 2563 drm_atomic_state_put(state); 2564 2565 drm_dbg_kms(&dev_priv->drm, 2566 "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", 2567 crtc->base.base.id, crtc->base.name); 2568 2569 crtc->active = false; 2570 crtc->base.enabled = false; 2571 2572 drm_WARN_ON(&dev_priv->drm, 2573 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0); 2574 crtc_state->uapi.active = false; 2575 crtc_state->uapi.connector_mask = 0; 2576 crtc_state->uapi.encoder_mask = 0; 2577 intel_crtc_free_hw_state(crtc_state); 2578 memset(&crtc_state->hw, 0, sizeof(crtc_state->hw)); 2579 2580 for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder) 2581 encoder->base.crtc = NULL; 2582 2583 intel_fbc_disable(crtc); 2584 intel_update_watermarks(dev_priv); 2585 intel_disable_shared_dpll(crtc_state); 2586 2587 intel_display_power_put_all_in_set(dev_priv, &crtc->enabled_power_domains); 2588 2589 cdclk_state->min_cdclk[pipe] = 0; 2590 cdclk_state->min_voltage_level[pipe] = 0; 2591 cdclk_state->active_pipes &= ~BIT(pipe); 2592 2593 dbuf_state->active_pipes &= ~BIT(pipe); 2594 2595 bw_state->data_rate[pipe] = 0; 2596 bw_state->num_active_planes[pipe] = 0; 2597 } 2598 2599 /* 2600 * turn all crtc's off, but do not adjust state 2601 * This has to be paired with a call to intel_modeset_setup_hw_state. 2602 */ 2603 int intel_display_suspend(struct drm_device *dev) 2604 { 2605 struct drm_i915_private *dev_priv = to_i915(dev); 2606 struct drm_atomic_state *state; 2607 int ret; 2608 2609 if (!HAS_DISPLAY(dev_priv)) 2610 return 0; 2611 2612 state = drm_atomic_helper_suspend(dev); 2613 ret = PTR_ERR_OR_ZERO(state); 2614 if (ret) 2615 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", 2616 ret); 2617 else 2618 dev_priv->modeset_restore_state = state; 2619 return ret; 2620 } 2621 2622 void intel_encoder_destroy(struct drm_encoder *encoder) 2623 { 2624 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2625 2626 drm_encoder_cleanup(encoder); 2627 kfree(intel_encoder); 2628 } 2629 2630 /* Cross check the actual hw state with our own modeset state tracking (and it's 2631 * internal consistency). */ 2632 static void intel_connector_verify_state(struct intel_crtc_state *crtc_state, 2633 struct drm_connector_state *conn_state) 2634 { 2635 struct intel_connector *connector = to_intel_connector(conn_state->connector); 2636 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2637 2638 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", 2639 connector->base.base.id, connector->base.name); 2640 2641 if (connector->get_hw_state(connector)) { 2642 struct intel_encoder *encoder = intel_attached_encoder(connector); 2643 2644 I915_STATE_WARN(!crtc_state, 2645 "connector enabled without attached crtc\n"); 2646 2647 if (!crtc_state) 2648 return; 2649 2650 I915_STATE_WARN(!crtc_state->hw.active, 2651 "connector is active, but attached crtc isn't\n"); 2652 2653 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) 2654 return; 2655 2656 I915_STATE_WARN(conn_state->best_encoder != &encoder->base, 2657 "atomic encoder doesn't match attached encoder\n"); 2658 2659 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, 2660 "attached encoder crtc differs from connector crtc\n"); 2661 } else { 2662 I915_STATE_WARN(crtc_state && crtc_state->hw.active, 2663 "attached crtc is active, but connector isn't\n"); 2664 I915_STATE_WARN(!crtc_state && conn_state->best_encoder, 2665 "best encoder set without crtc!\n"); 2666 } 2667 } 2668 2669 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) 2670 { 2671 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2672 2673 /* GDG double wide on either pipe, otherwise pipe A only */ 2674 return DISPLAY_VER(dev_priv) < 4 && 2675 (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); 2676 } 2677 2678 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) 2679 { 2680 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock; 2681 struct drm_rect src; 2682 2683 /* 2684 * We only use IF-ID interlacing. If we ever use 2685 * PF-ID we'll need to adjust the pixel_rate here. 2686 */ 2687 2688 if (!crtc_state->pch_pfit.enabled) 2689 return pixel_rate; 2690 2691 drm_rect_init(&src, 0, 0, 2692 drm_rect_width(&crtc_state->pipe_src) << 16, 2693 drm_rect_height(&crtc_state->pipe_src) << 16); 2694 2695 return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst, 2696 pixel_rate); 2697 } 2698 2699 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode, 2700 const struct drm_display_mode *timings) 2701 { 2702 mode->hdisplay = timings->crtc_hdisplay; 2703 mode->htotal = timings->crtc_htotal; 2704 mode->hsync_start = timings->crtc_hsync_start; 2705 mode->hsync_end = timings->crtc_hsync_end; 2706 2707 mode->vdisplay = timings->crtc_vdisplay; 2708 mode->vtotal = timings->crtc_vtotal; 2709 mode->vsync_start = timings->crtc_vsync_start; 2710 mode->vsync_end = timings->crtc_vsync_end; 2711 2712 mode->flags = timings->flags; 2713 mode->type = DRM_MODE_TYPE_DRIVER; 2714 2715 mode->clock = timings->crtc_clock; 2716 2717 drm_mode_set_name(mode); 2718 } 2719 2720 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) 2721 { 2722 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2723 2724 if (HAS_GMCH(dev_priv)) 2725 /* FIXME calculate proper pipe pixel rate for GMCH pfit */ 2726 crtc_state->pixel_rate = 2727 crtc_state->hw.pipe_mode.crtc_clock; 2728 else 2729 crtc_state->pixel_rate = 2730 ilk_pipe_pixel_rate(crtc_state); 2731 } 2732 2733 static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state *crtc_state, 2734 struct drm_display_mode *mode) 2735 { 2736 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2737 2738 if (num_pipes < 2) 2739 return; 2740 2741 mode->crtc_clock /= num_pipes; 2742 mode->crtc_hdisplay /= num_pipes; 2743 mode->crtc_hblank_start /= num_pipes; 2744 mode->crtc_hblank_end /= num_pipes; 2745 mode->crtc_hsync_start /= num_pipes; 2746 mode->crtc_hsync_end /= num_pipes; 2747 mode->crtc_htotal /= num_pipes; 2748 } 2749 2750 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state, 2751 struct drm_display_mode *mode) 2752 { 2753 int overlap = crtc_state->splitter.pixel_overlap; 2754 int n = crtc_state->splitter.link_count; 2755 2756 if (!crtc_state->splitter.enable) 2757 return; 2758 2759 /* 2760 * eDP MSO uses segment timings from EDID for transcoder 2761 * timings, but full mode for everything else. 2762 * 2763 * h_full = (h_segment - pixel_overlap) * link_count 2764 */ 2765 mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n; 2766 mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n; 2767 mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n; 2768 mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n; 2769 mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n; 2770 mode->crtc_htotal = (mode->crtc_htotal - overlap) * n; 2771 mode->crtc_clock *= n; 2772 } 2773 2774 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state) 2775 { 2776 struct drm_display_mode *mode = &crtc_state->hw.mode; 2777 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2778 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2779 2780 /* 2781 * Start with the adjusted_mode crtc timings, which 2782 * have been filled with the transcoder timings. 2783 */ 2784 drm_mode_copy(pipe_mode, adjusted_mode); 2785 2786 /* Expand MSO per-segment transcoder timings to full */ 2787 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2788 2789 /* 2790 * We want the full numbers in adjusted_mode normal timings, 2791 * adjusted_mode crtc timings are left with the raw transcoder 2792 * timings. 2793 */ 2794 intel_mode_from_crtc_timings(adjusted_mode, pipe_mode); 2795 2796 /* Populate the "user" mode with full numbers */ 2797 drm_mode_copy(mode, pipe_mode); 2798 intel_mode_from_crtc_timings(mode, mode); 2799 mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) * 2800 (intel_bigjoiner_num_pipes(crtc_state) ?: 1); 2801 mode->vdisplay = drm_rect_height(&crtc_state->pipe_src); 2802 2803 /* Derive per-pipe timings in case bigjoiner is used */ 2804 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2805 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2806 2807 intel_crtc_compute_pixel_rate(crtc_state); 2808 } 2809 2810 static void intel_encoder_get_config(struct intel_encoder *encoder, 2811 struct intel_crtc_state *crtc_state) 2812 { 2813 encoder->get_config(encoder, crtc_state); 2814 2815 intel_crtc_readout_derived_state(crtc_state); 2816 } 2817 2818 static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state *crtc_state) 2819 { 2820 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2821 int width, height; 2822 2823 if (num_pipes < 2) 2824 return; 2825 2826 width = drm_rect_width(&crtc_state->pipe_src); 2827 height = drm_rect_height(&crtc_state->pipe_src); 2828 2829 drm_rect_init(&crtc_state->pipe_src, 0, 0, 2830 width / num_pipes, height); 2831 } 2832 2833 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state) 2834 { 2835 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2836 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2837 2838 intel_bigjoiner_compute_pipe_src(crtc_state); 2839 2840 /* 2841 * Pipe horizontal size must be even in: 2842 * - DVO ganged mode 2843 * - LVDS dual channel mode 2844 * - Double wide pipe 2845 */ 2846 if (drm_rect_width(&crtc_state->pipe_src) & 1) { 2847 if (crtc_state->double_wide) { 2848 drm_dbg_kms(&i915->drm, 2849 "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n", 2850 crtc->base.base.id, crtc->base.name); 2851 return -EINVAL; 2852 } 2853 2854 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 2855 intel_is_dual_link_lvds(i915)) { 2856 drm_dbg_kms(&i915->drm, 2857 "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n", 2858 crtc->base.base.id, crtc->base.name); 2859 return -EINVAL; 2860 } 2861 } 2862 2863 return 0; 2864 } 2865 2866 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state) 2867 { 2868 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2869 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2870 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2871 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2872 int clock_limit = i915->max_dotclk_freq; 2873 2874 /* 2875 * Start with the adjusted_mode crtc timings, which 2876 * have been filled with the transcoder timings. 2877 */ 2878 drm_mode_copy(pipe_mode, adjusted_mode); 2879 2880 /* Expand MSO per-segment transcoder timings to full */ 2881 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2882 2883 /* Derive per-pipe timings in case bigjoiner is used */ 2884 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2885 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2886 2887 if (DISPLAY_VER(i915) < 4) { 2888 clock_limit = i915->max_cdclk_freq * 9 / 10; 2889 2890 /* 2891 * Enable double wide mode when the dot clock 2892 * is > 90% of the (display) core speed. 2893 */ 2894 if (intel_crtc_supports_double_wide(crtc) && 2895 pipe_mode->crtc_clock > clock_limit) { 2896 clock_limit = i915->max_dotclk_freq; 2897 crtc_state->double_wide = true; 2898 } 2899 } 2900 2901 if (pipe_mode->crtc_clock > clock_limit) { 2902 drm_dbg_kms(&i915->drm, 2903 "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", 2904 crtc->base.base.id, crtc->base.name, 2905 pipe_mode->crtc_clock, clock_limit, 2906 str_yes_no(crtc_state->double_wide)); 2907 return -EINVAL; 2908 } 2909 2910 return 0; 2911 } 2912 2913 static int intel_crtc_compute_config(struct intel_crtc *crtc, 2914 struct intel_crtc_state *crtc_state) 2915 { 2916 int ret; 2917 2918 ret = intel_crtc_compute_pipe_src(crtc_state); 2919 if (ret) 2920 return ret; 2921 2922 ret = intel_crtc_compute_pipe_mode(crtc_state); 2923 if (ret) 2924 return ret; 2925 2926 intel_crtc_compute_pixel_rate(crtc_state); 2927 2928 if (crtc_state->has_pch_encoder) 2929 return ilk_fdi_compute_config(crtc, crtc_state); 2930 2931 return 0; 2932 } 2933 2934 static void 2935 intel_reduce_m_n_ratio(u32 *num, u32 *den) 2936 { 2937 while (*num > DATA_LINK_M_N_MASK || 2938 *den > DATA_LINK_M_N_MASK) { 2939 *num >>= 1; 2940 *den >>= 1; 2941 } 2942 } 2943 2944 static void compute_m_n(unsigned int m, unsigned int n, 2945 u32 *ret_m, u32 *ret_n, 2946 bool constant_n) 2947 { 2948 /* 2949 * Several DP dongles in particular seem to be fussy about 2950 * too large link M/N values. Give N value as 0x8000 that 2951 * should be acceptable by specific devices. 0x8000 is the 2952 * specified fixed N value for asynchronous clock mode, 2953 * which the devices expect also in synchronous clock mode. 2954 */ 2955 if (constant_n) 2956 *ret_n = DP_LINK_CONSTANT_N_VALUE; 2957 else 2958 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); 2959 2960 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n); 2961 intel_reduce_m_n_ratio(ret_m, ret_n); 2962 } 2963 2964 void 2965 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes, 2966 int pixel_clock, int link_clock, 2967 struct intel_link_m_n *m_n, 2968 bool constant_n, bool fec_enable) 2969 { 2970 u32 data_clock = bits_per_pixel * pixel_clock; 2971 2972 if (fec_enable) 2973 data_clock = intel_dp_mode_to_fec_clock(data_clock); 2974 2975 m_n->tu = 64; 2976 compute_m_n(data_clock, 2977 link_clock * nlanes * 8, 2978 &m_n->data_m, &m_n->data_n, 2979 constant_n); 2980 2981 compute_m_n(pixel_clock, link_clock, 2982 &m_n->link_m, &m_n->link_n, 2983 constant_n); 2984 } 2985 2986 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv) 2987 { 2988 /* 2989 * There may be no VBT; and if the BIOS enabled SSC we can 2990 * just keep using it to avoid unnecessary flicker. Whereas if the 2991 * BIOS isn't using it, don't assume it will work even if the VBT 2992 * indicates as much. 2993 */ 2994 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { 2995 bool bios_lvds_use_ssc = intel_de_read(dev_priv, 2996 PCH_DREF_CONTROL) & 2997 DREF_SSC1_ENABLE; 2998 2999 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { 3000 drm_dbg_kms(&dev_priv->drm, 3001 "SSC %s by BIOS, overriding VBT which says %s\n", 3002 str_enabled_disabled(bios_lvds_use_ssc), 3003 str_enabled_disabled(dev_priv->vbt.lvds_use_ssc)); 3004 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; 3005 } 3006 } 3007 } 3008 3009 void intel_zero_m_n(struct intel_link_m_n *m_n) 3010 { 3011 /* corresponds to 0 register value */ 3012 memset(m_n, 0, sizeof(*m_n)); 3013 m_n->tu = 1; 3014 } 3015 3016 void intel_set_m_n(struct drm_i915_private *i915, 3017 const struct intel_link_m_n *m_n, 3018 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 3019 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 3020 { 3021 intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); 3022 intel_de_write(i915, data_n_reg, m_n->data_n); 3023 intel_de_write(i915, link_m_reg, m_n->link_m); 3024 /* 3025 * On BDW+ writing LINK_N arms the double buffered update 3026 * of all the M/N registers, so it must be written last. 3027 */ 3028 intel_de_write(i915, link_n_reg, m_n->link_n); 3029 } 3030 3031 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, 3032 enum transcoder transcoder) 3033 { 3034 if (IS_HASWELL(dev_priv)) 3035 return transcoder == TRANSCODER_EDP; 3036 3037 return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv); 3038 } 3039 3040 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, 3041 enum transcoder transcoder, 3042 const struct intel_link_m_n *m_n) 3043 { 3044 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3045 enum pipe pipe = crtc->pipe; 3046 3047 if (DISPLAY_VER(dev_priv) >= 5) 3048 intel_set_m_n(dev_priv, m_n, 3049 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 3050 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 3051 else 3052 intel_set_m_n(dev_priv, m_n, 3053 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 3054 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 3055 } 3056 3057 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, 3058 enum transcoder transcoder, 3059 const struct intel_link_m_n *m_n) 3060 { 3061 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3062 3063 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 3064 return; 3065 3066 intel_set_m_n(dev_priv, m_n, 3067 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 3068 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 3069 } 3070 3071 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) 3072 { 3073 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3074 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3075 enum pipe pipe = crtc->pipe; 3076 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3077 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 3078 u32 crtc_vtotal, crtc_vblank_end; 3079 int vsyncshift = 0; 3080 3081 /* We need to be careful not to changed the adjusted mode, for otherwise 3082 * the hw state checker will get angry at the mismatch. */ 3083 crtc_vtotal = adjusted_mode->crtc_vtotal; 3084 crtc_vblank_end = adjusted_mode->crtc_vblank_end; 3085 3086 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 3087 /* the chip adds 2 halflines automatically */ 3088 crtc_vtotal -= 1; 3089 crtc_vblank_end -= 1; 3090 3091 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3092 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; 3093 else 3094 vsyncshift = adjusted_mode->crtc_hsync_start - 3095 adjusted_mode->crtc_htotal / 2; 3096 if (vsyncshift < 0) 3097 vsyncshift += adjusted_mode->crtc_htotal; 3098 } 3099 3100 if (DISPLAY_VER(dev_priv) > 3) 3101 intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder), 3102 vsyncshift); 3103 3104 intel_de_write(dev_priv, HTOTAL(cpu_transcoder), 3105 (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16)); 3106 intel_de_write(dev_priv, HBLANK(cpu_transcoder), 3107 (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16)); 3108 intel_de_write(dev_priv, HSYNC(cpu_transcoder), 3109 (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16)); 3110 3111 intel_de_write(dev_priv, VTOTAL(cpu_transcoder), 3112 (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16)); 3113 intel_de_write(dev_priv, VBLANK(cpu_transcoder), 3114 (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16)); 3115 intel_de_write(dev_priv, VSYNC(cpu_transcoder), 3116 (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16)); 3117 3118 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be 3119 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is 3120 * documented on the DDI_FUNC_CTL register description, EDP Input Select 3121 * bits. */ 3122 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && 3123 (pipe == PIPE_B || pipe == PIPE_C)) 3124 intel_de_write(dev_priv, VTOTAL(pipe), 3125 intel_de_read(dev_priv, VTOTAL(cpu_transcoder))); 3126 3127 } 3128 3129 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) 3130 { 3131 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3132 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3133 int width = drm_rect_width(&crtc_state->pipe_src); 3134 int height = drm_rect_height(&crtc_state->pipe_src); 3135 enum pipe pipe = crtc->pipe; 3136 3137 /* pipesrc controls the size that is scaled from, which should 3138 * always be the user's requested size. 3139 */ 3140 intel_de_write(dev_priv, PIPESRC(pipe), 3141 PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1)); 3142 } 3143 3144 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) 3145 { 3146 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3147 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3148 3149 if (DISPLAY_VER(dev_priv) == 2) 3150 return false; 3151 3152 if (DISPLAY_VER(dev_priv) >= 9 || 3153 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 3154 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW; 3155 else 3156 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK; 3157 } 3158 3159 static void intel_get_transcoder_timings(struct intel_crtc *crtc, 3160 struct intel_crtc_state *pipe_config) 3161 { 3162 struct drm_device *dev = crtc->base.dev; 3163 struct drm_i915_private *dev_priv = to_i915(dev); 3164 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3165 u32 tmp; 3166 3167 tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder)); 3168 pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; 3169 pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; 3170 3171 if (!transcoder_is_dsi(cpu_transcoder)) { 3172 tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder)); 3173 pipe_config->hw.adjusted_mode.crtc_hblank_start = 3174 (tmp & 0xffff) + 1; 3175 pipe_config->hw.adjusted_mode.crtc_hblank_end = 3176 ((tmp >> 16) & 0xffff) + 1; 3177 } 3178 tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder)); 3179 pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; 3180 pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; 3181 3182 tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder)); 3183 pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; 3184 pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; 3185 3186 if (!transcoder_is_dsi(cpu_transcoder)) { 3187 tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder)); 3188 pipe_config->hw.adjusted_mode.crtc_vblank_start = 3189 (tmp & 0xffff) + 1; 3190 pipe_config->hw.adjusted_mode.crtc_vblank_end = 3191 ((tmp >> 16) & 0xffff) + 1; 3192 } 3193 tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder)); 3194 pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; 3195 pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; 3196 3197 if (intel_pipe_is_interlaced(pipe_config)) { 3198 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; 3199 pipe_config->hw.adjusted_mode.crtc_vtotal += 1; 3200 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1; 3201 } 3202 } 3203 3204 static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state) 3205 { 3206 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3207 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 3208 enum pipe master_pipe, pipe = crtc->pipe; 3209 int width; 3210 3211 if (num_pipes < 2) 3212 return; 3213 3214 master_pipe = bigjoiner_master_pipe(crtc_state); 3215 width = drm_rect_width(&crtc_state->pipe_src); 3216 3217 drm_rect_translate_to(&crtc_state->pipe_src, 3218 (pipe - master_pipe) * width, 0); 3219 } 3220 3221 static void intel_get_pipe_src_size(struct intel_crtc *crtc, 3222 struct intel_crtc_state *pipe_config) 3223 { 3224 struct drm_device *dev = crtc->base.dev; 3225 struct drm_i915_private *dev_priv = to_i915(dev); 3226 u32 tmp; 3227 3228 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe)); 3229 3230 drm_rect_init(&pipe_config->pipe_src, 0, 0, 3231 REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1, 3232 REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1); 3233 3234 intel_bigjoiner_adjust_pipe_src(pipe_config); 3235 } 3236 3237 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) 3238 { 3239 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3240 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3241 u32 pipeconf = 0; 3242 3243 /* we keep both pipes enabled on 830 */ 3244 if (IS_I830(dev_priv)) 3245 pipeconf |= PIPECONF_ENABLE; 3246 3247 if (crtc_state->double_wide) 3248 pipeconf |= PIPECONF_DOUBLE_WIDE; 3249 3250 /* only g4x and later have fancy bpc/dither controls */ 3251 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 3252 IS_CHERRYVIEW(dev_priv)) { 3253 /* Bspec claims that we can't use dithering for 30bpp pipes. */ 3254 if (crtc_state->dither && crtc_state->pipe_bpp != 30) 3255 pipeconf |= PIPECONF_DITHER_EN | 3256 PIPECONF_DITHER_TYPE_SP; 3257 3258 switch (crtc_state->pipe_bpp) { 3259 case 18: 3260 pipeconf |= PIPECONF_BPC_6; 3261 break; 3262 case 24: 3263 pipeconf |= PIPECONF_BPC_8; 3264 break; 3265 case 30: 3266 pipeconf |= PIPECONF_BPC_10; 3267 break; 3268 default: 3269 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3270 BUG(); 3271 } 3272 } 3273 3274 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 3275 if (DISPLAY_VER(dev_priv) < 4 || 3276 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3277 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; 3278 else 3279 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; 3280 } else { 3281 pipeconf |= PIPECONF_INTERLACE_PROGRESSIVE; 3282 } 3283 3284 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 3285 crtc_state->limited_color_range) 3286 pipeconf |= PIPECONF_COLOR_RANGE_SELECT; 3287 3288 pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); 3289 3290 pipeconf |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3291 3292 intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf); 3293 intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe)); 3294 } 3295 3296 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv) 3297 { 3298 if (IS_I830(dev_priv)) 3299 return false; 3300 3301 return DISPLAY_VER(dev_priv) >= 4 || 3302 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); 3303 } 3304 3305 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state) 3306 { 3307 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3308 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3309 u32 tmp; 3310 3311 if (!i9xx_has_pfit(dev_priv)) 3312 return; 3313 3314 tmp = intel_de_read(dev_priv, PFIT_CONTROL); 3315 if (!(tmp & PFIT_ENABLE)) 3316 return; 3317 3318 /* Check whether the pfit is attached to our pipe. */ 3319 if (DISPLAY_VER(dev_priv) < 4) { 3320 if (crtc->pipe != PIPE_B) 3321 return; 3322 } else { 3323 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) 3324 return; 3325 } 3326 3327 crtc_state->gmch_pfit.control = tmp; 3328 crtc_state->gmch_pfit.pgm_ratios = 3329 intel_de_read(dev_priv, PFIT_PGM_RATIOS); 3330 } 3331 3332 static void vlv_crtc_clock_get(struct intel_crtc *crtc, 3333 struct intel_crtc_state *pipe_config) 3334 { 3335 struct drm_device *dev = crtc->base.dev; 3336 struct drm_i915_private *dev_priv = to_i915(dev); 3337 enum pipe pipe = crtc->pipe; 3338 struct dpll clock; 3339 u32 mdiv; 3340 int refclk = 100000; 3341 3342 /* In case of DSI, DPLL will not be used */ 3343 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 3344 return; 3345 3346 vlv_dpio_get(dev_priv); 3347 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); 3348 vlv_dpio_put(dev_priv); 3349 3350 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; 3351 clock.m2 = mdiv & DPIO_M2DIV_MASK; 3352 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; 3353 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; 3354 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; 3355 3356 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); 3357 } 3358 3359 static void chv_crtc_clock_get(struct intel_crtc *crtc, 3360 struct intel_crtc_state *pipe_config) 3361 { 3362 struct drm_device *dev = crtc->base.dev; 3363 struct drm_i915_private *dev_priv = to_i915(dev); 3364 enum pipe pipe = crtc->pipe; 3365 enum dpio_channel port = vlv_pipe_to_channel(pipe); 3366 struct dpll clock; 3367 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; 3368 int refclk = 100000; 3369 3370 /* In case of DSI, DPLL will not be used */ 3371 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 3372 return; 3373 3374 vlv_dpio_get(dev_priv); 3375 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); 3376 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); 3377 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); 3378 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); 3379 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); 3380 vlv_dpio_put(dev_priv); 3381 3382 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; 3383 clock.m2 = (pll_dw0 & 0xff) << 22; 3384 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) 3385 clock.m2 |= pll_dw2 & 0x3fffff; 3386 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; 3387 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; 3388 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; 3389 3390 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); 3391 } 3392 3393 static enum intel_output_format 3394 bdw_get_pipemisc_output_format(struct intel_crtc *crtc) 3395 { 3396 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3397 u32 tmp; 3398 3399 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); 3400 3401 if (tmp & PIPEMISC_YUV420_ENABLE) { 3402 /* We support 4:2:0 in full blend mode only */ 3403 drm_WARN_ON(&dev_priv->drm, 3404 (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0); 3405 3406 return INTEL_OUTPUT_FORMAT_YCBCR420; 3407 } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) { 3408 return INTEL_OUTPUT_FORMAT_YCBCR444; 3409 } else { 3410 return INTEL_OUTPUT_FORMAT_RGB; 3411 } 3412 } 3413 3414 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state) 3415 { 3416 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3417 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 3418 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3419 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 3420 u32 tmp; 3421 3422 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); 3423 3424 if (tmp & DISP_PIPE_GAMMA_ENABLE) 3425 crtc_state->gamma_enable = true; 3426 3427 if (!HAS_GMCH(dev_priv) && 3428 tmp & DISP_PIPE_CSC_ENABLE) 3429 crtc_state->csc_enable = true; 3430 } 3431 3432 static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 3433 struct intel_crtc_state *pipe_config) 3434 { 3435 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3436 enum intel_display_power_domain power_domain; 3437 intel_wakeref_t wakeref; 3438 u32 tmp; 3439 bool ret; 3440 3441 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3442 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3443 if (!wakeref) 3444 return false; 3445 3446 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3447 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3448 pipe_config->shared_dpll = NULL; 3449 3450 ret = false; 3451 3452 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); 3453 if (!(tmp & PIPECONF_ENABLE)) 3454 goto out; 3455 3456 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 3457 IS_CHERRYVIEW(dev_priv)) { 3458 switch (tmp & PIPECONF_BPC_MASK) { 3459 case PIPECONF_BPC_6: 3460 pipe_config->pipe_bpp = 18; 3461 break; 3462 case PIPECONF_BPC_8: 3463 pipe_config->pipe_bpp = 24; 3464 break; 3465 case PIPECONF_BPC_10: 3466 pipe_config->pipe_bpp = 30; 3467 break; 3468 default: 3469 MISSING_CASE(tmp); 3470 break; 3471 } 3472 } 3473 3474 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 3475 (tmp & PIPECONF_COLOR_RANGE_SELECT)) 3476 pipe_config->limited_color_range = true; 3477 3478 pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_I9XX, tmp); 3479 3480 pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1; 3481 3482 if (IS_CHERRYVIEW(dev_priv)) 3483 pipe_config->cgm_mode = intel_de_read(dev_priv, 3484 CGM_PIPE_MODE(crtc->pipe)); 3485 3486 i9xx_get_pipe_color_config(pipe_config); 3487 intel_color_get_config(pipe_config); 3488 3489 if (DISPLAY_VER(dev_priv) < 4) 3490 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; 3491 3492 intel_get_transcoder_timings(crtc, pipe_config); 3493 intel_get_pipe_src_size(crtc, pipe_config); 3494 3495 i9xx_get_pfit_config(pipe_config); 3496 3497 if (DISPLAY_VER(dev_priv) >= 4) { 3498 /* No way to read it out on pipes B and C */ 3499 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) 3500 tmp = dev_priv->chv_dpll_md[crtc->pipe]; 3501 else 3502 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe)); 3503 pipe_config->pixel_multiplier = 3504 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) 3505 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; 3506 pipe_config->dpll_hw_state.dpll_md = tmp; 3507 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 3508 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 3509 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe)); 3510 pipe_config->pixel_multiplier = 3511 ((tmp & SDVO_MULTIPLIER_MASK) 3512 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; 3513 } else { 3514 /* Note that on i915G/GM the pixel multiplier is in the sdvo 3515 * port and will be fixed up in the encoder->get_config 3516 * function. */ 3517 pipe_config->pixel_multiplier = 1; 3518 } 3519 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv, 3520 DPLL(crtc->pipe)); 3521 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 3522 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv, 3523 FP0(crtc->pipe)); 3524 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv, 3525 FP1(crtc->pipe)); 3526 } else { 3527 /* Mask out read-only status bits. */ 3528 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | 3529 DPLL_PORTC_READY_MASK | 3530 DPLL_PORTB_READY_MASK); 3531 } 3532 3533 if (IS_CHERRYVIEW(dev_priv)) 3534 chv_crtc_clock_get(crtc, pipe_config); 3535 else if (IS_VALLEYVIEW(dev_priv)) 3536 vlv_crtc_clock_get(crtc, pipe_config); 3537 else 3538 i9xx_crtc_clock_get(crtc, pipe_config); 3539 3540 /* 3541 * Normally the dotclock is filled in by the encoder .get_config() 3542 * but in case the pipe is enabled w/o any ports we need a sane 3543 * default. 3544 */ 3545 pipe_config->hw.adjusted_mode.crtc_clock = 3546 pipe_config->port_clock / pipe_config->pixel_multiplier; 3547 3548 ret = true; 3549 3550 out: 3551 intel_display_power_put(dev_priv, power_domain, wakeref); 3552 3553 return ret; 3554 } 3555 3556 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) 3557 { 3558 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3559 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3560 enum pipe pipe = crtc->pipe; 3561 u32 val; 3562 3563 val = 0; 3564 3565 switch (crtc_state->pipe_bpp) { 3566 case 18: 3567 val |= PIPECONF_BPC_6; 3568 break; 3569 case 24: 3570 val |= PIPECONF_BPC_8; 3571 break; 3572 case 30: 3573 val |= PIPECONF_BPC_10; 3574 break; 3575 case 36: 3576 val |= PIPECONF_BPC_12; 3577 break; 3578 default: 3579 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3580 BUG(); 3581 } 3582 3583 if (crtc_state->dither) 3584 val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP; 3585 3586 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3587 val |= PIPECONF_INTERLACE_IF_ID_ILK; 3588 else 3589 val |= PIPECONF_INTERLACE_PF_PD_ILK; 3590 3591 /* 3592 * This would end up with an odd purple hue over 3593 * the entire display. Make sure we don't do it. 3594 */ 3595 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 3596 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 3597 3598 if (crtc_state->limited_color_range && 3599 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3600 val |= PIPECONF_COLOR_RANGE_SELECT; 3601 3602 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3603 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709; 3604 3605 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); 3606 3607 val |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3608 val |= PIPECONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay); 3609 3610 intel_de_write(dev_priv, PIPECONF(pipe), val); 3611 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 3612 } 3613 3614 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) 3615 { 3616 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3617 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3618 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3619 u32 val = 0; 3620 3621 if (IS_HASWELL(dev_priv) && crtc_state->dither) 3622 val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP; 3623 3624 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3625 val |= PIPECONF_INTERLACE_IF_ID_ILK; 3626 else 3627 val |= PIPECONF_INTERLACE_PF_PD_ILK; 3628 3629 if (IS_HASWELL(dev_priv) && 3630 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3631 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW; 3632 3633 intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val); 3634 intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder)); 3635 } 3636 3637 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) 3638 { 3639 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3640 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3641 u32 val = 0; 3642 3643 switch (crtc_state->pipe_bpp) { 3644 case 18: 3645 val |= PIPEMISC_BPC_6; 3646 break; 3647 case 24: 3648 val |= PIPEMISC_BPC_8; 3649 break; 3650 case 30: 3651 val |= PIPEMISC_BPC_10; 3652 break; 3653 case 36: 3654 /* Port output 12BPC defined for ADLP+ */ 3655 if (DISPLAY_VER(dev_priv) > 12) 3656 val |= PIPEMISC_BPC_12_ADLP; 3657 break; 3658 default: 3659 MISSING_CASE(crtc_state->pipe_bpp); 3660 break; 3661 } 3662 3663 if (crtc_state->dither) 3664 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; 3665 3666 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 3667 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 3668 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV; 3669 3670 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 3671 val |= PIPEMISC_YUV420_ENABLE | 3672 PIPEMISC_YUV420_MODE_FULL_BLEND; 3673 3674 if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state)) 3675 val |= PIPEMISC_HDR_MODE_PRECISION; 3676 3677 if (DISPLAY_VER(dev_priv) >= 12) 3678 val |= PIPEMISC_PIXEL_ROUNDING_TRUNC; 3679 3680 intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val); 3681 } 3682 3683 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) 3684 { 3685 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3686 u32 tmp; 3687 3688 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); 3689 3690 switch (tmp & PIPEMISC_BPC_MASK) { 3691 case PIPEMISC_BPC_6: 3692 return 18; 3693 case PIPEMISC_BPC_8: 3694 return 24; 3695 case PIPEMISC_BPC_10: 3696 return 30; 3697 /* 3698 * PORT OUTPUT 12 BPC defined for ADLP+. 3699 * 3700 * TODO: 3701 * For previous platforms with DSI interface, bits 5:7 3702 * are used for storing pipe_bpp irrespective of dithering. 3703 * Since the value of 12 BPC is not defined for these bits 3704 * on older platforms, need to find a workaround for 12 BPC 3705 * MIPI DSI HW readout. 3706 */ 3707 case PIPEMISC_BPC_12_ADLP: 3708 if (DISPLAY_VER(dev_priv) > 12) 3709 return 36; 3710 fallthrough; 3711 default: 3712 MISSING_CASE(tmp); 3713 return 0; 3714 } 3715 } 3716 3717 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) 3718 { 3719 /* 3720 * Account for spread spectrum to avoid 3721 * oversubscribing the link. Max center spread 3722 * is 2.5%; use 5% for safety's sake. 3723 */ 3724 u32 bps = target_clock * bpp * 21 / 20; 3725 return DIV_ROUND_UP(bps, link_bw * 8); 3726 } 3727 3728 void intel_get_m_n(struct drm_i915_private *i915, 3729 struct intel_link_m_n *m_n, 3730 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 3731 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 3732 { 3733 m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK; 3734 m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK; 3735 m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK; 3736 m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK; 3737 m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1; 3738 } 3739 3740 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, 3741 enum transcoder transcoder, 3742 struct intel_link_m_n *m_n) 3743 { 3744 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3745 enum pipe pipe = crtc->pipe; 3746 3747 if (DISPLAY_VER(dev_priv) >= 5) 3748 intel_get_m_n(dev_priv, m_n, 3749 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 3750 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 3751 else 3752 intel_get_m_n(dev_priv, m_n, 3753 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 3754 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 3755 } 3756 3757 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, 3758 enum transcoder transcoder, 3759 struct intel_link_m_n *m_n) 3760 { 3761 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3762 3763 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 3764 return; 3765 3766 intel_get_m_n(dev_priv, m_n, 3767 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 3768 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 3769 } 3770 3771 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state, 3772 u32 pos, u32 size) 3773 { 3774 drm_rect_init(&crtc_state->pch_pfit.dst, 3775 pos >> 16, pos & 0xffff, 3776 size >> 16, size & 0xffff); 3777 } 3778 3779 static void skl_get_pfit_config(struct intel_crtc_state *crtc_state) 3780 { 3781 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3782 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3783 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; 3784 int id = -1; 3785 int i; 3786 3787 /* find scaler attached to this pipe */ 3788 for (i = 0; i < crtc->num_scalers; i++) { 3789 u32 ctl, pos, size; 3790 3791 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i)); 3792 if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN) 3793 continue; 3794 3795 id = i; 3796 crtc_state->pch_pfit.enabled = true; 3797 3798 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i)); 3799 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i)); 3800 3801 ilk_get_pfit_pos_size(crtc_state, pos, size); 3802 3803 scaler_state->scalers[i].in_use = true; 3804 break; 3805 } 3806 3807 scaler_state->scaler_id = id; 3808 if (id >= 0) 3809 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); 3810 else 3811 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); 3812 } 3813 3814 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state) 3815 { 3816 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3817 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3818 u32 ctl, pos, size; 3819 3820 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe)); 3821 if ((ctl & PF_ENABLE) == 0) 3822 return; 3823 3824 crtc_state->pch_pfit.enabled = true; 3825 3826 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe)); 3827 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe)); 3828 3829 ilk_get_pfit_pos_size(crtc_state, pos, size); 3830 3831 /* 3832 * We currently do not free assignements of panel fitters on 3833 * ivb/hsw (since we don't use the higher upscaling modes which 3834 * differentiates them) so just WARN about this case for now. 3835 */ 3836 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 7 && 3837 (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe)); 3838 } 3839 3840 static bool ilk_get_pipe_config(struct intel_crtc *crtc, 3841 struct intel_crtc_state *pipe_config) 3842 { 3843 struct drm_device *dev = crtc->base.dev; 3844 struct drm_i915_private *dev_priv = to_i915(dev); 3845 enum intel_display_power_domain power_domain; 3846 intel_wakeref_t wakeref; 3847 u32 tmp; 3848 bool ret; 3849 3850 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3851 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3852 if (!wakeref) 3853 return false; 3854 3855 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3856 pipe_config->shared_dpll = NULL; 3857 3858 ret = false; 3859 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); 3860 if (!(tmp & PIPECONF_ENABLE)) 3861 goto out; 3862 3863 switch (tmp & PIPECONF_BPC_MASK) { 3864 case PIPECONF_BPC_6: 3865 pipe_config->pipe_bpp = 18; 3866 break; 3867 case PIPECONF_BPC_8: 3868 pipe_config->pipe_bpp = 24; 3869 break; 3870 case PIPECONF_BPC_10: 3871 pipe_config->pipe_bpp = 30; 3872 break; 3873 case PIPECONF_BPC_12: 3874 pipe_config->pipe_bpp = 36; 3875 break; 3876 default: 3877 break; 3878 } 3879 3880 if (tmp & PIPECONF_COLOR_RANGE_SELECT) 3881 pipe_config->limited_color_range = true; 3882 3883 switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) { 3884 case PIPECONF_OUTPUT_COLORSPACE_YUV601: 3885 case PIPECONF_OUTPUT_COLORSPACE_YUV709: 3886 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3887 break; 3888 default: 3889 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3890 break; 3891 } 3892 3893 pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_ILK, tmp); 3894 3895 pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1; 3896 3897 pipe_config->msa_timing_delay = REG_FIELD_GET(PIPECONF_MSA_TIMING_DELAY_MASK, tmp); 3898 3899 pipe_config->csc_mode = intel_de_read(dev_priv, 3900 PIPE_CSC_MODE(crtc->pipe)); 3901 3902 i9xx_get_pipe_color_config(pipe_config); 3903 intel_color_get_config(pipe_config); 3904 3905 pipe_config->pixel_multiplier = 1; 3906 3907 ilk_pch_get_config(pipe_config); 3908 3909 intel_get_transcoder_timings(crtc, pipe_config); 3910 intel_get_pipe_src_size(crtc, pipe_config); 3911 3912 ilk_get_pfit_config(pipe_config); 3913 3914 ret = true; 3915 3916 out: 3917 intel_display_power_put(dev_priv, power_domain, wakeref); 3918 3919 return ret; 3920 } 3921 3922 static u8 bigjoiner_pipes(struct drm_i915_private *i915) 3923 { 3924 if (DISPLAY_VER(i915) >= 12) 3925 return BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D); 3926 else if (DISPLAY_VER(i915) >= 11) 3927 return BIT(PIPE_B) | BIT(PIPE_C); 3928 else 3929 return 0; 3930 } 3931 3932 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv, 3933 enum transcoder cpu_transcoder) 3934 { 3935 enum intel_display_power_domain power_domain; 3936 intel_wakeref_t wakeref; 3937 u32 tmp = 0; 3938 3939 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3940 3941 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3942 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3943 3944 return tmp & TRANS_DDI_FUNC_ENABLE; 3945 } 3946 3947 static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv, 3948 u8 *master_pipes, u8 *slave_pipes) 3949 { 3950 struct intel_crtc *crtc; 3951 3952 *master_pipes = 0; 3953 *slave_pipes = 0; 3954 3955 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, 3956 bigjoiner_pipes(dev_priv)) { 3957 enum intel_display_power_domain power_domain; 3958 enum pipe pipe = crtc->pipe; 3959 intel_wakeref_t wakeref; 3960 3961 power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe); 3962 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3963 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3964 3965 if (!(tmp & BIG_JOINER_ENABLE)) 3966 continue; 3967 3968 if (tmp & MASTER_BIG_JOINER_ENABLE) 3969 *master_pipes |= BIT(pipe); 3970 else 3971 *slave_pipes |= BIT(pipe); 3972 } 3973 3974 if (DISPLAY_VER(dev_priv) < 13) 3975 continue; 3976 3977 power_domain = POWER_DOMAIN_PIPE(pipe); 3978 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3979 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3980 3981 if (tmp & UNCOMPRESSED_JOINER_MASTER) 3982 *master_pipes |= BIT(pipe); 3983 if (tmp & UNCOMPRESSED_JOINER_SLAVE) 3984 *slave_pipes |= BIT(pipe); 3985 } 3986 } 3987 3988 /* Bigjoiner pipes should always be consecutive master and slave */ 3989 drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1, 3990 "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n", 3991 *master_pipes, *slave_pipes); 3992 } 3993 3994 static enum pipe get_bigjoiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3995 { 3996 if ((slave_pipes & BIT(pipe)) == 0) 3997 return pipe; 3998 3999 /* ignore everything above our pipe */ 4000 master_pipes &= ~GENMASK(7, pipe); 4001 4002 /* highest remaining bit should be our master pipe */ 4003 return fls(master_pipes) - 1; 4004 } 4005 4006 static u8 get_bigjoiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 4007 { 4008 enum pipe master_pipe, next_master_pipe; 4009 4010 master_pipe = get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes); 4011 4012 if ((master_pipes & BIT(master_pipe)) == 0) 4013 return 0; 4014 4015 /* ignore our master pipe and everything below it */ 4016 master_pipes &= ~GENMASK(master_pipe, 0); 4017 /* make sure a high bit is set for the ffs() */ 4018 master_pipes |= BIT(7); 4019 /* lowest remaining bit should be the next master pipe */ 4020 next_master_pipe = ffs(master_pipes) - 1; 4021 4022 return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe); 4023 } 4024 4025 static u8 hsw_panel_transcoders(struct drm_i915_private *i915) 4026 { 4027 u8 panel_transcoder_mask = BIT(TRANSCODER_EDP); 4028 4029 if (DISPLAY_VER(i915) >= 11) 4030 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); 4031 4032 return panel_transcoder_mask; 4033 } 4034 4035 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) 4036 { 4037 struct drm_device *dev = crtc->base.dev; 4038 struct drm_i915_private *dev_priv = to_i915(dev); 4039 u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv); 4040 enum transcoder cpu_transcoder; 4041 u8 master_pipes, slave_pipes; 4042 u8 enabled_transcoders = 0; 4043 4044 /* 4045 * XXX: Do intel_display_power_get_if_enabled before reading this (for 4046 * consistency and less surprising code; it's in always on power). 4047 */ 4048 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, 4049 panel_transcoder_mask) { 4050 enum intel_display_power_domain power_domain; 4051 intel_wakeref_t wakeref; 4052 enum pipe trans_pipe; 4053 u32 tmp = 0; 4054 4055 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 4056 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 4057 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 4058 4059 if (!(tmp & TRANS_DDI_FUNC_ENABLE)) 4060 continue; 4061 4062 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 4063 default: 4064 drm_WARN(dev, 1, 4065 "unknown pipe linked to transcoder %s\n", 4066 transcoder_name(cpu_transcoder)); 4067 fallthrough; 4068 case TRANS_DDI_EDP_INPUT_A_ONOFF: 4069 case TRANS_DDI_EDP_INPUT_A_ON: 4070 trans_pipe = PIPE_A; 4071 break; 4072 case TRANS_DDI_EDP_INPUT_B_ONOFF: 4073 trans_pipe = PIPE_B; 4074 break; 4075 case TRANS_DDI_EDP_INPUT_C_ONOFF: 4076 trans_pipe = PIPE_C; 4077 break; 4078 case TRANS_DDI_EDP_INPUT_D_ONOFF: 4079 trans_pipe = PIPE_D; 4080 break; 4081 } 4082 4083 if (trans_pipe == crtc->pipe) 4084 enabled_transcoders |= BIT(cpu_transcoder); 4085 } 4086 4087 /* single pipe or bigjoiner master */ 4088 cpu_transcoder = (enum transcoder) crtc->pipe; 4089 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 4090 enabled_transcoders |= BIT(cpu_transcoder); 4091 4092 /* bigjoiner slave -> consider the master pipe's transcoder as well */ 4093 enabled_bigjoiner_pipes(dev_priv, &master_pipes, &slave_pipes); 4094 if (slave_pipes & BIT(crtc->pipe)) { 4095 cpu_transcoder = (enum transcoder) 4096 get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes); 4097 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 4098 enabled_transcoders |= BIT(cpu_transcoder); 4099 } 4100 4101 return enabled_transcoders; 4102 } 4103 4104 static bool has_edp_transcoders(u8 enabled_transcoders) 4105 { 4106 return enabled_transcoders & BIT(TRANSCODER_EDP); 4107 } 4108 4109 static bool has_dsi_transcoders(u8 enabled_transcoders) 4110 { 4111 return enabled_transcoders & (BIT(TRANSCODER_DSI_0) | 4112 BIT(TRANSCODER_DSI_1)); 4113 } 4114 4115 static bool has_pipe_transcoders(u8 enabled_transcoders) 4116 { 4117 return enabled_transcoders & ~(BIT(TRANSCODER_EDP) | 4118 BIT(TRANSCODER_DSI_0) | 4119 BIT(TRANSCODER_DSI_1)); 4120 } 4121 4122 static void assert_enabled_transcoders(struct drm_i915_private *i915, 4123 u8 enabled_transcoders) 4124 { 4125 /* Only one type of transcoder please */ 4126 drm_WARN_ON(&i915->drm, 4127 has_edp_transcoders(enabled_transcoders) + 4128 has_dsi_transcoders(enabled_transcoders) + 4129 has_pipe_transcoders(enabled_transcoders) > 1); 4130 4131 /* Only DSI transcoders can be ganged */ 4132 drm_WARN_ON(&i915->drm, 4133 !has_dsi_transcoders(enabled_transcoders) && 4134 !is_power_of_2(enabled_transcoders)); 4135 } 4136 4137 static bool hsw_get_transcoder_state(struct intel_crtc *crtc, 4138 struct intel_crtc_state *pipe_config, 4139 struct intel_display_power_domain_set *power_domain_set) 4140 { 4141 struct drm_device *dev = crtc->base.dev; 4142 struct drm_i915_private *dev_priv = to_i915(dev); 4143 unsigned long enabled_transcoders; 4144 u32 tmp; 4145 4146 enabled_transcoders = hsw_enabled_transcoders(crtc); 4147 if (!enabled_transcoders) 4148 return false; 4149 4150 assert_enabled_transcoders(dev_priv, enabled_transcoders); 4151 4152 /* 4153 * With the exception of DSI we should only ever have 4154 * a single enabled transcoder. With DSI let's just 4155 * pick the first one. 4156 */ 4157 pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1; 4158 4159 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 4160 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) 4161 return false; 4162 4163 if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) { 4164 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); 4165 4166 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF) 4167 pipe_config->pch_pfit.force_thru = true; 4168 } 4169 4170 tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder)); 4171 4172 return tmp & PIPECONF_ENABLE; 4173 } 4174 4175 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, 4176 struct intel_crtc_state *pipe_config, 4177 struct intel_display_power_domain_set *power_domain_set) 4178 { 4179 struct drm_device *dev = crtc->base.dev; 4180 struct drm_i915_private *dev_priv = to_i915(dev); 4181 enum transcoder cpu_transcoder; 4182 enum port port; 4183 u32 tmp; 4184 4185 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { 4186 if (port == PORT_A) 4187 cpu_transcoder = TRANSCODER_DSI_A; 4188 else 4189 cpu_transcoder = TRANSCODER_DSI_C; 4190 4191 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 4192 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) 4193 continue; 4194 4195 /* 4196 * The PLL needs to be enabled with a valid divider 4197 * configuration, otherwise accessing DSI registers will hang 4198 * the machine. See BSpec North Display Engine 4199 * registers/MIPI[BXT]. We can break out here early, since we 4200 * need the same DSI PLL to be enabled for both DSI ports. 4201 */ 4202 if (!bxt_dsi_pll_is_enabled(dev_priv)) 4203 break; 4204 4205 /* XXX: this works for video mode only */ 4206 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); 4207 if (!(tmp & DPI_ENABLE)) 4208 continue; 4209 4210 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 4211 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) 4212 continue; 4213 4214 pipe_config->cpu_transcoder = cpu_transcoder; 4215 break; 4216 } 4217 4218 return transcoder_is_dsi(pipe_config->cpu_transcoder); 4219 } 4220 4221 static void intel_bigjoiner_get_config(struct intel_crtc_state *crtc_state) 4222 { 4223 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4224 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4225 u8 master_pipes, slave_pipes; 4226 enum pipe pipe = crtc->pipe; 4227 4228 enabled_bigjoiner_pipes(i915, &master_pipes, &slave_pipes); 4229 4230 if (((master_pipes | slave_pipes) & BIT(pipe)) == 0) 4231 return; 4232 4233 crtc_state->bigjoiner_pipes = 4234 BIT(get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes)) | 4235 get_bigjoiner_slave_pipes(pipe, master_pipes, slave_pipes); 4236 } 4237 4238 static bool hsw_get_pipe_config(struct intel_crtc *crtc, 4239 struct intel_crtc_state *pipe_config) 4240 { 4241 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4242 struct intel_display_power_domain_set power_domain_set = { }; 4243 bool active; 4244 u32 tmp; 4245 4246 if (!intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set, 4247 POWER_DOMAIN_PIPE(crtc->pipe))) 4248 return false; 4249 4250 pipe_config->shared_dpll = NULL; 4251 4252 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_set); 4253 4254 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 4255 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_set)) { 4256 drm_WARN_ON(&dev_priv->drm, active); 4257 active = true; 4258 } 4259 4260 if (!active) 4261 goto out; 4262 4263 intel_dsc_get_config(pipe_config); 4264 intel_bigjoiner_get_config(pipe_config); 4265 4266 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || 4267 DISPLAY_VER(dev_priv) >= 11) 4268 intel_get_transcoder_timings(crtc, pipe_config); 4269 4270 if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder)) 4271 intel_vrr_get_config(crtc, pipe_config); 4272 4273 intel_get_pipe_src_size(crtc, pipe_config); 4274 4275 if (IS_HASWELL(dev_priv)) { 4276 u32 tmp = intel_de_read(dev_priv, 4277 PIPECONF(pipe_config->cpu_transcoder)); 4278 4279 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW) 4280 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 4281 else 4282 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 4283 } else { 4284 pipe_config->output_format = 4285 bdw_get_pipemisc_output_format(crtc); 4286 } 4287 4288 pipe_config->gamma_mode = intel_de_read(dev_priv, 4289 GAMMA_MODE(crtc->pipe)); 4290 4291 pipe_config->csc_mode = intel_de_read(dev_priv, 4292 PIPE_CSC_MODE(crtc->pipe)); 4293 4294 if (DISPLAY_VER(dev_priv) >= 9) { 4295 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe)); 4296 4297 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE) 4298 pipe_config->gamma_enable = true; 4299 4300 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE) 4301 pipe_config->csc_enable = true; 4302 } else { 4303 i9xx_get_pipe_color_config(pipe_config); 4304 } 4305 4306 intel_color_get_config(pipe_config); 4307 4308 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe)); 4309 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); 4310 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 4311 pipe_config->ips_linetime = 4312 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); 4313 4314 if (intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set, 4315 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) { 4316 if (DISPLAY_VER(dev_priv) >= 9) 4317 skl_get_pfit_config(pipe_config); 4318 else 4319 ilk_get_pfit_config(pipe_config); 4320 } 4321 4322 hsw_ips_get_config(pipe_config); 4323 4324 if (pipe_config->cpu_transcoder != TRANSCODER_EDP && 4325 !transcoder_is_dsi(pipe_config->cpu_transcoder)) { 4326 pipe_config->pixel_multiplier = 4327 intel_de_read(dev_priv, 4328 PIPE_MULT(pipe_config->cpu_transcoder)) + 1; 4329 } else { 4330 pipe_config->pixel_multiplier = 1; 4331 } 4332 4333 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { 4334 tmp = intel_de_read(dev_priv, CHICKEN_TRANS(pipe_config->cpu_transcoder)); 4335 4336 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1; 4337 } else { 4338 /* no idea if this is correct */ 4339 pipe_config->framestart_delay = 1; 4340 } 4341 4342 out: 4343 intel_display_power_put_all_in_set(dev_priv, &power_domain_set); 4344 4345 return active; 4346 } 4347 4348 static bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state) 4349 { 4350 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4351 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4352 4353 if (!i915->display->get_pipe_config(crtc, crtc_state)) 4354 return false; 4355 4356 crtc_state->hw.active = true; 4357 4358 intel_crtc_readout_derived_state(crtc_state); 4359 4360 return true; 4361 } 4362 4363 /* VESA 640x480x72Hz mode to set on the pipe */ 4364 static const struct drm_display_mode load_detect_mode = { 4365 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, 4366 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 4367 }; 4368 4369 static int intel_modeset_disable_planes(struct drm_atomic_state *state, 4370 struct drm_crtc *crtc) 4371 { 4372 struct drm_plane *plane; 4373 struct drm_plane_state *plane_state; 4374 int ret, i; 4375 4376 ret = drm_atomic_add_affected_planes(state, crtc); 4377 if (ret) 4378 return ret; 4379 4380 for_each_new_plane_in_state(state, plane, plane_state, i) { 4381 if (plane_state->crtc != crtc) 4382 continue; 4383 4384 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL); 4385 if (ret) 4386 return ret; 4387 4388 drm_atomic_set_fb_for_plane(plane_state, NULL); 4389 } 4390 4391 return 0; 4392 } 4393 4394 int intel_get_load_detect_pipe(struct drm_connector *connector, 4395 struct intel_load_detect_pipe *old, 4396 struct drm_modeset_acquire_ctx *ctx) 4397 { 4398 struct intel_encoder *encoder = 4399 intel_attached_encoder(to_intel_connector(connector)); 4400 struct intel_crtc *possible_crtc; 4401 struct intel_crtc *crtc = NULL; 4402 struct drm_device *dev = encoder->base.dev; 4403 struct drm_i915_private *dev_priv = to_i915(dev); 4404 struct drm_mode_config *config = &dev->mode_config; 4405 struct drm_atomic_state *state = NULL, *restore_state = NULL; 4406 struct drm_connector_state *connector_state; 4407 struct intel_crtc_state *crtc_state; 4408 int ret; 4409 4410 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 4411 connector->base.id, connector->name, 4412 encoder->base.base.id, encoder->base.name); 4413 4414 old->restore_state = NULL; 4415 4416 drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex)); 4417 4418 /* 4419 * Algorithm gets a little messy: 4420 * 4421 * - if the connector already has an assigned crtc, use it (but make 4422 * sure it's on first) 4423 * 4424 * - try to find the first unused crtc that can drive this connector, 4425 * and use that if we find one 4426 */ 4427 4428 /* See if we already have a CRTC for this connector */ 4429 if (connector->state->crtc) { 4430 crtc = to_intel_crtc(connector->state->crtc); 4431 4432 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4433 if (ret) 4434 goto fail; 4435 4436 /* Make sure the crtc and connector are running */ 4437 goto found; 4438 } 4439 4440 /* Find an unused one (if possible) */ 4441 for_each_intel_crtc(dev, possible_crtc) { 4442 if (!(encoder->base.possible_crtcs & 4443 drm_crtc_mask(&possible_crtc->base))) 4444 continue; 4445 4446 ret = drm_modeset_lock(&possible_crtc->base.mutex, ctx); 4447 if (ret) 4448 goto fail; 4449 4450 if (possible_crtc->base.state->enable) { 4451 drm_modeset_unlock(&possible_crtc->base.mutex); 4452 continue; 4453 } 4454 4455 crtc = possible_crtc; 4456 break; 4457 } 4458 4459 /* 4460 * If we didn't find an unused CRTC, don't use any. 4461 */ 4462 if (!crtc) { 4463 drm_dbg_kms(&dev_priv->drm, 4464 "no pipe available for load-detect\n"); 4465 ret = -ENODEV; 4466 goto fail; 4467 } 4468 4469 found: 4470 state = drm_atomic_state_alloc(dev); 4471 restore_state = drm_atomic_state_alloc(dev); 4472 if (!state || !restore_state) { 4473 ret = -ENOMEM; 4474 goto fail; 4475 } 4476 4477 state->acquire_ctx = ctx; 4478 restore_state->acquire_ctx = ctx; 4479 4480 connector_state = drm_atomic_get_connector_state(state, connector); 4481 if (IS_ERR(connector_state)) { 4482 ret = PTR_ERR(connector_state); 4483 goto fail; 4484 } 4485 4486 ret = drm_atomic_set_crtc_for_connector(connector_state, &crtc->base); 4487 if (ret) 4488 goto fail; 4489 4490 crtc_state = intel_atomic_get_crtc_state(state, crtc); 4491 if (IS_ERR(crtc_state)) { 4492 ret = PTR_ERR(crtc_state); 4493 goto fail; 4494 } 4495 4496 crtc_state->uapi.active = true; 4497 4498 ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi, 4499 &load_detect_mode); 4500 if (ret) 4501 goto fail; 4502 4503 ret = intel_modeset_disable_planes(state, &crtc->base); 4504 if (ret) 4505 goto fail; 4506 4507 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); 4508 if (!ret) 4509 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, &crtc->base)); 4510 if (!ret) 4511 ret = drm_atomic_add_affected_planes(restore_state, &crtc->base); 4512 if (ret) { 4513 drm_dbg_kms(&dev_priv->drm, 4514 "Failed to create a copy of old state to restore: %i\n", 4515 ret); 4516 goto fail; 4517 } 4518 4519 ret = drm_atomic_commit(state); 4520 if (ret) { 4521 drm_dbg_kms(&dev_priv->drm, 4522 "failed to set mode on load-detect pipe\n"); 4523 goto fail; 4524 } 4525 4526 old->restore_state = restore_state; 4527 drm_atomic_state_put(state); 4528 4529 /* let the connector get through one full cycle before testing */ 4530 intel_crtc_wait_for_next_vblank(crtc); 4531 4532 return true; 4533 4534 fail: 4535 if (state) { 4536 drm_atomic_state_put(state); 4537 state = NULL; 4538 } 4539 if (restore_state) { 4540 drm_atomic_state_put(restore_state); 4541 restore_state = NULL; 4542 } 4543 4544 if (ret == -EDEADLK) 4545 return ret; 4546 4547 return false; 4548 } 4549 4550 void intel_release_load_detect_pipe(struct drm_connector *connector, 4551 struct intel_load_detect_pipe *old, 4552 struct drm_modeset_acquire_ctx *ctx) 4553 { 4554 struct intel_encoder *intel_encoder = 4555 intel_attached_encoder(to_intel_connector(connector)); 4556 struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev); 4557 struct drm_encoder *encoder = &intel_encoder->base; 4558 struct drm_atomic_state *state = old->restore_state; 4559 int ret; 4560 4561 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 4562 connector->base.id, connector->name, 4563 encoder->base.id, encoder->name); 4564 4565 if (!state) 4566 return; 4567 4568 ret = drm_atomic_helper_commit_duplicated_state(state, ctx); 4569 if (ret) 4570 drm_dbg_kms(&i915->drm, 4571 "Couldn't release load detect pipe: %i\n", ret); 4572 drm_atomic_state_put(state); 4573 } 4574 4575 static int i9xx_pll_refclk(struct drm_device *dev, 4576 const struct intel_crtc_state *pipe_config) 4577 { 4578 struct drm_i915_private *dev_priv = to_i915(dev); 4579 u32 dpll = pipe_config->dpll_hw_state.dpll; 4580 4581 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) 4582 return dev_priv->vbt.lvds_ssc_freq; 4583 else if (HAS_PCH_SPLIT(dev_priv)) 4584 return 120000; 4585 else if (DISPLAY_VER(dev_priv) != 2) 4586 return 96000; 4587 else 4588 return 48000; 4589 } 4590 4591 /* Returns the clock of the currently programmed mode of the given pipe. */ 4592 void i9xx_crtc_clock_get(struct intel_crtc *crtc, 4593 struct intel_crtc_state *pipe_config) 4594 { 4595 struct drm_device *dev = crtc->base.dev; 4596 struct drm_i915_private *dev_priv = to_i915(dev); 4597 u32 dpll = pipe_config->dpll_hw_state.dpll; 4598 u32 fp; 4599 struct dpll clock; 4600 int port_clock; 4601 int refclk = i9xx_pll_refclk(dev, pipe_config); 4602 4603 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 4604 fp = pipe_config->dpll_hw_state.fp0; 4605 else 4606 fp = pipe_config->dpll_hw_state.fp1; 4607 4608 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 4609 if (IS_PINEVIEW(dev_priv)) { 4610 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; 4611 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; 4612 } else { 4613 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 4614 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 4615 } 4616 4617 if (DISPLAY_VER(dev_priv) != 2) { 4618 if (IS_PINEVIEW(dev_priv)) 4619 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> 4620 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); 4621 else 4622 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> 4623 DPLL_FPA01_P1_POST_DIV_SHIFT); 4624 4625 switch (dpll & DPLL_MODE_MASK) { 4626 case DPLLB_MODE_DAC_SERIAL: 4627 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 4628 5 : 10; 4629 break; 4630 case DPLLB_MODE_LVDS: 4631 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 4632 7 : 14; 4633 break; 4634 default: 4635 drm_dbg_kms(&dev_priv->drm, 4636 "Unknown DPLL mode %08x in programmed " 4637 "mode\n", (int)(dpll & DPLL_MODE_MASK)); 4638 return; 4639 } 4640 4641 if (IS_PINEVIEW(dev_priv)) 4642 port_clock = pnv_calc_dpll_params(refclk, &clock); 4643 else 4644 port_clock = i9xx_calc_dpll_params(refclk, &clock); 4645 } else { 4646 enum pipe lvds_pipe; 4647 4648 if (IS_I85X(dev_priv) && 4649 intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) && 4650 lvds_pipe == crtc->pipe) { 4651 u32 lvds = intel_de_read(dev_priv, LVDS); 4652 4653 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 4654 DPLL_FPA01_P1_POST_DIV_SHIFT); 4655 4656 if (lvds & LVDS_CLKB_POWER_UP) 4657 clock.p2 = 7; 4658 else 4659 clock.p2 = 14; 4660 } else { 4661 if (dpll & PLL_P1_DIVIDE_BY_TWO) 4662 clock.p1 = 2; 4663 else { 4664 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 4665 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 4666 } 4667 if (dpll & PLL_P2_DIVIDE_BY_4) 4668 clock.p2 = 4; 4669 else 4670 clock.p2 = 2; 4671 } 4672 4673 port_clock = i9xx_calc_dpll_params(refclk, &clock); 4674 } 4675 4676 /* 4677 * This value includes pixel_multiplier. We will use 4678 * port_clock to compute adjusted_mode.crtc_clock in the 4679 * encoder's get_config() function. 4680 */ 4681 pipe_config->port_clock = port_clock; 4682 } 4683 4684 int intel_dotclock_calculate(int link_freq, 4685 const struct intel_link_m_n *m_n) 4686 { 4687 /* 4688 * The calculation for the data clock is: 4689 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp 4690 * But we want to avoid losing precison if possible, so: 4691 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) 4692 * 4693 * and the link clock is simpler: 4694 * link_clock = (m * link_clock) / n 4695 */ 4696 4697 if (!m_n->link_n) 4698 return 0; 4699 4700 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n); 4701 } 4702 4703 /* Returns the currently programmed mode of the given encoder. */ 4704 struct drm_display_mode * 4705 intel_encoder_current_mode(struct intel_encoder *encoder) 4706 { 4707 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4708 struct intel_crtc_state *crtc_state; 4709 struct drm_display_mode *mode; 4710 struct intel_crtc *crtc; 4711 enum pipe pipe; 4712 4713 if (!encoder->get_hw_state(encoder, &pipe)) 4714 return NULL; 4715 4716 crtc = intel_crtc_for_pipe(dev_priv, pipe); 4717 4718 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 4719 if (!mode) 4720 return NULL; 4721 4722 crtc_state = intel_crtc_state_alloc(crtc); 4723 if (!crtc_state) { 4724 kfree(mode); 4725 return NULL; 4726 } 4727 4728 if (!intel_crtc_get_pipe_config(crtc_state)) { 4729 kfree(crtc_state); 4730 kfree(mode); 4731 return NULL; 4732 } 4733 4734 intel_encoder_get_config(encoder, crtc_state); 4735 4736 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode); 4737 4738 kfree(crtc_state); 4739 4740 return mode; 4741 } 4742 4743 static bool encoders_cloneable(const struct intel_encoder *a, 4744 const struct intel_encoder *b) 4745 { 4746 /* masks could be asymmetric, so check both ways */ 4747 return a == b || (a->cloneable & (1 << b->type) && 4748 b->cloneable & (1 << a->type)); 4749 } 4750 4751 static bool check_single_encoder_cloning(struct intel_atomic_state *state, 4752 struct intel_crtc *crtc, 4753 struct intel_encoder *encoder) 4754 { 4755 struct intel_encoder *source_encoder; 4756 struct drm_connector *connector; 4757 struct drm_connector_state *connector_state; 4758 int i; 4759 4760 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4761 if (connector_state->crtc != &crtc->base) 4762 continue; 4763 4764 source_encoder = 4765 to_intel_encoder(connector_state->best_encoder); 4766 if (!encoders_cloneable(encoder, source_encoder)) 4767 return false; 4768 } 4769 4770 return true; 4771 } 4772 4773 static int icl_add_linked_planes(struct intel_atomic_state *state) 4774 { 4775 struct intel_plane *plane, *linked; 4776 struct intel_plane_state *plane_state, *linked_plane_state; 4777 int i; 4778 4779 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4780 linked = plane_state->planar_linked_plane; 4781 4782 if (!linked) 4783 continue; 4784 4785 linked_plane_state = intel_atomic_get_plane_state(state, linked); 4786 if (IS_ERR(linked_plane_state)) 4787 return PTR_ERR(linked_plane_state); 4788 4789 drm_WARN_ON(state->base.dev, 4790 linked_plane_state->planar_linked_plane != plane); 4791 drm_WARN_ON(state->base.dev, 4792 linked_plane_state->planar_slave == plane_state->planar_slave); 4793 } 4794 4795 return 0; 4796 } 4797 4798 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state) 4799 { 4800 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4801 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4802 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 4803 struct intel_plane *plane, *linked; 4804 struct intel_plane_state *plane_state; 4805 int i; 4806 4807 if (DISPLAY_VER(dev_priv) < 11) 4808 return 0; 4809 4810 /* 4811 * Destroy all old plane links and make the slave plane invisible 4812 * in the crtc_state->active_planes mask. 4813 */ 4814 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4815 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane) 4816 continue; 4817 4818 plane_state->planar_linked_plane = NULL; 4819 if (plane_state->planar_slave && !plane_state->uapi.visible) { 4820 crtc_state->enabled_planes &= ~BIT(plane->id); 4821 crtc_state->active_planes &= ~BIT(plane->id); 4822 crtc_state->update_planes |= BIT(plane->id); 4823 crtc_state->data_rate[plane->id] = 0; 4824 crtc_state->rel_data_rate[plane->id] = 0; 4825 } 4826 4827 plane_state->planar_slave = false; 4828 } 4829 4830 if (!crtc_state->nv12_planes) 4831 return 0; 4832 4833 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4834 struct intel_plane_state *linked_state = NULL; 4835 4836 if (plane->pipe != crtc->pipe || 4837 !(crtc_state->nv12_planes & BIT(plane->id))) 4838 continue; 4839 4840 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) { 4841 if (!icl_is_nv12_y_plane(dev_priv, linked->id)) 4842 continue; 4843 4844 if (crtc_state->active_planes & BIT(linked->id)) 4845 continue; 4846 4847 linked_state = intel_atomic_get_plane_state(state, linked); 4848 if (IS_ERR(linked_state)) 4849 return PTR_ERR(linked_state); 4850 4851 break; 4852 } 4853 4854 if (!linked_state) { 4855 drm_dbg_kms(&dev_priv->drm, 4856 "Need %d free Y planes for planar YUV\n", 4857 hweight8(crtc_state->nv12_planes)); 4858 4859 return -EINVAL; 4860 } 4861 4862 plane_state->planar_linked_plane = linked; 4863 4864 linked_state->planar_slave = true; 4865 linked_state->planar_linked_plane = plane; 4866 crtc_state->enabled_planes |= BIT(linked->id); 4867 crtc_state->active_planes |= BIT(linked->id); 4868 crtc_state->update_planes |= BIT(linked->id); 4869 crtc_state->data_rate[linked->id] = 4870 crtc_state->data_rate_y[plane->id]; 4871 crtc_state->rel_data_rate[linked->id] = 4872 crtc_state->rel_data_rate_y[plane->id]; 4873 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n", 4874 linked->base.name, plane->base.name); 4875 4876 /* Copy parameters to slave plane */ 4877 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE; 4878 linked_state->color_ctl = plane_state->color_ctl; 4879 linked_state->view = plane_state->view; 4880 linked_state->decrypt = plane_state->decrypt; 4881 4882 intel_plane_copy_hw_state(linked_state, plane_state); 4883 linked_state->uapi.src = plane_state->uapi.src; 4884 linked_state->uapi.dst = plane_state->uapi.dst; 4885 4886 if (icl_is_hdr_plane(dev_priv, plane->id)) { 4887 if (linked->id == PLANE_SPRITE5) 4888 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL; 4889 else if (linked->id == PLANE_SPRITE4) 4890 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL; 4891 else if (linked->id == PLANE_SPRITE3) 4892 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL; 4893 else if (linked->id == PLANE_SPRITE2) 4894 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL; 4895 else 4896 MISSING_CASE(linked->id); 4897 } 4898 } 4899 4900 return 0; 4901 } 4902 4903 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state) 4904 { 4905 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 4906 struct intel_atomic_state *state = 4907 to_intel_atomic_state(new_crtc_state->uapi.state); 4908 const struct intel_crtc_state *old_crtc_state = 4909 intel_atomic_get_old_crtc_state(state, crtc); 4910 4911 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes; 4912 } 4913 4914 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) 4915 { 4916 const struct drm_display_mode *pipe_mode = 4917 &crtc_state->hw.pipe_mode; 4918 int linetime_wm; 4919 4920 if (!crtc_state->hw.enable) 4921 return 0; 4922 4923 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4924 pipe_mode->crtc_clock); 4925 4926 return min(linetime_wm, 0x1ff); 4927 } 4928 4929 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, 4930 const struct intel_cdclk_state *cdclk_state) 4931 { 4932 const struct drm_display_mode *pipe_mode = 4933 &crtc_state->hw.pipe_mode; 4934 int linetime_wm; 4935 4936 if (!crtc_state->hw.enable) 4937 return 0; 4938 4939 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4940 cdclk_state->logical.cdclk); 4941 4942 return min(linetime_wm, 0x1ff); 4943 } 4944 4945 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) 4946 { 4947 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4948 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4949 const struct drm_display_mode *pipe_mode = 4950 &crtc_state->hw.pipe_mode; 4951 int linetime_wm; 4952 4953 if (!crtc_state->hw.enable) 4954 return 0; 4955 4956 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8, 4957 crtc_state->pixel_rate); 4958 4959 /* Display WA #1135: BXT:ALL GLK:ALL */ 4960 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 4961 dev_priv->ipc_enabled) 4962 linetime_wm /= 2; 4963 4964 return min(linetime_wm, 0x1ff); 4965 } 4966 4967 static int hsw_compute_linetime_wm(struct intel_atomic_state *state, 4968 struct intel_crtc *crtc) 4969 { 4970 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4971 struct intel_crtc_state *crtc_state = 4972 intel_atomic_get_new_crtc_state(state, crtc); 4973 const struct intel_cdclk_state *cdclk_state; 4974 4975 if (DISPLAY_VER(dev_priv) >= 9) 4976 crtc_state->linetime = skl_linetime_wm(crtc_state); 4977 else 4978 crtc_state->linetime = hsw_linetime_wm(crtc_state); 4979 4980 if (!hsw_crtc_supports_ips(crtc)) 4981 return 0; 4982 4983 cdclk_state = intel_atomic_get_cdclk_state(state); 4984 if (IS_ERR(cdclk_state)) 4985 return PTR_ERR(cdclk_state); 4986 4987 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state, 4988 cdclk_state); 4989 4990 return 0; 4991 } 4992 4993 static int intel_crtc_atomic_check(struct intel_atomic_state *state, 4994 struct intel_crtc *crtc) 4995 { 4996 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4997 struct intel_crtc_state *crtc_state = 4998 intel_atomic_get_new_crtc_state(state, crtc); 4999 bool mode_changed = intel_crtc_needs_modeset(crtc_state); 5000 int ret; 5001 5002 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) && 5003 mode_changed && !crtc_state->hw.active) 5004 crtc_state->update_wm_post = true; 5005 5006 if (mode_changed && crtc_state->hw.enable && 5007 !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) { 5008 ret = intel_dpll_crtc_compute_clock(crtc_state); 5009 if (ret) 5010 return ret; 5011 } 5012 5013 /* 5014 * May need to update pipe gamma enable bits 5015 * when C8 planes are getting enabled/disabled. 5016 */ 5017 if (c8_planes_changed(crtc_state)) 5018 crtc_state->uapi.color_mgmt_changed = true; 5019 5020 if (mode_changed || crtc_state->update_pipe || 5021 crtc_state->uapi.color_mgmt_changed) { 5022 ret = intel_color_check(crtc_state); 5023 if (ret) 5024 return ret; 5025 } 5026 5027 ret = intel_compute_pipe_wm(state, crtc); 5028 if (ret) { 5029 drm_dbg_kms(&dev_priv->drm, 5030 "Target pipe watermarks are invalid\n"); 5031 return ret; 5032 } 5033 5034 /* 5035 * Calculate 'intermediate' watermarks that satisfy both the 5036 * old state and the new state. We can program these 5037 * immediately. 5038 */ 5039 ret = intel_compute_intermediate_wm(state, crtc); 5040 if (ret) { 5041 drm_dbg_kms(&dev_priv->drm, 5042 "No valid intermediate pipe watermarks are possible\n"); 5043 return ret; 5044 } 5045 5046 if (DISPLAY_VER(dev_priv) >= 9) { 5047 if (mode_changed || crtc_state->update_pipe) { 5048 ret = skl_update_scaler_crtc(crtc_state); 5049 if (ret) 5050 return ret; 5051 } 5052 5053 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state); 5054 if (ret) 5055 return ret; 5056 } 5057 5058 if (HAS_IPS(dev_priv)) { 5059 ret = hsw_ips_compute_config(state, crtc); 5060 if (ret) 5061 return ret; 5062 } 5063 5064 if (DISPLAY_VER(dev_priv) >= 9 || 5065 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 5066 ret = hsw_compute_linetime_wm(state, crtc); 5067 if (ret) 5068 return ret; 5069 5070 } 5071 5072 ret = intel_psr2_sel_fetch_update(state, crtc); 5073 if (ret) 5074 return ret; 5075 5076 return 0; 5077 } 5078 5079 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) 5080 { 5081 struct intel_connector *connector; 5082 struct drm_connector_list_iter conn_iter; 5083 5084 drm_connector_list_iter_begin(dev, &conn_iter); 5085 for_each_intel_connector_iter(connector, &conn_iter) { 5086 struct drm_connector_state *conn_state = connector->base.state; 5087 struct intel_encoder *encoder = 5088 to_intel_encoder(connector->base.encoder); 5089 5090 if (conn_state->crtc) 5091 drm_connector_put(&connector->base); 5092 5093 if (encoder) { 5094 struct intel_crtc *crtc = 5095 to_intel_crtc(encoder->base.crtc); 5096 const struct intel_crtc_state *crtc_state = 5097 to_intel_crtc_state(crtc->base.state); 5098 5099 conn_state->best_encoder = &encoder->base; 5100 conn_state->crtc = &crtc->base; 5101 conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3; 5102 5103 drm_connector_get(&connector->base); 5104 } else { 5105 conn_state->best_encoder = NULL; 5106 conn_state->crtc = NULL; 5107 } 5108 } 5109 drm_connector_list_iter_end(&conn_iter); 5110 } 5111 5112 static int 5113 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state, 5114 struct intel_crtc_state *pipe_config) 5115 { 5116 struct drm_connector *connector = conn_state->connector; 5117 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); 5118 const struct drm_display_info *info = &connector->display_info; 5119 int bpp; 5120 5121 switch (conn_state->max_bpc) { 5122 case 6 ... 7: 5123 bpp = 6 * 3; 5124 break; 5125 case 8 ... 9: 5126 bpp = 8 * 3; 5127 break; 5128 case 10 ... 11: 5129 bpp = 10 * 3; 5130 break; 5131 case 12 ... 16: 5132 bpp = 12 * 3; 5133 break; 5134 default: 5135 MISSING_CASE(conn_state->max_bpc); 5136 return -EINVAL; 5137 } 5138 5139 if (bpp < pipe_config->pipe_bpp) { 5140 drm_dbg_kms(&i915->drm, 5141 "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of " 5142 "EDID bpp %d, requested bpp %d, max platform bpp %d\n", 5143 connector->base.id, connector->name, 5144 bpp, 3 * info->bpc, 5145 3 * conn_state->max_requested_bpc, 5146 pipe_config->pipe_bpp); 5147 5148 pipe_config->pipe_bpp = bpp; 5149 } 5150 5151 return 0; 5152 } 5153 5154 static int 5155 compute_baseline_pipe_bpp(struct intel_crtc *crtc, 5156 struct intel_crtc_state *pipe_config) 5157 { 5158 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5159 struct drm_atomic_state *state = pipe_config->uapi.state; 5160 struct drm_connector *connector; 5161 struct drm_connector_state *connector_state; 5162 int bpp, i; 5163 5164 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 5165 IS_CHERRYVIEW(dev_priv))) 5166 bpp = 10*3; 5167 else if (DISPLAY_VER(dev_priv) >= 5) 5168 bpp = 12*3; 5169 else 5170 bpp = 8*3; 5171 5172 pipe_config->pipe_bpp = bpp; 5173 5174 /* Clamp display bpp to connector max bpp */ 5175 for_each_new_connector_in_state(state, connector, connector_state, i) { 5176 int ret; 5177 5178 if (connector_state->crtc != &crtc->base) 5179 continue; 5180 5181 ret = compute_sink_pipe_bpp(connector_state, pipe_config); 5182 if (ret) 5183 return ret; 5184 } 5185 5186 return 0; 5187 } 5188 5189 static void intel_dump_crtc_timings(struct drm_i915_private *i915, 5190 const struct drm_display_mode *mode) 5191 { 5192 drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, " 5193 "type: 0x%x flags: 0x%x\n", 5194 mode->crtc_clock, 5195 mode->crtc_hdisplay, mode->crtc_hsync_start, 5196 mode->crtc_hsync_end, mode->crtc_htotal, 5197 mode->crtc_vdisplay, mode->crtc_vsync_start, 5198 mode->crtc_vsync_end, mode->crtc_vtotal, 5199 mode->type, mode->flags); 5200 } 5201 5202 static void 5203 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config, 5204 const char *id, unsigned int lane_count, 5205 const struct intel_link_m_n *m_n) 5206 { 5207 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); 5208 5209 drm_dbg_kms(&i915->drm, 5210 "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n", 5211 id, lane_count, 5212 m_n->data_m, m_n->data_n, 5213 m_n->link_m, m_n->link_n, m_n->tu); 5214 } 5215 5216 static void 5217 intel_dump_infoframe(struct drm_i915_private *dev_priv, 5218 const union hdmi_infoframe *frame) 5219 { 5220 if (!drm_debug_enabled(DRM_UT_KMS)) 5221 return; 5222 5223 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame); 5224 } 5225 5226 static void 5227 intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv, 5228 const struct drm_dp_vsc_sdp *vsc) 5229 { 5230 if (!drm_debug_enabled(DRM_UT_KMS)) 5231 return; 5232 5233 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc); 5234 } 5235 5236 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x 5237 5238 static const char * const output_type_str[] = { 5239 OUTPUT_TYPE(UNUSED), 5240 OUTPUT_TYPE(ANALOG), 5241 OUTPUT_TYPE(DVO), 5242 OUTPUT_TYPE(SDVO), 5243 OUTPUT_TYPE(LVDS), 5244 OUTPUT_TYPE(TVOUT), 5245 OUTPUT_TYPE(HDMI), 5246 OUTPUT_TYPE(DP), 5247 OUTPUT_TYPE(EDP), 5248 OUTPUT_TYPE(DSI), 5249 OUTPUT_TYPE(DDI), 5250 OUTPUT_TYPE(DP_MST), 5251 }; 5252 5253 #undef OUTPUT_TYPE 5254 5255 static void snprintf_output_types(char *buf, size_t len, 5256 unsigned int output_types) 5257 { 5258 char *str = buf; 5259 int i; 5260 5261 str[0] = '\0'; 5262 5263 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) { 5264 int r; 5265 5266 if ((output_types & BIT(i)) == 0) 5267 continue; 5268 5269 r = snprintf(str, len, "%s%s", 5270 str != buf ? "," : "", output_type_str[i]); 5271 if (r >= len) 5272 break; 5273 str += r; 5274 len -= r; 5275 5276 output_types &= ~BIT(i); 5277 } 5278 5279 WARN_ON_ONCE(output_types != 0); 5280 } 5281 5282 static const char * const output_format_str[] = { 5283 [INTEL_OUTPUT_FORMAT_RGB] = "RGB", 5284 [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0", 5285 [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4", 5286 }; 5287 5288 static const char *output_formats(enum intel_output_format format) 5289 { 5290 if (format >= ARRAY_SIZE(output_format_str)) 5291 return "invalid"; 5292 return output_format_str[format]; 5293 } 5294 5295 static void intel_dump_plane_state(const struct intel_plane_state *plane_state) 5296 { 5297 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 5298 struct drm_i915_private *i915 = to_i915(plane->base.dev); 5299 const struct drm_framebuffer *fb = plane_state->hw.fb; 5300 5301 if (!fb) { 5302 drm_dbg_kms(&i915->drm, 5303 "[PLANE:%d:%s] fb: [NOFB], visible: %s\n", 5304 plane->base.base.id, plane->base.name, 5305 str_yes_no(plane_state->uapi.visible)); 5306 return; 5307 } 5308 5309 drm_dbg_kms(&i915->drm, 5310 "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %p4cc modifier = 0x%llx, visible: %s\n", 5311 plane->base.base.id, plane->base.name, 5312 fb->base.id, fb->width, fb->height, &fb->format->format, 5313 fb->modifier, str_yes_no(plane_state->uapi.visible)); 5314 drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n", 5315 plane_state->hw.rotation, plane_state->scaler_id); 5316 if (plane_state->uapi.visible) 5317 drm_dbg_kms(&i915->drm, 5318 "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n", 5319 DRM_RECT_FP_ARG(&plane_state->uapi.src), 5320 DRM_RECT_ARG(&plane_state->uapi.dst)); 5321 } 5322 5323 static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, 5324 struct intel_atomic_state *state, 5325 const char *context) 5326 { 5327 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 5328 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5329 const struct intel_plane_state *plane_state; 5330 struct intel_plane *plane; 5331 char buf[64]; 5332 int i; 5333 5334 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n", 5335 crtc->base.base.id, crtc->base.name, 5336 str_yes_no(pipe_config->hw.enable), context); 5337 5338 if (!pipe_config->hw.enable) 5339 goto dump_planes; 5340 5341 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types); 5342 drm_dbg_kms(&dev_priv->drm, 5343 "active: %s, output_types: %s (0x%x), output format: %s\n", 5344 str_yes_no(pipe_config->hw.active), 5345 buf, pipe_config->output_types, 5346 output_formats(pipe_config->output_format)); 5347 5348 drm_dbg_kms(&dev_priv->drm, 5349 "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", 5350 transcoder_name(pipe_config->cpu_transcoder), 5351 pipe_config->pipe_bpp, pipe_config->dither); 5352 5353 drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n", 5354 transcoder_name(pipe_config->mst_master_transcoder)); 5355 5356 drm_dbg_kms(&dev_priv->drm, 5357 "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n", 5358 transcoder_name(pipe_config->master_transcoder), 5359 pipe_config->sync_mode_slaves_mask); 5360 5361 drm_dbg_kms(&dev_priv->drm, "bigjoiner: %s, pipes: 0x%x\n", 5362 intel_crtc_is_bigjoiner_slave(pipe_config) ? "slave" : 5363 intel_crtc_is_bigjoiner_master(pipe_config) ? "master" : "no", 5364 pipe_config->bigjoiner_pipes); 5365 5366 drm_dbg_kms(&dev_priv->drm, "splitter: %s, link count %d, overlap %d\n", 5367 str_enabled_disabled(pipe_config->splitter.enable), 5368 pipe_config->splitter.link_count, 5369 pipe_config->splitter.pixel_overlap); 5370 5371 if (pipe_config->has_pch_encoder) 5372 intel_dump_m_n_config(pipe_config, "fdi", 5373 pipe_config->fdi_lanes, 5374 &pipe_config->fdi_m_n); 5375 5376 if (intel_crtc_has_dp_encoder(pipe_config)) { 5377 intel_dump_m_n_config(pipe_config, "dp m_n", 5378 pipe_config->lane_count, 5379 &pipe_config->dp_m_n); 5380 intel_dump_m_n_config(pipe_config, "dp m2_n2", 5381 pipe_config->lane_count, 5382 &pipe_config->dp_m2_n2); 5383 } 5384 5385 drm_dbg_kms(&dev_priv->drm, "framestart delay: %d, MSA timing delay: %d\n", 5386 pipe_config->framestart_delay, pipe_config->msa_timing_delay); 5387 5388 drm_dbg_kms(&dev_priv->drm, 5389 "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n", 5390 pipe_config->has_audio, pipe_config->has_infoframe, 5391 pipe_config->infoframes.enable); 5392 5393 if (pipe_config->infoframes.enable & 5394 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) 5395 drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n", 5396 pipe_config->infoframes.gcp); 5397 if (pipe_config->infoframes.enable & 5398 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) 5399 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi); 5400 if (pipe_config->infoframes.enable & 5401 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD)) 5402 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd); 5403 if (pipe_config->infoframes.enable & 5404 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR)) 5405 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi); 5406 if (pipe_config->infoframes.enable & 5407 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) 5408 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); 5409 if (pipe_config->infoframes.enable & 5410 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA)) 5411 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); 5412 if (pipe_config->infoframes.enable & 5413 intel_hdmi_infoframe_enable(DP_SDP_VSC)) 5414 intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc); 5415 5416 drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n", 5417 str_yes_no(pipe_config->vrr.enable), 5418 pipe_config->vrr.vmin, pipe_config->vrr.vmax, 5419 pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband, 5420 pipe_config->vrr.flipline, 5421 intel_vrr_vmin_vblank_start(pipe_config), 5422 intel_vrr_vmax_vblank_start(pipe_config)); 5423 5424 drm_dbg_kms(&dev_priv->drm, "requested mode:\n"); 5425 drm_mode_debug_printmodeline(&pipe_config->hw.mode); 5426 drm_dbg_kms(&dev_priv->drm, "adjusted mode:\n"); 5427 drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode); 5428 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode); 5429 drm_dbg_kms(&dev_priv->drm, "pipe mode:\n"); 5430 drm_mode_debug_printmodeline(&pipe_config->hw.pipe_mode); 5431 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode); 5432 drm_dbg_kms(&dev_priv->drm, 5433 "port clock: %d, pipe src: " DRM_RECT_FMT ", pixel rate %d\n", 5434 pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src), 5435 pipe_config->pixel_rate); 5436 5437 drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n", 5438 pipe_config->linetime, pipe_config->ips_linetime); 5439 5440 if (DISPLAY_VER(dev_priv) >= 9) 5441 drm_dbg_kms(&dev_priv->drm, 5442 "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", 5443 crtc->num_scalers, 5444 pipe_config->scaler_state.scaler_users, 5445 pipe_config->scaler_state.scaler_id); 5446 5447 if (HAS_GMCH(dev_priv)) 5448 drm_dbg_kms(&dev_priv->drm, 5449 "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", 5450 pipe_config->gmch_pfit.control, 5451 pipe_config->gmch_pfit.pgm_ratios, 5452 pipe_config->gmch_pfit.lvds_border_bits); 5453 else 5454 drm_dbg_kms(&dev_priv->drm, 5455 "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n", 5456 DRM_RECT_ARG(&pipe_config->pch_pfit.dst), 5457 str_enabled_disabled(pipe_config->pch_pfit.enabled), 5458 str_yes_no(pipe_config->pch_pfit.force_thru)); 5459 5460 drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i, drrs: %i\n", 5461 pipe_config->ips_enabled, pipe_config->double_wide, 5462 pipe_config->has_drrs); 5463 5464 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state); 5465 5466 if (IS_CHERRYVIEW(dev_priv)) 5467 drm_dbg_kms(&dev_priv->drm, 5468 "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", 5469 pipe_config->cgm_mode, pipe_config->gamma_mode, 5470 pipe_config->gamma_enable, pipe_config->csc_enable); 5471 else 5472 drm_dbg_kms(&dev_priv->drm, 5473 "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", 5474 pipe_config->csc_mode, pipe_config->gamma_mode, 5475 pipe_config->gamma_enable, pipe_config->csc_enable); 5476 5477 drm_dbg_kms(&dev_priv->drm, "degamma lut: %d entries, gamma lut: %d entries\n", 5478 pipe_config->hw.degamma_lut ? 5479 drm_color_lut_size(pipe_config->hw.degamma_lut) : 0, 5480 pipe_config->hw.gamma_lut ? 5481 drm_color_lut_size(pipe_config->hw.gamma_lut) : 0); 5482 5483 dump_planes: 5484 if (!state) 5485 return; 5486 5487 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 5488 if (plane->pipe == crtc->pipe) 5489 intel_dump_plane_state(plane_state); 5490 } 5491 } 5492 5493 static bool check_digital_port_conflicts(struct intel_atomic_state *state) 5494 { 5495 struct drm_device *dev = state->base.dev; 5496 struct drm_connector *connector; 5497 struct drm_connector_list_iter conn_iter; 5498 unsigned int used_ports = 0; 5499 unsigned int used_mst_ports = 0; 5500 bool ret = true; 5501 5502 /* 5503 * We're going to peek into connector->state, 5504 * hence connection_mutex must be held. 5505 */ 5506 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex); 5507 5508 /* 5509 * Walk the connector list instead of the encoder 5510 * list to detect the problem on ddi platforms 5511 * where there's just one encoder per digital port. 5512 */ 5513 drm_connector_list_iter_begin(dev, &conn_iter); 5514 drm_for_each_connector_iter(connector, &conn_iter) { 5515 struct drm_connector_state *connector_state; 5516 struct intel_encoder *encoder; 5517 5518 connector_state = 5519 drm_atomic_get_new_connector_state(&state->base, 5520 connector); 5521 if (!connector_state) 5522 connector_state = connector->state; 5523 5524 if (!connector_state->best_encoder) 5525 continue; 5526 5527 encoder = to_intel_encoder(connector_state->best_encoder); 5528 5529 drm_WARN_ON(dev, !connector_state->crtc); 5530 5531 switch (encoder->type) { 5532 case INTEL_OUTPUT_DDI: 5533 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev)))) 5534 break; 5535 fallthrough; 5536 case INTEL_OUTPUT_DP: 5537 case INTEL_OUTPUT_HDMI: 5538 case INTEL_OUTPUT_EDP: 5539 /* the same port mustn't appear more than once */ 5540 if (used_ports & BIT(encoder->port)) 5541 ret = false; 5542 5543 used_ports |= BIT(encoder->port); 5544 break; 5545 case INTEL_OUTPUT_DP_MST: 5546 used_mst_ports |= 5547 1 << encoder->port; 5548 break; 5549 default: 5550 break; 5551 } 5552 } 5553 drm_connector_list_iter_end(&conn_iter); 5554 5555 /* can't mix MST and SST/HDMI on the same port */ 5556 if (used_ports & used_mst_ports) 5557 return false; 5558 5559 return ret; 5560 } 5561 5562 static void 5563 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state, 5564 struct intel_crtc *crtc) 5565 { 5566 struct intel_crtc_state *crtc_state = 5567 intel_atomic_get_new_crtc_state(state, crtc); 5568 5569 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 5570 5571 drm_property_replace_blob(&crtc_state->hw.degamma_lut, 5572 crtc_state->uapi.degamma_lut); 5573 drm_property_replace_blob(&crtc_state->hw.gamma_lut, 5574 crtc_state->uapi.gamma_lut); 5575 drm_property_replace_blob(&crtc_state->hw.ctm, 5576 crtc_state->uapi.ctm); 5577 } 5578 5579 static void 5580 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state, 5581 struct intel_crtc *crtc) 5582 { 5583 struct intel_crtc_state *crtc_state = 5584 intel_atomic_get_new_crtc_state(state, crtc); 5585 5586 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 5587 5588 crtc_state->hw.enable = crtc_state->uapi.enable; 5589 crtc_state->hw.active = crtc_state->uapi.active; 5590 drm_mode_copy(&crtc_state->hw.mode, 5591 &crtc_state->uapi.mode); 5592 drm_mode_copy(&crtc_state->hw.adjusted_mode, 5593 &crtc_state->uapi.adjusted_mode); 5594 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter; 5595 5596 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 5597 } 5598 5599 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state) 5600 { 5601 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 5602 return; 5603 5604 crtc_state->uapi.enable = crtc_state->hw.enable; 5605 crtc_state->uapi.active = crtc_state->hw.active; 5606 drm_WARN_ON(crtc_state->uapi.crtc->dev, 5607 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0); 5608 5609 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode; 5610 crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter; 5611 5612 drm_property_replace_blob(&crtc_state->uapi.degamma_lut, 5613 crtc_state->hw.degamma_lut); 5614 drm_property_replace_blob(&crtc_state->uapi.gamma_lut, 5615 crtc_state->hw.gamma_lut); 5616 drm_property_replace_blob(&crtc_state->uapi.ctm, 5617 crtc_state->hw.ctm); 5618 } 5619 5620 static void 5621 copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state, 5622 struct intel_crtc *slave_crtc) 5623 { 5624 struct intel_crtc_state *slave_crtc_state = 5625 intel_atomic_get_new_crtc_state(state, slave_crtc); 5626 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 5627 const struct intel_crtc_state *master_crtc_state = 5628 intel_atomic_get_new_crtc_state(state, master_crtc); 5629 5630 drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut, 5631 master_crtc_state->hw.degamma_lut); 5632 drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut, 5633 master_crtc_state->hw.gamma_lut); 5634 drm_property_replace_blob(&slave_crtc_state->hw.ctm, 5635 master_crtc_state->hw.ctm); 5636 5637 slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed; 5638 } 5639 5640 static int 5641 copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state, 5642 struct intel_crtc *slave_crtc) 5643 { 5644 struct intel_crtc_state *slave_crtc_state = 5645 intel_atomic_get_new_crtc_state(state, slave_crtc); 5646 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 5647 const struct intel_crtc_state *master_crtc_state = 5648 intel_atomic_get_new_crtc_state(state, master_crtc); 5649 struct intel_crtc_state *saved_state; 5650 5651 WARN_ON(master_crtc_state->bigjoiner_pipes != 5652 slave_crtc_state->bigjoiner_pipes); 5653 5654 saved_state = kmemdup(master_crtc_state, sizeof(*saved_state), GFP_KERNEL); 5655 if (!saved_state) 5656 return -ENOMEM; 5657 5658 /* preserve some things from the slave's original crtc state */ 5659 saved_state->uapi = slave_crtc_state->uapi; 5660 saved_state->scaler_state = slave_crtc_state->scaler_state; 5661 saved_state->shared_dpll = slave_crtc_state->shared_dpll; 5662 saved_state->dpll_hw_state = slave_crtc_state->dpll_hw_state; 5663 saved_state->crc_enabled = slave_crtc_state->crc_enabled; 5664 5665 intel_crtc_free_hw_state(slave_crtc_state); 5666 memcpy(slave_crtc_state, saved_state, sizeof(*slave_crtc_state)); 5667 kfree(saved_state); 5668 5669 /* Re-init hw state */ 5670 memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw)); 5671 slave_crtc_state->hw.enable = master_crtc_state->hw.enable; 5672 slave_crtc_state->hw.active = master_crtc_state->hw.active; 5673 drm_mode_copy(&slave_crtc_state->hw.mode, 5674 &master_crtc_state->hw.mode); 5675 drm_mode_copy(&slave_crtc_state->hw.pipe_mode, 5676 &master_crtc_state->hw.pipe_mode); 5677 drm_mode_copy(&slave_crtc_state->hw.adjusted_mode, 5678 &master_crtc_state->hw.adjusted_mode); 5679 slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter; 5680 5681 copy_bigjoiner_crtc_state_nomodeset(state, slave_crtc); 5682 5683 slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed; 5684 slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed; 5685 slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed; 5686 5687 WARN_ON(master_crtc_state->bigjoiner_pipes != 5688 slave_crtc_state->bigjoiner_pipes); 5689 5690 return 0; 5691 } 5692 5693 static int 5694 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state, 5695 struct intel_crtc *crtc) 5696 { 5697 struct intel_crtc_state *crtc_state = 5698 intel_atomic_get_new_crtc_state(state, crtc); 5699 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5700 struct intel_crtc_state *saved_state; 5701 5702 saved_state = intel_crtc_state_alloc(crtc); 5703 if (!saved_state) 5704 return -ENOMEM; 5705 5706 /* free the old crtc_state->hw members */ 5707 intel_crtc_free_hw_state(crtc_state); 5708 5709 /* FIXME: before the switch to atomic started, a new pipe_config was 5710 * kzalloc'd. Code that depends on any field being zero should be 5711 * fixed, so that the crtc_state can be safely duplicated. For now, 5712 * only fields that are know to not cause problems are preserved. */ 5713 5714 saved_state->uapi = crtc_state->uapi; 5715 saved_state->scaler_state = crtc_state->scaler_state; 5716 saved_state->shared_dpll = crtc_state->shared_dpll; 5717 saved_state->dpll_hw_state = crtc_state->dpll_hw_state; 5718 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, 5719 sizeof(saved_state->icl_port_dplls)); 5720 saved_state->crc_enabled = crtc_state->crc_enabled; 5721 if (IS_G4X(dev_priv) || 5722 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5723 saved_state->wm = crtc_state->wm; 5724 5725 memcpy(crtc_state, saved_state, sizeof(*crtc_state)); 5726 kfree(saved_state); 5727 5728 intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc); 5729 5730 return 0; 5731 } 5732 5733 static int 5734 intel_modeset_pipe_config(struct intel_atomic_state *state, 5735 struct intel_crtc_state *pipe_config) 5736 { 5737 struct drm_crtc *crtc = pipe_config->uapi.crtc; 5738 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); 5739 struct drm_connector *connector; 5740 struct drm_connector_state *connector_state; 5741 int pipe_src_w, pipe_src_h; 5742 int base_bpp, ret, i; 5743 bool retry = true; 5744 5745 pipe_config->cpu_transcoder = 5746 (enum transcoder) to_intel_crtc(crtc)->pipe; 5747 5748 pipe_config->framestart_delay = 1; 5749 5750 /* 5751 * Sanitize sync polarity flags based on requested ones. If neither 5752 * positive or negative polarity is requested, treat this as meaning 5753 * negative polarity. 5754 */ 5755 if (!(pipe_config->hw.adjusted_mode.flags & 5756 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) 5757 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; 5758 5759 if (!(pipe_config->hw.adjusted_mode.flags & 5760 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 5761 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; 5762 5763 ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc), 5764 pipe_config); 5765 if (ret) 5766 return ret; 5767 5768 base_bpp = pipe_config->pipe_bpp; 5769 5770 /* 5771 * Determine the real pipe dimensions. Note that stereo modes can 5772 * increase the actual pipe size due to the frame doubling and 5773 * insertion of additional space for blanks between the frame. This 5774 * is stored in the crtc timings. We use the requested mode to do this 5775 * computation to clearly distinguish it from the adjusted mode, which 5776 * can be changed by the connectors in the below retry loop. 5777 */ 5778 drm_mode_get_hv_timing(&pipe_config->hw.mode, 5779 &pipe_src_w, &pipe_src_h); 5780 drm_rect_init(&pipe_config->pipe_src, 0, 0, 5781 pipe_src_w, pipe_src_h); 5782 5783 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5784 struct intel_encoder *encoder = 5785 to_intel_encoder(connector_state->best_encoder); 5786 5787 if (connector_state->crtc != crtc) 5788 continue; 5789 5790 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) { 5791 drm_dbg_kms(&i915->drm, 5792 "rejecting invalid cloning configuration\n"); 5793 return -EINVAL; 5794 } 5795 5796 /* 5797 * Determine output_types before calling the .compute_config() 5798 * hooks so that the hooks can use this information safely. 5799 */ 5800 if (encoder->compute_output_type) 5801 pipe_config->output_types |= 5802 BIT(encoder->compute_output_type(encoder, pipe_config, 5803 connector_state)); 5804 else 5805 pipe_config->output_types |= BIT(encoder->type); 5806 } 5807 5808 encoder_retry: 5809 /* Ensure the port clock defaults are reset when retrying. */ 5810 pipe_config->port_clock = 0; 5811 pipe_config->pixel_multiplier = 1; 5812 5813 /* Fill in default crtc timings, allow encoders to overwrite them. */ 5814 drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode, 5815 CRTC_STEREO_DOUBLE); 5816 5817 /* Pass our mode to the connectors and the CRTC to give them a chance to 5818 * adjust it according to limitations or connector properties, and also 5819 * a chance to reject the mode entirely. 5820 */ 5821 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5822 struct intel_encoder *encoder = 5823 to_intel_encoder(connector_state->best_encoder); 5824 5825 if (connector_state->crtc != crtc) 5826 continue; 5827 5828 ret = encoder->compute_config(encoder, pipe_config, 5829 connector_state); 5830 if (ret == -EDEADLK) 5831 return ret; 5832 if (ret < 0) { 5833 drm_dbg_kms(&i915->drm, "Encoder config failure: %d\n", ret); 5834 return ret; 5835 } 5836 } 5837 5838 /* Set default port clock if not overwritten by the encoder. Needs to be 5839 * done afterwards in case the encoder adjusts the mode. */ 5840 if (!pipe_config->port_clock) 5841 pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock 5842 * pipe_config->pixel_multiplier; 5843 5844 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); 5845 if (ret == -EDEADLK) 5846 return ret; 5847 if (ret == -EAGAIN) { 5848 if (drm_WARN(&i915->drm, !retry, 5849 "loop in pipe configuration computation\n")) 5850 return -EINVAL; 5851 5852 drm_dbg_kms(&i915->drm, "CRTC bw constrained, retrying\n"); 5853 retry = false; 5854 goto encoder_retry; 5855 } 5856 if (ret < 0) { 5857 drm_dbg_kms(&i915->drm, "CRTC config failure: %d\n", ret); 5858 return ret; 5859 } 5860 5861 /* Dithering seems to not pass-through bits correctly when it should, so 5862 * only enable it on 6bpc panels and when its not a compliance 5863 * test requesting 6bpc video pattern. 5864 */ 5865 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) && 5866 !pipe_config->dither_force_disable; 5867 drm_dbg_kms(&i915->drm, 5868 "hw max bpp: %i, pipe bpp: %i, dithering: %i\n", 5869 base_bpp, pipe_config->pipe_bpp, pipe_config->dither); 5870 5871 return 0; 5872 } 5873 5874 static int 5875 intel_modeset_pipe_config_late(struct intel_crtc_state *crtc_state) 5876 { 5877 struct intel_atomic_state *state = 5878 to_intel_atomic_state(crtc_state->uapi.state); 5879 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 5880 struct drm_connector_state *conn_state; 5881 struct drm_connector *connector; 5882 int i; 5883 5884 intel_bigjoiner_adjust_pipe_src(crtc_state); 5885 5886 for_each_new_connector_in_state(&state->base, connector, 5887 conn_state, i) { 5888 struct intel_encoder *encoder = 5889 to_intel_encoder(conn_state->best_encoder); 5890 int ret; 5891 5892 if (conn_state->crtc != &crtc->base || 5893 !encoder->compute_config_late) 5894 continue; 5895 5896 ret = encoder->compute_config_late(encoder, crtc_state, 5897 conn_state); 5898 if (ret) 5899 return ret; 5900 } 5901 5902 return 0; 5903 } 5904 5905 bool intel_fuzzy_clock_check(int clock1, int clock2) 5906 { 5907 int diff; 5908 5909 if (clock1 == clock2) 5910 return true; 5911 5912 if (!clock1 || !clock2) 5913 return false; 5914 5915 diff = abs(clock1 - clock2); 5916 5917 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) 5918 return true; 5919 5920 return false; 5921 } 5922 5923 static bool 5924 intel_compare_m_n(unsigned int m, unsigned int n, 5925 unsigned int m2, unsigned int n2, 5926 bool exact) 5927 { 5928 if (m == m2 && n == n2) 5929 return true; 5930 5931 if (exact || !m || !n || !m2 || !n2) 5932 return false; 5933 5934 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); 5935 5936 if (n > n2) { 5937 while (n > n2) { 5938 m2 <<= 1; 5939 n2 <<= 1; 5940 } 5941 } else if (n < n2) { 5942 while (n < n2) { 5943 m <<= 1; 5944 n <<= 1; 5945 } 5946 } 5947 5948 if (n != n2) 5949 return false; 5950 5951 return intel_fuzzy_clock_check(m, m2); 5952 } 5953 5954 static bool 5955 intel_compare_link_m_n(const struct intel_link_m_n *m_n, 5956 const struct intel_link_m_n *m2_n2, 5957 bool exact) 5958 { 5959 return m_n->tu == m2_n2->tu && 5960 intel_compare_m_n(m_n->data_m, m_n->data_n, 5961 m2_n2->data_m, m2_n2->data_n, exact) && 5962 intel_compare_m_n(m_n->link_m, m_n->link_n, 5963 m2_n2->link_m, m2_n2->link_n, exact); 5964 } 5965 5966 static bool 5967 intel_compare_infoframe(const union hdmi_infoframe *a, 5968 const union hdmi_infoframe *b) 5969 { 5970 return memcmp(a, b, sizeof(*a)) == 0; 5971 } 5972 5973 static bool 5974 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a, 5975 const struct drm_dp_vsc_sdp *b) 5976 { 5977 return memcmp(a, b, sizeof(*a)) == 0; 5978 } 5979 5980 static void 5981 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv, 5982 bool fastset, const char *name, 5983 const union hdmi_infoframe *a, 5984 const union hdmi_infoframe *b) 5985 { 5986 if (fastset) { 5987 if (!drm_debug_enabled(DRM_UT_KMS)) 5988 return; 5989 5990 drm_dbg_kms(&dev_priv->drm, 5991 "fastset mismatch in %s infoframe\n", name); 5992 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 5993 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a); 5994 drm_dbg_kms(&dev_priv->drm, "found:\n"); 5995 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b); 5996 } else { 5997 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name); 5998 drm_err(&dev_priv->drm, "expected:\n"); 5999 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a); 6000 drm_err(&dev_priv->drm, "found:\n"); 6001 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b); 6002 } 6003 } 6004 6005 static void 6006 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv, 6007 bool fastset, const char *name, 6008 const struct drm_dp_vsc_sdp *a, 6009 const struct drm_dp_vsc_sdp *b) 6010 { 6011 if (fastset) { 6012 if (!drm_debug_enabled(DRM_UT_KMS)) 6013 return; 6014 6015 drm_dbg_kms(&dev_priv->drm, 6016 "fastset mismatch in %s dp sdp\n", name); 6017 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 6018 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a); 6019 drm_dbg_kms(&dev_priv->drm, "found:\n"); 6020 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b); 6021 } else { 6022 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name); 6023 drm_err(&dev_priv->drm, "expected:\n"); 6024 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a); 6025 drm_err(&dev_priv->drm, "found:\n"); 6026 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b); 6027 } 6028 } 6029 6030 static void __printf(4, 5) 6031 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc, 6032 const char *name, const char *format, ...) 6033 { 6034 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 6035 struct va_format vaf; 6036 va_list args; 6037 6038 va_start(args, format); 6039 vaf.fmt = format; 6040 vaf.va = &args; 6041 6042 if (fastset) 6043 drm_dbg_kms(&i915->drm, 6044 "[CRTC:%d:%s] fastset mismatch in %s %pV\n", 6045 crtc->base.base.id, crtc->base.name, name, &vaf); 6046 else 6047 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n", 6048 crtc->base.base.id, crtc->base.name, name, &vaf); 6049 6050 va_end(args); 6051 } 6052 6053 static bool fastboot_enabled(struct drm_i915_private *dev_priv) 6054 { 6055 if (dev_priv->params.fastboot != -1) 6056 return dev_priv->params.fastboot; 6057 6058 /* Enable fastboot by default on Skylake and newer */ 6059 if (DISPLAY_VER(dev_priv) >= 9) 6060 return true; 6061 6062 /* Enable fastboot by default on VLV and CHV */ 6063 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 6064 return true; 6065 6066 /* Disabled by default on all others */ 6067 return false; 6068 } 6069 6070 static bool 6071 intel_pipe_config_compare(const struct intel_crtc_state *current_config, 6072 const struct intel_crtc_state *pipe_config, 6073 bool fastset) 6074 { 6075 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev); 6076 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 6077 bool ret = true; 6078 u32 bp_gamma = 0; 6079 bool fixup_inherited = fastset && 6080 current_config->inherited && !pipe_config->inherited; 6081 6082 if (fixup_inherited && !fastboot_enabled(dev_priv)) { 6083 drm_dbg_kms(&dev_priv->drm, 6084 "initial modeset and fastboot not set\n"); 6085 ret = false; 6086 } 6087 6088 #define PIPE_CONF_CHECK_X(name) do { \ 6089 if (current_config->name != pipe_config->name) { \ 6090 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6091 "(expected 0x%08x, found 0x%08x)", \ 6092 current_config->name, \ 6093 pipe_config->name); \ 6094 ret = false; \ 6095 } \ 6096 } while (0) 6097 6098 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \ 6099 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \ 6100 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6101 "(expected 0x%08x, found 0x%08x)", \ 6102 current_config->name & (mask), \ 6103 pipe_config->name & (mask)); \ 6104 ret = false; \ 6105 } \ 6106 } while (0) 6107 6108 #define PIPE_CONF_CHECK_I(name) do { \ 6109 if (current_config->name != pipe_config->name) { \ 6110 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6111 "(expected %i, found %i)", \ 6112 current_config->name, \ 6113 pipe_config->name); \ 6114 ret = false; \ 6115 } \ 6116 } while (0) 6117 6118 #define PIPE_CONF_CHECK_BOOL(name) do { \ 6119 if (current_config->name != pipe_config->name) { \ 6120 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6121 "(expected %s, found %s)", \ 6122 str_yes_no(current_config->name), \ 6123 str_yes_no(pipe_config->name)); \ 6124 ret = false; \ 6125 } \ 6126 } while (0) 6127 6128 /* 6129 * Checks state where we only read out the enabling, but not the entire 6130 * state itself (like full infoframes or ELD for audio). These states 6131 * require a full modeset on bootup to fix up. 6132 */ 6133 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \ 6134 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \ 6135 PIPE_CONF_CHECK_BOOL(name); \ 6136 } else { \ 6137 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6138 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \ 6139 str_yes_no(current_config->name), \ 6140 str_yes_no(pipe_config->name)); \ 6141 ret = false; \ 6142 } \ 6143 } while (0) 6144 6145 #define PIPE_CONF_CHECK_P(name) do { \ 6146 if (current_config->name != pipe_config->name) { \ 6147 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6148 "(expected %p, found %p)", \ 6149 current_config->name, \ 6150 pipe_config->name); \ 6151 ret = false; \ 6152 } \ 6153 } while (0) 6154 6155 #define PIPE_CONF_CHECK_M_N(name) do { \ 6156 if (!intel_compare_link_m_n(¤t_config->name, \ 6157 &pipe_config->name,\ 6158 !fastset)) { \ 6159 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6160 "(expected tu %i data %i/%i link %i/%i, " \ 6161 "found tu %i, data %i/%i link %i/%i)", \ 6162 current_config->name.tu, \ 6163 current_config->name.data_m, \ 6164 current_config->name.data_n, \ 6165 current_config->name.link_m, \ 6166 current_config->name.link_n, \ 6167 pipe_config->name.tu, \ 6168 pipe_config->name.data_m, \ 6169 pipe_config->name.data_n, \ 6170 pipe_config->name.link_m, \ 6171 pipe_config->name.link_n); \ 6172 ret = false; \ 6173 } \ 6174 } while (0) 6175 6176 /* This is required for BDW+ where there is only one set of registers for 6177 * switching between high and low RR. 6178 * This macro can be used whenever a comparison has to be made between one 6179 * hw state and multiple sw state variables. 6180 */ 6181 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \ 6182 if (!intel_compare_link_m_n(¤t_config->name, \ 6183 &pipe_config->name, !fastset) && \ 6184 !intel_compare_link_m_n(¤t_config->alt_name, \ 6185 &pipe_config->name, !fastset)) { \ 6186 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6187 "(expected tu %i data %i/%i link %i/%i, " \ 6188 "or tu %i data %i/%i link %i/%i, " \ 6189 "found tu %i, data %i/%i link %i/%i)", \ 6190 current_config->name.tu, \ 6191 current_config->name.data_m, \ 6192 current_config->name.data_n, \ 6193 current_config->name.link_m, \ 6194 current_config->name.link_n, \ 6195 current_config->alt_name.tu, \ 6196 current_config->alt_name.data_m, \ 6197 current_config->alt_name.data_n, \ 6198 current_config->alt_name.link_m, \ 6199 current_config->alt_name.link_n, \ 6200 pipe_config->name.tu, \ 6201 pipe_config->name.data_m, \ 6202 pipe_config->name.data_n, \ 6203 pipe_config->name.link_m, \ 6204 pipe_config->name.link_n); \ 6205 ret = false; \ 6206 } \ 6207 } while (0) 6208 6209 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \ 6210 if ((current_config->name ^ pipe_config->name) & (mask)) { \ 6211 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6212 "(%x) (expected %i, found %i)", \ 6213 (mask), \ 6214 current_config->name & (mask), \ 6215 pipe_config->name & (mask)); \ 6216 ret = false; \ 6217 } \ 6218 } while (0) 6219 6220 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \ 6221 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ 6222 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6223 "(expected %i, found %i)", \ 6224 current_config->name, \ 6225 pipe_config->name); \ 6226 ret = false; \ 6227 } \ 6228 } while (0) 6229 6230 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \ 6231 if (!intel_compare_infoframe(¤t_config->infoframes.name, \ 6232 &pipe_config->infoframes.name)) { \ 6233 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \ 6234 ¤t_config->infoframes.name, \ 6235 &pipe_config->infoframes.name); \ 6236 ret = false; \ 6237 } \ 6238 } while (0) 6239 6240 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \ 6241 if (!current_config->has_psr && !pipe_config->has_psr && \ 6242 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \ 6243 &pipe_config->infoframes.name)) { \ 6244 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \ 6245 ¤t_config->infoframes.name, \ 6246 &pipe_config->infoframes.name); \ 6247 ret = false; \ 6248 } \ 6249 } while (0) 6250 6251 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \ 6252 if (current_config->name1 != pipe_config->name1) { \ 6253 pipe_config_mismatch(fastset, crtc, __stringify(name1), \ 6254 "(expected %i, found %i, won't compare lut values)", \ 6255 current_config->name1, \ 6256 pipe_config->name1); \ 6257 ret = false;\ 6258 } else { \ 6259 if (!intel_color_lut_equal(current_config->name2, \ 6260 pipe_config->name2, pipe_config->name1, \ 6261 bit_precision)) { \ 6262 pipe_config_mismatch(fastset, crtc, __stringify(name2), \ 6263 "hw_state doesn't match sw_state"); \ 6264 ret = false; \ 6265 } \ 6266 } \ 6267 } while (0) 6268 6269 #define PIPE_CONF_QUIRK(quirk) \ 6270 ((current_config->quirks | pipe_config->quirks) & (quirk)) 6271 6272 PIPE_CONF_CHECK_I(cpu_transcoder); 6273 6274 PIPE_CONF_CHECK_BOOL(has_pch_encoder); 6275 PIPE_CONF_CHECK_I(fdi_lanes); 6276 PIPE_CONF_CHECK_M_N(fdi_m_n); 6277 6278 PIPE_CONF_CHECK_I(lane_count); 6279 PIPE_CONF_CHECK_X(lane_lat_optim_mask); 6280 6281 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) { 6282 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); 6283 } else { 6284 PIPE_CONF_CHECK_M_N(dp_m_n); 6285 PIPE_CONF_CHECK_M_N(dp_m2_n2); 6286 } 6287 6288 PIPE_CONF_CHECK_X(output_types); 6289 6290 PIPE_CONF_CHECK_I(framestart_delay); 6291 PIPE_CONF_CHECK_I(msa_timing_delay); 6292 6293 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay); 6294 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_htotal); 6295 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_start); 6296 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_end); 6297 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_start); 6298 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_end); 6299 6300 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vdisplay); 6301 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vtotal); 6302 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_start); 6303 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_end); 6304 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_start); 6305 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_end); 6306 6307 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay); 6308 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal); 6309 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start); 6310 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end); 6311 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start); 6312 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end); 6313 6314 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay); 6315 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal); 6316 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start); 6317 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end); 6318 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start); 6319 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end); 6320 6321 PIPE_CONF_CHECK_I(pixel_multiplier); 6322 6323 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6324 DRM_MODE_FLAG_INTERLACE); 6325 6326 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { 6327 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6328 DRM_MODE_FLAG_PHSYNC); 6329 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6330 DRM_MODE_FLAG_NHSYNC); 6331 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6332 DRM_MODE_FLAG_PVSYNC); 6333 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6334 DRM_MODE_FLAG_NVSYNC); 6335 } 6336 6337 PIPE_CONF_CHECK_I(output_format); 6338 PIPE_CONF_CHECK_BOOL(has_hdmi_sink); 6339 if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || 6340 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 6341 PIPE_CONF_CHECK_BOOL(limited_color_range); 6342 6343 PIPE_CONF_CHECK_BOOL(hdmi_scrambling); 6344 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio); 6345 PIPE_CONF_CHECK_BOOL(has_infoframe); 6346 PIPE_CONF_CHECK_BOOL(fec_enable); 6347 6348 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio); 6349 6350 PIPE_CONF_CHECK_X(gmch_pfit.control); 6351 /* pfit ratios are autocomputed by the hw on gen4+ */ 6352 if (DISPLAY_VER(dev_priv) < 4) 6353 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); 6354 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); 6355 6356 /* 6357 * Changing the EDP transcoder input mux 6358 * (A_ONOFF vs. A_ON) requires a full modeset. 6359 */ 6360 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru); 6361 6362 if (!fastset) { 6363 PIPE_CONF_CHECK_I(pipe_src.x1); 6364 PIPE_CONF_CHECK_I(pipe_src.y1); 6365 PIPE_CONF_CHECK_I(pipe_src.x2); 6366 PIPE_CONF_CHECK_I(pipe_src.y2); 6367 6368 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled); 6369 if (current_config->pch_pfit.enabled) { 6370 PIPE_CONF_CHECK_I(pch_pfit.dst.x1); 6371 PIPE_CONF_CHECK_I(pch_pfit.dst.y1); 6372 PIPE_CONF_CHECK_I(pch_pfit.dst.x2); 6373 PIPE_CONF_CHECK_I(pch_pfit.dst.y2); 6374 } 6375 6376 PIPE_CONF_CHECK_I(scaler_state.scaler_id); 6377 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate); 6378 6379 PIPE_CONF_CHECK_X(gamma_mode); 6380 if (IS_CHERRYVIEW(dev_priv)) 6381 PIPE_CONF_CHECK_X(cgm_mode); 6382 else 6383 PIPE_CONF_CHECK_X(csc_mode); 6384 PIPE_CONF_CHECK_BOOL(gamma_enable); 6385 PIPE_CONF_CHECK_BOOL(csc_enable); 6386 6387 PIPE_CONF_CHECK_I(linetime); 6388 PIPE_CONF_CHECK_I(ips_linetime); 6389 6390 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config); 6391 if (bp_gamma) 6392 PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma); 6393 6394 if (current_config->active_planes) { 6395 PIPE_CONF_CHECK_BOOL(has_psr); 6396 PIPE_CONF_CHECK_BOOL(has_psr2); 6397 PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); 6398 PIPE_CONF_CHECK_I(dc3co_exitline); 6399 } 6400 } 6401 6402 PIPE_CONF_CHECK_BOOL(double_wide); 6403 6404 if (dev_priv->dpll.mgr) { 6405 PIPE_CONF_CHECK_P(shared_dpll); 6406 6407 PIPE_CONF_CHECK_X(dpll_hw_state.dpll); 6408 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); 6409 PIPE_CONF_CHECK_X(dpll_hw_state.fp0); 6410 PIPE_CONF_CHECK_X(dpll_hw_state.fp1); 6411 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); 6412 PIPE_CONF_CHECK_X(dpll_hw_state.spll); 6413 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); 6414 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); 6415 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); 6416 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); 6417 PIPE_CONF_CHECK_X(dpll_hw_state.div0); 6418 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); 6419 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); 6420 PIPE_CONF_CHECK_X(dpll_hw_state.pll0); 6421 PIPE_CONF_CHECK_X(dpll_hw_state.pll1); 6422 PIPE_CONF_CHECK_X(dpll_hw_state.pll2); 6423 PIPE_CONF_CHECK_X(dpll_hw_state.pll3); 6424 PIPE_CONF_CHECK_X(dpll_hw_state.pll6); 6425 PIPE_CONF_CHECK_X(dpll_hw_state.pll8); 6426 PIPE_CONF_CHECK_X(dpll_hw_state.pll9); 6427 PIPE_CONF_CHECK_X(dpll_hw_state.pll10); 6428 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); 6429 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl); 6430 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1); 6431 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl); 6432 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0); 6433 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1); 6434 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf); 6435 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock); 6436 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc); 6437 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias); 6438 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias); 6439 } 6440 6441 PIPE_CONF_CHECK_X(dsi_pll.ctrl); 6442 PIPE_CONF_CHECK_X(dsi_pll.div); 6443 6444 if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5) 6445 PIPE_CONF_CHECK_I(pipe_bpp); 6446 6447 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock); 6448 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock); 6449 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); 6450 6451 PIPE_CONF_CHECK_I(min_voltage_level); 6452 6453 if (current_config->has_psr || pipe_config->has_psr) 6454 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable, 6455 ~intel_hdmi_infoframe_enable(DP_SDP_VSC)); 6456 else 6457 PIPE_CONF_CHECK_X(infoframes.enable); 6458 6459 PIPE_CONF_CHECK_X(infoframes.gcp); 6460 PIPE_CONF_CHECK_INFOFRAME(avi); 6461 PIPE_CONF_CHECK_INFOFRAME(spd); 6462 PIPE_CONF_CHECK_INFOFRAME(hdmi); 6463 PIPE_CONF_CHECK_INFOFRAME(drm); 6464 PIPE_CONF_CHECK_DP_VSC_SDP(vsc); 6465 6466 PIPE_CONF_CHECK_X(sync_mode_slaves_mask); 6467 PIPE_CONF_CHECK_I(master_transcoder); 6468 PIPE_CONF_CHECK_X(bigjoiner_pipes); 6469 6470 PIPE_CONF_CHECK_I(dsc.compression_enable); 6471 PIPE_CONF_CHECK_I(dsc.dsc_split); 6472 PIPE_CONF_CHECK_I(dsc.compressed_bpp); 6473 6474 PIPE_CONF_CHECK_BOOL(splitter.enable); 6475 PIPE_CONF_CHECK_I(splitter.link_count); 6476 PIPE_CONF_CHECK_I(splitter.pixel_overlap); 6477 6478 PIPE_CONF_CHECK_I(mst_master_transcoder); 6479 6480 PIPE_CONF_CHECK_BOOL(vrr.enable); 6481 PIPE_CONF_CHECK_I(vrr.vmin); 6482 PIPE_CONF_CHECK_I(vrr.vmax); 6483 PIPE_CONF_CHECK_I(vrr.flipline); 6484 PIPE_CONF_CHECK_I(vrr.pipeline_full); 6485 PIPE_CONF_CHECK_I(vrr.guardband); 6486 6487 #undef PIPE_CONF_CHECK_X 6488 #undef PIPE_CONF_CHECK_I 6489 #undef PIPE_CONF_CHECK_BOOL 6490 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE 6491 #undef PIPE_CONF_CHECK_P 6492 #undef PIPE_CONF_CHECK_FLAGS 6493 #undef PIPE_CONF_CHECK_CLOCK_FUZZY 6494 #undef PIPE_CONF_CHECK_COLOR_LUT 6495 #undef PIPE_CONF_QUIRK 6496 6497 return ret; 6498 } 6499 6500 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, 6501 const struct intel_crtc_state *pipe_config) 6502 { 6503 if (pipe_config->has_pch_encoder) { 6504 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), 6505 &pipe_config->fdi_m_n); 6506 int dotclock = pipe_config->hw.adjusted_mode.crtc_clock; 6507 6508 /* 6509 * FDI already provided one idea for the dotclock. 6510 * Yell if the encoder disagrees. 6511 */ 6512 drm_WARN(&dev_priv->drm, 6513 !intel_fuzzy_clock_check(fdi_dotclock, dotclock), 6514 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", 6515 fdi_dotclock, dotclock); 6516 } 6517 } 6518 6519 static void verify_wm_state(struct intel_crtc *crtc, 6520 struct intel_crtc_state *new_crtc_state) 6521 { 6522 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6523 struct skl_hw_state { 6524 struct skl_ddb_entry ddb[I915_MAX_PLANES]; 6525 struct skl_ddb_entry ddb_y[I915_MAX_PLANES]; 6526 struct skl_pipe_wm wm; 6527 } *hw; 6528 const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal; 6529 int level, max_level = ilk_wm_max_level(dev_priv); 6530 struct intel_plane *plane; 6531 u8 hw_enabled_slices; 6532 6533 if (DISPLAY_VER(dev_priv) < 9 || !new_crtc_state->hw.active) 6534 return; 6535 6536 hw = kzalloc(sizeof(*hw), GFP_KERNEL); 6537 if (!hw) 6538 return; 6539 6540 skl_pipe_wm_get_hw_state(crtc, &hw->wm); 6541 6542 skl_pipe_ddb_get_hw_state(crtc, hw->ddb, hw->ddb_y); 6543 6544 hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv); 6545 6546 if (DISPLAY_VER(dev_priv) >= 11 && 6547 hw_enabled_slices != dev_priv->dbuf.enabled_slices) 6548 drm_err(&dev_priv->drm, 6549 "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n", 6550 dev_priv->dbuf.enabled_slices, 6551 hw_enabled_slices); 6552 6553 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 6554 const struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; 6555 const struct skl_wm_level *hw_wm_level, *sw_wm_level; 6556 6557 /* Watermarks */ 6558 for (level = 0; level <= max_level; level++) { 6559 hw_wm_level = &hw->wm.planes[plane->id].wm[level]; 6560 sw_wm_level = skl_plane_wm_level(sw_wm, plane->id, level); 6561 6562 if (skl_wm_level_equals(hw_wm_level, sw_wm_level)) 6563 continue; 6564 6565 drm_err(&dev_priv->drm, 6566 "[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 6567 plane->base.base.id, plane->base.name, level, 6568 sw_wm_level->enable, 6569 sw_wm_level->blocks, 6570 sw_wm_level->lines, 6571 hw_wm_level->enable, 6572 hw_wm_level->blocks, 6573 hw_wm_level->lines); 6574 } 6575 6576 hw_wm_level = &hw->wm.planes[plane->id].trans_wm; 6577 sw_wm_level = skl_plane_trans_wm(sw_wm, plane->id); 6578 6579 if (!skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 6580 drm_err(&dev_priv->drm, 6581 "[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 6582 plane->base.base.id, plane->base.name, 6583 sw_wm_level->enable, 6584 sw_wm_level->blocks, 6585 sw_wm_level->lines, 6586 hw_wm_level->enable, 6587 hw_wm_level->blocks, 6588 hw_wm_level->lines); 6589 } 6590 6591 hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0; 6592 sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0; 6593 6594 if (HAS_HW_SAGV_WM(dev_priv) && 6595 !skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 6596 drm_err(&dev_priv->drm, 6597 "[PLANE:%d:%s] mismatch in SAGV WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 6598 plane->base.base.id, plane->base.name, 6599 sw_wm_level->enable, 6600 sw_wm_level->blocks, 6601 sw_wm_level->lines, 6602 hw_wm_level->enable, 6603 hw_wm_level->blocks, 6604 hw_wm_level->lines); 6605 } 6606 6607 hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm; 6608 sw_wm_level = &sw_wm->planes[plane->id].sagv.trans_wm; 6609 6610 if (HAS_HW_SAGV_WM(dev_priv) && 6611 !skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 6612 drm_err(&dev_priv->drm, 6613 "[PLANE:%d:%s] mismatch in SAGV trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 6614 plane->base.base.id, plane->base.name, 6615 sw_wm_level->enable, 6616 sw_wm_level->blocks, 6617 sw_wm_level->lines, 6618 hw_wm_level->enable, 6619 hw_wm_level->blocks, 6620 hw_wm_level->lines); 6621 } 6622 6623 /* DDB */ 6624 hw_ddb_entry = &hw->ddb[PLANE_CURSOR]; 6625 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[PLANE_CURSOR]; 6626 6627 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { 6628 drm_err(&dev_priv->drm, 6629 "[PLANE:%d:%s] mismatch in DDB (expected (%u,%u), found (%u,%u))\n", 6630 plane->base.base.id, plane->base.name, 6631 sw_ddb_entry->start, sw_ddb_entry->end, 6632 hw_ddb_entry->start, hw_ddb_entry->end); 6633 } 6634 } 6635 6636 kfree(hw); 6637 } 6638 6639 static void 6640 verify_connector_state(struct intel_atomic_state *state, 6641 struct intel_crtc *crtc) 6642 { 6643 struct drm_connector *connector; 6644 struct drm_connector_state *new_conn_state; 6645 int i; 6646 6647 for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) { 6648 struct drm_encoder *encoder = connector->encoder; 6649 struct intel_crtc_state *crtc_state = NULL; 6650 6651 if (new_conn_state->crtc != &crtc->base) 6652 continue; 6653 6654 if (crtc) 6655 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6656 6657 intel_connector_verify_state(crtc_state, new_conn_state); 6658 6659 I915_STATE_WARN(new_conn_state->best_encoder != encoder, 6660 "connector's atomic encoder doesn't match legacy encoder\n"); 6661 } 6662 } 6663 6664 static void 6665 verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state) 6666 { 6667 struct intel_encoder *encoder; 6668 struct drm_connector *connector; 6669 struct drm_connector_state *old_conn_state, *new_conn_state; 6670 int i; 6671 6672 for_each_intel_encoder(&dev_priv->drm, encoder) { 6673 bool enabled = false, found = false; 6674 enum pipe pipe; 6675 6676 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n", 6677 encoder->base.base.id, 6678 encoder->base.name); 6679 6680 for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state, 6681 new_conn_state, i) { 6682 if (old_conn_state->best_encoder == &encoder->base) 6683 found = true; 6684 6685 if (new_conn_state->best_encoder != &encoder->base) 6686 continue; 6687 found = enabled = true; 6688 6689 I915_STATE_WARN(new_conn_state->crtc != 6690 encoder->base.crtc, 6691 "connector's crtc doesn't match encoder crtc\n"); 6692 } 6693 6694 if (!found) 6695 continue; 6696 6697 I915_STATE_WARN(!!encoder->base.crtc != enabled, 6698 "encoder's enabled state mismatch " 6699 "(expected %i, found %i)\n", 6700 !!encoder->base.crtc, enabled); 6701 6702 if (!encoder->base.crtc) { 6703 bool active; 6704 6705 active = encoder->get_hw_state(encoder, &pipe); 6706 I915_STATE_WARN(active, 6707 "encoder detached but still enabled on pipe %c.\n", 6708 pipe_name(pipe)); 6709 } 6710 } 6711 } 6712 6713 static void 6714 verify_crtc_state(struct intel_crtc *crtc, 6715 struct intel_crtc_state *old_crtc_state, 6716 struct intel_crtc_state *new_crtc_state) 6717 { 6718 struct drm_device *dev = crtc->base.dev; 6719 struct drm_i915_private *dev_priv = to_i915(dev); 6720 struct intel_encoder *encoder; 6721 struct intel_crtc_state *pipe_config = old_crtc_state; 6722 struct drm_atomic_state *state = old_crtc_state->uapi.state; 6723 struct intel_crtc *master_crtc; 6724 6725 __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi); 6726 intel_crtc_free_hw_state(old_crtc_state); 6727 intel_crtc_state_reset(old_crtc_state, crtc); 6728 old_crtc_state->uapi.state = state; 6729 6730 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id, 6731 crtc->base.name); 6732 6733 pipe_config->hw.enable = new_crtc_state->hw.enable; 6734 6735 intel_crtc_get_pipe_config(pipe_config); 6736 6737 /* we keep both pipes enabled on 830 */ 6738 if (IS_I830(dev_priv) && pipe_config->hw.active) 6739 pipe_config->hw.active = new_crtc_state->hw.active; 6740 6741 I915_STATE_WARN(new_crtc_state->hw.active != pipe_config->hw.active, 6742 "crtc active state doesn't match with hw state " 6743 "(expected %i, found %i)\n", 6744 new_crtc_state->hw.active, pipe_config->hw.active); 6745 6746 I915_STATE_WARN(crtc->active != new_crtc_state->hw.active, 6747 "transitional active state does not match atomic hw state " 6748 "(expected %i, found %i)\n", 6749 new_crtc_state->hw.active, crtc->active); 6750 6751 master_crtc = intel_master_crtc(new_crtc_state); 6752 6753 for_each_encoder_on_crtc(dev, &master_crtc->base, encoder) { 6754 enum pipe pipe; 6755 bool active; 6756 6757 active = encoder->get_hw_state(encoder, &pipe); 6758 I915_STATE_WARN(active != new_crtc_state->hw.active, 6759 "[ENCODER:%i] active %i with crtc active %i\n", 6760 encoder->base.base.id, active, 6761 new_crtc_state->hw.active); 6762 6763 I915_STATE_WARN(active && master_crtc->pipe != pipe, 6764 "Encoder connected to wrong pipe %c\n", 6765 pipe_name(pipe)); 6766 6767 if (active) 6768 intel_encoder_get_config(encoder, pipe_config); 6769 } 6770 6771 if (!new_crtc_state->hw.active) 6772 return; 6773 6774 intel_pipe_config_sanity_check(dev_priv, pipe_config); 6775 6776 if (!intel_pipe_config_compare(new_crtc_state, 6777 pipe_config, false)) { 6778 I915_STATE_WARN(1, "pipe state doesn't match!\n"); 6779 intel_dump_pipe_config(pipe_config, NULL, "[hw state]"); 6780 intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]"); 6781 } 6782 } 6783 6784 static void 6785 intel_verify_planes(struct intel_atomic_state *state) 6786 { 6787 struct intel_plane *plane; 6788 const struct intel_plane_state *plane_state; 6789 int i; 6790 6791 for_each_new_intel_plane_in_state(state, plane, 6792 plane_state, i) 6793 assert_plane(plane, plane_state->planar_slave || 6794 plane_state->uapi.visible); 6795 } 6796 6797 static void 6798 verify_single_dpll_state(struct drm_i915_private *dev_priv, 6799 struct intel_shared_dpll *pll, 6800 struct intel_crtc *crtc, 6801 struct intel_crtc_state *new_crtc_state) 6802 { 6803 struct intel_dpll_hw_state dpll_hw_state; 6804 u8 pipe_mask; 6805 bool active; 6806 6807 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); 6808 6809 drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name); 6810 6811 active = intel_dpll_get_hw_state(dev_priv, pll, &dpll_hw_state); 6812 6813 if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) { 6814 I915_STATE_WARN(!pll->on && pll->active_mask, 6815 "pll in active use but not on in sw tracking\n"); 6816 I915_STATE_WARN(pll->on && !pll->active_mask, 6817 "pll is on but not used by any active pipe\n"); 6818 I915_STATE_WARN(pll->on != active, 6819 "pll on state mismatch (expected %i, found %i)\n", 6820 pll->on, active); 6821 } 6822 6823 if (!crtc) { 6824 I915_STATE_WARN(pll->active_mask & ~pll->state.pipe_mask, 6825 "more active pll users than references: 0x%x vs 0x%x\n", 6826 pll->active_mask, pll->state.pipe_mask); 6827 6828 return; 6829 } 6830 6831 pipe_mask = BIT(crtc->pipe); 6832 6833 if (new_crtc_state->hw.active) 6834 I915_STATE_WARN(!(pll->active_mask & pipe_mask), 6835 "pll active mismatch (expected pipe %c in active mask 0x%x)\n", 6836 pipe_name(crtc->pipe), pll->active_mask); 6837 else 6838 I915_STATE_WARN(pll->active_mask & pipe_mask, 6839 "pll active mismatch (didn't expect pipe %c in active mask 0x%x)\n", 6840 pipe_name(crtc->pipe), pll->active_mask); 6841 6842 I915_STATE_WARN(!(pll->state.pipe_mask & pipe_mask), 6843 "pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n", 6844 pipe_mask, pll->state.pipe_mask); 6845 6846 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state, 6847 &dpll_hw_state, 6848 sizeof(dpll_hw_state)), 6849 "pll hw state mismatch\n"); 6850 } 6851 6852 static void 6853 verify_shared_dpll_state(struct intel_crtc *crtc, 6854 struct intel_crtc_state *old_crtc_state, 6855 struct intel_crtc_state *new_crtc_state) 6856 { 6857 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6858 6859 if (new_crtc_state->shared_dpll) 6860 verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state); 6861 6862 if (old_crtc_state->shared_dpll && 6863 old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) { 6864 u8 pipe_mask = BIT(crtc->pipe); 6865 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll; 6866 6867 I915_STATE_WARN(pll->active_mask & pipe_mask, 6868 "pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n", 6869 pipe_name(crtc->pipe), pll->active_mask); 6870 I915_STATE_WARN(pll->state.pipe_mask & pipe_mask, 6871 "pll enabled crtcs mismatch (found %x in enabled mask (0x%x))\n", 6872 pipe_name(crtc->pipe), pll->state.pipe_mask); 6873 } 6874 } 6875 6876 static void 6877 verify_mpllb_state(struct intel_atomic_state *state, 6878 struct intel_crtc_state *new_crtc_state) 6879 { 6880 struct drm_i915_private *i915 = to_i915(state->base.dev); 6881 struct intel_mpllb_state mpllb_hw_state = { 0 }; 6882 struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->mpllb_state; 6883 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 6884 struct intel_encoder *encoder; 6885 6886 if (!IS_DG2(i915)) 6887 return; 6888 6889 if (!new_crtc_state->hw.active) 6890 return; 6891 6892 encoder = intel_get_crtc_new_encoder(state, new_crtc_state); 6893 intel_mpllb_readout_hw_state(encoder, &mpllb_hw_state); 6894 6895 #define MPLLB_CHECK(name) do { \ 6896 if (mpllb_sw_state->name != mpllb_hw_state.name) { \ 6897 pipe_config_mismatch(false, crtc, "MPLLB:" __stringify(name), \ 6898 "(expected 0x%08x, found 0x%08x)", \ 6899 mpllb_sw_state->name, \ 6900 mpllb_hw_state.name); \ 6901 } \ 6902 } while (0) 6903 6904 MPLLB_CHECK(mpllb_cp); 6905 MPLLB_CHECK(mpllb_div); 6906 MPLLB_CHECK(mpllb_div2); 6907 MPLLB_CHECK(mpllb_fracn1); 6908 MPLLB_CHECK(mpllb_fracn2); 6909 MPLLB_CHECK(mpllb_sscen); 6910 MPLLB_CHECK(mpllb_sscstep); 6911 6912 /* 6913 * ref_control is handled by the hardware/firemware and never 6914 * programmed by the software, but the proper values are supplied 6915 * in the bspec for verification purposes. 6916 */ 6917 MPLLB_CHECK(ref_control); 6918 6919 #undef MPLLB_CHECK 6920 } 6921 6922 static void 6923 intel_modeset_verify_crtc(struct intel_crtc *crtc, 6924 struct intel_atomic_state *state, 6925 struct intel_crtc_state *old_crtc_state, 6926 struct intel_crtc_state *new_crtc_state) 6927 { 6928 if (!intel_crtc_needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe) 6929 return; 6930 6931 verify_wm_state(crtc, new_crtc_state); 6932 verify_connector_state(state, crtc); 6933 verify_crtc_state(crtc, old_crtc_state, new_crtc_state); 6934 verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state); 6935 verify_mpllb_state(state, new_crtc_state); 6936 } 6937 6938 static void 6939 verify_disabled_dpll_state(struct drm_i915_private *dev_priv) 6940 { 6941 int i; 6942 6943 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) 6944 verify_single_dpll_state(dev_priv, 6945 &dev_priv->dpll.shared_dplls[i], 6946 NULL, NULL); 6947 } 6948 6949 static void 6950 intel_modeset_verify_disabled(struct drm_i915_private *dev_priv, 6951 struct intel_atomic_state *state) 6952 { 6953 verify_encoder_state(dev_priv, state); 6954 verify_connector_state(state, NULL); 6955 verify_disabled_dpll_state(dev_priv); 6956 } 6957 6958 int intel_modeset_all_pipes(struct intel_atomic_state *state) 6959 { 6960 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6961 struct intel_crtc *crtc; 6962 6963 /* 6964 * Add all pipes to the state, and force 6965 * a modeset on all the active ones. 6966 */ 6967 for_each_intel_crtc(&dev_priv->drm, crtc) { 6968 struct intel_crtc_state *crtc_state; 6969 int ret; 6970 6971 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6972 if (IS_ERR(crtc_state)) 6973 return PTR_ERR(crtc_state); 6974 6975 if (!crtc_state->hw.active || 6976 drm_atomic_crtc_needs_modeset(&crtc_state->uapi)) 6977 continue; 6978 6979 crtc_state->uapi.mode_changed = true; 6980 6981 ret = drm_atomic_add_affected_connectors(&state->base, 6982 &crtc->base); 6983 if (ret) 6984 return ret; 6985 6986 ret = intel_atomic_add_affected_planes(state, crtc); 6987 if (ret) 6988 return ret; 6989 6990 crtc_state->update_planes |= crtc_state->active_planes; 6991 } 6992 6993 return 0; 6994 } 6995 6996 static void 6997 intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state) 6998 { 6999 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 7000 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 7001 struct drm_display_mode adjusted_mode = 7002 crtc_state->hw.adjusted_mode; 7003 7004 if (crtc_state->vrr.enable) { 7005 adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax; 7006 adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax; 7007 adjusted_mode.crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state); 7008 crtc->vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state); 7009 } 7010 7011 drm_calc_timestamping_constants(&crtc->base, &adjusted_mode); 7012 7013 crtc->mode_flags = crtc_state->mode_flags; 7014 7015 /* 7016 * The scanline counter increments at the leading edge of hsync. 7017 * 7018 * On most platforms it starts counting from vtotal-1 on the 7019 * first active line. That means the scanline counter value is 7020 * always one less than what we would expect. Ie. just after 7021 * start of vblank, which also occurs at start of hsync (on the 7022 * last active line), the scanline counter will read vblank_start-1. 7023 * 7024 * On gen2 the scanline counter starts counting from 1 instead 7025 * of vtotal-1, so we have to subtract one (or rather add vtotal-1 7026 * to keep the value positive), instead of adding one. 7027 * 7028 * On HSW+ the behaviour of the scanline counter depends on the output 7029 * type. For DP ports it behaves like most other platforms, but on HDMI 7030 * there's an extra 1 line difference. So we need to add two instead of 7031 * one to the value. 7032 * 7033 * On VLV/CHV DSI the scanline counter would appear to increment 7034 * approx. 1/3 of a scanline before start of vblank. Unfortunately 7035 * that means we can't tell whether we're in vblank or not while 7036 * we're on that particular line. We must still set scanline_offset 7037 * to 1 so that the vblank timestamps come out correct when we query 7038 * the scanline counter from within the vblank interrupt handler. 7039 * However if queried just before the start of vblank we'll get an 7040 * answer that's slightly in the future. 7041 */ 7042 if (DISPLAY_VER(dev_priv) == 2) { 7043 int vtotal; 7044 7045 vtotal = adjusted_mode.crtc_vtotal; 7046 if (adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 7047 vtotal /= 2; 7048 7049 crtc->scanline_offset = vtotal - 1; 7050 } else if (HAS_DDI(dev_priv) && 7051 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 7052 crtc->scanline_offset = 2; 7053 } else { 7054 crtc->scanline_offset = 1; 7055 } 7056 } 7057 7058 static void intel_modeset_clear_plls(struct intel_atomic_state *state) 7059 { 7060 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7061 struct intel_crtc_state *new_crtc_state; 7062 struct intel_crtc *crtc; 7063 int i; 7064 7065 if (!dev_priv->dpll_funcs) 7066 return; 7067 7068 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7069 if (!intel_crtc_needs_modeset(new_crtc_state)) 7070 continue; 7071 7072 intel_release_shared_dplls(state, crtc); 7073 } 7074 } 7075 7076 /* 7077 * This implements the workaround described in the "notes" section of the mode 7078 * set sequence documentation. When going from no pipes or single pipe to 7079 * multiple pipes, and planes are enabled after the pipe, we need to wait at 7080 * least 2 vblanks on the first pipe before enabling planes on the second pipe. 7081 */ 7082 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state) 7083 { 7084 struct intel_crtc_state *crtc_state; 7085 struct intel_crtc *crtc; 7086 struct intel_crtc_state *first_crtc_state = NULL; 7087 struct intel_crtc_state *other_crtc_state = NULL; 7088 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; 7089 int i; 7090 7091 /* look at all crtc's that are going to be enabled in during modeset */ 7092 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7093 if (!crtc_state->hw.active || 7094 !intel_crtc_needs_modeset(crtc_state)) 7095 continue; 7096 7097 if (first_crtc_state) { 7098 other_crtc_state = crtc_state; 7099 break; 7100 } else { 7101 first_crtc_state = crtc_state; 7102 first_pipe = crtc->pipe; 7103 } 7104 } 7105 7106 /* No workaround needed? */ 7107 if (!first_crtc_state) 7108 return 0; 7109 7110 /* w/a possibly needed, check how many crtc's are already enabled. */ 7111 for_each_intel_crtc(state->base.dev, crtc) { 7112 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 7113 if (IS_ERR(crtc_state)) 7114 return PTR_ERR(crtc_state); 7115 7116 crtc_state->hsw_workaround_pipe = INVALID_PIPE; 7117 7118 if (!crtc_state->hw.active || 7119 intel_crtc_needs_modeset(crtc_state)) 7120 continue; 7121 7122 /* 2 or more enabled crtcs means no need for w/a */ 7123 if (enabled_pipe != INVALID_PIPE) 7124 return 0; 7125 7126 enabled_pipe = crtc->pipe; 7127 } 7128 7129 if (enabled_pipe != INVALID_PIPE) 7130 first_crtc_state->hsw_workaround_pipe = enabled_pipe; 7131 else if (other_crtc_state) 7132 other_crtc_state->hsw_workaround_pipe = first_pipe; 7133 7134 return 0; 7135 } 7136 7137 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 7138 u8 active_pipes) 7139 { 7140 const struct intel_crtc_state *crtc_state; 7141 struct intel_crtc *crtc; 7142 int i; 7143 7144 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7145 if (crtc_state->hw.active) 7146 active_pipes |= BIT(crtc->pipe); 7147 else 7148 active_pipes &= ~BIT(crtc->pipe); 7149 } 7150 7151 return active_pipes; 7152 } 7153 7154 static int intel_modeset_checks(struct intel_atomic_state *state) 7155 { 7156 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7157 7158 state->modeset = true; 7159 7160 if (IS_HASWELL(dev_priv)) 7161 return hsw_mode_set_planes_workaround(state); 7162 7163 return 0; 7164 } 7165 7166 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state, 7167 struct intel_crtc_state *new_crtc_state) 7168 { 7169 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) 7170 return; 7171 7172 new_crtc_state->uapi.mode_changed = false; 7173 new_crtc_state->update_pipe = true; 7174 } 7175 7176 static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state, 7177 struct intel_crtc_state *new_crtc_state) 7178 { 7179 /* 7180 * If we're not doing the full modeset we want to 7181 * keep the current M/N values as they may be 7182 * sufficiently different to the computed values 7183 * to cause problems. 7184 * 7185 * FIXME: should really copy more fuzzy state here 7186 */ 7187 new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n; 7188 new_crtc_state->dp_m_n = old_crtc_state->dp_m_n; 7189 new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2; 7190 new_crtc_state->has_drrs = old_crtc_state->has_drrs; 7191 } 7192 7193 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state, 7194 struct intel_crtc *crtc, 7195 u8 plane_ids_mask) 7196 { 7197 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7198 struct intel_plane *plane; 7199 7200 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 7201 struct intel_plane_state *plane_state; 7202 7203 if ((plane_ids_mask & BIT(plane->id)) == 0) 7204 continue; 7205 7206 plane_state = intel_atomic_get_plane_state(state, plane); 7207 if (IS_ERR(plane_state)) 7208 return PTR_ERR(plane_state); 7209 } 7210 7211 return 0; 7212 } 7213 7214 int intel_atomic_add_affected_planes(struct intel_atomic_state *state, 7215 struct intel_crtc *crtc) 7216 { 7217 const struct intel_crtc_state *old_crtc_state = 7218 intel_atomic_get_old_crtc_state(state, crtc); 7219 const struct intel_crtc_state *new_crtc_state = 7220 intel_atomic_get_new_crtc_state(state, crtc); 7221 7222 return intel_crtc_add_planes_to_state(state, crtc, 7223 old_crtc_state->enabled_planes | 7224 new_crtc_state->enabled_planes); 7225 } 7226 7227 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv) 7228 { 7229 /* See {hsw,vlv,ivb}_plane_ratio() */ 7230 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) || 7231 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) || 7232 IS_IVYBRIDGE(dev_priv); 7233 } 7234 7235 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state, 7236 struct intel_crtc *crtc, 7237 struct intel_crtc *other) 7238 { 7239 const struct intel_plane_state *plane_state; 7240 struct intel_plane *plane; 7241 u8 plane_ids = 0; 7242 int i; 7243 7244 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 7245 if (plane->pipe == crtc->pipe) 7246 plane_ids |= BIT(plane->id); 7247 } 7248 7249 return intel_crtc_add_planes_to_state(state, other, plane_ids); 7250 } 7251 7252 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state) 7253 { 7254 struct drm_i915_private *i915 = to_i915(state->base.dev); 7255 const struct intel_crtc_state *crtc_state; 7256 struct intel_crtc *crtc; 7257 int i; 7258 7259 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7260 struct intel_crtc *other; 7261 7262 for_each_intel_crtc_in_pipe_mask(&i915->drm, other, 7263 crtc_state->bigjoiner_pipes) { 7264 int ret; 7265 7266 if (crtc == other) 7267 continue; 7268 7269 ret = intel_crtc_add_bigjoiner_planes(state, crtc, other); 7270 if (ret) 7271 return ret; 7272 } 7273 } 7274 7275 return 0; 7276 } 7277 7278 static int intel_atomic_check_planes(struct intel_atomic_state *state) 7279 { 7280 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7281 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7282 struct intel_plane_state *plane_state; 7283 struct intel_plane *plane; 7284 struct intel_crtc *crtc; 7285 int i, ret; 7286 7287 ret = icl_add_linked_planes(state); 7288 if (ret) 7289 return ret; 7290 7291 ret = intel_bigjoiner_add_affected_planes(state); 7292 if (ret) 7293 return ret; 7294 7295 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 7296 ret = intel_plane_atomic_check(state, plane); 7297 if (ret) { 7298 drm_dbg_atomic(&dev_priv->drm, 7299 "[PLANE:%d:%s] atomic driver check failed\n", 7300 plane->base.base.id, plane->base.name); 7301 return ret; 7302 } 7303 } 7304 7305 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7306 new_crtc_state, i) { 7307 u8 old_active_planes, new_active_planes; 7308 7309 ret = icl_check_nv12_planes(new_crtc_state); 7310 if (ret) 7311 return ret; 7312 7313 /* 7314 * On some platforms the number of active planes affects 7315 * the planes' minimum cdclk calculation. Add such planes 7316 * to the state before we compute the minimum cdclk. 7317 */ 7318 if (!active_planes_affects_min_cdclk(dev_priv)) 7319 continue; 7320 7321 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 7322 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 7323 7324 if (hweight8(old_active_planes) == hweight8(new_active_planes)) 7325 continue; 7326 7327 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes); 7328 if (ret) 7329 return ret; 7330 } 7331 7332 return 0; 7333 } 7334 7335 static int intel_atomic_check_crtcs(struct intel_atomic_state *state) 7336 { 7337 struct intel_crtc_state *crtc_state; 7338 struct intel_crtc *crtc; 7339 int i; 7340 7341 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7342 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 7343 int ret; 7344 7345 ret = intel_crtc_atomic_check(state, crtc); 7346 if (ret) { 7347 drm_dbg_atomic(&i915->drm, 7348 "[CRTC:%d:%s] atomic driver check failed\n", 7349 crtc->base.base.id, crtc->base.name); 7350 return ret; 7351 } 7352 } 7353 7354 return 0; 7355 } 7356 7357 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, 7358 u8 transcoders) 7359 { 7360 const struct intel_crtc_state *new_crtc_state; 7361 struct intel_crtc *crtc; 7362 int i; 7363 7364 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7365 if (new_crtc_state->hw.enable && 7366 transcoders & BIT(new_crtc_state->cpu_transcoder) && 7367 intel_crtc_needs_modeset(new_crtc_state)) 7368 return true; 7369 } 7370 7371 return false; 7372 } 7373 7374 static bool intel_pipes_need_modeset(struct intel_atomic_state *state, 7375 u8 pipes) 7376 { 7377 const struct intel_crtc_state *new_crtc_state; 7378 struct intel_crtc *crtc; 7379 int i; 7380 7381 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7382 if (new_crtc_state->hw.enable && 7383 pipes & BIT(crtc->pipe) && 7384 intel_crtc_needs_modeset(new_crtc_state)) 7385 return true; 7386 } 7387 7388 return false; 7389 } 7390 7391 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state, 7392 struct intel_crtc *master_crtc) 7393 { 7394 struct drm_i915_private *i915 = to_i915(state->base.dev); 7395 struct intel_crtc_state *master_crtc_state = 7396 intel_atomic_get_new_crtc_state(state, master_crtc); 7397 struct intel_crtc *slave_crtc; 7398 7399 if (!master_crtc_state->bigjoiner_pipes) 7400 return 0; 7401 7402 /* sanity check */ 7403 if (drm_WARN_ON(&i915->drm, 7404 master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state))) 7405 return -EINVAL; 7406 7407 if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) { 7408 drm_dbg_kms(&i915->drm, 7409 "[CRTC:%d:%s] Cannot act as big joiner master " 7410 "(need 0x%x as pipes, only 0x%x possible)\n", 7411 master_crtc->base.base.id, master_crtc->base.name, 7412 master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915)); 7413 return -EINVAL; 7414 } 7415 7416 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 7417 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 7418 struct intel_crtc_state *slave_crtc_state; 7419 int ret; 7420 7421 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc); 7422 if (IS_ERR(slave_crtc_state)) 7423 return PTR_ERR(slave_crtc_state); 7424 7425 /* master being enabled, slave was already configured? */ 7426 if (slave_crtc_state->uapi.enable) { 7427 drm_dbg_kms(&i915->drm, 7428 "[CRTC:%d:%s] Slave is enabled as normal CRTC, but " 7429 "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n", 7430 slave_crtc->base.base.id, slave_crtc->base.name, 7431 master_crtc->base.base.id, master_crtc->base.name); 7432 return -EINVAL; 7433 } 7434 7435 /* 7436 * The state copy logic assumes the master crtc gets processed 7437 * before the slave crtc during the main compute_config loop. 7438 * This works because the crtcs are created in pipe order, 7439 * and the hardware requires master pipe < slave pipe as well. 7440 * Should that change we need to rethink the logic. 7441 */ 7442 if (WARN_ON(drm_crtc_index(&master_crtc->base) > 7443 drm_crtc_index(&slave_crtc->base))) 7444 return -EINVAL; 7445 7446 drm_dbg_kms(&i915->drm, 7447 "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n", 7448 slave_crtc->base.base.id, slave_crtc->base.name, 7449 master_crtc->base.base.id, master_crtc->base.name); 7450 7451 slave_crtc_state->bigjoiner_pipes = 7452 master_crtc_state->bigjoiner_pipes; 7453 7454 ret = copy_bigjoiner_crtc_state_modeset(state, slave_crtc); 7455 if (ret) 7456 return ret; 7457 } 7458 7459 return 0; 7460 } 7461 7462 static void kill_bigjoiner_slave(struct intel_atomic_state *state, 7463 struct intel_crtc *master_crtc) 7464 { 7465 struct drm_i915_private *i915 = to_i915(state->base.dev); 7466 struct intel_crtc_state *master_crtc_state = 7467 intel_atomic_get_new_crtc_state(state, master_crtc); 7468 struct intel_crtc *slave_crtc; 7469 7470 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 7471 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 7472 struct intel_crtc_state *slave_crtc_state = 7473 intel_atomic_get_new_crtc_state(state, slave_crtc); 7474 7475 slave_crtc_state->bigjoiner_pipes = 0; 7476 7477 intel_crtc_copy_uapi_to_hw_state_modeset(state, slave_crtc); 7478 } 7479 7480 master_crtc_state->bigjoiner_pipes = 0; 7481 } 7482 7483 /** 7484 * DOC: asynchronous flip implementation 7485 * 7486 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC 7487 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL. 7488 * Correspondingly, support is currently added for primary plane only. 7489 * 7490 * Async flip can only change the plane surface address, so anything else 7491 * changing is rejected from the intel_async_flip_check_hw() function. 7492 * Once this check is cleared, flip done interrupt is enabled using 7493 * the intel_crtc_enable_flip_done() function. 7494 * 7495 * As soon as the surface address register is written, flip done interrupt is 7496 * generated and the requested events are sent to the usersapce in the interrupt 7497 * handler itself. The timestamp and sequence sent during the flip done event 7498 * correspond to the last vblank and have no relation to the actual time when 7499 * the flip done event was sent. 7500 */ 7501 static int intel_async_flip_check_uapi(struct intel_atomic_state *state, 7502 struct intel_crtc *crtc) 7503 { 7504 struct drm_i915_private *i915 = to_i915(state->base.dev); 7505 const struct intel_crtc_state *new_crtc_state = 7506 intel_atomic_get_new_crtc_state(state, crtc); 7507 const struct intel_plane_state *old_plane_state; 7508 struct intel_plane_state *new_plane_state; 7509 struct intel_plane *plane; 7510 int i; 7511 7512 if (!new_crtc_state->uapi.async_flip) 7513 return 0; 7514 7515 if (!new_crtc_state->uapi.active) { 7516 drm_dbg_kms(&i915->drm, 7517 "[CRTC:%d:%s] not active\n", 7518 crtc->base.base.id, crtc->base.name); 7519 return -EINVAL; 7520 } 7521 7522 if (intel_crtc_needs_modeset(new_crtc_state)) { 7523 drm_dbg_kms(&i915->drm, 7524 "[CRTC:%d:%s] modeset required\n", 7525 crtc->base.base.id, crtc->base.name); 7526 return -EINVAL; 7527 } 7528 7529 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 7530 new_plane_state, i) { 7531 if (plane->pipe != crtc->pipe) 7532 continue; 7533 7534 /* 7535 * TODO: Async flip is only supported through the page flip IOCTL 7536 * as of now. So support currently added for primary plane only. 7537 * Support for other planes on platforms on which supports 7538 * this(vlv/chv and icl+) should be added when async flip is 7539 * enabled in the atomic IOCTL path. 7540 */ 7541 if (!plane->async_flip) { 7542 drm_dbg_kms(&i915->drm, 7543 "[PLANE:%d:%s] async flip not supported\n", 7544 plane->base.base.id, plane->base.name); 7545 return -EINVAL; 7546 } 7547 7548 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) { 7549 drm_dbg_kms(&i915->drm, 7550 "[PLANE:%d:%s] no old or new framebuffer\n", 7551 plane->base.base.id, plane->base.name); 7552 return -EINVAL; 7553 } 7554 } 7555 7556 return 0; 7557 } 7558 7559 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc) 7560 { 7561 struct drm_i915_private *i915 = to_i915(state->base.dev); 7562 const struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7563 const struct intel_plane_state *new_plane_state, *old_plane_state; 7564 struct intel_plane *plane; 7565 int i; 7566 7567 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 7568 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 7569 7570 if (!new_crtc_state->uapi.async_flip) 7571 return 0; 7572 7573 if (!new_crtc_state->hw.active) { 7574 drm_dbg_kms(&i915->drm, 7575 "[CRTC:%d:%s] not active\n", 7576 crtc->base.base.id, crtc->base.name); 7577 return -EINVAL; 7578 } 7579 7580 if (intel_crtc_needs_modeset(new_crtc_state)) { 7581 drm_dbg_kms(&i915->drm, 7582 "[CRTC:%d:%s] modeset required\n", 7583 crtc->base.base.id, crtc->base.name); 7584 return -EINVAL; 7585 } 7586 7587 if (old_crtc_state->active_planes != new_crtc_state->active_planes) { 7588 drm_dbg_kms(&i915->drm, 7589 "[CRTC:%d:%s] Active planes cannot be in async flip\n", 7590 crtc->base.base.id, crtc->base.name); 7591 return -EINVAL; 7592 } 7593 7594 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 7595 new_plane_state, i) { 7596 if (plane->pipe != crtc->pipe) 7597 continue; 7598 7599 /* 7600 * Only async flip capable planes should be in the state 7601 * if we're really about to ask the hardware to perform 7602 * an async flip. We should never get this far otherwise. 7603 */ 7604 if (drm_WARN_ON(&i915->drm, 7605 new_crtc_state->do_async_flip && !plane->async_flip)) 7606 return -EINVAL; 7607 7608 /* 7609 * Only check async flip capable planes other planes 7610 * may be involved in the initial commit due to 7611 * the wm0/ddb optimization. 7612 * 7613 * TODO maybe should track which planes actually 7614 * were requested to do the async flip... 7615 */ 7616 if (!plane->async_flip) 7617 continue; 7618 7619 /* 7620 * FIXME: This check is kept generic for all platforms. 7621 * Need to verify this for all gen9 platforms to enable 7622 * this selectively if required. 7623 */ 7624 switch (new_plane_state->hw.fb->modifier) { 7625 case I915_FORMAT_MOD_X_TILED: 7626 case I915_FORMAT_MOD_Y_TILED: 7627 case I915_FORMAT_MOD_Yf_TILED: 7628 case I915_FORMAT_MOD_4_TILED: 7629 break; 7630 default: 7631 drm_dbg_kms(&i915->drm, 7632 "[PLANE:%d:%s] Modifier does not support async flips\n", 7633 plane->base.base.id, plane->base.name); 7634 return -EINVAL; 7635 } 7636 7637 if (new_plane_state->hw.fb->format->num_planes > 1) { 7638 drm_dbg_kms(&i915->drm, 7639 "[PLANE:%d:%s] Planar formats do not support async flips\n", 7640 plane->base.base.id, plane->base.name); 7641 return -EINVAL; 7642 } 7643 7644 if (old_plane_state->view.color_plane[0].mapping_stride != 7645 new_plane_state->view.color_plane[0].mapping_stride) { 7646 drm_dbg_kms(&i915->drm, 7647 "[PLANE:%d:%s] Stride cannot be changed in async flip\n", 7648 plane->base.base.id, plane->base.name); 7649 return -EINVAL; 7650 } 7651 7652 if (old_plane_state->hw.fb->modifier != 7653 new_plane_state->hw.fb->modifier) { 7654 drm_dbg_kms(&i915->drm, 7655 "[PLANE:%d:%s] Modifier cannot be changed in async flip\n", 7656 plane->base.base.id, plane->base.name); 7657 return -EINVAL; 7658 } 7659 7660 if (old_plane_state->hw.fb->format != 7661 new_plane_state->hw.fb->format) { 7662 drm_dbg_kms(&i915->drm, 7663 "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n", 7664 plane->base.base.id, plane->base.name); 7665 return -EINVAL; 7666 } 7667 7668 if (old_plane_state->hw.rotation != 7669 new_plane_state->hw.rotation) { 7670 drm_dbg_kms(&i915->drm, 7671 "[PLANE:%d:%s] Rotation cannot be changed in async flip\n", 7672 plane->base.base.id, plane->base.name); 7673 return -EINVAL; 7674 } 7675 7676 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) || 7677 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) { 7678 drm_dbg_kms(&i915->drm, 7679 "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n", 7680 plane->base.base.id, plane->base.name); 7681 return -EINVAL; 7682 } 7683 7684 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) { 7685 drm_dbg_kms(&i915->drm, 7686 "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n", 7687 plane->base.base.id, plane->base.name); 7688 return -EINVAL; 7689 } 7690 7691 if (old_plane_state->hw.pixel_blend_mode != 7692 new_plane_state->hw.pixel_blend_mode) { 7693 drm_dbg_kms(&i915->drm, 7694 "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n", 7695 plane->base.base.id, plane->base.name); 7696 return -EINVAL; 7697 } 7698 7699 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) { 7700 drm_dbg_kms(&i915->drm, 7701 "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n", 7702 plane->base.base.id, plane->base.name); 7703 return -EINVAL; 7704 } 7705 7706 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) { 7707 drm_dbg_kms(&i915->drm, 7708 "[PLANE:%d:%s] Color range cannot be changed in async flip\n", 7709 plane->base.base.id, plane->base.name); 7710 return -EINVAL; 7711 } 7712 7713 /* plane decryption is allow to change only in synchronous flips */ 7714 if (old_plane_state->decrypt != new_plane_state->decrypt) { 7715 drm_dbg_kms(&i915->drm, 7716 "[PLANE:%d:%s] Decryption cannot be changed in async flip\n", 7717 plane->base.base.id, plane->base.name); 7718 return -EINVAL; 7719 } 7720 } 7721 7722 return 0; 7723 } 7724 7725 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state) 7726 { 7727 struct drm_i915_private *i915 = to_i915(state->base.dev); 7728 struct intel_crtc_state *crtc_state; 7729 struct intel_crtc *crtc; 7730 u8 affected_pipes = 0; 7731 u8 modeset_pipes = 0; 7732 int i; 7733 7734 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7735 affected_pipes |= crtc_state->bigjoiner_pipes; 7736 if (intel_crtc_needs_modeset(crtc_state)) 7737 modeset_pipes |= crtc_state->bigjoiner_pipes; 7738 } 7739 7740 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) { 7741 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 7742 if (IS_ERR(crtc_state)) 7743 return PTR_ERR(crtc_state); 7744 } 7745 7746 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) { 7747 int ret; 7748 7749 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 7750 7751 crtc_state->uapi.mode_changed = true; 7752 7753 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); 7754 if (ret) 7755 return ret; 7756 7757 ret = intel_atomic_add_affected_planes(state, crtc); 7758 if (ret) 7759 return ret; 7760 } 7761 7762 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7763 /* Kill old bigjoiner link, we may re-establish afterwards */ 7764 if (intel_crtc_needs_modeset(crtc_state) && 7765 intel_crtc_is_bigjoiner_master(crtc_state)) 7766 kill_bigjoiner_slave(state, crtc); 7767 } 7768 7769 return 0; 7770 } 7771 7772 /** 7773 * intel_atomic_check - validate state object 7774 * @dev: drm device 7775 * @_state: state to validate 7776 */ 7777 static int intel_atomic_check(struct drm_device *dev, 7778 struct drm_atomic_state *_state) 7779 { 7780 struct drm_i915_private *dev_priv = to_i915(dev); 7781 struct intel_atomic_state *state = to_intel_atomic_state(_state); 7782 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7783 struct intel_crtc *crtc; 7784 int ret, i; 7785 bool any_ms = false; 7786 7787 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7788 new_crtc_state, i) { 7789 if (new_crtc_state->inherited != old_crtc_state->inherited) 7790 new_crtc_state->uapi.mode_changed = true; 7791 7792 if (new_crtc_state->uapi.scaling_filter != 7793 old_crtc_state->uapi.scaling_filter) 7794 new_crtc_state->uapi.mode_changed = true; 7795 } 7796 7797 intel_vrr_check_modeset(state); 7798 7799 ret = drm_atomic_helper_check_modeset(dev, &state->base); 7800 if (ret) 7801 goto fail; 7802 7803 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7804 ret = intel_async_flip_check_uapi(state, crtc); 7805 if (ret) 7806 return ret; 7807 } 7808 7809 ret = intel_bigjoiner_add_affected_crtcs(state); 7810 if (ret) 7811 goto fail; 7812 7813 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7814 new_crtc_state, i) { 7815 if (!intel_crtc_needs_modeset(new_crtc_state)) { 7816 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 7817 copy_bigjoiner_crtc_state_nomodeset(state, crtc); 7818 else 7819 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 7820 continue; 7821 } 7822 7823 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) { 7824 drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable); 7825 continue; 7826 } 7827 7828 ret = intel_crtc_prepare_cleared_state(state, crtc); 7829 if (ret) 7830 goto fail; 7831 7832 if (!new_crtc_state->hw.enable) 7833 continue; 7834 7835 ret = intel_modeset_pipe_config(state, new_crtc_state); 7836 if (ret) 7837 goto fail; 7838 7839 ret = intel_atomic_check_bigjoiner(state, crtc); 7840 if (ret) 7841 goto fail; 7842 } 7843 7844 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7845 new_crtc_state, i) { 7846 if (!intel_crtc_needs_modeset(new_crtc_state)) 7847 continue; 7848 7849 ret = intel_modeset_pipe_config_late(new_crtc_state); 7850 if (ret) 7851 goto fail; 7852 7853 intel_crtc_check_fastset(old_crtc_state, new_crtc_state); 7854 } 7855 7856 /** 7857 * Check if fastset is allowed by external dependencies like other 7858 * pipes and transcoders. 7859 * 7860 * Right now it only forces a fullmodeset when the MST master 7861 * transcoder did not changed but the pipe of the master transcoder 7862 * needs a fullmodeset so all slaves also needs to do a fullmodeset or 7863 * in case of port synced crtcs, if one of the synced crtcs 7864 * needs a full modeset, all other synced crtcs should be 7865 * forced a full modeset. 7866 */ 7867 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7868 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state)) 7869 continue; 7870 7871 if (intel_dp_mst_is_slave_trans(new_crtc_state)) { 7872 enum transcoder master = new_crtc_state->mst_master_transcoder; 7873 7874 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) { 7875 new_crtc_state->uapi.mode_changed = true; 7876 new_crtc_state->update_pipe = false; 7877 } 7878 } 7879 7880 if (is_trans_port_sync_mode(new_crtc_state)) { 7881 u8 trans = new_crtc_state->sync_mode_slaves_mask; 7882 7883 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER) 7884 trans |= BIT(new_crtc_state->master_transcoder); 7885 7886 if (intel_cpu_transcoders_need_modeset(state, trans)) { 7887 new_crtc_state->uapi.mode_changed = true; 7888 new_crtc_state->update_pipe = false; 7889 } 7890 } 7891 7892 if (new_crtc_state->bigjoiner_pipes) { 7893 if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) { 7894 new_crtc_state->uapi.mode_changed = true; 7895 new_crtc_state->update_pipe = false; 7896 } 7897 } 7898 } 7899 7900 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7901 new_crtc_state, i) { 7902 if (intel_crtc_needs_modeset(new_crtc_state)) { 7903 any_ms = true; 7904 continue; 7905 } 7906 7907 if (!new_crtc_state->update_pipe) 7908 continue; 7909 7910 intel_crtc_copy_fastset(old_crtc_state, new_crtc_state); 7911 } 7912 7913 if (any_ms && !check_digital_port_conflicts(state)) { 7914 drm_dbg_kms(&dev_priv->drm, 7915 "rejecting conflicting digital port configuration\n"); 7916 ret = -EINVAL; 7917 goto fail; 7918 } 7919 7920 ret = drm_dp_mst_atomic_check(&state->base); 7921 if (ret) 7922 goto fail; 7923 7924 ret = intel_atomic_check_planes(state); 7925 if (ret) 7926 goto fail; 7927 7928 ret = intel_compute_global_watermarks(state); 7929 if (ret) 7930 goto fail; 7931 7932 ret = intel_bw_atomic_check(state); 7933 if (ret) 7934 goto fail; 7935 7936 ret = intel_cdclk_atomic_check(state, &any_ms); 7937 if (ret) 7938 goto fail; 7939 7940 if (intel_any_crtc_needs_modeset(state)) 7941 any_ms = true; 7942 7943 if (any_ms) { 7944 ret = intel_modeset_checks(state); 7945 if (ret) 7946 goto fail; 7947 7948 ret = intel_modeset_calc_cdclk(state); 7949 if (ret) 7950 return ret; 7951 7952 intel_modeset_clear_plls(state); 7953 } 7954 7955 ret = intel_atomic_check_crtcs(state); 7956 if (ret) 7957 goto fail; 7958 7959 ret = intel_fbc_atomic_check(state); 7960 if (ret) 7961 goto fail; 7962 7963 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7964 new_crtc_state, i) { 7965 ret = intel_async_flip_check_hw(state, crtc); 7966 if (ret) 7967 goto fail; 7968 7969 if (!intel_crtc_needs_modeset(new_crtc_state) && 7970 !new_crtc_state->update_pipe) 7971 continue; 7972 7973 intel_dump_pipe_config(new_crtc_state, state, 7974 intel_crtc_needs_modeset(new_crtc_state) ? 7975 "[modeset]" : "[fastset]"); 7976 } 7977 7978 return 0; 7979 7980 fail: 7981 if (ret == -EDEADLK) 7982 return ret; 7983 7984 /* 7985 * FIXME would probably be nice to know which crtc specifically 7986 * caused the failure, in cases where we can pinpoint it. 7987 */ 7988 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7989 new_crtc_state, i) 7990 intel_dump_pipe_config(new_crtc_state, state, "[failed]"); 7991 7992 return ret; 7993 } 7994 7995 static int intel_atomic_prepare_commit(struct intel_atomic_state *state) 7996 { 7997 struct intel_crtc_state *crtc_state; 7998 struct intel_crtc *crtc; 7999 int i, ret; 8000 8001 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base); 8002 if (ret < 0) 8003 return ret; 8004 8005 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 8006 bool mode_changed = intel_crtc_needs_modeset(crtc_state); 8007 8008 if (mode_changed || crtc_state->update_pipe || 8009 crtc_state->uapi.color_mgmt_changed) { 8010 intel_dsb_prepare(crtc_state); 8011 } 8012 } 8013 8014 return 0; 8015 } 8016 8017 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 8018 struct intel_crtc_state *crtc_state) 8019 { 8020 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 8021 8022 if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes) 8023 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 8024 8025 if (crtc_state->has_pch_encoder) { 8026 enum pipe pch_transcoder = 8027 intel_crtc_pch_transcoder(crtc); 8028 8029 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true); 8030 } 8031 } 8032 8033 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, 8034 const struct intel_crtc_state *new_crtc_state) 8035 { 8036 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 8037 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 8038 8039 /* 8040 * Update pipe size and adjust fitter if needed: the reason for this is 8041 * that in compute_mode_changes we check the native mode (not the pfit 8042 * mode) to see if we can flip rather than do a full mode set. In the 8043 * fastboot case, we'll flip, but if we don't update the pipesrc and 8044 * pfit state, we'll end up with a big fb scanned out into the wrong 8045 * sized surface. 8046 */ 8047 intel_set_pipe_src_size(new_crtc_state); 8048 8049 /* on skylake this is done by detaching scalers */ 8050 if (DISPLAY_VER(dev_priv) >= 9) { 8051 if (new_crtc_state->pch_pfit.enabled) 8052 skl_pfit_enable(new_crtc_state); 8053 } else if (HAS_PCH_SPLIT(dev_priv)) { 8054 if (new_crtc_state->pch_pfit.enabled) 8055 ilk_pfit_enable(new_crtc_state); 8056 else if (old_crtc_state->pch_pfit.enabled) 8057 ilk_pfit_disable(old_crtc_state); 8058 } 8059 8060 /* 8061 * The register is supposedly single buffered so perhaps 8062 * not 100% correct to do this here. But SKL+ calculate 8063 * this based on the adjust pixel rate so pfit changes do 8064 * affect it and so it must be updated for fastsets. 8065 * HSW/BDW only really need this here for fastboot, after 8066 * that the value should not change without a full modeset. 8067 */ 8068 if (DISPLAY_VER(dev_priv) >= 9 || 8069 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 8070 hsw_set_linetime_wm(new_crtc_state); 8071 } 8072 8073 static void commit_pipe_pre_planes(struct intel_atomic_state *state, 8074 struct intel_crtc *crtc) 8075 { 8076 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8077 const struct intel_crtc_state *old_crtc_state = 8078 intel_atomic_get_old_crtc_state(state, crtc); 8079 const struct intel_crtc_state *new_crtc_state = 8080 intel_atomic_get_new_crtc_state(state, crtc); 8081 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 8082 8083 /* 8084 * During modesets pipe configuration was programmed as the 8085 * CRTC was enabled. 8086 */ 8087 if (!modeset) { 8088 if (new_crtc_state->uapi.color_mgmt_changed || 8089 new_crtc_state->update_pipe) 8090 intel_color_commit_arm(new_crtc_state); 8091 8092 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 8093 bdw_set_pipemisc(new_crtc_state); 8094 8095 if (new_crtc_state->update_pipe) 8096 intel_pipe_fastset(old_crtc_state, new_crtc_state); 8097 } 8098 8099 intel_psr2_program_trans_man_trk_ctl(new_crtc_state); 8100 8101 intel_atomic_update_watermarks(state, crtc); 8102 } 8103 8104 static void commit_pipe_post_planes(struct intel_atomic_state *state, 8105 struct intel_crtc *crtc) 8106 { 8107 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8108 const struct intel_crtc_state *new_crtc_state = 8109 intel_atomic_get_new_crtc_state(state, crtc); 8110 8111 /* 8112 * Disable the scaler(s) after the plane(s) so that we don't 8113 * get a catastrophic underrun even if the two operations 8114 * end up happening in two different frames. 8115 */ 8116 if (DISPLAY_VER(dev_priv) >= 9 && 8117 !intel_crtc_needs_modeset(new_crtc_state)) 8118 skl_detach_scalers(new_crtc_state); 8119 } 8120 8121 static void intel_enable_crtc(struct intel_atomic_state *state, 8122 struct intel_crtc *crtc) 8123 { 8124 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8125 const struct intel_crtc_state *new_crtc_state = 8126 intel_atomic_get_new_crtc_state(state, crtc); 8127 8128 if (!intel_crtc_needs_modeset(new_crtc_state)) 8129 return; 8130 8131 intel_crtc_update_active_timings(new_crtc_state); 8132 8133 dev_priv->display->crtc_enable(state, crtc); 8134 8135 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 8136 return; 8137 8138 /* vblanks work again, re-enable pipe CRC. */ 8139 intel_crtc_enable_pipe_crc(crtc); 8140 } 8141 8142 static void intel_update_crtc(struct intel_atomic_state *state, 8143 struct intel_crtc *crtc) 8144 { 8145 struct drm_i915_private *i915 = to_i915(state->base.dev); 8146 const struct intel_crtc_state *old_crtc_state = 8147 intel_atomic_get_old_crtc_state(state, crtc); 8148 struct intel_crtc_state *new_crtc_state = 8149 intel_atomic_get_new_crtc_state(state, crtc); 8150 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 8151 8152 if (!modeset) { 8153 if (new_crtc_state->preload_luts && 8154 (new_crtc_state->uapi.color_mgmt_changed || 8155 new_crtc_state->update_pipe)) 8156 intel_color_load_luts(new_crtc_state); 8157 8158 intel_pre_plane_update(state, crtc); 8159 8160 if (new_crtc_state->update_pipe) 8161 intel_encoders_update_pipe(state, crtc); 8162 8163 if (DISPLAY_VER(i915) >= 11 && 8164 new_crtc_state->update_pipe) 8165 icl_set_pipe_chicken(new_crtc_state); 8166 } 8167 8168 intel_fbc_update(state, crtc); 8169 8170 if (!modeset && 8171 (new_crtc_state->uapi.color_mgmt_changed || 8172 new_crtc_state->update_pipe)) 8173 intel_color_commit_noarm(new_crtc_state); 8174 8175 intel_crtc_planes_update_noarm(state, crtc); 8176 8177 /* Perform vblank evasion around commit operation */ 8178 intel_pipe_update_start(new_crtc_state); 8179 8180 commit_pipe_pre_planes(state, crtc); 8181 8182 intel_crtc_planes_update_arm(state, crtc); 8183 8184 commit_pipe_post_planes(state, crtc); 8185 8186 intel_pipe_update_end(new_crtc_state); 8187 8188 /* 8189 * We usually enable FIFO underrun interrupts as part of the 8190 * CRTC enable sequence during modesets. But when we inherit a 8191 * valid pipe configuration from the BIOS we need to take care 8192 * of enabling them on the CRTC's first fastset. 8193 */ 8194 if (new_crtc_state->update_pipe && !modeset && 8195 old_crtc_state->inherited) 8196 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state); 8197 } 8198 8199 static void intel_old_crtc_state_disables(struct intel_atomic_state *state, 8200 struct intel_crtc_state *old_crtc_state, 8201 struct intel_crtc_state *new_crtc_state, 8202 struct intel_crtc *crtc) 8203 { 8204 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8205 8206 /* 8207 * We need to disable pipe CRC before disabling the pipe, 8208 * or we race against vblank off. 8209 */ 8210 intel_crtc_disable_pipe_crc(crtc); 8211 8212 dev_priv->display->crtc_disable(state, crtc); 8213 crtc->active = false; 8214 intel_fbc_disable(crtc); 8215 intel_disable_shared_dpll(old_crtc_state); 8216 8217 /* FIXME unify this for all platforms */ 8218 if (!new_crtc_state->hw.active && 8219 !HAS_GMCH(dev_priv)) 8220 intel_initial_watermarks(state, crtc); 8221 } 8222 8223 static void intel_commit_modeset_disables(struct intel_atomic_state *state) 8224 { 8225 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 8226 struct intel_crtc *crtc; 8227 u32 handled = 0; 8228 int i; 8229 8230 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8231 new_crtc_state, i) { 8232 if (!intel_crtc_needs_modeset(new_crtc_state)) 8233 continue; 8234 8235 if (!old_crtc_state->hw.active) 8236 continue; 8237 8238 intel_pre_plane_update(state, crtc); 8239 intel_crtc_disable_planes(state, crtc); 8240 } 8241 8242 /* Only disable port sync and MST slaves */ 8243 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8244 new_crtc_state, i) { 8245 if (!intel_crtc_needs_modeset(new_crtc_state)) 8246 continue; 8247 8248 if (!old_crtc_state->hw.active) 8249 continue; 8250 8251 /* In case of Transcoder port Sync master slave CRTCs can be 8252 * assigned in any order and we need to make sure that 8253 * slave CRTCs are disabled first and then master CRTC since 8254 * Slave vblanks are masked till Master Vblanks. 8255 */ 8256 if (!is_trans_port_sync_slave(old_crtc_state) && 8257 !intel_dp_mst_is_slave_trans(old_crtc_state) && 8258 !intel_crtc_is_bigjoiner_slave(old_crtc_state)) 8259 continue; 8260 8261 intel_old_crtc_state_disables(state, old_crtc_state, 8262 new_crtc_state, crtc); 8263 handled |= BIT(crtc->pipe); 8264 } 8265 8266 /* Disable everything else left on */ 8267 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8268 new_crtc_state, i) { 8269 if (!intel_crtc_needs_modeset(new_crtc_state) || 8270 (handled & BIT(crtc->pipe))) 8271 continue; 8272 8273 if (!old_crtc_state->hw.active) 8274 continue; 8275 8276 intel_old_crtc_state_disables(state, old_crtc_state, 8277 new_crtc_state, crtc); 8278 } 8279 } 8280 8281 static void intel_commit_modeset_enables(struct intel_atomic_state *state) 8282 { 8283 struct intel_crtc_state *new_crtc_state; 8284 struct intel_crtc *crtc; 8285 int i; 8286 8287 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8288 if (!new_crtc_state->hw.active) 8289 continue; 8290 8291 intel_enable_crtc(state, crtc); 8292 intel_update_crtc(state, crtc); 8293 } 8294 } 8295 8296 static void skl_commit_modeset_enables(struct intel_atomic_state *state) 8297 { 8298 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8299 struct intel_crtc *crtc; 8300 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 8301 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; 8302 u8 update_pipes = 0, modeset_pipes = 0; 8303 int i; 8304 8305 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 8306 enum pipe pipe = crtc->pipe; 8307 8308 if (!new_crtc_state->hw.active) 8309 continue; 8310 8311 /* ignore allocations for crtc's that have been turned off. */ 8312 if (!intel_crtc_needs_modeset(new_crtc_state)) { 8313 entries[pipe] = old_crtc_state->wm.skl.ddb; 8314 update_pipes |= BIT(pipe); 8315 } else { 8316 modeset_pipes |= BIT(pipe); 8317 } 8318 } 8319 8320 /* 8321 * Whenever the number of active pipes changes, we need to make sure we 8322 * update the pipes in the right order so that their ddb allocations 8323 * never overlap with each other between CRTC updates. Otherwise we'll 8324 * cause pipe underruns and other bad stuff. 8325 * 8326 * So first lets enable all pipes that do not need a fullmodeset as 8327 * those don't have any external dependency. 8328 */ 8329 while (update_pipes) { 8330 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8331 new_crtc_state, i) { 8332 enum pipe pipe = crtc->pipe; 8333 8334 if ((update_pipes & BIT(pipe)) == 0) 8335 continue; 8336 8337 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 8338 entries, I915_MAX_PIPES, pipe)) 8339 continue; 8340 8341 entries[pipe] = new_crtc_state->wm.skl.ddb; 8342 update_pipes &= ~BIT(pipe); 8343 8344 intel_update_crtc(state, crtc); 8345 8346 /* 8347 * If this is an already active pipe, it's DDB changed, 8348 * and this isn't the last pipe that needs updating 8349 * then we need to wait for a vblank to pass for the 8350 * new ddb allocation to take effect. 8351 */ 8352 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, 8353 &old_crtc_state->wm.skl.ddb) && 8354 (update_pipes | modeset_pipes)) 8355 intel_crtc_wait_for_next_vblank(crtc); 8356 } 8357 } 8358 8359 update_pipes = modeset_pipes; 8360 8361 /* 8362 * Enable all pipes that needs a modeset and do not depends on other 8363 * pipes 8364 */ 8365 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8366 enum pipe pipe = crtc->pipe; 8367 8368 if ((modeset_pipes & BIT(pipe)) == 0) 8369 continue; 8370 8371 if (intel_dp_mst_is_slave_trans(new_crtc_state) || 8372 is_trans_port_sync_master(new_crtc_state) || 8373 intel_crtc_is_bigjoiner_master(new_crtc_state)) 8374 continue; 8375 8376 modeset_pipes &= ~BIT(pipe); 8377 8378 intel_enable_crtc(state, crtc); 8379 } 8380 8381 /* 8382 * Then we enable all remaining pipes that depend on other 8383 * pipes: MST slaves and port sync masters, big joiner master 8384 */ 8385 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8386 enum pipe pipe = crtc->pipe; 8387 8388 if ((modeset_pipes & BIT(pipe)) == 0) 8389 continue; 8390 8391 modeset_pipes &= ~BIT(pipe); 8392 8393 intel_enable_crtc(state, crtc); 8394 } 8395 8396 /* 8397 * Finally we do the plane updates/etc. for all pipes that got enabled. 8398 */ 8399 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8400 enum pipe pipe = crtc->pipe; 8401 8402 if ((update_pipes & BIT(pipe)) == 0) 8403 continue; 8404 8405 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 8406 entries, I915_MAX_PIPES, pipe)); 8407 8408 entries[pipe] = new_crtc_state->wm.skl.ddb; 8409 update_pipes &= ~BIT(pipe); 8410 8411 intel_update_crtc(state, crtc); 8412 } 8413 8414 drm_WARN_ON(&dev_priv->drm, modeset_pipes); 8415 drm_WARN_ON(&dev_priv->drm, update_pipes); 8416 } 8417 8418 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) 8419 { 8420 struct intel_atomic_state *state, *next; 8421 struct llist_node *freed; 8422 8423 freed = llist_del_all(&dev_priv->atomic_helper.free_list); 8424 llist_for_each_entry_safe(state, next, freed, freed) 8425 drm_atomic_state_put(&state->base); 8426 } 8427 8428 static void intel_atomic_helper_free_state_worker(struct work_struct *work) 8429 { 8430 struct drm_i915_private *dev_priv = 8431 container_of(work, typeof(*dev_priv), atomic_helper.free_work); 8432 8433 intel_atomic_helper_free_state(dev_priv); 8434 } 8435 8436 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) 8437 { 8438 struct wait_queue_entry wait_fence, wait_reset; 8439 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); 8440 8441 init_wait_entry(&wait_fence, 0); 8442 init_wait_entry(&wait_reset, 0); 8443 for (;;) { 8444 prepare_to_wait(&intel_state->commit_ready.wait, 8445 &wait_fence, TASK_UNINTERRUPTIBLE); 8446 prepare_to_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 8447 I915_RESET_MODESET), 8448 &wait_reset, TASK_UNINTERRUPTIBLE); 8449 8450 8451 if (i915_sw_fence_done(&intel_state->commit_ready) || 8452 test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags)) 8453 break; 8454 8455 schedule(); 8456 } 8457 finish_wait(&intel_state->commit_ready.wait, &wait_fence); 8458 finish_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 8459 I915_RESET_MODESET), 8460 &wait_reset); 8461 } 8462 8463 static void intel_cleanup_dsbs(struct intel_atomic_state *state) 8464 { 8465 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 8466 struct intel_crtc *crtc; 8467 int i; 8468 8469 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8470 new_crtc_state, i) 8471 intel_dsb_cleanup(old_crtc_state); 8472 } 8473 8474 static void intel_atomic_cleanup_work(struct work_struct *work) 8475 { 8476 struct intel_atomic_state *state = 8477 container_of(work, struct intel_atomic_state, base.commit_work); 8478 struct drm_i915_private *i915 = to_i915(state->base.dev); 8479 8480 intel_cleanup_dsbs(state); 8481 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base); 8482 drm_atomic_helper_commit_cleanup_done(&state->base); 8483 drm_atomic_state_put(&state->base); 8484 8485 intel_atomic_helper_free_state(i915); 8486 } 8487 8488 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state) 8489 { 8490 struct drm_i915_private *i915 = to_i915(state->base.dev); 8491 struct intel_plane *plane; 8492 struct intel_plane_state *plane_state; 8493 int i; 8494 8495 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 8496 struct drm_framebuffer *fb = plane_state->hw.fb; 8497 int cc_plane; 8498 int ret; 8499 8500 if (!fb) 8501 continue; 8502 8503 cc_plane = intel_fb_rc_ccs_cc_plane(fb); 8504 if (cc_plane < 0) 8505 continue; 8506 8507 /* 8508 * The layout of the fast clear color value expected by HW 8509 * (the DRM ABI requiring this value to be located in fb at offset 0 of plane#2): 8510 * - 4 x 4 bytes per-channel value 8511 * (in surface type specific float/int format provided by the fb user) 8512 * - 8 bytes native color value used by the display 8513 * (converted/written by GPU during a fast clear operation using the 8514 * above per-channel values) 8515 * 8516 * The commit's FB prepare hook already ensured that FB obj is pinned and the 8517 * caller made sure that the object is synced wrt. the related color clear value 8518 * GPU write on it. 8519 */ 8520 ret = i915_gem_object_read_from_page(intel_fb_obj(fb), 8521 fb->offsets[cc_plane] + 16, 8522 &plane_state->ccval, 8523 sizeof(plane_state->ccval)); 8524 /* The above could only fail if the FB obj has an unexpected backing store type. */ 8525 drm_WARN_ON(&i915->drm, ret); 8526 } 8527 } 8528 8529 static void intel_atomic_commit_tail(struct intel_atomic_state *state) 8530 { 8531 struct drm_device *dev = state->base.dev; 8532 struct drm_i915_private *dev_priv = to_i915(dev); 8533 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 8534 struct intel_crtc *crtc; 8535 u64 put_domains[I915_MAX_PIPES] = {}; 8536 intel_wakeref_t wakeref = 0; 8537 int i; 8538 8539 intel_atomic_commit_fence_wait(state); 8540 8541 drm_atomic_helper_wait_for_dependencies(&state->base); 8542 8543 if (state->modeset) 8544 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); 8545 8546 intel_atomic_prepare_plane_clear_colors(state); 8547 8548 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8549 new_crtc_state, i) { 8550 if (intel_crtc_needs_modeset(new_crtc_state) || 8551 new_crtc_state->update_pipe) { 8552 8553 put_domains[crtc->pipe] = 8554 modeset_get_crtc_power_domains(new_crtc_state); 8555 } 8556 } 8557 8558 intel_commit_modeset_disables(state); 8559 8560 /* FIXME: Eventually get rid of our crtc->config pointer */ 8561 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 8562 crtc->config = new_crtc_state; 8563 8564 if (state->modeset) { 8565 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base); 8566 8567 intel_set_cdclk_pre_plane_update(state); 8568 8569 intel_modeset_verify_disabled(dev_priv, state); 8570 } 8571 8572 intel_sagv_pre_plane_update(state); 8573 8574 /* Complete the events for pipes that have now been disabled */ 8575 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8576 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 8577 8578 /* Complete events for now disable pipes here. */ 8579 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) { 8580 spin_lock_irq(&dev->event_lock); 8581 drm_crtc_send_vblank_event(&crtc->base, 8582 new_crtc_state->uapi.event); 8583 spin_unlock_irq(&dev->event_lock); 8584 8585 new_crtc_state->uapi.event = NULL; 8586 } 8587 } 8588 8589 intel_encoders_update_prepare(state); 8590 8591 intel_dbuf_pre_plane_update(state); 8592 8593 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8594 if (new_crtc_state->do_async_flip) 8595 intel_crtc_enable_flip_done(state, crtc); 8596 } 8597 8598 /* Now enable the clocks, plane, pipe, and connectors that we set up. */ 8599 dev_priv->display->commit_modeset_enables(state); 8600 8601 intel_encoders_update_complete(state); 8602 8603 if (state->modeset) 8604 intel_set_cdclk_post_plane_update(state); 8605 8606 intel_wait_for_vblank_workers(state); 8607 8608 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here 8609 * already, but still need the state for the delayed optimization. To 8610 * fix this: 8611 * - wrap the optimization/post_plane_update stuff into a per-crtc work. 8612 * - schedule that vblank worker _before_ calling hw_done 8613 * - at the start of commit_tail, cancel it _synchrously 8614 * - switch over to the vblank wait helper in the core after that since 8615 * we don't need out special handling any more. 8616 */ 8617 drm_atomic_helper_wait_for_flip_done(dev, &state->base); 8618 8619 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8620 if (new_crtc_state->do_async_flip) 8621 intel_crtc_disable_flip_done(state, crtc); 8622 } 8623 8624 /* 8625 * Now that the vblank has passed, we can go ahead and program the 8626 * optimal watermarks on platforms that need two-step watermark 8627 * programming. 8628 * 8629 * TODO: Move this (and other cleanup) to an async worker eventually. 8630 */ 8631 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8632 new_crtc_state, i) { 8633 /* 8634 * Gen2 reports pipe underruns whenever all planes are disabled. 8635 * So re-enable underrun reporting after some planes get enabled. 8636 * 8637 * We do this before .optimize_watermarks() so that we have a 8638 * chance of catching underruns with the intermediate watermarks 8639 * vs. the new plane configuration. 8640 */ 8641 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state)) 8642 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 8643 8644 intel_optimize_watermarks(state, crtc); 8645 } 8646 8647 intel_dbuf_post_plane_update(state); 8648 intel_psr_post_plane_update(state); 8649 8650 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 8651 intel_post_plane_update(state, crtc); 8652 8653 modeset_put_crtc_power_domains(crtc, put_domains[crtc->pipe]); 8654 8655 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state); 8656 8657 /* 8658 * DSB cleanup is done in cleanup_work aligning with framebuffer 8659 * cleanup. So copy and reset the dsb structure to sync with 8660 * commit_done and later do dsb cleanup in cleanup_work. 8661 */ 8662 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb); 8663 } 8664 8665 /* Underruns don't always raise interrupts, so check manually */ 8666 intel_check_cpu_fifo_underruns(dev_priv); 8667 intel_check_pch_fifo_underruns(dev_priv); 8668 8669 if (state->modeset) 8670 intel_verify_planes(state); 8671 8672 intel_sagv_post_plane_update(state); 8673 8674 drm_atomic_helper_commit_hw_done(&state->base); 8675 8676 if (state->modeset) { 8677 /* As one of the primary mmio accessors, KMS has a high 8678 * likelihood of triggering bugs in unclaimed access. After we 8679 * finish modesetting, see if an error has been flagged, and if 8680 * so enable debugging for the next modeset - and hope we catch 8681 * the culprit. 8682 */ 8683 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); 8684 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref); 8685 } 8686 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 8687 8688 /* 8689 * Defer the cleanup of the old state to a separate worker to not 8690 * impede the current task (userspace for blocking modesets) that 8691 * are executed inline. For out-of-line asynchronous modesets/flips, 8692 * deferring to a new worker seems overkill, but we would place a 8693 * schedule point (cond_resched()) here anyway to keep latencies 8694 * down. 8695 */ 8696 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work); 8697 queue_work(system_highpri_wq, &state->base.commit_work); 8698 } 8699 8700 static void intel_atomic_commit_work(struct work_struct *work) 8701 { 8702 struct intel_atomic_state *state = 8703 container_of(work, struct intel_atomic_state, base.commit_work); 8704 8705 intel_atomic_commit_tail(state); 8706 } 8707 8708 static int 8709 intel_atomic_commit_ready(struct i915_sw_fence *fence, 8710 enum i915_sw_fence_notify notify) 8711 { 8712 struct intel_atomic_state *state = 8713 container_of(fence, struct intel_atomic_state, commit_ready); 8714 8715 switch (notify) { 8716 case FENCE_COMPLETE: 8717 /* we do blocking waits in the worker, nothing to do here */ 8718 break; 8719 case FENCE_FREE: 8720 { 8721 struct intel_atomic_helper *helper = 8722 &to_i915(state->base.dev)->atomic_helper; 8723 8724 if (llist_add(&state->freed, &helper->free_list)) 8725 schedule_work(&helper->free_work); 8726 break; 8727 } 8728 } 8729 8730 return NOTIFY_DONE; 8731 } 8732 8733 static void intel_atomic_track_fbs(struct intel_atomic_state *state) 8734 { 8735 struct intel_plane_state *old_plane_state, *new_plane_state; 8736 struct intel_plane *plane; 8737 int i; 8738 8739 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 8740 new_plane_state, i) 8741 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), 8742 to_intel_frontbuffer(new_plane_state->hw.fb), 8743 plane->frontbuffer_bit); 8744 } 8745 8746 static int intel_atomic_commit(struct drm_device *dev, 8747 struct drm_atomic_state *_state, 8748 bool nonblock) 8749 { 8750 struct intel_atomic_state *state = to_intel_atomic_state(_state); 8751 struct drm_i915_private *dev_priv = to_i915(dev); 8752 int ret = 0; 8753 8754 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 8755 8756 drm_atomic_state_get(&state->base); 8757 i915_sw_fence_init(&state->commit_ready, 8758 intel_atomic_commit_ready); 8759 8760 /* 8761 * The intel_legacy_cursor_update() fast path takes care 8762 * of avoiding the vblank waits for simple cursor 8763 * movement and flips. For cursor on/off and size changes, 8764 * we want to perform the vblank waits so that watermark 8765 * updates happen during the correct frames. Gen9+ have 8766 * double buffered watermarks and so shouldn't need this. 8767 * 8768 * Unset state->legacy_cursor_update before the call to 8769 * drm_atomic_helper_setup_commit() because otherwise 8770 * drm_atomic_helper_wait_for_flip_done() is a noop and 8771 * we get FIFO underruns because we didn't wait 8772 * for vblank. 8773 * 8774 * FIXME doing watermarks and fb cleanup from a vblank worker 8775 * (assuming we had any) would solve these problems. 8776 */ 8777 if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) { 8778 struct intel_crtc_state *new_crtc_state; 8779 struct intel_crtc *crtc; 8780 int i; 8781 8782 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 8783 if (new_crtc_state->wm.need_postvbl_update || 8784 new_crtc_state->update_wm_post) 8785 state->base.legacy_cursor_update = false; 8786 } 8787 8788 ret = intel_atomic_prepare_commit(state); 8789 if (ret) { 8790 drm_dbg_atomic(&dev_priv->drm, 8791 "Preparing state failed with %i\n", ret); 8792 i915_sw_fence_commit(&state->commit_ready); 8793 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 8794 return ret; 8795 } 8796 8797 ret = drm_atomic_helper_setup_commit(&state->base, nonblock); 8798 if (!ret) 8799 ret = drm_atomic_helper_swap_state(&state->base, true); 8800 if (!ret) 8801 intel_atomic_swap_global_state(state); 8802 8803 if (ret) { 8804 struct intel_crtc_state *new_crtc_state; 8805 struct intel_crtc *crtc; 8806 int i; 8807 8808 i915_sw_fence_commit(&state->commit_ready); 8809 8810 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 8811 intel_dsb_cleanup(new_crtc_state); 8812 8813 drm_atomic_helper_cleanup_planes(dev, &state->base); 8814 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 8815 return ret; 8816 } 8817 intel_shared_dpll_swap_state(state); 8818 intel_atomic_track_fbs(state); 8819 8820 drm_atomic_state_get(&state->base); 8821 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work); 8822 8823 i915_sw_fence_commit(&state->commit_ready); 8824 if (nonblock && state->modeset) { 8825 queue_work(dev_priv->modeset_wq, &state->base.commit_work); 8826 } else if (nonblock) { 8827 queue_work(dev_priv->flip_wq, &state->base.commit_work); 8828 } else { 8829 if (state->modeset) 8830 flush_workqueue(dev_priv->modeset_wq); 8831 intel_atomic_commit_tail(state); 8832 } 8833 8834 return 0; 8835 } 8836 8837 /** 8838 * intel_plane_destroy - destroy a plane 8839 * @plane: plane to destroy 8840 * 8841 * Common destruction function for all types of planes (primary, cursor, 8842 * sprite). 8843 */ 8844 void intel_plane_destroy(struct drm_plane *plane) 8845 { 8846 drm_plane_cleanup(plane); 8847 kfree(to_intel_plane(plane)); 8848 } 8849 8850 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv) 8851 { 8852 struct intel_plane *plane; 8853 8854 for_each_intel_plane(&dev_priv->drm, plane) { 8855 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, 8856 plane->pipe); 8857 8858 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base); 8859 } 8860 } 8861 8862 8863 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 8864 struct drm_file *file) 8865 { 8866 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; 8867 struct drm_crtc *drmmode_crtc; 8868 struct intel_crtc *crtc; 8869 8870 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id); 8871 if (!drmmode_crtc) 8872 return -ENOENT; 8873 8874 crtc = to_intel_crtc(drmmode_crtc); 8875 pipe_from_crtc_id->pipe = crtc->pipe; 8876 8877 return 0; 8878 } 8879 8880 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder) 8881 { 8882 struct drm_device *dev = encoder->base.dev; 8883 struct intel_encoder *source_encoder; 8884 u32 possible_clones = 0; 8885 8886 for_each_intel_encoder(dev, source_encoder) { 8887 if (encoders_cloneable(encoder, source_encoder)) 8888 possible_clones |= drm_encoder_mask(&source_encoder->base); 8889 } 8890 8891 return possible_clones; 8892 } 8893 8894 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder) 8895 { 8896 struct drm_device *dev = encoder->base.dev; 8897 struct intel_crtc *crtc; 8898 u32 possible_crtcs = 0; 8899 8900 for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask) 8901 possible_crtcs |= drm_crtc_mask(&crtc->base); 8902 8903 return possible_crtcs; 8904 } 8905 8906 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv) 8907 { 8908 if (!IS_MOBILE(dev_priv)) 8909 return false; 8910 8911 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0) 8912 return false; 8913 8914 if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE)) 8915 return false; 8916 8917 return true; 8918 } 8919 8920 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv) 8921 { 8922 if (DISPLAY_VER(dev_priv) >= 9) 8923 return false; 8924 8925 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) 8926 return false; 8927 8928 if (HAS_PCH_LPT_H(dev_priv) && 8929 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) 8930 return false; 8931 8932 /* DDI E can't be used if DDI A requires 4 lanes */ 8933 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 8934 return false; 8935 8936 if (!dev_priv->vbt.int_crt_support) 8937 return false; 8938 8939 return true; 8940 } 8941 8942 static void intel_setup_outputs(struct drm_i915_private *dev_priv) 8943 { 8944 struct intel_encoder *encoder; 8945 bool dpd_is_edp = false; 8946 8947 intel_pps_unlock_regs_wa(dev_priv); 8948 8949 if (!HAS_DISPLAY(dev_priv)) 8950 return; 8951 8952 if (IS_DG2(dev_priv)) { 8953 intel_ddi_init(dev_priv, PORT_A); 8954 intel_ddi_init(dev_priv, PORT_B); 8955 intel_ddi_init(dev_priv, PORT_C); 8956 intel_ddi_init(dev_priv, PORT_D_XELPD); 8957 intel_ddi_init(dev_priv, PORT_TC1); 8958 } else if (IS_ALDERLAKE_P(dev_priv)) { 8959 intel_ddi_init(dev_priv, PORT_A); 8960 intel_ddi_init(dev_priv, PORT_B); 8961 intel_ddi_init(dev_priv, PORT_TC1); 8962 intel_ddi_init(dev_priv, PORT_TC2); 8963 intel_ddi_init(dev_priv, PORT_TC3); 8964 intel_ddi_init(dev_priv, PORT_TC4); 8965 icl_dsi_init(dev_priv); 8966 } else if (IS_ALDERLAKE_S(dev_priv)) { 8967 intel_ddi_init(dev_priv, PORT_A); 8968 intel_ddi_init(dev_priv, PORT_TC1); 8969 intel_ddi_init(dev_priv, PORT_TC2); 8970 intel_ddi_init(dev_priv, PORT_TC3); 8971 intel_ddi_init(dev_priv, PORT_TC4); 8972 } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) { 8973 intel_ddi_init(dev_priv, PORT_A); 8974 intel_ddi_init(dev_priv, PORT_B); 8975 intel_ddi_init(dev_priv, PORT_TC1); 8976 intel_ddi_init(dev_priv, PORT_TC2); 8977 } else if (DISPLAY_VER(dev_priv) >= 12) { 8978 intel_ddi_init(dev_priv, PORT_A); 8979 intel_ddi_init(dev_priv, PORT_B); 8980 intel_ddi_init(dev_priv, PORT_TC1); 8981 intel_ddi_init(dev_priv, PORT_TC2); 8982 intel_ddi_init(dev_priv, PORT_TC3); 8983 intel_ddi_init(dev_priv, PORT_TC4); 8984 intel_ddi_init(dev_priv, PORT_TC5); 8985 intel_ddi_init(dev_priv, PORT_TC6); 8986 icl_dsi_init(dev_priv); 8987 } else if (IS_JSL_EHL(dev_priv)) { 8988 intel_ddi_init(dev_priv, PORT_A); 8989 intel_ddi_init(dev_priv, PORT_B); 8990 intel_ddi_init(dev_priv, PORT_C); 8991 intel_ddi_init(dev_priv, PORT_D); 8992 icl_dsi_init(dev_priv); 8993 } else if (DISPLAY_VER(dev_priv) == 11) { 8994 intel_ddi_init(dev_priv, PORT_A); 8995 intel_ddi_init(dev_priv, PORT_B); 8996 intel_ddi_init(dev_priv, PORT_C); 8997 intel_ddi_init(dev_priv, PORT_D); 8998 intel_ddi_init(dev_priv, PORT_E); 8999 intel_ddi_init(dev_priv, PORT_F); 9000 icl_dsi_init(dev_priv); 9001 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 9002 intel_ddi_init(dev_priv, PORT_A); 9003 intel_ddi_init(dev_priv, PORT_B); 9004 intel_ddi_init(dev_priv, PORT_C); 9005 vlv_dsi_init(dev_priv); 9006 } else if (DISPLAY_VER(dev_priv) >= 9) { 9007 intel_ddi_init(dev_priv, PORT_A); 9008 intel_ddi_init(dev_priv, PORT_B); 9009 intel_ddi_init(dev_priv, PORT_C); 9010 intel_ddi_init(dev_priv, PORT_D); 9011 intel_ddi_init(dev_priv, PORT_E); 9012 } else if (HAS_DDI(dev_priv)) { 9013 u32 found; 9014 9015 if (intel_ddi_crt_present(dev_priv)) 9016 intel_crt_init(dev_priv); 9017 9018 /* Haswell uses DDI functions to detect digital outputs. */ 9019 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 9020 if (found) 9021 intel_ddi_init(dev_priv, PORT_A); 9022 9023 found = intel_de_read(dev_priv, SFUSE_STRAP); 9024 if (found & SFUSE_STRAP_DDIB_DETECTED) 9025 intel_ddi_init(dev_priv, PORT_B); 9026 if (found & SFUSE_STRAP_DDIC_DETECTED) 9027 intel_ddi_init(dev_priv, PORT_C); 9028 if (found & SFUSE_STRAP_DDID_DETECTED) 9029 intel_ddi_init(dev_priv, PORT_D); 9030 if (found & SFUSE_STRAP_DDIF_DETECTED) 9031 intel_ddi_init(dev_priv, PORT_F); 9032 } else if (HAS_PCH_SPLIT(dev_priv)) { 9033 int found; 9034 9035 /* 9036 * intel_edp_init_connector() depends on this completing first, 9037 * to prevent the registration of both eDP and LVDS and the 9038 * incorrect sharing of the PPS. 9039 */ 9040 intel_lvds_init(dev_priv); 9041 intel_crt_init(dev_priv); 9042 9043 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D); 9044 9045 if (ilk_has_edp_a(dev_priv)) 9046 g4x_dp_init(dev_priv, DP_A, PORT_A); 9047 9048 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) { 9049 /* PCH SDVOB multiplex with HDMIB */ 9050 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); 9051 if (!found) 9052 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); 9053 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED)) 9054 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B); 9055 } 9056 9057 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED) 9058 g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); 9059 9060 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED) 9061 g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D); 9062 9063 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED) 9064 g4x_dp_init(dev_priv, PCH_DP_C, PORT_C); 9065 9066 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED) 9067 g4x_dp_init(dev_priv, PCH_DP_D, PORT_D); 9068 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 9069 bool has_edp, has_port; 9070 9071 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support) 9072 intel_crt_init(dev_priv); 9073 9074 /* 9075 * The DP_DETECTED bit is the latched state of the DDC 9076 * SDA pin at boot. However since eDP doesn't require DDC 9077 * (no way to plug in a DP->HDMI dongle) the DDC pins for 9078 * eDP ports may have been muxed to an alternate function. 9079 * Thus we can't rely on the DP_DETECTED bit alone to detect 9080 * eDP ports. Consult the VBT as well as DP_DETECTED to 9081 * detect eDP ports. 9082 * 9083 * Sadly the straps seem to be missing sometimes even for HDMI 9084 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap 9085 * and VBT for the presence of the port. Additionally we can't 9086 * trust the port type the VBT declares as we've seen at least 9087 * HDMI ports that the VBT claim are DP or eDP. 9088 */ 9089 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B); 9090 has_port = intel_bios_is_port_present(dev_priv, PORT_B); 9091 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port) 9092 has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B); 9093 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) 9094 g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); 9095 9096 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C); 9097 has_port = intel_bios_is_port_present(dev_priv, PORT_C); 9098 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port) 9099 has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C); 9100 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) 9101 g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); 9102 9103 if (IS_CHERRYVIEW(dev_priv)) { 9104 /* 9105 * eDP not supported on port D, 9106 * so no need to worry about it 9107 */ 9108 has_port = intel_bios_is_port_present(dev_priv, PORT_D); 9109 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port) 9110 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D); 9111 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port) 9112 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D); 9113 } 9114 9115 vlv_dsi_init(dev_priv); 9116 } else if (IS_PINEVIEW(dev_priv)) { 9117 intel_lvds_init(dev_priv); 9118 intel_crt_init(dev_priv); 9119 } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) { 9120 bool found = false; 9121 9122 if (IS_MOBILE(dev_priv)) 9123 intel_lvds_init(dev_priv); 9124 9125 intel_crt_init(dev_priv); 9126 9127 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 9128 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n"); 9129 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); 9130 if (!found && IS_G4X(dev_priv)) { 9131 drm_dbg_kms(&dev_priv->drm, 9132 "probing HDMI on SDVOB\n"); 9133 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); 9134 } 9135 9136 if (!found && IS_G4X(dev_priv)) 9137 g4x_dp_init(dev_priv, DP_B, PORT_B); 9138 } 9139 9140 /* Before G4X SDVOC doesn't have its own detect register */ 9141 9142 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 9143 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n"); 9144 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); 9145 } 9146 9147 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) { 9148 9149 if (IS_G4X(dev_priv)) { 9150 drm_dbg_kms(&dev_priv->drm, 9151 "probing HDMI on SDVOC\n"); 9152 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); 9153 } 9154 if (IS_G4X(dev_priv)) 9155 g4x_dp_init(dev_priv, DP_C, PORT_C); 9156 } 9157 9158 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED)) 9159 g4x_dp_init(dev_priv, DP_D, PORT_D); 9160 9161 if (SUPPORTS_TV(dev_priv)) 9162 intel_tv_init(dev_priv); 9163 } else if (DISPLAY_VER(dev_priv) == 2) { 9164 if (IS_I85X(dev_priv)) 9165 intel_lvds_init(dev_priv); 9166 9167 intel_crt_init(dev_priv); 9168 intel_dvo_init(dev_priv); 9169 } 9170 9171 for_each_intel_encoder(&dev_priv->drm, encoder) { 9172 encoder->base.possible_crtcs = 9173 intel_encoder_possible_crtcs(encoder); 9174 encoder->base.possible_clones = 9175 intel_encoder_possible_clones(encoder); 9176 } 9177 9178 intel_init_pch_refclk(dev_priv); 9179 9180 drm_helper_move_panel_connectors_to_head(&dev_priv->drm); 9181 } 9182 9183 static enum drm_mode_status 9184 intel_mode_valid(struct drm_device *dev, 9185 const struct drm_display_mode *mode) 9186 { 9187 struct drm_i915_private *dev_priv = to_i915(dev); 9188 int hdisplay_max, htotal_max; 9189 int vdisplay_max, vtotal_max; 9190 9191 /* 9192 * Can't reject DBLSCAN here because Xorg ddxen can add piles 9193 * of DBLSCAN modes to the output's mode list when they detect 9194 * the scaling mode property on the connector. And they don't 9195 * ask the kernel to validate those modes in any way until 9196 * modeset time at which point the client gets a protocol error. 9197 * So in order to not upset those clients we silently ignore the 9198 * DBLSCAN flag on such connectors. For other connectors we will 9199 * reject modes with the DBLSCAN flag in encoder->compute_config(). 9200 * And we always reject DBLSCAN modes in connector->mode_valid() 9201 * as we never want such modes on the connector's mode list. 9202 */ 9203 9204 if (mode->vscan > 1) 9205 return MODE_NO_VSCAN; 9206 9207 if (mode->flags & DRM_MODE_FLAG_HSKEW) 9208 return MODE_H_ILLEGAL; 9209 9210 if (mode->flags & (DRM_MODE_FLAG_CSYNC | 9211 DRM_MODE_FLAG_NCSYNC | 9212 DRM_MODE_FLAG_PCSYNC)) 9213 return MODE_HSYNC; 9214 9215 if (mode->flags & (DRM_MODE_FLAG_BCAST | 9216 DRM_MODE_FLAG_PIXMUX | 9217 DRM_MODE_FLAG_CLKDIV2)) 9218 return MODE_BAD; 9219 9220 /* Transcoder timing limits */ 9221 if (DISPLAY_VER(dev_priv) >= 11) { 9222 hdisplay_max = 16384; 9223 vdisplay_max = 8192; 9224 htotal_max = 16384; 9225 vtotal_max = 8192; 9226 } else if (DISPLAY_VER(dev_priv) >= 9 || 9227 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 9228 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ 9229 vdisplay_max = 4096; 9230 htotal_max = 8192; 9231 vtotal_max = 8192; 9232 } else if (DISPLAY_VER(dev_priv) >= 3) { 9233 hdisplay_max = 4096; 9234 vdisplay_max = 4096; 9235 htotal_max = 8192; 9236 vtotal_max = 8192; 9237 } else { 9238 hdisplay_max = 2048; 9239 vdisplay_max = 2048; 9240 htotal_max = 4096; 9241 vtotal_max = 4096; 9242 } 9243 9244 if (mode->hdisplay > hdisplay_max || 9245 mode->hsync_start > htotal_max || 9246 mode->hsync_end > htotal_max || 9247 mode->htotal > htotal_max) 9248 return MODE_H_ILLEGAL; 9249 9250 if (mode->vdisplay > vdisplay_max || 9251 mode->vsync_start > vtotal_max || 9252 mode->vsync_end > vtotal_max || 9253 mode->vtotal > vtotal_max) 9254 return MODE_V_ILLEGAL; 9255 9256 if (DISPLAY_VER(dev_priv) >= 5) { 9257 if (mode->hdisplay < 64 || 9258 mode->htotal - mode->hdisplay < 32) 9259 return MODE_H_ILLEGAL; 9260 9261 if (mode->vtotal - mode->vdisplay < 5) 9262 return MODE_V_ILLEGAL; 9263 } else { 9264 if (mode->htotal - mode->hdisplay < 32) 9265 return MODE_H_ILLEGAL; 9266 9267 if (mode->vtotal - mode->vdisplay < 3) 9268 return MODE_V_ILLEGAL; 9269 } 9270 9271 /* 9272 * Cantiga+ cannot handle modes with a hsync front porch of 0. 9273 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. 9274 */ 9275 if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) && 9276 mode->hsync_start == mode->hdisplay) 9277 return MODE_H_ILLEGAL; 9278 9279 return MODE_OK; 9280 } 9281 9282 enum drm_mode_status 9283 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 9284 const struct drm_display_mode *mode, 9285 bool bigjoiner) 9286 { 9287 int plane_width_max, plane_height_max; 9288 9289 /* 9290 * intel_mode_valid() should be 9291 * sufficient on older platforms. 9292 */ 9293 if (DISPLAY_VER(dev_priv) < 9) 9294 return MODE_OK; 9295 9296 /* 9297 * Most people will probably want a fullscreen 9298 * plane so let's not advertize modes that are 9299 * too big for that. 9300 */ 9301 if (DISPLAY_VER(dev_priv) >= 11) { 9302 plane_width_max = 5120 << bigjoiner; 9303 plane_height_max = 4320; 9304 } else { 9305 plane_width_max = 5120; 9306 plane_height_max = 4096; 9307 } 9308 9309 if (mode->hdisplay > plane_width_max) 9310 return MODE_H_ILLEGAL; 9311 9312 if (mode->vdisplay > plane_height_max) 9313 return MODE_V_ILLEGAL; 9314 9315 return MODE_OK; 9316 } 9317 9318 static const struct drm_mode_config_funcs intel_mode_funcs = { 9319 .fb_create = intel_user_framebuffer_create, 9320 .get_format_info = intel_fb_get_format_info, 9321 .output_poll_changed = intel_fbdev_output_poll_changed, 9322 .mode_valid = intel_mode_valid, 9323 .atomic_check = intel_atomic_check, 9324 .atomic_commit = intel_atomic_commit, 9325 .atomic_state_alloc = intel_atomic_state_alloc, 9326 .atomic_state_clear = intel_atomic_state_clear, 9327 .atomic_state_free = intel_atomic_state_free, 9328 }; 9329 9330 static const struct drm_i915_display_funcs skl_display_funcs = { 9331 .get_pipe_config = hsw_get_pipe_config, 9332 .crtc_enable = hsw_crtc_enable, 9333 .crtc_disable = hsw_crtc_disable, 9334 .commit_modeset_enables = skl_commit_modeset_enables, 9335 .get_initial_plane_config = skl_get_initial_plane_config, 9336 }; 9337 9338 static const struct drm_i915_display_funcs ddi_display_funcs = { 9339 .get_pipe_config = hsw_get_pipe_config, 9340 .crtc_enable = hsw_crtc_enable, 9341 .crtc_disable = hsw_crtc_disable, 9342 .commit_modeset_enables = intel_commit_modeset_enables, 9343 .get_initial_plane_config = i9xx_get_initial_plane_config, 9344 }; 9345 9346 static const struct drm_i915_display_funcs pch_split_display_funcs = { 9347 .get_pipe_config = ilk_get_pipe_config, 9348 .crtc_enable = ilk_crtc_enable, 9349 .crtc_disable = ilk_crtc_disable, 9350 .commit_modeset_enables = intel_commit_modeset_enables, 9351 .get_initial_plane_config = i9xx_get_initial_plane_config, 9352 }; 9353 9354 static const struct drm_i915_display_funcs vlv_display_funcs = { 9355 .get_pipe_config = i9xx_get_pipe_config, 9356 .crtc_enable = valleyview_crtc_enable, 9357 .crtc_disable = i9xx_crtc_disable, 9358 .commit_modeset_enables = intel_commit_modeset_enables, 9359 .get_initial_plane_config = i9xx_get_initial_plane_config, 9360 }; 9361 9362 static const struct drm_i915_display_funcs i9xx_display_funcs = { 9363 .get_pipe_config = i9xx_get_pipe_config, 9364 .crtc_enable = i9xx_crtc_enable, 9365 .crtc_disable = i9xx_crtc_disable, 9366 .commit_modeset_enables = intel_commit_modeset_enables, 9367 .get_initial_plane_config = i9xx_get_initial_plane_config, 9368 }; 9369 9370 /** 9371 * intel_init_display_hooks - initialize the display modesetting hooks 9372 * @dev_priv: device private 9373 */ 9374 void intel_init_display_hooks(struct drm_i915_private *dev_priv) 9375 { 9376 if (!HAS_DISPLAY(dev_priv)) 9377 return; 9378 9379 intel_init_cdclk_hooks(dev_priv); 9380 intel_audio_hooks_init(dev_priv); 9381 9382 intel_dpll_init_clock_hook(dev_priv); 9383 9384 if (DISPLAY_VER(dev_priv) >= 9) { 9385 dev_priv->display = &skl_display_funcs; 9386 } else if (HAS_DDI(dev_priv)) { 9387 dev_priv->display = &ddi_display_funcs; 9388 } else if (HAS_PCH_SPLIT(dev_priv)) { 9389 dev_priv->display = &pch_split_display_funcs; 9390 } else if (IS_CHERRYVIEW(dev_priv) || 9391 IS_VALLEYVIEW(dev_priv)) { 9392 dev_priv->display = &vlv_display_funcs; 9393 } else { 9394 dev_priv->display = &i9xx_display_funcs; 9395 } 9396 9397 intel_fdi_init_hook(dev_priv); 9398 } 9399 9400 void intel_modeset_init_hw(struct drm_i915_private *i915) 9401 { 9402 struct intel_cdclk_state *cdclk_state; 9403 9404 if (!HAS_DISPLAY(i915)) 9405 return; 9406 9407 cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state); 9408 9409 intel_update_cdclk(i915); 9410 intel_cdclk_dump_config(i915, &i915->cdclk.hw, "Current CDCLK"); 9411 cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw; 9412 } 9413 9414 static int sanitize_watermarks_add_affected(struct drm_atomic_state *state) 9415 { 9416 struct drm_plane *plane; 9417 struct intel_crtc *crtc; 9418 9419 for_each_intel_crtc(state->dev, crtc) { 9420 struct intel_crtc_state *crtc_state; 9421 9422 crtc_state = intel_atomic_get_crtc_state(state, crtc); 9423 if (IS_ERR(crtc_state)) 9424 return PTR_ERR(crtc_state); 9425 9426 if (crtc_state->hw.active) { 9427 /* 9428 * Preserve the inherited flag to avoid 9429 * taking the full modeset path. 9430 */ 9431 crtc_state->inherited = true; 9432 } 9433 } 9434 9435 drm_for_each_plane(plane, state->dev) { 9436 struct drm_plane_state *plane_state; 9437 9438 plane_state = drm_atomic_get_plane_state(state, plane); 9439 if (IS_ERR(plane_state)) 9440 return PTR_ERR(plane_state); 9441 } 9442 9443 return 0; 9444 } 9445 9446 /* 9447 * Calculate what we think the watermarks should be for the state we've read 9448 * out of the hardware and then immediately program those watermarks so that 9449 * we ensure the hardware settings match our internal state. 9450 * 9451 * We can calculate what we think WM's should be by creating a duplicate of the 9452 * current state (which was constructed during hardware readout) and running it 9453 * through the atomic check code to calculate new watermark values in the 9454 * state object. 9455 */ 9456 static void sanitize_watermarks(struct drm_i915_private *dev_priv) 9457 { 9458 struct drm_atomic_state *state; 9459 struct intel_atomic_state *intel_state; 9460 struct intel_crtc *crtc; 9461 struct intel_crtc_state *crtc_state; 9462 struct drm_modeset_acquire_ctx ctx; 9463 int ret; 9464 int i; 9465 9466 /* Only supported on platforms that use atomic watermark design */ 9467 if (!dev_priv->wm_disp->optimize_watermarks) 9468 return; 9469 9470 state = drm_atomic_state_alloc(&dev_priv->drm); 9471 if (drm_WARN_ON(&dev_priv->drm, !state)) 9472 return; 9473 9474 intel_state = to_intel_atomic_state(state); 9475 9476 drm_modeset_acquire_init(&ctx, 0); 9477 9478 retry: 9479 state->acquire_ctx = &ctx; 9480 9481 /* 9482 * Hardware readout is the only time we don't want to calculate 9483 * intermediate watermarks (since we don't trust the current 9484 * watermarks). 9485 */ 9486 if (!HAS_GMCH(dev_priv)) 9487 intel_state->skip_intermediate_wm = true; 9488 9489 ret = sanitize_watermarks_add_affected(state); 9490 if (ret) 9491 goto fail; 9492 9493 ret = intel_atomic_check(&dev_priv->drm, state); 9494 if (ret) 9495 goto fail; 9496 9497 /* Write calculated watermark values back */ 9498 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) { 9499 crtc_state->wm.need_postvbl_update = true; 9500 intel_optimize_watermarks(intel_state, crtc); 9501 9502 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm; 9503 } 9504 9505 fail: 9506 if (ret == -EDEADLK) { 9507 drm_atomic_state_clear(state); 9508 drm_modeset_backoff(&ctx); 9509 goto retry; 9510 } 9511 9512 /* 9513 * If we fail here, it means that the hardware appears to be 9514 * programmed in a way that shouldn't be possible, given our 9515 * understanding of watermark requirements. This might mean a 9516 * mistake in the hardware readout code or a mistake in the 9517 * watermark calculations for a given platform. Raise a WARN 9518 * so that this is noticeable. 9519 * 9520 * If this actually happens, we'll have to just leave the 9521 * BIOS-programmed watermarks untouched and hope for the best. 9522 */ 9523 drm_WARN(&dev_priv->drm, ret, 9524 "Could not determine valid watermarks for inherited state\n"); 9525 9526 drm_atomic_state_put(state); 9527 9528 drm_modeset_drop_locks(&ctx); 9529 drm_modeset_acquire_fini(&ctx); 9530 } 9531 9532 static int intel_initial_commit(struct drm_device *dev) 9533 { 9534 struct drm_atomic_state *state = NULL; 9535 struct drm_modeset_acquire_ctx ctx; 9536 struct intel_crtc *crtc; 9537 int ret = 0; 9538 9539 state = drm_atomic_state_alloc(dev); 9540 if (!state) 9541 return -ENOMEM; 9542 9543 drm_modeset_acquire_init(&ctx, 0); 9544 9545 retry: 9546 state->acquire_ctx = &ctx; 9547 9548 for_each_intel_crtc(dev, crtc) { 9549 struct intel_crtc_state *crtc_state = 9550 intel_atomic_get_crtc_state(state, crtc); 9551 9552 if (IS_ERR(crtc_state)) { 9553 ret = PTR_ERR(crtc_state); 9554 goto out; 9555 } 9556 9557 if (crtc_state->hw.active) { 9558 struct intel_encoder *encoder; 9559 9560 /* 9561 * We've not yet detected sink capabilities 9562 * (audio,infoframes,etc.) and thus we don't want to 9563 * force a full state recomputation yet. We want that to 9564 * happen only for the first real commit from userspace. 9565 * So preserve the inherited flag for the time being. 9566 */ 9567 crtc_state->inherited = true; 9568 9569 ret = drm_atomic_add_affected_planes(state, &crtc->base); 9570 if (ret) 9571 goto out; 9572 9573 /* 9574 * FIXME hack to force a LUT update to avoid the 9575 * plane update forcing the pipe gamma on without 9576 * having a proper LUT loaded. Remove once we 9577 * have readout for pipe gamma enable. 9578 */ 9579 crtc_state->uapi.color_mgmt_changed = true; 9580 9581 for_each_intel_encoder_mask(dev, encoder, 9582 crtc_state->uapi.encoder_mask) { 9583 if (encoder->initial_fastset_check && 9584 !encoder->initial_fastset_check(encoder, crtc_state)) { 9585 ret = drm_atomic_add_affected_connectors(state, 9586 &crtc->base); 9587 if (ret) 9588 goto out; 9589 } 9590 } 9591 } 9592 } 9593 9594 ret = drm_atomic_commit(state); 9595 9596 out: 9597 if (ret == -EDEADLK) { 9598 drm_atomic_state_clear(state); 9599 drm_modeset_backoff(&ctx); 9600 goto retry; 9601 } 9602 9603 drm_atomic_state_put(state); 9604 9605 drm_modeset_drop_locks(&ctx); 9606 drm_modeset_acquire_fini(&ctx); 9607 9608 return ret; 9609 } 9610 9611 static void intel_mode_config_init(struct drm_i915_private *i915) 9612 { 9613 struct drm_mode_config *mode_config = &i915->drm.mode_config; 9614 9615 drm_mode_config_init(&i915->drm); 9616 INIT_LIST_HEAD(&i915->global_obj_list); 9617 9618 mode_config->min_width = 0; 9619 mode_config->min_height = 0; 9620 9621 mode_config->preferred_depth = 24; 9622 mode_config->prefer_shadow = 1; 9623 9624 mode_config->funcs = &intel_mode_funcs; 9625 9626 mode_config->async_page_flip = HAS_ASYNC_FLIPS(i915); 9627 9628 /* 9629 * Maximum framebuffer dimensions, chosen to match 9630 * the maximum render engine surface size on gen4+. 9631 */ 9632 if (DISPLAY_VER(i915) >= 7) { 9633 mode_config->max_width = 16384; 9634 mode_config->max_height = 16384; 9635 } else if (DISPLAY_VER(i915) >= 4) { 9636 mode_config->max_width = 8192; 9637 mode_config->max_height = 8192; 9638 } else if (DISPLAY_VER(i915) == 3) { 9639 mode_config->max_width = 4096; 9640 mode_config->max_height = 4096; 9641 } else { 9642 mode_config->max_width = 2048; 9643 mode_config->max_height = 2048; 9644 } 9645 9646 if (IS_I845G(i915) || IS_I865G(i915)) { 9647 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512; 9648 mode_config->cursor_height = 1023; 9649 } else if (IS_I830(i915) || IS_I85X(i915) || 9650 IS_I915G(i915) || IS_I915GM(i915)) { 9651 mode_config->cursor_width = 64; 9652 mode_config->cursor_height = 64; 9653 } else { 9654 mode_config->cursor_width = 256; 9655 mode_config->cursor_height = 256; 9656 } 9657 } 9658 9659 static void intel_mode_config_cleanup(struct drm_i915_private *i915) 9660 { 9661 intel_atomic_global_obj_cleanup(i915); 9662 drm_mode_config_cleanup(&i915->drm); 9663 } 9664 9665 /* part #1: call before irq install */ 9666 int intel_modeset_init_noirq(struct drm_i915_private *i915) 9667 { 9668 int ret; 9669 9670 if (i915_inject_probe_failure(i915)) 9671 return -ENODEV; 9672 9673 if (HAS_DISPLAY(i915)) { 9674 ret = drm_vblank_init(&i915->drm, 9675 INTEL_NUM_PIPES(i915)); 9676 if (ret) 9677 return ret; 9678 } 9679 9680 intel_bios_init(i915); 9681 9682 ret = intel_vga_register(i915); 9683 if (ret) 9684 goto cleanup_bios; 9685 9686 /* FIXME: completely on the wrong abstraction layer */ 9687 intel_power_domains_init_hw(i915, false); 9688 9689 if (!HAS_DISPLAY(i915)) 9690 return 0; 9691 9692 intel_dmc_ucode_init(i915); 9693 9694 i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0); 9695 i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI | 9696 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE); 9697 9698 i915->window2_delay = 0; /* No DSB so no window2 delay */ 9699 9700 intel_mode_config_init(i915); 9701 9702 ret = intel_cdclk_init(i915); 9703 if (ret) 9704 goto cleanup_vga_client_pw_domain_dmc; 9705 9706 ret = intel_dbuf_init(i915); 9707 if (ret) 9708 goto cleanup_vga_client_pw_domain_dmc; 9709 9710 ret = intel_bw_init(i915); 9711 if (ret) 9712 goto cleanup_vga_client_pw_domain_dmc; 9713 9714 init_llist_head(&i915->atomic_helper.free_list); 9715 INIT_WORK(&i915->atomic_helper.free_work, 9716 intel_atomic_helper_free_state_worker); 9717 9718 intel_init_quirks(i915); 9719 9720 intel_fbc_init(i915); 9721 9722 return 0; 9723 9724 cleanup_vga_client_pw_domain_dmc: 9725 intel_dmc_ucode_fini(i915); 9726 intel_power_domains_driver_remove(i915); 9727 intel_vga_unregister(i915); 9728 cleanup_bios: 9729 intel_bios_driver_remove(i915); 9730 9731 return ret; 9732 } 9733 9734 /* part #2: call after irq install, but before gem init */ 9735 int intel_modeset_init_nogem(struct drm_i915_private *i915) 9736 { 9737 struct drm_device *dev = &i915->drm; 9738 enum pipe pipe; 9739 struct intel_crtc *crtc; 9740 int ret; 9741 9742 if (!HAS_DISPLAY(i915)) 9743 return 0; 9744 9745 intel_init_pm(i915); 9746 9747 intel_panel_sanitize_ssc(i915); 9748 9749 intel_pps_setup(i915); 9750 9751 intel_gmbus_setup(i915); 9752 9753 drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n", 9754 INTEL_NUM_PIPES(i915), 9755 INTEL_NUM_PIPES(i915) > 1 ? "s" : ""); 9756 9757 for_each_pipe(i915, pipe) { 9758 ret = intel_crtc_init(i915, pipe); 9759 if (ret) { 9760 intel_mode_config_cleanup(i915); 9761 return ret; 9762 } 9763 } 9764 9765 intel_plane_possible_crtcs_init(i915); 9766 intel_shared_dpll_init(dev); 9767 intel_fdi_pll_freq_update(i915); 9768 9769 intel_update_czclk(i915); 9770 intel_modeset_init_hw(i915); 9771 intel_dpll_update_ref_clks(i915); 9772 9773 intel_hdcp_component_init(i915); 9774 9775 if (i915->max_cdclk_freq == 0) 9776 intel_update_max_cdclk(i915); 9777 9778 /* 9779 * If the platform has HTI, we need to find out whether it has reserved 9780 * any display resources before we create our display outputs. 9781 */ 9782 if (INTEL_INFO(i915)->display.has_hti) 9783 i915->hti_state = intel_de_read(i915, HDPORT_STATE); 9784 9785 /* Just disable it once at startup */ 9786 intel_vga_disable(i915); 9787 intel_setup_outputs(i915); 9788 9789 drm_modeset_lock_all(dev); 9790 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx); 9791 intel_acpi_assign_connector_fwnodes(i915); 9792 drm_modeset_unlock_all(dev); 9793 9794 for_each_intel_crtc(dev, crtc) { 9795 if (!to_intel_crtc_state(crtc->base.state)->uapi.active) 9796 continue; 9797 intel_crtc_initial_plane_config(crtc); 9798 } 9799 9800 /* 9801 * Make sure hardware watermarks really match the state we read out. 9802 * Note that we need to do this after reconstructing the BIOS fb's 9803 * since the watermark calculation done here will use pstate->fb. 9804 */ 9805 if (!HAS_GMCH(i915)) 9806 sanitize_watermarks(i915); 9807 9808 return 0; 9809 } 9810 9811 /* part #3: call after gem init */ 9812 int intel_modeset_init(struct drm_i915_private *i915) 9813 { 9814 int ret; 9815 9816 if (!HAS_DISPLAY(i915)) 9817 return 0; 9818 9819 /* 9820 * Force all active planes to recompute their states. So that on 9821 * mode_setcrtc after probe, all the intel_plane_state variables 9822 * are already calculated and there is no assert_plane warnings 9823 * during bootup. 9824 */ 9825 ret = intel_initial_commit(&i915->drm); 9826 if (ret) 9827 drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret); 9828 9829 intel_overlay_setup(i915); 9830 9831 ret = intel_fbdev_init(&i915->drm); 9832 if (ret) 9833 return ret; 9834 9835 /* Only enable hotplug handling once the fbdev is fully set up. */ 9836 intel_hpd_init(i915); 9837 intel_hpd_poll_disable(i915); 9838 9839 intel_init_ipc(i915); 9840 9841 return 0; 9842 } 9843 9844 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 9845 { 9846 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 9847 /* 640x480@60Hz, ~25175 kHz */ 9848 struct dpll clock = { 9849 .m1 = 18, 9850 .m2 = 7, 9851 .p1 = 13, 9852 .p2 = 4, 9853 .n = 2, 9854 }; 9855 u32 dpll, fp; 9856 int i; 9857 9858 drm_WARN_ON(&dev_priv->drm, 9859 i9xx_calc_dpll_params(48000, &clock) != 25154); 9860 9861 drm_dbg_kms(&dev_priv->drm, 9862 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n", 9863 pipe_name(pipe), clock.vco, clock.dot); 9864 9865 fp = i9xx_dpll_compute_fp(&clock); 9866 dpll = DPLL_DVO_2X_MODE | 9867 DPLL_VGA_MODE_DIS | 9868 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | 9869 PLL_P2_DIVIDE_BY_4 | 9870 PLL_REF_INPUT_DREFCLK | 9871 DPLL_VCO_ENABLE; 9872 9873 intel_de_write(dev_priv, FP0(pipe), fp); 9874 intel_de_write(dev_priv, FP1(pipe), fp); 9875 9876 intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16)); 9877 intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16)); 9878 intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16)); 9879 intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16)); 9880 intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16)); 9881 intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16)); 9882 intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1)); 9883 9884 /* 9885 * Apparently we need to have VGA mode enabled prior to changing 9886 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 9887 * dividers, even though the register value does change. 9888 */ 9889 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); 9890 intel_de_write(dev_priv, DPLL(pipe), dpll); 9891 9892 /* Wait for the clocks to stabilize. */ 9893 intel_de_posting_read(dev_priv, DPLL(pipe)); 9894 udelay(150); 9895 9896 /* The pixel multiplier can only be updated once the 9897 * DPLL is enabled and the clocks are stable. 9898 * 9899 * So write it again. 9900 */ 9901 intel_de_write(dev_priv, DPLL(pipe), dpll); 9902 9903 /* We do this three times for luck */ 9904 for (i = 0; i < 3 ; i++) { 9905 intel_de_write(dev_priv, DPLL(pipe), dpll); 9906 intel_de_posting_read(dev_priv, DPLL(pipe)); 9907 udelay(150); /* wait for warmup */ 9908 } 9909 9910 intel_de_write(dev_priv, PIPECONF(pipe), PIPECONF_ENABLE); 9911 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 9912 9913 intel_wait_for_pipe_scanline_moving(crtc); 9914 } 9915 9916 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 9917 { 9918 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 9919 9920 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n", 9921 pipe_name(pipe)); 9922 9923 drm_WARN_ON(&dev_priv->drm, 9924 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE); 9925 drm_WARN_ON(&dev_priv->drm, 9926 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE); 9927 drm_WARN_ON(&dev_priv->drm, 9928 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE); 9929 drm_WARN_ON(&dev_priv->drm, 9930 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK); 9931 drm_WARN_ON(&dev_priv->drm, 9932 intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK); 9933 9934 intel_de_write(dev_priv, PIPECONF(pipe), 0); 9935 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 9936 9937 intel_wait_for_pipe_scanline_stopped(crtc); 9938 9939 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); 9940 intel_de_posting_read(dev_priv, DPLL(pipe)); 9941 } 9942 9943 static void 9944 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv) 9945 { 9946 struct intel_crtc *crtc; 9947 9948 if (DISPLAY_VER(dev_priv) >= 4) 9949 return; 9950 9951 for_each_intel_crtc(&dev_priv->drm, crtc) { 9952 struct intel_plane *plane = 9953 to_intel_plane(crtc->base.primary); 9954 struct intel_crtc *plane_crtc; 9955 enum pipe pipe; 9956 9957 if (!plane->get_hw_state(plane, &pipe)) 9958 continue; 9959 9960 if (pipe == crtc->pipe) 9961 continue; 9962 9963 drm_dbg_kms(&dev_priv->drm, 9964 "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n", 9965 plane->base.base.id, plane->base.name); 9966 9967 plane_crtc = intel_crtc_for_pipe(dev_priv, pipe); 9968 intel_plane_disable_noatomic(plane_crtc, plane); 9969 } 9970 } 9971 9972 static bool intel_crtc_has_encoders(struct intel_crtc *crtc) 9973 { 9974 struct drm_device *dev = crtc->base.dev; 9975 struct intel_encoder *encoder; 9976 9977 for_each_encoder_on_crtc(dev, &crtc->base, encoder) 9978 return true; 9979 9980 return false; 9981 } 9982 9983 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) 9984 { 9985 struct drm_device *dev = encoder->base.dev; 9986 struct intel_connector *connector; 9987 9988 for_each_connector_on_encoder(dev, &encoder->base, connector) 9989 return connector; 9990 9991 return NULL; 9992 } 9993 9994 static void intel_sanitize_crtc(struct intel_crtc *crtc, 9995 struct drm_modeset_acquire_ctx *ctx) 9996 { 9997 struct drm_device *dev = crtc->base.dev; 9998 struct drm_i915_private *dev_priv = to_i915(dev); 9999 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); 10000 10001 if (crtc_state->hw.active) { 10002 struct intel_plane *plane; 10003 10004 /* Disable everything but the primary plane */ 10005 for_each_intel_plane_on_crtc(dev, crtc, plane) { 10006 const struct intel_plane_state *plane_state = 10007 to_intel_plane_state(plane->base.state); 10008 10009 if (plane_state->uapi.visible && 10010 plane->base.type != DRM_PLANE_TYPE_PRIMARY) 10011 intel_plane_disable_noatomic(crtc, plane); 10012 } 10013 10014 /* Disable any background color/etc. set by the BIOS */ 10015 intel_color_commit_noarm(crtc_state); 10016 intel_color_commit_arm(crtc_state); 10017 } 10018 10019 /* Adjust the state of the output pipe according to whether we 10020 * have active connectors/encoders. */ 10021 if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) && 10022 !intel_crtc_is_bigjoiner_slave(crtc_state)) 10023 intel_crtc_disable_noatomic(crtc, ctx); 10024 10025 if (crtc_state->hw.active || HAS_GMCH(dev_priv)) { 10026 /* 10027 * We start out with underrun reporting disabled to avoid races. 10028 * For correct bookkeeping mark this on active crtcs. 10029 * 10030 * Also on gmch platforms we dont have any hardware bits to 10031 * disable the underrun reporting. Which means we need to start 10032 * out with underrun reporting disabled also on inactive pipes, 10033 * since otherwise we'll complain about the garbage we read when 10034 * e.g. coming up after runtime pm. 10035 * 10036 * No protection against concurrent access is required - at 10037 * worst a fifo underrun happens which also sets this to false. 10038 */ 10039 crtc->cpu_fifo_underrun_disabled = true; 10040 /* 10041 * We track the PCH trancoder underrun reporting state 10042 * within the crtc. With crtc for pipe A housing the underrun 10043 * reporting state for PCH transcoder A, crtc for pipe B housing 10044 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, 10045 * and marking underrun reporting as disabled for the non-existing 10046 * PCH transcoders B and C would prevent enabling the south 10047 * error interrupt (see cpt_can_enable_serr_int()). 10048 */ 10049 if (intel_has_pch_trancoder(dev_priv, crtc->pipe)) 10050 crtc->pch_fifo_underrun_disabled = true; 10051 } 10052 } 10053 10054 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state) 10055 { 10056 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 10057 10058 /* 10059 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram 10060 * the hardware when a high res displays plugged in. DPLL P 10061 * divider is zero, and the pipe timings are bonkers. We'll 10062 * try to disable everything in that case. 10063 * 10064 * FIXME would be nice to be able to sanitize this state 10065 * without several WARNs, but for now let's take the easy 10066 * road. 10067 */ 10068 return IS_SANDYBRIDGE(dev_priv) && 10069 crtc_state->hw.active && 10070 crtc_state->shared_dpll && 10071 crtc_state->port_clock == 0; 10072 } 10073 10074 static void intel_sanitize_encoder(struct intel_encoder *encoder) 10075 { 10076 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 10077 struct intel_connector *connector; 10078 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 10079 struct intel_crtc_state *crtc_state = crtc ? 10080 to_intel_crtc_state(crtc->base.state) : NULL; 10081 10082 /* We need to check both for a crtc link (meaning that the 10083 * encoder is active and trying to read from a pipe) and the 10084 * pipe itself being active. */ 10085 bool has_active_crtc = crtc_state && 10086 crtc_state->hw.active; 10087 10088 if (crtc_state && has_bogus_dpll_config(crtc_state)) { 10089 drm_dbg_kms(&dev_priv->drm, 10090 "BIOS has misprogrammed the hardware. Disabling pipe %c\n", 10091 pipe_name(crtc->pipe)); 10092 has_active_crtc = false; 10093 } 10094 10095 connector = intel_encoder_find_connector(encoder); 10096 if (connector && !has_active_crtc) { 10097 drm_dbg_kms(&dev_priv->drm, 10098 "[ENCODER:%d:%s] has active connectors but no active pipe!\n", 10099 encoder->base.base.id, 10100 encoder->base.name); 10101 10102 /* Connector is active, but has no active pipe. This is 10103 * fallout from our resume register restoring. Disable 10104 * the encoder manually again. */ 10105 if (crtc_state) { 10106 struct drm_encoder *best_encoder; 10107 10108 drm_dbg_kms(&dev_priv->drm, 10109 "[ENCODER:%d:%s] manually disabled\n", 10110 encoder->base.base.id, 10111 encoder->base.name); 10112 10113 /* avoid oopsing in case the hooks consult best_encoder */ 10114 best_encoder = connector->base.state->best_encoder; 10115 connector->base.state->best_encoder = &encoder->base; 10116 10117 /* FIXME NULL atomic state passed! */ 10118 if (encoder->disable) 10119 encoder->disable(NULL, encoder, crtc_state, 10120 connector->base.state); 10121 if (encoder->post_disable) 10122 encoder->post_disable(NULL, encoder, crtc_state, 10123 connector->base.state); 10124 10125 connector->base.state->best_encoder = best_encoder; 10126 } 10127 encoder->base.crtc = NULL; 10128 10129 /* Inconsistent output/port/pipe state happens presumably due to 10130 * a bug in one of the get_hw_state functions. Or someplace else 10131 * in our code, like the register restore mess on resume. Clamp 10132 * things to off as a safer default. */ 10133 10134 connector->base.dpms = DRM_MODE_DPMS_OFF; 10135 connector->base.encoder = NULL; 10136 } 10137 10138 /* notify opregion of the sanitized encoder state */ 10139 intel_opregion_notify_encoder(encoder, connector && has_active_crtc); 10140 10141 if (HAS_DDI(dev_priv)) 10142 intel_ddi_sanitize_encoder_pll_mapping(encoder); 10143 } 10144 10145 /* FIXME read out full plane state for all planes */ 10146 static void readout_plane_state(struct drm_i915_private *dev_priv) 10147 { 10148 struct intel_plane *plane; 10149 struct intel_crtc *crtc; 10150 10151 for_each_intel_plane(&dev_priv->drm, plane) { 10152 struct intel_plane_state *plane_state = 10153 to_intel_plane_state(plane->base.state); 10154 struct intel_crtc_state *crtc_state; 10155 enum pipe pipe = PIPE_A; 10156 bool visible; 10157 10158 visible = plane->get_hw_state(plane, &pipe); 10159 10160 crtc = intel_crtc_for_pipe(dev_priv, pipe); 10161 crtc_state = to_intel_crtc_state(crtc->base.state); 10162 10163 intel_set_plane_visible(crtc_state, plane_state, visible); 10164 10165 drm_dbg_kms(&dev_priv->drm, 10166 "[PLANE:%d:%s] hw state readout: %s, pipe %c\n", 10167 plane->base.base.id, plane->base.name, 10168 str_enabled_disabled(visible), pipe_name(pipe)); 10169 } 10170 10171 for_each_intel_crtc(&dev_priv->drm, crtc) { 10172 struct intel_crtc_state *crtc_state = 10173 to_intel_crtc_state(crtc->base.state); 10174 10175 fixup_plane_bitmasks(crtc_state); 10176 } 10177 } 10178 10179 static void intel_modeset_readout_hw_state(struct drm_device *dev) 10180 { 10181 struct drm_i915_private *dev_priv = to_i915(dev); 10182 struct intel_cdclk_state *cdclk_state = 10183 to_intel_cdclk_state(dev_priv->cdclk.obj.state); 10184 struct intel_dbuf_state *dbuf_state = 10185 to_intel_dbuf_state(dev_priv->dbuf.obj.state); 10186 enum pipe pipe; 10187 struct intel_crtc *crtc; 10188 struct intel_encoder *encoder; 10189 struct intel_connector *connector; 10190 struct drm_connector_list_iter conn_iter; 10191 u8 active_pipes = 0; 10192 10193 for_each_intel_crtc(dev, crtc) { 10194 struct intel_crtc_state *crtc_state = 10195 to_intel_crtc_state(crtc->base.state); 10196 10197 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi); 10198 intel_crtc_free_hw_state(crtc_state); 10199 intel_crtc_state_reset(crtc_state, crtc); 10200 10201 intel_crtc_get_pipe_config(crtc_state); 10202 10203 crtc_state->hw.enable = crtc_state->hw.active; 10204 10205 crtc->base.enabled = crtc_state->hw.enable; 10206 crtc->active = crtc_state->hw.active; 10207 10208 if (crtc_state->hw.active) 10209 active_pipes |= BIT(crtc->pipe); 10210 10211 drm_dbg_kms(&dev_priv->drm, 10212 "[CRTC:%d:%s] hw state readout: %s\n", 10213 crtc->base.base.id, crtc->base.name, 10214 str_enabled_disabled(crtc_state->hw.active)); 10215 } 10216 10217 cdclk_state->active_pipes = dbuf_state->active_pipes = active_pipes; 10218 10219 readout_plane_state(dev_priv); 10220 10221 for_each_intel_encoder(dev, encoder) { 10222 struct intel_crtc_state *crtc_state = NULL; 10223 10224 pipe = 0; 10225 10226 if (encoder->get_hw_state(encoder, &pipe)) { 10227 crtc = intel_crtc_for_pipe(dev_priv, pipe); 10228 crtc_state = to_intel_crtc_state(crtc->base.state); 10229 10230 encoder->base.crtc = &crtc->base; 10231 intel_encoder_get_config(encoder, crtc_state); 10232 10233 /* read out to slave crtc as well for bigjoiner */ 10234 if (crtc_state->bigjoiner_pipes) { 10235 struct intel_crtc *slave_crtc; 10236 10237 /* encoder should read be linked to bigjoiner master */ 10238 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 10239 10240 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc, 10241 intel_crtc_bigjoiner_slave_pipes(crtc_state)) { 10242 struct intel_crtc_state *slave_crtc_state; 10243 10244 slave_crtc_state = to_intel_crtc_state(slave_crtc->base.state); 10245 intel_encoder_get_config(encoder, slave_crtc_state); 10246 } 10247 } 10248 } else { 10249 encoder->base.crtc = NULL; 10250 } 10251 10252 if (encoder->sync_state) 10253 encoder->sync_state(encoder, crtc_state); 10254 10255 drm_dbg_kms(&dev_priv->drm, 10256 "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", 10257 encoder->base.base.id, encoder->base.name, 10258 str_enabled_disabled(encoder->base.crtc), 10259 pipe_name(pipe)); 10260 } 10261 10262 intel_dpll_readout_hw_state(dev_priv); 10263 10264 drm_connector_list_iter_begin(dev, &conn_iter); 10265 for_each_intel_connector_iter(connector, &conn_iter) { 10266 if (connector->get_hw_state(connector)) { 10267 struct intel_crtc_state *crtc_state; 10268 struct intel_crtc *crtc; 10269 10270 connector->base.dpms = DRM_MODE_DPMS_ON; 10271 10272 encoder = intel_attached_encoder(connector); 10273 connector->base.encoder = &encoder->base; 10274 10275 crtc = to_intel_crtc(encoder->base.crtc); 10276 crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL; 10277 10278 if (crtc_state && crtc_state->hw.active) { 10279 /* 10280 * This has to be done during hardware readout 10281 * because anything calling .crtc_disable may 10282 * rely on the connector_mask being accurate. 10283 */ 10284 crtc_state->uapi.connector_mask |= 10285 drm_connector_mask(&connector->base); 10286 crtc_state->uapi.encoder_mask |= 10287 drm_encoder_mask(&encoder->base); 10288 } 10289 } else { 10290 connector->base.dpms = DRM_MODE_DPMS_OFF; 10291 connector->base.encoder = NULL; 10292 } 10293 drm_dbg_kms(&dev_priv->drm, 10294 "[CONNECTOR:%d:%s] hw state readout: %s\n", 10295 connector->base.base.id, connector->base.name, 10296 str_enabled_disabled(connector->base.encoder)); 10297 } 10298 drm_connector_list_iter_end(&conn_iter); 10299 10300 for_each_intel_crtc(dev, crtc) { 10301 struct intel_bw_state *bw_state = 10302 to_intel_bw_state(dev_priv->bw_obj.state); 10303 struct intel_crtc_state *crtc_state = 10304 to_intel_crtc_state(crtc->base.state); 10305 struct intel_plane *plane; 10306 int min_cdclk = 0; 10307 10308 if (crtc_state->hw.active) { 10309 /* 10310 * The initial mode needs to be set in order to keep 10311 * the atomic core happy. It wants a valid mode if the 10312 * crtc's enabled, so we do the above call. 10313 * 10314 * But we don't set all the derived state fully, hence 10315 * set a flag to indicate that a full recalculation is 10316 * needed on the next commit. 10317 */ 10318 crtc_state->inherited = true; 10319 10320 intel_crtc_update_active_timings(crtc_state); 10321 10322 intel_crtc_copy_hw_to_uapi_state(crtc_state); 10323 } 10324 10325 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 10326 const struct intel_plane_state *plane_state = 10327 to_intel_plane_state(plane->base.state); 10328 10329 /* 10330 * FIXME don't have the fb yet, so can't 10331 * use intel_plane_data_rate() :( 10332 */ 10333 if (plane_state->uapi.visible) 10334 crtc_state->data_rate[plane->id] = 10335 4 * crtc_state->pixel_rate; 10336 /* 10337 * FIXME don't have the fb yet, so can't 10338 * use plane->min_cdclk() :( 10339 */ 10340 if (plane_state->uapi.visible && plane->min_cdclk) { 10341 if (crtc_state->double_wide || DISPLAY_VER(dev_priv) >= 10) 10342 crtc_state->min_cdclk[plane->id] = 10343 DIV_ROUND_UP(crtc_state->pixel_rate, 2); 10344 else 10345 crtc_state->min_cdclk[plane->id] = 10346 crtc_state->pixel_rate; 10347 } 10348 drm_dbg_kms(&dev_priv->drm, 10349 "[PLANE:%d:%s] min_cdclk %d kHz\n", 10350 plane->base.base.id, plane->base.name, 10351 crtc_state->min_cdclk[plane->id]); 10352 } 10353 10354 if (crtc_state->hw.active) { 10355 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); 10356 if (drm_WARN_ON(dev, min_cdclk < 0)) 10357 min_cdclk = 0; 10358 } 10359 10360 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; 10361 cdclk_state->min_voltage_level[crtc->pipe] = 10362 crtc_state->min_voltage_level; 10363 10364 intel_bw_crtc_update(bw_state, crtc_state); 10365 10366 intel_pipe_config_sanity_check(dev_priv, crtc_state); 10367 } 10368 } 10369 10370 static void 10371 get_encoder_power_domains(struct drm_i915_private *dev_priv) 10372 { 10373 struct intel_encoder *encoder; 10374 10375 for_each_intel_encoder(&dev_priv->drm, encoder) { 10376 struct intel_crtc_state *crtc_state; 10377 10378 if (!encoder->get_power_domains) 10379 continue; 10380 10381 /* 10382 * MST-primary and inactive encoders don't have a crtc state 10383 * and neither of these require any power domain references. 10384 */ 10385 if (!encoder->base.crtc) 10386 continue; 10387 10388 crtc_state = to_intel_crtc_state(encoder->base.crtc->state); 10389 encoder->get_power_domains(encoder, crtc_state); 10390 } 10391 } 10392 10393 static void intel_early_display_was(struct drm_i915_private *dev_priv) 10394 { 10395 /* 10396 * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl 10397 * Also known as Wa_14010480278. 10398 */ 10399 if (IS_DISPLAY_VER(dev_priv, 10, 12)) 10400 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0, 10401 intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS); 10402 10403 if (IS_HASWELL(dev_priv)) { 10404 /* 10405 * WaRsPkgCStateDisplayPMReq:hsw 10406 * System hang if this isn't done before disabling all planes! 10407 */ 10408 intel_de_write(dev_priv, CHICKEN_PAR1_1, 10409 intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); 10410 } 10411 10412 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) { 10413 /* Display WA #1142:kbl,cfl,cml */ 10414 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 10415 KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22); 10416 intel_de_rmw(dev_priv, CHICKEN_MISC_2, 10417 KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14, 10418 KBL_ARB_FILL_SPARE_14); 10419 } 10420 } 10421 10422 10423 /* Scan out the current hw modeset state, 10424 * and sanitizes it to the current state 10425 */ 10426 static void 10427 intel_modeset_setup_hw_state(struct drm_device *dev, 10428 struct drm_modeset_acquire_ctx *ctx) 10429 { 10430 struct drm_i915_private *dev_priv = to_i915(dev); 10431 struct intel_encoder *encoder; 10432 struct intel_crtc *crtc; 10433 intel_wakeref_t wakeref; 10434 10435 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 10436 10437 intel_early_display_was(dev_priv); 10438 intel_modeset_readout_hw_state(dev); 10439 10440 /* HW state is read out, now we need to sanitize this mess. */ 10441 get_encoder_power_domains(dev_priv); 10442 10443 intel_pch_sanitize(dev_priv); 10444 10445 /* 10446 * intel_sanitize_plane_mapping() may need to do vblank 10447 * waits, so we need vblank interrupts restored beforehand. 10448 */ 10449 for_each_intel_crtc(&dev_priv->drm, crtc) { 10450 struct intel_crtc_state *crtc_state = 10451 to_intel_crtc_state(crtc->base.state); 10452 10453 drm_crtc_vblank_reset(&crtc->base); 10454 10455 if (crtc_state->hw.active) 10456 intel_crtc_vblank_on(crtc_state); 10457 } 10458 10459 intel_sanitize_plane_mapping(dev_priv); 10460 10461 for_each_intel_encoder(dev, encoder) 10462 intel_sanitize_encoder(encoder); 10463 10464 for_each_intel_crtc(&dev_priv->drm, crtc) { 10465 struct intel_crtc_state *crtc_state = 10466 to_intel_crtc_state(crtc->base.state); 10467 10468 intel_sanitize_crtc(crtc, ctx); 10469 intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]"); 10470 } 10471 10472 intel_modeset_update_connector_atomic_state(dev); 10473 10474 intel_dpll_sanitize_state(dev_priv); 10475 10476 if (IS_G4X(dev_priv)) { 10477 g4x_wm_get_hw_state(dev_priv); 10478 g4x_wm_sanitize(dev_priv); 10479 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 10480 vlv_wm_get_hw_state(dev_priv); 10481 vlv_wm_sanitize(dev_priv); 10482 } else if (DISPLAY_VER(dev_priv) >= 9) { 10483 skl_wm_get_hw_state(dev_priv); 10484 skl_wm_sanitize(dev_priv); 10485 } else if (HAS_PCH_SPLIT(dev_priv)) { 10486 ilk_wm_get_hw_state(dev_priv); 10487 } 10488 10489 for_each_intel_crtc(dev, crtc) { 10490 struct intel_crtc_state *crtc_state = 10491 to_intel_crtc_state(crtc->base.state); 10492 u64 put_domains; 10493 10494 put_domains = modeset_get_crtc_power_domains(crtc_state); 10495 if (drm_WARN_ON(dev, put_domains)) 10496 modeset_put_crtc_power_domains(crtc, put_domains); 10497 } 10498 10499 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref); 10500 10501 intel_power_domains_sanitize_state(dev_priv); 10502 } 10503 10504 void intel_display_resume(struct drm_device *dev) 10505 { 10506 struct drm_i915_private *dev_priv = to_i915(dev); 10507 struct drm_atomic_state *state = dev_priv->modeset_restore_state; 10508 struct drm_modeset_acquire_ctx ctx; 10509 int ret; 10510 10511 if (!HAS_DISPLAY(dev_priv)) 10512 return; 10513 10514 dev_priv->modeset_restore_state = NULL; 10515 if (state) 10516 state->acquire_ctx = &ctx; 10517 10518 drm_modeset_acquire_init(&ctx, 0); 10519 10520 while (1) { 10521 ret = drm_modeset_lock_all_ctx(dev, &ctx); 10522 if (ret != -EDEADLK) 10523 break; 10524 10525 drm_modeset_backoff(&ctx); 10526 } 10527 10528 if (!ret) 10529 ret = __intel_display_resume(dev, state, &ctx); 10530 10531 intel_enable_ipc(dev_priv); 10532 drm_modeset_drop_locks(&ctx); 10533 drm_modeset_acquire_fini(&ctx); 10534 10535 if (ret) 10536 drm_err(&dev_priv->drm, 10537 "Restoring old state failed with %i\n", ret); 10538 if (state) 10539 drm_atomic_state_put(state); 10540 } 10541 10542 static void intel_hpd_poll_fini(struct drm_i915_private *i915) 10543 { 10544 struct intel_connector *connector; 10545 struct drm_connector_list_iter conn_iter; 10546 10547 /* Kill all the work that may have been queued by hpd. */ 10548 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 10549 for_each_intel_connector_iter(connector, &conn_iter) { 10550 if (connector->modeset_retry_work.func) 10551 cancel_work_sync(&connector->modeset_retry_work); 10552 if (connector->hdcp.shim) { 10553 cancel_delayed_work_sync(&connector->hdcp.check_work); 10554 cancel_work_sync(&connector->hdcp.prop_work); 10555 } 10556 } 10557 drm_connector_list_iter_end(&conn_iter); 10558 } 10559 10560 /* part #1: call before irq uninstall */ 10561 void intel_modeset_driver_remove(struct drm_i915_private *i915) 10562 { 10563 if (!HAS_DISPLAY(i915)) 10564 return; 10565 10566 flush_workqueue(i915->flip_wq); 10567 flush_workqueue(i915->modeset_wq); 10568 10569 flush_work(&i915->atomic_helper.free_work); 10570 drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list)); 10571 } 10572 10573 /* part #2: call after irq uninstall */ 10574 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915) 10575 { 10576 if (!HAS_DISPLAY(i915)) 10577 return; 10578 10579 /* 10580 * Due to the hpd irq storm handling the hotplug work can re-arm the 10581 * poll handlers. Hence disable polling after hpd handling is shut down. 10582 */ 10583 intel_hpd_poll_fini(i915); 10584 10585 /* 10586 * MST topology needs to be suspended so we don't have any calls to 10587 * fbdev after it's finalized. MST will be destroyed later as part of 10588 * drm_mode_config_cleanup() 10589 */ 10590 intel_dp_mst_suspend(i915); 10591 10592 /* poll work can call into fbdev, hence clean that up afterwards */ 10593 intel_fbdev_fini(i915); 10594 10595 intel_unregister_dsm_handler(); 10596 10597 intel_fbc_global_disable(i915); 10598 10599 /* flush any delayed tasks or pending work */ 10600 flush_scheduled_work(); 10601 10602 intel_hdcp_component_fini(i915); 10603 10604 intel_mode_config_cleanup(i915); 10605 10606 intel_overlay_cleanup(i915); 10607 10608 intel_gmbus_teardown(i915); 10609 10610 destroy_workqueue(i915->flip_wq); 10611 destroy_workqueue(i915->modeset_wq); 10612 10613 intel_fbc_cleanup(i915); 10614 } 10615 10616 /* part #3: call after gem init */ 10617 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915) 10618 { 10619 intel_dmc_ucode_fini(i915); 10620 10621 intel_power_domains_driver_remove(i915); 10622 10623 intel_vga_unregister(i915); 10624 10625 intel_bios_driver_remove(i915); 10626 } 10627 10628 bool intel_modeset_probe_defer(struct pci_dev *pdev) 10629 { 10630 struct drm_privacy_screen *privacy_screen; 10631 10632 /* 10633 * apple-gmux is needed on dual GPU MacBook Pro 10634 * to probe the panel if we're the inactive GPU. 10635 */ 10636 if (vga_switcheroo_client_probe_defer(pdev)) 10637 return true; 10638 10639 /* If the LCD panel has a privacy-screen, wait for it */ 10640 privacy_screen = drm_privacy_screen_get(&pdev->dev, NULL); 10641 if (IS_ERR(privacy_screen) && PTR_ERR(privacy_screen) == -EPROBE_DEFER) 10642 return true; 10643 10644 drm_privacy_screen_put(privacy_screen); 10645 10646 return false; 10647 } 10648 10649 void intel_display_driver_register(struct drm_i915_private *i915) 10650 { 10651 if (!HAS_DISPLAY(i915)) 10652 return; 10653 10654 intel_display_debugfs_register(i915); 10655 10656 /* Must be done after probing outputs */ 10657 intel_opregion_register(i915); 10658 acpi_video_register(); 10659 10660 intel_audio_init(i915); 10661 10662 /* 10663 * Some ports require correctly set-up hpd registers for 10664 * detection to work properly (leading to ghost connected 10665 * connector status), e.g. VGA on gm45. Hence we can only set 10666 * up the initial fbdev config after hpd irqs are fully 10667 * enabled. We do it last so that the async config cannot run 10668 * before the connectors are registered. 10669 */ 10670 intel_fbdev_initial_config_async(&i915->drm); 10671 10672 /* 10673 * We need to coordinate the hotplugs with the asynchronous 10674 * fbdev configuration, for which we use the 10675 * fbdev->async_cookie. 10676 */ 10677 drm_kms_helper_poll_init(&i915->drm); 10678 } 10679 10680 void intel_display_driver_unregister(struct drm_i915_private *i915) 10681 { 10682 if (!HAS_DISPLAY(i915)) 10683 return; 10684 10685 intel_fbdev_unregister(i915); 10686 intel_audio_deinit(i915); 10687 10688 /* 10689 * After flushing the fbdev (incl. a late async config which 10690 * will have delayed queuing of a hotplug event), then flush 10691 * the hotplug events. 10692 */ 10693 drm_kms_helper_poll_fini(&i915->drm); 10694 drm_atomic_helper_shutdown(&i915->drm); 10695 10696 acpi_video_unregister(); 10697 intel_opregion_unregister(i915); 10698 } 10699