1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <acpi/video.h> 28 #include <linux/i2c.h> 29 #include <linux/input.h> 30 #include <linux/intel-iommu.h> 31 #include <linux/kernel.h> 32 #include <linux/module.h> 33 #include <linux/dma-resv.h> 34 #include <linux/slab.h> 35 #include <linux/string_helpers.h> 36 #include <linux/vga_switcheroo.h> 37 38 #include <drm/drm_atomic.h> 39 #include <drm/drm_atomic_helper.h> 40 #include <drm/drm_atomic_uapi.h> 41 #include <drm/drm_damage_helper.h> 42 #include <drm/dp/drm_dp_helper.h> 43 #include <drm/drm_edid.h> 44 #include <drm/drm_fourcc.h> 45 #include <drm/drm_plane_helper.h> 46 #include <drm/drm_privacy_screen_consumer.h> 47 #include <drm/drm_probe_helper.h> 48 #include <drm/drm_rect.h> 49 50 #include "display/intel_audio.h" 51 #include "display/intel_crt.h" 52 #include "display/intel_ddi.h" 53 #include "display/intel_display_debugfs.h" 54 #include "display/intel_display_power.h" 55 #include "display/intel_dp.h" 56 #include "display/intel_dp_mst.h" 57 #include "display/intel_dpll.h" 58 #include "display/intel_dpll_mgr.h" 59 #include "display/intel_drrs.h" 60 #include "display/intel_dsi.h" 61 #include "display/intel_dvo.h" 62 #include "display/intel_fb.h" 63 #include "display/intel_gmbus.h" 64 #include "display/intel_hdmi.h" 65 #include "display/intel_lvds.h" 66 #include "display/intel_sdvo.h" 67 #include "display/intel_snps_phy.h" 68 #include "display/intel_tv.h" 69 #include "display/intel_vdsc.h" 70 #include "display/intel_vrr.h" 71 72 #include "gem/i915_gem_lmem.h" 73 #include "gem/i915_gem_object.h" 74 75 #include "gt/gen8_ppgtt.h" 76 77 #include "g4x_dp.h" 78 #include "g4x_hdmi.h" 79 #include "hsw_ips.h" 80 #include "i915_drv.h" 81 #include "i915_utils.h" 82 #include "icl_dsi.h" 83 #include "intel_acpi.h" 84 #include "intel_atomic.h" 85 #include "intel_atomic_plane.h" 86 #include "intel_bw.h" 87 #include "intel_cdclk.h" 88 #include "intel_color.h" 89 #include "intel_crtc.h" 90 #include "intel_de.h" 91 #include "intel_display_types.h" 92 #include "intel_dmc.h" 93 #include "intel_dp_link_training.h" 94 #include "intel_dpt.h" 95 #include "intel_fbc.h" 96 #include "intel_fbdev.h" 97 #include "intel_fdi.h" 98 #include "intel_fifo_underrun.h" 99 #include "intel_frontbuffer.h" 100 #include "intel_hdcp.h" 101 #include "intel_hotplug.h" 102 #include "intel_modeset_verify.h" 103 #include "intel_overlay.h" 104 #include "intel_panel.h" 105 #include "intel_pch_display.h" 106 #include "intel_pch_refclk.h" 107 #include "intel_pcode.h" 108 #include "intel_pipe_crc.h" 109 #include "intel_plane_initial.h" 110 #include "intel_pm.h" 111 #include "intel_pps.h" 112 #include "intel_psr.h" 113 #include "intel_quirks.h" 114 #include "intel_sprite.h" 115 #include "intel_tc.h" 116 #include "intel_vga.h" 117 #include "i9xx_plane.h" 118 #include "skl_scaler.h" 119 #include "skl_universal_plane.h" 120 #include "vlv_dsi.h" 121 #include "vlv_dsi_pll.h" 122 #include "vlv_dsi_regs.h" 123 #include "vlv_sideband.h" 124 125 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state); 126 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state); 127 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state); 128 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state); 129 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state); 130 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state); 131 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state); 132 static void intel_modeset_setup_hw_state(struct drm_device *dev, 133 struct drm_modeset_acquire_ctx *ctx); 134 135 /** 136 * intel_update_watermarks - update FIFO watermark values based on current modes 137 * @dev_priv: i915 device 138 * 139 * Calculate watermark values for the various WM regs based on current mode 140 * and plane configuration. 141 * 142 * There are several cases to deal with here: 143 * - normal (i.e. non-self-refresh) 144 * - self-refresh (SR) mode 145 * - lines are large relative to FIFO size (buffer can hold up to 2) 146 * - lines are small relative to FIFO size (buffer can hold more than 2 147 * lines), so need to account for TLB latency 148 * 149 * The normal calculation is: 150 * watermark = dotclock * bytes per pixel * latency 151 * where latency is platform & configuration dependent (we assume pessimal 152 * values here). 153 * 154 * The SR calculation is: 155 * watermark = (trunc(latency/line time)+1) * surface width * 156 * bytes per pixel 157 * where 158 * line time = htotal / dotclock 159 * surface width = hdisplay for normal plane and 64 for cursor 160 * and latency is assumed to be high, as above. 161 * 162 * The final value programmed to the register should always be rounded up, 163 * and include an extra 2 entries to account for clock crossings. 164 * 165 * We don't use the sprite, so we can ignore that. And on Crestline we have 166 * to set the non-SR watermarks to 8. 167 */ 168 static void intel_update_watermarks(struct drm_i915_private *dev_priv) 169 { 170 if (dev_priv->wm_disp->update_wm) 171 dev_priv->wm_disp->update_wm(dev_priv); 172 } 173 174 static int intel_compute_pipe_wm(struct intel_atomic_state *state, 175 struct intel_crtc *crtc) 176 { 177 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 178 if (dev_priv->wm_disp->compute_pipe_wm) 179 return dev_priv->wm_disp->compute_pipe_wm(state, crtc); 180 return 0; 181 } 182 183 static int intel_compute_intermediate_wm(struct intel_atomic_state *state, 184 struct intel_crtc *crtc) 185 { 186 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 187 if (!dev_priv->wm_disp->compute_intermediate_wm) 188 return 0; 189 if (drm_WARN_ON(&dev_priv->drm, 190 !dev_priv->wm_disp->compute_pipe_wm)) 191 return 0; 192 return dev_priv->wm_disp->compute_intermediate_wm(state, crtc); 193 } 194 195 static bool intel_initial_watermarks(struct intel_atomic_state *state, 196 struct intel_crtc *crtc) 197 { 198 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 199 if (dev_priv->wm_disp->initial_watermarks) { 200 dev_priv->wm_disp->initial_watermarks(state, crtc); 201 return true; 202 } 203 return false; 204 } 205 206 static void intel_atomic_update_watermarks(struct intel_atomic_state *state, 207 struct intel_crtc *crtc) 208 { 209 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 210 if (dev_priv->wm_disp->atomic_update_watermarks) 211 dev_priv->wm_disp->atomic_update_watermarks(state, crtc); 212 } 213 214 static void intel_optimize_watermarks(struct intel_atomic_state *state, 215 struct intel_crtc *crtc) 216 { 217 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 218 if (dev_priv->wm_disp->optimize_watermarks) 219 dev_priv->wm_disp->optimize_watermarks(state, crtc); 220 } 221 222 static int intel_compute_global_watermarks(struct intel_atomic_state *state) 223 { 224 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 225 if (dev_priv->wm_disp->compute_global_watermarks) 226 return dev_priv->wm_disp->compute_global_watermarks(state); 227 return 0; 228 } 229 230 /* returns HPLL frequency in kHz */ 231 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) 232 { 233 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; 234 235 /* Obtain SKU information */ 236 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & 237 CCK_FUSE_HPLL_FREQ_MASK; 238 239 return vco_freq[hpll_freq] * 1000; 240 } 241 242 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 243 const char *name, u32 reg, int ref_freq) 244 { 245 u32 val; 246 int divider; 247 248 val = vlv_cck_read(dev_priv, reg); 249 divider = val & CCK_FREQUENCY_VALUES; 250 251 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != 252 (divider << CCK_FREQUENCY_STATUS_SHIFT), 253 "%s change in progress\n", name); 254 255 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); 256 } 257 258 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 259 const char *name, u32 reg) 260 { 261 int hpll; 262 263 vlv_cck_get(dev_priv); 264 265 if (dev_priv->hpll_freq == 0) 266 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); 267 268 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); 269 270 vlv_cck_put(dev_priv); 271 272 return hpll; 273 } 274 275 static void intel_update_czclk(struct drm_i915_private *dev_priv) 276 { 277 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) 278 return; 279 280 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", 281 CCK_CZ_CLOCK_CONTROL); 282 283 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", 284 dev_priv->czclk_freq); 285 } 286 287 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state) 288 { 289 return (crtc_state->active_planes & 290 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0; 291 } 292 293 /* WA Display #0827: Gen9:all */ 294 static void 295 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) 296 { 297 if (enable) 298 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 299 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS); 300 else 301 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 302 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS)); 303 } 304 305 /* Wa_2006604312:icl,ehl */ 306 static void 307 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 308 bool enable) 309 { 310 if (enable) 311 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 312 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS); 313 else 314 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 315 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS); 316 } 317 318 /* Wa_1604331009:icl,jsl,ehl */ 319 static void 320 icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 321 bool enable) 322 { 323 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), CURSOR_GATING_DIS, 324 enable ? CURSOR_GATING_DIS : 0); 325 } 326 327 static bool 328 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state) 329 { 330 return crtc_state->master_transcoder != INVALID_TRANSCODER; 331 } 332 333 static bool 334 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state) 335 { 336 return crtc_state->sync_mode_slaves_mask != 0; 337 } 338 339 bool 340 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state) 341 { 342 return is_trans_port_sync_master(crtc_state) || 343 is_trans_port_sync_slave(crtc_state); 344 } 345 346 static enum pipe bigjoiner_master_pipe(const struct intel_crtc_state *crtc_state) 347 { 348 return ffs(crtc_state->bigjoiner_pipes) - 1; 349 } 350 351 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state) 352 { 353 if (crtc_state->bigjoiner_pipes) 354 return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state)); 355 else 356 return 0; 357 } 358 359 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state) 360 { 361 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 362 363 return crtc_state->bigjoiner_pipes && 364 crtc->pipe != bigjoiner_master_pipe(crtc_state); 365 } 366 367 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state) 368 { 369 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 370 371 return crtc_state->bigjoiner_pipes && 372 crtc->pipe == bigjoiner_master_pipe(crtc_state); 373 } 374 375 static int intel_bigjoiner_num_pipes(const struct intel_crtc_state *crtc_state) 376 { 377 return hweight8(crtc_state->bigjoiner_pipes); 378 } 379 380 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state) 381 { 382 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 383 384 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 385 return intel_crtc_for_pipe(i915, bigjoiner_master_pipe(crtc_state)); 386 else 387 return to_intel_crtc(crtc_state->uapi.crtc); 388 } 389 390 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv, 391 enum pipe pipe) 392 { 393 i915_reg_t reg = PIPEDSL(pipe); 394 u32 line1, line2; 395 396 line1 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK; 397 msleep(5); 398 line2 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK; 399 400 return line1 != line2; 401 } 402 403 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state) 404 { 405 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 406 enum pipe pipe = crtc->pipe; 407 408 /* Wait for the display line to settle/start moving */ 409 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100)) 410 drm_err(&dev_priv->drm, 411 "pipe %c scanline %s wait timed out\n", 412 pipe_name(pipe), str_on_off(state)); 413 } 414 415 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc) 416 { 417 wait_for_pipe_scanline_moving(crtc, false); 418 } 419 420 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc) 421 { 422 wait_for_pipe_scanline_moving(crtc, true); 423 } 424 425 static void 426 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) 427 { 428 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 429 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 430 431 if (DISPLAY_VER(dev_priv) >= 4) { 432 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 433 434 /* Wait for the Pipe State to go off */ 435 if (intel_de_wait_for_clear(dev_priv, PIPECONF(cpu_transcoder), 436 PIPECONF_STATE_ENABLE, 100)) 437 drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n"); 438 } else { 439 intel_wait_for_pipe_scanline_stopped(crtc); 440 } 441 } 442 443 void assert_transcoder(struct drm_i915_private *dev_priv, 444 enum transcoder cpu_transcoder, bool state) 445 { 446 bool cur_state; 447 enum intel_display_power_domain power_domain; 448 intel_wakeref_t wakeref; 449 450 /* we keep both pipes enabled on 830 */ 451 if (IS_I830(dev_priv)) 452 state = true; 453 454 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 455 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 456 if (wakeref) { 457 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); 458 cur_state = !!(val & PIPECONF_ENABLE); 459 460 intel_display_power_put(dev_priv, power_domain, wakeref); 461 } else { 462 cur_state = false; 463 } 464 465 I915_STATE_WARN(cur_state != state, 466 "transcoder %s assertion failure (expected %s, current %s)\n", 467 transcoder_name(cpu_transcoder), 468 str_on_off(state), str_on_off(cur_state)); 469 } 470 471 static void assert_plane(struct intel_plane *plane, bool state) 472 { 473 enum pipe pipe; 474 bool cur_state; 475 476 cur_state = plane->get_hw_state(plane, &pipe); 477 478 I915_STATE_WARN(cur_state != state, 479 "%s assertion failure (expected %s, current %s)\n", 480 plane->base.name, str_on_off(state), 481 str_on_off(cur_state)); 482 } 483 484 #define assert_plane_enabled(p) assert_plane(p, true) 485 #define assert_plane_disabled(p) assert_plane(p, false) 486 487 static void assert_planes_disabled(struct intel_crtc *crtc) 488 { 489 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 490 struct intel_plane *plane; 491 492 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) 493 assert_plane_disabled(plane); 494 } 495 496 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 497 struct intel_digital_port *dig_port, 498 unsigned int expected_mask) 499 { 500 u32 port_mask; 501 i915_reg_t dpll_reg; 502 503 switch (dig_port->base.port) { 504 default: 505 MISSING_CASE(dig_port->base.port); 506 fallthrough; 507 case PORT_B: 508 port_mask = DPLL_PORTB_READY_MASK; 509 dpll_reg = DPLL(0); 510 break; 511 case PORT_C: 512 port_mask = DPLL_PORTC_READY_MASK; 513 dpll_reg = DPLL(0); 514 expected_mask <<= 4; 515 break; 516 case PORT_D: 517 port_mask = DPLL_PORTD_READY_MASK; 518 dpll_reg = DPIO_PHY_STATUS; 519 break; 520 } 521 522 if (intel_de_wait_for_register(dev_priv, dpll_reg, 523 port_mask, expected_mask, 1000)) 524 drm_WARN(&dev_priv->drm, 1, 525 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", 526 dig_port->base.base.base.id, dig_port->base.base.name, 527 intel_de_read(dev_priv, dpll_reg) & port_mask, 528 expected_mask); 529 } 530 531 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) 532 { 533 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 534 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 535 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 536 enum pipe pipe = crtc->pipe; 537 i915_reg_t reg; 538 u32 val; 539 540 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe)); 541 542 assert_planes_disabled(crtc); 543 544 /* 545 * A pipe without a PLL won't actually be able to drive bits from 546 * a plane. On ILK+ the pipe PLLs are integrated, so we don't 547 * need the check. 548 */ 549 if (HAS_GMCH(dev_priv)) { 550 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI)) 551 assert_dsi_pll_enabled(dev_priv); 552 else 553 assert_pll_enabled(dev_priv, pipe); 554 } else { 555 if (new_crtc_state->has_pch_encoder) { 556 /* if driving the PCH, we need FDI enabled */ 557 assert_fdi_rx_pll_enabled(dev_priv, 558 intel_crtc_pch_transcoder(crtc)); 559 assert_fdi_tx_pll_enabled(dev_priv, 560 (enum pipe) cpu_transcoder); 561 } 562 /* FIXME: assert CPU port conditions for SNB+ */ 563 } 564 565 /* Wa_22012358565:adl-p */ 566 if (DISPLAY_VER(dev_priv) == 13) 567 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe), 568 0, PIPE_ARB_USE_PROG_SLOTS); 569 570 reg = PIPECONF(cpu_transcoder); 571 val = intel_de_read(dev_priv, reg); 572 if (val & PIPECONF_ENABLE) { 573 /* we keep both pipes enabled on 830 */ 574 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv)); 575 return; 576 } 577 578 intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE); 579 intel_de_posting_read(dev_priv, reg); 580 581 /* 582 * Until the pipe starts PIPEDSL reads will return a stale value, 583 * which causes an apparent vblank timestamp jump when PIPEDSL 584 * resets to its proper value. That also messes up the frame count 585 * when it's derived from the timestamps. So let's wait for the 586 * pipe to start properly before we call drm_crtc_vblank_on() 587 */ 588 if (intel_crtc_max_vblank_count(new_crtc_state) == 0) 589 intel_wait_for_pipe_scanline_moving(crtc); 590 } 591 592 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) 593 { 594 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 595 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 596 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 597 enum pipe pipe = crtc->pipe; 598 i915_reg_t reg; 599 u32 val; 600 601 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe)); 602 603 /* 604 * Make sure planes won't keep trying to pump pixels to us, 605 * or we might hang the display. 606 */ 607 assert_planes_disabled(crtc); 608 609 reg = PIPECONF(cpu_transcoder); 610 val = intel_de_read(dev_priv, reg); 611 if ((val & PIPECONF_ENABLE) == 0) 612 return; 613 614 /* 615 * Double wide has implications for planes 616 * so best keep it disabled when not needed. 617 */ 618 if (old_crtc_state->double_wide) 619 val &= ~PIPECONF_DOUBLE_WIDE; 620 621 /* Don't disable pipe or pipe PLLs if needed */ 622 if (!IS_I830(dev_priv)) 623 val &= ~PIPECONF_ENABLE; 624 625 if (DISPLAY_VER(dev_priv) >= 12) 626 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 627 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 628 629 intel_de_write(dev_priv, reg, val); 630 if ((val & PIPECONF_ENABLE) == 0) 631 intel_wait_for_pipe_off(old_crtc_state); 632 } 633 634 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) 635 { 636 unsigned int size = 0; 637 int i; 638 639 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) 640 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width; 641 642 return size; 643 } 644 645 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info) 646 { 647 unsigned int size = 0; 648 int i; 649 650 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) { 651 unsigned int plane_size; 652 653 if (rem_info->plane[i].linear) 654 plane_size = rem_info->plane[i].size; 655 else 656 plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height; 657 658 if (plane_size == 0) 659 continue; 660 661 if (rem_info->plane_alignment) 662 size = ALIGN(size, rem_info->plane_alignment); 663 664 size += plane_size; 665 } 666 667 return size; 668 } 669 670 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) 671 { 672 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 673 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 674 675 return DISPLAY_VER(dev_priv) < 4 || 676 (plane->fbc && 677 plane_state->view.gtt.type == I915_GGTT_VIEW_NORMAL); 678 } 679 680 /* 681 * Convert the x/y offsets into a linear offset. 682 * Only valid with 0/180 degree rotation, which is fine since linear 683 * offset is only used with linear buffers on pre-hsw and tiled buffers 684 * with gen2/3, and 90/270 degree rotations isn't supported on any of them. 685 */ 686 u32 intel_fb_xy_to_linear(int x, int y, 687 const struct intel_plane_state *state, 688 int color_plane) 689 { 690 const struct drm_framebuffer *fb = state->hw.fb; 691 unsigned int cpp = fb->format->cpp[color_plane]; 692 unsigned int pitch = state->view.color_plane[color_plane].mapping_stride; 693 694 return y * pitch + x * cpp; 695 } 696 697 /* 698 * Add the x/y offsets derived from fb->offsets[] to the user 699 * specified plane src x/y offsets. The resulting x/y offsets 700 * specify the start of scanout from the beginning of the gtt mapping. 701 */ 702 void intel_add_fb_offsets(int *x, int *y, 703 const struct intel_plane_state *state, 704 int color_plane) 705 706 { 707 *x += state->view.color_plane[color_plane].x; 708 *y += state->view.color_plane[color_plane].y; 709 } 710 711 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 712 u32 pixel_format, u64 modifier) 713 { 714 struct intel_crtc *crtc; 715 struct intel_plane *plane; 716 717 if (!HAS_DISPLAY(dev_priv)) 718 return 0; 719 720 /* 721 * We assume the primary plane for pipe A has 722 * the highest stride limits of them all, 723 * if in case pipe A is disabled, use the first pipe from pipe_mask. 724 */ 725 crtc = intel_first_crtc(dev_priv); 726 if (!crtc) 727 return 0; 728 729 plane = to_intel_plane(crtc->base.primary); 730 731 return plane->max_stride(plane, pixel_format, modifier, 732 DRM_MODE_ROTATE_0); 733 } 734 735 static void 736 intel_set_plane_visible(struct intel_crtc_state *crtc_state, 737 struct intel_plane_state *plane_state, 738 bool visible) 739 { 740 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 741 742 plane_state->uapi.visible = visible; 743 744 if (visible) 745 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base); 746 else 747 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base); 748 } 749 750 static void fixup_plane_bitmasks(struct intel_crtc_state *crtc_state) 751 { 752 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 753 struct drm_plane *plane; 754 755 /* 756 * Active_planes aliases if multiple "primary" or cursor planes 757 * have been used on the same (or wrong) pipe. plane_mask uses 758 * unique ids, hence we can use that to reconstruct active_planes. 759 */ 760 crtc_state->enabled_planes = 0; 761 crtc_state->active_planes = 0; 762 763 drm_for_each_plane_mask(plane, &dev_priv->drm, 764 crtc_state->uapi.plane_mask) { 765 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id); 766 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id); 767 } 768 } 769 770 void intel_plane_disable_noatomic(struct intel_crtc *crtc, 771 struct intel_plane *plane) 772 { 773 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 774 struct intel_crtc_state *crtc_state = 775 to_intel_crtc_state(crtc->base.state); 776 struct intel_plane_state *plane_state = 777 to_intel_plane_state(plane->base.state); 778 779 drm_dbg_kms(&dev_priv->drm, 780 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n", 781 plane->base.base.id, plane->base.name, 782 crtc->base.base.id, crtc->base.name); 783 784 intel_set_plane_visible(crtc_state, plane_state, false); 785 fixup_plane_bitmasks(crtc_state); 786 crtc_state->data_rate[plane->id] = 0; 787 crtc_state->data_rate_y[plane->id] = 0; 788 crtc_state->rel_data_rate[plane->id] = 0; 789 crtc_state->rel_data_rate_y[plane->id] = 0; 790 crtc_state->min_cdclk[plane->id] = 0; 791 792 if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 && 793 hsw_ips_disable(crtc_state)) { 794 crtc_state->ips_enabled = false; 795 intel_crtc_wait_for_next_vblank(crtc); 796 } 797 798 /* 799 * Vblank time updates from the shadow to live plane control register 800 * are blocked if the memory self-refresh mode is active at that 801 * moment. So to make sure the plane gets truly disabled, disable 802 * first the self-refresh mode. The self-refresh enable bit in turn 803 * will be checked/applied by the HW only at the next frame start 804 * event which is after the vblank start event, so we need to have a 805 * wait-for-vblank between disabling the plane and the pipe. 806 */ 807 if (HAS_GMCH(dev_priv) && 808 intel_set_memory_cxsr(dev_priv, false)) 809 intel_crtc_wait_for_next_vblank(crtc); 810 811 /* 812 * Gen2 reports pipe underruns whenever all planes are disabled. 813 * So disable underrun reporting before all the planes get disabled. 814 */ 815 if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes) 816 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); 817 818 intel_plane_disable_arm(plane, crtc_state); 819 intel_crtc_wait_for_next_vblank(crtc); 820 } 821 822 unsigned int 823 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state) 824 { 825 int x = 0, y = 0; 826 827 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, 828 plane_state->view.color_plane[0].offset, 0); 829 830 return y; 831 } 832 833 static int 834 __intel_display_resume(struct drm_device *dev, 835 struct drm_atomic_state *state, 836 struct drm_modeset_acquire_ctx *ctx) 837 { 838 struct drm_crtc_state *crtc_state; 839 struct drm_crtc *crtc; 840 int i, ret; 841 842 intel_modeset_setup_hw_state(dev, ctx); 843 intel_vga_redisable(to_i915(dev)); 844 845 if (!state) 846 return 0; 847 848 /* 849 * We've duplicated the state, pointers to the old state are invalid. 850 * 851 * Don't attempt to use the old state until we commit the duplicated state. 852 */ 853 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 854 /* 855 * Force recalculation even if we restore 856 * current state. With fast modeset this may not result 857 * in a modeset when the state is compatible. 858 */ 859 crtc_state->mode_changed = true; 860 } 861 862 /* ignore any reset values/BIOS leftovers in the WM registers */ 863 if (!HAS_GMCH(to_i915(dev))) 864 to_intel_atomic_state(state)->skip_intermediate_wm = true; 865 866 ret = drm_atomic_helper_commit_duplicated_state(state, ctx); 867 868 drm_WARN_ON(dev, ret == -EDEADLK); 869 return ret; 870 } 871 872 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) 873 { 874 return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display && 875 intel_has_gpu_reset(to_gt(dev_priv))); 876 } 877 878 void intel_display_prepare_reset(struct drm_i915_private *dev_priv) 879 { 880 struct drm_device *dev = &dev_priv->drm; 881 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; 882 struct drm_atomic_state *state; 883 int ret; 884 885 if (!HAS_DISPLAY(dev_priv)) 886 return; 887 888 /* reset doesn't touch the display */ 889 if (!dev_priv->params.force_reset_modeset_test && 890 !gpu_reset_clobbers_display(dev_priv)) 891 return; 892 893 /* We have a modeset vs reset deadlock, defensively unbreak it. */ 894 set_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags); 895 smp_mb__after_atomic(); 896 wake_up_bit(&to_gt(dev_priv)->reset.flags, I915_RESET_MODESET); 897 898 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) { 899 drm_dbg_kms(&dev_priv->drm, 900 "Modeset potentially stuck, unbreaking through wedging\n"); 901 intel_gt_set_wedged(to_gt(dev_priv)); 902 } 903 904 /* 905 * Need mode_config.mutex so that we don't 906 * trample ongoing ->detect() and whatnot. 907 */ 908 mutex_lock(&dev->mode_config.mutex); 909 drm_modeset_acquire_init(ctx, 0); 910 while (1) { 911 ret = drm_modeset_lock_all_ctx(dev, ctx); 912 if (ret != -EDEADLK) 913 break; 914 915 drm_modeset_backoff(ctx); 916 } 917 /* 918 * Disabling the crtcs gracefully seems nicer. Also the 919 * g33 docs say we should at least disable all the planes. 920 */ 921 state = drm_atomic_helper_duplicate_state(dev, ctx); 922 if (IS_ERR(state)) { 923 ret = PTR_ERR(state); 924 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n", 925 ret); 926 return; 927 } 928 929 ret = drm_atomic_helper_disable_all(dev, ctx); 930 if (ret) { 931 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", 932 ret); 933 drm_atomic_state_put(state); 934 return; 935 } 936 937 dev_priv->modeset_restore_state = state; 938 state->acquire_ctx = ctx; 939 } 940 941 void intel_display_finish_reset(struct drm_i915_private *dev_priv) 942 { 943 struct drm_device *dev = &dev_priv->drm; 944 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; 945 struct drm_atomic_state *state; 946 int ret; 947 948 if (!HAS_DISPLAY(dev_priv)) 949 return; 950 951 /* reset doesn't touch the display */ 952 if (!test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags)) 953 return; 954 955 state = fetch_and_zero(&dev_priv->modeset_restore_state); 956 if (!state) 957 goto unlock; 958 959 /* reset doesn't touch the display */ 960 if (!gpu_reset_clobbers_display(dev_priv)) { 961 /* for testing only restore the display */ 962 ret = __intel_display_resume(dev, state, ctx); 963 if (ret) 964 drm_err(&dev_priv->drm, 965 "Restoring old state failed with %i\n", ret); 966 } else { 967 /* 968 * The display has been reset as well, 969 * so need a full re-initialization. 970 */ 971 intel_pps_unlock_regs_wa(dev_priv); 972 intel_modeset_init_hw(dev_priv); 973 intel_init_clock_gating(dev_priv); 974 intel_hpd_init(dev_priv); 975 976 ret = __intel_display_resume(dev, state, ctx); 977 if (ret) 978 drm_err(&dev_priv->drm, 979 "Restoring old state failed with %i\n", ret); 980 981 intel_hpd_poll_disable(dev_priv); 982 } 983 984 drm_atomic_state_put(state); 985 unlock: 986 drm_modeset_drop_locks(ctx); 987 drm_modeset_acquire_fini(ctx); 988 mutex_unlock(&dev->mode_config.mutex); 989 990 clear_bit_unlock(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags); 991 } 992 993 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) 994 { 995 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 996 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 997 enum pipe pipe = crtc->pipe; 998 u32 tmp; 999 1000 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe)); 1001 1002 /* 1003 * Display WA #1153: icl 1004 * enable hardware to bypass the alpha math 1005 * and rounding for per-pixel values 00 and 0xff 1006 */ 1007 tmp |= PER_PIXEL_ALPHA_BYPASS_EN; 1008 /* 1009 * Display WA # 1605353570: icl 1010 * Set the pixel rounding bit to 1 for allowing 1011 * passthrough of Frame buffer pixels unmodified 1012 * across pipe 1013 */ 1014 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU; 1015 1016 /* 1017 * Underrun recovery must always be disabled on display 13+. 1018 * DG2 chicken bit meaning is inverted compared to other platforms. 1019 */ 1020 if (IS_DG2(dev_priv)) 1021 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2; 1022 else if (DISPLAY_VER(dev_priv) >= 13) 1023 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP; 1024 1025 /* Wa_14010547955:dg2 */ 1026 if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER)) 1027 tmp |= DG2_RENDER_CCSTAG_4_3_EN; 1028 1029 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp); 1030 } 1031 1032 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) 1033 { 1034 struct drm_crtc *crtc; 1035 bool cleanup_done; 1036 1037 drm_for_each_crtc(crtc, &dev_priv->drm) { 1038 struct drm_crtc_commit *commit; 1039 spin_lock(&crtc->commit_lock); 1040 commit = list_first_entry_or_null(&crtc->commit_list, 1041 struct drm_crtc_commit, commit_entry); 1042 cleanup_done = commit ? 1043 try_wait_for_completion(&commit->cleanup_done) : true; 1044 spin_unlock(&crtc->commit_lock); 1045 1046 if (cleanup_done) 1047 continue; 1048 1049 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc)); 1050 1051 return true; 1052 } 1053 1054 return false; 1055 } 1056 1057 /* 1058 * Finds the encoder associated with the given CRTC. This can only be 1059 * used when we know that the CRTC isn't feeding multiple encoders! 1060 */ 1061 struct intel_encoder * 1062 intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 1063 const struct intel_crtc_state *crtc_state) 1064 { 1065 const struct drm_connector_state *connector_state; 1066 const struct drm_connector *connector; 1067 struct intel_encoder *encoder = NULL; 1068 struct intel_crtc *master_crtc; 1069 int num_encoders = 0; 1070 int i; 1071 1072 master_crtc = intel_master_crtc(crtc_state); 1073 1074 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 1075 if (connector_state->crtc != &master_crtc->base) 1076 continue; 1077 1078 encoder = to_intel_encoder(connector_state->best_encoder); 1079 num_encoders++; 1080 } 1081 1082 drm_WARN(encoder->base.dev, num_encoders != 1, 1083 "%d encoders for pipe %c\n", 1084 num_encoders, pipe_name(master_crtc->pipe)); 1085 1086 return encoder; 1087 } 1088 1089 static void cpt_verify_modeset(struct drm_i915_private *dev_priv, 1090 enum pipe pipe) 1091 { 1092 i915_reg_t dslreg = PIPEDSL(pipe); 1093 u32 temp; 1094 1095 temp = intel_de_read(dev_priv, dslreg); 1096 udelay(500); 1097 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) { 1098 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) 1099 drm_err(&dev_priv->drm, 1100 "mode set failed: pipe %c stuck\n", 1101 pipe_name(pipe)); 1102 } 1103 } 1104 1105 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state) 1106 { 1107 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1108 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1109 const struct drm_rect *dst = &crtc_state->pch_pfit.dst; 1110 enum pipe pipe = crtc->pipe; 1111 int width = drm_rect_width(dst); 1112 int height = drm_rect_height(dst); 1113 int x = dst->x1; 1114 int y = dst->y1; 1115 1116 if (!crtc_state->pch_pfit.enabled) 1117 return; 1118 1119 /* Force use of hard-coded filter coefficients 1120 * as some pre-programmed values are broken, 1121 * e.g. x201. 1122 */ 1123 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) 1124 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 1125 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe)); 1126 else 1127 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 1128 PF_FILTER_MED_3x3); 1129 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), x << 16 | y); 1130 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), width << 16 | height); 1131 } 1132 1133 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc) 1134 { 1135 if (crtc->overlay) 1136 (void) intel_overlay_switch_off(crtc->overlay); 1137 1138 /* Let userspace switch the overlay on again. In most cases userspace 1139 * has to recompute where to put it anyway. 1140 */ 1141 } 1142 1143 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state) 1144 { 1145 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1146 1147 if (!crtc_state->nv12_planes) 1148 return false; 1149 1150 /* WA Display #0827: Gen9:all */ 1151 if (DISPLAY_VER(dev_priv) == 9) 1152 return true; 1153 1154 return false; 1155 } 1156 1157 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state) 1158 { 1159 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1160 1161 /* Wa_2006604312:icl,ehl */ 1162 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11) 1163 return true; 1164 1165 return false; 1166 } 1167 1168 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state) 1169 { 1170 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1171 1172 /* Wa_1604331009:icl,jsl,ehl */ 1173 if (is_hdr_mode(crtc_state) && 1174 crtc_state->active_planes & BIT(PLANE_CURSOR) && 1175 DISPLAY_VER(dev_priv) == 11) 1176 return true; 1177 1178 return false; 1179 } 1180 1181 static void intel_async_flip_vtd_wa(struct drm_i915_private *i915, 1182 enum pipe pipe, bool enable) 1183 { 1184 if (DISPLAY_VER(i915) == 9) { 1185 /* 1186 * "Plane N strech max must be programmed to 11b (x1) 1187 * when Async flips are enabled on that plane." 1188 */ 1189 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 1190 SKL_PLANE1_STRETCH_MAX_MASK, 1191 enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8); 1192 } else { 1193 /* Also needed on HSW/BDW albeit undocumented */ 1194 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 1195 HSW_PRI_STRETCH_MAX_MASK, 1196 enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8); 1197 } 1198 } 1199 1200 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state) 1201 { 1202 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1203 1204 return crtc_state->uapi.async_flip && i915_vtd_active(i915) && 1205 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915)); 1206 } 1207 1208 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state, 1209 const struct intel_crtc_state *new_crtc_state) 1210 { 1211 return (!old_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)) && 1212 new_crtc_state->active_planes; 1213 } 1214 1215 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state, 1216 const struct intel_crtc_state *new_crtc_state) 1217 { 1218 return old_crtc_state->active_planes && 1219 (!new_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)); 1220 } 1221 1222 static void intel_post_plane_update(struct intel_atomic_state *state, 1223 struct intel_crtc *crtc) 1224 { 1225 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1226 const struct intel_crtc_state *old_crtc_state = 1227 intel_atomic_get_old_crtc_state(state, crtc); 1228 const struct intel_crtc_state *new_crtc_state = 1229 intel_atomic_get_new_crtc_state(state, crtc); 1230 enum pipe pipe = crtc->pipe; 1231 1232 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); 1233 1234 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) 1235 intel_update_watermarks(dev_priv); 1236 1237 hsw_ips_post_update(state, crtc); 1238 intel_fbc_post_update(state, crtc); 1239 1240 if (needs_async_flip_vtd_wa(old_crtc_state) && 1241 !needs_async_flip_vtd_wa(new_crtc_state)) 1242 intel_async_flip_vtd_wa(dev_priv, pipe, false); 1243 1244 if (needs_nv12_wa(old_crtc_state) && 1245 !needs_nv12_wa(new_crtc_state)) 1246 skl_wa_827(dev_priv, pipe, false); 1247 1248 if (needs_scalerclk_wa(old_crtc_state) && 1249 !needs_scalerclk_wa(new_crtc_state)) 1250 icl_wa_scalerclkgating(dev_priv, pipe, false); 1251 1252 if (needs_cursorclk_wa(old_crtc_state) && 1253 !needs_cursorclk_wa(new_crtc_state)) 1254 icl_wa_cursorclkgating(dev_priv, pipe, false); 1255 1256 intel_drrs_activate(new_crtc_state); 1257 } 1258 1259 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state, 1260 struct intel_crtc *crtc) 1261 { 1262 const struct intel_crtc_state *crtc_state = 1263 intel_atomic_get_new_crtc_state(state, crtc); 1264 u8 update_planes = crtc_state->update_planes; 1265 const struct intel_plane_state *plane_state; 1266 struct intel_plane *plane; 1267 int i; 1268 1269 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1270 if (plane->pipe == crtc->pipe && 1271 update_planes & BIT(plane->id)) 1272 plane->enable_flip_done(plane); 1273 } 1274 } 1275 1276 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state, 1277 struct intel_crtc *crtc) 1278 { 1279 const struct intel_crtc_state *crtc_state = 1280 intel_atomic_get_new_crtc_state(state, crtc); 1281 u8 update_planes = crtc_state->update_planes; 1282 const struct intel_plane_state *plane_state; 1283 struct intel_plane *plane; 1284 int i; 1285 1286 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1287 if (plane->pipe == crtc->pipe && 1288 update_planes & BIT(plane->id)) 1289 plane->disable_flip_done(plane); 1290 } 1291 } 1292 1293 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state, 1294 struct intel_crtc *crtc) 1295 { 1296 const struct intel_crtc_state *old_crtc_state = 1297 intel_atomic_get_old_crtc_state(state, crtc); 1298 const struct intel_crtc_state *new_crtc_state = 1299 intel_atomic_get_new_crtc_state(state, crtc); 1300 u8 update_planes = new_crtc_state->update_planes; 1301 const struct intel_plane_state *old_plane_state; 1302 struct intel_plane *plane; 1303 bool need_vbl_wait = false; 1304 int i; 1305 1306 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1307 if (plane->need_async_flip_disable_wa && 1308 plane->pipe == crtc->pipe && 1309 update_planes & BIT(plane->id)) { 1310 /* 1311 * Apart from the async flip bit we want to 1312 * preserve the old state for the plane. 1313 */ 1314 plane->async_flip(plane, old_crtc_state, 1315 old_plane_state, false); 1316 need_vbl_wait = true; 1317 } 1318 } 1319 1320 if (need_vbl_wait) 1321 intel_crtc_wait_for_next_vblank(crtc); 1322 } 1323 1324 static void intel_pre_plane_update(struct intel_atomic_state *state, 1325 struct intel_crtc *crtc) 1326 { 1327 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1328 const struct intel_crtc_state *old_crtc_state = 1329 intel_atomic_get_old_crtc_state(state, crtc); 1330 const struct intel_crtc_state *new_crtc_state = 1331 intel_atomic_get_new_crtc_state(state, crtc); 1332 enum pipe pipe = crtc->pipe; 1333 1334 intel_drrs_deactivate(old_crtc_state); 1335 1336 intel_psr_pre_plane_update(state, crtc); 1337 1338 if (hsw_ips_pre_update(state, crtc)) 1339 intel_crtc_wait_for_next_vblank(crtc); 1340 1341 if (intel_fbc_pre_update(state, crtc)) 1342 intel_crtc_wait_for_next_vblank(crtc); 1343 1344 if (!needs_async_flip_vtd_wa(old_crtc_state) && 1345 needs_async_flip_vtd_wa(new_crtc_state)) 1346 intel_async_flip_vtd_wa(dev_priv, pipe, true); 1347 1348 /* Display WA 827 */ 1349 if (!needs_nv12_wa(old_crtc_state) && 1350 needs_nv12_wa(new_crtc_state)) 1351 skl_wa_827(dev_priv, pipe, true); 1352 1353 /* Wa_2006604312:icl,ehl */ 1354 if (!needs_scalerclk_wa(old_crtc_state) && 1355 needs_scalerclk_wa(new_crtc_state)) 1356 icl_wa_scalerclkgating(dev_priv, pipe, true); 1357 1358 /* Wa_1604331009:icl,jsl,ehl */ 1359 if (!needs_cursorclk_wa(old_crtc_state) && 1360 needs_cursorclk_wa(new_crtc_state)) 1361 icl_wa_cursorclkgating(dev_priv, pipe, true); 1362 1363 /* 1364 * Vblank time updates from the shadow to live plane control register 1365 * are blocked if the memory self-refresh mode is active at that 1366 * moment. So to make sure the plane gets truly disabled, disable 1367 * first the self-refresh mode. The self-refresh enable bit in turn 1368 * will be checked/applied by the HW only at the next frame start 1369 * event which is after the vblank start event, so we need to have a 1370 * wait-for-vblank between disabling the plane and the pipe. 1371 */ 1372 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active && 1373 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) 1374 intel_crtc_wait_for_next_vblank(crtc); 1375 1376 /* 1377 * IVB workaround: must disable low power watermarks for at least 1378 * one frame before enabling scaling. LP watermarks can be re-enabled 1379 * when scaling is disabled. 1380 * 1381 * WaCxSRDisabledForSpriteScaling:ivb 1382 */ 1383 if (old_crtc_state->hw.active && 1384 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv)) 1385 intel_crtc_wait_for_next_vblank(crtc); 1386 1387 /* 1388 * If we're doing a modeset we don't need to do any 1389 * pre-vblank watermark programming here. 1390 */ 1391 if (!intel_crtc_needs_modeset(new_crtc_state)) { 1392 /* 1393 * For platforms that support atomic watermarks, program the 1394 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these 1395 * will be the intermediate values that are safe for both pre- and 1396 * post- vblank; when vblank happens, the 'active' values will be set 1397 * to the final 'target' values and we'll do this again to get the 1398 * optimal watermarks. For gen9+ platforms, the values we program here 1399 * will be the final target values which will get automatically latched 1400 * at vblank time; no further programming will be necessary. 1401 * 1402 * If a platform hasn't been transitioned to atomic watermarks yet, 1403 * we'll continue to update watermarks the old way, if flags tell 1404 * us to. 1405 */ 1406 if (!intel_initial_watermarks(state, crtc)) 1407 if (new_crtc_state->update_wm_pre) 1408 intel_update_watermarks(dev_priv); 1409 } 1410 1411 /* 1412 * Gen2 reports pipe underruns whenever all planes are disabled. 1413 * So disable underrun reporting before all the planes get disabled. 1414 * 1415 * We do this after .initial_watermarks() so that we have a 1416 * chance of catching underruns with the intermediate watermarks 1417 * vs. the old plane configuration. 1418 */ 1419 if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state)) 1420 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1421 1422 /* 1423 * WA for platforms where async address update enable bit 1424 * is double buffered and only latched at start of vblank. 1425 */ 1426 if (old_crtc_state->uapi.async_flip && !new_crtc_state->uapi.async_flip) 1427 intel_crtc_async_flip_disable_wa(state, crtc); 1428 } 1429 1430 static void intel_crtc_disable_planes(struct intel_atomic_state *state, 1431 struct intel_crtc *crtc) 1432 { 1433 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1434 const struct intel_crtc_state *new_crtc_state = 1435 intel_atomic_get_new_crtc_state(state, crtc); 1436 unsigned int update_mask = new_crtc_state->update_planes; 1437 const struct intel_plane_state *old_plane_state; 1438 struct intel_plane *plane; 1439 unsigned fb_bits = 0; 1440 int i; 1441 1442 intel_crtc_dpms_overlay_disable(crtc); 1443 1444 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1445 if (crtc->pipe != plane->pipe || 1446 !(update_mask & BIT(plane->id))) 1447 continue; 1448 1449 intel_plane_disable_arm(plane, new_crtc_state); 1450 1451 if (old_plane_state->uapi.visible) 1452 fb_bits |= plane->frontbuffer_bit; 1453 } 1454 1455 intel_frontbuffer_flip(dev_priv, fb_bits); 1456 } 1457 1458 /* 1459 * intel_connector_primary_encoder - get the primary encoder for a connector 1460 * @connector: connector for which to return the encoder 1461 * 1462 * Returns the primary encoder for a connector. There is a 1:1 mapping from 1463 * all connectors to their encoder, except for DP-MST connectors which have 1464 * both a virtual and a primary encoder. These DP-MST primary encoders can be 1465 * pointed to by as many DP-MST connectors as there are pipes. 1466 */ 1467 static struct intel_encoder * 1468 intel_connector_primary_encoder(struct intel_connector *connector) 1469 { 1470 struct intel_encoder *encoder; 1471 1472 if (connector->mst_port) 1473 return &dp_to_dig_port(connector->mst_port)->base; 1474 1475 encoder = intel_attached_encoder(connector); 1476 drm_WARN_ON(connector->base.dev, !encoder); 1477 1478 return encoder; 1479 } 1480 1481 static void intel_encoders_update_prepare(struct intel_atomic_state *state) 1482 { 1483 struct drm_i915_private *i915 = to_i915(state->base.dev); 1484 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 1485 struct intel_crtc *crtc; 1486 struct drm_connector_state *new_conn_state; 1487 struct drm_connector *connector; 1488 int i; 1489 1490 /* 1491 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits. 1492 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook. 1493 */ 1494 if (i915->dpll.mgr) { 1495 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1496 if (intel_crtc_needs_modeset(new_crtc_state)) 1497 continue; 1498 1499 new_crtc_state->shared_dpll = old_crtc_state->shared_dpll; 1500 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state; 1501 } 1502 } 1503 1504 if (!state->modeset) 1505 return; 1506 1507 for_each_new_connector_in_state(&state->base, connector, new_conn_state, 1508 i) { 1509 struct intel_connector *intel_connector; 1510 struct intel_encoder *encoder; 1511 struct intel_crtc *crtc; 1512 1513 if (!intel_connector_needs_modeset(state, connector)) 1514 continue; 1515 1516 intel_connector = to_intel_connector(connector); 1517 encoder = intel_connector_primary_encoder(intel_connector); 1518 if (!encoder->update_prepare) 1519 continue; 1520 1521 crtc = new_conn_state->crtc ? 1522 to_intel_crtc(new_conn_state->crtc) : NULL; 1523 encoder->update_prepare(state, encoder, crtc); 1524 } 1525 } 1526 1527 static void intel_encoders_update_complete(struct intel_atomic_state *state) 1528 { 1529 struct drm_connector_state *new_conn_state; 1530 struct drm_connector *connector; 1531 int i; 1532 1533 if (!state->modeset) 1534 return; 1535 1536 for_each_new_connector_in_state(&state->base, connector, new_conn_state, 1537 i) { 1538 struct intel_connector *intel_connector; 1539 struct intel_encoder *encoder; 1540 struct intel_crtc *crtc; 1541 1542 if (!intel_connector_needs_modeset(state, connector)) 1543 continue; 1544 1545 intel_connector = to_intel_connector(connector); 1546 encoder = intel_connector_primary_encoder(intel_connector); 1547 if (!encoder->update_complete) 1548 continue; 1549 1550 crtc = new_conn_state->crtc ? 1551 to_intel_crtc(new_conn_state->crtc) : NULL; 1552 encoder->update_complete(state, encoder, crtc); 1553 } 1554 } 1555 1556 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state, 1557 struct intel_crtc *crtc) 1558 { 1559 const struct intel_crtc_state *crtc_state = 1560 intel_atomic_get_new_crtc_state(state, crtc); 1561 const struct drm_connector_state *conn_state; 1562 struct drm_connector *conn; 1563 int i; 1564 1565 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1566 struct intel_encoder *encoder = 1567 to_intel_encoder(conn_state->best_encoder); 1568 1569 if (conn_state->crtc != &crtc->base) 1570 continue; 1571 1572 if (encoder->pre_pll_enable) 1573 encoder->pre_pll_enable(state, encoder, 1574 crtc_state, conn_state); 1575 } 1576 } 1577 1578 static void intel_encoders_pre_enable(struct intel_atomic_state *state, 1579 struct intel_crtc *crtc) 1580 { 1581 const struct intel_crtc_state *crtc_state = 1582 intel_atomic_get_new_crtc_state(state, crtc); 1583 const struct drm_connector_state *conn_state; 1584 struct drm_connector *conn; 1585 int i; 1586 1587 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1588 struct intel_encoder *encoder = 1589 to_intel_encoder(conn_state->best_encoder); 1590 1591 if (conn_state->crtc != &crtc->base) 1592 continue; 1593 1594 if (encoder->pre_enable) 1595 encoder->pre_enable(state, encoder, 1596 crtc_state, conn_state); 1597 } 1598 } 1599 1600 static void intel_encoders_enable(struct intel_atomic_state *state, 1601 struct intel_crtc *crtc) 1602 { 1603 const struct intel_crtc_state *crtc_state = 1604 intel_atomic_get_new_crtc_state(state, crtc); 1605 const struct drm_connector_state *conn_state; 1606 struct drm_connector *conn; 1607 int i; 1608 1609 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1610 struct intel_encoder *encoder = 1611 to_intel_encoder(conn_state->best_encoder); 1612 1613 if (conn_state->crtc != &crtc->base) 1614 continue; 1615 1616 if (encoder->enable) 1617 encoder->enable(state, encoder, 1618 crtc_state, conn_state); 1619 intel_opregion_notify_encoder(encoder, true); 1620 } 1621 } 1622 1623 static void intel_encoders_disable(struct intel_atomic_state *state, 1624 struct intel_crtc *crtc) 1625 { 1626 const struct intel_crtc_state *old_crtc_state = 1627 intel_atomic_get_old_crtc_state(state, crtc); 1628 const struct drm_connector_state *old_conn_state; 1629 struct drm_connector *conn; 1630 int i; 1631 1632 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1633 struct intel_encoder *encoder = 1634 to_intel_encoder(old_conn_state->best_encoder); 1635 1636 if (old_conn_state->crtc != &crtc->base) 1637 continue; 1638 1639 intel_opregion_notify_encoder(encoder, false); 1640 if (encoder->disable) 1641 encoder->disable(state, encoder, 1642 old_crtc_state, old_conn_state); 1643 } 1644 } 1645 1646 static void intel_encoders_post_disable(struct intel_atomic_state *state, 1647 struct intel_crtc *crtc) 1648 { 1649 const struct intel_crtc_state *old_crtc_state = 1650 intel_atomic_get_old_crtc_state(state, crtc); 1651 const struct drm_connector_state *old_conn_state; 1652 struct drm_connector *conn; 1653 int i; 1654 1655 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1656 struct intel_encoder *encoder = 1657 to_intel_encoder(old_conn_state->best_encoder); 1658 1659 if (old_conn_state->crtc != &crtc->base) 1660 continue; 1661 1662 if (encoder->post_disable) 1663 encoder->post_disable(state, encoder, 1664 old_crtc_state, old_conn_state); 1665 } 1666 } 1667 1668 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state, 1669 struct intel_crtc *crtc) 1670 { 1671 const struct intel_crtc_state *old_crtc_state = 1672 intel_atomic_get_old_crtc_state(state, crtc); 1673 const struct drm_connector_state *old_conn_state; 1674 struct drm_connector *conn; 1675 int i; 1676 1677 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1678 struct intel_encoder *encoder = 1679 to_intel_encoder(old_conn_state->best_encoder); 1680 1681 if (old_conn_state->crtc != &crtc->base) 1682 continue; 1683 1684 if (encoder->post_pll_disable) 1685 encoder->post_pll_disable(state, encoder, 1686 old_crtc_state, old_conn_state); 1687 } 1688 } 1689 1690 static void intel_encoders_update_pipe(struct intel_atomic_state *state, 1691 struct intel_crtc *crtc) 1692 { 1693 const struct intel_crtc_state *crtc_state = 1694 intel_atomic_get_new_crtc_state(state, crtc); 1695 const struct drm_connector_state *conn_state; 1696 struct drm_connector *conn; 1697 int i; 1698 1699 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1700 struct intel_encoder *encoder = 1701 to_intel_encoder(conn_state->best_encoder); 1702 1703 if (conn_state->crtc != &crtc->base) 1704 continue; 1705 1706 if (encoder->update_pipe) 1707 encoder->update_pipe(state, encoder, 1708 crtc_state, conn_state); 1709 } 1710 } 1711 1712 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state) 1713 { 1714 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1715 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 1716 1717 plane->disable_arm(plane, crtc_state); 1718 } 1719 1720 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1721 { 1722 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1723 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1724 1725 if (crtc_state->has_pch_encoder) { 1726 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1727 &crtc_state->fdi_m_n); 1728 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1729 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1730 &crtc_state->dp_m_n); 1731 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1732 &crtc_state->dp_m2_n2); 1733 } 1734 1735 intel_set_transcoder_timings(crtc_state); 1736 1737 ilk_set_pipeconf(crtc_state); 1738 } 1739 1740 static void ilk_crtc_enable(struct intel_atomic_state *state, 1741 struct intel_crtc *crtc) 1742 { 1743 const struct intel_crtc_state *new_crtc_state = 1744 intel_atomic_get_new_crtc_state(state, crtc); 1745 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1746 enum pipe pipe = crtc->pipe; 1747 1748 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1749 return; 1750 1751 /* 1752 * Sometimes spurious CPU pipe underruns happen during FDI 1753 * training, at least with VGA+HDMI cloning. Suppress them. 1754 * 1755 * On ILK we get an occasional spurious CPU pipe underruns 1756 * between eDP port A enable and vdd enable. Also PCH port 1757 * enable seems to result in the occasional CPU pipe underrun. 1758 * 1759 * Spurious PCH underruns also occur during PCH enabling. 1760 */ 1761 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1762 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 1763 1764 ilk_configure_cpu_transcoder(new_crtc_state); 1765 1766 intel_set_pipe_src_size(new_crtc_state); 1767 1768 crtc->active = true; 1769 1770 intel_encoders_pre_enable(state, crtc); 1771 1772 if (new_crtc_state->has_pch_encoder) { 1773 ilk_pch_pre_enable(state, crtc); 1774 } else { 1775 assert_fdi_tx_disabled(dev_priv, pipe); 1776 assert_fdi_rx_disabled(dev_priv, pipe); 1777 } 1778 1779 ilk_pfit_enable(new_crtc_state); 1780 1781 /* 1782 * On ILK+ LUT must be loaded before the pipe is running but with 1783 * clocks enabled 1784 */ 1785 intel_color_load_luts(new_crtc_state); 1786 intel_color_commit_noarm(new_crtc_state); 1787 intel_color_commit_arm(new_crtc_state); 1788 /* update DSPCNTR to configure gamma for pipe bottom color */ 1789 intel_disable_primary_plane(new_crtc_state); 1790 1791 intel_initial_watermarks(state, crtc); 1792 intel_enable_transcoder(new_crtc_state); 1793 1794 if (new_crtc_state->has_pch_encoder) 1795 ilk_pch_enable(state, crtc); 1796 1797 intel_crtc_vblank_on(new_crtc_state); 1798 1799 intel_encoders_enable(state, crtc); 1800 1801 if (HAS_PCH_CPT(dev_priv)) 1802 cpt_verify_modeset(dev_priv, pipe); 1803 1804 /* 1805 * Must wait for vblank to avoid spurious PCH FIFO underruns. 1806 * And a second vblank wait is needed at least on ILK with 1807 * some interlaced HDMI modes. Let's do the double wait always 1808 * in case there are more corner cases we don't know about. 1809 */ 1810 if (new_crtc_state->has_pch_encoder) { 1811 intel_crtc_wait_for_next_vblank(crtc); 1812 intel_crtc_wait_for_next_vblank(crtc); 1813 } 1814 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1815 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 1816 } 1817 1818 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, 1819 enum pipe pipe, bool apply) 1820 { 1821 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)); 1822 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS; 1823 1824 if (apply) 1825 val |= mask; 1826 else 1827 val &= ~mask; 1828 1829 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val); 1830 } 1831 1832 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state) 1833 { 1834 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1835 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1836 1837 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe), 1838 HSW_LINETIME(crtc_state->linetime) | 1839 HSW_IPS_LINETIME(crtc_state->ips_linetime)); 1840 } 1841 1842 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) 1843 { 1844 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1845 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1846 i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder); 1847 u32 val; 1848 1849 val = intel_de_read(dev_priv, reg); 1850 val &= ~HSW_FRAME_START_DELAY_MASK; 1851 val |= HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 1852 intel_de_write(dev_priv, reg, val); 1853 } 1854 1855 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state, 1856 const struct intel_crtc_state *crtc_state) 1857 { 1858 struct intel_crtc *master_crtc = intel_master_crtc(crtc_state); 1859 1860 /* 1861 * Enable sequence steps 1-7 on bigjoiner master 1862 */ 1863 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1864 intel_encoders_pre_pll_enable(state, master_crtc); 1865 1866 if (crtc_state->shared_dpll) 1867 intel_enable_shared_dpll(crtc_state); 1868 1869 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1870 intel_encoders_pre_enable(state, master_crtc); 1871 } 1872 1873 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1874 { 1875 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1876 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1877 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1878 1879 if (crtc_state->has_pch_encoder) { 1880 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1881 &crtc_state->fdi_m_n); 1882 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1883 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1884 &crtc_state->dp_m_n); 1885 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1886 &crtc_state->dp_m2_n2); 1887 } 1888 1889 intel_set_transcoder_timings(crtc_state); 1890 1891 if (cpu_transcoder != TRANSCODER_EDP) 1892 intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder), 1893 crtc_state->pixel_multiplier - 1); 1894 1895 hsw_set_frame_start_delay(crtc_state); 1896 1897 hsw_set_transconf(crtc_state); 1898 } 1899 1900 static void hsw_crtc_enable(struct intel_atomic_state *state, 1901 struct intel_crtc *crtc) 1902 { 1903 const struct intel_crtc_state *new_crtc_state = 1904 intel_atomic_get_new_crtc_state(state, crtc); 1905 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1906 enum pipe pipe = crtc->pipe, hsw_workaround_pipe; 1907 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 1908 bool psl_clkgate_wa; 1909 1910 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1911 return; 1912 1913 if (!new_crtc_state->bigjoiner_pipes) { 1914 intel_encoders_pre_pll_enable(state, crtc); 1915 1916 if (new_crtc_state->shared_dpll) 1917 intel_enable_shared_dpll(new_crtc_state); 1918 1919 intel_encoders_pre_enable(state, crtc); 1920 } else { 1921 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state); 1922 } 1923 1924 intel_dsc_enable(new_crtc_state); 1925 1926 if (DISPLAY_VER(dev_priv) >= 13) 1927 intel_uncompressed_joiner_enable(new_crtc_state); 1928 1929 intel_set_pipe_src_size(new_crtc_state); 1930 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 1931 bdw_set_pipemisc(new_crtc_state); 1932 1933 if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) && 1934 !transcoder_is_dsi(cpu_transcoder)) 1935 hsw_configure_cpu_transcoder(new_crtc_state); 1936 1937 crtc->active = true; 1938 1939 /* Display WA #1180: WaDisableScalarClockGating: glk */ 1940 psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 && 1941 new_crtc_state->pch_pfit.enabled; 1942 if (psl_clkgate_wa) 1943 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true); 1944 1945 if (DISPLAY_VER(dev_priv) >= 9) 1946 skl_pfit_enable(new_crtc_state); 1947 else 1948 ilk_pfit_enable(new_crtc_state); 1949 1950 /* 1951 * On ILK+ LUT must be loaded before the pipe is running but with 1952 * clocks enabled 1953 */ 1954 intel_color_load_luts(new_crtc_state); 1955 intel_color_commit_noarm(new_crtc_state); 1956 intel_color_commit_arm(new_crtc_state); 1957 /* update DSPCNTR to configure gamma/csc for pipe bottom color */ 1958 if (DISPLAY_VER(dev_priv) < 9) 1959 intel_disable_primary_plane(new_crtc_state); 1960 1961 hsw_set_linetime_wm(new_crtc_state); 1962 1963 if (DISPLAY_VER(dev_priv) >= 11) 1964 icl_set_pipe_chicken(new_crtc_state); 1965 1966 intel_initial_watermarks(state, crtc); 1967 1968 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 1969 intel_crtc_vblank_on(new_crtc_state); 1970 1971 intel_encoders_enable(state, crtc); 1972 1973 if (psl_clkgate_wa) { 1974 intel_crtc_wait_for_next_vblank(crtc); 1975 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false); 1976 } 1977 1978 /* If we change the relative order between pipe/planes enabling, we need 1979 * to change the workaround. */ 1980 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe; 1981 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { 1982 struct intel_crtc *wa_crtc; 1983 1984 wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe); 1985 1986 intel_crtc_wait_for_next_vblank(wa_crtc); 1987 intel_crtc_wait_for_next_vblank(wa_crtc); 1988 } 1989 } 1990 1991 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state) 1992 { 1993 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1994 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1995 enum pipe pipe = crtc->pipe; 1996 1997 /* To avoid upsetting the power well on haswell only disable the pfit if 1998 * it's in use. The hw state code will make sure we get this right. */ 1999 if (!old_crtc_state->pch_pfit.enabled) 2000 return; 2001 2002 intel_de_write_fw(dev_priv, PF_CTL(pipe), 0); 2003 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0); 2004 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0); 2005 } 2006 2007 static void ilk_crtc_disable(struct intel_atomic_state *state, 2008 struct intel_crtc *crtc) 2009 { 2010 const struct intel_crtc_state *old_crtc_state = 2011 intel_atomic_get_old_crtc_state(state, crtc); 2012 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2013 enum pipe pipe = crtc->pipe; 2014 2015 /* 2016 * Sometimes spurious CPU pipe underruns happen when the 2017 * pipe is already disabled, but FDI RX/TX is still enabled. 2018 * Happens at least with VGA+HDMI cloning. Suppress them. 2019 */ 2020 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 2021 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 2022 2023 intel_encoders_disable(state, crtc); 2024 2025 intel_crtc_vblank_off(old_crtc_state); 2026 2027 intel_disable_transcoder(old_crtc_state); 2028 2029 ilk_pfit_disable(old_crtc_state); 2030 2031 if (old_crtc_state->has_pch_encoder) 2032 ilk_pch_disable(state, crtc); 2033 2034 intel_encoders_post_disable(state, crtc); 2035 2036 if (old_crtc_state->has_pch_encoder) 2037 ilk_pch_post_disable(state, crtc); 2038 2039 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2040 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 2041 } 2042 2043 static void hsw_crtc_disable(struct intel_atomic_state *state, 2044 struct intel_crtc *crtc) 2045 { 2046 const struct intel_crtc_state *old_crtc_state = 2047 intel_atomic_get_old_crtc_state(state, crtc); 2048 2049 /* 2050 * FIXME collapse everything to one hook. 2051 * Need care with mst->ddi interactions. 2052 */ 2053 if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) { 2054 intel_encoders_disable(state, crtc); 2055 intel_encoders_post_disable(state, crtc); 2056 } 2057 } 2058 2059 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) 2060 { 2061 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2062 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2063 2064 if (!crtc_state->gmch_pfit.control) 2065 return; 2066 2067 /* 2068 * The panel fitter should only be adjusted whilst the pipe is disabled, 2069 * according to register description and PRM. 2070 */ 2071 drm_WARN_ON(&dev_priv->drm, 2072 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE); 2073 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 2074 2075 intel_de_write(dev_priv, PFIT_PGM_RATIOS, 2076 crtc_state->gmch_pfit.pgm_ratios); 2077 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control); 2078 2079 /* Border color in case we don't scale up to the full screen. Black by 2080 * default, change to something else for debugging. */ 2081 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); 2082 } 2083 2084 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) 2085 { 2086 if (phy == PHY_NONE) 2087 return false; 2088 else if (IS_DG2(dev_priv)) 2089 /* 2090 * DG2 outputs labelled as "combo PHY" in the bspec use 2091 * SNPS PHYs with completely different programming, 2092 * hence we always return false here. 2093 */ 2094 return false; 2095 else if (IS_ALDERLAKE_S(dev_priv)) 2096 return phy <= PHY_E; 2097 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) 2098 return phy <= PHY_D; 2099 else if (IS_JSL_EHL(dev_priv)) 2100 return phy <= PHY_C; 2101 else if (DISPLAY_VER(dev_priv) >= 11) 2102 return phy <= PHY_B; 2103 else 2104 return false; 2105 } 2106 2107 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) 2108 { 2109 if (IS_DG2(dev_priv)) 2110 /* DG2's "TC1" output uses a SNPS PHY */ 2111 return false; 2112 else if (IS_ALDERLAKE_P(dev_priv)) 2113 return phy >= PHY_F && phy <= PHY_I; 2114 else if (IS_TIGERLAKE(dev_priv)) 2115 return phy >= PHY_D && phy <= PHY_I; 2116 else if (IS_ICELAKE(dev_priv)) 2117 return phy >= PHY_C && phy <= PHY_F; 2118 else 2119 return false; 2120 } 2121 2122 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy) 2123 { 2124 if (phy == PHY_NONE) 2125 return false; 2126 else if (IS_DG2(dev_priv)) 2127 /* 2128 * All four "combo" ports and the TC1 port (PHY E) use 2129 * Synopsis PHYs. 2130 */ 2131 return phy <= PHY_E; 2132 2133 return false; 2134 } 2135 2136 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) 2137 { 2138 if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD) 2139 return PHY_D + port - PORT_D_XELPD; 2140 else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1) 2141 return PHY_F + port - PORT_TC1; 2142 else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1) 2143 return PHY_B + port - PORT_TC1; 2144 else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1) 2145 return PHY_C + port - PORT_TC1; 2146 else if (IS_JSL_EHL(i915) && port == PORT_D) 2147 return PHY_A; 2148 2149 return PHY_A + port - PORT_A; 2150 } 2151 2152 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) 2153 { 2154 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port))) 2155 return TC_PORT_NONE; 2156 2157 if (DISPLAY_VER(dev_priv) >= 12) 2158 return TC_PORT_1 + port - PORT_TC1; 2159 else 2160 return TC_PORT_1 + port - PORT_C; 2161 } 2162 2163 enum intel_display_power_domain 2164 intel_aux_power_domain(struct intel_digital_port *dig_port) 2165 { 2166 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 2167 2168 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 2169 return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch); 2170 2171 return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch); 2172 } 2173 2174 static void get_crtc_power_domains(struct intel_crtc_state *crtc_state, 2175 struct intel_power_domain_mask *mask) 2176 { 2177 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2178 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2179 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2180 struct drm_encoder *encoder; 2181 enum pipe pipe = crtc->pipe; 2182 2183 bitmap_zero(mask->bits, POWER_DOMAIN_NUM); 2184 2185 if (!crtc_state->hw.active) 2186 return; 2187 2188 set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits); 2189 set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits); 2190 if (crtc_state->pch_pfit.enabled || 2191 crtc_state->pch_pfit.force_thru) 2192 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits); 2193 2194 drm_for_each_encoder_mask(encoder, &dev_priv->drm, 2195 crtc_state->uapi.encoder_mask) { 2196 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2197 2198 set_bit(intel_encoder->power_domain, mask->bits); 2199 } 2200 2201 if (HAS_DDI(dev_priv) && crtc_state->has_audio) 2202 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits); 2203 2204 if (crtc_state->shared_dpll) 2205 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits); 2206 2207 if (crtc_state->dsc.compression_enable) 2208 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits); 2209 } 2210 2211 static void 2212 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, 2213 struct intel_power_domain_mask *old_domains) 2214 { 2215 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2216 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2217 enum intel_display_power_domain domain; 2218 struct intel_power_domain_mask domains, new_domains; 2219 2220 get_crtc_power_domains(crtc_state, &domains); 2221 2222 bitmap_andnot(new_domains.bits, 2223 domains.bits, 2224 crtc->enabled_power_domains.mask.bits, 2225 POWER_DOMAIN_NUM); 2226 bitmap_andnot(old_domains->bits, 2227 crtc->enabled_power_domains.mask.bits, 2228 domains.bits, 2229 POWER_DOMAIN_NUM); 2230 2231 for_each_power_domain(domain, &new_domains) 2232 intel_display_power_get_in_set(dev_priv, 2233 &crtc->enabled_power_domains, 2234 domain); 2235 } 2236 2237 static void modeset_put_crtc_power_domains(struct intel_crtc *crtc, 2238 struct intel_power_domain_mask *domains) 2239 { 2240 intel_display_power_put_mask_in_set(to_i915(crtc->base.dev), 2241 &crtc->enabled_power_domains, 2242 domains); 2243 } 2244 2245 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 2246 { 2247 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2248 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2249 2250 if (intel_crtc_has_dp_encoder(crtc_state)) { 2251 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 2252 &crtc_state->dp_m_n); 2253 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 2254 &crtc_state->dp_m2_n2); 2255 } 2256 2257 intel_set_transcoder_timings(crtc_state); 2258 2259 i9xx_set_pipeconf(crtc_state); 2260 } 2261 2262 static void valleyview_crtc_enable(struct intel_atomic_state *state, 2263 struct intel_crtc *crtc) 2264 { 2265 const struct intel_crtc_state *new_crtc_state = 2266 intel_atomic_get_new_crtc_state(state, crtc); 2267 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2268 enum pipe pipe = crtc->pipe; 2269 2270 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 2271 return; 2272 2273 i9xx_configure_cpu_transcoder(new_crtc_state); 2274 2275 intel_set_pipe_src_size(new_crtc_state); 2276 2277 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 2278 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY); 2279 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0); 2280 } 2281 2282 crtc->active = true; 2283 2284 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2285 2286 intel_encoders_pre_pll_enable(state, crtc); 2287 2288 if (IS_CHERRYVIEW(dev_priv)) 2289 chv_enable_pll(new_crtc_state); 2290 else 2291 vlv_enable_pll(new_crtc_state); 2292 2293 intel_encoders_pre_enable(state, crtc); 2294 2295 i9xx_pfit_enable(new_crtc_state); 2296 2297 intel_color_load_luts(new_crtc_state); 2298 intel_color_commit_noarm(new_crtc_state); 2299 intel_color_commit_arm(new_crtc_state); 2300 /* update DSPCNTR to configure gamma for pipe bottom color */ 2301 intel_disable_primary_plane(new_crtc_state); 2302 2303 intel_initial_watermarks(state, crtc); 2304 intel_enable_transcoder(new_crtc_state); 2305 2306 intel_crtc_vblank_on(new_crtc_state); 2307 2308 intel_encoders_enable(state, crtc); 2309 } 2310 2311 static void i9xx_crtc_enable(struct intel_atomic_state *state, 2312 struct intel_crtc *crtc) 2313 { 2314 const struct intel_crtc_state *new_crtc_state = 2315 intel_atomic_get_new_crtc_state(state, crtc); 2316 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2317 enum pipe pipe = crtc->pipe; 2318 2319 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 2320 return; 2321 2322 i9xx_configure_cpu_transcoder(new_crtc_state); 2323 2324 intel_set_pipe_src_size(new_crtc_state); 2325 2326 crtc->active = true; 2327 2328 if (DISPLAY_VER(dev_priv) != 2) 2329 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2330 2331 intel_encoders_pre_enable(state, crtc); 2332 2333 i9xx_enable_pll(new_crtc_state); 2334 2335 i9xx_pfit_enable(new_crtc_state); 2336 2337 intel_color_load_luts(new_crtc_state); 2338 intel_color_commit_noarm(new_crtc_state); 2339 intel_color_commit_arm(new_crtc_state); 2340 /* update DSPCNTR to configure gamma for pipe bottom color */ 2341 intel_disable_primary_plane(new_crtc_state); 2342 2343 if (!intel_initial_watermarks(state, crtc)) 2344 intel_update_watermarks(dev_priv); 2345 intel_enable_transcoder(new_crtc_state); 2346 2347 intel_crtc_vblank_on(new_crtc_state); 2348 2349 intel_encoders_enable(state, crtc); 2350 2351 /* prevents spurious underruns */ 2352 if (DISPLAY_VER(dev_priv) == 2) 2353 intel_crtc_wait_for_next_vblank(crtc); 2354 } 2355 2356 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) 2357 { 2358 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 2359 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2360 2361 if (!old_crtc_state->gmch_pfit.control) 2362 return; 2363 2364 assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder); 2365 2366 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n", 2367 intel_de_read(dev_priv, PFIT_CONTROL)); 2368 intel_de_write(dev_priv, PFIT_CONTROL, 0); 2369 } 2370 2371 static void i9xx_crtc_disable(struct intel_atomic_state *state, 2372 struct intel_crtc *crtc) 2373 { 2374 struct intel_crtc_state *old_crtc_state = 2375 intel_atomic_get_old_crtc_state(state, crtc); 2376 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2377 enum pipe pipe = crtc->pipe; 2378 2379 /* 2380 * On gen2 planes are double buffered but the pipe isn't, so we must 2381 * wait for planes to fully turn off before disabling the pipe. 2382 */ 2383 if (DISPLAY_VER(dev_priv) == 2) 2384 intel_crtc_wait_for_next_vblank(crtc); 2385 2386 intel_encoders_disable(state, crtc); 2387 2388 intel_crtc_vblank_off(old_crtc_state); 2389 2390 intel_disable_transcoder(old_crtc_state); 2391 2392 i9xx_pfit_disable(old_crtc_state); 2393 2394 intel_encoders_post_disable(state, crtc); 2395 2396 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) { 2397 if (IS_CHERRYVIEW(dev_priv)) 2398 chv_disable_pll(dev_priv, pipe); 2399 else if (IS_VALLEYVIEW(dev_priv)) 2400 vlv_disable_pll(dev_priv, pipe); 2401 else 2402 i9xx_disable_pll(old_crtc_state); 2403 } 2404 2405 intel_encoders_post_pll_disable(state, crtc); 2406 2407 if (DISPLAY_VER(dev_priv) != 2) 2408 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 2409 2410 if (!dev_priv->wm_disp->initial_watermarks) 2411 intel_update_watermarks(dev_priv); 2412 2413 /* clock the pipe down to 640x480@60 to potentially save power */ 2414 if (IS_I830(dev_priv)) 2415 i830_enable_pipe(dev_priv, pipe); 2416 } 2417 2418 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, 2419 struct drm_modeset_acquire_ctx *ctx) 2420 { 2421 struct intel_encoder *encoder; 2422 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2423 struct intel_bw_state *bw_state = 2424 to_intel_bw_state(dev_priv->bw_obj.state); 2425 struct intel_cdclk_state *cdclk_state = 2426 to_intel_cdclk_state(dev_priv->cdclk.obj.state); 2427 struct intel_dbuf_state *dbuf_state = 2428 to_intel_dbuf_state(dev_priv->dbuf.obj.state); 2429 struct intel_crtc_state *crtc_state = 2430 to_intel_crtc_state(crtc->base.state); 2431 struct intel_plane *plane; 2432 struct drm_atomic_state *state; 2433 struct intel_crtc_state *temp_crtc_state; 2434 enum pipe pipe = crtc->pipe; 2435 int ret; 2436 2437 if (!crtc_state->hw.active) 2438 return; 2439 2440 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 2441 const struct intel_plane_state *plane_state = 2442 to_intel_plane_state(plane->base.state); 2443 2444 if (plane_state->uapi.visible) 2445 intel_plane_disable_noatomic(crtc, plane); 2446 } 2447 2448 state = drm_atomic_state_alloc(&dev_priv->drm); 2449 if (!state) { 2450 drm_dbg_kms(&dev_priv->drm, 2451 "failed to disable [CRTC:%d:%s], out of memory", 2452 crtc->base.base.id, crtc->base.name); 2453 return; 2454 } 2455 2456 state->acquire_ctx = ctx; 2457 2458 /* Everything's already locked, -EDEADLK can't happen. */ 2459 temp_crtc_state = intel_atomic_get_crtc_state(state, crtc); 2460 ret = drm_atomic_add_affected_connectors(state, &crtc->base); 2461 2462 drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret); 2463 2464 dev_priv->display->crtc_disable(to_intel_atomic_state(state), crtc); 2465 2466 drm_atomic_state_put(state); 2467 2468 drm_dbg_kms(&dev_priv->drm, 2469 "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", 2470 crtc->base.base.id, crtc->base.name); 2471 2472 crtc->active = false; 2473 crtc->base.enabled = false; 2474 2475 drm_WARN_ON(&dev_priv->drm, 2476 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0); 2477 crtc_state->uapi.active = false; 2478 crtc_state->uapi.connector_mask = 0; 2479 crtc_state->uapi.encoder_mask = 0; 2480 intel_crtc_free_hw_state(crtc_state); 2481 memset(&crtc_state->hw, 0, sizeof(crtc_state->hw)); 2482 2483 for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder) 2484 encoder->base.crtc = NULL; 2485 2486 intel_fbc_disable(crtc); 2487 intel_update_watermarks(dev_priv); 2488 intel_disable_shared_dpll(crtc_state); 2489 2490 intel_display_power_put_all_in_set(dev_priv, &crtc->enabled_power_domains); 2491 2492 cdclk_state->min_cdclk[pipe] = 0; 2493 cdclk_state->min_voltage_level[pipe] = 0; 2494 cdclk_state->active_pipes &= ~BIT(pipe); 2495 2496 dbuf_state->active_pipes &= ~BIT(pipe); 2497 2498 bw_state->data_rate[pipe] = 0; 2499 bw_state->num_active_planes[pipe] = 0; 2500 } 2501 2502 /* 2503 * turn all crtc's off, but do not adjust state 2504 * This has to be paired with a call to intel_modeset_setup_hw_state. 2505 */ 2506 int intel_display_suspend(struct drm_device *dev) 2507 { 2508 struct drm_i915_private *dev_priv = to_i915(dev); 2509 struct drm_atomic_state *state; 2510 int ret; 2511 2512 if (!HAS_DISPLAY(dev_priv)) 2513 return 0; 2514 2515 state = drm_atomic_helper_suspend(dev); 2516 ret = PTR_ERR_OR_ZERO(state); 2517 if (ret) 2518 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", 2519 ret); 2520 else 2521 dev_priv->modeset_restore_state = state; 2522 return ret; 2523 } 2524 2525 void intel_encoder_destroy(struct drm_encoder *encoder) 2526 { 2527 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2528 2529 drm_encoder_cleanup(encoder); 2530 kfree(intel_encoder); 2531 } 2532 2533 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) 2534 { 2535 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2536 2537 /* GDG double wide on either pipe, otherwise pipe A only */ 2538 return DISPLAY_VER(dev_priv) < 4 && 2539 (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); 2540 } 2541 2542 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) 2543 { 2544 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock; 2545 struct drm_rect src; 2546 2547 /* 2548 * We only use IF-ID interlacing. If we ever use 2549 * PF-ID we'll need to adjust the pixel_rate here. 2550 */ 2551 2552 if (!crtc_state->pch_pfit.enabled) 2553 return pixel_rate; 2554 2555 drm_rect_init(&src, 0, 0, 2556 drm_rect_width(&crtc_state->pipe_src) << 16, 2557 drm_rect_height(&crtc_state->pipe_src) << 16); 2558 2559 return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst, 2560 pixel_rate); 2561 } 2562 2563 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode, 2564 const struct drm_display_mode *timings) 2565 { 2566 mode->hdisplay = timings->crtc_hdisplay; 2567 mode->htotal = timings->crtc_htotal; 2568 mode->hsync_start = timings->crtc_hsync_start; 2569 mode->hsync_end = timings->crtc_hsync_end; 2570 2571 mode->vdisplay = timings->crtc_vdisplay; 2572 mode->vtotal = timings->crtc_vtotal; 2573 mode->vsync_start = timings->crtc_vsync_start; 2574 mode->vsync_end = timings->crtc_vsync_end; 2575 2576 mode->flags = timings->flags; 2577 mode->type = DRM_MODE_TYPE_DRIVER; 2578 2579 mode->clock = timings->crtc_clock; 2580 2581 drm_mode_set_name(mode); 2582 } 2583 2584 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) 2585 { 2586 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2587 2588 if (HAS_GMCH(dev_priv)) 2589 /* FIXME calculate proper pipe pixel rate for GMCH pfit */ 2590 crtc_state->pixel_rate = 2591 crtc_state->hw.pipe_mode.crtc_clock; 2592 else 2593 crtc_state->pixel_rate = 2594 ilk_pipe_pixel_rate(crtc_state); 2595 } 2596 2597 static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state *crtc_state, 2598 struct drm_display_mode *mode) 2599 { 2600 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2601 2602 if (num_pipes < 2) 2603 return; 2604 2605 mode->crtc_clock /= num_pipes; 2606 mode->crtc_hdisplay /= num_pipes; 2607 mode->crtc_hblank_start /= num_pipes; 2608 mode->crtc_hblank_end /= num_pipes; 2609 mode->crtc_hsync_start /= num_pipes; 2610 mode->crtc_hsync_end /= num_pipes; 2611 mode->crtc_htotal /= num_pipes; 2612 } 2613 2614 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state, 2615 struct drm_display_mode *mode) 2616 { 2617 int overlap = crtc_state->splitter.pixel_overlap; 2618 int n = crtc_state->splitter.link_count; 2619 2620 if (!crtc_state->splitter.enable) 2621 return; 2622 2623 /* 2624 * eDP MSO uses segment timings from EDID for transcoder 2625 * timings, but full mode for everything else. 2626 * 2627 * h_full = (h_segment - pixel_overlap) * link_count 2628 */ 2629 mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n; 2630 mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n; 2631 mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n; 2632 mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n; 2633 mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n; 2634 mode->crtc_htotal = (mode->crtc_htotal - overlap) * n; 2635 mode->crtc_clock *= n; 2636 } 2637 2638 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state) 2639 { 2640 struct drm_display_mode *mode = &crtc_state->hw.mode; 2641 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2642 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2643 2644 /* 2645 * Start with the adjusted_mode crtc timings, which 2646 * have been filled with the transcoder timings. 2647 */ 2648 drm_mode_copy(pipe_mode, adjusted_mode); 2649 2650 /* Expand MSO per-segment transcoder timings to full */ 2651 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2652 2653 /* 2654 * We want the full numbers in adjusted_mode normal timings, 2655 * adjusted_mode crtc timings are left with the raw transcoder 2656 * timings. 2657 */ 2658 intel_mode_from_crtc_timings(adjusted_mode, pipe_mode); 2659 2660 /* Populate the "user" mode with full numbers */ 2661 drm_mode_copy(mode, pipe_mode); 2662 intel_mode_from_crtc_timings(mode, mode); 2663 mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) * 2664 (intel_bigjoiner_num_pipes(crtc_state) ?: 1); 2665 mode->vdisplay = drm_rect_height(&crtc_state->pipe_src); 2666 2667 /* Derive per-pipe timings in case bigjoiner is used */ 2668 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2669 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2670 2671 intel_crtc_compute_pixel_rate(crtc_state); 2672 } 2673 2674 void intel_encoder_get_config(struct intel_encoder *encoder, 2675 struct intel_crtc_state *crtc_state) 2676 { 2677 encoder->get_config(encoder, crtc_state); 2678 2679 intel_crtc_readout_derived_state(crtc_state); 2680 } 2681 2682 static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state *crtc_state) 2683 { 2684 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2685 int width, height; 2686 2687 if (num_pipes < 2) 2688 return; 2689 2690 width = drm_rect_width(&crtc_state->pipe_src); 2691 height = drm_rect_height(&crtc_state->pipe_src); 2692 2693 drm_rect_init(&crtc_state->pipe_src, 0, 0, 2694 width / num_pipes, height); 2695 } 2696 2697 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state) 2698 { 2699 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2700 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2701 2702 intel_bigjoiner_compute_pipe_src(crtc_state); 2703 2704 /* 2705 * Pipe horizontal size must be even in: 2706 * - DVO ganged mode 2707 * - LVDS dual channel mode 2708 * - Double wide pipe 2709 */ 2710 if (drm_rect_width(&crtc_state->pipe_src) & 1) { 2711 if (crtc_state->double_wide) { 2712 drm_dbg_kms(&i915->drm, 2713 "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n", 2714 crtc->base.base.id, crtc->base.name); 2715 return -EINVAL; 2716 } 2717 2718 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 2719 intel_is_dual_link_lvds(i915)) { 2720 drm_dbg_kms(&i915->drm, 2721 "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n", 2722 crtc->base.base.id, crtc->base.name); 2723 return -EINVAL; 2724 } 2725 } 2726 2727 return 0; 2728 } 2729 2730 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state) 2731 { 2732 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2733 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2734 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2735 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2736 int clock_limit = i915->max_dotclk_freq; 2737 2738 /* 2739 * Start with the adjusted_mode crtc timings, which 2740 * have been filled with the transcoder timings. 2741 */ 2742 drm_mode_copy(pipe_mode, adjusted_mode); 2743 2744 /* Expand MSO per-segment transcoder timings to full */ 2745 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2746 2747 /* Derive per-pipe timings in case bigjoiner is used */ 2748 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2749 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2750 2751 if (DISPLAY_VER(i915) < 4) { 2752 clock_limit = i915->max_cdclk_freq * 9 / 10; 2753 2754 /* 2755 * Enable double wide mode when the dot clock 2756 * is > 90% of the (display) core speed. 2757 */ 2758 if (intel_crtc_supports_double_wide(crtc) && 2759 pipe_mode->crtc_clock > clock_limit) { 2760 clock_limit = i915->max_dotclk_freq; 2761 crtc_state->double_wide = true; 2762 } 2763 } 2764 2765 if (pipe_mode->crtc_clock > clock_limit) { 2766 drm_dbg_kms(&i915->drm, 2767 "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", 2768 crtc->base.base.id, crtc->base.name, 2769 pipe_mode->crtc_clock, clock_limit, 2770 str_yes_no(crtc_state->double_wide)); 2771 return -EINVAL; 2772 } 2773 2774 return 0; 2775 } 2776 2777 static int intel_crtc_compute_config(struct intel_atomic_state *state, 2778 struct intel_crtc *crtc) 2779 { 2780 struct intel_crtc_state *crtc_state = 2781 intel_atomic_get_new_crtc_state(state, crtc); 2782 int ret; 2783 2784 ret = intel_crtc_compute_pipe_src(crtc_state); 2785 if (ret) 2786 return ret; 2787 2788 ret = intel_crtc_compute_pipe_mode(crtc_state); 2789 if (ret) 2790 return ret; 2791 2792 intel_crtc_compute_pixel_rate(crtc_state); 2793 2794 if (crtc_state->has_pch_encoder) 2795 return ilk_fdi_compute_config(crtc, crtc_state); 2796 2797 return 0; 2798 } 2799 2800 static void 2801 intel_reduce_m_n_ratio(u32 *num, u32 *den) 2802 { 2803 while (*num > DATA_LINK_M_N_MASK || 2804 *den > DATA_LINK_M_N_MASK) { 2805 *num >>= 1; 2806 *den >>= 1; 2807 } 2808 } 2809 2810 static void compute_m_n(unsigned int m, unsigned int n, 2811 u32 *ret_m, u32 *ret_n, 2812 bool constant_n) 2813 { 2814 /* 2815 * Several DP dongles in particular seem to be fussy about 2816 * too large link M/N values. Give N value as 0x8000 that 2817 * should be acceptable by specific devices. 0x8000 is the 2818 * specified fixed N value for asynchronous clock mode, 2819 * which the devices expect also in synchronous clock mode. 2820 */ 2821 if (constant_n) 2822 *ret_n = DP_LINK_CONSTANT_N_VALUE; 2823 else 2824 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); 2825 2826 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n); 2827 intel_reduce_m_n_ratio(ret_m, ret_n); 2828 } 2829 2830 void 2831 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes, 2832 int pixel_clock, int link_clock, 2833 struct intel_link_m_n *m_n, 2834 bool constant_n, bool fec_enable) 2835 { 2836 u32 data_clock = bits_per_pixel * pixel_clock; 2837 2838 if (fec_enable) 2839 data_clock = intel_dp_mode_to_fec_clock(data_clock); 2840 2841 m_n->tu = 64; 2842 compute_m_n(data_clock, 2843 link_clock * nlanes * 8, 2844 &m_n->data_m, &m_n->data_n, 2845 constant_n); 2846 2847 compute_m_n(pixel_clock, link_clock, 2848 &m_n->link_m, &m_n->link_n, 2849 constant_n); 2850 } 2851 2852 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv) 2853 { 2854 /* 2855 * There may be no VBT; and if the BIOS enabled SSC we can 2856 * just keep using it to avoid unnecessary flicker. Whereas if the 2857 * BIOS isn't using it, don't assume it will work even if the VBT 2858 * indicates as much. 2859 */ 2860 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { 2861 bool bios_lvds_use_ssc = intel_de_read(dev_priv, 2862 PCH_DREF_CONTROL) & 2863 DREF_SSC1_ENABLE; 2864 2865 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { 2866 drm_dbg_kms(&dev_priv->drm, 2867 "SSC %s by BIOS, overriding VBT which says %s\n", 2868 str_enabled_disabled(bios_lvds_use_ssc), 2869 str_enabled_disabled(dev_priv->vbt.lvds_use_ssc)); 2870 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; 2871 } 2872 } 2873 } 2874 2875 void intel_zero_m_n(struct intel_link_m_n *m_n) 2876 { 2877 /* corresponds to 0 register value */ 2878 memset(m_n, 0, sizeof(*m_n)); 2879 m_n->tu = 1; 2880 } 2881 2882 void intel_set_m_n(struct drm_i915_private *i915, 2883 const struct intel_link_m_n *m_n, 2884 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 2885 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 2886 { 2887 intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); 2888 intel_de_write(i915, data_n_reg, m_n->data_n); 2889 intel_de_write(i915, link_m_reg, m_n->link_m); 2890 /* 2891 * On BDW+ writing LINK_N arms the double buffered update 2892 * of all the M/N registers, so it must be written last. 2893 */ 2894 intel_de_write(i915, link_n_reg, m_n->link_n); 2895 } 2896 2897 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, 2898 enum transcoder transcoder) 2899 { 2900 if (IS_HASWELL(dev_priv)) 2901 return transcoder == TRANSCODER_EDP; 2902 2903 return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv); 2904 } 2905 2906 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, 2907 enum transcoder transcoder, 2908 const struct intel_link_m_n *m_n) 2909 { 2910 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2911 enum pipe pipe = crtc->pipe; 2912 2913 if (DISPLAY_VER(dev_priv) >= 5) 2914 intel_set_m_n(dev_priv, m_n, 2915 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 2916 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 2917 else 2918 intel_set_m_n(dev_priv, m_n, 2919 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 2920 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 2921 } 2922 2923 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, 2924 enum transcoder transcoder, 2925 const struct intel_link_m_n *m_n) 2926 { 2927 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2928 2929 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 2930 return; 2931 2932 intel_set_m_n(dev_priv, m_n, 2933 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 2934 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 2935 } 2936 2937 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) 2938 { 2939 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2940 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2941 enum pipe pipe = crtc->pipe; 2942 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2943 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2944 u32 crtc_vtotal, crtc_vblank_end; 2945 int vsyncshift = 0; 2946 2947 /* We need to be careful not to changed the adjusted mode, for otherwise 2948 * the hw state checker will get angry at the mismatch. */ 2949 crtc_vtotal = adjusted_mode->crtc_vtotal; 2950 crtc_vblank_end = adjusted_mode->crtc_vblank_end; 2951 2952 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 2953 /* the chip adds 2 halflines automatically */ 2954 crtc_vtotal -= 1; 2955 crtc_vblank_end -= 1; 2956 2957 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 2958 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; 2959 else 2960 vsyncshift = adjusted_mode->crtc_hsync_start - 2961 adjusted_mode->crtc_htotal / 2; 2962 if (vsyncshift < 0) 2963 vsyncshift += adjusted_mode->crtc_htotal; 2964 } 2965 2966 if (DISPLAY_VER(dev_priv) > 3) 2967 intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder), 2968 vsyncshift); 2969 2970 intel_de_write(dev_priv, HTOTAL(cpu_transcoder), 2971 (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16)); 2972 intel_de_write(dev_priv, HBLANK(cpu_transcoder), 2973 (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16)); 2974 intel_de_write(dev_priv, HSYNC(cpu_transcoder), 2975 (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16)); 2976 2977 intel_de_write(dev_priv, VTOTAL(cpu_transcoder), 2978 (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16)); 2979 intel_de_write(dev_priv, VBLANK(cpu_transcoder), 2980 (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16)); 2981 intel_de_write(dev_priv, VSYNC(cpu_transcoder), 2982 (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16)); 2983 2984 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be 2985 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is 2986 * documented on the DDI_FUNC_CTL register description, EDP Input Select 2987 * bits. */ 2988 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && 2989 (pipe == PIPE_B || pipe == PIPE_C)) 2990 intel_de_write(dev_priv, VTOTAL(pipe), 2991 intel_de_read(dev_priv, VTOTAL(cpu_transcoder))); 2992 2993 } 2994 2995 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) 2996 { 2997 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2998 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2999 int width = drm_rect_width(&crtc_state->pipe_src); 3000 int height = drm_rect_height(&crtc_state->pipe_src); 3001 enum pipe pipe = crtc->pipe; 3002 3003 /* pipesrc controls the size that is scaled from, which should 3004 * always be the user's requested size. 3005 */ 3006 intel_de_write(dev_priv, PIPESRC(pipe), 3007 PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1)); 3008 } 3009 3010 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) 3011 { 3012 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3013 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3014 3015 if (DISPLAY_VER(dev_priv) == 2) 3016 return false; 3017 3018 if (DISPLAY_VER(dev_priv) >= 9 || 3019 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 3020 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW; 3021 else 3022 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK; 3023 } 3024 3025 static void intel_get_transcoder_timings(struct intel_crtc *crtc, 3026 struct intel_crtc_state *pipe_config) 3027 { 3028 struct drm_device *dev = crtc->base.dev; 3029 struct drm_i915_private *dev_priv = to_i915(dev); 3030 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3031 u32 tmp; 3032 3033 tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder)); 3034 pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; 3035 pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; 3036 3037 if (!transcoder_is_dsi(cpu_transcoder)) { 3038 tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder)); 3039 pipe_config->hw.adjusted_mode.crtc_hblank_start = 3040 (tmp & 0xffff) + 1; 3041 pipe_config->hw.adjusted_mode.crtc_hblank_end = 3042 ((tmp >> 16) & 0xffff) + 1; 3043 } 3044 tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder)); 3045 pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; 3046 pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; 3047 3048 tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder)); 3049 pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; 3050 pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; 3051 3052 if (!transcoder_is_dsi(cpu_transcoder)) { 3053 tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder)); 3054 pipe_config->hw.adjusted_mode.crtc_vblank_start = 3055 (tmp & 0xffff) + 1; 3056 pipe_config->hw.adjusted_mode.crtc_vblank_end = 3057 ((tmp >> 16) & 0xffff) + 1; 3058 } 3059 tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder)); 3060 pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; 3061 pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; 3062 3063 if (intel_pipe_is_interlaced(pipe_config)) { 3064 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; 3065 pipe_config->hw.adjusted_mode.crtc_vtotal += 1; 3066 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1; 3067 } 3068 } 3069 3070 static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state) 3071 { 3072 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3073 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 3074 enum pipe master_pipe, pipe = crtc->pipe; 3075 int width; 3076 3077 if (num_pipes < 2) 3078 return; 3079 3080 master_pipe = bigjoiner_master_pipe(crtc_state); 3081 width = drm_rect_width(&crtc_state->pipe_src); 3082 3083 drm_rect_translate_to(&crtc_state->pipe_src, 3084 (pipe - master_pipe) * width, 0); 3085 } 3086 3087 static void intel_get_pipe_src_size(struct intel_crtc *crtc, 3088 struct intel_crtc_state *pipe_config) 3089 { 3090 struct drm_device *dev = crtc->base.dev; 3091 struct drm_i915_private *dev_priv = to_i915(dev); 3092 u32 tmp; 3093 3094 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe)); 3095 3096 drm_rect_init(&pipe_config->pipe_src, 0, 0, 3097 REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1, 3098 REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1); 3099 3100 intel_bigjoiner_adjust_pipe_src(pipe_config); 3101 } 3102 3103 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) 3104 { 3105 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3106 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3107 u32 pipeconf = 0; 3108 3109 /* we keep both pipes enabled on 830 */ 3110 if (IS_I830(dev_priv)) 3111 pipeconf |= PIPECONF_ENABLE; 3112 3113 if (crtc_state->double_wide) 3114 pipeconf |= PIPECONF_DOUBLE_WIDE; 3115 3116 /* only g4x and later have fancy bpc/dither controls */ 3117 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 3118 IS_CHERRYVIEW(dev_priv)) { 3119 /* Bspec claims that we can't use dithering for 30bpp pipes. */ 3120 if (crtc_state->dither && crtc_state->pipe_bpp != 30) 3121 pipeconf |= PIPECONF_DITHER_EN | 3122 PIPECONF_DITHER_TYPE_SP; 3123 3124 switch (crtc_state->pipe_bpp) { 3125 default: 3126 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3127 MISSING_CASE(crtc_state->pipe_bpp); 3128 fallthrough; 3129 case 18: 3130 pipeconf |= PIPECONF_BPC_6; 3131 break; 3132 case 24: 3133 pipeconf |= PIPECONF_BPC_8; 3134 break; 3135 case 30: 3136 pipeconf |= PIPECONF_BPC_10; 3137 break; 3138 } 3139 } 3140 3141 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 3142 if (DISPLAY_VER(dev_priv) < 4 || 3143 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3144 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; 3145 else 3146 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; 3147 } else { 3148 pipeconf |= PIPECONF_INTERLACE_PROGRESSIVE; 3149 } 3150 3151 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 3152 crtc_state->limited_color_range) 3153 pipeconf |= PIPECONF_COLOR_RANGE_SELECT; 3154 3155 pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); 3156 3157 pipeconf |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3158 3159 intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf); 3160 intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe)); 3161 } 3162 3163 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv) 3164 { 3165 if (IS_I830(dev_priv)) 3166 return false; 3167 3168 return DISPLAY_VER(dev_priv) >= 4 || 3169 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); 3170 } 3171 3172 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state) 3173 { 3174 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3175 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3176 u32 tmp; 3177 3178 if (!i9xx_has_pfit(dev_priv)) 3179 return; 3180 3181 tmp = intel_de_read(dev_priv, PFIT_CONTROL); 3182 if (!(tmp & PFIT_ENABLE)) 3183 return; 3184 3185 /* Check whether the pfit is attached to our pipe. */ 3186 if (DISPLAY_VER(dev_priv) < 4) { 3187 if (crtc->pipe != PIPE_B) 3188 return; 3189 } else { 3190 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) 3191 return; 3192 } 3193 3194 crtc_state->gmch_pfit.control = tmp; 3195 crtc_state->gmch_pfit.pgm_ratios = 3196 intel_de_read(dev_priv, PFIT_PGM_RATIOS); 3197 } 3198 3199 static void vlv_crtc_clock_get(struct intel_crtc *crtc, 3200 struct intel_crtc_state *pipe_config) 3201 { 3202 struct drm_device *dev = crtc->base.dev; 3203 struct drm_i915_private *dev_priv = to_i915(dev); 3204 enum pipe pipe = crtc->pipe; 3205 struct dpll clock; 3206 u32 mdiv; 3207 int refclk = 100000; 3208 3209 /* In case of DSI, DPLL will not be used */ 3210 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 3211 return; 3212 3213 vlv_dpio_get(dev_priv); 3214 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); 3215 vlv_dpio_put(dev_priv); 3216 3217 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; 3218 clock.m2 = mdiv & DPIO_M2DIV_MASK; 3219 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; 3220 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; 3221 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; 3222 3223 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); 3224 } 3225 3226 static void chv_crtc_clock_get(struct intel_crtc *crtc, 3227 struct intel_crtc_state *pipe_config) 3228 { 3229 struct drm_device *dev = crtc->base.dev; 3230 struct drm_i915_private *dev_priv = to_i915(dev); 3231 enum pipe pipe = crtc->pipe; 3232 enum dpio_channel port = vlv_pipe_to_channel(pipe); 3233 struct dpll clock; 3234 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; 3235 int refclk = 100000; 3236 3237 /* In case of DSI, DPLL will not be used */ 3238 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 3239 return; 3240 3241 vlv_dpio_get(dev_priv); 3242 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); 3243 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); 3244 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); 3245 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); 3246 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); 3247 vlv_dpio_put(dev_priv); 3248 3249 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; 3250 clock.m2 = (pll_dw0 & 0xff) << 22; 3251 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) 3252 clock.m2 |= pll_dw2 & 0x3fffff; 3253 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; 3254 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; 3255 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; 3256 3257 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); 3258 } 3259 3260 static enum intel_output_format 3261 bdw_get_pipemisc_output_format(struct intel_crtc *crtc) 3262 { 3263 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3264 u32 tmp; 3265 3266 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); 3267 3268 if (tmp & PIPEMISC_YUV420_ENABLE) { 3269 /* We support 4:2:0 in full blend mode only */ 3270 drm_WARN_ON(&dev_priv->drm, 3271 (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0); 3272 3273 return INTEL_OUTPUT_FORMAT_YCBCR420; 3274 } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) { 3275 return INTEL_OUTPUT_FORMAT_YCBCR444; 3276 } else { 3277 return INTEL_OUTPUT_FORMAT_RGB; 3278 } 3279 } 3280 3281 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state) 3282 { 3283 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3284 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 3285 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3286 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 3287 u32 tmp; 3288 3289 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); 3290 3291 if (tmp & DISP_PIPE_GAMMA_ENABLE) 3292 crtc_state->gamma_enable = true; 3293 3294 if (!HAS_GMCH(dev_priv) && 3295 tmp & DISP_PIPE_CSC_ENABLE) 3296 crtc_state->csc_enable = true; 3297 } 3298 3299 static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 3300 struct intel_crtc_state *pipe_config) 3301 { 3302 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3303 enum intel_display_power_domain power_domain; 3304 intel_wakeref_t wakeref; 3305 u32 tmp; 3306 bool ret; 3307 3308 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3309 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3310 if (!wakeref) 3311 return false; 3312 3313 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3314 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3315 pipe_config->shared_dpll = NULL; 3316 3317 ret = false; 3318 3319 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); 3320 if (!(tmp & PIPECONF_ENABLE)) 3321 goto out; 3322 3323 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 3324 IS_CHERRYVIEW(dev_priv)) { 3325 switch (tmp & PIPECONF_BPC_MASK) { 3326 case PIPECONF_BPC_6: 3327 pipe_config->pipe_bpp = 18; 3328 break; 3329 case PIPECONF_BPC_8: 3330 pipe_config->pipe_bpp = 24; 3331 break; 3332 case PIPECONF_BPC_10: 3333 pipe_config->pipe_bpp = 30; 3334 break; 3335 default: 3336 MISSING_CASE(tmp); 3337 break; 3338 } 3339 } 3340 3341 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 3342 (tmp & PIPECONF_COLOR_RANGE_SELECT)) 3343 pipe_config->limited_color_range = true; 3344 3345 pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_I9XX, tmp); 3346 3347 pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1; 3348 3349 if (IS_CHERRYVIEW(dev_priv)) 3350 pipe_config->cgm_mode = intel_de_read(dev_priv, 3351 CGM_PIPE_MODE(crtc->pipe)); 3352 3353 i9xx_get_pipe_color_config(pipe_config); 3354 intel_color_get_config(pipe_config); 3355 3356 if (DISPLAY_VER(dev_priv) < 4) 3357 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; 3358 3359 intel_get_transcoder_timings(crtc, pipe_config); 3360 intel_get_pipe_src_size(crtc, pipe_config); 3361 3362 i9xx_get_pfit_config(pipe_config); 3363 3364 if (DISPLAY_VER(dev_priv) >= 4) { 3365 /* No way to read it out on pipes B and C */ 3366 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) 3367 tmp = dev_priv->chv_dpll_md[crtc->pipe]; 3368 else 3369 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe)); 3370 pipe_config->pixel_multiplier = 3371 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) 3372 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; 3373 pipe_config->dpll_hw_state.dpll_md = tmp; 3374 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 3375 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 3376 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe)); 3377 pipe_config->pixel_multiplier = 3378 ((tmp & SDVO_MULTIPLIER_MASK) 3379 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; 3380 } else { 3381 /* Note that on i915G/GM the pixel multiplier is in the sdvo 3382 * port and will be fixed up in the encoder->get_config 3383 * function. */ 3384 pipe_config->pixel_multiplier = 1; 3385 } 3386 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv, 3387 DPLL(crtc->pipe)); 3388 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 3389 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv, 3390 FP0(crtc->pipe)); 3391 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv, 3392 FP1(crtc->pipe)); 3393 } else { 3394 /* Mask out read-only status bits. */ 3395 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | 3396 DPLL_PORTC_READY_MASK | 3397 DPLL_PORTB_READY_MASK); 3398 } 3399 3400 if (IS_CHERRYVIEW(dev_priv)) 3401 chv_crtc_clock_get(crtc, pipe_config); 3402 else if (IS_VALLEYVIEW(dev_priv)) 3403 vlv_crtc_clock_get(crtc, pipe_config); 3404 else 3405 i9xx_crtc_clock_get(crtc, pipe_config); 3406 3407 /* 3408 * Normally the dotclock is filled in by the encoder .get_config() 3409 * but in case the pipe is enabled w/o any ports we need a sane 3410 * default. 3411 */ 3412 pipe_config->hw.adjusted_mode.crtc_clock = 3413 pipe_config->port_clock / pipe_config->pixel_multiplier; 3414 3415 ret = true; 3416 3417 out: 3418 intel_display_power_put(dev_priv, power_domain, wakeref); 3419 3420 return ret; 3421 } 3422 3423 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) 3424 { 3425 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3426 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3427 enum pipe pipe = crtc->pipe; 3428 u32 val; 3429 3430 val = 0; 3431 3432 switch (crtc_state->pipe_bpp) { 3433 default: 3434 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3435 MISSING_CASE(crtc_state->pipe_bpp); 3436 fallthrough; 3437 case 18: 3438 val |= PIPECONF_BPC_6; 3439 break; 3440 case 24: 3441 val |= PIPECONF_BPC_8; 3442 break; 3443 case 30: 3444 val |= PIPECONF_BPC_10; 3445 break; 3446 case 36: 3447 val |= PIPECONF_BPC_12; 3448 break; 3449 } 3450 3451 if (crtc_state->dither) 3452 val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP; 3453 3454 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3455 val |= PIPECONF_INTERLACE_IF_ID_ILK; 3456 else 3457 val |= PIPECONF_INTERLACE_PF_PD_ILK; 3458 3459 /* 3460 * This would end up with an odd purple hue over 3461 * the entire display. Make sure we don't do it. 3462 */ 3463 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 3464 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 3465 3466 if (crtc_state->limited_color_range && 3467 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3468 val |= PIPECONF_COLOR_RANGE_SELECT; 3469 3470 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3471 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709; 3472 3473 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); 3474 3475 val |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3476 val |= PIPECONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay); 3477 3478 intel_de_write(dev_priv, PIPECONF(pipe), val); 3479 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 3480 } 3481 3482 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) 3483 { 3484 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3485 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3486 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3487 u32 val = 0; 3488 3489 if (IS_HASWELL(dev_priv) && crtc_state->dither) 3490 val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP; 3491 3492 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3493 val |= PIPECONF_INTERLACE_IF_ID_ILK; 3494 else 3495 val |= PIPECONF_INTERLACE_PF_PD_ILK; 3496 3497 if (IS_HASWELL(dev_priv) && 3498 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3499 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW; 3500 3501 intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val); 3502 intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder)); 3503 } 3504 3505 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) 3506 { 3507 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3508 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3509 u32 val = 0; 3510 3511 switch (crtc_state->pipe_bpp) { 3512 case 18: 3513 val |= PIPEMISC_BPC_6; 3514 break; 3515 case 24: 3516 val |= PIPEMISC_BPC_8; 3517 break; 3518 case 30: 3519 val |= PIPEMISC_BPC_10; 3520 break; 3521 case 36: 3522 /* Port output 12BPC defined for ADLP+ */ 3523 if (DISPLAY_VER(dev_priv) > 12) 3524 val |= PIPEMISC_BPC_12_ADLP; 3525 break; 3526 default: 3527 MISSING_CASE(crtc_state->pipe_bpp); 3528 break; 3529 } 3530 3531 if (crtc_state->dither) 3532 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; 3533 3534 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 3535 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 3536 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV; 3537 3538 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 3539 val |= PIPEMISC_YUV420_ENABLE | 3540 PIPEMISC_YUV420_MODE_FULL_BLEND; 3541 3542 if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state)) 3543 val |= PIPEMISC_HDR_MODE_PRECISION; 3544 3545 if (DISPLAY_VER(dev_priv) >= 12) 3546 val |= PIPEMISC_PIXEL_ROUNDING_TRUNC; 3547 3548 intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val); 3549 } 3550 3551 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) 3552 { 3553 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3554 u32 tmp; 3555 3556 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); 3557 3558 switch (tmp & PIPEMISC_BPC_MASK) { 3559 case PIPEMISC_BPC_6: 3560 return 18; 3561 case PIPEMISC_BPC_8: 3562 return 24; 3563 case PIPEMISC_BPC_10: 3564 return 30; 3565 /* 3566 * PORT OUTPUT 12 BPC defined for ADLP+. 3567 * 3568 * TODO: 3569 * For previous platforms with DSI interface, bits 5:7 3570 * are used for storing pipe_bpp irrespective of dithering. 3571 * Since the value of 12 BPC is not defined for these bits 3572 * on older platforms, need to find a workaround for 12 BPC 3573 * MIPI DSI HW readout. 3574 */ 3575 case PIPEMISC_BPC_12_ADLP: 3576 if (DISPLAY_VER(dev_priv) > 12) 3577 return 36; 3578 fallthrough; 3579 default: 3580 MISSING_CASE(tmp); 3581 return 0; 3582 } 3583 } 3584 3585 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) 3586 { 3587 /* 3588 * Account for spread spectrum to avoid 3589 * oversubscribing the link. Max center spread 3590 * is 2.5%; use 5% for safety's sake. 3591 */ 3592 u32 bps = target_clock * bpp * 21 / 20; 3593 return DIV_ROUND_UP(bps, link_bw * 8); 3594 } 3595 3596 void intel_get_m_n(struct drm_i915_private *i915, 3597 struct intel_link_m_n *m_n, 3598 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 3599 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 3600 { 3601 m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK; 3602 m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK; 3603 m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK; 3604 m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK; 3605 m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1; 3606 } 3607 3608 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, 3609 enum transcoder transcoder, 3610 struct intel_link_m_n *m_n) 3611 { 3612 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3613 enum pipe pipe = crtc->pipe; 3614 3615 if (DISPLAY_VER(dev_priv) >= 5) 3616 intel_get_m_n(dev_priv, m_n, 3617 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 3618 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 3619 else 3620 intel_get_m_n(dev_priv, m_n, 3621 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 3622 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 3623 } 3624 3625 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, 3626 enum transcoder transcoder, 3627 struct intel_link_m_n *m_n) 3628 { 3629 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3630 3631 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 3632 return; 3633 3634 intel_get_m_n(dev_priv, m_n, 3635 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 3636 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 3637 } 3638 3639 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state, 3640 u32 pos, u32 size) 3641 { 3642 drm_rect_init(&crtc_state->pch_pfit.dst, 3643 pos >> 16, pos & 0xffff, 3644 size >> 16, size & 0xffff); 3645 } 3646 3647 static void skl_get_pfit_config(struct intel_crtc_state *crtc_state) 3648 { 3649 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3650 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3651 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; 3652 int id = -1; 3653 int i; 3654 3655 /* find scaler attached to this pipe */ 3656 for (i = 0; i < crtc->num_scalers; i++) { 3657 u32 ctl, pos, size; 3658 3659 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i)); 3660 if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN) 3661 continue; 3662 3663 id = i; 3664 crtc_state->pch_pfit.enabled = true; 3665 3666 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i)); 3667 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i)); 3668 3669 ilk_get_pfit_pos_size(crtc_state, pos, size); 3670 3671 scaler_state->scalers[i].in_use = true; 3672 break; 3673 } 3674 3675 scaler_state->scaler_id = id; 3676 if (id >= 0) 3677 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); 3678 else 3679 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); 3680 } 3681 3682 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state) 3683 { 3684 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3685 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3686 u32 ctl, pos, size; 3687 3688 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe)); 3689 if ((ctl & PF_ENABLE) == 0) 3690 return; 3691 3692 crtc_state->pch_pfit.enabled = true; 3693 3694 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe)); 3695 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe)); 3696 3697 ilk_get_pfit_pos_size(crtc_state, pos, size); 3698 3699 /* 3700 * We currently do not free assignements of panel fitters on 3701 * ivb/hsw (since we don't use the higher upscaling modes which 3702 * differentiates them) so just WARN about this case for now. 3703 */ 3704 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 7 && 3705 (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe)); 3706 } 3707 3708 static bool ilk_get_pipe_config(struct intel_crtc *crtc, 3709 struct intel_crtc_state *pipe_config) 3710 { 3711 struct drm_device *dev = crtc->base.dev; 3712 struct drm_i915_private *dev_priv = to_i915(dev); 3713 enum intel_display_power_domain power_domain; 3714 intel_wakeref_t wakeref; 3715 u32 tmp; 3716 bool ret; 3717 3718 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3719 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3720 if (!wakeref) 3721 return false; 3722 3723 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3724 pipe_config->shared_dpll = NULL; 3725 3726 ret = false; 3727 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); 3728 if (!(tmp & PIPECONF_ENABLE)) 3729 goto out; 3730 3731 switch (tmp & PIPECONF_BPC_MASK) { 3732 case PIPECONF_BPC_6: 3733 pipe_config->pipe_bpp = 18; 3734 break; 3735 case PIPECONF_BPC_8: 3736 pipe_config->pipe_bpp = 24; 3737 break; 3738 case PIPECONF_BPC_10: 3739 pipe_config->pipe_bpp = 30; 3740 break; 3741 case PIPECONF_BPC_12: 3742 pipe_config->pipe_bpp = 36; 3743 break; 3744 default: 3745 break; 3746 } 3747 3748 if (tmp & PIPECONF_COLOR_RANGE_SELECT) 3749 pipe_config->limited_color_range = true; 3750 3751 switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) { 3752 case PIPECONF_OUTPUT_COLORSPACE_YUV601: 3753 case PIPECONF_OUTPUT_COLORSPACE_YUV709: 3754 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3755 break; 3756 default: 3757 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3758 break; 3759 } 3760 3761 pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_ILK, tmp); 3762 3763 pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1; 3764 3765 pipe_config->msa_timing_delay = REG_FIELD_GET(PIPECONF_MSA_TIMING_DELAY_MASK, tmp); 3766 3767 pipe_config->csc_mode = intel_de_read(dev_priv, 3768 PIPE_CSC_MODE(crtc->pipe)); 3769 3770 i9xx_get_pipe_color_config(pipe_config); 3771 intel_color_get_config(pipe_config); 3772 3773 pipe_config->pixel_multiplier = 1; 3774 3775 ilk_pch_get_config(pipe_config); 3776 3777 intel_get_transcoder_timings(crtc, pipe_config); 3778 intel_get_pipe_src_size(crtc, pipe_config); 3779 3780 ilk_get_pfit_config(pipe_config); 3781 3782 ret = true; 3783 3784 out: 3785 intel_display_power_put(dev_priv, power_domain, wakeref); 3786 3787 return ret; 3788 } 3789 3790 static u8 bigjoiner_pipes(struct drm_i915_private *i915) 3791 { 3792 if (DISPLAY_VER(i915) >= 12) 3793 return BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D); 3794 else if (DISPLAY_VER(i915) >= 11) 3795 return BIT(PIPE_B) | BIT(PIPE_C); 3796 else 3797 return 0; 3798 } 3799 3800 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv, 3801 enum transcoder cpu_transcoder) 3802 { 3803 enum intel_display_power_domain power_domain; 3804 intel_wakeref_t wakeref; 3805 u32 tmp = 0; 3806 3807 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3808 3809 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3810 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3811 3812 return tmp & TRANS_DDI_FUNC_ENABLE; 3813 } 3814 3815 static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv, 3816 u8 *master_pipes, u8 *slave_pipes) 3817 { 3818 struct intel_crtc *crtc; 3819 3820 *master_pipes = 0; 3821 *slave_pipes = 0; 3822 3823 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, 3824 bigjoiner_pipes(dev_priv)) { 3825 enum intel_display_power_domain power_domain; 3826 enum pipe pipe = crtc->pipe; 3827 intel_wakeref_t wakeref; 3828 3829 power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe); 3830 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3831 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3832 3833 if (!(tmp & BIG_JOINER_ENABLE)) 3834 continue; 3835 3836 if (tmp & MASTER_BIG_JOINER_ENABLE) 3837 *master_pipes |= BIT(pipe); 3838 else 3839 *slave_pipes |= BIT(pipe); 3840 } 3841 3842 if (DISPLAY_VER(dev_priv) < 13) 3843 continue; 3844 3845 power_domain = POWER_DOMAIN_PIPE(pipe); 3846 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3847 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3848 3849 if (tmp & UNCOMPRESSED_JOINER_MASTER) 3850 *master_pipes |= BIT(pipe); 3851 if (tmp & UNCOMPRESSED_JOINER_SLAVE) 3852 *slave_pipes |= BIT(pipe); 3853 } 3854 } 3855 3856 /* Bigjoiner pipes should always be consecutive master and slave */ 3857 drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1, 3858 "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n", 3859 *master_pipes, *slave_pipes); 3860 } 3861 3862 static enum pipe get_bigjoiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3863 { 3864 if ((slave_pipes & BIT(pipe)) == 0) 3865 return pipe; 3866 3867 /* ignore everything above our pipe */ 3868 master_pipes &= ~GENMASK(7, pipe); 3869 3870 /* highest remaining bit should be our master pipe */ 3871 return fls(master_pipes) - 1; 3872 } 3873 3874 static u8 get_bigjoiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3875 { 3876 enum pipe master_pipe, next_master_pipe; 3877 3878 master_pipe = get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes); 3879 3880 if ((master_pipes & BIT(master_pipe)) == 0) 3881 return 0; 3882 3883 /* ignore our master pipe and everything below it */ 3884 master_pipes &= ~GENMASK(master_pipe, 0); 3885 /* make sure a high bit is set for the ffs() */ 3886 master_pipes |= BIT(7); 3887 /* lowest remaining bit should be the next master pipe */ 3888 next_master_pipe = ffs(master_pipes) - 1; 3889 3890 return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe); 3891 } 3892 3893 static u8 hsw_panel_transcoders(struct drm_i915_private *i915) 3894 { 3895 u8 panel_transcoder_mask = BIT(TRANSCODER_EDP); 3896 3897 if (DISPLAY_VER(i915) >= 11) 3898 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); 3899 3900 return panel_transcoder_mask; 3901 } 3902 3903 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) 3904 { 3905 struct drm_device *dev = crtc->base.dev; 3906 struct drm_i915_private *dev_priv = to_i915(dev); 3907 u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv); 3908 enum transcoder cpu_transcoder; 3909 u8 master_pipes, slave_pipes; 3910 u8 enabled_transcoders = 0; 3911 3912 /* 3913 * XXX: Do intel_display_power_get_if_enabled before reading this (for 3914 * consistency and less surprising code; it's in always on power). 3915 */ 3916 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, 3917 panel_transcoder_mask) { 3918 enum intel_display_power_domain power_domain; 3919 intel_wakeref_t wakeref; 3920 enum pipe trans_pipe; 3921 u32 tmp = 0; 3922 3923 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3924 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3925 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3926 3927 if (!(tmp & TRANS_DDI_FUNC_ENABLE)) 3928 continue; 3929 3930 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 3931 default: 3932 drm_WARN(dev, 1, 3933 "unknown pipe linked to transcoder %s\n", 3934 transcoder_name(cpu_transcoder)); 3935 fallthrough; 3936 case TRANS_DDI_EDP_INPUT_A_ONOFF: 3937 case TRANS_DDI_EDP_INPUT_A_ON: 3938 trans_pipe = PIPE_A; 3939 break; 3940 case TRANS_DDI_EDP_INPUT_B_ONOFF: 3941 trans_pipe = PIPE_B; 3942 break; 3943 case TRANS_DDI_EDP_INPUT_C_ONOFF: 3944 trans_pipe = PIPE_C; 3945 break; 3946 case TRANS_DDI_EDP_INPUT_D_ONOFF: 3947 trans_pipe = PIPE_D; 3948 break; 3949 } 3950 3951 if (trans_pipe == crtc->pipe) 3952 enabled_transcoders |= BIT(cpu_transcoder); 3953 } 3954 3955 /* single pipe or bigjoiner master */ 3956 cpu_transcoder = (enum transcoder) crtc->pipe; 3957 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 3958 enabled_transcoders |= BIT(cpu_transcoder); 3959 3960 /* bigjoiner slave -> consider the master pipe's transcoder as well */ 3961 enabled_bigjoiner_pipes(dev_priv, &master_pipes, &slave_pipes); 3962 if (slave_pipes & BIT(crtc->pipe)) { 3963 cpu_transcoder = (enum transcoder) 3964 get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes); 3965 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 3966 enabled_transcoders |= BIT(cpu_transcoder); 3967 } 3968 3969 return enabled_transcoders; 3970 } 3971 3972 static bool has_edp_transcoders(u8 enabled_transcoders) 3973 { 3974 return enabled_transcoders & BIT(TRANSCODER_EDP); 3975 } 3976 3977 static bool has_dsi_transcoders(u8 enabled_transcoders) 3978 { 3979 return enabled_transcoders & (BIT(TRANSCODER_DSI_0) | 3980 BIT(TRANSCODER_DSI_1)); 3981 } 3982 3983 static bool has_pipe_transcoders(u8 enabled_transcoders) 3984 { 3985 return enabled_transcoders & ~(BIT(TRANSCODER_EDP) | 3986 BIT(TRANSCODER_DSI_0) | 3987 BIT(TRANSCODER_DSI_1)); 3988 } 3989 3990 static void assert_enabled_transcoders(struct drm_i915_private *i915, 3991 u8 enabled_transcoders) 3992 { 3993 /* Only one type of transcoder please */ 3994 drm_WARN_ON(&i915->drm, 3995 has_edp_transcoders(enabled_transcoders) + 3996 has_dsi_transcoders(enabled_transcoders) + 3997 has_pipe_transcoders(enabled_transcoders) > 1); 3998 3999 /* Only DSI transcoders can be ganged */ 4000 drm_WARN_ON(&i915->drm, 4001 !has_dsi_transcoders(enabled_transcoders) && 4002 !is_power_of_2(enabled_transcoders)); 4003 } 4004 4005 static bool hsw_get_transcoder_state(struct intel_crtc *crtc, 4006 struct intel_crtc_state *pipe_config, 4007 struct intel_display_power_domain_set *power_domain_set) 4008 { 4009 struct drm_device *dev = crtc->base.dev; 4010 struct drm_i915_private *dev_priv = to_i915(dev); 4011 unsigned long enabled_transcoders; 4012 u32 tmp; 4013 4014 enabled_transcoders = hsw_enabled_transcoders(crtc); 4015 if (!enabled_transcoders) 4016 return false; 4017 4018 assert_enabled_transcoders(dev_priv, enabled_transcoders); 4019 4020 /* 4021 * With the exception of DSI we should only ever have 4022 * a single enabled transcoder. With DSI let's just 4023 * pick the first one. 4024 */ 4025 pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1; 4026 4027 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 4028 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) 4029 return false; 4030 4031 if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) { 4032 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); 4033 4034 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF) 4035 pipe_config->pch_pfit.force_thru = true; 4036 } 4037 4038 tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder)); 4039 4040 return tmp & PIPECONF_ENABLE; 4041 } 4042 4043 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, 4044 struct intel_crtc_state *pipe_config, 4045 struct intel_display_power_domain_set *power_domain_set) 4046 { 4047 struct drm_device *dev = crtc->base.dev; 4048 struct drm_i915_private *dev_priv = to_i915(dev); 4049 enum transcoder cpu_transcoder; 4050 enum port port; 4051 u32 tmp; 4052 4053 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { 4054 if (port == PORT_A) 4055 cpu_transcoder = TRANSCODER_DSI_A; 4056 else 4057 cpu_transcoder = TRANSCODER_DSI_C; 4058 4059 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 4060 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) 4061 continue; 4062 4063 /* 4064 * The PLL needs to be enabled with a valid divider 4065 * configuration, otherwise accessing DSI registers will hang 4066 * the machine. See BSpec North Display Engine 4067 * registers/MIPI[BXT]. We can break out here early, since we 4068 * need the same DSI PLL to be enabled for both DSI ports. 4069 */ 4070 if (!bxt_dsi_pll_is_enabled(dev_priv)) 4071 break; 4072 4073 /* XXX: this works for video mode only */ 4074 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); 4075 if (!(tmp & DPI_ENABLE)) 4076 continue; 4077 4078 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 4079 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) 4080 continue; 4081 4082 pipe_config->cpu_transcoder = cpu_transcoder; 4083 break; 4084 } 4085 4086 return transcoder_is_dsi(pipe_config->cpu_transcoder); 4087 } 4088 4089 static void intel_bigjoiner_get_config(struct intel_crtc_state *crtc_state) 4090 { 4091 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4092 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4093 u8 master_pipes, slave_pipes; 4094 enum pipe pipe = crtc->pipe; 4095 4096 enabled_bigjoiner_pipes(i915, &master_pipes, &slave_pipes); 4097 4098 if (((master_pipes | slave_pipes) & BIT(pipe)) == 0) 4099 return; 4100 4101 crtc_state->bigjoiner_pipes = 4102 BIT(get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes)) | 4103 get_bigjoiner_slave_pipes(pipe, master_pipes, slave_pipes); 4104 } 4105 4106 static bool hsw_get_pipe_config(struct intel_crtc *crtc, 4107 struct intel_crtc_state *pipe_config) 4108 { 4109 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4110 struct intel_display_power_domain_set power_domain_set = { }; 4111 bool active; 4112 u32 tmp; 4113 4114 if (!intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set, 4115 POWER_DOMAIN_PIPE(crtc->pipe))) 4116 return false; 4117 4118 pipe_config->shared_dpll = NULL; 4119 4120 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_set); 4121 4122 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 4123 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_set)) { 4124 drm_WARN_ON(&dev_priv->drm, active); 4125 active = true; 4126 } 4127 4128 if (!active) 4129 goto out; 4130 4131 intel_dsc_get_config(pipe_config); 4132 intel_bigjoiner_get_config(pipe_config); 4133 4134 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || 4135 DISPLAY_VER(dev_priv) >= 11) 4136 intel_get_transcoder_timings(crtc, pipe_config); 4137 4138 if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder)) 4139 intel_vrr_get_config(crtc, pipe_config); 4140 4141 intel_get_pipe_src_size(crtc, pipe_config); 4142 4143 if (IS_HASWELL(dev_priv)) { 4144 u32 tmp = intel_de_read(dev_priv, 4145 PIPECONF(pipe_config->cpu_transcoder)); 4146 4147 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW) 4148 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 4149 else 4150 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 4151 } else { 4152 pipe_config->output_format = 4153 bdw_get_pipemisc_output_format(crtc); 4154 } 4155 4156 pipe_config->gamma_mode = intel_de_read(dev_priv, 4157 GAMMA_MODE(crtc->pipe)); 4158 4159 pipe_config->csc_mode = intel_de_read(dev_priv, 4160 PIPE_CSC_MODE(crtc->pipe)); 4161 4162 if (DISPLAY_VER(dev_priv) >= 9) { 4163 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe)); 4164 4165 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE) 4166 pipe_config->gamma_enable = true; 4167 4168 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE) 4169 pipe_config->csc_enable = true; 4170 } else { 4171 i9xx_get_pipe_color_config(pipe_config); 4172 } 4173 4174 intel_color_get_config(pipe_config); 4175 4176 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe)); 4177 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); 4178 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 4179 pipe_config->ips_linetime = 4180 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); 4181 4182 if (intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set, 4183 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) { 4184 if (DISPLAY_VER(dev_priv) >= 9) 4185 skl_get_pfit_config(pipe_config); 4186 else 4187 ilk_get_pfit_config(pipe_config); 4188 } 4189 4190 hsw_ips_get_config(pipe_config); 4191 4192 if (pipe_config->cpu_transcoder != TRANSCODER_EDP && 4193 !transcoder_is_dsi(pipe_config->cpu_transcoder)) { 4194 pipe_config->pixel_multiplier = 4195 intel_de_read(dev_priv, 4196 PIPE_MULT(pipe_config->cpu_transcoder)) + 1; 4197 } else { 4198 pipe_config->pixel_multiplier = 1; 4199 } 4200 4201 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { 4202 tmp = intel_de_read(dev_priv, CHICKEN_TRANS(pipe_config->cpu_transcoder)); 4203 4204 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1; 4205 } else { 4206 /* no idea if this is correct */ 4207 pipe_config->framestart_delay = 1; 4208 } 4209 4210 out: 4211 intel_display_power_put_all_in_set(dev_priv, &power_domain_set); 4212 4213 return active; 4214 } 4215 4216 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state) 4217 { 4218 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4219 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4220 4221 if (!i915->display->get_pipe_config(crtc, crtc_state)) 4222 return false; 4223 4224 crtc_state->hw.active = true; 4225 4226 intel_crtc_readout_derived_state(crtc_state); 4227 4228 return true; 4229 } 4230 4231 /* VESA 640x480x72Hz mode to set on the pipe */ 4232 static const struct drm_display_mode load_detect_mode = { 4233 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, 4234 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 4235 }; 4236 4237 static int intel_modeset_disable_planes(struct drm_atomic_state *state, 4238 struct drm_crtc *crtc) 4239 { 4240 struct drm_plane *plane; 4241 struct drm_plane_state *plane_state; 4242 int ret, i; 4243 4244 ret = drm_atomic_add_affected_planes(state, crtc); 4245 if (ret) 4246 return ret; 4247 4248 for_each_new_plane_in_state(state, plane, plane_state, i) { 4249 if (plane_state->crtc != crtc) 4250 continue; 4251 4252 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL); 4253 if (ret) 4254 return ret; 4255 4256 drm_atomic_set_fb_for_plane(plane_state, NULL); 4257 } 4258 4259 return 0; 4260 } 4261 4262 int intel_get_load_detect_pipe(struct drm_connector *connector, 4263 struct intel_load_detect_pipe *old, 4264 struct drm_modeset_acquire_ctx *ctx) 4265 { 4266 struct intel_encoder *encoder = 4267 intel_attached_encoder(to_intel_connector(connector)); 4268 struct intel_crtc *possible_crtc; 4269 struct intel_crtc *crtc = NULL; 4270 struct drm_device *dev = encoder->base.dev; 4271 struct drm_i915_private *dev_priv = to_i915(dev); 4272 struct drm_mode_config *config = &dev->mode_config; 4273 struct drm_atomic_state *state = NULL, *restore_state = NULL; 4274 struct drm_connector_state *connector_state; 4275 struct intel_crtc_state *crtc_state; 4276 int ret; 4277 4278 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 4279 connector->base.id, connector->name, 4280 encoder->base.base.id, encoder->base.name); 4281 4282 old->restore_state = NULL; 4283 4284 drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex)); 4285 4286 /* 4287 * Algorithm gets a little messy: 4288 * 4289 * - if the connector already has an assigned crtc, use it (but make 4290 * sure it's on first) 4291 * 4292 * - try to find the first unused crtc that can drive this connector, 4293 * and use that if we find one 4294 */ 4295 4296 /* See if we already have a CRTC for this connector */ 4297 if (connector->state->crtc) { 4298 crtc = to_intel_crtc(connector->state->crtc); 4299 4300 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4301 if (ret) 4302 goto fail; 4303 4304 /* Make sure the crtc and connector are running */ 4305 goto found; 4306 } 4307 4308 /* Find an unused one (if possible) */ 4309 for_each_intel_crtc(dev, possible_crtc) { 4310 if (!(encoder->base.possible_crtcs & 4311 drm_crtc_mask(&possible_crtc->base))) 4312 continue; 4313 4314 ret = drm_modeset_lock(&possible_crtc->base.mutex, ctx); 4315 if (ret) 4316 goto fail; 4317 4318 if (possible_crtc->base.state->enable) { 4319 drm_modeset_unlock(&possible_crtc->base.mutex); 4320 continue; 4321 } 4322 4323 crtc = possible_crtc; 4324 break; 4325 } 4326 4327 /* 4328 * If we didn't find an unused CRTC, don't use any. 4329 */ 4330 if (!crtc) { 4331 drm_dbg_kms(&dev_priv->drm, 4332 "no pipe available for load-detect\n"); 4333 ret = -ENODEV; 4334 goto fail; 4335 } 4336 4337 found: 4338 state = drm_atomic_state_alloc(dev); 4339 restore_state = drm_atomic_state_alloc(dev); 4340 if (!state || !restore_state) { 4341 ret = -ENOMEM; 4342 goto fail; 4343 } 4344 4345 state->acquire_ctx = ctx; 4346 restore_state->acquire_ctx = ctx; 4347 4348 connector_state = drm_atomic_get_connector_state(state, connector); 4349 if (IS_ERR(connector_state)) { 4350 ret = PTR_ERR(connector_state); 4351 goto fail; 4352 } 4353 4354 ret = drm_atomic_set_crtc_for_connector(connector_state, &crtc->base); 4355 if (ret) 4356 goto fail; 4357 4358 crtc_state = intel_atomic_get_crtc_state(state, crtc); 4359 if (IS_ERR(crtc_state)) { 4360 ret = PTR_ERR(crtc_state); 4361 goto fail; 4362 } 4363 4364 crtc_state->uapi.active = true; 4365 4366 ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi, 4367 &load_detect_mode); 4368 if (ret) 4369 goto fail; 4370 4371 ret = intel_modeset_disable_planes(state, &crtc->base); 4372 if (ret) 4373 goto fail; 4374 4375 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); 4376 if (!ret) 4377 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, &crtc->base)); 4378 if (!ret) 4379 ret = drm_atomic_add_affected_planes(restore_state, &crtc->base); 4380 if (ret) { 4381 drm_dbg_kms(&dev_priv->drm, 4382 "Failed to create a copy of old state to restore: %i\n", 4383 ret); 4384 goto fail; 4385 } 4386 4387 ret = drm_atomic_commit(state); 4388 if (ret) { 4389 drm_dbg_kms(&dev_priv->drm, 4390 "failed to set mode on load-detect pipe\n"); 4391 goto fail; 4392 } 4393 4394 old->restore_state = restore_state; 4395 drm_atomic_state_put(state); 4396 4397 /* let the connector get through one full cycle before testing */ 4398 intel_crtc_wait_for_next_vblank(crtc); 4399 4400 return true; 4401 4402 fail: 4403 if (state) { 4404 drm_atomic_state_put(state); 4405 state = NULL; 4406 } 4407 if (restore_state) { 4408 drm_atomic_state_put(restore_state); 4409 restore_state = NULL; 4410 } 4411 4412 if (ret == -EDEADLK) 4413 return ret; 4414 4415 return false; 4416 } 4417 4418 void intel_release_load_detect_pipe(struct drm_connector *connector, 4419 struct intel_load_detect_pipe *old, 4420 struct drm_modeset_acquire_ctx *ctx) 4421 { 4422 struct intel_encoder *intel_encoder = 4423 intel_attached_encoder(to_intel_connector(connector)); 4424 struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev); 4425 struct drm_encoder *encoder = &intel_encoder->base; 4426 struct drm_atomic_state *state = old->restore_state; 4427 int ret; 4428 4429 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 4430 connector->base.id, connector->name, 4431 encoder->base.id, encoder->name); 4432 4433 if (!state) 4434 return; 4435 4436 ret = drm_atomic_helper_commit_duplicated_state(state, ctx); 4437 if (ret) 4438 drm_dbg_kms(&i915->drm, 4439 "Couldn't release load detect pipe: %i\n", ret); 4440 drm_atomic_state_put(state); 4441 } 4442 4443 static int i9xx_pll_refclk(struct drm_device *dev, 4444 const struct intel_crtc_state *pipe_config) 4445 { 4446 struct drm_i915_private *dev_priv = to_i915(dev); 4447 u32 dpll = pipe_config->dpll_hw_state.dpll; 4448 4449 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) 4450 return dev_priv->vbt.lvds_ssc_freq; 4451 else if (HAS_PCH_SPLIT(dev_priv)) 4452 return 120000; 4453 else if (DISPLAY_VER(dev_priv) != 2) 4454 return 96000; 4455 else 4456 return 48000; 4457 } 4458 4459 /* Returns the clock of the currently programmed mode of the given pipe. */ 4460 void i9xx_crtc_clock_get(struct intel_crtc *crtc, 4461 struct intel_crtc_state *pipe_config) 4462 { 4463 struct drm_device *dev = crtc->base.dev; 4464 struct drm_i915_private *dev_priv = to_i915(dev); 4465 u32 dpll = pipe_config->dpll_hw_state.dpll; 4466 u32 fp; 4467 struct dpll clock; 4468 int port_clock; 4469 int refclk = i9xx_pll_refclk(dev, pipe_config); 4470 4471 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 4472 fp = pipe_config->dpll_hw_state.fp0; 4473 else 4474 fp = pipe_config->dpll_hw_state.fp1; 4475 4476 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 4477 if (IS_PINEVIEW(dev_priv)) { 4478 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; 4479 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; 4480 } else { 4481 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 4482 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 4483 } 4484 4485 if (DISPLAY_VER(dev_priv) != 2) { 4486 if (IS_PINEVIEW(dev_priv)) 4487 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> 4488 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); 4489 else 4490 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> 4491 DPLL_FPA01_P1_POST_DIV_SHIFT); 4492 4493 switch (dpll & DPLL_MODE_MASK) { 4494 case DPLLB_MODE_DAC_SERIAL: 4495 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 4496 5 : 10; 4497 break; 4498 case DPLLB_MODE_LVDS: 4499 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 4500 7 : 14; 4501 break; 4502 default: 4503 drm_dbg_kms(&dev_priv->drm, 4504 "Unknown DPLL mode %08x in programmed " 4505 "mode\n", (int)(dpll & DPLL_MODE_MASK)); 4506 return; 4507 } 4508 4509 if (IS_PINEVIEW(dev_priv)) 4510 port_clock = pnv_calc_dpll_params(refclk, &clock); 4511 else 4512 port_clock = i9xx_calc_dpll_params(refclk, &clock); 4513 } else { 4514 enum pipe lvds_pipe; 4515 4516 if (IS_I85X(dev_priv) && 4517 intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) && 4518 lvds_pipe == crtc->pipe) { 4519 u32 lvds = intel_de_read(dev_priv, LVDS); 4520 4521 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 4522 DPLL_FPA01_P1_POST_DIV_SHIFT); 4523 4524 if (lvds & LVDS_CLKB_POWER_UP) 4525 clock.p2 = 7; 4526 else 4527 clock.p2 = 14; 4528 } else { 4529 if (dpll & PLL_P1_DIVIDE_BY_TWO) 4530 clock.p1 = 2; 4531 else { 4532 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 4533 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 4534 } 4535 if (dpll & PLL_P2_DIVIDE_BY_4) 4536 clock.p2 = 4; 4537 else 4538 clock.p2 = 2; 4539 } 4540 4541 port_clock = i9xx_calc_dpll_params(refclk, &clock); 4542 } 4543 4544 /* 4545 * This value includes pixel_multiplier. We will use 4546 * port_clock to compute adjusted_mode.crtc_clock in the 4547 * encoder's get_config() function. 4548 */ 4549 pipe_config->port_clock = port_clock; 4550 } 4551 4552 int intel_dotclock_calculate(int link_freq, 4553 const struct intel_link_m_n *m_n) 4554 { 4555 /* 4556 * The calculation for the data clock is: 4557 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp 4558 * But we want to avoid losing precison if possible, so: 4559 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) 4560 * 4561 * and the link clock is simpler: 4562 * link_clock = (m * link_clock) / n 4563 */ 4564 4565 if (!m_n->link_n) 4566 return 0; 4567 4568 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n); 4569 } 4570 4571 /* Returns the currently programmed mode of the given encoder. */ 4572 struct drm_display_mode * 4573 intel_encoder_current_mode(struct intel_encoder *encoder) 4574 { 4575 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4576 struct intel_crtc_state *crtc_state; 4577 struct drm_display_mode *mode; 4578 struct intel_crtc *crtc; 4579 enum pipe pipe; 4580 4581 if (!encoder->get_hw_state(encoder, &pipe)) 4582 return NULL; 4583 4584 crtc = intel_crtc_for_pipe(dev_priv, pipe); 4585 4586 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 4587 if (!mode) 4588 return NULL; 4589 4590 crtc_state = intel_crtc_state_alloc(crtc); 4591 if (!crtc_state) { 4592 kfree(mode); 4593 return NULL; 4594 } 4595 4596 if (!intel_crtc_get_pipe_config(crtc_state)) { 4597 kfree(crtc_state); 4598 kfree(mode); 4599 return NULL; 4600 } 4601 4602 intel_encoder_get_config(encoder, crtc_state); 4603 4604 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode); 4605 4606 kfree(crtc_state); 4607 4608 return mode; 4609 } 4610 4611 static bool encoders_cloneable(const struct intel_encoder *a, 4612 const struct intel_encoder *b) 4613 { 4614 /* masks could be asymmetric, so check both ways */ 4615 return a == b || (a->cloneable & (1 << b->type) && 4616 b->cloneable & (1 << a->type)); 4617 } 4618 4619 static bool check_single_encoder_cloning(struct intel_atomic_state *state, 4620 struct intel_crtc *crtc, 4621 struct intel_encoder *encoder) 4622 { 4623 struct intel_encoder *source_encoder; 4624 struct drm_connector *connector; 4625 struct drm_connector_state *connector_state; 4626 int i; 4627 4628 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4629 if (connector_state->crtc != &crtc->base) 4630 continue; 4631 4632 source_encoder = 4633 to_intel_encoder(connector_state->best_encoder); 4634 if (!encoders_cloneable(encoder, source_encoder)) 4635 return false; 4636 } 4637 4638 return true; 4639 } 4640 4641 static int icl_add_linked_planes(struct intel_atomic_state *state) 4642 { 4643 struct intel_plane *plane, *linked; 4644 struct intel_plane_state *plane_state, *linked_plane_state; 4645 int i; 4646 4647 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4648 linked = plane_state->planar_linked_plane; 4649 4650 if (!linked) 4651 continue; 4652 4653 linked_plane_state = intel_atomic_get_plane_state(state, linked); 4654 if (IS_ERR(linked_plane_state)) 4655 return PTR_ERR(linked_plane_state); 4656 4657 drm_WARN_ON(state->base.dev, 4658 linked_plane_state->planar_linked_plane != plane); 4659 drm_WARN_ON(state->base.dev, 4660 linked_plane_state->planar_slave == plane_state->planar_slave); 4661 } 4662 4663 return 0; 4664 } 4665 4666 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state) 4667 { 4668 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4669 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4670 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 4671 struct intel_plane *plane, *linked; 4672 struct intel_plane_state *plane_state; 4673 int i; 4674 4675 if (DISPLAY_VER(dev_priv) < 11) 4676 return 0; 4677 4678 /* 4679 * Destroy all old plane links and make the slave plane invisible 4680 * in the crtc_state->active_planes mask. 4681 */ 4682 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4683 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane) 4684 continue; 4685 4686 plane_state->planar_linked_plane = NULL; 4687 if (plane_state->planar_slave && !plane_state->uapi.visible) { 4688 crtc_state->enabled_planes &= ~BIT(plane->id); 4689 crtc_state->active_planes &= ~BIT(plane->id); 4690 crtc_state->update_planes |= BIT(plane->id); 4691 crtc_state->data_rate[plane->id] = 0; 4692 crtc_state->rel_data_rate[plane->id] = 0; 4693 } 4694 4695 plane_state->planar_slave = false; 4696 } 4697 4698 if (!crtc_state->nv12_planes) 4699 return 0; 4700 4701 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4702 struct intel_plane_state *linked_state = NULL; 4703 4704 if (plane->pipe != crtc->pipe || 4705 !(crtc_state->nv12_planes & BIT(plane->id))) 4706 continue; 4707 4708 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) { 4709 if (!icl_is_nv12_y_plane(dev_priv, linked->id)) 4710 continue; 4711 4712 if (crtc_state->active_planes & BIT(linked->id)) 4713 continue; 4714 4715 linked_state = intel_atomic_get_plane_state(state, linked); 4716 if (IS_ERR(linked_state)) 4717 return PTR_ERR(linked_state); 4718 4719 break; 4720 } 4721 4722 if (!linked_state) { 4723 drm_dbg_kms(&dev_priv->drm, 4724 "Need %d free Y planes for planar YUV\n", 4725 hweight8(crtc_state->nv12_planes)); 4726 4727 return -EINVAL; 4728 } 4729 4730 plane_state->planar_linked_plane = linked; 4731 4732 linked_state->planar_slave = true; 4733 linked_state->planar_linked_plane = plane; 4734 crtc_state->enabled_planes |= BIT(linked->id); 4735 crtc_state->active_planes |= BIT(linked->id); 4736 crtc_state->update_planes |= BIT(linked->id); 4737 crtc_state->data_rate[linked->id] = 4738 crtc_state->data_rate_y[plane->id]; 4739 crtc_state->rel_data_rate[linked->id] = 4740 crtc_state->rel_data_rate_y[plane->id]; 4741 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n", 4742 linked->base.name, plane->base.name); 4743 4744 /* Copy parameters to slave plane */ 4745 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE; 4746 linked_state->color_ctl = plane_state->color_ctl; 4747 linked_state->view = plane_state->view; 4748 linked_state->decrypt = plane_state->decrypt; 4749 4750 intel_plane_copy_hw_state(linked_state, plane_state); 4751 linked_state->uapi.src = plane_state->uapi.src; 4752 linked_state->uapi.dst = plane_state->uapi.dst; 4753 4754 if (icl_is_hdr_plane(dev_priv, plane->id)) { 4755 if (linked->id == PLANE_SPRITE5) 4756 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL; 4757 else if (linked->id == PLANE_SPRITE4) 4758 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL; 4759 else if (linked->id == PLANE_SPRITE3) 4760 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL; 4761 else if (linked->id == PLANE_SPRITE2) 4762 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL; 4763 else 4764 MISSING_CASE(linked->id); 4765 } 4766 } 4767 4768 return 0; 4769 } 4770 4771 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state) 4772 { 4773 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 4774 struct intel_atomic_state *state = 4775 to_intel_atomic_state(new_crtc_state->uapi.state); 4776 const struct intel_crtc_state *old_crtc_state = 4777 intel_atomic_get_old_crtc_state(state, crtc); 4778 4779 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes; 4780 } 4781 4782 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) 4783 { 4784 const struct drm_display_mode *pipe_mode = 4785 &crtc_state->hw.pipe_mode; 4786 int linetime_wm; 4787 4788 if (!crtc_state->hw.enable) 4789 return 0; 4790 4791 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4792 pipe_mode->crtc_clock); 4793 4794 return min(linetime_wm, 0x1ff); 4795 } 4796 4797 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, 4798 const struct intel_cdclk_state *cdclk_state) 4799 { 4800 const struct drm_display_mode *pipe_mode = 4801 &crtc_state->hw.pipe_mode; 4802 int linetime_wm; 4803 4804 if (!crtc_state->hw.enable) 4805 return 0; 4806 4807 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4808 cdclk_state->logical.cdclk); 4809 4810 return min(linetime_wm, 0x1ff); 4811 } 4812 4813 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) 4814 { 4815 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4816 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4817 const struct drm_display_mode *pipe_mode = 4818 &crtc_state->hw.pipe_mode; 4819 int linetime_wm; 4820 4821 if (!crtc_state->hw.enable) 4822 return 0; 4823 4824 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8, 4825 crtc_state->pixel_rate); 4826 4827 /* Display WA #1135: BXT:ALL GLK:ALL */ 4828 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 4829 dev_priv->ipc_enabled) 4830 linetime_wm /= 2; 4831 4832 return min(linetime_wm, 0x1ff); 4833 } 4834 4835 static int hsw_compute_linetime_wm(struct intel_atomic_state *state, 4836 struct intel_crtc *crtc) 4837 { 4838 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4839 struct intel_crtc_state *crtc_state = 4840 intel_atomic_get_new_crtc_state(state, crtc); 4841 const struct intel_cdclk_state *cdclk_state; 4842 4843 if (DISPLAY_VER(dev_priv) >= 9) 4844 crtc_state->linetime = skl_linetime_wm(crtc_state); 4845 else 4846 crtc_state->linetime = hsw_linetime_wm(crtc_state); 4847 4848 if (!hsw_crtc_supports_ips(crtc)) 4849 return 0; 4850 4851 cdclk_state = intel_atomic_get_cdclk_state(state); 4852 if (IS_ERR(cdclk_state)) 4853 return PTR_ERR(cdclk_state); 4854 4855 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state, 4856 cdclk_state); 4857 4858 return 0; 4859 } 4860 4861 static int intel_crtc_atomic_check(struct intel_atomic_state *state, 4862 struct intel_crtc *crtc) 4863 { 4864 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4865 struct intel_crtc_state *crtc_state = 4866 intel_atomic_get_new_crtc_state(state, crtc); 4867 bool mode_changed = intel_crtc_needs_modeset(crtc_state); 4868 int ret; 4869 4870 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) && 4871 mode_changed && !crtc_state->hw.active) 4872 crtc_state->update_wm_post = true; 4873 4874 if (mode_changed) { 4875 ret = intel_dpll_crtc_compute_clock(state, crtc); 4876 if (ret) 4877 return ret; 4878 4879 ret = intel_dpll_crtc_get_shared_dpll(state, crtc); 4880 if (ret) 4881 return ret; 4882 } 4883 4884 /* 4885 * May need to update pipe gamma enable bits 4886 * when C8 planes are getting enabled/disabled. 4887 */ 4888 if (c8_planes_changed(crtc_state)) 4889 crtc_state->uapi.color_mgmt_changed = true; 4890 4891 if (mode_changed || crtc_state->update_pipe || 4892 crtc_state->uapi.color_mgmt_changed) { 4893 ret = intel_color_check(crtc_state); 4894 if (ret) 4895 return ret; 4896 } 4897 4898 ret = intel_compute_pipe_wm(state, crtc); 4899 if (ret) { 4900 drm_dbg_kms(&dev_priv->drm, 4901 "Target pipe watermarks are invalid\n"); 4902 return ret; 4903 } 4904 4905 /* 4906 * Calculate 'intermediate' watermarks that satisfy both the 4907 * old state and the new state. We can program these 4908 * immediately. 4909 */ 4910 ret = intel_compute_intermediate_wm(state, crtc); 4911 if (ret) { 4912 drm_dbg_kms(&dev_priv->drm, 4913 "No valid intermediate pipe watermarks are possible\n"); 4914 return ret; 4915 } 4916 4917 if (DISPLAY_VER(dev_priv) >= 9) { 4918 if (mode_changed || crtc_state->update_pipe) { 4919 ret = skl_update_scaler_crtc(crtc_state); 4920 if (ret) 4921 return ret; 4922 } 4923 4924 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state); 4925 if (ret) 4926 return ret; 4927 } 4928 4929 if (HAS_IPS(dev_priv)) { 4930 ret = hsw_ips_compute_config(state, crtc); 4931 if (ret) 4932 return ret; 4933 } 4934 4935 if (DISPLAY_VER(dev_priv) >= 9 || 4936 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 4937 ret = hsw_compute_linetime_wm(state, crtc); 4938 if (ret) 4939 return ret; 4940 4941 } 4942 4943 ret = intel_psr2_sel_fetch_update(state, crtc); 4944 if (ret) 4945 return ret; 4946 4947 return 0; 4948 } 4949 4950 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) 4951 { 4952 struct intel_connector *connector; 4953 struct drm_connector_list_iter conn_iter; 4954 4955 drm_connector_list_iter_begin(dev, &conn_iter); 4956 for_each_intel_connector_iter(connector, &conn_iter) { 4957 struct drm_connector_state *conn_state = connector->base.state; 4958 struct intel_encoder *encoder = 4959 to_intel_encoder(connector->base.encoder); 4960 4961 if (conn_state->crtc) 4962 drm_connector_put(&connector->base); 4963 4964 if (encoder) { 4965 struct intel_crtc *crtc = 4966 to_intel_crtc(encoder->base.crtc); 4967 const struct intel_crtc_state *crtc_state = 4968 to_intel_crtc_state(crtc->base.state); 4969 4970 conn_state->best_encoder = &encoder->base; 4971 conn_state->crtc = &crtc->base; 4972 conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3; 4973 4974 drm_connector_get(&connector->base); 4975 } else { 4976 conn_state->best_encoder = NULL; 4977 conn_state->crtc = NULL; 4978 } 4979 } 4980 drm_connector_list_iter_end(&conn_iter); 4981 } 4982 4983 static int 4984 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state, 4985 struct intel_crtc_state *crtc_state) 4986 { 4987 struct drm_connector *connector = conn_state->connector; 4988 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 4989 const struct drm_display_info *info = &connector->display_info; 4990 int bpp; 4991 4992 switch (conn_state->max_bpc) { 4993 case 6 ... 7: 4994 bpp = 6 * 3; 4995 break; 4996 case 8 ... 9: 4997 bpp = 8 * 3; 4998 break; 4999 case 10 ... 11: 5000 bpp = 10 * 3; 5001 break; 5002 case 12 ... 16: 5003 bpp = 12 * 3; 5004 break; 5005 default: 5006 MISSING_CASE(conn_state->max_bpc); 5007 return -EINVAL; 5008 } 5009 5010 if (bpp < crtc_state->pipe_bpp) { 5011 drm_dbg_kms(&i915->drm, 5012 "[CONNECTOR:%d:%s] Limiting display bpp to %d " 5013 "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n", 5014 connector->base.id, connector->name, 5015 bpp, 3 * info->bpc, 5016 3 * conn_state->max_requested_bpc, 5017 crtc_state->pipe_bpp); 5018 5019 crtc_state->pipe_bpp = bpp; 5020 } 5021 5022 return 0; 5023 } 5024 5025 static int 5026 compute_baseline_pipe_bpp(struct intel_atomic_state *state, 5027 struct intel_crtc *crtc) 5028 { 5029 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5030 struct intel_crtc_state *crtc_state = 5031 intel_atomic_get_new_crtc_state(state, crtc); 5032 struct drm_connector *connector; 5033 struct drm_connector_state *connector_state; 5034 int bpp, i; 5035 5036 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 5037 IS_CHERRYVIEW(dev_priv))) 5038 bpp = 10*3; 5039 else if (DISPLAY_VER(dev_priv) >= 5) 5040 bpp = 12*3; 5041 else 5042 bpp = 8*3; 5043 5044 crtc_state->pipe_bpp = bpp; 5045 5046 /* Clamp display bpp to connector max bpp */ 5047 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5048 int ret; 5049 5050 if (connector_state->crtc != &crtc->base) 5051 continue; 5052 5053 ret = compute_sink_pipe_bpp(connector_state, crtc_state); 5054 if (ret) 5055 return ret; 5056 } 5057 5058 return 0; 5059 } 5060 5061 static void intel_dump_crtc_timings(struct drm_i915_private *i915, 5062 const struct drm_display_mode *mode) 5063 { 5064 drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, " 5065 "type: 0x%x flags: 0x%x\n", 5066 mode->crtc_clock, 5067 mode->crtc_hdisplay, mode->crtc_hsync_start, 5068 mode->crtc_hsync_end, mode->crtc_htotal, 5069 mode->crtc_vdisplay, mode->crtc_vsync_start, 5070 mode->crtc_vsync_end, mode->crtc_vtotal, 5071 mode->type, mode->flags); 5072 } 5073 5074 static void 5075 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config, 5076 const char *id, unsigned int lane_count, 5077 const struct intel_link_m_n *m_n) 5078 { 5079 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); 5080 5081 drm_dbg_kms(&i915->drm, 5082 "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n", 5083 id, lane_count, 5084 m_n->data_m, m_n->data_n, 5085 m_n->link_m, m_n->link_n, m_n->tu); 5086 } 5087 5088 static void 5089 intel_dump_infoframe(struct drm_i915_private *dev_priv, 5090 const union hdmi_infoframe *frame) 5091 { 5092 if (!drm_debug_enabled(DRM_UT_KMS)) 5093 return; 5094 5095 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame); 5096 } 5097 5098 static void 5099 intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv, 5100 const struct drm_dp_vsc_sdp *vsc) 5101 { 5102 if (!drm_debug_enabled(DRM_UT_KMS)) 5103 return; 5104 5105 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc); 5106 } 5107 5108 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x 5109 5110 static const char * const output_type_str[] = { 5111 OUTPUT_TYPE(UNUSED), 5112 OUTPUT_TYPE(ANALOG), 5113 OUTPUT_TYPE(DVO), 5114 OUTPUT_TYPE(SDVO), 5115 OUTPUT_TYPE(LVDS), 5116 OUTPUT_TYPE(TVOUT), 5117 OUTPUT_TYPE(HDMI), 5118 OUTPUT_TYPE(DP), 5119 OUTPUT_TYPE(EDP), 5120 OUTPUT_TYPE(DSI), 5121 OUTPUT_TYPE(DDI), 5122 OUTPUT_TYPE(DP_MST), 5123 }; 5124 5125 #undef OUTPUT_TYPE 5126 5127 static void snprintf_output_types(char *buf, size_t len, 5128 unsigned int output_types) 5129 { 5130 char *str = buf; 5131 int i; 5132 5133 str[0] = '\0'; 5134 5135 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) { 5136 int r; 5137 5138 if ((output_types & BIT(i)) == 0) 5139 continue; 5140 5141 r = snprintf(str, len, "%s%s", 5142 str != buf ? "," : "", output_type_str[i]); 5143 if (r >= len) 5144 break; 5145 str += r; 5146 len -= r; 5147 5148 output_types &= ~BIT(i); 5149 } 5150 5151 WARN_ON_ONCE(output_types != 0); 5152 } 5153 5154 static const char * const output_format_str[] = { 5155 [INTEL_OUTPUT_FORMAT_RGB] = "RGB", 5156 [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0", 5157 [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4", 5158 }; 5159 5160 static const char *output_formats(enum intel_output_format format) 5161 { 5162 if (format >= ARRAY_SIZE(output_format_str)) 5163 return "invalid"; 5164 return output_format_str[format]; 5165 } 5166 5167 static void intel_dump_plane_state(const struct intel_plane_state *plane_state) 5168 { 5169 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 5170 struct drm_i915_private *i915 = to_i915(plane->base.dev); 5171 const struct drm_framebuffer *fb = plane_state->hw.fb; 5172 5173 if (!fb) { 5174 drm_dbg_kms(&i915->drm, 5175 "[PLANE:%d:%s] fb: [NOFB], visible: %s\n", 5176 plane->base.base.id, plane->base.name, 5177 str_yes_no(plane_state->uapi.visible)); 5178 return; 5179 } 5180 5181 drm_dbg_kms(&i915->drm, 5182 "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %p4cc modifier = 0x%llx, visible: %s\n", 5183 plane->base.base.id, plane->base.name, 5184 fb->base.id, fb->width, fb->height, &fb->format->format, 5185 fb->modifier, str_yes_no(plane_state->uapi.visible)); 5186 drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n", 5187 plane_state->hw.rotation, plane_state->scaler_id); 5188 if (plane_state->uapi.visible) 5189 drm_dbg_kms(&i915->drm, 5190 "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n", 5191 DRM_RECT_FP_ARG(&plane_state->uapi.src), 5192 DRM_RECT_ARG(&plane_state->uapi.dst)); 5193 } 5194 5195 void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, 5196 struct intel_atomic_state *state, 5197 const char *context) 5198 { 5199 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 5200 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5201 const struct intel_plane_state *plane_state; 5202 struct intel_plane *plane; 5203 char buf[64]; 5204 int i; 5205 5206 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n", 5207 crtc->base.base.id, crtc->base.name, 5208 str_yes_no(pipe_config->hw.enable), context); 5209 5210 if (!pipe_config->hw.enable) 5211 goto dump_planes; 5212 5213 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types); 5214 drm_dbg_kms(&dev_priv->drm, 5215 "active: %s, output_types: %s (0x%x), output format: %s\n", 5216 str_yes_no(pipe_config->hw.active), 5217 buf, pipe_config->output_types, 5218 output_formats(pipe_config->output_format)); 5219 5220 drm_dbg_kms(&dev_priv->drm, 5221 "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", 5222 transcoder_name(pipe_config->cpu_transcoder), 5223 pipe_config->pipe_bpp, pipe_config->dither); 5224 5225 drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n", 5226 transcoder_name(pipe_config->mst_master_transcoder)); 5227 5228 drm_dbg_kms(&dev_priv->drm, 5229 "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n", 5230 transcoder_name(pipe_config->master_transcoder), 5231 pipe_config->sync_mode_slaves_mask); 5232 5233 drm_dbg_kms(&dev_priv->drm, "bigjoiner: %s, pipes: 0x%x\n", 5234 intel_crtc_is_bigjoiner_slave(pipe_config) ? "slave" : 5235 intel_crtc_is_bigjoiner_master(pipe_config) ? "master" : "no", 5236 pipe_config->bigjoiner_pipes); 5237 5238 drm_dbg_kms(&dev_priv->drm, "splitter: %s, link count %d, overlap %d\n", 5239 str_enabled_disabled(pipe_config->splitter.enable), 5240 pipe_config->splitter.link_count, 5241 pipe_config->splitter.pixel_overlap); 5242 5243 if (pipe_config->has_pch_encoder) 5244 intel_dump_m_n_config(pipe_config, "fdi", 5245 pipe_config->fdi_lanes, 5246 &pipe_config->fdi_m_n); 5247 5248 if (intel_crtc_has_dp_encoder(pipe_config)) { 5249 intel_dump_m_n_config(pipe_config, "dp m_n", 5250 pipe_config->lane_count, 5251 &pipe_config->dp_m_n); 5252 intel_dump_m_n_config(pipe_config, "dp m2_n2", 5253 pipe_config->lane_count, 5254 &pipe_config->dp_m2_n2); 5255 } 5256 5257 drm_dbg_kms(&dev_priv->drm, "framestart delay: %d, MSA timing delay: %d\n", 5258 pipe_config->framestart_delay, pipe_config->msa_timing_delay); 5259 5260 drm_dbg_kms(&dev_priv->drm, 5261 "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n", 5262 pipe_config->has_audio, pipe_config->has_infoframe, 5263 pipe_config->infoframes.enable); 5264 5265 if (pipe_config->infoframes.enable & 5266 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) 5267 drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n", 5268 pipe_config->infoframes.gcp); 5269 if (pipe_config->infoframes.enable & 5270 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) 5271 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi); 5272 if (pipe_config->infoframes.enable & 5273 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD)) 5274 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd); 5275 if (pipe_config->infoframes.enable & 5276 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR)) 5277 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi); 5278 if (pipe_config->infoframes.enable & 5279 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) 5280 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); 5281 if (pipe_config->infoframes.enable & 5282 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA)) 5283 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); 5284 if (pipe_config->infoframes.enable & 5285 intel_hdmi_infoframe_enable(DP_SDP_VSC)) 5286 intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc); 5287 5288 drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n", 5289 str_yes_no(pipe_config->vrr.enable), 5290 pipe_config->vrr.vmin, pipe_config->vrr.vmax, 5291 pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband, 5292 pipe_config->vrr.flipline, 5293 intel_vrr_vmin_vblank_start(pipe_config), 5294 intel_vrr_vmax_vblank_start(pipe_config)); 5295 5296 drm_dbg_kms(&dev_priv->drm, "requested mode: " DRM_MODE_FMT "\n", 5297 DRM_MODE_ARG(&pipe_config->hw.mode)); 5298 drm_dbg_kms(&dev_priv->drm, "adjusted mode: " DRM_MODE_FMT "\n", 5299 DRM_MODE_ARG(&pipe_config->hw.adjusted_mode)); 5300 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode); 5301 drm_dbg_kms(&dev_priv->drm, "pipe mode: " DRM_MODE_FMT "\n", 5302 DRM_MODE_ARG(&pipe_config->hw.pipe_mode)); 5303 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode); 5304 drm_dbg_kms(&dev_priv->drm, 5305 "port clock: %d, pipe src: " DRM_RECT_FMT ", pixel rate %d\n", 5306 pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src), 5307 pipe_config->pixel_rate); 5308 5309 drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n", 5310 pipe_config->linetime, pipe_config->ips_linetime); 5311 5312 if (DISPLAY_VER(dev_priv) >= 9) 5313 drm_dbg_kms(&dev_priv->drm, 5314 "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", 5315 crtc->num_scalers, 5316 pipe_config->scaler_state.scaler_users, 5317 pipe_config->scaler_state.scaler_id); 5318 5319 if (HAS_GMCH(dev_priv)) 5320 drm_dbg_kms(&dev_priv->drm, 5321 "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", 5322 pipe_config->gmch_pfit.control, 5323 pipe_config->gmch_pfit.pgm_ratios, 5324 pipe_config->gmch_pfit.lvds_border_bits); 5325 else 5326 drm_dbg_kms(&dev_priv->drm, 5327 "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n", 5328 DRM_RECT_ARG(&pipe_config->pch_pfit.dst), 5329 str_enabled_disabled(pipe_config->pch_pfit.enabled), 5330 str_yes_no(pipe_config->pch_pfit.force_thru)); 5331 5332 drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i, drrs: %i\n", 5333 pipe_config->ips_enabled, pipe_config->double_wide, 5334 pipe_config->has_drrs); 5335 5336 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state); 5337 5338 if (IS_CHERRYVIEW(dev_priv)) 5339 drm_dbg_kms(&dev_priv->drm, 5340 "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", 5341 pipe_config->cgm_mode, pipe_config->gamma_mode, 5342 pipe_config->gamma_enable, pipe_config->csc_enable); 5343 else 5344 drm_dbg_kms(&dev_priv->drm, 5345 "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", 5346 pipe_config->csc_mode, pipe_config->gamma_mode, 5347 pipe_config->gamma_enable, pipe_config->csc_enable); 5348 5349 drm_dbg_kms(&dev_priv->drm, "degamma lut: %d entries, gamma lut: %d entries\n", 5350 pipe_config->hw.degamma_lut ? 5351 drm_color_lut_size(pipe_config->hw.degamma_lut) : 0, 5352 pipe_config->hw.gamma_lut ? 5353 drm_color_lut_size(pipe_config->hw.gamma_lut) : 0); 5354 5355 dump_planes: 5356 if (!state) 5357 return; 5358 5359 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 5360 if (plane->pipe == crtc->pipe) 5361 intel_dump_plane_state(plane_state); 5362 } 5363 } 5364 5365 static bool check_digital_port_conflicts(struct intel_atomic_state *state) 5366 { 5367 struct drm_device *dev = state->base.dev; 5368 struct drm_connector *connector; 5369 struct drm_connector_list_iter conn_iter; 5370 unsigned int used_ports = 0; 5371 unsigned int used_mst_ports = 0; 5372 bool ret = true; 5373 5374 /* 5375 * We're going to peek into connector->state, 5376 * hence connection_mutex must be held. 5377 */ 5378 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex); 5379 5380 /* 5381 * Walk the connector list instead of the encoder 5382 * list to detect the problem on ddi platforms 5383 * where there's just one encoder per digital port. 5384 */ 5385 drm_connector_list_iter_begin(dev, &conn_iter); 5386 drm_for_each_connector_iter(connector, &conn_iter) { 5387 struct drm_connector_state *connector_state; 5388 struct intel_encoder *encoder; 5389 5390 connector_state = 5391 drm_atomic_get_new_connector_state(&state->base, 5392 connector); 5393 if (!connector_state) 5394 connector_state = connector->state; 5395 5396 if (!connector_state->best_encoder) 5397 continue; 5398 5399 encoder = to_intel_encoder(connector_state->best_encoder); 5400 5401 drm_WARN_ON(dev, !connector_state->crtc); 5402 5403 switch (encoder->type) { 5404 case INTEL_OUTPUT_DDI: 5405 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev)))) 5406 break; 5407 fallthrough; 5408 case INTEL_OUTPUT_DP: 5409 case INTEL_OUTPUT_HDMI: 5410 case INTEL_OUTPUT_EDP: 5411 /* the same port mustn't appear more than once */ 5412 if (used_ports & BIT(encoder->port)) 5413 ret = false; 5414 5415 used_ports |= BIT(encoder->port); 5416 break; 5417 case INTEL_OUTPUT_DP_MST: 5418 used_mst_ports |= 5419 1 << encoder->port; 5420 break; 5421 default: 5422 break; 5423 } 5424 } 5425 drm_connector_list_iter_end(&conn_iter); 5426 5427 /* can't mix MST and SST/HDMI on the same port */ 5428 if (used_ports & used_mst_ports) 5429 return false; 5430 5431 return ret; 5432 } 5433 5434 static void 5435 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state, 5436 struct intel_crtc *crtc) 5437 { 5438 struct intel_crtc_state *crtc_state = 5439 intel_atomic_get_new_crtc_state(state, crtc); 5440 5441 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 5442 5443 drm_property_replace_blob(&crtc_state->hw.degamma_lut, 5444 crtc_state->uapi.degamma_lut); 5445 drm_property_replace_blob(&crtc_state->hw.gamma_lut, 5446 crtc_state->uapi.gamma_lut); 5447 drm_property_replace_blob(&crtc_state->hw.ctm, 5448 crtc_state->uapi.ctm); 5449 } 5450 5451 static void 5452 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state, 5453 struct intel_crtc *crtc) 5454 { 5455 struct intel_crtc_state *crtc_state = 5456 intel_atomic_get_new_crtc_state(state, crtc); 5457 5458 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 5459 5460 crtc_state->hw.enable = crtc_state->uapi.enable; 5461 crtc_state->hw.active = crtc_state->uapi.active; 5462 drm_mode_copy(&crtc_state->hw.mode, 5463 &crtc_state->uapi.mode); 5464 drm_mode_copy(&crtc_state->hw.adjusted_mode, 5465 &crtc_state->uapi.adjusted_mode); 5466 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter; 5467 5468 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 5469 } 5470 5471 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state) 5472 { 5473 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 5474 return; 5475 5476 crtc_state->uapi.enable = crtc_state->hw.enable; 5477 crtc_state->uapi.active = crtc_state->hw.active; 5478 drm_WARN_ON(crtc_state->uapi.crtc->dev, 5479 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0); 5480 5481 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode; 5482 crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter; 5483 5484 drm_property_replace_blob(&crtc_state->uapi.degamma_lut, 5485 crtc_state->hw.degamma_lut); 5486 drm_property_replace_blob(&crtc_state->uapi.gamma_lut, 5487 crtc_state->hw.gamma_lut); 5488 drm_property_replace_blob(&crtc_state->uapi.ctm, 5489 crtc_state->hw.ctm); 5490 } 5491 5492 static void 5493 copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state, 5494 struct intel_crtc *slave_crtc) 5495 { 5496 struct intel_crtc_state *slave_crtc_state = 5497 intel_atomic_get_new_crtc_state(state, slave_crtc); 5498 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 5499 const struct intel_crtc_state *master_crtc_state = 5500 intel_atomic_get_new_crtc_state(state, master_crtc); 5501 5502 drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut, 5503 master_crtc_state->hw.degamma_lut); 5504 drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut, 5505 master_crtc_state->hw.gamma_lut); 5506 drm_property_replace_blob(&slave_crtc_state->hw.ctm, 5507 master_crtc_state->hw.ctm); 5508 5509 slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed; 5510 } 5511 5512 static int 5513 copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state, 5514 struct intel_crtc *slave_crtc) 5515 { 5516 struct intel_crtc_state *slave_crtc_state = 5517 intel_atomic_get_new_crtc_state(state, slave_crtc); 5518 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 5519 const struct intel_crtc_state *master_crtc_state = 5520 intel_atomic_get_new_crtc_state(state, master_crtc); 5521 struct intel_crtc_state *saved_state; 5522 5523 WARN_ON(master_crtc_state->bigjoiner_pipes != 5524 slave_crtc_state->bigjoiner_pipes); 5525 5526 saved_state = kmemdup(master_crtc_state, sizeof(*saved_state), GFP_KERNEL); 5527 if (!saved_state) 5528 return -ENOMEM; 5529 5530 /* preserve some things from the slave's original crtc state */ 5531 saved_state->uapi = slave_crtc_state->uapi; 5532 saved_state->scaler_state = slave_crtc_state->scaler_state; 5533 saved_state->shared_dpll = slave_crtc_state->shared_dpll; 5534 saved_state->dpll_hw_state = slave_crtc_state->dpll_hw_state; 5535 saved_state->crc_enabled = slave_crtc_state->crc_enabled; 5536 5537 intel_crtc_free_hw_state(slave_crtc_state); 5538 memcpy(slave_crtc_state, saved_state, sizeof(*slave_crtc_state)); 5539 kfree(saved_state); 5540 5541 /* Re-init hw state */ 5542 memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw)); 5543 slave_crtc_state->hw.enable = master_crtc_state->hw.enable; 5544 slave_crtc_state->hw.active = master_crtc_state->hw.active; 5545 drm_mode_copy(&slave_crtc_state->hw.mode, 5546 &master_crtc_state->hw.mode); 5547 drm_mode_copy(&slave_crtc_state->hw.pipe_mode, 5548 &master_crtc_state->hw.pipe_mode); 5549 drm_mode_copy(&slave_crtc_state->hw.adjusted_mode, 5550 &master_crtc_state->hw.adjusted_mode); 5551 slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter; 5552 5553 copy_bigjoiner_crtc_state_nomodeset(state, slave_crtc); 5554 5555 slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed; 5556 slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed; 5557 slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed; 5558 5559 WARN_ON(master_crtc_state->bigjoiner_pipes != 5560 slave_crtc_state->bigjoiner_pipes); 5561 5562 return 0; 5563 } 5564 5565 static int 5566 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state, 5567 struct intel_crtc *crtc) 5568 { 5569 struct intel_crtc_state *crtc_state = 5570 intel_atomic_get_new_crtc_state(state, crtc); 5571 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5572 struct intel_crtc_state *saved_state; 5573 5574 saved_state = intel_crtc_state_alloc(crtc); 5575 if (!saved_state) 5576 return -ENOMEM; 5577 5578 /* free the old crtc_state->hw members */ 5579 intel_crtc_free_hw_state(crtc_state); 5580 5581 /* FIXME: before the switch to atomic started, a new pipe_config was 5582 * kzalloc'd. Code that depends on any field being zero should be 5583 * fixed, so that the crtc_state can be safely duplicated. For now, 5584 * only fields that are know to not cause problems are preserved. */ 5585 5586 saved_state->uapi = crtc_state->uapi; 5587 saved_state->scaler_state = crtc_state->scaler_state; 5588 saved_state->shared_dpll = crtc_state->shared_dpll; 5589 saved_state->dpll_hw_state = crtc_state->dpll_hw_state; 5590 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, 5591 sizeof(saved_state->icl_port_dplls)); 5592 saved_state->crc_enabled = crtc_state->crc_enabled; 5593 if (IS_G4X(dev_priv) || 5594 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5595 saved_state->wm = crtc_state->wm; 5596 5597 memcpy(crtc_state, saved_state, sizeof(*crtc_state)); 5598 kfree(saved_state); 5599 5600 intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc); 5601 5602 return 0; 5603 } 5604 5605 static int 5606 intel_modeset_pipe_config(struct intel_atomic_state *state, 5607 struct intel_crtc *crtc) 5608 { 5609 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 5610 struct intel_crtc_state *crtc_state = 5611 intel_atomic_get_new_crtc_state(state, crtc); 5612 struct drm_connector *connector; 5613 struct drm_connector_state *connector_state; 5614 int pipe_src_w, pipe_src_h; 5615 int base_bpp, ret, i; 5616 bool retry = true; 5617 5618 crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe; 5619 5620 crtc_state->framestart_delay = 1; 5621 5622 /* 5623 * Sanitize sync polarity flags based on requested ones. If neither 5624 * positive or negative polarity is requested, treat this as meaning 5625 * negative polarity. 5626 */ 5627 if (!(crtc_state->hw.adjusted_mode.flags & 5628 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) 5629 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; 5630 5631 if (!(crtc_state->hw.adjusted_mode.flags & 5632 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 5633 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; 5634 5635 ret = compute_baseline_pipe_bpp(state, crtc); 5636 if (ret) 5637 return ret; 5638 5639 base_bpp = crtc_state->pipe_bpp; 5640 5641 /* 5642 * Determine the real pipe dimensions. Note that stereo modes can 5643 * increase the actual pipe size due to the frame doubling and 5644 * insertion of additional space for blanks between the frame. This 5645 * is stored in the crtc timings. We use the requested mode to do this 5646 * computation to clearly distinguish it from the adjusted mode, which 5647 * can be changed by the connectors in the below retry loop. 5648 */ 5649 drm_mode_get_hv_timing(&crtc_state->hw.mode, 5650 &pipe_src_w, &pipe_src_h); 5651 drm_rect_init(&crtc_state->pipe_src, 0, 0, 5652 pipe_src_w, pipe_src_h); 5653 5654 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5655 struct intel_encoder *encoder = 5656 to_intel_encoder(connector_state->best_encoder); 5657 5658 if (connector_state->crtc != &crtc->base) 5659 continue; 5660 5661 if (!check_single_encoder_cloning(state, crtc, encoder)) { 5662 drm_dbg_kms(&i915->drm, 5663 "[ENCODER:%d:%s] rejecting invalid cloning configuration\n", 5664 encoder->base.base.id, encoder->base.name); 5665 return -EINVAL; 5666 } 5667 5668 /* 5669 * Determine output_types before calling the .compute_config() 5670 * hooks so that the hooks can use this information safely. 5671 */ 5672 if (encoder->compute_output_type) 5673 crtc_state->output_types |= 5674 BIT(encoder->compute_output_type(encoder, crtc_state, 5675 connector_state)); 5676 else 5677 crtc_state->output_types |= BIT(encoder->type); 5678 } 5679 5680 encoder_retry: 5681 /* Ensure the port clock defaults are reset when retrying. */ 5682 crtc_state->port_clock = 0; 5683 crtc_state->pixel_multiplier = 1; 5684 5685 /* Fill in default crtc timings, allow encoders to overwrite them. */ 5686 drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode, 5687 CRTC_STEREO_DOUBLE); 5688 5689 /* Pass our mode to the connectors and the CRTC to give them a chance to 5690 * adjust it according to limitations or connector properties, and also 5691 * a chance to reject the mode entirely. 5692 */ 5693 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5694 struct intel_encoder *encoder = 5695 to_intel_encoder(connector_state->best_encoder); 5696 5697 if (connector_state->crtc != &crtc->base) 5698 continue; 5699 5700 ret = encoder->compute_config(encoder, crtc_state, 5701 connector_state); 5702 if (ret == -EDEADLK) 5703 return ret; 5704 if (ret < 0) { 5705 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n", 5706 encoder->base.base.id, encoder->base.name, ret); 5707 return ret; 5708 } 5709 } 5710 5711 /* Set default port clock if not overwritten by the encoder. Needs to be 5712 * done afterwards in case the encoder adjusts the mode. */ 5713 if (!crtc_state->port_clock) 5714 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock 5715 * crtc_state->pixel_multiplier; 5716 5717 ret = intel_crtc_compute_config(state, crtc); 5718 if (ret == -EDEADLK) 5719 return ret; 5720 if (ret == -EAGAIN) { 5721 if (drm_WARN(&i915->drm, !retry, 5722 "[CRTC:%d:%s] loop in pipe configuration computation\n", 5723 crtc->base.base.id, crtc->base.name)) 5724 return -EINVAL; 5725 5726 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] bw constrained, retrying\n", 5727 crtc->base.base.id, crtc->base.name); 5728 retry = false; 5729 goto encoder_retry; 5730 } 5731 if (ret < 0) { 5732 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n", 5733 crtc->base.base.id, crtc->base.name, ret); 5734 return ret; 5735 } 5736 5737 /* Dithering seems to not pass-through bits correctly when it should, so 5738 * only enable it on 6bpc panels and when its not a compliance 5739 * test requesting 6bpc video pattern. 5740 */ 5741 crtc_state->dither = (crtc_state->pipe_bpp == 6*3) && 5742 !crtc_state->dither_force_disable; 5743 drm_dbg_kms(&i915->drm, 5744 "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n", 5745 crtc->base.base.id, crtc->base.name, 5746 base_bpp, crtc_state->pipe_bpp, crtc_state->dither); 5747 5748 return 0; 5749 } 5750 5751 static int 5752 intel_modeset_pipe_config_late(struct intel_atomic_state *state, 5753 struct intel_crtc *crtc) 5754 { 5755 struct intel_crtc_state *crtc_state = 5756 intel_atomic_get_new_crtc_state(state, crtc); 5757 struct drm_connector_state *conn_state; 5758 struct drm_connector *connector; 5759 int i; 5760 5761 intel_bigjoiner_adjust_pipe_src(crtc_state); 5762 5763 for_each_new_connector_in_state(&state->base, connector, 5764 conn_state, i) { 5765 struct intel_encoder *encoder = 5766 to_intel_encoder(conn_state->best_encoder); 5767 int ret; 5768 5769 if (conn_state->crtc != &crtc->base || 5770 !encoder->compute_config_late) 5771 continue; 5772 5773 ret = encoder->compute_config_late(encoder, crtc_state, 5774 conn_state); 5775 if (ret) 5776 return ret; 5777 } 5778 5779 return 0; 5780 } 5781 5782 bool intel_fuzzy_clock_check(int clock1, int clock2) 5783 { 5784 int diff; 5785 5786 if (clock1 == clock2) 5787 return true; 5788 5789 if (!clock1 || !clock2) 5790 return false; 5791 5792 diff = abs(clock1 - clock2); 5793 5794 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) 5795 return true; 5796 5797 return false; 5798 } 5799 5800 static bool 5801 intel_compare_m_n(unsigned int m, unsigned int n, 5802 unsigned int m2, unsigned int n2, 5803 bool exact) 5804 { 5805 if (m == m2 && n == n2) 5806 return true; 5807 5808 if (exact || !m || !n || !m2 || !n2) 5809 return false; 5810 5811 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); 5812 5813 if (n > n2) { 5814 while (n > n2) { 5815 m2 <<= 1; 5816 n2 <<= 1; 5817 } 5818 } else if (n < n2) { 5819 while (n < n2) { 5820 m <<= 1; 5821 n <<= 1; 5822 } 5823 } 5824 5825 if (n != n2) 5826 return false; 5827 5828 return intel_fuzzy_clock_check(m, m2); 5829 } 5830 5831 static bool 5832 intel_compare_link_m_n(const struct intel_link_m_n *m_n, 5833 const struct intel_link_m_n *m2_n2, 5834 bool exact) 5835 { 5836 return m_n->tu == m2_n2->tu && 5837 intel_compare_m_n(m_n->data_m, m_n->data_n, 5838 m2_n2->data_m, m2_n2->data_n, exact) && 5839 intel_compare_m_n(m_n->link_m, m_n->link_n, 5840 m2_n2->link_m, m2_n2->link_n, exact); 5841 } 5842 5843 static bool 5844 intel_compare_infoframe(const union hdmi_infoframe *a, 5845 const union hdmi_infoframe *b) 5846 { 5847 return memcmp(a, b, sizeof(*a)) == 0; 5848 } 5849 5850 static bool 5851 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a, 5852 const struct drm_dp_vsc_sdp *b) 5853 { 5854 return memcmp(a, b, sizeof(*a)) == 0; 5855 } 5856 5857 static void 5858 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv, 5859 bool fastset, const char *name, 5860 const union hdmi_infoframe *a, 5861 const union hdmi_infoframe *b) 5862 { 5863 if (fastset) { 5864 if (!drm_debug_enabled(DRM_UT_KMS)) 5865 return; 5866 5867 drm_dbg_kms(&dev_priv->drm, 5868 "fastset mismatch in %s infoframe\n", name); 5869 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 5870 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a); 5871 drm_dbg_kms(&dev_priv->drm, "found:\n"); 5872 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b); 5873 } else { 5874 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name); 5875 drm_err(&dev_priv->drm, "expected:\n"); 5876 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a); 5877 drm_err(&dev_priv->drm, "found:\n"); 5878 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b); 5879 } 5880 } 5881 5882 static void 5883 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv, 5884 bool fastset, const char *name, 5885 const struct drm_dp_vsc_sdp *a, 5886 const struct drm_dp_vsc_sdp *b) 5887 { 5888 if (fastset) { 5889 if (!drm_debug_enabled(DRM_UT_KMS)) 5890 return; 5891 5892 drm_dbg_kms(&dev_priv->drm, 5893 "fastset mismatch in %s dp sdp\n", name); 5894 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 5895 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a); 5896 drm_dbg_kms(&dev_priv->drm, "found:\n"); 5897 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b); 5898 } else { 5899 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name); 5900 drm_err(&dev_priv->drm, "expected:\n"); 5901 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a); 5902 drm_err(&dev_priv->drm, "found:\n"); 5903 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b); 5904 } 5905 } 5906 5907 static void __printf(4, 5) 5908 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc, 5909 const char *name, const char *format, ...) 5910 { 5911 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 5912 struct va_format vaf; 5913 va_list args; 5914 5915 va_start(args, format); 5916 vaf.fmt = format; 5917 vaf.va = &args; 5918 5919 if (fastset) 5920 drm_dbg_kms(&i915->drm, 5921 "[CRTC:%d:%s] fastset mismatch in %s %pV\n", 5922 crtc->base.base.id, crtc->base.name, name, &vaf); 5923 else 5924 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n", 5925 crtc->base.base.id, crtc->base.name, name, &vaf); 5926 5927 va_end(args); 5928 } 5929 5930 static bool fastboot_enabled(struct drm_i915_private *dev_priv) 5931 { 5932 if (dev_priv->params.fastboot != -1) 5933 return dev_priv->params.fastboot; 5934 5935 /* Enable fastboot by default on Skylake and newer */ 5936 if (DISPLAY_VER(dev_priv) >= 9) 5937 return true; 5938 5939 /* Enable fastboot by default on VLV and CHV */ 5940 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5941 return true; 5942 5943 /* Disabled by default on all others */ 5944 return false; 5945 } 5946 5947 bool 5948 intel_pipe_config_compare(const struct intel_crtc_state *current_config, 5949 const struct intel_crtc_state *pipe_config, 5950 bool fastset) 5951 { 5952 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev); 5953 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 5954 bool ret = true; 5955 u32 bp_gamma = 0; 5956 bool fixup_inherited = fastset && 5957 current_config->inherited && !pipe_config->inherited; 5958 5959 if (fixup_inherited && !fastboot_enabled(dev_priv)) { 5960 drm_dbg_kms(&dev_priv->drm, 5961 "initial modeset and fastboot not set\n"); 5962 ret = false; 5963 } 5964 5965 #define PIPE_CONF_CHECK_X(name) do { \ 5966 if (current_config->name != pipe_config->name) { \ 5967 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5968 "(expected 0x%08x, found 0x%08x)", \ 5969 current_config->name, \ 5970 pipe_config->name); \ 5971 ret = false; \ 5972 } \ 5973 } while (0) 5974 5975 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \ 5976 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \ 5977 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5978 "(expected 0x%08x, found 0x%08x)", \ 5979 current_config->name & (mask), \ 5980 pipe_config->name & (mask)); \ 5981 ret = false; \ 5982 } \ 5983 } while (0) 5984 5985 #define PIPE_CONF_CHECK_I(name) do { \ 5986 if (current_config->name != pipe_config->name) { \ 5987 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5988 "(expected %i, found %i)", \ 5989 current_config->name, \ 5990 pipe_config->name); \ 5991 ret = false; \ 5992 } \ 5993 } while (0) 5994 5995 #define PIPE_CONF_CHECK_BOOL(name) do { \ 5996 if (current_config->name != pipe_config->name) { \ 5997 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5998 "(expected %s, found %s)", \ 5999 str_yes_no(current_config->name), \ 6000 str_yes_no(pipe_config->name)); \ 6001 ret = false; \ 6002 } \ 6003 } while (0) 6004 6005 /* 6006 * Checks state where we only read out the enabling, but not the entire 6007 * state itself (like full infoframes or ELD for audio). These states 6008 * require a full modeset on bootup to fix up. 6009 */ 6010 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \ 6011 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \ 6012 PIPE_CONF_CHECK_BOOL(name); \ 6013 } else { \ 6014 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6015 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \ 6016 str_yes_no(current_config->name), \ 6017 str_yes_no(pipe_config->name)); \ 6018 ret = false; \ 6019 } \ 6020 } while (0) 6021 6022 #define PIPE_CONF_CHECK_P(name) do { \ 6023 if (current_config->name != pipe_config->name) { \ 6024 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6025 "(expected %p, found %p)", \ 6026 current_config->name, \ 6027 pipe_config->name); \ 6028 ret = false; \ 6029 } \ 6030 } while (0) 6031 6032 #define PIPE_CONF_CHECK_M_N(name) do { \ 6033 if (!intel_compare_link_m_n(¤t_config->name, \ 6034 &pipe_config->name,\ 6035 !fastset)) { \ 6036 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6037 "(expected tu %i data %i/%i link %i/%i, " \ 6038 "found tu %i, data %i/%i link %i/%i)", \ 6039 current_config->name.tu, \ 6040 current_config->name.data_m, \ 6041 current_config->name.data_n, \ 6042 current_config->name.link_m, \ 6043 current_config->name.link_n, \ 6044 pipe_config->name.tu, \ 6045 pipe_config->name.data_m, \ 6046 pipe_config->name.data_n, \ 6047 pipe_config->name.link_m, \ 6048 pipe_config->name.link_n); \ 6049 ret = false; \ 6050 } \ 6051 } while (0) 6052 6053 #define PIPE_CONF_CHECK_TIMINGS(name) do { \ 6054 PIPE_CONF_CHECK_I(name.crtc_hdisplay); \ 6055 PIPE_CONF_CHECK_I(name.crtc_htotal); \ 6056 PIPE_CONF_CHECK_I(name.crtc_hblank_start); \ 6057 PIPE_CONF_CHECK_I(name.crtc_hblank_end); \ 6058 PIPE_CONF_CHECK_I(name.crtc_hsync_start); \ 6059 PIPE_CONF_CHECK_I(name.crtc_hsync_end); \ 6060 PIPE_CONF_CHECK_I(name.crtc_vdisplay); \ 6061 PIPE_CONF_CHECK_I(name.crtc_vtotal); \ 6062 PIPE_CONF_CHECK_I(name.crtc_vblank_start); \ 6063 PIPE_CONF_CHECK_I(name.crtc_vblank_end); \ 6064 PIPE_CONF_CHECK_I(name.crtc_vsync_start); \ 6065 PIPE_CONF_CHECK_I(name.crtc_vsync_end); \ 6066 } while (0) 6067 6068 #define PIPE_CONF_CHECK_RECT(name) do { \ 6069 PIPE_CONF_CHECK_I(name.x1); \ 6070 PIPE_CONF_CHECK_I(name.x2); \ 6071 PIPE_CONF_CHECK_I(name.y1); \ 6072 PIPE_CONF_CHECK_I(name.y2); \ 6073 } while (0) 6074 6075 /* This is required for BDW+ where there is only one set of registers for 6076 * switching between high and low RR. 6077 * This macro can be used whenever a comparison has to be made between one 6078 * hw state and multiple sw state variables. 6079 */ 6080 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \ 6081 if (!intel_compare_link_m_n(¤t_config->name, \ 6082 &pipe_config->name, !fastset) && \ 6083 !intel_compare_link_m_n(¤t_config->alt_name, \ 6084 &pipe_config->name, !fastset)) { \ 6085 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6086 "(expected tu %i data %i/%i link %i/%i, " \ 6087 "or tu %i data %i/%i link %i/%i, " \ 6088 "found tu %i, data %i/%i link %i/%i)", \ 6089 current_config->name.tu, \ 6090 current_config->name.data_m, \ 6091 current_config->name.data_n, \ 6092 current_config->name.link_m, \ 6093 current_config->name.link_n, \ 6094 current_config->alt_name.tu, \ 6095 current_config->alt_name.data_m, \ 6096 current_config->alt_name.data_n, \ 6097 current_config->alt_name.link_m, \ 6098 current_config->alt_name.link_n, \ 6099 pipe_config->name.tu, \ 6100 pipe_config->name.data_m, \ 6101 pipe_config->name.data_n, \ 6102 pipe_config->name.link_m, \ 6103 pipe_config->name.link_n); \ 6104 ret = false; \ 6105 } \ 6106 } while (0) 6107 6108 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \ 6109 if ((current_config->name ^ pipe_config->name) & (mask)) { \ 6110 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6111 "(%x) (expected %i, found %i)", \ 6112 (mask), \ 6113 current_config->name & (mask), \ 6114 pipe_config->name & (mask)); \ 6115 ret = false; \ 6116 } \ 6117 } while (0) 6118 6119 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \ 6120 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ 6121 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6122 "(expected %i, found %i)", \ 6123 current_config->name, \ 6124 pipe_config->name); \ 6125 ret = false; \ 6126 } \ 6127 } while (0) 6128 6129 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \ 6130 if (!intel_compare_infoframe(¤t_config->infoframes.name, \ 6131 &pipe_config->infoframes.name)) { \ 6132 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \ 6133 ¤t_config->infoframes.name, \ 6134 &pipe_config->infoframes.name); \ 6135 ret = false; \ 6136 } \ 6137 } while (0) 6138 6139 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \ 6140 if (!current_config->has_psr && !pipe_config->has_psr && \ 6141 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \ 6142 &pipe_config->infoframes.name)) { \ 6143 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \ 6144 ¤t_config->infoframes.name, \ 6145 &pipe_config->infoframes.name); \ 6146 ret = false; \ 6147 } \ 6148 } while (0) 6149 6150 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \ 6151 if (current_config->name1 != pipe_config->name1) { \ 6152 pipe_config_mismatch(fastset, crtc, __stringify(name1), \ 6153 "(expected %i, found %i, won't compare lut values)", \ 6154 current_config->name1, \ 6155 pipe_config->name1); \ 6156 ret = false;\ 6157 } else { \ 6158 if (!intel_color_lut_equal(current_config->name2, \ 6159 pipe_config->name2, pipe_config->name1, \ 6160 bit_precision)) { \ 6161 pipe_config_mismatch(fastset, crtc, __stringify(name2), \ 6162 "hw_state doesn't match sw_state"); \ 6163 ret = false; \ 6164 } \ 6165 } \ 6166 } while (0) 6167 6168 #define PIPE_CONF_QUIRK(quirk) \ 6169 ((current_config->quirks | pipe_config->quirks) & (quirk)) 6170 6171 PIPE_CONF_CHECK_I(hw.enable); 6172 PIPE_CONF_CHECK_I(hw.active); 6173 6174 PIPE_CONF_CHECK_I(cpu_transcoder); 6175 PIPE_CONF_CHECK_I(mst_master_transcoder); 6176 6177 PIPE_CONF_CHECK_BOOL(has_pch_encoder); 6178 PIPE_CONF_CHECK_I(fdi_lanes); 6179 PIPE_CONF_CHECK_M_N(fdi_m_n); 6180 6181 PIPE_CONF_CHECK_I(lane_count); 6182 PIPE_CONF_CHECK_X(lane_lat_optim_mask); 6183 6184 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) { 6185 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); 6186 } else { 6187 PIPE_CONF_CHECK_M_N(dp_m_n); 6188 PIPE_CONF_CHECK_M_N(dp_m2_n2); 6189 } 6190 6191 PIPE_CONF_CHECK_X(output_types); 6192 6193 PIPE_CONF_CHECK_I(framestart_delay); 6194 PIPE_CONF_CHECK_I(msa_timing_delay); 6195 6196 PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode); 6197 PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode); 6198 6199 PIPE_CONF_CHECK_I(pixel_multiplier); 6200 6201 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6202 DRM_MODE_FLAG_INTERLACE); 6203 6204 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { 6205 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6206 DRM_MODE_FLAG_PHSYNC); 6207 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6208 DRM_MODE_FLAG_NHSYNC); 6209 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6210 DRM_MODE_FLAG_PVSYNC); 6211 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6212 DRM_MODE_FLAG_NVSYNC); 6213 } 6214 6215 PIPE_CONF_CHECK_I(output_format); 6216 PIPE_CONF_CHECK_BOOL(has_hdmi_sink); 6217 if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || 6218 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 6219 PIPE_CONF_CHECK_BOOL(limited_color_range); 6220 6221 PIPE_CONF_CHECK_BOOL(hdmi_scrambling); 6222 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio); 6223 PIPE_CONF_CHECK_BOOL(has_infoframe); 6224 PIPE_CONF_CHECK_BOOL(fec_enable); 6225 6226 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio); 6227 6228 PIPE_CONF_CHECK_X(gmch_pfit.control); 6229 /* pfit ratios are autocomputed by the hw on gen4+ */ 6230 if (DISPLAY_VER(dev_priv) < 4) 6231 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); 6232 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); 6233 6234 /* 6235 * Changing the EDP transcoder input mux 6236 * (A_ONOFF vs. A_ON) requires a full modeset. 6237 */ 6238 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru); 6239 6240 if (!fastset) { 6241 PIPE_CONF_CHECK_RECT(pipe_src); 6242 6243 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled); 6244 PIPE_CONF_CHECK_RECT(pch_pfit.dst); 6245 6246 PIPE_CONF_CHECK_I(scaler_state.scaler_id); 6247 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate); 6248 6249 PIPE_CONF_CHECK_X(gamma_mode); 6250 if (IS_CHERRYVIEW(dev_priv)) 6251 PIPE_CONF_CHECK_X(cgm_mode); 6252 else 6253 PIPE_CONF_CHECK_X(csc_mode); 6254 PIPE_CONF_CHECK_BOOL(gamma_enable); 6255 PIPE_CONF_CHECK_BOOL(csc_enable); 6256 6257 PIPE_CONF_CHECK_I(linetime); 6258 PIPE_CONF_CHECK_I(ips_linetime); 6259 6260 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config); 6261 if (bp_gamma) 6262 PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma); 6263 6264 if (current_config->active_planes) { 6265 PIPE_CONF_CHECK_BOOL(has_psr); 6266 PIPE_CONF_CHECK_BOOL(has_psr2); 6267 PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); 6268 PIPE_CONF_CHECK_I(dc3co_exitline); 6269 } 6270 } 6271 6272 PIPE_CONF_CHECK_BOOL(double_wide); 6273 6274 if (dev_priv->dpll.mgr) { 6275 PIPE_CONF_CHECK_P(shared_dpll); 6276 6277 PIPE_CONF_CHECK_X(dpll_hw_state.dpll); 6278 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); 6279 PIPE_CONF_CHECK_X(dpll_hw_state.fp0); 6280 PIPE_CONF_CHECK_X(dpll_hw_state.fp1); 6281 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); 6282 PIPE_CONF_CHECK_X(dpll_hw_state.spll); 6283 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); 6284 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); 6285 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); 6286 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); 6287 PIPE_CONF_CHECK_X(dpll_hw_state.div0); 6288 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); 6289 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); 6290 PIPE_CONF_CHECK_X(dpll_hw_state.pll0); 6291 PIPE_CONF_CHECK_X(dpll_hw_state.pll1); 6292 PIPE_CONF_CHECK_X(dpll_hw_state.pll2); 6293 PIPE_CONF_CHECK_X(dpll_hw_state.pll3); 6294 PIPE_CONF_CHECK_X(dpll_hw_state.pll6); 6295 PIPE_CONF_CHECK_X(dpll_hw_state.pll8); 6296 PIPE_CONF_CHECK_X(dpll_hw_state.pll9); 6297 PIPE_CONF_CHECK_X(dpll_hw_state.pll10); 6298 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); 6299 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl); 6300 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1); 6301 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl); 6302 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0); 6303 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1); 6304 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf); 6305 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock); 6306 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc); 6307 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias); 6308 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias); 6309 } 6310 6311 PIPE_CONF_CHECK_X(dsi_pll.ctrl); 6312 PIPE_CONF_CHECK_X(dsi_pll.div); 6313 6314 if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5) 6315 PIPE_CONF_CHECK_I(pipe_bpp); 6316 6317 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock); 6318 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock); 6319 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); 6320 6321 PIPE_CONF_CHECK_I(min_voltage_level); 6322 6323 if (current_config->has_psr || pipe_config->has_psr) 6324 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable, 6325 ~intel_hdmi_infoframe_enable(DP_SDP_VSC)); 6326 else 6327 PIPE_CONF_CHECK_X(infoframes.enable); 6328 6329 PIPE_CONF_CHECK_X(infoframes.gcp); 6330 PIPE_CONF_CHECK_INFOFRAME(avi); 6331 PIPE_CONF_CHECK_INFOFRAME(spd); 6332 PIPE_CONF_CHECK_INFOFRAME(hdmi); 6333 PIPE_CONF_CHECK_INFOFRAME(drm); 6334 PIPE_CONF_CHECK_DP_VSC_SDP(vsc); 6335 6336 PIPE_CONF_CHECK_X(sync_mode_slaves_mask); 6337 PIPE_CONF_CHECK_I(master_transcoder); 6338 PIPE_CONF_CHECK_X(bigjoiner_pipes); 6339 6340 PIPE_CONF_CHECK_I(dsc.compression_enable); 6341 PIPE_CONF_CHECK_I(dsc.dsc_split); 6342 PIPE_CONF_CHECK_I(dsc.compressed_bpp); 6343 6344 PIPE_CONF_CHECK_BOOL(splitter.enable); 6345 PIPE_CONF_CHECK_I(splitter.link_count); 6346 PIPE_CONF_CHECK_I(splitter.pixel_overlap); 6347 6348 PIPE_CONF_CHECK_BOOL(vrr.enable); 6349 PIPE_CONF_CHECK_I(vrr.vmin); 6350 PIPE_CONF_CHECK_I(vrr.vmax); 6351 PIPE_CONF_CHECK_I(vrr.flipline); 6352 PIPE_CONF_CHECK_I(vrr.pipeline_full); 6353 PIPE_CONF_CHECK_I(vrr.guardband); 6354 6355 #undef PIPE_CONF_CHECK_X 6356 #undef PIPE_CONF_CHECK_I 6357 #undef PIPE_CONF_CHECK_BOOL 6358 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE 6359 #undef PIPE_CONF_CHECK_P 6360 #undef PIPE_CONF_CHECK_FLAGS 6361 #undef PIPE_CONF_CHECK_CLOCK_FUZZY 6362 #undef PIPE_CONF_CHECK_COLOR_LUT 6363 #undef PIPE_CONF_CHECK_TIMINGS 6364 #undef PIPE_CONF_CHECK_RECT 6365 #undef PIPE_CONF_QUIRK 6366 6367 return ret; 6368 } 6369 6370 static void 6371 intel_verify_planes(struct intel_atomic_state *state) 6372 { 6373 struct intel_plane *plane; 6374 const struct intel_plane_state *plane_state; 6375 int i; 6376 6377 for_each_new_intel_plane_in_state(state, plane, 6378 plane_state, i) 6379 assert_plane(plane, plane_state->planar_slave || 6380 plane_state->uapi.visible); 6381 } 6382 6383 int intel_modeset_all_pipes(struct intel_atomic_state *state) 6384 { 6385 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6386 struct intel_crtc *crtc; 6387 6388 /* 6389 * Add all pipes to the state, and force 6390 * a modeset on all the active ones. 6391 */ 6392 for_each_intel_crtc(&dev_priv->drm, crtc) { 6393 struct intel_crtc_state *crtc_state; 6394 int ret; 6395 6396 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6397 if (IS_ERR(crtc_state)) 6398 return PTR_ERR(crtc_state); 6399 6400 if (!crtc_state->hw.active || 6401 drm_atomic_crtc_needs_modeset(&crtc_state->uapi)) 6402 continue; 6403 6404 crtc_state->uapi.mode_changed = true; 6405 6406 ret = drm_atomic_add_affected_connectors(&state->base, 6407 &crtc->base); 6408 if (ret) 6409 return ret; 6410 6411 ret = intel_atomic_add_affected_planes(state, crtc); 6412 if (ret) 6413 return ret; 6414 6415 crtc_state->update_planes |= crtc_state->active_planes; 6416 } 6417 6418 return 0; 6419 } 6420 6421 static void 6422 intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state) 6423 { 6424 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 6425 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6426 struct drm_display_mode adjusted_mode; 6427 6428 drm_mode_init(&adjusted_mode, &crtc_state->hw.adjusted_mode); 6429 6430 if (crtc_state->vrr.enable) { 6431 adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax; 6432 adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax; 6433 adjusted_mode.crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state); 6434 crtc->vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state); 6435 } 6436 6437 drm_calc_timestamping_constants(&crtc->base, &adjusted_mode); 6438 6439 crtc->mode_flags = crtc_state->mode_flags; 6440 6441 /* 6442 * The scanline counter increments at the leading edge of hsync. 6443 * 6444 * On most platforms it starts counting from vtotal-1 on the 6445 * first active line. That means the scanline counter value is 6446 * always one less than what we would expect. Ie. just after 6447 * start of vblank, which also occurs at start of hsync (on the 6448 * last active line), the scanline counter will read vblank_start-1. 6449 * 6450 * On gen2 the scanline counter starts counting from 1 instead 6451 * of vtotal-1, so we have to subtract one (or rather add vtotal-1 6452 * to keep the value positive), instead of adding one. 6453 * 6454 * On HSW+ the behaviour of the scanline counter depends on the output 6455 * type. For DP ports it behaves like most other platforms, but on HDMI 6456 * there's an extra 1 line difference. So we need to add two instead of 6457 * one to the value. 6458 * 6459 * On VLV/CHV DSI the scanline counter would appear to increment 6460 * approx. 1/3 of a scanline before start of vblank. Unfortunately 6461 * that means we can't tell whether we're in vblank or not while 6462 * we're on that particular line. We must still set scanline_offset 6463 * to 1 so that the vblank timestamps come out correct when we query 6464 * the scanline counter from within the vblank interrupt handler. 6465 * However if queried just before the start of vblank we'll get an 6466 * answer that's slightly in the future. 6467 */ 6468 if (DISPLAY_VER(dev_priv) == 2) { 6469 int vtotal; 6470 6471 vtotal = adjusted_mode.crtc_vtotal; 6472 if (adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 6473 vtotal /= 2; 6474 6475 crtc->scanline_offset = vtotal - 1; 6476 } else if (HAS_DDI(dev_priv) && 6477 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 6478 crtc->scanline_offset = 2; 6479 } else { 6480 crtc->scanline_offset = 1; 6481 } 6482 } 6483 6484 static void intel_modeset_clear_plls(struct intel_atomic_state *state) 6485 { 6486 struct intel_crtc_state *new_crtc_state; 6487 struct intel_crtc *crtc; 6488 int i; 6489 6490 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6491 if (!intel_crtc_needs_modeset(new_crtc_state)) 6492 continue; 6493 6494 intel_release_shared_dplls(state, crtc); 6495 } 6496 } 6497 6498 /* 6499 * This implements the workaround described in the "notes" section of the mode 6500 * set sequence documentation. When going from no pipes or single pipe to 6501 * multiple pipes, and planes are enabled after the pipe, we need to wait at 6502 * least 2 vblanks on the first pipe before enabling planes on the second pipe. 6503 */ 6504 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state) 6505 { 6506 struct intel_crtc_state *crtc_state; 6507 struct intel_crtc *crtc; 6508 struct intel_crtc_state *first_crtc_state = NULL; 6509 struct intel_crtc_state *other_crtc_state = NULL; 6510 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; 6511 int i; 6512 6513 /* look at all crtc's that are going to be enabled in during modeset */ 6514 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6515 if (!crtc_state->hw.active || 6516 !intel_crtc_needs_modeset(crtc_state)) 6517 continue; 6518 6519 if (first_crtc_state) { 6520 other_crtc_state = crtc_state; 6521 break; 6522 } else { 6523 first_crtc_state = crtc_state; 6524 first_pipe = crtc->pipe; 6525 } 6526 } 6527 6528 /* No workaround needed? */ 6529 if (!first_crtc_state) 6530 return 0; 6531 6532 /* w/a possibly needed, check how many crtc's are already enabled. */ 6533 for_each_intel_crtc(state->base.dev, crtc) { 6534 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6535 if (IS_ERR(crtc_state)) 6536 return PTR_ERR(crtc_state); 6537 6538 crtc_state->hsw_workaround_pipe = INVALID_PIPE; 6539 6540 if (!crtc_state->hw.active || 6541 intel_crtc_needs_modeset(crtc_state)) 6542 continue; 6543 6544 /* 2 or more enabled crtcs means no need for w/a */ 6545 if (enabled_pipe != INVALID_PIPE) 6546 return 0; 6547 6548 enabled_pipe = crtc->pipe; 6549 } 6550 6551 if (enabled_pipe != INVALID_PIPE) 6552 first_crtc_state->hsw_workaround_pipe = enabled_pipe; 6553 else if (other_crtc_state) 6554 other_crtc_state->hsw_workaround_pipe = first_pipe; 6555 6556 return 0; 6557 } 6558 6559 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 6560 u8 active_pipes) 6561 { 6562 const struct intel_crtc_state *crtc_state; 6563 struct intel_crtc *crtc; 6564 int i; 6565 6566 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6567 if (crtc_state->hw.active) 6568 active_pipes |= BIT(crtc->pipe); 6569 else 6570 active_pipes &= ~BIT(crtc->pipe); 6571 } 6572 6573 return active_pipes; 6574 } 6575 6576 static int intel_modeset_checks(struct intel_atomic_state *state) 6577 { 6578 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6579 6580 state->modeset = true; 6581 6582 if (IS_HASWELL(dev_priv)) 6583 return hsw_mode_set_planes_workaround(state); 6584 6585 return 0; 6586 } 6587 6588 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state, 6589 struct intel_crtc_state *new_crtc_state) 6590 { 6591 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) 6592 return; 6593 6594 new_crtc_state->uapi.mode_changed = false; 6595 new_crtc_state->update_pipe = true; 6596 } 6597 6598 static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state, 6599 struct intel_crtc_state *new_crtc_state) 6600 { 6601 /* 6602 * If we're not doing the full modeset we want to 6603 * keep the current M/N values as they may be 6604 * sufficiently different to the computed values 6605 * to cause problems. 6606 * 6607 * FIXME: should really copy more fuzzy state here 6608 */ 6609 new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n; 6610 new_crtc_state->dp_m_n = old_crtc_state->dp_m_n; 6611 new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2; 6612 new_crtc_state->has_drrs = old_crtc_state->has_drrs; 6613 } 6614 6615 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state, 6616 struct intel_crtc *crtc, 6617 u8 plane_ids_mask) 6618 { 6619 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6620 struct intel_plane *plane; 6621 6622 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 6623 struct intel_plane_state *plane_state; 6624 6625 if ((plane_ids_mask & BIT(plane->id)) == 0) 6626 continue; 6627 6628 plane_state = intel_atomic_get_plane_state(state, plane); 6629 if (IS_ERR(plane_state)) 6630 return PTR_ERR(plane_state); 6631 } 6632 6633 return 0; 6634 } 6635 6636 int intel_atomic_add_affected_planes(struct intel_atomic_state *state, 6637 struct intel_crtc *crtc) 6638 { 6639 const struct intel_crtc_state *old_crtc_state = 6640 intel_atomic_get_old_crtc_state(state, crtc); 6641 const struct intel_crtc_state *new_crtc_state = 6642 intel_atomic_get_new_crtc_state(state, crtc); 6643 6644 return intel_crtc_add_planes_to_state(state, crtc, 6645 old_crtc_state->enabled_planes | 6646 new_crtc_state->enabled_planes); 6647 } 6648 6649 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv) 6650 { 6651 /* See {hsw,vlv,ivb}_plane_ratio() */ 6652 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) || 6653 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) || 6654 IS_IVYBRIDGE(dev_priv); 6655 } 6656 6657 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state, 6658 struct intel_crtc *crtc, 6659 struct intel_crtc *other) 6660 { 6661 const struct intel_plane_state *plane_state; 6662 struct intel_plane *plane; 6663 u8 plane_ids = 0; 6664 int i; 6665 6666 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 6667 if (plane->pipe == crtc->pipe) 6668 plane_ids |= BIT(plane->id); 6669 } 6670 6671 return intel_crtc_add_planes_to_state(state, other, plane_ids); 6672 } 6673 6674 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state) 6675 { 6676 struct drm_i915_private *i915 = to_i915(state->base.dev); 6677 const struct intel_crtc_state *crtc_state; 6678 struct intel_crtc *crtc; 6679 int i; 6680 6681 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6682 struct intel_crtc *other; 6683 6684 for_each_intel_crtc_in_pipe_mask(&i915->drm, other, 6685 crtc_state->bigjoiner_pipes) { 6686 int ret; 6687 6688 if (crtc == other) 6689 continue; 6690 6691 ret = intel_crtc_add_bigjoiner_planes(state, crtc, other); 6692 if (ret) 6693 return ret; 6694 } 6695 } 6696 6697 return 0; 6698 } 6699 6700 static int intel_atomic_check_planes(struct intel_atomic_state *state) 6701 { 6702 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6703 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6704 struct intel_plane_state *plane_state; 6705 struct intel_plane *plane; 6706 struct intel_crtc *crtc; 6707 int i, ret; 6708 6709 ret = icl_add_linked_planes(state); 6710 if (ret) 6711 return ret; 6712 6713 ret = intel_bigjoiner_add_affected_planes(state); 6714 if (ret) 6715 return ret; 6716 6717 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 6718 ret = intel_plane_atomic_check(state, plane); 6719 if (ret) { 6720 drm_dbg_atomic(&dev_priv->drm, 6721 "[PLANE:%d:%s] atomic driver check failed\n", 6722 plane->base.base.id, plane->base.name); 6723 return ret; 6724 } 6725 } 6726 6727 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6728 new_crtc_state, i) { 6729 u8 old_active_planes, new_active_planes; 6730 6731 ret = icl_check_nv12_planes(new_crtc_state); 6732 if (ret) 6733 return ret; 6734 6735 /* 6736 * On some platforms the number of active planes affects 6737 * the planes' minimum cdclk calculation. Add such planes 6738 * to the state before we compute the minimum cdclk. 6739 */ 6740 if (!active_planes_affects_min_cdclk(dev_priv)) 6741 continue; 6742 6743 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 6744 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 6745 6746 if (hweight8(old_active_planes) == hweight8(new_active_planes)) 6747 continue; 6748 6749 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes); 6750 if (ret) 6751 return ret; 6752 } 6753 6754 return 0; 6755 } 6756 6757 static int intel_atomic_check_crtcs(struct intel_atomic_state *state) 6758 { 6759 struct intel_crtc_state *crtc_state; 6760 struct intel_crtc *crtc; 6761 int i; 6762 6763 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6764 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 6765 int ret; 6766 6767 ret = intel_crtc_atomic_check(state, crtc); 6768 if (ret) { 6769 drm_dbg_atomic(&i915->drm, 6770 "[CRTC:%d:%s] atomic driver check failed\n", 6771 crtc->base.base.id, crtc->base.name); 6772 return ret; 6773 } 6774 } 6775 6776 return 0; 6777 } 6778 6779 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, 6780 u8 transcoders) 6781 { 6782 const struct intel_crtc_state *new_crtc_state; 6783 struct intel_crtc *crtc; 6784 int i; 6785 6786 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6787 if (new_crtc_state->hw.enable && 6788 transcoders & BIT(new_crtc_state->cpu_transcoder) && 6789 intel_crtc_needs_modeset(new_crtc_state)) 6790 return true; 6791 } 6792 6793 return false; 6794 } 6795 6796 static bool intel_pipes_need_modeset(struct intel_atomic_state *state, 6797 u8 pipes) 6798 { 6799 const struct intel_crtc_state *new_crtc_state; 6800 struct intel_crtc *crtc; 6801 int i; 6802 6803 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6804 if (new_crtc_state->hw.enable && 6805 pipes & BIT(crtc->pipe) && 6806 intel_crtc_needs_modeset(new_crtc_state)) 6807 return true; 6808 } 6809 6810 return false; 6811 } 6812 6813 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state, 6814 struct intel_crtc *master_crtc) 6815 { 6816 struct drm_i915_private *i915 = to_i915(state->base.dev); 6817 struct intel_crtc_state *master_crtc_state = 6818 intel_atomic_get_new_crtc_state(state, master_crtc); 6819 struct intel_crtc *slave_crtc; 6820 6821 if (!master_crtc_state->bigjoiner_pipes) 6822 return 0; 6823 6824 /* sanity check */ 6825 if (drm_WARN_ON(&i915->drm, 6826 master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state))) 6827 return -EINVAL; 6828 6829 if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) { 6830 drm_dbg_kms(&i915->drm, 6831 "[CRTC:%d:%s] Cannot act as big joiner master " 6832 "(need 0x%x as pipes, only 0x%x possible)\n", 6833 master_crtc->base.base.id, master_crtc->base.name, 6834 master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915)); 6835 return -EINVAL; 6836 } 6837 6838 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 6839 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 6840 struct intel_crtc_state *slave_crtc_state; 6841 int ret; 6842 6843 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc); 6844 if (IS_ERR(slave_crtc_state)) 6845 return PTR_ERR(slave_crtc_state); 6846 6847 /* master being enabled, slave was already configured? */ 6848 if (slave_crtc_state->uapi.enable) { 6849 drm_dbg_kms(&i915->drm, 6850 "[CRTC:%d:%s] Slave is enabled as normal CRTC, but " 6851 "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n", 6852 slave_crtc->base.base.id, slave_crtc->base.name, 6853 master_crtc->base.base.id, master_crtc->base.name); 6854 return -EINVAL; 6855 } 6856 6857 /* 6858 * The state copy logic assumes the master crtc gets processed 6859 * before the slave crtc during the main compute_config loop. 6860 * This works because the crtcs are created in pipe order, 6861 * and the hardware requires master pipe < slave pipe as well. 6862 * Should that change we need to rethink the logic. 6863 */ 6864 if (WARN_ON(drm_crtc_index(&master_crtc->base) > 6865 drm_crtc_index(&slave_crtc->base))) 6866 return -EINVAL; 6867 6868 drm_dbg_kms(&i915->drm, 6869 "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n", 6870 slave_crtc->base.base.id, slave_crtc->base.name, 6871 master_crtc->base.base.id, master_crtc->base.name); 6872 6873 slave_crtc_state->bigjoiner_pipes = 6874 master_crtc_state->bigjoiner_pipes; 6875 6876 ret = copy_bigjoiner_crtc_state_modeset(state, slave_crtc); 6877 if (ret) 6878 return ret; 6879 } 6880 6881 return 0; 6882 } 6883 6884 static void kill_bigjoiner_slave(struct intel_atomic_state *state, 6885 struct intel_crtc *master_crtc) 6886 { 6887 struct drm_i915_private *i915 = to_i915(state->base.dev); 6888 struct intel_crtc_state *master_crtc_state = 6889 intel_atomic_get_new_crtc_state(state, master_crtc); 6890 struct intel_crtc *slave_crtc; 6891 6892 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 6893 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 6894 struct intel_crtc_state *slave_crtc_state = 6895 intel_atomic_get_new_crtc_state(state, slave_crtc); 6896 6897 slave_crtc_state->bigjoiner_pipes = 0; 6898 6899 intel_crtc_copy_uapi_to_hw_state_modeset(state, slave_crtc); 6900 } 6901 6902 master_crtc_state->bigjoiner_pipes = 0; 6903 } 6904 6905 /** 6906 * DOC: asynchronous flip implementation 6907 * 6908 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC 6909 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL. 6910 * Correspondingly, support is currently added for primary plane only. 6911 * 6912 * Async flip can only change the plane surface address, so anything else 6913 * changing is rejected from the intel_async_flip_check_hw() function. 6914 * Once this check is cleared, flip done interrupt is enabled using 6915 * the intel_crtc_enable_flip_done() function. 6916 * 6917 * As soon as the surface address register is written, flip done interrupt is 6918 * generated and the requested events are sent to the usersapce in the interrupt 6919 * handler itself. The timestamp and sequence sent during the flip done event 6920 * correspond to the last vblank and have no relation to the actual time when 6921 * the flip done event was sent. 6922 */ 6923 static int intel_async_flip_check_uapi(struct intel_atomic_state *state, 6924 struct intel_crtc *crtc) 6925 { 6926 struct drm_i915_private *i915 = to_i915(state->base.dev); 6927 const struct intel_crtc_state *new_crtc_state = 6928 intel_atomic_get_new_crtc_state(state, crtc); 6929 const struct intel_plane_state *old_plane_state; 6930 struct intel_plane_state *new_plane_state; 6931 struct intel_plane *plane; 6932 int i; 6933 6934 if (!new_crtc_state->uapi.async_flip) 6935 return 0; 6936 6937 if (!new_crtc_state->uapi.active) { 6938 drm_dbg_kms(&i915->drm, 6939 "[CRTC:%d:%s] not active\n", 6940 crtc->base.base.id, crtc->base.name); 6941 return -EINVAL; 6942 } 6943 6944 if (intel_crtc_needs_modeset(new_crtc_state)) { 6945 drm_dbg_kms(&i915->drm, 6946 "[CRTC:%d:%s] modeset required\n", 6947 crtc->base.base.id, crtc->base.name); 6948 return -EINVAL; 6949 } 6950 6951 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 6952 new_plane_state, i) { 6953 if (plane->pipe != crtc->pipe) 6954 continue; 6955 6956 /* 6957 * TODO: Async flip is only supported through the page flip IOCTL 6958 * as of now. So support currently added for primary plane only. 6959 * Support for other planes on platforms on which supports 6960 * this(vlv/chv and icl+) should be added when async flip is 6961 * enabled in the atomic IOCTL path. 6962 */ 6963 if (!plane->async_flip) { 6964 drm_dbg_kms(&i915->drm, 6965 "[PLANE:%d:%s] async flip not supported\n", 6966 plane->base.base.id, plane->base.name); 6967 return -EINVAL; 6968 } 6969 6970 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) { 6971 drm_dbg_kms(&i915->drm, 6972 "[PLANE:%d:%s] no old or new framebuffer\n", 6973 plane->base.base.id, plane->base.name); 6974 return -EINVAL; 6975 } 6976 } 6977 6978 return 0; 6979 } 6980 6981 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc) 6982 { 6983 struct drm_i915_private *i915 = to_i915(state->base.dev); 6984 const struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6985 const struct intel_plane_state *new_plane_state, *old_plane_state; 6986 struct intel_plane *plane; 6987 int i; 6988 6989 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 6990 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6991 6992 if (!new_crtc_state->uapi.async_flip) 6993 return 0; 6994 6995 if (!new_crtc_state->hw.active) { 6996 drm_dbg_kms(&i915->drm, 6997 "[CRTC:%d:%s] not active\n", 6998 crtc->base.base.id, crtc->base.name); 6999 return -EINVAL; 7000 } 7001 7002 if (intel_crtc_needs_modeset(new_crtc_state)) { 7003 drm_dbg_kms(&i915->drm, 7004 "[CRTC:%d:%s] modeset required\n", 7005 crtc->base.base.id, crtc->base.name); 7006 return -EINVAL; 7007 } 7008 7009 if (old_crtc_state->active_planes != new_crtc_state->active_planes) { 7010 drm_dbg_kms(&i915->drm, 7011 "[CRTC:%d:%s] Active planes cannot be in async flip\n", 7012 crtc->base.base.id, crtc->base.name); 7013 return -EINVAL; 7014 } 7015 7016 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 7017 new_plane_state, i) { 7018 if (plane->pipe != crtc->pipe) 7019 continue; 7020 7021 /* 7022 * Only async flip capable planes should be in the state 7023 * if we're really about to ask the hardware to perform 7024 * an async flip. We should never get this far otherwise. 7025 */ 7026 if (drm_WARN_ON(&i915->drm, 7027 new_crtc_state->do_async_flip && !plane->async_flip)) 7028 return -EINVAL; 7029 7030 /* 7031 * Only check async flip capable planes other planes 7032 * may be involved in the initial commit due to 7033 * the wm0/ddb optimization. 7034 * 7035 * TODO maybe should track which planes actually 7036 * were requested to do the async flip... 7037 */ 7038 if (!plane->async_flip) 7039 continue; 7040 7041 /* 7042 * FIXME: This check is kept generic for all platforms. 7043 * Need to verify this for all gen9 platforms to enable 7044 * this selectively if required. 7045 */ 7046 switch (new_plane_state->hw.fb->modifier) { 7047 case I915_FORMAT_MOD_X_TILED: 7048 case I915_FORMAT_MOD_Y_TILED: 7049 case I915_FORMAT_MOD_Yf_TILED: 7050 case I915_FORMAT_MOD_4_TILED: 7051 break; 7052 default: 7053 drm_dbg_kms(&i915->drm, 7054 "[PLANE:%d:%s] Modifier does not support async flips\n", 7055 plane->base.base.id, plane->base.name); 7056 return -EINVAL; 7057 } 7058 7059 if (new_plane_state->hw.fb->format->num_planes > 1) { 7060 drm_dbg_kms(&i915->drm, 7061 "[PLANE:%d:%s] Planar formats do not support async flips\n", 7062 plane->base.base.id, plane->base.name); 7063 return -EINVAL; 7064 } 7065 7066 if (old_plane_state->view.color_plane[0].mapping_stride != 7067 new_plane_state->view.color_plane[0].mapping_stride) { 7068 drm_dbg_kms(&i915->drm, 7069 "[PLANE:%d:%s] Stride cannot be changed in async flip\n", 7070 plane->base.base.id, plane->base.name); 7071 return -EINVAL; 7072 } 7073 7074 if (old_plane_state->hw.fb->modifier != 7075 new_plane_state->hw.fb->modifier) { 7076 drm_dbg_kms(&i915->drm, 7077 "[PLANE:%d:%s] Modifier cannot be changed in async flip\n", 7078 plane->base.base.id, plane->base.name); 7079 return -EINVAL; 7080 } 7081 7082 if (old_plane_state->hw.fb->format != 7083 new_plane_state->hw.fb->format) { 7084 drm_dbg_kms(&i915->drm, 7085 "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n", 7086 plane->base.base.id, plane->base.name); 7087 return -EINVAL; 7088 } 7089 7090 if (old_plane_state->hw.rotation != 7091 new_plane_state->hw.rotation) { 7092 drm_dbg_kms(&i915->drm, 7093 "[PLANE:%d:%s] Rotation cannot be changed in async flip\n", 7094 plane->base.base.id, plane->base.name); 7095 return -EINVAL; 7096 } 7097 7098 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) || 7099 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) { 7100 drm_dbg_kms(&i915->drm, 7101 "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n", 7102 plane->base.base.id, plane->base.name); 7103 return -EINVAL; 7104 } 7105 7106 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) { 7107 drm_dbg_kms(&i915->drm, 7108 "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n", 7109 plane->base.base.id, plane->base.name); 7110 return -EINVAL; 7111 } 7112 7113 if (old_plane_state->hw.pixel_blend_mode != 7114 new_plane_state->hw.pixel_blend_mode) { 7115 drm_dbg_kms(&i915->drm, 7116 "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n", 7117 plane->base.base.id, plane->base.name); 7118 return -EINVAL; 7119 } 7120 7121 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) { 7122 drm_dbg_kms(&i915->drm, 7123 "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n", 7124 plane->base.base.id, plane->base.name); 7125 return -EINVAL; 7126 } 7127 7128 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) { 7129 drm_dbg_kms(&i915->drm, 7130 "[PLANE:%d:%s] Color range cannot be changed in async flip\n", 7131 plane->base.base.id, plane->base.name); 7132 return -EINVAL; 7133 } 7134 7135 /* plane decryption is allow to change only in synchronous flips */ 7136 if (old_plane_state->decrypt != new_plane_state->decrypt) { 7137 drm_dbg_kms(&i915->drm, 7138 "[PLANE:%d:%s] Decryption cannot be changed in async flip\n", 7139 plane->base.base.id, plane->base.name); 7140 return -EINVAL; 7141 } 7142 } 7143 7144 return 0; 7145 } 7146 7147 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state) 7148 { 7149 struct drm_i915_private *i915 = to_i915(state->base.dev); 7150 struct intel_crtc_state *crtc_state; 7151 struct intel_crtc *crtc; 7152 u8 affected_pipes = 0; 7153 u8 modeset_pipes = 0; 7154 int i; 7155 7156 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7157 affected_pipes |= crtc_state->bigjoiner_pipes; 7158 if (intel_crtc_needs_modeset(crtc_state)) 7159 modeset_pipes |= crtc_state->bigjoiner_pipes; 7160 } 7161 7162 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) { 7163 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 7164 if (IS_ERR(crtc_state)) 7165 return PTR_ERR(crtc_state); 7166 } 7167 7168 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) { 7169 int ret; 7170 7171 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 7172 7173 crtc_state->uapi.mode_changed = true; 7174 7175 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); 7176 if (ret) 7177 return ret; 7178 7179 ret = intel_atomic_add_affected_planes(state, crtc); 7180 if (ret) 7181 return ret; 7182 } 7183 7184 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7185 /* Kill old bigjoiner link, we may re-establish afterwards */ 7186 if (intel_crtc_needs_modeset(crtc_state) && 7187 intel_crtc_is_bigjoiner_master(crtc_state)) 7188 kill_bigjoiner_slave(state, crtc); 7189 } 7190 7191 return 0; 7192 } 7193 7194 /** 7195 * intel_atomic_check - validate state object 7196 * @dev: drm device 7197 * @_state: state to validate 7198 */ 7199 static int intel_atomic_check(struct drm_device *dev, 7200 struct drm_atomic_state *_state) 7201 { 7202 struct drm_i915_private *dev_priv = to_i915(dev); 7203 struct intel_atomic_state *state = to_intel_atomic_state(_state); 7204 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7205 struct intel_crtc *crtc; 7206 int ret, i; 7207 bool any_ms = false; 7208 7209 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7210 new_crtc_state, i) { 7211 if (new_crtc_state->inherited != old_crtc_state->inherited) 7212 new_crtc_state->uapi.mode_changed = true; 7213 7214 if (new_crtc_state->uapi.scaling_filter != 7215 old_crtc_state->uapi.scaling_filter) 7216 new_crtc_state->uapi.mode_changed = true; 7217 } 7218 7219 intel_vrr_check_modeset(state); 7220 7221 ret = drm_atomic_helper_check_modeset(dev, &state->base); 7222 if (ret) 7223 goto fail; 7224 7225 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7226 ret = intel_async_flip_check_uapi(state, crtc); 7227 if (ret) 7228 return ret; 7229 } 7230 7231 ret = intel_bigjoiner_add_affected_crtcs(state); 7232 if (ret) 7233 goto fail; 7234 7235 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7236 new_crtc_state, i) { 7237 if (!intel_crtc_needs_modeset(new_crtc_state)) { 7238 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 7239 copy_bigjoiner_crtc_state_nomodeset(state, crtc); 7240 else 7241 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 7242 continue; 7243 } 7244 7245 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) { 7246 drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable); 7247 continue; 7248 } 7249 7250 ret = intel_crtc_prepare_cleared_state(state, crtc); 7251 if (ret) 7252 goto fail; 7253 7254 if (!new_crtc_state->hw.enable) 7255 continue; 7256 7257 ret = intel_modeset_pipe_config(state, crtc); 7258 if (ret) 7259 goto fail; 7260 7261 ret = intel_atomic_check_bigjoiner(state, crtc); 7262 if (ret) 7263 goto fail; 7264 } 7265 7266 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7267 new_crtc_state, i) { 7268 if (!intel_crtc_needs_modeset(new_crtc_state)) 7269 continue; 7270 7271 ret = intel_modeset_pipe_config_late(state, crtc); 7272 if (ret) 7273 goto fail; 7274 7275 intel_crtc_check_fastset(old_crtc_state, new_crtc_state); 7276 } 7277 7278 /** 7279 * Check if fastset is allowed by external dependencies like other 7280 * pipes and transcoders. 7281 * 7282 * Right now it only forces a fullmodeset when the MST master 7283 * transcoder did not changed but the pipe of the master transcoder 7284 * needs a fullmodeset so all slaves also needs to do a fullmodeset or 7285 * in case of port synced crtcs, if one of the synced crtcs 7286 * needs a full modeset, all other synced crtcs should be 7287 * forced a full modeset. 7288 */ 7289 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7290 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state)) 7291 continue; 7292 7293 if (intel_dp_mst_is_slave_trans(new_crtc_state)) { 7294 enum transcoder master = new_crtc_state->mst_master_transcoder; 7295 7296 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) { 7297 new_crtc_state->uapi.mode_changed = true; 7298 new_crtc_state->update_pipe = false; 7299 } 7300 } 7301 7302 if (is_trans_port_sync_mode(new_crtc_state)) { 7303 u8 trans = new_crtc_state->sync_mode_slaves_mask; 7304 7305 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER) 7306 trans |= BIT(new_crtc_state->master_transcoder); 7307 7308 if (intel_cpu_transcoders_need_modeset(state, trans)) { 7309 new_crtc_state->uapi.mode_changed = true; 7310 new_crtc_state->update_pipe = false; 7311 } 7312 } 7313 7314 if (new_crtc_state->bigjoiner_pipes) { 7315 if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) { 7316 new_crtc_state->uapi.mode_changed = true; 7317 new_crtc_state->update_pipe = false; 7318 } 7319 } 7320 } 7321 7322 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7323 new_crtc_state, i) { 7324 if (intel_crtc_needs_modeset(new_crtc_state)) { 7325 any_ms = true; 7326 continue; 7327 } 7328 7329 if (!new_crtc_state->update_pipe) 7330 continue; 7331 7332 intel_crtc_copy_fastset(old_crtc_state, new_crtc_state); 7333 } 7334 7335 if (any_ms && !check_digital_port_conflicts(state)) { 7336 drm_dbg_kms(&dev_priv->drm, 7337 "rejecting conflicting digital port configuration\n"); 7338 ret = -EINVAL; 7339 goto fail; 7340 } 7341 7342 ret = drm_dp_mst_atomic_check(&state->base); 7343 if (ret) 7344 goto fail; 7345 7346 ret = intel_atomic_check_planes(state); 7347 if (ret) 7348 goto fail; 7349 7350 ret = intel_compute_global_watermarks(state); 7351 if (ret) 7352 goto fail; 7353 7354 ret = intel_bw_atomic_check(state); 7355 if (ret) 7356 goto fail; 7357 7358 ret = intel_cdclk_atomic_check(state, &any_ms); 7359 if (ret) 7360 goto fail; 7361 7362 if (intel_any_crtc_needs_modeset(state)) 7363 any_ms = true; 7364 7365 if (any_ms) { 7366 ret = intel_modeset_checks(state); 7367 if (ret) 7368 goto fail; 7369 7370 ret = intel_modeset_calc_cdclk(state); 7371 if (ret) 7372 return ret; 7373 7374 intel_modeset_clear_plls(state); 7375 } 7376 7377 ret = intel_atomic_check_crtcs(state); 7378 if (ret) 7379 goto fail; 7380 7381 ret = intel_fbc_atomic_check(state); 7382 if (ret) 7383 goto fail; 7384 7385 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7386 new_crtc_state, i) { 7387 ret = intel_async_flip_check_hw(state, crtc); 7388 if (ret) 7389 goto fail; 7390 7391 if (!intel_crtc_needs_modeset(new_crtc_state) && 7392 !new_crtc_state->update_pipe) 7393 continue; 7394 7395 intel_dump_pipe_config(new_crtc_state, state, 7396 intel_crtc_needs_modeset(new_crtc_state) ? 7397 "[modeset]" : "[fastset]"); 7398 } 7399 7400 return 0; 7401 7402 fail: 7403 if (ret == -EDEADLK) 7404 return ret; 7405 7406 /* 7407 * FIXME would probably be nice to know which crtc specifically 7408 * caused the failure, in cases where we can pinpoint it. 7409 */ 7410 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7411 new_crtc_state, i) 7412 intel_dump_pipe_config(new_crtc_state, state, "[failed]"); 7413 7414 return ret; 7415 } 7416 7417 static int intel_atomic_prepare_commit(struct intel_atomic_state *state) 7418 { 7419 struct intel_crtc_state *crtc_state; 7420 struct intel_crtc *crtc; 7421 int i, ret; 7422 7423 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base); 7424 if (ret < 0) 7425 return ret; 7426 7427 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7428 bool mode_changed = intel_crtc_needs_modeset(crtc_state); 7429 7430 if (mode_changed || crtc_state->update_pipe || 7431 crtc_state->uapi.color_mgmt_changed) { 7432 intel_dsb_prepare(crtc_state); 7433 } 7434 } 7435 7436 return 0; 7437 } 7438 7439 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 7440 struct intel_crtc_state *crtc_state) 7441 { 7442 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 7443 7444 if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes) 7445 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 7446 7447 if (crtc_state->has_pch_encoder) { 7448 enum pipe pch_transcoder = 7449 intel_crtc_pch_transcoder(crtc); 7450 7451 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true); 7452 } 7453 } 7454 7455 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, 7456 const struct intel_crtc_state *new_crtc_state) 7457 { 7458 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 7459 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 7460 7461 /* 7462 * Update pipe size and adjust fitter if needed: the reason for this is 7463 * that in compute_mode_changes we check the native mode (not the pfit 7464 * mode) to see if we can flip rather than do a full mode set. In the 7465 * fastboot case, we'll flip, but if we don't update the pipesrc and 7466 * pfit state, we'll end up with a big fb scanned out into the wrong 7467 * sized surface. 7468 */ 7469 intel_set_pipe_src_size(new_crtc_state); 7470 7471 /* on skylake this is done by detaching scalers */ 7472 if (DISPLAY_VER(dev_priv) >= 9) { 7473 if (new_crtc_state->pch_pfit.enabled) 7474 skl_pfit_enable(new_crtc_state); 7475 } else if (HAS_PCH_SPLIT(dev_priv)) { 7476 if (new_crtc_state->pch_pfit.enabled) 7477 ilk_pfit_enable(new_crtc_state); 7478 else if (old_crtc_state->pch_pfit.enabled) 7479 ilk_pfit_disable(old_crtc_state); 7480 } 7481 7482 /* 7483 * The register is supposedly single buffered so perhaps 7484 * not 100% correct to do this here. But SKL+ calculate 7485 * this based on the adjust pixel rate so pfit changes do 7486 * affect it and so it must be updated for fastsets. 7487 * HSW/BDW only really need this here for fastboot, after 7488 * that the value should not change without a full modeset. 7489 */ 7490 if (DISPLAY_VER(dev_priv) >= 9 || 7491 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 7492 hsw_set_linetime_wm(new_crtc_state); 7493 } 7494 7495 static void commit_pipe_pre_planes(struct intel_atomic_state *state, 7496 struct intel_crtc *crtc) 7497 { 7498 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7499 const struct intel_crtc_state *old_crtc_state = 7500 intel_atomic_get_old_crtc_state(state, crtc); 7501 const struct intel_crtc_state *new_crtc_state = 7502 intel_atomic_get_new_crtc_state(state, crtc); 7503 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 7504 7505 /* 7506 * During modesets pipe configuration was programmed as the 7507 * CRTC was enabled. 7508 */ 7509 if (!modeset) { 7510 if (new_crtc_state->uapi.color_mgmt_changed || 7511 new_crtc_state->update_pipe) 7512 intel_color_commit_arm(new_crtc_state); 7513 7514 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 7515 bdw_set_pipemisc(new_crtc_state); 7516 7517 if (new_crtc_state->update_pipe) 7518 intel_pipe_fastset(old_crtc_state, new_crtc_state); 7519 } 7520 7521 intel_psr2_program_trans_man_trk_ctl(new_crtc_state); 7522 7523 intel_atomic_update_watermarks(state, crtc); 7524 } 7525 7526 static void commit_pipe_post_planes(struct intel_atomic_state *state, 7527 struct intel_crtc *crtc) 7528 { 7529 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7530 const struct intel_crtc_state *new_crtc_state = 7531 intel_atomic_get_new_crtc_state(state, crtc); 7532 7533 /* 7534 * Disable the scaler(s) after the plane(s) so that we don't 7535 * get a catastrophic underrun even if the two operations 7536 * end up happening in two different frames. 7537 */ 7538 if (DISPLAY_VER(dev_priv) >= 9 && 7539 !intel_crtc_needs_modeset(new_crtc_state)) 7540 skl_detach_scalers(new_crtc_state); 7541 } 7542 7543 static void intel_enable_crtc(struct intel_atomic_state *state, 7544 struct intel_crtc *crtc) 7545 { 7546 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7547 const struct intel_crtc_state *new_crtc_state = 7548 intel_atomic_get_new_crtc_state(state, crtc); 7549 7550 if (!intel_crtc_needs_modeset(new_crtc_state)) 7551 return; 7552 7553 intel_crtc_update_active_timings(new_crtc_state); 7554 7555 dev_priv->display->crtc_enable(state, crtc); 7556 7557 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 7558 return; 7559 7560 /* vblanks work again, re-enable pipe CRC. */ 7561 intel_crtc_enable_pipe_crc(crtc); 7562 } 7563 7564 static void intel_update_crtc(struct intel_atomic_state *state, 7565 struct intel_crtc *crtc) 7566 { 7567 struct drm_i915_private *i915 = to_i915(state->base.dev); 7568 const struct intel_crtc_state *old_crtc_state = 7569 intel_atomic_get_old_crtc_state(state, crtc); 7570 struct intel_crtc_state *new_crtc_state = 7571 intel_atomic_get_new_crtc_state(state, crtc); 7572 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 7573 7574 if (!modeset) { 7575 if (new_crtc_state->preload_luts && 7576 (new_crtc_state->uapi.color_mgmt_changed || 7577 new_crtc_state->update_pipe)) 7578 intel_color_load_luts(new_crtc_state); 7579 7580 intel_pre_plane_update(state, crtc); 7581 7582 if (new_crtc_state->update_pipe) 7583 intel_encoders_update_pipe(state, crtc); 7584 7585 if (DISPLAY_VER(i915) >= 11 && 7586 new_crtc_state->update_pipe) 7587 icl_set_pipe_chicken(new_crtc_state); 7588 } 7589 7590 intel_fbc_update(state, crtc); 7591 7592 if (!modeset && 7593 (new_crtc_state->uapi.color_mgmt_changed || 7594 new_crtc_state->update_pipe)) 7595 intel_color_commit_noarm(new_crtc_state); 7596 7597 intel_crtc_planes_update_noarm(state, crtc); 7598 7599 /* Perform vblank evasion around commit operation */ 7600 intel_pipe_update_start(new_crtc_state); 7601 7602 commit_pipe_pre_planes(state, crtc); 7603 7604 intel_crtc_planes_update_arm(state, crtc); 7605 7606 commit_pipe_post_planes(state, crtc); 7607 7608 intel_pipe_update_end(new_crtc_state); 7609 7610 /* 7611 * We usually enable FIFO underrun interrupts as part of the 7612 * CRTC enable sequence during modesets. But when we inherit a 7613 * valid pipe configuration from the BIOS we need to take care 7614 * of enabling them on the CRTC's first fastset. 7615 */ 7616 if (new_crtc_state->update_pipe && !modeset && 7617 old_crtc_state->inherited) 7618 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state); 7619 } 7620 7621 static void intel_old_crtc_state_disables(struct intel_atomic_state *state, 7622 struct intel_crtc_state *old_crtc_state, 7623 struct intel_crtc_state *new_crtc_state, 7624 struct intel_crtc *crtc) 7625 { 7626 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7627 7628 /* 7629 * We need to disable pipe CRC before disabling the pipe, 7630 * or we race against vblank off. 7631 */ 7632 intel_crtc_disable_pipe_crc(crtc); 7633 7634 dev_priv->display->crtc_disable(state, crtc); 7635 crtc->active = false; 7636 intel_fbc_disable(crtc); 7637 intel_disable_shared_dpll(old_crtc_state); 7638 7639 /* FIXME unify this for all platforms */ 7640 if (!new_crtc_state->hw.active && 7641 !HAS_GMCH(dev_priv)) 7642 intel_initial_watermarks(state, crtc); 7643 } 7644 7645 static void intel_commit_modeset_disables(struct intel_atomic_state *state) 7646 { 7647 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 7648 struct intel_crtc *crtc; 7649 u32 handled = 0; 7650 int i; 7651 7652 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7653 new_crtc_state, i) { 7654 if (!intel_crtc_needs_modeset(new_crtc_state)) 7655 continue; 7656 7657 if (!old_crtc_state->hw.active) 7658 continue; 7659 7660 intel_pre_plane_update(state, crtc); 7661 intel_crtc_disable_planes(state, crtc); 7662 } 7663 7664 /* Only disable port sync and MST slaves */ 7665 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7666 new_crtc_state, i) { 7667 if (!intel_crtc_needs_modeset(new_crtc_state)) 7668 continue; 7669 7670 if (!old_crtc_state->hw.active) 7671 continue; 7672 7673 /* In case of Transcoder port Sync master slave CRTCs can be 7674 * assigned in any order and we need to make sure that 7675 * slave CRTCs are disabled first and then master CRTC since 7676 * Slave vblanks are masked till Master Vblanks. 7677 */ 7678 if (!is_trans_port_sync_slave(old_crtc_state) && 7679 !intel_dp_mst_is_slave_trans(old_crtc_state) && 7680 !intel_crtc_is_bigjoiner_slave(old_crtc_state)) 7681 continue; 7682 7683 intel_old_crtc_state_disables(state, old_crtc_state, 7684 new_crtc_state, crtc); 7685 handled |= BIT(crtc->pipe); 7686 } 7687 7688 /* Disable everything else left on */ 7689 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7690 new_crtc_state, i) { 7691 if (!intel_crtc_needs_modeset(new_crtc_state) || 7692 (handled & BIT(crtc->pipe))) 7693 continue; 7694 7695 if (!old_crtc_state->hw.active) 7696 continue; 7697 7698 intel_old_crtc_state_disables(state, old_crtc_state, 7699 new_crtc_state, crtc); 7700 } 7701 } 7702 7703 static void intel_commit_modeset_enables(struct intel_atomic_state *state) 7704 { 7705 struct intel_crtc_state *new_crtc_state; 7706 struct intel_crtc *crtc; 7707 int i; 7708 7709 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7710 if (!new_crtc_state->hw.active) 7711 continue; 7712 7713 intel_enable_crtc(state, crtc); 7714 intel_update_crtc(state, crtc); 7715 } 7716 } 7717 7718 static void skl_commit_modeset_enables(struct intel_atomic_state *state) 7719 { 7720 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7721 struct intel_crtc *crtc; 7722 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7723 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; 7724 u8 update_pipes = 0, modeset_pipes = 0; 7725 int i; 7726 7727 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7728 enum pipe pipe = crtc->pipe; 7729 7730 if (!new_crtc_state->hw.active) 7731 continue; 7732 7733 /* ignore allocations for crtc's that have been turned off. */ 7734 if (!intel_crtc_needs_modeset(new_crtc_state)) { 7735 entries[pipe] = old_crtc_state->wm.skl.ddb; 7736 update_pipes |= BIT(pipe); 7737 } else { 7738 modeset_pipes |= BIT(pipe); 7739 } 7740 } 7741 7742 /* 7743 * Whenever the number of active pipes changes, we need to make sure we 7744 * update the pipes in the right order so that their ddb allocations 7745 * never overlap with each other between CRTC updates. Otherwise we'll 7746 * cause pipe underruns and other bad stuff. 7747 * 7748 * So first lets enable all pipes that do not need a fullmodeset as 7749 * those don't have any external dependency. 7750 */ 7751 while (update_pipes) { 7752 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7753 new_crtc_state, i) { 7754 enum pipe pipe = crtc->pipe; 7755 7756 if ((update_pipes & BIT(pipe)) == 0) 7757 continue; 7758 7759 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 7760 entries, I915_MAX_PIPES, pipe)) 7761 continue; 7762 7763 entries[pipe] = new_crtc_state->wm.skl.ddb; 7764 update_pipes &= ~BIT(pipe); 7765 7766 intel_update_crtc(state, crtc); 7767 7768 /* 7769 * If this is an already active pipe, it's DDB changed, 7770 * and this isn't the last pipe that needs updating 7771 * then we need to wait for a vblank to pass for the 7772 * new ddb allocation to take effect. 7773 */ 7774 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, 7775 &old_crtc_state->wm.skl.ddb) && 7776 (update_pipes | modeset_pipes)) 7777 intel_crtc_wait_for_next_vblank(crtc); 7778 } 7779 } 7780 7781 update_pipes = modeset_pipes; 7782 7783 /* 7784 * Enable all pipes that needs a modeset and do not depends on other 7785 * pipes 7786 */ 7787 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7788 enum pipe pipe = crtc->pipe; 7789 7790 if ((modeset_pipes & BIT(pipe)) == 0) 7791 continue; 7792 7793 if (intel_dp_mst_is_slave_trans(new_crtc_state) || 7794 is_trans_port_sync_master(new_crtc_state) || 7795 intel_crtc_is_bigjoiner_master(new_crtc_state)) 7796 continue; 7797 7798 modeset_pipes &= ~BIT(pipe); 7799 7800 intel_enable_crtc(state, crtc); 7801 } 7802 7803 /* 7804 * Then we enable all remaining pipes that depend on other 7805 * pipes: MST slaves and port sync masters, big joiner master 7806 */ 7807 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7808 enum pipe pipe = crtc->pipe; 7809 7810 if ((modeset_pipes & BIT(pipe)) == 0) 7811 continue; 7812 7813 modeset_pipes &= ~BIT(pipe); 7814 7815 intel_enable_crtc(state, crtc); 7816 } 7817 7818 /* 7819 * Finally we do the plane updates/etc. for all pipes that got enabled. 7820 */ 7821 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7822 enum pipe pipe = crtc->pipe; 7823 7824 if ((update_pipes & BIT(pipe)) == 0) 7825 continue; 7826 7827 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 7828 entries, I915_MAX_PIPES, pipe)); 7829 7830 entries[pipe] = new_crtc_state->wm.skl.ddb; 7831 update_pipes &= ~BIT(pipe); 7832 7833 intel_update_crtc(state, crtc); 7834 } 7835 7836 drm_WARN_ON(&dev_priv->drm, modeset_pipes); 7837 drm_WARN_ON(&dev_priv->drm, update_pipes); 7838 } 7839 7840 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) 7841 { 7842 struct intel_atomic_state *state, *next; 7843 struct llist_node *freed; 7844 7845 freed = llist_del_all(&dev_priv->atomic_helper.free_list); 7846 llist_for_each_entry_safe(state, next, freed, freed) 7847 drm_atomic_state_put(&state->base); 7848 } 7849 7850 static void intel_atomic_helper_free_state_worker(struct work_struct *work) 7851 { 7852 struct drm_i915_private *dev_priv = 7853 container_of(work, typeof(*dev_priv), atomic_helper.free_work); 7854 7855 intel_atomic_helper_free_state(dev_priv); 7856 } 7857 7858 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) 7859 { 7860 struct wait_queue_entry wait_fence, wait_reset; 7861 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); 7862 7863 init_wait_entry(&wait_fence, 0); 7864 init_wait_entry(&wait_reset, 0); 7865 for (;;) { 7866 prepare_to_wait(&intel_state->commit_ready.wait, 7867 &wait_fence, TASK_UNINTERRUPTIBLE); 7868 prepare_to_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 7869 I915_RESET_MODESET), 7870 &wait_reset, TASK_UNINTERRUPTIBLE); 7871 7872 7873 if (i915_sw_fence_done(&intel_state->commit_ready) || 7874 test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags)) 7875 break; 7876 7877 schedule(); 7878 } 7879 finish_wait(&intel_state->commit_ready.wait, &wait_fence); 7880 finish_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 7881 I915_RESET_MODESET), 7882 &wait_reset); 7883 } 7884 7885 static void intel_cleanup_dsbs(struct intel_atomic_state *state) 7886 { 7887 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7888 struct intel_crtc *crtc; 7889 int i; 7890 7891 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7892 new_crtc_state, i) 7893 intel_dsb_cleanup(old_crtc_state); 7894 } 7895 7896 static void intel_atomic_cleanup_work(struct work_struct *work) 7897 { 7898 struct intel_atomic_state *state = 7899 container_of(work, struct intel_atomic_state, base.commit_work); 7900 struct drm_i915_private *i915 = to_i915(state->base.dev); 7901 7902 intel_cleanup_dsbs(state); 7903 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base); 7904 drm_atomic_helper_commit_cleanup_done(&state->base); 7905 drm_atomic_state_put(&state->base); 7906 7907 intel_atomic_helper_free_state(i915); 7908 } 7909 7910 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state) 7911 { 7912 struct drm_i915_private *i915 = to_i915(state->base.dev); 7913 struct intel_plane *plane; 7914 struct intel_plane_state *plane_state; 7915 int i; 7916 7917 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 7918 struct drm_framebuffer *fb = plane_state->hw.fb; 7919 int cc_plane; 7920 int ret; 7921 7922 if (!fb) 7923 continue; 7924 7925 cc_plane = intel_fb_rc_ccs_cc_plane(fb); 7926 if (cc_plane < 0) 7927 continue; 7928 7929 /* 7930 * The layout of the fast clear color value expected by HW 7931 * (the DRM ABI requiring this value to be located in fb at 7932 * offset 0 of cc plane, plane #2 previous generations or 7933 * plane #1 for flat ccs): 7934 * - 4 x 4 bytes per-channel value 7935 * (in surface type specific float/int format provided by the fb user) 7936 * - 8 bytes native color value used by the display 7937 * (converted/written by GPU during a fast clear operation using the 7938 * above per-channel values) 7939 * 7940 * The commit's FB prepare hook already ensured that FB obj is pinned and the 7941 * caller made sure that the object is synced wrt. the related color clear value 7942 * GPU write on it. 7943 */ 7944 ret = i915_gem_object_read_from_page(intel_fb_obj(fb), 7945 fb->offsets[cc_plane] + 16, 7946 &plane_state->ccval, 7947 sizeof(plane_state->ccval)); 7948 /* The above could only fail if the FB obj has an unexpected backing store type. */ 7949 drm_WARN_ON(&i915->drm, ret); 7950 } 7951 } 7952 7953 static void intel_atomic_commit_tail(struct intel_atomic_state *state) 7954 { 7955 struct drm_device *dev = state->base.dev; 7956 struct drm_i915_private *dev_priv = to_i915(dev); 7957 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 7958 struct intel_crtc *crtc; 7959 struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {}; 7960 intel_wakeref_t wakeref = 0; 7961 int i; 7962 7963 intel_atomic_commit_fence_wait(state); 7964 7965 drm_atomic_helper_wait_for_dependencies(&state->base); 7966 7967 if (state->modeset) 7968 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); 7969 7970 intel_atomic_prepare_plane_clear_colors(state); 7971 7972 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7973 new_crtc_state, i) { 7974 if (intel_crtc_needs_modeset(new_crtc_state) || 7975 new_crtc_state->update_pipe) { 7976 modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]); 7977 } 7978 } 7979 7980 intel_commit_modeset_disables(state); 7981 7982 /* FIXME: Eventually get rid of our crtc->config pointer */ 7983 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7984 crtc->config = new_crtc_state; 7985 7986 if (state->modeset) { 7987 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base); 7988 7989 intel_set_cdclk_pre_plane_update(state); 7990 7991 intel_modeset_verify_disabled(dev_priv, state); 7992 } 7993 7994 intel_sagv_pre_plane_update(state); 7995 7996 /* Complete the events for pipes that have now been disabled */ 7997 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7998 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 7999 8000 /* Complete events for now disable pipes here. */ 8001 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) { 8002 spin_lock_irq(&dev->event_lock); 8003 drm_crtc_send_vblank_event(&crtc->base, 8004 new_crtc_state->uapi.event); 8005 spin_unlock_irq(&dev->event_lock); 8006 8007 new_crtc_state->uapi.event = NULL; 8008 } 8009 } 8010 8011 intel_encoders_update_prepare(state); 8012 8013 intel_dbuf_pre_plane_update(state); 8014 intel_mbus_dbox_update(state); 8015 8016 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8017 if (new_crtc_state->do_async_flip) 8018 intel_crtc_enable_flip_done(state, crtc); 8019 } 8020 8021 /* Now enable the clocks, plane, pipe, and connectors that we set up. */ 8022 dev_priv->display->commit_modeset_enables(state); 8023 8024 intel_encoders_update_complete(state); 8025 8026 if (state->modeset) 8027 intel_set_cdclk_post_plane_update(state); 8028 8029 intel_wait_for_vblank_workers(state); 8030 8031 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here 8032 * already, but still need the state for the delayed optimization. To 8033 * fix this: 8034 * - wrap the optimization/post_plane_update stuff into a per-crtc work. 8035 * - schedule that vblank worker _before_ calling hw_done 8036 * - at the start of commit_tail, cancel it _synchrously 8037 * - switch over to the vblank wait helper in the core after that since 8038 * we don't need out special handling any more. 8039 */ 8040 drm_atomic_helper_wait_for_flip_done(dev, &state->base); 8041 8042 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8043 if (new_crtc_state->do_async_flip) 8044 intel_crtc_disable_flip_done(state, crtc); 8045 } 8046 8047 /* 8048 * Now that the vblank has passed, we can go ahead and program the 8049 * optimal watermarks on platforms that need two-step watermark 8050 * programming. 8051 * 8052 * TODO: Move this (and other cleanup) to an async worker eventually. 8053 */ 8054 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8055 new_crtc_state, i) { 8056 /* 8057 * Gen2 reports pipe underruns whenever all planes are disabled. 8058 * So re-enable underrun reporting after some planes get enabled. 8059 * 8060 * We do this before .optimize_watermarks() so that we have a 8061 * chance of catching underruns with the intermediate watermarks 8062 * vs. the new plane configuration. 8063 */ 8064 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state)) 8065 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 8066 8067 intel_optimize_watermarks(state, crtc); 8068 } 8069 8070 intel_dbuf_post_plane_update(state); 8071 intel_psr_post_plane_update(state); 8072 8073 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 8074 intel_post_plane_update(state, crtc); 8075 8076 modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]); 8077 8078 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state); 8079 8080 /* 8081 * DSB cleanup is done in cleanup_work aligning with framebuffer 8082 * cleanup. So copy and reset the dsb structure to sync with 8083 * commit_done and later do dsb cleanup in cleanup_work. 8084 */ 8085 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb); 8086 } 8087 8088 /* Underruns don't always raise interrupts, so check manually */ 8089 intel_check_cpu_fifo_underruns(dev_priv); 8090 intel_check_pch_fifo_underruns(dev_priv); 8091 8092 if (state->modeset) 8093 intel_verify_planes(state); 8094 8095 intel_sagv_post_plane_update(state); 8096 8097 drm_atomic_helper_commit_hw_done(&state->base); 8098 8099 if (state->modeset) { 8100 /* As one of the primary mmio accessors, KMS has a high 8101 * likelihood of triggering bugs in unclaimed access. After we 8102 * finish modesetting, see if an error has been flagged, and if 8103 * so enable debugging for the next modeset - and hope we catch 8104 * the culprit. 8105 */ 8106 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); 8107 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref); 8108 } 8109 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 8110 8111 /* 8112 * Defer the cleanup of the old state to a separate worker to not 8113 * impede the current task (userspace for blocking modesets) that 8114 * are executed inline. For out-of-line asynchronous modesets/flips, 8115 * deferring to a new worker seems overkill, but we would place a 8116 * schedule point (cond_resched()) here anyway to keep latencies 8117 * down. 8118 */ 8119 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work); 8120 queue_work(system_highpri_wq, &state->base.commit_work); 8121 } 8122 8123 static void intel_atomic_commit_work(struct work_struct *work) 8124 { 8125 struct intel_atomic_state *state = 8126 container_of(work, struct intel_atomic_state, base.commit_work); 8127 8128 intel_atomic_commit_tail(state); 8129 } 8130 8131 static int 8132 intel_atomic_commit_ready(struct i915_sw_fence *fence, 8133 enum i915_sw_fence_notify notify) 8134 { 8135 struct intel_atomic_state *state = 8136 container_of(fence, struct intel_atomic_state, commit_ready); 8137 8138 switch (notify) { 8139 case FENCE_COMPLETE: 8140 /* we do blocking waits in the worker, nothing to do here */ 8141 break; 8142 case FENCE_FREE: 8143 { 8144 struct intel_atomic_helper *helper = 8145 &to_i915(state->base.dev)->atomic_helper; 8146 8147 if (llist_add(&state->freed, &helper->free_list)) 8148 schedule_work(&helper->free_work); 8149 break; 8150 } 8151 } 8152 8153 return NOTIFY_DONE; 8154 } 8155 8156 static void intel_atomic_track_fbs(struct intel_atomic_state *state) 8157 { 8158 struct intel_plane_state *old_plane_state, *new_plane_state; 8159 struct intel_plane *plane; 8160 int i; 8161 8162 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 8163 new_plane_state, i) 8164 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), 8165 to_intel_frontbuffer(new_plane_state->hw.fb), 8166 plane->frontbuffer_bit); 8167 } 8168 8169 static int intel_atomic_commit(struct drm_device *dev, 8170 struct drm_atomic_state *_state, 8171 bool nonblock) 8172 { 8173 struct intel_atomic_state *state = to_intel_atomic_state(_state); 8174 struct drm_i915_private *dev_priv = to_i915(dev); 8175 int ret = 0; 8176 8177 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 8178 8179 drm_atomic_state_get(&state->base); 8180 i915_sw_fence_init(&state->commit_ready, 8181 intel_atomic_commit_ready); 8182 8183 /* 8184 * The intel_legacy_cursor_update() fast path takes care 8185 * of avoiding the vblank waits for simple cursor 8186 * movement and flips. For cursor on/off and size changes, 8187 * we want to perform the vblank waits so that watermark 8188 * updates happen during the correct frames. Gen9+ have 8189 * double buffered watermarks and so shouldn't need this. 8190 * 8191 * Unset state->legacy_cursor_update before the call to 8192 * drm_atomic_helper_setup_commit() because otherwise 8193 * drm_atomic_helper_wait_for_flip_done() is a noop and 8194 * we get FIFO underruns because we didn't wait 8195 * for vblank. 8196 * 8197 * FIXME doing watermarks and fb cleanup from a vblank worker 8198 * (assuming we had any) would solve these problems. 8199 */ 8200 if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) { 8201 struct intel_crtc_state *new_crtc_state; 8202 struct intel_crtc *crtc; 8203 int i; 8204 8205 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 8206 if (new_crtc_state->wm.need_postvbl_update || 8207 new_crtc_state->update_wm_post) 8208 state->base.legacy_cursor_update = false; 8209 } 8210 8211 ret = intel_atomic_prepare_commit(state); 8212 if (ret) { 8213 drm_dbg_atomic(&dev_priv->drm, 8214 "Preparing state failed with %i\n", ret); 8215 i915_sw_fence_commit(&state->commit_ready); 8216 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 8217 return ret; 8218 } 8219 8220 ret = drm_atomic_helper_setup_commit(&state->base, nonblock); 8221 if (!ret) 8222 ret = drm_atomic_helper_swap_state(&state->base, true); 8223 if (!ret) 8224 intel_atomic_swap_global_state(state); 8225 8226 if (ret) { 8227 struct intel_crtc_state *new_crtc_state; 8228 struct intel_crtc *crtc; 8229 int i; 8230 8231 i915_sw_fence_commit(&state->commit_ready); 8232 8233 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 8234 intel_dsb_cleanup(new_crtc_state); 8235 8236 drm_atomic_helper_cleanup_planes(dev, &state->base); 8237 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 8238 return ret; 8239 } 8240 intel_shared_dpll_swap_state(state); 8241 intel_atomic_track_fbs(state); 8242 8243 drm_atomic_state_get(&state->base); 8244 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work); 8245 8246 i915_sw_fence_commit(&state->commit_ready); 8247 if (nonblock && state->modeset) { 8248 queue_work(dev_priv->modeset_wq, &state->base.commit_work); 8249 } else if (nonblock) { 8250 queue_work(dev_priv->flip_wq, &state->base.commit_work); 8251 } else { 8252 if (state->modeset) 8253 flush_workqueue(dev_priv->modeset_wq); 8254 intel_atomic_commit_tail(state); 8255 } 8256 8257 return 0; 8258 } 8259 8260 /** 8261 * intel_plane_destroy - destroy a plane 8262 * @plane: plane to destroy 8263 * 8264 * Common destruction function for all types of planes (primary, cursor, 8265 * sprite). 8266 */ 8267 void intel_plane_destroy(struct drm_plane *plane) 8268 { 8269 drm_plane_cleanup(plane); 8270 kfree(to_intel_plane(plane)); 8271 } 8272 8273 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv) 8274 { 8275 struct intel_plane *plane; 8276 8277 for_each_intel_plane(&dev_priv->drm, plane) { 8278 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, 8279 plane->pipe); 8280 8281 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base); 8282 } 8283 } 8284 8285 8286 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 8287 struct drm_file *file) 8288 { 8289 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; 8290 struct drm_crtc *drmmode_crtc; 8291 struct intel_crtc *crtc; 8292 8293 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id); 8294 if (!drmmode_crtc) 8295 return -ENOENT; 8296 8297 crtc = to_intel_crtc(drmmode_crtc); 8298 pipe_from_crtc_id->pipe = crtc->pipe; 8299 8300 return 0; 8301 } 8302 8303 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder) 8304 { 8305 struct drm_device *dev = encoder->base.dev; 8306 struct intel_encoder *source_encoder; 8307 u32 possible_clones = 0; 8308 8309 for_each_intel_encoder(dev, source_encoder) { 8310 if (encoders_cloneable(encoder, source_encoder)) 8311 possible_clones |= drm_encoder_mask(&source_encoder->base); 8312 } 8313 8314 return possible_clones; 8315 } 8316 8317 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder) 8318 { 8319 struct drm_device *dev = encoder->base.dev; 8320 struct intel_crtc *crtc; 8321 u32 possible_crtcs = 0; 8322 8323 for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask) 8324 possible_crtcs |= drm_crtc_mask(&crtc->base); 8325 8326 return possible_crtcs; 8327 } 8328 8329 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv) 8330 { 8331 if (!IS_MOBILE(dev_priv)) 8332 return false; 8333 8334 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0) 8335 return false; 8336 8337 if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE)) 8338 return false; 8339 8340 return true; 8341 } 8342 8343 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv) 8344 { 8345 if (DISPLAY_VER(dev_priv) >= 9) 8346 return false; 8347 8348 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) 8349 return false; 8350 8351 if (HAS_PCH_LPT_H(dev_priv) && 8352 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) 8353 return false; 8354 8355 /* DDI E can't be used if DDI A requires 4 lanes */ 8356 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 8357 return false; 8358 8359 if (!dev_priv->vbt.int_crt_support) 8360 return false; 8361 8362 return true; 8363 } 8364 8365 static void intel_setup_outputs(struct drm_i915_private *dev_priv) 8366 { 8367 struct intel_encoder *encoder; 8368 bool dpd_is_edp = false; 8369 8370 intel_pps_unlock_regs_wa(dev_priv); 8371 8372 if (!HAS_DISPLAY(dev_priv)) 8373 return; 8374 8375 if (IS_DG2(dev_priv)) { 8376 intel_ddi_init(dev_priv, PORT_A); 8377 intel_ddi_init(dev_priv, PORT_B); 8378 intel_ddi_init(dev_priv, PORT_C); 8379 intel_ddi_init(dev_priv, PORT_D_XELPD); 8380 intel_ddi_init(dev_priv, PORT_TC1); 8381 } else if (IS_ALDERLAKE_P(dev_priv)) { 8382 intel_ddi_init(dev_priv, PORT_A); 8383 intel_ddi_init(dev_priv, PORT_B); 8384 intel_ddi_init(dev_priv, PORT_TC1); 8385 intel_ddi_init(dev_priv, PORT_TC2); 8386 intel_ddi_init(dev_priv, PORT_TC3); 8387 intel_ddi_init(dev_priv, PORT_TC4); 8388 icl_dsi_init(dev_priv); 8389 } else if (IS_ALDERLAKE_S(dev_priv)) { 8390 intel_ddi_init(dev_priv, PORT_A); 8391 intel_ddi_init(dev_priv, PORT_TC1); 8392 intel_ddi_init(dev_priv, PORT_TC2); 8393 intel_ddi_init(dev_priv, PORT_TC3); 8394 intel_ddi_init(dev_priv, PORT_TC4); 8395 } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) { 8396 intel_ddi_init(dev_priv, PORT_A); 8397 intel_ddi_init(dev_priv, PORT_B); 8398 intel_ddi_init(dev_priv, PORT_TC1); 8399 intel_ddi_init(dev_priv, PORT_TC2); 8400 } else if (DISPLAY_VER(dev_priv) >= 12) { 8401 intel_ddi_init(dev_priv, PORT_A); 8402 intel_ddi_init(dev_priv, PORT_B); 8403 intel_ddi_init(dev_priv, PORT_TC1); 8404 intel_ddi_init(dev_priv, PORT_TC2); 8405 intel_ddi_init(dev_priv, PORT_TC3); 8406 intel_ddi_init(dev_priv, PORT_TC4); 8407 intel_ddi_init(dev_priv, PORT_TC5); 8408 intel_ddi_init(dev_priv, PORT_TC6); 8409 icl_dsi_init(dev_priv); 8410 } else if (IS_JSL_EHL(dev_priv)) { 8411 intel_ddi_init(dev_priv, PORT_A); 8412 intel_ddi_init(dev_priv, PORT_B); 8413 intel_ddi_init(dev_priv, PORT_C); 8414 intel_ddi_init(dev_priv, PORT_D); 8415 icl_dsi_init(dev_priv); 8416 } else if (DISPLAY_VER(dev_priv) == 11) { 8417 intel_ddi_init(dev_priv, PORT_A); 8418 intel_ddi_init(dev_priv, PORT_B); 8419 intel_ddi_init(dev_priv, PORT_C); 8420 intel_ddi_init(dev_priv, PORT_D); 8421 intel_ddi_init(dev_priv, PORT_E); 8422 intel_ddi_init(dev_priv, PORT_F); 8423 icl_dsi_init(dev_priv); 8424 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 8425 intel_ddi_init(dev_priv, PORT_A); 8426 intel_ddi_init(dev_priv, PORT_B); 8427 intel_ddi_init(dev_priv, PORT_C); 8428 vlv_dsi_init(dev_priv); 8429 } else if (DISPLAY_VER(dev_priv) >= 9) { 8430 intel_ddi_init(dev_priv, PORT_A); 8431 intel_ddi_init(dev_priv, PORT_B); 8432 intel_ddi_init(dev_priv, PORT_C); 8433 intel_ddi_init(dev_priv, PORT_D); 8434 intel_ddi_init(dev_priv, PORT_E); 8435 } else if (HAS_DDI(dev_priv)) { 8436 u32 found; 8437 8438 if (intel_ddi_crt_present(dev_priv)) 8439 intel_crt_init(dev_priv); 8440 8441 /* Haswell uses DDI functions to detect digital outputs. */ 8442 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 8443 if (found) 8444 intel_ddi_init(dev_priv, PORT_A); 8445 8446 found = intel_de_read(dev_priv, SFUSE_STRAP); 8447 if (found & SFUSE_STRAP_DDIB_DETECTED) 8448 intel_ddi_init(dev_priv, PORT_B); 8449 if (found & SFUSE_STRAP_DDIC_DETECTED) 8450 intel_ddi_init(dev_priv, PORT_C); 8451 if (found & SFUSE_STRAP_DDID_DETECTED) 8452 intel_ddi_init(dev_priv, PORT_D); 8453 if (found & SFUSE_STRAP_DDIF_DETECTED) 8454 intel_ddi_init(dev_priv, PORT_F); 8455 } else if (HAS_PCH_SPLIT(dev_priv)) { 8456 int found; 8457 8458 /* 8459 * intel_edp_init_connector() depends on this completing first, 8460 * to prevent the registration of both eDP and LVDS and the 8461 * incorrect sharing of the PPS. 8462 */ 8463 intel_lvds_init(dev_priv); 8464 intel_crt_init(dev_priv); 8465 8466 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D); 8467 8468 if (ilk_has_edp_a(dev_priv)) 8469 g4x_dp_init(dev_priv, DP_A, PORT_A); 8470 8471 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) { 8472 /* PCH SDVOB multiplex with HDMIB */ 8473 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); 8474 if (!found) 8475 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); 8476 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED)) 8477 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B); 8478 } 8479 8480 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED) 8481 g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); 8482 8483 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED) 8484 g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D); 8485 8486 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED) 8487 g4x_dp_init(dev_priv, PCH_DP_C, PORT_C); 8488 8489 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED) 8490 g4x_dp_init(dev_priv, PCH_DP_D, PORT_D); 8491 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 8492 bool has_edp, has_port; 8493 8494 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support) 8495 intel_crt_init(dev_priv); 8496 8497 /* 8498 * The DP_DETECTED bit is the latched state of the DDC 8499 * SDA pin at boot. However since eDP doesn't require DDC 8500 * (no way to plug in a DP->HDMI dongle) the DDC pins for 8501 * eDP ports may have been muxed to an alternate function. 8502 * Thus we can't rely on the DP_DETECTED bit alone to detect 8503 * eDP ports. Consult the VBT as well as DP_DETECTED to 8504 * detect eDP ports. 8505 * 8506 * Sadly the straps seem to be missing sometimes even for HDMI 8507 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap 8508 * and VBT for the presence of the port. Additionally we can't 8509 * trust the port type the VBT declares as we've seen at least 8510 * HDMI ports that the VBT claim are DP or eDP. 8511 */ 8512 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B); 8513 has_port = intel_bios_is_port_present(dev_priv, PORT_B); 8514 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port) 8515 has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B); 8516 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) 8517 g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); 8518 8519 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C); 8520 has_port = intel_bios_is_port_present(dev_priv, PORT_C); 8521 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port) 8522 has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C); 8523 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) 8524 g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); 8525 8526 if (IS_CHERRYVIEW(dev_priv)) { 8527 /* 8528 * eDP not supported on port D, 8529 * so no need to worry about it 8530 */ 8531 has_port = intel_bios_is_port_present(dev_priv, PORT_D); 8532 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port) 8533 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D); 8534 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port) 8535 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D); 8536 } 8537 8538 vlv_dsi_init(dev_priv); 8539 } else if (IS_PINEVIEW(dev_priv)) { 8540 intel_lvds_init(dev_priv); 8541 intel_crt_init(dev_priv); 8542 } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) { 8543 bool found = false; 8544 8545 if (IS_MOBILE(dev_priv)) 8546 intel_lvds_init(dev_priv); 8547 8548 intel_crt_init(dev_priv); 8549 8550 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 8551 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n"); 8552 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); 8553 if (!found && IS_G4X(dev_priv)) { 8554 drm_dbg_kms(&dev_priv->drm, 8555 "probing HDMI on SDVOB\n"); 8556 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); 8557 } 8558 8559 if (!found && IS_G4X(dev_priv)) 8560 g4x_dp_init(dev_priv, DP_B, PORT_B); 8561 } 8562 8563 /* Before G4X SDVOC doesn't have its own detect register */ 8564 8565 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 8566 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n"); 8567 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); 8568 } 8569 8570 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) { 8571 8572 if (IS_G4X(dev_priv)) { 8573 drm_dbg_kms(&dev_priv->drm, 8574 "probing HDMI on SDVOC\n"); 8575 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); 8576 } 8577 if (IS_G4X(dev_priv)) 8578 g4x_dp_init(dev_priv, DP_C, PORT_C); 8579 } 8580 8581 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED)) 8582 g4x_dp_init(dev_priv, DP_D, PORT_D); 8583 8584 if (SUPPORTS_TV(dev_priv)) 8585 intel_tv_init(dev_priv); 8586 } else if (DISPLAY_VER(dev_priv) == 2) { 8587 if (IS_I85X(dev_priv)) 8588 intel_lvds_init(dev_priv); 8589 8590 intel_crt_init(dev_priv); 8591 intel_dvo_init(dev_priv); 8592 } 8593 8594 for_each_intel_encoder(&dev_priv->drm, encoder) { 8595 encoder->base.possible_crtcs = 8596 intel_encoder_possible_crtcs(encoder); 8597 encoder->base.possible_clones = 8598 intel_encoder_possible_clones(encoder); 8599 } 8600 8601 intel_init_pch_refclk(dev_priv); 8602 8603 drm_helper_move_panel_connectors_to_head(&dev_priv->drm); 8604 } 8605 8606 static enum drm_mode_status 8607 intel_mode_valid(struct drm_device *dev, 8608 const struct drm_display_mode *mode) 8609 { 8610 struct drm_i915_private *dev_priv = to_i915(dev); 8611 int hdisplay_max, htotal_max; 8612 int vdisplay_max, vtotal_max; 8613 8614 /* 8615 * Can't reject DBLSCAN here because Xorg ddxen can add piles 8616 * of DBLSCAN modes to the output's mode list when they detect 8617 * the scaling mode property on the connector. And they don't 8618 * ask the kernel to validate those modes in any way until 8619 * modeset time at which point the client gets a protocol error. 8620 * So in order to not upset those clients we silently ignore the 8621 * DBLSCAN flag on such connectors. For other connectors we will 8622 * reject modes with the DBLSCAN flag in encoder->compute_config(). 8623 * And we always reject DBLSCAN modes in connector->mode_valid() 8624 * as we never want such modes on the connector's mode list. 8625 */ 8626 8627 if (mode->vscan > 1) 8628 return MODE_NO_VSCAN; 8629 8630 if (mode->flags & DRM_MODE_FLAG_HSKEW) 8631 return MODE_H_ILLEGAL; 8632 8633 if (mode->flags & (DRM_MODE_FLAG_CSYNC | 8634 DRM_MODE_FLAG_NCSYNC | 8635 DRM_MODE_FLAG_PCSYNC)) 8636 return MODE_HSYNC; 8637 8638 if (mode->flags & (DRM_MODE_FLAG_BCAST | 8639 DRM_MODE_FLAG_PIXMUX | 8640 DRM_MODE_FLAG_CLKDIV2)) 8641 return MODE_BAD; 8642 8643 /* Transcoder timing limits */ 8644 if (DISPLAY_VER(dev_priv) >= 11) { 8645 hdisplay_max = 16384; 8646 vdisplay_max = 8192; 8647 htotal_max = 16384; 8648 vtotal_max = 8192; 8649 } else if (DISPLAY_VER(dev_priv) >= 9 || 8650 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 8651 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ 8652 vdisplay_max = 4096; 8653 htotal_max = 8192; 8654 vtotal_max = 8192; 8655 } else if (DISPLAY_VER(dev_priv) >= 3) { 8656 hdisplay_max = 4096; 8657 vdisplay_max = 4096; 8658 htotal_max = 8192; 8659 vtotal_max = 8192; 8660 } else { 8661 hdisplay_max = 2048; 8662 vdisplay_max = 2048; 8663 htotal_max = 4096; 8664 vtotal_max = 4096; 8665 } 8666 8667 if (mode->hdisplay > hdisplay_max || 8668 mode->hsync_start > htotal_max || 8669 mode->hsync_end > htotal_max || 8670 mode->htotal > htotal_max) 8671 return MODE_H_ILLEGAL; 8672 8673 if (mode->vdisplay > vdisplay_max || 8674 mode->vsync_start > vtotal_max || 8675 mode->vsync_end > vtotal_max || 8676 mode->vtotal > vtotal_max) 8677 return MODE_V_ILLEGAL; 8678 8679 if (DISPLAY_VER(dev_priv) >= 5) { 8680 if (mode->hdisplay < 64 || 8681 mode->htotal - mode->hdisplay < 32) 8682 return MODE_H_ILLEGAL; 8683 8684 if (mode->vtotal - mode->vdisplay < 5) 8685 return MODE_V_ILLEGAL; 8686 } else { 8687 if (mode->htotal - mode->hdisplay < 32) 8688 return MODE_H_ILLEGAL; 8689 8690 if (mode->vtotal - mode->vdisplay < 3) 8691 return MODE_V_ILLEGAL; 8692 } 8693 8694 /* 8695 * Cantiga+ cannot handle modes with a hsync front porch of 0. 8696 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. 8697 */ 8698 if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) && 8699 mode->hsync_start == mode->hdisplay) 8700 return MODE_H_ILLEGAL; 8701 8702 return MODE_OK; 8703 } 8704 8705 enum drm_mode_status 8706 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 8707 const struct drm_display_mode *mode, 8708 bool bigjoiner) 8709 { 8710 int plane_width_max, plane_height_max; 8711 8712 /* 8713 * intel_mode_valid() should be 8714 * sufficient on older platforms. 8715 */ 8716 if (DISPLAY_VER(dev_priv) < 9) 8717 return MODE_OK; 8718 8719 /* 8720 * Most people will probably want a fullscreen 8721 * plane so let's not advertize modes that are 8722 * too big for that. 8723 */ 8724 if (DISPLAY_VER(dev_priv) >= 11) { 8725 plane_width_max = 5120 << bigjoiner; 8726 plane_height_max = 4320; 8727 } else { 8728 plane_width_max = 5120; 8729 plane_height_max = 4096; 8730 } 8731 8732 if (mode->hdisplay > plane_width_max) 8733 return MODE_H_ILLEGAL; 8734 8735 if (mode->vdisplay > plane_height_max) 8736 return MODE_V_ILLEGAL; 8737 8738 return MODE_OK; 8739 } 8740 8741 static const struct drm_mode_config_funcs intel_mode_funcs = { 8742 .fb_create = intel_user_framebuffer_create, 8743 .get_format_info = intel_fb_get_format_info, 8744 .output_poll_changed = intel_fbdev_output_poll_changed, 8745 .mode_valid = intel_mode_valid, 8746 .atomic_check = intel_atomic_check, 8747 .atomic_commit = intel_atomic_commit, 8748 .atomic_state_alloc = intel_atomic_state_alloc, 8749 .atomic_state_clear = intel_atomic_state_clear, 8750 .atomic_state_free = intel_atomic_state_free, 8751 }; 8752 8753 static const struct drm_i915_display_funcs skl_display_funcs = { 8754 .get_pipe_config = hsw_get_pipe_config, 8755 .crtc_enable = hsw_crtc_enable, 8756 .crtc_disable = hsw_crtc_disable, 8757 .commit_modeset_enables = skl_commit_modeset_enables, 8758 .get_initial_plane_config = skl_get_initial_plane_config, 8759 }; 8760 8761 static const struct drm_i915_display_funcs ddi_display_funcs = { 8762 .get_pipe_config = hsw_get_pipe_config, 8763 .crtc_enable = hsw_crtc_enable, 8764 .crtc_disable = hsw_crtc_disable, 8765 .commit_modeset_enables = intel_commit_modeset_enables, 8766 .get_initial_plane_config = i9xx_get_initial_plane_config, 8767 }; 8768 8769 static const struct drm_i915_display_funcs pch_split_display_funcs = { 8770 .get_pipe_config = ilk_get_pipe_config, 8771 .crtc_enable = ilk_crtc_enable, 8772 .crtc_disable = ilk_crtc_disable, 8773 .commit_modeset_enables = intel_commit_modeset_enables, 8774 .get_initial_plane_config = i9xx_get_initial_plane_config, 8775 }; 8776 8777 static const struct drm_i915_display_funcs vlv_display_funcs = { 8778 .get_pipe_config = i9xx_get_pipe_config, 8779 .crtc_enable = valleyview_crtc_enable, 8780 .crtc_disable = i9xx_crtc_disable, 8781 .commit_modeset_enables = intel_commit_modeset_enables, 8782 .get_initial_plane_config = i9xx_get_initial_plane_config, 8783 }; 8784 8785 static const struct drm_i915_display_funcs i9xx_display_funcs = { 8786 .get_pipe_config = i9xx_get_pipe_config, 8787 .crtc_enable = i9xx_crtc_enable, 8788 .crtc_disable = i9xx_crtc_disable, 8789 .commit_modeset_enables = intel_commit_modeset_enables, 8790 .get_initial_plane_config = i9xx_get_initial_plane_config, 8791 }; 8792 8793 /** 8794 * intel_init_display_hooks - initialize the display modesetting hooks 8795 * @dev_priv: device private 8796 */ 8797 void intel_init_display_hooks(struct drm_i915_private *dev_priv) 8798 { 8799 if (!HAS_DISPLAY(dev_priv)) 8800 return; 8801 8802 intel_init_cdclk_hooks(dev_priv); 8803 intel_audio_hooks_init(dev_priv); 8804 8805 intel_dpll_init_clock_hook(dev_priv); 8806 8807 if (DISPLAY_VER(dev_priv) >= 9) { 8808 dev_priv->display = &skl_display_funcs; 8809 } else if (HAS_DDI(dev_priv)) { 8810 dev_priv->display = &ddi_display_funcs; 8811 } else if (HAS_PCH_SPLIT(dev_priv)) { 8812 dev_priv->display = &pch_split_display_funcs; 8813 } else if (IS_CHERRYVIEW(dev_priv) || 8814 IS_VALLEYVIEW(dev_priv)) { 8815 dev_priv->display = &vlv_display_funcs; 8816 } else { 8817 dev_priv->display = &i9xx_display_funcs; 8818 } 8819 8820 intel_fdi_init_hook(dev_priv); 8821 } 8822 8823 void intel_modeset_init_hw(struct drm_i915_private *i915) 8824 { 8825 struct intel_cdclk_state *cdclk_state; 8826 8827 if (!HAS_DISPLAY(i915)) 8828 return; 8829 8830 cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state); 8831 8832 intel_update_cdclk(i915); 8833 intel_cdclk_dump_config(i915, &i915->cdclk.hw, "Current CDCLK"); 8834 cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw; 8835 } 8836 8837 static int sanitize_watermarks_add_affected(struct drm_atomic_state *state) 8838 { 8839 struct drm_plane *plane; 8840 struct intel_crtc *crtc; 8841 8842 for_each_intel_crtc(state->dev, crtc) { 8843 struct intel_crtc_state *crtc_state; 8844 8845 crtc_state = intel_atomic_get_crtc_state(state, crtc); 8846 if (IS_ERR(crtc_state)) 8847 return PTR_ERR(crtc_state); 8848 8849 if (crtc_state->hw.active) { 8850 /* 8851 * Preserve the inherited flag to avoid 8852 * taking the full modeset path. 8853 */ 8854 crtc_state->inherited = true; 8855 } 8856 } 8857 8858 drm_for_each_plane(plane, state->dev) { 8859 struct drm_plane_state *plane_state; 8860 8861 plane_state = drm_atomic_get_plane_state(state, plane); 8862 if (IS_ERR(plane_state)) 8863 return PTR_ERR(plane_state); 8864 } 8865 8866 return 0; 8867 } 8868 8869 /* 8870 * Calculate what we think the watermarks should be for the state we've read 8871 * out of the hardware and then immediately program those watermarks so that 8872 * we ensure the hardware settings match our internal state. 8873 * 8874 * We can calculate what we think WM's should be by creating a duplicate of the 8875 * current state (which was constructed during hardware readout) and running it 8876 * through the atomic check code to calculate new watermark values in the 8877 * state object. 8878 */ 8879 static void sanitize_watermarks(struct drm_i915_private *dev_priv) 8880 { 8881 struct drm_atomic_state *state; 8882 struct intel_atomic_state *intel_state; 8883 struct intel_crtc *crtc; 8884 struct intel_crtc_state *crtc_state; 8885 struct drm_modeset_acquire_ctx ctx; 8886 int ret; 8887 int i; 8888 8889 /* Only supported on platforms that use atomic watermark design */ 8890 if (!dev_priv->wm_disp->optimize_watermarks) 8891 return; 8892 8893 state = drm_atomic_state_alloc(&dev_priv->drm); 8894 if (drm_WARN_ON(&dev_priv->drm, !state)) 8895 return; 8896 8897 intel_state = to_intel_atomic_state(state); 8898 8899 drm_modeset_acquire_init(&ctx, 0); 8900 8901 retry: 8902 state->acquire_ctx = &ctx; 8903 8904 /* 8905 * Hardware readout is the only time we don't want to calculate 8906 * intermediate watermarks (since we don't trust the current 8907 * watermarks). 8908 */ 8909 if (!HAS_GMCH(dev_priv)) 8910 intel_state->skip_intermediate_wm = true; 8911 8912 ret = sanitize_watermarks_add_affected(state); 8913 if (ret) 8914 goto fail; 8915 8916 ret = intel_atomic_check(&dev_priv->drm, state); 8917 if (ret) 8918 goto fail; 8919 8920 /* Write calculated watermark values back */ 8921 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) { 8922 crtc_state->wm.need_postvbl_update = true; 8923 intel_optimize_watermarks(intel_state, crtc); 8924 8925 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm; 8926 } 8927 8928 fail: 8929 if (ret == -EDEADLK) { 8930 drm_atomic_state_clear(state); 8931 drm_modeset_backoff(&ctx); 8932 goto retry; 8933 } 8934 8935 /* 8936 * If we fail here, it means that the hardware appears to be 8937 * programmed in a way that shouldn't be possible, given our 8938 * understanding of watermark requirements. This might mean a 8939 * mistake in the hardware readout code or a mistake in the 8940 * watermark calculations for a given platform. Raise a WARN 8941 * so that this is noticeable. 8942 * 8943 * If this actually happens, we'll have to just leave the 8944 * BIOS-programmed watermarks untouched and hope for the best. 8945 */ 8946 drm_WARN(&dev_priv->drm, ret, 8947 "Could not determine valid watermarks for inherited state\n"); 8948 8949 drm_atomic_state_put(state); 8950 8951 drm_modeset_drop_locks(&ctx); 8952 drm_modeset_acquire_fini(&ctx); 8953 } 8954 8955 static int intel_initial_commit(struct drm_device *dev) 8956 { 8957 struct drm_atomic_state *state = NULL; 8958 struct drm_modeset_acquire_ctx ctx; 8959 struct intel_crtc *crtc; 8960 int ret = 0; 8961 8962 state = drm_atomic_state_alloc(dev); 8963 if (!state) 8964 return -ENOMEM; 8965 8966 drm_modeset_acquire_init(&ctx, 0); 8967 8968 retry: 8969 state->acquire_ctx = &ctx; 8970 8971 for_each_intel_crtc(dev, crtc) { 8972 struct intel_crtc_state *crtc_state = 8973 intel_atomic_get_crtc_state(state, crtc); 8974 8975 if (IS_ERR(crtc_state)) { 8976 ret = PTR_ERR(crtc_state); 8977 goto out; 8978 } 8979 8980 if (crtc_state->hw.active) { 8981 struct intel_encoder *encoder; 8982 8983 /* 8984 * We've not yet detected sink capabilities 8985 * (audio,infoframes,etc.) and thus we don't want to 8986 * force a full state recomputation yet. We want that to 8987 * happen only for the first real commit from userspace. 8988 * So preserve the inherited flag for the time being. 8989 */ 8990 crtc_state->inherited = true; 8991 8992 ret = drm_atomic_add_affected_planes(state, &crtc->base); 8993 if (ret) 8994 goto out; 8995 8996 /* 8997 * FIXME hack to force a LUT update to avoid the 8998 * plane update forcing the pipe gamma on without 8999 * having a proper LUT loaded. Remove once we 9000 * have readout for pipe gamma enable. 9001 */ 9002 crtc_state->uapi.color_mgmt_changed = true; 9003 9004 for_each_intel_encoder_mask(dev, encoder, 9005 crtc_state->uapi.encoder_mask) { 9006 if (encoder->initial_fastset_check && 9007 !encoder->initial_fastset_check(encoder, crtc_state)) { 9008 ret = drm_atomic_add_affected_connectors(state, 9009 &crtc->base); 9010 if (ret) 9011 goto out; 9012 } 9013 } 9014 } 9015 } 9016 9017 ret = drm_atomic_commit(state); 9018 9019 out: 9020 if (ret == -EDEADLK) { 9021 drm_atomic_state_clear(state); 9022 drm_modeset_backoff(&ctx); 9023 goto retry; 9024 } 9025 9026 drm_atomic_state_put(state); 9027 9028 drm_modeset_drop_locks(&ctx); 9029 drm_modeset_acquire_fini(&ctx); 9030 9031 return ret; 9032 } 9033 9034 static void intel_mode_config_init(struct drm_i915_private *i915) 9035 { 9036 struct drm_mode_config *mode_config = &i915->drm.mode_config; 9037 9038 drm_mode_config_init(&i915->drm); 9039 INIT_LIST_HEAD(&i915->global_obj_list); 9040 9041 mode_config->min_width = 0; 9042 mode_config->min_height = 0; 9043 9044 mode_config->preferred_depth = 24; 9045 mode_config->prefer_shadow = 1; 9046 9047 mode_config->funcs = &intel_mode_funcs; 9048 9049 mode_config->async_page_flip = HAS_ASYNC_FLIPS(i915); 9050 9051 /* 9052 * Maximum framebuffer dimensions, chosen to match 9053 * the maximum render engine surface size on gen4+. 9054 */ 9055 if (DISPLAY_VER(i915) >= 7) { 9056 mode_config->max_width = 16384; 9057 mode_config->max_height = 16384; 9058 } else if (DISPLAY_VER(i915) >= 4) { 9059 mode_config->max_width = 8192; 9060 mode_config->max_height = 8192; 9061 } else if (DISPLAY_VER(i915) == 3) { 9062 mode_config->max_width = 4096; 9063 mode_config->max_height = 4096; 9064 } else { 9065 mode_config->max_width = 2048; 9066 mode_config->max_height = 2048; 9067 } 9068 9069 if (IS_I845G(i915) || IS_I865G(i915)) { 9070 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512; 9071 mode_config->cursor_height = 1023; 9072 } else if (IS_I830(i915) || IS_I85X(i915) || 9073 IS_I915G(i915) || IS_I915GM(i915)) { 9074 mode_config->cursor_width = 64; 9075 mode_config->cursor_height = 64; 9076 } else { 9077 mode_config->cursor_width = 256; 9078 mode_config->cursor_height = 256; 9079 } 9080 } 9081 9082 static void intel_mode_config_cleanup(struct drm_i915_private *i915) 9083 { 9084 intel_atomic_global_obj_cleanup(i915); 9085 drm_mode_config_cleanup(&i915->drm); 9086 } 9087 9088 /* part #1: call before irq install */ 9089 int intel_modeset_init_noirq(struct drm_i915_private *i915) 9090 { 9091 int ret; 9092 9093 if (i915_inject_probe_failure(i915)) 9094 return -ENODEV; 9095 9096 if (HAS_DISPLAY(i915)) { 9097 ret = drm_vblank_init(&i915->drm, 9098 INTEL_NUM_PIPES(i915)); 9099 if (ret) 9100 return ret; 9101 } 9102 9103 intel_bios_init(i915); 9104 9105 ret = intel_vga_register(i915); 9106 if (ret) 9107 goto cleanup_bios; 9108 9109 /* FIXME: completely on the wrong abstraction layer */ 9110 intel_power_domains_init_hw(i915, false); 9111 9112 if (!HAS_DISPLAY(i915)) 9113 return 0; 9114 9115 intel_dmc_ucode_init(i915); 9116 9117 i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0); 9118 i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI | 9119 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE); 9120 9121 i915->window2_delay = 0; /* No DSB so no window2 delay */ 9122 9123 intel_mode_config_init(i915); 9124 9125 ret = intel_cdclk_init(i915); 9126 if (ret) 9127 goto cleanup_vga_client_pw_domain_dmc; 9128 9129 ret = intel_dbuf_init(i915); 9130 if (ret) 9131 goto cleanup_vga_client_pw_domain_dmc; 9132 9133 ret = intel_bw_init(i915); 9134 if (ret) 9135 goto cleanup_vga_client_pw_domain_dmc; 9136 9137 init_llist_head(&i915->atomic_helper.free_list); 9138 INIT_WORK(&i915->atomic_helper.free_work, 9139 intel_atomic_helper_free_state_worker); 9140 9141 intel_init_quirks(i915); 9142 9143 intel_fbc_init(i915); 9144 9145 return 0; 9146 9147 cleanup_vga_client_pw_domain_dmc: 9148 intel_dmc_ucode_fini(i915); 9149 intel_power_domains_driver_remove(i915); 9150 intel_vga_unregister(i915); 9151 cleanup_bios: 9152 intel_bios_driver_remove(i915); 9153 9154 return ret; 9155 } 9156 9157 /* part #2: call after irq install, but before gem init */ 9158 int intel_modeset_init_nogem(struct drm_i915_private *i915) 9159 { 9160 struct drm_device *dev = &i915->drm; 9161 enum pipe pipe; 9162 struct intel_crtc *crtc; 9163 int ret; 9164 9165 if (!HAS_DISPLAY(i915)) 9166 return 0; 9167 9168 intel_init_pm(i915); 9169 9170 intel_panel_sanitize_ssc(i915); 9171 9172 intel_pps_setup(i915); 9173 9174 intel_gmbus_setup(i915); 9175 9176 drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n", 9177 INTEL_NUM_PIPES(i915), 9178 INTEL_NUM_PIPES(i915) > 1 ? "s" : ""); 9179 9180 for_each_pipe(i915, pipe) { 9181 ret = intel_crtc_init(i915, pipe); 9182 if (ret) { 9183 intel_mode_config_cleanup(i915); 9184 return ret; 9185 } 9186 } 9187 9188 intel_plane_possible_crtcs_init(i915); 9189 intel_shared_dpll_init(i915); 9190 intel_fdi_pll_freq_update(i915); 9191 9192 intel_update_czclk(i915); 9193 intel_modeset_init_hw(i915); 9194 intel_dpll_update_ref_clks(i915); 9195 9196 intel_hdcp_component_init(i915); 9197 9198 if (i915->max_cdclk_freq == 0) 9199 intel_update_max_cdclk(i915); 9200 9201 /* 9202 * If the platform has HTI, we need to find out whether it has reserved 9203 * any display resources before we create our display outputs. 9204 */ 9205 if (INTEL_INFO(i915)->display.has_hti) 9206 i915->hti_state = intel_de_read(i915, HDPORT_STATE); 9207 9208 /* Just disable it once at startup */ 9209 intel_vga_disable(i915); 9210 intel_setup_outputs(i915); 9211 9212 drm_modeset_lock_all(dev); 9213 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx); 9214 intel_acpi_assign_connector_fwnodes(i915); 9215 drm_modeset_unlock_all(dev); 9216 9217 for_each_intel_crtc(dev, crtc) { 9218 if (!to_intel_crtc_state(crtc->base.state)->uapi.active) 9219 continue; 9220 intel_crtc_initial_plane_config(crtc); 9221 } 9222 9223 /* 9224 * Make sure hardware watermarks really match the state we read out. 9225 * Note that we need to do this after reconstructing the BIOS fb's 9226 * since the watermark calculation done here will use pstate->fb. 9227 */ 9228 if (!HAS_GMCH(i915)) 9229 sanitize_watermarks(i915); 9230 9231 return 0; 9232 } 9233 9234 /* part #3: call after gem init */ 9235 int intel_modeset_init(struct drm_i915_private *i915) 9236 { 9237 int ret; 9238 9239 if (!HAS_DISPLAY(i915)) 9240 return 0; 9241 9242 /* 9243 * Force all active planes to recompute their states. So that on 9244 * mode_setcrtc after probe, all the intel_plane_state variables 9245 * are already calculated and there is no assert_plane warnings 9246 * during bootup. 9247 */ 9248 ret = intel_initial_commit(&i915->drm); 9249 if (ret) 9250 drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret); 9251 9252 intel_overlay_setup(i915); 9253 9254 ret = intel_fbdev_init(&i915->drm); 9255 if (ret) 9256 return ret; 9257 9258 /* Only enable hotplug handling once the fbdev is fully set up. */ 9259 intel_hpd_init(i915); 9260 intel_hpd_poll_disable(i915); 9261 9262 intel_init_ipc(i915); 9263 9264 return 0; 9265 } 9266 9267 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 9268 { 9269 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 9270 /* 640x480@60Hz, ~25175 kHz */ 9271 struct dpll clock = { 9272 .m1 = 18, 9273 .m2 = 7, 9274 .p1 = 13, 9275 .p2 = 4, 9276 .n = 2, 9277 }; 9278 u32 dpll, fp; 9279 int i; 9280 9281 drm_WARN_ON(&dev_priv->drm, 9282 i9xx_calc_dpll_params(48000, &clock) != 25154); 9283 9284 drm_dbg_kms(&dev_priv->drm, 9285 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n", 9286 pipe_name(pipe), clock.vco, clock.dot); 9287 9288 fp = i9xx_dpll_compute_fp(&clock); 9289 dpll = DPLL_DVO_2X_MODE | 9290 DPLL_VGA_MODE_DIS | 9291 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | 9292 PLL_P2_DIVIDE_BY_4 | 9293 PLL_REF_INPUT_DREFCLK | 9294 DPLL_VCO_ENABLE; 9295 9296 intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16)); 9297 intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16)); 9298 intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16)); 9299 intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16)); 9300 intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16)); 9301 intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16)); 9302 intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1)); 9303 9304 intel_de_write(dev_priv, FP0(pipe), fp); 9305 intel_de_write(dev_priv, FP1(pipe), fp); 9306 9307 /* 9308 * Apparently we need to have VGA mode enabled prior to changing 9309 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 9310 * dividers, even though the register value does change. 9311 */ 9312 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); 9313 intel_de_write(dev_priv, DPLL(pipe), dpll); 9314 9315 /* Wait for the clocks to stabilize. */ 9316 intel_de_posting_read(dev_priv, DPLL(pipe)); 9317 udelay(150); 9318 9319 /* The pixel multiplier can only be updated once the 9320 * DPLL is enabled and the clocks are stable. 9321 * 9322 * So write it again. 9323 */ 9324 intel_de_write(dev_priv, DPLL(pipe), dpll); 9325 9326 /* We do this three times for luck */ 9327 for (i = 0; i < 3 ; i++) { 9328 intel_de_write(dev_priv, DPLL(pipe), dpll); 9329 intel_de_posting_read(dev_priv, DPLL(pipe)); 9330 udelay(150); /* wait for warmup */ 9331 } 9332 9333 intel_de_write(dev_priv, PIPECONF(pipe), PIPECONF_ENABLE); 9334 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 9335 9336 intel_wait_for_pipe_scanline_moving(crtc); 9337 } 9338 9339 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 9340 { 9341 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 9342 9343 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n", 9344 pipe_name(pipe)); 9345 9346 drm_WARN_ON(&dev_priv->drm, 9347 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE); 9348 drm_WARN_ON(&dev_priv->drm, 9349 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE); 9350 drm_WARN_ON(&dev_priv->drm, 9351 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE); 9352 drm_WARN_ON(&dev_priv->drm, 9353 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK); 9354 drm_WARN_ON(&dev_priv->drm, 9355 intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK); 9356 9357 intel_de_write(dev_priv, PIPECONF(pipe), 0); 9358 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 9359 9360 intel_wait_for_pipe_scanline_stopped(crtc); 9361 9362 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); 9363 intel_de_posting_read(dev_priv, DPLL(pipe)); 9364 } 9365 9366 static void 9367 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv) 9368 { 9369 struct intel_crtc *crtc; 9370 9371 if (DISPLAY_VER(dev_priv) >= 4) 9372 return; 9373 9374 for_each_intel_crtc(&dev_priv->drm, crtc) { 9375 struct intel_plane *plane = 9376 to_intel_plane(crtc->base.primary); 9377 struct intel_crtc *plane_crtc; 9378 enum pipe pipe; 9379 9380 if (!plane->get_hw_state(plane, &pipe)) 9381 continue; 9382 9383 if (pipe == crtc->pipe) 9384 continue; 9385 9386 drm_dbg_kms(&dev_priv->drm, 9387 "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n", 9388 plane->base.base.id, plane->base.name); 9389 9390 plane_crtc = intel_crtc_for_pipe(dev_priv, pipe); 9391 intel_plane_disable_noatomic(plane_crtc, plane); 9392 } 9393 } 9394 9395 static bool intel_crtc_has_encoders(struct intel_crtc *crtc) 9396 { 9397 struct drm_device *dev = crtc->base.dev; 9398 struct intel_encoder *encoder; 9399 9400 for_each_encoder_on_crtc(dev, &crtc->base, encoder) 9401 return true; 9402 9403 return false; 9404 } 9405 9406 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) 9407 { 9408 struct drm_device *dev = encoder->base.dev; 9409 struct intel_connector *connector; 9410 9411 for_each_connector_on_encoder(dev, &encoder->base, connector) 9412 return connector; 9413 9414 return NULL; 9415 } 9416 9417 static void intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state *crtc_state) 9418 { 9419 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 9420 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 9421 9422 if (!crtc_state->hw.active && !HAS_GMCH(i915)) 9423 return; 9424 9425 /* 9426 * We start out with underrun reporting disabled to avoid races. 9427 * For correct bookkeeping mark this on active crtcs. 9428 * 9429 * Also on gmch platforms we dont have any hardware bits to 9430 * disable the underrun reporting. Which means we need to start 9431 * out with underrun reporting disabled also on inactive pipes, 9432 * since otherwise we'll complain about the garbage we read when 9433 * e.g. coming up after runtime pm. 9434 * 9435 * No protection against concurrent access is required - at 9436 * worst a fifo underrun happens which also sets this to false. 9437 */ 9438 crtc->cpu_fifo_underrun_disabled = true; 9439 9440 /* 9441 * We track the PCH trancoder underrun reporting state 9442 * within the crtc. With crtc for pipe A housing the underrun 9443 * reporting state for PCH transcoder A, crtc for pipe B housing 9444 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, 9445 * and marking underrun reporting as disabled for the non-existing 9446 * PCH transcoders B and C would prevent enabling the south 9447 * error interrupt (see cpt_can_enable_serr_int()). 9448 */ 9449 if (intel_has_pch_trancoder(i915, crtc->pipe)) 9450 crtc->pch_fifo_underrun_disabled = true; 9451 } 9452 9453 static void intel_sanitize_crtc(struct intel_crtc *crtc, 9454 struct drm_modeset_acquire_ctx *ctx) 9455 { 9456 struct drm_device *dev = crtc->base.dev; 9457 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); 9458 9459 if (crtc_state->hw.active) { 9460 struct intel_plane *plane; 9461 9462 /* Disable everything but the primary plane */ 9463 for_each_intel_plane_on_crtc(dev, crtc, plane) { 9464 const struct intel_plane_state *plane_state = 9465 to_intel_plane_state(plane->base.state); 9466 9467 if (plane_state->uapi.visible && 9468 plane->base.type != DRM_PLANE_TYPE_PRIMARY) 9469 intel_plane_disable_noatomic(crtc, plane); 9470 } 9471 9472 /* Disable any background color/etc. set by the BIOS */ 9473 intel_color_commit_noarm(crtc_state); 9474 intel_color_commit_arm(crtc_state); 9475 } 9476 9477 /* Adjust the state of the output pipe according to whether we 9478 * have active connectors/encoders. */ 9479 if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) && 9480 !intel_crtc_is_bigjoiner_slave(crtc_state)) 9481 intel_crtc_disable_noatomic(crtc, ctx); 9482 } 9483 9484 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state) 9485 { 9486 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 9487 9488 /* 9489 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram 9490 * the hardware when a high res displays plugged in. DPLL P 9491 * divider is zero, and the pipe timings are bonkers. We'll 9492 * try to disable everything in that case. 9493 * 9494 * FIXME would be nice to be able to sanitize this state 9495 * without several WARNs, but for now let's take the easy 9496 * road. 9497 */ 9498 return IS_SANDYBRIDGE(dev_priv) && 9499 crtc_state->hw.active && 9500 crtc_state->shared_dpll && 9501 crtc_state->port_clock == 0; 9502 } 9503 9504 static void intel_sanitize_encoder(struct intel_encoder *encoder) 9505 { 9506 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 9507 struct intel_connector *connector; 9508 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 9509 struct intel_crtc_state *crtc_state = crtc ? 9510 to_intel_crtc_state(crtc->base.state) : NULL; 9511 9512 /* We need to check both for a crtc link (meaning that the 9513 * encoder is active and trying to read from a pipe) and the 9514 * pipe itself being active. */ 9515 bool has_active_crtc = crtc_state && 9516 crtc_state->hw.active; 9517 9518 if (crtc_state && has_bogus_dpll_config(crtc_state)) { 9519 drm_dbg_kms(&dev_priv->drm, 9520 "BIOS has misprogrammed the hardware. Disabling pipe %c\n", 9521 pipe_name(crtc->pipe)); 9522 has_active_crtc = false; 9523 } 9524 9525 connector = intel_encoder_find_connector(encoder); 9526 if (connector && !has_active_crtc) { 9527 drm_dbg_kms(&dev_priv->drm, 9528 "[ENCODER:%d:%s] has active connectors but no active pipe!\n", 9529 encoder->base.base.id, 9530 encoder->base.name); 9531 9532 /* Connector is active, but has no active pipe. This is 9533 * fallout from our resume register restoring. Disable 9534 * the encoder manually again. */ 9535 if (crtc_state) { 9536 struct drm_encoder *best_encoder; 9537 9538 drm_dbg_kms(&dev_priv->drm, 9539 "[ENCODER:%d:%s] manually disabled\n", 9540 encoder->base.base.id, 9541 encoder->base.name); 9542 9543 /* avoid oopsing in case the hooks consult best_encoder */ 9544 best_encoder = connector->base.state->best_encoder; 9545 connector->base.state->best_encoder = &encoder->base; 9546 9547 /* FIXME NULL atomic state passed! */ 9548 if (encoder->disable) 9549 encoder->disable(NULL, encoder, crtc_state, 9550 connector->base.state); 9551 if (encoder->post_disable) 9552 encoder->post_disable(NULL, encoder, crtc_state, 9553 connector->base.state); 9554 9555 connector->base.state->best_encoder = best_encoder; 9556 } 9557 encoder->base.crtc = NULL; 9558 9559 /* Inconsistent output/port/pipe state happens presumably due to 9560 * a bug in one of the get_hw_state functions. Or someplace else 9561 * in our code, like the register restore mess on resume. Clamp 9562 * things to off as a safer default. */ 9563 9564 connector->base.dpms = DRM_MODE_DPMS_OFF; 9565 connector->base.encoder = NULL; 9566 } 9567 9568 /* notify opregion of the sanitized encoder state */ 9569 intel_opregion_notify_encoder(encoder, connector && has_active_crtc); 9570 9571 if (HAS_DDI(dev_priv)) 9572 intel_ddi_sanitize_encoder_pll_mapping(encoder); 9573 } 9574 9575 /* FIXME read out full plane state for all planes */ 9576 static void readout_plane_state(struct drm_i915_private *dev_priv) 9577 { 9578 struct intel_plane *plane; 9579 struct intel_crtc *crtc; 9580 9581 for_each_intel_plane(&dev_priv->drm, plane) { 9582 struct intel_plane_state *plane_state = 9583 to_intel_plane_state(plane->base.state); 9584 struct intel_crtc_state *crtc_state; 9585 enum pipe pipe = PIPE_A; 9586 bool visible; 9587 9588 visible = plane->get_hw_state(plane, &pipe); 9589 9590 crtc = intel_crtc_for_pipe(dev_priv, pipe); 9591 crtc_state = to_intel_crtc_state(crtc->base.state); 9592 9593 intel_set_plane_visible(crtc_state, plane_state, visible); 9594 9595 drm_dbg_kms(&dev_priv->drm, 9596 "[PLANE:%d:%s] hw state readout: %s, pipe %c\n", 9597 plane->base.base.id, plane->base.name, 9598 str_enabled_disabled(visible), pipe_name(pipe)); 9599 } 9600 9601 for_each_intel_crtc(&dev_priv->drm, crtc) { 9602 struct intel_crtc_state *crtc_state = 9603 to_intel_crtc_state(crtc->base.state); 9604 9605 fixup_plane_bitmasks(crtc_state); 9606 } 9607 } 9608 9609 static void intel_modeset_readout_hw_state(struct drm_device *dev) 9610 { 9611 struct drm_i915_private *dev_priv = to_i915(dev); 9612 struct intel_cdclk_state *cdclk_state = 9613 to_intel_cdclk_state(dev_priv->cdclk.obj.state); 9614 struct intel_dbuf_state *dbuf_state = 9615 to_intel_dbuf_state(dev_priv->dbuf.obj.state); 9616 enum pipe pipe; 9617 struct intel_crtc *crtc; 9618 struct intel_encoder *encoder; 9619 struct intel_connector *connector; 9620 struct drm_connector_list_iter conn_iter; 9621 u8 active_pipes = 0; 9622 9623 for_each_intel_crtc(dev, crtc) { 9624 struct intel_crtc_state *crtc_state = 9625 to_intel_crtc_state(crtc->base.state); 9626 9627 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi); 9628 intel_crtc_free_hw_state(crtc_state); 9629 intel_crtc_state_reset(crtc_state, crtc); 9630 9631 intel_crtc_get_pipe_config(crtc_state); 9632 9633 crtc_state->hw.enable = crtc_state->hw.active; 9634 9635 crtc->base.enabled = crtc_state->hw.enable; 9636 crtc->active = crtc_state->hw.active; 9637 9638 if (crtc_state->hw.active) 9639 active_pipes |= BIT(crtc->pipe); 9640 9641 drm_dbg_kms(&dev_priv->drm, 9642 "[CRTC:%d:%s] hw state readout: %s\n", 9643 crtc->base.base.id, crtc->base.name, 9644 str_enabled_disabled(crtc_state->hw.active)); 9645 } 9646 9647 cdclk_state->active_pipes = dbuf_state->active_pipes = active_pipes; 9648 9649 readout_plane_state(dev_priv); 9650 9651 for_each_intel_encoder(dev, encoder) { 9652 struct intel_crtc_state *crtc_state = NULL; 9653 9654 pipe = 0; 9655 9656 if (encoder->get_hw_state(encoder, &pipe)) { 9657 crtc = intel_crtc_for_pipe(dev_priv, pipe); 9658 crtc_state = to_intel_crtc_state(crtc->base.state); 9659 9660 encoder->base.crtc = &crtc->base; 9661 intel_encoder_get_config(encoder, crtc_state); 9662 9663 /* read out to slave crtc as well for bigjoiner */ 9664 if (crtc_state->bigjoiner_pipes) { 9665 struct intel_crtc *slave_crtc; 9666 9667 /* encoder should read be linked to bigjoiner master */ 9668 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 9669 9670 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc, 9671 intel_crtc_bigjoiner_slave_pipes(crtc_state)) { 9672 struct intel_crtc_state *slave_crtc_state; 9673 9674 slave_crtc_state = to_intel_crtc_state(slave_crtc->base.state); 9675 intel_encoder_get_config(encoder, slave_crtc_state); 9676 } 9677 } 9678 } else { 9679 encoder->base.crtc = NULL; 9680 } 9681 9682 if (encoder->sync_state) 9683 encoder->sync_state(encoder, crtc_state); 9684 9685 drm_dbg_kms(&dev_priv->drm, 9686 "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", 9687 encoder->base.base.id, encoder->base.name, 9688 str_enabled_disabled(encoder->base.crtc), 9689 pipe_name(pipe)); 9690 } 9691 9692 intel_dpll_readout_hw_state(dev_priv); 9693 9694 drm_connector_list_iter_begin(dev, &conn_iter); 9695 for_each_intel_connector_iter(connector, &conn_iter) { 9696 if (connector->get_hw_state(connector)) { 9697 struct intel_crtc_state *crtc_state; 9698 struct intel_crtc *crtc; 9699 9700 connector->base.dpms = DRM_MODE_DPMS_ON; 9701 9702 encoder = intel_attached_encoder(connector); 9703 connector->base.encoder = &encoder->base; 9704 9705 crtc = to_intel_crtc(encoder->base.crtc); 9706 crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL; 9707 9708 if (crtc_state && crtc_state->hw.active) { 9709 /* 9710 * This has to be done during hardware readout 9711 * because anything calling .crtc_disable may 9712 * rely on the connector_mask being accurate. 9713 */ 9714 crtc_state->uapi.connector_mask |= 9715 drm_connector_mask(&connector->base); 9716 crtc_state->uapi.encoder_mask |= 9717 drm_encoder_mask(&encoder->base); 9718 } 9719 } else { 9720 connector->base.dpms = DRM_MODE_DPMS_OFF; 9721 connector->base.encoder = NULL; 9722 } 9723 drm_dbg_kms(&dev_priv->drm, 9724 "[CONNECTOR:%d:%s] hw state readout: %s\n", 9725 connector->base.base.id, connector->base.name, 9726 str_enabled_disabled(connector->base.encoder)); 9727 } 9728 drm_connector_list_iter_end(&conn_iter); 9729 9730 for_each_intel_crtc(dev, crtc) { 9731 struct intel_bw_state *bw_state = 9732 to_intel_bw_state(dev_priv->bw_obj.state); 9733 struct intel_crtc_state *crtc_state = 9734 to_intel_crtc_state(crtc->base.state); 9735 struct intel_plane *plane; 9736 int min_cdclk = 0; 9737 9738 if (crtc_state->hw.active) { 9739 /* 9740 * The initial mode needs to be set in order to keep 9741 * the atomic core happy. It wants a valid mode if the 9742 * crtc's enabled, so we do the above call. 9743 * 9744 * But we don't set all the derived state fully, hence 9745 * set a flag to indicate that a full recalculation is 9746 * needed on the next commit. 9747 */ 9748 crtc_state->inherited = true; 9749 9750 intel_crtc_update_active_timings(crtc_state); 9751 9752 intel_crtc_copy_hw_to_uapi_state(crtc_state); 9753 } 9754 9755 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 9756 const struct intel_plane_state *plane_state = 9757 to_intel_plane_state(plane->base.state); 9758 9759 /* 9760 * FIXME don't have the fb yet, so can't 9761 * use intel_plane_data_rate() :( 9762 */ 9763 if (plane_state->uapi.visible) 9764 crtc_state->data_rate[plane->id] = 9765 4 * crtc_state->pixel_rate; 9766 /* 9767 * FIXME don't have the fb yet, so can't 9768 * use plane->min_cdclk() :( 9769 */ 9770 if (plane_state->uapi.visible && plane->min_cdclk) { 9771 if (crtc_state->double_wide || DISPLAY_VER(dev_priv) >= 10) 9772 crtc_state->min_cdclk[plane->id] = 9773 DIV_ROUND_UP(crtc_state->pixel_rate, 2); 9774 else 9775 crtc_state->min_cdclk[plane->id] = 9776 crtc_state->pixel_rate; 9777 } 9778 drm_dbg_kms(&dev_priv->drm, 9779 "[PLANE:%d:%s] min_cdclk %d kHz\n", 9780 plane->base.base.id, plane->base.name, 9781 crtc_state->min_cdclk[plane->id]); 9782 } 9783 9784 if (crtc_state->hw.active) { 9785 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); 9786 if (drm_WARN_ON(dev, min_cdclk < 0)) 9787 min_cdclk = 0; 9788 } 9789 9790 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; 9791 cdclk_state->min_voltage_level[crtc->pipe] = 9792 crtc_state->min_voltage_level; 9793 9794 intel_bw_crtc_update(bw_state, crtc_state); 9795 } 9796 } 9797 9798 static void 9799 get_encoder_power_domains(struct drm_i915_private *dev_priv) 9800 { 9801 struct intel_encoder *encoder; 9802 9803 for_each_intel_encoder(&dev_priv->drm, encoder) { 9804 struct intel_crtc_state *crtc_state; 9805 9806 if (!encoder->get_power_domains) 9807 continue; 9808 9809 /* 9810 * MST-primary and inactive encoders don't have a crtc state 9811 * and neither of these require any power domain references. 9812 */ 9813 if (!encoder->base.crtc) 9814 continue; 9815 9816 crtc_state = to_intel_crtc_state(encoder->base.crtc->state); 9817 encoder->get_power_domains(encoder, crtc_state); 9818 } 9819 } 9820 9821 static void intel_early_display_was(struct drm_i915_private *dev_priv) 9822 { 9823 /* 9824 * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl 9825 * Also known as Wa_14010480278. 9826 */ 9827 if (IS_DISPLAY_VER(dev_priv, 10, 12)) 9828 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0, 9829 intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS); 9830 9831 if (IS_HASWELL(dev_priv)) { 9832 /* 9833 * WaRsPkgCStateDisplayPMReq:hsw 9834 * System hang if this isn't done before disabling all planes! 9835 */ 9836 intel_de_write(dev_priv, CHICKEN_PAR1_1, 9837 intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); 9838 } 9839 9840 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) { 9841 /* Display WA #1142:kbl,cfl,cml */ 9842 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 9843 KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22); 9844 intel_de_rmw(dev_priv, CHICKEN_MISC_2, 9845 KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14, 9846 KBL_ARB_FILL_SPARE_14); 9847 } 9848 } 9849 9850 9851 /* Scan out the current hw modeset state, 9852 * and sanitizes it to the current state 9853 */ 9854 static void 9855 intel_modeset_setup_hw_state(struct drm_device *dev, 9856 struct drm_modeset_acquire_ctx *ctx) 9857 { 9858 struct drm_i915_private *dev_priv = to_i915(dev); 9859 struct intel_encoder *encoder; 9860 struct intel_crtc *crtc; 9861 intel_wakeref_t wakeref; 9862 9863 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 9864 9865 intel_early_display_was(dev_priv); 9866 intel_modeset_readout_hw_state(dev); 9867 9868 /* HW state is read out, now we need to sanitize this mess. */ 9869 get_encoder_power_domains(dev_priv); 9870 9871 intel_pch_sanitize(dev_priv); 9872 9873 /* 9874 * intel_sanitize_plane_mapping() may need to do vblank 9875 * waits, so we need vblank interrupts restored beforehand. 9876 */ 9877 for_each_intel_crtc(&dev_priv->drm, crtc) { 9878 struct intel_crtc_state *crtc_state = 9879 to_intel_crtc_state(crtc->base.state); 9880 9881 intel_sanitize_fifo_underrun_reporting(crtc_state); 9882 9883 drm_crtc_vblank_reset(&crtc->base); 9884 9885 if (crtc_state->hw.active) 9886 intel_crtc_vblank_on(crtc_state); 9887 } 9888 9889 intel_fbc_sanitize(dev_priv); 9890 9891 intel_sanitize_plane_mapping(dev_priv); 9892 9893 for_each_intel_encoder(dev, encoder) 9894 intel_sanitize_encoder(encoder); 9895 9896 for_each_intel_crtc(&dev_priv->drm, crtc) { 9897 struct intel_crtc_state *crtc_state = 9898 to_intel_crtc_state(crtc->base.state); 9899 9900 intel_sanitize_crtc(crtc, ctx); 9901 intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]"); 9902 } 9903 9904 intel_modeset_update_connector_atomic_state(dev); 9905 9906 intel_dpll_sanitize_state(dev_priv); 9907 9908 if (IS_G4X(dev_priv)) { 9909 g4x_wm_get_hw_state(dev_priv); 9910 g4x_wm_sanitize(dev_priv); 9911 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 9912 vlv_wm_get_hw_state(dev_priv); 9913 vlv_wm_sanitize(dev_priv); 9914 } else if (DISPLAY_VER(dev_priv) >= 9) { 9915 skl_wm_get_hw_state(dev_priv); 9916 skl_wm_sanitize(dev_priv); 9917 } else if (HAS_PCH_SPLIT(dev_priv)) { 9918 ilk_wm_get_hw_state(dev_priv); 9919 } 9920 9921 for_each_intel_crtc(dev, crtc) { 9922 struct intel_crtc_state *crtc_state = 9923 to_intel_crtc_state(crtc->base.state); 9924 struct intel_power_domain_mask put_domains; 9925 9926 modeset_get_crtc_power_domains(crtc_state, &put_domains); 9927 if (drm_WARN_ON(dev, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM))) 9928 modeset_put_crtc_power_domains(crtc, &put_domains); 9929 } 9930 9931 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref); 9932 9933 intel_power_domains_sanitize_state(dev_priv); 9934 } 9935 9936 void intel_display_resume(struct drm_device *dev) 9937 { 9938 struct drm_i915_private *dev_priv = to_i915(dev); 9939 struct drm_atomic_state *state = dev_priv->modeset_restore_state; 9940 struct drm_modeset_acquire_ctx ctx; 9941 int ret; 9942 9943 if (!HAS_DISPLAY(dev_priv)) 9944 return; 9945 9946 dev_priv->modeset_restore_state = NULL; 9947 if (state) 9948 state->acquire_ctx = &ctx; 9949 9950 drm_modeset_acquire_init(&ctx, 0); 9951 9952 while (1) { 9953 ret = drm_modeset_lock_all_ctx(dev, &ctx); 9954 if (ret != -EDEADLK) 9955 break; 9956 9957 drm_modeset_backoff(&ctx); 9958 } 9959 9960 if (!ret) 9961 ret = __intel_display_resume(dev, state, &ctx); 9962 9963 intel_enable_ipc(dev_priv); 9964 drm_modeset_drop_locks(&ctx); 9965 drm_modeset_acquire_fini(&ctx); 9966 9967 if (ret) 9968 drm_err(&dev_priv->drm, 9969 "Restoring old state failed with %i\n", ret); 9970 if (state) 9971 drm_atomic_state_put(state); 9972 } 9973 9974 static void intel_hpd_poll_fini(struct drm_i915_private *i915) 9975 { 9976 struct intel_connector *connector; 9977 struct drm_connector_list_iter conn_iter; 9978 9979 /* Kill all the work that may have been queued by hpd. */ 9980 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 9981 for_each_intel_connector_iter(connector, &conn_iter) { 9982 if (connector->modeset_retry_work.func) 9983 cancel_work_sync(&connector->modeset_retry_work); 9984 if (connector->hdcp.shim) { 9985 cancel_delayed_work_sync(&connector->hdcp.check_work); 9986 cancel_work_sync(&connector->hdcp.prop_work); 9987 } 9988 } 9989 drm_connector_list_iter_end(&conn_iter); 9990 } 9991 9992 /* part #1: call before irq uninstall */ 9993 void intel_modeset_driver_remove(struct drm_i915_private *i915) 9994 { 9995 if (!HAS_DISPLAY(i915)) 9996 return; 9997 9998 flush_workqueue(i915->flip_wq); 9999 flush_workqueue(i915->modeset_wq); 10000 10001 flush_work(&i915->atomic_helper.free_work); 10002 drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list)); 10003 } 10004 10005 /* part #2: call after irq uninstall */ 10006 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915) 10007 { 10008 if (!HAS_DISPLAY(i915)) 10009 return; 10010 10011 /* 10012 * Due to the hpd irq storm handling the hotplug work can re-arm the 10013 * poll handlers. Hence disable polling after hpd handling is shut down. 10014 */ 10015 intel_hpd_poll_fini(i915); 10016 10017 /* 10018 * MST topology needs to be suspended so we don't have any calls to 10019 * fbdev after it's finalized. MST will be destroyed later as part of 10020 * drm_mode_config_cleanup() 10021 */ 10022 intel_dp_mst_suspend(i915); 10023 10024 /* poll work can call into fbdev, hence clean that up afterwards */ 10025 intel_fbdev_fini(i915); 10026 10027 intel_unregister_dsm_handler(); 10028 10029 /* flush any delayed tasks or pending work */ 10030 flush_scheduled_work(); 10031 10032 intel_hdcp_component_fini(i915); 10033 10034 intel_mode_config_cleanup(i915); 10035 10036 intel_overlay_cleanup(i915); 10037 10038 intel_gmbus_teardown(i915); 10039 10040 destroy_workqueue(i915->flip_wq); 10041 destroy_workqueue(i915->modeset_wq); 10042 10043 intel_fbc_cleanup(i915); 10044 } 10045 10046 /* part #3: call after gem init */ 10047 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915) 10048 { 10049 intel_dmc_ucode_fini(i915); 10050 10051 intel_power_domains_driver_remove(i915); 10052 10053 intel_vga_unregister(i915); 10054 10055 intel_bios_driver_remove(i915); 10056 } 10057 10058 bool intel_modeset_probe_defer(struct pci_dev *pdev) 10059 { 10060 struct drm_privacy_screen *privacy_screen; 10061 10062 /* 10063 * apple-gmux is needed on dual GPU MacBook Pro 10064 * to probe the panel if we're the inactive GPU. 10065 */ 10066 if (vga_switcheroo_client_probe_defer(pdev)) 10067 return true; 10068 10069 /* If the LCD panel has a privacy-screen, wait for it */ 10070 privacy_screen = drm_privacy_screen_get(&pdev->dev, NULL); 10071 if (IS_ERR(privacy_screen) && PTR_ERR(privacy_screen) == -EPROBE_DEFER) 10072 return true; 10073 10074 drm_privacy_screen_put(privacy_screen); 10075 10076 return false; 10077 } 10078 10079 void intel_display_driver_register(struct drm_i915_private *i915) 10080 { 10081 if (!HAS_DISPLAY(i915)) 10082 return; 10083 10084 intel_display_debugfs_register(i915); 10085 10086 /* Must be done after probing outputs */ 10087 intel_opregion_register(i915); 10088 acpi_video_register(); 10089 10090 intel_audio_init(i915); 10091 10092 /* 10093 * Some ports require correctly set-up hpd registers for 10094 * detection to work properly (leading to ghost connected 10095 * connector status), e.g. VGA on gm45. Hence we can only set 10096 * up the initial fbdev config after hpd irqs are fully 10097 * enabled. We do it last so that the async config cannot run 10098 * before the connectors are registered. 10099 */ 10100 intel_fbdev_initial_config_async(&i915->drm); 10101 10102 /* 10103 * We need to coordinate the hotplugs with the asynchronous 10104 * fbdev configuration, for which we use the 10105 * fbdev->async_cookie. 10106 */ 10107 drm_kms_helper_poll_init(&i915->drm); 10108 } 10109 10110 void intel_display_driver_unregister(struct drm_i915_private *i915) 10111 { 10112 if (!HAS_DISPLAY(i915)) 10113 return; 10114 10115 intel_fbdev_unregister(i915); 10116 intel_audio_deinit(i915); 10117 10118 /* 10119 * After flushing the fbdev (incl. a late async config which 10120 * will have delayed queuing of a hotplug event), then flush 10121 * the hotplug events. 10122 */ 10123 drm_kms_helper_poll_fini(&i915->drm); 10124 drm_atomic_helper_shutdown(&i915->drm); 10125 10126 acpi_video_unregister(); 10127 intel_opregion_unregister(i915); 10128 } 10129 10130 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915) 10131 { 10132 return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915); 10133 } 10134