1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <acpi/video.h> 28 #include <linux/i2c.h> 29 #include <linux/input.h> 30 #include <linux/intel-iommu.h> 31 #include <linux/kernel.h> 32 #include <linux/module.h> 33 #include <linux/dma-resv.h> 34 #include <linux/slab.h> 35 #include <linux/string_helpers.h> 36 #include <linux/vga_switcheroo.h> 37 38 #include <drm/drm_atomic.h> 39 #include <drm/drm_atomic_helper.h> 40 #include <drm/drm_atomic_uapi.h> 41 #include <drm/drm_damage_helper.h> 42 #include <drm/dp/drm_dp_helper.h> 43 #include <drm/drm_edid.h> 44 #include <drm/drm_fourcc.h> 45 #include <drm/drm_plane_helper.h> 46 #include <drm/drm_privacy_screen_consumer.h> 47 #include <drm/drm_probe_helper.h> 48 #include <drm/drm_rect.h> 49 50 #include "display/intel_audio.h" 51 #include "display/intel_crt.h" 52 #include "display/intel_ddi.h" 53 #include "display/intel_display_debugfs.h" 54 #include "display/intel_display_power.h" 55 #include "display/intel_dp.h" 56 #include "display/intel_dp_mst.h" 57 #include "display/intel_dpll.h" 58 #include "display/intel_dpll_mgr.h" 59 #include "display/intel_drrs.h" 60 #include "display/intel_dsi.h" 61 #include "display/intel_dvo.h" 62 #include "display/intel_fb.h" 63 #include "display/intel_gmbus.h" 64 #include "display/intel_hdmi.h" 65 #include "display/intel_lvds.h" 66 #include "display/intel_sdvo.h" 67 #include "display/intel_snps_phy.h" 68 #include "display/intel_tv.h" 69 #include "display/intel_vdsc.h" 70 #include "display/intel_vrr.h" 71 72 #include "gem/i915_gem_lmem.h" 73 #include "gem/i915_gem_object.h" 74 75 #include "gt/gen8_ppgtt.h" 76 77 #include "g4x_dp.h" 78 #include "g4x_hdmi.h" 79 #include "hsw_ips.h" 80 #include "i915_drv.h" 81 #include "i915_utils.h" 82 #include "icl_dsi.h" 83 #include "intel_acpi.h" 84 #include "intel_atomic.h" 85 #include "intel_atomic_plane.h" 86 #include "intel_bw.h" 87 #include "intel_cdclk.h" 88 #include "intel_color.h" 89 #include "intel_crtc.h" 90 #include "intel_crtc_state_dump.h" 91 #include "intel_de.h" 92 #include "intel_display_types.h" 93 #include "intel_dmc.h" 94 #include "intel_dp_link_training.h" 95 #include "intel_dpt.h" 96 #include "intel_fbc.h" 97 #include "intel_fbdev.h" 98 #include "intel_fdi.h" 99 #include "intel_fifo_underrun.h" 100 #include "intel_frontbuffer.h" 101 #include "intel_hdcp.h" 102 #include "intel_hotplug.h" 103 #include "intel_modeset_verify.h" 104 #include "intel_overlay.h" 105 #include "intel_panel.h" 106 #include "intel_pch_display.h" 107 #include "intel_pch_refclk.h" 108 #include "intel_pcode.h" 109 #include "intel_pipe_crc.h" 110 #include "intel_plane_initial.h" 111 #include "intel_pm.h" 112 #include "intel_pps.h" 113 #include "intel_psr.h" 114 #include "intel_quirks.h" 115 #include "intel_sprite.h" 116 #include "intel_tc.h" 117 #include "intel_vga.h" 118 #include "i9xx_plane.h" 119 #include "skl_scaler.h" 120 #include "skl_universal_plane.h" 121 #include "vlv_dsi.h" 122 #include "vlv_dsi_pll.h" 123 #include "vlv_dsi_regs.h" 124 #include "vlv_sideband.h" 125 126 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state); 127 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state); 128 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state); 129 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state); 130 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state); 131 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state); 132 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state); 133 static void intel_modeset_setup_hw_state(struct drm_device *dev, 134 struct drm_modeset_acquire_ctx *ctx); 135 136 /** 137 * intel_update_watermarks - update FIFO watermark values based on current modes 138 * @dev_priv: i915 device 139 * 140 * Calculate watermark values for the various WM regs based on current mode 141 * and plane configuration. 142 * 143 * There are several cases to deal with here: 144 * - normal (i.e. non-self-refresh) 145 * - self-refresh (SR) mode 146 * - lines are large relative to FIFO size (buffer can hold up to 2) 147 * - lines are small relative to FIFO size (buffer can hold more than 2 148 * lines), so need to account for TLB latency 149 * 150 * The normal calculation is: 151 * watermark = dotclock * bytes per pixel * latency 152 * where latency is platform & configuration dependent (we assume pessimal 153 * values here). 154 * 155 * The SR calculation is: 156 * watermark = (trunc(latency/line time)+1) * surface width * 157 * bytes per pixel 158 * where 159 * line time = htotal / dotclock 160 * surface width = hdisplay for normal plane and 64 for cursor 161 * and latency is assumed to be high, as above. 162 * 163 * The final value programmed to the register should always be rounded up, 164 * and include an extra 2 entries to account for clock crossings. 165 * 166 * We don't use the sprite, so we can ignore that. And on Crestline we have 167 * to set the non-SR watermarks to 8. 168 */ 169 static void intel_update_watermarks(struct drm_i915_private *dev_priv) 170 { 171 if (dev_priv->wm_disp->update_wm) 172 dev_priv->wm_disp->update_wm(dev_priv); 173 } 174 175 static int intel_compute_pipe_wm(struct intel_atomic_state *state, 176 struct intel_crtc *crtc) 177 { 178 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 179 if (dev_priv->wm_disp->compute_pipe_wm) 180 return dev_priv->wm_disp->compute_pipe_wm(state, crtc); 181 return 0; 182 } 183 184 static int intel_compute_intermediate_wm(struct intel_atomic_state *state, 185 struct intel_crtc *crtc) 186 { 187 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 188 if (!dev_priv->wm_disp->compute_intermediate_wm) 189 return 0; 190 if (drm_WARN_ON(&dev_priv->drm, 191 !dev_priv->wm_disp->compute_pipe_wm)) 192 return 0; 193 return dev_priv->wm_disp->compute_intermediate_wm(state, crtc); 194 } 195 196 static bool intel_initial_watermarks(struct intel_atomic_state *state, 197 struct intel_crtc *crtc) 198 { 199 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 200 if (dev_priv->wm_disp->initial_watermarks) { 201 dev_priv->wm_disp->initial_watermarks(state, crtc); 202 return true; 203 } 204 return false; 205 } 206 207 static void intel_atomic_update_watermarks(struct intel_atomic_state *state, 208 struct intel_crtc *crtc) 209 { 210 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 211 if (dev_priv->wm_disp->atomic_update_watermarks) 212 dev_priv->wm_disp->atomic_update_watermarks(state, crtc); 213 } 214 215 static void intel_optimize_watermarks(struct intel_atomic_state *state, 216 struct intel_crtc *crtc) 217 { 218 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 219 if (dev_priv->wm_disp->optimize_watermarks) 220 dev_priv->wm_disp->optimize_watermarks(state, crtc); 221 } 222 223 static int intel_compute_global_watermarks(struct intel_atomic_state *state) 224 { 225 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 226 if (dev_priv->wm_disp->compute_global_watermarks) 227 return dev_priv->wm_disp->compute_global_watermarks(state); 228 return 0; 229 } 230 231 /* returns HPLL frequency in kHz */ 232 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) 233 { 234 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; 235 236 /* Obtain SKU information */ 237 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & 238 CCK_FUSE_HPLL_FREQ_MASK; 239 240 return vco_freq[hpll_freq] * 1000; 241 } 242 243 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 244 const char *name, u32 reg, int ref_freq) 245 { 246 u32 val; 247 int divider; 248 249 val = vlv_cck_read(dev_priv, reg); 250 divider = val & CCK_FREQUENCY_VALUES; 251 252 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != 253 (divider << CCK_FREQUENCY_STATUS_SHIFT), 254 "%s change in progress\n", name); 255 256 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); 257 } 258 259 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 260 const char *name, u32 reg) 261 { 262 int hpll; 263 264 vlv_cck_get(dev_priv); 265 266 if (dev_priv->hpll_freq == 0) 267 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); 268 269 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); 270 271 vlv_cck_put(dev_priv); 272 273 return hpll; 274 } 275 276 static void intel_update_czclk(struct drm_i915_private *dev_priv) 277 { 278 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) 279 return; 280 281 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", 282 CCK_CZ_CLOCK_CONTROL); 283 284 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", 285 dev_priv->czclk_freq); 286 } 287 288 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state) 289 { 290 return (crtc_state->active_planes & 291 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0; 292 } 293 294 /* WA Display #0827: Gen9:all */ 295 static void 296 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) 297 { 298 if (enable) 299 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 300 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS); 301 else 302 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 303 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS)); 304 } 305 306 /* Wa_2006604312:icl,ehl */ 307 static void 308 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 309 bool enable) 310 { 311 if (enable) 312 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 313 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS); 314 else 315 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 316 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS); 317 } 318 319 /* Wa_1604331009:icl,jsl,ehl */ 320 static void 321 icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 322 bool enable) 323 { 324 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), CURSOR_GATING_DIS, 325 enable ? CURSOR_GATING_DIS : 0); 326 } 327 328 static bool 329 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state) 330 { 331 return crtc_state->master_transcoder != INVALID_TRANSCODER; 332 } 333 334 static bool 335 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state) 336 { 337 return crtc_state->sync_mode_slaves_mask != 0; 338 } 339 340 bool 341 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state) 342 { 343 return is_trans_port_sync_master(crtc_state) || 344 is_trans_port_sync_slave(crtc_state); 345 } 346 347 static enum pipe bigjoiner_master_pipe(const struct intel_crtc_state *crtc_state) 348 { 349 return ffs(crtc_state->bigjoiner_pipes) - 1; 350 } 351 352 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state) 353 { 354 if (crtc_state->bigjoiner_pipes) 355 return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state)); 356 else 357 return 0; 358 } 359 360 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state) 361 { 362 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 363 364 return crtc_state->bigjoiner_pipes && 365 crtc->pipe != bigjoiner_master_pipe(crtc_state); 366 } 367 368 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state) 369 { 370 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 371 372 return crtc_state->bigjoiner_pipes && 373 crtc->pipe == bigjoiner_master_pipe(crtc_state); 374 } 375 376 static int intel_bigjoiner_num_pipes(const struct intel_crtc_state *crtc_state) 377 { 378 return hweight8(crtc_state->bigjoiner_pipes); 379 } 380 381 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state) 382 { 383 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 384 385 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 386 return intel_crtc_for_pipe(i915, bigjoiner_master_pipe(crtc_state)); 387 else 388 return to_intel_crtc(crtc_state->uapi.crtc); 389 } 390 391 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv, 392 enum pipe pipe) 393 { 394 i915_reg_t reg = PIPEDSL(pipe); 395 u32 line1, line2; 396 397 line1 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK; 398 msleep(5); 399 line2 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK; 400 401 return line1 != line2; 402 } 403 404 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state) 405 { 406 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 407 enum pipe pipe = crtc->pipe; 408 409 /* Wait for the display line to settle/start moving */ 410 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100)) 411 drm_err(&dev_priv->drm, 412 "pipe %c scanline %s wait timed out\n", 413 pipe_name(pipe), str_on_off(state)); 414 } 415 416 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc) 417 { 418 wait_for_pipe_scanline_moving(crtc, false); 419 } 420 421 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc) 422 { 423 wait_for_pipe_scanline_moving(crtc, true); 424 } 425 426 static void 427 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) 428 { 429 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 430 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 431 432 if (DISPLAY_VER(dev_priv) >= 4) { 433 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 434 435 /* Wait for the Pipe State to go off */ 436 if (intel_de_wait_for_clear(dev_priv, PIPECONF(cpu_transcoder), 437 PIPECONF_STATE_ENABLE, 100)) 438 drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n"); 439 } else { 440 intel_wait_for_pipe_scanline_stopped(crtc); 441 } 442 } 443 444 void assert_transcoder(struct drm_i915_private *dev_priv, 445 enum transcoder cpu_transcoder, bool state) 446 { 447 bool cur_state; 448 enum intel_display_power_domain power_domain; 449 intel_wakeref_t wakeref; 450 451 /* we keep both pipes enabled on 830 */ 452 if (IS_I830(dev_priv)) 453 state = true; 454 455 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 456 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 457 if (wakeref) { 458 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); 459 cur_state = !!(val & PIPECONF_ENABLE); 460 461 intel_display_power_put(dev_priv, power_domain, wakeref); 462 } else { 463 cur_state = false; 464 } 465 466 I915_STATE_WARN(cur_state != state, 467 "transcoder %s assertion failure (expected %s, current %s)\n", 468 transcoder_name(cpu_transcoder), 469 str_on_off(state), str_on_off(cur_state)); 470 } 471 472 static void assert_plane(struct intel_plane *plane, bool state) 473 { 474 enum pipe pipe; 475 bool cur_state; 476 477 cur_state = plane->get_hw_state(plane, &pipe); 478 479 I915_STATE_WARN(cur_state != state, 480 "%s assertion failure (expected %s, current %s)\n", 481 plane->base.name, str_on_off(state), 482 str_on_off(cur_state)); 483 } 484 485 #define assert_plane_enabled(p) assert_plane(p, true) 486 #define assert_plane_disabled(p) assert_plane(p, false) 487 488 static void assert_planes_disabled(struct intel_crtc *crtc) 489 { 490 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 491 struct intel_plane *plane; 492 493 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) 494 assert_plane_disabled(plane); 495 } 496 497 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 498 struct intel_digital_port *dig_port, 499 unsigned int expected_mask) 500 { 501 u32 port_mask; 502 i915_reg_t dpll_reg; 503 504 switch (dig_port->base.port) { 505 default: 506 MISSING_CASE(dig_port->base.port); 507 fallthrough; 508 case PORT_B: 509 port_mask = DPLL_PORTB_READY_MASK; 510 dpll_reg = DPLL(0); 511 break; 512 case PORT_C: 513 port_mask = DPLL_PORTC_READY_MASK; 514 dpll_reg = DPLL(0); 515 expected_mask <<= 4; 516 break; 517 case PORT_D: 518 port_mask = DPLL_PORTD_READY_MASK; 519 dpll_reg = DPIO_PHY_STATUS; 520 break; 521 } 522 523 if (intel_de_wait_for_register(dev_priv, dpll_reg, 524 port_mask, expected_mask, 1000)) 525 drm_WARN(&dev_priv->drm, 1, 526 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", 527 dig_port->base.base.base.id, dig_port->base.base.name, 528 intel_de_read(dev_priv, dpll_reg) & port_mask, 529 expected_mask); 530 } 531 532 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) 533 { 534 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 535 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 536 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 537 enum pipe pipe = crtc->pipe; 538 i915_reg_t reg; 539 u32 val; 540 541 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe)); 542 543 assert_planes_disabled(crtc); 544 545 /* 546 * A pipe without a PLL won't actually be able to drive bits from 547 * a plane. On ILK+ the pipe PLLs are integrated, so we don't 548 * need the check. 549 */ 550 if (HAS_GMCH(dev_priv)) { 551 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI)) 552 assert_dsi_pll_enabled(dev_priv); 553 else 554 assert_pll_enabled(dev_priv, pipe); 555 } else { 556 if (new_crtc_state->has_pch_encoder) { 557 /* if driving the PCH, we need FDI enabled */ 558 assert_fdi_rx_pll_enabled(dev_priv, 559 intel_crtc_pch_transcoder(crtc)); 560 assert_fdi_tx_pll_enabled(dev_priv, 561 (enum pipe) cpu_transcoder); 562 } 563 /* FIXME: assert CPU port conditions for SNB+ */ 564 } 565 566 /* Wa_22012358565:adl-p */ 567 if (DISPLAY_VER(dev_priv) == 13) 568 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe), 569 0, PIPE_ARB_USE_PROG_SLOTS); 570 571 reg = PIPECONF(cpu_transcoder); 572 val = intel_de_read(dev_priv, reg); 573 if (val & PIPECONF_ENABLE) { 574 /* we keep both pipes enabled on 830 */ 575 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv)); 576 return; 577 } 578 579 intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE); 580 intel_de_posting_read(dev_priv, reg); 581 582 /* 583 * Until the pipe starts PIPEDSL reads will return a stale value, 584 * which causes an apparent vblank timestamp jump when PIPEDSL 585 * resets to its proper value. That also messes up the frame count 586 * when it's derived from the timestamps. So let's wait for the 587 * pipe to start properly before we call drm_crtc_vblank_on() 588 */ 589 if (intel_crtc_max_vblank_count(new_crtc_state) == 0) 590 intel_wait_for_pipe_scanline_moving(crtc); 591 } 592 593 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) 594 { 595 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 596 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 597 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 598 enum pipe pipe = crtc->pipe; 599 i915_reg_t reg; 600 u32 val; 601 602 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe)); 603 604 /* 605 * Make sure planes won't keep trying to pump pixels to us, 606 * or we might hang the display. 607 */ 608 assert_planes_disabled(crtc); 609 610 reg = PIPECONF(cpu_transcoder); 611 val = intel_de_read(dev_priv, reg); 612 if ((val & PIPECONF_ENABLE) == 0) 613 return; 614 615 /* 616 * Double wide has implications for planes 617 * so best keep it disabled when not needed. 618 */ 619 if (old_crtc_state->double_wide) 620 val &= ~PIPECONF_DOUBLE_WIDE; 621 622 /* Don't disable pipe or pipe PLLs if needed */ 623 if (!IS_I830(dev_priv)) 624 val &= ~PIPECONF_ENABLE; 625 626 if (DISPLAY_VER(dev_priv) >= 12) 627 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 628 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 629 630 intel_de_write(dev_priv, reg, val); 631 if ((val & PIPECONF_ENABLE) == 0) 632 intel_wait_for_pipe_off(old_crtc_state); 633 } 634 635 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) 636 { 637 unsigned int size = 0; 638 int i; 639 640 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) 641 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width; 642 643 return size; 644 } 645 646 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info) 647 { 648 unsigned int size = 0; 649 int i; 650 651 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) { 652 unsigned int plane_size; 653 654 if (rem_info->plane[i].linear) 655 plane_size = rem_info->plane[i].size; 656 else 657 plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height; 658 659 if (plane_size == 0) 660 continue; 661 662 if (rem_info->plane_alignment) 663 size = ALIGN(size, rem_info->plane_alignment); 664 665 size += plane_size; 666 } 667 668 return size; 669 } 670 671 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) 672 { 673 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 674 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 675 676 return DISPLAY_VER(dev_priv) < 4 || 677 (plane->fbc && 678 plane_state->view.gtt.type == I915_GGTT_VIEW_NORMAL); 679 } 680 681 /* 682 * Convert the x/y offsets into a linear offset. 683 * Only valid with 0/180 degree rotation, which is fine since linear 684 * offset is only used with linear buffers on pre-hsw and tiled buffers 685 * with gen2/3, and 90/270 degree rotations isn't supported on any of them. 686 */ 687 u32 intel_fb_xy_to_linear(int x, int y, 688 const struct intel_plane_state *state, 689 int color_plane) 690 { 691 const struct drm_framebuffer *fb = state->hw.fb; 692 unsigned int cpp = fb->format->cpp[color_plane]; 693 unsigned int pitch = state->view.color_plane[color_plane].mapping_stride; 694 695 return y * pitch + x * cpp; 696 } 697 698 /* 699 * Add the x/y offsets derived from fb->offsets[] to the user 700 * specified plane src x/y offsets. The resulting x/y offsets 701 * specify the start of scanout from the beginning of the gtt mapping. 702 */ 703 void intel_add_fb_offsets(int *x, int *y, 704 const struct intel_plane_state *state, 705 int color_plane) 706 707 { 708 *x += state->view.color_plane[color_plane].x; 709 *y += state->view.color_plane[color_plane].y; 710 } 711 712 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 713 u32 pixel_format, u64 modifier) 714 { 715 struct intel_crtc *crtc; 716 struct intel_plane *plane; 717 718 if (!HAS_DISPLAY(dev_priv)) 719 return 0; 720 721 /* 722 * We assume the primary plane for pipe A has 723 * the highest stride limits of them all, 724 * if in case pipe A is disabled, use the first pipe from pipe_mask. 725 */ 726 crtc = intel_first_crtc(dev_priv); 727 if (!crtc) 728 return 0; 729 730 plane = to_intel_plane(crtc->base.primary); 731 732 return plane->max_stride(plane, pixel_format, modifier, 733 DRM_MODE_ROTATE_0); 734 } 735 736 static void 737 intel_set_plane_visible(struct intel_crtc_state *crtc_state, 738 struct intel_plane_state *plane_state, 739 bool visible) 740 { 741 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 742 743 plane_state->uapi.visible = visible; 744 745 if (visible) 746 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base); 747 else 748 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base); 749 } 750 751 static void fixup_plane_bitmasks(struct intel_crtc_state *crtc_state) 752 { 753 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 754 struct drm_plane *plane; 755 756 /* 757 * Active_planes aliases if multiple "primary" or cursor planes 758 * have been used on the same (or wrong) pipe. plane_mask uses 759 * unique ids, hence we can use that to reconstruct active_planes. 760 */ 761 crtc_state->enabled_planes = 0; 762 crtc_state->active_planes = 0; 763 764 drm_for_each_plane_mask(plane, &dev_priv->drm, 765 crtc_state->uapi.plane_mask) { 766 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id); 767 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id); 768 } 769 } 770 771 void intel_plane_disable_noatomic(struct intel_crtc *crtc, 772 struct intel_plane *plane) 773 { 774 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 775 struct intel_crtc_state *crtc_state = 776 to_intel_crtc_state(crtc->base.state); 777 struct intel_plane_state *plane_state = 778 to_intel_plane_state(plane->base.state); 779 780 drm_dbg_kms(&dev_priv->drm, 781 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n", 782 plane->base.base.id, plane->base.name, 783 crtc->base.base.id, crtc->base.name); 784 785 intel_set_plane_visible(crtc_state, plane_state, false); 786 fixup_plane_bitmasks(crtc_state); 787 crtc_state->data_rate[plane->id] = 0; 788 crtc_state->data_rate_y[plane->id] = 0; 789 crtc_state->rel_data_rate[plane->id] = 0; 790 crtc_state->rel_data_rate_y[plane->id] = 0; 791 crtc_state->min_cdclk[plane->id] = 0; 792 793 if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 && 794 hsw_ips_disable(crtc_state)) { 795 crtc_state->ips_enabled = false; 796 intel_crtc_wait_for_next_vblank(crtc); 797 } 798 799 /* 800 * Vblank time updates from the shadow to live plane control register 801 * are blocked if the memory self-refresh mode is active at that 802 * moment. So to make sure the plane gets truly disabled, disable 803 * first the self-refresh mode. The self-refresh enable bit in turn 804 * will be checked/applied by the HW only at the next frame start 805 * event which is after the vblank start event, so we need to have a 806 * wait-for-vblank between disabling the plane and the pipe. 807 */ 808 if (HAS_GMCH(dev_priv) && 809 intel_set_memory_cxsr(dev_priv, false)) 810 intel_crtc_wait_for_next_vblank(crtc); 811 812 /* 813 * Gen2 reports pipe underruns whenever all planes are disabled. 814 * So disable underrun reporting before all the planes get disabled. 815 */ 816 if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes) 817 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); 818 819 intel_plane_disable_arm(plane, crtc_state); 820 intel_crtc_wait_for_next_vblank(crtc); 821 } 822 823 unsigned int 824 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state) 825 { 826 int x = 0, y = 0; 827 828 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, 829 plane_state->view.color_plane[0].offset, 0); 830 831 return y; 832 } 833 834 static int 835 __intel_display_resume(struct drm_i915_private *i915, 836 struct drm_atomic_state *state, 837 struct drm_modeset_acquire_ctx *ctx) 838 { 839 struct drm_crtc_state *crtc_state; 840 struct drm_crtc *crtc; 841 int i, ret; 842 843 intel_modeset_setup_hw_state(&i915->drm, ctx); 844 intel_vga_redisable(i915); 845 846 if (!state) 847 return 0; 848 849 /* 850 * We've duplicated the state, pointers to the old state are invalid. 851 * 852 * Don't attempt to use the old state until we commit the duplicated state. 853 */ 854 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 855 /* 856 * Force recalculation even if we restore 857 * current state. With fast modeset this may not result 858 * in a modeset when the state is compatible. 859 */ 860 crtc_state->mode_changed = true; 861 } 862 863 /* ignore any reset values/BIOS leftovers in the WM registers */ 864 if (!HAS_GMCH(i915)) 865 to_intel_atomic_state(state)->skip_intermediate_wm = true; 866 867 ret = drm_atomic_helper_commit_duplicated_state(state, ctx); 868 869 drm_WARN_ON(&i915->drm, ret == -EDEADLK); 870 871 return ret; 872 } 873 874 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) 875 { 876 return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display && 877 intel_has_gpu_reset(to_gt(dev_priv))); 878 } 879 880 void intel_display_prepare_reset(struct drm_i915_private *dev_priv) 881 { 882 struct drm_device *dev = &dev_priv->drm; 883 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; 884 struct drm_atomic_state *state; 885 int ret; 886 887 if (!HAS_DISPLAY(dev_priv)) 888 return; 889 890 /* reset doesn't touch the display */ 891 if (!dev_priv->params.force_reset_modeset_test && 892 !gpu_reset_clobbers_display(dev_priv)) 893 return; 894 895 /* We have a modeset vs reset deadlock, defensively unbreak it. */ 896 set_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags); 897 smp_mb__after_atomic(); 898 wake_up_bit(&to_gt(dev_priv)->reset.flags, I915_RESET_MODESET); 899 900 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) { 901 drm_dbg_kms(&dev_priv->drm, 902 "Modeset potentially stuck, unbreaking through wedging\n"); 903 intel_gt_set_wedged(to_gt(dev_priv)); 904 } 905 906 /* 907 * Need mode_config.mutex so that we don't 908 * trample ongoing ->detect() and whatnot. 909 */ 910 mutex_lock(&dev->mode_config.mutex); 911 drm_modeset_acquire_init(ctx, 0); 912 while (1) { 913 ret = drm_modeset_lock_all_ctx(dev, ctx); 914 if (ret != -EDEADLK) 915 break; 916 917 drm_modeset_backoff(ctx); 918 } 919 /* 920 * Disabling the crtcs gracefully seems nicer. Also the 921 * g33 docs say we should at least disable all the planes. 922 */ 923 state = drm_atomic_helper_duplicate_state(dev, ctx); 924 if (IS_ERR(state)) { 925 ret = PTR_ERR(state); 926 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n", 927 ret); 928 return; 929 } 930 931 ret = drm_atomic_helper_disable_all(dev, ctx); 932 if (ret) { 933 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", 934 ret); 935 drm_atomic_state_put(state); 936 return; 937 } 938 939 dev_priv->modeset_restore_state = state; 940 state->acquire_ctx = ctx; 941 } 942 943 void intel_display_finish_reset(struct drm_i915_private *i915) 944 { 945 struct drm_modeset_acquire_ctx *ctx = &i915->reset_ctx; 946 struct drm_atomic_state *state; 947 int ret; 948 949 if (!HAS_DISPLAY(i915)) 950 return; 951 952 /* reset doesn't touch the display */ 953 if (!test_bit(I915_RESET_MODESET, &to_gt(i915)->reset.flags)) 954 return; 955 956 state = fetch_and_zero(&i915->modeset_restore_state); 957 if (!state) 958 goto unlock; 959 960 /* reset doesn't touch the display */ 961 if (!gpu_reset_clobbers_display(i915)) { 962 /* for testing only restore the display */ 963 ret = __intel_display_resume(i915, state, ctx); 964 if (ret) 965 drm_err(&i915->drm, 966 "Restoring old state failed with %i\n", ret); 967 } else { 968 /* 969 * The display has been reset as well, 970 * so need a full re-initialization. 971 */ 972 intel_pps_unlock_regs_wa(i915); 973 intel_modeset_init_hw(i915); 974 intel_init_clock_gating(i915); 975 intel_hpd_init(i915); 976 977 ret = __intel_display_resume(i915, state, ctx); 978 if (ret) 979 drm_err(&i915->drm, 980 "Restoring old state failed with %i\n", ret); 981 982 intel_hpd_poll_disable(i915); 983 } 984 985 drm_atomic_state_put(state); 986 unlock: 987 drm_modeset_drop_locks(ctx); 988 drm_modeset_acquire_fini(ctx); 989 mutex_unlock(&i915->drm.mode_config.mutex); 990 991 clear_bit_unlock(I915_RESET_MODESET, &to_gt(i915)->reset.flags); 992 } 993 994 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) 995 { 996 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 997 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 998 enum pipe pipe = crtc->pipe; 999 u32 tmp; 1000 1001 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe)); 1002 1003 /* 1004 * Display WA #1153: icl 1005 * enable hardware to bypass the alpha math 1006 * and rounding for per-pixel values 00 and 0xff 1007 */ 1008 tmp |= PER_PIXEL_ALPHA_BYPASS_EN; 1009 /* 1010 * Display WA # 1605353570: icl 1011 * Set the pixel rounding bit to 1 for allowing 1012 * passthrough of Frame buffer pixels unmodified 1013 * across pipe 1014 */ 1015 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU; 1016 1017 /* 1018 * Underrun recovery must always be disabled on display 13+. 1019 * DG2 chicken bit meaning is inverted compared to other platforms. 1020 */ 1021 if (IS_DG2(dev_priv)) 1022 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2; 1023 else if (DISPLAY_VER(dev_priv) >= 13) 1024 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP; 1025 1026 /* Wa_14010547955:dg2 */ 1027 if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER)) 1028 tmp |= DG2_RENDER_CCSTAG_4_3_EN; 1029 1030 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp); 1031 } 1032 1033 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) 1034 { 1035 struct drm_crtc *crtc; 1036 bool cleanup_done; 1037 1038 drm_for_each_crtc(crtc, &dev_priv->drm) { 1039 struct drm_crtc_commit *commit; 1040 spin_lock(&crtc->commit_lock); 1041 commit = list_first_entry_or_null(&crtc->commit_list, 1042 struct drm_crtc_commit, commit_entry); 1043 cleanup_done = commit ? 1044 try_wait_for_completion(&commit->cleanup_done) : true; 1045 spin_unlock(&crtc->commit_lock); 1046 1047 if (cleanup_done) 1048 continue; 1049 1050 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc)); 1051 1052 return true; 1053 } 1054 1055 return false; 1056 } 1057 1058 /* 1059 * Finds the encoder associated with the given CRTC. This can only be 1060 * used when we know that the CRTC isn't feeding multiple encoders! 1061 */ 1062 struct intel_encoder * 1063 intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 1064 const struct intel_crtc_state *crtc_state) 1065 { 1066 const struct drm_connector_state *connector_state; 1067 const struct drm_connector *connector; 1068 struct intel_encoder *encoder = NULL; 1069 struct intel_crtc *master_crtc; 1070 int num_encoders = 0; 1071 int i; 1072 1073 master_crtc = intel_master_crtc(crtc_state); 1074 1075 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 1076 if (connector_state->crtc != &master_crtc->base) 1077 continue; 1078 1079 encoder = to_intel_encoder(connector_state->best_encoder); 1080 num_encoders++; 1081 } 1082 1083 drm_WARN(encoder->base.dev, num_encoders != 1, 1084 "%d encoders for pipe %c\n", 1085 num_encoders, pipe_name(master_crtc->pipe)); 1086 1087 return encoder; 1088 } 1089 1090 static void cpt_verify_modeset(struct drm_i915_private *dev_priv, 1091 enum pipe pipe) 1092 { 1093 i915_reg_t dslreg = PIPEDSL(pipe); 1094 u32 temp; 1095 1096 temp = intel_de_read(dev_priv, dslreg); 1097 udelay(500); 1098 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) { 1099 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) 1100 drm_err(&dev_priv->drm, 1101 "mode set failed: pipe %c stuck\n", 1102 pipe_name(pipe)); 1103 } 1104 } 1105 1106 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state) 1107 { 1108 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1109 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1110 const struct drm_rect *dst = &crtc_state->pch_pfit.dst; 1111 enum pipe pipe = crtc->pipe; 1112 int width = drm_rect_width(dst); 1113 int height = drm_rect_height(dst); 1114 int x = dst->x1; 1115 int y = dst->y1; 1116 1117 if (!crtc_state->pch_pfit.enabled) 1118 return; 1119 1120 /* Force use of hard-coded filter coefficients 1121 * as some pre-programmed values are broken, 1122 * e.g. x201. 1123 */ 1124 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) 1125 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 1126 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe)); 1127 else 1128 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 1129 PF_FILTER_MED_3x3); 1130 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), x << 16 | y); 1131 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), width << 16 | height); 1132 } 1133 1134 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc) 1135 { 1136 if (crtc->overlay) 1137 (void) intel_overlay_switch_off(crtc->overlay); 1138 1139 /* Let userspace switch the overlay on again. In most cases userspace 1140 * has to recompute where to put it anyway. 1141 */ 1142 } 1143 1144 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state) 1145 { 1146 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1147 1148 if (!crtc_state->nv12_planes) 1149 return false; 1150 1151 /* WA Display #0827: Gen9:all */ 1152 if (DISPLAY_VER(dev_priv) == 9) 1153 return true; 1154 1155 return false; 1156 } 1157 1158 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state) 1159 { 1160 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1161 1162 /* Wa_2006604312:icl,ehl */ 1163 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11) 1164 return true; 1165 1166 return false; 1167 } 1168 1169 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state) 1170 { 1171 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1172 1173 /* Wa_1604331009:icl,jsl,ehl */ 1174 if (is_hdr_mode(crtc_state) && 1175 crtc_state->active_planes & BIT(PLANE_CURSOR) && 1176 DISPLAY_VER(dev_priv) == 11) 1177 return true; 1178 1179 return false; 1180 } 1181 1182 static void intel_async_flip_vtd_wa(struct drm_i915_private *i915, 1183 enum pipe pipe, bool enable) 1184 { 1185 if (DISPLAY_VER(i915) == 9) { 1186 /* 1187 * "Plane N strech max must be programmed to 11b (x1) 1188 * when Async flips are enabled on that plane." 1189 */ 1190 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 1191 SKL_PLANE1_STRETCH_MAX_MASK, 1192 enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8); 1193 } else { 1194 /* Also needed on HSW/BDW albeit undocumented */ 1195 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 1196 HSW_PRI_STRETCH_MAX_MASK, 1197 enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8); 1198 } 1199 } 1200 1201 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state) 1202 { 1203 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1204 1205 return crtc_state->uapi.async_flip && i915_vtd_active(i915) && 1206 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915)); 1207 } 1208 1209 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state, 1210 const struct intel_crtc_state *new_crtc_state) 1211 { 1212 return (!old_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)) && 1213 new_crtc_state->active_planes; 1214 } 1215 1216 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state, 1217 const struct intel_crtc_state *new_crtc_state) 1218 { 1219 return old_crtc_state->active_planes && 1220 (!new_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)); 1221 } 1222 1223 static void intel_post_plane_update(struct intel_atomic_state *state, 1224 struct intel_crtc *crtc) 1225 { 1226 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1227 const struct intel_crtc_state *old_crtc_state = 1228 intel_atomic_get_old_crtc_state(state, crtc); 1229 const struct intel_crtc_state *new_crtc_state = 1230 intel_atomic_get_new_crtc_state(state, crtc); 1231 enum pipe pipe = crtc->pipe; 1232 1233 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); 1234 1235 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) 1236 intel_update_watermarks(dev_priv); 1237 1238 hsw_ips_post_update(state, crtc); 1239 intel_fbc_post_update(state, crtc); 1240 1241 if (needs_async_flip_vtd_wa(old_crtc_state) && 1242 !needs_async_flip_vtd_wa(new_crtc_state)) 1243 intel_async_flip_vtd_wa(dev_priv, pipe, false); 1244 1245 if (needs_nv12_wa(old_crtc_state) && 1246 !needs_nv12_wa(new_crtc_state)) 1247 skl_wa_827(dev_priv, pipe, false); 1248 1249 if (needs_scalerclk_wa(old_crtc_state) && 1250 !needs_scalerclk_wa(new_crtc_state)) 1251 icl_wa_scalerclkgating(dev_priv, pipe, false); 1252 1253 if (needs_cursorclk_wa(old_crtc_state) && 1254 !needs_cursorclk_wa(new_crtc_state)) 1255 icl_wa_cursorclkgating(dev_priv, pipe, false); 1256 1257 intel_drrs_activate(new_crtc_state); 1258 } 1259 1260 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state, 1261 struct intel_crtc *crtc) 1262 { 1263 const struct intel_crtc_state *crtc_state = 1264 intel_atomic_get_new_crtc_state(state, crtc); 1265 u8 update_planes = crtc_state->update_planes; 1266 const struct intel_plane_state *plane_state; 1267 struct intel_plane *plane; 1268 int i; 1269 1270 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1271 if (plane->pipe == crtc->pipe && 1272 update_planes & BIT(plane->id)) 1273 plane->enable_flip_done(plane); 1274 } 1275 } 1276 1277 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state, 1278 struct intel_crtc *crtc) 1279 { 1280 const struct intel_crtc_state *crtc_state = 1281 intel_atomic_get_new_crtc_state(state, crtc); 1282 u8 update_planes = crtc_state->update_planes; 1283 const struct intel_plane_state *plane_state; 1284 struct intel_plane *plane; 1285 int i; 1286 1287 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1288 if (plane->pipe == crtc->pipe && 1289 update_planes & BIT(plane->id)) 1290 plane->disable_flip_done(plane); 1291 } 1292 } 1293 1294 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state, 1295 struct intel_crtc *crtc) 1296 { 1297 const struct intel_crtc_state *old_crtc_state = 1298 intel_atomic_get_old_crtc_state(state, crtc); 1299 const struct intel_crtc_state *new_crtc_state = 1300 intel_atomic_get_new_crtc_state(state, crtc); 1301 u8 update_planes = new_crtc_state->update_planes; 1302 const struct intel_plane_state *old_plane_state; 1303 struct intel_plane *plane; 1304 bool need_vbl_wait = false; 1305 int i; 1306 1307 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1308 if (plane->need_async_flip_disable_wa && 1309 plane->pipe == crtc->pipe && 1310 update_planes & BIT(plane->id)) { 1311 /* 1312 * Apart from the async flip bit we want to 1313 * preserve the old state for the plane. 1314 */ 1315 plane->async_flip(plane, old_crtc_state, 1316 old_plane_state, false); 1317 need_vbl_wait = true; 1318 } 1319 } 1320 1321 if (need_vbl_wait) 1322 intel_crtc_wait_for_next_vblank(crtc); 1323 } 1324 1325 static void intel_pre_plane_update(struct intel_atomic_state *state, 1326 struct intel_crtc *crtc) 1327 { 1328 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1329 const struct intel_crtc_state *old_crtc_state = 1330 intel_atomic_get_old_crtc_state(state, crtc); 1331 const struct intel_crtc_state *new_crtc_state = 1332 intel_atomic_get_new_crtc_state(state, crtc); 1333 enum pipe pipe = crtc->pipe; 1334 1335 intel_drrs_deactivate(old_crtc_state); 1336 1337 intel_psr_pre_plane_update(state, crtc); 1338 1339 if (hsw_ips_pre_update(state, crtc)) 1340 intel_crtc_wait_for_next_vblank(crtc); 1341 1342 if (intel_fbc_pre_update(state, crtc)) 1343 intel_crtc_wait_for_next_vblank(crtc); 1344 1345 if (!needs_async_flip_vtd_wa(old_crtc_state) && 1346 needs_async_flip_vtd_wa(new_crtc_state)) 1347 intel_async_flip_vtd_wa(dev_priv, pipe, true); 1348 1349 /* Display WA 827 */ 1350 if (!needs_nv12_wa(old_crtc_state) && 1351 needs_nv12_wa(new_crtc_state)) 1352 skl_wa_827(dev_priv, pipe, true); 1353 1354 /* Wa_2006604312:icl,ehl */ 1355 if (!needs_scalerclk_wa(old_crtc_state) && 1356 needs_scalerclk_wa(new_crtc_state)) 1357 icl_wa_scalerclkgating(dev_priv, pipe, true); 1358 1359 /* Wa_1604331009:icl,jsl,ehl */ 1360 if (!needs_cursorclk_wa(old_crtc_state) && 1361 needs_cursorclk_wa(new_crtc_state)) 1362 icl_wa_cursorclkgating(dev_priv, pipe, true); 1363 1364 /* 1365 * Vblank time updates from the shadow to live plane control register 1366 * are blocked if the memory self-refresh mode is active at that 1367 * moment. So to make sure the plane gets truly disabled, disable 1368 * first the self-refresh mode. The self-refresh enable bit in turn 1369 * will be checked/applied by the HW only at the next frame start 1370 * event which is after the vblank start event, so we need to have a 1371 * wait-for-vblank between disabling the plane and the pipe. 1372 */ 1373 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active && 1374 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) 1375 intel_crtc_wait_for_next_vblank(crtc); 1376 1377 /* 1378 * IVB workaround: must disable low power watermarks for at least 1379 * one frame before enabling scaling. LP watermarks can be re-enabled 1380 * when scaling is disabled. 1381 * 1382 * WaCxSRDisabledForSpriteScaling:ivb 1383 */ 1384 if (old_crtc_state->hw.active && 1385 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv)) 1386 intel_crtc_wait_for_next_vblank(crtc); 1387 1388 /* 1389 * If we're doing a modeset we don't need to do any 1390 * pre-vblank watermark programming here. 1391 */ 1392 if (!intel_crtc_needs_modeset(new_crtc_state)) { 1393 /* 1394 * For platforms that support atomic watermarks, program the 1395 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these 1396 * will be the intermediate values that are safe for both pre- and 1397 * post- vblank; when vblank happens, the 'active' values will be set 1398 * to the final 'target' values and we'll do this again to get the 1399 * optimal watermarks. For gen9+ platforms, the values we program here 1400 * will be the final target values which will get automatically latched 1401 * at vblank time; no further programming will be necessary. 1402 * 1403 * If a platform hasn't been transitioned to atomic watermarks yet, 1404 * we'll continue to update watermarks the old way, if flags tell 1405 * us to. 1406 */ 1407 if (!intel_initial_watermarks(state, crtc)) 1408 if (new_crtc_state->update_wm_pre) 1409 intel_update_watermarks(dev_priv); 1410 } 1411 1412 /* 1413 * Gen2 reports pipe underruns whenever all planes are disabled. 1414 * So disable underrun reporting before all the planes get disabled. 1415 * 1416 * We do this after .initial_watermarks() so that we have a 1417 * chance of catching underruns with the intermediate watermarks 1418 * vs. the old plane configuration. 1419 */ 1420 if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state)) 1421 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1422 1423 /* 1424 * WA for platforms where async address update enable bit 1425 * is double buffered and only latched at start of vblank. 1426 */ 1427 if (old_crtc_state->uapi.async_flip && !new_crtc_state->uapi.async_flip) 1428 intel_crtc_async_flip_disable_wa(state, crtc); 1429 } 1430 1431 static void intel_crtc_disable_planes(struct intel_atomic_state *state, 1432 struct intel_crtc *crtc) 1433 { 1434 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1435 const struct intel_crtc_state *new_crtc_state = 1436 intel_atomic_get_new_crtc_state(state, crtc); 1437 unsigned int update_mask = new_crtc_state->update_planes; 1438 const struct intel_plane_state *old_plane_state; 1439 struct intel_plane *plane; 1440 unsigned fb_bits = 0; 1441 int i; 1442 1443 intel_crtc_dpms_overlay_disable(crtc); 1444 1445 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1446 if (crtc->pipe != plane->pipe || 1447 !(update_mask & BIT(plane->id))) 1448 continue; 1449 1450 intel_plane_disable_arm(plane, new_crtc_state); 1451 1452 if (old_plane_state->uapi.visible) 1453 fb_bits |= plane->frontbuffer_bit; 1454 } 1455 1456 intel_frontbuffer_flip(dev_priv, fb_bits); 1457 } 1458 1459 /* 1460 * intel_connector_primary_encoder - get the primary encoder for a connector 1461 * @connector: connector for which to return the encoder 1462 * 1463 * Returns the primary encoder for a connector. There is a 1:1 mapping from 1464 * all connectors to their encoder, except for DP-MST connectors which have 1465 * both a virtual and a primary encoder. These DP-MST primary encoders can be 1466 * pointed to by as many DP-MST connectors as there are pipes. 1467 */ 1468 static struct intel_encoder * 1469 intel_connector_primary_encoder(struct intel_connector *connector) 1470 { 1471 struct intel_encoder *encoder; 1472 1473 if (connector->mst_port) 1474 return &dp_to_dig_port(connector->mst_port)->base; 1475 1476 encoder = intel_attached_encoder(connector); 1477 drm_WARN_ON(connector->base.dev, !encoder); 1478 1479 return encoder; 1480 } 1481 1482 static void intel_encoders_update_prepare(struct intel_atomic_state *state) 1483 { 1484 struct drm_i915_private *i915 = to_i915(state->base.dev); 1485 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 1486 struct intel_crtc *crtc; 1487 struct drm_connector_state *new_conn_state; 1488 struct drm_connector *connector; 1489 int i; 1490 1491 /* 1492 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits. 1493 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook. 1494 */ 1495 if (i915->dpll.mgr) { 1496 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1497 if (intel_crtc_needs_modeset(new_crtc_state)) 1498 continue; 1499 1500 new_crtc_state->shared_dpll = old_crtc_state->shared_dpll; 1501 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state; 1502 } 1503 } 1504 1505 if (!state->modeset) 1506 return; 1507 1508 for_each_new_connector_in_state(&state->base, connector, new_conn_state, 1509 i) { 1510 struct intel_connector *intel_connector; 1511 struct intel_encoder *encoder; 1512 struct intel_crtc *crtc; 1513 1514 if (!intel_connector_needs_modeset(state, connector)) 1515 continue; 1516 1517 intel_connector = to_intel_connector(connector); 1518 encoder = intel_connector_primary_encoder(intel_connector); 1519 if (!encoder->update_prepare) 1520 continue; 1521 1522 crtc = new_conn_state->crtc ? 1523 to_intel_crtc(new_conn_state->crtc) : NULL; 1524 encoder->update_prepare(state, encoder, crtc); 1525 } 1526 } 1527 1528 static void intel_encoders_update_complete(struct intel_atomic_state *state) 1529 { 1530 struct drm_connector_state *new_conn_state; 1531 struct drm_connector *connector; 1532 int i; 1533 1534 if (!state->modeset) 1535 return; 1536 1537 for_each_new_connector_in_state(&state->base, connector, new_conn_state, 1538 i) { 1539 struct intel_connector *intel_connector; 1540 struct intel_encoder *encoder; 1541 struct intel_crtc *crtc; 1542 1543 if (!intel_connector_needs_modeset(state, connector)) 1544 continue; 1545 1546 intel_connector = to_intel_connector(connector); 1547 encoder = intel_connector_primary_encoder(intel_connector); 1548 if (!encoder->update_complete) 1549 continue; 1550 1551 crtc = new_conn_state->crtc ? 1552 to_intel_crtc(new_conn_state->crtc) : NULL; 1553 encoder->update_complete(state, encoder, crtc); 1554 } 1555 } 1556 1557 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state, 1558 struct intel_crtc *crtc) 1559 { 1560 const struct intel_crtc_state *crtc_state = 1561 intel_atomic_get_new_crtc_state(state, crtc); 1562 const struct drm_connector_state *conn_state; 1563 struct drm_connector *conn; 1564 int i; 1565 1566 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1567 struct intel_encoder *encoder = 1568 to_intel_encoder(conn_state->best_encoder); 1569 1570 if (conn_state->crtc != &crtc->base) 1571 continue; 1572 1573 if (encoder->pre_pll_enable) 1574 encoder->pre_pll_enable(state, encoder, 1575 crtc_state, conn_state); 1576 } 1577 } 1578 1579 static void intel_encoders_pre_enable(struct intel_atomic_state *state, 1580 struct intel_crtc *crtc) 1581 { 1582 const struct intel_crtc_state *crtc_state = 1583 intel_atomic_get_new_crtc_state(state, crtc); 1584 const struct drm_connector_state *conn_state; 1585 struct drm_connector *conn; 1586 int i; 1587 1588 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1589 struct intel_encoder *encoder = 1590 to_intel_encoder(conn_state->best_encoder); 1591 1592 if (conn_state->crtc != &crtc->base) 1593 continue; 1594 1595 if (encoder->pre_enable) 1596 encoder->pre_enable(state, encoder, 1597 crtc_state, conn_state); 1598 } 1599 } 1600 1601 static void intel_encoders_enable(struct intel_atomic_state *state, 1602 struct intel_crtc *crtc) 1603 { 1604 const struct intel_crtc_state *crtc_state = 1605 intel_atomic_get_new_crtc_state(state, crtc); 1606 const struct drm_connector_state *conn_state; 1607 struct drm_connector *conn; 1608 int i; 1609 1610 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1611 struct intel_encoder *encoder = 1612 to_intel_encoder(conn_state->best_encoder); 1613 1614 if (conn_state->crtc != &crtc->base) 1615 continue; 1616 1617 if (encoder->enable) 1618 encoder->enable(state, encoder, 1619 crtc_state, conn_state); 1620 intel_opregion_notify_encoder(encoder, true); 1621 } 1622 } 1623 1624 static void intel_encoders_disable(struct intel_atomic_state *state, 1625 struct intel_crtc *crtc) 1626 { 1627 const struct intel_crtc_state *old_crtc_state = 1628 intel_atomic_get_old_crtc_state(state, crtc); 1629 const struct drm_connector_state *old_conn_state; 1630 struct drm_connector *conn; 1631 int i; 1632 1633 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1634 struct intel_encoder *encoder = 1635 to_intel_encoder(old_conn_state->best_encoder); 1636 1637 if (old_conn_state->crtc != &crtc->base) 1638 continue; 1639 1640 intel_opregion_notify_encoder(encoder, false); 1641 if (encoder->disable) 1642 encoder->disable(state, encoder, 1643 old_crtc_state, old_conn_state); 1644 } 1645 } 1646 1647 static void intel_encoders_post_disable(struct intel_atomic_state *state, 1648 struct intel_crtc *crtc) 1649 { 1650 const struct intel_crtc_state *old_crtc_state = 1651 intel_atomic_get_old_crtc_state(state, crtc); 1652 const struct drm_connector_state *old_conn_state; 1653 struct drm_connector *conn; 1654 int i; 1655 1656 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1657 struct intel_encoder *encoder = 1658 to_intel_encoder(old_conn_state->best_encoder); 1659 1660 if (old_conn_state->crtc != &crtc->base) 1661 continue; 1662 1663 if (encoder->post_disable) 1664 encoder->post_disable(state, encoder, 1665 old_crtc_state, old_conn_state); 1666 } 1667 } 1668 1669 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state, 1670 struct intel_crtc *crtc) 1671 { 1672 const struct intel_crtc_state *old_crtc_state = 1673 intel_atomic_get_old_crtc_state(state, crtc); 1674 const struct drm_connector_state *old_conn_state; 1675 struct drm_connector *conn; 1676 int i; 1677 1678 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1679 struct intel_encoder *encoder = 1680 to_intel_encoder(old_conn_state->best_encoder); 1681 1682 if (old_conn_state->crtc != &crtc->base) 1683 continue; 1684 1685 if (encoder->post_pll_disable) 1686 encoder->post_pll_disable(state, encoder, 1687 old_crtc_state, old_conn_state); 1688 } 1689 } 1690 1691 static void intel_encoders_update_pipe(struct intel_atomic_state *state, 1692 struct intel_crtc *crtc) 1693 { 1694 const struct intel_crtc_state *crtc_state = 1695 intel_atomic_get_new_crtc_state(state, crtc); 1696 const struct drm_connector_state *conn_state; 1697 struct drm_connector *conn; 1698 int i; 1699 1700 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1701 struct intel_encoder *encoder = 1702 to_intel_encoder(conn_state->best_encoder); 1703 1704 if (conn_state->crtc != &crtc->base) 1705 continue; 1706 1707 if (encoder->update_pipe) 1708 encoder->update_pipe(state, encoder, 1709 crtc_state, conn_state); 1710 } 1711 } 1712 1713 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state) 1714 { 1715 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1716 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 1717 1718 plane->disable_arm(plane, crtc_state); 1719 } 1720 1721 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1722 { 1723 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1724 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1725 1726 if (crtc_state->has_pch_encoder) { 1727 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1728 &crtc_state->fdi_m_n); 1729 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1730 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1731 &crtc_state->dp_m_n); 1732 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1733 &crtc_state->dp_m2_n2); 1734 } 1735 1736 intel_set_transcoder_timings(crtc_state); 1737 1738 ilk_set_pipeconf(crtc_state); 1739 } 1740 1741 static void ilk_crtc_enable(struct intel_atomic_state *state, 1742 struct intel_crtc *crtc) 1743 { 1744 const struct intel_crtc_state *new_crtc_state = 1745 intel_atomic_get_new_crtc_state(state, crtc); 1746 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1747 enum pipe pipe = crtc->pipe; 1748 1749 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1750 return; 1751 1752 /* 1753 * Sometimes spurious CPU pipe underruns happen during FDI 1754 * training, at least with VGA+HDMI cloning. Suppress them. 1755 * 1756 * On ILK we get an occasional spurious CPU pipe underruns 1757 * between eDP port A enable and vdd enable. Also PCH port 1758 * enable seems to result in the occasional CPU pipe underrun. 1759 * 1760 * Spurious PCH underruns also occur during PCH enabling. 1761 */ 1762 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1763 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 1764 1765 ilk_configure_cpu_transcoder(new_crtc_state); 1766 1767 intel_set_pipe_src_size(new_crtc_state); 1768 1769 crtc->active = true; 1770 1771 intel_encoders_pre_enable(state, crtc); 1772 1773 if (new_crtc_state->has_pch_encoder) { 1774 ilk_pch_pre_enable(state, crtc); 1775 } else { 1776 assert_fdi_tx_disabled(dev_priv, pipe); 1777 assert_fdi_rx_disabled(dev_priv, pipe); 1778 } 1779 1780 ilk_pfit_enable(new_crtc_state); 1781 1782 /* 1783 * On ILK+ LUT must be loaded before the pipe is running but with 1784 * clocks enabled 1785 */ 1786 intel_color_load_luts(new_crtc_state); 1787 intel_color_commit_noarm(new_crtc_state); 1788 intel_color_commit_arm(new_crtc_state); 1789 /* update DSPCNTR to configure gamma for pipe bottom color */ 1790 intel_disable_primary_plane(new_crtc_state); 1791 1792 intel_initial_watermarks(state, crtc); 1793 intel_enable_transcoder(new_crtc_state); 1794 1795 if (new_crtc_state->has_pch_encoder) 1796 ilk_pch_enable(state, crtc); 1797 1798 intel_crtc_vblank_on(new_crtc_state); 1799 1800 intel_encoders_enable(state, crtc); 1801 1802 if (HAS_PCH_CPT(dev_priv)) 1803 cpt_verify_modeset(dev_priv, pipe); 1804 1805 /* 1806 * Must wait for vblank to avoid spurious PCH FIFO underruns. 1807 * And a second vblank wait is needed at least on ILK with 1808 * some interlaced HDMI modes. Let's do the double wait always 1809 * in case there are more corner cases we don't know about. 1810 */ 1811 if (new_crtc_state->has_pch_encoder) { 1812 intel_crtc_wait_for_next_vblank(crtc); 1813 intel_crtc_wait_for_next_vblank(crtc); 1814 } 1815 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1816 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 1817 } 1818 1819 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, 1820 enum pipe pipe, bool apply) 1821 { 1822 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)); 1823 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS; 1824 1825 if (apply) 1826 val |= mask; 1827 else 1828 val &= ~mask; 1829 1830 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val); 1831 } 1832 1833 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state) 1834 { 1835 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1836 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1837 1838 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe), 1839 HSW_LINETIME(crtc_state->linetime) | 1840 HSW_IPS_LINETIME(crtc_state->ips_linetime)); 1841 } 1842 1843 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) 1844 { 1845 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1846 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1847 i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder); 1848 u32 val; 1849 1850 val = intel_de_read(dev_priv, reg); 1851 val &= ~HSW_FRAME_START_DELAY_MASK; 1852 val |= HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 1853 intel_de_write(dev_priv, reg, val); 1854 } 1855 1856 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state, 1857 const struct intel_crtc_state *crtc_state) 1858 { 1859 struct intel_crtc *master_crtc = intel_master_crtc(crtc_state); 1860 1861 /* 1862 * Enable sequence steps 1-7 on bigjoiner master 1863 */ 1864 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1865 intel_encoders_pre_pll_enable(state, master_crtc); 1866 1867 if (crtc_state->shared_dpll) 1868 intel_enable_shared_dpll(crtc_state); 1869 1870 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1871 intel_encoders_pre_enable(state, master_crtc); 1872 } 1873 1874 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1875 { 1876 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1877 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1878 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1879 1880 if (crtc_state->has_pch_encoder) { 1881 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1882 &crtc_state->fdi_m_n); 1883 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1884 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1885 &crtc_state->dp_m_n); 1886 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1887 &crtc_state->dp_m2_n2); 1888 } 1889 1890 intel_set_transcoder_timings(crtc_state); 1891 1892 if (cpu_transcoder != TRANSCODER_EDP) 1893 intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder), 1894 crtc_state->pixel_multiplier - 1); 1895 1896 hsw_set_frame_start_delay(crtc_state); 1897 1898 hsw_set_transconf(crtc_state); 1899 } 1900 1901 static void hsw_crtc_enable(struct intel_atomic_state *state, 1902 struct intel_crtc *crtc) 1903 { 1904 const struct intel_crtc_state *new_crtc_state = 1905 intel_atomic_get_new_crtc_state(state, crtc); 1906 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1907 enum pipe pipe = crtc->pipe, hsw_workaround_pipe; 1908 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 1909 bool psl_clkgate_wa; 1910 1911 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1912 return; 1913 1914 if (!new_crtc_state->bigjoiner_pipes) { 1915 intel_encoders_pre_pll_enable(state, crtc); 1916 1917 if (new_crtc_state->shared_dpll) 1918 intel_enable_shared_dpll(new_crtc_state); 1919 1920 intel_encoders_pre_enable(state, crtc); 1921 } else { 1922 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state); 1923 } 1924 1925 intel_dsc_enable(new_crtc_state); 1926 1927 if (DISPLAY_VER(dev_priv) >= 13) 1928 intel_uncompressed_joiner_enable(new_crtc_state); 1929 1930 intel_set_pipe_src_size(new_crtc_state); 1931 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 1932 bdw_set_pipemisc(new_crtc_state); 1933 1934 if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) && 1935 !transcoder_is_dsi(cpu_transcoder)) 1936 hsw_configure_cpu_transcoder(new_crtc_state); 1937 1938 crtc->active = true; 1939 1940 /* Display WA #1180: WaDisableScalarClockGating: glk */ 1941 psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 && 1942 new_crtc_state->pch_pfit.enabled; 1943 if (psl_clkgate_wa) 1944 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true); 1945 1946 if (DISPLAY_VER(dev_priv) >= 9) 1947 skl_pfit_enable(new_crtc_state); 1948 else 1949 ilk_pfit_enable(new_crtc_state); 1950 1951 /* 1952 * On ILK+ LUT must be loaded before the pipe is running but with 1953 * clocks enabled 1954 */ 1955 intel_color_load_luts(new_crtc_state); 1956 intel_color_commit_noarm(new_crtc_state); 1957 intel_color_commit_arm(new_crtc_state); 1958 /* update DSPCNTR to configure gamma/csc for pipe bottom color */ 1959 if (DISPLAY_VER(dev_priv) < 9) 1960 intel_disable_primary_plane(new_crtc_state); 1961 1962 hsw_set_linetime_wm(new_crtc_state); 1963 1964 if (DISPLAY_VER(dev_priv) >= 11) 1965 icl_set_pipe_chicken(new_crtc_state); 1966 1967 intel_initial_watermarks(state, crtc); 1968 1969 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 1970 intel_crtc_vblank_on(new_crtc_state); 1971 1972 intel_encoders_enable(state, crtc); 1973 1974 if (psl_clkgate_wa) { 1975 intel_crtc_wait_for_next_vblank(crtc); 1976 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false); 1977 } 1978 1979 /* If we change the relative order between pipe/planes enabling, we need 1980 * to change the workaround. */ 1981 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe; 1982 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { 1983 struct intel_crtc *wa_crtc; 1984 1985 wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe); 1986 1987 intel_crtc_wait_for_next_vblank(wa_crtc); 1988 intel_crtc_wait_for_next_vblank(wa_crtc); 1989 } 1990 } 1991 1992 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state) 1993 { 1994 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1995 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1996 enum pipe pipe = crtc->pipe; 1997 1998 /* To avoid upsetting the power well on haswell only disable the pfit if 1999 * it's in use. The hw state code will make sure we get this right. */ 2000 if (!old_crtc_state->pch_pfit.enabled) 2001 return; 2002 2003 intel_de_write_fw(dev_priv, PF_CTL(pipe), 0); 2004 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0); 2005 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0); 2006 } 2007 2008 static void ilk_crtc_disable(struct intel_atomic_state *state, 2009 struct intel_crtc *crtc) 2010 { 2011 const struct intel_crtc_state *old_crtc_state = 2012 intel_atomic_get_old_crtc_state(state, crtc); 2013 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2014 enum pipe pipe = crtc->pipe; 2015 2016 /* 2017 * Sometimes spurious CPU pipe underruns happen when the 2018 * pipe is already disabled, but FDI RX/TX is still enabled. 2019 * Happens at least with VGA+HDMI cloning. Suppress them. 2020 */ 2021 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 2022 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 2023 2024 intel_encoders_disable(state, crtc); 2025 2026 intel_crtc_vblank_off(old_crtc_state); 2027 2028 intel_disable_transcoder(old_crtc_state); 2029 2030 ilk_pfit_disable(old_crtc_state); 2031 2032 if (old_crtc_state->has_pch_encoder) 2033 ilk_pch_disable(state, crtc); 2034 2035 intel_encoders_post_disable(state, crtc); 2036 2037 if (old_crtc_state->has_pch_encoder) 2038 ilk_pch_post_disable(state, crtc); 2039 2040 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2041 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 2042 } 2043 2044 static void hsw_crtc_disable(struct intel_atomic_state *state, 2045 struct intel_crtc *crtc) 2046 { 2047 const struct intel_crtc_state *old_crtc_state = 2048 intel_atomic_get_old_crtc_state(state, crtc); 2049 2050 /* 2051 * FIXME collapse everything to one hook. 2052 * Need care with mst->ddi interactions. 2053 */ 2054 if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) { 2055 intel_encoders_disable(state, crtc); 2056 intel_encoders_post_disable(state, crtc); 2057 } 2058 } 2059 2060 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) 2061 { 2062 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2063 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2064 2065 if (!crtc_state->gmch_pfit.control) 2066 return; 2067 2068 /* 2069 * The panel fitter should only be adjusted whilst the pipe is disabled, 2070 * according to register description and PRM. 2071 */ 2072 drm_WARN_ON(&dev_priv->drm, 2073 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE); 2074 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 2075 2076 intel_de_write(dev_priv, PFIT_PGM_RATIOS, 2077 crtc_state->gmch_pfit.pgm_ratios); 2078 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control); 2079 2080 /* Border color in case we don't scale up to the full screen. Black by 2081 * default, change to something else for debugging. */ 2082 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); 2083 } 2084 2085 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) 2086 { 2087 if (phy == PHY_NONE) 2088 return false; 2089 else if (IS_DG2(dev_priv)) 2090 /* 2091 * DG2 outputs labelled as "combo PHY" in the bspec use 2092 * SNPS PHYs with completely different programming, 2093 * hence we always return false here. 2094 */ 2095 return false; 2096 else if (IS_ALDERLAKE_S(dev_priv)) 2097 return phy <= PHY_E; 2098 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) 2099 return phy <= PHY_D; 2100 else if (IS_JSL_EHL(dev_priv)) 2101 return phy <= PHY_C; 2102 else if (DISPLAY_VER(dev_priv) >= 11) 2103 return phy <= PHY_B; 2104 else 2105 return false; 2106 } 2107 2108 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) 2109 { 2110 if (IS_DG2(dev_priv)) 2111 /* DG2's "TC1" output uses a SNPS PHY */ 2112 return false; 2113 else if (IS_ALDERLAKE_P(dev_priv)) 2114 return phy >= PHY_F && phy <= PHY_I; 2115 else if (IS_TIGERLAKE(dev_priv)) 2116 return phy >= PHY_D && phy <= PHY_I; 2117 else if (IS_ICELAKE(dev_priv)) 2118 return phy >= PHY_C && phy <= PHY_F; 2119 else 2120 return false; 2121 } 2122 2123 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy) 2124 { 2125 if (phy == PHY_NONE) 2126 return false; 2127 else if (IS_DG2(dev_priv)) 2128 /* 2129 * All four "combo" ports and the TC1 port (PHY E) use 2130 * Synopsis PHYs. 2131 */ 2132 return phy <= PHY_E; 2133 2134 return false; 2135 } 2136 2137 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) 2138 { 2139 if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD) 2140 return PHY_D + port - PORT_D_XELPD; 2141 else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1) 2142 return PHY_F + port - PORT_TC1; 2143 else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1) 2144 return PHY_B + port - PORT_TC1; 2145 else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1) 2146 return PHY_C + port - PORT_TC1; 2147 else if (IS_JSL_EHL(i915) && port == PORT_D) 2148 return PHY_A; 2149 2150 return PHY_A + port - PORT_A; 2151 } 2152 2153 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) 2154 { 2155 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port))) 2156 return TC_PORT_NONE; 2157 2158 if (DISPLAY_VER(dev_priv) >= 12) 2159 return TC_PORT_1 + port - PORT_TC1; 2160 else 2161 return TC_PORT_1 + port - PORT_C; 2162 } 2163 2164 enum intel_display_power_domain 2165 intel_aux_power_domain(struct intel_digital_port *dig_port) 2166 { 2167 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 2168 2169 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 2170 return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch); 2171 2172 return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch); 2173 } 2174 2175 static void get_crtc_power_domains(struct intel_crtc_state *crtc_state, 2176 struct intel_power_domain_mask *mask) 2177 { 2178 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2179 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2180 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2181 struct drm_encoder *encoder; 2182 enum pipe pipe = crtc->pipe; 2183 2184 bitmap_zero(mask->bits, POWER_DOMAIN_NUM); 2185 2186 if (!crtc_state->hw.active) 2187 return; 2188 2189 set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits); 2190 set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits); 2191 if (crtc_state->pch_pfit.enabled || 2192 crtc_state->pch_pfit.force_thru) 2193 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits); 2194 2195 drm_for_each_encoder_mask(encoder, &dev_priv->drm, 2196 crtc_state->uapi.encoder_mask) { 2197 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2198 2199 set_bit(intel_encoder->power_domain, mask->bits); 2200 } 2201 2202 if (HAS_DDI(dev_priv) && crtc_state->has_audio) 2203 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits); 2204 2205 if (crtc_state->shared_dpll) 2206 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits); 2207 2208 if (crtc_state->dsc.compression_enable) 2209 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits); 2210 } 2211 2212 static void 2213 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, 2214 struct intel_power_domain_mask *old_domains) 2215 { 2216 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2217 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2218 enum intel_display_power_domain domain; 2219 struct intel_power_domain_mask domains, new_domains; 2220 2221 get_crtc_power_domains(crtc_state, &domains); 2222 2223 bitmap_andnot(new_domains.bits, 2224 domains.bits, 2225 crtc->enabled_power_domains.mask.bits, 2226 POWER_DOMAIN_NUM); 2227 bitmap_andnot(old_domains->bits, 2228 crtc->enabled_power_domains.mask.bits, 2229 domains.bits, 2230 POWER_DOMAIN_NUM); 2231 2232 for_each_power_domain(domain, &new_domains) 2233 intel_display_power_get_in_set(dev_priv, 2234 &crtc->enabled_power_domains, 2235 domain); 2236 } 2237 2238 static void modeset_put_crtc_power_domains(struct intel_crtc *crtc, 2239 struct intel_power_domain_mask *domains) 2240 { 2241 intel_display_power_put_mask_in_set(to_i915(crtc->base.dev), 2242 &crtc->enabled_power_domains, 2243 domains); 2244 } 2245 2246 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 2247 { 2248 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2249 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2250 2251 if (intel_crtc_has_dp_encoder(crtc_state)) { 2252 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 2253 &crtc_state->dp_m_n); 2254 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 2255 &crtc_state->dp_m2_n2); 2256 } 2257 2258 intel_set_transcoder_timings(crtc_state); 2259 2260 i9xx_set_pipeconf(crtc_state); 2261 } 2262 2263 static void valleyview_crtc_enable(struct intel_atomic_state *state, 2264 struct intel_crtc *crtc) 2265 { 2266 const struct intel_crtc_state *new_crtc_state = 2267 intel_atomic_get_new_crtc_state(state, crtc); 2268 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2269 enum pipe pipe = crtc->pipe; 2270 2271 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 2272 return; 2273 2274 i9xx_configure_cpu_transcoder(new_crtc_state); 2275 2276 intel_set_pipe_src_size(new_crtc_state); 2277 2278 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 2279 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY); 2280 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0); 2281 } 2282 2283 crtc->active = true; 2284 2285 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2286 2287 intel_encoders_pre_pll_enable(state, crtc); 2288 2289 if (IS_CHERRYVIEW(dev_priv)) 2290 chv_enable_pll(new_crtc_state); 2291 else 2292 vlv_enable_pll(new_crtc_state); 2293 2294 intel_encoders_pre_enable(state, crtc); 2295 2296 i9xx_pfit_enable(new_crtc_state); 2297 2298 intel_color_load_luts(new_crtc_state); 2299 intel_color_commit_noarm(new_crtc_state); 2300 intel_color_commit_arm(new_crtc_state); 2301 /* update DSPCNTR to configure gamma for pipe bottom color */ 2302 intel_disable_primary_plane(new_crtc_state); 2303 2304 intel_initial_watermarks(state, crtc); 2305 intel_enable_transcoder(new_crtc_state); 2306 2307 intel_crtc_vblank_on(new_crtc_state); 2308 2309 intel_encoders_enable(state, crtc); 2310 } 2311 2312 static void i9xx_crtc_enable(struct intel_atomic_state *state, 2313 struct intel_crtc *crtc) 2314 { 2315 const struct intel_crtc_state *new_crtc_state = 2316 intel_atomic_get_new_crtc_state(state, crtc); 2317 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2318 enum pipe pipe = crtc->pipe; 2319 2320 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 2321 return; 2322 2323 i9xx_configure_cpu_transcoder(new_crtc_state); 2324 2325 intel_set_pipe_src_size(new_crtc_state); 2326 2327 crtc->active = true; 2328 2329 if (DISPLAY_VER(dev_priv) != 2) 2330 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2331 2332 intel_encoders_pre_enable(state, crtc); 2333 2334 i9xx_enable_pll(new_crtc_state); 2335 2336 i9xx_pfit_enable(new_crtc_state); 2337 2338 intel_color_load_luts(new_crtc_state); 2339 intel_color_commit_noarm(new_crtc_state); 2340 intel_color_commit_arm(new_crtc_state); 2341 /* update DSPCNTR to configure gamma for pipe bottom color */ 2342 intel_disable_primary_plane(new_crtc_state); 2343 2344 if (!intel_initial_watermarks(state, crtc)) 2345 intel_update_watermarks(dev_priv); 2346 intel_enable_transcoder(new_crtc_state); 2347 2348 intel_crtc_vblank_on(new_crtc_state); 2349 2350 intel_encoders_enable(state, crtc); 2351 2352 /* prevents spurious underruns */ 2353 if (DISPLAY_VER(dev_priv) == 2) 2354 intel_crtc_wait_for_next_vblank(crtc); 2355 } 2356 2357 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) 2358 { 2359 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 2360 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2361 2362 if (!old_crtc_state->gmch_pfit.control) 2363 return; 2364 2365 assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder); 2366 2367 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n", 2368 intel_de_read(dev_priv, PFIT_CONTROL)); 2369 intel_de_write(dev_priv, PFIT_CONTROL, 0); 2370 } 2371 2372 static void i9xx_crtc_disable(struct intel_atomic_state *state, 2373 struct intel_crtc *crtc) 2374 { 2375 struct intel_crtc_state *old_crtc_state = 2376 intel_atomic_get_old_crtc_state(state, crtc); 2377 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2378 enum pipe pipe = crtc->pipe; 2379 2380 /* 2381 * On gen2 planes are double buffered but the pipe isn't, so we must 2382 * wait for planes to fully turn off before disabling the pipe. 2383 */ 2384 if (DISPLAY_VER(dev_priv) == 2) 2385 intel_crtc_wait_for_next_vblank(crtc); 2386 2387 intel_encoders_disable(state, crtc); 2388 2389 intel_crtc_vblank_off(old_crtc_state); 2390 2391 intel_disable_transcoder(old_crtc_state); 2392 2393 i9xx_pfit_disable(old_crtc_state); 2394 2395 intel_encoders_post_disable(state, crtc); 2396 2397 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) { 2398 if (IS_CHERRYVIEW(dev_priv)) 2399 chv_disable_pll(dev_priv, pipe); 2400 else if (IS_VALLEYVIEW(dev_priv)) 2401 vlv_disable_pll(dev_priv, pipe); 2402 else 2403 i9xx_disable_pll(old_crtc_state); 2404 } 2405 2406 intel_encoders_post_pll_disable(state, crtc); 2407 2408 if (DISPLAY_VER(dev_priv) != 2) 2409 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 2410 2411 if (!dev_priv->wm_disp->initial_watermarks) 2412 intel_update_watermarks(dev_priv); 2413 2414 /* clock the pipe down to 640x480@60 to potentially save power */ 2415 if (IS_I830(dev_priv)) 2416 i830_enable_pipe(dev_priv, pipe); 2417 } 2418 2419 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, 2420 struct drm_modeset_acquire_ctx *ctx) 2421 { 2422 struct intel_encoder *encoder; 2423 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2424 struct intel_bw_state *bw_state = 2425 to_intel_bw_state(dev_priv->bw_obj.state); 2426 struct intel_cdclk_state *cdclk_state = 2427 to_intel_cdclk_state(dev_priv->cdclk.obj.state); 2428 struct intel_dbuf_state *dbuf_state = 2429 to_intel_dbuf_state(dev_priv->dbuf.obj.state); 2430 struct intel_crtc_state *crtc_state = 2431 to_intel_crtc_state(crtc->base.state); 2432 struct intel_plane *plane; 2433 struct drm_atomic_state *state; 2434 struct intel_crtc_state *temp_crtc_state; 2435 enum pipe pipe = crtc->pipe; 2436 int ret; 2437 2438 if (!crtc_state->hw.active) 2439 return; 2440 2441 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 2442 const struct intel_plane_state *plane_state = 2443 to_intel_plane_state(plane->base.state); 2444 2445 if (plane_state->uapi.visible) 2446 intel_plane_disable_noatomic(crtc, plane); 2447 } 2448 2449 state = drm_atomic_state_alloc(&dev_priv->drm); 2450 if (!state) { 2451 drm_dbg_kms(&dev_priv->drm, 2452 "failed to disable [CRTC:%d:%s], out of memory", 2453 crtc->base.base.id, crtc->base.name); 2454 return; 2455 } 2456 2457 state->acquire_ctx = ctx; 2458 2459 /* Everything's already locked, -EDEADLK can't happen. */ 2460 temp_crtc_state = intel_atomic_get_crtc_state(state, crtc); 2461 ret = drm_atomic_add_affected_connectors(state, &crtc->base); 2462 2463 drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret); 2464 2465 dev_priv->display->crtc_disable(to_intel_atomic_state(state), crtc); 2466 2467 drm_atomic_state_put(state); 2468 2469 drm_dbg_kms(&dev_priv->drm, 2470 "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", 2471 crtc->base.base.id, crtc->base.name); 2472 2473 crtc->active = false; 2474 crtc->base.enabled = false; 2475 2476 drm_WARN_ON(&dev_priv->drm, 2477 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0); 2478 crtc_state->uapi.active = false; 2479 crtc_state->uapi.connector_mask = 0; 2480 crtc_state->uapi.encoder_mask = 0; 2481 intel_crtc_free_hw_state(crtc_state); 2482 memset(&crtc_state->hw, 0, sizeof(crtc_state->hw)); 2483 2484 for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder) 2485 encoder->base.crtc = NULL; 2486 2487 intel_fbc_disable(crtc); 2488 intel_update_watermarks(dev_priv); 2489 intel_disable_shared_dpll(crtc_state); 2490 2491 intel_display_power_put_all_in_set(dev_priv, &crtc->enabled_power_domains); 2492 2493 cdclk_state->min_cdclk[pipe] = 0; 2494 cdclk_state->min_voltage_level[pipe] = 0; 2495 cdclk_state->active_pipes &= ~BIT(pipe); 2496 2497 dbuf_state->active_pipes &= ~BIT(pipe); 2498 2499 bw_state->data_rate[pipe] = 0; 2500 bw_state->num_active_planes[pipe] = 0; 2501 } 2502 2503 /* 2504 * turn all crtc's off, but do not adjust state 2505 * This has to be paired with a call to intel_modeset_setup_hw_state. 2506 */ 2507 int intel_display_suspend(struct drm_device *dev) 2508 { 2509 struct drm_i915_private *dev_priv = to_i915(dev); 2510 struct drm_atomic_state *state; 2511 int ret; 2512 2513 if (!HAS_DISPLAY(dev_priv)) 2514 return 0; 2515 2516 state = drm_atomic_helper_suspend(dev); 2517 ret = PTR_ERR_OR_ZERO(state); 2518 if (ret) 2519 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", 2520 ret); 2521 else 2522 dev_priv->modeset_restore_state = state; 2523 return ret; 2524 } 2525 2526 void intel_encoder_destroy(struct drm_encoder *encoder) 2527 { 2528 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2529 2530 drm_encoder_cleanup(encoder); 2531 kfree(intel_encoder); 2532 } 2533 2534 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) 2535 { 2536 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2537 2538 /* GDG double wide on either pipe, otherwise pipe A only */ 2539 return DISPLAY_VER(dev_priv) < 4 && 2540 (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); 2541 } 2542 2543 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) 2544 { 2545 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock; 2546 struct drm_rect src; 2547 2548 /* 2549 * We only use IF-ID interlacing. If we ever use 2550 * PF-ID we'll need to adjust the pixel_rate here. 2551 */ 2552 2553 if (!crtc_state->pch_pfit.enabled) 2554 return pixel_rate; 2555 2556 drm_rect_init(&src, 0, 0, 2557 drm_rect_width(&crtc_state->pipe_src) << 16, 2558 drm_rect_height(&crtc_state->pipe_src) << 16); 2559 2560 return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst, 2561 pixel_rate); 2562 } 2563 2564 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode, 2565 const struct drm_display_mode *timings) 2566 { 2567 mode->hdisplay = timings->crtc_hdisplay; 2568 mode->htotal = timings->crtc_htotal; 2569 mode->hsync_start = timings->crtc_hsync_start; 2570 mode->hsync_end = timings->crtc_hsync_end; 2571 2572 mode->vdisplay = timings->crtc_vdisplay; 2573 mode->vtotal = timings->crtc_vtotal; 2574 mode->vsync_start = timings->crtc_vsync_start; 2575 mode->vsync_end = timings->crtc_vsync_end; 2576 2577 mode->flags = timings->flags; 2578 mode->type = DRM_MODE_TYPE_DRIVER; 2579 2580 mode->clock = timings->crtc_clock; 2581 2582 drm_mode_set_name(mode); 2583 } 2584 2585 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) 2586 { 2587 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2588 2589 if (HAS_GMCH(dev_priv)) 2590 /* FIXME calculate proper pipe pixel rate for GMCH pfit */ 2591 crtc_state->pixel_rate = 2592 crtc_state->hw.pipe_mode.crtc_clock; 2593 else 2594 crtc_state->pixel_rate = 2595 ilk_pipe_pixel_rate(crtc_state); 2596 } 2597 2598 static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state *crtc_state, 2599 struct drm_display_mode *mode) 2600 { 2601 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2602 2603 if (num_pipes < 2) 2604 return; 2605 2606 mode->crtc_clock /= num_pipes; 2607 mode->crtc_hdisplay /= num_pipes; 2608 mode->crtc_hblank_start /= num_pipes; 2609 mode->crtc_hblank_end /= num_pipes; 2610 mode->crtc_hsync_start /= num_pipes; 2611 mode->crtc_hsync_end /= num_pipes; 2612 mode->crtc_htotal /= num_pipes; 2613 } 2614 2615 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state, 2616 struct drm_display_mode *mode) 2617 { 2618 int overlap = crtc_state->splitter.pixel_overlap; 2619 int n = crtc_state->splitter.link_count; 2620 2621 if (!crtc_state->splitter.enable) 2622 return; 2623 2624 /* 2625 * eDP MSO uses segment timings from EDID for transcoder 2626 * timings, but full mode for everything else. 2627 * 2628 * h_full = (h_segment - pixel_overlap) * link_count 2629 */ 2630 mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n; 2631 mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n; 2632 mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n; 2633 mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n; 2634 mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n; 2635 mode->crtc_htotal = (mode->crtc_htotal - overlap) * n; 2636 mode->crtc_clock *= n; 2637 } 2638 2639 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state) 2640 { 2641 struct drm_display_mode *mode = &crtc_state->hw.mode; 2642 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2643 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2644 2645 /* 2646 * Start with the adjusted_mode crtc timings, which 2647 * have been filled with the transcoder timings. 2648 */ 2649 drm_mode_copy(pipe_mode, adjusted_mode); 2650 2651 /* Expand MSO per-segment transcoder timings to full */ 2652 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2653 2654 /* 2655 * We want the full numbers in adjusted_mode normal timings, 2656 * adjusted_mode crtc timings are left with the raw transcoder 2657 * timings. 2658 */ 2659 intel_mode_from_crtc_timings(adjusted_mode, pipe_mode); 2660 2661 /* Populate the "user" mode with full numbers */ 2662 drm_mode_copy(mode, pipe_mode); 2663 intel_mode_from_crtc_timings(mode, mode); 2664 mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) * 2665 (intel_bigjoiner_num_pipes(crtc_state) ?: 1); 2666 mode->vdisplay = drm_rect_height(&crtc_state->pipe_src); 2667 2668 /* Derive per-pipe timings in case bigjoiner is used */ 2669 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2670 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2671 2672 intel_crtc_compute_pixel_rate(crtc_state); 2673 } 2674 2675 void intel_encoder_get_config(struct intel_encoder *encoder, 2676 struct intel_crtc_state *crtc_state) 2677 { 2678 encoder->get_config(encoder, crtc_state); 2679 2680 intel_crtc_readout_derived_state(crtc_state); 2681 } 2682 2683 static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state *crtc_state) 2684 { 2685 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2686 int width, height; 2687 2688 if (num_pipes < 2) 2689 return; 2690 2691 width = drm_rect_width(&crtc_state->pipe_src); 2692 height = drm_rect_height(&crtc_state->pipe_src); 2693 2694 drm_rect_init(&crtc_state->pipe_src, 0, 0, 2695 width / num_pipes, height); 2696 } 2697 2698 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state) 2699 { 2700 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2701 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2702 2703 intel_bigjoiner_compute_pipe_src(crtc_state); 2704 2705 /* 2706 * Pipe horizontal size must be even in: 2707 * - DVO ganged mode 2708 * - LVDS dual channel mode 2709 * - Double wide pipe 2710 */ 2711 if (drm_rect_width(&crtc_state->pipe_src) & 1) { 2712 if (crtc_state->double_wide) { 2713 drm_dbg_kms(&i915->drm, 2714 "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n", 2715 crtc->base.base.id, crtc->base.name); 2716 return -EINVAL; 2717 } 2718 2719 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 2720 intel_is_dual_link_lvds(i915)) { 2721 drm_dbg_kms(&i915->drm, 2722 "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n", 2723 crtc->base.base.id, crtc->base.name); 2724 return -EINVAL; 2725 } 2726 } 2727 2728 return 0; 2729 } 2730 2731 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state) 2732 { 2733 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2734 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2735 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2736 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2737 int clock_limit = i915->max_dotclk_freq; 2738 2739 /* 2740 * Start with the adjusted_mode crtc timings, which 2741 * have been filled with the transcoder timings. 2742 */ 2743 drm_mode_copy(pipe_mode, adjusted_mode); 2744 2745 /* Expand MSO per-segment transcoder timings to full */ 2746 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2747 2748 /* Derive per-pipe timings in case bigjoiner is used */ 2749 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2750 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2751 2752 if (DISPLAY_VER(i915) < 4) { 2753 clock_limit = i915->max_cdclk_freq * 9 / 10; 2754 2755 /* 2756 * Enable double wide mode when the dot clock 2757 * is > 90% of the (display) core speed. 2758 */ 2759 if (intel_crtc_supports_double_wide(crtc) && 2760 pipe_mode->crtc_clock > clock_limit) { 2761 clock_limit = i915->max_dotclk_freq; 2762 crtc_state->double_wide = true; 2763 } 2764 } 2765 2766 if (pipe_mode->crtc_clock > clock_limit) { 2767 drm_dbg_kms(&i915->drm, 2768 "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", 2769 crtc->base.base.id, crtc->base.name, 2770 pipe_mode->crtc_clock, clock_limit, 2771 str_yes_no(crtc_state->double_wide)); 2772 return -EINVAL; 2773 } 2774 2775 return 0; 2776 } 2777 2778 static int intel_crtc_compute_config(struct intel_atomic_state *state, 2779 struct intel_crtc *crtc) 2780 { 2781 struct intel_crtc_state *crtc_state = 2782 intel_atomic_get_new_crtc_state(state, crtc); 2783 int ret; 2784 2785 ret = intel_crtc_compute_pipe_src(crtc_state); 2786 if (ret) 2787 return ret; 2788 2789 ret = intel_crtc_compute_pipe_mode(crtc_state); 2790 if (ret) 2791 return ret; 2792 2793 intel_crtc_compute_pixel_rate(crtc_state); 2794 2795 if (crtc_state->has_pch_encoder) 2796 return ilk_fdi_compute_config(crtc, crtc_state); 2797 2798 return 0; 2799 } 2800 2801 static void 2802 intel_reduce_m_n_ratio(u32 *num, u32 *den) 2803 { 2804 while (*num > DATA_LINK_M_N_MASK || 2805 *den > DATA_LINK_M_N_MASK) { 2806 *num >>= 1; 2807 *den >>= 1; 2808 } 2809 } 2810 2811 static void compute_m_n(unsigned int m, unsigned int n, 2812 u32 *ret_m, u32 *ret_n, 2813 bool constant_n) 2814 { 2815 /* 2816 * Several DP dongles in particular seem to be fussy about 2817 * too large link M/N values. Give N value as 0x8000 that 2818 * should be acceptable by specific devices. 0x8000 is the 2819 * specified fixed N value for asynchronous clock mode, 2820 * which the devices expect also in synchronous clock mode. 2821 */ 2822 if (constant_n) 2823 *ret_n = DP_LINK_CONSTANT_N_VALUE; 2824 else 2825 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); 2826 2827 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n); 2828 intel_reduce_m_n_ratio(ret_m, ret_n); 2829 } 2830 2831 void 2832 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes, 2833 int pixel_clock, int link_clock, 2834 struct intel_link_m_n *m_n, 2835 bool constant_n, bool fec_enable) 2836 { 2837 u32 data_clock = bits_per_pixel * pixel_clock; 2838 2839 if (fec_enable) 2840 data_clock = intel_dp_mode_to_fec_clock(data_clock); 2841 2842 m_n->tu = 64; 2843 compute_m_n(data_clock, 2844 link_clock * nlanes * 8, 2845 &m_n->data_m, &m_n->data_n, 2846 constant_n); 2847 2848 compute_m_n(pixel_clock, link_clock, 2849 &m_n->link_m, &m_n->link_n, 2850 constant_n); 2851 } 2852 2853 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv) 2854 { 2855 /* 2856 * There may be no VBT; and if the BIOS enabled SSC we can 2857 * just keep using it to avoid unnecessary flicker. Whereas if the 2858 * BIOS isn't using it, don't assume it will work even if the VBT 2859 * indicates as much. 2860 */ 2861 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { 2862 bool bios_lvds_use_ssc = intel_de_read(dev_priv, 2863 PCH_DREF_CONTROL) & 2864 DREF_SSC1_ENABLE; 2865 2866 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { 2867 drm_dbg_kms(&dev_priv->drm, 2868 "SSC %s by BIOS, overriding VBT which says %s\n", 2869 str_enabled_disabled(bios_lvds_use_ssc), 2870 str_enabled_disabled(dev_priv->vbt.lvds_use_ssc)); 2871 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; 2872 } 2873 } 2874 } 2875 2876 void intel_zero_m_n(struct intel_link_m_n *m_n) 2877 { 2878 /* corresponds to 0 register value */ 2879 memset(m_n, 0, sizeof(*m_n)); 2880 m_n->tu = 1; 2881 } 2882 2883 void intel_set_m_n(struct drm_i915_private *i915, 2884 const struct intel_link_m_n *m_n, 2885 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 2886 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 2887 { 2888 intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); 2889 intel_de_write(i915, data_n_reg, m_n->data_n); 2890 intel_de_write(i915, link_m_reg, m_n->link_m); 2891 /* 2892 * On BDW+ writing LINK_N arms the double buffered update 2893 * of all the M/N registers, so it must be written last. 2894 */ 2895 intel_de_write(i915, link_n_reg, m_n->link_n); 2896 } 2897 2898 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, 2899 enum transcoder transcoder) 2900 { 2901 if (IS_HASWELL(dev_priv)) 2902 return transcoder == TRANSCODER_EDP; 2903 2904 return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv); 2905 } 2906 2907 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, 2908 enum transcoder transcoder, 2909 const struct intel_link_m_n *m_n) 2910 { 2911 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2912 enum pipe pipe = crtc->pipe; 2913 2914 if (DISPLAY_VER(dev_priv) >= 5) 2915 intel_set_m_n(dev_priv, m_n, 2916 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 2917 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 2918 else 2919 intel_set_m_n(dev_priv, m_n, 2920 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 2921 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 2922 } 2923 2924 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, 2925 enum transcoder transcoder, 2926 const struct intel_link_m_n *m_n) 2927 { 2928 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2929 2930 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 2931 return; 2932 2933 intel_set_m_n(dev_priv, m_n, 2934 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 2935 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 2936 } 2937 2938 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) 2939 { 2940 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2941 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2942 enum pipe pipe = crtc->pipe; 2943 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2944 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2945 u32 crtc_vtotal, crtc_vblank_end; 2946 int vsyncshift = 0; 2947 2948 /* We need to be careful not to changed the adjusted mode, for otherwise 2949 * the hw state checker will get angry at the mismatch. */ 2950 crtc_vtotal = adjusted_mode->crtc_vtotal; 2951 crtc_vblank_end = adjusted_mode->crtc_vblank_end; 2952 2953 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 2954 /* the chip adds 2 halflines automatically */ 2955 crtc_vtotal -= 1; 2956 crtc_vblank_end -= 1; 2957 2958 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 2959 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; 2960 else 2961 vsyncshift = adjusted_mode->crtc_hsync_start - 2962 adjusted_mode->crtc_htotal / 2; 2963 if (vsyncshift < 0) 2964 vsyncshift += adjusted_mode->crtc_htotal; 2965 } 2966 2967 if (DISPLAY_VER(dev_priv) > 3) 2968 intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder), 2969 vsyncshift); 2970 2971 intel_de_write(dev_priv, HTOTAL(cpu_transcoder), 2972 (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16)); 2973 intel_de_write(dev_priv, HBLANK(cpu_transcoder), 2974 (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16)); 2975 intel_de_write(dev_priv, HSYNC(cpu_transcoder), 2976 (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16)); 2977 2978 intel_de_write(dev_priv, VTOTAL(cpu_transcoder), 2979 (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16)); 2980 intel_de_write(dev_priv, VBLANK(cpu_transcoder), 2981 (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16)); 2982 intel_de_write(dev_priv, VSYNC(cpu_transcoder), 2983 (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16)); 2984 2985 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be 2986 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is 2987 * documented on the DDI_FUNC_CTL register description, EDP Input Select 2988 * bits. */ 2989 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && 2990 (pipe == PIPE_B || pipe == PIPE_C)) 2991 intel_de_write(dev_priv, VTOTAL(pipe), 2992 intel_de_read(dev_priv, VTOTAL(cpu_transcoder))); 2993 2994 } 2995 2996 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) 2997 { 2998 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2999 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3000 int width = drm_rect_width(&crtc_state->pipe_src); 3001 int height = drm_rect_height(&crtc_state->pipe_src); 3002 enum pipe pipe = crtc->pipe; 3003 3004 /* pipesrc controls the size that is scaled from, which should 3005 * always be the user's requested size. 3006 */ 3007 intel_de_write(dev_priv, PIPESRC(pipe), 3008 PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1)); 3009 } 3010 3011 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) 3012 { 3013 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3014 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3015 3016 if (DISPLAY_VER(dev_priv) == 2) 3017 return false; 3018 3019 if (DISPLAY_VER(dev_priv) >= 9 || 3020 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 3021 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW; 3022 else 3023 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK; 3024 } 3025 3026 static void intel_get_transcoder_timings(struct intel_crtc *crtc, 3027 struct intel_crtc_state *pipe_config) 3028 { 3029 struct drm_device *dev = crtc->base.dev; 3030 struct drm_i915_private *dev_priv = to_i915(dev); 3031 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3032 u32 tmp; 3033 3034 tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder)); 3035 pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; 3036 pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; 3037 3038 if (!transcoder_is_dsi(cpu_transcoder)) { 3039 tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder)); 3040 pipe_config->hw.adjusted_mode.crtc_hblank_start = 3041 (tmp & 0xffff) + 1; 3042 pipe_config->hw.adjusted_mode.crtc_hblank_end = 3043 ((tmp >> 16) & 0xffff) + 1; 3044 } 3045 tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder)); 3046 pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; 3047 pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; 3048 3049 tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder)); 3050 pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; 3051 pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; 3052 3053 if (!transcoder_is_dsi(cpu_transcoder)) { 3054 tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder)); 3055 pipe_config->hw.adjusted_mode.crtc_vblank_start = 3056 (tmp & 0xffff) + 1; 3057 pipe_config->hw.adjusted_mode.crtc_vblank_end = 3058 ((tmp >> 16) & 0xffff) + 1; 3059 } 3060 tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder)); 3061 pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; 3062 pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; 3063 3064 if (intel_pipe_is_interlaced(pipe_config)) { 3065 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; 3066 pipe_config->hw.adjusted_mode.crtc_vtotal += 1; 3067 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1; 3068 } 3069 } 3070 3071 static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state) 3072 { 3073 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3074 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 3075 enum pipe master_pipe, pipe = crtc->pipe; 3076 int width; 3077 3078 if (num_pipes < 2) 3079 return; 3080 3081 master_pipe = bigjoiner_master_pipe(crtc_state); 3082 width = drm_rect_width(&crtc_state->pipe_src); 3083 3084 drm_rect_translate_to(&crtc_state->pipe_src, 3085 (pipe - master_pipe) * width, 0); 3086 } 3087 3088 static void intel_get_pipe_src_size(struct intel_crtc *crtc, 3089 struct intel_crtc_state *pipe_config) 3090 { 3091 struct drm_device *dev = crtc->base.dev; 3092 struct drm_i915_private *dev_priv = to_i915(dev); 3093 u32 tmp; 3094 3095 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe)); 3096 3097 drm_rect_init(&pipe_config->pipe_src, 0, 0, 3098 REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1, 3099 REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1); 3100 3101 intel_bigjoiner_adjust_pipe_src(pipe_config); 3102 } 3103 3104 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) 3105 { 3106 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3107 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3108 u32 pipeconf = 0; 3109 3110 /* we keep both pipes enabled on 830 */ 3111 if (IS_I830(dev_priv)) 3112 pipeconf |= PIPECONF_ENABLE; 3113 3114 if (crtc_state->double_wide) 3115 pipeconf |= PIPECONF_DOUBLE_WIDE; 3116 3117 /* only g4x and later have fancy bpc/dither controls */ 3118 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 3119 IS_CHERRYVIEW(dev_priv)) { 3120 /* Bspec claims that we can't use dithering for 30bpp pipes. */ 3121 if (crtc_state->dither && crtc_state->pipe_bpp != 30) 3122 pipeconf |= PIPECONF_DITHER_EN | 3123 PIPECONF_DITHER_TYPE_SP; 3124 3125 switch (crtc_state->pipe_bpp) { 3126 default: 3127 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3128 MISSING_CASE(crtc_state->pipe_bpp); 3129 fallthrough; 3130 case 18: 3131 pipeconf |= PIPECONF_BPC_6; 3132 break; 3133 case 24: 3134 pipeconf |= PIPECONF_BPC_8; 3135 break; 3136 case 30: 3137 pipeconf |= PIPECONF_BPC_10; 3138 break; 3139 } 3140 } 3141 3142 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 3143 if (DISPLAY_VER(dev_priv) < 4 || 3144 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3145 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; 3146 else 3147 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; 3148 } else { 3149 pipeconf |= PIPECONF_INTERLACE_PROGRESSIVE; 3150 } 3151 3152 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 3153 crtc_state->limited_color_range) 3154 pipeconf |= PIPECONF_COLOR_RANGE_SELECT; 3155 3156 pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); 3157 3158 pipeconf |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3159 3160 intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf); 3161 intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe)); 3162 } 3163 3164 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv) 3165 { 3166 if (IS_I830(dev_priv)) 3167 return false; 3168 3169 return DISPLAY_VER(dev_priv) >= 4 || 3170 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); 3171 } 3172 3173 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state) 3174 { 3175 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3176 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3177 u32 tmp; 3178 3179 if (!i9xx_has_pfit(dev_priv)) 3180 return; 3181 3182 tmp = intel_de_read(dev_priv, PFIT_CONTROL); 3183 if (!(tmp & PFIT_ENABLE)) 3184 return; 3185 3186 /* Check whether the pfit is attached to our pipe. */ 3187 if (DISPLAY_VER(dev_priv) < 4) { 3188 if (crtc->pipe != PIPE_B) 3189 return; 3190 } else { 3191 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) 3192 return; 3193 } 3194 3195 crtc_state->gmch_pfit.control = tmp; 3196 crtc_state->gmch_pfit.pgm_ratios = 3197 intel_de_read(dev_priv, PFIT_PGM_RATIOS); 3198 } 3199 3200 static void vlv_crtc_clock_get(struct intel_crtc *crtc, 3201 struct intel_crtc_state *pipe_config) 3202 { 3203 struct drm_device *dev = crtc->base.dev; 3204 struct drm_i915_private *dev_priv = to_i915(dev); 3205 enum pipe pipe = crtc->pipe; 3206 struct dpll clock; 3207 u32 mdiv; 3208 int refclk = 100000; 3209 3210 /* In case of DSI, DPLL will not be used */ 3211 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 3212 return; 3213 3214 vlv_dpio_get(dev_priv); 3215 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); 3216 vlv_dpio_put(dev_priv); 3217 3218 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; 3219 clock.m2 = mdiv & DPIO_M2DIV_MASK; 3220 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; 3221 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; 3222 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; 3223 3224 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); 3225 } 3226 3227 static void chv_crtc_clock_get(struct intel_crtc *crtc, 3228 struct intel_crtc_state *pipe_config) 3229 { 3230 struct drm_device *dev = crtc->base.dev; 3231 struct drm_i915_private *dev_priv = to_i915(dev); 3232 enum pipe pipe = crtc->pipe; 3233 enum dpio_channel port = vlv_pipe_to_channel(pipe); 3234 struct dpll clock; 3235 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; 3236 int refclk = 100000; 3237 3238 /* In case of DSI, DPLL will not be used */ 3239 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 3240 return; 3241 3242 vlv_dpio_get(dev_priv); 3243 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); 3244 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); 3245 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); 3246 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); 3247 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); 3248 vlv_dpio_put(dev_priv); 3249 3250 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; 3251 clock.m2 = (pll_dw0 & 0xff) << 22; 3252 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) 3253 clock.m2 |= pll_dw2 & 0x3fffff; 3254 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; 3255 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; 3256 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; 3257 3258 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); 3259 } 3260 3261 static enum intel_output_format 3262 bdw_get_pipemisc_output_format(struct intel_crtc *crtc) 3263 { 3264 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3265 u32 tmp; 3266 3267 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); 3268 3269 if (tmp & PIPEMISC_YUV420_ENABLE) { 3270 /* We support 4:2:0 in full blend mode only */ 3271 drm_WARN_ON(&dev_priv->drm, 3272 (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0); 3273 3274 return INTEL_OUTPUT_FORMAT_YCBCR420; 3275 } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) { 3276 return INTEL_OUTPUT_FORMAT_YCBCR444; 3277 } else { 3278 return INTEL_OUTPUT_FORMAT_RGB; 3279 } 3280 } 3281 3282 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state) 3283 { 3284 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3285 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 3286 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3287 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 3288 u32 tmp; 3289 3290 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); 3291 3292 if (tmp & DISP_PIPE_GAMMA_ENABLE) 3293 crtc_state->gamma_enable = true; 3294 3295 if (!HAS_GMCH(dev_priv) && 3296 tmp & DISP_PIPE_CSC_ENABLE) 3297 crtc_state->csc_enable = true; 3298 } 3299 3300 static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 3301 struct intel_crtc_state *pipe_config) 3302 { 3303 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3304 enum intel_display_power_domain power_domain; 3305 intel_wakeref_t wakeref; 3306 u32 tmp; 3307 bool ret; 3308 3309 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3310 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3311 if (!wakeref) 3312 return false; 3313 3314 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3315 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3316 pipe_config->shared_dpll = NULL; 3317 3318 ret = false; 3319 3320 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); 3321 if (!(tmp & PIPECONF_ENABLE)) 3322 goto out; 3323 3324 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 3325 IS_CHERRYVIEW(dev_priv)) { 3326 switch (tmp & PIPECONF_BPC_MASK) { 3327 case PIPECONF_BPC_6: 3328 pipe_config->pipe_bpp = 18; 3329 break; 3330 case PIPECONF_BPC_8: 3331 pipe_config->pipe_bpp = 24; 3332 break; 3333 case PIPECONF_BPC_10: 3334 pipe_config->pipe_bpp = 30; 3335 break; 3336 default: 3337 MISSING_CASE(tmp); 3338 break; 3339 } 3340 } 3341 3342 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 3343 (tmp & PIPECONF_COLOR_RANGE_SELECT)) 3344 pipe_config->limited_color_range = true; 3345 3346 pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_I9XX, tmp); 3347 3348 pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1; 3349 3350 if (IS_CHERRYVIEW(dev_priv)) 3351 pipe_config->cgm_mode = intel_de_read(dev_priv, 3352 CGM_PIPE_MODE(crtc->pipe)); 3353 3354 i9xx_get_pipe_color_config(pipe_config); 3355 intel_color_get_config(pipe_config); 3356 3357 if (DISPLAY_VER(dev_priv) < 4) 3358 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; 3359 3360 intel_get_transcoder_timings(crtc, pipe_config); 3361 intel_get_pipe_src_size(crtc, pipe_config); 3362 3363 i9xx_get_pfit_config(pipe_config); 3364 3365 if (DISPLAY_VER(dev_priv) >= 4) { 3366 /* No way to read it out on pipes B and C */ 3367 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) 3368 tmp = dev_priv->chv_dpll_md[crtc->pipe]; 3369 else 3370 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe)); 3371 pipe_config->pixel_multiplier = 3372 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) 3373 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; 3374 pipe_config->dpll_hw_state.dpll_md = tmp; 3375 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 3376 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 3377 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe)); 3378 pipe_config->pixel_multiplier = 3379 ((tmp & SDVO_MULTIPLIER_MASK) 3380 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; 3381 } else { 3382 /* Note that on i915G/GM the pixel multiplier is in the sdvo 3383 * port and will be fixed up in the encoder->get_config 3384 * function. */ 3385 pipe_config->pixel_multiplier = 1; 3386 } 3387 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv, 3388 DPLL(crtc->pipe)); 3389 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 3390 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv, 3391 FP0(crtc->pipe)); 3392 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv, 3393 FP1(crtc->pipe)); 3394 } else { 3395 /* Mask out read-only status bits. */ 3396 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | 3397 DPLL_PORTC_READY_MASK | 3398 DPLL_PORTB_READY_MASK); 3399 } 3400 3401 if (IS_CHERRYVIEW(dev_priv)) 3402 chv_crtc_clock_get(crtc, pipe_config); 3403 else if (IS_VALLEYVIEW(dev_priv)) 3404 vlv_crtc_clock_get(crtc, pipe_config); 3405 else 3406 i9xx_crtc_clock_get(crtc, pipe_config); 3407 3408 /* 3409 * Normally the dotclock is filled in by the encoder .get_config() 3410 * but in case the pipe is enabled w/o any ports we need a sane 3411 * default. 3412 */ 3413 pipe_config->hw.adjusted_mode.crtc_clock = 3414 pipe_config->port_clock / pipe_config->pixel_multiplier; 3415 3416 ret = true; 3417 3418 out: 3419 intel_display_power_put(dev_priv, power_domain, wakeref); 3420 3421 return ret; 3422 } 3423 3424 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) 3425 { 3426 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3427 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3428 enum pipe pipe = crtc->pipe; 3429 u32 val; 3430 3431 val = 0; 3432 3433 switch (crtc_state->pipe_bpp) { 3434 default: 3435 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3436 MISSING_CASE(crtc_state->pipe_bpp); 3437 fallthrough; 3438 case 18: 3439 val |= PIPECONF_BPC_6; 3440 break; 3441 case 24: 3442 val |= PIPECONF_BPC_8; 3443 break; 3444 case 30: 3445 val |= PIPECONF_BPC_10; 3446 break; 3447 case 36: 3448 val |= PIPECONF_BPC_12; 3449 break; 3450 } 3451 3452 if (crtc_state->dither) 3453 val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP; 3454 3455 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3456 val |= PIPECONF_INTERLACE_IF_ID_ILK; 3457 else 3458 val |= PIPECONF_INTERLACE_PF_PD_ILK; 3459 3460 /* 3461 * This would end up with an odd purple hue over 3462 * the entire display. Make sure we don't do it. 3463 */ 3464 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 3465 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 3466 3467 if (crtc_state->limited_color_range && 3468 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3469 val |= PIPECONF_COLOR_RANGE_SELECT; 3470 3471 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3472 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709; 3473 3474 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); 3475 3476 val |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3477 val |= PIPECONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay); 3478 3479 intel_de_write(dev_priv, PIPECONF(pipe), val); 3480 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 3481 } 3482 3483 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) 3484 { 3485 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3486 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3487 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3488 u32 val = 0; 3489 3490 if (IS_HASWELL(dev_priv) && crtc_state->dither) 3491 val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP; 3492 3493 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3494 val |= PIPECONF_INTERLACE_IF_ID_ILK; 3495 else 3496 val |= PIPECONF_INTERLACE_PF_PD_ILK; 3497 3498 if (IS_HASWELL(dev_priv) && 3499 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3500 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW; 3501 3502 intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val); 3503 intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder)); 3504 } 3505 3506 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) 3507 { 3508 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3509 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3510 u32 val = 0; 3511 3512 switch (crtc_state->pipe_bpp) { 3513 case 18: 3514 val |= PIPEMISC_BPC_6; 3515 break; 3516 case 24: 3517 val |= PIPEMISC_BPC_8; 3518 break; 3519 case 30: 3520 val |= PIPEMISC_BPC_10; 3521 break; 3522 case 36: 3523 /* Port output 12BPC defined for ADLP+ */ 3524 if (DISPLAY_VER(dev_priv) > 12) 3525 val |= PIPEMISC_BPC_12_ADLP; 3526 break; 3527 default: 3528 MISSING_CASE(crtc_state->pipe_bpp); 3529 break; 3530 } 3531 3532 if (crtc_state->dither) 3533 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; 3534 3535 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 3536 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 3537 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV; 3538 3539 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 3540 val |= PIPEMISC_YUV420_ENABLE | 3541 PIPEMISC_YUV420_MODE_FULL_BLEND; 3542 3543 if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state)) 3544 val |= PIPEMISC_HDR_MODE_PRECISION; 3545 3546 if (DISPLAY_VER(dev_priv) >= 12) 3547 val |= PIPEMISC_PIXEL_ROUNDING_TRUNC; 3548 3549 intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val); 3550 } 3551 3552 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) 3553 { 3554 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3555 u32 tmp; 3556 3557 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); 3558 3559 switch (tmp & PIPEMISC_BPC_MASK) { 3560 case PIPEMISC_BPC_6: 3561 return 18; 3562 case PIPEMISC_BPC_8: 3563 return 24; 3564 case PIPEMISC_BPC_10: 3565 return 30; 3566 /* 3567 * PORT OUTPUT 12 BPC defined for ADLP+. 3568 * 3569 * TODO: 3570 * For previous platforms with DSI interface, bits 5:7 3571 * are used for storing pipe_bpp irrespective of dithering. 3572 * Since the value of 12 BPC is not defined for these bits 3573 * on older platforms, need to find a workaround for 12 BPC 3574 * MIPI DSI HW readout. 3575 */ 3576 case PIPEMISC_BPC_12_ADLP: 3577 if (DISPLAY_VER(dev_priv) > 12) 3578 return 36; 3579 fallthrough; 3580 default: 3581 MISSING_CASE(tmp); 3582 return 0; 3583 } 3584 } 3585 3586 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) 3587 { 3588 /* 3589 * Account for spread spectrum to avoid 3590 * oversubscribing the link. Max center spread 3591 * is 2.5%; use 5% for safety's sake. 3592 */ 3593 u32 bps = target_clock * bpp * 21 / 20; 3594 return DIV_ROUND_UP(bps, link_bw * 8); 3595 } 3596 3597 void intel_get_m_n(struct drm_i915_private *i915, 3598 struct intel_link_m_n *m_n, 3599 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 3600 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 3601 { 3602 m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK; 3603 m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK; 3604 m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK; 3605 m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK; 3606 m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1; 3607 } 3608 3609 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, 3610 enum transcoder transcoder, 3611 struct intel_link_m_n *m_n) 3612 { 3613 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3614 enum pipe pipe = crtc->pipe; 3615 3616 if (DISPLAY_VER(dev_priv) >= 5) 3617 intel_get_m_n(dev_priv, m_n, 3618 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 3619 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 3620 else 3621 intel_get_m_n(dev_priv, m_n, 3622 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 3623 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 3624 } 3625 3626 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, 3627 enum transcoder transcoder, 3628 struct intel_link_m_n *m_n) 3629 { 3630 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3631 3632 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 3633 return; 3634 3635 intel_get_m_n(dev_priv, m_n, 3636 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 3637 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 3638 } 3639 3640 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state, 3641 u32 pos, u32 size) 3642 { 3643 drm_rect_init(&crtc_state->pch_pfit.dst, 3644 pos >> 16, pos & 0xffff, 3645 size >> 16, size & 0xffff); 3646 } 3647 3648 static void skl_get_pfit_config(struct intel_crtc_state *crtc_state) 3649 { 3650 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3651 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3652 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; 3653 int id = -1; 3654 int i; 3655 3656 /* find scaler attached to this pipe */ 3657 for (i = 0; i < crtc->num_scalers; i++) { 3658 u32 ctl, pos, size; 3659 3660 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i)); 3661 if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN) 3662 continue; 3663 3664 id = i; 3665 crtc_state->pch_pfit.enabled = true; 3666 3667 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i)); 3668 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i)); 3669 3670 ilk_get_pfit_pos_size(crtc_state, pos, size); 3671 3672 scaler_state->scalers[i].in_use = true; 3673 break; 3674 } 3675 3676 scaler_state->scaler_id = id; 3677 if (id >= 0) 3678 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); 3679 else 3680 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); 3681 } 3682 3683 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state) 3684 { 3685 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3686 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3687 u32 ctl, pos, size; 3688 3689 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe)); 3690 if ((ctl & PF_ENABLE) == 0) 3691 return; 3692 3693 crtc_state->pch_pfit.enabled = true; 3694 3695 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe)); 3696 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe)); 3697 3698 ilk_get_pfit_pos_size(crtc_state, pos, size); 3699 3700 /* 3701 * We currently do not free assignements of panel fitters on 3702 * ivb/hsw (since we don't use the higher upscaling modes which 3703 * differentiates them) so just WARN about this case for now. 3704 */ 3705 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 7 && 3706 (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe)); 3707 } 3708 3709 static bool ilk_get_pipe_config(struct intel_crtc *crtc, 3710 struct intel_crtc_state *pipe_config) 3711 { 3712 struct drm_device *dev = crtc->base.dev; 3713 struct drm_i915_private *dev_priv = to_i915(dev); 3714 enum intel_display_power_domain power_domain; 3715 intel_wakeref_t wakeref; 3716 u32 tmp; 3717 bool ret; 3718 3719 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3720 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3721 if (!wakeref) 3722 return false; 3723 3724 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3725 pipe_config->shared_dpll = NULL; 3726 3727 ret = false; 3728 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); 3729 if (!(tmp & PIPECONF_ENABLE)) 3730 goto out; 3731 3732 switch (tmp & PIPECONF_BPC_MASK) { 3733 case PIPECONF_BPC_6: 3734 pipe_config->pipe_bpp = 18; 3735 break; 3736 case PIPECONF_BPC_8: 3737 pipe_config->pipe_bpp = 24; 3738 break; 3739 case PIPECONF_BPC_10: 3740 pipe_config->pipe_bpp = 30; 3741 break; 3742 case PIPECONF_BPC_12: 3743 pipe_config->pipe_bpp = 36; 3744 break; 3745 default: 3746 break; 3747 } 3748 3749 if (tmp & PIPECONF_COLOR_RANGE_SELECT) 3750 pipe_config->limited_color_range = true; 3751 3752 switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) { 3753 case PIPECONF_OUTPUT_COLORSPACE_YUV601: 3754 case PIPECONF_OUTPUT_COLORSPACE_YUV709: 3755 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3756 break; 3757 default: 3758 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3759 break; 3760 } 3761 3762 pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_ILK, tmp); 3763 3764 pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1; 3765 3766 pipe_config->msa_timing_delay = REG_FIELD_GET(PIPECONF_MSA_TIMING_DELAY_MASK, tmp); 3767 3768 pipe_config->csc_mode = intel_de_read(dev_priv, 3769 PIPE_CSC_MODE(crtc->pipe)); 3770 3771 i9xx_get_pipe_color_config(pipe_config); 3772 intel_color_get_config(pipe_config); 3773 3774 pipe_config->pixel_multiplier = 1; 3775 3776 ilk_pch_get_config(pipe_config); 3777 3778 intel_get_transcoder_timings(crtc, pipe_config); 3779 intel_get_pipe_src_size(crtc, pipe_config); 3780 3781 ilk_get_pfit_config(pipe_config); 3782 3783 ret = true; 3784 3785 out: 3786 intel_display_power_put(dev_priv, power_domain, wakeref); 3787 3788 return ret; 3789 } 3790 3791 static u8 bigjoiner_pipes(struct drm_i915_private *i915) 3792 { 3793 if (DISPLAY_VER(i915) >= 12) 3794 return BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D); 3795 else if (DISPLAY_VER(i915) >= 11) 3796 return BIT(PIPE_B) | BIT(PIPE_C); 3797 else 3798 return 0; 3799 } 3800 3801 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv, 3802 enum transcoder cpu_transcoder) 3803 { 3804 enum intel_display_power_domain power_domain; 3805 intel_wakeref_t wakeref; 3806 u32 tmp = 0; 3807 3808 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3809 3810 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3811 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3812 3813 return tmp & TRANS_DDI_FUNC_ENABLE; 3814 } 3815 3816 static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv, 3817 u8 *master_pipes, u8 *slave_pipes) 3818 { 3819 struct intel_crtc *crtc; 3820 3821 *master_pipes = 0; 3822 *slave_pipes = 0; 3823 3824 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, 3825 bigjoiner_pipes(dev_priv)) { 3826 enum intel_display_power_domain power_domain; 3827 enum pipe pipe = crtc->pipe; 3828 intel_wakeref_t wakeref; 3829 3830 power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe); 3831 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3832 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3833 3834 if (!(tmp & BIG_JOINER_ENABLE)) 3835 continue; 3836 3837 if (tmp & MASTER_BIG_JOINER_ENABLE) 3838 *master_pipes |= BIT(pipe); 3839 else 3840 *slave_pipes |= BIT(pipe); 3841 } 3842 3843 if (DISPLAY_VER(dev_priv) < 13) 3844 continue; 3845 3846 power_domain = POWER_DOMAIN_PIPE(pipe); 3847 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3848 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3849 3850 if (tmp & UNCOMPRESSED_JOINER_MASTER) 3851 *master_pipes |= BIT(pipe); 3852 if (tmp & UNCOMPRESSED_JOINER_SLAVE) 3853 *slave_pipes |= BIT(pipe); 3854 } 3855 } 3856 3857 /* Bigjoiner pipes should always be consecutive master and slave */ 3858 drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1, 3859 "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n", 3860 *master_pipes, *slave_pipes); 3861 } 3862 3863 static enum pipe get_bigjoiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3864 { 3865 if ((slave_pipes & BIT(pipe)) == 0) 3866 return pipe; 3867 3868 /* ignore everything above our pipe */ 3869 master_pipes &= ~GENMASK(7, pipe); 3870 3871 /* highest remaining bit should be our master pipe */ 3872 return fls(master_pipes) - 1; 3873 } 3874 3875 static u8 get_bigjoiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3876 { 3877 enum pipe master_pipe, next_master_pipe; 3878 3879 master_pipe = get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes); 3880 3881 if ((master_pipes & BIT(master_pipe)) == 0) 3882 return 0; 3883 3884 /* ignore our master pipe and everything below it */ 3885 master_pipes &= ~GENMASK(master_pipe, 0); 3886 /* make sure a high bit is set for the ffs() */ 3887 master_pipes |= BIT(7); 3888 /* lowest remaining bit should be the next master pipe */ 3889 next_master_pipe = ffs(master_pipes) - 1; 3890 3891 return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe); 3892 } 3893 3894 static u8 hsw_panel_transcoders(struct drm_i915_private *i915) 3895 { 3896 u8 panel_transcoder_mask = BIT(TRANSCODER_EDP); 3897 3898 if (DISPLAY_VER(i915) >= 11) 3899 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); 3900 3901 return panel_transcoder_mask; 3902 } 3903 3904 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) 3905 { 3906 struct drm_device *dev = crtc->base.dev; 3907 struct drm_i915_private *dev_priv = to_i915(dev); 3908 u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv); 3909 enum transcoder cpu_transcoder; 3910 u8 master_pipes, slave_pipes; 3911 u8 enabled_transcoders = 0; 3912 3913 /* 3914 * XXX: Do intel_display_power_get_if_enabled before reading this (for 3915 * consistency and less surprising code; it's in always on power). 3916 */ 3917 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, 3918 panel_transcoder_mask) { 3919 enum intel_display_power_domain power_domain; 3920 intel_wakeref_t wakeref; 3921 enum pipe trans_pipe; 3922 u32 tmp = 0; 3923 3924 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3925 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3926 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3927 3928 if (!(tmp & TRANS_DDI_FUNC_ENABLE)) 3929 continue; 3930 3931 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 3932 default: 3933 drm_WARN(dev, 1, 3934 "unknown pipe linked to transcoder %s\n", 3935 transcoder_name(cpu_transcoder)); 3936 fallthrough; 3937 case TRANS_DDI_EDP_INPUT_A_ONOFF: 3938 case TRANS_DDI_EDP_INPUT_A_ON: 3939 trans_pipe = PIPE_A; 3940 break; 3941 case TRANS_DDI_EDP_INPUT_B_ONOFF: 3942 trans_pipe = PIPE_B; 3943 break; 3944 case TRANS_DDI_EDP_INPUT_C_ONOFF: 3945 trans_pipe = PIPE_C; 3946 break; 3947 case TRANS_DDI_EDP_INPUT_D_ONOFF: 3948 trans_pipe = PIPE_D; 3949 break; 3950 } 3951 3952 if (trans_pipe == crtc->pipe) 3953 enabled_transcoders |= BIT(cpu_transcoder); 3954 } 3955 3956 /* single pipe or bigjoiner master */ 3957 cpu_transcoder = (enum transcoder) crtc->pipe; 3958 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 3959 enabled_transcoders |= BIT(cpu_transcoder); 3960 3961 /* bigjoiner slave -> consider the master pipe's transcoder as well */ 3962 enabled_bigjoiner_pipes(dev_priv, &master_pipes, &slave_pipes); 3963 if (slave_pipes & BIT(crtc->pipe)) { 3964 cpu_transcoder = (enum transcoder) 3965 get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes); 3966 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 3967 enabled_transcoders |= BIT(cpu_transcoder); 3968 } 3969 3970 return enabled_transcoders; 3971 } 3972 3973 static bool has_edp_transcoders(u8 enabled_transcoders) 3974 { 3975 return enabled_transcoders & BIT(TRANSCODER_EDP); 3976 } 3977 3978 static bool has_dsi_transcoders(u8 enabled_transcoders) 3979 { 3980 return enabled_transcoders & (BIT(TRANSCODER_DSI_0) | 3981 BIT(TRANSCODER_DSI_1)); 3982 } 3983 3984 static bool has_pipe_transcoders(u8 enabled_transcoders) 3985 { 3986 return enabled_transcoders & ~(BIT(TRANSCODER_EDP) | 3987 BIT(TRANSCODER_DSI_0) | 3988 BIT(TRANSCODER_DSI_1)); 3989 } 3990 3991 static void assert_enabled_transcoders(struct drm_i915_private *i915, 3992 u8 enabled_transcoders) 3993 { 3994 /* Only one type of transcoder please */ 3995 drm_WARN_ON(&i915->drm, 3996 has_edp_transcoders(enabled_transcoders) + 3997 has_dsi_transcoders(enabled_transcoders) + 3998 has_pipe_transcoders(enabled_transcoders) > 1); 3999 4000 /* Only DSI transcoders can be ganged */ 4001 drm_WARN_ON(&i915->drm, 4002 !has_dsi_transcoders(enabled_transcoders) && 4003 !is_power_of_2(enabled_transcoders)); 4004 } 4005 4006 static bool hsw_get_transcoder_state(struct intel_crtc *crtc, 4007 struct intel_crtc_state *pipe_config, 4008 struct intel_display_power_domain_set *power_domain_set) 4009 { 4010 struct drm_device *dev = crtc->base.dev; 4011 struct drm_i915_private *dev_priv = to_i915(dev); 4012 unsigned long enabled_transcoders; 4013 u32 tmp; 4014 4015 enabled_transcoders = hsw_enabled_transcoders(crtc); 4016 if (!enabled_transcoders) 4017 return false; 4018 4019 assert_enabled_transcoders(dev_priv, enabled_transcoders); 4020 4021 /* 4022 * With the exception of DSI we should only ever have 4023 * a single enabled transcoder. With DSI let's just 4024 * pick the first one. 4025 */ 4026 pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1; 4027 4028 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 4029 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) 4030 return false; 4031 4032 if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) { 4033 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); 4034 4035 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF) 4036 pipe_config->pch_pfit.force_thru = true; 4037 } 4038 4039 tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder)); 4040 4041 return tmp & PIPECONF_ENABLE; 4042 } 4043 4044 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, 4045 struct intel_crtc_state *pipe_config, 4046 struct intel_display_power_domain_set *power_domain_set) 4047 { 4048 struct drm_device *dev = crtc->base.dev; 4049 struct drm_i915_private *dev_priv = to_i915(dev); 4050 enum transcoder cpu_transcoder; 4051 enum port port; 4052 u32 tmp; 4053 4054 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { 4055 if (port == PORT_A) 4056 cpu_transcoder = TRANSCODER_DSI_A; 4057 else 4058 cpu_transcoder = TRANSCODER_DSI_C; 4059 4060 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 4061 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) 4062 continue; 4063 4064 /* 4065 * The PLL needs to be enabled with a valid divider 4066 * configuration, otherwise accessing DSI registers will hang 4067 * the machine. See BSpec North Display Engine 4068 * registers/MIPI[BXT]. We can break out here early, since we 4069 * need the same DSI PLL to be enabled for both DSI ports. 4070 */ 4071 if (!bxt_dsi_pll_is_enabled(dev_priv)) 4072 break; 4073 4074 /* XXX: this works for video mode only */ 4075 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); 4076 if (!(tmp & DPI_ENABLE)) 4077 continue; 4078 4079 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 4080 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) 4081 continue; 4082 4083 pipe_config->cpu_transcoder = cpu_transcoder; 4084 break; 4085 } 4086 4087 return transcoder_is_dsi(pipe_config->cpu_transcoder); 4088 } 4089 4090 static void intel_bigjoiner_get_config(struct intel_crtc_state *crtc_state) 4091 { 4092 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4093 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4094 u8 master_pipes, slave_pipes; 4095 enum pipe pipe = crtc->pipe; 4096 4097 enabled_bigjoiner_pipes(i915, &master_pipes, &slave_pipes); 4098 4099 if (((master_pipes | slave_pipes) & BIT(pipe)) == 0) 4100 return; 4101 4102 crtc_state->bigjoiner_pipes = 4103 BIT(get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes)) | 4104 get_bigjoiner_slave_pipes(pipe, master_pipes, slave_pipes); 4105 } 4106 4107 static bool hsw_get_pipe_config(struct intel_crtc *crtc, 4108 struct intel_crtc_state *pipe_config) 4109 { 4110 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4111 struct intel_display_power_domain_set power_domain_set = { }; 4112 bool active; 4113 u32 tmp; 4114 4115 if (!intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set, 4116 POWER_DOMAIN_PIPE(crtc->pipe))) 4117 return false; 4118 4119 pipe_config->shared_dpll = NULL; 4120 4121 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_set); 4122 4123 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 4124 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_set)) { 4125 drm_WARN_ON(&dev_priv->drm, active); 4126 active = true; 4127 } 4128 4129 if (!active) 4130 goto out; 4131 4132 intel_dsc_get_config(pipe_config); 4133 intel_bigjoiner_get_config(pipe_config); 4134 4135 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || 4136 DISPLAY_VER(dev_priv) >= 11) 4137 intel_get_transcoder_timings(crtc, pipe_config); 4138 4139 if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder)) 4140 intel_vrr_get_config(crtc, pipe_config); 4141 4142 intel_get_pipe_src_size(crtc, pipe_config); 4143 4144 if (IS_HASWELL(dev_priv)) { 4145 u32 tmp = intel_de_read(dev_priv, 4146 PIPECONF(pipe_config->cpu_transcoder)); 4147 4148 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW) 4149 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 4150 else 4151 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 4152 } else { 4153 pipe_config->output_format = 4154 bdw_get_pipemisc_output_format(crtc); 4155 } 4156 4157 pipe_config->gamma_mode = intel_de_read(dev_priv, 4158 GAMMA_MODE(crtc->pipe)); 4159 4160 pipe_config->csc_mode = intel_de_read(dev_priv, 4161 PIPE_CSC_MODE(crtc->pipe)); 4162 4163 if (DISPLAY_VER(dev_priv) >= 9) { 4164 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe)); 4165 4166 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE) 4167 pipe_config->gamma_enable = true; 4168 4169 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE) 4170 pipe_config->csc_enable = true; 4171 } else { 4172 i9xx_get_pipe_color_config(pipe_config); 4173 } 4174 4175 intel_color_get_config(pipe_config); 4176 4177 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe)); 4178 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); 4179 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 4180 pipe_config->ips_linetime = 4181 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); 4182 4183 if (intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set, 4184 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) { 4185 if (DISPLAY_VER(dev_priv) >= 9) 4186 skl_get_pfit_config(pipe_config); 4187 else 4188 ilk_get_pfit_config(pipe_config); 4189 } 4190 4191 hsw_ips_get_config(pipe_config); 4192 4193 if (pipe_config->cpu_transcoder != TRANSCODER_EDP && 4194 !transcoder_is_dsi(pipe_config->cpu_transcoder)) { 4195 pipe_config->pixel_multiplier = 4196 intel_de_read(dev_priv, 4197 PIPE_MULT(pipe_config->cpu_transcoder)) + 1; 4198 } else { 4199 pipe_config->pixel_multiplier = 1; 4200 } 4201 4202 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { 4203 tmp = intel_de_read(dev_priv, CHICKEN_TRANS(pipe_config->cpu_transcoder)); 4204 4205 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1; 4206 } else { 4207 /* no idea if this is correct */ 4208 pipe_config->framestart_delay = 1; 4209 } 4210 4211 out: 4212 intel_display_power_put_all_in_set(dev_priv, &power_domain_set); 4213 4214 return active; 4215 } 4216 4217 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state) 4218 { 4219 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4220 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4221 4222 if (!i915->display->get_pipe_config(crtc, crtc_state)) 4223 return false; 4224 4225 crtc_state->hw.active = true; 4226 4227 intel_crtc_readout_derived_state(crtc_state); 4228 4229 return true; 4230 } 4231 4232 /* VESA 640x480x72Hz mode to set on the pipe */ 4233 static const struct drm_display_mode load_detect_mode = { 4234 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, 4235 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 4236 }; 4237 4238 static int intel_modeset_disable_planes(struct drm_atomic_state *state, 4239 struct drm_crtc *crtc) 4240 { 4241 struct drm_plane *plane; 4242 struct drm_plane_state *plane_state; 4243 int ret, i; 4244 4245 ret = drm_atomic_add_affected_planes(state, crtc); 4246 if (ret) 4247 return ret; 4248 4249 for_each_new_plane_in_state(state, plane, plane_state, i) { 4250 if (plane_state->crtc != crtc) 4251 continue; 4252 4253 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL); 4254 if (ret) 4255 return ret; 4256 4257 drm_atomic_set_fb_for_plane(plane_state, NULL); 4258 } 4259 4260 return 0; 4261 } 4262 4263 int intel_get_load_detect_pipe(struct drm_connector *connector, 4264 struct intel_load_detect_pipe *old, 4265 struct drm_modeset_acquire_ctx *ctx) 4266 { 4267 struct intel_encoder *encoder = 4268 intel_attached_encoder(to_intel_connector(connector)); 4269 struct intel_crtc *possible_crtc; 4270 struct intel_crtc *crtc = NULL; 4271 struct drm_device *dev = encoder->base.dev; 4272 struct drm_i915_private *dev_priv = to_i915(dev); 4273 struct drm_mode_config *config = &dev->mode_config; 4274 struct drm_atomic_state *state = NULL, *restore_state = NULL; 4275 struct drm_connector_state *connector_state; 4276 struct intel_crtc_state *crtc_state; 4277 int ret; 4278 4279 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 4280 connector->base.id, connector->name, 4281 encoder->base.base.id, encoder->base.name); 4282 4283 old->restore_state = NULL; 4284 4285 drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex)); 4286 4287 /* 4288 * Algorithm gets a little messy: 4289 * 4290 * - if the connector already has an assigned crtc, use it (but make 4291 * sure it's on first) 4292 * 4293 * - try to find the first unused crtc that can drive this connector, 4294 * and use that if we find one 4295 */ 4296 4297 /* See if we already have a CRTC for this connector */ 4298 if (connector->state->crtc) { 4299 crtc = to_intel_crtc(connector->state->crtc); 4300 4301 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4302 if (ret) 4303 goto fail; 4304 4305 /* Make sure the crtc and connector are running */ 4306 goto found; 4307 } 4308 4309 /* Find an unused one (if possible) */ 4310 for_each_intel_crtc(dev, possible_crtc) { 4311 if (!(encoder->base.possible_crtcs & 4312 drm_crtc_mask(&possible_crtc->base))) 4313 continue; 4314 4315 ret = drm_modeset_lock(&possible_crtc->base.mutex, ctx); 4316 if (ret) 4317 goto fail; 4318 4319 if (possible_crtc->base.state->enable) { 4320 drm_modeset_unlock(&possible_crtc->base.mutex); 4321 continue; 4322 } 4323 4324 crtc = possible_crtc; 4325 break; 4326 } 4327 4328 /* 4329 * If we didn't find an unused CRTC, don't use any. 4330 */ 4331 if (!crtc) { 4332 drm_dbg_kms(&dev_priv->drm, 4333 "no pipe available for load-detect\n"); 4334 ret = -ENODEV; 4335 goto fail; 4336 } 4337 4338 found: 4339 state = drm_atomic_state_alloc(dev); 4340 restore_state = drm_atomic_state_alloc(dev); 4341 if (!state || !restore_state) { 4342 ret = -ENOMEM; 4343 goto fail; 4344 } 4345 4346 state->acquire_ctx = ctx; 4347 restore_state->acquire_ctx = ctx; 4348 4349 connector_state = drm_atomic_get_connector_state(state, connector); 4350 if (IS_ERR(connector_state)) { 4351 ret = PTR_ERR(connector_state); 4352 goto fail; 4353 } 4354 4355 ret = drm_atomic_set_crtc_for_connector(connector_state, &crtc->base); 4356 if (ret) 4357 goto fail; 4358 4359 crtc_state = intel_atomic_get_crtc_state(state, crtc); 4360 if (IS_ERR(crtc_state)) { 4361 ret = PTR_ERR(crtc_state); 4362 goto fail; 4363 } 4364 4365 crtc_state->uapi.active = true; 4366 4367 ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi, 4368 &load_detect_mode); 4369 if (ret) 4370 goto fail; 4371 4372 ret = intel_modeset_disable_planes(state, &crtc->base); 4373 if (ret) 4374 goto fail; 4375 4376 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); 4377 if (!ret) 4378 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, &crtc->base)); 4379 if (!ret) 4380 ret = drm_atomic_add_affected_planes(restore_state, &crtc->base); 4381 if (ret) { 4382 drm_dbg_kms(&dev_priv->drm, 4383 "Failed to create a copy of old state to restore: %i\n", 4384 ret); 4385 goto fail; 4386 } 4387 4388 ret = drm_atomic_commit(state); 4389 if (ret) { 4390 drm_dbg_kms(&dev_priv->drm, 4391 "failed to set mode on load-detect pipe\n"); 4392 goto fail; 4393 } 4394 4395 old->restore_state = restore_state; 4396 drm_atomic_state_put(state); 4397 4398 /* let the connector get through one full cycle before testing */ 4399 intel_crtc_wait_for_next_vblank(crtc); 4400 4401 return true; 4402 4403 fail: 4404 if (state) { 4405 drm_atomic_state_put(state); 4406 state = NULL; 4407 } 4408 if (restore_state) { 4409 drm_atomic_state_put(restore_state); 4410 restore_state = NULL; 4411 } 4412 4413 if (ret == -EDEADLK) 4414 return ret; 4415 4416 return false; 4417 } 4418 4419 void intel_release_load_detect_pipe(struct drm_connector *connector, 4420 struct intel_load_detect_pipe *old, 4421 struct drm_modeset_acquire_ctx *ctx) 4422 { 4423 struct intel_encoder *intel_encoder = 4424 intel_attached_encoder(to_intel_connector(connector)); 4425 struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev); 4426 struct drm_encoder *encoder = &intel_encoder->base; 4427 struct drm_atomic_state *state = old->restore_state; 4428 int ret; 4429 4430 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 4431 connector->base.id, connector->name, 4432 encoder->base.id, encoder->name); 4433 4434 if (!state) 4435 return; 4436 4437 ret = drm_atomic_helper_commit_duplicated_state(state, ctx); 4438 if (ret) 4439 drm_dbg_kms(&i915->drm, 4440 "Couldn't release load detect pipe: %i\n", ret); 4441 drm_atomic_state_put(state); 4442 } 4443 4444 static int i9xx_pll_refclk(struct drm_device *dev, 4445 const struct intel_crtc_state *pipe_config) 4446 { 4447 struct drm_i915_private *dev_priv = to_i915(dev); 4448 u32 dpll = pipe_config->dpll_hw_state.dpll; 4449 4450 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) 4451 return dev_priv->vbt.lvds_ssc_freq; 4452 else if (HAS_PCH_SPLIT(dev_priv)) 4453 return 120000; 4454 else if (DISPLAY_VER(dev_priv) != 2) 4455 return 96000; 4456 else 4457 return 48000; 4458 } 4459 4460 /* Returns the clock of the currently programmed mode of the given pipe. */ 4461 void i9xx_crtc_clock_get(struct intel_crtc *crtc, 4462 struct intel_crtc_state *pipe_config) 4463 { 4464 struct drm_device *dev = crtc->base.dev; 4465 struct drm_i915_private *dev_priv = to_i915(dev); 4466 u32 dpll = pipe_config->dpll_hw_state.dpll; 4467 u32 fp; 4468 struct dpll clock; 4469 int port_clock; 4470 int refclk = i9xx_pll_refclk(dev, pipe_config); 4471 4472 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 4473 fp = pipe_config->dpll_hw_state.fp0; 4474 else 4475 fp = pipe_config->dpll_hw_state.fp1; 4476 4477 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 4478 if (IS_PINEVIEW(dev_priv)) { 4479 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; 4480 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; 4481 } else { 4482 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 4483 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 4484 } 4485 4486 if (DISPLAY_VER(dev_priv) != 2) { 4487 if (IS_PINEVIEW(dev_priv)) 4488 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> 4489 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); 4490 else 4491 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> 4492 DPLL_FPA01_P1_POST_DIV_SHIFT); 4493 4494 switch (dpll & DPLL_MODE_MASK) { 4495 case DPLLB_MODE_DAC_SERIAL: 4496 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 4497 5 : 10; 4498 break; 4499 case DPLLB_MODE_LVDS: 4500 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 4501 7 : 14; 4502 break; 4503 default: 4504 drm_dbg_kms(&dev_priv->drm, 4505 "Unknown DPLL mode %08x in programmed " 4506 "mode\n", (int)(dpll & DPLL_MODE_MASK)); 4507 return; 4508 } 4509 4510 if (IS_PINEVIEW(dev_priv)) 4511 port_clock = pnv_calc_dpll_params(refclk, &clock); 4512 else 4513 port_clock = i9xx_calc_dpll_params(refclk, &clock); 4514 } else { 4515 enum pipe lvds_pipe; 4516 4517 if (IS_I85X(dev_priv) && 4518 intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) && 4519 lvds_pipe == crtc->pipe) { 4520 u32 lvds = intel_de_read(dev_priv, LVDS); 4521 4522 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 4523 DPLL_FPA01_P1_POST_DIV_SHIFT); 4524 4525 if (lvds & LVDS_CLKB_POWER_UP) 4526 clock.p2 = 7; 4527 else 4528 clock.p2 = 14; 4529 } else { 4530 if (dpll & PLL_P1_DIVIDE_BY_TWO) 4531 clock.p1 = 2; 4532 else { 4533 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 4534 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 4535 } 4536 if (dpll & PLL_P2_DIVIDE_BY_4) 4537 clock.p2 = 4; 4538 else 4539 clock.p2 = 2; 4540 } 4541 4542 port_clock = i9xx_calc_dpll_params(refclk, &clock); 4543 } 4544 4545 /* 4546 * This value includes pixel_multiplier. We will use 4547 * port_clock to compute adjusted_mode.crtc_clock in the 4548 * encoder's get_config() function. 4549 */ 4550 pipe_config->port_clock = port_clock; 4551 } 4552 4553 int intel_dotclock_calculate(int link_freq, 4554 const struct intel_link_m_n *m_n) 4555 { 4556 /* 4557 * The calculation for the data clock is: 4558 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp 4559 * But we want to avoid losing precison if possible, so: 4560 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) 4561 * 4562 * and the link clock is simpler: 4563 * link_clock = (m * link_clock) / n 4564 */ 4565 4566 if (!m_n->link_n) 4567 return 0; 4568 4569 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n); 4570 } 4571 4572 /* Returns the currently programmed mode of the given encoder. */ 4573 struct drm_display_mode * 4574 intel_encoder_current_mode(struct intel_encoder *encoder) 4575 { 4576 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4577 struct intel_crtc_state *crtc_state; 4578 struct drm_display_mode *mode; 4579 struct intel_crtc *crtc; 4580 enum pipe pipe; 4581 4582 if (!encoder->get_hw_state(encoder, &pipe)) 4583 return NULL; 4584 4585 crtc = intel_crtc_for_pipe(dev_priv, pipe); 4586 4587 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 4588 if (!mode) 4589 return NULL; 4590 4591 crtc_state = intel_crtc_state_alloc(crtc); 4592 if (!crtc_state) { 4593 kfree(mode); 4594 return NULL; 4595 } 4596 4597 if (!intel_crtc_get_pipe_config(crtc_state)) { 4598 kfree(crtc_state); 4599 kfree(mode); 4600 return NULL; 4601 } 4602 4603 intel_encoder_get_config(encoder, crtc_state); 4604 4605 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode); 4606 4607 kfree(crtc_state); 4608 4609 return mode; 4610 } 4611 4612 static bool encoders_cloneable(const struct intel_encoder *a, 4613 const struct intel_encoder *b) 4614 { 4615 /* masks could be asymmetric, so check both ways */ 4616 return a == b || (a->cloneable & (1 << b->type) && 4617 b->cloneable & (1 << a->type)); 4618 } 4619 4620 static bool check_single_encoder_cloning(struct intel_atomic_state *state, 4621 struct intel_crtc *crtc, 4622 struct intel_encoder *encoder) 4623 { 4624 struct intel_encoder *source_encoder; 4625 struct drm_connector *connector; 4626 struct drm_connector_state *connector_state; 4627 int i; 4628 4629 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4630 if (connector_state->crtc != &crtc->base) 4631 continue; 4632 4633 source_encoder = 4634 to_intel_encoder(connector_state->best_encoder); 4635 if (!encoders_cloneable(encoder, source_encoder)) 4636 return false; 4637 } 4638 4639 return true; 4640 } 4641 4642 static int icl_add_linked_planes(struct intel_atomic_state *state) 4643 { 4644 struct intel_plane *plane, *linked; 4645 struct intel_plane_state *plane_state, *linked_plane_state; 4646 int i; 4647 4648 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4649 linked = plane_state->planar_linked_plane; 4650 4651 if (!linked) 4652 continue; 4653 4654 linked_plane_state = intel_atomic_get_plane_state(state, linked); 4655 if (IS_ERR(linked_plane_state)) 4656 return PTR_ERR(linked_plane_state); 4657 4658 drm_WARN_ON(state->base.dev, 4659 linked_plane_state->planar_linked_plane != plane); 4660 drm_WARN_ON(state->base.dev, 4661 linked_plane_state->planar_slave == plane_state->planar_slave); 4662 } 4663 4664 return 0; 4665 } 4666 4667 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state) 4668 { 4669 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4670 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4671 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 4672 struct intel_plane *plane, *linked; 4673 struct intel_plane_state *plane_state; 4674 int i; 4675 4676 if (DISPLAY_VER(dev_priv) < 11) 4677 return 0; 4678 4679 /* 4680 * Destroy all old plane links and make the slave plane invisible 4681 * in the crtc_state->active_planes mask. 4682 */ 4683 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4684 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane) 4685 continue; 4686 4687 plane_state->planar_linked_plane = NULL; 4688 if (plane_state->planar_slave && !plane_state->uapi.visible) { 4689 crtc_state->enabled_planes &= ~BIT(plane->id); 4690 crtc_state->active_planes &= ~BIT(plane->id); 4691 crtc_state->update_planes |= BIT(plane->id); 4692 crtc_state->data_rate[plane->id] = 0; 4693 crtc_state->rel_data_rate[plane->id] = 0; 4694 } 4695 4696 plane_state->planar_slave = false; 4697 } 4698 4699 if (!crtc_state->nv12_planes) 4700 return 0; 4701 4702 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4703 struct intel_plane_state *linked_state = NULL; 4704 4705 if (plane->pipe != crtc->pipe || 4706 !(crtc_state->nv12_planes & BIT(plane->id))) 4707 continue; 4708 4709 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) { 4710 if (!icl_is_nv12_y_plane(dev_priv, linked->id)) 4711 continue; 4712 4713 if (crtc_state->active_planes & BIT(linked->id)) 4714 continue; 4715 4716 linked_state = intel_atomic_get_plane_state(state, linked); 4717 if (IS_ERR(linked_state)) 4718 return PTR_ERR(linked_state); 4719 4720 break; 4721 } 4722 4723 if (!linked_state) { 4724 drm_dbg_kms(&dev_priv->drm, 4725 "Need %d free Y planes for planar YUV\n", 4726 hweight8(crtc_state->nv12_planes)); 4727 4728 return -EINVAL; 4729 } 4730 4731 plane_state->planar_linked_plane = linked; 4732 4733 linked_state->planar_slave = true; 4734 linked_state->planar_linked_plane = plane; 4735 crtc_state->enabled_planes |= BIT(linked->id); 4736 crtc_state->active_planes |= BIT(linked->id); 4737 crtc_state->update_planes |= BIT(linked->id); 4738 crtc_state->data_rate[linked->id] = 4739 crtc_state->data_rate_y[plane->id]; 4740 crtc_state->rel_data_rate[linked->id] = 4741 crtc_state->rel_data_rate_y[plane->id]; 4742 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n", 4743 linked->base.name, plane->base.name); 4744 4745 /* Copy parameters to slave plane */ 4746 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE; 4747 linked_state->color_ctl = plane_state->color_ctl; 4748 linked_state->view = plane_state->view; 4749 linked_state->decrypt = plane_state->decrypt; 4750 4751 intel_plane_copy_hw_state(linked_state, plane_state); 4752 linked_state->uapi.src = plane_state->uapi.src; 4753 linked_state->uapi.dst = plane_state->uapi.dst; 4754 4755 if (icl_is_hdr_plane(dev_priv, plane->id)) { 4756 if (linked->id == PLANE_SPRITE5) 4757 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL; 4758 else if (linked->id == PLANE_SPRITE4) 4759 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL; 4760 else if (linked->id == PLANE_SPRITE3) 4761 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL; 4762 else if (linked->id == PLANE_SPRITE2) 4763 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL; 4764 else 4765 MISSING_CASE(linked->id); 4766 } 4767 } 4768 4769 return 0; 4770 } 4771 4772 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state) 4773 { 4774 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 4775 struct intel_atomic_state *state = 4776 to_intel_atomic_state(new_crtc_state->uapi.state); 4777 const struct intel_crtc_state *old_crtc_state = 4778 intel_atomic_get_old_crtc_state(state, crtc); 4779 4780 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes; 4781 } 4782 4783 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) 4784 { 4785 const struct drm_display_mode *pipe_mode = 4786 &crtc_state->hw.pipe_mode; 4787 int linetime_wm; 4788 4789 if (!crtc_state->hw.enable) 4790 return 0; 4791 4792 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4793 pipe_mode->crtc_clock); 4794 4795 return min(linetime_wm, 0x1ff); 4796 } 4797 4798 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, 4799 const struct intel_cdclk_state *cdclk_state) 4800 { 4801 const struct drm_display_mode *pipe_mode = 4802 &crtc_state->hw.pipe_mode; 4803 int linetime_wm; 4804 4805 if (!crtc_state->hw.enable) 4806 return 0; 4807 4808 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4809 cdclk_state->logical.cdclk); 4810 4811 return min(linetime_wm, 0x1ff); 4812 } 4813 4814 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) 4815 { 4816 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4817 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4818 const struct drm_display_mode *pipe_mode = 4819 &crtc_state->hw.pipe_mode; 4820 int linetime_wm; 4821 4822 if (!crtc_state->hw.enable) 4823 return 0; 4824 4825 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8, 4826 crtc_state->pixel_rate); 4827 4828 /* Display WA #1135: BXT:ALL GLK:ALL */ 4829 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 4830 dev_priv->ipc_enabled) 4831 linetime_wm /= 2; 4832 4833 return min(linetime_wm, 0x1ff); 4834 } 4835 4836 static int hsw_compute_linetime_wm(struct intel_atomic_state *state, 4837 struct intel_crtc *crtc) 4838 { 4839 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4840 struct intel_crtc_state *crtc_state = 4841 intel_atomic_get_new_crtc_state(state, crtc); 4842 const struct intel_cdclk_state *cdclk_state; 4843 4844 if (DISPLAY_VER(dev_priv) >= 9) 4845 crtc_state->linetime = skl_linetime_wm(crtc_state); 4846 else 4847 crtc_state->linetime = hsw_linetime_wm(crtc_state); 4848 4849 if (!hsw_crtc_supports_ips(crtc)) 4850 return 0; 4851 4852 cdclk_state = intel_atomic_get_cdclk_state(state); 4853 if (IS_ERR(cdclk_state)) 4854 return PTR_ERR(cdclk_state); 4855 4856 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state, 4857 cdclk_state); 4858 4859 return 0; 4860 } 4861 4862 static int intel_crtc_atomic_check(struct intel_atomic_state *state, 4863 struct intel_crtc *crtc) 4864 { 4865 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4866 struct intel_crtc_state *crtc_state = 4867 intel_atomic_get_new_crtc_state(state, crtc); 4868 bool mode_changed = intel_crtc_needs_modeset(crtc_state); 4869 int ret; 4870 4871 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) && 4872 mode_changed && !crtc_state->hw.active) 4873 crtc_state->update_wm_post = true; 4874 4875 if (mode_changed) { 4876 ret = intel_dpll_crtc_compute_clock(state, crtc); 4877 if (ret) 4878 return ret; 4879 4880 ret = intel_dpll_crtc_get_shared_dpll(state, crtc); 4881 if (ret) 4882 return ret; 4883 } 4884 4885 /* 4886 * May need to update pipe gamma enable bits 4887 * when C8 planes are getting enabled/disabled. 4888 */ 4889 if (c8_planes_changed(crtc_state)) 4890 crtc_state->uapi.color_mgmt_changed = true; 4891 4892 if (mode_changed || crtc_state->update_pipe || 4893 crtc_state->uapi.color_mgmt_changed) { 4894 ret = intel_color_check(crtc_state); 4895 if (ret) 4896 return ret; 4897 } 4898 4899 ret = intel_compute_pipe_wm(state, crtc); 4900 if (ret) { 4901 drm_dbg_kms(&dev_priv->drm, 4902 "Target pipe watermarks are invalid\n"); 4903 return ret; 4904 } 4905 4906 /* 4907 * Calculate 'intermediate' watermarks that satisfy both the 4908 * old state and the new state. We can program these 4909 * immediately. 4910 */ 4911 ret = intel_compute_intermediate_wm(state, crtc); 4912 if (ret) { 4913 drm_dbg_kms(&dev_priv->drm, 4914 "No valid intermediate pipe watermarks are possible\n"); 4915 return ret; 4916 } 4917 4918 if (DISPLAY_VER(dev_priv) >= 9) { 4919 if (mode_changed || crtc_state->update_pipe) { 4920 ret = skl_update_scaler_crtc(crtc_state); 4921 if (ret) 4922 return ret; 4923 } 4924 4925 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state); 4926 if (ret) 4927 return ret; 4928 } 4929 4930 if (HAS_IPS(dev_priv)) { 4931 ret = hsw_ips_compute_config(state, crtc); 4932 if (ret) 4933 return ret; 4934 } 4935 4936 if (DISPLAY_VER(dev_priv) >= 9 || 4937 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 4938 ret = hsw_compute_linetime_wm(state, crtc); 4939 if (ret) 4940 return ret; 4941 4942 } 4943 4944 ret = intel_psr2_sel_fetch_update(state, crtc); 4945 if (ret) 4946 return ret; 4947 4948 return 0; 4949 } 4950 4951 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) 4952 { 4953 struct intel_connector *connector; 4954 struct drm_connector_list_iter conn_iter; 4955 4956 drm_connector_list_iter_begin(dev, &conn_iter); 4957 for_each_intel_connector_iter(connector, &conn_iter) { 4958 struct drm_connector_state *conn_state = connector->base.state; 4959 struct intel_encoder *encoder = 4960 to_intel_encoder(connector->base.encoder); 4961 4962 if (conn_state->crtc) 4963 drm_connector_put(&connector->base); 4964 4965 if (encoder) { 4966 struct intel_crtc *crtc = 4967 to_intel_crtc(encoder->base.crtc); 4968 const struct intel_crtc_state *crtc_state = 4969 to_intel_crtc_state(crtc->base.state); 4970 4971 conn_state->best_encoder = &encoder->base; 4972 conn_state->crtc = &crtc->base; 4973 conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3; 4974 4975 drm_connector_get(&connector->base); 4976 } else { 4977 conn_state->best_encoder = NULL; 4978 conn_state->crtc = NULL; 4979 } 4980 } 4981 drm_connector_list_iter_end(&conn_iter); 4982 } 4983 4984 static int 4985 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state, 4986 struct intel_crtc_state *crtc_state) 4987 { 4988 struct drm_connector *connector = conn_state->connector; 4989 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 4990 const struct drm_display_info *info = &connector->display_info; 4991 int bpp; 4992 4993 switch (conn_state->max_bpc) { 4994 case 6 ... 7: 4995 bpp = 6 * 3; 4996 break; 4997 case 8 ... 9: 4998 bpp = 8 * 3; 4999 break; 5000 case 10 ... 11: 5001 bpp = 10 * 3; 5002 break; 5003 case 12 ... 16: 5004 bpp = 12 * 3; 5005 break; 5006 default: 5007 MISSING_CASE(conn_state->max_bpc); 5008 return -EINVAL; 5009 } 5010 5011 if (bpp < crtc_state->pipe_bpp) { 5012 drm_dbg_kms(&i915->drm, 5013 "[CONNECTOR:%d:%s] Limiting display bpp to %d " 5014 "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n", 5015 connector->base.id, connector->name, 5016 bpp, 3 * info->bpc, 5017 3 * conn_state->max_requested_bpc, 5018 crtc_state->pipe_bpp); 5019 5020 crtc_state->pipe_bpp = bpp; 5021 } 5022 5023 return 0; 5024 } 5025 5026 static int 5027 compute_baseline_pipe_bpp(struct intel_atomic_state *state, 5028 struct intel_crtc *crtc) 5029 { 5030 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5031 struct intel_crtc_state *crtc_state = 5032 intel_atomic_get_new_crtc_state(state, crtc); 5033 struct drm_connector *connector; 5034 struct drm_connector_state *connector_state; 5035 int bpp, i; 5036 5037 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 5038 IS_CHERRYVIEW(dev_priv))) 5039 bpp = 10*3; 5040 else if (DISPLAY_VER(dev_priv) >= 5) 5041 bpp = 12*3; 5042 else 5043 bpp = 8*3; 5044 5045 crtc_state->pipe_bpp = bpp; 5046 5047 /* Clamp display bpp to connector max bpp */ 5048 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5049 int ret; 5050 5051 if (connector_state->crtc != &crtc->base) 5052 continue; 5053 5054 ret = compute_sink_pipe_bpp(connector_state, crtc_state); 5055 if (ret) 5056 return ret; 5057 } 5058 5059 return 0; 5060 } 5061 5062 static bool check_digital_port_conflicts(struct intel_atomic_state *state) 5063 { 5064 struct drm_device *dev = state->base.dev; 5065 struct drm_connector *connector; 5066 struct drm_connector_list_iter conn_iter; 5067 unsigned int used_ports = 0; 5068 unsigned int used_mst_ports = 0; 5069 bool ret = true; 5070 5071 /* 5072 * We're going to peek into connector->state, 5073 * hence connection_mutex must be held. 5074 */ 5075 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex); 5076 5077 /* 5078 * Walk the connector list instead of the encoder 5079 * list to detect the problem on ddi platforms 5080 * where there's just one encoder per digital port. 5081 */ 5082 drm_connector_list_iter_begin(dev, &conn_iter); 5083 drm_for_each_connector_iter(connector, &conn_iter) { 5084 struct drm_connector_state *connector_state; 5085 struct intel_encoder *encoder; 5086 5087 connector_state = 5088 drm_atomic_get_new_connector_state(&state->base, 5089 connector); 5090 if (!connector_state) 5091 connector_state = connector->state; 5092 5093 if (!connector_state->best_encoder) 5094 continue; 5095 5096 encoder = to_intel_encoder(connector_state->best_encoder); 5097 5098 drm_WARN_ON(dev, !connector_state->crtc); 5099 5100 switch (encoder->type) { 5101 case INTEL_OUTPUT_DDI: 5102 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev)))) 5103 break; 5104 fallthrough; 5105 case INTEL_OUTPUT_DP: 5106 case INTEL_OUTPUT_HDMI: 5107 case INTEL_OUTPUT_EDP: 5108 /* the same port mustn't appear more than once */ 5109 if (used_ports & BIT(encoder->port)) 5110 ret = false; 5111 5112 used_ports |= BIT(encoder->port); 5113 break; 5114 case INTEL_OUTPUT_DP_MST: 5115 used_mst_ports |= 5116 1 << encoder->port; 5117 break; 5118 default: 5119 break; 5120 } 5121 } 5122 drm_connector_list_iter_end(&conn_iter); 5123 5124 /* can't mix MST and SST/HDMI on the same port */ 5125 if (used_ports & used_mst_ports) 5126 return false; 5127 5128 return ret; 5129 } 5130 5131 static void 5132 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state, 5133 struct intel_crtc *crtc) 5134 { 5135 struct intel_crtc_state *crtc_state = 5136 intel_atomic_get_new_crtc_state(state, crtc); 5137 5138 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 5139 5140 drm_property_replace_blob(&crtc_state->hw.degamma_lut, 5141 crtc_state->uapi.degamma_lut); 5142 drm_property_replace_blob(&crtc_state->hw.gamma_lut, 5143 crtc_state->uapi.gamma_lut); 5144 drm_property_replace_blob(&crtc_state->hw.ctm, 5145 crtc_state->uapi.ctm); 5146 } 5147 5148 static void 5149 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state, 5150 struct intel_crtc *crtc) 5151 { 5152 struct intel_crtc_state *crtc_state = 5153 intel_atomic_get_new_crtc_state(state, crtc); 5154 5155 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 5156 5157 crtc_state->hw.enable = crtc_state->uapi.enable; 5158 crtc_state->hw.active = crtc_state->uapi.active; 5159 drm_mode_copy(&crtc_state->hw.mode, 5160 &crtc_state->uapi.mode); 5161 drm_mode_copy(&crtc_state->hw.adjusted_mode, 5162 &crtc_state->uapi.adjusted_mode); 5163 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter; 5164 5165 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 5166 } 5167 5168 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state) 5169 { 5170 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 5171 return; 5172 5173 crtc_state->uapi.enable = crtc_state->hw.enable; 5174 crtc_state->uapi.active = crtc_state->hw.active; 5175 drm_WARN_ON(crtc_state->uapi.crtc->dev, 5176 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0); 5177 5178 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode; 5179 crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter; 5180 5181 drm_property_replace_blob(&crtc_state->uapi.degamma_lut, 5182 crtc_state->hw.degamma_lut); 5183 drm_property_replace_blob(&crtc_state->uapi.gamma_lut, 5184 crtc_state->hw.gamma_lut); 5185 drm_property_replace_blob(&crtc_state->uapi.ctm, 5186 crtc_state->hw.ctm); 5187 } 5188 5189 static void 5190 copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state, 5191 struct intel_crtc *slave_crtc) 5192 { 5193 struct intel_crtc_state *slave_crtc_state = 5194 intel_atomic_get_new_crtc_state(state, slave_crtc); 5195 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 5196 const struct intel_crtc_state *master_crtc_state = 5197 intel_atomic_get_new_crtc_state(state, master_crtc); 5198 5199 drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut, 5200 master_crtc_state->hw.degamma_lut); 5201 drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut, 5202 master_crtc_state->hw.gamma_lut); 5203 drm_property_replace_blob(&slave_crtc_state->hw.ctm, 5204 master_crtc_state->hw.ctm); 5205 5206 slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed; 5207 } 5208 5209 static int 5210 copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state, 5211 struct intel_crtc *slave_crtc) 5212 { 5213 struct intel_crtc_state *slave_crtc_state = 5214 intel_atomic_get_new_crtc_state(state, slave_crtc); 5215 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 5216 const struct intel_crtc_state *master_crtc_state = 5217 intel_atomic_get_new_crtc_state(state, master_crtc); 5218 struct intel_crtc_state *saved_state; 5219 5220 WARN_ON(master_crtc_state->bigjoiner_pipes != 5221 slave_crtc_state->bigjoiner_pipes); 5222 5223 saved_state = kmemdup(master_crtc_state, sizeof(*saved_state), GFP_KERNEL); 5224 if (!saved_state) 5225 return -ENOMEM; 5226 5227 /* preserve some things from the slave's original crtc state */ 5228 saved_state->uapi = slave_crtc_state->uapi; 5229 saved_state->scaler_state = slave_crtc_state->scaler_state; 5230 saved_state->shared_dpll = slave_crtc_state->shared_dpll; 5231 saved_state->dpll_hw_state = slave_crtc_state->dpll_hw_state; 5232 saved_state->crc_enabled = slave_crtc_state->crc_enabled; 5233 5234 intel_crtc_free_hw_state(slave_crtc_state); 5235 memcpy(slave_crtc_state, saved_state, sizeof(*slave_crtc_state)); 5236 kfree(saved_state); 5237 5238 /* Re-init hw state */ 5239 memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw)); 5240 slave_crtc_state->hw.enable = master_crtc_state->hw.enable; 5241 slave_crtc_state->hw.active = master_crtc_state->hw.active; 5242 drm_mode_copy(&slave_crtc_state->hw.mode, 5243 &master_crtc_state->hw.mode); 5244 drm_mode_copy(&slave_crtc_state->hw.pipe_mode, 5245 &master_crtc_state->hw.pipe_mode); 5246 drm_mode_copy(&slave_crtc_state->hw.adjusted_mode, 5247 &master_crtc_state->hw.adjusted_mode); 5248 slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter; 5249 5250 copy_bigjoiner_crtc_state_nomodeset(state, slave_crtc); 5251 5252 slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed; 5253 slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed; 5254 slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed; 5255 5256 WARN_ON(master_crtc_state->bigjoiner_pipes != 5257 slave_crtc_state->bigjoiner_pipes); 5258 5259 return 0; 5260 } 5261 5262 static int 5263 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state, 5264 struct intel_crtc *crtc) 5265 { 5266 struct intel_crtc_state *crtc_state = 5267 intel_atomic_get_new_crtc_state(state, crtc); 5268 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5269 struct intel_crtc_state *saved_state; 5270 5271 saved_state = intel_crtc_state_alloc(crtc); 5272 if (!saved_state) 5273 return -ENOMEM; 5274 5275 /* free the old crtc_state->hw members */ 5276 intel_crtc_free_hw_state(crtc_state); 5277 5278 /* FIXME: before the switch to atomic started, a new pipe_config was 5279 * kzalloc'd. Code that depends on any field being zero should be 5280 * fixed, so that the crtc_state can be safely duplicated. For now, 5281 * only fields that are know to not cause problems are preserved. */ 5282 5283 saved_state->uapi = crtc_state->uapi; 5284 saved_state->scaler_state = crtc_state->scaler_state; 5285 saved_state->shared_dpll = crtc_state->shared_dpll; 5286 saved_state->dpll_hw_state = crtc_state->dpll_hw_state; 5287 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, 5288 sizeof(saved_state->icl_port_dplls)); 5289 saved_state->crc_enabled = crtc_state->crc_enabled; 5290 if (IS_G4X(dev_priv) || 5291 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5292 saved_state->wm = crtc_state->wm; 5293 5294 memcpy(crtc_state, saved_state, sizeof(*crtc_state)); 5295 kfree(saved_state); 5296 5297 intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc); 5298 5299 return 0; 5300 } 5301 5302 static int 5303 intel_modeset_pipe_config(struct intel_atomic_state *state, 5304 struct intel_crtc *crtc) 5305 { 5306 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 5307 struct intel_crtc_state *crtc_state = 5308 intel_atomic_get_new_crtc_state(state, crtc); 5309 struct drm_connector *connector; 5310 struct drm_connector_state *connector_state; 5311 int pipe_src_w, pipe_src_h; 5312 int base_bpp, ret, i; 5313 bool retry = true; 5314 5315 crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe; 5316 5317 crtc_state->framestart_delay = 1; 5318 5319 /* 5320 * Sanitize sync polarity flags based on requested ones. If neither 5321 * positive or negative polarity is requested, treat this as meaning 5322 * negative polarity. 5323 */ 5324 if (!(crtc_state->hw.adjusted_mode.flags & 5325 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) 5326 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; 5327 5328 if (!(crtc_state->hw.adjusted_mode.flags & 5329 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 5330 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; 5331 5332 ret = compute_baseline_pipe_bpp(state, crtc); 5333 if (ret) 5334 return ret; 5335 5336 base_bpp = crtc_state->pipe_bpp; 5337 5338 /* 5339 * Determine the real pipe dimensions. Note that stereo modes can 5340 * increase the actual pipe size due to the frame doubling and 5341 * insertion of additional space for blanks between the frame. This 5342 * is stored in the crtc timings. We use the requested mode to do this 5343 * computation to clearly distinguish it from the adjusted mode, which 5344 * can be changed by the connectors in the below retry loop. 5345 */ 5346 drm_mode_get_hv_timing(&crtc_state->hw.mode, 5347 &pipe_src_w, &pipe_src_h); 5348 drm_rect_init(&crtc_state->pipe_src, 0, 0, 5349 pipe_src_w, pipe_src_h); 5350 5351 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5352 struct intel_encoder *encoder = 5353 to_intel_encoder(connector_state->best_encoder); 5354 5355 if (connector_state->crtc != &crtc->base) 5356 continue; 5357 5358 if (!check_single_encoder_cloning(state, crtc, encoder)) { 5359 drm_dbg_kms(&i915->drm, 5360 "[ENCODER:%d:%s] rejecting invalid cloning configuration\n", 5361 encoder->base.base.id, encoder->base.name); 5362 return -EINVAL; 5363 } 5364 5365 /* 5366 * Determine output_types before calling the .compute_config() 5367 * hooks so that the hooks can use this information safely. 5368 */ 5369 if (encoder->compute_output_type) 5370 crtc_state->output_types |= 5371 BIT(encoder->compute_output_type(encoder, crtc_state, 5372 connector_state)); 5373 else 5374 crtc_state->output_types |= BIT(encoder->type); 5375 } 5376 5377 encoder_retry: 5378 /* Ensure the port clock defaults are reset when retrying. */ 5379 crtc_state->port_clock = 0; 5380 crtc_state->pixel_multiplier = 1; 5381 5382 /* Fill in default crtc timings, allow encoders to overwrite them. */ 5383 drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode, 5384 CRTC_STEREO_DOUBLE); 5385 5386 /* Pass our mode to the connectors and the CRTC to give them a chance to 5387 * adjust it according to limitations or connector properties, and also 5388 * a chance to reject the mode entirely. 5389 */ 5390 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5391 struct intel_encoder *encoder = 5392 to_intel_encoder(connector_state->best_encoder); 5393 5394 if (connector_state->crtc != &crtc->base) 5395 continue; 5396 5397 ret = encoder->compute_config(encoder, crtc_state, 5398 connector_state); 5399 if (ret == -EDEADLK) 5400 return ret; 5401 if (ret < 0) { 5402 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n", 5403 encoder->base.base.id, encoder->base.name, ret); 5404 return ret; 5405 } 5406 } 5407 5408 /* Set default port clock if not overwritten by the encoder. Needs to be 5409 * done afterwards in case the encoder adjusts the mode. */ 5410 if (!crtc_state->port_clock) 5411 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock 5412 * crtc_state->pixel_multiplier; 5413 5414 ret = intel_crtc_compute_config(state, crtc); 5415 if (ret == -EDEADLK) 5416 return ret; 5417 if (ret == -EAGAIN) { 5418 if (drm_WARN(&i915->drm, !retry, 5419 "[CRTC:%d:%s] loop in pipe configuration computation\n", 5420 crtc->base.base.id, crtc->base.name)) 5421 return -EINVAL; 5422 5423 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] bw constrained, retrying\n", 5424 crtc->base.base.id, crtc->base.name); 5425 retry = false; 5426 goto encoder_retry; 5427 } 5428 if (ret < 0) { 5429 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n", 5430 crtc->base.base.id, crtc->base.name, ret); 5431 return ret; 5432 } 5433 5434 /* Dithering seems to not pass-through bits correctly when it should, so 5435 * only enable it on 6bpc panels and when its not a compliance 5436 * test requesting 6bpc video pattern. 5437 */ 5438 crtc_state->dither = (crtc_state->pipe_bpp == 6*3) && 5439 !crtc_state->dither_force_disable; 5440 drm_dbg_kms(&i915->drm, 5441 "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n", 5442 crtc->base.base.id, crtc->base.name, 5443 base_bpp, crtc_state->pipe_bpp, crtc_state->dither); 5444 5445 return 0; 5446 } 5447 5448 static int 5449 intel_modeset_pipe_config_late(struct intel_atomic_state *state, 5450 struct intel_crtc *crtc) 5451 { 5452 struct intel_crtc_state *crtc_state = 5453 intel_atomic_get_new_crtc_state(state, crtc); 5454 struct drm_connector_state *conn_state; 5455 struct drm_connector *connector; 5456 int i; 5457 5458 intel_bigjoiner_adjust_pipe_src(crtc_state); 5459 5460 for_each_new_connector_in_state(&state->base, connector, 5461 conn_state, i) { 5462 struct intel_encoder *encoder = 5463 to_intel_encoder(conn_state->best_encoder); 5464 int ret; 5465 5466 if (conn_state->crtc != &crtc->base || 5467 !encoder->compute_config_late) 5468 continue; 5469 5470 ret = encoder->compute_config_late(encoder, crtc_state, 5471 conn_state); 5472 if (ret) 5473 return ret; 5474 } 5475 5476 return 0; 5477 } 5478 5479 bool intel_fuzzy_clock_check(int clock1, int clock2) 5480 { 5481 int diff; 5482 5483 if (clock1 == clock2) 5484 return true; 5485 5486 if (!clock1 || !clock2) 5487 return false; 5488 5489 diff = abs(clock1 - clock2); 5490 5491 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) 5492 return true; 5493 5494 return false; 5495 } 5496 5497 static bool 5498 intel_compare_m_n(unsigned int m, unsigned int n, 5499 unsigned int m2, unsigned int n2, 5500 bool exact) 5501 { 5502 if (m == m2 && n == n2) 5503 return true; 5504 5505 if (exact || !m || !n || !m2 || !n2) 5506 return false; 5507 5508 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); 5509 5510 if (n > n2) { 5511 while (n > n2) { 5512 m2 <<= 1; 5513 n2 <<= 1; 5514 } 5515 } else if (n < n2) { 5516 while (n < n2) { 5517 m <<= 1; 5518 n <<= 1; 5519 } 5520 } 5521 5522 if (n != n2) 5523 return false; 5524 5525 return intel_fuzzy_clock_check(m, m2); 5526 } 5527 5528 static bool 5529 intel_compare_link_m_n(const struct intel_link_m_n *m_n, 5530 const struct intel_link_m_n *m2_n2, 5531 bool exact) 5532 { 5533 return m_n->tu == m2_n2->tu && 5534 intel_compare_m_n(m_n->data_m, m_n->data_n, 5535 m2_n2->data_m, m2_n2->data_n, exact) && 5536 intel_compare_m_n(m_n->link_m, m_n->link_n, 5537 m2_n2->link_m, m2_n2->link_n, exact); 5538 } 5539 5540 static bool 5541 intel_compare_infoframe(const union hdmi_infoframe *a, 5542 const union hdmi_infoframe *b) 5543 { 5544 return memcmp(a, b, sizeof(*a)) == 0; 5545 } 5546 5547 static bool 5548 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a, 5549 const struct drm_dp_vsc_sdp *b) 5550 { 5551 return memcmp(a, b, sizeof(*a)) == 0; 5552 } 5553 5554 static void 5555 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv, 5556 bool fastset, const char *name, 5557 const union hdmi_infoframe *a, 5558 const union hdmi_infoframe *b) 5559 { 5560 if (fastset) { 5561 if (!drm_debug_enabled(DRM_UT_KMS)) 5562 return; 5563 5564 drm_dbg_kms(&dev_priv->drm, 5565 "fastset mismatch in %s infoframe\n", name); 5566 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 5567 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a); 5568 drm_dbg_kms(&dev_priv->drm, "found:\n"); 5569 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b); 5570 } else { 5571 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name); 5572 drm_err(&dev_priv->drm, "expected:\n"); 5573 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a); 5574 drm_err(&dev_priv->drm, "found:\n"); 5575 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b); 5576 } 5577 } 5578 5579 static void 5580 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv, 5581 bool fastset, const char *name, 5582 const struct drm_dp_vsc_sdp *a, 5583 const struct drm_dp_vsc_sdp *b) 5584 { 5585 if (fastset) { 5586 if (!drm_debug_enabled(DRM_UT_KMS)) 5587 return; 5588 5589 drm_dbg_kms(&dev_priv->drm, 5590 "fastset mismatch in %s dp sdp\n", name); 5591 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 5592 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a); 5593 drm_dbg_kms(&dev_priv->drm, "found:\n"); 5594 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b); 5595 } else { 5596 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name); 5597 drm_err(&dev_priv->drm, "expected:\n"); 5598 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a); 5599 drm_err(&dev_priv->drm, "found:\n"); 5600 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b); 5601 } 5602 } 5603 5604 static void __printf(4, 5) 5605 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc, 5606 const char *name, const char *format, ...) 5607 { 5608 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 5609 struct va_format vaf; 5610 va_list args; 5611 5612 va_start(args, format); 5613 vaf.fmt = format; 5614 vaf.va = &args; 5615 5616 if (fastset) 5617 drm_dbg_kms(&i915->drm, 5618 "[CRTC:%d:%s] fastset mismatch in %s %pV\n", 5619 crtc->base.base.id, crtc->base.name, name, &vaf); 5620 else 5621 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n", 5622 crtc->base.base.id, crtc->base.name, name, &vaf); 5623 5624 va_end(args); 5625 } 5626 5627 static bool fastboot_enabled(struct drm_i915_private *dev_priv) 5628 { 5629 if (dev_priv->params.fastboot != -1) 5630 return dev_priv->params.fastboot; 5631 5632 /* Enable fastboot by default on Skylake and newer */ 5633 if (DISPLAY_VER(dev_priv) >= 9) 5634 return true; 5635 5636 /* Enable fastboot by default on VLV and CHV */ 5637 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5638 return true; 5639 5640 /* Disabled by default on all others */ 5641 return false; 5642 } 5643 5644 bool 5645 intel_pipe_config_compare(const struct intel_crtc_state *current_config, 5646 const struct intel_crtc_state *pipe_config, 5647 bool fastset) 5648 { 5649 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev); 5650 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 5651 bool ret = true; 5652 u32 bp_gamma = 0; 5653 bool fixup_inherited = fastset && 5654 current_config->inherited && !pipe_config->inherited; 5655 5656 if (fixup_inherited && !fastboot_enabled(dev_priv)) { 5657 drm_dbg_kms(&dev_priv->drm, 5658 "initial modeset and fastboot not set\n"); 5659 ret = false; 5660 } 5661 5662 #define PIPE_CONF_CHECK_X(name) do { \ 5663 if (current_config->name != pipe_config->name) { \ 5664 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5665 "(expected 0x%08x, found 0x%08x)", \ 5666 current_config->name, \ 5667 pipe_config->name); \ 5668 ret = false; \ 5669 } \ 5670 } while (0) 5671 5672 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \ 5673 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \ 5674 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5675 "(expected 0x%08x, found 0x%08x)", \ 5676 current_config->name & (mask), \ 5677 pipe_config->name & (mask)); \ 5678 ret = false; \ 5679 } \ 5680 } while (0) 5681 5682 #define PIPE_CONF_CHECK_I(name) do { \ 5683 if (current_config->name != pipe_config->name) { \ 5684 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5685 "(expected %i, found %i)", \ 5686 current_config->name, \ 5687 pipe_config->name); \ 5688 ret = false; \ 5689 } \ 5690 } while (0) 5691 5692 #define PIPE_CONF_CHECK_BOOL(name) do { \ 5693 if (current_config->name != pipe_config->name) { \ 5694 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5695 "(expected %s, found %s)", \ 5696 str_yes_no(current_config->name), \ 5697 str_yes_no(pipe_config->name)); \ 5698 ret = false; \ 5699 } \ 5700 } while (0) 5701 5702 /* 5703 * Checks state where we only read out the enabling, but not the entire 5704 * state itself (like full infoframes or ELD for audio). These states 5705 * require a full modeset on bootup to fix up. 5706 */ 5707 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \ 5708 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \ 5709 PIPE_CONF_CHECK_BOOL(name); \ 5710 } else { \ 5711 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5712 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \ 5713 str_yes_no(current_config->name), \ 5714 str_yes_no(pipe_config->name)); \ 5715 ret = false; \ 5716 } \ 5717 } while (0) 5718 5719 #define PIPE_CONF_CHECK_P(name) do { \ 5720 if (current_config->name != pipe_config->name) { \ 5721 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5722 "(expected %p, found %p)", \ 5723 current_config->name, \ 5724 pipe_config->name); \ 5725 ret = false; \ 5726 } \ 5727 } while (0) 5728 5729 #define PIPE_CONF_CHECK_M_N(name) do { \ 5730 if (!intel_compare_link_m_n(¤t_config->name, \ 5731 &pipe_config->name,\ 5732 !fastset)) { \ 5733 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5734 "(expected tu %i data %i/%i link %i/%i, " \ 5735 "found tu %i, data %i/%i link %i/%i)", \ 5736 current_config->name.tu, \ 5737 current_config->name.data_m, \ 5738 current_config->name.data_n, \ 5739 current_config->name.link_m, \ 5740 current_config->name.link_n, \ 5741 pipe_config->name.tu, \ 5742 pipe_config->name.data_m, \ 5743 pipe_config->name.data_n, \ 5744 pipe_config->name.link_m, \ 5745 pipe_config->name.link_n); \ 5746 ret = false; \ 5747 } \ 5748 } while (0) 5749 5750 #define PIPE_CONF_CHECK_TIMINGS(name) do { \ 5751 PIPE_CONF_CHECK_I(name.crtc_hdisplay); \ 5752 PIPE_CONF_CHECK_I(name.crtc_htotal); \ 5753 PIPE_CONF_CHECK_I(name.crtc_hblank_start); \ 5754 PIPE_CONF_CHECK_I(name.crtc_hblank_end); \ 5755 PIPE_CONF_CHECK_I(name.crtc_hsync_start); \ 5756 PIPE_CONF_CHECK_I(name.crtc_hsync_end); \ 5757 PIPE_CONF_CHECK_I(name.crtc_vdisplay); \ 5758 PIPE_CONF_CHECK_I(name.crtc_vtotal); \ 5759 PIPE_CONF_CHECK_I(name.crtc_vblank_start); \ 5760 PIPE_CONF_CHECK_I(name.crtc_vblank_end); \ 5761 PIPE_CONF_CHECK_I(name.crtc_vsync_start); \ 5762 PIPE_CONF_CHECK_I(name.crtc_vsync_end); \ 5763 } while (0) 5764 5765 #define PIPE_CONF_CHECK_RECT(name) do { \ 5766 PIPE_CONF_CHECK_I(name.x1); \ 5767 PIPE_CONF_CHECK_I(name.x2); \ 5768 PIPE_CONF_CHECK_I(name.y1); \ 5769 PIPE_CONF_CHECK_I(name.y2); \ 5770 } while (0) 5771 5772 /* This is required for BDW+ where there is only one set of registers for 5773 * switching between high and low RR. 5774 * This macro can be used whenever a comparison has to be made between one 5775 * hw state and multiple sw state variables. 5776 */ 5777 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \ 5778 if (!intel_compare_link_m_n(¤t_config->name, \ 5779 &pipe_config->name, !fastset) && \ 5780 !intel_compare_link_m_n(¤t_config->alt_name, \ 5781 &pipe_config->name, !fastset)) { \ 5782 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5783 "(expected tu %i data %i/%i link %i/%i, " \ 5784 "or tu %i data %i/%i link %i/%i, " \ 5785 "found tu %i, data %i/%i link %i/%i)", \ 5786 current_config->name.tu, \ 5787 current_config->name.data_m, \ 5788 current_config->name.data_n, \ 5789 current_config->name.link_m, \ 5790 current_config->name.link_n, \ 5791 current_config->alt_name.tu, \ 5792 current_config->alt_name.data_m, \ 5793 current_config->alt_name.data_n, \ 5794 current_config->alt_name.link_m, \ 5795 current_config->alt_name.link_n, \ 5796 pipe_config->name.tu, \ 5797 pipe_config->name.data_m, \ 5798 pipe_config->name.data_n, \ 5799 pipe_config->name.link_m, \ 5800 pipe_config->name.link_n); \ 5801 ret = false; \ 5802 } \ 5803 } while (0) 5804 5805 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \ 5806 if ((current_config->name ^ pipe_config->name) & (mask)) { \ 5807 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5808 "(%x) (expected %i, found %i)", \ 5809 (mask), \ 5810 current_config->name & (mask), \ 5811 pipe_config->name & (mask)); \ 5812 ret = false; \ 5813 } \ 5814 } while (0) 5815 5816 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \ 5817 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ 5818 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5819 "(expected %i, found %i)", \ 5820 current_config->name, \ 5821 pipe_config->name); \ 5822 ret = false; \ 5823 } \ 5824 } while (0) 5825 5826 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \ 5827 if (!intel_compare_infoframe(¤t_config->infoframes.name, \ 5828 &pipe_config->infoframes.name)) { \ 5829 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \ 5830 ¤t_config->infoframes.name, \ 5831 &pipe_config->infoframes.name); \ 5832 ret = false; \ 5833 } \ 5834 } while (0) 5835 5836 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \ 5837 if (!current_config->has_psr && !pipe_config->has_psr && \ 5838 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \ 5839 &pipe_config->infoframes.name)) { \ 5840 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \ 5841 ¤t_config->infoframes.name, \ 5842 &pipe_config->infoframes.name); \ 5843 ret = false; \ 5844 } \ 5845 } while (0) 5846 5847 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \ 5848 if (current_config->name1 != pipe_config->name1) { \ 5849 pipe_config_mismatch(fastset, crtc, __stringify(name1), \ 5850 "(expected %i, found %i, won't compare lut values)", \ 5851 current_config->name1, \ 5852 pipe_config->name1); \ 5853 ret = false;\ 5854 } else { \ 5855 if (!intel_color_lut_equal(current_config->name2, \ 5856 pipe_config->name2, pipe_config->name1, \ 5857 bit_precision)) { \ 5858 pipe_config_mismatch(fastset, crtc, __stringify(name2), \ 5859 "hw_state doesn't match sw_state"); \ 5860 ret = false; \ 5861 } \ 5862 } \ 5863 } while (0) 5864 5865 #define PIPE_CONF_QUIRK(quirk) \ 5866 ((current_config->quirks | pipe_config->quirks) & (quirk)) 5867 5868 PIPE_CONF_CHECK_I(hw.enable); 5869 PIPE_CONF_CHECK_I(hw.active); 5870 5871 PIPE_CONF_CHECK_I(cpu_transcoder); 5872 PIPE_CONF_CHECK_I(mst_master_transcoder); 5873 5874 PIPE_CONF_CHECK_BOOL(has_pch_encoder); 5875 PIPE_CONF_CHECK_I(fdi_lanes); 5876 PIPE_CONF_CHECK_M_N(fdi_m_n); 5877 5878 PIPE_CONF_CHECK_I(lane_count); 5879 PIPE_CONF_CHECK_X(lane_lat_optim_mask); 5880 5881 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) { 5882 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); 5883 } else { 5884 PIPE_CONF_CHECK_M_N(dp_m_n); 5885 PIPE_CONF_CHECK_M_N(dp_m2_n2); 5886 } 5887 5888 PIPE_CONF_CHECK_X(output_types); 5889 5890 PIPE_CONF_CHECK_I(framestart_delay); 5891 PIPE_CONF_CHECK_I(msa_timing_delay); 5892 5893 PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode); 5894 PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode); 5895 5896 PIPE_CONF_CHECK_I(pixel_multiplier); 5897 5898 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5899 DRM_MODE_FLAG_INTERLACE); 5900 5901 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { 5902 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5903 DRM_MODE_FLAG_PHSYNC); 5904 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5905 DRM_MODE_FLAG_NHSYNC); 5906 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5907 DRM_MODE_FLAG_PVSYNC); 5908 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5909 DRM_MODE_FLAG_NVSYNC); 5910 } 5911 5912 PIPE_CONF_CHECK_I(output_format); 5913 PIPE_CONF_CHECK_BOOL(has_hdmi_sink); 5914 if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || 5915 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5916 PIPE_CONF_CHECK_BOOL(limited_color_range); 5917 5918 PIPE_CONF_CHECK_BOOL(hdmi_scrambling); 5919 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio); 5920 PIPE_CONF_CHECK_BOOL(has_infoframe); 5921 PIPE_CONF_CHECK_BOOL(fec_enable); 5922 5923 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio); 5924 5925 PIPE_CONF_CHECK_X(gmch_pfit.control); 5926 /* pfit ratios are autocomputed by the hw on gen4+ */ 5927 if (DISPLAY_VER(dev_priv) < 4) 5928 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); 5929 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); 5930 5931 /* 5932 * Changing the EDP transcoder input mux 5933 * (A_ONOFF vs. A_ON) requires a full modeset. 5934 */ 5935 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru); 5936 5937 if (!fastset) { 5938 PIPE_CONF_CHECK_RECT(pipe_src); 5939 5940 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled); 5941 PIPE_CONF_CHECK_RECT(pch_pfit.dst); 5942 5943 PIPE_CONF_CHECK_I(scaler_state.scaler_id); 5944 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate); 5945 5946 PIPE_CONF_CHECK_X(gamma_mode); 5947 if (IS_CHERRYVIEW(dev_priv)) 5948 PIPE_CONF_CHECK_X(cgm_mode); 5949 else 5950 PIPE_CONF_CHECK_X(csc_mode); 5951 PIPE_CONF_CHECK_BOOL(gamma_enable); 5952 PIPE_CONF_CHECK_BOOL(csc_enable); 5953 5954 PIPE_CONF_CHECK_I(linetime); 5955 PIPE_CONF_CHECK_I(ips_linetime); 5956 5957 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config); 5958 if (bp_gamma) 5959 PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma); 5960 5961 if (current_config->active_planes) { 5962 PIPE_CONF_CHECK_BOOL(has_psr); 5963 PIPE_CONF_CHECK_BOOL(has_psr2); 5964 PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); 5965 PIPE_CONF_CHECK_I(dc3co_exitline); 5966 } 5967 } 5968 5969 PIPE_CONF_CHECK_BOOL(double_wide); 5970 5971 if (dev_priv->dpll.mgr) { 5972 PIPE_CONF_CHECK_P(shared_dpll); 5973 5974 PIPE_CONF_CHECK_X(dpll_hw_state.dpll); 5975 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); 5976 PIPE_CONF_CHECK_X(dpll_hw_state.fp0); 5977 PIPE_CONF_CHECK_X(dpll_hw_state.fp1); 5978 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); 5979 PIPE_CONF_CHECK_X(dpll_hw_state.spll); 5980 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); 5981 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); 5982 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); 5983 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); 5984 PIPE_CONF_CHECK_X(dpll_hw_state.div0); 5985 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); 5986 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); 5987 PIPE_CONF_CHECK_X(dpll_hw_state.pll0); 5988 PIPE_CONF_CHECK_X(dpll_hw_state.pll1); 5989 PIPE_CONF_CHECK_X(dpll_hw_state.pll2); 5990 PIPE_CONF_CHECK_X(dpll_hw_state.pll3); 5991 PIPE_CONF_CHECK_X(dpll_hw_state.pll6); 5992 PIPE_CONF_CHECK_X(dpll_hw_state.pll8); 5993 PIPE_CONF_CHECK_X(dpll_hw_state.pll9); 5994 PIPE_CONF_CHECK_X(dpll_hw_state.pll10); 5995 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); 5996 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl); 5997 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1); 5998 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl); 5999 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0); 6000 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1); 6001 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf); 6002 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock); 6003 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc); 6004 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias); 6005 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias); 6006 } 6007 6008 PIPE_CONF_CHECK_X(dsi_pll.ctrl); 6009 PIPE_CONF_CHECK_X(dsi_pll.div); 6010 6011 if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5) 6012 PIPE_CONF_CHECK_I(pipe_bpp); 6013 6014 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock); 6015 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock); 6016 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); 6017 6018 PIPE_CONF_CHECK_I(min_voltage_level); 6019 6020 if (current_config->has_psr || pipe_config->has_psr) 6021 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable, 6022 ~intel_hdmi_infoframe_enable(DP_SDP_VSC)); 6023 else 6024 PIPE_CONF_CHECK_X(infoframes.enable); 6025 6026 PIPE_CONF_CHECK_X(infoframes.gcp); 6027 PIPE_CONF_CHECK_INFOFRAME(avi); 6028 PIPE_CONF_CHECK_INFOFRAME(spd); 6029 PIPE_CONF_CHECK_INFOFRAME(hdmi); 6030 PIPE_CONF_CHECK_INFOFRAME(drm); 6031 PIPE_CONF_CHECK_DP_VSC_SDP(vsc); 6032 6033 PIPE_CONF_CHECK_X(sync_mode_slaves_mask); 6034 PIPE_CONF_CHECK_I(master_transcoder); 6035 PIPE_CONF_CHECK_X(bigjoiner_pipes); 6036 6037 PIPE_CONF_CHECK_I(dsc.compression_enable); 6038 PIPE_CONF_CHECK_I(dsc.dsc_split); 6039 PIPE_CONF_CHECK_I(dsc.compressed_bpp); 6040 6041 PIPE_CONF_CHECK_BOOL(splitter.enable); 6042 PIPE_CONF_CHECK_I(splitter.link_count); 6043 PIPE_CONF_CHECK_I(splitter.pixel_overlap); 6044 6045 PIPE_CONF_CHECK_BOOL(vrr.enable); 6046 PIPE_CONF_CHECK_I(vrr.vmin); 6047 PIPE_CONF_CHECK_I(vrr.vmax); 6048 PIPE_CONF_CHECK_I(vrr.flipline); 6049 PIPE_CONF_CHECK_I(vrr.pipeline_full); 6050 PIPE_CONF_CHECK_I(vrr.guardband); 6051 6052 #undef PIPE_CONF_CHECK_X 6053 #undef PIPE_CONF_CHECK_I 6054 #undef PIPE_CONF_CHECK_BOOL 6055 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE 6056 #undef PIPE_CONF_CHECK_P 6057 #undef PIPE_CONF_CHECK_FLAGS 6058 #undef PIPE_CONF_CHECK_CLOCK_FUZZY 6059 #undef PIPE_CONF_CHECK_COLOR_LUT 6060 #undef PIPE_CONF_CHECK_TIMINGS 6061 #undef PIPE_CONF_CHECK_RECT 6062 #undef PIPE_CONF_QUIRK 6063 6064 return ret; 6065 } 6066 6067 static void 6068 intel_verify_planes(struct intel_atomic_state *state) 6069 { 6070 struct intel_plane *plane; 6071 const struct intel_plane_state *plane_state; 6072 int i; 6073 6074 for_each_new_intel_plane_in_state(state, plane, 6075 plane_state, i) 6076 assert_plane(plane, plane_state->planar_slave || 6077 plane_state->uapi.visible); 6078 } 6079 6080 int intel_modeset_all_pipes(struct intel_atomic_state *state) 6081 { 6082 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6083 struct intel_crtc *crtc; 6084 6085 /* 6086 * Add all pipes to the state, and force 6087 * a modeset on all the active ones. 6088 */ 6089 for_each_intel_crtc(&dev_priv->drm, crtc) { 6090 struct intel_crtc_state *crtc_state; 6091 int ret; 6092 6093 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6094 if (IS_ERR(crtc_state)) 6095 return PTR_ERR(crtc_state); 6096 6097 if (!crtc_state->hw.active || 6098 drm_atomic_crtc_needs_modeset(&crtc_state->uapi)) 6099 continue; 6100 6101 crtc_state->uapi.mode_changed = true; 6102 6103 ret = drm_atomic_add_affected_connectors(&state->base, 6104 &crtc->base); 6105 if (ret) 6106 return ret; 6107 6108 ret = intel_atomic_add_affected_planes(state, crtc); 6109 if (ret) 6110 return ret; 6111 6112 crtc_state->update_planes |= crtc_state->active_planes; 6113 } 6114 6115 return 0; 6116 } 6117 6118 static void 6119 intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state) 6120 { 6121 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 6122 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6123 struct drm_display_mode adjusted_mode; 6124 6125 drm_mode_init(&adjusted_mode, &crtc_state->hw.adjusted_mode); 6126 6127 if (crtc_state->vrr.enable) { 6128 adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax; 6129 adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax; 6130 adjusted_mode.crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state); 6131 crtc->vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state); 6132 } 6133 6134 drm_calc_timestamping_constants(&crtc->base, &adjusted_mode); 6135 6136 crtc->mode_flags = crtc_state->mode_flags; 6137 6138 /* 6139 * The scanline counter increments at the leading edge of hsync. 6140 * 6141 * On most platforms it starts counting from vtotal-1 on the 6142 * first active line. That means the scanline counter value is 6143 * always one less than what we would expect. Ie. just after 6144 * start of vblank, which also occurs at start of hsync (on the 6145 * last active line), the scanline counter will read vblank_start-1. 6146 * 6147 * On gen2 the scanline counter starts counting from 1 instead 6148 * of vtotal-1, so we have to subtract one (or rather add vtotal-1 6149 * to keep the value positive), instead of adding one. 6150 * 6151 * On HSW+ the behaviour of the scanline counter depends on the output 6152 * type. For DP ports it behaves like most other platforms, but on HDMI 6153 * there's an extra 1 line difference. So we need to add two instead of 6154 * one to the value. 6155 * 6156 * On VLV/CHV DSI the scanline counter would appear to increment 6157 * approx. 1/3 of a scanline before start of vblank. Unfortunately 6158 * that means we can't tell whether we're in vblank or not while 6159 * we're on that particular line. We must still set scanline_offset 6160 * to 1 so that the vblank timestamps come out correct when we query 6161 * the scanline counter from within the vblank interrupt handler. 6162 * However if queried just before the start of vblank we'll get an 6163 * answer that's slightly in the future. 6164 */ 6165 if (DISPLAY_VER(dev_priv) == 2) { 6166 int vtotal; 6167 6168 vtotal = adjusted_mode.crtc_vtotal; 6169 if (adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 6170 vtotal /= 2; 6171 6172 crtc->scanline_offset = vtotal - 1; 6173 } else if (HAS_DDI(dev_priv) && 6174 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 6175 crtc->scanline_offset = 2; 6176 } else { 6177 crtc->scanline_offset = 1; 6178 } 6179 } 6180 6181 static void intel_modeset_clear_plls(struct intel_atomic_state *state) 6182 { 6183 struct intel_crtc_state *new_crtc_state; 6184 struct intel_crtc *crtc; 6185 int i; 6186 6187 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6188 if (!intel_crtc_needs_modeset(new_crtc_state)) 6189 continue; 6190 6191 intel_release_shared_dplls(state, crtc); 6192 } 6193 } 6194 6195 /* 6196 * This implements the workaround described in the "notes" section of the mode 6197 * set sequence documentation. When going from no pipes or single pipe to 6198 * multiple pipes, and planes are enabled after the pipe, we need to wait at 6199 * least 2 vblanks on the first pipe before enabling planes on the second pipe. 6200 */ 6201 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state) 6202 { 6203 struct intel_crtc_state *crtc_state; 6204 struct intel_crtc *crtc; 6205 struct intel_crtc_state *first_crtc_state = NULL; 6206 struct intel_crtc_state *other_crtc_state = NULL; 6207 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; 6208 int i; 6209 6210 /* look at all crtc's that are going to be enabled in during modeset */ 6211 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6212 if (!crtc_state->hw.active || 6213 !intel_crtc_needs_modeset(crtc_state)) 6214 continue; 6215 6216 if (first_crtc_state) { 6217 other_crtc_state = crtc_state; 6218 break; 6219 } else { 6220 first_crtc_state = crtc_state; 6221 first_pipe = crtc->pipe; 6222 } 6223 } 6224 6225 /* No workaround needed? */ 6226 if (!first_crtc_state) 6227 return 0; 6228 6229 /* w/a possibly needed, check how many crtc's are already enabled. */ 6230 for_each_intel_crtc(state->base.dev, crtc) { 6231 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6232 if (IS_ERR(crtc_state)) 6233 return PTR_ERR(crtc_state); 6234 6235 crtc_state->hsw_workaround_pipe = INVALID_PIPE; 6236 6237 if (!crtc_state->hw.active || 6238 intel_crtc_needs_modeset(crtc_state)) 6239 continue; 6240 6241 /* 2 or more enabled crtcs means no need for w/a */ 6242 if (enabled_pipe != INVALID_PIPE) 6243 return 0; 6244 6245 enabled_pipe = crtc->pipe; 6246 } 6247 6248 if (enabled_pipe != INVALID_PIPE) 6249 first_crtc_state->hsw_workaround_pipe = enabled_pipe; 6250 else if (other_crtc_state) 6251 other_crtc_state->hsw_workaround_pipe = first_pipe; 6252 6253 return 0; 6254 } 6255 6256 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 6257 u8 active_pipes) 6258 { 6259 const struct intel_crtc_state *crtc_state; 6260 struct intel_crtc *crtc; 6261 int i; 6262 6263 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6264 if (crtc_state->hw.active) 6265 active_pipes |= BIT(crtc->pipe); 6266 else 6267 active_pipes &= ~BIT(crtc->pipe); 6268 } 6269 6270 return active_pipes; 6271 } 6272 6273 static int intel_modeset_checks(struct intel_atomic_state *state) 6274 { 6275 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6276 6277 state->modeset = true; 6278 6279 if (IS_HASWELL(dev_priv)) 6280 return hsw_mode_set_planes_workaround(state); 6281 6282 return 0; 6283 } 6284 6285 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state, 6286 struct intel_crtc_state *new_crtc_state) 6287 { 6288 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) 6289 return; 6290 6291 new_crtc_state->uapi.mode_changed = false; 6292 new_crtc_state->update_pipe = true; 6293 } 6294 6295 static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state, 6296 struct intel_crtc_state *new_crtc_state) 6297 { 6298 /* 6299 * If we're not doing the full modeset we want to 6300 * keep the current M/N values as they may be 6301 * sufficiently different to the computed values 6302 * to cause problems. 6303 * 6304 * FIXME: should really copy more fuzzy state here 6305 */ 6306 new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n; 6307 new_crtc_state->dp_m_n = old_crtc_state->dp_m_n; 6308 new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2; 6309 new_crtc_state->has_drrs = old_crtc_state->has_drrs; 6310 } 6311 6312 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state, 6313 struct intel_crtc *crtc, 6314 u8 plane_ids_mask) 6315 { 6316 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6317 struct intel_plane *plane; 6318 6319 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 6320 struct intel_plane_state *plane_state; 6321 6322 if ((plane_ids_mask & BIT(plane->id)) == 0) 6323 continue; 6324 6325 plane_state = intel_atomic_get_plane_state(state, plane); 6326 if (IS_ERR(plane_state)) 6327 return PTR_ERR(plane_state); 6328 } 6329 6330 return 0; 6331 } 6332 6333 int intel_atomic_add_affected_planes(struct intel_atomic_state *state, 6334 struct intel_crtc *crtc) 6335 { 6336 const struct intel_crtc_state *old_crtc_state = 6337 intel_atomic_get_old_crtc_state(state, crtc); 6338 const struct intel_crtc_state *new_crtc_state = 6339 intel_atomic_get_new_crtc_state(state, crtc); 6340 6341 return intel_crtc_add_planes_to_state(state, crtc, 6342 old_crtc_state->enabled_planes | 6343 new_crtc_state->enabled_planes); 6344 } 6345 6346 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv) 6347 { 6348 /* See {hsw,vlv,ivb}_plane_ratio() */ 6349 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) || 6350 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) || 6351 IS_IVYBRIDGE(dev_priv); 6352 } 6353 6354 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state, 6355 struct intel_crtc *crtc, 6356 struct intel_crtc *other) 6357 { 6358 const struct intel_plane_state *plane_state; 6359 struct intel_plane *plane; 6360 u8 plane_ids = 0; 6361 int i; 6362 6363 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 6364 if (plane->pipe == crtc->pipe) 6365 plane_ids |= BIT(plane->id); 6366 } 6367 6368 return intel_crtc_add_planes_to_state(state, other, plane_ids); 6369 } 6370 6371 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state) 6372 { 6373 struct drm_i915_private *i915 = to_i915(state->base.dev); 6374 const struct intel_crtc_state *crtc_state; 6375 struct intel_crtc *crtc; 6376 int i; 6377 6378 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6379 struct intel_crtc *other; 6380 6381 for_each_intel_crtc_in_pipe_mask(&i915->drm, other, 6382 crtc_state->bigjoiner_pipes) { 6383 int ret; 6384 6385 if (crtc == other) 6386 continue; 6387 6388 ret = intel_crtc_add_bigjoiner_planes(state, crtc, other); 6389 if (ret) 6390 return ret; 6391 } 6392 } 6393 6394 return 0; 6395 } 6396 6397 static int intel_atomic_check_planes(struct intel_atomic_state *state) 6398 { 6399 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6400 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6401 struct intel_plane_state *plane_state; 6402 struct intel_plane *plane; 6403 struct intel_crtc *crtc; 6404 int i, ret; 6405 6406 ret = icl_add_linked_planes(state); 6407 if (ret) 6408 return ret; 6409 6410 ret = intel_bigjoiner_add_affected_planes(state); 6411 if (ret) 6412 return ret; 6413 6414 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 6415 ret = intel_plane_atomic_check(state, plane); 6416 if (ret) { 6417 drm_dbg_atomic(&dev_priv->drm, 6418 "[PLANE:%d:%s] atomic driver check failed\n", 6419 plane->base.base.id, plane->base.name); 6420 return ret; 6421 } 6422 } 6423 6424 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6425 new_crtc_state, i) { 6426 u8 old_active_planes, new_active_planes; 6427 6428 ret = icl_check_nv12_planes(new_crtc_state); 6429 if (ret) 6430 return ret; 6431 6432 /* 6433 * On some platforms the number of active planes affects 6434 * the planes' minimum cdclk calculation. Add such planes 6435 * to the state before we compute the minimum cdclk. 6436 */ 6437 if (!active_planes_affects_min_cdclk(dev_priv)) 6438 continue; 6439 6440 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 6441 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 6442 6443 if (hweight8(old_active_planes) == hweight8(new_active_planes)) 6444 continue; 6445 6446 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes); 6447 if (ret) 6448 return ret; 6449 } 6450 6451 return 0; 6452 } 6453 6454 static int intel_atomic_check_crtcs(struct intel_atomic_state *state) 6455 { 6456 struct intel_crtc_state *crtc_state; 6457 struct intel_crtc *crtc; 6458 int i; 6459 6460 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6461 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 6462 int ret; 6463 6464 ret = intel_crtc_atomic_check(state, crtc); 6465 if (ret) { 6466 drm_dbg_atomic(&i915->drm, 6467 "[CRTC:%d:%s] atomic driver check failed\n", 6468 crtc->base.base.id, crtc->base.name); 6469 return ret; 6470 } 6471 } 6472 6473 return 0; 6474 } 6475 6476 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, 6477 u8 transcoders) 6478 { 6479 const struct intel_crtc_state *new_crtc_state; 6480 struct intel_crtc *crtc; 6481 int i; 6482 6483 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6484 if (new_crtc_state->hw.enable && 6485 transcoders & BIT(new_crtc_state->cpu_transcoder) && 6486 intel_crtc_needs_modeset(new_crtc_state)) 6487 return true; 6488 } 6489 6490 return false; 6491 } 6492 6493 static bool intel_pipes_need_modeset(struct intel_atomic_state *state, 6494 u8 pipes) 6495 { 6496 const struct intel_crtc_state *new_crtc_state; 6497 struct intel_crtc *crtc; 6498 int i; 6499 6500 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6501 if (new_crtc_state->hw.enable && 6502 pipes & BIT(crtc->pipe) && 6503 intel_crtc_needs_modeset(new_crtc_state)) 6504 return true; 6505 } 6506 6507 return false; 6508 } 6509 6510 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state, 6511 struct intel_crtc *master_crtc) 6512 { 6513 struct drm_i915_private *i915 = to_i915(state->base.dev); 6514 struct intel_crtc_state *master_crtc_state = 6515 intel_atomic_get_new_crtc_state(state, master_crtc); 6516 struct intel_crtc *slave_crtc; 6517 6518 if (!master_crtc_state->bigjoiner_pipes) 6519 return 0; 6520 6521 /* sanity check */ 6522 if (drm_WARN_ON(&i915->drm, 6523 master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state))) 6524 return -EINVAL; 6525 6526 if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) { 6527 drm_dbg_kms(&i915->drm, 6528 "[CRTC:%d:%s] Cannot act as big joiner master " 6529 "(need 0x%x as pipes, only 0x%x possible)\n", 6530 master_crtc->base.base.id, master_crtc->base.name, 6531 master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915)); 6532 return -EINVAL; 6533 } 6534 6535 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 6536 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 6537 struct intel_crtc_state *slave_crtc_state; 6538 int ret; 6539 6540 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc); 6541 if (IS_ERR(slave_crtc_state)) 6542 return PTR_ERR(slave_crtc_state); 6543 6544 /* master being enabled, slave was already configured? */ 6545 if (slave_crtc_state->uapi.enable) { 6546 drm_dbg_kms(&i915->drm, 6547 "[CRTC:%d:%s] Slave is enabled as normal CRTC, but " 6548 "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n", 6549 slave_crtc->base.base.id, slave_crtc->base.name, 6550 master_crtc->base.base.id, master_crtc->base.name); 6551 return -EINVAL; 6552 } 6553 6554 /* 6555 * The state copy logic assumes the master crtc gets processed 6556 * before the slave crtc during the main compute_config loop. 6557 * This works because the crtcs are created in pipe order, 6558 * and the hardware requires master pipe < slave pipe as well. 6559 * Should that change we need to rethink the logic. 6560 */ 6561 if (WARN_ON(drm_crtc_index(&master_crtc->base) > 6562 drm_crtc_index(&slave_crtc->base))) 6563 return -EINVAL; 6564 6565 drm_dbg_kms(&i915->drm, 6566 "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n", 6567 slave_crtc->base.base.id, slave_crtc->base.name, 6568 master_crtc->base.base.id, master_crtc->base.name); 6569 6570 slave_crtc_state->bigjoiner_pipes = 6571 master_crtc_state->bigjoiner_pipes; 6572 6573 ret = copy_bigjoiner_crtc_state_modeset(state, slave_crtc); 6574 if (ret) 6575 return ret; 6576 } 6577 6578 return 0; 6579 } 6580 6581 static void kill_bigjoiner_slave(struct intel_atomic_state *state, 6582 struct intel_crtc *master_crtc) 6583 { 6584 struct drm_i915_private *i915 = to_i915(state->base.dev); 6585 struct intel_crtc_state *master_crtc_state = 6586 intel_atomic_get_new_crtc_state(state, master_crtc); 6587 struct intel_crtc *slave_crtc; 6588 6589 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 6590 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 6591 struct intel_crtc_state *slave_crtc_state = 6592 intel_atomic_get_new_crtc_state(state, slave_crtc); 6593 6594 slave_crtc_state->bigjoiner_pipes = 0; 6595 6596 intel_crtc_copy_uapi_to_hw_state_modeset(state, slave_crtc); 6597 } 6598 6599 master_crtc_state->bigjoiner_pipes = 0; 6600 } 6601 6602 /** 6603 * DOC: asynchronous flip implementation 6604 * 6605 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC 6606 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL. 6607 * Correspondingly, support is currently added for primary plane only. 6608 * 6609 * Async flip can only change the plane surface address, so anything else 6610 * changing is rejected from the intel_async_flip_check_hw() function. 6611 * Once this check is cleared, flip done interrupt is enabled using 6612 * the intel_crtc_enable_flip_done() function. 6613 * 6614 * As soon as the surface address register is written, flip done interrupt is 6615 * generated and the requested events are sent to the usersapce in the interrupt 6616 * handler itself. The timestamp and sequence sent during the flip done event 6617 * correspond to the last vblank and have no relation to the actual time when 6618 * the flip done event was sent. 6619 */ 6620 static int intel_async_flip_check_uapi(struct intel_atomic_state *state, 6621 struct intel_crtc *crtc) 6622 { 6623 struct drm_i915_private *i915 = to_i915(state->base.dev); 6624 const struct intel_crtc_state *new_crtc_state = 6625 intel_atomic_get_new_crtc_state(state, crtc); 6626 const struct intel_plane_state *old_plane_state; 6627 struct intel_plane_state *new_plane_state; 6628 struct intel_plane *plane; 6629 int i; 6630 6631 if (!new_crtc_state->uapi.async_flip) 6632 return 0; 6633 6634 if (!new_crtc_state->uapi.active) { 6635 drm_dbg_kms(&i915->drm, 6636 "[CRTC:%d:%s] not active\n", 6637 crtc->base.base.id, crtc->base.name); 6638 return -EINVAL; 6639 } 6640 6641 if (intel_crtc_needs_modeset(new_crtc_state)) { 6642 drm_dbg_kms(&i915->drm, 6643 "[CRTC:%d:%s] modeset required\n", 6644 crtc->base.base.id, crtc->base.name); 6645 return -EINVAL; 6646 } 6647 6648 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 6649 new_plane_state, i) { 6650 if (plane->pipe != crtc->pipe) 6651 continue; 6652 6653 /* 6654 * TODO: Async flip is only supported through the page flip IOCTL 6655 * as of now. So support currently added for primary plane only. 6656 * Support for other planes on platforms on which supports 6657 * this(vlv/chv and icl+) should be added when async flip is 6658 * enabled in the atomic IOCTL path. 6659 */ 6660 if (!plane->async_flip) { 6661 drm_dbg_kms(&i915->drm, 6662 "[PLANE:%d:%s] async flip not supported\n", 6663 plane->base.base.id, plane->base.name); 6664 return -EINVAL; 6665 } 6666 6667 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) { 6668 drm_dbg_kms(&i915->drm, 6669 "[PLANE:%d:%s] no old or new framebuffer\n", 6670 plane->base.base.id, plane->base.name); 6671 return -EINVAL; 6672 } 6673 } 6674 6675 return 0; 6676 } 6677 6678 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc) 6679 { 6680 struct drm_i915_private *i915 = to_i915(state->base.dev); 6681 const struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6682 const struct intel_plane_state *new_plane_state, *old_plane_state; 6683 struct intel_plane *plane; 6684 int i; 6685 6686 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 6687 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6688 6689 if (!new_crtc_state->uapi.async_flip) 6690 return 0; 6691 6692 if (!new_crtc_state->hw.active) { 6693 drm_dbg_kms(&i915->drm, 6694 "[CRTC:%d:%s] not active\n", 6695 crtc->base.base.id, crtc->base.name); 6696 return -EINVAL; 6697 } 6698 6699 if (intel_crtc_needs_modeset(new_crtc_state)) { 6700 drm_dbg_kms(&i915->drm, 6701 "[CRTC:%d:%s] modeset required\n", 6702 crtc->base.base.id, crtc->base.name); 6703 return -EINVAL; 6704 } 6705 6706 if (old_crtc_state->active_planes != new_crtc_state->active_planes) { 6707 drm_dbg_kms(&i915->drm, 6708 "[CRTC:%d:%s] Active planes cannot be in async flip\n", 6709 crtc->base.base.id, crtc->base.name); 6710 return -EINVAL; 6711 } 6712 6713 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 6714 new_plane_state, i) { 6715 if (plane->pipe != crtc->pipe) 6716 continue; 6717 6718 /* 6719 * Only async flip capable planes should be in the state 6720 * if we're really about to ask the hardware to perform 6721 * an async flip. We should never get this far otherwise. 6722 */ 6723 if (drm_WARN_ON(&i915->drm, 6724 new_crtc_state->do_async_flip && !plane->async_flip)) 6725 return -EINVAL; 6726 6727 /* 6728 * Only check async flip capable planes other planes 6729 * may be involved in the initial commit due to 6730 * the wm0/ddb optimization. 6731 * 6732 * TODO maybe should track which planes actually 6733 * were requested to do the async flip... 6734 */ 6735 if (!plane->async_flip) 6736 continue; 6737 6738 /* 6739 * FIXME: This check is kept generic for all platforms. 6740 * Need to verify this for all gen9 platforms to enable 6741 * this selectively if required. 6742 */ 6743 switch (new_plane_state->hw.fb->modifier) { 6744 case I915_FORMAT_MOD_X_TILED: 6745 case I915_FORMAT_MOD_Y_TILED: 6746 case I915_FORMAT_MOD_Yf_TILED: 6747 case I915_FORMAT_MOD_4_TILED: 6748 break; 6749 default: 6750 drm_dbg_kms(&i915->drm, 6751 "[PLANE:%d:%s] Modifier does not support async flips\n", 6752 plane->base.base.id, plane->base.name); 6753 return -EINVAL; 6754 } 6755 6756 if (new_plane_state->hw.fb->format->num_planes > 1) { 6757 drm_dbg_kms(&i915->drm, 6758 "[PLANE:%d:%s] Planar formats do not support async flips\n", 6759 plane->base.base.id, plane->base.name); 6760 return -EINVAL; 6761 } 6762 6763 if (old_plane_state->view.color_plane[0].mapping_stride != 6764 new_plane_state->view.color_plane[0].mapping_stride) { 6765 drm_dbg_kms(&i915->drm, 6766 "[PLANE:%d:%s] Stride cannot be changed in async flip\n", 6767 plane->base.base.id, plane->base.name); 6768 return -EINVAL; 6769 } 6770 6771 if (old_plane_state->hw.fb->modifier != 6772 new_plane_state->hw.fb->modifier) { 6773 drm_dbg_kms(&i915->drm, 6774 "[PLANE:%d:%s] Modifier cannot be changed in async flip\n", 6775 plane->base.base.id, plane->base.name); 6776 return -EINVAL; 6777 } 6778 6779 if (old_plane_state->hw.fb->format != 6780 new_plane_state->hw.fb->format) { 6781 drm_dbg_kms(&i915->drm, 6782 "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n", 6783 plane->base.base.id, plane->base.name); 6784 return -EINVAL; 6785 } 6786 6787 if (old_plane_state->hw.rotation != 6788 new_plane_state->hw.rotation) { 6789 drm_dbg_kms(&i915->drm, 6790 "[PLANE:%d:%s] Rotation cannot be changed in async flip\n", 6791 plane->base.base.id, plane->base.name); 6792 return -EINVAL; 6793 } 6794 6795 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) || 6796 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) { 6797 drm_dbg_kms(&i915->drm, 6798 "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n", 6799 plane->base.base.id, plane->base.name); 6800 return -EINVAL; 6801 } 6802 6803 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) { 6804 drm_dbg_kms(&i915->drm, 6805 "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n", 6806 plane->base.base.id, plane->base.name); 6807 return -EINVAL; 6808 } 6809 6810 if (old_plane_state->hw.pixel_blend_mode != 6811 new_plane_state->hw.pixel_blend_mode) { 6812 drm_dbg_kms(&i915->drm, 6813 "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n", 6814 plane->base.base.id, plane->base.name); 6815 return -EINVAL; 6816 } 6817 6818 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) { 6819 drm_dbg_kms(&i915->drm, 6820 "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n", 6821 plane->base.base.id, plane->base.name); 6822 return -EINVAL; 6823 } 6824 6825 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) { 6826 drm_dbg_kms(&i915->drm, 6827 "[PLANE:%d:%s] Color range cannot be changed in async flip\n", 6828 plane->base.base.id, plane->base.name); 6829 return -EINVAL; 6830 } 6831 6832 /* plane decryption is allow to change only in synchronous flips */ 6833 if (old_plane_state->decrypt != new_plane_state->decrypt) { 6834 drm_dbg_kms(&i915->drm, 6835 "[PLANE:%d:%s] Decryption cannot be changed in async flip\n", 6836 plane->base.base.id, plane->base.name); 6837 return -EINVAL; 6838 } 6839 } 6840 6841 return 0; 6842 } 6843 6844 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state) 6845 { 6846 struct drm_i915_private *i915 = to_i915(state->base.dev); 6847 struct intel_crtc_state *crtc_state; 6848 struct intel_crtc *crtc; 6849 u8 affected_pipes = 0; 6850 u8 modeset_pipes = 0; 6851 int i; 6852 6853 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6854 affected_pipes |= crtc_state->bigjoiner_pipes; 6855 if (intel_crtc_needs_modeset(crtc_state)) 6856 modeset_pipes |= crtc_state->bigjoiner_pipes; 6857 } 6858 6859 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) { 6860 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6861 if (IS_ERR(crtc_state)) 6862 return PTR_ERR(crtc_state); 6863 } 6864 6865 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) { 6866 int ret; 6867 6868 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6869 6870 crtc_state->uapi.mode_changed = true; 6871 6872 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); 6873 if (ret) 6874 return ret; 6875 6876 ret = intel_atomic_add_affected_planes(state, crtc); 6877 if (ret) 6878 return ret; 6879 } 6880 6881 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6882 /* Kill old bigjoiner link, we may re-establish afterwards */ 6883 if (intel_crtc_needs_modeset(crtc_state) && 6884 intel_crtc_is_bigjoiner_master(crtc_state)) 6885 kill_bigjoiner_slave(state, crtc); 6886 } 6887 6888 return 0; 6889 } 6890 6891 /** 6892 * intel_atomic_check - validate state object 6893 * @dev: drm device 6894 * @_state: state to validate 6895 */ 6896 static int intel_atomic_check(struct drm_device *dev, 6897 struct drm_atomic_state *_state) 6898 { 6899 struct drm_i915_private *dev_priv = to_i915(dev); 6900 struct intel_atomic_state *state = to_intel_atomic_state(_state); 6901 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6902 struct intel_crtc *crtc; 6903 int ret, i; 6904 bool any_ms = false; 6905 6906 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6907 new_crtc_state, i) { 6908 if (new_crtc_state->inherited != old_crtc_state->inherited) 6909 new_crtc_state->uapi.mode_changed = true; 6910 6911 if (new_crtc_state->uapi.scaling_filter != 6912 old_crtc_state->uapi.scaling_filter) 6913 new_crtc_state->uapi.mode_changed = true; 6914 } 6915 6916 intel_vrr_check_modeset(state); 6917 6918 ret = drm_atomic_helper_check_modeset(dev, &state->base); 6919 if (ret) 6920 goto fail; 6921 6922 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6923 ret = intel_async_flip_check_uapi(state, crtc); 6924 if (ret) 6925 return ret; 6926 } 6927 6928 ret = intel_bigjoiner_add_affected_crtcs(state); 6929 if (ret) 6930 goto fail; 6931 6932 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6933 new_crtc_state, i) { 6934 if (!intel_crtc_needs_modeset(new_crtc_state)) { 6935 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 6936 copy_bigjoiner_crtc_state_nomodeset(state, crtc); 6937 else 6938 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 6939 continue; 6940 } 6941 6942 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) { 6943 drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable); 6944 continue; 6945 } 6946 6947 ret = intel_crtc_prepare_cleared_state(state, crtc); 6948 if (ret) 6949 goto fail; 6950 6951 if (!new_crtc_state->hw.enable) 6952 continue; 6953 6954 ret = intel_modeset_pipe_config(state, crtc); 6955 if (ret) 6956 goto fail; 6957 6958 ret = intel_atomic_check_bigjoiner(state, crtc); 6959 if (ret) 6960 goto fail; 6961 } 6962 6963 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6964 new_crtc_state, i) { 6965 if (!intel_crtc_needs_modeset(new_crtc_state)) 6966 continue; 6967 6968 ret = intel_modeset_pipe_config_late(state, crtc); 6969 if (ret) 6970 goto fail; 6971 6972 intel_crtc_check_fastset(old_crtc_state, new_crtc_state); 6973 } 6974 6975 /** 6976 * Check if fastset is allowed by external dependencies like other 6977 * pipes and transcoders. 6978 * 6979 * Right now it only forces a fullmodeset when the MST master 6980 * transcoder did not changed but the pipe of the master transcoder 6981 * needs a fullmodeset so all slaves also needs to do a fullmodeset or 6982 * in case of port synced crtcs, if one of the synced crtcs 6983 * needs a full modeset, all other synced crtcs should be 6984 * forced a full modeset. 6985 */ 6986 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6987 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state)) 6988 continue; 6989 6990 if (intel_dp_mst_is_slave_trans(new_crtc_state)) { 6991 enum transcoder master = new_crtc_state->mst_master_transcoder; 6992 6993 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) { 6994 new_crtc_state->uapi.mode_changed = true; 6995 new_crtc_state->update_pipe = false; 6996 } 6997 } 6998 6999 if (is_trans_port_sync_mode(new_crtc_state)) { 7000 u8 trans = new_crtc_state->sync_mode_slaves_mask; 7001 7002 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER) 7003 trans |= BIT(new_crtc_state->master_transcoder); 7004 7005 if (intel_cpu_transcoders_need_modeset(state, trans)) { 7006 new_crtc_state->uapi.mode_changed = true; 7007 new_crtc_state->update_pipe = false; 7008 } 7009 } 7010 7011 if (new_crtc_state->bigjoiner_pipes) { 7012 if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) { 7013 new_crtc_state->uapi.mode_changed = true; 7014 new_crtc_state->update_pipe = false; 7015 } 7016 } 7017 } 7018 7019 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7020 new_crtc_state, i) { 7021 if (intel_crtc_needs_modeset(new_crtc_state)) { 7022 any_ms = true; 7023 continue; 7024 } 7025 7026 if (!new_crtc_state->update_pipe) 7027 continue; 7028 7029 intel_crtc_copy_fastset(old_crtc_state, new_crtc_state); 7030 } 7031 7032 if (any_ms && !check_digital_port_conflicts(state)) { 7033 drm_dbg_kms(&dev_priv->drm, 7034 "rejecting conflicting digital port configuration\n"); 7035 ret = -EINVAL; 7036 goto fail; 7037 } 7038 7039 ret = drm_dp_mst_atomic_check(&state->base); 7040 if (ret) 7041 goto fail; 7042 7043 ret = intel_atomic_check_planes(state); 7044 if (ret) 7045 goto fail; 7046 7047 ret = intel_compute_global_watermarks(state); 7048 if (ret) 7049 goto fail; 7050 7051 ret = intel_bw_atomic_check(state); 7052 if (ret) 7053 goto fail; 7054 7055 ret = intel_cdclk_atomic_check(state, &any_ms); 7056 if (ret) 7057 goto fail; 7058 7059 if (intel_any_crtc_needs_modeset(state)) 7060 any_ms = true; 7061 7062 if (any_ms) { 7063 ret = intel_modeset_checks(state); 7064 if (ret) 7065 goto fail; 7066 7067 ret = intel_modeset_calc_cdclk(state); 7068 if (ret) 7069 return ret; 7070 7071 intel_modeset_clear_plls(state); 7072 } 7073 7074 ret = intel_atomic_check_crtcs(state); 7075 if (ret) 7076 goto fail; 7077 7078 ret = intel_fbc_atomic_check(state); 7079 if (ret) 7080 goto fail; 7081 7082 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7083 new_crtc_state, i) { 7084 ret = intel_async_flip_check_hw(state, crtc); 7085 if (ret) 7086 goto fail; 7087 7088 if (!intel_crtc_needs_modeset(new_crtc_state) && 7089 !new_crtc_state->update_pipe) 7090 continue; 7091 7092 intel_crtc_state_dump(new_crtc_state, state, 7093 intel_crtc_needs_modeset(new_crtc_state) ? 7094 "modeset" : "fastset"); 7095 } 7096 7097 return 0; 7098 7099 fail: 7100 if (ret == -EDEADLK) 7101 return ret; 7102 7103 /* 7104 * FIXME would probably be nice to know which crtc specifically 7105 * caused the failure, in cases where we can pinpoint it. 7106 */ 7107 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7108 new_crtc_state, i) 7109 intel_crtc_state_dump(new_crtc_state, state, "failed"); 7110 7111 return ret; 7112 } 7113 7114 static int intel_atomic_prepare_commit(struct intel_atomic_state *state) 7115 { 7116 struct intel_crtc_state *crtc_state; 7117 struct intel_crtc *crtc; 7118 int i, ret; 7119 7120 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base); 7121 if (ret < 0) 7122 return ret; 7123 7124 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7125 bool mode_changed = intel_crtc_needs_modeset(crtc_state); 7126 7127 if (mode_changed || crtc_state->update_pipe || 7128 crtc_state->uapi.color_mgmt_changed) { 7129 intel_dsb_prepare(crtc_state); 7130 } 7131 } 7132 7133 return 0; 7134 } 7135 7136 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 7137 struct intel_crtc_state *crtc_state) 7138 { 7139 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 7140 7141 if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes) 7142 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 7143 7144 if (crtc_state->has_pch_encoder) { 7145 enum pipe pch_transcoder = 7146 intel_crtc_pch_transcoder(crtc); 7147 7148 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true); 7149 } 7150 } 7151 7152 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, 7153 const struct intel_crtc_state *new_crtc_state) 7154 { 7155 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 7156 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 7157 7158 /* 7159 * Update pipe size and adjust fitter if needed: the reason for this is 7160 * that in compute_mode_changes we check the native mode (not the pfit 7161 * mode) to see if we can flip rather than do a full mode set. In the 7162 * fastboot case, we'll flip, but if we don't update the pipesrc and 7163 * pfit state, we'll end up with a big fb scanned out into the wrong 7164 * sized surface. 7165 */ 7166 intel_set_pipe_src_size(new_crtc_state); 7167 7168 /* on skylake this is done by detaching scalers */ 7169 if (DISPLAY_VER(dev_priv) >= 9) { 7170 if (new_crtc_state->pch_pfit.enabled) 7171 skl_pfit_enable(new_crtc_state); 7172 } else if (HAS_PCH_SPLIT(dev_priv)) { 7173 if (new_crtc_state->pch_pfit.enabled) 7174 ilk_pfit_enable(new_crtc_state); 7175 else if (old_crtc_state->pch_pfit.enabled) 7176 ilk_pfit_disable(old_crtc_state); 7177 } 7178 7179 /* 7180 * The register is supposedly single buffered so perhaps 7181 * not 100% correct to do this here. But SKL+ calculate 7182 * this based on the adjust pixel rate so pfit changes do 7183 * affect it and so it must be updated for fastsets. 7184 * HSW/BDW only really need this here for fastboot, after 7185 * that the value should not change without a full modeset. 7186 */ 7187 if (DISPLAY_VER(dev_priv) >= 9 || 7188 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 7189 hsw_set_linetime_wm(new_crtc_state); 7190 } 7191 7192 static void commit_pipe_pre_planes(struct intel_atomic_state *state, 7193 struct intel_crtc *crtc) 7194 { 7195 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7196 const struct intel_crtc_state *old_crtc_state = 7197 intel_atomic_get_old_crtc_state(state, crtc); 7198 const struct intel_crtc_state *new_crtc_state = 7199 intel_atomic_get_new_crtc_state(state, crtc); 7200 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 7201 7202 /* 7203 * During modesets pipe configuration was programmed as the 7204 * CRTC was enabled. 7205 */ 7206 if (!modeset) { 7207 if (new_crtc_state->uapi.color_mgmt_changed || 7208 new_crtc_state->update_pipe) 7209 intel_color_commit_arm(new_crtc_state); 7210 7211 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 7212 bdw_set_pipemisc(new_crtc_state); 7213 7214 if (new_crtc_state->update_pipe) 7215 intel_pipe_fastset(old_crtc_state, new_crtc_state); 7216 } 7217 7218 intel_psr2_program_trans_man_trk_ctl(new_crtc_state); 7219 7220 intel_atomic_update_watermarks(state, crtc); 7221 } 7222 7223 static void commit_pipe_post_planes(struct intel_atomic_state *state, 7224 struct intel_crtc *crtc) 7225 { 7226 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7227 const struct intel_crtc_state *new_crtc_state = 7228 intel_atomic_get_new_crtc_state(state, crtc); 7229 7230 /* 7231 * Disable the scaler(s) after the plane(s) so that we don't 7232 * get a catastrophic underrun even if the two operations 7233 * end up happening in two different frames. 7234 */ 7235 if (DISPLAY_VER(dev_priv) >= 9 && 7236 !intel_crtc_needs_modeset(new_crtc_state)) 7237 skl_detach_scalers(new_crtc_state); 7238 } 7239 7240 static void intel_enable_crtc(struct intel_atomic_state *state, 7241 struct intel_crtc *crtc) 7242 { 7243 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7244 const struct intel_crtc_state *new_crtc_state = 7245 intel_atomic_get_new_crtc_state(state, crtc); 7246 7247 if (!intel_crtc_needs_modeset(new_crtc_state)) 7248 return; 7249 7250 intel_crtc_update_active_timings(new_crtc_state); 7251 7252 dev_priv->display->crtc_enable(state, crtc); 7253 7254 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 7255 return; 7256 7257 /* vblanks work again, re-enable pipe CRC. */ 7258 intel_crtc_enable_pipe_crc(crtc); 7259 } 7260 7261 static void intel_update_crtc(struct intel_atomic_state *state, 7262 struct intel_crtc *crtc) 7263 { 7264 struct drm_i915_private *i915 = to_i915(state->base.dev); 7265 const struct intel_crtc_state *old_crtc_state = 7266 intel_atomic_get_old_crtc_state(state, crtc); 7267 struct intel_crtc_state *new_crtc_state = 7268 intel_atomic_get_new_crtc_state(state, crtc); 7269 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 7270 7271 if (!modeset) { 7272 if (new_crtc_state->preload_luts && 7273 (new_crtc_state->uapi.color_mgmt_changed || 7274 new_crtc_state->update_pipe)) 7275 intel_color_load_luts(new_crtc_state); 7276 7277 intel_pre_plane_update(state, crtc); 7278 7279 if (new_crtc_state->update_pipe) 7280 intel_encoders_update_pipe(state, crtc); 7281 7282 if (DISPLAY_VER(i915) >= 11 && 7283 new_crtc_state->update_pipe) 7284 icl_set_pipe_chicken(new_crtc_state); 7285 } 7286 7287 intel_fbc_update(state, crtc); 7288 7289 if (!modeset && 7290 (new_crtc_state->uapi.color_mgmt_changed || 7291 new_crtc_state->update_pipe)) 7292 intel_color_commit_noarm(new_crtc_state); 7293 7294 intel_crtc_planes_update_noarm(state, crtc); 7295 7296 /* Perform vblank evasion around commit operation */ 7297 intel_pipe_update_start(new_crtc_state); 7298 7299 commit_pipe_pre_planes(state, crtc); 7300 7301 intel_crtc_planes_update_arm(state, crtc); 7302 7303 commit_pipe_post_planes(state, crtc); 7304 7305 intel_pipe_update_end(new_crtc_state); 7306 7307 /* 7308 * We usually enable FIFO underrun interrupts as part of the 7309 * CRTC enable sequence during modesets. But when we inherit a 7310 * valid pipe configuration from the BIOS we need to take care 7311 * of enabling them on the CRTC's first fastset. 7312 */ 7313 if (new_crtc_state->update_pipe && !modeset && 7314 old_crtc_state->inherited) 7315 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state); 7316 } 7317 7318 static void intel_old_crtc_state_disables(struct intel_atomic_state *state, 7319 struct intel_crtc_state *old_crtc_state, 7320 struct intel_crtc_state *new_crtc_state, 7321 struct intel_crtc *crtc) 7322 { 7323 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7324 7325 /* 7326 * We need to disable pipe CRC before disabling the pipe, 7327 * or we race against vblank off. 7328 */ 7329 intel_crtc_disable_pipe_crc(crtc); 7330 7331 dev_priv->display->crtc_disable(state, crtc); 7332 crtc->active = false; 7333 intel_fbc_disable(crtc); 7334 intel_disable_shared_dpll(old_crtc_state); 7335 7336 /* FIXME unify this for all platforms */ 7337 if (!new_crtc_state->hw.active && 7338 !HAS_GMCH(dev_priv)) 7339 intel_initial_watermarks(state, crtc); 7340 } 7341 7342 static void intel_commit_modeset_disables(struct intel_atomic_state *state) 7343 { 7344 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 7345 struct intel_crtc *crtc; 7346 u32 handled = 0; 7347 int i; 7348 7349 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7350 new_crtc_state, i) { 7351 if (!intel_crtc_needs_modeset(new_crtc_state)) 7352 continue; 7353 7354 if (!old_crtc_state->hw.active) 7355 continue; 7356 7357 intel_pre_plane_update(state, crtc); 7358 intel_crtc_disable_planes(state, crtc); 7359 } 7360 7361 /* Only disable port sync and MST slaves */ 7362 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7363 new_crtc_state, i) { 7364 if (!intel_crtc_needs_modeset(new_crtc_state)) 7365 continue; 7366 7367 if (!old_crtc_state->hw.active) 7368 continue; 7369 7370 /* In case of Transcoder port Sync master slave CRTCs can be 7371 * assigned in any order and we need to make sure that 7372 * slave CRTCs are disabled first and then master CRTC since 7373 * Slave vblanks are masked till Master Vblanks. 7374 */ 7375 if (!is_trans_port_sync_slave(old_crtc_state) && 7376 !intel_dp_mst_is_slave_trans(old_crtc_state) && 7377 !intel_crtc_is_bigjoiner_slave(old_crtc_state)) 7378 continue; 7379 7380 intel_old_crtc_state_disables(state, old_crtc_state, 7381 new_crtc_state, crtc); 7382 handled |= BIT(crtc->pipe); 7383 } 7384 7385 /* Disable everything else left on */ 7386 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7387 new_crtc_state, i) { 7388 if (!intel_crtc_needs_modeset(new_crtc_state) || 7389 (handled & BIT(crtc->pipe))) 7390 continue; 7391 7392 if (!old_crtc_state->hw.active) 7393 continue; 7394 7395 intel_old_crtc_state_disables(state, old_crtc_state, 7396 new_crtc_state, crtc); 7397 } 7398 } 7399 7400 static void intel_commit_modeset_enables(struct intel_atomic_state *state) 7401 { 7402 struct intel_crtc_state *new_crtc_state; 7403 struct intel_crtc *crtc; 7404 int i; 7405 7406 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7407 if (!new_crtc_state->hw.active) 7408 continue; 7409 7410 intel_enable_crtc(state, crtc); 7411 intel_update_crtc(state, crtc); 7412 } 7413 } 7414 7415 static void skl_commit_modeset_enables(struct intel_atomic_state *state) 7416 { 7417 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7418 struct intel_crtc *crtc; 7419 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7420 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; 7421 u8 update_pipes = 0, modeset_pipes = 0; 7422 int i; 7423 7424 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7425 enum pipe pipe = crtc->pipe; 7426 7427 if (!new_crtc_state->hw.active) 7428 continue; 7429 7430 /* ignore allocations for crtc's that have been turned off. */ 7431 if (!intel_crtc_needs_modeset(new_crtc_state)) { 7432 entries[pipe] = old_crtc_state->wm.skl.ddb; 7433 update_pipes |= BIT(pipe); 7434 } else { 7435 modeset_pipes |= BIT(pipe); 7436 } 7437 } 7438 7439 /* 7440 * Whenever the number of active pipes changes, we need to make sure we 7441 * update the pipes in the right order so that their ddb allocations 7442 * never overlap with each other between CRTC updates. Otherwise we'll 7443 * cause pipe underruns and other bad stuff. 7444 * 7445 * So first lets enable all pipes that do not need a fullmodeset as 7446 * those don't have any external dependency. 7447 */ 7448 while (update_pipes) { 7449 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7450 new_crtc_state, i) { 7451 enum pipe pipe = crtc->pipe; 7452 7453 if ((update_pipes & BIT(pipe)) == 0) 7454 continue; 7455 7456 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 7457 entries, I915_MAX_PIPES, pipe)) 7458 continue; 7459 7460 entries[pipe] = new_crtc_state->wm.skl.ddb; 7461 update_pipes &= ~BIT(pipe); 7462 7463 intel_update_crtc(state, crtc); 7464 7465 /* 7466 * If this is an already active pipe, it's DDB changed, 7467 * and this isn't the last pipe that needs updating 7468 * then we need to wait for a vblank to pass for the 7469 * new ddb allocation to take effect. 7470 */ 7471 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, 7472 &old_crtc_state->wm.skl.ddb) && 7473 (update_pipes | modeset_pipes)) 7474 intel_crtc_wait_for_next_vblank(crtc); 7475 } 7476 } 7477 7478 update_pipes = modeset_pipes; 7479 7480 /* 7481 * Enable all pipes that needs a modeset and do not depends on other 7482 * pipes 7483 */ 7484 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7485 enum pipe pipe = crtc->pipe; 7486 7487 if ((modeset_pipes & BIT(pipe)) == 0) 7488 continue; 7489 7490 if (intel_dp_mst_is_slave_trans(new_crtc_state) || 7491 is_trans_port_sync_master(new_crtc_state) || 7492 intel_crtc_is_bigjoiner_master(new_crtc_state)) 7493 continue; 7494 7495 modeset_pipes &= ~BIT(pipe); 7496 7497 intel_enable_crtc(state, crtc); 7498 } 7499 7500 /* 7501 * Then we enable all remaining pipes that depend on other 7502 * pipes: MST slaves and port sync masters, big joiner master 7503 */ 7504 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7505 enum pipe pipe = crtc->pipe; 7506 7507 if ((modeset_pipes & BIT(pipe)) == 0) 7508 continue; 7509 7510 modeset_pipes &= ~BIT(pipe); 7511 7512 intel_enable_crtc(state, crtc); 7513 } 7514 7515 /* 7516 * Finally we do the plane updates/etc. for all pipes that got enabled. 7517 */ 7518 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7519 enum pipe pipe = crtc->pipe; 7520 7521 if ((update_pipes & BIT(pipe)) == 0) 7522 continue; 7523 7524 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 7525 entries, I915_MAX_PIPES, pipe)); 7526 7527 entries[pipe] = new_crtc_state->wm.skl.ddb; 7528 update_pipes &= ~BIT(pipe); 7529 7530 intel_update_crtc(state, crtc); 7531 } 7532 7533 drm_WARN_ON(&dev_priv->drm, modeset_pipes); 7534 drm_WARN_ON(&dev_priv->drm, update_pipes); 7535 } 7536 7537 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) 7538 { 7539 struct intel_atomic_state *state, *next; 7540 struct llist_node *freed; 7541 7542 freed = llist_del_all(&dev_priv->atomic_helper.free_list); 7543 llist_for_each_entry_safe(state, next, freed, freed) 7544 drm_atomic_state_put(&state->base); 7545 } 7546 7547 static void intel_atomic_helper_free_state_worker(struct work_struct *work) 7548 { 7549 struct drm_i915_private *dev_priv = 7550 container_of(work, typeof(*dev_priv), atomic_helper.free_work); 7551 7552 intel_atomic_helper_free_state(dev_priv); 7553 } 7554 7555 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) 7556 { 7557 struct wait_queue_entry wait_fence, wait_reset; 7558 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); 7559 7560 init_wait_entry(&wait_fence, 0); 7561 init_wait_entry(&wait_reset, 0); 7562 for (;;) { 7563 prepare_to_wait(&intel_state->commit_ready.wait, 7564 &wait_fence, TASK_UNINTERRUPTIBLE); 7565 prepare_to_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 7566 I915_RESET_MODESET), 7567 &wait_reset, TASK_UNINTERRUPTIBLE); 7568 7569 7570 if (i915_sw_fence_done(&intel_state->commit_ready) || 7571 test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags)) 7572 break; 7573 7574 schedule(); 7575 } 7576 finish_wait(&intel_state->commit_ready.wait, &wait_fence); 7577 finish_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 7578 I915_RESET_MODESET), 7579 &wait_reset); 7580 } 7581 7582 static void intel_cleanup_dsbs(struct intel_atomic_state *state) 7583 { 7584 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7585 struct intel_crtc *crtc; 7586 int i; 7587 7588 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7589 new_crtc_state, i) 7590 intel_dsb_cleanup(old_crtc_state); 7591 } 7592 7593 static void intel_atomic_cleanup_work(struct work_struct *work) 7594 { 7595 struct intel_atomic_state *state = 7596 container_of(work, struct intel_atomic_state, base.commit_work); 7597 struct drm_i915_private *i915 = to_i915(state->base.dev); 7598 7599 intel_cleanup_dsbs(state); 7600 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base); 7601 drm_atomic_helper_commit_cleanup_done(&state->base); 7602 drm_atomic_state_put(&state->base); 7603 7604 intel_atomic_helper_free_state(i915); 7605 } 7606 7607 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state) 7608 { 7609 struct drm_i915_private *i915 = to_i915(state->base.dev); 7610 struct intel_plane *plane; 7611 struct intel_plane_state *plane_state; 7612 int i; 7613 7614 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 7615 struct drm_framebuffer *fb = plane_state->hw.fb; 7616 int cc_plane; 7617 int ret; 7618 7619 if (!fb) 7620 continue; 7621 7622 cc_plane = intel_fb_rc_ccs_cc_plane(fb); 7623 if (cc_plane < 0) 7624 continue; 7625 7626 /* 7627 * The layout of the fast clear color value expected by HW 7628 * (the DRM ABI requiring this value to be located in fb at 7629 * offset 0 of cc plane, plane #2 previous generations or 7630 * plane #1 for flat ccs): 7631 * - 4 x 4 bytes per-channel value 7632 * (in surface type specific float/int format provided by the fb user) 7633 * - 8 bytes native color value used by the display 7634 * (converted/written by GPU during a fast clear operation using the 7635 * above per-channel values) 7636 * 7637 * The commit's FB prepare hook already ensured that FB obj is pinned and the 7638 * caller made sure that the object is synced wrt. the related color clear value 7639 * GPU write on it. 7640 */ 7641 ret = i915_gem_object_read_from_page(intel_fb_obj(fb), 7642 fb->offsets[cc_plane] + 16, 7643 &plane_state->ccval, 7644 sizeof(plane_state->ccval)); 7645 /* The above could only fail if the FB obj has an unexpected backing store type. */ 7646 drm_WARN_ON(&i915->drm, ret); 7647 } 7648 } 7649 7650 static void intel_atomic_commit_tail(struct intel_atomic_state *state) 7651 { 7652 struct drm_device *dev = state->base.dev; 7653 struct drm_i915_private *dev_priv = to_i915(dev); 7654 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 7655 struct intel_crtc *crtc; 7656 struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {}; 7657 intel_wakeref_t wakeref = 0; 7658 int i; 7659 7660 intel_atomic_commit_fence_wait(state); 7661 7662 drm_atomic_helper_wait_for_dependencies(&state->base); 7663 7664 if (state->modeset) 7665 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); 7666 7667 intel_atomic_prepare_plane_clear_colors(state); 7668 7669 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7670 new_crtc_state, i) { 7671 if (intel_crtc_needs_modeset(new_crtc_state) || 7672 new_crtc_state->update_pipe) { 7673 modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]); 7674 } 7675 } 7676 7677 intel_commit_modeset_disables(state); 7678 7679 /* FIXME: Eventually get rid of our crtc->config pointer */ 7680 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7681 crtc->config = new_crtc_state; 7682 7683 if (state->modeset) { 7684 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base); 7685 7686 intel_set_cdclk_pre_plane_update(state); 7687 7688 intel_modeset_verify_disabled(dev_priv, state); 7689 } 7690 7691 intel_sagv_pre_plane_update(state); 7692 7693 /* Complete the events for pipes that have now been disabled */ 7694 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7695 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 7696 7697 /* Complete events for now disable pipes here. */ 7698 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) { 7699 spin_lock_irq(&dev->event_lock); 7700 drm_crtc_send_vblank_event(&crtc->base, 7701 new_crtc_state->uapi.event); 7702 spin_unlock_irq(&dev->event_lock); 7703 7704 new_crtc_state->uapi.event = NULL; 7705 } 7706 } 7707 7708 intel_encoders_update_prepare(state); 7709 7710 intel_dbuf_pre_plane_update(state); 7711 intel_mbus_dbox_update(state); 7712 7713 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7714 if (new_crtc_state->do_async_flip) 7715 intel_crtc_enable_flip_done(state, crtc); 7716 } 7717 7718 /* Now enable the clocks, plane, pipe, and connectors that we set up. */ 7719 dev_priv->display->commit_modeset_enables(state); 7720 7721 intel_encoders_update_complete(state); 7722 7723 if (state->modeset) 7724 intel_set_cdclk_post_plane_update(state); 7725 7726 intel_wait_for_vblank_workers(state); 7727 7728 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here 7729 * already, but still need the state for the delayed optimization. To 7730 * fix this: 7731 * - wrap the optimization/post_plane_update stuff into a per-crtc work. 7732 * - schedule that vblank worker _before_ calling hw_done 7733 * - at the start of commit_tail, cancel it _synchrously 7734 * - switch over to the vblank wait helper in the core after that since 7735 * we don't need out special handling any more. 7736 */ 7737 drm_atomic_helper_wait_for_flip_done(dev, &state->base); 7738 7739 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7740 if (new_crtc_state->do_async_flip) 7741 intel_crtc_disable_flip_done(state, crtc); 7742 } 7743 7744 /* 7745 * Now that the vblank has passed, we can go ahead and program the 7746 * optimal watermarks on platforms that need two-step watermark 7747 * programming. 7748 * 7749 * TODO: Move this (and other cleanup) to an async worker eventually. 7750 */ 7751 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7752 new_crtc_state, i) { 7753 /* 7754 * Gen2 reports pipe underruns whenever all planes are disabled. 7755 * So re-enable underrun reporting after some planes get enabled. 7756 * 7757 * We do this before .optimize_watermarks() so that we have a 7758 * chance of catching underruns with the intermediate watermarks 7759 * vs. the new plane configuration. 7760 */ 7761 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state)) 7762 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 7763 7764 intel_optimize_watermarks(state, crtc); 7765 } 7766 7767 intel_dbuf_post_plane_update(state); 7768 intel_psr_post_plane_update(state); 7769 7770 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7771 intel_post_plane_update(state, crtc); 7772 7773 modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]); 7774 7775 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state); 7776 7777 /* 7778 * DSB cleanup is done in cleanup_work aligning with framebuffer 7779 * cleanup. So copy and reset the dsb structure to sync with 7780 * commit_done and later do dsb cleanup in cleanup_work. 7781 */ 7782 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb); 7783 } 7784 7785 /* Underruns don't always raise interrupts, so check manually */ 7786 intel_check_cpu_fifo_underruns(dev_priv); 7787 intel_check_pch_fifo_underruns(dev_priv); 7788 7789 if (state->modeset) 7790 intel_verify_planes(state); 7791 7792 intel_sagv_post_plane_update(state); 7793 7794 drm_atomic_helper_commit_hw_done(&state->base); 7795 7796 if (state->modeset) { 7797 /* As one of the primary mmio accessors, KMS has a high 7798 * likelihood of triggering bugs in unclaimed access. After we 7799 * finish modesetting, see if an error has been flagged, and if 7800 * so enable debugging for the next modeset - and hope we catch 7801 * the culprit. 7802 */ 7803 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); 7804 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref); 7805 } 7806 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7807 7808 /* 7809 * Defer the cleanup of the old state to a separate worker to not 7810 * impede the current task (userspace for blocking modesets) that 7811 * are executed inline. For out-of-line asynchronous modesets/flips, 7812 * deferring to a new worker seems overkill, but we would place a 7813 * schedule point (cond_resched()) here anyway to keep latencies 7814 * down. 7815 */ 7816 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work); 7817 queue_work(system_highpri_wq, &state->base.commit_work); 7818 } 7819 7820 static void intel_atomic_commit_work(struct work_struct *work) 7821 { 7822 struct intel_atomic_state *state = 7823 container_of(work, struct intel_atomic_state, base.commit_work); 7824 7825 intel_atomic_commit_tail(state); 7826 } 7827 7828 static int 7829 intel_atomic_commit_ready(struct i915_sw_fence *fence, 7830 enum i915_sw_fence_notify notify) 7831 { 7832 struct intel_atomic_state *state = 7833 container_of(fence, struct intel_atomic_state, commit_ready); 7834 7835 switch (notify) { 7836 case FENCE_COMPLETE: 7837 /* we do blocking waits in the worker, nothing to do here */ 7838 break; 7839 case FENCE_FREE: 7840 { 7841 struct intel_atomic_helper *helper = 7842 &to_i915(state->base.dev)->atomic_helper; 7843 7844 if (llist_add(&state->freed, &helper->free_list)) 7845 schedule_work(&helper->free_work); 7846 break; 7847 } 7848 } 7849 7850 return NOTIFY_DONE; 7851 } 7852 7853 static void intel_atomic_track_fbs(struct intel_atomic_state *state) 7854 { 7855 struct intel_plane_state *old_plane_state, *new_plane_state; 7856 struct intel_plane *plane; 7857 int i; 7858 7859 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 7860 new_plane_state, i) 7861 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), 7862 to_intel_frontbuffer(new_plane_state->hw.fb), 7863 plane->frontbuffer_bit); 7864 } 7865 7866 static int intel_atomic_commit(struct drm_device *dev, 7867 struct drm_atomic_state *_state, 7868 bool nonblock) 7869 { 7870 struct intel_atomic_state *state = to_intel_atomic_state(_state); 7871 struct drm_i915_private *dev_priv = to_i915(dev); 7872 int ret = 0; 7873 7874 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 7875 7876 drm_atomic_state_get(&state->base); 7877 i915_sw_fence_init(&state->commit_ready, 7878 intel_atomic_commit_ready); 7879 7880 /* 7881 * The intel_legacy_cursor_update() fast path takes care 7882 * of avoiding the vblank waits for simple cursor 7883 * movement and flips. For cursor on/off and size changes, 7884 * we want to perform the vblank waits so that watermark 7885 * updates happen during the correct frames. Gen9+ have 7886 * double buffered watermarks and so shouldn't need this. 7887 * 7888 * Unset state->legacy_cursor_update before the call to 7889 * drm_atomic_helper_setup_commit() because otherwise 7890 * drm_atomic_helper_wait_for_flip_done() is a noop and 7891 * we get FIFO underruns because we didn't wait 7892 * for vblank. 7893 * 7894 * FIXME doing watermarks and fb cleanup from a vblank worker 7895 * (assuming we had any) would solve these problems. 7896 */ 7897 if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) { 7898 struct intel_crtc_state *new_crtc_state; 7899 struct intel_crtc *crtc; 7900 int i; 7901 7902 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7903 if (new_crtc_state->wm.need_postvbl_update || 7904 new_crtc_state->update_wm_post) 7905 state->base.legacy_cursor_update = false; 7906 } 7907 7908 ret = intel_atomic_prepare_commit(state); 7909 if (ret) { 7910 drm_dbg_atomic(&dev_priv->drm, 7911 "Preparing state failed with %i\n", ret); 7912 i915_sw_fence_commit(&state->commit_ready); 7913 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7914 return ret; 7915 } 7916 7917 ret = drm_atomic_helper_setup_commit(&state->base, nonblock); 7918 if (!ret) 7919 ret = drm_atomic_helper_swap_state(&state->base, true); 7920 if (!ret) 7921 intel_atomic_swap_global_state(state); 7922 7923 if (ret) { 7924 struct intel_crtc_state *new_crtc_state; 7925 struct intel_crtc *crtc; 7926 int i; 7927 7928 i915_sw_fence_commit(&state->commit_ready); 7929 7930 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7931 intel_dsb_cleanup(new_crtc_state); 7932 7933 drm_atomic_helper_cleanup_planes(dev, &state->base); 7934 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7935 return ret; 7936 } 7937 intel_shared_dpll_swap_state(state); 7938 intel_atomic_track_fbs(state); 7939 7940 drm_atomic_state_get(&state->base); 7941 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work); 7942 7943 i915_sw_fence_commit(&state->commit_ready); 7944 if (nonblock && state->modeset) { 7945 queue_work(dev_priv->modeset_wq, &state->base.commit_work); 7946 } else if (nonblock) { 7947 queue_work(dev_priv->flip_wq, &state->base.commit_work); 7948 } else { 7949 if (state->modeset) 7950 flush_workqueue(dev_priv->modeset_wq); 7951 intel_atomic_commit_tail(state); 7952 } 7953 7954 return 0; 7955 } 7956 7957 /** 7958 * intel_plane_destroy - destroy a plane 7959 * @plane: plane to destroy 7960 * 7961 * Common destruction function for all types of planes (primary, cursor, 7962 * sprite). 7963 */ 7964 void intel_plane_destroy(struct drm_plane *plane) 7965 { 7966 drm_plane_cleanup(plane); 7967 kfree(to_intel_plane(plane)); 7968 } 7969 7970 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv) 7971 { 7972 struct intel_plane *plane; 7973 7974 for_each_intel_plane(&dev_priv->drm, plane) { 7975 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, 7976 plane->pipe); 7977 7978 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base); 7979 } 7980 } 7981 7982 7983 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 7984 struct drm_file *file) 7985 { 7986 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; 7987 struct drm_crtc *drmmode_crtc; 7988 struct intel_crtc *crtc; 7989 7990 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id); 7991 if (!drmmode_crtc) 7992 return -ENOENT; 7993 7994 crtc = to_intel_crtc(drmmode_crtc); 7995 pipe_from_crtc_id->pipe = crtc->pipe; 7996 7997 return 0; 7998 } 7999 8000 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder) 8001 { 8002 struct drm_device *dev = encoder->base.dev; 8003 struct intel_encoder *source_encoder; 8004 u32 possible_clones = 0; 8005 8006 for_each_intel_encoder(dev, source_encoder) { 8007 if (encoders_cloneable(encoder, source_encoder)) 8008 possible_clones |= drm_encoder_mask(&source_encoder->base); 8009 } 8010 8011 return possible_clones; 8012 } 8013 8014 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder) 8015 { 8016 struct drm_device *dev = encoder->base.dev; 8017 struct intel_crtc *crtc; 8018 u32 possible_crtcs = 0; 8019 8020 for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask) 8021 possible_crtcs |= drm_crtc_mask(&crtc->base); 8022 8023 return possible_crtcs; 8024 } 8025 8026 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv) 8027 { 8028 if (!IS_MOBILE(dev_priv)) 8029 return false; 8030 8031 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0) 8032 return false; 8033 8034 if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE)) 8035 return false; 8036 8037 return true; 8038 } 8039 8040 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv) 8041 { 8042 if (DISPLAY_VER(dev_priv) >= 9) 8043 return false; 8044 8045 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) 8046 return false; 8047 8048 if (HAS_PCH_LPT_H(dev_priv) && 8049 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) 8050 return false; 8051 8052 /* DDI E can't be used if DDI A requires 4 lanes */ 8053 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 8054 return false; 8055 8056 if (!dev_priv->vbt.int_crt_support) 8057 return false; 8058 8059 return true; 8060 } 8061 8062 static void intel_setup_outputs(struct drm_i915_private *dev_priv) 8063 { 8064 struct intel_encoder *encoder; 8065 bool dpd_is_edp = false; 8066 8067 intel_pps_unlock_regs_wa(dev_priv); 8068 8069 if (!HAS_DISPLAY(dev_priv)) 8070 return; 8071 8072 if (IS_DG2(dev_priv)) { 8073 intel_ddi_init(dev_priv, PORT_A); 8074 intel_ddi_init(dev_priv, PORT_B); 8075 intel_ddi_init(dev_priv, PORT_C); 8076 intel_ddi_init(dev_priv, PORT_D_XELPD); 8077 intel_ddi_init(dev_priv, PORT_TC1); 8078 } else if (IS_ALDERLAKE_P(dev_priv)) { 8079 intel_ddi_init(dev_priv, PORT_A); 8080 intel_ddi_init(dev_priv, PORT_B); 8081 intel_ddi_init(dev_priv, PORT_TC1); 8082 intel_ddi_init(dev_priv, PORT_TC2); 8083 intel_ddi_init(dev_priv, PORT_TC3); 8084 intel_ddi_init(dev_priv, PORT_TC4); 8085 icl_dsi_init(dev_priv); 8086 } else if (IS_ALDERLAKE_S(dev_priv)) { 8087 intel_ddi_init(dev_priv, PORT_A); 8088 intel_ddi_init(dev_priv, PORT_TC1); 8089 intel_ddi_init(dev_priv, PORT_TC2); 8090 intel_ddi_init(dev_priv, PORT_TC3); 8091 intel_ddi_init(dev_priv, PORT_TC4); 8092 } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) { 8093 intel_ddi_init(dev_priv, PORT_A); 8094 intel_ddi_init(dev_priv, PORT_B); 8095 intel_ddi_init(dev_priv, PORT_TC1); 8096 intel_ddi_init(dev_priv, PORT_TC2); 8097 } else if (DISPLAY_VER(dev_priv) >= 12) { 8098 intel_ddi_init(dev_priv, PORT_A); 8099 intel_ddi_init(dev_priv, PORT_B); 8100 intel_ddi_init(dev_priv, PORT_TC1); 8101 intel_ddi_init(dev_priv, PORT_TC2); 8102 intel_ddi_init(dev_priv, PORT_TC3); 8103 intel_ddi_init(dev_priv, PORT_TC4); 8104 intel_ddi_init(dev_priv, PORT_TC5); 8105 intel_ddi_init(dev_priv, PORT_TC6); 8106 icl_dsi_init(dev_priv); 8107 } else if (IS_JSL_EHL(dev_priv)) { 8108 intel_ddi_init(dev_priv, PORT_A); 8109 intel_ddi_init(dev_priv, PORT_B); 8110 intel_ddi_init(dev_priv, PORT_C); 8111 intel_ddi_init(dev_priv, PORT_D); 8112 icl_dsi_init(dev_priv); 8113 } else if (DISPLAY_VER(dev_priv) == 11) { 8114 intel_ddi_init(dev_priv, PORT_A); 8115 intel_ddi_init(dev_priv, PORT_B); 8116 intel_ddi_init(dev_priv, PORT_C); 8117 intel_ddi_init(dev_priv, PORT_D); 8118 intel_ddi_init(dev_priv, PORT_E); 8119 intel_ddi_init(dev_priv, PORT_F); 8120 icl_dsi_init(dev_priv); 8121 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 8122 intel_ddi_init(dev_priv, PORT_A); 8123 intel_ddi_init(dev_priv, PORT_B); 8124 intel_ddi_init(dev_priv, PORT_C); 8125 vlv_dsi_init(dev_priv); 8126 } else if (DISPLAY_VER(dev_priv) >= 9) { 8127 intel_ddi_init(dev_priv, PORT_A); 8128 intel_ddi_init(dev_priv, PORT_B); 8129 intel_ddi_init(dev_priv, PORT_C); 8130 intel_ddi_init(dev_priv, PORT_D); 8131 intel_ddi_init(dev_priv, PORT_E); 8132 } else if (HAS_DDI(dev_priv)) { 8133 u32 found; 8134 8135 if (intel_ddi_crt_present(dev_priv)) 8136 intel_crt_init(dev_priv); 8137 8138 /* Haswell uses DDI functions to detect digital outputs. */ 8139 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 8140 if (found) 8141 intel_ddi_init(dev_priv, PORT_A); 8142 8143 found = intel_de_read(dev_priv, SFUSE_STRAP); 8144 if (found & SFUSE_STRAP_DDIB_DETECTED) 8145 intel_ddi_init(dev_priv, PORT_B); 8146 if (found & SFUSE_STRAP_DDIC_DETECTED) 8147 intel_ddi_init(dev_priv, PORT_C); 8148 if (found & SFUSE_STRAP_DDID_DETECTED) 8149 intel_ddi_init(dev_priv, PORT_D); 8150 if (found & SFUSE_STRAP_DDIF_DETECTED) 8151 intel_ddi_init(dev_priv, PORT_F); 8152 } else if (HAS_PCH_SPLIT(dev_priv)) { 8153 int found; 8154 8155 /* 8156 * intel_edp_init_connector() depends on this completing first, 8157 * to prevent the registration of both eDP and LVDS and the 8158 * incorrect sharing of the PPS. 8159 */ 8160 intel_lvds_init(dev_priv); 8161 intel_crt_init(dev_priv); 8162 8163 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D); 8164 8165 if (ilk_has_edp_a(dev_priv)) 8166 g4x_dp_init(dev_priv, DP_A, PORT_A); 8167 8168 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) { 8169 /* PCH SDVOB multiplex with HDMIB */ 8170 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); 8171 if (!found) 8172 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); 8173 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED)) 8174 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B); 8175 } 8176 8177 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED) 8178 g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); 8179 8180 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED) 8181 g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D); 8182 8183 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED) 8184 g4x_dp_init(dev_priv, PCH_DP_C, PORT_C); 8185 8186 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED) 8187 g4x_dp_init(dev_priv, PCH_DP_D, PORT_D); 8188 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 8189 bool has_edp, has_port; 8190 8191 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support) 8192 intel_crt_init(dev_priv); 8193 8194 /* 8195 * The DP_DETECTED bit is the latched state of the DDC 8196 * SDA pin at boot. However since eDP doesn't require DDC 8197 * (no way to plug in a DP->HDMI dongle) the DDC pins for 8198 * eDP ports may have been muxed to an alternate function. 8199 * Thus we can't rely on the DP_DETECTED bit alone to detect 8200 * eDP ports. Consult the VBT as well as DP_DETECTED to 8201 * detect eDP ports. 8202 * 8203 * Sadly the straps seem to be missing sometimes even for HDMI 8204 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap 8205 * and VBT for the presence of the port. Additionally we can't 8206 * trust the port type the VBT declares as we've seen at least 8207 * HDMI ports that the VBT claim are DP or eDP. 8208 */ 8209 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B); 8210 has_port = intel_bios_is_port_present(dev_priv, PORT_B); 8211 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port) 8212 has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B); 8213 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) 8214 g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); 8215 8216 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C); 8217 has_port = intel_bios_is_port_present(dev_priv, PORT_C); 8218 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port) 8219 has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C); 8220 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) 8221 g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); 8222 8223 if (IS_CHERRYVIEW(dev_priv)) { 8224 /* 8225 * eDP not supported on port D, 8226 * so no need to worry about it 8227 */ 8228 has_port = intel_bios_is_port_present(dev_priv, PORT_D); 8229 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port) 8230 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D); 8231 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port) 8232 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D); 8233 } 8234 8235 vlv_dsi_init(dev_priv); 8236 } else if (IS_PINEVIEW(dev_priv)) { 8237 intel_lvds_init(dev_priv); 8238 intel_crt_init(dev_priv); 8239 } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) { 8240 bool found = false; 8241 8242 if (IS_MOBILE(dev_priv)) 8243 intel_lvds_init(dev_priv); 8244 8245 intel_crt_init(dev_priv); 8246 8247 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 8248 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n"); 8249 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); 8250 if (!found && IS_G4X(dev_priv)) { 8251 drm_dbg_kms(&dev_priv->drm, 8252 "probing HDMI on SDVOB\n"); 8253 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); 8254 } 8255 8256 if (!found && IS_G4X(dev_priv)) 8257 g4x_dp_init(dev_priv, DP_B, PORT_B); 8258 } 8259 8260 /* Before G4X SDVOC doesn't have its own detect register */ 8261 8262 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 8263 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n"); 8264 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); 8265 } 8266 8267 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) { 8268 8269 if (IS_G4X(dev_priv)) { 8270 drm_dbg_kms(&dev_priv->drm, 8271 "probing HDMI on SDVOC\n"); 8272 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); 8273 } 8274 if (IS_G4X(dev_priv)) 8275 g4x_dp_init(dev_priv, DP_C, PORT_C); 8276 } 8277 8278 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED)) 8279 g4x_dp_init(dev_priv, DP_D, PORT_D); 8280 8281 if (SUPPORTS_TV(dev_priv)) 8282 intel_tv_init(dev_priv); 8283 } else if (DISPLAY_VER(dev_priv) == 2) { 8284 if (IS_I85X(dev_priv)) 8285 intel_lvds_init(dev_priv); 8286 8287 intel_crt_init(dev_priv); 8288 intel_dvo_init(dev_priv); 8289 } 8290 8291 for_each_intel_encoder(&dev_priv->drm, encoder) { 8292 encoder->base.possible_crtcs = 8293 intel_encoder_possible_crtcs(encoder); 8294 encoder->base.possible_clones = 8295 intel_encoder_possible_clones(encoder); 8296 } 8297 8298 intel_init_pch_refclk(dev_priv); 8299 8300 drm_helper_move_panel_connectors_to_head(&dev_priv->drm); 8301 } 8302 8303 static enum drm_mode_status 8304 intel_mode_valid(struct drm_device *dev, 8305 const struct drm_display_mode *mode) 8306 { 8307 struct drm_i915_private *dev_priv = to_i915(dev); 8308 int hdisplay_max, htotal_max; 8309 int vdisplay_max, vtotal_max; 8310 8311 /* 8312 * Can't reject DBLSCAN here because Xorg ddxen can add piles 8313 * of DBLSCAN modes to the output's mode list when they detect 8314 * the scaling mode property on the connector. And they don't 8315 * ask the kernel to validate those modes in any way until 8316 * modeset time at which point the client gets a protocol error. 8317 * So in order to not upset those clients we silently ignore the 8318 * DBLSCAN flag on such connectors. For other connectors we will 8319 * reject modes with the DBLSCAN flag in encoder->compute_config(). 8320 * And we always reject DBLSCAN modes in connector->mode_valid() 8321 * as we never want such modes on the connector's mode list. 8322 */ 8323 8324 if (mode->vscan > 1) 8325 return MODE_NO_VSCAN; 8326 8327 if (mode->flags & DRM_MODE_FLAG_HSKEW) 8328 return MODE_H_ILLEGAL; 8329 8330 if (mode->flags & (DRM_MODE_FLAG_CSYNC | 8331 DRM_MODE_FLAG_NCSYNC | 8332 DRM_MODE_FLAG_PCSYNC)) 8333 return MODE_HSYNC; 8334 8335 if (mode->flags & (DRM_MODE_FLAG_BCAST | 8336 DRM_MODE_FLAG_PIXMUX | 8337 DRM_MODE_FLAG_CLKDIV2)) 8338 return MODE_BAD; 8339 8340 /* Transcoder timing limits */ 8341 if (DISPLAY_VER(dev_priv) >= 11) { 8342 hdisplay_max = 16384; 8343 vdisplay_max = 8192; 8344 htotal_max = 16384; 8345 vtotal_max = 8192; 8346 } else if (DISPLAY_VER(dev_priv) >= 9 || 8347 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 8348 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ 8349 vdisplay_max = 4096; 8350 htotal_max = 8192; 8351 vtotal_max = 8192; 8352 } else if (DISPLAY_VER(dev_priv) >= 3) { 8353 hdisplay_max = 4096; 8354 vdisplay_max = 4096; 8355 htotal_max = 8192; 8356 vtotal_max = 8192; 8357 } else { 8358 hdisplay_max = 2048; 8359 vdisplay_max = 2048; 8360 htotal_max = 4096; 8361 vtotal_max = 4096; 8362 } 8363 8364 if (mode->hdisplay > hdisplay_max || 8365 mode->hsync_start > htotal_max || 8366 mode->hsync_end > htotal_max || 8367 mode->htotal > htotal_max) 8368 return MODE_H_ILLEGAL; 8369 8370 if (mode->vdisplay > vdisplay_max || 8371 mode->vsync_start > vtotal_max || 8372 mode->vsync_end > vtotal_max || 8373 mode->vtotal > vtotal_max) 8374 return MODE_V_ILLEGAL; 8375 8376 if (DISPLAY_VER(dev_priv) >= 5) { 8377 if (mode->hdisplay < 64 || 8378 mode->htotal - mode->hdisplay < 32) 8379 return MODE_H_ILLEGAL; 8380 8381 if (mode->vtotal - mode->vdisplay < 5) 8382 return MODE_V_ILLEGAL; 8383 } else { 8384 if (mode->htotal - mode->hdisplay < 32) 8385 return MODE_H_ILLEGAL; 8386 8387 if (mode->vtotal - mode->vdisplay < 3) 8388 return MODE_V_ILLEGAL; 8389 } 8390 8391 /* 8392 * Cantiga+ cannot handle modes with a hsync front porch of 0. 8393 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. 8394 */ 8395 if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) && 8396 mode->hsync_start == mode->hdisplay) 8397 return MODE_H_ILLEGAL; 8398 8399 return MODE_OK; 8400 } 8401 8402 enum drm_mode_status 8403 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 8404 const struct drm_display_mode *mode, 8405 bool bigjoiner) 8406 { 8407 int plane_width_max, plane_height_max; 8408 8409 /* 8410 * intel_mode_valid() should be 8411 * sufficient on older platforms. 8412 */ 8413 if (DISPLAY_VER(dev_priv) < 9) 8414 return MODE_OK; 8415 8416 /* 8417 * Most people will probably want a fullscreen 8418 * plane so let's not advertize modes that are 8419 * too big for that. 8420 */ 8421 if (DISPLAY_VER(dev_priv) >= 11) { 8422 plane_width_max = 5120 << bigjoiner; 8423 plane_height_max = 4320; 8424 } else { 8425 plane_width_max = 5120; 8426 plane_height_max = 4096; 8427 } 8428 8429 if (mode->hdisplay > plane_width_max) 8430 return MODE_H_ILLEGAL; 8431 8432 if (mode->vdisplay > plane_height_max) 8433 return MODE_V_ILLEGAL; 8434 8435 return MODE_OK; 8436 } 8437 8438 static const struct drm_mode_config_funcs intel_mode_funcs = { 8439 .fb_create = intel_user_framebuffer_create, 8440 .get_format_info = intel_fb_get_format_info, 8441 .output_poll_changed = intel_fbdev_output_poll_changed, 8442 .mode_valid = intel_mode_valid, 8443 .atomic_check = intel_atomic_check, 8444 .atomic_commit = intel_atomic_commit, 8445 .atomic_state_alloc = intel_atomic_state_alloc, 8446 .atomic_state_clear = intel_atomic_state_clear, 8447 .atomic_state_free = intel_atomic_state_free, 8448 }; 8449 8450 static const struct drm_i915_display_funcs skl_display_funcs = { 8451 .get_pipe_config = hsw_get_pipe_config, 8452 .crtc_enable = hsw_crtc_enable, 8453 .crtc_disable = hsw_crtc_disable, 8454 .commit_modeset_enables = skl_commit_modeset_enables, 8455 .get_initial_plane_config = skl_get_initial_plane_config, 8456 }; 8457 8458 static const struct drm_i915_display_funcs ddi_display_funcs = { 8459 .get_pipe_config = hsw_get_pipe_config, 8460 .crtc_enable = hsw_crtc_enable, 8461 .crtc_disable = hsw_crtc_disable, 8462 .commit_modeset_enables = intel_commit_modeset_enables, 8463 .get_initial_plane_config = i9xx_get_initial_plane_config, 8464 }; 8465 8466 static const struct drm_i915_display_funcs pch_split_display_funcs = { 8467 .get_pipe_config = ilk_get_pipe_config, 8468 .crtc_enable = ilk_crtc_enable, 8469 .crtc_disable = ilk_crtc_disable, 8470 .commit_modeset_enables = intel_commit_modeset_enables, 8471 .get_initial_plane_config = i9xx_get_initial_plane_config, 8472 }; 8473 8474 static const struct drm_i915_display_funcs vlv_display_funcs = { 8475 .get_pipe_config = i9xx_get_pipe_config, 8476 .crtc_enable = valleyview_crtc_enable, 8477 .crtc_disable = i9xx_crtc_disable, 8478 .commit_modeset_enables = intel_commit_modeset_enables, 8479 .get_initial_plane_config = i9xx_get_initial_plane_config, 8480 }; 8481 8482 static const struct drm_i915_display_funcs i9xx_display_funcs = { 8483 .get_pipe_config = i9xx_get_pipe_config, 8484 .crtc_enable = i9xx_crtc_enable, 8485 .crtc_disable = i9xx_crtc_disable, 8486 .commit_modeset_enables = intel_commit_modeset_enables, 8487 .get_initial_plane_config = i9xx_get_initial_plane_config, 8488 }; 8489 8490 /** 8491 * intel_init_display_hooks - initialize the display modesetting hooks 8492 * @dev_priv: device private 8493 */ 8494 void intel_init_display_hooks(struct drm_i915_private *dev_priv) 8495 { 8496 if (!HAS_DISPLAY(dev_priv)) 8497 return; 8498 8499 intel_init_cdclk_hooks(dev_priv); 8500 intel_audio_hooks_init(dev_priv); 8501 8502 intel_dpll_init_clock_hook(dev_priv); 8503 8504 if (DISPLAY_VER(dev_priv) >= 9) { 8505 dev_priv->display = &skl_display_funcs; 8506 } else if (HAS_DDI(dev_priv)) { 8507 dev_priv->display = &ddi_display_funcs; 8508 } else if (HAS_PCH_SPLIT(dev_priv)) { 8509 dev_priv->display = &pch_split_display_funcs; 8510 } else if (IS_CHERRYVIEW(dev_priv) || 8511 IS_VALLEYVIEW(dev_priv)) { 8512 dev_priv->display = &vlv_display_funcs; 8513 } else { 8514 dev_priv->display = &i9xx_display_funcs; 8515 } 8516 8517 intel_fdi_init_hook(dev_priv); 8518 } 8519 8520 void intel_modeset_init_hw(struct drm_i915_private *i915) 8521 { 8522 struct intel_cdclk_state *cdclk_state; 8523 8524 if (!HAS_DISPLAY(i915)) 8525 return; 8526 8527 cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state); 8528 8529 intel_update_cdclk(i915); 8530 intel_cdclk_dump_config(i915, &i915->cdclk.hw, "Current CDCLK"); 8531 cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw; 8532 } 8533 8534 static int sanitize_watermarks_add_affected(struct drm_atomic_state *state) 8535 { 8536 struct drm_plane *plane; 8537 struct intel_crtc *crtc; 8538 8539 for_each_intel_crtc(state->dev, crtc) { 8540 struct intel_crtc_state *crtc_state; 8541 8542 crtc_state = intel_atomic_get_crtc_state(state, crtc); 8543 if (IS_ERR(crtc_state)) 8544 return PTR_ERR(crtc_state); 8545 8546 if (crtc_state->hw.active) { 8547 /* 8548 * Preserve the inherited flag to avoid 8549 * taking the full modeset path. 8550 */ 8551 crtc_state->inherited = true; 8552 } 8553 } 8554 8555 drm_for_each_plane(plane, state->dev) { 8556 struct drm_plane_state *plane_state; 8557 8558 plane_state = drm_atomic_get_plane_state(state, plane); 8559 if (IS_ERR(plane_state)) 8560 return PTR_ERR(plane_state); 8561 } 8562 8563 return 0; 8564 } 8565 8566 /* 8567 * Calculate what we think the watermarks should be for the state we've read 8568 * out of the hardware and then immediately program those watermarks so that 8569 * we ensure the hardware settings match our internal state. 8570 * 8571 * We can calculate what we think WM's should be by creating a duplicate of the 8572 * current state (which was constructed during hardware readout) and running it 8573 * through the atomic check code to calculate new watermark values in the 8574 * state object. 8575 */ 8576 static void sanitize_watermarks(struct drm_i915_private *dev_priv) 8577 { 8578 struct drm_atomic_state *state; 8579 struct intel_atomic_state *intel_state; 8580 struct intel_crtc *crtc; 8581 struct intel_crtc_state *crtc_state; 8582 struct drm_modeset_acquire_ctx ctx; 8583 int ret; 8584 int i; 8585 8586 /* Only supported on platforms that use atomic watermark design */ 8587 if (!dev_priv->wm_disp->optimize_watermarks) 8588 return; 8589 8590 state = drm_atomic_state_alloc(&dev_priv->drm); 8591 if (drm_WARN_ON(&dev_priv->drm, !state)) 8592 return; 8593 8594 intel_state = to_intel_atomic_state(state); 8595 8596 drm_modeset_acquire_init(&ctx, 0); 8597 8598 retry: 8599 state->acquire_ctx = &ctx; 8600 8601 /* 8602 * Hardware readout is the only time we don't want to calculate 8603 * intermediate watermarks (since we don't trust the current 8604 * watermarks). 8605 */ 8606 if (!HAS_GMCH(dev_priv)) 8607 intel_state->skip_intermediate_wm = true; 8608 8609 ret = sanitize_watermarks_add_affected(state); 8610 if (ret) 8611 goto fail; 8612 8613 ret = intel_atomic_check(&dev_priv->drm, state); 8614 if (ret) 8615 goto fail; 8616 8617 /* Write calculated watermark values back */ 8618 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) { 8619 crtc_state->wm.need_postvbl_update = true; 8620 intel_optimize_watermarks(intel_state, crtc); 8621 8622 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm; 8623 } 8624 8625 fail: 8626 if (ret == -EDEADLK) { 8627 drm_atomic_state_clear(state); 8628 drm_modeset_backoff(&ctx); 8629 goto retry; 8630 } 8631 8632 /* 8633 * If we fail here, it means that the hardware appears to be 8634 * programmed in a way that shouldn't be possible, given our 8635 * understanding of watermark requirements. This might mean a 8636 * mistake in the hardware readout code or a mistake in the 8637 * watermark calculations for a given platform. Raise a WARN 8638 * so that this is noticeable. 8639 * 8640 * If this actually happens, we'll have to just leave the 8641 * BIOS-programmed watermarks untouched and hope for the best. 8642 */ 8643 drm_WARN(&dev_priv->drm, ret, 8644 "Could not determine valid watermarks for inherited state\n"); 8645 8646 drm_atomic_state_put(state); 8647 8648 drm_modeset_drop_locks(&ctx); 8649 drm_modeset_acquire_fini(&ctx); 8650 } 8651 8652 static int intel_initial_commit(struct drm_device *dev) 8653 { 8654 struct drm_atomic_state *state = NULL; 8655 struct drm_modeset_acquire_ctx ctx; 8656 struct intel_crtc *crtc; 8657 int ret = 0; 8658 8659 state = drm_atomic_state_alloc(dev); 8660 if (!state) 8661 return -ENOMEM; 8662 8663 drm_modeset_acquire_init(&ctx, 0); 8664 8665 retry: 8666 state->acquire_ctx = &ctx; 8667 8668 for_each_intel_crtc(dev, crtc) { 8669 struct intel_crtc_state *crtc_state = 8670 intel_atomic_get_crtc_state(state, crtc); 8671 8672 if (IS_ERR(crtc_state)) { 8673 ret = PTR_ERR(crtc_state); 8674 goto out; 8675 } 8676 8677 if (crtc_state->hw.active) { 8678 struct intel_encoder *encoder; 8679 8680 /* 8681 * We've not yet detected sink capabilities 8682 * (audio,infoframes,etc.) and thus we don't want to 8683 * force a full state recomputation yet. We want that to 8684 * happen only for the first real commit from userspace. 8685 * So preserve the inherited flag for the time being. 8686 */ 8687 crtc_state->inherited = true; 8688 8689 ret = drm_atomic_add_affected_planes(state, &crtc->base); 8690 if (ret) 8691 goto out; 8692 8693 /* 8694 * FIXME hack to force a LUT update to avoid the 8695 * plane update forcing the pipe gamma on without 8696 * having a proper LUT loaded. Remove once we 8697 * have readout for pipe gamma enable. 8698 */ 8699 crtc_state->uapi.color_mgmt_changed = true; 8700 8701 for_each_intel_encoder_mask(dev, encoder, 8702 crtc_state->uapi.encoder_mask) { 8703 if (encoder->initial_fastset_check && 8704 !encoder->initial_fastset_check(encoder, crtc_state)) { 8705 ret = drm_atomic_add_affected_connectors(state, 8706 &crtc->base); 8707 if (ret) 8708 goto out; 8709 } 8710 } 8711 } 8712 } 8713 8714 ret = drm_atomic_commit(state); 8715 8716 out: 8717 if (ret == -EDEADLK) { 8718 drm_atomic_state_clear(state); 8719 drm_modeset_backoff(&ctx); 8720 goto retry; 8721 } 8722 8723 drm_atomic_state_put(state); 8724 8725 drm_modeset_drop_locks(&ctx); 8726 drm_modeset_acquire_fini(&ctx); 8727 8728 return ret; 8729 } 8730 8731 static void intel_mode_config_init(struct drm_i915_private *i915) 8732 { 8733 struct drm_mode_config *mode_config = &i915->drm.mode_config; 8734 8735 drm_mode_config_init(&i915->drm); 8736 INIT_LIST_HEAD(&i915->global_obj_list); 8737 8738 mode_config->min_width = 0; 8739 mode_config->min_height = 0; 8740 8741 mode_config->preferred_depth = 24; 8742 mode_config->prefer_shadow = 1; 8743 8744 mode_config->funcs = &intel_mode_funcs; 8745 8746 mode_config->async_page_flip = HAS_ASYNC_FLIPS(i915); 8747 8748 /* 8749 * Maximum framebuffer dimensions, chosen to match 8750 * the maximum render engine surface size on gen4+. 8751 */ 8752 if (DISPLAY_VER(i915) >= 7) { 8753 mode_config->max_width = 16384; 8754 mode_config->max_height = 16384; 8755 } else if (DISPLAY_VER(i915) >= 4) { 8756 mode_config->max_width = 8192; 8757 mode_config->max_height = 8192; 8758 } else if (DISPLAY_VER(i915) == 3) { 8759 mode_config->max_width = 4096; 8760 mode_config->max_height = 4096; 8761 } else { 8762 mode_config->max_width = 2048; 8763 mode_config->max_height = 2048; 8764 } 8765 8766 if (IS_I845G(i915) || IS_I865G(i915)) { 8767 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512; 8768 mode_config->cursor_height = 1023; 8769 } else if (IS_I830(i915) || IS_I85X(i915) || 8770 IS_I915G(i915) || IS_I915GM(i915)) { 8771 mode_config->cursor_width = 64; 8772 mode_config->cursor_height = 64; 8773 } else { 8774 mode_config->cursor_width = 256; 8775 mode_config->cursor_height = 256; 8776 } 8777 } 8778 8779 static void intel_mode_config_cleanup(struct drm_i915_private *i915) 8780 { 8781 intel_atomic_global_obj_cleanup(i915); 8782 drm_mode_config_cleanup(&i915->drm); 8783 } 8784 8785 /* part #1: call before irq install */ 8786 int intel_modeset_init_noirq(struct drm_i915_private *i915) 8787 { 8788 int ret; 8789 8790 if (i915_inject_probe_failure(i915)) 8791 return -ENODEV; 8792 8793 if (HAS_DISPLAY(i915)) { 8794 ret = drm_vblank_init(&i915->drm, 8795 INTEL_NUM_PIPES(i915)); 8796 if (ret) 8797 return ret; 8798 } 8799 8800 intel_bios_init(i915); 8801 8802 ret = intel_vga_register(i915); 8803 if (ret) 8804 goto cleanup_bios; 8805 8806 /* FIXME: completely on the wrong abstraction layer */ 8807 intel_power_domains_init_hw(i915, false); 8808 8809 if (!HAS_DISPLAY(i915)) 8810 return 0; 8811 8812 intel_dmc_ucode_init(i915); 8813 8814 i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0); 8815 i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI | 8816 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE); 8817 8818 i915->window2_delay = 0; /* No DSB so no window2 delay */ 8819 8820 intel_mode_config_init(i915); 8821 8822 ret = intel_cdclk_init(i915); 8823 if (ret) 8824 goto cleanup_vga_client_pw_domain_dmc; 8825 8826 ret = intel_dbuf_init(i915); 8827 if (ret) 8828 goto cleanup_vga_client_pw_domain_dmc; 8829 8830 ret = intel_bw_init(i915); 8831 if (ret) 8832 goto cleanup_vga_client_pw_domain_dmc; 8833 8834 init_llist_head(&i915->atomic_helper.free_list); 8835 INIT_WORK(&i915->atomic_helper.free_work, 8836 intel_atomic_helper_free_state_worker); 8837 8838 intel_init_quirks(i915); 8839 8840 intel_fbc_init(i915); 8841 8842 return 0; 8843 8844 cleanup_vga_client_pw_domain_dmc: 8845 intel_dmc_ucode_fini(i915); 8846 intel_power_domains_driver_remove(i915); 8847 intel_vga_unregister(i915); 8848 cleanup_bios: 8849 intel_bios_driver_remove(i915); 8850 8851 return ret; 8852 } 8853 8854 /* part #2: call after irq install, but before gem init */ 8855 int intel_modeset_init_nogem(struct drm_i915_private *i915) 8856 { 8857 struct drm_device *dev = &i915->drm; 8858 enum pipe pipe; 8859 struct intel_crtc *crtc; 8860 int ret; 8861 8862 if (!HAS_DISPLAY(i915)) 8863 return 0; 8864 8865 intel_init_pm(i915); 8866 8867 intel_panel_sanitize_ssc(i915); 8868 8869 intel_pps_setup(i915); 8870 8871 intel_gmbus_setup(i915); 8872 8873 drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n", 8874 INTEL_NUM_PIPES(i915), 8875 INTEL_NUM_PIPES(i915) > 1 ? "s" : ""); 8876 8877 for_each_pipe(i915, pipe) { 8878 ret = intel_crtc_init(i915, pipe); 8879 if (ret) { 8880 intel_mode_config_cleanup(i915); 8881 return ret; 8882 } 8883 } 8884 8885 intel_plane_possible_crtcs_init(i915); 8886 intel_shared_dpll_init(i915); 8887 intel_fdi_pll_freq_update(i915); 8888 8889 intel_update_czclk(i915); 8890 intel_modeset_init_hw(i915); 8891 intel_dpll_update_ref_clks(i915); 8892 8893 intel_hdcp_component_init(i915); 8894 8895 if (i915->max_cdclk_freq == 0) 8896 intel_update_max_cdclk(i915); 8897 8898 /* 8899 * If the platform has HTI, we need to find out whether it has reserved 8900 * any display resources before we create our display outputs. 8901 */ 8902 if (INTEL_INFO(i915)->display.has_hti) 8903 i915->hti_state = intel_de_read(i915, HDPORT_STATE); 8904 8905 /* Just disable it once at startup */ 8906 intel_vga_disable(i915); 8907 intel_setup_outputs(i915); 8908 8909 drm_modeset_lock_all(dev); 8910 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx); 8911 intel_acpi_assign_connector_fwnodes(i915); 8912 drm_modeset_unlock_all(dev); 8913 8914 for_each_intel_crtc(dev, crtc) { 8915 if (!to_intel_crtc_state(crtc->base.state)->uapi.active) 8916 continue; 8917 intel_crtc_initial_plane_config(crtc); 8918 } 8919 8920 /* 8921 * Make sure hardware watermarks really match the state we read out. 8922 * Note that we need to do this after reconstructing the BIOS fb's 8923 * since the watermark calculation done here will use pstate->fb. 8924 */ 8925 if (!HAS_GMCH(i915)) 8926 sanitize_watermarks(i915); 8927 8928 return 0; 8929 } 8930 8931 /* part #3: call after gem init */ 8932 int intel_modeset_init(struct drm_i915_private *i915) 8933 { 8934 int ret; 8935 8936 if (!HAS_DISPLAY(i915)) 8937 return 0; 8938 8939 /* 8940 * Force all active planes to recompute their states. So that on 8941 * mode_setcrtc after probe, all the intel_plane_state variables 8942 * are already calculated and there is no assert_plane warnings 8943 * during bootup. 8944 */ 8945 ret = intel_initial_commit(&i915->drm); 8946 if (ret) 8947 drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret); 8948 8949 intel_overlay_setup(i915); 8950 8951 ret = intel_fbdev_init(&i915->drm); 8952 if (ret) 8953 return ret; 8954 8955 /* Only enable hotplug handling once the fbdev is fully set up. */ 8956 intel_hpd_init(i915); 8957 intel_hpd_poll_disable(i915); 8958 8959 intel_init_ipc(i915); 8960 8961 return 0; 8962 } 8963 8964 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 8965 { 8966 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 8967 /* 640x480@60Hz, ~25175 kHz */ 8968 struct dpll clock = { 8969 .m1 = 18, 8970 .m2 = 7, 8971 .p1 = 13, 8972 .p2 = 4, 8973 .n = 2, 8974 }; 8975 u32 dpll, fp; 8976 int i; 8977 8978 drm_WARN_ON(&dev_priv->drm, 8979 i9xx_calc_dpll_params(48000, &clock) != 25154); 8980 8981 drm_dbg_kms(&dev_priv->drm, 8982 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n", 8983 pipe_name(pipe), clock.vco, clock.dot); 8984 8985 fp = i9xx_dpll_compute_fp(&clock); 8986 dpll = DPLL_DVO_2X_MODE | 8987 DPLL_VGA_MODE_DIS | 8988 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | 8989 PLL_P2_DIVIDE_BY_4 | 8990 PLL_REF_INPUT_DREFCLK | 8991 DPLL_VCO_ENABLE; 8992 8993 intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16)); 8994 intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16)); 8995 intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16)); 8996 intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16)); 8997 intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16)); 8998 intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16)); 8999 intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1)); 9000 9001 intel_de_write(dev_priv, FP0(pipe), fp); 9002 intel_de_write(dev_priv, FP1(pipe), fp); 9003 9004 /* 9005 * Apparently we need to have VGA mode enabled prior to changing 9006 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 9007 * dividers, even though the register value does change. 9008 */ 9009 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); 9010 intel_de_write(dev_priv, DPLL(pipe), dpll); 9011 9012 /* Wait for the clocks to stabilize. */ 9013 intel_de_posting_read(dev_priv, DPLL(pipe)); 9014 udelay(150); 9015 9016 /* The pixel multiplier can only be updated once the 9017 * DPLL is enabled and the clocks are stable. 9018 * 9019 * So write it again. 9020 */ 9021 intel_de_write(dev_priv, DPLL(pipe), dpll); 9022 9023 /* We do this three times for luck */ 9024 for (i = 0; i < 3 ; i++) { 9025 intel_de_write(dev_priv, DPLL(pipe), dpll); 9026 intel_de_posting_read(dev_priv, DPLL(pipe)); 9027 udelay(150); /* wait for warmup */ 9028 } 9029 9030 intel_de_write(dev_priv, PIPECONF(pipe), PIPECONF_ENABLE); 9031 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 9032 9033 intel_wait_for_pipe_scanline_moving(crtc); 9034 } 9035 9036 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 9037 { 9038 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 9039 9040 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n", 9041 pipe_name(pipe)); 9042 9043 drm_WARN_ON(&dev_priv->drm, 9044 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE); 9045 drm_WARN_ON(&dev_priv->drm, 9046 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE); 9047 drm_WARN_ON(&dev_priv->drm, 9048 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE); 9049 drm_WARN_ON(&dev_priv->drm, 9050 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK); 9051 drm_WARN_ON(&dev_priv->drm, 9052 intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK); 9053 9054 intel_de_write(dev_priv, PIPECONF(pipe), 0); 9055 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 9056 9057 intel_wait_for_pipe_scanline_stopped(crtc); 9058 9059 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); 9060 intel_de_posting_read(dev_priv, DPLL(pipe)); 9061 } 9062 9063 static void 9064 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv) 9065 { 9066 struct intel_crtc *crtc; 9067 9068 if (DISPLAY_VER(dev_priv) >= 4) 9069 return; 9070 9071 for_each_intel_crtc(&dev_priv->drm, crtc) { 9072 struct intel_plane *plane = 9073 to_intel_plane(crtc->base.primary); 9074 struct intel_crtc *plane_crtc; 9075 enum pipe pipe; 9076 9077 if (!plane->get_hw_state(plane, &pipe)) 9078 continue; 9079 9080 if (pipe == crtc->pipe) 9081 continue; 9082 9083 drm_dbg_kms(&dev_priv->drm, 9084 "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n", 9085 plane->base.base.id, plane->base.name); 9086 9087 plane_crtc = intel_crtc_for_pipe(dev_priv, pipe); 9088 intel_plane_disable_noatomic(plane_crtc, plane); 9089 } 9090 } 9091 9092 static bool intel_crtc_has_encoders(struct intel_crtc *crtc) 9093 { 9094 struct drm_device *dev = crtc->base.dev; 9095 struct intel_encoder *encoder; 9096 9097 for_each_encoder_on_crtc(dev, &crtc->base, encoder) 9098 return true; 9099 9100 return false; 9101 } 9102 9103 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) 9104 { 9105 struct drm_device *dev = encoder->base.dev; 9106 struct intel_connector *connector; 9107 9108 for_each_connector_on_encoder(dev, &encoder->base, connector) 9109 return connector; 9110 9111 return NULL; 9112 } 9113 9114 static void intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state *crtc_state) 9115 { 9116 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 9117 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 9118 9119 if (!crtc_state->hw.active && !HAS_GMCH(i915)) 9120 return; 9121 9122 /* 9123 * We start out with underrun reporting disabled to avoid races. 9124 * For correct bookkeeping mark this on active crtcs. 9125 * 9126 * Also on gmch platforms we dont have any hardware bits to 9127 * disable the underrun reporting. Which means we need to start 9128 * out with underrun reporting disabled also on inactive pipes, 9129 * since otherwise we'll complain about the garbage we read when 9130 * e.g. coming up after runtime pm. 9131 * 9132 * No protection against concurrent access is required - at 9133 * worst a fifo underrun happens which also sets this to false. 9134 */ 9135 crtc->cpu_fifo_underrun_disabled = true; 9136 9137 /* 9138 * We track the PCH trancoder underrun reporting state 9139 * within the crtc. With crtc for pipe A housing the underrun 9140 * reporting state for PCH transcoder A, crtc for pipe B housing 9141 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, 9142 * and marking underrun reporting as disabled for the non-existing 9143 * PCH transcoders B and C would prevent enabling the south 9144 * error interrupt (see cpt_can_enable_serr_int()). 9145 */ 9146 if (intel_has_pch_trancoder(i915, crtc->pipe)) 9147 crtc->pch_fifo_underrun_disabled = true; 9148 } 9149 9150 static void intel_sanitize_crtc(struct intel_crtc *crtc, 9151 struct drm_modeset_acquire_ctx *ctx) 9152 { 9153 struct drm_device *dev = crtc->base.dev; 9154 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); 9155 9156 if (crtc_state->hw.active) { 9157 struct intel_plane *plane; 9158 9159 /* Disable everything but the primary plane */ 9160 for_each_intel_plane_on_crtc(dev, crtc, plane) { 9161 const struct intel_plane_state *plane_state = 9162 to_intel_plane_state(plane->base.state); 9163 9164 if (plane_state->uapi.visible && 9165 plane->base.type != DRM_PLANE_TYPE_PRIMARY) 9166 intel_plane_disable_noatomic(crtc, plane); 9167 } 9168 9169 /* Disable any background color/etc. set by the BIOS */ 9170 intel_color_commit_noarm(crtc_state); 9171 intel_color_commit_arm(crtc_state); 9172 } 9173 9174 /* Adjust the state of the output pipe according to whether we 9175 * have active connectors/encoders. */ 9176 if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) && 9177 !intel_crtc_is_bigjoiner_slave(crtc_state)) 9178 intel_crtc_disable_noatomic(crtc, ctx); 9179 } 9180 9181 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state) 9182 { 9183 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 9184 9185 /* 9186 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram 9187 * the hardware when a high res displays plugged in. DPLL P 9188 * divider is zero, and the pipe timings are bonkers. We'll 9189 * try to disable everything in that case. 9190 * 9191 * FIXME would be nice to be able to sanitize this state 9192 * without several WARNs, but for now let's take the easy 9193 * road. 9194 */ 9195 return IS_SANDYBRIDGE(dev_priv) && 9196 crtc_state->hw.active && 9197 crtc_state->shared_dpll && 9198 crtc_state->port_clock == 0; 9199 } 9200 9201 static void intel_sanitize_encoder(struct intel_encoder *encoder) 9202 { 9203 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 9204 struct intel_connector *connector; 9205 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 9206 struct intel_crtc_state *crtc_state = crtc ? 9207 to_intel_crtc_state(crtc->base.state) : NULL; 9208 9209 /* We need to check both for a crtc link (meaning that the 9210 * encoder is active and trying to read from a pipe) and the 9211 * pipe itself being active. */ 9212 bool has_active_crtc = crtc_state && 9213 crtc_state->hw.active; 9214 9215 if (crtc_state && has_bogus_dpll_config(crtc_state)) { 9216 drm_dbg_kms(&dev_priv->drm, 9217 "BIOS has misprogrammed the hardware. Disabling pipe %c\n", 9218 pipe_name(crtc->pipe)); 9219 has_active_crtc = false; 9220 } 9221 9222 connector = intel_encoder_find_connector(encoder); 9223 if (connector && !has_active_crtc) { 9224 drm_dbg_kms(&dev_priv->drm, 9225 "[ENCODER:%d:%s] has active connectors but no active pipe!\n", 9226 encoder->base.base.id, 9227 encoder->base.name); 9228 9229 /* Connector is active, but has no active pipe. This is 9230 * fallout from our resume register restoring. Disable 9231 * the encoder manually again. */ 9232 if (crtc_state) { 9233 struct drm_encoder *best_encoder; 9234 9235 drm_dbg_kms(&dev_priv->drm, 9236 "[ENCODER:%d:%s] manually disabled\n", 9237 encoder->base.base.id, 9238 encoder->base.name); 9239 9240 /* avoid oopsing in case the hooks consult best_encoder */ 9241 best_encoder = connector->base.state->best_encoder; 9242 connector->base.state->best_encoder = &encoder->base; 9243 9244 /* FIXME NULL atomic state passed! */ 9245 if (encoder->disable) 9246 encoder->disable(NULL, encoder, crtc_state, 9247 connector->base.state); 9248 if (encoder->post_disable) 9249 encoder->post_disable(NULL, encoder, crtc_state, 9250 connector->base.state); 9251 9252 connector->base.state->best_encoder = best_encoder; 9253 } 9254 encoder->base.crtc = NULL; 9255 9256 /* Inconsistent output/port/pipe state happens presumably due to 9257 * a bug in one of the get_hw_state functions. Or someplace else 9258 * in our code, like the register restore mess on resume. Clamp 9259 * things to off as a safer default. */ 9260 9261 connector->base.dpms = DRM_MODE_DPMS_OFF; 9262 connector->base.encoder = NULL; 9263 } 9264 9265 /* notify opregion of the sanitized encoder state */ 9266 intel_opregion_notify_encoder(encoder, connector && has_active_crtc); 9267 9268 if (HAS_DDI(dev_priv)) 9269 intel_ddi_sanitize_encoder_pll_mapping(encoder); 9270 } 9271 9272 /* FIXME read out full plane state for all planes */ 9273 static void readout_plane_state(struct drm_i915_private *dev_priv) 9274 { 9275 struct intel_plane *plane; 9276 struct intel_crtc *crtc; 9277 9278 for_each_intel_plane(&dev_priv->drm, plane) { 9279 struct intel_plane_state *plane_state = 9280 to_intel_plane_state(plane->base.state); 9281 struct intel_crtc_state *crtc_state; 9282 enum pipe pipe = PIPE_A; 9283 bool visible; 9284 9285 visible = plane->get_hw_state(plane, &pipe); 9286 9287 crtc = intel_crtc_for_pipe(dev_priv, pipe); 9288 crtc_state = to_intel_crtc_state(crtc->base.state); 9289 9290 intel_set_plane_visible(crtc_state, plane_state, visible); 9291 9292 drm_dbg_kms(&dev_priv->drm, 9293 "[PLANE:%d:%s] hw state readout: %s, pipe %c\n", 9294 plane->base.base.id, plane->base.name, 9295 str_enabled_disabled(visible), pipe_name(pipe)); 9296 } 9297 9298 for_each_intel_crtc(&dev_priv->drm, crtc) { 9299 struct intel_crtc_state *crtc_state = 9300 to_intel_crtc_state(crtc->base.state); 9301 9302 fixup_plane_bitmasks(crtc_state); 9303 } 9304 } 9305 9306 static void intel_modeset_readout_hw_state(struct drm_device *dev) 9307 { 9308 struct drm_i915_private *dev_priv = to_i915(dev); 9309 struct intel_cdclk_state *cdclk_state = 9310 to_intel_cdclk_state(dev_priv->cdclk.obj.state); 9311 struct intel_dbuf_state *dbuf_state = 9312 to_intel_dbuf_state(dev_priv->dbuf.obj.state); 9313 enum pipe pipe; 9314 struct intel_crtc *crtc; 9315 struct intel_encoder *encoder; 9316 struct intel_connector *connector; 9317 struct drm_connector_list_iter conn_iter; 9318 u8 active_pipes = 0; 9319 9320 for_each_intel_crtc(dev, crtc) { 9321 struct intel_crtc_state *crtc_state = 9322 to_intel_crtc_state(crtc->base.state); 9323 9324 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi); 9325 intel_crtc_free_hw_state(crtc_state); 9326 intel_crtc_state_reset(crtc_state, crtc); 9327 9328 intel_crtc_get_pipe_config(crtc_state); 9329 9330 crtc_state->hw.enable = crtc_state->hw.active; 9331 9332 crtc->base.enabled = crtc_state->hw.enable; 9333 crtc->active = crtc_state->hw.active; 9334 9335 if (crtc_state->hw.active) 9336 active_pipes |= BIT(crtc->pipe); 9337 9338 drm_dbg_kms(&dev_priv->drm, 9339 "[CRTC:%d:%s] hw state readout: %s\n", 9340 crtc->base.base.id, crtc->base.name, 9341 str_enabled_disabled(crtc_state->hw.active)); 9342 } 9343 9344 cdclk_state->active_pipes = dbuf_state->active_pipes = active_pipes; 9345 9346 readout_plane_state(dev_priv); 9347 9348 for_each_intel_encoder(dev, encoder) { 9349 struct intel_crtc_state *crtc_state = NULL; 9350 9351 pipe = 0; 9352 9353 if (encoder->get_hw_state(encoder, &pipe)) { 9354 crtc = intel_crtc_for_pipe(dev_priv, pipe); 9355 crtc_state = to_intel_crtc_state(crtc->base.state); 9356 9357 encoder->base.crtc = &crtc->base; 9358 intel_encoder_get_config(encoder, crtc_state); 9359 9360 /* read out to slave crtc as well for bigjoiner */ 9361 if (crtc_state->bigjoiner_pipes) { 9362 struct intel_crtc *slave_crtc; 9363 9364 /* encoder should read be linked to bigjoiner master */ 9365 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 9366 9367 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc, 9368 intel_crtc_bigjoiner_slave_pipes(crtc_state)) { 9369 struct intel_crtc_state *slave_crtc_state; 9370 9371 slave_crtc_state = to_intel_crtc_state(slave_crtc->base.state); 9372 intel_encoder_get_config(encoder, slave_crtc_state); 9373 } 9374 } 9375 } else { 9376 encoder->base.crtc = NULL; 9377 } 9378 9379 if (encoder->sync_state) 9380 encoder->sync_state(encoder, crtc_state); 9381 9382 drm_dbg_kms(&dev_priv->drm, 9383 "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", 9384 encoder->base.base.id, encoder->base.name, 9385 str_enabled_disabled(encoder->base.crtc), 9386 pipe_name(pipe)); 9387 } 9388 9389 intel_dpll_readout_hw_state(dev_priv); 9390 9391 drm_connector_list_iter_begin(dev, &conn_iter); 9392 for_each_intel_connector_iter(connector, &conn_iter) { 9393 if (connector->get_hw_state(connector)) { 9394 struct intel_crtc_state *crtc_state; 9395 struct intel_crtc *crtc; 9396 9397 connector->base.dpms = DRM_MODE_DPMS_ON; 9398 9399 encoder = intel_attached_encoder(connector); 9400 connector->base.encoder = &encoder->base; 9401 9402 crtc = to_intel_crtc(encoder->base.crtc); 9403 crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL; 9404 9405 if (crtc_state && crtc_state->hw.active) { 9406 /* 9407 * This has to be done during hardware readout 9408 * because anything calling .crtc_disable may 9409 * rely on the connector_mask being accurate. 9410 */ 9411 crtc_state->uapi.connector_mask |= 9412 drm_connector_mask(&connector->base); 9413 crtc_state->uapi.encoder_mask |= 9414 drm_encoder_mask(&encoder->base); 9415 } 9416 } else { 9417 connector->base.dpms = DRM_MODE_DPMS_OFF; 9418 connector->base.encoder = NULL; 9419 } 9420 drm_dbg_kms(&dev_priv->drm, 9421 "[CONNECTOR:%d:%s] hw state readout: %s\n", 9422 connector->base.base.id, connector->base.name, 9423 str_enabled_disabled(connector->base.encoder)); 9424 } 9425 drm_connector_list_iter_end(&conn_iter); 9426 9427 for_each_intel_crtc(dev, crtc) { 9428 struct intel_bw_state *bw_state = 9429 to_intel_bw_state(dev_priv->bw_obj.state); 9430 struct intel_crtc_state *crtc_state = 9431 to_intel_crtc_state(crtc->base.state); 9432 struct intel_plane *plane; 9433 int min_cdclk = 0; 9434 9435 if (crtc_state->hw.active) { 9436 /* 9437 * The initial mode needs to be set in order to keep 9438 * the atomic core happy. It wants a valid mode if the 9439 * crtc's enabled, so we do the above call. 9440 * 9441 * But we don't set all the derived state fully, hence 9442 * set a flag to indicate that a full recalculation is 9443 * needed on the next commit. 9444 */ 9445 crtc_state->inherited = true; 9446 9447 intel_crtc_update_active_timings(crtc_state); 9448 9449 intel_crtc_copy_hw_to_uapi_state(crtc_state); 9450 } 9451 9452 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 9453 const struct intel_plane_state *plane_state = 9454 to_intel_plane_state(plane->base.state); 9455 9456 /* 9457 * FIXME don't have the fb yet, so can't 9458 * use intel_plane_data_rate() :( 9459 */ 9460 if (plane_state->uapi.visible) 9461 crtc_state->data_rate[plane->id] = 9462 4 * crtc_state->pixel_rate; 9463 /* 9464 * FIXME don't have the fb yet, so can't 9465 * use plane->min_cdclk() :( 9466 */ 9467 if (plane_state->uapi.visible && plane->min_cdclk) { 9468 if (crtc_state->double_wide || DISPLAY_VER(dev_priv) >= 10) 9469 crtc_state->min_cdclk[plane->id] = 9470 DIV_ROUND_UP(crtc_state->pixel_rate, 2); 9471 else 9472 crtc_state->min_cdclk[plane->id] = 9473 crtc_state->pixel_rate; 9474 } 9475 drm_dbg_kms(&dev_priv->drm, 9476 "[PLANE:%d:%s] min_cdclk %d kHz\n", 9477 plane->base.base.id, plane->base.name, 9478 crtc_state->min_cdclk[plane->id]); 9479 } 9480 9481 if (crtc_state->hw.active) { 9482 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); 9483 if (drm_WARN_ON(dev, min_cdclk < 0)) 9484 min_cdclk = 0; 9485 } 9486 9487 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; 9488 cdclk_state->min_voltage_level[crtc->pipe] = 9489 crtc_state->min_voltage_level; 9490 9491 intel_bw_crtc_update(bw_state, crtc_state); 9492 } 9493 } 9494 9495 static void 9496 get_encoder_power_domains(struct drm_i915_private *dev_priv) 9497 { 9498 struct intel_encoder *encoder; 9499 9500 for_each_intel_encoder(&dev_priv->drm, encoder) { 9501 struct intel_crtc_state *crtc_state; 9502 9503 if (!encoder->get_power_domains) 9504 continue; 9505 9506 /* 9507 * MST-primary and inactive encoders don't have a crtc state 9508 * and neither of these require any power domain references. 9509 */ 9510 if (!encoder->base.crtc) 9511 continue; 9512 9513 crtc_state = to_intel_crtc_state(encoder->base.crtc->state); 9514 encoder->get_power_domains(encoder, crtc_state); 9515 } 9516 } 9517 9518 static void intel_early_display_was(struct drm_i915_private *dev_priv) 9519 { 9520 /* 9521 * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl 9522 * Also known as Wa_14010480278. 9523 */ 9524 if (IS_DISPLAY_VER(dev_priv, 10, 12)) 9525 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0, 9526 intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS); 9527 9528 if (IS_HASWELL(dev_priv)) { 9529 /* 9530 * WaRsPkgCStateDisplayPMReq:hsw 9531 * System hang if this isn't done before disabling all planes! 9532 */ 9533 intel_de_write(dev_priv, CHICKEN_PAR1_1, 9534 intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); 9535 } 9536 9537 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) { 9538 /* Display WA #1142:kbl,cfl,cml */ 9539 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 9540 KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22); 9541 intel_de_rmw(dev_priv, CHICKEN_MISC_2, 9542 KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14, 9543 KBL_ARB_FILL_SPARE_14); 9544 } 9545 } 9546 9547 9548 /* Scan out the current hw modeset state, 9549 * and sanitizes it to the current state 9550 */ 9551 static void 9552 intel_modeset_setup_hw_state(struct drm_device *dev, 9553 struct drm_modeset_acquire_ctx *ctx) 9554 { 9555 struct drm_i915_private *dev_priv = to_i915(dev); 9556 struct intel_encoder *encoder; 9557 struct intel_crtc *crtc; 9558 intel_wakeref_t wakeref; 9559 9560 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 9561 9562 intel_early_display_was(dev_priv); 9563 intel_modeset_readout_hw_state(dev); 9564 9565 /* HW state is read out, now we need to sanitize this mess. */ 9566 get_encoder_power_domains(dev_priv); 9567 9568 intel_pch_sanitize(dev_priv); 9569 9570 /* 9571 * intel_sanitize_plane_mapping() may need to do vblank 9572 * waits, so we need vblank interrupts restored beforehand. 9573 */ 9574 for_each_intel_crtc(&dev_priv->drm, crtc) { 9575 struct intel_crtc_state *crtc_state = 9576 to_intel_crtc_state(crtc->base.state); 9577 9578 intel_sanitize_fifo_underrun_reporting(crtc_state); 9579 9580 drm_crtc_vblank_reset(&crtc->base); 9581 9582 if (crtc_state->hw.active) 9583 intel_crtc_vblank_on(crtc_state); 9584 } 9585 9586 intel_fbc_sanitize(dev_priv); 9587 9588 intel_sanitize_plane_mapping(dev_priv); 9589 9590 for_each_intel_encoder(dev, encoder) 9591 intel_sanitize_encoder(encoder); 9592 9593 for_each_intel_crtc(&dev_priv->drm, crtc) { 9594 struct intel_crtc_state *crtc_state = 9595 to_intel_crtc_state(crtc->base.state); 9596 9597 intel_sanitize_crtc(crtc, ctx); 9598 intel_crtc_state_dump(crtc_state, NULL, "setup_hw_state"); 9599 } 9600 9601 intel_modeset_update_connector_atomic_state(dev); 9602 9603 intel_dpll_sanitize_state(dev_priv); 9604 9605 if (IS_G4X(dev_priv)) { 9606 g4x_wm_get_hw_state(dev_priv); 9607 g4x_wm_sanitize(dev_priv); 9608 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 9609 vlv_wm_get_hw_state(dev_priv); 9610 vlv_wm_sanitize(dev_priv); 9611 } else if (DISPLAY_VER(dev_priv) >= 9) { 9612 skl_wm_get_hw_state(dev_priv); 9613 skl_wm_sanitize(dev_priv); 9614 } else if (HAS_PCH_SPLIT(dev_priv)) { 9615 ilk_wm_get_hw_state(dev_priv); 9616 } 9617 9618 for_each_intel_crtc(dev, crtc) { 9619 struct intel_crtc_state *crtc_state = 9620 to_intel_crtc_state(crtc->base.state); 9621 struct intel_power_domain_mask put_domains; 9622 9623 modeset_get_crtc_power_domains(crtc_state, &put_domains); 9624 if (drm_WARN_ON(dev, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM))) 9625 modeset_put_crtc_power_domains(crtc, &put_domains); 9626 } 9627 9628 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref); 9629 9630 intel_power_domains_sanitize_state(dev_priv); 9631 } 9632 9633 void intel_display_resume(struct drm_device *dev) 9634 { 9635 struct drm_i915_private *i915 = to_i915(dev); 9636 struct drm_atomic_state *state = i915->modeset_restore_state; 9637 struct drm_modeset_acquire_ctx ctx; 9638 int ret; 9639 9640 if (!HAS_DISPLAY(i915)) 9641 return; 9642 9643 i915->modeset_restore_state = NULL; 9644 if (state) 9645 state->acquire_ctx = &ctx; 9646 9647 drm_modeset_acquire_init(&ctx, 0); 9648 9649 while (1) { 9650 ret = drm_modeset_lock_all_ctx(dev, &ctx); 9651 if (ret != -EDEADLK) 9652 break; 9653 9654 drm_modeset_backoff(&ctx); 9655 } 9656 9657 if (!ret) 9658 ret = __intel_display_resume(i915, state, &ctx); 9659 9660 intel_enable_ipc(i915); 9661 drm_modeset_drop_locks(&ctx); 9662 drm_modeset_acquire_fini(&ctx); 9663 9664 if (ret) 9665 drm_err(&i915->drm, 9666 "Restoring old state failed with %i\n", ret); 9667 if (state) 9668 drm_atomic_state_put(state); 9669 } 9670 9671 static void intel_hpd_poll_fini(struct drm_i915_private *i915) 9672 { 9673 struct intel_connector *connector; 9674 struct drm_connector_list_iter conn_iter; 9675 9676 /* Kill all the work that may have been queued by hpd. */ 9677 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 9678 for_each_intel_connector_iter(connector, &conn_iter) { 9679 if (connector->modeset_retry_work.func) 9680 cancel_work_sync(&connector->modeset_retry_work); 9681 if (connector->hdcp.shim) { 9682 cancel_delayed_work_sync(&connector->hdcp.check_work); 9683 cancel_work_sync(&connector->hdcp.prop_work); 9684 } 9685 } 9686 drm_connector_list_iter_end(&conn_iter); 9687 } 9688 9689 /* part #1: call before irq uninstall */ 9690 void intel_modeset_driver_remove(struct drm_i915_private *i915) 9691 { 9692 if (!HAS_DISPLAY(i915)) 9693 return; 9694 9695 flush_workqueue(i915->flip_wq); 9696 flush_workqueue(i915->modeset_wq); 9697 9698 flush_work(&i915->atomic_helper.free_work); 9699 drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list)); 9700 } 9701 9702 /* part #2: call after irq uninstall */ 9703 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915) 9704 { 9705 if (!HAS_DISPLAY(i915)) 9706 return; 9707 9708 /* 9709 * Due to the hpd irq storm handling the hotplug work can re-arm the 9710 * poll handlers. Hence disable polling after hpd handling is shut down. 9711 */ 9712 intel_hpd_poll_fini(i915); 9713 9714 /* 9715 * MST topology needs to be suspended so we don't have any calls to 9716 * fbdev after it's finalized. MST will be destroyed later as part of 9717 * drm_mode_config_cleanup() 9718 */ 9719 intel_dp_mst_suspend(i915); 9720 9721 /* poll work can call into fbdev, hence clean that up afterwards */ 9722 intel_fbdev_fini(i915); 9723 9724 intel_unregister_dsm_handler(); 9725 9726 /* flush any delayed tasks or pending work */ 9727 flush_scheduled_work(); 9728 9729 intel_hdcp_component_fini(i915); 9730 9731 intel_mode_config_cleanup(i915); 9732 9733 intel_overlay_cleanup(i915); 9734 9735 intel_gmbus_teardown(i915); 9736 9737 destroy_workqueue(i915->flip_wq); 9738 destroy_workqueue(i915->modeset_wq); 9739 9740 intel_fbc_cleanup(i915); 9741 } 9742 9743 /* part #3: call after gem init */ 9744 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915) 9745 { 9746 intel_dmc_ucode_fini(i915); 9747 9748 intel_power_domains_driver_remove(i915); 9749 9750 intel_vga_unregister(i915); 9751 9752 intel_bios_driver_remove(i915); 9753 } 9754 9755 bool intel_modeset_probe_defer(struct pci_dev *pdev) 9756 { 9757 struct drm_privacy_screen *privacy_screen; 9758 9759 /* 9760 * apple-gmux is needed on dual GPU MacBook Pro 9761 * to probe the panel if we're the inactive GPU. 9762 */ 9763 if (vga_switcheroo_client_probe_defer(pdev)) 9764 return true; 9765 9766 /* If the LCD panel has a privacy-screen, wait for it */ 9767 privacy_screen = drm_privacy_screen_get(&pdev->dev, NULL); 9768 if (IS_ERR(privacy_screen) && PTR_ERR(privacy_screen) == -EPROBE_DEFER) 9769 return true; 9770 9771 drm_privacy_screen_put(privacy_screen); 9772 9773 return false; 9774 } 9775 9776 void intel_display_driver_register(struct drm_i915_private *i915) 9777 { 9778 if (!HAS_DISPLAY(i915)) 9779 return; 9780 9781 intel_display_debugfs_register(i915); 9782 9783 /* Must be done after probing outputs */ 9784 intel_opregion_register(i915); 9785 acpi_video_register(); 9786 9787 intel_audio_init(i915); 9788 9789 /* 9790 * Some ports require correctly set-up hpd registers for 9791 * detection to work properly (leading to ghost connected 9792 * connector status), e.g. VGA on gm45. Hence we can only set 9793 * up the initial fbdev config after hpd irqs are fully 9794 * enabled. We do it last so that the async config cannot run 9795 * before the connectors are registered. 9796 */ 9797 intel_fbdev_initial_config_async(&i915->drm); 9798 9799 /* 9800 * We need to coordinate the hotplugs with the asynchronous 9801 * fbdev configuration, for which we use the 9802 * fbdev->async_cookie. 9803 */ 9804 drm_kms_helper_poll_init(&i915->drm); 9805 } 9806 9807 void intel_display_driver_unregister(struct drm_i915_private *i915) 9808 { 9809 if (!HAS_DISPLAY(i915)) 9810 return; 9811 9812 intel_fbdev_unregister(i915); 9813 intel_audio_deinit(i915); 9814 9815 /* 9816 * After flushing the fbdev (incl. a late async config which 9817 * will have delayed queuing of a hotplug event), then flush 9818 * the hotplug events. 9819 */ 9820 drm_kms_helper_poll_fini(&i915->drm); 9821 drm_atomic_helper_shutdown(&i915->drm); 9822 9823 acpi_video_unregister(); 9824 intel_opregion_unregister(i915); 9825 } 9826 9827 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915) 9828 { 9829 return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915); 9830 } 9831