1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <acpi/video.h> 28 #include <linux/i2c.h> 29 #include <linux/input.h> 30 #include <linux/intel-iommu.h> 31 #include <linux/kernel.h> 32 #include <linux/module.h> 33 #include <linux/dma-resv.h> 34 #include <linux/slab.h> 35 #include <linux/string_helpers.h> 36 #include <linux/vga_switcheroo.h> 37 38 #include <drm/drm_atomic.h> 39 #include <drm/drm_atomic_helper.h> 40 #include <drm/drm_atomic_uapi.h> 41 #include <drm/drm_damage_helper.h> 42 #include <drm/dp/drm_dp_helper.h> 43 #include <drm/drm_edid.h> 44 #include <drm/drm_fourcc.h> 45 #include <drm/drm_plane_helper.h> 46 #include <drm/drm_privacy_screen_consumer.h> 47 #include <drm/drm_probe_helper.h> 48 #include <drm/drm_rect.h> 49 50 #include "display/intel_audio.h" 51 #include "display/intel_crt.h" 52 #include "display/intel_ddi.h" 53 #include "display/intel_display_debugfs.h" 54 #include "display/intel_dp.h" 55 #include "display/intel_dp_mst.h" 56 #include "display/intel_dpll.h" 57 #include "display/intel_dpll_mgr.h" 58 #include "display/intel_drrs.h" 59 #include "display/intel_dsi.h" 60 #include "display/intel_dvo.h" 61 #include "display/intel_fb.h" 62 #include "display/intel_gmbus.h" 63 #include "display/intel_hdmi.h" 64 #include "display/intel_lvds.h" 65 #include "display/intel_sdvo.h" 66 #include "display/intel_snps_phy.h" 67 #include "display/intel_tv.h" 68 #include "display/intel_vdsc.h" 69 #include "display/intel_vrr.h" 70 71 #include "gem/i915_gem_lmem.h" 72 #include "gem/i915_gem_object.h" 73 74 #include "gt/gen8_ppgtt.h" 75 76 #include "g4x_dp.h" 77 #include "g4x_hdmi.h" 78 #include "hsw_ips.h" 79 #include "i915_drv.h" 80 #include "icl_dsi.h" 81 #include "intel_acpi.h" 82 #include "intel_atomic.h" 83 #include "intel_atomic_plane.h" 84 #include "intel_bw.h" 85 #include "intel_cdclk.h" 86 #include "intel_color.h" 87 #include "intel_crtc.h" 88 #include "intel_de.h" 89 #include "intel_display_types.h" 90 #include "intel_dmc.h" 91 #include "intel_dp_link_training.h" 92 #include "intel_dpt.h" 93 #include "intel_fbc.h" 94 #include "intel_fbdev.h" 95 #include "intel_fdi.h" 96 #include "intel_fifo_underrun.h" 97 #include "intel_frontbuffer.h" 98 #include "intel_hdcp.h" 99 #include "intel_hotplug.h" 100 #include "intel_overlay.h" 101 #include "intel_panel.h" 102 #include "intel_pch_display.h" 103 #include "intel_pch_refclk.h" 104 #include "intel_pcode.h" 105 #include "intel_pipe_crc.h" 106 #include "intel_plane_initial.h" 107 #include "intel_pm.h" 108 #include "intel_pps.h" 109 #include "intel_psr.h" 110 #include "intel_quirks.h" 111 #include "intel_sprite.h" 112 #include "intel_tc.h" 113 #include "intel_vga.h" 114 #include "i9xx_plane.h" 115 #include "skl_scaler.h" 116 #include "skl_universal_plane.h" 117 #include "vlv_dsi.h" 118 #include "vlv_dsi_pll.h" 119 #include "vlv_dsi_regs.h" 120 #include "vlv_sideband.h" 121 122 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state); 123 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state); 124 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state); 125 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state); 126 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state); 127 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state); 128 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state); 129 static void intel_modeset_setup_hw_state(struct drm_device *dev, 130 struct drm_modeset_acquire_ctx *ctx); 131 132 /** 133 * intel_update_watermarks - update FIFO watermark values based on current modes 134 * @dev_priv: i915 device 135 * 136 * Calculate watermark values for the various WM regs based on current mode 137 * and plane configuration. 138 * 139 * There are several cases to deal with here: 140 * - normal (i.e. non-self-refresh) 141 * - self-refresh (SR) mode 142 * - lines are large relative to FIFO size (buffer can hold up to 2) 143 * - lines are small relative to FIFO size (buffer can hold more than 2 144 * lines), so need to account for TLB latency 145 * 146 * The normal calculation is: 147 * watermark = dotclock * bytes per pixel * latency 148 * where latency is platform & configuration dependent (we assume pessimal 149 * values here). 150 * 151 * The SR calculation is: 152 * watermark = (trunc(latency/line time)+1) * surface width * 153 * bytes per pixel 154 * where 155 * line time = htotal / dotclock 156 * surface width = hdisplay for normal plane and 64 for cursor 157 * and latency is assumed to be high, as above. 158 * 159 * The final value programmed to the register should always be rounded up, 160 * and include an extra 2 entries to account for clock crossings. 161 * 162 * We don't use the sprite, so we can ignore that. And on Crestline we have 163 * to set the non-SR watermarks to 8. 164 */ 165 static void intel_update_watermarks(struct drm_i915_private *dev_priv) 166 { 167 if (dev_priv->wm_disp->update_wm) 168 dev_priv->wm_disp->update_wm(dev_priv); 169 } 170 171 static int intel_compute_pipe_wm(struct intel_atomic_state *state, 172 struct intel_crtc *crtc) 173 { 174 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 175 if (dev_priv->wm_disp->compute_pipe_wm) 176 return dev_priv->wm_disp->compute_pipe_wm(state, crtc); 177 return 0; 178 } 179 180 static int intel_compute_intermediate_wm(struct intel_atomic_state *state, 181 struct intel_crtc *crtc) 182 { 183 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 184 if (!dev_priv->wm_disp->compute_intermediate_wm) 185 return 0; 186 if (drm_WARN_ON(&dev_priv->drm, 187 !dev_priv->wm_disp->compute_pipe_wm)) 188 return 0; 189 return dev_priv->wm_disp->compute_intermediate_wm(state, crtc); 190 } 191 192 static bool intel_initial_watermarks(struct intel_atomic_state *state, 193 struct intel_crtc *crtc) 194 { 195 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 196 if (dev_priv->wm_disp->initial_watermarks) { 197 dev_priv->wm_disp->initial_watermarks(state, crtc); 198 return true; 199 } 200 return false; 201 } 202 203 static void intel_atomic_update_watermarks(struct intel_atomic_state *state, 204 struct intel_crtc *crtc) 205 { 206 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 207 if (dev_priv->wm_disp->atomic_update_watermarks) 208 dev_priv->wm_disp->atomic_update_watermarks(state, crtc); 209 } 210 211 static void intel_optimize_watermarks(struct intel_atomic_state *state, 212 struct intel_crtc *crtc) 213 { 214 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 215 if (dev_priv->wm_disp->optimize_watermarks) 216 dev_priv->wm_disp->optimize_watermarks(state, crtc); 217 } 218 219 static int intel_compute_global_watermarks(struct intel_atomic_state *state) 220 { 221 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 222 if (dev_priv->wm_disp->compute_global_watermarks) 223 return dev_priv->wm_disp->compute_global_watermarks(state); 224 return 0; 225 } 226 227 /* returns HPLL frequency in kHz */ 228 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) 229 { 230 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; 231 232 /* Obtain SKU information */ 233 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & 234 CCK_FUSE_HPLL_FREQ_MASK; 235 236 return vco_freq[hpll_freq] * 1000; 237 } 238 239 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 240 const char *name, u32 reg, int ref_freq) 241 { 242 u32 val; 243 int divider; 244 245 val = vlv_cck_read(dev_priv, reg); 246 divider = val & CCK_FREQUENCY_VALUES; 247 248 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != 249 (divider << CCK_FREQUENCY_STATUS_SHIFT), 250 "%s change in progress\n", name); 251 252 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); 253 } 254 255 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 256 const char *name, u32 reg) 257 { 258 int hpll; 259 260 vlv_cck_get(dev_priv); 261 262 if (dev_priv->hpll_freq == 0) 263 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); 264 265 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); 266 267 vlv_cck_put(dev_priv); 268 269 return hpll; 270 } 271 272 static void intel_update_czclk(struct drm_i915_private *dev_priv) 273 { 274 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) 275 return; 276 277 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", 278 CCK_CZ_CLOCK_CONTROL); 279 280 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", 281 dev_priv->czclk_freq); 282 } 283 284 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state) 285 { 286 return (crtc_state->active_planes & 287 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0; 288 } 289 290 /* WA Display #0827: Gen9:all */ 291 static void 292 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) 293 { 294 if (enable) 295 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 296 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS); 297 else 298 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 299 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS)); 300 } 301 302 /* Wa_2006604312:icl,ehl */ 303 static void 304 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 305 bool enable) 306 { 307 if (enable) 308 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 309 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS); 310 else 311 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 312 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS); 313 } 314 315 /* Wa_1604331009:icl,jsl,ehl */ 316 static void 317 icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 318 bool enable) 319 { 320 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), CURSOR_GATING_DIS, 321 enable ? CURSOR_GATING_DIS : 0); 322 } 323 324 static bool 325 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state) 326 { 327 return crtc_state->master_transcoder != INVALID_TRANSCODER; 328 } 329 330 static bool 331 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state) 332 { 333 return crtc_state->sync_mode_slaves_mask != 0; 334 } 335 336 bool 337 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state) 338 { 339 return is_trans_port_sync_master(crtc_state) || 340 is_trans_port_sync_slave(crtc_state); 341 } 342 343 static enum pipe bigjoiner_master_pipe(const struct intel_crtc_state *crtc_state) 344 { 345 return ffs(crtc_state->bigjoiner_pipes) - 1; 346 } 347 348 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state) 349 { 350 if (crtc_state->bigjoiner_pipes) 351 return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state)); 352 else 353 return 0; 354 } 355 356 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state) 357 { 358 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 359 360 return crtc_state->bigjoiner_pipes && 361 crtc->pipe != bigjoiner_master_pipe(crtc_state); 362 } 363 364 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state) 365 { 366 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 367 368 return crtc_state->bigjoiner_pipes && 369 crtc->pipe == bigjoiner_master_pipe(crtc_state); 370 } 371 372 static int intel_bigjoiner_num_pipes(const struct intel_crtc_state *crtc_state) 373 { 374 return hweight8(crtc_state->bigjoiner_pipes); 375 } 376 377 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state) 378 { 379 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 380 381 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 382 return intel_crtc_for_pipe(i915, bigjoiner_master_pipe(crtc_state)); 383 else 384 return to_intel_crtc(crtc_state->uapi.crtc); 385 } 386 387 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv, 388 enum pipe pipe) 389 { 390 i915_reg_t reg = PIPEDSL(pipe); 391 u32 line1, line2; 392 393 line1 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK; 394 msleep(5); 395 line2 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK; 396 397 return line1 != line2; 398 } 399 400 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state) 401 { 402 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 403 enum pipe pipe = crtc->pipe; 404 405 /* Wait for the display line to settle/start moving */ 406 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100)) 407 drm_err(&dev_priv->drm, 408 "pipe %c scanline %s wait timed out\n", 409 pipe_name(pipe), str_on_off(state)); 410 } 411 412 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc) 413 { 414 wait_for_pipe_scanline_moving(crtc, false); 415 } 416 417 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc) 418 { 419 wait_for_pipe_scanline_moving(crtc, true); 420 } 421 422 static void 423 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) 424 { 425 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 426 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 427 428 if (DISPLAY_VER(dev_priv) >= 4) { 429 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 430 431 /* Wait for the Pipe State to go off */ 432 if (intel_de_wait_for_clear(dev_priv, PIPECONF(cpu_transcoder), 433 PIPECONF_STATE_ENABLE, 100)) 434 drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n"); 435 } else { 436 intel_wait_for_pipe_scanline_stopped(crtc); 437 } 438 } 439 440 void assert_transcoder(struct drm_i915_private *dev_priv, 441 enum transcoder cpu_transcoder, bool state) 442 { 443 bool cur_state; 444 enum intel_display_power_domain power_domain; 445 intel_wakeref_t wakeref; 446 447 /* we keep both pipes enabled on 830 */ 448 if (IS_I830(dev_priv)) 449 state = true; 450 451 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 452 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 453 if (wakeref) { 454 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); 455 cur_state = !!(val & PIPECONF_ENABLE); 456 457 intel_display_power_put(dev_priv, power_domain, wakeref); 458 } else { 459 cur_state = false; 460 } 461 462 I915_STATE_WARN(cur_state != state, 463 "transcoder %s assertion failure (expected %s, current %s)\n", 464 transcoder_name(cpu_transcoder), 465 str_on_off(state), str_on_off(cur_state)); 466 } 467 468 static void assert_plane(struct intel_plane *plane, bool state) 469 { 470 enum pipe pipe; 471 bool cur_state; 472 473 cur_state = plane->get_hw_state(plane, &pipe); 474 475 I915_STATE_WARN(cur_state != state, 476 "%s assertion failure (expected %s, current %s)\n", 477 plane->base.name, str_on_off(state), 478 str_on_off(cur_state)); 479 } 480 481 #define assert_plane_enabled(p) assert_plane(p, true) 482 #define assert_plane_disabled(p) assert_plane(p, false) 483 484 static void assert_planes_disabled(struct intel_crtc *crtc) 485 { 486 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 487 struct intel_plane *plane; 488 489 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) 490 assert_plane_disabled(plane); 491 } 492 493 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 494 struct intel_digital_port *dig_port, 495 unsigned int expected_mask) 496 { 497 u32 port_mask; 498 i915_reg_t dpll_reg; 499 500 switch (dig_port->base.port) { 501 case PORT_B: 502 port_mask = DPLL_PORTB_READY_MASK; 503 dpll_reg = DPLL(0); 504 break; 505 case PORT_C: 506 port_mask = DPLL_PORTC_READY_MASK; 507 dpll_reg = DPLL(0); 508 expected_mask <<= 4; 509 break; 510 case PORT_D: 511 port_mask = DPLL_PORTD_READY_MASK; 512 dpll_reg = DPIO_PHY_STATUS; 513 break; 514 default: 515 BUG(); 516 } 517 518 if (intel_de_wait_for_register(dev_priv, dpll_reg, 519 port_mask, expected_mask, 1000)) 520 drm_WARN(&dev_priv->drm, 1, 521 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", 522 dig_port->base.base.base.id, dig_port->base.base.name, 523 intel_de_read(dev_priv, dpll_reg) & port_mask, 524 expected_mask); 525 } 526 527 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) 528 { 529 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 530 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 531 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 532 enum pipe pipe = crtc->pipe; 533 i915_reg_t reg; 534 u32 val; 535 536 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe)); 537 538 assert_planes_disabled(crtc); 539 540 /* 541 * A pipe without a PLL won't actually be able to drive bits from 542 * a plane. On ILK+ the pipe PLLs are integrated, so we don't 543 * need the check. 544 */ 545 if (HAS_GMCH(dev_priv)) { 546 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI)) 547 assert_dsi_pll_enabled(dev_priv); 548 else 549 assert_pll_enabled(dev_priv, pipe); 550 } else { 551 if (new_crtc_state->has_pch_encoder) { 552 /* if driving the PCH, we need FDI enabled */ 553 assert_fdi_rx_pll_enabled(dev_priv, 554 intel_crtc_pch_transcoder(crtc)); 555 assert_fdi_tx_pll_enabled(dev_priv, 556 (enum pipe) cpu_transcoder); 557 } 558 /* FIXME: assert CPU port conditions for SNB+ */ 559 } 560 561 /* Wa_22012358565:adl-p */ 562 if (DISPLAY_VER(dev_priv) == 13) 563 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe), 564 0, PIPE_ARB_USE_PROG_SLOTS); 565 566 reg = PIPECONF(cpu_transcoder); 567 val = intel_de_read(dev_priv, reg); 568 if (val & PIPECONF_ENABLE) { 569 /* we keep both pipes enabled on 830 */ 570 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv)); 571 return; 572 } 573 574 intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE); 575 intel_de_posting_read(dev_priv, reg); 576 577 /* 578 * Until the pipe starts PIPEDSL reads will return a stale value, 579 * which causes an apparent vblank timestamp jump when PIPEDSL 580 * resets to its proper value. That also messes up the frame count 581 * when it's derived from the timestamps. So let's wait for the 582 * pipe to start properly before we call drm_crtc_vblank_on() 583 */ 584 if (intel_crtc_max_vblank_count(new_crtc_state) == 0) 585 intel_wait_for_pipe_scanline_moving(crtc); 586 } 587 588 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) 589 { 590 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 591 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 592 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 593 enum pipe pipe = crtc->pipe; 594 i915_reg_t reg; 595 u32 val; 596 597 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe)); 598 599 /* 600 * Make sure planes won't keep trying to pump pixels to us, 601 * or we might hang the display. 602 */ 603 assert_planes_disabled(crtc); 604 605 reg = PIPECONF(cpu_transcoder); 606 val = intel_de_read(dev_priv, reg); 607 if ((val & PIPECONF_ENABLE) == 0) 608 return; 609 610 /* 611 * Double wide has implications for planes 612 * so best keep it disabled when not needed. 613 */ 614 if (old_crtc_state->double_wide) 615 val &= ~PIPECONF_DOUBLE_WIDE; 616 617 /* Don't disable pipe or pipe PLLs if needed */ 618 if (!IS_I830(dev_priv)) 619 val &= ~PIPECONF_ENABLE; 620 621 if (DISPLAY_VER(dev_priv) >= 12) 622 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 623 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 624 625 intel_de_write(dev_priv, reg, val); 626 if ((val & PIPECONF_ENABLE) == 0) 627 intel_wait_for_pipe_off(old_crtc_state); 628 } 629 630 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) 631 { 632 unsigned int size = 0; 633 int i; 634 635 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) 636 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width; 637 638 return size; 639 } 640 641 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info) 642 { 643 unsigned int size = 0; 644 int i; 645 646 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) { 647 unsigned int plane_size; 648 649 if (rem_info->plane[i].linear) 650 plane_size = rem_info->plane[i].size; 651 else 652 plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height; 653 654 if (plane_size == 0) 655 continue; 656 657 if (rem_info->plane_alignment) 658 size = ALIGN(size, rem_info->plane_alignment); 659 660 size += plane_size; 661 } 662 663 return size; 664 } 665 666 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) 667 { 668 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 669 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 670 671 return DISPLAY_VER(dev_priv) < 4 || 672 (plane->fbc && 673 plane_state->view.gtt.type == I915_GGTT_VIEW_NORMAL); 674 } 675 676 /* 677 * Convert the x/y offsets into a linear offset. 678 * Only valid with 0/180 degree rotation, which is fine since linear 679 * offset is only used with linear buffers on pre-hsw and tiled buffers 680 * with gen2/3, and 90/270 degree rotations isn't supported on any of them. 681 */ 682 u32 intel_fb_xy_to_linear(int x, int y, 683 const struct intel_plane_state *state, 684 int color_plane) 685 { 686 const struct drm_framebuffer *fb = state->hw.fb; 687 unsigned int cpp = fb->format->cpp[color_plane]; 688 unsigned int pitch = state->view.color_plane[color_plane].mapping_stride; 689 690 return y * pitch + x * cpp; 691 } 692 693 /* 694 * Add the x/y offsets derived from fb->offsets[] to the user 695 * specified plane src x/y offsets. The resulting x/y offsets 696 * specify the start of scanout from the beginning of the gtt mapping. 697 */ 698 void intel_add_fb_offsets(int *x, int *y, 699 const struct intel_plane_state *state, 700 int color_plane) 701 702 { 703 *x += state->view.color_plane[color_plane].x; 704 *y += state->view.color_plane[color_plane].y; 705 } 706 707 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 708 u32 pixel_format, u64 modifier) 709 { 710 struct intel_crtc *crtc; 711 struct intel_plane *plane; 712 713 if (!HAS_DISPLAY(dev_priv)) 714 return 0; 715 716 /* 717 * We assume the primary plane for pipe A has 718 * the highest stride limits of them all, 719 * if in case pipe A is disabled, use the first pipe from pipe_mask. 720 */ 721 crtc = intel_first_crtc(dev_priv); 722 if (!crtc) 723 return 0; 724 725 plane = to_intel_plane(crtc->base.primary); 726 727 return plane->max_stride(plane, pixel_format, modifier, 728 DRM_MODE_ROTATE_0); 729 } 730 731 static void 732 intel_set_plane_visible(struct intel_crtc_state *crtc_state, 733 struct intel_plane_state *plane_state, 734 bool visible) 735 { 736 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 737 738 plane_state->uapi.visible = visible; 739 740 if (visible) 741 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base); 742 else 743 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base); 744 } 745 746 static void fixup_plane_bitmasks(struct intel_crtc_state *crtc_state) 747 { 748 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 749 struct drm_plane *plane; 750 751 /* 752 * Active_planes aliases if multiple "primary" or cursor planes 753 * have been used on the same (or wrong) pipe. plane_mask uses 754 * unique ids, hence we can use that to reconstruct active_planes. 755 */ 756 crtc_state->enabled_planes = 0; 757 crtc_state->active_planes = 0; 758 759 drm_for_each_plane_mask(plane, &dev_priv->drm, 760 crtc_state->uapi.plane_mask) { 761 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id); 762 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id); 763 } 764 } 765 766 void intel_plane_disable_noatomic(struct intel_crtc *crtc, 767 struct intel_plane *plane) 768 { 769 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 770 struct intel_crtc_state *crtc_state = 771 to_intel_crtc_state(crtc->base.state); 772 struct intel_plane_state *plane_state = 773 to_intel_plane_state(plane->base.state); 774 775 drm_dbg_kms(&dev_priv->drm, 776 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n", 777 plane->base.base.id, plane->base.name, 778 crtc->base.base.id, crtc->base.name); 779 780 intel_set_plane_visible(crtc_state, plane_state, false); 781 fixup_plane_bitmasks(crtc_state); 782 crtc_state->data_rate[plane->id] = 0; 783 crtc_state->data_rate_y[plane->id] = 0; 784 crtc_state->rel_data_rate[plane->id] = 0; 785 crtc_state->rel_data_rate_y[plane->id] = 0; 786 crtc_state->min_cdclk[plane->id] = 0; 787 788 if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 && 789 hsw_ips_disable(crtc_state)) { 790 crtc_state->ips_enabled = false; 791 intel_crtc_wait_for_next_vblank(crtc); 792 } 793 794 /* 795 * Vblank time updates from the shadow to live plane control register 796 * are blocked if the memory self-refresh mode is active at that 797 * moment. So to make sure the plane gets truly disabled, disable 798 * first the self-refresh mode. The self-refresh enable bit in turn 799 * will be checked/applied by the HW only at the next frame start 800 * event which is after the vblank start event, so we need to have a 801 * wait-for-vblank between disabling the plane and the pipe. 802 */ 803 if (HAS_GMCH(dev_priv) && 804 intel_set_memory_cxsr(dev_priv, false)) 805 intel_crtc_wait_for_next_vblank(crtc); 806 807 /* 808 * Gen2 reports pipe underruns whenever all planes are disabled. 809 * So disable underrun reporting before all the planes get disabled. 810 */ 811 if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes) 812 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); 813 814 intel_plane_disable_arm(plane, crtc_state); 815 intel_crtc_wait_for_next_vblank(crtc); 816 } 817 818 unsigned int 819 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state) 820 { 821 int x = 0, y = 0; 822 823 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, 824 plane_state->view.color_plane[0].offset, 0); 825 826 return y; 827 } 828 829 static int 830 __intel_display_resume(struct drm_device *dev, 831 struct drm_atomic_state *state, 832 struct drm_modeset_acquire_ctx *ctx) 833 { 834 struct drm_crtc_state *crtc_state; 835 struct drm_crtc *crtc; 836 int i, ret; 837 838 intel_modeset_setup_hw_state(dev, ctx); 839 intel_vga_redisable(to_i915(dev)); 840 841 if (!state) 842 return 0; 843 844 /* 845 * We've duplicated the state, pointers to the old state are invalid. 846 * 847 * Don't attempt to use the old state until we commit the duplicated state. 848 */ 849 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 850 /* 851 * Force recalculation even if we restore 852 * current state. With fast modeset this may not result 853 * in a modeset when the state is compatible. 854 */ 855 crtc_state->mode_changed = true; 856 } 857 858 /* ignore any reset values/BIOS leftovers in the WM registers */ 859 if (!HAS_GMCH(to_i915(dev))) 860 to_intel_atomic_state(state)->skip_intermediate_wm = true; 861 862 ret = drm_atomic_helper_commit_duplicated_state(state, ctx); 863 864 drm_WARN_ON(dev, ret == -EDEADLK); 865 return ret; 866 } 867 868 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) 869 { 870 return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display && 871 intel_has_gpu_reset(to_gt(dev_priv))); 872 } 873 874 void intel_display_prepare_reset(struct drm_i915_private *dev_priv) 875 { 876 struct drm_device *dev = &dev_priv->drm; 877 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; 878 struct drm_atomic_state *state; 879 int ret; 880 881 if (!HAS_DISPLAY(dev_priv)) 882 return; 883 884 /* reset doesn't touch the display */ 885 if (!dev_priv->params.force_reset_modeset_test && 886 !gpu_reset_clobbers_display(dev_priv)) 887 return; 888 889 /* We have a modeset vs reset deadlock, defensively unbreak it. */ 890 set_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags); 891 smp_mb__after_atomic(); 892 wake_up_bit(&to_gt(dev_priv)->reset.flags, I915_RESET_MODESET); 893 894 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) { 895 drm_dbg_kms(&dev_priv->drm, 896 "Modeset potentially stuck, unbreaking through wedging\n"); 897 intel_gt_set_wedged(to_gt(dev_priv)); 898 } 899 900 /* 901 * Need mode_config.mutex so that we don't 902 * trample ongoing ->detect() and whatnot. 903 */ 904 mutex_lock(&dev->mode_config.mutex); 905 drm_modeset_acquire_init(ctx, 0); 906 while (1) { 907 ret = drm_modeset_lock_all_ctx(dev, ctx); 908 if (ret != -EDEADLK) 909 break; 910 911 drm_modeset_backoff(ctx); 912 } 913 /* 914 * Disabling the crtcs gracefully seems nicer. Also the 915 * g33 docs say we should at least disable all the planes. 916 */ 917 state = drm_atomic_helper_duplicate_state(dev, ctx); 918 if (IS_ERR(state)) { 919 ret = PTR_ERR(state); 920 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n", 921 ret); 922 return; 923 } 924 925 ret = drm_atomic_helper_disable_all(dev, ctx); 926 if (ret) { 927 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", 928 ret); 929 drm_atomic_state_put(state); 930 return; 931 } 932 933 dev_priv->modeset_restore_state = state; 934 state->acquire_ctx = ctx; 935 } 936 937 void intel_display_finish_reset(struct drm_i915_private *dev_priv) 938 { 939 struct drm_device *dev = &dev_priv->drm; 940 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; 941 struct drm_atomic_state *state; 942 int ret; 943 944 if (!HAS_DISPLAY(dev_priv)) 945 return; 946 947 /* reset doesn't touch the display */ 948 if (!test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags)) 949 return; 950 951 state = fetch_and_zero(&dev_priv->modeset_restore_state); 952 if (!state) 953 goto unlock; 954 955 /* reset doesn't touch the display */ 956 if (!gpu_reset_clobbers_display(dev_priv)) { 957 /* for testing only restore the display */ 958 ret = __intel_display_resume(dev, state, ctx); 959 if (ret) 960 drm_err(&dev_priv->drm, 961 "Restoring old state failed with %i\n", ret); 962 } else { 963 /* 964 * The display has been reset as well, 965 * so need a full re-initialization. 966 */ 967 intel_pps_unlock_regs_wa(dev_priv); 968 intel_modeset_init_hw(dev_priv); 969 intel_init_clock_gating(dev_priv); 970 intel_hpd_init(dev_priv); 971 972 ret = __intel_display_resume(dev, state, ctx); 973 if (ret) 974 drm_err(&dev_priv->drm, 975 "Restoring old state failed with %i\n", ret); 976 977 intel_hpd_poll_disable(dev_priv); 978 } 979 980 drm_atomic_state_put(state); 981 unlock: 982 drm_modeset_drop_locks(ctx); 983 drm_modeset_acquire_fini(ctx); 984 mutex_unlock(&dev->mode_config.mutex); 985 986 clear_bit_unlock(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags); 987 } 988 989 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) 990 { 991 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 992 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 993 enum pipe pipe = crtc->pipe; 994 u32 tmp; 995 996 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe)); 997 998 /* 999 * Display WA #1153: icl 1000 * enable hardware to bypass the alpha math 1001 * and rounding for per-pixel values 00 and 0xff 1002 */ 1003 tmp |= PER_PIXEL_ALPHA_BYPASS_EN; 1004 /* 1005 * Display WA # 1605353570: icl 1006 * Set the pixel rounding bit to 1 for allowing 1007 * passthrough of Frame buffer pixels unmodified 1008 * across pipe 1009 */ 1010 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU; 1011 1012 /* 1013 * Underrun recovery must always be disabled on display 13+. 1014 * DG2 chicken bit meaning is inverted compared to other platforms. 1015 */ 1016 if (IS_DG2(dev_priv)) 1017 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2; 1018 else if (DISPLAY_VER(dev_priv) >= 13) 1019 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP; 1020 1021 /* Wa_14010547955:dg2 */ 1022 if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER)) 1023 tmp |= DG2_RENDER_CCSTAG_4_3_EN; 1024 1025 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp); 1026 } 1027 1028 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) 1029 { 1030 struct drm_crtc *crtc; 1031 bool cleanup_done; 1032 1033 drm_for_each_crtc(crtc, &dev_priv->drm) { 1034 struct drm_crtc_commit *commit; 1035 spin_lock(&crtc->commit_lock); 1036 commit = list_first_entry_or_null(&crtc->commit_list, 1037 struct drm_crtc_commit, commit_entry); 1038 cleanup_done = commit ? 1039 try_wait_for_completion(&commit->cleanup_done) : true; 1040 spin_unlock(&crtc->commit_lock); 1041 1042 if (cleanup_done) 1043 continue; 1044 1045 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc)); 1046 1047 return true; 1048 } 1049 1050 return false; 1051 } 1052 1053 /* 1054 * Finds the encoder associated with the given CRTC. This can only be 1055 * used when we know that the CRTC isn't feeding multiple encoders! 1056 */ 1057 struct intel_encoder * 1058 intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 1059 const struct intel_crtc_state *crtc_state) 1060 { 1061 const struct drm_connector_state *connector_state; 1062 const struct drm_connector *connector; 1063 struct intel_encoder *encoder = NULL; 1064 struct intel_crtc *master_crtc; 1065 int num_encoders = 0; 1066 int i; 1067 1068 master_crtc = intel_master_crtc(crtc_state); 1069 1070 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 1071 if (connector_state->crtc != &master_crtc->base) 1072 continue; 1073 1074 encoder = to_intel_encoder(connector_state->best_encoder); 1075 num_encoders++; 1076 } 1077 1078 drm_WARN(encoder->base.dev, num_encoders != 1, 1079 "%d encoders for pipe %c\n", 1080 num_encoders, pipe_name(master_crtc->pipe)); 1081 1082 return encoder; 1083 } 1084 1085 static void cpt_verify_modeset(struct drm_i915_private *dev_priv, 1086 enum pipe pipe) 1087 { 1088 i915_reg_t dslreg = PIPEDSL(pipe); 1089 u32 temp; 1090 1091 temp = intel_de_read(dev_priv, dslreg); 1092 udelay(500); 1093 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) { 1094 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) 1095 drm_err(&dev_priv->drm, 1096 "mode set failed: pipe %c stuck\n", 1097 pipe_name(pipe)); 1098 } 1099 } 1100 1101 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state) 1102 { 1103 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1104 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1105 const struct drm_rect *dst = &crtc_state->pch_pfit.dst; 1106 enum pipe pipe = crtc->pipe; 1107 int width = drm_rect_width(dst); 1108 int height = drm_rect_height(dst); 1109 int x = dst->x1; 1110 int y = dst->y1; 1111 1112 if (!crtc_state->pch_pfit.enabled) 1113 return; 1114 1115 /* Force use of hard-coded filter coefficients 1116 * as some pre-programmed values are broken, 1117 * e.g. x201. 1118 */ 1119 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) 1120 intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE | 1121 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe)); 1122 else 1123 intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE | 1124 PF_FILTER_MED_3x3); 1125 intel_de_write(dev_priv, PF_WIN_POS(pipe), x << 16 | y); 1126 intel_de_write(dev_priv, PF_WIN_SZ(pipe), width << 16 | height); 1127 } 1128 1129 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc) 1130 { 1131 if (crtc->overlay) 1132 (void) intel_overlay_switch_off(crtc->overlay); 1133 1134 /* Let userspace switch the overlay on again. In most cases userspace 1135 * has to recompute where to put it anyway. 1136 */ 1137 } 1138 1139 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state) 1140 { 1141 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1142 1143 if (!crtc_state->nv12_planes) 1144 return false; 1145 1146 /* WA Display #0827: Gen9:all */ 1147 if (DISPLAY_VER(dev_priv) == 9) 1148 return true; 1149 1150 return false; 1151 } 1152 1153 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state) 1154 { 1155 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1156 1157 /* Wa_2006604312:icl,ehl */ 1158 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11) 1159 return true; 1160 1161 return false; 1162 } 1163 1164 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state) 1165 { 1166 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1167 1168 /* Wa_1604331009:icl,jsl,ehl */ 1169 if (is_hdr_mode(crtc_state) && 1170 crtc_state->active_planes & BIT(PLANE_CURSOR) && 1171 DISPLAY_VER(dev_priv) == 11) 1172 return true; 1173 1174 return false; 1175 } 1176 1177 static void intel_async_flip_vtd_wa(struct drm_i915_private *i915, 1178 enum pipe pipe, bool enable) 1179 { 1180 if (DISPLAY_VER(i915) == 9) { 1181 /* 1182 * "Plane N strech max must be programmed to 11b (x1) 1183 * when Async flips are enabled on that plane." 1184 */ 1185 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 1186 SKL_PLANE1_STRETCH_MAX_MASK, 1187 enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8); 1188 } else { 1189 /* Also needed on HSW/BDW albeit undocumented */ 1190 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 1191 HSW_PRI_STRETCH_MAX_MASK, 1192 enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8); 1193 } 1194 } 1195 1196 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state) 1197 { 1198 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1199 1200 return crtc_state->uapi.async_flip && intel_vtd_active(i915) && 1201 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915)); 1202 } 1203 1204 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state, 1205 const struct intel_crtc_state *new_crtc_state) 1206 { 1207 return (!old_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)) && 1208 new_crtc_state->active_planes; 1209 } 1210 1211 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state, 1212 const struct intel_crtc_state *new_crtc_state) 1213 { 1214 return old_crtc_state->active_planes && 1215 (!new_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)); 1216 } 1217 1218 static void intel_post_plane_update(struct intel_atomic_state *state, 1219 struct intel_crtc *crtc) 1220 { 1221 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1222 const struct intel_crtc_state *old_crtc_state = 1223 intel_atomic_get_old_crtc_state(state, crtc); 1224 const struct intel_crtc_state *new_crtc_state = 1225 intel_atomic_get_new_crtc_state(state, crtc); 1226 enum pipe pipe = crtc->pipe; 1227 1228 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); 1229 1230 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) 1231 intel_update_watermarks(dev_priv); 1232 1233 hsw_ips_post_update(state, crtc); 1234 intel_fbc_post_update(state, crtc); 1235 1236 if (needs_async_flip_vtd_wa(old_crtc_state) && 1237 !needs_async_flip_vtd_wa(new_crtc_state)) 1238 intel_async_flip_vtd_wa(dev_priv, pipe, false); 1239 1240 if (needs_nv12_wa(old_crtc_state) && 1241 !needs_nv12_wa(new_crtc_state)) 1242 skl_wa_827(dev_priv, pipe, false); 1243 1244 if (needs_scalerclk_wa(old_crtc_state) && 1245 !needs_scalerclk_wa(new_crtc_state)) 1246 icl_wa_scalerclkgating(dev_priv, pipe, false); 1247 1248 if (needs_cursorclk_wa(old_crtc_state) && 1249 !needs_cursorclk_wa(new_crtc_state)) 1250 icl_wa_cursorclkgating(dev_priv, pipe, false); 1251 1252 intel_drrs_enable(new_crtc_state); 1253 } 1254 1255 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state, 1256 struct intel_crtc *crtc) 1257 { 1258 const struct intel_crtc_state *crtc_state = 1259 intel_atomic_get_new_crtc_state(state, crtc); 1260 u8 update_planes = crtc_state->update_planes; 1261 const struct intel_plane_state *plane_state; 1262 struct intel_plane *plane; 1263 int i; 1264 1265 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1266 if (plane->pipe == crtc->pipe && 1267 update_planes & BIT(plane->id)) 1268 plane->enable_flip_done(plane); 1269 } 1270 } 1271 1272 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state, 1273 struct intel_crtc *crtc) 1274 { 1275 const struct intel_crtc_state *crtc_state = 1276 intel_atomic_get_new_crtc_state(state, crtc); 1277 u8 update_planes = crtc_state->update_planes; 1278 const struct intel_plane_state *plane_state; 1279 struct intel_plane *plane; 1280 int i; 1281 1282 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1283 if (plane->pipe == crtc->pipe && 1284 update_planes & BIT(plane->id)) 1285 plane->disable_flip_done(plane); 1286 } 1287 } 1288 1289 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state, 1290 struct intel_crtc *crtc) 1291 { 1292 const struct intel_crtc_state *old_crtc_state = 1293 intel_atomic_get_old_crtc_state(state, crtc); 1294 const struct intel_crtc_state *new_crtc_state = 1295 intel_atomic_get_new_crtc_state(state, crtc); 1296 u8 update_planes = new_crtc_state->update_planes; 1297 const struct intel_plane_state *old_plane_state; 1298 struct intel_plane *plane; 1299 bool need_vbl_wait = false; 1300 int i; 1301 1302 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1303 if (plane->need_async_flip_disable_wa && 1304 plane->pipe == crtc->pipe && 1305 update_planes & BIT(plane->id)) { 1306 /* 1307 * Apart from the async flip bit we want to 1308 * preserve the old state for the plane. 1309 */ 1310 plane->async_flip(plane, old_crtc_state, 1311 old_plane_state, false); 1312 need_vbl_wait = true; 1313 } 1314 } 1315 1316 if (need_vbl_wait) 1317 intel_crtc_wait_for_next_vblank(crtc); 1318 } 1319 1320 static void intel_pre_plane_update(struct intel_atomic_state *state, 1321 struct intel_crtc *crtc) 1322 { 1323 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1324 const struct intel_crtc_state *old_crtc_state = 1325 intel_atomic_get_old_crtc_state(state, crtc); 1326 const struct intel_crtc_state *new_crtc_state = 1327 intel_atomic_get_new_crtc_state(state, crtc); 1328 enum pipe pipe = crtc->pipe; 1329 1330 intel_drrs_disable(old_crtc_state); 1331 1332 intel_psr_pre_plane_update(state, crtc); 1333 1334 if (hsw_ips_pre_update(state, crtc)) 1335 intel_crtc_wait_for_next_vblank(crtc); 1336 1337 if (intel_fbc_pre_update(state, crtc)) 1338 intel_crtc_wait_for_next_vblank(crtc); 1339 1340 if (!needs_async_flip_vtd_wa(old_crtc_state) && 1341 needs_async_flip_vtd_wa(new_crtc_state)) 1342 intel_async_flip_vtd_wa(dev_priv, pipe, true); 1343 1344 /* Display WA 827 */ 1345 if (!needs_nv12_wa(old_crtc_state) && 1346 needs_nv12_wa(new_crtc_state)) 1347 skl_wa_827(dev_priv, pipe, true); 1348 1349 /* Wa_2006604312:icl,ehl */ 1350 if (!needs_scalerclk_wa(old_crtc_state) && 1351 needs_scalerclk_wa(new_crtc_state)) 1352 icl_wa_scalerclkgating(dev_priv, pipe, true); 1353 1354 /* Wa_1604331009:icl,jsl,ehl */ 1355 if (!needs_cursorclk_wa(old_crtc_state) && 1356 needs_cursorclk_wa(new_crtc_state)) 1357 icl_wa_cursorclkgating(dev_priv, pipe, true); 1358 1359 /* 1360 * Vblank time updates from the shadow to live plane control register 1361 * are blocked if the memory self-refresh mode is active at that 1362 * moment. So to make sure the plane gets truly disabled, disable 1363 * first the self-refresh mode. The self-refresh enable bit in turn 1364 * will be checked/applied by the HW only at the next frame start 1365 * event which is after the vblank start event, so we need to have a 1366 * wait-for-vblank between disabling the plane and the pipe. 1367 */ 1368 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active && 1369 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) 1370 intel_crtc_wait_for_next_vblank(crtc); 1371 1372 /* 1373 * IVB workaround: must disable low power watermarks for at least 1374 * one frame before enabling scaling. LP watermarks can be re-enabled 1375 * when scaling is disabled. 1376 * 1377 * WaCxSRDisabledForSpriteScaling:ivb 1378 */ 1379 if (old_crtc_state->hw.active && 1380 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv)) 1381 intel_crtc_wait_for_next_vblank(crtc); 1382 1383 /* 1384 * If we're doing a modeset we don't need to do any 1385 * pre-vblank watermark programming here. 1386 */ 1387 if (!intel_crtc_needs_modeset(new_crtc_state)) { 1388 /* 1389 * For platforms that support atomic watermarks, program the 1390 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these 1391 * will be the intermediate values that are safe for both pre- and 1392 * post- vblank; when vblank happens, the 'active' values will be set 1393 * to the final 'target' values and we'll do this again to get the 1394 * optimal watermarks. For gen9+ platforms, the values we program here 1395 * will be the final target values which will get automatically latched 1396 * at vblank time; no further programming will be necessary. 1397 * 1398 * If a platform hasn't been transitioned to atomic watermarks yet, 1399 * we'll continue to update watermarks the old way, if flags tell 1400 * us to. 1401 */ 1402 if (!intel_initial_watermarks(state, crtc)) 1403 if (new_crtc_state->update_wm_pre) 1404 intel_update_watermarks(dev_priv); 1405 } 1406 1407 /* 1408 * Gen2 reports pipe underruns whenever all planes are disabled. 1409 * So disable underrun reporting before all the planes get disabled. 1410 * 1411 * We do this after .initial_watermarks() so that we have a 1412 * chance of catching underruns with the intermediate watermarks 1413 * vs. the old plane configuration. 1414 */ 1415 if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state)) 1416 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1417 1418 /* 1419 * WA for platforms where async address update enable bit 1420 * is double buffered and only latched at start of vblank. 1421 */ 1422 if (old_crtc_state->uapi.async_flip && !new_crtc_state->uapi.async_flip) 1423 intel_crtc_async_flip_disable_wa(state, crtc); 1424 } 1425 1426 static void intel_crtc_disable_planes(struct intel_atomic_state *state, 1427 struct intel_crtc *crtc) 1428 { 1429 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1430 const struct intel_crtc_state *new_crtc_state = 1431 intel_atomic_get_new_crtc_state(state, crtc); 1432 unsigned int update_mask = new_crtc_state->update_planes; 1433 const struct intel_plane_state *old_plane_state; 1434 struct intel_plane *plane; 1435 unsigned fb_bits = 0; 1436 int i; 1437 1438 intel_crtc_dpms_overlay_disable(crtc); 1439 1440 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1441 if (crtc->pipe != plane->pipe || 1442 !(update_mask & BIT(plane->id))) 1443 continue; 1444 1445 intel_plane_disable_arm(plane, new_crtc_state); 1446 1447 if (old_plane_state->uapi.visible) 1448 fb_bits |= plane->frontbuffer_bit; 1449 } 1450 1451 intel_frontbuffer_flip(dev_priv, fb_bits); 1452 } 1453 1454 /* 1455 * intel_connector_primary_encoder - get the primary encoder for a connector 1456 * @connector: connector for which to return the encoder 1457 * 1458 * Returns the primary encoder for a connector. There is a 1:1 mapping from 1459 * all connectors to their encoder, except for DP-MST connectors which have 1460 * both a virtual and a primary encoder. These DP-MST primary encoders can be 1461 * pointed to by as many DP-MST connectors as there are pipes. 1462 */ 1463 static struct intel_encoder * 1464 intel_connector_primary_encoder(struct intel_connector *connector) 1465 { 1466 struct intel_encoder *encoder; 1467 1468 if (connector->mst_port) 1469 return &dp_to_dig_port(connector->mst_port)->base; 1470 1471 encoder = intel_attached_encoder(connector); 1472 drm_WARN_ON(connector->base.dev, !encoder); 1473 1474 return encoder; 1475 } 1476 1477 static void intel_encoders_update_prepare(struct intel_atomic_state *state) 1478 { 1479 struct drm_i915_private *i915 = to_i915(state->base.dev); 1480 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 1481 struct intel_crtc *crtc; 1482 struct drm_connector_state *new_conn_state; 1483 struct drm_connector *connector; 1484 int i; 1485 1486 /* 1487 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits. 1488 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook. 1489 */ 1490 if (i915->dpll.mgr) { 1491 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1492 if (intel_crtc_needs_modeset(new_crtc_state)) 1493 continue; 1494 1495 new_crtc_state->shared_dpll = old_crtc_state->shared_dpll; 1496 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state; 1497 } 1498 } 1499 1500 if (!state->modeset) 1501 return; 1502 1503 for_each_new_connector_in_state(&state->base, connector, new_conn_state, 1504 i) { 1505 struct intel_connector *intel_connector; 1506 struct intel_encoder *encoder; 1507 struct intel_crtc *crtc; 1508 1509 if (!intel_connector_needs_modeset(state, connector)) 1510 continue; 1511 1512 intel_connector = to_intel_connector(connector); 1513 encoder = intel_connector_primary_encoder(intel_connector); 1514 if (!encoder->update_prepare) 1515 continue; 1516 1517 crtc = new_conn_state->crtc ? 1518 to_intel_crtc(new_conn_state->crtc) : NULL; 1519 encoder->update_prepare(state, encoder, crtc); 1520 } 1521 } 1522 1523 static void intel_encoders_update_complete(struct intel_atomic_state *state) 1524 { 1525 struct drm_connector_state *new_conn_state; 1526 struct drm_connector *connector; 1527 int i; 1528 1529 if (!state->modeset) 1530 return; 1531 1532 for_each_new_connector_in_state(&state->base, connector, new_conn_state, 1533 i) { 1534 struct intel_connector *intel_connector; 1535 struct intel_encoder *encoder; 1536 struct intel_crtc *crtc; 1537 1538 if (!intel_connector_needs_modeset(state, connector)) 1539 continue; 1540 1541 intel_connector = to_intel_connector(connector); 1542 encoder = intel_connector_primary_encoder(intel_connector); 1543 if (!encoder->update_complete) 1544 continue; 1545 1546 crtc = new_conn_state->crtc ? 1547 to_intel_crtc(new_conn_state->crtc) : NULL; 1548 encoder->update_complete(state, encoder, crtc); 1549 } 1550 } 1551 1552 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state, 1553 struct intel_crtc *crtc) 1554 { 1555 const struct intel_crtc_state *crtc_state = 1556 intel_atomic_get_new_crtc_state(state, crtc); 1557 const struct drm_connector_state *conn_state; 1558 struct drm_connector *conn; 1559 int i; 1560 1561 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1562 struct intel_encoder *encoder = 1563 to_intel_encoder(conn_state->best_encoder); 1564 1565 if (conn_state->crtc != &crtc->base) 1566 continue; 1567 1568 if (encoder->pre_pll_enable) 1569 encoder->pre_pll_enable(state, encoder, 1570 crtc_state, conn_state); 1571 } 1572 } 1573 1574 static void intel_encoders_pre_enable(struct intel_atomic_state *state, 1575 struct intel_crtc *crtc) 1576 { 1577 const struct intel_crtc_state *crtc_state = 1578 intel_atomic_get_new_crtc_state(state, crtc); 1579 const struct drm_connector_state *conn_state; 1580 struct drm_connector *conn; 1581 int i; 1582 1583 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1584 struct intel_encoder *encoder = 1585 to_intel_encoder(conn_state->best_encoder); 1586 1587 if (conn_state->crtc != &crtc->base) 1588 continue; 1589 1590 if (encoder->pre_enable) 1591 encoder->pre_enable(state, encoder, 1592 crtc_state, conn_state); 1593 } 1594 } 1595 1596 static void intel_encoders_enable(struct intel_atomic_state *state, 1597 struct intel_crtc *crtc) 1598 { 1599 const struct intel_crtc_state *crtc_state = 1600 intel_atomic_get_new_crtc_state(state, crtc); 1601 const struct drm_connector_state *conn_state; 1602 struct drm_connector *conn; 1603 int i; 1604 1605 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1606 struct intel_encoder *encoder = 1607 to_intel_encoder(conn_state->best_encoder); 1608 1609 if (conn_state->crtc != &crtc->base) 1610 continue; 1611 1612 if (encoder->enable) 1613 encoder->enable(state, encoder, 1614 crtc_state, conn_state); 1615 intel_opregion_notify_encoder(encoder, true); 1616 } 1617 } 1618 1619 static void intel_encoders_disable(struct intel_atomic_state *state, 1620 struct intel_crtc *crtc) 1621 { 1622 const struct intel_crtc_state *old_crtc_state = 1623 intel_atomic_get_old_crtc_state(state, crtc); 1624 const struct drm_connector_state *old_conn_state; 1625 struct drm_connector *conn; 1626 int i; 1627 1628 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1629 struct intel_encoder *encoder = 1630 to_intel_encoder(old_conn_state->best_encoder); 1631 1632 if (old_conn_state->crtc != &crtc->base) 1633 continue; 1634 1635 intel_opregion_notify_encoder(encoder, false); 1636 if (encoder->disable) 1637 encoder->disable(state, encoder, 1638 old_crtc_state, old_conn_state); 1639 } 1640 } 1641 1642 static void intel_encoders_post_disable(struct intel_atomic_state *state, 1643 struct intel_crtc *crtc) 1644 { 1645 const struct intel_crtc_state *old_crtc_state = 1646 intel_atomic_get_old_crtc_state(state, crtc); 1647 const struct drm_connector_state *old_conn_state; 1648 struct drm_connector *conn; 1649 int i; 1650 1651 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1652 struct intel_encoder *encoder = 1653 to_intel_encoder(old_conn_state->best_encoder); 1654 1655 if (old_conn_state->crtc != &crtc->base) 1656 continue; 1657 1658 if (encoder->post_disable) 1659 encoder->post_disable(state, encoder, 1660 old_crtc_state, old_conn_state); 1661 } 1662 } 1663 1664 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state, 1665 struct intel_crtc *crtc) 1666 { 1667 const struct intel_crtc_state *old_crtc_state = 1668 intel_atomic_get_old_crtc_state(state, crtc); 1669 const struct drm_connector_state *old_conn_state; 1670 struct drm_connector *conn; 1671 int i; 1672 1673 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1674 struct intel_encoder *encoder = 1675 to_intel_encoder(old_conn_state->best_encoder); 1676 1677 if (old_conn_state->crtc != &crtc->base) 1678 continue; 1679 1680 if (encoder->post_pll_disable) 1681 encoder->post_pll_disable(state, encoder, 1682 old_crtc_state, old_conn_state); 1683 } 1684 } 1685 1686 static void intel_encoders_update_pipe(struct intel_atomic_state *state, 1687 struct intel_crtc *crtc) 1688 { 1689 const struct intel_crtc_state *crtc_state = 1690 intel_atomic_get_new_crtc_state(state, crtc); 1691 const struct drm_connector_state *conn_state; 1692 struct drm_connector *conn; 1693 int i; 1694 1695 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1696 struct intel_encoder *encoder = 1697 to_intel_encoder(conn_state->best_encoder); 1698 1699 if (conn_state->crtc != &crtc->base) 1700 continue; 1701 1702 if (encoder->update_pipe) 1703 encoder->update_pipe(state, encoder, 1704 crtc_state, conn_state); 1705 } 1706 } 1707 1708 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state) 1709 { 1710 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1711 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 1712 1713 plane->disable_arm(plane, crtc_state); 1714 } 1715 1716 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1717 { 1718 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1719 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1720 1721 if (crtc_state->has_pch_encoder) { 1722 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1723 &crtc_state->fdi_m_n); 1724 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1725 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1726 &crtc_state->dp_m_n); 1727 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1728 &crtc_state->dp_m2_n2); 1729 } 1730 1731 intel_set_transcoder_timings(crtc_state); 1732 1733 ilk_set_pipeconf(crtc_state); 1734 } 1735 1736 static void ilk_crtc_enable(struct intel_atomic_state *state, 1737 struct intel_crtc *crtc) 1738 { 1739 const struct intel_crtc_state *new_crtc_state = 1740 intel_atomic_get_new_crtc_state(state, crtc); 1741 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1742 enum pipe pipe = crtc->pipe; 1743 1744 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1745 return; 1746 1747 /* 1748 * Sometimes spurious CPU pipe underruns happen during FDI 1749 * training, at least with VGA+HDMI cloning. Suppress them. 1750 * 1751 * On ILK we get an occasional spurious CPU pipe underruns 1752 * between eDP port A enable and vdd enable. Also PCH port 1753 * enable seems to result in the occasional CPU pipe underrun. 1754 * 1755 * Spurious PCH underruns also occur during PCH enabling. 1756 */ 1757 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1758 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 1759 1760 ilk_configure_cpu_transcoder(new_crtc_state); 1761 1762 intel_set_pipe_src_size(new_crtc_state); 1763 1764 crtc->active = true; 1765 1766 intel_encoders_pre_enable(state, crtc); 1767 1768 if (new_crtc_state->has_pch_encoder) { 1769 ilk_pch_pre_enable(state, crtc); 1770 } else { 1771 assert_fdi_tx_disabled(dev_priv, pipe); 1772 assert_fdi_rx_disabled(dev_priv, pipe); 1773 } 1774 1775 ilk_pfit_enable(new_crtc_state); 1776 1777 /* 1778 * On ILK+ LUT must be loaded before the pipe is running but with 1779 * clocks enabled 1780 */ 1781 intel_color_load_luts(new_crtc_state); 1782 intel_color_commit(new_crtc_state); 1783 /* update DSPCNTR to configure gamma for pipe bottom color */ 1784 intel_disable_primary_plane(new_crtc_state); 1785 1786 intel_initial_watermarks(state, crtc); 1787 intel_enable_transcoder(new_crtc_state); 1788 1789 if (new_crtc_state->has_pch_encoder) 1790 ilk_pch_enable(state, crtc); 1791 1792 intel_crtc_vblank_on(new_crtc_state); 1793 1794 intel_encoders_enable(state, crtc); 1795 1796 if (HAS_PCH_CPT(dev_priv)) 1797 cpt_verify_modeset(dev_priv, pipe); 1798 1799 /* 1800 * Must wait for vblank to avoid spurious PCH FIFO underruns. 1801 * And a second vblank wait is needed at least on ILK with 1802 * some interlaced HDMI modes. Let's do the double wait always 1803 * in case there are more corner cases we don't know about. 1804 */ 1805 if (new_crtc_state->has_pch_encoder) { 1806 intel_crtc_wait_for_next_vblank(crtc); 1807 intel_crtc_wait_for_next_vblank(crtc); 1808 } 1809 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1810 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 1811 } 1812 1813 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, 1814 enum pipe pipe, bool apply) 1815 { 1816 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)); 1817 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS; 1818 1819 if (apply) 1820 val |= mask; 1821 else 1822 val &= ~mask; 1823 1824 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val); 1825 } 1826 1827 static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool joined_mbus) 1828 { 1829 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1830 enum pipe pipe = crtc->pipe; 1831 u32 val; 1832 1833 /* Wa_22010947358:adl-p */ 1834 if (IS_ALDERLAKE_P(dev_priv)) 1835 val = joined_mbus ? MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4); 1836 else 1837 val = MBUS_DBOX_A_CREDIT(2); 1838 1839 if (DISPLAY_VER(dev_priv) >= 12) { 1840 val |= MBUS_DBOX_BW_CREDIT(2); 1841 val |= MBUS_DBOX_B_CREDIT(12); 1842 } else { 1843 val |= MBUS_DBOX_BW_CREDIT(1); 1844 val |= MBUS_DBOX_B_CREDIT(8); 1845 } 1846 1847 intel_de_write(dev_priv, PIPE_MBUS_DBOX_CTL(pipe), val); 1848 } 1849 1850 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state) 1851 { 1852 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1853 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1854 1855 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe), 1856 HSW_LINETIME(crtc_state->linetime) | 1857 HSW_IPS_LINETIME(crtc_state->ips_linetime)); 1858 } 1859 1860 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) 1861 { 1862 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1863 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1864 i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder); 1865 u32 val; 1866 1867 val = intel_de_read(dev_priv, reg); 1868 val &= ~HSW_FRAME_START_DELAY_MASK; 1869 val |= HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 1870 intel_de_write(dev_priv, reg, val); 1871 } 1872 1873 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state, 1874 const struct intel_crtc_state *crtc_state) 1875 { 1876 struct intel_crtc *master_crtc = intel_master_crtc(crtc_state); 1877 1878 /* 1879 * Enable sequence steps 1-7 on bigjoiner master 1880 */ 1881 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1882 intel_encoders_pre_pll_enable(state, master_crtc); 1883 1884 if (crtc_state->shared_dpll) 1885 intel_enable_shared_dpll(crtc_state); 1886 1887 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1888 intel_encoders_pre_enable(state, master_crtc); 1889 } 1890 1891 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1892 { 1893 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1894 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1895 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1896 1897 if (crtc_state->has_pch_encoder) { 1898 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1899 &crtc_state->fdi_m_n); 1900 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1901 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1902 &crtc_state->dp_m_n); 1903 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1904 &crtc_state->dp_m2_n2); 1905 } 1906 1907 intel_set_transcoder_timings(crtc_state); 1908 1909 if (cpu_transcoder != TRANSCODER_EDP) 1910 intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder), 1911 crtc_state->pixel_multiplier - 1); 1912 1913 hsw_set_frame_start_delay(crtc_state); 1914 1915 hsw_set_transconf(crtc_state); 1916 } 1917 1918 static void hsw_crtc_enable(struct intel_atomic_state *state, 1919 struct intel_crtc *crtc) 1920 { 1921 const struct intel_crtc_state *new_crtc_state = 1922 intel_atomic_get_new_crtc_state(state, crtc); 1923 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1924 enum pipe pipe = crtc->pipe, hsw_workaround_pipe; 1925 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 1926 bool psl_clkgate_wa; 1927 1928 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1929 return; 1930 1931 if (!new_crtc_state->bigjoiner_pipes) { 1932 intel_encoders_pre_pll_enable(state, crtc); 1933 1934 if (new_crtc_state->shared_dpll) 1935 intel_enable_shared_dpll(new_crtc_state); 1936 1937 intel_encoders_pre_enable(state, crtc); 1938 } else { 1939 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state); 1940 } 1941 1942 intel_dsc_enable(new_crtc_state); 1943 1944 if (DISPLAY_VER(dev_priv) >= 13) 1945 intel_uncompressed_joiner_enable(new_crtc_state); 1946 1947 intel_set_pipe_src_size(new_crtc_state); 1948 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 1949 bdw_set_pipemisc(new_crtc_state); 1950 1951 if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) && 1952 !transcoder_is_dsi(cpu_transcoder)) 1953 hsw_configure_cpu_transcoder(new_crtc_state); 1954 1955 crtc->active = true; 1956 1957 /* Display WA #1180: WaDisableScalarClockGating: glk */ 1958 psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 && 1959 new_crtc_state->pch_pfit.enabled; 1960 if (psl_clkgate_wa) 1961 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true); 1962 1963 if (DISPLAY_VER(dev_priv) >= 9) 1964 skl_pfit_enable(new_crtc_state); 1965 else 1966 ilk_pfit_enable(new_crtc_state); 1967 1968 /* 1969 * On ILK+ LUT must be loaded before the pipe is running but with 1970 * clocks enabled 1971 */ 1972 intel_color_load_luts(new_crtc_state); 1973 intel_color_commit(new_crtc_state); 1974 /* update DSPCNTR to configure gamma/csc for pipe bottom color */ 1975 if (DISPLAY_VER(dev_priv) < 9) 1976 intel_disable_primary_plane(new_crtc_state); 1977 1978 hsw_set_linetime_wm(new_crtc_state); 1979 1980 if (DISPLAY_VER(dev_priv) >= 11) 1981 icl_set_pipe_chicken(new_crtc_state); 1982 1983 intel_initial_watermarks(state, crtc); 1984 1985 if (DISPLAY_VER(dev_priv) >= 11) { 1986 const struct intel_dbuf_state *dbuf_state = 1987 intel_atomic_get_new_dbuf_state(state); 1988 1989 icl_pipe_mbus_enable(crtc, dbuf_state->joined_mbus); 1990 } 1991 1992 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 1993 intel_crtc_vblank_on(new_crtc_state); 1994 1995 intel_encoders_enable(state, crtc); 1996 1997 if (psl_clkgate_wa) { 1998 intel_crtc_wait_for_next_vblank(crtc); 1999 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false); 2000 } 2001 2002 /* If we change the relative order between pipe/planes enabling, we need 2003 * to change the workaround. */ 2004 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe; 2005 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { 2006 struct intel_crtc *wa_crtc; 2007 2008 wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe); 2009 2010 intel_crtc_wait_for_next_vblank(wa_crtc); 2011 intel_crtc_wait_for_next_vblank(wa_crtc); 2012 } 2013 } 2014 2015 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state) 2016 { 2017 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 2018 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2019 enum pipe pipe = crtc->pipe; 2020 2021 /* To avoid upsetting the power well on haswell only disable the pfit if 2022 * it's in use. The hw state code will make sure we get this right. */ 2023 if (!old_crtc_state->pch_pfit.enabled) 2024 return; 2025 2026 intel_de_write(dev_priv, PF_CTL(pipe), 0); 2027 intel_de_write(dev_priv, PF_WIN_POS(pipe), 0); 2028 intel_de_write(dev_priv, PF_WIN_SZ(pipe), 0); 2029 } 2030 2031 static void ilk_crtc_disable(struct intel_atomic_state *state, 2032 struct intel_crtc *crtc) 2033 { 2034 const struct intel_crtc_state *old_crtc_state = 2035 intel_atomic_get_old_crtc_state(state, crtc); 2036 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2037 enum pipe pipe = crtc->pipe; 2038 2039 /* 2040 * Sometimes spurious CPU pipe underruns happen when the 2041 * pipe is already disabled, but FDI RX/TX is still enabled. 2042 * Happens at least with VGA+HDMI cloning. Suppress them. 2043 */ 2044 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 2045 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 2046 2047 intel_encoders_disable(state, crtc); 2048 2049 intel_crtc_vblank_off(old_crtc_state); 2050 2051 intel_disable_transcoder(old_crtc_state); 2052 2053 ilk_pfit_disable(old_crtc_state); 2054 2055 if (old_crtc_state->has_pch_encoder) 2056 ilk_pch_disable(state, crtc); 2057 2058 intel_encoders_post_disable(state, crtc); 2059 2060 if (old_crtc_state->has_pch_encoder) 2061 ilk_pch_post_disable(state, crtc); 2062 2063 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2064 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 2065 } 2066 2067 static void hsw_crtc_disable(struct intel_atomic_state *state, 2068 struct intel_crtc *crtc) 2069 { 2070 const struct intel_crtc_state *old_crtc_state = 2071 intel_atomic_get_old_crtc_state(state, crtc); 2072 2073 /* 2074 * FIXME collapse everything to one hook. 2075 * Need care with mst->ddi interactions. 2076 */ 2077 if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) { 2078 intel_encoders_disable(state, crtc); 2079 intel_encoders_post_disable(state, crtc); 2080 } 2081 } 2082 2083 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) 2084 { 2085 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2086 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2087 2088 if (!crtc_state->gmch_pfit.control) 2089 return; 2090 2091 /* 2092 * The panel fitter should only be adjusted whilst the pipe is disabled, 2093 * according to register description and PRM. 2094 */ 2095 drm_WARN_ON(&dev_priv->drm, 2096 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE); 2097 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 2098 2099 intel_de_write(dev_priv, PFIT_PGM_RATIOS, 2100 crtc_state->gmch_pfit.pgm_ratios); 2101 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control); 2102 2103 /* Border color in case we don't scale up to the full screen. Black by 2104 * default, change to something else for debugging. */ 2105 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); 2106 } 2107 2108 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) 2109 { 2110 if (phy == PHY_NONE) 2111 return false; 2112 else if (IS_DG2(dev_priv)) 2113 /* 2114 * DG2 outputs labelled as "combo PHY" in the bspec use 2115 * SNPS PHYs with completely different programming, 2116 * hence we always return false here. 2117 */ 2118 return false; 2119 else if (IS_ALDERLAKE_S(dev_priv)) 2120 return phy <= PHY_E; 2121 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) 2122 return phy <= PHY_D; 2123 else if (IS_JSL_EHL(dev_priv)) 2124 return phy <= PHY_C; 2125 else if (DISPLAY_VER(dev_priv) >= 11) 2126 return phy <= PHY_B; 2127 else 2128 return false; 2129 } 2130 2131 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) 2132 { 2133 if (IS_DG2(dev_priv)) 2134 /* DG2's "TC1" output uses a SNPS PHY */ 2135 return false; 2136 else if (IS_ALDERLAKE_P(dev_priv)) 2137 return phy >= PHY_F && phy <= PHY_I; 2138 else if (IS_TIGERLAKE(dev_priv)) 2139 return phy >= PHY_D && phy <= PHY_I; 2140 else if (IS_ICELAKE(dev_priv)) 2141 return phy >= PHY_C && phy <= PHY_F; 2142 else 2143 return false; 2144 } 2145 2146 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy) 2147 { 2148 if (phy == PHY_NONE) 2149 return false; 2150 else if (IS_DG2(dev_priv)) 2151 /* 2152 * All four "combo" ports and the TC1 port (PHY E) use 2153 * Synopsis PHYs. 2154 */ 2155 return phy <= PHY_E; 2156 2157 return false; 2158 } 2159 2160 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) 2161 { 2162 if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD) 2163 return PHY_D + port - PORT_D_XELPD; 2164 else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1) 2165 return PHY_F + port - PORT_TC1; 2166 else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1) 2167 return PHY_B + port - PORT_TC1; 2168 else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1) 2169 return PHY_C + port - PORT_TC1; 2170 else if (IS_JSL_EHL(i915) && port == PORT_D) 2171 return PHY_A; 2172 2173 return PHY_A + port - PORT_A; 2174 } 2175 2176 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) 2177 { 2178 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port))) 2179 return TC_PORT_NONE; 2180 2181 if (DISPLAY_VER(dev_priv) >= 12) 2182 return TC_PORT_1 + port - PORT_TC1; 2183 else 2184 return TC_PORT_1 + port - PORT_C; 2185 } 2186 2187 enum intel_display_power_domain intel_port_to_power_domain(enum port port) 2188 { 2189 switch (port) { 2190 case PORT_A: 2191 return POWER_DOMAIN_PORT_DDI_A_LANES; 2192 case PORT_B: 2193 return POWER_DOMAIN_PORT_DDI_B_LANES; 2194 case PORT_C: 2195 return POWER_DOMAIN_PORT_DDI_C_LANES; 2196 case PORT_D: 2197 return POWER_DOMAIN_PORT_DDI_D_LANES; 2198 case PORT_E: 2199 return POWER_DOMAIN_PORT_DDI_E_LANES; 2200 case PORT_F: 2201 return POWER_DOMAIN_PORT_DDI_F_LANES; 2202 case PORT_G: 2203 return POWER_DOMAIN_PORT_DDI_G_LANES; 2204 case PORT_H: 2205 return POWER_DOMAIN_PORT_DDI_H_LANES; 2206 case PORT_I: 2207 return POWER_DOMAIN_PORT_DDI_I_LANES; 2208 default: 2209 MISSING_CASE(port); 2210 return POWER_DOMAIN_PORT_OTHER; 2211 } 2212 } 2213 2214 enum intel_display_power_domain 2215 intel_aux_power_domain(struct intel_digital_port *dig_port) 2216 { 2217 if (intel_tc_port_in_tbt_alt_mode(dig_port)) { 2218 switch (dig_port->aux_ch) { 2219 case AUX_CH_C: 2220 return POWER_DOMAIN_AUX_C_TBT; 2221 case AUX_CH_D: 2222 return POWER_DOMAIN_AUX_D_TBT; 2223 case AUX_CH_E: 2224 return POWER_DOMAIN_AUX_E_TBT; 2225 case AUX_CH_F: 2226 return POWER_DOMAIN_AUX_F_TBT; 2227 case AUX_CH_G: 2228 return POWER_DOMAIN_AUX_G_TBT; 2229 case AUX_CH_H: 2230 return POWER_DOMAIN_AUX_H_TBT; 2231 case AUX_CH_I: 2232 return POWER_DOMAIN_AUX_I_TBT; 2233 default: 2234 MISSING_CASE(dig_port->aux_ch); 2235 return POWER_DOMAIN_AUX_C_TBT; 2236 } 2237 } 2238 2239 return intel_legacy_aux_to_power_domain(dig_port->aux_ch); 2240 } 2241 2242 /* 2243 * Converts aux_ch to power_domain without caring about TBT ports for that use 2244 * intel_aux_power_domain() 2245 */ 2246 enum intel_display_power_domain 2247 intel_legacy_aux_to_power_domain(enum aux_ch aux_ch) 2248 { 2249 switch (aux_ch) { 2250 case AUX_CH_A: 2251 return POWER_DOMAIN_AUX_A; 2252 case AUX_CH_B: 2253 return POWER_DOMAIN_AUX_B; 2254 case AUX_CH_C: 2255 return POWER_DOMAIN_AUX_C; 2256 case AUX_CH_D: 2257 return POWER_DOMAIN_AUX_D; 2258 case AUX_CH_E: 2259 return POWER_DOMAIN_AUX_E; 2260 case AUX_CH_F: 2261 return POWER_DOMAIN_AUX_F; 2262 case AUX_CH_G: 2263 return POWER_DOMAIN_AUX_G; 2264 case AUX_CH_H: 2265 return POWER_DOMAIN_AUX_H; 2266 case AUX_CH_I: 2267 return POWER_DOMAIN_AUX_I; 2268 default: 2269 MISSING_CASE(aux_ch); 2270 return POWER_DOMAIN_AUX_A; 2271 } 2272 } 2273 2274 static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state) 2275 { 2276 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2277 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2278 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2279 struct drm_encoder *encoder; 2280 enum pipe pipe = crtc->pipe; 2281 u64 mask; 2282 2283 if (!crtc_state->hw.active) 2284 return 0; 2285 2286 mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe)); 2287 mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 2288 if (crtc_state->pch_pfit.enabled || 2289 crtc_state->pch_pfit.force_thru) 2290 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); 2291 2292 drm_for_each_encoder_mask(encoder, &dev_priv->drm, 2293 crtc_state->uapi.encoder_mask) { 2294 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2295 2296 mask |= BIT_ULL(intel_encoder->power_domain); 2297 } 2298 2299 if (HAS_DDI(dev_priv) && crtc_state->has_audio) 2300 mask |= BIT_ULL(POWER_DOMAIN_AUDIO_MMIO); 2301 2302 if (crtc_state->shared_dpll) 2303 mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE); 2304 2305 if (crtc_state->dsc.compression_enable) 2306 mask |= BIT_ULL(intel_dsc_power_domain(crtc, cpu_transcoder)); 2307 2308 return mask; 2309 } 2310 2311 static u64 2312 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state) 2313 { 2314 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2315 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2316 enum intel_display_power_domain domain; 2317 u64 domains, new_domains, old_domains; 2318 2319 domains = get_crtc_power_domains(crtc_state); 2320 2321 new_domains = domains & ~crtc->enabled_power_domains.mask; 2322 old_domains = crtc->enabled_power_domains.mask & ~domains; 2323 2324 for_each_power_domain(domain, new_domains) 2325 intel_display_power_get_in_set(dev_priv, 2326 &crtc->enabled_power_domains, 2327 domain); 2328 2329 return old_domains; 2330 } 2331 2332 static void modeset_put_crtc_power_domains(struct intel_crtc *crtc, 2333 u64 domains) 2334 { 2335 intel_display_power_put_mask_in_set(to_i915(crtc->base.dev), 2336 &crtc->enabled_power_domains, 2337 domains); 2338 } 2339 2340 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 2341 { 2342 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2343 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2344 2345 if (intel_crtc_has_dp_encoder(crtc_state)) { 2346 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 2347 &crtc_state->dp_m_n); 2348 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 2349 &crtc_state->dp_m2_n2); 2350 } 2351 2352 intel_set_transcoder_timings(crtc_state); 2353 2354 i9xx_set_pipeconf(crtc_state); 2355 } 2356 2357 static void valleyview_crtc_enable(struct intel_atomic_state *state, 2358 struct intel_crtc *crtc) 2359 { 2360 const struct intel_crtc_state *new_crtc_state = 2361 intel_atomic_get_new_crtc_state(state, crtc); 2362 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2363 enum pipe pipe = crtc->pipe; 2364 2365 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 2366 return; 2367 2368 i9xx_configure_cpu_transcoder(new_crtc_state); 2369 2370 intel_set_pipe_src_size(new_crtc_state); 2371 2372 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 2373 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY); 2374 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0); 2375 } 2376 2377 crtc->active = true; 2378 2379 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2380 2381 intel_encoders_pre_pll_enable(state, crtc); 2382 2383 if (IS_CHERRYVIEW(dev_priv)) 2384 chv_enable_pll(new_crtc_state); 2385 else 2386 vlv_enable_pll(new_crtc_state); 2387 2388 intel_encoders_pre_enable(state, crtc); 2389 2390 i9xx_pfit_enable(new_crtc_state); 2391 2392 intel_color_load_luts(new_crtc_state); 2393 intel_color_commit(new_crtc_state); 2394 /* update DSPCNTR to configure gamma for pipe bottom color */ 2395 intel_disable_primary_plane(new_crtc_state); 2396 2397 intel_initial_watermarks(state, crtc); 2398 intel_enable_transcoder(new_crtc_state); 2399 2400 intel_crtc_vblank_on(new_crtc_state); 2401 2402 intel_encoders_enable(state, crtc); 2403 } 2404 2405 static void i9xx_crtc_enable(struct intel_atomic_state *state, 2406 struct intel_crtc *crtc) 2407 { 2408 const struct intel_crtc_state *new_crtc_state = 2409 intel_atomic_get_new_crtc_state(state, crtc); 2410 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2411 enum pipe pipe = crtc->pipe; 2412 2413 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 2414 return; 2415 2416 i9xx_configure_cpu_transcoder(new_crtc_state); 2417 2418 intel_set_pipe_src_size(new_crtc_state); 2419 2420 crtc->active = true; 2421 2422 if (DISPLAY_VER(dev_priv) != 2) 2423 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2424 2425 intel_encoders_pre_enable(state, crtc); 2426 2427 i9xx_enable_pll(new_crtc_state); 2428 2429 i9xx_pfit_enable(new_crtc_state); 2430 2431 intel_color_load_luts(new_crtc_state); 2432 intel_color_commit(new_crtc_state); 2433 /* update DSPCNTR to configure gamma for pipe bottom color */ 2434 intel_disable_primary_plane(new_crtc_state); 2435 2436 if (!intel_initial_watermarks(state, crtc)) 2437 intel_update_watermarks(dev_priv); 2438 intel_enable_transcoder(new_crtc_state); 2439 2440 intel_crtc_vblank_on(new_crtc_state); 2441 2442 intel_encoders_enable(state, crtc); 2443 2444 /* prevents spurious underruns */ 2445 if (DISPLAY_VER(dev_priv) == 2) 2446 intel_crtc_wait_for_next_vblank(crtc); 2447 } 2448 2449 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) 2450 { 2451 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 2452 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2453 2454 if (!old_crtc_state->gmch_pfit.control) 2455 return; 2456 2457 assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder); 2458 2459 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n", 2460 intel_de_read(dev_priv, PFIT_CONTROL)); 2461 intel_de_write(dev_priv, PFIT_CONTROL, 0); 2462 } 2463 2464 static void i9xx_crtc_disable(struct intel_atomic_state *state, 2465 struct intel_crtc *crtc) 2466 { 2467 struct intel_crtc_state *old_crtc_state = 2468 intel_atomic_get_old_crtc_state(state, crtc); 2469 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2470 enum pipe pipe = crtc->pipe; 2471 2472 /* 2473 * On gen2 planes are double buffered but the pipe isn't, so we must 2474 * wait for planes to fully turn off before disabling the pipe. 2475 */ 2476 if (DISPLAY_VER(dev_priv) == 2) 2477 intel_crtc_wait_for_next_vblank(crtc); 2478 2479 intel_encoders_disable(state, crtc); 2480 2481 intel_crtc_vblank_off(old_crtc_state); 2482 2483 intel_disable_transcoder(old_crtc_state); 2484 2485 i9xx_pfit_disable(old_crtc_state); 2486 2487 intel_encoders_post_disable(state, crtc); 2488 2489 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) { 2490 if (IS_CHERRYVIEW(dev_priv)) 2491 chv_disable_pll(dev_priv, pipe); 2492 else if (IS_VALLEYVIEW(dev_priv)) 2493 vlv_disable_pll(dev_priv, pipe); 2494 else 2495 i9xx_disable_pll(old_crtc_state); 2496 } 2497 2498 intel_encoders_post_pll_disable(state, crtc); 2499 2500 if (DISPLAY_VER(dev_priv) != 2) 2501 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 2502 2503 if (!dev_priv->wm_disp->initial_watermarks) 2504 intel_update_watermarks(dev_priv); 2505 2506 /* clock the pipe down to 640x480@60 to potentially save power */ 2507 if (IS_I830(dev_priv)) 2508 i830_enable_pipe(dev_priv, pipe); 2509 } 2510 2511 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, 2512 struct drm_modeset_acquire_ctx *ctx) 2513 { 2514 struct intel_encoder *encoder; 2515 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2516 struct intel_bw_state *bw_state = 2517 to_intel_bw_state(dev_priv->bw_obj.state); 2518 struct intel_cdclk_state *cdclk_state = 2519 to_intel_cdclk_state(dev_priv->cdclk.obj.state); 2520 struct intel_dbuf_state *dbuf_state = 2521 to_intel_dbuf_state(dev_priv->dbuf.obj.state); 2522 struct intel_crtc_state *crtc_state = 2523 to_intel_crtc_state(crtc->base.state); 2524 struct intel_plane *plane; 2525 struct drm_atomic_state *state; 2526 struct intel_crtc_state *temp_crtc_state; 2527 enum pipe pipe = crtc->pipe; 2528 int ret; 2529 2530 if (!crtc_state->hw.active) 2531 return; 2532 2533 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 2534 const struct intel_plane_state *plane_state = 2535 to_intel_plane_state(plane->base.state); 2536 2537 if (plane_state->uapi.visible) 2538 intel_plane_disable_noatomic(crtc, plane); 2539 } 2540 2541 state = drm_atomic_state_alloc(&dev_priv->drm); 2542 if (!state) { 2543 drm_dbg_kms(&dev_priv->drm, 2544 "failed to disable [CRTC:%d:%s], out of memory", 2545 crtc->base.base.id, crtc->base.name); 2546 return; 2547 } 2548 2549 state->acquire_ctx = ctx; 2550 2551 /* Everything's already locked, -EDEADLK can't happen. */ 2552 temp_crtc_state = intel_atomic_get_crtc_state(state, crtc); 2553 ret = drm_atomic_add_affected_connectors(state, &crtc->base); 2554 2555 drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret); 2556 2557 dev_priv->display->crtc_disable(to_intel_atomic_state(state), crtc); 2558 2559 drm_atomic_state_put(state); 2560 2561 drm_dbg_kms(&dev_priv->drm, 2562 "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", 2563 crtc->base.base.id, crtc->base.name); 2564 2565 crtc->active = false; 2566 crtc->base.enabled = false; 2567 2568 drm_WARN_ON(&dev_priv->drm, 2569 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0); 2570 crtc_state->uapi.active = false; 2571 crtc_state->uapi.connector_mask = 0; 2572 crtc_state->uapi.encoder_mask = 0; 2573 intel_crtc_free_hw_state(crtc_state); 2574 memset(&crtc_state->hw, 0, sizeof(crtc_state->hw)); 2575 2576 for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder) 2577 encoder->base.crtc = NULL; 2578 2579 intel_fbc_disable(crtc); 2580 intel_update_watermarks(dev_priv); 2581 intel_disable_shared_dpll(crtc_state); 2582 2583 intel_display_power_put_all_in_set(dev_priv, &crtc->enabled_power_domains); 2584 2585 cdclk_state->min_cdclk[pipe] = 0; 2586 cdclk_state->min_voltage_level[pipe] = 0; 2587 cdclk_state->active_pipes &= ~BIT(pipe); 2588 2589 dbuf_state->active_pipes &= ~BIT(pipe); 2590 2591 bw_state->data_rate[pipe] = 0; 2592 bw_state->num_active_planes[pipe] = 0; 2593 } 2594 2595 /* 2596 * turn all crtc's off, but do not adjust state 2597 * This has to be paired with a call to intel_modeset_setup_hw_state. 2598 */ 2599 int intel_display_suspend(struct drm_device *dev) 2600 { 2601 struct drm_i915_private *dev_priv = to_i915(dev); 2602 struct drm_atomic_state *state; 2603 int ret; 2604 2605 if (!HAS_DISPLAY(dev_priv)) 2606 return 0; 2607 2608 state = drm_atomic_helper_suspend(dev); 2609 ret = PTR_ERR_OR_ZERO(state); 2610 if (ret) 2611 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", 2612 ret); 2613 else 2614 dev_priv->modeset_restore_state = state; 2615 return ret; 2616 } 2617 2618 void intel_encoder_destroy(struct drm_encoder *encoder) 2619 { 2620 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2621 2622 drm_encoder_cleanup(encoder); 2623 kfree(intel_encoder); 2624 } 2625 2626 /* Cross check the actual hw state with our own modeset state tracking (and it's 2627 * internal consistency). */ 2628 static void intel_connector_verify_state(struct intel_crtc_state *crtc_state, 2629 struct drm_connector_state *conn_state) 2630 { 2631 struct intel_connector *connector = to_intel_connector(conn_state->connector); 2632 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2633 2634 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", 2635 connector->base.base.id, connector->base.name); 2636 2637 if (connector->get_hw_state(connector)) { 2638 struct intel_encoder *encoder = intel_attached_encoder(connector); 2639 2640 I915_STATE_WARN(!crtc_state, 2641 "connector enabled without attached crtc\n"); 2642 2643 if (!crtc_state) 2644 return; 2645 2646 I915_STATE_WARN(!crtc_state->hw.active, 2647 "connector is active, but attached crtc isn't\n"); 2648 2649 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) 2650 return; 2651 2652 I915_STATE_WARN(conn_state->best_encoder != &encoder->base, 2653 "atomic encoder doesn't match attached encoder\n"); 2654 2655 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, 2656 "attached encoder crtc differs from connector crtc\n"); 2657 } else { 2658 I915_STATE_WARN(crtc_state && crtc_state->hw.active, 2659 "attached crtc is active, but connector isn't\n"); 2660 I915_STATE_WARN(!crtc_state && conn_state->best_encoder, 2661 "best encoder set without crtc!\n"); 2662 } 2663 } 2664 2665 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) 2666 { 2667 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2668 2669 /* GDG double wide on either pipe, otherwise pipe A only */ 2670 return DISPLAY_VER(dev_priv) < 4 && 2671 (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); 2672 } 2673 2674 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) 2675 { 2676 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock; 2677 struct drm_rect src; 2678 2679 /* 2680 * We only use IF-ID interlacing. If we ever use 2681 * PF-ID we'll need to adjust the pixel_rate here. 2682 */ 2683 2684 if (!crtc_state->pch_pfit.enabled) 2685 return pixel_rate; 2686 2687 drm_rect_init(&src, 0, 0, 2688 drm_rect_width(&crtc_state->pipe_src) << 16, 2689 drm_rect_height(&crtc_state->pipe_src) << 16); 2690 2691 return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst, 2692 pixel_rate); 2693 } 2694 2695 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode, 2696 const struct drm_display_mode *timings) 2697 { 2698 mode->hdisplay = timings->crtc_hdisplay; 2699 mode->htotal = timings->crtc_htotal; 2700 mode->hsync_start = timings->crtc_hsync_start; 2701 mode->hsync_end = timings->crtc_hsync_end; 2702 2703 mode->vdisplay = timings->crtc_vdisplay; 2704 mode->vtotal = timings->crtc_vtotal; 2705 mode->vsync_start = timings->crtc_vsync_start; 2706 mode->vsync_end = timings->crtc_vsync_end; 2707 2708 mode->flags = timings->flags; 2709 mode->type = DRM_MODE_TYPE_DRIVER; 2710 2711 mode->clock = timings->crtc_clock; 2712 2713 drm_mode_set_name(mode); 2714 } 2715 2716 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) 2717 { 2718 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2719 2720 if (HAS_GMCH(dev_priv)) 2721 /* FIXME calculate proper pipe pixel rate for GMCH pfit */ 2722 crtc_state->pixel_rate = 2723 crtc_state->hw.pipe_mode.crtc_clock; 2724 else 2725 crtc_state->pixel_rate = 2726 ilk_pipe_pixel_rate(crtc_state); 2727 } 2728 2729 static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state *crtc_state, 2730 struct drm_display_mode *mode) 2731 { 2732 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2733 2734 if (num_pipes < 2) 2735 return; 2736 2737 mode->crtc_clock /= num_pipes; 2738 mode->crtc_hdisplay /= num_pipes; 2739 mode->crtc_hblank_start /= num_pipes; 2740 mode->crtc_hblank_end /= num_pipes; 2741 mode->crtc_hsync_start /= num_pipes; 2742 mode->crtc_hsync_end /= num_pipes; 2743 mode->crtc_htotal /= num_pipes; 2744 } 2745 2746 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state, 2747 struct drm_display_mode *mode) 2748 { 2749 int overlap = crtc_state->splitter.pixel_overlap; 2750 int n = crtc_state->splitter.link_count; 2751 2752 if (!crtc_state->splitter.enable) 2753 return; 2754 2755 /* 2756 * eDP MSO uses segment timings from EDID for transcoder 2757 * timings, but full mode for everything else. 2758 * 2759 * h_full = (h_segment - pixel_overlap) * link_count 2760 */ 2761 mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n; 2762 mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n; 2763 mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n; 2764 mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n; 2765 mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n; 2766 mode->crtc_htotal = (mode->crtc_htotal - overlap) * n; 2767 mode->crtc_clock *= n; 2768 } 2769 2770 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state) 2771 { 2772 struct drm_display_mode *mode = &crtc_state->hw.mode; 2773 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2774 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2775 2776 /* 2777 * Start with the adjusted_mode crtc timings, which 2778 * have been filled with the transcoder timings. 2779 */ 2780 drm_mode_copy(pipe_mode, adjusted_mode); 2781 2782 /* Expand MSO per-segment transcoder timings to full */ 2783 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2784 2785 /* 2786 * We want the full numbers in adjusted_mode normal timings, 2787 * adjusted_mode crtc timings are left with the raw transcoder 2788 * timings. 2789 */ 2790 intel_mode_from_crtc_timings(adjusted_mode, pipe_mode); 2791 2792 /* Populate the "user" mode with full numbers */ 2793 drm_mode_copy(mode, pipe_mode); 2794 intel_mode_from_crtc_timings(mode, mode); 2795 mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) * 2796 (intel_bigjoiner_num_pipes(crtc_state) ?: 1); 2797 mode->vdisplay = drm_rect_height(&crtc_state->pipe_src); 2798 2799 /* Derive per-pipe timings in case bigjoiner is used */ 2800 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2801 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2802 2803 intel_crtc_compute_pixel_rate(crtc_state); 2804 } 2805 2806 static void intel_encoder_get_config(struct intel_encoder *encoder, 2807 struct intel_crtc_state *crtc_state) 2808 { 2809 encoder->get_config(encoder, crtc_state); 2810 2811 intel_crtc_readout_derived_state(crtc_state); 2812 } 2813 2814 static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state *crtc_state) 2815 { 2816 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2817 int width, height; 2818 2819 if (num_pipes < 2) 2820 return; 2821 2822 width = drm_rect_width(&crtc_state->pipe_src); 2823 height = drm_rect_height(&crtc_state->pipe_src); 2824 2825 drm_rect_init(&crtc_state->pipe_src, 0, 0, 2826 width / num_pipes, height); 2827 } 2828 2829 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state) 2830 { 2831 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2832 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2833 2834 intel_bigjoiner_compute_pipe_src(crtc_state); 2835 2836 /* 2837 * Pipe horizontal size must be even in: 2838 * - DVO ganged mode 2839 * - LVDS dual channel mode 2840 * - Double wide pipe 2841 */ 2842 if (drm_rect_width(&crtc_state->pipe_src) & 1) { 2843 if (crtc_state->double_wide) { 2844 drm_dbg_kms(&i915->drm, 2845 "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n", 2846 crtc->base.base.id, crtc->base.name); 2847 return -EINVAL; 2848 } 2849 2850 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 2851 intel_is_dual_link_lvds(i915)) { 2852 drm_dbg_kms(&i915->drm, 2853 "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n", 2854 crtc->base.base.id, crtc->base.name); 2855 return -EINVAL; 2856 } 2857 } 2858 2859 return 0; 2860 } 2861 2862 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state) 2863 { 2864 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2865 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2866 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2867 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2868 int clock_limit = i915->max_dotclk_freq; 2869 2870 /* 2871 * Start with the adjusted_mode crtc timings, which 2872 * have been filled with the transcoder timings. 2873 */ 2874 drm_mode_copy(pipe_mode, adjusted_mode); 2875 2876 /* Expand MSO per-segment transcoder timings to full */ 2877 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2878 2879 /* Derive per-pipe timings in case bigjoiner is used */ 2880 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2881 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2882 2883 if (DISPLAY_VER(i915) < 4) { 2884 clock_limit = i915->max_cdclk_freq * 9 / 10; 2885 2886 /* 2887 * Enable double wide mode when the dot clock 2888 * is > 90% of the (display) core speed. 2889 */ 2890 if (intel_crtc_supports_double_wide(crtc) && 2891 pipe_mode->crtc_clock > clock_limit) { 2892 clock_limit = i915->max_dotclk_freq; 2893 crtc_state->double_wide = true; 2894 } 2895 } 2896 2897 if (pipe_mode->crtc_clock > clock_limit) { 2898 drm_dbg_kms(&i915->drm, 2899 "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", 2900 crtc->base.base.id, crtc->base.name, 2901 pipe_mode->crtc_clock, clock_limit, 2902 str_yes_no(crtc_state->double_wide)); 2903 return -EINVAL; 2904 } 2905 2906 return 0; 2907 } 2908 2909 static int intel_crtc_compute_config(struct intel_crtc *crtc, 2910 struct intel_crtc_state *crtc_state) 2911 { 2912 int ret; 2913 2914 ret = intel_crtc_compute_pipe_src(crtc_state); 2915 if (ret) 2916 return ret; 2917 2918 ret = intel_crtc_compute_pipe_mode(crtc_state); 2919 if (ret) 2920 return ret; 2921 2922 intel_crtc_compute_pixel_rate(crtc_state); 2923 2924 if (crtc_state->has_pch_encoder) 2925 return ilk_fdi_compute_config(crtc, crtc_state); 2926 2927 return 0; 2928 } 2929 2930 static void 2931 intel_reduce_m_n_ratio(u32 *num, u32 *den) 2932 { 2933 while (*num > DATA_LINK_M_N_MASK || 2934 *den > DATA_LINK_M_N_MASK) { 2935 *num >>= 1; 2936 *den >>= 1; 2937 } 2938 } 2939 2940 static void compute_m_n(unsigned int m, unsigned int n, 2941 u32 *ret_m, u32 *ret_n, 2942 bool constant_n) 2943 { 2944 /* 2945 * Several DP dongles in particular seem to be fussy about 2946 * too large link M/N values. Give N value as 0x8000 that 2947 * should be acceptable by specific devices. 0x8000 is the 2948 * specified fixed N value for asynchronous clock mode, 2949 * which the devices expect also in synchronous clock mode. 2950 */ 2951 if (constant_n) 2952 *ret_n = DP_LINK_CONSTANT_N_VALUE; 2953 else 2954 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); 2955 2956 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n); 2957 intel_reduce_m_n_ratio(ret_m, ret_n); 2958 } 2959 2960 void 2961 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes, 2962 int pixel_clock, int link_clock, 2963 struct intel_link_m_n *m_n, 2964 bool constant_n, bool fec_enable) 2965 { 2966 u32 data_clock = bits_per_pixel * pixel_clock; 2967 2968 if (fec_enable) 2969 data_clock = intel_dp_mode_to_fec_clock(data_clock); 2970 2971 m_n->tu = 64; 2972 compute_m_n(data_clock, 2973 link_clock * nlanes * 8, 2974 &m_n->data_m, &m_n->data_n, 2975 constant_n); 2976 2977 compute_m_n(pixel_clock, link_clock, 2978 &m_n->link_m, &m_n->link_n, 2979 constant_n); 2980 } 2981 2982 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv) 2983 { 2984 /* 2985 * There may be no VBT; and if the BIOS enabled SSC we can 2986 * just keep using it to avoid unnecessary flicker. Whereas if the 2987 * BIOS isn't using it, don't assume it will work even if the VBT 2988 * indicates as much. 2989 */ 2990 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { 2991 bool bios_lvds_use_ssc = intel_de_read(dev_priv, 2992 PCH_DREF_CONTROL) & 2993 DREF_SSC1_ENABLE; 2994 2995 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { 2996 drm_dbg_kms(&dev_priv->drm, 2997 "SSC %s by BIOS, overriding VBT which says %s\n", 2998 str_enabled_disabled(bios_lvds_use_ssc), 2999 str_enabled_disabled(dev_priv->vbt.lvds_use_ssc)); 3000 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; 3001 } 3002 } 3003 } 3004 3005 void intel_zero_m_n(struct intel_link_m_n *m_n) 3006 { 3007 /* corresponds to 0 register value */ 3008 memset(m_n, 0, sizeof(*m_n)); 3009 m_n->tu = 1; 3010 } 3011 3012 void intel_set_m_n(struct drm_i915_private *i915, 3013 const struct intel_link_m_n *m_n, 3014 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 3015 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 3016 { 3017 intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); 3018 intel_de_write(i915, data_n_reg, m_n->data_n); 3019 intel_de_write(i915, link_m_reg, m_n->link_m); 3020 /* 3021 * On BDW+ writing LINK_N arms the double buffered update 3022 * of all the M/N registers, so it must be written last. 3023 */ 3024 intel_de_write(i915, link_n_reg, m_n->link_n); 3025 } 3026 3027 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, 3028 enum transcoder transcoder) 3029 { 3030 if (IS_HASWELL(dev_priv)) 3031 return transcoder == TRANSCODER_EDP; 3032 3033 return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv); 3034 } 3035 3036 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, 3037 enum transcoder transcoder, 3038 const struct intel_link_m_n *m_n) 3039 { 3040 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3041 enum pipe pipe = crtc->pipe; 3042 3043 if (DISPLAY_VER(dev_priv) >= 5) 3044 intel_set_m_n(dev_priv, m_n, 3045 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 3046 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 3047 else 3048 intel_set_m_n(dev_priv, m_n, 3049 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 3050 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 3051 } 3052 3053 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, 3054 enum transcoder transcoder, 3055 const struct intel_link_m_n *m_n) 3056 { 3057 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3058 3059 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 3060 return; 3061 3062 intel_set_m_n(dev_priv, m_n, 3063 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 3064 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 3065 } 3066 3067 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) 3068 { 3069 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3070 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3071 enum pipe pipe = crtc->pipe; 3072 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3073 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 3074 u32 crtc_vtotal, crtc_vblank_end; 3075 int vsyncshift = 0; 3076 3077 /* We need to be careful not to changed the adjusted mode, for otherwise 3078 * the hw state checker will get angry at the mismatch. */ 3079 crtc_vtotal = adjusted_mode->crtc_vtotal; 3080 crtc_vblank_end = adjusted_mode->crtc_vblank_end; 3081 3082 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 3083 /* the chip adds 2 halflines automatically */ 3084 crtc_vtotal -= 1; 3085 crtc_vblank_end -= 1; 3086 3087 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3088 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; 3089 else 3090 vsyncshift = adjusted_mode->crtc_hsync_start - 3091 adjusted_mode->crtc_htotal / 2; 3092 if (vsyncshift < 0) 3093 vsyncshift += adjusted_mode->crtc_htotal; 3094 } 3095 3096 if (DISPLAY_VER(dev_priv) > 3) 3097 intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder), 3098 vsyncshift); 3099 3100 intel_de_write(dev_priv, HTOTAL(cpu_transcoder), 3101 (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16)); 3102 intel_de_write(dev_priv, HBLANK(cpu_transcoder), 3103 (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16)); 3104 intel_de_write(dev_priv, HSYNC(cpu_transcoder), 3105 (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16)); 3106 3107 intel_de_write(dev_priv, VTOTAL(cpu_transcoder), 3108 (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16)); 3109 intel_de_write(dev_priv, VBLANK(cpu_transcoder), 3110 (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16)); 3111 intel_de_write(dev_priv, VSYNC(cpu_transcoder), 3112 (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16)); 3113 3114 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be 3115 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is 3116 * documented on the DDI_FUNC_CTL register description, EDP Input Select 3117 * bits. */ 3118 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && 3119 (pipe == PIPE_B || pipe == PIPE_C)) 3120 intel_de_write(dev_priv, VTOTAL(pipe), 3121 intel_de_read(dev_priv, VTOTAL(cpu_transcoder))); 3122 3123 } 3124 3125 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) 3126 { 3127 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3128 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3129 int width = drm_rect_width(&crtc_state->pipe_src); 3130 int height = drm_rect_height(&crtc_state->pipe_src); 3131 enum pipe pipe = crtc->pipe; 3132 3133 /* pipesrc controls the size that is scaled from, which should 3134 * always be the user's requested size. 3135 */ 3136 intel_de_write(dev_priv, PIPESRC(pipe), 3137 PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1)); 3138 } 3139 3140 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) 3141 { 3142 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3143 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3144 3145 if (DISPLAY_VER(dev_priv) == 2) 3146 return false; 3147 3148 if (DISPLAY_VER(dev_priv) >= 9 || 3149 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 3150 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW; 3151 else 3152 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK; 3153 } 3154 3155 static void intel_get_transcoder_timings(struct intel_crtc *crtc, 3156 struct intel_crtc_state *pipe_config) 3157 { 3158 struct drm_device *dev = crtc->base.dev; 3159 struct drm_i915_private *dev_priv = to_i915(dev); 3160 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3161 u32 tmp; 3162 3163 tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder)); 3164 pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; 3165 pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; 3166 3167 if (!transcoder_is_dsi(cpu_transcoder)) { 3168 tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder)); 3169 pipe_config->hw.adjusted_mode.crtc_hblank_start = 3170 (tmp & 0xffff) + 1; 3171 pipe_config->hw.adjusted_mode.crtc_hblank_end = 3172 ((tmp >> 16) & 0xffff) + 1; 3173 } 3174 tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder)); 3175 pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; 3176 pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; 3177 3178 tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder)); 3179 pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; 3180 pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; 3181 3182 if (!transcoder_is_dsi(cpu_transcoder)) { 3183 tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder)); 3184 pipe_config->hw.adjusted_mode.crtc_vblank_start = 3185 (tmp & 0xffff) + 1; 3186 pipe_config->hw.adjusted_mode.crtc_vblank_end = 3187 ((tmp >> 16) & 0xffff) + 1; 3188 } 3189 tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder)); 3190 pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; 3191 pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; 3192 3193 if (intel_pipe_is_interlaced(pipe_config)) { 3194 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; 3195 pipe_config->hw.adjusted_mode.crtc_vtotal += 1; 3196 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1; 3197 } 3198 } 3199 3200 static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state) 3201 { 3202 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3203 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 3204 enum pipe master_pipe, pipe = crtc->pipe; 3205 int width; 3206 3207 if (num_pipes < 2) 3208 return; 3209 3210 master_pipe = bigjoiner_master_pipe(crtc_state); 3211 width = drm_rect_width(&crtc_state->pipe_src); 3212 3213 drm_rect_translate_to(&crtc_state->pipe_src, 3214 (pipe - master_pipe) * width, 0); 3215 } 3216 3217 static void intel_get_pipe_src_size(struct intel_crtc *crtc, 3218 struct intel_crtc_state *pipe_config) 3219 { 3220 struct drm_device *dev = crtc->base.dev; 3221 struct drm_i915_private *dev_priv = to_i915(dev); 3222 u32 tmp; 3223 3224 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe)); 3225 3226 drm_rect_init(&pipe_config->pipe_src, 0, 0, 3227 REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1, 3228 REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1); 3229 3230 intel_bigjoiner_adjust_pipe_src(pipe_config); 3231 } 3232 3233 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) 3234 { 3235 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3236 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3237 u32 pipeconf = 0; 3238 3239 /* we keep both pipes enabled on 830 */ 3240 if (IS_I830(dev_priv)) 3241 pipeconf |= PIPECONF_ENABLE; 3242 3243 if (crtc_state->double_wide) 3244 pipeconf |= PIPECONF_DOUBLE_WIDE; 3245 3246 /* only g4x and later have fancy bpc/dither controls */ 3247 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 3248 IS_CHERRYVIEW(dev_priv)) { 3249 /* Bspec claims that we can't use dithering for 30bpp pipes. */ 3250 if (crtc_state->dither && crtc_state->pipe_bpp != 30) 3251 pipeconf |= PIPECONF_DITHER_EN | 3252 PIPECONF_DITHER_TYPE_SP; 3253 3254 switch (crtc_state->pipe_bpp) { 3255 case 18: 3256 pipeconf |= PIPECONF_BPC_6; 3257 break; 3258 case 24: 3259 pipeconf |= PIPECONF_BPC_8; 3260 break; 3261 case 30: 3262 pipeconf |= PIPECONF_BPC_10; 3263 break; 3264 default: 3265 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3266 BUG(); 3267 } 3268 } 3269 3270 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 3271 if (DISPLAY_VER(dev_priv) < 4 || 3272 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3273 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; 3274 else 3275 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; 3276 } else { 3277 pipeconf |= PIPECONF_INTERLACE_PROGRESSIVE; 3278 } 3279 3280 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 3281 crtc_state->limited_color_range) 3282 pipeconf |= PIPECONF_COLOR_RANGE_SELECT; 3283 3284 pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); 3285 3286 pipeconf |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3287 3288 intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf); 3289 intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe)); 3290 } 3291 3292 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv) 3293 { 3294 if (IS_I830(dev_priv)) 3295 return false; 3296 3297 return DISPLAY_VER(dev_priv) >= 4 || 3298 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); 3299 } 3300 3301 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state) 3302 { 3303 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3304 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3305 u32 tmp; 3306 3307 if (!i9xx_has_pfit(dev_priv)) 3308 return; 3309 3310 tmp = intel_de_read(dev_priv, PFIT_CONTROL); 3311 if (!(tmp & PFIT_ENABLE)) 3312 return; 3313 3314 /* Check whether the pfit is attached to our pipe. */ 3315 if (DISPLAY_VER(dev_priv) < 4) { 3316 if (crtc->pipe != PIPE_B) 3317 return; 3318 } else { 3319 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) 3320 return; 3321 } 3322 3323 crtc_state->gmch_pfit.control = tmp; 3324 crtc_state->gmch_pfit.pgm_ratios = 3325 intel_de_read(dev_priv, PFIT_PGM_RATIOS); 3326 } 3327 3328 static void vlv_crtc_clock_get(struct intel_crtc *crtc, 3329 struct intel_crtc_state *pipe_config) 3330 { 3331 struct drm_device *dev = crtc->base.dev; 3332 struct drm_i915_private *dev_priv = to_i915(dev); 3333 enum pipe pipe = crtc->pipe; 3334 struct dpll clock; 3335 u32 mdiv; 3336 int refclk = 100000; 3337 3338 /* In case of DSI, DPLL will not be used */ 3339 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 3340 return; 3341 3342 vlv_dpio_get(dev_priv); 3343 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); 3344 vlv_dpio_put(dev_priv); 3345 3346 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; 3347 clock.m2 = mdiv & DPIO_M2DIV_MASK; 3348 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; 3349 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; 3350 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; 3351 3352 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); 3353 } 3354 3355 static void chv_crtc_clock_get(struct intel_crtc *crtc, 3356 struct intel_crtc_state *pipe_config) 3357 { 3358 struct drm_device *dev = crtc->base.dev; 3359 struct drm_i915_private *dev_priv = to_i915(dev); 3360 enum pipe pipe = crtc->pipe; 3361 enum dpio_channel port = vlv_pipe_to_channel(pipe); 3362 struct dpll clock; 3363 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; 3364 int refclk = 100000; 3365 3366 /* In case of DSI, DPLL will not be used */ 3367 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 3368 return; 3369 3370 vlv_dpio_get(dev_priv); 3371 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); 3372 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); 3373 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); 3374 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); 3375 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); 3376 vlv_dpio_put(dev_priv); 3377 3378 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; 3379 clock.m2 = (pll_dw0 & 0xff) << 22; 3380 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) 3381 clock.m2 |= pll_dw2 & 0x3fffff; 3382 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; 3383 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; 3384 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; 3385 3386 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); 3387 } 3388 3389 static enum intel_output_format 3390 bdw_get_pipemisc_output_format(struct intel_crtc *crtc) 3391 { 3392 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3393 u32 tmp; 3394 3395 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); 3396 3397 if (tmp & PIPEMISC_YUV420_ENABLE) { 3398 /* We support 4:2:0 in full blend mode only */ 3399 drm_WARN_ON(&dev_priv->drm, 3400 (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0); 3401 3402 return INTEL_OUTPUT_FORMAT_YCBCR420; 3403 } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) { 3404 return INTEL_OUTPUT_FORMAT_YCBCR444; 3405 } else { 3406 return INTEL_OUTPUT_FORMAT_RGB; 3407 } 3408 } 3409 3410 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state) 3411 { 3412 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3413 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 3414 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3415 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 3416 u32 tmp; 3417 3418 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); 3419 3420 if (tmp & DISP_PIPE_GAMMA_ENABLE) 3421 crtc_state->gamma_enable = true; 3422 3423 if (!HAS_GMCH(dev_priv) && 3424 tmp & DISP_PIPE_CSC_ENABLE) 3425 crtc_state->csc_enable = true; 3426 } 3427 3428 static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 3429 struct intel_crtc_state *pipe_config) 3430 { 3431 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3432 enum intel_display_power_domain power_domain; 3433 intel_wakeref_t wakeref; 3434 u32 tmp; 3435 bool ret; 3436 3437 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3438 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3439 if (!wakeref) 3440 return false; 3441 3442 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3443 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3444 pipe_config->shared_dpll = NULL; 3445 3446 ret = false; 3447 3448 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); 3449 if (!(tmp & PIPECONF_ENABLE)) 3450 goto out; 3451 3452 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 3453 IS_CHERRYVIEW(dev_priv)) { 3454 switch (tmp & PIPECONF_BPC_MASK) { 3455 case PIPECONF_BPC_6: 3456 pipe_config->pipe_bpp = 18; 3457 break; 3458 case PIPECONF_BPC_8: 3459 pipe_config->pipe_bpp = 24; 3460 break; 3461 case PIPECONF_BPC_10: 3462 pipe_config->pipe_bpp = 30; 3463 break; 3464 default: 3465 MISSING_CASE(tmp); 3466 break; 3467 } 3468 } 3469 3470 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 3471 (tmp & PIPECONF_COLOR_RANGE_SELECT)) 3472 pipe_config->limited_color_range = true; 3473 3474 pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_I9XX, tmp); 3475 3476 pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1; 3477 3478 if (IS_CHERRYVIEW(dev_priv)) 3479 pipe_config->cgm_mode = intel_de_read(dev_priv, 3480 CGM_PIPE_MODE(crtc->pipe)); 3481 3482 i9xx_get_pipe_color_config(pipe_config); 3483 intel_color_get_config(pipe_config); 3484 3485 if (DISPLAY_VER(dev_priv) < 4) 3486 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; 3487 3488 intel_get_transcoder_timings(crtc, pipe_config); 3489 intel_get_pipe_src_size(crtc, pipe_config); 3490 3491 i9xx_get_pfit_config(pipe_config); 3492 3493 if (DISPLAY_VER(dev_priv) >= 4) { 3494 /* No way to read it out on pipes B and C */ 3495 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) 3496 tmp = dev_priv->chv_dpll_md[crtc->pipe]; 3497 else 3498 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe)); 3499 pipe_config->pixel_multiplier = 3500 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) 3501 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; 3502 pipe_config->dpll_hw_state.dpll_md = tmp; 3503 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 3504 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 3505 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe)); 3506 pipe_config->pixel_multiplier = 3507 ((tmp & SDVO_MULTIPLIER_MASK) 3508 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; 3509 } else { 3510 /* Note that on i915G/GM the pixel multiplier is in the sdvo 3511 * port and will be fixed up in the encoder->get_config 3512 * function. */ 3513 pipe_config->pixel_multiplier = 1; 3514 } 3515 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv, 3516 DPLL(crtc->pipe)); 3517 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 3518 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv, 3519 FP0(crtc->pipe)); 3520 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv, 3521 FP1(crtc->pipe)); 3522 } else { 3523 /* Mask out read-only status bits. */ 3524 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | 3525 DPLL_PORTC_READY_MASK | 3526 DPLL_PORTB_READY_MASK); 3527 } 3528 3529 if (IS_CHERRYVIEW(dev_priv)) 3530 chv_crtc_clock_get(crtc, pipe_config); 3531 else if (IS_VALLEYVIEW(dev_priv)) 3532 vlv_crtc_clock_get(crtc, pipe_config); 3533 else 3534 i9xx_crtc_clock_get(crtc, pipe_config); 3535 3536 /* 3537 * Normally the dotclock is filled in by the encoder .get_config() 3538 * but in case the pipe is enabled w/o any ports we need a sane 3539 * default. 3540 */ 3541 pipe_config->hw.adjusted_mode.crtc_clock = 3542 pipe_config->port_clock / pipe_config->pixel_multiplier; 3543 3544 ret = true; 3545 3546 out: 3547 intel_display_power_put(dev_priv, power_domain, wakeref); 3548 3549 return ret; 3550 } 3551 3552 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) 3553 { 3554 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3555 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3556 enum pipe pipe = crtc->pipe; 3557 u32 val; 3558 3559 val = 0; 3560 3561 switch (crtc_state->pipe_bpp) { 3562 case 18: 3563 val |= PIPECONF_BPC_6; 3564 break; 3565 case 24: 3566 val |= PIPECONF_BPC_8; 3567 break; 3568 case 30: 3569 val |= PIPECONF_BPC_10; 3570 break; 3571 case 36: 3572 val |= PIPECONF_BPC_12; 3573 break; 3574 default: 3575 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3576 BUG(); 3577 } 3578 3579 if (crtc_state->dither) 3580 val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP; 3581 3582 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3583 val |= PIPECONF_INTERLACE_IF_ID_ILK; 3584 else 3585 val |= PIPECONF_INTERLACE_PF_PD_ILK; 3586 3587 /* 3588 * This would end up with an odd purple hue over 3589 * the entire display. Make sure we don't do it. 3590 */ 3591 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 3592 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 3593 3594 if (crtc_state->limited_color_range && 3595 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3596 val |= PIPECONF_COLOR_RANGE_SELECT; 3597 3598 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3599 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709; 3600 3601 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); 3602 3603 val |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3604 val |= PIPECONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay); 3605 3606 intel_de_write(dev_priv, PIPECONF(pipe), val); 3607 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 3608 } 3609 3610 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) 3611 { 3612 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3613 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3614 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3615 u32 val = 0; 3616 3617 if (IS_HASWELL(dev_priv) && crtc_state->dither) 3618 val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP; 3619 3620 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3621 val |= PIPECONF_INTERLACE_IF_ID_ILK; 3622 else 3623 val |= PIPECONF_INTERLACE_PF_PD_ILK; 3624 3625 if (IS_HASWELL(dev_priv) && 3626 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3627 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW; 3628 3629 intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val); 3630 intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder)); 3631 } 3632 3633 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) 3634 { 3635 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3636 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3637 u32 val = 0; 3638 3639 switch (crtc_state->pipe_bpp) { 3640 case 18: 3641 val |= PIPEMISC_BPC_6; 3642 break; 3643 case 24: 3644 val |= PIPEMISC_BPC_8; 3645 break; 3646 case 30: 3647 val |= PIPEMISC_BPC_10; 3648 break; 3649 case 36: 3650 /* Port output 12BPC defined for ADLP+ */ 3651 if (DISPLAY_VER(dev_priv) > 12) 3652 val |= PIPEMISC_BPC_12_ADLP; 3653 break; 3654 default: 3655 MISSING_CASE(crtc_state->pipe_bpp); 3656 break; 3657 } 3658 3659 if (crtc_state->dither) 3660 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; 3661 3662 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 3663 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 3664 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV; 3665 3666 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 3667 val |= PIPEMISC_YUV420_ENABLE | 3668 PIPEMISC_YUV420_MODE_FULL_BLEND; 3669 3670 if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state)) 3671 val |= PIPEMISC_HDR_MODE_PRECISION; 3672 3673 if (DISPLAY_VER(dev_priv) >= 12) 3674 val |= PIPEMISC_PIXEL_ROUNDING_TRUNC; 3675 3676 intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val); 3677 } 3678 3679 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) 3680 { 3681 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3682 u32 tmp; 3683 3684 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); 3685 3686 switch (tmp & PIPEMISC_BPC_MASK) { 3687 case PIPEMISC_BPC_6: 3688 return 18; 3689 case PIPEMISC_BPC_8: 3690 return 24; 3691 case PIPEMISC_BPC_10: 3692 return 30; 3693 /* 3694 * PORT OUTPUT 12 BPC defined for ADLP+. 3695 * 3696 * TODO: 3697 * For previous platforms with DSI interface, bits 5:7 3698 * are used for storing pipe_bpp irrespective of dithering. 3699 * Since the value of 12 BPC is not defined for these bits 3700 * on older platforms, need to find a workaround for 12 BPC 3701 * MIPI DSI HW readout. 3702 */ 3703 case PIPEMISC_BPC_12_ADLP: 3704 if (DISPLAY_VER(dev_priv) > 12) 3705 return 36; 3706 fallthrough; 3707 default: 3708 MISSING_CASE(tmp); 3709 return 0; 3710 } 3711 } 3712 3713 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) 3714 { 3715 /* 3716 * Account for spread spectrum to avoid 3717 * oversubscribing the link. Max center spread 3718 * is 2.5%; use 5% for safety's sake. 3719 */ 3720 u32 bps = target_clock * bpp * 21 / 20; 3721 return DIV_ROUND_UP(bps, link_bw * 8); 3722 } 3723 3724 void intel_get_m_n(struct drm_i915_private *i915, 3725 struct intel_link_m_n *m_n, 3726 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 3727 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 3728 { 3729 m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK; 3730 m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK; 3731 m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK; 3732 m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK; 3733 m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1; 3734 } 3735 3736 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, 3737 enum transcoder transcoder, 3738 struct intel_link_m_n *m_n) 3739 { 3740 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3741 enum pipe pipe = crtc->pipe; 3742 3743 if (DISPLAY_VER(dev_priv) >= 5) 3744 intel_get_m_n(dev_priv, m_n, 3745 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 3746 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 3747 else 3748 intel_get_m_n(dev_priv, m_n, 3749 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 3750 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 3751 } 3752 3753 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, 3754 enum transcoder transcoder, 3755 struct intel_link_m_n *m_n) 3756 { 3757 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3758 3759 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 3760 return; 3761 3762 intel_get_m_n(dev_priv, m_n, 3763 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 3764 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 3765 } 3766 3767 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state, 3768 u32 pos, u32 size) 3769 { 3770 drm_rect_init(&crtc_state->pch_pfit.dst, 3771 pos >> 16, pos & 0xffff, 3772 size >> 16, size & 0xffff); 3773 } 3774 3775 static void skl_get_pfit_config(struct intel_crtc_state *crtc_state) 3776 { 3777 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3778 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3779 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; 3780 int id = -1; 3781 int i; 3782 3783 /* find scaler attached to this pipe */ 3784 for (i = 0; i < crtc->num_scalers; i++) { 3785 u32 ctl, pos, size; 3786 3787 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i)); 3788 if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN) 3789 continue; 3790 3791 id = i; 3792 crtc_state->pch_pfit.enabled = true; 3793 3794 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i)); 3795 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i)); 3796 3797 ilk_get_pfit_pos_size(crtc_state, pos, size); 3798 3799 scaler_state->scalers[i].in_use = true; 3800 break; 3801 } 3802 3803 scaler_state->scaler_id = id; 3804 if (id >= 0) 3805 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); 3806 else 3807 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); 3808 } 3809 3810 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state) 3811 { 3812 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3813 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3814 u32 ctl, pos, size; 3815 3816 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe)); 3817 if ((ctl & PF_ENABLE) == 0) 3818 return; 3819 3820 crtc_state->pch_pfit.enabled = true; 3821 3822 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe)); 3823 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe)); 3824 3825 ilk_get_pfit_pos_size(crtc_state, pos, size); 3826 3827 /* 3828 * We currently do not free assignements of panel fitters on 3829 * ivb/hsw (since we don't use the higher upscaling modes which 3830 * differentiates them) so just WARN about this case for now. 3831 */ 3832 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 7 && 3833 (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe)); 3834 } 3835 3836 static bool ilk_get_pipe_config(struct intel_crtc *crtc, 3837 struct intel_crtc_state *pipe_config) 3838 { 3839 struct drm_device *dev = crtc->base.dev; 3840 struct drm_i915_private *dev_priv = to_i915(dev); 3841 enum intel_display_power_domain power_domain; 3842 intel_wakeref_t wakeref; 3843 u32 tmp; 3844 bool ret; 3845 3846 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3847 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3848 if (!wakeref) 3849 return false; 3850 3851 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3852 pipe_config->shared_dpll = NULL; 3853 3854 ret = false; 3855 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); 3856 if (!(tmp & PIPECONF_ENABLE)) 3857 goto out; 3858 3859 switch (tmp & PIPECONF_BPC_MASK) { 3860 case PIPECONF_BPC_6: 3861 pipe_config->pipe_bpp = 18; 3862 break; 3863 case PIPECONF_BPC_8: 3864 pipe_config->pipe_bpp = 24; 3865 break; 3866 case PIPECONF_BPC_10: 3867 pipe_config->pipe_bpp = 30; 3868 break; 3869 case PIPECONF_BPC_12: 3870 pipe_config->pipe_bpp = 36; 3871 break; 3872 default: 3873 break; 3874 } 3875 3876 if (tmp & PIPECONF_COLOR_RANGE_SELECT) 3877 pipe_config->limited_color_range = true; 3878 3879 switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) { 3880 case PIPECONF_OUTPUT_COLORSPACE_YUV601: 3881 case PIPECONF_OUTPUT_COLORSPACE_YUV709: 3882 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3883 break; 3884 default: 3885 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3886 break; 3887 } 3888 3889 pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_ILK, tmp); 3890 3891 pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1; 3892 3893 pipe_config->msa_timing_delay = REG_FIELD_GET(PIPECONF_MSA_TIMING_DELAY_MASK, tmp); 3894 3895 pipe_config->csc_mode = intel_de_read(dev_priv, 3896 PIPE_CSC_MODE(crtc->pipe)); 3897 3898 i9xx_get_pipe_color_config(pipe_config); 3899 intel_color_get_config(pipe_config); 3900 3901 pipe_config->pixel_multiplier = 1; 3902 3903 ilk_pch_get_config(pipe_config); 3904 3905 intel_get_transcoder_timings(crtc, pipe_config); 3906 intel_get_pipe_src_size(crtc, pipe_config); 3907 3908 ilk_get_pfit_config(pipe_config); 3909 3910 ret = true; 3911 3912 out: 3913 intel_display_power_put(dev_priv, power_domain, wakeref); 3914 3915 return ret; 3916 } 3917 3918 static u8 bigjoiner_pipes(struct drm_i915_private *i915) 3919 { 3920 if (DISPLAY_VER(i915) >= 12) 3921 return BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D); 3922 else if (DISPLAY_VER(i915) >= 11) 3923 return BIT(PIPE_B) | BIT(PIPE_C); 3924 else 3925 return 0; 3926 } 3927 3928 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv, 3929 enum transcoder cpu_transcoder) 3930 { 3931 enum intel_display_power_domain power_domain; 3932 intel_wakeref_t wakeref; 3933 u32 tmp = 0; 3934 3935 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3936 3937 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3938 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3939 3940 return tmp & TRANS_DDI_FUNC_ENABLE; 3941 } 3942 3943 static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv, 3944 u8 *master_pipes, u8 *slave_pipes) 3945 { 3946 struct intel_crtc *crtc; 3947 3948 *master_pipes = 0; 3949 *slave_pipes = 0; 3950 3951 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, 3952 bigjoiner_pipes(dev_priv)) { 3953 enum intel_display_power_domain power_domain; 3954 enum pipe pipe = crtc->pipe; 3955 intel_wakeref_t wakeref; 3956 3957 power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe); 3958 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3959 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3960 3961 if (!(tmp & BIG_JOINER_ENABLE)) 3962 continue; 3963 3964 if (tmp & MASTER_BIG_JOINER_ENABLE) 3965 *master_pipes |= BIT(pipe); 3966 else 3967 *slave_pipes |= BIT(pipe); 3968 } 3969 3970 if (DISPLAY_VER(dev_priv) < 13) 3971 continue; 3972 3973 power_domain = POWER_DOMAIN_PIPE(pipe); 3974 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3975 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3976 3977 if (tmp & UNCOMPRESSED_JOINER_MASTER) 3978 *master_pipes |= BIT(pipe); 3979 if (tmp & UNCOMPRESSED_JOINER_SLAVE) 3980 *slave_pipes |= BIT(pipe); 3981 } 3982 } 3983 3984 /* Bigjoiner pipes should always be consecutive master and slave */ 3985 drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1, 3986 "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n", 3987 *master_pipes, *slave_pipes); 3988 } 3989 3990 static enum pipe get_bigjoiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3991 { 3992 if ((slave_pipes & BIT(pipe)) == 0) 3993 return pipe; 3994 3995 /* ignore everything above our pipe */ 3996 master_pipes &= ~GENMASK(7, pipe); 3997 3998 /* highest remaining bit should be our master pipe */ 3999 return fls(master_pipes) - 1; 4000 } 4001 4002 static u8 get_bigjoiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 4003 { 4004 enum pipe master_pipe, next_master_pipe; 4005 4006 master_pipe = get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes); 4007 4008 if ((master_pipes & BIT(master_pipe)) == 0) 4009 return 0; 4010 4011 /* ignore our master pipe and everything below it */ 4012 master_pipes &= ~GENMASK(master_pipe, 0); 4013 /* make sure a high bit is set for the ffs() */ 4014 master_pipes |= BIT(7); 4015 /* lowest remaining bit should be the next master pipe */ 4016 next_master_pipe = ffs(master_pipes) - 1; 4017 4018 return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe); 4019 } 4020 4021 static u8 hsw_panel_transcoders(struct drm_i915_private *i915) 4022 { 4023 u8 panel_transcoder_mask = BIT(TRANSCODER_EDP); 4024 4025 if (DISPLAY_VER(i915) >= 11) 4026 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); 4027 4028 return panel_transcoder_mask; 4029 } 4030 4031 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) 4032 { 4033 struct drm_device *dev = crtc->base.dev; 4034 struct drm_i915_private *dev_priv = to_i915(dev); 4035 u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv); 4036 enum transcoder cpu_transcoder; 4037 u8 master_pipes, slave_pipes; 4038 u8 enabled_transcoders = 0; 4039 4040 /* 4041 * XXX: Do intel_display_power_get_if_enabled before reading this (for 4042 * consistency and less surprising code; it's in always on power). 4043 */ 4044 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, 4045 panel_transcoder_mask) { 4046 enum intel_display_power_domain power_domain; 4047 intel_wakeref_t wakeref; 4048 enum pipe trans_pipe; 4049 u32 tmp = 0; 4050 4051 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 4052 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 4053 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 4054 4055 if (!(tmp & TRANS_DDI_FUNC_ENABLE)) 4056 continue; 4057 4058 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 4059 default: 4060 drm_WARN(dev, 1, 4061 "unknown pipe linked to transcoder %s\n", 4062 transcoder_name(cpu_transcoder)); 4063 fallthrough; 4064 case TRANS_DDI_EDP_INPUT_A_ONOFF: 4065 case TRANS_DDI_EDP_INPUT_A_ON: 4066 trans_pipe = PIPE_A; 4067 break; 4068 case TRANS_DDI_EDP_INPUT_B_ONOFF: 4069 trans_pipe = PIPE_B; 4070 break; 4071 case TRANS_DDI_EDP_INPUT_C_ONOFF: 4072 trans_pipe = PIPE_C; 4073 break; 4074 case TRANS_DDI_EDP_INPUT_D_ONOFF: 4075 trans_pipe = PIPE_D; 4076 break; 4077 } 4078 4079 if (trans_pipe == crtc->pipe) 4080 enabled_transcoders |= BIT(cpu_transcoder); 4081 } 4082 4083 /* single pipe or bigjoiner master */ 4084 cpu_transcoder = (enum transcoder) crtc->pipe; 4085 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 4086 enabled_transcoders |= BIT(cpu_transcoder); 4087 4088 /* bigjoiner slave -> consider the master pipe's transcoder as well */ 4089 enabled_bigjoiner_pipes(dev_priv, &master_pipes, &slave_pipes); 4090 if (slave_pipes & BIT(crtc->pipe)) { 4091 cpu_transcoder = (enum transcoder) 4092 get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes); 4093 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 4094 enabled_transcoders |= BIT(cpu_transcoder); 4095 } 4096 4097 return enabled_transcoders; 4098 } 4099 4100 static bool has_edp_transcoders(u8 enabled_transcoders) 4101 { 4102 return enabled_transcoders & BIT(TRANSCODER_EDP); 4103 } 4104 4105 static bool has_dsi_transcoders(u8 enabled_transcoders) 4106 { 4107 return enabled_transcoders & (BIT(TRANSCODER_DSI_0) | 4108 BIT(TRANSCODER_DSI_1)); 4109 } 4110 4111 static bool has_pipe_transcoders(u8 enabled_transcoders) 4112 { 4113 return enabled_transcoders & ~(BIT(TRANSCODER_EDP) | 4114 BIT(TRANSCODER_DSI_0) | 4115 BIT(TRANSCODER_DSI_1)); 4116 } 4117 4118 static void assert_enabled_transcoders(struct drm_i915_private *i915, 4119 u8 enabled_transcoders) 4120 { 4121 /* Only one type of transcoder please */ 4122 drm_WARN_ON(&i915->drm, 4123 has_edp_transcoders(enabled_transcoders) + 4124 has_dsi_transcoders(enabled_transcoders) + 4125 has_pipe_transcoders(enabled_transcoders) > 1); 4126 4127 /* Only DSI transcoders can be ganged */ 4128 drm_WARN_ON(&i915->drm, 4129 !has_dsi_transcoders(enabled_transcoders) && 4130 !is_power_of_2(enabled_transcoders)); 4131 } 4132 4133 static bool hsw_get_transcoder_state(struct intel_crtc *crtc, 4134 struct intel_crtc_state *pipe_config, 4135 struct intel_display_power_domain_set *power_domain_set) 4136 { 4137 struct drm_device *dev = crtc->base.dev; 4138 struct drm_i915_private *dev_priv = to_i915(dev); 4139 unsigned long enabled_transcoders; 4140 u32 tmp; 4141 4142 enabled_transcoders = hsw_enabled_transcoders(crtc); 4143 if (!enabled_transcoders) 4144 return false; 4145 4146 assert_enabled_transcoders(dev_priv, enabled_transcoders); 4147 4148 /* 4149 * With the exception of DSI we should only ever have 4150 * a single enabled transcoder. With DSI let's just 4151 * pick the first one. 4152 */ 4153 pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1; 4154 4155 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 4156 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) 4157 return false; 4158 4159 if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) { 4160 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); 4161 4162 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF) 4163 pipe_config->pch_pfit.force_thru = true; 4164 } 4165 4166 tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder)); 4167 4168 return tmp & PIPECONF_ENABLE; 4169 } 4170 4171 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, 4172 struct intel_crtc_state *pipe_config, 4173 struct intel_display_power_domain_set *power_domain_set) 4174 { 4175 struct drm_device *dev = crtc->base.dev; 4176 struct drm_i915_private *dev_priv = to_i915(dev); 4177 enum transcoder cpu_transcoder; 4178 enum port port; 4179 u32 tmp; 4180 4181 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { 4182 if (port == PORT_A) 4183 cpu_transcoder = TRANSCODER_DSI_A; 4184 else 4185 cpu_transcoder = TRANSCODER_DSI_C; 4186 4187 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 4188 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) 4189 continue; 4190 4191 /* 4192 * The PLL needs to be enabled with a valid divider 4193 * configuration, otherwise accessing DSI registers will hang 4194 * the machine. See BSpec North Display Engine 4195 * registers/MIPI[BXT]. We can break out here early, since we 4196 * need the same DSI PLL to be enabled for both DSI ports. 4197 */ 4198 if (!bxt_dsi_pll_is_enabled(dev_priv)) 4199 break; 4200 4201 /* XXX: this works for video mode only */ 4202 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); 4203 if (!(tmp & DPI_ENABLE)) 4204 continue; 4205 4206 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 4207 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) 4208 continue; 4209 4210 pipe_config->cpu_transcoder = cpu_transcoder; 4211 break; 4212 } 4213 4214 return transcoder_is_dsi(pipe_config->cpu_transcoder); 4215 } 4216 4217 static void intel_bigjoiner_get_config(struct intel_crtc_state *crtc_state) 4218 { 4219 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4220 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4221 u8 master_pipes, slave_pipes; 4222 enum pipe pipe = crtc->pipe; 4223 4224 enabled_bigjoiner_pipes(i915, &master_pipes, &slave_pipes); 4225 4226 if (((master_pipes | slave_pipes) & BIT(pipe)) == 0) 4227 return; 4228 4229 crtc_state->bigjoiner_pipes = 4230 BIT(get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes)) | 4231 get_bigjoiner_slave_pipes(pipe, master_pipes, slave_pipes); 4232 } 4233 4234 static bool hsw_get_pipe_config(struct intel_crtc *crtc, 4235 struct intel_crtc_state *pipe_config) 4236 { 4237 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4238 struct intel_display_power_domain_set power_domain_set = { }; 4239 bool active; 4240 u32 tmp; 4241 4242 if (!intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set, 4243 POWER_DOMAIN_PIPE(crtc->pipe))) 4244 return false; 4245 4246 pipe_config->shared_dpll = NULL; 4247 4248 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_set); 4249 4250 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 4251 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_set)) { 4252 drm_WARN_ON(&dev_priv->drm, active); 4253 active = true; 4254 } 4255 4256 if (!active) 4257 goto out; 4258 4259 intel_dsc_get_config(pipe_config); 4260 intel_bigjoiner_get_config(pipe_config); 4261 4262 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || 4263 DISPLAY_VER(dev_priv) >= 11) 4264 intel_get_transcoder_timings(crtc, pipe_config); 4265 4266 if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder)) 4267 intel_vrr_get_config(crtc, pipe_config); 4268 4269 intel_get_pipe_src_size(crtc, pipe_config); 4270 4271 if (IS_HASWELL(dev_priv)) { 4272 u32 tmp = intel_de_read(dev_priv, 4273 PIPECONF(pipe_config->cpu_transcoder)); 4274 4275 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW) 4276 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 4277 else 4278 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 4279 } else { 4280 pipe_config->output_format = 4281 bdw_get_pipemisc_output_format(crtc); 4282 } 4283 4284 pipe_config->gamma_mode = intel_de_read(dev_priv, 4285 GAMMA_MODE(crtc->pipe)); 4286 4287 pipe_config->csc_mode = intel_de_read(dev_priv, 4288 PIPE_CSC_MODE(crtc->pipe)); 4289 4290 if (DISPLAY_VER(dev_priv) >= 9) { 4291 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe)); 4292 4293 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE) 4294 pipe_config->gamma_enable = true; 4295 4296 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE) 4297 pipe_config->csc_enable = true; 4298 } else { 4299 i9xx_get_pipe_color_config(pipe_config); 4300 } 4301 4302 intel_color_get_config(pipe_config); 4303 4304 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe)); 4305 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); 4306 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 4307 pipe_config->ips_linetime = 4308 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); 4309 4310 if (intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set, 4311 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) { 4312 if (DISPLAY_VER(dev_priv) >= 9) 4313 skl_get_pfit_config(pipe_config); 4314 else 4315 ilk_get_pfit_config(pipe_config); 4316 } 4317 4318 hsw_ips_get_config(pipe_config); 4319 4320 if (pipe_config->cpu_transcoder != TRANSCODER_EDP && 4321 !transcoder_is_dsi(pipe_config->cpu_transcoder)) { 4322 pipe_config->pixel_multiplier = 4323 intel_de_read(dev_priv, 4324 PIPE_MULT(pipe_config->cpu_transcoder)) + 1; 4325 } else { 4326 pipe_config->pixel_multiplier = 1; 4327 } 4328 4329 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { 4330 tmp = intel_de_read(dev_priv, CHICKEN_TRANS(pipe_config->cpu_transcoder)); 4331 4332 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1; 4333 } else { 4334 /* no idea if this is correct */ 4335 pipe_config->framestart_delay = 1; 4336 } 4337 4338 out: 4339 intel_display_power_put_all_in_set(dev_priv, &power_domain_set); 4340 4341 return active; 4342 } 4343 4344 static bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state) 4345 { 4346 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4347 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4348 4349 if (!i915->display->get_pipe_config(crtc, crtc_state)) 4350 return false; 4351 4352 crtc_state->hw.active = true; 4353 4354 intel_crtc_readout_derived_state(crtc_state); 4355 4356 return true; 4357 } 4358 4359 /* VESA 640x480x72Hz mode to set on the pipe */ 4360 static const struct drm_display_mode load_detect_mode = { 4361 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, 4362 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 4363 }; 4364 4365 static int intel_modeset_disable_planes(struct drm_atomic_state *state, 4366 struct drm_crtc *crtc) 4367 { 4368 struct drm_plane *plane; 4369 struct drm_plane_state *plane_state; 4370 int ret, i; 4371 4372 ret = drm_atomic_add_affected_planes(state, crtc); 4373 if (ret) 4374 return ret; 4375 4376 for_each_new_plane_in_state(state, plane, plane_state, i) { 4377 if (plane_state->crtc != crtc) 4378 continue; 4379 4380 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL); 4381 if (ret) 4382 return ret; 4383 4384 drm_atomic_set_fb_for_plane(plane_state, NULL); 4385 } 4386 4387 return 0; 4388 } 4389 4390 int intel_get_load_detect_pipe(struct drm_connector *connector, 4391 struct intel_load_detect_pipe *old, 4392 struct drm_modeset_acquire_ctx *ctx) 4393 { 4394 struct intel_encoder *encoder = 4395 intel_attached_encoder(to_intel_connector(connector)); 4396 struct intel_crtc *possible_crtc; 4397 struct intel_crtc *crtc = NULL; 4398 struct drm_device *dev = encoder->base.dev; 4399 struct drm_i915_private *dev_priv = to_i915(dev); 4400 struct drm_mode_config *config = &dev->mode_config; 4401 struct drm_atomic_state *state = NULL, *restore_state = NULL; 4402 struct drm_connector_state *connector_state; 4403 struct intel_crtc_state *crtc_state; 4404 int ret; 4405 4406 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 4407 connector->base.id, connector->name, 4408 encoder->base.base.id, encoder->base.name); 4409 4410 old->restore_state = NULL; 4411 4412 drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex)); 4413 4414 /* 4415 * Algorithm gets a little messy: 4416 * 4417 * - if the connector already has an assigned crtc, use it (but make 4418 * sure it's on first) 4419 * 4420 * - try to find the first unused crtc that can drive this connector, 4421 * and use that if we find one 4422 */ 4423 4424 /* See if we already have a CRTC for this connector */ 4425 if (connector->state->crtc) { 4426 crtc = to_intel_crtc(connector->state->crtc); 4427 4428 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4429 if (ret) 4430 goto fail; 4431 4432 /* Make sure the crtc and connector are running */ 4433 goto found; 4434 } 4435 4436 /* Find an unused one (if possible) */ 4437 for_each_intel_crtc(dev, possible_crtc) { 4438 if (!(encoder->base.possible_crtcs & 4439 drm_crtc_mask(&possible_crtc->base))) 4440 continue; 4441 4442 ret = drm_modeset_lock(&possible_crtc->base.mutex, ctx); 4443 if (ret) 4444 goto fail; 4445 4446 if (possible_crtc->base.state->enable) { 4447 drm_modeset_unlock(&possible_crtc->base.mutex); 4448 continue; 4449 } 4450 4451 crtc = possible_crtc; 4452 break; 4453 } 4454 4455 /* 4456 * If we didn't find an unused CRTC, don't use any. 4457 */ 4458 if (!crtc) { 4459 drm_dbg_kms(&dev_priv->drm, 4460 "no pipe available for load-detect\n"); 4461 ret = -ENODEV; 4462 goto fail; 4463 } 4464 4465 found: 4466 state = drm_atomic_state_alloc(dev); 4467 restore_state = drm_atomic_state_alloc(dev); 4468 if (!state || !restore_state) { 4469 ret = -ENOMEM; 4470 goto fail; 4471 } 4472 4473 state->acquire_ctx = ctx; 4474 restore_state->acquire_ctx = ctx; 4475 4476 connector_state = drm_atomic_get_connector_state(state, connector); 4477 if (IS_ERR(connector_state)) { 4478 ret = PTR_ERR(connector_state); 4479 goto fail; 4480 } 4481 4482 ret = drm_atomic_set_crtc_for_connector(connector_state, &crtc->base); 4483 if (ret) 4484 goto fail; 4485 4486 crtc_state = intel_atomic_get_crtc_state(state, crtc); 4487 if (IS_ERR(crtc_state)) { 4488 ret = PTR_ERR(crtc_state); 4489 goto fail; 4490 } 4491 4492 crtc_state->uapi.active = true; 4493 4494 ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi, 4495 &load_detect_mode); 4496 if (ret) 4497 goto fail; 4498 4499 ret = intel_modeset_disable_planes(state, &crtc->base); 4500 if (ret) 4501 goto fail; 4502 4503 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); 4504 if (!ret) 4505 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, &crtc->base)); 4506 if (!ret) 4507 ret = drm_atomic_add_affected_planes(restore_state, &crtc->base); 4508 if (ret) { 4509 drm_dbg_kms(&dev_priv->drm, 4510 "Failed to create a copy of old state to restore: %i\n", 4511 ret); 4512 goto fail; 4513 } 4514 4515 ret = drm_atomic_commit(state); 4516 if (ret) { 4517 drm_dbg_kms(&dev_priv->drm, 4518 "failed to set mode on load-detect pipe\n"); 4519 goto fail; 4520 } 4521 4522 old->restore_state = restore_state; 4523 drm_atomic_state_put(state); 4524 4525 /* let the connector get through one full cycle before testing */ 4526 intel_crtc_wait_for_next_vblank(crtc); 4527 4528 return true; 4529 4530 fail: 4531 if (state) { 4532 drm_atomic_state_put(state); 4533 state = NULL; 4534 } 4535 if (restore_state) { 4536 drm_atomic_state_put(restore_state); 4537 restore_state = NULL; 4538 } 4539 4540 if (ret == -EDEADLK) 4541 return ret; 4542 4543 return false; 4544 } 4545 4546 void intel_release_load_detect_pipe(struct drm_connector *connector, 4547 struct intel_load_detect_pipe *old, 4548 struct drm_modeset_acquire_ctx *ctx) 4549 { 4550 struct intel_encoder *intel_encoder = 4551 intel_attached_encoder(to_intel_connector(connector)); 4552 struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev); 4553 struct drm_encoder *encoder = &intel_encoder->base; 4554 struct drm_atomic_state *state = old->restore_state; 4555 int ret; 4556 4557 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 4558 connector->base.id, connector->name, 4559 encoder->base.id, encoder->name); 4560 4561 if (!state) 4562 return; 4563 4564 ret = drm_atomic_helper_commit_duplicated_state(state, ctx); 4565 if (ret) 4566 drm_dbg_kms(&i915->drm, 4567 "Couldn't release load detect pipe: %i\n", ret); 4568 drm_atomic_state_put(state); 4569 } 4570 4571 static int i9xx_pll_refclk(struct drm_device *dev, 4572 const struct intel_crtc_state *pipe_config) 4573 { 4574 struct drm_i915_private *dev_priv = to_i915(dev); 4575 u32 dpll = pipe_config->dpll_hw_state.dpll; 4576 4577 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) 4578 return dev_priv->vbt.lvds_ssc_freq; 4579 else if (HAS_PCH_SPLIT(dev_priv)) 4580 return 120000; 4581 else if (DISPLAY_VER(dev_priv) != 2) 4582 return 96000; 4583 else 4584 return 48000; 4585 } 4586 4587 /* Returns the clock of the currently programmed mode of the given pipe. */ 4588 void i9xx_crtc_clock_get(struct intel_crtc *crtc, 4589 struct intel_crtc_state *pipe_config) 4590 { 4591 struct drm_device *dev = crtc->base.dev; 4592 struct drm_i915_private *dev_priv = to_i915(dev); 4593 u32 dpll = pipe_config->dpll_hw_state.dpll; 4594 u32 fp; 4595 struct dpll clock; 4596 int port_clock; 4597 int refclk = i9xx_pll_refclk(dev, pipe_config); 4598 4599 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 4600 fp = pipe_config->dpll_hw_state.fp0; 4601 else 4602 fp = pipe_config->dpll_hw_state.fp1; 4603 4604 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 4605 if (IS_PINEVIEW(dev_priv)) { 4606 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; 4607 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; 4608 } else { 4609 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 4610 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 4611 } 4612 4613 if (DISPLAY_VER(dev_priv) != 2) { 4614 if (IS_PINEVIEW(dev_priv)) 4615 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> 4616 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); 4617 else 4618 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> 4619 DPLL_FPA01_P1_POST_DIV_SHIFT); 4620 4621 switch (dpll & DPLL_MODE_MASK) { 4622 case DPLLB_MODE_DAC_SERIAL: 4623 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 4624 5 : 10; 4625 break; 4626 case DPLLB_MODE_LVDS: 4627 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 4628 7 : 14; 4629 break; 4630 default: 4631 drm_dbg_kms(&dev_priv->drm, 4632 "Unknown DPLL mode %08x in programmed " 4633 "mode\n", (int)(dpll & DPLL_MODE_MASK)); 4634 return; 4635 } 4636 4637 if (IS_PINEVIEW(dev_priv)) 4638 port_clock = pnv_calc_dpll_params(refclk, &clock); 4639 else 4640 port_clock = i9xx_calc_dpll_params(refclk, &clock); 4641 } else { 4642 enum pipe lvds_pipe; 4643 4644 if (IS_I85X(dev_priv) && 4645 intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) && 4646 lvds_pipe == crtc->pipe) { 4647 u32 lvds = intel_de_read(dev_priv, LVDS); 4648 4649 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 4650 DPLL_FPA01_P1_POST_DIV_SHIFT); 4651 4652 if (lvds & LVDS_CLKB_POWER_UP) 4653 clock.p2 = 7; 4654 else 4655 clock.p2 = 14; 4656 } else { 4657 if (dpll & PLL_P1_DIVIDE_BY_TWO) 4658 clock.p1 = 2; 4659 else { 4660 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 4661 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 4662 } 4663 if (dpll & PLL_P2_DIVIDE_BY_4) 4664 clock.p2 = 4; 4665 else 4666 clock.p2 = 2; 4667 } 4668 4669 port_clock = i9xx_calc_dpll_params(refclk, &clock); 4670 } 4671 4672 /* 4673 * This value includes pixel_multiplier. We will use 4674 * port_clock to compute adjusted_mode.crtc_clock in the 4675 * encoder's get_config() function. 4676 */ 4677 pipe_config->port_clock = port_clock; 4678 } 4679 4680 int intel_dotclock_calculate(int link_freq, 4681 const struct intel_link_m_n *m_n) 4682 { 4683 /* 4684 * The calculation for the data clock is: 4685 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp 4686 * But we want to avoid losing precison if possible, so: 4687 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) 4688 * 4689 * and the link clock is simpler: 4690 * link_clock = (m * link_clock) / n 4691 */ 4692 4693 if (!m_n->link_n) 4694 return 0; 4695 4696 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n); 4697 } 4698 4699 /* Returns the currently programmed mode of the given encoder. */ 4700 struct drm_display_mode * 4701 intel_encoder_current_mode(struct intel_encoder *encoder) 4702 { 4703 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4704 struct intel_crtc_state *crtc_state; 4705 struct drm_display_mode *mode; 4706 struct intel_crtc *crtc; 4707 enum pipe pipe; 4708 4709 if (!encoder->get_hw_state(encoder, &pipe)) 4710 return NULL; 4711 4712 crtc = intel_crtc_for_pipe(dev_priv, pipe); 4713 4714 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 4715 if (!mode) 4716 return NULL; 4717 4718 crtc_state = intel_crtc_state_alloc(crtc); 4719 if (!crtc_state) { 4720 kfree(mode); 4721 return NULL; 4722 } 4723 4724 if (!intel_crtc_get_pipe_config(crtc_state)) { 4725 kfree(crtc_state); 4726 kfree(mode); 4727 return NULL; 4728 } 4729 4730 intel_encoder_get_config(encoder, crtc_state); 4731 4732 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode); 4733 4734 kfree(crtc_state); 4735 4736 return mode; 4737 } 4738 4739 static bool encoders_cloneable(const struct intel_encoder *a, 4740 const struct intel_encoder *b) 4741 { 4742 /* masks could be asymmetric, so check both ways */ 4743 return a == b || (a->cloneable & (1 << b->type) && 4744 b->cloneable & (1 << a->type)); 4745 } 4746 4747 static bool check_single_encoder_cloning(struct intel_atomic_state *state, 4748 struct intel_crtc *crtc, 4749 struct intel_encoder *encoder) 4750 { 4751 struct intel_encoder *source_encoder; 4752 struct drm_connector *connector; 4753 struct drm_connector_state *connector_state; 4754 int i; 4755 4756 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4757 if (connector_state->crtc != &crtc->base) 4758 continue; 4759 4760 source_encoder = 4761 to_intel_encoder(connector_state->best_encoder); 4762 if (!encoders_cloneable(encoder, source_encoder)) 4763 return false; 4764 } 4765 4766 return true; 4767 } 4768 4769 static int icl_add_linked_planes(struct intel_atomic_state *state) 4770 { 4771 struct intel_plane *plane, *linked; 4772 struct intel_plane_state *plane_state, *linked_plane_state; 4773 int i; 4774 4775 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4776 linked = plane_state->planar_linked_plane; 4777 4778 if (!linked) 4779 continue; 4780 4781 linked_plane_state = intel_atomic_get_plane_state(state, linked); 4782 if (IS_ERR(linked_plane_state)) 4783 return PTR_ERR(linked_plane_state); 4784 4785 drm_WARN_ON(state->base.dev, 4786 linked_plane_state->planar_linked_plane != plane); 4787 drm_WARN_ON(state->base.dev, 4788 linked_plane_state->planar_slave == plane_state->planar_slave); 4789 } 4790 4791 return 0; 4792 } 4793 4794 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state) 4795 { 4796 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4797 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4798 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 4799 struct intel_plane *plane, *linked; 4800 struct intel_plane_state *plane_state; 4801 int i; 4802 4803 if (DISPLAY_VER(dev_priv) < 11) 4804 return 0; 4805 4806 /* 4807 * Destroy all old plane links and make the slave plane invisible 4808 * in the crtc_state->active_planes mask. 4809 */ 4810 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4811 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane) 4812 continue; 4813 4814 plane_state->planar_linked_plane = NULL; 4815 if (plane_state->planar_slave && !plane_state->uapi.visible) { 4816 crtc_state->enabled_planes &= ~BIT(plane->id); 4817 crtc_state->active_planes &= ~BIT(plane->id); 4818 crtc_state->update_planes |= BIT(plane->id); 4819 crtc_state->data_rate[plane->id] = 0; 4820 crtc_state->rel_data_rate[plane->id] = 0; 4821 } 4822 4823 plane_state->planar_slave = false; 4824 } 4825 4826 if (!crtc_state->nv12_planes) 4827 return 0; 4828 4829 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4830 struct intel_plane_state *linked_state = NULL; 4831 4832 if (plane->pipe != crtc->pipe || 4833 !(crtc_state->nv12_planes & BIT(plane->id))) 4834 continue; 4835 4836 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) { 4837 if (!icl_is_nv12_y_plane(dev_priv, linked->id)) 4838 continue; 4839 4840 if (crtc_state->active_planes & BIT(linked->id)) 4841 continue; 4842 4843 linked_state = intel_atomic_get_plane_state(state, linked); 4844 if (IS_ERR(linked_state)) 4845 return PTR_ERR(linked_state); 4846 4847 break; 4848 } 4849 4850 if (!linked_state) { 4851 drm_dbg_kms(&dev_priv->drm, 4852 "Need %d free Y planes for planar YUV\n", 4853 hweight8(crtc_state->nv12_planes)); 4854 4855 return -EINVAL; 4856 } 4857 4858 plane_state->planar_linked_plane = linked; 4859 4860 linked_state->planar_slave = true; 4861 linked_state->planar_linked_plane = plane; 4862 crtc_state->enabled_planes |= BIT(linked->id); 4863 crtc_state->active_planes |= BIT(linked->id); 4864 crtc_state->update_planes |= BIT(linked->id); 4865 crtc_state->data_rate[linked->id] = 4866 crtc_state->data_rate_y[plane->id]; 4867 crtc_state->rel_data_rate[linked->id] = 4868 crtc_state->rel_data_rate_y[plane->id]; 4869 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n", 4870 linked->base.name, plane->base.name); 4871 4872 /* Copy parameters to slave plane */ 4873 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE; 4874 linked_state->color_ctl = plane_state->color_ctl; 4875 linked_state->view = plane_state->view; 4876 linked_state->decrypt = plane_state->decrypt; 4877 4878 intel_plane_copy_hw_state(linked_state, plane_state); 4879 linked_state->uapi.src = plane_state->uapi.src; 4880 linked_state->uapi.dst = plane_state->uapi.dst; 4881 4882 if (icl_is_hdr_plane(dev_priv, plane->id)) { 4883 if (linked->id == PLANE_SPRITE5) 4884 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL; 4885 else if (linked->id == PLANE_SPRITE4) 4886 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL; 4887 else if (linked->id == PLANE_SPRITE3) 4888 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL; 4889 else if (linked->id == PLANE_SPRITE2) 4890 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL; 4891 else 4892 MISSING_CASE(linked->id); 4893 } 4894 } 4895 4896 return 0; 4897 } 4898 4899 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state) 4900 { 4901 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 4902 struct intel_atomic_state *state = 4903 to_intel_atomic_state(new_crtc_state->uapi.state); 4904 const struct intel_crtc_state *old_crtc_state = 4905 intel_atomic_get_old_crtc_state(state, crtc); 4906 4907 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes; 4908 } 4909 4910 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) 4911 { 4912 const struct drm_display_mode *pipe_mode = 4913 &crtc_state->hw.pipe_mode; 4914 int linetime_wm; 4915 4916 if (!crtc_state->hw.enable) 4917 return 0; 4918 4919 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4920 pipe_mode->crtc_clock); 4921 4922 return min(linetime_wm, 0x1ff); 4923 } 4924 4925 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, 4926 const struct intel_cdclk_state *cdclk_state) 4927 { 4928 const struct drm_display_mode *pipe_mode = 4929 &crtc_state->hw.pipe_mode; 4930 int linetime_wm; 4931 4932 if (!crtc_state->hw.enable) 4933 return 0; 4934 4935 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4936 cdclk_state->logical.cdclk); 4937 4938 return min(linetime_wm, 0x1ff); 4939 } 4940 4941 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) 4942 { 4943 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4944 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4945 const struct drm_display_mode *pipe_mode = 4946 &crtc_state->hw.pipe_mode; 4947 int linetime_wm; 4948 4949 if (!crtc_state->hw.enable) 4950 return 0; 4951 4952 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8, 4953 crtc_state->pixel_rate); 4954 4955 /* Display WA #1135: BXT:ALL GLK:ALL */ 4956 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 4957 dev_priv->ipc_enabled) 4958 linetime_wm /= 2; 4959 4960 return min(linetime_wm, 0x1ff); 4961 } 4962 4963 static int hsw_compute_linetime_wm(struct intel_atomic_state *state, 4964 struct intel_crtc *crtc) 4965 { 4966 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4967 struct intel_crtc_state *crtc_state = 4968 intel_atomic_get_new_crtc_state(state, crtc); 4969 const struct intel_cdclk_state *cdclk_state; 4970 4971 if (DISPLAY_VER(dev_priv) >= 9) 4972 crtc_state->linetime = skl_linetime_wm(crtc_state); 4973 else 4974 crtc_state->linetime = hsw_linetime_wm(crtc_state); 4975 4976 if (!hsw_crtc_supports_ips(crtc)) 4977 return 0; 4978 4979 cdclk_state = intel_atomic_get_cdclk_state(state); 4980 if (IS_ERR(cdclk_state)) 4981 return PTR_ERR(cdclk_state); 4982 4983 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state, 4984 cdclk_state); 4985 4986 return 0; 4987 } 4988 4989 static int intel_crtc_atomic_check(struct intel_atomic_state *state, 4990 struct intel_crtc *crtc) 4991 { 4992 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4993 struct intel_crtc_state *crtc_state = 4994 intel_atomic_get_new_crtc_state(state, crtc); 4995 bool mode_changed = intel_crtc_needs_modeset(crtc_state); 4996 int ret; 4997 4998 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) && 4999 mode_changed && !crtc_state->hw.active) 5000 crtc_state->update_wm_post = true; 5001 5002 if (mode_changed && crtc_state->hw.enable && 5003 !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) { 5004 ret = intel_dpll_crtc_compute_clock(crtc_state); 5005 if (ret) 5006 return ret; 5007 } 5008 5009 /* 5010 * May need to update pipe gamma enable bits 5011 * when C8 planes are getting enabled/disabled. 5012 */ 5013 if (c8_planes_changed(crtc_state)) 5014 crtc_state->uapi.color_mgmt_changed = true; 5015 5016 if (mode_changed || crtc_state->update_pipe || 5017 crtc_state->uapi.color_mgmt_changed) { 5018 ret = intel_color_check(crtc_state); 5019 if (ret) 5020 return ret; 5021 } 5022 5023 ret = intel_compute_pipe_wm(state, crtc); 5024 if (ret) { 5025 drm_dbg_kms(&dev_priv->drm, 5026 "Target pipe watermarks are invalid\n"); 5027 return ret; 5028 } 5029 5030 /* 5031 * Calculate 'intermediate' watermarks that satisfy both the 5032 * old state and the new state. We can program these 5033 * immediately. 5034 */ 5035 ret = intel_compute_intermediate_wm(state, crtc); 5036 if (ret) { 5037 drm_dbg_kms(&dev_priv->drm, 5038 "No valid intermediate pipe watermarks are possible\n"); 5039 return ret; 5040 } 5041 5042 if (DISPLAY_VER(dev_priv) >= 9) { 5043 if (mode_changed || crtc_state->update_pipe) { 5044 ret = skl_update_scaler_crtc(crtc_state); 5045 if (ret) 5046 return ret; 5047 } 5048 5049 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state); 5050 if (ret) 5051 return ret; 5052 } 5053 5054 if (HAS_IPS(dev_priv)) { 5055 ret = hsw_ips_compute_config(state, crtc); 5056 if (ret) 5057 return ret; 5058 } 5059 5060 if (DISPLAY_VER(dev_priv) >= 9 || 5061 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 5062 ret = hsw_compute_linetime_wm(state, crtc); 5063 if (ret) 5064 return ret; 5065 5066 } 5067 5068 ret = intel_psr2_sel_fetch_update(state, crtc); 5069 if (ret) 5070 return ret; 5071 5072 return 0; 5073 } 5074 5075 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) 5076 { 5077 struct intel_connector *connector; 5078 struct drm_connector_list_iter conn_iter; 5079 5080 drm_connector_list_iter_begin(dev, &conn_iter); 5081 for_each_intel_connector_iter(connector, &conn_iter) { 5082 struct drm_connector_state *conn_state = connector->base.state; 5083 struct intel_encoder *encoder = 5084 to_intel_encoder(connector->base.encoder); 5085 5086 if (conn_state->crtc) 5087 drm_connector_put(&connector->base); 5088 5089 if (encoder) { 5090 struct intel_crtc *crtc = 5091 to_intel_crtc(encoder->base.crtc); 5092 const struct intel_crtc_state *crtc_state = 5093 to_intel_crtc_state(crtc->base.state); 5094 5095 conn_state->best_encoder = &encoder->base; 5096 conn_state->crtc = &crtc->base; 5097 conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3; 5098 5099 drm_connector_get(&connector->base); 5100 } else { 5101 conn_state->best_encoder = NULL; 5102 conn_state->crtc = NULL; 5103 } 5104 } 5105 drm_connector_list_iter_end(&conn_iter); 5106 } 5107 5108 static int 5109 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state, 5110 struct intel_crtc_state *pipe_config) 5111 { 5112 struct drm_connector *connector = conn_state->connector; 5113 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); 5114 const struct drm_display_info *info = &connector->display_info; 5115 int bpp; 5116 5117 switch (conn_state->max_bpc) { 5118 case 6 ... 7: 5119 bpp = 6 * 3; 5120 break; 5121 case 8 ... 9: 5122 bpp = 8 * 3; 5123 break; 5124 case 10 ... 11: 5125 bpp = 10 * 3; 5126 break; 5127 case 12 ... 16: 5128 bpp = 12 * 3; 5129 break; 5130 default: 5131 MISSING_CASE(conn_state->max_bpc); 5132 return -EINVAL; 5133 } 5134 5135 if (bpp < pipe_config->pipe_bpp) { 5136 drm_dbg_kms(&i915->drm, 5137 "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of " 5138 "EDID bpp %d, requested bpp %d, max platform bpp %d\n", 5139 connector->base.id, connector->name, 5140 bpp, 3 * info->bpc, 5141 3 * conn_state->max_requested_bpc, 5142 pipe_config->pipe_bpp); 5143 5144 pipe_config->pipe_bpp = bpp; 5145 } 5146 5147 return 0; 5148 } 5149 5150 static int 5151 compute_baseline_pipe_bpp(struct intel_crtc *crtc, 5152 struct intel_crtc_state *pipe_config) 5153 { 5154 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5155 struct drm_atomic_state *state = pipe_config->uapi.state; 5156 struct drm_connector *connector; 5157 struct drm_connector_state *connector_state; 5158 int bpp, i; 5159 5160 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 5161 IS_CHERRYVIEW(dev_priv))) 5162 bpp = 10*3; 5163 else if (DISPLAY_VER(dev_priv) >= 5) 5164 bpp = 12*3; 5165 else 5166 bpp = 8*3; 5167 5168 pipe_config->pipe_bpp = bpp; 5169 5170 /* Clamp display bpp to connector max bpp */ 5171 for_each_new_connector_in_state(state, connector, connector_state, i) { 5172 int ret; 5173 5174 if (connector_state->crtc != &crtc->base) 5175 continue; 5176 5177 ret = compute_sink_pipe_bpp(connector_state, pipe_config); 5178 if (ret) 5179 return ret; 5180 } 5181 5182 return 0; 5183 } 5184 5185 static void intel_dump_crtc_timings(struct drm_i915_private *i915, 5186 const struct drm_display_mode *mode) 5187 { 5188 drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, " 5189 "type: 0x%x flags: 0x%x\n", 5190 mode->crtc_clock, 5191 mode->crtc_hdisplay, mode->crtc_hsync_start, 5192 mode->crtc_hsync_end, mode->crtc_htotal, 5193 mode->crtc_vdisplay, mode->crtc_vsync_start, 5194 mode->crtc_vsync_end, mode->crtc_vtotal, 5195 mode->type, mode->flags); 5196 } 5197 5198 static void 5199 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config, 5200 const char *id, unsigned int lane_count, 5201 const struct intel_link_m_n *m_n) 5202 { 5203 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); 5204 5205 drm_dbg_kms(&i915->drm, 5206 "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n", 5207 id, lane_count, 5208 m_n->data_m, m_n->data_n, 5209 m_n->link_m, m_n->link_n, m_n->tu); 5210 } 5211 5212 static void 5213 intel_dump_infoframe(struct drm_i915_private *dev_priv, 5214 const union hdmi_infoframe *frame) 5215 { 5216 if (!drm_debug_enabled(DRM_UT_KMS)) 5217 return; 5218 5219 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame); 5220 } 5221 5222 static void 5223 intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv, 5224 const struct drm_dp_vsc_sdp *vsc) 5225 { 5226 if (!drm_debug_enabled(DRM_UT_KMS)) 5227 return; 5228 5229 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc); 5230 } 5231 5232 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x 5233 5234 static const char * const output_type_str[] = { 5235 OUTPUT_TYPE(UNUSED), 5236 OUTPUT_TYPE(ANALOG), 5237 OUTPUT_TYPE(DVO), 5238 OUTPUT_TYPE(SDVO), 5239 OUTPUT_TYPE(LVDS), 5240 OUTPUT_TYPE(TVOUT), 5241 OUTPUT_TYPE(HDMI), 5242 OUTPUT_TYPE(DP), 5243 OUTPUT_TYPE(EDP), 5244 OUTPUT_TYPE(DSI), 5245 OUTPUT_TYPE(DDI), 5246 OUTPUT_TYPE(DP_MST), 5247 }; 5248 5249 #undef OUTPUT_TYPE 5250 5251 static void snprintf_output_types(char *buf, size_t len, 5252 unsigned int output_types) 5253 { 5254 char *str = buf; 5255 int i; 5256 5257 str[0] = '\0'; 5258 5259 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) { 5260 int r; 5261 5262 if ((output_types & BIT(i)) == 0) 5263 continue; 5264 5265 r = snprintf(str, len, "%s%s", 5266 str != buf ? "," : "", output_type_str[i]); 5267 if (r >= len) 5268 break; 5269 str += r; 5270 len -= r; 5271 5272 output_types &= ~BIT(i); 5273 } 5274 5275 WARN_ON_ONCE(output_types != 0); 5276 } 5277 5278 static const char * const output_format_str[] = { 5279 [INTEL_OUTPUT_FORMAT_RGB] = "RGB", 5280 [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0", 5281 [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4", 5282 }; 5283 5284 static const char *output_formats(enum intel_output_format format) 5285 { 5286 if (format >= ARRAY_SIZE(output_format_str)) 5287 return "invalid"; 5288 return output_format_str[format]; 5289 } 5290 5291 static void intel_dump_plane_state(const struct intel_plane_state *plane_state) 5292 { 5293 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 5294 struct drm_i915_private *i915 = to_i915(plane->base.dev); 5295 const struct drm_framebuffer *fb = plane_state->hw.fb; 5296 5297 if (!fb) { 5298 drm_dbg_kms(&i915->drm, 5299 "[PLANE:%d:%s] fb: [NOFB], visible: %s\n", 5300 plane->base.base.id, plane->base.name, 5301 str_yes_no(plane_state->uapi.visible)); 5302 return; 5303 } 5304 5305 drm_dbg_kms(&i915->drm, 5306 "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %p4cc modifier = 0x%llx, visible: %s\n", 5307 plane->base.base.id, plane->base.name, 5308 fb->base.id, fb->width, fb->height, &fb->format->format, 5309 fb->modifier, str_yes_no(plane_state->uapi.visible)); 5310 drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n", 5311 plane_state->hw.rotation, plane_state->scaler_id); 5312 if (plane_state->uapi.visible) 5313 drm_dbg_kms(&i915->drm, 5314 "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n", 5315 DRM_RECT_FP_ARG(&plane_state->uapi.src), 5316 DRM_RECT_ARG(&plane_state->uapi.dst)); 5317 } 5318 5319 static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, 5320 struct intel_atomic_state *state, 5321 const char *context) 5322 { 5323 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 5324 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5325 const struct intel_plane_state *plane_state; 5326 struct intel_plane *plane; 5327 char buf[64]; 5328 int i; 5329 5330 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n", 5331 crtc->base.base.id, crtc->base.name, 5332 str_yes_no(pipe_config->hw.enable), context); 5333 5334 if (!pipe_config->hw.enable) 5335 goto dump_planes; 5336 5337 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types); 5338 drm_dbg_kms(&dev_priv->drm, 5339 "active: %s, output_types: %s (0x%x), output format: %s\n", 5340 str_yes_no(pipe_config->hw.active), 5341 buf, pipe_config->output_types, 5342 output_formats(pipe_config->output_format)); 5343 5344 drm_dbg_kms(&dev_priv->drm, 5345 "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", 5346 transcoder_name(pipe_config->cpu_transcoder), 5347 pipe_config->pipe_bpp, pipe_config->dither); 5348 5349 drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n", 5350 transcoder_name(pipe_config->mst_master_transcoder)); 5351 5352 drm_dbg_kms(&dev_priv->drm, 5353 "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n", 5354 transcoder_name(pipe_config->master_transcoder), 5355 pipe_config->sync_mode_slaves_mask); 5356 5357 drm_dbg_kms(&dev_priv->drm, "bigjoiner: %s, pipes: 0x%x\n", 5358 intel_crtc_is_bigjoiner_slave(pipe_config) ? "slave" : 5359 intel_crtc_is_bigjoiner_master(pipe_config) ? "master" : "no", 5360 pipe_config->bigjoiner_pipes); 5361 5362 drm_dbg_kms(&dev_priv->drm, "splitter: %s, link count %d, overlap %d\n", 5363 str_enabled_disabled(pipe_config->splitter.enable), 5364 pipe_config->splitter.link_count, 5365 pipe_config->splitter.pixel_overlap); 5366 5367 if (pipe_config->has_pch_encoder) 5368 intel_dump_m_n_config(pipe_config, "fdi", 5369 pipe_config->fdi_lanes, 5370 &pipe_config->fdi_m_n); 5371 5372 if (intel_crtc_has_dp_encoder(pipe_config)) { 5373 intel_dump_m_n_config(pipe_config, "dp m_n", 5374 pipe_config->lane_count, 5375 &pipe_config->dp_m_n); 5376 intel_dump_m_n_config(pipe_config, "dp m2_n2", 5377 pipe_config->lane_count, 5378 &pipe_config->dp_m2_n2); 5379 } 5380 5381 drm_dbg_kms(&dev_priv->drm, "framestart delay: %d, MSA timing delay: %d\n", 5382 pipe_config->framestart_delay, pipe_config->msa_timing_delay); 5383 5384 drm_dbg_kms(&dev_priv->drm, 5385 "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n", 5386 pipe_config->has_audio, pipe_config->has_infoframe, 5387 pipe_config->infoframes.enable); 5388 5389 if (pipe_config->infoframes.enable & 5390 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) 5391 drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n", 5392 pipe_config->infoframes.gcp); 5393 if (pipe_config->infoframes.enable & 5394 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) 5395 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi); 5396 if (pipe_config->infoframes.enable & 5397 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD)) 5398 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd); 5399 if (pipe_config->infoframes.enable & 5400 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR)) 5401 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi); 5402 if (pipe_config->infoframes.enable & 5403 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) 5404 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); 5405 if (pipe_config->infoframes.enable & 5406 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA)) 5407 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); 5408 if (pipe_config->infoframes.enable & 5409 intel_hdmi_infoframe_enable(DP_SDP_VSC)) 5410 intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc); 5411 5412 drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n", 5413 str_yes_no(pipe_config->vrr.enable), 5414 pipe_config->vrr.vmin, pipe_config->vrr.vmax, 5415 pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband, 5416 pipe_config->vrr.flipline, 5417 intel_vrr_vmin_vblank_start(pipe_config), 5418 intel_vrr_vmax_vblank_start(pipe_config)); 5419 5420 drm_dbg_kms(&dev_priv->drm, "requested mode:\n"); 5421 drm_mode_debug_printmodeline(&pipe_config->hw.mode); 5422 drm_dbg_kms(&dev_priv->drm, "adjusted mode:\n"); 5423 drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode); 5424 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode); 5425 drm_dbg_kms(&dev_priv->drm, "pipe mode:\n"); 5426 drm_mode_debug_printmodeline(&pipe_config->hw.pipe_mode); 5427 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode); 5428 drm_dbg_kms(&dev_priv->drm, 5429 "port clock: %d, pipe src: " DRM_RECT_FMT ", pixel rate %d\n", 5430 pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src), 5431 pipe_config->pixel_rate); 5432 5433 drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n", 5434 pipe_config->linetime, pipe_config->ips_linetime); 5435 5436 if (DISPLAY_VER(dev_priv) >= 9) 5437 drm_dbg_kms(&dev_priv->drm, 5438 "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", 5439 crtc->num_scalers, 5440 pipe_config->scaler_state.scaler_users, 5441 pipe_config->scaler_state.scaler_id); 5442 5443 if (HAS_GMCH(dev_priv)) 5444 drm_dbg_kms(&dev_priv->drm, 5445 "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", 5446 pipe_config->gmch_pfit.control, 5447 pipe_config->gmch_pfit.pgm_ratios, 5448 pipe_config->gmch_pfit.lvds_border_bits); 5449 else 5450 drm_dbg_kms(&dev_priv->drm, 5451 "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n", 5452 DRM_RECT_ARG(&pipe_config->pch_pfit.dst), 5453 str_enabled_disabled(pipe_config->pch_pfit.enabled), 5454 str_yes_no(pipe_config->pch_pfit.force_thru)); 5455 5456 drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i, drrs: %i\n", 5457 pipe_config->ips_enabled, pipe_config->double_wide, 5458 pipe_config->has_drrs); 5459 5460 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state); 5461 5462 if (IS_CHERRYVIEW(dev_priv)) 5463 drm_dbg_kms(&dev_priv->drm, 5464 "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", 5465 pipe_config->cgm_mode, pipe_config->gamma_mode, 5466 pipe_config->gamma_enable, pipe_config->csc_enable); 5467 else 5468 drm_dbg_kms(&dev_priv->drm, 5469 "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", 5470 pipe_config->csc_mode, pipe_config->gamma_mode, 5471 pipe_config->gamma_enable, pipe_config->csc_enable); 5472 5473 drm_dbg_kms(&dev_priv->drm, "degamma lut: %d entries, gamma lut: %d entries\n", 5474 pipe_config->hw.degamma_lut ? 5475 drm_color_lut_size(pipe_config->hw.degamma_lut) : 0, 5476 pipe_config->hw.gamma_lut ? 5477 drm_color_lut_size(pipe_config->hw.gamma_lut) : 0); 5478 5479 dump_planes: 5480 if (!state) 5481 return; 5482 5483 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 5484 if (plane->pipe == crtc->pipe) 5485 intel_dump_plane_state(plane_state); 5486 } 5487 } 5488 5489 static bool check_digital_port_conflicts(struct intel_atomic_state *state) 5490 { 5491 struct drm_device *dev = state->base.dev; 5492 struct drm_connector *connector; 5493 struct drm_connector_list_iter conn_iter; 5494 unsigned int used_ports = 0; 5495 unsigned int used_mst_ports = 0; 5496 bool ret = true; 5497 5498 /* 5499 * We're going to peek into connector->state, 5500 * hence connection_mutex must be held. 5501 */ 5502 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex); 5503 5504 /* 5505 * Walk the connector list instead of the encoder 5506 * list to detect the problem on ddi platforms 5507 * where there's just one encoder per digital port. 5508 */ 5509 drm_connector_list_iter_begin(dev, &conn_iter); 5510 drm_for_each_connector_iter(connector, &conn_iter) { 5511 struct drm_connector_state *connector_state; 5512 struct intel_encoder *encoder; 5513 5514 connector_state = 5515 drm_atomic_get_new_connector_state(&state->base, 5516 connector); 5517 if (!connector_state) 5518 connector_state = connector->state; 5519 5520 if (!connector_state->best_encoder) 5521 continue; 5522 5523 encoder = to_intel_encoder(connector_state->best_encoder); 5524 5525 drm_WARN_ON(dev, !connector_state->crtc); 5526 5527 switch (encoder->type) { 5528 case INTEL_OUTPUT_DDI: 5529 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev)))) 5530 break; 5531 fallthrough; 5532 case INTEL_OUTPUT_DP: 5533 case INTEL_OUTPUT_HDMI: 5534 case INTEL_OUTPUT_EDP: 5535 /* the same port mustn't appear more than once */ 5536 if (used_ports & BIT(encoder->port)) 5537 ret = false; 5538 5539 used_ports |= BIT(encoder->port); 5540 break; 5541 case INTEL_OUTPUT_DP_MST: 5542 used_mst_ports |= 5543 1 << encoder->port; 5544 break; 5545 default: 5546 break; 5547 } 5548 } 5549 drm_connector_list_iter_end(&conn_iter); 5550 5551 /* can't mix MST and SST/HDMI on the same port */ 5552 if (used_ports & used_mst_ports) 5553 return false; 5554 5555 return ret; 5556 } 5557 5558 static void 5559 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state, 5560 struct intel_crtc *crtc) 5561 { 5562 struct intel_crtc_state *crtc_state = 5563 intel_atomic_get_new_crtc_state(state, crtc); 5564 5565 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 5566 5567 drm_property_replace_blob(&crtc_state->hw.degamma_lut, 5568 crtc_state->uapi.degamma_lut); 5569 drm_property_replace_blob(&crtc_state->hw.gamma_lut, 5570 crtc_state->uapi.gamma_lut); 5571 drm_property_replace_blob(&crtc_state->hw.ctm, 5572 crtc_state->uapi.ctm); 5573 } 5574 5575 static void 5576 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state, 5577 struct intel_crtc *crtc) 5578 { 5579 struct intel_crtc_state *crtc_state = 5580 intel_atomic_get_new_crtc_state(state, crtc); 5581 5582 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 5583 5584 crtc_state->hw.enable = crtc_state->uapi.enable; 5585 crtc_state->hw.active = crtc_state->uapi.active; 5586 drm_mode_copy(&crtc_state->hw.mode, 5587 &crtc_state->uapi.mode); 5588 drm_mode_copy(&crtc_state->hw.adjusted_mode, 5589 &crtc_state->uapi.adjusted_mode); 5590 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter; 5591 5592 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 5593 } 5594 5595 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state) 5596 { 5597 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 5598 return; 5599 5600 crtc_state->uapi.enable = crtc_state->hw.enable; 5601 crtc_state->uapi.active = crtc_state->hw.active; 5602 drm_WARN_ON(crtc_state->uapi.crtc->dev, 5603 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0); 5604 5605 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode; 5606 crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter; 5607 5608 drm_property_replace_blob(&crtc_state->uapi.degamma_lut, 5609 crtc_state->hw.degamma_lut); 5610 drm_property_replace_blob(&crtc_state->uapi.gamma_lut, 5611 crtc_state->hw.gamma_lut); 5612 drm_property_replace_blob(&crtc_state->uapi.ctm, 5613 crtc_state->hw.ctm); 5614 } 5615 5616 static void 5617 copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state, 5618 struct intel_crtc *slave_crtc) 5619 { 5620 struct intel_crtc_state *slave_crtc_state = 5621 intel_atomic_get_new_crtc_state(state, slave_crtc); 5622 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 5623 const struct intel_crtc_state *master_crtc_state = 5624 intel_atomic_get_new_crtc_state(state, master_crtc); 5625 5626 drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut, 5627 master_crtc_state->hw.degamma_lut); 5628 drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut, 5629 master_crtc_state->hw.gamma_lut); 5630 drm_property_replace_blob(&slave_crtc_state->hw.ctm, 5631 master_crtc_state->hw.ctm); 5632 5633 slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed; 5634 } 5635 5636 static int 5637 copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state, 5638 struct intel_crtc *slave_crtc) 5639 { 5640 struct intel_crtc_state *slave_crtc_state = 5641 intel_atomic_get_new_crtc_state(state, slave_crtc); 5642 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 5643 const struct intel_crtc_state *master_crtc_state = 5644 intel_atomic_get_new_crtc_state(state, master_crtc); 5645 struct intel_crtc_state *saved_state; 5646 5647 WARN_ON(master_crtc_state->bigjoiner_pipes != 5648 slave_crtc_state->bigjoiner_pipes); 5649 5650 saved_state = kmemdup(master_crtc_state, sizeof(*saved_state), GFP_KERNEL); 5651 if (!saved_state) 5652 return -ENOMEM; 5653 5654 /* preserve some things from the slave's original crtc state */ 5655 saved_state->uapi = slave_crtc_state->uapi; 5656 saved_state->scaler_state = slave_crtc_state->scaler_state; 5657 saved_state->shared_dpll = slave_crtc_state->shared_dpll; 5658 saved_state->dpll_hw_state = slave_crtc_state->dpll_hw_state; 5659 saved_state->crc_enabled = slave_crtc_state->crc_enabled; 5660 5661 intel_crtc_free_hw_state(slave_crtc_state); 5662 memcpy(slave_crtc_state, saved_state, sizeof(*slave_crtc_state)); 5663 kfree(saved_state); 5664 5665 /* Re-init hw state */ 5666 memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw)); 5667 slave_crtc_state->hw.enable = master_crtc_state->hw.enable; 5668 slave_crtc_state->hw.active = master_crtc_state->hw.active; 5669 drm_mode_copy(&slave_crtc_state->hw.mode, 5670 &master_crtc_state->hw.mode); 5671 drm_mode_copy(&slave_crtc_state->hw.pipe_mode, 5672 &master_crtc_state->hw.pipe_mode); 5673 drm_mode_copy(&slave_crtc_state->hw.adjusted_mode, 5674 &master_crtc_state->hw.adjusted_mode); 5675 slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter; 5676 5677 copy_bigjoiner_crtc_state_nomodeset(state, slave_crtc); 5678 5679 slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed; 5680 slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed; 5681 slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed; 5682 5683 WARN_ON(master_crtc_state->bigjoiner_pipes != 5684 slave_crtc_state->bigjoiner_pipes); 5685 5686 return 0; 5687 } 5688 5689 static int 5690 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state, 5691 struct intel_crtc *crtc) 5692 { 5693 struct intel_crtc_state *crtc_state = 5694 intel_atomic_get_new_crtc_state(state, crtc); 5695 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5696 struct intel_crtc_state *saved_state; 5697 5698 saved_state = intel_crtc_state_alloc(crtc); 5699 if (!saved_state) 5700 return -ENOMEM; 5701 5702 /* free the old crtc_state->hw members */ 5703 intel_crtc_free_hw_state(crtc_state); 5704 5705 /* FIXME: before the switch to atomic started, a new pipe_config was 5706 * kzalloc'd. Code that depends on any field being zero should be 5707 * fixed, so that the crtc_state can be safely duplicated. For now, 5708 * only fields that are know to not cause problems are preserved. */ 5709 5710 saved_state->uapi = crtc_state->uapi; 5711 saved_state->scaler_state = crtc_state->scaler_state; 5712 saved_state->shared_dpll = crtc_state->shared_dpll; 5713 saved_state->dpll_hw_state = crtc_state->dpll_hw_state; 5714 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, 5715 sizeof(saved_state->icl_port_dplls)); 5716 saved_state->crc_enabled = crtc_state->crc_enabled; 5717 if (IS_G4X(dev_priv) || 5718 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5719 saved_state->wm = crtc_state->wm; 5720 5721 memcpy(crtc_state, saved_state, sizeof(*crtc_state)); 5722 kfree(saved_state); 5723 5724 intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc); 5725 5726 return 0; 5727 } 5728 5729 static int 5730 intel_modeset_pipe_config(struct intel_atomic_state *state, 5731 struct intel_crtc_state *pipe_config) 5732 { 5733 struct drm_crtc *crtc = pipe_config->uapi.crtc; 5734 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); 5735 struct drm_connector *connector; 5736 struct drm_connector_state *connector_state; 5737 int pipe_src_w, pipe_src_h; 5738 int base_bpp, ret, i; 5739 bool retry = true; 5740 5741 pipe_config->cpu_transcoder = 5742 (enum transcoder) to_intel_crtc(crtc)->pipe; 5743 5744 pipe_config->framestart_delay = 1; 5745 5746 /* 5747 * Sanitize sync polarity flags based on requested ones. If neither 5748 * positive or negative polarity is requested, treat this as meaning 5749 * negative polarity. 5750 */ 5751 if (!(pipe_config->hw.adjusted_mode.flags & 5752 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) 5753 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; 5754 5755 if (!(pipe_config->hw.adjusted_mode.flags & 5756 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 5757 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; 5758 5759 ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc), 5760 pipe_config); 5761 if (ret) 5762 return ret; 5763 5764 base_bpp = pipe_config->pipe_bpp; 5765 5766 /* 5767 * Determine the real pipe dimensions. Note that stereo modes can 5768 * increase the actual pipe size due to the frame doubling and 5769 * insertion of additional space for blanks between the frame. This 5770 * is stored in the crtc timings. We use the requested mode to do this 5771 * computation to clearly distinguish it from the adjusted mode, which 5772 * can be changed by the connectors in the below retry loop. 5773 */ 5774 drm_mode_get_hv_timing(&pipe_config->hw.mode, 5775 &pipe_src_w, &pipe_src_h); 5776 drm_rect_init(&pipe_config->pipe_src, 0, 0, 5777 pipe_src_w, pipe_src_h); 5778 5779 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5780 struct intel_encoder *encoder = 5781 to_intel_encoder(connector_state->best_encoder); 5782 5783 if (connector_state->crtc != crtc) 5784 continue; 5785 5786 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) { 5787 drm_dbg_kms(&i915->drm, 5788 "rejecting invalid cloning configuration\n"); 5789 return -EINVAL; 5790 } 5791 5792 /* 5793 * Determine output_types before calling the .compute_config() 5794 * hooks so that the hooks can use this information safely. 5795 */ 5796 if (encoder->compute_output_type) 5797 pipe_config->output_types |= 5798 BIT(encoder->compute_output_type(encoder, pipe_config, 5799 connector_state)); 5800 else 5801 pipe_config->output_types |= BIT(encoder->type); 5802 } 5803 5804 encoder_retry: 5805 /* Ensure the port clock defaults are reset when retrying. */ 5806 pipe_config->port_clock = 0; 5807 pipe_config->pixel_multiplier = 1; 5808 5809 /* Fill in default crtc timings, allow encoders to overwrite them. */ 5810 drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode, 5811 CRTC_STEREO_DOUBLE); 5812 5813 /* Pass our mode to the connectors and the CRTC to give them a chance to 5814 * adjust it according to limitations or connector properties, and also 5815 * a chance to reject the mode entirely. 5816 */ 5817 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5818 struct intel_encoder *encoder = 5819 to_intel_encoder(connector_state->best_encoder); 5820 5821 if (connector_state->crtc != crtc) 5822 continue; 5823 5824 ret = encoder->compute_config(encoder, pipe_config, 5825 connector_state); 5826 if (ret == -EDEADLK) 5827 return ret; 5828 if (ret < 0) { 5829 drm_dbg_kms(&i915->drm, "Encoder config failure: %d\n", ret); 5830 return ret; 5831 } 5832 } 5833 5834 /* Set default port clock if not overwritten by the encoder. Needs to be 5835 * done afterwards in case the encoder adjusts the mode. */ 5836 if (!pipe_config->port_clock) 5837 pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock 5838 * pipe_config->pixel_multiplier; 5839 5840 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); 5841 if (ret == -EDEADLK) 5842 return ret; 5843 if (ret == -EAGAIN) { 5844 if (drm_WARN(&i915->drm, !retry, 5845 "loop in pipe configuration computation\n")) 5846 return -EINVAL; 5847 5848 drm_dbg_kms(&i915->drm, "CRTC bw constrained, retrying\n"); 5849 retry = false; 5850 goto encoder_retry; 5851 } 5852 if (ret < 0) { 5853 drm_dbg_kms(&i915->drm, "CRTC config failure: %d\n", ret); 5854 return ret; 5855 } 5856 5857 /* Dithering seems to not pass-through bits correctly when it should, so 5858 * only enable it on 6bpc panels and when its not a compliance 5859 * test requesting 6bpc video pattern. 5860 */ 5861 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) && 5862 !pipe_config->dither_force_disable; 5863 drm_dbg_kms(&i915->drm, 5864 "hw max bpp: %i, pipe bpp: %i, dithering: %i\n", 5865 base_bpp, pipe_config->pipe_bpp, pipe_config->dither); 5866 5867 return 0; 5868 } 5869 5870 static int 5871 intel_modeset_pipe_config_late(struct intel_crtc_state *crtc_state) 5872 { 5873 struct intel_atomic_state *state = 5874 to_intel_atomic_state(crtc_state->uapi.state); 5875 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 5876 struct drm_connector_state *conn_state; 5877 struct drm_connector *connector; 5878 int i; 5879 5880 intel_bigjoiner_adjust_pipe_src(crtc_state); 5881 5882 for_each_new_connector_in_state(&state->base, connector, 5883 conn_state, i) { 5884 struct intel_encoder *encoder = 5885 to_intel_encoder(conn_state->best_encoder); 5886 int ret; 5887 5888 if (conn_state->crtc != &crtc->base || 5889 !encoder->compute_config_late) 5890 continue; 5891 5892 ret = encoder->compute_config_late(encoder, crtc_state, 5893 conn_state); 5894 if (ret) 5895 return ret; 5896 } 5897 5898 return 0; 5899 } 5900 5901 bool intel_fuzzy_clock_check(int clock1, int clock2) 5902 { 5903 int diff; 5904 5905 if (clock1 == clock2) 5906 return true; 5907 5908 if (!clock1 || !clock2) 5909 return false; 5910 5911 diff = abs(clock1 - clock2); 5912 5913 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) 5914 return true; 5915 5916 return false; 5917 } 5918 5919 static bool 5920 intel_compare_m_n(unsigned int m, unsigned int n, 5921 unsigned int m2, unsigned int n2, 5922 bool exact) 5923 { 5924 if (m == m2 && n == n2) 5925 return true; 5926 5927 if (exact || !m || !n || !m2 || !n2) 5928 return false; 5929 5930 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); 5931 5932 if (n > n2) { 5933 while (n > n2) { 5934 m2 <<= 1; 5935 n2 <<= 1; 5936 } 5937 } else if (n < n2) { 5938 while (n < n2) { 5939 m <<= 1; 5940 n <<= 1; 5941 } 5942 } 5943 5944 if (n != n2) 5945 return false; 5946 5947 return intel_fuzzy_clock_check(m, m2); 5948 } 5949 5950 static bool 5951 intel_compare_link_m_n(const struct intel_link_m_n *m_n, 5952 const struct intel_link_m_n *m2_n2, 5953 bool exact) 5954 { 5955 return m_n->tu == m2_n2->tu && 5956 intel_compare_m_n(m_n->data_m, m_n->data_n, 5957 m2_n2->data_m, m2_n2->data_n, exact) && 5958 intel_compare_m_n(m_n->link_m, m_n->link_n, 5959 m2_n2->link_m, m2_n2->link_n, exact); 5960 } 5961 5962 static bool 5963 intel_compare_infoframe(const union hdmi_infoframe *a, 5964 const union hdmi_infoframe *b) 5965 { 5966 return memcmp(a, b, sizeof(*a)) == 0; 5967 } 5968 5969 static bool 5970 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a, 5971 const struct drm_dp_vsc_sdp *b) 5972 { 5973 return memcmp(a, b, sizeof(*a)) == 0; 5974 } 5975 5976 static void 5977 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv, 5978 bool fastset, const char *name, 5979 const union hdmi_infoframe *a, 5980 const union hdmi_infoframe *b) 5981 { 5982 if (fastset) { 5983 if (!drm_debug_enabled(DRM_UT_KMS)) 5984 return; 5985 5986 drm_dbg_kms(&dev_priv->drm, 5987 "fastset mismatch in %s infoframe\n", name); 5988 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 5989 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a); 5990 drm_dbg_kms(&dev_priv->drm, "found:\n"); 5991 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b); 5992 } else { 5993 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name); 5994 drm_err(&dev_priv->drm, "expected:\n"); 5995 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a); 5996 drm_err(&dev_priv->drm, "found:\n"); 5997 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b); 5998 } 5999 } 6000 6001 static void 6002 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv, 6003 bool fastset, const char *name, 6004 const struct drm_dp_vsc_sdp *a, 6005 const struct drm_dp_vsc_sdp *b) 6006 { 6007 if (fastset) { 6008 if (!drm_debug_enabled(DRM_UT_KMS)) 6009 return; 6010 6011 drm_dbg_kms(&dev_priv->drm, 6012 "fastset mismatch in %s dp sdp\n", name); 6013 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 6014 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a); 6015 drm_dbg_kms(&dev_priv->drm, "found:\n"); 6016 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b); 6017 } else { 6018 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name); 6019 drm_err(&dev_priv->drm, "expected:\n"); 6020 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a); 6021 drm_err(&dev_priv->drm, "found:\n"); 6022 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b); 6023 } 6024 } 6025 6026 static void __printf(4, 5) 6027 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc, 6028 const char *name, const char *format, ...) 6029 { 6030 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 6031 struct va_format vaf; 6032 va_list args; 6033 6034 va_start(args, format); 6035 vaf.fmt = format; 6036 vaf.va = &args; 6037 6038 if (fastset) 6039 drm_dbg_kms(&i915->drm, 6040 "[CRTC:%d:%s] fastset mismatch in %s %pV\n", 6041 crtc->base.base.id, crtc->base.name, name, &vaf); 6042 else 6043 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n", 6044 crtc->base.base.id, crtc->base.name, name, &vaf); 6045 6046 va_end(args); 6047 } 6048 6049 static bool fastboot_enabled(struct drm_i915_private *dev_priv) 6050 { 6051 if (dev_priv->params.fastboot != -1) 6052 return dev_priv->params.fastboot; 6053 6054 /* Enable fastboot by default on Skylake and newer */ 6055 if (DISPLAY_VER(dev_priv) >= 9) 6056 return true; 6057 6058 /* Enable fastboot by default on VLV and CHV */ 6059 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 6060 return true; 6061 6062 /* Disabled by default on all others */ 6063 return false; 6064 } 6065 6066 static bool 6067 intel_pipe_config_compare(const struct intel_crtc_state *current_config, 6068 const struct intel_crtc_state *pipe_config, 6069 bool fastset) 6070 { 6071 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev); 6072 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 6073 bool ret = true; 6074 u32 bp_gamma = 0; 6075 bool fixup_inherited = fastset && 6076 current_config->inherited && !pipe_config->inherited; 6077 6078 if (fixup_inherited && !fastboot_enabled(dev_priv)) { 6079 drm_dbg_kms(&dev_priv->drm, 6080 "initial modeset and fastboot not set\n"); 6081 ret = false; 6082 } 6083 6084 #define PIPE_CONF_CHECK_X(name) do { \ 6085 if (current_config->name != pipe_config->name) { \ 6086 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6087 "(expected 0x%08x, found 0x%08x)", \ 6088 current_config->name, \ 6089 pipe_config->name); \ 6090 ret = false; \ 6091 } \ 6092 } while (0) 6093 6094 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \ 6095 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \ 6096 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6097 "(expected 0x%08x, found 0x%08x)", \ 6098 current_config->name & (mask), \ 6099 pipe_config->name & (mask)); \ 6100 ret = false; \ 6101 } \ 6102 } while (0) 6103 6104 #define PIPE_CONF_CHECK_I(name) do { \ 6105 if (current_config->name != pipe_config->name) { \ 6106 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6107 "(expected %i, found %i)", \ 6108 current_config->name, \ 6109 pipe_config->name); \ 6110 ret = false; \ 6111 } \ 6112 } while (0) 6113 6114 #define PIPE_CONF_CHECK_BOOL(name) do { \ 6115 if (current_config->name != pipe_config->name) { \ 6116 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6117 "(expected %s, found %s)", \ 6118 str_yes_no(current_config->name), \ 6119 str_yes_no(pipe_config->name)); \ 6120 ret = false; \ 6121 } \ 6122 } while (0) 6123 6124 /* 6125 * Checks state where we only read out the enabling, but not the entire 6126 * state itself (like full infoframes or ELD for audio). These states 6127 * require a full modeset on bootup to fix up. 6128 */ 6129 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \ 6130 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \ 6131 PIPE_CONF_CHECK_BOOL(name); \ 6132 } else { \ 6133 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6134 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \ 6135 str_yes_no(current_config->name), \ 6136 str_yes_no(pipe_config->name)); \ 6137 ret = false; \ 6138 } \ 6139 } while (0) 6140 6141 #define PIPE_CONF_CHECK_P(name) do { \ 6142 if (current_config->name != pipe_config->name) { \ 6143 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6144 "(expected %p, found %p)", \ 6145 current_config->name, \ 6146 pipe_config->name); \ 6147 ret = false; \ 6148 } \ 6149 } while (0) 6150 6151 #define PIPE_CONF_CHECK_M_N(name) do { \ 6152 if (!intel_compare_link_m_n(¤t_config->name, \ 6153 &pipe_config->name,\ 6154 !fastset)) { \ 6155 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6156 "(expected tu %i data %i/%i link %i/%i, " \ 6157 "found tu %i, data %i/%i link %i/%i)", \ 6158 current_config->name.tu, \ 6159 current_config->name.data_m, \ 6160 current_config->name.data_n, \ 6161 current_config->name.link_m, \ 6162 current_config->name.link_n, \ 6163 pipe_config->name.tu, \ 6164 pipe_config->name.data_m, \ 6165 pipe_config->name.data_n, \ 6166 pipe_config->name.link_m, \ 6167 pipe_config->name.link_n); \ 6168 ret = false; \ 6169 } \ 6170 } while (0) 6171 6172 /* This is required for BDW+ where there is only one set of registers for 6173 * switching between high and low RR. 6174 * This macro can be used whenever a comparison has to be made between one 6175 * hw state and multiple sw state variables. 6176 */ 6177 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \ 6178 if (!intel_compare_link_m_n(¤t_config->name, \ 6179 &pipe_config->name, !fastset) && \ 6180 !intel_compare_link_m_n(¤t_config->alt_name, \ 6181 &pipe_config->name, !fastset)) { \ 6182 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6183 "(expected tu %i data %i/%i link %i/%i, " \ 6184 "or tu %i data %i/%i link %i/%i, " \ 6185 "found tu %i, data %i/%i link %i/%i)", \ 6186 current_config->name.tu, \ 6187 current_config->name.data_m, \ 6188 current_config->name.data_n, \ 6189 current_config->name.link_m, \ 6190 current_config->name.link_n, \ 6191 current_config->alt_name.tu, \ 6192 current_config->alt_name.data_m, \ 6193 current_config->alt_name.data_n, \ 6194 current_config->alt_name.link_m, \ 6195 current_config->alt_name.link_n, \ 6196 pipe_config->name.tu, \ 6197 pipe_config->name.data_m, \ 6198 pipe_config->name.data_n, \ 6199 pipe_config->name.link_m, \ 6200 pipe_config->name.link_n); \ 6201 ret = false; \ 6202 } \ 6203 } while (0) 6204 6205 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \ 6206 if ((current_config->name ^ pipe_config->name) & (mask)) { \ 6207 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6208 "(%x) (expected %i, found %i)", \ 6209 (mask), \ 6210 current_config->name & (mask), \ 6211 pipe_config->name & (mask)); \ 6212 ret = false; \ 6213 } \ 6214 } while (0) 6215 6216 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \ 6217 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ 6218 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6219 "(expected %i, found %i)", \ 6220 current_config->name, \ 6221 pipe_config->name); \ 6222 ret = false; \ 6223 } \ 6224 } while (0) 6225 6226 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \ 6227 if (!intel_compare_infoframe(¤t_config->infoframes.name, \ 6228 &pipe_config->infoframes.name)) { \ 6229 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \ 6230 ¤t_config->infoframes.name, \ 6231 &pipe_config->infoframes.name); \ 6232 ret = false; \ 6233 } \ 6234 } while (0) 6235 6236 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \ 6237 if (!current_config->has_psr && !pipe_config->has_psr && \ 6238 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \ 6239 &pipe_config->infoframes.name)) { \ 6240 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \ 6241 ¤t_config->infoframes.name, \ 6242 &pipe_config->infoframes.name); \ 6243 ret = false; \ 6244 } \ 6245 } while (0) 6246 6247 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \ 6248 if (current_config->name1 != pipe_config->name1) { \ 6249 pipe_config_mismatch(fastset, crtc, __stringify(name1), \ 6250 "(expected %i, found %i, won't compare lut values)", \ 6251 current_config->name1, \ 6252 pipe_config->name1); \ 6253 ret = false;\ 6254 } else { \ 6255 if (!intel_color_lut_equal(current_config->name2, \ 6256 pipe_config->name2, pipe_config->name1, \ 6257 bit_precision)) { \ 6258 pipe_config_mismatch(fastset, crtc, __stringify(name2), \ 6259 "hw_state doesn't match sw_state"); \ 6260 ret = false; \ 6261 } \ 6262 } \ 6263 } while (0) 6264 6265 #define PIPE_CONF_QUIRK(quirk) \ 6266 ((current_config->quirks | pipe_config->quirks) & (quirk)) 6267 6268 PIPE_CONF_CHECK_I(cpu_transcoder); 6269 6270 PIPE_CONF_CHECK_BOOL(has_pch_encoder); 6271 PIPE_CONF_CHECK_I(fdi_lanes); 6272 PIPE_CONF_CHECK_M_N(fdi_m_n); 6273 6274 PIPE_CONF_CHECK_I(lane_count); 6275 PIPE_CONF_CHECK_X(lane_lat_optim_mask); 6276 6277 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) { 6278 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); 6279 } else { 6280 PIPE_CONF_CHECK_M_N(dp_m_n); 6281 PIPE_CONF_CHECK_M_N(dp_m2_n2); 6282 } 6283 6284 PIPE_CONF_CHECK_X(output_types); 6285 6286 PIPE_CONF_CHECK_I(framestart_delay); 6287 PIPE_CONF_CHECK_I(msa_timing_delay); 6288 6289 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay); 6290 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_htotal); 6291 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_start); 6292 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_end); 6293 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_start); 6294 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_end); 6295 6296 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vdisplay); 6297 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vtotal); 6298 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_start); 6299 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_end); 6300 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_start); 6301 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_end); 6302 6303 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay); 6304 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal); 6305 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start); 6306 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end); 6307 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start); 6308 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end); 6309 6310 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay); 6311 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal); 6312 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start); 6313 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end); 6314 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start); 6315 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end); 6316 6317 PIPE_CONF_CHECK_I(pixel_multiplier); 6318 6319 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6320 DRM_MODE_FLAG_INTERLACE); 6321 6322 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { 6323 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6324 DRM_MODE_FLAG_PHSYNC); 6325 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6326 DRM_MODE_FLAG_NHSYNC); 6327 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6328 DRM_MODE_FLAG_PVSYNC); 6329 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6330 DRM_MODE_FLAG_NVSYNC); 6331 } 6332 6333 PIPE_CONF_CHECK_I(output_format); 6334 PIPE_CONF_CHECK_BOOL(has_hdmi_sink); 6335 if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || 6336 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 6337 PIPE_CONF_CHECK_BOOL(limited_color_range); 6338 6339 PIPE_CONF_CHECK_BOOL(hdmi_scrambling); 6340 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio); 6341 PIPE_CONF_CHECK_BOOL(has_infoframe); 6342 PIPE_CONF_CHECK_BOOL(fec_enable); 6343 6344 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio); 6345 6346 PIPE_CONF_CHECK_X(gmch_pfit.control); 6347 /* pfit ratios are autocomputed by the hw on gen4+ */ 6348 if (DISPLAY_VER(dev_priv) < 4) 6349 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); 6350 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); 6351 6352 /* 6353 * Changing the EDP transcoder input mux 6354 * (A_ONOFF vs. A_ON) requires a full modeset. 6355 */ 6356 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru); 6357 6358 if (!fastset) { 6359 PIPE_CONF_CHECK_I(pipe_src.x1); 6360 PIPE_CONF_CHECK_I(pipe_src.y1); 6361 PIPE_CONF_CHECK_I(pipe_src.x2); 6362 PIPE_CONF_CHECK_I(pipe_src.y2); 6363 6364 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled); 6365 if (current_config->pch_pfit.enabled) { 6366 PIPE_CONF_CHECK_I(pch_pfit.dst.x1); 6367 PIPE_CONF_CHECK_I(pch_pfit.dst.y1); 6368 PIPE_CONF_CHECK_I(pch_pfit.dst.x2); 6369 PIPE_CONF_CHECK_I(pch_pfit.dst.y2); 6370 } 6371 6372 PIPE_CONF_CHECK_I(scaler_state.scaler_id); 6373 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate); 6374 6375 PIPE_CONF_CHECK_X(gamma_mode); 6376 if (IS_CHERRYVIEW(dev_priv)) 6377 PIPE_CONF_CHECK_X(cgm_mode); 6378 else 6379 PIPE_CONF_CHECK_X(csc_mode); 6380 PIPE_CONF_CHECK_BOOL(gamma_enable); 6381 PIPE_CONF_CHECK_BOOL(csc_enable); 6382 6383 PIPE_CONF_CHECK_I(linetime); 6384 PIPE_CONF_CHECK_I(ips_linetime); 6385 6386 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config); 6387 if (bp_gamma) 6388 PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma); 6389 6390 if (current_config->active_planes) { 6391 PIPE_CONF_CHECK_BOOL(has_psr); 6392 PIPE_CONF_CHECK_BOOL(has_psr2); 6393 PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); 6394 PIPE_CONF_CHECK_I(dc3co_exitline); 6395 } 6396 } 6397 6398 PIPE_CONF_CHECK_BOOL(double_wide); 6399 6400 if (dev_priv->dpll.mgr) { 6401 PIPE_CONF_CHECK_P(shared_dpll); 6402 6403 PIPE_CONF_CHECK_X(dpll_hw_state.dpll); 6404 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); 6405 PIPE_CONF_CHECK_X(dpll_hw_state.fp0); 6406 PIPE_CONF_CHECK_X(dpll_hw_state.fp1); 6407 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); 6408 PIPE_CONF_CHECK_X(dpll_hw_state.spll); 6409 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); 6410 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); 6411 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); 6412 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); 6413 PIPE_CONF_CHECK_X(dpll_hw_state.div0); 6414 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); 6415 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); 6416 PIPE_CONF_CHECK_X(dpll_hw_state.pll0); 6417 PIPE_CONF_CHECK_X(dpll_hw_state.pll1); 6418 PIPE_CONF_CHECK_X(dpll_hw_state.pll2); 6419 PIPE_CONF_CHECK_X(dpll_hw_state.pll3); 6420 PIPE_CONF_CHECK_X(dpll_hw_state.pll6); 6421 PIPE_CONF_CHECK_X(dpll_hw_state.pll8); 6422 PIPE_CONF_CHECK_X(dpll_hw_state.pll9); 6423 PIPE_CONF_CHECK_X(dpll_hw_state.pll10); 6424 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); 6425 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl); 6426 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1); 6427 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl); 6428 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0); 6429 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1); 6430 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf); 6431 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock); 6432 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc); 6433 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias); 6434 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias); 6435 } 6436 6437 PIPE_CONF_CHECK_X(dsi_pll.ctrl); 6438 PIPE_CONF_CHECK_X(dsi_pll.div); 6439 6440 if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5) 6441 PIPE_CONF_CHECK_I(pipe_bpp); 6442 6443 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock); 6444 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock); 6445 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); 6446 6447 PIPE_CONF_CHECK_I(min_voltage_level); 6448 6449 if (current_config->has_psr || pipe_config->has_psr) 6450 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable, 6451 ~intel_hdmi_infoframe_enable(DP_SDP_VSC)); 6452 else 6453 PIPE_CONF_CHECK_X(infoframes.enable); 6454 6455 PIPE_CONF_CHECK_X(infoframes.gcp); 6456 PIPE_CONF_CHECK_INFOFRAME(avi); 6457 PIPE_CONF_CHECK_INFOFRAME(spd); 6458 PIPE_CONF_CHECK_INFOFRAME(hdmi); 6459 PIPE_CONF_CHECK_INFOFRAME(drm); 6460 PIPE_CONF_CHECK_DP_VSC_SDP(vsc); 6461 6462 PIPE_CONF_CHECK_X(sync_mode_slaves_mask); 6463 PIPE_CONF_CHECK_I(master_transcoder); 6464 PIPE_CONF_CHECK_X(bigjoiner_pipes); 6465 6466 PIPE_CONF_CHECK_I(dsc.compression_enable); 6467 PIPE_CONF_CHECK_I(dsc.dsc_split); 6468 PIPE_CONF_CHECK_I(dsc.compressed_bpp); 6469 6470 PIPE_CONF_CHECK_BOOL(splitter.enable); 6471 PIPE_CONF_CHECK_I(splitter.link_count); 6472 PIPE_CONF_CHECK_I(splitter.pixel_overlap); 6473 6474 PIPE_CONF_CHECK_I(mst_master_transcoder); 6475 6476 PIPE_CONF_CHECK_BOOL(vrr.enable); 6477 PIPE_CONF_CHECK_I(vrr.vmin); 6478 PIPE_CONF_CHECK_I(vrr.vmax); 6479 PIPE_CONF_CHECK_I(vrr.flipline); 6480 PIPE_CONF_CHECK_I(vrr.pipeline_full); 6481 PIPE_CONF_CHECK_I(vrr.guardband); 6482 6483 #undef PIPE_CONF_CHECK_X 6484 #undef PIPE_CONF_CHECK_I 6485 #undef PIPE_CONF_CHECK_BOOL 6486 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE 6487 #undef PIPE_CONF_CHECK_P 6488 #undef PIPE_CONF_CHECK_FLAGS 6489 #undef PIPE_CONF_CHECK_CLOCK_FUZZY 6490 #undef PIPE_CONF_CHECK_COLOR_LUT 6491 #undef PIPE_CONF_QUIRK 6492 6493 return ret; 6494 } 6495 6496 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, 6497 const struct intel_crtc_state *pipe_config) 6498 { 6499 if (pipe_config->has_pch_encoder) { 6500 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), 6501 &pipe_config->fdi_m_n); 6502 int dotclock = pipe_config->hw.adjusted_mode.crtc_clock; 6503 6504 /* 6505 * FDI already provided one idea for the dotclock. 6506 * Yell if the encoder disagrees. 6507 */ 6508 drm_WARN(&dev_priv->drm, 6509 !intel_fuzzy_clock_check(fdi_dotclock, dotclock), 6510 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", 6511 fdi_dotclock, dotclock); 6512 } 6513 } 6514 6515 static void verify_wm_state(struct intel_crtc *crtc, 6516 struct intel_crtc_state *new_crtc_state) 6517 { 6518 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6519 struct skl_hw_state { 6520 struct skl_ddb_entry ddb[I915_MAX_PLANES]; 6521 struct skl_ddb_entry ddb_y[I915_MAX_PLANES]; 6522 struct skl_pipe_wm wm; 6523 } *hw; 6524 const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal; 6525 int level, max_level = ilk_wm_max_level(dev_priv); 6526 struct intel_plane *plane; 6527 u8 hw_enabled_slices; 6528 6529 if (DISPLAY_VER(dev_priv) < 9 || !new_crtc_state->hw.active) 6530 return; 6531 6532 hw = kzalloc(sizeof(*hw), GFP_KERNEL); 6533 if (!hw) 6534 return; 6535 6536 skl_pipe_wm_get_hw_state(crtc, &hw->wm); 6537 6538 skl_pipe_ddb_get_hw_state(crtc, hw->ddb, hw->ddb_y); 6539 6540 hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv); 6541 6542 if (DISPLAY_VER(dev_priv) >= 11 && 6543 hw_enabled_slices != dev_priv->dbuf.enabled_slices) 6544 drm_err(&dev_priv->drm, 6545 "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n", 6546 dev_priv->dbuf.enabled_slices, 6547 hw_enabled_slices); 6548 6549 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 6550 const struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; 6551 const struct skl_wm_level *hw_wm_level, *sw_wm_level; 6552 6553 /* Watermarks */ 6554 for (level = 0; level <= max_level; level++) { 6555 hw_wm_level = &hw->wm.planes[plane->id].wm[level]; 6556 sw_wm_level = skl_plane_wm_level(sw_wm, plane->id, level); 6557 6558 if (skl_wm_level_equals(hw_wm_level, sw_wm_level)) 6559 continue; 6560 6561 drm_err(&dev_priv->drm, 6562 "[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 6563 plane->base.base.id, plane->base.name, level, 6564 sw_wm_level->enable, 6565 sw_wm_level->blocks, 6566 sw_wm_level->lines, 6567 hw_wm_level->enable, 6568 hw_wm_level->blocks, 6569 hw_wm_level->lines); 6570 } 6571 6572 hw_wm_level = &hw->wm.planes[plane->id].trans_wm; 6573 sw_wm_level = skl_plane_trans_wm(sw_wm, plane->id); 6574 6575 if (!skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 6576 drm_err(&dev_priv->drm, 6577 "[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 6578 plane->base.base.id, plane->base.name, 6579 sw_wm_level->enable, 6580 sw_wm_level->blocks, 6581 sw_wm_level->lines, 6582 hw_wm_level->enable, 6583 hw_wm_level->blocks, 6584 hw_wm_level->lines); 6585 } 6586 6587 hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0; 6588 sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0; 6589 6590 if (HAS_HW_SAGV_WM(dev_priv) && 6591 !skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 6592 drm_err(&dev_priv->drm, 6593 "[PLANE:%d:%s] mismatch in SAGV WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 6594 plane->base.base.id, plane->base.name, 6595 sw_wm_level->enable, 6596 sw_wm_level->blocks, 6597 sw_wm_level->lines, 6598 hw_wm_level->enable, 6599 hw_wm_level->blocks, 6600 hw_wm_level->lines); 6601 } 6602 6603 hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm; 6604 sw_wm_level = &sw_wm->planes[plane->id].sagv.trans_wm; 6605 6606 if (HAS_HW_SAGV_WM(dev_priv) && 6607 !skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 6608 drm_err(&dev_priv->drm, 6609 "[PLANE:%d:%s] mismatch in SAGV trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 6610 plane->base.base.id, plane->base.name, 6611 sw_wm_level->enable, 6612 sw_wm_level->blocks, 6613 sw_wm_level->lines, 6614 hw_wm_level->enable, 6615 hw_wm_level->blocks, 6616 hw_wm_level->lines); 6617 } 6618 6619 /* DDB */ 6620 hw_ddb_entry = &hw->ddb[PLANE_CURSOR]; 6621 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[PLANE_CURSOR]; 6622 6623 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { 6624 drm_err(&dev_priv->drm, 6625 "[PLANE:%d:%s] mismatch in DDB (expected (%u,%u), found (%u,%u))\n", 6626 plane->base.base.id, plane->base.name, 6627 sw_ddb_entry->start, sw_ddb_entry->end, 6628 hw_ddb_entry->start, hw_ddb_entry->end); 6629 } 6630 } 6631 6632 kfree(hw); 6633 } 6634 6635 static void 6636 verify_connector_state(struct intel_atomic_state *state, 6637 struct intel_crtc *crtc) 6638 { 6639 struct drm_connector *connector; 6640 struct drm_connector_state *new_conn_state; 6641 int i; 6642 6643 for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) { 6644 struct drm_encoder *encoder = connector->encoder; 6645 struct intel_crtc_state *crtc_state = NULL; 6646 6647 if (new_conn_state->crtc != &crtc->base) 6648 continue; 6649 6650 if (crtc) 6651 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6652 6653 intel_connector_verify_state(crtc_state, new_conn_state); 6654 6655 I915_STATE_WARN(new_conn_state->best_encoder != encoder, 6656 "connector's atomic encoder doesn't match legacy encoder\n"); 6657 } 6658 } 6659 6660 static void 6661 verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state) 6662 { 6663 struct intel_encoder *encoder; 6664 struct drm_connector *connector; 6665 struct drm_connector_state *old_conn_state, *new_conn_state; 6666 int i; 6667 6668 for_each_intel_encoder(&dev_priv->drm, encoder) { 6669 bool enabled = false, found = false; 6670 enum pipe pipe; 6671 6672 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n", 6673 encoder->base.base.id, 6674 encoder->base.name); 6675 6676 for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state, 6677 new_conn_state, i) { 6678 if (old_conn_state->best_encoder == &encoder->base) 6679 found = true; 6680 6681 if (new_conn_state->best_encoder != &encoder->base) 6682 continue; 6683 found = enabled = true; 6684 6685 I915_STATE_WARN(new_conn_state->crtc != 6686 encoder->base.crtc, 6687 "connector's crtc doesn't match encoder crtc\n"); 6688 } 6689 6690 if (!found) 6691 continue; 6692 6693 I915_STATE_WARN(!!encoder->base.crtc != enabled, 6694 "encoder's enabled state mismatch " 6695 "(expected %i, found %i)\n", 6696 !!encoder->base.crtc, enabled); 6697 6698 if (!encoder->base.crtc) { 6699 bool active; 6700 6701 active = encoder->get_hw_state(encoder, &pipe); 6702 I915_STATE_WARN(active, 6703 "encoder detached but still enabled on pipe %c.\n", 6704 pipe_name(pipe)); 6705 } 6706 } 6707 } 6708 6709 static void 6710 verify_crtc_state(struct intel_crtc *crtc, 6711 struct intel_crtc_state *old_crtc_state, 6712 struct intel_crtc_state *new_crtc_state) 6713 { 6714 struct drm_device *dev = crtc->base.dev; 6715 struct drm_i915_private *dev_priv = to_i915(dev); 6716 struct intel_encoder *encoder; 6717 struct intel_crtc_state *pipe_config = old_crtc_state; 6718 struct drm_atomic_state *state = old_crtc_state->uapi.state; 6719 struct intel_crtc *master_crtc; 6720 6721 __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi); 6722 intel_crtc_free_hw_state(old_crtc_state); 6723 intel_crtc_state_reset(old_crtc_state, crtc); 6724 old_crtc_state->uapi.state = state; 6725 6726 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id, 6727 crtc->base.name); 6728 6729 pipe_config->hw.enable = new_crtc_state->hw.enable; 6730 6731 intel_crtc_get_pipe_config(pipe_config); 6732 6733 /* we keep both pipes enabled on 830 */ 6734 if (IS_I830(dev_priv) && pipe_config->hw.active) 6735 pipe_config->hw.active = new_crtc_state->hw.active; 6736 6737 I915_STATE_WARN(new_crtc_state->hw.active != pipe_config->hw.active, 6738 "crtc active state doesn't match with hw state " 6739 "(expected %i, found %i)\n", 6740 new_crtc_state->hw.active, pipe_config->hw.active); 6741 6742 I915_STATE_WARN(crtc->active != new_crtc_state->hw.active, 6743 "transitional active state does not match atomic hw state " 6744 "(expected %i, found %i)\n", 6745 new_crtc_state->hw.active, crtc->active); 6746 6747 master_crtc = intel_master_crtc(new_crtc_state); 6748 6749 for_each_encoder_on_crtc(dev, &master_crtc->base, encoder) { 6750 enum pipe pipe; 6751 bool active; 6752 6753 active = encoder->get_hw_state(encoder, &pipe); 6754 I915_STATE_WARN(active != new_crtc_state->hw.active, 6755 "[ENCODER:%i] active %i with crtc active %i\n", 6756 encoder->base.base.id, active, 6757 new_crtc_state->hw.active); 6758 6759 I915_STATE_WARN(active && master_crtc->pipe != pipe, 6760 "Encoder connected to wrong pipe %c\n", 6761 pipe_name(pipe)); 6762 6763 if (active) 6764 intel_encoder_get_config(encoder, pipe_config); 6765 } 6766 6767 if (!new_crtc_state->hw.active) 6768 return; 6769 6770 intel_pipe_config_sanity_check(dev_priv, pipe_config); 6771 6772 if (!intel_pipe_config_compare(new_crtc_state, 6773 pipe_config, false)) { 6774 I915_STATE_WARN(1, "pipe state doesn't match!\n"); 6775 intel_dump_pipe_config(pipe_config, NULL, "[hw state]"); 6776 intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]"); 6777 } 6778 } 6779 6780 static void 6781 intel_verify_planes(struct intel_atomic_state *state) 6782 { 6783 struct intel_plane *plane; 6784 const struct intel_plane_state *plane_state; 6785 int i; 6786 6787 for_each_new_intel_plane_in_state(state, plane, 6788 plane_state, i) 6789 assert_plane(plane, plane_state->planar_slave || 6790 plane_state->uapi.visible); 6791 } 6792 6793 static void 6794 verify_single_dpll_state(struct drm_i915_private *dev_priv, 6795 struct intel_shared_dpll *pll, 6796 struct intel_crtc *crtc, 6797 struct intel_crtc_state *new_crtc_state) 6798 { 6799 struct intel_dpll_hw_state dpll_hw_state; 6800 u8 pipe_mask; 6801 bool active; 6802 6803 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); 6804 6805 drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name); 6806 6807 active = intel_dpll_get_hw_state(dev_priv, pll, &dpll_hw_state); 6808 6809 if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) { 6810 I915_STATE_WARN(!pll->on && pll->active_mask, 6811 "pll in active use but not on in sw tracking\n"); 6812 I915_STATE_WARN(pll->on && !pll->active_mask, 6813 "pll is on but not used by any active pipe\n"); 6814 I915_STATE_WARN(pll->on != active, 6815 "pll on state mismatch (expected %i, found %i)\n", 6816 pll->on, active); 6817 } 6818 6819 if (!crtc) { 6820 I915_STATE_WARN(pll->active_mask & ~pll->state.pipe_mask, 6821 "more active pll users than references: 0x%x vs 0x%x\n", 6822 pll->active_mask, pll->state.pipe_mask); 6823 6824 return; 6825 } 6826 6827 pipe_mask = BIT(crtc->pipe); 6828 6829 if (new_crtc_state->hw.active) 6830 I915_STATE_WARN(!(pll->active_mask & pipe_mask), 6831 "pll active mismatch (expected pipe %c in active mask 0x%x)\n", 6832 pipe_name(crtc->pipe), pll->active_mask); 6833 else 6834 I915_STATE_WARN(pll->active_mask & pipe_mask, 6835 "pll active mismatch (didn't expect pipe %c in active mask 0x%x)\n", 6836 pipe_name(crtc->pipe), pll->active_mask); 6837 6838 I915_STATE_WARN(!(pll->state.pipe_mask & pipe_mask), 6839 "pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n", 6840 pipe_mask, pll->state.pipe_mask); 6841 6842 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state, 6843 &dpll_hw_state, 6844 sizeof(dpll_hw_state)), 6845 "pll hw state mismatch\n"); 6846 } 6847 6848 static void 6849 verify_shared_dpll_state(struct intel_crtc *crtc, 6850 struct intel_crtc_state *old_crtc_state, 6851 struct intel_crtc_state *new_crtc_state) 6852 { 6853 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6854 6855 if (new_crtc_state->shared_dpll) 6856 verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state); 6857 6858 if (old_crtc_state->shared_dpll && 6859 old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) { 6860 u8 pipe_mask = BIT(crtc->pipe); 6861 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll; 6862 6863 I915_STATE_WARN(pll->active_mask & pipe_mask, 6864 "pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n", 6865 pipe_name(crtc->pipe), pll->active_mask); 6866 I915_STATE_WARN(pll->state.pipe_mask & pipe_mask, 6867 "pll enabled crtcs mismatch (found %x in enabled mask (0x%x))\n", 6868 pipe_name(crtc->pipe), pll->state.pipe_mask); 6869 } 6870 } 6871 6872 static void 6873 verify_mpllb_state(struct intel_atomic_state *state, 6874 struct intel_crtc_state *new_crtc_state) 6875 { 6876 struct drm_i915_private *i915 = to_i915(state->base.dev); 6877 struct intel_mpllb_state mpllb_hw_state = { 0 }; 6878 struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->mpllb_state; 6879 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 6880 struct intel_encoder *encoder; 6881 6882 if (!IS_DG2(i915)) 6883 return; 6884 6885 if (!new_crtc_state->hw.active) 6886 return; 6887 6888 encoder = intel_get_crtc_new_encoder(state, new_crtc_state); 6889 intel_mpllb_readout_hw_state(encoder, &mpllb_hw_state); 6890 6891 #define MPLLB_CHECK(name) do { \ 6892 if (mpllb_sw_state->name != mpllb_hw_state.name) { \ 6893 pipe_config_mismatch(false, crtc, "MPLLB:" __stringify(name), \ 6894 "(expected 0x%08x, found 0x%08x)", \ 6895 mpllb_sw_state->name, \ 6896 mpllb_hw_state.name); \ 6897 } \ 6898 } while (0) 6899 6900 MPLLB_CHECK(mpllb_cp); 6901 MPLLB_CHECK(mpllb_div); 6902 MPLLB_CHECK(mpllb_div2); 6903 MPLLB_CHECK(mpllb_fracn1); 6904 MPLLB_CHECK(mpllb_fracn2); 6905 MPLLB_CHECK(mpllb_sscen); 6906 MPLLB_CHECK(mpllb_sscstep); 6907 6908 /* 6909 * ref_control is handled by the hardware/firemware and never 6910 * programmed by the software, but the proper values are supplied 6911 * in the bspec for verification purposes. 6912 */ 6913 MPLLB_CHECK(ref_control); 6914 6915 #undef MPLLB_CHECK 6916 } 6917 6918 static void 6919 intel_modeset_verify_crtc(struct intel_crtc *crtc, 6920 struct intel_atomic_state *state, 6921 struct intel_crtc_state *old_crtc_state, 6922 struct intel_crtc_state *new_crtc_state) 6923 { 6924 if (!intel_crtc_needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe) 6925 return; 6926 6927 verify_wm_state(crtc, new_crtc_state); 6928 verify_connector_state(state, crtc); 6929 verify_crtc_state(crtc, old_crtc_state, new_crtc_state); 6930 verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state); 6931 verify_mpllb_state(state, new_crtc_state); 6932 } 6933 6934 static void 6935 verify_disabled_dpll_state(struct drm_i915_private *dev_priv) 6936 { 6937 int i; 6938 6939 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) 6940 verify_single_dpll_state(dev_priv, 6941 &dev_priv->dpll.shared_dplls[i], 6942 NULL, NULL); 6943 } 6944 6945 static void 6946 intel_modeset_verify_disabled(struct drm_i915_private *dev_priv, 6947 struct intel_atomic_state *state) 6948 { 6949 verify_encoder_state(dev_priv, state); 6950 verify_connector_state(state, NULL); 6951 verify_disabled_dpll_state(dev_priv); 6952 } 6953 6954 int intel_modeset_all_pipes(struct intel_atomic_state *state) 6955 { 6956 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6957 struct intel_crtc *crtc; 6958 6959 /* 6960 * Add all pipes to the state, and force 6961 * a modeset on all the active ones. 6962 */ 6963 for_each_intel_crtc(&dev_priv->drm, crtc) { 6964 struct intel_crtc_state *crtc_state; 6965 int ret; 6966 6967 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6968 if (IS_ERR(crtc_state)) 6969 return PTR_ERR(crtc_state); 6970 6971 if (!crtc_state->hw.active || 6972 drm_atomic_crtc_needs_modeset(&crtc_state->uapi)) 6973 continue; 6974 6975 crtc_state->uapi.mode_changed = true; 6976 6977 ret = drm_atomic_add_affected_connectors(&state->base, 6978 &crtc->base); 6979 if (ret) 6980 return ret; 6981 6982 ret = intel_atomic_add_affected_planes(state, crtc); 6983 if (ret) 6984 return ret; 6985 6986 crtc_state->update_planes |= crtc_state->active_planes; 6987 } 6988 6989 return 0; 6990 } 6991 6992 static void 6993 intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state) 6994 { 6995 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 6996 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6997 struct drm_display_mode adjusted_mode = 6998 crtc_state->hw.adjusted_mode; 6999 7000 if (crtc_state->vrr.enable) { 7001 adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax; 7002 adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax; 7003 adjusted_mode.crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state); 7004 crtc->vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state); 7005 } 7006 7007 drm_calc_timestamping_constants(&crtc->base, &adjusted_mode); 7008 7009 crtc->mode_flags = crtc_state->mode_flags; 7010 7011 /* 7012 * The scanline counter increments at the leading edge of hsync. 7013 * 7014 * On most platforms it starts counting from vtotal-1 on the 7015 * first active line. That means the scanline counter value is 7016 * always one less than what we would expect. Ie. just after 7017 * start of vblank, which also occurs at start of hsync (on the 7018 * last active line), the scanline counter will read vblank_start-1. 7019 * 7020 * On gen2 the scanline counter starts counting from 1 instead 7021 * of vtotal-1, so we have to subtract one (or rather add vtotal-1 7022 * to keep the value positive), instead of adding one. 7023 * 7024 * On HSW+ the behaviour of the scanline counter depends on the output 7025 * type. For DP ports it behaves like most other platforms, but on HDMI 7026 * there's an extra 1 line difference. So we need to add two instead of 7027 * one to the value. 7028 * 7029 * On VLV/CHV DSI the scanline counter would appear to increment 7030 * approx. 1/3 of a scanline before start of vblank. Unfortunately 7031 * that means we can't tell whether we're in vblank or not while 7032 * we're on that particular line. We must still set scanline_offset 7033 * to 1 so that the vblank timestamps come out correct when we query 7034 * the scanline counter from within the vblank interrupt handler. 7035 * However if queried just before the start of vblank we'll get an 7036 * answer that's slightly in the future. 7037 */ 7038 if (DISPLAY_VER(dev_priv) == 2) { 7039 int vtotal; 7040 7041 vtotal = adjusted_mode.crtc_vtotal; 7042 if (adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 7043 vtotal /= 2; 7044 7045 crtc->scanline_offset = vtotal - 1; 7046 } else if (HAS_DDI(dev_priv) && 7047 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 7048 crtc->scanline_offset = 2; 7049 } else { 7050 crtc->scanline_offset = 1; 7051 } 7052 } 7053 7054 static void intel_modeset_clear_plls(struct intel_atomic_state *state) 7055 { 7056 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7057 struct intel_crtc_state *new_crtc_state; 7058 struct intel_crtc *crtc; 7059 int i; 7060 7061 if (!dev_priv->dpll_funcs) 7062 return; 7063 7064 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7065 if (!intel_crtc_needs_modeset(new_crtc_state)) 7066 continue; 7067 7068 intel_release_shared_dplls(state, crtc); 7069 } 7070 } 7071 7072 /* 7073 * This implements the workaround described in the "notes" section of the mode 7074 * set sequence documentation. When going from no pipes or single pipe to 7075 * multiple pipes, and planes are enabled after the pipe, we need to wait at 7076 * least 2 vblanks on the first pipe before enabling planes on the second pipe. 7077 */ 7078 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state) 7079 { 7080 struct intel_crtc_state *crtc_state; 7081 struct intel_crtc *crtc; 7082 struct intel_crtc_state *first_crtc_state = NULL; 7083 struct intel_crtc_state *other_crtc_state = NULL; 7084 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; 7085 int i; 7086 7087 /* look at all crtc's that are going to be enabled in during modeset */ 7088 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7089 if (!crtc_state->hw.active || 7090 !intel_crtc_needs_modeset(crtc_state)) 7091 continue; 7092 7093 if (first_crtc_state) { 7094 other_crtc_state = crtc_state; 7095 break; 7096 } else { 7097 first_crtc_state = crtc_state; 7098 first_pipe = crtc->pipe; 7099 } 7100 } 7101 7102 /* No workaround needed? */ 7103 if (!first_crtc_state) 7104 return 0; 7105 7106 /* w/a possibly needed, check how many crtc's are already enabled. */ 7107 for_each_intel_crtc(state->base.dev, crtc) { 7108 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 7109 if (IS_ERR(crtc_state)) 7110 return PTR_ERR(crtc_state); 7111 7112 crtc_state->hsw_workaround_pipe = INVALID_PIPE; 7113 7114 if (!crtc_state->hw.active || 7115 intel_crtc_needs_modeset(crtc_state)) 7116 continue; 7117 7118 /* 2 or more enabled crtcs means no need for w/a */ 7119 if (enabled_pipe != INVALID_PIPE) 7120 return 0; 7121 7122 enabled_pipe = crtc->pipe; 7123 } 7124 7125 if (enabled_pipe != INVALID_PIPE) 7126 first_crtc_state->hsw_workaround_pipe = enabled_pipe; 7127 else if (other_crtc_state) 7128 other_crtc_state->hsw_workaround_pipe = first_pipe; 7129 7130 return 0; 7131 } 7132 7133 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 7134 u8 active_pipes) 7135 { 7136 const struct intel_crtc_state *crtc_state; 7137 struct intel_crtc *crtc; 7138 int i; 7139 7140 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7141 if (crtc_state->hw.active) 7142 active_pipes |= BIT(crtc->pipe); 7143 else 7144 active_pipes &= ~BIT(crtc->pipe); 7145 } 7146 7147 return active_pipes; 7148 } 7149 7150 static int intel_modeset_checks(struct intel_atomic_state *state) 7151 { 7152 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7153 7154 state->modeset = true; 7155 7156 if (IS_HASWELL(dev_priv)) 7157 return hsw_mode_set_planes_workaround(state); 7158 7159 return 0; 7160 } 7161 7162 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state, 7163 struct intel_crtc_state *new_crtc_state) 7164 { 7165 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) 7166 return; 7167 7168 new_crtc_state->uapi.mode_changed = false; 7169 new_crtc_state->update_pipe = true; 7170 } 7171 7172 static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state, 7173 struct intel_crtc_state *new_crtc_state) 7174 { 7175 /* 7176 * If we're not doing the full modeset we want to 7177 * keep the current M/N values as they may be 7178 * sufficiently different to the computed values 7179 * to cause problems. 7180 * 7181 * FIXME: should really copy more fuzzy state here 7182 */ 7183 new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n; 7184 new_crtc_state->dp_m_n = old_crtc_state->dp_m_n; 7185 new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2; 7186 new_crtc_state->has_drrs = old_crtc_state->has_drrs; 7187 } 7188 7189 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state, 7190 struct intel_crtc *crtc, 7191 u8 plane_ids_mask) 7192 { 7193 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7194 struct intel_plane *plane; 7195 7196 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 7197 struct intel_plane_state *plane_state; 7198 7199 if ((plane_ids_mask & BIT(plane->id)) == 0) 7200 continue; 7201 7202 plane_state = intel_atomic_get_plane_state(state, plane); 7203 if (IS_ERR(plane_state)) 7204 return PTR_ERR(plane_state); 7205 } 7206 7207 return 0; 7208 } 7209 7210 int intel_atomic_add_affected_planes(struct intel_atomic_state *state, 7211 struct intel_crtc *crtc) 7212 { 7213 const struct intel_crtc_state *old_crtc_state = 7214 intel_atomic_get_old_crtc_state(state, crtc); 7215 const struct intel_crtc_state *new_crtc_state = 7216 intel_atomic_get_new_crtc_state(state, crtc); 7217 7218 return intel_crtc_add_planes_to_state(state, crtc, 7219 old_crtc_state->enabled_planes | 7220 new_crtc_state->enabled_planes); 7221 } 7222 7223 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv) 7224 { 7225 /* See {hsw,vlv,ivb}_plane_ratio() */ 7226 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) || 7227 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) || 7228 IS_IVYBRIDGE(dev_priv); 7229 } 7230 7231 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state, 7232 struct intel_crtc *crtc, 7233 struct intel_crtc *other) 7234 { 7235 const struct intel_plane_state *plane_state; 7236 struct intel_plane *plane; 7237 u8 plane_ids = 0; 7238 int i; 7239 7240 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 7241 if (plane->pipe == crtc->pipe) 7242 plane_ids |= BIT(plane->id); 7243 } 7244 7245 return intel_crtc_add_planes_to_state(state, other, plane_ids); 7246 } 7247 7248 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state) 7249 { 7250 struct drm_i915_private *i915 = to_i915(state->base.dev); 7251 const struct intel_crtc_state *crtc_state; 7252 struct intel_crtc *crtc; 7253 int i; 7254 7255 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7256 struct intel_crtc *other; 7257 7258 for_each_intel_crtc_in_pipe_mask(&i915->drm, other, 7259 crtc_state->bigjoiner_pipes) { 7260 int ret; 7261 7262 if (crtc == other) 7263 continue; 7264 7265 ret = intel_crtc_add_bigjoiner_planes(state, crtc, other); 7266 if (ret) 7267 return ret; 7268 } 7269 } 7270 7271 return 0; 7272 } 7273 7274 static int intel_atomic_check_planes(struct intel_atomic_state *state) 7275 { 7276 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7277 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7278 struct intel_plane_state *plane_state; 7279 struct intel_plane *plane; 7280 struct intel_crtc *crtc; 7281 int i, ret; 7282 7283 ret = icl_add_linked_planes(state); 7284 if (ret) 7285 return ret; 7286 7287 ret = intel_bigjoiner_add_affected_planes(state); 7288 if (ret) 7289 return ret; 7290 7291 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 7292 ret = intel_plane_atomic_check(state, plane); 7293 if (ret) { 7294 drm_dbg_atomic(&dev_priv->drm, 7295 "[PLANE:%d:%s] atomic driver check failed\n", 7296 plane->base.base.id, plane->base.name); 7297 return ret; 7298 } 7299 } 7300 7301 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7302 new_crtc_state, i) { 7303 u8 old_active_planes, new_active_planes; 7304 7305 ret = icl_check_nv12_planes(new_crtc_state); 7306 if (ret) 7307 return ret; 7308 7309 /* 7310 * On some platforms the number of active planes affects 7311 * the planes' minimum cdclk calculation. Add such planes 7312 * to the state before we compute the minimum cdclk. 7313 */ 7314 if (!active_planes_affects_min_cdclk(dev_priv)) 7315 continue; 7316 7317 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 7318 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 7319 7320 if (hweight8(old_active_planes) == hweight8(new_active_planes)) 7321 continue; 7322 7323 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes); 7324 if (ret) 7325 return ret; 7326 } 7327 7328 return 0; 7329 } 7330 7331 static int intel_atomic_check_crtcs(struct intel_atomic_state *state) 7332 { 7333 struct intel_crtc_state *crtc_state; 7334 struct intel_crtc *crtc; 7335 int i; 7336 7337 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7338 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 7339 int ret; 7340 7341 ret = intel_crtc_atomic_check(state, crtc); 7342 if (ret) { 7343 drm_dbg_atomic(&i915->drm, 7344 "[CRTC:%d:%s] atomic driver check failed\n", 7345 crtc->base.base.id, crtc->base.name); 7346 return ret; 7347 } 7348 } 7349 7350 return 0; 7351 } 7352 7353 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, 7354 u8 transcoders) 7355 { 7356 const struct intel_crtc_state *new_crtc_state; 7357 struct intel_crtc *crtc; 7358 int i; 7359 7360 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7361 if (new_crtc_state->hw.enable && 7362 transcoders & BIT(new_crtc_state->cpu_transcoder) && 7363 intel_crtc_needs_modeset(new_crtc_state)) 7364 return true; 7365 } 7366 7367 return false; 7368 } 7369 7370 static bool intel_pipes_need_modeset(struct intel_atomic_state *state, 7371 u8 pipes) 7372 { 7373 const struct intel_crtc_state *new_crtc_state; 7374 struct intel_crtc *crtc; 7375 int i; 7376 7377 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7378 if (new_crtc_state->hw.enable && 7379 pipes & BIT(crtc->pipe) && 7380 intel_crtc_needs_modeset(new_crtc_state)) 7381 return true; 7382 } 7383 7384 return false; 7385 } 7386 7387 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state, 7388 struct intel_crtc *master_crtc) 7389 { 7390 struct drm_i915_private *i915 = to_i915(state->base.dev); 7391 struct intel_crtc_state *master_crtc_state = 7392 intel_atomic_get_new_crtc_state(state, master_crtc); 7393 struct intel_crtc *slave_crtc; 7394 7395 if (!master_crtc_state->bigjoiner_pipes) 7396 return 0; 7397 7398 /* sanity check */ 7399 if (drm_WARN_ON(&i915->drm, 7400 master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state))) 7401 return -EINVAL; 7402 7403 if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) { 7404 drm_dbg_kms(&i915->drm, 7405 "[CRTC:%d:%s] Cannot act as big joiner master " 7406 "(need 0x%x as pipes, only 0x%x possible)\n", 7407 master_crtc->base.base.id, master_crtc->base.name, 7408 master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915)); 7409 return -EINVAL; 7410 } 7411 7412 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 7413 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 7414 struct intel_crtc_state *slave_crtc_state; 7415 int ret; 7416 7417 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc); 7418 if (IS_ERR(slave_crtc_state)) 7419 return PTR_ERR(slave_crtc_state); 7420 7421 /* master being enabled, slave was already configured? */ 7422 if (slave_crtc_state->uapi.enable) { 7423 drm_dbg_kms(&i915->drm, 7424 "[CRTC:%d:%s] Slave is enabled as normal CRTC, but " 7425 "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n", 7426 slave_crtc->base.base.id, slave_crtc->base.name, 7427 master_crtc->base.base.id, master_crtc->base.name); 7428 return -EINVAL; 7429 } 7430 7431 /* 7432 * The state copy logic assumes the master crtc gets processed 7433 * before the slave crtc during the main compute_config loop. 7434 * This works because the crtcs are created in pipe order, 7435 * and the hardware requires master pipe < slave pipe as well. 7436 * Should that change we need to rethink the logic. 7437 */ 7438 if (WARN_ON(drm_crtc_index(&master_crtc->base) > 7439 drm_crtc_index(&slave_crtc->base))) 7440 return -EINVAL; 7441 7442 drm_dbg_kms(&i915->drm, 7443 "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n", 7444 slave_crtc->base.base.id, slave_crtc->base.name, 7445 master_crtc->base.base.id, master_crtc->base.name); 7446 7447 slave_crtc_state->bigjoiner_pipes = 7448 master_crtc_state->bigjoiner_pipes; 7449 7450 ret = copy_bigjoiner_crtc_state_modeset(state, slave_crtc); 7451 if (ret) 7452 return ret; 7453 } 7454 7455 return 0; 7456 } 7457 7458 static void kill_bigjoiner_slave(struct intel_atomic_state *state, 7459 struct intel_crtc *master_crtc) 7460 { 7461 struct drm_i915_private *i915 = to_i915(state->base.dev); 7462 struct intel_crtc_state *master_crtc_state = 7463 intel_atomic_get_new_crtc_state(state, master_crtc); 7464 struct intel_crtc *slave_crtc; 7465 7466 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 7467 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 7468 struct intel_crtc_state *slave_crtc_state = 7469 intel_atomic_get_new_crtc_state(state, slave_crtc); 7470 7471 slave_crtc_state->bigjoiner_pipes = 0; 7472 7473 intel_crtc_copy_uapi_to_hw_state_modeset(state, slave_crtc); 7474 } 7475 7476 master_crtc_state->bigjoiner_pipes = 0; 7477 } 7478 7479 /** 7480 * DOC: asynchronous flip implementation 7481 * 7482 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC 7483 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL. 7484 * Correspondingly, support is currently added for primary plane only. 7485 * 7486 * Async flip can only change the plane surface address, so anything else 7487 * changing is rejected from the intel_async_flip_check_hw() function. 7488 * Once this check is cleared, flip done interrupt is enabled using 7489 * the intel_crtc_enable_flip_done() function. 7490 * 7491 * As soon as the surface address register is written, flip done interrupt is 7492 * generated and the requested events are sent to the usersapce in the interrupt 7493 * handler itself. The timestamp and sequence sent during the flip done event 7494 * correspond to the last vblank and have no relation to the actual time when 7495 * the flip done event was sent. 7496 */ 7497 static int intel_async_flip_check_uapi(struct intel_atomic_state *state, 7498 struct intel_crtc *crtc) 7499 { 7500 struct drm_i915_private *i915 = to_i915(state->base.dev); 7501 const struct intel_crtc_state *new_crtc_state = 7502 intel_atomic_get_new_crtc_state(state, crtc); 7503 const struct intel_plane_state *old_plane_state; 7504 struct intel_plane_state *new_plane_state; 7505 struct intel_plane *plane; 7506 int i; 7507 7508 if (!new_crtc_state->uapi.async_flip) 7509 return 0; 7510 7511 if (!new_crtc_state->uapi.active) { 7512 drm_dbg_kms(&i915->drm, 7513 "[CRTC:%d:%s] not active\n", 7514 crtc->base.base.id, crtc->base.name); 7515 return -EINVAL; 7516 } 7517 7518 if (intel_crtc_needs_modeset(new_crtc_state)) { 7519 drm_dbg_kms(&i915->drm, 7520 "[CRTC:%d:%s] modeset required\n", 7521 crtc->base.base.id, crtc->base.name); 7522 return -EINVAL; 7523 } 7524 7525 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 7526 new_plane_state, i) { 7527 if (plane->pipe != crtc->pipe) 7528 continue; 7529 7530 /* 7531 * TODO: Async flip is only supported through the page flip IOCTL 7532 * as of now. So support currently added for primary plane only. 7533 * Support for other planes on platforms on which supports 7534 * this(vlv/chv and icl+) should be added when async flip is 7535 * enabled in the atomic IOCTL path. 7536 */ 7537 if (!plane->async_flip) { 7538 drm_dbg_kms(&i915->drm, 7539 "[PLANE:%d:%s] async flip not supported\n", 7540 plane->base.base.id, plane->base.name); 7541 return -EINVAL; 7542 } 7543 7544 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) { 7545 drm_dbg_kms(&i915->drm, 7546 "[PLANE:%d:%s] no old or new framebuffer\n", 7547 plane->base.base.id, plane->base.name); 7548 return -EINVAL; 7549 } 7550 } 7551 7552 return 0; 7553 } 7554 7555 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc) 7556 { 7557 struct drm_i915_private *i915 = to_i915(state->base.dev); 7558 const struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7559 const struct intel_plane_state *new_plane_state, *old_plane_state; 7560 struct intel_plane *plane; 7561 int i; 7562 7563 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 7564 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 7565 7566 if (!new_crtc_state->uapi.async_flip) 7567 return 0; 7568 7569 if (!new_crtc_state->hw.active) { 7570 drm_dbg_kms(&i915->drm, 7571 "[CRTC:%d:%s] not active\n", 7572 crtc->base.base.id, crtc->base.name); 7573 return -EINVAL; 7574 } 7575 7576 if (intel_crtc_needs_modeset(new_crtc_state)) { 7577 drm_dbg_kms(&i915->drm, 7578 "[CRTC:%d:%s] modeset required\n", 7579 crtc->base.base.id, crtc->base.name); 7580 return -EINVAL; 7581 } 7582 7583 if (old_crtc_state->active_planes != new_crtc_state->active_planes) { 7584 drm_dbg_kms(&i915->drm, 7585 "[CRTC:%d:%s] Active planes cannot be in async flip\n", 7586 crtc->base.base.id, crtc->base.name); 7587 return -EINVAL; 7588 } 7589 7590 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 7591 new_plane_state, i) { 7592 if (plane->pipe != crtc->pipe) 7593 continue; 7594 7595 /* 7596 * Only async flip capable planes should be in the state 7597 * if we're really about to ask the hardware to perform 7598 * an async flip. We should never get this far otherwise. 7599 */ 7600 if (drm_WARN_ON(&i915->drm, 7601 new_crtc_state->do_async_flip && !plane->async_flip)) 7602 return -EINVAL; 7603 7604 /* 7605 * Only check async flip capable planes other planes 7606 * may be involved in the initial commit due to 7607 * the wm0/ddb optimization. 7608 * 7609 * TODO maybe should track which planes actually 7610 * were requested to do the async flip... 7611 */ 7612 if (!plane->async_flip) 7613 continue; 7614 7615 /* 7616 * FIXME: This check is kept generic for all platforms. 7617 * Need to verify this for all gen9 platforms to enable 7618 * this selectively if required. 7619 */ 7620 switch (new_plane_state->hw.fb->modifier) { 7621 case I915_FORMAT_MOD_X_TILED: 7622 case I915_FORMAT_MOD_Y_TILED: 7623 case I915_FORMAT_MOD_Yf_TILED: 7624 case I915_FORMAT_MOD_4_TILED: 7625 break; 7626 default: 7627 drm_dbg_kms(&i915->drm, 7628 "[PLANE:%d:%s] Modifier does not support async flips\n", 7629 plane->base.base.id, plane->base.name); 7630 return -EINVAL; 7631 } 7632 7633 if (new_plane_state->hw.fb->format->num_planes > 1) { 7634 drm_dbg_kms(&i915->drm, 7635 "[PLANE:%d:%s] Planar formats do not support async flips\n", 7636 plane->base.base.id, plane->base.name); 7637 return -EINVAL; 7638 } 7639 7640 if (old_plane_state->view.color_plane[0].mapping_stride != 7641 new_plane_state->view.color_plane[0].mapping_stride) { 7642 drm_dbg_kms(&i915->drm, 7643 "[PLANE:%d:%s] Stride cannot be changed in async flip\n", 7644 plane->base.base.id, plane->base.name); 7645 return -EINVAL; 7646 } 7647 7648 if (old_plane_state->hw.fb->modifier != 7649 new_plane_state->hw.fb->modifier) { 7650 drm_dbg_kms(&i915->drm, 7651 "[PLANE:%d:%s] Modifier cannot be changed in async flip\n", 7652 plane->base.base.id, plane->base.name); 7653 return -EINVAL; 7654 } 7655 7656 if (old_plane_state->hw.fb->format != 7657 new_plane_state->hw.fb->format) { 7658 drm_dbg_kms(&i915->drm, 7659 "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n", 7660 plane->base.base.id, plane->base.name); 7661 return -EINVAL; 7662 } 7663 7664 if (old_plane_state->hw.rotation != 7665 new_plane_state->hw.rotation) { 7666 drm_dbg_kms(&i915->drm, 7667 "[PLANE:%d:%s] Rotation cannot be changed in async flip\n", 7668 plane->base.base.id, plane->base.name); 7669 return -EINVAL; 7670 } 7671 7672 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) || 7673 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) { 7674 drm_dbg_kms(&i915->drm, 7675 "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n", 7676 plane->base.base.id, plane->base.name); 7677 return -EINVAL; 7678 } 7679 7680 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) { 7681 drm_dbg_kms(&i915->drm, 7682 "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n", 7683 plane->base.base.id, plane->base.name); 7684 return -EINVAL; 7685 } 7686 7687 if (old_plane_state->hw.pixel_blend_mode != 7688 new_plane_state->hw.pixel_blend_mode) { 7689 drm_dbg_kms(&i915->drm, 7690 "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n", 7691 plane->base.base.id, plane->base.name); 7692 return -EINVAL; 7693 } 7694 7695 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) { 7696 drm_dbg_kms(&i915->drm, 7697 "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n", 7698 plane->base.base.id, plane->base.name); 7699 return -EINVAL; 7700 } 7701 7702 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) { 7703 drm_dbg_kms(&i915->drm, 7704 "[PLANE:%d:%s] Color range cannot be changed in async flip\n", 7705 plane->base.base.id, plane->base.name); 7706 return -EINVAL; 7707 } 7708 7709 /* plane decryption is allow to change only in synchronous flips */ 7710 if (old_plane_state->decrypt != new_plane_state->decrypt) { 7711 drm_dbg_kms(&i915->drm, 7712 "[PLANE:%d:%s] Decryption cannot be changed in async flip\n", 7713 plane->base.base.id, plane->base.name); 7714 return -EINVAL; 7715 } 7716 } 7717 7718 return 0; 7719 } 7720 7721 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state) 7722 { 7723 struct drm_i915_private *i915 = to_i915(state->base.dev); 7724 struct intel_crtc_state *crtc_state; 7725 struct intel_crtc *crtc; 7726 u8 affected_pipes = 0; 7727 u8 modeset_pipes = 0; 7728 int i; 7729 7730 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7731 affected_pipes |= crtc_state->bigjoiner_pipes; 7732 if (intel_crtc_needs_modeset(crtc_state)) 7733 modeset_pipes |= crtc_state->bigjoiner_pipes; 7734 } 7735 7736 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) { 7737 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 7738 if (IS_ERR(crtc_state)) 7739 return PTR_ERR(crtc_state); 7740 } 7741 7742 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) { 7743 int ret; 7744 7745 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 7746 7747 crtc_state->uapi.mode_changed = true; 7748 7749 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); 7750 if (ret) 7751 return ret; 7752 7753 ret = intel_atomic_add_affected_planes(state, crtc); 7754 if (ret) 7755 return ret; 7756 } 7757 7758 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7759 /* Kill old bigjoiner link, we may re-establish afterwards */ 7760 if (intel_crtc_needs_modeset(crtc_state) && 7761 intel_crtc_is_bigjoiner_master(crtc_state)) 7762 kill_bigjoiner_slave(state, crtc); 7763 } 7764 7765 return 0; 7766 } 7767 7768 /** 7769 * intel_atomic_check - validate state object 7770 * @dev: drm device 7771 * @_state: state to validate 7772 */ 7773 static int intel_atomic_check(struct drm_device *dev, 7774 struct drm_atomic_state *_state) 7775 { 7776 struct drm_i915_private *dev_priv = to_i915(dev); 7777 struct intel_atomic_state *state = to_intel_atomic_state(_state); 7778 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7779 struct intel_crtc *crtc; 7780 int ret, i; 7781 bool any_ms = false; 7782 7783 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7784 new_crtc_state, i) { 7785 if (new_crtc_state->inherited != old_crtc_state->inherited) 7786 new_crtc_state->uapi.mode_changed = true; 7787 7788 if (new_crtc_state->uapi.scaling_filter != 7789 old_crtc_state->uapi.scaling_filter) 7790 new_crtc_state->uapi.mode_changed = true; 7791 } 7792 7793 intel_vrr_check_modeset(state); 7794 7795 ret = drm_atomic_helper_check_modeset(dev, &state->base); 7796 if (ret) 7797 goto fail; 7798 7799 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7800 ret = intel_async_flip_check_uapi(state, crtc); 7801 if (ret) 7802 return ret; 7803 } 7804 7805 ret = intel_bigjoiner_add_affected_crtcs(state); 7806 if (ret) 7807 goto fail; 7808 7809 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7810 new_crtc_state, i) { 7811 if (!intel_crtc_needs_modeset(new_crtc_state)) { 7812 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 7813 copy_bigjoiner_crtc_state_nomodeset(state, crtc); 7814 else 7815 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 7816 continue; 7817 } 7818 7819 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) { 7820 drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable); 7821 continue; 7822 } 7823 7824 ret = intel_crtc_prepare_cleared_state(state, crtc); 7825 if (ret) 7826 goto fail; 7827 7828 if (!new_crtc_state->hw.enable) 7829 continue; 7830 7831 ret = intel_modeset_pipe_config(state, new_crtc_state); 7832 if (ret) 7833 goto fail; 7834 7835 ret = intel_atomic_check_bigjoiner(state, crtc); 7836 if (ret) 7837 goto fail; 7838 } 7839 7840 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7841 new_crtc_state, i) { 7842 if (!intel_crtc_needs_modeset(new_crtc_state)) 7843 continue; 7844 7845 ret = intel_modeset_pipe_config_late(new_crtc_state); 7846 if (ret) 7847 goto fail; 7848 7849 intel_crtc_check_fastset(old_crtc_state, new_crtc_state); 7850 } 7851 7852 /** 7853 * Check if fastset is allowed by external dependencies like other 7854 * pipes and transcoders. 7855 * 7856 * Right now it only forces a fullmodeset when the MST master 7857 * transcoder did not changed but the pipe of the master transcoder 7858 * needs a fullmodeset so all slaves also needs to do a fullmodeset or 7859 * in case of port synced crtcs, if one of the synced crtcs 7860 * needs a full modeset, all other synced crtcs should be 7861 * forced a full modeset. 7862 */ 7863 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7864 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state)) 7865 continue; 7866 7867 if (intel_dp_mst_is_slave_trans(new_crtc_state)) { 7868 enum transcoder master = new_crtc_state->mst_master_transcoder; 7869 7870 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) { 7871 new_crtc_state->uapi.mode_changed = true; 7872 new_crtc_state->update_pipe = false; 7873 } 7874 } 7875 7876 if (is_trans_port_sync_mode(new_crtc_state)) { 7877 u8 trans = new_crtc_state->sync_mode_slaves_mask; 7878 7879 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER) 7880 trans |= BIT(new_crtc_state->master_transcoder); 7881 7882 if (intel_cpu_transcoders_need_modeset(state, trans)) { 7883 new_crtc_state->uapi.mode_changed = true; 7884 new_crtc_state->update_pipe = false; 7885 } 7886 } 7887 7888 if (new_crtc_state->bigjoiner_pipes) { 7889 if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) { 7890 new_crtc_state->uapi.mode_changed = true; 7891 new_crtc_state->update_pipe = false; 7892 } 7893 } 7894 } 7895 7896 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7897 new_crtc_state, i) { 7898 if (intel_crtc_needs_modeset(new_crtc_state)) { 7899 any_ms = true; 7900 continue; 7901 } 7902 7903 if (!new_crtc_state->update_pipe) 7904 continue; 7905 7906 intel_crtc_copy_fastset(old_crtc_state, new_crtc_state); 7907 } 7908 7909 if (any_ms && !check_digital_port_conflicts(state)) { 7910 drm_dbg_kms(&dev_priv->drm, 7911 "rejecting conflicting digital port configuration\n"); 7912 ret = -EINVAL; 7913 goto fail; 7914 } 7915 7916 ret = drm_dp_mst_atomic_check(&state->base); 7917 if (ret) 7918 goto fail; 7919 7920 ret = intel_atomic_check_planes(state); 7921 if (ret) 7922 goto fail; 7923 7924 ret = intel_compute_global_watermarks(state); 7925 if (ret) 7926 goto fail; 7927 7928 ret = intel_bw_atomic_check(state); 7929 if (ret) 7930 goto fail; 7931 7932 ret = intel_cdclk_atomic_check(state, &any_ms); 7933 if (ret) 7934 goto fail; 7935 7936 if (intel_any_crtc_needs_modeset(state)) 7937 any_ms = true; 7938 7939 if (any_ms) { 7940 ret = intel_modeset_checks(state); 7941 if (ret) 7942 goto fail; 7943 7944 ret = intel_modeset_calc_cdclk(state); 7945 if (ret) 7946 return ret; 7947 7948 intel_modeset_clear_plls(state); 7949 } 7950 7951 ret = intel_atomic_check_crtcs(state); 7952 if (ret) 7953 goto fail; 7954 7955 ret = intel_fbc_atomic_check(state); 7956 if (ret) 7957 goto fail; 7958 7959 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7960 new_crtc_state, i) { 7961 ret = intel_async_flip_check_hw(state, crtc); 7962 if (ret) 7963 goto fail; 7964 7965 if (!intel_crtc_needs_modeset(new_crtc_state) && 7966 !new_crtc_state->update_pipe) 7967 continue; 7968 7969 intel_dump_pipe_config(new_crtc_state, state, 7970 intel_crtc_needs_modeset(new_crtc_state) ? 7971 "[modeset]" : "[fastset]"); 7972 } 7973 7974 return 0; 7975 7976 fail: 7977 if (ret == -EDEADLK) 7978 return ret; 7979 7980 /* 7981 * FIXME would probably be nice to know which crtc specifically 7982 * caused the failure, in cases where we can pinpoint it. 7983 */ 7984 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7985 new_crtc_state, i) 7986 intel_dump_pipe_config(new_crtc_state, state, "[failed]"); 7987 7988 return ret; 7989 } 7990 7991 static int intel_atomic_prepare_commit(struct intel_atomic_state *state) 7992 { 7993 struct intel_crtc_state *crtc_state; 7994 struct intel_crtc *crtc; 7995 int i, ret; 7996 7997 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base); 7998 if (ret < 0) 7999 return ret; 8000 8001 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 8002 bool mode_changed = intel_crtc_needs_modeset(crtc_state); 8003 8004 if (mode_changed || crtc_state->update_pipe || 8005 crtc_state->uapi.color_mgmt_changed) { 8006 intel_dsb_prepare(crtc_state); 8007 } 8008 } 8009 8010 return 0; 8011 } 8012 8013 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 8014 struct intel_crtc_state *crtc_state) 8015 { 8016 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 8017 8018 if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes) 8019 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 8020 8021 if (crtc_state->has_pch_encoder) { 8022 enum pipe pch_transcoder = 8023 intel_crtc_pch_transcoder(crtc); 8024 8025 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true); 8026 } 8027 } 8028 8029 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, 8030 const struct intel_crtc_state *new_crtc_state) 8031 { 8032 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 8033 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 8034 8035 /* 8036 * Update pipe size and adjust fitter if needed: the reason for this is 8037 * that in compute_mode_changes we check the native mode (not the pfit 8038 * mode) to see if we can flip rather than do a full mode set. In the 8039 * fastboot case, we'll flip, but if we don't update the pipesrc and 8040 * pfit state, we'll end up with a big fb scanned out into the wrong 8041 * sized surface. 8042 */ 8043 intel_set_pipe_src_size(new_crtc_state); 8044 8045 /* on skylake this is done by detaching scalers */ 8046 if (DISPLAY_VER(dev_priv) >= 9) { 8047 if (new_crtc_state->pch_pfit.enabled) 8048 skl_pfit_enable(new_crtc_state); 8049 } else if (HAS_PCH_SPLIT(dev_priv)) { 8050 if (new_crtc_state->pch_pfit.enabled) 8051 ilk_pfit_enable(new_crtc_state); 8052 else if (old_crtc_state->pch_pfit.enabled) 8053 ilk_pfit_disable(old_crtc_state); 8054 } 8055 8056 /* 8057 * The register is supposedly single buffered so perhaps 8058 * not 100% correct to do this here. But SKL+ calculate 8059 * this based on the adjust pixel rate so pfit changes do 8060 * affect it and so it must be updated for fastsets. 8061 * HSW/BDW only really need this here for fastboot, after 8062 * that the value should not change without a full modeset. 8063 */ 8064 if (DISPLAY_VER(dev_priv) >= 9 || 8065 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 8066 hsw_set_linetime_wm(new_crtc_state); 8067 } 8068 8069 static void commit_pipe_pre_planes(struct intel_atomic_state *state, 8070 struct intel_crtc *crtc) 8071 { 8072 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8073 const struct intel_crtc_state *old_crtc_state = 8074 intel_atomic_get_old_crtc_state(state, crtc); 8075 const struct intel_crtc_state *new_crtc_state = 8076 intel_atomic_get_new_crtc_state(state, crtc); 8077 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 8078 8079 /* 8080 * During modesets pipe configuration was programmed as the 8081 * CRTC was enabled. 8082 */ 8083 if (!modeset) { 8084 if (new_crtc_state->uapi.color_mgmt_changed || 8085 new_crtc_state->update_pipe) 8086 intel_color_commit(new_crtc_state); 8087 8088 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 8089 bdw_set_pipemisc(new_crtc_state); 8090 8091 if (new_crtc_state->update_pipe) 8092 intel_pipe_fastset(old_crtc_state, new_crtc_state); 8093 } 8094 8095 intel_psr2_program_trans_man_trk_ctl(new_crtc_state); 8096 8097 intel_atomic_update_watermarks(state, crtc); 8098 } 8099 8100 static void commit_pipe_post_planes(struct intel_atomic_state *state, 8101 struct intel_crtc *crtc) 8102 { 8103 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8104 const struct intel_crtc_state *new_crtc_state = 8105 intel_atomic_get_new_crtc_state(state, crtc); 8106 8107 /* 8108 * Disable the scaler(s) after the plane(s) so that we don't 8109 * get a catastrophic underrun even if the two operations 8110 * end up happening in two different frames. 8111 */ 8112 if (DISPLAY_VER(dev_priv) >= 9 && 8113 !intel_crtc_needs_modeset(new_crtc_state)) 8114 skl_detach_scalers(new_crtc_state); 8115 } 8116 8117 static void intel_enable_crtc(struct intel_atomic_state *state, 8118 struct intel_crtc *crtc) 8119 { 8120 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8121 const struct intel_crtc_state *new_crtc_state = 8122 intel_atomic_get_new_crtc_state(state, crtc); 8123 8124 if (!intel_crtc_needs_modeset(new_crtc_state)) 8125 return; 8126 8127 intel_crtc_update_active_timings(new_crtc_state); 8128 8129 dev_priv->display->crtc_enable(state, crtc); 8130 8131 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 8132 return; 8133 8134 /* vblanks work again, re-enable pipe CRC. */ 8135 intel_crtc_enable_pipe_crc(crtc); 8136 } 8137 8138 static void intel_update_crtc(struct intel_atomic_state *state, 8139 struct intel_crtc *crtc) 8140 { 8141 struct drm_i915_private *i915 = to_i915(state->base.dev); 8142 const struct intel_crtc_state *old_crtc_state = 8143 intel_atomic_get_old_crtc_state(state, crtc); 8144 struct intel_crtc_state *new_crtc_state = 8145 intel_atomic_get_new_crtc_state(state, crtc); 8146 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 8147 8148 if (!modeset) { 8149 if (new_crtc_state->preload_luts && 8150 (new_crtc_state->uapi.color_mgmt_changed || 8151 new_crtc_state->update_pipe)) 8152 intel_color_load_luts(new_crtc_state); 8153 8154 intel_pre_plane_update(state, crtc); 8155 8156 if (new_crtc_state->update_pipe) 8157 intel_encoders_update_pipe(state, crtc); 8158 8159 if (DISPLAY_VER(i915) >= 11 && 8160 new_crtc_state->update_pipe) 8161 icl_set_pipe_chicken(new_crtc_state); 8162 } 8163 8164 intel_fbc_update(state, crtc); 8165 8166 intel_crtc_planes_update_noarm(state, crtc); 8167 8168 /* Perform vblank evasion around commit operation */ 8169 intel_pipe_update_start(new_crtc_state); 8170 8171 commit_pipe_pre_planes(state, crtc); 8172 8173 intel_crtc_planes_update_arm(state, crtc); 8174 8175 commit_pipe_post_planes(state, crtc); 8176 8177 intel_pipe_update_end(new_crtc_state); 8178 8179 /* 8180 * We usually enable FIFO underrun interrupts as part of the 8181 * CRTC enable sequence during modesets. But when we inherit a 8182 * valid pipe configuration from the BIOS we need to take care 8183 * of enabling them on the CRTC's first fastset. 8184 */ 8185 if (new_crtc_state->update_pipe && !modeset && 8186 old_crtc_state->inherited) 8187 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state); 8188 } 8189 8190 static void intel_old_crtc_state_disables(struct intel_atomic_state *state, 8191 struct intel_crtc_state *old_crtc_state, 8192 struct intel_crtc_state *new_crtc_state, 8193 struct intel_crtc *crtc) 8194 { 8195 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8196 8197 /* 8198 * We need to disable pipe CRC before disabling the pipe, 8199 * or we race against vblank off. 8200 */ 8201 intel_crtc_disable_pipe_crc(crtc); 8202 8203 dev_priv->display->crtc_disable(state, crtc); 8204 crtc->active = false; 8205 intel_fbc_disable(crtc); 8206 intel_disable_shared_dpll(old_crtc_state); 8207 8208 /* FIXME unify this for all platforms */ 8209 if (!new_crtc_state->hw.active && 8210 !HAS_GMCH(dev_priv)) 8211 intel_initial_watermarks(state, crtc); 8212 } 8213 8214 static void intel_commit_modeset_disables(struct intel_atomic_state *state) 8215 { 8216 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 8217 struct intel_crtc *crtc; 8218 u32 handled = 0; 8219 int i; 8220 8221 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8222 new_crtc_state, i) { 8223 if (!intel_crtc_needs_modeset(new_crtc_state)) 8224 continue; 8225 8226 if (!old_crtc_state->hw.active) 8227 continue; 8228 8229 intel_pre_plane_update(state, crtc); 8230 intel_crtc_disable_planes(state, crtc); 8231 } 8232 8233 /* Only disable port sync and MST slaves */ 8234 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8235 new_crtc_state, i) { 8236 if (!intel_crtc_needs_modeset(new_crtc_state)) 8237 continue; 8238 8239 if (!old_crtc_state->hw.active) 8240 continue; 8241 8242 /* In case of Transcoder port Sync master slave CRTCs can be 8243 * assigned in any order and we need to make sure that 8244 * slave CRTCs are disabled first and then master CRTC since 8245 * Slave vblanks are masked till Master Vblanks. 8246 */ 8247 if (!is_trans_port_sync_slave(old_crtc_state) && 8248 !intel_dp_mst_is_slave_trans(old_crtc_state) && 8249 !intel_crtc_is_bigjoiner_slave(old_crtc_state)) 8250 continue; 8251 8252 intel_old_crtc_state_disables(state, old_crtc_state, 8253 new_crtc_state, crtc); 8254 handled |= BIT(crtc->pipe); 8255 } 8256 8257 /* Disable everything else left on */ 8258 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8259 new_crtc_state, i) { 8260 if (!intel_crtc_needs_modeset(new_crtc_state) || 8261 (handled & BIT(crtc->pipe))) 8262 continue; 8263 8264 if (!old_crtc_state->hw.active) 8265 continue; 8266 8267 intel_old_crtc_state_disables(state, old_crtc_state, 8268 new_crtc_state, crtc); 8269 } 8270 } 8271 8272 static void intel_commit_modeset_enables(struct intel_atomic_state *state) 8273 { 8274 struct intel_crtc_state *new_crtc_state; 8275 struct intel_crtc *crtc; 8276 int i; 8277 8278 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8279 if (!new_crtc_state->hw.active) 8280 continue; 8281 8282 intel_enable_crtc(state, crtc); 8283 intel_update_crtc(state, crtc); 8284 } 8285 } 8286 8287 static void skl_commit_modeset_enables(struct intel_atomic_state *state) 8288 { 8289 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8290 struct intel_crtc *crtc; 8291 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 8292 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; 8293 u8 update_pipes = 0, modeset_pipes = 0; 8294 int i; 8295 8296 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 8297 enum pipe pipe = crtc->pipe; 8298 8299 if (!new_crtc_state->hw.active) 8300 continue; 8301 8302 /* ignore allocations for crtc's that have been turned off. */ 8303 if (!intel_crtc_needs_modeset(new_crtc_state)) { 8304 entries[pipe] = old_crtc_state->wm.skl.ddb; 8305 update_pipes |= BIT(pipe); 8306 } else { 8307 modeset_pipes |= BIT(pipe); 8308 } 8309 } 8310 8311 /* 8312 * Whenever the number of active pipes changes, we need to make sure we 8313 * update the pipes in the right order so that their ddb allocations 8314 * never overlap with each other between CRTC updates. Otherwise we'll 8315 * cause pipe underruns and other bad stuff. 8316 * 8317 * So first lets enable all pipes that do not need a fullmodeset as 8318 * those don't have any external dependency. 8319 */ 8320 while (update_pipes) { 8321 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8322 new_crtc_state, i) { 8323 enum pipe pipe = crtc->pipe; 8324 8325 if ((update_pipes & BIT(pipe)) == 0) 8326 continue; 8327 8328 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 8329 entries, I915_MAX_PIPES, pipe)) 8330 continue; 8331 8332 entries[pipe] = new_crtc_state->wm.skl.ddb; 8333 update_pipes &= ~BIT(pipe); 8334 8335 intel_update_crtc(state, crtc); 8336 8337 /* 8338 * If this is an already active pipe, it's DDB changed, 8339 * and this isn't the last pipe that needs updating 8340 * then we need to wait for a vblank to pass for the 8341 * new ddb allocation to take effect. 8342 */ 8343 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, 8344 &old_crtc_state->wm.skl.ddb) && 8345 (update_pipes | modeset_pipes)) 8346 intel_crtc_wait_for_next_vblank(crtc); 8347 } 8348 } 8349 8350 update_pipes = modeset_pipes; 8351 8352 /* 8353 * Enable all pipes that needs a modeset and do not depends on other 8354 * pipes 8355 */ 8356 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8357 enum pipe pipe = crtc->pipe; 8358 8359 if ((modeset_pipes & BIT(pipe)) == 0) 8360 continue; 8361 8362 if (intel_dp_mst_is_slave_trans(new_crtc_state) || 8363 is_trans_port_sync_master(new_crtc_state) || 8364 intel_crtc_is_bigjoiner_master(new_crtc_state)) 8365 continue; 8366 8367 modeset_pipes &= ~BIT(pipe); 8368 8369 intel_enable_crtc(state, crtc); 8370 } 8371 8372 /* 8373 * Then we enable all remaining pipes that depend on other 8374 * pipes: MST slaves and port sync masters, big joiner master 8375 */ 8376 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8377 enum pipe pipe = crtc->pipe; 8378 8379 if ((modeset_pipes & BIT(pipe)) == 0) 8380 continue; 8381 8382 modeset_pipes &= ~BIT(pipe); 8383 8384 intel_enable_crtc(state, crtc); 8385 } 8386 8387 /* 8388 * Finally we do the plane updates/etc. for all pipes that got enabled. 8389 */ 8390 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8391 enum pipe pipe = crtc->pipe; 8392 8393 if ((update_pipes & BIT(pipe)) == 0) 8394 continue; 8395 8396 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 8397 entries, I915_MAX_PIPES, pipe)); 8398 8399 entries[pipe] = new_crtc_state->wm.skl.ddb; 8400 update_pipes &= ~BIT(pipe); 8401 8402 intel_update_crtc(state, crtc); 8403 } 8404 8405 drm_WARN_ON(&dev_priv->drm, modeset_pipes); 8406 drm_WARN_ON(&dev_priv->drm, update_pipes); 8407 } 8408 8409 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) 8410 { 8411 struct intel_atomic_state *state, *next; 8412 struct llist_node *freed; 8413 8414 freed = llist_del_all(&dev_priv->atomic_helper.free_list); 8415 llist_for_each_entry_safe(state, next, freed, freed) 8416 drm_atomic_state_put(&state->base); 8417 } 8418 8419 static void intel_atomic_helper_free_state_worker(struct work_struct *work) 8420 { 8421 struct drm_i915_private *dev_priv = 8422 container_of(work, typeof(*dev_priv), atomic_helper.free_work); 8423 8424 intel_atomic_helper_free_state(dev_priv); 8425 } 8426 8427 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) 8428 { 8429 struct wait_queue_entry wait_fence, wait_reset; 8430 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); 8431 8432 init_wait_entry(&wait_fence, 0); 8433 init_wait_entry(&wait_reset, 0); 8434 for (;;) { 8435 prepare_to_wait(&intel_state->commit_ready.wait, 8436 &wait_fence, TASK_UNINTERRUPTIBLE); 8437 prepare_to_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 8438 I915_RESET_MODESET), 8439 &wait_reset, TASK_UNINTERRUPTIBLE); 8440 8441 8442 if (i915_sw_fence_done(&intel_state->commit_ready) || 8443 test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags)) 8444 break; 8445 8446 schedule(); 8447 } 8448 finish_wait(&intel_state->commit_ready.wait, &wait_fence); 8449 finish_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 8450 I915_RESET_MODESET), 8451 &wait_reset); 8452 } 8453 8454 static void intel_cleanup_dsbs(struct intel_atomic_state *state) 8455 { 8456 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 8457 struct intel_crtc *crtc; 8458 int i; 8459 8460 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8461 new_crtc_state, i) 8462 intel_dsb_cleanup(old_crtc_state); 8463 } 8464 8465 static void intel_atomic_cleanup_work(struct work_struct *work) 8466 { 8467 struct intel_atomic_state *state = 8468 container_of(work, struct intel_atomic_state, base.commit_work); 8469 struct drm_i915_private *i915 = to_i915(state->base.dev); 8470 8471 intel_cleanup_dsbs(state); 8472 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base); 8473 drm_atomic_helper_commit_cleanup_done(&state->base); 8474 drm_atomic_state_put(&state->base); 8475 8476 intel_atomic_helper_free_state(i915); 8477 } 8478 8479 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state) 8480 { 8481 struct drm_i915_private *i915 = to_i915(state->base.dev); 8482 struct intel_plane *plane; 8483 struct intel_plane_state *plane_state; 8484 int i; 8485 8486 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 8487 struct drm_framebuffer *fb = plane_state->hw.fb; 8488 int cc_plane; 8489 int ret; 8490 8491 if (!fb) 8492 continue; 8493 8494 cc_plane = intel_fb_rc_ccs_cc_plane(fb); 8495 if (cc_plane < 0) 8496 continue; 8497 8498 /* 8499 * The layout of the fast clear color value expected by HW 8500 * (the DRM ABI requiring this value to be located in fb at offset 0 of plane#2): 8501 * - 4 x 4 bytes per-channel value 8502 * (in surface type specific float/int format provided by the fb user) 8503 * - 8 bytes native color value used by the display 8504 * (converted/written by GPU during a fast clear operation using the 8505 * above per-channel values) 8506 * 8507 * The commit's FB prepare hook already ensured that FB obj is pinned and the 8508 * caller made sure that the object is synced wrt. the related color clear value 8509 * GPU write on it. 8510 */ 8511 ret = i915_gem_object_read_from_page(intel_fb_obj(fb), 8512 fb->offsets[cc_plane] + 16, 8513 &plane_state->ccval, 8514 sizeof(plane_state->ccval)); 8515 /* The above could only fail if the FB obj has an unexpected backing store type. */ 8516 drm_WARN_ON(&i915->drm, ret); 8517 } 8518 } 8519 8520 static void intel_atomic_commit_tail(struct intel_atomic_state *state) 8521 { 8522 struct drm_device *dev = state->base.dev; 8523 struct drm_i915_private *dev_priv = to_i915(dev); 8524 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 8525 struct intel_crtc *crtc; 8526 u64 put_domains[I915_MAX_PIPES] = {}; 8527 intel_wakeref_t wakeref = 0; 8528 int i; 8529 8530 intel_atomic_commit_fence_wait(state); 8531 8532 drm_atomic_helper_wait_for_dependencies(&state->base); 8533 8534 if (state->modeset) 8535 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); 8536 8537 intel_atomic_prepare_plane_clear_colors(state); 8538 8539 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8540 new_crtc_state, i) { 8541 if (intel_crtc_needs_modeset(new_crtc_state) || 8542 new_crtc_state->update_pipe) { 8543 8544 put_domains[crtc->pipe] = 8545 modeset_get_crtc_power_domains(new_crtc_state); 8546 } 8547 } 8548 8549 intel_commit_modeset_disables(state); 8550 8551 /* FIXME: Eventually get rid of our crtc->config pointer */ 8552 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 8553 crtc->config = new_crtc_state; 8554 8555 if (state->modeset) { 8556 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base); 8557 8558 intel_set_cdclk_pre_plane_update(state); 8559 8560 intel_modeset_verify_disabled(dev_priv, state); 8561 } 8562 8563 intel_sagv_pre_plane_update(state); 8564 8565 /* Complete the events for pipes that have now been disabled */ 8566 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8567 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 8568 8569 /* Complete events for now disable pipes here. */ 8570 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) { 8571 spin_lock_irq(&dev->event_lock); 8572 drm_crtc_send_vblank_event(&crtc->base, 8573 new_crtc_state->uapi.event); 8574 spin_unlock_irq(&dev->event_lock); 8575 8576 new_crtc_state->uapi.event = NULL; 8577 } 8578 } 8579 8580 intel_encoders_update_prepare(state); 8581 8582 intel_dbuf_pre_plane_update(state); 8583 8584 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8585 if (new_crtc_state->do_async_flip) 8586 intel_crtc_enable_flip_done(state, crtc); 8587 } 8588 8589 /* Now enable the clocks, plane, pipe, and connectors that we set up. */ 8590 dev_priv->display->commit_modeset_enables(state); 8591 8592 intel_encoders_update_complete(state); 8593 8594 if (state->modeset) 8595 intel_set_cdclk_post_plane_update(state); 8596 8597 intel_wait_for_vblank_workers(state); 8598 8599 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here 8600 * already, but still need the state for the delayed optimization. To 8601 * fix this: 8602 * - wrap the optimization/post_plane_update stuff into a per-crtc work. 8603 * - schedule that vblank worker _before_ calling hw_done 8604 * - at the start of commit_tail, cancel it _synchrously 8605 * - switch over to the vblank wait helper in the core after that since 8606 * we don't need out special handling any more. 8607 */ 8608 drm_atomic_helper_wait_for_flip_done(dev, &state->base); 8609 8610 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8611 if (new_crtc_state->do_async_flip) 8612 intel_crtc_disable_flip_done(state, crtc); 8613 } 8614 8615 /* 8616 * Now that the vblank has passed, we can go ahead and program the 8617 * optimal watermarks on platforms that need two-step watermark 8618 * programming. 8619 * 8620 * TODO: Move this (and other cleanup) to an async worker eventually. 8621 */ 8622 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8623 new_crtc_state, i) { 8624 /* 8625 * Gen2 reports pipe underruns whenever all planes are disabled. 8626 * So re-enable underrun reporting after some planes get enabled. 8627 * 8628 * We do this before .optimize_watermarks() so that we have a 8629 * chance of catching underruns with the intermediate watermarks 8630 * vs. the new plane configuration. 8631 */ 8632 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state)) 8633 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 8634 8635 intel_optimize_watermarks(state, crtc); 8636 } 8637 8638 intel_dbuf_post_plane_update(state); 8639 intel_psr_post_plane_update(state); 8640 8641 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 8642 intel_post_plane_update(state, crtc); 8643 8644 modeset_put_crtc_power_domains(crtc, put_domains[crtc->pipe]); 8645 8646 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state); 8647 8648 /* 8649 * DSB cleanup is done in cleanup_work aligning with framebuffer 8650 * cleanup. So copy and reset the dsb structure to sync with 8651 * commit_done and later do dsb cleanup in cleanup_work. 8652 */ 8653 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb); 8654 } 8655 8656 /* Underruns don't always raise interrupts, so check manually */ 8657 intel_check_cpu_fifo_underruns(dev_priv); 8658 intel_check_pch_fifo_underruns(dev_priv); 8659 8660 if (state->modeset) 8661 intel_verify_planes(state); 8662 8663 intel_sagv_post_plane_update(state); 8664 8665 drm_atomic_helper_commit_hw_done(&state->base); 8666 8667 if (state->modeset) { 8668 /* As one of the primary mmio accessors, KMS has a high 8669 * likelihood of triggering bugs in unclaimed access. After we 8670 * finish modesetting, see if an error has been flagged, and if 8671 * so enable debugging for the next modeset - and hope we catch 8672 * the culprit. 8673 */ 8674 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); 8675 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref); 8676 } 8677 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 8678 8679 /* 8680 * Defer the cleanup of the old state to a separate worker to not 8681 * impede the current task (userspace for blocking modesets) that 8682 * are executed inline. For out-of-line asynchronous modesets/flips, 8683 * deferring to a new worker seems overkill, but we would place a 8684 * schedule point (cond_resched()) here anyway to keep latencies 8685 * down. 8686 */ 8687 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work); 8688 queue_work(system_highpri_wq, &state->base.commit_work); 8689 } 8690 8691 static void intel_atomic_commit_work(struct work_struct *work) 8692 { 8693 struct intel_atomic_state *state = 8694 container_of(work, struct intel_atomic_state, base.commit_work); 8695 8696 intel_atomic_commit_tail(state); 8697 } 8698 8699 static int 8700 intel_atomic_commit_ready(struct i915_sw_fence *fence, 8701 enum i915_sw_fence_notify notify) 8702 { 8703 struct intel_atomic_state *state = 8704 container_of(fence, struct intel_atomic_state, commit_ready); 8705 8706 switch (notify) { 8707 case FENCE_COMPLETE: 8708 /* we do blocking waits in the worker, nothing to do here */ 8709 break; 8710 case FENCE_FREE: 8711 { 8712 struct intel_atomic_helper *helper = 8713 &to_i915(state->base.dev)->atomic_helper; 8714 8715 if (llist_add(&state->freed, &helper->free_list)) 8716 schedule_work(&helper->free_work); 8717 break; 8718 } 8719 } 8720 8721 return NOTIFY_DONE; 8722 } 8723 8724 static void intel_atomic_track_fbs(struct intel_atomic_state *state) 8725 { 8726 struct intel_plane_state *old_plane_state, *new_plane_state; 8727 struct intel_plane *plane; 8728 int i; 8729 8730 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 8731 new_plane_state, i) 8732 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), 8733 to_intel_frontbuffer(new_plane_state->hw.fb), 8734 plane->frontbuffer_bit); 8735 } 8736 8737 static int intel_atomic_commit(struct drm_device *dev, 8738 struct drm_atomic_state *_state, 8739 bool nonblock) 8740 { 8741 struct intel_atomic_state *state = to_intel_atomic_state(_state); 8742 struct drm_i915_private *dev_priv = to_i915(dev); 8743 int ret = 0; 8744 8745 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 8746 8747 drm_atomic_state_get(&state->base); 8748 i915_sw_fence_init(&state->commit_ready, 8749 intel_atomic_commit_ready); 8750 8751 /* 8752 * The intel_legacy_cursor_update() fast path takes care 8753 * of avoiding the vblank waits for simple cursor 8754 * movement and flips. For cursor on/off and size changes, 8755 * we want to perform the vblank waits so that watermark 8756 * updates happen during the correct frames. Gen9+ have 8757 * double buffered watermarks and so shouldn't need this. 8758 * 8759 * Unset state->legacy_cursor_update before the call to 8760 * drm_atomic_helper_setup_commit() because otherwise 8761 * drm_atomic_helper_wait_for_flip_done() is a noop and 8762 * we get FIFO underruns because we didn't wait 8763 * for vblank. 8764 * 8765 * FIXME doing watermarks and fb cleanup from a vblank worker 8766 * (assuming we had any) would solve these problems. 8767 */ 8768 if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) { 8769 struct intel_crtc_state *new_crtc_state; 8770 struct intel_crtc *crtc; 8771 int i; 8772 8773 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 8774 if (new_crtc_state->wm.need_postvbl_update || 8775 new_crtc_state->update_wm_post) 8776 state->base.legacy_cursor_update = false; 8777 } 8778 8779 ret = intel_atomic_prepare_commit(state); 8780 if (ret) { 8781 drm_dbg_atomic(&dev_priv->drm, 8782 "Preparing state failed with %i\n", ret); 8783 i915_sw_fence_commit(&state->commit_ready); 8784 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 8785 return ret; 8786 } 8787 8788 ret = drm_atomic_helper_setup_commit(&state->base, nonblock); 8789 if (!ret) 8790 ret = drm_atomic_helper_swap_state(&state->base, true); 8791 if (!ret) 8792 intel_atomic_swap_global_state(state); 8793 8794 if (ret) { 8795 struct intel_crtc_state *new_crtc_state; 8796 struct intel_crtc *crtc; 8797 int i; 8798 8799 i915_sw_fence_commit(&state->commit_ready); 8800 8801 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 8802 intel_dsb_cleanup(new_crtc_state); 8803 8804 drm_atomic_helper_cleanup_planes(dev, &state->base); 8805 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 8806 return ret; 8807 } 8808 intel_shared_dpll_swap_state(state); 8809 intel_atomic_track_fbs(state); 8810 8811 drm_atomic_state_get(&state->base); 8812 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work); 8813 8814 i915_sw_fence_commit(&state->commit_ready); 8815 if (nonblock && state->modeset) { 8816 queue_work(dev_priv->modeset_wq, &state->base.commit_work); 8817 } else if (nonblock) { 8818 queue_work(dev_priv->flip_wq, &state->base.commit_work); 8819 } else { 8820 if (state->modeset) 8821 flush_workqueue(dev_priv->modeset_wq); 8822 intel_atomic_commit_tail(state); 8823 } 8824 8825 return 0; 8826 } 8827 8828 /** 8829 * intel_plane_destroy - destroy a plane 8830 * @plane: plane to destroy 8831 * 8832 * Common destruction function for all types of planes (primary, cursor, 8833 * sprite). 8834 */ 8835 void intel_plane_destroy(struct drm_plane *plane) 8836 { 8837 drm_plane_cleanup(plane); 8838 kfree(to_intel_plane(plane)); 8839 } 8840 8841 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv) 8842 { 8843 struct intel_plane *plane; 8844 8845 for_each_intel_plane(&dev_priv->drm, plane) { 8846 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, 8847 plane->pipe); 8848 8849 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base); 8850 } 8851 } 8852 8853 8854 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 8855 struct drm_file *file) 8856 { 8857 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; 8858 struct drm_crtc *drmmode_crtc; 8859 struct intel_crtc *crtc; 8860 8861 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id); 8862 if (!drmmode_crtc) 8863 return -ENOENT; 8864 8865 crtc = to_intel_crtc(drmmode_crtc); 8866 pipe_from_crtc_id->pipe = crtc->pipe; 8867 8868 return 0; 8869 } 8870 8871 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder) 8872 { 8873 struct drm_device *dev = encoder->base.dev; 8874 struct intel_encoder *source_encoder; 8875 u32 possible_clones = 0; 8876 8877 for_each_intel_encoder(dev, source_encoder) { 8878 if (encoders_cloneable(encoder, source_encoder)) 8879 possible_clones |= drm_encoder_mask(&source_encoder->base); 8880 } 8881 8882 return possible_clones; 8883 } 8884 8885 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder) 8886 { 8887 struct drm_device *dev = encoder->base.dev; 8888 struct intel_crtc *crtc; 8889 u32 possible_crtcs = 0; 8890 8891 for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask) 8892 possible_crtcs |= drm_crtc_mask(&crtc->base); 8893 8894 return possible_crtcs; 8895 } 8896 8897 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv) 8898 { 8899 if (!IS_MOBILE(dev_priv)) 8900 return false; 8901 8902 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0) 8903 return false; 8904 8905 if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE)) 8906 return false; 8907 8908 return true; 8909 } 8910 8911 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv) 8912 { 8913 if (DISPLAY_VER(dev_priv) >= 9) 8914 return false; 8915 8916 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) 8917 return false; 8918 8919 if (HAS_PCH_LPT_H(dev_priv) && 8920 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) 8921 return false; 8922 8923 /* DDI E can't be used if DDI A requires 4 lanes */ 8924 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 8925 return false; 8926 8927 if (!dev_priv->vbt.int_crt_support) 8928 return false; 8929 8930 return true; 8931 } 8932 8933 static void intel_setup_outputs(struct drm_i915_private *dev_priv) 8934 { 8935 struct intel_encoder *encoder; 8936 bool dpd_is_edp = false; 8937 8938 intel_pps_unlock_regs_wa(dev_priv); 8939 8940 if (!HAS_DISPLAY(dev_priv)) 8941 return; 8942 8943 if (IS_DG2(dev_priv)) { 8944 intel_ddi_init(dev_priv, PORT_A); 8945 intel_ddi_init(dev_priv, PORT_B); 8946 intel_ddi_init(dev_priv, PORT_C); 8947 intel_ddi_init(dev_priv, PORT_D_XELPD); 8948 intel_ddi_init(dev_priv, PORT_TC1); 8949 } else if (IS_ALDERLAKE_P(dev_priv)) { 8950 intel_ddi_init(dev_priv, PORT_A); 8951 intel_ddi_init(dev_priv, PORT_B); 8952 intel_ddi_init(dev_priv, PORT_TC1); 8953 intel_ddi_init(dev_priv, PORT_TC2); 8954 intel_ddi_init(dev_priv, PORT_TC3); 8955 intel_ddi_init(dev_priv, PORT_TC4); 8956 icl_dsi_init(dev_priv); 8957 } else if (IS_ALDERLAKE_S(dev_priv)) { 8958 intel_ddi_init(dev_priv, PORT_A); 8959 intel_ddi_init(dev_priv, PORT_TC1); 8960 intel_ddi_init(dev_priv, PORT_TC2); 8961 intel_ddi_init(dev_priv, PORT_TC3); 8962 intel_ddi_init(dev_priv, PORT_TC4); 8963 } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) { 8964 intel_ddi_init(dev_priv, PORT_A); 8965 intel_ddi_init(dev_priv, PORT_B); 8966 intel_ddi_init(dev_priv, PORT_TC1); 8967 intel_ddi_init(dev_priv, PORT_TC2); 8968 } else if (DISPLAY_VER(dev_priv) >= 12) { 8969 intel_ddi_init(dev_priv, PORT_A); 8970 intel_ddi_init(dev_priv, PORT_B); 8971 intel_ddi_init(dev_priv, PORT_TC1); 8972 intel_ddi_init(dev_priv, PORT_TC2); 8973 intel_ddi_init(dev_priv, PORT_TC3); 8974 intel_ddi_init(dev_priv, PORT_TC4); 8975 intel_ddi_init(dev_priv, PORT_TC5); 8976 intel_ddi_init(dev_priv, PORT_TC6); 8977 icl_dsi_init(dev_priv); 8978 } else if (IS_JSL_EHL(dev_priv)) { 8979 intel_ddi_init(dev_priv, PORT_A); 8980 intel_ddi_init(dev_priv, PORT_B); 8981 intel_ddi_init(dev_priv, PORT_C); 8982 intel_ddi_init(dev_priv, PORT_D); 8983 icl_dsi_init(dev_priv); 8984 } else if (DISPLAY_VER(dev_priv) == 11) { 8985 intel_ddi_init(dev_priv, PORT_A); 8986 intel_ddi_init(dev_priv, PORT_B); 8987 intel_ddi_init(dev_priv, PORT_C); 8988 intel_ddi_init(dev_priv, PORT_D); 8989 intel_ddi_init(dev_priv, PORT_E); 8990 intel_ddi_init(dev_priv, PORT_F); 8991 icl_dsi_init(dev_priv); 8992 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 8993 intel_ddi_init(dev_priv, PORT_A); 8994 intel_ddi_init(dev_priv, PORT_B); 8995 intel_ddi_init(dev_priv, PORT_C); 8996 vlv_dsi_init(dev_priv); 8997 } else if (DISPLAY_VER(dev_priv) >= 9) { 8998 intel_ddi_init(dev_priv, PORT_A); 8999 intel_ddi_init(dev_priv, PORT_B); 9000 intel_ddi_init(dev_priv, PORT_C); 9001 intel_ddi_init(dev_priv, PORT_D); 9002 intel_ddi_init(dev_priv, PORT_E); 9003 } else if (HAS_DDI(dev_priv)) { 9004 u32 found; 9005 9006 if (intel_ddi_crt_present(dev_priv)) 9007 intel_crt_init(dev_priv); 9008 9009 /* Haswell uses DDI functions to detect digital outputs. */ 9010 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 9011 if (found) 9012 intel_ddi_init(dev_priv, PORT_A); 9013 9014 found = intel_de_read(dev_priv, SFUSE_STRAP); 9015 if (found & SFUSE_STRAP_DDIB_DETECTED) 9016 intel_ddi_init(dev_priv, PORT_B); 9017 if (found & SFUSE_STRAP_DDIC_DETECTED) 9018 intel_ddi_init(dev_priv, PORT_C); 9019 if (found & SFUSE_STRAP_DDID_DETECTED) 9020 intel_ddi_init(dev_priv, PORT_D); 9021 if (found & SFUSE_STRAP_DDIF_DETECTED) 9022 intel_ddi_init(dev_priv, PORT_F); 9023 } else if (HAS_PCH_SPLIT(dev_priv)) { 9024 int found; 9025 9026 /* 9027 * intel_edp_init_connector() depends on this completing first, 9028 * to prevent the registration of both eDP and LVDS and the 9029 * incorrect sharing of the PPS. 9030 */ 9031 intel_lvds_init(dev_priv); 9032 intel_crt_init(dev_priv); 9033 9034 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D); 9035 9036 if (ilk_has_edp_a(dev_priv)) 9037 g4x_dp_init(dev_priv, DP_A, PORT_A); 9038 9039 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) { 9040 /* PCH SDVOB multiplex with HDMIB */ 9041 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); 9042 if (!found) 9043 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); 9044 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED)) 9045 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B); 9046 } 9047 9048 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED) 9049 g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); 9050 9051 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED) 9052 g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D); 9053 9054 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED) 9055 g4x_dp_init(dev_priv, PCH_DP_C, PORT_C); 9056 9057 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED) 9058 g4x_dp_init(dev_priv, PCH_DP_D, PORT_D); 9059 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 9060 bool has_edp, has_port; 9061 9062 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support) 9063 intel_crt_init(dev_priv); 9064 9065 /* 9066 * The DP_DETECTED bit is the latched state of the DDC 9067 * SDA pin at boot. However since eDP doesn't require DDC 9068 * (no way to plug in a DP->HDMI dongle) the DDC pins for 9069 * eDP ports may have been muxed to an alternate function. 9070 * Thus we can't rely on the DP_DETECTED bit alone to detect 9071 * eDP ports. Consult the VBT as well as DP_DETECTED to 9072 * detect eDP ports. 9073 * 9074 * Sadly the straps seem to be missing sometimes even for HDMI 9075 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap 9076 * and VBT for the presence of the port. Additionally we can't 9077 * trust the port type the VBT declares as we've seen at least 9078 * HDMI ports that the VBT claim are DP or eDP. 9079 */ 9080 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B); 9081 has_port = intel_bios_is_port_present(dev_priv, PORT_B); 9082 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port) 9083 has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B); 9084 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) 9085 g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); 9086 9087 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C); 9088 has_port = intel_bios_is_port_present(dev_priv, PORT_C); 9089 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port) 9090 has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C); 9091 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) 9092 g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); 9093 9094 if (IS_CHERRYVIEW(dev_priv)) { 9095 /* 9096 * eDP not supported on port D, 9097 * so no need to worry about it 9098 */ 9099 has_port = intel_bios_is_port_present(dev_priv, PORT_D); 9100 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port) 9101 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D); 9102 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port) 9103 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D); 9104 } 9105 9106 vlv_dsi_init(dev_priv); 9107 } else if (IS_PINEVIEW(dev_priv)) { 9108 intel_lvds_init(dev_priv); 9109 intel_crt_init(dev_priv); 9110 } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) { 9111 bool found = false; 9112 9113 if (IS_MOBILE(dev_priv)) 9114 intel_lvds_init(dev_priv); 9115 9116 intel_crt_init(dev_priv); 9117 9118 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 9119 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n"); 9120 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); 9121 if (!found && IS_G4X(dev_priv)) { 9122 drm_dbg_kms(&dev_priv->drm, 9123 "probing HDMI on SDVOB\n"); 9124 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); 9125 } 9126 9127 if (!found && IS_G4X(dev_priv)) 9128 g4x_dp_init(dev_priv, DP_B, PORT_B); 9129 } 9130 9131 /* Before G4X SDVOC doesn't have its own detect register */ 9132 9133 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 9134 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n"); 9135 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); 9136 } 9137 9138 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) { 9139 9140 if (IS_G4X(dev_priv)) { 9141 drm_dbg_kms(&dev_priv->drm, 9142 "probing HDMI on SDVOC\n"); 9143 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); 9144 } 9145 if (IS_G4X(dev_priv)) 9146 g4x_dp_init(dev_priv, DP_C, PORT_C); 9147 } 9148 9149 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED)) 9150 g4x_dp_init(dev_priv, DP_D, PORT_D); 9151 9152 if (SUPPORTS_TV(dev_priv)) 9153 intel_tv_init(dev_priv); 9154 } else if (DISPLAY_VER(dev_priv) == 2) { 9155 if (IS_I85X(dev_priv)) 9156 intel_lvds_init(dev_priv); 9157 9158 intel_crt_init(dev_priv); 9159 intel_dvo_init(dev_priv); 9160 } 9161 9162 for_each_intel_encoder(&dev_priv->drm, encoder) { 9163 encoder->base.possible_crtcs = 9164 intel_encoder_possible_crtcs(encoder); 9165 encoder->base.possible_clones = 9166 intel_encoder_possible_clones(encoder); 9167 } 9168 9169 intel_init_pch_refclk(dev_priv); 9170 9171 drm_helper_move_panel_connectors_to_head(&dev_priv->drm); 9172 } 9173 9174 static enum drm_mode_status 9175 intel_mode_valid(struct drm_device *dev, 9176 const struct drm_display_mode *mode) 9177 { 9178 struct drm_i915_private *dev_priv = to_i915(dev); 9179 int hdisplay_max, htotal_max; 9180 int vdisplay_max, vtotal_max; 9181 9182 /* 9183 * Can't reject DBLSCAN here because Xorg ddxen can add piles 9184 * of DBLSCAN modes to the output's mode list when they detect 9185 * the scaling mode property on the connector. And they don't 9186 * ask the kernel to validate those modes in any way until 9187 * modeset time at which point the client gets a protocol error. 9188 * So in order to not upset those clients we silently ignore the 9189 * DBLSCAN flag on such connectors. For other connectors we will 9190 * reject modes with the DBLSCAN flag in encoder->compute_config(). 9191 * And we always reject DBLSCAN modes in connector->mode_valid() 9192 * as we never want such modes on the connector's mode list. 9193 */ 9194 9195 if (mode->vscan > 1) 9196 return MODE_NO_VSCAN; 9197 9198 if (mode->flags & DRM_MODE_FLAG_HSKEW) 9199 return MODE_H_ILLEGAL; 9200 9201 if (mode->flags & (DRM_MODE_FLAG_CSYNC | 9202 DRM_MODE_FLAG_NCSYNC | 9203 DRM_MODE_FLAG_PCSYNC)) 9204 return MODE_HSYNC; 9205 9206 if (mode->flags & (DRM_MODE_FLAG_BCAST | 9207 DRM_MODE_FLAG_PIXMUX | 9208 DRM_MODE_FLAG_CLKDIV2)) 9209 return MODE_BAD; 9210 9211 /* Transcoder timing limits */ 9212 if (DISPLAY_VER(dev_priv) >= 11) { 9213 hdisplay_max = 16384; 9214 vdisplay_max = 8192; 9215 htotal_max = 16384; 9216 vtotal_max = 8192; 9217 } else if (DISPLAY_VER(dev_priv) >= 9 || 9218 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 9219 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ 9220 vdisplay_max = 4096; 9221 htotal_max = 8192; 9222 vtotal_max = 8192; 9223 } else if (DISPLAY_VER(dev_priv) >= 3) { 9224 hdisplay_max = 4096; 9225 vdisplay_max = 4096; 9226 htotal_max = 8192; 9227 vtotal_max = 8192; 9228 } else { 9229 hdisplay_max = 2048; 9230 vdisplay_max = 2048; 9231 htotal_max = 4096; 9232 vtotal_max = 4096; 9233 } 9234 9235 if (mode->hdisplay > hdisplay_max || 9236 mode->hsync_start > htotal_max || 9237 mode->hsync_end > htotal_max || 9238 mode->htotal > htotal_max) 9239 return MODE_H_ILLEGAL; 9240 9241 if (mode->vdisplay > vdisplay_max || 9242 mode->vsync_start > vtotal_max || 9243 mode->vsync_end > vtotal_max || 9244 mode->vtotal > vtotal_max) 9245 return MODE_V_ILLEGAL; 9246 9247 if (DISPLAY_VER(dev_priv) >= 5) { 9248 if (mode->hdisplay < 64 || 9249 mode->htotal - mode->hdisplay < 32) 9250 return MODE_H_ILLEGAL; 9251 9252 if (mode->vtotal - mode->vdisplay < 5) 9253 return MODE_V_ILLEGAL; 9254 } else { 9255 if (mode->htotal - mode->hdisplay < 32) 9256 return MODE_H_ILLEGAL; 9257 9258 if (mode->vtotal - mode->vdisplay < 3) 9259 return MODE_V_ILLEGAL; 9260 } 9261 9262 /* 9263 * Cantiga+ cannot handle modes with a hsync front porch of 0. 9264 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. 9265 */ 9266 if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) && 9267 mode->hsync_start == mode->hdisplay) 9268 return MODE_H_ILLEGAL; 9269 9270 return MODE_OK; 9271 } 9272 9273 enum drm_mode_status 9274 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 9275 const struct drm_display_mode *mode, 9276 bool bigjoiner) 9277 { 9278 int plane_width_max, plane_height_max; 9279 9280 /* 9281 * intel_mode_valid() should be 9282 * sufficient on older platforms. 9283 */ 9284 if (DISPLAY_VER(dev_priv) < 9) 9285 return MODE_OK; 9286 9287 /* 9288 * Most people will probably want a fullscreen 9289 * plane so let's not advertize modes that are 9290 * too big for that. 9291 */ 9292 if (DISPLAY_VER(dev_priv) >= 11) { 9293 plane_width_max = 5120 << bigjoiner; 9294 plane_height_max = 4320; 9295 } else { 9296 plane_width_max = 5120; 9297 plane_height_max = 4096; 9298 } 9299 9300 if (mode->hdisplay > plane_width_max) 9301 return MODE_H_ILLEGAL; 9302 9303 if (mode->vdisplay > plane_height_max) 9304 return MODE_V_ILLEGAL; 9305 9306 return MODE_OK; 9307 } 9308 9309 static const struct drm_mode_config_funcs intel_mode_funcs = { 9310 .fb_create = intel_user_framebuffer_create, 9311 .get_format_info = intel_fb_get_format_info, 9312 .output_poll_changed = intel_fbdev_output_poll_changed, 9313 .mode_valid = intel_mode_valid, 9314 .atomic_check = intel_atomic_check, 9315 .atomic_commit = intel_atomic_commit, 9316 .atomic_state_alloc = intel_atomic_state_alloc, 9317 .atomic_state_clear = intel_atomic_state_clear, 9318 .atomic_state_free = intel_atomic_state_free, 9319 }; 9320 9321 static const struct drm_i915_display_funcs skl_display_funcs = { 9322 .get_pipe_config = hsw_get_pipe_config, 9323 .crtc_enable = hsw_crtc_enable, 9324 .crtc_disable = hsw_crtc_disable, 9325 .commit_modeset_enables = skl_commit_modeset_enables, 9326 .get_initial_plane_config = skl_get_initial_plane_config, 9327 }; 9328 9329 static const struct drm_i915_display_funcs ddi_display_funcs = { 9330 .get_pipe_config = hsw_get_pipe_config, 9331 .crtc_enable = hsw_crtc_enable, 9332 .crtc_disable = hsw_crtc_disable, 9333 .commit_modeset_enables = intel_commit_modeset_enables, 9334 .get_initial_plane_config = i9xx_get_initial_plane_config, 9335 }; 9336 9337 static const struct drm_i915_display_funcs pch_split_display_funcs = { 9338 .get_pipe_config = ilk_get_pipe_config, 9339 .crtc_enable = ilk_crtc_enable, 9340 .crtc_disable = ilk_crtc_disable, 9341 .commit_modeset_enables = intel_commit_modeset_enables, 9342 .get_initial_plane_config = i9xx_get_initial_plane_config, 9343 }; 9344 9345 static const struct drm_i915_display_funcs vlv_display_funcs = { 9346 .get_pipe_config = i9xx_get_pipe_config, 9347 .crtc_enable = valleyview_crtc_enable, 9348 .crtc_disable = i9xx_crtc_disable, 9349 .commit_modeset_enables = intel_commit_modeset_enables, 9350 .get_initial_plane_config = i9xx_get_initial_plane_config, 9351 }; 9352 9353 static const struct drm_i915_display_funcs i9xx_display_funcs = { 9354 .get_pipe_config = i9xx_get_pipe_config, 9355 .crtc_enable = i9xx_crtc_enable, 9356 .crtc_disable = i9xx_crtc_disable, 9357 .commit_modeset_enables = intel_commit_modeset_enables, 9358 .get_initial_plane_config = i9xx_get_initial_plane_config, 9359 }; 9360 9361 /** 9362 * intel_init_display_hooks - initialize the display modesetting hooks 9363 * @dev_priv: device private 9364 */ 9365 void intel_init_display_hooks(struct drm_i915_private *dev_priv) 9366 { 9367 if (!HAS_DISPLAY(dev_priv)) 9368 return; 9369 9370 intel_init_cdclk_hooks(dev_priv); 9371 intel_audio_hooks_init(dev_priv); 9372 9373 intel_dpll_init_clock_hook(dev_priv); 9374 9375 if (DISPLAY_VER(dev_priv) >= 9) { 9376 dev_priv->display = &skl_display_funcs; 9377 } else if (HAS_DDI(dev_priv)) { 9378 dev_priv->display = &ddi_display_funcs; 9379 } else if (HAS_PCH_SPLIT(dev_priv)) { 9380 dev_priv->display = &pch_split_display_funcs; 9381 } else if (IS_CHERRYVIEW(dev_priv) || 9382 IS_VALLEYVIEW(dev_priv)) { 9383 dev_priv->display = &vlv_display_funcs; 9384 } else { 9385 dev_priv->display = &i9xx_display_funcs; 9386 } 9387 9388 intel_fdi_init_hook(dev_priv); 9389 } 9390 9391 void intel_modeset_init_hw(struct drm_i915_private *i915) 9392 { 9393 struct intel_cdclk_state *cdclk_state; 9394 9395 if (!HAS_DISPLAY(i915)) 9396 return; 9397 9398 cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state); 9399 9400 intel_update_cdclk(i915); 9401 intel_cdclk_dump_config(i915, &i915->cdclk.hw, "Current CDCLK"); 9402 cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw; 9403 } 9404 9405 static int sanitize_watermarks_add_affected(struct drm_atomic_state *state) 9406 { 9407 struct drm_plane *plane; 9408 struct intel_crtc *crtc; 9409 9410 for_each_intel_crtc(state->dev, crtc) { 9411 struct intel_crtc_state *crtc_state; 9412 9413 crtc_state = intel_atomic_get_crtc_state(state, crtc); 9414 if (IS_ERR(crtc_state)) 9415 return PTR_ERR(crtc_state); 9416 9417 if (crtc_state->hw.active) { 9418 /* 9419 * Preserve the inherited flag to avoid 9420 * taking the full modeset path. 9421 */ 9422 crtc_state->inherited = true; 9423 } 9424 } 9425 9426 drm_for_each_plane(plane, state->dev) { 9427 struct drm_plane_state *plane_state; 9428 9429 plane_state = drm_atomic_get_plane_state(state, plane); 9430 if (IS_ERR(plane_state)) 9431 return PTR_ERR(plane_state); 9432 } 9433 9434 return 0; 9435 } 9436 9437 /* 9438 * Calculate what we think the watermarks should be for the state we've read 9439 * out of the hardware and then immediately program those watermarks so that 9440 * we ensure the hardware settings match our internal state. 9441 * 9442 * We can calculate what we think WM's should be by creating a duplicate of the 9443 * current state (which was constructed during hardware readout) and running it 9444 * through the atomic check code to calculate new watermark values in the 9445 * state object. 9446 */ 9447 static void sanitize_watermarks(struct drm_i915_private *dev_priv) 9448 { 9449 struct drm_atomic_state *state; 9450 struct intel_atomic_state *intel_state; 9451 struct intel_crtc *crtc; 9452 struct intel_crtc_state *crtc_state; 9453 struct drm_modeset_acquire_ctx ctx; 9454 int ret; 9455 int i; 9456 9457 /* Only supported on platforms that use atomic watermark design */ 9458 if (!dev_priv->wm_disp->optimize_watermarks) 9459 return; 9460 9461 state = drm_atomic_state_alloc(&dev_priv->drm); 9462 if (drm_WARN_ON(&dev_priv->drm, !state)) 9463 return; 9464 9465 intel_state = to_intel_atomic_state(state); 9466 9467 drm_modeset_acquire_init(&ctx, 0); 9468 9469 retry: 9470 state->acquire_ctx = &ctx; 9471 9472 /* 9473 * Hardware readout is the only time we don't want to calculate 9474 * intermediate watermarks (since we don't trust the current 9475 * watermarks). 9476 */ 9477 if (!HAS_GMCH(dev_priv)) 9478 intel_state->skip_intermediate_wm = true; 9479 9480 ret = sanitize_watermarks_add_affected(state); 9481 if (ret) 9482 goto fail; 9483 9484 ret = intel_atomic_check(&dev_priv->drm, state); 9485 if (ret) 9486 goto fail; 9487 9488 /* Write calculated watermark values back */ 9489 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) { 9490 crtc_state->wm.need_postvbl_update = true; 9491 intel_optimize_watermarks(intel_state, crtc); 9492 9493 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm; 9494 } 9495 9496 fail: 9497 if (ret == -EDEADLK) { 9498 drm_atomic_state_clear(state); 9499 drm_modeset_backoff(&ctx); 9500 goto retry; 9501 } 9502 9503 /* 9504 * If we fail here, it means that the hardware appears to be 9505 * programmed in a way that shouldn't be possible, given our 9506 * understanding of watermark requirements. This might mean a 9507 * mistake in the hardware readout code or a mistake in the 9508 * watermark calculations for a given platform. Raise a WARN 9509 * so that this is noticeable. 9510 * 9511 * If this actually happens, we'll have to just leave the 9512 * BIOS-programmed watermarks untouched and hope for the best. 9513 */ 9514 drm_WARN(&dev_priv->drm, ret, 9515 "Could not determine valid watermarks for inherited state\n"); 9516 9517 drm_atomic_state_put(state); 9518 9519 drm_modeset_drop_locks(&ctx); 9520 drm_modeset_acquire_fini(&ctx); 9521 } 9522 9523 static int intel_initial_commit(struct drm_device *dev) 9524 { 9525 struct drm_atomic_state *state = NULL; 9526 struct drm_modeset_acquire_ctx ctx; 9527 struct intel_crtc *crtc; 9528 int ret = 0; 9529 9530 state = drm_atomic_state_alloc(dev); 9531 if (!state) 9532 return -ENOMEM; 9533 9534 drm_modeset_acquire_init(&ctx, 0); 9535 9536 retry: 9537 state->acquire_ctx = &ctx; 9538 9539 for_each_intel_crtc(dev, crtc) { 9540 struct intel_crtc_state *crtc_state = 9541 intel_atomic_get_crtc_state(state, crtc); 9542 9543 if (IS_ERR(crtc_state)) { 9544 ret = PTR_ERR(crtc_state); 9545 goto out; 9546 } 9547 9548 if (crtc_state->hw.active) { 9549 struct intel_encoder *encoder; 9550 9551 /* 9552 * We've not yet detected sink capabilities 9553 * (audio,infoframes,etc.) and thus we don't want to 9554 * force a full state recomputation yet. We want that to 9555 * happen only for the first real commit from userspace. 9556 * So preserve the inherited flag for the time being. 9557 */ 9558 crtc_state->inherited = true; 9559 9560 ret = drm_atomic_add_affected_planes(state, &crtc->base); 9561 if (ret) 9562 goto out; 9563 9564 /* 9565 * FIXME hack to force a LUT update to avoid the 9566 * plane update forcing the pipe gamma on without 9567 * having a proper LUT loaded. Remove once we 9568 * have readout for pipe gamma enable. 9569 */ 9570 crtc_state->uapi.color_mgmt_changed = true; 9571 9572 for_each_intel_encoder_mask(dev, encoder, 9573 crtc_state->uapi.encoder_mask) { 9574 if (encoder->initial_fastset_check && 9575 !encoder->initial_fastset_check(encoder, crtc_state)) { 9576 ret = drm_atomic_add_affected_connectors(state, 9577 &crtc->base); 9578 if (ret) 9579 goto out; 9580 } 9581 } 9582 } 9583 } 9584 9585 ret = drm_atomic_commit(state); 9586 9587 out: 9588 if (ret == -EDEADLK) { 9589 drm_atomic_state_clear(state); 9590 drm_modeset_backoff(&ctx); 9591 goto retry; 9592 } 9593 9594 drm_atomic_state_put(state); 9595 9596 drm_modeset_drop_locks(&ctx); 9597 drm_modeset_acquire_fini(&ctx); 9598 9599 return ret; 9600 } 9601 9602 static void intel_mode_config_init(struct drm_i915_private *i915) 9603 { 9604 struct drm_mode_config *mode_config = &i915->drm.mode_config; 9605 9606 drm_mode_config_init(&i915->drm); 9607 INIT_LIST_HEAD(&i915->global_obj_list); 9608 9609 mode_config->min_width = 0; 9610 mode_config->min_height = 0; 9611 9612 mode_config->preferred_depth = 24; 9613 mode_config->prefer_shadow = 1; 9614 9615 mode_config->funcs = &intel_mode_funcs; 9616 9617 mode_config->async_page_flip = HAS_ASYNC_FLIPS(i915); 9618 9619 /* 9620 * Maximum framebuffer dimensions, chosen to match 9621 * the maximum render engine surface size on gen4+. 9622 */ 9623 if (DISPLAY_VER(i915) >= 7) { 9624 mode_config->max_width = 16384; 9625 mode_config->max_height = 16384; 9626 } else if (DISPLAY_VER(i915) >= 4) { 9627 mode_config->max_width = 8192; 9628 mode_config->max_height = 8192; 9629 } else if (DISPLAY_VER(i915) == 3) { 9630 mode_config->max_width = 4096; 9631 mode_config->max_height = 4096; 9632 } else { 9633 mode_config->max_width = 2048; 9634 mode_config->max_height = 2048; 9635 } 9636 9637 if (IS_I845G(i915) || IS_I865G(i915)) { 9638 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512; 9639 mode_config->cursor_height = 1023; 9640 } else if (IS_I830(i915) || IS_I85X(i915) || 9641 IS_I915G(i915) || IS_I915GM(i915)) { 9642 mode_config->cursor_width = 64; 9643 mode_config->cursor_height = 64; 9644 } else { 9645 mode_config->cursor_width = 256; 9646 mode_config->cursor_height = 256; 9647 } 9648 } 9649 9650 static void intel_mode_config_cleanup(struct drm_i915_private *i915) 9651 { 9652 intel_atomic_global_obj_cleanup(i915); 9653 drm_mode_config_cleanup(&i915->drm); 9654 } 9655 9656 /* part #1: call before irq install */ 9657 int intel_modeset_init_noirq(struct drm_i915_private *i915) 9658 { 9659 int ret; 9660 9661 if (i915_inject_probe_failure(i915)) 9662 return -ENODEV; 9663 9664 if (HAS_DISPLAY(i915)) { 9665 ret = drm_vblank_init(&i915->drm, 9666 INTEL_NUM_PIPES(i915)); 9667 if (ret) 9668 return ret; 9669 } 9670 9671 intel_bios_init(i915); 9672 9673 ret = intel_vga_register(i915); 9674 if (ret) 9675 goto cleanup_bios; 9676 9677 /* FIXME: completely on the wrong abstraction layer */ 9678 intel_power_domains_init_hw(i915, false); 9679 9680 if (!HAS_DISPLAY(i915)) 9681 return 0; 9682 9683 intel_dmc_ucode_init(i915); 9684 9685 i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0); 9686 i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI | 9687 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE); 9688 9689 i915->window2_delay = 0; /* No DSB so no window2 delay */ 9690 9691 intel_mode_config_init(i915); 9692 9693 ret = intel_cdclk_init(i915); 9694 if (ret) 9695 goto cleanup_vga_client_pw_domain_dmc; 9696 9697 ret = intel_dbuf_init(i915); 9698 if (ret) 9699 goto cleanup_vga_client_pw_domain_dmc; 9700 9701 ret = intel_bw_init(i915); 9702 if (ret) 9703 goto cleanup_vga_client_pw_domain_dmc; 9704 9705 init_llist_head(&i915->atomic_helper.free_list); 9706 INIT_WORK(&i915->atomic_helper.free_work, 9707 intel_atomic_helper_free_state_worker); 9708 9709 intel_init_quirks(i915); 9710 9711 intel_fbc_init(i915); 9712 9713 return 0; 9714 9715 cleanup_vga_client_pw_domain_dmc: 9716 intel_dmc_ucode_fini(i915); 9717 intel_power_domains_driver_remove(i915); 9718 intel_vga_unregister(i915); 9719 cleanup_bios: 9720 intel_bios_driver_remove(i915); 9721 9722 return ret; 9723 } 9724 9725 /* part #2: call after irq install, but before gem init */ 9726 int intel_modeset_init_nogem(struct drm_i915_private *i915) 9727 { 9728 struct drm_device *dev = &i915->drm; 9729 enum pipe pipe; 9730 struct intel_crtc *crtc; 9731 int ret; 9732 9733 if (!HAS_DISPLAY(i915)) 9734 return 0; 9735 9736 intel_init_pm(i915); 9737 9738 intel_panel_sanitize_ssc(i915); 9739 9740 intel_pps_setup(i915); 9741 9742 intel_gmbus_setup(i915); 9743 9744 drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n", 9745 INTEL_NUM_PIPES(i915), 9746 INTEL_NUM_PIPES(i915) > 1 ? "s" : ""); 9747 9748 for_each_pipe(i915, pipe) { 9749 ret = intel_crtc_init(i915, pipe); 9750 if (ret) { 9751 intel_mode_config_cleanup(i915); 9752 return ret; 9753 } 9754 } 9755 9756 intel_plane_possible_crtcs_init(i915); 9757 intel_shared_dpll_init(dev); 9758 intel_fdi_pll_freq_update(i915); 9759 9760 intel_update_czclk(i915); 9761 intel_modeset_init_hw(i915); 9762 intel_dpll_update_ref_clks(i915); 9763 9764 intel_hdcp_component_init(i915); 9765 9766 if (i915->max_cdclk_freq == 0) 9767 intel_update_max_cdclk(i915); 9768 9769 /* 9770 * If the platform has HTI, we need to find out whether it has reserved 9771 * any display resources before we create our display outputs. 9772 */ 9773 if (INTEL_INFO(i915)->display.has_hti) 9774 i915->hti_state = intel_de_read(i915, HDPORT_STATE); 9775 9776 /* Just disable it once at startup */ 9777 intel_vga_disable(i915); 9778 intel_setup_outputs(i915); 9779 9780 drm_modeset_lock_all(dev); 9781 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx); 9782 intel_acpi_assign_connector_fwnodes(i915); 9783 drm_modeset_unlock_all(dev); 9784 9785 for_each_intel_crtc(dev, crtc) { 9786 if (!to_intel_crtc_state(crtc->base.state)->uapi.active) 9787 continue; 9788 intel_crtc_initial_plane_config(crtc); 9789 } 9790 9791 /* 9792 * Make sure hardware watermarks really match the state we read out. 9793 * Note that we need to do this after reconstructing the BIOS fb's 9794 * since the watermark calculation done here will use pstate->fb. 9795 */ 9796 if (!HAS_GMCH(i915)) 9797 sanitize_watermarks(i915); 9798 9799 return 0; 9800 } 9801 9802 /* part #3: call after gem init */ 9803 int intel_modeset_init(struct drm_i915_private *i915) 9804 { 9805 int ret; 9806 9807 if (!HAS_DISPLAY(i915)) 9808 return 0; 9809 9810 /* 9811 * Force all active planes to recompute their states. So that on 9812 * mode_setcrtc after probe, all the intel_plane_state variables 9813 * are already calculated and there is no assert_plane warnings 9814 * during bootup. 9815 */ 9816 ret = intel_initial_commit(&i915->drm); 9817 if (ret) 9818 drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret); 9819 9820 intel_overlay_setup(i915); 9821 9822 ret = intel_fbdev_init(&i915->drm); 9823 if (ret) 9824 return ret; 9825 9826 /* Only enable hotplug handling once the fbdev is fully set up. */ 9827 intel_hpd_init(i915); 9828 intel_hpd_poll_disable(i915); 9829 9830 intel_init_ipc(i915); 9831 9832 return 0; 9833 } 9834 9835 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 9836 { 9837 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 9838 /* 640x480@60Hz, ~25175 kHz */ 9839 struct dpll clock = { 9840 .m1 = 18, 9841 .m2 = 7, 9842 .p1 = 13, 9843 .p2 = 4, 9844 .n = 2, 9845 }; 9846 u32 dpll, fp; 9847 int i; 9848 9849 drm_WARN_ON(&dev_priv->drm, 9850 i9xx_calc_dpll_params(48000, &clock) != 25154); 9851 9852 drm_dbg_kms(&dev_priv->drm, 9853 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n", 9854 pipe_name(pipe), clock.vco, clock.dot); 9855 9856 fp = i9xx_dpll_compute_fp(&clock); 9857 dpll = DPLL_DVO_2X_MODE | 9858 DPLL_VGA_MODE_DIS | 9859 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | 9860 PLL_P2_DIVIDE_BY_4 | 9861 PLL_REF_INPUT_DREFCLK | 9862 DPLL_VCO_ENABLE; 9863 9864 intel_de_write(dev_priv, FP0(pipe), fp); 9865 intel_de_write(dev_priv, FP1(pipe), fp); 9866 9867 intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16)); 9868 intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16)); 9869 intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16)); 9870 intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16)); 9871 intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16)); 9872 intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16)); 9873 intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1)); 9874 9875 /* 9876 * Apparently we need to have VGA mode enabled prior to changing 9877 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 9878 * dividers, even though the register value does change. 9879 */ 9880 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); 9881 intel_de_write(dev_priv, DPLL(pipe), dpll); 9882 9883 /* Wait for the clocks to stabilize. */ 9884 intel_de_posting_read(dev_priv, DPLL(pipe)); 9885 udelay(150); 9886 9887 /* The pixel multiplier can only be updated once the 9888 * DPLL is enabled and the clocks are stable. 9889 * 9890 * So write it again. 9891 */ 9892 intel_de_write(dev_priv, DPLL(pipe), dpll); 9893 9894 /* We do this three times for luck */ 9895 for (i = 0; i < 3 ; i++) { 9896 intel_de_write(dev_priv, DPLL(pipe), dpll); 9897 intel_de_posting_read(dev_priv, DPLL(pipe)); 9898 udelay(150); /* wait for warmup */ 9899 } 9900 9901 intel_de_write(dev_priv, PIPECONF(pipe), PIPECONF_ENABLE); 9902 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 9903 9904 intel_wait_for_pipe_scanline_moving(crtc); 9905 } 9906 9907 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 9908 { 9909 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 9910 9911 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n", 9912 pipe_name(pipe)); 9913 9914 drm_WARN_ON(&dev_priv->drm, 9915 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE); 9916 drm_WARN_ON(&dev_priv->drm, 9917 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE); 9918 drm_WARN_ON(&dev_priv->drm, 9919 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE); 9920 drm_WARN_ON(&dev_priv->drm, 9921 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK); 9922 drm_WARN_ON(&dev_priv->drm, 9923 intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK); 9924 9925 intel_de_write(dev_priv, PIPECONF(pipe), 0); 9926 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 9927 9928 intel_wait_for_pipe_scanline_stopped(crtc); 9929 9930 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); 9931 intel_de_posting_read(dev_priv, DPLL(pipe)); 9932 } 9933 9934 static void 9935 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv) 9936 { 9937 struct intel_crtc *crtc; 9938 9939 if (DISPLAY_VER(dev_priv) >= 4) 9940 return; 9941 9942 for_each_intel_crtc(&dev_priv->drm, crtc) { 9943 struct intel_plane *plane = 9944 to_intel_plane(crtc->base.primary); 9945 struct intel_crtc *plane_crtc; 9946 enum pipe pipe; 9947 9948 if (!plane->get_hw_state(plane, &pipe)) 9949 continue; 9950 9951 if (pipe == crtc->pipe) 9952 continue; 9953 9954 drm_dbg_kms(&dev_priv->drm, 9955 "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n", 9956 plane->base.base.id, plane->base.name); 9957 9958 plane_crtc = intel_crtc_for_pipe(dev_priv, pipe); 9959 intel_plane_disable_noatomic(plane_crtc, plane); 9960 } 9961 } 9962 9963 static bool intel_crtc_has_encoders(struct intel_crtc *crtc) 9964 { 9965 struct drm_device *dev = crtc->base.dev; 9966 struct intel_encoder *encoder; 9967 9968 for_each_encoder_on_crtc(dev, &crtc->base, encoder) 9969 return true; 9970 9971 return false; 9972 } 9973 9974 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) 9975 { 9976 struct drm_device *dev = encoder->base.dev; 9977 struct intel_connector *connector; 9978 9979 for_each_connector_on_encoder(dev, &encoder->base, connector) 9980 return connector; 9981 9982 return NULL; 9983 } 9984 9985 static void intel_sanitize_crtc(struct intel_crtc *crtc, 9986 struct drm_modeset_acquire_ctx *ctx) 9987 { 9988 struct drm_device *dev = crtc->base.dev; 9989 struct drm_i915_private *dev_priv = to_i915(dev); 9990 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); 9991 9992 if (crtc_state->hw.active) { 9993 struct intel_plane *plane; 9994 9995 /* Disable everything but the primary plane */ 9996 for_each_intel_plane_on_crtc(dev, crtc, plane) { 9997 const struct intel_plane_state *plane_state = 9998 to_intel_plane_state(plane->base.state); 9999 10000 if (plane_state->uapi.visible && 10001 plane->base.type != DRM_PLANE_TYPE_PRIMARY) 10002 intel_plane_disable_noatomic(crtc, plane); 10003 } 10004 10005 /* Disable any background color/etc. set by the BIOS */ 10006 intel_color_commit(crtc_state); 10007 } 10008 10009 /* Adjust the state of the output pipe according to whether we 10010 * have active connectors/encoders. */ 10011 if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) && 10012 !intel_crtc_is_bigjoiner_slave(crtc_state)) 10013 intel_crtc_disable_noatomic(crtc, ctx); 10014 10015 if (crtc_state->hw.active || HAS_GMCH(dev_priv)) { 10016 /* 10017 * We start out with underrun reporting disabled to avoid races. 10018 * For correct bookkeeping mark this on active crtcs. 10019 * 10020 * Also on gmch platforms we dont have any hardware bits to 10021 * disable the underrun reporting. Which means we need to start 10022 * out with underrun reporting disabled also on inactive pipes, 10023 * since otherwise we'll complain about the garbage we read when 10024 * e.g. coming up after runtime pm. 10025 * 10026 * No protection against concurrent access is required - at 10027 * worst a fifo underrun happens which also sets this to false. 10028 */ 10029 crtc->cpu_fifo_underrun_disabled = true; 10030 /* 10031 * We track the PCH trancoder underrun reporting state 10032 * within the crtc. With crtc for pipe A housing the underrun 10033 * reporting state for PCH transcoder A, crtc for pipe B housing 10034 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, 10035 * and marking underrun reporting as disabled for the non-existing 10036 * PCH transcoders B and C would prevent enabling the south 10037 * error interrupt (see cpt_can_enable_serr_int()). 10038 */ 10039 if (intel_has_pch_trancoder(dev_priv, crtc->pipe)) 10040 crtc->pch_fifo_underrun_disabled = true; 10041 } 10042 } 10043 10044 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state) 10045 { 10046 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 10047 10048 /* 10049 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram 10050 * the hardware when a high res displays plugged in. DPLL P 10051 * divider is zero, and the pipe timings are bonkers. We'll 10052 * try to disable everything in that case. 10053 * 10054 * FIXME would be nice to be able to sanitize this state 10055 * without several WARNs, but for now let's take the easy 10056 * road. 10057 */ 10058 return IS_SANDYBRIDGE(dev_priv) && 10059 crtc_state->hw.active && 10060 crtc_state->shared_dpll && 10061 crtc_state->port_clock == 0; 10062 } 10063 10064 static void intel_sanitize_encoder(struct intel_encoder *encoder) 10065 { 10066 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 10067 struct intel_connector *connector; 10068 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 10069 struct intel_crtc_state *crtc_state = crtc ? 10070 to_intel_crtc_state(crtc->base.state) : NULL; 10071 10072 /* We need to check both for a crtc link (meaning that the 10073 * encoder is active and trying to read from a pipe) and the 10074 * pipe itself being active. */ 10075 bool has_active_crtc = crtc_state && 10076 crtc_state->hw.active; 10077 10078 if (crtc_state && has_bogus_dpll_config(crtc_state)) { 10079 drm_dbg_kms(&dev_priv->drm, 10080 "BIOS has misprogrammed the hardware. Disabling pipe %c\n", 10081 pipe_name(crtc->pipe)); 10082 has_active_crtc = false; 10083 } 10084 10085 connector = intel_encoder_find_connector(encoder); 10086 if (connector && !has_active_crtc) { 10087 drm_dbg_kms(&dev_priv->drm, 10088 "[ENCODER:%d:%s] has active connectors but no active pipe!\n", 10089 encoder->base.base.id, 10090 encoder->base.name); 10091 10092 /* Connector is active, but has no active pipe. This is 10093 * fallout from our resume register restoring. Disable 10094 * the encoder manually again. */ 10095 if (crtc_state) { 10096 struct drm_encoder *best_encoder; 10097 10098 drm_dbg_kms(&dev_priv->drm, 10099 "[ENCODER:%d:%s] manually disabled\n", 10100 encoder->base.base.id, 10101 encoder->base.name); 10102 10103 /* avoid oopsing in case the hooks consult best_encoder */ 10104 best_encoder = connector->base.state->best_encoder; 10105 connector->base.state->best_encoder = &encoder->base; 10106 10107 /* FIXME NULL atomic state passed! */ 10108 if (encoder->disable) 10109 encoder->disable(NULL, encoder, crtc_state, 10110 connector->base.state); 10111 if (encoder->post_disable) 10112 encoder->post_disable(NULL, encoder, crtc_state, 10113 connector->base.state); 10114 10115 connector->base.state->best_encoder = best_encoder; 10116 } 10117 encoder->base.crtc = NULL; 10118 10119 /* Inconsistent output/port/pipe state happens presumably due to 10120 * a bug in one of the get_hw_state functions. Or someplace else 10121 * in our code, like the register restore mess on resume. Clamp 10122 * things to off as a safer default. */ 10123 10124 connector->base.dpms = DRM_MODE_DPMS_OFF; 10125 connector->base.encoder = NULL; 10126 } 10127 10128 /* notify opregion of the sanitized encoder state */ 10129 intel_opregion_notify_encoder(encoder, connector && has_active_crtc); 10130 10131 if (HAS_DDI(dev_priv)) 10132 intel_ddi_sanitize_encoder_pll_mapping(encoder); 10133 } 10134 10135 /* FIXME read out full plane state for all planes */ 10136 static void readout_plane_state(struct drm_i915_private *dev_priv) 10137 { 10138 struct intel_plane *plane; 10139 struct intel_crtc *crtc; 10140 10141 for_each_intel_plane(&dev_priv->drm, plane) { 10142 struct intel_plane_state *plane_state = 10143 to_intel_plane_state(plane->base.state); 10144 struct intel_crtc_state *crtc_state; 10145 enum pipe pipe = PIPE_A; 10146 bool visible; 10147 10148 visible = plane->get_hw_state(plane, &pipe); 10149 10150 crtc = intel_crtc_for_pipe(dev_priv, pipe); 10151 crtc_state = to_intel_crtc_state(crtc->base.state); 10152 10153 intel_set_plane_visible(crtc_state, plane_state, visible); 10154 10155 drm_dbg_kms(&dev_priv->drm, 10156 "[PLANE:%d:%s] hw state readout: %s, pipe %c\n", 10157 plane->base.base.id, plane->base.name, 10158 str_enabled_disabled(visible), pipe_name(pipe)); 10159 } 10160 10161 for_each_intel_crtc(&dev_priv->drm, crtc) { 10162 struct intel_crtc_state *crtc_state = 10163 to_intel_crtc_state(crtc->base.state); 10164 10165 fixup_plane_bitmasks(crtc_state); 10166 } 10167 } 10168 10169 static void intel_modeset_readout_hw_state(struct drm_device *dev) 10170 { 10171 struct drm_i915_private *dev_priv = to_i915(dev); 10172 struct intel_cdclk_state *cdclk_state = 10173 to_intel_cdclk_state(dev_priv->cdclk.obj.state); 10174 struct intel_dbuf_state *dbuf_state = 10175 to_intel_dbuf_state(dev_priv->dbuf.obj.state); 10176 enum pipe pipe; 10177 struct intel_crtc *crtc; 10178 struct intel_encoder *encoder; 10179 struct intel_connector *connector; 10180 struct drm_connector_list_iter conn_iter; 10181 u8 active_pipes = 0; 10182 10183 for_each_intel_crtc(dev, crtc) { 10184 struct intel_crtc_state *crtc_state = 10185 to_intel_crtc_state(crtc->base.state); 10186 10187 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi); 10188 intel_crtc_free_hw_state(crtc_state); 10189 intel_crtc_state_reset(crtc_state, crtc); 10190 10191 intel_crtc_get_pipe_config(crtc_state); 10192 10193 crtc_state->hw.enable = crtc_state->hw.active; 10194 10195 crtc->base.enabled = crtc_state->hw.enable; 10196 crtc->active = crtc_state->hw.active; 10197 10198 if (crtc_state->hw.active) 10199 active_pipes |= BIT(crtc->pipe); 10200 10201 drm_dbg_kms(&dev_priv->drm, 10202 "[CRTC:%d:%s] hw state readout: %s\n", 10203 crtc->base.base.id, crtc->base.name, 10204 str_enabled_disabled(crtc_state->hw.active)); 10205 } 10206 10207 cdclk_state->active_pipes = dbuf_state->active_pipes = active_pipes; 10208 10209 readout_plane_state(dev_priv); 10210 10211 for_each_intel_encoder(dev, encoder) { 10212 struct intel_crtc_state *crtc_state = NULL; 10213 10214 pipe = 0; 10215 10216 if (encoder->get_hw_state(encoder, &pipe)) { 10217 crtc = intel_crtc_for_pipe(dev_priv, pipe); 10218 crtc_state = to_intel_crtc_state(crtc->base.state); 10219 10220 encoder->base.crtc = &crtc->base; 10221 intel_encoder_get_config(encoder, crtc_state); 10222 10223 /* read out to slave crtc as well for bigjoiner */ 10224 if (crtc_state->bigjoiner_pipes) { 10225 struct intel_crtc *slave_crtc; 10226 10227 /* encoder should read be linked to bigjoiner master */ 10228 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 10229 10230 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc, 10231 intel_crtc_bigjoiner_slave_pipes(crtc_state)) { 10232 struct intel_crtc_state *slave_crtc_state; 10233 10234 slave_crtc_state = to_intel_crtc_state(slave_crtc->base.state); 10235 intel_encoder_get_config(encoder, slave_crtc_state); 10236 } 10237 } 10238 } else { 10239 encoder->base.crtc = NULL; 10240 } 10241 10242 if (encoder->sync_state) 10243 encoder->sync_state(encoder, crtc_state); 10244 10245 drm_dbg_kms(&dev_priv->drm, 10246 "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", 10247 encoder->base.base.id, encoder->base.name, 10248 str_enabled_disabled(encoder->base.crtc), 10249 pipe_name(pipe)); 10250 } 10251 10252 intel_dpll_readout_hw_state(dev_priv); 10253 10254 drm_connector_list_iter_begin(dev, &conn_iter); 10255 for_each_intel_connector_iter(connector, &conn_iter) { 10256 if (connector->get_hw_state(connector)) { 10257 struct intel_crtc_state *crtc_state; 10258 struct intel_crtc *crtc; 10259 10260 connector->base.dpms = DRM_MODE_DPMS_ON; 10261 10262 encoder = intel_attached_encoder(connector); 10263 connector->base.encoder = &encoder->base; 10264 10265 crtc = to_intel_crtc(encoder->base.crtc); 10266 crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL; 10267 10268 if (crtc_state && crtc_state->hw.active) { 10269 /* 10270 * This has to be done during hardware readout 10271 * because anything calling .crtc_disable may 10272 * rely on the connector_mask being accurate. 10273 */ 10274 crtc_state->uapi.connector_mask |= 10275 drm_connector_mask(&connector->base); 10276 crtc_state->uapi.encoder_mask |= 10277 drm_encoder_mask(&encoder->base); 10278 } 10279 } else { 10280 connector->base.dpms = DRM_MODE_DPMS_OFF; 10281 connector->base.encoder = NULL; 10282 } 10283 drm_dbg_kms(&dev_priv->drm, 10284 "[CONNECTOR:%d:%s] hw state readout: %s\n", 10285 connector->base.base.id, connector->base.name, 10286 str_enabled_disabled(connector->base.encoder)); 10287 } 10288 drm_connector_list_iter_end(&conn_iter); 10289 10290 for_each_intel_crtc(dev, crtc) { 10291 struct intel_bw_state *bw_state = 10292 to_intel_bw_state(dev_priv->bw_obj.state); 10293 struct intel_crtc_state *crtc_state = 10294 to_intel_crtc_state(crtc->base.state); 10295 struct intel_plane *plane; 10296 int min_cdclk = 0; 10297 10298 if (crtc_state->hw.active) { 10299 /* 10300 * The initial mode needs to be set in order to keep 10301 * the atomic core happy. It wants a valid mode if the 10302 * crtc's enabled, so we do the above call. 10303 * 10304 * But we don't set all the derived state fully, hence 10305 * set a flag to indicate that a full recalculation is 10306 * needed on the next commit. 10307 */ 10308 crtc_state->inherited = true; 10309 10310 intel_crtc_update_active_timings(crtc_state); 10311 10312 intel_crtc_copy_hw_to_uapi_state(crtc_state); 10313 } 10314 10315 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 10316 const struct intel_plane_state *plane_state = 10317 to_intel_plane_state(plane->base.state); 10318 10319 /* 10320 * FIXME don't have the fb yet, so can't 10321 * use intel_plane_data_rate() :( 10322 */ 10323 if (plane_state->uapi.visible) 10324 crtc_state->data_rate[plane->id] = 10325 4 * crtc_state->pixel_rate; 10326 /* 10327 * FIXME don't have the fb yet, so can't 10328 * use plane->min_cdclk() :( 10329 */ 10330 if (plane_state->uapi.visible && plane->min_cdclk) { 10331 if (crtc_state->double_wide || DISPLAY_VER(dev_priv) >= 10) 10332 crtc_state->min_cdclk[plane->id] = 10333 DIV_ROUND_UP(crtc_state->pixel_rate, 2); 10334 else 10335 crtc_state->min_cdclk[plane->id] = 10336 crtc_state->pixel_rate; 10337 } 10338 drm_dbg_kms(&dev_priv->drm, 10339 "[PLANE:%d:%s] min_cdclk %d kHz\n", 10340 plane->base.base.id, plane->base.name, 10341 crtc_state->min_cdclk[plane->id]); 10342 } 10343 10344 if (crtc_state->hw.active) { 10345 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); 10346 if (drm_WARN_ON(dev, min_cdclk < 0)) 10347 min_cdclk = 0; 10348 } 10349 10350 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; 10351 cdclk_state->min_voltage_level[crtc->pipe] = 10352 crtc_state->min_voltage_level; 10353 10354 intel_bw_crtc_update(bw_state, crtc_state); 10355 10356 intel_pipe_config_sanity_check(dev_priv, crtc_state); 10357 } 10358 } 10359 10360 static void 10361 get_encoder_power_domains(struct drm_i915_private *dev_priv) 10362 { 10363 struct intel_encoder *encoder; 10364 10365 for_each_intel_encoder(&dev_priv->drm, encoder) { 10366 struct intel_crtc_state *crtc_state; 10367 10368 if (!encoder->get_power_domains) 10369 continue; 10370 10371 /* 10372 * MST-primary and inactive encoders don't have a crtc state 10373 * and neither of these require any power domain references. 10374 */ 10375 if (!encoder->base.crtc) 10376 continue; 10377 10378 crtc_state = to_intel_crtc_state(encoder->base.crtc->state); 10379 encoder->get_power_domains(encoder, crtc_state); 10380 } 10381 } 10382 10383 static void intel_early_display_was(struct drm_i915_private *dev_priv) 10384 { 10385 /* 10386 * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl 10387 * Also known as Wa_14010480278. 10388 */ 10389 if (IS_DISPLAY_VER(dev_priv, 10, 12)) 10390 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0, 10391 intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS); 10392 10393 if (IS_HASWELL(dev_priv)) { 10394 /* 10395 * WaRsPkgCStateDisplayPMReq:hsw 10396 * System hang if this isn't done before disabling all planes! 10397 */ 10398 intel_de_write(dev_priv, CHICKEN_PAR1_1, 10399 intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); 10400 } 10401 10402 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) { 10403 /* Display WA #1142:kbl,cfl,cml */ 10404 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 10405 KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22); 10406 intel_de_rmw(dev_priv, CHICKEN_MISC_2, 10407 KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14, 10408 KBL_ARB_FILL_SPARE_14); 10409 } 10410 } 10411 10412 10413 /* Scan out the current hw modeset state, 10414 * and sanitizes it to the current state 10415 */ 10416 static void 10417 intel_modeset_setup_hw_state(struct drm_device *dev, 10418 struct drm_modeset_acquire_ctx *ctx) 10419 { 10420 struct drm_i915_private *dev_priv = to_i915(dev); 10421 struct intel_encoder *encoder; 10422 struct intel_crtc *crtc; 10423 intel_wakeref_t wakeref; 10424 10425 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 10426 10427 intel_early_display_was(dev_priv); 10428 intel_modeset_readout_hw_state(dev); 10429 10430 /* HW state is read out, now we need to sanitize this mess. */ 10431 get_encoder_power_domains(dev_priv); 10432 10433 intel_pch_sanitize(dev_priv); 10434 10435 /* 10436 * intel_sanitize_plane_mapping() may need to do vblank 10437 * waits, so we need vblank interrupts restored beforehand. 10438 */ 10439 for_each_intel_crtc(&dev_priv->drm, crtc) { 10440 struct intel_crtc_state *crtc_state = 10441 to_intel_crtc_state(crtc->base.state); 10442 10443 drm_crtc_vblank_reset(&crtc->base); 10444 10445 if (crtc_state->hw.active) 10446 intel_crtc_vblank_on(crtc_state); 10447 } 10448 10449 intel_sanitize_plane_mapping(dev_priv); 10450 10451 for_each_intel_encoder(dev, encoder) 10452 intel_sanitize_encoder(encoder); 10453 10454 for_each_intel_crtc(&dev_priv->drm, crtc) { 10455 struct intel_crtc_state *crtc_state = 10456 to_intel_crtc_state(crtc->base.state); 10457 10458 intel_sanitize_crtc(crtc, ctx); 10459 intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]"); 10460 } 10461 10462 intel_modeset_update_connector_atomic_state(dev); 10463 10464 intel_dpll_sanitize_state(dev_priv); 10465 10466 if (IS_G4X(dev_priv)) { 10467 g4x_wm_get_hw_state(dev_priv); 10468 g4x_wm_sanitize(dev_priv); 10469 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 10470 vlv_wm_get_hw_state(dev_priv); 10471 vlv_wm_sanitize(dev_priv); 10472 } else if (DISPLAY_VER(dev_priv) >= 9) { 10473 skl_wm_get_hw_state(dev_priv); 10474 skl_wm_sanitize(dev_priv); 10475 } else if (HAS_PCH_SPLIT(dev_priv)) { 10476 ilk_wm_get_hw_state(dev_priv); 10477 } 10478 10479 for_each_intel_crtc(dev, crtc) { 10480 struct intel_crtc_state *crtc_state = 10481 to_intel_crtc_state(crtc->base.state); 10482 u64 put_domains; 10483 10484 put_domains = modeset_get_crtc_power_domains(crtc_state); 10485 if (drm_WARN_ON(dev, put_domains)) 10486 modeset_put_crtc_power_domains(crtc, put_domains); 10487 } 10488 10489 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref); 10490 10491 intel_power_domains_sanitize_state(dev_priv); 10492 } 10493 10494 void intel_display_resume(struct drm_device *dev) 10495 { 10496 struct drm_i915_private *dev_priv = to_i915(dev); 10497 struct drm_atomic_state *state = dev_priv->modeset_restore_state; 10498 struct drm_modeset_acquire_ctx ctx; 10499 int ret; 10500 10501 if (!HAS_DISPLAY(dev_priv)) 10502 return; 10503 10504 dev_priv->modeset_restore_state = NULL; 10505 if (state) 10506 state->acquire_ctx = &ctx; 10507 10508 drm_modeset_acquire_init(&ctx, 0); 10509 10510 while (1) { 10511 ret = drm_modeset_lock_all_ctx(dev, &ctx); 10512 if (ret != -EDEADLK) 10513 break; 10514 10515 drm_modeset_backoff(&ctx); 10516 } 10517 10518 if (!ret) 10519 ret = __intel_display_resume(dev, state, &ctx); 10520 10521 intel_enable_ipc(dev_priv); 10522 drm_modeset_drop_locks(&ctx); 10523 drm_modeset_acquire_fini(&ctx); 10524 10525 if (ret) 10526 drm_err(&dev_priv->drm, 10527 "Restoring old state failed with %i\n", ret); 10528 if (state) 10529 drm_atomic_state_put(state); 10530 } 10531 10532 static void intel_hpd_poll_fini(struct drm_i915_private *i915) 10533 { 10534 struct intel_connector *connector; 10535 struct drm_connector_list_iter conn_iter; 10536 10537 /* Kill all the work that may have been queued by hpd. */ 10538 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 10539 for_each_intel_connector_iter(connector, &conn_iter) { 10540 if (connector->modeset_retry_work.func) 10541 cancel_work_sync(&connector->modeset_retry_work); 10542 if (connector->hdcp.shim) { 10543 cancel_delayed_work_sync(&connector->hdcp.check_work); 10544 cancel_work_sync(&connector->hdcp.prop_work); 10545 } 10546 } 10547 drm_connector_list_iter_end(&conn_iter); 10548 } 10549 10550 /* part #1: call before irq uninstall */ 10551 void intel_modeset_driver_remove(struct drm_i915_private *i915) 10552 { 10553 if (!HAS_DISPLAY(i915)) 10554 return; 10555 10556 flush_workqueue(i915->flip_wq); 10557 flush_workqueue(i915->modeset_wq); 10558 10559 flush_work(&i915->atomic_helper.free_work); 10560 drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list)); 10561 } 10562 10563 /* part #2: call after irq uninstall */ 10564 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915) 10565 { 10566 if (!HAS_DISPLAY(i915)) 10567 return; 10568 10569 /* 10570 * Due to the hpd irq storm handling the hotplug work can re-arm the 10571 * poll handlers. Hence disable polling after hpd handling is shut down. 10572 */ 10573 intel_hpd_poll_fini(i915); 10574 10575 /* 10576 * MST topology needs to be suspended so we don't have any calls to 10577 * fbdev after it's finalized. MST will be destroyed later as part of 10578 * drm_mode_config_cleanup() 10579 */ 10580 intel_dp_mst_suspend(i915); 10581 10582 /* poll work can call into fbdev, hence clean that up afterwards */ 10583 intel_fbdev_fini(i915); 10584 10585 intel_unregister_dsm_handler(); 10586 10587 intel_fbc_global_disable(i915); 10588 10589 /* flush any delayed tasks or pending work */ 10590 flush_scheduled_work(); 10591 10592 intel_hdcp_component_fini(i915); 10593 10594 intel_mode_config_cleanup(i915); 10595 10596 intel_overlay_cleanup(i915); 10597 10598 intel_gmbus_teardown(i915); 10599 10600 destroy_workqueue(i915->flip_wq); 10601 destroy_workqueue(i915->modeset_wq); 10602 10603 intel_fbc_cleanup(i915); 10604 } 10605 10606 /* part #3: call after gem init */ 10607 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915) 10608 { 10609 intel_dmc_ucode_fini(i915); 10610 10611 intel_power_domains_driver_remove(i915); 10612 10613 intel_vga_unregister(i915); 10614 10615 intel_bios_driver_remove(i915); 10616 } 10617 10618 bool intel_modeset_probe_defer(struct pci_dev *pdev) 10619 { 10620 struct drm_privacy_screen *privacy_screen; 10621 10622 /* 10623 * apple-gmux is needed on dual GPU MacBook Pro 10624 * to probe the panel if we're the inactive GPU. 10625 */ 10626 if (vga_switcheroo_client_probe_defer(pdev)) 10627 return true; 10628 10629 /* If the LCD panel has a privacy-screen, wait for it */ 10630 privacy_screen = drm_privacy_screen_get(&pdev->dev, NULL); 10631 if (IS_ERR(privacy_screen) && PTR_ERR(privacy_screen) == -EPROBE_DEFER) 10632 return true; 10633 10634 drm_privacy_screen_put(privacy_screen); 10635 10636 return false; 10637 } 10638 10639 void intel_display_driver_register(struct drm_i915_private *i915) 10640 { 10641 if (!HAS_DISPLAY(i915)) 10642 return; 10643 10644 intel_display_debugfs_register(i915); 10645 10646 /* Must be done after probing outputs */ 10647 intel_opregion_register(i915); 10648 acpi_video_register(); 10649 10650 intel_audio_init(i915); 10651 10652 /* 10653 * Some ports require correctly set-up hpd registers for 10654 * detection to work properly (leading to ghost connected 10655 * connector status), e.g. VGA on gm45. Hence we can only set 10656 * up the initial fbdev config after hpd irqs are fully 10657 * enabled. We do it last so that the async config cannot run 10658 * before the connectors are registered. 10659 */ 10660 intel_fbdev_initial_config_async(&i915->drm); 10661 10662 /* 10663 * We need to coordinate the hotplugs with the asynchronous 10664 * fbdev configuration, for which we use the 10665 * fbdev->async_cookie. 10666 */ 10667 drm_kms_helper_poll_init(&i915->drm); 10668 } 10669 10670 void intel_display_driver_unregister(struct drm_i915_private *i915) 10671 { 10672 if (!HAS_DISPLAY(i915)) 10673 return; 10674 10675 intel_fbdev_unregister(i915); 10676 intel_audio_deinit(i915); 10677 10678 /* 10679 * After flushing the fbdev (incl. a late async config which 10680 * will have delayed queuing of a hotplug event), then flush 10681 * the hotplug events. 10682 */ 10683 drm_kms_helper_poll_fini(&i915->drm); 10684 drm_atomic_helper_shutdown(&i915->drm); 10685 10686 acpi_video_unregister(); 10687 intel_opregion_unregister(i915); 10688 } 10689