1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <acpi/video.h> 28 #include <linux/i2c.h> 29 #include <linux/input.h> 30 #include <linux/intel-iommu.h> 31 #include <linux/kernel.h> 32 #include <linux/module.h> 33 #include <linux/dma-resv.h> 34 #include <linux/slab.h> 35 #include <linux/string_helpers.h> 36 #include <linux/vga_switcheroo.h> 37 38 #include <drm/drm_atomic.h> 39 #include <drm/drm_atomic_helper.h> 40 #include <drm/drm_atomic_uapi.h> 41 #include <drm/drm_damage_helper.h> 42 #include <drm/dp/drm_dp_helper.h> 43 #include <drm/drm_edid.h> 44 #include <drm/drm_fourcc.h> 45 #include <drm/drm_plane_helper.h> 46 #include <drm/drm_privacy_screen_consumer.h> 47 #include <drm/drm_probe_helper.h> 48 #include <drm/drm_rect.h> 49 50 #include "display/intel_audio.h" 51 #include "display/intel_crt.h" 52 #include "display/intel_ddi.h" 53 #include "display/intel_display_debugfs.h" 54 #include "display/intel_display_power.h" 55 #include "display/intel_dp.h" 56 #include "display/intel_dp_mst.h" 57 #include "display/intel_dpll.h" 58 #include "display/intel_dpll_mgr.h" 59 #include "display/intel_drrs.h" 60 #include "display/intel_dsi.h" 61 #include "display/intel_dvo.h" 62 #include "display/intel_fb.h" 63 #include "display/intel_gmbus.h" 64 #include "display/intel_hdmi.h" 65 #include "display/intel_lvds.h" 66 #include "display/intel_sdvo.h" 67 #include "display/intel_snps_phy.h" 68 #include "display/intel_tv.h" 69 #include "display/intel_vdsc.h" 70 #include "display/intel_vrr.h" 71 72 #include "gem/i915_gem_lmem.h" 73 #include "gem/i915_gem_object.h" 74 75 #include "gt/gen8_ppgtt.h" 76 77 #include "g4x_dp.h" 78 #include "g4x_hdmi.h" 79 #include "hsw_ips.h" 80 #include "i915_drv.h" 81 #include "i915_utils.h" 82 #include "icl_dsi.h" 83 #include "intel_acpi.h" 84 #include "intel_atomic.h" 85 #include "intel_atomic_plane.h" 86 #include "intel_bw.h" 87 #include "intel_cdclk.h" 88 #include "intel_color.h" 89 #include "intel_crtc.h" 90 #include "intel_de.h" 91 #include "intel_display_types.h" 92 #include "intel_dmc.h" 93 #include "intel_dp_link_training.h" 94 #include "intel_dpt.h" 95 #include "intel_fbc.h" 96 #include "intel_fbdev.h" 97 #include "intel_fdi.h" 98 #include "intel_fifo_underrun.h" 99 #include "intel_frontbuffer.h" 100 #include "intel_hdcp.h" 101 #include "intel_hotplug.h" 102 #include "intel_overlay.h" 103 #include "intel_panel.h" 104 #include "intel_pch_display.h" 105 #include "intel_pch_refclk.h" 106 #include "intel_pcode.h" 107 #include "intel_pipe_crc.h" 108 #include "intel_plane_initial.h" 109 #include "intel_pm.h" 110 #include "intel_pps.h" 111 #include "intel_psr.h" 112 #include "intel_quirks.h" 113 #include "intel_sprite.h" 114 #include "intel_tc.h" 115 #include "intel_vga.h" 116 #include "i9xx_plane.h" 117 #include "skl_scaler.h" 118 #include "skl_universal_plane.h" 119 #include "vlv_dsi.h" 120 #include "vlv_dsi_pll.h" 121 #include "vlv_dsi_regs.h" 122 #include "vlv_sideband.h" 123 124 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state); 125 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state); 126 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state); 127 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state); 128 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state); 129 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state); 130 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state); 131 static void intel_modeset_setup_hw_state(struct drm_device *dev, 132 struct drm_modeset_acquire_ctx *ctx); 133 134 /** 135 * intel_update_watermarks - update FIFO watermark values based on current modes 136 * @dev_priv: i915 device 137 * 138 * Calculate watermark values for the various WM regs based on current mode 139 * and plane configuration. 140 * 141 * There are several cases to deal with here: 142 * - normal (i.e. non-self-refresh) 143 * - self-refresh (SR) mode 144 * - lines are large relative to FIFO size (buffer can hold up to 2) 145 * - lines are small relative to FIFO size (buffer can hold more than 2 146 * lines), so need to account for TLB latency 147 * 148 * The normal calculation is: 149 * watermark = dotclock * bytes per pixel * latency 150 * where latency is platform & configuration dependent (we assume pessimal 151 * values here). 152 * 153 * The SR calculation is: 154 * watermark = (trunc(latency/line time)+1) * surface width * 155 * bytes per pixel 156 * where 157 * line time = htotal / dotclock 158 * surface width = hdisplay for normal plane and 64 for cursor 159 * and latency is assumed to be high, as above. 160 * 161 * The final value programmed to the register should always be rounded up, 162 * and include an extra 2 entries to account for clock crossings. 163 * 164 * We don't use the sprite, so we can ignore that. And on Crestline we have 165 * to set the non-SR watermarks to 8. 166 */ 167 static void intel_update_watermarks(struct drm_i915_private *dev_priv) 168 { 169 if (dev_priv->wm_disp->update_wm) 170 dev_priv->wm_disp->update_wm(dev_priv); 171 } 172 173 static int intel_compute_pipe_wm(struct intel_atomic_state *state, 174 struct intel_crtc *crtc) 175 { 176 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 177 if (dev_priv->wm_disp->compute_pipe_wm) 178 return dev_priv->wm_disp->compute_pipe_wm(state, crtc); 179 return 0; 180 } 181 182 static int intel_compute_intermediate_wm(struct intel_atomic_state *state, 183 struct intel_crtc *crtc) 184 { 185 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 186 if (!dev_priv->wm_disp->compute_intermediate_wm) 187 return 0; 188 if (drm_WARN_ON(&dev_priv->drm, 189 !dev_priv->wm_disp->compute_pipe_wm)) 190 return 0; 191 return dev_priv->wm_disp->compute_intermediate_wm(state, crtc); 192 } 193 194 static bool intel_initial_watermarks(struct intel_atomic_state *state, 195 struct intel_crtc *crtc) 196 { 197 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 198 if (dev_priv->wm_disp->initial_watermarks) { 199 dev_priv->wm_disp->initial_watermarks(state, crtc); 200 return true; 201 } 202 return false; 203 } 204 205 static void intel_atomic_update_watermarks(struct intel_atomic_state *state, 206 struct intel_crtc *crtc) 207 { 208 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 209 if (dev_priv->wm_disp->atomic_update_watermarks) 210 dev_priv->wm_disp->atomic_update_watermarks(state, crtc); 211 } 212 213 static void intel_optimize_watermarks(struct intel_atomic_state *state, 214 struct intel_crtc *crtc) 215 { 216 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 217 if (dev_priv->wm_disp->optimize_watermarks) 218 dev_priv->wm_disp->optimize_watermarks(state, crtc); 219 } 220 221 static int intel_compute_global_watermarks(struct intel_atomic_state *state) 222 { 223 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 224 if (dev_priv->wm_disp->compute_global_watermarks) 225 return dev_priv->wm_disp->compute_global_watermarks(state); 226 return 0; 227 } 228 229 /* returns HPLL frequency in kHz */ 230 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) 231 { 232 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; 233 234 /* Obtain SKU information */ 235 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & 236 CCK_FUSE_HPLL_FREQ_MASK; 237 238 return vco_freq[hpll_freq] * 1000; 239 } 240 241 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 242 const char *name, u32 reg, int ref_freq) 243 { 244 u32 val; 245 int divider; 246 247 val = vlv_cck_read(dev_priv, reg); 248 divider = val & CCK_FREQUENCY_VALUES; 249 250 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != 251 (divider << CCK_FREQUENCY_STATUS_SHIFT), 252 "%s change in progress\n", name); 253 254 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); 255 } 256 257 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 258 const char *name, u32 reg) 259 { 260 int hpll; 261 262 vlv_cck_get(dev_priv); 263 264 if (dev_priv->hpll_freq == 0) 265 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); 266 267 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); 268 269 vlv_cck_put(dev_priv); 270 271 return hpll; 272 } 273 274 static void intel_update_czclk(struct drm_i915_private *dev_priv) 275 { 276 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) 277 return; 278 279 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", 280 CCK_CZ_CLOCK_CONTROL); 281 282 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", 283 dev_priv->czclk_freq); 284 } 285 286 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state) 287 { 288 return (crtc_state->active_planes & 289 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0; 290 } 291 292 /* WA Display #0827: Gen9:all */ 293 static void 294 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) 295 { 296 if (enable) 297 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 298 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS); 299 else 300 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 301 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS)); 302 } 303 304 /* Wa_2006604312:icl,ehl */ 305 static void 306 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 307 bool enable) 308 { 309 if (enable) 310 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 311 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS); 312 else 313 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 314 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS); 315 } 316 317 /* Wa_1604331009:icl,jsl,ehl */ 318 static void 319 icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 320 bool enable) 321 { 322 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), CURSOR_GATING_DIS, 323 enable ? CURSOR_GATING_DIS : 0); 324 } 325 326 static bool 327 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state) 328 { 329 return crtc_state->master_transcoder != INVALID_TRANSCODER; 330 } 331 332 static bool 333 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state) 334 { 335 return crtc_state->sync_mode_slaves_mask != 0; 336 } 337 338 bool 339 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state) 340 { 341 return is_trans_port_sync_master(crtc_state) || 342 is_trans_port_sync_slave(crtc_state); 343 } 344 345 static enum pipe bigjoiner_master_pipe(const struct intel_crtc_state *crtc_state) 346 { 347 return ffs(crtc_state->bigjoiner_pipes) - 1; 348 } 349 350 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state) 351 { 352 if (crtc_state->bigjoiner_pipes) 353 return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state)); 354 else 355 return 0; 356 } 357 358 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state) 359 { 360 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 361 362 return crtc_state->bigjoiner_pipes && 363 crtc->pipe != bigjoiner_master_pipe(crtc_state); 364 } 365 366 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state) 367 { 368 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 369 370 return crtc_state->bigjoiner_pipes && 371 crtc->pipe == bigjoiner_master_pipe(crtc_state); 372 } 373 374 static int intel_bigjoiner_num_pipes(const struct intel_crtc_state *crtc_state) 375 { 376 return hweight8(crtc_state->bigjoiner_pipes); 377 } 378 379 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state) 380 { 381 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 382 383 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 384 return intel_crtc_for_pipe(i915, bigjoiner_master_pipe(crtc_state)); 385 else 386 return to_intel_crtc(crtc_state->uapi.crtc); 387 } 388 389 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv, 390 enum pipe pipe) 391 { 392 i915_reg_t reg = PIPEDSL(pipe); 393 u32 line1, line2; 394 395 line1 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK; 396 msleep(5); 397 line2 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK; 398 399 return line1 != line2; 400 } 401 402 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state) 403 { 404 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 405 enum pipe pipe = crtc->pipe; 406 407 /* Wait for the display line to settle/start moving */ 408 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100)) 409 drm_err(&dev_priv->drm, 410 "pipe %c scanline %s wait timed out\n", 411 pipe_name(pipe), str_on_off(state)); 412 } 413 414 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc) 415 { 416 wait_for_pipe_scanline_moving(crtc, false); 417 } 418 419 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc) 420 { 421 wait_for_pipe_scanline_moving(crtc, true); 422 } 423 424 static void 425 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) 426 { 427 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 428 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 429 430 if (DISPLAY_VER(dev_priv) >= 4) { 431 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 432 433 /* Wait for the Pipe State to go off */ 434 if (intel_de_wait_for_clear(dev_priv, PIPECONF(cpu_transcoder), 435 PIPECONF_STATE_ENABLE, 100)) 436 drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n"); 437 } else { 438 intel_wait_for_pipe_scanline_stopped(crtc); 439 } 440 } 441 442 void assert_transcoder(struct drm_i915_private *dev_priv, 443 enum transcoder cpu_transcoder, bool state) 444 { 445 bool cur_state; 446 enum intel_display_power_domain power_domain; 447 intel_wakeref_t wakeref; 448 449 /* we keep both pipes enabled on 830 */ 450 if (IS_I830(dev_priv)) 451 state = true; 452 453 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 454 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 455 if (wakeref) { 456 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); 457 cur_state = !!(val & PIPECONF_ENABLE); 458 459 intel_display_power_put(dev_priv, power_domain, wakeref); 460 } else { 461 cur_state = false; 462 } 463 464 I915_STATE_WARN(cur_state != state, 465 "transcoder %s assertion failure (expected %s, current %s)\n", 466 transcoder_name(cpu_transcoder), 467 str_on_off(state), str_on_off(cur_state)); 468 } 469 470 static void assert_plane(struct intel_plane *plane, bool state) 471 { 472 enum pipe pipe; 473 bool cur_state; 474 475 cur_state = plane->get_hw_state(plane, &pipe); 476 477 I915_STATE_WARN(cur_state != state, 478 "%s assertion failure (expected %s, current %s)\n", 479 plane->base.name, str_on_off(state), 480 str_on_off(cur_state)); 481 } 482 483 #define assert_plane_enabled(p) assert_plane(p, true) 484 #define assert_plane_disabled(p) assert_plane(p, false) 485 486 static void assert_planes_disabled(struct intel_crtc *crtc) 487 { 488 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 489 struct intel_plane *plane; 490 491 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) 492 assert_plane_disabled(plane); 493 } 494 495 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 496 struct intel_digital_port *dig_port, 497 unsigned int expected_mask) 498 { 499 u32 port_mask; 500 i915_reg_t dpll_reg; 501 502 switch (dig_port->base.port) { 503 default: 504 MISSING_CASE(dig_port->base.port); 505 fallthrough; 506 case PORT_B: 507 port_mask = DPLL_PORTB_READY_MASK; 508 dpll_reg = DPLL(0); 509 break; 510 case PORT_C: 511 port_mask = DPLL_PORTC_READY_MASK; 512 dpll_reg = DPLL(0); 513 expected_mask <<= 4; 514 break; 515 case PORT_D: 516 port_mask = DPLL_PORTD_READY_MASK; 517 dpll_reg = DPIO_PHY_STATUS; 518 break; 519 } 520 521 if (intel_de_wait_for_register(dev_priv, dpll_reg, 522 port_mask, expected_mask, 1000)) 523 drm_WARN(&dev_priv->drm, 1, 524 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", 525 dig_port->base.base.base.id, dig_port->base.base.name, 526 intel_de_read(dev_priv, dpll_reg) & port_mask, 527 expected_mask); 528 } 529 530 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) 531 { 532 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 533 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 534 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 535 enum pipe pipe = crtc->pipe; 536 i915_reg_t reg; 537 u32 val; 538 539 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe)); 540 541 assert_planes_disabled(crtc); 542 543 /* 544 * A pipe without a PLL won't actually be able to drive bits from 545 * a plane. On ILK+ the pipe PLLs are integrated, so we don't 546 * need the check. 547 */ 548 if (HAS_GMCH(dev_priv)) { 549 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI)) 550 assert_dsi_pll_enabled(dev_priv); 551 else 552 assert_pll_enabled(dev_priv, pipe); 553 } else { 554 if (new_crtc_state->has_pch_encoder) { 555 /* if driving the PCH, we need FDI enabled */ 556 assert_fdi_rx_pll_enabled(dev_priv, 557 intel_crtc_pch_transcoder(crtc)); 558 assert_fdi_tx_pll_enabled(dev_priv, 559 (enum pipe) cpu_transcoder); 560 } 561 /* FIXME: assert CPU port conditions for SNB+ */ 562 } 563 564 /* Wa_22012358565:adl-p */ 565 if (DISPLAY_VER(dev_priv) == 13) 566 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe), 567 0, PIPE_ARB_USE_PROG_SLOTS); 568 569 reg = PIPECONF(cpu_transcoder); 570 val = intel_de_read(dev_priv, reg); 571 if (val & PIPECONF_ENABLE) { 572 /* we keep both pipes enabled on 830 */ 573 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv)); 574 return; 575 } 576 577 intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE); 578 intel_de_posting_read(dev_priv, reg); 579 580 /* 581 * Until the pipe starts PIPEDSL reads will return a stale value, 582 * which causes an apparent vblank timestamp jump when PIPEDSL 583 * resets to its proper value. That also messes up the frame count 584 * when it's derived from the timestamps. So let's wait for the 585 * pipe to start properly before we call drm_crtc_vblank_on() 586 */ 587 if (intel_crtc_max_vblank_count(new_crtc_state) == 0) 588 intel_wait_for_pipe_scanline_moving(crtc); 589 } 590 591 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) 592 { 593 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 594 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 595 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 596 enum pipe pipe = crtc->pipe; 597 i915_reg_t reg; 598 u32 val; 599 600 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe)); 601 602 /* 603 * Make sure planes won't keep trying to pump pixels to us, 604 * or we might hang the display. 605 */ 606 assert_planes_disabled(crtc); 607 608 reg = PIPECONF(cpu_transcoder); 609 val = intel_de_read(dev_priv, reg); 610 if ((val & PIPECONF_ENABLE) == 0) 611 return; 612 613 /* 614 * Double wide has implications for planes 615 * so best keep it disabled when not needed. 616 */ 617 if (old_crtc_state->double_wide) 618 val &= ~PIPECONF_DOUBLE_WIDE; 619 620 /* Don't disable pipe or pipe PLLs if needed */ 621 if (!IS_I830(dev_priv)) 622 val &= ~PIPECONF_ENABLE; 623 624 if (DISPLAY_VER(dev_priv) >= 12) 625 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 626 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 627 628 intel_de_write(dev_priv, reg, val); 629 if ((val & PIPECONF_ENABLE) == 0) 630 intel_wait_for_pipe_off(old_crtc_state); 631 } 632 633 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) 634 { 635 unsigned int size = 0; 636 int i; 637 638 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) 639 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width; 640 641 return size; 642 } 643 644 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info) 645 { 646 unsigned int size = 0; 647 int i; 648 649 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) { 650 unsigned int plane_size; 651 652 if (rem_info->plane[i].linear) 653 plane_size = rem_info->plane[i].size; 654 else 655 plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height; 656 657 if (plane_size == 0) 658 continue; 659 660 if (rem_info->plane_alignment) 661 size = ALIGN(size, rem_info->plane_alignment); 662 663 size += plane_size; 664 } 665 666 return size; 667 } 668 669 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) 670 { 671 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 672 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 673 674 return DISPLAY_VER(dev_priv) < 4 || 675 (plane->fbc && 676 plane_state->view.gtt.type == I915_GGTT_VIEW_NORMAL); 677 } 678 679 /* 680 * Convert the x/y offsets into a linear offset. 681 * Only valid with 0/180 degree rotation, which is fine since linear 682 * offset is only used with linear buffers on pre-hsw and tiled buffers 683 * with gen2/3, and 90/270 degree rotations isn't supported on any of them. 684 */ 685 u32 intel_fb_xy_to_linear(int x, int y, 686 const struct intel_plane_state *state, 687 int color_plane) 688 { 689 const struct drm_framebuffer *fb = state->hw.fb; 690 unsigned int cpp = fb->format->cpp[color_plane]; 691 unsigned int pitch = state->view.color_plane[color_plane].mapping_stride; 692 693 return y * pitch + x * cpp; 694 } 695 696 /* 697 * Add the x/y offsets derived from fb->offsets[] to the user 698 * specified plane src x/y offsets. The resulting x/y offsets 699 * specify the start of scanout from the beginning of the gtt mapping. 700 */ 701 void intel_add_fb_offsets(int *x, int *y, 702 const struct intel_plane_state *state, 703 int color_plane) 704 705 { 706 *x += state->view.color_plane[color_plane].x; 707 *y += state->view.color_plane[color_plane].y; 708 } 709 710 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 711 u32 pixel_format, u64 modifier) 712 { 713 struct intel_crtc *crtc; 714 struct intel_plane *plane; 715 716 if (!HAS_DISPLAY(dev_priv)) 717 return 0; 718 719 /* 720 * We assume the primary plane for pipe A has 721 * the highest stride limits of them all, 722 * if in case pipe A is disabled, use the first pipe from pipe_mask. 723 */ 724 crtc = intel_first_crtc(dev_priv); 725 if (!crtc) 726 return 0; 727 728 plane = to_intel_plane(crtc->base.primary); 729 730 return plane->max_stride(plane, pixel_format, modifier, 731 DRM_MODE_ROTATE_0); 732 } 733 734 static void 735 intel_set_plane_visible(struct intel_crtc_state *crtc_state, 736 struct intel_plane_state *plane_state, 737 bool visible) 738 { 739 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 740 741 plane_state->uapi.visible = visible; 742 743 if (visible) 744 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base); 745 else 746 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base); 747 } 748 749 static void fixup_plane_bitmasks(struct intel_crtc_state *crtc_state) 750 { 751 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 752 struct drm_plane *plane; 753 754 /* 755 * Active_planes aliases if multiple "primary" or cursor planes 756 * have been used on the same (or wrong) pipe. plane_mask uses 757 * unique ids, hence we can use that to reconstruct active_planes. 758 */ 759 crtc_state->enabled_planes = 0; 760 crtc_state->active_planes = 0; 761 762 drm_for_each_plane_mask(plane, &dev_priv->drm, 763 crtc_state->uapi.plane_mask) { 764 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id); 765 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id); 766 } 767 } 768 769 void intel_plane_disable_noatomic(struct intel_crtc *crtc, 770 struct intel_plane *plane) 771 { 772 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 773 struct intel_crtc_state *crtc_state = 774 to_intel_crtc_state(crtc->base.state); 775 struct intel_plane_state *plane_state = 776 to_intel_plane_state(plane->base.state); 777 778 drm_dbg_kms(&dev_priv->drm, 779 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n", 780 plane->base.base.id, plane->base.name, 781 crtc->base.base.id, crtc->base.name); 782 783 intel_set_plane_visible(crtc_state, plane_state, false); 784 fixup_plane_bitmasks(crtc_state); 785 crtc_state->data_rate[plane->id] = 0; 786 crtc_state->data_rate_y[plane->id] = 0; 787 crtc_state->rel_data_rate[plane->id] = 0; 788 crtc_state->rel_data_rate_y[plane->id] = 0; 789 crtc_state->min_cdclk[plane->id] = 0; 790 791 if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 && 792 hsw_ips_disable(crtc_state)) { 793 crtc_state->ips_enabled = false; 794 intel_crtc_wait_for_next_vblank(crtc); 795 } 796 797 /* 798 * Vblank time updates from the shadow to live plane control register 799 * are blocked if the memory self-refresh mode is active at that 800 * moment. So to make sure the plane gets truly disabled, disable 801 * first the self-refresh mode. The self-refresh enable bit in turn 802 * will be checked/applied by the HW only at the next frame start 803 * event which is after the vblank start event, so we need to have a 804 * wait-for-vblank between disabling the plane and the pipe. 805 */ 806 if (HAS_GMCH(dev_priv) && 807 intel_set_memory_cxsr(dev_priv, false)) 808 intel_crtc_wait_for_next_vblank(crtc); 809 810 /* 811 * Gen2 reports pipe underruns whenever all planes are disabled. 812 * So disable underrun reporting before all the planes get disabled. 813 */ 814 if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes) 815 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); 816 817 intel_plane_disable_arm(plane, crtc_state); 818 intel_crtc_wait_for_next_vblank(crtc); 819 } 820 821 unsigned int 822 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state) 823 { 824 int x = 0, y = 0; 825 826 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, 827 plane_state->view.color_plane[0].offset, 0); 828 829 return y; 830 } 831 832 static int 833 __intel_display_resume(struct drm_device *dev, 834 struct drm_atomic_state *state, 835 struct drm_modeset_acquire_ctx *ctx) 836 { 837 struct drm_crtc_state *crtc_state; 838 struct drm_crtc *crtc; 839 int i, ret; 840 841 intel_modeset_setup_hw_state(dev, ctx); 842 intel_vga_redisable(to_i915(dev)); 843 844 if (!state) 845 return 0; 846 847 /* 848 * We've duplicated the state, pointers to the old state are invalid. 849 * 850 * Don't attempt to use the old state until we commit the duplicated state. 851 */ 852 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 853 /* 854 * Force recalculation even if we restore 855 * current state. With fast modeset this may not result 856 * in a modeset when the state is compatible. 857 */ 858 crtc_state->mode_changed = true; 859 } 860 861 /* ignore any reset values/BIOS leftovers in the WM registers */ 862 if (!HAS_GMCH(to_i915(dev))) 863 to_intel_atomic_state(state)->skip_intermediate_wm = true; 864 865 ret = drm_atomic_helper_commit_duplicated_state(state, ctx); 866 867 drm_WARN_ON(dev, ret == -EDEADLK); 868 return ret; 869 } 870 871 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) 872 { 873 return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display && 874 intel_has_gpu_reset(to_gt(dev_priv))); 875 } 876 877 void intel_display_prepare_reset(struct drm_i915_private *dev_priv) 878 { 879 struct drm_device *dev = &dev_priv->drm; 880 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; 881 struct drm_atomic_state *state; 882 int ret; 883 884 if (!HAS_DISPLAY(dev_priv)) 885 return; 886 887 /* reset doesn't touch the display */ 888 if (!dev_priv->params.force_reset_modeset_test && 889 !gpu_reset_clobbers_display(dev_priv)) 890 return; 891 892 /* We have a modeset vs reset deadlock, defensively unbreak it. */ 893 set_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags); 894 smp_mb__after_atomic(); 895 wake_up_bit(&to_gt(dev_priv)->reset.flags, I915_RESET_MODESET); 896 897 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) { 898 drm_dbg_kms(&dev_priv->drm, 899 "Modeset potentially stuck, unbreaking through wedging\n"); 900 intel_gt_set_wedged(to_gt(dev_priv)); 901 } 902 903 /* 904 * Need mode_config.mutex so that we don't 905 * trample ongoing ->detect() and whatnot. 906 */ 907 mutex_lock(&dev->mode_config.mutex); 908 drm_modeset_acquire_init(ctx, 0); 909 while (1) { 910 ret = drm_modeset_lock_all_ctx(dev, ctx); 911 if (ret != -EDEADLK) 912 break; 913 914 drm_modeset_backoff(ctx); 915 } 916 /* 917 * Disabling the crtcs gracefully seems nicer. Also the 918 * g33 docs say we should at least disable all the planes. 919 */ 920 state = drm_atomic_helper_duplicate_state(dev, ctx); 921 if (IS_ERR(state)) { 922 ret = PTR_ERR(state); 923 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n", 924 ret); 925 return; 926 } 927 928 ret = drm_atomic_helper_disable_all(dev, ctx); 929 if (ret) { 930 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", 931 ret); 932 drm_atomic_state_put(state); 933 return; 934 } 935 936 dev_priv->modeset_restore_state = state; 937 state->acquire_ctx = ctx; 938 } 939 940 void intel_display_finish_reset(struct drm_i915_private *dev_priv) 941 { 942 struct drm_device *dev = &dev_priv->drm; 943 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; 944 struct drm_atomic_state *state; 945 int ret; 946 947 if (!HAS_DISPLAY(dev_priv)) 948 return; 949 950 /* reset doesn't touch the display */ 951 if (!test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags)) 952 return; 953 954 state = fetch_and_zero(&dev_priv->modeset_restore_state); 955 if (!state) 956 goto unlock; 957 958 /* reset doesn't touch the display */ 959 if (!gpu_reset_clobbers_display(dev_priv)) { 960 /* for testing only restore the display */ 961 ret = __intel_display_resume(dev, state, ctx); 962 if (ret) 963 drm_err(&dev_priv->drm, 964 "Restoring old state failed with %i\n", ret); 965 } else { 966 /* 967 * The display has been reset as well, 968 * so need a full re-initialization. 969 */ 970 intel_pps_unlock_regs_wa(dev_priv); 971 intel_modeset_init_hw(dev_priv); 972 intel_init_clock_gating(dev_priv); 973 intel_hpd_init(dev_priv); 974 975 ret = __intel_display_resume(dev, state, ctx); 976 if (ret) 977 drm_err(&dev_priv->drm, 978 "Restoring old state failed with %i\n", ret); 979 980 intel_hpd_poll_disable(dev_priv); 981 } 982 983 drm_atomic_state_put(state); 984 unlock: 985 drm_modeset_drop_locks(ctx); 986 drm_modeset_acquire_fini(ctx); 987 mutex_unlock(&dev->mode_config.mutex); 988 989 clear_bit_unlock(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags); 990 } 991 992 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) 993 { 994 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 995 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 996 enum pipe pipe = crtc->pipe; 997 u32 tmp; 998 999 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe)); 1000 1001 /* 1002 * Display WA #1153: icl 1003 * enable hardware to bypass the alpha math 1004 * and rounding for per-pixel values 00 and 0xff 1005 */ 1006 tmp |= PER_PIXEL_ALPHA_BYPASS_EN; 1007 /* 1008 * Display WA # 1605353570: icl 1009 * Set the pixel rounding bit to 1 for allowing 1010 * passthrough of Frame buffer pixels unmodified 1011 * across pipe 1012 */ 1013 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU; 1014 1015 /* 1016 * Underrun recovery must always be disabled on display 13+. 1017 * DG2 chicken bit meaning is inverted compared to other platforms. 1018 */ 1019 if (IS_DG2(dev_priv)) 1020 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2; 1021 else if (DISPLAY_VER(dev_priv) >= 13) 1022 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP; 1023 1024 /* Wa_14010547955:dg2 */ 1025 if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER)) 1026 tmp |= DG2_RENDER_CCSTAG_4_3_EN; 1027 1028 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp); 1029 } 1030 1031 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) 1032 { 1033 struct drm_crtc *crtc; 1034 bool cleanup_done; 1035 1036 drm_for_each_crtc(crtc, &dev_priv->drm) { 1037 struct drm_crtc_commit *commit; 1038 spin_lock(&crtc->commit_lock); 1039 commit = list_first_entry_or_null(&crtc->commit_list, 1040 struct drm_crtc_commit, commit_entry); 1041 cleanup_done = commit ? 1042 try_wait_for_completion(&commit->cleanup_done) : true; 1043 spin_unlock(&crtc->commit_lock); 1044 1045 if (cleanup_done) 1046 continue; 1047 1048 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc)); 1049 1050 return true; 1051 } 1052 1053 return false; 1054 } 1055 1056 /* 1057 * Finds the encoder associated with the given CRTC. This can only be 1058 * used when we know that the CRTC isn't feeding multiple encoders! 1059 */ 1060 struct intel_encoder * 1061 intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 1062 const struct intel_crtc_state *crtc_state) 1063 { 1064 const struct drm_connector_state *connector_state; 1065 const struct drm_connector *connector; 1066 struct intel_encoder *encoder = NULL; 1067 struct intel_crtc *master_crtc; 1068 int num_encoders = 0; 1069 int i; 1070 1071 master_crtc = intel_master_crtc(crtc_state); 1072 1073 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 1074 if (connector_state->crtc != &master_crtc->base) 1075 continue; 1076 1077 encoder = to_intel_encoder(connector_state->best_encoder); 1078 num_encoders++; 1079 } 1080 1081 drm_WARN(encoder->base.dev, num_encoders != 1, 1082 "%d encoders for pipe %c\n", 1083 num_encoders, pipe_name(master_crtc->pipe)); 1084 1085 return encoder; 1086 } 1087 1088 static void cpt_verify_modeset(struct drm_i915_private *dev_priv, 1089 enum pipe pipe) 1090 { 1091 i915_reg_t dslreg = PIPEDSL(pipe); 1092 u32 temp; 1093 1094 temp = intel_de_read(dev_priv, dslreg); 1095 udelay(500); 1096 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) { 1097 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) 1098 drm_err(&dev_priv->drm, 1099 "mode set failed: pipe %c stuck\n", 1100 pipe_name(pipe)); 1101 } 1102 } 1103 1104 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state) 1105 { 1106 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1107 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1108 const struct drm_rect *dst = &crtc_state->pch_pfit.dst; 1109 enum pipe pipe = crtc->pipe; 1110 int width = drm_rect_width(dst); 1111 int height = drm_rect_height(dst); 1112 int x = dst->x1; 1113 int y = dst->y1; 1114 1115 if (!crtc_state->pch_pfit.enabled) 1116 return; 1117 1118 /* Force use of hard-coded filter coefficients 1119 * as some pre-programmed values are broken, 1120 * e.g. x201. 1121 */ 1122 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) 1123 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 1124 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe)); 1125 else 1126 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 1127 PF_FILTER_MED_3x3); 1128 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), x << 16 | y); 1129 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), width << 16 | height); 1130 } 1131 1132 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc) 1133 { 1134 if (crtc->overlay) 1135 (void) intel_overlay_switch_off(crtc->overlay); 1136 1137 /* Let userspace switch the overlay on again. In most cases userspace 1138 * has to recompute where to put it anyway. 1139 */ 1140 } 1141 1142 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state) 1143 { 1144 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1145 1146 if (!crtc_state->nv12_planes) 1147 return false; 1148 1149 /* WA Display #0827: Gen9:all */ 1150 if (DISPLAY_VER(dev_priv) == 9) 1151 return true; 1152 1153 return false; 1154 } 1155 1156 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state) 1157 { 1158 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1159 1160 /* Wa_2006604312:icl,ehl */ 1161 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11) 1162 return true; 1163 1164 return false; 1165 } 1166 1167 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state) 1168 { 1169 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1170 1171 /* Wa_1604331009:icl,jsl,ehl */ 1172 if (is_hdr_mode(crtc_state) && 1173 crtc_state->active_planes & BIT(PLANE_CURSOR) && 1174 DISPLAY_VER(dev_priv) == 11) 1175 return true; 1176 1177 return false; 1178 } 1179 1180 static void intel_async_flip_vtd_wa(struct drm_i915_private *i915, 1181 enum pipe pipe, bool enable) 1182 { 1183 if (DISPLAY_VER(i915) == 9) { 1184 /* 1185 * "Plane N strech max must be programmed to 11b (x1) 1186 * when Async flips are enabled on that plane." 1187 */ 1188 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 1189 SKL_PLANE1_STRETCH_MAX_MASK, 1190 enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8); 1191 } else { 1192 /* Also needed on HSW/BDW albeit undocumented */ 1193 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 1194 HSW_PRI_STRETCH_MAX_MASK, 1195 enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8); 1196 } 1197 } 1198 1199 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state) 1200 { 1201 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1202 1203 return crtc_state->uapi.async_flip && i915_vtd_active(i915) && 1204 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915)); 1205 } 1206 1207 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state, 1208 const struct intel_crtc_state *new_crtc_state) 1209 { 1210 return (!old_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)) && 1211 new_crtc_state->active_planes; 1212 } 1213 1214 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state, 1215 const struct intel_crtc_state *new_crtc_state) 1216 { 1217 return old_crtc_state->active_planes && 1218 (!new_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)); 1219 } 1220 1221 static void intel_post_plane_update(struct intel_atomic_state *state, 1222 struct intel_crtc *crtc) 1223 { 1224 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1225 const struct intel_crtc_state *old_crtc_state = 1226 intel_atomic_get_old_crtc_state(state, crtc); 1227 const struct intel_crtc_state *new_crtc_state = 1228 intel_atomic_get_new_crtc_state(state, crtc); 1229 enum pipe pipe = crtc->pipe; 1230 1231 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); 1232 1233 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) 1234 intel_update_watermarks(dev_priv); 1235 1236 hsw_ips_post_update(state, crtc); 1237 intel_fbc_post_update(state, crtc); 1238 1239 if (needs_async_flip_vtd_wa(old_crtc_state) && 1240 !needs_async_flip_vtd_wa(new_crtc_state)) 1241 intel_async_flip_vtd_wa(dev_priv, pipe, false); 1242 1243 if (needs_nv12_wa(old_crtc_state) && 1244 !needs_nv12_wa(new_crtc_state)) 1245 skl_wa_827(dev_priv, pipe, false); 1246 1247 if (needs_scalerclk_wa(old_crtc_state) && 1248 !needs_scalerclk_wa(new_crtc_state)) 1249 icl_wa_scalerclkgating(dev_priv, pipe, false); 1250 1251 if (needs_cursorclk_wa(old_crtc_state) && 1252 !needs_cursorclk_wa(new_crtc_state)) 1253 icl_wa_cursorclkgating(dev_priv, pipe, false); 1254 1255 intel_drrs_activate(new_crtc_state); 1256 } 1257 1258 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state, 1259 struct intel_crtc *crtc) 1260 { 1261 const struct intel_crtc_state *crtc_state = 1262 intel_atomic_get_new_crtc_state(state, crtc); 1263 u8 update_planes = crtc_state->update_planes; 1264 const struct intel_plane_state *plane_state; 1265 struct intel_plane *plane; 1266 int i; 1267 1268 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1269 if (plane->pipe == crtc->pipe && 1270 update_planes & BIT(plane->id)) 1271 plane->enable_flip_done(plane); 1272 } 1273 } 1274 1275 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state, 1276 struct intel_crtc *crtc) 1277 { 1278 const struct intel_crtc_state *crtc_state = 1279 intel_atomic_get_new_crtc_state(state, crtc); 1280 u8 update_planes = crtc_state->update_planes; 1281 const struct intel_plane_state *plane_state; 1282 struct intel_plane *plane; 1283 int i; 1284 1285 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1286 if (plane->pipe == crtc->pipe && 1287 update_planes & BIT(plane->id)) 1288 plane->disable_flip_done(plane); 1289 } 1290 } 1291 1292 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state, 1293 struct intel_crtc *crtc) 1294 { 1295 const struct intel_crtc_state *old_crtc_state = 1296 intel_atomic_get_old_crtc_state(state, crtc); 1297 const struct intel_crtc_state *new_crtc_state = 1298 intel_atomic_get_new_crtc_state(state, crtc); 1299 u8 update_planes = new_crtc_state->update_planes; 1300 const struct intel_plane_state *old_plane_state; 1301 struct intel_plane *plane; 1302 bool need_vbl_wait = false; 1303 int i; 1304 1305 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1306 if (plane->need_async_flip_disable_wa && 1307 plane->pipe == crtc->pipe && 1308 update_planes & BIT(plane->id)) { 1309 /* 1310 * Apart from the async flip bit we want to 1311 * preserve the old state for the plane. 1312 */ 1313 plane->async_flip(plane, old_crtc_state, 1314 old_plane_state, false); 1315 need_vbl_wait = true; 1316 } 1317 } 1318 1319 if (need_vbl_wait) 1320 intel_crtc_wait_for_next_vblank(crtc); 1321 } 1322 1323 static void intel_pre_plane_update(struct intel_atomic_state *state, 1324 struct intel_crtc *crtc) 1325 { 1326 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1327 const struct intel_crtc_state *old_crtc_state = 1328 intel_atomic_get_old_crtc_state(state, crtc); 1329 const struct intel_crtc_state *new_crtc_state = 1330 intel_atomic_get_new_crtc_state(state, crtc); 1331 enum pipe pipe = crtc->pipe; 1332 1333 intel_drrs_deactivate(old_crtc_state); 1334 1335 intel_psr_pre_plane_update(state, crtc); 1336 1337 if (hsw_ips_pre_update(state, crtc)) 1338 intel_crtc_wait_for_next_vblank(crtc); 1339 1340 if (intel_fbc_pre_update(state, crtc)) 1341 intel_crtc_wait_for_next_vblank(crtc); 1342 1343 if (!needs_async_flip_vtd_wa(old_crtc_state) && 1344 needs_async_flip_vtd_wa(new_crtc_state)) 1345 intel_async_flip_vtd_wa(dev_priv, pipe, true); 1346 1347 /* Display WA 827 */ 1348 if (!needs_nv12_wa(old_crtc_state) && 1349 needs_nv12_wa(new_crtc_state)) 1350 skl_wa_827(dev_priv, pipe, true); 1351 1352 /* Wa_2006604312:icl,ehl */ 1353 if (!needs_scalerclk_wa(old_crtc_state) && 1354 needs_scalerclk_wa(new_crtc_state)) 1355 icl_wa_scalerclkgating(dev_priv, pipe, true); 1356 1357 /* Wa_1604331009:icl,jsl,ehl */ 1358 if (!needs_cursorclk_wa(old_crtc_state) && 1359 needs_cursorclk_wa(new_crtc_state)) 1360 icl_wa_cursorclkgating(dev_priv, pipe, true); 1361 1362 /* 1363 * Vblank time updates from the shadow to live plane control register 1364 * are blocked if the memory self-refresh mode is active at that 1365 * moment. So to make sure the plane gets truly disabled, disable 1366 * first the self-refresh mode. The self-refresh enable bit in turn 1367 * will be checked/applied by the HW only at the next frame start 1368 * event which is after the vblank start event, so we need to have a 1369 * wait-for-vblank between disabling the plane and the pipe. 1370 */ 1371 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active && 1372 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) 1373 intel_crtc_wait_for_next_vblank(crtc); 1374 1375 /* 1376 * IVB workaround: must disable low power watermarks for at least 1377 * one frame before enabling scaling. LP watermarks can be re-enabled 1378 * when scaling is disabled. 1379 * 1380 * WaCxSRDisabledForSpriteScaling:ivb 1381 */ 1382 if (old_crtc_state->hw.active && 1383 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv)) 1384 intel_crtc_wait_for_next_vblank(crtc); 1385 1386 /* 1387 * If we're doing a modeset we don't need to do any 1388 * pre-vblank watermark programming here. 1389 */ 1390 if (!intel_crtc_needs_modeset(new_crtc_state)) { 1391 /* 1392 * For platforms that support atomic watermarks, program the 1393 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these 1394 * will be the intermediate values that are safe for both pre- and 1395 * post- vblank; when vblank happens, the 'active' values will be set 1396 * to the final 'target' values and we'll do this again to get the 1397 * optimal watermarks. For gen9+ platforms, the values we program here 1398 * will be the final target values which will get automatically latched 1399 * at vblank time; no further programming will be necessary. 1400 * 1401 * If a platform hasn't been transitioned to atomic watermarks yet, 1402 * we'll continue to update watermarks the old way, if flags tell 1403 * us to. 1404 */ 1405 if (!intel_initial_watermarks(state, crtc)) 1406 if (new_crtc_state->update_wm_pre) 1407 intel_update_watermarks(dev_priv); 1408 } 1409 1410 /* 1411 * Gen2 reports pipe underruns whenever all planes are disabled. 1412 * So disable underrun reporting before all the planes get disabled. 1413 * 1414 * We do this after .initial_watermarks() so that we have a 1415 * chance of catching underruns with the intermediate watermarks 1416 * vs. the old plane configuration. 1417 */ 1418 if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state)) 1419 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1420 1421 /* 1422 * WA for platforms where async address update enable bit 1423 * is double buffered and only latched at start of vblank. 1424 */ 1425 if (old_crtc_state->uapi.async_flip && !new_crtc_state->uapi.async_flip) 1426 intel_crtc_async_flip_disable_wa(state, crtc); 1427 } 1428 1429 static void intel_crtc_disable_planes(struct intel_atomic_state *state, 1430 struct intel_crtc *crtc) 1431 { 1432 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1433 const struct intel_crtc_state *new_crtc_state = 1434 intel_atomic_get_new_crtc_state(state, crtc); 1435 unsigned int update_mask = new_crtc_state->update_planes; 1436 const struct intel_plane_state *old_plane_state; 1437 struct intel_plane *plane; 1438 unsigned fb_bits = 0; 1439 int i; 1440 1441 intel_crtc_dpms_overlay_disable(crtc); 1442 1443 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1444 if (crtc->pipe != plane->pipe || 1445 !(update_mask & BIT(plane->id))) 1446 continue; 1447 1448 intel_plane_disable_arm(plane, new_crtc_state); 1449 1450 if (old_plane_state->uapi.visible) 1451 fb_bits |= plane->frontbuffer_bit; 1452 } 1453 1454 intel_frontbuffer_flip(dev_priv, fb_bits); 1455 } 1456 1457 /* 1458 * intel_connector_primary_encoder - get the primary encoder for a connector 1459 * @connector: connector for which to return the encoder 1460 * 1461 * Returns the primary encoder for a connector. There is a 1:1 mapping from 1462 * all connectors to their encoder, except for DP-MST connectors which have 1463 * both a virtual and a primary encoder. These DP-MST primary encoders can be 1464 * pointed to by as many DP-MST connectors as there are pipes. 1465 */ 1466 static struct intel_encoder * 1467 intel_connector_primary_encoder(struct intel_connector *connector) 1468 { 1469 struct intel_encoder *encoder; 1470 1471 if (connector->mst_port) 1472 return &dp_to_dig_port(connector->mst_port)->base; 1473 1474 encoder = intel_attached_encoder(connector); 1475 drm_WARN_ON(connector->base.dev, !encoder); 1476 1477 return encoder; 1478 } 1479 1480 static void intel_encoders_update_prepare(struct intel_atomic_state *state) 1481 { 1482 struct drm_i915_private *i915 = to_i915(state->base.dev); 1483 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 1484 struct intel_crtc *crtc; 1485 struct drm_connector_state *new_conn_state; 1486 struct drm_connector *connector; 1487 int i; 1488 1489 /* 1490 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits. 1491 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook. 1492 */ 1493 if (i915->dpll.mgr) { 1494 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1495 if (intel_crtc_needs_modeset(new_crtc_state)) 1496 continue; 1497 1498 new_crtc_state->shared_dpll = old_crtc_state->shared_dpll; 1499 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state; 1500 } 1501 } 1502 1503 if (!state->modeset) 1504 return; 1505 1506 for_each_new_connector_in_state(&state->base, connector, new_conn_state, 1507 i) { 1508 struct intel_connector *intel_connector; 1509 struct intel_encoder *encoder; 1510 struct intel_crtc *crtc; 1511 1512 if (!intel_connector_needs_modeset(state, connector)) 1513 continue; 1514 1515 intel_connector = to_intel_connector(connector); 1516 encoder = intel_connector_primary_encoder(intel_connector); 1517 if (!encoder->update_prepare) 1518 continue; 1519 1520 crtc = new_conn_state->crtc ? 1521 to_intel_crtc(new_conn_state->crtc) : NULL; 1522 encoder->update_prepare(state, encoder, crtc); 1523 } 1524 } 1525 1526 static void intel_encoders_update_complete(struct intel_atomic_state *state) 1527 { 1528 struct drm_connector_state *new_conn_state; 1529 struct drm_connector *connector; 1530 int i; 1531 1532 if (!state->modeset) 1533 return; 1534 1535 for_each_new_connector_in_state(&state->base, connector, new_conn_state, 1536 i) { 1537 struct intel_connector *intel_connector; 1538 struct intel_encoder *encoder; 1539 struct intel_crtc *crtc; 1540 1541 if (!intel_connector_needs_modeset(state, connector)) 1542 continue; 1543 1544 intel_connector = to_intel_connector(connector); 1545 encoder = intel_connector_primary_encoder(intel_connector); 1546 if (!encoder->update_complete) 1547 continue; 1548 1549 crtc = new_conn_state->crtc ? 1550 to_intel_crtc(new_conn_state->crtc) : NULL; 1551 encoder->update_complete(state, encoder, crtc); 1552 } 1553 } 1554 1555 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state, 1556 struct intel_crtc *crtc) 1557 { 1558 const struct intel_crtc_state *crtc_state = 1559 intel_atomic_get_new_crtc_state(state, crtc); 1560 const struct drm_connector_state *conn_state; 1561 struct drm_connector *conn; 1562 int i; 1563 1564 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1565 struct intel_encoder *encoder = 1566 to_intel_encoder(conn_state->best_encoder); 1567 1568 if (conn_state->crtc != &crtc->base) 1569 continue; 1570 1571 if (encoder->pre_pll_enable) 1572 encoder->pre_pll_enable(state, encoder, 1573 crtc_state, conn_state); 1574 } 1575 } 1576 1577 static void intel_encoders_pre_enable(struct intel_atomic_state *state, 1578 struct intel_crtc *crtc) 1579 { 1580 const struct intel_crtc_state *crtc_state = 1581 intel_atomic_get_new_crtc_state(state, crtc); 1582 const struct drm_connector_state *conn_state; 1583 struct drm_connector *conn; 1584 int i; 1585 1586 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1587 struct intel_encoder *encoder = 1588 to_intel_encoder(conn_state->best_encoder); 1589 1590 if (conn_state->crtc != &crtc->base) 1591 continue; 1592 1593 if (encoder->pre_enable) 1594 encoder->pre_enable(state, encoder, 1595 crtc_state, conn_state); 1596 } 1597 } 1598 1599 static void intel_encoders_enable(struct intel_atomic_state *state, 1600 struct intel_crtc *crtc) 1601 { 1602 const struct intel_crtc_state *crtc_state = 1603 intel_atomic_get_new_crtc_state(state, crtc); 1604 const struct drm_connector_state *conn_state; 1605 struct drm_connector *conn; 1606 int i; 1607 1608 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1609 struct intel_encoder *encoder = 1610 to_intel_encoder(conn_state->best_encoder); 1611 1612 if (conn_state->crtc != &crtc->base) 1613 continue; 1614 1615 if (encoder->enable) 1616 encoder->enable(state, encoder, 1617 crtc_state, conn_state); 1618 intel_opregion_notify_encoder(encoder, true); 1619 } 1620 } 1621 1622 static void intel_encoders_disable(struct intel_atomic_state *state, 1623 struct intel_crtc *crtc) 1624 { 1625 const struct intel_crtc_state *old_crtc_state = 1626 intel_atomic_get_old_crtc_state(state, crtc); 1627 const struct drm_connector_state *old_conn_state; 1628 struct drm_connector *conn; 1629 int i; 1630 1631 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1632 struct intel_encoder *encoder = 1633 to_intel_encoder(old_conn_state->best_encoder); 1634 1635 if (old_conn_state->crtc != &crtc->base) 1636 continue; 1637 1638 intel_opregion_notify_encoder(encoder, false); 1639 if (encoder->disable) 1640 encoder->disable(state, encoder, 1641 old_crtc_state, old_conn_state); 1642 } 1643 } 1644 1645 static void intel_encoders_post_disable(struct intel_atomic_state *state, 1646 struct intel_crtc *crtc) 1647 { 1648 const struct intel_crtc_state *old_crtc_state = 1649 intel_atomic_get_old_crtc_state(state, crtc); 1650 const struct drm_connector_state *old_conn_state; 1651 struct drm_connector *conn; 1652 int i; 1653 1654 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1655 struct intel_encoder *encoder = 1656 to_intel_encoder(old_conn_state->best_encoder); 1657 1658 if (old_conn_state->crtc != &crtc->base) 1659 continue; 1660 1661 if (encoder->post_disable) 1662 encoder->post_disable(state, encoder, 1663 old_crtc_state, old_conn_state); 1664 } 1665 } 1666 1667 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state, 1668 struct intel_crtc *crtc) 1669 { 1670 const struct intel_crtc_state *old_crtc_state = 1671 intel_atomic_get_old_crtc_state(state, crtc); 1672 const struct drm_connector_state *old_conn_state; 1673 struct drm_connector *conn; 1674 int i; 1675 1676 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1677 struct intel_encoder *encoder = 1678 to_intel_encoder(old_conn_state->best_encoder); 1679 1680 if (old_conn_state->crtc != &crtc->base) 1681 continue; 1682 1683 if (encoder->post_pll_disable) 1684 encoder->post_pll_disable(state, encoder, 1685 old_crtc_state, old_conn_state); 1686 } 1687 } 1688 1689 static void intel_encoders_update_pipe(struct intel_atomic_state *state, 1690 struct intel_crtc *crtc) 1691 { 1692 const struct intel_crtc_state *crtc_state = 1693 intel_atomic_get_new_crtc_state(state, crtc); 1694 const struct drm_connector_state *conn_state; 1695 struct drm_connector *conn; 1696 int i; 1697 1698 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1699 struct intel_encoder *encoder = 1700 to_intel_encoder(conn_state->best_encoder); 1701 1702 if (conn_state->crtc != &crtc->base) 1703 continue; 1704 1705 if (encoder->update_pipe) 1706 encoder->update_pipe(state, encoder, 1707 crtc_state, conn_state); 1708 } 1709 } 1710 1711 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state) 1712 { 1713 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1714 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 1715 1716 plane->disable_arm(plane, crtc_state); 1717 } 1718 1719 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1720 { 1721 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1722 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1723 1724 if (crtc_state->has_pch_encoder) { 1725 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1726 &crtc_state->fdi_m_n); 1727 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1728 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1729 &crtc_state->dp_m_n); 1730 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1731 &crtc_state->dp_m2_n2); 1732 } 1733 1734 intel_set_transcoder_timings(crtc_state); 1735 1736 ilk_set_pipeconf(crtc_state); 1737 } 1738 1739 static void ilk_crtc_enable(struct intel_atomic_state *state, 1740 struct intel_crtc *crtc) 1741 { 1742 const struct intel_crtc_state *new_crtc_state = 1743 intel_atomic_get_new_crtc_state(state, crtc); 1744 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1745 enum pipe pipe = crtc->pipe; 1746 1747 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1748 return; 1749 1750 /* 1751 * Sometimes spurious CPU pipe underruns happen during FDI 1752 * training, at least with VGA+HDMI cloning. Suppress them. 1753 * 1754 * On ILK we get an occasional spurious CPU pipe underruns 1755 * between eDP port A enable and vdd enable. Also PCH port 1756 * enable seems to result in the occasional CPU pipe underrun. 1757 * 1758 * Spurious PCH underruns also occur during PCH enabling. 1759 */ 1760 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1761 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 1762 1763 ilk_configure_cpu_transcoder(new_crtc_state); 1764 1765 intel_set_pipe_src_size(new_crtc_state); 1766 1767 crtc->active = true; 1768 1769 intel_encoders_pre_enable(state, crtc); 1770 1771 if (new_crtc_state->has_pch_encoder) { 1772 ilk_pch_pre_enable(state, crtc); 1773 } else { 1774 assert_fdi_tx_disabled(dev_priv, pipe); 1775 assert_fdi_rx_disabled(dev_priv, pipe); 1776 } 1777 1778 ilk_pfit_enable(new_crtc_state); 1779 1780 /* 1781 * On ILK+ LUT must be loaded before the pipe is running but with 1782 * clocks enabled 1783 */ 1784 intel_color_load_luts(new_crtc_state); 1785 intel_color_commit_noarm(new_crtc_state); 1786 intel_color_commit_arm(new_crtc_state); 1787 /* update DSPCNTR to configure gamma for pipe bottom color */ 1788 intel_disable_primary_plane(new_crtc_state); 1789 1790 intel_initial_watermarks(state, crtc); 1791 intel_enable_transcoder(new_crtc_state); 1792 1793 if (new_crtc_state->has_pch_encoder) 1794 ilk_pch_enable(state, crtc); 1795 1796 intel_crtc_vblank_on(new_crtc_state); 1797 1798 intel_encoders_enable(state, crtc); 1799 1800 if (HAS_PCH_CPT(dev_priv)) 1801 cpt_verify_modeset(dev_priv, pipe); 1802 1803 /* 1804 * Must wait for vblank to avoid spurious PCH FIFO underruns. 1805 * And a second vblank wait is needed at least on ILK with 1806 * some interlaced HDMI modes. Let's do the double wait always 1807 * in case there are more corner cases we don't know about. 1808 */ 1809 if (new_crtc_state->has_pch_encoder) { 1810 intel_crtc_wait_for_next_vblank(crtc); 1811 intel_crtc_wait_for_next_vblank(crtc); 1812 } 1813 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1814 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 1815 } 1816 1817 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, 1818 enum pipe pipe, bool apply) 1819 { 1820 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)); 1821 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS; 1822 1823 if (apply) 1824 val |= mask; 1825 else 1826 val &= ~mask; 1827 1828 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val); 1829 } 1830 1831 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state) 1832 { 1833 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1834 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1835 1836 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe), 1837 HSW_LINETIME(crtc_state->linetime) | 1838 HSW_IPS_LINETIME(crtc_state->ips_linetime)); 1839 } 1840 1841 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) 1842 { 1843 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1844 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1845 i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder); 1846 u32 val; 1847 1848 val = intel_de_read(dev_priv, reg); 1849 val &= ~HSW_FRAME_START_DELAY_MASK; 1850 val |= HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 1851 intel_de_write(dev_priv, reg, val); 1852 } 1853 1854 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state, 1855 const struct intel_crtc_state *crtc_state) 1856 { 1857 struct intel_crtc *master_crtc = intel_master_crtc(crtc_state); 1858 1859 /* 1860 * Enable sequence steps 1-7 on bigjoiner master 1861 */ 1862 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1863 intel_encoders_pre_pll_enable(state, master_crtc); 1864 1865 if (crtc_state->shared_dpll) 1866 intel_enable_shared_dpll(crtc_state); 1867 1868 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1869 intel_encoders_pre_enable(state, master_crtc); 1870 } 1871 1872 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1873 { 1874 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1875 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1876 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1877 1878 if (crtc_state->has_pch_encoder) { 1879 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1880 &crtc_state->fdi_m_n); 1881 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1882 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1883 &crtc_state->dp_m_n); 1884 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1885 &crtc_state->dp_m2_n2); 1886 } 1887 1888 intel_set_transcoder_timings(crtc_state); 1889 1890 if (cpu_transcoder != TRANSCODER_EDP) 1891 intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder), 1892 crtc_state->pixel_multiplier - 1); 1893 1894 hsw_set_frame_start_delay(crtc_state); 1895 1896 hsw_set_transconf(crtc_state); 1897 } 1898 1899 static void hsw_crtc_enable(struct intel_atomic_state *state, 1900 struct intel_crtc *crtc) 1901 { 1902 const struct intel_crtc_state *new_crtc_state = 1903 intel_atomic_get_new_crtc_state(state, crtc); 1904 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1905 enum pipe pipe = crtc->pipe, hsw_workaround_pipe; 1906 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 1907 bool psl_clkgate_wa; 1908 1909 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1910 return; 1911 1912 if (!new_crtc_state->bigjoiner_pipes) { 1913 intel_encoders_pre_pll_enable(state, crtc); 1914 1915 if (new_crtc_state->shared_dpll) 1916 intel_enable_shared_dpll(new_crtc_state); 1917 1918 intel_encoders_pre_enable(state, crtc); 1919 } else { 1920 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state); 1921 } 1922 1923 intel_dsc_enable(new_crtc_state); 1924 1925 if (DISPLAY_VER(dev_priv) >= 13) 1926 intel_uncompressed_joiner_enable(new_crtc_state); 1927 1928 intel_set_pipe_src_size(new_crtc_state); 1929 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 1930 bdw_set_pipemisc(new_crtc_state); 1931 1932 if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) && 1933 !transcoder_is_dsi(cpu_transcoder)) 1934 hsw_configure_cpu_transcoder(new_crtc_state); 1935 1936 crtc->active = true; 1937 1938 /* Display WA #1180: WaDisableScalarClockGating: glk */ 1939 psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 && 1940 new_crtc_state->pch_pfit.enabled; 1941 if (psl_clkgate_wa) 1942 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true); 1943 1944 if (DISPLAY_VER(dev_priv) >= 9) 1945 skl_pfit_enable(new_crtc_state); 1946 else 1947 ilk_pfit_enable(new_crtc_state); 1948 1949 /* 1950 * On ILK+ LUT must be loaded before the pipe is running but with 1951 * clocks enabled 1952 */ 1953 intel_color_load_luts(new_crtc_state); 1954 intel_color_commit_noarm(new_crtc_state); 1955 intel_color_commit_arm(new_crtc_state); 1956 /* update DSPCNTR to configure gamma/csc for pipe bottom color */ 1957 if (DISPLAY_VER(dev_priv) < 9) 1958 intel_disable_primary_plane(new_crtc_state); 1959 1960 hsw_set_linetime_wm(new_crtc_state); 1961 1962 if (DISPLAY_VER(dev_priv) >= 11) 1963 icl_set_pipe_chicken(new_crtc_state); 1964 1965 intel_initial_watermarks(state, crtc); 1966 1967 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 1968 intel_crtc_vblank_on(new_crtc_state); 1969 1970 intel_encoders_enable(state, crtc); 1971 1972 if (psl_clkgate_wa) { 1973 intel_crtc_wait_for_next_vblank(crtc); 1974 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false); 1975 } 1976 1977 /* If we change the relative order between pipe/planes enabling, we need 1978 * to change the workaround. */ 1979 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe; 1980 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { 1981 struct intel_crtc *wa_crtc; 1982 1983 wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe); 1984 1985 intel_crtc_wait_for_next_vblank(wa_crtc); 1986 intel_crtc_wait_for_next_vblank(wa_crtc); 1987 } 1988 } 1989 1990 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state) 1991 { 1992 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1993 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1994 enum pipe pipe = crtc->pipe; 1995 1996 /* To avoid upsetting the power well on haswell only disable the pfit if 1997 * it's in use. The hw state code will make sure we get this right. */ 1998 if (!old_crtc_state->pch_pfit.enabled) 1999 return; 2000 2001 intel_de_write_fw(dev_priv, PF_CTL(pipe), 0); 2002 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0); 2003 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0); 2004 } 2005 2006 static void ilk_crtc_disable(struct intel_atomic_state *state, 2007 struct intel_crtc *crtc) 2008 { 2009 const struct intel_crtc_state *old_crtc_state = 2010 intel_atomic_get_old_crtc_state(state, crtc); 2011 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2012 enum pipe pipe = crtc->pipe; 2013 2014 /* 2015 * Sometimes spurious CPU pipe underruns happen when the 2016 * pipe is already disabled, but FDI RX/TX is still enabled. 2017 * Happens at least with VGA+HDMI cloning. Suppress them. 2018 */ 2019 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 2020 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 2021 2022 intel_encoders_disable(state, crtc); 2023 2024 intel_crtc_vblank_off(old_crtc_state); 2025 2026 intel_disable_transcoder(old_crtc_state); 2027 2028 ilk_pfit_disable(old_crtc_state); 2029 2030 if (old_crtc_state->has_pch_encoder) 2031 ilk_pch_disable(state, crtc); 2032 2033 intel_encoders_post_disable(state, crtc); 2034 2035 if (old_crtc_state->has_pch_encoder) 2036 ilk_pch_post_disable(state, crtc); 2037 2038 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2039 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 2040 } 2041 2042 static void hsw_crtc_disable(struct intel_atomic_state *state, 2043 struct intel_crtc *crtc) 2044 { 2045 const struct intel_crtc_state *old_crtc_state = 2046 intel_atomic_get_old_crtc_state(state, crtc); 2047 2048 /* 2049 * FIXME collapse everything to one hook. 2050 * Need care with mst->ddi interactions. 2051 */ 2052 if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) { 2053 intel_encoders_disable(state, crtc); 2054 intel_encoders_post_disable(state, crtc); 2055 } 2056 } 2057 2058 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) 2059 { 2060 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2061 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2062 2063 if (!crtc_state->gmch_pfit.control) 2064 return; 2065 2066 /* 2067 * The panel fitter should only be adjusted whilst the pipe is disabled, 2068 * according to register description and PRM. 2069 */ 2070 drm_WARN_ON(&dev_priv->drm, 2071 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE); 2072 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 2073 2074 intel_de_write(dev_priv, PFIT_PGM_RATIOS, 2075 crtc_state->gmch_pfit.pgm_ratios); 2076 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control); 2077 2078 /* Border color in case we don't scale up to the full screen. Black by 2079 * default, change to something else for debugging. */ 2080 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); 2081 } 2082 2083 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) 2084 { 2085 if (phy == PHY_NONE) 2086 return false; 2087 else if (IS_DG2(dev_priv)) 2088 /* 2089 * DG2 outputs labelled as "combo PHY" in the bspec use 2090 * SNPS PHYs with completely different programming, 2091 * hence we always return false here. 2092 */ 2093 return false; 2094 else if (IS_ALDERLAKE_S(dev_priv)) 2095 return phy <= PHY_E; 2096 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) 2097 return phy <= PHY_D; 2098 else if (IS_JSL_EHL(dev_priv)) 2099 return phy <= PHY_C; 2100 else if (DISPLAY_VER(dev_priv) >= 11) 2101 return phy <= PHY_B; 2102 else 2103 return false; 2104 } 2105 2106 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) 2107 { 2108 if (IS_DG2(dev_priv)) 2109 /* DG2's "TC1" output uses a SNPS PHY */ 2110 return false; 2111 else if (IS_ALDERLAKE_P(dev_priv)) 2112 return phy >= PHY_F && phy <= PHY_I; 2113 else if (IS_TIGERLAKE(dev_priv)) 2114 return phy >= PHY_D && phy <= PHY_I; 2115 else if (IS_ICELAKE(dev_priv)) 2116 return phy >= PHY_C && phy <= PHY_F; 2117 else 2118 return false; 2119 } 2120 2121 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy) 2122 { 2123 if (phy == PHY_NONE) 2124 return false; 2125 else if (IS_DG2(dev_priv)) 2126 /* 2127 * All four "combo" ports and the TC1 port (PHY E) use 2128 * Synopsis PHYs. 2129 */ 2130 return phy <= PHY_E; 2131 2132 return false; 2133 } 2134 2135 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) 2136 { 2137 if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD) 2138 return PHY_D + port - PORT_D_XELPD; 2139 else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1) 2140 return PHY_F + port - PORT_TC1; 2141 else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1) 2142 return PHY_B + port - PORT_TC1; 2143 else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1) 2144 return PHY_C + port - PORT_TC1; 2145 else if (IS_JSL_EHL(i915) && port == PORT_D) 2146 return PHY_A; 2147 2148 return PHY_A + port - PORT_A; 2149 } 2150 2151 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) 2152 { 2153 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port))) 2154 return TC_PORT_NONE; 2155 2156 if (DISPLAY_VER(dev_priv) >= 12) 2157 return TC_PORT_1 + port - PORT_TC1; 2158 else 2159 return TC_PORT_1 + port - PORT_C; 2160 } 2161 2162 enum intel_display_power_domain 2163 intel_aux_power_domain(struct intel_digital_port *dig_port) 2164 { 2165 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 2166 2167 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 2168 return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch); 2169 2170 return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch); 2171 } 2172 2173 static void get_crtc_power_domains(struct intel_crtc_state *crtc_state, 2174 struct intel_power_domain_mask *mask) 2175 { 2176 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2177 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2178 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2179 struct drm_encoder *encoder; 2180 enum pipe pipe = crtc->pipe; 2181 2182 bitmap_zero(mask->bits, POWER_DOMAIN_NUM); 2183 2184 if (!crtc_state->hw.active) 2185 return; 2186 2187 set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits); 2188 set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits); 2189 if (crtc_state->pch_pfit.enabled || 2190 crtc_state->pch_pfit.force_thru) 2191 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits); 2192 2193 drm_for_each_encoder_mask(encoder, &dev_priv->drm, 2194 crtc_state->uapi.encoder_mask) { 2195 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2196 2197 set_bit(intel_encoder->power_domain, mask->bits); 2198 } 2199 2200 if (HAS_DDI(dev_priv) && crtc_state->has_audio) 2201 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits); 2202 2203 if (crtc_state->shared_dpll) 2204 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits); 2205 2206 if (crtc_state->dsc.compression_enable) 2207 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits); 2208 } 2209 2210 static void 2211 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, 2212 struct intel_power_domain_mask *old_domains) 2213 { 2214 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2215 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2216 enum intel_display_power_domain domain; 2217 struct intel_power_domain_mask domains, new_domains; 2218 2219 get_crtc_power_domains(crtc_state, &domains); 2220 2221 bitmap_andnot(new_domains.bits, 2222 domains.bits, 2223 crtc->enabled_power_domains.mask.bits, 2224 POWER_DOMAIN_NUM); 2225 bitmap_andnot(old_domains->bits, 2226 crtc->enabled_power_domains.mask.bits, 2227 domains.bits, 2228 POWER_DOMAIN_NUM); 2229 2230 for_each_power_domain(domain, &new_domains) 2231 intel_display_power_get_in_set(dev_priv, 2232 &crtc->enabled_power_domains, 2233 domain); 2234 } 2235 2236 static void modeset_put_crtc_power_domains(struct intel_crtc *crtc, 2237 struct intel_power_domain_mask *domains) 2238 { 2239 intel_display_power_put_mask_in_set(to_i915(crtc->base.dev), 2240 &crtc->enabled_power_domains, 2241 domains); 2242 } 2243 2244 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 2245 { 2246 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2247 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2248 2249 if (intel_crtc_has_dp_encoder(crtc_state)) { 2250 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 2251 &crtc_state->dp_m_n); 2252 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 2253 &crtc_state->dp_m2_n2); 2254 } 2255 2256 intel_set_transcoder_timings(crtc_state); 2257 2258 i9xx_set_pipeconf(crtc_state); 2259 } 2260 2261 static void valleyview_crtc_enable(struct intel_atomic_state *state, 2262 struct intel_crtc *crtc) 2263 { 2264 const struct intel_crtc_state *new_crtc_state = 2265 intel_atomic_get_new_crtc_state(state, crtc); 2266 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2267 enum pipe pipe = crtc->pipe; 2268 2269 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 2270 return; 2271 2272 i9xx_configure_cpu_transcoder(new_crtc_state); 2273 2274 intel_set_pipe_src_size(new_crtc_state); 2275 2276 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 2277 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY); 2278 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0); 2279 } 2280 2281 crtc->active = true; 2282 2283 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2284 2285 intel_encoders_pre_pll_enable(state, crtc); 2286 2287 if (IS_CHERRYVIEW(dev_priv)) 2288 chv_enable_pll(new_crtc_state); 2289 else 2290 vlv_enable_pll(new_crtc_state); 2291 2292 intel_encoders_pre_enable(state, crtc); 2293 2294 i9xx_pfit_enable(new_crtc_state); 2295 2296 intel_color_load_luts(new_crtc_state); 2297 intel_color_commit_noarm(new_crtc_state); 2298 intel_color_commit_arm(new_crtc_state); 2299 /* update DSPCNTR to configure gamma for pipe bottom color */ 2300 intel_disable_primary_plane(new_crtc_state); 2301 2302 intel_initial_watermarks(state, crtc); 2303 intel_enable_transcoder(new_crtc_state); 2304 2305 intel_crtc_vblank_on(new_crtc_state); 2306 2307 intel_encoders_enable(state, crtc); 2308 } 2309 2310 static void i9xx_crtc_enable(struct intel_atomic_state *state, 2311 struct intel_crtc *crtc) 2312 { 2313 const struct intel_crtc_state *new_crtc_state = 2314 intel_atomic_get_new_crtc_state(state, crtc); 2315 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2316 enum pipe pipe = crtc->pipe; 2317 2318 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 2319 return; 2320 2321 i9xx_configure_cpu_transcoder(new_crtc_state); 2322 2323 intel_set_pipe_src_size(new_crtc_state); 2324 2325 crtc->active = true; 2326 2327 if (DISPLAY_VER(dev_priv) != 2) 2328 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2329 2330 intel_encoders_pre_enable(state, crtc); 2331 2332 i9xx_enable_pll(new_crtc_state); 2333 2334 i9xx_pfit_enable(new_crtc_state); 2335 2336 intel_color_load_luts(new_crtc_state); 2337 intel_color_commit_noarm(new_crtc_state); 2338 intel_color_commit_arm(new_crtc_state); 2339 /* update DSPCNTR to configure gamma for pipe bottom color */ 2340 intel_disable_primary_plane(new_crtc_state); 2341 2342 if (!intel_initial_watermarks(state, crtc)) 2343 intel_update_watermarks(dev_priv); 2344 intel_enable_transcoder(new_crtc_state); 2345 2346 intel_crtc_vblank_on(new_crtc_state); 2347 2348 intel_encoders_enable(state, crtc); 2349 2350 /* prevents spurious underruns */ 2351 if (DISPLAY_VER(dev_priv) == 2) 2352 intel_crtc_wait_for_next_vblank(crtc); 2353 } 2354 2355 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) 2356 { 2357 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 2358 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2359 2360 if (!old_crtc_state->gmch_pfit.control) 2361 return; 2362 2363 assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder); 2364 2365 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n", 2366 intel_de_read(dev_priv, PFIT_CONTROL)); 2367 intel_de_write(dev_priv, PFIT_CONTROL, 0); 2368 } 2369 2370 static void i9xx_crtc_disable(struct intel_atomic_state *state, 2371 struct intel_crtc *crtc) 2372 { 2373 struct intel_crtc_state *old_crtc_state = 2374 intel_atomic_get_old_crtc_state(state, crtc); 2375 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2376 enum pipe pipe = crtc->pipe; 2377 2378 /* 2379 * On gen2 planes are double buffered but the pipe isn't, so we must 2380 * wait for planes to fully turn off before disabling the pipe. 2381 */ 2382 if (DISPLAY_VER(dev_priv) == 2) 2383 intel_crtc_wait_for_next_vblank(crtc); 2384 2385 intel_encoders_disable(state, crtc); 2386 2387 intel_crtc_vblank_off(old_crtc_state); 2388 2389 intel_disable_transcoder(old_crtc_state); 2390 2391 i9xx_pfit_disable(old_crtc_state); 2392 2393 intel_encoders_post_disable(state, crtc); 2394 2395 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) { 2396 if (IS_CHERRYVIEW(dev_priv)) 2397 chv_disable_pll(dev_priv, pipe); 2398 else if (IS_VALLEYVIEW(dev_priv)) 2399 vlv_disable_pll(dev_priv, pipe); 2400 else 2401 i9xx_disable_pll(old_crtc_state); 2402 } 2403 2404 intel_encoders_post_pll_disable(state, crtc); 2405 2406 if (DISPLAY_VER(dev_priv) != 2) 2407 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 2408 2409 if (!dev_priv->wm_disp->initial_watermarks) 2410 intel_update_watermarks(dev_priv); 2411 2412 /* clock the pipe down to 640x480@60 to potentially save power */ 2413 if (IS_I830(dev_priv)) 2414 i830_enable_pipe(dev_priv, pipe); 2415 } 2416 2417 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, 2418 struct drm_modeset_acquire_ctx *ctx) 2419 { 2420 struct intel_encoder *encoder; 2421 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2422 struct intel_bw_state *bw_state = 2423 to_intel_bw_state(dev_priv->bw_obj.state); 2424 struct intel_cdclk_state *cdclk_state = 2425 to_intel_cdclk_state(dev_priv->cdclk.obj.state); 2426 struct intel_dbuf_state *dbuf_state = 2427 to_intel_dbuf_state(dev_priv->dbuf.obj.state); 2428 struct intel_crtc_state *crtc_state = 2429 to_intel_crtc_state(crtc->base.state); 2430 struct intel_plane *plane; 2431 struct drm_atomic_state *state; 2432 struct intel_crtc_state *temp_crtc_state; 2433 enum pipe pipe = crtc->pipe; 2434 int ret; 2435 2436 if (!crtc_state->hw.active) 2437 return; 2438 2439 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 2440 const struct intel_plane_state *plane_state = 2441 to_intel_plane_state(plane->base.state); 2442 2443 if (plane_state->uapi.visible) 2444 intel_plane_disable_noatomic(crtc, plane); 2445 } 2446 2447 state = drm_atomic_state_alloc(&dev_priv->drm); 2448 if (!state) { 2449 drm_dbg_kms(&dev_priv->drm, 2450 "failed to disable [CRTC:%d:%s], out of memory", 2451 crtc->base.base.id, crtc->base.name); 2452 return; 2453 } 2454 2455 state->acquire_ctx = ctx; 2456 2457 /* Everything's already locked, -EDEADLK can't happen. */ 2458 temp_crtc_state = intel_atomic_get_crtc_state(state, crtc); 2459 ret = drm_atomic_add_affected_connectors(state, &crtc->base); 2460 2461 drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret); 2462 2463 dev_priv->display->crtc_disable(to_intel_atomic_state(state), crtc); 2464 2465 drm_atomic_state_put(state); 2466 2467 drm_dbg_kms(&dev_priv->drm, 2468 "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", 2469 crtc->base.base.id, crtc->base.name); 2470 2471 crtc->active = false; 2472 crtc->base.enabled = false; 2473 2474 drm_WARN_ON(&dev_priv->drm, 2475 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0); 2476 crtc_state->uapi.active = false; 2477 crtc_state->uapi.connector_mask = 0; 2478 crtc_state->uapi.encoder_mask = 0; 2479 intel_crtc_free_hw_state(crtc_state); 2480 memset(&crtc_state->hw, 0, sizeof(crtc_state->hw)); 2481 2482 for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder) 2483 encoder->base.crtc = NULL; 2484 2485 intel_fbc_disable(crtc); 2486 intel_update_watermarks(dev_priv); 2487 intel_disable_shared_dpll(crtc_state); 2488 2489 intel_display_power_put_all_in_set(dev_priv, &crtc->enabled_power_domains); 2490 2491 cdclk_state->min_cdclk[pipe] = 0; 2492 cdclk_state->min_voltage_level[pipe] = 0; 2493 cdclk_state->active_pipes &= ~BIT(pipe); 2494 2495 dbuf_state->active_pipes &= ~BIT(pipe); 2496 2497 bw_state->data_rate[pipe] = 0; 2498 bw_state->num_active_planes[pipe] = 0; 2499 } 2500 2501 /* 2502 * turn all crtc's off, but do not adjust state 2503 * This has to be paired with a call to intel_modeset_setup_hw_state. 2504 */ 2505 int intel_display_suspend(struct drm_device *dev) 2506 { 2507 struct drm_i915_private *dev_priv = to_i915(dev); 2508 struct drm_atomic_state *state; 2509 int ret; 2510 2511 if (!HAS_DISPLAY(dev_priv)) 2512 return 0; 2513 2514 state = drm_atomic_helper_suspend(dev); 2515 ret = PTR_ERR_OR_ZERO(state); 2516 if (ret) 2517 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", 2518 ret); 2519 else 2520 dev_priv->modeset_restore_state = state; 2521 return ret; 2522 } 2523 2524 void intel_encoder_destroy(struct drm_encoder *encoder) 2525 { 2526 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2527 2528 drm_encoder_cleanup(encoder); 2529 kfree(intel_encoder); 2530 } 2531 2532 /* Cross check the actual hw state with our own modeset state tracking (and it's 2533 * internal consistency). */ 2534 static void intel_connector_verify_state(struct intel_crtc_state *crtc_state, 2535 struct drm_connector_state *conn_state) 2536 { 2537 struct intel_connector *connector = to_intel_connector(conn_state->connector); 2538 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2539 2540 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", 2541 connector->base.base.id, connector->base.name); 2542 2543 if (connector->get_hw_state(connector)) { 2544 struct intel_encoder *encoder = intel_attached_encoder(connector); 2545 2546 I915_STATE_WARN(!crtc_state, 2547 "connector enabled without attached crtc\n"); 2548 2549 if (!crtc_state) 2550 return; 2551 2552 I915_STATE_WARN(!crtc_state->hw.active, 2553 "connector is active, but attached crtc isn't\n"); 2554 2555 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) 2556 return; 2557 2558 I915_STATE_WARN(conn_state->best_encoder != &encoder->base, 2559 "atomic encoder doesn't match attached encoder\n"); 2560 2561 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, 2562 "attached encoder crtc differs from connector crtc\n"); 2563 } else { 2564 I915_STATE_WARN(crtc_state && crtc_state->hw.active, 2565 "attached crtc is active, but connector isn't\n"); 2566 I915_STATE_WARN(!crtc_state && conn_state->best_encoder, 2567 "best encoder set without crtc!\n"); 2568 } 2569 } 2570 2571 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) 2572 { 2573 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2574 2575 /* GDG double wide on either pipe, otherwise pipe A only */ 2576 return DISPLAY_VER(dev_priv) < 4 && 2577 (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); 2578 } 2579 2580 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) 2581 { 2582 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock; 2583 struct drm_rect src; 2584 2585 /* 2586 * We only use IF-ID interlacing. If we ever use 2587 * PF-ID we'll need to adjust the pixel_rate here. 2588 */ 2589 2590 if (!crtc_state->pch_pfit.enabled) 2591 return pixel_rate; 2592 2593 drm_rect_init(&src, 0, 0, 2594 drm_rect_width(&crtc_state->pipe_src) << 16, 2595 drm_rect_height(&crtc_state->pipe_src) << 16); 2596 2597 return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst, 2598 pixel_rate); 2599 } 2600 2601 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode, 2602 const struct drm_display_mode *timings) 2603 { 2604 mode->hdisplay = timings->crtc_hdisplay; 2605 mode->htotal = timings->crtc_htotal; 2606 mode->hsync_start = timings->crtc_hsync_start; 2607 mode->hsync_end = timings->crtc_hsync_end; 2608 2609 mode->vdisplay = timings->crtc_vdisplay; 2610 mode->vtotal = timings->crtc_vtotal; 2611 mode->vsync_start = timings->crtc_vsync_start; 2612 mode->vsync_end = timings->crtc_vsync_end; 2613 2614 mode->flags = timings->flags; 2615 mode->type = DRM_MODE_TYPE_DRIVER; 2616 2617 mode->clock = timings->crtc_clock; 2618 2619 drm_mode_set_name(mode); 2620 } 2621 2622 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) 2623 { 2624 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2625 2626 if (HAS_GMCH(dev_priv)) 2627 /* FIXME calculate proper pipe pixel rate for GMCH pfit */ 2628 crtc_state->pixel_rate = 2629 crtc_state->hw.pipe_mode.crtc_clock; 2630 else 2631 crtc_state->pixel_rate = 2632 ilk_pipe_pixel_rate(crtc_state); 2633 } 2634 2635 static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state *crtc_state, 2636 struct drm_display_mode *mode) 2637 { 2638 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2639 2640 if (num_pipes < 2) 2641 return; 2642 2643 mode->crtc_clock /= num_pipes; 2644 mode->crtc_hdisplay /= num_pipes; 2645 mode->crtc_hblank_start /= num_pipes; 2646 mode->crtc_hblank_end /= num_pipes; 2647 mode->crtc_hsync_start /= num_pipes; 2648 mode->crtc_hsync_end /= num_pipes; 2649 mode->crtc_htotal /= num_pipes; 2650 } 2651 2652 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state, 2653 struct drm_display_mode *mode) 2654 { 2655 int overlap = crtc_state->splitter.pixel_overlap; 2656 int n = crtc_state->splitter.link_count; 2657 2658 if (!crtc_state->splitter.enable) 2659 return; 2660 2661 /* 2662 * eDP MSO uses segment timings from EDID for transcoder 2663 * timings, but full mode for everything else. 2664 * 2665 * h_full = (h_segment - pixel_overlap) * link_count 2666 */ 2667 mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n; 2668 mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n; 2669 mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n; 2670 mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n; 2671 mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n; 2672 mode->crtc_htotal = (mode->crtc_htotal - overlap) * n; 2673 mode->crtc_clock *= n; 2674 } 2675 2676 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state) 2677 { 2678 struct drm_display_mode *mode = &crtc_state->hw.mode; 2679 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2680 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2681 2682 /* 2683 * Start with the adjusted_mode crtc timings, which 2684 * have been filled with the transcoder timings. 2685 */ 2686 drm_mode_copy(pipe_mode, adjusted_mode); 2687 2688 /* Expand MSO per-segment transcoder timings to full */ 2689 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2690 2691 /* 2692 * We want the full numbers in adjusted_mode normal timings, 2693 * adjusted_mode crtc timings are left with the raw transcoder 2694 * timings. 2695 */ 2696 intel_mode_from_crtc_timings(adjusted_mode, pipe_mode); 2697 2698 /* Populate the "user" mode with full numbers */ 2699 drm_mode_copy(mode, pipe_mode); 2700 intel_mode_from_crtc_timings(mode, mode); 2701 mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) * 2702 (intel_bigjoiner_num_pipes(crtc_state) ?: 1); 2703 mode->vdisplay = drm_rect_height(&crtc_state->pipe_src); 2704 2705 /* Derive per-pipe timings in case bigjoiner is used */ 2706 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2707 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2708 2709 intel_crtc_compute_pixel_rate(crtc_state); 2710 } 2711 2712 static void intel_encoder_get_config(struct intel_encoder *encoder, 2713 struct intel_crtc_state *crtc_state) 2714 { 2715 encoder->get_config(encoder, crtc_state); 2716 2717 intel_crtc_readout_derived_state(crtc_state); 2718 } 2719 2720 static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state *crtc_state) 2721 { 2722 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2723 int width, height; 2724 2725 if (num_pipes < 2) 2726 return; 2727 2728 width = drm_rect_width(&crtc_state->pipe_src); 2729 height = drm_rect_height(&crtc_state->pipe_src); 2730 2731 drm_rect_init(&crtc_state->pipe_src, 0, 0, 2732 width / num_pipes, height); 2733 } 2734 2735 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state) 2736 { 2737 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2738 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2739 2740 intel_bigjoiner_compute_pipe_src(crtc_state); 2741 2742 /* 2743 * Pipe horizontal size must be even in: 2744 * - DVO ganged mode 2745 * - LVDS dual channel mode 2746 * - Double wide pipe 2747 */ 2748 if (drm_rect_width(&crtc_state->pipe_src) & 1) { 2749 if (crtc_state->double_wide) { 2750 drm_dbg_kms(&i915->drm, 2751 "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n", 2752 crtc->base.base.id, crtc->base.name); 2753 return -EINVAL; 2754 } 2755 2756 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 2757 intel_is_dual_link_lvds(i915)) { 2758 drm_dbg_kms(&i915->drm, 2759 "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n", 2760 crtc->base.base.id, crtc->base.name); 2761 return -EINVAL; 2762 } 2763 } 2764 2765 return 0; 2766 } 2767 2768 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state) 2769 { 2770 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2771 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2772 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2773 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2774 int clock_limit = i915->max_dotclk_freq; 2775 2776 /* 2777 * Start with the adjusted_mode crtc timings, which 2778 * have been filled with the transcoder timings. 2779 */ 2780 drm_mode_copy(pipe_mode, adjusted_mode); 2781 2782 /* Expand MSO per-segment transcoder timings to full */ 2783 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2784 2785 /* Derive per-pipe timings in case bigjoiner is used */ 2786 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2787 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2788 2789 if (DISPLAY_VER(i915) < 4) { 2790 clock_limit = i915->max_cdclk_freq * 9 / 10; 2791 2792 /* 2793 * Enable double wide mode when the dot clock 2794 * is > 90% of the (display) core speed. 2795 */ 2796 if (intel_crtc_supports_double_wide(crtc) && 2797 pipe_mode->crtc_clock > clock_limit) { 2798 clock_limit = i915->max_dotclk_freq; 2799 crtc_state->double_wide = true; 2800 } 2801 } 2802 2803 if (pipe_mode->crtc_clock > clock_limit) { 2804 drm_dbg_kms(&i915->drm, 2805 "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", 2806 crtc->base.base.id, crtc->base.name, 2807 pipe_mode->crtc_clock, clock_limit, 2808 str_yes_no(crtc_state->double_wide)); 2809 return -EINVAL; 2810 } 2811 2812 return 0; 2813 } 2814 2815 static int intel_crtc_compute_config(struct intel_atomic_state *state, 2816 struct intel_crtc *crtc) 2817 { 2818 struct intel_crtc_state *crtc_state = 2819 intel_atomic_get_new_crtc_state(state, crtc); 2820 int ret; 2821 2822 ret = intel_crtc_compute_pipe_src(crtc_state); 2823 if (ret) 2824 return ret; 2825 2826 ret = intel_crtc_compute_pipe_mode(crtc_state); 2827 if (ret) 2828 return ret; 2829 2830 intel_crtc_compute_pixel_rate(crtc_state); 2831 2832 if (crtc_state->has_pch_encoder) 2833 return ilk_fdi_compute_config(crtc, crtc_state); 2834 2835 return 0; 2836 } 2837 2838 static void 2839 intel_reduce_m_n_ratio(u32 *num, u32 *den) 2840 { 2841 while (*num > DATA_LINK_M_N_MASK || 2842 *den > DATA_LINK_M_N_MASK) { 2843 *num >>= 1; 2844 *den >>= 1; 2845 } 2846 } 2847 2848 static void compute_m_n(unsigned int m, unsigned int n, 2849 u32 *ret_m, u32 *ret_n, 2850 bool constant_n) 2851 { 2852 /* 2853 * Several DP dongles in particular seem to be fussy about 2854 * too large link M/N values. Give N value as 0x8000 that 2855 * should be acceptable by specific devices. 0x8000 is the 2856 * specified fixed N value for asynchronous clock mode, 2857 * which the devices expect also in synchronous clock mode. 2858 */ 2859 if (constant_n) 2860 *ret_n = DP_LINK_CONSTANT_N_VALUE; 2861 else 2862 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); 2863 2864 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n); 2865 intel_reduce_m_n_ratio(ret_m, ret_n); 2866 } 2867 2868 void 2869 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes, 2870 int pixel_clock, int link_clock, 2871 struct intel_link_m_n *m_n, 2872 bool constant_n, bool fec_enable) 2873 { 2874 u32 data_clock = bits_per_pixel * pixel_clock; 2875 2876 if (fec_enable) 2877 data_clock = intel_dp_mode_to_fec_clock(data_clock); 2878 2879 m_n->tu = 64; 2880 compute_m_n(data_clock, 2881 link_clock * nlanes * 8, 2882 &m_n->data_m, &m_n->data_n, 2883 constant_n); 2884 2885 compute_m_n(pixel_clock, link_clock, 2886 &m_n->link_m, &m_n->link_n, 2887 constant_n); 2888 } 2889 2890 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv) 2891 { 2892 /* 2893 * There may be no VBT; and if the BIOS enabled SSC we can 2894 * just keep using it to avoid unnecessary flicker. Whereas if the 2895 * BIOS isn't using it, don't assume it will work even if the VBT 2896 * indicates as much. 2897 */ 2898 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { 2899 bool bios_lvds_use_ssc = intel_de_read(dev_priv, 2900 PCH_DREF_CONTROL) & 2901 DREF_SSC1_ENABLE; 2902 2903 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { 2904 drm_dbg_kms(&dev_priv->drm, 2905 "SSC %s by BIOS, overriding VBT which says %s\n", 2906 str_enabled_disabled(bios_lvds_use_ssc), 2907 str_enabled_disabled(dev_priv->vbt.lvds_use_ssc)); 2908 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; 2909 } 2910 } 2911 } 2912 2913 void intel_zero_m_n(struct intel_link_m_n *m_n) 2914 { 2915 /* corresponds to 0 register value */ 2916 memset(m_n, 0, sizeof(*m_n)); 2917 m_n->tu = 1; 2918 } 2919 2920 void intel_set_m_n(struct drm_i915_private *i915, 2921 const struct intel_link_m_n *m_n, 2922 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 2923 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 2924 { 2925 intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); 2926 intel_de_write(i915, data_n_reg, m_n->data_n); 2927 intel_de_write(i915, link_m_reg, m_n->link_m); 2928 /* 2929 * On BDW+ writing LINK_N arms the double buffered update 2930 * of all the M/N registers, so it must be written last. 2931 */ 2932 intel_de_write(i915, link_n_reg, m_n->link_n); 2933 } 2934 2935 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, 2936 enum transcoder transcoder) 2937 { 2938 if (IS_HASWELL(dev_priv)) 2939 return transcoder == TRANSCODER_EDP; 2940 2941 return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv); 2942 } 2943 2944 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, 2945 enum transcoder transcoder, 2946 const struct intel_link_m_n *m_n) 2947 { 2948 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2949 enum pipe pipe = crtc->pipe; 2950 2951 if (DISPLAY_VER(dev_priv) >= 5) 2952 intel_set_m_n(dev_priv, m_n, 2953 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 2954 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 2955 else 2956 intel_set_m_n(dev_priv, m_n, 2957 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 2958 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 2959 } 2960 2961 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, 2962 enum transcoder transcoder, 2963 const struct intel_link_m_n *m_n) 2964 { 2965 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2966 2967 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 2968 return; 2969 2970 intel_set_m_n(dev_priv, m_n, 2971 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 2972 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 2973 } 2974 2975 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) 2976 { 2977 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2978 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2979 enum pipe pipe = crtc->pipe; 2980 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2981 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2982 u32 crtc_vtotal, crtc_vblank_end; 2983 int vsyncshift = 0; 2984 2985 /* We need to be careful not to changed the adjusted mode, for otherwise 2986 * the hw state checker will get angry at the mismatch. */ 2987 crtc_vtotal = adjusted_mode->crtc_vtotal; 2988 crtc_vblank_end = adjusted_mode->crtc_vblank_end; 2989 2990 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 2991 /* the chip adds 2 halflines automatically */ 2992 crtc_vtotal -= 1; 2993 crtc_vblank_end -= 1; 2994 2995 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 2996 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; 2997 else 2998 vsyncshift = adjusted_mode->crtc_hsync_start - 2999 adjusted_mode->crtc_htotal / 2; 3000 if (vsyncshift < 0) 3001 vsyncshift += adjusted_mode->crtc_htotal; 3002 } 3003 3004 if (DISPLAY_VER(dev_priv) > 3) 3005 intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder), 3006 vsyncshift); 3007 3008 intel_de_write(dev_priv, HTOTAL(cpu_transcoder), 3009 (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16)); 3010 intel_de_write(dev_priv, HBLANK(cpu_transcoder), 3011 (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16)); 3012 intel_de_write(dev_priv, HSYNC(cpu_transcoder), 3013 (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16)); 3014 3015 intel_de_write(dev_priv, VTOTAL(cpu_transcoder), 3016 (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16)); 3017 intel_de_write(dev_priv, VBLANK(cpu_transcoder), 3018 (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16)); 3019 intel_de_write(dev_priv, VSYNC(cpu_transcoder), 3020 (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16)); 3021 3022 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be 3023 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is 3024 * documented on the DDI_FUNC_CTL register description, EDP Input Select 3025 * bits. */ 3026 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && 3027 (pipe == PIPE_B || pipe == PIPE_C)) 3028 intel_de_write(dev_priv, VTOTAL(pipe), 3029 intel_de_read(dev_priv, VTOTAL(cpu_transcoder))); 3030 3031 } 3032 3033 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) 3034 { 3035 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3036 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3037 int width = drm_rect_width(&crtc_state->pipe_src); 3038 int height = drm_rect_height(&crtc_state->pipe_src); 3039 enum pipe pipe = crtc->pipe; 3040 3041 /* pipesrc controls the size that is scaled from, which should 3042 * always be the user's requested size. 3043 */ 3044 intel_de_write(dev_priv, PIPESRC(pipe), 3045 PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1)); 3046 } 3047 3048 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) 3049 { 3050 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3051 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3052 3053 if (DISPLAY_VER(dev_priv) == 2) 3054 return false; 3055 3056 if (DISPLAY_VER(dev_priv) >= 9 || 3057 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 3058 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW; 3059 else 3060 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK; 3061 } 3062 3063 static void intel_get_transcoder_timings(struct intel_crtc *crtc, 3064 struct intel_crtc_state *pipe_config) 3065 { 3066 struct drm_device *dev = crtc->base.dev; 3067 struct drm_i915_private *dev_priv = to_i915(dev); 3068 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3069 u32 tmp; 3070 3071 tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder)); 3072 pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; 3073 pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; 3074 3075 if (!transcoder_is_dsi(cpu_transcoder)) { 3076 tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder)); 3077 pipe_config->hw.adjusted_mode.crtc_hblank_start = 3078 (tmp & 0xffff) + 1; 3079 pipe_config->hw.adjusted_mode.crtc_hblank_end = 3080 ((tmp >> 16) & 0xffff) + 1; 3081 } 3082 tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder)); 3083 pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; 3084 pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; 3085 3086 tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder)); 3087 pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; 3088 pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; 3089 3090 if (!transcoder_is_dsi(cpu_transcoder)) { 3091 tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder)); 3092 pipe_config->hw.adjusted_mode.crtc_vblank_start = 3093 (tmp & 0xffff) + 1; 3094 pipe_config->hw.adjusted_mode.crtc_vblank_end = 3095 ((tmp >> 16) & 0xffff) + 1; 3096 } 3097 tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder)); 3098 pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; 3099 pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; 3100 3101 if (intel_pipe_is_interlaced(pipe_config)) { 3102 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; 3103 pipe_config->hw.adjusted_mode.crtc_vtotal += 1; 3104 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1; 3105 } 3106 } 3107 3108 static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state) 3109 { 3110 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3111 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 3112 enum pipe master_pipe, pipe = crtc->pipe; 3113 int width; 3114 3115 if (num_pipes < 2) 3116 return; 3117 3118 master_pipe = bigjoiner_master_pipe(crtc_state); 3119 width = drm_rect_width(&crtc_state->pipe_src); 3120 3121 drm_rect_translate_to(&crtc_state->pipe_src, 3122 (pipe - master_pipe) * width, 0); 3123 } 3124 3125 static void intel_get_pipe_src_size(struct intel_crtc *crtc, 3126 struct intel_crtc_state *pipe_config) 3127 { 3128 struct drm_device *dev = crtc->base.dev; 3129 struct drm_i915_private *dev_priv = to_i915(dev); 3130 u32 tmp; 3131 3132 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe)); 3133 3134 drm_rect_init(&pipe_config->pipe_src, 0, 0, 3135 REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1, 3136 REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1); 3137 3138 intel_bigjoiner_adjust_pipe_src(pipe_config); 3139 } 3140 3141 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) 3142 { 3143 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3144 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3145 u32 pipeconf = 0; 3146 3147 /* we keep both pipes enabled on 830 */ 3148 if (IS_I830(dev_priv)) 3149 pipeconf |= PIPECONF_ENABLE; 3150 3151 if (crtc_state->double_wide) 3152 pipeconf |= PIPECONF_DOUBLE_WIDE; 3153 3154 /* only g4x and later have fancy bpc/dither controls */ 3155 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 3156 IS_CHERRYVIEW(dev_priv)) { 3157 /* Bspec claims that we can't use dithering for 30bpp pipes. */ 3158 if (crtc_state->dither && crtc_state->pipe_bpp != 30) 3159 pipeconf |= PIPECONF_DITHER_EN | 3160 PIPECONF_DITHER_TYPE_SP; 3161 3162 switch (crtc_state->pipe_bpp) { 3163 default: 3164 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3165 MISSING_CASE(crtc_state->pipe_bpp); 3166 fallthrough; 3167 case 18: 3168 pipeconf |= PIPECONF_BPC_6; 3169 break; 3170 case 24: 3171 pipeconf |= PIPECONF_BPC_8; 3172 break; 3173 case 30: 3174 pipeconf |= PIPECONF_BPC_10; 3175 break; 3176 } 3177 } 3178 3179 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 3180 if (DISPLAY_VER(dev_priv) < 4 || 3181 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3182 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; 3183 else 3184 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; 3185 } else { 3186 pipeconf |= PIPECONF_INTERLACE_PROGRESSIVE; 3187 } 3188 3189 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 3190 crtc_state->limited_color_range) 3191 pipeconf |= PIPECONF_COLOR_RANGE_SELECT; 3192 3193 pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); 3194 3195 pipeconf |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3196 3197 intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf); 3198 intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe)); 3199 } 3200 3201 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv) 3202 { 3203 if (IS_I830(dev_priv)) 3204 return false; 3205 3206 return DISPLAY_VER(dev_priv) >= 4 || 3207 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); 3208 } 3209 3210 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state) 3211 { 3212 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3213 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3214 u32 tmp; 3215 3216 if (!i9xx_has_pfit(dev_priv)) 3217 return; 3218 3219 tmp = intel_de_read(dev_priv, PFIT_CONTROL); 3220 if (!(tmp & PFIT_ENABLE)) 3221 return; 3222 3223 /* Check whether the pfit is attached to our pipe. */ 3224 if (DISPLAY_VER(dev_priv) < 4) { 3225 if (crtc->pipe != PIPE_B) 3226 return; 3227 } else { 3228 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) 3229 return; 3230 } 3231 3232 crtc_state->gmch_pfit.control = tmp; 3233 crtc_state->gmch_pfit.pgm_ratios = 3234 intel_de_read(dev_priv, PFIT_PGM_RATIOS); 3235 } 3236 3237 static void vlv_crtc_clock_get(struct intel_crtc *crtc, 3238 struct intel_crtc_state *pipe_config) 3239 { 3240 struct drm_device *dev = crtc->base.dev; 3241 struct drm_i915_private *dev_priv = to_i915(dev); 3242 enum pipe pipe = crtc->pipe; 3243 struct dpll clock; 3244 u32 mdiv; 3245 int refclk = 100000; 3246 3247 /* In case of DSI, DPLL will not be used */ 3248 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 3249 return; 3250 3251 vlv_dpio_get(dev_priv); 3252 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); 3253 vlv_dpio_put(dev_priv); 3254 3255 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; 3256 clock.m2 = mdiv & DPIO_M2DIV_MASK; 3257 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; 3258 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; 3259 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; 3260 3261 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); 3262 } 3263 3264 static void chv_crtc_clock_get(struct intel_crtc *crtc, 3265 struct intel_crtc_state *pipe_config) 3266 { 3267 struct drm_device *dev = crtc->base.dev; 3268 struct drm_i915_private *dev_priv = to_i915(dev); 3269 enum pipe pipe = crtc->pipe; 3270 enum dpio_channel port = vlv_pipe_to_channel(pipe); 3271 struct dpll clock; 3272 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; 3273 int refclk = 100000; 3274 3275 /* In case of DSI, DPLL will not be used */ 3276 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 3277 return; 3278 3279 vlv_dpio_get(dev_priv); 3280 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); 3281 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); 3282 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); 3283 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); 3284 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); 3285 vlv_dpio_put(dev_priv); 3286 3287 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; 3288 clock.m2 = (pll_dw0 & 0xff) << 22; 3289 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) 3290 clock.m2 |= pll_dw2 & 0x3fffff; 3291 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; 3292 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; 3293 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; 3294 3295 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); 3296 } 3297 3298 static enum intel_output_format 3299 bdw_get_pipemisc_output_format(struct intel_crtc *crtc) 3300 { 3301 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3302 u32 tmp; 3303 3304 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); 3305 3306 if (tmp & PIPEMISC_YUV420_ENABLE) { 3307 /* We support 4:2:0 in full blend mode only */ 3308 drm_WARN_ON(&dev_priv->drm, 3309 (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0); 3310 3311 return INTEL_OUTPUT_FORMAT_YCBCR420; 3312 } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) { 3313 return INTEL_OUTPUT_FORMAT_YCBCR444; 3314 } else { 3315 return INTEL_OUTPUT_FORMAT_RGB; 3316 } 3317 } 3318 3319 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state) 3320 { 3321 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3322 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 3323 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3324 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 3325 u32 tmp; 3326 3327 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); 3328 3329 if (tmp & DISP_PIPE_GAMMA_ENABLE) 3330 crtc_state->gamma_enable = true; 3331 3332 if (!HAS_GMCH(dev_priv) && 3333 tmp & DISP_PIPE_CSC_ENABLE) 3334 crtc_state->csc_enable = true; 3335 } 3336 3337 static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 3338 struct intel_crtc_state *pipe_config) 3339 { 3340 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3341 enum intel_display_power_domain power_domain; 3342 intel_wakeref_t wakeref; 3343 u32 tmp; 3344 bool ret; 3345 3346 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3347 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3348 if (!wakeref) 3349 return false; 3350 3351 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3352 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3353 pipe_config->shared_dpll = NULL; 3354 3355 ret = false; 3356 3357 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); 3358 if (!(tmp & PIPECONF_ENABLE)) 3359 goto out; 3360 3361 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 3362 IS_CHERRYVIEW(dev_priv)) { 3363 switch (tmp & PIPECONF_BPC_MASK) { 3364 case PIPECONF_BPC_6: 3365 pipe_config->pipe_bpp = 18; 3366 break; 3367 case PIPECONF_BPC_8: 3368 pipe_config->pipe_bpp = 24; 3369 break; 3370 case PIPECONF_BPC_10: 3371 pipe_config->pipe_bpp = 30; 3372 break; 3373 default: 3374 MISSING_CASE(tmp); 3375 break; 3376 } 3377 } 3378 3379 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 3380 (tmp & PIPECONF_COLOR_RANGE_SELECT)) 3381 pipe_config->limited_color_range = true; 3382 3383 pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_I9XX, tmp); 3384 3385 pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1; 3386 3387 if (IS_CHERRYVIEW(dev_priv)) 3388 pipe_config->cgm_mode = intel_de_read(dev_priv, 3389 CGM_PIPE_MODE(crtc->pipe)); 3390 3391 i9xx_get_pipe_color_config(pipe_config); 3392 intel_color_get_config(pipe_config); 3393 3394 if (DISPLAY_VER(dev_priv) < 4) 3395 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; 3396 3397 intel_get_transcoder_timings(crtc, pipe_config); 3398 intel_get_pipe_src_size(crtc, pipe_config); 3399 3400 i9xx_get_pfit_config(pipe_config); 3401 3402 if (DISPLAY_VER(dev_priv) >= 4) { 3403 /* No way to read it out on pipes B and C */ 3404 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) 3405 tmp = dev_priv->chv_dpll_md[crtc->pipe]; 3406 else 3407 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe)); 3408 pipe_config->pixel_multiplier = 3409 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) 3410 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; 3411 pipe_config->dpll_hw_state.dpll_md = tmp; 3412 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 3413 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 3414 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe)); 3415 pipe_config->pixel_multiplier = 3416 ((tmp & SDVO_MULTIPLIER_MASK) 3417 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; 3418 } else { 3419 /* Note that on i915G/GM the pixel multiplier is in the sdvo 3420 * port and will be fixed up in the encoder->get_config 3421 * function. */ 3422 pipe_config->pixel_multiplier = 1; 3423 } 3424 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv, 3425 DPLL(crtc->pipe)); 3426 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 3427 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv, 3428 FP0(crtc->pipe)); 3429 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv, 3430 FP1(crtc->pipe)); 3431 } else { 3432 /* Mask out read-only status bits. */ 3433 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | 3434 DPLL_PORTC_READY_MASK | 3435 DPLL_PORTB_READY_MASK); 3436 } 3437 3438 if (IS_CHERRYVIEW(dev_priv)) 3439 chv_crtc_clock_get(crtc, pipe_config); 3440 else if (IS_VALLEYVIEW(dev_priv)) 3441 vlv_crtc_clock_get(crtc, pipe_config); 3442 else 3443 i9xx_crtc_clock_get(crtc, pipe_config); 3444 3445 /* 3446 * Normally the dotclock is filled in by the encoder .get_config() 3447 * but in case the pipe is enabled w/o any ports we need a sane 3448 * default. 3449 */ 3450 pipe_config->hw.adjusted_mode.crtc_clock = 3451 pipe_config->port_clock / pipe_config->pixel_multiplier; 3452 3453 ret = true; 3454 3455 out: 3456 intel_display_power_put(dev_priv, power_domain, wakeref); 3457 3458 return ret; 3459 } 3460 3461 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) 3462 { 3463 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3464 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3465 enum pipe pipe = crtc->pipe; 3466 u32 val; 3467 3468 val = 0; 3469 3470 switch (crtc_state->pipe_bpp) { 3471 default: 3472 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3473 MISSING_CASE(crtc_state->pipe_bpp); 3474 fallthrough; 3475 case 18: 3476 val |= PIPECONF_BPC_6; 3477 break; 3478 case 24: 3479 val |= PIPECONF_BPC_8; 3480 break; 3481 case 30: 3482 val |= PIPECONF_BPC_10; 3483 break; 3484 case 36: 3485 val |= PIPECONF_BPC_12; 3486 break; 3487 } 3488 3489 if (crtc_state->dither) 3490 val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP; 3491 3492 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3493 val |= PIPECONF_INTERLACE_IF_ID_ILK; 3494 else 3495 val |= PIPECONF_INTERLACE_PF_PD_ILK; 3496 3497 /* 3498 * This would end up with an odd purple hue over 3499 * the entire display. Make sure we don't do it. 3500 */ 3501 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 3502 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 3503 3504 if (crtc_state->limited_color_range && 3505 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3506 val |= PIPECONF_COLOR_RANGE_SELECT; 3507 3508 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3509 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709; 3510 3511 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); 3512 3513 val |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3514 val |= PIPECONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay); 3515 3516 intel_de_write(dev_priv, PIPECONF(pipe), val); 3517 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 3518 } 3519 3520 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) 3521 { 3522 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3523 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3524 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3525 u32 val = 0; 3526 3527 if (IS_HASWELL(dev_priv) && crtc_state->dither) 3528 val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP; 3529 3530 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3531 val |= PIPECONF_INTERLACE_IF_ID_ILK; 3532 else 3533 val |= PIPECONF_INTERLACE_PF_PD_ILK; 3534 3535 if (IS_HASWELL(dev_priv) && 3536 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3537 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW; 3538 3539 intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val); 3540 intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder)); 3541 } 3542 3543 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) 3544 { 3545 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3546 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3547 u32 val = 0; 3548 3549 switch (crtc_state->pipe_bpp) { 3550 case 18: 3551 val |= PIPEMISC_BPC_6; 3552 break; 3553 case 24: 3554 val |= PIPEMISC_BPC_8; 3555 break; 3556 case 30: 3557 val |= PIPEMISC_BPC_10; 3558 break; 3559 case 36: 3560 /* Port output 12BPC defined for ADLP+ */ 3561 if (DISPLAY_VER(dev_priv) > 12) 3562 val |= PIPEMISC_BPC_12_ADLP; 3563 break; 3564 default: 3565 MISSING_CASE(crtc_state->pipe_bpp); 3566 break; 3567 } 3568 3569 if (crtc_state->dither) 3570 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; 3571 3572 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 3573 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 3574 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV; 3575 3576 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 3577 val |= PIPEMISC_YUV420_ENABLE | 3578 PIPEMISC_YUV420_MODE_FULL_BLEND; 3579 3580 if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state)) 3581 val |= PIPEMISC_HDR_MODE_PRECISION; 3582 3583 if (DISPLAY_VER(dev_priv) >= 12) 3584 val |= PIPEMISC_PIXEL_ROUNDING_TRUNC; 3585 3586 intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val); 3587 } 3588 3589 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) 3590 { 3591 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3592 u32 tmp; 3593 3594 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); 3595 3596 switch (tmp & PIPEMISC_BPC_MASK) { 3597 case PIPEMISC_BPC_6: 3598 return 18; 3599 case PIPEMISC_BPC_8: 3600 return 24; 3601 case PIPEMISC_BPC_10: 3602 return 30; 3603 /* 3604 * PORT OUTPUT 12 BPC defined for ADLP+. 3605 * 3606 * TODO: 3607 * For previous platforms with DSI interface, bits 5:7 3608 * are used for storing pipe_bpp irrespective of dithering. 3609 * Since the value of 12 BPC is not defined for these bits 3610 * on older platforms, need to find a workaround for 12 BPC 3611 * MIPI DSI HW readout. 3612 */ 3613 case PIPEMISC_BPC_12_ADLP: 3614 if (DISPLAY_VER(dev_priv) > 12) 3615 return 36; 3616 fallthrough; 3617 default: 3618 MISSING_CASE(tmp); 3619 return 0; 3620 } 3621 } 3622 3623 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) 3624 { 3625 /* 3626 * Account for spread spectrum to avoid 3627 * oversubscribing the link. Max center spread 3628 * is 2.5%; use 5% for safety's sake. 3629 */ 3630 u32 bps = target_clock * bpp * 21 / 20; 3631 return DIV_ROUND_UP(bps, link_bw * 8); 3632 } 3633 3634 void intel_get_m_n(struct drm_i915_private *i915, 3635 struct intel_link_m_n *m_n, 3636 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 3637 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 3638 { 3639 m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK; 3640 m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK; 3641 m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK; 3642 m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK; 3643 m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1; 3644 } 3645 3646 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, 3647 enum transcoder transcoder, 3648 struct intel_link_m_n *m_n) 3649 { 3650 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3651 enum pipe pipe = crtc->pipe; 3652 3653 if (DISPLAY_VER(dev_priv) >= 5) 3654 intel_get_m_n(dev_priv, m_n, 3655 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 3656 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 3657 else 3658 intel_get_m_n(dev_priv, m_n, 3659 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 3660 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 3661 } 3662 3663 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, 3664 enum transcoder transcoder, 3665 struct intel_link_m_n *m_n) 3666 { 3667 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3668 3669 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 3670 return; 3671 3672 intel_get_m_n(dev_priv, m_n, 3673 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 3674 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 3675 } 3676 3677 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state, 3678 u32 pos, u32 size) 3679 { 3680 drm_rect_init(&crtc_state->pch_pfit.dst, 3681 pos >> 16, pos & 0xffff, 3682 size >> 16, size & 0xffff); 3683 } 3684 3685 static void skl_get_pfit_config(struct intel_crtc_state *crtc_state) 3686 { 3687 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3688 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3689 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; 3690 int id = -1; 3691 int i; 3692 3693 /* find scaler attached to this pipe */ 3694 for (i = 0; i < crtc->num_scalers; i++) { 3695 u32 ctl, pos, size; 3696 3697 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i)); 3698 if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN) 3699 continue; 3700 3701 id = i; 3702 crtc_state->pch_pfit.enabled = true; 3703 3704 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i)); 3705 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i)); 3706 3707 ilk_get_pfit_pos_size(crtc_state, pos, size); 3708 3709 scaler_state->scalers[i].in_use = true; 3710 break; 3711 } 3712 3713 scaler_state->scaler_id = id; 3714 if (id >= 0) 3715 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); 3716 else 3717 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); 3718 } 3719 3720 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state) 3721 { 3722 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3723 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3724 u32 ctl, pos, size; 3725 3726 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe)); 3727 if ((ctl & PF_ENABLE) == 0) 3728 return; 3729 3730 crtc_state->pch_pfit.enabled = true; 3731 3732 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe)); 3733 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe)); 3734 3735 ilk_get_pfit_pos_size(crtc_state, pos, size); 3736 3737 /* 3738 * We currently do not free assignements of panel fitters on 3739 * ivb/hsw (since we don't use the higher upscaling modes which 3740 * differentiates them) so just WARN about this case for now. 3741 */ 3742 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 7 && 3743 (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe)); 3744 } 3745 3746 static bool ilk_get_pipe_config(struct intel_crtc *crtc, 3747 struct intel_crtc_state *pipe_config) 3748 { 3749 struct drm_device *dev = crtc->base.dev; 3750 struct drm_i915_private *dev_priv = to_i915(dev); 3751 enum intel_display_power_domain power_domain; 3752 intel_wakeref_t wakeref; 3753 u32 tmp; 3754 bool ret; 3755 3756 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3757 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3758 if (!wakeref) 3759 return false; 3760 3761 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3762 pipe_config->shared_dpll = NULL; 3763 3764 ret = false; 3765 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); 3766 if (!(tmp & PIPECONF_ENABLE)) 3767 goto out; 3768 3769 switch (tmp & PIPECONF_BPC_MASK) { 3770 case PIPECONF_BPC_6: 3771 pipe_config->pipe_bpp = 18; 3772 break; 3773 case PIPECONF_BPC_8: 3774 pipe_config->pipe_bpp = 24; 3775 break; 3776 case PIPECONF_BPC_10: 3777 pipe_config->pipe_bpp = 30; 3778 break; 3779 case PIPECONF_BPC_12: 3780 pipe_config->pipe_bpp = 36; 3781 break; 3782 default: 3783 break; 3784 } 3785 3786 if (tmp & PIPECONF_COLOR_RANGE_SELECT) 3787 pipe_config->limited_color_range = true; 3788 3789 switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) { 3790 case PIPECONF_OUTPUT_COLORSPACE_YUV601: 3791 case PIPECONF_OUTPUT_COLORSPACE_YUV709: 3792 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3793 break; 3794 default: 3795 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3796 break; 3797 } 3798 3799 pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_ILK, tmp); 3800 3801 pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1; 3802 3803 pipe_config->msa_timing_delay = REG_FIELD_GET(PIPECONF_MSA_TIMING_DELAY_MASK, tmp); 3804 3805 pipe_config->csc_mode = intel_de_read(dev_priv, 3806 PIPE_CSC_MODE(crtc->pipe)); 3807 3808 i9xx_get_pipe_color_config(pipe_config); 3809 intel_color_get_config(pipe_config); 3810 3811 pipe_config->pixel_multiplier = 1; 3812 3813 ilk_pch_get_config(pipe_config); 3814 3815 intel_get_transcoder_timings(crtc, pipe_config); 3816 intel_get_pipe_src_size(crtc, pipe_config); 3817 3818 ilk_get_pfit_config(pipe_config); 3819 3820 ret = true; 3821 3822 out: 3823 intel_display_power_put(dev_priv, power_domain, wakeref); 3824 3825 return ret; 3826 } 3827 3828 static u8 bigjoiner_pipes(struct drm_i915_private *i915) 3829 { 3830 if (DISPLAY_VER(i915) >= 12) 3831 return BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D); 3832 else if (DISPLAY_VER(i915) >= 11) 3833 return BIT(PIPE_B) | BIT(PIPE_C); 3834 else 3835 return 0; 3836 } 3837 3838 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv, 3839 enum transcoder cpu_transcoder) 3840 { 3841 enum intel_display_power_domain power_domain; 3842 intel_wakeref_t wakeref; 3843 u32 tmp = 0; 3844 3845 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3846 3847 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3848 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3849 3850 return tmp & TRANS_DDI_FUNC_ENABLE; 3851 } 3852 3853 static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv, 3854 u8 *master_pipes, u8 *slave_pipes) 3855 { 3856 struct intel_crtc *crtc; 3857 3858 *master_pipes = 0; 3859 *slave_pipes = 0; 3860 3861 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, 3862 bigjoiner_pipes(dev_priv)) { 3863 enum intel_display_power_domain power_domain; 3864 enum pipe pipe = crtc->pipe; 3865 intel_wakeref_t wakeref; 3866 3867 power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe); 3868 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3869 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3870 3871 if (!(tmp & BIG_JOINER_ENABLE)) 3872 continue; 3873 3874 if (tmp & MASTER_BIG_JOINER_ENABLE) 3875 *master_pipes |= BIT(pipe); 3876 else 3877 *slave_pipes |= BIT(pipe); 3878 } 3879 3880 if (DISPLAY_VER(dev_priv) < 13) 3881 continue; 3882 3883 power_domain = POWER_DOMAIN_PIPE(pipe); 3884 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3885 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3886 3887 if (tmp & UNCOMPRESSED_JOINER_MASTER) 3888 *master_pipes |= BIT(pipe); 3889 if (tmp & UNCOMPRESSED_JOINER_SLAVE) 3890 *slave_pipes |= BIT(pipe); 3891 } 3892 } 3893 3894 /* Bigjoiner pipes should always be consecutive master and slave */ 3895 drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1, 3896 "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n", 3897 *master_pipes, *slave_pipes); 3898 } 3899 3900 static enum pipe get_bigjoiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3901 { 3902 if ((slave_pipes & BIT(pipe)) == 0) 3903 return pipe; 3904 3905 /* ignore everything above our pipe */ 3906 master_pipes &= ~GENMASK(7, pipe); 3907 3908 /* highest remaining bit should be our master pipe */ 3909 return fls(master_pipes) - 1; 3910 } 3911 3912 static u8 get_bigjoiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3913 { 3914 enum pipe master_pipe, next_master_pipe; 3915 3916 master_pipe = get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes); 3917 3918 if ((master_pipes & BIT(master_pipe)) == 0) 3919 return 0; 3920 3921 /* ignore our master pipe and everything below it */ 3922 master_pipes &= ~GENMASK(master_pipe, 0); 3923 /* make sure a high bit is set for the ffs() */ 3924 master_pipes |= BIT(7); 3925 /* lowest remaining bit should be the next master pipe */ 3926 next_master_pipe = ffs(master_pipes) - 1; 3927 3928 return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe); 3929 } 3930 3931 static u8 hsw_panel_transcoders(struct drm_i915_private *i915) 3932 { 3933 u8 panel_transcoder_mask = BIT(TRANSCODER_EDP); 3934 3935 if (DISPLAY_VER(i915) >= 11) 3936 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); 3937 3938 return panel_transcoder_mask; 3939 } 3940 3941 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) 3942 { 3943 struct drm_device *dev = crtc->base.dev; 3944 struct drm_i915_private *dev_priv = to_i915(dev); 3945 u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv); 3946 enum transcoder cpu_transcoder; 3947 u8 master_pipes, slave_pipes; 3948 u8 enabled_transcoders = 0; 3949 3950 /* 3951 * XXX: Do intel_display_power_get_if_enabled before reading this (for 3952 * consistency and less surprising code; it's in always on power). 3953 */ 3954 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, 3955 panel_transcoder_mask) { 3956 enum intel_display_power_domain power_domain; 3957 intel_wakeref_t wakeref; 3958 enum pipe trans_pipe; 3959 u32 tmp = 0; 3960 3961 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3962 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3963 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3964 3965 if (!(tmp & TRANS_DDI_FUNC_ENABLE)) 3966 continue; 3967 3968 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 3969 default: 3970 drm_WARN(dev, 1, 3971 "unknown pipe linked to transcoder %s\n", 3972 transcoder_name(cpu_transcoder)); 3973 fallthrough; 3974 case TRANS_DDI_EDP_INPUT_A_ONOFF: 3975 case TRANS_DDI_EDP_INPUT_A_ON: 3976 trans_pipe = PIPE_A; 3977 break; 3978 case TRANS_DDI_EDP_INPUT_B_ONOFF: 3979 trans_pipe = PIPE_B; 3980 break; 3981 case TRANS_DDI_EDP_INPUT_C_ONOFF: 3982 trans_pipe = PIPE_C; 3983 break; 3984 case TRANS_DDI_EDP_INPUT_D_ONOFF: 3985 trans_pipe = PIPE_D; 3986 break; 3987 } 3988 3989 if (trans_pipe == crtc->pipe) 3990 enabled_transcoders |= BIT(cpu_transcoder); 3991 } 3992 3993 /* single pipe or bigjoiner master */ 3994 cpu_transcoder = (enum transcoder) crtc->pipe; 3995 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 3996 enabled_transcoders |= BIT(cpu_transcoder); 3997 3998 /* bigjoiner slave -> consider the master pipe's transcoder as well */ 3999 enabled_bigjoiner_pipes(dev_priv, &master_pipes, &slave_pipes); 4000 if (slave_pipes & BIT(crtc->pipe)) { 4001 cpu_transcoder = (enum transcoder) 4002 get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes); 4003 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 4004 enabled_transcoders |= BIT(cpu_transcoder); 4005 } 4006 4007 return enabled_transcoders; 4008 } 4009 4010 static bool has_edp_transcoders(u8 enabled_transcoders) 4011 { 4012 return enabled_transcoders & BIT(TRANSCODER_EDP); 4013 } 4014 4015 static bool has_dsi_transcoders(u8 enabled_transcoders) 4016 { 4017 return enabled_transcoders & (BIT(TRANSCODER_DSI_0) | 4018 BIT(TRANSCODER_DSI_1)); 4019 } 4020 4021 static bool has_pipe_transcoders(u8 enabled_transcoders) 4022 { 4023 return enabled_transcoders & ~(BIT(TRANSCODER_EDP) | 4024 BIT(TRANSCODER_DSI_0) | 4025 BIT(TRANSCODER_DSI_1)); 4026 } 4027 4028 static void assert_enabled_transcoders(struct drm_i915_private *i915, 4029 u8 enabled_transcoders) 4030 { 4031 /* Only one type of transcoder please */ 4032 drm_WARN_ON(&i915->drm, 4033 has_edp_transcoders(enabled_transcoders) + 4034 has_dsi_transcoders(enabled_transcoders) + 4035 has_pipe_transcoders(enabled_transcoders) > 1); 4036 4037 /* Only DSI transcoders can be ganged */ 4038 drm_WARN_ON(&i915->drm, 4039 !has_dsi_transcoders(enabled_transcoders) && 4040 !is_power_of_2(enabled_transcoders)); 4041 } 4042 4043 static bool hsw_get_transcoder_state(struct intel_crtc *crtc, 4044 struct intel_crtc_state *pipe_config, 4045 struct intel_display_power_domain_set *power_domain_set) 4046 { 4047 struct drm_device *dev = crtc->base.dev; 4048 struct drm_i915_private *dev_priv = to_i915(dev); 4049 unsigned long enabled_transcoders; 4050 u32 tmp; 4051 4052 enabled_transcoders = hsw_enabled_transcoders(crtc); 4053 if (!enabled_transcoders) 4054 return false; 4055 4056 assert_enabled_transcoders(dev_priv, enabled_transcoders); 4057 4058 /* 4059 * With the exception of DSI we should only ever have 4060 * a single enabled transcoder. With DSI let's just 4061 * pick the first one. 4062 */ 4063 pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1; 4064 4065 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 4066 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) 4067 return false; 4068 4069 if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) { 4070 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); 4071 4072 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF) 4073 pipe_config->pch_pfit.force_thru = true; 4074 } 4075 4076 tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder)); 4077 4078 return tmp & PIPECONF_ENABLE; 4079 } 4080 4081 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, 4082 struct intel_crtc_state *pipe_config, 4083 struct intel_display_power_domain_set *power_domain_set) 4084 { 4085 struct drm_device *dev = crtc->base.dev; 4086 struct drm_i915_private *dev_priv = to_i915(dev); 4087 enum transcoder cpu_transcoder; 4088 enum port port; 4089 u32 tmp; 4090 4091 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { 4092 if (port == PORT_A) 4093 cpu_transcoder = TRANSCODER_DSI_A; 4094 else 4095 cpu_transcoder = TRANSCODER_DSI_C; 4096 4097 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 4098 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) 4099 continue; 4100 4101 /* 4102 * The PLL needs to be enabled with a valid divider 4103 * configuration, otherwise accessing DSI registers will hang 4104 * the machine. See BSpec North Display Engine 4105 * registers/MIPI[BXT]. We can break out here early, since we 4106 * need the same DSI PLL to be enabled for both DSI ports. 4107 */ 4108 if (!bxt_dsi_pll_is_enabled(dev_priv)) 4109 break; 4110 4111 /* XXX: this works for video mode only */ 4112 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); 4113 if (!(tmp & DPI_ENABLE)) 4114 continue; 4115 4116 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 4117 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) 4118 continue; 4119 4120 pipe_config->cpu_transcoder = cpu_transcoder; 4121 break; 4122 } 4123 4124 return transcoder_is_dsi(pipe_config->cpu_transcoder); 4125 } 4126 4127 static void intel_bigjoiner_get_config(struct intel_crtc_state *crtc_state) 4128 { 4129 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4130 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4131 u8 master_pipes, slave_pipes; 4132 enum pipe pipe = crtc->pipe; 4133 4134 enabled_bigjoiner_pipes(i915, &master_pipes, &slave_pipes); 4135 4136 if (((master_pipes | slave_pipes) & BIT(pipe)) == 0) 4137 return; 4138 4139 crtc_state->bigjoiner_pipes = 4140 BIT(get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes)) | 4141 get_bigjoiner_slave_pipes(pipe, master_pipes, slave_pipes); 4142 } 4143 4144 static bool hsw_get_pipe_config(struct intel_crtc *crtc, 4145 struct intel_crtc_state *pipe_config) 4146 { 4147 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4148 struct intel_display_power_domain_set power_domain_set = { }; 4149 bool active; 4150 u32 tmp; 4151 4152 if (!intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set, 4153 POWER_DOMAIN_PIPE(crtc->pipe))) 4154 return false; 4155 4156 pipe_config->shared_dpll = NULL; 4157 4158 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_set); 4159 4160 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 4161 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_set)) { 4162 drm_WARN_ON(&dev_priv->drm, active); 4163 active = true; 4164 } 4165 4166 if (!active) 4167 goto out; 4168 4169 intel_dsc_get_config(pipe_config); 4170 intel_bigjoiner_get_config(pipe_config); 4171 4172 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || 4173 DISPLAY_VER(dev_priv) >= 11) 4174 intel_get_transcoder_timings(crtc, pipe_config); 4175 4176 if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder)) 4177 intel_vrr_get_config(crtc, pipe_config); 4178 4179 intel_get_pipe_src_size(crtc, pipe_config); 4180 4181 if (IS_HASWELL(dev_priv)) { 4182 u32 tmp = intel_de_read(dev_priv, 4183 PIPECONF(pipe_config->cpu_transcoder)); 4184 4185 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW) 4186 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 4187 else 4188 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 4189 } else { 4190 pipe_config->output_format = 4191 bdw_get_pipemisc_output_format(crtc); 4192 } 4193 4194 pipe_config->gamma_mode = intel_de_read(dev_priv, 4195 GAMMA_MODE(crtc->pipe)); 4196 4197 pipe_config->csc_mode = intel_de_read(dev_priv, 4198 PIPE_CSC_MODE(crtc->pipe)); 4199 4200 if (DISPLAY_VER(dev_priv) >= 9) { 4201 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe)); 4202 4203 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE) 4204 pipe_config->gamma_enable = true; 4205 4206 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE) 4207 pipe_config->csc_enable = true; 4208 } else { 4209 i9xx_get_pipe_color_config(pipe_config); 4210 } 4211 4212 intel_color_get_config(pipe_config); 4213 4214 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe)); 4215 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); 4216 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 4217 pipe_config->ips_linetime = 4218 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); 4219 4220 if (intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set, 4221 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) { 4222 if (DISPLAY_VER(dev_priv) >= 9) 4223 skl_get_pfit_config(pipe_config); 4224 else 4225 ilk_get_pfit_config(pipe_config); 4226 } 4227 4228 hsw_ips_get_config(pipe_config); 4229 4230 if (pipe_config->cpu_transcoder != TRANSCODER_EDP && 4231 !transcoder_is_dsi(pipe_config->cpu_transcoder)) { 4232 pipe_config->pixel_multiplier = 4233 intel_de_read(dev_priv, 4234 PIPE_MULT(pipe_config->cpu_transcoder)) + 1; 4235 } else { 4236 pipe_config->pixel_multiplier = 1; 4237 } 4238 4239 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { 4240 tmp = intel_de_read(dev_priv, CHICKEN_TRANS(pipe_config->cpu_transcoder)); 4241 4242 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1; 4243 } else { 4244 /* no idea if this is correct */ 4245 pipe_config->framestart_delay = 1; 4246 } 4247 4248 out: 4249 intel_display_power_put_all_in_set(dev_priv, &power_domain_set); 4250 4251 return active; 4252 } 4253 4254 static bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state) 4255 { 4256 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4257 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4258 4259 if (!i915->display->get_pipe_config(crtc, crtc_state)) 4260 return false; 4261 4262 crtc_state->hw.active = true; 4263 4264 intel_crtc_readout_derived_state(crtc_state); 4265 4266 return true; 4267 } 4268 4269 /* VESA 640x480x72Hz mode to set on the pipe */ 4270 static const struct drm_display_mode load_detect_mode = { 4271 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, 4272 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 4273 }; 4274 4275 static int intel_modeset_disable_planes(struct drm_atomic_state *state, 4276 struct drm_crtc *crtc) 4277 { 4278 struct drm_plane *plane; 4279 struct drm_plane_state *plane_state; 4280 int ret, i; 4281 4282 ret = drm_atomic_add_affected_planes(state, crtc); 4283 if (ret) 4284 return ret; 4285 4286 for_each_new_plane_in_state(state, plane, plane_state, i) { 4287 if (plane_state->crtc != crtc) 4288 continue; 4289 4290 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL); 4291 if (ret) 4292 return ret; 4293 4294 drm_atomic_set_fb_for_plane(plane_state, NULL); 4295 } 4296 4297 return 0; 4298 } 4299 4300 int intel_get_load_detect_pipe(struct drm_connector *connector, 4301 struct intel_load_detect_pipe *old, 4302 struct drm_modeset_acquire_ctx *ctx) 4303 { 4304 struct intel_encoder *encoder = 4305 intel_attached_encoder(to_intel_connector(connector)); 4306 struct intel_crtc *possible_crtc; 4307 struct intel_crtc *crtc = NULL; 4308 struct drm_device *dev = encoder->base.dev; 4309 struct drm_i915_private *dev_priv = to_i915(dev); 4310 struct drm_mode_config *config = &dev->mode_config; 4311 struct drm_atomic_state *state = NULL, *restore_state = NULL; 4312 struct drm_connector_state *connector_state; 4313 struct intel_crtc_state *crtc_state; 4314 int ret; 4315 4316 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 4317 connector->base.id, connector->name, 4318 encoder->base.base.id, encoder->base.name); 4319 4320 old->restore_state = NULL; 4321 4322 drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex)); 4323 4324 /* 4325 * Algorithm gets a little messy: 4326 * 4327 * - if the connector already has an assigned crtc, use it (but make 4328 * sure it's on first) 4329 * 4330 * - try to find the first unused crtc that can drive this connector, 4331 * and use that if we find one 4332 */ 4333 4334 /* See if we already have a CRTC for this connector */ 4335 if (connector->state->crtc) { 4336 crtc = to_intel_crtc(connector->state->crtc); 4337 4338 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4339 if (ret) 4340 goto fail; 4341 4342 /* Make sure the crtc and connector are running */ 4343 goto found; 4344 } 4345 4346 /* Find an unused one (if possible) */ 4347 for_each_intel_crtc(dev, possible_crtc) { 4348 if (!(encoder->base.possible_crtcs & 4349 drm_crtc_mask(&possible_crtc->base))) 4350 continue; 4351 4352 ret = drm_modeset_lock(&possible_crtc->base.mutex, ctx); 4353 if (ret) 4354 goto fail; 4355 4356 if (possible_crtc->base.state->enable) { 4357 drm_modeset_unlock(&possible_crtc->base.mutex); 4358 continue; 4359 } 4360 4361 crtc = possible_crtc; 4362 break; 4363 } 4364 4365 /* 4366 * If we didn't find an unused CRTC, don't use any. 4367 */ 4368 if (!crtc) { 4369 drm_dbg_kms(&dev_priv->drm, 4370 "no pipe available for load-detect\n"); 4371 ret = -ENODEV; 4372 goto fail; 4373 } 4374 4375 found: 4376 state = drm_atomic_state_alloc(dev); 4377 restore_state = drm_atomic_state_alloc(dev); 4378 if (!state || !restore_state) { 4379 ret = -ENOMEM; 4380 goto fail; 4381 } 4382 4383 state->acquire_ctx = ctx; 4384 restore_state->acquire_ctx = ctx; 4385 4386 connector_state = drm_atomic_get_connector_state(state, connector); 4387 if (IS_ERR(connector_state)) { 4388 ret = PTR_ERR(connector_state); 4389 goto fail; 4390 } 4391 4392 ret = drm_atomic_set_crtc_for_connector(connector_state, &crtc->base); 4393 if (ret) 4394 goto fail; 4395 4396 crtc_state = intel_atomic_get_crtc_state(state, crtc); 4397 if (IS_ERR(crtc_state)) { 4398 ret = PTR_ERR(crtc_state); 4399 goto fail; 4400 } 4401 4402 crtc_state->uapi.active = true; 4403 4404 ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi, 4405 &load_detect_mode); 4406 if (ret) 4407 goto fail; 4408 4409 ret = intel_modeset_disable_planes(state, &crtc->base); 4410 if (ret) 4411 goto fail; 4412 4413 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); 4414 if (!ret) 4415 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, &crtc->base)); 4416 if (!ret) 4417 ret = drm_atomic_add_affected_planes(restore_state, &crtc->base); 4418 if (ret) { 4419 drm_dbg_kms(&dev_priv->drm, 4420 "Failed to create a copy of old state to restore: %i\n", 4421 ret); 4422 goto fail; 4423 } 4424 4425 ret = drm_atomic_commit(state); 4426 if (ret) { 4427 drm_dbg_kms(&dev_priv->drm, 4428 "failed to set mode on load-detect pipe\n"); 4429 goto fail; 4430 } 4431 4432 old->restore_state = restore_state; 4433 drm_atomic_state_put(state); 4434 4435 /* let the connector get through one full cycle before testing */ 4436 intel_crtc_wait_for_next_vblank(crtc); 4437 4438 return true; 4439 4440 fail: 4441 if (state) { 4442 drm_atomic_state_put(state); 4443 state = NULL; 4444 } 4445 if (restore_state) { 4446 drm_atomic_state_put(restore_state); 4447 restore_state = NULL; 4448 } 4449 4450 if (ret == -EDEADLK) 4451 return ret; 4452 4453 return false; 4454 } 4455 4456 void intel_release_load_detect_pipe(struct drm_connector *connector, 4457 struct intel_load_detect_pipe *old, 4458 struct drm_modeset_acquire_ctx *ctx) 4459 { 4460 struct intel_encoder *intel_encoder = 4461 intel_attached_encoder(to_intel_connector(connector)); 4462 struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev); 4463 struct drm_encoder *encoder = &intel_encoder->base; 4464 struct drm_atomic_state *state = old->restore_state; 4465 int ret; 4466 4467 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 4468 connector->base.id, connector->name, 4469 encoder->base.id, encoder->name); 4470 4471 if (!state) 4472 return; 4473 4474 ret = drm_atomic_helper_commit_duplicated_state(state, ctx); 4475 if (ret) 4476 drm_dbg_kms(&i915->drm, 4477 "Couldn't release load detect pipe: %i\n", ret); 4478 drm_atomic_state_put(state); 4479 } 4480 4481 static int i9xx_pll_refclk(struct drm_device *dev, 4482 const struct intel_crtc_state *pipe_config) 4483 { 4484 struct drm_i915_private *dev_priv = to_i915(dev); 4485 u32 dpll = pipe_config->dpll_hw_state.dpll; 4486 4487 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) 4488 return dev_priv->vbt.lvds_ssc_freq; 4489 else if (HAS_PCH_SPLIT(dev_priv)) 4490 return 120000; 4491 else if (DISPLAY_VER(dev_priv) != 2) 4492 return 96000; 4493 else 4494 return 48000; 4495 } 4496 4497 /* Returns the clock of the currently programmed mode of the given pipe. */ 4498 void i9xx_crtc_clock_get(struct intel_crtc *crtc, 4499 struct intel_crtc_state *pipe_config) 4500 { 4501 struct drm_device *dev = crtc->base.dev; 4502 struct drm_i915_private *dev_priv = to_i915(dev); 4503 u32 dpll = pipe_config->dpll_hw_state.dpll; 4504 u32 fp; 4505 struct dpll clock; 4506 int port_clock; 4507 int refclk = i9xx_pll_refclk(dev, pipe_config); 4508 4509 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 4510 fp = pipe_config->dpll_hw_state.fp0; 4511 else 4512 fp = pipe_config->dpll_hw_state.fp1; 4513 4514 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 4515 if (IS_PINEVIEW(dev_priv)) { 4516 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; 4517 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; 4518 } else { 4519 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 4520 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 4521 } 4522 4523 if (DISPLAY_VER(dev_priv) != 2) { 4524 if (IS_PINEVIEW(dev_priv)) 4525 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> 4526 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); 4527 else 4528 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> 4529 DPLL_FPA01_P1_POST_DIV_SHIFT); 4530 4531 switch (dpll & DPLL_MODE_MASK) { 4532 case DPLLB_MODE_DAC_SERIAL: 4533 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 4534 5 : 10; 4535 break; 4536 case DPLLB_MODE_LVDS: 4537 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 4538 7 : 14; 4539 break; 4540 default: 4541 drm_dbg_kms(&dev_priv->drm, 4542 "Unknown DPLL mode %08x in programmed " 4543 "mode\n", (int)(dpll & DPLL_MODE_MASK)); 4544 return; 4545 } 4546 4547 if (IS_PINEVIEW(dev_priv)) 4548 port_clock = pnv_calc_dpll_params(refclk, &clock); 4549 else 4550 port_clock = i9xx_calc_dpll_params(refclk, &clock); 4551 } else { 4552 enum pipe lvds_pipe; 4553 4554 if (IS_I85X(dev_priv) && 4555 intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) && 4556 lvds_pipe == crtc->pipe) { 4557 u32 lvds = intel_de_read(dev_priv, LVDS); 4558 4559 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 4560 DPLL_FPA01_P1_POST_DIV_SHIFT); 4561 4562 if (lvds & LVDS_CLKB_POWER_UP) 4563 clock.p2 = 7; 4564 else 4565 clock.p2 = 14; 4566 } else { 4567 if (dpll & PLL_P1_DIVIDE_BY_TWO) 4568 clock.p1 = 2; 4569 else { 4570 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 4571 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 4572 } 4573 if (dpll & PLL_P2_DIVIDE_BY_4) 4574 clock.p2 = 4; 4575 else 4576 clock.p2 = 2; 4577 } 4578 4579 port_clock = i9xx_calc_dpll_params(refclk, &clock); 4580 } 4581 4582 /* 4583 * This value includes pixel_multiplier. We will use 4584 * port_clock to compute adjusted_mode.crtc_clock in the 4585 * encoder's get_config() function. 4586 */ 4587 pipe_config->port_clock = port_clock; 4588 } 4589 4590 int intel_dotclock_calculate(int link_freq, 4591 const struct intel_link_m_n *m_n) 4592 { 4593 /* 4594 * The calculation for the data clock is: 4595 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp 4596 * But we want to avoid losing precison if possible, so: 4597 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) 4598 * 4599 * and the link clock is simpler: 4600 * link_clock = (m * link_clock) / n 4601 */ 4602 4603 if (!m_n->link_n) 4604 return 0; 4605 4606 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n); 4607 } 4608 4609 /* Returns the currently programmed mode of the given encoder. */ 4610 struct drm_display_mode * 4611 intel_encoder_current_mode(struct intel_encoder *encoder) 4612 { 4613 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4614 struct intel_crtc_state *crtc_state; 4615 struct drm_display_mode *mode; 4616 struct intel_crtc *crtc; 4617 enum pipe pipe; 4618 4619 if (!encoder->get_hw_state(encoder, &pipe)) 4620 return NULL; 4621 4622 crtc = intel_crtc_for_pipe(dev_priv, pipe); 4623 4624 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 4625 if (!mode) 4626 return NULL; 4627 4628 crtc_state = intel_crtc_state_alloc(crtc); 4629 if (!crtc_state) { 4630 kfree(mode); 4631 return NULL; 4632 } 4633 4634 if (!intel_crtc_get_pipe_config(crtc_state)) { 4635 kfree(crtc_state); 4636 kfree(mode); 4637 return NULL; 4638 } 4639 4640 intel_encoder_get_config(encoder, crtc_state); 4641 4642 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode); 4643 4644 kfree(crtc_state); 4645 4646 return mode; 4647 } 4648 4649 static bool encoders_cloneable(const struct intel_encoder *a, 4650 const struct intel_encoder *b) 4651 { 4652 /* masks could be asymmetric, so check both ways */ 4653 return a == b || (a->cloneable & (1 << b->type) && 4654 b->cloneable & (1 << a->type)); 4655 } 4656 4657 static bool check_single_encoder_cloning(struct intel_atomic_state *state, 4658 struct intel_crtc *crtc, 4659 struct intel_encoder *encoder) 4660 { 4661 struct intel_encoder *source_encoder; 4662 struct drm_connector *connector; 4663 struct drm_connector_state *connector_state; 4664 int i; 4665 4666 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4667 if (connector_state->crtc != &crtc->base) 4668 continue; 4669 4670 source_encoder = 4671 to_intel_encoder(connector_state->best_encoder); 4672 if (!encoders_cloneable(encoder, source_encoder)) 4673 return false; 4674 } 4675 4676 return true; 4677 } 4678 4679 static int icl_add_linked_planes(struct intel_atomic_state *state) 4680 { 4681 struct intel_plane *plane, *linked; 4682 struct intel_plane_state *plane_state, *linked_plane_state; 4683 int i; 4684 4685 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4686 linked = plane_state->planar_linked_plane; 4687 4688 if (!linked) 4689 continue; 4690 4691 linked_plane_state = intel_atomic_get_plane_state(state, linked); 4692 if (IS_ERR(linked_plane_state)) 4693 return PTR_ERR(linked_plane_state); 4694 4695 drm_WARN_ON(state->base.dev, 4696 linked_plane_state->planar_linked_plane != plane); 4697 drm_WARN_ON(state->base.dev, 4698 linked_plane_state->planar_slave == plane_state->planar_slave); 4699 } 4700 4701 return 0; 4702 } 4703 4704 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state) 4705 { 4706 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4707 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4708 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 4709 struct intel_plane *plane, *linked; 4710 struct intel_plane_state *plane_state; 4711 int i; 4712 4713 if (DISPLAY_VER(dev_priv) < 11) 4714 return 0; 4715 4716 /* 4717 * Destroy all old plane links and make the slave plane invisible 4718 * in the crtc_state->active_planes mask. 4719 */ 4720 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4721 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane) 4722 continue; 4723 4724 plane_state->planar_linked_plane = NULL; 4725 if (plane_state->planar_slave && !plane_state->uapi.visible) { 4726 crtc_state->enabled_planes &= ~BIT(plane->id); 4727 crtc_state->active_planes &= ~BIT(plane->id); 4728 crtc_state->update_planes |= BIT(plane->id); 4729 crtc_state->data_rate[plane->id] = 0; 4730 crtc_state->rel_data_rate[plane->id] = 0; 4731 } 4732 4733 plane_state->planar_slave = false; 4734 } 4735 4736 if (!crtc_state->nv12_planes) 4737 return 0; 4738 4739 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4740 struct intel_plane_state *linked_state = NULL; 4741 4742 if (plane->pipe != crtc->pipe || 4743 !(crtc_state->nv12_planes & BIT(plane->id))) 4744 continue; 4745 4746 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) { 4747 if (!icl_is_nv12_y_plane(dev_priv, linked->id)) 4748 continue; 4749 4750 if (crtc_state->active_planes & BIT(linked->id)) 4751 continue; 4752 4753 linked_state = intel_atomic_get_plane_state(state, linked); 4754 if (IS_ERR(linked_state)) 4755 return PTR_ERR(linked_state); 4756 4757 break; 4758 } 4759 4760 if (!linked_state) { 4761 drm_dbg_kms(&dev_priv->drm, 4762 "Need %d free Y planes for planar YUV\n", 4763 hweight8(crtc_state->nv12_planes)); 4764 4765 return -EINVAL; 4766 } 4767 4768 plane_state->planar_linked_plane = linked; 4769 4770 linked_state->planar_slave = true; 4771 linked_state->planar_linked_plane = plane; 4772 crtc_state->enabled_planes |= BIT(linked->id); 4773 crtc_state->active_planes |= BIT(linked->id); 4774 crtc_state->update_planes |= BIT(linked->id); 4775 crtc_state->data_rate[linked->id] = 4776 crtc_state->data_rate_y[plane->id]; 4777 crtc_state->rel_data_rate[linked->id] = 4778 crtc_state->rel_data_rate_y[plane->id]; 4779 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n", 4780 linked->base.name, plane->base.name); 4781 4782 /* Copy parameters to slave plane */ 4783 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE; 4784 linked_state->color_ctl = plane_state->color_ctl; 4785 linked_state->view = plane_state->view; 4786 linked_state->decrypt = plane_state->decrypt; 4787 4788 intel_plane_copy_hw_state(linked_state, plane_state); 4789 linked_state->uapi.src = plane_state->uapi.src; 4790 linked_state->uapi.dst = plane_state->uapi.dst; 4791 4792 if (icl_is_hdr_plane(dev_priv, plane->id)) { 4793 if (linked->id == PLANE_SPRITE5) 4794 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL; 4795 else if (linked->id == PLANE_SPRITE4) 4796 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL; 4797 else if (linked->id == PLANE_SPRITE3) 4798 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL; 4799 else if (linked->id == PLANE_SPRITE2) 4800 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL; 4801 else 4802 MISSING_CASE(linked->id); 4803 } 4804 } 4805 4806 return 0; 4807 } 4808 4809 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state) 4810 { 4811 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 4812 struct intel_atomic_state *state = 4813 to_intel_atomic_state(new_crtc_state->uapi.state); 4814 const struct intel_crtc_state *old_crtc_state = 4815 intel_atomic_get_old_crtc_state(state, crtc); 4816 4817 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes; 4818 } 4819 4820 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) 4821 { 4822 const struct drm_display_mode *pipe_mode = 4823 &crtc_state->hw.pipe_mode; 4824 int linetime_wm; 4825 4826 if (!crtc_state->hw.enable) 4827 return 0; 4828 4829 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4830 pipe_mode->crtc_clock); 4831 4832 return min(linetime_wm, 0x1ff); 4833 } 4834 4835 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, 4836 const struct intel_cdclk_state *cdclk_state) 4837 { 4838 const struct drm_display_mode *pipe_mode = 4839 &crtc_state->hw.pipe_mode; 4840 int linetime_wm; 4841 4842 if (!crtc_state->hw.enable) 4843 return 0; 4844 4845 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4846 cdclk_state->logical.cdclk); 4847 4848 return min(linetime_wm, 0x1ff); 4849 } 4850 4851 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) 4852 { 4853 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4854 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4855 const struct drm_display_mode *pipe_mode = 4856 &crtc_state->hw.pipe_mode; 4857 int linetime_wm; 4858 4859 if (!crtc_state->hw.enable) 4860 return 0; 4861 4862 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8, 4863 crtc_state->pixel_rate); 4864 4865 /* Display WA #1135: BXT:ALL GLK:ALL */ 4866 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 4867 dev_priv->ipc_enabled) 4868 linetime_wm /= 2; 4869 4870 return min(linetime_wm, 0x1ff); 4871 } 4872 4873 static int hsw_compute_linetime_wm(struct intel_atomic_state *state, 4874 struct intel_crtc *crtc) 4875 { 4876 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4877 struct intel_crtc_state *crtc_state = 4878 intel_atomic_get_new_crtc_state(state, crtc); 4879 const struct intel_cdclk_state *cdclk_state; 4880 4881 if (DISPLAY_VER(dev_priv) >= 9) 4882 crtc_state->linetime = skl_linetime_wm(crtc_state); 4883 else 4884 crtc_state->linetime = hsw_linetime_wm(crtc_state); 4885 4886 if (!hsw_crtc_supports_ips(crtc)) 4887 return 0; 4888 4889 cdclk_state = intel_atomic_get_cdclk_state(state); 4890 if (IS_ERR(cdclk_state)) 4891 return PTR_ERR(cdclk_state); 4892 4893 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state, 4894 cdclk_state); 4895 4896 return 0; 4897 } 4898 4899 static int intel_crtc_atomic_check(struct intel_atomic_state *state, 4900 struct intel_crtc *crtc) 4901 { 4902 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4903 struct intel_crtc_state *crtc_state = 4904 intel_atomic_get_new_crtc_state(state, crtc); 4905 bool mode_changed = intel_crtc_needs_modeset(crtc_state); 4906 int ret; 4907 4908 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) && 4909 mode_changed && !crtc_state->hw.active) 4910 crtc_state->update_wm_post = true; 4911 4912 if (mode_changed) { 4913 ret = intel_dpll_crtc_compute_clock(state, crtc); 4914 if (ret) 4915 return ret; 4916 4917 ret = intel_dpll_crtc_get_shared_dpll(state, crtc); 4918 if (ret) 4919 return ret; 4920 } 4921 4922 /* 4923 * May need to update pipe gamma enable bits 4924 * when C8 planes are getting enabled/disabled. 4925 */ 4926 if (c8_planes_changed(crtc_state)) 4927 crtc_state->uapi.color_mgmt_changed = true; 4928 4929 if (mode_changed || crtc_state->update_pipe || 4930 crtc_state->uapi.color_mgmt_changed) { 4931 ret = intel_color_check(crtc_state); 4932 if (ret) 4933 return ret; 4934 } 4935 4936 ret = intel_compute_pipe_wm(state, crtc); 4937 if (ret) { 4938 drm_dbg_kms(&dev_priv->drm, 4939 "Target pipe watermarks are invalid\n"); 4940 return ret; 4941 } 4942 4943 /* 4944 * Calculate 'intermediate' watermarks that satisfy both the 4945 * old state and the new state. We can program these 4946 * immediately. 4947 */ 4948 ret = intel_compute_intermediate_wm(state, crtc); 4949 if (ret) { 4950 drm_dbg_kms(&dev_priv->drm, 4951 "No valid intermediate pipe watermarks are possible\n"); 4952 return ret; 4953 } 4954 4955 if (DISPLAY_VER(dev_priv) >= 9) { 4956 if (mode_changed || crtc_state->update_pipe) { 4957 ret = skl_update_scaler_crtc(crtc_state); 4958 if (ret) 4959 return ret; 4960 } 4961 4962 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state); 4963 if (ret) 4964 return ret; 4965 } 4966 4967 if (HAS_IPS(dev_priv)) { 4968 ret = hsw_ips_compute_config(state, crtc); 4969 if (ret) 4970 return ret; 4971 } 4972 4973 if (DISPLAY_VER(dev_priv) >= 9 || 4974 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 4975 ret = hsw_compute_linetime_wm(state, crtc); 4976 if (ret) 4977 return ret; 4978 4979 } 4980 4981 ret = intel_psr2_sel_fetch_update(state, crtc); 4982 if (ret) 4983 return ret; 4984 4985 return 0; 4986 } 4987 4988 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) 4989 { 4990 struct intel_connector *connector; 4991 struct drm_connector_list_iter conn_iter; 4992 4993 drm_connector_list_iter_begin(dev, &conn_iter); 4994 for_each_intel_connector_iter(connector, &conn_iter) { 4995 struct drm_connector_state *conn_state = connector->base.state; 4996 struct intel_encoder *encoder = 4997 to_intel_encoder(connector->base.encoder); 4998 4999 if (conn_state->crtc) 5000 drm_connector_put(&connector->base); 5001 5002 if (encoder) { 5003 struct intel_crtc *crtc = 5004 to_intel_crtc(encoder->base.crtc); 5005 const struct intel_crtc_state *crtc_state = 5006 to_intel_crtc_state(crtc->base.state); 5007 5008 conn_state->best_encoder = &encoder->base; 5009 conn_state->crtc = &crtc->base; 5010 conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3; 5011 5012 drm_connector_get(&connector->base); 5013 } else { 5014 conn_state->best_encoder = NULL; 5015 conn_state->crtc = NULL; 5016 } 5017 } 5018 drm_connector_list_iter_end(&conn_iter); 5019 } 5020 5021 static int 5022 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state, 5023 struct intel_crtc_state *crtc_state) 5024 { 5025 struct drm_connector *connector = conn_state->connector; 5026 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 5027 const struct drm_display_info *info = &connector->display_info; 5028 int bpp; 5029 5030 switch (conn_state->max_bpc) { 5031 case 6 ... 7: 5032 bpp = 6 * 3; 5033 break; 5034 case 8 ... 9: 5035 bpp = 8 * 3; 5036 break; 5037 case 10 ... 11: 5038 bpp = 10 * 3; 5039 break; 5040 case 12 ... 16: 5041 bpp = 12 * 3; 5042 break; 5043 default: 5044 MISSING_CASE(conn_state->max_bpc); 5045 return -EINVAL; 5046 } 5047 5048 if (bpp < crtc_state->pipe_bpp) { 5049 drm_dbg_kms(&i915->drm, 5050 "[CONNECTOR:%d:%s] Limiting display bpp to %d " 5051 "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n", 5052 connector->base.id, connector->name, 5053 bpp, 3 * info->bpc, 5054 3 * conn_state->max_requested_bpc, 5055 crtc_state->pipe_bpp); 5056 5057 crtc_state->pipe_bpp = bpp; 5058 } 5059 5060 return 0; 5061 } 5062 5063 static int 5064 compute_baseline_pipe_bpp(struct intel_atomic_state *state, 5065 struct intel_crtc *crtc) 5066 { 5067 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5068 struct intel_crtc_state *crtc_state = 5069 intel_atomic_get_new_crtc_state(state, crtc); 5070 struct drm_connector *connector; 5071 struct drm_connector_state *connector_state; 5072 int bpp, i; 5073 5074 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 5075 IS_CHERRYVIEW(dev_priv))) 5076 bpp = 10*3; 5077 else if (DISPLAY_VER(dev_priv) >= 5) 5078 bpp = 12*3; 5079 else 5080 bpp = 8*3; 5081 5082 crtc_state->pipe_bpp = bpp; 5083 5084 /* Clamp display bpp to connector max bpp */ 5085 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5086 int ret; 5087 5088 if (connector_state->crtc != &crtc->base) 5089 continue; 5090 5091 ret = compute_sink_pipe_bpp(connector_state, crtc_state); 5092 if (ret) 5093 return ret; 5094 } 5095 5096 return 0; 5097 } 5098 5099 static void intel_dump_crtc_timings(struct drm_i915_private *i915, 5100 const struct drm_display_mode *mode) 5101 { 5102 drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, " 5103 "type: 0x%x flags: 0x%x\n", 5104 mode->crtc_clock, 5105 mode->crtc_hdisplay, mode->crtc_hsync_start, 5106 mode->crtc_hsync_end, mode->crtc_htotal, 5107 mode->crtc_vdisplay, mode->crtc_vsync_start, 5108 mode->crtc_vsync_end, mode->crtc_vtotal, 5109 mode->type, mode->flags); 5110 } 5111 5112 static void 5113 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config, 5114 const char *id, unsigned int lane_count, 5115 const struct intel_link_m_n *m_n) 5116 { 5117 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); 5118 5119 drm_dbg_kms(&i915->drm, 5120 "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n", 5121 id, lane_count, 5122 m_n->data_m, m_n->data_n, 5123 m_n->link_m, m_n->link_n, m_n->tu); 5124 } 5125 5126 static void 5127 intel_dump_infoframe(struct drm_i915_private *dev_priv, 5128 const union hdmi_infoframe *frame) 5129 { 5130 if (!drm_debug_enabled(DRM_UT_KMS)) 5131 return; 5132 5133 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame); 5134 } 5135 5136 static void 5137 intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv, 5138 const struct drm_dp_vsc_sdp *vsc) 5139 { 5140 if (!drm_debug_enabled(DRM_UT_KMS)) 5141 return; 5142 5143 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc); 5144 } 5145 5146 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x 5147 5148 static const char * const output_type_str[] = { 5149 OUTPUT_TYPE(UNUSED), 5150 OUTPUT_TYPE(ANALOG), 5151 OUTPUT_TYPE(DVO), 5152 OUTPUT_TYPE(SDVO), 5153 OUTPUT_TYPE(LVDS), 5154 OUTPUT_TYPE(TVOUT), 5155 OUTPUT_TYPE(HDMI), 5156 OUTPUT_TYPE(DP), 5157 OUTPUT_TYPE(EDP), 5158 OUTPUT_TYPE(DSI), 5159 OUTPUT_TYPE(DDI), 5160 OUTPUT_TYPE(DP_MST), 5161 }; 5162 5163 #undef OUTPUT_TYPE 5164 5165 static void snprintf_output_types(char *buf, size_t len, 5166 unsigned int output_types) 5167 { 5168 char *str = buf; 5169 int i; 5170 5171 str[0] = '\0'; 5172 5173 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) { 5174 int r; 5175 5176 if ((output_types & BIT(i)) == 0) 5177 continue; 5178 5179 r = snprintf(str, len, "%s%s", 5180 str != buf ? "," : "", output_type_str[i]); 5181 if (r >= len) 5182 break; 5183 str += r; 5184 len -= r; 5185 5186 output_types &= ~BIT(i); 5187 } 5188 5189 WARN_ON_ONCE(output_types != 0); 5190 } 5191 5192 static const char * const output_format_str[] = { 5193 [INTEL_OUTPUT_FORMAT_RGB] = "RGB", 5194 [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0", 5195 [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4", 5196 }; 5197 5198 static const char *output_formats(enum intel_output_format format) 5199 { 5200 if (format >= ARRAY_SIZE(output_format_str)) 5201 return "invalid"; 5202 return output_format_str[format]; 5203 } 5204 5205 static void intel_dump_plane_state(const struct intel_plane_state *plane_state) 5206 { 5207 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 5208 struct drm_i915_private *i915 = to_i915(plane->base.dev); 5209 const struct drm_framebuffer *fb = plane_state->hw.fb; 5210 5211 if (!fb) { 5212 drm_dbg_kms(&i915->drm, 5213 "[PLANE:%d:%s] fb: [NOFB], visible: %s\n", 5214 plane->base.base.id, plane->base.name, 5215 str_yes_no(plane_state->uapi.visible)); 5216 return; 5217 } 5218 5219 drm_dbg_kms(&i915->drm, 5220 "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %p4cc modifier = 0x%llx, visible: %s\n", 5221 plane->base.base.id, plane->base.name, 5222 fb->base.id, fb->width, fb->height, &fb->format->format, 5223 fb->modifier, str_yes_no(plane_state->uapi.visible)); 5224 drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n", 5225 plane_state->hw.rotation, plane_state->scaler_id); 5226 if (plane_state->uapi.visible) 5227 drm_dbg_kms(&i915->drm, 5228 "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n", 5229 DRM_RECT_FP_ARG(&plane_state->uapi.src), 5230 DRM_RECT_ARG(&plane_state->uapi.dst)); 5231 } 5232 5233 static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, 5234 struct intel_atomic_state *state, 5235 const char *context) 5236 { 5237 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 5238 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5239 const struct intel_plane_state *plane_state; 5240 struct intel_plane *plane; 5241 char buf[64]; 5242 int i; 5243 5244 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n", 5245 crtc->base.base.id, crtc->base.name, 5246 str_yes_no(pipe_config->hw.enable), context); 5247 5248 if (!pipe_config->hw.enable) 5249 goto dump_planes; 5250 5251 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types); 5252 drm_dbg_kms(&dev_priv->drm, 5253 "active: %s, output_types: %s (0x%x), output format: %s\n", 5254 str_yes_no(pipe_config->hw.active), 5255 buf, pipe_config->output_types, 5256 output_formats(pipe_config->output_format)); 5257 5258 drm_dbg_kms(&dev_priv->drm, 5259 "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", 5260 transcoder_name(pipe_config->cpu_transcoder), 5261 pipe_config->pipe_bpp, pipe_config->dither); 5262 5263 drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n", 5264 transcoder_name(pipe_config->mst_master_transcoder)); 5265 5266 drm_dbg_kms(&dev_priv->drm, 5267 "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n", 5268 transcoder_name(pipe_config->master_transcoder), 5269 pipe_config->sync_mode_slaves_mask); 5270 5271 drm_dbg_kms(&dev_priv->drm, "bigjoiner: %s, pipes: 0x%x\n", 5272 intel_crtc_is_bigjoiner_slave(pipe_config) ? "slave" : 5273 intel_crtc_is_bigjoiner_master(pipe_config) ? "master" : "no", 5274 pipe_config->bigjoiner_pipes); 5275 5276 drm_dbg_kms(&dev_priv->drm, "splitter: %s, link count %d, overlap %d\n", 5277 str_enabled_disabled(pipe_config->splitter.enable), 5278 pipe_config->splitter.link_count, 5279 pipe_config->splitter.pixel_overlap); 5280 5281 if (pipe_config->has_pch_encoder) 5282 intel_dump_m_n_config(pipe_config, "fdi", 5283 pipe_config->fdi_lanes, 5284 &pipe_config->fdi_m_n); 5285 5286 if (intel_crtc_has_dp_encoder(pipe_config)) { 5287 intel_dump_m_n_config(pipe_config, "dp m_n", 5288 pipe_config->lane_count, 5289 &pipe_config->dp_m_n); 5290 intel_dump_m_n_config(pipe_config, "dp m2_n2", 5291 pipe_config->lane_count, 5292 &pipe_config->dp_m2_n2); 5293 } 5294 5295 drm_dbg_kms(&dev_priv->drm, "framestart delay: %d, MSA timing delay: %d\n", 5296 pipe_config->framestart_delay, pipe_config->msa_timing_delay); 5297 5298 drm_dbg_kms(&dev_priv->drm, 5299 "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n", 5300 pipe_config->has_audio, pipe_config->has_infoframe, 5301 pipe_config->infoframes.enable); 5302 5303 if (pipe_config->infoframes.enable & 5304 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) 5305 drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n", 5306 pipe_config->infoframes.gcp); 5307 if (pipe_config->infoframes.enable & 5308 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) 5309 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi); 5310 if (pipe_config->infoframes.enable & 5311 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD)) 5312 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd); 5313 if (pipe_config->infoframes.enable & 5314 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR)) 5315 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi); 5316 if (pipe_config->infoframes.enable & 5317 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) 5318 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); 5319 if (pipe_config->infoframes.enable & 5320 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA)) 5321 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); 5322 if (pipe_config->infoframes.enable & 5323 intel_hdmi_infoframe_enable(DP_SDP_VSC)) 5324 intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc); 5325 5326 drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n", 5327 str_yes_no(pipe_config->vrr.enable), 5328 pipe_config->vrr.vmin, pipe_config->vrr.vmax, 5329 pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband, 5330 pipe_config->vrr.flipline, 5331 intel_vrr_vmin_vblank_start(pipe_config), 5332 intel_vrr_vmax_vblank_start(pipe_config)); 5333 5334 drm_dbg_kms(&dev_priv->drm, "requested mode: " DRM_MODE_FMT "\n", 5335 DRM_MODE_ARG(&pipe_config->hw.mode)); 5336 drm_dbg_kms(&dev_priv->drm, "adjusted mode: " DRM_MODE_FMT "\n", 5337 DRM_MODE_ARG(&pipe_config->hw.adjusted_mode)); 5338 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode); 5339 drm_dbg_kms(&dev_priv->drm, "pipe mode: " DRM_MODE_FMT "\n", 5340 DRM_MODE_ARG(&pipe_config->hw.pipe_mode)); 5341 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode); 5342 drm_dbg_kms(&dev_priv->drm, 5343 "port clock: %d, pipe src: " DRM_RECT_FMT ", pixel rate %d\n", 5344 pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src), 5345 pipe_config->pixel_rate); 5346 5347 drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n", 5348 pipe_config->linetime, pipe_config->ips_linetime); 5349 5350 if (DISPLAY_VER(dev_priv) >= 9) 5351 drm_dbg_kms(&dev_priv->drm, 5352 "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", 5353 crtc->num_scalers, 5354 pipe_config->scaler_state.scaler_users, 5355 pipe_config->scaler_state.scaler_id); 5356 5357 if (HAS_GMCH(dev_priv)) 5358 drm_dbg_kms(&dev_priv->drm, 5359 "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", 5360 pipe_config->gmch_pfit.control, 5361 pipe_config->gmch_pfit.pgm_ratios, 5362 pipe_config->gmch_pfit.lvds_border_bits); 5363 else 5364 drm_dbg_kms(&dev_priv->drm, 5365 "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n", 5366 DRM_RECT_ARG(&pipe_config->pch_pfit.dst), 5367 str_enabled_disabled(pipe_config->pch_pfit.enabled), 5368 str_yes_no(pipe_config->pch_pfit.force_thru)); 5369 5370 drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i, drrs: %i\n", 5371 pipe_config->ips_enabled, pipe_config->double_wide, 5372 pipe_config->has_drrs); 5373 5374 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state); 5375 5376 if (IS_CHERRYVIEW(dev_priv)) 5377 drm_dbg_kms(&dev_priv->drm, 5378 "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", 5379 pipe_config->cgm_mode, pipe_config->gamma_mode, 5380 pipe_config->gamma_enable, pipe_config->csc_enable); 5381 else 5382 drm_dbg_kms(&dev_priv->drm, 5383 "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", 5384 pipe_config->csc_mode, pipe_config->gamma_mode, 5385 pipe_config->gamma_enable, pipe_config->csc_enable); 5386 5387 drm_dbg_kms(&dev_priv->drm, "degamma lut: %d entries, gamma lut: %d entries\n", 5388 pipe_config->hw.degamma_lut ? 5389 drm_color_lut_size(pipe_config->hw.degamma_lut) : 0, 5390 pipe_config->hw.gamma_lut ? 5391 drm_color_lut_size(pipe_config->hw.gamma_lut) : 0); 5392 5393 dump_planes: 5394 if (!state) 5395 return; 5396 5397 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 5398 if (plane->pipe == crtc->pipe) 5399 intel_dump_plane_state(plane_state); 5400 } 5401 } 5402 5403 static bool check_digital_port_conflicts(struct intel_atomic_state *state) 5404 { 5405 struct drm_device *dev = state->base.dev; 5406 struct drm_connector *connector; 5407 struct drm_connector_list_iter conn_iter; 5408 unsigned int used_ports = 0; 5409 unsigned int used_mst_ports = 0; 5410 bool ret = true; 5411 5412 /* 5413 * We're going to peek into connector->state, 5414 * hence connection_mutex must be held. 5415 */ 5416 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex); 5417 5418 /* 5419 * Walk the connector list instead of the encoder 5420 * list to detect the problem on ddi platforms 5421 * where there's just one encoder per digital port. 5422 */ 5423 drm_connector_list_iter_begin(dev, &conn_iter); 5424 drm_for_each_connector_iter(connector, &conn_iter) { 5425 struct drm_connector_state *connector_state; 5426 struct intel_encoder *encoder; 5427 5428 connector_state = 5429 drm_atomic_get_new_connector_state(&state->base, 5430 connector); 5431 if (!connector_state) 5432 connector_state = connector->state; 5433 5434 if (!connector_state->best_encoder) 5435 continue; 5436 5437 encoder = to_intel_encoder(connector_state->best_encoder); 5438 5439 drm_WARN_ON(dev, !connector_state->crtc); 5440 5441 switch (encoder->type) { 5442 case INTEL_OUTPUT_DDI: 5443 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev)))) 5444 break; 5445 fallthrough; 5446 case INTEL_OUTPUT_DP: 5447 case INTEL_OUTPUT_HDMI: 5448 case INTEL_OUTPUT_EDP: 5449 /* the same port mustn't appear more than once */ 5450 if (used_ports & BIT(encoder->port)) 5451 ret = false; 5452 5453 used_ports |= BIT(encoder->port); 5454 break; 5455 case INTEL_OUTPUT_DP_MST: 5456 used_mst_ports |= 5457 1 << encoder->port; 5458 break; 5459 default: 5460 break; 5461 } 5462 } 5463 drm_connector_list_iter_end(&conn_iter); 5464 5465 /* can't mix MST and SST/HDMI on the same port */ 5466 if (used_ports & used_mst_ports) 5467 return false; 5468 5469 return ret; 5470 } 5471 5472 static void 5473 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state, 5474 struct intel_crtc *crtc) 5475 { 5476 struct intel_crtc_state *crtc_state = 5477 intel_atomic_get_new_crtc_state(state, crtc); 5478 5479 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 5480 5481 drm_property_replace_blob(&crtc_state->hw.degamma_lut, 5482 crtc_state->uapi.degamma_lut); 5483 drm_property_replace_blob(&crtc_state->hw.gamma_lut, 5484 crtc_state->uapi.gamma_lut); 5485 drm_property_replace_blob(&crtc_state->hw.ctm, 5486 crtc_state->uapi.ctm); 5487 } 5488 5489 static void 5490 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state, 5491 struct intel_crtc *crtc) 5492 { 5493 struct intel_crtc_state *crtc_state = 5494 intel_atomic_get_new_crtc_state(state, crtc); 5495 5496 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 5497 5498 crtc_state->hw.enable = crtc_state->uapi.enable; 5499 crtc_state->hw.active = crtc_state->uapi.active; 5500 drm_mode_copy(&crtc_state->hw.mode, 5501 &crtc_state->uapi.mode); 5502 drm_mode_copy(&crtc_state->hw.adjusted_mode, 5503 &crtc_state->uapi.adjusted_mode); 5504 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter; 5505 5506 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 5507 } 5508 5509 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state) 5510 { 5511 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 5512 return; 5513 5514 crtc_state->uapi.enable = crtc_state->hw.enable; 5515 crtc_state->uapi.active = crtc_state->hw.active; 5516 drm_WARN_ON(crtc_state->uapi.crtc->dev, 5517 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0); 5518 5519 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode; 5520 crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter; 5521 5522 drm_property_replace_blob(&crtc_state->uapi.degamma_lut, 5523 crtc_state->hw.degamma_lut); 5524 drm_property_replace_blob(&crtc_state->uapi.gamma_lut, 5525 crtc_state->hw.gamma_lut); 5526 drm_property_replace_blob(&crtc_state->uapi.ctm, 5527 crtc_state->hw.ctm); 5528 } 5529 5530 static void 5531 copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state, 5532 struct intel_crtc *slave_crtc) 5533 { 5534 struct intel_crtc_state *slave_crtc_state = 5535 intel_atomic_get_new_crtc_state(state, slave_crtc); 5536 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 5537 const struct intel_crtc_state *master_crtc_state = 5538 intel_atomic_get_new_crtc_state(state, master_crtc); 5539 5540 drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut, 5541 master_crtc_state->hw.degamma_lut); 5542 drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut, 5543 master_crtc_state->hw.gamma_lut); 5544 drm_property_replace_blob(&slave_crtc_state->hw.ctm, 5545 master_crtc_state->hw.ctm); 5546 5547 slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed; 5548 } 5549 5550 static int 5551 copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state, 5552 struct intel_crtc *slave_crtc) 5553 { 5554 struct intel_crtc_state *slave_crtc_state = 5555 intel_atomic_get_new_crtc_state(state, slave_crtc); 5556 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 5557 const struct intel_crtc_state *master_crtc_state = 5558 intel_atomic_get_new_crtc_state(state, master_crtc); 5559 struct intel_crtc_state *saved_state; 5560 5561 WARN_ON(master_crtc_state->bigjoiner_pipes != 5562 slave_crtc_state->bigjoiner_pipes); 5563 5564 saved_state = kmemdup(master_crtc_state, sizeof(*saved_state), GFP_KERNEL); 5565 if (!saved_state) 5566 return -ENOMEM; 5567 5568 /* preserve some things from the slave's original crtc state */ 5569 saved_state->uapi = slave_crtc_state->uapi; 5570 saved_state->scaler_state = slave_crtc_state->scaler_state; 5571 saved_state->shared_dpll = slave_crtc_state->shared_dpll; 5572 saved_state->dpll_hw_state = slave_crtc_state->dpll_hw_state; 5573 saved_state->crc_enabled = slave_crtc_state->crc_enabled; 5574 5575 intel_crtc_free_hw_state(slave_crtc_state); 5576 memcpy(slave_crtc_state, saved_state, sizeof(*slave_crtc_state)); 5577 kfree(saved_state); 5578 5579 /* Re-init hw state */ 5580 memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw)); 5581 slave_crtc_state->hw.enable = master_crtc_state->hw.enable; 5582 slave_crtc_state->hw.active = master_crtc_state->hw.active; 5583 drm_mode_copy(&slave_crtc_state->hw.mode, 5584 &master_crtc_state->hw.mode); 5585 drm_mode_copy(&slave_crtc_state->hw.pipe_mode, 5586 &master_crtc_state->hw.pipe_mode); 5587 drm_mode_copy(&slave_crtc_state->hw.adjusted_mode, 5588 &master_crtc_state->hw.adjusted_mode); 5589 slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter; 5590 5591 copy_bigjoiner_crtc_state_nomodeset(state, slave_crtc); 5592 5593 slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed; 5594 slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed; 5595 slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed; 5596 5597 WARN_ON(master_crtc_state->bigjoiner_pipes != 5598 slave_crtc_state->bigjoiner_pipes); 5599 5600 return 0; 5601 } 5602 5603 static int 5604 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state, 5605 struct intel_crtc *crtc) 5606 { 5607 struct intel_crtc_state *crtc_state = 5608 intel_atomic_get_new_crtc_state(state, crtc); 5609 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5610 struct intel_crtc_state *saved_state; 5611 5612 saved_state = intel_crtc_state_alloc(crtc); 5613 if (!saved_state) 5614 return -ENOMEM; 5615 5616 /* free the old crtc_state->hw members */ 5617 intel_crtc_free_hw_state(crtc_state); 5618 5619 /* FIXME: before the switch to atomic started, a new pipe_config was 5620 * kzalloc'd. Code that depends on any field being zero should be 5621 * fixed, so that the crtc_state can be safely duplicated. For now, 5622 * only fields that are know to not cause problems are preserved. */ 5623 5624 saved_state->uapi = crtc_state->uapi; 5625 saved_state->scaler_state = crtc_state->scaler_state; 5626 saved_state->shared_dpll = crtc_state->shared_dpll; 5627 saved_state->dpll_hw_state = crtc_state->dpll_hw_state; 5628 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, 5629 sizeof(saved_state->icl_port_dplls)); 5630 saved_state->crc_enabled = crtc_state->crc_enabled; 5631 if (IS_G4X(dev_priv) || 5632 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5633 saved_state->wm = crtc_state->wm; 5634 5635 memcpy(crtc_state, saved_state, sizeof(*crtc_state)); 5636 kfree(saved_state); 5637 5638 intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc); 5639 5640 return 0; 5641 } 5642 5643 static int 5644 intel_modeset_pipe_config(struct intel_atomic_state *state, 5645 struct intel_crtc *crtc) 5646 { 5647 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 5648 struct intel_crtc_state *crtc_state = 5649 intel_atomic_get_new_crtc_state(state, crtc); 5650 struct drm_connector *connector; 5651 struct drm_connector_state *connector_state; 5652 int pipe_src_w, pipe_src_h; 5653 int base_bpp, ret, i; 5654 bool retry = true; 5655 5656 crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe; 5657 5658 crtc_state->framestart_delay = 1; 5659 5660 /* 5661 * Sanitize sync polarity flags based on requested ones. If neither 5662 * positive or negative polarity is requested, treat this as meaning 5663 * negative polarity. 5664 */ 5665 if (!(crtc_state->hw.adjusted_mode.flags & 5666 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) 5667 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; 5668 5669 if (!(crtc_state->hw.adjusted_mode.flags & 5670 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 5671 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; 5672 5673 ret = compute_baseline_pipe_bpp(state, crtc); 5674 if (ret) 5675 return ret; 5676 5677 base_bpp = crtc_state->pipe_bpp; 5678 5679 /* 5680 * Determine the real pipe dimensions. Note that stereo modes can 5681 * increase the actual pipe size due to the frame doubling and 5682 * insertion of additional space for blanks between the frame. This 5683 * is stored in the crtc timings. We use the requested mode to do this 5684 * computation to clearly distinguish it from the adjusted mode, which 5685 * can be changed by the connectors in the below retry loop. 5686 */ 5687 drm_mode_get_hv_timing(&crtc_state->hw.mode, 5688 &pipe_src_w, &pipe_src_h); 5689 drm_rect_init(&crtc_state->pipe_src, 0, 0, 5690 pipe_src_w, pipe_src_h); 5691 5692 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5693 struct intel_encoder *encoder = 5694 to_intel_encoder(connector_state->best_encoder); 5695 5696 if (connector_state->crtc != &crtc->base) 5697 continue; 5698 5699 if (!check_single_encoder_cloning(state, crtc, encoder)) { 5700 drm_dbg_kms(&i915->drm, 5701 "[ENCODER:%d:%s] rejecting invalid cloning configuration\n", 5702 encoder->base.base.id, encoder->base.name); 5703 return -EINVAL; 5704 } 5705 5706 /* 5707 * Determine output_types before calling the .compute_config() 5708 * hooks so that the hooks can use this information safely. 5709 */ 5710 if (encoder->compute_output_type) 5711 crtc_state->output_types |= 5712 BIT(encoder->compute_output_type(encoder, crtc_state, 5713 connector_state)); 5714 else 5715 crtc_state->output_types |= BIT(encoder->type); 5716 } 5717 5718 encoder_retry: 5719 /* Ensure the port clock defaults are reset when retrying. */ 5720 crtc_state->port_clock = 0; 5721 crtc_state->pixel_multiplier = 1; 5722 5723 /* Fill in default crtc timings, allow encoders to overwrite them. */ 5724 drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode, 5725 CRTC_STEREO_DOUBLE); 5726 5727 /* Pass our mode to the connectors and the CRTC to give them a chance to 5728 * adjust it according to limitations or connector properties, and also 5729 * a chance to reject the mode entirely. 5730 */ 5731 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5732 struct intel_encoder *encoder = 5733 to_intel_encoder(connector_state->best_encoder); 5734 5735 if (connector_state->crtc != &crtc->base) 5736 continue; 5737 5738 ret = encoder->compute_config(encoder, crtc_state, 5739 connector_state); 5740 if (ret == -EDEADLK) 5741 return ret; 5742 if (ret < 0) { 5743 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n", 5744 encoder->base.base.id, encoder->base.name, ret); 5745 return ret; 5746 } 5747 } 5748 5749 /* Set default port clock if not overwritten by the encoder. Needs to be 5750 * done afterwards in case the encoder adjusts the mode. */ 5751 if (!crtc_state->port_clock) 5752 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock 5753 * crtc_state->pixel_multiplier; 5754 5755 ret = intel_crtc_compute_config(state, crtc); 5756 if (ret == -EDEADLK) 5757 return ret; 5758 if (ret == -EAGAIN) { 5759 if (drm_WARN(&i915->drm, !retry, 5760 "[CRTC:%d:%s] loop in pipe configuration computation\n", 5761 crtc->base.base.id, crtc->base.name)) 5762 return -EINVAL; 5763 5764 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] bw constrained, retrying\n", 5765 crtc->base.base.id, crtc->base.name); 5766 retry = false; 5767 goto encoder_retry; 5768 } 5769 if (ret < 0) { 5770 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n", 5771 crtc->base.base.id, crtc->base.name, ret); 5772 return ret; 5773 } 5774 5775 /* Dithering seems to not pass-through bits correctly when it should, so 5776 * only enable it on 6bpc panels and when its not a compliance 5777 * test requesting 6bpc video pattern. 5778 */ 5779 crtc_state->dither = (crtc_state->pipe_bpp == 6*3) && 5780 !crtc_state->dither_force_disable; 5781 drm_dbg_kms(&i915->drm, 5782 "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n", 5783 crtc->base.base.id, crtc->base.name, 5784 base_bpp, crtc_state->pipe_bpp, crtc_state->dither); 5785 5786 return 0; 5787 } 5788 5789 static int 5790 intel_modeset_pipe_config_late(struct intel_atomic_state *state, 5791 struct intel_crtc *crtc) 5792 { 5793 struct intel_crtc_state *crtc_state = 5794 intel_atomic_get_new_crtc_state(state, crtc); 5795 struct drm_connector_state *conn_state; 5796 struct drm_connector *connector; 5797 int i; 5798 5799 intel_bigjoiner_adjust_pipe_src(crtc_state); 5800 5801 for_each_new_connector_in_state(&state->base, connector, 5802 conn_state, i) { 5803 struct intel_encoder *encoder = 5804 to_intel_encoder(conn_state->best_encoder); 5805 int ret; 5806 5807 if (conn_state->crtc != &crtc->base || 5808 !encoder->compute_config_late) 5809 continue; 5810 5811 ret = encoder->compute_config_late(encoder, crtc_state, 5812 conn_state); 5813 if (ret) 5814 return ret; 5815 } 5816 5817 return 0; 5818 } 5819 5820 bool intel_fuzzy_clock_check(int clock1, int clock2) 5821 { 5822 int diff; 5823 5824 if (clock1 == clock2) 5825 return true; 5826 5827 if (!clock1 || !clock2) 5828 return false; 5829 5830 diff = abs(clock1 - clock2); 5831 5832 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) 5833 return true; 5834 5835 return false; 5836 } 5837 5838 static bool 5839 intel_compare_m_n(unsigned int m, unsigned int n, 5840 unsigned int m2, unsigned int n2, 5841 bool exact) 5842 { 5843 if (m == m2 && n == n2) 5844 return true; 5845 5846 if (exact || !m || !n || !m2 || !n2) 5847 return false; 5848 5849 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); 5850 5851 if (n > n2) { 5852 while (n > n2) { 5853 m2 <<= 1; 5854 n2 <<= 1; 5855 } 5856 } else if (n < n2) { 5857 while (n < n2) { 5858 m <<= 1; 5859 n <<= 1; 5860 } 5861 } 5862 5863 if (n != n2) 5864 return false; 5865 5866 return intel_fuzzy_clock_check(m, m2); 5867 } 5868 5869 static bool 5870 intel_compare_link_m_n(const struct intel_link_m_n *m_n, 5871 const struct intel_link_m_n *m2_n2, 5872 bool exact) 5873 { 5874 return m_n->tu == m2_n2->tu && 5875 intel_compare_m_n(m_n->data_m, m_n->data_n, 5876 m2_n2->data_m, m2_n2->data_n, exact) && 5877 intel_compare_m_n(m_n->link_m, m_n->link_n, 5878 m2_n2->link_m, m2_n2->link_n, exact); 5879 } 5880 5881 static bool 5882 intel_compare_infoframe(const union hdmi_infoframe *a, 5883 const union hdmi_infoframe *b) 5884 { 5885 return memcmp(a, b, sizeof(*a)) == 0; 5886 } 5887 5888 static bool 5889 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a, 5890 const struct drm_dp_vsc_sdp *b) 5891 { 5892 return memcmp(a, b, sizeof(*a)) == 0; 5893 } 5894 5895 static void 5896 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv, 5897 bool fastset, const char *name, 5898 const union hdmi_infoframe *a, 5899 const union hdmi_infoframe *b) 5900 { 5901 if (fastset) { 5902 if (!drm_debug_enabled(DRM_UT_KMS)) 5903 return; 5904 5905 drm_dbg_kms(&dev_priv->drm, 5906 "fastset mismatch in %s infoframe\n", name); 5907 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 5908 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a); 5909 drm_dbg_kms(&dev_priv->drm, "found:\n"); 5910 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b); 5911 } else { 5912 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name); 5913 drm_err(&dev_priv->drm, "expected:\n"); 5914 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a); 5915 drm_err(&dev_priv->drm, "found:\n"); 5916 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b); 5917 } 5918 } 5919 5920 static void 5921 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv, 5922 bool fastset, const char *name, 5923 const struct drm_dp_vsc_sdp *a, 5924 const struct drm_dp_vsc_sdp *b) 5925 { 5926 if (fastset) { 5927 if (!drm_debug_enabled(DRM_UT_KMS)) 5928 return; 5929 5930 drm_dbg_kms(&dev_priv->drm, 5931 "fastset mismatch in %s dp sdp\n", name); 5932 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 5933 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a); 5934 drm_dbg_kms(&dev_priv->drm, "found:\n"); 5935 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b); 5936 } else { 5937 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name); 5938 drm_err(&dev_priv->drm, "expected:\n"); 5939 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a); 5940 drm_err(&dev_priv->drm, "found:\n"); 5941 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b); 5942 } 5943 } 5944 5945 static void __printf(4, 5) 5946 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc, 5947 const char *name, const char *format, ...) 5948 { 5949 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 5950 struct va_format vaf; 5951 va_list args; 5952 5953 va_start(args, format); 5954 vaf.fmt = format; 5955 vaf.va = &args; 5956 5957 if (fastset) 5958 drm_dbg_kms(&i915->drm, 5959 "[CRTC:%d:%s] fastset mismatch in %s %pV\n", 5960 crtc->base.base.id, crtc->base.name, name, &vaf); 5961 else 5962 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n", 5963 crtc->base.base.id, crtc->base.name, name, &vaf); 5964 5965 va_end(args); 5966 } 5967 5968 static bool fastboot_enabled(struct drm_i915_private *dev_priv) 5969 { 5970 if (dev_priv->params.fastboot != -1) 5971 return dev_priv->params.fastboot; 5972 5973 /* Enable fastboot by default on Skylake and newer */ 5974 if (DISPLAY_VER(dev_priv) >= 9) 5975 return true; 5976 5977 /* Enable fastboot by default on VLV and CHV */ 5978 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5979 return true; 5980 5981 /* Disabled by default on all others */ 5982 return false; 5983 } 5984 5985 static bool 5986 intel_pipe_config_compare(const struct intel_crtc_state *current_config, 5987 const struct intel_crtc_state *pipe_config, 5988 bool fastset) 5989 { 5990 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev); 5991 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 5992 bool ret = true; 5993 u32 bp_gamma = 0; 5994 bool fixup_inherited = fastset && 5995 current_config->inherited && !pipe_config->inherited; 5996 5997 if (fixup_inherited && !fastboot_enabled(dev_priv)) { 5998 drm_dbg_kms(&dev_priv->drm, 5999 "initial modeset and fastboot not set\n"); 6000 ret = false; 6001 } 6002 6003 #define PIPE_CONF_CHECK_X(name) do { \ 6004 if (current_config->name != pipe_config->name) { \ 6005 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6006 "(expected 0x%08x, found 0x%08x)", \ 6007 current_config->name, \ 6008 pipe_config->name); \ 6009 ret = false; \ 6010 } \ 6011 } while (0) 6012 6013 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \ 6014 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \ 6015 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6016 "(expected 0x%08x, found 0x%08x)", \ 6017 current_config->name & (mask), \ 6018 pipe_config->name & (mask)); \ 6019 ret = false; \ 6020 } \ 6021 } while (0) 6022 6023 #define PIPE_CONF_CHECK_I(name) do { \ 6024 if (current_config->name != pipe_config->name) { \ 6025 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6026 "(expected %i, found %i)", \ 6027 current_config->name, \ 6028 pipe_config->name); \ 6029 ret = false; \ 6030 } \ 6031 } while (0) 6032 6033 #define PIPE_CONF_CHECK_BOOL(name) do { \ 6034 if (current_config->name != pipe_config->name) { \ 6035 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6036 "(expected %s, found %s)", \ 6037 str_yes_no(current_config->name), \ 6038 str_yes_no(pipe_config->name)); \ 6039 ret = false; \ 6040 } \ 6041 } while (0) 6042 6043 /* 6044 * Checks state where we only read out the enabling, but not the entire 6045 * state itself (like full infoframes or ELD for audio). These states 6046 * require a full modeset on bootup to fix up. 6047 */ 6048 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \ 6049 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \ 6050 PIPE_CONF_CHECK_BOOL(name); \ 6051 } else { \ 6052 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6053 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \ 6054 str_yes_no(current_config->name), \ 6055 str_yes_no(pipe_config->name)); \ 6056 ret = false; \ 6057 } \ 6058 } while (0) 6059 6060 #define PIPE_CONF_CHECK_P(name) do { \ 6061 if (current_config->name != pipe_config->name) { \ 6062 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6063 "(expected %p, found %p)", \ 6064 current_config->name, \ 6065 pipe_config->name); \ 6066 ret = false; \ 6067 } \ 6068 } while (0) 6069 6070 #define PIPE_CONF_CHECK_M_N(name) do { \ 6071 if (!intel_compare_link_m_n(¤t_config->name, \ 6072 &pipe_config->name,\ 6073 !fastset)) { \ 6074 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6075 "(expected tu %i data %i/%i link %i/%i, " \ 6076 "found tu %i, data %i/%i link %i/%i)", \ 6077 current_config->name.tu, \ 6078 current_config->name.data_m, \ 6079 current_config->name.data_n, \ 6080 current_config->name.link_m, \ 6081 current_config->name.link_n, \ 6082 pipe_config->name.tu, \ 6083 pipe_config->name.data_m, \ 6084 pipe_config->name.data_n, \ 6085 pipe_config->name.link_m, \ 6086 pipe_config->name.link_n); \ 6087 ret = false; \ 6088 } \ 6089 } while (0) 6090 6091 #define PIPE_CONF_CHECK_TIMINGS(name) do { \ 6092 PIPE_CONF_CHECK_I(name.crtc_hdisplay); \ 6093 PIPE_CONF_CHECK_I(name.crtc_htotal); \ 6094 PIPE_CONF_CHECK_I(name.crtc_hblank_start); \ 6095 PIPE_CONF_CHECK_I(name.crtc_hblank_end); \ 6096 PIPE_CONF_CHECK_I(name.crtc_hsync_start); \ 6097 PIPE_CONF_CHECK_I(name.crtc_hsync_end); \ 6098 PIPE_CONF_CHECK_I(name.crtc_vdisplay); \ 6099 PIPE_CONF_CHECK_I(name.crtc_vtotal); \ 6100 PIPE_CONF_CHECK_I(name.crtc_vblank_start); \ 6101 PIPE_CONF_CHECK_I(name.crtc_vblank_end); \ 6102 PIPE_CONF_CHECK_I(name.crtc_vsync_start); \ 6103 PIPE_CONF_CHECK_I(name.crtc_vsync_end); \ 6104 } while (0) 6105 6106 #define PIPE_CONF_CHECK_RECT(name) do { \ 6107 PIPE_CONF_CHECK_I(name.x1); \ 6108 PIPE_CONF_CHECK_I(name.x2); \ 6109 PIPE_CONF_CHECK_I(name.y1); \ 6110 PIPE_CONF_CHECK_I(name.y2); \ 6111 } while (0) 6112 6113 /* This is required for BDW+ where there is only one set of registers for 6114 * switching between high and low RR. 6115 * This macro can be used whenever a comparison has to be made between one 6116 * hw state and multiple sw state variables. 6117 */ 6118 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \ 6119 if (!intel_compare_link_m_n(¤t_config->name, \ 6120 &pipe_config->name, !fastset) && \ 6121 !intel_compare_link_m_n(¤t_config->alt_name, \ 6122 &pipe_config->name, !fastset)) { \ 6123 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6124 "(expected tu %i data %i/%i link %i/%i, " \ 6125 "or tu %i data %i/%i link %i/%i, " \ 6126 "found tu %i, data %i/%i link %i/%i)", \ 6127 current_config->name.tu, \ 6128 current_config->name.data_m, \ 6129 current_config->name.data_n, \ 6130 current_config->name.link_m, \ 6131 current_config->name.link_n, \ 6132 current_config->alt_name.tu, \ 6133 current_config->alt_name.data_m, \ 6134 current_config->alt_name.data_n, \ 6135 current_config->alt_name.link_m, \ 6136 current_config->alt_name.link_n, \ 6137 pipe_config->name.tu, \ 6138 pipe_config->name.data_m, \ 6139 pipe_config->name.data_n, \ 6140 pipe_config->name.link_m, \ 6141 pipe_config->name.link_n); \ 6142 ret = false; \ 6143 } \ 6144 } while (0) 6145 6146 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \ 6147 if ((current_config->name ^ pipe_config->name) & (mask)) { \ 6148 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6149 "(%x) (expected %i, found %i)", \ 6150 (mask), \ 6151 current_config->name & (mask), \ 6152 pipe_config->name & (mask)); \ 6153 ret = false; \ 6154 } \ 6155 } while (0) 6156 6157 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \ 6158 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ 6159 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6160 "(expected %i, found %i)", \ 6161 current_config->name, \ 6162 pipe_config->name); \ 6163 ret = false; \ 6164 } \ 6165 } while (0) 6166 6167 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \ 6168 if (!intel_compare_infoframe(¤t_config->infoframes.name, \ 6169 &pipe_config->infoframes.name)) { \ 6170 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \ 6171 ¤t_config->infoframes.name, \ 6172 &pipe_config->infoframes.name); \ 6173 ret = false; \ 6174 } \ 6175 } while (0) 6176 6177 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \ 6178 if (!current_config->has_psr && !pipe_config->has_psr && \ 6179 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \ 6180 &pipe_config->infoframes.name)) { \ 6181 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \ 6182 ¤t_config->infoframes.name, \ 6183 &pipe_config->infoframes.name); \ 6184 ret = false; \ 6185 } \ 6186 } while (0) 6187 6188 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \ 6189 if (current_config->name1 != pipe_config->name1) { \ 6190 pipe_config_mismatch(fastset, crtc, __stringify(name1), \ 6191 "(expected %i, found %i, won't compare lut values)", \ 6192 current_config->name1, \ 6193 pipe_config->name1); \ 6194 ret = false;\ 6195 } else { \ 6196 if (!intel_color_lut_equal(current_config->name2, \ 6197 pipe_config->name2, pipe_config->name1, \ 6198 bit_precision)) { \ 6199 pipe_config_mismatch(fastset, crtc, __stringify(name2), \ 6200 "hw_state doesn't match sw_state"); \ 6201 ret = false; \ 6202 } \ 6203 } \ 6204 } while (0) 6205 6206 #define PIPE_CONF_QUIRK(quirk) \ 6207 ((current_config->quirks | pipe_config->quirks) & (quirk)) 6208 6209 PIPE_CONF_CHECK_I(hw.enable); 6210 PIPE_CONF_CHECK_I(hw.active); 6211 6212 PIPE_CONF_CHECK_I(cpu_transcoder); 6213 PIPE_CONF_CHECK_I(mst_master_transcoder); 6214 6215 PIPE_CONF_CHECK_BOOL(has_pch_encoder); 6216 PIPE_CONF_CHECK_I(fdi_lanes); 6217 PIPE_CONF_CHECK_M_N(fdi_m_n); 6218 6219 PIPE_CONF_CHECK_I(lane_count); 6220 PIPE_CONF_CHECK_X(lane_lat_optim_mask); 6221 6222 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) { 6223 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); 6224 } else { 6225 PIPE_CONF_CHECK_M_N(dp_m_n); 6226 PIPE_CONF_CHECK_M_N(dp_m2_n2); 6227 } 6228 6229 PIPE_CONF_CHECK_X(output_types); 6230 6231 PIPE_CONF_CHECK_I(framestart_delay); 6232 PIPE_CONF_CHECK_I(msa_timing_delay); 6233 6234 PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode); 6235 PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode); 6236 6237 PIPE_CONF_CHECK_I(pixel_multiplier); 6238 6239 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6240 DRM_MODE_FLAG_INTERLACE); 6241 6242 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { 6243 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6244 DRM_MODE_FLAG_PHSYNC); 6245 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6246 DRM_MODE_FLAG_NHSYNC); 6247 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6248 DRM_MODE_FLAG_PVSYNC); 6249 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6250 DRM_MODE_FLAG_NVSYNC); 6251 } 6252 6253 PIPE_CONF_CHECK_I(output_format); 6254 PIPE_CONF_CHECK_BOOL(has_hdmi_sink); 6255 if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || 6256 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 6257 PIPE_CONF_CHECK_BOOL(limited_color_range); 6258 6259 PIPE_CONF_CHECK_BOOL(hdmi_scrambling); 6260 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio); 6261 PIPE_CONF_CHECK_BOOL(has_infoframe); 6262 PIPE_CONF_CHECK_BOOL(fec_enable); 6263 6264 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio); 6265 6266 PIPE_CONF_CHECK_X(gmch_pfit.control); 6267 /* pfit ratios are autocomputed by the hw on gen4+ */ 6268 if (DISPLAY_VER(dev_priv) < 4) 6269 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); 6270 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); 6271 6272 /* 6273 * Changing the EDP transcoder input mux 6274 * (A_ONOFF vs. A_ON) requires a full modeset. 6275 */ 6276 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru); 6277 6278 if (!fastset) { 6279 PIPE_CONF_CHECK_RECT(pipe_src); 6280 6281 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled); 6282 PIPE_CONF_CHECK_RECT(pch_pfit.dst); 6283 6284 PIPE_CONF_CHECK_I(scaler_state.scaler_id); 6285 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate); 6286 6287 PIPE_CONF_CHECK_X(gamma_mode); 6288 if (IS_CHERRYVIEW(dev_priv)) 6289 PIPE_CONF_CHECK_X(cgm_mode); 6290 else 6291 PIPE_CONF_CHECK_X(csc_mode); 6292 PIPE_CONF_CHECK_BOOL(gamma_enable); 6293 PIPE_CONF_CHECK_BOOL(csc_enable); 6294 6295 PIPE_CONF_CHECK_I(linetime); 6296 PIPE_CONF_CHECK_I(ips_linetime); 6297 6298 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config); 6299 if (bp_gamma) 6300 PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma); 6301 6302 if (current_config->active_planes) { 6303 PIPE_CONF_CHECK_BOOL(has_psr); 6304 PIPE_CONF_CHECK_BOOL(has_psr2); 6305 PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); 6306 PIPE_CONF_CHECK_I(dc3co_exitline); 6307 } 6308 } 6309 6310 PIPE_CONF_CHECK_BOOL(double_wide); 6311 6312 if (dev_priv->dpll.mgr) { 6313 PIPE_CONF_CHECK_P(shared_dpll); 6314 6315 PIPE_CONF_CHECK_X(dpll_hw_state.dpll); 6316 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); 6317 PIPE_CONF_CHECK_X(dpll_hw_state.fp0); 6318 PIPE_CONF_CHECK_X(dpll_hw_state.fp1); 6319 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); 6320 PIPE_CONF_CHECK_X(dpll_hw_state.spll); 6321 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); 6322 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); 6323 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); 6324 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); 6325 PIPE_CONF_CHECK_X(dpll_hw_state.div0); 6326 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); 6327 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); 6328 PIPE_CONF_CHECK_X(dpll_hw_state.pll0); 6329 PIPE_CONF_CHECK_X(dpll_hw_state.pll1); 6330 PIPE_CONF_CHECK_X(dpll_hw_state.pll2); 6331 PIPE_CONF_CHECK_X(dpll_hw_state.pll3); 6332 PIPE_CONF_CHECK_X(dpll_hw_state.pll6); 6333 PIPE_CONF_CHECK_X(dpll_hw_state.pll8); 6334 PIPE_CONF_CHECK_X(dpll_hw_state.pll9); 6335 PIPE_CONF_CHECK_X(dpll_hw_state.pll10); 6336 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); 6337 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl); 6338 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1); 6339 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl); 6340 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0); 6341 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1); 6342 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf); 6343 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock); 6344 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc); 6345 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias); 6346 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias); 6347 } 6348 6349 PIPE_CONF_CHECK_X(dsi_pll.ctrl); 6350 PIPE_CONF_CHECK_X(dsi_pll.div); 6351 6352 if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5) 6353 PIPE_CONF_CHECK_I(pipe_bpp); 6354 6355 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock); 6356 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock); 6357 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); 6358 6359 PIPE_CONF_CHECK_I(min_voltage_level); 6360 6361 if (current_config->has_psr || pipe_config->has_psr) 6362 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable, 6363 ~intel_hdmi_infoframe_enable(DP_SDP_VSC)); 6364 else 6365 PIPE_CONF_CHECK_X(infoframes.enable); 6366 6367 PIPE_CONF_CHECK_X(infoframes.gcp); 6368 PIPE_CONF_CHECK_INFOFRAME(avi); 6369 PIPE_CONF_CHECK_INFOFRAME(spd); 6370 PIPE_CONF_CHECK_INFOFRAME(hdmi); 6371 PIPE_CONF_CHECK_INFOFRAME(drm); 6372 PIPE_CONF_CHECK_DP_VSC_SDP(vsc); 6373 6374 PIPE_CONF_CHECK_X(sync_mode_slaves_mask); 6375 PIPE_CONF_CHECK_I(master_transcoder); 6376 PIPE_CONF_CHECK_X(bigjoiner_pipes); 6377 6378 PIPE_CONF_CHECK_I(dsc.compression_enable); 6379 PIPE_CONF_CHECK_I(dsc.dsc_split); 6380 PIPE_CONF_CHECK_I(dsc.compressed_bpp); 6381 6382 PIPE_CONF_CHECK_BOOL(splitter.enable); 6383 PIPE_CONF_CHECK_I(splitter.link_count); 6384 PIPE_CONF_CHECK_I(splitter.pixel_overlap); 6385 6386 PIPE_CONF_CHECK_BOOL(vrr.enable); 6387 PIPE_CONF_CHECK_I(vrr.vmin); 6388 PIPE_CONF_CHECK_I(vrr.vmax); 6389 PIPE_CONF_CHECK_I(vrr.flipline); 6390 PIPE_CONF_CHECK_I(vrr.pipeline_full); 6391 PIPE_CONF_CHECK_I(vrr.guardband); 6392 6393 #undef PIPE_CONF_CHECK_X 6394 #undef PIPE_CONF_CHECK_I 6395 #undef PIPE_CONF_CHECK_BOOL 6396 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE 6397 #undef PIPE_CONF_CHECK_P 6398 #undef PIPE_CONF_CHECK_FLAGS 6399 #undef PIPE_CONF_CHECK_CLOCK_FUZZY 6400 #undef PIPE_CONF_CHECK_COLOR_LUT 6401 #undef PIPE_CONF_CHECK_TIMINGS 6402 #undef PIPE_CONF_CHECK_RECT 6403 #undef PIPE_CONF_QUIRK 6404 6405 return ret; 6406 } 6407 6408 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, 6409 const struct intel_crtc_state *pipe_config) 6410 { 6411 if (pipe_config->has_pch_encoder) { 6412 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), 6413 &pipe_config->fdi_m_n); 6414 int dotclock = pipe_config->hw.adjusted_mode.crtc_clock; 6415 6416 /* 6417 * FDI already provided one idea for the dotclock. 6418 * Yell if the encoder disagrees. 6419 */ 6420 drm_WARN(&dev_priv->drm, 6421 !intel_fuzzy_clock_check(fdi_dotclock, dotclock), 6422 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", 6423 fdi_dotclock, dotclock); 6424 } 6425 } 6426 6427 static void verify_wm_state(struct intel_crtc *crtc, 6428 struct intel_crtc_state *new_crtc_state) 6429 { 6430 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6431 struct skl_hw_state { 6432 struct skl_ddb_entry ddb[I915_MAX_PLANES]; 6433 struct skl_ddb_entry ddb_y[I915_MAX_PLANES]; 6434 struct skl_pipe_wm wm; 6435 } *hw; 6436 const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal; 6437 int level, max_level = ilk_wm_max_level(dev_priv); 6438 struct intel_plane *plane; 6439 u8 hw_enabled_slices; 6440 6441 if (DISPLAY_VER(dev_priv) < 9 || !new_crtc_state->hw.active) 6442 return; 6443 6444 hw = kzalloc(sizeof(*hw), GFP_KERNEL); 6445 if (!hw) 6446 return; 6447 6448 skl_pipe_wm_get_hw_state(crtc, &hw->wm); 6449 6450 skl_pipe_ddb_get_hw_state(crtc, hw->ddb, hw->ddb_y); 6451 6452 hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv); 6453 6454 if (DISPLAY_VER(dev_priv) >= 11 && 6455 hw_enabled_slices != dev_priv->dbuf.enabled_slices) 6456 drm_err(&dev_priv->drm, 6457 "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n", 6458 dev_priv->dbuf.enabled_slices, 6459 hw_enabled_slices); 6460 6461 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 6462 const struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; 6463 const struct skl_wm_level *hw_wm_level, *sw_wm_level; 6464 6465 /* Watermarks */ 6466 for (level = 0; level <= max_level; level++) { 6467 hw_wm_level = &hw->wm.planes[plane->id].wm[level]; 6468 sw_wm_level = skl_plane_wm_level(sw_wm, plane->id, level); 6469 6470 if (skl_wm_level_equals(hw_wm_level, sw_wm_level)) 6471 continue; 6472 6473 drm_err(&dev_priv->drm, 6474 "[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 6475 plane->base.base.id, plane->base.name, level, 6476 sw_wm_level->enable, 6477 sw_wm_level->blocks, 6478 sw_wm_level->lines, 6479 hw_wm_level->enable, 6480 hw_wm_level->blocks, 6481 hw_wm_level->lines); 6482 } 6483 6484 hw_wm_level = &hw->wm.planes[plane->id].trans_wm; 6485 sw_wm_level = skl_plane_trans_wm(sw_wm, plane->id); 6486 6487 if (!skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 6488 drm_err(&dev_priv->drm, 6489 "[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 6490 plane->base.base.id, plane->base.name, 6491 sw_wm_level->enable, 6492 sw_wm_level->blocks, 6493 sw_wm_level->lines, 6494 hw_wm_level->enable, 6495 hw_wm_level->blocks, 6496 hw_wm_level->lines); 6497 } 6498 6499 hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0; 6500 sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0; 6501 6502 if (HAS_HW_SAGV_WM(dev_priv) && 6503 !skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 6504 drm_err(&dev_priv->drm, 6505 "[PLANE:%d:%s] mismatch in SAGV WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 6506 plane->base.base.id, plane->base.name, 6507 sw_wm_level->enable, 6508 sw_wm_level->blocks, 6509 sw_wm_level->lines, 6510 hw_wm_level->enable, 6511 hw_wm_level->blocks, 6512 hw_wm_level->lines); 6513 } 6514 6515 hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm; 6516 sw_wm_level = &sw_wm->planes[plane->id].sagv.trans_wm; 6517 6518 if (HAS_HW_SAGV_WM(dev_priv) && 6519 !skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 6520 drm_err(&dev_priv->drm, 6521 "[PLANE:%d:%s] mismatch in SAGV trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 6522 plane->base.base.id, plane->base.name, 6523 sw_wm_level->enable, 6524 sw_wm_level->blocks, 6525 sw_wm_level->lines, 6526 hw_wm_level->enable, 6527 hw_wm_level->blocks, 6528 hw_wm_level->lines); 6529 } 6530 6531 /* DDB */ 6532 hw_ddb_entry = &hw->ddb[PLANE_CURSOR]; 6533 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[PLANE_CURSOR]; 6534 6535 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { 6536 drm_err(&dev_priv->drm, 6537 "[PLANE:%d:%s] mismatch in DDB (expected (%u,%u), found (%u,%u))\n", 6538 plane->base.base.id, plane->base.name, 6539 sw_ddb_entry->start, sw_ddb_entry->end, 6540 hw_ddb_entry->start, hw_ddb_entry->end); 6541 } 6542 } 6543 6544 kfree(hw); 6545 } 6546 6547 static void 6548 verify_connector_state(struct intel_atomic_state *state, 6549 struct intel_crtc *crtc) 6550 { 6551 struct drm_connector *connector; 6552 struct drm_connector_state *new_conn_state; 6553 int i; 6554 6555 for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) { 6556 struct drm_encoder *encoder = connector->encoder; 6557 struct intel_crtc_state *crtc_state = NULL; 6558 6559 if (new_conn_state->crtc != &crtc->base) 6560 continue; 6561 6562 if (crtc) 6563 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6564 6565 intel_connector_verify_state(crtc_state, new_conn_state); 6566 6567 I915_STATE_WARN(new_conn_state->best_encoder != encoder, 6568 "connector's atomic encoder doesn't match legacy encoder\n"); 6569 } 6570 } 6571 6572 static void 6573 verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state) 6574 { 6575 struct intel_encoder *encoder; 6576 struct drm_connector *connector; 6577 struct drm_connector_state *old_conn_state, *new_conn_state; 6578 int i; 6579 6580 for_each_intel_encoder(&dev_priv->drm, encoder) { 6581 bool enabled = false, found = false; 6582 enum pipe pipe; 6583 6584 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n", 6585 encoder->base.base.id, 6586 encoder->base.name); 6587 6588 for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state, 6589 new_conn_state, i) { 6590 if (old_conn_state->best_encoder == &encoder->base) 6591 found = true; 6592 6593 if (new_conn_state->best_encoder != &encoder->base) 6594 continue; 6595 found = enabled = true; 6596 6597 I915_STATE_WARN(new_conn_state->crtc != 6598 encoder->base.crtc, 6599 "connector's crtc doesn't match encoder crtc\n"); 6600 } 6601 6602 if (!found) 6603 continue; 6604 6605 I915_STATE_WARN(!!encoder->base.crtc != enabled, 6606 "encoder's enabled state mismatch " 6607 "(expected %i, found %i)\n", 6608 !!encoder->base.crtc, enabled); 6609 6610 if (!encoder->base.crtc) { 6611 bool active; 6612 6613 active = encoder->get_hw_state(encoder, &pipe); 6614 I915_STATE_WARN(active, 6615 "encoder detached but still enabled on pipe %c.\n", 6616 pipe_name(pipe)); 6617 } 6618 } 6619 } 6620 6621 static void 6622 verify_crtc_state(struct intel_crtc *crtc, 6623 struct intel_crtc_state *old_crtc_state, 6624 struct intel_crtc_state *new_crtc_state) 6625 { 6626 struct drm_device *dev = crtc->base.dev; 6627 struct drm_i915_private *dev_priv = to_i915(dev); 6628 struct intel_encoder *encoder; 6629 struct intel_crtc_state *pipe_config = old_crtc_state; 6630 struct drm_atomic_state *state = old_crtc_state->uapi.state; 6631 struct intel_crtc *master_crtc; 6632 6633 __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi); 6634 intel_crtc_free_hw_state(old_crtc_state); 6635 intel_crtc_state_reset(old_crtc_state, crtc); 6636 old_crtc_state->uapi.state = state; 6637 6638 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id, 6639 crtc->base.name); 6640 6641 pipe_config->hw.enable = new_crtc_state->hw.enable; 6642 6643 intel_crtc_get_pipe_config(pipe_config); 6644 6645 /* we keep both pipes enabled on 830 */ 6646 if (IS_I830(dev_priv) && pipe_config->hw.active) 6647 pipe_config->hw.active = new_crtc_state->hw.active; 6648 6649 I915_STATE_WARN(new_crtc_state->hw.active != pipe_config->hw.active, 6650 "crtc active state doesn't match with hw state " 6651 "(expected %i, found %i)\n", 6652 new_crtc_state->hw.active, pipe_config->hw.active); 6653 6654 I915_STATE_WARN(crtc->active != new_crtc_state->hw.active, 6655 "transitional active state does not match atomic hw state " 6656 "(expected %i, found %i)\n", 6657 new_crtc_state->hw.active, crtc->active); 6658 6659 master_crtc = intel_master_crtc(new_crtc_state); 6660 6661 for_each_encoder_on_crtc(dev, &master_crtc->base, encoder) { 6662 enum pipe pipe; 6663 bool active; 6664 6665 active = encoder->get_hw_state(encoder, &pipe); 6666 I915_STATE_WARN(active != new_crtc_state->hw.active, 6667 "[ENCODER:%i] active %i with crtc active %i\n", 6668 encoder->base.base.id, active, 6669 new_crtc_state->hw.active); 6670 6671 I915_STATE_WARN(active && master_crtc->pipe != pipe, 6672 "Encoder connected to wrong pipe %c\n", 6673 pipe_name(pipe)); 6674 6675 if (active) 6676 intel_encoder_get_config(encoder, pipe_config); 6677 } 6678 6679 if (!new_crtc_state->hw.active) 6680 return; 6681 6682 intel_pipe_config_sanity_check(dev_priv, pipe_config); 6683 6684 if (!intel_pipe_config_compare(new_crtc_state, 6685 pipe_config, false)) { 6686 I915_STATE_WARN(1, "pipe state doesn't match!\n"); 6687 intel_dump_pipe_config(pipe_config, NULL, "[hw state]"); 6688 intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]"); 6689 } 6690 } 6691 6692 static void 6693 intel_verify_planes(struct intel_atomic_state *state) 6694 { 6695 struct intel_plane *plane; 6696 const struct intel_plane_state *plane_state; 6697 int i; 6698 6699 for_each_new_intel_plane_in_state(state, plane, 6700 plane_state, i) 6701 assert_plane(plane, plane_state->planar_slave || 6702 plane_state->uapi.visible); 6703 } 6704 6705 static void 6706 verify_single_dpll_state(struct drm_i915_private *dev_priv, 6707 struct intel_shared_dpll *pll, 6708 struct intel_crtc *crtc, 6709 struct intel_crtc_state *new_crtc_state) 6710 { 6711 struct intel_dpll_hw_state dpll_hw_state; 6712 u8 pipe_mask; 6713 bool active; 6714 6715 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); 6716 6717 drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name); 6718 6719 active = intel_dpll_get_hw_state(dev_priv, pll, &dpll_hw_state); 6720 6721 if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) { 6722 I915_STATE_WARN(!pll->on && pll->active_mask, 6723 "pll in active use but not on in sw tracking\n"); 6724 I915_STATE_WARN(pll->on && !pll->active_mask, 6725 "pll is on but not used by any active pipe\n"); 6726 I915_STATE_WARN(pll->on != active, 6727 "pll on state mismatch (expected %i, found %i)\n", 6728 pll->on, active); 6729 } 6730 6731 if (!crtc) { 6732 I915_STATE_WARN(pll->active_mask & ~pll->state.pipe_mask, 6733 "more active pll users than references: 0x%x vs 0x%x\n", 6734 pll->active_mask, pll->state.pipe_mask); 6735 6736 return; 6737 } 6738 6739 pipe_mask = BIT(crtc->pipe); 6740 6741 if (new_crtc_state->hw.active) 6742 I915_STATE_WARN(!(pll->active_mask & pipe_mask), 6743 "pll active mismatch (expected pipe %c in active mask 0x%x)\n", 6744 pipe_name(crtc->pipe), pll->active_mask); 6745 else 6746 I915_STATE_WARN(pll->active_mask & pipe_mask, 6747 "pll active mismatch (didn't expect pipe %c in active mask 0x%x)\n", 6748 pipe_name(crtc->pipe), pll->active_mask); 6749 6750 I915_STATE_WARN(!(pll->state.pipe_mask & pipe_mask), 6751 "pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n", 6752 pipe_mask, pll->state.pipe_mask); 6753 6754 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state, 6755 &dpll_hw_state, 6756 sizeof(dpll_hw_state)), 6757 "pll hw state mismatch\n"); 6758 } 6759 6760 static void 6761 verify_shared_dpll_state(struct intel_crtc *crtc, 6762 struct intel_crtc_state *old_crtc_state, 6763 struct intel_crtc_state *new_crtc_state) 6764 { 6765 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6766 6767 if (new_crtc_state->shared_dpll) 6768 verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state); 6769 6770 if (old_crtc_state->shared_dpll && 6771 old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) { 6772 u8 pipe_mask = BIT(crtc->pipe); 6773 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll; 6774 6775 I915_STATE_WARN(pll->active_mask & pipe_mask, 6776 "pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n", 6777 pipe_name(crtc->pipe), pll->active_mask); 6778 I915_STATE_WARN(pll->state.pipe_mask & pipe_mask, 6779 "pll enabled crtcs mismatch (found %x in enabled mask (0x%x))\n", 6780 pipe_name(crtc->pipe), pll->state.pipe_mask); 6781 } 6782 } 6783 6784 static void 6785 verify_mpllb_state(struct intel_atomic_state *state, 6786 struct intel_crtc_state *new_crtc_state) 6787 { 6788 struct drm_i915_private *i915 = to_i915(state->base.dev); 6789 struct intel_mpllb_state mpllb_hw_state = { 0 }; 6790 struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->mpllb_state; 6791 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 6792 struct intel_encoder *encoder; 6793 6794 if (!IS_DG2(i915)) 6795 return; 6796 6797 if (!new_crtc_state->hw.active) 6798 return; 6799 6800 encoder = intel_get_crtc_new_encoder(state, new_crtc_state); 6801 intel_mpllb_readout_hw_state(encoder, &mpllb_hw_state); 6802 6803 #define MPLLB_CHECK(name) do { \ 6804 if (mpllb_sw_state->name != mpllb_hw_state.name) { \ 6805 pipe_config_mismatch(false, crtc, "MPLLB:" __stringify(name), \ 6806 "(expected 0x%08x, found 0x%08x)", \ 6807 mpllb_sw_state->name, \ 6808 mpllb_hw_state.name); \ 6809 } \ 6810 } while (0) 6811 6812 MPLLB_CHECK(mpllb_cp); 6813 MPLLB_CHECK(mpllb_div); 6814 MPLLB_CHECK(mpllb_div2); 6815 MPLLB_CHECK(mpllb_fracn1); 6816 MPLLB_CHECK(mpllb_fracn2); 6817 MPLLB_CHECK(mpllb_sscen); 6818 MPLLB_CHECK(mpllb_sscstep); 6819 6820 /* 6821 * ref_control is handled by the hardware/firemware and never 6822 * programmed by the software, but the proper values are supplied 6823 * in the bspec for verification purposes. 6824 */ 6825 MPLLB_CHECK(ref_control); 6826 6827 #undef MPLLB_CHECK 6828 } 6829 6830 static void 6831 intel_modeset_verify_crtc(struct intel_crtc *crtc, 6832 struct intel_atomic_state *state, 6833 struct intel_crtc_state *old_crtc_state, 6834 struct intel_crtc_state *new_crtc_state) 6835 { 6836 if (!intel_crtc_needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe) 6837 return; 6838 6839 verify_wm_state(crtc, new_crtc_state); 6840 verify_connector_state(state, crtc); 6841 verify_crtc_state(crtc, old_crtc_state, new_crtc_state); 6842 verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state); 6843 verify_mpllb_state(state, new_crtc_state); 6844 } 6845 6846 static void 6847 verify_disabled_dpll_state(struct drm_i915_private *dev_priv) 6848 { 6849 int i; 6850 6851 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) 6852 verify_single_dpll_state(dev_priv, 6853 &dev_priv->dpll.shared_dplls[i], 6854 NULL, NULL); 6855 } 6856 6857 static void 6858 intel_modeset_verify_disabled(struct drm_i915_private *dev_priv, 6859 struct intel_atomic_state *state) 6860 { 6861 verify_encoder_state(dev_priv, state); 6862 verify_connector_state(state, NULL); 6863 verify_disabled_dpll_state(dev_priv); 6864 } 6865 6866 int intel_modeset_all_pipes(struct intel_atomic_state *state) 6867 { 6868 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6869 struct intel_crtc *crtc; 6870 6871 /* 6872 * Add all pipes to the state, and force 6873 * a modeset on all the active ones. 6874 */ 6875 for_each_intel_crtc(&dev_priv->drm, crtc) { 6876 struct intel_crtc_state *crtc_state; 6877 int ret; 6878 6879 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6880 if (IS_ERR(crtc_state)) 6881 return PTR_ERR(crtc_state); 6882 6883 if (!crtc_state->hw.active || 6884 drm_atomic_crtc_needs_modeset(&crtc_state->uapi)) 6885 continue; 6886 6887 crtc_state->uapi.mode_changed = true; 6888 6889 ret = drm_atomic_add_affected_connectors(&state->base, 6890 &crtc->base); 6891 if (ret) 6892 return ret; 6893 6894 ret = intel_atomic_add_affected_planes(state, crtc); 6895 if (ret) 6896 return ret; 6897 6898 crtc_state->update_planes |= crtc_state->active_planes; 6899 } 6900 6901 return 0; 6902 } 6903 6904 static void 6905 intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state) 6906 { 6907 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 6908 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6909 struct drm_display_mode adjusted_mode; 6910 6911 drm_mode_init(&adjusted_mode, &crtc_state->hw.adjusted_mode); 6912 6913 if (crtc_state->vrr.enable) { 6914 adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax; 6915 adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax; 6916 adjusted_mode.crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state); 6917 crtc->vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state); 6918 } 6919 6920 drm_calc_timestamping_constants(&crtc->base, &adjusted_mode); 6921 6922 crtc->mode_flags = crtc_state->mode_flags; 6923 6924 /* 6925 * The scanline counter increments at the leading edge of hsync. 6926 * 6927 * On most platforms it starts counting from vtotal-1 on the 6928 * first active line. That means the scanline counter value is 6929 * always one less than what we would expect. Ie. just after 6930 * start of vblank, which also occurs at start of hsync (on the 6931 * last active line), the scanline counter will read vblank_start-1. 6932 * 6933 * On gen2 the scanline counter starts counting from 1 instead 6934 * of vtotal-1, so we have to subtract one (or rather add vtotal-1 6935 * to keep the value positive), instead of adding one. 6936 * 6937 * On HSW+ the behaviour of the scanline counter depends on the output 6938 * type. For DP ports it behaves like most other platforms, but on HDMI 6939 * there's an extra 1 line difference. So we need to add two instead of 6940 * one to the value. 6941 * 6942 * On VLV/CHV DSI the scanline counter would appear to increment 6943 * approx. 1/3 of a scanline before start of vblank. Unfortunately 6944 * that means we can't tell whether we're in vblank or not while 6945 * we're on that particular line. We must still set scanline_offset 6946 * to 1 so that the vblank timestamps come out correct when we query 6947 * the scanline counter from within the vblank interrupt handler. 6948 * However if queried just before the start of vblank we'll get an 6949 * answer that's slightly in the future. 6950 */ 6951 if (DISPLAY_VER(dev_priv) == 2) { 6952 int vtotal; 6953 6954 vtotal = adjusted_mode.crtc_vtotal; 6955 if (adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 6956 vtotal /= 2; 6957 6958 crtc->scanline_offset = vtotal - 1; 6959 } else if (HAS_DDI(dev_priv) && 6960 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 6961 crtc->scanline_offset = 2; 6962 } else { 6963 crtc->scanline_offset = 1; 6964 } 6965 } 6966 6967 static void intel_modeset_clear_plls(struct intel_atomic_state *state) 6968 { 6969 struct intel_crtc_state *new_crtc_state; 6970 struct intel_crtc *crtc; 6971 int i; 6972 6973 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6974 if (!intel_crtc_needs_modeset(new_crtc_state)) 6975 continue; 6976 6977 intel_release_shared_dplls(state, crtc); 6978 } 6979 } 6980 6981 /* 6982 * This implements the workaround described in the "notes" section of the mode 6983 * set sequence documentation. When going from no pipes or single pipe to 6984 * multiple pipes, and planes are enabled after the pipe, we need to wait at 6985 * least 2 vblanks on the first pipe before enabling planes on the second pipe. 6986 */ 6987 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state) 6988 { 6989 struct intel_crtc_state *crtc_state; 6990 struct intel_crtc *crtc; 6991 struct intel_crtc_state *first_crtc_state = NULL; 6992 struct intel_crtc_state *other_crtc_state = NULL; 6993 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; 6994 int i; 6995 6996 /* look at all crtc's that are going to be enabled in during modeset */ 6997 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6998 if (!crtc_state->hw.active || 6999 !intel_crtc_needs_modeset(crtc_state)) 7000 continue; 7001 7002 if (first_crtc_state) { 7003 other_crtc_state = crtc_state; 7004 break; 7005 } else { 7006 first_crtc_state = crtc_state; 7007 first_pipe = crtc->pipe; 7008 } 7009 } 7010 7011 /* No workaround needed? */ 7012 if (!first_crtc_state) 7013 return 0; 7014 7015 /* w/a possibly needed, check how many crtc's are already enabled. */ 7016 for_each_intel_crtc(state->base.dev, crtc) { 7017 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 7018 if (IS_ERR(crtc_state)) 7019 return PTR_ERR(crtc_state); 7020 7021 crtc_state->hsw_workaround_pipe = INVALID_PIPE; 7022 7023 if (!crtc_state->hw.active || 7024 intel_crtc_needs_modeset(crtc_state)) 7025 continue; 7026 7027 /* 2 or more enabled crtcs means no need for w/a */ 7028 if (enabled_pipe != INVALID_PIPE) 7029 return 0; 7030 7031 enabled_pipe = crtc->pipe; 7032 } 7033 7034 if (enabled_pipe != INVALID_PIPE) 7035 first_crtc_state->hsw_workaround_pipe = enabled_pipe; 7036 else if (other_crtc_state) 7037 other_crtc_state->hsw_workaround_pipe = first_pipe; 7038 7039 return 0; 7040 } 7041 7042 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 7043 u8 active_pipes) 7044 { 7045 const struct intel_crtc_state *crtc_state; 7046 struct intel_crtc *crtc; 7047 int i; 7048 7049 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7050 if (crtc_state->hw.active) 7051 active_pipes |= BIT(crtc->pipe); 7052 else 7053 active_pipes &= ~BIT(crtc->pipe); 7054 } 7055 7056 return active_pipes; 7057 } 7058 7059 static int intel_modeset_checks(struct intel_atomic_state *state) 7060 { 7061 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7062 7063 state->modeset = true; 7064 7065 if (IS_HASWELL(dev_priv)) 7066 return hsw_mode_set_planes_workaround(state); 7067 7068 return 0; 7069 } 7070 7071 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state, 7072 struct intel_crtc_state *new_crtc_state) 7073 { 7074 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) 7075 return; 7076 7077 new_crtc_state->uapi.mode_changed = false; 7078 new_crtc_state->update_pipe = true; 7079 } 7080 7081 static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state, 7082 struct intel_crtc_state *new_crtc_state) 7083 { 7084 /* 7085 * If we're not doing the full modeset we want to 7086 * keep the current M/N values as they may be 7087 * sufficiently different to the computed values 7088 * to cause problems. 7089 * 7090 * FIXME: should really copy more fuzzy state here 7091 */ 7092 new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n; 7093 new_crtc_state->dp_m_n = old_crtc_state->dp_m_n; 7094 new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2; 7095 new_crtc_state->has_drrs = old_crtc_state->has_drrs; 7096 } 7097 7098 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state, 7099 struct intel_crtc *crtc, 7100 u8 plane_ids_mask) 7101 { 7102 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7103 struct intel_plane *plane; 7104 7105 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 7106 struct intel_plane_state *plane_state; 7107 7108 if ((plane_ids_mask & BIT(plane->id)) == 0) 7109 continue; 7110 7111 plane_state = intel_atomic_get_plane_state(state, plane); 7112 if (IS_ERR(plane_state)) 7113 return PTR_ERR(plane_state); 7114 } 7115 7116 return 0; 7117 } 7118 7119 int intel_atomic_add_affected_planes(struct intel_atomic_state *state, 7120 struct intel_crtc *crtc) 7121 { 7122 const struct intel_crtc_state *old_crtc_state = 7123 intel_atomic_get_old_crtc_state(state, crtc); 7124 const struct intel_crtc_state *new_crtc_state = 7125 intel_atomic_get_new_crtc_state(state, crtc); 7126 7127 return intel_crtc_add_planes_to_state(state, crtc, 7128 old_crtc_state->enabled_planes | 7129 new_crtc_state->enabled_planes); 7130 } 7131 7132 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv) 7133 { 7134 /* See {hsw,vlv,ivb}_plane_ratio() */ 7135 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) || 7136 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) || 7137 IS_IVYBRIDGE(dev_priv); 7138 } 7139 7140 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state, 7141 struct intel_crtc *crtc, 7142 struct intel_crtc *other) 7143 { 7144 const struct intel_plane_state *plane_state; 7145 struct intel_plane *plane; 7146 u8 plane_ids = 0; 7147 int i; 7148 7149 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 7150 if (plane->pipe == crtc->pipe) 7151 plane_ids |= BIT(plane->id); 7152 } 7153 7154 return intel_crtc_add_planes_to_state(state, other, plane_ids); 7155 } 7156 7157 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state) 7158 { 7159 struct drm_i915_private *i915 = to_i915(state->base.dev); 7160 const struct intel_crtc_state *crtc_state; 7161 struct intel_crtc *crtc; 7162 int i; 7163 7164 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7165 struct intel_crtc *other; 7166 7167 for_each_intel_crtc_in_pipe_mask(&i915->drm, other, 7168 crtc_state->bigjoiner_pipes) { 7169 int ret; 7170 7171 if (crtc == other) 7172 continue; 7173 7174 ret = intel_crtc_add_bigjoiner_planes(state, crtc, other); 7175 if (ret) 7176 return ret; 7177 } 7178 } 7179 7180 return 0; 7181 } 7182 7183 static int intel_atomic_check_planes(struct intel_atomic_state *state) 7184 { 7185 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7186 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7187 struct intel_plane_state *plane_state; 7188 struct intel_plane *plane; 7189 struct intel_crtc *crtc; 7190 int i, ret; 7191 7192 ret = icl_add_linked_planes(state); 7193 if (ret) 7194 return ret; 7195 7196 ret = intel_bigjoiner_add_affected_planes(state); 7197 if (ret) 7198 return ret; 7199 7200 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 7201 ret = intel_plane_atomic_check(state, plane); 7202 if (ret) { 7203 drm_dbg_atomic(&dev_priv->drm, 7204 "[PLANE:%d:%s] atomic driver check failed\n", 7205 plane->base.base.id, plane->base.name); 7206 return ret; 7207 } 7208 } 7209 7210 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7211 new_crtc_state, i) { 7212 u8 old_active_planes, new_active_planes; 7213 7214 ret = icl_check_nv12_planes(new_crtc_state); 7215 if (ret) 7216 return ret; 7217 7218 /* 7219 * On some platforms the number of active planes affects 7220 * the planes' minimum cdclk calculation. Add such planes 7221 * to the state before we compute the minimum cdclk. 7222 */ 7223 if (!active_planes_affects_min_cdclk(dev_priv)) 7224 continue; 7225 7226 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 7227 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 7228 7229 if (hweight8(old_active_planes) == hweight8(new_active_planes)) 7230 continue; 7231 7232 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes); 7233 if (ret) 7234 return ret; 7235 } 7236 7237 return 0; 7238 } 7239 7240 static int intel_atomic_check_crtcs(struct intel_atomic_state *state) 7241 { 7242 struct intel_crtc_state *crtc_state; 7243 struct intel_crtc *crtc; 7244 int i; 7245 7246 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7247 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 7248 int ret; 7249 7250 ret = intel_crtc_atomic_check(state, crtc); 7251 if (ret) { 7252 drm_dbg_atomic(&i915->drm, 7253 "[CRTC:%d:%s] atomic driver check failed\n", 7254 crtc->base.base.id, crtc->base.name); 7255 return ret; 7256 } 7257 } 7258 7259 return 0; 7260 } 7261 7262 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, 7263 u8 transcoders) 7264 { 7265 const struct intel_crtc_state *new_crtc_state; 7266 struct intel_crtc *crtc; 7267 int i; 7268 7269 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7270 if (new_crtc_state->hw.enable && 7271 transcoders & BIT(new_crtc_state->cpu_transcoder) && 7272 intel_crtc_needs_modeset(new_crtc_state)) 7273 return true; 7274 } 7275 7276 return false; 7277 } 7278 7279 static bool intel_pipes_need_modeset(struct intel_atomic_state *state, 7280 u8 pipes) 7281 { 7282 const struct intel_crtc_state *new_crtc_state; 7283 struct intel_crtc *crtc; 7284 int i; 7285 7286 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7287 if (new_crtc_state->hw.enable && 7288 pipes & BIT(crtc->pipe) && 7289 intel_crtc_needs_modeset(new_crtc_state)) 7290 return true; 7291 } 7292 7293 return false; 7294 } 7295 7296 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state, 7297 struct intel_crtc *master_crtc) 7298 { 7299 struct drm_i915_private *i915 = to_i915(state->base.dev); 7300 struct intel_crtc_state *master_crtc_state = 7301 intel_atomic_get_new_crtc_state(state, master_crtc); 7302 struct intel_crtc *slave_crtc; 7303 7304 if (!master_crtc_state->bigjoiner_pipes) 7305 return 0; 7306 7307 /* sanity check */ 7308 if (drm_WARN_ON(&i915->drm, 7309 master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state))) 7310 return -EINVAL; 7311 7312 if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) { 7313 drm_dbg_kms(&i915->drm, 7314 "[CRTC:%d:%s] Cannot act as big joiner master " 7315 "(need 0x%x as pipes, only 0x%x possible)\n", 7316 master_crtc->base.base.id, master_crtc->base.name, 7317 master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915)); 7318 return -EINVAL; 7319 } 7320 7321 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 7322 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 7323 struct intel_crtc_state *slave_crtc_state; 7324 int ret; 7325 7326 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc); 7327 if (IS_ERR(slave_crtc_state)) 7328 return PTR_ERR(slave_crtc_state); 7329 7330 /* master being enabled, slave was already configured? */ 7331 if (slave_crtc_state->uapi.enable) { 7332 drm_dbg_kms(&i915->drm, 7333 "[CRTC:%d:%s] Slave is enabled as normal CRTC, but " 7334 "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n", 7335 slave_crtc->base.base.id, slave_crtc->base.name, 7336 master_crtc->base.base.id, master_crtc->base.name); 7337 return -EINVAL; 7338 } 7339 7340 /* 7341 * The state copy logic assumes the master crtc gets processed 7342 * before the slave crtc during the main compute_config loop. 7343 * This works because the crtcs are created in pipe order, 7344 * and the hardware requires master pipe < slave pipe as well. 7345 * Should that change we need to rethink the logic. 7346 */ 7347 if (WARN_ON(drm_crtc_index(&master_crtc->base) > 7348 drm_crtc_index(&slave_crtc->base))) 7349 return -EINVAL; 7350 7351 drm_dbg_kms(&i915->drm, 7352 "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n", 7353 slave_crtc->base.base.id, slave_crtc->base.name, 7354 master_crtc->base.base.id, master_crtc->base.name); 7355 7356 slave_crtc_state->bigjoiner_pipes = 7357 master_crtc_state->bigjoiner_pipes; 7358 7359 ret = copy_bigjoiner_crtc_state_modeset(state, slave_crtc); 7360 if (ret) 7361 return ret; 7362 } 7363 7364 return 0; 7365 } 7366 7367 static void kill_bigjoiner_slave(struct intel_atomic_state *state, 7368 struct intel_crtc *master_crtc) 7369 { 7370 struct drm_i915_private *i915 = to_i915(state->base.dev); 7371 struct intel_crtc_state *master_crtc_state = 7372 intel_atomic_get_new_crtc_state(state, master_crtc); 7373 struct intel_crtc *slave_crtc; 7374 7375 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 7376 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 7377 struct intel_crtc_state *slave_crtc_state = 7378 intel_atomic_get_new_crtc_state(state, slave_crtc); 7379 7380 slave_crtc_state->bigjoiner_pipes = 0; 7381 7382 intel_crtc_copy_uapi_to_hw_state_modeset(state, slave_crtc); 7383 } 7384 7385 master_crtc_state->bigjoiner_pipes = 0; 7386 } 7387 7388 /** 7389 * DOC: asynchronous flip implementation 7390 * 7391 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC 7392 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL. 7393 * Correspondingly, support is currently added for primary plane only. 7394 * 7395 * Async flip can only change the plane surface address, so anything else 7396 * changing is rejected from the intel_async_flip_check_hw() function. 7397 * Once this check is cleared, flip done interrupt is enabled using 7398 * the intel_crtc_enable_flip_done() function. 7399 * 7400 * As soon as the surface address register is written, flip done interrupt is 7401 * generated and the requested events are sent to the usersapce in the interrupt 7402 * handler itself. The timestamp and sequence sent during the flip done event 7403 * correspond to the last vblank and have no relation to the actual time when 7404 * the flip done event was sent. 7405 */ 7406 static int intel_async_flip_check_uapi(struct intel_atomic_state *state, 7407 struct intel_crtc *crtc) 7408 { 7409 struct drm_i915_private *i915 = to_i915(state->base.dev); 7410 const struct intel_crtc_state *new_crtc_state = 7411 intel_atomic_get_new_crtc_state(state, crtc); 7412 const struct intel_plane_state *old_plane_state; 7413 struct intel_plane_state *new_plane_state; 7414 struct intel_plane *plane; 7415 int i; 7416 7417 if (!new_crtc_state->uapi.async_flip) 7418 return 0; 7419 7420 if (!new_crtc_state->uapi.active) { 7421 drm_dbg_kms(&i915->drm, 7422 "[CRTC:%d:%s] not active\n", 7423 crtc->base.base.id, crtc->base.name); 7424 return -EINVAL; 7425 } 7426 7427 if (intel_crtc_needs_modeset(new_crtc_state)) { 7428 drm_dbg_kms(&i915->drm, 7429 "[CRTC:%d:%s] modeset required\n", 7430 crtc->base.base.id, crtc->base.name); 7431 return -EINVAL; 7432 } 7433 7434 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 7435 new_plane_state, i) { 7436 if (plane->pipe != crtc->pipe) 7437 continue; 7438 7439 /* 7440 * TODO: Async flip is only supported through the page flip IOCTL 7441 * as of now. So support currently added for primary plane only. 7442 * Support for other planes on platforms on which supports 7443 * this(vlv/chv and icl+) should be added when async flip is 7444 * enabled in the atomic IOCTL path. 7445 */ 7446 if (!plane->async_flip) { 7447 drm_dbg_kms(&i915->drm, 7448 "[PLANE:%d:%s] async flip not supported\n", 7449 plane->base.base.id, plane->base.name); 7450 return -EINVAL; 7451 } 7452 7453 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) { 7454 drm_dbg_kms(&i915->drm, 7455 "[PLANE:%d:%s] no old or new framebuffer\n", 7456 plane->base.base.id, plane->base.name); 7457 return -EINVAL; 7458 } 7459 } 7460 7461 return 0; 7462 } 7463 7464 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc) 7465 { 7466 struct drm_i915_private *i915 = to_i915(state->base.dev); 7467 const struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7468 const struct intel_plane_state *new_plane_state, *old_plane_state; 7469 struct intel_plane *plane; 7470 int i; 7471 7472 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 7473 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 7474 7475 if (!new_crtc_state->uapi.async_flip) 7476 return 0; 7477 7478 if (!new_crtc_state->hw.active) { 7479 drm_dbg_kms(&i915->drm, 7480 "[CRTC:%d:%s] not active\n", 7481 crtc->base.base.id, crtc->base.name); 7482 return -EINVAL; 7483 } 7484 7485 if (intel_crtc_needs_modeset(new_crtc_state)) { 7486 drm_dbg_kms(&i915->drm, 7487 "[CRTC:%d:%s] modeset required\n", 7488 crtc->base.base.id, crtc->base.name); 7489 return -EINVAL; 7490 } 7491 7492 if (old_crtc_state->active_planes != new_crtc_state->active_planes) { 7493 drm_dbg_kms(&i915->drm, 7494 "[CRTC:%d:%s] Active planes cannot be in async flip\n", 7495 crtc->base.base.id, crtc->base.name); 7496 return -EINVAL; 7497 } 7498 7499 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 7500 new_plane_state, i) { 7501 if (plane->pipe != crtc->pipe) 7502 continue; 7503 7504 /* 7505 * Only async flip capable planes should be in the state 7506 * if we're really about to ask the hardware to perform 7507 * an async flip. We should never get this far otherwise. 7508 */ 7509 if (drm_WARN_ON(&i915->drm, 7510 new_crtc_state->do_async_flip && !plane->async_flip)) 7511 return -EINVAL; 7512 7513 /* 7514 * Only check async flip capable planes other planes 7515 * may be involved in the initial commit due to 7516 * the wm0/ddb optimization. 7517 * 7518 * TODO maybe should track which planes actually 7519 * were requested to do the async flip... 7520 */ 7521 if (!plane->async_flip) 7522 continue; 7523 7524 /* 7525 * FIXME: This check is kept generic for all platforms. 7526 * Need to verify this for all gen9 platforms to enable 7527 * this selectively if required. 7528 */ 7529 switch (new_plane_state->hw.fb->modifier) { 7530 case I915_FORMAT_MOD_X_TILED: 7531 case I915_FORMAT_MOD_Y_TILED: 7532 case I915_FORMAT_MOD_Yf_TILED: 7533 case I915_FORMAT_MOD_4_TILED: 7534 break; 7535 default: 7536 drm_dbg_kms(&i915->drm, 7537 "[PLANE:%d:%s] Modifier does not support async flips\n", 7538 plane->base.base.id, plane->base.name); 7539 return -EINVAL; 7540 } 7541 7542 if (new_plane_state->hw.fb->format->num_planes > 1) { 7543 drm_dbg_kms(&i915->drm, 7544 "[PLANE:%d:%s] Planar formats do not support async flips\n", 7545 plane->base.base.id, plane->base.name); 7546 return -EINVAL; 7547 } 7548 7549 if (old_plane_state->view.color_plane[0].mapping_stride != 7550 new_plane_state->view.color_plane[0].mapping_stride) { 7551 drm_dbg_kms(&i915->drm, 7552 "[PLANE:%d:%s] Stride cannot be changed in async flip\n", 7553 plane->base.base.id, plane->base.name); 7554 return -EINVAL; 7555 } 7556 7557 if (old_plane_state->hw.fb->modifier != 7558 new_plane_state->hw.fb->modifier) { 7559 drm_dbg_kms(&i915->drm, 7560 "[PLANE:%d:%s] Modifier cannot be changed in async flip\n", 7561 plane->base.base.id, plane->base.name); 7562 return -EINVAL; 7563 } 7564 7565 if (old_plane_state->hw.fb->format != 7566 new_plane_state->hw.fb->format) { 7567 drm_dbg_kms(&i915->drm, 7568 "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n", 7569 plane->base.base.id, plane->base.name); 7570 return -EINVAL; 7571 } 7572 7573 if (old_plane_state->hw.rotation != 7574 new_plane_state->hw.rotation) { 7575 drm_dbg_kms(&i915->drm, 7576 "[PLANE:%d:%s] Rotation cannot be changed in async flip\n", 7577 plane->base.base.id, plane->base.name); 7578 return -EINVAL; 7579 } 7580 7581 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) || 7582 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) { 7583 drm_dbg_kms(&i915->drm, 7584 "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n", 7585 plane->base.base.id, plane->base.name); 7586 return -EINVAL; 7587 } 7588 7589 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) { 7590 drm_dbg_kms(&i915->drm, 7591 "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n", 7592 plane->base.base.id, plane->base.name); 7593 return -EINVAL; 7594 } 7595 7596 if (old_plane_state->hw.pixel_blend_mode != 7597 new_plane_state->hw.pixel_blend_mode) { 7598 drm_dbg_kms(&i915->drm, 7599 "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n", 7600 plane->base.base.id, plane->base.name); 7601 return -EINVAL; 7602 } 7603 7604 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) { 7605 drm_dbg_kms(&i915->drm, 7606 "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n", 7607 plane->base.base.id, plane->base.name); 7608 return -EINVAL; 7609 } 7610 7611 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) { 7612 drm_dbg_kms(&i915->drm, 7613 "[PLANE:%d:%s] Color range cannot be changed in async flip\n", 7614 plane->base.base.id, plane->base.name); 7615 return -EINVAL; 7616 } 7617 7618 /* plane decryption is allow to change only in synchronous flips */ 7619 if (old_plane_state->decrypt != new_plane_state->decrypt) { 7620 drm_dbg_kms(&i915->drm, 7621 "[PLANE:%d:%s] Decryption cannot be changed in async flip\n", 7622 plane->base.base.id, plane->base.name); 7623 return -EINVAL; 7624 } 7625 } 7626 7627 return 0; 7628 } 7629 7630 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state) 7631 { 7632 struct drm_i915_private *i915 = to_i915(state->base.dev); 7633 struct intel_crtc_state *crtc_state; 7634 struct intel_crtc *crtc; 7635 u8 affected_pipes = 0; 7636 u8 modeset_pipes = 0; 7637 int i; 7638 7639 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7640 affected_pipes |= crtc_state->bigjoiner_pipes; 7641 if (intel_crtc_needs_modeset(crtc_state)) 7642 modeset_pipes |= crtc_state->bigjoiner_pipes; 7643 } 7644 7645 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) { 7646 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 7647 if (IS_ERR(crtc_state)) 7648 return PTR_ERR(crtc_state); 7649 } 7650 7651 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) { 7652 int ret; 7653 7654 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 7655 7656 crtc_state->uapi.mode_changed = true; 7657 7658 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); 7659 if (ret) 7660 return ret; 7661 7662 ret = intel_atomic_add_affected_planes(state, crtc); 7663 if (ret) 7664 return ret; 7665 } 7666 7667 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7668 /* Kill old bigjoiner link, we may re-establish afterwards */ 7669 if (intel_crtc_needs_modeset(crtc_state) && 7670 intel_crtc_is_bigjoiner_master(crtc_state)) 7671 kill_bigjoiner_slave(state, crtc); 7672 } 7673 7674 return 0; 7675 } 7676 7677 /** 7678 * intel_atomic_check - validate state object 7679 * @dev: drm device 7680 * @_state: state to validate 7681 */ 7682 static int intel_atomic_check(struct drm_device *dev, 7683 struct drm_atomic_state *_state) 7684 { 7685 struct drm_i915_private *dev_priv = to_i915(dev); 7686 struct intel_atomic_state *state = to_intel_atomic_state(_state); 7687 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7688 struct intel_crtc *crtc; 7689 int ret, i; 7690 bool any_ms = false; 7691 7692 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7693 new_crtc_state, i) { 7694 if (new_crtc_state->inherited != old_crtc_state->inherited) 7695 new_crtc_state->uapi.mode_changed = true; 7696 7697 if (new_crtc_state->uapi.scaling_filter != 7698 old_crtc_state->uapi.scaling_filter) 7699 new_crtc_state->uapi.mode_changed = true; 7700 } 7701 7702 intel_vrr_check_modeset(state); 7703 7704 ret = drm_atomic_helper_check_modeset(dev, &state->base); 7705 if (ret) 7706 goto fail; 7707 7708 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7709 ret = intel_async_flip_check_uapi(state, crtc); 7710 if (ret) 7711 return ret; 7712 } 7713 7714 ret = intel_bigjoiner_add_affected_crtcs(state); 7715 if (ret) 7716 goto fail; 7717 7718 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7719 new_crtc_state, i) { 7720 if (!intel_crtc_needs_modeset(new_crtc_state)) { 7721 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 7722 copy_bigjoiner_crtc_state_nomodeset(state, crtc); 7723 else 7724 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 7725 continue; 7726 } 7727 7728 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) { 7729 drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable); 7730 continue; 7731 } 7732 7733 ret = intel_crtc_prepare_cleared_state(state, crtc); 7734 if (ret) 7735 goto fail; 7736 7737 if (!new_crtc_state->hw.enable) 7738 continue; 7739 7740 ret = intel_modeset_pipe_config(state, crtc); 7741 if (ret) 7742 goto fail; 7743 7744 ret = intel_atomic_check_bigjoiner(state, crtc); 7745 if (ret) 7746 goto fail; 7747 } 7748 7749 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7750 new_crtc_state, i) { 7751 if (!intel_crtc_needs_modeset(new_crtc_state)) 7752 continue; 7753 7754 ret = intel_modeset_pipe_config_late(state, crtc); 7755 if (ret) 7756 goto fail; 7757 7758 intel_crtc_check_fastset(old_crtc_state, new_crtc_state); 7759 } 7760 7761 /** 7762 * Check if fastset is allowed by external dependencies like other 7763 * pipes and transcoders. 7764 * 7765 * Right now it only forces a fullmodeset when the MST master 7766 * transcoder did not changed but the pipe of the master transcoder 7767 * needs a fullmodeset so all slaves also needs to do a fullmodeset or 7768 * in case of port synced crtcs, if one of the synced crtcs 7769 * needs a full modeset, all other synced crtcs should be 7770 * forced a full modeset. 7771 */ 7772 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7773 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state)) 7774 continue; 7775 7776 if (intel_dp_mst_is_slave_trans(new_crtc_state)) { 7777 enum transcoder master = new_crtc_state->mst_master_transcoder; 7778 7779 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) { 7780 new_crtc_state->uapi.mode_changed = true; 7781 new_crtc_state->update_pipe = false; 7782 } 7783 } 7784 7785 if (is_trans_port_sync_mode(new_crtc_state)) { 7786 u8 trans = new_crtc_state->sync_mode_slaves_mask; 7787 7788 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER) 7789 trans |= BIT(new_crtc_state->master_transcoder); 7790 7791 if (intel_cpu_transcoders_need_modeset(state, trans)) { 7792 new_crtc_state->uapi.mode_changed = true; 7793 new_crtc_state->update_pipe = false; 7794 } 7795 } 7796 7797 if (new_crtc_state->bigjoiner_pipes) { 7798 if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) { 7799 new_crtc_state->uapi.mode_changed = true; 7800 new_crtc_state->update_pipe = false; 7801 } 7802 } 7803 } 7804 7805 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7806 new_crtc_state, i) { 7807 if (intel_crtc_needs_modeset(new_crtc_state)) { 7808 any_ms = true; 7809 continue; 7810 } 7811 7812 if (!new_crtc_state->update_pipe) 7813 continue; 7814 7815 intel_crtc_copy_fastset(old_crtc_state, new_crtc_state); 7816 } 7817 7818 if (any_ms && !check_digital_port_conflicts(state)) { 7819 drm_dbg_kms(&dev_priv->drm, 7820 "rejecting conflicting digital port configuration\n"); 7821 ret = -EINVAL; 7822 goto fail; 7823 } 7824 7825 ret = drm_dp_mst_atomic_check(&state->base); 7826 if (ret) 7827 goto fail; 7828 7829 ret = intel_atomic_check_planes(state); 7830 if (ret) 7831 goto fail; 7832 7833 ret = intel_compute_global_watermarks(state); 7834 if (ret) 7835 goto fail; 7836 7837 ret = intel_bw_atomic_check(state); 7838 if (ret) 7839 goto fail; 7840 7841 ret = intel_cdclk_atomic_check(state, &any_ms); 7842 if (ret) 7843 goto fail; 7844 7845 if (intel_any_crtc_needs_modeset(state)) 7846 any_ms = true; 7847 7848 if (any_ms) { 7849 ret = intel_modeset_checks(state); 7850 if (ret) 7851 goto fail; 7852 7853 ret = intel_modeset_calc_cdclk(state); 7854 if (ret) 7855 return ret; 7856 7857 intel_modeset_clear_plls(state); 7858 } 7859 7860 ret = intel_atomic_check_crtcs(state); 7861 if (ret) 7862 goto fail; 7863 7864 ret = intel_fbc_atomic_check(state); 7865 if (ret) 7866 goto fail; 7867 7868 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7869 new_crtc_state, i) { 7870 ret = intel_async_flip_check_hw(state, crtc); 7871 if (ret) 7872 goto fail; 7873 7874 if (!intel_crtc_needs_modeset(new_crtc_state) && 7875 !new_crtc_state->update_pipe) 7876 continue; 7877 7878 intel_dump_pipe_config(new_crtc_state, state, 7879 intel_crtc_needs_modeset(new_crtc_state) ? 7880 "[modeset]" : "[fastset]"); 7881 } 7882 7883 return 0; 7884 7885 fail: 7886 if (ret == -EDEADLK) 7887 return ret; 7888 7889 /* 7890 * FIXME would probably be nice to know which crtc specifically 7891 * caused the failure, in cases where we can pinpoint it. 7892 */ 7893 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7894 new_crtc_state, i) 7895 intel_dump_pipe_config(new_crtc_state, state, "[failed]"); 7896 7897 return ret; 7898 } 7899 7900 static int intel_atomic_prepare_commit(struct intel_atomic_state *state) 7901 { 7902 struct intel_crtc_state *crtc_state; 7903 struct intel_crtc *crtc; 7904 int i, ret; 7905 7906 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base); 7907 if (ret < 0) 7908 return ret; 7909 7910 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7911 bool mode_changed = intel_crtc_needs_modeset(crtc_state); 7912 7913 if (mode_changed || crtc_state->update_pipe || 7914 crtc_state->uapi.color_mgmt_changed) { 7915 intel_dsb_prepare(crtc_state); 7916 } 7917 } 7918 7919 return 0; 7920 } 7921 7922 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 7923 struct intel_crtc_state *crtc_state) 7924 { 7925 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 7926 7927 if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes) 7928 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 7929 7930 if (crtc_state->has_pch_encoder) { 7931 enum pipe pch_transcoder = 7932 intel_crtc_pch_transcoder(crtc); 7933 7934 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true); 7935 } 7936 } 7937 7938 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, 7939 const struct intel_crtc_state *new_crtc_state) 7940 { 7941 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 7942 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 7943 7944 /* 7945 * Update pipe size and adjust fitter if needed: the reason for this is 7946 * that in compute_mode_changes we check the native mode (not the pfit 7947 * mode) to see if we can flip rather than do a full mode set. In the 7948 * fastboot case, we'll flip, but if we don't update the pipesrc and 7949 * pfit state, we'll end up with a big fb scanned out into the wrong 7950 * sized surface. 7951 */ 7952 intel_set_pipe_src_size(new_crtc_state); 7953 7954 /* on skylake this is done by detaching scalers */ 7955 if (DISPLAY_VER(dev_priv) >= 9) { 7956 if (new_crtc_state->pch_pfit.enabled) 7957 skl_pfit_enable(new_crtc_state); 7958 } else if (HAS_PCH_SPLIT(dev_priv)) { 7959 if (new_crtc_state->pch_pfit.enabled) 7960 ilk_pfit_enable(new_crtc_state); 7961 else if (old_crtc_state->pch_pfit.enabled) 7962 ilk_pfit_disable(old_crtc_state); 7963 } 7964 7965 /* 7966 * The register is supposedly single buffered so perhaps 7967 * not 100% correct to do this here. But SKL+ calculate 7968 * this based on the adjust pixel rate so pfit changes do 7969 * affect it and so it must be updated for fastsets. 7970 * HSW/BDW only really need this here for fastboot, after 7971 * that the value should not change without a full modeset. 7972 */ 7973 if (DISPLAY_VER(dev_priv) >= 9 || 7974 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 7975 hsw_set_linetime_wm(new_crtc_state); 7976 } 7977 7978 static void commit_pipe_pre_planes(struct intel_atomic_state *state, 7979 struct intel_crtc *crtc) 7980 { 7981 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7982 const struct intel_crtc_state *old_crtc_state = 7983 intel_atomic_get_old_crtc_state(state, crtc); 7984 const struct intel_crtc_state *new_crtc_state = 7985 intel_atomic_get_new_crtc_state(state, crtc); 7986 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 7987 7988 /* 7989 * During modesets pipe configuration was programmed as the 7990 * CRTC was enabled. 7991 */ 7992 if (!modeset) { 7993 if (new_crtc_state->uapi.color_mgmt_changed || 7994 new_crtc_state->update_pipe) 7995 intel_color_commit_arm(new_crtc_state); 7996 7997 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 7998 bdw_set_pipemisc(new_crtc_state); 7999 8000 if (new_crtc_state->update_pipe) 8001 intel_pipe_fastset(old_crtc_state, new_crtc_state); 8002 } 8003 8004 intel_psr2_program_trans_man_trk_ctl(new_crtc_state); 8005 8006 intel_atomic_update_watermarks(state, crtc); 8007 } 8008 8009 static void commit_pipe_post_planes(struct intel_atomic_state *state, 8010 struct intel_crtc *crtc) 8011 { 8012 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8013 const struct intel_crtc_state *new_crtc_state = 8014 intel_atomic_get_new_crtc_state(state, crtc); 8015 8016 /* 8017 * Disable the scaler(s) after the plane(s) so that we don't 8018 * get a catastrophic underrun even if the two operations 8019 * end up happening in two different frames. 8020 */ 8021 if (DISPLAY_VER(dev_priv) >= 9 && 8022 !intel_crtc_needs_modeset(new_crtc_state)) 8023 skl_detach_scalers(new_crtc_state); 8024 } 8025 8026 static void intel_enable_crtc(struct intel_atomic_state *state, 8027 struct intel_crtc *crtc) 8028 { 8029 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8030 const struct intel_crtc_state *new_crtc_state = 8031 intel_atomic_get_new_crtc_state(state, crtc); 8032 8033 if (!intel_crtc_needs_modeset(new_crtc_state)) 8034 return; 8035 8036 intel_crtc_update_active_timings(new_crtc_state); 8037 8038 dev_priv->display->crtc_enable(state, crtc); 8039 8040 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 8041 return; 8042 8043 /* vblanks work again, re-enable pipe CRC. */ 8044 intel_crtc_enable_pipe_crc(crtc); 8045 } 8046 8047 static void intel_update_crtc(struct intel_atomic_state *state, 8048 struct intel_crtc *crtc) 8049 { 8050 struct drm_i915_private *i915 = to_i915(state->base.dev); 8051 const struct intel_crtc_state *old_crtc_state = 8052 intel_atomic_get_old_crtc_state(state, crtc); 8053 struct intel_crtc_state *new_crtc_state = 8054 intel_atomic_get_new_crtc_state(state, crtc); 8055 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 8056 8057 if (!modeset) { 8058 if (new_crtc_state->preload_luts && 8059 (new_crtc_state->uapi.color_mgmt_changed || 8060 new_crtc_state->update_pipe)) 8061 intel_color_load_luts(new_crtc_state); 8062 8063 intel_pre_plane_update(state, crtc); 8064 8065 if (new_crtc_state->update_pipe) 8066 intel_encoders_update_pipe(state, crtc); 8067 8068 if (DISPLAY_VER(i915) >= 11 && 8069 new_crtc_state->update_pipe) 8070 icl_set_pipe_chicken(new_crtc_state); 8071 } 8072 8073 intel_fbc_update(state, crtc); 8074 8075 if (!modeset && 8076 (new_crtc_state->uapi.color_mgmt_changed || 8077 new_crtc_state->update_pipe)) 8078 intel_color_commit_noarm(new_crtc_state); 8079 8080 intel_crtc_planes_update_noarm(state, crtc); 8081 8082 /* Perform vblank evasion around commit operation */ 8083 intel_pipe_update_start(new_crtc_state); 8084 8085 commit_pipe_pre_planes(state, crtc); 8086 8087 intel_crtc_planes_update_arm(state, crtc); 8088 8089 commit_pipe_post_planes(state, crtc); 8090 8091 intel_pipe_update_end(new_crtc_state); 8092 8093 /* 8094 * We usually enable FIFO underrun interrupts as part of the 8095 * CRTC enable sequence during modesets. But when we inherit a 8096 * valid pipe configuration from the BIOS we need to take care 8097 * of enabling them on the CRTC's first fastset. 8098 */ 8099 if (new_crtc_state->update_pipe && !modeset && 8100 old_crtc_state->inherited) 8101 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state); 8102 } 8103 8104 static void intel_old_crtc_state_disables(struct intel_atomic_state *state, 8105 struct intel_crtc_state *old_crtc_state, 8106 struct intel_crtc_state *new_crtc_state, 8107 struct intel_crtc *crtc) 8108 { 8109 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8110 8111 /* 8112 * We need to disable pipe CRC before disabling the pipe, 8113 * or we race against vblank off. 8114 */ 8115 intel_crtc_disable_pipe_crc(crtc); 8116 8117 dev_priv->display->crtc_disable(state, crtc); 8118 crtc->active = false; 8119 intel_fbc_disable(crtc); 8120 intel_disable_shared_dpll(old_crtc_state); 8121 8122 /* FIXME unify this for all platforms */ 8123 if (!new_crtc_state->hw.active && 8124 !HAS_GMCH(dev_priv)) 8125 intel_initial_watermarks(state, crtc); 8126 } 8127 8128 static void intel_commit_modeset_disables(struct intel_atomic_state *state) 8129 { 8130 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 8131 struct intel_crtc *crtc; 8132 u32 handled = 0; 8133 int i; 8134 8135 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8136 new_crtc_state, i) { 8137 if (!intel_crtc_needs_modeset(new_crtc_state)) 8138 continue; 8139 8140 if (!old_crtc_state->hw.active) 8141 continue; 8142 8143 intel_pre_plane_update(state, crtc); 8144 intel_crtc_disable_planes(state, crtc); 8145 } 8146 8147 /* Only disable port sync and MST slaves */ 8148 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8149 new_crtc_state, i) { 8150 if (!intel_crtc_needs_modeset(new_crtc_state)) 8151 continue; 8152 8153 if (!old_crtc_state->hw.active) 8154 continue; 8155 8156 /* In case of Transcoder port Sync master slave CRTCs can be 8157 * assigned in any order and we need to make sure that 8158 * slave CRTCs are disabled first and then master CRTC since 8159 * Slave vblanks are masked till Master Vblanks. 8160 */ 8161 if (!is_trans_port_sync_slave(old_crtc_state) && 8162 !intel_dp_mst_is_slave_trans(old_crtc_state) && 8163 !intel_crtc_is_bigjoiner_slave(old_crtc_state)) 8164 continue; 8165 8166 intel_old_crtc_state_disables(state, old_crtc_state, 8167 new_crtc_state, crtc); 8168 handled |= BIT(crtc->pipe); 8169 } 8170 8171 /* Disable everything else left on */ 8172 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8173 new_crtc_state, i) { 8174 if (!intel_crtc_needs_modeset(new_crtc_state) || 8175 (handled & BIT(crtc->pipe))) 8176 continue; 8177 8178 if (!old_crtc_state->hw.active) 8179 continue; 8180 8181 intel_old_crtc_state_disables(state, old_crtc_state, 8182 new_crtc_state, crtc); 8183 } 8184 } 8185 8186 static void intel_commit_modeset_enables(struct intel_atomic_state *state) 8187 { 8188 struct intel_crtc_state *new_crtc_state; 8189 struct intel_crtc *crtc; 8190 int i; 8191 8192 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8193 if (!new_crtc_state->hw.active) 8194 continue; 8195 8196 intel_enable_crtc(state, crtc); 8197 intel_update_crtc(state, crtc); 8198 } 8199 } 8200 8201 static void skl_commit_modeset_enables(struct intel_atomic_state *state) 8202 { 8203 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8204 struct intel_crtc *crtc; 8205 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 8206 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; 8207 u8 update_pipes = 0, modeset_pipes = 0; 8208 int i; 8209 8210 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 8211 enum pipe pipe = crtc->pipe; 8212 8213 if (!new_crtc_state->hw.active) 8214 continue; 8215 8216 /* ignore allocations for crtc's that have been turned off. */ 8217 if (!intel_crtc_needs_modeset(new_crtc_state)) { 8218 entries[pipe] = old_crtc_state->wm.skl.ddb; 8219 update_pipes |= BIT(pipe); 8220 } else { 8221 modeset_pipes |= BIT(pipe); 8222 } 8223 } 8224 8225 /* 8226 * Whenever the number of active pipes changes, we need to make sure we 8227 * update the pipes in the right order so that their ddb allocations 8228 * never overlap with each other between CRTC updates. Otherwise we'll 8229 * cause pipe underruns and other bad stuff. 8230 * 8231 * So first lets enable all pipes that do not need a fullmodeset as 8232 * those don't have any external dependency. 8233 */ 8234 while (update_pipes) { 8235 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8236 new_crtc_state, i) { 8237 enum pipe pipe = crtc->pipe; 8238 8239 if ((update_pipes & BIT(pipe)) == 0) 8240 continue; 8241 8242 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 8243 entries, I915_MAX_PIPES, pipe)) 8244 continue; 8245 8246 entries[pipe] = new_crtc_state->wm.skl.ddb; 8247 update_pipes &= ~BIT(pipe); 8248 8249 intel_update_crtc(state, crtc); 8250 8251 /* 8252 * If this is an already active pipe, it's DDB changed, 8253 * and this isn't the last pipe that needs updating 8254 * then we need to wait for a vblank to pass for the 8255 * new ddb allocation to take effect. 8256 */ 8257 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, 8258 &old_crtc_state->wm.skl.ddb) && 8259 (update_pipes | modeset_pipes)) 8260 intel_crtc_wait_for_next_vblank(crtc); 8261 } 8262 } 8263 8264 update_pipes = modeset_pipes; 8265 8266 /* 8267 * Enable all pipes that needs a modeset and do not depends on other 8268 * pipes 8269 */ 8270 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8271 enum pipe pipe = crtc->pipe; 8272 8273 if ((modeset_pipes & BIT(pipe)) == 0) 8274 continue; 8275 8276 if (intel_dp_mst_is_slave_trans(new_crtc_state) || 8277 is_trans_port_sync_master(new_crtc_state) || 8278 intel_crtc_is_bigjoiner_master(new_crtc_state)) 8279 continue; 8280 8281 modeset_pipes &= ~BIT(pipe); 8282 8283 intel_enable_crtc(state, crtc); 8284 } 8285 8286 /* 8287 * Then we enable all remaining pipes that depend on other 8288 * pipes: MST slaves and port sync masters, big joiner master 8289 */ 8290 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8291 enum pipe pipe = crtc->pipe; 8292 8293 if ((modeset_pipes & BIT(pipe)) == 0) 8294 continue; 8295 8296 modeset_pipes &= ~BIT(pipe); 8297 8298 intel_enable_crtc(state, crtc); 8299 } 8300 8301 /* 8302 * Finally we do the plane updates/etc. for all pipes that got enabled. 8303 */ 8304 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8305 enum pipe pipe = crtc->pipe; 8306 8307 if ((update_pipes & BIT(pipe)) == 0) 8308 continue; 8309 8310 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 8311 entries, I915_MAX_PIPES, pipe)); 8312 8313 entries[pipe] = new_crtc_state->wm.skl.ddb; 8314 update_pipes &= ~BIT(pipe); 8315 8316 intel_update_crtc(state, crtc); 8317 } 8318 8319 drm_WARN_ON(&dev_priv->drm, modeset_pipes); 8320 drm_WARN_ON(&dev_priv->drm, update_pipes); 8321 } 8322 8323 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) 8324 { 8325 struct intel_atomic_state *state, *next; 8326 struct llist_node *freed; 8327 8328 freed = llist_del_all(&dev_priv->atomic_helper.free_list); 8329 llist_for_each_entry_safe(state, next, freed, freed) 8330 drm_atomic_state_put(&state->base); 8331 } 8332 8333 static void intel_atomic_helper_free_state_worker(struct work_struct *work) 8334 { 8335 struct drm_i915_private *dev_priv = 8336 container_of(work, typeof(*dev_priv), atomic_helper.free_work); 8337 8338 intel_atomic_helper_free_state(dev_priv); 8339 } 8340 8341 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) 8342 { 8343 struct wait_queue_entry wait_fence, wait_reset; 8344 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); 8345 8346 init_wait_entry(&wait_fence, 0); 8347 init_wait_entry(&wait_reset, 0); 8348 for (;;) { 8349 prepare_to_wait(&intel_state->commit_ready.wait, 8350 &wait_fence, TASK_UNINTERRUPTIBLE); 8351 prepare_to_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 8352 I915_RESET_MODESET), 8353 &wait_reset, TASK_UNINTERRUPTIBLE); 8354 8355 8356 if (i915_sw_fence_done(&intel_state->commit_ready) || 8357 test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags)) 8358 break; 8359 8360 schedule(); 8361 } 8362 finish_wait(&intel_state->commit_ready.wait, &wait_fence); 8363 finish_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 8364 I915_RESET_MODESET), 8365 &wait_reset); 8366 } 8367 8368 static void intel_cleanup_dsbs(struct intel_atomic_state *state) 8369 { 8370 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 8371 struct intel_crtc *crtc; 8372 int i; 8373 8374 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8375 new_crtc_state, i) 8376 intel_dsb_cleanup(old_crtc_state); 8377 } 8378 8379 static void intel_atomic_cleanup_work(struct work_struct *work) 8380 { 8381 struct intel_atomic_state *state = 8382 container_of(work, struct intel_atomic_state, base.commit_work); 8383 struct drm_i915_private *i915 = to_i915(state->base.dev); 8384 8385 intel_cleanup_dsbs(state); 8386 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base); 8387 drm_atomic_helper_commit_cleanup_done(&state->base); 8388 drm_atomic_state_put(&state->base); 8389 8390 intel_atomic_helper_free_state(i915); 8391 } 8392 8393 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state) 8394 { 8395 struct drm_i915_private *i915 = to_i915(state->base.dev); 8396 struct intel_plane *plane; 8397 struct intel_plane_state *plane_state; 8398 int i; 8399 8400 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 8401 struct drm_framebuffer *fb = plane_state->hw.fb; 8402 int cc_plane; 8403 int ret; 8404 8405 if (!fb) 8406 continue; 8407 8408 cc_plane = intel_fb_rc_ccs_cc_plane(fb); 8409 if (cc_plane < 0) 8410 continue; 8411 8412 /* 8413 * The layout of the fast clear color value expected by HW 8414 * (the DRM ABI requiring this value to be located in fb at 8415 * offset 0 of cc plane, plane #2 previous generations or 8416 * plane #1 for flat ccs): 8417 * - 4 x 4 bytes per-channel value 8418 * (in surface type specific float/int format provided by the fb user) 8419 * - 8 bytes native color value used by the display 8420 * (converted/written by GPU during a fast clear operation using the 8421 * above per-channel values) 8422 * 8423 * The commit's FB prepare hook already ensured that FB obj is pinned and the 8424 * caller made sure that the object is synced wrt. the related color clear value 8425 * GPU write on it. 8426 */ 8427 ret = i915_gem_object_read_from_page(intel_fb_obj(fb), 8428 fb->offsets[cc_plane] + 16, 8429 &plane_state->ccval, 8430 sizeof(plane_state->ccval)); 8431 /* The above could only fail if the FB obj has an unexpected backing store type. */ 8432 drm_WARN_ON(&i915->drm, ret); 8433 } 8434 } 8435 8436 static void intel_atomic_commit_tail(struct intel_atomic_state *state) 8437 { 8438 struct drm_device *dev = state->base.dev; 8439 struct drm_i915_private *dev_priv = to_i915(dev); 8440 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 8441 struct intel_crtc *crtc; 8442 struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {}; 8443 intel_wakeref_t wakeref = 0; 8444 int i; 8445 8446 intel_atomic_commit_fence_wait(state); 8447 8448 drm_atomic_helper_wait_for_dependencies(&state->base); 8449 8450 if (state->modeset) 8451 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); 8452 8453 intel_atomic_prepare_plane_clear_colors(state); 8454 8455 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8456 new_crtc_state, i) { 8457 if (intel_crtc_needs_modeset(new_crtc_state) || 8458 new_crtc_state->update_pipe) { 8459 modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]); 8460 } 8461 } 8462 8463 intel_commit_modeset_disables(state); 8464 8465 /* FIXME: Eventually get rid of our crtc->config pointer */ 8466 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 8467 crtc->config = new_crtc_state; 8468 8469 if (state->modeset) { 8470 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base); 8471 8472 intel_set_cdclk_pre_plane_update(state); 8473 8474 intel_modeset_verify_disabled(dev_priv, state); 8475 } 8476 8477 intel_sagv_pre_plane_update(state); 8478 8479 /* Complete the events for pipes that have now been disabled */ 8480 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8481 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 8482 8483 /* Complete events for now disable pipes here. */ 8484 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) { 8485 spin_lock_irq(&dev->event_lock); 8486 drm_crtc_send_vblank_event(&crtc->base, 8487 new_crtc_state->uapi.event); 8488 spin_unlock_irq(&dev->event_lock); 8489 8490 new_crtc_state->uapi.event = NULL; 8491 } 8492 } 8493 8494 intel_encoders_update_prepare(state); 8495 8496 intel_dbuf_pre_plane_update(state); 8497 intel_mbus_dbox_update(state); 8498 8499 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8500 if (new_crtc_state->do_async_flip) 8501 intel_crtc_enable_flip_done(state, crtc); 8502 } 8503 8504 /* Now enable the clocks, plane, pipe, and connectors that we set up. */ 8505 dev_priv->display->commit_modeset_enables(state); 8506 8507 intel_encoders_update_complete(state); 8508 8509 if (state->modeset) 8510 intel_set_cdclk_post_plane_update(state); 8511 8512 intel_wait_for_vblank_workers(state); 8513 8514 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here 8515 * already, but still need the state for the delayed optimization. To 8516 * fix this: 8517 * - wrap the optimization/post_plane_update stuff into a per-crtc work. 8518 * - schedule that vblank worker _before_ calling hw_done 8519 * - at the start of commit_tail, cancel it _synchrously 8520 * - switch over to the vblank wait helper in the core after that since 8521 * we don't need out special handling any more. 8522 */ 8523 drm_atomic_helper_wait_for_flip_done(dev, &state->base); 8524 8525 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8526 if (new_crtc_state->do_async_flip) 8527 intel_crtc_disable_flip_done(state, crtc); 8528 } 8529 8530 /* 8531 * Now that the vblank has passed, we can go ahead and program the 8532 * optimal watermarks on platforms that need two-step watermark 8533 * programming. 8534 * 8535 * TODO: Move this (and other cleanup) to an async worker eventually. 8536 */ 8537 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8538 new_crtc_state, i) { 8539 /* 8540 * Gen2 reports pipe underruns whenever all planes are disabled. 8541 * So re-enable underrun reporting after some planes get enabled. 8542 * 8543 * We do this before .optimize_watermarks() so that we have a 8544 * chance of catching underruns with the intermediate watermarks 8545 * vs. the new plane configuration. 8546 */ 8547 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state)) 8548 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 8549 8550 intel_optimize_watermarks(state, crtc); 8551 } 8552 8553 intel_dbuf_post_plane_update(state); 8554 intel_psr_post_plane_update(state); 8555 8556 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 8557 intel_post_plane_update(state, crtc); 8558 8559 modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]); 8560 8561 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state); 8562 8563 /* 8564 * DSB cleanup is done in cleanup_work aligning with framebuffer 8565 * cleanup. So copy and reset the dsb structure to sync with 8566 * commit_done and later do dsb cleanup in cleanup_work. 8567 */ 8568 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb); 8569 } 8570 8571 /* Underruns don't always raise interrupts, so check manually */ 8572 intel_check_cpu_fifo_underruns(dev_priv); 8573 intel_check_pch_fifo_underruns(dev_priv); 8574 8575 if (state->modeset) 8576 intel_verify_planes(state); 8577 8578 intel_sagv_post_plane_update(state); 8579 8580 drm_atomic_helper_commit_hw_done(&state->base); 8581 8582 if (state->modeset) { 8583 /* As one of the primary mmio accessors, KMS has a high 8584 * likelihood of triggering bugs in unclaimed access. After we 8585 * finish modesetting, see if an error has been flagged, and if 8586 * so enable debugging for the next modeset - and hope we catch 8587 * the culprit. 8588 */ 8589 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); 8590 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref); 8591 } 8592 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 8593 8594 /* 8595 * Defer the cleanup of the old state to a separate worker to not 8596 * impede the current task (userspace for blocking modesets) that 8597 * are executed inline. For out-of-line asynchronous modesets/flips, 8598 * deferring to a new worker seems overkill, but we would place a 8599 * schedule point (cond_resched()) here anyway to keep latencies 8600 * down. 8601 */ 8602 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work); 8603 queue_work(system_highpri_wq, &state->base.commit_work); 8604 } 8605 8606 static void intel_atomic_commit_work(struct work_struct *work) 8607 { 8608 struct intel_atomic_state *state = 8609 container_of(work, struct intel_atomic_state, base.commit_work); 8610 8611 intel_atomic_commit_tail(state); 8612 } 8613 8614 static int 8615 intel_atomic_commit_ready(struct i915_sw_fence *fence, 8616 enum i915_sw_fence_notify notify) 8617 { 8618 struct intel_atomic_state *state = 8619 container_of(fence, struct intel_atomic_state, commit_ready); 8620 8621 switch (notify) { 8622 case FENCE_COMPLETE: 8623 /* we do blocking waits in the worker, nothing to do here */ 8624 break; 8625 case FENCE_FREE: 8626 { 8627 struct intel_atomic_helper *helper = 8628 &to_i915(state->base.dev)->atomic_helper; 8629 8630 if (llist_add(&state->freed, &helper->free_list)) 8631 schedule_work(&helper->free_work); 8632 break; 8633 } 8634 } 8635 8636 return NOTIFY_DONE; 8637 } 8638 8639 static void intel_atomic_track_fbs(struct intel_atomic_state *state) 8640 { 8641 struct intel_plane_state *old_plane_state, *new_plane_state; 8642 struct intel_plane *plane; 8643 int i; 8644 8645 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 8646 new_plane_state, i) 8647 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), 8648 to_intel_frontbuffer(new_plane_state->hw.fb), 8649 plane->frontbuffer_bit); 8650 } 8651 8652 static int intel_atomic_commit(struct drm_device *dev, 8653 struct drm_atomic_state *_state, 8654 bool nonblock) 8655 { 8656 struct intel_atomic_state *state = to_intel_atomic_state(_state); 8657 struct drm_i915_private *dev_priv = to_i915(dev); 8658 int ret = 0; 8659 8660 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 8661 8662 drm_atomic_state_get(&state->base); 8663 i915_sw_fence_init(&state->commit_ready, 8664 intel_atomic_commit_ready); 8665 8666 /* 8667 * The intel_legacy_cursor_update() fast path takes care 8668 * of avoiding the vblank waits for simple cursor 8669 * movement and flips. For cursor on/off and size changes, 8670 * we want to perform the vblank waits so that watermark 8671 * updates happen during the correct frames. Gen9+ have 8672 * double buffered watermarks and so shouldn't need this. 8673 * 8674 * Unset state->legacy_cursor_update before the call to 8675 * drm_atomic_helper_setup_commit() because otherwise 8676 * drm_atomic_helper_wait_for_flip_done() is a noop and 8677 * we get FIFO underruns because we didn't wait 8678 * for vblank. 8679 * 8680 * FIXME doing watermarks and fb cleanup from a vblank worker 8681 * (assuming we had any) would solve these problems. 8682 */ 8683 if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) { 8684 struct intel_crtc_state *new_crtc_state; 8685 struct intel_crtc *crtc; 8686 int i; 8687 8688 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 8689 if (new_crtc_state->wm.need_postvbl_update || 8690 new_crtc_state->update_wm_post) 8691 state->base.legacy_cursor_update = false; 8692 } 8693 8694 ret = intel_atomic_prepare_commit(state); 8695 if (ret) { 8696 drm_dbg_atomic(&dev_priv->drm, 8697 "Preparing state failed with %i\n", ret); 8698 i915_sw_fence_commit(&state->commit_ready); 8699 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 8700 return ret; 8701 } 8702 8703 ret = drm_atomic_helper_setup_commit(&state->base, nonblock); 8704 if (!ret) 8705 ret = drm_atomic_helper_swap_state(&state->base, true); 8706 if (!ret) 8707 intel_atomic_swap_global_state(state); 8708 8709 if (ret) { 8710 struct intel_crtc_state *new_crtc_state; 8711 struct intel_crtc *crtc; 8712 int i; 8713 8714 i915_sw_fence_commit(&state->commit_ready); 8715 8716 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 8717 intel_dsb_cleanup(new_crtc_state); 8718 8719 drm_atomic_helper_cleanup_planes(dev, &state->base); 8720 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 8721 return ret; 8722 } 8723 intel_shared_dpll_swap_state(state); 8724 intel_atomic_track_fbs(state); 8725 8726 drm_atomic_state_get(&state->base); 8727 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work); 8728 8729 i915_sw_fence_commit(&state->commit_ready); 8730 if (nonblock && state->modeset) { 8731 queue_work(dev_priv->modeset_wq, &state->base.commit_work); 8732 } else if (nonblock) { 8733 queue_work(dev_priv->flip_wq, &state->base.commit_work); 8734 } else { 8735 if (state->modeset) 8736 flush_workqueue(dev_priv->modeset_wq); 8737 intel_atomic_commit_tail(state); 8738 } 8739 8740 return 0; 8741 } 8742 8743 /** 8744 * intel_plane_destroy - destroy a plane 8745 * @plane: plane to destroy 8746 * 8747 * Common destruction function for all types of planes (primary, cursor, 8748 * sprite). 8749 */ 8750 void intel_plane_destroy(struct drm_plane *plane) 8751 { 8752 drm_plane_cleanup(plane); 8753 kfree(to_intel_plane(plane)); 8754 } 8755 8756 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv) 8757 { 8758 struct intel_plane *plane; 8759 8760 for_each_intel_plane(&dev_priv->drm, plane) { 8761 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, 8762 plane->pipe); 8763 8764 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base); 8765 } 8766 } 8767 8768 8769 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 8770 struct drm_file *file) 8771 { 8772 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; 8773 struct drm_crtc *drmmode_crtc; 8774 struct intel_crtc *crtc; 8775 8776 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id); 8777 if (!drmmode_crtc) 8778 return -ENOENT; 8779 8780 crtc = to_intel_crtc(drmmode_crtc); 8781 pipe_from_crtc_id->pipe = crtc->pipe; 8782 8783 return 0; 8784 } 8785 8786 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder) 8787 { 8788 struct drm_device *dev = encoder->base.dev; 8789 struct intel_encoder *source_encoder; 8790 u32 possible_clones = 0; 8791 8792 for_each_intel_encoder(dev, source_encoder) { 8793 if (encoders_cloneable(encoder, source_encoder)) 8794 possible_clones |= drm_encoder_mask(&source_encoder->base); 8795 } 8796 8797 return possible_clones; 8798 } 8799 8800 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder) 8801 { 8802 struct drm_device *dev = encoder->base.dev; 8803 struct intel_crtc *crtc; 8804 u32 possible_crtcs = 0; 8805 8806 for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask) 8807 possible_crtcs |= drm_crtc_mask(&crtc->base); 8808 8809 return possible_crtcs; 8810 } 8811 8812 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv) 8813 { 8814 if (!IS_MOBILE(dev_priv)) 8815 return false; 8816 8817 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0) 8818 return false; 8819 8820 if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE)) 8821 return false; 8822 8823 return true; 8824 } 8825 8826 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv) 8827 { 8828 if (DISPLAY_VER(dev_priv) >= 9) 8829 return false; 8830 8831 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) 8832 return false; 8833 8834 if (HAS_PCH_LPT_H(dev_priv) && 8835 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) 8836 return false; 8837 8838 /* DDI E can't be used if DDI A requires 4 lanes */ 8839 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 8840 return false; 8841 8842 if (!dev_priv->vbt.int_crt_support) 8843 return false; 8844 8845 return true; 8846 } 8847 8848 static void intel_setup_outputs(struct drm_i915_private *dev_priv) 8849 { 8850 struct intel_encoder *encoder; 8851 bool dpd_is_edp = false; 8852 8853 intel_pps_unlock_regs_wa(dev_priv); 8854 8855 if (!HAS_DISPLAY(dev_priv)) 8856 return; 8857 8858 if (IS_DG2(dev_priv)) { 8859 intel_ddi_init(dev_priv, PORT_A); 8860 intel_ddi_init(dev_priv, PORT_B); 8861 intel_ddi_init(dev_priv, PORT_C); 8862 intel_ddi_init(dev_priv, PORT_D_XELPD); 8863 intel_ddi_init(dev_priv, PORT_TC1); 8864 } else if (IS_ALDERLAKE_P(dev_priv)) { 8865 intel_ddi_init(dev_priv, PORT_A); 8866 intel_ddi_init(dev_priv, PORT_B); 8867 intel_ddi_init(dev_priv, PORT_TC1); 8868 intel_ddi_init(dev_priv, PORT_TC2); 8869 intel_ddi_init(dev_priv, PORT_TC3); 8870 intel_ddi_init(dev_priv, PORT_TC4); 8871 icl_dsi_init(dev_priv); 8872 } else if (IS_ALDERLAKE_S(dev_priv)) { 8873 intel_ddi_init(dev_priv, PORT_A); 8874 intel_ddi_init(dev_priv, PORT_TC1); 8875 intel_ddi_init(dev_priv, PORT_TC2); 8876 intel_ddi_init(dev_priv, PORT_TC3); 8877 intel_ddi_init(dev_priv, PORT_TC4); 8878 } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) { 8879 intel_ddi_init(dev_priv, PORT_A); 8880 intel_ddi_init(dev_priv, PORT_B); 8881 intel_ddi_init(dev_priv, PORT_TC1); 8882 intel_ddi_init(dev_priv, PORT_TC2); 8883 } else if (DISPLAY_VER(dev_priv) >= 12) { 8884 intel_ddi_init(dev_priv, PORT_A); 8885 intel_ddi_init(dev_priv, PORT_B); 8886 intel_ddi_init(dev_priv, PORT_TC1); 8887 intel_ddi_init(dev_priv, PORT_TC2); 8888 intel_ddi_init(dev_priv, PORT_TC3); 8889 intel_ddi_init(dev_priv, PORT_TC4); 8890 intel_ddi_init(dev_priv, PORT_TC5); 8891 intel_ddi_init(dev_priv, PORT_TC6); 8892 icl_dsi_init(dev_priv); 8893 } else if (IS_JSL_EHL(dev_priv)) { 8894 intel_ddi_init(dev_priv, PORT_A); 8895 intel_ddi_init(dev_priv, PORT_B); 8896 intel_ddi_init(dev_priv, PORT_C); 8897 intel_ddi_init(dev_priv, PORT_D); 8898 icl_dsi_init(dev_priv); 8899 } else if (DISPLAY_VER(dev_priv) == 11) { 8900 intel_ddi_init(dev_priv, PORT_A); 8901 intel_ddi_init(dev_priv, PORT_B); 8902 intel_ddi_init(dev_priv, PORT_C); 8903 intel_ddi_init(dev_priv, PORT_D); 8904 intel_ddi_init(dev_priv, PORT_E); 8905 intel_ddi_init(dev_priv, PORT_F); 8906 icl_dsi_init(dev_priv); 8907 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 8908 intel_ddi_init(dev_priv, PORT_A); 8909 intel_ddi_init(dev_priv, PORT_B); 8910 intel_ddi_init(dev_priv, PORT_C); 8911 vlv_dsi_init(dev_priv); 8912 } else if (DISPLAY_VER(dev_priv) >= 9) { 8913 intel_ddi_init(dev_priv, PORT_A); 8914 intel_ddi_init(dev_priv, PORT_B); 8915 intel_ddi_init(dev_priv, PORT_C); 8916 intel_ddi_init(dev_priv, PORT_D); 8917 intel_ddi_init(dev_priv, PORT_E); 8918 } else if (HAS_DDI(dev_priv)) { 8919 u32 found; 8920 8921 if (intel_ddi_crt_present(dev_priv)) 8922 intel_crt_init(dev_priv); 8923 8924 /* Haswell uses DDI functions to detect digital outputs. */ 8925 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 8926 if (found) 8927 intel_ddi_init(dev_priv, PORT_A); 8928 8929 found = intel_de_read(dev_priv, SFUSE_STRAP); 8930 if (found & SFUSE_STRAP_DDIB_DETECTED) 8931 intel_ddi_init(dev_priv, PORT_B); 8932 if (found & SFUSE_STRAP_DDIC_DETECTED) 8933 intel_ddi_init(dev_priv, PORT_C); 8934 if (found & SFUSE_STRAP_DDID_DETECTED) 8935 intel_ddi_init(dev_priv, PORT_D); 8936 if (found & SFUSE_STRAP_DDIF_DETECTED) 8937 intel_ddi_init(dev_priv, PORT_F); 8938 } else if (HAS_PCH_SPLIT(dev_priv)) { 8939 int found; 8940 8941 /* 8942 * intel_edp_init_connector() depends on this completing first, 8943 * to prevent the registration of both eDP and LVDS and the 8944 * incorrect sharing of the PPS. 8945 */ 8946 intel_lvds_init(dev_priv); 8947 intel_crt_init(dev_priv); 8948 8949 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D); 8950 8951 if (ilk_has_edp_a(dev_priv)) 8952 g4x_dp_init(dev_priv, DP_A, PORT_A); 8953 8954 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) { 8955 /* PCH SDVOB multiplex with HDMIB */ 8956 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); 8957 if (!found) 8958 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); 8959 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED)) 8960 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B); 8961 } 8962 8963 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED) 8964 g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); 8965 8966 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED) 8967 g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D); 8968 8969 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED) 8970 g4x_dp_init(dev_priv, PCH_DP_C, PORT_C); 8971 8972 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED) 8973 g4x_dp_init(dev_priv, PCH_DP_D, PORT_D); 8974 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 8975 bool has_edp, has_port; 8976 8977 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support) 8978 intel_crt_init(dev_priv); 8979 8980 /* 8981 * The DP_DETECTED bit is the latched state of the DDC 8982 * SDA pin at boot. However since eDP doesn't require DDC 8983 * (no way to plug in a DP->HDMI dongle) the DDC pins for 8984 * eDP ports may have been muxed to an alternate function. 8985 * Thus we can't rely on the DP_DETECTED bit alone to detect 8986 * eDP ports. Consult the VBT as well as DP_DETECTED to 8987 * detect eDP ports. 8988 * 8989 * Sadly the straps seem to be missing sometimes even for HDMI 8990 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap 8991 * and VBT for the presence of the port. Additionally we can't 8992 * trust the port type the VBT declares as we've seen at least 8993 * HDMI ports that the VBT claim are DP or eDP. 8994 */ 8995 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B); 8996 has_port = intel_bios_is_port_present(dev_priv, PORT_B); 8997 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port) 8998 has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B); 8999 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) 9000 g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); 9001 9002 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C); 9003 has_port = intel_bios_is_port_present(dev_priv, PORT_C); 9004 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port) 9005 has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C); 9006 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) 9007 g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); 9008 9009 if (IS_CHERRYVIEW(dev_priv)) { 9010 /* 9011 * eDP not supported on port D, 9012 * so no need to worry about it 9013 */ 9014 has_port = intel_bios_is_port_present(dev_priv, PORT_D); 9015 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port) 9016 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D); 9017 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port) 9018 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D); 9019 } 9020 9021 vlv_dsi_init(dev_priv); 9022 } else if (IS_PINEVIEW(dev_priv)) { 9023 intel_lvds_init(dev_priv); 9024 intel_crt_init(dev_priv); 9025 } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) { 9026 bool found = false; 9027 9028 if (IS_MOBILE(dev_priv)) 9029 intel_lvds_init(dev_priv); 9030 9031 intel_crt_init(dev_priv); 9032 9033 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 9034 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n"); 9035 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); 9036 if (!found && IS_G4X(dev_priv)) { 9037 drm_dbg_kms(&dev_priv->drm, 9038 "probing HDMI on SDVOB\n"); 9039 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); 9040 } 9041 9042 if (!found && IS_G4X(dev_priv)) 9043 g4x_dp_init(dev_priv, DP_B, PORT_B); 9044 } 9045 9046 /* Before G4X SDVOC doesn't have its own detect register */ 9047 9048 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 9049 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n"); 9050 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); 9051 } 9052 9053 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) { 9054 9055 if (IS_G4X(dev_priv)) { 9056 drm_dbg_kms(&dev_priv->drm, 9057 "probing HDMI on SDVOC\n"); 9058 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); 9059 } 9060 if (IS_G4X(dev_priv)) 9061 g4x_dp_init(dev_priv, DP_C, PORT_C); 9062 } 9063 9064 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED)) 9065 g4x_dp_init(dev_priv, DP_D, PORT_D); 9066 9067 if (SUPPORTS_TV(dev_priv)) 9068 intel_tv_init(dev_priv); 9069 } else if (DISPLAY_VER(dev_priv) == 2) { 9070 if (IS_I85X(dev_priv)) 9071 intel_lvds_init(dev_priv); 9072 9073 intel_crt_init(dev_priv); 9074 intel_dvo_init(dev_priv); 9075 } 9076 9077 for_each_intel_encoder(&dev_priv->drm, encoder) { 9078 encoder->base.possible_crtcs = 9079 intel_encoder_possible_crtcs(encoder); 9080 encoder->base.possible_clones = 9081 intel_encoder_possible_clones(encoder); 9082 } 9083 9084 intel_init_pch_refclk(dev_priv); 9085 9086 drm_helper_move_panel_connectors_to_head(&dev_priv->drm); 9087 } 9088 9089 static enum drm_mode_status 9090 intel_mode_valid(struct drm_device *dev, 9091 const struct drm_display_mode *mode) 9092 { 9093 struct drm_i915_private *dev_priv = to_i915(dev); 9094 int hdisplay_max, htotal_max; 9095 int vdisplay_max, vtotal_max; 9096 9097 /* 9098 * Can't reject DBLSCAN here because Xorg ddxen can add piles 9099 * of DBLSCAN modes to the output's mode list when they detect 9100 * the scaling mode property on the connector. And they don't 9101 * ask the kernel to validate those modes in any way until 9102 * modeset time at which point the client gets a protocol error. 9103 * So in order to not upset those clients we silently ignore the 9104 * DBLSCAN flag on such connectors. For other connectors we will 9105 * reject modes with the DBLSCAN flag in encoder->compute_config(). 9106 * And we always reject DBLSCAN modes in connector->mode_valid() 9107 * as we never want such modes on the connector's mode list. 9108 */ 9109 9110 if (mode->vscan > 1) 9111 return MODE_NO_VSCAN; 9112 9113 if (mode->flags & DRM_MODE_FLAG_HSKEW) 9114 return MODE_H_ILLEGAL; 9115 9116 if (mode->flags & (DRM_MODE_FLAG_CSYNC | 9117 DRM_MODE_FLAG_NCSYNC | 9118 DRM_MODE_FLAG_PCSYNC)) 9119 return MODE_HSYNC; 9120 9121 if (mode->flags & (DRM_MODE_FLAG_BCAST | 9122 DRM_MODE_FLAG_PIXMUX | 9123 DRM_MODE_FLAG_CLKDIV2)) 9124 return MODE_BAD; 9125 9126 /* Transcoder timing limits */ 9127 if (DISPLAY_VER(dev_priv) >= 11) { 9128 hdisplay_max = 16384; 9129 vdisplay_max = 8192; 9130 htotal_max = 16384; 9131 vtotal_max = 8192; 9132 } else if (DISPLAY_VER(dev_priv) >= 9 || 9133 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 9134 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ 9135 vdisplay_max = 4096; 9136 htotal_max = 8192; 9137 vtotal_max = 8192; 9138 } else if (DISPLAY_VER(dev_priv) >= 3) { 9139 hdisplay_max = 4096; 9140 vdisplay_max = 4096; 9141 htotal_max = 8192; 9142 vtotal_max = 8192; 9143 } else { 9144 hdisplay_max = 2048; 9145 vdisplay_max = 2048; 9146 htotal_max = 4096; 9147 vtotal_max = 4096; 9148 } 9149 9150 if (mode->hdisplay > hdisplay_max || 9151 mode->hsync_start > htotal_max || 9152 mode->hsync_end > htotal_max || 9153 mode->htotal > htotal_max) 9154 return MODE_H_ILLEGAL; 9155 9156 if (mode->vdisplay > vdisplay_max || 9157 mode->vsync_start > vtotal_max || 9158 mode->vsync_end > vtotal_max || 9159 mode->vtotal > vtotal_max) 9160 return MODE_V_ILLEGAL; 9161 9162 if (DISPLAY_VER(dev_priv) >= 5) { 9163 if (mode->hdisplay < 64 || 9164 mode->htotal - mode->hdisplay < 32) 9165 return MODE_H_ILLEGAL; 9166 9167 if (mode->vtotal - mode->vdisplay < 5) 9168 return MODE_V_ILLEGAL; 9169 } else { 9170 if (mode->htotal - mode->hdisplay < 32) 9171 return MODE_H_ILLEGAL; 9172 9173 if (mode->vtotal - mode->vdisplay < 3) 9174 return MODE_V_ILLEGAL; 9175 } 9176 9177 /* 9178 * Cantiga+ cannot handle modes with a hsync front porch of 0. 9179 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. 9180 */ 9181 if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) && 9182 mode->hsync_start == mode->hdisplay) 9183 return MODE_H_ILLEGAL; 9184 9185 return MODE_OK; 9186 } 9187 9188 enum drm_mode_status 9189 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 9190 const struct drm_display_mode *mode, 9191 bool bigjoiner) 9192 { 9193 int plane_width_max, plane_height_max; 9194 9195 /* 9196 * intel_mode_valid() should be 9197 * sufficient on older platforms. 9198 */ 9199 if (DISPLAY_VER(dev_priv) < 9) 9200 return MODE_OK; 9201 9202 /* 9203 * Most people will probably want a fullscreen 9204 * plane so let's not advertize modes that are 9205 * too big for that. 9206 */ 9207 if (DISPLAY_VER(dev_priv) >= 11) { 9208 plane_width_max = 5120 << bigjoiner; 9209 plane_height_max = 4320; 9210 } else { 9211 plane_width_max = 5120; 9212 plane_height_max = 4096; 9213 } 9214 9215 if (mode->hdisplay > plane_width_max) 9216 return MODE_H_ILLEGAL; 9217 9218 if (mode->vdisplay > plane_height_max) 9219 return MODE_V_ILLEGAL; 9220 9221 return MODE_OK; 9222 } 9223 9224 static const struct drm_mode_config_funcs intel_mode_funcs = { 9225 .fb_create = intel_user_framebuffer_create, 9226 .get_format_info = intel_fb_get_format_info, 9227 .output_poll_changed = intel_fbdev_output_poll_changed, 9228 .mode_valid = intel_mode_valid, 9229 .atomic_check = intel_atomic_check, 9230 .atomic_commit = intel_atomic_commit, 9231 .atomic_state_alloc = intel_atomic_state_alloc, 9232 .atomic_state_clear = intel_atomic_state_clear, 9233 .atomic_state_free = intel_atomic_state_free, 9234 }; 9235 9236 static const struct drm_i915_display_funcs skl_display_funcs = { 9237 .get_pipe_config = hsw_get_pipe_config, 9238 .crtc_enable = hsw_crtc_enable, 9239 .crtc_disable = hsw_crtc_disable, 9240 .commit_modeset_enables = skl_commit_modeset_enables, 9241 .get_initial_plane_config = skl_get_initial_plane_config, 9242 }; 9243 9244 static const struct drm_i915_display_funcs ddi_display_funcs = { 9245 .get_pipe_config = hsw_get_pipe_config, 9246 .crtc_enable = hsw_crtc_enable, 9247 .crtc_disable = hsw_crtc_disable, 9248 .commit_modeset_enables = intel_commit_modeset_enables, 9249 .get_initial_plane_config = i9xx_get_initial_plane_config, 9250 }; 9251 9252 static const struct drm_i915_display_funcs pch_split_display_funcs = { 9253 .get_pipe_config = ilk_get_pipe_config, 9254 .crtc_enable = ilk_crtc_enable, 9255 .crtc_disable = ilk_crtc_disable, 9256 .commit_modeset_enables = intel_commit_modeset_enables, 9257 .get_initial_plane_config = i9xx_get_initial_plane_config, 9258 }; 9259 9260 static const struct drm_i915_display_funcs vlv_display_funcs = { 9261 .get_pipe_config = i9xx_get_pipe_config, 9262 .crtc_enable = valleyview_crtc_enable, 9263 .crtc_disable = i9xx_crtc_disable, 9264 .commit_modeset_enables = intel_commit_modeset_enables, 9265 .get_initial_plane_config = i9xx_get_initial_plane_config, 9266 }; 9267 9268 static const struct drm_i915_display_funcs i9xx_display_funcs = { 9269 .get_pipe_config = i9xx_get_pipe_config, 9270 .crtc_enable = i9xx_crtc_enable, 9271 .crtc_disable = i9xx_crtc_disable, 9272 .commit_modeset_enables = intel_commit_modeset_enables, 9273 .get_initial_plane_config = i9xx_get_initial_plane_config, 9274 }; 9275 9276 /** 9277 * intel_init_display_hooks - initialize the display modesetting hooks 9278 * @dev_priv: device private 9279 */ 9280 void intel_init_display_hooks(struct drm_i915_private *dev_priv) 9281 { 9282 if (!HAS_DISPLAY(dev_priv)) 9283 return; 9284 9285 intel_init_cdclk_hooks(dev_priv); 9286 intel_audio_hooks_init(dev_priv); 9287 9288 intel_dpll_init_clock_hook(dev_priv); 9289 9290 if (DISPLAY_VER(dev_priv) >= 9) { 9291 dev_priv->display = &skl_display_funcs; 9292 } else if (HAS_DDI(dev_priv)) { 9293 dev_priv->display = &ddi_display_funcs; 9294 } else if (HAS_PCH_SPLIT(dev_priv)) { 9295 dev_priv->display = &pch_split_display_funcs; 9296 } else if (IS_CHERRYVIEW(dev_priv) || 9297 IS_VALLEYVIEW(dev_priv)) { 9298 dev_priv->display = &vlv_display_funcs; 9299 } else { 9300 dev_priv->display = &i9xx_display_funcs; 9301 } 9302 9303 intel_fdi_init_hook(dev_priv); 9304 } 9305 9306 void intel_modeset_init_hw(struct drm_i915_private *i915) 9307 { 9308 struct intel_cdclk_state *cdclk_state; 9309 9310 if (!HAS_DISPLAY(i915)) 9311 return; 9312 9313 cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state); 9314 9315 intel_update_cdclk(i915); 9316 intel_cdclk_dump_config(i915, &i915->cdclk.hw, "Current CDCLK"); 9317 cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw; 9318 } 9319 9320 static int sanitize_watermarks_add_affected(struct drm_atomic_state *state) 9321 { 9322 struct drm_plane *plane; 9323 struct intel_crtc *crtc; 9324 9325 for_each_intel_crtc(state->dev, crtc) { 9326 struct intel_crtc_state *crtc_state; 9327 9328 crtc_state = intel_atomic_get_crtc_state(state, crtc); 9329 if (IS_ERR(crtc_state)) 9330 return PTR_ERR(crtc_state); 9331 9332 if (crtc_state->hw.active) { 9333 /* 9334 * Preserve the inherited flag to avoid 9335 * taking the full modeset path. 9336 */ 9337 crtc_state->inherited = true; 9338 } 9339 } 9340 9341 drm_for_each_plane(plane, state->dev) { 9342 struct drm_plane_state *plane_state; 9343 9344 plane_state = drm_atomic_get_plane_state(state, plane); 9345 if (IS_ERR(plane_state)) 9346 return PTR_ERR(plane_state); 9347 } 9348 9349 return 0; 9350 } 9351 9352 /* 9353 * Calculate what we think the watermarks should be for the state we've read 9354 * out of the hardware and then immediately program those watermarks so that 9355 * we ensure the hardware settings match our internal state. 9356 * 9357 * We can calculate what we think WM's should be by creating a duplicate of the 9358 * current state (which was constructed during hardware readout) and running it 9359 * through the atomic check code to calculate new watermark values in the 9360 * state object. 9361 */ 9362 static void sanitize_watermarks(struct drm_i915_private *dev_priv) 9363 { 9364 struct drm_atomic_state *state; 9365 struct intel_atomic_state *intel_state; 9366 struct intel_crtc *crtc; 9367 struct intel_crtc_state *crtc_state; 9368 struct drm_modeset_acquire_ctx ctx; 9369 int ret; 9370 int i; 9371 9372 /* Only supported on platforms that use atomic watermark design */ 9373 if (!dev_priv->wm_disp->optimize_watermarks) 9374 return; 9375 9376 state = drm_atomic_state_alloc(&dev_priv->drm); 9377 if (drm_WARN_ON(&dev_priv->drm, !state)) 9378 return; 9379 9380 intel_state = to_intel_atomic_state(state); 9381 9382 drm_modeset_acquire_init(&ctx, 0); 9383 9384 retry: 9385 state->acquire_ctx = &ctx; 9386 9387 /* 9388 * Hardware readout is the only time we don't want to calculate 9389 * intermediate watermarks (since we don't trust the current 9390 * watermarks). 9391 */ 9392 if (!HAS_GMCH(dev_priv)) 9393 intel_state->skip_intermediate_wm = true; 9394 9395 ret = sanitize_watermarks_add_affected(state); 9396 if (ret) 9397 goto fail; 9398 9399 ret = intel_atomic_check(&dev_priv->drm, state); 9400 if (ret) 9401 goto fail; 9402 9403 /* Write calculated watermark values back */ 9404 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) { 9405 crtc_state->wm.need_postvbl_update = true; 9406 intel_optimize_watermarks(intel_state, crtc); 9407 9408 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm; 9409 } 9410 9411 fail: 9412 if (ret == -EDEADLK) { 9413 drm_atomic_state_clear(state); 9414 drm_modeset_backoff(&ctx); 9415 goto retry; 9416 } 9417 9418 /* 9419 * If we fail here, it means that the hardware appears to be 9420 * programmed in a way that shouldn't be possible, given our 9421 * understanding of watermark requirements. This might mean a 9422 * mistake in the hardware readout code or a mistake in the 9423 * watermark calculations for a given platform. Raise a WARN 9424 * so that this is noticeable. 9425 * 9426 * If this actually happens, we'll have to just leave the 9427 * BIOS-programmed watermarks untouched and hope for the best. 9428 */ 9429 drm_WARN(&dev_priv->drm, ret, 9430 "Could not determine valid watermarks for inherited state\n"); 9431 9432 drm_atomic_state_put(state); 9433 9434 drm_modeset_drop_locks(&ctx); 9435 drm_modeset_acquire_fini(&ctx); 9436 } 9437 9438 static int intel_initial_commit(struct drm_device *dev) 9439 { 9440 struct drm_atomic_state *state = NULL; 9441 struct drm_modeset_acquire_ctx ctx; 9442 struct intel_crtc *crtc; 9443 int ret = 0; 9444 9445 state = drm_atomic_state_alloc(dev); 9446 if (!state) 9447 return -ENOMEM; 9448 9449 drm_modeset_acquire_init(&ctx, 0); 9450 9451 retry: 9452 state->acquire_ctx = &ctx; 9453 9454 for_each_intel_crtc(dev, crtc) { 9455 struct intel_crtc_state *crtc_state = 9456 intel_atomic_get_crtc_state(state, crtc); 9457 9458 if (IS_ERR(crtc_state)) { 9459 ret = PTR_ERR(crtc_state); 9460 goto out; 9461 } 9462 9463 if (crtc_state->hw.active) { 9464 struct intel_encoder *encoder; 9465 9466 /* 9467 * We've not yet detected sink capabilities 9468 * (audio,infoframes,etc.) and thus we don't want to 9469 * force a full state recomputation yet. We want that to 9470 * happen only for the first real commit from userspace. 9471 * So preserve the inherited flag for the time being. 9472 */ 9473 crtc_state->inherited = true; 9474 9475 ret = drm_atomic_add_affected_planes(state, &crtc->base); 9476 if (ret) 9477 goto out; 9478 9479 /* 9480 * FIXME hack to force a LUT update to avoid the 9481 * plane update forcing the pipe gamma on without 9482 * having a proper LUT loaded. Remove once we 9483 * have readout for pipe gamma enable. 9484 */ 9485 crtc_state->uapi.color_mgmt_changed = true; 9486 9487 for_each_intel_encoder_mask(dev, encoder, 9488 crtc_state->uapi.encoder_mask) { 9489 if (encoder->initial_fastset_check && 9490 !encoder->initial_fastset_check(encoder, crtc_state)) { 9491 ret = drm_atomic_add_affected_connectors(state, 9492 &crtc->base); 9493 if (ret) 9494 goto out; 9495 } 9496 } 9497 } 9498 } 9499 9500 ret = drm_atomic_commit(state); 9501 9502 out: 9503 if (ret == -EDEADLK) { 9504 drm_atomic_state_clear(state); 9505 drm_modeset_backoff(&ctx); 9506 goto retry; 9507 } 9508 9509 drm_atomic_state_put(state); 9510 9511 drm_modeset_drop_locks(&ctx); 9512 drm_modeset_acquire_fini(&ctx); 9513 9514 return ret; 9515 } 9516 9517 static void intel_mode_config_init(struct drm_i915_private *i915) 9518 { 9519 struct drm_mode_config *mode_config = &i915->drm.mode_config; 9520 9521 drm_mode_config_init(&i915->drm); 9522 INIT_LIST_HEAD(&i915->global_obj_list); 9523 9524 mode_config->min_width = 0; 9525 mode_config->min_height = 0; 9526 9527 mode_config->preferred_depth = 24; 9528 mode_config->prefer_shadow = 1; 9529 9530 mode_config->funcs = &intel_mode_funcs; 9531 9532 mode_config->async_page_flip = HAS_ASYNC_FLIPS(i915); 9533 9534 /* 9535 * Maximum framebuffer dimensions, chosen to match 9536 * the maximum render engine surface size on gen4+. 9537 */ 9538 if (DISPLAY_VER(i915) >= 7) { 9539 mode_config->max_width = 16384; 9540 mode_config->max_height = 16384; 9541 } else if (DISPLAY_VER(i915) >= 4) { 9542 mode_config->max_width = 8192; 9543 mode_config->max_height = 8192; 9544 } else if (DISPLAY_VER(i915) == 3) { 9545 mode_config->max_width = 4096; 9546 mode_config->max_height = 4096; 9547 } else { 9548 mode_config->max_width = 2048; 9549 mode_config->max_height = 2048; 9550 } 9551 9552 if (IS_I845G(i915) || IS_I865G(i915)) { 9553 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512; 9554 mode_config->cursor_height = 1023; 9555 } else if (IS_I830(i915) || IS_I85X(i915) || 9556 IS_I915G(i915) || IS_I915GM(i915)) { 9557 mode_config->cursor_width = 64; 9558 mode_config->cursor_height = 64; 9559 } else { 9560 mode_config->cursor_width = 256; 9561 mode_config->cursor_height = 256; 9562 } 9563 } 9564 9565 static void intel_mode_config_cleanup(struct drm_i915_private *i915) 9566 { 9567 intel_atomic_global_obj_cleanup(i915); 9568 drm_mode_config_cleanup(&i915->drm); 9569 } 9570 9571 /* part #1: call before irq install */ 9572 int intel_modeset_init_noirq(struct drm_i915_private *i915) 9573 { 9574 int ret; 9575 9576 if (i915_inject_probe_failure(i915)) 9577 return -ENODEV; 9578 9579 if (HAS_DISPLAY(i915)) { 9580 ret = drm_vblank_init(&i915->drm, 9581 INTEL_NUM_PIPES(i915)); 9582 if (ret) 9583 return ret; 9584 } 9585 9586 intel_bios_init(i915); 9587 9588 ret = intel_vga_register(i915); 9589 if (ret) 9590 goto cleanup_bios; 9591 9592 /* FIXME: completely on the wrong abstraction layer */ 9593 intel_power_domains_init_hw(i915, false); 9594 9595 if (!HAS_DISPLAY(i915)) 9596 return 0; 9597 9598 intel_dmc_ucode_init(i915); 9599 9600 i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0); 9601 i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI | 9602 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE); 9603 9604 i915->window2_delay = 0; /* No DSB so no window2 delay */ 9605 9606 intel_mode_config_init(i915); 9607 9608 ret = intel_cdclk_init(i915); 9609 if (ret) 9610 goto cleanup_vga_client_pw_domain_dmc; 9611 9612 ret = intel_dbuf_init(i915); 9613 if (ret) 9614 goto cleanup_vga_client_pw_domain_dmc; 9615 9616 ret = intel_bw_init(i915); 9617 if (ret) 9618 goto cleanup_vga_client_pw_domain_dmc; 9619 9620 init_llist_head(&i915->atomic_helper.free_list); 9621 INIT_WORK(&i915->atomic_helper.free_work, 9622 intel_atomic_helper_free_state_worker); 9623 9624 intel_init_quirks(i915); 9625 9626 intel_fbc_init(i915); 9627 9628 return 0; 9629 9630 cleanup_vga_client_pw_domain_dmc: 9631 intel_dmc_ucode_fini(i915); 9632 intel_power_domains_driver_remove(i915); 9633 intel_vga_unregister(i915); 9634 cleanup_bios: 9635 intel_bios_driver_remove(i915); 9636 9637 return ret; 9638 } 9639 9640 /* part #2: call after irq install, but before gem init */ 9641 int intel_modeset_init_nogem(struct drm_i915_private *i915) 9642 { 9643 struct drm_device *dev = &i915->drm; 9644 enum pipe pipe; 9645 struct intel_crtc *crtc; 9646 int ret; 9647 9648 if (!HAS_DISPLAY(i915)) 9649 return 0; 9650 9651 intel_init_pm(i915); 9652 9653 intel_panel_sanitize_ssc(i915); 9654 9655 intel_pps_setup(i915); 9656 9657 intel_gmbus_setup(i915); 9658 9659 drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n", 9660 INTEL_NUM_PIPES(i915), 9661 INTEL_NUM_PIPES(i915) > 1 ? "s" : ""); 9662 9663 for_each_pipe(i915, pipe) { 9664 ret = intel_crtc_init(i915, pipe); 9665 if (ret) { 9666 intel_mode_config_cleanup(i915); 9667 return ret; 9668 } 9669 } 9670 9671 intel_plane_possible_crtcs_init(i915); 9672 intel_shared_dpll_init(i915); 9673 intel_fdi_pll_freq_update(i915); 9674 9675 intel_update_czclk(i915); 9676 intel_modeset_init_hw(i915); 9677 intel_dpll_update_ref_clks(i915); 9678 9679 intel_hdcp_component_init(i915); 9680 9681 if (i915->max_cdclk_freq == 0) 9682 intel_update_max_cdclk(i915); 9683 9684 /* 9685 * If the platform has HTI, we need to find out whether it has reserved 9686 * any display resources before we create our display outputs. 9687 */ 9688 if (INTEL_INFO(i915)->display.has_hti) 9689 i915->hti_state = intel_de_read(i915, HDPORT_STATE); 9690 9691 /* Just disable it once at startup */ 9692 intel_vga_disable(i915); 9693 intel_setup_outputs(i915); 9694 9695 drm_modeset_lock_all(dev); 9696 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx); 9697 intel_acpi_assign_connector_fwnodes(i915); 9698 drm_modeset_unlock_all(dev); 9699 9700 for_each_intel_crtc(dev, crtc) { 9701 if (!to_intel_crtc_state(crtc->base.state)->uapi.active) 9702 continue; 9703 intel_crtc_initial_plane_config(crtc); 9704 } 9705 9706 /* 9707 * Make sure hardware watermarks really match the state we read out. 9708 * Note that we need to do this after reconstructing the BIOS fb's 9709 * since the watermark calculation done here will use pstate->fb. 9710 */ 9711 if (!HAS_GMCH(i915)) 9712 sanitize_watermarks(i915); 9713 9714 return 0; 9715 } 9716 9717 /* part #3: call after gem init */ 9718 int intel_modeset_init(struct drm_i915_private *i915) 9719 { 9720 int ret; 9721 9722 if (!HAS_DISPLAY(i915)) 9723 return 0; 9724 9725 /* 9726 * Force all active planes to recompute their states. So that on 9727 * mode_setcrtc after probe, all the intel_plane_state variables 9728 * are already calculated and there is no assert_plane warnings 9729 * during bootup. 9730 */ 9731 ret = intel_initial_commit(&i915->drm); 9732 if (ret) 9733 drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret); 9734 9735 intel_overlay_setup(i915); 9736 9737 ret = intel_fbdev_init(&i915->drm); 9738 if (ret) 9739 return ret; 9740 9741 /* Only enable hotplug handling once the fbdev is fully set up. */ 9742 intel_hpd_init(i915); 9743 intel_hpd_poll_disable(i915); 9744 9745 intel_init_ipc(i915); 9746 9747 return 0; 9748 } 9749 9750 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 9751 { 9752 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 9753 /* 640x480@60Hz, ~25175 kHz */ 9754 struct dpll clock = { 9755 .m1 = 18, 9756 .m2 = 7, 9757 .p1 = 13, 9758 .p2 = 4, 9759 .n = 2, 9760 }; 9761 u32 dpll, fp; 9762 int i; 9763 9764 drm_WARN_ON(&dev_priv->drm, 9765 i9xx_calc_dpll_params(48000, &clock) != 25154); 9766 9767 drm_dbg_kms(&dev_priv->drm, 9768 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n", 9769 pipe_name(pipe), clock.vco, clock.dot); 9770 9771 fp = i9xx_dpll_compute_fp(&clock); 9772 dpll = DPLL_DVO_2X_MODE | 9773 DPLL_VGA_MODE_DIS | 9774 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | 9775 PLL_P2_DIVIDE_BY_4 | 9776 PLL_REF_INPUT_DREFCLK | 9777 DPLL_VCO_ENABLE; 9778 9779 intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16)); 9780 intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16)); 9781 intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16)); 9782 intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16)); 9783 intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16)); 9784 intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16)); 9785 intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1)); 9786 9787 intel_de_write(dev_priv, FP0(pipe), fp); 9788 intel_de_write(dev_priv, FP1(pipe), fp); 9789 9790 /* 9791 * Apparently we need to have VGA mode enabled prior to changing 9792 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 9793 * dividers, even though the register value does change. 9794 */ 9795 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); 9796 intel_de_write(dev_priv, DPLL(pipe), dpll); 9797 9798 /* Wait for the clocks to stabilize. */ 9799 intel_de_posting_read(dev_priv, DPLL(pipe)); 9800 udelay(150); 9801 9802 /* The pixel multiplier can only be updated once the 9803 * DPLL is enabled and the clocks are stable. 9804 * 9805 * So write it again. 9806 */ 9807 intel_de_write(dev_priv, DPLL(pipe), dpll); 9808 9809 /* We do this three times for luck */ 9810 for (i = 0; i < 3 ; i++) { 9811 intel_de_write(dev_priv, DPLL(pipe), dpll); 9812 intel_de_posting_read(dev_priv, DPLL(pipe)); 9813 udelay(150); /* wait for warmup */ 9814 } 9815 9816 intel_de_write(dev_priv, PIPECONF(pipe), PIPECONF_ENABLE); 9817 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 9818 9819 intel_wait_for_pipe_scanline_moving(crtc); 9820 } 9821 9822 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 9823 { 9824 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 9825 9826 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n", 9827 pipe_name(pipe)); 9828 9829 drm_WARN_ON(&dev_priv->drm, 9830 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE); 9831 drm_WARN_ON(&dev_priv->drm, 9832 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE); 9833 drm_WARN_ON(&dev_priv->drm, 9834 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE); 9835 drm_WARN_ON(&dev_priv->drm, 9836 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK); 9837 drm_WARN_ON(&dev_priv->drm, 9838 intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK); 9839 9840 intel_de_write(dev_priv, PIPECONF(pipe), 0); 9841 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 9842 9843 intel_wait_for_pipe_scanline_stopped(crtc); 9844 9845 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); 9846 intel_de_posting_read(dev_priv, DPLL(pipe)); 9847 } 9848 9849 static void 9850 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv) 9851 { 9852 struct intel_crtc *crtc; 9853 9854 if (DISPLAY_VER(dev_priv) >= 4) 9855 return; 9856 9857 for_each_intel_crtc(&dev_priv->drm, crtc) { 9858 struct intel_plane *plane = 9859 to_intel_plane(crtc->base.primary); 9860 struct intel_crtc *plane_crtc; 9861 enum pipe pipe; 9862 9863 if (!plane->get_hw_state(plane, &pipe)) 9864 continue; 9865 9866 if (pipe == crtc->pipe) 9867 continue; 9868 9869 drm_dbg_kms(&dev_priv->drm, 9870 "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n", 9871 plane->base.base.id, plane->base.name); 9872 9873 plane_crtc = intel_crtc_for_pipe(dev_priv, pipe); 9874 intel_plane_disable_noatomic(plane_crtc, plane); 9875 } 9876 } 9877 9878 static bool intel_crtc_has_encoders(struct intel_crtc *crtc) 9879 { 9880 struct drm_device *dev = crtc->base.dev; 9881 struct intel_encoder *encoder; 9882 9883 for_each_encoder_on_crtc(dev, &crtc->base, encoder) 9884 return true; 9885 9886 return false; 9887 } 9888 9889 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) 9890 { 9891 struct drm_device *dev = encoder->base.dev; 9892 struct intel_connector *connector; 9893 9894 for_each_connector_on_encoder(dev, &encoder->base, connector) 9895 return connector; 9896 9897 return NULL; 9898 } 9899 9900 static void intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state *crtc_state) 9901 { 9902 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 9903 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 9904 9905 if (!crtc_state->hw.active && !HAS_GMCH(i915)) 9906 return; 9907 9908 /* 9909 * We start out with underrun reporting disabled to avoid races. 9910 * For correct bookkeeping mark this on active crtcs. 9911 * 9912 * Also on gmch platforms we dont have any hardware bits to 9913 * disable the underrun reporting. Which means we need to start 9914 * out with underrun reporting disabled also on inactive pipes, 9915 * since otherwise we'll complain about the garbage we read when 9916 * e.g. coming up after runtime pm. 9917 * 9918 * No protection against concurrent access is required - at 9919 * worst a fifo underrun happens which also sets this to false. 9920 */ 9921 crtc->cpu_fifo_underrun_disabled = true; 9922 9923 /* 9924 * We track the PCH trancoder underrun reporting state 9925 * within the crtc. With crtc for pipe A housing the underrun 9926 * reporting state for PCH transcoder A, crtc for pipe B housing 9927 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, 9928 * and marking underrun reporting as disabled for the non-existing 9929 * PCH transcoders B and C would prevent enabling the south 9930 * error interrupt (see cpt_can_enable_serr_int()). 9931 */ 9932 if (intel_has_pch_trancoder(i915, crtc->pipe)) 9933 crtc->pch_fifo_underrun_disabled = true; 9934 } 9935 9936 static void intel_sanitize_crtc(struct intel_crtc *crtc, 9937 struct drm_modeset_acquire_ctx *ctx) 9938 { 9939 struct drm_device *dev = crtc->base.dev; 9940 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); 9941 9942 if (crtc_state->hw.active) { 9943 struct intel_plane *plane; 9944 9945 /* Disable everything but the primary plane */ 9946 for_each_intel_plane_on_crtc(dev, crtc, plane) { 9947 const struct intel_plane_state *plane_state = 9948 to_intel_plane_state(plane->base.state); 9949 9950 if (plane_state->uapi.visible && 9951 plane->base.type != DRM_PLANE_TYPE_PRIMARY) 9952 intel_plane_disable_noatomic(crtc, plane); 9953 } 9954 9955 /* Disable any background color/etc. set by the BIOS */ 9956 intel_color_commit_noarm(crtc_state); 9957 intel_color_commit_arm(crtc_state); 9958 } 9959 9960 /* Adjust the state of the output pipe according to whether we 9961 * have active connectors/encoders. */ 9962 if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) && 9963 !intel_crtc_is_bigjoiner_slave(crtc_state)) 9964 intel_crtc_disable_noatomic(crtc, ctx); 9965 9966 intel_sanitize_fifo_underrun_reporting(crtc_state); 9967 } 9968 9969 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state) 9970 { 9971 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 9972 9973 /* 9974 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram 9975 * the hardware when a high res displays plugged in. DPLL P 9976 * divider is zero, and the pipe timings are bonkers. We'll 9977 * try to disable everything in that case. 9978 * 9979 * FIXME would be nice to be able to sanitize this state 9980 * without several WARNs, but for now let's take the easy 9981 * road. 9982 */ 9983 return IS_SANDYBRIDGE(dev_priv) && 9984 crtc_state->hw.active && 9985 crtc_state->shared_dpll && 9986 crtc_state->port_clock == 0; 9987 } 9988 9989 static void intel_sanitize_encoder(struct intel_encoder *encoder) 9990 { 9991 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 9992 struct intel_connector *connector; 9993 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 9994 struct intel_crtc_state *crtc_state = crtc ? 9995 to_intel_crtc_state(crtc->base.state) : NULL; 9996 9997 /* We need to check both for a crtc link (meaning that the 9998 * encoder is active and trying to read from a pipe) and the 9999 * pipe itself being active. */ 10000 bool has_active_crtc = crtc_state && 10001 crtc_state->hw.active; 10002 10003 if (crtc_state && has_bogus_dpll_config(crtc_state)) { 10004 drm_dbg_kms(&dev_priv->drm, 10005 "BIOS has misprogrammed the hardware. Disabling pipe %c\n", 10006 pipe_name(crtc->pipe)); 10007 has_active_crtc = false; 10008 } 10009 10010 connector = intel_encoder_find_connector(encoder); 10011 if (connector && !has_active_crtc) { 10012 drm_dbg_kms(&dev_priv->drm, 10013 "[ENCODER:%d:%s] has active connectors but no active pipe!\n", 10014 encoder->base.base.id, 10015 encoder->base.name); 10016 10017 /* Connector is active, but has no active pipe. This is 10018 * fallout from our resume register restoring. Disable 10019 * the encoder manually again. */ 10020 if (crtc_state) { 10021 struct drm_encoder *best_encoder; 10022 10023 drm_dbg_kms(&dev_priv->drm, 10024 "[ENCODER:%d:%s] manually disabled\n", 10025 encoder->base.base.id, 10026 encoder->base.name); 10027 10028 /* avoid oopsing in case the hooks consult best_encoder */ 10029 best_encoder = connector->base.state->best_encoder; 10030 connector->base.state->best_encoder = &encoder->base; 10031 10032 /* FIXME NULL atomic state passed! */ 10033 if (encoder->disable) 10034 encoder->disable(NULL, encoder, crtc_state, 10035 connector->base.state); 10036 if (encoder->post_disable) 10037 encoder->post_disable(NULL, encoder, crtc_state, 10038 connector->base.state); 10039 10040 connector->base.state->best_encoder = best_encoder; 10041 } 10042 encoder->base.crtc = NULL; 10043 10044 /* Inconsistent output/port/pipe state happens presumably due to 10045 * a bug in one of the get_hw_state functions. Or someplace else 10046 * in our code, like the register restore mess on resume. Clamp 10047 * things to off as a safer default. */ 10048 10049 connector->base.dpms = DRM_MODE_DPMS_OFF; 10050 connector->base.encoder = NULL; 10051 } 10052 10053 /* notify opregion of the sanitized encoder state */ 10054 intel_opregion_notify_encoder(encoder, connector && has_active_crtc); 10055 10056 if (HAS_DDI(dev_priv)) 10057 intel_ddi_sanitize_encoder_pll_mapping(encoder); 10058 } 10059 10060 /* FIXME read out full plane state for all planes */ 10061 static void readout_plane_state(struct drm_i915_private *dev_priv) 10062 { 10063 struct intel_plane *plane; 10064 struct intel_crtc *crtc; 10065 10066 for_each_intel_plane(&dev_priv->drm, plane) { 10067 struct intel_plane_state *plane_state = 10068 to_intel_plane_state(plane->base.state); 10069 struct intel_crtc_state *crtc_state; 10070 enum pipe pipe = PIPE_A; 10071 bool visible; 10072 10073 visible = plane->get_hw_state(plane, &pipe); 10074 10075 crtc = intel_crtc_for_pipe(dev_priv, pipe); 10076 crtc_state = to_intel_crtc_state(crtc->base.state); 10077 10078 intel_set_plane_visible(crtc_state, plane_state, visible); 10079 10080 drm_dbg_kms(&dev_priv->drm, 10081 "[PLANE:%d:%s] hw state readout: %s, pipe %c\n", 10082 plane->base.base.id, plane->base.name, 10083 str_enabled_disabled(visible), pipe_name(pipe)); 10084 } 10085 10086 for_each_intel_crtc(&dev_priv->drm, crtc) { 10087 struct intel_crtc_state *crtc_state = 10088 to_intel_crtc_state(crtc->base.state); 10089 10090 fixup_plane_bitmasks(crtc_state); 10091 } 10092 } 10093 10094 static void intel_modeset_readout_hw_state(struct drm_device *dev) 10095 { 10096 struct drm_i915_private *dev_priv = to_i915(dev); 10097 struct intel_cdclk_state *cdclk_state = 10098 to_intel_cdclk_state(dev_priv->cdclk.obj.state); 10099 struct intel_dbuf_state *dbuf_state = 10100 to_intel_dbuf_state(dev_priv->dbuf.obj.state); 10101 enum pipe pipe; 10102 struct intel_crtc *crtc; 10103 struct intel_encoder *encoder; 10104 struct intel_connector *connector; 10105 struct drm_connector_list_iter conn_iter; 10106 u8 active_pipes = 0; 10107 10108 for_each_intel_crtc(dev, crtc) { 10109 struct intel_crtc_state *crtc_state = 10110 to_intel_crtc_state(crtc->base.state); 10111 10112 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi); 10113 intel_crtc_free_hw_state(crtc_state); 10114 intel_crtc_state_reset(crtc_state, crtc); 10115 10116 intel_crtc_get_pipe_config(crtc_state); 10117 10118 crtc_state->hw.enable = crtc_state->hw.active; 10119 10120 crtc->base.enabled = crtc_state->hw.enable; 10121 crtc->active = crtc_state->hw.active; 10122 10123 if (crtc_state->hw.active) 10124 active_pipes |= BIT(crtc->pipe); 10125 10126 drm_dbg_kms(&dev_priv->drm, 10127 "[CRTC:%d:%s] hw state readout: %s\n", 10128 crtc->base.base.id, crtc->base.name, 10129 str_enabled_disabled(crtc_state->hw.active)); 10130 } 10131 10132 cdclk_state->active_pipes = dbuf_state->active_pipes = active_pipes; 10133 10134 readout_plane_state(dev_priv); 10135 10136 for_each_intel_encoder(dev, encoder) { 10137 struct intel_crtc_state *crtc_state = NULL; 10138 10139 pipe = 0; 10140 10141 if (encoder->get_hw_state(encoder, &pipe)) { 10142 crtc = intel_crtc_for_pipe(dev_priv, pipe); 10143 crtc_state = to_intel_crtc_state(crtc->base.state); 10144 10145 encoder->base.crtc = &crtc->base; 10146 intel_encoder_get_config(encoder, crtc_state); 10147 10148 /* read out to slave crtc as well for bigjoiner */ 10149 if (crtc_state->bigjoiner_pipes) { 10150 struct intel_crtc *slave_crtc; 10151 10152 /* encoder should read be linked to bigjoiner master */ 10153 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 10154 10155 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc, 10156 intel_crtc_bigjoiner_slave_pipes(crtc_state)) { 10157 struct intel_crtc_state *slave_crtc_state; 10158 10159 slave_crtc_state = to_intel_crtc_state(slave_crtc->base.state); 10160 intel_encoder_get_config(encoder, slave_crtc_state); 10161 } 10162 } 10163 } else { 10164 encoder->base.crtc = NULL; 10165 } 10166 10167 if (encoder->sync_state) 10168 encoder->sync_state(encoder, crtc_state); 10169 10170 drm_dbg_kms(&dev_priv->drm, 10171 "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", 10172 encoder->base.base.id, encoder->base.name, 10173 str_enabled_disabled(encoder->base.crtc), 10174 pipe_name(pipe)); 10175 } 10176 10177 intel_dpll_readout_hw_state(dev_priv); 10178 10179 drm_connector_list_iter_begin(dev, &conn_iter); 10180 for_each_intel_connector_iter(connector, &conn_iter) { 10181 if (connector->get_hw_state(connector)) { 10182 struct intel_crtc_state *crtc_state; 10183 struct intel_crtc *crtc; 10184 10185 connector->base.dpms = DRM_MODE_DPMS_ON; 10186 10187 encoder = intel_attached_encoder(connector); 10188 connector->base.encoder = &encoder->base; 10189 10190 crtc = to_intel_crtc(encoder->base.crtc); 10191 crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL; 10192 10193 if (crtc_state && crtc_state->hw.active) { 10194 /* 10195 * This has to be done during hardware readout 10196 * because anything calling .crtc_disable may 10197 * rely on the connector_mask being accurate. 10198 */ 10199 crtc_state->uapi.connector_mask |= 10200 drm_connector_mask(&connector->base); 10201 crtc_state->uapi.encoder_mask |= 10202 drm_encoder_mask(&encoder->base); 10203 } 10204 } else { 10205 connector->base.dpms = DRM_MODE_DPMS_OFF; 10206 connector->base.encoder = NULL; 10207 } 10208 drm_dbg_kms(&dev_priv->drm, 10209 "[CONNECTOR:%d:%s] hw state readout: %s\n", 10210 connector->base.base.id, connector->base.name, 10211 str_enabled_disabled(connector->base.encoder)); 10212 } 10213 drm_connector_list_iter_end(&conn_iter); 10214 10215 for_each_intel_crtc(dev, crtc) { 10216 struct intel_bw_state *bw_state = 10217 to_intel_bw_state(dev_priv->bw_obj.state); 10218 struct intel_crtc_state *crtc_state = 10219 to_intel_crtc_state(crtc->base.state); 10220 struct intel_plane *plane; 10221 int min_cdclk = 0; 10222 10223 if (crtc_state->hw.active) { 10224 /* 10225 * The initial mode needs to be set in order to keep 10226 * the atomic core happy. It wants a valid mode if the 10227 * crtc's enabled, so we do the above call. 10228 * 10229 * But we don't set all the derived state fully, hence 10230 * set a flag to indicate that a full recalculation is 10231 * needed on the next commit. 10232 */ 10233 crtc_state->inherited = true; 10234 10235 intel_crtc_update_active_timings(crtc_state); 10236 10237 intel_crtc_copy_hw_to_uapi_state(crtc_state); 10238 } 10239 10240 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 10241 const struct intel_plane_state *plane_state = 10242 to_intel_plane_state(plane->base.state); 10243 10244 /* 10245 * FIXME don't have the fb yet, so can't 10246 * use intel_plane_data_rate() :( 10247 */ 10248 if (plane_state->uapi.visible) 10249 crtc_state->data_rate[plane->id] = 10250 4 * crtc_state->pixel_rate; 10251 /* 10252 * FIXME don't have the fb yet, so can't 10253 * use plane->min_cdclk() :( 10254 */ 10255 if (plane_state->uapi.visible && plane->min_cdclk) { 10256 if (crtc_state->double_wide || DISPLAY_VER(dev_priv) >= 10) 10257 crtc_state->min_cdclk[plane->id] = 10258 DIV_ROUND_UP(crtc_state->pixel_rate, 2); 10259 else 10260 crtc_state->min_cdclk[plane->id] = 10261 crtc_state->pixel_rate; 10262 } 10263 drm_dbg_kms(&dev_priv->drm, 10264 "[PLANE:%d:%s] min_cdclk %d kHz\n", 10265 plane->base.base.id, plane->base.name, 10266 crtc_state->min_cdclk[plane->id]); 10267 } 10268 10269 if (crtc_state->hw.active) { 10270 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); 10271 if (drm_WARN_ON(dev, min_cdclk < 0)) 10272 min_cdclk = 0; 10273 } 10274 10275 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; 10276 cdclk_state->min_voltage_level[crtc->pipe] = 10277 crtc_state->min_voltage_level; 10278 10279 intel_bw_crtc_update(bw_state, crtc_state); 10280 } 10281 } 10282 10283 static void 10284 get_encoder_power_domains(struct drm_i915_private *dev_priv) 10285 { 10286 struct intel_encoder *encoder; 10287 10288 for_each_intel_encoder(&dev_priv->drm, encoder) { 10289 struct intel_crtc_state *crtc_state; 10290 10291 if (!encoder->get_power_domains) 10292 continue; 10293 10294 /* 10295 * MST-primary and inactive encoders don't have a crtc state 10296 * and neither of these require any power domain references. 10297 */ 10298 if (!encoder->base.crtc) 10299 continue; 10300 10301 crtc_state = to_intel_crtc_state(encoder->base.crtc->state); 10302 encoder->get_power_domains(encoder, crtc_state); 10303 } 10304 } 10305 10306 static void intel_early_display_was(struct drm_i915_private *dev_priv) 10307 { 10308 /* 10309 * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl 10310 * Also known as Wa_14010480278. 10311 */ 10312 if (IS_DISPLAY_VER(dev_priv, 10, 12)) 10313 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0, 10314 intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS); 10315 10316 if (IS_HASWELL(dev_priv)) { 10317 /* 10318 * WaRsPkgCStateDisplayPMReq:hsw 10319 * System hang if this isn't done before disabling all planes! 10320 */ 10321 intel_de_write(dev_priv, CHICKEN_PAR1_1, 10322 intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); 10323 } 10324 10325 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) { 10326 /* Display WA #1142:kbl,cfl,cml */ 10327 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 10328 KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22); 10329 intel_de_rmw(dev_priv, CHICKEN_MISC_2, 10330 KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14, 10331 KBL_ARB_FILL_SPARE_14); 10332 } 10333 } 10334 10335 10336 /* Scan out the current hw modeset state, 10337 * and sanitizes it to the current state 10338 */ 10339 static void 10340 intel_modeset_setup_hw_state(struct drm_device *dev, 10341 struct drm_modeset_acquire_ctx *ctx) 10342 { 10343 struct drm_i915_private *dev_priv = to_i915(dev); 10344 struct intel_encoder *encoder; 10345 struct intel_crtc *crtc; 10346 intel_wakeref_t wakeref; 10347 10348 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 10349 10350 intel_early_display_was(dev_priv); 10351 intel_modeset_readout_hw_state(dev); 10352 10353 /* HW state is read out, now we need to sanitize this mess. */ 10354 get_encoder_power_domains(dev_priv); 10355 10356 intel_pch_sanitize(dev_priv); 10357 10358 /* 10359 * intel_sanitize_plane_mapping() may need to do vblank 10360 * waits, so we need vblank interrupts restored beforehand. 10361 */ 10362 for_each_intel_crtc(&dev_priv->drm, crtc) { 10363 struct intel_crtc_state *crtc_state = 10364 to_intel_crtc_state(crtc->base.state); 10365 10366 drm_crtc_vblank_reset(&crtc->base); 10367 10368 if (crtc_state->hw.active) 10369 intel_crtc_vblank_on(crtc_state); 10370 } 10371 10372 intel_fbc_sanitize(dev_priv); 10373 10374 intel_sanitize_plane_mapping(dev_priv); 10375 10376 for_each_intel_encoder(dev, encoder) 10377 intel_sanitize_encoder(encoder); 10378 10379 for_each_intel_crtc(&dev_priv->drm, crtc) { 10380 struct intel_crtc_state *crtc_state = 10381 to_intel_crtc_state(crtc->base.state); 10382 10383 intel_sanitize_crtc(crtc, ctx); 10384 intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]"); 10385 } 10386 10387 intel_modeset_update_connector_atomic_state(dev); 10388 10389 intel_dpll_sanitize_state(dev_priv); 10390 10391 if (IS_G4X(dev_priv)) { 10392 g4x_wm_get_hw_state(dev_priv); 10393 g4x_wm_sanitize(dev_priv); 10394 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 10395 vlv_wm_get_hw_state(dev_priv); 10396 vlv_wm_sanitize(dev_priv); 10397 } else if (DISPLAY_VER(dev_priv) >= 9) { 10398 skl_wm_get_hw_state(dev_priv); 10399 skl_wm_sanitize(dev_priv); 10400 } else if (HAS_PCH_SPLIT(dev_priv)) { 10401 ilk_wm_get_hw_state(dev_priv); 10402 } 10403 10404 for_each_intel_crtc(dev, crtc) { 10405 struct intel_crtc_state *crtc_state = 10406 to_intel_crtc_state(crtc->base.state); 10407 struct intel_power_domain_mask put_domains; 10408 10409 modeset_get_crtc_power_domains(crtc_state, &put_domains); 10410 if (drm_WARN_ON(dev, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM))) 10411 modeset_put_crtc_power_domains(crtc, &put_domains); 10412 } 10413 10414 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref); 10415 10416 intel_power_domains_sanitize_state(dev_priv); 10417 } 10418 10419 void intel_display_resume(struct drm_device *dev) 10420 { 10421 struct drm_i915_private *dev_priv = to_i915(dev); 10422 struct drm_atomic_state *state = dev_priv->modeset_restore_state; 10423 struct drm_modeset_acquire_ctx ctx; 10424 int ret; 10425 10426 if (!HAS_DISPLAY(dev_priv)) 10427 return; 10428 10429 dev_priv->modeset_restore_state = NULL; 10430 if (state) 10431 state->acquire_ctx = &ctx; 10432 10433 drm_modeset_acquire_init(&ctx, 0); 10434 10435 while (1) { 10436 ret = drm_modeset_lock_all_ctx(dev, &ctx); 10437 if (ret != -EDEADLK) 10438 break; 10439 10440 drm_modeset_backoff(&ctx); 10441 } 10442 10443 if (!ret) 10444 ret = __intel_display_resume(dev, state, &ctx); 10445 10446 intel_enable_ipc(dev_priv); 10447 drm_modeset_drop_locks(&ctx); 10448 drm_modeset_acquire_fini(&ctx); 10449 10450 if (ret) 10451 drm_err(&dev_priv->drm, 10452 "Restoring old state failed with %i\n", ret); 10453 if (state) 10454 drm_atomic_state_put(state); 10455 } 10456 10457 static void intel_hpd_poll_fini(struct drm_i915_private *i915) 10458 { 10459 struct intel_connector *connector; 10460 struct drm_connector_list_iter conn_iter; 10461 10462 /* Kill all the work that may have been queued by hpd. */ 10463 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 10464 for_each_intel_connector_iter(connector, &conn_iter) { 10465 if (connector->modeset_retry_work.func) 10466 cancel_work_sync(&connector->modeset_retry_work); 10467 if (connector->hdcp.shim) { 10468 cancel_delayed_work_sync(&connector->hdcp.check_work); 10469 cancel_work_sync(&connector->hdcp.prop_work); 10470 } 10471 } 10472 drm_connector_list_iter_end(&conn_iter); 10473 } 10474 10475 /* part #1: call before irq uninstall */ 10476 void intel_modeset_driver_remove(struct drm_i915_private *i915) 10477 { 10478 if (!HAS_DISPLAY(i915)) 10479 return; 10480 10481 flush_workqueue(i915->flip_wq); 10482 flush_workqueue(i915->modeset_wq); 10483 10484 flush_work(&i915->atomic_helper.free_work); 10485 drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list)); 10486 } 10487 10488 /* part #2: call after irq uninstall */ 10489 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915) 10490 { 10491 if (!HAS_DISPLAY(i915)) 10492 return; 10493 10494 /* 10495 * Due to the hpd irq storm handling the hotplug work can re-arm the 10496 * poll handlers. Hence disable polling after hpd handling is shut down. 10497 */ 10498 intel_hpd_poll_fini(i915); 10499 10500 /* 10501 * MST topology needs to be suspended so we don't have any calls to 10502 * fbdev after it's finalized. MST will be destroyed later as part of 10503 * drm_mode_config_cleanup() 10504 */ 10505 intel_dp_mst_suspend(i915); 10506 10507 /* poll work can call into fbdev, hence clean that up afterwards */ 10508 intel_fbdev_fini(i915); 10509 10510 intel_unregister_dsm_handler(); 10511 10512 /* flush any delayed tasks or pending work */ 10513 flush_scheduled_work(); 10514 10515 intel_hdcp_component_fini(i915); 10516 10517 intel_mode_config_cleanup(i915); 10518 10519 intel_overlay_cleanup(i915); 10520 10521 intel_gmbus_teardown(i915); 10522 10523 destroy_workqueue(i915->flip_wq); 10524 destroy_workqueue(i915->modeset_wq); 10525 10526 intel_fbc_cleanup(i915); 10527 } 10528 10529 /* part #3: call after gem init */ 10530 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915) 10531 { 10532 intel_dmc_ucode_fini(i915); 10533 10534 intel_power_domains_driver_remove(i915); 10535 10536 intel_vga_unregister(i915); 10537 10538 intel_bios_driver_remove(i915); 10539 } 10540 10541 bool intel_modeset_probe_defer(struct pci_dev *pdev) 10542 { 10543 struct drm_privacy_screen *privacy_screen; 10544 10545 /* 10546 * apple-gmux is needed on dual GPU MacBook Pro 10547 * to probe the panel if we're the inactive GPU. 10548 */ 10549 if (vga_switcheroo_client_probe_defer(pdev)) 10550 return true; 10551 10552 /* If the LCD panel has a privacy-screen, wait for it */ 10553 privacy_screen = drm_privacy_screen_get(&pdev->dev, NULL); 10554 if (IS_ERR(privacy_screen) && PTR_ERR(privacy_screen) == -EPROBE_DEFER) 10555 return true; 10556 10557 drm_privacy_screen_put(privacy_screen); 10558 10559 return false; 10560 } 10561 10562 void intel_display_driver_register(struct drm_i915_private *i915) 10563 { 10564 if (!HAS_DISPLAY(i915)) 10565 return; 10566 10567 intel_display_debugfs_register(i915); 10568 10569 /* Must be done after probing outputs */ 10570 intel_opregion_register(i915); 10571 acpi_video_register(); 10572 10573 intel_audio_init(i915); 10574 10575 /* 10576 * Some ports require correctly set-up hpd registers for 10577 * detection to work properly (leading to ghost connected 10578 * connector status), e.g. VGA on gm45. Hence we can only set 10579 * up the initial fbdev config after hpd irqs are fully 10580 * enabled. We do it last so that the async config cannot run 10581 * before the connectors are registered. 10582 */ 10583 intel_fbdev_initial_config_async(&i915->drm); 10584 10585 /* 10586 * We need to coordinate the hotplugs with the asynchronous 10587 * fbdev configuration, for which we use the 10588 * fbdev->async_cookie. 10589 */ 10590 drm_kms_helper_poll_init(&i915->drm); 10591 } 10592 10593 void intel_display_driver_unregister(struct drm_i915_private *i915) 10594 { 10595 if (!HAS_DISPLAY(i915)) 10596 return; 10597 10598 intel_fbdev_unregister(i915); 10599 intel_audio_deinit(i915); 10600 10601 /* 10602 * After flushing the fbdev (incl. a late async config which 10603 * will have delayed queuing of a hotplug event), then flush 10604 * the hotplug events. 10605 */ 10606 drm_kms_helper_poll_fini(&i915->drm); 10607 drm_atomic_helper_shutdown(&i915->drm); 10608 10609 acpi_video_unregister(); 10610 intel_opregion_unregister(i915); 10611 } 10612 10613 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915) 10614 { 10615 return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915); 10616 } 10617