1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <linux/dma-resv.h> 28 #include <linux/i2c.h> 29 #include <linux/input.h> 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/slab.h> 33 #include <linux/string_helpers.h> 34 35 #include <drm/display/drm_dp_helper.h> 36 #include <drm/drm_atomic.h> 37 #include <drm/drm_atomic_helper.h> 38 #include <drm/drm_atomic_uapi.h> 39 #include <drm/drm_damage_helper.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_fourcc.h> 42 #include <drm/drm_probe_helper.h> 43 #include <drm/drm_rect.h> 44 45 #include "gem/i915_gem_lmem.h" 46 #include "gem/i915_gem_object.h" 47 48 #include "g4x_dp.h" 49 #include "g4x_hdmi.h" 50 #include "hsw_ips.h" 51 #include "i915_drv.h" 52 #include "i915_reg.h" 53 #include "i915_utils.h" 54 #include "i9xx_plane.h" 55 #include "i9xx_wm.h" 56 #include "icl_dsi.h" 57 #include "intel_atomic.h" 58 #include "intel_atomic_plane.h" 59 #include "intel_audio.h" 60 #include "intel_bw.h" 61 #include "intel_cdclk.h" 62 #include "intel_clock_gating.h" 63 #include "intel_color.h" 64 #include "intel_crt.h" 65 #include "intel_crtc.h" 66 #include "intel_crtc_state_dump.h" 67 #include "intel_ddi.h" 68 #include "intel_de.h" 69 #include "intel_display_driver.h" 70 #include "intel_display_power.h" 71 #include "intel_display_types.h" 72 #include "intel_dmc.h" 73 #include "intel_dp.h" 74 #include "intel_dp_link_training.h" 75 #include "intel_dp_mst.h" 76 #include "intel_dpio_phy.h" 77 #include "intel_dpll.h" 78 #include "intel_dpll_mgr.h" 79 #include "intel_dpt.h" 80 #include "intel_drrs.h" 81 #include "intel_dsi.h" 82 #include "intel_dvo.h" 83 #include "intel_fb.h" 84 #include "intel_fbc.h" 85 #include "intel_fbdev.h" 86 #include "intel_fdi.h" 87 #include "intel_fifo_underrun.h" 88 #include "intel_frontbuffer.h" 89 #include "intel_hdmi.h" 90 #include "intel_hotplug.h" 91 #include "intel_lvds.h" 92 #include "intel_lvds_regs.h" 93 #include "intel_modeset_setup.h" 94 #include "intel_modeset_verify.h" 95 #include "intel_overlay.h" 96 #include "intel_panel.h" 97 #include "intel_pch_display.h" 98 #include "intel_pch_refclk.h" 99 #include "intel_pcode.h" 100 #include "intel_pipe_crc.h" 101 #include "intel_plane_initial.h" 102 #include "intel_pps.h" 103 #include "intel_psr.h" 104 #include "intel_sdvo.h" 105 #include "intel_snps_phy.h" 106 #include "intel_tc.h" 107 #include "intel_tv.h" 108 #include "intel_vblank.h" 109 #include "intel_vdsc.h" 110 #include "intel_vdsc_regs.h" 111 #include "intel_vga.h" 112 #include "intel_vrr.h" 113 #include "intel_wm.h" 114 #include "skl_scaler.h" 115 #include "skl_universal_plane.h" 116 #include "skl_watermark.h" 117 #include "vlv_dsi.h" 118 #include "vlv_dsi_pll.h" 119 #include "vlv_dsi_regs.h" 120 #include "vlv_sideband.h" 121 122 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state); 123 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state); 124 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state); 125 static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state); 126 127 /* returns HPLL frequency in kHz */ 128 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) 129 { 130 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; 131 132 /* Obtain SKU information */ 133 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & 134 CCK_FUSE_HPLL_FREQ_MASK; 135 136 return vco_freq[hpll_freq] * 1000; 137 } 138 139 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 140 const char *name, u32 reg, int ref_freq) 141 { 142 u32 val; 143 int divider; 144 145 val = vlv_cck_read(dev_priv, reg); 146 divider = val & CCK_FREQUENCY_VALUES; 147 148 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != 149 (divider << CCK_FREQUENCY_STATUS_SHIFT), 150 "%s change in progress\n", name); 151 152 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); 153 } 154 155 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 156 const char *name, u32 reg) 157 { 158 int hpll; 159 160 vlv_cck_get(dev_priv); 161 162 if (dev_priv->hpll_freq == 0) 163 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); 164 165 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); 166 167 vlv_cck_put(dev_priv); 168 169 return hpll; 170 } 171 172 void intel_update_czclk(struct drm_i915_private *dev_priv) 173 { 174 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) 175 return; 176 177 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", 178 CCK_CZ_CLOCK_CONTROL); 179 180 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", 181 dev_priv->czclk_freq); 182 } 183 184 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state) 185 { 186 return (crtc_state->active_planes & 187 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0; 188 } 189 190 /* WA Display #0827: Gen9:all */ 191 static void 192 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) 193 { 194 if (enable) 195 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 196 0, DUPS1_GATING_DIS | DUPS2_GATING_DIS); 197 else 198 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 199 DUPS1_GATING_DIS | DUPS2_GATING_DIS, 0); 200 } 201 202 /* Wa_2006604312:icl,ehl */ 203 static void 204 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 205 bool enable) 206 { 207 if (enable) 208 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 0, DPFR_GATING_DIS); 209 else 210 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), DPFR_GATING_DIS, 0); 211 } 212 213 /* Wa_1604331009:icl,jsl,ehl */ 214 static void 215 icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 216 bool enable) 217 { 218 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), CURSOR_GATING_DIS, 219 enable ? CURSOR_GATING_DIS : 0); 220 } 221 222 static bool 223 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state) 224 { 225 return crtc_state->master_transcoder != INVALID_TRANSCODER; 226 } 227 228 static bool 229 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state) 230 { 231 return crtc_state->sync_mode_slaves_mask != 0; 232 } 233 234 bool 235 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state) 236 { 237 return is_trans_port_sync_master(crtc_state) || 238 is_trans_port_sync_slave(crtc_state); 239 } 240 241 static enum pipe bigjoiner_master_pipe(const struct intel_crtc_state *crtc_state) 242 { 243 return ffs(crtc_state->bigjoiner_pipes) - 1; 244 } 245 246 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state) 247 { 248 if (crtc_state->bigjoiner_pipes) 249 return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state)); 250 else 251 return 0; 252 } 253 254 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state) 255 { 256 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 257 258 return crtc_state->bigjoiner_pipes && 259 crtc->pipe != bigjoiner_master_pipe(crtc_state); 260 } 261 262 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state) 263 { 264 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 265 266 return crtc_state->bigjoiner_pipes && 267 crtc->pipe == bigjoiner_master_pipe(crtc_state); 268 } 269 270 static int intel_bigjoiner_num_pipes(const struct intel_crtc_state *crtc_state) 271 { 272 return hweight8(crtc_state->bigjoiner_pipes); 273 } 274 275 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state) 276 { 277 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 278 279 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 280 return intel_crtc_for_pipe(i915, bigjoiner_master_pipe(crtc_state)); 281 else 282 return to_intel_crtc(crtc_state->uapi.crtc); 283 } 284 285 static void 286 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) 287 { 288 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 289 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 290 291 if (DISPLAY_VER(dev_priv) >= 4) { 292 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 293 294 /* Wait for the Pipe State to go off */ 295 if (intel_de_wait_for_clear(dev_priv, TRANSCONF(cpu_transcoder), 296 TRANSCONF_STATE_ENABLE, 100)) 297 drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n"); 298 } else { 299 intel_wait_for_pipe_scanline_stopped(crtc); 300 } 301 } 302 303 void assert_transcoder(struct drm_i915_private *dev_priv, 304 enum transcoder cpu_transcoder, bool state) 305 { 306 bool cur_state; 307 enum intel_display_power_domain power_domain; 308 intel_wakeref_t wakeref; 309 310 /* we keep both pipes enabled on 830 */ 311 if (IS_I830(dev_priv)) 312 state = true; 313 314 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 315 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 316 if (wakeref) { 317 u32 val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)); 318 cur_state = !!(val & TRANSCONF_ENABLE); 319 320 intel_display_power_put(dev_priv, power_domain, wakeref); 321 } else { 322 cur_state = false; 323 } 324 325 I915_STATE_WARN(cur_state != state, 326 "transcoder %s assertion failure (expected %s, current %s)\n", 327 transcoder_name(cpu_transcoder), 328 str_on_off(state), str_on_off(cur_state)); 329 } 330 331 static void assert_plane(struct intel_plane *plane, bool state) 332 { 333 enum pipe pipe; 334 bool cur_state; 335 336 cur_state = plane->get_hw_state(plane, &pipe); 337 338 I915_STATE_WARN(cur_state != state, 339 "%s assertion failure (expected %s, current %s)\n", 340 plane->base.name, str_on_off(state), 341 str_on_off(cur_state)); 342 } 343 344 #define assert_plane_enabled(p) assert_plane(p, true) 345 #define assert_plane_disabled(p) assert_plane(p, false) 346 347 static void assert_planes_disabled(struct intel_crtc *crtc) 348 { 349 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 350 struct intel_plane *plane; 351 352 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) 353 assert_plane_disabled(plane); 354 } 355 356 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 357 struct intel_digital_port *dig_port, 358 unsigned int expected_mask) 359 { 360 u32 port_mask; 361 i915_reg_t dpll_reg; 362 363 switch (dig_port->base.port) { 364 default: 365 MISSING_CASE(dig_port->base.port); 366 fallthrough; 367 case PORT_B: 368 port_mask = DPLL_PORTB_READY_MASK; 369 dpll_reg = DPLL(0); 370 break; 371 case PORT_C: 372 port_mask = DPLL_PORTC_READY_MASK; 373 dpll_reg = DPLL(0); 374 expected_mask <<= 4; 375 break; 376 case PORT_D: 377 port_mask = DPLL_PORTD_READY_MASK; 378 dpll_reg = DPIO_PHY_STATUS; 379 break; 380 } 381 382 if (intel_de_wait_for_register(dev_priv, dpll_reg, 383 port_mask, expected_mask, 1000)) 384 drm_WARN(&dev_priv->drm, 1, 385 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", 386 dig_port->base.base.base.id, dig_port->base.base.name, 387 intel_de_read(dev_priv, dpll_reg) & port_mask, 388 expected_mask); 389 } 390 391 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) 392 { 393 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 394 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 395 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 396 enum pipe pipe = crtc->pipe; 397 i915_reg_t reg; 398 u32 val; 399 400 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe)); 401 402 assert_planes_disabled(crtc); 403 404 /* 405 * A pipe without a PLL won't actually be able to drive bits from 406 * a plane. On ILK+ the pipe PLLs are integrated, so we don't 407 * need the check. 408 */ 409 if (HAS_GMCH(dev_priv)) { 410 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI)) 411 assert_dsi_pll_enabled(dev_priv); 412 else 413 assert_pll_enabled(dev_priv, pipe); 414 } else { 415 if (new_crtc_state->has_pch_encoder) { 416 /* if driving the PCH, we need FDI enabled */ 417 assert_fdi_rx_pll_enabled(dev_priv, 418 intel_crtc_pch_transcoder(crtc)); 419 assert_fdi_tx_pll_enabled(dev_priv, 420 (enum pipe) cpu_transcoder); 421 } 422 /* FIXME: assert CPU port conditions for SNB+ */ 423 } 424 425 /* Wa_22012358565:adl-p */ 426 if (DISPLAY_VER(dev_priv) == 13) 427 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe), 428 0, PIPE_ARB_USE_PROG_SLOTS); 429 430 reg = TRANSCONF(cpu_transcoder); 431 val = intel_de_read(dev_priv, reg); 432 if (val & TRANSCONF_ENABLE) { 433 /* we keep both pipes enabled on 830 */ 434 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv)); 435 return; 436 } 437 438 intel_de_write(dev_priv, reg, val | TRANSCONF_ENABLE); 439 intel_de_posting_read(dev_priv, reg); 440 441 /* 442 * Until the pipe starts PIPEDSL reads will return a stale value, 443 * which causes an apparent vblank timestamp jump when PIPEDSL 444 * resets to its proper value. That also messes up the frame count 445 * when it's derived from the timestamps. So let's wait for the 446 * pipe to start properly before we call drm_crtc_vblank_on() 447 */ 448 if (intel_crtc_max_vblank_count(new_crtc_state) == 0) 449 intel_wait_for_pipe_scanline_moving(crtc); 450 } 451 452 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) 453 { 454 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 455 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 456 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 457 enum pipe pipe = crtc->pipe; 458 i915_reg_t reg; 459 u32 val; 460 461 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe)); 462 463 /* 464 * Make sure planes won't keep trying to pump pixels to us, 465 * or we might hang the display. 466 */ 467 assert_planes_disabled(crtc); 468 469 reg = TRANSCONF(cpu_transcoder); 470 val = intel_de_read(dev_priv, reg); 471 if ((val & TRANSCONF_ENABLE) == 0) 472 return; 473 474 /* 475 * Double wide has implications for planes 476 * so best keep it disabled when not needed. 477 */ 478 if (old_crtc_state->double_wide) 479 val &= ~TRANSCONF_DOUBLE_WIDE; 480 481 /* Don't disable pipe or pipe PLLs if needed */ 482 if (!IS_I830(dev_priv)) 483 val &= ~TRANSCONF_ENABLE; 484 485 if (DISPLAY_VER(dev_priv) >= 14) 486 intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder), 487 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 488 else if (DISPLAY_VER(dev_priv) >= 12) 489 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 490 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 491 492 intel_de_write(dev_priv, reg, val); 493 if ((val & TRANSCONF_ENABLE) == 0) 494 intel_wait_for_pipe_off(old_crtc_state); 495 } 496 497 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) 498 { 499 unsigned int size = 0; 500 int i; 501 502 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) 503 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width; 504 505 return size; 506 } 507 508 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info) 509 { 510 unsigned int size = 0; 511 int i; 512 513 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) { 514 unsigned int plane_size; 515 516 if (rem_info->plane[i].linear) 517 plane_size = rem_info->plane[i].size; 518 else 519 plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height; 520 521 if (plane_size == 0) 522 continue; 523 524 if (rem_info->plane_alignment) 525 size = ALIGN(size, rem_info->plane_alignment); 526 527 size += plane_size; 528 } 529 530 return size; 531 } 532 533 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) 534 { 535 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 536 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 537 538 return DISPLAY_VER(dev_priv) < 4 || 539 (plane->fbc && 540 plane_state->view.gtt.type == I915_GTT_VIEW_NORMAL); 541 } 542 543 /* 544 * Convert the x/y offsets into a linear offset. 545 * Only valid with 0/180 degree rotation, which is fine since linear 546 * offset is only used with linear buffers on pre-hsw and tiled buffers 547 * with gen2/3, and 90/270 degree rotations isn't supported on any of them. 548 */ 549 u32 intel_fb_xy_to_linear(int x, int y, 550 const struct intel_plane_state *state, 551 int color_plane) 552 { 553 const struct drm_framebuffer *fb = state->hw.fb; 554 unsigned int cpp = fb->format->cpp[color_plane]; 555 unsigned int pitch = state->view.color_plane[color_plane].mapping_stride; 556 557 return y * pitch + x * cpp; 558 } 559 560 /* 561 * Add the x/y offsets derived from fb->offsets[] to the user 562 * specified plane src x/y offsets. The resulting x/y offsets 563 * specify the start of scanout from the beginning of the gtt mapping. 564 */ 565 void intel_add_fb_offsets(int *x, int *y, 566 const struct intel_plane_state *state, 567 int color_plane) 568 569 { 570 *x += state->view.color_plane[color_plane].x; 571 *y += state->view.color_plane[color_plane].y; 572 } 573 574 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 575 u32 pixel_format, u64 modifier) 576 { 577 struct intel_crtc *crtc; 578 struct intel_plane *plane; 579 580 if (!HAS_DISPLAY(dev_priv)) 581 return 0; 582 583 /* 584 * We assume the primary plane for pipe A has 585 * the highest stride limits of them all, 586 * if in case pipe A is disabled, use the first pipe from pipe_mask. 587 */ 588 crtc = intel_first_crtc(dev_priv); 589 if (!crtc) 590 return 0; 591 592 plane = to_intel_plane(crtc->base.primary); 593 594 return plane->max_stride(plane, pixel_format, modifier, 595 DRM_MODE_ROTATE_0); 596 } 597 598 void intel_set_plane_visible(struct intel_crtc_state *crtc_state, 599 struct intel_plane_state *plane_state, 600 bool visible) 601 { 602 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 603 604 plane_state->uapi.visible = visible; 605 606 if (visible) 607 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base); 608 else 609 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base); 610 } 611 612 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state) 613 { 614 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 615 struct drm_plane *plane; 616 617 /* 618 * Active_planes aliases if multiple "primary" or cursor planes 619 * have been used on the same (or wrong) pipe. plane_mask uses 620 * unique ids, hence we can use that to reconstruct active_planes. 621 */ 622 crtc_state->enabled_planes = 0; 623 crtc_state->active_planes = 0; 624 625 drm_for_each_plane_mask(plane, &dev_priv->drm, 626 crtc_state->uapi.plane_mask) { 627 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id); 628 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id); 629 } 630 } 631 632 void intel_plane_disable_noatomic(struct intel_crtc *crtc, 633 struct intel_plane *plane) 634 { 635 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 636 struct intel_crtc_state *crtc_state = 637 to_intel_crtc_state(crtc->base.state); 638 struct intel_plane_state *plane_state = 639 to_intel_plane_state(plane->base.state); 640 641 drm_dbg_kms(&dev_priv->drm, 642 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n", 643 plane->base.base.id, plane->base.name, 644 crtc->base.base.id, crtc->base.name); 645 646 intel_set_plane_visible(crtc_state, plane_state, false); 647 intel_plane_fixup_bitmasks(crtc_state); 648 crtc_state->data_rate[plane->id] = 0; 649 crtc_state->data_rate_y[plane->id] = 0; 650 crtc_state->rel_data_rate[plane->id] = 0; 651 crtc_state->rel_data_rate_y[plane->id] = 0; 652 crtc_state->min_cdclk[plane->id] = 0; 653 654 if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 && 655 hsw_ips_disable(crtc_state)) { 656 crtc_state->ips_enabled = false; 657 intel_crtc_wait_for_next_vblank(crtc); 658 } 659 660 /* 661 * Vblank time updates from the shadow to live plane control register 662 * are blocked if the memory self-refresh mode is active at that 663 * moment. So to make sure the plane gets truly disabled, disable 664 * first the self-refresh mode. The self-refresh enable bit in turn 665 * will be checked/applied by the HW only at the next frame start 666 * event which is after the vblank start event, so we need to have a 667 * wait-for-vblank between disabling the plane and the pipe. 668 */ 669 if (HAS_GMCH(dev_priv) && 670 intel_set_memory_cxsr(dev_priv, false)) 671 intel_crtc_wait_for_next_vblank(crtc); 672 673 /* 674 * Gen2 reports pipe underruns whenever all planes are disabled. 675 * So disable underrun reporting before all the planes get disabled. 676 */ 677 if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes) 678 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); 679 680 intel_plane_disable_arm(plane, crtc_state); 681 intel_crtc_wait_for_next_vblank(crtc); 682 } 683 684 unsigned int 685 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state) 686 { 687 int x = 0, y = 0; 688 689 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, 690 plane_state->view.color_plane[0].offset, 0); 691 692 return y; 693 } 694 695 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) 696 { 697 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 698 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 699 enum pipe pipe = crtc->pipe; 700 u32 tmp; 701 702 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe)); 703 704 /* 705 * Display WA #1153: icl 706 * enable hardware to bypass the alpha math 707 * and rounding for per-pixel values 00 and 0xff 708 */ 709 tmp |= PER_PIXEL_ALPHA_BYPASS_EN; 710 /* 711 * Display WA # 1605353570: icl 712 * Set the pixel rounding bit to 1 for allowing 713 * passthrough of Frame buffer pixels unmodified 714 * across pipe 715 */ 716 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU; 717 718 /* 719 * Underrun recovery must always be disabled on display 13+. 720 * DG2 chicken bit meaning is inverted compared to other platforms. 721 */ 722 if (IS_DG2(dev_priv)) 723 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2; 724 else if (DISPLAY_VER(dev_priv) >= 13) 725 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP; 726 727 /* Wa_14010547955:dg2 */ 728 if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER)) 729 tmp |= DG2_RENDER_CCSTAG_4_3_EN; 730 731 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp); 732 } 733 734 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) 735 { 736 struct drm_crtc *crtc; 737 bool cleanup_done; 738 739 drm_for_each_crtc(crtc, &dev_priv->drm) { 740 struct drm_crtc_commit *commit; 741 spin_lock(&crtc->commit_lock); 742 commit = list_first_entry_or_null(&crtc->commit_list, 743 struct drm_crtc_commit, commit_entry); 744 cleanup_done = commit ? 745 try_wait_for_completion(&commit->cleanup_done) : true; 746 spin_unlock(&crtc->commit_lock); 747 748 if (cleanup_done) 749 continue; 750 751 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc)); 752 753 return true; 754 } 755 756 return false; 757 } 758 759 /* 760 * Finds the encoder associated with the given CRTC. This can only be 761 * used when we know that the CRTC isn't feeding multiple encoders! 762 */ 763 struct intel_encoder * 764 intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 765 const struct intel_crtc_state *crtc_state) 766 { 767 const struct drm_connector_state *connector_state; 768 const struct drm_connector *connector; 769 struct intel_encoder *encoder = NULL; 770 struct intel_crtc *master_crtc; 771 int num_encoders = 0; 772 int i; 773 774 master_crtc = intel_master_crtc(crtc_state); 775 776 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 777 if (connector_state->crtc != &master_crtc->base) 778 continue; 779 780 encoder = to_intel_encoder(connector_state->best_encoder); 781 num_encoders++; 782 } 783 784 drm_WARN(state->base.dev, num_encoders != 1, 785 "%d encoders for pipe %c\n", 786 num_encoders, pipe_name(master_crtc->pipe)); 787 788 return encoder; 789 } 790 791 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state) 792 { 793 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 794 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 795 const struct drm_rect *dst = &crtc_state->pch_pfit.dst; 796 enum pipe pipe = crtc->pipe; 797 int width = drm_rect_width(dst); 798 int height = drm_rect_height(dst); 799 int x = dst->x1; 800 int y = dst->y1; 801 802 if (!crtc_state->pch_pfit.enabled) 803 return; 804 805 /* Force use of hard-coded filter coefficients 806 * as some pre-programmed values are broken, 807 * e.g. x201. 808 */ 809 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) 810 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 811 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe)); 812 else 813 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 814 PF_FILTER_MED_3x3); 815 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 816 PF_WIN_XPOS(x) | PF_WIN_YPOS(y)); 817 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 818 PF_WIN_XSIZE(width) | PF_WIN_YSIZE(height)); 819 } 820 821 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc) 822 { 823 if (crtc->overlay) 824 (void) intel_overlay_switch_off(crtc->overlay); 825 826 /* Let userspace switch the overlay on again. In most cases userspace 827 * has to recompute where to put it anyway. 828 */ 829 } 830 831 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state) 832 { 833 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 834 835 if (!crtc_state->nv12_planes) 836 return false; 837 838 /* WA Display #0827: Gen9:all */ 839 if (DISPLAY_VER(dev_priv) == 9) 840 return true; 841 842 return false; 843 } 844 845 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state) 846 { 847 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 848 849 /* Wa_2006604312:icl,ehl */ 850 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11) 851 return true; 852 853 return false; 854 } 855 856 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state) 857 { 858 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 859 860 /* Wa_1604331009:icl,jsl,ehl */ 861 if (is_hdr_mode(crtc_state) && 862 crtc_state->active_planes & BIT(PLANE_CURSOR) && 863 DISPLAY_VER(dev_priv) == 11) 864 return true; 865 866 return false; 867 } 868 869 static void intel_async_flip_vtd_wa(struct drm_i915_private *i915, 870 enum pipe pipe, bool enable) 871 { 872 if (DISPLAY_VER(i915) == 9) { 873 /* 874 * "Plane N strech max must be programmed to 11b (x1) 875 * when Async flips are enabled on that plane." 876 */ 877 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 878 SKL_PLANE1_STRETCH_MAX_MASK, 879 enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8); 880 } else { 881 /* Also needed on HSW/BDW albeit undocumented */ 882 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 883 HSW_PRI_STRETCH_MAX_MASK, 884 enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8); 885 } 886 } 887 888 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state) 889 { 890 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 891 892 return crtc_state->uapi.async_flip && i915_vtd_active(i915) && 893 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915)); 894 } 895 896 #define is_enabling(feature, old_crtc_state, new_crtc_state) \ 897 ((!(old_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)) && \ 898 (new_crtc_state)->feature) 899 #define is_disabling(feature, old_crtc_state, new_crtc_state) \ 900 ((old_crtc_state)->feature && \ 901 (!(new_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state))) 902 903 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state, 904 const struct intel_crtc_state *new_crtc_state) 905 { 906 return is_enabling(active_planes, old_crtc_state, new_crtc_state); 907 } 908 909 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state, 910 const struct intel_crtc_state *new_crtc_state) 911 { 912 return is_disabling(active_planes, old_crtc_state, new_crtc_state); 913 } 914 915 static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state, 916 const struct intel_crtc_state *new_crtc_state) 917 { 918 return is_enabling(vrr.enable, old_crtc_state, new_crtc_state); 919 } 920 921 static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state, 922 const struct intel_crtc_state *new_crtc_state) 923 { 924 return is_disabling(vrr.enable, old_crtc_state, new_crtc_state); 925 } 926 927 #undef is_disabling 928 #undef is_enabling 929 930 static void intel_post_plane_update(struct intel_atomic_state *state, 931 struct intel_crtc *crtc) 932 { 933 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 934 const struct intel_crtc_state *old_crtc_state = 935 intel_atomic_get_old_crtc_state(state, crtc); 936 const struct intel_crtc_state *new_crtc_state = 937 intel_atomic_get_new_crtc_state(state, crtc); 938 enum pipe pipe = crtc->pipe; 939 940 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); 941 942 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) 943 intel_update_watermarks(dev_priv); 944 945 intel_fbc_post_update(state, crtc); 946 947 if (needs_async_flip_vtd_wa(old_crtc_state) && 948 !needs_async_flip_vtd_wa(new_crtc_state)) 949 intel_async_flip_vtd_wa(dev_priv, pipe, false); 950 951 if (needs_nv12_wa(old_crtc_state) && 952 !needs_nv12_wa(new_crtc_state)) 953 skl_wa_827(dev_priv, pipe, false); 954 955 if (needs_scalerclk_wa(old_crtc_state) && 956 !needs_scalerclk_wa(new_crtc_state)) 957 icl_wa_scalerclkgating(dev_priv, pipe, false); 958 959 if (needs_cursorclk_wa(old_crtc_state) && 960 !needs_cursorclk_wa(new_crtc_state)) 961 icl_wa_cursorclkgating(dev_priv, pipe, false); 962 963 if (intel_crtc_needs_color_update(new_crtc_state)) 964 intel_color_post_update(new_crtc_state); 965 } 966 967 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state, 968 struct intel_crtc *crtc) 969 { 970 const struct intel_crtc_state *crtc_state = 971 intel_atomic_get_new_crtc_state(state, crtc); 972 u8 update_planes = crtc_state->update_planes; 973 const struct intel_plane_state *plane_state; 974 struct intel_plane *plane; 975 int i; 976 977 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 978 if (plane->pipe == crtc->pipe && 979 update_planes & BIT(plane->id)) 980 plane->enable_flip_done(plane); 981 } 982 } 983 984 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state, 985 struct intel_crtc *crtc) 986 { 987 const struct intel_crtc_state *crtc_state = 988 intel_atomic_get_new_crtc_state(state, crtc); 989 u8 update_planes = crtc_state->update_planes; 990 const struct intel_plane_state *plane_state; 991 struct intel_plane *plane; 992 int i; 993 994 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 995 if (plane->pipe == crtc->pipe && 996 update_planes & BIT(plane->id)) 997 plane->disable_flip_done(plane); 998 } 999 } 1000 1001 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state, 1002 struct intel_crtc *crtc) 1003 { 1004 const struct intel_crtc_state *old_crtc_state = 1005 intel_atomic_get_old_crtc_state(state, crtc); 1006 const struct intel_crtc_state *new_crtc_state = 1007 intel_atomic_get_new_crtc_state(state, crtc); 1008 u8 disable_async_flip_planes = old_crtc_state->async_flip_planes & 1009 ~new_crtc_state->async_flip_planes; 1010 const struct intel_plane_state *old_plane_state; 1011 struct intel_plane *plane; 1012 bool need_vbl_wait = false; 1013 int i; 1014 1015 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1016 if (plane->need_async_flip_disable_wa && 1017 plane->pipe == crtc->pipe && 1018 disable_async_flip_planes & BIT(plane->id)) { 1019 /* 1020 * Apart from the async flip bit we want to 1021 * preserve the old state for the plane. 1022 */ 1023 plane->async_flip(plane, old_crtc_state, 1024 old_plane_state, false); 1025 need_vbl_wait = true; 1026 } 1027 } 1028 1029 if (need_vbl_wait) 1030 intel_crtc_wait_for_next_vblank(crtc); 1031 } 1032 1033 static void intel_pre_plane_update(struct intel_atomic_state *state, 1034 struct intel_crtc *crtc) 1035 { 1036 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1037 const struct intel_crtc_state *old_crtc_state = 1038 intel_atomic_get_old_crtc_state(state, crtc); 1039 const struct intel_crtc_state *new_crtc_state = 1040 intel_atomic_get_new_crtc_state(state, crtc); 1041 enum pipe pipe = crtc->pipe; 1042 1043 if (vrr_disabling(old_crtc_state, new_crtc_state)) { 1044 intel_vrr_disable(old_crtc_state); 1045 intel_crtc_update_active_timings(old_crtc_state, false); 1046 } 1047 1048 intel_drrs_deactivate(old_crtc_state); 1049 1050 intel_psr_pre_plane_update(state, crtc); 1051 1052 if (hsw_ips_pre_update(state, crtc)) 1053 intel_crtc_wait_for_next_vblank(crtc); 1054 1055 if (intel_fbc_pre_update(state, crtc)) 1056 intel_crtc_wait_for_next_vblank(crtc); 1057 1058 if (!needs_async_flip_vtd_wa(old_crtc_state) && 1059 needs_async_flip_vtd_wa(new_crtc_state)) 1060 intel_async_flip_vtd_wa(dev_priv, pipe, true); 1061 1062 /* Display WA 827 */ 1063 if (!needs_nv12_wa(old_crtc_state) && 1064 needs_nv12_wa(new_crtc_state)) 1065 skl_wa_827(dev_priv, pipe, true); 1066 1067 /* Wa_2006604312:icl,ehl */ 1068 if (!needs_scalerclk_wa(old_crtc_state) && 1069 needs_scalerclk_wa(new_crtc_state)) 1070 icl_wa_scalerclkgating(dev_priv, pipe, true); 1071 1072 /* Wa_1604331009:icl,jsl,ehl */ 1073 if (!needs_cursorclk_wa(old_crtc_state) && 1074 needs_cursorclk_wa(new_crtc_state)) 1075 icl_wa_cursorclkgating(dev_priv, pipe, true); 1076 1077 /* 1078 * Vblank time updates from the shadow to live plane control register 1079 * are blocked if the memory self-refresh mode is active at that 1080 * moment. So to make sure the plane gets truly disabled, disable 1081 * first the self-refresh mode. The self-refresh enable bit in turn 1082 * will be checked/applied by the HW only at the next frame start 1083 * event which is after the vblank start event, so we need to have a 1084 * wait-for-vblank between disabling the plane and the pipe. 1085 */ 1086 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active && 1087 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) 1088 intel_crtc_wait_for_next_vblank(crtc); 1089 1090 /* 1091 * IVB workaround: must disable low power watermarks for at least 1092 * one frame before enabling scaling. LP watermarks can be re-enabled 1093 * when scaling is disabled. 1094 * 1095 * WaCxSRDisabledForSpriteScaling:ivb 1096 */ 1097 if (old_crtc_state->hw.active && 1098 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv)) 1099 intel_crtc_wait_for_next_vblank(crtc); 1100 1101 /* 1102 * If we're doing a modeset we don't need to do any 1103 * pre-vblank watermark programming here. 1104 */ 1105 if (!intel_crtc_needs_modeset(new_crtc_state)) { 1106 /* 1107 * For platforms that support atomic watermarks, program the 1108 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these 1109 * will be the intermediate values that are safe for both pre- and 1110 * post- vblank; when vblank happens, the 'active' values will be set 1111 * to the final 'target' values and we'll do this again to get the 1112 * optimal watermarks. For gen9+ platforms, the values we program here 1113 * will be the final target values which will get automatically latched 1114 * at vblank time; no further programming will be necessary. 1115 * 1116 * If a platform hasn't been transitioned to atomic watermarks yet, 1117 * we'll continue to update watermarks the old way, if flags tell 1118 * us to. 1119 */ 1120 if (!intel_initial_watermarks(state, crtc)) 1121 if (new_crtc_state->update_wm_pre) 1122 intel_update_watermarks(dev_priv); 1123 } 1124 1125 /* 1126 * Gen2 reports pipe underruns whenever all planes are disabled. 1127 * So disable underrun reporting before all the planes get disabled. 1128 * 1129 * We do this after .initial_watermarks() so that we have a 1130 * chance of catching underruns with the intermediate watermarks 1131 * vs. the old plane configuration. 1132 */ 1133 if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state)) 1134 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1135 1136 /* 1137 * WA for platforms where async address update enable bit 1138 * is double buffered and only latched at start of vblank. 1139 */ 1140 if (old_crtc_state->async_flip_planes & ~new_crtc_state->async_flip_planes) 1141 intel_crtc_async_flip_disable_wa(state, crtc); 1142 } 1143 1144 static void intel_crtc_disable_planes(struct intel_atomic_state *state, 1145 struct intel_crtc *crtc) 1146 { 1147 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1148 const struct intel_crtc_state *new_crtc_state = 1149 intel_atomic_get_new_crtc_state(state, crtc); 1150 unsigned int update_mask = new_crtc_state->update_planes; 1151 const struct intel_plane_state *old_plane_state; 1152 struct intel_plane *plane; 1153 unsigned fb_bits = 0; 1154 int i; 1155 1156 intel_crtc_dpms_overlay_disable(crtc); 1157 1158 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1159 if (crtc->pipe != plane->pipe || 1160 !(update_mask & BIT(plane->id))) 1161 continue; 1162 1163 intel_plane_disable_arm(plane, new_crtc_state); 1164 1165 if (old_plane_state->uapi.visible) 1166 fb_bits |= plane->frontbuffer_bit; 1167 } 1168 1169 intel_frontbuffer_flip(dev_priv, fb_bits); 1170 } 1171 1172 static void intel_encoders_update_prepare(struct intel_atomic_state *state) 1173 { 1174 struct drm_i915_private *i915 = to_i915(state->base.dev); 1175 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 1176 struct intel_crtc *crtc; 1177 int i; 1178 1179 /* 1180 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits. 1181 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook. 1182 */ 1183 if (i915->display.dpll.mgr) { 1184 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1185 if (intel_crtc_needs_modeset(new_crtc_state)) 1186 continue; 1187 1188 new_crtc_state->shared_dpll = old_crtc_state->shared_dpll; 1189 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state; 1190 } 1191 } 1192 } 1193 1194 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state, 1195 struct intel_crtc *crtc) 1196 { 1197 const struct intel_crtc_state *crtc_state = 1198 intel_atomic_get_new_crtc_state(state, crtc); 1199 const struct drm_connector_state *conn_state; 1200 struct drm_connector *conn; 1201 int i; 1202 1203 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1204 struct intel_encoder *encoder = 1205 to_intel_encoder(conn_state->best_encoder); 1206 1207 if (conn_state->crtc != &crtc->base) 1208 continue; 1209 1210 if (encoder->pre_pll_enable) 1211 encoder->pre_pll_enable(state, encoder, 1212 crtc_state, conn_state); 1213 } 1214 } 1215 1216 static void intel_encoders_pre_enable(struct intel_atomic_state *state, 1217 struct intel_crtc *crtc) 1218 { 1219 const struct intel_crtc_state *crtc_state = 1220 intel_atomic_get_new_crtc_state(state, crtc); 1221 const struct drm_connector_state *conn_state; 1222 struct drm_connector *conn; 1223 int i; 1224 1225 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1226 struct intel_encoder *encoder = 1227 to_intel_encoder(conn_state->best_encoder); 1228 1229 if (conn_state->crtc != &crtc->base) 1230 continue; 1231 1232 if (encoder->pre_enable) 1233 encoder->pre_enable(state, encoder, 1234 crtc_state, conn_state); 1235 } 1236 } 1237 1238 static void intel_encoders_enable(struct intel_atomic_state *state, 1239 struct intel_crtc *crtc) 1240 { 1241 const struct intel_crtc_state *crtc_state = 1242 intel_atomic_get_new_crtc_state(state, crtc); 1243 const struct drm_connector_state *conn_state; 1244 struct drm_connector *conn; 1245 int i; 1246 1247 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1248 struct intel_encoder *encoder = 1249 to_intel_encoder(conn_state->best_encoder); 1250 1251 if (conn_state->crtc != &crtc->base) 1252 continue; 1253 1254 if (encoder->enable) 1255 encoder->enable(state, encoder, 1256 crtc_state, conn_state); 1257 intel_opregion_notify_encoder(encoder, true); 1258 } 1259 } 1260 1261 static void intel_encoders_disable(struct intel_atomic_state *state, 1262 struct intel_crtc *crtc) 1263 { 1264 const struct intel_crtc_state *old_crtc_state = 1265 intel_atomic_get_old_crtc_state(state, crtc); 1266 const struct drm_connector_state *old_conn_state; 1267 struct drm_connector *conn; 1268 int i; 1269 1270 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1271 struct intel_encoder *encoder = 1272 to_intel_encoder(old_conn_state->best_encoder); 1273 1274 if (old_conn_state->crtc != &crtc->base) 1275 continue; 1276 1277 intel_opregion_notify_encoder(encoder, false); 1278 if (encoder->disable) 1279 encoder->disable(state, encoder, 1280 old_crtc_state, old_conn_state); 1281 } 1282 } 1283 1284 static void intel_encoders_post_disable(struct intel_atomic_state *state, 1285 struct intel_crtc *crtc) 1286 { 1287 const struct intel_crtc_state *old_crtc_state = 1288 intel_atomic_get_old_crtc_state(state, crtc); 1289 const struct drm_connector_state *old_conn_state; 1290 struct drm_connector *conn; 1291 int i; 1292 1293 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1294 struct intel_encoder *encoder = 1295 to_intel_encoder(old_conn_state->best_encoder); 1296 1297 if (old_conn_state->crtc != &crtc->base) 1298 continue; 1299 1300 if (encoder->post_disable) 1301 encoder->post_disable(state, encoder, 1302 old_crtc_state, old_conn_state); 1303 } 1304 } 1305 1306 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state, 1307 struct intel_crtc *crtc) 1308 { 1309 const struct intel_crtc_state *old_crtc_state = 1310 intel_atomic_get_old_crtc_state(state, crtc); 1311 const struct drm_connector_state *old_conn_state; 1312 struct drm_connector *conn; 1313 int i; 1314 1315 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1316 struct intel_encoder *encoder = 1317 to_intel_encoder(old_conn_state->best_encoder); 1318 1319 if (old_conn_state->crtc != &crtc->base) 1320 continue; 1321 1322 if (encoder->post_pll_disable) 1323 encoder->post_pll_disable(state, encoder, 1324 old_crtc_state, old_conn_state); 1325 } 1326 } 1327 1328 static void intel_encoders_update_pipe(struct intel_atomic_state *state, 1329 struct intel_crtc *crtc) 1330 { 1331 const struct intel_crtc_state *crtc_state = 1332 intel_atomic_get_new_crtc_state(state, crtc); 1333 const struct drm_connector_state *conn_state; 1334 struct drm_connector *conn; 1335 int i; 1336 1337 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1338 struct intel_encoder *encoder = 1339 to_intel_encoder(conn_state->best_encoder); 1340 1341 if (conn_state->crtc != &crtc->base) 1342 continue; 1343 1344 if (encoder->update_pipe) 1345 encoder->update_pipe(state, encoder, 1346 crtc_state, conn_state); 1347 } 1348 } 1349 1350 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state) 1351 { 1352 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1353 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 1354 1355 plane->disable_arm(plane, crtc_state); 1356 } 1357 1358 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1359 { 1360 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1361 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1362 1363 if (crtc_state->has_pch_encoder) { 1364 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1365 &crtc_state->fdi_m_n); 1366 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1367 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1368 &crtc_state->dp_m_n); 1369 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1370 &crtc_state->dp_m2_n2); 1371 } 1372 1373 intel_set_transcoder_timings(crtc_state); 1374 1375 ilk_set_pipeconf(crtc_state); 1376 } 1377 1378 static void ilk_crtc_enable(struct intel_atomic_state *state, 1379 struct intel_crtc *crtc) 1380 { 1381 const struct intel_crtc_state *new_crtc_state = 1382 intel_atomic_get_new_crtc_state(state, crtc); 1383 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1384 enum pipe pipe = crtc->pipe; 1385 1386 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1387 return; 1388 1389 /* 1390 * Sometimes spurious CPU pipe underruns happen during FDI 1391 * training, at least with VGA+HDMI cloning. Suppress them. 1392 * 1393 * On ILK we get an occasional spurious CPU pipe underruns 1394 * between eDP port A enable and vdd enable. Also PCH port 1395 * enable seems to result in the occasional CPU pipe underrun. 1396 * 1397 * Spurious PCH underruns also occur during PCH enabling. 1398 */ 1399 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1400 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 1401 1402 ilk_configure_cpu_transcoder(new_crtc_state); 1403 1404 intel_set_pipe_src_size(new_crtc_state); 1405 1406 crtc->active = true; 1407 1408 intel_encoders_pre_enable(state, crtc); 1409 1410 if (new_crtc_state->has_pch_encoder) { 1411 ilk_pch_pre_enable(state, crtc); 1412 } else { 1413 assert_fdi_tx_disabled(dev_priv, pipe); 1414 assert_fdi_rx_disabled(dev_priv, pipe); 1415 } 1416 1417 ilk_pfit_enable(new_crtc_state); 1418 1419 /* 1420 * On ILK+ LUT must be loaded before the pipe is running but with 1421 * clocks enabled 1422 */ 1423 intel_color_load_luts(new_crtc_state); 1424 intel_color_commit_noarm(new_crtc_state); 1425 intel_color_commit_arm(new_crtc_state); 1426 /* update DSPCNTR to configure gamma for pipe bottom color */ 1427 intel_disable_primary_plane(new_crtc_state); 1428 1429 intel_initial_watermarks(state, crtc); 1430 intel_enable_transcoder(new_crtc_state); 1431 1432 if (new_crtc_state->has_pch_encoder) 1433 ilk_pch_enable(state, crtc); 1434 1435 intel_crtc_vblank_on(new_crtc_state); 1436 1437 intel_encoders_enable(state, crtc); 1438 1439 if (HAS_PCH_CPT(dev_priv)) 1440 intel_wait_for_pipe_scanline_moving(crtc); 1441 1442 /* 1443 * Must wait for vblank to avoid spurious PCH FIFO underruns. 1444 * And a second vblank wait is needed at least on ILK with 1445 * some interlaced HDMI modes. Let's do the double wait always 1446 * in case there are more corner cases we don't know about. 1447 */ 1448 if (new_crtc_state->has_pch_encoder) { 1449 intel_crtc_wait_for_next_vblank(crtc); 1450 intel_crtc_wait_for_next_vblank(crtc); 1451 } 1452 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1453 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 1454 } 1455 1456 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, 1457 enum pipe pipe, bool apply) 1458 { 1459 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)); 1460 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS; 1461 1462 if (apply) 1463 val |= mask; 1464 else 1465 val &= ~mask; 1466 1467 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val); 1468 } 1469 1470 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state) 1471 { 1472 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1473 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1474 1475 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe), 1476 HSW_LINETIME(crtc_state->linetime) | 1477 HSW_IPS_LINETIME(crtc_state->ips_linetime)); 1478 } 1479 1480 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) 1481 { 1482 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1483 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1484 enum transcoder transcoder = crtc_state->cpu_transcoder; 1485 i915_reg_t reg = DISPLAY_VER(dev_priv) >= 14 ? MTL_CHICKEN_TRANS(transcoder) : 1486 CHICKEN_TRANS(transcoder); 1487 1488 intel_de_rmw(dev_priv, reg, 1489 HSW_FRAME_START_DELAY_MASK, 1490 HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1)); 1491 } 1492 1493 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state, 1494 const struct intel_crtc_state *crtc_state) 1495 { 1496 struct intel_crtc *master_crtc = intel_master_crtc(crtc_state); 1497 1498 /* 1499 * Enable sequence steps 1-7 on bigjoiner master 1500 */ 1501 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1502 intel_encoders_pre_pll_enable(state, master_crtc); 1503 1504 if (crtc_state->shared_dpll) 1505 intel_enable_shared_dpll(crtc_state); 1506 1507 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1508 intel_encoders_pre_enable(state, master_crtc); 1509 } 1510 1511 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1512 { 1513 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1514 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1515 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1516 1517 if (crtc_state->has_pch_encoder) { 1518 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1519 &crtc_state->fdi_m_n); 1520 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1521 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1522 &crtc_state->dp_m_n); 1523 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1524 &crtc_state->dp_m2_n2); 1525 } 1526 1527 intel_set_transcoder_timings(crtc_state); 1528 if (HAS_VRR(dev_priv)) 1529 intel_vrr_set_transcoder_timings(crtc_state); 1530 1531 if (cpu_transcoder != TRANSCODER_EDP) 1532 intel_de_write(dev_priv, TRANS_MULT(cpu_transcoder), 1533 crtc_state->pixel_multiplier - 1); 1534 1535 hsw_set_frame_start_delay(crtc_state); 1536 1537 hsw_set_transconf(crtc_state); 1538 } 1539 1540 static void hsw_crtc_enable(struct intel_atomic_state *state, 1541 struct intel_crtc *crtc) 1542 { 1543 const struct intel_crtc_state *new_crtc_state = 1544 intel_atomic_get_new_crtc_state(state, crtc); 1545 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1546 enum pipe pipe = crtc->pipe, hsw_workaround_pipe; 1547 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 1548 bool psl_clkgate_wa; 1549 1550 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1551 return; 1552 1553 intel_dmc_enable_pipe(dev_priv, crtc->pipe); 1554 1555 if (!new_crtc_state->bigjoiner_pipes) { 1556 intel_encoders_pre_pll_enable(state, crtc); 1557 1558 if (new_crtc_state->shared_dpll) 1559 intel_enable_shared_dpll(new_crtc_state); 1560 1561 intel_encoders_pre_enable(state, crtc); 1562 } else { 1563 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state); 1564 } 1565 1566 intel_dsc_enable(new_crtc_state); 1567 1568 if (DISPLAY_VER(dev_priv) >= 13) 1569 intel_uncompressed_joiner_enable(new_crtc_state); 1570 1571 intel_set_pipe_src_size(new_crtc_state); 1572 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 1573 bdw_set_pipe_misc(new_crtc_state); 1574 1575 if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) && 1576 !transcoder_is_dsi(cpu_transcoder)) 1577 hsw_configure_cpu_transcoder(new_crtc_state); 1578 1579 crtc->active = true; 1580 1581 /* Display WA #1180: WaDisableScalarClockGating: glk */ 1582 psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 && 1583 new_crtc_state->pch_pfit.enabled; 1584 if (psl_clkgate_wa) 1585 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true); 1586 1587 if (DISPLAY_VER(dev_priv) >= 9) 1588 skl_pfit_enable(new_crtc_state); 1589 else 1590 ilk_pfit_enable(new_crtc_state); 1591 1592 /* 1593 * On ILK+ LUT must be loaded before the pipe is running but with 1594 * clocks enabled 1595 */ 1596 intel_color_load_luts(new_crtc_state); 1597 intel_color_commit_noarm(new_crtc_state); 1598 intel_color_commit_arm(new_crtc_state); 1599 /* update DSPCNTR to configure gamma/csc for pipe bottom color */ 1600 if (DISPLAY_VER(dev_priv) < 9) 1601 intel_disable_primary_plane(new_crtc_state); 1602 1603 hsw_set_linetime_wm(new_crtc_state); 1604 1605 if (DISPLAY_VER(dev_priv) >= 11) 1606 icl_set_pipe_chicken(new_crtc_state); 1607 1608 intel_initial_watermarks(state, crtc); 1609 1610 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 1611 intel_crtc_vblank_on(new_crtc_state); 1612 1613 intel_encoders_enable(state, crtc); 1614 1615 if (psl_clkgate_wa) { 1616 intel_crtc_wait_for_next_vblank(crtc); 1617 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false); 1618 } 1619 1620 /* If we change the relative order between pipe/planes enabling, we need 1621 * to change the workaround. */ 1622 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe; 1623 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { 1624 struct intel_crtc *wa_crtc; 1625 1626 wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe); 1627 1628 intel_crtc_wait_for_next_vblank(wa_crtc); 1629 intel_crtc_wait_for_next_vblank(wa_crtc); 1630 } 1631 } 1632 1633 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state) 1634 { 1635 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1636 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1637 enum pipe pipe = crtc->pipe; 1638 1639 /* To avoid upsetting the power well on haswell only disable the pfit if 1640 * it's in use. The hw state code will make sure we get this right. */ 1641 if (!old_crtc_state->pch_pfit.enabled) 1642 return; 1643 1644 intel_de_write_fw(dev_priv, PF_CTL(pipe), 0); 1645 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0); 1646 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0); 1647 } 1648 1649 static void ilk_crtc_disable(struct intel_atomic_state *state, 1650 struct intel_crtc *crtc) 1651 { 1652 const struct intel_crtc_state *old_crtc_state = 1653 intel_atomic_get_old_crtc_state(state, crtc); 1654 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1655 enum pipe pipe = crtc->pipe; 1656 1657 /* 1658 * Sometimes spurious CPU pipe underruns happen when the 1659 * pipe is already disabled, but FDI RX/TX is still enabled. 1660 * Happens at least with VGA+HDMI cloning. Suppress them. 1661 */ 1662 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1663 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 1664 1665 intel_encoders_disable(state, crtc); 1666 1667 intel_crtc_vblank_off(old_crtc_state); 1668 1669 intel_disable_transcoder(old_crtc_state); 1670 1671 ilk_pfit_disable(old_crtc_state); 1672 1673 if (old_crtc_state->has_pch_encoder) 1674 ilk_pch_disable(state, crtc); 1675 1676 intel_encoders_post_disable(state, crtc); 1677 1678 if (old_crtc_state->has_pch_encoder) 1679 ilk_pch_post_disable(state, crtc); 1680 1681 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1682 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 1683 1684 intel_disable_shared_dpll(old_crtc_state); 1685 } 1686 1687 static void hsw_crtc_disable(struct intel_atomic_state *state, 1688 struct intel_crtc *crtc) 1689 { 1690 const struct intel_crtc_state *old_crtc_state = 1691 intel_atomic_get_old_crtc_state(state, crtc); 1692 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 1693 1694 /* 1695 * FIXME collapse everything to one hook. 1696 * Need care with mst->ddi interactions. 1697 */ 1698 if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) { 1699 intel_encoders_disable(state, crtc); 1700 intel_encoders_post_disable(state, crtc); 1701 } 1702 1703 intel_disable_shared_dpll(old_crtc_state); 1704 1705 intel_encoders_post_pll_disable(state, crtc); 1706 1707 intel_dmc_disable_pipe(i915, crtc->pipe); 1708 } 1709 1710 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) 1711 { 1712 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1713 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1714 1715 if (!crtc_state->gmch_pfit.control) 1716 return; 1717 1718 /* 1719 * The panel fitter should only be adjusted whilst the pipe is disabled, 1720 * according to register description and PRM. 1721 */ 1722 drm_WARN_ON(&dev_priv->drm, 1723 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE); 1724 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 1725 1726 intel_de_write(dev_priv, PFIT_PGM_RATIOS, 1727 crtc_state->gmch_pfit.pgm_ratios); 1728 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control); 1729 1730 /* Border color in case we don't scale up to the full screen. Black by 1731 * default, change to something else for debugging. */ 1732 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); 1733 } 1734 1735 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) 1736 { 1737 if (phy == PHY_NONE) 1738 return false; 1739 else if (IS_ALDERLAKE_S(dev_priv)) 1740 return phy <= PHY_E; 1741 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) 1742 return phy <= PHY_D; 1743 else if (IS_JSL_EHL(dev_priv)) 1744 return phy <= PHY_C; 1745 else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12)) 1746 return phy <= PHY_B; 1747 else 1748 /* 1749 * DG2 outputs labelled as "combo PHY" in the bspec use 1750 * SNPS PHYs with completely different programming, 1751 * hence we always return false here. 1752 */ 1753 return false; 1754 } 1755 1756 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) 1757 { 1758 if (IS_DG2(dev_priv)) 1759 /* DG2's "TC1" output uses a SNPS PHY */ 1760 return false; 1761 else if (IS_ALDERLAKE_P(dev_priv) || IS_METEORLAKE(dev_priv)) 1762 return phy >= PHY_F && phy <= PHY_I; 1763 else if (IS_TIGERLAKE(dev_priv)) 1764 return phy >= PHY_D && phy <= PHY_I; 1765 else if (IS_ICELAKE(dev_priv)) 1766 return phy >= PHY_C && phy <= PHY_F; 1767 else 1768 return false; 1769 } 1770 1771 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy) 1772 { 1773 if (phy == PHY_NONE) 1774 return false; 1775 else if (IS_DG2(dev_priv)) 1776 /* 1777 * All four "combo" ports and the TC1 port (PHY E) use 1778 * Synopsis PHYs. 1779 */ 1780 return phy <= PHY_E; 1781 1782 return false; 1783 } 1784 1785 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) 1786 { 1787 if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD) 1788 return PHY_D + port - PORT_D_XELPD; 1789 else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1) 1790 return PHY_F + port - PORT_TC1; 1791 else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1) 1792 return PHY_B + port - PORT_TC1; 1793 else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1) 1794 return PHY_C + port - PORT_TC1; 1795 else if (IS_JSL_EHL(i915) && port == PORT_D) 1796 return PHY_A; 1797 1798 return PHY_A + port - PORT_A; 1799 } 1800 1801 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) 1802 { 1803 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port))) 1804 return TC_PORT_NONE; 1805 1806 if (DISPLAY_VER(dev_priv) >= 12) 1807 return TC_PORT_1 + port - PORT_TC1; 1808 else 1809 return TC_PORT_1 + port - PORT_C; 1810 } 1811 1812 enum intel_display_power_domain 1813 intel_aux_power_domain(struct intel_digital_port *dig_port) 1814 { 1815 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1816 1817 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 1818 return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch); 1819 1820 return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch); 1821 } 1822 1823 static void get_crtc_power_domains(struct intel_crtc_state *crtc_state, 1824 struct intel_power_domain_mask *mask) 1825 { 1826 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1827 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1828 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1829 struct drm_encoder *encoder; 1830 enum pipe pipe = crtc->pipe; 1831 1832 bitmap_zero(mask->bits, POWER_DOMAIN_NUM); 1833 1834 if (!crtc_state->hw.active) 1835 return; 1836 1837 set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits); 1838 set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits); 1839 if (crtc_state->pch_pfit.enabled || 1840 crtc_state->pch_pfit.force_thru) 1841 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits); 1842 1843 drm_for_each_encoder_mask(encoder, &dev_priv->drm, 1844 crtc_state->uapi.encoder_mask) { 1845 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 1846 1847 set_bit(intel_encoder->power_domain, mask->bits); 1848 } 1849 1850 if (HAS_DDI(dev_priv) && crtc_state->has_audio) 1851 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits); 1852 1853 if (crtc_state->shared_dpll) 1854 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits); 1855 1856 if (crtc_state->dsc.compression_enable) 1857 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits); 1858 } 1859 1860 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, 1861 struct intel_power_domain_mask *old_domains) 1862 { 1863 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1864 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1865 enum intel_display_power_domain domain; 1866 struct intel_power_domain_mask domains, new_domains; 1867 1868 get_crtc_power_domains(crtc_state, &domains); 1869 1870 bitmap_andnot(new_domains.bits, 1871 domains.bits, 1872 crtc->enabled_power_domains.mask.bits, 1873 POWER_DOMAIN_NUM); 1874 bitmap_andnot(old_domains->bits, 1875 crtc->enabled_power_domains.mask.bits, 1876 domains.bits, 1877 POWER_DOMAIN_NUM); 1878 1879 for_each_power_domain(domain, &new_domains) 1880 intel_display_power_get_in_set(dev_priv, 1881 &crtc->enabled_power_domains, 1882 domain); 1883 } 1884 1885 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc, 1886 struct intel_power_domain_mask *domains) 1887 { 1888 intel_display_power_put_mask_in_set(to_i915(crtc->base.dev), 1889 &crtc->enabled_power_domains, 1890 domains); 1891 } 1892 1893 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1894 { 1895 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1896 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1897 1898 if (intel_crtc_has_dp_encoder(crtc_state)) { 1899 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1900 &crtc_state->dp_m_n); 1901 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1902 &crtc_state->dp_m2_n2); 1903 } 1904 1905 intel_set_transcoder_timings(crtc_state); 1906 1907 i9xx_set_pipeconf(crtc_state); 1908 } 1909 1910 static void valleyview_crtc_enable(struct intel_atomic_state *state, 1911 struct intel_crtc *crtc) 1912 { 1913 const struct intel_crtc_state *new_crtc_state = 1914 intel_atomic_get_new_crtc_state(state, crtc); 1915 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1916 enum pipe pipe = crtc->pipe; 1917 1918 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1919 return; 1920 1921 i9xx_configure_cpu_transcoder(new_crtc_state); 1922 1923 intel_set_pipe_src_size(new_crtc_state); 1924 1925 intel_de_write(dev_priv, VLV_PIPE_MSA_MISC(pipe), 0); 1926 1927 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 1928 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY); 1929 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0); 1930 } 1931 1932 crtc->active = true; 1933 1934 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1935 1936 intel_encoders_pre_pll_enable(state, crtc); 1937 1938 if (IS_CHERRYVIEW(dev_priv)) 1939 chv_enable_pll(new_crtc_state); 1940 else 1941 vlv_enable_pll(new_crtc_state); 1942 1943 intel_encoders_pre_enable(state, crtc); 1944 1945 i9xx_pfit_enable(new_crtc_state); 1946 1947 intel_color_load_luts(new_crtc_state); 1948 intel_color_commit_noarm(new_crtc_state); 1949 intel_color_commit_arm(new_crtc_state); 1950 /* update DSPCNTR to configure gamma for pipe bottom color */ 1951 intel_disable_primary_plane(new_crtc_state); 1952 1953 intel_initial_watermarks(state, crtc); 1954 intel_enable_transcoder(new_crtc_state); 1955 1956 intel_crtc_vblank_on(new_crtc_state); 1957 1958 intel_encoders_enable(state, crtc); 1959 } 1960 1961 static void i9xx_crtc_enable(struct intel_atomic_state *state, 1962 struct intel_crtc *crtc) 1963 { 1964 const struct intel_crtc_state *new_crtc_state = 1965 intel_atomic_get_new_crtc_state(state, crtc); 1966 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1967 enum pipe pipe = crtc->pipe; 1968 1969 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1970 return; 1971 1972 i9xx_configure_cpu_transcoder(new_crtc_state); 1973 1974 intel_set_pipe_src_size(new_crtc_state); 1975 1976 crtc->active = true; 1977 1978 if (DISPLAY_VER(dev_priv) != 2) 1979 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1980 1981 intel_encoders_pre_enable(state, crtc); 1982 1983 i9xx_enable_pll(new_crtc_state); 1984 1985 i9xx_pfit_enable(new_crtc_state); 1986 1987 intel_color_load_luts(new_crtc_state); 1988 intel_color_commit_noarm(new_crtc_state); 1989 intel_color_commit_arm(new_crtc_state); 1990 /* update DSPCNTR to configure gamma for pipe bottom color */ 1991 intel_disable_primary_plane(new_crtc_state); 1992 1993 if (!intel_initial_watermarks(state, crtc)) 1994 intel_update_watermarks(dev_priv); 1995 intel_enable_transcoder(new_crtc_state); 1996 1997 intel_crtc_vblank_on(new_crtc_state); 1998 1999 intel_encoders_enable(state, crtc); 2000 2001 /* prevents spurious underruns */ 2002 if (DISPLAY_VER(dev_priv) == 2) 2003 intel_crtc_wait_for_next_vblank(crtc); 2004 } 2005 2006 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) 2007 { 2008 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 2009 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2010 2011 if (!old_crtc_state->gmch_pfit.control) 2012 return; 2013 2014 assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder); 2015 2016 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n", 2017 intel_de_read(dev_priv, PFIT_CONTROL)); 2018 intel_de_write(dev_priv, PFIT_CONTROL, 0); 2019 } 2020 2021 static void i9xx_crtc_disable(struct intel_atomic_state *state, 2022 struct intel_crtc *crtc) 2023 { 2024 struct intel_crtc_state *old_crtc_state = 2025 intel_atomic_get_old_crtc_state(state, crtc); 2026 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2027 enum pipe pipe = crtc->pipe; 2028 2029 /* 2030 * On gen2 planes are double buffered but the pipe isn't, so we must 2031 * wait for planes to fully turn off before disabling the pipe. 2032 */ 2033 if (DISPLAY_VER(dev_priv) == 2) 2034 intel_crtc_wait_for_next_vblank(crtc); 2035 2036 intel_encoders_disable(state, crtc); 2037 2038 intel_crtc_vblank_off(old_crtc_state); 2039 2040 intel_disable_transcoder(old_crtc_state); 2041 2042 i9xx_pfit_disable(old_crtc_state); 2043 2044 intel_encoders_post_disable(state, crtc); 2045 2046 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) { 2047 if (IS_CHERRYVIEW(dev_priv)) 2048 chv_disable_pll(dev_priv, pipe); 2049 else if (IS_VALLEYVIEW(dev_priv)) 2050 vlv_disable_pll(dev_priv, pipe); 2051 else 2052 i9xx_disable_pll(old_crtc_state); 2053 } 2054 2055 intel_encoders_post_pll_disable(state, crtc); 2056 2057 if (DISPLAY_VER(dev_priv) != 2) 2058 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 2059 2060 if (!dev_priv->display.funcs.wm->initial_watermarks) 2061 intel_update_watermarks(dev_priv); 2062 2063 /* clock the pipe down to 640x480@60 to potentially save power */ 2064 if (IS_I830(dev_priv)) 2065 i830_enable_pipe(dev_priv, pipe); 2066 } 2067 2068 void intel_encoder_destroy(struct drm_encoder *encoder) 2069 { 2070 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2071 2072 drm_encoder_cleanup(encoder); 2073 kfree(intel_encoder); 2074 } 2075 2076 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) 2077 { 2078 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2079 2080 /* GDG double wide on either pipe, otherwise pipe A only */ 2081 return DISPLAY_VER(dev_priv) < 4 && 2082 (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); 2083 } 2084 2085 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) 2086 { 2087 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock; 2088 struct drm_rect src; 2089 2090 /* 2091 * We only use IF-ID interlacing. If we ever use 2092 * PF-ID we'll need to adjust the pixel_rate here. 2093 */ 2094 2095 if (!crtc_state->pch_pfit.enabled) 2096 return pixel_rate; 2097 2098 drm_rect_init(&src, 0, 0, 2099 drm_rect_width(&crtc_state->pipe_src) << 16, 2100 drm_rect_height(&crtc_state->pipe_src) << 16); 2101 2102 return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst, 2103 pixel_rate); 2104 } 2105 2106 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode, 2107 const struct drm_display_mode *timings) 2108 { 2109 mode->hdisplay = timings->crtc_hdisplay; 2110 mode->htotal = timings->crtc_htotal; 2111 mode->hsync_start = timings->crtc_hsync_start; 2112 mode->hsync_end = timings->crtc_hsync_end; 2113 2114 mode->vdisplay = timings->crtc_vdisplay; 2115 mode->vtotal = timings->crtc_vtotal; 2116 mode->vsync_start = timings->crtc_vsync_start; 2117 mode->vsync_end = timings->crtc_vsync_end; 2118 2119 mode->flags = timings->flags; 2120 mode->type = DRM_MODE_TYPE_DRIVER; 2121 2122 mode->clock = timings->crtc_clock; 2123 2124 drm_mode_set_name(mode); 2125 } 2126 2127 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) 2128 { 2129 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2130 2131 if (HAS_GMCH(dev_priv)) 2132 /* FIXME calculate proper pipe pixel rate for GMCH pfit */ 2133 crtc_state->pixel_rate = 2134 crtc_state->hw.pipe_mode.crtc_clock; 2135 else 2136 crtc_state->pixel_rate = 2137 ilk_pipe_pixel_rate(crtc_state); 2138 } 2139 2140 static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state *crtc_state, 2141 struct drm_display_mode *mode) 2142 { 2143 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2144 2145 if (num_pipes < 2) 2146 return; 2147 2148 mode->crtc_clock /= num_pipes; 2149 mode->crtc_hdisplay /= num_pipes; 2150 mode->crtc_hblank_start /= num_pipes; 2151 mode->crtc_hblank_end /= num_pipes; 2152 mode->crtc_hsync_start /= num_pipes; 2153 mode->crtc_hsync_end /= num_pipes; 2154 mode->crtc_htotal /= num_pipes; 2155 } 2156 2157 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state, 2158 struct drm_display_mode *mode) 2159 { 2160 int overlap = crtc_state->splitter.pixel_overlap; 2161 int n = crtc_state->splitter.link_count; 2162 2163 if (!crtc_state->splitter.enable) 2164 return; 2165 2166 /* 2167 * eDP MSO uses segment timings from EDID for transcoder 2168 * timings, but full mode for everything else. 2169 * 2170 * h_full = (h_segment - pixel_overlap) * link_count 2171 */ 2172 mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n; 2173 mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n; 2174 mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n; 2175 mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n; 2176 mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n; 2177 mode->crtc_htotal = (mode->crtc_htotal - overlap) * n; 2178 mode->crtc_clock *= n; 2179 } 2180 2181 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state) 2182 { 2183 struct drm_display_mode *mode = &crtc_state->hw.mode; 2184 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2185 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2186 2187 /* 2188 * Start with the adjusted_mode crtc timings, which 2189 * have been filled with the transcoder timings. 2190 */ 2191 drm_mode_copy(pipe_mode, adjusted_mode); 2192 2193 /* Expand MSO per-segment transcoder timings to full */ 2194 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2195 2196 /* 2197 * We want the full numbers in adjusted_mode normal timings, 2198 * adjusted_mode crtc timings are left with the raw transcoder 2199 * timings. 2200 */ 2201 intel_mode_from_crtc_timings(adjusted_mode, pipe_mode); 2202 2203 /* Populate the "user" mode with full numbers */ 2204 drm_mode_copy(mode, pipe_mode); 2205 intel_mode_from_crtc_timings(mode, mode); 2206 mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) * 2207 (intel_bigjoiner_num_pipes(crtc_state) ?: 1); 2208 mode->vdisplay = drm_rect_height(&crtc_state->pipe_src); 2209 2210 /* Derive per-pipe timings in case bigjoiner is used */ 2211 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2212 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2213 2214 intel_crtc_compute_pixel_rate(crtc_state); 2215 } 2216 2217 void intel_encoder_get_config(struct intel_encoder *encoder, 2218 struct intel_crtc_state *crtc_state) 2219 { 2220 encoder->get_config(encoder, crtc_state); 2221 2222 intel_crtc_readout_derived_state(crtc_state); 2223 } 2224 2225 static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state *crtc_state) 2226 { 2227 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2228 int width, height; 2229 2230 if (num_pipes < 2) 2231 return; 2232 2233 width = drm_rect_width(&crtc_state->pipe_src); 2234 height = drm_rect_height(&crtc_state->pipe_src); 2235 2236 drm_rect_init(&crtc_state->pipe_src, 0, 0, 2237 width / num_pipes, height); 2238 } 2239 2240 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state) 2241 { 2242 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2243 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2244 2245 intel_bigjoiner_compute_pipe_src(crtc_state); 2246 2247 /* 2248 * Pipe horizontal size must be even in: 2249 * - DVO ganged mode 2250 * - LVDS dual channel mode 2251 * - Double wide pipe 2252 */ 2253 if (drm_rect_width(&crtc_state->pipe_src) & 1) { 2254 if (crtc_state->double_wide) { 2255 drm_dbg_kms(&i915->drm, 2256 "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n", 2257 crtc->base.base.id, crtc->base.name); 2258 return -EINVAL; 2259 } 2260 2261 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 2262 intel_is_dual_link_lvds(i915)) { 2263 drm_dbg_kms(&i915->drm, 2264 "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n", 2265 crtc->base.base.id, crtc->base.name); 2266 return -EINVAL; 2267 } 2268 } 2269 2270 return 0; 2271 } 2272 2273 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state) 2274 { 2275 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2276 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2277 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2278 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2279 int clock_limit = i915->max_dotclk_freq; 2280 2281 /* 2282 * Start with the adjusted_mode crtc timings, which 2283 * have been filled with the transcoder timings. 2284 */ 2285 drm_mode_copy(pipe_mode, adjusted_mode); 2286 2287 /* Expand MSO per-segment transcoder timings to full */ 2288 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2289 2290 /* Derive per-pipe timings in case bigjoiner is used */ 2291 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2292 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2293 2294 if (DISPLAY_VER(i915) < 4) { 2295 clock_limit = i915->display.cdclk.max_cdclk_freq * 9 / 10; 2296 2297 /* 2298 * Enable double wide mode when the dot clock 2299 * is > 90% of the (display) core speed. 2300 */ 2301 if (intel_crtc_supports_double_wide(crtc) && 2302 pipe_mode->crtc_clock > clock_limit) { 2303 clock_limit = i915->max_dotclk_freq; 2304 crtc_state->double_wide = true; 2305 } 2306 } 2307 2308 if (pipe_mode->crtc_clock > clock_limit) { 2309 drm_dbg_kms(&i915->drm, 2310 "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", 2311 crtc->base.base.id, crtc->base.name, 2312 pipe_mode->crtc_clock, clock_limit, 2313 str_yes_no(crtc_state->double_wide)); 2314 return -EINVAL; 2315 } 2316 2317 return 0; 2318 } 2319 2320 static int intel_crtc_compute_config(struct intel_atomic_state *state, 2321 struct intel_crtc *crtc) 2322 { 2323 struct intel_crtc_state *crtc_state = 2324 intel_atomic_get_new_crtc_state(state, crtc); 2325 int ret; 2326 2327 ret = intel_dpll_crtc_compute_clock(state, crtc); 2328 if (ret) 2329 return ret; 2330 2331 ret = intel_crtc_compute_pipe_src(crtc_state); 2332 if (ret) 2333 return ret; 2334 2335 ret = intel_crtc_compute_pipe_mode(crtc_state); 2336 if (ret) 2337 return ret; 2338 2339 intel_crtc_compute_pixel_rate(crtc_state); 2340 2341 if (crtc_state->has_pch_encoder) 2342 return ilk_fdi_compute_config(crtc, crtc_state); 2343 2344 return 0; 2345 } 2346 2347 static void 2348 intel_reduce_m_n_ratio(u32 *num, u32 *den) 2349 { 2350 while (*num > DATA_LINK_M_N_MASK || 2351 *den > DATA_LINK_M_N_MASK) { 2352 *num >>= 1; 2353 *den >>= 1; 2354 } 2355 } 2356 2357 static void compute_m_n(u32 *ret_m, u32 *ret_n, 2358 u32 m, u32 n, u32 constant_n) 2359 { 2360 if (constant_n) 2361 *ret_n = constant_n; 2362 else 2363 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); 2364 2365 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n); 2366 intel_reduce_m_n_ratio(ret_m, ret_n); 2367 } 2368 2369 void 2370 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes, 2371 int pixel_clock, int link_clock, 2372 struct intel_link_m_n *m_n, 2373 bool fec_enable) 2374 { 2375 u32 data_clock = bits_per_pixel * pixel_clock; 2376 2377 if (fec_enable) 2378 data_clock = intel_dp_mode_to_fec_clock(data_clock); 2379 2380 /* 2381 * Windows/BIOS uses fixed M/N values always. Follow suit. 2382 * 2383 * Also several DP dongles in particular seem to be fussy 2384 * about too large link M/N values. Presumably the 20bit 2385 * value used by Windows/BIOS is acceptable to everyone. 2386 */ 2387 m_n->tu = 64; 2388 compute_m_n(&m_n->data_m, &m_n->data_n, 2389 data_clock, link_clock * nlanes * 8, 2390 0x8000000); 2391 2392 compute_m_n(&m_n->link_m, &m_n->link_n, 2393 pixel_clock, link_clock, 2394 0x80000); 2395 } 2396 2397 void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv) 2398 { 2399 /* 2400 * There may be no VBT; and if the BIOS enabled SSC we can 2401 * just keep using it to avoid unnecessary flicker. Whereas if the 2402 * BIOS isn't using it, don't assume it will work even if the VBT 2403 * indicates as much. 2404 */ 2405 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { 2406 bool bios_lvds_use_ssc = intel_de_read(dev_priv, 2407 PCH_DREF_CONTROL) & 2408 DREF_SSC1_ENABLE; 2409 2410 if (dev_priv->display.vbt.lvds_use_ssc != bios_lvds_use_ssc) { 2411 drm_dbg_kms(&dev_priv->drm, 2412 "SSC %s by BIOS, overriding VBT which says %s\n", 2413 str_enabled_disabled(bios_lvds_use_ssc), 2414 str_enabled_disabled(dev_priv->display.vbt.lvds_use_ssc)); 2415 dev_priv->display.vbt.lvds_use_ssc = bios_lvds_use_ssc; 2416 } 2417 } 2418 } 2419 2420 void intel_zero_m_n(struct intel_link_m_n *m_n) 2421 { 2422 /* corresponds to 0 register value */ 2423 memset(m_n, 0, sizeof(*m_n)); 2424 m_n->tu = 1; 2425 } 2426 2427 void intel_set_m_n(struct drm_i915_private *i915, 2428 const struct intel_link_m_n *m_n, 2429 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 2430 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 2431 { 2432 intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); 2433 intel_de_write(i915, data_n_reg, m_n->data_n); 2434 intel_de_write(i915, link_m_reg, m_n->link_m); 2435 /* 2436 * On BDW+ writing LINK_N arms the double buffered update 2437 * of all the M/N registers, so it must be written last. 2438 */ 2439 intel_de_write(i915, link_n_reg, m_n->link_n); 2440 } 2441 2442 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, 2443 enum transcoder transcoder) 2444 { 2445 if (IS_HASWELL(dev_priv)) 2446 return transcoder == TRANSCODER_EDP; 2447 2448 return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv); 2449 } 2450 2451 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, 2452 enum transcoder transcoder, 2453 const struct intel_link_m_n *m_n) 2454 { 2455 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2456 enum pipe pipe = crtc->pipe; 2457 2458 if (DISPLAY_VER(dev_priv) >= 5) 2459 intel_set_m_n(dev_priv, m_n, 2460 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 2461 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 2462 else 2463 intel_set_m_n(dev_priv, m_n, 2464 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 2465 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 2466 } 2467 2468 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, 2469 enum transcoder transcoder, 2470 const struct intel_link_m_n *m_n) 2471 { 2472 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2473 2474 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 2475 return; 2476 2477 intel_set_m_n(dev_priv, m_n, 2478 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 2479 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 2480 } 2481 2482 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) 2483 { 2484 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2485 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2486 enum pipe pipe = crtc->pipe; 2487 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2488 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2489 u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end; 2490 int vsyncshift = 0; 2491 2492 /* We need to be careful not to changed the adjusted mode, for otherwise 2493 * the hw state checker will get angry at the mismatch. */ 2494 crtc_vdisplay = adjusted_mode->crtc_vdisplay; 2495 crtc_vtotal = adjusted_mode->crtc_vtotal; 2496 crtc_vblank_start = adjusted_mode->crtc_vblank_start; 2497 crtc_vblank_end = adjusted_mode->crtc_vblank_end; 2498 2499 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 2500 /* the chip adds 2 halflines automatically */ 2501 crtc_vtotal -= 1; 2502 crtc_vblank_end -= 1; 2503 2504 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 2505 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; 2506 else 2507 vsyncshift = adjusted_mode->crtc_hsync_start - 2508 adjusted_mode->crtc_htotal / 2; 2509 if (vsyncshift < 0) 2510 vsyncshift += adjusted_mode->crtc_htotal; 2511 } 2512 2513 /* 2514 * VBLANK_START no longer works on ADL+, instead we must use 2515 * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start. 2516 */ 2517 if (DISPLAY_VER(dev_priv) >= 13) { 2518 intel_de_write(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder), 2519 crtc_vblank_start - crtc_vdisplay); 2520 2521 /* 2522 * VBLANK_START not used by hw, just clear it 2523 * to make it stand out in register dumps. 2524 */ 2525 crtc_vblank_start = 1; 2526 } 2527 2528 if (DISPLAY_VER(dev_priv) > 3) 2529 intel_de_write(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder), 2530 vsyncshift); 2531 2532 intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder), 2533 HACTIVE(adjusted_mode->crtc_hdisplay - 1) | 2534 HTOTAL(adjusted_mode->crtc_htotal - 1)); 2535 intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder), 2536 HBLANK_START(adjusted_mode->crtc_hblank_start - 1) | 2537 HBLANK_END(adjusted_mode->crtc_hblank_end - 1)); 2538 intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder), 2539 HSYNC_START(adjusted_mode->crtc_hsync_start - 1) | 2540 HSYNC_END(adjusted_mode->crtc_hsync_end - 1)); 2541 2542 intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder), 2543 VACTIVE(crtc_vdisplay - 1) | 2544 VTOTAL(crtc_vtotal - 1)); 2545 intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), 2546 VBLANK_START(crtc_vblank_start - 1) | 2547 VBLANK_END(crtc_vblank_end - 1)); 2548 intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder), 2549 VSYNC_START(adjusted_mode->crtc_vsync_start - 1) | 2550 VSYNC_END(adjusted_mode->crtc_vsync_end - 1)); 2551 2552 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be 2553 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is 2554 * documented on the DDI_FUNC_CTL register description, EDP Input Select 2555 * bits. */ 2556 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && 2557 (pipe == PIPE_B || pipe == PIPE_C)) 2558 intel_de_write(dev_priv, TRANS_VTOTAL(pipe), 2559 VACTIVE(crtc_vdisplay - 1) | 2560 VTOTAL(crtc_vtotal - 1)); 2561 } 2562 2563 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) 2564 { 2565 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2566 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2567 int width = drm_rect_width(&crtc_state->pipe_src); 2568 int height = drm_rect_height(&crtc_state->pipe_src); 2569 enum pipe pipe = crtc->pipe; 2570 2571 /* pipesrc controls the size that is scaled from, which should 2572 * always be the user's requested size. 2573 */ 2574 intel_de_write(dev_priv, PIPESRC(pipe), 2575 PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1)); 2576 } 2577 2578 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) 2579 { 2580 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2581 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2582 2583 if (DISPLAY_VER(dev_priv) == 2) 2584 return false; 2585 2586 if (DISPLAY_VER(dev_priv) >= 9 || 2587 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2588 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW; 2589 else 2590 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK; 2591 } 2592 2593 static void intel_get_transcoder_timings(struct intel_crtc *crtc, 2594 struct intel_crtc_state *pipe_config) 2595 { 2596 struct drm_device *dev = crtc->base.dev; 2597 struct drm_i915_private *dev_priv = to_i915(dev); 2598 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 2599 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2600 u32 tmp; 2601 2602 tmp = intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder)); 2603 adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1; 2604 adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1; 2605 2606 if (!transcoder_is_dsi(cpu_transcoder)) { 2607 tmp = intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder)); 2608 adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1; 2609 adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1; 2610 } 2611 2612 tmp = intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder)); 2613 adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1; 2614 adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1; 2615 2616 tmp = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder)); 2617 adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1; 2618 adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1; 2619 2620 /* FIXME TGL+ DSI transcoders have this! */ 2621 if (!transcoder_is_dsi(cpu_transcoder)) { 2622 tmp = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder)); 2623 adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1; 2624 adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1; 2625 } 2626 tmp = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder)); 2627 adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1; 2628 adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1; 2629 2630 if (intel_pipe_is_interlaced(pipe_config)) { 2631 adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE; 2632 adjusted_mode->crtc_vtotal += 1; 2633 adjusted_mode->crtc_vblank_end += 1; 2634 } 2635 2636 if (DISPLAY_VER(dev_priv) >= 13 && !transcoder_is_dsi(cpu_transcoder)) 2637 adjusted_mode->crtc_vblank_start = 2638 adjusted_mode->crtc_vdisplay + 2639 intel_de_read(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder)); 2640 } 2641 2642 static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state) 2643 { 2644 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2645 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2646 enum pipe master_pipe, pipe = crtc->pipe; 2647 int width; 2648 2649 if (num_pipes < 2) 2650 return; 2651 2652 master_pipe = bigjoiner_master_pipe(crtc_state); 2653 width = drm_rect_width(&crtc_state->pipe_src); 2654 2655 drm_rect_translate_to(&crtc_state->pipe_src, 2656 (pipe - master_pipe) * width, 0); 2657 } 2658 2659 static void intel_get_pipe_src_size(struct intel_crtc *crtc, 2660 struct intel_crtc_state *pipe_config) 2661 { 2662 struct drm_device *dev = crtc->base.dev; 2663 struct drm_i915_private *dev_priv = to_i915(dev); 2664 u32 tmp; 2665 2666 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe)); 2667 2668 drm_rect_init(&pipe_config->pipe_src, 0, 0, 2669 REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1, 2670 REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1); 2671 2672 intel_bigjoiner_adjust_pipe_src(pipe_config); 2673 } 2674 2675 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) 2676 { 2677 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2678 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2679 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2680 u32 val = 0; 2681 2682 /* 2683 * - We keep both pipes enabled on 830 2684 * - During modeset the pipe is still disabled and must remain so 2685 * - During fastset the pipe is already enabled and must remain so 2686 */ 2687 if (IS_I830(dev_priv) || !intel_crtc_needs_modeset(crtc_state)) 2688 val |= TRANSCONF_ENABLE; 2689 2690 if (crtc_state->double_wide) 2691 val |= TRANSCONF_DOUBLE_WIDE; 2692 2693 /* only g4x and later have fancy bpc/dither controls */ 2694 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 2695 IS_CHERRYVIEW(dev_priv)) { 2696 /* Bspec claims that we can't use dithering for 30bpp pipes. */ 2697 if (crtc_state->dither && crtc_state->pipe_bpp != 30) 2698 val |= TRANSCONF_DITHER_EN | 2699 TRANSCONF_DITHER_TYPE_SP; 2700 2701 switch (crtc_state->pipe_bpp) { 2702 default: 2703 /* Case prevented by intel_choose_pipe_bpp_dither. */ 2704 MISSING_CASE(crtc_state->pipe_bpp); 2705 fallthrough; 2706 case 18: 2707 val |= TRANSCONF_BPC_6; 2708 break; 2709 case 24: 2710 val |= TRANSCONF_BPC_8; 2711 break; 2712 case 30: 2713 val |= TRANSCONF_BPC_10; 2714 break; 2715 } 2716 } 2717 2718 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 2719 if (DISPLAY_VER(dev_priv) < 4 || 2720 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 2721 val |= TRANSCONF_INTERLACE_W_FIELD_INDICATION; 2722 else 2723 val |= TRANSCONF_INTERLACE_W_SYNC_SHIFT; 2724 } else { 2725 val |= TRANSCONF_INTERLACE_PROGRESSIVE; 2726 } 2727 2728 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 2729 crtc_state->limited_color_range) 2730 val |= TRANSCONF_COLOR_RANGE_SELECT; 2731 2732 val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode); 2733 2734 val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 2735 2736 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); 2737 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); 2738 } 2739 2740 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv) 2741 { 2742 if (IS_I830(dev_priv)) 2743 return false; 2744 2745 return DISPLAY_VER(dev_priv) >= 4 || 2746 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); 2747 } 2748 2749 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state) 2750 { 2751 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2752 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2753 enum pipe pipe; 2754 u32 tmp; 2755 2756 if (!i9xx_has_pfit(dev_priv)) 2757 return; 2758 2759 tmp = intel_de_read(dev_priv, PFIT_CONTROL); 2760 if (!(tmp & PFIT_ENABLE)) 2761 return; 2762 2763 /* Check whether the pfit is attached to our pipe. */ 2764 if (DISPLAY_VER(dev_priv) >= 4) 2765 pipe = REG_FIELD_GET(PFIT_PIPE_MASK, tmp); 2766 else 2767 pipe = PIPE_B; 2768 2769 if (pipe != crtc->pipe) 2770 return; 2771 2772 crtc_state->gmch_pfit.control = tmp; 2773 crtc_state->gmch_pfit.pgm_ratios = 2774 intel_de_read(dev_priv, PFIT_PGM_RATIOS); 2775 } 2776 2777 static void vlv_crtc_clock_get(struct intel_crtc *crtc, 2778 struct intel_crtc_state *pipe_config) 2779 { 2780 struct drm_device *dev = crtc->base.dev; 2781 struct drm_i915_private *dev_priv = to_i915(dev); 2782 enum pipe pipe = crtc->pipe; 2783 struct dpll clock; 2784 u32 mdiv; 2785 int refclk = 100000; 2786 2787 /* In case of DSI, DPLL will not be used */ 2788 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 2789 return; 2790 2791 vlv_dpio_get(dev_priv); 2792 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); 2793 vlv_dpio_put(dev_priv); 2794 2795 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; 2796 clock.m2 = mdiv & DPIO_M2DIV_MASK; 2797 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; 2798 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; 2799 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; 2800 2801 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); 2802 } 2803 2804 static void chv_crtc_clock_get(struct intel_crtc *crtc, 2805 struct intel_crtc_state *pipe_config) 2806 { 2807 struct drm_device *dev = crtc->base.dev; 2808 struct drm_i915_private *dev_priv = to_i915(dev); 2809 enum pipe pipe = crtc->pipe; 2810 enum dpio_channel port = vlv_pipe_to_channel(pipe); 2811 struct dpll clock; 2812 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; 2813 int refclk = 100000; 2814 2815 /* In case of DSI, DPLL will not be used */ 2816 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 2817 return; 2818 2819 vlv_dpio_get(dev_priv); 2820 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); 2821 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); 2822 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); 2823 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); 2824 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); 2825 vlv_dpio_put(dev_priv); 2826 2827 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; 2828 clock.m2 = (pll_dw0 & 0xff) << 22; 2829 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) 2830 clock.m2 |= pll_dw2 & 0x3fffff; 2831 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; 2832 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; 2833 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; 2834 2835 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); 2836 } 2837 2838 static enum intel_output_format 2839 bdw_get_pipe_misc_output_format(struct intel_crtc *crtc) 2840 { 2841 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2842 u32 tmp; 2843 2844 tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe)); 2845 2846 if (tmp & PIPE_MISC_YUV420_ENABLE) { 2847 /* We support 4:2:0 in full blend mode only */ 2848 drm_WARN_ON(&dev_priv->drm, 2849 (tmp & PIPE_MISC_YUV420_MODE_FULL_BLEND) == 0); 2850 2851 return INTEL_OUTPUT_FORMAT_YCBCR420; 2852 } else if (tmp & PIPE_MISC_OUTPUT_COLORSPACE_YUV) { 2853 return INTEL_OUTPUT_FORMAT_YCBCR444; 2854 } else { 2855 return INTEL_OUTPUT_FORMAT_RGB; 2856 } 2857 } 2858 2859 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state) 2860 { 2861 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2862 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 2863 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2864 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 2865 u32 tmp; 2866 2867 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); 2868 2869 if (tmp & DISP_PIPE_GAMMA_ENABLE) 2870 crtc_state->gamma_enable = true; 2871 2872 if (!HAS_GMCH(dev_priv) && 2873 tmp & DISP_PIPE_CSC_ENABLE) 2874 crtc_state->csc_enable = true; 2875 } 2876 2877 static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 2878 struct intel_crtc_state *pipe_config) 2879 { 2880 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2881 enum intel_display_power_domain power_domain; 2882 intel_wakeref_t wakeref; 2883 u32 tmp; 2884 bool ret; 2885 2886 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 2887 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 2888 if (!wakeref) 2889 return false; 2890 2891 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 2892 pipe_config->sink_format = pipe_config->output_format; 2893 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 2894 pipe_config->shared_dpll = NULL; 2895 2896 ret = false; 2897 2898 tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder)); 2899 if (!(tmp & TRANSCONF_ENABLE)) 2900 goto out; 2901 2902 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 2903 IS_CHERRYVIEW(dev_priv)) { 2904 switch (tmp & TRANSCONF_BPC_MASK) { 2905 case TRANSCONF_BPC_6: 2906 pipe_config->pipe_bpp = 18; 2907 break; 2908 case TRANSCONF_BPC_8: 2909 pipe_config->pipe_bpp = 24; 2910 break; 2911 case TRANSCONF_BPC_10: 2912 pipe_config->pipe_bpp = 30; 2913 break; 2914 default: 2915 MISSING_CASE(tmp); 2916 break; 2917 } 2918 } 2919 2920 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 2921 (tmp & TRANSCONF_COLOR_RANGE_SELECT)) 2922 pipe_config->limited_color_range = true; 2923 2924 pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp); 2925 2926 pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1; 2927 2928 if (IS_CHERRYVIEW(dev_priv)) 2929 pipe_config->cgm_mode = intel_de_read(dev_priv, 2930 CGM_PIPE_MODE(crtc->pipe)); 2931 2932 i9xx_get_pipe_color_config(pipe_config); 2933 intel_color_get_config(pipe_config); 2934 2935 if (DISPLAY_VER(dev_priv) < 4) 2936 pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE; 2937 2938 intel_get_transcoder_timings(crtc, pipe_config); 2939 intel_get_pipe_src_size(crtc, pipe_config); 2940 2941 i9xx_get_pfit_config(pipe_config); 2942 2943 if (DISPLAY_VER(dev_priv) >= 4) { 2944 /* No way to read it out on pipes B and C */ 2945 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) 2946 tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe]; 2947 else 2948 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe)); 2949 pipe_config->pixel_multiplier = 2950 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) 2951 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; 2952 pipe_config->dpll_hw_state.dpll_md = tmp; 2953 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 2954 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 2955 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe)); 2956 pipe_config->pixel_multiplier = 2957 ((tmp & SDVO_MULTIPLIER_MASK) 2958 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; 2959 } else { 2960 /* Note that on i915G/GM the pixel multiplier is in the sdvo 2961 * port and will be fixed up in the encoder->get_config 2962 * function. */ 2963 pipe_config->pixel_multiplier = 1; 2964 } 2965 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv, 2966 DPLL(crtc->pipe)); 2967 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 2968 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv, 2969 FP0(crtc->pipe)); 2970 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv, 2971 FP1(crtc->pipe)); 2972 } else { 2973 /* Mask out read-only status bits. */ 2974 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | 2975 DPLL_PORTC_READY_MASK | 2976 DPLL_PORTB_READY_MASK); 2977 } 2978 2979 if (IS_CHERRYVIEW(dev_priv)) 2980 chv_crtc_clock_get(crtc, pipe_config); 2981 else if (IS_VALLEYVIEW(dev_priv)) 2982 vlv_crtc_clock_get(crtc, pipe_config); 2983 else 2984 i9xx_crtc_clock_get(crtc, pipe_config); 2985 2986 /* 2987 * Normally the dotclock is filled in by the encoder .get_config() 2988 * but in case the pipe is enabled w/o any ports we need a sane 2989 * default. 2990 */ 2991 pipe_config->hw.adjusted_mode.crtc_clock = 2992 pipe_config->port_clock / pipe_config->pixel_multiplier; 2993 2994 ret = true; 2995 2996 out: 2997 intel_display_power_put(dev_priv, power_domain, wakeref); 2998 2999 return ret; 3000 } 3001 3002 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) 3003 { 3004 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3005 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3006 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3007 u32 val = 0; 3008 3009 /* 3010 * - During modeset the pipe is still disabled and must remain so 3011 * - During fastset the pipe is already enabled and must remain so 3012 */ 3013 if (!intel_crtc_needs_modeset(crtc_state)) 3014 val |= TRANSCONF_ENABLE; 3015 3016 switch (crtc_state->pipe_bpp) { 3017 default: 3018 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3019 MISSING_CASE(crtc_state->pipe_bpp); 3020 fallthrough; 3021 case 18: 3022 val |= TRANSCONF_BPC_6; 3023 break; 3024 case 24: 3025 val |= TRANSCONF_BPC_8; 3026 break; 3027 case 30: 3028 val |= TRANSCONF_BPC_10; 3029 break; 3030 case 36: 3031 val |= TRANSCONF_BPC_12; 3032 break; 3033 } 3034 3035 if (crtc_state->dither) 3036 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP; 3037 3038 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3039 val |= TRANSCONF_INTERLACE_IF_ID_ILK; 3040 else 3041 val |= TRANSCONF_INTERLACE_PF_PD_ILK; 3042 3043 /* 3044 * This would end up with an odd purple hue over 3045 * the entire display. Make sure we don't do it. 3046 */ 3047 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 3048 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 3049 3050 if (crtc_state->limited_color_range && 3051 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3052 val |= TRANSCONF_COLOR_RANGE_SELECT; 3053 3054 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3055 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV709; 3056 3057 val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode); 3058 3059 val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3060 val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay); 3061 3062 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); 3063 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); 3064 } 3065 3066 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) 3067 { 3068 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3069 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3070 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3071 u32 val = 0; 3072 3073 /* 3074 * - During modeset the pipe is still disabled and must remain so 3075 * - During fastset the pipe is already enabled and must remain so 3076 */ 3077 if (!intel_crtc_needs_modeset(crtc_state)) 3078 val |= TRANSCONF_ENABLE; 3079 3080 if (IS_HASWELL(dev_priv) && crtc_state->dither) 3081 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP; 3082 3083 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3084 val |= TRANSCONF_INTERLACE_IF_ID_ILK; 3085 else 3086 val |= TRANSCONF_INTERLACE_PF_PD_ILK; 3087 3088 if (IS_HASWELL(dev_priv) && 3089 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3090 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW; 3091 3092 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); 3093 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); 3094 } 3095 3096 static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state) 3097 { 3098 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3099 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3100 u32 val = 0; 3101 3102 switch (crtc_state->pipe_bpp) { 3103 case 18: 3104 val |= PIPE_MISC_BPC_6; 3105 break; 3106 case 24: 3107 val |= PIPE_MISC_BPC_8; 3108 break; 3109 case 30: 3110 val |= PIPE_MISC_BPC_10; 3111 break; 3112 case 36: 3113 /* Port output 12BPC defined for ADLP+ */ 3114 if (DISPLAY_VER(dev_priv) > 12) 3115 val |= PIPE_MISC_BPC_12_ADLP; 3116 break; 3117 default: 3118 MISSING_CASE(crtc_state->pipe_bpp); 3119 break; 3120 } 3121 3122 if (crtc_state->dither) 3123 val |= PIPE_MISC_DITHER_ENABLE | PIPE_MISC_DITHER_TYPE_SP; 3124 3125 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 3126 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 3127 val |= PIPE_MISC_OUTPUT_COLORSPACE_YUV; 3128 3129 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 3130 val |= PIPE_MISC_YUV420_ENABLE | 3131 PIPE_MISC_YUV420_MODE_FULL_BLEND; 3132 3133 if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state)) 3134 val |= PIPE_MISC_HDR_MODE_PRECISION; 3135 3136 if (DISPLAY_VER(dev_priv) >= 12) 3137 val |= PIPE_MISC_PIXEL_ROUNDING_TRUNC; 3138 3139 intel_de_write(dev_priv, PIPE_MISC(crtc->pipe), val); 3140 } 3141 3142 int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc) 3143 { 3144 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3145 u32 tmp; 3146 3147 tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe)); 3148 3149 switch (tmp & PIPE_MISC_BPC_MASK) { 3150 case PIPE_MISC_BPC_6: 3151 return 18; 3152 case PIPE_MISC_BPC_8: 3153 return 24; 3154 case PIPE_MISC_BPC_10: 3155 return 30; 3156 /* 3157 * PORT OUTPUT 12 BPC defined for ADLP+. 3158 * 3159 * TODO: 3160 * For previous platforms with DSI interface, bits 5:7 3161 * are used for storing pipe_bpp irrespective of dithering. 3162 * Since the value of 12 BPC is not defined for these bits 3163 * on older platforms, need to find a workaround for 12 BPC 3164 * MIPI DSI HW readout. 3165 */ 3166 case PIPE_MISC_BPC_12_ADLP: 3167 if (DISPLAY_VER(dev_priv) > 12) 3168 return 36; 3169 fallthrough; 3170 default: 3171 MISSING_CASE(tmp); 3172 return 0; 3173 } 3174 } 3175 3176 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) 3177 { 3178 /* 3179 * Account for spread spectrum to avoid 3180 * oversubscribing the link. Max center spread 3181 * is 2.5%; use 5% for safety's sake. 3182 */ 3183 u32 bps = target_clock * bpp * 21 / 20; 3184 return DIV_ROUND_UP(bps, link_bw * 8); 3185 } 3186 3187 void intel_get_m_n(struct drm_i915_private *i915, 3188 struct intel_link_m_n *m_n, 3189 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 3190 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 3191 { 3192 m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK; 3193 m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK; 3194 m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK; 3195 m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK; 3196 m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1; 3197 } 3198 3199 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, 3200 enum transcoder transcoder, 3201 struct intel_link_m_n *m_n) 3202 { 3203 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3204 enum pipe pipe = crtc->pipe; 3205 3206 if (DISPLAY_VER(dev_priv) >= 5) 3207 intel_get_m_n(dev_priv, m_n, 3208 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 3209 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 3210 else 3211 intel_get_m_n(dev_priv, m_n, 3212 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 3213 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 3214 } 3215 3216 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, 3217 enum transcoder transcoder, 3218 struct intel_link_m_n *m_n) 3219 { 3220 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3221 3222 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 3223 return; 3224 3225 intel_get_m_n(dev_priv, m_n, 3226 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 3227 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 3228 } 3229 3230 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state) 3231 { 3232 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3233 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3234 u32 ctl, pos, size; 3235 enum pipe pipe; 3236 3237 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe)); 3238 if ((ctl & PF_ENABLE) == 0) 3239 return; 3240 3241 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) 3242 pipe = REG_FIELD_GET(PF_PIPE_SEL_MASK_IVB, ctl); 3243 else 3244 pipe = crtc->pipe; 3245 3246 crtc_state->pch_pfit.enabled = true; 3247 3248 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe)); 3249 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe)); 3250 3251 drm_rect_init(&crtc_state->pch_pfit.dst, 3252 REG_FIELD_GET(PF_WIN_XPOS_MASK, pos), 3253 REG_FIELD_GET(PF_WIN_YPOS_MASK, pos), 3254 REG_FIELD_GET(PF_WIN_XSIZE_MASK, size), 3255 REG_FIELD_GET(PF_WIN_YSIZE_MASK, size)); 3256 3257 /* 3258 * We currently do not free assignements of panel fitters on 3259 * ivb/hsw (since we don't use the higher upscaling modes which 3260 * differentiates them) so just WARN about this case for now. 3261 */ 3262 drm_WARN_ON(&dev_priv->drm, pipe != crtc->pipe); 3263 } 3264 3265 static bool ilk_get_pipe_config(struct intel_crtc *crtc, 3266 struct intel_crtc_state *pipe_config) 3267 { 3268 struct drm_device *dev = crtc->base.dev; 3269 struct drm_i915_private *dev_priv = to_i915(dev); 3270 enum intel_display_power_domain power_domain; 3271 intel_wakeref_t wakeref; 3272 u32 tmp; 3273 bool ret; 3274 3275 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3276 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3277 if (!wakeref) 3278 return false; 3279 3280 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3281 pipe_config->shared_dpll = NULL; 3282 3283 ret = false; 3284 tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder)); 3285 if (!(tmp & TRANSCONF_ENABLE)) 3286 goto out; 3287 3288 switch (tmp & TRANSCONF_BPC_MASK) { 3289 case TRANSCONF_BPC_6: 3290 pipe_config->pipe_bpp = 18; 3291 break; 3292 case TRANSCONF_BPC_8: 3293 pipe_config->pipe_bpp = 24; 3294 break; 3295 case TRANSCONF_BPC_10: 3296 pipe_config->pipe_bpp = 30; 3297 break; 3298 case TRANSCONF_BPC_12: 3299 pipe_config->pipe_bpp = 36; 3300 break; 3301 default: 3302 break; 3303 } 3304 3305 if (tmp & TRANSCONF_COLOR_RANGE_SELECT) 3306 pipe_config->limited_color_range = true; 3307 3308 switch (tmp & TRANSCONF_OUTPUT_COLORSPACE_MASK) { 3309 case TRANSCONF_OUTPUT_COLORSPACE_YUV601: 3310 case TRANSCONF_OUTPUT_COLORSPACE_YUV709: 3311 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3312 break; 3313 default: 3314 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3315 break; 3316 } 3317 3318 pipe_config->sink_format = pipe_config->output_format; 3319 3320 pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp); 3321 3322 pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1; 3323 3324 pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp); 3325 3326 pipe_config->csc_mode = intel_de_read(dev_priv, 3327 PIPE_CSC_MODE(crtc->pipe)); 3328 3329 i9xx_get_pipe_color_config(pipe_config); 3330 intel_color_get_config(pipe_config); 3331 3332 pipe_config->pixel_multiplier = 1; 3333 3334 ilk_pch_get_config(pipe_config); 3335 3336 intel_get_transcoder_timings(crtc, pipe_config); 3337 intel_get_pipe_src_size(crtc, pipe_config); 3338 3339 ilk_get_pfit_config(pipe_config); 3340 3341 ret = true; 3342 3343 out: 3344 intel_display_power_put(dev_priv, power_domain, wakeref); 3345 3346 return ret; 3347 } 3348 3349 static u8 bigjoiner_pipes(struct drm_i915_private *i915) 3350 { 3351 u8 pipes; 3352 3353 if (DISPLAY_VER(i915) >= 12) 3354 pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D); 3355 else if (DISPLAY_VER(i915) >= 11) 3356 pipes = BIT(PIPE_B) | BIT(PIPE_C); 3357 else 3358 pipes = 0; 3359 3360 return pipes & RUNTIME_INFO(i915)->pipe_mask; 3361 } 3362 3363 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv, 3364 enum transcoder cpu_transcoder) 3365 { 3366 enum intel_display_power_domain power_domain; 3367 intel_wakeref_t wakeref; 3368 u32 tmp = 0; 3369 3370 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3371 3372 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3373 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3374 3375 return tmp & TRANS_DDI_FUNC_ENABLE; 3376 } 3377 3378 static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv, 3379 u8 *master_pipes, u8 *slave_pipes) 3380 { 3381 struct intel_crtc *crtc; 3382 3383 *master_pipes = 0; 3384 *slave_pipes = 0; 3385 3386 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, 3387 bigjoiner_pipes(dev_priv)) { 3388 enum intel_display_power_domain power_domain; 3389 enum pipe pipe = crtc->pipe; 3390 intel_wakeref_t wakeref; 3391 3392 power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe); 3393 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3394 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3395 3396 if (!(tmp & BIG_JOINER_ENABLE)) 3397 continue; 3398 3399 if (tmp & MASTER_BIG_JOINER_ENABLE) 3400 *master_pipes |= BIT(pipe); 3401 else 3402 *slave_pipes |= BIT(pipe); 3403 } 3404 3405 if (DISPLAY_VER(dev_priv) < 13) 3406 continue; 3407 3408 power_domain = POWER_DOMAIN_PIPE(pipe); 3409 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3410 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3411 3412 if (tmp & UNCOMPRESSED_JOINER_MASTER) 3413 *master_pipes |= BIT(pipe); 3414 if (tmp & UNCOMPRESSED_JOINER_SLAVE) 3415 *slave_pipes |= BIT(pipe); 3416 } 3417 } 3418 3419 /* Bigjoiner pipes should always be consecutive master and slave */ 3420 drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1, 3421 "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n", 3422 *master_pipes, *slave_pipes); 3423 } 3424 3425 static enum pipe get_bigjoiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3426 { 3427 if ((slave_pipes & BIT(pipe)) == 0) 3428 return pipe; 3429 3430 /* ignore everything above our pipe */ 3431 master_pipes &= ~GENMASK(7, pipe); 3432 3433 /* highest remaining bit should be our master pipe */ 3434 return fls(master_pipes) - 1; 3435 } 3436 3437 static u8 get_bigjoiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3438 { 3439 enum pipe master_pipe, next_master_pipe; 3440 3441 master_pipe = get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes); 3442 3443 if ((master_pipes & BIT(master_pipe)) == 0) 3444 return 0; 3445 3446 /* ignore our master pipe and everything below it */ 3447 master_pipes &= ~GENMASK(master_pipe, 0); 3448 /* make sure a high bit is set for the ffs() */ 3449 master_pipes |= BIT(7); 3450 /* lowest remaining bit should be the next master pipe */ 3451 next_master_pipe = ffs(master_pipes) - 1; 3452 3453 return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe); 3454 } 3455 3456 static u8 hsw_panel_transcoders(struct drm_i915_private *i915) 3457 { 3458 u8 panel_transcoder_mask = BIT(TRANSCODER_EDP); 3459 3460 if (DISPLAY_VER(i915) >= 11) 3461 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); 3462 3463 return panel_transcoder_mask; 3464 } 3465 3466 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) 3467 { 3468 struct drm_device *dev = crtc->base.dev; 3469 struct drm_i915_private *dev_priv = to_i915(dev); 3470 u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv); 3471 enum transcoder cpu_transcoder; 3472 u8 master_pipes, slave_pipes; 3473 u8 enabled_transcoders = 0; 3474 3475 /* 3476 * XXX: Do intel_display_power_get_if_enabled before reading this (for 3477 * consistency and less surprising code; it's in always on power). 3478 */ 3479 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, 3480 panel_transcoder_mask) { 3481 enum intel_display_power_domain power_domain; 3482 intel_wakeref_t wakeref; 3483 enum pipe trans_pipe; 3484 u32 tmp = 0; 3485 3486 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3487 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3488 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3489 3490 if (!(tmp & TRANS_DDI_FUNC_ENABLE)) 3491 continue; 3492 3493 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 3494 default: 3495 drm_WARN(dev, 1, 3496 "unknown pipe linked to transcoder %s\n", 3497 transcoder_name(cpu_transcoder)); 3498 fallthrough; 3499 case TRANS_DDI_EDP_INPUT_A_ONOFF: 3500 case TRANS_DDI_EDP_INPUT_A_ON: 3501 trans_pipe = PIPE_A; 3502 break; 3503 case TRANS_DDI_EDP_INPUT_B_ONOFF: 3504 trans_pipe = PIPE_B; 3505 break; 3506 case TRANS_DDI_EDP_INPUT_C_ONOFF: 3507 trans_pipe = PIPE_C; 3508 break; 3509 case TRANS_DDI_EDP_INPUT_D_ONOFF: 3510 trans_pipe = PIPE_D; 3511 break; 3512 } 3513 3514 if (trans_pipe == crtc->pipe) 3515 enabled_transcoders |= BIT(cpu_transcoder); 3516 } 3517 3518 /* single pipe or bigjoiner master */ 3519 cpu_transcoder = (enum transcoder) crtc->pipe; 3520 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 3521 enabled_transcoders |= BIT(cpu_transcoder); 3522 3523 /* bigjoiner slave -> consider the master pipe's transcoder as well */ 3524 enabled_bigjoiner_pipes(dev_priv, &master_pipes, &slave_pipes); 3525 if (slave_pipes & BIT(crtc->pipe)) { 3526 cpu_transcoder = (enum transcoder) 3527 get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes); 3528 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 3529 enabled_transcoders |= BIT(cpu_transcoder); 3530 } 3531 3532 return enabled_transcoders; 3533 } 3534 3535 static bool has_edp_transcoders(u8 enabled_transcoders) 3536 { 3537 return enabled_transcoders & BIT(TRANSCODER_EDP); 3538 } 3539 3540 static bool has_dsi_transcoders(u8 enabled_transcoders) 3541 { 3542 return enabled_transcoders & (BIT(TRANSCODER_DSI_0) | 3543 BIT(TRANSCODER_DSI_1)); 3544 } 3545 3546 static bool has_pipe_transcoders(u8 enabled_transcoders) 3547 { 3548 return enabled_transcoders & ~(BIT(TRANSCODER_EDP) | 3549 BIT(TRANSCODER_DSI_0) | 3550 BIT(TRANSCODER_DSI_1)); 3551 } 3552 3553 static void assert_enabled_transcoders(struct drm_i915_private *i915, 3554 u8 enabled_transcoders) 3555 { 3556 /* Only one type of transcoder please */ 3557 drm_WARN_ON(&i915->drm, 3558 has_edp_transcoders(enabled_transcoders) + 3559 has_dsi_transcoders(enabled_transcoders) + 3560 has_pipe_transcoders(enabled_transcoders) > 1); 3561 3562 /* Only DSI transcoders can be ganged */ 3563 drm_WARN_ON(&i915->drm, 3564 !has_dsi_transcoders(enabled_transcoders) && 3565 !is_power_of_2(enabled_transcoders)); 3566 } 3567 3568 static bool hsw_get_transcoder_state(struct intel_crtc *crtc, 3569 struct intel_crtc_state *pipe_config, 3570 struct intel_display_power_domain_set *power_domain_set) 3571 { 3572 struct drm_device *dev = crtc->base.dev; 3573 struct drm_i915_private *dev_priv = to_i915(dev); 3574 unsigned long enabled_transcoders; 3575 u32 tmp; 3576 3577 enabled_transcoders = hsw_enabled_transcoders(crtc); 3578 if (!enabled_transcoders) 3579 return false; 3580 3581 assert_enabled_transcoders(dev_priv, enabled_transcoders); 3582 3583 /* 3584 * With the exception of DSI we should only ever have 3585 * a single enabled transcoder. With DSI let's just 3586 * pick the first one. 3587 */ 3588 pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1; 3589 3590 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 3591 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) 3592 return false; 3593 3594 if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) { 3595 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); 3596 3597 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF) 3598 pipe_config->pch_pfit.force_thru = true; 3599 } 3600 3601 tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder)); 3602 3603 return tmp & TRANSCONF_ENABLE; 3604 } 3605 3606 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, 3607 struct intel_crtc_state *pipe_config, 3608 struct intel_display_power_domain_set *power_domain_set) 3609 { 3610 struct drm_device *dev = crtc->base.dev; 3611 struct drm_i915_private *dev_priv = to_i915(dev); 3612 enum transcoder cpu_transcoder; 3613 enum port port; 3614 u32 tmp; 3615 3616 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { 3617 if (port == PORT_A) 3618 cpu_transcoder = TRANSCODER_DSI_A; 3619 else 3620 cpu_transcoder = TRANSCODER_DSI_C; 3621 3622 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 3623 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) 3624 continue; 3625 3626 /* 3627 * The PLL needs to be enabled with a valid divider 3628 * configuration, otherwise accessing DSI registers will hang 3629 * the machine. See BSpec North Display Engine 3630 * registers/MIPI[BXT]. We can break out here early, since we 3631 * need the same DSI PLL to be enabled for both DSI ports. 3632 */ 3633 if (!bxt_dsi_pll_is_enabled(dev_priv)) 3634 break; 3635 3636 /* XXX: this works for video mode only */ 3637 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); 3638 if (!(tmp & DPI_ENABLE)) 3639 continue; 3640 3641 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 3642 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) 3643 continue; 3644 3645 pipe_config->cpu_transcoder = cpu_transcoder; 3646 break; 3647 } 3648 3649 return transcoder_is_dsi(pipe_config->cpu_transcoder); 3650 } 3651 3652 static void intel_bigjoiner_get_config(struct intel_crtc_state *crtc_state) 3653 { 3654 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3655 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 3656 u8 master_pipes, slave_pipes; 3657 enum pipe pipe = crtc->pipe; 3658 3659 enabled_bigjoiner_pipes(i915, &master_pipes, &slave_pipes); 3660 3661 if (((master_pipes | slave_pipes) & BIT(pipe)) == 0) 3662 return; 3663 3664 crtc_state->bigjoiner_pipes = 3665 BIT(get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes)) | 3666 get_bigjoiner_slave_pipes(pipe, master_pipes, slave_pipes); 3667 } 3668 3669 static bool hsw_get_pipe_config(struct intel_crtc *crtc, 3670 struct intel_crtc_state *pipe_config) 3671 { 3672 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3673 bool active; 3674 u32 tmp; 3675 3676 if (!intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains, 3677 POWER_DOMAIN_PIPE(crtc->pipe))) 3678 return false; 3679 3680 pipe_config->shared_dpll = NULL; 3681 3682 active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains); 3683 3684 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 3685 bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) { 3686 drm_WARN_ON(&dev_priv->drm, active); 3687 active = true; 3688 } 3689 3690 if (!active) 3691 goto out; 3692 3693 intel_dsc_get_config(pipe_config); 3694 intel_bigjoiner_get_config(pipe_config); 3695 3696 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || 3697 DISPLAY_VER(dev_priv) >= 11) 3698 intel_get_transcoder_timings(crtc, pipe_config); 3699 3700 if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder)) 3701 intel_vrr_get_config(pipe_config); 3702 3703 intel_get_pipe_src_size(crtc, pipe_config); 3704 3705 if (IS_HASWELL(dev_priv)) { 3706 u32 tmp = intel_de_read(dev_priv, 3707 TRANSCONF(pipe_config->cpu_transcoder)); 3708 3709 if (tmp & TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW) 3710 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3711 else 3712 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3713 } else { 3714 pipe_config->output_format = 3715 bdw_get_pipe_misc_output_format(crtc); 3716 } 3717 3718 pipe_config->sink_format = pipe_config->output_format; 3719 3720 pipe_config->gamma_mode = intel_de_read(dev_priv, 3721 GAMMA_MODE(crtc->pipe)); 3722 3723 pipe_config->csc_mode = intel_de_read(dev_priv, 3724 PIPE_CSC_MODE(crtc->pipe)); 3725 3726 if (DISPLAY_VER(dev_priv) >= 9) { 3727 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe)); 3728 3729 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE) 3730 pipe_config->gamma_enable = true; 3731 3732 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE) 3733 pipe_config->csc_enable = true; 3734 } else { 3735 i9xx_get_pipe_color_config(pipe_config); 3736 } 3737 3738 intel_color_get_config(pipe_config); 3739 3740 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe)); 3741 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); 3742 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 3743 pipe_config->ips_linetime = 3744 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); 3745 3746 if (intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains, 3747 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) { 3748 if (DISPLAY_VER(dev_priv) >= 9) 3749 skl_scaler_get_config(pipe_config); 3750 else 3751 ilk_get_pfit_config(pipe_config); 3752 } 3753 3754 hsw_ips_get_config(pipe_config); 3755 3756 if (pipe_config->cpu_transcoder != TRANSCODER_EDP && 3757 !transcoder_is_dsi(pipe_config->cpu_transcoder)) { 3758 pipe_config->pixel_multiplier = 3759 intel_de_read(dev_priv, 3760 TRANS_MULT(pipe_config->cpu_transcoder)) + 1; 3761 } else { 3762 pipe_config->pixel_multiplier = 1; 3763 } 3764 3765 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { 3766 tmp = intel_de_read(dev_priv, DISPLAY_VER(dev_priv) >= 14 ? 3767 MTL_CHICKEN_TRANS(pipe_config->cpu_transcoder) : 3768 CHICKEN_TRANS(pipe_config->cpu_transcoder)); 3769 3770 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1; 3771 } else { 3772 /* no idea if this is correct */ 3773 pipe_config->framestart_delay = 1; 3774 } 3775 3776 out: 3777 intel_display_power_put_all_in_set(dev_priv, &crtc->hw_readout_power_domains); 3778 3779 return active; 3780 } 3781 3782 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state) 3783 { 3784 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3785 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 3786 3787 if (!i915->display.funcs.display->get_pipe_config(crtc, crtc_state)) 3788 return false; 3789 3790 crtc_state->hw.active = true; 3791 3792 intel_crtc_readout_derived_state(crtc_state); 3793 3794 return true; 3795 } 3796 3797 static int i9xx_pll_refclk(struct drm_device *dev, 3798 const struct intel_crtc_state *pipe_config) 3799 { 3800 struct drm_i915_private *dev_priv = to_i915(dev); 3801 u32 dpll = pipe_config->dpll_hw_state.dpll; 3802 3803 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) 3804 return dev_priv->display.vbt.lvds_ssc_freq; 3805 else if (HAS_PCH_SPLIT(dev_priv)) 3806 return 120000; 3807 else if (DISPLAY_VER(dev_priv) != 2) 3808 return 96000; 3809 else 3810 return 48000; 3811 } 3812 3813 /* Returns the clock of the currently programmed mode of the given pipe. */ 3814 void i9xx_crtc_clock_get(struct intel_crtc *crtc, 3815 struct intel_crtc_state *pipe_config) 3816 { 3817 struct drm_device *dev = crtc->base.dev; 3818 struct drm_i915_private *dev_priv = to_i915(dev); 3819 u32 dpll = pipe_config->dpll_hw_state.dpll; 3820 u32 fp; 3821 struct dpll clock; 3822 int port_clock; 3823 int refclk = i9xx_pll_refclk(dev, pipe_config); 3824 3825 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 3826 fp = pipe_config->dpll_hw_state.fp0; 3827 else 3828 fp = pipe_config->dpll_hw_state.fp1; 3829 3830 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 3831 if (IS_PINEVIEW(dev_priv)) { 3832 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; 3833 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; 3834 } else { 3835 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 3836 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 3837 } 3838 3839 if (DISPLAY_VER(dev_priv) != 2) { 3840 if (IS_PINEVIEW(dev_priv)) 3841 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> 3842 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); 3843 else 3844 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> 3845 DPLL_FPA01_P1_POST_DIV_SHIFT); 3846 3847 switch (dpll & DPLL_MODE_MASK) { 3848 case DPLLB_MODE_DAC_SERIAL: 3849 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 3850 5 : 10; 3851 break; 3852 case DPLLB_MODE_LVDS: 3853 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 3854 7 : 14; 3855 break; 3856 default: 3857 drm_dbg_kms(&dev_priv->drm, 3858 "Unknown DPLL mode %08x in programmed " 3859 "mode\n", (int)(dpll & DPLL_MODE_MASK)); 3860 return; 3861 } 3862 3863 if (IS_PINEVIEW(dev_priv)) 3864 port_clock = pnv_calc_dpll_params(refclk, &clock); 3865 else 3866 port_clock = i9xx_calc_dpll_params(refclk, &clock); 3867 } else { 3868 enum pipe lvds_pipe; 3869 3870 if (IS_I85X(dev_priv) && 3871 intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) && 3872 lvds_pipe == crtc->pipe) { 3873 u32 lvds = intel_de_read(dev_priv, LVDS); 3874 3875 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 3876 DPLL_FPA01_P1_POST_DIV_SHIFT); 3877 3878 if (lvds & LVDS_CLKB_POWER_UP) 3879 clock.p2 = 7; 3880 else 3881 clock.p2 = 14; 3882 } else { 3883 if (dpll & PLL_P1_DIVIDE_BY_TWO) 3884 clock.p1 = 2; 3885 else { 3886 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 3887 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 3888 } 3889 if (dpll & PLL_P2_DIVIDE_BY_4) 3890 clock.p2 = 4; 3891 else 3892 clock.p2 = 2; 3893 } 3894 3895 port_clock = i9xx_calc_dpll_params(refclk, &clock); 3896 } 3897 3898 /* 3899 * This value includes pixel_multiplier. We will use 3900 * port_clock to compute adjusted_mode.crtc_clock in the 3901 * encoder's get_config() function. 3902 */ 3903 pipe_config->port_clock = port_clock; 3904 } 3905 3906 int intel_dotclock_calculate(int link_freq, 3907 const struct intel_link_m_n *m_n) 3908 { 3909 /* 3910 * The calculation for the data clock is: 3911 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp 3912 * But we want to avoid losing precison if possible, so: 3913 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) 3914 * 3915 * and the link clock is simpler: 3916 * link_clock = (m * link_clock) / n 3917 */ 3918 3919 if (!m_n->link_n) 3920 return 0; 3921 3922 return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq), 3923 m_n->link_n); 3924 } 3925 3926 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config) 3927 { 3928 int dotclock; 3929 3930 if (intel_crtc_has_dp_encoder(pipe_config)) 3931 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 3932 &pipe_config->dp_m_n); 3933 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) 3934 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24, 3935 pipe_config->pipe_bpp); 3936 else 3937 dotclock = pipe_config->port_clock; 3938 3939 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 3940 !intel_crtc_has_dp_encoder(pipe_config)) 3941 dotclock *= 2; 3942 3943 if (pipe_config->pixel_multiplier) 3944 dotclock /= pipe_config->pixel_multiplier; 3945 3946 return dotclock; 3947 } 3948 3949 /* Returns the currently programmed mode of the given encoder. */ 3950 struct drm_display_mode * 3951 intel_encoder_current_mode(struct intel_encoder *encoder) 3952 { 3953 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3954 struct intel_crtc_state *crtc_state; 3955 struct drm_display_mode *mode; 3956 struct intel_crtc *crtc; 3957 enum pipe pipe; 3958 3959 if (!encoder->get_hw_state(encoder, &pipe)) 3960 return NULL; 3961 3962 crtc = intel_crtc_for_pipe(dev_priv, pipe); 3963 3964 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 3965 if (!mode) 3966 return NULL; 3967 3968 crtc_state = intel_crtc_state_alloc(crtc); 3969 if (!crtc_state) { 3970 kfree(mode); 3971 return NULL; 3972 } 3973 3974 if (!intel_crtc_get_pipe_config(crtc_state)) { 3975 kfree(crtc_state); 3976 kfree(mode); 3977 return NULL; 3978 } 3979 3980 intel_encoder_get_config(encoder, crtc_state); 3981 3982 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode); 3983 3984 kfree(crtc_state); 3985 3986 return mode; 3987 } 3988 3989 static bool encoders_cloneable(const struct intel_encoder *a, 3990 const struct intel_encoder *b) 3991 { 3992 /* masks could be asymmetric, so check both ways */ 3993 return a == b || (a->cloneable & BIT(b->type) && 3994 b->cloneable & BIT(a->type)); 3995 } 3996 3997 static bool check_single_encoder_cloning(struct intel_atomic_state *state, 3998 struct intel_crtc *crtc, 3999 struct intel_encoder *encoder) 4000 { 4001 struct intel_encoder *source_encoder; 4002 struct drm_connector *connector; 4003 struct drm_connector_state *connector_state; 4004 int i; 4005 4006 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4007 if (connector_state->crtc != &crtc->base) 4008 continue; 4009 4010 source_encoder = 4011 to_intel_encoder(connector_state->best_encoder); 4012 if (!encoders_cloneable(encoder, source_encoder)) 4013 return false; 4014 } 4015 4016 return true; 4017 } 4018 4019 static int icl_add_linked_planes(struct intel_atomic_state *state) 4020 { 4021 struct intel_plane *plane, *linked; 4022 struct intel_plane_state *plane_state, *linked_plane_state; 4023 int i; 4024 4025 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4026 linked = plane_state->planar_linked_plane; 4027 4028 if (!linked) 4029 continue; 4030 4031 linked_plane_state = intel_atomic_get_plane_state(state, linked); 4032 if (IS_ERR(linked_plane_state)) 4033 return PTR_ERR(linked_plane_state); 4034 4035 drm_WARN_ON(state->base.dev, 4036 linked_plane_state->planar_linked_plane != plane); 4037 drm_WARN_ON(state->base.dev, 4038 linked_plane_state->planar_slave == plane_state->planar_slave); 4039 } 4040 4041 return 0; 4042 } 4043 4044 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state) 4045 { 4046 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4047 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4048 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 4049 struct intel_plane *plane, *linked; 4050 struct intel_plane_state *plane_state; 4051 int i; 4052 4053 if (DISPLAY_VER(dev_priv) < 11) 4054 return 0; 4055 4056 /* 4057 * Destroy all old plane links and make the slave plane invisible 4058 * in the crtc_state->active_planes mask. 4059 */ 4060 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4061 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane) 4062 continue; 4063 4064 plane_state->planar_linked_plane = NULL; 4065 if (plane_state->planar_slave && !plane_state->uapi.visible) { 4066 crtc_state->enabled_planes &= ~BIT(plane->id); 4067 crtc_state->active_planes &= ~BIT(plane->id); 4068 crtc_state->update_planes |= BIT(plane->id); 4069 crtc_state->data_rate[plane->id] = 0; 4070 crtc_state->rel_data_rate[plane->id] = 0; 4071 } 4072 4073 plane_state->planar_slave = false; 4074 } 4075 4076 if (!crtc_state->nv12_planes) 4077 return 0; 4078 4079 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4080 struct intel_plane_state *linked_state = NULL; 4081 4082 if (plane->pipe != crtc->pipe || 4083 !(crtc_state->nv12_planes & BIT(plane->id))) 4084 continue; 4085 4086 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) { 4087 if (!icl_is_nv12_y_plane(dev_priv, linked->id)) 4088 continue; 4089 4090 if (crtc_state->active_planes & BIT(linked->id)) 4091 continue; 4092 4093 linked_state = intel_atomic_get_plane_state(state, linked); 4094 if (IS_ERR(linked_state)) 4095 return PTR_ERR(linked_state); 4096 4097 break; 4098 } 4099 4100 if (!linked_state) { 4101 drm_dbg_kms(&dev_priv->drm, 4102 "Need %d free Y planes for planar YUV\n", 4103 hweight8(crtc_state->nv12_planes)); 4104 4105 return -EINVAL; 4106 } 4107 4108 plane_state->planar_linked_plane = linked; 4109 4110 linked_state->planar_slave = true; 4111 linked_state->planar_linked_plane = plane; 4112 crtc_state->enabled_planes |= BIT(linked->id); 4113 crtc_state->active_planes |= BIT(linked->id); 4114 crtc_state->update_planes |= BIT(linked->id); 4115 crtc_state->data_rate[linked->id] = 4116 crtc_state->data_rate_y[plane->id]; 4117 crtc_state->rel_data_rate[linked->id] = 4118 crtc_state->rel_data_rate_y[plane->id]; 4119 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n", 4120 linked->base.name, plane->base.name); 4121 4122 /* Copy parameters to slave plane */ 4123 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE; 4124 linked_state->color_ctl = plane_state->color_ctl; 4125 linked_state->view = plane_state->view; 4126 linked_state->decrypt = plane_state->decrypt; 4127 4128 intel_plane_copy_hw_state(linked_state, plane_state); 4129 linked_state->uapi.src = plane_state->uapi.src; 4130 linked_state->uapi.dst = plane_state->uapi.dst; 4131 4132 if (icl_is_hdr_plane(dev_priv, plane->id)) { 4133 if (linked->id == PLANE_SPRITE5) 4134 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL; 4135 else if (linked->id == PLANE_SPRITE4) 4136 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL; 4137 else if (linked->id == PLANE_SPRITE3) 4138 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL; 4139 else if (linked->id == PLANE_SPRITE2) 4140 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL; 4141 else 4142 MISSING_CASE(linked->id); 4143 } 4144 } 4145 4146 return 0; 4147 } 4148 4149 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state) 4150 { 4151 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 4152 struct intel_atomic_state *state = 4153 to_intel_atomic_state(new_crtc_state->uapi.state); 4154 const struct intel_crtc_state *old_crtc_state = 4155 intel_atomic_get_old_crtc_state(state, crtc); 4156 4157 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes; 4158 } 4159 4160 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) 4161 { 4162 const struct drm_display_mode *pipe_mode = 4163 &crtc_state->hw.pipe_mode; 4164 int linetime_wm; 4165 4166 if (!crtc_state->hw.enable) 4167 return 0; 4168 4169 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4170 pipe_mode->crtc_clock); 4171 4172 return min(linetime_wm, 0x1ff); 4173 } 4174 4175 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, 4176 const struct intel_cdclk_state *cdclk_state) 4177 { 4178 const struct drm_display_mode *pipe_mode = 4179 &crtc_state->hw.pipe_mode; 4180 int linetime_wm; 4181 4182 if (!crtc_state->hw.enable) 4183 return 0; 4184 4185 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4186 cdclk_state->logical.cdclk); 4187 4188 return min(linetime_wm, 0x1ff); 4189 } 4190 4191 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) 4192 { 4193 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4194 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4195 const struct drm_display_mode *pipe_mode = 4196 &crtc_state->hw.pipe_mode; 4197 int linetime_wm; 4198 4199 if (!crtc_state->hw.enable) 4200 return 0; 4201 4202 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8, 4203 crtc_state->pixel_rate); 4204 4205 /* Display WA #1135: BXT:ALL GLK:ALL */ 4206 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 4207 skl_watermark_ipc_enabled(dev_priv)) 4208 linetime_wm /= 2; 4209 4210 return min(linetime_wm, 0x1ff); 4211 } 4212 4213 static int hsw_compute_linetime_wm(struct intel_atomic_state *state, 4214 struct intel_crtc *crtc) 4215 { 4216 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4217 struct intel_crtc_state *crtc_state = 4218 intel_atomic_get_new_crtc_state(state, crtc); 4219 const struct intel_cdclk_state *cdclk_state; 4220 4221 if (DISPLAY_VER(dev_priv) >= 9) 4222 crtc_state->linetime = skl_linetime_wm(crtc_state); 4223 else 4224 crtc_state->linetime = hsw_linetime_wm(crtc_state); 4225 4226 if (!hsw_crtc_supports_ips(crtc)) 4227 return 0; 4228 4229 cdclk_state = intel_atomic_get_cdclk_state(state); 4230 if (IS_ERR(cdclk_state)) 4231 return PTR_ERR(cdclk_state); 4232 4233 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state, 4234 cdclk_state); 4235 4236 return 0; 4237 } 4238 4239 static int intel_crtc_atomic_check(struct intel_atomic_state *state, 4240 struct intel_crtc *crtc) 4241 { 4242 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4243 struct intel_crtc_state *crtc_state = 4244 intel_atomic_get_new_crtc_state(state, crtc); 4245 int ret; 4246 4247 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) && 4248 intel_crtc_needs_modeset(crtc_state) && 4249 !crtc_state->hw.active) 4250 crtc_state->update_wm_post = true; 4251 4252 if (intel_crtc_needs_modeset(crtc_state)) { 4253 ret = intel_dpll_crtc_get_shared_dpll(state, crtc); 4254 if (ret) 4255 return ret; 4256 } 4257 4258 /* 4259 * May need to update pipe gamma enable bits 4260 * when C8 planes are getting enabled/disabled. 4261 */ 4262 if (c8_planes_changed(crtc_state)) 4263 crtc_state->uapi.color_mgmt_changed = true; 4264 4265 if (intel_crtc_needs_color_update(crtc_state)) { 4266 ret = intel_color_check(crtc_state); 4267 if (ret) 4268 return ret; 4269 } 4270 4271 ret = intel_compute_pipe_wm(state, crtc); 4272 if (ret) { 4273 drm_dbg_kms(&dev_priv->drm, 4274 "Target pipe watermarks are invalid\n"); 4275 return ret; 4276 } 4277 4278 /* 4279 * Calculate 'intermediate' watermarks that satisfy both the 4280 * old state and the new state. We can program these 4281 * immediately. 4282 */ 4283 ret = intel_compute_intermediate_wm(state, crtc); 4284 if (ret) { 4285 drm_dbg_kms(&dev_priv->drm, 4286 "No valid intermediate pipe watermarks are possible\n"); 4287 return ret; 4288 } 4289 4290 if (DISPLAY_VER(dev_priv) >= 9) { 4291 if (intel_crtc_needs_modeset(crtc_state) || 4292 intel_crtc_needs_fastset(crtc_state)) { 4293 ret = skl_update_scaler_crtc(crtc_state); 4294 if (ret) 4295 return ret; 4296 } 4297 4298 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state); 4299 if (ret) 4300 return ret; 4301 } 4302 4303 if (HAS_IPS(dev_priv)) { 4304 ret = hsw_ips_compute_config(state, crtc); 4305 if (ret) 4306 return ret; 4307 } 4308 4309 if (DISPLAY_VER(dev_priv) >= 9 || 4310 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 4311 ret = hsw_compute_linetime_wm(state, crtc); 4312 if (ret) 4313 return ret; 4314 4315 } 4316 4317 ret = intel_psr2_sel_fetch_update(state, crtc); 4318 if (ret) 4319 return ret; 4320 4321 return 0; 4322 } 4323 4324 static int 4325 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state, 4326 struct intel_crtc_state *crtc_state) 4327 { 4328 struct drm_connector *connector = conn_state->connector; 4329 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 4330 const struct drm_display_info *info = &connector->display_info; 4331 int bpp; 4332 4333 switch (conn_state->max_bpc) { 4334 case 6 ... 7: 4335 bpp = 6 * 3; 4336 break; 4337 case 8 ... 9: 4338 bpp = 8 * 3; 4339 break; 4340 case 10 ... 11: 4341 bpp = 10 * 3; 4342 break; 4343 case 12 ... 16: 4344 bpp = 12 * 3; 4345 break; 4346 default: 4347 MISSING_CASE(conn_state->max_bpc); 4348 return -EINVAL; 4349 } 4350 4351 if (bpp < crtc_state->pipe_bpp) { 4352 drm_dbg_kms(&i915->drm, 4353 "[CONNECTOR:%d:%s] Limiting display bpp to %d " 4354 "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n", 4355 connector->base.id, connector->name, 4356 bpp, 3 * info->bpc, 4357 3 * conn_state->max_requested_bpc, 4358 crtc_state->pipe_bpp); 4359 4360 crtc_state->pipe_bpp = bpp; 4361 } 4362 4363 return 0; 4364 } 4365 4366 static int 4367 compute_baseline_pipe_bpp(struct intel_atomic_state *state, 4368 struct intel_crtc *crtc) 4369 { 4370 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4371 struct intel_crtc_state *crtc_state = 4372 intel_atomic_get_new_crtc_state(state, crtc); 4373 struct drm_connector *connector; 4374 struct drm_connector_state *connector_state; 4375 int bpp, i; 4376 4377 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 4378 IS_CHERRYVIEW(dev_priv))) 4379 bpp = 10*3; 4380 else if (DISPLAY_VER(dev_priv) >= 5) 4381 bpp = 12*3; 4382 else 4383 bpp = 8*3; 4384 4385 crtc_state->pipe_bpp = bpp; 4386 4387 /* Clamp display bpp to connector max bpp */ 4388 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4389 int ret; 4390 4391 if (connector_state->crtc != &crtc->base) 4392 continue; 4393 4394 ret = compute_sink_pipe_bpp(connector_state, crtc_state); 4395 if (ret) 4396 return ret; 4397 } 4398 4399 return 0; 4400 } 4401 4402 static bool check_digital_port_conflicts(struct intel_atomic_state *state) 4403 { 4404 struct drm_device *dev = state->base.dev; 4405 struct drm_connector *connector; 4406 struct drm_connector_list_iter conn_iter; 4407 unsigned int used_ports = 0; 4408 unsigned int used_mst_ports = 0; 4409 bool ret = true; 4410 4411 /* 4412 * We're going to peek into connector->state, 4413 * hence connection_mutex must be held. 4414 */ 4415 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex); 4416 4417 /* 4418 * Walk the connector list instead of the encoder 4419 * list to detect the problem on ddi platforms 4420 * where there's just one encoder per digital port. 4421 */ 4422 drm_connector_list_iter_begin(dev, &conn_iter); 4423 drm_for_each_connector_iter(connector, &conn_iter) { 4424 struct drm_connector_state *connector_state; 4425 struct intel_encoder *encoder; 4426 4427 connector_state = 4428 drm_atomic_get_new_connector_state(&state->base, 4429 connector); 4430 if (!connector_state) 4431 connector_state = connector->state; 4432 4433 if (!connector_state->best_encoder) 4434 continue; 4435 4436 encoder = to_intel_encoder(connector_state->best_encoder); 4437 4438 drm_WARN_ON(dev, !connector_state->crtc); 4439 4440 switch (encoder->type) { 4441 case INTEL_OUTPUT_DDI: 4442 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev)))) 4443 break; 4444 fallthrough; 4445 case INTEL_OUTPUT_DP: 4446 case INTEL_OUTPUT_HDMI: 4447 case INTEL_OUTPUT_EDP: 4448 /* the same port mustn't appear more than once */ 4449 if (used_ports & BIT(encoder->port)) 4450 ret = false; 4451 4452 used_ports |= BIT(encoder->port); 4453 break; 4454 case INTEL_OUTPUT_DP_MST: 4455 used_mst_ports |= 4456 1 << encoder->port; 4457 break; 4458 default: 4459 break; 4460 } 4461 } 4462 drm_connector_list_iter_end(&conn_iter); 4463 4464 /* can't mix MST and SST/HDMI on the same port */ 4465 if (used_ports & used_mst_ports) 4466 return false; 4467 4468 return ret; 4469 } 4470 4471 static void 4472 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state, 4473 struct intel_crtc *crtc) 4474 { 4475 struct intel_crtc_state *crtc_state = 4476 intel_atomic_get_new_crtc_state(state, crtc); 4477 4478 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 4479 4480 drm_property_replace_blob(&crtc_state->hw.degamma_lut, 4481 crtc_state->uapi.degamma_lut); 4482 drm_property_replace_blob(&crtc_state->hw.gamma_lut, 4483 crtc_state->uapi.gamma_lut); 4484 drm_property_replace_blob(&crtc_state->hw.ctm, 4485 crtc_state->uapi.ctm); 4486 } 4487 4488 static void 4489 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state, 4490 struct intel_crtc *crtc) 4491 { 4492 struct intel_crtc_state *crtc_state = 4493 intel_atomic_get_new_crtc_state(state, crtc); 4494 4495 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 4496 4497 crtc_state->hw.enable = crtc_state->uapi.enable; 4498 crtc_state->hw.active = crtc_state->uapi.active; 4499 drm_mode_copy(&crtc_state->hw.mode, 4500 &crtc_state->uapi.mode); 4501 drm_mode_copy(&crtc_state->hw.adjusted_mode, 4502 &crtc_state->uapi.adjusted_mode); 4503 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter; 4504 4505 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 4506 } 4507 4508 static void 4509 copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state, 4510 struct intel_crtc *slave_crtc) 4511 { 4512 struct intel_crtc_state *slave_crtc_state = 4513 intel_atomic_get_new_crtc_state(state, slave_crtc); 4514 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 4515 const struct intel_crtc_state *master_crtc_state = 4516 intel_atomic_get_new_crtc_state(state, master_crtc); 4517 4518 drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut, 4519 master_crtc_state->hw.degamma_lut); 4520 drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut, 4521 master_crtc_state->hw.gamma_lut); 4522 drm_property_replace_blob(&slave_crtc_state->hw.ctm, 4523 master_crtc_state->hw.ctm); 4524 4525 slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed; 4526 } 4527 4528 static int 4529 copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state, 4530 struct intel_crtc *slave_crtc) 4531 { 4532 struct intel_crtc_state *slave_crtc_state = 4533 intel_atomic_get_new_crtc_state(state, slave_crtc); 4534 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 4535 const struct intel_crtc_state *master_crtc_state = 4536 intel_atomic_get_new_crtc_state(state, master_crtc); 4537 struct intel_crtc_state *saved_state; 4538 4539 WARN_ON(master_crtc_state->bigjoiner_pipes != 4540 slave_crtc_state->bigjoiner_pipes); 4541 4542 saved_state = kmemdup(master_crtc_state, sizeof(*saved_state), GFP_KERNEL); 4543 if (!saved_state) 4544 return -ENOMEM; 4545 4546 /* preserve some things from the slave's original crtc state */ 4547 saved_state->uapi = slave_crtc_state->uapi; 4548 saved_state->scaler_state = slave_crtc_state->scaler_state; 4549 saved_state->shared_dpll = slave_crtc_state->shared_dpll; 4550 saved_state->dpll_hw_state = slave_crtc_state->dpll_hw_state; 4551 saved_state->crc_enabled = slave_crtc_state->crc_enabled; 4552 4553 intel_crtc_free_hw_state(slave_crtc_state); 4554 memcpy(slave_crtc_state, saved_state, sizeof(*slave_crtc_state)); 4555 kfree(saved_state); 4556 4557 /* Re-init hw state */ 4558 memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw)); 4559 slave_crtc_state->hw.enable = master_crtc_state->hw.enable; 4560 slave_crtc_state->hw.active = master_crtc_state->hw.active; 4561 drm_mode_copy(&slave_crtc_state->hw.mode, 4562 &master_crtc_state->hw.mode); 4563 drm_mode_copy(&slave_crtc_state->hw.pipe_mode, 4564 &master_crtc_state->hw.pipe_mode); 4565 drm_mode_copy(&slave_crtc_state->hw.adjusted_mode, 4566 &master_crtc_state->hw.adjusted_mode); 4567 slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter; 4568 4569 copy_bigjoiner_crtc_state_nomodeset(state, slave_crtc); 4570 4571 slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed; 4572 slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed; 4573 slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed; 4574 4575 WARN_ON(master_crtc_state->bigjoiner_pipes != 4576 slave_crtc_state->bigjoiner_pipes); 4577 4578 return 0; 4579 } 4580 4581 static int 4582 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state, 4583 struct intel_crtc *crtc) 4584 { 4585 struct intel_crtc_state *crtc_state = 4586 intel_atomic_get_new_crtc_state(state, crtc); 4587 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4588 struct intel_crtc_state *saved_state; 4589 4590 saved_state = intel_crtc_state_alloc(crtc); 4591 if (!saved_state) 4592 return -ENOMEM; 4593 4594 /* free the old crtc_state->hw members */ 4595 intel_crtc_free_hw_state(crtc_state); 4596 4597 /* FIXME: before the switch to atomic started, a new pipe_config was 4598 * kzalloc'd. Code that depends on any field being zero should be 4599 * fixed, so that the crtc_state can be safely duplicated. For now, 4600 * only fields that are know to not cause problems are preserved. */ 4601 4602 saved_state->uapi = crtc_state->uapi; 4603 saved_state->inherited = crtc_state->inherited; 4604 saved_state->scaler_state = crtc_state->scaler_state; 4605 saved_state->shared_dpll = crtc_state->shared_dpll; 4606 saved_state->dpll_hw_state = crtc_state->dpll_hw_state; 4607 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, 4608 sizeof(saved_state->icl_port_dplls)); 4609 saved_state->crc_enabled = crtc_state->crc_enabled; 4610 if (IS_G4X(dev_priv) || 4611 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 4612 saved_state->wm = crtc_state->wm; 4613 4614 memcpy(crtc_state, saved_state, sizeof(*crtc_state)); 4615 kfree(saved_state); 4616 4617 intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc); 4618 4619 return 0; 4620 } 4621 4622 static int 4623 intel_modeset_pipe_config(struct intel_atomic_state *state, 4624 struct intel_crtc *crtc) 4625 { 4626 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4627 struct intel_crtc_state *crtc_state = 4628 intel_atomic_get_new_crtc_state(state, crtc); 4629 struct drm_connector *connector; 4630 struct drm_connector_state *connector_state; 4631 int pipe_src_w, pipe_src_h; 4632 int base_bpp, ret, i; 4633 bool retry = true; 4634 4635 crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe; 4636 4637 crtc_state->framestart_delay = 1; 4638 4639 /* 4640 * Sanitize sync polarity flags based on requested ones. If neither 4641 * positive or negative polarity is requested, treat this as meaning 4642 * negative polarity. 4643 */ 4644 if (!(crtc_state->hw.adjusted_mode.flags & 4645 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) 4646 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; 4647 4648 if (!(crtc_state->hw.adjusted_mode.flags & 4649 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 4650 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; 4651 4652 ret = compute_baseline_pipe_bpp(state, crtc); 4653 if (ret) 4654 return ret; 4655 4656 base_bpp = crtc_state->pipe_bpp; 4657 4658 /* 4659 * Determine the real pipe dimensions. Note that stereo modes can 4660 * increase the actual pipe size due to the frame doubling and 4661 * insertion of additional space for blanks between the frame. This 4662 * is stored in the crtc timings. We use the requested mode to do this 4663 * computation to clearly distinguish it from the adjusted mode, which 4664 * can be changed by the connectors in the below retry loop. 4665 */ 4666 drm_mode_get_hv_timing(&crtc_state->hw.mode, 4667 &pipe_src_w, &pipe_src_h); 4668 drm_rect_init(&crtc_state->pipe_src, 0, 0, 4669 pipe_src_w, pipe_src_h); 4670 4671 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4672 struct intel_encoder *encoder = 4673 to_intel_encoder(connector_state->best_encoder); 4674 4675 if (connector_state->crtc != &crtc->base) 4676 continue; 4677 4678 if (!check_single_encoder_cloning(state, crtc, encoder)) { 4679 drm_dbg_kms(&i915->drm, 4680 "[ENCODER:%d:%s] rejecting invalid cloning configuration\n", 4681 encoder->base.base.id, encoder->base.name); 4682 return -EINVAL; 4683 } 4684 4685 /* 4686 * Determine output_types before calling the .compute_config() 4687 * hooks so that the hooks can use this information safely. 4688 */ 4689 if (encoder->compute_output_type) 4690 crtc_state->output_types |= 4691 BIT(encoder->compute_output_type(encoder, crtc_state, 4692 connector_state)); 4693 else 4694 crtc_state->output_types |= BIT(encoder->type); 4695 } 4696 4697 encoder_retry: 4698 /* Ensure the port clock defaults are reset when retrying. */ 4699 crtc_state->port_clock = 0; 4700 crtc_state->pixel_multiplier = 1; 4701 4702 /* Fill in default crtc timings, allow encoders to overwrite them. */ 4703 drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode, 4704 CRTC_STEREO_DOUBLE); 4705 4706 /* Pass our mode to the connectors and the CRTC to give them a chance to 4707 * adjust it according to limitations or connector properties, and also 4708 * a chance to reject the mode entirely. 4709 */ 4710 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4711 struct intel_encoder *encoder = 4712 to_intel_encoder(connector_state->best_encoder); 4713 4714 if (connector_state->crtc != &crtc->base) 4715 continue; 4716 4717 ret = encoder->compute_config(encoder, crtc_state, 4718 connector_state); 4719 if (ret == -EDEADLK) 4720 return ret; 4721 if (ret < 0) { 4722 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n", 4723 encoder->base.base.id, encoder->base.name, ret); 4724 return ret; 4725 } 4726 } 4727 4728 /* Set default port clock if not overwritten by the encoder. Needs to be 4729 * done afterwards in case the encoder adjusts the mode. */ 4730 if (!crtc_state->port_clock) 4731 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock 4732 * crtc_state->pixel_multiplier; 4733 4734 ret = intel_crtc_compute_config(state, crtc); 4735 if (ret == -EDEADLK) 4736 return ret; 4737 if (ret == -EAGAIN) { 4738 if (drm_WARN(&i915->drm, !retry, 4739 "[CRTC:%d:%s] loop in pipe configuration computation\n", 4740 crtc->base.base.id, crtc->base.name)) 4741 return -EINVAL; 4742 4743 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] bw constrained, retrying\n", 4744 crtc->base.base.id, crtc->base.name); 4745 retry = false; 4746 goto encoder_retry; 4747 } 4748 if (ret < 0) { 4749 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n", 4750 crtc->base.base.id, crtc->base.name, ret); 4751 return ret; 4752 } 4753 4754 /* Dithering seems to not pass-through bits correctly when it should, so 4755 * only enable it on 6bpc panels and when its not a compliance 4756 * test requesting 6bpc video pattern. 4757 */ 4758 crtc_state->dither = (crtc_state->pipe_bpp == 6*3) && 4759 !crtc_state->dither_force_disable; 4760 drm_dbg_kms(&i915->drm, 4761 "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n", 4762 crtc->base.base.id, crtc->base.name, 4763 base_bpp, crtc_state->pipe_bpp, crtc_state->dither); 4764 4765 return 0; 4766 } 4767 4768 static int 4769 intel_modeset_pipe_config_late(struct intel_atomic_state *state, 4770 struct intel_crtc *crtc) 4771 { 4772 struct intel_crtc_state *crtc_state = 4773 intel_atomic_get_new_crtc_state(state, crtc); 4774 struct drm_connector_state *conn_state; 4775 struct drm_connector *connector; 4776 int i; 4777 4778 intel_bigjoiner_adjust_pipe_src(crtc_state); 4779 4780 for_each_new_connector_in_state(&state->base, connector, 4781 conn_state, i) { 4782 struct intel_encoder *encoder = 4783 to_intel_encoder(conn_state->best_encoder); 4784 int ret; 4785 4786 if (conn_state->crtc != &crtc->base || 4787 !encoder->compute_config_late) 4788 continue; 4789 4790 ret = encoder->compute_config_late(encoder, crtc_state, 4791 conn_state); 4792 if (ret) 4793 return ret; 4794 } 4795 4796 return 0; 4797 } 4798 4799 bool intel_fuzzy_clock_check(int clock1, int clock2) 4800 { 4801 int diff; 4802 4803 if (clock1 == clock2) 4804 return true; 4805 4806 if (!clock1 || !clock2) 4807 return false; 4808 4809 diff = abs(clock1 - clock2); 4810 4811 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) 4812 return true; 4813 4814 return false; 4815 } 4816 4817 static bool 4818 intel_compare_link_m_n(const struct intel_link_m_n *m_n, 4819 const struct intel_link_m_n *m2_n2) 4820 { 4821 return m_n->tu == m2_n2->tu && 4822 m_n->data_m == m2_n2->data_m && 4823 m_n->data_n == m2_n2->data_n && 4824 m_n->link_m == m2_n2->link_m && 4825 m_n->link_n == m2_n2->link_n; 4826 } 4827 4828 static bool 4829 intel_compare_infoframe(const union hdmi_infoframe *a, 4830 const union hdmi_infoframe *b) 4831 { 4832 return memcmp(a, b, sizeof(*a)) == 0; 4833 } 4834 4835 static bool 4836 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a, 4837 const struct drm_dp_vsc_sdp *b) 4838 { 4839 return memcmp(a, b, sizeof(*a)) == 0; 4840 } 4841 4842 static bool 4843 intel_compare_buffer(const u8 *a, const u8 *b, size_t len) 4844 { 4845 return memcmp(a, b, len) == 0; 4846 } 4847 4848 static void 4849 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv, 4850 bool fastset, const char *name, 4851 const union hdmi_infoframe *a, 4852 const union hdmi_infoframe *b) 4853 { 4854 if (fastset) { 4855 if (!drm_debug_enabled(DRM_UT_KMS)) 4856 return; 4857 4858 drm_dbg_kms(&dev_priv->drm, 4859 "fastset mismatch in %s infoframe\n", name); 4860 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 4861 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a); 4862 drm_dbg_kms(&dev_priv->drm, "found:\n"); 4863 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b); 4864 } else { 4865 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name); 4866 drm_err(&dev_priv->drm, "expected:\n"); 4867 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a); 4868 drm_err(&dev_priv->drm, "found:\n"); 4869 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b); 4870 } 4871 } 4872 4873 static void 4874 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv, 4875 bool fastset, const char *name, 4876 const struct drm_dp_vsc_sdp *a, 4877 const struct drm_dp_vsc_sdp *b) 4878 { 4879 if (fastset) { 4880 if (!drm_debug_enabled(DRM_UT_KMS)) 4881 return; 4882 4883 drm_dbg_kms(&dev_priv->drm, 4884 "fastset mismatch in %s dp sdp\n", name); 4885 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 4886 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a); 4887 drm_dbg_kms(&dev_priv->drm, "found:\n"); 4888 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b); 4889 } else { 4890 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name); 4891 drm_err(&dev_priv->drm, "expected:\n"); 4892 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a); 4893 drm_err(&dev_priv->drm, "found:\n"); 4894 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b); 4895 } 4896 } 4897 4898 /* Returns the length up to and including the last differing byte */ 4899 static size_t 4900 memcmp_diff_len(const u8 *a, const u8 *b, size_t len) 4901 { 4902 int i; 4903 4904 for (i = len - 1; i >= 0; i--) { 4905 if (a[i] != b[i]) 4906 return i + 1; 4907 } 4908 4909 return 0; 4910 } 4911 4912 static void 4913 pipe_config_buffer_mismatch(struct drm_i915_private *dev_priv, 4914 bool fastset, const char *name, 4915 const u8 *a, const u8 *b, size_t len) 4916 { 4917 if (fastset) { 4918 if (!drm_debug_enabled(DRM_UT_KMS)) 4919 return; 4920 4921 /* only dump up to the last difference */ 4922 len = memcmp_diff_len(a, b, len); 4923 4924 drm_dbg_kms(&dev_priv->drm, 4925 "fastset mismatch in %s buffer\n", name); 4926 print_hex_dump(KERN_DEBUG, "expected: ", DUMP_PREFIX_NONE, 4927 16, 0, a, len, false); 4928 print_hex_dump(KERN_DEBUG, "found: ", DUMP_PREFIX_NONE, 4929 16, 0, b, len, false); 4930 } else { 4931 /* only dump up to the last difference */ 4932 len = memcmp_diff_len(a, b, len); 4933 4934 drm_err(&dev_priv->drm, "mismatch in %s buffer\n", name); 4935 print_hex_dump(KERN_ERR, "expected: ", DUMP_PREFIX_NONE, 4936 16, 0, a, len, false); 4937 print_hex_dump(KERN_ERR, "found: ", DUMP_PREFIX_NONE, 4938 16, 0, b, len, false); 4939 } 4940 } 4941 4942 static void __printf(4, 5) 4943 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc, 4944 const char *name, const char *format, ...) 4945 { 4946 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4947 struct va_format vaf; 4948 va_list args; 4949 4950 va_start(args, format); 4951 vaf.fmt = format; 4952 vaf.va = &args; 4953 4954 if (fastset) 4955 drm_dbg_kms(&i915->drm, 4956 "[CRTC:%d:%s] fastset mismatch in %s %pV\n", 4957 crtc->base.base.id, crtc->base.name, name, &vaf); 4958 else 4959 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n", 4960 crtc->base.base.id, crtc->base.name, name, &vaf); 4961 4962 va_end(args); 4963 } 4964 4965 static bool fastboot_enabled(struct drm_i915_private *dev_priv) 4966 { 4967 if (dev_priv->params.fastboot != -1) 4968 return dev_priv->params.fastboot; 4969 4970 /* Enable fastboot by default on Skylake and newer */ 4971 if (DISPLAY_VER(dev_priv) >= 9) 4972 return true; 4973 4974 /* Enable fastboot by default on VLV and CHV */ 4975 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 4976 return true; 4977 4978 /* Disabled by default on all others */ 4979 return false; 4980 } 4981 4982 bool 4983 intel_pipe_config_compare(const struct intel_crtc_state *current_config, 4984 const struct intel_crtc_state *pipe_config, 4985 bool fastset) 4986 { 4987 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev); 4988 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4989 bool ret = true; 4990 bool fixup_inherited = fastset && 4991 current_config->inherited && !pipe_config->inherited; 4992 4993 if (fixup_inherited && !fastboot_enabled(dev_priv)) { 4994 drm_dbg_kms(&dev_priv->drm, 4995 "initial modeset and fastboot not set\n"); 4996 ret = false; 4997 } 4998 4999 #define PIPE_CONF_CHECK_X(name) do { \ 5000 if (current_config->name != pipe_config->name) { \ 5001 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5002 "(expected 0x%08x, found 0x%08x)", \ 5003 current_config->name, \ 5004 pipe_config->name); \ 5005 ret = false; \ 5006 } \ 5007 } while (0) 5008 5009 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \ 5010 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \ 5011 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5012 "(expected 0x%08x, found 0x%08x)", \ 5013 current_config->name & (mask), \ 5014 pipe_config->name & (mask)); \ 5015 ret = false; \ 5016 } \ 5017 } while (0) 5018 5019 #define PIPE_CONF_CHECK_I(name) do { \ 5020 if (current_config->name != pipe_config->name) { \ 5021 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5022 "(expected %i, found %i)", \ 5023 current_config->name, \ 5024 pipe_config->name); \ 5025 ret = false; \ 5026 } \ 5027 } while (0) 5028 5029 #define PIPE_CONF_CHECK_BOOL(name) do { \ 5030 if (current_config->name != pipe_config->name) { \ 5031 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5032 "(expected %s, found %s)", \ 5033 str_yes_no(current_config->name), \ 5034 str_yes_no(pipe_config->name)); \ 5035 ret = false; \ 5036 } \ 5037 } while (0) 5038 5039 /* 5040 * Checks state where we only read out the enabling, but not the entire 5041 * state itself (like full infoframes or ELD for audio). These states 5042 * require a full modeset on bootup to fix up. 5043 */ 5044 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \ 5045 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \ 5046 PIPE_CONF_CHECK_BOOL(name); \ 5047 } else { \ 5048 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5049 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \ 5050 str_yes_no(current_config->name), \ 5051 str_yes_no(pipe_config->name)); \ 5052 ret = false; \ 5053 } \ 5054 } while (0) 5055 5056 #define PIPE_CONF_CHECK_P(name) do { \ 5057 if (current_config->name != pipe_config->name) { \ 5058 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5059 "(expected %p, found %p)", \ 5060 current_config->name, \ 5061 pipe_config->name); \ 5062 ret = false; \ 5063 } \ 5064 } while (0) 5065 5066 #define PIPE_CONF_CHECK_M_N(name) do { \ 5067 if (!intel_compare_link_m_n(¤t_config->name, \ 5068 &pipe_config->name)) { \ 5069 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5070 "(expected tu %i data %i/%i link %i/%i, " \ 5071 "found tu %i, data %i/%i link %i/%i)", \ 5072 current_config->name.tu, \ 5073 current_config->name.data_m, \ 5074 current_config->name.data_n, \ 5075 current_config->name.link_m, \ 5076 current_config->name.link_n, \ 5077 pipe_config->name.tu, \ 5078 pipe_config->name.data_m, \ 5079 pipe_config->name.data_n, \ 5080 pipe_config->name.link_m, \ 5081 pipe_config->name.link_n); \ 5082 ret = false; \ 5083 } \ 5084 } while (0) 5085 5086 #define PIPE_CONF_CHECK_TIMINGS(name) do { \ 5087 PIPE_CONF_CHECK_I(name.crtc_hdisplay); \ 5088 PIPE_CONF_CHECK_I(name.crtc_htotal); \ 5089 PIPE_CONF_CHECK_I(name.crtc_hblank_start); \ 5090 PIPE_CONF_CHECK_I(name.crtc_hblank_end); \ 5091 PIPE_CONF_CHECK_I(name.crtc_hsync_start); \ 5092 PIPE_CONF_CHECK_I(name.crtc_hsync_end); \ 5093 PIPE_CONF_CHECK_I(name.crtc_vdisplay); \ 5094 PIPE_CONF_CHECK_I(name.crtc_vtotal); \ 5095 PIPE_CONF_CHECK_I(name.crtc_vblank_start); \ 5096 PIPE_CONF_CHECK_I(name.crtc_vblank_end); \ 5097 PIPE_CONF_CHECK_I(name.crtc_vsync_start); \ 5098 PIPE_CONF_CHECK_I(name.crtc_vsync_end); \ 5099 } while (0) 5100 5101 #define PIPE_CONF_CHECK_RECT(name) do { \ 5102 PIPE_CONF_CHECK_I(name.x1); \ 5103 PIPE_CONF_CHECK_I(name.x2); \ 5104 PIPE_CONF_CHECK_I(name.y1); \ 5105 PIPE_CONF_CHECK_I(name.y2); \ 5106 } while (0) 5107 5108 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \ 5109 if ((current_config->name ^ pipe_config->name) & (mask)) { \ 5110 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5111 "(%x) (expected %i, found %i)", \ 5112 (mask), \ 5113 current_config->name & (mask), \ 5114 pipe_config->name & (mask)); \ 5115 ret = false; \ 5116 } \ 5117 } while (0) 5118 5119 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \ 5120 if (!intel_compare_infoframe(¤t_config->infoframes.name, \ 5121 &pipe_config->infoframes.name)) { \ 5122 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \ 5123 ¤t_config->infoframes.name, \ 5124 &pipe_config->infoframes.name); \ 5125 ret = false; \ 5126 } \ 5127 } while (0) 5128 5129 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \ 5130 if (!current_config->has_psr && !pipe_config->has_psr && \ 5131 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \ 5132 &pipe_config->infoframes.name)) { \ 5133 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \ 5134 ¤t_config->infoframes.name, \ 5135 &pipe_config->infoframes.name); \ 5136 ret = false; \ 5137 } \ 5138 } while (0) 5139 5140 #define PIPE_CONF_CHECK_BUFFER(name, len) do { \ 5141 BUILD_BUG_ON(sizeof(current_config->name) != (len)); \ 5142 BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \ 5143 if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \ 5144 pipe_config_buffer_mismatch(dev_priv, fastset, __stringify(name), \ 5145 current_config->name, \ 5146 pipe_config->name, \ 5147 (len)); \ 5148 ret = false; \ 5149 } \ 5150 } while (0) 5151 5152 #define PIPE_CONF_CHECK_COLOR_LUT(lut, is_pre_csc_lut) do { \ 5153 if (current_config->gamma_mode == pipe_config->gamma_mode && \ 5154 !intel_color_lut_equal(current_config, \ 5155 current_config->lut, pipe_config->lut, \ 5156 is_pre_csc_lut)) { \ 5157 pipe_config_mismatch(fastset, crtc, __stringify(lut), \ 5158 "hw_state doesn't match sw_state"); \ 5159 ret = false; \ 5160 } \ 5161 } while (0) 5162 5163 #define PIPE_CONF_CHECK_CSC(name) do { \ 5164 PIPE_CONF_CHECK_X(name.preoff[0]); \ 5165 PIPE_CONF_CHECK_X(name.preoff[1]); \ 5166 PIPE_CONF_CHECK_X(name.preoff[2]); \ 5167 PIPE_CONF_CHECK_X(name.coeff[0]); \ 5168 PIPE_CONF_CHECK_X(name.coeff[1]); \ 5169 PIPE_CONF_CHECK_X(name.coeff[2]); \ 5170 PIPE_CONF_CHECK_X(name.coeff[3]); \ 5171 PIPE_CONF_CHECK_X(name.coeff[4]); \ 5172 PIPE_CONF_CHECK_X(name.coeff[5]); \ 5173 PIPE_CONF_CHECK_X(name.coeff[6]); \ 5174 PIPE_CONF_CHECK_X(name.coeff[7]); \ 5175 PIPE_CONF_CHECK_X(name.coeff[8]); \ 5176 PIPE_CONF_CHECK_X(name.postoff[0]); \ 5177 PIPE_CONF_CHECK_X(name.postoff[1]); \ 5178 PIPE_CONF_CHECK_X(name.postoff[2]); \ 5179 } while (0) 5180 5181 #define PIPE_CONF_QUIRK(quirk) \ 5182 ((current_config->quirks | pipe_config->quirks) & (quirk)) 5183 5184 PIPE_CONF_CHECK_I(hw.enable); 5185 PIPE_CONF_CHECK_I(hw.active); 5186 5187 PIPE_CONF_CHECK_I(cpu_transcoder); 5188 PIPE_CONF_CHECK_I(mst_master_transcoder); 5189 5190 PIPE_CONF_CHECK_BOOL(has_pch_encoder); 5191 PIPE_CONF_CHECK_I(fdi_lanes); 5192 PIPE_CONF_CHECK_M_N(fdi_m_n); 5193 5194 PIPE_CONF_CHECK_I(lane_count); 5195 PIPE_CONF_CHECK_X(lane_lat_optim_mask); 5196 5197 if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) { 5198 if (!fastset || !pipe_config->seamless_m_n) 5199 PIPE_CONF_CHECK_M_N(dp_m_n); 5200 } else { 5201 PIPE_CONF_CHECK_M_N(dp_m_n); 5202 PIPE_CONF_CHECK_M_N(dp_m2_n2); 5203 } 5204 5205 PIPE_CONF_CHECK_X(output_types); 5206 5207 PIPE_CONF_CHECK_I(framestart_delay); 5208 PIPE_CONF_CHECK_I(msa_timing_delay); 5209 5210 PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode); 5211 PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode); 5212 5213 PIPE_CONF_CHECK_I(pixel_multiplier); 5214 5215 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5216 DRM_MODE_FLAG_INTERLACE); 5217 5218 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { 5219 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5220 DRM_MODE_FLAG_PHSYNC); 5221 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5222 DRM_MODE_FLAG_NHSYNC); 5223 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5224 DRM_MODE_FLAG_PVSYNC); 5225 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5226 DRM_MODE_FLAG_NVSYNC); 5227 } 5228 5229 PIPE_CONF_CHECK_I(output_format); 5230 PIPE_CONF_CHECK_BOOL(has_hdmi_sink); 5231 if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || 5232 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5233 PIPE_CONF_CHECK_BOOL(limited_color_range); 5234 5235 PIPE_CONF_CHECK_BOOL(hdmi_scrambling); 5236 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio); 5237 PIPE_CONF_CHECK_BOOL(has_infoframe); 5238 PIPE_CONF_CHECK_BOOL(fec_enable); 5239 5240 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio); 5241 PIPE_CONF_CHECK_BUFFER(eld, MAX_ELD_BYTES); 5242 5243 PIPE_CONF_CHECK_X(gmch_pfit.control); 5244 /* pfit ratios are autocomputed by the hw on gen4+ */ 5245 if (DISPLAY_VER(dev_priv) < 4) 5246 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); 5247 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); 5248 5249 /* 5250 * Changing the EDP transcoder input mux 5251 * (A_ONOFF vs. A_ON) requires a full modeset. 5252 */ 5253 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru); 5254 5255 if (!fastset) { 5256 PIPE_CONF_CHECK_RECT(pipe_src); 5257 5258 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled); 5259 PIPE_CONF_CHECK_RECT(pch_pfit.dst); 5260 5261 PIPE_CONF_CHECK_I(scaler_state.scaler_id); 5262 PIPE_CONF_CHECK_I(pixel_rate); 5263 5264 PIPE_CONF_CHECK_X(gamma_mode); 5265 if (IS_CHERRYVIEW(dev_priv)) 5266 PIPE_CONF_CHECK_X(cgm_mode); 5267 else 5268 PIPE_CONF_CHECK_X(csc_mode); 5269 PIPE_CONF_CHECK_BOOL(gamma_enable); 5270 PIPE_CONF_CHECK_BOOL(csc_enable); 5271 5272 PIPE_CONF_CHECK_I(linetime); 5273 PIPE_CONF_CHECK_I(ips_linetime); 5274 5275 PIPE_CONF_CHECK_COLOR_LUT(pre_csc_lut, true); 5276 PIPE_CONF_CHECK_COLOR_LUT(post_csc_lut, false); 5277 5278 PIPE_CONF_CHECK_CSC(csc); 5279 PIPE_CONF_CHECK_CSC(output_csc); 5280 5281 if (current_config->active_planes) { 5282 PIPE_CONF_CHECK_BOOL(has_psr); 5283 PIPE_CONF_CHECK_BOOL(has_psr2); 5284 PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); 5285 PIPE_CONF_CHECK_I(dc3co_exitline); 5286 } 5287 } 5288 5289 PIPE_CONF_CHECK_BOOL(double_wide); 5290 5291 if (dev_priv->display.dpll.mgr) { 5292 PIPE_CONF_CHECK_P(shared_dpll); 5293 5294 PIPE_CONF_CHECK_X(dpll_hw_state.dpll); 5295 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); 5296 PIPE_CONF_CHECK_X(dpll_hw_state.fp0); 5297 PIPE_CONF_CHECK_X(dpll_hw_state.fp1); 5298 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); 5299 PIPE_CONF_CHECK_X(dpll_hw_state.spll); 5300 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); 5301 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); 5302 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); 5303 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); 5304 PIPE_CONF_CHECK_X(dpll_hw_state.div0); 5305 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); 5306 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); 5307 PIPE_CONF_CHECK_X(dpll_hw_state.pll0); 5308 PIPE_CONF_CHECK_X(dpll_hw_state.pll1); 5309 PIPE_CONF_CHECK_X(dpll_hw_state.pll2); 5310 PIPE_CONF_CHECK_X(dpll_hw_state.pll3); 5311 PIPE_CONF_CHECK_X(dpll_hw_state.pll6); 5312 PIPE_CONF_CHECK_X(dpll_hw_state.pll8); 5313 PIPE_CONF_CHECK_X(dpll_hw_state.pll9); 5314 PIPE_CONF_CHECK_X(dpll_hw_state.pll10); 5315 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); 5316 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl); 5317 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1); 5318 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl); 5319 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0); 5320 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1); 5321 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf); 5322 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock); 5323 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc); 5324 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias); 5325 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias); 5326 } 5327 5328 PIPE_CONF_CHECK_X(dsi_pll.ctrl); 5329 PIPE_CONF_CHECK_X(dsi_pll.div); 5330 5331 if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5) 5332 PIPE_CONF_CHECK_I(pipe_bpp); 5333 5334 if (!fastset || !pipe_config->seamless_m_n) { 5335 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock); 5336 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock); 5337 } 5338 PIPE_CONF_CHECK_I(port_clock); 5339 5340 PIPE_CONF_CHECK_I(min_voltage_level); 5341 5342 if (current_config->has_psr || pipe_config->has_psr) 5343 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable, 5344 ~intel_hdmi_infoframe_enable(DP_SDP_VSC)); 5345 else 5346 PIPE_CONF_CHECK_X(infoframes.enable); 5347 5348 PIPE_CONF_CHECK_X(infoframes.gcp); 5349 PIPE_CONF_CHECK_INFOFRAME(avi); 5350 PIPE_CONF_CHECK_INFOFRAME(spd); 5351 PIPE_CONF_CHECK_INFOFRAME(hdmi); 5352 PIPE_CONF_CHECK_INFOFRAME(drm); 5353 PIPE_CONF_CHECK_DP_VSC_SDP(vsc); 5354 5355 PIPE_CONF_CHECK_X(sync_mode_slaves_mask); 5356 PIPE_CONF_CHECK_I(master_transcoder); 5357 PIPE_CONF_CHECK_X(bigjoiner_pipes); 5358 5359 PIPE_CONF_CHECK_I(dsc.compression_enable); 5360 PIPE_CONF_CHECK_I(dsc.dsc_split); 5361 PIPE_CONF_CHECK_I(dsc.compressed_bpp); 5362 5363 PIPE_CONF_CHECK_BOOL(splitter.enable); 5364 PIPE_CONF_CHECK_I(splitter.link_count); 5365 PIPE_CONF_CHECK_I(splitter.pixel_overlap); 5366 5367 if (!fastset) 5368 PIPE_CONF_CHECK_BOOL(vrr.enable); 5369 PIPE_CONF_CHECK_I(vrr.vmin); 5370 PIPE_CONF_CHECK_I(vrr.vmax); 5371 PIPE_CONF_CHECK_I(vrr.flipline); 5372 PIPE_CONF_CHECK_I(vrr.pipeline_full); 5373 PIPE_CONF_CHECK_I(vrr.guardband); 5374 5375 #undef PIPE_CONF_CHECK_X 5376 #undef PIPE_CONF_CHECK_I 5377 #undef PIPE_CONF_CHECK_BOOL 5378 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE 5379 #undef PIPE_CONF_CHECK_P 5380 #undef PIPE_CONF_CHECK_FLAGS 5381 #undef PIPE_CONF_CHECK_COLOR_LUT 5382 #undef PIPE_CONF_CHECK_TIMINGS 5383 #undef PIPE_CONF_CHECK_RECT 5384 #undef PIPE_CONF_QUIRK 5385 5386 return ret; 5387 } 5388 5389 static void 5390 intel_verify_planes(struct intel_atomic_state *state) 5391 { 5392 struct intel_plane *plane; 5393 const struct intel_plane_state *plane_state; 5394 int i; 5395 5396 for_each_new_intel_plane_in_state(state, plane, 5397 plane_state, i) 5398 assert_plane(plane, plane_state->planar_slave || 5399 plane_state->uapi.visible); 5400 } 5401 5402 int intel_modeset_all_pipes(struct intel_atomic_state *state, 5403 const char *reason) 5404 { 5405 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 5406 struct intel_crtc *crtc; 5407 5408 /* 5409 * Add all pipes to the state, and force 5410 * a modeset on all the active ones. 5411 */ 5412 for_each_intel_crtc(&dev_priv->drm, crtc) { 5413 struct intel_crtc_state *crtc_state; 5414 int ret; 5415 5416 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 5417 if (IS_ERR(crtc_state)) 5418 return PTR_ERR(crtc_state); 5419 5420 if (!crtc_state->hw.active || 5421 intel_crtc_needs_modeset(crtc_state)) 5422 continue; 5423 5424 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] Full modeset due to %s\n", 5425 crtc->base.base.id, crtc->base.name, reason); 5426 5427 crtc_state->uapi.mode_changed = true; 5428 crtc_state->update_pipe = false; 5429 5430 ret = drm_atomic_add_affected_connectors(&state->base, 5431 &crtc->base); 5432 if (ret) 5433 return ret; 5434 5435 ret = intel_dp_mst_add_topology_state_for_crtc(state, crtc); 5436 if (ret) 5437 return ret; 5438 5439 ret = intel_atomic_add_affected_planes(state, crtc); 5440 if (ret) 5441 return ret; 5442 5443 crtc_state->update_planes |= crtc_state->active_planes; 5444 crtc_state->async_flip_planes = 0; 5445 crtc_state->do_async_flip = false; 5446 } 5447 5448 return 0; 5449 } 5450 5451 /* 5452 * This implements the workaround described in the "notes" section of the mode 5453 * set sequence documentation. When going from no pipes or single pipe to 5454 * multiple pipes, and planes are enabled after the pipe, we need to wait at 5455 * least 2 vblanks on the first pipe before enabling planes on the second pipe. 5456 */ 5457 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state) 5458 { 5459 struct intel_crtc_state *crtc_state; 5460 struct intel_crtc *crtc; 5461 struct intel_crtc_state *first_crtc_state = NULL; 5462 struct intel_crtc_state *other_crtc_state = NULL; 5463 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; 5464 int i; 5465 5466 /* look at all crtc's that are going to be enabled in during modeset */ 5467 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5468 if (!crtc_state->hw.active || 5469 !intel_crtc_needs_modeset(crtc_state)) 5470 continue; 5471 5472 if (first_crtc_state) { 5473 other_crtc_state = crtc_state; 5474 break; 5475 } else { 5476 first_crtc_state = crtc_state; 5477 first_pipe = crtc->pipe; 5478 } 5479 } 5480 5481 /* No workaround needed? */ 5482 if (!first_crtc_state) 5483 return 0; 5484 5485 /* w/a possibly needed, check how many crtc's are already enabled. */ 5486 for_each_intel_crtc(state->base.dev, crtc) { 5487 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 5488 if (IS_ERR(crtc_state)) 5489 return PTR_ERR(crtc_state); 5490 5491 crtc_state->hsw_workaround_pipe = INVALID_PIPE; 5492 5493 if (!crtc_state->hw.active || 5494 intel_crtc_needs_modeset(crtc_state)) 5495 continue; 5496 5497 /* 2 or more enabled crtcs means no need for w/a */ 5498 if (enabled_pipe != INVALID_PIPE) 5499 return 0; 5500 5501 enabled_pipe = crtc->pipe; 5502 } 5503 5504 if (enabled_pipe != INVALID_PIPE) 5505 first_crtc_state->hsw_workaround_pipe = enabled_pipe; 5506 else if (other_crtc_state) 5507 other_crtc_state->hsw_workaround_pipe = first_pipe; 5508 5509 return 0; 5510 } 5511 5512 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 5513 u8 active_pipes) 5514 { 5515 const struct intel_crtc_state *crtc_state; 5516 struct intel_crtc *crtc; 5517 int i; 5518 5519 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5520 if (crtc_state->hw.active) 5521 active_pipes |= BIT(crtc->pipe); 5522 else 5523 active_pipes &= ~BIT(crtc->pipe); 5524 } 5525 5526 return active_pipes; 5527 } 5528 5529 static int intel_modeset_checks(struct intel_atomic_state *state) 5530 { 5531 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 5532 5533 state->modeset = true; 5534 5535 if (IS_HASWELL(dev_priv)) 5536 return hsw_mode_set_planes_workaround(state); 5537 5538 return 0; 5539 } 5540 5541 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state, 5542 struct intel_crtc_state *new_crtc_state) 5543 { 5544 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) 5545 return; 5546 5547 new_crtc_state->uapi.mode_changed = false; 5548 if (!intel_crtc_needs_modeset(new_crtc_state)) 5549 new_crtc_state->update_pipe = true; 5550 } 5551 5552 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state, 5553 struct intel_crtc *crtc, 5554 u8 plane_ids_mask) 5555 { 5556 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 5557 struct intel_plane *plane; 5558 5559 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 5560 struct intel_plane_state *plane_state; 5561 5562 if ((plane_ids_mask & BIT(plane->id)) == 0) 5563 continue; 5564 5565 plane_state = intel_atomic_get_plane_state(state, plane); 5566 if (IS_ERR(plane_state)) 5567 return PTR_ERR(plane_state); 5568 } 5569 5570 return 0; 5571 } 5572 5573 int intel_atomic_add_affected_planes(struct intel_atomic_state *state, 5574 struct intel_crtc *crtc) 5575 { 5576 const struct intel_crtc_state *old_crtc_state = 5577 intel_atomic_get_old_crtc_state(state, crtc); 5578 const struct intel_crtc_state *new_crtc_state = 5579 intel_atomic_get_new_crtc_state(state, crtc); 5580 5581 return intel_crtc_add_planes_to_state(state, crtc, 5582 old_crtc_state->enabled_planes | 5583 new_crtc_state->enabled_planes); 5584 } 5585 5586 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv) 5587 { 5588 /* See {hsw,vlv,ivb}_plane_ratio() */ 5589 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) || 5590 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) || 5591 IS_IVYBRIDGE(dev_priv); 5592 } 5593 5594 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state, 5595 struct intel_crtc *crtc, 5596 struct intel_crtc *other) 5597 { 5598 const struct intel_plane_state *plane_state; 5599 struct intel_plane *plane; 5600 u8 plane_ids = 0; 5601 int i; 5602 5603 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 5604 if (plane->pipe == crtc->pipe) 5605 plane_ids |= BIT(plane->id); 5606 } 5607 5608 return intel_crtc_add_planes_to_state(state, other, plane_ids); 5609 } 5610 5611 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state) 5612 { 5613 struct drm_i915_private *i915 = to_i915(state->base.dev); 5614 const struct intel_crtc_state *crtc_state; 5615 struct intel_crtc *crtc; 5616 int i; 5617 5618 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5619 struct intel_crtc *other; 5620 5621 for_each_intel_crtc_in_pipe_mask(&i915->drm, other, 5622 crtc_state->bigjoiner_pipes) { 5623 int ret; 5624 5625 if (crtc == other) 5626 continue; 5627 5628 ret = intel_crtc_add_bigjoiner_planes(state, crtc, other); 5629 if (ret) 5630 return ret; 5631 } 5632 } 5633 5634 return 0; 5635 } 5636 5637 static int intel_atomic_check_planes(struct intel_atomic_state *state) 5638 { 5639 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 5640 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 5641 struct intel_plane_state *plane_state; 5642 struct intel_plane *plane; 5643 struct intel_crtc *crtc; 5644 int i, ret; 5645 5646 ret = icl_add_linked_planes(state); 5647 if (ret) 5648 return ret; 5649 5650 ret = intel_bigjoiner_add_affected_planes(state); 5651 if (ret) 5652 return ret; 5653 5654 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 5655 ret = intel_plane_atomic_check(state, plane); 5656 if (ret) { 5657 drm_dbg_atomic(&dev_priv->drm, 5658 "[PLANE:%d:%s] atomic driver check failed\n", 5659 plane->base.base.id, plane->base.name); 5660 return ret; 5661 } 5662 } 5663 5664 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 5665 new_crtc_state, i) { 5666 u8 old_active_planes, new_active_planes; 5667 5668 ret = icl_check_nv12_planes(new_crtc_state); 5669 if (ret) 5670 return ret; 5671 5672 /* 5673 * On some platforms the number of active planes affects 5674 * the planes' minimum cdclk calculation. Add such planes 5675 * to the state before we compute the minimum cdclk. 5676 */ 5677 if (!active_planes_affects_min_cdclk(dev_priv)) 5678 continue; 5679 5680 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 5681 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 5682 5683 if (hweight8(old_active_planes) == hweight8(new_active_planes)) 5684 continue; 5685 5686 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes); 5687 if (ret) 5688 return ret; 5689 } 5690 5691 return 0; 5692 } 5693 5694 static int intel_atomic_check_crtcs(struct intel_atomic_state *state) 5695 { 5696 struct intel_crtc_state *crtc_state; 5697 struct intel_crtc *crtc; 5698 int i; 5699 5700 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5701 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 5702 int ret; 5703 5704 ret = intel_crtc_atomic_check(state, crtc); 5705 if (ret) { 5706 drm_dbg_atomic(&i915->drm, 5707 "[CRTC:%d:%s] atomic driver check failed\n", 5708 crtc->base.base.id, crtc->base.name); 5709 return ret; 5710 } 5711 } 5712 5713 return 0; 5714 } 5715 5716 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, 5717 u8 transcoders) 5718 { 5719 const struct intel_crtc_state *new_crtc_state; 5720 struct intel_crtc *crtc; 5721 int i; 5722 5723 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 5724 if (new_crtc_state->hw.enable && 5725 transcoders & BIT(new_crtc_state->cpu_transcoder) && 5726 intel_crtc_needs_modeset(new_crtc_state)) 5727 return true; 5728 } 5729 5730 return false; 5731 } 5732 5733 static bool intel_pipes_need_modeset(struct intel_atomic_state *state, 5734 u8 pipes) 5735 { 5736 const struct intel_crtc_state *new_crtc_state; 5737 struct intel_crtc *crtc; 5738 int i; 5739 5740 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 5741 if (new_crtc_state->hw.enable && 5742 pipes & BIT(crtc->pipe) && 5743 intel_crtc_needs_modeset(new_crtc_state)) 5744 return true; 5745 } 5746 5747 return false; 5748 } 5749 5750 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state, 5751 struct intel_crtc *master_crtc) 5752 { 5753 struct drm_i915_private *i915 = to_i915(state->base.dev); 5754 struct intel_crtc_state *master_crtc_state = 5755 intel_atomic_get_new_crtc_state(state, master_crtc); 5756 struct intel_crtc *slave_crtc; 5757 5758 if (!master_crtc_state->bigjoiner_pipes) 5759 return 0; 5760 5761 /* sanity check */ 5762 if (drm_WARN_ON(&i915->drm, 5763 master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state))) 5764 return -EINVAL; 5765 5766 if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) { 5767 drm_dbg_kms(&i915->drm, 5768 "[CRTC:%d:%s] Cannot act as big joiner master " 5769 "(need 0x%x as pipes, only 0x%x possible)\n", 5770 master_crtc->base.base.id, master_crtc->base.name, 5771 master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915)); 5772 return -EINVAL; 5773 } 5774 5775 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 5776 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 5777 struct intel_crtc_state *slave_crtc_state; 5778 int ret; 5779 5780 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc); 5781 if (IS_ERR(slave_crtc_state)) 5782 return PTR_ERR(slave_crtc_state); 5783 5784 /* master being enabled, slave was already configured? */ 5785 if (slave_crtc_state->uapi.enable) { 5786 drm_dbg_kms(&i915->drm, 5787 "[CRTC:%d:%s] Slave is enabled as normal CRTC, but " 5788 "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n", 5789 slave_crtc->base.base.id, slave_crtc->base.name, 5790 master_crtc->base.base.id, master_crtc->base.name); 5791 return -EINVAL; 5792 } 5793 5794 /* 5795 * The state copy logic assumes the master crtc gets processed 5796 * before the slave crtc during the main compute_config loop. 5797 * This works because the crtcs are created in pipe order, 5798 * and the hardware requires master pipe < slave pipe as well. 5799 * Should that change we need to rethink the logic. 5800 */ 5801 if (WARN_ON(drm_crtc_index(&master_crtc->base) > 5802 drm_crtc_index(&slave_crtc->base))) 5803 return -EINVAL; 5804 5805 drm_dbg_kms(&i915->drm, 5806 "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n", 5807 slave_crtc->base.base.id, slave_crtc->base.name, 5808 master_crtc->base.base.id, master_crtc->base.name); 5809 5810 slave_crtc_state->bigjoiner_pipes = 5811 master_crtc_state->bigjoiner_pipes; 5812 5813 ret = copy_bigjoiner_crtc_state_modeset(state, slave_crtc); 5814 if (ret) 5815 return ret; 5816 } 5817 5818 return 0; 5819 } 5820 5821 static void kill_bigjoiner_slave(struct intel_atomic_state *state, 5822 struct intel_crtc *master_crtc) 5823 { 5824 struct drm_i915_private *i915 = to_i915(state->base.dev); 5825 struct intel_crtc_state *master_crtc_state = 5826 intel_atomic_get_new_crtc_state(state, master_crtc); 5827 struct intel_crtc *slave_crtc; 5828 5829 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 5830 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 5831 struct intel_crtc_state *slave_crtc_state = 5832 intel_atomic_get_new_crtc_state(state, slave_crtc); 5833 5834 slave_crtc_state->bigjoiner_pipes = 0; 5835 5836 intel_crtc_copy_uapi_to_hw_state_modeset(state, slave_crtc); 5837 } 5838 5839 master_crtc_state->bigjoiner_pipes = 0; 5840 } 5841 5842 /** 5843 * DOC: asynchronous flip implementation 5844 * 5845 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC 5846 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL. 5847 * Correspondingly, support is currently added for primary plane only. 5848 * 5849 * Async flip can only change the plane surface address, so anything else 5850 * changing is rejected from the intel_async_flip_check_hw() function. 5851 * Once this check is cleared, flip done interrupt is enabled using 5852 * the intel_crtc_enable_flip_done() function. 5853 * 5854 * As soon as the surface address register is written, flip done interrupt is 5855 * generated and the requested events are sent to the usersapce in the interrupt 5856 * handler itself. The timestamp and sequence sent during the flip done event 5857 * correspond to the last vblank and have no relation to the actual time when 5858 * the flip done event was sent. 5859 */ 5860 static int intel_async_flip_check_uapi(struct intel_atomic_state *state, 5861 struct intel_crtc *crtc) 5862 { 5863 struct drm_i915_private *i915 = to_i915(state->base.dev); 5864 const struct intel_crtc_state *new_crtc_state = 5865 intel_atomic_get_new_crtc_state(state, crtc); 5866 const struct intel_plane_state *old_plane_state; 5867 struct intel_plane_state *new_plane_state; 5868 struct intel_plane *plane; 5869 int i; 5870 5871 if (!new_crtc_state->uapi.async_flip) 5872 return 0; 5873 5874 if (!new_crtc_state->uapi.active) { 5875 drm_dbg_kms(&i915->drm, 5876 "[CRTC:%d:%s] not active\n", 5877 crtc->base.base.id, crtc->base.name); 5878 return -EINVAL; 5879 } 5880 5881 if (intel_crtc_needs_modeset(new_crtc_state)) { 5882 drm_dbg_kms(&i915->drm, 5883 "[CRTC:%d:%s] modeset required\n", 5884 crtc->base.base.id, crtc->base.name); 5885 return -EINVAL; 5886 } 5887 5888 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 5889 new_plane_state, i) { 5890 if (plane->pipe != crtc->pipe) 5891 continue; 5892 5893 /* 5894 * TODO: Async flip is only supported through the page flip IOCTL 5895 * as of now. So support currently added for primary plane only. 5896 * Support for other planes on platforms on which supports 5897 * this(vlv/chv and icl+) should be added when async flip is 5898 * enabled in the atomic IOCTL path. 5899 */ 5900 if (!plane->async_flip) { 5901 drm_dbg_kms(&i915->drm, 5902 "[PLANE:%d:%s] async flip not supported\n", 5903 plane->base.base.id, plane->base.name); 5904 return -EINVAL; 5905 } 5906 5907 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) { 5908 drm_dbg_kms(&i915->drm, 5909 "[PLANE:%d:%s] no old or new framebuffer\n", 5910 plane->base.base.id, plane->base.name); 5911 return -EINVAL; 5912 } 5913 } 5914 5915 return 0; 5916 } 5917 5918 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc) 5919 { 5920 struct drm_i915_private *i915 = to_i915(state->base.dev); 5921 const struct intel_crtc_state *old_crtc_state, *new_crtc_state; 5922 const struct intel_plane_state *new_plane_state, *old_plane_state; 5923 struct intel_plane *plane; 5924 int i; 5925 5926 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 5927 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 5928 5929 if (!new_crtc_state->uapi.async_flip) 5930 return 0; 5931 5932 if (!new_crtc_state->hw.active) { 5933 drm_dbg_kms(&i915->drm, 5934 "[CRTC:%d:%s] not active\n", 5935 crtc->base.base.id, crtc->base.name); 5936 return -EINVAL; 5937 } 5938 5939 if (intel_crtc_needs_modeset(new_crtc_state)) { 5940 drm_dbg_kms(&i915->drm, 5941 "[CRTC:%d:%s] modeset required\n", 5942 crtc->base.base.id, crtc->base.name); 5943 return -EINVAL; 5944 } 5945 5946 if (old_crtc_state->active_planes != new_crtc_state->active_planes) { 5947 drm_dbg_kms(&i915->drm, 5948 "[CRTC:%d:%s] Active planes cannot be in async flip\n", 5949 crtc->base.base.id, crtc->base.name); 5950 return -EINVAL; 5951 } 5952 5953 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 5954 new_plane_state, i) { 5955 if (plane->pipe != crtc->pipe) 5956 continue; 5957 5958 /* 5959 * Only async flip capable planes should be in the state 5960 * if we're really about to ask the hardware to perform 5961 * an async flip. We should never get this far otherwise. 5962 */ 5963 if (drm_WARN_ON(&i915->drm, 5964 new_crtc_state->do_async_flip && !plane->async_flip)) 5965 return -EINVAL; 5966 5967 /* 5968 * Only check async flip capable planes other planes 5969 * may be involved in the initial commit due to 5970 * the wm0/ddb optimization. 5971 * 5972 * TODO maybe should track which planes actually 5973 * were requested to do the async flip... 5974 */ 5975 if (!plane->async_flip) 5976 continue; 5977 5978 /* 5979 * FIXME: This check is kept generic for all platforms. 5980 * Need to verify this for all gen9 platforms to enable 5981 * this selectively if required. 5982 */ 5983 switch (new_plane_state->hw.fb->modifier) { 5984 case I915_FORMAT_MOD_X_TILED: 5985 case I915_FORMAT_MOD_Y_TILED: 5986 case I915_FORMAT_MOD_Yf_TILED: 5987 case I915_FORMAT_MOD_4_TILED: 5988 break; 5989 default: 5990 drm_dbg_kms(&i915->drm, 5991 "[PLANE:%d:%s] Modifier does not support async flips\n", 5992 plane->base.base.id, plane->base.name); 5993 return -EINVAL; 5994 } 5995 5996 if (new_plane_state->hw.fb->format->num_planes > 1) { 5997 drm_dbg_kms(&i915->drm, 5998 "[PLANE:%d:%s] Planar formats do not support async flips\n", 5999 plane->base.base.id, plane->base.name); 6000 return -EINVAL; 6001 } 6002 6003 if (old_plane_state->view.color_plane[0].mapping_stride != 6004 new_plane_state->view.color_plane[0].mapping_stride) { 6005 drm_dbg_kms(&i915->drm, 6006 "[PLANE:%d:%s] Stride cannot be changed in async flip\n", 6007 plane->base.base.id, plane->base.name); 6008 return -EINVAL; 6009 } 6010 6011 if (old_plane_state->hw.fb->modifier != 6012 new_plane_state->hw.fb->modifier) { 6013 drm_dbg_kms(&i915->drm, 6014 "[PLANE:%d:%s] Modifier cannot be changed in async flip\n", 6015 plane->base.base.id, plane->base.name); 6016 return -EINVAL; 6017 } 6018 6019 if (old_plane_state->hw.fb->format != 6020 new_plane_state->hw.fb->format) { 6021 drm_dbg_kms(&i915->drm, 6022 "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n", 6023 plane->base.base.id, plane->base.name); 6024 return -EINVAL; 6025 } 6026 6027 if (old_plane_state->hw.rotation != 6028 new_plane_state->hw.rotation) { 6029 drm_dbg_kms(&i915->drm, 6030 "[PLANE:%d:%s] Rotation cannot be changed in async flip\n", 6031 plane->base.base.id, plane->base.name); 6032 return -EINVAL; 6033 } 6034 6035 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) || 6036 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) { 6037 drm_dbg_kms(&i915->drm, 6038 "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n", 6039 plane->base.base.id, plane->base.name); 6040 return -EINVAL; 6041 } 6042 6043 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) { 6044 drm_dbg_kms(&i915->drm, 6045 "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n", 6046 plane->base.base.id, plane->base.name); 6047 return -EINVAL; 6048 } 6049 6050 if (old_plane_state->hw.pixel_blend_mode != 6051 new_plane_state->hw.pixel_blend_mode) { 6052 drm_dbg_kms(&i915->drm, 6053 "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n", 6054 plane->base.base.id, plane->base.name); 6055 return -EINVAL; 6056 } 6057 6058 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) { 6059 drm_dbg_kms(&i915->drm, 6060 "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n", 6061 plane->base.base.id, plane->base.name); 6062 return -EINVAL; 6063 } 6064 6065 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) { 6066 drm_dbg_kms(&i915->drm, 6067 "[PLANE:%d:%s] Color range cannot be changed in async flip\n", 6068 plane->base.base.id, plane->base.name); 6069 return -EINVAL; 6070 } 6071 6072 /* plane decryption is allow to change only in synchronous flips */ 6073 if (old_plane_state->decrypt != new_plane_state->decrypt) { 6074 drm_dbg_kms(&i915->drm, 6075 "[PLANE:%d:%s] Decryption cannot be changed in async flip\n", 6076 plane->base.base.id, plane->base.name); 6077 return -EINVAL; 6078 } 6079 } 6080 6081 return 0; 6082 } 6083 6084 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state) 6085 { 6086 struct drm_i915_private *i915 = to_i915(state->base.dev); 6087 struct intel_crtc_state *crtc_state; 6088 struct intel_crtc *crtc; 6089 u8 affected_pipes = 0; 6090 u8 modeset_pipes = 0; 6091 int i; 6092 6093 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6094 affected_pipes |= crtc_state->bigjoiner_pipes; 6095 if (intel_crtc_needs_modeset(crtc_state)) 6096 modeset_pipes |= crtc_state->bigjoiner_pipes; 6097 } 6098 6099 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) { 6100 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6101 if (IS_ERR(crtc_state)) 6102 return PTR_ERR(crtc_state); 6103 } 6104 6105 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) { 6106 int ret; 6107 6108 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6109 6110 crtc_state->uapi.mode_changed = true; 6111 6112 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); 6113 if (ret) 6114 return ret; 6115 6116 ret = intel_atomic_add_affected_planes(state, crtc); 6117 if (ret) 6118 return ret; 6119 } 6120 6121 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6122 /* Kill old bigjoiner link, we may re-establish afterwards */ 6123 if (intel_crtc_needs_modeset(crtc_state) && 6124 intel_crtc_is_bigjoiner_master(crtc_state)) 6125 kill_bigjoiner_slave(state, crtc); 6126 } 6127 6128 return 0; 6129 } 6130 6131 /** 6132 * intel_atomic_check - validate state object 6133 * @dev: drm device 6134 * @_state: state to validate 6135 */ 6136 int intel_atomic_check(struct drm_device *dev, 6137 struct drm_atomic_state *_state) 6138 { 6139 struct drm_i915_private *dev_priv = to_i915(dev); 6140 struct intel_atomic_state *state = to_intel_atomic_state(_state); 6141 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6142 struct intel_crtc *crtc; 6143 int ret, i; 6144 bool any_ms = false; 6145 6146 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6147 new_crtc_state, i) { 6148 /* 6149 * crtc's state no longer considered to be inherited 6150 * after the first userspace/client initiated commit. 6151 */ 6152 if (!state->internal) 6153 new_crtc_state->inherited = false; 6154 6155 if (new_crtc_state->inherited != old_crtc_state->inherited) 6156 new_crtc_state->uapi.mode_changed = true; 6157 6158 if (new_crtc_state->uapi.scaling_filter != 6159 old_crtc_state->uapi.scaling_filter) 6160 new_crtc_state->uapi.mode_changed = true; 6161 } 6162 6163 intel_vrr_check_modeset(state); 6164 6165 ret = drm_atomic_helper_check_modeset(dev, &state->base); 6166 if (ret) 6167 goto fail; 6168 6169 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6170 ret = intel_async_flip_check_uapi(state, crtc); 6171 if (ret) 6172 return ret; 6173 } 6174 6175 ret = intel_bigjoiner_add_affected_crtcs(state); 6176 if (ret) 6177 goto fail; 6178 6179 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6180 new_crtc_state, i) { 6181 if (!intel_crtc_needs_modeset(new_crtc_state)) { 6182 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 6183 copy_bigjoiner_crtc_state_nomodeset(state, crtc); 6184 else 6185 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 6186 continue; 6187 } 6188 6189 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) { 6190 drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable); 6191 continue; 6192 } 6193 6194 ret = intel_crtc_prepare_cleared_state(state, crtc); 6195 if (ret) 6196 goto fail; 6197 6198 if (!new_crtc_state->hw.enable) 6199 continue; 6200 6201 ret = intel_modeset_pipe_config(state, crtc); 6202 if (ret) 6203 goto fail; 6204 6205 ret = intel_atomic_check_bigjoiner(state, crtc); 6206 if (ret) 6207 goto fail; 6208 } 6209 6210 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6211 new_crtc_state, i) { 6212 if (!intel_crtc_needs_modeset(new_crtc_state)) 6213 continue; 6214 6215 if (new_crtc_state->hw.enable) { 6216 ret = intel_modeset_pipe_config_late(state, crtc); 6217 if (ret) 6218 goto fail; 6219 } 6220 6221 intel_crtc_check_fastset(old_crtc_state, new_crtc_state); 6222 } 6223 6224 /** 6225 * Check if fastset is allowed by external dependencies like other 6226 * pipes and transcoders. 6227 * 6228 * Right now it only forces a fullmodeset when the MST master 6229 * transcoder did not changed but the pipe of the master transcoder 6230 * needs a fullmodeset so all slaves also needs to do a fullmodeset or 6231 * in case of port synced crtcs, if one of the synced crtcs 6232 * needs a full modeset, all other synced crtcs should be 6233 * forced a full modeset. 6234 */ 6235 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6236 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state)) 6237 continue; 6238 6239 if (intel_dp_mst_is_slave_trans(new_crtc_state)) { 6240 enum transcoder master = new_crtc_state->mst_master_transcoder; 6241 6242 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) { 6243 new_crtc_state->uapi.mode_changed = true; 6244 new_crtc_state->update_pipe = false; 6245 } 6246 } 6247 6248 if (is_trans_port_sync_mode(new_crtc_state)) { 6249 u8 trans = new_crtc_state->sync_mode_slaves_mask; 6250 6251 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER) 6252 trans |= BIT(new_crtc_state->master_transcoder); 6253 6254 if (intel_cpu_transcoders_need_modeset(state, trans)) { 6255 new_crtc_state->uapi.mode_changed = true; 6256 new_crtc_state->update_pipe = false; 6257 } 6258 } 6259 6260 if (new_crtc_state->bigjoiner_pipes) { 6261 if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) { 6262 new_crtc_state->uapi.mode_changed = true; 6263 new_crtc_state->update_pipe = false; 6264 } 6265 } 6266 } 6267 6268 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6269 new_crtc_state, i) { 6270 if (!intel_crtc_needs_modeset(new_crtc_state)) 6271 continue; 6272 6273 any_ms = true; 6274 6275 intel_release_shared_dplls(state, crtc); 6276 } 6277 6278 if (any_ms && !check_digital_port_conflicts(state)) { 6279 drm_dbg_kms(&dev_priv->drm, 6280 "rejecting conflicting digital port configuration\n"); 6281 ret = -EINVAL; 6282 goto fail; 6283 } 6284 6285 ret = drm_dp_mst_atomic_check(&state->base); 6286 if (ret) 6287 goto fail; 6288 6289 ret = intel_atomic_check_planes(state); 6290 if (ret) 6291 goto fail; 6292 6293 ret = intel_compute_global_watermarks(state); 6294 if (ret) 6295 goto fail; 6296 6297 ret = intel_bw_atomic_check(state); 6298 if (ret) 6299 goto fail; 6300 6301 ret = intel_cdclk_atomic_check(state, &any_ms); 6302 if (ret) 6303 goto fail; 6304 6305 if (intel_any_crtc_needs_modeset(state)) 6306 any_ms = true; 6307 6308 if (any_ms) { 6309 ret = intel_modeset_checks(state); 6310 if (ret) 6311 goto fail; 6312 6313 ret = intel_modeset_calc_cdclk(state); 6314 if (ret) 6315 return ret; 6316 } 6317 6318 ret = intel_atomic_check_crtcs(state); 6319 if (ret) 6320 goto fail; 6321 6322 ret = intel_fbc_atomic_check(state); 6323 if (ret) 6324 goto fail; 6325 6326 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6327 new_crtc_state, i) { 6328 intel_color_assert_luts(new_crtc_state); 6329 6330 ret = intel_async_flip_check_hw(state, crtc); 6331 if (ret) 6332 goto fail; 6333 6334 /* Either full modeset or fastset (or neither), never both */ 6335 drm_WARN_ON(&dev_priv->drm, 6336 intel_crtc_needs_modeset(new_crtc_state) && 6337 intel_crtc_needs_fastset(new_crtc_state)); 6338 6339 if (!intel_crtc_needs_modeset(new_crtc_state) && 6340 !intel_crtc_needs_fastset(new_crtc_state)) 6341 continue; 6342 6343 intel_crtc_state_dump(new_crtc_state, state, 6344 intel_crtc_needs_modeset(new_crtc_state) ? 6345 "modeset" : "fastset"); 6346 } 6347 6348 return 0; 6349 6350 fail: 6351 if (ret == -EDEADLK) 6352 return ret; 6353 6354 /* 6355 * FIXME would probably be nice to know which crtc specifically 6356 * caused the failure, in cases where we can pinpoint it. 6357 */ 6358 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6359 new_crtc_state, i) 6360 intel_crtc_state_dump(new_crtc_state, state, "failed"); 6361 6362 return ret; 6363 } 6364 6365 static int intel_atomic_prepare_commit(struct intel_atomic_state *state) 6366 { 6367 struct intel_crtc_state *crtc_state; 6368 struct intel_crtc *crtc; 6369 int i, ret; 6370 6371 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base); 6372 if (ret < 0) 6373 return ret; 6374 6375 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6376 if (intel_crtc_needs_color_update(crtc_state)) 6377 intel_color_prepare_commit(crtc_state); 6378 } 6379 6380 return 0; 6381 } 6382 6383 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 6384 struct intel_crtc_state *crtc_state) 6385 { 6386 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6387 6388 if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes) 6389 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 6390 6391 if (crtc_state->has_pch_encoder) { 6392 enum pipe pch_transcoder = 6393 intel_crtc_pch_transcoder(crtc); 6394 6395 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true); 6396 } 6397 } 6398 6399 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, 6400 const struct intel_crtc_state *new_crtc_state) 6401 { 6402 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 6403 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6404 6405 /* 6406 * Update pipe size and adjust fitter if needed: the reason for this is 6407 * that in compute_mode_changes we check the native mode (not the pfit 6408 * mode) to see if we can flip rather than do a full mode set. In the 6409 * fastboot case, we'll flip, but if we don't update the pipesrc and 6410 * pfit state, we'll end up with a big fb scanned out into the wrong 6411 * sized surface. 6412 */ 6413 intel_set_pipe_src_size(new_crtc_state); 6414 6415 /* on skylake this is done by detaching scalers */ 6416 if (DISPLAY_VER(dev_priv) >= 9) { 6417 if (new_crtc_state->pch_pfit.enabled) 6418 skl_pfit_enable(new_crtc_state); 6419 } else if (HAS_PCH_SPLIT(dev_priv)) { 6420 if (new_crtc_state->pch_pfit.enabled) 6421 ilk_pfit_enable(new_crtc_state); 6422 else if (old_crtc_state->pch_pfit.enabled) 6423 ilk_pfit_disable(old_crtc_state); 6424 } 6425 6426 /* 6427 * The register is supposedly single buffered so perhaps 6428 * not 100% correct to do this here. But SKL+ calculate 6429 * this based on the adjust pixel rate so pfit changes do 6430 * affect it and so it must be updated for fastsets. 6431 * HSW/BDW only really need this here for fastboot, after 6432 * that the value should not change without a full modeset. 6433 */ 6434 if (DISPLAY_VER(dev_priv) >= 9 || 6435 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 6436 hsw_set_linetime_wm(new_crtc_state); 6437 6438 if (new_crtc_state->seamless_m_n) 6439 intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder, 6440 &new_crtc_state->dp_m_n); 6441 } 6442 6443 static void commit_pipe_pre_planes(struct intel_atomic_state *state, 6444 struct intel_crtc *crtc) 6445 { 6446 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6447 const struct intel_crtc_state *old_crtc_state = 6448 intel_atomic_get_old_crtc_state(state, crtc); 6449 const struct intel_crtc_state *new_crtc_state = 6450 intel_atomic_get_new_crtc_state(state, crtc); 6451 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 6452 6453 /* 6454 * During modesets pipe configuration was programmed as the 6455 * CRTC was enabled. 6456 */ 6457 if (!modeset) { 6458 if (intel_crtc_needs_color_update(new_crtc_state)) 6459 intel_color_commit_arm(new_crtc_state); 6460 6461 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 6462 bdw_set_pipe_misc(new_crtc_state); 6463 6464 if (intel_crtc_needs_fastset(new_crtc_state)) 6465 intel_pipe_fastset(old_crtc_state, new_crtc_state); 6466 } 6467 6468 intel_psr2_program_trans_man_trk_ctl(new_crtc_state); 6469 6470 intel_atomic_update_watermarks(state, crtc); 6471 } 6472 6473 static void commit_pipe_post_planes(struct intel_atomic_state *state, 6474 struct intel_crtc *crtc) 6475 { 6476 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6477 const struct intel_crtc_state *new_crtc_state = 6478 intel_atomic_get_new_crtc_state(state, crtc); 6479 6480 /* 6481 * Disable the scaler(s) after the plane(s) so that we don't 6482 * get a catastrophic underrun even if the two operations 6483 * end up happening in two different frames. 6484 */ 6485 if (DISPLAY_VER(dev_priv) >= 9 && 6486 !intel_crtc_needs_modeset(new_crtc_state)) 6487 skl_detach_scalers(new_crtc_state); 6488 } 6489 6490 static void intel_enable_crtc(struct intel_atomic_state *state, 6491 struct intel_crtc *crtc) 6492 { 6493 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6494 const struct intel_crtc_state *new_crtc_state = 6495 intel_atomic_get_new_crtc_state(state, crtc); 6496 6497 if (!intel_crtc_needs_modeset(new_crtc_state)) 6498 return; 6499 6500 /* VRR will be enable later, if required */ 6501 intel_crtc_update_active_timings(new_crtc_state, false); 6502 6503 dev_priv->display.funcs.display->crtc_enable(state, crtc); 6504 6505 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 6506 return; 6507 6508 /* vblanks work again, re-enable pipe CRC. */ 6509 intel_crtc_enable_pipe_crc(crtc); 6510 } 6511 6512 static void intel_update_crtc(struct intel_atomic_state *state, 6513 struct intel_crtc *crtc) 6514 { 6515 struct drm_i915_private *i915 = to_i915(state->base.dev); 6516 const struct intel_crtc_state *old_crtc_state = 6517 intel_atomic_get_old_crtc_state(state, crtc); 6518 struct intel_crtc_state *new_crtc_state = 6519 intel_atomic_get_new_crtc_state(state, crtc); 6520 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 6521 6522 if (old_crtc_state->inherited || 6523 intel_crtc_needs_modeset(new_crtc_state)) { 6524 if (HAS_DPT(i915)) 6525 intel_dpt_configure(crtc); 6526 } 6527 6528 if (vrr_enabling(old_crtc_state, new_crtc_state)) { 6529 intel_vrr_enable(new_crtc_state); 6530 intel_crtc_update_active_timings(new_crtc_state, 6531 new_crtc_state->vrr.enable); 6532 } 6533 6534 if (!modeset) { 6535 if (new_crtc_state->preload_luts && 6536 intel_crtc_needs_color_update(new_crtc_state)) 6537 intel_color_load_luts(new_crtc_state); 6538 6539 intel_pre_plane_update(state, crtc); 6540 6541 if (intel_crtc_needs_fastset(new_crtc_state)) 6542 intel_encoders_update_pipe(state, crtc); 6543 6544 if (DISPLAY_VER(i915) >= 11 && 6545 intel_crtc_needs_fastset(new_crtc_state)) 6546 icl_set_pipe_chicken(new_crtc_state); 6547 } 6548 6549 intel_fbc_update(state, crtc); 6550 6551 drm_WARN_ON(&i915->drm, !intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF)); 6552 6553 if (!modeset && 6554 intel_crtc_needs_color_update(new_crtc_state)) 6555 intel_color_commit_noarm(new_crtc_state); 6556 6557 intel_crtc_planes_update_noarm(state, crtc); 6558 6559 /* Perform vblank evasion around commit operation */ 6560 intel_pipe_update_start(new_crtc_state); 6561 6562 commit_pipe_pre_planes(state, crtc); 6563 6564 intel_crtc_planes_update_arm(state, crtc); 6565 6566 commit_pipe_post_planes(state, crtc); 6567 6568 intel_pipe_update_end(new_crtc_state); 6569 6570 /* 6571 * We usually enable FIFO underrun interrupts as part of the 6572 * CRTC enable sequence during modesets. But when we inherit a 6573 * valid pipe configuration from the BIOS we need to take care 6574 * of enabling them on the CRTC's first fastset. 6575 */ 6576 if (intel_crtc_needs_fastset(new_crtc_state) && !modeset && 6577 old_crtc_state->inherited) 6578 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state); 6579 } 6580 6581 static void intel_old_crtc_state_disables(struct intel_atomic_state *state, 6582 struct intel_crtc_state *old_crtc_state, 6583 struct intel_crtc_state *new_crtc_state, 6584 struct intel_crtc *crtc) 6585 { 6586 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6587 6588 /* 6589 * We need to disable pipe CRC before disabling the pipe, 6590 * or we race against vblank off. 6591 */ 6592 intel_crtc_disable_pipe_crc(crtc); 6593 6594 dev_priv->display.funcs.display->crtc_disable(state, crtc); 6595 crtc->active = false; 6596 intel_fbc_disable(crtc); 6597 6598 if (!new_crtc_state->hw.active) 6599 intel_initial_watermarks(state, crtc); 6600 } 6601 6602 static void intel_commit_modeset_disables(struct intel_atomic_state *state) 6603 { 6604 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 6605 struct intel_crtc *crtc; 6606 u32 handled = 0; 6607 int i; 6608 6609 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6610 new_crtc_state, i) { 6611 if (!intel_crtc_needs_modeset(new_crtc_state)) 6612 continue; 6613 6614 if (!old_crtc_state->hw.active) 6615 continue; 6616 6617 intel_pre_plane_update(state, crtc); 6618 intel_crtc_disable_planes(state, crtc); 6619 } 6620 6621 /* Only disable port sync and MST slaves */ 6622 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6623 new_crtc_state, i) { 6624 if (!intel_crtc_needs_modeset(new_crtc_state)) 6625 continue; 6626 6627 if (!old_crtc_state->hw.active) 6628 continue; 6629 6630 /* In case of Transcoder port Sync master slave CRTCs can be 6631 * assigned in any order and we need to make sure that 6632 * slave CRTCs are disabled first and then master CRTC since 6633 * Slave vblanks are masked till Master Vblanks. 6634 */ 6635 if (!is_trans_port_sync_slave(old_crtc_state) && 6636 !intel_dp_mst_is_slave_trans(old_crtc_state) && 6637 !intel_crtc_is_bigjoiner_slave(old_crtc_state)) 6638 continue; 6639 6640 intel_old_crtc_state_disables(state, old_crtc_state, 6641 new_crtc_state, crtc); 6642 handled |= BIT(crtc->pipe); 6643 } 6644 6645 /* Disable everything else left on */ 6646 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6647 new_crtc_state, i) { 6648 if (!intel_crtc_needs_modeset(new_crtc_state) || 6649 (handled & BIT(crtc->pipe))) 6650 continue; 6651 6652 if (!old_crtc_state->hw.active) 6653 continue; 6654 6655 intel_old_crtc_state_disables(state, old_crtc_state, 6656 new_crtc_state, crtc); 6657 } 6658 } 6659 6660 static void intel_commit_modeset_enables(struct intel_atomic_state *state) 6661 { 6662 struct intel_crtc_state *new_crtc_state; 6663 struct intel_crtc *crtc; 6664 int i; 6665 6666 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6667 if (!new_crtc_state->hw.active) 6668 continue; 6669 6670 intel_enable_crtc(state, crtc); 6671 intel_update_crtc(state, crtc); 6672 } 6673 } 6674 6675 static void skl_commit_modeset_enables(struct intel_atomic_state *state) 6676 { 6677 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6678 struct intel_crtc *crtc; 6679 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6680 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; 6681 u8 update_pipes = 0, modeset_pipes = 0; 6682 int i; 6683 6684 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6685 enum pipe pipe = crtc->pipe; 6686 6687 if (!new_crtc_state->hw.active) 6688 continue; 6689 6690 /* ignore allocations for crtc's that have been turned off. */ 6691 if (!intel_crtc_needs_modeset(new_crtc_state)) { 6692 entries[pipe] = old_crtc_state->wm.skl.ddb; 6693 update_pipes |= BIT(pipe); 6694 } else { 6695 modeset_pipes |= BIT(pipe); 6696 } 6697 } 6698 6699 /* 6700 * Whenever the number of active pipes changes, we need to make sure we 6701 * update the pipes in the right order so that their ddb allocations 6702 * never overlap with each other between CRTC updates. Otherwise we'll 6703 * cause pipe underruns and other bad stuff. 6704 * 6705 * So first lets enable all pipes that do not need a fullmodeset as 6706 * those don't have any external dependency. 6707 */ 6708 while (update_pipes) { 6709 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6710 new_crtc_state, i) { 6711 enum pipe pipe = crtc->pipe; 6712 6713 if ((update_pipes & BIT(pipe)) == 0) 6714 continue; 6715 6716 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 6717 entries, I915_MAX_PIPES, pipe)) 6718 continue; 6719 6720 entries[pipe] = new_crtc_state->wm.skl.ddb; 6721 update_pipes &= ~BIT(pipe); 6722 6723 intel_update_crtc(state, crtc); 6724 6725 /* 6726 * If this is an already active pipe, it's DDB changed, 6727 * and this isn't the last pipe that needs updating 6728 * then we need to wait for a vblank to pass for the 6729 * new ddb allocation to take effect. 6730 */ 6731 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, 6732 &old_crtc_state->wm.skl.ddb) && 6733 (update_pipes | modeset_pipes)) 6734 intel_crtc_wait_for_next_vblank(crtc); 6735 } 6736 } 6737 6738 update_pipes = modeset_pipes; 6739 6740 /* 6741 * Enable all pipes that needs a modeset and do not depends on other 6742 * pipes 6743 */ 6744 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6745 enum pipe pipe = crtc->pipe; 6746 6747 if ((modeset_pipes & BIT(pipe)) == 0) 6748 continue; 6749 6750 if (intel_dp_mst_is_slave_trans(new_crtc_state) || 6751 is_trans_port_sync_master(new_crtc_state) || 6752 intel_crtc_is_bigjoiner_master(new_crtc_state)) 6753 continue; 6754 6755 modeset_pipes &= ~BIT(pipe); 6756 6757 intel_enable_crtc(state, crtc); 6758 } 6759 6760 /* 6761 * Then we enable all remaining pipes that depend on other 6762 * pipes: MST slaves and port sync masters, big joiner master 6763 */ 6764 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6765 enum pipe pipe = crtc->pipe; 6766 6767 if ((modeset_pipes & BIT(pipe)) == 0) 6768 continue; 6769 6770 modeset_pipes &= ~BIT(pipe); 6771 6772 intel_enable_crtc(state, crtc); 6773 } 6774 6775 /* 6776 * Finally we do the plane updates/etc. for all pipes that got enabled. 6777 */ 6778 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6779 enum pipe pipe = crtc->pipe; 6780 6781 if ((update_pipes & BIT(pipe)) == 0) 6782 continue; 6783 6784 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 6785 entries, I915_MAX_PIPES, pipe)); 6786 6787 entries[pipe] = new_crtc_state->wm.skl.ddb; 6788 update_pipes &= ~BIT(pipe); 6789 6790 intel_update_crtc(state, crtc); 6791 } 6792 6793 drm_WARN_ON(&dev_priv->drm, modeset_pipes); 6794 drm_WARN_ON(&dev_priv->drm, update_pipes); 6795 } 6796 6797 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) 6798 { 6799 struct intel_atomic_state *state, *next; 6800 struct llist_node *freed; 6801 6802 freed = llist_del_all(&dev_priv->display.atomic_helper.free_list); 6803 llist_for_each_entry_safe(state, next, freed, freed) 6804 drm_atomic_state_put(&state->base); 6805 } 6806 6807 void intel_atomic_helper_free_state_worker(struct work_struct *work) 6808 { 6809 struct drm_i915_private *dev_priv = 6810 container_of(work, typeof(*dev_priv), display.atomic_helper.free_work); 6811 6812 intel_atomic_helper_free_state(dev_priv); 6813 } 6814 6815 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) 6816 { 6817 struct wait_queue_entry wait_fence, wait_reset; 6818 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); 6819 6820 init_wait_entry(&wait_fence, 0); 6821 init_wait_entry(&wait_reset, 0); 6822 for (;;) { 6823 prepare_to_wait(&intel_state->commit_ready.wait, 6824 &wait_fence, TASK_UNINTERRUPTIBLE); 6825 prepare_to_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 6826 I915_RESET_MODESET), 6827 &wait_reset, TASK_UNINTERRUPTIBLE); 6828 6829 6830 if (i915_sw_fence_done(&intel_state->commit_ready) || 6831 test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags)) 6832 break; 6833 6834 schedule(); 6835 } 6836 finish_wait(&intel_state->commit_ready.wait, &wait_fence); 6837 finish_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 6838 I915_RESET_MODESET), 6839 &wait_reset); 6840 } 6841 6842 static void intel_atomic_cleanup_work(struct work_struct *work) 6843 { 6844 struct intel_atomic_state *state = 6845 container_of(work, struct intel_atomic_state, base.commit_work); 6846 struct drm_i915_private *i915 = to_i915(state->base.dev); 6847 struct intel_crtc_state *old_crtc_state; 6848 struct intel_crtc *crtc; 6849 int i; 6850 6851 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) 6852 intel_color_cleanup_commit(old_crtc_state); 6853 6854 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base); 6855 drm_atomic_helper_commit_cleanup_done(&state->base); 6856 drm_atomic_state_put(&state->base); 6857 6858 intel_atomic_helper_free_state(i915); 6859 } 6860 6861 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state) 6862 { 6863 struct drm_i915_private *i915 = to_i915(state->base.dev); 6864 struct intel_plane *plane; 6865 struct intel_plane_state *plane_state; 6866 int i; 6867 6868 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 6869 struct drm_framebuffer *fb = plane_state->hw.fb; 6870 int cc_plane; 6871 int ret; 6872 6873 if (!fb) 6874 continue; 6875 6876 cc_plane = intel_fb_rc_ccs_cc_plane(fb); 6877 if (cc_plane < 0) 6878 continue; 6879 6880 /* 6881 * The layout of the fast clear color value expected by HW 6882 * (the DRM ABI requiring this value to be located in fb at 6883 * offset 0 of cc plane, plane #2 previous generations or 6884 * plane #1 for flat ccs): 6885 * - 4 x 4 bytes per-channel value 6886 * (in surface type specific float/int format provided by the fb user) 6887 * - 8 bytes native color value used by the display 6888 * (converted/written by GPU during a fast clear operation using the 6889 * above per-channel values) 6890 * 6891 * The commit's FB prepare hook already ensured that FB obj is pinned and the 6892 * caller made sure that the object is synced wrt. the related color clear value 6893 * GPU write on it. 6894 */ 6895 ret = i915_gem_object_read_from_page(intel_fb_obj(fb), 6896 fb->offsets[cc_plane] + 16, 6897 &plane_state->ccval, 6898 sizeof(plane_state->ccval)); 6899 /* The above could only fail if the FB obj has an unexpected backing store type. */ 6900 drm_WARN_ON(&i915->drm, ret); 6901 } 6902 } 6903 6904 static void intel_atomic_commit_tail(struct intel_atomic_state *state) 6905 { 6906 struct drm_device *dev = state->base.dev; 6907 struct drm_i915_private *dev_priv = to_i915(dev); 6908 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 6909 struct intel_crtc *crtc; 6910 struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {}; 6911 intel_wakeref_t wakeref = 0; 6912 int i; 6913 6914 intel_atomic_commit_fence_wait(state); 6915 6916 drm_atomic_helper_wait_for_dependencies(&state->base); 6917 drm_dp_mst_atomic_wait_for_dependencies(&state->base); 6918 6919 /* 6920 * During full modesets we write a lot of registers, wait 6921 * for PLLs, etc. Doing that while DC states are enabled 6922 * is not a good idea. 6923 * 6924 * During fastsets and other updates we also need to 6925 * disable DC states due to the following scenario: 6926 * 1. DC5 exit and PSR exit happen 6927 * 2. Some or all _noarm() registers are written 6928 * 3. Due to some long delay PSR is re-entered 6929 * 4. DC5 entry -> DMC saves the already written new 6930 * _noarm() registers and the old not yet written 6931 * _arm() registers 6932 * 5. DC5 exit -> DMC restores a mixture of old and 6933 * new register values and arms the update 6934 * 6. PSR exit -> hardware latches a mixture of old and 6935 * new register values -> corrupted frame, or worse 6936 * 7. New _arm() registers are finally written 6937 * 8. Hardware finally latches a complete set of new 6938 * register values, and subsequent frames will be OK again 6939 * 6940 * Also note that due to the pipe CSC hardware issues on 6941 * SKL/GLK DC states must remain off until the pipe CSC 6942 * state readout has happened. Otherwise we risk corrupting 6943 * the CSC latched register values with the readout (see 6944 * skl_read_csc() and skl_color_commit_noarm()). 6945 */ 6946 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DC_OFF); 6947 6948 intel_atomic_prepare_plane_clear_colors(state); 6949 6950 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6951 new_crtc_state, i) { 6952 if (intel_crtc_needs_modeset(new_crtc_state) || 6953 intel_crtc_needs_fastset(new_crtc_state)) 6954 intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]); 6955 } 6956 6957 intel_commit_modeset_disables(state); 6958 6959 /* FIXME: Eventually get rid of our crtc->config pointer */ 6960 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 6961 crtc->config = new_crtc_state; 6962 6963 if (state->modeset) { 6964 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base); 6965 6966 intel_set_cdclk_pre_plane_update(state); 6967 6968 intel_modeset_verify_disabled(dev_priv, state); 6969 } 6970 6971 intel_sagv_pre_plane_update(state); 6972 6973 /* Complete the events for pipes that have now been disabled */ 6974 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6975 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 6976 6977 /* Complete events for now disable pipes here. */ 6978 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) { 6979 spin_lock_irq(&dev->event_lock); 6980 drm_crtc_send_vblank_event(&crtc->base, 6981 new_crtc_state->uapi.event); 6982 spin_unlock_irq(&dev->event_lock); 6983 6984 new_crtc_state->uapi.event = NULL; 6985 } 6986 } 6987 6988 intel_encoders_update_prepare(state); 6989 6990 intel_dbuf_pre_plane_update(state); 6991 intel_mbus_dbox_update(state); 6992 6993 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6994 if (new_crtc_state->do_async_flip) 6995 intel_crtc_enable_flip_done(state, crtc); 6996 } 6997 6998 /* Now enable the clocks, plane, pipe, and connectors that we set up. */ 6999 dev_priv->display.funcs.display->commit_modeset_enables(state); 7000 7001 if (state->modeset) 7002 intel_set_cdclk_post_plane_update(state); 7003 7004 intel_wait_for_vblank_workers(state); 7005 7006 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here 7007 * already, but still need the state for the delayed optimization. To 7008 * fix this: 7009 * - wrap the optimization/post_plane_update stuff into a per-crtc work. 7010 * - schedule that vblank worker _before_ calling hw_done 7011 * - at the start of commit_tail, cancel it _synchrously 7012 * - switch over to the vblank wait helper in the core after that since 7013 * we don't need out special handling any more. 7014 */ 7015 drm_atomic_helper_wait_for_flip_done(dev, &state->base); 7016 7017 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7018 if (new_crtc_state->do_async_flip) 7019 intel_crtc_disable_flip_done(state, crtc); 7020 } 7021 7022 /* 7023 * Now that the vblank has passed, we can go ahead and program the 7024 * optimal watermarks on platforms that need two-step watermark 7025 * programming. 7026 * 7027 * TODO: Move this (and other cleanup) to an async worker eventually. 7028 */ 7029 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7030 new_crtc_state, i) { 7031 /* 7032 * Gen2 reports pipe underruns whenever all planes are disabled. 7033 * So re-enable underrun reporting after some planes get enabled. 7034 * 7035 * We do this before .optimize_watermarks() so that we have a 7036 * chance of catching underruns with the intermediate watermarks 7037 * vs. the new plane configuration. 7038 */ 7039 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state)) 7040 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 7041 7042 intel_optimize_watermarks(state, crtc); 7043 } 7044 7045 intel_dbuf_post_plane_update(state); 7046 intel_psr_post_plane_update(state); 7047 7048 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7049 intel_post_plane_update(state, crtc); 7050 7051 intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]); 7052 7053 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state); 7054 7055 /* Must be done after gamma readout due to HSW split gamma vs. IPS w/a */ 7056 hsw_ips_post_update(state, crtc); 7057 7058 /* 7059 * Activate DRRS after state readout to avoid 7060 * dp_m_n vs. dp_m2_n2 confusion on BDW+. 7061 */ 7062 intel_drrs_activate(new_crtc_state); 7063 7064 /* 7065 * DSB cleanup is done in cleanup_work aligning with framebuffer 7066 * cleanup. So copy and reset the dsb structure to sync with 7067 * commit_done and later do dsb cleanup in cleanup_work. 7068 * 7069 * FIXME get rid of this funny new->old swapping 7070 */ 7071 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb); 7072 } 7073 7074 /* Underruns don't always raise interrupts, so check manually */ 7075 intel_check_cpu_fifo_underruns(dev_priv); 7076 intel_check_pch_fifo_underruns(dev_priv); 7077 7078 if (state->modeset) 7079 intel_verify_planes(state); 7080 7081 intel_sagv_post_plane_update(state); 7082 7083 drm_atomic_helper_commit_hw_done(&state->base); 7084 7085 if (state->modeset) { 7086 /* As one of the primary mmio accessors, KMS has a high 7087 * likelihood of triggering bugs in unclaimed access. After we 7088 * finish modesetting, see if an error has been flagged, and if 7089 * so enable debugging for the next modeset - and hope we catch 7090 * the culprit. 7091 */ 7092 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); 7093 } 7094 intel_display_power_put(dev_priv, POWER_DOMAIN_DC_OFF, wakeref); 7095 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7096 7097 /* 7098 * Defer the cleanup of the old state to a separate worker to not 7099 * impede the current task (userspace for blocking modesets) that 7100 * are executed inline. For out-of-line asynchronous modesets/flips, 7101 * deferring to a new worker seems overkill, but we would place a 7102 * schedule point (cond_resched()) here anyway to keep latencies 7103 * down. 7104 */ 7105 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work); 7106 queue_work(system_highpri_wq, &state->base.commit_work); 7107 } 7108 7109 static void intel_atomic_commit_work(struct work_struct *work) 7110 { 7111 struct intel_atomic_state *state = 7112 container_of(work, struct intel_atomic_state, base.commit_work); 7113 7114 intel_atomic_commit_tail(state); 7115 } 7116 7117 static int 7118 intel_atomic_commit_ready(struct i915_sw_fence *fence, 7119 enum i915_sw_fence_notify notify) 7120 { 7121 struct intel_atomic_state *state = 7122 container_of(fence, struct intel_atomic_state, commit_ready); 7123 7124 switch (notify) { 7125 case FENCE_COMPLETE: 7126 /* we do blocking waits in the worker, nothing to do here */ 7127 break; 7128 case FENCE_FREE: 7129 { 7130 struct intel_atomic_helper *helper = 7131 &to_i915(state->base.dev)->display.atomic_helper; 7132 7133 if (llist_add(&state->freed, &helper->free_list)) 7134 schedule_work(&helper->free_work); 7135 break; 7136 } 7137 } 7138 7139 return NOTIFY_DONE; 7140 } 7141 7142 static void intel_atomic_track_fbs(struct intel_atomic_state *state) 7143 { 7144 struct intel_plane_state *old_plane_state, *new_plane_state; 7145 struct intel_plane *plane; 7146 int i; 7147 7148 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 7149 new_plane_state, i) 7150 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), 7151 to_intel_frontbuffer(new_plane_state->hw.fb), 7152 plane->frontbuffer_bit); 7153 } 7154 7155 int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state, 7156 bool nonblock) 7157 { 7158 struct intel_atomic_state *state = to_intel_atomic_state(_state); 7159 struct drm_i915_private *dev_priv = to_i915(dev); 7160 int ret = 0; 7161 7162 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 7163 7164 drm_atomic_state_get(&state->base); 7165 i915_sw_fence_init(&state->commit_ready, 7166 intel_atomic_commit_ready); 7167 7168 /* 7169 * The intel_legacy_cursor_update() fast path takes care 7170 * of avoiding the vblank waits for simple cursor 7171 * movement and flips. For cursor on/off and size changes, 7172 * we want to perform the vblank waits so that watermark 7173 * updates happen during the correct frames. Gen9+ have 7174 * double buffered watermarks and so shouldn't need this. 7175 * 7176 * Unset state->legacy_cursor_update before the call to 7177 * drm_atomic_helper_setup_commit() because otherwise 7178 * drm_atomic_helper_wait_for_flip_done() is a noop and 7179 * we get FIFO underruns because we didn't wait 7180 * for vblank. 7181 * 7182 * FIXME doing watermarks and fb cleanup from a vblank worker 7183 * (assuming we had any) would solve these problems. 7184 */ 7185 if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) { 7186 struct intel_crtc_state *new_crtc_state; 7187 struct intel_crtc *crtc; 7188 int i; 7189 7190 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7191 if (new_crtc_state->wm.need_postvbl_update || 7192 new_crtc_state->update_wm_post) 7193 state->base.legacy_cursor_update = false; 7194 } 7195 7196 ret = intel_atomic_prepare_commit(state); 7197 if (ret) { 7198 drm_dbg_atomic(&dev_priv->drm, 7199 "Preparing state failed with %i\n", ret); 7200 i915_sw_fence_commit(&state->commit_ready); 7201 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7202 return ret; 7203 } 7204 7205 ret = drm_atomic_helper_setup_commit(&state->base, nonblock); 7206 if (!ret) 7207 ret = drm_atomic_helper_swap_state(&state->base, true); 7208 if (!ret) 7209 intel_atomic_swap_global_state(state); 7210 7211 if (ret) { 7212 struct intel_crtc_state *new_crtc_state; 7213 struct intel_crtc *crtc; 7214 int i; 7215 7216 i915_sw_fence_commit(&state->commit_ready); 7217 7218 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7219 intel_color_cleanup_commit(new_crtc_state); 7220 7221 drm_atomic_helper_cleanup_planes(dev, &state->base); 7222 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7223 return ret; 7224 } 7225 intel_shared_dpll_swap_state(state); 7226 intel_atomic_track_fbs(state); 7227 7228 drm_atomic_state_get(&state->base); 7229 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work); 7230 7231 i915_sw_fence_commit(&state->commit_ready); 7232 if (nonblock && state->modeset) { 7233 queue_work(dev_priv->display.wq.modeset, &state->base.commit_work); 7234 } else if (nonblock) { 7235 queue_work(dev_priv->display.wq.flip, &state->base.commit_work); 7236 } else { 7237 if (state->modeset) 7238 flush_workqueue(dev_priv->display.wq.modeset); 7239 intel_atomic_commit_tail(state); 7240 } 7241 7242 return 0; 7243 } 7244 7245 /** 7246 * intel_plane_destroy - destroy a plane 7247 * @plane: plane to destroy 7248 * 7249 * Common destruction function for all types of planes (primary, cursor, 7250 * sprite). 7251 */ 7252 void intel_plane_destroy(struct drm_plane *plane) 7253 { 7254 drm_plane_cleanup(plane); 7255 kfree(to_intel_plane(plane)); 7256 } 7257 7258 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 7259 struct drm_file *file) 7260 { 7261 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; 7262 struct drm_crtc *drmmode_crtc; 7263 struct intel_crtc *crtc; 7264 7265 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id); 7266 if (!drmmode_crtc) 7267 return -ENOENT; 7268 7269 crtc = to_intel_crtc(drmmode_crtc); 7270 pipe_from_crtc_id->pipe = crtc->pipe; 7271 7272 return 0; 7273 } 7274 7275 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder) 7276 { 7277 struct drm_device *dev = encoder->base.dev; 7278 struct intel_encoder *source_encoder; 7279 u32 possible_clones = 0; 7280 7281 for_each_intel_encoder(dev, source_encoder) { 7282 if (encoders_cloneable(encoder, source_encoder)) 7283 possible_clones |= drm_encoder_mask(&source_encoder->base); 7284 } 7285 7286 return possible_clones; 7287 } 7288 7289 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder) 7290 { 7291 struct drm_device *dev = encoder->base.dev; 7292 struct intel_crtc *crtc; 7293 u32 possible_crtcs = 0; 7294 7295 for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask) 7296 possible_crtcs |= drm_crtc_mask(&crtc->base); 7297 7298 return possible_crtcs; 7299 } 7300 7301 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv) 7302 { 7303 if (!IS_MOBILE(dev_priv)) 7304 return false; 7305 7306 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0) 7307 return false; 7308 7309 if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE)) 7310 return false; 7311 7312 return true; 7313 } 7314 7315 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv) 7316 { 7317 if (DISPLAY_VER(dev_priv) >= 9) 7318 return false; 7319 7320 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) 7321 return false; 7322 7323 if (HAS_PCH_LPT_H(dev_priv) && 7324 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) 7325 return false; 7326 7327 /* DDI E can't be used if DDI A requires 4 lanes */ 7328 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 7329 return false; 7330 7331 if (!dev_priv->display.vbt.int_crt_support) 7332 return false; 7333 7334 return true; 7335 } 7336 7337 void intel_setup_outputs(struct drm_i915_private *dev_priv) 7338 { 7339 struct intel_encoder *encoder; 7340 bool dpd_is_edp = false; 7341 7342 intel_pps_unlock_regs_wa(dev_priv); 7343 7344 if (!HAS_DISPLAY(dev_priv)) 7345 return; 7346 7347 if (IS_METEORLAKE(dev_priv)) { 7348 intel_ddi_init(dev_priv, PORT_A); 7349 intel_ddi_init(dev_priv, PORT_B); 7350 intel_ddi_init(dev_priv, PORT_TC1); 7351 intel_ddi_init(dev_priv, PORT_TC2); 7352 intel_ddi_init(dev_priv, PORT_TC3); 7353 intel_ddi_init(dev_priv, PORT_TC4); 7354 } else if (IS_DG2(dev_priv)) { 7355 intel_ddi_init(dev_priv, PORT_A); 7356 intel_ddi_init(dev_priv, PORT_B); 7357 intel_ddi_init(dev_priv, PORT_C); 7358 intel_ddi_init(dev_priv, PORT_D_XELPD); 7359 intel_ddi_init(dev_priv, PORT_TC1); 7360 } else if (IS_ALDERLAKE_P(dev_priv)) { 7361 intel_ddi_init(dev_priv, PORT_A); 7362 intel_ddi_init(dev_priv, PORT_B); 7363 intel_ddi_init(dev_priv, PORT_TC1); 7364 intel_ddi_init(dev_priv, PORT_TC2); 7365 intel_ddi_init(dev_priv, PORT_TC3); 7366 intel_ddi_init(dev_priv, PORT_TC4); 7367 icl_dsi_init(dev_priv); 7368 } else if (IS_ALDERLAKE_S(dev_priv)) { 7369 intel_ddi_init(dev_priv, PORT_A); 7370 intel_ddi_init(dev_priv, PORT_TC1); 7371 intel_ddi_init(dev_priv, PORT_TC2); 7372 intel_ddi_init(dev_priv, PORT_TC3); 7373 intel_ddi_init(dev_priv, PORT_TC4); 7374 } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) { 7375 intel_ddi_init(dev_priv, PORT_A); 7376 intel_ddi_init(dev_priv, PORT_B); 7377 intel_ddi_init(dev_priv, PORT_TC1); 7378 intel_ddi_init(dev_priv, PORT_TC2); 7379 } else if (DISPLAY_VER(dev_priv) >= 12) { 7380 intel_ddi_init(dev_priv, PORT_A); 7381 intel_ddi_init(dev_priv, PORT_B); 7382 intel_ddi_init(dev_priv, PORT_TC1); 7383 intel_ddi_init(dev_priv, PORT_TC2); 7384 intel_ddi_init(dev_priv, PORT_TC3); 7385 intel_ddi_init(dev_priv, PORT_TC4); 7386 intel_ddi_init(dev_priv, PORT_TC5); 7387 intel_ddi_init(dev_priv, PORT_TC6); 7388 icl_dsi_init(dev_priv); 7389 } else if (IS_JSL_EHL(dev_priv)) { 7390 intel_ddi_init(dev_priv, PORT_A); 7391 intel_ddi_init(dev_priv, PORT_B); 7392 intel_ddi_init(dev_priv, PORT_C); 7393 intel_ddi_init(dev_priv, PORT_D); 7394 icl_dsi_init(dev_priv); 7395 } else if (DISPLAY_VER(dev_priv) == 11) { 7396 intel_ddi_init(dev_priv, PORT_A); 7397 intel_ddi_init(dev_priv, PORT_B); 7398 intel_ddi_init(dev_priv, PORT_C); 7399 intel_ddi_init(dev_priv, PORT_D); 7400 intel_ddi_init(dev_priv, PORT_E); 7401 intel_ddi_init(dev_priv, PORT_F); 7402 icl_dsi_init(dev_priv); 7403 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 7404 intel_ddi_init(dev_priv, PORT_A); 7405 intel_ddi_init(dev_priv, PORT_B); 7406 intel_ddi_init(dev_priv, PORT_C); 7407 vlv_dsi_init(dev_priv); 7408 } else if (DISPLAY_VER(dev_priv) >= 9) { 7409 intel_ddi_init(dev_priv, PORT_A); 7410 intel_ddi_init(dev_priv, PORT_B); 7411 intel_ddi_init(dev_priv, PORT_C); 7412 intel_ddi_init(dev_priv, PORT_D); 7413 intel_ddi_init(dev_priv, PORT_E); 7414 } else if (HAS_DDI(dev_priv)) { 7415 u32 found; 7416 7417 if (intel_ddi_crt_present(dev_priv)) 7418 intel_crt_init(dev_priv); 7419 7420 /* Haswell uses DDI functions to detect digital outputs. */ 7421 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 7422 if (found) 7423 intel_ddi_init(dev_priv, PORT_A); 7424 7425 found = intel_de_read(dev_priv, SFUSE_STRAP); 7426 if (found & SFUSE_STRAP_DDIB_DETECTED) 7427 intel_ddi_init(dev_priv, PORT_B); 7428 if (found & SFUSE_STRAP_DDIC_DETECTED) 7429 intel_ddi_init(dev_priv, PORT_C); 7430 if (found & SFUSE_STRAP_DDID_DETECTED) 7431 intel_ddi_init(dev_priv, PORT_D); 7432 if (found & SFUSE_STRAP_DDIF_DETECTED) 7433 intel_ddi_init(dev_priv, PORT_F); 7434 } else if (HAS_PCH_SPLIT(dev_priv)) { 7435 int found; 7436 7437 /* 7438 * intel_edp_init_connector() depends on this completing first, 7439 * to prevent the registration of both eDP and LVDS and the 7440 * incorrect sharing of the PPS. 7441 */ 7442 intel_lvds_init(dev_priv); 7443 intel_crt_init(dev_priv); 7444 7445 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D); 7446 7447 if (ilk_has_edp_a(dev_priv)) 7448 g4x_dp_init(dev_priv, DP_A, PORT_A); 7449 7450 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) { 7451 /* PCH SDVOB multiplex with HDMIB */ 7452 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); 7453 if (!found) 7454 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); 7455 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED)) 7456 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B); 7457 } 7458 7459 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED) 7460 g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); 7461 7462 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED) 7463 g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D); 7464 7465 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED) 7466 g4x_dp_init(dev_priv, PCH_DP_C, PORT_C); 7467 7468 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED) 7469 g4x_dp_init(dev_priv, PCH_DP_D, PORT_D); 7470 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 7471 bool has_edp, has_port; 7472 7473 if (IS_VALLEYVIEW(dev_priv) && dev_priv->display.vbt.int_crt_support) 7474 intel_crt_init(dev_priv); 7475 7476 /* 7477 * The DP_DETECTED bit is the latched state of the DDC 7478 * SDA pin at boot. However since eDP doesn't require DDC 7479 * (no way to plug in a DP->HDMI dongle) the DDC pins for 7480 * eDP ports may have been muxed to an alternate function. 7481 * Thus we can't rely on the DP_DETECTED bit alone to detect 7482 * eDP ports. Consult the VBT as well as DP_DETECTED to 7483 * detect eDP ports. 7484 * 7485 * Sadly the straps seem to be missing sometimes even for HDMI 7486 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap 7487 * and VBT for the presence of the port. Additionally we can't 7488 * trust the port type the VBT declares as we've seen at least 7489 * HDMI ports that the VBT claim are DP or eDP. 7490 */ 7491 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B); 7492 has_port = intel_bios_is_port_present(dev_priv, PORT_B); 7493 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port) 7494 has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B); 7495 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) 7496 g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); 7497 7498 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C); 7499 has_port = intel_bios_is_port_present(dev_priv, PORT_C); 7500 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port) 7501 has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C); 7502 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) 7503 g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); 7504 7505 if (IS_CHERRYVIEW(dev_priv)) { 7506 /* 7507 * eDP not supported on port D, 7508 * so no need to worry about it 7509 */ 7510 has_port = intel_bios_is_port_present(dev_priv, PORT_D); 7511 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port) 7512 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D); 7513 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port) 7514 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D); 7515 } 7516 7517 vlv_dsi_init(dev_priv); 7518 } else if (IS_PINEVIEW(dev_priv)) { 7519 intel_lvds_init(dev_priv); 7520 intel_crt_init(dev_priv); 7521 } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) { 7522 bool found = false; 7523 7524 if (IS_MOBILE(dev_priv)) 7525 intel_lvds_init(dev_priv); 7526 7527 intel_crt_init(dev_priv); 7528 7529 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 7530 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n"); 7531 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); 7532 if (!found && IS_G4X(dev_priv)) { 7533 drm_dbg_kms(&dev_priv->drm, 7534 "probing HDMI on SDVOB\n"); 7535 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); 7536 } 7537 7538 if (!found && IS_G4X(dev_priv)) 7539 g4x_dp_init(dev_priv, DP_B, PORT_B); 7540 } 7541 7542 /* Before G4X SDVOC doesn't have its own detect register */ 7543 7544 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 7545 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n"); 7546 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); 7547 } 7548 7549 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) { 7550 7551 if (IS_G4X(dev_priv)) { 7552 drm_dbg_kms(&dev_priv->drm, 7553 "probing HDMI on SDVOC\n"); 7554 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); 7555 } 7556 if (IS_G4X(dev_priv)) 7557 g4x_dp_init(dev_priv, DP_C, PORT_C); 7558 } 7559 7560 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED)) 7561 g4x_dp_init(dev_priv, DP_D, PORT_D); 7562 7563 if (SUPPORTS_TV(dev_priv)) 7564 intel_tv_init(dev_priv); 7565 } else if (DISPLAY_VER(dev_priv) == 2) { 7566 if (IS_I85X(dev_priv)) 7567 intel_lvds_init(dev_priv); 7568 7569 intel_crt_init(dev_priv); 7570 intel_dvo_init(dev_priv); 7571 } 7572 7573 for_each_intel_encoder(&dev_priv->drm, encoder) { 7574 encoder->base.possible_crtcs = 7575 intel_encoder_possible_crtcs(encoder); 7576 encoder->base.possible_clones = 7577 intel_encoder_possible_clones(encoder); 7578 } 7579 7580 intel_init_pch_refclk(dev_priv); 7581 7582 drm_helper_move_panel_connectors_to_head(&dev_priv->drm); 7583 } 7584 7585 static int max_dotclock(struct drm_i915_private *i915) 7586 { 7587 int max_dotclock = i915->max_dotclk_freq; 7588 7589 /* icl+ might use bigjoiner */ 7590 if (DISPLAY_VER(i915) >= 11) 7591 max_dotclock *= 2; 7592 7593 return max_dotclock; 7594 } 7595 7596 enum drm_mode_status intel_mode_valid(struct drm_device *dev, 7597 const struct drm_display_mode *mode) 7598 { 7599 struct drm_i915_private *dev_priv = to_i915(dev); 7600 int hdisplay_max, htotal_max; 7601 int vdisplay_max, vtotal_max; 7602 7603 /* 7604 * Can't reject DBLSCAN here because Xorg ddxen can add piles 7605 * of DBLSCAN modes to the output's mode list when they detect 7606 * the scaling mode property on the connector. And they don't 7607 * ask the kernel to validate those modes in any way until 7608 * modeset time at which point the client gets a protocol error. 7609 * So in order to not upset those clients we silently ignore the 7610 * DBLSCAN flag on such connectors. For other connectors we will 7611 * reject modes with the DBLSCAN flag in encoder->compute_config(). 7612 * And we always reject DBLSCAN modes in connector->mode_valid() 7613 * as we never want such modes on the connector's mode list. 7614 */ 7615 7616 if (mode->vscan > 1) 7617 return MODE_NO_VSCAN; 7618 7619 if (mode->flags & DRM_MODE_FLAG_HSKEW) 7620 return MODE_H_ILLEGAL; 7621 7622 if (mode->flags & (DRM_MODE_FLAG_CSYNC | 7623 DRM_MODE_FLAG_NCSYNC | 7624 DRM_MODE_FLAG_PCSYNC)) 7625 return MODE_HSYNC; 7626 7627 if (mode->flags & (DRM_MODE_FLAG_BCAST | 7628 DRM_MODE_FLAG_PIXMUX | 7629 DRM_MODE_FLAG_CLKDIV2)) 7630 return MODE_BAD; 7631 7632 /* 7633 * Reject clearly excessive dotclocks early to 7634 * avoid having to worry about huge integers later. 7635 */ 7636 if (mode->clock > max_dotclock(dev_priv)) 7637 return MODE_CLOCK_HIGH; 7638 7639 /* Transcoder timing limits */ 7640 if (DISPLAY_VER(dev_priv) >= 11) { 7641 hdisplay_max = 16384; 7642 vdisplay_max = 8192; 7643 htotal_max = 16384; 7644 vtotal_max = 8192; 7645 } else if (DISPLAY_VER(dev_priv) >= 9 || 7646 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 7647 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ 7648 vdisplay_max = 4096; 7649 htotal_max = 8192; 7650 vtotal_max = 8192; 7651 } else if (DISPLAY_VER(dev_priv) >= 3) { 7652 hdisplay_max = 4096; 7653 vdisplay_max = 4096; 7654 htotal_max = 8192; 7655 vtotal_max = 8192; 7656 } else { 7657 hdisplay_max = 2048; 7658 vdisplay_max = 2048; 7659 htotal_max = 4096; 7660 vtotal_max = 4096; 7661 } 7662 7663 if (mode->hdisplay > hdisplay_max || 7664 mode->hsync_start > htotal_max || 7665 mode->hsync_end > htotal_max || 7666 mode->htotal > htotal_max) 7667 return MODE_H_ILLEGAL; 7668 7669 if (mode->vdisplay > vdisplay_max || 7670 mode->vsync_start > vtotal_max || 7671 mode->vsync_end > vtotal_max || 7672 mode->vtotal > vtotal_max) 7673 return MODE_V_ILLEGAL; 7674 7675 if (DISPLAY_VER(dev_priv) >= 5) { 7676 if (mode->hdisplay < 64 || 7677 mode->htotal - mode->hdisplay < 32) 7678 return MODE_H_ILLEGAL; 7679 7680 if (mode->vtotal - mode->vdisplay < 5) 7681 return MODE_V_ILLEGAL; 7682 } else { 7683 if (mode->htotal - mode->hdisplay < 32) 7684 return MODE_H_ILLEGAL; 7685 7686 if (mode->vtotal - mode->vdisplay < 3) 7687 return MODE_V_ILLEGAL; 7688 } 7689 7690 /* 7691 * Cantiga+ cannot handle modes with a hsync front porch of 0. 7692 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. 7693 */ 7694 if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) && 7695 mode->hsync_start == mode->hdisplay) 7696 return MODE_H_ILLEGAL; 7697 7698 return MODE_OK; 7699 } 7700 7701 enum drm_mode_status 7702 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 7703 const struct drm_display_mode *mode, 7704 bool bigjoiner) 7705 { 7706 int plane_width_max, plane_height_max; 7707 7708 /* 7709 * intel_mode_valid() should be 7710 * sufficient on older platforms. 7711 */ 7712 if (DISPLAY_VER(dev_priv) < 9) 7713 return MODE_OK; 7714 7715 /* 7716 * Most people will probably want a fullscreen 7717 * plane so let's not advertize modes that are 7718 * too big for that. 7719 */ 7720 if (DISPLAY_VER(dev_priv) >= 11) { 7721 plane_width_max = 5120 << bigjoiner; 7722 plane_height_max = 4320; 7723 } else { 7724 plane_width_max = 5120; 7725 plane_height_max = 4096; 7726 } 7727 7728 if (mode->hdisplay > plane_width_max) 7729 return MODE_H_ILLEGAL; 7730 7731 if (mode->vdisplay > plane_height_max) 7732 return MODE_V_ILLEGAL; 7733 7734 return MODE_OK; 7735 } 7736 7737 static const struct intel_display_funcs skl_display_funcs = { 7738 .get_pipe_config = hsw_get_pipe_config, 7739 .crtc_enable = hsw_crtc_enable, 7740 .crtc_disable = hsw_crtc_disable, 7741 .commit_modeset_enables = skl_commit_modeset_enables, 7742 .get_initial_plane_config = skl_get_initial_plane_config, 7743 }; 7744 7745 static const struct intel_display_funcs ddi_display_funcs = { 7746 .get_pipe_config = hsw_get_pipe_config, 7747 .crtc_enable = hsw_crtc_enable, 7748 .crtc_disable = hsw_crtc_disable, 7749 .commit_modeset_enables = intel_commit_modeset_enables, 7750 .get_initial_plane_config = i9xx_get_initial_plane_config, 7751 }; 7752 7753 static const struct intel_display_funcs pch_split_display_funcs = { 7754 .get_pipe_config = ilk_get_pipe_config, 7755 .crtc_enable = ilk_crtc_enable, 7756 .crtc_disable = ilk_crtc_disable, 7757 .commit_modeset_enables = intel_commit_modeset_enables, 7758 .get_initial_plane_config = i9xx_get_initial_plane_config, 7759 }; 7760 7761 static const struct intel_display_funcs vlv_display_funcs = { 7762 .get_pipe_config = i9xx_get_pipe_config, 7763 .crtc_enable = valleyview_crtc_enable, 7764 .crtc_disable = i9xx_crtc_disable, 7765 .commit_modeset_enables = intel_commit_modeset_enables, 7766 .get_initial_plane_config = i9xx_get_initial_plane_config, 7767 }; 7768 7769 static const struct intel_display_funcs i9xx_display_funcs = { 7770 .get_pipe_config = i9xx_get_pipe_config, 7771 .crtc_enable = i9xx_crtc_enable, 7772 .crtc_disable = i9xx_crtc_disable, 7773 .commit_modeset_enables = intel_commit_modeset_enables, 7774 .get_initial_plane_config = i9xx_get_initial_plane_config, 7775 }; 7776 7777 /** 7778 * intel_init_display_hooks - initialize the display modesetting hooks 7779 * @dev_priv: device private 7780 */ 7781 void intel_init_display_hooks(struct drm_i915_private *dev_priv) 7782 { 7783 if (DISPLAY_VER(dev_priv) >= 9) { 7784 dev_priv->display.funcs.display = &skl_display_funcs; 7785 } else if (HAS_DDI(dev_priv)) { 7786 dev_priv->display.funcs.display = &ddi_display_funcs; 7787 } else if (HAS_PCH_SPLIT(dev_priv)) { 7788 dev_priv->display.funcs.display = &pch_split_display_funcs; 7789 } else if (IS_CHERRYVIEW(dev_priv) || 7790 IS_VALLEYVIEW(dev_priv)) { 7791 dev_priv->display.funcs.display = &vlv_display_funcs; 7792 } else { 7793 dev_priv->display.funcs.display = &i9xx_display_funcs; 7794 } 7795 } 7796 7797 int intel_initial_commit(struct drm_device *dev) 7798 { 7799 struct drm_atomic_state *state = NULL; 7800 struct drm_modeset_acquire_ctx ctx; 7801 struct intel_crtc *crtc; 7802 int ret = 0; 7803 7804 state = drm_atomic_state_alloc(dev); 7805 if (!state) 7806 return -ENOMEM; 7807 7808 drm_modeset_acquire_init(&ctx, 0); 7809 7810 state->acquire_ctx = &ctx; 7811 to_intel_atomic_state(state)->internal = true; 7812 7813 retry: 7814 for_each_intel_crtc(dev, crtc) { 7815 struct intel_crtc_state *crtc_state = 7816 intel_atomic_get_crtc_state(state, crtc); 7817 7818 if (IS_ERR(crtc_state)) { 7819 ret = PTR_ERR(crtc_state); 7820 goto out; 7821 } 7822 7823 if (crtc_state->hw.active) { 7824 struct intel_encoder *encoder; 7825 7826 ret = drm_atomic_add_affected_planes(state, &crtc->base); 7827 if (ret) 7828 goto out; 7829 7830 /* 7831 * FIXME hack to force a LUT update to avoid the 7832 * plane update forcing the pipe gamma on without 7833 * having a proper LUT loaded. Remove once we 7834 * have readout for pipe gamma enable. 7835 */ 7836 crtc_state->uapi.color_mgmt_changed = true; 7837 7838 for_each_intel_encoder_mask(dev, encoder, 7839 crtc_state->uapi.encoder_mask) { 7840 if (encoder->initial_fastset_check && 7841 !encoder->initial_fastset_check(encoder, crtc_state)) { 7842 ret = drm_atomic_add_affected_connectors(state, 7843 &crtc->base); 7844 if (ret) 7845 goto out; 7846 } 7847 } 7848 } 7849 } 7850 7851 ret = drm_atomic_commit(state); 7852 7853 out: 7854 if (ret == -EDEADLK) { 7855 drm_atomic_state_clear(state); 7856 drm_modeset_backoff(&ctx); 7857 goto retry; 7858 } 7859 7860 drm_atomic_state_put(state); 7861 7862 drm_modeset_drop_locks(&ctx); 7863 drm_modeset_acquire_fini(&ctx); 7864 7865 return ret; 7866 } 7867 7868 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 7869 { 7870 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 7871 enum transcoder cpu_transcoder = (enum transcoder)pipe; 7872 /* 640x480@60Hz, ~25175 kHz */ 7873 struct dpll clock = { 7874 .m1 = 18, 7875 .m2 = 7, 7876 .p1 = 13, 7877 .p2 = 4, 7878 .n = 2, 7879 }; 7880 u32 dpll, fp; 7881 int i; 7882 7883 drm_WARN_ON(&dev_priv->drm, 7884 i9xx_calc_dpll_params(48000, &clock) != 25154); 7885 7886 drm_dbg_kms(&dev_priv->drm, 7887 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n", 7888 pipe_name(pipe), clock.vco, clock.dot); 7889 7890 fp = i9xx_dpll_compute_fp(&clock); 7891 dpll = DPLL_DVO_2X_MODE | 7892 DPLL_VGA_MODE_DIS | 7893 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | 7894 PLL_P2_DIVIDE_BY_4 | 7895 PLL_REF_INPUT_DREFCLK | 7896 DPLL_VCO_ENABLE; 7897 7898 intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder), 7899 HACTIVE(640 - 1) | HTOTAL(800 - 1)); 7900 intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder), 7901 HBLANK_START(640 - 1) | HBLANK_END(800 - 1)); 7902 intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder), 7903 HSYNC_START(656 - 1) | HSYNC_END(752 - 1)); 7904 intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder), 7905 VACTIVE(480 - 1) | VTOTAL(525 - 1)); 7906 intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), 7907 VBLANK_START(480 - 1) | VBLANK_END(525 - 1)); 7908 intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder), 7909 VSYNC_START(490 - 1) | VSYNC_END(492 - 1)); 7910 intel_de_write(dev_priv, PIPESRC(pipe), 7911 PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1)); 7912 7913 intel_de_write(dev_priv, FP0(pipe), fp); 7914 intel_de_write(dev_priv, FP1(pipe), fp); 7915 7916 /* 7917 * Apparently we need to have VGA mode enabled prior to changing 7918 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 7919 * dividers, even though the register value does change. 7920 */ 7921 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); 7922 intel_de_write(dev_priv, DPLL(pipe), dpll); 7923 7924 /* Wait for the clocks to stabilize. */ 7925 intel_de_posting_read(dev_priv, DPLL(pipe)); 7926 udelay(150); 7927 7928 /* The pixel multiplier can only be updated once the 7929 * DPLL is enabled and the clocks are stable. 7930 * 7931 * So write it again. 7932 */ 7933 intel_de_write(dev_priv, DPLL(pipe), dpll); 7934 7935 /* We do this three times for luck */ 7936 for (i = 0; i < 3 ; i++) { 7937 intel_de_write(dev_priv, DPLL(pipe), dpll); 7938 intel_de_posting_read(dev_priv, DPLL(pipe)); 7939 udelay(150); /* wait for warmup */ 7940 } 7941 7942 intel_de_write(dev_priv, TRANSCONF(pipe), TRANSCONF_ENABLE); 7943 intel_de_posting_read(dev_priv, TRANSCONF(pipe)); 7944 7945 intel_wait_for_pipe_scanline_moving(crtc); 7946 } 7947 7948 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 7949 { 7950 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 7951 7952 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n", 7953 pipe_name(pipe)); 7954 7955 drm_WARN_ON(&dev_priv->drm, 7956 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE); 7957 drm_WARN_ON(&dev_priv->drm, 7958 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE); 7959 drm_WARN_ON(&dev_priv->drm, 7960 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE); 7961 drm_WARN_ON(&dev_priv->drm, 7962 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK); 7963 drm_WARN_ON(&dev_priv->drm, 7964 intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK); 7965 7966 intel_de_write(dev_priv, TRANSCONF(pipe), 0); 7967 intel_de_posting_read(dev_priv, TRANSCONF(pipe)); 7968 7969 intel_wait_for_pipe_scanline_stopped(crtc); 7970 7971 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); 7972 intel_de_posting_read(dev_priv, DPLL(pipe)); 7973 } 7974 7975 void intel_hpd_poll_fini(struct drm_i915_private *i915) 7976 { 7977 struct intel_connector *connector; 7978 struct drm_connector_list_iter conn_iter; 7979 7980 /* Kill all the work that may have been queued by hpd. */ 7981 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 7982 for_each_intel_connector_iter(connector, &conn_iter) { 7983 if (connector->modeset_retry_work.func) 7984 cancel_work_sync(&connector->modeset_retry_work); 7985 if (connector->hdcp.shim) { 7986 cancel_delayed_work_sync(&connector->hdcp.check_work); 7987 cancel_work_sync(&connector->hdcp.prop_work); 7988 } 7989 } 7990 drm_connector_list_iter_end(&conn_iter); 7991 } 7992 7993 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915) 7994 { 7995 return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915); 7996 } 7997