1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <acpi/video.h> 28 #include <linux/i2c.h> 29 #include <linux/input.h> 30 #include <linux/intel-iommu.h> 31 #include <linux/kernel.h> 32 #include <linux/module.h> 33 #include <linux/dma-resv.h> 34 #include <linux/slab.h> 35 #include <linux/string_helpers.h> 36 #include <linux/vga_switcheroo.h> 37 38 #include <drm/drm_atomic.h> 39 #include <drm/drm_atomic_helper.h> 40 #include <drm/drm_atomic_uapi.h> 41 #include <drm/drm_damage_helper.h> 42 #include <drm/dp/drm_dp_helper.h> 43 #include <drm/drm_edid.h> 44 #include <drm/drm_fourcc.h> 45 #include <drm/drm_plane_helper.h> 46 #include <drm/drm_privacy_screen_consumer.h> 47 #include <drm/drm_probe_helper.h> 48 #include <drm/drm_rect.h> 49 50 #include "display/intel_audio.h" 51 #include "display/intel_crt.h" 52 #include "display/intel_ddi.h" 53 #include "display/intel_display_debugfs.h" 54 #include "display/intel_dp.h" 55 #include "display/intel_dp_mst.h" 56 #include "display/intel_dpll.h" 57 #include "display/intel_dpll_mgr.h" 58 #include "display/intel_drrs.h" 59 #include "display/intel_dsi.h" 60 #include "display/intel_dvo.h" 61 #include "display/intel_fb.h" 62 #include "display/intel_gmbus.h" 63 #include "display/intel_hdmi.h" 64 #include "display/intel_lvds.h" 65 #include "display/intel_sdvo.h" 66 #include "display/intel_snps_phy.h" 67 #include "display/intel_tv.h" 68 #include "display/intel_vdsc.h" 69 #include "display/intel_vrr.h" 70 71 #include "gem/i915_gem_lmem.h" 72 #include "gem/i915_gem_object.h" 73 74 #include "gt/gen8_ppgtt.h" 75 76 #include "g4x_dp.h" 77 #include "g4x_hdmi.h" 78 #include "hsw_ips.h" 79 #include "i915_drv.h" 80 #include "icl_dsi.h" 81 #include "intel_acpi.h" 82 #include "intel_atomic.h" 83 #include "intel_atomic_plane.h" 84 #include "intel_bw.h" 85 #include "intel_cdclk.h" 86 #include "intel_color.h" 87 #include "intel_crtc.h" 88 #include "intel_de.h" 89 #include "intel_display_types.h" 90 #include "intel_dmc.h" 91 #include "intel_dp_link_training.h" 92 #include "intel_dpt.h" 93 #include "intel_fbc.h" 94 #include "intel_fbdev.h" 95 #include "intel_fdi.h" 96 #include "intel_fifo_underrun.h" 97 #include "intel_frontbuffer.h" 98 #include "intel_hdcp.h" 99 #include "intel_hotplug.h" 100 #include "intel_overlay.h" 101 #include "intel_panel.h" 102 #include "intel_pch_display.h" 103 #include "intel_pch_refclk.h" 104 #include "intel_pcode.h" 105 #include "intel_pipe_crc.h" 106 #include "intel_plane_initial.h" 107 #include "intel_pm.h" 108 #include "intel_pps.h" 109 #include "intel_psr.h" 110 #include "intel_quirks.h" 111 #include "intel_sprite.h" 112 #include "intel_tc.h" 113 #include "intel_vga.h" 114 #include "i9xx_plane.h" 115 #include "skl_scaler.h" 116 #include "skl_universal_plane.h" 117 #include "vlv_dsi.h" 118 #include "vlv_dsi_pll.h" 119 #include "vlv_dsi_regs.h" 120 #include "vlv_sideband.h" 121 122 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state); 123 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state); 124 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state); 125 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state); 126 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state); 127 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state); 128 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state); 129 static void intel_modeset_setup_hw_state(struct drm_device *dev, 130 struct drm_modeset_acquire_ctx *ctx); 131 132 /** 133 * intel_update_watermarks - update FIFO watermark values based on current modes 134 * @dev_priv: i915 device 135 * 136 * Calculate watermark values for the various WM regs based on current mode 137 * and plane configuration. 138 * 139 * There are several cases to deal with here: 140 * - normal (i.e. non-self-refresh) 141 * - self-refresh (SR) mode 142 * - lines are large relative to FIFO size (buffer can hold up to 2) 143 * - lines are small relative to FIFO size (buffer can hold more than 2 144 * lines), so need to account for TLB latency 145 * 146 * The normal calculation is: 147 * watermark = dotclock * bytes per pixel * latency 148 * where latency is platform & configuration dependent (we assume pessimal 149 * values here). 150 * 151 * The SR calculation is: 152 * watermark = (trunc(latency/line time)+1) * surface width * 153 * bytes per pixel 154 * where 155 * line time = htotal / dotclock 156 * surface width = hdisplay for normal plane and 64 for cursor 157 * and latency is assumed to be high, as above. 158 * 159 * The final value programmed to the register should always be rounded up, 160 * and include an extra 2 entries to account for clock crossings. 161 * 162 * We don't use the sprite, so we can ignore that. And on Crestline we have 163 * to set the non-SR watermarks to 8. 164 */ 165 static void intel_update_watermarks(struct drm_i915_private *dev_priv) 166 { 167 if (dev_priv->wm_disp->update_wm) 168 dev_priv->wm_disp->update_wm(dev_priv); 169 } 170 171 static int intel_compute_pipe_wm(struct intel_atomic_state *state, 172 struct intel_crtc *crtc) 173 { 174 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 175 if (dev_priv->wm_disp->compute_pipe_wm) 176 return dev_priv->wm_disp->compute_pipe_wm(state, crtc); 177 return 0; 178 } 179 180 static int intel_compute_intermediate_wm(struct intel_atomic_state *state, 181 struct intel_crtc *crtc) 182 { 183 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 184 if (!dev_priv->wm_disp->compute_intermediate_wm) 185 return 0; 186 if (drm_WARN_ON(&dev_priv->drm, 187 !dev_priv->wm_disp->compute_pipe_wm)) 188 return 0; 189 return dev_priv->wm_disp->compute_intermediate_wm(state, crtc); 190 } 191 192 static bool intel_initial_watermarks(struct intel_atomic_state *state, 193 struct intel_crtc *crtc) 194 { 195 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 196 if (dev_priv->wm_disp->initial_watermarks) { 197 dev_priv->wm_disp->initial_watermarks(state, crtc); 198 return true; 199 } 200 return false; 201 } 202 203 static void intel_atomic_update_watermarks(struct intel_atomic_state *state, 204 struct intel_crtc *crtc) 205 { 206 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 207 if (dev_priv->wm_disp->atomic_update_watermarks) 208 dev_priv->wm_disp->atomic_update_watermarks(state, crtc); 209 } 210 211 static void intel_optimize_watermarks(struct intel_atomic_state *state, 212 struct intel_crtc *crtc) 213 { 214 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 215 if (dev_priv->wm_disp->optimize_watermarks) 216 dev_priv->wm_disp->optimize_watermarks(state, crtc); 217 } 218 219 static int intel_compute_global_watermarks(struct intel_atomic_state *state) 220 { 221 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 222 if (dev_priv->wm_disp->compute_global_watermarks) 223 return dev_priv->wm_disp->compute_global_watermarks(state); 224 return 0; 225 } 226 227 /* returns HPLL frequency in kHz */ 228 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) 229 { 230 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; 231 232 /* Obtain SKU information */ 233 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & 234 CCK_FUSE_HPLL_FREQ_MASK; 235 236 return vco_freq[hpll_freq] * 1000; 237 } 238 239 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 240 const char *name, u32 reg, int ref_freq) 241 { 242 u32 val; 243 int divider; 244 245 val = vlv_cck_read(dev_priv, reg); 246 divider = val & CCK_FREQUENCY_VALUES; 247 248 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != 249 (divider << CCK_FREQUENCY_STATUS_SHIFT), 250 "%s change in progress\n", name); 251 252 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); 253 } 254 255 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 256 const char *name, u32 reg) 257 { 258 int hpll; 259 260 vlv_cck_get(dev_priv); 261 262 if (dev_priv->hpll_freq == 0) 263 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); 264 265 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); 266 267 vlv_cck_put(dev_priv); 268 269 return hpll; 270 } 271 272 static void intel_update_czclk(struct drm_i915_private *dev_priv) 273 { 274 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) 275 return; 276 277 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", 278 CCK_CZ_CLOCK_CONTROL); 279 280 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", 281 dev_priv->czclk_freq); 282 } 283 284 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state) 285 { 286 return (crtc_state->active_planes & 287 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0; 288 } 289 290 /* WA Display #0827: Gen9:all */ 291 static void 292 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) 293 { 294 if (enable) 295 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 296 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS); 297 else 298 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 299 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS)); 300 } 301 302 /* Wa_2006604312:icl,ehl */ 303 static void 304 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 305 bool enable) 306 { 307 if (enable) 308 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 309 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS); 310 else 311 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 312 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS); 313 } 314 315 /* Wa_1604331009:icl,jsl,ehl */ 316 static void 317 icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 318 bool enable) 319 { 320 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), CURSOR_GATING_DIS, 321 enable ? CURSOR_GATING_DIS : 0); 322 } 323 324 static bool 325 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state) 326 { 327 return crtc_state->master_transcoder != INVALID_TRANSCODER; 328 } 329 330 static bool 331 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state) 332 { 333 return crtc_state->sync_mode_slaves_mask != 0; 334 } 335 336 bool 337 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state) 338 { 339 return is_trans_port_sync_master(crtc_state) || 340 is_trans_port_sync_slave(crtc_state); 341 } 342 343 static enum pipe bigjoiner_master_pipe(const struct intel_crtc_state *crtc_state) 344 { 345 return ffs(crtc_state->bigjoiner_pipes) - 1; 346 } 347 348 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state) 349 { 350 if (crtc_state->bigjoiner_pipes) 351 return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state)); 352 else 353 return 0; 354 } 355 356 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state) 357 { 358 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 359 360 return crtc_state->bigjoiner_pipes && 361 crtc->pipe != bigjoiner_master_pipe(crtc_state); 362 } 363 364 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state) 365 { 366 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 367 368 return crtc_state->bigjoiner_pipes && 369 crtc->pipe == bigjoiner_master_pipe(crtc_state); 370 } 371 372 static int intel_bigjoiner_num_pipes(const struct intel_crtc_state *crtc_state) 373 { 374 return hweight8(crtc_state->bigjoiner_pipes); 375 } 376 377 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state) 378 { 379 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 380 381 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 382 return intel_crtc_for_pipe(i915, bigjoiner_master_pipe(crtc_state)); 383 else 384 return to_intel_crtc(crtc_state->uapi.crtc); 385 } 386 387 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv, 388 enum pipe pipe) 389 { 390 i915_reg_t reg = PIPEDSL(pipe); 391 u32 line1, line2; 392 393 line1 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK; 394 msleep(5); 395 line2 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK; 396 397 return line1 != line2; 398 } 399 400 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state) 401 { 402 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 403 enum pipe pipe = crtc->pipe; 404 405 /* Wait for the display line to settle/start moving */ 406 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100)) 407 drm_err(&dev_priv->drm, 408 "pipe %c scanline %s wait timed out\n", 409 pipe_name(pipe), str_on_off(state)); 410 } 411 412 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc) 413 { 414 wait_for_pipe_scanline_moving(crtc, false); 415 } 416 417 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc) 418 { 419 wait_for_pipe_scanline_moving(crtc, true); 420 } 421 422 static void 423 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) 424 { 425 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 426 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 427 428 if (DISPLAY_VER(dev_priv) >= 4) { 429 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 430 431 /* Wait for the Pipe State to go off */ 432 if (intel_de_wait_for_clear(dev_priv, PIPECONF(cpu_transcoder), 433 PIPECONF_STATE_ENABLE, 100)) 434 drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n"); 435 } else { 436 intel_wait_for_pipe_scanline_stopped(crtc); 437 } 438 } 439 440 void assert_transcoder(struct drm_i915_private *dev_priv, 441 enum transcoder cpu_transcoder, bool state) 442 { 443 bool cur_state; 444 enum intel_display_power_domain power_domain; 445 intel_wakeref_t wakeref; 446 447 /* we keep both pipes enabled on 830 */ 448 if (IS_I830(dev_priv)) 449 state = true; 450 451 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 452 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 453 if (wakeref) { 454 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); 455 cur_state = !!(val & PIPECONF_ENABLE); 456 457 intel_display_power_put(dev_priv, power_domain, wakeref); 458 } else { 459 cur_state = false; 460 } 461 462 I915_STATE_WARN(cur_state != state, 463 "transcoder %s assertion failure (expected %s, current %s)\n", 464 transcoder_name(cpu_transcoder), 465 str_on_off(state), str_on_off(cur_state)); 466 } 467 468 static void assert_plane(struct intel_plane *plane, bool state) 469 { 470 enum pipe pipe; 471 bool cur_state; 472 473 cur_state = plane->get_hw_state(plane, &pipe); 474 475 I915_STATE_WARN(cur_state != state, 476 "%s assertion failure (expected %s, current %s)\n", 477 plane->base.name, str_on_off(state), 478 str_on_off(cur_state)); 479 } 480 481 #define assert_plane_enabled(p) assert_plane(p, true) 482 #define assert_plane_disabled(p) assert_plane(p, false) 483 484 static void assert_planes_disabled(struct intel_crtc *crtc) 485 { 486 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 487 struct intel_plane *plane; 488 489 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) 490 assert_plane_disabled(plane); 491 } 492 493 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 494 struct intel_digital_port *dig_port, 495 unsigned int expected_mask) 496 { 497 u32 port_mask; 498 i915_reg_t dpll_reg; 499 500 switch (dig_port->base.port) { 501 case PORT_B: 502 port_mask = DPLL_PORTB_READY_MASK; 503 dpll_reg = DPLL(0); 504 break; 505 case PORT_C: 506 port_mask = DPLL_PORTC_READY_MASK; 507 dpll_reg = DPLL(0); 508 expected_mask <<= 4; 509 break; 510 case PORT_D: 511 port_mask = DPLL_PORTD_READY_MASK; 512 dpll_reg = DPIO_PHY_STATUS; 513 break; 514 default: 515 BUG(); 516 } 517 518 if (intel_de_wait_for_register(dev_priv, dpll_reg, 519 port_mask, expected_mask, 1000)) 520 drm_WARN(&dev_priv->drm, 1, 521 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", 522 dig_port->base.base.base.id, dig_port->base.base.name, 523 intel_de_read(dev_priv, dpll_reg) & port_mask, 524 expected_mask); 525 } 526 527 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) 528 { 529 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 530 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 531 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 532 enum pipe pipe = crtc->pipe; 533 i915_reg_t reg; 534 u32 val; 535 536 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe)); 537 538 assert_planes_disabled(crtc); 539 540 /* 541 * A pipe without a PLL won't actually be able to drive bits from 542 * a plane. On ILK+ the pipe PLLs are integrated, so we don't 543 * need the check. 544 */ 545 if (HAS_GMCH(dev_priv)) { 546 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI)) 547 assert_dsi_pll_enabled(dev_priv); 548 else 549 assert_pll_enabled(dev_priv, pipe); 550 } else { 551 if (new_crtc_state->has_pch_encoder) { 552 /* if driving the PCH, we need FDI enabled */ 553 assert_fdi_rx_pll_enabled(dev_priv, 554 intel_crtc_pch_transcoder(crtc)); 555 assert_fdi_tx_pll_enabled(dev_priv, 556 (enum pipe) cpu_transcoder); 557 } 558 /* FIXME: assert CPU port conditions for SNB+ */ 559 } 560 561 /* Wa_22012358565:adl-p */ 562 if (DISPLAY_VER(dev_priv) == 13) 563 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe), 564 0, PIPE_ARB_USE_PROG_SLOTS); 565 566 reg = PIPECONF(cpu_transcoder); 567 val = intel_de_read(dev_priv, reg); 568 if (val & PIPECONF_ENABLE) { 569 /* we keep both pipes enabled on 830 */ 570 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv)); 571 return; 572 } 573 574 intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE); 575 intel_de_posting_read(dev_priv, reg); 576 577 /* 578 * Until the pipe starts PIPEDSL reads will return a stale value, 579 * which causes an apparent vblank timestamp jump when PIPEDSL 580 * resets to its proper value. That also messes up the frame count 581 * when it's derived from the timestamps. So let's wait for the 582 * pipe to start properly before we call drm_crtc_vblank_on() 583 */ 584 if (intel_crtc_max_vblank_count(new_crtc_state) == 0) 585 intel_wait_for_pipe_scanline_moving(crtc); 586 } 587 588 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) 589 { 590 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 591 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 592 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 593 enum pipe pipe = crtc->pipe; 594 i915_reg_t reg; 595 u32 val; 596 597 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe)); 598 599 /* 600 * Make sure planes won't keep trying to pump pixels to us, 601 * or we might hang the display. 602 */ 603 assert_planes_disabled(crtc); 604 605 reg = PIPECONF(cpu_transcoder); 606 val = intel_de_read(dev_priv, reg); 607 if ((val & PIPECONF_ENABLE) == 0) 608 return; 609 610 /* 611 * Double wide has implications for planes 612 * so best keep it disabled when not needed. 613 */ 614 if (old_crtc_state->double_wide) 615 val &= ~PIPECONF_DOUBLE_WIDE; 616 617 /* Don't disable pipe or pipe PLLs if needed */ 618 if (!IS_I830(dev_priv)) 619 val &= ~PIPECONF_ENABLE; 620 621 if (DISPLAY_VER(dev_priv) >= 12) 622 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 623 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 624 625 intel_de_write(dev_priv, reg, val); 626 if ((val & PIPECONF_ENABLE) == 0) 627 intel_wait_for_pipe_off(old_crtc_state); 628 } 629 630 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) 631 { 632 unsigned int size = 0; 633 int i; 634 635 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) 636 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width; 637 638 return size; 639 } 640 641 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info) 642 { 643 unsigned int size = 0; 644 int i; 645 646 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) { 647 unsigned int plane_size; 648 649 if (rem_info->plane[i].linear) 650 plane_size = rem_info->plane[i].size; 651 else 652 plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height; 653 654 if (plane_size == 0) 655 continue; 656 657 if (rem_info->plane_alignment) 658 size = ALIGN(size, rem_info->plane_alignment); 659 660 size += plane_size; 661 } 662 663 return size; 664 } 665 666 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) 667 { 668 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 669 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 670 671 return DISPLAY_VER(dev_priv) < 4 || 672 (plane->fbc && 673 plane_state->view.gtt.type == I915_GGTT_VIEW_NORMAL); 674 } 675 676 /* 677 * Convert the x/y offsets into a linear offset. 678 * Only valid with 0/180 degree rotation, which is fine since linear 679 * offset is only used with linear buffers on pre-hsw and tiled buffers 680 * with gen2/3, and 90/270 degree rotations isn't supported on any of them. 681 */ 682 u32 intel_fb_xy_to_linear(int x, int y, 683 const struct intel_plane_state *state, 684 int color_plane) 685 { 686 const struct drm_framebuffer *fb = state->hw.fb; 687 unsigned int cpp = fb->format->cpp[color_plane]; 688 unsigned int pitch = state->view.color_plane[color_plane].mapping_stride; 689 690 return y * pitch + x * cpp; 691 } 692 693 /* 694 * Add the x/y offsets derived from fb->offsets[] to the user 695 * specified plane src x/y offsets. The resulting x/y offsets 696 * specify the start of scanout from the beginning of the gtt mapping. 697 */ 698 void intel_add_fb_offsets(int *x, int *y, 699 const struct intel_plane_state *state, 700 int color_plane) 701 702 { 703 *x += state->view.color_plane[color_plane].x; 704 *y += state->view.color_plane[color_plane].y; 705 } 706 707 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 708 u32 pixel_format, u64 modifier) 709 { 710 struct intel_crtc *crtc; 711 struct intel_plane *plane; 712 713 if (!HAS_DISPLAY(dev_priv)) 714 return 0; 715 716 /* 717 * We assume the primary plane for pipe A has 718 * the highest stride limits of them all, 719 * if in case pipe A is disabled, use the first pipe from pipe_mask. 720 */ 721 crtc = intel_first_crtc(dev_priv); 722 if (!crtc) 723 return 0; 724 725 plane = to_intel_plane(crtc->base.primary); 726 727 return plane->max_stride(plane, pixel_format, modifier, 728 DRM_MODE_ROTATE_0); 729 } 730 731 static void 732 intel_set_plane_visible(struct intel_crtc_state *crtc_state, 733 struct intel_plane_state *plane_state, 734 bool visible) 735 { 736 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 737 738 plane_state->uapi.visible = visible; 739 740 if (visible) 741 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base); 742 else 743 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base); 744 } 745 746 static void fixup_plane_bitmasks(struct intel_crtc_state *crtc_state) 747 { 748 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 749 struct drm_plane *plane; 750 751 /* 752 * Active_planes aliases if multiple "primary" or cursor planes 753 * have been used on the same (or wrong) pipe. plane_mask uses 754 * unique ids, hence we can use that to reconstruct active_planes. 755 */ 756 crtc_state->enabled_planes = 0; 757 crtc_state->active_planes = 0; 758 759 drm_for_each_plane_mask(plane, &dev_priv->drm, 760 crtc_state->uapi.plane_mask) { 761 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id); 762 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id); 763 } 764 } 765 766 void intel_plane_disable_noatomic(struct intel_crtc *crtc, 767 struct intel_plane *plane) 768 { 769 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 770 struct intel_crtc_state *crtc_state = 771 to_intel_crtc_state(crtc->base.state); 772 struct intel_plane_state *plane_state = 773 to_intel_plane_state(plane->base.state); 774 775 drm_dbg_kms(&dev_priv->drm, 776 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n", 777 plane->base.base.id, plane->base.name, 778 crtc->base.base.id, crtc->base.name); 779 780 intel_set_plane_visible(crtc_state, plane_state, false); 781 fixup_plane_bitmasks(crtc_state); 782 crtc_state->data_rate[plane->id] = 0; 783 crtc_state->min_cdclk[plane->id] = 0; 784 785 if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 && 786 hsw_ips_disable(crtc_state)) { 787 crtc_state->ips_enabled = false; 788 intel_crtc_wait_for_next_vblank(crtc); 789 } 790 791 /* 792 * Vblank time updates from the shadow to live plane control register 793 * are blocked if the memory self-refresh mode is active at that 794 * moment. So to make sure the plane gets truly disabled, disable 795 * first the self-refresh mode. The self-refresh enable bit in turn 796 * will be checked/applied by the HW only at the next frame start 797 * event which is after the vblank start event, so we need to have a 798 * wait-for-vblank between disabling the plane and the pipe. 799 */ 800 if (HAS_GMCH(dev_priv) && 801 intel_set_memory_cxsr(dev_priv, false)) 802 intel_crtc_wait_for_next_vblank(crtc); 803 804 /* 805 * Gen2 reports pipe underruns whenever all planes are disabled. 806 * So disable underrun reporting before all the planes get disabled. 807 */ 808 if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes) 809 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); 810 811 intel_plane_disable_arm(plane, crtc_state); 812 intel_crtc_wait_for_next_vblank(crtc); 813 } 814 815 unsigned int 816 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state) 817 { 818 int x = 0, y = 0; 819 820 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, 821 plane_state->view.color_plane[0].offset, 0); 822 823 return y; 824 } 825 826 static int 827 __intel_display_resume(struct drm_device *dev, 828 struct drm_atomic_state *state, 829 struct drm_modeset_acquire_ctx *ctx) 830 { 831 struct drm_crtc_state *crtc_state; 832 struct drm_crtc *crtc; 833 int i, ret; 834 835 intel_modeset_setup_hw_state(dev, ctx); 836 intel_vga_redisable(to_i915(dev)); 837 838 if (!state) 839 return 0; 840 841 /* 842 * We've duplicated the state, pointers to the old state are invalid. 843 * 844 * Don't attempt to use the old state until we commit the duplicated state. 845 */ 846 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 847 /* 848 * Force recalculation even if we restore 849 * current state. With fast modeset this may not result 850 * in a modeset when the state is compatible. 851 */ 852 crtc_state->mode_changed = true; 853 } 854 855 /* ignore any reset values/BIOS leftovers in the WM registers */ 856 if (!HAS_GMCH(to_i915(dev))) 857 to_intel_atomic_state(state)->skip_intermediate_wm = true; 858 859 ret = drm_atomic_helper_commit_duplicated_state(state, ctx); 860 861 drm_WARN_ON(dev, ret == -EDEADLK); 862 return ret; 863 } 864 865 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) 866 { 867 return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display && 868 intel_has_gpu_reset(to_gt(dev_priv))); 869 } 870 871 void intel_display_prepare_reset(struct drm_i915_private *dev_priv) 872 { 873 struct drm_device *dev = &dev_priv->drm; 874 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; 875 struct drm_atomic_state *state; 876 int ret; 877 878 if (!HAS_DISPLAY(dev_priv)) 879 return; 880 881 /* reset doesn't touch the display */ 882 if (!dev_priv->params.force_reset_modeset_test && 883 !gpu_reset_clobbers_display(dev_priv)) 884 return; 885 886 /* We have a modeset vs reset deadlock, defensively unbreak it. */ 887 set_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags); 888 smp_mb__after_atomic(); 889 wake_up_bit(&to_gt(dev_priv)->reset.flags, I915_RESET_MODESET); 890 891 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) { 892 drm_dbg_kms(&dev_priv->drm, 893 "Modeset potentially stuck, unbreaking through wedging\n"); 894 intel_gt_set_wedged(to_gt(dev_priv)); 895 } 896 897 /* 898 * Need mode_config.mutex so that we don't 899 * trample ongoing ->detect() and whatnot. 900 */ 901 mutex_lock(&dev->mode_config.mutex); 902 drm_modeset_acquire_init(ctx, 0); 903 while (1) { 904 ret = drm_modeset_lock_all_ctx(dev, ctx); 905 if (ret != -EDEADLK) 906 break; 907 908 drm_modeset_backoff(ctx); 909 } 910 /* 911 * Disabling the crtcs gracefully seems nicer. Also the 912 * g33 docs say we should at least disable all the planes. 913 */ 914 state = drm_atomic_helper_duplicate_state(dev, ctx); 915 if (IS_ERR(state)) { 916 ret = PTR_ERR(state); 917 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n", 918 ret); 919 return; 920 } 921 922 ret = drm_atomic_helper_disable_all(dev, ctx); 923 if (ret) { 924 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", 925 ret); 926 drm_atomic_state_put(state); 927 return; 928 } 929 930 dev_priv->modeset_restore_state = state; 931 state->acquire_ctx = ctx; 932 } 933 934 void intel_display_finish_reset(struct drm_i915_private *dev_priv) 935 { 936 struct drm_device *dev = &dev_priv->drm; 937 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; 938 struct drm_atomic_state *state; 939 int ret; 940 941 if (!HAS_DISPLAY(dev_priv)) 942 return; 943 944 /* reset doesn't touch the display */ 945 if (!test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags)) 946 return; 947 948 state = fetch_and_zero(&dev_priv->modeset_restore_state); 949 if (!state) 950 goto unlock; 951 952 /* reset doesn't touch the display */ 953 if (!gpu_reset_clobbers_display(dev_priv)) { 954 /* for testing only restore the display */ 955 ret = __intel_display_resume(dev, state, ctx); 956 if (ret) 957 drm_err(&dev_priv->drm, 958 "Restoring old state failed with %i\n", ret); 959 } else { 960 /* 961 * The display has been reset as well, 962 * so need a full re-initialization. 963 */ 964 intel_pps_unlock_regs_wa(dev_priv); 965 intel_modeset_init_hw(dev_priv); 966 intel_init_clock_gating(dev_priv); 967 intel_hpd_init(dev_priv); 968 969 ret = __intel_display_resume(dev, state, ctx); 970 if (ret) 971 drm_err(&dev_priv->drm, 972 "Restoring old state failed with %i\n", ret); 973 974 intel_hpd_poll_disable(dev_priv); 975 } 976 977 drm_atomic_state_put(state); 978 unlock: 979 drm_modeset_drop_locks(ctx); 980 drm_modeset_acquire_fini(ctx); 981 mutex_unlock(&dev->mode_config.mutex); 982 983 clear_bit_unlock(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags); 984 } 985 986 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) 987 { 988 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 989 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 990 enum pipe pipe = crtc->pipe; 991 u32 tmp; 992 993 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe)); 994 995 /* 996 * Display WA #1153: icl 997 * enable hardware to bypass the alpha math 998 * and rounding for per-pixel values 00 and 0xff 999 */ 1000 tmp |= PER_PIXEL_ALPHA_BYPASS_EN; 1001 /* 1002 * Display WA # 1605353570: icl 1003 * Set the pixel rounding bit to 1 for allowing 1004 * passthrough of Frame buffer pixels unmodified 1005 * across pipe 1006 */ 1007 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU; 1008 1009 /* 1010 * Underrun recovery must always be disabled on display 13+. 1011 * DG2 chicken bit meaning is inverted compared to other platforms. 1012 */ 1013 if (IS_DG2(dev_priv)) 1014 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2; 1015 else if (DISPLAY_VER(dev_priv) >= 13) 1016 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP; 1017 1018 /* Wa_14010547955:dg2 */ 1019 if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER)) 1020 tmp |= DG2_RENDER_CCSTAG_4_3_EN; 1021 1022 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp); 1023 } 1024 1025 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) 1026 { 1027 struct drm_crtc *crtc; 1028 bool cleanup_done; 1029 1030 drm_for_each_crtc(crtc, &dev_priv->drm) { 1031 struct drm_crtc_commit *commit; 1032 spin_lock(&crtc->commit_lock); 1033 commit = list_first_entry_or_null(&crtc->commit_list, 1034 struct drm_crtc_commit, commit_entry); 1035 cleanup_done = commit ? 1036 try_wait_for_completion(&commit->cleanup_done) : true; 1037 spin_unlock(&crtc->commit_lock); 1038 1039 if (cleanup_done) 1040 continue; 1041 1042 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc)); 1043 1044 return true; 1045 } 1046 1047 return false; 1048 } 1049 1050 /* 1051 * Finds the encoder associated with the given CRTC. This can only be 1052 * used when we know that the CRTC isn't feeding multiple encoders! 1053 */ 1054 struct intel_encoder * 1055 intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 1056 const struct intel_crtc_state *crtc_state) 1057 { 1058 const struct drm_connector_state *connector_state; 1059 const struct drm_connector *connector; 1060 struct intel_encoder *encoder = NULL; 1061 struct intel_crtc *master_crtc; 1062 int num_encoders = 0; 1063 int i; 1064 1065 master_crtc = intel_master_crtc(crtc_state); 1066 1067 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 1068 if (connector_state->crtc != &master_crtc->base) 1069 continue; 1070 1071 encoder = to_intel_encoder(connector_state->best_encoder); 1072 num_encoders++; 1073 } 1074 1075 drm_WARN(encoder->base.dev, num_encoders != 1, 1076 "%d encoders for pipe %c\n", 1077 num_encoders, pipe_name(master_crtc->pipe)); 1078 1079 return encoder; 1080 } 1081 1082 static void cpt_verify_modeset(struct drm_i915_private *dev_priv, 1083 enum pipe pipe) 1084 { 1085 i915_reg_t dslreg = PIPEDSL(pipe); 1086 u32 temp; 1087 1088 temp = intel_de_read(dev_priv, dslreg); 1089 udelay(500); 1090 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) { 1091 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) 1092 drm_err(&dev_priv->drm, 1093 "mode set failed: pipe %c stuck\n", 1094 pipe_name(pipe)); 1095 } 1096 } 1097 1098 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state) 1099 { 1100 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1101 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1102 const struct drm_rect *dst = &crtc_state->pch_pfit.dst; 1103 enum pipe pipe = crtc->pipe; 1104 int width = drm_rect_width(dst); 1105 int height = drm_rect_height(dst); 1106 int x = dst->x1; 1107 int y = dst->y1; 1108 1109 if (!crtc_state->pch_pfit.enabled) 1110 return; 1111 1112 /* Force use of hard-coded filter coefficients 1113 * as some pre-programmed values are broken, 1114 * e.g. x201. 1115 */ 1116 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) 1117 intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE | 1118 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe)); 1119 else 1120 intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE | 1121 PF_FILTER_MED_3x3); 1122 intel_de_write(dev_priv, PF_WIN_POS(pipe), x << 16 | y); 1123 intel_de_write(dev_priv, PF_WIN_SZ(pipe), width << 16 | height); 1124 } 1125 1126 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc) 1127 { 1128 if (crtc->overlay) 1129 (void) intel_overlay_switch_off(crtc->overlay); 1130 1131 /* Let userspace switch the overlay on again. In most cases userspace 1132 * has to recompute where to put it anyway. 1133 */ 1134 } 1135 1136 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state) 1137 { 1138 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1139 1140 if (!crtc_state->nv12_planes) 1141 return false; 1142 1143 /* WA Display #0827: Gen9:all */ 1144 if (DISPLAY_VER(dev_priv) == 9) 1145 return true; 1146 1147 return false; 1148 } 1149 1150 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state) 1151 { 1152 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1153 1154 /* Wa_2006604312:icl,ehl */ 1155 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11) 1156 return true; 1157 1158 return false; 1159 } 1160 1161 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state) 1162 { 1163 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1164 1165 /* Wa_1604331009:icl,jsl,ehl */ 1166 if (is_hdr_mode(crtc_state) && 1167 crtc_state->active_planes & BIT(PLANE_CURSOR) && 1168 DISPLAY_VER(dev_priv) == 11) 1169 return true; 1170 1171 return false; 1172 } 1173 1174 static void intel_async_flip_vtd_wa(struct drm_i915_private *i915, 1175 enum pipe pipe, bool enable) 1176 { 1177 if (DISPLAY_VER(i915) == 9) { 1178 /* 1179 * "Plane N strech max must be programmed to 11b (x1) 1180 * when Async flips are enabled on that plane." 1181 */ 1182 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 1183 SKL_PLANE1_STRETCH_MAX_MASK, 1184 enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8); 1185 } else { 1186 /* Also needed on HSW/BDW albeit undocumented */ 1187 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 1188 HSW_PRI_STRETCH_MAX_MASK, 1189 enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8); 1190 } 1191 } 1192 1193 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state) 1194 { 1195 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1196 1197 return crtc_state->uapi.async_flip && intel_vtd_active(i915) && 1198 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915)); 1199 } 1200 1201 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state, 1202 const struct intel_crtc_state *new_crtc_state) 1203 { 1204 return (!old_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)) && 1205 new_crtc_state->active_planes; 1206 } 1207 1208 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state, 1209 const struct intel_crtc_state *new_crtc_state) 1210 { 1211 return old_crtc_state->active_planes && 1212 (!new_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)); 1213 } 1214 1215 static void intel_post_plane_update(struct intel_atomic_state *state, 1216 struct intel_crtc *crtc) 1217 { 1218 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1219 const struct intel_crtc_state *old_crtc_state = 1220 intel_atomic_get_old_crtc_state(state, crtc); 1221 const struct intel_crtc_state *new_crtc_state = 1222 intel_atomic_get_new_crtc_state(state, crtc); 1223 enum pipe pipe = crtc->pipe; 1224 1225 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); 1226 1227 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) 1228 intel_update_watermarks(dev_priv); 1229 1230 hsw_ips_post_update(state, crtc); 1231 intel_fbc_post_update(state, crtc); 1232 1233 if (needs_async_flip_vtd_wa(old_crtc_state) && 1234 !needs_async_flip_vtd_wa(new_crtc_state)) 1235 intel_async_flip_vtd_wa(dev_priv, pipe, false); 1236 1237 if (needs_nv12_wa(old_crtc_state) && 1238 !needs_nv12_wa(new_crtc_state)) 1239 skl_wa_827(dev_priv, pipe, false); 1240 1241 if (needs_scalerclk_wa(old_crtc_state) && 1242 !needs_scalerclk_wa(new_crtc_state)) 1243 icl_wa_scalerclkgating(dev_priv, pipe, false); 1244 1245 if (needs_cursorclk_wa(old_crtc_state) && 1246 !needs_cursorclk_wa(new_crtc_state)) 1247 icl_wa_cursorclkgating(dev_priv, pipe, false); 1248 1249 intel_drrs_enable(new_crtc_state); 1250 } 1251 1252 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state, 1253 struct intel_crtc *crtc) 1254 { 1255 const struct intel_crtc_state *crtc_state = 1256 intel_atomic_get_new_crtc_state(state, crtc); 1257 u8 update_planes = crtc_state->update_planes; 1258 const struct intel_plane_state *plane_state; 1259 struct intel_plane *plane; 1260 int i; 1261 1262 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1263 if (plane->pipe == crtc->pipe && 1264 update_planes & BIT(plane->id)) 1265 plane->enable_flip_done(plane); 1266 } 1267 } 1268 1269 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state, 1270 struct intel_crtc *crtc) 1271 { 1272 const struct intel_crtc_state *crtc_state = 1273 intel_atomic_get_new_crtc_state(state, crtc); 1274 u8 update_planes = crtc_state->update_planes; 1275 const struct intel_plane_state *plane_state; 1276 struct intel_plane *plane; 1277 int i; 1278 1279 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1280 if (plane->pipe == crtc->pipe && 1281 update_planes & BIT(plane->id)) 1282 plane->disable_flip_done(plane); 1283 } 1284 } 1285 1286 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state, 1287 struct intel_crtc *crtc) 1288 { 1289 const struct intel_crtc_state *old_crtc_state = 1290 intel_atomic_get_old_crtc_state(state, crtc); 1291 const struct intel_crtc_state *new_crtc_state = 1292 intel_atomic_get_new_crtc_state(state, crtc); 1293 u8 update_planes = new_crtc_state->update_planes; 1294 const struct intel_plane_state *old_plane_state; 1295 struct intel_plane *plane; 1296 bool need_vbl_wait = false; 1297 int i; 1298 1299 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1300 if (plane->need_async_flip_disable_wa && 1301 plane->pipe == crtc->pipe && 1302 update_planes & BIT(plane->id)) { 1303 /* 1304 * Apart from the async flip bit we want to 1305 * preserve the old state for the plane. 1306 */ 1307 plane->async_flip(plane, old_crtc_state, 1308 old_plane_state, false); 1309 need_vbl_wait = true; 1310 } 1311 } 1312 1313 if (need_vbl_wait) 1314 intel_crtc_wait_for_next_vblank(crtc); 1315 } 1316 1317 static void intel_pre_plane_update(struct intel_atomic_state *state, 1318 struct intel_crtc *crtc) 1319 { 1320 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1321 const struct intel_crtc_state *old_crtc_state = 1322 intel_atomic_get_old_crtc_state(state, crtc); 1323 const struct intel_crtc_state *new_crtc_state = 1324 intel_atomic_get_new_crtc_state(state, crtc); 1325 enum pipe pipe = crtc->pipe; 1326 1327 intel_drrs_disable(old_crtc_state); 1328 1329 intel_psr_pre_plane_update(state, crtc); 1330 1331 if (hsw_ips_pre_update(state, crtc)) 1332 intel_crtc_wait_for_next_vblank(crtc); 1333 1334 if (intel_fbc_pre_update(state, crtc)) 1335 intel_crtc_wait_for_next_vblank(crtc); 1336 1337 if (!needs_async_flip_vtd_wa(old_crtc_state) && 1338 needs_async_flip_vtd_wa(new_crtc_state)) 1339 intel_async_flip_vtd_wa(dev_priv, pipe, true); 1340 1341 /* Display WA 827 */ 1342 if (!needs_nv12_wa(old_crtc_state) && 1343 needs_nv12_wa(new_crtc_state)) 1344 skl_wa_827(dev_priv, pipe, true); 1345 1346 /* Wa_2006604312:icl,ehl */ 1347 if (!needs_scalerclk_wa(old_crtc_state) && 1348 needs_scalerclk_wa(new_crtc_state)) 1349 icl_wa_scalerclkgating(dev_priv, pipe, true); 1350 1351 /* Wa_1604331009:icl,jsl,ehl */ 1352 if (!needs_cursorclk_wa(old_crtc_state) && 1353 needs_cursorclk_wa(new_crtc_state)) 1354 icl_wa_cursorclkgating(dev_priv, pipe, true); 1355 1356 /* 1357 * Vblank time updates from the shadow to live plane control register 1358 * are blocked if the memory self-refresh mode is active at that 1359 * moment. So to make sure the plane gets truly disabled, disable 1360 * first the self-refresh mode. The self-refresh enable bit in turn 1361 * will be checked/applied by the HW only at the next frame start 1362 * event which is after the vblank start event, so we need to have a 1363 * wait-for-vblank between disabling the plane and the pipe. 1364 */ 1365 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active && 1366 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) 1367 intel_crtc_wait_for_next_vblank(crtc); 1368 1369 /* 1370 * IVB workaround: must disable low power watermarks for at least 1371 * one frame before enabling scaling. LP watermarks can be re-enabled 1372 * when scaling is disabled. 1373 * 1374 * WaCxSRDisabledForSpriteScaling:ivb 1375 */ 1376 if (old_crtc_state->hw.active && 1377 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv)) 1378 intel_crtc_wait_for_next_vblank(crtc); 1379 1380 /* 1381 * If we're doing a modeset we don't need to do any 1382 * pre-vblank watermark programming here. 1383 */ 1384 if (!intel_crtc_needs_modeset(new_crtc_state)) { 1385 /* 1386 * For platforms that support atomic watermarks, program the 1387 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these 1388 * will be the intermediate values that are safe for both pre- and 1389 * post- vblank; when vblank happens, the 'active' values will be set 1390 * to the final 'target' values and we'll do this again to get the 1391 * optimal watermarks. For gen9+ platforms, the values we program here 1392 * will be the final target values which will get automatically latched 1393 * at vblank time; no further programming will be necessary. 1394 * 1395 * If a platform hasn't been transitioned to atomic watermarks yet, 1396 * we'll continue to update watermarks the old way, if flags tell 1397 * us to. 1398 */ 1399 if (!intel_initial_watermarks(state, crtc)) 1400 if (new_crtc_state->update_wm_pre) 1401 intel_update_watermarks(dev_priv); 1402 } 1403 1404 /* 1405 * Gen2 reports pipe underruns whenever all planes are disabled. 1406 * So disable underrun reporting before all the planes get disabled. 1407 * 1408 * We do this after .initial_watermarks() so that we have a 1409 * chance of catching underruns with the intermediate watermarks 1410 * vs. the old plane configuration. 1411 */ 1412 if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state)) 1413 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1414 1415 /* 1416 * WA for platforms where async address update enable bit 1417 * is double buffered and only latched at start of vblank. 1418 */ 1419 if (old_crtc_state->uapi.async_flip && !new_crtc_state->uapi.async_flip) 1420 intel_crtc_async_flip_disable_wa(state, crtc); 1421 } 1422 1423 static void intel_crtc_disable_planes(struct intel_atomic_state *state, 1424 struct intel_crtc *crtc) 1425 { 1426 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1427 const struct intel_crtc_state *new_crtc_state = 1428 intel_atomic_get_new_crtc_state(state, crtc); 1429 unsigned int update_mask = new_crtc_state->update_planes; 1430 const struct intel_plane_state *old_plane_state; 1431 struct intel_plane *plane; 1432 unsigned fb_bits = 0; 1433 int i; 1434 1435 intel_crtc_dpms_overlay_disable(crtc); 1436 1437 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1438 if (crtc->pipe != plane->pipe || 1439 !(update_mask & BIT(plane->id))) 1440 continue; 1441 1442 intel_plane_disable_arm(plane, new_crtc_state); 1443 1444 if (old_plane_state->uapi.visible) 1445 fb_bits |= plane->frontbuffer_bit; 1446 } 1447 1448 intel_frontbuffer_flip(dev_priv, fb_bits); 1449 } 1450 1451 /* 1452 * intel_connector_primary_encoder - get the primary encoder for a connector 1453 * @connector: connector for which to return the encoder 1454 * 1455 * Returns the primary encoder for a connector. There is a 1:1 mapping from 1456 * all connectors to their encoder, except for DP-MST connectors which have 1457 * both a virtual and a primary encoder. These DP-MST primary encoders can be 1458 * pointed to by as many DP-MST connectors as there are pipes. 1459 */ 1460 static struct intel_encoder * 1461 intel_connector_primary_encoder(struct intel_connector *connector) 1462 { 1463 struct intel_encoder *encoder; 1464 1465 if (connector->mst_port) 1466 return &dp_to_dig_port(connector->mst_port)->base; 1467 1468 encoder = intel_attached_encoder(connector); 1469 drm_WARN_ON(connector->base.dev, !encoder); 1470 1471 return encoder; 1472 } 1473 1474 static void intel_encoders_update_prepare(struct intel_atomic_state *state) 1475 { 1476 struct drm_i915_private *i915 = to_i915(state->base.dev); 1477 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 1478 struct intel_crtc *crtc; 1479 struct drm_connector_state *new_conn_state; 1480 struct drm_connector *connector; 1481 int i; 1482 1483 /* 1484 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits. 1485 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook. 1486 */ 1487 if (i915->dpll.mgr) { 1488 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1489 if (intel_crtc_needs_modeset(new_crtc_state)) 1490 continue; 1491 1492 new_crtc_state->shared_dpll = old_crtc_state->shared_dpll; 1493 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state; 1494 } 1495 } 1496 1497 if (!state->modeset) 1498 return; 1499 1500 for_each_new_connector_in_state(&state->base, connector, new_conn_state, 1501 i) { 1502 struct intel_connector *intel_connector; 1503 struct intel_encoder *encoder; 1504 struct intel_crtc *crtc; 1505 1506 if (!intel_connector_needs_modeset(state, connector)) 1507 continue; 1508 1509 intel_connector = to_intel_connector(connector); 1510 encoder = intel_connector_primary_encoder(intel_connector); 1511 if (!encoder->update_prepare) 1512 continue; 1513 1514 crtc = new_conn_state->crtc ? 1515 to_intel_crtc(new_conn_state->crtc) : NULL; 1516 encoder->update_prepare(state, encoder, crtc); 1517 } 1518 } 1519 1520 static void intel_encoders_update_complete(struct intel_atomic_state *state) 1521 { 1522 struct drm_connector_state *new_conn_state; 1523 struct drm_connector *connector; 1524 int i; 1525 1526 if (!state->modeset) 1527 return; 1528 1529 for_each_new_connector_in_state(&state->base, connector, new_conn_state, 1530 i) { 1531 struct intel_connector *intel_connector; 1532 struct intel_encoder *encoder; 1533 struct intel_crtc *crtc; 1534 1535 if (!intel_connector_needs_modeset(state, connector)) 1536 continue; 1537 1538 intel_connector = to_intel_connector(connector); 1539 encoder = intel_connector_primary_encoder(intel_connector); 1540 if (!encoder->update_complete) 1541 continue; 1542 1543 crtc = new_conn_state->crtc ? 1544 to_intel_crtc(new_conn_state->crtc) : NULL; 1545 encoder->update_complete(state, encoder, crtc); 1546 } 1547 } 1548 1549 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state, 1550 struct intel_crtc *crtc) 1551 { 1552 const struct intel_crtc_state *crtc_state = 1553 intel_atomic_get_new_crtc_state(state, crtc); 1554 const struct drm_connector_state *conn_state; 1555 struct drm_connector *conn; 1556 int i; 1557 1558 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1559 struct intel_encoder *encoder = 1560 to_intel_encoder(conn_state->best_encoder); 1561 1562 if (conn_state->crtc != &crtc->base) 1563 continue; 1564 1565 if (encoder->pre_pll_enable) 1566 encoder->pre_pll_enable(state, encoder, 1567 crtc_state, conn_state); 1568 } 1569 } 1570 1571 static void intel_encoders_pre_enable(struct intel_atomic_state *state, 1572 struct intel_crtc *crtc) 1573 { 1574 const struct intel_crtc_state *crtc_state = 1575 intel_atomic_get_new_crtc_state(state, crtc); 1576 const struct drm_connector_state *conn_state; 1577 struct drm_connector *conn; 1578 int i; 1579 1580 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1581 struct intel_encoder *encoder = 1582 to_intel_encoder(conn_state->best_encoder); 1583 1584 if (conn_state->crtc != &crtc->base) 1585 continue; 1586 1587 if (encoder->pre_enable) 1588 encoder->pre_enable(state, encoder, 1589 crtc_state, conn_state); 1590 } 1591 } 1592 1593 static void intel_encoders_enable(struct intel_atomic_state *state, 1594 struct intel_crtc *crtc) 1595 { 1596 const struct intel_crtc_state *crtc_state = 1597 intel_atomic_get_new_crtc_state(state, crtc); 1598 const struct drm_connector_state *conn_state; 1599 struct drm_connector *conn; 1600 int i; 1601 1602 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1603 struct intel_encoder *encoder = 1604 to_intel_encoder(conn_state->best_encoder); 1605 1606 if (conn_state->crtc != &crtc->base) 1607 continue; 1608 1609 if (encoder->enable) 1610 encoder->enable(state, encoder, 1611 crtc_state, conn_state); 1612 intel_opregion_notify_encoder(encoder, true); 1613 } 1614 } 1615 1616 static void intel_encoders_disable(struct intel_atomic_state *state, 1617 struct intel_crtc *crtc) 1618 { 1619 const struct intel_crtc_state *old_crtc_state = 1620 intel_atomic_get_old_crtc_state(state, crtc); 1621 const struct drm_connector_state *old_conn_state; 1622 struct drm_connector *conn; 1623 int i; 1624 1625 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1626 struct intel_encoder *encoder = 1627 to_intel_encoder(old_conn_state->best_encoder); 1628 1629 if (old_conn_state->crtc != &crtc->base) 1630 continue; 1631 1632 intel_opregion_notify_encoder(encoder, false); 1633 if (encoder->disable) 1634 encoder->disable(state, encoder, 1635 old_crtc_state, old_conn_state); 1636 } 1637 } 1638 1639 static void intel_encoders_post_disable(struct intel_atomic_state *state, 1640 struct intel_crtc *crtc) 1641 { 1642 const struct intel_crtc_state *old_crtc_state = 1643 intel_atomic_get_old_crtc_state(state, crtc); 1644 const struct drm_connector_state *old_conn_state; 1645 struct drm_connector *conn; 1646 int i; 1647 1648 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1649 struct intel_encoder *encoder = 1650 to_intel_encoder(old_conn_state->best_encoder); 1651 1652 if (old_conn_state->crtc != &crtc->base) 1653 continue; 1654 1655 if (encoder->post_disable) 1656 encoder->post_disable(state, encoder, 1657 old_crtc_state, old_conn_state); 1658 } 1659 } 1660 1661 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state, 1662 struct intel_crtc *crtc) 1663 { 1664 const struct intel_crtc_state *old_crtc_state = 1665 intel_atomic_get_old_crtc_state(state, crtc); 1666 const struct drm_connector_state *old_conn_state; 1667 struct drm_connector *conn; 1668 int i; 1669 1670 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1671 struct intel_encoder *encoder = 1672 to_intel_encoder(old_conn_state->best_encoder); 1673 1674 if (old_conn_state->crtc != &crtc->base) 1675 continue; 1676 1677 if (encoder->post_pll_disable) 1678 encoder->post_pll_disable(state, encoder, 1679 old_crtc_state, old_conn_state); 1680 } 1681 } 1682 1683 static void intel_encoders_update_pipe(struct intel_atomic_state *state, 1684 struct intel_crtc *crtc) 1685 { 1686 const struct intel_crtc_state *crtc_state = 1687 intel_atomic_get_new_crtc_state(state, crtc); 1688 const struct drm_connector_state *conn_state; 1689 struct drm_connector *conn; 1690 int i; 1691 1692 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1693 struct intel_encoder *encoder = 1694 to_intel_encoder(conn_state->best_encoder); 1695 1696 if (conn_state->crtc != &crtc->base) 1697 continue; 1698 1699 if (encoder->update_pipe) 1700 encoder->update_pipe(state, encoder, 1701 crtc_state, conn_state); 1702 } 1703 } 1704 1705 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state) 1706 { 1707 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1708 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 1709 1710 plane->disable_arm(plane, crtc_state); 1711 } 1712 1713 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1714 { 1715 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1716 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1717 1718 if (crtc_state->has_pch_encoder) { 1719 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1720 &crtc_state->fdi_m_n); 1721 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1722 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1723 &crtc_state->dp_m_n); 1724 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1725 &crtc_state->dp_m2_n2); 1726 } 1727 1728 intel_set_transcoder_timings(crtc_state); 1729 1730 ilk_set_pipeconf(crtc_state); 1731 } 1732 1733 static void ilk_crtc_enable(struct intel_atomic_state *state, 1734 struct intel_crtc *crtc) 1735 { 1736 const struct intel_crtc_state *new_crtc_state = 1737 intel_atomic_get_new_crtc_state(state, crtc); 1738 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1739 enum pipe pipe = crtc->pipe; 1740 1741 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1742 return; 1743 1744 /* 1745 * Sometimes spurious CPU pipe underruns happen during FDI 1746 * training, at least with VGA+HDMI cloning. Suppress them. 1747 * 1748 * On ILK we get an occasional spurious CPU pipe underruns 1749 * between eDP port A enable and vdd enable. Also PCH port 1750 * enable seems to result in the occasional CPU pipe underrun. 1751 * 1752 * Spurious PCH underruns also occur during PCH enabling. 1753 */ 1754 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1755 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 1756 1757 ilk_configure_cpu_transcoder(new_crtc_state); 1758 1759 intel_set_pipe_src_size(new_crtc_state); 1760 1761 crtc->active = true; 1762 1763 intel_encoders_pre_enable(state, crtc); 1764 1765 if (new_crtc_state->has_pch_encoder) { 1766 ilk_pch_pre_enable(state, crtc); 1767 } else { 1768 assert_fdi_tx_disabled(dev_priv, pipe); 1769 assert_fdi_rx_disabled(dev_priv, pipe); 1770 } 1771 1772 ilk_pfit_enable(new_crtc_state); 1773 1774 /* 1775 * On ILK+ LUT must be loaded before the pipe is running but with 1776 * clocks enabled 1777 */ 1778 intel_color_load_luts(new_crtc_state); 1779 intel_color_commit(new_crtc_state); 1780 /* update DSPCNTR to configure gamma for pipe bottom color */ 1781 intel_disable_primary_plane(new_crtc_state); 1782 1783 intel_initial_watermarks(state, crtc); 1784 intel_enable_transcoder(new_crtc_state); 1785 1786 if (new_crtc_state->has_pch_encoder) 1787 ilk_pch_enable(state, crtc); 1788 1789 intel_crtc_vblank_on(new_crtc_state); 1790 1791 intel_encoders_enable(state, crtc); 1792 1793 if (HAS_PCH_CPT(dev_priv)) 1794 cpt_verify_modeset(dev_priv, pipe); 1795 1796 /* 1797 * Must wait for vblank to avoid spurious PCH FIFO underruns. 1798 * And a second vblank wait is needed at least on ILK with 1799 * some interlaced HDMI modes. Let's do the double wait always 1800 * in case there are more corner cases we don't know about. 1801 */ 1802 if (new_crtc_state->has_pch_encoder) { 1803 intel_crtc_wait_for_next_vblank(crtc); 1804 intel_crtc_wait_for_next_vblank(crtc); 1805 } 1806 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1807 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 1808 } 1809 1810 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, 1811 enum pipe pipe, bool apply) 1812 { 1813 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)); 1814 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS; 1815 1816 if (apply) 1817 val |= mask; 1818 else 1819 val &= ~mask; 1820 1821 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val); 1822 } 1823 1824 static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool joined_mbus) 1825 { 1826 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1827 enum pipe pipe = crtc->pipe; 1828 u32 val; 1829 1830 /* Wa_22010947358:adl-p */ 1831 if (IS_ALDERLAKE_P(dev_priv)) 1832 val = joined_mbus ? MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4); 1833 else 1834 val = MBUS_DBOX_A_CREDIT(2); 1835 1836 if (DISPLAY_VER(dev_priv) >= 12) { 1837 val |= MBUS_DBOX_BW_CREDIT(2); 1838 val |= MBUS_DBOX_B_CREDIT(12); 1839 } else { 1840 val |= MBUS_DBOX_BW_CREDIT(1); 1841 val |= MBUS_DBOX_B_CREDIT(8); 1842 } 1843 1844 intel_de_write(dev_priv, PIPE_MBUS_DBOX_CTL(pipe), val); 1845 } 1846 1847 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state) 1848 { 1849 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1850 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1851 1852 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe), 1853 HSW_LINETIME(crtc_state->linetime) | 1854 HSW_IPS_LINETIME(crtc_state->ips_linetime)); 1855 } 1856 1857 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) 1858 { 1859 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1860 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1861 i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder); 1862 u32 val; 1863 1864 val = intel_de_read(dev_priv, reg); 1865 val &= ~HSW_FRAME_START_DELAY_MASK; 1866 val |= HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 1867 intel_de_write(dev_priv, reg, val); 1868 } 1869 1870 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state, 1871 const struct intel_crtc_state *crtc_state) 1872 { 1873 struct intel_crtc *master_crtc = intel_master_crtc(crtc_state); 1874 1875 /* 1876 * Enable sequence steps 1-7 on bigjoiner master 1877 */ 1878 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1879 intel_encoders_pre_pll_enable(state, master_crtc); 1880 1881 if (crtc_state->shared_dpll) 1882 intel_enable_shared_dpll(crtc_state); 1883 1884 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1885 intel_encoders_pre_enable(state, master_crtc); 1886 } 1887 1888 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1889 { 1890 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1891 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1892 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1893 1894 if (crtc_state->has_pch_encoder) { 1895 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1896 &crtc_state->fdi_m_n); 1897 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1898 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1899 &crtc_state->dp_m_n); 1900 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1901 &crtc_state->dp_m2_n2); 1902 } 1903 1904 intel_set_transcoder_timings(crtc_state); 1905 1906 if (cpu_transcoder != TRANSCODER_EDP) 1907 intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder), 1908 crtc_state->pixel_multiplier - 1); 1909 1910 hsw_set_frame_start_delay(crtc_state); 1911 1912 hsw_set_transconf(crtc_state); 1913 } 1914 1915 static void hsw_crtc_enable(struct intel_atomic_state *state, 1916 struct intel_crtc *crtc) 1917 { 1918 const struct intel_crtc_state *new_crtc_state = 1919 intel_atomic_get_new_crtc_state(state, crtc); 1920 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1921 enum pipe pipe = crtc->pipe, hsw_workaround_pipe; 1922 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 1923 bool psl_clkgate_wa; 1924 1925 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1926 return; 1927 1928 if (!new_crtc_state->bigjoiner_pipes) { 1929 intel_encoders_pre_pll_enable(state, crtc); 1930 1931 if (new_crtc_state->shared_dpll) 1932 intel_enable_shared_dpll(new_crtc_state); 1933 1934 intel_encoders_pre_enable(state, crtc); 1935 } else { 1936 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state); 1937 } 1938 1939 intel_dsc_enable(new_crtc_state); 1940 1941 if (DISPLAY_VER(dev_priv) >= 13) 1942 intel_uncompressed_joiner_enable(new_crtc_state); 1943 1944 intel_set_pipe_src_size(new_crtc_state); 1945 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 1946 bdw_set_pipemisc(new_crtc_state); 1947 1948 if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) && 1949 !transcoder_is_dsi(cpu_transcoder)) 1950 hsw_configure_cpu_transcoder(new_crtc_state); 1951 1952 crtc->active = true; 1953 1954 /* Display WA #1180: WaDisableScalarClockGating: glk */ 1955 psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 && 1956 new_crtc_state->pch_pfit.enabled; 1957 if (psl_clkgate_wa) 1958 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true); 1959 1960 if (DISPLAY_VER(dev_priv) >= 9) 1961 skl_pfit_enable(new_crtc_state); 1962 else 1963 ilk_pfit_enable(new_crtc_state); 1964 1965 /* 1966 * On ILK+ LUT must be loaded before the pipe is running but with 1967 * clocks enabled 1968 */ 1969 intel_color_load_luts(new_crtc_state); 1970 intel_color_commit(new_crtc_state); 1971 /* update DSPCNTR to configure gamma/csc for pipe bottom color */ 1972 if (DISPLAY_VER(dev_priv) < 9) 1973 intel_disable_primary_plane(new_crtc_state); 1974 1975 hsw_set_linetime_wm(new_crtc_state); 1976 1977 if (DISPLAY_VER(dev_priv) >= 11) 1978 icl_set_pipe_chicken(new_crtc_state); 1979 1980 intel_initial_watermarks(state, crtc); 1981 1982 if (DISPLAY_VER(dev_priv) >= 11) { 1983 const struct intel_dbuf_state *dbuf_state = 1984 intel_atomic_get_new_dbuf_state(state); 1985 1986 icl_pipe_mbus_enable(crtc, dbuf_state->joined_mbus); 1987 } 1988 1989 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 1990 intel_crtc_vblank_on(new_crtc_state); 1991 1992 intel_encoders_enable(state, crtc); 1993 1994 if (psl_clkgate_wa) { 1995 intel_crtc_wait_for_next_vblank(crtc); 1996 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false); 1997 } 1998 1999 /* If we change the relative order between pipe/planes enabling, we need 2000 * to change the workaround. */ 2001 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe; 2002 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { 2003 struct intel_crtc *wa_crtc; 2004 2005 wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe); 2006 2007 intel_crtc_wait_for_next_vblank(wa_crtc); 2008 intel_crtc_wait_for_next_vblank(wa_crtc); 2009 } 2010 } 2011 2012 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state) 2013 { 2014 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 2015 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2016 enum pipe pipe = crtc->pipe; 2017 2018 /* To avoid upsetting the power well on haswell only disable the pfit if 2019 * it's in use. The hw state code will make sure we get this right. */ 2020 if (!old_crtc_state->pch_pfit.enabled) 2021 return; 2022 2023 intel_de_write(dev_priv, PF_CTL(pipe), 0); 2024 intel_de_write(dev_priv, PF_WIN_POS(pipe), 0); 2025 intel_de_write(dev_priv, PF_WIN_SZ(pipe), 0); 2026 } 2027 2028 static void ilk_crtc_disable(struct intel_atomic_state *state, 2029 struct intel_crtc *crtc) 2030 { 2031 const struct intel_crtc_state *old_crtc_state = 2032 intel_atomic_get_old_crtc_state(state, crtc); 2033 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2034 enum pipe pipe = crtc->pipe; 2035 2036 /* 2037 * Sometimes spurious CPU pipe underruns happen when the 2038 * pipe is already disabled, but FDI RX/TX is still enabled. 2039 * Happens at least with VGA+HDMI cloning. Suppress them. 2040 */ 2041 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 2042 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 2043 2044 intel_encoders_disable(state, crtc); 2045 2046 intel_crtc_vblank_off(old_crtc_state); 2047 2048 intel_disable_transcoder(old_crtc_state); 2049 2050 ilk_pfit_disable(old_crtc_state); 2051 2052 if (old_crtc_state->has_pch_encoder) 2053 ilk_pch_disable(state, crtc); 2054 2055 intel_encoders_post_disable(state, crtc); 2056 2057 if (old_crtc_state->has_pch_encoder) 2058 ilk_pch_post_disable(state, crtc); 2059 2060 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2061 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 2062 } 2063 2064 static void hsw_crtc_disable(struct intel_atomic_state *state, 2065 struct intel_crtc *crtc) 2066 { 2067 const struct intel_crtc_state *old_crtc_state = 2068 intel_atomic_get_old_crtc_state(state, crtc); 2069 2070 /* 2071 * FIXME collapse everything to one hook. 2072 * Need care with mst->ddi interactions. 2073 */ 2074 if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) { 2075 intel_encoders_disable(state, crtc); 2076 intel_encoders_post_disable(state, crtc); 2077 } 2078 } 2079 2080 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) 2081 { 2082 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2083 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2084 2085 if (!crtc_state->gmch_pfit.control) 2086 return; 2087 2088 /* 2089 * The panel fitter should only be adjusted whilst the pipe is disabled, 2090 * according to register description and PRM. 2091 */ 2092 drm_WARN_ON(&dev_priv->drm, 2093 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE); 2094 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 2095 2096 intel_de_write(dev_priv, PFIT_PGM_RATIOS, 2097 crtc_state->gmch_pfit.pgm_ratios); 2098 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control); 2099 2100 /* Border color in case we don't scale up to the full screen. Black by 2101 * default, change to something else for debugging. */ 2102 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); 2103 } 2104 2105 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) 2106 { 2107 if (phy == PHY_NONE) 2108 return false; 2109 else if (IS_DG2(dev_priv)) 2110 /* 2111 * DG2 outputs labelled as "combo PHY" in the bspec use 2112 * SNPS PHYs with completely different programming, 2113 * hence we always return false here. 2114 */ 2115 return false; 2116 else if (IS_ALDERLAKE_S(dev_priv)) 2117 return phy <= PHY_E; 2118 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) 2119 return phy <= PHY_D; 2120 else if (IS_JSL_EHL(dev_priv)) 2121 return phy <= PHY_C; 2122 else if (DISPLAY_VER(dev_priv) >= 11) 2123 return phy <= PHY_B; 2124 else 2125 return false; 2126 } 2127 2128 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) 2129 { 2130 if (IS_DG2(dev_priv)) 2131 /* DG2's "TC1" output uses a SNPS PHY */ 2132 return false; 2133 else if (IS_ALDERLAKE_P(dev_priv)) 2134 return phy >= PHY_F && phy <= PHY_I; 2135 else if (IS_TIGERLAKE(dev_priv)) 2136 return phy >= PHY_D && phy <= PHY_I; 2137 else if (IS_ICELAKE(dev_priv)) 2138 return phy >= PHY_C && phy <= PHY_F; 2139 else 2140 return false; 2141 } 2142 2143 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy) 2144 { 2145 if (phy == PHY_NONE) 2146 return false; 2147 else if (IS_DG2(dev_priv)) 2148 /* 2149 * All four "combo" ports and the TC1 port (PHY E) use 2150 * Synopsis PHYs. 2151 */ 2152 return phy <= PHY_E; 2153 2154 return false; 2155 } 2156 2157 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) 2158 { 2159 if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD) 2160 return PHY_D + port - PORT_D_XELPD; 2161 else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1) 2162 return PHY_F + port - PORT_TC1; 2163 else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1) 2164 return PHY_B + port - PORT_TC1; 2165 else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1) 2166 return PHY_C + port - PORT_TC1; 2167 else if (IS_JSL_EHL(i915) && port == PORT_D) 2168 return PHY_A; 2169 2170 return PHY_A + port - PORT_A; 2171 } 2172 2173 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) 2174 { 2175 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port))) 2176 return TC_PORT_NONE; 2177 2178 if (DISPLAY_VER(dev_priv) >= 12) 2179 return TC_PORT_1 + port - PORT_TC1; 2180 else 2181 return TC_PORT_1 + port - PORT_C; 2182 } 2183 2184 enum intel_display_power_domain intel_port_to_power_domain(enum port port) 2185 { 2186 switch (port) { 2187 case PORT_A: 2188 return POWER_DOMAIN_PORT_DDI_A_LANES; 2189 case PORT_B: 2190 return POWER_DOMAIN_PORT_DDI_B_LANES; 2191 case PORT_C: 2192 return POWER_DOMAIN_PORT_DDI_C_LANES; 2193 case PORT_D: 2194 return POWER_DOMAIN_PORT_DDI_D_LANES; 2195 case PORT_E: 2196 return POWER_DOMAIN_PORT_DDI_E_LANES; 2197 case PORT_F: 2198 return POWER_DOMAIN_PORT_DDI_F_LANES; 2199 case PORT_G: 2200 return POWER_DOMAIN_PORT_DDI_G_LANES; 2201 case PORT_H: 2202 return POWER_DOMAIN_PORT_DDI_H_LANES; 2203 case PORT_I: 2204 return POWER_DOMAIN_PORT_DDI_I_LANES; 2205 default: 2206 MISSING_CASE(port); 2207 return POWER_DOMAIN_PORT_OTHER; 2208 } 2209 } 2210 2211 enum intel_display_power_domain 2212 intel_aux_power_domain(struct intel_digital_port *dig_port) 2213 { 2214 if (intel_tc_port_in_tbt_alt_mode(dig_port)) { 2215 switch (dig_port->aux_ch) { 2216 case AUX_CH_C: 2217 return POWER_DOMAIN_AUX_C_TBT; 2218 case AUX_CH_D: 2219 return POWER_DOMAIN_AUX_D_TBT; 2220 case AUX_CH_E: 2221 return POWER_DOMAIN_AUX_E_TBT; 2222 case AUX_CH_F: 2223 return POWER_DOMAIN_AUX_F_TBT; 2224 case AUX_CH_G: 2225 return POWER_DOMAIN_AUX_G_TBT; 2226 case AUX_CH_H: 2227 return POWER_DOMAIN_AUX_H_TBT; 2228 case AUX_CH_I: 2229 return POWER_DOMAIN_AUX_I_TBT; 2230 default: 2231 MISSING_CASE(dig_port->aux_ch); 2232 return POWER_DOMAIN_AUX_C_TBT; 2233 } 2234 } 2235 2236 return intel_legacy_aux_to_power_domain(dig_port->aux_ch); 2237 } 2238 2239 /* 2240 * Converts aux_ch to power_domain without caring about TBT ports for that use 2241 * intel_aux_power_domain() 2242 */ 2243 enum intel_display_power_domain 2244 intel_legacy_aux_to_power_domain(enum aux_ch aux_ch) 2245 { 2246 switch (aux_ch) { 2247 case AUX_CH_A: 2248 return POWER_DOMAIN_AUX_A; 2249 case AUX_CH_B: 2250 return POWER_DOMAIN_AUX_B; 2251 case AUX_CH_C: 2252 return POWER_DOMAIN_AUX_C; 2253 case AUX_CH_D: 2254 return POWER_DOMAIN_AUX_D; 2255 case AUX_CH_E: 2256 return POWER_DOMAIN_AUX_E; 2257 case AUX_CH_F: 2258 return POWER_DOMAIN_AUX_F; 2259 case AUX_CH_G: 2260 return POWER_DOMAIN_AUX_G; 2261 case AUX_CH_H: 2262 return POWER_DOMAIN_AUX_H; 2263 case AUX_CH_I: 2264 return POWER_DOMAIN_AUX_I; 2265 default: 2266 MISSING_CASE(aux_ch); 2267 return POWER_DOMAIN_AUX_A; 2268 } 2269 } 2270 2271 static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state) 2272 { 2273 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2274 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2275 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2276 struct drm_encoder *encoder; 2277 enum pipe pipe = crtc->pipe; 2278 u64 mask; 2279 2280 if (!crtc_state->hw.active) 2281 return 0; 2282 2283 mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe)); 2284 mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 2285 if (crtc_state->pch_pfit.enabled || 2286 crtc_state->pch_pfit.force_thru) 2287 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); 2288 2289 drm_for_each_encoder_mask(encoder, &dev_priv->drm, 2290 crtc_state->uapi.encoder_mask) { 2291 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2292 2293 mask |= BIT_ULL(intel_encoder->power_domain); 2294 } 2295 2296 if (HAS_DDI(dev_priv) && crtc_state->has_audio) 2297 mask |= BIT_ULL(POWER_DOMAIN_AUDIO_MMIO); 2298 2299 if (crtc_state->shared_dpll) 2300 mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE); 2301 2302 if (crtc_state->dsc.compression_enable) 2303 mask |= BIT_ULL(intel_dsc_power_domain(crtc, cpu_transcoder)); 2304 2305 return mask; 2306 } 2307 2308 static u64 2309 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state) 2310 { 2311 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2312 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2313 enum intel_display_power_domain domain; 2314 u64 domains, new_domains, old_domains; 2315 2316 domains = get_crtc_power_domains(crtc_state); 2317 2318 new_domains = domains & ~crtc->enabled_power_domains.mask; 2319 old_domains = crtc->enabled_power_domains.mask & ~domains; 2320 2321 for_each_power_domain(domain, new_domains) 2322 intel_display_power_get_in_set(dev_priv, 2323 &crtc->enabled_power_domains, 2324 domain); 2325 2326 return old_domains; 2327 } 2328 2329 static void modeset_put_crtc_power_domains(struct intel_crtc *crtc, 2330 u64 domains) 2331 { 2332 intel_display_power_put_mask_in_set(to_i915(crtc->base.dev), 2333 &crtc->enabled_power_domains, 2334 domains); 2335 } 2336 2337 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 2338 { 2339 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2340 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2341 2342 if (intel_crtc_has_dp_encoder(crtc_state)) { 2343 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 2344 &crtc_state->dp_m_n); 2345 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 2346 &crtc_state->dp_m2_n2); 2347 } 2348 2349 intel_set_transcoder_timings(crtc_state); 2350 2351 i9xx_set_pipeconf(crtc_state); 2352 } 2353 2354 static void valleyview_crtc_enable(struct intel_atomic_state *state, 2355 struct intel_crtc *crtc) 2356 { 2357 const struct intel_crtc_state *new_crtc_state = 2358 intel_atomic_get_new_crtc_state(state, crtc); 2359 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2360 enum pipe pipe = crtc->pipe; 2361 2362 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 2363 return; 2364 2365 i9xx_configure_cpu_transcoder(new_crtc_state); 2366 2367 intel_set_pipe_src_size(new_crtc_state); 2368 2369 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 2370 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY); 2371 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0); 2372 } 2373 2374 crtc->active = true; 2375 2376 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2377 2378 intel_encoders_pre_pll_enable(state, crtc); 2379 2380 if (IS_CHERRYVIEW(dev_priv)) 2381 chv_enable_pll(new_crtc_state); 2382 else 2383 vlv_enable_pll(new_crtc_state); 2384 2385 intel_encoders_pre_enable(state, crtc); 2386 2387 i9xx_pfit_enable(new_crtc_state); 2388 2389 intel_color_load_luts(new_crtc_state); 2390 intel_color_commit(new_crtc_state); 2391 /* update DSPCNTR to configure gamma for pipe bottom color */ 2392 intel_disable_primary_plane(new_crtc_state); 2393 2394 intel_initial_watermarks(state, crtc); 2395 intel_enable_transcoder(new_crtc_state); 2396 2397 intel_crtc_vblank_on(new_crtc_state); 2398 2399 intel_encoders_enable(state, crtc); 2400 } 2401 2402 static void i9xx_crtc_enable(struct intel_atomic_state *state, 2403 struct intel_crtc *crtc) 2404 { 2405 const struct intel_crtc_state *new_crtc_state = 2406 intel_atomic_get_new_crtc_state(state, crtc); 2407 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2408 enum pipe pipe = crtc->pipe; 2409 2410 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 2411 return; 2412 2413 i9xx_configure_cpu_transcoder(new_crtc_state); 2414 2415 intel_set_pipe_src_size(new_crtc_state); 2416 2417 crtc->active = true; 2418 2419 if (DISPLAY_VER(dev_priv) != 2) 2420 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2421 2422 intel_encoders_pre_enable(state, crtc); 2423 2424 i9xx_enable_pll(new_crtc_state); 2425 2426 i9xx_pfit_enable(new_crtc_state); 2427 2428 intel_color_load_luts(new_crtc_state); 2429 intel_color_commit(new_crtc_state); 2430 /* update DSPCNTR to configure gamma for pipe bottom color */ 2431 intel_disable_primary_plane(new_crtc_state); 2432 2433 if (!intel_initial_watermarks(state, crtc)) 2434 intel_update_watermarks(dev_priv); 2435 intel_enable_transcoder(new_crtc_state); 2436 2437 intel_crtc_vblank_on(new_crtc_state); 2438 2439 intel_encoders_enable(state, crtc); 2440 2441 /* prevents spurious underruns */ 2442 if (DISPLAY_VER(dev_priv) == 2) 2443 intel_crtc_wait_for_next_vblank(crtc); 2444 } 2445 2446 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) 2447 { 2448 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 2449 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2450 2451 if (!old_crtc_state->gmch_pfit.control) 2452 return; 2453 2454 assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder); 2455 2456 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n", 2457 intel_de_read(dev_priv, PFIT_CONTROL)); 2458 intel_de_write(dev_priv, PFIT_CONTROL, 0); 2459 } 2460 2461 static void i9xx_crtc_disable(struct intel_atomic_state *state, 2462 struct intel_crtc *crtc) 2463 { 2464 struct intel_crtc_state *old_crtc_state = 2465 intel_atomic_get_old_crtc_state(state, crtc); 2466 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2467 enum pipe pipe = crtc->pipe; 2468 2469 /* 2470 * On gen2 planes are double buffered but the pipe isn't, so we must 2471 * wait for planes to fully turn off before disabling the pipe. 2472 */ 2473 if (DISPLAY_VER(dev_priv) == 2) 2474 intel_crtc_wait_for_next_vblank(crtc); 2475 2476 intel_encoders_disable(state, crtc); 2477 2478 intel_crtc_vblank_off(old_crtc_state); 2479 2480 intel_disable_transcoder(old_crtc_state); 2481 2482 i9xx_pfit_disable(old_crtc_state); 2483 2484 intel_encoders_post_disable(state, crtc); 2485 2486 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) { 2487 if (IS_CHERRYVIEW(dev_priv)) 2488 chv_disable_pll(dev_priv, pipe); 2489 else if (IS_VALLEYVIEW(dev_priv)) 2490 vlv_disable_pll(dev_priv, pipe); 2491 else 2492 i9xx_disable_pll(old_crtc_state); 2493 } 2494 2495 intel_encoders_post_pll_disable(state, crtc); 2496 2497 if (DISPLAY_VER(dev_priv) != 2) 2498 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 2499 2500 if (!dev_priv->wm_disp->initial_watermarks) 2501 intel_update_watermarks(dev_priv); 2502 2503 /* clock the pipe down to 640x480@60 to potentially save power */ 2504 if (IS_I830(dev_priv)) 2505 i830_enable_pipe(dev_priv, pipe); 2506 } 2507 2508 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, 2509 struct drm_modeset_acquire_ctx *ctx) 2510 { 2511 struct intel_encoder *encoder; 2512 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2513 struct intel_bw_state *bw_state = 2514 to_intel_bw_state(dev_priv->bw_obj.state); 2515 struct intel_cdclk_state *cdclk_state = 2516 to_intel_cdclk_state(dev_priv->cdclk.obj.state); 2517 struct intel_dbuf_state *dbuf_state = 2518 to_intel_dbuf_state(dev_priv->dbuf.obj.state); 2519 struct intel_crtc_state *crtc_state = 2520 to_intel_crtc_state(crtc->base.state); 2521 struct intel_plane *plane; 2522 struct drm_atomic_state *state; 2523 struct intel_crtc_state *temp_crtc_state; 2524 enum pipe pipe = crtc->pipe; 2525 int ret; 2526 2527 if (!crtc_state->hw.active) 2528 return; 2529 2530 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 2531 const struct intel_plane_state *plane_state = 2532 to_intel_plane_state(plane->base.state); 2533 2534 if (plane_state->uapi.visible) 2535 intel_plane_disable_noatomic(crtc, plane); 2536 } 2537 2538 state = drm_atomic_state_alloc(&dev_priv->drm); 2539 if (!state) { 2540 drm_dbg_kms(&dev_priv->drm, 2541 "failed to disable [CRTC:%d:%s], out of memory", 2542 crtc->base.base.id, crtc->base.name); 2543 return; 2544 } 2545 2546 state->acquire_ctx = ctx; 2547 2548 /* Everything's already locked, -EDEADLK can't happen. */ 2549 temp_crtc_state = intel_atomic_get_crtc_state(state, crtc); 2550 ret = drm_atomic_add_affected_connectors(state, &crtc->base); 2551 2552 drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret); 2553 2554 dev_priv->display->crtc_disable(to_intel_atomic_state(state), crtc); 2555 2556 drm_atomic_state_put(state); 2557 2558 drm_dbg_kms(&dev_priv->drm, 2559 "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", 2560 crtc->base.base.id, crtc->base.name); 2561 2562 crtc->active = false; 2563 crtc->base.enabled = false; 2564 2565 drm_WARN_ON(&dev_priv->drm, 2566 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0); 2567 crtc_state->uapi.active = false; 2568 crtc_state->uapi.connector_mask = 0; 2569 crtc_state->uapi.encoder_mask = 0; 2570 intel_crtc_free_hw_state(crtc_state); 2571 memset(&crtc_state->hw, 0, sizeof(crtc_state->hw)); 2572 2573 for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder) 2574 encoder->base.crtc = NULL; 2575 2576 intel_fbc_disable(crtc); 2577 intel_update_watermarks(dev_priv); 2578 intel_disable_shared_dpll(crtc_state); 2579 2580 intel_display_power_put_all_in_set(dev_priv, &crtc->enabled_power_domains); 2581 2582 cdclk_state->min_cdclk[pipe] = 0; 2583 cdclk_state->min_voltage_level[pipe] = 0; 2584 cdclk_state->active_pipes &= ~BIT(pipe); 2585 2586 dbuf_state->active_pipes &= ~BIT(pipe); 2587 2588 bw_state->data_rate[pipe] = 0; 2589 bw_state->num_active_planes[pipe] = 0; 2590 } 2591 2592 /* 2593 * turn all crtc's off, but do not adjust state 2594 * This has to be paired with a call to intel_modeset_setup_hw_state. 2595 */ 2596 int intel_display_suspend(struct drm_device *dev) 2597 { 2598 struct drm_i915_private *dev_priv = to_i915(dev); 2599 struct drm_atomic_state *state; 2600 int ret; 2601 2602 if (!HAS_DISPLAY(dev_priv)) 2603 return 0; 2604 2605 state = drm_atomic_helper_suspend(dev); 2606 ret = PTR_ERR_OR_ZERO(state); 2607 if (ret) 2608 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", 2609 ret); 2610 else 2611 dev_priv->modeset_restore_state = state; 2612 return ret; 2613 } 2614 2615 void intel_encoder_destroy(struct drm_encoder *encoder) 2616 { 2617 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2618 2619 drm_encoder_cleanup(encoder); 2620 kfree(intel_encoder); 2621 } 2622 2623 /* Cross check the actual hw state with our own modeset state tracking (and it's 2624 * internal consistency). */ 2625 static void intel_connector_verify_state(struct intel_crtc_state *crtc_state, 2626 struct drm_connector_state *conn_state) 2627 { 2628 struct intel_connector *connector = to_intel_connector(conn_state->connector); 2629 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2630 2631 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", 2632 connector->base.base.id, connector->base.name); 2633 2634 if (connector->get_hw_state(connector)) { 2635 struct intel_encoder *encoder = intel_attached_encoder(connector); 2636 2637 I915_STATE_WARN(!crtc_state, 2638 "connector enabled without attached crtc\n"); 2639 2640 if (!crtc_state) 2641 return; 2642 2643 I915_STATE_WARN(!crtc_state->hw.active, 2644 "connector is active, but attached crtc isn't\n"); 2645 2646 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) 2647 return; 2648 2649 I915_STATE_WARN(conn_state->best_encoder != &encoder->base, 2650 "atomic encoder doesn't match attached encoder\n"); 2651 2652 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, 2653 "attached encoder crtc differs from connector crtc\n"); 2654 } else { 2655 I915_STATE_WARN(crtc_state && crtc_state->hw.active, 2656 "attached crtc is active, but connector isn't\n"); 2657 I915_STATE_WARN(!crtc_state && conn_state->best_encoder, 2658 "best encoder set without crtc!\n"); 2659 } 2660 } 2661 2662 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) 2663 { 2664 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2665 2666 /* GDG double wide on either pipe, otherwise pipe A only */ 2667 return DISPLAY_VER(dev_priv) < 4 && 2668 (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); 2669 } 2670 2671 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) 2672 { 2673 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock; 2674 struct drm_rect src; 2675 2676 /* 2677 * We only use IF-ID interlacing. If we ever use 2678 * PF-ID we'll need to adjust the pixel_rate here. 2679 */ 2680 2681 if (!crtc_state->pch_pfit.enabled) 2682 return pixel_rate; 2683 2684 drm_rect_init(&src, 0, 0, 2685 drm_rect_width(&crtc_state->pipe_src) << 16, 2686 drm_rect_height(&crtc_state->pipe_src) << 16); 2687 2688 return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst, 2689 pixel_rate); 2690 } 2691 2692 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode, 2693 const struct drm_display_mode *timings) 2694 { 2695 mode->hdisplay = timings->crtc_hdisplay; 2696 mode->htotal = timings->crtc_htotal; 2697 mode->hsync_start = timings->crtc_hsync_start; 2698 mode->hsync_end = timings->crtc_hsync_end; 2699 2700 mode->vdisplay = timings->crtc_vdisplay; 2701 mode->vtotal = timings->crtc_vtotal; 2702 mode->vsync_start = timings->crtc_vsync_start; 2703 mode->vsync_end = timings->crtc_vsync_end; 2704 2705 mode->flags = timings->flags; 2706 mode->type = DRM_MODE_TYPE_DRIVER; 2707 2708 mode->clock = timings->crtc_clock; 2709 2710 drm_mode_set_name(mode); 2711 } 2712 2713 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) 2714 { 2715 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2716 2717 if (HAS_GMCH(dev_priv)) 2718 /* FIXME calculate proper pipe pixel rate for GMCH pfit */ 2719 crtc_state->pixel_rate = 2720 crtc_state->hw.pipe_mode.crtc_clock; 2721 else 2722 crtc_state->pixel_rate = 2723 ilk_pipe_pixel_rate(crtc_state); 2724 } 2725 2726 static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state *crtc_state, 2727 struct drm_display_mode *mode) 2728 { 2729 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2730 2731 if (num_pipes < 2) 2732 return; 2733 2734 mode->crtc_clock /= num_pipes; 2735 mode->crtc_hdisplay /= num_pipes; 2736 mode->crtc_hblank_start /= num_pipes; 2737 mode->crtc_hblank_end /= num_pipes; 2738 mode->crtc_hsync_start /= num_pipes; 2739 mode->crtc_hsync_end /= num_pipes; 2740 mode->crtc_htotal /= num_pipes; 2741 } 2742 2743 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state, 2744 struct drm_display_mode *mode) 2745 { 2746 int overlap = crtc_state->splitter.pixel_overlap; 2747 int n = crtc_state->splitter.link_count; 2748 2749 if (!crtc_state->splitter.enable) 2750 return; 2751 2752 /* 2753 * eDP MSO uses segment timings from EDID for transcoder 2754 * timings, but full mode for everything else. 2755 * 2756 * h_full = (h_segment - pixel_overlap) * link_count 2757 */ 2758 mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n; 2759 mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n; 2760 mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n; 2761 mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n; 2762 mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n; 2763 mode->crtc_htotal = (mode->crtc_htotal - overlap) * n; 2764 mode->crtc_clock *= n; 2765 } 2766 2767 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state) 2768 { 2769 struct drm_display_mode *mode = &crtc_state->hw.mode; 2770 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2771 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2772 2773 /* 2774 * Start with the adjusted_mode crtc timings, which 2775 * have been filled with the transcoder timings. 2776 */ 2777 drm_mode_copy(pipe_mode, adjusted_mode); 2778 2779 /* Expand MSO per-segment transcoder timings to full */ 2780 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2781 2782 /* 2783 * We want the full numbers in adjusted_mode normal timings, 2784 * adjusted_mode crtc timings are left with the raw transcoder 2785 * timings. 2786 */ 2787 intel_mode_from_crtc_timings(adjusted_mode, pipe_mode); 2788 2789 /* Populate the "user" mode with full numbers */ 2790 drm_mode_copy(mode, pipe_mode); 2791 intel_mode_from_crtc_timings(mode, mode); 2792 mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) * 2793 (intel_bigjoiner_num_pipes(crtc_state) ?: 1); 2794 mode->vdisplay = drm_rect_height(&crtc_state->pipe_src); 2795 2796 /* Derive per-pipe timings in case bigjoiner is used */ 2797 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2798 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2799 2800 intel_crtc_compute_pixel_rate(crtc_state); 2801 } 2802 2803 static void intel_encoder_get_config(struct intel_encoder *encoder, 2804 struct intel_crtc_state *crtc_state) 2805 { 2806 encoder->get_config(encoder, crtc_state); 2807 2808 intel_crtc_readout_derived_state(crtc_state); 2809 } 2810 2811 static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state *crtc_state) 2812 { 2813 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2814 int width, height; 2815 2816 if (num_pipes < 2) 2817 return; 2818 2819 width = drm_rect_width(&crtc_state->pipe_src); 2820 height = drm_rect_height(&crtc_state->pipe_src); 2821 2822 drm_rect_init(&crtc_state->pipe_src, 0, 0, 2823 width / num_pipes, height); 2824 } 2825 2826 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state) 2827 { 2828 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2829 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2830 2831 intel_bigjoiner_compute_pipe_src(crtc_state); 2832 2833 /* 2834 * Pipe horizontal size must be even in: 2835 * - DVO ganged mode 2836 * - LVDS dual channel mode 2837 * - Double wide pipe 2838 */ 2839 if (drm_rect_width(&crtc_state->pipe_src) & 1) { 2840 if (crtc_state->double_wide) { 2841 drm_dbg_kms(&i915->drm, 2842 "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n", 2843 crtc->base.base.id, crtc->base.name); 2844 return -EINVAL; 2845 } 2846 2847 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 2848 intel_is_dual_link_lvds(i915)) { 2849 drm_dbg_kms(&i915->drm, 2850 "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n", 2851 crtc->base.base.id, crtc->base.name); 2852 return -EINVAL; 2853 } 2854 } 2855 2856 return 0; 2857 } 2858 2859 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state) 2860 { 2861 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2862 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2863 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2864 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2865 int clock_limit = i915->max_dotclk_freq; 2866 2867 /* 2868 * Start with the adjusted_mode crtc timings, which 2869 * have been filled with the transcoder timings. 2870 */ 2871 drm_mode_copy(pipe_mode, adjusted_mode); 2872 2873 /* Expand MSO per-segment transcoder timings to full */ 2874 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2875 2876 /* Derive per-pipe timings in case bigjoiner is used */ 2877 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2878 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2879 2880 if (DISPLAY_VER(i915) < 4) { 2881 clock_limit = i915->max_cdclk_freq * 9 / 10; 2882 2883 /* 2884 * Enable double wide mode when the dot clock 2885 * is > 90% of the (display) core speed. 2886 */ 2887 if (intel_crtc_supports_double_wide(crtc) && 2888 pipe_mode->crtc_clock > clock_limit) { 2889 clock_limit = i915->max_dotclk_freq; 2890 crtc_state->double_wide = true; 2891 } 2892 } 2893 2894 if (pipe_mode->crtc_clock > clock_limit) { 2895 drm_dbg_kms(&i915->drm, 2896 "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", 2897 crtc->base.base.id, crtc->base.name, 2898 pipe_mode->crtc_clock, clock_limit, 2899 str_yes_no(crtc_state->double_wide)); 2900 return -EINVAL; 2901 } 2902 2903 return 0; 2904 } 2905 2906 static int intel_crtc_compute_config(struct intel_crtc *crtc, 2907 struct intel_crtc_state *crtc_state) 2908 { 2909 int ret; 2910 2911 ret = intel_crtc_compute_pipe_src(crtc_state); 2912 if (ret) 2913 return ret; 2914 2915 ret = intel_crtc_compute_pipe_mode(crtc_state); 2916 if (ret) 2917 return ret; 2918 2919 intel_crtc_compute_pixel_rate(crtc_state); 2920 2921 if (crtc_state->has_pch_encoder) 2922 return ilk_fdi_compute_config(crtc, crtc_state); 2923 2924 return 0; 2925 } 2926 2927 static void 2928 intel_reduce_m_n_ratio(u32 *num, u32 *den) 2929 { 2930 while (*num > DATA_LINK_M_N_MASK || 2931 *den > DATA_LINK_M_N_MASK) { 2932 *num >>= 1; 2933 *den >>= 1; 2934 } 2935 } 2936 2937 static void compute_m_n(unsigned int m, unsigned int n, 2938 u32 *ret_m, u32 *ret_n, 2939 bool constant_n) 2940 { 2941 /* 2942 * Several DP dongles in particular seem to be fussy about 2943 * too large link M/N values. Give N value as 0x8000 that 2944 * should be acceptable by specific devices. 0x8000 is the 2945 * specified fixed N value for asynchronous clock mode, 2946 * which the devices expect also in synchronous clock mode. 2947 */ 2948 if (constant_n) 2949 *ret_n = DP_LINK_CONSTANT_N_VALUE; 2950 else 2951 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); 2952 2953 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n); 2954 intel_reduce_m_n_ratio(ret_m, ret_n); 2955 } 2956 2957 void 2958 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes, 2959 int pixel_clock, int link_clock, 2960 struct intel_link_m_n *m_n, 2961 bool constant_n, bool fec_enable) 2962 { 2963 u32 data_clock = bits_per_pixel * pixel_clock; 2964 2965 if (fec_enable) 2966 data_clock = intel_dp_mode_to_fec_clock(data_clock); 2967 2968 m_n->tu = 64; 2969 compute_m_n(data_clock, 2970 link_clock * nlanes * 8, 2971 &m_n->data_m, &m_n->data_n, 2972 constant_n); 2973 2974 compute_m_n(pixel_clock, link_clock, 2975 &m_n->link_m, &m_n->link_n, 2976 constant_n); 2977 } 2978 2979 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv) 2980 { 2981 /* 2982 * There may be no VBT; and if the BIOS enabled SSC we can 2983 * just keep using it to avoid unnecessary flicker. Whereas if the 2984 * BIOS isn't using it, don't assume it will work even if the VBT 2985 * indicates as much. 2986 */ 2987 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { 2988 bool bios_lvds_use_ssc = intel_de_read(dev_priv, 2989 PCH_DREF_CONTROL) & 2990 DREF_SSC1_ENABLE; 2991 2992 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { 2993 drm_dbg_kms(&dev_priv->drm, 2994 "SSC %s by BIOS, overriding VBT which says %s\n", 2995 str_enabled_disabled(bios_lvds_use_ssc), 2996 str_enabled_disabled(dev_priv->vbt.lvds_use_ssc)); 2997 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; 2998 } 2999 } 3000 } 3001 3002 void intel_zero_m_n(struct intel_link_m_n *m_n) 3003 { 3004 /* corresponds to 0 register value */ 3005 memset(m_n, 0, sizeof(*m_n)); 3006 m_n->tu = 1; 3007 } 3008 3009 void intel_set_m_n(struct drm_i915_private *i915, 3010 const struct intel_link_m_n *m_n, 3011 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 3012 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 3013 { 3014 intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); 3015 intel_de_write(i915, data_n_reg, m_n->data_n); 3016 intel_de_write(i915, link_m_reg, m_n->link_m); 3017 /* 3018 * On BDW+ writing LINK_N arms the double buffered update 3019 * of all the M/N registers, so it must be written last. 3020 */ 3021 intel_de_write(i915, link_n_reg, m_n->link_n); 3022 } 3023 3024 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, 3025 enum transcoder transcoder) 3026 { 3027 if (IS_HASWELL(dev_priv)) 3028 return transcoder == TRANSCODER_EDP; 3029 3030 return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv); 3031 } 3032 3033 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, 3034 enum transcoder transcoder, 3035 const struct intel_link_m_n *m_n) 3036 { 3037 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3038 enum pipe pipe = crtc->pipe; 3039 3040 if (DISPLAY_VER(dev_priv) >= 5) 3041 intel_set_m_n(dev_priv, m_n, 3042 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 3043 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 3044 else 3045 intel_set_m_n(dev_priv, m_n, 3046 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 3047 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 3048 } 3049 3050 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, 3051 enum transcoder transcoder, 3052 const struct intel_link_m_n *m_n) 3053 { 3054 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3055 3056 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 3057 return; 3058 3059 intel_set_m_n(dev_priv, m_n, 3060 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 3061 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 3062 } 3063 3064 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) 3065 { 3066 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3067 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3068 enum pipe pipe = crtc->pipe; 3069 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3070 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 3071 u32 crtc_vtotal, crtc_vblank_end; 3072 int vsyncshift = 0; 3073 3074 /* We need to be careful not to changed the adjusted mode, for otherwise 3075 * the hw state checker will get angry at the mismatch. */ 3076 crtc_vtotal = adjusted_mode->crtc_vtotal; 3077 crtc_vblank_end = adjusted_mode->crtc_vblank_end; 3078 3079 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 3080 /* the chip adds 2 halflines automatically */ 3081 crtc_vtotal -= 1; 3082 crtc_vblank_end -= 1; 3083 3084 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3085 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; 3086 else 3087 vsyncshift = adjusted_mode->crtc_hsync_start - 3088 adjusted_mode->crtc_htotal / 2; 3089 if (vsyncshift < 0) 3090 vsyncshift += adjusted_mode->crtc_htotal; 3091 } 3092 3093 if (DISPLAY_VER(dev_priv) > 3) 3094 intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder), 3095 vsyncshift); 3096 3097 intel_de_write(dev_priv, HTOTAL(cpu_transcoder), 3098 (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16)); 3099 intel_de_write(dev_priv, HBLANK(cpu_transcoder), 3100 (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16)); 3101 intel_de_write(dev_priv, HSYNC(cpu_transcoder), 3102 (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16)); 3103 3104 intel_de_write(dev_priv, VTOTAL(cpu_transcoder), 3105 (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16)); 3106 intel_de_write(dev_priv, VBLANK(cpu_transcoder), 3107 (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16)); 3108 intel_de_write(dev_priv, VSYNC(cpu_transcoder), 3109 (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16)); 3110 3111 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be 3112 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is 3113 * documented on the DDI_FUNC_CTL register description, EDP Input Select 3114 * bits. */ 3115 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && 3116 (pipe == PIPE_B || pipe == PIPE_C)) 3117 intel_de_write(dev_priv, VTOTAL(pipe), 3118 intel_de_read(dev_priv, VTOTAL(cpu_transcoder))); 3119 3120 } 3121 3122 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) 3123 { 3124 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3125 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3126 int width = drm_rect_width(&crtc_state->pipe_src); 3127 int height = drm_rect_height(&crtc_state->pipe_src); 3128 enum pipe pipe = crtc->pipe; 3129 3130 /* pipesrc controls the size that is scaled from, which should 3131 * always be the user's requested size. 3132 */ 3133 intel_de_write(dev_priv, PIPESRC(pipe), 3134 PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1)); 3135 } 3136 3137 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) 3138 { 3139 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3140 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3141 3142 if (DISPLAY_VER(dev_priv) == 2) 3143 return false; 3144 3145 if (DISPLAY_VER(dev_priv) >= 9 || 3146 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 3147 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW; 3148 else 3149 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK; 3150 } 3151 3152 static void intel_get_transcoder_timings(struct intel_crtc *crtc, 3153 struct intel_crtc_state *pipe_config) 3154 { 3155 struct drm_device *dev = crtc->base.dev; 3156 struct drm_i915_private *dev_priv = to_i915(dev); 3157 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3158 u32 tmp; 3159 3160 tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder)); 3161 pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; 3162 pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; 3163 3164 if (!transcoder_is_dsi(cpu_transcoder)) { 3165 tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder)); 3166 pipe_config->hw.adjusted_mode.crtc_hblank_start = 3167 (tmp & 0xffff) + 1; 3168 pipe_config->hw.adjusted_mode.crtc_hblank_end = 3169 ((tmp >> 16) & 0xffff) + 1; 3170 } 3171 tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder)); 3172 pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; 3173 pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; 3174 3175 tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder)); 3176 pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; 3177 pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; 3178 3179 if (!transcoder_is_dsi(cpu_transcoder)) { 3180 tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder)); 3181 pipe_config->hw.adjusted_mode.crtc_vblank_start = 3182 (tmp & 0xffff) + 1; 3183 pipe_config->hw.adjusted_mode.crtc_vblank_end = 3184 ((tmp >> 16) & 0xffff) + 1; 3185 } 3186 tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder)); 3187 pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; 3188 pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; 3189 3190 if (intel_pipe_is_interlaced(pipe_config)) { 3191 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; 3192 pipe_config->hw.adjusted_mode.crtc_vtotal += 1; 3193 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1; 3194 } 3195 } 3196 3197 static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state) 3198 { 3199 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3200 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 3201 enum pipe master_pipe, pipe = crtc->pipe; 3202 int width; 3203 3204 if (num_pipes < 2) 3205 return; 3206 3207 master_pipe = bigjoiner_master_pipe(crtc_state); 3208 width = drm_rect_width(&crtc_state->pipe_src); 3209 3210 drm_rect_translate_to(&crtc_state->pipe_src, 3211 (pipe - master_pipe) * width, 0); 3212 } 3213 3214 static void intel_get_pipe_src_size(struct intel_crtc *crtc, 3215 struct intel_crtc_state *pipe_config) 3216 { 3217 struct drm_device *dev = crtc->base.dev; 3218 struct drm_i915_private *dev_priv = to_i915(dev); 3219 u32 tmp; 3220 3221 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe)); 3222 3223 drm_rect_init(&pipe_config->pipe_src, 0, 0, 3224 REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1, 3225 REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1); 3226 3227 intel_bigjoiner_adjust_pipe_src(pipe_config); 3228 } 3229 3230 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) 3231 { 3232 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3233 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3234 u32 pipeconf = 0; 3235 3236 /* we keep both pipes enabled on 830 */ 3237 if (IS_I830(dev_priv)) 3238 pipeconf |= PIPECONF_ENABLE; 3239 3240 if (crtc_state->double_wide) 3241 pipeconf |= PIPECONF_DOUBLE_WIDE; 3242 3243 /* only g4x and later have fancy bpc/dither controls */ 3244 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 3245 IS_CHERRYVIEW(dev_priv)) { 3246 /* Bspec claims that we can't use dithering for 30bpp pipes. */ 3247 if (crtc_state->dither && crtc_state->pipe_bpp != 30) 3248 pipeconf |= PIPECONF_DITHER_EN | 3249 PIPECONF_DITHER_TYPE_SP; 3250 3251 switch (crtc_state->pipe_bpp) { 3252 case 18: 3253 pipeconf |= PIPECONF_BPC_6; 3254 break; 3255 case 24: 3256 pipeconf |= PIPECONF_BPC_8; 3257 break; 3258 case 30: 3259 pipeconf |= PIPECONF_BPC_10; 3260 break; 3261 default: 3262 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3263 BUG(); 3264 } 3265 } 3266 3267 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 3268 if (DISPLAY_VER(dev_priv) < 4 || 3269 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3270 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; 3271 else 3272 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; 3273 } else { 3274 pipeconf |= PIPECONF_INTERLACE_PROGRESSIVE; 3275 } 3276 3277 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 3278 crtc_state->limited_color_range) 3279 pipeconf |= PIPECONF_COLOR_RANGE_SELECT; 3280 3281 pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); 3282 3283 pipeconf |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3284 3285 intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf); 3286 intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe)); 3287 } 3288 3289 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv) 3290 { 3291 if (IS_I830(dev_priv)) 3292 return false; 3293 3294 return DISPLAY_VER(dev_priv) >= 4 || 3295 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); 3296 } 3297 3298 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state) 3299 { 3300 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3301 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3302 u32 tmp; 3303 3304 if (!i9xx_has_pfit(dev_priv)) 3305 return; 3306 3307 tmp = intel_de_read(dev_priv, PFIT_CONTROL); 3308 if (!(tmp & PFIT_ENABLE)) 3309 return; 3310 3311 /* Check whether the pfit is attached to our pipe. */ 3312 if (DISPLAY_VER(dev_priv) < 4) { 3313 if (crtc->pipe != PIPE_B) 3314 return; 3315 } else { 3316 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) 3317 return; 3318 } 3319 3320 crtc_state->gmch_pfit.control = tmp; 3321 crtc_state->gmch_pfit.pgm_ratios = 3322 intel_de_read(dev_priv, PFIT_PGM_RATIOS); 3323 } 3324 3325 static void vlv_crtc_clock_get(struct intel_crtc *crtc, 3326 struct intel_crtc_state *pipe_config) 3327 { 3328 struct drm_device *dev = crtc->base.dev; 3329 struct drm_i915_private *dev_priv = to_i915(dev); 3330 enum pipe pipe = crtc->pipe; 3331 struct dpll clock; 3332 u32 mdiv; 3333 int refclk = 100000; 3334 3335 /* In case of DSI, DPLL will not be used */ 3336 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 3337 return; 3338 3339 vlv_dpio_get(dev_priv); 3340 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); 3341 vlv_dpio_put(dev_priv); 3342 3343 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; 3344 clock.m2 = mdiv & DPIO_M2DIV_MASK; 3345 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; 3346 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; 3347 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; 3348 3349 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); 3350 } 3351 3352 static void chv_crtc_clock_get(struct intel_crtc *crtc, 3353 struct intel_crtc_state *pipe_config) 3354 { 3355 struct drm_device *dev = crtc->base.dev; 3356 struct drm_i915_private *dev_priv = to_i915(dev); 3357 enum pipe pipe = crtc->pipe; 3358 enum dpio_channel port = vlv_pipe_to_channel(pipe); 3359 struct dpll clock; 3360 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; 3361 int refclk = 100000; 3362 3363 /* In case of DSI, DPLL will not be used */ 3364 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 3365 return; 3366 3367 vlv_dpio_get(dev_priv); 3368 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); 3369 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); 3370 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); 3371 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); 3372 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); 3373 vlv_dpio_put(dev_priv); 3374 3375 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; 3376 clock.m2 = (pll_dw0 & 0xff) << 22; 3377 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) 3378 clock.m2 |= pll_dw2 & 0x3fffff; 3379 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; 3380 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; 3381 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; 3382 3383 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); 3384 } 3385 3386 static enum intel_output_format 3387 bdw_get_pipemisc_output_format(struct intel_crtc *crtc) 3388 { 3389 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3390 u32 tmp; 3391 3392 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); 3393 3394 if (tmp & PIPEMISC_YUV420_ENABLE) { 3395 /* We support 4:2:0 in full blend mode only */ 3396 drm_WARN_ON(&dev_priv->drm, 3397 (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0); 3398 3399 return INTEL_OUTPUT_FORMAT_YCBCR420; 3400 } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) { 3401 return INTEL_OUTPUT_FORMAT_YCBCR444; 3402 } else { 3403 return INTEL_OUTPUT_FORMAT_RGB; 3404 } 3405 } 3406 3407 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state) 3408 { 3409 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3410 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 3411 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3412 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 3413 u32 tmp; 3414 3415 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); 3416 3417 if (tmp & DISP_PIPE_GAMMA_ENABLE) 3418 crtc_state->gamma_enable = true; 3419 3420 if (!HAS_GMCH(dev_priv) && 3421 tmp & DISP_PIPE_CSC_ENABLE) 3422 crtc_state->csc_enable = true; 3423 } 3424 3425 static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 3426 struct intel_crtc_state *pipe_config) 3427 { 3428 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3429 enum intel_display_power_domain power_domain; 3430 intel_wakeref_t wakeref; 3431 u32 tmp; 3432 bool ret; 3433 3434 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3435 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3436 if (!wakeref) 3437 return false; 3438 3439 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3440 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3441 pipe_config->shared_dpll = NULL; 3442 3443 ret = false; 3444 3445 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); 3446 if (!(tmp & PIPECONF_ENABLE)) 3447 goto out; 3448 3449 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 3450 IS_CHERRYVIEW(dev_priv)) { 3451 switch (tmp & PIPECONF_BPC_MASK) { 3452 case PIPECONF_BPC_6: 3453 pipe_config->pipe_bpp = 18; 3454 break; 3455 case PIPECONF_BPC_8: 3456 pipe_config->pipe_bpp = 24; 3457 break; 3458 case PIPECONF_BPC_10: 3459 pipe_config->pipe_bpp = 30; 3460 break; 3461 default: 3462 MISSING_CASE(tmp); 3463 break; 3464 } 3465 } 3466 3467 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 3468 (tmp & PIPECONF_COLOR_RANGE_SELECT)) 3469 pipe_config->limited_color_range = true; 3470 3471 pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_I9XX, tmp); 3472 3473 pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1; 3474 3475 if (IS_CHERRYVIEW(dev_priv)) 3476 pipe_config->cgm_mode = intel_de_read(dev_priv, 3477 CGM_PIPE_MODE(crtc->pipe)); 3478 3479 i9xx_get_pipe_color_config(pipe_config); 3480 intel_color_get_config(pipe_config); 3481 3482 if (DISPLAY_VER(dev_priv) < 4) 3483 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; 3484 3485 intel_get_transcoder_timings(crtc, pipe_config); 3486 intel_get_pipe_src_size(crtc, pipe_config); 3487 3488 i9xx_get_pfit_config(pipe_config); 3489 3490 if (DISPLAY_VER(dev_priv) >= 4) { 3491 /* No way to read it out on pipes B and C */ 3492 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) 3493 tmp = dev_priv->chv_dpll_md[crtc->pipe]; 3494 else 3495 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe)); 3496 pipe_config->pixel_multiplier = 3497 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) 3498 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; 3499 pipe_config->dpll_hw_state.dpll_md = tmp; 3500 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 3501 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 3502 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe)); 3503 pipe_config->pixel_multiplier = 3504 ((tmp & SDVO_MULTIPLIER_MASK) 3505 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; 3506 } else { 3507 /* Note that on i915G/GM the pixel multiplier is in the sdvo 3508 * port and will be fixed up in the encoder->get_config 3509 * function. */ 3510 pipe_config->pixel_multiplier = 1; 3511 } 3512 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv, 3513 DPLL(crtc->pipe)); 3514 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 3515 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv, 3516 FP0(crtc->pipe)); 3517 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv, 3518 FP1(crtc->pipe)); 3519 } else { 3520 /* Mask out read-only status bits. */ 3521 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | 3522 DPLL_PORTC_READY_MASK | 3523 DPLL_PORTB_READY_MASK); 3524 } 3525 3526 if (IS_CHERRYVIEW(dev_priv)) 3527 chv_crtc_clock_get(crtc, pipe_config); 3528 else if (IS_VALLEYVIEW(dev_priv)) 3529 vlv_crtc_clock_get(crtc, pipe_config); 3530 else 3531 i9xx_crtc_clock_get(crtc, pipe_config); 3532 3533 /* 3534 * Normally the dotclock is filled in by the encoder .get_config() 3535 * but in case the pipe is enabled w/o any ports we need a sane 3536 * default. 3537 */ 3538 pipe_config->hw.adjusted_mode.crtc_clock = 3539 pipe_config->port_clock / pipe_config->pixel_multiplier; 3540 3541 ret = true; 3542 3543 out: 3544 intel_display_power_put(dev_priv, power_domain, wakeref); 3545 3546 return ret; 3547 } 3548 3549 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) 3550 { 3551 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3552 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3553 enum pipe pipe = crtc->pipe; 3554 u32 val; 3555 3556 val = 0; 3557 3558 switch (crtc_state->pipe_bpp) { 3559 case 18: 3560 val |= PIPECONF_BPC_6; 3561 break; 3562 case 24: 3563 val |= PIPECONF_BPC_8; 3564 break; 3565 case 30: 3566 val |= PIPECONF_BPC_10; 3567 break; 3568 case 36: 3569 val |= PIPECONF_BPC_12; 3570 break; 3571 default: 3572 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3573 BUG(); 3574 } 3575 3576 if (crtc_state->dither) 3577 val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP; 3578 3579 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3580 val |= PIPECONF_INTERLACE_IF_ID_ILK; 3581 else 3582 val |= PIPECONF_INTERLACE_PF_PD_ILK; 3583 3584 /* 3585 * This would end up with an odd purple hue over 3586 * the entire display. Make sure we don't do it. 3587 */ 3588 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 3589 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 3590 3591 if (crtc_state->limited_color_range && 3592 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3593 val |= PIPECONF_COLOR_RANGE_SELECT; 3594 3595 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3596 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709; 3597 3598 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); 3599 3600 val |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3601 val |= PIPECONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay); 3602 3603 intel_de_write(dev_priv, PIPECONF(pipe), val); 3604 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 3605 } 3606 3607 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) 3608 { 3609 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3610 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3611 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3612 u32 val = 0; 3613 3614 if (IS_HASWELL(dev_priv) && crtc_state->dither) 3615 val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP; 3616 3617 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3618 val |= PIPECONF_INTERLACE_IF_ID_ILK; 3619 else 3620 val |= PIPECONF_INTERLACE_PF_PD_ILK; 3621 3622 if (IS_HASWELL(dev_priv) && 3623 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3624 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW; 3625 3626 intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val); 3627 intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder)); 3628 } 3629 3630 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) 3631 { 3632 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3633 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3634 u32 val = 0; 3635 3636 switch (crtc_state->pipe_bpp) { 3637 case 18: 3638 val |= PIPEMISC_BPC_6; 3639 break; 3640 case 24: 3641 val |= PIPEMISC_BPC_8; 3642 break; 3643 case 30: 3644 val |= PIPEMISC_BPC_10; 3645 break; 3646 case 36: 3647 /* Port output 12BPC defined for ADLP+ */ 3648 if (DISPLAY_VER(dev_priv) > 12) 3649 val |= PIPEMISC_BPC_12_ADLP; 3650 break; 3651 default: 3652 MISSING_CASE(crtc_state->pipe_bpp); 3653 break; 3654 } 3655 3656 if (crtc_state->dither) 3657 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; 3658 3659 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 3660 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 3661 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV; 3662 3663 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 3664 val |= PIPEMISC_YUV420_ENABLE | 3665 PIPEMISC_YUV420_MODE_FULL_BLEND; 3666 3667 if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state)) 3668 val |= PIPEMISC_HDR_MODE_PRECISION; 3669 3670 if (DISPLAY_VER(dev_priv) >= 12) 3671 val |= PIPEMISC_PIXEL_ROUNDING_TRUNC; 3672 3673 intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val); 3674 } 3675 3676 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) 3677 { 3678 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3679 u32 tmp; 3680 3681 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); 3682 3683 switch (tmp & PIPEMISC_BPC_MASK) { 3684 case PIPEMISC_BPC_6: 3685 return 18; 3686 case PIPEMISC_BPC_8: 3687 return 24; 3688 case PIPEMISC_BPC_10: 3689 return 30; 3690 /* 3691 * PORT OUTPUT 12 BPC defined for ADLP+. 3692 * 3693 * TODO: 3694 * For previous platforms with DSI interface, bits 5:7 3695 * are used for storing pipe_bpp irrespective of dithering. 3696 * Since the value of 12 BPC is not defined for these bits 3697 * on older platforms, need to find a workaround for 12 BPC 3698 * MIPI DSI HW readout. 3699 */ 3700 case PIPEMISC_BPC_12_ADLP: 3701 if (DISPLAY_VER(dev_priv) > 12) 3702 return 36; 3703 fallthrough; 3704 default: 3705 MISSING_CASE(tmp); 3706 return 0; 3707 } 3708 } 3709 3710 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) 3711 { 3712 /* 3713 * Account for spread spectrum to avoid 3714 * oversubscribing the link. Max center spread 3715 * is 2.5%; use 5% for safety's sake. 3716 */ 3717 u32 bps = target_clock * bpp * 21 / 20; 3718 return DIV_ROUND_UP(bps, link_bw * 8); 3719 } 3720 3721 void intel_get_m_n(struct drm_i915_private *i915, 3722 struct intel_link_m_n *m_n, 3723 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 3724 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 3725 { 3726 m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK; 3727 m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK; 3728 m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK; 3729 m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK; 3730 m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1; 3731 } 3732 3733 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, 3734 enum transcoder transcoder, 3735 struct intel_link_m_n *m_n) 3736 { 3737 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3738 enum pipe pipe = crtc->pipe; 3739 3740 if (DISPLAY_VER(dev_priv) >= 5) 3741 intel_get_m_n(dev_priv, m_n, 3742 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 3743 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 3744 else 3745 intel_get_m_n(dev_priv, m_n, 3746 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 3747 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 3748 } 3749 3750 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, 3751 enum transcoder transcoder, 3752 struct intel_link_m_n *m_n) 3753 { 3754 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3755 3756 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 3757 return; 3758 3759 intel_get_m_n(dev_priv, m_n, 3760 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 3761 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 3762 } 3763 3764 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state, 3765 u32 pos, u32 size) 3766 { 3767 drm_rect_init(&crtc_state->pch_pfit.dst, 3768 pos >> 16, pos & 0xffff, 3769 size >> 16, size & 0xffff); 3770 } 3771 3772 static void skl_get_pfit_config(struct intel_crtc_state *crtc_state) 3773 { 3774 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3775 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3776 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; 3777 int id = -1; 3778 int i; 3779 3780 /* find scaler attached to this pipe */ 3781 for (i = 0; i < crtc->num_scalers; i++) { 3782 u32 ctl, pos, size; 3783 3784 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i)); 3785 if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN) 3786 continue; 3787 3788 id = i; 3789 crtc_state->pch_pfit.enabled = true; 3790 3791 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i)); 3792 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i)); 3793 3794 ilk_get_pfit_pos_size(crtc_state, pos, size); 3795 3796 scaler_state->scalers[i].in_use = true; 3797 break; 3798 } 3799 3800 scaler_state->scaler_id = id; 3801 if (id >= 0) 3802 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); 3803 else 3804 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); 3805 } 3806 3807 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state) 3808 { 3809 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3810 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3811 u32 ctl, pos, size; 3812 3813 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe)); 3814 if ((ctl & PF_ENABLE) == 0) 3815 return; 3816 3817 crtc_state->pch_pfit.enabled = true; 3818 3819 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe)); 3820 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe)); 3821 3822 ilk_get_pfit_pos_size(crtc_state, pos, size); 3823 3824 /* 3825 * We currently do not free assignements of panel fitters on 3826 * ivb/hsw (since we don't use the higher upscaling modes which 3827 * differentiates them) so just WARN about this case for now. 3828 */ 3829 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 7 && 3830 (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe)); 3831 } 3832 3833 static bool ilk_get_pipe_config(struct intel_crtc *crtc, 3834 struct intel_crtc_state *pipe_config) 3835 { 3836 struct drm_device *dev = crtc->base.dev; 3837 struct drm_i915_private *dev_priv = to_i915(dev); 3838 enum intel_display_power_domain power_domain; 3839 intel_wakeref_t wakeref; 3840 u32 tmp; 3841 bool ret; 3842 3843 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3844 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3845 if (!wakeref) 3846 return false; 3847 3848 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3849 pipe_config->shared_dpll = NULL; 3850 3851 ret = false; 3852 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); 3853 if (!(tmp & PIPECONF_ENABLE)) 3854 goto out; 3855 3856 switch (tmp & PIPECONF_BPC_MASK) { 3857 case PIPECONF_BPC_6: 3858 pipe_config->pipe_bpp = 18; 3859 break; 3860 case PIPECONF_BPC_8: 3861 pipe_config->pipe_bpp = 24; 3862 break; 3863 case PIPECONF_BPC_10: 3864 pipe_config->pipe_bpp = 30; 3865 break; 3866 case PIPECONF_BPC_12: 3867 pipe_config->pipe_bpp = 36; 3868 break; 3869 default: 3870 break; 3871 } 3872 3873 if (tmp & PIPECONF_COLOR_RANGE_SELECT) 3874 pipe_config->limited_color_range = true; 3875 3876 switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) { 3877 case PIPECONF_OUTPUT_COLORSPACE_YUV601: 3878 case PIPECONF_OUTPUT_COLORSPACE_YUV709: 3879 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3880 break; 3881 default: 3882 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3883 break; 3884 } 3885 3886 pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_ILK, tmp); 3887 3888 pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1; 3889 3890 pipe_config->msa_timing_delay = REG_FIELD_GET(PIPECONF_MSA_TIMING_DELAY_MASK, tmp); 3891 3892 pipe_config->csc_mode = intel_de_read(dev_priv, 3893 PIPE_CSC_MODE(crtc->pipe)); 3894 3895 i9xx_get_pipe_color_config(pipe_config); 3896 intel_color_get_config(pipe_config); 3897 3898 pipe_config->pixel_multiplier = 1; 3899 3900 ilk_pch_get_config(pipe_config); 3901 3902 intel_get_transcoder_timings(crtc, pipe_config); 3903 intel_get_pipe_src_size(crtc, pipe_config); 3904 3905 ilk_get_pfit_config(pipe_config); 3906 3907 ret = true; 3908 3909 out: 3910 intel_display_power_put(dev_priv, power_domain, wakeref); 3911 3912 return ret; 3913 } 3914 3915 static u8 bigjoiner_pipes(struct drm_i915_private *i915) 3916 { 3917 if (DISPLAY_VER(i915) >= 12) 3918 return BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D); 3919 else if (DISPLAY_VER(i915) >= 11) 3920 return BIT(PIPE_B) | BIT(PIPE_C); 3921 else 3922 return 0; 3923 } 3924 3925 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv, 3926 enum transcoder cpu_transcoder) 3927 { 3928 enum intel_display_power_domain power_domain; 3929 intel_wakeref_t wakeref; 3930 u32 tmp = 0; 3931 3932 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3933 3934 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3935 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3936 3937 return tmp & TRANS_DDI_FUNC_ENABLE; 3938 } 3939 3940 static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv, 3941 u8 *master_pipes, u8 *slave_pipes) 3942 { 3943 struct intel_crtc *crtc; 3944 3945 *master_pipes = 0; 3946 *slave_pipes = 0; 3947 3948 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, 3949 bigjoiner_pipes(dev_priv)) { 3950 enum intel_display_power_domain power_domain; 3951 enum pipe pipe = crtc->pipe; 3952 intel_wakeref_t wakeref; 3953 3954 power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe); 3955 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3956 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3957 3958 if (!(tmp & BIG_JOINER_ENABLE)) 3959 continue; 3960 3961 if (tmp & MASTER_BIG_JOINER_ENABLE) 3962 *master_pipes |= BIT(pipe); 3963 else 3964 *slave_pipes |= BIT(pipe); 3965 } 3966 3967 if (DISPLAY_VER(dev_priv) < 13) 3968 continue; 3969 3970 power_domain = POWER_DOMAIN_PIPE(pipe); 3971 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3972 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3973 3974 if (tmp & UNCOMPRESSED_JOINER_MASTER) 3975 *master_pipes |= BIT(pipe); 3976 if (tmp & UNCOMPRESSED_JOINER_SLAVE) 3977 *slave_pipes |= BIT(pipe); 3978 } 3979 } 3980 3981 /* Bigjoiner pipes should always be consecutive master and slave */ 3982 drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1, 3983 "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n", 3984 *master_pipes, *slave_pipes); 3985 } 3986 3987 static enum pipe get_bigjoiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3988 { 3989 if ((slave_pipes & BIT(pipe)) == 0) 3990 return pipe; 3991 3992 /* ignore everything above our pipe */ 3993 master_pipes &= ~GENMASK(7, pipe); 3994 3995 /* highest remaining bit should be our master pipe */ 3996 return fls(master_pipes) - 1; 3997 } 3998 3999 static u8 get_bigjoiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 4000 { 4001 enum pipe master_pipe, next_master_pipe; 4002 4003 master_pipe = get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes); 4004 4005 if ((master_pipes & BIT(master_pipe)) == 0) 4006 return 0; 4007 4008 /* ignore our master pipe and everything below it */ 4009 master_pipes &= ~GENMASK(master_pipe, 0); 4010 /* make sure a high bit is set for the ffs() */ 4011 master_pipes |= BIT(7); 4012 /* lowest remaining bit should be the next master pipe */ 4013 next_master_pipe = ffs(master_pipes) - 1; 4014 4015 return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe); 4016 } 4017 4018 static u8 hsw_panel_transcoders(struct drm_i915_private *i915) 4019 { 4020 u8 panel_transcoder_mask = BIT(TRANSCODER_EDP); 4021 4022 if (DISPLAY_VER(i915) >= 11) 4023 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); 4024 4025 return panel_transcoder_mask; 4026 } 4027 4028 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) 4029 { 4030 struct drm_device *dev = crtc->base.dev; 4031 struct drm_i915_private *dev_priv = to_i915(dev); 4032 u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv); 4033 enum transcoder cpu_transcoder; 4034 u8 master_pipes, slave_pipes; 4035 u8 enabled_transcoders = 0; 4036 4037 /* 4038 * XXX: Do intel_display_power_get_if_enabled before reading this (for 4039 * consistency and less surprising code; it's in always on power). 4040 */ 4041 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, 4042 panel_transcoder_mask) { 4043 enum intel_display_power_domain power_domain; 4044 intel_wakeref_t wakeref; 4045 enum pipe trans_pipe; 4046 u32 tmp = 0; 4047 4048 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 4049 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 4050 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 4051 4052 if (!(tmp & TRANS_DDI_FUNC_ENABLE)) 4053 continue; 4054 4055 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 4056 default: 4057 drm_WARN(dev, 1, 4058 "unknown pipe linked to transcoder %s\n", 4059 transcoder_name(cpu_transcoder)); 4060 fallthrough; 4061 case TRANS_DDI_EDP_INPUT_A_ONOFF: 4062 case TRANS_DDI_EDP_INPUT_A_ON: 4063 trans_pipe = PIPE_A; 4064 break; 4065 case TRANS_DDI_EDP_INPUT_B_ONOFF: 4066 trans_pipe = PIPE_B; 4067 break; 4068 case TRANS_DDI_EDP_INPUT_C_ONOFF: 4069 trans_pipe = PIPE_C; 4070 break; 4071 case TRANS_DDI_EDP_INPUT_D_ONOFF: 4072 trans_pipe = PIPE_D; 4073 break; 4074 } 4075 4076 if (trans_pipe == crtc->pipe) 4077 enabled_transcoders |= BIT(cpu_transcoder); 4078 } 4079 4080 /* single pipe or bigjoiner master */ 4081 cpu_transcoder = (enum transcoder) crtc->pipe; 4082 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 4083 enabled_transcoders |= BIT(cpu_transcoder); 4084 4085 /* bigjoiner slave -> consider the master pipe's transcoder as well */ 4086 enabled_bigjoiner_pipes(dev_priv, &master_pipes, &slave_pipes); 4087 if (slave_pipes & BIT(crtc->pipe)) { 4088 cpu_transcoder = (enum transcoder) 4089 get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes); 4090 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 4091 enabled_transcoders |= BIT(cpu_transcoder); 4092 } 4093 4094 return enabled_transcoders; 4095 } 4096 4097 static bool has_edp_transcoders(u8 enabled_transcoders) 4098 { 4099 return enabled_transcoders & BIT(TRANSCODER_EDP); 4100 } 4101 4102 static bool has_dsi_transcoders(u8 enabled_transcoders) 4103 { 4104 return enabled_transcoders & (BIT(TRANSCODER_DSI_0) | 4105 BIT(TRANSCODER_DSI_1)); 4106 } 4107 4108 static bool has_pipe_transcoders(u8 enabled_transcoders) 4109 { 4110 return enabled_transcoders & ~(BIT(TRANSCODER_EDP) | 4111 BIT(TRANSCODER_DSI_0) | 4112 BIT(TRANSCODER_DSI_1)); 4113 } 4114 4115 static void assert_enabled_transcoders(struct drm_i915_private *i915, 4116 u8 enabled_transcoders) 4117 { 4118 /* Only one type of transcoder please */ 4119 drm_WARN_ON(&i915->drm, 4120 has_edp_transcoders(enabled_transcoders) + 4121 has_dsi_transcoders(enabled_transcoders) + 4122 has_pipe_transcoders(enabled_transcoders) > 1); 4123 4124 /* Only DSI transcoders can be ganged */ 4125 drm_WARN_ON(&i915->drm, 4126 !has_dsi_transcoders(enabled_transcoders) && 4127 !is_power_of_2(enabled_transcoders)); 4128 } 4129 4130 static bool hsw_get_transcoder_state(struct intel_crtc *crtc, 4131 struct intel_crtc_state *pipe_config, 4132 struct intel_display_power_domain_set *power_domain_set) 4133 { 4134 struct drm_device *dev = crtc->base.dev; 4135 struct drm_i915_private *dev_priv = to_i915(dev); 4136 unsigned long enabled_transcoders; 4137 u32 tmp; 4138 4139 enabled_transcoders = hsw_enabled_transcoders(crtc); 4140 if (!enabled_transcoders) 4141 return false; 4142 4143 assert_enabled_transcoders(dev_priv, enabled_transcoders); 4144 4145 /* 4146 * With the exception of DSI we should only ever have 4147 * a single enabled transcoder. With DSI let's just 4148 * pick the first one. 4149 */ 4150 pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1; 4151 4152 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 4153 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) 4154 return false; 4155 4156 if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) { 4157 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); 4158 4159 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF) 4160 pipe_config->pch_pfit.force_thru = true; 4161 } 4162 4163 tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder)); 4164 4165 return tmp & PIPECONF_ENABLE; 4166 } 4167 4168 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, 4169 struct intel_crtc_state *pipe_config, 4170 struct intel_display_power_domain_set *power_domain_set) 4171 { 4172 struct drm_device *dev = crtc->base.dev; 4173 struct drm_i915_private *dev_priv = to_i915(dev); 4174 enum transcoder cpu_transcoder; 4175 enum port port; 4176 u32 tmp; 4177 4178 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { 4179 if (port == PORT_A) 4180 cpu_transcoder = TRANSCODER_DSI_A; 4181 else 4182 cpu_transcoder = TRANSCODER_DSI_C; 4183 4184 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 4185 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) 4186 continue; 4187 4188 /* 4189 * The PLL needs to be enabled with a valid divider 4190 * configuration, otherwise accessing DSI registers will hang 4191 * the machine. See BSpec North Display Engine 4192 * registers/MIPI[BXT]. We can break out here early, since we 4193 * need the same DSI PLL to be enabled for both DSI ports. 4194 */ 4195 if (!bxt_dsi_pll_is_enabled(dev_priv)) 4196 break; 4197 4198 /* XXX: this works for video mode only */ 4199 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); 4200 if (!(tmp & DPI_ENABLE)) 4201 continue; 4202 4203 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 4204 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) 4205 continue; 4206 4207 pipe_config->cpu_transcoder = cpu_transcoder; 4208 break; 4209 } 4210 4211 return transcoder_is_dsi(pipe_config->cpu_transcoder); 4212 } 4213 4214 static void intel_bigjoiner_get_config(struct intel_crtc_state *crtc_state) 4215 { 4216 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4217 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4218 u8 master_pipes, slave_pipes; 4219 enum pipe pipe = crtc->pipe; 4220 4221 enabled_bigjoiner_pipes(i915, &master_pipes, &slave_pipes); 4222 4223 if (((master_pipes | slave_pipes) & BIT(pipe)) == 0) 4224 return; 4225 4226 crtc_state->bigjoiner_pipes = 4227 BIT(get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes)) | 4228 get_bigjoiner_slave_pipes(pipe, master_pipes, slave_pipes); 4229 } 4230 4231 static bool hsw_get_pipe_config(struct intel_crtc *crtc, 4232 struct intel_crtc_state *pipe_config) 4233 { 4234 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4235 struct intel_display_power_domain_set power_domain_set = { }; 4236 bool active; 4237 u32 tmp; 4238 4239 if (!intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set, 4240 POWER_DOMAIN_PIPE(crtc->pipe))) 4241 return false; 4242 4243 pipe_config->shared_dpll = NULL; 4244 4245 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_set); 4246 4247 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 4248 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_set)) { 4249 drm_WARN_ON(&dev_priv->drm, active); 4250 active = true; 4251 } 4252 4253 if (!active) 4254 goto out; 4255 4256 intel_dsc_get_config(pipe_config); 4257 intel_bigjoiner_get_config(pipe_config); 4258 4259 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || 4260 DISPLAY_VER(dev_priv) >= 11) 4261 intel_get_transcoder_timings(crtc, pipe_config); 4262 4263 if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder)) 4264 intel_vrr_get_config(crtc, pipe_config); 4265 4266 intel_get_pipe_src_size(crtc, pipe_config); 4267 4268 if (IS_HASWELL(dev_priv)) { 4269 u32 tmp = intel_de_read(dev_priv, 4270 PIPECONF(pipe_config->cpu_transcoder)); 4271 4272 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW) 4273 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 4274 else 4275 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 4276 } else { 4277 pipe_config->output_format = 4278 bdw_get_pipemisc_output_format(crtc); 4279 } 4280 4281 pipe_config->gamma_mode = intel_de_read(dev_priv, 4282 GAMMA_MODE(crtc->pipe)); 4283 4284 pipe_config->csc_mode = intel_de_read(dev_priv, 4285 PIPE_CSC_MODE(crtc->pipe)); 4286 4287 if (DISPLAY_VER(dev_priv) >= 9) { 4288 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe)); 4289 4290 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE) 4291 pipe_config->gamma_enable = true; 4292 4293 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE) 4294 pipe_config->csc_enable = true; 4295 } else { 4296 i9xx_get_pipe_color_config(pipe_config); 4297 } 4298 4299 intel_color_get_config(pipe_config); 4300 4301 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe)); 4302 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); 4303 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 4304 pipe_config->ips_linetime = 4305 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); 4306 4307 if (intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set, 4308 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) { 4309 if (DISPLAY_VER(dev_priv) >= 9) 4310 skl_get_pfit_config(pipe_config); 4311 else 4312 ilk_get_pfit_config(pipe_config); 4313 } 4314 4315 hsw_ips_get_config(pipe_config); 4316 4317 if (pipe_config->cpu_transcoder != TRANSCODER_EDP && 4318 !transcoder_is_dsi(pipe_config->cpu_transcoder)) { 4319 pipe_config->pixel_multiplier = 4320 intel_de_read(dev_priv, 4321 PIPE_MULT(pipe_config->cpu_transcoder)) + 1; 4322 } else { 4323 pipe_config->pixel_multiplier = 1; 4324 } 4325 4326 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { 4327 tmp = intel_de_read(dev_priv, CHICKEN_TRANS(pipe_config->cpu_transcoder)); 4328 4329 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1; 4330 } else { 4331 /* no idea if this is correct */ 4332 pipe_config->framestart_delay = 1; 4333 } 4334 4335 out: 4336 intel_display_power_put_all_in_set(dev_priv, &power_domain_set); 4337 4338 return active; 4339 } 4340 4341 static bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state) 4342 { 4343 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4344 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4345 4346 if (!i915->display->get_pipe_config(crtc, crtc_state)) 4347 return false; 4348 4349 crtc_state->hw.active = true; 4350 4351 intel_crtc_readout_derived_state(crtc_state); 4352 4353 return true; 4354 } 4355 4356 /* VESA 640x480x72Hz mode to set on the pipe */ 4357 static const struct drm_display_mode load_detect_mode = { 4358 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, 4359 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 4360 }; 4361 4362 static int intel_modeset_disable_planes(struct drm_atomic_state *state, 4363 struct drm_crtc *crtc) 4364 { 4365 struct drm_plane *plane; 4366 struct drm_plane_state *plane_state; 4367 int ret, i; 4368 4369 ret = drm_atomic_add_affected_planes(state, crtc); 4370 if (ret) 4371 return ret; 4372 4373 for_each_new_plane_in_state(state, plane, plane_state, i) { 4374 if (plane_state->crtc != crtc) 4375 continue; 4376 4377 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL); 4378 if (ret) 4379 return ret; 4380 4381 drm_atomic_set_fb_for_plane(plane_state, NULL); 4382 } 4383 4384 return 0; 4385 } 4386 4387 int intel_get_load_detect_pipe(struct drm_connector *connector, 4388 struct intel_load_detect_pipe *old, 4389 struct drm_modeset_acquire_ctx *ctx) 4390 { 4391 struct intel_encoder *encoder = 4392 intel_attached_encoder(to_intel_connector(connector)); 4393 struct intel_crtc *possible_crtc; 4394 struct intel_crtc *crtc = NULL; 4395 struct drm_device *dev = encoder->base.dev; 4396 struct drm_i915_private *dev_priv = to_i915(dev); 4397 struct drm_mode_config *config = &dev->mode_config; 4398 struct drm_atomic_state *state = NULL, *restore_state = NULL; 4399 struct drm_connector_state *connector_state; 4400 struct intel_crtc_state *crtc_state; 4401 int ret; 4402 4403 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 4404 connector->base.id, connector->name, 4405 encoder->base.base.id, encoder->base.name); 4406 4407 old->restore_state = NULL; 4408 4409 drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex)); 4410 4411 /* 4412 * Algorithm gets a little messy: 4413 * 4414 * - if the connector already has an assigned crtc, use it (but make 4415 * sure it's on first) 4416 * 4417 * - try to find the first unused crtc that can drive this connector, 4418 * and use that if we find one 4419 */ 4420 4421 /* See if we already have a CRTC for this connector */ 4422 if (connector->state->crtc) { 4423 crtc = to_intel_crtc(connector->state->crtc); 4424 4425 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4426 if (ret) 4427 goto fail; 4428 4429 /* Make sure the crtc and connector are running */ 4430 goto found; 4431 } 4432 4433 /* Find an unused one (if possible) */ 4434 for_each_intel_crtc(dev, possible_crtc) { 4435 if (!(encoder->base.possible_crtcs & 4436 drm_crtc_mask(&possible_crtc->base))) 4437 continue; 4438 4439 ret = drm_modeset_lock(&possible_crtc->base.mutex, ctx); 4440 if (ret) 4441 goto fail; 4442 4443 if (possible_crtc->base.state->enable) { 4444 drm_modeset_unlock(&possible_crtc->base.mutex); 4445 continue; 4446 } 4447 4448 crtc = possible_crtc; 4449 break; 4450 } 4451 4452 /* 4453 * If we didn't find an unused CRTC, don't use any. 4454 */ 4455 if (!crtc) { 4456 drm_dbg_kms(&dev_priv->drm, 4457 "no pipe available for load-detect\n"); 4458 ret = -ENODEV; 4459 goto fail; 4460 } 4461 4462 found: 4463 state = drm_atomic_state_alloc(dev); 4464 restore_state = drm_atomic_state_alloc(dev); 4465 if (!state || !restore_state) { 4466 ret = -ENOMEM; 4467 goto fail; 4468 } 4469 4470 state->acquire_ctx = ctx; 4471 restore_state->acquire_ctx = ctx; 4472 4473 connector_state = drm_atomic_get_connector_state(state, connector); 4474 if (IS_ERR(connector_state)) { 4475 ret = PTR_ERR(connector_state); 4476 goto fail; 4477 } 4478 4479 ret = drm_atomic_set_crtc_for_connector(connector_state, &crtc->base); 4480 if (ret) 4481 goto fail; 4482 4483 crtc_state = intel_atomic_get_crtc_state(state, crtc); 4484 if (IS_ERR(crtc_state)) { 4485 ret = PTR_ERR(crtc_state); 4486 goto fail; 4487 } 4488 4489 crtc_state->uapi.active = true; 4490 4491 ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi, 4492 &load_detect_mode); 4493 if (ret) 4494 goto fail; 4495 4496 ret = intel_modeset_disable_planes(state, &crtc->base); 4497 if (ret) 4498 goto fail; 4499 4500 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); 4501 if (!ret) 4502 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, &crtc->base)); 4503 if (!ret) 4504 ret = drm_atomic_add_affected_planes(restore_state, &crtc->base); 4505 if (ret) { 4506 drm_dbg_kms(&dev_priv->drm, 4507 "Failed to create a copy of old state to restore: %i\n", 4508 ret); 4509 goto fail; 4510 } 4511 4512 ret = drm_atomic_commit(state); 4513 if (ret) { 4514 drm_dbg_kms(&dev_priv->drm, 4515 "failed to set mode on load-detect pipe\n"); 4516 goto fail; 4517 } 4518 4519 old->restore_state = restore_state; 4520 drm_atomic_state_put(state); 4521 4522 /* let the connector get through one full cycle before testing */ 4523 intel_crtc_wait_for_next_vblank(crtc); 4524 4525 return true; 4526 4527 fail: 4528 if (state) { 4529 drm_atomic_state_put(state); 4530 state = NULL; 4531 } 4532 if (restore_state) { 4533 drm_atomic_state_put(restore_state); 4534 restore_state = NULL; 4535 } 4536 4537 if (ret == -EDEADLK) 4538 return ret; 4539 4540 return false; 4541 } 4542 4543 void intel_release_load_detect_pipe(struct drm_connector *connector, 4544 struct intel_load_detect_pipe *old, 4545 struct drm_modeset_acquire_ctx *ctx) 4546 { 4547 struct intel_encoder *intel_encoder = 4548 intel_attached_encoder(to_intel_connector(connector)); 4549 struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev); 4550 struct drm_encoder *encoder = &intel_encoder->base; 4551 struct drm_atomic_state *state = old->restore_state; 4552 int ret; 4553 4554 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 4555 connector->base.id, connector->name, 4556 encoder->base.id, encoder->name); 4557 4558 if (!state) 4559 return; 4560 4561 ret = drm_atomic_helper_commit_duplicated_state(state, ctx); 4562 if (ret) 4563 drm_dbg_kms(&i915->drm, 4564 "Couldn't release load detect pipe: %i\n", ret); 4565 drm_atomic_state_put(state); 4566 } 4567 4568 static int i9xx_pll_refclk(struct drm_device *dev, 4569 const struct intel_crtc_state *pipe_config) 4570 { 4571 struct drm_i915_private *dev_priv = to_i915(dev); 4572 u32 dpll = pipe_config->dpll_hw_state.dpll; 4573 4574 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) 4575 return dev_priv->vbt.lvds_ssc_freq; 4576 else if (HAS_PCH_SPLIT(dev_priv)) 4577 return 120000; 4578 else if (DISPLAY_VER(dev_priv) != 2) 4579 return 96000; 4580 else 4581 return 48000; 4582 } 4583 4584 /* Returns the clock of the currently programmed mode of the given pipe. */ 4585 void i9xx_crtc_clock_get(struct intel_crtc *crtc, 4586 struct intel_crtc_state *pipe_config) 4587 { 4588 struct drm_device *dev = crtc->base.dev; 4589 struct drm_i915_private *dev_priv = to_i915(dev); 4590 u32 dpll = pipe_config->dpll_hw_state.dpll; 4591 u32 fp; 4592 struct dpll clock; 4593 int port_clock; 4594 int refclk = i9xx_pll_refclk(dev, pipe_config); 4595 4596 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 4597 fp = pipe_config->dpll_hw_state.fp0; 4598 else 4599 fp = pipe_config->dpll_hw_state.fp1; 4600 4601 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 4602 if (IS_PINEVIEW(dev_priv)) { 4603 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; 4604 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; 4605 } else { 4606 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 4607 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 4608 } 4609 4610 if (DISPLAY_VER(dev_priv) != 2) { 4611 if (IS_PINEVIEW(dev_priv)) 4612 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> 4613 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); 4614 else 4615 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> 4616 DPLL_FPA01_P1_POST_DIV_SHIFT); 4617 4618 switch (dpll & DPLL_MODE_MASK) { 4619 case DPLLB_MODE_DAC_SERIAL: 4620 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 4621 5 : 10; 4622 break; 4623 case DPLLB_MODE_LVDS: 4624 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 4625 7 : 14; 4626 break; 4627 default: 4628 drm_dbg_kms(&dev_priv->drm, 4629 "Unknown DPLL mode %08x in programmed " 4630 "mode\n", (int)(dpll & DPLL_MODE_MASK)); 4631 return; 4632 } 4633 4634 if (IS_PINEVIEW(dev_priv)) 4635 port_clock = pnv_calc_dpll_params(refclk, &clock); 4636 else 4637 port_clock = i9xx_calc_dpll_params(refclk, &clock); 4638 } else { 4639 enum pipe lvds_pipe; 4640 4641 if (IS_I85X(dev_priv) && 4642 intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) && 4643 lvds_pipe == crtc->pipe) { 4644 u32 lvds = intel_de_read(dev_priv, LVDS); 4645 4646 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 4647 DPLL_FPA01_P1_POST_DIV_SHIFT); 4648 4649 if (lvds & LVDS_CLKB_POWER_UP) 4650 clock.p2 = 7; 4651 else 4652 clock.p2 = 14; 4653 } else { 4654 if (dpll & PLL_P1_DIVIDE_BY_TWO) 4655 clock.p1 = 2; 4656 else { 4657 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 4658 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 4659 } 4660 if (dpll & PLL_P2_DIVIDE_BY_4) 4661 clock.p2 = 4; 4662 else 4663 clock.p2 = 2; 4664 } 4665 4666 port_clock = i9xx_calc_dpll_params(refclk, &clock); 4667 } 4668 4669 /* 4670 * This value includes pixel_multiplier. We will use 4671 * port_clock to compute adjusted_mode.crtc_clock in the 4672 * encoder's get_config() function. 4673 */ 4674 pipe_config->port_clock = port_clock; 4675 } 4676 4677 int intel_dotclock_calculate(int link_freq, 4678 const struct intel_link_m_n *m_n) 4679 { 4680 /* 4681 * The calculation for the data clock is: 4682 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp 4683 * But we want to avoid losing precison if possible, so: 4684 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) 4685 * 4686 * and the link clock is simpler: 4687 * link_clock = (m * link_clock) / n 4688 */ 4689 4690 if (!m_n->link_n) 4691 return 0; 4692 4693 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n); 4694 } 4695 4696 /* Returns the currently programmed mode of the given encoder. */ 4697 struct drm_display_mode * 4698 intel_encoder_current_mode(struct intel_encoder *encoder) 4699 { 4700 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4701 struct intel_crtc_state *crtc_state; 4702 struct drm_display_mode *mode; 4703 struct intel_crtc *crtc; 4704 enum pipe pipe; 4705 4706 if (!encoder->get_hw_state(encoder, &pipe)) 4707 return NULL; 4708 4709 crtc = intel_crtc_for_pipe(dev_priv, pipe); 4710 4711 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 4712 if (!mode) 4713 return NULL; 4714 4715 crtc_state = intel_crtc_state_alloc(crtc); 4716 if (!crtc_state) { 4717 kfree(mode); 4718 return NULL; 4719 } 4720 4721 if (!intel_crtc_get_pipe_config(crtc_state)) { 4722 kfree(crtc_state); 4723 kfree(mode); 4724 return NULL; 4725 } 4726 4727 intel_encoder_get_config(encoder, crtc_state); 4728 4729 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode); 4730 4731 kfree(crtc_state); 4732 4733 return mode; 4734 } 4735 4736 static bool encoders_cloneable(const struct intel_encoder *a, 4737 const struct intel_encoder *b) 4738 { 4739 /* masks could be asymmetric, so check both ways */ 4740 return a == b || (a->cloneable & (1 << b->type) && 4741 b->cloneable & (1 << a->type)); 4742 } 4743 4744 static bool check_single_encoder_cloning(struct intel_atomic_state *state, 4745 struct intel_crtc *crtc, 4746 struct intel_encoder *encoder) 4747 { 4748 struct intel_encoder *source_encoder; 4749 struct drm_connector *connector; 4750 struct drm_connector_state *connector_state; 4751 int i; 4752 4753 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4754 if (connector_state->crtc != &crtc->base) 4755 continue; 4756 4757 source_encoder = 4758 to_intel_encoder(connector_state->best_encoder); 4759 if (!encoders_cloneable(encoder, source_encoder)) 4760 return false; 4761 } 4762 4763 return true; 4764 } 4765 4766 static int icl_add_linked_planes(struct intel_atomic_state *state) 4767 { 4768 struct intel_plane *plane, *linked; 4769 struct intel_plane_state *plane_state, *linked_plane_state; 4770 int i; 4771 4772 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4773 linked = plane_state->planar_linked_plane; 4774 4775 if (!linked) 4776 continue; 4777 4778 linked_plane_state = intel_atomic_get_plane_state(state, linked); 4779 if (IS_ERR(linked_plane_state)) 4780 return PTR_ERR(linked_plane_state); 4781 4782 drm_WARN_ON(state->base.dev, 4783 linked_plane_state->planar_linked_plane != plane); 4784 drm_WARN_ON(state->base.dev, 4785 linked_plane_state->planar_slave == plane_state->planar_slave); 4786 } 4787 4788 return 0; 4789 } 4790 4791 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state) 4792 { 4793 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4794 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4795 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 4796 struct intel_plane *plane, *linked; 4797 struct intel_plane_state *plane_state; 4798 int i; 4799 4800 if (DISPLAY_VER(dev_priv) < 11) 4801 return 0; 4802 4803 /* 4804 * Destroy all old plane links and make the slave plane invisible 4805 * in the crtc_state->active_planes mask. 4806 */ 4807 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4808 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane) 4809 continue; 4810 4811 plane_state->planar_linked_plane = NULL; 4812 if (plane_state->planar_slave && !plane_state->uapi.visible) { 4813 crtc_state->enabled_planes &= ~BIT(plane->id); 4814 crtc_state->active_planes &= ~BIT(plane->id); 4815 crtc_state->update_planes |= BIT(plane->id); 4816 } 4817 4818 plane_state->planar_slave = false; 4819 } 4820 4821 if (!crtc_state->nv12_planes) 4822 return 0; 4823 4824 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4825 struct intel_plane_state *linked_state = NULL; 4826 4827 if (plane->pipe != crtc->pipe || 4828 !(crtc_state->nv12_planes & BIT(plane->id))) 4829 continue; 4830 4831 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) { 4832 if (!icl_is_nv12_y_plane(dev_priv, linked->id)) 4833 continue; 4834 4835 if (crtc_state->active_planes & BIT(linked->id)) 4836 continue; 4837 4838 linked_state = intel_atomic_get_plane_state(state, linked); 4839 if (IS_ERR(linked_state)) 4840 return PTR_ERR(linked_state); 4841 4842 break; 4843 } 4844 4845 if (!linked_state) { 4846 drm_dbg_kms(&dev_priv->drm, 4847 "Need %d free Y planes for planar YUV\n", 4848 hweight8(crtc_state->nv12_planes)); 4849 4850 return -EINVAL; 4851 } 4852 4853 plane_state->planar_linked_plane = linked; 4854 4855 linked_state->planar_slave = true; 4856 linked_state->planar_linked_plane = plane; 4857 crtc_state->enabled_planes |= BIT(linked->id); 4858 crtc_state->active_planes |= BIT(linked->id); 4859 crtc_state->update_planes |= BIT(linked->id); 4860 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n", 4861 linked->base.name, plane->base.name); 4862 4863 /* Copy parameters to slave plane */ 4864 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE; 4865 linked_state->color_ctl = plane_state->color_ctl; 4866 linked_state->view = plane_state->view; 4867 linked_state->decrypt = plane_state->decrypt; 4868 4869 intel_plane_copy_hw_state(linked_state, plane_state); 4870 linked_state->uapi.src = plane_state->uapi.src; 4871 linked_state->uapi.dst = plane_state->uapi.dst; 4872 4873 if (icl_is_hdr_plane(dev_priv, plane->id)) { 4874 if (linked->id == PLANE_SPRITE5) 4875 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL; 4876 else if (linked->id == PLANE_SPRITE4) 4877 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL; 4878 else if (linked->id == PLANE_SPRITE3) 4879 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL; 4880 else if (linked->id == PLANE_SPRITE2) 4881 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL; 4882 else 4883 MISSING_CASE(linked->id); 4884 } 4885 } 4886 4887 return 0; 4888 } 4889 4890 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state) 4891 { 4892 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 4893 struct intel_atomic_state *state = 4894 to_intel_atomic_state(new_crtc_state->uapi.state); 4895 const struct intel_crtc_state *old_crtc_state = 4896 intel_atomic_get_old_crtc_state(state, crtc); 4897 4898 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes; 4899 } 4900 4901 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) 4902 { 4903 const struct drm_display_mode *pipe_mode = 4904 &crtc_state->hw.pipe_mode; 4905 int linetime_wm; 4906 4907 if (!crtc_state->hw.enable) 4908 return 0; 4909 4910 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4911 pipe_mode->crtc_clock); 4912 4913 return min(linetime_wm, 0x1ff); 4914 } 4915 4916 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, 4917 const struct intel_cdclk_state *cdclk_state) 4918 { 4919 const struct drm_display_mode *pipe_mode = 4920 &crtc_state->hw.pipe_mode; 4921 int linetime_wm; 4922 4923 if (!crtc_state->hw.enable) 4924 return 0; 4925 4926 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4927 cdclk_state->logical.cdclk); 4928 4929 return min(linetime_wm, 0x1ff); 4930 } 4931 4932 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) 4933 { 4934 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4935 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4936 const struct drm_display_mode *pipe_mode = 4937 &crtc_state->hw.pipe_mode; 4938 int linetime_wm; 4939 4940 if (!crtc_state->hw.enable) 4941 return 0; 4942 4943 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8, 4944 crtc_state->pixel_rate); 4945 4946 /* Display WA #1135: BXT:ALL GLK:ALL */ 4947 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 4948 dev_priv->ipc_enabled) 4949 linetime_wm /= 2; 4950 4951 return min(linetime_wm, 0x1ff); 4952 } 4953 4954 static int hsw_compute_linetime_wm(struct intel_atomic_state *state, 4955 struct intel_crtc *crtc) 4956 { 4957 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4958 struct intel_crtc_state *crtc_state = 4959 intel_atomic_get_new_crtc_state(state, crtc); 4960 const struct intel_cdclk_state *cdclk_state; 4961 4962 if (DISPLAY_VER(dev_priv) >= 9) 4963 crtc_state->linetime = skl_linetime_wm(crtc_state); 4964 else 4965 crtc_state->linetime = hsw_linetime_wm(crtc_state); 4966 4967 if (!hsw_crtc_supports_ips(crtc)) 4968 return 0; 4969 4970 cdclk_state = intel_atomic_get_cdclk_state(state); 4971 if (IS_ERR(cdclk_state)) 4972 return PTR_ERR(cdclk_state); 4973 4974 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state, 4975 cdclk_state); 4976 4977 return 0; 4978 } 4979 4980 static int intel_crtc_atomic_check(struct intel_atomic_state *state, 4981 struct intel_crtc *crtc) 4982 { 4983 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4984 struct intel_crtc_state *crtc_state = 4985 intel_atomic_get_new_crtc_state(state, crtc); 4986 bool mode_changed = intel_crtc_needs_modeset(crtc_state); 4987 int ret; 4988 4989 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) && 4990 mode_changed && !crtc_state->hw.active) 4991 crtc_state->update_wm_post = true; 4992 4993 if (mode_changed && crtc_state->hw.enable && 4994 !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) { 4995 ret = intel_dpll_crtc_compute_clock(crtc_state); 4996 if (ret) 4997 return ret; 4998 } 4999 5000 /* 5001 * May need to update pipe gamma enable bits 5002 * when C8 planes are getting enabled/disabled. 5003 */ 5004 if (c8_planes_changed(crtc_state)) 5005 crtc_state->uapi.color_mgmt_changed = true; 5006 5007 if (mode_changed || crtc_state->update_pipe || 5008 crtc_state->uapi.color_mgmt_changed) { 5009 ret = intel_color_check(crtc_state); 5010 if (ret) 5011 return ret; 5012 } 5013 5014 ret = intel_compute_pipe_wm(state, crtc); 5015 if (ret) { 5016 drm_dbg_kms(&dev_priv->drm, 5017 "Target pipe watermarks are invalid\n"); 5018 return ret; 5019 } 5020 5021 /* 5022 * Calculate 'intermediate' watermarks that satisfy both the 5023 * old state and the new state. We can program these 5024 * immediately. 5025 */ 5026 ret = intel_compute_intermediate_wm(state, crtc); 5027 if (ret) { 5028 drm_dbg_kms(&dev_priv->drm, 5029 "No valid intermediate pipe watermarks are possible\n"); 5030 return ret; 5031 } 5032 5033 if (DISPLAY_VER(dev_priv) >= 9) { 5034 if (mode_changed || crtc_state->update_pipe) { 5035 ret = skl_update_scaler_crtc(crtc_state); 5036 if (ret) 5037 return ret; 5038 } 5039 5040 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state); 5041 if (ret) 5042 return ret; 5043 } 5044 5045 if (HAS_IPS(dev_priv)) { 5046 ret = hsw_ips_compute_config(state, crtc); 5047 if (ret) 5048 return ret; 5049 } 5050 5051 if (DISPLAY_VER(dev_priv) >= 9 || 5052 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 5053 ret = hsw_compute_linetime_wm(state, crtc); 5054 if (ret) 5055 return ret; 5056 5057 } 5058 5059 ret = intel_psr2_sel_fetch_update(state, crtc); 5060 if (ret) 5061 return ret; 5062 5063 return 0; 5064 } 5065 5066 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) 5067 { 5068 struct intel_connector *connector; 5069 struct drm_connector_list_iter conn_iter; 5070 5071 drm_connector_list_iter_begin(dev, &conn_iter); 5072 for_each_intel_connector_iter(connector, &conn_iter) { 5073 struct drm_connector_state *conn_state = connector->base.state; 5074 struct intel_encoder *encoder = 5075 to_intel_encoder(connector->base.encoder); 5076 5077 if (conn_state->crtc) 5078 drm_connector_put(&connector->base); 5079 5080 if (encoder) { 5081 struct intel_crtc *crtc = 5082 to_intel_crtc(encoder->base.crtc); 5083 const struct intel_crtc_state *crtc_state = 5084 to_intel_crtc_state(crtc->base.state); 5085 5086 conn_state->best_encoder = &encoder->base; 5087 conn_state->crtc = &crtc->base; 5088 conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3; 5089 5090 drm_connector_get(&connector->base); 5091 } else { 5092 conn_state->best_encoder = NULL; 5093 conn_state->crtc = NULL; 5094 } 5095 } 5096 drm_connector_list_iter_end(&conn_iter); 5097 } 5098 5099 static int 5100 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state, 5101 struct intel_crtc_state *pipe_config) 5102 { 5103 struct drm_connector *connector = conn_state->connector; 5104 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); 5105 const struct drm_display_info *info = &connector->display_info; 5106 int bpp; 5107 5108 switch (conn_state->max_bpc) { 5109 case 6 ... 7: 5110 bpp = 6 * 3; 5111 break; 5112 case 8 ... 9: 5113 bpp = 8 * 3; 5114 break; 5115 case 10 ... 11: 5116 bpp = 10 * 3; 5117 break; 5118 case 12 ... 16: 5119 bpp = 12 * 3; 5120 break; 5121 default: 5122 MISSING_CASE(conn_state->max_bpc); 5123 return -EINVAL; 5124 } 5125 5126 if (bpp < pipe_config->pipe_bpp) { 5127 drm_dbg_kms(&i915->drm, 5128 "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of " 5129 "EDID bpp %d, requested bpp %d, max platform bpp %d\n", 5130 connector->base.id, connector->name, 5131 bpp, 3 * info->bpc, 5132 3 * conn_state->max_requested_bpc, 5133 pipe_config->pipe_bpp); 5134 5135 pipe_config->pipe_bpp = bpp; 5136 } 5137 5138 return 0; 5139 } 5140 5141 static int 5142 compute_baseline_pipe_bpp(struct intel_crtc *crtc, 5143 struct intel_crtc_state *pipe_config) 5144 { 5145 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5146 struct drm_atomic_state *state = pipe_config->uapi.state; 5147 struct drm_connector *connector; 5148 struct drm_connector_state *connector_state; 5149 int bpp, i; 5150 5151 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 5152 IS_CHERRYVIEW(dev_priv))) 5153 bpp = 10*3; 5154 else if (DISPLAY_VER(dev_priv) >= 5) 5155 bpp = 12*3; 5156 else 5157 bpp = 8*3; 5158 5159 pipe_config->pipe_bpp = bpp; 5160 5161 /* Clamp display bpp to connector max bpp */ 5162 for_each_new_connector_in_state(state, connector, connector_state, i) { 5163 int ret; 5164 5165 if (connector_state->crtc != &crtc->base) 5166 continue; 5167 5168 ret = compute_sink_pipe_bpp(connector_state, pipe_config); 5169 if (ret) 5170 return ret; 5171 } 5172 5173 return 0; 5174 } 5175 5176 static void intel_dump_crtc_timings(struct drm_i915_private *i915, 5177 const struct drm_display_mode *mode) 5178 { 5179 drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, " 5180 "type: 0x%x flags: 0x%x\n", 5181 mode->crtc_clock, 5182 mode->crtc_hdisplay, mode->crtc_hsync_start, 5183 mode->crtc_hsync_end, mode->crtc_htotal, 5184 mode->crtc_vdisplay, mode->crtc_vsync_start, 5185 mode->crtc_vsync_end, mode->crtc_vtotal, 5186 mode->type, mode->flags); 5187 } 5188 5189 static void 5190 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config, 5191 const char *id, unsigned int lane_count, 5192 const struct intel_link_m_n *m_n) 5193 { 5194 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); 5195 5196 drm_dbg_kms(&i915->drm, 5197 "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n", 5198 id, lane_count, 5199 m_n->data_m, m_n->data_n, 5200 m_n->link_m, m_n->link_n, m_n->tu); 5201 } 5202 5203 static void 5204 intel_dump_infoframe(struct drm_i915_private *dev_priv, 5205 const union hdmi_infoframe *frame) 5206 { 5207 if (!drm_debug_enabled(DRM_UT_KMS)) 5208 return; 5209 5210 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame); 5211 } 5212 5213 static void 5214 intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv, 5215 const struct drm_dp_vsc_sdp *vsc) 5216 { 5217 if (!drm_debug_enabled(DRM_UT_KMS)) 5218 return; 5219 5220 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc); 5221 } 5222 5223 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x 5224 5225 static const char * const output_type_str[] = { 5226 OUTPUT_TYPE(UNUSED), 5227 OUTPUT_TYPE(ANALOG), 5228 OUTPUT_TYPE(DVO), 5229 OUTPUT_TYPE(SDVO), 5230 OUTPUT_TYPE(LVDS), 5231 OUTPUT_TYPE(TVOUT), 5232 OUTPUT_TYPE(HDMI), 5233 OUTPUT_TYPE(DP), 5234 OUTPUT_TYPE(EDP), 5235 OUTPUT_TYPE(DSI), 5236 OUTPUT_TYPE(DDI), 5237 OUTPUT_TYPE(DP_MST), 5238 }; 5239 5240 #undef OUTPUT_TYPE 5241 5242 static void snprintf_output_types(char *buf, size_t len, 5243 unsigned int output_types) 5244 { 5245 char *str = buf; 5246 int i; 5247 5248 str[0] = '\0'; 5249 5250 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) { 5251 int r; 5252 5253 if ((output_types & BIT(i)) == 0) 5254 continue; 5255 5256 r = snprintf(str, len, "%s%s", 5257 str != buf ? "," : "", output_type_str[i]); 5258 if (r >= len) 5259 break; 5260 str += r; 5261 len -= r; 5262 5263 output_types &= ~BIT(i); 5264 } 5265 5266 WARN_ON_ONCE(output_types != 0); 5267 } 5268 5269 static const char * const output_format_str[] = { 5270 [INTEL_OUTPUT_FORMAT_RGB] = "RGB", 5271 [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0", 5272 [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4", 5273 }; 5274 5275 static const char *output_formats(enum intel_output_format format) 5276 { 5277 if (format >= ARRAY_SIZE(output_format_str)) 5278 return "invalid"; 5279 return output_format_str[format]; 5280 } 5281 5282 static void intel_dump_plane_state(const struct intel_plane_state *plane_state) 5283 { 5284 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 5285 struct drm_i915_private *i915 = to_i915(plane->base.dev); 5286 const struct drm_framebuffer *fb = plane_state->hw.fb; 5287 5288 if (!fb) { 5289 drm_dbg_kms(&i915->drm, 5290 "[PLANE:%d:%s] fb: [NOFB], visible: %s\n", 5291 plane->base.base.id, plane->base.name, 5292 str_yes_no(plane_state->uapi.visible)); 5293 return; 5294 } 5295 5296 drm_dbg_kms(&i915->drm, 5297 "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %p4cc modifier = 0x%llx, visible: %s\n", 5298 plane->base.base.id, plane->base.name, 5299 fb->base.id, fb->width, fb->height, &fb->format->format, 5300 fb->modifier, str_yes_no(plane_state->uapi.visible)); 5301 drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n", 5302 plane_state->hw.rotation, plane_state->scaler_id); 5303 if (plane_state->uapi.visible) 5304 drm_dbg_kms(&i915->drm, 5305 "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n", 5306 DRM_RECT_FP_ARG(&plane_state->uapi.src), 5307 DRM_RECT_ARG(&plane_state->uapi.dst)); 5308 } 5309 5310 static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, 5311 struct intel_atomic_state *state, 5312 const char *context) 5313 { 5314 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 5315 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5316 const struct intel_plane_state *plane_state; 5317 struct intel_plane *plane; 5318 char buf[64]; 5319 int i; 5320 5321 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n", 5322 crtc->base.base.id, crtc->base.name, 5323 str_yes_no(pipe_config->hw.enable), context); 5324 5325 if (!pipe_config->hw.enable) 5326 goto dump_planes; 5327 5328 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types); 5329 drm_dbg_kms(&dev_priv->drm, 5330 "active: %s, output_types: %s (0x%x), output format: %s\n", 5331 str_yes_no(pipe_config->hw.active), 5332 buf, pipe_config->output_types, 5333 output_formats(pipe_config->output_format)); 5334 5335 drm_dbg_kms(&dev_priv->drm, 5336 "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", 5337 transcoder_name(pipe_config->cpu_transcoder), 5338 pipe_config->pipe_bpp, pipe_config->dither); 5339 5340 drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n", 5341 transcoder_name(pipe_config->mst_master_transcoder)); 5342 5343 drm_dbg_kms(&dev_priv->drm, 5344 "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n", 5345 transcoder_name(pipe_config->master_transcoder), 5346 pipe_config->sync_mode_slaves_mask); 5347 5348 drm_dbg_kms(&dev_priv->drm, "bigjoiner: %s, pipes: 0x%x\n", 5349 intel_crtc_is_bigjoiner_slave(pipe_config) ? "slave" : 5350 intel_crtc_is_bigjoiner_master(pipe_config) ? "master" : "no", 5351 pipe_config->bigjoiner_pipes); 5352 5353 drm_dbg_kms(&dev_priv->drm, "splitter: %s, link count %d, overlap %d\n", 5354 str_enabled_disabled(pipe_config->splitter.enable), 5355 pipe_config->splitter.link_count, 5356 pipe_config->splitter.pixel_overlap); 5357 5358 if (pipe_config->has_pch_encoder) 5359 intel_dump_m_n_config(pipe_config, "fdi", 5360 pipe_config->fdi_lanes, 5361 &pipe_config->fdi_m_n); 5362 5363 if (intel_crtc_has_dp_encoder(pipe_config)) { 5364 intel_dump_m_n_config(pipe_config, "dp m_n", 5365 pipe_config->lane_count, 5366 &pipe_config->dp_m_n); 5367 intel_dump_m_n_config(pipe_config, "dp m2_n2", 5368 pipe_config->lane_count, 5369 &pipe_config->dp_m2_n2); 5370 } 5371 5372 drm_dbg_kms(&dev_priv->drm, "framestart delay: %d, MSA timing delay: %d\n", 5373 pipe_config->framestart_delay, pipe_config->msa_timing_delay); 5374 5375 drm_dbg_kms(&dev_priv->drm, 5376 "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n", 5377 pipe_config->has_audio, pipe_config->has_infoframe, 5378 pipe_config->infoframes.enable); 5379 5380 if (pipe_config->infoframes.enable & 5381 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) 5382 drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n", 5383 pipe_config->infoframes.gcp); 5384 if (pipe_config->infoframes.enable & 5385 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) 5386 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi); 5387 if (pipe_config->infoframes.enable & 5388 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD)) 5389 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd); 5390 if (pipe_config->infoframes.enable & 5391 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR)) 5392 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi); 5393 if (pipe_config->infoframes.enable & 5394 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) 5395 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); 5396 if (pipe_config->infoframes.enable & 5397 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA)) 5398 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); 5399 if (pipe_config->infoframes.enable & 5400 intel_hdmi_infoframe_enable(DP_SDP_VSC)) 5401 intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc); 5402 5403 drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n", 5404 str_yes_no(pipe_config->vrr.enable), 5405 pipe_config->vrr.vmin, pipe_config->vrr.vmax, 5406 pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband, 5407 pipe_config->vrr.flipline, 5408 intel_vrr_vmin_vblank_start(pipe_config), 5409 intel_vrr_vmax_vblank_start(pipe_config)); 5410 5411 drm_dbg_kms(&dev_priv->drm, "requested mode:\n"); 5412 drm_mode_debug_printmodeline(&pipe_config->hw.mode); 5413 drm_dbg_kms(&dev_priv->drm, "adjusted mode:\n"); 5414 drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode); 5415 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode); 5416 drm_dbg_kms(&dev_priv->drm, "pipe mode:\n"); 5417 drm_mode_debug_printmodeline(&pipe_config->hw.pipe_mode); 5418 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode); 5419 drm_dbg_kms(&dev_priv->drm, 5420 "port clock: %d, pipe src: " DRM_RECT_FMT ", pixel rate %d\n", 5421 pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src), 5422 pipe_config->pixel_rate); 5423 5424 drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n", 5425 pipe_config->linetime, pipe_config->ips_linetime); 5426 5427 if (DISPLAY_VER(dev_priv) >= 9) 5428 drm_dbg_kms(&dev_priv->drm, 5429 "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", 5430 crtc->num_scalers, 5431 pipe_config->scaler_state.scaler_users, 5432 pipe_config->scaler_state.scaler_id); 5433 5434 if (HAS_GMCH(dev_priv)) 5435 drm_dbg_kms(&dev_priv->drm, 5436 "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", 5437 pipe_config->gmch_pfit.control, 5438 pipe_config->gmch_pfit.pgm_ratios, 5439 pipe_config->gmch_pfit.lvds_border_bits); 5440 else 5441 drm_dbg_kms(&dev_priv->drm, 5442 "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n", 5443 DRM_RECT_ARG(&pipe_config->pch_pfit.dst), 5444 str_enabled_disabled(pipe_config->pch_pfit.enabled), 5445 str_yes_no(pipe_config->pch_pfit.force_thru)); 5446 5447 drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i, drrs: %i\n", 5448 pipe_config->ips_enabled, pipe_config->double_wide, 5449 pipe_config->has_drrs); 5450 5451 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state); 5452 5453 if (IS_CHERRYVIEW(dev_priv)) 5454 drm_dbg_kms(&dev_priv->drm, 5455 "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", 5456 pipe_config->cgm_mode, pipe_config->gamma_mode, 5457 pipe_config->gamma_enable, pipe_config->csc_enable); 5458 else 5459 drm_dbg_kms(&dev_priv->drm, 5460 "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", 5461 pipe_config->csc_mode, pipe_config->gamma_mode, 5462 pipe_config->gamma_enable, pipe_config->csc_enable); 5463 5464 drm_dbg_kms(&dev_priv->drm, "degamma lut: %d entries, gamma lut: %d entries\n", 5465 pipe_config->hw.degamma_lut ? 5466 drm_color_lut_size(pipe_config->hw.degamma_lut) : 0, 5467 pipe_config->hw.gamma_lut ? 5468 drm_color_lut_size(pipe_config->hw.gamma_lut) : 0); 5469 5470 dump_planes: 5471 if (!state) 5472 return; 5473 5474 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 5475 if (plane->pipe == crtc->pipe) 5476 intel_dump_plane_state(plane_state); 5477 } 5478 } 5479 5480 static bool check_digital_port_conflicts(struct intel_atomic_state *state) 5481 { 5482 struct drm_device *dev = state->base.dev; 5483 struct drm_connector *connector; 5484 struct drm_connector_list_iter conn_iter; 5485 unsigned int used_ports = 0; 5486 unsigned int used_mst_ports = 0; 5487 bool ret = true; 5488 5489 /* 5490 * We're going to peek into connector->state, 5491 * hence connection_mutex must be held. 5492 */ 5493 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex); 5494 5495 /* 5496 * Walk the connector list instead of the encoder 5497 * list to detect the problem on ddi platforms 5498 * where there's just one encoder per digital port. 5499 */ 5500 drm_connector_list_iter_begin(dev, &conn_iter); 5501 drm_for_each_connector_iter(connector, &conn_iter) { 5502 struct drm_connector_state *connector_state; 5503 struct intel_encoder *encoder; 5504 5505 connector_state = 5506 drm_atomic_get_new_connector_state(&state->base, 5507 connector); 5508 if (!connector_state) 5509 connector_state = connector->state; 5510 5511 if (!connector_state->best_encoder) 5512 continue; 5513 5514 encoder = to_intel_encoder(connector_state->best_encoder); 5515 5516 drm_WARN_ON(dev, !connector_state->crtc); 5517 5518 switch (encoder->type) { 5519 case INTEL_OUTPUT_DDI: 5520 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev)))) 5521 break; 5522 fallthrough; 5523 case INTEL_OUTPUT_DP: 5524 case INTEL_OUTPUT_HDMI: 5525 case INTEL_OUTPUT_EDP: 5526 /* the same port mustn't appear more than once */ 5527 if (used_ports & BIT(encoder->port)) 5528 ret = false; 5529 5530 used_ports |= BIT(encoder->port); 5531 break; 5532 case INTEL_OUTPUT_DP_MST: 5533 used_mst_ports |= 5534 1 << encoder->port; 5535 break; 5536 default: 5537 break; 5538 } 5539 } 5540 drm_connector_list_iter_end(&conn_iter); 5541 5542 /* can't mix MST and SST/HDMI on the same port */ 5543 if (used_ports & used_mst_ports) 5544 return false; 5545 5546 return ret; 5547 } 5548 5549 static void 5550 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state, 5551 struct intel_crtc *crtc) 5552 { 5553 struct intel_crtc_state *crtc_state = 5554 intel_atomic_get_new_crtc_state(state, crtc); 5555 5556 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 5557 5558 drm_property_replace_blob(&crtc_state->hw.degamma_lut, 5559 crtc_state->uapi.degamma_lut); 5560 drm_property_replace_blob(&crtc_state->hw.gamma_lut, 5561 crtc_state->uapi.gamma_lut); 5562 drm_property_replace_blob(&crtc_state->hw.ctm, 5563 crtc_state->uapi.ctm); 5564 } 5565 5566 static void 5567 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state, 5568 struct intel_crtc *crtc) 5569 { 5570 struct intel_crtc_state *crtc_state = 5571 intel_atomic_get_new_crtc_state(state, crtc); 5572 5573 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 5574 5575 crtc_state->hw.enable = crtc_state->uapi.enable; 5576 crtc_state->hw.active = crtc_state->uapi.active; 5577 drm_mode_copy(&crtc_state->hw.mode, 5578 &crtc_state->uapi.mode); 5579 drm_mode_copy(&crtc_state->hw.adjusted_mode, 5580 &crtc_state->uapi.adjusted_mode); 5581 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter; 5582 5583 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 5584 } 5585 5586 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state) 5587 { 5588 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 5589 return; 5590 5591 crtc_state->uapi.enable = crtc_state->hw.enable; 5592 crtc_state->uapi.active = crtc_state->hw.active; 5593 drm_WARN_ON(crtc_state->uapi.crtc->dev, 5594 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0); 5595 5596 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode; 5597 crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter; 5598 5599 drm_property_replace_blob(&crtc_state->uapi.degamma_lut, 5600 crtc_state->hw.degamma_lut); 5601 drm_property_replace_blob(&crtc_state->uapi.gamma_lut, 5602 crtc_state->hw.gamma_lut); 5603 drm_property_replace_blob(&crtc_state->uapi.ctm, 5604 crtc_state->hw.ctm); 5605 } 5606 5607 static void 5608 copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state, 5609 struct intel_crtc *slave_crtc) 5610 { 5611 struct intel_crtc_state *slave_crtc_state = 5612 intel_atomic_get_new_crtc_state(state, slave_crtc); 5613 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 5614 const struct intel_crtc_state *master_crtc_state = 5615 intel_atomic_get_new_crtc_state(state, master_crtc); 5616 5617 drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut, 5618 master_crtc_state->hw.degamma_lut); 5619 drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut, 5620 master_crtc_state->hw.gamma_lut); 5621 drm_property_replace_blob(&slave_crtc_state->hw.ctm, 5622 master_crtc_state->hw.ctm); 5623 5624 slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed; 5625 } 5626 5627 static int 5628 copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state, 5629 struct intel_crtc *slave_crtc) 5630 { 5631 struct intel_crtc_state *slave_crtc_state = 5632 intel_atomic_get_new_crtc_state(state, slave_crtc); 5633 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 5634 const struct intel_crtc_state *master_crtc_state = 5635 intel_atomic_get_new_crtc_state(state, master_crtc); 5636 struct intel_crtc_state *saved_state; 5637 5638 WARN_ON(master_crtc_state->bigjoiner_pipes != 5639 slave_crtc_state->bigjoiner_pipes); 5640 5641 saved_state = kmemdup(master_crtc_state, sizeof(*saved_state), GFP_KERNEL); 5642 if (!saved_state) 5643 return -ENOMEM; 5644 5645 /* preserve some things from the slave's original crtc state */ 5646 saved_state->uapi = slave_crtc_state->uapi; 5647 saved_state->scaler_state = slave_crtc_state->scaler_state; 5648 saved_state->shared_dpll = slave_crtc_state->shared_dpll; 5649 saved_state->dpll_hw_state = slave_crtc_state->dpll_hw_state; 5650 saved_state->crc_enabled = slave_crtc_state->crc_enabled; 5651 5652 intel_crtc_free_hw_state(slave_crtc_state); 5653 memcpy(slave_crtc_state, saved_state, sizeof(*slave_crtc_state)); 5654 kfree(saved_state); 5655 5656 /* Re-init hw state */ 5657 memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw)); 5658 slave_crtc_state->hw.enable = master_crtc_state->hw.enable; 5659 slave_crtc_state->hw.active = master_crtc_state->hw.active; 5660 drm_mode_copy(&slave_crtc_state->hw.mode, 5661 &master_crtc_state->hw.mode); 5662 drm_mode_copy(&slave_crtc_state->hw.pipe_mode, 5663 &master_crtc_state->hw.pipe_mode); 5664 drm_mode_copy(&slave_crtc_state->hw.adjusted_mode, 5665 &master_crtc_state->hw.adjusted_mode); 5666 slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter; 5667 5668 copy_bigjoiner_crtc_state_nomodeset(state, slave_crtc); 5669 5670 slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed; 5671 slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed; 5672 slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed; 5673 5674 WARN_ON(master_crtc_state->bigjoiner_pipes != 5675 slave_crtc_state->bigjoiner_pipes); 5676 5677 return 0; 5678 } 5679 5680 static int 5681 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state, 5682 struct intel_crtc *crtc) 5683 { 5684 struct intel_crtc_state *crtc_state = 5685 intel_atomic_get_new_crtc_state(state, crtc); 5686 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5687 struct intel_crtc_state *saved_state; 5688 5689 saved_state = intel_crtc_state_alloc(crtc); 5690 if (!saved_state) 5691 return -ENOMEM; 5692 5693 /* free the old crtc_state->hw members */ 5694 intel_crtc_free_hw_state(crtc_state); 5695 5696 /* FIXME: before the switch to atomic started, a new pipe_config was 5697 * kzalloc'd. Code that depends on any field being zero should be 5698 * fixed, so that the crtc_state can be safely duplicated. For now, 5699 * only fields that are know to not cause problems are preserved. */ 5700 5701 saved_state->uapi = crtc_state->uapi; 5702 saved_state->scaler_state = crtc_state->scaler_state; 5703 saved_state->shared_dpll = crtc_state->shared_dpll; 5704 saved_state->dpll_hw_state = crtc_state->dpll_hw_state; 5705 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, 5706 sizeof(saved_state->icl_port_dplls)); 5707 saved_state->crc_enabled = crtc_state->crc_enabled; 5708 if (IS_G4X(dev_priv) || 5709 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5710 saved_state->wm = crtc_state->wm; 5711 5712 memcpy(crtc_state, saved_state, sizeof(*crtc_state)); 5713 kfree(saved_state); 5714 5715 intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc); 5716 5717 return 0; 5718 } 5719 5720 static int 5721 intel_modeset_pipe_config(struct intel_atomic_state *state, 5722 struct intel_crtc_state *pipe_config) 5723 { 5724 struct drm_crtc *crtc = pipe_config->uapi.crtc; 5725 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); 5726 struct drm_connector *connector; 5727 struct drm_connector_state *connector_state; 5728 int pipe_src_w, pipe_src_h; 5729 int base_bpp, ret, i; 5730 bool retry = true; 5731 5732 pipe_config->cpu_transcoder = 5733 (enum transcoder) to_intel_crtc(crtc)->pipe; 5734 5735 pipe_config->framestart_delay = 1; 5736 5737 /* 5738 * Sanitize sync polarity flags based on requested ones. If neither 5739 * positive or negative polarity is requested, treat this as meaning 5740 * negative polarity. 5741 */ 5742 if (!(pipe_config->hw.adjusted_mode.flags & 5743 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) 5744 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; 5745 5746 if (!(pipe_config->hw.adjusted_mode.flags & 5747 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 5748 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; 5749 5750 ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc), 5751 pipe_config); 5752 if (ret) 5753 return ret; 5754 5755 base_bpp = pipe_config->pipe_bpp; 5756 5757 /* 5758 * Determine the real pipe dimensions. Note that stereo modes can 5759 * increase the actual pipe size due to the frame doubling and 5760 * insertion of additional space for blanks between the frame. This 5761 * is stored in the crtc timings. We use the requested mode to do this 5762 * computation to clearly distinguish it from the adjusted mode, which 5763 * can be changed by the connectors in the below retry loop. 5764 */ 5765 drm_mode_get_hv_timing(&pipe_config->hw.mode, 5766 &pipe_src_w, &pipe_src_h); 5767 drm_rect_init(&pipe_config->pipe_src, 0, 0, 5768 pipe_src_w, pipe_src_h); 5769 5770 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5771 struct intel_encoder *encoder = 5772 to_intel_encoder(connector_state->best_encoder); 5773 5774 if (connector_state->crtc != crtc) 5775 continue; 5776 5777 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) { 5778 drm_dbg_kms(&i915->drm, 5779 "rejecting invalid cloning configuration\n"); 5780 return -EINVAL; 5781 } 5782 5783 /* 5784 * Determine output_types before calling the .compute_config() 5785 * hooks so that the hooks can use this information safely. 5786 */ 5787 if (encoder->compute_output_type) 5788 pipe_config->output_types |= 5789 BIT(encoder->compute_output_type(encoder, pipe_config, 5790 connector_state)); 5791 else 5792 pipe_config->output_types |= BIT(encoder->type); 5793 } 5794 5795 encoder_retry: 5796 /* Ensure the port clock defaults are reset when retrying. */ 5797 pipe_config->port_clock = 0; 5798 pipe_config->pixel_multiplier = 1; 5799 5800 /* Fill in default crtc timings, allow encoders to overwrite them. */ 5801 drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode, 5802 CRTC_STEREO_DOUBLE); 5803 5804 /* Pass our mode to the connectors and the CRTC to give them a chance to 5805 * adjust it according to limitations or connector properties, and also 5806 * a chance to reject the mode entirely. 5807 */ 5808 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5809 struct intel_encoder *encoder = 5810 to_intel_encoder(connector_state->best_encoder); 5811 5812 if (connector_state->crtc != crtc) 5813 continue; 5814 5815 ret = encoder->compute_config(encoder, pipe_config, 5816 connector_state); 5817 if (ret == -EDEADLK) 5818 return ret; 5819 if (ret < 0) { 5820 drm_dbg_kms(&i915->drm, "Encoder config failure: %d\n", ret); 5821 return ret; 5822 } 5823 } 5824 5825 /* Set default port clock if not overwritten by the encoder. Needs to be 5826 * done afterwards in case the encoder adjusts the mode. */ 5827 if (!pipe_config->port_clock) 5828 pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock 5829 * pipe_config->pixel_multiplier; 5830 5831 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); 5832 if (ret == -EDEADLK) 5833 return ret; 5834 if (ret == -EAGAIN) { 5835 if (drm_WARN(&i915->drm, !retry, 5836 "loop in pipe configuration computation\n")) 5837 return -EINVAL; 5838 5839 drm_dbg_kms(&i915->drm, "CRTC bw constrained, retrying\n"); 5840 retry = false; 5841 goto encoder_retry; 5842 } 5843 if (ret < 0) { 5844 drm_dbg_kms(&i915->drm, "CRTC config failure: %d\n", ret); 5845 return ret; 5846 } 5847 5848 /* Dithering seems to not pass-through bits correctly when it should, so 5849 * only enable it on 6bpc panels and when its not a compliance 5850 * test requesting 6bpc video pattern. 5851 */ 5852 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) && 5853 !pipe_config->dither_force_disable; 5854 drm_dbg_kms(&i915->drm, 5855 "hw max bpp: %i, pipe bpp: %i, dithering: %i\n", 5856 base_bpp, pipe_config->pipe_bpp, pipe_config->dither); 5857 5858 return 0; 5859 } 5860 5861 static int 5862 intel_modeset_pipe_config_late(struct intel_crtc_state *crtc_state) 5863 { 5864 struct intel_atomic_state *state = 5865 to_intel_atomic_state(crtc_state->uapi.state); 5866 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 5867 struct drm_connector_state *conn_state; 5868 struct drm_connector *connector; 5869 int i; 5870 5871 intel_bigjoiner_adjust_pipe_src(crtc_state); 5872 5873 for_each_new_connector_in_state(&state->base, connector, 5874 conn_state, i) { 5875 struct intel_encoder *encoder = 5876 to_intel_encoder(conn_state->best_encoder); 5877 int ret; 5878 5879 if (conn_state->crtc != &crtc->base || 5880 !encoder->compute_config_late) 5881 continue; 5882 5883 ret = encoder->compute_config_late(encoder, crtc_state, 5884 conn_state); 5885 if (ret) 5886 return ret; 5887 } 5888 5889 return 0; 5890 } 5891 5892 bool intel_fuzzy_clock_check(int clock1, int clock2) 5893 { 5894 int diff; 5895 5896 if (clock1 == clock2) 5897 return true; 5898 5899 if (!clock1 || !clock2) 5900 return false; 5901 5902 diff = abs(clock1 - clock2); 5903 5904 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) 5905 return true; 5906 5907 return false; 5908 } 5909 5910 static bool 5911 intel_compare_m_n(unsigned int m, unsigned int n, 5912 unsigned int m2, unsigned int n2, 5913 bool exact) 5914 { 5915 if (m == m2 && n == n2) 5916 return true; 5917 5918 if (exact || !m || !n || !m2 || !n2) 5919 return false; 5920 5921 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); 5922 5923 if (n > n2) { 5924 while (n > n2) { 5925 m2 <<= 1; 5926 n2 <<= 1; 5927 } 5928 } else if (n < n2) { 5929 while (n < n2) { 5930 m <<= 1; 5931 n <<= 1; 5932 } 5933 } 5934 5935 if (n != n2) 5936 return false; 5937 5938 return intel_fuzzy_clock_check(m, m2); 5939 } 5940 5941 static bool 5942 intel_compare_link_m_n(const struct intel_link_m_n *m_n, 5943 const struct intel_link_m_n *m2_n2, 5944 bool exact) 5945 { 5946 return m_n->tu == m2_n2->tu && 5947 intel_compare_m_n(m_n->data_m, m_n->data_n, 5948 m2_n2->data_m, m2_n2->data_n, exact) && 5949 intel_compare_m_n(m_n->link_m, m_n->link_n, 5950 m2_n2->link_m, m2_n2->link_n, exact); 5951 } 5952 5953 static bool 5954 intel_compare_infoframe(const union hdmi_infoframe *a, 5955 const union hdmi_infoframe *b) 5956 { 5957 return memcmp(a, b, sizeof(*a)) == 0; 5958 } 5959 5960 static bool 5961 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a, 5962 const struct drm_dp_vsc_sdp *b) 5963 { 5964 return memcmp(a, b, sizeof(*a)) == 0; 5965 } 5966 5967 static void 5968 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv, 5969 bool fastset, const char *name, 5970 const union hdmi_infoframe *a, 5971 const union hdmi_infoframe *b) 5972 { 5973 if (fastset) { 5974 if (!drm_debug_enabled(DRM_UT_KMS)) 5975 return; 5976 5977 drm_dbg_kms(&dev_priv->drm, 5978 "fastset mismatch in %s infoframe\n", name); 5979 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 5980 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a); 5981 drm_dbg_kms(&dev_priv->drm, "found:\n"); 5982 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b); 5983 } else { 5984 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name); 5985 drm_err(&dev_priv->drm, "expected:\n"); 5986 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a); 5987 drm_err(&dev_priv->drm, "found:\n"); 5988 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b); 5989 } 5990 } 5991 5992 static void 5993 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv, 5994 bool fastset, const char *name, 5995 const struct drm_dp_vsc_sdp *a, 5996 const struct drm_dp_vsc_sdp *b) 5997 { 5998 if (fastset) { 5999 if (!drm_debug_enabled(DRM_UT_KMS)) 6000 return; 6001 6002 drm_dbg_kms(&dev_priv->drm, 6003 "fastset mismatch in %s dp sdp\n", name); 6004 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 6005 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a); 6006 drm_dbg_kms(&dev_priv->drm, "found:\n"); 6007 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b); 6008 } else { 6009 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name); 6010 drm_err(&dev_priv->drm, "expected:\n"); 6011 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a); 6012 drm_err(&dev_priv->drm, "found:\n"); 6013 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b); 6014 } 6015 } 6016 6017 static void __printf(4, 5) 6018 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc, 6019 const char *name, const char *format, ...) 6020 { 6021 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 6022 struct va_format vaf; 6023 va_list args; 6024 6025 va_start(args, format); 6026 vaf.fmt = format; 6027 vaf.va = &args; 6028 6029 if (fastset) 6030 drm_dbg_kms(&i915->drm, 6031 "[CRTC:%d:%s] fastset mismatch in %s %pV\n", 6032 crtc->base.base.id, crtc->base.name, name, &vaf); 6033 else 6034 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n", 6035 crtc->base.base.id, crtc->base.name, name, &vaf); 6036 6037 va_end(args); 6038 } 6039 6040 static bool fastboot_enabled(struct drm_i915_private *dev_priv) 6041 { 6042 if (dev_priv->params.fastboot != -1) 6043 return dev_priv->params.fastboot; 6044 6045 /* Enable fastboot by default on Skylake and newer */ 6046 if (DISPLAY_VER(dev_priv) >= 9) 6047 return true; 6048 6049 /* Enable fastboot by default on VLV and CHV */ 6050 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 6051 return true; 6052 6053 /* Disabled by default on all others */ 6054 return false; 6055 } 6056 6057 static bool 6058 intel_pipe_config_compare(const struct intel_crtc_state *current_config, 6059 const struct intel_crtc_state *pipe_config, 6060 bool fastset) 6061 { 6062 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev); 6063 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 6064 bool ret = true; 6065 u32 bp_gamma = 0; 6066 bool fixup_inherited = fastset && 6067 current_config->inherited && !pipe_config->inherited; 6068 6069 if (fixup_inherited && !fastboot_enabled(dev_priv)) { 6070 drm_dbg_kms(&dev_priv->drm, 6071 "initial modeset and fastboot not set\n"); 6072 ret = false; 6073 } 6074 6075 #define PIPE_CONF_CHECK_X(name) do { \ 6076 if (current_config->name != pipe_config->name) { \ 6077 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6078 "(expected 0x%08x, found 0x%08x)", \ 6079 current_config->name, \ 6080 pipe_config->name); \ 6081 ret = false; \ 6082 } \ 6083 } while (0) 6084 6085 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \ 6086 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \ 6087 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6088 "(expected 0x%08x, found 0x%08x)", \ 6089 current_config->name & (mask), \ 6090 pipe_config->name & (mask)); \ 6091 ret = false; \ 6092 } \ 6093 } while (0) 6094 6095 #define PIPE_CONF_CHECK_I(name) do { \ 6096 if (current_config->name != pipe_config->name) { \ 6097 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6098 "(expected %i, found %i)", \ 6099 current_config->name, \ 6100 pipe_config->name); \ 6101 ret = false; \ 6102 } \ 6103 } while (0) 6104 6105 #define PIPE_CONF_CHECK_BOOL(name) do { \ 6106 if (current_config->name != pipe_config->name) { \ 6107 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6108 "(expected %s, found %s)", \ 6109 str_yes_no(current_config->name), \ 6110 str_yes_no(pipe_config->name)); \ 6111 ret = false; \ 6112 } \ 6113 } while (0) 6114 6115 /* 6116 * Checks state where we only read out the enabling, but not the entire 6117 * state itself (like full infoframes or ELD for audio). These states 6118 * require a full modeset on bootup to fix up. 6119 */ 6120 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \ 6121 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \ 6122 PIPE_CONF_CHECK_BOOL(name); \ 6123 } else { \ 6124 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6125 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \ 6126 str_yes_no(current_config->name), \ 6127 str_yes_no(pipe_config->name)); \ 6128 ret = false; \ 6129 } \ 6130 } while (0) 6131 6132 #define PIPE_CONF_CHECK_P(name) do { \ 6133 if (current_config->name != pipe_config->name) { \ 6134 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6135 "(expected %p, found %p)", \ 6136 current_config->name, \ 6137 pipe_config->name); \ 6138 ret = false; \ 6139 } \ 6140 } while (0) 6141 6142 #define PIPE_CONF_CHECK_M_N(name) do { \ 6143 if (!intel_compare_link_m_n(¤t_config->name, \ 6144 &pipe_config->name,\ 6145 !fastset)) { \ 6146 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6147 "(expected tu %i data %i/%i link %i/%i, " \ 6148 "found tu %i, data %i/%i link %i/%i)", \ 6149 current_config->name.tu, \ 6150 current_config->name.data_m, \ 6151 current_config->name.data_n, \ 6152 current_config->name.link_m, \ 6153 current_config->name.link_n, \ 6154 pipe_config->name.tu, \ 6155 pipe_config->name.data_m, \ 6156 pipe_config->name.data_n, \ 6157 pipe_config->name.link_m, \ 6158 pipe_config->name.link_n); \ 6159 ret = false; \ 6160 } \ 6161 } while (0) 6162 6163 /* This is required for BDW+ where there is only one set of registers for 6164 * switching between high and low RR. 6165 * This macro can be used whenever a comparison has to be made between one 6166 * hw state and multiple sw state variables. 6167 */ 6168 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \ 6169 if (!intel_compare_link_m_n(¤t_config->name, \ 6170 &pipe_config->name, !fastset) && \ 6171 !intel_compare_link_m_n(¤t_config->alt_name, \ 6172 &pipe_config->name, !fastset)) { \ 6173 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6174 "(expected tu %i data %i/%i link %i/%i, " \ 6175 "or tu %i data %i/%i link %i/%i, " \ 6176 "found tu %i, data %i/%i link %i/%i)", \ 6177 current_config->name.tu, \ 6178 current_config->name.data_m, \ 6179 current_config->name.data_n, \ 6180 current_config->name.link_m, \ 6181 current_config->name.link_n, \ 6182 current_config->alt_name.tu, \ 6183 current_config->alt_name.data_m, \ 6184 current_config->alt_name.data_n, \ 6185 current_config->alt_name.link_m, \ 6186 current_config->alt_name.link_n, \ 6187 pipe_config->name.tu, \ 6188 pipe_config->name.data_m, \ 6189 pipe_config->name.data_n, \ 6190 pipe_config->name.link_m, \ 6191 pipe_config->name.link_n); \ 6192 ret = false; \ 6193 } \ 6194 } while (0) 6195 6196 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \ 6197 if ((current_config->name ^ pipe_config->name) & (mask)) { \ 6198 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6199 "(%x) (expected %i, found %i)", \ 6200 (mask), \ 6201 current_config->name & (mask), \ 6202 pipe_config->name & (mask)); \ 6203 ret = false; \ 6204 } \ 6205 } while (0) 6206 6207 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \ 6208 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ 6209 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6210 "(expected %i, found %i)", \ 6211 current_config->name, \ 6212 pipe_config->name); \ 6213 ret = false; \ 6214 } \ 6215 } while (0) 6216 6217 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \ 6218 if (!intel_compare_infoframe(¤t_config->infoframes.name, \ 6219 &pipe_config->infoframes.name)) { \ 6220 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \ 6221 ¤t_config->infoframes.name, \ 6222 &pipe_config->infoframes.name); \ 6223 ret = false; \ 6224 } \ 6225 } while (0) 6226 6227 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \ 6228 if (!current_config->has_psr && !pipe_config->has_psr && \ 6229 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \ 6230 &pipe_config->infoframes.name)) { \ 6231 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \ 6232 ¤t_config->infoframes.name, \ 6233 &pipe_config->infoframes.name); \ 6234 ret = false; \ 6235 } \ 6236 } while (0) 6237 6238 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \ 6239 if (current_config->name1 != pipe_config->name1) { \ 6240 pipe_config_mismatch(fastset, crtc, __stringify(name1), \ 6241 "(expected %i, found %i, won't compare lut values)", \ 6242 current_config->name1, \ 6243 pipe_config->name1); \ 6244 ret = false;\ 6245 } else { \ 6246 if (!intel_color_lut_equal(current_config->name2, \ 6247 pipe_config->name2, pipe_config->name1, \ 6248 bit_precision)) { \ 6249 pipe_config_mismatch(fastset, crtc, __stringify(name2), \ 6250 "hw_state doesn't match sw_state"); \ 6251 ret = false; \ 6252 } \ 6253 } \ 6254 } while (0) 6255 6256 #define PIPE_CONF_QUIRK(quirk) \ 6257 ((current_config->quirks | pipe_config->quirks) & (quirk)) 6258 6259 PIPE_CONF_CHECK_I(cpu_transcoder); 6260 6261 PIPE_CONF_CHECK_BOOL(has_pch_encoder); 6262 PIPE_CONF_CHECK_I(fdi_lanes); 6263 PIPE_CONF_CHECK_M_N(fdi_m_n); 6264 6265 PIPE_CONF_CHECK_I(lane_count); 6266 PIPE_CONF_CHECK_X(lane_lat_optim_mask); 6267 6268 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) { 6269 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); 6270 } else { 6271 PIPE_CONF_CHECK_M_N(dp_m_n); 6272 PIPE_CONF_CHECK_M_N(dp_m2_n2); 6273 } 6274 6275 PIPE_CONF_CHECK_X(output_types); 6276 6277 PIPE_CONF_CHECK_I(framestart_delay); 6278 PIPE_CONF_CHECK_I(msa_timing_delay); 6279 6280 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay); 6281 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_htotal); 6282 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_start); 6283 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_end); 6284 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_start); 6285 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_end); 6286 6287 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vdisplay); 6288 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vtotal); 6289 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_start); 6290 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_end); 6291 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_start); 6292 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_end); 6293 6294 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay); 6295 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal); 6296 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start); 6297 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end); 6298 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start); 6299 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end); 6300 6301 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay); 6302 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal); 6303 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start); 6304 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end); 6305 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start); 6306 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end); 6307 6308 PIPE_CONF_CHECK_I(pixel_multiplier); 6309 6310 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6311 DRM_MODE_FLAG_INTERLACE); 6312 6313 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { 6314 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6315 DRM_MODE_FLAG_PHSYNC); 6316 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6317 DRM_MODE_FLAG_NHSYNC); 6318 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6319 DRM_MODE_FLAG_PVSYNC); 6320 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6321 DRM_MODE_FLAG_NVSYNC); 6322 } 6323 6324 PIPE_CONF_CHECK_I(output_format); 6325 PIPE_CONF_CHECK_BOOL(has_hdmi_sink); 6326 if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || 6327 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 6328 PIPE_CONF_CHECK_BOOL(limited_color_range); 6329 6330 PIPE_CONF_CHECK_BOOL(hdmi_scrambling); 6331 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio); 6332 PIPE_CONF_CHECK_BOOL(has_infoframe); 6333 PIPE_CONF_CHECK_BOOL(fec_enable); 6334 6335 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio); 6336 6337 PIPE_CONF_CHECK_X(gmch_pfit.control); 6338 /* pfit ratios are autocomputed by the hw on gen4+ */ 6339 if (DISPLAY_VER(dev_priv) < 4) 6340 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); 6341 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); 6342 6343 /* 6344 * Changing the EDP transcoder input mux 6345 * (A_ONOFF vs. A_ON) requires a full modeset. 6346 */ 6347 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru); 6348 6349 if (!fastset) { 6350 PIPE_CONF_CHECK_I(pipe_src.x1); 6351 PIPE_CONF_CHECK_I(pipe_src.y1); 6352 PIPE_CONF_CHECK_I(pipe_src.x2); 6353 PIPE_CONF_CHECK_I(pipe_src.y2); 6354 6355 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled); 6356 if (current_config->pch_pfit.enabled) { 6357 PIPE_CONF_CHECK_I(pch_pfit.dst.x1); 6358 PIPE_CONF_CHECK_I(pch_pfit.dst.y1); 6359 PIPE_CONF_CHECK_I(pch_pfit.dst.x2); 6360 PIPE_CONF_CHECK_I(pch_pfit.dst.y2); 6361 } 6362 6363 PIPE_CONF_CHECK_I(scaler_state.scaler_id); 6364 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate); 6365 6366 PIPE_CONF_CHECK_X(gamma_mode); 6367 if (IS_CHERRYVIEW(dev_priv)) 6368 PIPE_CONF_CHECK_X(cgm_mode); 6369 else 6370 PIPE_CONF_CHECK_X(csc_mode); 6371 PIPE_CONF_CHECK_BOOL(gamma_enable); 6372 PIPE_CONF_CHECK_BOOL(csc_enable); 6373 6374 PIPE_CONF_CHECK_I(linetime); 6375 PIPE_CONF_CHECK_I(ips_linetime); 6376 6377 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config); 6378 if (bp_gamma) 6379 PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma); 6380 6381 if (current_config->active_planes) { 6382 PIPE_CONF_CHECK_BOOL(has_psr); 6383 PIPE_CONF_CHECK_BOOL(has_psr2); 6384 PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); 6385 PIPE_CONF_CHECK_I(dc3co_exitline); 6386 } 6387 } 6388 6389 PIPE_CONF_CHECK_BOOL(double_wide); 6390 6391 if (dev_priv->dpll.mgr) { 6392 PIPE_CONF_CHECK_P(shared_dpll); 6393 6394 PIPE_CONF_CHECK_X(dpll_hw_state.dpll); 6395 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); 6396 PIPE_CONF_CHECK_X(dpll_hw_state.fp0); 6397 PIPE_CONF_CHECK_X(dpll_hw_state.fp1); 6398 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); 6399 PIPE_CONF_CHECK_X(dpll_hw_state.spll); 6400 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); 6401 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); 6402 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); 6403 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); 6404 PIPE_CONF_CHECK_X(dpll_hw_state.div0); 6405 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); 6406 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); 6407 PIPE_CONF_CHECK_X(dpll_hw_state.pll0); 6408 PIPE_CONF_CHECK_X(dpll_hw_state.pll1); 6409 PIPE_CONF_CHECK_X(dpll_hw_state.pll2); 6410 PIPE_CONF_CHECK_X(dpll_hw_state.pll3); 6411 PIPE_CONF_CHECK_X(dpll_hw_state.pll6); 6412 PIPE_CONF_CHECK_X(dpll_hw_state.pll8); 6413 PIPE_CONF_CHECK_X(dpll_hw_state.pll9); 6414 PIPE_CONF_CHECK_X(dpll_hw_state.pll10); 6415 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); 6416 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl); 6417 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1); 6418 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl); 6419 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0); 6420 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1); 6421 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf); 6422 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock); 6423 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc); 6424 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias); 6425 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias); 6426 } 6427 6428 PIPE_CONF_CHECK_X(dsi_pll.ctrl); 6429 PIPE_CONF_CHECK_X(dsi_pll.div); 6430 6431 if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5) 6432 PIPE_CONF_CHECK_I(pipe_bpp); 6433 6434 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock); 6435 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock); 6436 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); 6437 6438 PIPE_CONF_CHECK_I(min_voltage_level); 6439 6440 if (current_config->has_psr || pipe_config->has_psr) 6441 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable, 6442 ~intel_hdmi_infoframe_enable(DP_SDP_VSC)); 6443 else 6444 PIPE_CONF_CHECK_X(infoframes.enable); 6445 6446 PIPE_CONF_CHECK_X(infoframes.gcp); 6447 PIPE_CONF_CHECK_INFOFRAME(avi); 6448 PIPE_CONF_CHECK_INFOFRAME(spd); 6449 PIPE_CONF_CHECK_INFOFRAME(hdmi); 6450 PIPE_CONF_CHECK_INFOFRAME(drm); 6451 PIPE_CONF_CHECK_DP_VSC_SDP(vsc); 6452 6453 PIPE_CONF_CHECK_X(sync_mode_slaves_mask); 6454 PIPE_CONF_CHECK_I(master_transcoder); 6455 PIPE_CONF_CHECK_X(bigjoiner_pipes); 6456 6457 PIPE_CONF_CHECK_I(dsc.compression_enable); 6458 PIPE_CONF_CHECK_I(dsc.dsc_split); 6459 PIPE_CONF_CHECK_I(dsc.compressed_bpp); 6460 6461 PIPE_CONF_CHECK_BOOL(splitter.enable); 6462 PIPE_CONF_CHECK_I(splitter.link_count); 6463 PIPE_CONF_CHECK_I(splitter.pixel_overlap); 6464 6465 PIPE_CONF_CHECK_I(mst_master_transcoder); 6466 6467 PIPE_CONF_CHECK_BOOL(vrr.enable); 6468 PIPE_CONF_CHECK_I(vrr.vmin); 6469 PIPE_CONF_CHECK_I(vrr.vmax); 6470 PIPE_CONF_CHECK_I(vrr.flipline); 6471 PIPE_CONF_CHECK_I(vrr.pipeline_full); 6472 PIPE_CONF_CHECK_I(vrr.guardband); 6473 6474 #undef PIPE_CONF_CHECK_X 6475 #undef PIPE_CONF_CHECK_I 6476 #undef PIPE_CONF_CHECK_BOOL 6477 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE 6478 #undef PIPE_CONF_CHECK_P 6479 #undef PIPE_CONF_CHECK_FLAGS 6480 #undef PIPE_CONF_CHECK_CLOCK_FUZZY 6481 #undef PIPE_CONF_CHECK_COLOR_LUT 6482 #undef PIPE_CONF_QUIRK 6483 6484 return ret; 6485 } 6486 6487 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, 6488 const struct intel_crtc_state *pipe_config) 6489 { 6490 if (pipe_config->has_pch_encoder) { 6491 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), 6492 &pipe_config->fdi_m_n); 6493 int dotclock = pipe_config->hw.adjusted_mode.crtc_clock; 6494 6495 /* 6496 * FDI already provided one idea for the dotclock. 6497 * Yell if the encoder disagrees. 6498 */ 6499 drm_WARN(&dev_priv->drm, 6500 !intel_fuzzy_clock_check(fdi_dotclock, dotclock), 6501 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", 6502 fdi_dotclock, dotclock); 6503 } 6504 } 6505 6506 static void verify_wm_state(struct intel_crtc *crtc, 6507 struct intel_crtc_state *new_crtc_state) 6508 { 6509 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6510 struct skl_hw_state { 6511 struct skl_ddb_entry ddb[I915_MAX_PLANES]; 6512 struct skl_ddb_entry ddb_y[I915_MAX_PLANES]; 6513 struct skl_pipe_wm wm; 6514 } *hw; 6515 const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal; 6516 int level, max_level = ilk_wm_max_level(dev_priv); 6517 struct intel_plane *plane; 6518 u8 hw_enabled_slices; 6519 6520 if (DISPLAY_VER(dev_priv) < 9 || !new_crtc_state->hw.active) 6521 return; 6522 6523 hw = kzalloc(sizeof(*hw), GFP_KERNEL); 6524 if (!hw) 6525 return; 6526 6527 skl_pipe_wm_get_hw_state(crtc, &hw->wm); 6528 6529 skl_pipe_ddb_get_hw_state(crtc, hw->ddb, hw->ddb_y); 6530 6531 hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv); 6532 6533 if (DISPLAY_VER(dev_priv) >= 11 && 6534 hw_enabled_slices != dev_priv->dbuf.enabled_slices) 6535 drm_err(&dev_priv->drm, 6536 "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n", 6537 dev_priv->dbuf.enabled_slices, 6538 hw_enabled_slices); 6539 6540 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 6541 const struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; 6542 const struct skl_wm_level *hw_wm_level, *sw_wm_level; 6543 6544 /* Watermarks */ 6545 for (level = 0; level <= max_level; level++) { 6546 hw_wm_level = &hw->wm.planes[plane->id].wm[level]; 6547 sw_wm_level = skl_plane_wm_level(sw_wm, plane->id, level); 6548 6549 if (skl_wm_level_equals(hw_wm_level, sw_wm_level)) 6550 continue; 6551 6552 drm_err(&dev_priv->drm, 6553 "[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 6554 plane->base.base.id, plane->base.name, level, 6555 sw_wm_level->enable, 6556 sw_wm_level->blocks, 6557 sw_wm_level->lines, 6558 hw_wm_level->enable, 6559 hw_wm_level->blocks, 6560 hw_wm_level->lines); 6561 } 6562 6563 hw_wm_level = &hw->wm.planes[plane->id].trans_wm; 6564 sw_wm_level = skl_plane_trans_wm(sw_wm, plane->id); 6565 6566 if (!skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 6567 drm_err(&dev_priv->drm, 6568 "[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 6569 plane->base.base.id, plane->base.name, 6570 sw_wm_level->enable, 6571 sw_wm_level->blocks, 6572 sw_wm_level->lines, 6573 hw_wm_level->enable, 6574 hw_wm_level->blocks, 6575 hw_wm_level->lines); 6576 } 6577 6578 hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0; 6579 sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0; 6580 6581 if (HAS_HW_SAGV_WM(dev_priv) && 6582 !skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 6583 drm_err(&dev_priv->drm, 6584 "[PLANE:%d:%s] mismatch in SAGV WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 6585 plane->base.base.id, plane->base.name, 6586 sw_wm_level->enable, 6587 sw_wm_level->blocks, 6588 sw_wm_level->lines, 6589 hw_wm_level->enable, 6590 hw_wm_level->blocks, 6591 hw_wm_level->lines); 6592 } 6593 6594 hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm; 6595 sw_wm_level = &sw_wm->planes[plane->id].sagv.trans_wm; 6596 6597 if (HAS_HW_SAGV_WM(dev_priv) && 6598 !skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 6599 drm_err(&dev_priv->drm, 6600 "[PLANE:%d:%s] mismatch in SAGV trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 6601 plane->base.base.id, plane->base.name, 6602 sw_wm_level->enable, 6603 sw_wm_level->blocks, 6604 sw_wm_level->lines, 6605 hw_wm_level->enable, 6606 hw_wm_level->blocks, 6607 hw_wm_level->lines); 6608 } 6609 6610 /* DDB */ 6611 hw_ddb_entry = &hw->ddb[PLANE_CURSOR]; 6612 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[PLANE_CURSOR]; 6613 6614 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { 6615 drm_err(&dev_priv->drm, 6616 "[PLANE:%d:%s] mismatch in DDB (expected (%u,%u), found (%u,%u))\n", 6617 plane->base.base.id, plane->base.name, 6618 sw_ddb_entry->start, sw_ddb_entry->end, 6619 hw_ddb_entry->start, hw_ddb_entry->end); 6620 } 6621 } 6622 6623 kfree(hw); 6624 } 6625 6626 static void 6627 verify_connector_state(struct intel_atomic_state *state, 6628 struct intel_crtc *crtc) 6629 { 6630 struct drm_connector *connector; 6631 struct drm_connector_state *new_conn_state; 6632 int i; 6633 6634 for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) { 6635 struct drm_encoder *encoder = connector->encoder; 6636 struct intel_crtc_state *crtc_state = NULL; 6637 6638 if (new_conn_state->crtc != &crtc->base) 6639 continue; 6640 6641 if (crtc) 6642 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6643 6644 intel_connector_verify_state(crtc_state, new_conn_state); 6645 6646 I915_STATE_WARN(new_conn_state->best_encoder != encoder, 6647 "connector's atomic encoder doesn't match legacy encoder\n"); 6648 } 6649 } 6650 6651 static void 6652 verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state) 6653 { 6654 struct intel_encoder *encoder; 6655 struct drm_connector *connector; 6656 struct drm_connector_state *old_conn_state, *new_conn_state; 6657 int i; 6658 6659 for_each_intel_encoder(&dev_priv->drm, encoder) { 6660 bool enabled = false, found = false; 6661 enum pipe pipe; 6662 6663 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n", 6664 encoder->base.base.id, 6665 encoder->base.name); 6666 6667 for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state, 6668 new_conn_state, i) { 6669 if (old_conn_state->best_encoder == &encoder->base) 6670 found = true; 6671 6672 if (new_conn_state->best_encoder != &encoder->base) 6673 continue; 6674 found = enabled = true; 6675 6676 I915_STATE_WARN(new_conn_state->crtc != 6677 encoder->base.crtc, 6678 "connector's crtc doesn't match encoder crtc\n"); 6679 } 6680 6681 if (!found) 6682 continue; 6683 6684 I915_STATE_WARN(!!encoder->base.crtc != enabled, 6685 "encoder's enabled state mismatch " 6686 "(expected %i, found %i)\n", 6687 !!encoder->base.crtc, enabled); 6688 6689 if (!encoder->base.crtc) { 6690 bool active; 6691 6692 active = encoder->get_hw_state(encoder, &pipe); 6693 I915_STATE_WARN(active, 6694 "encoder detached but still enabled on pipe %c.\n", 6695 pipe_name(pipe)); 6696 } 6697 } 6698 } 6699 6700 static void 6701 verify_crtc_state(struct intel_crtc *crtc, 6702 struct intel_crtc_state *old_crtc_state, 6703 struct intel_crtc_state *new_crtc_state) 6704 { 6705 struct drm_device *dev = crtc->base.dev; 6706 struct drm_i915_private *dev_priv = to_i915(dev); 6707 struct intel_encoder *encoder; 6708 struct intel_crtc_state *pipe_config = old_crtc_state; 6709 struct drm_atomic_state *state = old_crtc_state->uapi.state; 6710 struct intel_crtc *master_crtc; 6711 6712 __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi); 6713 intel_crtc_free_hw_state(old_crtc_state); 6714 intel_crtc_state_reset(old_crtc_state, crtc); 6715 old_crtc_state->uapi.state = state; 6716 6717 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id, 6718 crtc->base.name); 6719 6720 pipe_config->hw.enable = new_crtc_state->hw.enable; 6721 6722 intel_crtc_get_pipe_config(pipe_config); 6723 6724 /* we keep both pipes enabled on 830 */ 6725 if (IS_I830(dev_priv) && pipe_config->hw.active) 6726 pipe_config->hw.active = new_crtc_state->hw.active; 6727 6728 I915_STATE_WARN(new_crtc_state->hw.active != pipe_config->hw.active, 6729 "crtc active state doesn't match with hw state " 6730 "(expected %i, found %i)\n", 6731 new_crtc_state->hw.active, pipe_config->hw.active); 6732 6733 I915_STATE_WARN(crtc->active != new_crtc_state->hw.active, 6734 "transitional active state does not match atomic hw state " 6735 "(expected %i, found %i)\n", 6736 new_crtc_state->hw.active, crtc->active); 6737 6738 master_crtc = intel_master_crtc(new_crtc_state); 6739 6740 for_each_encoder_on_crtc(dev, &master_crtc->base, encoder) { 6741 enum pipe pipe; 6742 bool active; 6743 6744 active = encoder->get_hw_state(encoder, &pipe); 6745 I915_STATE_WARN(active != new_crtc_state->hw.active, 6746 "[ENCODER:%i] active %i with crtc active %i\n", 6747 encoder->base.base.id, active, 6748 new_crtc_state->hw.active); 6749 6750 I915_STATE_WARN(active && master_crtc->pipe != pipe, 6751 "Encoder connected to wrong pipe %c\n", 6752 pipe_name(pipe)); 6753 6754 if (active) 6755 intel_encoder_get_config(encoder, pipe_config); 6756 } 6757 6758 if (!new_crtc_state->hw.active) 6759 return; 6760 6761 intel_pipe_config_sanity_check(dev_priv, pipe_config); 6762 6763 if (!intel_pipe_config_compare(new_crtc_state, 6764 pipe_config, false)) { 6765 I915_STATE_WARN(1, "pipe state doesn't match!\n"); 6766 intel_dump_pipe_config(pipe_config, NULL, "[hw state]"); 6767 intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]"); 6768 } 6769 } 6770 6771 static void 6772 intel_verify_planes(struct intel_atomic_state *state) 6773 { 6774 struct intel_plane *plane; 6775 const struct intel_plane_state *plane_state; 6776 int i; 6777 6778 for_each_new_intel_plane_in_state(state, plane, 6779 plane_state, i) 6780 assert_plane(plane, plane_state->planar_slave || 6781 plane_state->uapi.visible); 6782 } 6783 6784 static void 6785 verify_single_dpll_state(struct drm_i915_private *dev_priv, 6786 struct intel_shared_dpll *pll, 6787 struct intel_crtc *crtc, 6788 struct intel_crtc_state *new_crtc_state) 6789 { 6790 struct intel_dpll_hw_state dpll_hw_state; 6791 u8 pipe_mask; 6792 bool active; 6793 6794 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); 6795 6796 drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name); 6797 6798 active = intel_dpll_get_hw_state(dev_priv, pll, &dpll_hw_state); 6799 6800 if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) { 6801 I915_STATE_WARN(!pll->on && pll->active_mask, 6802 "pll in active use but not on in sw tracking\n"); 6803 I915_STATE_WARN(pll->on && !pll->active_mask, 6804 "pll is on but not used by any active pipe\n"); 6805 I915_STATE_WARN(pll->on != active, 6806 "pll on state mismatch (expected %i, found %i)\n", 6807 pll->on, active); 6808 } 6809 6810 if (!crtc) { 6811 I915_STATE_WARN(pll->active_mask & ~pll->state.pipe_mask, 6812 "more active pll users than references: 0x%x vs 0x%x\n", 6813 pll->active_mask, pll->state.pipe_mask); 6814 6815 return; 6816 } 6817 6818 pipe_mask = BIT(crtc->pipe); 6819 6820 if (new_crtc_state->hw.active) 6821 I915_STATE_WARN(!(pll->active_mask & pipe_mask), 6822 "pll active mismatch (expected pipe %c in active mask 0x%x)\n", 6823 pipe_name(crtc->pipe), pll->active_mask); 6824 else 6825 I915_STATE_WARN(pll->active_mask & pipe_mask, 6826 "pll active mismatch (didn't expect pipe %c in active mask 0x%x)\n", 6827 pipe_name(crtc->pipe), pll->active_mask); 6828 6829 I915_STATE_WARN(!(pll->state.pipe_mask & pipe_mask), 6830 "pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n", 6831 pipe_mask, pll->state.pipe_mask); 6832 6833 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state, 6834 &dpll_hw_state, 6835 sizeof(dpll_hw_state)), 6836 "pll hw state mismatch\n"); 6837 } 6838 6839 static void 6840 verify_shared_dpll_state(struct intel_crtc *crtc, 6841 struct intel_crtc_state *old_crtc_state, 6842 struct intel_crtc_state *new_crtc_state) 6843 { 6844 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6845 6846 if (new_crtc_state->shared_dpll) 6847 verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state); 6848 6849 if (old_crtc_state->shared_dpll && 6850 old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) { 6851 u8 pipe_mask = BIT(crtc->pipe); 6852 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll; 6853 6854 I915_STATE_WARN(pll->active_mask & pipe_mask, 6855 "pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n", 6856 pipe_name(crtc->pipe), pll->active_mask); 6857 I915_STATE_WARN(pll->state.pipe_mask & pipe_mask, 6858 "pll enabled crtcs mismatch (found %x in enabled mask (0x%x))\n", 6859 pipe_name(crtc->pipe), pll->state.pipe_mask); 6860 } 6861 } 6862 6863 static void 6864 verify_mpllb_state(struct intel_atomic_state *state, 6865 struct intel_crtc_state *new_crtc_state) 6866 { 6867 struct drm_i915_private *i915 = to_i915(state->base.dev); 6868 struct intel_mpllb_state mpllb_hw_state = { 0 }; 6869 struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->mpllb_state; 6870 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 6871 struct intel_encoder *encoder; 6872 6873 if (!IS_DG2(i915)) 6874 return; 6875 6876 if (!new_crtc_state->hw.active) 6877 return; 6878 6879 encoder = intel_get_crtc_new_encoder(state, new_crtc_state); 6880 intel_mpllb_readout_hw_state(encoder, &mpllb_hw_state); 6881 6882 #define MPLLB_CHECK(name) do { \ 6883 if (mpllb_sw_state->name != mpllb_hw_state.name) { \ 6884 pipe_config_mismatch(false, crtc, "MPLLB:" __stringify(name), \ 6885 "(expected 0x%08x, found 0x%08x)", \ 6886 mpllb_sw_state->name, \ 6887 mpllb_hw_state.name); \ 6888 } \ 6889 } while (0) 6890 6891 MPLLB_CHECK(mpllb_cp); 6892 MPLLB_CHECK(mpllb_div); 6893 MPLLB_CHECK(mpllb_div2); 6894 MPLLB_CHECK(mpllb_fracn1); 6895 MPLLB_CHECK(mpllb_fracn2); 6896 MPLLB_CHECK(mpllb_sscen); 6897 MPLLB_CHECK(mpllb_sscstep); 6898 6899 /* 6900 * ref_control is handled by the hardware/firemware and never 6901 * programmed by the software, but the proper values are supplied 6902 * in the bspec for verification purposes. 6903 */ 6904 MPLLB_CHECK(ref_control); 6905 6906 #undef MPLLB_CHECK 6907 } 6908 6909 static void 6910 intel_modeset_verify_crtc(struct intel_crtc *crtc, 6911 struct intel_atomic_state *state, 6912 struct intel_crtc_state *old_crtc_state, 6913 struct intel_crtc_state *new_crtc_state) 6914 { 6915 if (!intel_crtc_needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe) 6916 return; 6917 6918 verify_wm_state(crtc, new_crtc_state); 6919 verify_connector_state(state, crtc); 6920 verify_crtc_state(crtc, old_crtc_state, new_crtc_state); 6921 verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state); 6922 verify_mpllb_state(state, new_crtc_state); 6923 } 6924 6925 static void 6926 verify_disabled_dpll_state(struct drm_i915_private *dev_priv) 6927 { 6928 int i; 6929 6930 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) 6931 verify_single_dpll_state(dev_priv, 6932 &dev_priv->dpll.shared_dplls[i], 6933 NULL, NULL); 6934 } 6935 6936 static void 6937 intel_modeset_verify_disabled(struct drm_i915_private *dev_priv, 6938 struct intel_atomic_state *state) 6939 { 6940 verify_encoder_state(dev_priv, state); 6941 verify_connector_state(state, NULL); 6942 verify_disabled_dpll_state(dev_priv); 6943 } 6944 6945 int intel_modeset_all_pipes(struct intel_atomic_state *state) 6946 { 6947 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6948 struct intel_crtc *crtc; 6949 6950 /* 6951 * Add all pipes to the state, and force 6952 * a modeset on all the active ones. 6953 */ 6954 for_each_intel_crtc(&dev_priv->drm, crtc) { 6955 struct intel_crtc_state *crtc_state; 6956 int ret; 6957 6958 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6959 if (IS_ERR(crtc_state)) 6960 return PTR_ERR(crtc_state); 6961 6962 if (!crtc_state->hw.active || 6963 drm_atomic_crtc_needs_modeset(&crtc_state->uapi)) 6964 continue; 6965 6966 crtc_state->uapi.mode_changed = true; 6967 6968 ret = drm_atomic_add_affected_connectors(&state->base, 6969 &crtc->base); 6970 if (ret) 6971 return ret; 6972 6973 ret = intel_atomic_add_affected_planes(state, crtc); 6974 if (ret) 6975 return ret; 6976 6977 crtc_state->update_planes |= crtc_state->active_planes; 6978 } 6979 6980 return 0; 6981 } 6982 6983 static void 6984 intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state) 6985 { 6986 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 6987 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6988 struct drm_display_mode adjusted_mode = 6989 crtc_state->hw.adjusted_mode; 6990 6991 if (crtc_state->vrr.enable) { 6992 adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax; 6993 adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax; 6994 adjusted_mode.crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state); 6995 crtc->vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state); 6996 } 6997 6998 drm_calc_timestamping_constants(&crtc->base, &adjusted_mode); 6999 7000 crtc->mode_flags = crtc_state->mode_flags; 7001 7002 /* 7003 * The scanline counter increments at the leading edge of hsync. 7004 * 7005 * On most platforms it starts counting from vtotal-1 on the 7006 * first active line. That means the scanline counter value is 7007 * always one less than what we would expect. Ie. just after 7008 * start of vblank, which also occurs at start of hsync (on the 7009 * last active line), the scanline counter will read vblank_start-1. 7010 * 7011 * On gen2 the scanline counter starts counting from 1 instead 7012 * of vtotal-1, so we have to subtract one (or rather add vtotal-1 7013 * to keep the value positive), instead of adding one. 7014 * 7015 * On HSW+ the behaviour of the scanline counter depends on the output 7016 * type. For DP ports it behaves like most other platforms, but on HDMI 7017 * there's an extra 1 line difference. So we need to add two instead of 7018 * one to the value. 7019 * 7020 * On VLV/CHV DSI the scanline counter would appear to increment 7021 * approx. 1/3 of a scanline before start of vblank. Unfortunately 7022 * that means we can't tell whether we're in vblank or not while 7023 * we're on that particular line. We must still set scanline_offset 7024 * to 1 so that the vblank timestamps come out correct when we query 7025 * the scanline counter from within the vblank interrupt handler. 7026 * However if queried just before the start of vblank we'll get an 7027 * answer that's slightly in the future. 7028 */ 7029 if (DISPLAY_VER(dev_priv) == 2) { 7030 int vtotal; 7031 7032 vtotal = adjusted_mode.crtc_vtotal; 7033 if (adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 7034 vtotal /= 2; 7035 7036 crtc->scanline_offset = vtotal - 1; 7037 } else if (HAS_DDI(dev_priv) && 7038 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 7039 crtc->scanline_offset = 2; 7040 } else { 7041 crtc->scanline_offset = 1; 7042 } 7043 } 7044 7045 static void intel_modeset_clear_plls(struct intel_atomic_state *state) 7046 { 7047 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7048 struct intel_crtc_state *new_crtc_state; 7049 struct intel_crtc *crtc; 7050 int i; 7051 7052 if (!dev_priv->dpll_funcs) 7053 return; 7054 7055 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7056 if (!intel_crtc_needs_modeset(new_crtc_state)) 7057 continue; 7058 7059 intel_release_shared_dplls(state, crtc); 7060 } 7061 } 7062 7063 /* 7064 * This implements the workaround described in the "notes" section of the mode 7065 * set sequence documentation. When going from no pipes or single pipe to 7066 * multiple pipes, and planes are enabled after the pipe, we need to wait at 7067 * least 2 vblanks on the first pipe before enabling planes on the second pipe. 7068 */ 7069 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state) 7070 { 7071 struct intel_crtc_state *crtc_state; 7072 struct intel_crtc *crtc; 7073 struct intel_crtc_state *first_crtc_state = NULL; 7074 struct intel_crtc_state *other_crtc_state = NULL; 7075 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; 7076 int i; 7077 7078 /* look at all crtc's that are going to be enabled in during modeset */ 7079 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7080 if (!crtc_state->hw.active || 7081 !intel_crtc_needs_modeset(crtc_state)) 7082 continue; 7083 7084 if (first_crtc_state) { 7085 other_crtc_state = crtc_state; 7086 break; 7087 } else { 7088 first_crtc_state = crtc_state; 7089 first_pipe = crtc->pipe; 7090 } 7091 } 7092 7093 /* No workaround needed? */ 7094 if (!first_crtc_state) 7095 return 0; 7096 7097 /* w/a possibly needed, check how many crtc's are already enabled. */ 7098 for_each_intel_crtc(state->base.dev, crtc) { 7099 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 7100 if (IS_ERR(crtc_state)) 7101 return PTR_ERR(crtc_state); 7102 7103 crtc_state->hsw_workaround_pipe = INVALID_PIPE; 7104 7105 if (!crtc_state->hw.active || 7106 intel_crtc_needs_modeset(crtc_state)) 7107 continue; 7108 7109 /* 2 or more enabled crtcs means no need for w/a */ 7110 if (enabled_pipe != INVALID_PIPE) 7111 return 0; 7112 7113 enabled_pipe = crtc->pipe; 7114 } 7115 7116 if (enabled_pipe != INVALID_PIPE) 7117 first_crtc_state->hsw_workaround_pipe = enabled_pipe; 7118 else if (other_crtc_state) 7119 other_crtc_state->hsw_workaround_pipe = first_pipe; 7120 7121 return 0; 7122 } 7123 7124 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 7125 u8 active_pipes) 7126 { 7127 const struct intel_crtc_state *crtc_state; 7128 struct intel_crtc *crtc; 7129 int i; 7130 7131 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7132 if (crtc_state->hw.active) 7133 active_pipes |= BIT(crtc->pipe); 7134 else 7135 active_pipes &= ~BIT(crtc->pipe); 7136 } 7137 7138 return active_pipes; 7139 } 7140 7141 static int intel_modeset_checks(struct intel_atomic_state *state) 7142 { 7143 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7144 7145 state->modeset = true; 7146 7147 if (IS_HASWELL(dev_priv)) 7148 return hsw_mode_set_planes_workaround(state); 7149 7150 return 0; 7151 } 7152 7153 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state, 7154 struct intel_crtc_state *new_crtc_state) 7155 { 7156 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) 7157 return; 7158 7159 new_crtc_state->uapi.mode_changed = false; 7160 new_crtc_state->update_pipe = true; 7161 } 7162 7163 static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state, 7164 struct intel_crtc_state *new_crtc_state) 7165 { 7166 /* 7167 * If we're not doing the full modeset we want to 7168 * keep the current M/N values as they may be 7169 * sufficiently different to the computed values 7170 * to cause problems. 7171 * 7172 * FIXME: should really copy more fuzzy state here 7173 */ 7174 new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n; 7175 new_crtc_state->dp_m_n = old_crtc_state->dp_m_n; 7176 new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2; 7177 new_crtc_state->has_drrs = old_crtc_state->has_drrs; 7178 } 7179 7180 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state, 7181 struct intel_crtc *crtc, 7182 u8 plane_ids_mask) 7183 { 7184 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7185 struct intel_plane *plane; 7186 7187 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 7188 struct intel_plane_state *plane_state; 7189 7190 if ((plane_ids_mask & BIT(plane->id)) == 0) 7191 continue; 7192 7193 plane_state = intel_atomic_get_plane_state(state, plane); 7194 if (IS_ERR(plane_state)) 7195 return PTR_ERR(plane_state); 7196 } 7197 7198 return 0; 7199 } 7200 7201 int intel_atomic_add_affected_planes(struct intel_atomic_state *state, 7202 struct intel_crtc *crtc) 7203 { 7204 const struct intel_crtc_state *old_crtc_state = 7205 intel_atomic_get_old_crtc_state(state, crtc); 7206 const struct intel_crtc_state *new_crtc_state = 7207 intel_atomic_get_new_crtc_state(state, crtc); 7208 7209 return intel_crtc_add_planes_to_state(state, crtc, 7210 old_crtc_state->enabled_planes | 7211 new_crtc_state->enabled_planes); 7212 } 7213 7214 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv) 7215 { 7216 /* See {hsw,vlv,ivb}_plane_ratio() */ 7217 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) || 7218 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) || 7219 IS_IVYBRIDGE(dev_priv); 7220 } 7221 7222 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state, 7223 struct intel_crtc *crtc, 7224 struct intel_crtc *other) 7225 { 7226 const struct intel_plane_state *plane_state; 7227 struct intel_plane *plane; 7228 u8 plane_ids = 0; 7229 int i; 7230 7231 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 7232 if (plane->pipe == crtc->pipe) 7233 plane_ids |= BIT(plane->id); 7234 } 7235 7236 return intel_crtc_add_planes_to_state(state, other, plane_ids); 7237 } 7238 7239 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state) 7240 { 7241 struct drm_i915_private *i915 = to_i915(state->base.dev); 7242 const struct intel_crtc_state *crtc_state; 7243 struct intel_crtc *crtc; 7244 int i; 7245 7246 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7247 struct intel_crtc *other; 7248 7249 for_each_intel_crtc_in_pipe_mask(&i915->drm, other, 7250 crtc_state->bigjoiner_pipes) { 7251 int ret; 7252 7253 if (crtc == other) 7254 continue; 7255 7256 ret = intel_crtc_add_bigjoiner_planes(state, crtc, other); 7257 if (ret) 7258 return ret; 7259 } 7260 } 7261 7262 return 0; 7263 } 7264 7265 static int intel_atomic_check_planes(struct intel_atomic_state *state) 7266 { 7267 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7268 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7269 struct intel_plane_state *plane_state; 7270 struct intel_plane *plane; 7271 struct intel_crtc *crtc; 7272 int i, ret; 7273 7274 ret = icl_add_linked_planes(state); 7275 if (ret) 7276 return ret; 7277 7278 ret = intel_bigjoiner_add_affected_planes(state); 7279 if (ret) 7280 return ret; 7281 7282 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 7283 ret = intel_plane_atomic_check(state, plane); 7284 if (ret) { 7285 drm_dbg_atomic(&dev_priv->drm, 7286 "[PLANE:%d:%s] atomic driver check failed\n", 7287 plane->base.base.id, plane->base.name); 7288 return ret; 7289 } 7290 } 7291 7292 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7293 new_crtc_state, i) { 7294 u8 old_active_planes, new_active_planes; 7295 7296 ret = icl_check_nv12_planes(new_crtc_state); 7297 if (ret) 7298 return ret; 7299 7300 /* 7301 * On some platforms the number of active planes affects 7302 * the planes' minimum cdclk calculation. Add such planes 7303 * to the state before we compute the minimum cdclk. 7304 */ 7305 if (!active_planes_affects_min_cdclk(dev_priv)) 7306 continue; 7307 7308 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 7309 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 7310 7311 if (hweight8(old_active_planes) == hweight8(new_active_planes)) 7312 continue; 7313 7314 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes); 7315 if (ret) 7316 return ret; 7317 } 7318 7319 return 0; 7320 } 7321 7322 static int intel_atomic_check_crtcs(struct intel_atomic_state *state) 7323 { 7324 struct intel_crtc_state *crtc_state; 7325 struct intel_crtc *crtc; 7326 int i; 7327 7328 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7329 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 7330 int ret; 7331 7332 ret = intel_crtc_atomic_check(state, crtc); 7333 if (ret) { 7334 drm_dbg_atomic(&i915->drm, 7335 "[CRTC:%d:%s] atomic driver check failed\n", 7336 crtc->base.base.id, crtc->base.name); 7337 return ret; 7338 } 7339 } 7340 7341 return 0; 7342 } 7343 7344 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, 7345 u8 transcoders) 7346 { 7347 const struct intel_crtc_state *new_crtc_state; 7348 struct intel_crtc *crtc; 7349 int i; 7350 7351 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7352 if (new_crtc_state->hw.enable && 7353 transcoders & BIT(new_crtc_state->cpu_transcoder) && 7354 intel_crtc_needs_modeset(new_crtc_state)) 7355 return true; 7356 } 7357 7358 return false; 7359 } 7360 7361 static bool intel_pipes_need_modeset(struct intel_atomic_state *state, 7362 u8 pipes) 7363 { 7364 const struct intel_crtc_state *new_crtc_state; 7365 struct intel_crtc *crtc; 7366 int i; 7367 7368 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7369 if (new_crtc_state->hw.enable && 7370 pipes & BIT(crtc->pipe) && 7371 intel_crtc_needs_modeset(new_crtc_state)) 7372 return true; 7373 } 7374 7375 return false; 7376 } 7377 7378 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state, 7379 struct intel_crtc *master_crtc) 7380 { 7381 struct drm_i915_private *i915 = to_i915(state->base.dev); 7382 struct intel_crtc_state *master_crtc_state = 7383 intel_atomic_get_new_crtc_state(state, master_crtc); 7384 struct intel_crtc *slave_crtc; 7385 7386 if (!master_crtc_state->bigjoiner_pipes) 7387 return 0; 7388 7389 /* sanity check */ 7390 if (drm_WARN_ON(&i915->drm, 7391 master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state))) 7392 return -EINVAL; 7393 7394 if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) { 7395 drm_dbg_kms(&i915->drm, 7396 "[CRTC:%d:%s] Cannot act as big joiner master " 7397 "(need 0x%x as pipes, only 0x%x possible)\n", 7398 master_crtc->base.base.id, master_crtc->base.name, 7399 master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915)); 7400 return -EINVAL; 7401 } 7402 7403 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 7404 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 7405 struct intel_crtc_state *slave_crtc_state; 7406 int ret; 7407 7408 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc); 7409 if (IS_ERR(slave_crtc_state)) 7410 return PTR_ERR(slave_crtc_state); 7411 7412 /* master being enabled, slave was already configured? */ 7413 if (slave_crtc_state->uapi.enable) { 7414 drm_dbg_kms(&i915->drm, 7415 "[CRTC:%d:%s] Slave is enabled as normal CRTC, but " 7416 "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n", 7417 slave_crtc->base.base.id, slave_crtc->base.name, 7418 master_crtc->base.base.id, master_crtc->base.name); 7419 return -EINVAL; 7420 } 7421 7422 /* 7423 * The state copy logic assumes the master crtc gets processed 7424 * before the slave crtc during the main compute_config loop. 7425 * This works because the crtcs are created in pipe order, 7426 * and the hardware requires master pipe < slave pipe as well. 7427 * Should that change we need to rethink the logic. 7428 */ 7429 if (WARN_ON(drm_crtc_index(&master_crtc->base) > 7430 drm_crtc_index(&slave_crtc->base))) 7431 return -EINVAL; 7432 7433 drm_dbg_kms(&i915->drm, 7434 "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n", 7435 slave_crtc->base.base.id, slave_crtc->base.name, 7436 master_crtc->base.base.id, master_crtc->base.name); 7437 7438 slave_crtc_state->bigjoiner_pipes = 7439 master_crtc_state->bigjoiner_pipes; 7440 7441 ret = copy_bigjoiner_crtc_state_modeset(state, slave_crtc); 7442 if (ret) 7443 return ret; 7444 } 7445 7446 return 0; 7447 } 7448 7449 static void kill_bigjoiner_slave(struct intel_atomic_state *state, 7450 struct intel_crtc *master_crtc) 7451 { 7452 struct drm_i915_private *i915 = to_i915(state->base.dev); 7453 struct intel_crtc_state *master_crtc_state = 7454 intel_atomic_get_new_crtc_state(state, master_crtc); 7455 struct intel_crtc *slave_crtc; 7456 7457 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 7458 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 7459 struct intel_crtc_state *slave_crtc_state = 7460 intel_atomic_get_new_crtc_state(state, slave_crtc); 7461 7462 slave_crtc_state->bigjoiner_pipes = 0; 7463 7464 intel_crtc_copy_uapi_to_hw_state_modeset(state, slave_crtc); 7465 } 7466 7467 master_crtc_state->bigjoiner_pipes = 0; 7468 } 7469 7470 /** 7471 * DOC: asynchronous flip implementation 7472 * 7473 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC 7474 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL. 7475 * Correspondingly, support is currently added for primary plane only. 7476 * 7477 * Async flip can only change the plane surface address, so anything else 7478 * changing is rejected from the intel_async_flip_check_hw() function. 7479 * Once this check is cleared, flip done interrupt is enabled using 7480 * the intel_crtc_enable_flip_done() function. 7481 * 7482 * As soon as the surface address register is written, flip done interrupt is 7483 * generated and the requested events are sent to the usersapce in the interrupt 7484 * handler itself. The timestamp and sequence sent during the flip done event 7485 * correspond to the last vblank and have no relation to the actual time when 7486 * the flip done event was sent. 7487 */ 7488 static int intel_async_flip_check_uapi(struct intel_atomic_state *state, 7489 struct intel_crtc *crtc) 7490 { 7491 struct drm_i915_private *i915 = to_i915(state->base.dev); 7492 const struct intel_crtc_state *new_crtc_state = 7493 intel_atomic_get_new_crtc_state(state, crtc); 7494 const struct intel_plane_state *old_plane_state; 7495 struct intel_plane_state *new_plane_state; 7496 struct intel_plane *plane; 7497 int i; 7498 7499 if (!new_crtc_state->uapi.async_flip) 7500 return 0; 7501 7502 if (!new_crtc_state->uapi.active) { 7503 drm_dbg_kms(&i915->drm, 7504 "[CRTC:%d:%s] not active\n", 7505 crtc->base.base.id, crtc->base.name); 7506 return -EINVAL; 7507 } 7508 7509 if (intel_crtc_needs_modeset(new_crtc_state)) { 7510 drm_dbg_kms(&i915->drm, 7511 "[CRTC:%d:%s] modeset required\n", 7512 crtc->base.base.id, crtc->base.name); 7513 return -EINVAL; 7514 } 7515 7516 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 7517 new_plane_state, i) { 7518 if (plane->pipe != crtc->pipe) 7519 continue; 7520 7521 /* 7522 * TODO: Async flip is only supported through the page flip IOCTL 7523 * as of now. So support currently added for primary plane only. 7524 * Support for other planes on platforms on which supports 7525 * this(vlv/chv and icl+) should be added when async flip is 7526 * enabled in the atomic IOCTL path. 7527 */ 7528 if (!plane->async_flip) { 7529 drm_dbg_kms(&i915->drm, 7530 "[PLANE:%d:%s] async flip not supported\n", 7531 plane->base.base.id, plane->base.name); 7532 return -EINVAL; 7533 } 7534 7535 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) { 7536 drm_dbg_kms(&i915->drm, 7537 "[PLANE:%d:%s] no old or new framebuffer\n", 7538 plane->base.base.id, plane->base.name); 7539 return -EINVAL; 7540 } 7541 } 7542 7543 return 0; 7544 } 7545 7546 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc) 7547 { 7548 struct drm_i915_private *i915 = to_i915(state->base.dev); 7549 const struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7550 const struct intel_plane_state *new_plane_state, *old_plane_state; 7551 struct intel_plane *plane; 7552 int i; 7553 7554 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 7555 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 7556 7557 if (!new_crtc_state->uapi.async_flip) 7558 return 0; 7559 7560 if (!new_crtc_state->hw.active) { 7561 drm_dbg_kms(&i915->drm, 7562 "[CRTC:%d:%s] not active\n", 7563 crtc->base.base.id, crtc->base.name); 7564 return -EINVAL; 7565 } 7566 7567 if (intel_crtc_needs_modeset(new_crtc_state)) { 7568 drm_dbg_kms(&i915->drm, 7569 "[CRTC:%d:%s] modeset required\n", 7570 crtc->base.base.id, crtc->base.name); 7571 return -EINVAL; 7572 } 7573 7574 if (old_crtc_state->active_planes != new_crtc_state->active_planes) { 7575 drm_dbg_kms(&i915->drm, 7576 "[CRTC:%d:%s] Active planes cannot be in async flip\n", 7577 crtc->base.base.id, crtc->base.name); 7578 return -EINVAL; 7579 } 7580 7581 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 7582 new_plane_state, i) { 7583 if (plane->pipe != crtc->pipe) 7584 continue; 7585 7586 /* 7587 * Only async flip capable planes should be in the state 7588 * if we're really about to ask the hardware to perform 7589 * an async flip. We should never get this far otherwise. 7590 */ 7591 if (drm_WARN_ON(&i915->drm, 7592 new_crtc_state->do_async_flip && !plane->async_flip)) 7593 return -EINVAL; 7594 7595 /* 7596 * Only check async flip capable planes other planes 7597 * may be involved in the initial commit due to 7598 * the wm0/ddb optimization. 7599 * 7600 * TODO maybe should track which planes actually 7601 * were requested to do the async flip... 7602 */ 7603 if (!plane->async_flip) 7604 continue; 7605 7606 /* 7607 * FIXME: This check is kept generic for all platforms. 7608 * Need to verify this for all gen9 platforms to enable 7609 * this selectively if required. 7610 */ 7611 switch (new_plane_state->hw.fb->modifier) { 7612 case I915_FORMAT_MOD_X_TILED: 7613 case I915_FORMAT_MOD_Y_TILED: 7614 case I915_FORMAT_MOD_Yf_TILED: 7615 case I915_FORMAT_MOD_4_TILED: 7616 break; 7617 default: 7618 drm_dbg_kms(&i915->drm, 7619 "[PLANE:%d:%s] Modifier does not support async flips\n", 7620 plane->base.base.id, plane->base.name); 7621 return -EINVAL; 7622 } 7623 7624 if (new_plane_state->hw.fb->format->num_planes > 1) { 7625 drm_dbg_kms(&i915->drm, 7626 "[PLANE:%d:%s] Planar formats do not support async flips\n", 7627 plane->base.base.id, plane->base.name); 7628 return -EINVAL; 7629 } 7630 7631 if (old_plane_state->view.color_plane[0].mapping_stride != 7632 new_plane_state->view.color_plane[0].mapping_stride) { 7633 drm_dbg_kms(&i915->drm, 7634 "[PLANE:%d:%s] Stride cannot be changed in async flip\n", 7635 plane->base.base.id, plane->base.name); 7636 return -EINVAL; 7637 } 7638 7639 if (old_plane_state->hw.fb->modifier != 7640 new_plane_state->hw.fb->modifier) { 7641 drm_dbg_kms(&i915->drm, 7642 "[PLANE:%d:%s] Modifier cannot be changed in async flip\n", 7643 plane->base.base.id, plane->base.name); 7644 return -EINVAL; 7645 } 7646 7647 if (old_plane_state->hw.fb->format != 7648 new_plane_state->hw.fb->format) { 7649 drm_dbg_kms(&i915->drm, 7650 "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n", 7651 plane->base.base.id, plane->base.name); 7652 return -EINVAL; 7653 } 7654 7655 if (old_plane_state->hw.rotation != 7656 new_plane_state->hw.rotation) { 7657 drm_dbg_kms(&i915->drm, 7658 "[PLANE:%d:%s] Rotation cannot be changed in async flip\n", 7659 plane->base.base.id, plane->base.name); 7660 return -EINVAL; 7661 } 7662 7663 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) || 7664 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) { 7665 drm_dbg_kms(&i915->drm, 7666 "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n", 7667 plane->base.base.id, plane->base.name); 7668 return -EINVAL; 7669 } 7670 7671 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) { 7672 drm_dbg_kms(&i915->drm, 7673 "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n", 7674 plane->base.base.id, plane->base.name); 7675 return -EINVAL; 7676 } 7677 7678 if (old_plane_state->hw.pixel_blend_mode != 7679 new_plane_state->hw.pixel_blend_mode) { 7680 drm_dbg_kms(&i915->drm, 7681 "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n", 7682 plane->base.base.id, plane->base.name); 7683 return -EINVAL; 7684 } 7685 7686 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) { 7687 drm_dbg_kms(&i915->drm, 7688 "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n", 7689 plane->base.base.id, plane->base.name); 7690 return -EINVAL; 7691 } 7692 7693 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) { 7694 drm_dbg_kms(&i915->drm, 7695 "[PLANE:%d:%s] Color range cannot be changed in async flip\n", 7696 plane->base.base.id, plane->base.name); 7697 return -EINVAL; 7698 } 7699 7700 /* plane decryption is allow to change only in synchronous flips */ 7701 if (old_plane_state->decrypt != new_plane_state->decrypt) { 7702 drm_dbg_kms(&i915->drm, 7703 "[PLANE:%d:%s] Decryption cannot be changed in async flip\n", 7704 plane->base.base.id, plane->base.name); 7705 return -EINVAL; 7706 } 7707 } 7708 7709 return 0; 7710 } 7711 7712 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state) 7713 { 7714 struct drm_i915_private *i915 = to_i915(state->base.dev); 7715 struct intel_crtc_state *crtc_state; 7716 struct intel_crtc *crtc; 7717 u8 affected_pipes = 0; 7718 u8 modeset_pipes = 0; 7719 int i; 7720 7721 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7722 affected_pipes |= crtc_state->bigjoiner_pipes; 7723 if (intel_crtc_needs_modeset(crtc_state)) 7724 modeset_pipes |= crtc_state->bigjoiner_pipes; 7725 } 7726 7727 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) { 7728 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 7729 if (IS_ERR(crtc_state)) 7730 return PTR_ERR(crtc_state); 7731 } 7732 7733 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) { 7734 int ret; 7735 7736 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 7737 7738 crtc_state->uapi.mode_changed = true; 7739 7740 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); 7741 if (ret) 7742 return ret; 7743 7744 ret = intel_atomic_add_affected_planes(state, crtc); 7745 if (ret) 7746 return ret; 7747 } 7748 7749 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7750 /* Kill old bigjoiner link, we may re-establish afterwards */ 7751 if (intel_crtc_needs_modeset(crtc_state) && 7752 intel_crtc_is_bigjoiner_master(crtc_state)) 7753 kill_bigjoiner_slave(state, crtc); 7754 } 7755 7756 return 0; 7757 } 7758 7759 /** 7760 * intel_atomic_check - validate state object 7761 * @dev: drm device 7762 * @_state: state to validate 7763 */ 7764 static int intel_atomic_check(struct drm_device *dev, 7765 struct drm_atomic_state *_state) 7766 { 7767 struct drm_i915_private *dev_priv = to_i915(dev); 7768 struct intel_atomic_state *state = to_intel_atomic_state(_state); 7769 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7770 struct intel_crtc *crtc; 7771 int ret, i; 7772 bool any_ms = false; 7773 7774 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7775 new_crtc_state, i) { 7776 if (new_crtc_state->inherited != old_crtc_state->inherited) 7777 new_crtc_state->uapi.mode_changed = true; 7778 7779 if (new_crtc_state->uapi.scaling_filter != 7780 old_crtc_state->uapi.scaling_filter) 7781 new_crtc_state->uapi.mode_changed = true; 7782 } 7783 7784 intel_vrr_check_modeset(state); 7785 7786 ret = drm_atomic_helper_check_modeset(dev, &state->base); 7787 if (ret) 7788 goto fail; 7789 7790 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7791 ret = intel_async_flip_check_uapi(state, crtc); 7792 if (ret) 7793 return ret; 7794 } 7795 7796 ret = intel_bigjoiner_add_affected_crtcs(state); 7797 if (ret) 7798 goto fail; 7799 7800 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7801 new_crtc_state, i) { 7802 if (!intel_crtc_needs_modeset(new_crtc_state)) { 7803 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 7804 copy_bigjoiner_crtc_state_nomodeset(state, crtc); 7805 else 7806 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 7807 continue; 7808 } 7809 7810 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) { 7811 drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable); 7812 continue; 7813 } 7814 7815 ret = intel_crtc_prepare_cleared_state(state, crtc); 7816 if (ret) 7817 goto fail; 7818 7819 if (!new_crtc_state->hw.enable) 7820 continue; 7821 7822 ret = intel_modeset_pipe_config(state, new_crtc_state); 7823 if (ret) 7824 goto fail; 7825 7826 ret = intel_atomic_check_bigjoiner(state, crtc); 7827 if (ret) 7828 goto fail; 7829 } 7830 7831 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7832 new_crtc_state, i) { 7833 if (!intel_crtc_needs_modeset(new_crtc_state)) 7834 continue; 7835 7836 ret = intel_modeset_pipe_config_late(new_crtc_state); 7837 if (ret) 7838 goto fail; 7839 7840 intel_crtc_check_fastset(old_crtc_state, new_crtc_state); 7841 } 7842 7843 /** 7844 * Check if fastset is allowed by external dependencies like other 7845 * pipes and transcoders. 7846 * 7847 * Right now it only forces a fullmodeset when the MST master 7848 * transcoder did not changed but the pipe of the master transcoder 7849 * needs a fullmodeset so all slaves also needs to do a fullmodeset or 7850 * in case of port synced crtcs, if one of the synced crtcs 7851 * needs a full modeset, all other synced crtcs should be 7852 * forced a full modeset. 7853 */ 7854 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7855 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state)) 7856 continue; 7857 7858 if (intel_dp_mst_is_slave_trans(new_crtc_state)) { 7859 enum transcoder master = new_crtc_state->mst_master_transcoder; 7860 7861 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) { 7862 new_crtc_state->uapi.mode_changed = true; 7863 new_crtc_state->update_pipe = false; 7864 } 7865 } 7866 7867 if (is_trans_port_sync_mode(new_crtc_state)) { 7868 u8 trans = new_crtc_state->sync_mode_slaves_mask; 7869 7870 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER) 7871 trans |= BIT(new_crtc_state->master_transcoder); 7872 7873 if (intel_cpu_transcoders_need_modeset(state, trans)) { 7874 new_crtc_state->uapi.mode_changed = true; 7875 new_crtc_state->update_pipe = false; 7876 } 7877 } 7878 7879 if (new_crtc_state->bigjoiner_pipes) { 7880 if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) { 7881 new_crtc_state->uapi.mode_changed = true; 7882 new_crtc_state->update_pipe = false; 7883 } 7884 } 7885 } 7886 7887 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7888 new_crtc_state, i) { 7889 if (intel_crtc_needs_modeset(new_crtc_state)) { 7890 any_ms = true; 7891 continue; 7892 } 7893 7894 if (!new_crtc_state->update_pipe) 7895 continue; 7896 7897 intel_crtc_copy_fastset(old_crtc_state, new_crtc_state); 7898 } 7899 7900 if (any_ms && !check_digital_port_conflicts(state)) { 7901 drm_dbg_kms(&dev_priv->drm, 7902 "rejecting conflicting digital port configuration\n"); 7903 ret = -EINVAL; 7904 goto fail; 7905 } 7906 7907 ret = drm_dp_mst_atomic_check(&state->base); 7908 if (ret) 7909 goto fail; 7910 7911 ret = intel_atomic_check_planes(state); 7912 if (ret) 7913 goto fail; 7914 7915 ret = intel_compute_global_watermarks(state); 7916 if (ret) 7917 goto fail; 7918 7919 ret = intel_bw_atomic_check(state); 7920 if (ret) 7921 goto fail; 7922 7923 ret = intel_cdclk_atomic_check(state, &any_ms); 7924 if (ret) 7925 goto fail; 7926 7927 if (intel_any_crtc_needs_modeset(state)) 7928 any_ms = true; 7929 7930 if (any_ms) { 7931 ret = intel_modeset_checks(state); 7932 if (ret) 7933 goto fail; 7934 7935 ret = intel_modeset_calc_cdclk(state); 7936 if (ret) 7937 return ret; 7938 7939 intel_modeset_clear_plls(state); 7940 } 7941 7942 ret = intel_atomic_check_crtcs(state); 7943 if (ret) 7944 goto fail; 7945 7946 ret = intel_fbc_atomic_check(state); 7947 if (ret) 7948 goto fail; 7949 7950 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7951 new_crtc_state, i) { 7952 ret = intel_async_flip_check_hw(state, crtc); 7953 if (ret) 7954 goto fail; 7955 7956 if (!intel_crtc_needs_modeset(new_crtc_state) && 7957 !new_crtc_state->update_pipe) 7958 continue; 7959 7960 intel_dump_pipe_config(new_crtc_state, state, 7961 intel_crtc_needs_modeset(new_crtc_state) ? 7962 "[modeset]" : "[fastset]"); 7963 } 7964 7965 return 0; 7966 7967 fail: 7968 if (ret == -EDEADLK) 7969 return ret; 7970 7971 /* 7972 * FIXME would probably be nice to know which crtc specifically 7973 * caused the failure, in cases where we can pinpoint it. 7974 */ 7975 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7976 new_crtc_state, i) 7977 intel_dump_pipe_config(new_crtc_state, state, "[failed]"); 7978 7979 return ret; 7980 } 7981 7982 static int intel_atomic_prepare_commit(struct intel_atomic_state *state) 7983 { 7984 struct intel_crtc_state *crtc_state; 7985 struct intel_crtc *crtc; 7986 int i, ret; 7987 7988 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base); 7989 if (ret < 0) 7990 return ret; 7991 7992 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7993 bool mode_changed = intel_crtc_needs_modeset(crtc_state); 7994 7995 if (mode_changed || crtc_state->update_pipe || 7996 crtc_state->uapi.color_mgmt_changed) { 7997 intel_dsb_prepare(crtc_state); 7998 } 7999 } 8000 8001 return 0; 8002 } 8003 8004 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 8005 struct intel_crtc_state *crtc_state) 8006 { 8007 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 8008 8009 if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes) 8010 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 8011 8012 if (crtc_state->has_pch_encoder) { 8013 enum pipe pch_transcoder = 8014 intel_crtc_pch_transcoder(crtc); 8015 8016 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true); 8017 } 8018 } 8019 8020 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, 8021 const struct intel_crtc_state *new_crtc_state) 8022 { 8023 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 8024 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 8025 8026 /* 8027 * Update pipe size and adjust fitter if needed: the reason for this is 8028 * that in compute_mode_changes we check the native mode (not the pfit 8029 * mode) to see if we can flip rather than do a full mode set. In the 8030 * fastboot case, we'll flip, but if we don't update the pipesrc and 8031 * pfit state, we'll end up with a big fb scanned out into the wrong 8032 * sized surface. 8033 */ 8034 intel_set_pipe_src_size(new_crtc_state); 8035 8036 /* on skylake this is done by detaching scalers */ 8037 if (DISPLAY_VER(dev_priv) >= 9) { 8038 if (new_crtc_state->pch_pfit.enabled) 8039 skl_pfit_enable(new_crtc_state); 8040 } else if (HAS_PCH_SPLIT(dev_priv)) { 8041 if (new_crtc_state->pch_pfit.enabled) 8042 ilk_pfit_enable(new_crtc_state); 8043 else if (old_crtc_state->pch_pfit.enabled) 8044 ilk_pfit_disable(old_crtc_state); 8045 } 8046 8047 /* 8048 * The register is supposedly single buffered so perhaps 8049 * not 100% correct to do this here. But SKL+ calculate 8050 * this based on the adjust pixel rate so pfit changes do 8051 * affect it and so it must be updated for fastsets. 8052 * HSW/BDW only really need this here for fastboot, after 8053 * that the value should not change without a full modeset. 8054 */ 8055 if (DISPLAY_VER(dev_priv) >= 9 || 8056 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 8057 hsw_set_linetime_wm(new_crtc_state); 8058 } 8059 8060 static void commit_pipe_pre_planes(struct intel_atomic_state *state, 8061 struct intel_crtc *crtc) 8062 { 8063 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8064 const struct intel_crtc_state *old_crtc_state = 8065 intel_atomic_get_old_crtc_state(state, crtc); 8066 const struct intel_crtc_state *new_crtc_state = 8067 intel_atomic_get_new_crtc_state(state, crtc); 8068 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 8069 8070 /* 8071 * During modesets pipe configuration was programmed as the 8072 * CRTC was enabled. 8073 */ 8074 if (!modeset) { 8075 if (new_crtc_state->uapi.color_mgmt_changed || 8076 new_crtc_state->update_pipe) 8077 intel_color_commit(new_crtc_state); 8078 8079 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 8080 bdw_set_pipemisc(new_crtc_state); 8081 8082 if (new_crtc_state->update_pipe) 8083 intel_pipe_fastset(old_crtc_state, new_crtc_state); 8084 } 8085 8086 intel_psr2_program_trans_man_trk_ctl(new_crtc_state); 8087 8088 intel_atomic_update_watermarks(state, crtc); 8089 } 8090 8091 static void commit_pipe_post_planes(struct intel_atomic_state *state, 8092 struct intel_crtc *crtc) 8093 { 8094 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8095 const struct intel_crtc_state *new_crtc_state = 8096 intel_atomic_get_new_crtc_state(state, crtc); 8097 8098 /* 8099 * Disable the scaler(s) after the plane(s) so that we don't 8100 * get a catastrophic underrun even if the two operations 8101 * end up happening in two different frames. 8102 */ 8103 if (DISPLAY_VER(dev_priv) >= 9 && 8104 !intel_crtc_needs_modeset(new_crtc_state)) 8105 skl_detach_scalers(new_crtc_state); 8106 } 8107 8108 static void intel_enable_crtc(struct intel_atomic_state *state, 8109 struct intel_crtc *crtc) 8110 { 8111 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8112 const struct intel_crtc_state *new_crtc_state = 8113 intel_atomic_get_new_crtc_state(state, crtc); 8114 8115 if (!intel_crtc_needs_modeset(new_crtc_state)) 8116 return; 8117 8118 intel_crtc_update_active_timings(new_crtc_state); 8119 8120 dev_priv->display->crtc_enable(state, crtc); 8121 8122 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 8123 return; 8124 8125 /* vblanks work again, re-enable pipe CRC. */ 8126 intel_crtc_enable_pipe_crc(crtc); 8127 } 8128 8129 static void intel_update_crtc(struct intel_atomic_state *state, 8130 struct intel_crtc *crtc) 8131 { 8132 struct drm_i915_private *i915 = to_i915(state->base.dev); 8133 const struct intel_crtc_state *old_crtc_state = 8134 intel_atomic_get_old_crtc_state(state, crtc); 8135 struct intel_crtc_state *new_crtc_state = 8136 intel_atomic_get_new_crtc_state(state, crtc); 8137 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 8138 8139 if (!modeset) { 8140 if (new_crtc_state->preload_luts && 8141 (new_crtc_state->uapi.color_mgmt_changed || 8142 new_crtc_state->update_pipe)) 8143 intel_color_load_luts(new_crtc_state); 8144 8145 intel_pre_plane_update(state, crtc); 8146 8147 if (new_crtc_state->update_pipe) 8148 intel_encoders_update_pipe(state, crtc); 8149 8150 if (DISPLAY_VER(i915) >= 11 && 8151 new_crtc_state->update_pipe) 8152 icl_set_pipe_chicken(new_crtc_state); 8153 } 8154 8155 intel_fbc_update(state, crtc); 8156 8157 intel_crtc_planes_update_noarm(state, crtc); 8158 8159 /* Perform vblank evasion around commit operation */ 8160 intel_pipe_update_start(new_crtc_state); 8161 8162 commit_pipe_pre_planes(state, crtc); 8163 8164 intel_crtc_planes_update_arm(state, crtc); 8165 8166 commit_pipe_post_planes(state, crtc); 8167 8168 intel_pipe_update_end(new_crtc_state); 8169 8170 /* 8171 * We usually enable FIFO underrun interrupts as part of the 8172 * CRTC enable sequence during modesets. But when we inherit a 8173 * valid pipe configuration from the BIOS we need to take care 8174 * of enabling them on the CRTC's first fastset. 8175 */ 8176 if (new_crtc_state->update_pipe && !modeset && 8177 old_crtc_state->inherited) 8178 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state); 8179 } 8180 8181 static void intel_old_crtc_state_disables(struct intel_atomic_state *state, 8182 struct intel_crtc_state *old_crtc_state, 8183 struct intel_crtc_state *new_crtc_state, 8184 struct intel_crtc *crtc) 8185 { 8186 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8187 8188 /* 8189 * We need to disable pipe CRC before disabling the pipe, 8190 * or we race against vblank off. 8191 */ 8192 intel_crtc_disable_pipe_crc(crtc); 8193 8194 dev_priv->display->crtc_disable(state, crtc); 8195 crtc->active = false; 8196 intel_fbc_disable(crtc); 8197 intel_disable_shared_dpll(old_crtc_state); 8198 8199 /* FIXME unify this for all platforms */ 8200 if (!new_crtc_state->hw.active && 8201 !HAS_GMCH(dev_priv)) 8202 intel_initial_watermarks(state, crtc); 8203 } 8204 8205 static void intel_commit_modeset_disables(struct intel_atomic_state *state) 8206 { 8207 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 8208 struct intel_crtc *crtc; 8209 u32 handled = 0; 8210 int i; 8211 8212 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8213 new_crtc_state, i) { 8214 if (!intel_crtc_needs_modeset(new_crtc_state)) 8215 continue; 8216 8217 if (!old_crtc_state->hw.active) 8218 continue; 8219 8220 intel_pre_plane_update(state, crtc); 8221 intel_crtc_disable_planes(state, crtc); 8222 } 8223 8224 /* Only disable port sync and MST slaves */ 8225 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8226 new_crtc_state, i) { 8227 if (!intel_crtc_needs_modeset(new_crtc_state)) 8228 continue; 8229 8230 if (!old_crtc_state->hw.active) 8231 continue; 8232 8233 /* In case of Transcoder port Sync master slave CRTCs can be 8234 * assigned in any order and we need to make sure that 8235 * slave CRTCs are disabled first and then master CRTC since 8236 * Slave vblanks are masked till Master Vblanks. 8237 */ 8238 if (!is_trans_port_sync_slave(old_crtc_state) && 8239 !intel_dp_mst_is_slave_trans(old_crtc_state) && 8240 !intel_crtc_is_bigjoiner_slave(old_crtc_state)) 8241 continue; 8242 8243 intel_old_crtc_state_disables(state, old_crtc_state, 8244 new_crtc_state, crtc); 8245 handled |= BIT(crtc->pipe); 8246 } 8247 8248 /* Disable everything else left on */ 8249 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8250 new_crtc_state, i) { 8251 if (!intel_crtc_needs_modeset(new_crtc_state) || 8252 (handled & BIT(crtc->pipe))) 8253 continue; 8254 8255 if (!old_crtc_state->hw.active) 8256 continue; 8257 8258 intel_old_crtc_state_disables(state, old_crtc_state, 8259 new_crtc_state, crtc); 8260 } 8261 } 8262 8263 static void intel_commit_modeset_enables(struct intel_atomic_state *state) 8264 { 8265 struct intel_crtc_state *new_crtc_state; 8266 struct intel_crtc *crtc; 8267 int i; 8268 8269 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8270 if (!new_crtc_state->hw.active) 8271 continue; 8272 8273 intel_enable_crtc(state, crtc); 8274 intel_update_crtc(state, crtc); 8275 } 8276 } 8277 8278 static void skl_commit_modeset_enables(struct intel_atomic_state *state) 8279 { 8280 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8281 struct intel_crtc *crtc; 8282 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 8283 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; 8284 u8 update_pipes = 0, modeset_pipes = 0; 8285 int i; 8286 8287 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 8288 enum pipe pipe = crtc->pipe; 8289 8290 if (!new_crtc_state->hw.active) 8291 continue; 8292 8293 /* ignore allocations for crtc's that have been turned off. */ 8294 if (!intel_crtc_needs_modeset(new_crtc_state)) { 8295 entries[pipe] = old_crtc_state->wm.skl.ddb; 8296 update_pipes |= BIT(pipe); 8297 } else { 8298 modeset_pipes |= BIT(pipe); 8299 } 8300 } 8301 8302 /* 8303 * Whenever the number of active pipes changes, we need to make sure we 8304 * update the pipes in the right order so that their ddb allocations 8305 * never overlap with each other between CRTC updates. Otherwise we'll 8306 * cause pipe underruns and other bad stuff. 8307 * 8308 * So first lets enable all pipes that do not need a fullmodeset as 8309 * those don't have any external dependency. 8310 */ 8311 while (update_pipes) { 8312 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8313 new_crtc_state, i) { 8314 enum pipe pipe = crtc->pipe; 8315 8316 if ((update_pipes & BIT(pipe)) == 0) 8317 continue; 8318 8319 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 8320 entries, I915_MAX_PIPES, pipe)) 8321 continue; 8322 8323 entries[pipe] = new_crtc_state->wm.skl.ddb; 8324 update_pipes &= ~BIT(pipe); 8325 8326 intel_update_crtc(state, crtc); 8327 8328 /* 8329 * If this is an already active pipe, it's DDB changed, 8330 * and this isn't the last pipe that needs updating 8331 * then we need to wait for a vblank to pass for the 8332 * new ddb allocation to take effect. 8333 */ 8334 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, 8335 &old_crtc_state->wm.skl.ddb) && 8336 (update_pipes | modeset_pipes)) 8337 intel_crtc_wait_for_next_vblank(crtc); 8338 } 8339 } 8340 8341 update_pipes = modeset_pipes; 8342 8343 /* 8344 * Enable all pipes that needs a modeset and do not depends on other 8345 * pipes 8346 */ 8347 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8348 enum pipe pipe = crtc->pipe; 8349 8350 if ((modeset_pipes & BIT(pipe)) == 0) 8351 continue; 8352 8353 if (intel_dp_mst_is_slave_trans(new_crtc_state) || 8354 is_trans_port_sync_master(new_crtc_state) || 8355 intel_crtc_is_bigjoiner_master(new_crtc_state)) 8356 continue; 8357 8358 modeset_pipes &= ~BIT(pipe); 8359 8360 intel_enable_crtc(state, crtc); 8361 } 8362 8363 /* 8364 * Then we enable all remaining pipes that depend on other 8365 * pipes: MST slaves and port sync masters, big joiner master 8366 */ 8367 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8368 enum pipe pipe = crtc->pipe; 8369 8370 if ((modeset_pipes & BIT(pipe)) == 0) 8371 continue; 8372 8373 modeset_pipes &= ~BIT(pipe); 8374 8375 intel_enable_crtc(state, crtc); 8376 } 8377 8378 /* 8379 * Finally we do the plane updates/etc. for all pipes that got enabled. 8380 */ 8381 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8382 enum pipe pipe = crtc->pipe; 8383 8384 if ((update_pipes & BIT(pipe)) == 0) 8385 continue; 8386 8387 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 8388 entries, I915_MAX_PIPES, pipe)); 8389 8390 entries[pipe] = new_crtc_state->wm.skl.ddb; 8391 update_pipes &= ~BIT(pipe); 8392 8393 intel_update_crtc(state, crtc); 8394 } 8395 8396 drm_WARN_ON(&dev_priv->drm, modeset_pipes); 8397 drm_WARN_ON(&dev_priv->drm, update_pipes); 8398 } 8399 8400 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) 8401 { 8402 struct intel_atomic_state *state, *next; 8403 struct llist_node *freed; 8404 8405 freed = llist_del_all(&dev_priv->atomic_helper.free_list); 8406 llist_for_each_entry_safe(state, next, freed, freed) 8407 drm_atomic_state_put(&state->base); 8408 } 8409 8410 static void intel_atomic_helper_free_state_worker(struct work_struct *work) 8411 { 8412 struct drm_i915_private *dev_priv = 8413 container_of(work, typeof(*dev_priv), atomic_helper.free_work); 8414 8415 intel_atomic_helper_free_state(dev_priv); 8416 } 8417 8418 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) 8419 { 8420 struct wait_queue_entry wait_fence, wait_reset; 8421 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); 8422 8423 init_wait_entry(&wait_fence, 0); 8424 init_wait_entry(&wait_reset, 0); 8425 for (;;) { 8426 prepare_to_wait(&intel_state->commit_ready.wait, 8427 &wait_fence, TASK_UNINTERRUPTIBLE); 8428 prepare_to_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 8429 I915_RESET_MODESET), 8430 &wait_reset, TASK_UNINTERRUPTIBLE); 8431 8432 8433 if (i915_sw_fence_done(&intel_state->commit_ready) || 8434 test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags)) 8435 break; 8436 8437 schedule(); 8438 } 8439 finish_wait(&intel_state->commit_ready.wait, &wait_fence); 8440 finish_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 8441 I915_RESET_MODESET), 8442 &wait_reset); 8443 } 8444 8445 static void intel_cleanup_dsbs(struct intel_atomic_state *state) 8446 { 8447 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 8448 struct intel_crtc *crtc; 8449 int i; 8450 8451 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8452 new_crtc_state, i) 8453 intel_dsb_cleanup(old_crtc_state); 8454 } 8455 8456 static void intel_atomic_cleanup_work(struct work_struct *work) 8457 { 8458 struct intel_atomic_state *state = 8459 container_of(work, struct intel_atomic_state, base.commit_work); 8460 struct drm_i915_private *i915 = to_i915(state->base.dev); 8461 8462 intel_cleanup_dsbs(state); 8463 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base); 8464 drm_atomic_helper_commit_cleanup_done(&state->base); 8465 drm_atomic_state_put(&state->base); 8466 8467 intel_atomic_helper_free_state(i915); 8468 } 8469 8470 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state) 8471 { 8472 struct drm_i915_private *i915 = to_i915(state->base.dev); 8473 struct intel_plane *plane; 8474 struct intel_plane_state *plane_state; 8475 int i; 8476 8477 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 8478 struct drm_framebuffer *fb = plane_state->hw.fb; 8479 int cc_plane; 8480 int ret; 8481 8482 if (!fb) 8483 continue; 8484 8485 cc_plane = intel_fb_rc_ccs_cc_plane(fb); 8486 if (cc_plane < 0) 8487 continue; 8488 8489 /* 8490 * The layout of the fast clear color value expected by HW 8491 * (the DRM ABI requiring this value to be located in fb at offset 0 of plane#2): 8492 * - 4 x 4 bytes per-channel value 8493 * (in surface type specific float/int format provided by the fb user) 8494 * - 8 bytes native color value used by the display 8495 * (converted/written by GPU during a fast clear operation using the 8496 * above per-channel values) 8497 * 8498 * The commit's FB prepare hook already ensured that FB obj is pinned and the 8499 * caller made sure that the object is synced wrt. the related color clear value 8500 * GPU write on it. 8501 */ 8502 ret = i915_gem_object_read_from_page(intel_fb_obj(fb), 8503 fb->offsets[cc_plane] + 16, 8504 &plane_state->ccval, 8505 sizeof(plane_state->ccval)); 8506 /* The above could only fail if the FB obj has an unexpected backing store type. */ 8507 drm_WARN_ON(&i915->drm, ret); 8508 } 8509 } 8510 8511 static void intel_atomic_commit_tail(struct intel_atomic_state *state) 8512 { 8513 struct drm_device *dev = state->base.dev; 8514 struct drm_i915_private *dev_priv = to_i915(dev); 8515 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 8516 struct intel_crtc *crtc; 8517 u64 put_domains[I915_MAX_PIPES] = {}; 8518 intel_wakeref_t wakeref = 0; 8519 int i; 8520 8521 intel_atomic_commit_fence_wait(state); 8522 8523 drm_atomic_helper_wait_for_dependencies(&state->base); 8524 8525 if (state->modeset) 8526 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); 8527 8528 intel_atomic_prepare_plane_clear_colors(state); 8529 8530 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8531 new_crtc_state, i) { 8532 if (intel_crtc_needs_modeset(new_crtc_state) || 8533 new_crtc_state->update_pipe) { 8534 8535 put_domains[crtc->pipe] = 8536 modeset_get_crtc_power_domains(new_crtc_state); 8537 } 8538 } 8539 8540 intel_commit_modeset_disables(state); 8541 8542 /* FIXME: Eventually get rid of our crtc->config pointer */ 8543 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 8544 crtc->config = new_crtc_state; 8545 8546 if (state->modeset) { 8547 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base); 8548 8549 intel_set_cdclk_pre_plane_update(state); 8550 8551 intel_modeset_verify_disabled(dev_priv, state); 8552 } 8553 8554 intel_sagv_pre_plane_update(state); 8555 8556 /* Complete the events for pipes that have now been disabled */ 8557 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8558 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 8559 8560 /* Complete events for now disable pipes here. */ 8561 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) { 8562 spin_lock_irq(&dev->event_lock); 8563 drm_crtc_send_vblank_event(&crtc->base, 8564 new_crtc_state->uapi.event); 8565 spin_unlock_irq(&dev->event_lock); 8566 8567 new_crtc_state->uapi.event = NULL; 8568 } 8569 } 8570 8571 intel_encoders_update_prepare(state); 8572 8573 intel_dbuf_pre_plane_update(state); 8574 8575 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8576 if (new_crtc_state->do_async_flip) 8577 intel_crtc_enable_flip_done(state, crtc); 8578 } 8579 8580 /* Now enable the clocks, plane, pipe, and connectors that we set up. */ 8581 dev_priv->display->commit_modeset_enables(state); 8582 8583 intel_encoders_update_complete(state); 8584 8585 if (state->modeset) 8586 intel_set_cdclk_post_plane_update(state); 8587 8588 intel_wait_for_vblank_workers(state); 8589 8590 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here 8591 * already, but still need the state for the delayed optimization. To 8592 * fix this: 8593 * - wrap the optimization/post_plane_update stuff into a per-crtc work. 8594 * - schedule that vblank worker _before_ calling hw_done 8595 * - at the start of commit_tail, cancel it _synchrously 8596 * - switch over to the vblank wait helper in the core after that since 8597 * we don't need out special handling any more. 8598 */ 8599 drm_atomic_helper_wait_for_flip_done(dev, &state->base); 8600 8601 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8602 if (new_crtc_state->do_async_flip) 8603 intel_crtc_disable_flip_done(state, crtc); 8604 } 8605 8606 /* 8607 * Now that the vblank has passed, we can go ahead and program the 8608 * optimal watermarks on platforms that need two-step watermark 8609 * programming. 8610 * 8611 * TODO: Move this (and other cleanup) to an async worker eventually. 8612 */ 8613 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8614 new_crtc_state, i) { 8615 /* 8616 * Gen2 reports pipe underruns whenever all planes are disabled. 8617 * So re-enable underrun reporting after some planes get enabled. 8618 * 8619 * We do this before .optimize_watermarks() so that we have a 8620 * chance of catching underruns with the intermediate watermarks 8621 * vs. the new plane configuration. 8622 */ 8623 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state)) 8624 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 8625 8626 intel_optimize_watermarks(state, crtc); 8627 } 8628 8629 intel_dbuf_post_plane_update(state); 8630 intel_psr_post_plane_update(state); 8631 8632 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 8633 intel_post_plane_update(state, crtc); 8634 8635 modeset_put_crtc_power_domains(crtc, put_domains[crtc->pipe]); 8636 8637 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state); 8638 8639 /* 8640 * DSB cleanup is done in cleanup_work aligning with framebuffer 8641 * cleanup. So copy and reset the dsb structure to sync with 8642 * commit_done and later do dsb cleanup in cleanup_work. 8643 */ 8644 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb); 8645 } 8646 8647 /* Underruns don't always raise interrupts, so check manually */ 8648 intel_check_cpu_fifo_underruns(dev_priv); 8649 intel_check_pch_fifo_underruns(dev_priv); 8650 8651 if (state->modeset) 8652 intel_verify_planes(state); 8653 8654 intel_sagv_post_plane_update(state); 8655 8656 drm_atomic_helper_commit_hw_done(&state->base); 8657 8658 if (state->modeset) { 8659 /* As one of the primary mmio accessors, KMS has a high 8660 * likelihood of triggering bugs in unclaimed access. After we 8661 * finish modesetting, see if an error has been flagged, and if 8662 * so enable debugging for the next modeset - and hope we catch 8663 * the culprit. 8664 */ 8665 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); 8666 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref); 8667 } 8668 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 8669 8670 /* 8671 * Defer the cleanup of the old state to a separate worker to not 8672 * impede the current task (userspace for blocking modesets) that 8673 * are executed inline. For out-of-line asynchronous modesets/flips, 8674 * deferring to a new worker seems overkill, but we would place a 8675 * schedule point (cond_resched()) here anyway to keep latencies 8676 * down. 8677 */ 8678 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work); 8679 queue_work(system_highpri_wq, &state->base.commit_work); 8680 } 8681 8682 static void intel_atomic_commit_work(struct work_struct *work) 8683 { 8684 struct intel_atomic_state *state = 8685 container_of(work, struct intel_atomic_state, base.commit_work); 8686 8687 intel_atomic_commit_tail(state); 8688 } 8689 8690 static int 8691 intel_atomic_commit_ready(struct i915_sw_fence *fence, 8692 enum i915_sw_fence_notify notify) 8693 { 8694 struct intel_atomic_state *state = 8695 container_of(fence, struct intel_atomic_state, commit_ready); 8696 8697 switch (notify) { 8698 case FENCE_COMPLETE: 8699 /* we do blocking waits in the worker, nothing to do here */ 8700 break; 8701 case FENCE_FREE: 8702 { 8703 struct intel_atomic_helper *helper = 8704 &to_i915(state->base.dev)->atomic_helper; 8705 8706 if (llist_add(&state->freed, &helper->free_list)) 8707 schedule_work(&helper->free_work); 8708 break; 8709 } 8710 } 8711 8712 return NOTIFY_DONE; 8713 } 8714 8715 static void intel_atomic_track_fbs(struct intel_atomic_state *state) 8716 { 8717 struct intel_plane_state *old_plane_state, *new_plane_state; 8718 struct intel_plane *plane; 8719 int i; 8720 8721 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 8722 new_plane_state, i) 8723 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), 8724 to_intel_frontbuffer(new_plane_state->hw.fb), 8725 plane->frontbuffer_bit); 8726 } 8727 8728 static int intel_atomic_commit(struct drm_device *dev, 8729 struct drm_atomic_state *_state, 8730 bool nonblock) 8731 { 8732 struct intel_atomic_state *state = to_intel_atomic_state(_state); 8733 struct drm_i915_private *dev_priv = to_i915(dev); 8734 int ret = 0; 8735 8736 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 8737 8738 drm_atomic_state_get(&state->base); 8739 i915_sw_fence_init(&state->commit_ready, 8740 intel_atomic_commit_ready); 8741 8742 /* 8743 * The intel_legacy_cursor_update() fast path takes care 8744 * of avoiding the vblank waits for simple cursor 8745 * movement and flips. For cursor on/off and size changes, 8746 * we want to perform the vblank waits so that watermark 8747 * updates happen during the correct frames. Gen9+ have 8748 * double buffered watermarks and so shouldn't need this. 8749 * 8750 * Unset state->legacy_cursor_update before the call to 8751 * drm_atomic_helper_setup_commit() because otherwise 8752 * drm_atomic_helper_wait_for_flip_done() is a noop and 8753 * we get FIFO underruns because we didn't wait 8754 * for vblank. 8755 * 8756 * FIXME doing watermarks and fb cleanup from a vblank worker 8757 * (assuming we had any) would solve these problems. 8758 */ 8759 if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) { 8760 struct intel_crtc_state *new_crtc_state; 8761 struct intel_crtc *crtc; 8762 int i; 8763 8764 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 8765 if (new_crtc_state->wm.need_postvbl_update || 8766 new_crtc_state->update_wm_post) 8767 state->base.legacy_cursor_update = false; 8768 } 8769 8770 ret = intel_atomic_prepare_commit(state); 8771 if (ret) { 8772 drm_dbg_atomic(&dev_priv->drm, 8773 "Preparing state failed with %i\n", ret); 8774 i915_sw_fence_commit(&state->commit_ready); 8775 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 8776 return ret; 8777 } 8778 8779 ret = drm_atomic_helper_setup_commit(&state->base, nonblock); 8780 if (!ret) 8781 ret = drm_atomic_helper_swap_state(&state->base, true); 8782 if (!ret) 8783 intel_atomic_swap_global_state(state); 8784 8785 if (ret) { 8786 struct intel_crtc_state *new_crtc_state; 8787 struct intel_crtc *crtc; 8788 int i; 8789 8790 i915_sw_fence_commit(&state->commit_ready); 8791 8792 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 8793 intel_dsb_cleanup(new_crtc_state); 8794 8795 drm_atomic_helper_cleanup_planes(dev, &state->base); 8796 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 8797 return ret; 8798 } 8799 intel_shared_dpll_swap_state(state); 8800 intel_atomic_track_fbs(state); 8801 8802 drm_atomic_state_get(&state->base); 8803 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work); 8804 8805 i915_sw_fence_commit(&state->commit_ready); 8806 if (nonblock && state->modeset) { 8807 queue_work(dev_priv->modeset_wq, &state->base.commit_work); 8808 } else if (nonblock) { 8809 queue_work(dev_priv->flip_wq, &state->base.commit_work); 8810 } else { 8811 if (state->modeset) 8812 flush_workqueue(dev_priv->modeset_wq); 8813 intel_atomic_commit_tail(state); 8814 } 8815 8816 return 0; 8817 } 8818 8819 /** 8820 * intel_plane_destroy - destroy a plane 8821 * @plane: plane to destroy 8822 * 8823 * Common destruction function for all types of planes (primary, cursor, 8824 * sprite). 8825 */ 8826 void intel_plane_destroy(struct drm_plane *plane) 8827 { 8828 drm_plane_cleanup(plane); 8829 kfree(to_intel_plane(plane)); 8830 } 8831 8832 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv) 8833 { 8834 struct intel_plane *plane; 8835 8836 for_each_intel_plane(&dev_priv->drm, plane) { 8837 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, 8838 plane->pipe); 8839 8840 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base); 8841 } 8842 } 8843 8844 8845 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 8846 struct drm_file *file) 8847 { 8848 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; 8849 struct drm_crtc *drmmode_crtc; 8850 struct intel_crtc *crtc; 8851 8852 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id); 8853 if (!drmmode_crtc) 8854 return -ENOENT; 8855 8856 crtc = to_intel_crtc(drmmode_crtc); 8857 pipe_from_crtc_id->pipe = crtc->pipe; 8858 8859 return 0; 8860 } 8861 8862 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder) 8863 { 8864 struct drm_device *dev = encoder->base.dev; 8865 struct intel_encoder *source_encoder; 8866 u32 possible_clones = 0; 8867 8868 for_each_intel_encoder(dev, source_encoder) { 8869 if (encoders_cloneable(encoder, source_encoder)) 8870 possible_clones |= drm_encoder_mask(&source_encoder->base); 8871 } 8872 8873 return possible_clones; 8874 } 8875 8876 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder) 8877 { 8878 struct drm_device *dev = encoder->base.dev; 8879 struct intel_crtc *crtc; 8880 u32 possible_crtcs = 0; 8881 8882 for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask) 8883 possible_crtcs |= drm_crtc_mask(&crtc->base); 8884 8885 return possible_crtcs; 8886 } 8887 8888 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv) 8889 { 8890 if (!IS_MOBILE(dev_priv)) 8891 return false; 8892 8893 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0) 8894 return false; 8895 8896 if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE)) 8897 return false; 8898 8899 return true; 8900 } 8901 8902 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv) 8903 { 8904 if (DISPLAY_VER(dev_priv) >= 9) 8905 return false; 8906 8907 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) 8908 return false; 8909 8910 if (HAS_PCH_LPT_H(dev_priv) && 8911 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) 8912 return false; 8913 8914 /* DDI E can't be used if DDI A requires 4 lanes */ 8915 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 8916 return false; 8917 8918 if (!dev_priv->vbt.int_crt_support) 8919 return false; 8920 8921 return true; 8922 } 8923 8924 static void intel_setup_outputs(struct drm_i915_private *dev_priv) 8925 { 8926 struct intel_encoder *encoder; 8927 bool dpd_is_edp = false; 8928 8929 intel_pps_unlock_regs_wa(dev_priv); 8930 8931 if (!HAS_DISPLAY(dev_priv)) 8932 return; 8933 8934 if (IS_DG2(dev_priv)) { 8935 intel_ddi_init(dev_priv, PORT_A); 8936 intel_ddi_init(dev_priv, PORT_B); 8937 intel_ddi_init(dev_priv, PORT_C); 8938 intel_ddi_init(dev_priv, PORT_D_XELPD); 8939 intel_ddi_init(dev_priv, PORT_TC1); 8940 } else if (IS_ALDERLAKE_P(dev_priv)) { 8941 intel_ddi_init(dev_priv, PORT_A); 8942 intel_ddi_init(dev_priv, PORT_B); 8943 intel_ddi_init(dev_priv, PORT_TC1); 8944 intel_ddi_init(dev_priv, PORT_TC2); 8945 intel_ddi_init(dev_priv, PORT_TC3); 8946 intel_ddi_init(dev_priv, PORT_TC4); 8947 icl_dsi_init(dev_priv); 8948 } else if (IS_ALDERLAKE_S(dev_priv)) { 8949 intel_ddi_init(dev_priv, PORT_A); 8950 intel_ddi_init(dev_priv, PORT_TC1); 8951 intel_ddi_init(dev_priv, PORT_TC2); 8952 intel_ddi_init(dev_priv, PORT_TC3); 8953 intel_ddi_init(dev_priv, PORT_TC4); 8954 } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) { 8955 intel_ddi_init(dev_priv, PORT_A); 8956 intel_ddi_init(dev_priv, PORT_B); 8957 intel_ddi_init(dev_priv, PORT_TC1); 8958 intel_ddi_init(dev_priv, PORT_TC2); 8959 } else if (DISPLAY_VER(dev_priv) >= 12) { 8960 intel_ddi_init(dev_priv, PORT_A); 8961 intel_ddi_init(dev_priv, PORT_B); 8962 intel_ddi_init(dev_priv, PORT_TC1); 8963 intel_ddi_init(dev_priv, PORT_TC2); 8964 intel_ddi_init(dev_priv, PORT_TC3); 8965 intel_ddi_init(dev_priv, PORT_TC4); 8966 intel_ddi_init(dev_priv, PORT_TC5); 8967 intel_ddi_init(dev_priv, PORT_TC6); 8968 icl_dsi_init(dev_priv); 8969 } else if (IS_JSL_EHL(dev_priv)) { 8970 intel_ddi_init(dev_priv, PORT_A); 8971 intel_ddi_init(dev_priv, PORT_B); 8972 intel_ddi_init(dev_priv, PORT_C); 8973 intel_ddi_init(dev_priv, PORT_D); 8974 icl_dsi_init(dev_priv); 8975 } else if (DISPLAY_VER(dev_priv) == 11) { 8976 intel_ddi_init(dev_priv, PORT_A); 8977 intel_ddi_init(dev_priv, PORT_B); 8978 intel_ddi_init(dev_priv, PORT_C); 8979 intel_ddi_init(dev_priv, PORT_D); 8980 intel_ddi_init(dev_priv, PORT_E); 8981 intel_ddi_init(dev_priv, PORT_F); 8982 icl_dsi_init(dev_priv); 8983 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 8984 intel_ddi_init(dev_priv, PORT_A); 8985 intel_ddi_init(dev_priv, PORT_B); 8986 intel_ddi_init(dev_priv, PORT_C); 8987 vlv_dsi_init(dev_priv); 8988 } else if (DISPLAY_VER(dev_priv) >= 9) { 8989 intel_ddi_init(dev_priv, PORT_A); 8990 intel_ddi_init(dev_priv, PORT_B); 8991 intel_ddi_init(dev_priv, PORT_C); 8992 intel_ddi_init(dev_priv, PORT_D); 8993 intel_ddi_init(dev_priv, PORT_E); 8994 } else if (HAS_DDI(dev_priv)) { 8995 u32 found; 8996 8997 if (intel_ddi_crt_present(dev_priv)) 8998 intel_crt_init(dev_priv); 8999 9000 /* Haswell uses DDI functions to detect digital outputs. */ 9001 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 9002 if (found) 9003 intel_ddi_init(dev_priv, PORT_A); 9004 9005 found = intel_de_read(dev_priv, SFUSE_STRAP); 9006 if (found & SFUSE_STRAP_DDIB_DETECTED) 9007 intel_ddi_init(dev_priv, PORT_B); 9008 if (found & SFUSE_STRAP_DDIC_DETECTED) 9009 intel_ddi_init(dev_priv, PORT_C); 9010 if (found & SFUSE_STRAP_DDID_DETECTED) 9011 intel_ddi_init(dev_priv, PORT_D); 9012 if (found & SFUSE_STRAP_DDIF_DETECTED) 9013 intel_ddi_init(dev_priv, PORT_F); 9014 } else if (HAS_PCH_SPLIT(dev_priv)) { 9015 int found; 9016 9017 /* 9018 * intel_edp_init_connector() depends on this completing first, 9019 * to prevent the registration of both eDP and LVDS and the 9020 * incorrect sharing of the PPS. 9021 */ 9022 intel_lvds_init(dev_priv); 9023 intel_crt_init(dev_priv); 9024 9025 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D); 9026 9027 if (ilk_has_edp_a(dev_priv)) 9028 g4x_dp_init(dev_priv, DP_A, PORT_A); 9029 9030 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) { 9031 /* PCH SDVOB multiplex with HDMIB */ 9032 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); 9033 if (!found) 9034 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); 9035 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED)) 9036 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B); 9037 } 9038 9039 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED) 9040 g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); 9041 9042 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED) 9043 g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D); 9044 9045 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED) 9046 g4x_dp_init(dev_priv, PCH_DP_C, PORT_C); 9047 9048 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED) 9049 g4x_dp_init(dev_priv, PCH_DP_D, PORT_D); 9050 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 9051 bool has_edp, has_port; 9052 9053 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support) 9054 intel_crt_init(dev_priv); 9055 9056 /* 9057 * The DP_DETECTED bit is the latched state of the DDC 9058 * SDA pin at boot. However since eDP doesn't require DDC 9059 * (no way to plug in a DP->HDMI dongle) the DDC pins for 9060 * eDP ports may have been muxed to an alternate function. 9061 * Thus we can't rely on the DP_DETECTED bit alone to detect 9062 * eDP ports. Consult the VBT as well as DP_DETECTED to 9063 * detect eDP ports. 9064 * 9065 * Sadly the straps seem to be missing sometimes even for HDMI 9066 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap 9067 * and VBT for the presence of the port. Additionally we can't 9068 * trust the port type the VBT declares as we've seen at least 9069 * HDMI ports that the VBT claim are DP or eDP. 9070 */ 9071 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B); 9072 has_port = intel_bios_is_port_present(dev_priv, PORT_B); 9073 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port) 9074 has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B); 9075 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) 9076 g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); 9077 9078 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C); 9079 has_port = intel_bios_is_port_present(dev_priv, PORT_C); 9080 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port) 9081 has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C); 9082 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) 9083 g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); 9084 9085 if (IS_CHERRYVIEW(dev_priv)) { 9086 /* 9087 * eDP not supported on port D, 9088 * so no need to worry about it 9089 */ 9090 has_port = intel_bios_is_port_present(dev_priv, PORT_D); 9091 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port) 9092 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D); 9093 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port) 9094 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D); 9095 } 9096 9097 vlv_dsi_init(dev_priv); 9098 } else if (IS_PINEVIEW(dev_priv)) { 9099 intel_lvds_init(dev_priv); 9100 intel_crt_init(dev_priv); 9101 } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) { 9102 bool found = false; 9103 9104 if (IS_MOBILE(dev_priv)) 9105 intel_lvds_init(dev_priv); 9106 9107 intel_crt_init(dev_priv); 9108 9109 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 9110 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n"); 9111 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); 9112 if (!found && IS_G4X(dev_priv)) { 9113 drm_dbg_kms(&dev_priv->drm, 9114 "probing HDMI on SDVOB\n"); 9115 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); 9116 } 9117 9118 if (!found && IS_G4X(dev_priv)) 9119 g4x_dp_init(dev_priv, DP_B, PORT_B); 9120 } 9121 9122 /* Before G4X SDVOC doesn't have its own detect register */ 9123 9124 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 9125 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n"); 9126 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); 9127 } 9128 9129 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) { 9130 9131 if (IS_G4X(dev_priv)) { 9132 drm_dbg_kms(&dev_priv->drm, 9133 "probing HDMI on SDVOC\n"); 9134 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); 9135 } 9136 if (IS_G4X(dev_priv)) 9137 g4x_dp_init(dev_priv, DP_C, PORT_C); 9138 } 9139 9140 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED)) 9141 g4x_dp_init(dev_priv, DP_D, PORT_D); 9142 9143 if (SUPPORTS_TV(dev_priv)) 9144 intel_tv_init(dev_priv); 9145 } else if (DISPLAY_VER(dev_priv) == 2) { 9146 if (IS_I85X(dev_priv)) 9147 intel_lvds_init(dev_priv); 9148 9149 intel_crt_init(dev_priv); 9150 intel_dvo_init(dev_priv); 9151 } 9152 9153 for_each_intel_encoder(&dev_priv->drm, encoder) { 9154 encoder->base.possible_crtcs = 9155 intel_encoder_possible_crtcs(encoder); 9156 encoder->base.possible_clones = 9157 intel_encoder_possible_clones(encoder); 9158 } 9159 9160 intel_init_pch_refclk(dev_priv); 9161 9162 drm_helper_move_panel_connectors_to_head(&dev_priv->drm); 9163 } 9164 9165 static enum drm_mode_status 9166 intel_mode_valid(struct drm_device *dev, 9167 const struct drm_display_mode *mode) 9168 { 9169 struct drm_i915_private *dev_priv = to_i915(dev); 9170 int hdisplay_max, htotal_max; 9171 int vdisplay_max, vtotal_max; 9172 9173 /* 9174 * Can't reject DBLSCAN here because Xorg ddxen can add piles 9175 * of DBLSCAN modes to the output's mode list when they detect 9176 * the scaling mode property on the connector. And they don't 9177 * ask the kernel to validate those modes in any way until 9178 * modeset time at which point the client gets a protocol error. 9179 * So in order to not upset those clients we silently ignore the 9180 * DBLSCAN flag on such connectors. For other connectors we will 9181 * reject modes with the DBLSCAN flag in encoder->compute_config(). 9182 * And we always reject DBLSCAN modes in connector->mode_valid() 9183 * as we never want such modes on the connector's mode list. 9184 */ 9185 9186 if (mode->vscan > 1) 9187 return MODE_NO_VSCAN; 9188 9189 if (mode->flags & DRM_MODE_FLAG_HSKEW) 9190 return MODE_H_ILLEGAL; 9191 9192 if (mode->flags & (DRM_MODE_FLAG_CSYNC | 9193 DRM_MODE_FLAG_NCSYNC | 9194 DRM_MODE_FLAG_PCSYNC)) 9195 return MODE_HSYNC; 9196 9197 if (mode->flags & (DRM_MODE_FLAG_BCAST | 9198 DRM_MODE_FLAG_PIXMUX | 9199 DRM_MODE_FLAG_CLKDIV2)) 9200 return MODE_BAD; 9201 9202 /* Transcoder timing limits */ 9203 if (DISPLAY_VER(dev_priv) >= 11) { 9204 hdisplay_max = 16384; 9205 vdisplay_max = 8192; 9206 htotal_max = 16384; 9207 vtotal_max = 8192; 9208 } else if (DISPLAY_VER(dev_priv) >= 9 || 9209 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 9210 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ 9211 vdisplay_max = 4096; 9212 htotal_max = 8192; 9213 vtotal_max = 8192; 9214 } else if (DISPLAY_VER(dev_priv) >= 3) { 9215 hdisplay_max = 4096; 9216 vdisplay_max = 4096; 9217 htotal_max = 8192; 9218 vtotal_max = 8192; 9219 } else { 9220 hdisplay_max = 2048; 9221 vdisplay_max = 2048; 9222 htotal_max = 4096; 9223 vtotal_max = 4096; 9224 } 9225 9226 if (mode->hdisplay > hdisplay_max || 9227 mode->hsync_start > htotal_max || 9228 mode->hsync_end > htotal_max || 9229 mode->htotal > htotal_max) 9230 return MODE_H_ILLEGAL; 9231 9232 if (mode->vdisplay > vdisplay_max || 9233 mode->vsync_start > vtotal_max || 9234 mode->vsync_end > vtotal_max || 9235 mode->vtotal > vtotal_max) 9236 return MODE_V_ILLEGAL; 9237 9238 if (DISPLAY_VER(dev_priv) >= 5) { 9239 if (mode->hdisplay < 64 || 9240 mode->htotal - mode->hdisplay < 32) 9241 return MODE_H_ILLEGAL; 9242 9243 if (mode->vtotal - mode->vdisplay < 5) 9244 return MODE_V_ILLEGAL; 9245 } else { 9246 if (mode->htotal - mode->hdisplay < 32) 9247 return MODE_H_ILLEGAL; 9248 9249 if (mode->vtotal - mode->vdisplay < 3) 9250 return MODE_V_ILLEGAL; 9251 } 9252 9253 /* 9254 * Cantiga+ cannot handle modes with a hsync front porch of 0. 9255 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. 9256 */ 9257 if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) && 9258 mode->hsync_start == mode->hdisplay) 9259 return MODE_H_ILLEGAL; 9260 9261 return MODE_OK; 9262 } 9263 9264 enum drm_mode_status 9265 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 9266 const struct drm_display_mode *mode, 9267 bool bigjoiner) 9268 { 9269 int plane_width_max, plane_height_max; 9270 9271 /* 9272 * intel_mode_valid() should be 9273 * sufficient on older platforms. 9274 */ 9275 if (DISPLAY_VER(dev_priv) < 9) 9276 return MODE_OK; 9277 9278 /* 9279 * Most people will probably want a fullscreen 9280 * plane so let's not advertize modes that are 9281 * too big for that. 9282 */ 9283 if (DISPLAY_VER(dev_priv) >= 11) { 9284 plane_width_max = 5120 << bigjoiner; 9285 plane_height_max = 4320; 9286 } else { 9287 plane_width_max = 5120; 9288 plane_height_max = 4096; 9289 } 9290 9291 if (mode->hdisplay > plane_width_max) 9292 return MODE_H_ILLEGAL; 9293 9294 if (mode->vdisplay > plane_height_max) 9295 return MODE_V_ILLEGAL; 9296 9297 return MODE_OK; 9298 } 9299 9300 static const struct drm_mode_config_funcs intel_mode_funcs = { 9301 .fb_create = intel_user_framebuffer_create, 9302 .get_format_info = intel_fb_get_format_info, 9303 .output_poll_changed = intel_fbdev_output_poll_changed, 9304 .mode_valid = intel_mode_valid, 9305 .atomic_check = intel_atomic_check, 9306 .atomic_commit = intel_atomic_commit, 9307 .atomic_state_alloc = intel_atomic_state_alloc, 9308 .atomic_state_clear = intel_atomic_state_clear, 9309 .atomic_state_free = intel_atomic_state_free, 9310 }; 9311 9312 static const struct drm_i915_display_funcs skl_display_funcs = { 9313 .get_pipe_config = hsw_get_pipe_config, 9314 .crtc_enable = hsw_crtc_enable, 9315 .crtc_disable = hsw_crtc_disable, 9316 .commit_modeset_enables = skl_commit_modeset_enables, 9317 .get_initial_plane_config = skl_get_initial_plane_config, 9318 }; 9319 9320 static const struct drm_i915_display_funcs ddi_display_funcs = { 9321 .get_pipe_config = hsw_get_pipe_config, 9322 .crtc_enable = hsw_crtc_enable, 9323 .crtc_disable = hsw_crtc_disable, 9324 .commit_modeset_enables = intel_commit_modeset_enables, 9325 .get_initial_plane_config = i9xx_get_initial_plane_config, 9326 }; 9327 9328 static const struct drm_i915_display_funcs pch_split_display_funcs = { 9329 .get_pipe_config = ilk_get_pipe_config, 9330 .crtc_enable = ilk_crtc_enable, 9331 .crtc_disable = ilk_crtc_disable, 9332 .commit_modeset_enables = intel_commit_modeset_enables, 9333 .get_initial_plane_config = i9xx_get_initial_plane_config, 9334 }; 9335 9336 static const struct drm_i915_display_funcs vlv_display_funcs = { 9337 .get_pipe_config = i9xx_get_pipe_config, 9338 .crtc_enable = valleyview_crtc_enable, 9339 .crtc_disable = i9xx_crtc_disable, 9340 .commit_modeset_enables = intel_commit_modeset_enables, 9341 .get_initial_plane_config = i9xx_get_initial_plane_config, 9342 }; 9343 9344 static const struct drm_i915_display_funcs i9xx_display_funcs = { 9345 .get_pipe_config = i9xx_get_pipe_config, 9346 .crtc_enable = i9xx_crtc_enable, 9347 .crtc_disable = i9xx_crtc_disable, 9348 .commit_modeset_enables = intel_commit_modeset_enables, 9349 .get_initial_plane_config = i9xx_get_initial_plane_config, 9350 }; 9351 9352 /** 9353 * intel_init_display_hooks - initialize the display modesetting hooks 9354 * @dev_priv: device private 9355 */ 9356 void intel_init_display_hooks(struct drm_i915_private *dev_priv) 9357 { 9358 if (!HAS_DISPLAY(dev_priv)) 9359 return; 9360 9361 intel_init_cdclk_hooks(dev_priv); 9362 intel_audio_hooks_init(dev_priv); 9363 9364 intel_dpll_init_clock_hook(dev_priv); 9365 9366 if (DISPLAY_VER(dev_priv) >= 9) { 9367 dev_priv->display = &skl_display_funcs; 9368 } else if (HAS_DDI(dev_priv)) { 9369 dev_priv->display = &ddi_display_funcs; 9370 } else if (HAS_PCH_SPLIT(dev_priv)) { 9371 dev_priv->display = &pch_split_display_funcs; 9372 } else if (IS_CHERRYVIEW(dev_priv) || 9373 IS_VALLEYVIEW(dev_priv)) { 9374 dev_priv->display = &vlv_display_funcs; 9375 } else { 9376 dev_priv->display = &i9xx_display_funcs; 9377 } 9378 9379 intel_fdi_init_hook(dev_priv); 9380 } 9381 9382 void intel_modeset_init_hw(struct drm_i915_private *i915) 9383 { 9384 struct intel_cdclk_state *cdclk_state; 9385 9386 if (!HAS_DISPLAY(i915)) 9387 return; 9388 9389 cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state); 9390 9391 intel_update_cdclk(i915); 9392 intel_cdclk_dump_config(i915, &i915->cdclk.hw, "Current CDCLK"); 9393 cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw; 9394 } 9395 9396 static int sanitize_watermarks_add_affected(struct drm_atomic_state *state) 9397 { 9398 struct drm_plane *plane; 9399 struct intel_crtc *crtc; 9400 9401 for_each_intel_crtc(state->dev, crtc) { 9402 struct intel_crtc_state *crtc_state; 9403 9404 crtc_state = intel_atomic_get_crtc_state(state, crtc); 9405 if (IS_ERR(crtc_state)) 9406 return PTR_ERR(crtc_state); 9407 9408 if (crtc_state->hw.active) { 9409 /* 9410 * Preserve the inherited flag to avoid 9411 * taking the full modeset path. 9412 */ 9413 crtc_state->inherited = true; 9414 } 9415 } 9416 9417 drm_for_each_plane(plane, state->dev) { 9418 struct drm_plane_state *plane_state; 9419 9420 plane_state = drm_atomic_get_plane_state(state, plane); 9421 if (IS_ERR(plane_state)) 9422 return PTR_ERR(plane_state); 9423 } 9424 9425 return 0; 9426 } 9427 9428 /* 9429 * Calculate what we think the watermarks should be for the state we've read 9430 * out of the hardware and then immediately program those watermarks so that 9431 * we ensure the hardware settings match our internal state. 9432 * 9433 * We can calculate what we think WM's should be by creating a duplicate of the 9434 * current state (which was constructed during hardware readout) and running it 9435 * through the atomic check code to calculate new watermark values in the 9436 * state object. 9437 */ 9438 static void sanitize_watermarks(struct drm_i915_private *dev_priv) 9439 { 9440 struct drm_atomic_state *state; 9441 struct intel_atomic_state *intel_state; 9442 struct intel_crtc *crtc; 9443 struct intel_crtc_state *crtc_state; 9444 struct drm_modeset_acquire_ctx ctx; 9445 int ret; 9446 int i; 9447 9448 /* Only supported on platforms that use atomic watermark design */ 9449 if (!dev_priv->wm_disp->optimize_watermarks) 9450 return; 9451 9452 state = drm_atomic_state_alloc(&dev_priv->drm); 9453 if (drm_WARN_ON(&dev_priv->drm, !state)) 9454 return; 9455 9456 intel_state = to_intel_atomic_state(state); 9457 9458 drm_modeset_acquire_init(&ctx, 0); 9459 9460 retry: 9461 state->acquire_ctx = &ctx; 9462 9463 /* 9464 * Hardware readout is the only time we don't want to calculate 9465 * intermediate watermarks (since we don't trust the current 9466 * watermarks). 9467 */ 9468 if (!HAS_GMCH(dev_priv)) 9469 intel_state->skip_intermediate_wm = true; 9470 9471 ret = sanitize_watermarks_add_affected(state); 9472 if (ret) 9473 goto fail; 9474 9475 ret = intel_atomic_check(&dev_priv->drm, state); 9476 if (ret) 9477 goto fail; 9478 9479 /* Write calculated watermark values back */ 9480 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) { 9481 crtc_state->wm.need_postvbl_update = true; 9482 intel_optimize_watermarks(intel_state, crtc); 9483 9484 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm; 9485 } 9486 9487 fail: 9488 if (ret == -EDEADLK) { 9489 drm_atomic_state_clear(state); 9490 drm_modeset_backoff(&ctx); 9491 goto retry; 9492 } 9493 9494 /* 9495 * If we fail here, it means that the hardware appears to be 9496 * programmed in a way that shouldn't be possible, given our 9497 * understanding of watermark requirements. This might mean a 9498 * mistake in the hardware readout code or a mistake in the 9499 * watermark calculations for a given platform. Raise a WARN 9500 * so that this is noticeable. 9501 * 9502 * If this actually happens, we'll have to just leave the 9503 * BIOS-programmed watermarks untouched and hope for the best. 9504 */ 9505 drm_WARN(&dev_priv->drm, ret, 9506 "Could not determine valid watermarks for inherited state\n"); 9507 9508 drm_atomic_state_put(state); 9509 9510 drm_modeset_drop_locks(&ctx); 9511 drm_modeset_acquire_fini(&ctx); 9512 } 9513 9514 static int intel_initial_commit(struct drm_device *dev) 9515 { 9516 struct drm_atomic_state *state = NULL; 9517 struct drm_modeset_acquire_ctx ctx; 9518 struct intel_crtc *crtc; 9519 int ret = 0; 9520 9521 state = drm_atomic_state_alloc(dev); 9522 if (!state) 9523 return -ENOMEM; 9524 9525 drm_modeset_acquire_init(&ctx, 0); 9526 9527 retry: 9528 state->acquire_ctx = &ctx; 9529 9530 for_each_intel_crtc(dev, crtc) { 9531 struct intel_crtc_state *crtc_state = 9532 intel_atomic_get_crtc_state(state, crtc); 9533 9534 if (IS_ERR(crtc_state)) { 9535 ret = PTR_ERR(crtc_state); 9536 goto out; 9537 } 9538 9539 if (crtc_state->hw.active) { 9540 struct intel_encoder *encoder; 9541 9542 /* 9543 * We've not yet detected sink capabilities 9544 * (audio,infoframes,etc.) and thus we don't want to 9545 * force a full state recomputation yet. We want that to 9546 * happen only for the first real commit from userspace. 9547 * So preserve the inherited flag for the time being. 9548 */ 9549 crtc_state->inherited = true; 9550 9551 ret = drm_atomic_add_affected_planes(state, &crtc->base); 9552 if (ret) 9553 goto out; 9554 9555 /* 9556 * FIXME hack to force a LUT update to avoid the 9557 * plane update forcing the pipe gamma on without 9558 * having a proper LUT loaded. Remove once we 9559 * have readout for pipe gamma enable. 9560 */ 9561 crtc_state->uapi.color_mgmt_changed = true; 9562 9563 for_each_intel_encoder_mask(dev, encoder, 9564 crtc_state->uapi.encoder_mask) { 9565 if (encoder->initial_fastset_check && 9566 !encoder->initial_fastset_check(encoder, crtc_state)) { 9567 ret = drm_atomic_add_affected_connectors(state, 9568 &crtc->base); 9569 if (ret) 9570 goto out; 9571 } 9572 } 9573 } 9574 } 9575 9576 ret = drm_atomic_commit(state); 9577 9578 out: 9579 if (ret == -EDEADLK) { 9580 drm_atomic_state_clear(state); 9581 drm_modeset_backoff(&ctx); 9582 goto retry; 9583 } 9584 9585 drm_atomic_state_put(state); 9586 9587 drm_modeset_drop_locks(&ctx); 9588 drm_modeset_acquire_fini(&ctx); 9589 9590 return ret; 9591 } 9592 9593 static void intel_mode_config_init(struct drm_i915_private *i915) 9594 { 9595 struct drm_mode_config *mode_config = &i915->drm.mode_config; 9596 9597 drm_mode_config_init(&i915->drm); 9598 INIT_LIST_HEAD(&i915->global_obj_list); 9599 9600 mode_config->min_width = 0; 9601 mode_config->min_height = 0; 9602 9603 mode_config->preferred_depth = 24; 9604 mode_config->prefer_shadow = 1; 9605 9606 mode_config->funcs = &intel_mode_funcs; 9607 9608 mode_config->async_page_flip = HAS_ASYNC_FLIPS(i915); 9609 9610 /* 9611 * Maximum framebuffer dimensions, chosen to match 9612 * the maximum render engine surface size on gen4+. 9613 */ 9614 if (DISPLAY_VER(i915) >= 7) { 9615 mode_config->max_width = 16384; 9616 mode_config->max_height = 16384; 9617 } else if (DISPLAY_VER(i915) >= 4) { 9618 mode_config->max_width = 8192; 9619 mode_config->max_height = 8192; 9620 } else if (DISPLAY_VER(i915) == 3) { 9621 mode_config->max_width = 4096; 9622 mode_config->max_height = 4096; 9623 } else { 9624 mode_config->max_width = 2048; 9625 mode_config->max_height = 2048; 9626 } 9627 9628 if (IS_I845G(i915) || IS_I865G(i915)) { 9629 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512; 9630 mode_config->cursor_height = 1023; 9631 } else if (IS_I830(i915) || IS_I85X(i915) || 9632 IS_I915G(i915) || IS_I915GM(i915)) { 9633 mode_config->cursor_width = 64; 9634 mode_config->cursor_height = 64; 9635 } else { 9636 mode_config->cursor_width = 256; 9637 mode_config->cursor_height = 256; 9638 } 9639 } 9640 9641 static void intel_mode_config_cleanup(struct drm_i915_private *i915) 9642 { 9643 intel_atomic_global_obj_cleanup(i915); 9644 drm_mode_config_cleanup(&i915->drm); 9645 } 9646 9647 /* part #1: call before irq install */ 9648 int intel_modeset_init_noirq(struct drm_i915_private *i915) 9649 { 9650 int ret; 9651 9652 if (i915_inject_probe_failure(i915)) 9653 return -ENODEV; 9654 9655 if (HAS_DISPLAY(i915)) { 9656 ret = drm_vblank_init(&i915->drm, 9657 INTEL_NUM_PIPES(i915)); 9658 if (ret) 9659 return ret; 9660 } 9661 9662 intel_bios_init(i915); 9663 9664 ret = intel_vga_register(i915); 9665 if (ret) 9666 goto cleanup_bios; 9667 9668 /* FIXME: completely on the wrong abstraction layer */ 9669 intel_power_domains_init_hw(i915, false); 9670 9671 if (!HAS_DISPLAY(i915)) 9672 return 0; 9673 9674 intel_dmc_ucode_init(i915); 9675 9676 i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0); 9677 i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI | 9678 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE); 9679 9680 i915->window2_delay = 0; /* No DSB so no window2 delay */ 9681 9682 intel_mode_config_init(i915); 9683 9684 ret = intel_cdclk_init(i915); 9685 if (ret) 9686 goto cleanup_vga_client_pw_domain_dmc; 9687 9688 ret = intel_dbuf_init(i915); 9689 if (ret) 9690 goto cleanup_vga_client_pw_domain_dmc; 9691 9692 ret = intel_bw_init(i915); 9693 if (ret) 9694 goto cleanup_vga_client_pw_domain_dmc; 9695 9696 init_llist_head(&i915->atomic_helper.free_list); 9697 INIT_WORK(&i915->atomic_helper.free_work, 9698 intel_atomic_helper_free_state_worker); 9699 9700 intel_init_quirks(i915); 9701 9702 intel_fbc_init(i915); 9703 9704 return 0; 9705 9706 cleanup_vga_client_pw_domain_dmc: 9707 intel_dmc_ucode_fini(i915); 9708 intel_power_domains_driver_remove(i915); 9709 intel_vga_unregister(i915); 9710 cleanup_bios: 9711 intel_bios_driver_remove(i915); 9712 9713 return ret; 9714 } 9715 9716 /* part #2: call after irq install, but before gem init */ 9717 int intel_modeset_init_nogem(struct drm_i915_private *i915) 9718 { 9719 struct drm_device *dev = &i915->drm; 9720 enum pipe pipe; 9721 struct intel_crtc *crtc; 9722 int ret; 9723 9724 if (!HAS_DISPLAY(i915)) 9725 return 0; 9726 9727 intel_init_pm(i915); 9728 9729 intel_panel_sanitize_ssc(i915); 9730 9731 intel_pps_setup(i915); 9732 9733 intel_gmbus_setup(i915); 9734 9735 drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n", 9736 INTEL_NUM_PIPES(i915), 9737 INTEL_NUM_PIPES(i915) > 1 ? "s" : ""); 9738 9739 for_each_pipe(i915, pipe) { 9740 ret = intel_crtc_init(i915, pipe); 9741 if (ret) { 9742 intel_mode_config_cleanup(i915); 9743 return ret; 9744 } 9745 } 9746 9747 intel_plane_possible_crtcs_init(i915); 9748 intel_shared_dpll_init(dev); 9749 intel_fdi_pll_freq_update(i915); 9750 9751 intel_update_czclk(i915); 9752 intel_modeset_init_hw(i915); 9753 intel_dpll_update_ref_clks(i915); 9754 9755 intel_hdcp_component_init(i915); 9756 9757 if (i915->max_cdclk_freq == 0) 9758 intel_update_max_cdclk(i915); 9759 9760 /* 9761 * If the platform has HTI, we need to find out whether it has reserved 9762 * any display resources before we create our display outputs. 9763 */ 9764 if (INTEL_INFO(i915)->display.has_hti) 9765 i915->hti_state = intel_de_read(i915, HDPORT_STATE); 9766 9767 /* Just disable it once at startup */ 9768 intel_vga_disable(i915); 9769 intel_setup_outputs(i915); 9770 9771 drm_modeset_lock_all(dev); 9772 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx); 9773 intel_acpi_assign_connector_fwnodes(i915); 9774 drm_modeset_unlock_all(dev); 9775 9776 for_each_intel_crtc(dev, crtc) { 9777 if (!to_intel_crtc_state(crtc->base.state)->uapi.active) 9778 continue; 9779 intel_crtc_initial_plane_config(crtc); 9780 } 9781 9782 /* 9783 * Make sure hardware watermarks really match the state we read out. 9784 * Note that we need to do this after reconstructing the BIOS fb's 9785 * since the watermark calculation done here will use pstate->fb. 9786 */ 9787 if (!HAS_GMCH(i915)) 9788 sanitize_watermarks(i915); 9789 9790 return 0; 9791 } 9792 9793 /* part #3: call after gem init */ 9794 int intel_modeset_init(struct drm_i915_private *i915) 9795 { 9796 int ret; 9797 9798 if (!HAS_DISPLAY(i915)) 9799 return 0; 9800 9801 /* 9802 * Force all active planes to recompute their states. So that on 9803 * mode_setcrtc after probe, all the intel_plane_state variables 9804 * are already calculated and there is no assert_plane warnings 9805 * during bootup. 9806 */ 9807 ret = intel_initial_commit(&i915->drm); 9808 if (ret) 9809 drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret); 9810 9811 intel_overlay_setup(i915); 9812 9813 ret = intel_fbdev_init(&i915->drm); 9814 if (ret) 9815 return ret; 9816 9817 /* Only enable hotplug handling once the fbdev is fully set up. */ 9818 intel_hpd_init(i915); 9819 intel_hpd_poll_disable(i915); 9820 9821 intel_init_ipc(i915); 9822 9823 return 0; 9824 } 9825 9826 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 9827 { 9828 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 9829 /* 640x480@60Hz, ~25175 kHz */ 9830 struct dpll clock = { 9831 .m1 = 18, 9832 .m2 = 7, 9833 .p1 = 13, 9834 .p2 = 4, 9835 .n = 2, 9836 }; 9837 u32 dpll, fp; 9838 int i; 9839 9840 drm_WARN_ON(&dev_priv->drm, 9841 i9xx_calc_dpll_params(48000, &clock) != 25154); 9842 9843 drm_dbg_kms(&dev_priv->drm, 9844 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n", 9845 pipe_name(pipe), clock.vco, clock.dot); 9846 9847 fp = i9xx_dpll_compute_fp(&clock); 9848 dpll = DPLL_DVO_2X_MODE | 9849 DPLL_VGA_MODE_DIS | 9850 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | 9851 PLL_P2_DIVIDE_BY_4 | 9852 PLL_REF_INPUT_DREFCLK | 9853 DPLL_VCO_ENABLE; 9854 9855 intel_de_write(dev_priv, FP0(pipe), fp); 9856 intel_de_write(dev_priv, FP1(pipe), fp); 9857 9858 intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16)); 9859 intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16)); 9860 intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16)); 9861 intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16)); 9862 intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16)); 9863 intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16)); 9864 intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1)); 9865 9866 /* 9867 * Apparently we need to have VGA mode enabled prior to changing 9868 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 9869 * dividers, even though the register value does change. 9870 */ 9871 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); 9872 intel_de_write(dev_priv, DPLL(pipe), dpll); 9873 9874 /* Wait for the clocks to stabilize. */ 9875 intel_de_posting_read(dev_priv, DPLL(pipe)); 9876 udelay(150); 9877 9878 /* The pixel multiplier can only be updated once the 9879 * DPLL is enabled and the clocks are stable. 9880 * 9881 * So write it again. 9882 */ 9883 intel_de_write(dev_priv, DPLL(pipe), dpll); 9884 9885 /* We do this three times for luck */ 9886 for (i = 0; i < 3 ; i++) { 9887 intel_de_write(dev_priv, DPLL(pipe), dpll); 9888 intel_de_posting_read(dev_priv, DPLL(pipe)); 9889 udelay(150); /* wait for warmup */ 9890 } 9891 9892 intel_de_write(dev_priv, PIPECONF(pipe), PIPECONF_ENABLE); 9893 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 9894 9895 intel_wait_for_pipe_scanline_moving(crtc); 9896 } 9897 9898 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 9899 { 9900 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 9901 9902 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n", 9903 pipe_name(pipe)); 9904 9905 drm_WARN_ON(&dev_priv->drm, 9906 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE); 9907 drm_WARN_ON(&dev_priv->drm, 9908 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE); 9909 drm_WARN_ON(&dev_priv->drm, 9910 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE); 9911 drm_WARN_ON(&dev_priv->drm, 9912 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK); 9913 drm_WARN_ON(&dev_priv->drm, 9914 intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK); 9915 9916 intel_de_write(dev_priv, PIPECONF(pipe), 0); 9917 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 9918 9919 intel_wait_for_pipe_scanline_stopped(crtc); 9920 9921 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); 9922 intel_de_posting_read(dev_priv, DPLL(pipe)); 9923 } 9924 9925 static void 9926 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv) 9927 { 9928 struct intel_crtc *crtc; 9929 9930 if (DISPLAY_VER(dev_priv) >= 4) 9931 return; 9932 9933 for_each_intel_crtc(&dev_priv->drm, crtc) { 9934 struct intel_plane *plane = 9935 to_intel_plane(crtc->base.primary); 9936 struct intel_crtc *plane_crtc; 9937 enum pipe pipe; 9938 9939 if (!plane->get_hw_state(plane, &pipe)) 9940 continue; 9941 9942 if (pipe == crtc->pipe) 9943 continue; 9944 9945 drm_dbg_kms(&dev_priv->drm, 9946 "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n", 9947 plane->base.base.id, plane->base.name); 9948 9949 plane_crtc = intel_crtc_for_pipe(dev_priv, pipe); 9950 intel_plane_disable_noatomic(plane_crtc, plane); 9951 } 9952 } 9953 9954 static bool intel_crtc_has_encoders(struct intel_crtc *crtc) 9955 { 9956 struct drm_device *dev = crtc->base.dev; 9957 struct intel_encoder *encoder; 9958 9959 for_each_encoder_on_crtc(dev, &crtc->base, encoder) 9960 return true; 9961 9962 return false; 9963 } 9964 9965 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) 9966 { 9967 struct drm_device *dev = encoder->base.dev; 9968 struct intel_connector *connector; 9969 9970 for_each_connector_on_encoder(dev, &encoder->base, connector) 9971 return connector; 9972 9973 return NULL; 9974 } 9975 9976 static void intel_sanitize_crtc(struct intel_crtc *crtc, 9977 struct drm_modeset_acquire_ctx *ctx) 9978 { 9979 struct drm_device *dev = crtc->base.dev; 9980 struct drm_i915_private *dev_priv = to_i915(dev); 9981 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); 9982 9983 if (crtc_state->hw.active) { 9984 struct intel_plane *plane; 9985 9986 /* Disable everything but the primary plane */ 9987 for_each_intel_plane_on_crtc(dev, crtc, plane) { 9988 const struct intel_plane_state *plane_state = 9989 to_intel_plane_state(plane->base.state); 9990 9991 if (plane_state->uapi.visible && 9992 plane->base.type != DRM_PLANE_TYPE_PRIMARY) 9993 intel_plane_disable_noatomic(crtc, plane); 9994 } 9995 9996 /* Disable any background color/etc. set by the BIOS */ 9997 intel_color_commit(crtc_state); 9998 } 9999 10000 /* Adjust the state of the output pipe according to whether we 10001 * have active connectors/encoders. */ 10002 if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) && 10003 !intel_crtc_is_bigjoiner_slave(crtc_state)) 10004 intel_crtc_disable_noatomic(crtc, ctx); 10005 10006 if (crtc_state->hw.active || HAS_GMCH(dev_priv)) { 10007 /* 10008 * We start out with underrun reporting disabled to avoid races. 10009 * For correct bookkeeping mark this on active crtcs. 10010 * 10011 * Also on gmch platforms we dont have any hardware bits to 10012 * disable the underrun reporting. Which means we need to start 10013 * out with underrun reporting disabled also on inactive pipes, 10014 * since otherwise we'll complain about the garbage we read when 10015 * e.g. coming up after runtime pm. 10016 * 10017 * No protection against concurrent access is required - at 10018 * worst a fifo underrun happens which also sets this to false. 10019 */ 10020 crtc->cpu_fifo_underrun_disabled = true; 10021 /* 10022 * We track the PCH trancoder underrun reporting state 10023 * within the crtc. With crtc for pipe A housing the underrun 10024 * reporting state for PCH transcoder A, crtc for pipe B housing 10025 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, 10026 * and marking underrun reporting as disabled for the non-existing 10027 * PCH transcoders B and C would prevent enabling the south 10028 * error interrupt (see cpt_can_enable_serr_int()). 10029 */ 10030 if (intel_has_pch_trancoder(dev_priv, crtc->pipe)) 10031 crtc->pch_fifo_underrun_disabled = true; 10032 } 10033 } 10034 10035 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state) 10036 { 10037 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 10038 10039 /* 10040 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram 10041 * the hardware when a high res displays plugged in. DPLL P 10042 * divider is zero, and the pipe timings are bonkers. We'll 10043 * try to disable everything in that case. 10044 * 10045 * FIXME would be nice to be able to sanitize this state 10046 * without several WARNs, but for now let's take the easy 10047 * road. 10048 */ 10049 return IS_SANDYBRIDGE(dev_priv) && 10050 crtc_state->hw.active && 10051 crtc_state->shared_dpll && 10052 crtc_state->port_clock == 0; 10053 } 10054 10055 static void intel_sanitize_encoder(struct intel_encoder *encoder) 10056 { 10057 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 10058 struct intel_connector *connector; 10059 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 10060 struct intel_crtc_state *crtc_state = crtc ? 10061 to_intel_crtc_state(crtc->base.state) : NULL; 10062 10063 /* We need to check both for a crtc link (meaning that the 10064 * encoder is active and trying to read from a pipe) and the 10065 * pipe itself being active. */ 10066 bool has_active_crtc = crtc_state && 10067 crtc_state->hw.active; 10068 10069 if (crtc_state && has_bogus_dpll_config(crtc_state)) { 10070 drm_dbg_kms(&dev_priv->drm, 10071 "BIOS has misprogrammed the hardware. Disabling pipe %c\n", 10072 pipe_name(crtc->pipe)); 10073 has_active_crtc = false; 10074 } 10075 10076 connector = intel_encoder_find_connector(encoder); 10077 if (connector && !has_active_crtc) { 10078 drm_dbg_kms(&dev_priv->drm, 10079 "[ENCODER:%d:%s] has active connectors but no active pipe!\n", 10080 encoder->base.base.id, 10081 encoder->base.name); 10082 10083 /* Connector is active, but has no active pipe. This is 10084 * fallout from our resume register restoring. Disable 10085 * the encoder manually again. */ 10086 if (crtc_state) { 10087 struct drm_encoder *best_encoder; 10088 10089 drm_dbg_kms(&dev_priv->drm, 10090 "[ENCODER:%d:%s] manually disabled\n", 10091 encoder->base.base.id, 10092 encoder->base.name); 10093 10094 /* avoid oopsing in case the hooks consult best_encoder */ 10095 best_encoder = connector->base.state->best_encoder; 10096 connector->base.state->best_encoder = &encoder->base; 10097 10098 /* FIXME NULL atomic state passed! */ 10099 if (encoder->disable) 10100 encoder->disable(NULL, encoder, crtc_state, 10101 connector->base.state); 10102 if (encoder->post_disable) 10103 encoder->post_disable(NULL, encoder, crtc_state, 10104 connector->base.state); 10105 10106 connector->base.state->best_encoder = best_encoder; 10107 } 10108 encoder->base.crtc = NULL; 10109 10110 /* Inconsistent output/port/pipe state happens presumably due to 10111 * a bug in one of the get_hw_state functions. Or someplace else 10112 * in our code, like the register restore mess on resume. Clamp 10113 * things to off as a safer default. */ 10114 10115 connector->base.dpms = DRM_MODE_DPMS_OFF; 10116 connector->base.encoder = NULL; 10117 } 10118 10119 /* notify opregion of the sanitized encoder state */ 10120 intel_opregion_notify_encoder(encoder, connector && has_active_crtc); 10121 10122 if (HAS_DDI(dev_priv)) 10123 intel_ddi_sanitize_encoder_pll_mapping(encoder); 10124 } 10125 10126 /* FIXME read out full plane state for all planes */ 10127 static void readout_plane_state(struct drm_i915_private *dev_priv) 10128 { 10129 struct intel_plane *plane; 10130 struct intel_crtc *crtc; 10131 10132 for_each_intel_plane(&dev_priv->drm, plane) { 10133 struct intel_plane_state *plane_state = 10134 to_intel_plane_state(plane->base.state); 10135 struct intel_crtc_state *crtc_state; 10136 enum pipe pipe = PIPE_A; 10137 bool visible; 10138 10139 visible = plane->get_hw_state(plane, &pipe); 10140 10141 crtc = intel_crtc_for_pipe(dev_priv, pipe); 10142 crtc_state = to_intel_crtc_state(crtc->base.state); 10143 10144 intel_set_plane_visible(crtc_state, plane_state, visible); 10145 10146 drm_dbg_kms(&dev_priv->drm, 10147 "[PLANE:%d:%s] hw state readout: %s, pipe %c\n", 10148 plane->base.base.id, plane->base.name, 10149 str_enabled_disabled(visible), pipe_name(pipe)); 10150 } 10151 10152 for_each_intel_crtc(&dev_priv->drm, crtc) { 10153 struct intel_crtc_state *crtc_state = 10154 to_intel_crtc_state(crtc->base.state); 10155 10156 fixup_plane_bitmasks(crtc_state); 10157 } 10158 } 10159 10160 static void intel_modeset_readout_hw_state(struct drm_device *dev) 10161 { 10162 struct drm_i915_private *dev_priv = to_i915(dev); 10163 struct intel_cdclk_state *cdclk_state = 10164 to_intel_cdclk_state(dev_priv->cdclk.obj.state); 10165 struct intel_dbuf_state *dbuf_state = 10166 to_intel_dbuf_state(dev_priv->dbuf.obj.state); 10167 enum pipe pipe; 10168 struct intel_crtc *crtc; 10169 struct intel_encoder *encoder; 10170 struct intel_connector *connector; 10171 struct drm_connector_list_iter conn_iter; 10172 u8 active_pipes = 0; 10173 10174 for_each_intel_crtc(dev, crtc) { 10175 struct intel_crtc_state *crtc_state = 10176 to_intel_crtc_state(crtc->base.state); 10177 10178 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi); 10179 intel_crtc_free_hw_state(crtc_state); 10180 intel_crtc_state_reset(crtc_state, crtc); 10181 10182 intel_crtc_get_pipe_config(crtc_state); 10183 10184 crtc_state->hw.enable = crtc_state->hw.active; 10185 10186 crtc->base.enabled = crtc_state->hw.enable; 10187 crtc->active = crtc_state->hw.active; 10188 10189 if (crtc_state->hw.active) 10190 active_pipes |= BIT(crtc->pipe); 10191 10192 drm_dbg_kms(&dev_priv->drm, 10193 "[CRTC:%d:%s] hw state readout: %s\n", 10194 crtc->base.base.id, crtc->base.name, 10195 str_enabled_disabled(crtc_state->hw.active)); 10196 } 10197 10198 cdclk_state->active_pipes = dbuf_state->active_pipes = active_pipes; 10199 10200 readout_plane_state(dev_priv); 10201 10202 for_each_intel_encoder(dev, encoder) { 10203 struct intel_crtc_state *crtc_state = NULL; 10204 10205 pipe = 0; 10206 10207 if (encoder->get_hw_state(encoder, &pipe)) { 10208 crtc = intel_crtc_for_pipe(dev_priv, pipe); 10209 crtc_state = to_intel_crtc_state(crtc->base.state); 10210 10211 encoder->base.crtc = &crtc->base; 10212 intel_encoder_get_config(encoder, crtc_state); 10213 10214 /* read out to slave crtc as well for bigjoiner */ 10215 if (crtc_state->bigjoiner_pipes) { 10216 struct intel_crtc *slave_crtc; 10217 10218 /* encoder should read be linked to bigjoiner master */ 10219 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 10220 10221 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc, 10222 intel_crtc_bigjoiner_slave_pipes(crtc_state)) { 10223 struct intel_crtc_state *slave_crtc_state; 10224 10225 slave_crtc_state = to_intel_crtc_state(slave_crtc->base.state); 10226 intel_encoder_get_config(encoder, slave_crtc_state); 10227 } 10228 } 10229 } else { 10230 encoder->base.crtc = NULL; 10231 } 10232 10233 if (encoder->sync_state) 10234 encoder->sync_state(encoder, crtc_state); 10235 10236 drm_dbg_kms(&dev_priv->drm, 10237 "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", 10238 encoder->base.base.id, encoder->base.name, 10239 str_enabled_disabled(encoder->base.crtc), 10240 pipe_name(pipe)); 10241 } 10242 10243 intel_dpll_readout_hw_state(dev_priv); 10244 10245 drm_connector_list_iter_begin(dev, &conn_iter); 10246 for_each_intel_connector_iter(connector, &conn_iter) { 10247 if (connector->get_hw_state(connector)) { 10248 struct intel_crtc_state *crtc_state; 10249 struct intel_crtc *crtc; 10250 10251 connector->base.dpms = DRM_MODE_DPMS_ON; 10252 10253 encoder = intel_attached_encoder(connector); 10254 connector->base.encoder = &encoder->base; 10255 10256 crtc = to_intel_crtc(encoder->base.crtc); 10257 crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL; 10258 10259 if (crtc_state && crtc_state->hw.active) { 10260 /* 10261 * This has to be done during hardware readout 10262 * because anything calling .crtc_disable may 10263 * rely on the connector_mask being accurate. 10264 */ 10265 crtc_state->uapi.connector_mask |= 10266 drm_connector_mask(&connector->base); 10267 crtc_state->uapi.encoder_mask |= 10268 drm_encoder_mask(&encoder->base); 10269 } 10270 } else { 10271 connector->base.dpms = DRM_MODE_DPMS_OFF; 10272 connector->base.encoder = NULL; 10273 } 10274 drm_dbg_kms(&dev_priv->drm, 10275 "[CONNECTOR:%d:%s] hw state readout: %s\n", 10276 connector->base.base.id, connector->base.name, 10277 str_enabled_disabled(connector->base.encoder)); 10278 } 10279 drm_connector_list_iter_end(&conn_iter); 10280 10281 for_each_intel_crtc(dev, crtc) { 10282 struct intel_bw_state *bw_state = 10283 to_intel_bw_state(dev_priv->bw_obj.state); 10284 struct intel_crtc_state *crtc_state = 10285 to_intel_crtc_state(crtc->base.state); 10286 struct intel_plane *plane; 10287 int min_cdclk = 0; 10288 10289 if (crtc_state->hw.active) { 10290 /* 10291 * The initial mode needs to be set in order to keep 10292 * the atomic core happy. It wants a valid mode if the 10293 * crtc's enabled, so we do the above call. 10294 * 10295 * But we don't set all the derived state fully, hence 10296 * set a flag to indicate that a full recalculation is 10297 * needed on the next commit. 10298 */ 10299 crtc_state->inherited = true; 10300 10301 intel_crtc_update_active_timings(crtc_state); 10302 10303 intel_crtc_copy_hw_to_uapi_state(crtc_state); 10304 } 10305 10306 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 10307 const struct intel_plane_state *plane_state = 10308 to_intel_plane_state(plane->base.state); 10309 10310 /* 10311 * FIXME don't have the fb yet, so can't 10312 * use intel_plane_data_rate() :( 10313 */ 10314 if (plane_state->uapi.visible) 10315 crtc_state->data_rate[plane->id] = 10316 4 * crtc_state->pixel_rate; 10317 /* 10318 * FIXME don't have the fb yet, so can't 10319 * use plane->min_cdclk() :( 10320 */ 10321 if (plane_state->uapi.visible && plane->min_cdclk) { 10322 if (crtc_state->double_wide || DISPLAY_VER(dev_priv) >= 10) 10323 crtc_state->min_cdclk[plane->id] = 10324 DIV_ROUND_UP(crtc_state->pixel_rate, 2); 10325 else 10326 crtc_state->min_cdclk[plane->id] = 10327 crtc_state->pixel_rate; 10328 } 10329 drm_dbg_kms(&dev_priv->drm, 10330 "[PLANE:%d:%s] min_cdclk %d kHz\n", 10331 plane->base.base.id, plane->base.name, 10332 crtc_state->min_cdclk[plane->id]); 10333 } 10334 10335 if (crtc_state->hw.active) { 10336 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); 10337 if (drm_WARN_ON(dev, min_cdclk < 0)) 10338 min_cdclk = 0; 10339 } 10340 10341 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; 10342 cdclk_state->min_voltage_level[crtc->pipe] = 10343 crtc_state->min_voltage_level; 10344 10345 intel_bw_crtc_update(bw_state, crtc_state); 10346 10347 intel_pipe_config_sanity_check(dev_priv, crtc_state); 10348 } 10349 } 10350 10351 static void 10352 get_encoder_power_domains(struct drm_i915_private *dev_priv) 10353 { 10354 struct intel_encoder *encoder; 10355 10356 for_each_intel_encoder(&dev_priv->drm, encoder) { 10357 struct intel_crtc_state *crtc_state; 10358 10359 if (!encoder->get_power_domains) 10360 continue; 10361 10362 /* 10363 * MST-primary and inactive encoders don't have a crtc state 10364 * and neither of these require any power domain references. 10365 */ 10366 if (!encoder->base.crtc) 10367 continue; 10368 10369 crtc_state = to_intel_crtc_state(encoder->base.crtc->state); 10370 encoder->get_power_domains(encoder, crtc_state); 10371 } 10372 } 10373 10374 static void intel_early_display_was(struct drm_i915_private *dev_priv) 10375 { 10376 /* 10377 * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl 10378 * Also known as Wa_14010480278. 10379 */ 10380 if (IS_DISPLAY_VER(dev_priv, 10, 12)) 10381 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0, 10382 intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS); 10383 10384 if (IS_HASWELL(dev_priv)) { 10385 /* 10386 * WaRsPkgCStateDisplayPMReq:hsw 10387 * System hang if this isn't done before disabling all planes! 10388 */ 10389 intel_de_write(dev_priv, CHICKEN_PAR1_1, 10390 intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); 10391 } 10392 10393 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) { 10394 /* Display WA #1142:kbl,cfl,cml */ 10395 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 10396 KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22); 10397 intel_de_rmw(dev_priv, CHICKEN_MISC_2, 10398 KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14, 10399 KBL_ARB_FILL_SPARE_14); 10400 } 10401 } 10402 10403 10404 /* Scan out the current hw modeset state, 10405 * and sanitizes it to the current state 10406 */ 10407 static void 10408 intel_modeset_setup_hw_state(struct drm_device *dev, 10409 struct drm_modeset_acquire_ctx *ctx) 10410 { 10411 struct drm_i915_private *dev_priv = to_i915(dev); 10412 struct intel_encoder *encoder; 10413 struct intel_crtc *crtc; 10414 intel_wakeref_t wakeref; 10415 10416 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 10417 10418 intel_early_display_was(dev_priv); 10419 intel_modeset_readout_hw_state(dev); 10420 10421 /* HW state is read out, now we need to sanitize this mess. */ 10422 get_encoder_power_domains(dev_priv); 10423 10424 intel_pch_sanitize(dev_priv); 10425 10426 /* 10427 * intel_sanitize_plane_mapping() may need to do vblank 10428 * waits, so we need vblank interrupts restored beforehand. 10429 */ 10430 for_each_intel_crtc(&dev_priv->drm, crtc) { 10431 struct intel_crtc_state *crtc_state = 10432 to_intel_crtc_state(crtc->base.state); 10433 10434 drm_crtc_vblank_reset(&crtc->base); 10435 10436 if (crtc_state->hw.active) 10437 intel_crtc_vblank_on(crtc_state); 10438 } 10439 10440 intel_sanitize_plane_mapping(dev_priv); 10441 10442 for_each_intel_encoder(dev, encoder) 10443 intel_sanitize_encoder(encoder); 10444 10445 for_each_intel_crtc(&dev_priv->drm, crtc) { 10446 struct intel_crtc_state *crtc_state = 10447 to_intel_crtc_state(crtc->base.state); 10448 10449 intel_sanitize_crtc(crtc, ctx); 10450 intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]"); 10451 } 10452 10453 intel_modeset_update_connector_atomic_state(dev); 10454 10455 intel_dpll_sanitize_state(dev_priv); 10456 10457 if (IS_G4X(dev_priv)) { 10458 g4x_wm_get_hw_state(dev_priv); 10459 g4x_wm_sanitize(dev_priv); 10460 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 10461 vlv_wm_get_hw_state(dev_priv); 10462 vlv_wm_sanitize(dev_priv); 10463 } else if (DISPLAY_VER(dev_priv) >= 9) { 10464 skl_wm_get_hw_state(dev_priv); 10465 skl_wm_sanitize(dev_priv); 10466 } else if (HAS_PCH_SPLIT(dev_priv)) { 10467 ilk_wm_get_hw_state(dev_priv); 10468 } 10469 10470 for_each_intel_crtc(dev, crtc) { 10471 struct intel_crtc_state *crtc_state = 10472 to_intel_crtc_state(crtc->base.state); 10473 u64 put_domains; 10474 10475 put_domains = modeset_get_crtc_power_domains(crtc_state); 10476 if (drm_WARN_ON(dev, put_domains)) 10477 modeset_put_crtc_power_domains(crtc, put_domains); 10478 } 10479 10480 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref); 10481 10482 intel_power_domains_sanitize_state(dev_priv); 10483 } 10484 10485 void intel_display_resume(struct drm_device *dev) 10486 { 10487 struct drm_i915_private *dev_priv = to_i915(dev); 10488 struct drm_atomic_state *state = dev_priv->modeset_restore_state; 10489 struct drm_modeset_acquire_ctx ctx; 10490 int ret; 10491 10492 if (!HAS_DISPLAY(dev_priv)) 10493 return; 10494 10495 dev_priv->modeset_restore_state = NULL; 10496 if (state) 10497 state->acquire_ctx = &ctx; 10498 10499 drm_modeset_acquire_init(&ctx, 0); 10500 10501 while (1) { 10502 ret = drm_modeset_lock_all_ctx(dev, &ctx); 10503 if (ret != -EDEADLK) 10504 break; 10505 10506 drm_modeset_backoff(&ctx); 10507 } 10508 10509 if (!ret) 10510 ret = __intel_display_resume(dev, state, &ctx); 10511 10512 intel_enable_ipc(dev_priv); 10513 drm_modeset_drop_locks(&ctx); 10514 drm_modeset_acquire_fini(&ctx); 10515 10516 if (ret) 10517 drm_err(&dev_priv->drm, 10518 "Restoring old state failed with %i\n", ret); 10519 if (state) 10520 drm_atomic_state_put(state); 10521 } 10522 10523 static void intel_hpd_poll_fini(struct drm_i915_private *i915) 10524 { 10525 struct intel_connector *connector; 10526 struct drm_connector_list_iter conn_iter; 10527 10528 /* Kill all the work that may have been queued by hpd. */ 10529 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 10530 for_each_intel_connector_iter(connector, &conn_iter) { 10531 if (connector->modeset_retry_work.func) 10532 cancel_work_sync(&connector->modeset_retry_work); 10533 if (connector->hdcp.shim) { 10534 cancel_delayed_work_sync(&connector->hdcp.check_work); 10535 cancel_work_sync(&connector->hdcp.prop_work); 10536 } 10537 } 10538 drm_connector_list_iter_end(&conn_iter); 10539 } 10540 10541 /* part #1: call before irq uninstall */ 10542 void intel_modeset_driver_remove(struct drm_i915_private *i915) 10543 { 10544 if (!HAS_DISPLAY(i915)) 10545 return; 10546 10547 flush_workqueue(i915->flip_wq); 10548 flush_workqueue(i915->modeset_wq); 10549 10550 flush_work(&i915->atomic_helper.free_work); 10551 drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list)); 10552 } 10553 10554 /* part #2: call after irq uninstall */ 10555 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915) 10556 { 10557 if (!HAS_DISPLAY(i915)) 10558 return; 10559 10560 /* 10561 * Due to the hpd irq storm handling the hotplug work can re-arm the 10562 * poll handlers. Hence disable polling after hpd handling is shut down. 10563 */ 10564 intel_hpd_poll_fini(i915); 10565 10566 /* 10567 * MST topology needs to be suspended so we don't have any calls to 10568 * fbdev after it's finalized. MST will be destroyed later as part of 10569 * drm_mode_config_cleanup() 10570 */ 10571 intel_dp_mst_suspend(i915); 10572 10573 /* poll work can call into fbdev, hence clean that up afterwards */ 10574 intel_fbdev_fini(i915); 10575 10576 intel_unregister_dsm_handler(); 10577 10578 intel_fbc_global_disable(i915); 10579 10580 /* flush any delayed tasks or pending work */ 10581 flush_scheduled_work(); 10582 10583 intel_hdcp_component_fini(i915); 10584 10585 intel_mode_config_cleanup(i915); 10586 10587 intel_overlay_cleanup(i915); 10588 10589 intel_gmbus_teardown(i915); 10590 10591 destroy_workqueue(i915->flip_wq); 10592 destroy_workqueue(i915->modeset_wq); 10593 10594 intel_fbc_cleanup(i915); 10595 } 10596 10597 /* part #3: call after gem init */ 10598 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915) 10599 { 10600 intel_dmc_ucode_fini(i915); 10601 10602 intel_power_domains_driver_remove(i915); 10603 10604 intel_vga_unregister(i915); 10605 10606 intel_bios_driver_remove(i915); 10607 } 10608 10609 bool intel_modeset_probe_defer(struct pci_dev *pdev) 10610 { 10611 struct drm_privacy_screen *privacy_screen; 10612 10613 /* 10614 * apple-gmux is needed on dual GPU MacBook Pro 10615 * to probe the panel if we're the inactive GPU. 10616 */ 10617 if (vga_switcheroo_client_probe_defer(pdev)) 10618 return true; 10619 10620 /* If the LCD panel has a privacy-screen, wait for it */ 10621 privacy_screen = drm_privacy_screen_get(&pdev->dev, NULL); 10622 if (IS_ERR(privacy_screen) && PTR_ERR(privacy_screen) == -EPROBE_DEFER) 10623 return true; 10624 10625 drm_privacy_screen_put(privacy_screen); 10626 10627 return false; 10628 } 10629 10630 void intel_display_driver_register(struct drm_i915_private *i915) 10631 { 10632 if (!HAS_DISPLAY(i915)) 10633 return; 10634 10635 intel_display_debugfs_register(i915); 10636 10637 /* Must be done after probing outputs */ 10638 intel_opregion_register(i915); 10639 acpi_video_register(); 10640 10641 intel_audio_init(i915); 10642 10643 /* 10644 * Some ports require correctly set-up hpd registers for 10645 * detection to work properly (leading to ghost connected 10646 * connector status), e.g. VGA on gm45. Hence we can only set 10647 * up the initial fbdev config after hpd irqs are fully 10648 * enabled. We do it last so that the async config cannot run 10649 * before the connectors are registered. 10650 */ 10651 intel_fbdev_initial_config_async(&i915->drm); 10652 10653 /* 10654 * We need to coordinate the hotplugs with the asynchronous 10655 * fbdev configuration, for which we use the 10656 * fbdev->async_cookie. 10657 */ 10658 drm_kms_helper_poll_init(&i915->drm); 10659 } 10660 10661 void intel_display_driver_unregister(struct drm_i915_private *i915) 10662 { 10663 if (!HAS_DISPLAY(i915)) 10664 return; 10665 10666 intel_fbdev_unregister(i915); 10667 intel_audio_deinit(i915); 10668 10669 /* 10670 * After flushing the fbdev (incl. a late async config which 10671 * will have delayed queuing of a hotplug event), then flush 10672 * the hotplug events. 10673 */ 10674 drm_kms_helper_poll_fini(&i915->drm); 10675 drm_atomic_helper_shutdown(&i915->drm); 10676 10677 acpi_video_unregister(); 10678 intel_opregion_unregister(i915); 10679 } 10680