1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <linux/dma-resv.h> 28 #include <linux/i2c.h> 29 #include <linux/input.h> 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/slab.h> 33 #include <linux/string_helpers.h> 34 35 #include <drm/display/drm_dp_helper.h> 36 #include <drm/drm_atomic.h> 37 #include <drm/drm_atomic_helper.h> 38 #include <drm/drm_atomic_uapi.h> 39 #include <drm/drm_damage_helper.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_fourcc.h> 42 #include <drm/drm_probe_helper.h> 43 #include <drm/drm_rect.h> 44 45 #include "gem/i915_gem_lmem.h" 46 #include "gem/i915_gem_object.h" 47 48 #include "g4x_dp.h" 49 #include "g4x_hdmi.h" 50 #include "hsw_ips.h" 51 #include "i915_drv.h" 52 #include "i915_reg.h" 53 #include "i915_utils.h" 54 #include "i9xx_plane.h" 55 #include "i9xx_wm.h" 56 #include "icl_dsi.h" 57 #include "intel_atomic.h" 58 #include "intel_atomic_plane.h" 59 #include "intel_audio.h" 60 #include "intel_bw.h" 61 #include "intel_cdclk.h" 62 #include "intel_clock_gating.h" 63 #include "intel_color.h" 64 #include "intel_crt.h" 65 #include "intel_crtc.h" 66 #include "intel_crtc_state_dump.h" 67 #include "intel_ddi.h" 68 #include "intel_de.h" 69 #include "intel_display_driver.h" 70 #include "intel_display_power.h" 71 #include "intel_display_types.h" 72 #include "intel_dmc.h" 73 #include "intel_dp.h" 74 #include "intel_dp_link_training.h" 75 #include "intel_dp_mst.h" 76 #include "intel_dpio_phy.h" 77 #include "intel_dpll.h" 78 #include "intel_dpll_mgr.h" 79 #include "intel_dpt.h" 80 #include "intel_drrs.h" 81 #include "intel_dsi.h" 82 #include "intel_dvo.h" 83 #include "intel_fb.h" 84 #include "intel_fbc.h" 85 #include "intel_fbdev.h" 86 #include "intel_fdi.h" 87 #include "intel_fifo_underrun.h" 88 #include "intel_frontbuffer.h" 89 #include "intel_hdmi.h" 90 #include "intel_hotplug.h" 91 #include "intel_lvds.h" 92 #include "intel_lvds_regs.h" 93 #include "intel_modeset_setup.h" 94 #include "intel_modeset_verify.h" 95 #include "intel_overlay.h" 96 #include "intel_panel.h" 97 #include "intel_pch_display.h" 98 #include "intel_pch_refclk.h" 99 #include "intel_pcode.h" 100 #include "intel_pipe_crc.h" 101 #include "intel_plane_initial.h" 102 #include "intel_pmdemand.h" 103 #include "intel_pps.h" 104 #include "intel_psr.h" 105 #include "intel_sdvo.h" 106 #include "intel_snps_phy.h" 107 #include "intel_tc.h" 108 #include "intel_tv.h" 109 #include "intel_vblank.h" 110 #include "intel_vdsc.h" 111 #include "intel_vdsc_regs.h" 112 #include "intel_vga.h" 113 #include "intel_vrr.h" 114 #include "intel_wm.h" 115 #include "skl_scaler.h" 116 #include "skl_universal_plane.h" 117 #include "skl_watermark.h" 118 #include "vlv_dsi.h" 119 #include "vlv_dsi_pll.h" 120 #include "vlv_dsi_regs.h" 121 #include "vlv_sideband.h" 122 123 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state); 124 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state); 125 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state); 126 static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state); 127 128 /* returns HPLL frequency in kHz */ 129 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) 130 { 131 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; 132 133 /* Obtain SKU information */ 134 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & 135 CCK_FUSE_HPLL_FREQ_MASK; 136 137 return vco_freq[hpll_freq] * 1000; 138 } 139 140 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 141 const char *name, u32 reg, int ref_freq) 142 { 143 u32 val; 144 int divider; 145 146 val = vlv_cck_read(dev_priv, reg); 147 divider = val & CCK_FREQUENCY_VALUES; 148 149 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != 150 (divider << CCK_FREQUENCY_STATUS_SHIFT), 151 "%s change in progress\n", name); 152 153 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); 154 } 155 156 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 157 const char *name, u32 reg) 158 { 159 int hpll; 160 161 vlv_cck_get(dev_priv); 162 163 if (dev_priv->hpll_freq == 0) 164 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); 165 166 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); 167 168 vlv_cck_put(dev_priv); 169 170 return hpll; 171 } 172 173 void intel_update_czclk(struct drm_i915_private *dev_priv) 174 { 175 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) 176 return; 177 178 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", 179 CCK_CZ_CLOCK_CONTROL); 180 181 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", 182 dev_priv->czclk_freq); 183 } 184 185 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state) 186 { 187 return (crtc_state->active_planes & 188 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0; 189 } 190 191 /* WA Display #0827: Gen9:all */ 192 static void 193 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) 194 { 195 if (enable) 196 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 197 0, DUPS1_GATING_DIS | DUPS2_GATING_DIS); 198 else 199 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 200 DUPS1_GATING_DIS | DUPS2_GATING_DIS, 0); 201 } 202 203 /* Wa_2006604312:icl,ehl */ 204 static void 205 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 206 bool enable) 207 { 208 if (enable) 209 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 0, DPFR_GATING_DIS); 210 else 211 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), DPFR_GATING_DIS, 0); 212 } 213 214 /* Wa_1604331009:icl,jsl,ehl */ 215 static void 216 icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 217 bool enable) 218 { 219 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), CURSOR_GATING_DIS, 220 enable ? CURSOR_GATING_DIS : 0); 221 } 222 223 static bool 224 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state) 225 { 226 return crtc_state->master_transcoder != INVALID_TRANSCODER; 227 } 228 229 bool 230 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state) 231 { 232 return crtc_state->sync_mode_slaves_mask != 0; 233 } 234 235 bool 236 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state) 237 { 238 return is_trans_port_sync_master(crtc_state) || 239 is_trans_port_sync_slave(crtc_state); 240 } 241 242 static enum pipe bigjoiner_master_pipe(const struct intel_crtc_state *crtc_state) 243 { 244 return ffs(crtc_state->bigjoiner_pipes) - 1; 245 } 246 247 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state) 248 { 249 if (crtc_state->bigjoiner_pipes) 250 return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state)); 251 else 252 return 0; 253 } 254 255 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state) 256 { 257 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 258 259 return crtc_state->bigjoiner_pipes && 260 crtc->pipe != bigjoiner_master_pipe(crtc_state); 261 } 262 263 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state) 264 { 265 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 266 267 return crtc_state->bigjoiner_pipes && 268 crtc->pipe == bigjoiner_master_pipe(crtc_state); 269 } 270 271 static int intel_bigjoiner_num_pipes(const struct intel_crtc_state *crtc_state) 272 { 273 return hweight8(crtc_state->bigjoiner_pipes); 274 } 275 276 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state) 277 { 278 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 279 280 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 281 return intel_crtc_for_pipe(i915, bigjoiner_master_pipe(crtc_state)); 282 else 283 return to_intel_crtc(crtc_state->uapi.crtc); 284 } 285 286 static void 287 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) 288 { 289 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 290 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 291 292 if (DISPLAY_VER(dev_priv) >= 4) { 293 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 294 295 /* Wait for the Pipe State to go off */ 296 if (intel_de_wait_for_clear(dev_priv, TRANSCONF(cpu_transcoder), 297 TRANSCONF_STATE_ENABLE, 100)) 298 drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n"); 299 } else { 300 intel_wait_for_pipe_scanline_stopped(crtc); 301 } 302 } 303 304 void assert_transcoder(struct drm_i915_private *dev_priv, 305 enum transcoder cpu_transcoder, bool state) 306 { 307 bool cur_state; 308 enum intel_display_power_domain power_domain; 309 intel_wakeref_t wakeref; 310 311 /* we keep both pipes enabled on 830 */ 312 if (IS_I830(dev_priv)) 313 state = true; 314 315 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 316 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 317 if (wakeref) { 318 u32 val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)); 319 cur_state = !!(val & TRANSCONF_ENABLE); 320 321 intel_display_power_put(dev_priv, power_domain, wakeref); 322 } else { 323 cur_state = false; 324 } 325 326 I915_STATE_WARN(dev_priv, cur_state != state, 327 "transcoder %s assertion failure (expected %s, current %s)\n", 328 transcoder_name(cpu_transcoder), str_on_off(state), 329 str_on_off(cur_state)); 330 } 331 332 static void assert_plane(struct intel_plane *plane, bool state) 333 { 334 struct drm_i915_private *i915 = to_i915(plane->base.dev); 335 enum pipe pipe; 336 bool cur_state; 337 338 cur_state = plane->get_hw_state(plane, &pipe); 339 340 I915_STATE_WARN(i915, cur_state != state, 341 "%s assertion failure (expected %s, current %s)\n", 342 plane->base.name, str_on_off(state), 343 str_on_off(cur_state)); 344 } 345 346 #define assert_plane_enabled(p) assert_plane(p, true) 347 #define assert_plane_disabled(p) assert_plane(p, false) 348 349 static void assert_planes_disabled(struct intel_crtc *crtc) 350 { 351 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 352 struct intel_plane *plane; 353 354 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) 355 assert_plane_disabled(plane); 356 } 357 358 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 359 struct intel_digital_port *dig_port, 360 unsigned int expected_mask) 361 { 362 u32 port_mask; 363 i915_reg_t dpll_reg; 364 365 switch (dig_port->base.port) { 366 default: 367 MISSING_CASE(dig_port->base.port); 368 fallthrough; 369 case PORT_B: 370 port_mask = DPLL_PORTB_READY_MASK; 371 dpll_reg = DPLL(0); 372 break; 373 case PORT_C: 374 port_mask = DPLL_PORTC_READY_MASK; 375 dpll_reg = DPLL(0); 376 expected_mask <<= 4; 377 break; 378 case PORT_D: 379 port_mask = DPLL_PORTD_READY_MASK; 380 dpll_reg = DPIO_PHY_STATUS; 381 break; 382 } 383 384 if (intel_de_wait_for_register(dev_priv, dpll_reg, 385 port_mask, expected_mask, 1000)) 386 drm_WARN(&dev_priv->drm, 1, 387 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", 388 dig_port->base.base.base.id, dig_port->base.base.name, 389 intel_de_read(dev_priv, dpll_reg) & port_mask, 390 expected_mask); 391 } 392 393 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) 394 { 395 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 396 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 397 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 398 enum pipe pipe = crtc->pipe; 399 i915_reg_t reg; 400 u32 val; 401 402 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe)); 403 404 assert_planes_disabled(crtc); 405 406 /* 407 * A pipe without a PLL won't actually be able to drive bits from 408 * a plane. On ILK+ the pipe PLLs are integrated, so we don't 409 * need the check. 410 */ 411 if (HAS_GMCH(dev_priv)) { 412 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI)) 413 assert_dsi_pll_enabled(dev_priv); 414 else 415 assert_pll_enabled(dev_priv, pipe); 416 } else { 417 if (new_crtc_state->has_pch_encoder) { 418 /* if driving the PCH, we need FDI enabled */ 419 assert_fdi_rx_pll_enabled(dev_priv, 420 intel_crtc_pch_transcoder(crtc)); 421 assert_fdi_tx_pll_enabled(dev_priv, 422 (enum pipe) cpu_transcoder); 423 } 424 /* FIXME: assert CPU port conditions for SNB+ */ 425 } 426 427 /* Wa_22012358565:adl-p */ 428 if (DISPLAY_VER(dev_priv) == 13) 429 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe), 430 0, PIPE_ARB_USE_PROG_SLOTS); 431 432 reg = TRANSCONF(cpu_transcoder); 433 val = intel_de_read(dev_priv, reg); 434 if (val & TRANSCONF_ENABLE) { 435 /* we keep both pipes enabled on 830 */ 436 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv)); 437 return; 438 } 439 440 intel_de_write(dev_priv, reg, val | TRANSCONF_ENABLE); 441 intel_de_posting_read(dev_priv, reg); 442 443 /* 444 * Until the pipe starts PIPEDSL reads will return a stale value, 445 * which causes an apparent vblank timestamp jump when PIPEDSL 446 * resets to its proper value. That also messes up the frame count 447 * when it's derived from the timestamps. So let's wait for the 448 * pipe to start properly before we call drm_crtc_vblank_on() 449 */ 450 if (intel_crtc_max_vblank_count(new_crtc_state) == 0) 451 intel_wait_for_pipe_scanline_moving(crtc); 452 } 453 454 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) 455 { 456 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 457 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 458 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 459 enum pipe pipe = crtc->pipe; 460 i915_reg_t reg; 461 u32 val; 462 463 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe)); 464 465 /* 466 * Make sure planes won't keep trying to pump pixels to us, 467 * or we might hang the display. 468 */ 469 assert_planes_disabled(crtc); 470 471 reg = TRANSCONF(cpu_transcoder); 472 val = intel_de_read(dev_priv, reg); 473 if ((val & TRANSCONF_ENABLE) == 0) 474 return; 475 476 /* 477 * Double wide has implications for planes 478 * so best keep it disabled when not needed. 479 */ 480 if (old_crtc_state->double_wide) 481 val &= ~TRANSCONF_DOUBLE_WIDE; 482 483 /* Don't disable pipe or pipe PLLs if needed */ 484 if (!IS_I830(dev_priv)) 485 val &= ~TRANSCONF_ENABLE; 486 487 if (DISPLAY_VER(dev_priv) >= 14) 488 intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder), 489 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 490 else if (DISPLAY_VER(dev_priv) >= 12) 491 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 492 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 493 494 intel_de_write(dev_priv, reg, val); 495 if ((val & TRANSCONF_ENABLE) == 0) 496 intel_wait_for_pipe_off(old_crtc_state); 497 } 498 499 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) 500 { 501 unsigned int size = 0; 502 int i; 503 504 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) 505 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width; 506 507 return size; 508 } 509 510 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info) 511 { 512 unsigned int size = 0; 513 int i; 514 515 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) { 516 unsigned int plane_size; 517 518 if (rem_info->plane[i].linear) 519 plane_size = rem_info->plane[i].size; 520 else 521 plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height; 522 523 if (plane_size == 0) 524 continue; 525 526 if (rem_info->plane_alignment) 527 size = ALIGN(size, rem_info->plane_alignment); 528 529 size += plane_size; 530 } 531 532 return size; 533 } 534 535 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) 536 { 537 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 538 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 539 540 return DISPLAY_VER(dev_priv) < 4 || 541 (plane->fbc && 542 plane_state->view.gtt.type == I915_GTT_VIEW_NORMAL); 543 } 544 545 /* 546 * Convert the x/y offsets into a linear offset. 547 * Only valid with 0/180 degree rotation, which is fine since linear 548 * offset is only used with linear buffers on pre-hsw and tiled buffers 549 * with gen2/3, and 90/270 degree rotations isn't supported on any of them. 550 */ 551 u32 intel_fb_xy_to_linear(int x, int y, 552 const struct intel_plane_state *state, 553 int color_plane) 554 { 555 const struct drm_framebuffer *fb = state->hw.fb; 556 unsigned int cpp = fb->format->cpp[color_plane]; 557 unsigned int pitch = state->view.color_plane[color_plane].mapping_stride; 558 559 return y * pitch + x * cpp; 560 } 561 562 /* 563 * Add the x/y offsets derived from fb->offsets[] to the user 564 * specified plane src x/y offsets. The resulting x/y offsets 565 * specify the start of scanout from the beginning of the gtt mapping. 566 */ 567 void intel_add_fb_offsets(int *x, int *y, 568 const struct intel_plane_state *state, 569 int color_plane) 570 571 { 572 *x += state->view.color_plane[color_plane].x; 573 *y += state->view.color_plane[color_plane].y; 574 } 575 576 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 577 u32 pixel_format, u64 modifier) 578 { 579 struct intel_crtc *crtc; 580 struct intel_plane *plane; 581 582 if (!HAS_DISPLAY(dev_priv)) 583 return 0; 584 585 /* 586 * We assume the primary plane for pipe A has 587 * the highest stride limits of them all, 588 * if in case pipe A is disabled, use the first pipe from pipe_mask. 589 */ 590 crtc = intel_first_crtc(dev_priv); 591 if (!crtc) 592 return 0; 593 594 plane = to_intel_plane(crtc->base.primary); 595 596 return plane->max_stride(plane, pixel_format, modifier, 597 DRM_MODE_ROTATE_0); 598 } 599 600 void intel_set_plane_visible(struct intel_crtc_state *crtc_state, 601 struct intel_plane_state *plane_state, 602 bool visible) 603 { 604 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 605 606 plane_state->uapi.visible = visible; 607 608 if (visible) 609 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base); 610 else 611 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base); 612 } 613 614 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state) 615 { 616 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 617 struct drm_plane *plane; 618 619 /* 620 * Active_planes aliases if multiple "primary" or cursor planes 621 * have been used on the same (or wrong) pipe. plane_mask uses 622 * unique ids, hence we can use that to reconstruct active_planes. 623 */ 624 crtc_state->enabled_planes = 0; 625 crtc_state->active_planes = 0; 626 627 drm_for_each_plane_mask(plane, &dev_priv->drm, 628 crtc_state->uapi.plane_mask) { 629 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id); 630 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id); 631 } 632 } 633 634 void intel_plane_disable_noatomic(struct intel_crtc *crtc, 635 struct intel_plane *plane) 636 { 637 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 638 struct intel_crtc_state *crtc_state = 639 to_intel_crtc_state(crtc->base.state); 640 struct intel_plane_state *plane_state = 641 to_intel_plane_state(plane->base.state); 642 643 drm_dbg_kms(&dev_priv->drm, 644 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n", 645 plane->base.base.id, plane->base.name, 646 crtc->base.base.id, crtc->base.name); 647 648 intel_set_plane_visible(crtc_state, plane_state, false); 649 intel_plane_fixup_bitmasks(crtc_state); 650 crtc_state->data_rate[plane->id] = 0; 651 crtc_state->data_rate_y[plane->id] = 0; 652 crtc_state->rel_data_rate[plane->id] = 0; 653 crtc_state->rel_data_rate_y[plane->id] = 0; 654 crtc_state->min_cdclk[plane->id] = 0; 655 656 if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 && 657 hsw_ips_disable(crtc_state)) { 658 crtc_state->ips_enabled = false; 659 intel_crtc_wait_for_next_vblank(crtc); 660 } 661 662 /* 663 * Vblank time updates from the shadow to live plane control register 664 * are blocked if the memory self-refresh mode is active at that 665 * moment. So to make sure the plane gets truly disabled, disable 666 * first the self-refresh mode. The self-refresh enable bit in turn 667 * will be checked/applied by the HW only at the next frame start 668 * event which is after the vblank start event, so we need to have a 669 * wait-for-vblank between disabling the plane and the pipe. 670 */ 671 if (HAS_GMCH(dev_priv) && 672 intel_set_memory_cxsr(dev_priv, false)) 673 intel_crtc_wait_for_next_vblank(crtc); 674 675 /* 676 * Gen2 reports pipe underruns whenever all planes are disabled. 677 * So disable underrun reporting before all the planes get disabled. 678 */ 679 if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes) 680 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); 681 682 intel_plane_disable_arm(plane, crtc_state); 683 intel_crtc_wait_for_next_vblank(crtc); 684 } 685 686 unsigned int 687 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state) 688 { 689 int x = 0, y = 0; 690 691 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, 692 plane_state->view.color_plane[0].offset, 0); 693 694 return y; 695 } 696 697 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) 698 { 699 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 700 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 701 enum pipe pipe = crtc->pipe; 702 u32 tmp; 703 704 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe)); 705 706 /* 707 * Display WA #1153: icl 708 * enable hardware to bypass the alpha math 709 * and rounding for per-pixel values 00 and 0xff 710 */ 711 tmp |= PER_PIXEL_ALPHA_BYPASS_EN; 712 /* 713 * Display WA # 1605353570: icl 714 * Set the pixel rounding bit to 1 for allowing 715 * passthrough of Frame buffer pixels unmodified 716 * across pipe 717 */ 718 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU; 719 720 /* 721 * Underrun recovery must always be disabled on display 13+. 722 * DG2 chicken bit meaning is inverted compared to other platforms. 723 */ 724 if (IS_DG2(dev_priv)) 725 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2; 726 else if (DISPLAY_VER(dev_priv) >= 13) 727 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP; 728 729 /* Wa_14010547955:dg2 */ 730 if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER)) 731 tmp |= DG2_RENDER_CCSTAG_4_3_EN; 732 733 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp); 734 } 735 736 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) 737 { 738 struct drm_crtc *crtc; 739 bool cleanup_done; 740 741 drm_for_each_crtc(crtc, &dev_priv->drm) { 742 struct drm_crtc_commit *commit; 743 spin_lock(&crtc->commit_lock); 744 commit = list_first_entry_or_null(&crtc->commit_list, 745 struct drm_crtc_commit, commit_entry); 746 cleanup_done = commit ? 747 try_wait_for_completion(&commit->cleanup_done) : true; 748 spin_unlock(&crtc->commit_lock); 749 750 if (cleanup_done) 751 continue; 752 753 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc)); 754 755 return true; 756 } 757 758 return false; 759 } 760 761 /* 762 * Finds the encoder associated with the given CRTC. This can only be 763 * used when we know that the CRTC isn't feeding multiple encoders! 764 */ 765 struct intel_encoder * 766 intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 767 const struct intel_crtc_state *crtc_state) 768 { 769 const struct drm_connector_state *connector_state; 770 const struct drm_connector *connector; 771 struct intel_encoder *encoder = NULL; 772 struct intel_crtc *master_crtc; 773 int num_encoders = 0; 774 int i; 775 776 master_crtc = intel_master_crtc(crtc_state); 777 778 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 779 if (connector_state->crtc != &master_crtc->base) 780 continue; 781 782 encoder = to_intel_encoder(connector_state->best_encoder); 783 num_encoders++; 784 } 785 786 drm_WARN(state->base.dev, num_encoders != 1, 787 "%d encoders for pipe %c\n", 788 num_encoders, pipe_name(master_crtc->pipe)); 789 790 return encoder; 791 } 792 793 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state) 794 { 795 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 796 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 797 const struct drm_rect *dst = &crtc_state->pch_pfit.dst; 798 enum pipe pipe = crtc->pipe; 799 int width = drm_rect_width(dst); 800 int height = drm_rect_height(dst); 801 int x = dst->x1; 802 int y = dst->y1; 803 804 if (!crtc_state->pch_pfit.enabled) 805 return; 806 807 /* Force use of hard-coded filter coefficients 808 * as some pre-programmed values are broken, 809 * e.g. x201. 810 */ 811 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) 812 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 813 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe)); 814 else 815 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 816 PF_FILTER_MED_3x3); 817 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 818 PF_WIN_XPOS(x) | PF_WIN_YPOS(y)); 819 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 820 PF_WIN_XSIZE(width) | PF_WIN_YSIZE(height)); 821 } 822 823 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc) 824 { 825 if (crtc->overlay) 826 (void) intel_overlay_switch_off(crtc->overlay); 827 828 /* Let userspace switch the overlay on again. In most cases userspace 829 * has to recompute where to put it anyway. 830 */ 831 } 832 833 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state) 834 { 835 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 836 837 if (!crtc_state->nv12_planes) 838 return false; 839 840 /* WA Display #0827: Gen9:all */ 841 if (DISPLAY_VER(dev_priv) == 9) 842 return true; 843 844 return false; 845 } 846 847 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state) 848 { 849 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 850 851 /* Wa_2006604312:icl,ehl */ 852 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11) 853 return true; 854 855 return false; 856 } 857 858 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state) 859 { 860 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 861 862 /* Wa_1604331009:icl,jsl,ehl */ 863 if (is_hdr_mode(crtc_state) && 864 crtc_state->active_planes & BIT(PLANE_CURSOR) && 865 DISPLAY_VER(dev_priv) == 11) 866 return true; 867 868 return false; 869 } 870 871 static void intel_async_flip_vtd_wa(struct drm_i915_private *i915, 872 enum pipe pipe, bool enable) 873 { 874 if (DISPLAY_VER(i915) == 9) { 875 /* 876 * "Plane N strech max must be programmed to 11b (x1) 877 * when Async flips are enabled on that plane." 878 */ 879 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 880 SKL_PLANE1_STRETCH_MAX_MASK, 881 enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8); 882 } else { 883 /* Also needed on HSW/BDW albeit undocumented */ 884 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 885 HSW_PRI_STRETCH_MAX_MASK, 886 enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8); 887 } 888 } 889 890 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state) 891 { 892 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 893 894 return crtc_state->uapi.async_flip && i915_vtd_active(i915) && 895 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915)); 896 } 897 898 #define is_enabling(feature, old_crtc_state, new_crtc_state) \ 899 ((!(old_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)) && \ 900 (new_crtc_state)->feature) 901 #define is_disabling(feature, old_crtc_state, new_crtc_state) \ 902 ((old_crtc_state)->feature && \ 903 (!(new_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state))) 904 905 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state, 906 const struct intel_crtc_state *new_crtc_state) 907 { 908 return is_enabling(active_planes, old_crtc_state, new_crtc_state); 909 } 910 911 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state, 912 const struct intel_crtc_state *new_crtc_state) 913 { 914 return is_disabling(active_planes, old_crtc_state, new_crtc_state); 915 } 916 917 static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state, 918 const struct intel_crtc_state *new_crtc_state) 919 { 920 return is_enabling(vrr.enable, old_crtc_state, new_crtc_state); 921 } 922 923 static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state, 924 const struct intel_crtc_state *new_crtc_state) 925 { 926 return is_disabling(vrr.enable, old_crtc_state, new_crtc_state); 927 } 928 929 #undef is_disabling 930 #undef is_enabling 931 932 static void intel_post_plane_update(struct intel_atomic_state *state, 933 struct intel_crtc *crtc) 934 { 935 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 936 const struct intel_crtc_state *old_crtc_state = 937 intel_atomic_get_old_crtc_state(state, crtc); 938 const struct intel_crtc_state *new_crtc_state = 939 intel_atomic_get_new_crtc_state(state, crtc); 940 enum pipe pipe = crtc->pipe; 941 942 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); 943 944 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) 945 intel_update_watermarks(dev_priv); 946 947 intel_fbc_post_update(state, crtc); 948 949 if (needs_async_flip_vtd_wa(old_crtc_state) && 950 !needs_async_flip_vtd_wa(new_crtc_state)) 951 intel_async_flip_vtd_wa(dev_priv, pipe, false); 952 953 if (needs_nv12_wa(old_crtc_state) && 954 !needs_nv12_wa(new_crtc_state)) 955 skl_wa_827(dev_priv, pipe, false); 956 957 if (needs_scalerclk_wa(old_crtc_state) && 958 !needs_scalerclk_wa(new_crtc_state)) 959 icl_wa_scalerclkgating(dev_priv, pipe, false); 960 961 if (needs_cursorclk_wa(old_crtc_state) && 962 !needs_cursorclk_wa(new_crtc_state)) 963 icl_wa_cursorclkgating(dev_priv, pipe, false); 964 965 if (intel_crtc_needs_color_update(new_crtc_state)) 966 intel_color_post_update(new_crtc_state); 967 } 968 969 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state, 970 struct intel_crtc *crtc) 971 { 972 const struct intel_crtc_state *crtc_state = 973 intel_atomic_get_new_crtc_state(state, crtc); 974 u8 update_planes = crtc_state->update_planes; 975 const struct intel_plane_state __maybe_unused *plane_state; 976 struct intel_plane *plane; 977 int i; 978 979 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 980 if (plane->pipe == crtc->pipe && 981 update_planes & BIT(plane->id)) 982 plane->enable_flip_done(plane); 983 } 984 } 985 986 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state, 987 struct intel_crtc *crtc) 988 { 989 const struct intel_crtc_state *crtc_state = 990 intel_atomic_get_new_crtc_state(state, crtc); 991 u8 update_planes = crtc_state->update_planes; 992 const struct intel_plane_state __maybe_unused *plane_state; 993 struct intel_plane *plane; 994 int i; 995 996 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 997 if (plane->pipe == crtc->pipe && 998 update_planes & BIT(plane->id)) 999 plane->disable_flip_done(plane); 1000 } 1001 } 1002 1003 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state, 1004 struct intel_crtc *crtc) 1005 { 1006 const struct intel_crtc_state *old_crtc_state = 1007 intel_atomic_get_old_crtc_state(state, crtc); 1008 const struct intel_crtc_state *new_crtc_state = 1009 intel_atomic_get_new_crtc_state(state, crtc); 1010 u8 disable_async_flip_planes = old_crtc_state->async_flip_planes & 1011 ~new_crtc_state->async_flip_planes; 1012 const struct intel_plane_state *old_plane_state; 1013 struct intel_plane *plane; 1014 bool need_vbl_wait = false; 1015 int i; 1016 1017 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1018 if (plane->need_async_flip_disable_wa && 1019 plane->pipe == crtc->pipe && 1020 disable_async_flip_planes & BIT(plane->id)) { 1021 /* 1022 * Apart from the async flip bit we want to 1023 * preserve the old state for the plane. 1024 */ 1025 plane->async_flip(plane, old_crtc_state, 1026 old_plane_state, false); 1027 need_vbl_wait = true; 1028 } 1029 } 1030 1031 if (need_vbl_wait) 1032 intel_crtc_wait_for_next_vblank(crtc); 1033 } 1034 1035 static void intel_pre_plane_update(struct intel_atomic_state *state, 1036 struct intel_crtc *crtc) 1037 { 1038 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1039 const struct intel_crtc_state *old_crtc_state = 1040 intel_atomic_get_old_crtc_state(state, crtc); 1041 const struct intel_crtc_state *new_crtc_state = 1042 intel_atomic_get_new_crtc_state(state, crtc); 1043 enum pipe pipe = crtc->pipe; 1044 1045 if (vrr_disabling(old_crtc_state, new_crtc_state)) { 1046 intel_vrr_disable(old_crtc_state); 1047 intel_crtc_update_active_timings(old_crtc_state, false); 1048 } 1049 1050 intel_drrs_deactivate(old_crtc_state); 1051 1052 intel_psr_pre_plane_update(state, crtc); 1053 1054 if (hsw_ips_pre_update(state, crtc)) 1055 intel_crtc_wait_for_next_vblank(crtc); 1056 1057 if (intel_fbc_pre_update(state, crtc)) 1058 intel_crtc_wait_for_next_vblank(crtc); 1059 1060 if (!needs_async_flip_vtd_wa(old_crtc_state) && 1061 needs_async_flip_vtd_wa(new_crtc_state)) 1062 intel_async_flip_vtd_wa(dev_priv, pipe, true); 1063 1064 /* Display WA 827 */ 1065 if (!needs_nv12_wa(old_crtc_state) && 1066 needs_nv12_wa(new_crtc_state)) 1067 skl_wa_827(dev_priv, pipe, true); 1068 1069 /* Wa_2006604312:icl,ehl */ 1070 if (!needs_scalerclk_wa(old_crtc_state) && 1071 needs_scalerclk_wa(new_crtc_state)) 1072 icl_wa_scalerclkgating(dev_priv, pipe, true); 1073 1074 /* Wa_1604331009:icl,jsl,ehl */ 1075 if (!needs_cursorclk_wa(old_crtc_state) && 1076 needs_cursorclk_wa(new_crtc_state)) 1077 icl_wa_cursorclkgating(dev_priv, pipe, true); 1078 1079 /* 1080 * Vblank time updates from the shadow to live plane control register 1081 * are blocked if the memory self-refresh mode is active at that 1082 * moment. So to make sure the plane gets truly disabled, disable 1083 * first the self-refresh mode. The self-refresh enable bit in turn 1084 * will be checked/applied by the HW only at the next frame start 1085 * event which is after the vblank start event, so we need to have a 1086 * wait-for-vblank between disabling the plane and the pipe. 1087 */ 1088 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active && 1089 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) 1090 intel_crtc_wait_for_next_vblank(crtc); 1091 1092 /* 1093 * IVB workaround: must disable low power watermarks for at least 1094 * one frame before enabling scaling. LP watermarks can be re-enabled 1095 * when scaling is disabled. 1096 * 1097 * WaCxSRDisabledForSpriteScaling:ivb 1098 */ 1099 if (old_crtc_state->hw.active && 1100 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv)) 1101 intel_crtc_wait_for_next_vblank(crtc); 1102 1103 /* 1104 * If we're doing a modeset we don't need to do any 1105 * pre-vblank watermark programming here. 1106 */ 1107 if (!intel_crtc_needs_modeset(new_crtc_state)) { 1108 /* 1109 * For platforms that support atomic watermarks, program the 1110 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these 1111 * will be the intermediate values that are safe for both pre- and 1112 * post- vblank; when vblank happens, the 'active' values will be set 1113 * to the final 'target' values and we'll do this again to get the 1114 * optimal watermarks. For gen9+ platforms, the values we program here 1115 * will be the final target values which will get automatically latched 1116 * at vblank time; no further programming will be necessary. 1117 * 1118 * If a platform hasn't been transitioned to atomic watermarks yet, 1119 * we'll continue to update watermarks the old way, if flags tell 1120 * us to. 1121 */ 1122 if (!intel_initial_watermarks(state, crtc)) 1123 if (new_crtc_state->update_wm_pre) 1124 intel_update_watermarks(dev_priv); 1125 } 1126 1127 /* 1128 * Gen2 reports pipe underruns whenever all planes are disabled. 1129 * So disable underrun reporting before all the planes get disabled. 1130 * 1131 * We do this after .initial_watermarks() so that we have a 1132 * chance of catching underruns with the intermediate watermarks 1133 * vs. the old plane configuration. 1134 */ 1135 if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state)) 1136 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1137 1138 /* 1139 * WA for platforms where async address update enable bit 1140 * is double buffered and only latched at start of vblank. 1141 */ 1142 if (old_crtc_state->async_flip_planes & ~new_crtc_state->async_flip_planes) 1143 intel_crtc_async_flip_disable_wa(state, crtc); 1144 } 1145 1146 static void intel_crtc_disable_planes(struct intel_atomic_state *state, 1147 struct intel_crtc *crtc) 1148 { 1149 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1150 const struct intel_crtc_state *new_crtc_state = 1151 intel_atomic_get_new_crtc_state(state, crtc); 1152 unsigned int update_mask = new_crtc_state->update_planes; 1153 const struct intel_plane_state *old_plane_state; 1154 struct intel_plane *plane; 1155 unsigned fb_bits = 0; 1156 int i; 1157 1158 intel_crtc_dpms_overlay_disable(crtc); 1159 1160 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1161 if (crtc->pipe != plane->pipe || 1162 !(update_mask & BIT(plane->id))) 1163 continue; 1164 1165 intel_plane_disable_arm(plane, new_crtc_state); 1166 1167 if (old_plane_state->uapi.visible) 1168 fb_bits |= plane->frontbuffer_bit; 1169 } 1170 1171 intel_frontbuffer_flip(dev_priv, fb_bits); 1172 } 1173 1174 static void intel_encoders_update_prepare(struct intel_atomic_state *state) 1175 { 1176 struct drm_i915_private *i915 = to_i915(state->base.dev); 1177 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 1178 struct intel_crtc *crtc; 1179 int i; 1180 1181 /* 1182 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits. 1183 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook. 1184 */ 1185 if (i915->display.dpll.mgr) { 1186 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1187 if (intel_crtc_needs_modeset(new_crtc_state)) 1188 continue; 1189 1190 new_crtc_state->shared_dpll = old_crtc_state->shared_dpll; 1191 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state; 1192 } 1193 } 1194 } 1195 1196 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state, 1197 struct intel_crtc *crtc) 1198 { 1199 const struct intel_crtc_state *crtc_state = 1200 intel_atomic_get_new_crtc_state(state, crtc); 1201 const struct drm_connector_state *conn_state; 1202 struct drm_connector *conn; 1203 int i; 1204 1205 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1206 struct intel_encoder *encoder = 1207 to_intel_encoder(conn_state->best_encoder); 1208 1209 if (conn_state->crtc != &crtc->base) 1210 continue; 1211 1212 if (encoder->pre_pll_enable) 1213 encoder->pre_pll_enable(state, encoder, 1214 crtc_state, conn_state); 1215 } 1216 } 1217 1218 static void intel_encoders_pre_enable(struct intel_atomic_state *state, 1219 struct intel_crtc *crtc) 1220 { 1221 const struct intel_crtc_state *crtc_state = 1222 intel_atomic_get_new_crtc_state(state, crtc); 1223 const struct drm_connector_state *conn_state; 1224 struct drm_connector *conn; 1225 int i; 1226 1227 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1228 struct intel_encoder *encoder = 1229 to_intel_encoder(conn_state->best_encoder); 1230 1231 if (conn_state->crtc != &crtc->base) 1232 continue; 1233 1234 if (encoder->pre_enable) 1235 encoder->pre_enable(state, encoder, 1236 crtc_state, conn_state); 1237 } 1238 } 1239 1240 static void intel_encoders_enable(struct intel_atomic_state *state, 1241 struct intel_crtc *crtc) 1242 { 1243 const struct intel_crtc_state *crtc_state = 1244 intel_atomic_get_new_crtc_state(state, crtc); 1245 const struct drm_connector_state *conn_state; 1246 struct drm_connector *conn; 1247 int i; 1248 1249 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1250 struct intel_encoder *encoder = 1251 to_intel_encoder(conn_state->best_encoder); 1252 1253 if (conn_state->crtc != &crtc->base) 1254 continue; 1255 1256 if (encoder->enable) 1257 encoder->enable(state, encoder, 1258 crtc_state, conn_state); 1259 intel_opregion_notify_encoder(encoder, true); 1260 } 1261 } 1262 1263 static void intel_encoders_disable(struct intel_atomic_state *state, 1264 struct intel_crtc *crtc) 1265 { 1266 const struct intel_crtc_state *old_crtc_state = 1267 intel_atomic_get_old_crtc_state(state, crtc); 1268 const struct drm_connector_state *old_conn_state; 1269 struct drm_connector *conn; 1270 int i; 1271 1272 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1273 struct intel_encoder *encoder = 1274 to_intel_encoder(old_conn_state->best_encoder); 1275 1276 if (old_conn_state->crtc != &crtc->base) 1277 continue; 1278 1279 intel_opregion_notify_encoder(encoder, false); 1280 if (encoder->disable) 1281 encoder->disable(state, encoder, 1282 old_crtc_state, old_conn_state); 1283 } 1284 } 1285 1286 static void intel_encoders_post_disable(struct intel_atomic_state *state, 1287 struct intel_crtc *crtc) 1288 { 1289 const struct intel_crtc_state *old_crtc_state = 1290 intel_atomic_get_old_crtc_state(state, crtc); 1291 const struct drm_connector_state *old_conn_state; 1292 struct drm_connector *conn; 1293 int i; 1294 1295 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1296 struct intel_encoder *encoder = 1297 to_intel_encoder(old_conn_state->best_encoder); 1298 1299 if (old_conn_state->crtc != &crtc->base) 1300 continue; 1301 1302 if (encoder->post_disable) 1303 encoder->post_disable(state, encoder, 1304 old_crtc_state, old_conn_state); 1305 } 1306 } 1307 1308 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state, 1309 struct intel_crtc *crtc) 1310 { 1311 const struct intel_crtc_state *old_crtc_state = 1312 intel_atomic_get_old_crtc_state(state, crtc); 1313 const struct drm_connector_state *old_conn_state; 1314 struct drm_connector *conn; 1315 int i; 1316 1317 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1318 struct intel_encoder *encoder = 1319 to_intel_encoder(old_conn_state->best_encoder); 1320 1321 if (old_conn_state->crtc != &crtc->base) 1322 continue; 1323 1324 if (encoder->post_pll_disable) 1325 encoder->post_pll_disable(state, encoder, 1326 old_crtc_state, old_conn_state); 1327 } 1328 } 1329 1330 static void intel_encoders_update_pipe(struct intel_atomic_state *state, 1331 struct intel_crtc *crtc) 1332 { 1333 const struct intel_crtc_state *crtc_state = 1334 intel_atomic_get_new_crtc_state(state, crtc); 1335 const struct drm_connector_state *conn_state; 1336 struct drm_connector *conn; 1337 int i; 1338 1339 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1340 struct intel_encoder *encoder = 1341 to_intel_encoder(conn_state->best_encoder); 1342 1343 if (conn_state->crtc != &crtc->base) 1344 continue; 1345 1346 if (encoder->update_pipe) 1347 encoder->update_pipe(state, encoder, 1348 crtc_state, conn_state); 1349 } 1350 } 1351 1352 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state) 1353 { 1354 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1355 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 1356 1357 plane->disable_arm(plane, crtc_state); 1358 } 1359 1360 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1361 { 1362 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1363 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1364 1365 if (crtc_state->has_pch_encoder) { 1366 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1367 &crtc_state->fdi_m_n); 1368 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1369 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1370 &crtc_state->dp_m_n); 1371 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1372 &crtc_state->dp_m2_n2); 1373 } 1374 1375 intel_set_transcoder_timings(crtc_state); 1376 1377 ilk_set_pipeconf(crtc_state); 1378 } 1379 1380 static void ilk_crtc_enable(struct intel_atomic_state *state, 1381 struct intel_crtc *crtc) 1382 { 1383 const struct intel_crtc_state *new_crtc_state = 1384 intel_atomic_get_new_crtc_state(state, crtc); 1385 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1386 enum pipe pipe = crtc->pipe; 1387 1388 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1389 return; 1390 1391 /* 1392 * Sometimes spurious CPU pipe underruns happen during FDI 1393 * training, at least with VGA+HDMI cloning. Suppress them. 1394 * 1395 * On ILK we get an occasional spurious CPU pipe underruns 1396 * between eDP port A enable and vdd enable. Also PCH port 1397 * enable seems to result in the occasional CPU pipe underrun. 1398 * 1399 * Spurious PCH underruns also occur during PCH enabling. 1400 */ 1401 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1402 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 1403 1404 ilk_configure_cpu_transcoder(new_crtc_state); 1405 1406 intel_set_pipe_src_size(new_crtc_state); 1407 1408 crtc->active = true; 1409 1410 intel_encoders_pre_enable(state, crtc); 1411 1412 if (new_crtc_state->has_pch_encoder) { 1413 ilk_pch_pre_enable(state, crtc); 1414 } else { 1415 assert_fdi_tx_disabled(dev_priv, pipe); 1416 assert_fdi_rx_disabled(dev_priv, pipe); 1417 } 1418 1419 ilk_pfit_enable(new_crtc_state); 1420 1421 /* 1422 * On ILK+ LUT must be loaded before the pipe is running but with 1423 * clocks enabled 1424 */ 1425 intel_color_load_luts(new_crtc_state); 1426 intel_color_commit_noarm(new_crtc_state); 1427 intel_color_commit_arm(new_crtc_state); 1428 /* update DSPCNTR to configure gamma for pipe bottom color */ 1429 intel_disable_primary_plane(new_crtc_state); 1430 1431 intel_initial_watermarks(state, crtc); 1432 intel_enable_transcoder(new_crtc_state); 1433 1434 if (new_crtc_state->has_pch_encoder) 1435 ilk_pch_enable(state, crtc); 1436 1437 intel_crtc_vblank_on(new_crtc_state); 1438 1439 intel_encoders_enable(state, crtc); 1440 1441 if (HAS_PCH_CPT(dev_priv)) 1442 intel_wait_for_pipe_scanline_moving(crtc); 1443 1444 /* 1445 * Must wait for vblank to avoid spurious PCH FIFO underruns. 1446 * And a second vblank wait is needed at least on ILK with 1447 * some interlaced HDMI modes. Let's do the double wait always 1448 * in case there are more corner cases we don't know about. 1449 */ 1450 if (new_crtc_state->has_pch_encoder) { 1451 intel_crtc_wait_for_next_vblank(crtc); 1452 intel_crtc_wait_for_next_vblank(crtc); 1453 } 1454 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1455 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 1456 } 1457 1458 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, 1459 enum pipe pipe, bool apply) 1460 { 1461 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)); 1462 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS; 1463 1464 if (apply) 1465 val |= mask; 1466 else 1467 val &= ~mask; 1468 1469 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val); 1470 } 1471 1472 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state) 1473 { 1474 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1475 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1476 1477 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe), 1478 HSW_LINETIME(crtc_state->linetime) | 1479 HSW_IPS_LINETIME(crtc_state->ips_linetime)); 1480 } 1481 1482 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) 1483 { 1484 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1485 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1486 enum transcoder transcoder = crtc_state->cpu_transcoder; 1487 i915_reg_t reg = DISPLAY_VER(dev_priv) >= 14 ? MTL_CHICKEN_TRANS(transcoder) : 1488 CHICKEN_TRANS(transcoder); 1489 1490 intel_de_rmw(dev_priv, reg, 1491 HSW_FRAME_START_DELAY_MASK, 1492 HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1)); 1493 } 1494 1495 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state, 1496 const struct intel_crtc_state *crtc_state) 1497 { 1498 struct intel_crtc *master_crtc = intel_master_crtc(crtc_state); 1499 1500 /* 1501 * Enable sequence steps 1-7 on bigjoiner master 1502 */ 1503 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1504 intel_encoders_pre_pll_enable(state, master_crtc); 1505 1506 if (crtc_state->shared_dpll) 1507 intel_enable_shared_dpll(crtc_state); 1508 1509 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1510 intel_encoders_pre_enable(state, master_crtc); 1511 } 1512 1513 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1514 { 1515 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1516 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1517 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1518 1519 if (crtc_state->has_pch_encoder) { 1520 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1521 &crtc_state->fdi_m_n); 1522 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1523 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1524 &crtc_state->dp_m_n); 1525 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1526 &crtc_state->dp_m2_n2); 1527 } 1528 1529 intel_set_transcoder_timings(crtc_state); 1530 if (HAS_VRR(dev_priv)) 1531 intel_vrr_set_transcoder_timings(crtc_state); 1532 1533 if (cpu_transcoder != TRANSCODER_EDP) 1534 intel_de_write(dev_priv, TRANS_MULT(cpu_transcoder), 1535 crtc_state->pixel_multiplier - 1); 1536 1537 hsw_set_frame_start_delay(crtc_state); 1538 1539 hsw_set_transconf(crtc_state); 1540 } 1541 1542 static void hsw_crtc_enable(struct intel_atomic_state *state, 1543 struct intel_crtc *crtc) 1544 { 1545 const struct intel_crtc_state *new_crtc_state = 1546 intel_atomic_get_new_crtc_state(state, crtc); 1547 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1548 enum pipe pipe = crtc->pipe, hsw_workaround_pipe; 1549 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 1550 bool psl_clkgate_wa; 1551 1552 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1553 return; 1554 1555 intel_dmc_enable_pipe(dev_priv, crtc->pipe); 1556 1557 if (!new_crtc_state->bigjoiner_pipes) { 1558 intel_encoders_pre_pll_enable(state, crtc); 1559 1560 if (new_crtc_state->shared_dpll) 1561 intel_enable_shared_dpll(new_crtc_state); 1562 1563 intel_encoders_pre_enable(state, crtc); 1564 } else { 1565 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state); 1566 } 1567 1568 intel_dsc_enable(new_crtc_state); 1569 1570 if (DISPLAY_VER(dev_priv) >= 13) 1571 intel_uncompressed_joiner_enable(new_crtc_state); 1572 1573 intel_set_pipe_src_size(new_crtc_state); 1574 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 1575 bdw_set_pipe_misc(new_crtc_state); 1576 1577 if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) && 1578 !transcoder_is_dsi(cpu_transcoder)) 1579 hsw_configure_cpu_transcoder(new_crtc_state); 1580 1581 crtc->active = true; 1582 1583 /* Display WA #1180: WaDisableScalarClockGating: glk */ 1584 psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 && 1585 new_crtc_state->pch_pfit.enabled; 1586 if (psl_clkgate_wa) 1587 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true); 1588 1589 if (DISPLAY_VER(dev_priv) >= 9) 1590 skl_pfit_enable(new_crtc_state); 1591 else 1592 ilk_pfit_enable(new_crtc_state); 1593 1594 /* 1595 * On ILK+ LUT must be loaded before the pipe is running but with 1596 * clocks enabled 1597 */ 1598 intel_color_load_luts(new_crtc_state); 1599 intel_color_commit_noarm(new_crtc_state); 1600 intel_color_commit_arm(new_crtc_state); 1601 /* update DSPCNTR to configure gamma/csc for pipe bottom color */ 1602 if (DISPLAY_VER(dev_priv) < 9) 1603 intel_disable_primary_plane(new_crtc_state); 1604 1605 hsw_set_linetime_wm(new_crtc_state); 1606 1607 if (DISPLAY_VER(dev_priv) >= 11) 1608 icl_set_pipe_chicken(new_crtc_state); 1609 1610 intel_initial_watermarks(state, crtc); 1611 1612 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 1613 intel_crtc_vblank_on(new_crtc_state); 1614 1615 intel_encoders_enable(state, crtc); 1616 1617 if (psl_clkgate_wa) { 1618 intel_crtc_wait_for_next_vblank(crtc); 1619 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false); 1620 } 1621 1622 /* If we change the relative order between pipe/planes enabling, we need 1623 * to change the workaround. */ 1624 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe; 1625 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { 1626 struct intel_crtc *wa_crtc; 1627 1628 wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe); 1629 1630 intel_crtc_wait_for_next_vblank(wa_crtc); 1631 intel_crtc_wait_for_next_vblank(wa_crtc); 1632 } 1633 } 1634 1635 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state) 1636 { 1637 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1638 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1639 enum pipe pipe = crtc->pipe; 1640 1641 /* To avoid upsetting the power well on haswell only disable the pfit if 1642 * it's in use. The hw state code will make sure we get this right. */ 1643 if (!old_crtc_state->pch_pfit.enabled) 1644 return; 1645 1646 intel_de_write_fw(dev_priv, PF_CTL(pipe), 0); 1647 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0); 1648 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0); 1649 } 1650 1651 static void ilk_crtc_disable(struct intel_atomic_state *state, 1652 struct intel_crtc *crtc) 1653 { 1654 const struct intel_crtc_state *old_crtc_state = 1655 intel_atomic_get_old_crtc_state(state, crtc); 1656 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1657 enum pipe pipe = crtc->pipe; 1658 1659 /* 1660 * Sometimes spurious CPU pipe underruns happen when the 1661 * pipe is already disabled, but FDI RX/TX is still enabled. 1662 * Happens at least with VGA+HDMI cloning. Suppress them. 1663 */ 1664 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1665 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 1666 1667 intel_encoders_disable(state, crtc); 1668 1669 intel_crtc_vblank_off(old_crtc_state); 1670 1671 intel_disable_transcoder(old_crtc_state); 1672 1673 ilk_pfit_disable(old_crtc_state); 1674 1675 if (old_crtc_state->has_pch_encoder) 1676 ilk_pch_disable(state, crtc); 1677 1678 intel_encoders_post_disable(state, crtc); 1679 1680 if (old_crtc_state->has_pch_encoder) 1681 ilk_pch_post_disable(state, crtc); 1682 1683 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1684 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 1685 1686 intel_disable_shared_dpll(old_crtc_state); 1687 } 1688 1689 static void hsw_crtc_disable(struct intel_atomic_state *state, 1690 struct intel_crtc *crtc) 1691 { 1692 const struct intel_crtc_state *old_crtc_state = 1693 intel_atomic_get_old_crtc_state(state, crtc); 1694 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 1695 1696 /* 1697 * FIXME collapse everything to one hook. 1698 * Need care with mst->ddi interactions. 1699 */ 1700 if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) { 1701 intel_encoders_disable(state, crtc); 1702 intel_encoders_post_disable(state, crtc); 1703 } 1704 1705 intel_disable_shared_dpll(old_crtc_state); 1706 1707 if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) { 1708 struct intel_crtc *slave_crtc; 1709 1710 intel_encoders_post_pll_disable(state, crtc); 1711 1712 intel_dmc_disable_pipe(i915, crtc->pipe); 1713 1714 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 1715 intel_crtc_bigjoiner_slave_pipes(old_crtc_state)) 1716 intel_dmc_disable_pipe(i915, slave_crtc->pipe); 1717 } 1718 } 1719 1720 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) 1721 { 1722 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1723 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1724 1725 if (!crtc_state->gmch_pfit.control) 1726 return; 1727 1728 /* 1729 * The panel fitter should only be adjusted whilst the pipe is disabled, 1730 * according to register description and PRM. 1731 */ 1732 drm_WARN_ON(&dev_priv->drm, 1733 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE); 1734 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 1735 1736 intel_de_write(dev_priv, PFIT_PGM_RATIOS, 1737 crtc_state->gmch_pfit.pgm_ratios); 1738 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control); 1739 1740 /* Border color in case we don't scale up to the full screen. Black by 1741 * default, change to something else for debugging. */ 1742 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); 1743 } 1744 1745 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) 1746 { 1747 if (phy == PHY_NONE) 1748 return false; 1749 else if (IS_ALDERLAKE_S(dev_priv)) 1750 return phy <= PHY_E; 1751 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) 1752 return phy <= PHY_D; 1753 else if (IS_JSL_EHL(dev_priv)) 1754 return phy <= PHY_C; 1755 else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12)) 1756 return phy <= PHY_B; 1757 else 1758 /* 1759 * DG2 outputs labelled as "combo PHY" in the bspec use 1760 * SNPS PHYs with completely different programming, 1761 * hence we always return false here. 1762 */ 1763 return false; 1764 } 1765 1766 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) 1767 { 1768 if (IS_DG2(dev_priv)) 1769 /* DG2's "TC1" output uses a SNPS PHY */ 1770 return false; 1771 else if (IS_ALDERLAKE_P(dev_priv) || IS_METEORLAKE(dev_priv)) 1772 return phy >= PHY_F && phy <= PHY_I; 1773 else if (IS_TIGERLAKE(dev_priv)) 1774 return phy >= PHY_D && phy <= PHY_I; 1775 else if (IS_ICELAKE(dev_priv)) 1776 return phy >= PHY_C && phy <= PHY_F; 1777 else 1778 return false; 1779 } 1780 1781 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy) 1782 { 1783 if (phy == PHY_NONE) 1784 return false; 1785 else if (IS_DG2(dev_priv)) 1786 /* 1787 * All four "combo" ports and the TC1 port (PHY E) use 1788 * Synopsis PHYs. 1789 */ 1790 return phy <= PHY_E; 1791 1792 return false; 1793 } 1794 1795 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) 1796 { 1797 if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD) 1798 return PHY_D + port - PORT_D_XELPD; 1799 else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1) 1800 return PHY_F + port - PORT_TC1; 1801 else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1) 1802 return PHY_B + port - PORT_TC1; 1803 else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1) 1804 return PHY_C + port - PORT_TC1; 1805 else if (IS_JSL_EHL(i915) && port == PORT_D) 1806 return PHY_A; 1807 1808 return PHY_A + port - PORT_A; 1809 } 1810 1811 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) 1812 { 1813 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port))) 1814 return TC_PORT_NONE; 1815 1816 if (DISPLAY_VER(dev_priv) >= 12) 1817 return TC_PORT_1 + port - PORT_TC1; 1818 else 1819 return TC_PORT_1 + port - PORT_C; 1820 } 1821 1822 enum intel_display_power_domain 1823 intel_aux_power_domain(struct intel_digital_port *dig_port) 1824 { 1825 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1826 1827 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 1828 return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch); 1829 1830 return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch); 1831 } 1832 1833 static void get_crtc_power_domains(struct intel_crtc_state *crtc_state, 1834 struct intel_power_domain_mask *mask) 1835 { 1836 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1837 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1838 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1839 struct drm_encoder *encoder; 1840 enum pipe pipe = crtc->pipe; 1841 1842 bitmap_zero(mask->bits, POWER_DOMAIN_NUM); 1843 1844 if (!crtc_state->hw.active) 1845 return; 1846 1847 set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits); 1848 set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits); 1849 if (crtc_state->pch_pfit.enabled || 1850 crtc_state->pch_pfit.force_thru) 1851 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits); 1852 1853 drm_for_each_encoder_mask(encoder, &dev_priv->drm, 1854 crtc_state->uapi.encoder_mask) { 1855 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 1856 1857 set_bit(intel_encoder->power_domain, mask->bits); 1858 } 1859 1860 if (HAS_DDI(dev_priv) && crtc_state->has_audio) 1861 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits); 1862 1863 if (crtc_state->shared_dpll) 1864 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits); 1865 1866 if (crtc_state->dsc.compression_enable) 1867 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits); 1868 } 1869 1870 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, 1871 struct intel_power_domain_mask *old_domains) 1872 { 1873 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1874 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1875 enum intel_display_power_domain domain; 1876 struct intel_power_domain_mask domains, new_domains; 1877 1878 get_crtc_power_domains(crtc_state, &domains); 1879 1880 bitmap_andnot(new_domains.bits, 1881 domains.bits, 1882 crtc->enabled_power_domains.mask.bits, 1883 POWER_DOMAIN_NUM); 1884 bitmap_andnot(old_domains->bits, 1885 crtc->enabled_power_domains.mask.bits, 1886 domains.bits, 1887 POWER_DOMAIN_NUM); 1888 1889 for_each_power_domain(domain, &new_domains) 1890 intel_display_power_get_in_set(dev_priv, 1891 &crtc->enabled_power_domains, 1892 domain); 1893 } 1894 1895 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc, 1896 struct intel_power_domain_mask *domains) 1897 { 1898 intel_display_power_put_mask_in_set(to_i915(crtc->base.dev), 1899 &crtc->enabled_power_domains, 1900 domains); 1901 } 1902 1903 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1904 { 1905 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1906 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1907 1908 if (intel_crtc_has_dp_encoder(crtc_state)) { 1909 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1910 &crtc_state->dp_m_n); 1911 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1912 &crtc_state->dp_m2_n2); 1913 } 1914 1915 intel_set_transcoder_timings(crtc_state); 1916 1917 i9xx_set_pipeconf(crtc_state); 1918 } 1919 1920 static void valleyview_crtc_enable(struct intel_atomic_state *state, 1921 struct intel_crtc *crtc) 1922 { 1923 const struct intel_crtc_state *new_crtc_state = 1924 intel_atomic_get_new_crtc_state(state, crtc); 1925 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1926 enum pipe pipe = crtc->pipe; 1927 1928 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1929 return; 1930 1931 i9xx_configure_cpu_transcoder(new_crtc_state); 1932 1933 intel_set_pipe_src_size(new_crtc_state); 1934 1935 intel_de_write(dev_priv, VLV_PIPE_MSA_MISC(pipe), 0); 1936 1937 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 1938 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY); 1939 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0); 1940 } 1941 1942 crtc->active = true; 1943 1944 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1945 1946 intel_encoders_pre_pll_enable(state, crtc); 1947 1948 if (IS_CHERRYVIEW(dev_priv)) 1949 chv_enable_pll(new_crtc_state); 1950 else 1951 vlv_enable_pll(new_crtc_state); 1952 1953 intel_encoders_pre_enable(state, crtc); 1954 1955 i9xx_pfit_enable(new_crtc_state); 1956 1957 intel_color_load_luts(new_crtc_state); 1958 intel_color_commit_noarm(new_crtc_state); 1959 intel_color_commit_arm(new_crtc_state); 1960 /* update DSPCNTR to configure gamma for pipe bottom color */ 1961 intel_disable_primary_plane(new_crtc_state); 1962 1963 intel_initial_watermarks(state, crtc); 1964 intel_enable_transcoder(new_crtc_state); 1965 1966 intel_crtc_vblank_on(new_crtc_state); 1967 1968 intel_encoders_enable(state, crtc); 1969 } 1970 1971 static void i9xx_crtc_enable(struct intel_atomic_state *state, 1972 struct intel_crtc *crtc) 1973 { 1974 const struct intel_crtc_state *new_crtc_state = 1975 intel_atomic_get_new_crtc_state(state, crtc); 1976 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1977 enum pipe pipe = crtc->pipe; 1978 1979 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1980 return; 1981 1982 i9xx_configure_cpu_transcoder(new_crtc_state); 1983 1984 intel_set_pipe_src_size(new_crtc_state); 1985 1986 crtc->active = true; 1987 1988 if (DISPLAY_VER(dev_priv) != 2) 1989 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1990 1991 intel_encoders_pre_enable(state, crtc); 1992 1993 i9xx_enable_pll(new_crtc_state); 1994 1995 i9xx_pfit_enable(new_crtc_state); 1996 1997 intel_color_load_luts(new_crtc_state); 1998 intel_color_commit_noarm(new_crtc_state); 1999 intel_color_commit_arm(new_crtc_state); 2000 /* update DSPCNTR to configure gamma for pipe bottom color */ 2001 intel_disable_primary_plane(new_crtc_state); 2002 2003 if (!intel_initial_watermarks(state, crtc)) 2004 intel_update_watermarks(dev_priv); 2005 intel_enable_transcoder(new_crtc_state); 2006 2007 intel_crtc_vblank_on(new_crtc_state); 2008 2009 intel_encoders_enable(state, crtc); 2010 2011 /* prevents spurious underruns */ 2012 if (DISPLAY_VER(dev_priv) == 2) 2013 intel_crtc_wait_for_next_vblank(crtc); 2014 } 2015 2016 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) 2017 { 2018 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 2019 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2020 2021 if (!old_crtc_state->gmch_pfit.control) 2022 return; 2023 2024 assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder); 2025 2026 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n", 2027 intel_de_read(dev_priv, PFIT_CONTROL)); 2028 intel_de_write(dev_priv, PFIT_CONTROL, 0); 2029 } 2030 2031 static void i9xx_crtc_disable(struct intel_atomic_state *state, 2032 struct intel_crtc *crtc) 2033 { 2034 struct intel_crtc_state *old_crtc_state = 2035 intel_atomic_get_old_crtc_state(state, crtc); 2036 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2037 enum pipe pipe = crtc->pipe; 2038 2039 /* 2040 * On gen2 planes are double buffered but the pipe isn't, so we must 2041 * wait for planes to fully turn off before disabling the pipe. 2042 */ 2043 if (DISPLAY_VER(dev_priv) == 2) 2044 intel_crtc_wait_for_next_vblank(crtc); 2045 2046 intel_encoders_disable(state, crtc); 2047 2048 intel_crtc_vblank_off(old_crtc_state); 2049 2050 intel_disable_transcoder(old_crtc_state); 2051 2052 i9xx_pfit_disable(old_crtc_state); 2053 2054 intel_encoders_post_disable(state, crtc); 2055 2056 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) { 2057 if (IS_CHERRYVIEW(dev_priv)) 2058 chv_disable_pll(dev_priv, pipe); 2059 else if (IS_VALLEYVIEW(dev_priv)) 2060 vlv_disable_pll(dev_priv, pipe); 2061 else 2062 i9xx_disable_pll(old_crtc_state); 2063 } 2064 2065 intel_encoders_post_pll_disable(state, crtc); 2066 2067 if (DISPLAY_VER(dev_priv) != 2) 2068 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 2069 2070 if (!dev_priv->display.funcs.wm->initial_watermarks) 2071 intel_update_watermarks(dev_priv); 2072 2073 /* clock the pipe down to 640x480@60 to potentially save power */ 2074 if (IS_I830(dev_priv)) 2075 i830_enable_pipe(dev_priv, pipe); 2076 } 2077 2078 void intel_encoder_destroy(struct drm_encoder *encoder) 2079 { 2080 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2081 2082 drm_encoder_cleanup(encoder); 2083 kfree(intel_encoder); 2084 } 2085 2086 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) 2087 { 2088 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2089 2090 /* GDG double wide on either pipe, otherwise pipe A only */ 2091 return DISPLAY_VER(dev_priv) < 4 && 2092 (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); 2093 } 2094 2095 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) 2096 { 2097 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock; 2098 struct drm_rect src; 2099 2100 /* 2101 * We only use IF-ID interlacing. If we ever use 2102 * PF-ID we'll need to adjust the pixel_rate here. 2103 */ 2104 2105 if (!crtc_state->pch_pfit.enabled) 2106 return pixel_rate; 2107 2108 drm_rect_init(&src, 0, 0, 2109 drm_rect_width(&crtc_state->pipe_src) << 16, 2110 drm_rect_height(&crtc_state->pipe_src) << 16); 2111 2112 return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst, 2113 pixel_rate); 2114 } 2115 2116 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode, 2117 const struct drm_display_mode *timings) 2118 { 2119 mode->hdisplay = timings->crtc_hdisplay; 2120 mode->htotal = timings->crtc_htotal; 2121 mode->hsync_start = timings->crtc_hsync_start; 2122 mode->hsync_end = timings->crtc_hsync_end; 2123 2124 mode->vdisplay = timings->crtc_vdisplay; 2125 mode->vtotal = timings->crtc_vtotal; 2126 mode->vsync_start = timings->crtc_vsync_start; 2127 mode->vsync_end = timings->crtc_vsync_end; 2128 2129 mode->flags = timings->flags; 2130 mode->type = DRM_MODE_TYPE_DRIVER; 2131 2132 mode->clock = timings->crtc_clock; 2133 2134 drm_mode_set_name(mode); 2135 } 2136 2137 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) 2138 { 2139 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2140 2141 if (HAS_GMCH(dev_priv)) 2142 /* FIXME calculate proper pipe pixel rate for GMCH pfit */ 2143 crtc_state->pixel_rate = 2144 crtc_state->hw.pipe_mode.crtc_clock; 2145 else 2146 crtc_state->pixel_rate = 2147 ilk_pipe_pixel_rate(crtc_state); 2148 } 2149 2150 static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state *crtc_state, 2151 struct drm_display_mode *mode) 2152 { 2153 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2154 2155 if (num_pipes < 2) 2156 return; 2157 2158 mode->crtc_clock /= num_pipes; 2159 mode->crtc_hdisplay /= num_pipes; 2160 mode->crtc_hblank_start /= num_pipes; 2161 mode->crtc_hblank_end /= num_pipes; 2162 mode->crtc_hsync_start /= num_pipes; 2163 mode->crtc_hsync_end /= num_pipes; 2164 mode->crtc_htotal /= num_pipes; 2165 } 2166 2167 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state, 2168 struct drm_display_mode *mode) 2169 { 2170 int overlap = crtc_state->splitter.pixel_overlap; 2171 int n = crtc_state->splitter.link_count; 2172 2173 if (!crtc_state->splitter.enable) 2174 return; 2175 2176 /* 2177 * eDP MSO uses segment timings from EDID for transcoder 2178 * timings, but full mode for everything else. 2179 * 2180 * h_full = (h_segment - pixel_overlap) * link_count 2181 */ 2182 mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n; 2183 mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n; 2184 mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n; 2185 mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n; 2186 mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n; 2187 mode->crtc_htotal = (mode->crtc_htotal - overlap) * n; 2188 mode->crtc_clock *= n; 2189 } 2190 2191 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state) 2192 { 2193 struct drm_display_mode *mode = &crtc_state->hw.mode; 2194 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2195 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2196 2197 /* 2198 * Start with the adjusted_mode crtc timings, which 2199 * have been filled with the transcoder timings. 2200 */ 2201 drm_mode_copy(pipe_mode, adjusted_mode); 2202 2203 /* Expand MSO per-segment transcoder timings to full */ 2204 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2205 2206 /* 2207 * We want the full numbers in adjusted_mode normal timings, 2208 * adjusted_mode crtc timings are left with the raw transcoder 2209 * timings. 2210 */ 2211 intel_mode_from_crtc_timings(adjusted_mode, pipe_mode); 2212 2213 /* Populate the "user" mode with full numbers */ 2214 drm_mode_copy(mode, pipe_mode); 2215 intel_mode_from_crtc_timings(mode, mode); 2216 mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) * 2217 (intel_bigjoiner_num_pipes(crtc_state) ?: 1); 2218 mode->vdisplay = drm_rect_height(&crtc_state->pipe_src); 2219 2220 /* Derive per-pipe timings in case bigjoiner is used */ 2221 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2222 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2223 2224 intel_crtc_compute_pixel_rate(crtc_state); 2225 } 2226 2227 void intel_encoder_get_config(struct intel_encoder *encoder, 2228 struct intel_crtc_state *crtc_state) 2229 { 2230 encoder->get_config(encoder, crtc_state); 2231 2232 intel_crtc_readout_derived_state(crtc_state); 2233 } 2234 2235 static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state *crtc_state) 2236 { 2237 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2238 int width, height; 2239 2240 if (num_pipes < 2) 2241 return; 2242 2243 width = drm_rect_width(&crtc_state->pipe_src); 2244 height = drm_rect_height(&crtc_state->pipe_src); 2245 2246 drm_rect_init(&crtc_state->pipe_src, 0, 0, 2247 width / num_pipes, height); 2248 } 2249 2250 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state) 2251 { 2252 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2253 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2254 2255 intel_bigjoiner_compute_pipe_src(crtc_state); 2256 2257 /* 2258 * Pipe horizontal size must be even in: 2259 * - DVO ganged mode 2260 * - LVDS dual channel mode 2261 * - Double wide pipe 2262 */ 2263 if (drm_rect_width(&crtc_state->pipe_src) & 1) { 2264 if (crtc_state->double_wide) { 2265 drm_dbg_kms(&i915->drm, 2266 "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n", 2267 crtc->base.base.id, crtc->base.name); 2268 return -EINVAL; 2269 } 2270 2271 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 2272 intel_is_dual_link_lvds(i915)) { 2273 drm_dbg_kms(&i915->drm, 2274 "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n", 2275 crtc->base.base.id, crtc->base.name); 2276 return -EINVAL; 2277 } 2278 } 2279 2280 return 0; 2281 } 2282 2283 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state) 2284 { 2285 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2286 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2287 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2288 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2289 int clock_limit = i915->max_dotclk_freq; 2290 2291 /* 2292 * Start with the adjusted_mode crtc timings, which 2293 * have been filled with the transcoder timings. 2294 */ 2295 drm_mode_copy(pipe_mode, adjusted_mode); 2296 2297 /* Expand MSO per-segment transcoder timings to full */ 2298 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2299 2300 /* Derive per-pipe timings in case bigjoiner is used */ 2301 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2302 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2303 2304 if (DISPLAY_VER(i915) < 4) { 2305 clock_limit = i915->display.cdclk.max_cdclk_freq * 9 / 10; 2306 2307 /* 2308 * Enable double wide mode when the dot clock 2309 * is > 90% of the (display) core speed. 2310 */ 2311 if (intel_crtc_supports_double_wide(crtc) && 2312 pipe_mode->crtc_clock > clock_limit) { 2313 clock_limit = i915->max_dotclk_freq; 2314 crtc_state->double_wide = true; 2315 } 2316 } 2317 2318 if (pipe_mode->crtc_clock > clock_limit) { 2319 drm_dbg_kms(&i915->drm, 2320 "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", 2321 crtc->base.base.id, crtc->base.name, 2322 pipe_mode->crtc_clock, clock_limit, 2323 str_yes_no(crtc_state->double_wide)); 2324 return -EINVAL; 2325 } 2326 2327 return 0; 2328 } 2329 2330 static int intel_crtc_compute_config(struct intel_atomic_state *state, 2331 struct intel_crtc *crtc) 2332 { 2333 struct intel_crtc_state *crtc_state = 2334 intel_atomic_get_new_crtc_state(state, crtc); 2335 int ret; 2336 2337 ret = intel_dpll_crtc_compute_clock(state, crtc); 2338 if (ret) 2339 return ret; 2340 2341 ret = intel_crtc_compute_pipe_src(crtc_state); 2342 if (ret) 2343 return ret; 2344 2345 ret = intel_crtc_compute_pipe_mode(crtc_state); 2346 if (ret) 2347 return ret; 2348 2349 intel_crtc_compute_pixel_rate(crtc_state); 2350 2351 if (crtc_state->has_pch_encoder) 2352 return ilk_fdi_compute_config(crtc, crtc_state); 2353 2354 return 0; 2355 } 2356 2357 static void 2358 intel_reduce_m_n_ratio(u32 *num, u32 *den) 2359 { 2360 while (*num > DATA_LINK_M_N_MASK || 2361 *den > DATA_LINK_M_N_MASK) { 2362 *num >>= 1; 2363 *den >>= 1; 2364 } 2365 } 2366 2367 static void compute_m_n(u32 *ret_m, u32 *ret_n, 2368 u32 m, u32 n, u32 constant_n) 2369 { 2370 if (constant_n) 2371 *ret_n = constant_n; 2372 else 2373 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); 2374 2375 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n); 2376 intel_reduce_m_n_ratio(ret_m, ret_n); 2377 } 2378 2379 void 2380 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes, 2381 int pixel_clock, int link_clock, 2382 struct intel_link_m_n *m_n, 2383 bool fec_enable) 2384 { 2385 u32 data_clock = bits_per_pixel * pixel_clock; 2386 2387 if (fec_enable) 2388 data_clock = intel_dp_mode_to_fec_clock(data_clock); 2389 2390 /* 2391 * Windows/BIOS uses fixed M/N values always. Follow suit. 2392 * 2393 * Also several DP dongles in particular seem to be fussy 2394 * about too large link M/N values. Presumably the 20bit 2395 * value used by Windows/BIOS is acceptable to everyone. 2396 */ 2397 m_n->tu = 64; 2398 compute_m_n(&m_n->data_m, &m_n->data_n, 2399 data_clock, link_clock * nlanes * 8, 2400 0x8000000); 2401 2402 compute_m_n(&m_n->link_m, &m_n->link_n, 2403 pixel_clock, link_clock, 2404 0x80000); 2405 } 2406 2407 void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv) 2408 { 2409 /* 2410 * There may be no VBT; and if the BIOS enabled SSC we can 2411 * just keep using it to avoid unnecessary flicker. Whereas if the 2412 * BIOS isn't using it, don't assume it will work even if the VBT 2413 * indicates as much. 2414 */ 2415 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { 2416 bool bios_lvds_use_ssc = intel_de_read(dev_priv, 2417 PCH_DREF_CONTROL) & 2418 DREF_SSC1_ENABLE; 2419 2420 if (dev_priv->display.vbt.lvds_use_ssc != bios_lvds_use_ssc) { 2421 drm_dbg_kms(&dev_priv->drm, 2422 "SSC %s by BIOS, overriding VBT which says %s\n", 2423 str_enabled_disabled(bios_lvds_use_ssc), 2424 str_enabled_disabled(dev_priv->display.vbt.lvds_use_ssc)); 2425 dev_priv->display.vbt.lvds_use_ssc = bios_lvds_use_ssc; 2426 } 2427 } 2428 } 2429 2430 void intel_zero_m_n(struct intel_link_m_n *m_n) 2431 { 2432 /* corresponds to 0 register value */ 2433 memset(m_n, 0, sizeof(*m_n)); 2434 m_n->tu = 1; 2435 } 2436 2437 void intel_set_m_n(struct drm_i915_private *i915, 2438 const struct intel_link_m_n *m_n, 2439 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 2440 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 2441 { 2442 intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); 2443 intel_de_write(i915, data_n_reg, m_n->data_n); 2444 intel_de_write(i915, link_m_reg, m_n->link_m); 2445 /* 2446 * On BDW+ writing LINK_N arms the double buffered update 2447 * of all the M/N registers, so it must be written last. 2448 */ 2449 intel_de_write(i915, link_n_reg, m_n->link_n); 2450 } 2451 2452 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, 2453 enum transcoder transcoder) 2454 { 2455 if (IS_HASWELL(dev_priv)) 2456 return transcoder == TRANSCODER_EDP; 2457 2458 return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv); 2459 } 2460 2461 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, 2462 enum transcoder transcoder, 2463 const struct intel_link_m_n *m_n) 2464 { 2465 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2466 enum pipe pipe = crtc->pipe; 2467 2468 if (DISPLAY_VER(dev_priv) >= 5) 2469 intel_set_m_n(dev_priv, m_n, 2470 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 2471 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 2472 else 2473 intel_set_m_n(dev_priv, m_n, 2474 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 2475 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 2476 } 2477 2478 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, 2479 enum transcoder transcoder, 2480 const struct intel_link_m_n *m_n) 2481 { 2482 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2483 2484 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 2485 return; 2486 2487 intel_set_m_n(dev_priv, m_n, 2488 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 2489 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 2490 } 2491 2492 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) 2493 { 2494 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2495 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2496 enum pipe pipe = crtc->pipe; 2497 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2498 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2499 u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end; 2500 int vsyncshift = 0; 2501 2502 /* We need to be careful not to changed the adjusted mode, for otherwise 2503 * the hw state checker will get angry at the mismatch. */ 2504 crtc_vdisplay = adjusted_mode->crtc_vdisplay; 2505 crtc_vtotal = adjusted_mode->crtc_vtotal; 2506 crtc_vblank_start = adjusted_mode->crtc_vblank_start; 2507 crtc_vblank_end = adjusted_mode->crtc_vblank_end; 2508 2509 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 2510 /* the chip adds 2 halflines automatically */ 2511 crtc_vtotal -= 1; 2512 crtc_vblank_end -= 1; 2513 2514 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 2515 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; 2516 else 2517 vsyncshift = adjusted_mode->crtc_hsync_start - 2518 adjusted_mode->crtc_htotal / 2; 2519 if (vsyncshift < 0) 2520 vsyncshift += adjusted_mode->crtc_htotal; 2521 } 2522 2523 /* 2524 * VBLANK_START no longer works on ADL+, instead we must use 2525 * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start. 2526 */ 2527 if (DISPLAY_VER(dev_priv) >= 13) { 2528 intel_de_write(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder), 2529 crtc_vblank_start - crtc_vdisplay); 2530 2531 /* 2532 * VBLANK_START not used by hw, just clear it 2533 * to make it stand out in register dumps. 2534 */ 2535 crtc_vblank_start = 1; 2536 } 2537 2538 if (DISPLAY_VER(dev_priv) > 3) 2539 intel_de_write(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder), 2540 vsyncshift); 2541 2542 intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder), 2543 HACTIVE(adjusted_mode->crtc_hdisplay - 1) | 2544 HTOTAL(adjusted_mode->crtc_htotal - 1)); 2545 intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder), 2546 HBLANK_START(adjusted_mode->crtc_hblank_start - 1) | 2547 HBLANK_END(adjusted_mode->crtc_hblank_end - 1)); 2548 intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder), 2549 HSYNC_START(adjusted_mode->crtc_hsync_start - 1) | 2550 HSYNC_END(adjusted_mode->crtc_hsync_end - 1)); 2551 2552 intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder), 2553 VACTIVE(crtc_vdisplay - 1) | 2554 VTOTAL(crtc_vtotal - 1)); 2555 intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), 2556 VBLANK_START(crtc_vblank_start - 1) | 2557 VBLANK_END(crtc_vblank_end - 1)); 2558 intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder), 2559 VSYNC_START(adjusted_mode->crtc_vsync_start - 1) | 2560 VSYNC_END(adjusted_mode->crtc_vsync_end - 1)); 2561 2562 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be 2563 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is 2564 * documented on the DDI_FUNC_CTL register description, EDP Input Select 2565 * bits. */ 2566 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && 2567 (pipe == PIPE_B || pipe == PIPE_C)) 2568 intel_de_write(dev_priv, TRANS_VTOTAL(pipe), 2569 VACTIVE(crtc_vdisplay - 1) | 2570 VTOTAL(crtc_vtotal - 1)); 2571 } 2572 2573 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) 2574 { 2575 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2576 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2577 int width = drm_rect_width(&crtc_state->pipe_src); 2578 int height = drm_rect_height(&crtc_state->pipe_src); 2579 enum pipe pipe = crtc->pipe; 2580 2581 /* pipesrc controls the size that is scaled from, which should 2582 * always be the user's requested size. 2583 */ 2584 intel_de_write(dev_priv, PIPESRC(pipe), 2585 PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1)); 2586 } 2587 2588 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) 2589 { 2590 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2591 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2592 2593 if (DISPLAY_VER(dev_priv) == 2) 2594 return false; 2595 2596 if (DISPLAY_VER(dev_priv) >= 9 || 2597 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2598 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW; 2599 else 2600 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK; 2601 } 2602 2603 static void intel_get_transcoder_timings(struct intel_crtc *crtc, 2604 struct intel_crtc_state *pipe_config) 2605 { 2606 struct drm_device *dev = crtc->base.dev; 2607 struct drm_i915_private *dev_priv = to_i915(dev); 2608 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 2609 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2610 u32 tmp; 2611 2612 tmp = intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder)); 2613 adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1; 2614 adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1; 2615 2616 if (!transcoder_is_dsi(cpu_transcoder)) { 2617 tmp = intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder)); 2618 adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1; 2619 adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1; 2620 } 2621 2622 tmp = intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder)); 2623 adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1; 2624 adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1; 2625 2626 tmp = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder)); 2627 adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1; 2628 adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1; 2629 2630 /* FIXME TGL+ DSI transcoders have this! */ 2631 if (!transcoder_is_dsi(cpu_transcoder)) { 2632 tmp = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder)); 2633 adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1; 2634 adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1; 2635 } 2636 tmp = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder)); 2637 adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1; 2638 adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1; 2639 2640 if (intel_pipe_is_interlaced(pipe_config)) { 2641 adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE; 2642 adjusted_mode->crtc_vtotal += 1; 2643 adjusted_mode->crtc_vblank_end += 1; 2644 } 2645 2646 if (DISPLAY_VER(dev_priv) >= 13 && !transcoder_is_dsi(cpu_transcoder)) 2647 adjusted_mode->crtc_vblank_start = 2648 adjusted_mode->crtc_vdisplay + 2649 intel_de_read(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder)); 2650 } 2651 2652 static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state) 2653 { 2654 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2655 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2656 enum pipe master_pipe, pipe = crtc->pipe; 2657 int width; 2658 2659 if (num_pipes < 2) 2660 return; 2661 2662 master_pipe = bigjoiner_master_pipe(crtc_state); 2663 width = drm_rect_width(&crtc_state->pipe_src); 2664 2665 drm_rect_translate_to(&crtc_state->pipe_src, 2666 (pipe - master_pipe) * width, 0); 2667 } 2668 2669 static void intel_get_pipe_src_size(struct intel_crtc *crtc, 2670 struct intel_crtc_state *pipe_config) 2671 { 2672 struct drm_device *dev = crtc->base.dev; 2673 struct drm_i915_private *dev_priv = to_i915(dev); 2674 u32 tmp; 2675 2676 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe)); 2677 2678 drm_rect_init(&pipe_config->pipe_src, 0, 0, 2679 REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1, 2680 REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1); 2681 2682 intel_bigjoiner_adjust_pipe_src(pipe_config); 2683 } 2684 2685 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) 2686 { 2687 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2688 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2689 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2690 u32 val = 0; 2691 2692 /* 2693 * - We keep both pipes enabled on 830 2694 * - During modeset the pipe is still disabled and must remain so 2695 * - During fastset the pipe is already enabled and must remain so 2696 */ 2697 if (IS_I830(dev_priv) || !intel_crtc_needs_modeset(crtc_state)) 2698 val |= TRANSCONF_ENABLE; 2699 2700 if (crtc_state->double_wide) 2701 val |= TRANSCONF_DOUBLE_WIDE; 2702 2703 /* only g4x and later have fancy bpc/dither controls */ 2704 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 2705 IS_CHERRYVIEW(dev_priv)) { 2706 /* Bspec claims that we can't use dithering for 30bpp pipes. */ 2707 if (crtc_state->dither && crtc_state->pipe_bpp != 30) 2708 val |= TRANSCONF_DITHER_EN | 2709 TRANSCONF_DITHER_TYPE_SP; 2710 2711 switch (crtc_state->pipe_bpp) { 2712 default: 2713 /* Case prevented by intel_choose_pipe_bpp_dither. */ 2714 MISSING_CASE(crtc_state->pipe_bpp); 2715 fallthrough; 2716 case 18: 2717 val |= TRANSCONF_BPC_6; 2718 break; 2719 case 24: 2720 val |= TRANSCONF_BPC_8; 2721 break; 2722 case 30: 2723 val |= TRANSCONF_BPC_10; 2724 break; 2725 } 2726 } 2727 2728 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 2729 if (DISPLAY_VER(dev_priv) < 4 || 2730 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 2731 val |= TRANSCONF_INTERLACE_W_FIELD_INDICATION; 2732 else 2733 val |= TRANSCONF_INTERLACE_W_SYNC_SHIFT; 2734 } else { 2735 val |= TRANSCONF_INTERLACE_PROGRESSIVE; 2736 } 2737 2738 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 2739 crtc_state->limited_color_range) 2740 val |= TRANSCONF_COLOR_RANGE_SELECT; 2741 2742 val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode); 2743 2744 if (crtc_state->wgc_enable) 2745 val |= TRANSCONF_WGC_ENABLE; 2746 2747 val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 2748 2749 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); 2750 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); 2751 } 2752 2753 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv) 2754 { 2755 if (IS_I830(dev_priv)) 2756 return false; 2757 2758 return DISPLAY_VER(dev_priv) >= 4 || 2759 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); 2760 } 2761 2762 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state) 2763 { 2764 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2765 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2766 enum pipe pipe; 2767 u32 tmp; 2768 2769 if (!i9xx_has_pfit(dev_priv)) 2770 return; 2771 2772 tmp = intel_de_read(dev_priv, PFIT_CONTROL); 2773 if (!(tmp & PFIT_ENABLE)) 2774 return; 2775 2776 /* Check whether the pfit is attached to our pipe. */ 2777 if (DISPLAY_VER(dev_priv) >= 4) 2778 pipe = REG_FIELD_GET(PFIT_PIPE_MASK, tmp); 2779 else 2780 pipe = PIPE_B; 2781 2782 if (pipe != crtc->pipe) 2783 return; 2784 2785 crtc_state->gmch_pfit.control = tmp; 2786 crtc_state->gmch_pfit.pgm_ratios = 2787 intel_de_read(dev_priv, PFIT_PGM_RATIOS); 2788 } 2789 2790 static void vlv_crtc_clock_get(struct intel_crtc *crtc, 2791 struct intel_crtc_state *pipe_config) 2792 { 2793 struct drm_device *dev = crtc->base.dev; 2794 struct drm_i915_private *dev_priv = to_i915(dev); 2795 enum pipe pipe = crtc->pipe; 2796 struct dpll clock; 2797 u32 mdiv; 2798 int refclk = 100000; 2799 2800 /* In case of DSI, DPLL will not be used */ 2801 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 2802 return; 2803 2804 vlv_dpio_get(dev_priv); 2805 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); 2806 vlv_dpio_put(dev_priv); 2807 2808 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; 2809 clock.m2 = mdiv & DPIO_M2DIV_MASK; 2810 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; 2811 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; 2812 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; 2813 2814 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); 2815 } 2816 2817 static void chv_crtc_clock_get(struct intel_crtc *crtc, 2818 struct intel_crtc_state *pipe_config) 2819 { 2820 struct drm_device *dev = crtc->base.dev; 2821 struct drm_i915_private *dev_priv = to_i915(dev); 2822 enum pipe pipe = crtc->pipe; 2823 enum dpio_channel port = vlv_pipe_to_channel(pipe); 2824 struct dpll clock; 2825 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; 2826 int refclk = 100000; 2827 2828 /* In case of DSI, DPLL will not be used */ 2829 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 2830 return; 2831 2832 vlv_dpio_get(dev_priv); 2833 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); 2834 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); 2835 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); 2836 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); 2837 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); 2838 vlv_dpio_put(dev_priv); 2839 2840 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; 2841 clock.m2 = (pll_dw0 & 0xff) << 22; 2842 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) 2843 clock.m2 |= pll_dw2 & 0x3fffff; 2844 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; 2845 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; 2846 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; 2847 2848 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); 2849 } 2850 2851 static enum intel_output_format 2852 bdw_get_pipe_misc_output_format(struct intel_crtc *crtc) 2853 { 2854 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2855 u32 tmp; 2856 2857 tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe)); 2858 2859 if (tmp & PIPE_MISC_YUV420_ENABLE) { 2860 /* We support 4:2:0 in full blend mode only */ 2861 drm_WARN_ON(&dev_priv->drm, 2862 (tmp & PIPE_MISC_YUV420_MODE_FULL_BLEND) == 0); 2863 2864 return INTEL_OUTPUT_FORMAT_YCBCR420; 2865 } else if (tmp & PIPE_MISC_OUTPUT_COLORSPACE_YUV) { 2866 return INTEL_OUTPUT_FORMAT_YCBCR444; 2867 } else { 2868 return INTEL_OUTPUT_FORMAT_RGB; 2869 } 2870 } 2871 2872 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state) 2873 { 2874 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2875 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 2876 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2877 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 2878 u32 tmp; 2879 2880 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); 2881 2882 if (tmp & DISP_PIPE_GAMMA_ENABLE) 2883 crtc_state->gamma_enable = true; 2884 2885 if (!HAS_GMCH(dev_priv) && 2886 tmp & DISP_PIPE_CSC_ENABLE) 2887 crtc_state->csc_enable = true; 2888 } 2889 2890 static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 2891 struct intel_crtc_state *pipe_config) 2892 { 2893 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2894 enum intel_display_power_domain power_domain; 2895 intel_wakeref_t wakeref; 2896 u32 tmp; 2897 bool ret; 2898 2899 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 2900 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 2901 if (!wakeref) 2902 return false; 2903 2904 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 2905 pipe_config->sink_format = pipe_config->output_format; 2906 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 2907 pipe_config->shared_dpll = NULL; 2908 2909 ret = false; 2910 2911 tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder)); 2912 if (!(tmp & TRANSCONF_ENABLE)) 2913 goto out; 2914 2915 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 2916 IS_CHERRYVIEW(dev_priv)) { 2917 switch (tmp & TRANSCONF_BPC_MASK) { 2918 case TRANSCONF_BPC_6: 2919 pipe_config->pipe_bpp = 18; 2920 break; 2921 case TRANSCONF_BPC_8: 2922 pipe_config->pipe_bpp = 24; 2923 break; 2924 case TRANSCONF_BPC_10: 2925 pipe_config->pipe_bpp = 30; 2926 break; 2927 default: 2928 MISSING_CASE(tmp); 2929 break; 2930 } 2931 } 2932 2933 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 2934 (tmp & TRANSCONF_COLOR_RANGE_SELECT)) 2935 pipe_config->limited_color_range = true; 2936 2937 pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp); 2938 2939 pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1; 2940 2941 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 2942 (tmp & TRANSCONF_WGC_ENABLE)) 2943 pipe_config->wgc_enable = true; 2944 2945 if (IS_CHERRYVIEW(dev_priv)) 2946 pipe_config->cgm_mode = intel_de_read(dev_priv, 2947 CGM_PIPE_MODE(crtc->pipe)); 2948 2949 i9xx_get_pipe_color_config(pipe_config); 2950 intel_color_get_config(pipe_config); 2951 2952 if (DISPLAY_VER(dev_priv) < 4) 2953 pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE; 2954 2955 intel_get_transcoder_timings(crtc, pipe_config); 2956 intel_get_pipe_src_size(crtc, pipe_config); 2957 2958 i9xx_get_pfit_config(pipe_config); 2959 2960 if (DISPLAY_VER(dev_priv) >= 4) { 2961 /* No way to read it out on pipes B and C */ 2962 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) 2963 tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe]; 2964 else 2965 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe)); 2966 pipe_config->pixel_multiplier = 2967 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) 2968 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; 2969 pipe_config->dpll_hw_state.dpll_md = tmp; 2970 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 2971 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 2972 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe)); 2973 pipe_config->pixel_multiplier = 2974 ((tmp & SDVO_MULTIPLIER_MASK) 2975 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; 2976 } else { 2977 /* Note that on i915G/GM the pixel multiplier is in the sdvo 2978 * port and will be fixed up in the encoder->get_config 2979 * function. */ 2980 pipe_config->pixel_multiplier = 1; 2981 } 2982 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv, 2983 DPLL(crtc->pipe)); 2984 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 2985 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv, 2986 FP0(crtc->pipe)); 2987 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv, 2988 FP1(crtc->pipe)); 2989 } else { 2990 /* Mask out read-only status bits. */ 2991 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | 2992 DPLL_PORTC_READY_MASK | 2993 DPLL_PORTB_READY_MASK); 2994 } 2995 2996 if (IS_CHERRYVIEW(dev_priv)) 2997 chv_crtc_clock_get(crtc, pipe_config); 2998 else if (IS_VALLEYVIEW(dev_priv)) 2999 vlv_crtc_clock_get(crtc, pipe_config); 3000 else 3001 i9xx_crtc_clock_get(crtc, pipe_config); 3002 3003 /* 3004 * Normally the dotclock is filled in by the encoder .get_config() 3005 * but in case the pipe is enabled w/o any ports we need a sane 3006 * default. 3007 */ 3008 pipe_config->hw.adjusted_mode.crtc_clock = 3009 pipe_config->port_clock / pipe_config->pixel_multiplier; 3010 3011 ret = true; 3012 3013 out: 3014 intel_display_power_put(dev_priv, power_domain, wakeref); 3015 3016 return ret; 3017 } 3018 3019 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) 3020 { 3021 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3022 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3023 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3024 u32 val = 0; 3025 3026 /* 3027 * - During modeset the pipe is still disabled and must remain so 3028 * - During fastset the pipe is already enabled and must remain so 3029 */ 3030 if (!intel_crtc_needs_modeset(crtc_state)) 3031 val |= TRANSCONF_ENABLE; 3032 3033 switch (crtc_state->pipe_bpp) { 3034 default: 3035 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3036 MISSING_CASE(crtc_state->pipe_bpp); 3037 fallthrough; 3038 case 18: 3039 val |= TRANSCONF_BPC_6; 3040 break; 3041 case 24: 3042 val |= TRANSCONF_BPC_8; 3043 break; 3044 case 30: 3045 val |= TRANSCONF_BPC_10; 3046 break; 3047 case 36: 3048 val |= TRANSCONF_BPC_12; 3049 break; 3050 } 3051 3052 if (crtc_state->dither) 3053 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP; 3054 3055 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3056 val |= TRANSCONF_INTERLACE_IF_ID_ILK; 3057 else 3058 val |= TRANSCONF_INTERLACE_PF_PD_ILK; 3059 3060 /* 3061 * This would end up with an odd purple hue over 3062 * the entire display. Make sure we don't do it. 3063 */ 3064 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 3065 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 3066 3067 if (crtc_state->limited_color_range && 3068 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3069 val |= TRANSCONF_COLOR_RANGE_SELECT; 3070 3071 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3072 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV709; 3073 3074 val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode); 3075 3076 val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3077 val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay); 3078 3079 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); 3080 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); 3081 } 3082 3083 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) 3084 { 3085 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3086 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3087 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3088 u32 val = 0; 3089 3090 /* 3091 * - During modeset the pipe is still disabled and must remain so 3092 * - During fastset the pipe is already enabled and must remain so 3093 */ 3094 if (!intel_crtc_needs_modeset(crtc_state)) 3095 val |= TRANSCONF_ENABLE; 3096 3097 if (IS_HASWELL(dev_priv) && crtc_state->dither) 3098 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP; 3099 3100 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3101 val |= TRANSCONF_INTERLACE_IF_ID_ILK; 3102 else 3103 val |= TRANSCONF_INTERLACE_PF_PD_ILK; 3104 3105 if (IS_HASWELL(dev_priv) && 3106 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3107 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW; 3108 3109 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); 3110 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); 3111 } 3112 3113 static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state) 3114 { 3115 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3116 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3117 u32 val = 0; 3118 3119 switch (crtc_state->pipe_bpp) { 3120 case 18: 3121 val |= PIPE_MISC_BPC_6; 3122 break; 3123 case 24: 3124 val |= PIPE_MISC_BPC_8; 3125 break; 3126 case 30: 3127 val |= PIPE_MISC_BPC_10; 3128 break; 3129 case 36: 3130 /* Port output 12BPC defined for ADLP+ */ 3131 if (DISPLAY_VER(dev_priv) > 12) 3132 val |= PIPE_MISC_BPC_12_ADLP; 3133 break; 3134 default: 3135 MISSING_CASE(crtc_state->pipe_bpp); 3136 break; 3137 } 3138 3139 if (crtc_state->dither) 3140 val |= PIPE_MISC_DITHER_ENABLE | PIPE_MISC_DITHER_TYPE_SP; 3141 3142 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 3143 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 3144 val |= PIPE_MISC_OUTPUT_COLORSPACE_YUV; 3145 3146 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 3147 val |= PIPE_MISC_YUV420_ENABLE | 3148 PIPE_MISC_YUV420_MODE_FULL_BLEND; 3149 3150 if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state)) 3151 val |= PIPE_MISC_HDR_MODE_PRECISION; 3152 3153 if (DISPLAY_VER(dev_priv) >= 12) 3154 val |= PIPE_MISC_PIXEL_ROUNDING_TRUNC; 3155 3156 /* allow PSR with sprite enabled */ 3157 if (IS_BROADWELL(dev_priv)) 3158 val |= PIPE_MISC_PSR_MASK_SPRITE_ENABLE; 3159 3160 intel_de_write(dev_priv, PIPE_MISC(crtc->pipe), val); 3161 } 3162 3163 int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc) 3164 { 3165 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3166 u32 tmp; 3167 3168 tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe)); 3169 3170 switch (tmp & PIPE_MISC_BPC_MASK) { 3171 case PIPE_MISC_BPC_6: 3172 return 18; 3173 case PIPE_MISC_BPC_8: 3174 return 24; 3175 case PIPE_MISC_BPC_10: 3176 return 30; 3177 /* 3178 * PORT OUTPUT 12 BPC defined for ADLP+. 3179 * 3180 * TODO: 3181 * For previous platforms with DSI interface, bits 5:7 3182 * are used for storing pipe_bpp irrespective of dithering. 3183 * Since the value of 12 BPC is not defined for these bits 3184 * on older platforms, need to find a workaround for 12 BPC 3185 * MIPI DSI HW readout. 3186 */ 3187 case PIPE_MISC_BPC_12_ADLP: 3188 if (DISPLAY_VER(dev_priv) > 12) 3189 return 36; 3190 fallthrough; 3191 default: 3192 MISSING_CASE(tmp); 3193 return 0; 3194 } 3195 } 3196 3197 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) 3198 { 3199 /* 3200 * Account for spread spectrum to avoid 3201 * oversubscribing the link. Max center spread 3202 * is 2.5%; use 5% for safety's sake. 3203 */ 3204 u32 bps = target_clock * bpp * 21 / 20; 3205 return DIV_ROUND_UP(bps, link_bw * 8); 3206 } 3207 3208 void intel_get_m_n(struct drm_i915_private *i915, 3209 struct intel_link_m_n *m_n, 3210 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 3211 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 3212 { 3213 m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK; 3214 m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK; 3215 m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK; 3216 m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK; 3217 m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1; 3218 } 3219 3220 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, 3221 enum transcoder transcoder, 3222 struct intel_link_m_n *m_n) 3223 { 3224 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3225 enum pipe pipe = crtc->pipe; 3226 3227 if (DISPLAY_VER(dev_priv) >= 5) 3228 intel_get_m_n(dev_priv, m_n, 3229 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 3230 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 3231 else 3232 intel_get_m_n(dev_priv, m_n, 3233 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 3234 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 3235 } 3236 3237 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, 3238 enum transcoder transcoder, 3239 struct intel_link_m_n *m_n) 3240 { 3241 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3242 3243 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 3244 return; 3245 3246 intel_get_m_n(dev_priv, m_n, 3247 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 3248 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 3249 } 3250 3251 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state) 3252 { 3253 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3254 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3255 u32 ctl, pos, size; 3256 enum pipe pipe; 3257 3258 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe)); 3259 if ((ctl & PF_ENABLE) == 0) 3260 return; 3261 3262 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) 3263 pipe = REG_FIELD_GET(PF_PIPE_SEL_MASK_IVB, ctl); 3264 else 3265 pipe = crtc->pipe; 3266 3267 crtc_state->pch_pfit.enabled = true; 3268 3269 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe)); 3270 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe)); 3271 3272 drm_rect_init(&crtc_state->pch_pfit.dst, 3273 REG_FIELD_GET(PF_WIN_XPOS_MASK, pos), 3274 REG_FIELD_GET(PF_WIN_YPOS_MASK, pos), 3275 REG_FIELD_GET(PF_WIN_XSIZE_MASK, size), 3276 REG_FIELD_GET(PF_WIN_YSIZE_MASK, size)); 3277 3278 /* 3279 * We currently do not free assignements of panel fitters on 3280 * ivb/hsw (since we don't use the higher upscaling modes which 3281 * differentiates them) so just WARN about this case for now. 3282 */ 3283 drm_WARN_ON(&dev_priv->drm, pipe != crtc->pipe); 3284 } 3285 3286 static bool ilk_get_pipe_config(struct intel_crtc *crtc, 3287 struct intel_crtc_state *pipe_config) 3288 { 3289 struct drm_device *dev = crtc->base.dev; 3290 struct drm_i915_private *dev_priv = to_i915(dev); 3291 enum intel_display_power_domain power_domain; 3292 intel_wakeref_t wakeref; 3293 u32 tmp; 3294 bool ret; 3295 3296 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3297 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3298 if (!wakeref) 3299 return false; 3300 3301 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3302 pipe_config->shared_dpll = NULL; 3303 3304 ret = false; 3305 tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder)); 3306 if (!(tmp & TRANSCONF_ENABLE)) 3307 goto out; 3308 3309 switch (tmp & TRANSCONF_BPC_MASK) { 3310 case TRANSCONF_BPC_6: 3311 pipe_config->pipe_bpp = 18; 3312 break; 3313 case TRANSCONF_BPC_8: 3314 pipe_config->pipe_bpp = 24; 3315 break; 3316 case TRANSCONF_BPC_10: 3317 pipe_config->pipe_bpp = 30; 3318 break; 3319 case TRANSCONF_BPC_12: 3320 pipe_config->pipe_bpp = 36; 3321 break; 3322 default: 3323 break; 3324 } 3325 3326 if (tmp & TRANSCONF_COLOR_RANGE_SELECT) 3327 pipe_config->limited_color_range = true; 3328 3329 switch (tmp & TRANSCONF_OUTPUT_COLORSPACE_MASK) { 3330 case TRANSCONF_OUTPUT_COLORSPACE_YUV601: 3331 case TRANSCONF_OUTPUT_COLORSPACE_YUV709: 3332 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3333 break; 3334 default: 3335 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3336 break; 3337 } 3338 3339 pipe_config->sink_format = pipe_config->output_format; 3340 3341 pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp); 3342 3343 pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1; 3344 3345 pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp); 3346 3347 pipe_config->csc_mode = intel_de_read(dev_priv, 3348 PIPE_CSC_MODE(crtc->pipe)); 3349 3350 i9xx_get_pipe_color_config(pipe_config); 3351 intel_color_get_config(pipe_config); 3352 3353 pipe_config->pixel_multiplier = 1; 3354 3355 ilk_pch_get_config(pipe_config); 3356 3357 intel_get_transcoder_timings(crtc, pipe_config); 3358 intel_get_pipe_src_size(crtc, pipe_config); 3359 3360 ilk_get_pfit_config(pipe_config); 3361 3362 ret = true; 3363 3364 out: 3365 intel_display_power_put(dev_priv, power_domain, wakeref); 3366 3367 return ret; 3368 } 3369 3370 static u8 bigjoiner_pipes(struct drm_i915_private *i915) 3371 { 3372 u8 pipes; 3373 3374 if (DISPLAY_VER(i915) >= 12) 3375 pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D); 3376 else if (DISPLAY_VER(i915) >= 11) 3377 pipes = BIT(PIPE_B) | BIT(PIPE_C); 3378 else 3379 pipes = 0; 3380 3381 return pipes & DISPLAY_RUNTIME_INFO(i915)->pipe_mask; 3382 } 3383 3384 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv, 3385 enum transcoder cpu_transcoder) 3386 { 3387 enum intel_display_power_domain power_domain; 3388 intel_wakeref_t wakeref; 3389 u32 tmp = 0; 3390 3391 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3392 3393 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3394 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3395 3396 return tmp & TRANS_DDI_FUNC_ENABLE; 3397 } 3398 3399 static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv, 3400 u8 *master_pipes, u8 *slave_pipes) 3401 { 3402 struct intel_crtc *crtc; 3403 3404 *master_pipes = 0; 3405 *slave_pipes = 0; 3406 3407 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, 3408 bigjoiner_pipes(dev_priv)) { 3409 enum intel_display_power_domain power_domain; 3410 enum pipe pipe = crtc->pipe; 3411 intel_wakeref_t wakeref; 3412 3413 power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe); 3414 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3415 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3416 3417 if (!(tmp & BIG_JOINER_ENABLE)) 3418 continue; 3419 3420 if (tmp & MASTER_BIG_JOINER_ENABLE) 3421 *master_pipes |= BIT(pipe); 3422 else 3423 *slave_pipes |= BIT(pipe); 3424 } 3425 3426 if (DISPLAY_VER(dev_priv) < 13) 3427 continue; 3428 3429 power_domain = POWER_DOMAIN_PIPE(pipe); 3430 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3431 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3432 3433 if (tmp & UNCOMPRESSED_JOINER_MASTER) 3434 *master_pipes |= BIT(pipe); 3435 if (tmp & UNCOMPRESSED_JOINER_SLAVE) 3436 *slave_pipes |= BIT(pipe); 3437 } 3438 } 3439 3440 /* Bigjoiner pipes should always be consecutive master and slave */ 3441 drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1, 3442 "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n", 3443 *master_pipes, *slave_pipes); 3444 } 3445 3446 static enum pipe get_bigjoiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3447 { 3448 if ((slave_pipes & BIT(pipe)) == 0) 3449 return pipe; 3450 3451 /* ignore everything above our pipe */ 3452 master_pipes &= ~GENMASK(7, pipe); 3453 3454 /* highest remaining bit should be our master pipe */ 3455 return fls(master_pipes) - 1; 3456 } 3457 3458 static u8 get_bigjoiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3459 { 3460 enum pipe master_pipe, next_master_pipe; 3461 3462 master_pipe = get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes); 3463 3464 if ((master_pipes & BIT(master_pipe)) == 0) 3465 return 0; 3466 3467 /* ignore our master pipe and everything below it */ 3468 master_pipes &= ~GENMASK(master_pipe, 0); 3469 /* make sure a high bit is set for the ffs() */ 3470 master_pipes |= BIT(7); 3471 /* lowest remaining bit should be the next master pipe */ 3472 next_master_pipe = ffs(master_pipes) - 1; 3473 3474 return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe); 3475 } 3476 3477 static u8 hsw_panel_transcoders(struct drm_i915_private *i915) 3478 { 3479 u8 panel_transcoder_mask = BIT(TRANSCODER_EDP); 3480 3481 if (DISPLAY_VER(i915) >= 11) 3482 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); 3483 3484 return panel_transcoder_mask; 3485 } 3486 3487 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) 3488 { 3489 struct drm_device *dev = crtc->base.dev; 3490 struct drm_i915_private *dev_priv = to_i915(dev); 3491 u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv); 3492 enum transcoder cpu_transcoder; 3493 u8 master_pipes, slave_pipes; 3494 u8 enabled_transcoders = 0; 3495 3496 /* 3497 * XXX: Do intel_display_power_get_if_enabled before reading this (for 3498 * consistency and less surprising code; it's in always on power). 3499 */ 3500 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, 3501 panel_transcoder_mask) { 3502 enum intel_display_power_domain power_domain; 3503 intel_wakeref_t wakeref; 3504 enum pipe trans_pipe; 3505 u32 tmp = 0; 3506 3507 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3508 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3509 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3510 3511 if (!(tmp & TRANS_DDI_FUNC_ENABLE)) 3512 continue; 3513 3514 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 3515 default: 3516 drm_WARN(dev, 1, 3517 "unknown pipe linked to transcoder %s\n", 3518 transcoder_name(cpu_transcoder)); 3519 fallthrough; 3520 case TRANS_DDI_EDP_INPUT_A_ONOFF: 3521 case TRANS_DDI_EDP_INPUT_A_ON: 3522 trans_pipe = PIPE_A; 3523 break; 3524 case TRANS_DDI_EDP_INPUT_B_ONOFF: 3525 trans_pipe = PIPE_B; 3526 break; 3527 case TRANS_DDI_EDP_INPUT_C_ONOFF: 3528 trans_pipe = PIPE_C; 3529 break; 3530 case TRANS_DDI_EDP_INPUT_D_ONOFF: 3531 trans_pipe = PIPE_D; 3532 break; 3533 } 3534 3535 if (trans_pipe == crtc->pipe) 3536 enabled_transcoders |= BIT(cpu_transcoder); 3537 } 3538 3539 /* single pipe or bigjoiner master */ 3540 cpu_transcoder = (enum transcoder) crtc->pipe; 3541 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 3542 enabled_transcoders |= BIT(cpu_transcoder); 3543 3544 /* bigjoiner slave -> consider the master pipe's transcoder as well */ 3545 enabled_bigjoiner_pipes(dev_priv, &master_pipes, &slave_pipes); 3546 if (slave_pipes & BIT(crtc->pipe)) { 3547 cpu_transcoder = (enum transcoder) 3548 get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes); 3549 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 3550 enabled_transcoders |= BIT(cpu_transcoder); 3551 } 3552 3553 return enabled_transcoders; 3554 } 3555 3556 static bool has_edp_transcoders(u8 enabled_transcoders) 3557 { 3558 return enabled_transcoders & BIT(TRANSCODER_EDP); 3559 } 3560 3561 static bool has_dsi_transcoders(u8 enabled_transcoders) 3562 { 3563 return enabled_transcoders & (BIT(TRANSCODER_DSI_0) | 3564 BIT(TRANSCODER_DSI_1)); 3565 } 3566 3567 static bool has_pipe_transcoders(u8 enabled_transcoders) 3568 { 3569 return enabled_transcoders & ~(BIT(TRANSCODER_EDP) | 3570 BIT(TRANSCODER_DSI_0) | 3571 BIT(TRANSCODER_DSI_1)); 3572 } 3573 3574 static void assert_enabled_transcoders(struct drm_i915_private *i915, 3575 u8 enabled_transcoders) 3576 { 3577 /* Only one type of transcoder please */ 3578 drm_WARN_ON(&i915->drm, 3579 has_edp_transcoders(enabled_transcoders) + 3580 has_dsi_transcoders(enabled_transcoders) + 3581 has_pipe_transcoders(enabled_transcoders) > 1); 3582 3583 /* Only DSI transcoders can be ganged */ 3584 drm_WARN_ON(&i915->drm, 3585 !has_dsi_transcoders(enabled_transcoders) && 3586 !is_power_of_2(enabled_transcoders)); 3587 } 3588 3589 static bool hsw_get_transcoder_state(struct intel_crtc *crtc, 3590 struct intel_crtc_state *pipe_config, 3591 struct intel_display_power_domain_set *power_domain_set) 3592 { 3593 struct drm_device *dev = crtc->base.dev; 3594 struct drm_i915_private *dev_priv = to_i915(dev); 3595 unsigned long enabled_transcoders; 3596 u32 tmp; 3597 3598 enabled_transcoders = hsw_enabled_transcoders(crtc); 3599 if (!enabled_transcoders) 3600 return false; 3601 3602 assert_enabled_transcoders(dev_priv, enabled_transcoders); 3603 3604 /* 3605 * With the exception of DSI we should only ever have 3606 * a single enabled transcoder. With DSI let's just 3607 * pick the first one. 3608 */ 3609 pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1; 3610 3611 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 3612 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) 3613 return false; 3614 3615 if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) { 3616 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); 3617 3618 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF) 3619 pipe_config->pch_pfit.force_thru = true; 3620 } 3621 3622 tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder)); 3623 3624 return tmp & TRANSCONF_ENABLE; 3625 } 3626 3627 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, 3628 struct intel_crtc_state *pipe_config, 3629 struct intel_display_power_domain_set *power_domain_set) 3630 { 3631 struct drm_device *dev = crtc->base.dev; 3632 struct drm_i915_private *dev_priv = to_i915(dev); 3633 enum transcoder cpu_transcoder; 3634 enum port port; 3635 u32 tmp; 3636 3637 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { 3638 if (port == PORT_A) 3639 cpu_transcoder = TRANSCODER_DSI_A; 3640 else 3641 cpu_transcoder = TRANSCODER_DSI_C; 3642 3643 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 3644 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) 3645 continue; 3646 3647 /* 3648 * The PLL needs to be enabled with a valid divider 3649 * configuration, otherwise accessing DSI registers will hang 3650 * the machine. See BSpec North Display Engine 3651 * registers/MIPI[BXT]. We can break out here early, since we 3652 * need the same DSI PLL to be enabled for both DSI ports. 3653 */ 3654 if (!bxt_dsi_pll_is_enabled(dev_priv)) 3655 break; 3656 3657 /* XXX: this works for video mode only */ 3658 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); 3659 if (!(tmp & DPI_ENABLE)) 3660 continue; 3661 3662 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 3663 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) 3664 continue; 3665 3666 pipe_config->cpu_transcoder = cpu_transcoder; 3667 break; 3668 } 3669 3670 return transcoder_is_dsi(pipe_config->cpu_transcoder); 3671 } 3672 3673 static void intel_bigjoiner_get_config(struct intel_crtc_state *crtc_state) 3674 { 3675 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3676 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 3677 u8 master_pipes, slave_pipes; 3678 enum pipe pipe = crtc->pipe; 3679 3680 enabled_bigjoiner_pipes(i915, &master_pipes, &slave_pipes); 3681 3682 if (((master_pipes | slave_pipes) & BIT(pipe)) == 0) 3683 return; 3684 3685 crtc_state->bigjoiner_pipes = 3686 BIT(get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes)) | 3687 get_bigjoiner_slave_pipes(pipe, master_pipes, slave_pipes); 3688 } 3689 3690 static bool hsw_get_pipe_config(struct intel_crtc *crtc, 3691 struct intel_crtc_state *pipe_config) 3692 { 3693 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3694 bool active; 3695 u32 tmp; 3696 3697 if (!intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains, 3698 POWER_DOMAIN_PIPE(crtc->pipe))) 3699 return false; 3700 3701 pipe_config->shared_dpll = NULL; 3702 3703 active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains); 3704 3705 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 3706 bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) { 3707 drm_WARN_ON(&dev_priv->drm, active); 3708 active = true; 3709 } 3710 3711 if (!active) 3712 goto out; 3713 3714 intel_dsc_get_config(pipe_config); 3715 intel_bigjoiner_get_config(pipe_config); 3716 3717 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || 3718 DISPLAY_VER(dev_priv) >= 11) 3719 intel_get_transcoder_timings(crtc, pipe_config); 3720 3721 if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder)) 3722 intel_vrr_get_config(pipe_config); 3723 3724 intel_get_pipe_src_size(crtc, pipe_config); 3725 3726 if (IS_HASWELL(dev_priv)) { 3727 u32 tmp = intel_de_read(dev_priv, 3728 TRANSCONF(pipe_config->cpu_transcoder)); 3729 3730 if (tmp & TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW) 3731 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3732 else 3733 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3734 } else { 3735 pipe_config->output_format = 3736 bdw_get_pipe_misc_output_format(crtc); 3737 } 3738 3739 pipe_config->sink_format = pipe_config->output_format; 3740 3741 pipe_config->gamma_mode = intel_de_read(dev_priv, 3742 GAMMA_MODE(crtc->pipe)); 3743 3744 pipe_config->csc_mode = intel_de_read(dev_priv, 3745 PIPE_CSC_MODE(crtc->pipe)); 3746 3747 if (DISPLAY_VER(dev_priv) >= 9) { 3748 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe)); 3749 3750 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE) 3751 pipe_config->gamma_enable = true; 3752 3753 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE) 3754 pipe_config->csc_enable = true; 3755 } else { 3756 i9xx_get_pipe_color_config(pipe_config); 3757 } 3758 3759 intel_color_get_config(pipe_config); 3760 3761 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe)); 3762 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); 3763 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 3764 pipe_config->ips_linetime = 3765 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); 3766 3767 if (intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains, 3768 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) { 3769 if (DISPLAY_VER(dev_priv) >= 9) 3770 skl_scaler_get_config(pipe_config); 3771 else 3772 ilk_get_pfit_config(pipe_config); 3773 } 3774 3775 hsw_ips_get_config(pipe_config); 3776 3777 if (pipe_config->cpu_transcoder != TRANSCODER_EDP && 3778 !transcoder_is_dsi(pipe_config->cpu_transcoder)) { 3779 pipe_config->pixel_multiplier = 3780 intel_de_read(dev_priv, 3781 TRANS_MULT(pipe_config->cpu_transcoder)) + 1; 3782 } else { 3783 pipe_config->pixel_multiplier = 1; 3784 } 3785 3786 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { 3787 tmp = intel_de_read(dev_priv, DISPLAY_VER(dev_priv) >= 14 ? 3788 MTL_CHICKEN_TRANS(pipe_config->cpu_transcoder) : 3789 CHICKEN_TRANS(pipe_config->cpu_transcoder)); 3790 3791 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1; 3792 } else { 3793 /* no idea if this is correct */ 3794 pipe_config->framestart_delay = 1; 3795 } 3796 3797 out: 3798 intel_display_power_put_all_in_set(dev_priv, &crtc->hw_readout_power_domains); 3799 3800 return active; 3801 } 3802 3803 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state) 3804 { 3805 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3806 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 3807 3808 if (!i915->display.funcs.display->get_pipe_config(crtc, crtc_state)) 3809 return false; 3810 3811 crtc_state->hw.active = true; 3812 3813 intel_crtc_readout_derived_state(crtc_state); 3814 3815 return true; 3816 } 3817 3818 static int i9xx_pll_refclk(struct drm_device *dev, 3819 const struct intel_crtc_state *pipe_config) 3820 { 3821 struct drm_i915_private *dev_priv = to_i915(dev); 3822 u32 dpll = pipe_config->dpll_hw_state.dpll; 3823 3824 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) 3825 return dev_priv->display.vbt.lvds_ssc_freq; 3826 else if (HAS_PCH_SPLIT(dev_priv)) 3827 return 120000; 3828 else if (DISPLAY_VER(dev_priv) != 2) 3829 return 96000; 3830 else 3831 return 48000; 3832 } 3833 3834 /* Returns the clock of the currently programmed mode of the given pipe. */ 3835 void i9xx_crtc_clock_get(struct intel_crtc *crtc, 3836 struct intel_crtc_state *pipe_config) 3837 { 3838 struct drm_device *dev = crtc->base.dev; 3839 struct drm_i915_private *dev_priv = to_i915(dev); 3840 u32 dpll = pipe_config->dpll_hw_state.dpll; 3841 u32 fp; 3842 struct dpll clock; 3843 int port_clock; 3844 int refclk = i9xx_pll_refclk(dev, pipe_config); 3845 3846 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 3847 fp = pipe_config->dpll_hw_state.fp0; 3848 else 3849 fp = pipe_config->dpll_hw_state.fp1; 3850 3851 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 3852 if (IS_PINEVIEW(dev_priv)) { 3853 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; 3854 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; 3855 } else { 3856 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 3857 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 3858 } 3859 3860 if (DISPLAY_VER(dev_priv) != 2) { 3861 if (IS_PINEVIEW(dev_priv)) 3862 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> 3863 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); 3864 else 3865 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> 3866 DPLL_FPA01_P1_POST_DIV_SHIFT); 3867 3868 switch (dpll & DPLL_MODE_MASK) { 3869 case DPLLB_MODE_DAC_SERIAL: 3870 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 3871 5 : 10; 3872 break; 3873 case DPLLB_MODE_LVDS: 3874 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 3875 7 : 14; 3876 break; 3877 default: 3878 drm_dbg_kms(&dev_priv->drm, 3879 "Unknown DPLL mode %08x in programmed " 3880 "mode\n", (int)(dpll & DPLL_MODE_MASK)); 3881 return; 3882 } 3883 3884 if (IS_PINEVIEW(dev_priv)) 3885 port_clock = pnv_calc_dpll_params(refclk, &clock); 3886 else 3887 port_clock = i9xx_calc_dpll_params(refclk, &clock); 3888 } else { 3889 enum pipe lvds_pipe; 3890 3891 if (IS_I85X(dev_priv) && 3892 intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) && 3893 lvds_pipe == crtc->pipe) { 3894 u32 lvds = intel_de_read(dev_priv, LVDS); 3895 3896 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 3897 DPLL_FPA01_P1_POST_DIV_SHIFT); 3898 3899 if (lvds & LVDS_CLKB_POWER_UP) 3900 clock.p2 = 7; 3901 else 3902 clock.p2 = 14; 3903 } else { 3904 if (dpll & PLL_P1_DIVIDE_BY_TWO) 3905 clock.p1 = 2; 3906 else { 3907 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 3908 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 3909 } 3910 if (dpll & PLL_P2_DIVIDE_BY_4) 3911 clock.p2 = 4; 3912 else 3913 clock.p2 = 2; 3914 } 3915 3916 port_clock = i9xx_calc_dpll_params(refclk, &clock); 3917 } 3918 3919 /* 3920 * This value includes pixel_multiplier. We will use 3921 * port_clock to compute adjusted_mode.crtc_clock in the 3922 * encoder's get_config() function. 3923 */ 3924 pipe_config->port_clock = port_clock; 3925 } 3926 3927 int intel_dotclock_calculate(int link_freq, 3928 const struct intel_link_m_n *m_n) 3929 { 3930 /* 3931 * The calculation for the data clock is: 3932 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp 3933 * But we want to avoid losing precison if possible, so: 3934 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) 3935 * 3936 * and the link clock is simpler: 3937 * link_clock = (m * link_clock) / n 3938 */ 3939 3940 if (!m_n->link_n) 3941 return 0; 3942 3943 return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq), 3944 m_n->link_n); 3945 } 3946 3947 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config) 3948 { 3949 int dotclock; 3950 3951 if (intel_crtc_has_dp_encoder(pipe_config)) 3952 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 3953 &pipe_config->dp_m_n); 3954 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) 3955 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24, 3956 pipe_config->pipe_bpp); 3957 else 3958 dotclock = pipe_config->port_clock; 3959 3960 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 3961 !intel_crtc_has_dp_encoder(pipe_config)) 3962 dotclock *= 2; 3963 3964 if (pipe_config->pixel_multiplier) 3965 dotclock /= pipe_config->pixel_multiplier; 3966 3967 return dotclock; 3968 } 3969 3970 /* Returns the currently programmed mode of the given encoder. */ 3971 struct drm_display_mode * 3972 intel_encoder_current_mode(struct intel_encoder *encoder) 3973 { 3974 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3975 struct intel_crtc_state *crtc_state; 3976 struct drm_display_mode *mode; 3977 struct intel_crtc *crtc; 3978 enum pipe pipe; 3979 3980 if (!encoder->get_hw_state(encoder, &pipe)) 3981 return NULL; 3982 3983 crtc = intel_crtc_for_pipe(dev_priv, pipe); 3984 3985 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 3986 if (!mode) 3987 return NULL; 3988 3989 crtc_state = intel_crtc_state_alloc(crtc); 3990 if (!crtc_state) { 3991 kfree(mode); 3992 return NULL; 3993 } 3994 3995 if (!intel_crtc_get_pipe_config(crtc_state)) { 3996 kfree(crtc_state); 3997 kfree(mode); 3998 return NULL; 3999 } 4000 4001 intel_encoder_get_config(encoder, crtc_state); 4002 4003 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode); 4004 4005 kfree(crtc_state); 4006 4007 return mode; 4008 } 4009 4010 static bool encoders_cloneable(const struct intel_encoder *a, 4011 const struct intel_encoder *b) 4012 { 4013 /* masks could be asymmetric, so check both ways */ 4014 return a == b || (a->cloneable & BIT(b->type) && 4015 b->cloneable & BIT(a->type)); 4016 } 4017 4018 static bool check_single_encoder_cloning(struct intel_atomic_state *state, 4019 struct intel_crtc *crtc, 4020 struct intel_encoder *encoder) 4021 { 4022 struct intel_encoder *source_encoder; 4023 struct drm_connector *connector; 4024 struct drm_connector_state *connector_state; 4025 int i; 4026 4027 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4028 if (connector_state->crtc != &crtc->base) 4029 continue; 4030 4031 source_encoder = 4032 to_intel_encoder(connector_state->best_encoder); 4033 if (!encoders_cloneable(encoder, source_encoder)) 4034 return false; 4035 } 4036 4037 return true; 4038 } 4039 4040 static int icl_add_linked_planes(struct intel_atomic_state *state) 4041 { 4042 struct intel_plane *plane, *linked; 4043 struct intel_plane_state *plane_state, *linked_plane_state; 4044 int i; 4045 4046 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4047 linked = plane_state->planar_linked_plane; 4048 4049 if (!linked) 4050 continue; 4051 4052 linked_plane_state = intel_atomic_get_plane_state(state, linked); 4053 if (IS_ERR(linked_plane_state)) 4054 return PTR_ERR(linked_plane_state); 4055 4056 drm_WARN_ON(state->base.dev, 4057 linked_plane_state->planar_linked_plane != plane); 4058 drm_WARN_ON(state->base.dev, 4059 linked_plane_state->planar_slave == plane_state->planar_slave); 4060 } 4061 4062 return 0; 4063 } 4064 4065 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state) 4066 { 4067 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4068 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4069 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 4070 struct intel_plane *plane, *linked; 4071 struct intel_plane_state *plane_state; 4072 int i; 4073 4074 if (DISPLAY_VER(dev_priv) < 11) 4075 return 0; 4076 4077 /* 4078 * Destroy all old plane links and make the slave plane invisible 4079 * in the crtc_state->active_planes mask. 4080 */ 4081 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4082 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane) 4083 continue; 4084 4085 plane_state->planar_linked_plane = NULL; 4086 if (plane_state->planar_slave && !plane_state->uapi.visible) { 4087 crtc_state->enabled_planes &= ~BIT(plane->id); 4088 crtc_state->active_planes &= ~BIT(plane->id); 4089 crtc_state->update_planes |= BIT(plane->id); 4090 crtc_state->data_rate[plane->id] = 0; 4091 crtc_state->rel_data_rate[plane->id] = 0; 4092 } 4093 4094 plane_state->planar_slave = false; 4095 } 4096 4097 if (!crtc_state->nv12_planes) 4098 return 0; 4099 4100 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4101 struct intel_plane_state *linked_state = NULL; 4102 4103 if (plane->pipe != crtc->pipe || 4104 !(crtc_state->nv12_planes & BIT(plane->id))) 4105 continue; 4106 4107 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) { 4108 if (!icl_is_nv12_y_plane(dev_priv, linked->id)) 4109 continue; 4110 4111 if (crtc_state->active_planes & BIT(linked->id)) 4112 continue; 4113 4114 linked_state = intel_atomic_get_plane_state(state, linked); 4115 if (IS_ERR(linked_state)) 4116 return PTR_ERR(linked_state); 4117 4118 break; 4119 } 4120 4121 if (!linked_state) { 4122 drm_dbg_kms(&dev_priv->drm, 4123 "Need %d free Y planes for planar YUV\n", 4124 hweight8(crtc_state->nv12_planes)); 4125 4126 return -EINVAL; 4127 } 4128 4129 plane_state->planar_linked_plane = linked; 4130 4131 linked_state->planar_slave = true; 4132 linked_state->planar_linked_plane = plane; 4133 crtc_state->enabled_planes |= BIT(linked->id); 4134 crtc_state->active_planes |= BIT(linked->id); 4135 crtc_state->update_planes |= BIT(linked->id); 4136 crtc_state->data_rate[linked->id] = 4137 crtc_state->data_rate_y[plane->id]; 4138 crtc_state->rel_data_rate[linked->id] = 4139 crtc_state->rel_data_rate_y[plane->id]; 4140 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n", 4141 linked->base.name, plane->base.name); 4142 4143 /* Copy parameters to slave plane */ 4144 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE; 4145 linked_state->color_ctl = plane_state->color_ctl; 4146 linked_state->view = plane_state->view; 4147 linked_state->decrypt = plane_state->decrypt; 4148 4149 intel_plane_copy_hw_state(linked_state, plane_state); 4150 linked_state->uapi.src = plane_state->uapi.src; 4151 linked_state->uapi.dst = plane_state->uapi.dst; 4152 4153 if (icl_is_hdr_plane(dev_priv, plane->id)) { 4154 if (linked->id == PLANE_SPRITE5) 4155 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL; 4156 else if (linked->id == PLANE_SPRITE4) 4157 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL; 4158 else if (linked->id == PLANE_SPRITE3) 4159 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL; 4160 else if (linked->id == PLANE_SPRITE2) 4161 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL; 4162 else 4163 MISSING_CASE(linked->id); 4164 } 4165 } 4166 4167 return 0; 4168 } 4169 4170 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state) 4171 { 4172 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 4173 struct intel_atomic_state *state = 4174 to_intel_atomic_state(new_crtc_state->uapi.state); 4175 const struct intel_crtc_state *old_crtc_state = 4176 intel_atomic_get_old_crtc_state(state, crtc); 4177 4178 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes; 4179 } 4180 4181 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) 4182 { 4183 const struct drm_display_mode *pipe_mode = 4184 &crtc_state->hw.pipe_mode; 4185 int linetime_wm; 4186 4187 if (!crtc_state->hw.enable) 4188 return 0; 4189 4190 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4191 pipe_mode->crtc_clock); 4192 4193 return min(linetime_wm, 0x1ff); 4194 } 4195 4196 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, 4197 const struct intel_cdclk_state *cdclk_state) 4198 { 4199 const struct drm_display_mode *pipe_mode = 4200 &crtc_state->hw.pipe_mode; 4201 int linetime_wm; 4202 4203 if (!crtc_state->hw.enable) 4204 return 0; 4205 4206 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4207 cdclk_state->logical.cdclk); 4208 4209 return min(linetime_wm, 0x1ff); 4210 } 4211 4212 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) 4213 { 4214 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4215 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4216 const struct drm_display_mode *pipe_mode = 4217 &crtc_state->hw.pipe_mode; 4218 int linetime_wm; 4219 4220 if (!crtc_state->hw.enable) 4221 return 0; 4222 4223 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8, 4224 crtc_state->pixel_rate); 4225 4226 /* Display WA #1135: BXT:ALL GLK:ALL */ 4227 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 4228 skl_watermark_ipc_enabled(dev_priv)) 4229 linetime_wm /= 2; 4230 4231 return min(linetime_wm, 0x1ff); 4232 } 4233 4234 static int hsw_compute_linetime_wm(struct intel_atomic_state *state, 4235 struct intel_crtc *crtc) 4236 { 4237 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4238 struct intel_crtc_state *crtc_state = 4239 intel_atomic_get_new_crtc_state(state, crtc); 4240 const struct intel_cdclk_state *cdclk_state; 4241 4242 if (DISPLAY_VER(dev_priv) >= 9) 4243 crtc_state->linetime = skl_linetime_wm(crtc_state); 4244 else 4245 crtc_state->linetime = hsw_linetime_wm(crtc_state); 4246 4247 if (!hsw_crtc_supports_ips(crtc)) 4248 return 0; 4249 4250 cdclk_state = intel_atomic_get_cdclk_state(state); 4251 if (IS_ERR(cdclk_state)) 4252 return PTR_ERR(cdclk_state); 4253 4254 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state, 4255 cdclk_state); 4256 4257 return 0; 4258 } 4259 4260 static int intel_crtc_atomic_check(struct intel_atomic_state *state, 4261 struct intel_crtc *crtc) 4262 { 4263 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4264 struct intel_crtc_state *crtc_state = 4265 intel_atomic_get_new_crtc_state(state, crtc); 4266 int ret; 4267 4268 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) && 4269 intel_crtc_needs_modeset(crtc_state) && 4270 !crtc_state->hw.active) 4271 crtc_state->update_wm_post = true; 4272 4273 if (intel_crtc_needs_modeset(crtc_state)) { 4274 ret = intel_dpll_crtc_get_shared_dpll(state, crtc); 4275 if (ret) 4276 return ret; 4277 } 4278 4279 /* 4280 * May need to update pipe gamma enable bits 4281 * when C8 planes are getting enabled/disabled. 4282 */ 4283 if (c8_planes_changed(crtc_state)) 4284 crtc_state->uapi.color_mgmt_changed = true; 4285 4286 if (intel_crtc_needs_color_update(crtc_state)) { 4287 ret = intel_color_check(crtc_state); 4288 if (ret) 4289 return ret; 4290 } 4291 4292 ret = intel_compute_pipe_wm(state, crtc); 4293 if (ret) { 4294 drm_dbg_kms(&dev_priv->drm, 4295 "Target pipe watermarks are invalid\n"); 4296 return ret; 4297 } 4298 4299 /* 4300 * Calculate 'intermediate' watermarks that satisfy both the 4301 * old state and the new state. We can program these 4302 * immediately. 4303 */ 4304 ret = intel_compute_intermediate_wm(state, crtc); 4305 if (ret) { 4306 drm_dbg_kms(&dev_priv->drm, 4307 "No valid intermediate pipe watermarks are possible\n"); 4308 return ret; 4309 } 4310 4311 if (DISPLAY_VER(dev_priv) >= 9) { 4312 if (intel_crtc_needs_modeset(crtc_state) || 4313 intel_crtc_needs_fastset(crtc_state)) { 4314 ret = skl_update_scaler_crtc(crtc_state); 4315 if (ret) 4316 return ret; 4317 } 4318 4319 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state); 4320 if (ret) 4321 return ret; 4322 } 4323 4324 if (HAS_IPS(dev_priv)) { 4325 ret = hsw_ips_compute_config(state, crtc); 4326 if (ret) 4327 return ret; 4328 } 4329 4330 if (DISPLAY_VER(dev_priv) >= 9 || 4331 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 4332 ret = hsw_compute_linetime_wm(state, crtc); 4333 if (ret) 4334 return ret; 4335 4336 } 4337 4338 ret = intel_psr2_sel_fetch_update(state, crtc); 4339 if (ret) 4340 return ret; 4341 4342 return 0; 4343 } 4344 4345 static int 4346 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state, 4347 struct intel_crtc_state *crtc_state) 4348 { 4349 struct drm_connector *connector = conn_state->connector; 4350 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 4351 const struct drm_display_info *info = &connector->display_info; 4352 int bpp; 4353 4354 switch (conn_state->max_bpc) { 4355 case 6 ... 7: 4356 bpp = 6 * 3; 4357 break; 4358 case 8 ... 9: 4359 bpp = 8 * 3; 4360 break; 4361 case 10 ... 11: 4362 bpp = 10 * 3; 4363 break; 4364 case 12 ... 16: 4365 bpp = 12 * 3; 4366 break; 4367 default: 4368 MISSING_CASE(conn_state->max_bpc); 4369 return -EINVAL; 4370 } 4371 4372 if (bpp < crtc_state->pipe_bpp) { 4373 drm_dbg_kms(&i915->drm, 4374 "[CONNECTOR:%d:%s] Limiting display bpp to %d " 4375 "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n", 4376 connector->base.id, connector->name, 4377 bpp, 3 * info->bpc, 4378 3 * conn_state->max_requested_bpc, 4379 crtc_state->pipe_bpp); 4380 4381 crtc_state->pipe_bpp = bpp; 4382 } 4383 4384 return 0; 4385 } 4386 4387 static int 4388 compute_baseline_pipe_bpp(struct intel_atomic_state *state, 4389 struct intel_crtc *crtc) 4390 { 4391 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4392 struct intel_crtc_state *crtc_state = 4393 intel_atomic_get_new_crtc_state(state, crtc); 4394 struct drm_connector *connector; 4395 struct drm_connector_state *connector_state; 4396 int bpp, i; 4397 4398 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 4399 IS_CHERRYVIEW(dev_priv))) 4400 bpp = 10*3; 4401 else if (DISPLAY_VER(dev_priv) >= 5) 4402 bpp = 12*3; 4403 else 4404 bpp = 8*3; 4405 4406 crtc_state->pipe_bpp = bpp; 4407 4408 /* Clamp display bpp to connector max bpp */ 4409 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4410 int ret; 4411 4412 if (connector_state->crtc != &crtc->base) 4413 continue; 4414 4415 ret = compute_sink_pipe_bpp(connector_state, crtc_state); 4416 if (ret) 4417 return ret; 4418 } 4419 4420 return 0; 4421 } 4422 4423 static bool check_digital_port_conflicts(struct intel_atomic_state *state) 4424 { 4425 struct drm_device *dev = state->base.dev; 4426 struct drm_connector *connector; 4427 struct drm_connector_list_iter conn_iter; 4428 unsigned int used_ports = 0; 4429 unsigned int used_mst_ports = 0; 4430 bool ret = true; 4431 4432 /* 4433 * We're going to peek into connector->state, 4434 * hence connection_mutex must be held. 4435 */ 4436 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex); 4437 4438 /* 4439 * Walk the connector list instead of the encoder 4440 * list to detect the problem on ddi platforms 4441 * where there's just one encoder per digital port. 4442 */ 4443 drm_connector_list_iter_begin(dev, &conn_iter); 4444 drm_for_each_connector_iter(connector, &conn_iter) { 4445 struct drm_connector_state *connector_state; 4446 struct intel_encoder *encoder; 4447 4448 connector_state = 4449 drm_atomic_get_new_connector_state(&state->base, 4450 connector); 4451 if (!connector_state) 4452 connector_state = connector->state; 4453 4454 if (!connector_state->best_encoder) 4455 continue; 4456 4457 encoder = to_intel_encoder(connector_state->best_encoder); 4458 4459 drm_WARN_ON(dev, !connector_state->crtc); 4460 4461 switch (encoder->type) { 4462 case INTEL_OUTPUT_DDI: 4463 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev)))) 4464 break; 4465 fallthrough; 4466 case INTEL_OUTPUT_DP: 4467 case INTEL_OUTPUT_HDMI: 4468 case INTEL_OUTPUT_EDP: 4469 /* the same port mustn't appear more than once */ 4470 if (used_ports & BIT(encoder->port)) 4471 ret = false; 4472 4473 used_ports |= BIT(encoder->port); 4474 break; 4475 case INTEL_OUTPUT_DP_MST: 4476 used_mst_ports |= 4477 1 << encoder->port; 4478 break; 4479 default: 4480 break; 4481 } 4482 } 4483 drm_connector_list_iter_end(&conn_iter); 4484 4485 /* can't mix MST and SST/HDMI on the same port */ 4486 if (used_ports & used_mst_ports) 4487 return false; 4488 4489 return ret; 4490 } 4491 4492 static void 4493 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state, 4494 struct intel_crtc *crtc) 4495 { 4496 struct intel_crtc_state *crtc_state = 4497 intel_atomic_get_new_crtc_state(state, crtc); 4498 4499 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 4500 4501 drm_property_replace_blob(&crtc_state->hw.degamma_lut, 4502 crtc_state->uapi.degamma_lut); 4503 drm_property_replace_blob(&crtc_state->hw.gamma_lut, 4504 crtc_state->uapi.gamma_lut); 4505 drm_property_replace_blob(&crtc_state->hw.ctm, 4506 crtc_state->uapi.ctm); 4507 } 4508 4509 static void 4510 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state, 4511 struct intel_crtc *crtc) 4512 { 4513 struct intel_crtc_state *crtc_state = 4514 intel_atomic_get_new_crtc_state(state, crtc); 4515 4516 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 4517 4518 crtc_state->hw.enable = crtc_state->uapi.enable; 4519 crtc_state->hw.active = crtc_state->uapi.active; 4520 drm_mode_copy(&crtc_state->hw.mode, 4521 &crtc_state->uapi.mode); 4522 drm_mode_copy(&crtc_state->hw.adjusted_mode, 4523 &crtc_state->uapi.adjusted_mode); 4524 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter; 4525 4526 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 4527 } 4528 4529 static void 4530 copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state, 4531 struct intel_crtc *slave_crtc) 4532 { 4533 struct intel_crtc_state *slave_crtc_state = 4534 intel_atomic_get_new_crtc_state(state, slave_crtc); 4535 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 4536 const struct intel_crtc_state *master_crtc_state = 4537 intel_atomic_get_new_crtc_state(state, master_crtc); 4538 4539 drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut, 4540 master_crtc_state->hw.degamma_lut); 4541 drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut, 4542 master_crtc_state->hw.gamma_lut); 4543 drm_property_replace_blob(&slave_crtc_state->hw.ctm, 4544 master_crtc_state->hw.ctm); 4545 4546 slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed; 4547 } 4548 4549 static int 4550 copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state, 4551 struct intel_crtc *slave_crtc) 4552 { 4553 struct intel_crtc_state *slave_crtc_state = 4554 intel_atomic_get_new_crtc_state(state, slave_crtc); 4555 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 4556 const struct intel_crtc_state *master_crtc_state = 4557 intel_atomic_get_new_crtc_state(state, master_crtc); 4558 struct intel_crtc_state *saved_state; 4559 4560 WARN_ON(master_crtc_state->bigjoiner_pipes != 4561 slave_crtc_state->bigjoiner_pipes); 4562 4563 saved_state = kmemdup(master_crtc_state, sizeof(*saved_state), GFP_KERNEL); 4564 if (!saved_state) 4565 return -ENOMEM; 4566 4567 /* preserve some things from the slave's original crtc state */ 4568 saved_state->uapi = slave_crtc_state->uapi; 4569 saved_state->scaler_state = slave_crtc_state->scaler_state; 4570 saved_state->shared_dpll = slave_crtc_state->shared_dpll; 4571 saved_state->dpll_hw_state = slave_crtc_state->dpll_hw_state; 4572 saved_state->crc_enabled = slave_crtc_state->crc_enabled; 4573 4574 intel_crtc_free_hw_state(slave_crtc_state); 4575 memcpy(slave_crtc_state, saved_state, sizeof(*slave_crtc_state)); 4576 kfree(saved_state); 4577 4578 /* Re-init hw state */ 4579 memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw)); 4580 slave_crtc_state->hw.enable = master_crtc_state->hw.enable; 4581 slave_crtc_state->hw.active = master_crtc_state->hw.active; 4582 drm_mode_copy(&slave_crtc_state->hw.mode, 4583 &master_crtc_state->hw.mode); 4584 drm_mode_copy(&slave_crtc_state->hw.pipe_mode, 4585 &master_crtc_state->hw.pipe_mode); 4586 drm_mode_copy(&slave_crtc_state->hw.adjusted_mode, 4587 &master_crtc_state->hw.adjusted_mode); 4588 slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter; 4589 4590 copy_bigjoiner_crtc_state_nomodeset(state, slave_crtc); 4591 4592 slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed; 4593 slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed; 4594 slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed; 4595 4596 WARN_ON(master_crtc_state->bigjoiner_pipes != 4597 slave_crtc_state->bigjoiner_pipes); 4598 4599 return 0; 4600 } 4601 4602 static int 4603 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state, 4604 struct intel_crtc *crtc) 4605 { 4606 struct intel_crtc_state *crtc_state = 4607 intel_atomic_get_new_crtc_state(state, crtc); 4608 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4609 struct intel_crtc_state *saved_state; 4610 4611 saved_state = intel_crtc_state_alloc(crtc); 4612 if (!saved_state) 4613 return -ENOMEM; 4614 4615 /* free the old crtc_state->hw members */ 4616 intel_crtc_free_hw_state(crtc_state); 4617 4618 /* FIXME: before the switch to atomic started, a new pipe_config was 4619 * kzalloc'd. Code that depends on any field being zero should be 4620 * fixed, so that the crtc_state can be safely duplicated. For now, 4621 * only fields that are know to not cause problems are preserved. */ 4622 4623 saved_state->uapi = crtc_state->uapi; 4624 saved_state->inherited = crtc_state->inherited; 4625 saved_state->scaler_state = crtc_state->scaler_state; 4626 saved_state->shared_dpll = crtc_state->shared_dpll; 4627 saved_state->dpll_hw_state = crtc_state->dpll_hw_state; 4628 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, 4629 sizeof(saved_state->icl_port_dplls)); 4630 saved_state->crc_enabled = crtc_state->crc_enabled; 4631 if (IS_G4X(dev_priv) || 4632 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 4633 saved_state->wm = crtc_state->wm; 4634 4635 memcpy(crtc_state, saved_state, sizeof(*crtc_state)); 4636 kfree(saved_state); 4637 4638 intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc); 4639 4640 return 0; 4641 } 4642 4643 static int 4644 intel_modeset_pipe_config(struct intel_atomic_state *state, 4645 struct intel_crtc *crtc) 4646 { 4647 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4648 struct intel_crtc_state *crtc_state = 4649 intel_atomic_get_new_crtc_state(state, crtc); 4650 struct drm_connector *connector; 4651 struct drm_connector_state *connector_state; 4652 int pipe_src_w, pipe_src_h; 4653 int base_bpp, ret, i; 4654 bool retry = true; 4655 4656 crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe; 4657 4658 crtc_state->framestart_delay = 1; 4659 4660 /* 4661 * Sanitize sync polarity flags based on requested ones. If neither 4662 * positive or negative polarity is requested, treat this as meaning 4663 * negative polarity. 4664 */ 4665 if (!(crtc_state->hw.adjusted_mode.flags & 4666 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) 4667 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; 4668 4669 if (!(crtc_state->hw.adjusted_mode.flags & 4670 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 4671 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; 4672 4673 ret = compute_baseline_pipe_bpp(state, crtc); 4674 if (ret) 4675 return ret; 4676 4677 base_bpp = crtc_state->pipe_bpp; 4678 4679 /* 4680 * Determine the real pipe dimensions. Note that stereo modes can 4681 * increase the actual pipe size due to the frame doubling and 4682 * insertion of additional space for blanks between the frame. This 4683 * is stored in the crtc timings. We use the requested mode to do this 4684 * computation to clearly distinguish it from the adjusted mode, which 4685 * can be changed by the connectors in the below retry loop. 4686 */ 4687 drm_mode_get_hv_timing(&crtc_state->hw.mode, 4688 &pipe_src_w, &pipe_src_h); 4689 drm_rect_init(&crtc_state->pipe_src, 0, 0, 4690 pipe_src_w, pipe_src_h); 4691 4692 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4693 struct intel_encoder *encoder = 4694 to_intel_encoder(connector_state->best_encoder); 4695 4696 if (connector_state->crtc != &crtc->base) 4697 continue; 4698 4699 if (!check_single_encoder_cloning(state, crtc, encoder)) { 4700 drm_dbg_kms(&i915->drm, 4701 "[ENCODER:%d:%s] rejecting invalid cloning configuration\n", 4702 encoder->base.base.id, encoder->base.name); 4703 return -EINVAL; 4704 } 4705 4706 /* 4707 * Determine output_types before calling the .compute_config() 4708 * hooks so that the hooks can use this information safely. 4709 */ 4710 if (encoder->compute_output_type) 4711 crtc_state->output_types |= 4712 BIT(encoder->compute_output_type(encoder, crtc_state, 4713 connector_state)); 4714 else 4715 crtc_state->output_types |= BIT(encoder->type); 4716 } 4717 4718 encoder_retry: 4719 /* Ensure the port clock defaults are reset when retrying. */ 4720 crtc_state->port_clock = 0; 4721 crtc_state->pixel_multiplier = 1; 4722 4723 /* Fill in default crtc timings, allow encoders to overwrite them. */ 4724 drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode, 4725 CRTC_STEREO_DOUBLE); 4726 4727 /* Pass our mode to the connectors and the CRTC to give them a chance to 4728 * adjust it according to limitations or connector properties, and also 4729 * a chance to reject the mode entirely. 4730 */ 4731 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4732 struct intel_encoder *encoder = 4733 to_intel_encoder(connector_state->best_encoder); 4734 4735 if (connector_state->crtc != &crtc->base) 4736 continue; 4737 4738 ret = encoder->compute_config(encoder, crtc_state, 4739 connector_state); 4740 if (ret == -EDEADLK) 4741 return ret; 4742 if (ret < 0) { 4743 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n", 4744 encoder->base.base.id, encoder->base.name, ret); 4745 return ret; 4746 } 4747 } 4748 4749 /* Set default port clock if not overwritten by the encoder. Needs to be 4750 * done afterwards in case the encoder adjusts the mode. */ 4751 if (!crtc_state->port_clock) 4752 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock 4753 * crtc_state->pixel_multiplier; 4754 4755 ret = intel_crtc_compute_config(state, crtc); 4756 if (ret == -EDEADLK) 4757 return ret; 4758 if (ret == -EAGAIN) { 4759 if (drm_WARN(&i915->drm, !retry, 4760 "[CRTC:%d:%s] loop in pipe configuration computation\n", 4761 crtc->base.base.id, crtc->base.name)) 4762 return -EINVAL; 4763 4764 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] bw constrained, retrying\n", 4765 crtc->base.base.id, crtc->base.name); 4766 retry = false; 4767 goto encoder_retry; 4768 } 4769 if (ret < 0) { 4770 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n", 4771 crtc->base.base.id, crtc->base.name, ret); 4772 return ret; 4773 } 4774 4775 /* Dithering seems to not pass-through bits correctly when it should, so 4776 * only enable it on 6bpc panels and when its not a compliance 4777 * test requesting 6bpc video pattern. 4778 */ 4779 crtc_state->dither = (crtc_state->pipe_bpp == 6*3) && 4780 !crtc_state->dither_force_disable; 4781 drm_dbg_kms(&i915->drm, 4782 "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n", 4783 crtc->base.base.id, crtc->base.name, 4784 base_bpp, crtc_state->pipe_bpp, crtc_state->dither); 4785 4786 return 0; 4787 } 4788 4789 static int 4790 intel_modeset_pipe_config_late(struct intel_atomic_state *state, 4791 struct intel_crtc *crtc) 4792 { 4793 struct intel_crtc_state *crtc_state = 4794 intel_atomic_get_new_crtc_state(state, crtc); 4795 struct drm_connector_state *conn_state; 4796 struct drm_connector *connector; 4797 int i; 4798 4799 intel_bigjoiner_adjust_pipe_src(crtc_state); 4800 4801 for_each_new_connector_in_state(&state->base, connector, 4802 conn_state, i) { 4803 struct intel_encoder *encoder = 4804 to_intel_encoder(conn_state->best_encoder); 4805 int ret; 4806 4807 if (conn_state->crtc != &crtc->base || 4808 !encoder->compute_config_late) 4809 continue; 4810 4811 ret = encoder->compute_config_late(encoder, crtc_state, 4812 conn_state); 4813 if (ret) 4814 return ret; 4815 } 4816 4817 return 0; 4818 } 4819 4820 bool intel_fuzzy_clock_check(int clock1, int clock2) 4821 { 4822 int diff; 4823 4824 if (clock1 == clock2) 4825 return true; 4826 4827 if (!clock1 || !clock2) 4828 return false; 4829 4830 diff = abs(clock1 - clock2); 4831 4832 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) 4833 return true; 4834 4835 return false; 4836 } 4837 4838 static bool 4839 intel_compare_link_m_n(const struct intel_link_m_n *m_n, 4840 const struct intel_link_m_n *m2_n2) 4841 { 4842 return m_n->tu == m2_n2->tu && 4843 m_n->data_m == m2_n2->data_m && 4844 m_n->data_n == m2_n2->data_n && 4845 m_n->link_m == m2_n2->link_m && 4846 m_n->link_n == m2_n2->link_n; 4847 } 4848 4849 static bool 4850 intel_compare_infoframe(const union hdmi_infoframe *a, 4851 const union hdmi_infoframe *b) 4852 { 4853 return memcmp(a, b, sizeof(*a)) == 0; 4854 } 4855 4856 static bool 4857 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a, 4858 const struct drm_dp_vsc_sdp *b) 4859 { 4860 return memcmp(a, b, sizeof(*a)) == 0; 4861 } 4862 4863 static bool 4864 intel_compare_buffer(const u8 *a, const u8 *b, size_t len) 4865 { 4866 return memcmp(a, b, len) == 0; 4867 } 4868 4869 static void 4870 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv, 4871 bool fastset, const char *name, 4872 const union hdmi_infoframe *a, 4873 const union hdmi_infoframe *b) 4874 { 4875 if (fastset) { 4876 if (!drm_debug_enabled(DRM_UT_KMS)) 4877 return; 4878 4879 drm_dbg_kms(&dev_priv->drm, 4880 "fastset requirement not met in %s infoframe\n", name); 4881 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 4882 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a); 4883 drm_dbg_kms(&dev_priv->drm, "found:\n"); 4884 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b); 4885 } else { 4886 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name); 4887 drm_err(&dev_priv->drm, "expected:\n"); 4888 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a); 4889 drm_err(&dev_priv->drm, "found:\n"); 4890 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b); 4891 } 4892 } 4893 4894 static void 4895 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv, 4896 bool fastset, const char *name, 4897 const struct drm_dp_vsc_sdp *a, 4898 const struct drm_dp_vsc_sdp *b) 4899 { 4900 if (fastset) { 4901 if (!drm_debug_enabled(DRM_UT_KMS)) 4902 return; 4903 4904 drm_dbg_kms(&dev_priv->drm, 4905 "fastset requirement not met in %s dp sdp\n", name); 4906 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 4907 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a); 4908 drm_dbg_kms(&dev_priv->drm, "found:\n"); 4909 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b); 4910 } else { 4911 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name); 4912 drm_err(&dev_priv->drm, "expected:\n"); 4913 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a); 4914 drm_err(&dev_priv->drm, "found:\n"); 4915 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b); 4916 } 4917 } 4918 4919 /* Returns the length up to and including the last differing byte */ 4920 static size_t 4921 memcmp_diff_len(const u8 *a, const u8 *b, size_t len) 4922 { 4923 int i; 4924 4925 for (i = len - 1; i >= 0; i--) { 4926 if (a[i] != b[i]) 4927 return i + 1; 4928 } 4929 4930 return 0; 4931 } 4932 4933 static void 4934 pipe_config_buffer_mismatch(struct drm_i915_private *dev_priv, 4935 bool fastset, const char *name, 4936 const u8 *a, const u8 *b, size_t len) 4937 { 4938 if (fastset) { 4939 if (!drm_debug_enabled(DRM_UT_KMS)) 4940 return; 4941 4942 /* only dump up to the last difference */ 4943 len = memcmp_diff_len(a, b, len); 4944 4945 drm_dbg_kms(&dev_priv->drm, 4946 "fastset requirement not met in %s buffer\n", name); 4947 print_hex_dump(KERN_DEBUG, "expected: ", DUMP_PREFIX_NONE, 4948 16, 0, a, len, false); 4949 print_hex_dump(KERN_DEBUG, "found: ", DUMP_PREFIX_NONE, 4950 16, 0, b, len, false); 4951 } else { 4952 /* only dump up to the last difference */ 4953 len = memcmp_diff_len(a, b, len); 4954 4955 drm_err(&dev_priv->drm, "mismatch in %s buffer\n", name); 4956 print_hex_dump(KERN_ERR, "expected: ", DUMP_PREFIX_NONE, 4957 16, 0, a, len, false); 4958 print_hex_dump(KERN_ERR, "found: ", DUMP_PREFIX_NONE, 4959 16, 0, b, len, false); 4960 } 4961 } 4962 4963 static void __printf(4, 5) 4964 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc, 4965 const char *name, const char *format, ...) 4966 { 4967 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4968 struct va_format vaf; 4969 va_list args; 4970 4971 va_start(args, format); 4972 vaf.fmt = format; 4973 vaf.va = &args; 4974 4975 if (fastset) 4976 drm_dbg_kms(&i915->drm, 4977 "[CRTC:%d:%s] fastset requirement not met in %s %pV\n", 4978 crtc->base.base.id, crtc->base.name, name, &vaf); 4979 else 4980 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n", 4981 crtc->base.base.id, crtc->base.name, name, &vaf); 4982 4983 va_end(args); 4984 } 4985 4986 static bool fastboot_enabled(struct drm_i915_private *dev_priv) 4987 { 4988 if (dev_priv->params.fastboot != -1) 4989 return dev_priv->params.fastboot; 4990 4991 /* Enable fastboot by default on Skylake and newer */ 4992 if (DISPLAY_VER(dev_priv) >= 9) 4993 return true; 4994 4995 /* Enable fastboot by default on VLV and CHV */ 4996 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 4997 return true; 4998 4999 /* Disabled by default on all others */ 5000 return false; 5001 } 5002 5003 bool 5004 intel_pipe_config_compare(const struct intel_crtc_state *current_config, 5005 const struct intel_crtc_state *pipe_config, 5006 bool fastset) 5007 { 5008 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev); 5009 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 5010 bool ret = true; 5011 bool fixup_inherited = fastset && 5012 current_config->inherited && !pipe_config->inherited; 5013 5014 if (fixup_inherited && !fastboot_enabled(dev_priv)) { 5015 drm_dbg_kms(&dev_priv->drm, 5016 "initial modeset and fastboot not set\n"); 5017 ret = false; 5018 } 5019 5020 #define PIPE_CONF_CHECK_X(name) do { \ 5021 if (current_config->name != pipe_config->name) { \ 5022 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5023 "(expected 0x%08x, found 0x%08x)", \ 5024 current_config->name, \ 5025 pipe_config->name); \ 5026 ret = false; \ 5027 } \ 5028 } while (0) 5029 5030 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \ 5031 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \ 5032 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5033 "(expected 0x%08x, found 0x%08x)", \ 5034 current_config->name & (mask), \ 5035 pipe_config->name & (mask)); \ 5036 ret = false; \ 5037 } \ 5038 } while (0) 5039 5040 #define PIPE_CONF_CHECK_I(name) do { \ 5041 if (current_config->name != pipe_config->name) { \ 5042 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5043 "(expected %i, found %i)", \ 5044 current_config->name, \ 5045 pipe_config->name); \ 5046 ret = false; \ 5047 } \ 5048 } while (0) 5049 5050 #define PIPE_CONF_CHECK_BOOL(name) do { \ 5051 if (current_config->name != pipe_config->name) { \ 5052 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5053 "(expected %s, found %s)", \ 5054 str_yes_no(current_config->name), \ 5055 str_yes_no(pipe_config->name)); \ 5056 ret = false; \ 5057 } \ 5058 } while (0) 5059 5060 /* 5061 * Checks state where we only read out the enabling, but not the entire 5062 * state itself (like full infoframes or ELD for audio). These states 5063 * require a full modeset on bootup to fix up. 5064 */ 5065 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \ 5066 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \ 5067 PIPE_CONF_CHECK_BOOL(name); \ 5068 } else { \ 5069 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5070 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \ 5071 str_yes_no(current_config->name), \ 5072 str_yes_no(pipe_config->name)); \ 5073 ret = false; \ 5074 } \ 5075 } while (0) 5076 5077 #define PIPE_CONF_CHECK_P(name) do { \ 5078 if (current_config->name != pipe_config->name) { \ 5079 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5080 "(expected %p, found %p)", \ 5081 current_config->name, \ 5082 pipe_config->name); \ 5083 ret = false; \ 5084 } \ 5085 } while (0) 5086 5087 #define PIPE_CONF_CHECK_M_N(name) do { \ 5088 if (!intel_compare_link_m_n(¤t_config->name, \ 5089 &pipe_config->name)) { \ 5090 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5091 "(expected tu %i data %i/%i link %i/%i, " \ 5092 "found tu %i, data %i/%i link %i/%i)", \ 5093 current_config->name.tu, \ 5094 current_config->name.data_m, \ 5095 current_config->name.data_n, \ 5096 current_config->name.link_m, \ 5097 current_config->name.link_n, \ 5098 pipe_config->name.tu, \ 5099 pipe_config->name.data_m, \ 5100 pipe_config->name.data_n, \ 5101 pipe_config->name.link_m, \ 5102 pipe_config->name.link_n); \ 5103 ret = false; \ 5104 } \ 5105 } while (0) 5106 5107 #define PIPE_CONF_CHECK_TIMINGS(name) do { \ 5108 PIPE_CONF_CHECK_I(name.crtc_hdisplay); \ 5109 PIPE_CONF_CHECK_I(name.crtc_htotal); \ 5110 PIPE_CONF_CHECK_I(name.crtc_hblank_start); \ 5111 PIPE_CONF_CHECK_I(name.crtc_hblank_end); \ 5112 PIPE_CONF_CHECK_I(name.crtc_hsync_start); \ 5113 PIPE_CONF_CHECK_I(name.crtc_hsync_end); \ 5114 PIPE_CONF_CHECK_I(name.crtc_vdisplay); \ 5115 PIPE_CONF_CHECK_I(name.crtc_vtotal); \ 5116 PIPE_CONF_CHECK_I(name.crtc_vblank_start); \ 5117 PIPE_CONF_CHECK_I(name.crtc_vblank_end); \ 5118 PIPE_CONF_CHECK_I(name.crtc_vsync_start); \ 5119 PIPE_CONF_CHECK_I(name.crtc_vsync_end); \ 5120 } while (0) 5121 5122 #define PIPE_CONF_CHECK_RECT(name) do { \ 5123 PIPE_CONF_CHECK_I(name.x1); \ 5124 PIPE_CONF_CHECK_I(name.x2); \ 5125 PIPE_CONF_CHECK_I(name.y1); \ 5126 PIPE_CONF_CHECK_I(name.y2); \ 5127 } while (0) 5128 5129 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \ 5130 if ((current_config->name ^ pipe_config->name) & (mask)) { \ 5131 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5132 "(%x) (expected %i, found %i)", \ 5133 (mask), \ 5134 current_config->name & (mask), \ 5135 pipe_config->name & (mask)); \ 5136 ret = false; \ 5137 } \ 5138 } while (0) 5139 5140 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \ 5141 if (!intel_compare_infoframe(¤t_config->infoframes.name, \ 5142 &pipe_config->infoframes.name)) { \ 5143 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \ 5144 ¤t_config->infoframes.name, \ 5145 &pipe_config->infoframes.name); \ 5146 ret = false; \ 5147 } \ 5148 } while (0) 5149 5150 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \ 5151 if (!current_config->has_psr && !pipe_config->has_psr && \ 5152 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \ 5153 &pipe_config->infoframes.name)) { \ 5154 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \ 5155 ¤t_config->infoframes.name, \ 5156 &pipe_config->infoframes.name); \ 5157 ret = false; \ 5158 } \ 5159 } while (0) 5160 5161 #define PIPE_CONF_CHECK_BUFFER(name, len) do { \ 5162 BUILD_BUG_ON(sizeof(current_config->name) != (len)); \ 5163 BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \ 5164 if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \ 5165 pipe_config_buffer_mismatch(dev_priv, fastset, __stringify(name), \ 5166 current_config->name, \ 5167 pipe_config->name, \ 5168 (len)); \ 5169 ret = false; \ 5170 } \ 5171 } while (0) 5172 5173 #define PIPE_CONF_CHECK_COLOR_LUT(lut, is_pre_csc_lut) do { \ 5174 if (current_config->gamma_mode == pipe_config->gamma_mode && \ 5175 !intel_color_lut_equal(current_config, \ 5176 current_config->lut, pipe_config->lut, \ 5177 is_pre_csc_lut)) { \ 5178 pipe_config_mismatch(fastset, crtc, __stringify(lut), \ 5179 "hw_state doesn't match sw_state"); \ 5180 ret = false; \ 5181 } \ 5182 } while (0) 5183 5184 #define PIPE_CONF_CHECK_CSC(name) do { \ 5185 PIPE_CONF_CHECK_X(name.preoff[0]); \ 5186 PIPE_CONF_CHECK_X(name.preoff[1]); \ 5187 PIPE_CONF_CHECK_X(name.preoff[2]); \ 5188 PIPE_CONF_CHECK_X(name.coeff[0]); \ 5189 PIPE_CONF_CHECK_X(name.coeff[1]); \ 5190 PIPE_CONF_CHECK_X(name.coeff[2]); \ 5191 PIPE_CONF_CHECK_X(name.coeff[3]); \ 5192 PIPE_CONF_CHECK_X(name.coeff[4]); \ 5193 PIPE_CONF_CHECK_X(name.coeff[5]); \ 5194 PIPE_CONF_CHECK_X(name.coeff[6]); \ 5195 PIPE_CONF_CHECK_X(name.coeff[7]); \ 5196 PIPE_CONF_CHECK_X(name.coeff[8]); \ 5197 PIPE_CONF_CHECK_X(name.postoff[0]); \ 5198 PIPE_CONF_CHECK_X(name.postoff[1]); \ 5199 PIPE_CONF_CHECK_X(name.postoff[2]); \ 5200 } while (0) 5201 5202 #define PIPE_CONF_QUIRK(quirk) \ 5203 ((current_config->quirks | pipe_config->quirks) & (quirk)) 5204 5205 PIPE_CONF_CHECK_I(hw.enable); 5206 PIPE_CONF_CHECK_I(hw.active); 5207 5208 PIPE_CONF_CHECK_I(cpu_transcoder); 5209 PIPE_CONF_CHECK_I(mst_master_transcoder); 5210 5211 PIPE_CONF_CHECK_BOOL(has_pch_encoder); 5212 PIPE_CONF_CHECK_I(fdi_lanes); 5213 PIPE_CONF_CHECK_M_N(fdi_m_n); 5214 5215 PIPE_CONF_CHECK_I(lane_count); 5216 PIPE_CONF_CHECK_X(lane_lat_optim_mask); 5217 5218 if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) { 5219 if (!fastset || !pipe_config->seamless_m_n) 5220 PIPE_CONF_CHECK_M_N(dp_m_n); 5221 } else { 5222 PIPE_CONF_CHECK_M_N(dp_m_n); 5223 PIPE_CONF_CHECK_M_N(dp_m2_n2); 5224 } 5225 5226 PIPE_CONF_CHECK_X(output_types); 5227 5228 PIPE_CONF_CHECK_I(framestart_delay); 5229 PIPE_CONF_CHECK_I(msa_timing_delay); 5230 5231 PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode); 5232 PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode); 5233 5234 PIPE_CONF_CHECK_I(pixel_multiplier); 5235 5236 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5237 DRM_MODE_FLAG_INTERLACE); 5238 5239 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { 5240 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5241 DRM_MODE_FLAG_PHSYNC); 5242 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5243 DRM_MODE_FLAG_NHSYNC); 5244 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5245 DRM_MODE_FLAG_PVSYNC); 5246 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5247 DRM_MODE_FLAG_NVSYNC); 5248 } 5249 5250 PIPE_CONF_CHECK_I(output_format); 5251 PIPE_CONF_CHECK_BOOL(has_hdmi_sink); 5252 if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || 5253 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5254 PIPE_CONF_CHECK_BOOL(limited_color_range); 5255 5256 PIPE_CONF_CHECK_BOOL(hdmi_scrambling); 5257 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio); 5258 PIPE_CONF_CHECK_BOOL(has_infoframe); 5259 PIPE_CONF_CHECK_BOOL(fec_enable); 5260 5261 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio); 5262 PIPE_CONF_CHECK_BUFFER(eld, MAX_ELD_BYTES); 5263 5264 PIPE_CONF_CHECK_X(gmch_pfit.control); 5265 /* pfit ratios are autocomputed by the hw on gen4+ */ 5266 if (DISPLAY_VER(dev_priv) < 4) 5267 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); 5268 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); 5269 5270 /* 5271 * Changing the EDP transcoder input mux 5272 * (A_ONOFF vs. A_ON) requires a full modeset. 5273 */ 5274 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru); 5275 5276 if (!fastset) { 5277 PIPE_CONF_CHECK_RECT(pipe_src); 5278 5279 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled); 5280 PIPE_CONF_CHECK_RECT(pch_pfit.dst); 5281 5282 PIPE_CONF_CHECK_I(scaler_state.scaler_id); 5283 PIPE_CONF_CHECK_I(pixel_rate); 5284 5285 PIPE_CONF_CHECK_X(gamma_mode); 5286 if (IS_CHERRYVIEW(dev_priv)) 5287 PIPE_CONF_CHECK_X(cgm_mode); 5288 else 5289 PIPE_CONF_CHECK_X(csc_mode); 5290 PIPE_CONF_CHECK_BOOL(gamma_enable); 5291 PIPE_CONF_CHECK_BOOL(csc_enable); 5292 PIPE_CONF_CHECK_BOOL(wgc_enable); 5293 5294 PIPE_CONF_CHECK_I(linetime); 5295 PIPE_CONF_CHECK_I(ips_linetime); 5296 5297 PIPE_CONF_CHECK_COLOR_LUT(pre_csc_lut, true); 5298 PIPE_CONF_CHECK_COLOR_LUT(post_csc_lut, false); 5299 5300 PIPE_CONF_CHECK_CSC(csc); 5301 PIPE_CONF_CHECK_CSC(output_csc); 5302 5303 if (current_config->active_planes) { 5304 PIPE_CONF_CHECK_BOOL(has_psr); 5305 PIPE_CONF_CHECK_BOOL(has_psr2); 5306 PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); 5307 PIPE_CONF_CHECK_I(dc3co_exitline); 5308 } 5309 } 5310 5311 PIPE_CONF_CHECK_BOOL(double_wide); 5312 5313 if (dev_priv->display.dpll.mgr) { 5314 PIPE_CONF_CHECK_P(shared_dpll); 5315 5316 PIPE_CONF_CHECK_X(dpll_hw_state.dpll); 5317 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); 5318 PIPE_CONF_CHECK_X(dpll_hw_state.fp0); 5319 PIPE_CONF_CHECK_X(dpll_hw_state.fp1); 5320 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); 5321 PIPE_CONF_CHECK_X(dpll_hw_state.spll); 5322 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); 5323 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); 5324 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); 5325 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); 5326 PIPE_CONF_CHECK_X(dpll_hw_state.div0); 5327 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); 5328 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); 5329 PIPE_CONF_CHECK_X(dpll_hw_state.pll0); 5330 PIPE_CONF_CHECK_X(dpll_hw_state.pll1); 5331 PIPE_CONF_CHECK_X(dpll_hw_state.pll2); 5332 PIPE_CONF_CHECK_X(dpll_hw_state.pll3); 5333 PIPE_CONF_CHECK_X(dpll_hw_state.pll6); 5334 PIPE_CONF_CHECK_X(dpll_hw_state.pll8); 5335 PIPE_CONF_CHECK_X(dpll_hw_state.pll9); 5336 PIPE_CONF_CHECK_X(dpll_hw_state.pll10); 5337 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); 5338 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl); 5339 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1); 5340 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl); 5341 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0); 5342 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1); 5343 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf); 5344 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock); 5345 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc); 5346 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias); 5347 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias); 5348 } 5349 5350 PIPE_CONF_CHECK_X(dsi_pll.ctrl); 5351 PIPE_CONF_CHECK_X(dsi_pll.div); 5352 5353 if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5) 5354 PIPE_CONF_CHECK_I(pipe_bpp); 5355 5356 if (!fastset || !pipe_config->seamless_m_n) { 5357 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock); 5358 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock); 5359 } 5360 PIPE_CONF_CHECK_I(port_clock); 5361 5362 PIPE_CONF_CHECK_I(min_voltage_level); 5363 5364 if (current_config->has_psr || pipe_config->has_psr) 5365 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable, 5366 ~intel_hdmi_infoframe_enable(DP_SDP_VSC)); 5367 else 5368 PIPE_CONF_CHECK_X(infoframes.enable); 5369 5370 PIPE_CONF_CHECK_X(infoframes.gcp); 5371 PIPE_CONF_CHECK_INFOFRAME(avi); 5372 PIPE_CONF_CHECK_INFOFRAME(spd); 5373 PIPE_CONF_CHECK_INFOFRAME(hdmi); 5374 PIPE_CONF_CHECK_INFOFRAME(drm); 5375 PIPE_CONF_CHECK_DP_VSC_SDP(vsc); 5376 5377 PIPE_CONF_CHECK_X(sync_mode_slaves_mask); 5378 PIPE_CONF_CHECK_I(master_transcoder); 5379 PIPE_CONF_CHECK_X(bigjoiner_pipes); 5380 5381 PIPE_CONF_CHECK_I(dsc.compression_enable); 5382 PIPE_CONF_CHECK_I(dsc.dsc_split); 5383 PIPE_CONF_CHECK_I(dsc.compressed_bpp); 5384 5385 PIPE_CONF_CHECK_BOOL(splitter.enable); 5386 PIPE_CONF_CHECK_I(splitter.link_count); 5387 PIPE_CONF_CHECK_I(splitter.pixel_overlap); 5388 5389 if (!fastset) 5390 PIPE_CONF_CHECK_BOOL(vrr.enable); 5391 PIPE_CONF_CHECK_I(vrr.vmin); 5392 PIPE_CONF_CHECK_I(vrr.vmax); 5393 PIPE_CONF_CHECK_I(vrr.flipline); 5394 PIPE_CONF_CHECK_I(vrr.pipeline_full); 5395 PIPE_CONF_CHECK_I(vrr.guardband); 5396 5397 #undef PIPE_CONF_CHECK_X 5398 #undef PIPE_CONF_CHECK_I 5399 #undef PIPE_CONF_CHECK_BOOL 5400 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE 5401 #undef PIPE_CONF_CHECK_P 5402 #undef PIPE_CONF_CHECK_FLAGS 5403 #undef PIPE_CONF_CHECK_COLOR_LUT 5404 #undef PIPE_CONF_CHECK_TIMINGS 5405 #undef PIPE_CONF_CHECK_RECT 5406 #undef PIPE_CONF_QUIRK 5407 5408 return ret; 5409 } 5410 5411 static void 5412 intel_verify_planes(struct intel_atomic_state *state) 5413 { 5414 struct intel_plane *plane; 5415 const struct intel_plane_state *plane_state; 5416 int i; 5417 5418 for_each_new_intel_plane_in_state(state, plane, 5419 plane_state, i) 5420 assert_plane(plane, plane_state->planar_slave || 5421 plane_state->uapi.visible); 5422 } 5423 5424 int intel_modeset_all_pipes(struct intel_atomic_state *state, 5425 const char *reason) 5426 { 5427 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 5428 struct intel_crtc *crtc; 5429 5430 /* 5431 * Add all pipes to the state, and force 5432 * a modeset on all the active ones. 5433 */ 5434 for_each_intel_crtc(&dev_priv->drm, crtc) { 5435 struct intel_crtc_state *crtc_state; 5436 int ret; 5437 5438 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 5439 if (IS_ERR(crtc_state)) 5440 return PTR_ERR(crtc_state); 5441 5442 if (!crtc_state->hw.active || 5443 intel_crtc_needs_modeset(crtc_state)) 5444 continue; 5445 5446 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] Full modeset due to %s\n", 5447 crtc->base.base.id, crtc->base.name, reason); 5448 5449 crtc_state->uapi.mode_changed = true; 5450 crtc_state->update_pipe = false; 5451 5452 ret = drm_atomic_add_affected_connectors(&state->base, 5453 &crtc->base); 5454 if (ret) 5455 return ret; 5456 5457 ret = intel_dp_mst_add_topology_state_for_crtc(state, crtc); 5458 if (ret) 5459 return ret; 5460 5461 ret = intel_atomic_add_affected_planes(state, crtc); 5462 if (ret) 5463 return ret; 5464 5465 crtc_state->update_planes |= crtc_state->active_planes; 5466 crtc_state->async_flip_planes = 0; 5467 crtc_state->do_async_flip = false; 5468 } 5469 5470 return 0; 5471 } 5472 5473 /* 5474 * This implements the workaround described in the "notes" section of the mode 5475 * set sequence documentation. When going from no pipes or single pipe to 5476 * multiple pipes, and planes are enabled after the pipe, we need to wait at 5477 * least 2 vblanks on the first pipe before enabling planes on the second pipe. 5478 */ 5479 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state) 5480 { 5481 struct intel_crtc_state *crtc_state; 5482 struct intel_crtc *crtc; 5483 struct intel_crtc_state *first_crtc_state = NULL; 5484 struct intel_crtc_state *other_crtc_state = NULL; 5485 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; 5486 int i; 5487 5488 /* look at all crtc's that are going to be enabled in during modeset */ 5489 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5490 if (!crtc_state->hw.active || 5491 !intel_crtc_needs_modeset(crtc_state)) 5492 continue; 5493 5494 if (first_crtc_state) { 5495 other_crtc_state = crtc_state; 5496 break; 5497 } else { 5498 first_crtc_state = crtc_state; 5499 first_pipe = crtc->pipe; 5500 } 5501 } 5502 5503 /* No workaround needed? */ 5504 if (!first_crtc_state) 5505 return 0; 5506 5507 /* w/a possibly needed, check how many crtc's are already enabled. */ 5508 for_each_intel_crtc(state->base.dev, crtc) { 5509 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 5510 if (IS_ERR(crtc_state)) 5511 return PTR_ERR(crtc_state); 5512 5513 crtc_state->hsw_workaround_pipe = INVALID_PIPE; 5514 5515 if (!crtc_state->hw.active || 5516 intel_crtc_needs_modeset(crtc_state)) 5517 continue; 5518 5519 /* 2 or more enabled crtcs means no need for w/a */ 5520 if (enabled_pipe != INVALID_PIPE) 5521 return 0; 5522 5523 enabled_pipe = crtc->pipe; 5524 } 5525 5526 if (enabled_pipe != INVALID_PIPE) 5527 first_crtc_state->hsw_workaround_pipe = enabled_pipe; 5528 else if (other_crtc_state) 5529 other_crtc_state->hsw_workaround_pipe = first_pipe; 5530 5531 return 0; 5532 } 5533 5534 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 5535 u8 active_pipes) 5536 { 5537 const struct intel_crtc_state *crtc_state; 5538 struct intel_crtc *crtc; 5539 int i; 5540 5541 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5542 if (crtc_state->hw.active) 5543 active_pipes |= BIT(crtc->pipe); 5544 else 5545 active_pipes &= ~BIT(crtc->pipe); 5546 } 5547 5548 return active_pipes; 5549 } 5550 5551 static int intel_modeset_checks(struct intel_atomic_state *state) 5552 { 5553 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 5554 5555 state->modeset = true; 5556 5557 if (IS_HASWELL(dev_priv)) 5558 return hsw_mode_set_planes_workaround(state); 5559 5560 return 0; 5561 } 5562 5563 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state, 5564 struct intel_crtc_state *new_crtc_state) 5565 { 5566 struct drm_i915_private *i915 = to_i915(old_crtc_state->uapi.crtc->dev); 5567 5568 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) { 5569 drm_dbg_kms(&i915->drm, "fastset requirement not met, forcing full modeset\n"); 5570 5571 return; 5572 } 5573 5574 new_crtc_state->uapi.mode_changed = false; 5575 if (!intel_crtc_needs_modeset(new_crtc_state)) 5576 new_crtc_state->update_pipe = true; 5577 } 5578 5579 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state, 5580 struct intel_crtc *crtc, 5581 u8 plane_ids_mask) 5582 { 5583 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 5584 struct intel_plane *plane; 5585 5586 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 5587 struct intel_plane_state *plane_state; 5588 5589 if ((plane_ids_mask & BIT(plane->id)) == 0) 5590 continue; 5591 5592 plane_state = intel_atomic_get_plane_state(state, plane); 5593 if (IS_ERR(plane_state)) 5594 return PTR_ERR(plane_state); 5595 } 5596 5597 return 0; 5598 } 5599 5600 int intel_atomic_add_affected_planes(struct intel_atomic_state *state, 5601 struct intel_crtc *crtc) 5602 { 5603 const struct intel_crtc_state *old_crtc_state = 5604 intel_atomic_get_old_crtc_state(state, crtc); 5605 const struct intel_crtc_state *new_crtc_state = 5606 intel_atomic_get_new_crtc_state(state, crtc); 5607 5608 return intel_crtc_add_planes_to_state(state, crtc, 5609 old_crtc_state->enabled_planes | 5610 new_crtc_state->enabled_planes); 5611 } 5612 5613 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv) 5614 { 5615 /* See {hsw,vlv,ivb}_plane_ratio() */ 5616 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) || 5617 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) || 5618 IS_IVYBRIDGE(dev_priv); 5619 } 5620 5621 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state, 5622 struct intel_crtc *crtc, 5623 struct intel_crtc *other) 5624 { 5625 const struct intel_plane_state __maybe_unused *plane_state; 5626 struct intel_plane *plane; 5627 u8 plane_ids = 0; 5628 int i; 5629 5630 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 5631 if (plane->pipe == crtc->pipe) 5632 plane_ids |= BIT(plane->id); 5633 } 5634 5635 return intel_crtc_add_planes_to_state(state, other, plane_ids); 5636 } 5637 5638 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state) 5639 { 5640 struct drm_i915_private *i915 = to_i915(state->base.dev); 5641 const struct intel_crtc_state *crtc_state; 5642 struct intel_crtc *crtc; 5643 int i; 5644 5645 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5646 struct intel_crtc *other; 5647 5648 for_each_intel_crtc_in_pipe_mask(&i915->drm, other, 5649 crtc_state->bigjoiner_pipes) { 5650 int ret; 5651 5652 if (crtc == other) 5653 continue; 5654 5655 ret = intel_crtc_add_bigjoiner_planes(state, crtc, other); 5656 if (ret) 5657 return ret; 5658 } 5659 } 5660 5661 return 0; 5662 } 5663 5664 static int intel_atomic_check_planes(struct intel_atomic_state *state) 5665 { 5666 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 5667 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 5668 struct intel_plane_state __maybe_unused *plane_state; 5669 struct intel_plane *plane; 5670 struct intel_crtc *crtc; 5671 int i, ret; 5672 5673 ret = icl_add_linked_planes(state); 5674 if (ret) 5675 return ret; 5676 5677 ret = intel_bigjoiner_add_affected_planes(state); 5678 if (ret) 5679 return ret; 5680 5681 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 5682 ret = intel_plane_atomic_check(state, plane); 5683 if (ret) { 5684 drm_dbg_atomic(&dev_priv->drm, 5685 "[PLANE:%d:%s] atomic driver check failed\n", 5686 plane->base.base.id, plane->base.name); 5687 return ret; 5688 } 5689 } 5690 5691 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 5692 new_crtc_state, i) { 5693 u8 old_active_planes, new_active_planes; 5694 5695 ret = icl_check_nv12_planes(new_crtc_state); 5696 if (ret) 5697 return ret; 5698 5699 /* 5700 * On some platforms the number of active planes affects 5701 * the planes' minimum cdclk calculation. Add such planes 5702 * to the state before we compute the minimum cdclk. 5703 */ 5704 if (!active_planes_affects_min_cdclk(dev_priv)) 5705 continue; 5706 5707 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 5708 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 5709 5710 if (hweight8(old_active_planes) == hweight8(new_active_planes)) 5711 continue; 5712 5713 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes); 5714 if (ret) 5715 return ret; 5716 } 5717 5718 return 0; 5719 } 5720 5721 static int intel_atomic_check_crtcs(struct intel_atomic_state *state) 5722 { 5723 struct intel_crtc_state __maybe_unused *crtc_state; 5724 struct intel_crtc *crtc; 5725 int i; 5726 5727 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5728 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 5729 int ret; 5730 5731 ret = intel_crtc_atomic_check(state, crtc); 5732 if (ret) { 5733 drm_dbg_atomic(&i915->drm, 5734 "[CRTC:%d:%s] atomic driver check failed\n", 5735 crtc->base.base.id, crtc->base.name); 5736 return ret; 5737 } 5738 } 5739 5740 return 0; 5741 } 5742 5743 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, 5744 u8 transcoders) 5745 { 5746 const struct intel_crtc_state *new_crtc_state; 5747 struct intel_crtc *crtc; 5748 int i; 5749 5750 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 5751 if (new_crtc_state->hw.enable && 5752 transcoders & BIT(new_crtc_state->cpu_transcoder) && 5753 intel_crtc_needs_modeset(new_crtc_state)) 5754 return true; 5755 } 5756 5757 return false; 5758 } 5759 5760 static bool intel_pipes_need_modeset(struct intel_atomic_state *state, 5761 u8 pipes) 5762 { 5763 const struct intel_crtc_state *new_crtc_state; 5764 struct intel_crtc *crtc; 5765 int i; 5766 5767 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 5768 if (new_crtc_state->hw.enable && 5769 pipes & BIT(crtc->pipe) && 5770 intel_crtc_needs_modeset(new_crtc_state)) 5771 return true; 5772 } 5773 5774 return false; 5775 } 5776 5777 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state, 5778 struct intel_crtc *master_crtc) 5779 { 5780 struct drm_i915_private *i915 = to_i915(state->base.dev); 5781 struct intel_crtc_state *master_crtc_state = 5782 intel_atomic_get_new_crtc_state(state, master_crtc); 5783 struct intel_crtc *slave_crtc; 5784 5785 if (!master_crtc_state->bigjoiner_pipes) 5786 return 0; 5787 5788 /* sanity check */ 5789 if (drm_WARN_ON(&i915->drm, 5790 master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state))) 5791 return -EINVAL; 5792 5793 if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) { 5794 drm_dbg_kms(&i915->drm, 5795 "[CRTC:%d:%s] Cannot act as big joiner master " 5796 "(need 0x%x as pipes, only 0x%x possible)\n", 5797 master_crtc->base.base.id, master_crtc->base.name, 5798 master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915)); 5799 return -EINVAL; 5800 } 5801 5802 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 5803 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 5804 struct intel_crtc_state *slave_crtc_state; 5805 int ret; 5806 5807 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc); 5808 if (IS_ERR(slave_crtc_state)) 5809 return PTR_ERR(slave_crtc_state); 5810 5811 /* master being enabled, slave was already configured? */ 5812 if (slave_crtc_state->uapi.enable) { 5813 drm_dbg_kms(&i915->drm, 5814 "[CRTC:%d:%s] Slave is enabled as normal CRTC, but " 5815 "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n", 5816 slave_crtc->base.base.id, slave_crtc->base.name, 5817 master_crtc->base.base.id, master_crtc->base.name); 5818 return -EINVAL; 5819 } 5820 5821 /* 5822 * The state copy logic assumes the master crtc gets processed 5823 * before the slave crtc during the main compute_config loop. 5824 * This works because the crtcs are created in pipe order, 5825 * and the hardware requires master pipe < slave pipe as well. 5826 * Should that change we need to rethink the logic. 5827 */ 5828 if (WARN_ON(drm_crtc_index(&master_crtc->base) > 5829 drm_crtc_index(&slave_crtc->base))) 5830 return -EINVAL; 5831 5832 drm_dbg_kms(&i915->drm, 5833 "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n", 5834 slave_crtc->base.base.id, slave_crtc->base.name, 5835 master_crtc->base.base.id, master_crtc->base.name); 5836 5837 slave_crtc_state->bigjoiner_pipes = 5838 master_crtc_state->bigjoiner_pipes; 5839 5840 ret = copy_bigjoiner_crtc_state_modeset(state, slave_crtc); 5841 if (ret) 5842 return ret; 5843 } 5844 5845 return 0; 5846 } 5847 5848 static void kill_bigjoiner_slave(struct intel_atomic_state *state, 5849 struct intel_crtc *master_crtc) 5850 { 5851 struct drm_i915_private *i915 = to_i915(state->base.dev); 5852 struct intel_crtc_state *master_crtc_state = 5853 intel_atomic_get_new_crtc_state(state, master_crtc); 5854 struct intel_crtc *slave_crtc; 5855 5856 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 5857 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 5858 struct intel_crtc_state *slave_crtc_state = 5859 intel_atomic_get_new_crtc_state(state, slave_crtc); 5860 5861 slave_crtc_state->bigjoiner_pipes = 0; 5862 5863 intel_crtc_copy_uapi_to_hw_state_modeset(state, slave_crtc); 5864 } 5865 5866 master_crtc_state->bigjoiner_pipes = 0; 5867 } 5868 5869 /** 5870 * DOC: asynchronous flip implementation 5871 * 5872 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC 5873 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL. 5874 * Correspondingly, support is currently added for primary plane only. 5875 * 5876 * Async flip can only change the plane surface address, so anything else 5877 * changing is rejected from the intel_async_flip_check_hw() function. 5878 * Once this check is cleared, flip done interrupt is enabled using 5879 * the intel_crtc_enable_flip_done() function. 5880 * 5881 * As soon as the surface address register is written, flip done interrupt is 5882 * generated and the requested events are sent to the usersapce in the interrupt 5883 * handler itself. The timestamp and sequence sent during the flip done event 5884 * correspond to the last vblank and have no relation to the actual time when 5885 * the flip done event was sent. 5886 */ 5887 static int intel_async_flip_check_uapi(struct intel_atomic_state *state, 5888 struct intel_crtc *crtc) 5889 { 5890 struct drm_i915_private *i915 = to_i915(state->base.dev); 5891 const struct intel_crtc_state *new_crtc_state = 5892 intel_atomic_get_new_crtc_state(state, crtc); 5893 const struct intel_plane_state *old_plane_state; 5894 struct intel_plane_state *new_plane_state; 5895 struct intel_plane *plane; 5896 int i; 5897 5898 if (!new_crtc_state->uapi.async_flip) 5899 return 0; 5900 5901 if (!new_crtc_state->uapi.active) { 5902 drm_dbg_kms(&i915->drm, 5903 "[CRTC:%d:%s] not active\n", 5904 crtc->base.base.id, crtc->base.name); 5905 return -EINVAL; 5906 } 5907 5908 if (intel_crtc_needs_modeset(new_crtc_state)) { 5909 drm_dbg_kms(&i915->drm, 5910 "[CRTC:%d:%s] modeset required\n", 5911 crtc->base.base.id, crtc->base.name); 5912 return -EINVAL; 5913 } 5914 5915 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 5916 new_plane_state, i) { 5917 if (plane->pipe != crtc->pipe) 5918 continue; 5919 5920 /* 5921 * TODO: Async flip is only supported through the page flip IOCTL 5922 * as of now. So support currently added for primary plane only. 5923 * Support for other planes on platforms on which supports 5924 * this(vlv/chv and icl+) should be added when async flip is 5925 * enabled in the atomic IOCTL path. 5926 */ 5927 if (!plane->async_flip) { 5928 drm_dbg_kms(&i915->drm, 5929 "[PLANE:%d:%s] async flip not supported\n", 5930 plane->base.base.id, plane->base.name); 5931 return -EINVAL; 5932 } 5933 5934 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) { 5935 drm_dbg_kms(&i915->drm, 5936 "[PLANE:%d:%s] no old or new framebuffer\n", 5937 plane->base.base.id, plane->base.name); 5938 return -EINVAL; 5939 } 5940 } 5941 5942 return 0; 5943 } 5944 5945 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc) 5946 { 5947 struct drm_i915_private *i915 = to_i915(state->base.dev); 5948 const struct intel_crtc_state *old_crtc_state, *new_crtc_state; 5949 const struct intel_plane_state *new_plane_state, *old_plane_state; 5950 struct intel_plane *plane; 5951 int i; 5952 5953 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 5954 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 5955 5956 if (!new_crtc_state->uapi.async_flip) 5957 return 0; 5958 5959 if (!new_crtc_state->hw.active) { 5960 drm_dbg_kms(&i915->drm, 5961 "[CRTC:%d:%s] not active\n", 5962 crtc->base.base.id, crtc->base.name); 5963 return -EINVAL; 5964 } 5965 5966 if (intel_crtc_needs_modeset(new_crtc_state)) { 5967 drm_dbg_kms(&i915->drm, 5968 "[CRTC:%d:%s] modeset required\n", 5969 crtc->base.base.id, crtc->base.name); 5970 return -EINVAL; 5971 } 5972 5973 if (old_crtc_state->active_planes != new_crtc_state->active_planes) { 5974 drm_dbg_kms(&i915->drm, 5975 "[CRTC:%d:%s] Active planes cannot be in async flip\n", 5976 crtc->base.base.id, crtc->base.name); 5977 return -EINVAL; 5978 } 5979 5980 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 5981 new_plane_state, i) { 5982 if (plane->pipe != crtc->pipe) 5983 continue; 5984 5985 /* 5986 * Only async flip capable planes should be in the state 5987 * if we're really about to ask the hardware to perform 5988 * an async flip. We should never get this far otherwise. 5989 */ 5990 if (drm_WARN_ON(&i915->drm, 5991 new_crtc_state->do_async_flip && !plane->async_flip)) 5992 return -EINVAL; 5993 5994 /* 5995 * Only check async flip capable planes other planes 5996 * may be involved in the initial commit due to 5997 * the wm0/ddb optimization. 5998 * 5999 * TODO maybe should track which planes actually 6000 * were requested to do the async flip... 6001 */ 6002 if (!plane->async_flip) 6003 continue; 6004 6005 /* 6006 * FIXME: This check is kept generic for all platforms. 6007 * Need to verify this for all gen9 platforms to enable 6008 * this selectively if required. 6009 */ 6010 switch (new_plane_state->hw.fb->modifier) { 6011 case DRM_FORMAT_MOD_LINEAR: 6012 /* 6013 * FIXME: Async on Linear buffer is supported on ICL as 6014 * but with additional alignment and fbc restrictions 6015 * need to be taken care of. These aren't applicable for 6016 * gen12+. 6017 */ 6018 if (DISPLAY_VER(i915) < 12) { 6019 drm_dbg_kms(&i915->drm, 6020 "[PLANE:%d:%s] Modifier 0x%llx does not support async flip on display ver %d\n", 6021 plane->base.base.id, plane->base.name, 6022 new_plane_state->hw.fb->modifier, DISPLAY_VER(i915)); 6023 return -EINVAL; 6024 } 6025 break; 6026 6027 case I915_FORMAT_MOD_X_TILED: 6028 case I915_FORMAT_MOD_Y_TILED: 6029 case I915_FORMAT_MOD_Yf_TILED: 6030 case I915_FORMAT_MOD_4_TILED: 6031 break; 6032 default: 6033 drm_dbg_kms(&i915->drm, 6034 "[PLANE:%d:%s] Modifier 0x%llx does not support async flip\n", 6035 plane->base.base.id, plane->base.name, 6036 new_plane_state->hw.fb->modifier); 6037 return -EINVAL; 6038 } 6039 6040 if (new_plane_state->hw.fb->format->num_planes > 1) { 6041 drm_dbg_kms(&i915->drm, 6042 "[PLANE:%d:%s] Planar formats do not support async flips\n", 6043 plane->base.base.id, plane->base.name); 6044 return -EINVAL; 6045 } 6046 6047 if (old_plane_state->view.color_plane[0].mapping_stride != 6048 new_plane_state->view.color_plane[0].mapping_stride) { 6049 drm_dbg_kms(&i915->drm, 6050 "[PLANE:%d:%s] Stride cannot be changed in async flip\n", 6051 plane->base.base.id, plane->base.name); 6052 return -EINVAL; 6053 } 6054 6055 if (old_plane_state->hw.fb->modifier != 6056 new_plane_state->hw.fb->modifier) { 6057 drm_dbg_kms(&i915->drm, 6058 "[PLANE:%d:%s] Modifier cannot be changed in async flip\n", 6059 plane->base.base.id, plane->base.name); 6060 return -EINVAL; 6061 } 6062 6063 if (old_plane_state->hw.fb->format != 6064 new_plane_state->hw.fb->format) { 6065 drm_dbg_kms(&i915->drm, 6066 "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n", 6067 plane->base.base.id, plane->base.name); 6068 return -EINVAL; 6069 } 6070 6071 if (old_plane_state->hw.rotation != 6072 new_plane_state->hw.rotation) { 6073 drm_dbg_kms(&i915->drm, 6074 "[PLANE:%d:%s] Rotation cannot be changed in async flip\n", 6075 plane->base.base.id, plane->base.name); 6076 return -EINVAL; 6077 } 6078 6079 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) || 6080 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) { 6081 drm_dbg_kms(&i915->drm, 6082 "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n", 6083 plane->base.base.id, plane->base.name); 6084 return -EINVAL; 6085 } 6086 6087 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) { 6088 drm_dbg_kms(&i915->drm, 6089 "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n", 6090 plane->base.base.id, plane->base.name); 6091 return -EINVAL; 6092 } 6093 6094 if (old_plane_state->hw.pixel_blend_mode != 6095 new_plane_state->hw.pixel_blend_mode) { 6096 drm_dbg_kms(&i915->drm, 6097 "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n", 6098 plane->base.base.id, plane->base.name); 6099 return -EINVAL; 6100 } 6101 6102 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) { 6103 drm_dbg_kms(&i915->drm, 6104 "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n", 6105 plane->base.base.id, plane->base.name); 6106 return -EINVAL; 6107 } 6108 6109 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) { 6110 drm_dbg_kms(&i915->drm, 6111 "[PLANE:%d:%s] Color range cannot be changed in async flip\n", 6112 plane->base.base.id, plane->base.name); 6113 return -EINVAL; 6114 } 6115 6116 /* plane decryption is allow to change only in synchronous flips */ 6117 if (old_plane_state->decrypt != new_plane_state->decrypt) { 6118 drm_dbg_kms(&i915->drm, 6119 "[PLANE:%d:%s] Decryption cannot be changed in async flip\n", 6120 plane->base.base.id, plane->base.name); 6121 return -EINVAL; 6122 } 6123 } 6124 6125 return 0; 6126 } 6127 6128 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state) 6129 { 6130 struct drm_i915_private *i915 = to_i915(state->base.dev); 6131 struct intel_crtc_state *crtc_state; 6132 struct intel_crtc *crtc; 6133 u8 affected_pipes = 0; 6134 u8 modeset_pipes = 0; 6135 int i; 6136 6137 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6138 affected_pipes |= crtc_state->bigjoiner_pipes; 6139 if (intel_crtc_needs_modeset(crtc_state)) 6140 modeset_pipes |= crtc_state->bigjoiner_pipes; 6141 } 6142 6143 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) { 6144 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6145 if (IS_ERR(crtc_state)) 6146 return PTR_ERR(crtc_state); 6147 } 6148 6149 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) { 6150 int ret; 6151 6152 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6153 6154 crtc_state->uapi.mode_changed = true; 6155 6156 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); 6157 if (ret) 6158 return ret; 6159 6160 ret = intel_atomic_add_affected_planes(state, crtc); 6161 if (ret) 6162 return ret; 6163 } 6164 6165 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6166 /* Kill old bigjoiner link, we may re-establish afterwards */ 6167 if (intel_crtc_needs_modeset(crtc_state) && 6168 intel_crtc_is_bigjoiner_master(crtc_state)) 6169 kill_bigjoiner_slave(state, crtc); 6170 } 6171 6172 return 0; 6173 } 6174 6175 /** 6176 * intel_atomic_check - validate state object 6177 * @dev: drm device 6178 * @_state: state to validate 6179 */ 6180 int intel_atomic_check(struct drm_device *dev, 6181 struct drm_atomic_state *_state) 6182 { 6183 struct drm_i915_private *dev_priv = to_i915(dev); 6184 struct intel_atomic_state *state = to_intel_atomic_state(_state); 6185 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6186 struct intel_crtc *crtc; 6187 int ret, i; 6188 bool any_ms = false; 6189 6190 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6191 new_crtc_state, i) { 6192 /* 6193 * crtc's state no longer considered to be inherited 6194 * after the first userspace/client initiated commit. 6195 */ 6196 if (!state->internal) 6197 new_crtc_state->inherited = false; 6198 6199 if (new_crtc_state->inherited != old_crtc_state->inherited) 6200 new_crtc_state->uapi.mode_changed = true; 6201 6202 if (new_crtc_state->uapi.scaling_filter != 6203 old_crtc_state->uapi.scaling_filter) 6204 new_crtc_state->uapi.mode_changed = true; 6205 } 6206 6207 intel_vrr_check_modeset(state); 6208 6209 ret = drm_atomic_helper_check_modeset(dev, &state->base); 6210 if (ret) 6211 goto fail; 6212 6213 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6214 ret = intel_async_flip_check_uapi(state, crtc); 6215 if (ret) 6216 return ret; 6217 } 6218 6219 ret = intel_bigjoiner_add_affected_crtcs(state); 6220 if (ret) 6221 goto fail; 6222 6223 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6224 new_crtc_state, i) { 6225 if (!intel_crtc_needs_modeset(new_crtc_state)) { 6226 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 6227 copy_bigjoiner_crtc_state_nomodeset(state, crtc); 6228 else 6229 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 6230 continue; 6231 } 6232 6233 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) { 6234 drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable); 6235 continue; 6236 } 6237 6238 ret = intel_crtc_prepare_cleared_state(state, crtc); 6239 if (ret) 6240 goto fail; 6241 6242 if (!new_crtc_state->hw.enable) 6243 continue; 6244 6245 ret = intel_modeset_pipe_config(state, crtc); 6246 if (ret) 6247 goto fail; 6248 6249 ret = intel_atomic_check_bigjoiner(state, crtc); 6250 if (ret) 6251 goto fail; 6252 } 6253 6254 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6255 new_crtc_state, i) { 6256 if (!intel_crtc_needs_modeset(new_crtc_state)) 6257 continue; 6258 6259 if (new_crtc_state->hw.enable) { 6260 ret = intel_modeset_pipe_config_late(state, crtc); 6261 if (ret) 6262 goto fail; 6263 } 6264 6265 intel_crtc_check_fastset(old_crtc_state, new_crtc_state); 6266 } 6267 6268 /** 6269 * Check if fastset is allowed by external dependencies like other 6270 * pipes and transcoders. 6271 * 6272 * Right now it only forces a fullmodeset when the MST master 6273 * transcoder did not changed but the pipe of the master transcoder 6274 * needs a fullmodeset so all slaves also needs to do a fullmodeset or 6275 * in case of port synced crtcs, if one of the synced crtcs 6276 * needs a full modeset, all other synced crtcs should be 6277 * forced a full modeset. 6278 */ 6279 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6280 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state)) 6281 continue; 6282 6283 if (intel_dp_mst_is_slave_trans(new_crtc_state)) { 6284 enum transcoder master = new_crtc_state->mst_master_transcoder; 6285 6286 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) { 6287 new_crtc_state->uapi.mode_changed = true; 6288 new_crtc_state->update_pipe = false; 6289 } 6290 } 6291 6292 if (is_trans_port_sync_mode(new_crtc_state)) { 6293 u8 trans = new_crtc_state->sync_mode_slaves_mask; 6294 6295 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER) 6296 trans |= BIT(new_crtc_state->master_transcoder); 6297 6298 if (intel_cpu_transcoders_need_modeset(state, trans)) { 6299 new_crtc_state->uapi.mode_changed = true; 6300 new_crtc_state->update_pipe = false; 6301 } 6302 } 6303 6304 if (new_crtc_state->bigjoiner_pipes) { 6305 if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) { 6306 new_crtc_state->uapi.mode_changed = true; 6307 new_crtc_state->update_pipe = false; 6308 } 6309 } 6310 } 6311 6312 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6313 new_crtc_state, i) { 6314 if (!intel_crtc_needs_modeset(new_crtc_state)) 6315 continue; 6316 6317 any_ms = true; 6318 6319 intel_release_shared_dplls(state, crtc); 6320 } 6321 6322 if (any_ms && !check_digital_port_conflicts(state)) { 6323 drm_dbg_kms(&dev_priv->drm, 6324 "rejecting conflicting digital port configuration\n"); 6325 ret = -EINVAL; 6326 goto fail; 6327 } 6328 6329 ret = drm_dp_mst_atomic_check(&state->base); 6330 if (ret) 6331 goto fail; 6332 6333 ret = intel_atomic_check_planes(state); 6334 if (ret) 6335 goto fail; 6336 6337 ret = intel_compute_global_watermarks(state); 6338 if (ret) 6339 goto fail; 6340 6341 ret = intel_bw_atomic_check(state); 6342 if (ret) 6343 goto fail; 6344 6345 ret = intel_cdclk_atomic_check(state, &any_ms); 6346 if (ret) 6347 goto fail; 6348 6349 if (intel_any_crtc_needs_modeset(state)) 6350 any_ms = true; 6351 6352 if (any_ms) { 6353 ret = intel_modeset_checks(state); 6354 if (ret) 6355 goto fail; 6356 6357 ret = intel_modeset_calc_cdclk(state); 6358 if (ret) 6359 return ret; 6360 } 6361 6362 ret = intel_pmdemand_atomic_check(state); 6363 if (ret) 6364 goto fail; 6365 6366 ret = intel_atomic_check_crtcs(state); 6367 if (ret) 6368 goto fail; 6369 6370 ret = intel_fbc_atomic_check(state); 6371 if (ret) 6372 goto fail; 6373 6374 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6375 new_crtc_state, i) { 6376 intel_color_assert_luts(new_crtc_state); 6377 6378 ret = intel_async_flip_check_hw(state, crtc); 6379 if (ret) 6380 goto fail; 6381 6382 /* Either full modeset or fastset (or neither), never both */ 6383 drm_WARN_ON(&dev_priv->drm, 6384 intel_crtc_needs_modeset(new_crtc_state) && 6385 intel_crtc_needs_fastset(new_crtc_state)); 6386 6387 if (!intel_crtc_needs_modeset(new_crtc_state) && 6388 !intel_crtc_needs_fastset(new_crtc_state)) 6389 continue; 6390 6391 intel_crtc_state_dump(new_crtc_state, state, 6392 intel_crtc_needs_modeset(new_crtc_state) ? 6393 "modeset" : "fastset"); 6394 } 6395 6396 return 0; 6397 6398 fail: 6399 if (ret == -EDEADLK) 6400 return ret; 6401 6402 /* 6403 * FIXME would probably be nice to know which crtc specifically 6404 * caused the failure, in cases where we can pinpoint it. 6405 */ 6406 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6407 new_crtc_state, i) 6408 intel_crtc_state_dump(new_crtc_state, state, "failed"); 6409 6410 return ret; 6411 } 6412 6413 static int intel_atomic_prepare_commit(struct intel_atomic_state *state) 6414 { 6415 struct intel_crtc_state *crtc_state; 6416 struct intel_crtc *crtc; 6417 int i, ret; 6418 6419 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base); 6420 if (ret < 0) 6421 return ret; 6422 6423 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6424 if (intel_crtc_needs_color_update(crtc_state)) 6425 intel_color_prepare_commit(crtc_state); 6426 } 6427 6428 return 0; 6429 } 6430 6431 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 6432 struct intel_crtc_state *crtc_state) 6433 { 6434 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6435 6436 if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes) 6437 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 6438 6439 if (crtc_state->has_pch_encoder) { 6440 enum pipe pch_transcoder = 6441 intel_crtc_pch_transcoder(crtc); 6442 6443 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true); 6444 } 6445 } 6446 6447 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, 6448 const struct intel_crtc_state *new_crtc_state) 6449 { 6450 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 6451 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6452 6453 /* 6454 * Update pipe size and adjust fitter if needed: the reason for this is 6455 * that in compute_mode_changes we check the native mode (not the pfit 6456 * mode) to see if we can flip rather than do a full mode set. In the 6457 * fastboot case, we'll flip, but if we don't update the pipesrc and 6458 * pfit state, we'll end up with a big fb scanned out into the wrong 6459 * sized surface. 6460 */ 6461 intel_set_pipe_src_size(new_crtc_state); 6462 6463 /* on skylake this is done by detaching scalers */ 6464 if (DISPLAY_VER(dev_priv) >= 9) { 6465 if (new_crtc_state->pch_pfit.enabled) 6466 skl_pfit_enable(new_crtc_state); 6467 } else if (HAS_PCH_SPLIT(dev_priv)) { 6468 if (new_crtc_state->pch_pfit.enabled) 6469 ilk_pfit_enable(new_crtc_state); 6470 else if (old_crtc_state->pch_pfit.enabled) 6471 ilk_pfit_disable(old_crtc_state); 6472 } 6473 6474 /* 6475 * The register is supposedly single buffered so perhaps 6476 * not 100% correct to do this here. But SKL+ calculate 6477 * this based on the adjust pixel rate so pfit changes do 6478 * affect it and so it must be updated for fastsets. 6479 * HSW/BDW only really need this here for fastboot, after 6480 * that the value should not change without a full modeset. 6481 */ 6482 if (DISPLAY_VER(dev_priv) >= 9 || 6483 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 6484 hsw_set_linetime_wm(new_crtc_state); 6485 6486 if (new_crtc_state->seamless_m_n) 6487 intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder, 6488 &new_crtc_state->dp_m_n); 6489 } 6490 6491 static void commit_pipe_pre_planes(struct intel_atomic_state *state, 6492 struct intel_crtc *crtc) 6493 { 6494 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6495 const struct intel_crtc_state *old_crtc_state = 6496 intel_atomic_get_old_crtc_state(state, crtc); 6497 const struct intel_crtc_state *new_crtc_state = 6498 intel_atomic_get_new_crtc_state(state, crtc); 6499 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 6500 6501 /* 6502 * During modesets pipe configuration was programmed as the 6503 * CRTC was enabled. 6504 */ 6505 if (!modeset) { 6506 if (intel_crtc_needs_color_update(new_crtc_state)) 6507 intel_color_commit_arm(new_crtc_state); 6508 6509 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 6510 bdw_set_pipe_misc(new_crtc_state); 6511 6512 if (intel_crtc_needs_fastset(new_crtc_state)) 6513 intel_pipe_fastset(old_crtc_state, new_crtc_state); 6514 } 6515 6516 intel_psr2_program_trans_man_trk_ctl(new_crtc_state); 6517 6518 intel_atomic_update_watermarks(state, crtc); 6519 } 6520 6521 static void commit_pipe_post_planes(struct intel_atomic_state *state, 6522 struct intel_crtc *crtc) 6523 { 6524 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6525 const struct intel_crtc_state *new_crtc_state = 6526 intel_atomic_get_new_crtc_state(state, crtc); 6527 6528 /* 6529 * Disable the scaler(s) after the plane(s) so that we don't 6530 * get a catastrophic underrun even if the two operations 6531 * end up happening in two different frames. 6532 */ 6533 if (DISPLAY_VER(dev_priv) >= 9 && 6534 !intel_crtc_needs_modeset(new_crtc_state)) 6535 skl_detach_scalers(new_crtc_state); 6536 } 6537 6538 static void intel_enable_crtc(struct intel_atomic_state *state, 6539 struct intel_crtc *crtc) 6540 { 6541 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6542 const struct intel_crtc_state *new_crtc_state = 6543 intel_atomic_get_new_crtc_state(state, crtc); 6544 6545 if (!intel_crtc_needs_modeset(new_crtc_state)) 6546 return; 6547 6548 /* VRR will be enable later, if required */ 6549 intel_crtc_update_active_timings(new_crtc_state, false); 6550 6551 dev_priv->display.funcs.display->crtc_enable(state, crtc); 6552 6553 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 6554 return; 6555 6556 /* vblanks work again, re-enable pipe CRC. */ 6557 intel_crtc_enable_pipe_crc(crtc); 6558 } 6559 6560 static void intel_update_crtc(struct intel_atomic_state *state, 6561 struct intel_crtc *crtc) 6562 { 6563 struct drm_i915_private *i915 = to_i915(state->base.dev); 6564 const struct intel_crtc_state *old_crtc_state = 6565 intel_atomic_get_old_crtc_state(state, crtc); 6566 struct intel_crtc_state *new_crtc_state = 6567 intel_atomic_get_new_crtc_state(state, crtc); 6568 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 6569 6570 if (old_crtc_state->inherited || 6571 intel_crtc_needs_modeset(new_crtc_state)) { 6572 if (HAS_DPT(i915)) 6573 intel_dpt_configure(crtc); 6574 } 6575 6576 if (vrr_enabling(old_crtc_state, new_crtc_state)) { 6577 intel_vrr_enable(new_crtc_state); 6578 intel_crtc_update_active_timings(new_crtc_state, 6579 new_crtc_state->vrr.enable); 6580 } 6581 6582 if (!modeset) { 6583 if (new_crtc_state->preload_luts && 6584 intel_crtc_needs_color_update(new_crtc_state)) 6585 intel_color_load_luts(new_crtc_state); 6586 6587 intel_pre_plane_update(state, crtc); 6588 6589 if (intel_crtc_needs_fastset(new_crtc_state)) 6590 intel_encoders_update_pipe(state, crtc); 6591 6592 if (DISPLAY_VER(i915) >= 11 && 6593 intel_crtc_needs_fastset(new_crtc_state)) 6594 icl_set_pipe_chicken(new_crtc_state); 6595 } 6596 6597 intel_fbc_update(state, crtc); 6598 6599 drm_WARN_ON(&i915->drm, !intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF)); 6600 6601 if (!modeset && 6602 intel_crtc_needs_color_update(new_crtc_state)) 6603 intel_color_commit_noarm(new_crtc_state); 6604 6605 intel_crtc_planes_update_noarm(state, crtc); 6606 6607 /* Perform vblank evasion around commit operation */ 6608 intel_pipe_update_start(new_crtc_state); 6609 6610 commit_pipe_pre_planes(state, crtc); 6611 6612 intel_crtc_planes_update_arm(state, crtc); 6613 6614 commit_pipe_post_planes(state, crtc); 6615 6616 intel_pipe_update_end(new_crtc_state); 6617 6618 /* 6619 * We usually enable FIFO underrun interrupts as part of the 6620 * CRTC enable sequence during modesets. But when we inherit a 6621 * valid pipe configuration from the BIOS we need to take care 6622 * of enabling them on the CRTC's first fastset. 6623 */ 6624 if (intel_crtc_needs_fastset(new_crtc_state) && !modeset && 6625 old_crtc_state->inherited) 6626 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state); 6627 } 6628 6629 static void intel_old_crtc_state_disables(struct intel_atomic_state *state, 6630 struct intel_crtc_state *old_crtc_state, 6631 struct intel_crtc_state *new_crtc_state, 6632 struct intel_crtc *crtc) 6633 { 6634 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6635 6636 /* 6637 * We need to disable pipe CRC before disabling the pipe, 6638 * or we race against vblank off. 6639 */ 6640 intel_crtc_disable_pipe_crc(crtc); 6641 6642 dev_priv->display.funcs.display->crtc_disable(state, crtc); 6643 crtc->active = false; 6644 intel_fbc_disable(crtc); 6645 6646 if (!new_crtc_state->hw.active) 6647 intel_initial_watermarks(state, crtc); 6648 } 6649 6650 static void intel_commit_modeset_disables(struct intel_atomic_state *state) 6651 { 6652 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 6653 struct intel_crtc *crtc; 6654 u32 handled = 0; 6655 int i; 6656 6657 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6658 new_crtc_state, i) { 6659 if (!intel_crtc_needs_modeset(new_crtc_state)) 6660 continue; 6661 6662 if (!old_crtc_state->hw.active) 6663 continue; 6664 6665 intel_pre_plane_update(state, crtc); 6666 intel_crtc_disable_planes(state, crtc); 6667 } 6668 6669 /* Only disable port sync and MST slaves */ 6670 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6671 new_crtc_state, i) { 6672 if (!intel_crtc_needs_modeset(new_crtc_state)) 6673 continue; 6674 6675 if (!old_crtc_state->hw.active) 6676 continue; 6677 6678 /* In case of Transcoder port Sync master slave CRTCs can be 6679 * assigned in any order and we need to make sure that 6680 * slave CRTCs are disabled first and then master CRTC since 6681 * Slave vblanks are masked till Master Vblanks. 6682 */ 6683 if (!is_trans_port_sync_slave(old_crtc_state) && 6684 !intel_dp_mst_is_slave_trans(old_crtc_state) && 6685 !intel_crtc_is_bigjoiner_slave(old_crtc_state)) 6686 continue; 6687 6688 intel_old_crtc_state_disables(state, old_crtc_state, 6689 new_crtc_state, crtc); 6690 handled |= BIT(crtc->pipe); 6691 } 6692 6693 /* Disable everything else left on */ 6694 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6695 new_crtc_state, i) { 6696 if (!intel_crtc_needs_modeset(new_crtc_state) || 6697 (handled & BIT(crtc->pipe))) 6698 continue; 6699 6700 if (!old_crtc_state->hw.active) 6701 continue; 6702 6703 intel_old_crtc_state_disables(state, old_crtc_state, 6704 new_crtc_state, crtc); 6705 } 6706 } 6707 6708 static void intel_commit_modeset_enables(struct intel_atomic_state *state) 6709 { 6710 struct intel_crtc_state *new_crtc_state; 6711 struct intel_crtc *crtc; 6712 int i; 6713 6714 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6715 if (!new_crtc_state->hw.active) 6716 continue; 6717 6718 intel_enable_crtc(state, crtc); 6719 intel_update_crtc(state, crtc); 6720 } 6721 } 6722 6723 static void skl_commit_modeset_enables(struct intel_atomic_state *state) 6724 { 6725 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6726 struct intel_crtc *crtc; 6727 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6728 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; 6729 u8 update_pipes = 0, modeset_pipes = 0; 6730 int i; 6731 6732 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6733 enum pipe pipe = crtc->pipe; 6734 6735 if (!new_crtc_state->hw.active) 6736 continue; 6737 6738 /* ignore allocations for crtc's that have been turned off. */ 6739 if (!intel_crtc_needs_modeset(new_crtc_state)) { 6740 entries[pipe] = old_crtc_state->wm.skl.ddb; 6741 update_pipes |= BIT(pipe); 6742 } else { 6743 modeset_pipes |= BIT(pipe); 6744 } 6745 } 6746 6747 /* 6748 * Whenever the number of active pipes changes, we need to make sure we 6749 * update the pipes in the right order so that their ddb allocations 6750 * never overlap with each other between CRTC updates. Otherwise we'll 6751 * cause pipe underruns and other bad stuff. 6752 * 6753 * So first lets enable all pipes that do not need a fullmodeset as 6754 * those don't have any external dependency. 6755 */ 6756 while (update_pipes) { 6757 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6758 new_crtc_state, i) { 6759 enum pipe pipe = crtc->pipe; 6760 6761 if ((update_pipes & BIT(pipe)) == 0) 6762 continue; 6763 6764 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 6765 entries, I915_MAX_PIPES, pipe)) 6766 continue; 6767 6768 entries[pipe] = new_crtc_state->wm.skl.ddb; 6769 update_pipes &= ~BIT(pipe); 6770 6771 intel_update_crtc(state, crtc); 6772 6773 /* 6774 * If this is an already active pipe, it's DDB changed, 6775 * and this isn't the last pipe that needs updating 6776 * then we need to wait for a vblank to pass for the 6777 * new ddb allocation to take effect. 6778 */ 6779 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, 6780 &old_crtc_state->wm.skl.ddb) && 6781 (update_pipes | modeset_pipes)) 6782 intel_crtc_wait_for_next_vblank(crtc); 6783 } 6784 } 6785 6786 update_pipes = modeset_pipes; 6787 6788 /* 6789 * Enable all pipes that needs a modeset and do not depends on other 6790 * pipes 6791 */ 6792 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6793 enum pipe pipe = crtc->pipe; 6794 6795 if ((modeset_pipes & BIT(pipe)) == 0) 6796 continue; 6797 6798 if (intel_dp_mst_is_slave_trans(new_crtc_state) || 6799 is_trans_port_sync_master(new_crtc_state) || 6800 intel_crtc_is_bigjoiner_master(new_crtc_state)) 6801 continue; 6802 6803 modeset_pipes &= ~BIT(pipe); 6804 6805 intel_enable_crtc(state, crtc); 6806 } 6807 6808 /* 6809 * Then we enable all remaining pipes that depend on other 6810 * pipes: MST slaves and port sync masters, big joiner master 6811 */ 6812 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6813 enum pipe pipe = crtc->pipe; 6814 6815 if ((modeset_pipes & BIT(pipe)) == 0) 6816 continue; 6817 6818 modeset_pipes &= ~BIT(pipe); 6819 6820 intel_enable_crtc(state, crtc); 6821 } 6822 6823 /* 6824 * Finally we do the plane updates/etc. for all pipes that got enabled. 6825 */ 6826 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6827 enum pipe pipe = crtc->pipe; 6828 6829 if ((update_pipes & BIT(pipe)) == 0) 6830 continue; 6831 6832 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 6833 entries, I915_MAX_PIPES, pipe)); 6834 6835 entries[pipe] = new_crtc_state->wm.skl.ddb; 6836 update_pipes &= ~BIT(pipe); 6837 6838 intel_update_crtc(state, crtc); 6839 } 6840 6841 drm_WARN_ON(&dev_priv->drm, modeset_pipes); 6842 drm_WARN_ON(&dev_priv->drm, update_pipes); 6843 } 6844 6845 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) 6846 { 6847 struct intel_atomic_state *state, *next; 6848 struct llist_node *freed; 6849 6850 freed = llist_del_all(&dev_priv->display.atomic_helper.free_list); 6851 llist_for_each_entry_safe(state, next, freed, freed) 6852 drm_atomic_state_put(&state->base); 6853 } 6854 6855 void intel_atomic_helper_free_state_worker(struct work_struct *work) 6856 { 6857 struct drm_i915_private *dev_priv = 6858 container_of(work, typeof(*dev_priv), display.atomic_helper.free_work); 6859 6860 intel_atomic_helper_free_state(dev_priv); 6861 } 6862 6863 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) 6864 { 6865 struct wait_queue_entry wait_fence, wait_reset; 6866 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); 6867 6868 init_wait_entry(&wait_fence, 0); 6869 init_wait_entry(&wait_reset, 0); 6870 for (;;) { 6871 prepare_to_wait(&intel_state->commit_ready.wait, 6872 &wait_fence, TASK_UNINTERRUPTIBLE); 6873 prepare_to_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 6874 I915_RESET_MODESET), 6875 &wait_reset, TASK_UNINTERRUPTIBLE); 6876 6877 6878 if (i915_sw_fence_done(&intel_state->commit_ready) || 6879 test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags)) 6880 break; 6881 6882 schedule(); 6883 } 6884 finish_wait(&intel_state->commit_ready.wait, &wait_fence); 6885 finish_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 6886 I915_RESET_MODESET), 6887 &wait_reset); 6888 } 6889 6890 static void intel_atomic_cleanup_work(struct work_struct *work) 6891 { 6892 struct intel_atomic_state *state = 6893 container_of(work, struct intel_atomic_state, base.commit_work); 6894 struct drm_i915_private *i915 = to_i915(state->base.dev); 6895 struct intel_crtc_state *old_crtc_state; 6896 struct intel_crtc *crtc; 6897 int i; 6898 6899 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) 6900 intel_color_cleanup_commit(old_crtc_state); 6901 6902 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base); 6903 drm_atomic_helper_commit_cleanup_done(&state->base); 6904 drm_atomic_state_put(&state->base); 6905 6906 intel_atomic_helper_free_state(i915); 6907 } 6908 6909 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state) 6910 { 6911 struct drm_i915_private *i915 = to_i915(state->base.dev); 6912 struct intel_plane *plane; 6913 struct intel_plane_state *plane_state; 6914 int i; 6915 6916 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 6917 struct drm_framebuffer *fb = plane_state->hw.fb; 6918 int cc_plane; 6919 int ret; 6920 6921 if (!fb) 6922 continue; 6923 6924 cc_plane = intel_fb_rc_ccs_cc_plane(fb); 6925 if (cc_plane < 0) 6926 continue; 6927 6928 /* 6929 * The layout of the fast clear color value expected by HW 6930 * (the DRM ABI requiring this value to be located in fb at 6931 * offset 0 of cc plane, plane #2 previous generations or 6932 * plane #1 for flat ccs): 6933 * - 4 x 4 bytes per-channel value 6934 * (in surface type specific float/int format provided by the fb user) 6935 * - 8 bytes native color value used by the display 6936 * (converted/written by GPU during a fast clear operation using the 6937 * above per-channel values) 6938 * 6939 * The commit's FB prepare hook already ensured that FB obj is pinned and the 6940 * caller made sure that the object is synced wrt. the related color clear value 6941 * GPU write on it. 6942 */ 6943 ret = i915_gem_object_read_from_page(intel_fb_obj(fb), 6944 fb->offsets[cc_plane] + 16, 6945 &plane_state->ccval, 6946 sizeof(plane_state->ccval)); 6947 /* The above could only fail if the FB obj has an unexpected backing store type. */ 6948 drm_WARN_ON(&i915->drm, ret); 6949 } 6950 } 6951 6952 static void intel_atomic_commit_tail(struct intel_atomic_state *state) 6953 { 6954 struct drm_device *dev = state->base.dev; 6955 struct drm_i915_private *dev_priv = to_i915(dev); 6956 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 6957 struct intel_crtc *crtc; 6958 struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {}; 6959 intel_wakeref_t wakeref = 0; 6960 int i; 6961 6962 intel_atomic_commit_fence_wait(state); 6963 6964 drm_atomic_helper_wait_for_dependencies(&state->base); 6965 drm_dp_mst_atomic_wait_for_dependencies(&state->base); 6966 6967 /* 6968 * During full modesets we write a lot of registers, wait 6969 * for PLLs, etc. Doing that while DC states are enabled 6970 * is not a good idea. 6971 * 6972 * During fastsets and other updates we also need to 6973 * disable DC states due to the following scenario: 6974 * 1. DC5 exit and PSR exit happen 6975 * 2. Some or all _noarm() registers are written 6976 * 3. Due to some long delay PSR is re-entered 6977 * 4. DC5 entry -> DMC saves the already written new 6978 * _noarm() registers and the old not yet written 6979 * _arm() registers 6980 * 5. DC5 exit -> DMC restores a mixture of old and 6981 * new register values and arms the update 6982 * 6. PSR exit -> hardware latches a mixture of old and 6983 * new register values -> corrupted frame, or worse 6984 * 7. New _arm() registers are finally written 6985 * 8. Hardware finally latches a complete set of new 6986 * register values, and subsequent frames will be OK again 6987 * 6988 * Also note that due to the pipe CSC hardware issues on 6989 * SKL/GLK DC states must remain off until the pipe CSC 6990 * state readout has happened. Otherwise we risk corrupting 6991 * the CSC latched register values with the readout (see 6992 * skl_read_csc() and skl_color_commit_noarm()). 6993 */ 6994 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DC_OFF); 6995 6996 intel_atomic_prepare_plane_clear_colors(state); 6997 6998 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6999 new_crtc_state, i) { 7000 if (intel_crtc_needs_modeset(new_crtc_state) || 7001 intel_crtc_needs_fastset(new_crtc_state)) 7002 intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]); 7003 } 7004 7005 intel_commit_modeset_disables(state); 7006 7007 /* FIXME: Eventually get rid of our crtc->config pointer */ 7008 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7009 crtc->config = new_crtc_state; 7010 7011 /* 7012 * In XE_LPD+ Pmdemand combines many parameters such as voltage index, 7013 * plls, cdclk frequency, QGV point selection parameter etc. Voltage 7014 * index, cdclk/ddiclk frequencies are supposed to be configured before 7015 * the cdclk config is set. 7016 */ 7017 intel_pmdemand_pre_plane_update(state); 7018 7019 if (state->modeset) { 7020 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base); 7021 7022 intel_set_cdclk_pre_plane_update(state); 7023 7024 intel_modeset_verify_disabled(dev_priv, state); 7025 } 7026 7027 intel_sagv_pre_plane_update(state); 7028 7029 /* Complete the events for pipes that have now been disabled */ 7030 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7031 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 7032 7033 /* Complete events for now disable pipes here. */ 7034 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) { 7035 spin_lock_irq(&dev->event_lock); 7036 drm_crtc_send_vblank_event(&crtc->base, 7037 new_crtc_state->uapi.event); 7038 spin_unlock_irq(&dev->event_lock); 7039 7040 new_crtc_state->uapi.event = NULL; 7041 } 7042 } 7043 7044 intel_encoders_update_prepare(state); 7045 7046 intel_dbuf_pre_plane_update(state); 7047 intel_mbus_dbox_update(state); 7048 7049 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7050 if (new_crtc_state->do_async_flip) 7051 intel_crtc_enable_flip_done(state, crtc); 7052 } 7053 7054 /* Now enable the clocks, plane, pipe, and connectors that we set up. */ 7055 dev_priv->display.funcs.display->commit_modeset_enables(state); 7056 7057 if (state->modeset) 7058 intel_set_cdclk_post_plane_update(state); 7059 7060 intel_wait_for_vblank_workers(state); 7061 7062 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here 7063 * already, but still need the state for the delayed optimization. To 7064 * fix this: 7065 * - wrap the optimization/post_plane_update stuff into a per-crtc work. 7066 * - schedule that vblank worker _before_ calling hw_done 7067 * - at the start of commit_tail, cancel it _synchrously 7068 * - switch over to the vblank wait helper in the core after that since 7069 * we don't need out special handling any more. 7070 */ 7071 drm_atomic_helper_wait_for_flip_done(dev, &state->base); 7072 7073 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7074 if (new_crtc_state->do_async_flip) 7075 intel_crtc_disable_flip_done(state, crtc); 7076 } 7077 7078 /* 7079 * Now that the vblank has passed, we can go ahead and program the 7080 * optimal watermarks on platforms that need two-step watermark 7081 * programming. 7082 * 7083 * TODO: Move this (and other cleanup) to an async worker eventually. 7084 */ 7085 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7086 new_crtc_state, i) { 7087 /* 7088 * Gen2 reports pipe underruns whenever all planes are disabled. 7089 * So re-enable underrun reporting after some planes get enabled. 7090 * 7091 * We do this before .optimize_watermarks() so that we have a 7092 * chance of catching underruns with the intermediate watermarks 7093 * vs. the new plane configuration. 7094 */ 7095 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state)) 7096 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 7097 7098 intel_optimize_watermarks(state, crtc); 7099 } 7100 7101 intel_dbuf_post_plane_update(state); 7102 intel_psr_post_plane_update(state); 7103 7104 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7105 intel_post_plane_update(state, crtc); 7106 7107 intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]); 7108 7109 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state); 7110 7111 /* Must be done after gamma readout due to HSW split gamma vs. IPS w/a */ 7112 hsw_ips_post_update(state, crtc); 7113 7114 /* 7115 * Activate DRRS after state readout to avoid 7116 * dp_m_n vs. dp_m2_n2 confusion on BDW+. 7117 */ 7118 intel_drrs_activate(new_crtc_state); 7119 7120 /* 7121 * DSB cleanup is done in cleanup_work aligning with framebuffer 7122 * cleanup. So copy and reset the dsb structure to sync with 7123 * commit_done and later do dsb cleanup in cleanup_work. 7124 * 7125 * FIXME get rid of this funny new->old swapping 7126 */ 7127 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb); 7128 } 7129 7130 /* Underruns don't always raise interrupts, so check manually */ 7131 intel_check_cpu_fifo_underruns(dev_priv); 7132 intel_check_pch_fifo_underruns(dev_priv); 7133 7134 if (state->modeset) 7135 intel_verify_planes(state); 7136 7137 intel_sagv_post_plane_update(state); 7138 intel_pmdemand_post_plane_update(state); 7139 7140 drm_atomic_helper_commit_hw_done(&state->base); 7141 7142 if (state->modeset) { 7143 /* As one of the primary mmio accessors, KMS has a high 7144 * likelihood of triggering bugs in unclaimed access. After we 7145 * finish modesetting, see if an error has been flagged, and if 7146 * so enable debugging for the next modeset - and hope we catch 7147 * the culprit. 7148 */ 7149 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); 7150 } 7151 intel_display_power_put(dev_priv, POWER_DOMAIN_DC_OFF, wakeref); 7152 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7153 7154 /* 7155 * Defer the cleanup of the old state to a separate worker to not 7156 * impede the current task (userspace for blocking modesets) that 7157 * are executed inline. For out-of-line asynchronous modesets/flips, 7158 * deferring to a new worker seems overkill, but we would place a 7159 * schedule point (cond_resched()) here anyway to keep latencies 7160 * down. 7161 */ 7162 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work); 7163 queue_work(system_highpri_wq, &state->base.commit_work); 7164 } 7165 7166 static void intel_atomic_commit_work(struct work_struct *work) 7167 { 7168 struct intel_atomic_state *state = 7169 container_of(work, struct intel_atomic_state, base.commit_work); 7170 7171 intel_atomic_commit_tail(state); 7172 } 7173 7174 static int 7175 intel_atomic_commit_ready(struct i915_sw_fence *fence, 7176 enum i915_sw_fence_notify notify) 7177 { 7178 struct intel_atomic_state *state = 7179 container_of(fence, struct intel_atomic_state, commit_ready); 7180 7181 switch (notify) { 7182 case FENCE_COMPLETE: 7183 /* we do blocking waits in the worker, nothing to do here */ 7184 break; 7185 case FENCE_FREE: 7186 { 7187 struct drm_i915_private *i915 = to_i915(state->base.dev); 7188 struct intel_atomic_helper *helper = 7189 &i915->display.atomic_helper; 7190 7191 if (llist_add(&state->freed, &helper->free_list)) 7192 queue_work(i915->unordered_wq, &helper->free_work); 7193 break; 7194 } 7195 } 7196 7197 return NOTIFY_DONE; 7198 } 7199 7200 static void intel_atomic_track_fbs(struct intel_atomic_state *state) 7201 { 7202 struct intel_plane_state *old_plane_state, *new_plane_state; 7203 struct intel_plane *plane; 7204 int i; 7205 7206 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 7207 new_plane_state, i) 7208 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), 7209 to_intel_frontbuffer(new_plane_state->hw.fb), 7210 plane->frontbuffer_bit); 7211 } 7212 7213 int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state, 7214 bool nonblock) 7215 { 7216 struct intel_atomic_state *state = to_intel_atomic_state(_state); 7217 struct drm_i915_private *dev_priv = to_i915(dev); 7218 int ret = 0; 7219 7220 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 7221 7222 drm_atomic_state_get(&state->base); 7223 i915_sw_fence_init(&state->commit_ready, 7224 intel_atomic_commit_ready); 7225 7226 /* 7227 * The intel_legacy_cursor_update() fast path takes care 7228 * of avoiding the vblank waits for simple cursor 7229 * movement and flips. For cursor on/off and size changes, 7230 * we want to perform the vblank waits so that watermark 7231 * updates happen during the correct frames. Gen9+ have 7232 * double buffered watermarks and so shouldn't need this. 7233 * 7234 * Unset state->legacy_cursor_update before the call to 7235 * drm_atomic_helper_setup_commit() because otherwise 7236 * drm_atomic_helper_wait_for_flip_done() is a noop and 7237 * we get FIFO underruns because we didn't wait 7238 * for vblank. 7239 * 7240 * FIXME doing watermarks and fb cleanup from a vblank worker 7241 * (assuming we had any) would solve these problems. 7242 */ 7243 if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) { 7244 struct intel_crtc_state *new_crtc_state; 7245 struct intel_crtc *crtc; 7246 int i; 7247 7248 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7249 if (new_crtc_state->wm.need_postvbl_update || 7250 new_crtc_state->update_wm_post) 7251 state->base.legacy_cursor_update = false; 7252 } 7253 7254 ret = intel_atomic_prepare_commit(state); 7255 if (ret) { 7256 drm_dbg_atomic(&dev_priv->drm, 7257 "Preparing state failed with %i\n", ret); 7258 i915_sw_fence_commit(&state->commit_ready); 7259 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7260 return ret; 7261 } 7262 7263 ret = drm_atomic_helper_setup_commit(&state->base, nonblock); 7264 if (!ret) 7265 ret = drm_atomic_helper_swap_state(&state->base, true); 7266 if (!ret) 7267 intel_atomic_swap_global_state(state); 7268 7269 if (ret) { 7270 struct intel_crtc_state *new_crtc_state; 7271 struct intel_crtc *crtc; 7272 int i; 7273 7274 i915_sw_fence_commit(&state->commit_ready); 7275 7276 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7277 intel_color_cleanup_commit(new_crtc_state); 7278 7279 drm_atomic_helper_cleanup_planes(dev, &state->base); 7280 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7281 return ret; 7282 } 7283 intel_shared_dpll_swap_state(state); 7284 intel_atomic_track_fbs(state); 7285 7286 drm_atomic_state_get(&state->base); 7287 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work); 7288 7289 i915_sw_fence_commit(&state->commit_ready); 7290 if (nonblock && state->modeset) { 7291 queue_work(dev_priv->display.wq.modeset, &state->base.commit_work); 7292 } else if (nonblock) { 7293 queue_work(dev_priv->display.wq.flip, &state->base.commit_work); 7294 } else { 7295 if (state->modeset) 7296 flush_workqueue(dev_priv->display.wq.modeset); 7297 intel_atomic_commit_tail(state); 7298 } 7299 7300 return 0; 7301 } 7302 7303 /** 7304 * intel_plane_destroy - destroy a plane 7305 * @plane: plane to destroy 7306 * 7307 * Common destruction function for all types of planes (primary, cursor, 7308 * sprite). 7309 */ 7310 void intel_plane_destroy(struct drm_plane *plane) 7311 { 7312 drm_plane_cleanup(plane); 7313 kfree(to_intel_plane(plane)); 7314 } 7315 7316 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 7317 struct drm_file *file) 7318 { 7319 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; 7320 struct drm_crtc *drmmode_crtc; 7321 struct intel_crtc *crtc; 7322 7323 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id); 7324 if (!drmmode_crtc) 7325 return -ENOENT; 7326 7327 crtc = to_intel_crtc(drmmode_crtc); 7328 pipe_from_crtc_id->pipe = crtc->pipe; 7329 7330 return 0; 7331 } 7332 7333 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder) 7334 { 7335 struct drm_device *dev = encoder->base.dev; 7336 struct intel_encoder *source_encoder; 7337 u32 possible_clones = 0; 7338 7339 for_each_intel_encoder(dev, source_encoder) { 7340 if (encoders_cloneable(encoder, source_encoder)) 7341 possible_clones |= drm_encoder_mask(&source_encoder->base); 7342 } 7343 7344 return possible_clones; 7345 } 7346 7347 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder) 7348 { 7349 struct drm_device *dev = encoder->base.dev; 7350 struct intel_crtc *crtc; 7351 u32 possible_crtcs = 0; 7352 7353 for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask) 7354 possible_crtcs |= drm_crtc_mask(&crtc->base); 7355 7356 return possible_crtcs; 7357 } 7358 7359 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv) 7360 { 7361 if (!IS_MOBILE(dev_priv)) 7362 return false; 7363 7364 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0) 7365 return false; 7366 7367 if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE)) 7368 return false; 7369 7370 return true; 7371 } 7372 7373 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv) 7374 { 7375 if (DISPLAY_VER(dev_priv) >= 9) 7376 return false; 7377 7378 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) 7379 return false; 7380 7381 if (HAS_PCH_LPT_H(dev_priv) && 7382 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) 7383 return false; 7384 7385 /* DDI E can't be used if DDI A requires 4 lanes */ 7386 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 7387 return false; 7388 7389 if (!dev_priv->display.vbt.int_crt_support) 7390 return false; 7391 7392 return true; 7393 } 7394 7395 bool assert_port_valid(struct drm_i915_private *i915, enum port port) 7396 { 7397 return !drm_WARN(&i915->drm, !(DISPLAY_RUNTIME_INFO(i915)->port_mask & BIT(port)), 7398 "Platform does not support port %c\n", port_name(port)); 7399 } 7400 7401 void intel_setup_outputs(struct drm_i915_private *dev_priv) 7402 { 7403 struct intel_encoder *encoder; 7404 bool dpd_is_edp = false; 7405 7406 intel_pps_unlock_regs_wa(dev_priv); 7407 7408 if (!HAS_DISPLAY(dev_priv)) 7409 return; 7410 7411 if (DISPLAY_VER(dev_priv) >= 9) { 7412 enum port port; 7413 7414 for_each_port_masked(port, DISPLAY_RUNTIME_INFO(dev_priv)->port_mask) 7415 intel_ddi_init(dev_priv, port); 7416 7417 /* FIXME do something about DSI */ 7418 if (IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv) || 7419 DISPLAY_VER(dev_priv) == 11) 7420 icl_dsi_init(dev_priv); 7421 7422 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 7423 vlv_dsi_init(dev_priv); 7424 } else if (HAS_DDI(dev_priv)) { 7425 u32 found; 7426 7427 if (intel_ddi_crt_present(dev_priv)) 7428 intel_crt_init(dev_priv); 7429 7430 /* Haswell uses DDI functions to detect digital outputs. */ 7431 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 7432 if (found) 7433 intel_ddi_init(dev_priv, PORT_A); 7434 7435 found = intel_de_read(dev_priv, SFUSE_STRAP); 7436 if (found & SFUSE_STRAP_DDIB_DETECTED) 7437 intel_ddi_init(dev_priv, PORT_B); 7438 if (found & SFUSE_STRAP_DDIC_DETECTED) 7439 intel_ddi_init(dev_priv, PORT_C); 7440 if (found & SFUSE_STRAP_DDID_DETECTED) 7441 intel_ddi_init(dev_priv, PORT_D); 7442 } else if (HAS_PCH_SPLIT(dev_priv)) { 7443 int found; 7444 7445 /* 7446 * intel_edp_init_connector() depends on this completing first, 7447 * to prevent the registration of both eDP and LVDS and the 7448 * incorrect sharing of the PPS. 7449 */ 7450 intel_lvds_init(dev_priv); 7451 intel_crt_init(dev_priv); 7452 7453 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D); 7454 7455 if (ilk_has_edp_a(dev_priv)) 7456 g4x_dp_init(dev_priv, DP_A, PORT_A); 7457 7458 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) { 7459 /* PCH SDVOB multiplex with HDMIB */ 7460 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); 7461 if (!found) 7462 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); 7463 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED)) 7464 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B); 7465 } 7466 7467 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED) 7468 g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); 7469 7470 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED) 7471 g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D); 7472 7473 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED) 7474 g4x_dp_init(dev_priv, PCH_DP_C, PORT_C); 7475 7476 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED) 7477 g4x_dp_init(dev_priv, PCH_DP_D, PORT_D); 7478 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 7479 bool has_edp, has_port; 7480 7481 if (IS_VALLEYVIEW(dev_priv) && dev_priv->display.vbt.int_crt_support) 7482 intel_crt_init(dev_priv); 7483 7484 /* 7485 * The DP_DETECTED bit is the latched state of the DDC 7486 * SDA pin at boot. However since eDP doesn't require DDC 7487 * (no way to plug in a DP->HDMI dongle) the DDC pins for 7488 * eDP ports may have been muxed to an alternate function. 7489 * Thus we can't rely on the DP_DETECTED bit alone to detect 7490 * eDP ports. Consult the VBT as well as DP_DETECTED to 7491 * detect eDP ports. 7492 * 7493 * Sadly the straps seem to be missing sometimes even for HDMI 7494 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap 7495 * and VBT for the presence of the port. Additionally we can't 7496 * trust the port type the VBT declares as we've seen at least 7497 * HDMI ports that the VBT claim are DP or eDP. 7498 */ 7499 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B); 7500 has_port = intel_bios_is_port_present(dev_priv, PORT_B); 7501 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port) 7502 has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B); 7503 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) 7504 g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); 7505 7506 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C); 7507 has_port = intel_bios_is_port_present(dev_priv, PORT_C); 7508 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port) 7509 has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C); 7510 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) 7511 g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); 7512 7513 if (IS_CHERRYVIEW(dev_priv)) { 7514 /* 7515 * eDP not supported on port D, 7516 * so no need to worry about it 7517 */ 7518 has_port = intel_bios_is_port_present(dev_priv, PORT_D); 7519 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port) 7520 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D); 7521 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port) 7522 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D); 7523 } 7524 7525 vlv_dsi_init(dev_priv); 7526 } else if (IS_PINEVIEW(dev_priv)) { 7527 intel_lvds_init(dev_priv); 7528 intel_crt_init(dev_priv); 7529 } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) { 7530 bool found = false; 7531 7532 if (IS_MOBILE(dev_priv)) 7533 intel_lvds_init(dev_priv); 7534 7535 intel_crt_init(dev_priv); 7536 7537 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 7538 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n"); 7539 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); 7540 if (!found && IS_G4X(dev_priv)) { 7541 drm_dbg_kms(&dev_priv->drm, 7542 "probing HDMI on SDVOB\n"); 7543 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); 7544 } 7545 7546 if (!found && IS_G4X(dev_priv)) 7547 g4x_dp_init(dev_priv, DP_B, PORT_B); 7548 } 7549 7550 /* Before G4X SDVOC doesn't have its own detect register */ 7551 7552 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 7553 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n"); 7554 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); 7555 } 7556 7557 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) { 7558 7559 if (IS_G4X(dev_priv)) { 7560 drm_dbg_kms(&dev_priv->drm, 7561 "probing HDMI on SDVOC\n"); 7562 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); 7563 } 7564 if (IS_G4X(dev_priv)) 7565 g4x_dp_init(dev_priv, DP_C, PORT_C); 7566 } 7567 7568 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED)) 7569 g4x_dp_init(dev_priv, DP_D, PORT_D); 7570 7571 if (SUPPORTS_TV(dev_priv)) 7572 intel_tv_init(dev_priv); 7573 } else if (DISPLAY_VER(dev_priv) == 2) { 7574 if (IS_I85X(dev_priv)) 7575 intel_lvds_init(dev_priv); 7576 7577 intel_crt_init(dev_priv); 7578 intel_dvo_init(dev_priv); 7579 } 7580 7581 for_each_intel_encoder(&dev_priv->drm, encoder) { 7582 encoder->base.possible_crtcs = 7583 intel_encoder_possible_crtcs(encoder); 7584 encoder->base.possible_clones = 7585 intel_encoder_possible_clones(encoder); 7586 } 7587 7588 intel_init_pch_refclk(dev_priv); 7589 7590 drm_helper_move_panel_connectors_to_head(&dev_priv->drm); 7591 } 7592 7593 static int max_dotclock(struct drm_i915_private *i915) 7594 { 7595 int max_dotclock = i915->max_dotclk_freq; 7596 7597 /* icl+ might use bigjoiner */ 7598 if (DISPLAY_VER(i915) >= 11) 7599 max_dotclock *= 2; 7600 7601 return max_dotclock; 7602 } 7603 7604 enum drm_mode_status intel_mode_valid(struct drm_device *dev, 7605 const struct drm_display_mode *mode) 7606 { 7607 struct drm_i915_private *dev_priv = to_i915(dev); 7608 int hdisplay_max, htotal_max; 7609 int vdisplay_max, vtotal_max; 7610 7611 /* 7612 * Can't reject DBLSCAN here because Xorg ddxen can add piles 7613 * of DBLSCAN modes to the output's mode list when they detect 7614 * the scaling mode property on the connector. And they don't 7615 * ask the kernel to validate those modes in any way until 7616 * modeset time at which point the client gets a protocol error. 7617 * So in order to not upset those clients we silently ignore the 7618 * DBLSCAN flag on such connectors. For other connectors we will 7619 * reject modes with the DBLSCAN flag in encoder->compute_config(). 7620 * And we always reject DBLSCAN modes in connector->mode_valid() 7621 * as we never want such modes on the connector's mode list. 7622 */ 7623 7624 if (mode->vscan > 1) 7625 return MODE_NO_VSCAN; 7626 7627 if (mode->flags & DRM_MODE_FLAG_HSKEW) 7628 return MODE_H_ILLEGAL; 7629 7630 if (mode->flags & (DRM_MODE_FLAG_CSYNC | 7631 DRM_MODE_FLAG_NCSYNC | 7632 DRM_MODE_FLAG_PCSYNC)) 7633 return MODE_HSYNC; 7634 7635 if (mode->flags & (DRM_MODE_FLAG_BCAST | 7636 DRM_MODE_FLAG_PIXMUX | 7637 DRM_MODE_FLAG_CLKDIV2)) 7638 return MODE_BAD; 7639 7640 /* 7641 * Reject clearly excessive dotclocks early to 7642 * avoid having to worry about huge integers later. 7643 */ 7644 if (mode->clock > max_dotclock(dev_priv)) 7645 return MODE_CLOCK_HIGH; 7646 7647 /* Transcoder timing limits */ 7648 if (DISPLAY_VER(dev_priv) >= 11) { 7649 hdisplay_max = 16384; 7650 vdisplay_max = 8192; 7651 htotal_max = 16384; 7652 vtotal_max = 8192; 7653 } else if (DISPLAY_VER(dev_priv) >= 9 || 7654 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 7655 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ 7656 vdisplay_max = 4096; 7657 htotal_max = 8192; 7658 vtotal_max = 8192; 7659 } else if (DISPLAY_VER(dev_priv) >= 3) { 7660 hdisplay_max = 4096; 7661 vdisplay_max = 4096; 7662 htotal_max = 8192; 7663 vtotal_max = 8192; 7664 } else { 7665 hdisplay_max = 2048; 7666 vdisplay_max = 2048; 7667 htotal_max = 4096; 7668 vtotal_max = 4096; 7669 } 7670 7671 if (mode->hdisplay > hdisplay_max || 7672 mode->hsync_start > htotal_max || 7673 mode->hsync_end > htotal_max || 7674 mode->htotal > htotal_max) 7675 return MODE_H_ILLEGAL; 7676 7677 if (mode->vdisplay > vdisplay_max || 7678 mode->vsync_start > vtotal_max || 7679 mode->vsync_end > vtotal_max || 7680 mode->vtotal > vtotal_max) 7681 return MODE_V_ILLEGAL; 7682 7683 if (DISPLAY_VER(dev_priv) >= 5) { 7684 if (mode->hdisplay < 64 || 7685 mode->htotal - mode->hdisplay < 32) 7686 return MODE_H_ILLEGAL; 7687 7688 if (mode->vtotal - mode->vdisplay < 5) 7689 return MODE_V_ILLEGAL; 7690 } else { 7691 if (mode->htotal - mode->hdisplay < 32) 7692 return MODE_H_ILLEGAL; 7693 7694 if (mode->vtotal - mode->vdisplay < 3) 7695 return MODE_V_ILLEGAL; 7696 } 7697 7698 /* 7699 * Cantiga+ cannot handle modes with a hsync front porch of 0. 7700 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. 7701 */ 7702 if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) && 7703 mode->hsync_start == mode->hdisplay) 7704 return MODE_H_ILLEGAL; 7705 7706 return MODE_OK; 7707 } 7708 7709 enum drm_mode_status 7710 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 7711 const struct drm_display_mode *mode, 7712 bool bigjoiner) 7713 { 7714 int plane_width_max, plane_height_max; 7715 7716 /* 7717 * intel_mode_valid() should be 7718 * sufficient on older platforms. 7719 */ 7720 if (DISPLAY_VER(dev_priv) < 9) 7721 return MODE_OK; 7722 7723 /* 7724 * Most people will probably want a fullscreen 7725 * plane so let's not advertize modes that are 7726 * too big for that. 7727 */ 7728 if (DISPLAY_VER(dev_priv) >= 11) { 7729 plane_width_max = 5120 << bigjoiner; 7730 plane_height_max = 4320; 7731 } else { 7732 plane_width_max = 5120; 7733 plane_height_max = 4096; 7734 } 7735 7736 if (mode->hdisplay > plane_width_max) 7737 return MODE_H_ILLEGAL; 7738 7739 if (mode->vdisplay > plane_height_max) 7740 return MODE_V_ILLEGAL; 7741 7742 return MODE_OK; 7743 } 7744 7745 static const struct intel_display_funcs skl_display_funcs = { 7746 .get_pipe_config = hsw_get_pipe_config, 7747 .crtc_enable = hsw_crtc_enable, 7748 .crtc_disable = hsw_crtc_disable, 7749 .commit_modeset_enables = skl_commit_modeset_enables, 7750 .get_initial_plane_config = skl_get_initial_plane_config, 7751 }; 7752 7753 static const struct intel_display_funcs ddi_display_funcs = { 7754 .get_pipe_config = hsw_get_pipe_config, 7755 .crtc_enable = hsw_crtc_enable, 7756 .crtc_disable = hsw_crtc_disable, 7757 .commit_modeset_enables = intel_commit_modeset_enables, 7758 .get_initial_plane_config = i9xx_get_initial_plane_config, 7759 }; 7760 7761 static const struct intel_display_funcs pch_split_display_funcs = { 7762 .get_pipe_config = ilk_get_pipe_config, 7763 .crtc_enable = ilk_crtc_enable, 7764 .crtc_disable = ilk_crtc_disable, 7765 .commit_modeset_enables = intel_commit_modeset_enables, 7766 .get_initial_plane_config = i9xx_get_initial_plane_config, 7767 }; 7768 7769 static const struct intel_display_funcs vlv_display_funcs = { 7770 .get_pipe_config = i9xx_get_pipe_config, 7771 .crtc_enable = valleyview_crtc_enable, 7772 .crtc_disable = i9xx_crtc_disable, 7773 .commit_modeset_enables = intel_commit_modeset_enables, 7774 .get_initial_plane_config = i9xx_get_initial_plane_config, 7775 }; 7776 7777 static const struct intel_display_funcs i9xx_display_funcs = { 7778 .get_pipe_config = i9xx_get_pipe_config, 7779 .crtc_enable = i9xx_crtc_enable, 7780 .crtc_disable = i9xx_crtc_disable, 7781 .commit_modeset_enables = intel_commit_modeset_enables, 7782 .get_initial_plane_config = i9xx_get_initial_plane_config, 7783 }; 7784 7785 /** 7786 * intel_init_display_hooks - initialize the display modesetting hooks 7787 * @dev_priv: device private 7788 */ 7789 void intel_init_display_hooks(struct drm_i915_private *dev_priv) 7790 { 7791 if (DISPLAY_VER(dev_priv) >= 9) { 7792 dev_priv->display.funcs.display = &skl_display_funcs; 7793 } else if (HAS_DDI(dev_priv)) { 7794 dev_priv->display.funcs.display = &ddi_display_funcs; 7795 } else if (HAS_PCH_SPLIT(dev_priv)) { 7796 dev_priv->display.funcs.display = &pch_split_display_funcs; 7797 } else if (IS_CHERRYVIEW(dev_priv) || 7798 IS_VALLEYVIEW(dev_priv)) { 7799 dev_priv->display.funcs.display = &vlv_display_funcs; 7800 } else { 7801 dev_priv->display.funcs.display = &i9xx_display_funcs; 7802 } 7803 } 7804 7805 int intel_initial_commit(struct drm_device *dev) 7806 { 7807 struct drm_atomic_state *state = NULL; 7808 struct drm_modeset_acquire_ctx ctx; 7809 struct intel_crtc *crtc; 7810 int ret = 0; 7811 7812 state = drm_atomic_state_alloc(dev); 7813 if (!state) 7814 return -ENOMEM; 7815 7816 drm_modeset_acquire_init(&ctx, 0); 7817 7818 state->acquire_ctx = &ctx; 7819 to_intel_atomic_state(state)->internal = true; 7820 7821 retry: 7822 for_each_intel_crtc(dev, crtc) { 7823 struct intel_crtc_state *crtc_state = 7824 intel_atomic_get_crtc_state(state, crtc); 7825 7826 if (IS_ERR(crtc_state)) { 7827 ret = PTR_ERR(crtc_state); 7828 goto out; 7829 } 7830 7831 if (crtc_state->hw.active) { 7832 struct intel_encoder *encoder; 7833 7834 ret = drm_atomic_add_affected_planes(state, &crtc->base); 7835 if (ret) 7836 goto out; 7837 7838 /* 7839 * FIXME hack to force a LUT update to avoid the 7840 * plane update forcing the pipe gamma on without 7841 * having a proper LUT loaded. Remove once we 7842 * have readout for pipe gamma enable. 7843 */ 7844 crtc_state->uapi.color_mgmt_changed = true; 7845 7846 for_each_intel_encoder_mask(dev, encoder, 7847 crtc_state->uapi.encoder_mask) { 7848 if (encoder->initial_fastset_check && 7849 !encoder->initial_fastset_check(encoder, crtc_state)) { 7850 ret = drm_atomic_add_affected_connectors(state, 7851 &crtc->base); 7852 if (ret) 7853 goto out; 7854 } 7855 } 7856 } 7857 } 7858 7859 ret = drm_atomic_commit(state); 7860 7861 out: 7862 if (ret == -EDEADLK) { 7863 drm_atomic_state_clear(state); 7864 drm_modeset_backoff(&ctx); 7865 goto retry; 7866 } 7867 7868 drm_atomic_state_put(state); 7869 7870 drm_modeset_drop_locks(&ctx); 7871 drm_modeset_acquire_fini(&ctx); 7872 7873 return ret; 7874 } 7875 7876 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 7877 { 7878 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 7879 enum transcoder cpu_transcoder = (enum transcoder)pipe; 7880 /* 640x480@60Hz, ~25175 kHz */ 7881 struct dpll clock = { 7882 .m1 = 18, 7883 .m2 = 7, 7884 .p1 = 13, 7885 .p2 = 4, 7886 .n = 2, 7887 }; 7888 u32 dpll, fp; 7889 int i; 7890 7891 drm_WARN_ON(&dev_priv->drm, 7892 i9xx_calc_dpll_params(48000, &clock) != 25154); 7893 7894 drm_dbg_kms(&dev_priv->drm, 7895 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n", 7896 pipe_name(pipe), clock.vco, clock.dot); 7897 7898 fp = i9xx_dpll_compute_fp(&clock); 7899 dpll = DPLL_DVO_2X_MODE | 7900 DPLL_VGA_MODE_DIS | 7901 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | 7902 PLL_P2_DIVIDE_BY_4 | 7903 PLL_REF_INPUT_DREFCLK | 7904 DPLL_VCO_ENABLE; 7905 7906 intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder), 7907 HACTIVE(640 - 1) | HTOTAL(800 - 1)); 7908 intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder), 7909 HBLANK_START(640 - 1) | HBLANK_END(800 - 1)); 7910 intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder), 7911 HSYNC_START(656 - 1) | HSYNC_END(752 - 1)); 7912 intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder), 7913 VACTIVE(480 - 1) | VTOTAL(525 - 1)); 7914 intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), 7915 VBLANK_START(480 - 1) | VBLANK_END(525 - 1)); 7916 intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder), 7917 VSYNC_START(490 - 1) | VSYNC_END(492 - 1)); 7918 intel_de_write(dev_priv, PIPESRC(pipe), 7919 PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1)); 7920 7921 intel_de_write(dev_priv, FP0(pipe), fp); 7922 intel_de_write(dev_priv, FP1(pipe), fp); 7923 7924 /* 7925 * Apparently we need to have VGA mode enabled prior to changing 7926 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 7927 * dividers, even though the register value does change. 7928 */ 7929 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); 7930 intel_de_write(dev_priv, DPLL(pipe), dpll); 7931 7932 /* Wait for the clocks to stabilize. */ 7933 intel_de_posting_read(dev_priv, DPLL(pipe)); 7934 udelay(150); 7935 7936 /* The pixel multiplier can only be updated once the 7937 * DPLL is enabled and the clocks are stable. 7938 * 7939 * So write it again. 7940 */ 7941 intel_de_write(dev_priv, DPLL(pipe), dpll); 7942 7943 /* We do this three times for luck */ 7944 for (i = 0; i < 3 ; i++) { 7945 intel_de_write(dev_priv, DPLL(pipe), dpll); 7946 intel_de_posting_read(dev_priv, DPLL(pipe)); 7947 udelay(150); /* wait for warmup */ 7948 } 7949 7950 intel_de_write(dev_priv, TRANSCONF(pipe), TRANSCONF_ENABLE); 7951 intel_de_posting_read(dev_priv, TRANSCONF(pipe)); 7952 7953 intel_wait_for_pipe_scanline_moving(crtc); 7954 } 7955 7956 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 7957 { 7958 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 7959 7960 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n", 7961 pipe_name(pipe)); 7962 7963 drm_WARN_ON(&dev_priv->drm, 7964 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE); 7965 drm_WARN_ON(&dev_priv->drm, 7966 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE); 7967 drm_WARN_ON(&dev_priv->drm, 7968 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE); 7969 drm_WARN_ON(&dev_priv->drm, 7970 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK); 7971 drm_WARN_ON(&dev_priv->drm, 7972 intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK); 7973 7974 intel_de_write(dev_priv, TRANSCONF(pipe), 0); 7975 intel_de_posting_read(dev_priv, TRANSCONF(pipe)); 7976 7977 intel_wait_for_pipe_scanline_stopped(crtc); 7978 7979 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); 7980 intel_de_posting_read(dev_priv, DPLL(pipe)); 7981 } 7982 7983 void intel_hpd_poll_fini(struct drm_i915_private *i915) 7984 { 7985 struct intel_connector *connector; 7986 struct drm_connector_list_iter conn_iter; 7987 7988 /* Kill all the work that may have been queued by hpd. */ 7989 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 7990 for_each_intel_connector_iter(connector, &conn_iter) { 7991 if (connector->modeset_retry_work.func) 7992 cancel_work_sync(&connector->modeset_retry_work); 7993 if (connector->hdcp.shim) { 7994 cancel_delayed_work_sync(&connector->hdcp.check_work); 7995 cancel_work_sync(&connector->hdcp.prop_work); 7996 } 7997 } 7998 drm_connector_list_iter_end(&conn_iter); 7999 } 8000 8001 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915) 8002 { 8003 return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915); 8004 } 8005