1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <linux/dma-resv.h> 28 #include <linux/i2c.h> 29 #include <linux/input.h> 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/slab.h> 33 #include <linux/string_helpers.h> 34 35 #include <drm/display/drm_dp_helper.h> 36 #include <drm/drm_atomic.h> 37 #include <drm/drm_atomic_helper.h> 38 #include <drm/drm_atomic_uapi.h> 39 #include <drm/drm_damage_helper.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_fourcc.h> 42 #include <drm/drm_probe_helper.h> 43 #include <drm/drm_rect.h> 44 45 #include "gem/i915_gem_lmem.h" 46 #include "gem/i915_gem_object.h" 47 48 #include "g4x_dp.h" 49 #include "g4x_hdmi.h" 50 #include "hsw_ips.h" 51 #include "i915_drv.h" 52 #include "i915_reg.h" 53 #include "i915_utils.h" 54 #include "i9xx_plane.h" 55 #include "i9xx_wm.h" 56 #include "icl_dsi.h" 57 #include "intel_atomic.h" 58 #include "intel_atomic_plane.h" 59 #include "intel_audio.h" 60 #include "intel_bw.h" 61 #include "intel_cdclk.h" 62 #include "intel_clock_gating.h" 63 #include "intel_color.h" 64 #include "intel_crt.h" 65 #include "intel_crtc.h" 66 #include "intel_crtc_state_dump.h" 67 #include "intel_ddi.h" 68 #include "intel_de.h" 69 #include "intel_display_driver.h" 70 #include "intel_display_power.h" 71 #include "intel_display_types.h" 72 #include "intel_dmc.h" 73 #include "intel_dp.h" 74 #include "intel_dp_link_training.h" 75 #include "intel_dp_mst.h" 76 #include "intel_dpio_phy.h" 77 #include "intel_dpll.h" 78 #include "intel_dpll_mgr.h" 79 #include "intel_dpt.h" 80 #include "intel_drrs.h" 81 #include "intel_dsi.h" 82 #include "intel_dvo.h" 83 #include "intel_fb.h" 84 #include "intel_fbc.h" 85 #include "intel_fbdev.h" 86 #include "intel_fdi.h" 87 #include "intel_fifo_underrun.h" 88 #include "intel_frontbuffer.h" 89 #include "intel_hdmi.h" 90 #include "intel_hotplug.h" 91 #include "intel_lvds.h" 92 #include "intel_lvds_regs.h" 93 #include "intel_modeset_setup.h" 94 #include "intel_modeset_verify.h" 95 #include "intel_overlay.h" 96 #include "intel_panel.h" 97 #include "intel_pch_display.h" 98 #include "intel_pch_refclk.h" 99 #include "intel_pcode.h" 100 #include "intel_pipe_crc.h" 101 #include "intel_plane_initial.h" 102 #include "intel_pps.h" 103 #include "intel_psr.h" 104 #include "intel_sdvo.h" 105 #include "intel_snps_phy.h" 106 #include "intel_tc.h" 107 #include "intel_tv.h" 108 #include "intel_vblank.h" 109 #include "intel_vdsc.h" 110 #include "intel_vdsc_regs.h" 111 #include "intel_vga.h" 112 #include "intel_vrr.h" 113 #include "intel_wm.h" 114 #include "skl_scaler.h" 115 #include "skl_universal_plane.h" 116 #include "skl_watermark.h" 117 #include "vlv_dsi.h" 118 #include "vlv_dsi_pll.h" 119 #include "vlv_dsi_regs.h" 120 #include "vlv_sideband.h" 121 122 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state); 123 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state); 124 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state); 125 static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state); 126 127 /* returns HPLL frequency in kHz */ 128 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) 129 { 130 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; 131 132 /* Obtain SKU information */ 133 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & 134 CCK_FUSE_HPLL_FREQ_MASK; 135 136 return vco_freq[hpll_freq] * 1000; 137 } 138 139 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 140 const char *name, u32 reg, int ref_freq) 141 { 142 u32 val; 143 int divider; 144 145 val = vlv_cck_read(dev_priv, reg); 146 divider = val & CCK_FREQUENCY_VALUES; 147 148 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != 149 (divider << CCK_FREQUENCY_STATUS_SHIFT), 150 "%s change in progress\n", name); 151 152 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); 153 } 154 155 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 156 const char *name, u32 reg) 157 { 158 int hpll; 159 160 vlv_cck_get(dev_priv); 161 162 if (dev_priv->hpll_freq == 0) 163 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); 164 165 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); 166 167 vlv_cck_put(dev_priv); 168 169 return hpll; 170 } 171 172 void intel_update_czclk(struct drm_i915_private *dev_priv) 173 { 174 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) 175 return; 176 177 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", 178 CCK_CZ_CLOCK_CONTROL); 179 180 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", 181 dev_priv->czclk_freq); 182 } 183 184 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state) 185 { 186 return (crtc_state->active_planes & 187 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0; 188 } 189 190 /* WA Display #0827: Gen9:all */ 191 static void 192 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) 193 { 194 if (enable) 195 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 196 0, DUPS1_GATING_DIS | DUPS2_GATING_DIS); 197 else 198 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 199 DUPS1_GATING_DIS | DUPS2_GATING_DIS, 0); 200 } 201 202 /* Wa_2006604312:icl,ehl */ 203 static void 204 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 205 bool enable) 206 { 207 if (enable) 208 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 0, DPFR_GATING_DIS); 209 else 210 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), DPFR_GATING_DIS, 0); 211 } 212 213 /* Wa_1604331009:icl,jsl,ehl */ 214 static void 215 icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 216 bool enable) 217 { 218 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), CURSOR_GATING_DIS, 219 enable ? CURSOR_GATING_DIS : 0); 220 } 221 222 static bool 223 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state) 224 { 225 return crtc_state->master_transcoder != INVALID_TRANSCODER; 226 } 227 228 static bool 229 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state) 230 { 231 return crtc_state->sync_mode_slaves_mask != 0; 232 } 233 234 bool 235 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state) 236 { 237 return is_trans_port_sync_master(crtc_state) || 238 is_trans_port_sync_slave(crtc_state); 239 } 240 241 static enum pipe bigjoiner_master_pipe(const struct intel_crtc_state *crtc_state) 242 { 243 return ffs(crtc_state->bigjoiner_pipes) - 1; 244 } 245 246 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state) 247 { 248 if (crtc_state->bigjoiner_pipes) 249 return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state)); 250 else 251 return 0; 252 } 253 254 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state) 255 { 256 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 257 258 return crtc_state->bigjoiner_pipes && 259 crtc->pipe != bigjoiner_master_pipe(crtc_state); 260 } 261 262 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state) 263 { 264 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 265 266 return crtc_state->bigjoiner_pipes && 267 crtc->pipe == bigjoiner_master_pipe(crtc_state); 268 } 269 270 static int intel_bigjoiner_num_pipes(const struct intel_crtc_state *crtc_state) 271 { 272 return hweight8(crtc_state->bigjoiner_pipes); 273 } 274 275 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state) 276 { 277 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 278 279 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 280 return intel_crtc_for_pipe(i915, bigjoiner_master_pipe(crtc_state)); 281 else 282 return to_intel_crtc(crtc_state->uapi.crtc); 283 } 284 285 static void 286 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) 287 { 288 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 289 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 290 291 if (DISPLAY_VER(dev_priv) >= 4) { 292 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 293 294 /* Wait for the Pipe State to go off */ 295 if (intel_de_wait_for_clear(dev_priv, TRANSCONF(cpu_transcoder), 296 TRANSCONF_STATE_ENABLE, 100)) 297 drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n"); 298 } else { 299 intel_wait_for_pipe_scanline_stopped(crtc); 300 } 301 } 302 303 void assert_transcoder(struct drm_i915_private *dev_priv, 304 enum transcoder cpu_transcoder, bool state) 305 { 306 bool cur_state; 307 enum intel_display_power_domain power_domain; 308 intel_wakeref_t wakeref; 309 310 /* we keep both pipes enabled on 830 */ 311 if (IS_I830(dev_priv)) 312 state = true; 313 314 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 315 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 316 if (wakeref) { 317 u32 val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)); 318 cur_state = !!(val & TRANSCONF_ENABLE); 319 320 intel_display_power_put(dev_priv, power_domain, wakeref); 321 } else { 322 cur_state = false; 323 } 324 325 I915_STATE_WARN(cur_state != state, 326 "transcoder %s assertion failure (expected %s, current %s)\n", 327 transcoder_name(cpu_transcoder), 328 str_on_off(state), str_on_off(cur_state)); 329 } 330 331 static void assert_plane(struct intel_plane *plane, bool state) 332 { 333 enum pipe pipe; 334 bool cur_state; 335 336 cur_state = plane->get_hw_state(plane, &pipe); 337 338 I915_STATE_WARN(cur_state != state, 339 "%s assertion failure (expected %s, current %s)\n", 340 plane->base.name, str_on_off(state), 341 str_on_off(cur_state)); 342 } 343 344 #define assert_plane_enabled(p) assert_plane(p, true) 345 #define assert_plane_disabled(p) assert_plane(p, false) 346 347 static void assert_planes_disabled(struct intel_crtc *crtc) 348 { 349 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 350 struct intel_plane *plane; 351 352 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) 353 assert_plane_disabled(plane); 354 } 355 356 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 357 struct intel_digital_port *dig_port, 358 unsigned int expected_mask) 359 { 360 u32 port_mask; 361 i915_reg_t dpll_reg; 362 363 switch (dig_port->base.port) { 364 default: 365 MISSING_CASE(dig_port->base.port); 366 fallthrough; 367 case PORT_B: 368 port_mask = DPLL_PORTB_READY_MASK; 369 dpll_reg = DPLL(0); 370 break; 371 case PORT_C: 372 port_mask = DPLL_PORTC_READY_MASK; 373 dpll_reg = DPLL(0); 374 expected_mask <<= 4; 375 break; 376 case PORT_D: 377 port_mask = DPLL_PORTD_READY_MASK; 378 dpll_reg = DPIO_PHY_STATUS; 379 break; 380 } 381 382 if (intel_de_wait_for_register(dev_priv, dpll_reg, 383 port_mask, expected_mask, 1000)) 384 drm_WARN(&dev_priv->drm, 1, 385 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", 386 dig_port->base.base.base.id, dig_port->base.base.name, 387 intel_de_read(dev_priv, dpll_reg) & port_mask, 388 expected_mask); 389 } 390 391 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) 392 { 393 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 394 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 395 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 396 enum pipe pipe = crtc->pipe; 397 i915_reg_t reg; 398 u32 val; 399 400 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe)); 401 402 assert_planes_disabled(crtc); 403 404 /* 405 * A pipe without a PLL won't actually be able to drive bits from 406 * a plane. On ILK+ the pipe PLLs are integrated, so we don't 407 * need the check. 408 */ 409 if (HAS_GMCH(dev_priv)) { 410 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI)) 411 assert_dsi_pll_enabled(dev_priv); 412 else 413 assert_pll_enabled(dev_priv, pipe); 414 } else { 415 if (new_crtc_state->has_pch_encoder) { 416 /* if driving the PCH, we need FDI enabled */ 417 assert_fdi_rx_pll_enabled(dev_priv, 418 intel_crtc_pch_transcoder(crtc)); 419 assert_fdi_tx_pll_enabled(dev_priv, 420 (enum pipe) cpu_transcoder); 421 } 422 /* FIXME: assert CPU port conditions for SNB+ */ 423 } 424 425 /* Wa_22012358565:adl-p */ 426 if (DISPLAY_VER(dev_priv) == 13) 427 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe), 428 0, PIPE_ARB_USE_PROG_SLOTS); 429 430 reg = TRANSCONF(cpu_transcoder); 431 val = intel_de_read(dev_priv, reg); 432 if (val & TRANSCONF_ENABLE) { 433 /* we keep both pipes enabled on 830 */ 434 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv)); 435 return; 436 } 437 438 intel_de_write(dev_priv, reg, val | TRANSCONF_ENABLE); 439 intel_de_posting_read(dev_priv, reg); 440 441 /* 442 * Until the pipe starts PIPEDSL reads will return a stale value, 443 * which causes an apparent vblank timestamp jump when PIPEDSL 444 * resets to its proper value. That also messes up the frame count 445 * when it's derived from the timestamps. So let's wait for the 446 * pipe to start properly before we call drm_crtc_vblank_on() 447 */ 448 if (intel_crtc_max_vblank_count(new_crtc_state) == 0) 449 intel_wait_for_pipe_scanline_moving(crtc); 450 } 451 452 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) 453 { 454 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 455 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 456 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 457 enum pipe pipe = crtc->pipe; 458 i915_reg_t reg; 459 u32 val; 460 461 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe)); 462 463 /* 464 * Make sure planes won't keep trying to pump pixels to us, 465 * or we might hang the display. 466 */ 467 assert_planes_disabled(crtc); 468 469 reg = TRANSCONF(cpu_transcoder); 470 val = intel_de_read(dev_priv, reg); 471 if ((val & TRANSCONF_ENABLE) == 0) 472 return; 473 474 /* 475 * Double wide has implications for planes 476 * so best keep it disabled when not needed. 477 */ 478 if (old_crtc_state->double_wide) 479 val &= ~TRANSCONF_DOUBLE_WIDE; 480 481 /* Don't disable pipe or pipe PLLs if needed */ 482 if (!IS_I830(dev_priv)) 483 val &= ~TRANSCONF_ENABLE; 484 485 if (DISPLAY_VER(dev_priv) >= 14) 486 intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder), 487 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 488 else if (DISPLAY_VER(dev_priv) >= 12) 489 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 490 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 491 492 intel_de_write(dev_priv, reg, val); 493 if ((val & TRANSCONF_ENABLE) == 0) 494 intel_wait_for_pipe_off(old_crtc_state); 495 } 496 497 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) 498 { 499 unsigned int size = 0; 500 int i; 501 502 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) 503 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width; 504 505 return size; 506 } 507 508 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info) 509 { 510 unsigned int size = 0; 511 int i; 512 513 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) { 514 unsigned int plane_size; 515 516 if (rem_info->plane[i].linear) 517 plane_size = rem_info->plane[i].size; 518 else 519 plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height; 520 521 if (plane_size == 0) 522 continue; 523 524 if (rem_info->plane_alignment) 525 size = ALIGN(size, rem_info->plane_alignment); 526 527 size += plane_size; 528 } 529 530 return size; 531 } 532 533 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) 534 { 535 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 536 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 537 538 return DISPLAY_VER(dev_priv) < 4 || 539 (plane->fbc && 540 plane_state->view.gtt.type == I915_GTT_VIEW_NORMAL); 541 } 542 543 /* 544 * Convert the x/y offsets into a linear offset. 545 * Only valid with 0/180 degree rotation, which is fine since linear 546 * offset is only used with linear buffers on pre-hsw and tiled buffers 547 * with gen2/3, and 90/270 degree rotations isn't supported on any of them. 548 */ 549 u32 intel_fb_xy_to_linear(int x, int y, 550 const struct intel_plane_state *state, 551 int color_plane) 552 { 553 const struct drm_framebuffer *fb = state->hw.fb; 554 unsigned int cpp = fb->format->cpp[color_plane]; 555 unsigned int pitch = state->view.color_plane[color_plane].mapping_stride; 556 557 return y * pitch + x * cpp; 558 } 559 560 /* 561 * Add the x/y offsets derived from fb->offsets[] to the user 562 * specified plane src x/y offsets. The resulting x/y offsets 563 * specify the start of scanout from the beginning of the gtt mapping. 564 */ 565 void intel_add_fb_offsets(int *x, int *y, 566 const struct intel_plane_state *state, 567 int color_plane) 568 569 { 570 *x += state->view.color_plane[color_plane].x; 571 *y += state->view.color_plane[color_plane].y; 572 } 573 574 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 575 u32 pixel_format, u64 modifier) 576 { 577 struct intel_crtc *crtc; 578 struct intel_plane *plane; 579 580 if (!HAS_DISPLAY(dev_priv)) 581 return 0; 582 583 /* 584 * We assume the primary plane for pipe A has 585 * the highest stride limits of them all, 586 * if in case pipe A is disabled, use the first pipe from pipe_mask. 587 */ 588 crtc = intel_first_crtc(dev_priv); 589 if (!crtc) 590 return 0; 591 592 plane = to_intel_plane(crtc->base.primary); 593 594 return plane->max_stride(plane, pixel_format, modifier, 595 DRM_MODE_ROTATE_0); 596 } 597 598 void intel_set_plane_visible(struct intel_crtc_state *crtc_state, 599 struct intel_plane_state *plane_state, 600 bool visible) 601 { 602 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 603 604 plane_state->uapi.visible = visible; 605 606 if (visible) 607 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base); 608 else 609 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base); 610 } 611 612 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state) 613 { 614 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 615 struct drm_plane *plane; 616 617 /* 618 * Active_planes aliases if multiple "primary" or cursor planes 619 * have been used on the same (or wrong) pipe. plane_mask uses 620 * unique ids, hence we can use that to reconstruct active_planes. 621 */ 622 crtc_state->enabled_planes = 0; 623 crtc_state->active_planes = 0; 624 625 drm_for_each_plane_mask(plane, &dev_priv->drm, 626 crtc_state->uapi.plane_mask) { 627 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id); 628 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id); 629 } 630 } 631 632 void intel_plane_disable_noatomic(struct intel_crtc *crtc, 633 struct intel_plane *plane) 634 { 635 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 636 struct intel_crtc_state *crtc_state = 637 to_intel_crtc_state(crtc->base.state); 638 struct intel_plane_state *plane_state = 639 to_intel_plane_state(plane->base.state); 640 641 drm_dbg_kms(&dev_priv->drm, 642 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n", 643 plane->base.base.id, plane->base.name, 644 crtc->base.base.id, crtc->base.name); 645 646 intel_set_plane_visible(crtc_state, plane_state, false); 647 intel_plane_fixup_bitmasks(crtc_state); 648 crtc_state->data_rate[plane->id] = 0; 649 crtc_state->data_rate_y[plane->id] = 0; 650 crtc_state->rel_data_rate[plane->id] = 0; 651 crtc_state->rel_data_rate_y[plane->id] = 0; 652 crtc_state->min_cdclk[plane->id] = 0; 653 654 if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 && 655 hsw_ips_disable(crtc_state)) { 656 crtc_state->ips_enabled = false; 657 intel_crtc_wait_for_next_vblank(crtc); 658 } 659 660 /* 661 * Vblank time updates from the shadow to live plane control register 662 * are blocked if the memory self-refresh mode is active at that 663 * moment. So to make sure the plane gets truly disabled, disable 664 * first the self-refresh mode. The self-refresh enable bit in turn 665 * will be checked/applied by the HW only at the next frame start 666 * event which is after the vblank start event, so we need to have a 667 * wait-for-vblank between disabling the plane and the pipe. 668 */ 669 if (HAS_GMCH(dev_priv) && 670 intel_set_memory_cxsr(dev_priv, false)) 671 intel_crtc_wait_for_next_vblank(crtc); 672 673 /* 674 * Gen2 reports pipe underruns whenever all planes are disabled. 675 * So disable underrun reporting before all the planes get disabled. 676 */ 677 if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes) 678 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); 679 680 intel_plane_disable_arm(plane, crtc_state); 681 intel_crtc_wait_for_next_vblank(crtc); 682 } 683 684 unsigned int 685 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state) 686 { 687 int x = 0, y = 0; 688 689 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, 690 plane_state->view.color_plane[0].offset, 0); 691 692 return y; 693 } 694 695 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) 696 { 697 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 698 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 699 enum pipe pipe = crtc->pipe; 700 u32 tmp; 701 702 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe)); 703 704 /* 705 * Display WA #1153: icl 706 * enable hardware to bypass the alpha math 707 * and rounding for per-pixel values 00 and 0xff 708 */ 709 tmp |= PER_PIXEL_ALPHA_BYPASS_EN; 710 /* 711 * Display WA # 1605353570: icl 712 * Set the pixel rounding bit to 1 for allowing 713 * passthrough of Frame buffer pixels unmodified 714 * across pipe 715 */ 716 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU; 717 718 /* 719 * Underrun recovery must always be disabled on display 13+. 720 * DG2 chicken bit meaning is inverted compared to other platforms. 721 */ 722 if (IS_DG2(dev_priv)) 723 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2; 724 else if (DISPLAY_VER(dev_priv) >= 13) 725 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP; 726 727 /* Wa_14010547955:dg2 */ 728 if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER)) 729 tmp |= DG2_RENDER_CCSTAG_4_3_EN; 730 731 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp); 732 } 733 734 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) 735 { 736 struct drm_crtc *crtc; 737 bool cleanup_done; 738 739 drm_for_each_crtc(crtc, &dev_priv->drm) { 740 struct drm_crtc_commit *commit; 741 spin_lock(&crtc->commit_lock); 742 commit = list_first_entry_or_null(&crtc->commit_list, 743 struct drm_crtc_commit, commit_entry); 744 cleanup_done = commit ? 745 try_wait_for_completion(&commit->cleanup_done) : true; 746 spin_unlock(&crtc->commit_lock); 747 748 if (cleanup_done) 749 continue; 750 751 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc)); 752 753 return true; 754 } 755 756 return false; 757 } 758 759 /* 760 * Finds the encoder associated with the given CRTC. This can only be 761 * used when we know that the CRTC isn't feeding multiple encoders! 762 */ 763 struct intel_encoder * 764 intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 765 const struct intel_crtc_state *crtc_state) 766 { 767 const struct drm_connector_state *connector_state; 768 const struct drm_connector *connector; 769 struct intel_encoder *encoder = NULL; 770 struct intel_crtc *master_crtc; 771 int num_encoders = 0; 772 int i; 773 774 master_crtc = intel_master_crtc(crtc_state); 775 776 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 777 if (connector_state->crtc != &master_crtc->base) 778 continue; 779 780 encoder = to_intel_encoder(connector_state->best_encoder); 781 num_encoders++; 782 } 783 784 drm_WARN(state->base.dev, num_encoders != 1, 785 "%d encoders for pipe %c\n", 786 num_encoders, pipe_name(master_crtc->pipe)); 787 788 return encoder; 789 } 790 791 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state) 792 { 793 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 794 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 795 const struct drm_rect *dst = &crtc_state->pch_pfit.dst; 796 enum pipe pipe = crtc->pipe; 797 int width = drm_rect_width(dst); 798 int height = drm_rect_height(dst); 799 int x = dst->x1; 800 int y = dst->y1; 801 802 if (!crtc_state->pch_pfit.enabled) 803 return; 804 805 /* Force use of hard-coded filter coefficients 806 * as some pre-programmed values are broken, 807 * e.g. x201. 808 */ 809 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) 810 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 811 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe)); 812 else 813 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 814 PF_FILTER_MED_3x3); 815 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), x << 16 | y); 816 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), width << 16 | height); 817 } 818 819 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc) 820 { 821 if (crtc->overlay) 822 (void) intel_overlay_switch_off(crtc->overlay); 823 824 /* Let userspace switch the overlay on again. In most cases userspace 825 * has to recompute where to put it anyway. 826 */ 827 } 828 829 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state) 830 { 831 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 832 833 if (!crtc_state->nv12_planes) 834 return false; 835 836 /* WA Display #0827: Gen9:all */ 837 if (DISPLAY_VER(dev_priv) == 9) 838 return true; 839 840 return false; 841 } 842 843 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state) 844 { 845 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 846 847 /* Wa_2006604312:icl,ehl */ 848 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11) 849 return true; 850 851 return false; 852 } 853 854 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state) 855 { 856 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 857 858 /* Wa_1604331009:icl,jsl,ehl */ 859 if (is_hdr_mode(crtc_state) && 860 crtc_state->active_planes & BIT(PLANE_CURSOR) && 861 DISPLAY_VER(dev_priv) == 11) 862 return true; 863 864 return false; 865 } 866 867 static void intel_async_flip_vtd_wa(struct drm_i915_private *i915, 868 enum pipe pipe, bool enable) 869 { 870 if (DISPLAY_VER(i915) == 9) { 871 /* 872 * "Plane N strech max must be programmed to 11b (x1) 873 * when Async flips are enabled on that plane." 874 */ 875 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 876 SKL_PLANE1_STRETCH_MAX_MASK, 877 enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8); 878 } else { 879 /* Also needed on HSW/BDW albeit undocumented */ 880 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 881 HSW_PRI_STRETCH_MAX_MASK, 882 enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8); 883 } 884 } 885 886 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state) 887 { 888 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 889 890 return crtc_state->uapi.async_flip && i915_vtd_active(i915) && 891 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915)); 892 } 893 894 #define is_enabling(feature, old_crtc_state, new_crtc_state) \ 895 ((!(old_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)) && \ 896 (new_crtc_state)->feature) 897 #define is_disabling(feature, old_crtc_state, new_crtc_state) \ 898 ((old_crtc_state)->feature && \ 899 (!(new_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state))) 900 901 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state, 902 const struct intel_crtc_state *new_crtc_state) 903 { 904 return is_enabling(active_planes, old_crtc_state, new_crtc_state); 905 } 906 907 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state, 908 const struct intel_crtc_state *new_crtc_state) 909 { 910 return is_disabling(active_planes, old_crtc_state, new_crtc_state); 911 } 912 913 static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state, 914 const struct intel_crtc_state *new_crtc_state) 915 { 916 return is_enabling(vrr.enable, old_crtc_state, new_crtc_state); 917 } 918 919 static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state, 920 const struct intel_crtc_state *new_crtc_state) 921 { 922 return is_disabling(vrr.enable, old_crtc_state, new_crtc_state); 923 } 924 925 #undef is_disabling 926 #undef is_enabling 927 928 static void intel_post_plane_update(struct intel_atomic_state *state, 929 struct intel_crtc *crtc) 930 { 931 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 932 const struct intel_crtc_state *old_crtc_state = 933 intel_atomic_get_old_crtc_state(state, crtc); 934 const struct intel_crtc_state *new_crtc_state = 935 intel_atomic_get_new_crtc_state(state, crtc); 936 enum pipe pipe = crtc->pipe; 937 938 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); 939 940 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) 941 intel_update_watermarks(dev_priv); 942 943 intel_fbc_post_update(state, crtc); 944 945 if (needs_async_flip_vtd_wa(old_crtc_state) && 946 !needs_async_flip_vtd_wa(new_crtc_state)) 947 intel_async_flip_vtd_wa(dev_priv, pipe, false); 948 949 if (needs_nv12_wa(old_crtc_state) && 950 !needs_nv12_wa(new_crtc_state)) 951 skl_wa_827(dev_priv, pipe, false); 952 953 if (needs_scalerclk_wa(old_crtc_state) && 954 !needs_scalerclk_wa(new_crtc_state)) 955 icl_wa_scalerclkgating(dev_priv, pipe, false); 956 957 if (needs_cursorclk_wa(old_crtc_state) && 958 !needs_cursorclk_wa(new_crtc_state)) 959 icl_wa_cursorclkgating(dev_priv, pipe, false); 960 961 if (intel_crtc_needs_color_update(new_crtc_state)) 962 intel_color_post_update(new_crtc_state); 963 } 964 965 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state, 966 struct intel_crtc *crtc) 967 { 968 const struct intel_crtc_state *crtc_state = 969 intel_atomic_get_new_crtc_state(state, crtc); 970 u8 update_planes = crtc_state->update_planes; 971 const struct intel_plane_state *plane_state; 972 struct intel_plane *plane; 973 int i; 974 975 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 976 if (plane->pipe == crtc->pipe && 977 update_planes & BIT(plane->id)) 978 plane->enable_flip_done(plane); 979 } 980 } 981 982 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state, 983 struct intel_crtc *crtc) 984 { 985 const struct intel_crtc_state *crtc_state = 986 intel_atomic_get_new_crtc_state(state, crtc); 987 u8 update_planes = crtc_state->update_planes; 988 const struct intel_plane_state *plane_state; 989 struct intel_plane *plane; 990 int i; 991 992 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 993 if (plane->pipe == crtc->pipe && 994 update_planes & BIT(plane->id)) 995 plane->disable_flip_done(plane); 996 } 997 } 998 999 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state, 1000 struct intel_crtc *crtc) 1001 { 1002 const struct intel_crtc_state *old_crtc_state = 1003 intel_atomic_get_old_crtc_state(state, crtc); 1004 const struct intel_crtc_state *new_crtc_state = 1005 intel_atomic_get_new_crtc_state(state, crtc); 1006 u8 disable_async_flip_planes = old_crtc_state->async_flip_planes & 1007 ~new_crtc_state->async_flip_planes; 1008 const struct intel_plane_state *old_plane_state; 1009 struct intel_plane *plane; 1010 bool need_vbl_wait = false; 1011 int i; 1012 1013 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1014 if (plane->need_async_flip_disable_wa && 1015 plane->pipe == crtc->pipe && 1016 disable_async_flip_planes & BIT(plane->id)) { 1017 /* 1018 * Apart from the async flip bit we want to 1019 * preserve the old state for the plane. 1020 */ 1021 plane->async_flip(plane, old_crtc_state, 1022 old_plane_state, false); 1023 need_vbl_wait = true; 1024 } 1025 } 1026 1027 if (need_vbl_wait) 1028 intel_crtc_wait_for_next_vblank(crtc); 1029 } 1030 1031 static void intel_pre_plane_update(struct intel_atomic_state *state, 1032 struct intel_crtc *crtc) 1033 { 1034 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1035 const struct intel_crtc_state *old_crtc_state = 1036 intel_atomic_get_old_crtc_state(state, crtc); 1037 const struct intel_crtc_state *new_crtc_state = 1038 intel_atomic_get_new_crtc_state(state, crtc); 1039 enum pipe pipe = crtc->pipe; 1040 1041 if (vrr_disabling(old_crtc_state, new_crtc_state)) { 1042 intel_vrr_disable(old_crtc_state); 1043 intel_crtc_update_active_timings(old_crtc_state, false); 1044 } 1045 1046 intel_drrs_deactivate(old_crtc_state); 1047 1048 intel_psr_pre_plane_update(state, crtc); 1049 1050 if (hsw_ips_pre_update(state, crtc)) 1051 intel_crtc_wait_for_next_vblank(crtc); 1052 1053 if (intel_fbc_pre_update(state, crtc)) 1054 intel_crtc_wait_for_next_vblank(crtc); 1055 1056 if (!needs_async_flip_vtd_wa(old_crtc_state) && 1057 needs_async_flip_vtd_wa(new_crtc_state)) 1058 intel_async_flip_vtd_wa(dev_priv, pipe, true); 1059 1060 /* Display WA 827 */ 1061 if (!needs_nv12_wa(old_crtc_state) && 1062 needs_nv12_wa(new_crtc_state)) 1063 skl_wa_827(dev_priv, pipe, true); 1064 1065 /* Wa_2006604312:icl,ehl */ 1066 if (!needs_scalerclk_wa(old_crtc_state) && 1067 needs_scalerclk_wa(new_crtc_state)) 1068 icl_wa_scalerclkgating(dev_priv, pipe, true); 1069 1070 /* Wa_1604331009:icl,jsl,ehl */ 1071 if (!needs_cursorclk_wa(old_crtc_state) && 1072 needs_cursorclk_wa(new_crtc_state)) 1073 icl_wa_cursorclkgating(dev_priv, pipe, true); 1074 1075 /* 1076 * Vblank time updates from the shadow to live plane control register 1077 * are blocked if the memory self-refresh mode is active at that 1078 * moment. So to make sure the plane gets truly disabled, disable 1079 * first the self-refresh mode. The self-refresh enable bit in turn 1080 * will be checked/applied by the HW only at the next frame start 1081 * event which is after the vblank start event, so we need to have a 1082 * wait-for-vblank between disabling the plane and the pipe. 1083 */ 1084 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active && 1085 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) 1086 intel_crtc_wait_for_next_vblank(crtc); 1087 1088 /* 1089 * IVB workaround: must disable low power watermarks for at least 1090 * one frame before enabling scaling. LP watermarks can be re-enabled 1091 * when scaling is disabled. 1092 * 1093 * WaCxSRDisabledForSpriteScaling:ivb 1094 */ 1095 if (old_crtc_state->hw.active && 1096 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv)) 1097 intel_crtc_wait_for_next_vblank(crtc); 1098 1099 /* 1100 * If we're doing a modeset we don't need to do any 1101 * pre-vblank watermark programming here. 1102 */ 1103 if (!intel_crtc_needs_modeset(new_crtc_state)) { 1104 /* 1105 * For platforms that support atomic watermarks, program the 1106 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these 1107 * will be the intermediate values that are safe for both pre- and 1108 * post- vblank; when vblank happens, the 'active' values will be set 1109 * to the final 'target' values and we'll do this again to get the 1110 * optimal watermarks. For gen9+ platforms, the values we program here 1111 * will be the final target values which will get automatically latched 1112 * at vblank time; no further programming will be necessary. 1113 * 1114 * If a platform hasn't been transitioned to atomic watermarks yet, 1115 * we'll continue to update watermarks the old way, if flags tell 1116 * us to. 1117 */ 1118 if (!intel_initial_watermarks(state, crtc)) 1119 if (new_crtc_state->update_wm_pre) 1120 intel_update_watermarks(dev_priv); 1121 } 1122 1123 /* 1124 * Gen2 reports pipe underruns whenever all planes are disabled. 1125 * So disable underrun reporting before all the planes get disabled. 1126 * 1127 * We do this after .initial_watermarks() so that we have a 1128 * chance of catching underruns with the intermediate watermarks 1129 * vs. the old plane configuration. 1130 */ 1131 if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state)) 1132 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1133 1134 /* 1135 * WA for platforms where async address update enable bit 1136 * is double buffered and only latched at start of vblank. 1137 */ 1138 if (old_crtc_state->async_flip_planes & ~new_crtc_state->async_flip_planes) 1139 intel_crtc_async_flip_disable_wa(state, crtc); 1140 } 1141 1142 static void intel_crtc_disable_planes(struct intel_atomic_state *state, 1143 struct intel_crtc *crtc) 1144 { 1145 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1146 const struct intel_crtc_state *new_crtc_state = 1147 intel_atomic_get_new_crtc_state(state, crtc); 1148 unsigned int update_mask = new_crtc_state->update_planes; 1149 const struct intel_plane_state *old_plane_state; 1150 struct intel_plane *plane; 1151 unsigned fb_bits = 0; 1152 int i; 1153 1154 intel_crtc_dpms_overlay_disable(crtc); 1155 1156 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1157 if (crtc->pipe != plane->pipe || 1158 !(update_mask & BIT(plane->id))) 1159 continue; 1160 1161 intel_plane_disable_arm(plane, new_crtc_state); 1162 1163 if (old_plane_state->uapi.visible) 1164 fb_bits |= plane->frontbuffer_bit; 1165 } 1166 1167 intel_frontbuffer_flip(dev_priv, fb_bits); 1168 } 1169 1170 static void intel_encoders_update_prepare(struct intel_atomic_state *state) 1171 { 1172 struct drm_i915_private *i915 = to_i915(state->base.dev); 1173 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 1174 struct intel_crtc *crtc; 1175 int i; 1176 1177 /* 1178 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits. 1179 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook. 1180 */ 1181 if (i915->display.dpll.mgr) { 1182 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1183 if (intel_crtc_needs_modeset(new_crtc_state)) 1184 continue; 1185 1186 new_crtc_state->shared_dpll = old_crtc_state->shared_dpll; 1187 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state; 1188 } 1189 } 1190 } 1191 1192 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state, 1193 struct intel_crtc *crtc) 1194 { 1195 const struct intel_crtc_state *crtc_state = 1196 intel_atomic_get_new_crtc_state(state, crtc); 1197 const struct drm_connector_state *conn_state; 1198 struct drm_connector *conn; 1199 int i; 1200 1201 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1202 struct intel_encoder *encoder = 1203 to_intel_encoder(conn_state->best_encoder); 1204 1205 if (conn_state->crtc != &crtc->base) 1206 continue; 1207 1208 if (encoder->pre_pll_enable) 1209 encoder->pre_pll_enable(state, encoder, 1210 crtc_state, conn_state); 1211 } 1212 } 1213 1214 static void intel_encoders_pre_enable(struct intel_atomic_state *state, 1215 struct intel_crtc *crtc) 1216 { 1217 const struct intel_crtc_state *crtc_state = 1218 intel_atomic_get_new_crtc_state(state, crtc); 1219 const struct drm_connector_state *conn_state; 1220 struct drm_connector *conn; 1221 int i; 1222 1223 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1224 struct intel_encoder *encoder = 1225 to_intel_encoder(conn_state->best_encoder); 1226 1227 if (conn_state->crtc != &crtc->base) 1228 continue; 1229 1230 if (encoder->pre_enable) 1231 encoder->pre_enable(state, encoder, 1232 crtc_state, conn_state); 1233 } 1234 } 1235 1236 static void intel_encoders_enable(struct intel_atomic_state *state, 1237 struct intel_crtc *crtc) 1238 { 1239 const struct intel_crtc_state *crtc_state = 1240 intel_atomic_get_new_crtc_state(state, crtc); 1241 const struct drm_connector_state *conn_state; 1242 struct drm_connector *conn; 1243 int i; 1244 1245 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1246 struct intel_encoder *encoder = 1247 to_intel_encoder(conn_state->best_encoder); 1248 1249 if (conn_state->crtc != &crtc->base) 1250 continue; 1251 1252 if (encoder->enable) 1253 encoder->enable(state, encoder, 1254 crtc_state, conn_state); 1255 intel_opregion_notify_encoder(encoder, true); 1256 } 1257 } 1258 1259 static void intel_encoders_disable(struct intel_atomic_state *state, 1260 struct intel_crtc *crtc) 1261 { 1262 const struct intel_crtc_state *old_crtc_state = 1263 intel_atomic_get_old_crtc_state(state, crtc); 1264 const struct drm_connector_state *old_conn_state; 1265 struct drm_connector *conn; 1266 int i; 1267 1268 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1269 struct intel_encoder *encoder = 1270 to_intel_encoder(old_conn_state->best_encoder); 1271 1272 if (old_conn_state->crtc != &crtc->base) 1273 continue; 1274 1275 intel_opregion_notify_encoder(encoder, false); 1276 if (encoder->disable) 1277 encoder->disable(state, encoder, 1278 old_crtc_state, old_conn_state); 1279 } 1280 } 1281 1282 static void intel_encoders_post_disable(struct intel_atomic_state *state, 1283 struct intel_crtc *crtc) 1284 { 1285 const struct intel_crtc_state *old_crtc_state = 1286 intel_atomic_get_old_crtc_state(state, crtc); 1287 const struct drm_connector_state *old_conn_state; 1288 struct drm_connector *conn; 1289 int i; 1290 1291 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1292 struct intel_encoder *encoder = 1293 to_intel_encoder(old_conn_state->best_encoder); 1294 1295 if (old_conn_state->crtc != &crtc->base) 1296 continue; 1297 1298 if (encoder->post_disable) 1299 encoder->post_disable(state, encoder, 1300 old_crtc_state, old_conn_state); 1301 } 1302 } 1303 1304 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state, 1305 struct intel_crtc *crtc) 1306 { 1307 const struct intel_crtc_state *old_crtc_state = 1308 intel_atomic_get_old_crtc_state(state, crtc); 1309 const struct drm_connector_state *old_conn_state; 1310 struct drm_connector *conn; 1311 int i; 1312 1313 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1314 struct intel_encoder *encoder = 1315 to_intel_encoder(old_conn_state->best_encoder); 1316 1317 if (old_conn_state->crtc != &crtc->base) 1318 continue; 1319 1320 if (encoder->post_pll_disable) 1321 encoder->post_pll_disable(state, encoder, 1322 old_crtc_state, old_conn_state); 1323 } 1324 } 1325 1326 static void intel_encoders_update_pipe(struct intel_atomic_state *state, 1327 struct intel_crtc *crtc) 1328 { 1329 const struct intel_crtc_state *crtc_state = 1330 intel_atomic_get_new_crtc_state(state, crtc); 1331 const struct drm_connector_state *conn_state; 1332 struct drm_connector *conn; 1333 int i; 1334 1335 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1336 struct intel_encoder *encoder = 1337 to_intel_encoder(conn_state->best_encoder); 1338 1339 if (conn_state->crtc != &crtc->base) 1340 continue; 1341 1342 if (encoder->update_pipe) 1343 encoder->update_pipe(state, encoder, 1344 crtc_state, conn_state); 1345 } 1346 } 1347 1348 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state) 1349 { 1350 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1351 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 1352 1353 plane->disable_arm(plane, crtc_state); 1354 } 1355 1356 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1357 { 1358 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1359 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1360 1361 if (crtc_state->has_pch_encoder) { 1362 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1363 &crtc_state->fdi_m_n); 1364 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1365 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1366 &crtc_state->dp_m_n); 1367 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1368 &crtc_state->dp_m2_n2); 1369 } 1370 1371 intel_set_transcoder_timings(crtc_state); 1372 1373 ilk_set_pipeconf(crtc_state); 1374 } 1375 1376 static void ilk_crtc_enable(struct intel_atomic_state *state, 1377 struct intel_crtc *crtc) 1378 { 1379 const struct intel_crtc_state *new_crtc_state = 1380 intel_atomic_get_new_crtc_state(state, crtc); 1381 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1382 enum pipe pipe = crtc->pipe; 1383 1384 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1385 return; 1386 1387 /* 1388 * Sometimes spurious CPU pipe underruns happen during FDI 1389 * training, at least with VGA+HDMI cloning. Suppress them. 1390 * 1391 * On ILK we get an occasional spurious CPU pipe underruns 1392 * between eDP port A enable and vdd enable. Also PCH port 1393 * enable seems to result in the occasional CPU pipe underrun. 1394 * 1395 * Spurious PCH underruns also occur during PCH enabling. 1396 */ 1397 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1398 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 1399 1400 ilk_configure_cpu_transcoder(new_crtc_state); 1401 1402 intel_set_pipe_src_size(new_crtc_state); 1403 1404 crtc->active = true; 1405 1406 intel_encoders_pre_enable(state, crtc); 1407 1408 if (new_crtc_state->has_pch_encoder) { 1409 ilk_pch_pre_enable(state, crtc); 1410 } else { 1411 assert_fdi_tx_disabled(dev_priv, pipe); 1412 assert_fdi_rx_disabled(dev_priv, pipe); 1413 } 1414 1415 ilk_pfit_enable(new_crtc_state); 1416 1417 /* 1418 * On ILK+ LUT must be loaded before the pipe is running but with 1419 * clocks enabled 1420 */ 1421 intel_color_load_luts(new_crtc_state); 1422 intel_color_commit_noarm(new_crtc_state); 1423 intel_color_commit_arm(new_crtc_state); 1424 /* update DSPCNTR to configure gamma for pipe bottom color */ 1425 intel_disable_primary_plane(new_crtc_state); 1426 1427 intel_initial_watermarks(state, crtc); 1428 intel_enable_transcoder(new_crtc_state); 1429 1430 if (new_crtc_state->has_pch_encoder) 1431 ilk_pch_enable(state, crtc); 1432 1433 intel_crtc_vblank_on(new_crtc_state); 1434 1435 intel_encoders_enable(state, crtc); 1436 1437 if (HAS_PCH_CPT(dev_priv)) 1438 intel_wait_for_pipe_scanline_moving(crtc); 1439 1440 /* 1441 * Must wait for vblank to avoid spurious PCH FIFO underruns. 1442 * And a second vblank wait is needed at least on ILK with 1443 * some interlaced HDMI modes. Let's do the double wait always 1444 * in case there are more corner cases we don't know about. 1445 */ 1446 if (new_crtc_state->has_pch_encoder) { 1447 intel_crtc_wait_for_next_vblank(crtc); 1448 intel_crtc_wait_for_next_vblank(crtc); 1449 } 1450 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1451 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 1452 } 1453 1454 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, 1455 enum pipe pipe, bool apply) 1456 { 1457 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)); 1458 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS; 1459 1460 if (apply) 1461 val |= mask; 1462 else 1463 val &= ~mask; 1464 1465 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val); 1466 } 1467 1468 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state) 1469 { 1470 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1471 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1472 1473 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe), 1474 HSW_LINETIME(crtc_state->linetime) | 1475 HSW_IPS_LINETIME(crtc_state->ips_linetime)); 1476 } 1477 1478 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) 1479 { 1480 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1481 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1482 enum transcoder transcoder = crtc_state->cpu_transcoder; 1483 i915_reg_t reg = DISPLAY_VER(dev_priv) >= 14 ? MTL_CHICKEN_TRANS(transcoder) : 1484 CHICKEN_TRANS(transcoder); 1485 1486 intel_de_rmw(dev_priv, reg, 1487 HSW_FRAME_START_DELAY_MASK, 1488 HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1)); 1489 } 1490 1491 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state, 1492 const struct intel_crtc_state *crtc_state) 1493 { 1494 struct intel_crtc *master_crtc = intel_master_crtc(crtc_state); 1495 1496 /* 1497 * Enable sequence steps 1-7 on bigjoiner master 1498 */ 1499 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1500 intel_encoders_pre_pll_enable(state, master_crtc); 1501 1502 if (crtc_state->shared_dpll) 1503 intel_enable_shared_dpll(crtc_state); 1504 1505 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1506 intel_encoders_pre_enable(state, master_crtc); 1507 } 1508 1509 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1510 { 1511 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1512 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1513 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1514 1515 if (crtc_state->has_pch_encoder) { 1516 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1517 &crtc_state->fdi_m_n); 1518 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1519 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1520 &crtc_state->dp_m_n); 1521 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1522 &crtc_state->dp_m2_n2); 1523 } 1524 1525 intel_set_transcoder_timings(crtc_state); 1526 if (HAS_VRR(dev_priv)) 1527 intel_vrr_set_transcoder_timings(crtc_state); 1528 1529 if (cpu_transcoder != TRANSCODER_EDP) 1530 intel_de_write(dev_priv, TRANS_MULT(cpu_transcoder), 1531 crtc_state->pixel_multiplier - 1); 1532 1533 hsw_set_frame_start_delay(crtc_state); 1534 1535 hsw_set_transconf(crtc_state); 1536 } 1537 1538 static void hsw_crtc_enable(struct intel_atomic_state *state, 1539 struct intel_crtc *crtc) 1540 { 1541 const struct intel_crtc_state *new_crtc_state = 1542 intel_atomic_get_new_crtc_state(state, crtc); 1543 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1544 enum pipe pipe = crtc->pipe, hsw_workaround_pipe; 1545 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 1546 bool psl_clkgate_wa; 1547 1548 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1549 return; 1550 1551 intel_dmc_enable_pipe(dev_priv, crtc->pipe); 1552 1553 if (!new_crtc_state->bigjoiner_pipes) { 1554 intel_encoders_pre_pll_enable(state, crtc); 1555 1556 if (new_crtc_state->shared_dpll) 1557 intel_enable_shared_dpll(new_crtc_state); 1558 1559 intel_encoders_pre_enable(state, crtc); 1560 } else { 1561 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state); 1562 } 1563 1564 intel_dsc_enable(new_crtc_state); 1565 1566 if (DISPLAY_VER(dev_priv) >= 13) 1567 intel_uncompressed_joiner_enable(new_crtc_state); 1568 1569 intel_set_pipe_src_size(new_crtc_state); 1570 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 1571 bdw_set_pipe_misc(new_crtc_state); 1572 1573 if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) && 1574 !transcoder_is_dsi(cpu_transcoder)) 1575 hsw_configure_cpu_transcoder(new_crtc_state); 1576 1577 crtc->active = true; 1578 1579 /* Display WA #1180: WaDisableScalarClockGating: glk */ 1580 psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 && 1581 new_crtc_state->pch_pfit.enabled; 1582 if (psl_clkgate_wa) 1583 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true); 1584 1585 if (DISPLAY_VER(dev_priv) >= 9) 1586 skl_pfit_enable(new_crtc_state); 1587 else 1588 ilk_pfit_enable(new_crtc_state); 1589 1590 /* 1591 * On ILK+ LUT must be loaded before the pipe is running but with 1592 * clocks enabled 1593 */ 1594 intel_color_load_luts(new_crtc_state); 1595 intel_color_commit_noarm(new_crtc_state); 1596 intel_color_commit_arm(new_crtc_state); 1597 /* update DSPCNTR to configure gamma/csc for pipe bottom color */ 1598 if (DISPLAY_VER(dev_priv) < 9) 1599 intel_disable_primary_plane(new_crtc_state); 1600 1601 hsw_set_linetime_wm(new_crtc_state); 1602 1603 if (DISPLAY_VER(dev_priv) >= 11) 1604 icl_set_pipe_chicken(new_crtc_state); 1605 1606 intel_initial_watermarks(state, crtc); 1607 1608 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 1609 intel_crtc_vblank_on(new_crtc_state); 1610 1611 intel_encoders_enable(state, crtc); 1612 1613 if (psl_clkgate_wa) { 1614 intel_crtc_wait_for_next_vblank(crtc); 1615 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false); 1616 } 1617 1618 /* If we change the relative order between pipe/planes enabling, we need 1619 * to change the workaround. */ 1620 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe; 1621 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { 1622 struct intel_crtc *wa_crtc; 1623 1624 wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe); 1625 1626 intel_crtc_wait_for_next_vblank(wa_crtc); 1627 intel_crtc_wait_for_next_vblank(wa_crtc); 1628 } 1629 } 1630 1631 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state) 1632 { 1633 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1634 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1635 enum pipe pipe = crtc->pipe; 1636 1637 /* To avoid upsetting the power well on haswell only disable the pfit if 1638 * it's in use. The hw state code will make sure we get this right. */ 1639 if (!old_crtc_state->pch_pfit.enabled) 1640 return; 1641 1642 intel_de_write_fw(dev_priv, PF_CTL(pipe), 0); 1643 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0); 1644 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0); 1645 } 1646 1647 static void ilk_crtc_disable(struct intel_atomic_state *state, 1648 struct intel_crtc *crtc) 1649 { 1650 const struct intel_crtc_state *old_crtc_state = 1651 intel_atomic_get_old_crtc_state(state, crtc); 1652 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1653 enum pipe pipe = crtc->pipe; 1654 1655 /* 1656 * Sometimes spurious CPU pipe underruns happen when the 1657 * pipe is already disabled, but FDI RX/TX is still enabled. 1658 * Happens at least with VGA+HDMI cloning. Suppress them. 1659 */ 1660 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1661 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 1662 1663 intel_encoders_disable(state, crtc); 1664 1665 intel_crtc_vblank_off(old_crtc_state); 1666 1667 intel_disable_transcoder(old_crtc_state); 1668 1669 ilk_pfit_disable(old_crtc_state); 1670 1671 if (old_crtc_state->has_pch_encoder) 1672 ilk_pch_disable(state, crtc); 1673 1674 intel_encoders_post_disable(state, crtc); 1675 1676 if (old_crtc_state->has_pch_encoder) 1677 ilk_pch_post_disable(state, crtc); 1678 1679 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1680 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 1681 1682 intel_disable_shared_dpll(old_crtc_state); 1683 } 1684 1685 static void hsw_crtc_disable(struct intel_atomic_state *state, 1686 struct intel_crtc *crtc) 1687 { 1688 const struct intel_crtc_state *old_crtc_state = 1689 intel_atomic_get_old_crtc_state(state, crtc); 1690 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 1691 1692 /* 1693 * FIXME collapse everything to one hook. 1694 * Need care with mst->ddi interactions. 1695 */ 1696 if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) { 1697 intel_encoders_disable(state, crtc); 1698 intel_encoders_post_disable(state, crtc); 1699 } 1700 1701 intel_disable_shared_dpll(old_crtc_state); 1702 1703 intel_encoders_post_pll_disable(state, crtc); 1704 1705 intel_dmc_disable_pipe(i915, crtc->pipe); 1706 } 1707 1708 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) 1709 { 1710 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1711 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1712 1713 if (!crtc_state->gmch_pfit.control) 1714 return; 1715 1716 /* 1717 * The panel fitter should only be adjusted whilst the pipe is disabled, 1718 * according to register description and PRM. 1719 */ 1720 drm_WARN_ON(&dev_priv->drm, 1721 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE); 1722 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 1723 1724 intel_de_write(dev_priv, PFIT_PGM_RATIOS, 1725 crtc_state->gmch_pfit.pgm_ratios); 1726 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control); 1727 1728 /* Border color in case we don't scale up to the full screen. Black by 1729 * default, change to something else for debugging. */ 1730 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); 1731 } 1732 1733 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) 1734 { 1735 if (phy == PHY_NONE) 1736 return false; 1737 else if (IS_ALDERLAKE_S(dev_priv)) 1738 return phy <= PHY_E; 1739 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) 1740 return phy <= PHY_D; 1741 else if (IS_JSL_EHL(dev_priv)) 1742 return phy <= PHY_C; 1743 else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12)) 1744 return phy <= PHY_B; 1745 else 1746 /* 1747 * DG2 outputs labelled as "combo PHY" in the bspec use 1748 * SNPS PHYs with completely different programming, 1749 * hence we always return false here. 1750 */ 1751 return false; 1752 } 1753 1754 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) 1755 { 1756 if (IS_DG2(dev_priv)) 1757 /* DG2's "TC1" output uses a SNPS PHY */ 1758 return false; 1759 else if (IS_ALDERLAKE_P(dev_priv) || IS_METEORLAKE(dev_priv)) 1760 return phy >= PHY_F && phy <= PHY_I; 1761 else if (IS_TIGERLAKE(dev_priv)) 1762 return phy >= PHY_D && phy <= PHY_I; 1763 else if (IS_ICELAKE(dev_priv)) 1764 return phy >= PHY_C && phy <= PHY_F; 1765 else 1766 return false; 1767 } 1768 1769 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy) 1770 { 1771 if (phy == PHY_NONE) 1772 return false; 1773 else if (IS_DG2(dev_priv)) 1774 /* 1775 * All four "combo" ports and the TC1 port (PHY E) use 1776 * Synopsis PHYs. 1777 */ 1778 return phy <= PHY_E; 1779 1780 return false; 1781 } 1782 1783 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) 1784 { 1785 if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD) 1786 return PHY_D + port - PORT_D_XELPD; 1787 else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1) 1788 return PHY_F + port - PORT_TC1; 1789 else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1) 1790 return PHY_B + port - PORT_TC1; 1791 else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1) 1792 return PHY_C + port - PORT_TC1; 1793 else if (IS_JSL_EHL(i915) && port == PORT_D) 1794 return PHY_A; 1795 1796 return PHY_A + port - PORT_A; 1797 } 1798 1799 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) 1800 { 1801 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port))) 1802 return TC_PORT_NONE; 1803 1804 if (DISPLAY_VER(dev_priv) >= 12) 1805 return TC_PORT_1 + port - PORT_TC1; 1806 else 1807 return TC_PORT_1 + port - PORT_C; 1808 } 1809 1810 enum intel_display_power_domain 1811 intel_aux_power_domain(struct intel_digital_port *dig_port) 1812 { 1813 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1814 1815 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 1816 return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch); 1817 1818 return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch); 1819 } 1820 1821 static void get_crtc_power_domains(struct intel_crtc_state *crtc_state, 1822 struct intel_power_domain_mask *mask) 1823 { 1824 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1825 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1826 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1827 struct drm_encoder *encoder; 1828 enum pipe pipe = crtc->pipe; 1829 1830 bitmap_zero(mask->bits, POWER_DOMAIN_NUM); 1831 1832 if (!crtc_state->hw.active) 1833 return; 1834 1835 set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits); 1836 set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits); 1837 if (crtc_state->pch_pfit.enabled || 1838 crtc_state->pch_pfit.force_thru) 1839 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits); 1840 1841 drm_for_each_encoder_mask(encoder, &dev_priv->drm, 1842 crtc_state->uapi.encoder_mask) { 1843 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 1844 1845 set_bit(intel_encoder->power_domain, mask->bits); 1846 } 1847 1848 if (HAS_DDI(dev_priv) && crtc_state->has_audio) 1849 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits); 1850 1851 if (crtc_state->shared_dpll) 1852 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits); 1853 1854 if (crtc_state->dsc.compression_enable) 1855 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits); 1856 } 1857 1858 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, 1859 struct intel_power_domain_mask *old_domains) 1860 { 1861 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1862 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1863 enum intel_display_power_domain domain; 1864 struct intel_power_domain_mask domains, new_domains; 1865 1866 get_crtc_power_domains(crtc_state, &domains); 1867 1868 bitmap_andnot(new_domains.bits, 1869 domains.bits, 1870 crtc->enabled_power_domains.mask.bits, 1871 POWER_DOMAIN_NUM); 1872 bitmap_andnot(old_domains->bits, 1873 crtc->enabled_power_domains.mask.bits, 1874 domains.bits, 1875 POWER_DOMAIN_NUM); 1876 1877 for_each_power_domain(domain, &new_domains) 1878 intel_display_power_get_in_set(dev_priv, 1879 &crtc->enabled_power_domains, 1880 domain); 1881 } 1882 1883 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc, 1884 struct intel_power_domain_mask *domains) 1885 { 1886 intel_display_power_put_mask_in_set(to_i915(crtc->base.dev), 1887 &crtc->enabled_power_domains, 1888 domains); 1889 } 1890 1891 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1892 { 1893 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1894 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1895 1896 if (intel_crtc_has_dp_encoder(crtc_state)) { 1897 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1898 &crtc_state->dp_m_n); 1899 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1900 &crtc_state->dp_m2_n2); 1901 } 1902 1903 intel_set_transcoder_timings(crtc_state); 1904 1905 i9xx_set_pipeconf(crtc_state); 1906 } 1907 1908 static void valleyview_crtc_enable(struct intel_atomic_state *state, 1909 struct intel_crtc *crtc) 1910 { 1911 const struct intel_crtc_state *new_crtc_state = 1912 intel_atomic_get_new_crtc_state(state, crtc); 1913 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1914 enum pipe pipe = crtc->pipe; 1915 1916 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1917 return; 1918 1919 i9xx_configure_cpu_transcoder(new_crtc_state); 1920 1921 intel_set_pipe_src_size(new_crtc_state); 1922 1923 intel_de_write(dev_priv, VLV_PIPE_MSA_MISC(pipe), 0); 1924 1925 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 1926 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY); 1927 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0); 1928 } 1929 1930 crtc->active = true; 1931 1932 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1933 1934 intel_encoders_pre_pll_enable(state, crtc); 1935 1936 if (IS_CHERRYVIEW(dev_priv)) 1937 chv_enable_pll(new_crtc_state); 1938 else 1939 vlv_enable_pll(new_crtc_state); 1940 1941 intel_encoders_pre_enable(state, crtc); 1942 1943 i9xx_pfit_enable(new_crtc_state); 1944 1945 intel_color_load_luts(new_crtc_state); 1946 intel_color_commit_noarm(new_crtc_state); 1947 intel_color_commit_arm(new_crtc_state); 1948 /* update DSPCNTR to configure gamma for pipe bottom color */ 1949 intel_disable_primary_plane(new_crtc_state); 1950 1951 intel_initial_watermarks(state, crtc); 1952 intel_enable_transcoder(new_crtc_state); 1953 1954 intel_crtc_vblank_on(new_crtc_state); 1955 1956 intel_encoders_enable(state, crtc); 1957 } 1958 1959 static void i9xx_crtc_enable(struct intel_atomic_state *state, 1960 struct intel_crtc *crtc) 1961 { 1962 const struct intel_crtc_state *new_crtc_state = 1963 intel_atomic_get_new_crtc_state(state, crtc); 1964 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1965 enum pipe pipe = crtc->pipe; 1966 1967 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1968 return; 1969 1970 i9xx_configure_cpu_transcoder(new_crtc_state); 1971 1972 intel_set_pipe_src_size(new_crtc_state); 1973 1974 crtc->active = true; 1975 1976 if (DISPLAY_VER(dev_priv) != 2) 1977 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1978 1979 intel_encoders_pre_enable(state, crtc); 1980 1981 i9xx_enable_pll(new_crtc_state); 1982 1983 i9xx_pfit_enable(new_crtc_state); 1984 1985 intel_color_load_luts(new_crtc_state); 1986 intel_color_commit_noarm(new_crtc_state); 1987 intel_color_commit_arm(new_crtc_state); 1988 /* update DSPCNTR to configure gamma for pipe bottom color */ 1989 intel_disable_primary_plane(new_crtc_state); 1990 1991 if (!intel_initial_watermarks(state, crtc)) 1992 intel_update_watermarks(dev_priv); 1993 intel_enable_transcoder(new_crtc_state); 1994 1995 intel_crtc_vblank_on(new_crtc_state); 1996 1997 intel_encoders_enable(state, crtc); 1998 1999 /* prevents spurious underruns */ 2000 if (DISPLAY_VER(dev_priv) == 2) 2001 intel_crtc_wait_for_next_vblank(crtc); 2002 } 2003 2004 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) 2005 { 2006 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 2007 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2008 2009 if (!old_crtc_state->gmch_pfit.control) 2010 return; 2011 2012 assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder); 2013 2014 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n", 2015 intel_de_read(dev_priv, PFIT_CONTROL)); 2016 intel_de_write(dev_priv, PFIT_CONTROL, 0); 2017 } 2018 2019 static void i9xx_crtc_disable(struct intel_atomic_state *state, 2020 struct intel_crtc *crtc) 2021 { 2022 struct intel_crtc_state *old_crtc_state = 2023 intel_atomic_get_old_crtc_state(state, crtc); 2024 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2025 enum pipe pipe = crtc->pipe; 2026 2027 /* 2028 * On gen2 planes are double buffered but the pipe isn't, so we must 2029 * wait for planes to fully turn off before disabling the pipe. 2030 */ 2031 if (DISPLAY_VER(dev_priv) == 2) 2032 intel_crtc_wait_for_next_vblank(crtc); 2033 2034 intel_encoders_disable(state, crtc); 2035 2036 intel_crtc_vblank_off(old_crtc_state); 2037 2038 intel_disable_transcoder(old_crtc_state); 2039 2040 i9xx_pfit_disable(old_crtc_state); 2041 2042 intel_encoders_post_disable(state, crtc); 2043 2044 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) { 2045 if (IS_CHERRYVIEW(dev_priv)) 2046 chv_disable_pll(dev_priv, pipe); 2047 else if (IS_VALLEYVIEW(dev_priv)) 2048 vlv_disable_pll(dev_priv, pipe); 2049 else 2050 i9xx_disable_pll(old_crtc_state); 2051 } 2052 2053 intel_encoders_post_pll_disable(state, crtc); 2054 2055 if (DISPLAY_VER(dev_priv) != 2) 2056 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 2057 2058 if (!dev_priv->display.funcs.wm->initial_watermarks) 2059 intel_update_watermarks(dev_priv); 2060 2061 /* clock the pipe down to 640x480@60 to potentially save power */ 2062 if (IS_I830(dev_priv)) 2063 i830_enable_pipe(dev_priv, pipe); 2064 } 2065 2066 void intel_encoder_destroy(struct drm_encoder *encoder) 2067 { 2068 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2069 2070 drm_encoder_cleanup(encoder); 2071 kfree(intel_encoder); 2072 } 2073 2074 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) 2075 { 2076 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2077 2078 /* GDG double wide on either pipe, otherwise pipe A only */ 2079 return DISPLAY_VER(dev_priv) < 4 && 2080 (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); 2081 } 2082 2083 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) 2084 { 2085 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock; 2086 struct drm_rect src; 2087 2088 /* 2089 * We only use IF-ID interlacing. If we ever use 2090 * PF-ID we'll need to adjust the pixel_rate here. 2091 */ 2092 2093 if (!crtc_state->pch_pfit.enabled) 2094 return pixel_rate; 2095 2096 drm_rect_init(&src, 0, 0, 2097 drm_rect_width(&crtc_state->pipe_src) << 16, 2098 drm_rect_height(&crtc_state->pipe_src) << 16); 2099 2100 return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst, 2101 pixel_rate); 2102 } 2103 2104 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode, 2105 const struct drm_display_mode *timings) 2106 { 2107 mode->hdisplay = timings->crtc_hdisplay; 2108 mode->htotal = timings->crtc_htotal; 2109 mode->hsync_start = timings->crtc_hsync_start; 2110 mode->hsync_end = timings->crtc_hsync_end; 2111 2112 mode->vdisplay = timings->crtc_vdisplay; 2113 mode->vtotal = timings->crtc_vtotal; 2114 mode->vsync_start = timings->crtc_vsync_start; 2115 mode->vsync_end = timings->crtc_vsync_end; 2116 2117 mode->flags = timings->flags; 2118 mode->type = DRM_MODE_TYPE_DRIVER; 2119 2120 mode->clock = timings->crtc_clock; 2121 2122 drm_mode_set_name(mode); 2123 } 2124 2125 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) 2126 { 2127 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2128 2129 if (HAS_GMCH(dev_priv)) 2130 /* FIXME calculate proper pipe pixel rate for GMCH pfit */ 2131 crtc_state->pixel_rate = 2132 crtc_state->hw.pipe_mode.crtc_clock; 2133 else 2134 crtc_state->pixel_rate = 2135 ilk_pipe_pixel_rate(crtc_state); 2136 } 2137 2138 static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state *crtc_state, 2139 struct drm_display_mode *mode) 2140 { 2141 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2142 2143 if (num_pipes < 2) 2144 return; 2145 2146 mode->crtc_clock /= num_pipes; 2147 mode->crtc_hdisplay /= num_pipes; 2148 mode->crtc_hblank_start /= num_pipes; 2149 mode->crtc_hblank_end /= num_pipes; 2150 mode->crtc_hsync_start /= num_pipes; 2151 mode->crtc_hsync_end /= num_pipes; 2152 mode->crtc_htotal /= num_pipes; 2153 } 2154 2155 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state, 2156 struct drm_display_mode *mode) 2157 { 2158 int overlap = crtc_state->splitter.pixel_overlap; 2159 int n = crtc_state->splitter.link_count; 2160 2161 if (!crtc_state->splitter.enable) 2162 return; 2163 2164 /* 2165 * eDP MSO uses segment timings from EDID for transcoder 2166 * timings, but full mode for everything else. 2167 * 2168 * h_full = (h_segment - pixel_overlap) * link_count 2169 */ 2170 mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n; 2171 mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n; 2172 mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n; 2173 mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n; 2174 mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n; 2175 mode->crtc_htotal = (mode->crtc_htotal - overlap) * n; 2176 mode->crtc_clock *= n; 2177 } 2178 2179 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state) 2180 { 2181 struct drm_display_mode *mode = &crtc_state->hw.mode; 2182 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2183 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2184 2185 /* 2186 * Start with the adjusted_mode crtc timings, which 2187 * have been filled with the transcoder timings. 2188 */ 2189 drm_mode_copy(pipe_mode, adjusted_mode); 2190 2191 /* Expand MSO per-segment transcoder timings to full */ 2192 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2193 2194 /* 2195 * We want the full numbers in adjusted_mode normal timings, 2196 * adjusted_mode crtc timings are left with the raw transcoder 2197 * timings. 2198 */ 2199 intel_mode_from_crtc_timings(adjusted_mode, pipe_mode); 2200 2201 /* Populate the "user" mode with full numbers */ 2202 drm_mode_copy(mode, pipe_mode); 2203 intel_mode_from_crtc_timings(mode, mode); 2204 mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) * 2205 (intel_bigjoiner_num_pipes(crtc_state) ?: 1); 2206 mode->vdisplay = drm_rect_height(&crtc_state->pipe_src); 2207 2208 /* Derive per-pipe timings in case bigjoiner is used */ 2209 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2210 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2211 2212 intel_crtc_compute_pixel_rate(crtc_state); 2213 } 2214 2215 void intel_encoder_get_config(struct intel_encoder *encoder, 2216 struct intel_crtc_state *crtc_state) 2217 { 2218 encoder->get_config(encoder, crtc_state); 2219 2220 intel_crtc_readout_derived_state(crtc_state); 2221 } 2222 2223 static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state *crtc_state) 2224 { 2225 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2226 int width, height; 2227 2228 if (num_pipes < 2) 2229 return; 2230 2231 width = drm_rect_width(&crtc_state->pipe_src); 2232 height = drm_rect_height(&crtc_state->pipe_src); 2233 2234 drm_rect_init(&crtc_state->pipe_src, 0, 0, 2235 width / num_pipes, height); 2236 } 2237 2238 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state) 2239 { 2240 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2241 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2242 2243 intel_bigjoiner_compute_pipe_src(crtc_state); 2244 2245 /* 2246 * Pipe horizontal size must be even in: 2247 * - DVO ganged mode 2248 * - LVDS dual channel mode 2249 * - Double wide pipe 2250 */ 2251 if (drm_rect_width(&crtc_state->pipe_src) & 1) { 2252 if (crtc_state->double_wide) { 2253 drm_dbg_kms(&i915->drm, 2254 "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n", 2255 crtc->base.base.id, crtc->base.name); 2256 return -EINVAL; 2257 } 2258 2259 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 2260 intel_is_dual_link_lvds(i915)) { 2261 drm_dbg_kms(&i915->drm, 2262 "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n", 2263 crtc->base.base.id, crtc->base.name); 2264 return -EINVAL; 2265 } 2266 } 2267 2268 return 0; 2269 } 2270 2271 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state) 2272 { 2273 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2274 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2275 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2276 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2277 int clock_limit = i915->max_dotclk_freq; 2278 2279 /* 2280 * Start with the adjusted_mode crtc timings, which 2281 * have been filled with the transcoder timings. 2282 */ 2283 drm_mode_copy(pipe_mode, adjusted_mode); 2284 2285 /* Expand MSO per-segment transcoder timings to full */ 2286 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2287 2288 /* Derive per-pipe timings in case bigjoiner is used */ 2289 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2290 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2291 2292 if (DISPLAY_VER(i915) < 4) { 2293 clock_limit = i915->display.cdclk.max_cdclk_freq * 9 / 10; 2294 2295 /* 2296 * Enable double wide mode when the dot clock 2297 * is > 90% of the (display) core speed. 2298 */ 2299 if (intel_crtc_supports_double_wide(crtc) && 2300 pipe_mode->crtc_clock > clock_limit) { 2301 clock_limit = i915->max_dotclk_freq; 2302 crtc_state->double_wide = true; 2303 } 2304 } 2305 2306 if (pipe_mode->crtc_clock > clock_limit) { 2307 drm_dbg_kms(&i915->drm, 2308 "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", 2309 crtc->base.base.id, crtc->base.name, 2310 pipe_mode->crtc_clock, clock_limit, 2311 str_yes_no(crtc_state->double_wide)); 2312 return -EINVAL; 2313 } 2314 2315 return 0; 2316 } 2317 2318 static int intel_crtc_compute_config(struct intel_atomic_state *state, 2319 struct intel_crtc *crtc) 2320 { 2321 struct intel_crtc_state *crtc_state = 2322 intel_atomic_get_new_crtc_state(state, crtc); 2323 int ret; 2324 2325 ret = intel_dpll_crtc_compute_clock(state, crtc); 2326 if (ret) 2327 return ret; 2328 2329 ret = intel_crtc_compute_pipe_src(crtc_state); 2330 if (ret) 2331 return ret; 2332 2333 ret = intel_crtc_compute_pipe_mode(crtc_state); 2334 if (ret) 2335 return ret; 2336 2337 intel_crtc_compute_pixel_rate(crtc_state); 2338 2339 if (crtc_state->has_pch_encoder) 2340 return ilk_fdi_compute_config(crtc, crtc_state); 2341 2342 return 0; 2343 } 2344 2345 static void 2346 intel_reduce_m_n_ratio(u32 *num, u32 *den) 2347 { 2348 while (*num > DATA_LINK_M_N_MASK || 2349 *den > DATA_LINK_M_N_MASK) { 2350 *num >>= 1; 2351 *den >>= 1; 2352 } 2353 } 2354 2355 static void compute_m_n(u32 *ret_m, u32 *ret_n, 2356 u32 m, u32 n, u32 constant_n) 2357 { 2358 if (constant_n) 2359 *ret_n = constant_n; 2360 else 2361 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); 2362 2363 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n); 2364 intel_reduce_m_n_ratio(ret_m, ret_n); 2365 } 2366 2367 void 2368 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes, 2369 int pixel_clock, int link_clock, 2370 struct intel_link_m_n *m_n, 2371 bool fec_enable) 2372 { 2373 u32 data_clock = bits_per_pixel * pixel_clock; 2374 2375 if (fec_enable) 2376 data_clock = intel_dp_mode_to_fec_clock(data_clock); 2377 2378 /* 2379 * Windows/BIOS uses fixed M/N values always. Follow suit. 2380 * 2381 * Also several DP dongles in particular seem to be fussy 2382 * about too large link M/N values. Presumably the 20bit 2383 * value used by Windows/BIOS is acceptable to everyone. 2384 */ 2385 m_n->tu = 64; 2386 compute_m_n(&m_n->data_m, &m_n->data_n, 2387 data_clock, link_clock * nlanes * 8, 2388 0x8000000); 2389 2390 compute_m_n(&m_n->link_m, &m_n->link_n, 2391 pixel_clock, link_clock, 2392 0x80000); 2393 } 2394 2395 void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv) 2396 { 2397 /* 2398 * There may be no VBT; and if the BIOS enabled SSC we can 2399 * just keep using it to avoid unnecessary flicker. Whereas if the 2400 * BIOS isn't using it, don't assume it will work even if the VBT 2401 * indicates as much. 2402 */ 2403 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { 2404 bool bios_lvds_use_ssc = intel_de_read(dev_priv, 2405 PCH_DREF_CONTROL) & 2406 DREF_SSC1_ENABLE; 2407 2408 if (dev_priv->display.vbt.lvds_use_ssc != bios_lvds_use_ssc) { 2409 drm_dbg_kms(&dev_priv->drm, 2410 "SSC %s by BIOS, overriding VBT which says %s\n", 2411 str_enabled_disabled(bios_lvds_use_ssc), 2412 str_enabled_disabled(dev_priv->display.vbt.lvds_use_ssc)); 2413 dev_priv->display.vbt.lvds_use_ssc = bios_lvds_use_ssc; 2414 } 2415 } 2416 } 2417 2418 void intel_zero_m_n(struct intel_link_m_n *m_n) 2419 { 2420 /* corresponds to 0 register value */ 2421 memset(m_n, 0, sizeof(*m_n)); 2422 m_n->tu = 1; 2423 } 2424 2425 void intel_set_m_n(struct drm_i915_private *i915, 2426 const struct intel_link_m_n *m_n, 2427 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 2428 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 2429 { 2430 intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); 2431 intel_de_write(i915, data_n_reg, m_n->data_n); 2432 intel_de_write(i915, link_m_reg, m_n->link_m); 2433 /* 2434 * On BDW+ writing LINK_N arms the double buffered update 2435 * of all the M/N registers, so it must be written last. 2436 */ 2437 intel_de_write(i915, link_n_reg, m_n->link_n); 2438 } 2439 2440 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, 2441 enum transcoder transcoder) 2442 { 2443 if (IS_HASWELL(dev_priv)) 2444 return transcoder == TRANSCODER_EDP; 2445 2446 return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv); 2447 } 2448 2449 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, 2450 enum transcoder transcoder, 2451 const struct intel_link_m_n *m_n) 2452 { 2453 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2454 enum pipe pipe = crtc->pipe; 2455 2456 if (DISPLAY_VER(dev_priv) >= 5) 2457 intel_set_m_n(dev_priv, m_n, 2458 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 2459 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 2460 else 2461 intel_set_m_n(dev_priv, m_n, 2462 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 2463 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 2464 } 2465 2466 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, 2467 enum transcoder transcoder, 2468 const struct intel_link_m_n *m_n) 2469 { 2470 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2471 2472 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 2473 return; 2474 2475 intel_set_m_n(dev_priv, m_n, 2476 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 2477 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 2478 } 2479 2480 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) 2481 { 2482 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2483 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2484 enum pipe pipe = crtc->pipe; 2485 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2486 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2487 u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end; 2488 int vsyncshift = 0; 2489 2490 /* We need to be careful not to changed the adjusted mode, for otherwise 2491 * the hw state checker will get angry at the mismatch. */ 2492 crtc_vdisplay = adjusted_mode->crtc_vdisplay; 2493 crtc_vtotal = adjusted_mode->crtc_vtotal; 2494 crtc_vblank_start = adjusted_mode->crtc_vblank_start; 2495 crtc_vblank_end = adjusted_mode->crtc_vblank_end; 2496 2497 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 2498 /* the chip adds 2 halflines automatically */ 2499 crtc_vtotal -= 1; 2500 crtc_vblank_end -= 1; 2501 2502 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 2503 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; 2504 else 2505 vsyncshift = adjusted_mode->crtc_hsync_start - 2506 adjusted_mode->crtc_htotal / 2; 2507 if (vsyncshift < 0) 2508 vsyncshift += adjusted_mode->crtc_htotal; 2509 } 2510 2511 /* 2512 * VBLANK_START no longer works on ADL+, instead we must use 2513 * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start. 2514 */ 2515 if (DISPLAY_VER(dev_priv) >= 13) { 2516 intel_de_write(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder), 2517 crtc_vblank_start - crtc_vdisplay); 2518 2519 /* 2520 * VBLANK_START not used by hw, just clear it 2521 * to make it stand out in register dumps. 2522 */ 2523 crtc_vblank_start = 1; 2524 } 2525 2526 if (DISPLAY_VER(dev_priv) > 3) 2527 intel_de_write(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder), 2528 vsyncshift); 2529 2530 intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder), 2531 HACTIVE(adjusted_mode->crtc_hdisplay - 1) | 2532 HTOTAL(adjusted_mode->crtc_htotal - 1)); 2533 intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder), 2534 HBLANK_START(adjusted_mode->crtc_hblank_start - 1) | 2535 HBLANK_END(adjusted_mode->crtc_hblank_end - 1)); 2536 intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder), 2537 HSYNC_START(adjusted_mode->crtc_hsync_start - 1) | 2538 HSYNC_END(adjusted_mode->crtc_hsync_end - 1)); 2539 2540 intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder), 2541 VACTIVE(crtc_vdisplay - 1) | 2542 VTOTAL(crtc_vtotal - 1)); 2543 intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), 2544 VBLANK_START(crtc_vblank_start - 1) | 2545 VBLANK_END(crtc_vblank_end - 1)); 2546 intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder), 2547 VSYNC_START(adjusted_mode->crtc_vsync_start - 1) | 2548 VSYNC_END(adjusted_mode->crtc_vsync_end - 1)); 2549 2550 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be 2551 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is 2552 * documented on the DDI_FUNC_CTL register description, EDP Input Select 2553 * bits. */ 2554 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && 2555 (pipe == PIPE_B || pipe == PIPE_C)) 2556 intel_de_write(dev_priv, TRANS_VTOTAL(pipe), 2557 VACTIVE(crtc_vdisplay - 1) | 2558 VTOTAL(crtc_vtotal - 1)); 2559 } 2560 2561 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) 2562 { 2563 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2564 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2565 int width = drm_rect_width(&crtc_state->pipe_src); 2566 int height = drm_rect_height(&crtc_state->pipe_src); 2567 enum pipe pipe = crtc->pipe; 2568 2569 /* pipesrc controls the size that is scaled from, which should 2570 * always be the user's requested size. 2571 */ 2572 intel_de_write(dev_priv, PIPESRC(pipe), 2573 PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1)); 2574 } 2575 2576 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) 2577 { 2578 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2579 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2580 2581 if (DISPLAY_VER(dev_priv) == 2) 2582 return false; 2583 2584 if (DISPLAY_VER(dev_priv) >= 9 || 2585 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2586 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW; 2587 else 2588 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK; 2589 } 2590 2591 static void intel_get_transcoder_timings(struct intel_crtc *crtc, 2592 struct intel_crtc_state *pipe_config) 2593 { 2594 struct drm_device *dev = crtc->base.dev; 2595 struct drm_i915_private *dev_priv = to_i915(dev); 2596 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 2597 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2598 u32 tmp; 2599 2600 tmp = intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder)); 2601 adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1; 2602 adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1; 2603 2604 if (!transcoder_is_dsi(cpu_transcoder)) { 2605 tmp = intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder)); 2606 adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1; 2607 adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1; 2608 } 2609 2610 tmp = intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder)); 2611 adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1; 2612 adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1; 2613 2614 tmp = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder)); 2615 adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1; 2616 adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1; 2617 2618 /* FIXME TGL+ DSI transcoders have this! */ 2619 if (!transcoder_is_dsi(cpu_transcoder)) { 2620 tmp = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder)); 2621 adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1; 2622 adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1; 2623 } 2624 tmp = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder)); 2625 adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1; 2626 adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1; 2627 2628 if (intel_pipe_is_interlaced(pipe_config)) { 2629 adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE; 2630 adjusted_mode->crtc_vtotal += 1; 2631 adjusted_mode->crtc_vblank_end += 1; 2632 } 2633 2634 if (DISPLAY_VER(dev_priv) >= 13 && !transcoder_is_dsi(cpu_transcoder)) 2635 adjusted_mode->crtc_vblank_start = 2636 adjusted_mode->crtc_vdisplay + 2637 intel_de_read(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder)); 2638 } 2639 2640 static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state) 2641 { 2642 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2643 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2644 enum pipe master_pipe, pipe = crtc->pipe; 2645 int width; 2646 2647 if (num_pipes < 2) 2648 return; 2649 2650 master_pipe = bigjoiner_master_pipe(crtc_state); 2651 width = drm_rect_width(&crtc_state->pipe_src); 2652 2653 drm_rect_translate_to(&crtc_state->pipe_src, 2654 (pipe - master_pipe) * width, 0); 2655 } 2656 2657 static void intel_get_pipe_src_size(struct intel_crtc *crtc, 2658 struct intel_crtc_state *pipe_config) 2659 { 2660 struct drm_device *dev = crtc->base.dev; 2661 struct drm_i915_private *dev_priv = to_i915(dev); 2662 u32 tmp; 2663 2664 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe)); 2665 2666 drm_rect_init(&pipe_config->pipe_src, 0, 0, 2667 REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1, 2668 REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1); 2669 2670 intel_bigjoiner_adjust_pipe_src(pipe_config); 2671 } 2672 2673 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) 2674 { 2675 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2676 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2677 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2678 u32 val = 0; 2679 2680 /* 2681 * - We keep both pipes enabled on 830 2682 * - During modeset the pipe is still disabled and must remain so 2683 * - During fastset the pipe is already enabled and must remain so 2684 */ 2685 if (IS_I830(dev_priv) || !intel_crtc_needs_modeset(crtc_state)) 2686 val |= TRANSCONF_ENABLE; 2687 2688 if (crtc_state->double_wide) 2689 val |= TRANSCONF_DOUBLE_WIDE; 2690 2691 /* only g4x and later have fancy bpc/dither controls */ 2692 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 2693 IS_CHERRYVIEW(dev_priv)) { 2694 /* Bspec claims that we can't use dithering for 30bpp pipes. */ 2695 if (crtc_state->dither && crtc_state->pipe_bpp != 30) 2696 val |= TRANSCONF_DITHER_EN | 2697 TRANSCONF_DITHER_TYPE_SP; 2698 2699 switch (crtc_state->pipe_bpp) { 2700 default: 2701 /* Case prevented by intel_choose_pipe_bpp_dither. */ 2702 MISSING_CASE(crtc_state->pipe_bpp); 2703 fallthrough; 2704 case 18: 2705 val |= TRANSCONF_BPC_6; 2706 break; 2707 case 24: 2708 val |= TRANSCONF_BPC_8; 2709 break; 2710 case 30: 2711 val |= TRANSCONF_BPC_10; 2712 break; 2713 } 2714 } 2715 2716 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 2717 if (DISPLAY_VER(dev_priv) < 4 || 2718 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 2719 val |= TRANSCONF_INTERLACE_W_FIELD_INDICATION; 2720 else 2721 val |= TRANSCONF_INTERLACE_W_SYNC_SHIFT; 2722 } else { 2723 val |= TRANSCONF_INTERLACE_PROGRESSIVE; 2724 } 2725 2726 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 2727 crtc_state->limited_color_range) 2728 val |= TRANSCONF_COLOR_RANGE_SELECT; 2729 2730 val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode); 2731 2732 val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 2733 2734 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); 2735 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); 2736 } 2737 2738 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv) 2739 { 2740 if (IS_I830(dev_priv)) 2741 return false; 2742 2743 return DISPLAY_VER(dev_priv) >= 4 || 2744 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); 2745 } 2746 2747 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state) 2748 { 2749 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2750 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2751 enum pipe pipe; 2752 u32 tmp; 2753 2754 if (!i9xx_has_pfit(dev_priv)) 2755 return; 2756 2757 tmp = intel_de_read(dev_priv, PFIT_CONTROL); 2758 if (!(tmp & PFIT_ENABLE)) 2759 return; 2760 2761 /* Check whether the pfit is attached to our pipe. */ 2762 if (DISPLAY_VER(dev_priv) >= 4) 2763 pipe = REG_FIELD_GET(PFIT_PIPE_MASK, tmp); 2764 else 2765 pipe = PIPE_B; 2766 2767 if (pipe != crtc->pipe) 2768 return; 2769 2770 crtc_state->gmch_pfit.control = tmp; 2771 crtc_state->gmch_pfit.pgm_ratios = 2772 intel_de_read(dev_priv, PFIT_PGM_RATIOS); 2773 } 2774 2775 static void vlv_crtc_clock_get(struct intel_crtc *crtc, 2776 struct intel_crtc_state *pipe_config) 2777 { 2778 struct drm_device *dev = crtc->base.dev; 2779 struct drm_i915_private *dev_priv = to_i915(dev); 2780 enum pipe pipe = crtc->pipe; 2781 struct dpll clock; 2782 u32 mdiv; 2783 int refclk = 100000; 2784 2785 /* In case of DSI, DPLL will not be used */ 2786 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 2787 return; 2788 2789 vlv_dpio_get(dev_priv); 2790 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); 2791 vlv_dpio_put(dev_priv); 2792 2793 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; 2794 clock.m2 = mdiv & DPIO_M2DIV_MASK; 2795 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; 2796 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; 2797 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; 2798 2799 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); 2800 } 2801 2802 static void chv_crtc_clock_get(struct intel_crtc *crtc, 2803 struct intel_crtc_state *pipe_config) 2804 { 2805 struct drm_device *dev = crtc->base.dev; 2806 struct drm_i915_private *dev_priv = to_i915(dev); 2807 enum pipe pipe = crtc->pipe; 2808 enum dpio_channel port = vlv_pipe_to_channel(pipe); 2809 struct dpll clock; 2810 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; 2811 int refclk = 100000; 2812 2813 /* In case of DSI, DPLL will not be used */ 2814 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 2815 return; 2816 2817 vlv_dpio_get(dev_priv); 2818 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); 2819 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); 2820 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); 2821 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); 2822 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); 2823 vlv_dpio_put(dev_priv); 2824 2825 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; 2826 clock.m2 = (pll_dw0 & 0xff) << 22; 2827 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) 2828 clock.m2 |= pll_dw2 & 0x3fffff; 2829 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; 2830 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; 2831 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; 2832 2833 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); 2834 } 2835 2836 static enum intel_output_format 2837 bdw_get_pipe_misc_output_format(struct intel_crtc *crtc) 2838 { 2839 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2840 u32 tmp; 2841 2842 tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe)); 2843 2844 if (tmp & PIPE_MISC_YUV420_ENABLE) { 2845 /* We support 4:2:0 in full blend mode only */ 2846 drm_WARN_ON(&dev_priv->drm, 2847 (tmp & PIPE_MISC_YUV420_MODE_FULL_BLEND) == 0); 2848 2849 return INTEL_OUTPUT_FORMAT_YCBCR420; 2850 } else if (tmp & PIPE_MISC_OUTPUT_COLORSPACE_YUV) { 2851 return INTEL_OUTPUT_FORMAT_YCBCR444; 2852 } else { 2853 return INTEL_OUTPUT_FORMAT_RGB; 2854 } 2855 } 2856 2857 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state) 2858 { 2859 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2860 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 2861 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2862 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 2863 u32 tmp; 2864 2865 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); 2866 2867 if (tmp & DISP_PIPE_GAMMA_ENABLE) 2868 crtc_state->gamma_enable = true; 2869 2870 if (!HAS_GMCH(dev_priv) && 2871 tmp & DISP_PIPE_CSC_ENABLE) 2872 crtc_state->csc_enable = true; 2873 } 2874 2875 static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 2876 struct intel_crtc_state *pipe_config) 2877 { 2878 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2879 enum intel_display_power_domain power_domain; 2880 intel_wakeref_t wakeref; 2881 u32 tmp; 2882 bool ret; 2883 2884 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 2885 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 2886 if (!wakeref) 2887 return false; 2888 2889 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 2890 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 2891 pipe_config->shared_dpll = NULL; 2892 2893 ret = false; 2894 2895 tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder)); 2896 if (!(tmp & TRANSCONF_ENABLE)) 2897 goto out; 2898 2899 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 2900 IS_CHERRYVIEW(dev_priv)) { 2901 switch (tmp & TRANSCONF_BPC_MASK) { 2902 case TRANSCONF_BPC_6: 2903 pipe_config->pipe_bpp = 18; 2904 break; 2905 case TRANSCONF_BPC_8: 2906 pipe_config->pipe_bpp = 24; 2907 break; 2908 case TRANSCONF_BPC_10: 2909 pipe_config->pipe_bpp = 30; 2910 break; 2911 default: 2912 MISSING_CASE(tmp); 2913 break; 2914 } 2915 } 2916 2917 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 2918 (tmp & TRANSCONF_COLOR_RANGE_SELECT)) 2919 pipe_config->limited_color_range = true; 2920 2921 pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp); 2922 2923 pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1; 2924 2925 if (IS_CHERRYVIEW(dev_priv)) 2926 pipe_config->cgm_mode = intel_de_read(dev_priv, 2927 CGM_PIPE_MODE(crtc->pipe)); 2928 2929 i9xx_get_pipe_color_config(pipe_config); 2930 intel_color_get_config(pipe_config); 2931 2932 if (DISPLAY_VER(dev_priv) < 4) 2933 pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE; 2934 2935 intel_get_transcoder_timings(crtc, pipe_config); 2936 intel_get_pipe_src_size(crtc, pipe_config); 2937 2938 i9xx_get_pfit_config(pipe_config); 2939 2940 if (DISPLAY_VER(dev_priv) >= 4) { 2941 /* No way to read it out on pipes B and C */ 2942 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) 2943 tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe]; 2944 else 2945 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe)); 2946 pipe_config->pixel_multiplier = 2947 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) 2948 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; 2949 pipe_config->dpll_hw_state.dpll_md = tmp; 2950 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 2951 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 2952 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe)); 2953 pipe_config->pixel_multiplier = 2954 ((tmp & SDVO_MULTIPLIER_MASK) 2955 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; 2956 } else { 2957 /* Note that on i915G/GM the pixel multiplier is in the sdvo 2958 * port and will be fixed up in the encoder->get_config 2959 * function. */ 2960 pipe_config->pixel_multiplier = 1; 2961 } 2962 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv, 2963 DPLL(crtc->pipe)); 2964 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 2965 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv, 2966 FP0(crtc->pipe)); 2967 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv, 2968 FP1(crtc->pipe)); 2969 } else { 2970 /* Mask out read-only status bits. */ 2971 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | 2972 DPLL_PORTC_READY_MASK | 2973 DPLL_PORTB_READY_MASK); 2974 } 2975 2976 if (IS_CHERRYVIEW(dev_priv)) 2977 chv_crtc_clock_get(crtc, pipe_config); 2978 else if (IS_VALLEYVIEW(dev_priv)) 2979 vlv_crtc_clock_get(crtc, pipe_config); 2980 else 2981 i9xx_crtc_clock_get(crtc, pipe_config); 2982 2983 /* 2984 * Normally the dotclock is filled in by the encoder .get_config() 2985 * but in case the pipe is enabled w/o any ports we need a sane 2986 * default. 2987 */ 2988 pipe_config->hw.adjusted_mode.crtc_clock = 2989 pipe_config->port_clock / pipe_config->pixel_multiplier; 2990 2991 ret = true; 2992 2993 out: 2994 intel_display_power_put(dev_priv, power_domain, wakeref); 2995 2996 return ret; 2997 } 2998 2999 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) 3000 { 3001 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3002 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3003 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3004 u32 val = 0; 3005 3006 /* 3007 * - During modeset the pipe is still disabled and must remain so 3008 * - During fastset the pipe is already enabled and must remain so 3009 */ 3010 if (!intel_crtc_needs_modeset(crtc_state)) 3011 val |= TRANSCONF_ENABLE; 3012 3013 switch (crtc_state->pipe_bpp) { 3014 default: 3015 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3016 MISSING_CASE(crtc_state->pipe_bpp); 3017 fallthrough; 3018 case 18: 3019 val |= TRANSCONF_BPC_6; 3020 break; 3021 case 24: 3022 val |= TRANSCONF_BPC_8; 3023 break; 3024 case 30: 3025 val |= TRANSCONF_BPC_10; 3026 break; 3027 case 36: 3028 val |= TRANSCONF_BPC_12; 3029 break; 3030 } 3031 3032 if (crtc_state->dither) 3033 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP; 3034 3035 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3036 val |= TRANSCONF_INTERLACE_IF_ID_ILK; 3037 else 3038 val |= TRANSCONF_INTERLACE_PF_PD_ILK; 3039 3040 /* 3041 * This would end up with an odd purple hue over 3042 * the entire display. Make sure we don't do it. 3043 */ 3044 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 3045 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 3046 3047 if (crtc_state->limited_color_range && 3048 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3049 val |= TRANSCONF_COLOR_RANGE_SELECT; 3050 3051 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3052 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV709; 3053 3054 val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode); 3055 3056 val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3057 val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay); 3058 3059 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); 3060 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); 3061 } 3062 3063 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) 3064 { 3065 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3066 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3067 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3068 u32 val = 0; 3069 3070 /* 3071 * - During modeset the pipe is still disabled and must remain so 3072 * - During fastset the pipe is already enabled and must remain so 3073 */ 3074 if (!intel_crtc_needs_modeset(crtc_state)) 3075 val |= TRANSCONF_ENABLE; 3076 3077 if (IS_HASWELL(dev_priv) && crtc_state->dither) 3078 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP; 3079 3080 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3081 val |= TRANSCONF_INTERLACE_IF_ID_ILK; 3082 else 3083 val |= TRANSCONF_INTERLACE_PF_PD_ILK; 3084 3085 if (IS_HASWELL(dev_priv) && 3086 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3087 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW; 3088 3089 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); 3090 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); 3091 } 3092 3093 static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state) 3094 { 3095 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3096 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3097 u32 val = 0; 3098 3099 switch (crtc_state->pipe_bpp) { 3100 case 18: 3101 val |= PIPE_MISC_BPC_6; 3102 break; 3103 case 24: 3104 val |= PIPE_MISC_BPC_8; 3105 break; 3106 case 30: 3107 val |= PIPE_MISC_BPC_10; 3108 break; 3109 case 36: 3110 /* Port output 12BPC defined for ADLP+ */ 3111 if (DISPLAY_VER(dev_priv) > 12) 3112 val |= PIPE_MISC_BPC_12_ADLP; 3113 break; 3114 default: 3115 MISSING_CASE(crtc_state->pipe_bpp); 3116 break; 3117 } 3118 3119 if (crtc_state->dither) 3120 val |= PIPE_MISC_DITHER_ENABLE | PIPE_MISC_DITHER_TYPE_SP; 3121 3122 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 3123 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 3124 val |= PIPE_MISC_OUTPUT_COLORSPACE_YUV; 3125 3126 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 3127 val |= PIPE_MISC_YUV420_ENABLE | 3128 PIPE_MISC_YUV420_MODE_FULL_BLEND; 3129 3130 if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state)) 3131 val |= PIPE_MISC_HDR_MODE_PRECISION; 3132 3133 if (DISPLAY_VER(dev_priv) >= 12) 3134 val |= PIPE_MISC_PIXEL_ROUNDING_TRUNC; 3135 3136 intel_de_write(dev_priv, PIPE_MISC(crtc->pipe), val); 3137 } 3138 3139 int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc) 3140 { 3141 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3142 u32 tmp; 3143 3144 tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe)); 3145 3146 switch (tmp & PIPE_MISC_BPC_MASK) { 3147 case PIPE_MISC_BPC_6: 3148 return 18; 3149 case PIPE_MISC_BPC_8: 3150 return 24; 3151 case PIPE_MISC_BPC_10: 3152 return 30; 3153 /* 3154 * PORT OUTPUT 12 BPC defined for ADLP+. 3155 * 3156 * TODO: 3157 * For previous platforms with DSI interface, bits 5:7 3158 * are used for storing pipe_bpp irrespective of dithering. 3159 * Since the value of 12 BPC is not defined for these bits 3160 * on older platforms, need to find a workaround for 12 BPC 3161 * MIPI DSI HW readout. 3162 */ 3163 case PIPE_MISC_BPC_12_ADLP: 3164 if (DISPLAY_VER(dev_priv) > 12) 3165 return 36; 3166 fallthrough; 3167 default: 3168 MISSING_CASE(tmp); 3169 return 0; 3170 } 3171 } 3172 3173 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) 3174 { 3175 /* 3176 * Account for spread spectrum to avoid 3177 * oversubscribing the link. Max center spread 3178 * is 2.5%; use 5% for safety's sake. 3179 */ 3180 u32 bps = target_clock * bpp * 21 / 20; 3181 return DIV_ROUND_UP(bps, link_bw * 8); 3182 } 3183 3184 void intel_get_m_n(struct drm_i915_private *i915, 3185 struct intel_link_m_n *m_n, 3186 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 3187 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 3188 { 3189 m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK; 3190 m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK; 3191 m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK; 3192 m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK; 3193 m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1; 3194 } 3195 3196 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, 3197 enum transcoder transcoder, 3198 struct intel_link_m_n *m_n) 3199 { 3200 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3201 enum pipe pipe = crtc->pipe; 3202 3203 if (DISPLAY_VER(dev_priv) >= 5) 3204 intel_get_m_n(dev_priv, m_n, 3205 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 3206 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 3207 else 3208 intel_get_m_n(dev_priv, m_n, 3209 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 3210 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 3211 } 3212 3213 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, 3214 enum transcoder transcoder, 3215 struct intel_link_m_n *m_n) 3216 { 3217 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3218 3219 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 3220 return; 3221 3222 intel_get_m_n(dev_priv, m_n, 3223 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 3224 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 3225 } 3226 3227 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state) 3228 { 3229 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3230 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3231 u32 ctl, pos, size; 3232 enum pipe pipe; 3233 3234 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe)); 3235 if ((ctl & PF_ENABLE) == 0) 3236 return; 3237 3238 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) 3239 pipe = REG_FIELD_GET(PF_PIPE_SEL_MASK_IVB, ctl); 3240 else 3241 pipe = crtc->pipe; 3242 3243 crtc_state->pch_pfit.enabled = true; 3244 3245 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe)); 3246 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe)); 3247 3248 drm_rect_init(&crtc_state->pch_pfit.dst, 3249 pos >> 16, pos & 0xffff, 3250 size >> 16, size & 0xffff); 3251 3252 /* 3253 * We currently do not free assignements of panel fitters on 3254 * ivb/hsw (since we don't use the higher upscaling modes which 3255 * differentiates them) so just WARN about this case for now. 3256 */ 3257 drm_WARN_ON(&dev_priv->drm, pipe != crtc->pipe); 3258 } 3259 3260 static bool ilk_get_pipe_config(struct intel_crtc *crtc, 3261 struct intel_crtc_state *pipe_config) 3262 { 3263 struct drm_device *dev = crtc->base.dev; 3264 struct drm_i915_private *dev_priv = to_i915(dev); 3265 enum intel_display_power_domain power_domain; 3266 intel_wakeref_t wakeref; 3267 u32 tmp; 3268 bool ret; 3269 3270 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3271 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3272 if (!wakeref) 3273 return false; 3274 3275 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3276 pipe_config->shared_dpll = NULL; 3277 3278 ret = false; 3279 tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder)); 3280 if (!(tmp & TRANSCONF_ENABLE)) 3281 goto out; 3282 3283 switch (tmp & TRANSCONF_BPC_MASK) { 3284 case TRANSCONF_BPC_6: 3285 pipe_config->pipe_bpp = 18; 3286 break; 3287 case TRANSCONF_BPC_8: 3288 pipe_config->pipe_bpp = 24; 3289 break; 3290 case TRANSCONF_BPC_10: 3291 pipe_config->pipe_bpp = 30; 3292 break; 3293 case TRANSCONF_BPC_12: 3294 pipe_config->pipe_bpp = 36; 3295 break; 3296 default: 3297 break; 3298 } 3299 3300 if (tmp & TRANSCONF_COLOR_RANGE_SELECT) 3301 pipe_config->limited_color_range = true; 3302 3303 switch (tmp & TRANSCONF_OUTPUT_COLORSPACE_MASK) { 3304 case TRANSCONF_OUTPUT_COLORSPACE_YUV601: 3305 case TRANSCONF_OUTPUT_COLORSPACE_YUV709: 3306 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3307 break; 3308 default: 3309 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3310 break; 3311 } 3312 3313 pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp); 3314 3315 pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1; 3316 3317 pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp); 3318 3319 pipe_config->csc_mode = intel_de_read(dev_priv, 3320 PIPE_CSC_MODE(crtc->pipe)); 3321 3322 i9xx_get_pipe_color_config(pipe_config); 3323 intel_color_get_config(pipe_config); 3324 3325 pipe_config->pixel_multiplier = 1; 3326 3327 ilk_pch_get_config(pipe_config); 3328 3329 intel_get_transcoder_timings(crtc, pipe_config); 3330 intel_get_pipe_src_size(crtc, pipe_config); 3331 3332 ilk_get_pfit_config(pipe_config); 3333 3334 ret = true; 3335 3336 out: 3337 intel_display_power_put(dev_priv, power_domain, wakeref); 3338 3339 return ret; 3340 } 3341 3342 static u8 bigjoiner_pipes(struct drm_i915_private *i915) 3343 { 3344 u8 pipes; 3345 3346 if (DISPLAY_VER(i915) >= 12) 3347 pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D); 3348 else if (DISPLAY_VER(i915) >= 11) 3349 pipes = BIT(PIPE_B) | BIT(PIPE_C); 3350 else 3351 pipes = 0; 3352 3353 return pipes & RUNTIME_INFO(i915)->pipe_mask; 3354 } 3355 3356 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv, 3357 enum transcoder cpu_transcoder) 3358 { 3359 enum intel_display_power_domain power_domain; 3360 intel_wakeref_t wakeref; 3361 u32 tmp = 0; 3362 3363 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3364 3365 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3366 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3367 3368 return tmp & TRANS_DDI_FUNC_ENABLE; 3369 } 3370 3371 static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv, 3372 u8 *master_pipes, u8 *slave_pipes) 3373 { 3374 struct intel_crtc *crtc; 3375 3376 *master_pipes = 0; 3377 *slave_pipes = 0; 3378 3379 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, 3380 bigjoiner_pipes(dev_priv)) { 3381 enum intel_display_power_domain power_domain; 3382 enum pipe pipe = crtc->pipe; 3383 intel_wakeref_t wakeref; 3384 3385 power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe); 3386 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3387 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3388 3389 if (!(tmp & BIG_JOINER_ENABLE)) 3390 continue; 3391 3392 if (tmp & MASTER_BIG_JOINER_ENABLE) 3393 *master_pipes |= BIT(pipe); 3394 else 3395 *slave_pipes |= BIT(pipe); 3396 } 3397 3398 if (DISPLAY_VER(dev_priv) < 13) 3399 continue; 3400 3401 power_domain = POWER_DOMAIN_PIPE(pipe); 3402 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3403 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3404 3405 if (tmp & UNCOMPRESSED_JOINER_MASTER) 3406 *master_pipes |= BIT(pipe); 3407 if (tmp & UNCOMPRESSED_JOINER_SLAVE) 3408 *slave_pipes |= BIT(pipe); 3409 } 3410 } 3411 3412 /* Bigjoiner pipes should always be consecutive master and slave */ 3413 drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1, 3414 "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n", 3415 *master_pipes, *slave_pipes); 3416 } 3417 3418 static enum pipe get_bigjoiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3419 { 3420 if ((slave_pipes & BIT(pipe)) == 0) 3421 return pipe; 3422 3423 /* ignore everything above our pipe */ 3424 master_pipes &= ~GENMASK(7, pipe); 3425 3426 /* highest remaining bit should be our master pipe */ 3427 return fls(master_pipes) - 1; 3428 } 3429 3430 static u8 get_bigjoiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3431 { 3432 enum pipe master_pipe, next_master_pipe; 3433 3434 master_pipe = get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes); 3435 3436 if ((master_pipes & BIT(master_pipe)) == 0) 3437 return 0; 3438 3439 /* ignore our master pipe and everything below it */ 3440 master_pipes &= ~GENMASK(master_pipe, 0); 3441 /* make sure a high bit is set for the ffs() */ 3442 master_pipes |= BIT(7); 3443 /* lowest remaining bit should be the next master pipe */ 3444 next_master_pipe = ffs(master_pipes) - 1; 3445 3446 return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe); 3447 } 3448 3449 static u8 hsw_panel_transcoders(struct drm_i915_private *i915) 3450 { 3451 u8 panel_transcoder_mask = BIT(TRANSCODER_EDP); 3452 3453 if (DISPLAY_VER(i915) >= 11) 3454 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); 3455 3456 return panel_transcoder_mask; 3457 } 3458 3459 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) 3460 { 3461 struct drm_device *dev = crtc->base.dev; 3462 struct drm_i915_private *dev_priv = to_i915(dev); 3463 u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv); 3464 enum transcoder cpu_transcoder; 3465 u8 master_pipes, slave_pipes; 3466 u8 enabled_transcoders = 0; 3467 3468 /* 3469 * XXX: Do intel_display_power_get_if_enabled before reading this (for 3470 * consistency and less surprising code; it's in always on power). 3471 */ 3472 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, 3473 panel_transcoder_mask) { 3474 enum intel_display_power_domain power_domain; 3475 intel_wakeref_t wakeref; 3476 enum pipe trans_pipe; 3477 u32 tmp = 0; 3478 3479 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3480 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3481 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3482 3483 if (!(tmp & TRANS_DDI_FUNC_ENABLE)) 3484 continue; 3485 3486 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 3487 default: 3488 drm_WARN(dev, 1, 3489 "unknown pipe linked to transcoder %s\n", 3490 transcoder_name(cpu_transcoder)); 3491 fallthrough; 3492 case TRANS_DDI_EDP_INPUT_A_ONOFF: 3493 case TRANS_DDI_EDP_INPUT_A_ON: 3494 trans_pipe = PIPE_A; 3495 break; 3496 case TRANS_DDI_EDP_INPUT_B_ONOFF: 3497 trans_pipe = PIPE_B; 3498 break; 3499 case TRANS_DDI_EDP_INPUT_C_ONOFF: 3500 trans_pipe = PIPE_C; 3501 break; 3502 case TRANS_DDI_EDP_INPUT_D_ONOFF: 3503 trans_pipe = PIPE_D; 3504 break; 3505 } 3506 3507 if (trans_pipe == crtc->pipe) 3508 enabled_transcoders |= BIT(cpu_transcoder); 3509 } 3510 3511 /* single pipe or bigjoiner master */ 3512 cpu_transcoder = (enum transcoder) crtc->pipe; 3513 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 3514 enabled_transcoders |= BIT(cpu_transcoder); 3515 3516 /* bigjoiner slave -> consider the master pipe's transcoder as well */ 3517 enabled_bigjoiner_pipes(dev_priv, &master_pipes, &slave_pipes); 3518 if (slave_pipes & BIT(crtc->pipe)) { 3519 cpu_transcoder = (enum transcoder) 3520 get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes); 3521 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 3522 enabled_transcoders |= BIT(cpu_transcoder); 3523 } 3524 3525 return enabled_transcoders; 3526 } 3527 3528 static bool has_edp_transcoders(u8 enabled_transcoders) 3529 { 3530 return enabled_transcoders & BIT(TRANSCODER_EDP); 3531 } 3532 3533 static bool has_dsi_transcoders(u8 enabled_transcoders) 3534 { 3535 return enabled_transcoders & (BIT(TRANSCODER_DSI_0) | 3536 BIT(TRANSCODER_DSI_1)); 3537 } 3538 3539 static bool has_pipe_transcoders(u8 enabled_transcoders) 3540 { 3541 return enabled_transcoders & ~(BIT(TRANSCODER_EDP) | 3542 BIT(TRANSCODER_DSI_0) | 3543 BIT(TRANSCODER_DSI_1)); 3544 } 3545 3546 static void assert_enabled_transcoders(struct drm_i915_private *i915, 3547 u8 enabled_transcoders) 3548 { 3549 /* Only one type of transcoder please */ 3550 drm_WARN_ON(&i915->drm, 3551 has_edp_transcoders(enabled_transcoders) + 3552 has_dsi_transcoders(enabled_transcoders) + 3553 has_pipe_transcoders(enabled_transcoders) > 1); 3554 3555 /* Only DSI transcoders can be ganged */ 3556 drm_WARN_ON(&i915->drm, 3557 !has_dsi_transcoders(enabled_transcoders) && 3558 !is_power_of_2(enabled_transcoders)); 3559 } 3560 3561 static bool hsw_get_transcoder_state(struct intel_crtc *crtc, 3562 struct intel_crtc_state *pipe_config, 3563 struct intel_display_power_domain_set *power_domain_set) 3564 { 3565 struct drm_device *dev = crtc->base.dev; 3566 struct drm_i915_private *dev_priv = to_i915(dev); 3567 unsigned long enabled_transcoders; 3568 u32 tmp; 3569 3570 enabled_transcoders = hsw_enabled_transcoders(crtc); 3571 if (!enabled_transcoders) 3572 return false; 3573 3574 assert_enabled_transcoders(dev_priv, enabled_transcoders); 3575 3576 /* 3577 * With the exception of DSI we should only ever have 3578 * a single enabled transcoder. With DSI let's just 3579 * pick the first one. 3580 */ 3581 pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1; 3582 3583 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 3584 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) 3585 return false; 3586 3587 if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) { 3588 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); 3589 3590 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF) 3591 pipe_config->pch_pfit.force_thru = true; 3592 } 3593 3594 tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder)); 3595 3596 return tmp & TRANSCONF_ENABLE; 3597 } 3598 3599 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, 3600 struct intel_crtc_state *pipe_config, 3601 struct intel_display_power_domain_set *power_domain_set) 3602 { 3603 struct drm_device *dev = crtc->base.dev; 3604 struct drm_i915_private *dev_priv = to_i915(dev); 3605 enum transcoder cpu_transcoder; 3606 enum port port; 3607 u32 tmp; 3608 3609 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { 3610 if (port == PORT_A) 3611 cpu_transcoder = TRANSCODER_DSI_A; 3612 else 3613 cpu_transcoder = TRANSCODER_DSI_C; 3614 3615 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 3616 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) 3617 continue; 3618 3619 /* 3620 * The PLL needs to be enabled with a valid divider 3621 * configuration, otherwise accessing DSI registers will hang 3622 * the machine. See BSpec North Display Engine 3623 * registers/MIPI[BXT]. We can break out here early, since we 3624 * need the same DSI PLL to be enabled for both DSI ports. 3625 */ 3626 if (!bxt_dsi_pll_is_enabled(dev_priv)) 3627 break; 3628 3629 /* XXX: this works for video mode only */ 3630 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); 3631 if (!(tmp & DPI_ENABLE)) 3632 continue; 3633 3634 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 3635 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) 3636 continue; 3637 3638 pipe_config->cpu_transcoder = cpu_transcoder; 3639 break; 3640 } 3641 3642 return transcoder_is_dsi(pipe_config->cpu_transcoder); 3643 } 3644 3645 static void intel_bigjoiner_get_config(struct intel_crtc_state *crtc_state) 3646 { 3647 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3648 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 3649 u8 master_pipes, slave_pipes; 3650 enum pipe pipe = crtc->pipe; 3651 3652 enabled_bigjoiner_pipes(i915, &master_pipes, &slave_pipes); 3653 3654 if (((master_pipes | slave_pipes) & BIT(pipe)) == 0) 3655 return; 3656 3657 crtc_state->bigjoiner_pipes = 3658 BIT(get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes)) | 3659 get_bigjoiner_slave_pipes(pipe, master_pipes, slave_pipes); 3660 } 3661 3662 static bool hsw_get_pipe_config(struct intel_crtc *crtc, 3663 struct intel_crtc_state *pipe_config) 3664 { 3665 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3666 bool active; 3667 u32 tmp; 3668 3669 if (!intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains, 3670 POWER_DOMAIN_PIPE(crtc->pipe))) 3671 return false; 3672 3673 pipe_config->shared_dpll = NULL; 3674 3675 active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains); 3676 3677 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 3678 bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) { 3679 drm_WARN_ON(&dev_priv->drm, active); 3680 active = true; 3681 } 3682 3683 if (!active) 3684 goto out; 3685 3686 intel_dsc_get_config(pipe_config); 3687 intel_bigjoiner_get_config(pipe_config); 3688 3689 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || 3690 DISPLAY_VER(dev_priv) >= 11) 3691 intel_get_transcoder_timings(crtc, pipe_config); 3692 3693 if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder)) 3694 intel_vrr_get_config(pipe_config); 3695 3696 intel_get_pipe_src_size(crtc, pipe_config); 3697 3698 if (IS_HASWELL(dev_priv)) { 3699 u32 tmp = intel_de_read(dev_priv, 3700 TRANSCONF(pipe_config->cpu_transcoder)); 3701 3702 if (tmp & TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW) 3703 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3704 else 3705 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3706 } else { 3707 pipe_config->output_format = 3708 bdw_get_pipe_misc_output_format(crtc); 3709 } 3710 3711 pipe_config->gamma_mode = intel_de_read(dev_priv, 3712 GAMMA_MODE(crtc->pipe)); 3713 3714 pipe_config->csc_mode = intel_de_read(dev_priv, 3715 PIPE_CSC_MODE(crtc->pipe)); 3716 3717 if (DISPLAY_VER(dev_priv) >= 9) { 3718 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe)); 3719 3720 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE) 3721 pipe_config->gamma_enable = true; 3722 3723 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE) 3724 pipe_config->csc_enable = true; 3725 } else { 3726 i9xx_get_pipe_color_config(pipe_config); 3727 } 3728 3729 intel_color_get_config(pipe_config); 3730 3731 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe)); 3732 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); 3733 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 3734 pipe_config->ips_linetime = 3735 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); 3736 3737 if (intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains, 3738 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) { 3739 if (DISPLAY_VER(dev_priv) >= 9) 3740 skl_scaler_get_config(pipe_config); 3741 else 3742 ilk_get_pfit_config(pipe_config); 3743 } 3744 3745 hsw_ips_get_config(pipe_config); 3746 3747 if (pipe_config->cpu_transcoder != TRANSCODER_EDP && 3748 !transcoder_is_dsi(pipe_config->cpu_transcoder)) { 3749 pipe_config->pixel_multiplier = 3750 intel_de_read(dev_priv, 3751 TRANS_MULT(pipe_config->cpu_transcoder)) + 1; 3752 } else { 3753 pipe_config->pixel_multiplier = 1; 3754 } 3755 3756 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { 3757 tmp = intel_de_read(dev_priv, DISPLAY_VER(dev_priv) >= 14 ? 3758 MTL_CHICKEN_TRANS(pipe_config->cpu_transcoder) : 3759 CHICKEN_TRANS(pipe_config->cpu_transcoder)); 3760 3761 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1; 3762 } else { 3763 /* no idea if this is correct */ 3764 pipe_config->framestart_delay = 1; 3765 } 3766 3767 out: 3768 intel_display_power_put_all_in_set(dev_priv, &crtc->hw_readout_power_domains); 3769 3770 return active; 3771 } 3772 3773 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state) 3774 { 3775 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3776 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 3777 3778 if (!i915->display.funcs.display->get_pipe_config(crtc, crtc_state)) 3779 return false; 3780 3781 crtc_state->hw.active = true; 3782 3783 intel_crtc_readout_derived_state(crtc_state); 3784 3785 return true; 3786 } 3787 3788 static int i9xx_pll_refclk(struct drm_device *dev, 3789 const struct intel_crtc_state *pipe_config) 3790 { 3791 struct drm_i915_private *dev_priv = to_i915(dev); 3792 u32 dpll = pipe_config->dpll_hw_state.dpll; 3793 3794 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) 3795 return dev_priv->display.vbt.lvds_ssc_freq; 3796 else if (HAS_PCH_SPLIT(dev_priv)) 3797 return 120000; 3798 else if (DISPLAY_VER(dev_priv) != 2) 3799 return 96000; 3800 else 3801 return 48000; 3802 } 3803 3804 /* Returns the clock of the currently programmed mode of the given pipe. */ 3805 void i9xx_crtc_clock_get(struct intel_crtc *crtc, 3806 struct intel_crtc_state *pipe_config) 3807 { 3808 struct drm_device *dev = crtc->base.dev; 3809 struct drm_i915_private *dev_priv = to_i915(dev); 3810 u32 dpll = pipe_config->dpll_hw_state.dpll; 3811 u32 fp; 3812 struct dpll clock; 3813 int port_clock; 3814 int refclk = i9xx_pll_refclk(dev, pipe_config); 3815 3816 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 3817 fp = pipe_config->dpll_hw_state.fp0; 3818 else 3819 fp = pipe_config->dpll_hw_state.fp1; 3820 3821 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 3822 if (IS_PINEVIEW(dev_priv)) { 3823 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; 3824 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; 3825 } else { 3826 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 3827 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 3828 } 3829 3830 if (DISPLAY_VER(dev_priv) != 2) { 3831 if (IS_PINEVIEW(dev_priv)) 3832 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> 3833 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); 3834 else 3835 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> 3836 DPLL_FPA01_P1_POST_DIV_SHIFT); 3837 3838 switch (dpll & DPLL_MODE_MASK) { 3839 case DPLLB_MODE_DAC_SERIAL: 3840 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 3841 5 : 10; 3842 break; 3843 case DPLLB_MODE_LVDS: 3844 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 3845 7 : 14; 3846 break; 3847 default: 3848 drm_dbg_kms(&dev_priv->drm, 3849 "Unknown DPLL mode %08x in programmed " 3850 "mode\n", (int)(dpll & DPLL_MODE_MASK)); 3851 return; 3852 } 3853 3854 if (IS_PINEVIEW(dev_priv)) 3855 port_clock = pnv_calc_dpll_params(refclk, &clock); 3856 else 3857 port_clock = i9xx_calc_dpll_params(refclk, &clock); 3858 } else { 3859 enum pipe lvds_pipe; 3860 3861 if (IS_I85X(dev_priv) && 3862 intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) && 3863 lvds_pipe == crtc->pipe) { 3864 u32 lvds = intel_de_read(dev_priv, LVDS); 3865 3866 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 3867 DPLL_FPA01_P1_POST_DIV_SHIFT); 3868 3869 if (lvds & LVDS_CLKB_POWER_UP) 3870 clock.p2 = 7; 3871 else 3872 clock.p2 = 14; 3873 } else { 3874 if (dpll & PLL_P1_DIVIDE_BY_TWO) 3875 clock.p1 = 2; 3876 else { 3877 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 3878 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 3879 } 3880 if (dpll & PLL_P2_DIVIDE_BY_4) 3881 clock.p2 = 4; 3882 else 3883 clock.p2 = 2; 3884 } 3885 3886 port_clock = i9xx_calc_dpll_params(refclk, &clock); 3887 } 3888 3889 /* 3890 * This value includes pixel_multiplier. We will use 3891 * port_clock to compute adjusted_mode.crtc_clock in the 3892 * encoder's get_config() function. 3893 */ 3894 pipe_config->port_clock = port_clock; 3895 } 3896 3897 int intel_dotclock_calculate(int link_freq, 3898 const struct intel_link_m_n *m_n) 3899 { 3900 /* 3901 * The calculation for the data clock is: 3902 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp 3903 * But we want to avoid losing precison if possible, so: 3904 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) 3905 * 3906 * and the link clock is simpler: 3907 * link_clock = (m * link_clock) / n 3908 */ 3909 3910 if (!m_n->link_n) 3911 return 0; 3912 3913 return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq), 3914 m_n->link_n); 3915 } 3916 3917 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config) 3918 { 3919 int dotclock; 3920 3921 if (intel_crtc_has_dp_encoder(pipe_config)) 3922 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 3923 &pipe_config->dp_m_n); 3924 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) 3925 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24, 3926 pipe_config->pipe_bpp); 3927 else 3928 dotclock = pipe_config->port_clock; 3929 3930 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 3931 !intel_crtc_has_dp_encoder(pipe_config)) 3932 dotclock *= 2; 3933 3934 if (pipe_config->pixel_multiplier) 3935 dotclock /= pipe_config->pixel_multiplier; 3936 3937 return dotclock; 3938 } 3939 3940 /* Returns the currently programmed mode of the given encoder. */ 3941 struct drm_display_mode * 3942 intel_encoder_current_mode(struct intel_encoder *encoder) 3943 { 3944 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3945 struct intel_crtc_state *crtc_state; 3946 struct drm_display_mode *mode; 3947 struct intel_crtc *crtc; 3948 enum pipe pipe; 3949 3950 if (!encoder->get_hw_state(encoder, &pipe)) 3951 return NULL; 3952 3953 crtc = intel_crtc_for_pipe(dev_priv, pipe); 3954 3955 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 3956 if (!mode) 3957 return NULL; 3958 3959 crtc_state = intel_crtc_state_alloc(crtc); 3960 if (!crtc_state) { 3961 kfree(mode); 3962 return NULL; 3963 } 3964 3965 if (!intel_crtc_get_pipe_config(crtc_state)) { 3966 kfree(crtc_state); 3967 kfree(mode); 3968 return NULL; 3969 } 3970 3971 intel_encoder_get_config(encoder, crtc_state); 3972 3973 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode); 3974 3975 kfree(crtc_state); 3976 3977 return mode; 3978 } 3979 3980 static bool encoders_cloneable(const struct intel_encoder *a, 3981 const struct intel_encoder *b) 3982 { 3983 /* masks could be asymmetric, so check both ways */ 3984 return a == b || (a->cloneable & BIT(b->type) && 3985 b->cloneable & BIT(a->type)); 3986 } 3987 3988 static bool check_single_encoder_cloning(struct intel_atomic_state *state, 3989 struct intel_crtc *crtc, 3990 struct intel_encoder *encoder) 3991 { 3992 struct intel_encoder *source_encoder; 3993 struct drm_connector *connector; 3994 struct drm_connector_state *connector_state; 3995 int i; 3996 3997 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 3998 if (connector_state->crtc != &crtc->base) 3999 continue; 4000 4001 source_encoder = 4002 to_intel_encoder(connector_state->best_encoder); 4003 if (!encoders_cloneable(encoder, source_encoder)) 4004 return false; 4005 } 4006 4007 return true; 4008 } 4009 4010 static int icl_add_linked_planes(struct intel_atomic_state *state) 4011 { 4012 struct intel_plane *plane, *linked; 4013 struct intel_plane_state *plane_state, *linked_plane_state; 4014 int i; 4015 4016 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4017 linked = plane_state->planar_linked_plane; 4018 4019 if (!linked) 4020 continue; 4021 4022 linked_plane_state = intel_atomic_get_plane_state(state, linked); 4023 if (IS_ERR(linked_plane_state)) 4024 return PTR_ERR(linked_plane_state); 4025 4026 drm_WARN_ON(state->base.dev, 4027 linked_plane_state->planar_linked_plane != plane); 4028 drm_WARN_ON(state->base.dev, 4029 linked_plane_state->planar_slave == plane_state->planar_slave); 4030 } 4031 4032 return 0; 4033 } 4034 4035 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state) 4036 { 4037 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4038 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4039 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 4040 struct intel_plane *plane, *linked; 4041 struct intel_plane_state *plane_state; 4042 int i; 4043 4044 if (DISPLAY_VER(dev_priv) < 11) 4045 return 0; 4046 4047 /* 4048 * Destroy all old plane links and make the slave plane invisible 4049 * in the crtc_state->active_planes mask. 4050 */ 4051 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4052 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane) 4053 continue; 4054 4055 plane_state->planar_linked_plane = NULL; 4056 if (plane_state->planar_slave && !plane_state->uapi.visible) { 4057 crtc_state->enabled_planes &= ~BIT(plane->id); 4058 crtc_state->active_planes &= ~BIT(plane->id); 4059 crtc_state->update_planes |= BIT(plane->id); 4060 crtc_state->data_rate[plane->id] = 0; 4061 crtc_state->rel_data_rate[plane->id] = 0; 4062 } 4063 4064 plane_state->planar_slave = false; 4065 } 4066 4067 if (!crtc_state->nv12_planes) 4068 return 0; 4069 4070 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4071 struct intel_plane_state *linked_state = NULL; 4072 4073 if (plane->pipe != crtc->pipe || 4074 !(crtc_state->nv12_planes & BIT(plane->id))) 4075 continue; 4076 4077 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) { 4078 if (!icl_is_nv12_y_plane(dev_priv, linked->id)) 4079 continue; 4080 4081 if (crtc_state->active_planes & BIT(linked->id)) 4082 continue; 4083 4084 linked_state = intel_atomic_get_plane_state(state, linked); 4085 if (IS_ERR(linked_state)) 4086 return PTR_ERR(linked_state); 4087 4088 break; 4089 } 4090 4091 if (!linked_state) { 4092 drm_dbg_kms(&dev_priv->drm, 4093 "Need %d free Y planes for planar YUV\n", 4094 hweight8(crtc_state->nv12_planes)); 4095 4096 return -EINVAL; 4097 } 4098 4099 plane_state->planar_linked_plane = linked; 4100 4101 linked_state->planar_slave = true; 4102 linked_state->planar_linked_plane = plane; 4103 crtc_state->enabled_planes |= BIT(linked->id); 4104 crtc_state->active_planes |= BIT(linked->id); 4105 crtc_state->update_planes |= BIT(linked->id); 4106 crtc_state->data_rate[linked->id] = 4107 crtc_state->data_rate_y[plane->id]; 4108 crtc_state->rel_data_rate[linked->id] = 4109 crtc_state->rel_data_rate_y[plane->id]; 4110 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n", 4111 linked->base.name, plane->base.name); 4112 4113 /* Copy parameters to slave plane */ 4114 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE; 4115 linked_state->color_ctl = plane_state->color_ctl; 4116 linked_state->view = plane_state->view; 4117 linked_state->decrypt = plane_state->decrypt; 4118 4119 intel_plane_copy_hw_state(linked_state, plane_state); 4120 linked_state->uapi.src = plane_state->uapi.src; 4121 linked_state->uapi.dst = plane_state->uapi.dst; 4122 4123 if (icl_is_hdr_plane(dev_priv, plane->id)) { 4124 if (linked->id == PLANE_SPRITE5) 4125 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL; 4126 else if (linked->id == PLANE_SPRITE4) 4127 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL; 4128 else if (linked->id == PLANE_SPRITE3) 4129 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL; 4130 else if (linked->id == PLANE_SPRITE2) 4131 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL; 4132 else 4133 MISSING_CASE(linked->id); 4134 } 4135 } 4136 4137 return 0; 4138 } 4139 4140 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state) 4141 { 4142 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 4143 struct intel_atomic_state *state = 4144 to_intel_atomic_state(new_crtc_state->uapi.state); 4145 const struct intel_crtc_state *old_crtc_state = 4146 intel_atomic_get_old_crtc_state(state, crtc); 4147 4148 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes; 4149 } 4150 4151 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) 4152 { 4153 const struct drm_display_mode *pipe_mode = 4154 &crtc_state->hw.pipe_mode; 4155 int linetime_wm; 4156 4157 if (!crtc_state->hw.enable) 4158 return 0; 4159 4160 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4161 pipe_mode->crtc_clock); 4162 4163 return min(linetime_wm, 0x1ff); 4164 } 4165 4166 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, 4167 const struct intel_cdclk_state *cdclk_state) 4168 { 4169 const struct drm_display_mode *pipe_mode = 4170 &crtc_state->hw.pipe_mode; 4171 int linetime_wm; 4172 4173 if (!crtc_state->hw.enable) 4174 return 0; 4175 4176 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4177 cdclk_state->logical.cdclk); 4178 4179 return min(linetime_wm, 0x1ff); 4180 } 4181 4182 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) 4183 { 4184 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4185 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4186 const struct drm_display_mode *pipe_mode = 4187 &crtc_state->hw.pipe_mode; 4188 int linetime_wm; 4189 4190 if (!crtc_state->hw.enable) 4191 return 0; 4192 4193 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8, 4194 crtc_state->pixel_rate); 4195 4196 /* Display WA #1135: BXT:ALL GLK:ALL */ 4197 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 4198 skl_watermark_ipc_enabled(dev_priv)) 4199 linetime_wm /= 2; 4200 4201 return min(linetime_wm, 0x1ff); 4202 } 4203 4204 static int hsw_compute_linetime_wm(struct intel_atomic_state *state, 4205 struct intel_crtc *crtc) 4206 { 4207 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4208 struct intel_crtc_state *crtc_state = 4209 intel_atomic_get_new_crtc_state(state, crtc); 4210 const struct intel_cdclk_state *cdclk_state; 4211 4212 if (DISPLAY_VER(dev_priv) >= 9) 4213 crtc_state->linetime = skl_linetime_wm(crtc_state); 4214 else 4215 crtc_state->linetime = hsw_linetime_wm(crtc_state); 4216 4217 if (!hsw_crtc_supports_ips(crtc)) 4218 return 0; 4219 4220 cdclk_state = intel_atomic_get_cdclk_state(state); 4221 if (IS_ERR(cdclk_state)) 4222 return PTR_ERR(cdclk_state); 4223 4224 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state, 4225 cdclk_state); 4226 4227 return 0; 4228 } 4229 4230 static int intel_crtc_atomic_check(struct intel_atomic_state *state, 4231 struct intel_crtc *crtc) 4232 { 4233 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4234 struct intel_crtc_state *crtc_state = 4235 intel_atomic_get_new_crtc_state(state, crtc); 4236 int ret; 4237 4238 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) && 4239 intel_crtc_needs_modeset(crtc_state) && 4240 !crtc_state->hw.active) 4241 crtc_state->update_wm_post = true; 4242 4243 if (intel_crtc_needs_modeset(crtc_state)) { 4244 ret = intel_dpll_crtc_get_shared_dpll(state, crtc); 4245 if (ret) 4246 return ret; 4247 } 4248 4249 /* 4250 * May need to update pipe gamma enable bits 4251 * when C8 planes are getting enabled/disabled. 4252 */ 4253 if (c8_planes_changed(crtc_state)) 4254 crtc_state->uapi.color_mgmt_changed = true; 4255 4256 if (intel_crtc_needs_color_update(crtc_state)) { 4257 ret = intel_color_check(crtc_state); 4258 if (ret) 4259 return ret; 4260 } 4261 4262 ret = intel_compute_pipe_wm(state, crtc); 4263 if (ret) { 4264 drm_dbg_kms(&dev_priv->drm, 4265 "Target pipe watermarks are invalid\n"); 4266 return ret; 4267 } 4268 4269 /* 4270 * Calculate 'intermediate' watermarks that satisfy both the 4271 * old state and the new state. We can program these 4272 * immediately. 4273 */ 4274 ret = intel_compute_intermediate_wm(state, crtc); 4275 if (ret) { 4276 drm_dbg_kms(&dev_priv->drm, 4277 "No valid intermediate pipe watermarks are possible\n"); 4278 return ret; 4279 } 4280 4281 if (DISPLAY_VER(dev_priv) >= 9) { 4282 if (intel_crtc_needs_modeset(crtc_state) || 4283 intel_crtc_needs_fastset(crtc_state)) { 4284 ret = skl_update_scaler_crtc(crtc_state); 4285 if (ret) 4286 return ret; 4287 } 4288 4289 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state); 4290 if (ret) 4291 return ret; 4292 } 4293 4294 if (HAS_IPS(dev_priv)) { 4295 ret = hsw_ips_compute_config(state, crtc); 4296 if (ret) 4297 return ret; 4298 } 4299 4300 if (DISPLAY_VER(dev_priv) >= 9 || 4301 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 4302 ret = hsw_compute_linetime_wm(state, crtc); 4303 if (ret) 4304 return ret; 4305 4306 } 4307 4308 ret = intel_psr2_sel_fetch_update(state, crtc); 4309 if (ret) 4310 return ret; 4311 4312 return 0; 4313 } 4314 4315 static int 4316 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state, 4317 struct intel_crtc_state *crtc_state) 4318 { 4319 struct drm_connector *connector = conn_state->connector; 4320 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 4321 const struct drm_display_info *info = &connector->display_info; 4322 int bpp; 4323 4324 switch (conn_state->max_bpc) { 4325 case 6 ... 7: 4326 bpp = 6 * 3; 4327 break; 4328 case 8 ... 9: 4329 bpp = 8 * 3; 4330 break; 4331 case 10 ... 11: 4332 bpp = 10 * 3; 4333 break; 4334 case 12 ... 16: 4335 bpp = 12 * 3; 4336 break; 4337 default: 4338 MISSING_CASE(conn_state->max_bpc); 4339 return -EINVAL; 4340 } 4341 4342 if (bpp < crtc_state->pipe_bpp) { 4343 drm_dbg_kms(&i915->drm, 4344 "[CONNECTOR:%d:%s] Limiting display bpp to %d " 4345 "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n", 4346 connector->base.id, connector->name, 4347 bpp, 3 * info->bpc, 4348 3 * conn_state->max_requested_bpc, 4349 crtc_state->pipe_bpp); 4350 4351 crtc_state->pipe_bpp = bpp; 4352 } 4353 4354 return 0; 4355 } 4356 4357 static int 4358 compute_baseline_pipe_bpp(struct intel_atomic_state *state, 4359 struct intel_crtc *crtc) 4360 { 4361 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4362 struct intel_crtc_state *crtc_state = 4363 intel_atomic_get_new_crtc_state(state, crtc); 4364 struct drm_connector *connector; 4365 struct drm_connector_state *connector_state; 4366 int bpp, i; 4367 4368 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 4369 IS_CHERRYVIEW(dev_priv))) 4370 bpp = 10*3; 4371 else if (DISPLAY_VER(dev_priv) >= 5) 4372 bpp = 12*3; 4373 else 4374 bpp = 8*3; 4375 4376 crtc_state->pipe_bpp = bpp; 4377 4378 /* Clamp display bpp to connector max bpp */ 4379 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4380 int ret; 4381 4382 if (connector_state->crtc != &crtc->base) 4383 continue; 4384 4385 ret = compute_sink_pipe_bpp(connector_state, crtc_state); 4386 if (ret) 4387 return ret; 4388 } 4389 4390 return 0; 4391 } 4392 4393 static bool check_digital_port_conflicts(struct intel_atomic_state *state) 4394 { 4395 struct drm_device *dev = state->base.dev; 4396 struct drm_connector *connector; 4397 struct drm_connector_list_iter conn_iter; 4398 unsigned int used_ports = 0; 4399 unsigned int used_mst_ports = 0; 4400 bool ret = true; 4401 4402 /* 4403 * We're going to peek into connector->state, 4404 * hence connection_mutex must be held. 4405 */ 4406 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex); 4407 4408 /* 4409 * Walk the connector list instead of the encoder 4410 * list to detect the problem on ddi platforms 4411 * where there's just one encoder per digital port. 4412 */ 4413 drm_connector_list_iter_begin(dev, &conn_iter); 4414 drm_for_each_connector_iter(connector, &conn_iter) { 4415 struct drm_connector_state *connector_state; 4416 struct intel_encoder *encoder; 4417 4418 connector_state = 4419 drm_atomic_get_new_connector_state(&state->base, 4420 connector); 4421 if (!connector_state) 4422 connector_state = connector->state; 4423 4424 if (!connector_state->best_encoder) 4425 continue; 4426 4427 encoder = to_intel_encoder(connector_state->best_encoder); 4428 4429 drm_WARN_ON(dev, !connector_state->crtc); 4430 4431 switch (encoder->type) { 4432 case INTEL_OUTPUT_DDI: 4433 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev)))) 4434 break; 4435 fallthrough; 4436 case INTEL_OUTPUT_DP: 4437 case INTEL_OUTPUT_HDMI: 4438 case INTEL_OUTPUT_EDP: 4439 /* the same port mustn't appear more than once */ 4440 if (used_ports & BIT(encoder->port)) 4441 ret = false; 4442 4443 used_ports |= BIT(encoder->port); 4444 break; 4445 case INTEL_OUTPUT_DP_MST: 4446 used_mst_ports |= 4447 1 << encoder->port; 4448 break; 4449 default: 4450 break; 4451 } 4452 } 4453 drm_connector_list_iter_end(&conn_iter); 4454 4455 /* can't mix MST and SST/HDMI on the same port */ 4456 if (used_ports & used_mst_ports) 4457 return false; 4458 4459 return ret; 4460 } 4461 4462 static void 4463 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state, 4464 struct intel_crtc *crtc) 4465 { 4466 struct intel_crtc_state *crtc_state = 4467 intel_atomic_get_new_crtc_state(state, crtc); 4468 4469 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 4470 4471 drm_property_replace_blob(&crtc_state->hw.degamma_lut, 4472 crtc_state->uapi.degamma_lut); 4473 drm_property_replace_blob(&crtc_state->hw.gamma_lut, 4474 crtc_state->uapi.gamma_lut); 4475 drm_property_replace_blob(&crtc_state->hw.ctm, 4476 crtc_state->uapi.ctm); 4477 } 4478 4479 static void 4480 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state, 4481 struct intel_crtc *crtc) 4482 { 4483 struct intel_crtc_state *crtc_state = 4484 intel_atomic_get_new_crtc_state(state, crtc); 4485 4486 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 4487 4488 crtc_state->hw.enable = crtc_state->uapi.enable; 4489 crtc_state->hw.active = crtc_state->uapi.active; 4490 drm_mode_copy(&crtc_state->hw.mode, 4491 &crtc_state->uapi.mode); 4492 drm_mode_copy(&crtc_state->hw.adjusted_mode, 4493 &crtc_state->uapi.adjusted_mode); 4494 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter; 4495 4496 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 4497 } 4498 4499 static void 4500 copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state, 4501 struct intel_crtc *slave_crtc) 4502 { 4503 struct intel_crtc_state *slave_crtc_state = 4504 intel_atomic_get_new_crtc_state(state, slave_crtc); 4505 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 4506 const struct intel_crtc_state *master_crtc_state = 4507 intel_atomic_get_new_crtc_state(state, master_crtc); 4508 4509 drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut, 4510 master_crtc_state->hw.degamma_lut); 4511 drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut, 4512 master_crtc_state->hw.gamma_lut); 4513 drm_property_replace_blob(&slave_crtc_state->hw.ctm, 4514 master_crtc_state->hw.ctm); 4515 4516 slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed; 4517 } 4518 4519 static int 4520 copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state, 4521 struct intel_crtc *slave_crtc) 4522 { 4523 struct intel_crtc_state *slave_crtc_state = 4524 intel_atomic_get_new_crtc_state(state, slave_crtc); 4525 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 4526 const struct intel_crtc_state *master_crtc_state = 4527 intel_atomic_get_new_crtc_state(state, master_crtc); 4528 struct intel_crtc_state *saved_state; 4529 4530 WARN_ON(master_crtc_state->bigjoiner_pipes != 4531 slave_crtc_state->bigjoiner_pipes); 4532 4533 saved_state = kmemdup(master_crtc_state, sizeof(*saved_state), GFP_KERNEL); 4534 if (!saved_state) 4535 return -ENOMEM; 4536 4537 /* preserve some things from the slave's original crtc state */ 4538 saved_state->uapi = slave_crtc_state->uapi; 4539 saved_state->scaler_state = slave_crtc_state->scaler_state; 4540 saved_state->shared_dpll = slave_crtc_state->shared_dpll; 4541 saved_state->dpll_hw_state = slave_crtc_state->dpll_hw_state; 4542 saved_state->crc_enabled = slave_crtc_state->crc_enabled; 4543 4544 intel_crtc_free_hw_state(slave_crtc_state); 4545 memcpy(slave_crtc_state, saved_state, sizeof(*slave_crtc_state)); 4546 kfree(saved_state); 4547 4548 /* Re-init hw state */ 4549 memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw)); 4550 slave_crtc_state->hw.enable = master_crtc_state->hw.enable; 4551 slave_crtc_state->hw.active = master_crtc_state->hw.active; 4552 drm_mode_copy(&slave_crtc_state->hw.mode, 4553 &master_crtc_state->hw.mode); 4554 drm_mode_copy(&slave_crtc_state->hw.pipe_mode, 4555 &master_crtc_state->hw.pipe_mode); 4556 drm_mode_copy(&slave_crtc_state->hw.adjusted_mode, 4557 &master_crtc_state->hw.adjusted_mode); 4558 slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter; 4559 4560 copy_bigjoiner_crtc_state_nomodeset(state, slave_crtc); 4561 4562 slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed; 4563 slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed; 4564 slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed; 4565 4566 WARN_ON(master_crtc_state->bigjoiner_pipes != 4567 slave_crtc_state->bigjoiner_pipes); 4568 4569 return 0; 4570 } 4571 4572 static int 4573 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state, 4574 struct intel_crtc *crtc) 4575 { 4576 struct intel_crtc_state *crtc_state = 4577 intel_atomic_get_new_crtc_state(state, crtc); 4578 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4579 struct intel_crtc_state *saved_state; 4580 4581 saved_state = intel_crtc_state_alloc(crtc); 4582 if (!saved_state) 4583 return -ENOMEM; 4584 4585 /* free the old crtc_state->hw members */ 4586 intel_crtc_free_hw_state(crtc_state); 4587 4588 /* FIXME: before the switch to atomic started, a new pipe_config was 4589 * kzalloc'd. Code that depends on any field being zero should be 4590 * fixed, so that the crtc_state can be safely duplicated. For now, 4591 * only fields that are know to not cause problems are preserved. */ 4592 4593 saved_state->uapi = crtc_state->uapi; 4594 saved_state->inherited = crtc_state->inherited; 4595 saved_state->scaler_state = crtc_state->scaler_state; 4596 saved_state->shared_dpll = crtc_state->shared_dpll; 4597 saved_state->dpll_hw_state = crtc_state->dpll_hw_state; 4598 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, 4599 sizeof(saved_state->icl_port_dplls)); 4600 saved_state->crc_enabled = crtc_state->crc_enabled; 4601 if (IS_G4X(dev_priv) || 4602 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 4603 saved_state->wm = crtc_state->wm; 4604 4605 memcpy(crtc_state, saved_state, sizeof(*crtc_state)); 4606 kfree(saved_state); 4607 4608 intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc); 4609 4610 return 0; 4611 } 4612 4613 static int 4614 intel_modeset_pipe_config(struct intel_atomic_state *state, 4615 struct intel_crtc *crtc) 4616 { 4617 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4618 struct intel_crtc_state *crtc_state = 4619 intel_atomic_get_new_crtc_state(state, crtc); 4620 struct drm_connector *connector; 4621 struct drm_connector_state *connector_state; 4622 int pipe_src_w, pipe_src_h; 4623 int base_bpp, ret, i; 4624 bool retry = true; 4625 4626 crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe; 4627 4628 crtc_state->framestart_delay = 1; 4629 4630 /* 4631 * Sanitize sync polarity flags based on requested ones. If neither 4632 * positive or negative polarity is requested, treat this as meaning 4633 * negative polarity. 4634 */ 4635 if (!(crtc_state->hw.adjusted_mode.flags & 4636 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) 4637 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; 4638 4639 if (!(crtc_state->hw.adjusted_mode.flags & 4640 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 4641 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; 4642 4643 ret = compute_baseline_pipe_bpp(state, crtc); 4644 if (ret) 4645 return ret; 4646 4647 base_bpp = crtc_state->pipe_bpp; 4648 4649 /* 4650 * Determine the real pipe dimensions. Note that stereo modes can 4651 * increase the actual pipe size due to the frame doubling and 4652 * insertion of additional space for blanks between the frame. This 4653 * is stored in the crtc timings. We use the requested mode to do this 4654 * computation to clearly distinguish it from the adjusted mode, which 4655 * can be changed by the connectors in the below retry loop. 4656 */ 4657 drm_mode_get_hv_timing(&crtc_state->hw.mode, 4658 &pipe_src_w, &pipe_src_h); 4659 drm_rect_init(&crtc_state->pipe_src, 0, 0, 4660 pipe_src_w, pipe_src_h); 4661 4662 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4663 struct intel_encoder *encoder = 4664 to_intel_encoder(connector_state->best_encoder); 4665 4666 if (connector_state->crtc != &crtc->base) 4667 continue; 4668 4669 if (!check_single_encoder_cloning(state, crtc, encoder)) { 4670 drm_dbg_kms(&i915->drm, 4671 "[ENCODER:%d:%s] rejecting invalid cloning configuration\n", 4672 encoder->base.base.id, encoder->base.name); 4673 return -EINVAL; 4674 } 4675 4676 /* 4677 * Determine output_types before calling the .compute_config() 4678 * hooks so that the hooks can use this information safely. 4679 */ 4680 if (encoder->compute_output_type) 4681 crtc_state->output_types |= 4682 BIT(encoder->compute_output_type(encoder, crtc_state, 4683 connector_state)); 4684 else 4685 crtc_state->output_types |= BIT(encoder->type); 4686 } 4687 4688 encoder_retry: 4689 /* Ensure the port clock defaults are reset when retrying. */ 4690 crtc_state->port_clock = 0; 4691 crtc_state->pixel_multiplier = 1; 4692 4693 /* Fill in default crtc timings, allow encoders to overwrite them. */ 4694 drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode, 4695 CRTC_STEREO_DOUBLE); 4696 4697 /* Pass our mode to the connectors and the CRTC to give them a chance to 4698 * adjust it according to limitations or connector properties, and also 4699 * a chance to reject the mode entirely. 4700 */ 4701 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4702 struct intel_encoder *encoder = 4703 to_intel_encoder(connector_state->best_encoder); 4704 4705 if (connector_state->crtc != &crtc->base) 4706 continue; 4707 4708 ret = encoder->compute_config(encoder, crtc_state, 4709 connector_state); 4710 if (ret == -EDEADLK) 4711 return ret; 4712 if (ret < 0) { 4713 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n", 4714 encoder->base.base.id, encoder->base.name, ret); 4715 return ret; 4716 } 4717 } 4718 4719 /* Set default port clock if not overwritten by the encoder. Needs to be 4720 * done afterwards in case the encoder adjusts the mode. */ 4721 if (!crtc_state->port_clock) 4722 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock 4723 * crtc_state->pixel_multiplier; 4724 4725 ret = intel_crtc_compute_config(state, crtc); 4726 if (ret == -EDEADLK) 4727 return ret; 4728 if (ret == -EAGAIN) { 4729 if (drm_WARN(&i915->drm, !retry, 4730 "[CRTC:%d:%s] loop in pipe configuration computation\n", 4731 crtc->base.base.id, crtc->base.name)) 4732 return -EINVAL; 4733 4734 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] bw constrained, retrying\n", 4735 crtc->base.base.id, crtc->base.name); 4736 retry = false; 4737 goto encoder_retry; 4738 } 4739 if (ret < 0) { 4740 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n", 4741 crtc->base.base.id, crtc->base.name, ret); 4742 return ret; 4743 } 4744 4745 /* Dithering seems to not pass-through bits correctly when it should, so 4746 * only enable it on 6bpc panels and when its not a compliance 4747 * test requesting 6bpc video pattern. 4748 */ 4749 crtc_state->dither = (crtc_state->pipe_bpp == 6*3) && 4750 !crtc_state->dither_force_disable; 4751 drm_dbg_kms(&i915->drm, 4752 "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n", 4753 crtc->base.base.id, crtc->base.name, 4754 base_bpp, crtc_state->pipe_bpp, crtc_state->dither); 4755 4756 return 0; 4757 } 4758 4759 static int 4760 intel_modeset_pipe_config_late(struct intel_atomic_state *state, 4761 struct intel_crtc *crtc) 4762 { 4763 struct intel_crtc_state *crtc_state = 4764 intel_atomic_get_new_crtc_state(state, crtc); 4765 struct drm_connector_state *conn_state; 4766 struct drm_connector *connector; 4767 int i; 4768 4769 intel_bigjoiner_adjust_pipe_src(crtc_state); 4770 4771 for_each_new_connector_in_state(&state->base, connector, 4772 conn_state, i) { 4773 struct intel_encoder *encoder = 4774 to_intel_encoder(conn_state->best_encoder); 4775 int ret; 4776 4777 if (conn_state->crtc != &crtc->base || 4778 !encoder->compute_config_late) 4779 continue; 4780 4781 ret = encoder->compute_config_late(encoder, crtc_state, 4782 conn_state); 4783 if (ret) 4784 return ret; 4785 } 4786 4787 return 0; 4788 } 4789 4790 bool intel_fuzzy_clock_check(int clock1, int clock2) 4791 { 4792 int diff; 4793 4794 if (clock1 == clock2) 4795 return true; 4796 4797 if (!clock1 || !clock2) 4798 return false; 4799 4800 diff = abs(clock1 - clock2); 4801 4802 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) 4803 return true; 4804 4805 return false; 4806 } 4807 4808 static bool 4809 intel_compare_link_m_n(const struct intel_link_m_n *m_n, 4810 const struct intel_link_m_n *m2_n2) 4811 { 4812 return m_n->tu == m2_n2->tu && 4813 m_n->data_m == m2_n2->data_m && 4814 m_n->data_n == m2_n2->data_n && 4815 m_n->link_m == m2_n2->link_m && 4816 m_n->link_n == m2_n2->link_n; 4817 } 4818 4819 static bool 4820 intel_compare_infoframe(const union hdmi_infoframe *a, 4821 const union hdmi_infoframe *b) 4822 { 4823 return memcmp(a, b, sizeof(*a)) == 0; 4824 } 4825 4826 static bool 4827 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a, 4828 const struct drm_dp_vsc_sdp *b) 4829 { 4830 return memcmp(a, b, sizeof(*a)) == 0; 4831 } 4832 4833 static bool 4834 intel_compare_buffer(const u8 *a, const u8 *b, size_t len) 4835 { 4836 return memcmp(a, b, len) == 0; 4837 } 4838 4839 static void 4840 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv, 4841 bool fastset, const char *name, 4842 const union hdmi_infoframe *a, 4843 const union hdmi_infoframe *b) 4844 { 4845 if (fastset) { 4846 if (!drm_debug_enabled(DRM_UT_KMS)) 4847 return; 4848 4849 drm_dbg_kms(&dev_priv->drm, 4850 "fastset mismatch in %s infoframe\n", name); 4851 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 4852 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a); 4853 drm_dbg_kms(&dev_priv->drm, "found:\n"); 4854 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b); 4855 } else { 4856 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name); 4857 drm_err(&dev_priv->drm, "expected:\n"); 4858 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a); 4859 drm_err(&dev_priv->drm, "found:\n"); 4860 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b); 4861 } 4862 } 4863 4864 static void 4865 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv, 4866 bool fastset, const char *name, 4867 const struct drm_dp_vsc_sdp *a, 4868 const struct drm_dp_vsc_sdp *b) 4869 { 4870 if (fastset) { 4871 if (!drm_debug_enabled(DRM_UT_KMS)) 4872 return; 4873 4874 drm_dbg_kms(&dev_priv->drm, 4875 "fastset mismatch in %s dp sdp\n", name); 4876 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 4877 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a); 4878 drm_dbg_kms(&dev_priv->drm, "found:\n"); 4879 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b); 4880 } else { 4881 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name); 4882 drm_err(&dev_priv->drm, "expected:\n"); 4883 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a); 4884 drm_err(&dev_priv->drm, "found:\n"); 4885 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b); 4886 } 4887 } 4888 4889 /* Returns the length up to and including the last differing byte */ 4890 static size_t 4891 memcmp_diff_len(const u8 *a, const u8 *b, size_t len) 4892 { 4893 int i; 4894 4895 for (i = len - 1; i >= 0; i--) { 4896 if (a[i] != b[i]) 4897 return i + 1; 4898 } 4899 4900 return 0; 4901 } 4902 4903 static void 4904 pipe_config_buffer_mismatch(struct drm_i915_private *dev_priv, 4905 bool fastset, const char *name, 4906 const u8 *a, const u8 *b, size_t len) 4907 { 4908 if (fastset) { 4909 if (!drm_debug_enabled(DRM_UT_KMS)) 4910 return; 4911 4912 /* only dump up to the last difference */ 4913 len = memcmp_diff_len(a, b, len); 4914 4915 drm_dbg_kms(&dev_priv->drm, 4916 "fastset mismatch in %s buffer\n", name); 4917 print_hex_dump(KERN_DEBUG, "expected: ", DUMP_PREFIX_NONE, 4918 16, 0, a, len, false); 4919 print_hex_dump(KERN_DEBUG, "found: ", DUMP_PREFIX_NONE, 4920 16, 0, b, len, false); 4921 } else { 4922 /* only dump up to the last difference */ 4923 len = memcmp_diff_len(a, b, len); 4924 4925 drm_err(&dev_priv->drm, "mismatch in %s buffer\n", name); 4926 print_hex_dump(KERN_ERR, "expected: ", DUMP_PREFIX_NONE, 4927 16, 0, a, len, false); 4928 print_hex_dump(KERN_ERR, "found: ", DUMP_PREFIX_NONE, 4929 16, 0, b, len, false); 4930 } 4931 } 4932 4933 static void __printf(4, 5) 4934 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc, 4935 const char *name, const char *format, ...) 4936 { 4937 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4938 struct va_format vaf; 4939 va_list args; 4940 4941 va_start(args, format); 4942 vaf.fmt = format; 4943 vaf.va = &args; 4944 4945 if (fastset) 4946 drm_dbg_kms(&i915->drm, 4947 "[CRTC:%d:%s] fastset mismatch in %s %pV\n", 4948 crtc->base.base.id, crtc->base.name, name, &vaf); 4949 else 4950 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n", 4951 crtc->base.base.id, crtc->base.name, name, &vaf); 4952 4953 va_end(args); 4954 } 4955 4956 static bool fastboot_enabled(struct drm_i915_private *dev_priv) 4957 { 4958 if (dev_priv->params.fastboot != -1) 4959 return dev_priv->params.fastboot; 4960 4961 /* Enable fastboot by default on Skylake and newer */ 4962 if (DISPLAY_VER(dev_priv) >= 9) 4963 return true; 4964 4965 /* Enable fastboot by default on VLV and CHV */ 4966 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 4967 return true; 4968 4969 /* Disabled by default on all others */ 4970 return false; 4971 } 4972 4973 bool 4974 intel_pipe_config_compare(const struct intel_crtc_state *current_config, 4975 const struct intel_crtc_state *pipe_config, 4976 bool fastset) 4977 { 4978 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev); 4979 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4980 bool ret = true; 4981 bool fixup_inherited = fastset && 4982 current_config->inherited && !pipe_config->inherited; 4983 4984 if (fixup_inherited && !fastboot_enabled(dev_priv)) { 4985 drm_dbg_kms(&dev_priv->drm, 4986 "initial modeset and fastboot not set\n"); 4987 ret = false; 4988 } 4989 4990 #define PIPE_CONF_CHECK_X(name) do { \ 4991 if (current_config->name != pipe_config->name) { \ 4992 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 4993 "(expected 0x%08x, found 0x%08x)", \ 4994 current_config->name, \ 4995 pipe_config->name); \ 4996 ret = false; \ 4997 } \ 4998 } while (0) 4999 5000 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \ 5001 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \ 5002 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5003 "(expected 0x%08x, found 0x%08x)", \ 5004 current_config->name & (mask), \ 5005 pipe_config->name & (mask)); \ 5006 ret = false; \ 5007 } \ 5008 } while (0) 5009 5010 #define PIPE_CONF_CHECK_I(name) do { \ 5011 if (current_config->name != pipe_config->name) { \ 5012 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5013 "(expected %i, found %i)", \ 5014 current_config->name, \ 5015 pipe_config->name); \ 5016 ret = false; \ 5017 } \ 5018 } while (0) 5019 5020 #define PIPE_CONF_CHECK_BOOL(name) do { \ 5021 if (current_config->name != pipe_config->name) { \ 5022 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5023 "(expected %s, found %s)", \ 5024 str_yes_no(current_config->name), \ 5025 str_yes_no(pipe_config->name)); \ 5026 ret = false; \ 5027 } \ 5028 } while (0) 5029 5030 /* 5031 * Checks state where we only read out the enabling, but not the entire 5032 * state itself (like full infoframes or ELD for audio). These states 5033 * require a full modeset on bootup to fix up. 5034 */ 5035 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \ 5036 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \ 5037 PIPE_CONF_CHECK_BOOL(name); \ 5038 } else { \ 5039 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5040 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \ 5041 str_yes_no(current_config->name), \ 5042 str_yes_no(pipe_config->name)); \ 5043 ret = false; \ 5044 } \ 5045 } while (0) 5046 5047 #define PIPE_CONF_CHECK_P(name) do { \ 5048 if (current_config->name != pipe_config->name) { \ 5049 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5050 "(expected %p, found %p)", \ 5051 current_config->name, \ 5052 pipe_config->name); \ 5053 ret = false; \ 5054 } \ 5055 } while (0) 5056 5057 #define PIPE_CONF_CHECK_M_N(name) do { \ 5058 if (!intel_compare_link_m_n(¤t_config->name, \ 5059 &pipe_config->name)) { \ 5060 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5061 "(expected tu %i data %i/%i link %i/%i, " \ 5062 "found tu %i, data %i/%i link %i/%i)", \ 5063 current_config->name.tu, \ 5064 current_config->name.data_m, \ 5065 current_config->name.data_n, \ 5066 current_config->name.link_m, \ 5067 current_config->name.link_n, \ 5068 pipe_config->name.tu, \ 5069 pipe_config->name.data_m, \ 5070 pipe_config->name.data_n, \ 5071 pipe_config->name.link_m, \ 5072 pipe_config->name.link_n); \ 5073 ret = false; \ 5074 } \ 5075 } while (0) 5076 5077 #define PIPE_CONF_CHECK_TIMINGS(name) do { \ 5078 PIPE_CONF_CHECK_I(name.crtc_hdisplay); \ 5079 PIPE_CONF_CHECK_I(name.crtc_htotal); \ 5080 PIPE_CONF_CHECK_I(name.crtc_hblank_start); \ 5081 PIPE_CONF_CHECK_I(name.crtc_hblank_end); \ 5082 PIPE_CONF_CHECK_I(name.crtc_hsync_start); \ 5083 PIPE_CONF_CHECK_I(name.crtc_hsync_end); \ 5084 PIPE_CONF_CHECK_I(name.crtc_vdisplay); \ 5085 PIPE_CONF_CHECK_I(name.crtc_vtotal); \ 5086 PIPE_CONF_CHECK_I(name.crtc_vblank_start); \ 5087 PIPE_CONF_CHECK_I(name.crtc_vblank_end); \ 5088 PIPE_CONF_CHECK_I(name.crtc_vsync_start); \ 5089 PIPE_CONF_CHECK_I(name.crtc_vsync_end); \ 5090 } while (0) 5091 5092 #define PIPE_CONF_CHECK_RECT(name) do { \ 5093 PIPE_CONF_CHECK_I(name.x1); \ 5094 PIPE_CONF_CHECK_I(name.x2); \ 5095 PIPE_CONF_CHECK_I(name.y1); \ 5096 PIPE_CONF_CHECK_I(name.y2); \ 5097 } while (0) 5098 5099 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \ 5100 if ((current_config->name ^ pipe_config->name) & (mask)) { \ 5101 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5102 "(%x) (expected %i, found %i)", \ 5103 (mask), \ 5104 current_config->name & (mask), \ 5105 pipe_config->name & (mask)); \ 5106 ret = false; \ 5107 } \ 5108 } while (0) 5109 5110 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \ 5111 if (!intel_compare_infoframe(¤t_config->infoframes.name, \ 5112 &pipe_config->infoframes.name)) { \ 5113 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \ 5114 ¤t_config->infoframes.name, \ 5115 &pipe_config->infoframes.name); \ 5116 ret = false; \ 5117 } \ 5118 } while (0) 5119 5120 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \ 5121 if (!current_config->has_psr && !pipe_config->has_psr && \ 5122 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \ 5123 &pipe_config->infoframes.name)) { \ 5124 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \ 5125 ¤t_config->infoframes.name, \ 5126 &pipe_config->infoframes.name); \ 5127 ret = false; \ 5128 } \ 5129 } while (0) 5130 5131 #define PIPE_CONF_CHECK_BUFFER(name, len) do { \ 5132 BUILD_BUG_ON(sizeof(current_config->name) != (len)); \ 5133 BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \ 5134 if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \ 5135 pipe_config_buffer_mismatch(dev_priv, fastset, __stringify(name), \ 5136 current_config->name, \ 5137 pipe_config->name, \ 5138 (len)); \ 5139 ret = false; \ 5140 } \ 5141 } while (0) 5142 5143 #define PIPE_CONF_CHECK_COLOR_LUT(lut, is_pre_csc_lut) do { \ 5144 if (current_config->gamma_mode == pipe_config->gamma_mode && \ 5145 !intel_color_lut_equal(current_config, \ 5146 current_config->lut, pipe_config->lut, \ 5147 is_pre_csc_lut)) { \ 5148 pipe_config_mismatch(fastset, crtc, __stringify(lut), \ 5149 "hw_state doesn't match sw_state"); \ 5150 ret = false; \ 5151 } \ 5152 } while (0) 5153 5154 #define PIPE_CONF_CHECK_CSC(name) do { \ 5155 PIPE_CONF_CHECK_X(name.preoff[0]); \ 5156 PIPE_CONF_CHECK_X(name.preoff[1]); \ 5157 PIPE_CONF_CHECK_X(name.preoff[2]); \ 5158 PIPE_CONF_CHECK_X(name.coeff[0]); \ 5159 PIPE_CONF_CHECK_X(name.coeff[1]); \ 5160 PIPE_CONF_CHECK_X(name.coeff[2]); \ 5161 PIPE_CONF_CHECK_X(name.coeff[3]); \ 5162 PIPE_CONF_CHECK_X(name.coeff[4]); \ 5163 PIPE_CONF_CHECK_X(name.coeff[5]); \ 5164 PIPE_CONF_CHECK_X(name.coeff[6]); \ 5165 PIPE_CONF_CHECK_X(name.coeff[7]); \ 5166 PIPE_CONF_CHECK_X(name.coeff[8]); \ 5167 PIPE_CONF_CHECK_X(name.postoff[0]); \ 5168 PIPE_CONF_CHECK_X(name.postoff[1]); \ 5169 PIPE_CONF_CHECK_X(name.postoff[2]); \ 5170 } while (0) 5171 5172 #define PIPE_CONF_QUIRK(quirk) \ 5173 ((current_config->quirks | pipe_config->quirks) & (quirk)) 5174 5175 PIPE_CONF_CHECK_I(hw.enable); 5176 PIPE_CONF_CHECK_I(hw.active); 5177 5178 PIPE_CONF_CHECK_I(cpu_transcoder); 5179 PIPE_CONF_CHECK_I(mst_master_transcoder); 5180 5181 PIPE_CONF_CHECK_BOOL(has_pch_encoder); 5182 PIPE_CONF_CHECK_I(fdi_lanes); 5183 PIPE_CONF_CHECK_M_N(fdi_m_n); 5184 5185 PIPE_CONF_CHECK_I(lane_count); 5186 PIPE_CONF_CHECK_X(lane_lat_optim_mask); 5187 5188 if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) { 5189 if (!fastset || !pipe_config->seamless_m_n) 5190 PIPE_CONF_CHECK_M_N(dp_m_n); 5191 } else { 5192 PIPE_CONF_CHECK_M_N(dp_m_n); 5193 PIPE_CONF_CHECK_M_N(dp_m2_n2); 5194 } 5195 5196 PIPE_CONF_CHECK_X(output_types); 5197 5198 PIPE_CONF_CHECK_I(framestart_delay); 5199 PIPE_CONF_CHECK_I(msa_timing_delay); 5200 5201 PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode); 5202 PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode); 5203 5204 PIPE_CONF_CHECK_I(pixel_multiplier); 5205 5206 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5207 DRM_MODE_FLAG_INTERLACE); 5208 5209 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { 5210 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5211 DRM_MODE_FLAG_PHSYNC); 5212 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5213 DRM_MODE_FLAG_NHSYNC); 5214 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5215 DRM_MODE_FLAG_PVSYNC); 5216 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5217 DRM_MODE_FLAG_NVSYNC); 5218 } 5219 5220 PIPE_CONF_CHECK_I(output_format); 5221 PIPE_CONF_CHECK_BOOL(has_hdmi_sink); 5222 if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || 5223 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5224 PIPE_CONF_CHECK_BOOL(limited_color_range); 5225 5226 PIPE_CONF_CHECK_BOOL(hdmi_scrambling); 5227 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio); 5228 PIPE_CONF_CHECK_BOOL(has_infoframe); 5229 PIPE_CONF_CHECK_BOOL(fec_enable); 5230 5231 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio); 5232 PIPE_CONF_CHECK_BUFFER(eld, MAX_ELD_BYTES); 5233 5234 PIPE_CONF_CHECK_X(gmch_pfit.control); 5235 /* pfit ratios are autocomputed by the hw on gen4+ */ 5236 if (DISPLAY_VER(dev_priv) < 4) 5237 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); 5238 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); 5239 5240 /* 5241 * Changing the EDP transcoder input mux 5242 * (A_ONOFF vs. A_ON) requires a full modeset. 5243 */ 5244 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru); 5245 5246 if (!fastset) { 5247 PIPE_CONF_CHECK_RECT(pipe_src); 5248 5249 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled); 5250 PIPE_CONF_CHECK_RECT(pch_pfit.dst); 5251 5252 PIPE_CONF_CHECK_I(scaler_state.scaler_id); 5253 PIPE_CONF_CHECK_I(pixel_rate); 5254 5255 PIPE_CONF_CHECK_X(gamma_mode); 5256 if (IS_CHERRYVIEW(dev_priv)) 5257 PIPE_CONF_CHECK_X(cgm_mode); 5258 else 5259 PIPE_CONF_CHECK_X(csc_mode); 5260 PIPE_CONF_CHECK_BOOL(gamma_enable); 5261 PIPE_CONF_CHECK_BOOL(csc_enable); 5262 5263 PIPE_CONF_CHECK_I(linetime); 5264 PIPE_CONF_CHECK_I(ips_linetime); 5265 5266 PIPE_CONF_CHECK_COLOR_LUT(pre_csc_lut, true); 5267 PIPE_CONF_CHECK_COLOR_LUT(post_csc_lut, false); 5268 5269 PIPE_CONF_CHECK_CSC(csc); 5270 PIPE_CONF_CHECK_CSC(output_csc); 5271 5272 if (current_config->active_planes) { 5273 PIPE_CONF_CHECK_BOOL(has_psr); 5274 PIPE_CONF_CHECK_BOOL(has_psr2); 5275 PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); 5276 PIPE_CONF_CHECK_I(dc3co_exitline); 5277 } 5278 } 5279 5280 PIPE_CONF_CHECK_BOOL(double_wide); 5281 5282 if (dev_priv->display.dpll.mgr) { 5283 PIPE_CONF_CHECK_P(shared_dpll); 5284 5285 PIPE_CONF_CHECK_X(dpll_hw_state.dpll); 5286 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); 5287 PIPE_CONF_CHECK_X(dpll_hw_state.fp0); 5288 PIPE_CONF_CHECK_X(dpll_hw_state.fp1); 5289 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); 5290 PIPE_CONF_CHECK_X(dpll_hw_state.spll); 5291 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); 5292 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); 5293 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); 5294 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); 5295 PIPE_CONF_CHECK_X(dpll_hw_state.div0); 5296 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); 5297 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); 5298 PIPE_CONF_CHECK_X(dpll_hw_state.pll0); 5299 PIPE_CONF_CHECK_X(dpll_hw_state.pll1); 5300 PIPE_CONF_CHECK_X(dpll_hw_state.pll2); 5301 PIPE_CONF_CHECK_X(dpll_hw_state.pll3); 5302 PIPE_CONF_CHECK_X(dpll_hw_state.pll6); 5303 PIPE_CONF_CHECK_X(dpll_hw_state.pll8); 5304 PIPE_CONF_CHECK_X(dpll_hw_state.pll9); 5305 PIPE_CONF_CHECK_X(dpll_hw_state.pll10); 5306 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); 5307 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl); 5308 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1); 5309 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl); 5310 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0); 5311 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1); 5312 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf); 5313 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock); 5314 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc); 5315 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias); 5316 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias); 5317 } 5318 5319 PIPE_CONF_CHECK_X(dsi_pll.ctrl); 5320 PIPE_CONF_CHECK_X(dsi_pll.div); 5321 5322 if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5) 5323 PIPE_CONF_CHECK_I(pipe_bpp); 5324 5325 if (!fastset || !pipe_config->seamless_m_n) { 5326 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock); 5327 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock); 5328 } 5329 PIPE_CONF_CHECK_I(port_clock); 5330 5331 PIPE_CONF_CHECK_I(min_voltage_level); 5332 5333 if (current_config->has_psr || pipe_config->has_psr) 5334 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable, 5335 ~intel_hdmi_infoframe_enable(DP_SDP_VSC)); 5336 else 5337 PIPE_CONF_CHECK_X(infoframes.enable); 5338 5339 PIPE_CONF_CHECK_X(infoframes.gcp); 5340 PIPE_CONF_CHECK_INFOFRAME(avi); 5341 PIPE_CONF_CHECK_INFOFRAME(spd); 5342 PIPE_CONF_CHECK_INFOFRAME(hdmi); 5343 PIPE_CONF_CHECK_INFOFRAME(drm); 5344 PIPE_CONF_CHECK_DP_VSC_SDP(vsc); 5345 5346 PIPE_CONF_CHECK_X(sync_mode_slaves_mask); 5347 PIPE_CONF_CHECK_I(master_transcoder); 5348 PIPE_CONF_CHECK_X(bigjoiner_pipes); 5349 5350 PIPE_CONF_CHECK_I(dsc.compression_enable); 5351 PIPE_CONF_CHECK_I(dsc.dsc_split); 5352 PIPE_CONF_CHECK_I(dsc.compressed_bpp); 5353 5354 PIPE_CONF_CHECK_BOOL(splitter.enable); 5355 PIPE_CONF_CHECK_I(splitter.link_count); 5356 PIPE_CONF_CHECK_I(splitter.pixel_overlap); 5357 5358 if (!fastset) 5359 PIPE_CONF_CHECK_BOOL(vrr.enable); 5360 PIPE_CONF_CHECK_I(vrr.vmin); 5361 PIPE_CONF_CHECK_I(vrr.vmax); 5362 PIPE_CONF_CHECK_I(vrr.flipline); 5363 PIPE_CONF_CHECK_I(vrr.pipeline_full); 5364 PIPE_CONF_CHECK_I(vrr.guardband); 5365 5366 #undef PIPE_CONF_CHECK_X 5367 #undef PIPE_CONF_CHECK_I 5368 #undef PIPE_CONF_CHECK_BOOL 5369 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE 5370 #undef PIPE_CONF_CHECK_P 5371 #undef PIPE_CONF_CHECK_FLAGS 5372 #undef PIPE_CONF_CHECK_COLOR_LUT 5373 #undef PIPE_CONF_CHECK_TIMINGS 5374 #undef PIPE_CONF_CHECK_RECT 5375 #undef PIPE_CONF_QUIRK 5376 5377 return ret; 5378 } 5379 5380 static void 5381 intel_verify_planes(struct intel_atomic_state *state) 5382 { 5383 struct intel_plane *plane; 5384 const struct intel_plane_state *plane_state; 5385 int i; 5386 5387 for_each_new_intel_plane_in_state(state, plane, 5388 plane_state, i) 5389 assert_plane(plane, plane_state->planar_slave || 5390 plane_state->uapi.visible); 5391 } 5392 5393 int intel_modeset_all_pipes(struct intel_atomic_state *state, 5394 const char *reason) 5395 { 5396 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 5397 struct intel_crtc *crtc; 5398 5399 /* 5400 * Add all pipes to the state, and force 5401 * a modeset on all the active ones. 5402 */ 5403 for_each_intel_crtc(&dev_priv->drm, crtc) { 5404 struct intel_crtc_state *crtc_state; 5405 int ret; 5406 5407 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 5408 if (IS_ERR(crtc_state)) 5409 return PTR_ERR(crtc_state); 5410 5411 if (!crtc_state->hw.active || 5412 intel_crtc_needs_modeset(crtc_state)) 5413 continue; 5414 5415 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] Full modeset due to %s\n", 5416 crtc->base.base.id, crtc->base.name, reason); 5417 5418 crtc_state->uapi.mode_changed = true; 5419 crtc_state->update_pipe = false; 5420 5421 ret = drm_atomic_add_affected_connectors(&state->base, 5422 &crtc->base); 5423 if (ret) 5424 return ret; 5425 5426 ret = intel_dp_mst_add_topology_state_for_crtc(state, crtc); 5427 if (ret) 5428 return ret; 5429 5430 ret = intel_atomic_add_affected_planes(state, crtc); 5431 if (ret) 5432 return ret; 5433 5434 crtc_state->update_planes |= crtc_state->active_planes; 5435 crtc_state->async_flip_planes = 0; 5436 crtc_state->do_async_flip = false; 5437 } 5438 5439 return 0; 5440 } 5441 5442 /* 5443 * This implements the workaround described in the "notes" section of the mode 5444 * set sequence documentation. When going from no pipes or single pipe to 5445 * multiple pipes, and planes are enabled after the pipe, we need to wait at 5446 * least 2 vblanks on the first pipe before enabling planes on the second pipe. 5447 */ 5448 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state) 5449 { 5450 struct intel_crtc_state *crtc_state; 5451 struct intel_crtc *crtc; 5452 struct intel_crtc_state *first_crtc_state = NULL; 5453 struct intel_crtc_state *other_crtc_state = NULL; 5454 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; 5455 int i; 5456 5457 /* look at all crtc's that are going to be enabled in during modeset */ 5458 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5459 if (!crtc_state->hw.active || 5460 !intel_crtc_needs_modeset(crtc_state)) 5461 continue; 5462 5463 if (first_crtc_state) { 5464 other_crtc_state = crtc_state; 5465 break; 5466 } else { 5467 first_crtc_state = crtc_state; 5468 first_pipe = crtc->pipe; 5469 } 5470 } 5471 5472 /* No workaround needed? */ 5473 if (!first_crtc_state) 5474 return 0; 5475 5476 /* w/a possibly needed, check how many crtc's are already enabled. */ 5477 for_each_intel_crtc(state->base.dev, crtc) { 5478 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 5479 if (IS_ERR(crtc_state)) 5480 return PTR_ERR(crtc_state); 5481 5482 crtc_state->hsw_workaround_pipe = INVALID_PIPE; 5483 5484 if (!crtc_state->hw.active || 5485 intel_crtc_needs_modeset(crtc_state)) 5486 continue; 5487 5488 /* 2 or more enabled crtcs means no need for w/a */ 5489 if (enabled_pipe != INVALID_PIPE) 5490 return 0; 5491 5492 enabled_pipe = crtc->pipe; 5493 } 5494 5495 if (enabled_pipe != INVALID_PIPE) 5496 first_crtc_state->hsw_workaround_pipe = enabled_pipe; 5497 else if (other_crtc_state) 5498 other_crtc_state->hsw_workaround_pipe = first_pipe; 5499 5500 return 0; 5501 } 5502 5503 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 5504 u8 active_pipes) 5505 { 5506 const struct intel_crtc_state *crtc_state; 5507 struct intel_crtc *crtc; 5508 int i; 5509 5510 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5511 if (crtc_state->hw.active) 5512 active_pipes |= BIT(crtc->pipe); 5513 else 5514 active_pipes &= ~BIT(crtc->pipe); 5515 } 5516 5517 return active_pipes; 5518 } 5519 5520 static int intel_modeset_checks(struct intel_atomic_state *state) 5521 { 5522 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 5523 5524 state->modeset = true; 5525 5526 if (IS_HASWELL(dev_priv)) 5527 return hsw_mode_set_planes_workaround(state); 5528 5529 return 0; 5530 } 5531 5532 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state, 5533 struct intel_crtc_state *new_crtc_state) 5534 { 5535 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) 5536 return; 5537 5538 new_crtc_state->uapi.mode_changed = false; 5539 if (!intel_crtc_needs_modeset(new_crtc_state)) 5540 new_crtc_state->update_pipe = true; 5541 } 5542 5543 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state, 5544 struct intel_crtc *crtc, 5545 u8 plane_ids_mask) 5546 { 5547 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 5548 struct intel_plane *plane; 5549 5550 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 5551 struct intel_plane_state *plane_state; 5552 5553 if ((plane_ids_mask & BIT(plane->id)) == 0) 5554 continue; 5555 5556 plane_state = intel_atomic_get_plane_state(state, plane); 5557 if (IS_ERR(plane_state)) 5558 return PTR_ERR(plane_state); 5559 } 5560 5561 return 0; 5562 } 5563 5564 int intel_atomic_add_affected_planes(struct intel_atomic_state *state, 5565 struct intel_crtc *crtc) 5566 { 5567 const struct intel_crtc_state *old_crtc_state = 5568 intel_atomic_get_old_crtc_state(state, crtc); 5569 const struct intel_crtc_state *new_crtc_state = 5570 intel_atomic_get_new_crtc_state(state, crtc); 5571 5572 return intel_crtc_add_planes_to_state(state, crtc, 5573 old_crtc_state->enabled_planes | 5574 new_crtc_state->enabled_planes); 5575 } 5576 5577 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv) 5578 { 5579 /* See {hsw,vlv,ivb}_plane_ratio() */ 5580 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) || 5581 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) || 5582 IS_IVYBRIDGE(dev_priv); 5583 } 5584 5585 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state, 5586 struct intel_crtc *crtc, 5587 struct intel_crtc *other) 5588 { 5589 const struct intel_plane_state *plane_state; 5590 struct intel_plane *plane; 5591 u8 plane_ids = 0; 5592 int i; 5593 5594 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 5595 if (plane->pipe == crtc->pipe) 5596 plane_ids |= BIT(plane->id); 5597 } 5598 5599 return intel_crtc_add_planes_to_state(state, other, plane_ids); 5600 } 5601 5602 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state) 5603 { 5604 struct drm_i915_private *i915 = to_i915(state->base.dev); 5605 const struct intel_crtc_state *crtc_state; 5606 struct intel_crtc *crtc; 5607 int i; 5608 5609 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5610 struct intel_crtc *other; 5611 5612 for_each_intel_crtc_in_pipe_mask(&i915->drm, other, 5613 crtc_state->bigjoiner_pipes) { 5614 int ret; 5615 5616 if (crtc == other) 5617 continue; 5618 5619 ret = intel_crtc_add_bigjoiner_planes(state, crtc, other); 5620 if (ret) 5621 return ret; 5622 } 5623 } 5624 5625 return 0; 5626 } 5627 5628 static int intel_atomic_check_planes(struct intel_atomic_state *state) 5629 { 5630 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 5631 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 5632 struct intel_plane_state *plane_state; 5633 struct intel_plane *plane; 5634 struct intel_crtc *crtc; 5635 int i, ret; 5636 5637 ret = icl_add_linked_planes(state); 5638 if (ret) 5639 return ret; 5640 5641 ret = intel_bigjoiner_add_affected_planes(state); 5642 if (ret) 5643 return ret; 5644 5645 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 5646 ret = intel_plane_atomic_check(state, plane); 5647 if (ret) { 5648 drm_dbg_atomic(&dev_priv->drm, 5649 "[PLANE:%d:%s] atomic driver check failed\n", 5650 plane->base.base.id, plane->base.name); 5651 return ret; 5652 } 5653 } 5654 5655 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 5656 new_crtc_state, i) { 5657 u8 old_active_planes, new_active_planes; 5658 5659 ret = icl_check_nv12_planes(new_crtc_state); 5660 if (ret) 5661 return ret; 5662 5663 /* 5664 * On some platforms the number of active planes affects 5665 * the planes' minimum cdclk calculation. Add such planes 5666 * to the state before we compute the minimum cdclk. 5667 */ 5668 if (!active_planes_affects_min_cdclk(dev_priv)) 5669 continue; 5670 5671 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 5672 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 5673 5674 if (hweight8(old_active_planes) == hweight8(new_active_planes)) 5675 continue; 5676 5677 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes); 5678 if (ret) 5679 return ret; 5680 } 5681 5682 return 0; 5683 } 5684 5685 static int intel_atomic_check_crtcs(struct intel_atomic_state *state) 5686 { 5687 struct intel_crtc_state *crtc_state; 5688 struct intel_crtc *crtc; 5689 int i; 5690 5691 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5692 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 5693 int ret; 5694 5695 ret = intel_crtc_atomic_check(state, crtc); 5696 if (ret) { 5697 drm_dbg_atomic(&i915->drm, 5698 "[CRTC:%d:%s] atomic driver check failed\n", 5699 crtc->base.base.id, crtc->base.name); 5700 return ret; 5701 } 5702 } 5703 5704 return 0; 5705 } 5706 5707 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, 5708 u8 transcoders) 5709 { 5710 const struct intel_crtc_state *new_crtc_state; 5711 struct intel_crtc *crtc; 5712 int i; 5713 5714 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 5715 if (new_crtc_state->hw.enable && 5716 transcoders & BIT(new_crtc_state->cpu_transcoder) && 5717 intel_crtc_needs_modeset(new_crtc_state)) 5718 return true; 5719 } 5720 5721 return false; 5722 } 5723 5724 static bool intel_pipes_need_modeset(struct intel_atomic_state *state, 5725 u8 pipes) 5726 { 5727 const struct intel_crtc_state *new_crtc_state; 5728 struct intel_crtc *crtc; 5729 int i; 5730 5731 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 5732 if (new_crtc_state->hw.enable && 5733 pipes & BIT(crtc->pipe) && 5734 intel_crtc_needs_modeset(new_crtc_state)) 5735 return true; 5736 } 5737 5738 return false; 5739 } 5740 5741 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state, 5742 struct intel_crtc *master_crtc) 5743 { 5744 struct drm_i915_private *i915 = to_i915(state->base.dev); 5745 struct intel_crtc_state *master_crtc_state = 5746 intel_atomic_get_new_crtc_state(state, master_crtc); 5747 struct intel_crtc *slave_crtc; 5748 5749 if (!master_crtc_state->bigjoiner_pipes) 5750 return 0; 5751 5752 /* sanity check */ 5753 if (drm_WARN_ON(&i915->drm, 5754 master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state))) 5755 return -EINVAL; 5756 5757 if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) { 5758 drm_dbg_kms(&i915->drm, 5759 "[CRTC:%d:%s] Cannot act as big joiner master " 5760 "(need 0x%x as pipes, only 0x%x possible)\n", 5761 master_crtc->base.base.id, master_crtc->base.name, 5762 master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915)); 5763 return -EINVAL; 5764 } 5765 5766 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 5767 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 5768 struct intel_crtc_state *slave_crtc_state; 5769 int ret; 5770 5771 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc); 5772 if (IS_ERR(slave_crtc_state)) 5773 return PTR_ERR(slave_crtc_state); 5774 5775 /* master being enabled, slave was already configured? */ 5776 if (slave_crtc_state->uapi.enable) { 5777 drm_dbg_kms(&i915->drm, 5778 "[CRTC:%d:%s] Slave is enabled as normal CRTC, but " 5779 "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n", 5780 slave_crtc->base.base.id, slave_crtc->base.name, 5781 master_crtc->base.base.id, master_crtc->base.name); 5782 return -EINVAL; 5783 } 5784 5785 /* 5786 * The state copy logic assumes the master crtc gets processed 5787 * before the slave crtc during the main compute_config loop. 5788 * This works because the crtcs are created in pipe order, 5789 * and the hardware requires master pipe < slave pipe as well. 5790 * Should that change we need to rethink the logic. 5791 */ 5792 if (WARN_ON(drm_crtc_index(&master_crtc->base) > 5793 drm_crtc_index(&slave_crtc->base))) 5794 return -EINVAL; 5795 5796 drm_dbg_kms(&i915->drm, 5797 "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n", 5798 slave_crtc->base.base.id, slave_crtc->base.name, 5799 master_crtc->base.base.id, master_crtc->base.name); 5800 5801 slave_crtc_state->bigjoiner_pipes = 5802 master_crtc_state->bigjoiner_pipes; 5803 5804 ret = copy_bigjoiner_crtc_state_modeset(state, slave_crtc); 5805 if (ret) 5806 return ret; 5807 } 5808 5809 return 0; 5810 } 5811 5812 static void kill_bigjoiner_slave(struct intel_atomic_state *state, 5813 struct intel_crtc *master_crtc) 5814 { 5815 struct drm_i915_private *i915 = to_i915(state->base.dev); 5816 struct intel_crtc_state *master_crtc_state = 5817 intel_atomic_get_new_crtc_state(state, master_crtc); 5818 struct intel_crtc *slave_crtc; 5819 5820 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 5821 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 5822 struct intel_crtc_state *slave_crtc_state = 5823 intel_atomic_get_new_crtc_state(state, slave_crtc); 5824 5825 slave_crtc_state->bigjoiner_pipes = 0; 5826 5827 intel_crtc_copy_uapi_to_hw_state_modeset(state, slave_crtc); 5828 } 5829 5830 master_crtc_state->bigjoiner_pipes = 0; 5831 } 5832 5833 /** 5834 * DOC: asynchronous flip implementation 5835 * 5836 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC 5837 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL. 5838 * Correspondingly, support is currently added for primary plane only. 5839 * 5840 * Async flip can only change the plane surface address, so anything else 5841 * changing is rejected from the intel_async_flip_check_hw() function. 5842 * Once this check is cleared, flip done interrupt is enabled using 5843 * the intel_crtc_enable_flip_done() function. 5844 * 5845 * As soon as the surface address register is written, flip done interrupt is 5846 * generated and the requested events are sent to the usersapce in the interrupt 5847 * handler itself. The timestamp and sequence sent during the flip done event 5848 * correspond to the last vblank and have no relation to the actual time when 5849 * the flip done event was sent. 5850 */ 5851 static int intel_async_flip_check_uapi(struct intel_atomic_state *state, 5852 struct intel_crtc *crtc) 5853 { 5854 struct drm_i915_private *i915 = to_i915(state->base.dev); 5855 const struct intel_crtc_state *new_crtc_state = 5856 intel_atomic_get_new_crtc_state(state, crtc); 5857 const struct intel_plane_state *old_plane_state; 5858 struct intel_plane_state *new_plane_state; 5859 struct intel_plane *plane; 5860 int i; 5861 5862 if (!new_crtc_state->uapi.async_flip) 5863 return 0; 5864 5865 if (!new_crtc_state->uapi.active) { 5866 drm_dbg_kms(&i915->drm, 5867 "[CRTC:%d:%s] not active\n", 5868 crtc->base.base.id, crtc->base.name); 5869 return -EINVAL; 5870 } 5871 5872 if (intel_crtc_needs_modeset(new_crtc_state)) { 5873 drm_dbg_kms(&i915->drm, 5874 "[CRTC:%d:%s] modeset required\n", 5875 crtc->base.base.id, crtc->base.name); 5876 return -EINVAL; 5877 } 5878 5879 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 5880 new_plane_state, i) { 5881 if (plane->pipe != crtc->pipe) 5882 continue; 5883 5884 /* 5885 * TODO: Async flip is only supported through the page flip IOCTL 5886 * as of now. So support currently added for primary plane only. 5887 * Support for other planes on platforms on which supports 5888 * this(vlv/chv and icl+) should be added when async flip is 5889 * enabled in the atomic IOCTL path. 5890 */ 5891 if (!plane->async_flip) { 5892 drm_dbg_kms(&i915->drm, 5893 "[PLANE:%d:%s] async flip not supported\n", 5894 plane->base.base.id, plane->base.name); 5895 return -EINVAL; 5896 } 5897 5898 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) { 5899 drm_dbg_kms(&i915->drm, 5900 "[PLANE:%d:%s] no old or new framebuffer\n", 5901 plane->base.base.id, plane->base.name); 5902 return -EINVAL; 5903 } 5904 } 5905 5906 return 0; 5907 } 5908 5909 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc) 5910 { 5911 struct drm_i915_private *i915 = to_i915(state->base.dev); 5912 const struct intel_crtc_state *old_crtc_state, *new_crtc_state; 5913 const struct intel_plane_state *new_plane_state, *old_plane_state; 5914 struct intel_plane *plane; 5915 int i; 5916 5917 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 5918 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 5919 5920 if (!new_crtc_state->uapi.async_flip) 5921 return 0; 5922 5923 if (!new_crtc_state->hw.active) { 5924 drm_dbg_kms(&i915->drm, 5925 "[CRTC:%d:%s] not active\n", 5926 crtc->base.base.id, crtc->base.name); 5927 return -EINVAL; 5928 } 5929 5930 if (intel_crtc_needs_modeset(new_crtc_state)) { 5931 drm_dbg_kms(&i915->drm, 5932 "[CRTC:%d:%s] modeset required\n", 5933 crtc->base.base.id, crtc->base.name); 5934 return -EINVAL; 5935 } 5936 5937 if (old_crtc_state->active_planes != new_crtc_state->active_planes) { 5938 drm_dbg_kms(&i915->drm, 5939 "[CRTC:%d:%s] Active planes cannot be in async flip\n", 5940 crtc->base.base.id, crtc->base.name); 5941 return -EINVAL; 5942 } 5943 5944 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 5945 new_plane_state, i) { 5946 if (plane->pipe != crtc->pipe) 5947 continue; 5948 5949 /* 5950 * Only async flip capable planes should be in the state 5951 * if we're really about to ask the hardware to perform 5952 * an async flip. We should never get this far otherwise. 5953 */ 5954 if (drm_WARN_ON(&i915->drm, 5955 new_crtc_state->do_async_flip && !plane->async_flip)) 5956 return -EINVAL; 5957 5958 /* 5959 * Only check async flip capable planes other planes 5960 * may be involved in the initial commit due to 5961 * the wm0/ddb optimization. 5962 * 5963 * TODO maybe should track which planes actually 5964 * were requested to do the async flip... 5965 */ 5966 if (!plane->async_flip) 5967 continue; 5968 5969 /* 5970 * FIXME: This check is kept generic for all platforms. 5971 * Need to verify this for all gen9 platforms to enable 5972 * this selectively if required. 5973 */ 5974 switch (new_plane_state->hw.fb->modifier) { 5975 case I915_FORMAT_MOD_X_TILED: 5976 case I915_FORMAT_MOD_Y_TILED: 5977 case I915_FORMAT_MOD_Yf_TILED: 5978 case I915_FORMAT_MOD_4_TILED: 5979 break; 5980 default: 5981 drm_dbg_kms(&i915->drm, 5982 "[PLANE:%d:%s] Modifier does not support async flips\n", 5983 plane->base.base.id, plane->base.name); 5984 return -EINVAL; 5985 } 5986 5987 if (new_plane_state->hw.fb->format->num_planes > 1) { 5988 drm_dbg_kms(&i915->drm, 5989 "[PLANE:%d:%s] Planar formats do not support async flips\n", 5990 plane->base.base.id, plane->base.name); 5991 return -EINVAL; 5992 } 5993 5994 if (old_plane_state->view.color_plane[0].mapping_stride != 5995 new_plane_state->view.color_plane[0].mapping_stride) { 5996 drm_dbg_kms(&i915->drm, 5997 "[PLANE:%d:%s] Stride cannot be changed in async flip\n", 5998 plane->base.base.id, plane->base.name); 5999 return -EINVAL; 6000 } 6001 6002 if (old_plane_state->hw.fb->modifier != 6003 new_plane_state->hw.fb->modifier) { 6004 drm_dbg_kms(&i915->drm, 6005 "[PLANE:%d:%s] Modifier cannot be changed in async flip\n", 6006 plane->base.base.id, plane->base.name); 6007 return -EINVAL; 6008 } 6009 6010 if (old_plane_state->hw.fb->format != 6011 new_plane_state->hw.fb->format) { 6012 drm_dbg_kms(&i915->drm, 6013 "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n", 6014 plane->base.base.id, plane->base.name); 6015 return -EINVAL; 6016 } 6017 6018 if (old_plane_state->hw.rotation != 6019 new_plane_state->hw.rotation) { 6020 drm_dbg_kms(&i915->drm, 6021 "[PLANE:%d:%s] Rotation cannot be changed in async flip\n", 6022 plane->base.base.id, plane->base.name); 6023 return -EINVAL; 6024 } 6025 6026 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) || 6027 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) { 6028 drm_dbg_kms(&i915->drm, 6029 "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n", 6030 plane->base.base.id, plane->base.name); 6031 return -EINVAL; 6032 } 6033 6034 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) { 6035 drm_dbg_kms(&i915->drm, 6036 "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n", 6037 plane->base.base.id, plane->base.name); 6038 return -EINVAL; 6039 } 6040 6041 if (old_plane_state->hw.pixel_blend_mode != 6042 new_plane_state->hw.pixel_blend_mode) { 6043 drm_dbg_kms(&i915->drm, 6044 "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n", 6045 plane->base.base.id, plane->base.name); 6046 return -EINVAL; 6047 } 6048 6049 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) { 6050 drm_dbg_kms(&i915->drm, 6051 "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n", 6052 plane->base.base.id, plane->base.name); 6053 return -EINVAL; 6054 } 6055 6056 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) { 6057 drm_dbg_kms(&i915->drm, 6058 "[PLANE:%d:%s] Color range cannot be changed in async flip\n", 6059 plane->base.base.id, plane->base.name); 6060 return -EINVAL; 6061 } 6062 6063 /* plane decryption is allow to change only in synchronous flips */ 6064 if (old_plane_state->decrypt != new_plane_state->decrypt) { 6065 drm_dbg_kms(&i915->drm, 6066 "[PLANE:%d:%s] Decryption cannot be changed in async flip\n", 6067 plane->base.base.id, plane->base.name); 6068 return -EINVAL; 6069 } 6070 } 6071 6072 return 0; 6073 } 6074 6075 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state) 6076 { 6077 struct drm_i915_private *i915 = to_i915(state->base.dev); 6078 struct intel_crtc_state *crtc_state; 6079 struct intel_crtc *crtc; 6080 u8 affected_pipes = 0; 6081 u8 modeset_pipes = 0; 6082 int i; 6083 6084 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6085 affected_pipes |= crtc_state->bigjoiner_pipes; 6086 if (intel_crtc_needs_modeset(crtc_state)) 6087 modeset_pipes |= crtc_state->bigjoiner_pipes; 6088 } 6089 6090 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) { 6091 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6092 if (IS_ERR(crtc_state)) 6093 return PTR_ERR(crtc_state); 6094 } 6095 6096 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) { 6097 int ret; 6098 6099 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6100 6101 crtc_state->uapi.mode_changed = true; 6102 6103 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); 6104 if (ret) 6105 return ret; 6106 6107 ret = intel_atomic_add_affected_planes(state, crtc); 6108 if (ret) 6109 return ret; 6110 } 6111 6112 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6113 /* Kill old bigjoiner link, we may re-establish afterwards */ 6114 if (intel_crtc_needs_modeset(crtc_state) && 6115 intel_crtc_is_bigjoiner_master(crtc_state)) 6116 kill_bigjoiner_slave(state, crtc); 6117 } 6118 6119 return 0; 6120 } 6121 6122 /** 6123 * intel_atomic_check - validate state object 6124 * @dev: drm device 6125 * @_state: state to validate 6126 */ 6127 int intel_atomic_check(struct drm_device *dev, 6128 struct drm_atomic_state *_state) 6129 { 6130 struct drm_i915_private *dev_priv = to_i915(dev); 6131 struct intel_atomic_state *state = to_intel_atomic_state(_state); 6132 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6133 struct intel_crtc *crtc; 6134 int ret, i; 6135 bool any_ms = false; 6136 6137 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6138 new_crtc_state, i) { 6139 /* 6140 * crtc's state no longer considered to be inherited 6141 * after the first userspace/client initiated commit. 6142 */ 6143 if (!state->internal) 6144 new_crtc_state->inherited = false; 6145 6146 if (new_crtc_state->inherited != old_crtc_state->inherited) 6147 new_crtc_state->uapi.mode_changed = true; 6148 6149 if (new_crtc_state->uapi.scaling_filter != 6150 old_crtc_state->uapi.scaling_filter) 6151 new_crtc_state->uapi.mode_changed = true; 6152 } 6153 6154 intel_vrr_check_modeset(state); 6155 6156 ret = drm_atomic_helper_check_modeset(dev, &state->base); 6157 if (ret) 6158 goto fail; 6159 6160 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6161 ret = intel_async_flip_check_uapi(state, crtc); 6162 if (ret) 6163 return ret; 6164 } 6165 6166 ret = intel_bigjoiner_add_affected_crtcs(state); 6167 if (ret) 6168 goto fail; 6169 6170 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6171 new_crtc_state, i) { 6172 if (!intel_crtc_needs_modeset(new_crtc_state)) { 6173 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 6174 copy_bigjoiner_crtc_state_nomodeset(state, crtc); 6175 else 6176 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 6177 continue; 6178 } 6179 6180 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) { 6181 drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable); 6182 continue; 6183 } 6184 6185 ret = intel_crtc_prepare_cleared_state(state, crtc); 6186 if (ret) 6187 goto fail; 6188 6189 if (!new_crtc_state->hw.enable) 6190 continue; 6191 6192 ret = intel_modeset_pipe_config(state, crtc); 6193 if (ret) 6194 goto fail; 6195 6196 ret = intel_atomic_check_bigjoiner(state, crtc); 6197 if (ret) 6198 goto fail; 6199 } 6200 6201 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6202 new_crtc_state, i) { 6203 if (!intel_crtc_needs_modeset(new_crtc_state)) 6204 continue; 6205 6206 if (new_crtc_state->hw.enable) { 6207 ret = intel_modeset_pipe_config_late(state, crtc); 6208 if (ret) 6209 goto fail; 6210 } 6211 6212 intel_crtc_check_fastset(old_crtc_state, new_crtc_state); 6213 } 6214 6215 /** 6216 * Check if fastset is allowed by external dependencies like other 6217 * pipes and transcoders. 6218 * 6219 * Right now it only forces a fullmodeset when the MST master 6220 * transcoder did not changed but the pipe of the master transcoder 6221 * needs a fullmodeset so all slaves also needs to do a fullmodeset or 6222 * in case of port synced crtcs, if one of the synced crtcs 6223 * needs a full modeset, all other synced crtcs should be 6224 * forced a full modeset. 6225 */ 6226 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6227 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state)) 6228 continue; 6229 6230 if (intel_dp_mst_is_slave_trans(new_crtc_state)) { 6231 enum transcoder master = new_crtc_state->mst_master_transcoder; 6232 6233 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) { 6234 new_crtc_state->uapi.mode_changed = true; 6235 new_crtc_state->update_pipe = false; 6236 } 6237 } 6238 6239 if (is_trans_port_sync_mode(new_crtc_state)) { 6240 u8 trans = new_crtc_state->sync_mode_slaves_mask; 6241 6242 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER) 6243 trans |= BIT(new_crtc_state->master_transcoder); 6244 6245 if (intel_cpu_transcoders_need_modeset(state, trans)) { 6246 new_crtc_state->uapi.mode_changed = true; 6247 new_crtc_state->update_pipe = false; 6248 } 6249 } 6250 6251 if (new_crtc_state->bigjoiner_pipes) { 6252 if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) { 6253 new_crtc_state->uapi.mode_changed = true; 6254 new_crtc_state->update_pipe = false; 6255 } 6256 } 6257 } 6258 6259 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6260 new_crtc_state, i) { 6261 if (!intel_crtc_needs_modeset(new_crtc_state)) 6262 continue; 6263 6264 any_ms = true; 6265 6266 intel_release_shared_dplls(state, crtc); 6267 } 6268 6269 if (any_ms && !check_digital_port_conflicts(state)) { 6270 drm_dbg_kms(&dev_priv->drm, 6271 "rejecting conflicting digital port configuration\n"); 6272 ret = -EINVAL; 6273 goto fail; 6274 } 6275 6276 ret = drm_dp_mst_atomic_check(&state->base); 6277 if (ret) 6278 goto fail; 6279 6280 ret = intel_atomic_check_planes(state); 6281 if (ret) 6282 goto fail; 6283 6284 ret = intel_compute_global_watermarks(state); 6285 if (ret) 6286 goto fail; 6287 6288 ret = intel_bw_atomic_check(state); 6289 if (ret) 6290 goto fail; 6291 6292 ret = intel_cdclk_atomic_check(state, &any_ms); 6293 if (ret) 6294 goto fail; 6295 6296 if (intel_any_crtc_needs_modeset(state)) 6297 any_ms = true; 6298 6299 if (any_ms) { 6300 ret = intel_modeset_checks(state); 6301 if (ret) 6302 goto fail; 6303 6304 ret = intel_modeset_calc_cdclk(state); 6305 if (ret) 6306 return ret; 6307 } 6308 6309 ret = intel_atomic_check_crtcs(state); 6310 if (ret) 6311 goto fail; 6312 6313 ret = intel_fbc_atomic_check(state); 6314 if (ret) 6315 goto fail; 6316 6317 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6318 new_crtc_state, i) { 6319 intel_color_assert_luts(new_crtc_state); 6320 6321 ret = intel_async_flip_check_hw(state, crtc); 6322 if (ret) 6323 goto fail; 6324 6325 /* Either full modeset or fastset (or neither), never both */ 6326 drm_WARN_ON(&dev_priv->drm, 6327 intel_crtc_needs_modeset(new_crtc_state) && 6328 intel_crtc_needs_fastset(new_crtc_state)); 6329 6330 if (!intel_crtc_needs_modeset(new_crtc_state) && 6331 !intel_crtc_needs_fastset(new_crtc_state)) 6332 continue; 6333 6334 intel_crtc_state_dump(new_crtc_state, state, 6335 intel_crtc_needs_modeset(new_crtc_state) ? 6336 "modeset" : "fastset"); 6337 } 6338 6339 return 0; 6340 6341 fail: 6342 if (ret == -EDEADLK) 6343 return ret; 6344 6345 /* 6346 * FIXME would probably be nice to know which crtc specifically 6347 * caused the failure, in cases where we can pinpoint it. 6348 */ 6349 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6350 new_crtc_state, i) 6351 intel_crtc_state_dump(new_crtc_state, state, "failed"); 6352 6353 return ret; 6354 } 6355 6356 static int intel_atomic_prepare_commit(struct intel_atomic_state *state) 6357 { 6358 struct intel_crtc_state *crtc_state; 6359 struct intel_crtc *crtc; 6360 int i, ret; 6361 6362 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base); 6363 if (ret < 0) 6364 return ret; 6365 6366 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6367 if (intel_crtc_needs_color_update(crtc_state)) 6368 intel_color_prepare_commit(crtc_state); 6369 } 6370 6371 return 0; 6372 } 6373 6374 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 6375 struct intel_crtc_state *crtc_state) 6376 { 6377 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6378 6379 if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes) 6380 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 6381 6382 if (crtc_state->has_pch_encoder) { 6383 enum pipe pch_transcoder = 6384 intel_crtc_pch_transcoder(crtc); 6385 6386 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true); 6387 } 6388 } 6389 6390 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, 6391 const struct intel_crtc_state *new_crtc_state) 6392 { 6393 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 6394 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6395 6396 /* 6397 * Update pipe size and adjust fitter if needed: the reason for this is 6398 * that in compute_mode_changes we check the native mode (not the pfit 6399 * mode) to see if we can flip rather than do a full mode set. In the 6400 * fastboot case, we'll flip, but if we don't update the pipesrc and 6401 * pfit state, we'll end up with a big fb scanned out into the wrong 6402 * sized surface. 6403 */ 6404 intel_set_pipe_src_size(new_crtc_state); 6405 6406 /* on skylake this is done by detaching scalers */ 6407 if (DISPLAY_VER(dev_priv) >= 9) { 6408 if (new_crtc_state->pch_pfit.enabled) 6409 skl_pfit_enable(new_crtc_state); 6410 } else if (HAS_PCH_SPLIT(dev_priv)) { 6411 if (new_crtc_state->pch_pfit.enabled) 6412 ilk_pfit_enable(new_crtc_state); 6413 else if (old_crtc_state->pch_pfit.enabled) 6414 ilk_pfit_disable(old_crtc_state); 6415 } 6416 6417 /* 6418 * The register is supposedly single buffered so perhaps 6419 * not 100% correct to do this here. But SKL+ calculate 6420 * this based on the adjust pixel rate so pfit changes do 6421 * affect it and so it must be updated for fastsets. 6422 * HSW/BDW only really need this here for fastboot, after 6423 * that the value should not change without a full modeset. 6424 */ 6425 if (DISPLAY_VER(dev_priv) >= 9 || 6426 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 6427 hsw_set_linetime_wm(new_crtc_state); 6428 6429 if (new_crtc_state->seamless_m_n) 6430 intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder, 6431 &new_crtc_state->dp_m_n); 6432 } 6433 6434 static void commit_pipe_pre_planes(struct intel_atomic_state *state, 6435 struct intel_crtc *crtc) 6436 { 6437 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6438 const struct intel_crtc_state *old_crtc_state = 6439 intel_atomic_get_old_crtc_state(state, crtc); 6440 const struct intel_crtc_state *new_crtc_state = 6441 intel_atomic_get_new_crtc_state(state, crtc); 6442 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 6443 6444 /* 6445 * During modesets pipe configuration was programmed as the 6446 * CRTC was enabled. 6447 */ 6448 if (!modeset) { 6449 if (intel_crtc_needs_color_update(new_crtc_state)) 6450 intel_color_commit_arm(new_crtc_state); 6451 6452 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 6453 bdw_set_pipe_misc(new_crtc_state); 6454 6455 if (intel_crtc_needs_fastset(new_crtc_state)) 6456 intel_pipe_fastset(old_crtc_state, new_crtc_state); 6457 } 6458 6459 intel_psr2_program_trans_man_trk_ctl(new_crtc_state); 6460 6461 intel_atomic_update_watermarks(state, crtc); 6462 } 6463 6464 static void commit_pipe_post_planes(struct intel_atomic_state *state, 6465 struct intel_crtc *crtc) 6466 { 6467 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6468 const struct intel_crtc_state *new_crtc_state = 6469 intel_atomic_get_new_crtc_state(state, crtc); 6470 6471 /* 6472 * Disable the scaler(s) after the plane(s) so that we don't 6473 * get a catastrophic underrun even if the two operations 6474 * end up happening in two different frames. 6475 */ 6476 if (DISPLAY_VER(dev_priv) >= 9 && 6477 !intel_crtc_needs_modeset(new_crtc_state)) 6478 skl_detach_scalers(new_crtc_state); 6479 } 6480 6481 static void intel_enable_crtc(struct intel_atomic_state *state, 6482 struct intel_crtc *crtc) 6483 { 6484 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6485 const struct intel_crtc_state *new_crtc_state = 6486 intel_atomic_get_new_crtc_state(state, crtc); 6487 6488 if (!intel_crtc_needs_modeset(new_crtc_state)) 6489 return; 6490 6491 /* VRR will be enable later, if required */ 6492 intel_crtc_update_active_timings(new_crtc_state, false); 6493 6494 dev_priv->display.funcs.display->crtc_enable(state, crtc); 6495 6496 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 6497 return; 6498 6499 /* vblanks work again, re-enable pipe CRC. */ 6500 intel_crtc_enable_pipe_crc(crtc); 6501 } 6502 6503 static void intel_update_crtc(struct intel_atomic_state *state, 6504 struct intel_crtc *crtc) 6505 { 6506 struct drm_i915_private *i915 = to_i915(state->base.dev); 6507 const struct intel_crtc_state *old_crtc_state = 6508 intel_atomic_get_old_crtc_state(state, crtc); 6509 struct intel_crtc_state *new_crtc_state = 6510 intel_atomic_get_new_crtc_state(state, crtc); 6511 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 6512 6513 if (old_crtc_state->inherited || 6514 intel_crtc_needs_modeset(new_crtc_state)) { 6515 if (HAS_DPT(i915)) 6516 intel_dpt_configure(crtc); 6517 } 6518 6519 if (vrr_enabling(old_crtc_state, new_crtc_state)) { 6520 intel_vrr_enable(new_crtc_state); 6521 intel_crtc_update_active_timings(new_crtc_state, 6522 new_crtc_state->vrr.enable); 6523 } 6524 6525 if (!modeset) { 6526 if (new_crtc_state->preload_luts && 6527 intel_crtc_needs_color_update(new_crtc_state)) 6528 intel_color_load_luts(new_crtc_state); 6529 6530 intel_pre_plane_update(state, crtc); 6531 6532 if (intel_crtc_needs_fastset(new_crtc_state)) 6533 intel_encoders_update_pipe(state, crtc); 6534 6535 if (DISPLAY_VER(i915) >= 11 && 6536 intel_crtc_needs_fastset(new_crtc_state)) 6537 icl_set_pipe_chicken(new_crtc_state); 6538 } 6539 6540 intel_fbc_update(state, crtc); 6541 6542 drm_WARN_ON(&i915->drm, !intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF)); 6543 6544 if (!modeset && 6545 intel_crtc_needs_color_update(new_crtc_state)) 6546 intel_color_commit_noarm(new_crtc_state); 6547 6548 intel_crtc_planes_update_noarm(state, crtc); 6549 6550 /* Perform vblank evasion around commit operation */ 6551 intel_pipe_update_start(new_crtc_state); 6552 6553 commit_pipe_pre_planes(state, crtc); 6554 6555 intel_crtc_planes_update_arm(state, crtc); 6556 6557 commit_pipe_post_planes(state, crtc); 6558 6559 intel_pipe_update_end(new_crtc_state); 6560 6561 /* 6562 * We usually enable FIFO underrun interrupts as part of the 6563 * CRTC enable sequence during modesets. But when we inherit a 6564 * valid pipe configuration from the BIOS we need to take care 6565 * of enabling them on the CRTC's first fastset. 6566 */ 6567 if (intel_crtc_needs_fastset(new_crtc_state) && !modeset && 6568 old_crtc_state->inherited) 6569 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state); 6570 } 6571 6572 static void intel_old_crtc_state_disables(struct intel_atomic_state *state, 6573 struct intel_crtc_state *old_crtc_state, 6574 struct intel_crtc_state *new_crtc_state, 6575 struct intel_crtc *crtc) 6576 { 6577 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6578 6579 /* 6580 * We need to disable pipe CRC before disabling the pipe, 6581 * or we race against vblank off. 6582 */ 6583 intel_crtc_disable_pipe_crc(crtc); 6584 6585 dev_priv->display.funcs.display->crtc_disable(state, crtc); 6586 crtc->active = false; 6587 intel_fbc_disable(crtc); 6588 6589 if (!new_crtc_state->hw.active) 6590 intel_initial_watermarks(state, crtc); 6591 } 6592 6593 static void intel_commit_modeset_disables(struct intel_atomic_state *state) 6594 { 6595 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 6596 struct intel_crtc *crtc; 6597 u32 handled = 0; 6598 int i; 6599 6600 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6601 new_crtc_state, i) { 6602 if (!intel_crtc_needs_modeset(new_crtc_state)) 6603 continue; 6604 6605 if (!old_crtc_state->hw.active) 6606 continue; 6607 6608 intel_pre_plane_update(state, crtc); 6609 intel_crtc_disable_planes(state, crtc); 6610 } 6611 6612 /* Only disable port sync and MST slaves */ 6613 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6614 new_crtc_state, i) { 6615 if (!intel_crtc_needs_modeset(new_crtc_state)) 6616 continue; 6617 6618 if (!old_crtc_state->hw.active) 6619 continue; 6620 6621 /* In case of Transcoder port Sync master slave CRTCs can be 6622 * assigned in any order and we need to make sure that 6623 * slave CRTCs are disabled first and then master CRTC since 6624 * Slave vblanks are masked till Master Vblanks. 6625 */ 6626 if (!is_trans_port_sync_slave(old_crtc_state) && 6627 !intel_dp_mst_is_slave_trans(old_crtc_state) && 6628 !intel_crtc_is_bigjoiner_slave(old_crtc_state)) 6629 continue; 6630 6631 intel_old_crtc_state_disables(state, old_crtc_state, 6632 new_crtc_state, crtc); 6633 handled |= BIT(crtc->pipe); 6634 } 6635 6636 /* Disable everything else left on */ 6637 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6638 new_crtc_state, i) { 6639 if (!intel_crtc_needs_modeset(new_crtc_state) || 6640 (handled & BIT(crtc->pipe))) 6641 continue; 6642 6643 if (!old_crtc_state->hw.active) 6644 continue; 6645 6646 intel_old_crtc_state_disables(state, old_crtc_state, 6647 new_crtc_state, crtc); 6648 } 6649 } 6650 6651 static void intel_commit_modeset_enables(struct intel_atomic_state *state) 6652 { 6653 struct intel_crtc_state *new_crtc_state; 6654 struct intel_crtc *crtc; 6655 int i; 6656 6657 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6658 if (!new_crtc_state->hw.active) 6659 continue; 6660 6661 intel_enable_crtc(state, crtc); 6662 intel_update_crtc(state, crtc); 6663 } 6664 } 6665 6666 static void skl_commit_modeset_enables(struct intel_atomic_state *state) 6667 { 6668 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6669 struct intel_crtc *crtc; 6670 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6671 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; 6672 u8 update_pipes = 0, modeset_pipes = 0; 6673 int i; 6674 6675 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6676 enum pipe pipe = crtc->pipe; 6677 6678 if (!new_crtc_state->hw.active) 6679 continue; 6680 6681 /* ignore allocations for crtc's that have been turned off. */ 6682 if (!intel_crtc_needs_modeset(new_crtc_state)) { 6683 entries[pipe] = old_crtc_state->wm.skl.ddb; 6684 update_pipes |= BIT(pipe); 6685 } else { 6686 modeset_pipes |= BIT(pipe); 6687 } 6688 } 6689 6690 /* 6691 * Whenever the number of active pipes changes, we need to make sure we 6692 * update the pipes in the right order so that their ddb allocations 6693 * never overlap with each other between CRTC updates. Otherwise we'll 6694 * cause pipe underruns and other bad stuff. 6695 * 6696 * So first lets enable all pipes that do not need a fullmodeset as 6697 * those don't have any external dependency. 6698 */ 6699 while (update_pipes) { 6700 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6701 new_crtc_state, i) { 6702 enum pipe pipe = crtc->pipe; 6703 6704 if ((update_pipes & BIT(pipe)) == 0) 6705 continue; 6706 6707 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 6708 entries, I915_MAX_PIPES, pipe)) 6709 continue; 6710 6711 entries[pipe] = new_crtc_state->wm.skl.ddb; 6712 update_pipes &= ~BIT(pipe); 6713 6714 intel_update_crtc(state, crtc); 6715 6716 /* 6717 * If this is an already active pipe, it's DDB changed, 6718 * and this isn't the last pipe that needs updating 6719 * then we need to wait for a vblank to pass for the 6720 * new ddb allocation to take effect. 6721 */ 6722 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, 6723 &old_crtc_state->wm.skl.ddb) && 6724 (update_pipes | modeset_pipes)) 6725 intel_crtc_wait_for_next_vblank(crtc); 6726 } 6727 } 6728 6729 update_pipes = modeset_pipes; 6730 6731 /* 6732 * Enable all pipes that needs a modeset and do not depends on other 6733 * pipes 6734 */ 6735 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6736 enum pipe pipe = crtc->pipe; 6737 6738 if ((modeset_pipes & BIT(pipe)) == 0) 6739 continue; 6740 6741 if (intel_dp_mst_is_slave_trans(new_crtc_state) || 6742 is_trans_port_sync_master(new_crtc_state) || 6743 intel_crtc_is_bigjoiner_master(new_crtc_state)) 6744 continue; 6745 6746 modeset_pipes &= ~BIT(pipe); 6747 6748 intel_enable_crtc(state, crtc); 6749 } 6750 6751 /* 6752 * Then we enable all remaining pipes that depend on other 6753 * pipes: MST slaves and port sync masters, big joiner master 6754 */ 6755 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6756 enum pipe pipe = crtc->pipe; 6757 6758 if ((modeset_pipes & BIT(pipe)) == 0) 6759 continue; 6760 6761 modeset_pipes &= ~BIT(pipe); 6762 6763 intel_enable_crtc(state, crtc); 6764 } 6765 6766 /* 6767 * Finally we do the plane updates/etc. for all pipes that got enabled. 6768 */ 6769 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6770 enum pipe pipe = crtc->pipe; 6771 6772 if ((update_pipes & BIT(pipe)) == 0) 6773 continue; 6774 6775 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 6776 entries, I915_MAX_PIPES, pipe)); 6777 6778 entries[pipe] = new_crtc_state->wm.skl.ddb; 6779 update_pipes &= ~BIT(pipe); 6780 6781 intel_update_crtc(state, crtc); 6782 } 6783 6784 drm_WARN_ON(&dev_priv->drm, modeset_pipes); 6785 drm_WARN_ON(&dev_priv->drm, update_pipes); 6786 } 6787 6788 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) 6789 { 6790 struct intel_atomic_state *state, *next; 6791 struct llist_node *freed; 6792 6793 freed = llist_del_all(&dev_priv->display.atomic_helper.free_list); 6794 llist_for_each_entry_safe(state, next, freed, freed) 6795 drm_atomic_state_put(&state->base); 6796 } 6797 6798 void intel_atomic_helper_free_state_worker(struct work_struct *work) 6799 { 6800 struct drm_i915_private *dev_priv = 6801 container_of(work, typeof(*dev_priv), display.atomic_helper.free_work); 6802 6803 intel_atomic_helper_free_state(dev_priv); 6804 } 6805 6806 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) 6807 { 6808 struct wait_queue_entry wait_fence, wait_reset; 6809 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); 6810 6811 init_wait_entry(&wait_fence, 0); 6812 init_wait_entry(&wait_reset, 0); 6813 for (;;) { 6814 prepare_to_wait(&intel_state->commit_ready.wait, 6815 &wait_fence, TASK_UNINTERRUPTIBLE); 6816 prepare_to_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 6817 I915_RESET_MODESET), 6818 &wait_reset, TASK_UNINTERRUPTIBLE); 6819 6820 6821 if (i915_sw_fence_done(&intel_state->commit_ready) || 6822 test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags)) 6823 break; 6824 6825 schedule(); 6826 } 6827 finish_wait(&intel_state->commit_ready.wait, &wait_fence); 6828 finish_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 6829 I915_RESET_MODESET), 6830 &wait_reset); 6831 } 6832 6833 static void intel_atomic_cleanup_work(struct work_struct *work) 6834 { 6835 struct intel_atomic_state *state = 6836 container_of(work, struct intel_atomic_state, base.commit_work); 6837 struct drm_i915_private *i915 = to_i915(state->base.dev); 6838 struct intel_crtc_state *old_crtc_state; 6839 struct intel_crtc *crtc; 6840 int i; 6841 6842 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) 6843 intel_color_cleanup_commit(old_crtc_state); 6844 6845 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base); 6846 drm_atomic_helper_commit_cleanup_done(&state->base); 6847 drm_atomic_state_put(&state->base); 6848 6849 intel_atomic_helper_free_state(i915); 6850 } 6851 6852 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state) 6853 { 6854 struct drm_i915_private *i915 = to_i915(state->base.dev); 6855 struct intel_plane *plane; 6856 struct intel_plane_state *plane_state; 6857 int i; 6858 6859 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 6860 struct drm_framebuffer *fb = plane_state->hw.fb; 6861 int cc_plane; 6862 int ret; 6863 6864 if (!fb) 6865 continue; 6866 6867 cc_plane = intel_fb_rc_ccs_cc_plane(fb); 6868 if (cc_plane < 0) 6869 continue; 6870 6871 /* 6872 * The layout of the fast clear color value expected by HW 6873 * (the DRM ABI requiring this value to be located in fb at 6874 * offset 0 of cc plane, plane #2 previous generations or 6875 * plane #1 for flat ccs): 6876 * - 4 x 4 bytes per-channel value 6877 * (in surface type specific float/int format provided by the fb user) 6878 * - 8 bytes native color value used by the display 6879 * (converted/written by GPU during a fast clear operation using the 6880 * above per-channel values) 6881 * 6882 * The commit's FB prepare hook already ensured that FB obj is pinned and the 6883 * caller made sure that the object is synced wrt. the related color clear value 6884 * GPU write on it. 6885 */ 6886 ret = i915_gem_object_read_from_page(intel_fb_obj(fb), 6887 fb->offsets[cc_plane] + 16, 6888 &plane_state->ccval, 6889 sizeof(plane_state->ccval)); 6890 /* The above could only fail if the FB obj has an unexpected backing store type. */ 6891 drm_WARN_ON(&i915->drm, ret); 6892 } 6893 } 6894 6895 static void intel_atomic_commit_tail(struct intel_atomic_state *state) 6896 { 6897 struct drm_device *dev = state->base.dev; 6898 struct drm_i915_private *dev_priv = to_i915(dev); 6899 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 6900 struct intel_crtc *crtc; 6901 struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {}; 6902 intel_wakeref_t wakeref = 0; 6903 int i; 6904 6905 intel_atomic_commit_fence_wait(state); 6906 6907 drm_atomic_helper_wait_for_dependencies(&state->base); 6908 drm_dp_mst_atomic_wait_for_dependencies(&state->base); 6909 6910 /* 6911 * During full modesets we write a lot of registers, wait 6912 * for PLLs, etc. Doing that while DC states are enabled 6913 * is not a good idea. 6914 * 6915 * During fastsets and other updates we also need to 6916 * disable DC states due to the following scenario: 6917 * 1. DC5 exit and PSR exit happen 6918 * 2. Some or all _noarm() registers are written 6919 * 3. Due to some long delay PSR is re-entered 6920 * 4. DC5 entry -> DMC saves the already written new 6921 * _noarm() registers and the old not yet written 6922 * _arm() registers 6923 * 5. DC5 exit -> DMC restores a mixture of old and 6924 * new register values and arms the update 6925 * 6. PSR exit -> hardware latches a mixture of old and 6926 * new register values -> corrupted frame, or worse 6927 * 7. New _arm() registers are finally written 6928 * 8. Hardware finally latches a complete set of new 6929 * register values, and subsequent frames will be OK again 6930 * 6931 * Also note that due to the pipe CSC hardware issues on 6932 * SKL/GLK DC states must remain off until the pipe CSC 6933 * state readout has happened. Otherwise we risk corrupting 6934 * the CSC latched register values with the readout (see 6935 * skl_read_csc() and skl_color_commit_noarm()). 6936 */ 6937 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DC_OFF); 6938 6939 intel_atomic_prepare_plane_clear_colors(state); 6940 6941 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6942 new_crtc_state, i) { 6943 if (intel_crtc_needs_modeset(new_crtc_state) || 6944 intel_crtc_needs_fastset(new_crtc_state)) 6945 intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]); 6946 } 6947 6948 intel_commit_modeset_disables(state); 6949 6950 /* FIXME: Eventually get rid of our crtc->config pointer */ 6951 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 6952 crtc->config = new_crtc_state; 6953 6954 if (state->modeset) { 6955 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base); 6956 6957 intel_set_cdclk_pre_plane_update(state); 6958 6959 intel_modeset_verify_disabled(dev_priv, state); 6960 } 6961 6962 intel_sagv_pre_plane_update(state); 6963 6964 /* Complete the events for pipes that have now been disabled */ 6965 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6966 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 6967 6968 /* Complete events for now disable pipes here. */ 6969 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) { 6970 spin_lock_irq(&dev->event_lock); 6971 drm_crtc_send_vblank_event(&crtc->base, 6972 new_crtc_state->uapi.event); 6973 spin_unlock_irq(&dev->event_lock); 6974 6975 new_crtc_state->uapi.event = NULL; 6976 } 6977 } 6978 6979 intel_encoders_update_prepare(state); 6980 6981 intel_dbuf_pre_plane_update(state); 6982 intel_mbus_dbox_update(state); 6983 6984 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6985 if (new_crtc_state->do_async_flip) 6986 intel_crtc_enable_flip_done(state, crtc); 6987 } 6988 6989 /* Now enable the clocks, plane, pipe, and connectors that we set up. */ 6990 dev_priv->display.funcs.display->commit_modeset_enables(state); 6991 6992 if (state->modeset) 6993 intel_set_cdclk_post_plane_update(state); 6994 6995 intel_wait_for_vblank_workers(state); 6996 6997 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here 6998 * already, but still need the state for the delayed optimization. To 6999 * fix this: 7000 * - wrap the optimization/post_plane_update stuff into a per-crtc work. 7001 * - schedule that vblank worker _before_ calling hw_done 7002 * - at the start of commit_tail, cancel it _synchrously 7003 * - switch over to the vblank wait helper in the core after that since 7004 * we don't need out special handling any more. 7005 */ 7006 drm_atomic_helper_wait_for_flip_done(dev, &state->base); 7007 7008 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7009 if (new_crtc_state->do_async_flip) 7010 intel_crtc_disable_flip_done(state, crtc); 7011 } 7012 7013 /* 7014 * Now that the vblank has passed, we can go ahead and program the 7015 * optimal watermarks on platforms that need two-step watermark 7016 * programming. 7017 * 7018 * TODO: Move this (and other cleanup) to an async worker eventually. 7019 */ 7020 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7021 new_crtc_state, i) { 7022 /* 7023 * Gen2 reports pipe underruns whenever all planes are disabled. 7024 * So re-enable underrun reporting after some planes get enabled. 7025 * 7026 * We do this before .optimize_watermarks() so that we have a 7027 * chance of catching underruns with the intermediate watermarks 7028 * vs. the new plane configuration. 7029 */ 7030 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state)) 7031 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 7032 7033 intel_optimize_watermarks(state, crtc); 7034 } 7035 7036 intel_dbuf_post_plane_update(state); 7037 intel_psr_post_plane_update(state); 7038 7039 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7040 intel_post_plane_update(state, crtc); 7041 7042 intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]); 7043 7044 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state); 7045 7046 /* Must be done after gamma readout due to HSW split gamma vs. IPS w/a */ 7047 hsw_ips_post_update(state, crtc); 7048 7049 /* 7050 * Activate DRRS after state readout to avoid 7051 * dp_m_n vs. dp_m2_n2 confusion on BDW+. 7052 */ 7053 intel_drrs_activate(new_crtc_state); 7054 7055 /* 7056 * DSB cleanup is done in cleanup_work aligning with framebuffer 7057 * cleanup. So copy and reset the dsb structure to sync with 7058 * commit_done and later do dsb cleanup in cleanup_work. 7059 * 7060 * FIXME get rid of this funny new->old swapping 7061 */ 7062 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb); 7063 } 7064 7065 /* Underruns don't always raise interrupts, so check manually */ 7066 intel_check_cpu_fifo_underruns(dev_priv); 7067 intel_check_pch_fifo_underruns(dev_priv); 7068 7069 if (state->modeset) 7070 intel_verify_planes(state); 7071 7072 intel_sagv_post_plane_update(state); 7073 7074 drm_atomic_helper_commit_hw_done(&state->base); 7075 7076 if (state->modeset) { 7077 /* As one of the primary mmio accessors, KMS has a high 7078 * likelihood of triggering bugs in unclaimed access. After we 7079 * finish modesetting, see if an error has been flagged, and if 7080 * so enable debugging for the next modeset - and hope we catch 7081 * the culprit. 7082 */ 7083 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); 7084 } 7085 intel_display_power_put(dev_priv, POWER_DOMAIN_DC_OFF, wakeref); 7086 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7087 7088 /* 7089 * Defer the cleanup of the old state to a separate worker to not 7090 * impede the current task (userspace for blocking modesets) that 7091 * are executed inline. For out-of-line asynchronous modesets/flips, 7092 * deferring to a new worker seems overkill, but we would place a 7093 * schedule point (cond_resched()) here anyway to keep latencies 7094 * down. 7095 */ 7096 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work); 7097 queue_work(system_highpri_wq, &state->base.commit_work); 7098 } 7099 7100 static void intel_atomic_commit_work(struct work_struct *work) 7101 { 7102 struct intel_atomic_state *state = 7103 container_of(work, struct intel_atomic_state, base.commit_work); 7104 7105 intel_atomic_commit_tail(state); 7106 } 7107 7108 static int 7109 intel_atomic_commit_ready(struct i915_sw_fence *fence, 7110 enum i915_sw_fence_notify notify) 7111 { 7112 struct intel_atomic_state *state = 7113 container_of(fence, struct intel_atomic_state, commit_ready); 7114 7115 switch (notify) { 7116 case FENCE_COMPLETE: 7117 /* we do blocking waits in the worker, nothing to do here */ 7118 break; 7119 case FENCE_FREE: 7120 { 7121 struct intel_atomic_helper *helper = 7122 &to_i915(state->base.dev)->display.atomic_helper; 7123 7124 if (llist_add(&state->freed, &helper->free_list)) 7125 schedule_work(&helper->free_work); 7126 break; 7127 } 7128 } 7129 7130 return NOTIFY_DONE; 7131 } 7132 7133 static void intel_atomic_track_fbs(struct intel_atomic_state *state) 7134 { 7135 struct intel_plane_state *old_plane_state, *new_plane_state; 7136 struct intel_plane *plane; 7137 int i; 7138 7139 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 7140 new_plane_state, i) 7141 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), 7142 to_intel_frontbuffer(new_plane_state->hw.fb), 7143 plane->frontbuffer_bit); 7144 } 7145 7146 int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state, 7147 bool nonblock) 7148 { 7149 struct intel_atomic_state *state = to_intel_atomic_state(_state); 7150 struct drm_i915_private *dev_priv = to_i915(dev); 7151 int ret = 0; 7152 7153 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 7154 7155 drm_atomic_state_get(&state->base); 7156 i915_sw_fence_init(&state->commit_ready, 7157 intel_atomic_commit_ready); 7158 7159 /* 7160 * The intel_legacy_cursor_update() fast path takes care 7161 * of avoiding the vblank waits for simple cursor 7162 * movement and flips. For cursor on/off and size changes, 7163 * we want to perform the vblank waits so that watermark 7164 * updates happen during the correct frames. Gen9+ have 7165 * double buffered watermarks and so shouldn't need this. 7166 * 7167 * Unset state->legacy_cursor_update before the call to 7168 * drm_atomic_helper_setup_commit() because otherwise 7169 * drm_atomic_helper_wait_for_flip_done() is a noop and 7170 * we get FIFO underruns because we didn't wait 7171 * for vblank. 7172 * 7173 * FIXME doing watermarks and fb cleanup from a vblank worker 7174 * (assuming we had any) would solve these problems. 7175 */ 7176 if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) { 7177 struct intel_crtc_state *new_crtc_state; 7178 struct intel_crtc *crtc; 7179 int i; 7180 7181 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7182 if (new_crtc_state->wm.need_postvbl_update || 7183 new_crtc_state->update_wm_post) 7184 state->base.legacy_cursor_update = false; 7185 } 7186 7187 ret = intel_atomic_prepare_commit(state); 7188 if (ret) { 7189 drm_dbg_atomic(&dev_priv->drm, 7190 "Preparing state failed with %i\n", ret); 7191 i915_sw_fence_commit(&state->commit_ready); 7192 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7193 return ret; 7194 } 7195 7196 ret = drm_atomic_helper_setup_commit(&state->base, nonblock); 7197 if (!ret) 7198 ret = drm_atomic_helper_swap_state(&state->base, true); 7199 if (!ret) 7200 intel_atomic_swap_global_state(state); 7201 7202 if (ret) { 7203 struct intel_crtc_state *new_crtc_state; 7204 struct intel_crtc *crtc; 7205 int i; 7206 7207 i915_sw_fence_commit(&state->commit_ready); 7208 7209 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7210 intel_color_cleanup_commit(new_crtc_state); 7211 7212 drm_atomic_helper_cleanup_planes(dev, &state->base); 7213 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7214 return ret; 7215 } 7216 intel_shared_dpll_swap_state(state); 7217 intel_atomic_track_fbs(state); 7218 7219 drm_atomic_state_get(&state->base); 7220 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work); 7221 7222 i915_sw_fence_commit(&state->commit_ready); 7223 if (nonblock && state->modeset) { 7224 queue_work(dev_priv->display.wq.modeset, &state->base.commit_work); 7225 } else if (nonblock) { 7226 queue_work(dev_priv->display.wq.flip, &state->base.commit_work); 7227 } else { 7228 if (state->modeset) 7229 flush_workqueue(dev_priv->display.wq.modeset); 7230 intel_atomic_commit_tail(state); 7231 } 7232 7233 return 0; 7234 } 7235 7236 /** 7237 * intel_plane_destroy - destroy a plane 7238 * @plane: plane to destroy 7239 * 7240 * Common destruction function for all types of planes (primary, cursor, 7241 * sprite). 7242 */ 7243 void intel_plane_destroy(struct drm_plane *plane) 7244 { 7245 drm_plane_cleanup(plane); 7246 kfree(to_intel_plane(plane)); 7247 } 7248 7249 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 7250 struct drm_file *file) 7251 { 7252 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; 7253 struct drm_crtc *drmmode_crtc; 7254 struct intel_crtc *crtc; 7255 7256 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id); 7257 if (!drmmode_crtc) 7258 return -ENOENT; 7259 7260 crtc = to_intel_crtc(drmmode_crtc); 7261 pipe_from_crtc_id->pipe = crtc->pipe; 7262 7263 return 0; 7264 } 7265 7266 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder) 7267 { 7268 struct drm_device *dev = encoder->base.dev; 7269 struct intel_encoder *source_encoder; 7270 u32 possible_clones = 0; 7271 7272 for_each_intel_encoder(dev, source_encoder) { 7273 if (encoders_cloneable(encoder, source_encoder)) 7274 possible_clones |= drm_encoder_mask(&source_encoder->base); 7275 } 7276 7277 return possible_clones; 7278 } 7279 7280 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder) 7281 { 7282 struct drm_device *dev = encoder->base.dev; 7283 struct intel_crtc *crtc; 7284 u32 possible_crtcs = 0; 7285 7286 for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask) 7287 possible_crtcs |= drm_crtc_mask(&crtc->base); 7288 7289 return possible_crtcs; 7290 } 7291 7292 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv) 7293 { 7294 if (!IS_MOBILE(dev_priv)) 7295 return false; 7296 7297 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0) 7298 return false; 7299 7300 if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE)) 7301 return false; 7302 7303 return true; 7304 } 7305 7306 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv) 7307 { 7308 if (DISPLAY_VER(dev_priv) >= 9) 7309 return false; 7310 7311 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) 7312 return false; 7313 7314 if (HAS_PCH_LPT_H(dev_priv) && 7315 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) 7316 return false; 7317 7318 /* DDI E can't be used if DDI A requires 4 lanes */ 7319 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 7320 return false; 7321 7322 if (!dev_priv->display.vbt.int_crt_support) 7323 return false; 7324 7325 return true; 7326 } 7327 7328 void intel_setup_outputs(struct drm_i915_private *dev_priv) 7329 { 7330 struct intel_encoder *encoder; 7331 bool dpd_is_edp = false; 7332 7333 intel_pps_unlock_regs_wa(dev_priv); 7334 7335 if (!HAS_DISPLAY(dev_priv)) 7336 return; 7337 7338 if (IS_METEORLAKE(dev_priv)) { 7339 /* TODO: initialize TC ports as well */ 7340 intel_ddi_init(dev_priv, PORT_A); 7341 intel_ddi_init(dev_priv, PORT_B); 7342 } else if (IS_DG2(dev_priv)) { 7343 intel_ddi_init(dev_priv, PORT_A); 7344 intel_ddi_init(dev_priv, PORT_B); 7345 intel_ddi_init(dev_priv, PORT_C); 7346 intel_ddi_init(dev_priv, PORT_D_XELPD); 7347 intel_ddi_init(dev_priv, PORT_TC1); 7348 } else if (IS_ALDERLAKE_P(dev_priv)) { 7349 intel_ddi_init(dev_priv, PORT_A); 7350 intel_ddi_init(dev_priv, PORT_B); 7351 intel_ddi_init(dev_priv, PORT_TC1); 7352 intel_ddi_init(dev_priv, PORT_TC2); 7353 intel_ddi_init(dev_priv, PORT_TC3); 7354 intel_ddi_init(dev_priv, PORT_TC4); 7355 icl_dsi_init(dev_priv); 7356 } else if (IS_ALDERLAKE_S(dev_priv)) { 7357 intel_ddi_init(dev_priv, PORT_A); 7358 intel_ddi_init(dev_priv, PORT_TC1); 7359 intel_ddi_init(dev_priv, PORT_TC2); 7360 intel_ddi_init(dev_priv, PORT_TC3); 7361 intel_ddi_init(dev_priv, PORT_TC4); 7362 } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) { 7363 intel_ddi_init(dev_priv, PORT_A); 7364 intel_ddi_init(dev_priv, PORT_B); 7365 intel_ddi_init(dev_priv, PORT_TC1); 7366 intel_ddi_init(dev_priv, PORT_TC2); 7367 } else if (DISPLAY_VER(dev_priv) >= 12) { 7368 intel_ddi_init(dev_priv, PORT_A); 7369 intel_ddi_init(dev_priv, PORT_B); 7370 intel_ddi_init(dev_priv, PORT_TC1); 7371 intel_ddi_init(dev_priv, PORT_TC2); 7372 intel_ddi_init(dev_priv, PORT_TC3); 7373 intel_ddi_init(dev_priv, PORT_TC4); 7374 intel_ddi_init(dev_priv, PORT_TC5); 7375 intel_ddi_init(dev_priv, PORT_TC6); 7376 icl_dsi_init(dev_priv); 7377 } else if (IS_JSL_EHL(dev_priv)) { 7378 intel_ddi_init(dev_priv, PORT_A); 7379 intel_ddi_init(dev_priv, PORT_B); 7380 intel_ddi_init(dev_priv, PORT_C); 7381 intel_ddi_init(dev_priv, PORT_D); 7382 icl_dsi_init(dev_priv); 7383 } else if (DISPLAY_VER(dev_priv) == 11) { 7384 intel_ddi_init(dev_priv, PORT_A); 7385 intel_ddi_init(dev_priv, PORT_B); 7386 intel_ddi_init(dev_priv, PORT_C); 7387 intel_ddi_init(dev_priv, PORT_D); 7388 intel_ddi_init(dev_priv, PORT_E); 7389 intel_ddi_init(dev_priv, PORT_F); 7390 icl_dsi_init(dev_priv); 7391 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 7392 intel_ddi_init(dev_priv, PORT_A); 7393 intel_ddi_init(dev_priv, PORT_B); 7394 intel_ddi_init(dev_priv, PORT_C); 7395 vlv_dsi_init(dev_priv); 7396 } else if (DISPLAY_VER(dev_priv) >= 9) { 7397 intel_ddi_init(dev_priv, PORT_A); 7398 intel_ddi_init(dev_priv, PORT_B); 7399 intel_ddi_init(dev_priv, PORT_C); 7400 intel_ddi_init(dev_priv, PORT_D); 7401 intel_ddi_init(dev_priv, PORT_E); 7402 } else if (HAS_DDI(dev_priv)) { 7403 u32 found; 7404 7405 if (intel_ddi_crt_present(dev_priv)) 7406 intel_crt_init(dev_priv); 7407 7408 /* Haswell uses DDI functions to detect digital outputs. */ 7409 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 7410 if (found) 7411 intel_ddi_init(dev_priv, PORT_A); 7412 7413 found = intel_de_read(dev_priv, SFUSE_STRAP); 7414 if (found & SFUSE_STRAP_DDIB_DETECTED) 7415 intel_ddi_init(dev_priv, PORT_B); 7416 if (found & SFUSE_STRAP_DDIC_DETECTED) 7417 intel_ddi_init(dev_priv, PORT_C); 7418 if (found & SFUSE_STRAP_DDID_DETECTED) 7419 intel_ddi_init(dev_priv, PORT_D); 7420 if (found & SFUSE_STRAP_DDIF_DETECTED) 7421 intel_ddi_init(dev_priv, PORT_F); 7422 } else if (HAS_PCH_SPLIT(dev_priv)) { 7423 int found; 7424 7425 /* 7426 * intel_edp_init_connector() depends on this completing first, 7427 * to prevent the registration of both eDP and LVDS and the 7428 * incorrect sharing of the PPS. 7429 */ 7430 intel_lvds_init(dev_priv); 7431 intel_crt_init(dev_priv); 7432 7433 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D); 7434 7435 if (ilk_has_edp_a(dev_priv)) 7436 g4x_dp_init(dev_priv, DP_A, PORT_A); 7437 7438 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) { 7439 /* PCH SDVOB multiplex with HDMIB */ 7440 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); 7441 if (!found) 7442 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); 7443 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED)) 7444 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B); 7445 } 7446 7447 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED) 7448 g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); 7449 7450 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED) 7451 g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D); 7452 7453 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED) 7454 g4x_dp_init(dev_priv, PCH_DP_C, PORT_C); 7455 7456 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED) 7457 g4x_dp_init(dev_priv, PCH_DP_D, PORT_D); 7458 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 7459 bool has_edp, has_port; 7460 7461 if (IS_VALLEYVIEW(dev_priv) && dev_priv->display.vbt.int_crt_support) 7462 intel_crt_init(dev_priv); 7463 7464 /* 7465 * The DP_DETECTED bit is the latched state of the DDC 7466 * SDA pin at boot. However since eDP doesn't require DDC 7467 * (no way to plug in a DP->HDMI dongle) the DDC pins for 7468 * eDP ports may have been muxed to an alternate function. 7469 * Thus we can't rely on the DP_DETECTED bit alone to detect 7470 * eDP ports. Consult the VBT as well as DP_DETECTED to 7471 * detect eDP ports. 7472 * 7473 * Sadly the straps seem to be missing sometimes even for HDMI 7474 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap 7475 * and VBT for the presence of the port. Additionally we can't 7476 * trust the port type the VBT declares as we've seen at least 7477 * HDMI ports that the VBT claim are DP or eDP. 7478 */ 7479 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B); 7480 has_port = intel_bios_is_port_present(dev_priv, PORT_B); 7481 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port) 7482 has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B); 7483 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) 7484 g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); 7485 7486 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C); 7487 has_port = intel_bios_is_port_present(dev_priv, PORT_C); 7488 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port) 7489 has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C); 7490 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) 7491 g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); 7492 7493 if (IS_CHERRYVIEW(dev_priv)) { 7494 /* 7495 * eDP not supported on port D, 7496 * so no need to worry about it 7497 */ 7498 has_port = intel_bios_is_port_present(dev_priv, PORT_D); 7499 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port) 7500 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D); 7501 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port) 7502 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D); 7503 } 7504 7505 vlv_dsi_init(dev_priv); 7506 } else if (IS_PINEVIEW(dev_priv)) { 7507 intel_lvds_init(dev_priv); 7508 intel_crt_init(dev_priv); 7509 } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) { 7510 bool found = false; 7511 7512 if (IS_MOBILE(dev_priv)) 7513 intel_lvds_init(dev_priv); 7514 7515 intel_crt_init(dev_priv); 7516 7517 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 7518 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n"); 7519 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); 7520 if (!found && IS_G4X(dev_priv)) { 7521 drm_dbg_kms(&dev_priv->drm, 7522 "probing HDMI on SDVOB\n"); 7523 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); 7524 } 7525 7526 if (!found && IS_G4X(dev_priv)) 7527 g4x_dp_init(dev_priv, DP_B, PORT_B); 7528 } 7529 7530 /* Before G4X SDVOC doesn't have its own detect register */ 7531 7532 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 7533 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n"); 7534 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); 7535 } 7536 7537 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) { 7538 7539 if (IS_G4X(dev_priv)) { 7540 drm_dbg_kms(&dev_priv->drm, 7541 "probing HDMI on SDVOC\n"); 7542 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); 7543 } 7544 if (IS_G4X(dev_priv)) 7545 g4x_dp_init(dev_priv, DP_C, PORT_C); 7546 } 7547 7548 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED)) 7549 g4x_dp_init(dev_priv, DP_D, PORT_D); 7550 7551 if (SUPPORTS_TV(dev_priv)) 7552 intel_tv_init(dev_priv); 7553 } else if (DISPLAY_VER(dev_priv) == 2) { 7554 if (IS_I85X(dev_priv)) 7555 intel_lvds_init(dev_priv); 7556 7557 intel_crt_init(dev_priv); 7558 intel_dvo_init(dev_priv); 7559 } 7560 7561 for_each_intel_encoder(&dev_priv->drm, encoder) { 7562 encoder->base.possible_crtcs = 7563 intel_encoder_possible_crtcs(encoder); 7564 encoder->base.possible_clones = 7565 intel_encoder_possible_clones(encoder); 7566 } 7567 7568 intel_init_pch_refclk(dev_priv); 7569 7570 drm_helper_move_panel_connectors_to_head(&dev_priv->drm); 7571 } 7572 7573 static int max_dotclock(struct drm_i915_private *i915) 7574 { 7575 int max_dotclock = i915->max_dotclk_freq; 7576 7577 /* icl+ might use bigjoiner */ 7578 if (DISPLAY_VER(i915) >= 11) 7579 max_dotclock *= 2; 7580 7581 return max_dotclock; 7582 } 7583 7584 enum drm_mode_status intel_mode_valid(struct drm_device *dev, 7585 const struct drm_display_mode *mode) 7586 { 7587 struct drm_i915_private *dev_priv = to_i915(dev); 7588 int hdisplay_max, htotal_max; 7589 int vdisplay_max, vtotal_max; 7590 7591 /* 7592 * Can't reject DBLSCAN here because Xorg ddxen can add piles 7593 * of DBLSCAN modes to the output's mode list when they detect 7594 * the scaling mode property on the connector. And they don't 7595 * ask the kernel to validate those modes in any way until 7596 * modeset time at which point the client gets a protocol error. 7597 * So in order to not upset those clients we silently ignore the 7598 * DBLSCAN flag on such connectors. For other connectors we will 7599 * reject modes with the DBLSCAN flag in encoder->compute_config(). 7600 * And we always reject DBLSCAN modes in connector->mode_valid() 7601 * as we never want such modes on the connector's mode list. 7602 */ 7603 7604 if (mode->vscan > 1) 7605 return MODE_NO_VSCAN; 7606 7607 if (mode->flags & DRM_MODE_FLAG_HSKEW) 7608 return MODE_H_ILLEGAL; 7609 7610 if (mode->flags & (DRM_MODE_FLAG_CSYNC | 7611 DRM_MODE_FLAG_NCSYNC | 7612 DRM_MODE_FLAG_PCSYNC)) 7613 return MODE_HSYNC; 7614 7615 if (mode->flags & (DRM_MODE_FLAG_BCAST | 7616 DRM_MODE_FLAG_PIXMUX | 7617 DRM_MODE_FLAG_CLKDIV2)) 7618 return MODE_BAD; 7619 7620 /* 7621 * Reject clearly excessive dotclocks early to 7622 * avoid having to worry about huge integers later. 7623 */ 7624 if (mode->clock > max_dotclock(dev_priv)) 7625 return MODE_CLOCK_HIGH; 7626 7627 /* Transcoder timing limits */ 7628 if (DISPLAY_VER(dev_priv) >= 11) { 7629 hdisplay_max = 16384; 7630 vdisplay_max = 8192; 7631 htotal_max = 16384; 7632 vtotal_max = 8192; 7633 } else if (DISPLAY_VER(dev_priv) >= 9 || 7634 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 7635 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ 7636 vdisplay_max = 4096; 7637 htotal_max = 8192; 7638 vtotal_max = 8192; 7639 } else if (DISPLAY_VER(dev_priv) >= 3) { 7640 hdisplay_max = 4096; 7641 vdisplay_max = 4096; 7642 htotal_max = 8192; 7643 vtotal_max = 8192; 7644 } else { 7645 hdisplay_max = 2048; 7646 vdisplay_max = 2048; 7647 htotal_max = 4096; 7648 vtotal_max = 4096; 7649 } 7650 7651 if (mode->hdisplay > hdisplay_max || 7652 mode->hsync_start > htotal_max || 7653 mode->hsync_end > htotal_max || 7654 mode->htotal > htotal_max) 7655 return MODE_H_ILLEGAL; 7656 7657 if (mode->vdisplay > vdisplay_max || 7658 mode->vsync_start > vtotal_max || 7659 mode->vsync_end > vtotal_max || 7660 mode->vtotal > vtotal_max) 7661 return MODE_V_ILLEGAL; 7662 7663 if (DISPLAY_VER(dev_priv) >= 5) { 7664 if (mode->hdisplay < 64 || 7665 mode->htotal - mode->hdisplay < 32) 7666 return MODE_H_ILLEGAL; 7667 7668 if (mode->vtotal - mode->vdisplay < 5) 7669 return MODE_V_ILLEGAL; 7670 } else { 7671 if (mode->htotal - mode->hdisplay < 32) 7672 return MODE_H_ILLEGAL; 7673 7674 if (mode->vtotal - mode->vdisplay < 3) 7675 return MODE_V_ILLEGAL; 7676 } 7677 7678 /* 7679 * Cantiga+ cannot handle modes with a hsync front porch of 0. 7680 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. 7681 */ 7682 if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) && 7683 mode->hsync_start == mode->hdisplay) 7684 return MODE_H_ILLEGAL; 7685 7686 return MODE_OK; 7687 } 7688 7689 enum drm_mode_status 7690 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 7691 const struct drm_display_mode *mode, 7692 bool bigjoiner) 7693 { 7694 int plane_width_max, plane_height_max; 7695 7696 /* 7697 * intel_mode_valid() should be 7698 * sufficient on older platforms. 7699 */ 7700 if (DISPLAY_VER(dev_priv) < 9) 7701 return MODE_OK; 7702 7703 /* 7704 * Most people will probably want a fullscreen 7705 * plane so let's not advertize modes that are 7706 * too big for that. 7707 */ 7708 if (DISPLAY_VER(dev_priv) >= 11) { 7709 plane_width_max = 5120 << bigjoiner; 7710 plane_height_max = 4320; 7711 } else { 7712 plane_width_max = 5120; 7713 plane_height_max = 4096; 7714 } 7715 7716 if (mode->hdisplay > plane_width_max) 7717 return MODE_H_ILLEGAL; 7718 7719 if (mode->vdisplay > plane_height_max) 7720 return MODE_V_ILLEGAL; 7721 7722 return MODE_OK; 7723 } 7724 7725 static const struct intel_display_funcs skl_display_funcs = { 7726 .get_pipe_config = hsw_get_pipe_config, 7727 .crtc_enable = hsw_crtc_enable, 7728 .crtc_disable = hsw_crtc_disable, 7729 .commit_modeset_enables = skl_commit_modeset_enables, 7730 .get_initial_plane_config = skl_get_initial_plane_config, 7731 }; 7732 7733 static const struct intel_display_funcs ddi_display_funcs = { 7734 .get_pipe_config = hsw_get_pipe_config, 7735 .crtc_enable = hsw_crtc_enable, 7736 .crtc_disable = hsw_crtc_disable, 7737 .commit_modeset_enables = intel_commit_modeset_enables, 7738 .get_initial_plane_config = i9xx_get_initial_plane_config, 7739 }; 7740 7741 static const struct intel_display_funcs pch_split_display_funcs = { 7742 .get_pipe_config = ilk_get_pipe_config, 7743 .crtc_enable = ilk_crtc_enable, 7744 .crtc_disable = ilk_crtc_disable, 7745 .commit_modeset_enables = intel_commit_modeset_enables, 7746 .get_initial_plane_config = i9xx_get_initial_plane_config, 7747 }; 7748 7749 static const struct intel_display_funcs vlv_display_funcs = { 7750 .get_pipe_config = i9xx_get_pipe_config, 7751 .crtc_enable = valleyview_crtc_enable, 7752 .crtc_disable = i9xx_crtc_disable, 7753 .commit_modeset_enables = intel_commit_modeset_enables, 7754 .get_initial_plane_config = i9xx_get_initial_plane_config, 7755 }; 7756 7757 static const struct intel_display_funcs i9xx_display_funcs = { 7758 .get_pipe_config = i9xx_get_pipe_config, 7759 .crtc_enable = i9xx_crtc_enable, 7760 .crtc_disable = i9xx_crtc_disable, 7761 .commit_modeset_enables = intel_commit_modeset_enables, 7762 .get_initial_plane_config = i9xx_get_initial_plane_config, 7763 }; 7764 7765 /** 7766 * intel_init_display_hooks - initialize the display modesetting hooks 7767 * @dev_priv: device private 7768 */ 7769 void intel_init_display_hooks(struct drm_i915_private *dev_priv) 7770 { 7771 if (DISPLAY_VER(dev_priv) >= 9) { 7772 dev_priv->display.funcs.display = &skl_display_funcs; 7773 } else if (HAS_DDI(dev_priv)) { 7774 dev_priv->display.funcs.display = &ddi_display_funcs; 7775 } else if (HAS_PCH_SPLIT(dev_priv)) { 7776 dev_priv->display.funcs.display = &pch_split_display_funcs; 7777 } else if (IS_CHERRYVIEW(dev_priv) || 7778 IS_VALLEYVIEW(dev_priv)) { 7779 dev_priv->display.funcs.display = &vlv_display_funcs; 7780 } else { 7781 dev_priv->display.funcs.display = &i9xx_display_funcs; 7782 } 7783 } 7784 7785 int intel_initial_commit(struct drm_device *dev) 7786 { 7787 struct drm_atomic_state *state = NULL; 7788 struct drm_modeset_acquire_ctx ctx; 7789 struct intel_crtc *crtc; 7790 int ret = 0; 7791 7792 state = drm_atomic_state_alloc(dev); 7793 if (!state) 7794 return -ENOMEM; 7795 7796 drm_modeset_acquire_init(&ctx, 0); 7797 7798 state->acquire_ctx = &ctx; 7799 to_intel_atomic_state(state)->internal = true; 7800 7801 retry: 7802 for_each_intel_crtc(dev, crtc) { 7803 struct intel_crtc_state *crtc_state = 7804 intel_atomic_get_crtc_state(state, crtc); 7805 7806 if (IS_ERR(crtc_state)) { 7807 ret = PTR_ERR(crtc_state); 7808 goto out; 7809 } 7810 7811 if (crtc_state->hw.active) { 7812 struct intel_encoder *encoder; 7813 7814 ret = drm_atomic_add_affected_planes(state, &crtc->base); 7815 if (ret) 7816 goto out; 7817 7818 /* 7819 * FIXME hack to force a LUT update to avoid the 7820 * plane update forcing the pipe gamma on without 7821 * having a proper LUT loaded. Remove once we 7822 * have readout for pipe gamma enable. 7823 */ 7824 crtc_state->uapi.color_mgmt_changed = true; 7825 7826 for_each_intel_encoder_mask(dev, encoder, 7827 crtc_state->uapi.encoder_mask) { 7828 if (encoder->initial_fastset_check && 7829 !encoder->initial_fastset_check(encoder, crtc_state)) { 7830 ret = drm_atomic_add_affected_connectors(state, 7831 &crtc->base); 7832 if (ret) 7833 goto out; 7834 } 7835 } 7836 } 7837 } 7838 7839 ret = drm_atomic_commit(state); 7840 7841 out: 7842 if (ret == -EDEADLK) { 7843 drm_atomic_state_clear(state); 7844 drm_modeset_backoff(&ctx); 7845 goto retry; 7846 } 7847 7848 drm_atomic_state_put(state); 7849 7850 drm_modeset_drop_locks(&ctx); 7851 drm_modeset_acquire_fini(&ctx); 7852 7853 return ret; 7854 } 7855 7856 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 7857 { 7858 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 7859 enum transcoder cpu_transcoder = (enum transcoder)pipe; 7860 /* 640x480@60Hz, ~25175 kHz */ 7861 struct dpll clock = { 7862 .m1 = 18, 7863 .m2 = 7, 7864 .p1 = 13, 7865 .p2 = 4, 7866 .n = 2, 7867 }; 7868 u32 dpll, fp; 7869 int i; 7870 7871 drm_WARN_ON(&dev_priv->drm, 7872 i9xx_calc_dpll_params(48000, &clock) != 25154); 7873 7874 drm_dbg_kms(&dev_priv->drm, 7875 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n", 7876 pipe_name(pipe), clock.vco, clock.dot); 7877 7878 fp = i9xx_dpll_compute_fp(&clock); 7879 dpll = DPLL_DVO_2X_MODE | 7880 DPLL_VGA_MODE_DIS | 7881 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | 7882 PLL_P2_DIVIDE_BY_4 | 7883 PLL_REF_INPUT_DREFCLK | 7884 DPLL_VCO_ENABLE; 7885 7886 intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder), 7887 HACTIVE(640 - 1) | HTOTAL(800 - 1)); 7888 intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder), 7889 HBLANK_START(640 - 1) | HBLANK_END(800 - 1)); 7890 intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder), 7891 HSYNC_START(656 - 1) | HSYNC_END(752 - 1)); 7892 intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder), 7893 VACTIVE(480 - 1) | VTOTAL(525 - 1)); 7894 intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), 7895 VBLANK_START(480 - 1) | VBLANK_END(525 - 1)); 7896 intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder), 7897 VSYNC_START(490 - 1) | VSYNC_END(492 - 1)); 7898 intel_de_write(dev_priv, PIPESRC(pipe), 7899 PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1)); 7900 7901 intel_de_write(dev_priv, FP0(pipe), fp); 7902 intel_de_write(dev_priv, FP1(pipe), fp); 7903 7904 /* 7905 * Apparently we need to have VGA mode enabled prior to changing 7906 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 7907 * dividers, even though the register value does change. 7908 */ 7909 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); 7910 intel_de_write(dev_priv, DPLL(pipe), dpll); 7911 7912 /* Wait for the clocks to stabilize. */ 7913 intel_de_posting_read(dev_priv, DPLL(pipe)); 7914 udelay(150); 7915 7916 /* The pixel multiplier can only be updated once the 7917 * DPLL is enabled and the clocks are stable. 7918 * 7919 * So write it again. 7920 */ 7921 intel_de_write(dev_priv, DPLL(pipe), dpll); 7922 7923 /* We do this three times for luck */ 7924 for (i = 0; i < 3 ; i++) { 7925 intel_de_write(dev_priv, DPLL(pipe), dpll); 7926 intel_de_posting_read(dev_priv, DPLL(pipe)); 7927 udelay(150); /* wait for warmup */ 7928 } 7929 7930 intel_de_write(dev_priv, TRANSCONF(pipe), TRANSCONF_ENABLE); 7931 intel_de_posting_read(dev_priv, TRANSCONF(pipe)); 7932 7933 intel_wait_for_pipe_scanline_moving(crtc); 7934 } 7935 7936 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 7937 { 7938 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 7939 7940 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n", 7941 pipe_name(pipe)); 7942 7943 drm_WARN_ON(&dev_priv->drm, 7944 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE); 7945 drm_WARN_ON(&dev_priv->drm, 7946 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE); 7947 drm_WARN_ON(&dev_priv->drm, 7948 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE); 7949 drm_WARN_ON(&dev_priv->drm, 7950 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK); 7951 drm_WARN_ON(&dev_priv->drm, 7952 intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK); 7953 7954 intel_de_write(dev_priv, TRANSCONF(pipe), 0); 7955 intel_de_posting_read(dev_priv, TRANSCONF(pipe)); 7956 7957 intel_wait_for_pipe_scanline_stopped(crtc); 7958 7959 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); 7960 intel_de_posting_read(dev_priv, DPLL(pipe)); 7961 } 7962 7963 void intel_hpd_poll_fini(struct drm_i915_private *i915) 7964 { 7965 struct intel_connector *connector; 7966 struct drm_connector_list_iter conn_iter; 7967 7968 /* Kill all the work that may have been queued by hpd. */ 7969 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 7970 for_each_intel_connector_iter(connector, &conn_iter) { 7971 if (connector->modeset_retry_work.func) 7972 cancel_work_sync(&connector->modeset_retry_work); 7973 if (connector->hdcp.shim) { 7974 cancel_delayed_work_sync(&connector->hdcp.check_work); 7975 cancel_work_sync(&connector->hdcp.prop_work); 7976 } 7977 } 7978 drm_connector_list_iter_end(&conn_iter); 7979 } 7980 7981 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915) 7982 { 7983 return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915); 7984 } 7985