1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <linux/dma-resv.h> 28 #include <linux/i2c.h> 29 #include <linux/input.h> 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/slab.h> 33 #include <linux/string_helpers.h> 34 #include <linux/vga_switcheroo.h> 35 #include <acpi/video.h> 36 37 #include <drm/display/drm_dp_helper.h> 38 #include <drm/drm_atomic.h> 39 #include <drm/drm_atomic_helper.h> 40 #include <drm/drm_atomic_uapi.h> 41 #include <drm/drm_damage_helper.h> 42 #include <drm/drm_edid.h> 43 #include <drm/drm_fourcc.h> 44 #include <drm/drm_privacy_screen_consumer.h> 45 #include <drm/drm_probe_helper.h> 46 #include <drm/drm_rect.h> 47 48 #include "gem/i915_gem_lmem.h" 49 #include "gem/i915_gem_object.h" 50 51 #include "g4x_dp.h" 52 #include "g4x_hdmi.h" 53 #include "hsw_ips.h" 54 #include "i915_drv.h" 55 #include "i915_reg.h" 56 #include "i915_utils.h" 57 #include "i9xx_plane.h" 58 #include "i9xx_wm.h" 59 #include "icl_dsi.h" 60 #include "intel_acpi.h" 61 #include "intel_atomic.h" 62 #include "intel_atomic_plane.h" 63 #include "intel_audio.h" 64 #include "intel_bw.h" 65 #include "intel_cdclk.h" 66 #include "intel_color.h" 67 #include "intel_crt.h" 68 #include "intel_crtc.h" 69 #include "intel_crtc_state_dump.h" 70 #include "intel_ddi.h" 71 #include "intel_de.h" 72 #include "intel_display_debugfs.h" 73 #include "intel_display_power.h" 74 #include "intel_display_types.h" 75 #include "intel_dmc.h" 76 #include "intel_dp.h" 77 #include "intel_dp_link_training.h" 78 #include "intel_dp_mst.h" 79 #include "intel_dpio_phy.h" 80 #include "intel_dpll.h" 81 #include "intel_dpll_mgr.h" 82 #include "intel_dpt.h" 83 #include "intel_drrs.h" 84 #include "intel_dsi.h" 85 #include "intel_dvo.h" 86 #include "intel_fb.h" 87 #include "intel_fbc.h" 88 #include "intel_fbdev.h" 89 #include "intel_fdi.h" 90 #include "intel_fifo_underrun.h" 91 #include "intel_frontbuffer.h" 92 #include "intel_gmbus.h" 93 #include "intel_hdcp.h" 94 #include "intel_hdmi.h" 95 #include "intel_hotplug.h" 96 #include "intel_hti.h" 97 #include "intel_lvds.h" 98 #include "intel_lvds_regs.h" 99 #include "intel_modeset_setup.h" 100 #include "intel_modeset_verify.h" 101 #include "intel_overlay.h" 102 #include "intel_panel.h" 103 #include "intel_pch_display.h" 104 #include "intel_pch_refclk.h" 105 #include "intel_pcode.h" 106 #include "intel_pipe_crc.h" 107 #include "intel_plane_initial.h" 108 #include "intel_pm.h" 109 #include "intel_pps.h" 110 #include "intel_psr.h" 111 #include "intel_quirks.h" 112 #include "intel_sdvo.h" 113 #include "intel_snps_phy.h" 114 #include "intel_sprite.h" 115 #include "intel_tc.h" 116 #include "intel_tv.h" 117 #include "intel_vblank.h" 118 #include "intel_vdsc.h" 119 #include "intel_vga.h" 120 #include "intel_vrr.h" 121 #include "intel_wm.h" 122 #include "skl_scaler.h" 123 #include "skl_universal_plane.h" 124 #include "skl_watermark.h" 125 #include "vlv_dsi.h" 126 #include "vlv_dsi_pll.h" 127 #include "vlv_dsi_regs.h" 128 #include "vlv_sideband.h" 129 130 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state); 131 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state); 132 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state); 133 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state); 134 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state); 135 136 /* returns HPLL frequency in kHz */ 137 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) 138 { 139 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; 140 141 /* Obtain SKU information */ 142 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & 143 CCK_FUSE_HPLL_FREQ_MASK; 144 145 return vco_freq[hpll_freq] * 1000; 146 } 147 148 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 149 const char *name, u32 reg, int ref_freq) 150 { 151 u32 val; 152 int divider; 153 154 val = vlv_cck_read(dev_priv, reg); 155 divider = val & CCK_FREQUENCY_VALUES; 156 157 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != 158 (divider << CCK_FREQUENCY_STATUS_SHIFT), 159 "%s change in progress\n", name); 160 161 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); 162 } 163 164 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 165 const char *name, u32 reg) 166 { 167 int hpll; 168 169 vlv_cck_get(dev_priv); 170 171 if (dev_priv->hpll_freq == 0) 172 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); 173 174 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); 175 176 vlv_cck_put(dev_priv); 177 178 return hpll; 179 } 180 181 static void intel_update_czclk(struct drm_i915_private *dev_priv) 182 { 183 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) 184 return; 185 186 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", 187 CCK_CZ_CLOCK_CONTROL); 188 189 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", 190 dev_priv->czclk_freq); 191 } 192 193 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state) 194 { 195 return (crtc_state->active_planes & 196 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0; 197 } 198 199 /* WA Display #0827: Gen9:all */ 200 static void 201 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) 202 { 203 if (enable) 204 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 205 0, DUPS1_GATING_DIS | DUPS2_GATING_DIS); 206 else 207 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 208 DUPS1_GATING_DIS | DUPS2_GATING_DIS, 0); 209 } 210 211 /* Wa_2006604312:icl,ehl */ 212 static void 213 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 214 bool enable) 215 { 216 if (enable) 217 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 0, DPFR_GATING_DIS); 218 else 219 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), DPFR_GATING_DIS, 0); 220 } 221 222 /* Wa_1604331009:icl,jsl,ehl */ 223 static void 224 icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 225 bool enable) 226 { 227 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), CURSOR_GATING_DIS, 228 enable ? CURSOR_GATING_DIS : 0); 229 } 230 231 static bool 232 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state) 233 { 234 return crtc_state->master_transcoder != INVALID_TRANSCODER; 235 } 236 237 static bool 238 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state) 239 { 240 return crtc_state->sync_mode_slaves_mask != 0; 241 } 242 243 bool 244 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state) 245 { 246 return is_trans_port_sync_master(crtc_state) || 247 is_trans_port_sync_slave(crtc_state); 248 } 249 250 static enum pipe bigjoiner_master_pipe(const struct intel_crtc_state *crtc_state) 251 { 252 return ffs(crtc_state->bigjoiner_pipes) - 1; 253 } 254 255 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state) 256 { 257 if (crtc_state->bigjoiner_pipes) 258 return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state)); 259 else 260 return 0; 261 } 262 263 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state) 264 { 265 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 266 267 return crtc_state->bigjoiner_pipes && 268 crtc->pipe != bigjoiner_master_pipe(crtc_state); 269 } 270 271 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state) 272 { 273 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 274 275 return crtc_state->bigjoiner_pipes && 276 crtc->pipe == bigjoiner_master_pipe(crtc_state); 277 } 278 279 static int intel_bigjoiner_num_pipes(const struct intel_crtc_state *crtc_state) 280 { 281 return hweight8(crtc_state->bigjoiner_pipes); 282 } 283 284 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state) 285 { 286 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 287 288 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 289 return intel_crtc_for_pipe(i915, bigjoiner_master_pipe(crtc_state)); 290 else 291 return to_intel_crtc(crtc_state->uapi.crtc); 292 } 293 294 static void 295 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) 296 { 297 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 298 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 299 300 if (DISPLAY_VER(dev_priv) >= 4) { 301 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 302 303 /* Wait for the Pipe State to go off */ 304 if (intel_de_wait_for_clear(dev_priv, PIPECONF(cpu_transcoder), 305 PIPECONF_STATE_ENABLE, 100)) 306 drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n"); 307 } else { 308 intel_wait_for_pipe_scanline_stopped(crtc); 309 } 310 } 311 312 void assert_transcoder(struct drm_i915_private *dev_priv, 313 enum transcoder cpu_transcoder, bool state) 314 { 315 bool cur_state; 316 enum intel_display_power_domain power_domain; 317 intel_wakeref_t wakeref; 318 319 /* we keep both pipes enabled on 830 */ 320 if (IS_I830(dev_priv)) 321 state = true; 322 323 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 324 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 325 if (wakeref) { 326 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); 327 cur_state = !!(val & PIPECONF_ENABLE); 328 329 intel_display_power_put(dev_priv, power_domain, wakeref); 330 } else { 331 cur_state = false; 332 } 333 334 I915_STATE_WARN(cur_state != state, 335 "transcoder %s assertion failure (expected %s, current %s)\n", 336 transcoder_name(cpu_transcoder), 337 str_on_off(state), str_on_off(cur_state)); 338 } 339 340 static void assert_plane(struct intel_plane *plane, bool state) 341 { 342 enum pipe pipe; 343 bool cur_state; 344 345 cur_state = plane->get_hw_state(plane, &pipe); 346 347 I915_STATE_WARN(cur_state != state, 348 "%s assertion failure (expected %s, current %s)\n", 349 plane->base.name, str_on_off(state), 350 str_on_off(cur_state)); 351 } 352 353 #define assert_plane_enabled(p) assert_plane(p, true) 354 #define assert_plane_disabled(p) assert_plane(p, false) 355 356 static void assert_planes_disabled(struct intel_crtc *crtc) 357 { 358 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 359 struct intel_plane *plane; 360 361 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) 362 assert_plane_disabled(plane); 363 } 364 365 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 366 struct intel_digital_port *dig_port, 367 unsigned int expected_mask) 368 { 369 u32 port_mask; 370 i915_reg_t dpll_reg; 371 372 switch (dig_port->base.port) { 373 default: 374 MISSING_CASE(dig_port->base.port); 375 fallthrough; 376 case PORT_B: 377 port_mask = DPLL_PORTB_READY_MASK; 378 dpll_reg = DPLL(0); 379 break; 380 case PORT_C: 381 port_mask = DPLL_PORTC_READY_MASK; 382 dpll_reg = DPLL(0); 383 expected_mask <<= 4; 384 break; 385 case PORT_D: 386 port_mask = DPLL_PORTD_READY_MASK; 387 dpll_reg = DPIO_PHY_STATUS; 388 break; 389 } 390 391 if (intel_de_wait_for_register(dev_priv, dpll_reg, 392 port_mask, expected_mask, 1000)) 393 drm_WARN(&dev_priv->drm, 1, 394 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", 395 dig_port->base.base.base.id, dig_port->base.base.name, 396 intel_de_read(dev_priv, dpll_reg) & port_mask, 397 expected_mask); 398 } 399 400 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) 401 { 402 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 403 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 404 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 405 enum pipe pipe = crtc->pipe; 406 i915_reg_t reg; 407 u32 val; 408 409 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe)); 410 411 assert_planes_disabled(crtc); 412 413 /* 414 * A pipe without a PLL won't actually be able to drive bits from 415 * a plane. On ILK+ the pipe PLLs are integrated, so we don't 416 * need the check. 417 */ 418 if (HAS_GMCH(dev_priv)) { 419 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI)) 420 assert_dsi_pll_enabled(dev_priv); 421 else 422 assert_pll_enabled(dev_priv, pipe); 423 } else { 424 if (new_crtc_state->has_pch_encoder) { 425 /* if driving the PCH, we need FDI enabled */ 426 assert_fdi_rx_pll_enabled(dev_priv, 427 intel_crtc_pch_transcoder(crtc)); 428 assert_fdi_tx_pll_enabled(dev_priv, 429 (enum pipe) cpu_transcoder); 430 } 431 /* FIXME: assert CPU port conditions for SNB+ */ 432 } 433 434 /* Wa_22012358565:adl-p */ 435 if (DISPLAY_VER(dev_priv) == 13) 436 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe), 437 0, PIPE_ARB_USE_PROG_SLOTS); 438 439 reg = PIPECONF(cpu_transcoder); 440 val = intel_de_read(dev_priv, reg); 441 if (val & PIPECONF_ENABLE) { 442 /* we keep both pipes enabled on 830 */ 443 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv)); 444 return; 445 } 446 447 intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE); 448 intel_de_posting_read(dev_priv, reg); 449 450 /* 451 * Until the pipe starts PIPEDSL reads will return a stale value, 452 * which causes an apparent vblank timestamp jump when PIPEDSL 453 * resets to its proper value. That also messes up the frame count 454 * when it's derived from the timestamps. So let's wait for the 455 * pipe to start properly before we call drm_crtc_vblank_on() 456 */ 457 if (intel_crtc_max_vblank_count(new_crtc_state) == 0) 458 intel_wait_for_pipe_scanline_moving(crtc); 459 } 460 461 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) 462 { 463 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 464 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 465 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 466 enum pipe pipe = crtc->pipe; 467 i915_reg_t reg; 468 u32 val; 469 470 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe)); 471 472 /* 473 * Make sure planes won't keep trying to pump pixels to us, 474 * or we might hang the display. 475 */ 476 assert_planes_disabled(crtc); 477 478 reg = PIPECONF(cpu_transcoder); 479 val = intel_de_read(dev_priv, reg); 480 if ((val & PIPECONF_ENABLE) == 0) 481 return; 482 483 /* 484 * Double wide has implications for planes 485 * so best keep it disabled when not needed. 486 */ 487 if (old_crtc_state->double_wide) 488 val &= ~PIPECONF_DOUBLE_WIDE; 489 490 /* Don't disable pipe or pipe PLLs if needed */ 491 if (!IS_I830(dev_priv)) 492 val &= ~PIPECONF_ENABLE; 493 494 if (DISPLAY_VER(dev_priv) >= 14) 495 intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder), 496 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 497 else if (DISPLAY_VER(dev_priv) >= 12) 498 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 499 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 500 501 intel_de_write(dev_priv, reg, val); 502 if ((val & PIPECONF_ENABLE) == 0) 503 intel_wait_for_pipe_off(old_crtc_state); 504 } 505 506 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) 507 { 508 unsigned int size = 0; 509 int i; 510 511 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) 512 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width; 513 514 return size; 515 } 516 517 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info) 518 { 519 unsigned int size = 0; 520 int i; 521 522 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) { 523 unsigned int plane_size; 524 525 if (rem_info->plane[i].linear) 526 plane_size = rem_info->plane[i].size; 527 else 528 plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height; 529 530 if (plane_size == 0) 531 continue; 532 533 if (rem_info->plane_alignment) 534 size = ALIGN(size, rem_info->plane_alignment); 535 536 size += plane_size; 537 } 538 539 return size; 540 } 541 542 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) 543 { 544 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 545 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 546 547 return DISPLAY_VER(dev_priv) < 4 || 548 (plane->fbc && 549 plane_state->view.gtt.type == I915_GTT_VIEW_NORMAL); 550 } 551 552 /* 553 * Convert the x/y offsets into a linear offset. 554 * Only valid with 0/180 degree rotation, which is fine since linear 555 * offset is only used with linear buffers on pre-hsw and tiled buffers 556 * with gen2/3, and 90/270 degree rotations isn't supported on any of them. 557 */ 558 u32 intel_fb_xy_to_linear(int x, int y, 559 const struct intel_plane_state *state, 560 int color_plane) 561 { 562 const struct drm_framebuffer *fb = state->hw.fb; 563 unsigned int cpp = fb->format->cpp[color_plane]; 564 unsigned int pitch = state->view.color_plane[color_plane].mapping_stride; 565 566 return y * pitch + x * cpp; 567 } 568 569 /* 570 * Add the x/y offsets derived from fb->offsets[] to the user 571 * specified plane src x/y offsets. The resulting x/y offsets 572 * specify the start of scanout from the beginning of the gtt mapping. 573 */ 574 void intel_add_fb_offsets(int *x, int *y, 575 const struct intel_plane_state *state, 576 int color_plane) 577 578 { 579 *x += state->view.color_plane[color_plane].x; 580 *y += state->view.color_plane[color_plane].y; 581 } 582 583 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 584 u32 pixel_format, u64 modifier) 585 { 586 struct intel_crtc *crtc; 587 struct intel_plane *plane; 588 589 if (!HAS_DISPLAY(dev_priv)) 590 return 0; 591 592 /* 593 * We assume the primary plane for pipe A has 594 * the highest stride limits of them all, 595 * if in case pipe A is disabled, use the first pipe from pipe_mask. 596 */ 597 crtc = intel_first_crtc(dev_priv); 598 if (!crtc) 599 return 0; 600 601 plane = to_intel_plane(crtc->base.primary); 602 603 return plane->max_stride(plane, pixel_format, modifier, 604 DRM_MODE_ROTATE_0); 605 } 606 607 void intel_set_plane_visible(struct intel_crtc_state *crtc_state, 608 struct intel_plane_state *plane_state, 609 bool visible) 610 { 611 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 612 613 plane_state->uapi.visible = visible; 614 615 if (visible) 616 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base); 617 else 618 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base); 619 } 620 621 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state) 622 { 623 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 624 struct drm_plane *plane; 625 626 /* 627 * Active_planes aliases if multiple "primary" or cursor planes 628 * have been used on the same (or wrong) pipe. plane_mask uses 629 * unique ids, hence we can use that to reconstruct active_planes. 630 */ 631 crtc_state->enabled_planes = 0; 632 crtc_state->active_planes = 0; 633 634 drm_for_each_plane_mask(plane, &dev_priv->drm, 635 crtc_state->uapi.plane_mask) { 636 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id); 637 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id); 638 } 639 } 640 641 void intel_plane_disable_noatomic(struct intel_crtc *crtc, 642 struct intel_plane *plane) 643 { 644 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 645 struct intel_crtc_state *crtc_state = 646 to_intel_crtc_state(crtc->base.state); 647 struct intel_plane_state *plane_state = 648 to_intel_plane_state(plane->base.state); 649 650 drm_dbg_kms(&dev_priv->drm, 651 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n", 652 plane->base.base.id, plane->base.name, 653 crtc->base.base.id, crtc->base.name); 654 655 intel_set_plane_visible(crtc_state, plane_state, false); 656 intel_plane_fixup_bitmasks(crtc_state); 657 crtc_state->data_rate[plane->id] = 0; 658 crtc_state->data_rate_y[plane->id] = 0; 659 crtc_state->rel_data_rate[plane->id] = 0; 660 crtc_state->rel_data_rate_y[plane->id] = 0; 661 crtc_state->min_cdclk[plane->id] = 0; 662 663 if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 && 664 hsw_ips_disable(crtc_state)) { 665 crtc_state->ips_enabled = false; 666 intel_crtc_wait_for_next_vblank(crtc); 667 } 668 669 /* 670 * Vblank time updates from the shadow to live plane control register 671 * are blocked if the memory self-refresh mode is active at that 672 * moment. So to make sure the plane gets truly disabled, disable 673 * first the self-refresh mode. The self-refresh enable bit in turn 674 * will be checked/applied by the HW only at the next frame start 675 * event which is after the vblank start event, so we need to have a 676 * wait-for-vblank between disabling the plane and the pipe. 677 */ 678 if (HAS_GMCH(dev_priv) && 679 intel_set_memory_cxsr(dev_priv, false)) 680 intel_crtc_wait_for_next_vblank(crtc); 681 682 /* 683 * Gen2 reports pipe underruns whenever all planes are disabled. 684 * So disable underrun reporting before all the planes get disabled. 685 */ 686 if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes) 687 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); 688 689 intel_plane_disable_arm(plane, crtc_state); 690 intel_crtc_wait_for_next_vblank(crtc); 691 } 692 693 unsigned int 694 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state) 695 { 696 int x = 0, y = 0; 697 698 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, 699 plane_state->view.color_plane[0].offset, 0); 700 701 return y; 702 } 703 704 static int 705 intel_display_commit_duplicated_state(struct intel_atomic_state *state, 706 struct drm_modeset_acquire_ctx *ctx) 707 { 708 struct drm_i915_private *i915 = to_i915(state->base.dev); 709 int ret; 710 711 ret = drm_atomic_helper_commit_duplicated_state(&state->base, ctx); 712 713 drm_WARN_ON(&i915->drm, ret == -EDEADLK); 714 715 return ret; 716 } 717 718 static int 719 __intel_display_resume(struct drm_i915_private *i915, 720 struct drm_atomic_state *state, 721 struct drm_modeset_acquire_ctx *ctx) 722 { 723 struct drm_crtc_state *crtc_state; 724 struct drm_crtc *crtc; 725 int i; 726 727 intel_modeset_setup_hw_state(i915, ctx); 728 intel_vga_redisable(i915); 729 730 if (!state) 731 return 0; 732 733 /* 734 * We've duplicated the state, pointers to the old state are invalid. 735 * 736 * Don't attempt to use the old state until we commit the duplicated state. 737 */ 738 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 739 /* 740 * Force recalculation even if we restore 741 * current state. With fast modeset this may not result 742 * in a modeset when the state is compatible. 743 */ 744 crtc_state->mode_changed = true; 745 } 746 747 /* ignore any reset values/BIOS leftovers in the WM registers */ 748 if (!HAS_GMCH(i915)) 749 to_intel_atomic_state(state)->skip_intermediate_wm = true; 750 751 return intel_display_commit_duplicated_state(to_intel_atomic_state(state), ctx); 752 } 753 754 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) 755 { 756 return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display && 757 intel_has_gpu_reset(to_gt(dev_priv))); 758 } 759 760 void intel_display_prepare_reset(struct drm_i915_private *dev_priv) 761 { 762 struct drm_modeset_acquire_ctx *ctx = &dev_priv->display.restore.reset_ctx; 763 struct drm_atomic_state *state; 764 int ret; 765 766 if (!HAS_DISPLAY(dev_priv)) 767 return; 768 769 /* reset doesn't touch the display */ 770 if (!dev_priv->params.force_reset_modeset_test && 771 !gpu_reset_clobbers_display(dev_priv)) 772 return; 773 774 /* We have a modeset vs reset deadlock, defensively unbreak it. */ 775 set_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags); 776 smp_mb__after_atomic(); 777 wake_up_bit(&to_gt(dev_priv)->reset.flags, I915_RESET_MODESET); 778 779 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) { 780 drm_dbg_kms(&dev_priv->drm, 781 "Modeset potentially stuck, unbreaking through wedging\n"); 782 intel_gt_set_wedged(to_gt(dev_priv)); 783 } 784 785 /* 786 * Need mode_config.mutex so that we don't 787 * trample ongoing ->detect() and whatnot. 788 */ 789 mutex_lock(&dev_priv->drm.mode_config.mutex); 790 drm_modeset_acquire_init(ctx, 0); 791 while (1) { 792 ret = drm_modeset_lock_all_ctx(&dev_priv->drm, ctx); 793 if (ret != -EDEADLK) 794 break; 795 796 drm_modeset_backoff(ctx); 797 } 798 /* 799 * Disabling the crtcs gracefully seems nicer. Also the 800 * g33 docs say we should at least disable all the planes. 801 */ 802 state = drm_atomic_helper_duplicate_state(&dev_priv->drm, ctx); 803 if (IS_ERR(state)) { 804 ret = PTR_ERR(state); 805 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n", 806 ret); 807 return; 808 } 809 810 ret = drm_atomic_helper_disable_all(&dev_priv->drm, ctx); 811 if (ret) { 812 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", 813 ret); 814 drm_atomic_state_put(state); 815 return; 816 } 817 818 dev_priv->display.restore.modeset_state = state; 819 state->acquire_ctx = ctx; 820 } 821 822 void intel_display_finish_reset(struct drm_i915_private *i915) 823 { 824 struct drm_modeset_acquire_ctx *ctx = &i915->display.restore.reset_ctx; 825 struct drm_atomic_state *state; 826 int ret; 827 828 if (!HAS_DISPLAY(i915)) 829 return; 830 831 /* reset doesn't touch the display */ 832 if (!test_bit(I915_RESET_MODESET, &to_gt(i915)->reset.flags)) 833 return; 834 835 state = fetch_and_zero(&i915->display.restore.modeset_state); 836 if (!state) 837 goto unlock; 838 839 /* reset doesn't touch the display */ 840 if (!gpu_reset_clobbers_display(i915)) { 841 /* for testing only restore the display */ 842 ret = intel_display_commit_duplicated_state(to_intel_atomic_state(state), ctx); 843 if (ret) 844 drm_err(&i915->drm, 845 "Restoring old state failed with %i\n", ret); 846 } else { 847 /* 848 * The display has been reset as well, 849 * so need a full re-initialization. 850 */ 851 intel_pps_unlock_regs_wa(i915); 852 intel_modeset_init_hw(i915); 853 intel_init_clock_gating(i915); 854 intel_hpd_init(i915); 855 856 ret = __intel_display_resume(i915, state, ctx); 857 if (ret) 858 drm_err(&i915->drm, 859 "Restoring old state failed with %i\n", ret); 860 861 intel_hpd_poll_disable(i915); 862 } 863 864 drm_atomic_state_put(state); 865 unlock: 866 drm_modeset_drop_locks(ctx); 867 drm_modeset_acquire_fini(ctx); 868 mutex_unlock(&i915->drm.mode_config.mutex); 869 870 clear_bit_unlock(I915_RESET_MODESET, &to_gt(i915)->reset.flags); 871 } 872 873 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) 874 { 875 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 876 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 877 enum pipe pipe = crtc->pipe; 878 u32 tmp; 879 880 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe)); 881 882 /* 883 * Display WA #1153: icl 884 * enable hardware to bypass the alpha math 885 * and rounding for per-pixel values 00 and 0xff 886 */ 887 tmp |= PER_PIXEL_ALPHA_BYPASS_EN; 888 /* 889 * Display WA # 1605353570: icl 890 * Set the pixel rounding bit to 1 for allowing 891 * passthrough of Frame buffer pixels unmodified 892 * across pipe 893 */ 894 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU; 895 896 /* 897 * Underrun recovery must always be disabled on display 13+. 898 * DG2 chicken bit meaning is inverted compared to other platforms. 899 */ 900 if (IS_DG2(dev_priv)) 901 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2; 902 else if (DISPLAY_VER(dev_priv) >= 13) 903 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP; 904 905 /* Wa_14010547955:dg2 */ 906 if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER)) 907 tmp |= DG2_RENDER_CCSTAG_4_3_EN; 908 909 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp); 910 } 911 912 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) 913 { 914 struct drm_crtc *crtc; 915 bool cleanup_done; 916 917 drm_for_each_crtc(crtc, &dev_priv->drm) { 918 struct drm_crtc_commit *commit; 919 spin_lock(&crtc->commit_lock); 920 commit = list_first_entry_or_null(&crtc->commit_list, 921 struct drm_crtc_commit, commit_entry); 922 cleanup_done = commit ? 923 try_wait_for_completion(&commit->cleanup_done) : true; 924 spin_unlock(&crtc->commit_lock); 925 926 if (cleanup_done) 927 continue; 928 929 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc)); 930 931 return true; 932 } 933 934 return false; 935 } 936 937 /* 938 * Finds the encoder associated with the given CRTC. This can only be 939 * used when we know that the CRTC isn't feeding multiple encoders! 940 */ 941 struct intel_encoder * 942 intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 943 const struct intel_crtc_state *crtc_state) 944 { 945 const struct drm_connector_state *connector_state; 946 const struct drm_connector *connector; 947 struct intel_encoder *encoder = NULL; 948 struct intel_crtc *master_crtc; 949 int num_encoders = 0; 950 int i; 951 952 master_crtc = intel_master_crtc(crtc_state); 953 954 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 955 if (connector_state->crtc != &master_crtc->base) 956 continue; 957 958 encoder = to_intel_encoder(connector_state->best_encoder); 959 num_encoders++; 960 } 961 962 drm_WARN(encoder->base.dev, num_encoders != 1, 963 "%d encoders for pipe %c\n", 964 num_encoders, pipe_name(master_crtc->pipe)); 965 966 return encoder; 967 } 968 969 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state) 970 { 971 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 972 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 973 const struct drm_rect *dst = &crtc_state->pch_pfit.dst; 974 enum pipe pipe = crtc->pipe; 975 int width = drm_rect_width(dst); 976 int height = drm_rect_height(dst); 977 int x = dst->x1; 978 int y = dst->y1; 979 980 if (!crtc_state->pch_pfit.enabled) 981 return; 982 983 /* Force use of hard-coded filter coefficients 984 * as some pre-programmed values are broken, 985 * e.g. x201. 986 */ 987 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) 988 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 989 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe)); 990 else 991 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 992 PF_FILTER_MED_3x3); 993 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), x << 16 | y); 994 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), width << 16 | height); 995 } 996 997 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc) 998 { 999 if (crtc->overlay) 1000 (void) intel_overlay_switch_off(crtc->overlay); 1001 1002 /* Let userspace switch the overlay on again. In most cases userspace 1003 * has to recompute where to put it anyway. 1004 */ 1005 } 1006 1007 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state) 1008 { 1009 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1010 1011 if (!crtc_state->nv12_planes) 1012 return false; 1013 1014 /* WA Display #0827: Gen9:all */ 1015 if (DISPLAY_VER(dev_priv) == 9) 1016 return true; 1017 1018 return false; 1019 } 1020 1021 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state) 1022 { 1023 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1024 1025 /* Wa_2006604312:icl,ehl */ 1026 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11) 1027 return true; 1028 1029 return false; 1030 } 1031 1032 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state) 1033 { 1034 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1035 1036 /* Wa_1604331009:icl,jsl,ehl */ 1037 if (is_hdr_mode(crtc_state) && 1038 crtc_state->active_planes & BIT(PLANE_CURSOR) && 1039 DISPLAY_VER(dev_priv) == 11) 1040 return true; 1041 1042 return false; 1043 } 1044 1045 static void intel_async_flip_vtd_wa(struct drm_i915_private *i915, 1046 enum pipe pipe, bool enable) 1047 { 1048 if (DISPLAY_VER(i915) == 9) { 1049 /* 1050 * "Plane N strech max must be programmed to 11b (x1) 1051 * when Async flips are enabled on that plane." 1052 */ 1053 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 1054 SKL_PLANE1_STRETCH_MAX_MASK, 1055 enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8); 1056 } else { 1057 /* Also needed on HSW/BDW albeit undocumented */ 1058 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 1059 HSW_PRI_STRETCH_MAX_MASK, 1060 enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8); 1061 } 1062 } 1063 1064 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state) 1065 { 1066 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1067 1068 return crtc_state->uapi.async_flip && i915_vtd_active(i915) && 1069 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915)); 1070 } 1071 1072 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state, 1073 const struct intel_crtc_state *new_crtc_state) 1074 { 1075 return (!old_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)) && 1076 new_crtc_state->active_planes; 1077 } 1078 1079 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state, 1080 const struct intel_crtc_state *new_crtc_state) 1081 { 1082 return old_crtc_state->active_planes && 1083 (!new_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)); 1084 } 1085 1086 static void intel_post_plane_update(struct intel_atomic_state *state, 1087 struct intel_crtc *crtc) 1088 { 1089 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1090 const struct intel_crtc_state *old_crtc_state = 1091 intel_atomic_get_old_crtc_state(state, crtc); 1092 const struct intel_crtc_state *new_crtc_state = 1093 intel_atomic_get_new_crtc_state(state, crtc); 1094 enum pipe pipe = crtc->pipe; 1095 1096 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); 1097 1098 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) 1099 intel_update_watermarks(dev_priv); 1100 1101 intel_fbc_post_update(state, crtc); 1102 1103 if (needs_async_flip_vtd_wa(old_crtc_state) && 1104 !needs_async_flip_vtd_wa(new_crtc_state)) 1105 intel_async_flip_vtd_wa(dev_priv, pipe, false); 1106 1107 if (needs_nv12_wa(old_crtc_state) && 1108 !needs_nv12_wa(new_crtc_state)) 1109 skl_wa_827(dev_priv, pipe, false); 1110 1111 if (needs_scalerclk_wa(old_crtc_state) && 1112 !needs_scalerclk_wa(new_crtc_state)) 1113 icl_wa_scalerclkgating(dev_priv, pipe, false); 1114 1115 if (needs_cursorclk_wa(old_crtc_state) && 1116 !needs_cursorclk_wa(new_crtc_state)) 1117 icl_wa_cursorclkgating(dev_priv, pipe, false); 1118 } 1119 1120 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state, 1121 struct intel_crtc *crtc) 1122 { 1123 const struct intel_crtc_state *crtc_state = 1124 intel_atomic_get_new_crtc_state(state, crtc); 1125 u8 update_planes = crtc_state->update_planes; 1126 const struct intel_plane_state *plane_state; 1127 struct intel_plane *plane; 1128 int i; 1129 1130 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1131 if (plane->pipe == crtc->pipe && 1132 update_planes & BIT(plane->id)) 1133 plane->enable_flip_done(plane); 1134 } 1135 } 1136 1137 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state, 1138 struct intel_crtc *crtc) 1139 { 1140 const struct intel_crtc_state *crtc_state = 1141 intel_atomic_get_new_crtc_state(state, crtc); 1142 u8 update_planes = crtc_state->update_planes; 1143 const struct intel_plane_state *plane_state; 1144 struct intel_plane *plane; 1145 int i; 1146 1147 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1148 if (plane->pipe == crtc->pipe && 1149 update_planes & BIT(plane->id)) 1150 plane->disable_flip_done(plane); 1151 } 1152 } 1153 1154 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state, 1155 struct intel_crtc *crtc) 1156 { 1157 const struct intel_crtc_state *old_crtc_state = 1158 intel_atomic_get_old_crtc_state(state, crtc); 1159 const struct intel_crtc_state *new_crtc_state = 1160 intel_atomic_get_new_crtc_state(state, crtc); 1161 u8 disable_async_flip_planes = old_crtc_state->async_flip_planes & 1162 ~new_crtc_state->async_flip_planes; 1163 const struct intel_plane_state *old_plane_state; 1164 struct intel_plane *plane; 1165 bool need_vbl_wait = false; 1166 int i; 1167 1168 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1169 if (plane->need_async_flip_disable_wa && 1170 plane->pipe == crtc->pipe && 1171 disable_async_flip_planes & BIT(plane->id)) { 1172 /* 1173 * Apart from the async flip bit we want to 1174 * preserve the old state for the plane. 1175 */ 1176 plane->async_flip(plane, old_crtc_state, 1177 old_plane_state, false); 1178 need_vbl_wait = true; 1179 } 1180 } 1181 1182 if (need_vbl_wait) 1183 intel_crtc_wait_for_next_vblank(crtc); 1184 } 1185 1186 static void intel_pre_plane_update(struct intel_atomic_state *state, 1187 struct intel_crtc *crtc) 1188 { 1189 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1190 const struct intel_crtc_state *old_crtc_state = 1191 intel_atomic_get_old_crtc_state(state, crtc); 1192 const struct intel_crtc_state *new_crtc_state = 1193 intel_atomic_get_new_crtc_state(state, crtc); 1194 enum pipe pipe = crtc->pipe; 1195 1196 intel_drrs_deactivate(old_crtc_state); 1197 1198 intel_psr_pre_plane_update(state, crtc); 1199 1200 if (hsw_ips_pre_update(state, crtc)) 1201 intel_crtc_wait_for_next_vblank(crtc); 1202 1203 if (intel_fbc_pre_update(state, crtc)) 1204 intel_crtc_wait_for_next_vblank(crtc); 1205 1206 if (!needs_async_flip_vtd_wa(old_crtc_state) && 1207 needs_async_flip_vtd_wa(new_crtc_state)) 1208 intel_async_flip_vtd_wa(dev_priv, pipe, true); 1209 1210 /* Display WA 827 */ 1211 if (!needs_nv12_wa(old_crtc_state) && 1212 needs_nv12_wa(new_crtc_state)) 1213 skl_wa_827(dev_priv, pipe, true); 1214 1215 /* Wa_2006604312:icl,ehl */ 1216 if (!needs_scalerclk_wa(old_crtc_state) && 1217 needs_scalerclk_wa(new_crtc_state)) 1218 icl_wa_scalerclkgating(dev_priv, pipe, true); 1219 1220 /* Wa_1604331009:icl,jsl,ehl */ 1221 if (!needs_cursorclk_wa(old_crtc_state) && 1222 needs_cursorclk_wa(new_crtc_state)) 1223 icl_wa_cursorclkgating(dev_priv, pipe, true); 1224 1225 /* 1226 * Vblank time updates from the shadow to live plane control register 1227 * are blocked if the memory self-refresh mode is active at that 1228 * moment. So to make sure the plane gets truly disabled, disable 1229 * first the self-refresh mode. The self-refresh enable bit in turn 1230 * will be checked/applied by the HW only at the next frame start 1231 * event which is after the vblank start event, so we need to have a 1232 * wait-for-vblank between disabling the plane and the pipe. 1233 */ 1234 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active && 1235 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) 1236 intel_crtc_wait_for_next_vblank(crtc); 1237 1238 /* 1239 * IVB workaround: must disable low power watermarks for at least 1240 * one frame before enabling scaling. LP watermarks can be re-enabled 1241 * when scaling is disabled. 1242 * 1243 * WaCxSRDisabledForSpriteScaling:ivb 1244 */ 1245 if (old_crtc_state->hw.active && 1246 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv)) 1247 intel_crtc_wait_for_next_vblank(crtc); 1248 1249 /* 1250 * If we're doing a modeset we don't need to do any 1251 * pre-vblank watermark programming here. 1252 */ 1253 if (!intel_crtc_needs_modeset(new_crtc_state)) { 1254 /* 1255 * For platforms that support atomic watermarks, program the 1256 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these 1257 * will be the intermediate values that are safe for both pre- and 1258 * post- vblank; when vblank happens, the 'active' values will be set 1259 * to the final 'target' values and we'll do this again to get the 1260 * optimal watermarks. For gen9+ platforms, the values we program here 1261 * will be the final target values which will get automatically latched 1262 * at vblank time; no further programming will be necessary. 1263 * 1264 * If a platform hasn't been transitioned to atomic watermarks yet, 1265 * we'll continue to update watermarks the old way, if flags tell 1266 * us to. 1267 */ 1268 if (!intel_initial_watermarks(state, crtc)) 1269 if (new_crtc_state->update_wm_pre) 1270 intel_update_watermarks(dev_priv); 1271 } 1272 1273 /* 1274 * Gen2 reports pipe underruns whenever all planes are disabled. 1275 * So disable underrun reporting before all the planes get disabled. 1276 * 1277 * We do this after .initial_watermarks() so that we have a 1278 * chance of catching underruns with the intermediate watermarks 1279 * vs. the old plane configuration. 1280 */ 1281 if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state)) 1282 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1283 1284 /* 1285 * WA for platforms where async address update enable bit 1286 * is double buffered and only latched at start of vblank. 1287 */ 1288 if (old_crtc_state->async_flip_planes & ~new_crtc_state->async_flip_planes) 1289 intel_crtc_async_flip_disable_wa(state, crtc); 1290 } 1291 1292 static void intel_crtc_disable_planes(struct intel_atomic_state *state, 1293 struct intel_crtc *crtc) 1294 { 1295 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1296 const struct intel_crtc_state *new_crtc_state = 1297 intel_atomic_get_new_crtc_state(state, crtc); 1298 unsigned int update_mask = new_crtc_state->update_planes; 1299 const struct intel_plane_state *old_plane_state; 1300 struct intel_plane *plane; 1301 unsigned fb_bits = 0; 1302 int i; 1303 1304 intel_crtc_dpms_overlay_disable(crtc); 1305 1306 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1307 if (crtc->pipe != plane->pipe || 1308 !(update_mask & BIT(plane->id))) 1309 continue; 1310 1311 intel_plane_disable_arm(plane, new_crtc_state); 1312 1313 if (old_plane_state->uapi.visible) 1314 fb_bits |= plane->frontbuffer_bit; 1315 } 1316 1317 intel_frontbuffer_flip(dev_priv, fb_bits); 1318 } 1319 1320 /* 1321 * intel_connector_primary_encoder - get the primary encoder for a connector 1322 * @connector: connector for which to return the encoder 1323 * 1324 * Returns the primary encoder for a connector. There is a 1:1 mapping from 1325 * all connectors to their encoder, except for DP-MST connectors which have 1326 * both a virtual and a primary encoder. These DP-MST primary encoders can be 1327 * pointed to by as many DP-MST connectors as there are pipes. 1328 */ 1329 static struct intel_encoder * 1330 intel_connector_primary_encoder(struct intel_connector *connector) 1331 { 1332 struct intel_encoder *encoder; 1333 1334 if (connector->mst_port) 1335 return &dp_to_dig_port(connector->mst_port)->base; 1336 1337 encoder = intel_attached_encoder(connector); 1338 drm_WARN_ON(connector->base.dev, !encoder); 1339 1340 return encoder; 1341 } 1342 1343 static void intel_encoders_update_prepare(struct intel_atomic_state *state) 1344 { 1345 struct drm_i915_private *i915 = to_i915(state->base.dev); 1346 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 1347 struct intel_crtc *crtc; 1348 struct drm_connector_state *new_conn_state; 1349 struct drm_connector *connector; 1350 int i; 1351 1352 /* 1353 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits. 1354 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook. 1355 */ 1356 if (i915->display.dpll.mgr) { 1357 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1358 if (intel_crtc_needs_modeset(new_crtc_state)) 1359 continue; 1360 1361 new_crtc_state->shared_dpll = old_crtc_state->shared_dpll; 1362 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state; 1363 } 1364 } 1365 1366 if (!state->modeset) 1367 return; 1368 1369 for_each_new_connector_in_state(&state->base, connector, new_conn_state, 1370 i) { 1371 struct intel_connector *intel_connector; 1372 struct intel_encoder *encoder; 1373 struct intel_crtc *crtc; 1374 1375 if (!intel_connector_needs_modeset(state, connector)) 1376 continue; 1377 1378 intel_connector = to_intel_connector(connector); 1379 encoder = intel_connector_primary_encoder(intel_connector); 1380 if (!encoder->update_prepare) 1381 continue; 1382 1383 crtc = new_conn_state->crtc ? 1384 to_intel_crtc(new_conn_state->crtc) : NULL; 1385 encoder->update_prepare(state, encoder, crtc); 1386 } 1387 } 1388 1389 static void intel_encoders_update_complete(struct intel_atomic_state *state) 1390 { 1391 struct drm_connector_state *new_conn_state; 1392 struct drm_connector *connector; 1393 int i; 1394 1395 if (!state->modeset) 1396 return; 1397 1398 for_each_new_connector_in_state(&state->base, connector, new_conn_state, 1399 i) { 1400 struct intel_connector *intel_connector; 1401 struct intel_encoder *encoder; 1402 struct intel_crtc *crtc; 1403 1404 if (!intel_connector_needs_modeset(state, connector)) 1405 continue; 1406 1407 intel_connector = to_intel_connector(connector); 1408 encoder = intel_connector_primary_encoder(intel_connector); 1409 if (!encoder->update_complete) 1410 continue; 1411 1412 crtc = new_conn_state->crtc ? 1413 to_intel_crtc(new_conn_state->crtc) : NULL; 1414 encoder->update_complete(state, encoder, crtc); 1415 } 1416 } 1417 1418 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state, 1419 struct intel_crtc *crtc) 1420 { 1421 const struct intel_crtc_state *crtc_state = 1422 intel_atomic_get_new_crtc_state(state, crtc); 1423 const struct drm_connector_state *conn_state; 1424 struct drm_connector *conn; 1425 int i; 1426 1427 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1428 struct intel_encoder *encoder = 1429 to_intel_encoder(conn_state->best_encoder); 1430 1431 if (conn_state->crtc != &crtc->base) 1432 continue; 1433 1434 if (encoder->pre_pll_enable) 1435 encoder->pre_pll_enable(state, encoder, 1436 crtc_state, conn_state); 1437 } 1438 } 1439 1440 static void intel_encoders_pre_enable(struct intel_atomic_state *state, 1441 struct intel_crtc *crtc) 1442 { 1443 const struct intel_crtc_state *crtc_state = 1444 intel_atomic_get_new_crtc_state(state, crtc); 1445 const struct drm_connector_state *conn_state; 1446 struct drm_connector *conn; 1447 int i; 1448 1449 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1450 struct intel_encoder *encoder = 1451 to_intel_encoder(conn_state->best_encoder); 1452 1453 if (conn_state->crtc != &crtc->base) 1454 continue; 1455 1456 if (encoder->pre_enable) 1457 encoder->pre_enable(state, encoder, 1458 crtc_state, conn_state); 1459 } 1460 } 1461 1462 static void intel_encoders_enable(struct intel_atomic_state *state, 1463 struct intel_crtc *crtc) 1464 { 1465 const struct intel_crtc_state *crtc_state = 1466 intel_atomic_get_new_crtc_state(state, crtc); 1467 const struct drm_connector_state *conn_state; 1468 struct drm_connector *conn; 1469 int i; 1470 1471 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1472 struct intel_encoder *encoder = 1473 to_intel_encoder(conn_state->best_encoder); 1474 1475 if (conn_state->crtc != &crtc->base) 1476 continue; 1477 1478 if (encoder->enable) 1479 encoder->enable(state, encoder, 1480 crtc_state, conn_state); 1481 intel_opregion_notify_encoder(encoder, true); 1482 } 1483 } 1484 1485 static void intel_encoders_disable(struct intel_atomic_state *state, 1486 struct intel_crtc *crtc) 1487 { 1488 const struct intel_crtc_state *old_crtc_state = 1489 intel_atomic_get_old_crtc_state(state, crtc); 1490 const struct drm_connector_state *old_conn_state; 1491 struct drm_connector *conn; 1492 int i; 1493 1494 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1495 struct intel_encoder *encoder = 1496 to_intel_encoder(old_conn_state->best_encoder); 1497 1498 if (old_conn_state->crtc != &crtc->base) 1499 continue; 1500 1501 intel_opregion_notify_encoder(encoder, false); 1502 if (encoder->disable) 1503 encoder->disable(state, encoder, 1504 old_crtc_state, old_conn_state); 1505 } 1506 } 1507 1508 static void intel_encoders_post_disable(struct intel_atomic_state *state, 1509 struct intel_crtc *crtc) 1510 { 1511 const struct intel_crtc_state *old_crtc_state = 1512 intel_atomic_get_old_crtc_state(state, crtc); 1513 const struct drm_connector_state *old_conn_state; 1514 struct drm_connector *conn; 1515 int i; 1516 1517 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1518 struct intel_encoder *encoder = 1519 to_intel_encoder(old_conn_state->best_encoder); 1520 1521 if (old_conn_state->crtc != &crtc->base) 1522 continue; 1523 1524 if (encoder->post_disable) 1525 encoder->post_disable(state, encoder, 1526 old_crtc_state, old_conn_state); 1527 } 1528 } 1529 1530 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state, 1531 struct intel_crtc *crtc) 1532 { 1533 const struct intel_crtc_state *old_crtc_state = 1534 intel_atomic_get_old_crtc_state(state, crtc); 1535 const struct drm_connector_state *old_conn_state; 1536 struct drm_connector *conn; 1537 int i; 1538 1539 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1540 struct intel_encoder *encoder = 1541 to_intel_encoder(old_conn_state->best_encoder); 1542 1543 if (old_conn_state->crtc != &crtc->base) 1544 continue; 1545 1546 if (encoder->post_pll_disable) 1547 encoder->post_pll_disable(state, encoder, 1548 old_crtc_state, old_conn_state); 1549 } 1550 } 1551 1552 static void intel_encoders_update_pipe(struct intel_atomic_state *state, 1553 struct intel_crtc *crtc) 1554 { 1555 const struct intel_crtc_state *crtc_state = 1556 intel_atomic_get_new_crtc_state(state, crtc); 1557 const struct drm_connector_state *conn_state; 1558 struct drm_connector *conn; 1559 int i; 1560 1561 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1562 struct intel_encoder *encoder = 1563 to_intel_encoder(conn_state->best_encoder); 1564 1565 if (conn_state->crtc != &crtc->base) 1566 continue; 1567 1568 if (encoder->update_pipe) 1569 encoder->update_pipe(state, encoder, 1570 crtc_state, conn_state); 1571 } 1572 } 1573 1574 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state) 1575 { 1576 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1577 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 1578 1579 plane->disable_arm(plane, crtc_state); 1580 } 1581 1582 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1583 { 1584 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1585 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1586 1587 if (crtc_state->has_pch_encoder) { 1588 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1589 &crtc_state->fdi_m_n); 1590 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1591 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1592 &crtc_state->dp_m_n); 1593 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1594 &crtc_state->dp_m2_n2); 1595 } 1596 1597 intel_set_transcoder_timings(crtc_state); 1598 1599 ilk_set_pipeconf(crtc_state); 1600 } 1601 1602 static void ilk_crtc_enable(struct intel_atomic_state *state, 1603 struct intel_crtc *crtc) 1604 { 1605 const struct intel_crtc_state *new_crtc_state = 1606 intel_atomic_get_new_crtc_state(state, crtc); 1607 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1608 enum pipe pipe = crtc->pipe; 1609 1610 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1611 return; 1612 1613 /* 1614 * Sometimes spurious CPU pipe underruns happen during FDI 1615 * training, at least with VGA+HDMI cloning. Suppress them. 1616 * 1617 * On ILK we get an occasional spurious CPU pipe underruns 1618 * between eDP port A enable and vdd enable. Also PCH port 1619 * enable seems to result in the occasional CPU pipe underrun. 1620 * 1621 * Spurious PCH underruns also occur during PCH enabling. 1622 */ 1623 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1624 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 1625 1626 ilk_configure_cpu_transcoder(new_crtc_state); 1627 1628 intel_set_pipe_src_size(new_crtc_state); 1629 1630 crtc->active = true; 1631 1632 intel_encoders_pre_enable(state, crtc); 1633 1634 if (new_crtc_state->has_pch_encoder) { 1635 ilk_pch_pre_enable(state, crtc); 1636 } else { 1637 assert_fdi_tx_disabled(dev_priv, pipe); 1638 assert_fdi_rx_disabled(dev_priv, pipe); 1639 } 1640 1641 ilk_pfit_enable(new_crtc_state); 1642 1643 /* 1644 * On ILK+ LUT must be loaded before the pipe is running but with 1645 * clocks enabled 1646 */ 1647 intel_color_load_luts(new_crtc_state); 1648 intel_color_commit_noarm(new_crtc_state); 1649 intel_color_commit_arm(new_crtc_state); 1650 /* update DSPCNTR to configure gamma for pipe bottom color */ 1651 intel_disable_primary_plane(new_crtc_state); 1652 1653 intel_initial_watermarks(state, crtc); 1654 intel_enable_transcoder(new_crtc_state); 1655 1656 if (new_crtc_state->has_pch_encoder) 1657 ilk_pch_enable(state, crtc); 1658 1659 intel_crtc_vblank_on(new_crtc_state); 1660 1661 intel_encoders_enable(state, crtc); 1662 1663 if (HAS_PCH_CPT(dev_priv)) 1664 intel_wait_for_pipe_scanline_moving(crtc); 1665 1666 /* 1667 * Must wait for vblank to avoid spurious PCH FIFO underruns. 1668 * And a second vblank wait is needed at least on ILK with 1669 * some interlaced HDMI modes. Let's do the double wait always 1670 * in case there are more corner cases we don't know about. 1671 */ 1672 if (new_crtc_state->has_pch_encoder) { 1673 intel_crtc_wait_for_next_vblank(crtc); 1674 intel_crtc_wait_for_next_vblank(crtc); 1675 } 1676 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1677 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 1678 } 1679 1680 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, 1681 enum pipe pipe, bool apply) 1682 { 1683 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)); 1684 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS; 1685 1686 if (apply) 1687 val |= mask; 1688 else 1689 val &= ~mask; 1690 1691 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val); 1692 } 1693 1694 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state) 1695 { 1696 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1697 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1698 1699 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe), 1700 HSW_LINETIME(crtc_state->linetime) | 1701 HSW_IPS_LINETIME(crtc_state->ips_linetime)); 1702 } 1703 1704 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) 1705 { 1706 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1707 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1708 enum transcoder transcoder = crtc_state->cpu_transcoder; 1709 i915_reg_t reg = DISPLAY_VER(dev_priv) >= 14 ? MTL_CHICKEN_TRANS(transcoder) : 1710 CHICKEN_TRANS(transcoder); 1711 1712 intel_de_rmw(dev_priv, reg, 1713 HSW_FRAME_START_DELAY_MASK, 1714 HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1)); 1715 } 1716 1717 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state, 1718 const struct intel_crtc_state *crtc_state) 1719 { 1720 struct intel_crtc *master_crtc = intel_master_crtc(crtc_state); 1721 1722 /* 1723 * Enable sequence steps 1-7 on bigjoiner master 1724 */ 1725 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1726 intel_encoders_pre_pll_enable(state, master_crtc); 1727 1728 if (crtc_state->shared_dpll) 1729 intel_enable_shared_dpll(crtc_state); 1730 1731 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1732 intel_encoders_pre_enable(state, master_crtc); 1733 } 1734 1735 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1736 { 1737 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1738 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1739 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1740 1741 if (crtc_state->has_pch_encoder) { 1742 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1743 &crtc_state->fdi_m_n); 1744 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1745 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1746 &crtc_state->dp_m_n); 1747 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1748 &crtc_state->dp_m2_n2); 1749 } 1750 1751 intel_set_transcoder_timings(crtc_state); 1752 1753 if (cpu_transcoder != TRANSCODER_EDP) 1754 intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder), 1755 crtc_state->pixel_multiplier - 1); 1756 1757 hsw_set_frame_start_delay(crtc_state); 1758 1759 hsw_set_transconf(crtc_state); 1760 } 1761 1762 static void hsw_crtc_enable(struct intel_atomic_state *state, 1763 struct intel_crtc *crtc) 1764 { 1765 const struct intel_crtc_state *new_crtc_state = 1766 intel_atomic_get_new_crtc_state(state, crtc); 1767 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1768 enum pipe pipe = crtc->pipe, hsw_workaround_pipe; 1769 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 1770 bool psl_clkgate_wa; 1771 1772 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1773 return; 1774 1775 intel_dmc_enable_pipe(dev_priv, crtc->pipe); 1776 1777 if (!new_crtc_state->bigjoiner_pipes) { 1778 intel_encoders_pre_pll_enable(state, crtc); 1779 1780 if (new_crtc_state->shared_dpll) 1781 intel_enable_shared_dpll(new_crtc_state); 1782 1783 intel_encoders_pre_enable(state, crtc); 1784 } else { 1785 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state); 1786 } 1787 1788 intel_dsc_enable(new_crtc_state); 1789 1790 if (DISPLAY_VER(dev_priv) >= 13) 1791 intel_uncompressed_joiner_enable(new_crtc_state); 1792 1793 intel_set_pipe_src_size(new_crtc_state); 1794 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 1795 bdw_set_pipemisc(new_crtc_state); 1796 1797 if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) && 1798 !transcoder_is_dsi(cpu_transcoder)) 1799 hsw_configure_cpu_transcoder(new_crtc_state); 1800 1801 crtc->active = true; 1802 1803 /* Display WA #1180: WaDisableScalarClockGating: glk */ 1804 psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 && 1805 new_crtc_state->pch_pfit.enabled; 1806 if (psl_clkgate_wa) 1807 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true); 1808 1809 if (DISPLAY_VER(dev_priv) >= 9) 1810 skl_pfit_enable(new_crtc_state); 1811 else 1812 ilk_pfit_enable(new_crtc_state); 1813 1814 /* 1815 * On ILK+ LUT must be loaded before the pipe is running but with 1816 * clocks enabled 1817 */ 1818 intel_color_load_luts(new_crtc_state); 1819 intel_color_commit_noarm(new_crtc_state); 1820 intel_color_commit_arm(new_crtc_state); 1821 /* update DSPCNTR to configure gamma/csc for pipe bottom color */ 1822 if (DISPLAY_VER(dev_priv) < 9) 1823 intel_disable_primary_plane(new_crtc_state); 1824 1825 hsw_set_linetime_wm(new_crtc_state); 1826 1827 if (DISPLAY_VER(dev_priv) >= 11) 1828 icl_set_pipe_chicken(new_crtc_state); 1829 1830 intel_initial_watermarks(state, crtc); 1831 1832 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 1833 intel_crtc_vblank_on(new_crtc_state); 1834 1835 intel_encoders_enable(state, crtc); 1836 1837 if (psl_clkgate_wa) { 1838 intel_crtc_wait_for_next_vblank(crtc); 1839 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false); 1840 } 1841 1842 /* If we change the relative order between pipe/planes enabling, we need 1843 * to change the workaround. */ 1844 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe; 1845 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { 1846 struct intel_crtc *wa_crtc; 1847 1848 wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe); 1849 1850 intel_crtc_wait_for_next_vblank(wa_crtc); 1851 intel_crtc_wait_for_next_vblank(wa_crtc); 1852 } 1853 } 1854 1855 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state) 1856 { 1857 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1858 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1859 enum pipe pipe = crtc->pipe; 1860 1861 /* To avoid upsetting the power well on haswell only disable the pfit if 1862 * it's in use. The hw state code will make sure we get this right. */ 1863 if (!old_crtc_state->pch_pfit.enabled) 1864 return; 1865 1866 intel_de_write_fw(dev_priv, PF_CTL(pipe), 0); 1867 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0); 1868 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0); 1869 } 1870 1871 static void ilk_crtc_disable(struct intel_atomic_state *state, 1872 struct intel_crtc *crtc) 1873 { 1874 const struct intel_crtc_state *old_crtc_state = 1875 intel_atomic_get_old_crtc_state(state, crtc); 1876 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1877 enum pipe pipe = crtc->pipe; 1878 1879 /* 1880 * Sometimes spurious CPU pipe underruns happen when the 1881 * pipe is already disabled, but FDI RX/TX is still enabled. 1882 * Happens at least with VGA+HDMI cloning. Suppress them. 1883 */ 1884 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1885 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 1886 1887 intel_encoders_disable(state, crtc); 1888 1889 intel_crtc_vblank_off(old_crtc_state); 1890 1891 intel_disable_transcoder(old_crtc_state); 1892 1893 ilk_pfit_disable(old_crtc_state); 1894 1895 if (old_crtc_state->has_pch_encoder) 1896 ilk_pch_disable(state, crtc); 1897 1898 intel_encoders_post_disable(state, crtc); 1899 1900 if (old_crtc_state->has_pch_encoder) 1901 ilk_pch_post_disable(state, crtc); 1902 1903 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1904 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 1905 } 1906 1907 static void hsw_crtc_disable(struct intel_atomic_state *state, 1908 struct intel_crtc *crtc) 1909 { 1910 const struct intel_crtc_state *old_crtc_state = 1911 intel_atomic_get_old_crtc_state(state, crtc); 1912 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 1913 1914 /* 1915 * FIXME collapse everything to one hook. 1916 * Need care with mst->ddi interactions. 1917 */ 1918 if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) { 1919 intel_encoders_disable(state, crtc); 1920 intel_encoders_post_disable(state, crtc); 1921 } 1922 1923 intel_dmc_disable_pipe(i915, crtc->pipe); 1924 } 1925 1926 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) 1927 { 1928 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1929 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1930 1931 if (!crtc_state->gmch_pfit.control) 1932 return; 1933 1934 /* 1935 * The panel fitter should only be adjusted whilst the pipe is disabled, 1936 * according to register description and PRM. 1937 */ 1938 drm_WARN_ON(&dev_priv->drm, 1939 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE); 1940 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 1941 1942 intel_de_write(dev_priv, PFIT_PGM_RATIOS, 1943 crtc_state->gmch_pfit.pgm_ratios); 1944 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control); 1945 1946 /* Border color in case we don't scale up to the full screen. Black by 1947 * default, change to something else for debugging. */ 1948 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); 1949 } 1950 1951 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) 1952 { 1953 if (phy == PHY_NONE) 1954 return false; 1955 else if (IS_ALDERLAKE_S(dev_priv)) 1956 return phy <= PHY_E; 1957 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) 1958 return phy <= PHY_D; 1959 else if (IS_JSL_EHL(dev_priv)) 1960 return phy <= PHY_C; 1961 else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12)) 1962 return phy <= PHY_B; 1963 else 1964 /* 1965 * DG2 outputs labelled as "combo PHY" in the bspec use 1966 * SNPS PHYs with completely different programming, 1967 * hence we always return false here. 1968 */ 1969 return false; 1970 } 1971 1972 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) 1973 { 1974 if (IS_DG2(dev_priv)) 1975 /* DG2's "TC1" output uses a SNPS PHY */ 1976 return false; 1977 else if (IS_ALDERLAKE_P(dev_priv)) 1978 return phy >= PHY_F && phy <= PHY_I; 1979 else if (IS_TIGERLAKE(dev_priv)) 1980 return phy >= PHY_D && phy <= PHY_I; 1981 else if (IS_ICELAKE(dev_priv)) 1982 return phy >= PHY_C && phy <= PHY_F; 1983 else 1984 return false; 1985 } 1986 1987 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy) 1988 { 1989 if (phy == PHY_NONE) 1990 return false; 1991 else if (IS_DG2(dev_priv)) 1992 /* 1993 * All four "combo" ports and the TC1 port (PHY E) use 1994 * Synopsis PHYs. 1995 */ 1996 return phy <= PHY_E; 1997 1998 return false; 1999 } 2000 2001 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) 2002 { 2003 if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD) 2004 return PHY_D + port - PORT_D_XELPD; 2005 else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1) 2006 return PHY_F + port - PORT_TC1; 2007 else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1) 2008 return PHY_B + port - PORT_TC1; 2009 else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1) 2010 return PHY_C + port - PORT_TC1; 2011 else if (IS_JSL_EHL(i915) && port == PORT_D) 2012 return PHY_A; 2013 2014 return PHY_A + port - PORT_A; 2015 } 2016 2017 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) 2018 { 2019 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port))) 2020 return TC_PORT_NONE; 2021 2022 if (DISPLAY_VER(dev_priv) >= 12) 2023 return TC_PORT_1 + port - PORT_TC1; 2024 else 2025 return TC_PORT_1 + port - PORT_C; 2026 } 2027 2028 enum intel_display_power_domain 2029 intel_aux_power_domain(struct intel_digital_port *dig_port) 2030 { 2031 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 2032 2033 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 2034 return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch); 2035 2036 return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch); 2037 } 2038 2039 static void get_crtc_power_domains(struct intel_crtc_state *crtc_state, 2040 struct intel_power_domain_mask *mask) 2041 { 2042 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2043 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2044 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2045 struct drm_encoder *encoder; 2046 enum pipe pipe = crtc->pipe; 2047 2048 bitmap_zero(mask->bits, POWER_DOMAIN_NUM); 2049 2050 if (!crtc_state->hw.active) 2051 return; 2052 2053 set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits); 2054 set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits); 2055 if (crtc_state->pch_pfit.enabled || 2056 crtc_state->pch_pfit.force_thru) 2057 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits); 2058 2059 drm_for_each_encoder_mask(encoder, &dev_priv->drm, 2060 crtc_state->uapi.encoder_mask) { 2061 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2062 2063 set_bit(intel_encoder->power_domain, mask->bits); 2064 } 2065 2066 if (HAS_DDI(dev_priv) && crtc_state->has_audio) 2067 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits); 2068 2069 if (crtc_state->shared_dpll) 2070 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits); 2071 2072 if (crtc_state->dsc.compression_enable) 2073 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits); 2074 } 2075 2076 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, 2077 struct intel_power_domain_mask *old_domains) 2078 { 2079 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2080 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2081 enum intel_display_power_domain domain; 2082 struct intel_power_domain_mask domains, new_domains; 2083 2084 get_crtc_power_domains(crtc_state, &domains); 2085 2086 bitmap_andnot(new_domains.bits, 2087 domains.bits, 2088 crtc->enabled_power_domains.mask.bits, 2089 POWER_DOMAIN_NUM); 2090 bitmap_andnot(old_domains->bits, 2091 crtc->enabled_power_domains.mask.bits, 2092 domains.bits, 2093 POWER_DOMAIN_NUM); 2094 2095 for_each_power_domain(domain, &new_domains) 2096 intel_display_power_get_in_set(dev_priv, 2097 &crtc->enabled_power_domains, 2098 domain); 2099 } 2100 2101 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc, 2102 struct intel_power_domain_mask *domains) 2103 { 2104 intel_display_power_put_mask_in_set(to_i915(crtc->base.dev), 2105 &crtc->enabled_power_domains, 2106 domains); 2107 } 2108 2109 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 2110 { 2111 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2112 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2113 2114 if (intel_crtc_has_dp_encoder(crtc_state)) { 2115 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 2116 &crtc_state->dp_m_n); 2117 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 2118 &crtc_state->dp_m2_n2); 2119 } 2120 2121 intel_set_transcoder_timings(crtc_state); 2122 2123 i9xx_set_pipeconf(crtc_state); 2124 } 2125 2126 static void valleyview_crtc_enable(struct intel_atomic_state *state, 2127 struct intel_crtc *crtc) 2128 { 2129 const struct intel_crtc_state *new_crtc_state = 2130 intel_atomic_get_new_crtc_state(state, crtc); 2131 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2132 enum pipe pipe = crtc->pipe; 2133 2134 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 2135 return; 2136 2137 i9xx_configure_cpu_transcoder(new_crtc_state); 2138 2139 intel_set_pipe_src_size(new_crtc_state); 2140 2141 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 2142 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY); 2143 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0); 2144 } 2145 2146 crtc->active = true; 2147 2148 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2149 2150 intel_encoders_pre_pll_enable(state, crtc); 2151 2152 if (IS_CHERRYVIEW(dev_priv)) 2153 chv_enable_pll(new_crtc_state); 2154 else 2155 vlv_enable_pll(new_crtc_state); 2156 2157 intel_encoders_pre_enable(state, crtc); 2158 2159 i9xx_pfit_enable(new_crtc_state); 2160 2161 intel_color_load_luts(new_crtc_state); 2162 intel_color_commit_noarm(new_crtc_state); 2163 intel_color_commit_arm(new_crtc_state); 2164 /* update DSPCNTR to configure gamma for pipe bottom color */ 2165 intel_disable_primary_plane(new_crtc_state); 2166 2167 intel_initial_watermarks(state, crtc); 2168 intel_enable_transcoder(new_crtc_state); 2169 2170 intel_crtc_vblank_on(new_crtc_state); 2171 2172 intel_encoders_enable(state, crtc); 2173 } 2174 2175 static void i9xx_crtc_enable(struct intel_atomic_state *state, 2176 struct intel_crtc *crtc) 2177 { 2178 const struct intel_crtc_state *new_crtc_state = 2179 intel_atomic_get_new_crtc_state(state, crtc); 2180 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2181 enum pipe pipe = crtc->pipe; 2182 2183 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 2184 return; 2185 2186 i9xx_configure_cpu_transcoder(new_crtc_state); 2187 2188 intel_set_pipe_src_size(new_crtc_state); 2189 2190 crtc->active = true; 2191 2192 if (DISPLAY_VER(dev_priv) != 2) 2193 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2194 2195 intel_encoders_pre_enable(state, crtc); 2196 2197 i9xx_enable_pll(new_crtc_state); 2198 2199 i9xx_pfit_enable(new_crtc_state); 2200 2201 intel_color_load_luts(new_crtc_state); 2202 intel_color_commit_noarm(new_crtc_state); 2203 intel_color_commit_arm(new_crtc_state); 2204 /* update DSPCNTR to configure gamma for pipe bottom color */ 2205 intel_disable_primary_plane(new_crtc_state); 2206 2207 if (!intel_initial_watermarks(state, crtc)) 2208 intel_update_watermarks(dev_priv); 2209 intel_enable_transcoder(new_crtc_state); 2210 2211 intel_crtc_vblank_on(new_crtc_state); 2212 2213 intel_encoders_enable(state, crtc); 2214 2215 /* prevents spurious underruns */ 2216 if (DISPLAY_VER(dev_priv) == 2) 2217 intel_crtc_wait_for_next_vblank(crtc); 2218 } 2219 2220 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) 2221 { 2222 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 2223 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2224 2225 if (!old_crtc_state->gmch_pfit.control) 2226 return; 2227 2228 assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder); 2229 2230 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n", 2231 intel_de_read(dev_priv, PFIT_CONTROL)); 2232 intel_de_write(dev_priv, PFIT_CONTROL, 0); 2233 } 2234 2235 static void i9xx_crtc_disable(struct intel_atomic_state *state, 2236 struct intel_crtc *crtc) 2237 { 2238 struct intel_crtc_state *old_crtc_state = 2239 intel_atomic_get_old_crtc_state(state, crtc); 2240 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2241 enum pipe pipe = crtc->pipe; 2242 2243 /* 2244 * On gen2 planes are double buffered but the pipe isn't, so we must 2245 * wait for planes to fully turn off before disabling the pipe. 2246 */ 2247 if (DISPLAY_VER(dev_priv) == 2) 2248 intel_crtc_wait_for_next_vblank(crtc); 2249 2250 intel_encoders_disable(state, crtc); 2251 2252 intel_crtc_vblank_off(old_crtc_state); 2253 2254 intel_disable_transcoder(old_crtc_state); 2255 2256 i9xx_pfit_disable(old_crtc_state); 2257 2258 intel_encoders_post_disable(state, crtc); 2259 2260 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) { 2261 if (IS_CHERRYVIEW(dev_priv)) 2262 chv_disable_pll(dev_priv, pipe); 2263 else if (IS_VALLEYVIEW(dev_priv)) 2264 vlv_disable_pll(dev_priv, pipe); 2265 else 2266 i9xx_disable_pll(old_crtc_state); 2267 } 2268 2269 intel_encoders_post_pll_disable(state, crtc); 2270 2271 if (DISPLAY_VER(dev_priv) != 2) 2272 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 2273 2274 if (!dev_priv->display.funcs.wm->initial_watermarks) 2275 intel_update_watermarks(dev_priv); 2276 2277 /* clock the pipe down to 640x480@60 to potentially save power */ 2278 if (IS_I830(dev_priv)) 2279 i830_enable_pipe(dev_priv, pipe); 2280 } 2281 2282 2283 /* 2284 * turn all crtc's off, but do not adjust state 2285 * This has to be paired with a call to intel_modeset_setup_hw_state. 2286 */ 2287 int intel_display_suspend(struct drm_device *dev) 2288 { 2289 struct drm_i915_private *dev_priv = to_i915(dev); 2290 struct drm_atomic_state *state; 2291 int ret; 2292 2293 if (!HAS_DISPLAY(dev_priv)) 2294 return 0; 2295 2296 state = drm_atomic_helper_suspend(dev); 2297 ret = PTR_ERR_OR_ZERO(state); 2298 if (ret) 2299 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", 2300 ret); 2301 else 2302 dev_priv->display.restore.modeset_state = state; 2303 return ret; 2304 } 2305 2306 void intel_encoder_destroy(struct drm_encoder *encoder) 2307 { 2308 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2309 2310 drm_encoder_cleanup(encoder); 2311 kfree(intel_encoder); 2312 } 2313 2314 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) 2315 { 2316 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2317 2318 /* GDG double wide on either pipe, otherwise pipe A only */ 2319 return DISPLAY_VER(dev_priv) < 4 && 2320 (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); 2321 } 2322 2323 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) 2324 { 2325 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock; 2326 struct drm_rect src; 2327 2328 /* 2329 * We only use IF-ID interlacing. If we ever use 2330 * PF-ID we'll need to adjust the pixel_rate here. 2331 */ 2332 2333 if (!crtc_state->pch_pfit.enabled) 2334 return pixel_rate; 2335 2336 drm_rect_init(&src, 0, 0, 2337 drm_rect_width(&crtc_state->pipe_src) << 16, 2338 drm_rect_height(&crtc_state->pipe_src) << 16); 2339 2340 return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst, 2341 pixel_rate); 2342 } 2343 2344 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode, 2345 const struct drm_display_mode *timings) 2346 { 2347 mode->hdisplay = timings->crtc_hdisplay; 2348 mode->htotal = timings->crtc_htotal; 2349 mode->hsync_start = timings->crtc_hsync_start; 2350 mode->hsync_end = timings->crtc_hsync_end; 2351 2352 mode->vdisplay = timings->crtc_vdisplay; 2353 mode->vtotal = timings->crtc_vtotal; 2354 mode->vsync_start = timings->crtc_vsync_start; 2355 mode->vsync_end = timings->crtc_vsync_end; 2356 2357 mode->flags = timings->flags; 2358 mode->type = DRM_MODE_TYPE_DRIVER; 2359 2360 mode->clock = timings->crtc_clock; 2361 2362 drm_mode_set_name(mode); 2363 } 2364 2365 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) 2366 { 2367 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2368 2369 if (HAS_GMCH(dev_priv)) 2370 /* FIXME calculate proper pipe pixel rate for GMCH pfit */ 2371 crtc_state->pixel_rate = 2372 crtc_state->hw.pipe_mode.crtc_clock; 2373 else 2374 crtc_state->pixel_rate = 2375 ilk_pipe_pixel_rate(crtc_state); 2376 } 2377 2378 static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state *crtc_state, 2379 struct drm_display_mode *mode) 2380 { 2381 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2382 2383 if (num_pipes < 2) 2384 return; 2385 2386 mode->crtc_clock /= num_pipes; 2387 mode->crtc_hdisplay /= num_pipes; 2388 mode->crtc_hblank_start /= num_pipes; 2389 mode->crtc_hblank_end /= num_pipes; 2390 mode->crtc_hsync_start /= num_pipes; 2391 mode->crtc_hsync_end /= num_pipes; 2392 mode->crtc_htotal /= num_pipes; 2393 } 2394 2395 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state, 2396 struct drm_display_mode *mode) 2397 { 2398 int overlap = crtc_state->splitter.pixel_overlap; 2399 int n = crtc_state->splitter.link_count; 2400 2401 if (!crtc_state->splitter.enable) 2402 return; 2403 2404 /* 2405 * eDP MSO uses segment timings from EDID for transcoder 2406 * timings, but full mode for everything else. 2407 * 2408 * h_full = (h_segment - pixel_overlap) * link_count 2409 */ 2410 mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n; 2411 mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n; 2412 mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n; 2413 mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n; 2414 mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n; 2415 mode->crtc_htotal = (mode->crtc_htotal - overlap) * n; 2416 mode->crtc_clock *= n; 2417 } 2418 2419 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state) 2420 { 2421 struct drm_display_mode *mode = &crtc_state->hw.mode; 2422 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2423 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2424 2425 /* 2426 * Start with the adjusted_mode crtc timings, which 2427 * have been filled with the transcoder timings. 2428 */ 2429 drm_mode_copy(pipe_mode, adjusted_mode); 2430 2431 /* Expand MSO per-segment transcoder timings to full */ 2432 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2433 2434 /* 2435 * We want the full numbers in adjusted_mode normal timings, 2436 * adjusted_mode crtc timings are left with the raw transcoder 2437 * timings. 2438 */ 2439 intel_mode_from_crtc_timings(adjusted_mode, pipe_mode); 2440 2441 /* Populate the "user" mode with full numbers */ 2442 drm_mode_copy(mode, pipe_mode); 2443 intel_mode_from_crtc_timings(mode, mode); 2444 mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) * 2445 (intel_bigjoiner_num_pipes(crtc_state) ?: 1); 2446 mode->vdisplay = drm_rect_height(&crtc_state->pipe_src); 2447 2448 /* Derive per-pipe timings in case bigjoiner is used */ 2449 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2450 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2451 2452 intel_crtc_compute_pixel_rate(crtc_state); 2453 } 2454 2455 void intel_encoder_get_config(struct intel_encoder *encoder, 2456 struct intel_crtc_state *crtc_state) 2457 { 2458 encoder->get_config(encoder, crtc_state); 2459 2460 intel_crtc_readout_derived_state(crtc_state); 2461 } 2462 2463 static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state *crtc_state) 2464 { 2465 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2466 int width, height; 2467 2468 if (num_pipes < 2) 2469 return; 2470 2471 width = drm_rect_width(&crtc_state->pipe_src); 2472 height = drm_rect_height(&crtc_state->pipe_src); 2473 2474 drm_rect_init(&crtc_state->pipe_src, 0, 0, 2475 width / num_pipes, height); 2476 } 2477 2478 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state) 2479 { 2480 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2481 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2482 2483 intel_bigjoiner_compute_pipe_src(crtc_state); 2484 2485 /* 2486 * Pipe horizontal size must be even in: 2487 * - DVO ganged mode 2488 * - LVDS dual channel mode 2489 * - Double wide pipe 2490 */ 2491 if (drm_rect_width(&crtc_state->pipe_src) & 1) { 2492 if (crtc_state->double_wide) { 2493 drm_dbg_kms(&i915->drm, 2494 "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n", 2495 crtc->base.base.id, crtc->base.name); 2496 return -EINVAL; 2497 } 2498 2499 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 2500 intel_is_dual_link_lvds(i915)) { 2501 drm_dbg_kms(&i915->drm, 2502 "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n", 2503 crtc->base.base.id, crtc->base.name); 2504 return -EINVAL; 2505 } 2506 } 2507 2508 return 0; 2509 } 2510 2511 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state) 2512 { 2513 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2514 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2515 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2516 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2517 int clock_limit = i915->max_dotclk_freq; 2518 2519 /* 2520 * Start with the adjusted_mode crtc timings, which 2521 * have been filled with the transcoder timings. 2522 */ 2523 drm_mode_copy(pipe_mode, adjusted_mode); 2524 2525 /* Expand MSO per-segment transcoder timings to full */ 2526 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2527 2528 /* Derive per-pipe timings in case bigjoiner is used */ 2529 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2530 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2531 2532 if (DISPLAY_VER(i915) < 4) { 2533 clock_limit = i915->display.cdclk.max_cdclk_freq * 9 / 10; 2534 2535 /* 2536 * Enable double wide mode when the dot clock 2537 * is > 90% of the (display) core speed. 2538 */ 2539 if (intel_crtc_supports_double_wide(crtc) && 2540 pipe_mode->crtc_clock > clock_limit) { 2541 clock_limit = i915->max_dotclk_freq; 2542 crtc_state->double_wide = true; 2543 } 2544 } 2545 2546 if (pipe_mode->crtc_clock > clock_limit) { 2547 drm_dbg_kms(&i915->drm, 2548 "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", 2549 crtc->base.base.id, crtc->base.name, 2550 pipe_mode->crtc_clock, clock_limit, 2551 str_yes_no(crtc_state->double_wide)); 2552 return -EINVAL; 2553 } 2554 2555 return 0; 2556 } 2557 2558 static int intel_crtc_compute_config(struct intel_atomic_state *state, 2559 struct intel_crtc *crtc) 2560 { 2561 struct intel_crtc_state *crtc_state = 2562 intel_atomic_get_new_crtc_state(state, crtc); 2563 int ret; 2564 2565 ret = intel_dpll_crtc_compute_clock(state, crtc); 2566 if (ret) 2567 return ret; 2568 2569 ret = intel_crtc_compute_pipe_src(crtc_state); 2570 if (ret) 2571 return ret; 2572 2573 ret = intel_crtc_compute_pipe_mode(crtc_state); 2574 if (ret) 2575 return ret; 2576 2577 intel_crtc_compute_pixel_rate(crtc_state); 2578 2579 if (crtc_state->has_pch_encoder) 2580 return ilk_fdi_compute_config(crtc, crtc_state); 2581 2582 return 0; 2583 } 2584 2585 static void 2586 intel_reduce_m_n_ratio(u32 *num, u32 *den) 2587 { 2588 while (*num > DATA_LINK_M_N_MASK || 2589 *den > DATA_LINK_M_N_MASK) { 2590 *num >>= 1; 2591 *den >>= 1; 2592 } 2593 } 2594 2595 static void compute_m_n(u32 *ret_m, u32 *ret_n, 2596 u32 m, u32 n, u32 constant_n) 2597 { 2598 if (constant_n) 2599 *ret_n = constant_n; 2600 else 2601 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); 2602 2603 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n); 2604 intel_reduce_m_n_ratio(ret_m, ret_n); 2605 } 2606 2607 void 2608 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes, 2609 int pixel_clock, int link_clock, 2610 struct intel_link_m_n *m_n, 2611 bool fec_enable) 2612 { 2613 u32 data_clock = bits_per_pixel * pixel_clock; 2614 2615 if (fec_enable) 2616 data_clock = intel_dp_mode_to_fec_clock(data_clock); 2617 2618 /* 2619 * Windows/BIOS uses fixed M/N values always. Follow suit. 2620 * 2621 * Also several DP dongles in particular seem to be fussy 2622 * about too large link M/N values. Presumably the 20bit 2623 * value used by Windows/BIOS is acceptable to everyone. 2624 */ 2625 m_n->tu = 64; 2626 compute_m_n(&m_n->data_m, &m_n->data_n, 2627 data_clock, link_clock * nlanes * 8, 2628 0x8000000); 2629 2630 compute_m_n(&m_n->link_m, &m_n->link_n, 2631 pixel_clock, link_clock, 2632 0x80000); 2633 } 2634 2635 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv) 2636 { 2637 /* 2638 * There may be no VBT; and if the BIOS enabled SSC we can 2639 * just keep using it to avoid unnecessary flicker. Whereas if the 2640 * BIOS isn't using it, don't assume it will work even if the VBT 2641 * indicates as much. 2642 */ 2643 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { 2644 bool bios_lvds_use_ssc = intel_de_read(dev_priv, 2645 PCH_DREF_CONTROL) & 2646 DREF_SSC1_ENABLE; 2647 2648 if (dev_priv->display.vbt.lvds_use_ssc != bios_lvds_use_ssc) { 2649 drm_dbg_kms(&dev_priv->drm, 2650 "SSC %s by BIOS, overriding VBT which says %s\n", 2651 str_enabled_disabled(bios_lvds_use_ssc), 2652 str_enabled_disabled(dev_priv->display.vbt.lvds_use_ssc)); 2653 dev_priv->display.vbt.lvds_use_ssc = bios_lvds_use_ssc; 2654 } 2655 } 2656 } 2657 2658 void intel_zero_m_n(struct intel_link_m_n *m_n) 2659 { 2660 /* corresponds to 0 register value */ 2661 memset(m_n, 0, sizeof(*m_n)); 2662 m_n->tu = 1; 2663 } 2664 2665 void intel_set_m_n(struct drm_i915_private *i915, 2666 const struct intel_link_m_n *m_n, 2667 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 2668 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 2669 { 2670 intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); 2671 intel_de_write(i915, data_n_reg, m_n->data_n); 2672 intel_de_write(i915, link_m_reg, m_n->link_m); 2673 /* 2674 * On BDW+ writing LINK_N arms the double buffered update 2675 * of all the M/N registers, so it must be written last. 2676 */ 2677 intel_de_write(i915, link_n_reg, m_n->link_n); 2678 } 2679 2680 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, 2681 enum transcoder transcoder) 2682 { 2683 if (IS_HASWELL(dev_priv)) 2684 return transcoder == TRANSCODER_EDP; 2685 2686 return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv); 2687 } 2688 2689 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, 2690 enum transcoder transcoder, 2691 const struct intel_link_m_n *m_n) 2692 { 2693 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2694 enum pipe pipe = crtc->pipe; 2695 2696 if (DISPLAY_VER(dev_priv) >= 5) 2697 intel_set_m_n(dev_priv, m_n, 2698 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 2699 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 2700 else 2701 intel_set_m_n(dev_priv, m_n, 2702 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 2703 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 2704 } 2705 2706 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, 2707 enum transcoder transcoder, 2708 const struct intel_link_m_n *m_n) 2709 { 2710 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2711 2712 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 2713 return; 2714 2715 intel_set_m_n(dev_priv, m_n, 2716 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 2717 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 2718 } 2719 2720 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) 2721 { 2722 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2723 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2724 enum pipe pipe = crtc->pipe; 2725 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2726 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2727 u32 crtc_vtotal, crtc_vblank_end; 2728 int vsyncshift = 0; 2729 2730 /* We need to be careful not to changed the adjusted mode, for otherwise 2731 * the hw state checker will get angry at the mismatch. */ 2732 crtc_vtotal = adjusted_mode->crtc_vtotal; 2733 crtc_vblank_end = adjusted_mode->crtc_vblank_end; 2734 2735 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 2736 /* the chip adds 2 halflines automatically */ 2737 crtc_vtotal -= 1; 2738 crtc_vblank_end -= 1; 2739 2740 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 2741 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; 2742 else 2743 vsyncshift = adjusted_mode->crtc_hsync_start - 2744 adjusted_mode->crtc_htotal / 2; 2745 if (vsyncshift < 0) 2746 vsyncshift += adjusted_mode->crtc_htotal; 2747 } 2748 2749 if (DISPLAY_VER(dev_priv) > 3) 2750 intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder), 2751 vsyncshift); 2752 2753 intel_de_write(dev_priv, HTOTAL(cpu_transcoder), 2754 (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16)); 2755 intel_de_write(dev_priv, HBLANK(cpu_transcoder), 2756 (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16)); 2757 intel_de_write(dev_priv, HSYNC(cpu_transcoder), 2758 (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16)); 2759 2760 intel_de_write(dev_priv, VTOTAL(cpu_transcoder), 2761 (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16)); 2762 intel_de_write(dev_priv, VBLANK(cpu_transcoder), 2763 (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16)); 2764 intel_de_write(dev_priv, VSYNC(cpu_transcoder), 2765 (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16)); 2766 2767 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be 2768 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is 2769 * documented on the DDI_FUNC_CTL register description, EDP Input Select 2770 * bits. */ 2771 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && 2772 (pipe == PIPE_B || pipe == PIPE_C)) 2773 intel_de_write(dev_priv, VTOTAL(pipe), 2774 intel_de_read(dev_priv, VTOTAL(cpu_transcoder))); 2775 2776 } 2777 2778 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) 2779 { 2780 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2781 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2782 int width = drm_rect_width(&crtc_state->pipe_src); 2783 int height = drm_rect_height(&crtc_state->pipe_src); 2784 enum pipe pipe = crtc->pipe; 2785 2786 /* pipesrc controls the size that is scaled from, which should 2787 * always be the user's requested size. 2788 */ 2789 intel_de_write(dev_priv, PIPESRC(pipe), 2790 PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1)); 2791 } 2792 2793 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) 2794 { 2795 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2796 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2797 2798 if (DISPLAY_VER(dev_priv) == 2) 2799 return false; 2800 2801 if (DISPLAY_VER(dev_priv) >= 9 || 2802 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2803 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW; 2804 else 2805 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK; 2806 } 2807 2808 static void intel_get_transcoder_timings(struct intel_crtc *crtc, 2809 struct intel_crtc_state *pipe_config) 2810 { 2811 struct drm_device *dev = crtc->base.dev; 2812 struct drm_i915_private *dev_priv = to_i915(dev); 2813 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 2814 u32 tmp; 2815 2816 tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder)); 2817 pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; 2818 pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; 2819 2820 if (!transcoder_is_dsi(cpu_transcoder)) { 2821 tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder)); 2822 pipe_config->hw.adjusted_mode.crtc_hblank_start = 2823 (tmp & 0xffff) + 1; 2824 pipe_config->hw.adjusted_mode.crtc_hblank_end = 2825 ((tmp >> 16) & 0xffff) + 1; 2826 } 2827 tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder)); 2828 pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; 2829 pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; 2830 2831 tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder)); 2832 pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; 2833 pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; 2834 2835 if (!transcoder_is_dsi(cpu_transcoder)) { 2836 tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder)); 2837 pipe_config->hw.adjusted_mode.crtc_vblank_start = 2838 (tmp & 0xffff) + 1; 2839 pipe_config->hw.adjusted_mode.crtc_vblank_end = 2840 ((tmp >> 16) & 0xffff) + 1; 2841 } 2842 tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder)); 2843 pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; 2844 pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; 2845 2846 if (intel_pipe_is_interlaced(pipe_config)) { 2847 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; 2848 pipe_config->hw.adjusted_mode.crtc_vtotal += 1; 2849 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1; 2850 } 2851 } 2852 2853 static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state) 2854 { 2855 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2856 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2857 enum pipe master_pipe, pipe = crtc->pipe; 2858 int width; 2859 2860 if (num_pipes < 2) 2861 return; 2862 2863 master_pipe = bigjoiner_master_pipe(crtc_state); 2864 width = drm_rect_width(&crtc_state->pipe_src); 2865 2866 drm_rect_translate_to(&crtc_state->pipe_src, 2867 (pipe - master_pipe) * width, 0); 2868 } 2869 2870 static void intel_get_pipe_src_size(struct intel_crtc *crtc, 2871 struct intel_crtc_state *pipe_config) 2872 { 2873 struct drm_device *dev = crtc->base.dev; 2874 struct drm_i915_private *dev_priv = to_i915(dev); 2875 u32 tmp; 2876 2877 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe)); 2878 2879 drm_rect_init(&pipe_config->pipe_src, 0, 0, 2880 REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1, 2881 REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1); 2882 2883 intel_bigjoiner_adjust_pipe_src(pipe_config); 2884 } 2885 2886 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) 2887 { 2888 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2889 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2890 u32 pipeconf = 0; 2891 2892 /* 2893 * - We keep both pipes enabled on 830 2894 * - During modeset the pipe is still disabled and must remain so 2895 * - During fastset the pipe is already enabled and must remain so 2896 */ 2897 if (IS_I830(dev_priv) || !intel_crtc_needs_modeset(crtc_state)) 2898 pipeconf |= PIPECONF_ENABLE; 2899 2900 if (crtc_state->double_wide) 2901 pipeconf |= PIPECONF_DOUBLE_WIDE; 2902 2903 /* only g4x and later have fancy bpc/dither controls */ 2904 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 2905 IS_CHERRYVIEW(dev_priv)) { 2906 /* Bspec claims that we can't use dithering for 30bpp pipes. */ 2907 if (crtc_state->dither && crtc_state->pipe_bpp != 30) 2908 pipeconf |= PIPECONF_DITHER_EN | 2909 PIPECONF_DITHER_TYPE_SP; 2910 2911 switch (crtc_state->pipe_bpp) { 2912 default: 2913 /* Case prevented by intel_choose_pipe_bpp_dither. */ 2914 MISSING_CASE(crtc_state->pipe_bpp); 2915 fallthrough; 2916 case 18: 2917 pipeconf |= PIPECONF_BPC_6; 2918 break; 2919 case 24: 2920 pipeconf |= PIPECONF_BPC_8; 2921 break; 2922 case 30: 2923 pipeconf |= PIPECONF_BPC_10; 2924 break; 2925 } 2926 } 2927 2928 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 2929 if (DISPLAY_VER(dev_priv) < 4 || 2930 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 2931 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; 2932 else 2933 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; 2934 } else { 2935 pipeconf |= PIPECONF_INTERLACE_PROGRESSIVE; 2936 } 2937 2938 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 2939 crtc_state->limited_color_range) 2940 pipeconf |= PIPECONF_COLOR_RANGE_SELECT; 2941 2942 pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); 2943 2944 pipeconf |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 2945 2946 intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf); 2947 intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe)); 2948 } 2949 2950 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv) 2951 { 2952 if (IS_I830(dev_priv)) 2953 return false; 2954 2955 return DISPLAY_VER(dev_priv) >= 4 || 2956 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); 2957 } 2958 2959 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state) 2960 { 2961 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2962 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2963 u32 tmp; 2964 2965 if (!i9xx_has_pfit(dev_priv)) 2966 return; 2967 2968 tmp = intel_de_read(dev_priv, PFIT_CONTROL); 2969 if (!(tmp & PFIT_ENABLE)) 2970 return; 2971 2972 /* Check whether the pfit is attached to our pipe. */ 2973 if (DISPLAY_VER(dev_priv) < 4) { 2974 if (crtc->pipe != PIPE_B) 2975 return; 2976 } else { 2977 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) 2978 return; 2979 } 2980 2981 crtc_state->gmch_pfit.control = tmp; 2982 crtc_state->gmch_pfit.pgm_ratios = 2983 intel_de_read(dev_priv, PFIT_PGM_RATIOS); 2984 } 2985 2986 static void vlv_crtc_clock_get(struct intel_crtc *crtc, 2987 struct intel_crtc_state *pipe_config) 2988 { 2989 struct drm_device *dev = crtc->base.dev; 2990 struct drm_i915_private *dev_priv = to_i915(dev); 2991 enum pipe pipe = crtc->pipe; 2992 struct dpll clock; 2993 u32 mdiv; 2994 int refclk = 100000; 2995 2996 /* In case of DSI, DPLL will not be used */ 2997 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 2998 return; 2999 3000 vlv_dpio_get(dev_priv); 3001 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); 3002 vlv_dpio_put(dev_priv); 3003 3004 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; 3005 clock.m2 = mdiv & DPIO_M2DIV_MASK; 3006 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; 3007 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; 3008 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; 3009 3010 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); 3011 } 3012 3013 static void chv_crtc_clock_get(struct intel_crtc *crtc, 3014 struct intel_crtc_state *pipe_config) 3015 { 3016 struct drm_device *dev = crtc->base.dev; 3017 struct drm_i915_private *dev_priv = to_i915(dev); 3018 enum pipe pipe = crtc->pipe; 3019 enum dpio_channel port = vlv_pipe_to_channel(pipe); 3020 struct dpll clock; 3021 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; 3022 int refclk = 100000; 3023 3024 /* In case of DSI, DPLL will not be used */ 3025 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 3026 return; 3027 3028 vlv_dpio_get(dev_priv); 3029 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); 3030 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); 3031 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); 3032 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); 3033 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); 3034 vlv_dpio_put(dev_priv); 3035 3036 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; 3037 clock.m2 = (pll_dw0 & 0xff) << 22; 3038 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) 3039 clock.m2 |= pll_dw2 & 0x3fffff; 3040 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; 3041 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; 3042 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; 3043 3044 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); 3045 } 3046 3047 static enum intel_output_format 3048 bdw_get_pipemisc_output_format(struct intel_crtc *crtc) 3049 { 3050 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3051 u32 tmp; 3052 3053 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); 3054 3055 if (tmp & PIPEMISC_YUV420_ENABLE) { 3056 /* We support 4:2:0 in full blend mode only */ 3057 drm_WARN_ON(&dev_priv->drm, 3058 (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0); 3059 3060 return INTEL_OUTPUT_FORMAT_YCBCR420; 3061 } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) { 3062 return INTEL_OUTPUT_FORMAT_YCBCR444; 3063 } else { 3064 return INTEL_OUTPUT_FORMAT_RGB; 3065 } 3066 } 3067 3068 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state) 3069 { 3070 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3071 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 3072 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3073 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 3074 u32 tmp; 3075 3076 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); 3077 3078 if (tmp & DISP_PIPE_GAMMA_ENABLE) 3079 crtc_state->gamma_enable = true; 3080 3081 if (!HAS_GMCH(dev_priv) && 3082 tmp & DISP_PIPE_CSC_ENABLE) 3083 crtc_state->csc_enable = true; 3084 } 3085 3086 static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 3087 struct intel_crtc_state *pipe_config) 3088 { 3089 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3090 enum intel_display_power_domain power_domain; 3091 intel_wakeref_t wakeref; 3092 u32 tmp; 3093 bool ret; 3094 3095 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3096 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3097 if (!wakeref) 3098 return false; 3099 3100 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3101 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3102 pipe_config->shared_dpll = NULL; 3103 3104 ret = false; 3105 3106 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); 3107 if (!(tmp & PIPECONF_ENABLE)) 3108 goto out; 3109 3110 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 3111 IS_CHERRYVIEW(dev_priv)) { 3112 switch (tmp & PIPECONF_BPC_MASK) { 3113 case PIPECONF_BPC_6: 3114 pipe_config->pipe_bpp = 18; 3115 break; 3116 case PIPECONF_BPC_8: 3117 pipe_config->pipe_bpp = 24; 3118 break; 3119 case PIPECONF_BPC_10: 3120 pipe_config->pipe_bpp = 30; 3121 break; 3122 default: 3123 MISSING_CASE(tmp); 3124 break; 3125 } 3126 } 3127 3128 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 3129 (tmp & PIPECONF_COLOR_RANGE_SELECT)) 3130 pipe_config->limited_color_range = true; 3131 3132 pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_I9XX, tmp); 3133 3134 pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1; 3135 3136 if (IS_CHERRYVIEW(dev_priv)) 3137 pipe_config->cgm_mode = intel_de_read(dev_priv, 3138 CGM_PIPE_MODE(crtc->pipe)); 3139 3140 i9xx_get_pipe_color_config(pipe_config); 3141 intel_color_get_config(pipe_config); 3142 3143 if (DISPLAY_VER(dev_priv) < 4) 3144 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; 3145 3146 intel_get_transcoder_timings(crtc, pipe_config); 3147 intel_get_pipe_src_size(crtc, pipe_config); 3148 3149 i9xx_get_pfit_config(pipe_config); 3150 3151 if (DISPLAY_VER(dev_priv) >= 4) { 3152 /* No way to read it out on pipes B and C */ 3153 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) 3154 tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe]; 3155 else 3156 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe)); 3157 pipe_config->pixel_multiplier = 3158 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) 3159 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; 3160 pipe_config->dpll_hw_state.dpll_md = tmp; 3161 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 3162 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 3163 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe)); 3164 pipe_config->pixel_multiplier = 3165 ((tmp & SDVO_MULTIPLIER_MASK) 3166 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; 3167 } else { 3168 /* Note that on i915G/GM the pixel multiplier is in the sdvo 3169 * port and will be fixed up in the encoder->get_config 3170 * function. */ 3171 pipe_config->pixel_multiplier = 1; 3172 } 3173 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv, 3174 DPLL(crtc->pipe)); 3175 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 3176 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv, 3177 FP0(crtc->pipe)); 3178 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv, 3179 FP1(crtc->pipe)); 3180 } else { 3181 /* Mask out read-only status bits. */ 3182 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | 3183 DPLL_PORTC_READY_MASK | 3184 DPLL_PORTB_READY_MASK); 3185 } 3186 3187 if (IS_CHERRYVIEW(dev_priv)) 3188 chv_crtc_clock_get(crtc, pipe_config); 3189 else if (IS_VALLEYVIEW(dev_priv)) 3190 vlv_crtc_clock_get(crtc, pipe_config); 3191 else 3192 i9xx_crtc_clock_get(crtc, pipe_config); 3193 3194 /* 3195 * Normally the dotclock is filled in by the encoder .get_config() 3196 * but in case the pipe is enabled w/o any ports we need a sane 3197 * default. 3198 */ 3199 pipe_config->hw.adjusted_mode.crtc_clock = 3200 pipe_config->port_clock / pipe_config->pixel_multiplier; 3201 3202 ret = true; 3203 3204 out: 3205 intel_display_power_put(dev_priv, power_domain, wakeref); 3206 3207 return ret; 3208 } 3209 3210 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) 3211 { 3212 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3213 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3214 enum pipe pipe = crtc->pipe; 3215 u32 val = 0; 3216 3217 /* 3218 * - During modeset the pipe is still disabled and must remain so 3219 * - During fastset the pipe is already enabled and must remain so 3220 */ 3221 if (!intel_crtc_needs_modeset(crtc_state)) 3222 val |= PIPECONF_ENABLE; 3223 3224 switch (crtc_state->pipe_bpp) { 3225 default: 3226 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3227 MISSING_CASE(crtc_state->pipe_bpp); 3228 fallthrough; 3229 case 18: 3230 val |= PIPECONF_BPC_6; 3231 break; 3232 case 24: 3233 val |= PIPECONF_BPC_8; 3234 break; 3235 case 30: 3236 val |= PIPECONF_BPC_10; 3237 break; 3238 case 36: 3239 val |= PIPECONF_BPC_12; 3240 break; 3241 } 3242 3243 if (crtc_state->dither) 3244 val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP; 3245 3246 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3247 val |= PIPECONF_INTERLACE_IF_ID_ILK; 3248 else 3249 val |= PIPECONF_INTERLACE_PF_PD_ILK; 3250 3251 /* 3252 * This would end up with an odd purple hue over 3253 * the entire display. Make sure we don't do it. 3254 */ 3255 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 3256 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 3257 3258 if (crtc_state->limited_color_range && 3259 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3260 val |= PIPECONF_COLOR_RANGE_SELECT; 3261 3262 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3263 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709; 3264 3265 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); 3266 3267 val |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3268 val |= PIPECONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay); 3269 3270 intel_de_write(dev_priv, PIPECONF(pipe), val); 3271 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 3272 } 3273 3274 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) 3275 { 3276 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3277 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3278 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3279 u32 val = 0; 3280 3281 /* 3282 * - During modeset the pipe is still disabled and must remain so 3283 * - During fastset the pipe is already enabled and must remain so 3284 */ 3285 if (!intel_crtc_needs_modeset(crtc_state)) 3286 val |= PIPECONF_ENABLE; 3287 3288 if (IS_HASWELL(dev_priv) && crtc_state->dither) 3289 val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP; 3290 3291 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3292 val |= PIPECONF_INTERLACE_IF_ID_ILK; 3293 else 3294 val |= PIPECONF_INTERLACE_PF_PD_ILK; 3295 3296 if (IS_HASWELL(dev_priv) && 3297 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3298 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW; 3299 3300 intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val); 3301 intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder)); 3302 } 3303 3304 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) 3305 { 3306 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3307 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3308 u32 val = 0; 3309 3310 switch (crtc_state->pipe_bpp) { 3311 case 18: 3312 val |= PIPEMISC_BPC_6; 3313 break; 3314 case 24: 3315 val |= PIPEMISC_BPC_8; 3316 break; 3317 case 30: 3318 val |= PIPEMISC_BPC_10; 3319 break; 3320 case 36: 3321 /* Port output 12BPC defined for ADLP+ */ 3322 if (DISPLAY_VER(dev_priv) > 12) 3323 val |= PIPEMISC_BPC_12_ADLP; 3324 break; 3325 default: 3326 MISSING_CASE(crtc_state->pipe_bpp); 3327 break; 3328 } 3329 3330 if (crtc_state->dither) 3331 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; 3332 3333 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 3334 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 3335 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV; 3336 3337 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 3338 val |= PIPEMISC_YUV420_ENABLE | 3339 PIPEMISC_YUV420_MODE_FULL_BLEND; 3340 3341 if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state)) 3342 val |= PIPEMISC_HDR_MODE_PRECISION; 3343 3344 if (DISPLAY_VER(dev_priv) >= 12) 3345 val |= PIPEMISC_PIXEL_ROUNDING_TRUNC; 3346 3347 intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val); 3348 } 3349 3350 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) 3351 { 3352 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3353 u32 tmp; 3354 3355 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); 3356 3357 switch (tmp & PIPEMISC_BPC_MASK) { 3358 case PIPEMISC_BPC_6: 3359 return 18; 3360 case PIPEMISC_BPC_8: 3361 return 24; 3362 case PIPEMISC_BPC_10: 3363 return 30; 3364 /* 3365 * PORT OUTPUT 12 BPC defined for ADLP+. 3366 * 3367 * TODO: 3368 * For previous platforms with DSI interface, bits 5:7 3369 * are used for storing pipe_bpp irrespective of dithering. 3370 * Since the value of 12 BPC is not defined for these bits 3371 * on older platforms, need to find a workaround for 12 BPC 3372 * MIPI DSI HW readout. 3373 */ 3374 case PIPEMISC_BPC_12_ADLP: 3375 if (DISPLAY_VER(dev_priv) > 12) 3376 return 36; 3377 fallthrough; 3378 default: 3379 MISSING_CASE(tmp); 3380 return 0; 3381 } 3382 } 3383 3384 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) 3385 { 3386 /* 3387 * Account for spread spectrum to avoid 3388 * oversubscribing the link. Max center spread 3389 * is 2.5%; use 5% for safety's sake. 3390 */ 3391 u32 bps = target_clock * bpp * 21 / 20; 3392 return DIV_ROUND_UP(bps, link_bw * 8); 3393 } 3394 3395 void intel_get_m_n(struct drm_i915_private *i915, 3396 struct intel_link_m_n *m_n, 3397 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 3398 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 3399 { 3400 m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK; 3401 m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK; 3402 m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK; 3403 m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK; 3404 m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1; 3405 } 3406 3407 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, 3408 enum transcoder transcoder, 3409 struct intel_link_m_n *m_n) 3410 { 3411 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3412 enum pipe pipe = crtc->pipe; 3413 3414 if (DISPLAY_VER(dev_priv) >= 5) 3415 intel_get_m_n(dev_priv, m_n, 3416 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 3417 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 3418 else 3419 intel_get_m_n(dev_priv, m_n, 3420 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 3421 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 3422 } 3423 3424 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, 3425 enum transcoder transcoder, 3426 struct intel_link_m_n *m_n) 3427 { 3428 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3429 3430 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 3431 return; 3432 3433 intel_get_m_n(dev_priv, m_n, 3434 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 3435 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 3436 } 3437 3438 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state, 3439 u32 pos, u32 size) 3440 { 3441 drm_rect_init(&crtc_state->pch_pfit.dst, 3442 pos >> 16, pos & 0xffff, 3443 size >> 16, size & 0xffff); 3444 } 3445 3446 static void skl_get_pfit_config(struct intel_crtc_state *crtc_state) 3447 { 3448 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3449 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3450 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; 3451 int id = -1; 3452 int i; 3453 3454 /* find scaler attached to this pipe */ 3455 for (i = 0; i < crtc->num_scalers; i++) { 3456 u32 ctl, pos, size; 3457 3458 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i)); 3459 if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN) 3460 continue; 3461 3462 id = i; 3463 crtc_state->pch_pfit.enabled = true; 3464 3465 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i)); 3466 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i)); 3467 3468 ilk_get_pfit_pos_size(crtc_state, pos, size); 3469 3470 scaler_state->scalers[i].in_use = true; 3471 break; 3472 } 3473 3474 scaler_state->scaler_id = id; 3475 if (id >= 0) 3476 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); 3477 else 3478 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); 3479 } 3480 3481 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state) 3482 { 3483 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3484 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3485 u32 ctl, pos, size; 3486 3487 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe)); 3488 if ((ctl & PF_ENABLE) == 0) 3489 return; 3490 3491 crtc_state->pch_pfit.enabled = true; 3492 3493 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe)); 3494 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe)); 3495 3496 ilk_get_pfit_pos_size(crtc_state, pos, size); 3497 3498 /* 3499 * We currently do not free assignements of panel fitters on 3500 * ivb/hsw (since we don't use the higher upscaling modes which 3501 * differentiates them) so just WARN about this case for now. 3502 */ 3503 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 7 && 3504 (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe)); 3505 } 3506 3507 static bool ilk_get_pipe_config(struct intel_crtc *crtc, 3508 struct intel_crtc_state *pipe_config) 3509 { 3510 struct drm_device *dev = crtc->base.dev; 3511 struct drm_i915_private *dev_priv = to_i915(dev); 3512 enum intel_display_power_domain power_domain; 3513 intel_wakeref_t wakeref; 3514 u32 tmp; 3515 bool ret; 3516 3517 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3518 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3519 if (!wakeref) 3520 return false; 3521 3522 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3523 pipe_config->shared_dpll = NULL; 3524 3525 ret = false; 3526 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); 3527 if (!(tmp & PIPECONF_ENABLE)) 3528 goto out; 3529 3530 switch (tmp & PIPECONF_BPC_MASK) { 3531 case PIPECONF_BPC_6: 3532 pipe_config->pipe_bpp = 18; 3533 break; 3534 case PIPECONF_BPC_8: 3535 pipe_config->pipe_bpp = 24; 3536 break; 3537 case PIPECONF_BPC_10: 3538 pipe_config->pipe_bpp = 30; 3539 break; 3540 case PIPECONF_BPC_12: 3541 pipe_config->pipe_bpp = 36; 3542 break; 3543 default: 3544 break; 3545 } 3546 3547 if (tmp & PIPECONF_COLOR_RANGE_SELECT) 3548 pipe_config->limited_color_range = true; 3549 3550 switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) { 3551 case PIPECONF_OUTPUT_COLORSPACE_YUV601: 3552 case PIPECONF_OUTPUT_COLORSPACE_YUV709: 3553 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3554 break; 3555 default: 3556 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3557 break; 3558 } 3559 3560 pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_ILK, tmp); 3561 3562 pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1; 3563 3564 pipe_config->msa_timing_delay = REG_FIELD_GET(PIPECONF_MSA_TIMING_DELAY_MASK, tmp); 3565 3566 pipe_config->csc_mode = intel_de_read(dev_priv, 3567 PIPE_CSC_MODE(crtc->pipe)); 3568 3569 i9xx_get_pipe_color_config(pipe_config); 3570 intel_color_get_config(pipe_config); 3571 3572 pipe_config->pixel_multiplier = 1; 3573 3574 ilk_pch_get_config(pipe_config); 3575 3576 intel_get_transcoder_timings(crtc, pipe_config); 3577 intel_get_pipe_src_size(crtc, pipe_config); 3578 3579 ilk_get_pfit_config(pipe_config); 3580 3581 ret = true; 3582 3583 out: 3584 intel_display_power_put(dev_priv, power_domain, wakeref); 3585 3586 return ret; 3587 } 3588 3589 static u8 bigjoiner_pipes(struct drm_i915_private *i915) 3590 { 3591 u8 pipes; 3592 3593 if (DISPLAY_VER(i915) >= 12) 3594 pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D); 3595 else if (DISPLAY_VER(i915) >= 11) 3596 pipes = BIT(PIPE_B) | BIT(PIPE_C); 3597 else 3598 pipes = 0; 3599 3600 return pipes & RUNTIME_INFO(i915)->pipe_mask; 3601 } 3602 3603 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv, 3604 enum transcoder cpu_transcoder) 3605 { 3606 enum intel_display_power_domain power_domain; 3607 intel_wakeref_t wakeref; 3608 u32 tmp = 0; 3609 3610 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3611 3612 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3613 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3614 3615 return tmp & TRANS_DDI_FUNC_ENABLE; 3616 } 3617 3618 static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv, 3619 u8 *master_pipes, u8 *slave_pipes) 3620 { 3621 struct intel_crtc *crtc; 3622 3623 *master_pipes = 0; 3624 *slave_pipes = 0; 3625 3626 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, 3627 bigjoiner_pipes(dev_priv)) { 3628 enum intel_display_power_domain power_domain; 3629 enum pipe pipe = crtc->pipe; 3630 intel_wakeref_t wakeref; 3631 3632 power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe); 3633 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3634 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3635 3636 if (!(tmp & BIG_JOINER_ENABLE)) 3637 continue; 3638 3639 if (tmp & MASTER_BIG_JOINER_ENABLE) 3640 *master_pipes |= BIT(pipe); 3641 else 3642 *slave_pipes |= BIT(pipe); 3643 } 3644 3645 if (DISPLAY_VER(dev_priv) < 13) 3646 continue; 3647 3648 power_domain = POWER_DOMAIN_PIPE(pipe); 3649 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3650 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3651 3652 if (tmp & UNCOMPRESSED_JOINER_MASTER) 3653 *master_pipes |= BIT(pipe); 3654 if (tmp & UNCOMPRESSED_JOINER_SLAVE) 3655 *slave_pipes |= BIT(pipe); 3656 } 3657 } 3658 3659 /* Bigjoiner pipes should always be consecutive master and slave */ 3660 drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1, 3661 "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n", 3662 *master_pipes, *slave_pipes); 3663 } 3664 3665 static enum pipe get_bigjoiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3666 { 3667 if ((slave_pipes & BIT(pipe)) == 0) 3668 return pipe; 3669 3670 /* ignore everything above our pipe */ 3671 master_pipes &= ~GENMASK(7, pipe); 3672 3673 /* highest remaining bit should be our master pipe */ 3674 return fls(master_pipes) - 1; 3675 } 3676 3677 static u8 get_bigjoiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3678 { 3679 enum pipe master_pipe, next_master_pipe; 3680 3681 master_pipe = get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes); 3682 3683 if ((master_pipes & BIT(master_pipe)) == 0) 3684 return 0; 3685 3686 /* ignore our master pipe and everything below it */ 3687 master_pipes &= ~GENMASK(master_pipe, 0); 3688 /* make sure a high bit is set for the ffs() */ 3689 master_pipes |= BIT(7); 3690 /* lowest remaining bit should be the next master pipe */ 3691 next_master_pipe = ffs(master_pipes) - 1; 3692 3693 return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe); 3694 } 3695 3696 static u8 hsw_panel_transcoders(struct drm_i915_private *i915) 3697 { 3698 u8 panel_transcoder_mask = BIT(TRANSCODER_EDP); 3699 3700 if (DISPLAY_VER(i915) >= 11) 3701 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); 3702 3703 return panel_transcoder_mask; 3704 } 3705 3706 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) 3707 { 3708 struct drm_device *dev = crtc->base.dev; 3709 struct drm_i915_private *dev_priv = to_i915(dev); 3710 u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv); 3711 enum transcoder cpu_transcoder; 3712 u8 master_pipes, slave_pipes; 3713 u8 enabled_transcoders = 0; 3714 3715 /* 3716 * XXX: Do intel_display_power_get_if_enabled before reading this (for 3717 * consistency and less surprising code; it's in always on power). 3718 */ 3719 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, 3720 panel_transcoder_mask) { 3721 enum intel_display_power_domain power_domain; 3722 intel_wakeref_t wakeref; 3723 enum pipe trans_pipe; 3724 u32 tmp = 0; 3725 3726 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3727 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3728 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3729 3730 if (!(tmp & TRANS_DDI_FUNC_ENABLE)) 3731 continue; 3732 3733 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 3734 default: 3735 drm_WARN(dev, 1, 3736 "unknown pipe linked to transcoder %s\n", 3737 transcoder_name(cpu_transcoder)); 3738 fallthrough; 3739 case TRANS_DDI_EDP_INPUT_A_ONOFF: 3740 case TRANS_DDI_EDP_INPUT_A_ON: 3741 trans_pipe = PIPE_A; 3742 break; 3743 case TRANS_DDI_EDP_INPUT_B_ONOFF: 3744 trans_pipe = PIPE_B; 3745 break; 3746 case TRANS_DDI_EDP_INPUT_C_ONOFF: 3747 trans_pipe = PIPE_C; 3748 break; 3749 case TRANS_DDI_EDP_INPUT_D_ONOFF: 3750 trans_pipe = PIPE_D; 3751 break; 3752 } 3753 3754 if (trans_pipe == crtc->pipe) 3755 enabled_transcoders |= BIT(cpu_transcoder); 3756 } 3757 3758 /* single pipe or bigjoiner master */ 3759 cpu_transcoder = (enum transcoder) crtc->pipe; 3760 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 3761 enabled_transcoders |= BIT(cpu_transcoder); 3762 3763 /* bigjoiner slave -> consider the master pipe's transcoder as well */ 3764 enabled_bigjoiner_pipes(dev_priv, &master_pipes, &slave_pipes); 3765 if (slave_pipes & BIT(crtc->pipe)) { 3766 cpu_transcoder = (enum transcoder) 3767 get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes); 3768 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 3769 enabled_transcoders |= BIT(cpu_transcoder); 3770 } 3771 3772 return enabled_transcoders; 3773 } 3774 3775 static bool has_edp_transcoders(u8 enabled_transcoders) 3776 { 3777 return enabled_transcoders & BIT(TRANSCODER_EDP); 3778 } 3779 3780 static bool has_dsi_transcoders(u8 enabled_transcoders) 3781 { 3782 return enabled_transcoders & (BIT(TRANSCODER_DSI_0) | 3783 BIT(TRANSCODER_DSI_1)); 3784 } 3785 3786 static bool has_pipe_transcoders(u8 enabled_transcoders) 3787 { 3788 return enabled_transcoders & ~(BIT(TRANSCODER_EDP) | 3789 BIT(TRANSCODER_DSI_0) | 3790 BIT(TRANSCODER_DSI_1)); 3791 } 3792 3793 static void assert_enabled_transcoders(struct drm_i915_private *i915, 3794 u8 enabled_transcoders) 3795 { 3796 /* Only one type of transcoder please */ 3797 drm_WARN_ON(&i915->drm, 3798 has_edp_transcoders(enabled_transcoders) + 3799 has_dsi_transcoders(enabled_transcoders) + 3800 has_pipe_transcoders(enabled_transcoders) > 1); 3801 3802 /* Only DSI transcoders can be ganged */ 3803 drm_WARN_ON(&i915->drm, 3804 !has_dsi_transcoders(enabled_transcoders) && 3805 !is_power_of_2(enabled_transcoders)); 3806 } 3807 3808 static bool hsw_get_transcoder_state(struct intel_crtc *crtc, 3809 struct intel_crtc_state *pipe_config, 3810 struct intel_display_power_domain_set *power_domain_set) 3811 { 3812 struct drm_device *dev = crtc->base.dev; 3813 struct drm_i915_private *dev_priv = to_i915(dev); 3814 unsigned long enabled_transcoders; 3815 u32 tmp; 3816 3817 enabled_transcoders = hsw_enabled_transcoders(crtc); 3818 if (!enabled_transcoders) 3819 return false; 3820 3821 assert_enabled_transcoders(dev_priv, enabled_transcoders); 3822 3823 /* 3824 * With the exception of DSI we should only ever have 3825 * a single enabled transcoder. With DSI let's just 3826 * pick the first one. 3827 */ 3828 pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1; 3829 3830 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 3831 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) 3832 return false; 3833 3834 if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) { 3835 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); 3836 3837 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF) 3838 pipe_config->pch_pfit.force_thru = true; 3839 } 3840 3841 tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder)); 3842 3843 return tmp & PIPECONF_ENABLE; 3844 } 3845 3846 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, 3847 struct intel_crtc_state *pipe_config, 3848 struct intel_display_power_domain_set *power_domain_set) 3849 { 3850 struct drm_device *dev = crtc->base.dev; 3851 struct drm_i915_private *dev_priv = to_i915(dev); 3852 enum transcoder cpu_transcoder; 3853 enum port port; 3854 u32 tmp; 3855 3856 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { 3857 if (port == PORT_A) 3858 cpu_transcoder = TRANSCODER_DSI_A; 3859 else 3860 cpu_transcoder = TRANSCODER_DSI_C; 3861 3862 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 3863 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) 3864 continue; 3865 3866 /* 3867 * The PLL needs to be enabled with a valid divider 3868 * configuration, otherwise accessing DSI registers will hang 3869 * the machine. See BSpec North Display Engine 3870 * registers/MIPI[BXT]. We can break out here early, since we 3871 * need the same DSI PLL to be enabled for both DSI ports. 3872 */ 3873 if (!bxt_dsi_pll_is_enabled(dev_priv)) 3874 break; 3875 3876 /* XXX: this works for video mode only */ 3877 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); 3878 if (!(tmp & DPI_ENABLE)) 3879 continue; 3880 3881 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 3882 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) 3883 continue; 3884 3885 pipe_config->cpu_transcoder = cpu_transcoder; 3886 break; 3887 } 3888 3889 return transcoder_is_dsi(pipe_config->cpu_transcoder); 3890 } 3891 3892 static void intel_bigjoiner_get_config(struct intel_crtc_state *crtc_state) 3893 { 3894 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3895 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 3896 u8 master_pipes, slave_pipes; 3897 enum pipe pipe = crtc->pipe; 3898 3899 enabled_bigjoiner_pipes(i915, &master_pipes, &slave_pipes); 3900 3901 if (((master_pipes | slave_pipes) & BIT(pipe)) == 0) 3902 return; 3903 3904 crtc_state->bigjoiner_pipes = 3905 BIT(get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes)) | 3906 get_bigjoiner_slave_pipes(pipe, master_pipes, slave_pipes); 3907 } 3908 3909 static bool hsw_get_pipe_config(struct intel_crtc *crtc, 3910 struct intel_crtc_state *pipe_config) 3911 { 3912 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3913 bool active; 3914 u32 tmp; 3915 3916 if (!intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains, 3917 POWER_DOMAIN_PIPE(crtc->pipe))) 3918 return false; 3919 3920 pipe_config->shared_dpll = NULL; 3921 3922 active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains); 3923 3924 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 3925 bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) { 3926 drm_WARN_ON(&dev_priv->drm, active); 3927 active = true; 3928 } 3929 3930 if (!active) 3931 goto out; 3932 3933 intel_dsc_get_config(pipe_config); 3934 intel_bigjoiner_get_config(pipe_config); 3935 3936 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || 3937 DISPLAY_VER(dev_priv) >= 11) 3938 intel_get_transcoder_timings(crtc, pipe_config); 3939 3940 if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder)) 3941 intel_vrr_get_config(crtc, pipe_config); 3942 3943 intel_get_pipe_src_size(crtc, pipe_config); 3944 3945 if (IS_HASWELL(dev_priv)) { 3946 u32 tmp = intel_de_read(dev_priv, 3947 PIPECONF(pipe_config->cpu_transcoder)); 3948 3949 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW) 3950 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3951 else 3952 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3953 } else { 3954 pipe_config->output_format = 3955 bdw_get_pipemisc_output_format(crtc); 3956 } 3957 3958 pipe_config->gamma_mode = intel_de_read(dev_priv, 3959 GAMMA_MODE(crtc->pipe)); 3960 3961 pipe_config->csc_mode = intel_de_read(dev_priv, 3962 PIPE_CSC_MODE(crtc->pipe)); 3963 3964 if (DISPLAY_VER(dev_priv) >= 9) { 3965 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe)); 3966 3967 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE) 3968 pipe_config->gamma_enable = true; 3969 3970 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE) 3971 pipe_config->csc_enable = true; 3972 } else { 3973 i9xx_get_pipe_color_config(pipe_config); 3974 } 3975 3976 intel_color_get_config(pipe_config); 3977 3978 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe)); 3979 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); 3980 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 3981 pipe_config->ips_linetime = 3982 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); 3983 3984 if (intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains, 3985 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) { 3986 if (DISPLAY_VER(dev_priv) >= 9) 3987 skl_get_pfit_config(pipe_config); 3988 else 3989 ilk_get_pfit_config(pipe_config); 3990 } 3991 3992 hsw_ips_get_config(pipe_config); 3993 3994 if (pipe_config->cpu_transcoder != TRANSCODER_EDP && 3995 !transcoder_is_dsi(pipe_config->cpu_transcoder)) { 3996 pipe_config->pixel_multiplier = 3997 intel_de_read(dev_priv, 3998 PIPE_MULT(pipe_config->cpu_transcoder)) + 1; 3999 } else { 4000 pipe_config->pixel_multiplier = 1; 4001 } 4002 4003 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { 4004 tmp = intel_de_read(dev_priv, DISPLAY_VER(dev_priv) >= 14 ? 4005 MTL_CHICKEN_TRANS(pipe_config->cpu_transcoder) : 4006 CHICKEN_TRANS(pipe_config->cpu_transcoder)); 4007 4008 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1; 4009 } else { 4010 /* no idea if this is correct */ 4011 pipe_config->framestart_delay = 1; 4012 } 4013 4014 out: 4015 intel_display_power_put_all_in_set(dev_priv, &crtc->hw_readout_power_domains); 4016 4017 return active; 4018 } 4019 4020 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state) 4021 { 4022 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4023 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4024 4025 if (!i915->display.funcs.display->get_pipe_config(crtc, crtc_state)) 4026 return false; 4027 4028 crtc_state->hw.active = true; 4029 4030 intel_crtc_readout_derived_state(crtc_state); 4031 4032 return true; 4033 } 4034 4035 /* VESA 640x480x72Hz mode to set on the pipe */ 4036 static const struct drm_display_mode load_detect_mode = { 4037 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, 4038 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 4039 }; 4040 4041 static int intel_modeset_disable_planes(struct drm_atomic_state *state, 4042 struct drm_crtc *crtc) 4043 { 4044 struct drm_plane *plane; 4045 struct drm_plane_state *plane_state; 4046 int ret, i; 4047 4048 ret = drm_atomic_add_affected_planes(state, crtc); 4049 if (ret) 4050 return ret; 4051 4052 for_each_new_plane_in_state(state, plane, plane_state, i) { 4053 if (plane_state->crtc != crtc) 4054 continue; 4055 4056 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL); 4057 if (ret) 4058 return ret; 4059 4060 drm_atomic_set_fb_for_plane(plane_state, NULL); 4061 } 4062 4063 return 0; 4064 } 4065 4066 int intel_get_load_detect_pipe(struct drm_connector *connector, 4067 struct intel_load_detect_pipe *old, 4068 struct drm_modeset_acquire_ctx *ctx) 4069 { 4070 struct intel_encoder *encoder = 4071 intel_attached_encoder(to_intel_connector(connector)); 4072 struct intel_crtc *possible_crtc; 4073 struct intel_crtc *crtc = NULL; 4074 struct drm_device *dev = encoder->base.dev; 4075 struct drm_i915_private *dev_priv = to_i915(dev); 4076 struct drm_mode_config *config = &dev->mode_config; 4077 struct drm_atomic_state *state = NULL, *restore_state = NULL; 4078 struct drm_connector_state *connector_state; 4079 struct intel_crtc_state *crtc_state; 4080 int ret; 4081 4082 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 4083 connector->base.id, connector->name, 4084 encoder->base.base.id, encoder->base.name); 4085 4086 old->restore_state = NULL; 4087 4088 drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex)); 4089 4090 /* 4091 * Algorithm gets a little messy: 4092 * 4093 * - if the connector already has an assigned crtc, use it (but make 4094 * sure it's on first) 4095 * 4096 * - try to find the first unused crtc that can drive this connector, 4097 * and use that if we find one 4098 */ 4099 4100 /* See if we already have a CRTC for this connector */ 4101 if (connector->state->crtc) { 4102 crtc = to_intel_crtc(connector->state->crtc); 4103 4104 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4105 if (ret) 4106 goto fail; 4107 4108 /* Make sure the crtc and connector are running */ 4109 goto found; 4110 } 4111 4112 /* Find an unused one (if possible) */ 4113 for_each_intel_crtc(dev, possible_crtc) { 4114 if (!(encoder->base.possible_crtcs & 4115 drm_crtc_mask(&possible_crtc->base))) 4116 continue; 4117 4118 ret = drm_modeset_lock(&possible_crtc->base.mutex, ctx); 4119 if (ret) 4120 goto fail; 4121 4122 if (possible_crtc->base.state->enable) { 4123 drm_modeset_unlock(&possible_crtc->base.mutex); 4124 continue; 4125 } 4126 4127 crtc = possible_crtc; 4128 break; 4129 } 4130 4131 /* 4132 * If we didn't find an unused CRTC, don't use any. 4133 */ 4134 if (!crtc) { 4135 drm_dbg_kms(&dev_priv->drm, 4136 "no pipe available for load-detect\n"); 4137 ret = -ENODEV; 4138 goto fail; 4139 } 4140 4141 found: 4142 state = drm_atomic_state_alloc(dev); 4143 restore_state = drm_atomic_state_alloc(dev); 4144 if (!state || !restore_state) { 4145 ret = -ENOMEM; 4146 goto fail; 4147 } 4148 4149 state->acquire_ctx = ctx; 4150 restore_state->acquire_ctx = ctx; 4151 4152 connector_state = drm_atomic_get_connector_state(state, connector); 4153 if (IS_ERR(connector_state)) { 4154 ret = PTR_ERR(connector_state); 4155 goto fail; 4156 } 4157 4158 ret = drm_atomic_set_crtc_for_connector(connector_state, &crtc->base); 4159 if (ret) 4160 goto fail; 4161 4162 crtc_state = intel_atomic_get_crtc_state(state, crtc); 4163 if (IS_ERR(crtc_state)) { 4164 ret = PTR_ERR(crtc_state); 4165 goto fail; 4166 } 4167 4168 crtc_state->uapi.active = true; 4169 4170 ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi, 4171 &load_detect_mode); 4172 if (ret) 4173 goto fail; 4174 4175 ret = intel_modeset_disable_planes(state, &crtc->base); 4176 if (ret) 4177 goto fail; 4178 4179 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); 4180 if (!ret) 4181 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, &crtc->base)); 4182 if (!ret) 4183 ret = drm_atomic_add_affected_planes(restore_state, &crtc->base); 4184 if (ret) { 4185 drm_dbg_kms(&dev_priv->drm, 4186 "Failed to create a copy of old state to restore: %i\n", 4187 ret); 4188 goto fail; 4189 } 4190 4191 ret = drm_atomic_commit(state); 4192 if (ret) { 4193 drm_dbg_kms(&dev_priv->drm, 4194 "failed to set mode on load-detect pipe\n"); 4195 goto fail; 4196 } 4197 4198 old->restore_state = restore_state; 4199 drm_atomic_state_put(state); 4200 4201 /* let the connector get through one full cycle before testing */ 4202 intel_crtc_wait_for_next_vblank(crtc); 4203 4204 return true; 4205 4206 fail: 4207 if (state) { 4208 drm_atomic_state_put(state); 4209 state = NULL; 4210 } 4211 if (restore_state) { 4212 drm_atomic_state_put(restore_state); 4213 restore_state = NULL; 4214 } 4215 4216 if (ret == -EDEADLK) 4217 return ret; 4218 4219 return false; 4220 } 4221 4222 void intel_release_load_detect_pipe(struct drm_connector *connector, 4223 struct intel_load_detect_pipe *old, 4224 struct drm_modeset_acquire_ctx *ctx) 4225 { 4226 struct intel_encoder *intel_encoder = 4227 intel_attached_encoder(to_intel_connector(connector)); 4228 struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev); 4229 struct drm_encoder *encoder = &intel_encoder->base; 4230 struct drm_atomic_state *state = old->restore_state; 4231 int ret; 4232 4233 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 4234 connector->base.id, connector->name, 4235 encoder->base.id, encoder->name); 4236 4237 if (!state) 4238 return; 4239 4240 ret = drm_atomic_helper_commit_duplicated_state(state, ctx); 4241 if (ret) 4242 drm_dbg_kms(&i915->drm, 4243 "Couldn't release load detect pipe: %i\n", ret); 4244 drm_atomic_state_put(state); 4245 } 4246 4247 static int i9xx_pll_refclk(struct drm_device *dev, 4248 const struct intel_crtc_state *pipe_config) 4249 { 4250 struct drm_i915_private *dev_priv = to_i915(dev); 4251 u32 dpll = pipe_config->dpll_hw_state.dpll; 4252 4253 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) 4254 return dev_priv->display.vbt.lvds_ssc_freq; 4255 else if (HAS_PCH_SPLIT(dev_priv)) 4256 return 120000; 4257 else if (DISPLAY_VER(dev_priv) != 2) 4258 return 96000; 4259 else 4260 return 48000; 4261 } 4262 4263 /* Returns the clock of the currently programmed mode of the given pipe. */ 4264 void i9xx_crtc_clock_get(struct intel_crtc *crtc, 4265 struct intel_crtc_state *pipe_config) 4266 { 4267 struct drm_device *dev = crtc->base.dev; 4268 struct drm_i915_private *dev_priv = to_i915(dev); 4269 u32 dpll = pipe_config->dpll_hw_state.dpll; 4270 u32 fp; 4271 struct dpll clock; 4272 int port_clock; 4273 int refclk = i9xx_pll_refclk(dev, pipe_config); 4274 4275 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 4276 fp = pipe_config->dpll_hw_state.fp0; 4277 else 4278 fp = pipe_config->dpll_hw_state.fp1; 4279 4280 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 4281 if (IS_PINEVIEW(dev_priv)) { 4282 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; 4283 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; 4284 } else { 4285 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 4286 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 4287 } 4288 4289 if (DISPLAY_VER(dev_priv) != 2) { 4290 if (IS_PINEVIEW(dev_priv)) 4291 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> 4292 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); 4293 else 4294 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> 4295 DPLL_FPA01_P1_POST_DIV_SHIFT); 4296 4297 switch (dpll & DPLL_MODE_MASK) { 4298 case DPLLB_MODE_DAC_SERIAL: 4299 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 4300 5 : 10; 4301 break; 4302 case DPLLB_MODE_LVDS: 4303 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 4304 7 : 14; 4305 break; 4306 default: 4307 drm_dbg_kms(&dev_priv->drm, 4308 "Unknown DPLL mode %08x in programmed " 4309 "mode\n", (int)(dpll & DPLL_MODE_MASK)); 4310 return; 4311 } 4312 4313 if (IS_PINEVIEW(dev_priv)) 4314 port_clock = pnv_calc_dpll_params(refclk, &clock); 4315 else 4316 port_clock = i9xx_calc_dpll_params(refclk, &clock); 4317 } else { 4318 enum pipe lvds_pipe; 4319 4320 if (IS_I85X(dev_priv) && 4321 intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) && 4322 lvds_pipe == crtc->pipe) { 4323 u32 lvds = intel_de_read(dev_priv, LVDS); 4324 4325 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 4326 DPLL_FPA01_P1_POST_DIV_SHIFT); 4327 4328 if (lvds & LVDS_CLKB_POWER_UP) 4329 clock.p2 = 7; 4330 else 4331 clock.p2 = 14; 4332 } else { 4333 if (dpll & PLL_P1_DIVIDE_BY_TWO) 4334 clock.p1 = 2; 4335 else { 4336 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 4337 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 4338 } 4339 if (dpll & PLL_P2_DIVIDE_BY_4) 4340 clock.p2 = 4; 4341 else 4342 clock.p2 = 2; 4343 } 4344 4345 port_clock = i9xx_calc_dpll_params(refclk, &clock); 4346 } 4347 4348 /* 4349 * This value includes pixel_multiplier. We will use 4350 * port_clock to compute adjusted_mode.crtc_clock in the 4351 * encoder's get_config() function. 4352 */ 4353 pipe_config->port_clock = port_clock; 4354 } 4355 4356 int intel_dotclock_calculate(int link_freq, 4357 const struct intel_link_m_n *m_n) 4358 { 4359 /* 4360 * The calculation for the data clock is: 4361 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp 4362 * But we want to avoid losing precison if possible, so: 4363 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) 4364 * 4365 * and the link clock is simpler: 4366 * link_clock = (m * link_clock) / n 4367 */ 4368 4369 if (!m_n->link_n) 4370 return 0; 4371 4372 return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq), 4373 m_n->link_n); 4374 } 4375 4376 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config) 4377 { 4378 int dotclock; 4379 4380 if (intel_crtc_has_dp_encoder(pipe_config)) 4381 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 4382 &pipe_config->dp_m_n); 4383 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) 4384 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24, 4385 pipe_config->pipe_bpp); 4386 else 4387 dotclock = pipe_config->port_clock; 4388 4389 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 4390 !intel_crtc_has_dp_encoder(pipe_config)) 4391 dotclock *= 2; 4392 4393 if (pipe_config->pixel_multiplier) 4394 dotclock /= pipe_config->pixel_multiplier; 4395 4396 return dotclock; 4397 } 4398 4399 /* Returns the currently programmed mode of the given encoder. */ 4400 struct drm_display_mode * 4401 intel_encoder_current_mode(struct intel_encoder *encoder) 4402 { 4403 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4404 struct intel_crtc_state *crtc_state; 4405 struct drm_display_mode *mode; 4406 struct intel_crtc *crtc; 4407 enum pipe pipe; 4408 4409 if (!encoder->get_hw_state(encoder, &pipe)) 4410 return NULL; 4411 4412 crtc = intel_crtc_for_pipe(dev_priv, pipe); 4413 4414 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 4415 if (!mode) 4416 return NULL; 4417 4418 crtc_state = intel_crtc_state_alloc(crtc); 4419 if (!crtc_state) { 4420 kfree(mode); 4421 return NULL; 4422 } 4423 4424 if (!intel_crtc_get_pipe_config(crtc_state)) { 4425 kfree(crtc_state); 4426 kfree(mode); 4427 return NULL; 4428 } 4429 4430 intel_encoder_get_config(encoder, crtc_state); 4431 4432 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode); 4433 4434 kfree(crtc_state); 4435 4436 return mode; 4437 } 4438 4439 static bool encoders_cloneable(const struct intel_encoder *a, 4440 const struct intel_encoder *b) 4441 { 4442 /* masks could be asymmetric, so check both ways */ 4443 return a == b || (a->cloneable & BIT(b->type) && 4444 b->cloneable & BIT(a->type)); 4445 } 4446 4447 static bool check_single_encoder_cloning(struct intel_atomic_state *state, 4448 struct intel_crtc *crtc, 4449 struct intel_encoder *encoder) 4450 { 4451 struct intel_encoder *source_encoder; 4452 struct drm_connector *connector; 4453 struct drm_connector_state *connector_state; 4454 int i; 4455 4456 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4457 if (connector_state->crtc != &crtc->base) 4458 continue; 4459 4460 source_encoder = 4461 to_intel_encoder(connector_state->best_encoder); 4462 if (!encoders_cloneable(encoder, source_encoder)) 4463 return false; 4464 } 4465 4466 return true; 4467 } 4468 4469 static int icl_add_linked_planes(struct intel_atomic_state *state) 4470 { 4471 struct intel_plane *plane, *linked; 4472 struct intel_plane_state *plane_state, *linked_plane_state; 4473 int i; 4474 4475 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4476 linked = plane_state->planar_linked_plane; 4477 4478 if (!linked) 4479 continue; 4480 4481 linked_plane_state = intel_atomic_get_plane_state(state, linked); 4482 if (IS_ERR(linked_plane_state)) 4483 return PTR_ERR(linked_plane_state); 4484 4485 drm_WARN_ON(state->base.dev, 4486 linked_plane_state->planar_linked_plane != plane); 4487 drm_WARN_ON(state->base.dev, 4488 linked_plane_state->planar_slave == plane_state->planar_slave); 4489 } 4490 4491 return 0; 4492 } 4493 4494 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state) 4495 { 4496 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4497 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4498 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 4499 struct intel_plane *plane, *linked; 4500 struct intel_plane_state *plane_state; 4501 int i; 4502 4503 if (DISPLAY_VER(dev_priv) < 11) 4504 return 0; 4505 4506 /* 4507 * Destroy all old plane links and make the slave plane invisible 4508 * in the crtc_state->active_planes mask. 4509 */ 4510 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4511 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane) 4512 continue; 4513 4514 plane_state->planar_linked_plane = NULL; 4515 if (plane_state->planar_slave && !plane_state->uapi.visible) { 4516 crtc_state->enabled_planes &= ~BIT(plane->id); 4517 crtc_state->active_planes &= ~BIT(plane->id); 4518 crtc_state->update_planes |= BIT(plane->id); 4519 crtc_state->data_rate[plane->id] = 0; 4520 crtc_state->rel_data_rate[plane->id] = 0; 4521 } 4522 4523 plane_state->planar_slave = false; 4524 } 4525 4526 if (!crtc_state->nv12_planes) 4527 return 0; 4528 4529 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4530 struct intel_plane_state *linked_state = NULL; 4531 4532 if (plane->pipe != crtc->pipe || 4533 !(crtc_state->nv12_planes & BIT(plane->id))) 4534 continue; 4535 4536 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) { 4537 if (!icl_is_nv12_y_plane(dev_priv, linked->id)) 4538 continue; 4539 4540 if (crtc_state->active_planes & BIT(linked->id)) 4541 continue; 4542 4543 linked_state = intel_atomic_get_plane_state(state, linked); 4544 if (IS_ERR(linked_state)) 4545 return PTR_ERR(linked_state); 4546 4547 break; 4548 } 4549 4550 if (!linked_state) { 4551 drm_dbg_kms(&dev_priv->drm, 4552 "Need %d free Y planes for planar YUV\n", 4553 hweight8(crtc_state->nv12_planes)); 4554 4555 return -EINVAL; 4556 } 4557 4558 plane_state->planar_linked_plane = linked; 4559 4560 linked_state->planar_slave = true; 4561 linked_state->planar_linked_plane = plane; 4562 crtc_state->enabled_planes |= BIT(linked->id); 4563 crtc_state->active_planes |= BIT(linked->id); 4564 crtc_state->update_planes |= BIT(linked->id); 4565 crtc_state->data_rate[linked->id] = 4566 crtc_state->data_rate_y[plane->id]; 4567 crtc_state->rel_data_rate[linked->id] = 4568 crtc_state->rel_data_rate_y[plane->id]; 4569 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n", 4570 linked->base.name, plane->base.name); 4571 4572 /* Copy parameters to slave plane */ 4573 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE; 4574 linked_state->color_ctl = plane_state->color_ctl; 4575 linked_state->view = plane_state->view; 4576 linked_state->decrypt = plane_state->decrypt; 4577 4578 intel_plane_copy_hw_state(linked_state, plane_state); 4579 linked_state->uapi.src = plane_state->uapi.src; 4580 linked_state->uapi.dst = plane_state->uapi.dst; 4581 4582 if (icl_is_hdr_plane(dev_priv, plane->id)) { 4583 if (linked->id == PLANE_SPRITE5) 4584 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL; 4585 else if (linked->id == PLANE_SPRITE4) 4586 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL; 4587 else if (linked->id == PLANE_SPRITE3) 4588 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL; 4589 else if (linked->id == PLANE_SPRITE2) 4590 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL; 4591 else 4592 MISSING_CASE(linked->id); 4593 } 4594 } 4595 4596 return 0; 4597 } 4598 4599 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state) 4600 { 4601 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 4602 struct intel_atomic_state *state = 4603 to_intel_atomic_state(new_crtc_state->uapi.state); 4604 const struct intel_crtc_state *old_crtc_state = 4605 intel_atomic_get_old_crtc_state(state, crtc); 4606 4607 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes; 4608 } 4609 4610 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) 4611 { 4612 const struct drm_display_mode *pipe_mode = 4613 &crtc_state->hw.pipe_mode; 4614 int linetime_wm; 4615 4616 if (!crtc_state->hw.enable) 4617 return 0; 4618 4619 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4620 pipe_mode->crtc_clock); 4621 4622 return min(linetime_wm, 0x1ff); 4623 } 4624 4625 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, 4626 const struct intel_cdclk_state *cdclk_state) 4627 { 4628 const struct drm_display_mode *pipe_mode = 4629 &crtc_state->hw.pipe_mode; 4630 int linetime_wm; 4631 4632 if (!crtc_state->hw.enable) 4633 return 0; 4634 4635 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4636 cdclk_state->logical.cdclk); 4637 4638 return min(linetime_wm, 0x1ff); 4639 } 4640 4641 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) 4642 { 4643 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4644 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4645 const struct drm_display_mode *pipe_mode = 4646 &crtc_state->hw.pipe_mode; 4647 int linetime_wm; 4648 4649 if (!crtc_state->hw.enable) 4650 return 0; 4651 4652 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8, 4653 crtc_state->pixel_rate); 4654 4655 /* Display WA #1135: BXT:ALL GLK:ALL */ 4656 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 4657 skl_watermark_ipc_enabled(dev_priv)) 4658 linetime_wm /= 2; 4659 4660 return min(linetime_wm, 0x1ff); 4661 } 4662 4663 static int hsw_compute_linetime_wm(struct intel_atomic_state *state, 4664 struct intel_crtc *crtc) 4665 { 4666 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4667 struct intel_crtc_state *crtc_state = 4668 intel_atomic_get_new_crtc_state(state, crtc); 4669 const struct intel_cdclk_state *cdclk_state; 4670 4671 if (DISPLAY_VER(dev_priv) >= 9) 4672 crtc_state->linetime = skl_linetime_wm(crtc_state); 4673 else 4674 crtc_state->linetime = hsw_linetime_wm(crtc_state); 4675 4676 if (!hsw_crtc_supports_ips(crtc)) 4677 return 0; 4678 4679 cdclk_state = intel_atomic_get_cdclk_state(state); 4680 if (IS_ERR(cdclk_state)) 4681 return PTR_ERR(cdclk_state); 4682 4683 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state, 4684 cdclk_state); 4685 4686 return 0; 4687 } 4688 4689 static int intel_crtc_atomic_check(struct intel_atomic_state *state, 4690 struct intel_crtc *crtc) 4691 { 4692 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4693 struct intel_crtc_state *crtc_state = 4694 intel_atomic_get_new_crtc_state(state, crtc); 4695 int ret; 4696 4697 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) && 4698 intel_crtc_needs_modeset(crtc_state) && 4699 !crtc_state->hw.active) 4700 crtc_state->update_wm_post = true; 4701 4702 if (intel_crtc_needs_modeset(crtc_state)) { 4703 ret = intel_dpll_crtc_get_shared_dpll(state, crtc); 4704 if (ret) 4705 return ret; 4706 } 4707 4708 /* 4709 * May need to update pipe gamma enable bits 4710 * when C8 planes are getting enabled/disabled. 4711 */ 4712 if (c8_planes_changed(crtc_state)) 4713 crtc_state->uapi.color_mgmt_changed = true; 4714 4715 if (intel_crtc_needs_color_update(crtc_state)) { 4716 ret = intel_color_check(crtc_state); 4717 if (ret) 4718 return ret; 4719 } 4720 4721 ret = intel_compute_pipe_wm(state, crtc); 4722 if (ret) { 4723 drm_dbg_kms(&dev_priv->drm, 4724 "Target pipe watermarks are invalid\n"); 4725 return ret; 4726 } 4727 4728 /* 4729 * Calculate 'intermediate' watermarks that satisfy both the 4730 * old state and the new state. We can program these 4731 * immediately. 4732 */ 4733 ret = intel_compute_intermediate_wm(state, crtc); 4734 if (ret) { 4735 drm_dbg_kms(&dev_priv->drm, 4736 "No valid intermediate pipe watermarks are possible\n"); 4737 return ret; 4738 } 4739 4740 if (DISPLAY_VER(dev_priv) >= 9) { 4741 if (intel_crtc_needs_modeset(crtc_state) || 4742 intel_crtc_needs_fastset(crtc_state)) { 4743 ret = skl_update_scaler_crtc(crtc_state); 4744 if (ret) 4745 return ret; 4746 } 4747 4748 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state); 4749 if (ret) 4750 return ret; 4751 } 4752 4753 if (HAS_IPS(dev_priv)) { 4754 ret = hsw_ips_compute_config(state, crtc); 4755 if (ret) 4756 return ret; 4757 } 4758 4759 if (DISPLAY_VER(dev_priv) >= 9 || 4760 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 4761 ret = hsw_compute_linetime_wm(state, crtc); 4762 if (ret) 4763 return ret; 4764 4765 } 4766 4767 ret = intel_psr2_sel_fetch_update(state, crtc); 4768 if (ret) 4769 return ret; 4770 4771 return 0; 4772 } 4773 4774 static int 4775 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state, 4776 struct intel_crtc_state *crtc_state) 4777 { 4778 struct drm_connector *connector = conn_state->connector; 4779 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 4780 const struct drm_display_info *info = &connector->display_info; 4781 int bpp; 4782 4783 switch (conn_state->max_bpc) { 4784 case 6 ... 7: 4785 bpp = 6 * 3; 4786 break; 4787 case 8 ... 9: 4788 bpp = 8 * 3; 4789 break; 4790 case 10 ... 11: 4791 bpp = 10 * 3; 4792 break; 4793 case 12 ... 16: 4794 bpp = 12 * 3; 4795 break; 4796 default: 4797 MISSING_CASE(conn_state->max_bpc); 4798 return -EINVAL; 4799 } 4800 4801 if (bpp < crtc_state->pipe_bpp) { 4802 drm_dbg_kms(&i915->drm, 4803 "[CONNECTOR:%d:%s] Limiting display bpp to %d " 4804 "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n", 4805 connector->base.id, connector->name, 4806 bpp, 3 * info->bpc, 4807 3 * conn_state->max_requested_bpc, 4808 crtc_state->pipe_bpp); 4809 4810 crtc_state->pipe_bpp = bpp; 4811 } 4812 4813 return 0; 4814 } 4815 4816 static int 4817 compute_baseline_pipe_bpp(struct intel_atomic_state *state, 4818 struct intel_crtc *crtc) 4819 { 4820 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4821 struct intel_crtc_state *crtc_state = 4822 intel_atomic_get_new_crtc_state(state, crtc); 4823 struct drm_connector *connector; 4824 struct drm_connector_state *connector_state; 4825 int bpp, i; 4826 4827 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 4828 IS_CHERRYVIEW(dev_priv))) 4829 bpp = 10*3; 4830 else if (DISPLAY_VER(dev_priv) >= 5) 4831 bpp = 12*3; 4832 else 4833 bpp = 8*3; 4834 4835 crtc_state->pipe_bpp = bpp; 4836 4837 /* Clamp display bpp to connector max bpp */ 4838 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4839 int ret; 4840 4841 if (connector_state->crtc != &crtc->base) 4842 continue; 4843 4844 ret = compute_sink_pipe_bpp(connector_state, crtc_state); 4845 if (ret) 4846 return ret; 4847 } 4848 4849 return 0; 4850 } 4851 4852 static bool check_digital_port_conflicts(struct intel_atomic_state *state) 4853 { 4854 struct drm_device *dev = state->base.dev; 4855 struct drm_connector *connector; 4856 struct drm_connector_list_iter conn_iter; 4857 unsigned int used_ports = 0; 4858 unsigned int used_mst_ports = 0; 4859 bool ret = true; 4860 4861 /* 4862 * We're going to peek into connector->state, 4863 * hence connection_mutex must be held. 4864 */ 4865 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex); 4866 4867 /* 4868 * Walk the connector list instead of the encoder 4869 * list to detect the problem on ddi platforms 4870 * where there's just one encoder per digital port. 4871 */ 4872 drm_connector_list_iter_begin(dev, &conn_iter); 4873 drm_for_each_connector_iter(connector, &conn_iter) { 4874 struct drm_connector_state *connector_state; 4875 struct intel_encoder *encoder; 4876 4877 connector_state = 4878 drm_atomic_get_new_connector_state(&state->base, 4879 connector); 4880 if (!connector_state) 4881 connector_state = connector->state; 4882 4883 if (!connector_state->best_encoder) 4884 continue; 4885 4886 encoder = to_intel_encoder(connector_state->best_encoder); 4887 4888 drm_WARN_ON(dev, !connector_state->crtc); 4889 4890 switch (encoder->type) { 4891 case INTEL_OUTPUT_DDI: 4892 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev)))) 4893 break; 4894 fallthrough; 4895 case INTEL_OUTPUT_DP: 4896 case INTEL_OUTPUT_HDMI: 4897 case INTEL_OUTPUT_EDP: 4898 /* the same port mustn't appear more than once */ 4899 if (used_ports & BIT(encoder->port)) 4900 ret = false; 4901 4902 used_ports |= BIT(encoder->port); 4903 break; 4904 case INTEL_OUTPUT_DP_MST: 4905 used_mst_ports |= 4906 1 << encoder->port; 4907 break; 4908 default: 4909 break; 4910 } 4911 } 4912 drm_connector_list_iter_end(&conn_iter); 4913 4914 /* can't mix MST and SST/HDMI on the same port */ 4915 if (used_ports & used_mst_ports) 4916 return false; 4917 4918 return ret; 4919 } 4920 4921 static void 4922 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state, 4923 struct intel_crtc *crtc) 4924 { 4925 struct intel_crtc_state *crtc_state = 4926 intel_atomic_get_new_crtc_state(state, crtc); 4927 4928 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 4929 4930 drm_property_replace_blob(&crtc_state->hw.degamma_lut, 4931 crtc_state->uapi.degamma_lut); 4932 drm_property_replace_blob(&crtc_state->hw.gamma_lut, 4933 crtc_state->uapi.gamma_lut); 4934 drm_property_replace_blob(&crtc_state->hw.ctm, 4935 crtc_state->uapi.ctm); 4936 } 4937 4938 static void 4939 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state, 4940 struct intel_crtc *crtc) 4941 { 4942 struct intel_crtc_state *crtc_state = 4943 intel_atomic_get_new_crtc_state(state, crtc); 4944 4945 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 4946 4947 crtc_state->hw.enable = crtc_state->uapi.enable; 4948 crtc_state->hw.active = crtc_state->uapi.active; 4949 drm_mode_copy(&crtc_state->hw.mode, 4950 &crtc_state->uapi.mode); 4951 drm_mode_copy(&crtc_state->hw.adjusted_mode, 4952 &crtc_state->uapi.adjusted_mode); 4953 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter; 4954 4955 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 4956 } 4957 4958 static void 4959 copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state, 4960 struct intel_crtc *slave_crtc) 4961 { 4962 struct intel_crtc_state *slave_crtc_state = 4963 intel_atomic_get_new_crtc_state(state, slave_crtc); 4964 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 4965 const struct intel_crtc_state *master_crtc_state = 4966 intel_atomic_get_new_crtc_state(state, master_crtc); 4967 4968 drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut, 4969 master_crtc_state->hw.degamma_lut); 4970 drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut, 4971 master_crtc_state->hw.gamma_lut); 4972 drm_property_replace_blob(&slave_crtc_state->hw.ctm, 4973 master_crtc_state->hw.ctm); 4974 4975 slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed; 4976 } 4977 4978 static int 4979 copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state, 4980 struct intel_crtc *slave_crtc) 4981 { 4982 struct intel_crtc_state *slave_crtc_state = 4983 intel_atomic_get_new_crtc_state(state, slave_crtc); 4984 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 4985 const struct intel_crtc_state *master_crtc_state = 4986 intel_atomic_get_new_crtc_state(state, master_crtc); 4987 struct intel_crtc_state *saved_state; 4988 4989 WARN_ON(master_crtc_state->bigjoiner_pipes != 4990 slave_crtc_state->bigjoiner_pipes); 4991 4992 saved_state = kmemdup(master_crtc_state, sizeof(*saved_state), GFP_KERNEL); 4993 if (!saved_state) 4994 return -ENOMEM; 4995 4996 /* preserve some things from the slave's original crtc state */ 4997 saved_state->uapi = slave_crtc_state->uapi; 4998 saved_state->scaler_state = slave_crtc_state->scaler_state; 4999 saved_state->shared_dpll = slave_crtc_state->shared_dpll; 5000 saved_state->dpll_hw_state = slave_crtc_state->dpll_hw_state; 5001 saved_state->crc_enabled = slave_crtc_state->crc_enabled; 5002 5003 intel_crtc_free_hw_state(slave_crtc_state); 5004 memcpy(slave_crtc_state, saved_state, sizeof(*slave_crtc_state)); 5005 kfree(saved_state); 5006 5007 /* Re-init hw state */ 5008 memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw)); 5009 slave_crtc_state->hw.enable = master_crtc_state->hw.enable; 5010 slave_crtc_state->hw.active = master_crtc_state->hw.active; 5011 drm_mode_copy(&slave_crtc_state->hw.mode, 5012 &master_crtc_state->hw.mode); 5013 drm_mode_copy(&slave_crtc_state->hw.pipe_mode, 5014 &master_crtc_state->hw.pipe_mode); 5015 drm_mode_copy(&slave_crtc_state->hw.adjusted_mode, 5016 &master_crtc_state->hw.adjusted_mode); 5017 slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter; 5018 5019 copy_bigjoiner_crtc_state_nomodeset(state, slave_crtc); 5020 5021 slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed; 5022 slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed; 5023 slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed; 5024 5025 WARN_ON(master_crtc_state->bigjoiner_pipes != 5026 slave_crtc_state->bigjoiner_pipes); 5027 5028 return 0; 5029 } 5030 5031 static int 5032 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state, 5033 struct intel_crtc *crtc) 5034 { 5035 struct intel_crtc_state *crtc_state = 5036 intel_atomic_get_new_crtc_state(state, crtc); 5037 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5038 struct intel_crtc_state *saved_state; 5039 5040 saved_state = intel_crtc_state_alloc(crtc); 5041 if (!saved_state) 5042 return -ENOMEM; 5043 5044 /* free the old crtc_state->hw members */ 5045 intel_crtc_free_hw_state(crtc_state); 5046 5047 /* FIXME: before the switch to atomic started, a new pipe_config was 5048 * kzalloc'd. Code that depends on any field being zero should be 5049 * fixed, so that the crtc_state can be safely duplicated. For now, 5050 * only fields that are know to not cause problems are preserved. */ 5051 5052 saved_state->uapi = crtc_state->uapi; 5053 saved_state->scaler_state = crtc_state->scaler_state; 5054 saved_state->shared_dpll = crtc_state->shared_dpll; 5055 saved_state->dpll_hw_state = crtc_state->dpll_hw_state; 5056 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, 5057 sizeof(saved_state->icl_port_dplls)); 5058 saved_state->crc_enabled = crtc_state->crc_enabled; 5059 if (IS_G4X(dev_priv) || 5060 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5061 saved_state->wm = crtc_state->wm; 5062 5063 memcpy(crtc_state, saved_state, sizeof(*crtc_state)); 5064 kfree(saved_state); 5065 5066 intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc); 5067 5068 return 0; 5069 } 5070 5071 static int 5072 intel_modeset_pipe_config(struct intel_atomic_state *state, 5073 struct intel_crtc *crtc) 5074 { 5075 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 5076 struct intel_crtc_state *crtc_state = 5077 intel_atomic_get_new_crtc_state(state, crtc); 5078 struct drm_connector *connector; 5079 struct drm_connector_state *connector_state; 5080 int pipe_src_w, pipe_src_h; 5081 int base_bpp, ret, i; 5082 bool retry = true; 5083 5084 crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe; 5085 5086 crtc_state->framestart_delay = 1; 5087 5088 /* 5089 * Sanitize sync polarity flags based on requested ones. If neither 5090 * positive or negative polarity is requested, treat this as meaning 5091 * negative polarity. 5092 */ 5093 if (!(crtc_state->hw.adjusted_mode.flags & 5094 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) 5095 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; 5096 5097 if (!(crtc_state->hw.adjusted_mode.flags & 5098 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 5099 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; 5100 5101 ret = compute_baseline_pipe_bpp(state, crtc); 5102 if (ret) 5103 return ret; 5104 5105 base_bpp = crtc_state->pipe_bpp; 5106 5107 /* 5108 * Determine the real pipe dimensions. Note that stereo modes can 5109 * increase the actual pipe size due to the frame doubling and 5110 * insertion of additional space for blanks between the frame. This 5111 * is stored in the crtc timings. We use the requested mode to do this 5112 * computation to clearly distinguish it from the adjusted mode, which 5113 * can be changed by the connectors in the below retry loop. 5114 */ 5115 drm_mode_get_hv_timing(&crtc_state->hw.mode, 5116 &pipe_src_w, &pipe_src_h); 5117 drm_rect_init(&crtc_state->pipe_src, 0, 0, 5118 pipe_src_w, pipe_src_h); 5119 5120 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5121 struct intel_encoder *encoder = 5122 to_intel_encoder(connector_state->best_encoder); 5123 5124 if (connector_state->crtc != &crtc->base) 5125 continue; 5126 5127 if (!check_single_encoder_cloning(state, crtc, encoder)) { 5128 drm_dbg_kms(&i915->drm, 5129 "[ENCODER:%d:%s] rejecting invalid cloning configuration\n", 5130 encoder->base.base.id, encoder->base.name); 5131 return -EINVAL; 5132 } 5133 5134 /* 5135 * Determine output_types before calling the .compute_config() 5136 * hooks so that the hooks can use this information safely. 5137 */ 5138 if (encoder->compute_output_type) 5139 crtc_state->output_types |= 5140 BIT(encoder->compute_output_type(encoder, crtc_state, 5141 connector_state)); 5142 else 5143 crtc_state->output_types |= BIT(encoder->type); 5144 } 5145 5146 encoder_retry: 5147 /* Ensure the port clock defaults are reset when retrying. */ 5148 crtc_state->port_clock = 0; 5149 crtc_state->pixel_multiplier = 1; 5150 5151 /* Fill in default crtc timings, allow encoders to overwrite them. */ 5152 drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode, 5153 CRTC_STEREO_DOUBLE); 5154 5155 /* Pass our mode to the connectors and the CRTC to give them a chance to 5156 * adjust it according to limitations or connector properties, and also 5157 * a chance to reject the mode entirely. 5158 */ 5159 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5160 struct intel_encoder *encoder = 5161 to_intel_encoder(connector_state->best_encoder); 5162 5163 if (connector_state->crtc != &crtc->base) 5164 continue; 5165 5166 ret = encoder->compute_config(encoder, crtc_state, 5167 connector_state); 5168 if (ret == -EDEADLK) 5169 return ret; 5170 if (ret < 0) { 5171 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n", 5172 encoder->base.base.id, encoder->base.name, ret); 5173 return ret; 5174 } 5175 } 5176 5177 /* Set default port clock if not overwritten by the encoder. Needs to be 5178 * done afterwards in case the encoder adjusts the mode. */ 5179 if (!crtc_state->port_clock) 5180 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock 5181 * crtc_state->pixel_multiplier; 5182 5183 ret = intel_crtc_compute_config(state, crtc); 5184 if (ret == -EDEADLK) 5185 return ret; 5186 if (ret == -EAGAIN) { 5187 if (drm_WARN(&i915->drm, !retry, 5188 "[CRTC:%d:%s] loop in pipe configuration computation\n", 5189 crtc->base.base.id, crtc->base.name)) 5190 return -EINVAL; 5191 5192 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] bw constrained, retrying\n", 5193 crtc->base.base.id, crtc->base.name); 5194 retry = false; 5195 goto encoder_retry; 5196 } 5197 if (ret < 0) { 5198 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n", 5199 crtc->base.base.id, crtc->base.name, ret); 5200 return ret; 5201 } 5202 5203 /* Dithering seems to not pass-through bits correctly when it should, so 5204 * only enable it on 6bpc panels and when its not a compliance 5205 * test requesting 6bpc video pattern. 5206 */ 5207 crtc_state->dither = (crtc_state->pipe_bpp == 6*3) && 5208 !crtc_state->dither_force_disable; 5209 drm_dbg_kms(&i915->drm, 5210 "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n", 5211 crtc->base.base.id, crtc->base.name, 5212 base_bpp, crtc_state->pipe_bpp, crtc_state->dither); 5213 5214 return 0; 5215 } 5216 5217 static int 5218 intel_modeset_pipe_config_late(struct intel_atomic_state *state, 5219 struct intel_crtc *crtc) 5220 { 5221 struct intel_crtc_state *crtc_state = 5222 intel_atomic_get_new_crtc_state(state, crtc); 5223 struct drm_connector_state *conn_state; 5224 struct drm_connector *connector; 5225 int i; 5226 5227 intel_bigjoiner_adjust_pipe_src(crtc_state); 5228 5229 for_each_new_connector_in_state(&state->base, connector, 5230 conn_state, i) { 5231 struct intel_encoder *encoder = 5232 to_intel_encoder(conn_state->best_encoder); 5233 int ret; 5234 5235 if (conn_state->crtc != &crtc->base || 5236 !encoder->compute_config_late) 5237 continue; 5238 5239 ret = encoder->compute_config_late(encoder, crtc_state, 5240 conn_state); 5241 if (ret) 5242 return ret; 5243 } 5244 5245 return 0; 5246 } 5247 5248 bool intel_fuzzy_clock_check(int clock1, int clock2) 5249 { 5250 int diff; 5251 5252 if (clock1 == clock2) 5253 return true; 5254 5255 if (!clock1 || !clock2) 5256 return false; 5257 5258 diff = abs(clock1 - clock2); 5259 5260 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) 5261 return true; 5262 5263 return false; 5264 } 5265 5266 static bool 5267 intel_compare_link_m_n(const struct intel_link_m_n *m_n, 5268 const struct intel_link_m_n *m2_n2) 5269 { 5270 return m_n->tu == m2_n2->tu && 5271 m_n->data_m == m2_n2->data_m && 5272 m_n->data_n == m2_n2->data_n && 5273 m_n->link_m == m2_n2->link_m && 5274 m_n->link_n == m2_n2->link_n; 5275 } 5276 5277 static bool 5278 intel_compare_infoframe(const union hdmi_infoframe *a, 5279 const union hdmi_infoframe *b) 5280 { 5281 return memcmp(a, b, sizeof(*a)) == 0; 5282 } 5283 5284 static bool 5285 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a, 5286 const struct drm_dp_vsc_sdp *b) 5287 { 5288 return memcmp(a, b, sizeof(*a)) == 0; 5289 } 5290 5291 static bool 5292 intel_compare_buffer(const u8 *a, const u8 *b, size_t len) 5293 { 5294 return memcmp(a, b, len) == 0; 5295 } 5296 5297 static void 5298 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv, 5299 bool fastset, const char *name, 5300 const union hdmi_infoframe *a, 5301 const union hdmi_infoframe *b) 5302 { 5303 if (fastset) { 5304 if (!drm_debug_enabled(DRM_UT_KMS)) 5305 return; 5306 5307 drm_dbg_kms(&dev_priv->drm, 5308 "fastset mismatch in %s infoframe\n", name); 5309 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 5310 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a); 5311 drm_dbg_kms(&dev_priv->drm, "found:\n"); 5312 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b); 5313 } else { 5314 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name); 5315 drm_err(&dev_priv->drm, "expected:\n"); 5316 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a); 5317 drm_err(&dev_priv->drm, "found:\n"); 5318 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b); 5319 } 5320 } 5321 5322 static void 5323 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv, 5324 bool fastset, const char *name, 5325 const struct drm_dp_vsc_sdp *a, 5326 const struct drm_dp_vsc_sdp *b) 5327 { 5328 if (fastset) { 5329 if (!drm_debug_enabled(DRM_UT_KMS)) 5330 return; 5331 5332 drm_dbg_kms(&dev_priv->drm, 5333 "fastset mismatch in %s dp sdp\n", name); 5334 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 5335 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a); 5336 drm_dbg_kms(&dev_priv->drm, "found:\n"); 5337 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b); 5338 } else { 5339 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name); 5340 drm_err(&dev_priv->drm, "expected:\n"); 5341 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a); 5342 drm_err(&dev_priv->drm, "found:\n"); 5343 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b); 5344 } 5345 } 5346 5347 /* Returns the length up to and including the last differing byte */ 5348 static size_t 5349 memcmp_diff_len(const u8 *a, const u8 *b, size_t len) 5350 { 5351 int i; 5352 5353 for (i = len - 1; i >= 0; i--) { 5354 if (a[i] != b[i]) 5355 return i + 1; 5356 } 5357 5358 return 0; 5359 } 5360 5361 static void 5362 pipe_config_buffer_mismatch(struct drm_i915_private *dev_priv, 5363 bool fastset, const char *name, 5364 const u8 *a, const u8 *b, size_t len) 5365 { 5366 if (fastset) { 5367 if (!drm_debug_enabled(DRM_UT_KMS)) 5368 return; 5369 5370 /* only dump up to the last difference */ 5371 len = memcmp_diff_len(a, b, len); 5372 5373 drm_dbg_kms(&dev_priv->drm, 5374 "fastset mismatch in %s buffer\n", name); 5375 print_hex_dump(KERN_DEBUG, "expected: ", DUMP_PREFIX_NONE, 5376 16, 0, a, len, false); 5377 print_hex_dump(KERN_DEBUG, "found: ", DUMP_PREFIX_NONE, 5378 16, 0, b, len, false); 5379 } else { 5380 /* only dump up to the last difference */ 5381 len = memcmp_diff_len(a, b, len); 5382 5383 drm_err(&dev_priv->drm, "mismatch in %s buffer\n", name); 5384 print_hex_dump(KERN_ERR, "expected: ", DUMP_PREFIX_NONE, 5385 16, 0, a, len, false); 5386 print_hex_dump(KERN_ERR, "found: ", DUMP_PREFIX_NONE, 5387 16, 0, b, len, false); 5388 } 5389 } 5390 5391 static void __printf(4, 5) 5392 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc, 5393 const char *name, const char *format, ...) 5394 { 5395 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 5396 struct va_format vaf; 5397 va_list args; 5398 5399 va_start(args, format); 5400 vaf.fmt = format; 5401 vaf.va = &args; 5402 5403 if (fastset) 5404 drm_dbg_kms(&i915->drm, 5405 "[CRTC:%d:%s] fastset mismatch in %s %pV\n", 5406 crtc->base.base.id, crtc->base.name, name, &vaf); 5407 else 5408 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n", 5409 crtc->base.base.id, crtc->base.name, name, &vaf); 5410 5411 va_end(args); 5412 } 5413 5414 static bool fastboot_enabled(struct drm_i915_private *dev_priv) 5415 { 5416 if (dev_priv->params.fastboot != -1) 5417 return dev_priv->params.fastboot; 5418 5419 /* Enable fastboot by default on Skylake and newer */ 5420 if (DISPLAY_VER(dev_priv) >= 9) 5421 return true; 5422 5423 /* Enable fastboot by default on VLV and CHV */ 5424 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5425 return true; 5426 5427 /* Disabled by default on all others */ 5428 return false; 5429 } 5430 5431 bool 5432 intel_pipe_config_compare(const struct intel_crtc_state *current_config, 5433 const struct intel_crtc_state *pipe_config, 5434 bool fastset) 5435 { 5436 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev); 5437 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 5438 bool ret = true; 5439 bool fixup_inherited = fastset && 5440 current_config->inherited && !pipe_config->inherited; 5441 5442 if (fixup_inherited && !fastboot_enabled(dev_priv)) { 5443 drm_dbg_kms(&dev_priv->drm, 5444 "initial modeset and fastboot not set\n"); 5445 ret = false; 5446 } 5447 5448 #define PIPE_CONF_CHECK_X(name) do { \ 5449 if (current_config->name != pipe_config->name) { \ 5450 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5451 "(expected 0x%08x, found 0x%08x)", \ 5452 current_config->name, \ 5453 pipe_config->name); \ 5454 ret = false; \ 5455 } \ 5456 } while (0) 5457 5458 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \ 5459 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \ 5460 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5461 "(expected 0x%08x, found 0x%08x)", \ 5462 current_config->name & (mask), \ 5463 pipe_config->name & (mask)); \ 5464 ret = false; \ 5465 } \ 5466 } while (0) 5467 5468 #define PIPE_CONF_CHECK_I(name) do { \ 5469 if (current_config->name != pipe_config->name) { \ 5470 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5471 "(expected %i, found %i)", \ 5472 current_config->name, \ 5473 pipe_config->name); \ 5474 ret = false; \ 5475 } \ 5476 } while (0) 5477 5478 #define PIPE_CONF_CHECK_BOOL(name) do { \ 5479 if (current_config->name != pipe_config->name) { \ 5480 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5481 "(expected %s, found %s)", \ 5482 str_yes_no(current_config->name), \ 5483 str_yes_no(pipe_config->name)); \ 5484 ret = false; \ 5485 } \ 5486 } while (0) 5487 5488 /* 5489 * Checks state where we only read out the enabling, but not the entire 5490 * state itself (like full infoframes or ELD for audio). These states 5491 * require a full modeset on bootup to fix up. 5492 */ 5493 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \ 5494 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \ 5495 PIPE_CONF_CHECK_BOOL(name); \ 5496 } else { \ 5497 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5498 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \ 5499 str_yes_no(current_config->name), \ 5500 str_yes_no(pipe_config->name)); \ 5501 ret = false; \ 5502 } \ 5503 } while (0) 5504 5505 #define PIPE_CONF_CHECK_P(name) do { \ 5506 if (current_config->name != pipe_config->name) { \ 5507 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5508 "(expected %p, found %p)", \ 5509 current_config->name, \ 5510 pipe_config->name); \ 5511 ret = false; \ 5512 } \ 5513 } while (0) 5514 5515 #define PIPE_CONF_CHECK_M_N(name) do { \ 5516 if (!intel_compare_link_m_n(¤t_config->name, \ 5517 &pipe_config->name)) { \ 5518 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5519 "(expected tu %i data %i/%i link %i/%i, " \ 5520 "found tu %i, data %i/%i link %i/%i)", \ 5521 current_config->name.tu, \ 5522 current_config->name.data_m, \ 5523 current_config->name.data_n, \ 5524 current_config->name.link_m, \ 5525 current_config->name.link_n, \ 5526 pipe_config->name.tu, \ 5527 pipe_config->name.data_m, \ 5528 pipe_config->name.data_n, \ 5529 pipe_config->name.link_m, \ 5530 pipe_config->name.link_n); \ 5531 ret = false; \ 5532 } \ 5533 } while (0) 5534 5535 #define PIPE_CONF_CHECK_TIMINGS(name) do { \ 5536 PIPE_CONF_CHECK_I(name.crtc_hdisplay); \ 5537 PIPE_CONF_CHECK_I(name.crtc_htotal); \ 5538 PIPE_CONF_CHECK_I(name.crtc_hblank_start); \ 5539 PIPE_CONF_CHECK_I(name.crtc_hblank_end); \ 5540 PIPE_CONF_CHECK_I(name.crtc_hsync_start); \ 5541 PIPE_CONF_CHECK_I(name.crtc_hsync_end); \ 5542 PIPE_CONF_CHECK_I(name.crtc_vdisplay); \ 5543 PIPE_CONF_CHECK_I(name.crtc_vtotal); \ 5544 PIPE_CONF_CHECK_I(name.crtc_vblank_start); \ 5545 PIPE_CONF_CHECK_I(name.crtc_vblank_end); \ 5546 PIPE_CONF_CHECK_I(name.crtc_vsync_start); \ 5547 PIPE_CONF_CHECK_I(name.crtc_vsync_end); \ 5548 } while (0) 5549 5550 #define PIPE_CONF_CHECK_RECT(name) do { \ 5551 PIPE_CONF_CHECK_I(name.x1); \ 5552 PIPE_CONF_CHECK_I(name.x2); \ 5553 PIPE_CONF_CHECK_I(name.y1); \ 5554 PIPE_CONF_CHECK_I(name.y2); \ 5555 } while (0) 5556 5557 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \ 5558 if ((current_config->name ^ pipe_config->name) & (mask)) { \ 5559 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5560 "(%x) (expected %i, found %i)", \ 5561 (mask), \ 5562 current_config->name & (mask), \ 5563 pipe_config->name & (mask)); \ 5564 ret = false; \ 5565 } \ 5566 } while (0) 5567 5568 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \ 5569 if (!intel_compare_infoframe(¤t_config->infoframes.name, \ 5570 &pipe_config->infoframes.name)) { \ 5571 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \ 5572 ¤t_config->infoframes.name, \ 5573 &pipe_config->infoframes.name); \ 5574 ret = false; \ 5575 } \ 5576 } while (0) 5577 5578 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \ 5579 if (!current_config->has_psr && !pipe_config->has_psr && \ 5580 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \ 5581 &pipe_config->infoframes.name)) { \ 5582 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \ 5583 ¤t_config->infoframes.name, \ 5584 &pipe_config->infoframes.name); \ 5585 ret = false; \ 5586 } \ 5587 } while (0) 5588 5589 #define PIPE_CONF_CHECK_BUFFER(name, len) do { \ 5590 BUILD_BUG_ON(sizeof(current_config->name) != (len)); \ 5591 BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \ 5592 if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \ 5593 pipe_config_buffer_mismatch(dev_priv, fastset, __stringify(name), \ 5594 current_config->name, \ 5595 pipe_config->name, \ 5596 (len)); \ 5597 ret = false; \ 5598 } \ 5599 } while (0) 5600 5601 #define PIPE_CONF_CHECK_COLOR_LUT(lut, is_pre_csc_lut) do { \ 5602 if (current_config->gamma_mode == pipe_config->gamma_mode && \ 5603 !intel_color_lut_equal(current_config, \ 5604 current_config->lut, pipe_config->lut, \ 5605 is_pre_csc_lut)) { \ 5606 pipe_config_mismatch(fastset, crtc, __stringify(lut), \ 5607 "hw_state doesn't match sw_state"); \ 5608 ret = false; \ 5609 } \ 5610 } while (0) 5611 5612 #define PIPE_CONF_QUIRK(quirk) \ 5613 ((current_config->quirks | pipe_config->quirks) & (quirk)) 5614 5615 PIPE_CONF_CHECK_I(hw.enable); 5616 PIPE_CONF_CHECK_I(hw.active); 5617 5618 PIPE_CONF_CHECK_I(cpu_transcoder); 5619 PIPE_CONF_CHECK_I(mst_master_transcoder); 5620 5621 PIPE_CONF_CHECK_BOOL(has_pch_encoder); 5622 PIPE_CONF_CHECK_I(fdi_lanes); 5623 PIPE_CONF_CHECK_M_N(fdi_m_n); 5624 5625 PIPE_CONF_CHECK_I(lane_count); 5626 PIPE_CONF_CHECK_X(lane_lat_optim_mask); 5627 5628 if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) { 5629 if (!fastset || !pipe_config->seamless_m_n) 5630 PIPE_CONF_CHECK_M_N(dp_m_n); 5631 } else { 5632 PIPE_CONF_CHECK_M_N(dp_m_n); 5633 PIPE_CONF_CHECK_M_N(dp_m2_n2); 5634 } 5635 5636 PIPE_CONF_CHECK_X(output_types); 5637 5638 PIPE_CONF_CHECK_I(framestart_delay); 5639 PIPE_CONF_CHECK_I(msa_timing_delay); 5640 5641 PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode); 5642 PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode); 5643 5644 PIPE_CONF_CHECK_I(pixel_multiplier); 5645 5646 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5647 DRM_MODE_FLAG_INTERLACE); 5648 5649 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { 5650 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5651 DRM_MODE_FLAG_PHSYNC); 5652 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5653 DRM_MODE_FLAG_NHSYNC); 5654 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5655 DRM_MODE_FLAG_PVSYNC); 5656 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5657 DRM_MODE_FLAG_NVSYNC); 5658 } 5659 5660 PIPE_CONF_CHECK_I(output_format); 5661 PIPE_CONF_CHECK_BOOL(has_hdmi_sink); 5662 if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || 5663 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5664 PIPE_CONF_CHECK_BOOL(limited_color_range); 5665 5666 PIPE_CONF_CHECK_BOOL(hdmi_scrambling); 5667 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio); 5668 PIPE_CONF_CHECK_BOOL(has_infoframe); 5669 PIPE_CONF_CHECK_BOOL(fec_enable); 5670 5671 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio); 5672 PIPE_CONF_CHECK_BUFFER(eld, MAX_ELD_BYTES); 5673 5674 PIPE_CONF_CHECK_X(gmch_pfit.control); 5675 /* pfit ratios are autocomputed by the hw on gen4+ */ 5676 if (DISPLAY_VER(dev_priv) < 4) 5677 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); 5678 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); 5679 5680 /* 5681 * Changing the EDP transcoder input mux 5682 * (A_ONOFF vs. A_ON) requires a full modeset. 5683 */ 5684 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru); 5685 5686 if (!fastset) { 5687 PIPE_CONF_CHECK_RECT(pipe_src); 5688 5689 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled); 5690 PIPE_CONF_CHECK_RECT(pch_pfit.dst); 5691 5692 PIPE_CONF_CHECK_I(scaler_state.scaler_id); 5693 PIPE_CONF_CHECK_I(pixel_rate); 5694 5695 PIPE_CONF_CHECK_X(gamma_mode); 5696 if (IS_CHERRYVIEW(dev_priv)) 5697 PIPE_CONF_CHECK_X(cgm_mode); 5698 else 5699 PIPE_CONF_CHECK_X(csc_mode); 5700 PIPE_CONF_CHECK_BOOL(gamma_enable); 5701 PIPE_CONF_CHECK_BOOL(csc_enable); 5702 5703 PIPE_CONF_CHECK_I(linetime); 5704 PIPE_CONF_CHECK_I(ips_linetime); 5705 5706 PIPE_CONF_CHECK_COLOR_LUT(pre_csc_lut, true); 5707 PIPE_CONF_CHECK_COLOR_LUT(post_csc_lut, false); 5708 5709 if (current_config->active_planes) { 5710 PIPE_CONF_CHECK_BOOL(has_psr); 5711 PIPE_CONF_CHECK_BOOL(has_psr2); 5712 PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); 5713 PIPE_CONF_CHECK_I(dc3co_exitline); 5714 } 5715 } 5716 5717 PIPE_CONF_CHECK_BOOL(double_wide); 5718 5719 if (dev_priv->display.dpll.mgr) { 5720 PIPE_CONF_CHECK_P(shared_dpll); 5721 5722 PIPE_CONF_CHECK_X(dpll_hw_state.dpll); 5723 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); 5724 PIPE_CONF_CHECK_X(dpll_hw_state.fp0); 5725 PIPE_CONF_CHECK_X(dpll_hw_state.fp1); 5726 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); 5727 PIPE_CONF_CHECK_X(dpll_hw_state.spll); 5728 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); 5729 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); 5730 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); 5731 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); 5732 PIPE_CONF_CHECK_X(dpll_hw_state.div0); 5733 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); 5734 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); 5735 PIPE_CONF_CHECK_X(dpll_hw_state.pll0); 5736 PIPE_CONF_CHECK_X(dpll_hw_state.pll1); 5737 PIPE_CONF_CHECK_X(dpll_hw_state.pll2); 5738 PIPE_CONF_CHECK_X(dpll_hw_state.pll3); 5739 PIPE_CONF_CHECK_X(dpll_hw_state.pll6); 5740 PIPE_CONF_CHECK_X(dpll_hw_state.pll8); 5741 PIPE_CONF_CHECK_X(dpll_hw_state.pll9); 5742 PIPE_CONF_CHECK_X(dpll_hw_state.pll10); 5743 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); 5744 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl); 5745 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1); 5746 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl); 5747 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0); 5748 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1); 5749 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf); 5750 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock); 5751 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc); 5752 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias); 5753 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias); 5754 } 5755 5756 PIPE_CONF_CHECK_X(dsi_pll.ctrl); 5757 PIPE_CONF_CHECK_X(dsi_pll.div); 5758 5759 if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5) 5760 PIPE_CONF_CHECK_I(pipe_bpp); 5761 5762 if (!fastset || !pipe_config->seamless_m_n) { 5763 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock); 5764 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock); 5765 } 5766 PIPE_CONF_CHECK_I(port_clock); 5767 5768 PIPE_CONF_CHECK_I(min_voltage_level); 5769 5770 if (current_config->has_psr || pipe_config->has_psr) 5771 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable, 5772 ~intel_hdmi_infoframe_enable(DP_SDP_VSC)); 5773 else 5774 PIPE_CONF_CHECK_X(infoframes.enable); 5775 5776 PIPE_CONF_CHECK_X(infoframes.gcp); 5777 PIPE_CONF_CHECK_INFOFRAME(avi); 5778 PIPE_CONF_CHECK_INFOFRAME(spd); 5779 PIPE_CONF_CHECK_INFOFRAME(hdmi); 5780 PIPE_CONF_CHECK_INFOFRAME(drm); 5781 PIPE_CONF_CHECK_DP_VSC_SDP(vsc); 5782 5783 PIPE_CONF_CHECK_X(sync_mode_slaves_mask); 5784 PIPE_CONF_CHECK_I(master_transcoder); 5785 PIPE_CONF_CHECK_X(bigjoiner_pipes); 5786 5787 PIPE_CONF_CHECK_I(dsc.compression_enable); 5788 PIPE_CONF_CHECK_I(dsc.dsc_split); 5789 PIPE_CONF_CHECK_I(dsc.compressed_bpp); 5790 5791 PIPE_CONF_CHECK_BOOL(splitter.enable); 5792 PIPE_CONF_CHECK_I(splitter.link_count); 5793 PIPE_CONF_CHECK_I(splitter.pixel_overlap); 5794 5795 PIPE_CONF_CHECK_BOOL(vrr.enable); 5796 PIPE_CONF_CHECK_I(vrr.vmin); 5797 PIPE_CONF_CHECK_I(vrr.vmax); 5798 PIPE_CONF_CHECK_I(vrr.flipline); 5799 PIPE_CONF_CHECK_I(vrr.pipeline_full); 5800 PIPE_CONF_CHECK_I(vrr.guardband); 5801 5802 #undef PIPE_CONF_CHECK_X 5803 #undef PIPE_CONF_CHECK_I 5804 #undef PIPE_CONF_CHECK_BOOL 5805 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE 5806 #undef PIPE_CONF_CHECK_P 5807 #undef PIPE_CONF_CHECK_FLAGS 5808 #undef PIPE_CONF_CHECK_COLOR_LUT 5809 #undef PIPE_CONF_CHECK_TIMINGS 5810 #undef PIPE_CONF_CHECK_RECT 5811 #undef PIPE_CONF_QUIRK 5812 5813 return ret; 5814 } 5815 5816 static void 5817 intel_verify_planes(struct intel_atomic_state *state) 5818 { 5819 struct intel_plane *plane; 5820 const struct intel_plane_state *plane_state; 5821 int i; 5822 5823 for_each_new_intel_plane_in_state(state, plane, 5824 plane_state, i) 5825 assert_plane(plane, plane_state->planar_slave || 5826 plane_state->uapi.visible); 5827 } 5828 5829 int intel_modeset_all_pipes(struct intel_atomic_state *state, 5830 const char *reason) 5831 { 5832 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 5833 struct intel_crtc *crtc; 5834 5835 /* 5836 * Add all pipes to the state, and force 5837 * a modeset on all the active ones. 5838 */ 5839 for_each_intel_crtc(&dev_priv->drm, crtc) { 5840 struct intel_crtc_state *crtc_state; 5841 int ret; 5842 5843 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 5844 if (IS_ERR(crtc_state)) 5845 return PTR_ERR(crtc_state); 5846 5847 if (!crtc_state->hw.active || 5848 intel_crtc_needs_modeset(crtc_state)) 5849 continue; 5850 5851 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] Full modeset due to %s\n", 5852 crtc->base.base.id, crtc->base.name, reason); 5853 5854 crtc_state->uapi.mode_changed = true; 5855 crtc_state->update_pipe = false; 5856 5857 ret = drm_atomic_add_affected_connectors(&state->base, 5858 &crtc->base); 5859 if (ret) 5860 return ret; 5861 5862 ret = intel_atomic_add_affected_planes(state, crtc); 5863 if (ret) 5864 return ret; 5865 5866 crtc_state->update_planes |= crtc_state->active_planes; 5867 crtc_state->async_flip_planes = 0; 5868 crtc_state->do_async_flip = false; 5869 } 5870 5871 return 0; 5872 } 5873 5874 void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state) 5875 { 5876 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 5877 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5878 struct drm_display_mode adjusted_mode; 5879 5880 drm_mode_init(&adjusted_mode, &crtc_state->hw.adjusted_mode); 5881 5882 if (crtc_state->vrr.enable) { 5883 adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax; 5884 adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax; 5885 adjusted_mode.crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state); 5886 crtc->vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state); 5887 } 5888 5889 drm_calc_timestamping_constants(&crtc->base, &adjusted_mode); 5890 5891 crtc->mode_flags = crtc_state->mode_flags; 5892 5893 /* 5894 * The scanline counter increments at the leading edge of hsync. 5895 * 5896 * On most platforms it starts counting from vtotal-1 on the 5897 * first active line. That means the scanline counter value is 5898 * always one less than what we would expect. Ie. just after 5899 * start of vblank, which also occurs at start of hsync (on the 5900 * last active line), the scanline counter will read vblank_start-1. 5901 * 5902 * On gen2 the scanline counter starts counting from 1 instead 5903 * of vtotal-1, so we have to subtract one (or rather add vtotal-1 5904 * to keep the value positive), instead of adding one. 5905 * 5906 * On HSW+ the behaviour of the scanline counter depends on the output 5907 * type. For DP ports it behaves like most other platforms, but on HDMI 5908 * there's an extra 1 line difference. So we need to add two instead of 5909 * one to the value. 5910 * 5911 * On VLV/CHV DSI the scanline counter would appear to increment 5912 * approx. 1/3 of a scanline before start of vblank. Unfortunately 5913 * that means we can't tell whether we're in vblank or not while 5914 * we're on that particular line. We must still set scanline_offset 5915 * to 1 so that the vblank timestamps come out correct when we query 5916 * the scanline counter from within the vblank interrupt handler. 5917 * However if queried just before the start of vblank we'll get an 5918 * answer that's slightly in the future. 5919 */ 5920 if (DISPLAY_VER(dev_priv) == 2) { 5921 int vtotal; 5922 5923 vtotal = adjusted_mode.crtc_vtotal; 5924 if (adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 5925 vtotal /= 2; 5926 5927 crtc->scanline_offset = vtotal - 1; 5928 } else if (HAS_DDI(dev_priv) && 5929 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 5930 crtc->scanline_offset = 2; 5931 } else { 5932 crtc->scanline_offset = 1; 5933 } 5934 } 5935 5936 /* 5937 * This implements the workaround described in the "notes" section of the mode 5938 * set sequence documentation. When going from no pipes or single pipe to 5939 * multiple pipes, and planes are enabled after the pipe, we need to wait at 5940 * least 2 vblanks on the first pipe before enabling planes on the second pipe. 5941 */ 5942 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state) 5943 { 5944 struct intel_crtc_state *crtc_state; 5945 struct intel_crtc *crtc; 5946 struct intel_crtc_state *first_crtc_state = NULL; 5947 struct intel_crtc_state *other_crtc_state = NULL; 5948 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; 5949 int i; 5950 5951 /* look at all crtc's that are going to be enabled in during modeset */ 5952 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5953 if (!crtc_state->hw.active || 5954 !intel_crtc_needs_modeset(crtc_state)) 5955 continue; 5956 5957 if (first_crtc_state) { 5958 other_crtc_state = crtc_state; 5959 break; 5960 } else { 5961 first_crtc_state = crtc_state; 5962 first_pipe = crtc->pipe; 5963 } 5964 } 5965 5966 /* No workaround needed? */ 5967 if (!first_crtc_state) 5968 return 0; 5969 5970 /* w/a possibly needed, check how many crtc's are already enabled. */ 5971 for_each_intel_crtc(state->base.dev, crtc) { 5972 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 5973 if (IS_ERR(crtc_state)) 5974 return PTR_ERR(crtc_state); 5975 5976 crtc_state->hsw_workaround_pipe = INVALID_PIPE; 5977 5978 if (!crtc_state->hw.active || 5979 intel_crtc_needs_modeset(crtc_state)) 5980 continue; 5981 5982 /* 2 or more enabled crtcs means no need for w/a */ 5983 if (enabled_pipe != INVALID_PIPE) 5984 return 0; 5985 5986 enabled_pipe = crtc->pipe; 5987 } 5988 5989 if (enabled_pipe != INVALID_PIPE) 5990 first_crtc_state->hsw_workaround_pipe = enabled_pipe; 5991 else if (other_crtc_state) 5992 other_crtc_state->hsw_workaround_pipe = first_pipe; 5993 5994 return 0; 5995 } 5996 5997 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 5998 u8 active_pipes) 5999 { 6000 const struct intel_crtc_state *crtc_state; 6001 struct intel_crtc *crtc; 6002 int i; 6003 6004 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6005 if (crtc_state->hw.active) 6006 active_pipes |= BIT(crtc->pipe); 6007 else 6008 active_pipes &= ~BIT(crtc->pipe); 6009 } 6010 6011 return active_pipes; 6012 } 6013 6014 static int intel_modeset_checks(struct intel_atomic_state *state) 6015 { 6016 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6017 6018 state->modeset = true; 6019 6020 if (IS_HASWELL(dev_priv)) 6021 return hsw_mode_set_planes_workaround(state); 6022 6023 return 0; 6024 } 6025 6026 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state, 6027 struct intel_crtc_state *new_crtc_state) 6028 { 6029 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) 6030 return; 6031 6032 new_crtc_state->uapi.mode_changed = false; 6033 if (!intel_crtc_needs_modeset(new_crtc_state)) 6034 new_crtc_state->update_pipe = true; 6035 } 6036 6037 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state, 6038 struct intel_crtc *crtc, 6039 u8 plane_ids_mask) 6040 { 6041 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6042 struct intel_plane *plane; 6043 6044 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 6045 struct intel_plane_state *plane_state; 6046 6047 if ((plane_ids_mask & BIT(plane->id)) == 0) 6048 continue; 6049 6050 plane_state = intel_atomic_get_plane_state(state, plane); 6051 if (IS_ERR(plane_state)) 6052 return PTR_ERR(plane_state); 6053 } 6054 6055 return 0; 6056 } 6057 6058 int intel_atomic_add_affected_planes(struct intel_atomic_state *state, 6059 struct intel_crtc *crtc) 6060 { 6061 const struct intel_crtc_state *old_crtc_state = 6062 intel_atomic_get_old_crtc_state(state, crtc); 6063 const struct intel_crtc_state *new_crtc_state = 6064 intel_atomic_get_new_crtc_state(state, crtc); 6065 6066 return intel_crtc_add_planes_to_state(state, crtc, 6067 old_crtc_state->enabled_planes | 6068 new_crtc_state->enabled_planes); 6069 } 6070 6071 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv) 6072 { 6073 /* See {hsw,vlv,ivb}_plane_ratio() */ 6074 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) || 6075 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) || 6076 IS_IVYBRIDGE(dev_priv); 6077 } 6078 6079 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state, 6080 struct intel_crtc *crtc, 6081 struct intel_crtc *other) 6082 { 6083 const struct intel_plane_state *plane_state; 6084 struct intel_plane *plane; 6085 u8 plane_ids = 0; 6086 int i; 6087 6088 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 6089 if (plane->pipe == crtc->pipe) 6090 plane_ids |= BIT(plane->id); 6091 } 6092 6093 return intel_crtc_add_planes_to_state(state, other, plane_ids); 6094 } 6095 6096 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state) 6097 { 6098 struct drm_i915_private *i915 = to_i915(state->base.dev); 6099 const struct intel_crtc_state *crtc_state; 6100 struct intel_crtc *crtc; 6101 int i; 6102 6103 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6104 struct intel_crtc *other; 6105 6106 for_each_intel_crtc_in_pipe_mask(&i915->drm, other, 6107 crtc_state->bigjoiner_pipes) { 6108 int ret; 6109 6110 if (crtc == other) 6111 continue; 6112 6113 ret = intel_crtc_add_bigjoiner_planes(state, crtc, other); 6114 if (ret) 6115 return ret; 6116 } 6117 } 6118 6119 return 0; 6120 } 6121 6122 static int intel_atomic_check_planes(struct intel_atomic_state *state) 6123 { 6124 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6125 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6126 struct intel_plane_state *plane_state; 6127 struct intel_plane *plane; 6128 struct intel_crtc *crtc; 6129 int i, ret; 6130 6131 ret = icl_add_linked_planes(state); 6132 if (ret) 6133 return ret; 6134 6135 ret = intel_bigjoiner_add_affected_planes(state); 6136 if (ret) 6137 return ret; 6138 6139 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 6140 ret = intel_plane_atomic_check(state, plane); 6141 if (ret) { 6142 drm_dbg_atomic(&dev_priv->drm, 6143 "[PLANE:%d:%s] atomic driver check failed\n", 6144 plane->base.base.id, plane->base.name); 6145 return ret; 6146 } 6147 } 6148 6149 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6150 new_crtc_state, i) { 6151 u8 old_active_planes, new_active_planes; 6152 6153 ret = icl_check_nv12_planes(new_crtc_state); 6154 if (ret) 6155 return ret; 6156 6157 /* 6158 * On some platforms the number of active planes affects 6159 * the planes' minimum cdclk calculation. Add such planes 6160 * to the state before we compute the minimum cdclk. 6161 */ 6162 if (!active_planes_affects_min_cdclk(dev_priv)) 6163 continue; 6164 6165 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 6166 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 6167 6168 if (hweight8(old_active_planes) == hweight8(new_active_planes)) 6169 continue; 6170 6171 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes); 6172 if (ret) 6173 return ret; 6174 } 6175 6176 return 0; 6177 } 6178 6179 static int intel_atomic_check_crtcs(struct intel_atomic_state *state) 6180 { 6181 struct intel_crtc_state *crtc_state; 6182 struct intel_crtc *crtc; 6183 int i; 6184 6185 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6186 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 6187 int ret; 6188 6189 ret = intel_crtc_atomic_check(state, crtc); 6190 if (ret) { 6191 drm_dbg_atomic(&i915->drm, 6192 "[CRTC:%d:%s] atomic driver check failed\n", 6193 crtc->base.base.id, crtc->base.name); 6194 return ret; 6195 } 6196 } 6197 6198 return 0; 6199 } 6200 6201 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, 6202 u8 transcoders) 6203 { 6204 const struct intel_crtc_state *new_crtc_state; 6205 struct intel_crtc *crtc; 6206 int i; 6207 6208 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6209 if (new_crtc_state->hw.enable && 6210 transcoders & BIT(new_crtc_state->cpu_transcoder) && 6211 intel_crtc_needs_modeset(new_crtc_state)) 6212 return true; 6213 } 6214 6215 return false; 6216 } 6217 6218 static bool intel_pipes_need_modeset(struct intel_atomic_state *state, 6219 u8 pipes) 6220 { 6221 const struct intel_crtc_state *new_crtc_state; 6222 struct intel_crtc *crtc; 6223 int i; 6224 6225 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6226 if (new_crtc_state->hw.enable && 6227 pipes & BIT(crtc->pipe) && 6228 intel_crtc_needs_modeset(new_crtc_state)) 6229 return true; 6230 } 6231 6232 return false; 6233 } 6234 6235 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state, 6236 struct intel_crtc *master_crtc) 6237 { 6238 struct drm_i915_private *i915 = to_i915(state->base.dev); 6239 struct intel_crtc_state *master_crtc_state = 6240 intel_atomic_get_new_crtc_state(state, master_crtc); 6241 struct intel_crtc *slave_crtc; 6242 6243 if (!master_crtc_state->bigjoiner_pipes) 6244 return 0; 6245 6246 /* sanity check */ 6247 if (drm_WARN_ON(&i915->drm, 6248 master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state))) 6249 return -EINVAL; 6250 6251 if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) { 6252 drm_dbg_kms(&i915->drm, 6253 "[CRTC:%d:%s] Cannot act as big joiner master " 6254 "(need 0x%x as pipes, only 0x%x possible)\n", 6255 master_crtc->base.base.id, master_crtc->base.name, 6256 master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915)); 6257 return -EINVAL; 6258 } 6259 6260 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 6261 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 6262 struct intel_crtc_state *slave_crtc_state; 6263 int ret; 6264 6265 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc); 6266 if (IS_ERR(slave_crtc_state)) 6267 return PTR_ERR(slave_crtc_state); 6268 6269 /* master being enabled, slave was already configured? */ 6270 if (slave_crtc_state->uapi.enable) { 6271 drm_dbg_kms(&i915->drm, 6272 "[CRTC:%d:%s] Slave is enabled as normal CRTC, but " 6273 "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n", 6274 slave_crtc->base.base.id, slave_crtc->base.name, 6275 master_crtc->base.base.id, master_crtc->base.name); 6276 return -EINVAL; 6277 } 6278 6279 /* 6280 * The state copy logic assumes the master crtc gets processed 6281 * before the slave crtc during the main compute_config loop. 6282 * This works because the crtcs are created in pipe order, 6283 * and the hardware requires master pipe < slave pipe as well. 6284 * Should that change we need to rethink the logic. 6285 */ 6286 if (WARN_ON(drm_crtc_index(&master_crtc->base) > 6287 drm_crtc_index(&slave_crtc->base))) 6288 return -EINVAL; 6289 6290 drm_dbg_kms(&i915->drm, 6291 "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n", 6292 slave_crtc->base.base.id, slave_crtc->base.name, 6293 master_crtc->base.base.id, master_crtc->base.name); 6294 6295 slave_crtc_state->bigjoiner_pipes = 6296 master_crtc_state->bigjoiner_pipes; 6297 6298 ret = copy_bigjoiner_crtc_state_modeset(state, slave_crtc); 6299 if (ret) 6300 return ret; 6301 } 6302 6303 return 0; 6304 } 6305 6306 static void kill_bigjoiner_slave(struct intel_atomic_state *state, 6307 struct intel_crtc *master_crtc) 6308 { 6309 struct drm_i915_private *i915 = to_i915(state->base.dev); 6310 struct intel_crtc_state *master_crtc_state = 6311 intel_atomic_get_new_crtc_state(state, master_crtc); 6312 struct intel_crtc *slave_crtc; 6313 6314 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 6315 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 6316 struct intel_crtc_state *slave_crtc_state = 6317 intel_atomic_get_new_crtc_state(state, slave_crtc); 6318 6319 slave_crtc_state->bigjoiner_pipes = 0; 6320 6321 intel_crtc_copy_uapi_to_hw_state_modeset(state, slave_crtc); 6322 } 6323 6324 master_crtc_state->bigjoiner_pipes = 0; 6325 } 6326 6327 /** 6328 * DOC: asynchronous flip implementation 6329 * 6330 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC 6331 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL. 6332 * Correspondingly, support is currently added for primary plane only. 6333 * 6334 * Async flip can only change the plane surface address, so anything else 6335 * changing is rejected from the intel_async_flip_check_hw() function. 6336 * Once this check is cleared, flip done interrupt is enabled using 6337 * the intel_crtc_enable_flip_done() function. 6338 * 6339 * As soon as the surface address register is written, flip done interrupt is 6340 * generated and the requested events are sent to the usersapce in the interrupt 6341 * handler itself. The timestamp and sequence sent during the flip done event 6342 * correspond to the last vblank and have no relation to the actual time when 6343 * the flip done event was sent. 6344 */ 6345 static int intel_async_flip_check_uapi(struct intel_atomic_state *state, 6346 struct intel_crtc *crtc) 6347 { 6348 struct drm_i915_private *i915 = to_i915(state->base.dev); 6349 const struct intel_crtc_state *new_crtc_state = 6350 intel_atomic_get_new_crtc_state(state, crtc); 6351 const struct intel_plane_state *old_plane_state; 6352 struct intel_plane_state *new_plane_state; 6353 struct intel_plane *plane; 6354 int i; 6355 6356 if (!new_crtc_state->uapi.async_flip) 6357 return 0; 6358 6359 if (!new_crtc_state->uapi.active) { 6360 drm_dbg_kms(&i915->drm, 6361 "[CRTC:%d:%s] not active\n", 6362 crtc->base.base.id, crtc->base.name); 6363 return -EINVAL; 6364 } 6365 6366 if (intel_crtc_needs_modeset(new_crtc_state)) { 6367 drm_dbg_kms(&i915->drm, 6368 "[CRTC:%d:%s] modeset required\n", 6369 crtc->base.base.id, crtc->base.name); 6370 return -EINVAL; 6371 } 6372 6373 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 6374 new_plane_state, i) { 6375 if (plane->pipe != crtc->pipe) 6376 continue; 6377 6378 /* 6379 * TODO: Async flip is only supported through the page flip IOCTL 6380 * as of now. So support currently added for primary plane only. 6381 * Support for other planes on platforms on which supports 6382 * this(vlv/chv and icl+) should be added when async flip is 6383 * enabled in the atomic IOCTL path. 6384 */ 6385 if (!plane->async_flip) { 6386 drm_dbg_kms(&i915->drm, 6387 "[PLANE:%d:%s] async flip not supported\n", 6388 plane->base.base.id, plane->base.name); 6389 return -EINVAL; 6390 } 6391 6392 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) { 6393 drm_dbg_kms(&i915->drm, 6394 "[PLANE:%d:%s] no old or new framebuffer\n", 6395 plane->base.base.id, plane->base.name); 6396 return -EINVAL; 6397 } 6398 } 6399 6400 return 0; 6401 } 6402 6403 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc) 6404 { 6405 struct drm_i915_private *i915 = to_i915(state->base.dev); 6406 const struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6407 const struct intel_plane_state *new_plane_state, *old_plane_state; 6408 struct intel_plane *plane; 6409 int i; 6410 6411 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 6412 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6413 6414 if (!new_crtc_state->uapi.async_flip) 6415 return 0; 6416 6417 if (!new_crtc_state->hw.active) { 6418 drm_dbg_kms(&i915->drm, 6419 "[CRTC:%d:%s] not active\n", 6420 crtc->base.base.id, crtc->base.name); 6421 return -EINVAL; 6422 } 6423 6424 if (intel_crtc_needs_modeset(new_crtc_state)) { 6425 drm_dbg_kms(&i915->drm, 6426 "[CRTC:%d:%s] modeset required\n", 6427 crtc->base.base.id, crtc->base.name); 6428 return -EINVAL; 6429 } 6430 6431 if (old_crtc_state->active_planes != new_crtc_state->active_planes) { 6432 drm_dbg_kms(&i915->drm, 6433 "[CRTC:%d:%s] Active planes cannot be in async flip\n", 6434 crtc->base.base.id, crtc->base.name); 6435 return -EINVAL; 6436 } 6437 6438 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 6439 new_plane_state, i) { 6440 if (plane->pipe != crtc->pipe) 6441 continue; 6442 6443 /* 6444 * Only async flip capable planes should be in the state 6445 * if we're really about to ask the hardware to perform 6446 * an async flip. We should never get this far otherwise. 6447 */ 6448 if (drm_WARN_ON(&i915->drm, 6449 new_crtc_state->do_async_flip && !plane->async_flip)) 6450 return -EINVAL; 6451 6452 /* 6453 * Only check async flip capable planes other planes 6454 * may be involved in the initial commit due to 6455 * the wm0/ddb optimization. 6456 * 6457 * TODO maybe should track which planes actually 6458 * were requested to do the async flip... 6459 */ 6460 if (!plane->async_flip) 6461 continue; 6462 6463 /* 6464 * FIXME: This check is kept generic for all platforms. 6465 * Need to verify this for all gen9 platforms to enable 6466 * this selectively if required. 6467 */ 6468 switch (new_plane_state->hw.fb->modifier) { 6469 case I915_FORMAT_MOD_X_TILED: 6470 case I915_FORMAT_MOD_Y_TILED: 6471 case I915_FORMAT_MOD_Yf_TILED: 6472 case I915_FORMAT_MOD_4_TILED: 6473 break; 6474 default: 6475 drm_dbg_kms(&i915->drm, 6476 "[PLANE:%d:%s] Modifier does not support async flips\n", 6477 plane->base.base.id, plane->base.name); 6478 return -EINVAL; 6479 } 6480 6481 if (new_plane_state->hw.fb->format->num_planes > 1) { 6482 drm_dbg_kms(&i915->drm, 6483 "[PLANE:%d:%s] Planar formats do not support async flips\n", 6484 plane->base.base.id, plane->base.name); 6485 return -EINVAL; 6486 } 6487 6488 if (old_plane_state->view.color_plane[0].mapping_stride != 6489 new_plane_state->view.color_plane[0].mapping_stride) { 6490 drm_dbg_kms(&i915->drm, 6491 "[PLANE:%d:%s] Stride cannot be changed in async flip\n", 6492 plane->base.base.id, plane->base.name); 6493 return -EINVAL; 6494 } 6495 6496 if (old_plane_state->hw.fb->modifier != 6497 new_plane_state->hw.fb->modifier) { 6498 drm_dbg_kms(&i915->drm, 6499 "[PLANE:%d:%s] Modifier cannot be changed in async flip\n", 6500 plane->base.base.id, plane->base.name); 6501 return -EINVAL; 6502 } 6503 6504 if (old_plane_state->hw.fb->format != 6505 new_plane_state->hw.fb->format) { 6506 drm_dbg_kms(&i915->drm, 6507 "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n", 6508 plane->base.base.id, plane->base.name); 6509 return -EINVAL; 6510 } 6511 6512 if (old_plane_state->hw.rotation != 6513 new_plane_state->hw.rotation) { 6514 drm_dbg_kms(&i915->drm, 6515 "[PLANE:%d:%s] Rotation cannot be changed in async flip\n", 6516 plane->base.base.id, plane->base.name); 6517 return -EINVAL; 6518 } 6519 6520 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) || 6521 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) { 6522 drm_dbg_kms(&i915->drm, 6523 "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n", 6524 plane->base.base.id, plane->base.name); 6525 return -EINVAL; 6526 } 6527 6528 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) { 6529 drm_dbg_kms(&i915->drm, 6530 "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n", 6531 plane->base.base.id, plane->base.name); 6532 return -EINVAL; 6533 } 6534 6535 if (old_plane_state->hw.pixel_blend_mode != 6536 new_plane_state->hw.pixel_blend_mode) { 6537 drm_dbg_kms(&i915->drm, 6538 "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n", 6539 plane->base.base.id, plane->base.name); 6540 return -EINVAL; 6541 } 6542 6543 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) { 6544 drm_dbg_kms(&i915->drm, 6545 "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n", 6546 plane->base.base.id, plane->base.name); 6547 return -EINVAL; 6548 } 6549 6550 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) { 6551 drm_dbg_kms(&i915->drm, 6552 "[PLANE:%d:%s] Color range cannot be changed in async flip\n", 6553 plane->base.base.id, plane->base.name); 6554 return -EINVAL; 6555 } 6556 6557 /* plane decryption is allow to change only in synchronous flips */ 6558 if (old_plane_state->decrypt != new_plane_state->decrypt) { 6559 drm_dbg_kms(&i915->drm, 6560 "[PLANE:%d:%s] Decryption cannot be changed in async flip\n", 6561 plane->base.base.id, plane->base.name); 6562 return -EINVAL; 6563 } 6564 } 6565 6566 return 0; 6567 } 6568 6569 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state) 6570 { 6571 struct drm_i915_private *i915 = to_i915(state->base.dev); 6572 struct intel_crtc_state *crtc_state; 6573 struct intel_crtc *crtc; 6574 u8 affected_pipes = 0; 6575 u8 modeset_pipes = 0; 6576 int i; 6577 6578 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6579 affected_pipes |= crtc_state->bigjoiner_pipes; 6580 if (intel_crtc_needs_modeset(crtc_state)) 6581 modeset_pipes |= crtc_state->bigjoiner_pipes; 6582 } 6583 6584 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) { 6585 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6586 if (IS_ERR(crtc_state)) 6587 return PTR_ERR(crtc_state); 6588 } 6589 6590 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) { 6591 int ret; 6592 6593 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6594 6595 crtc_state->uapi.mode_changed = true; 6596 6597 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); 6598 if (ret) 6599 return ret; 6600 6601 ret = intel_atomic_add_affected_planes(state, crtc); 6602 if (ret) 6603 return ret; 6604 } 6605 6606 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6607 /* Kill old bigjoiner link, we may re-establish afterwards */ 6608 if (intel_crtc_needs_modeset(crtc_state) && 6609 intel_crtc_is_bigjoiner_master(crtc_state)) 6610 kill_bigjoiner_slave(state, crtc); 6611 } 6612 6613 return 0; 6614 } 6615 6616 /** 6617 * intel_atomic_check - validate state object 6618 * @dev: drm device 6619 * @_state: state to validate 6620 */ 6621 int intel_atomic_check(struct drm_device *dev, 6622 struct drm_atomic_state *_state) 6623 { 6624 struct drm_i915_private *dev_priv = to_i915(dev); 6625 struct intel_atomic_state *state = to_intel_atomic_state(_state); 6626 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6627 struct intel_crtc *crtc; 6628 int ret, i; 6629 bool any_ms = false; 6630 6631 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6632 new_crtc_state, i) { 6633 if (new_crtc_state->inherited != old_crtc_state->inherited) 6634 new_crtc_state->uapi.mode_changed = true; 6635 6636 if (new_crtc_state->uapi.scaling_filter != 6637 old_crtc_state->uapi.scaling_filter) 6638 new_crtc_state->uapi.mode_changed = true; 6639 } 6640 6641 intel_vrr_check_modeset(state); 6642 6643 ret = drm_atomic_helper_check_modeset(dev, &state->base); 6644 if (ret) 6645 goto fail; 6646 6647 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6648 ret = intel_async_flip_check_uapi(state, crtc); 6649 if (ret) 6650 return ret; 6651 } 6652 6653 ret = intel_bigjoiner_add_affected_crtcs(state); 6654 if (ret) 6655 goto fail; 6656 6657 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6658 new_crtc_state, i) { 6659 if (!intel_crtc_needs_modeset(new_crtc_state)) { 6660 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 6661 copy_bigjoiner_crtc_state_nomodeset(state, crtc); 6662 else 6663 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 6664 continue; 6665 } 6666 6667 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) { 6668 drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable); 6669 continue; 6670 } 6671 6672 ret = intel_crtc_prepare_cleared_state(state, crtc); 6673 if (ret) 6674 goto fail; 6675 6676 if (!new_crtc_state->hw.enable) 6677 continue; 6678 6679 ret = intel_modeset_pipe_config(state, crtc); 6680 if (ret) 6681 goto fail; 6682 6683 ret = intel_atomic_check_bigjoiner(state, crtc); 6684 if (ret) 6685 goto fail; 6686 } 6687 6688 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6689 new_crtc_state, i) { 6690 if (!intel_crtc_needs_modeset(new_crtc_state)) 6691 continue; 6692 6693 if (new_crtc_state->hw.enable) { 6694 ret = intel_modeset_pipe_config_late(state, crtc); 6695 if (ret) 6696 goto fail; 6697 } 6698 6699 intel_crtc_check_fastset(old_crtc_state, new_crtc_state); 6700 } 6701 6702 /** 6703 * Check if fastset is allowed by external dependencies like other 6704 * pipes and transcoders. 6705 * 6706 * Right now it only forces a fullmodeset when the MST master 6707 * transcoder did not changed but the pipe of the master transcoder 6708 * needs a fullmodeset so all slaves also needs to do a fullmodeset or 6709 * in case of port synced crtcs, if one of the synced crtcs 6710 * needs a full modeset, all other synced crtcs should be 6711 * forced a full modeset. 6712 */ 6713 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6714 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state)) 6715 continue; 6716 6717 if (intel_dp_mst_is_slave_trans(new_crtc_state)) { 6718 enum transcoder master = new_crtc_state->mst_master_transcoder; 6719 6720 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) { 6721 new_crtc_state->uapi.mode_changed = true; 6722 new_crtc_state->update_pipe = false; 6723 } 6724 } 6725 6726 if (is_trans_port_sync_mode(new_crtc_state)) { 6727 u8 trans = new_crtc_state->sync_mode_slaves_mask; 6728 6729 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER) 6730 trans |= BIT(new_crtc_state->master_transcoder); 6731 6732 if (intel_cpu_transcoders_need_modeset(state, trans)) { 6733 new_crtc_state->uapi.mode_changed = true; 6734 new_crtc_state->update_pipe = false; 6735 } 6736 } 6737 6738 if (new_crtc_state->bigjoiner_pipes) { 6739 if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) { 6740 new_crtc_state->uapi.mode_changed = true; 6741 new_crtc_state->update_pipe = false; 6742 } 6743 } 6744 } 6745 6746 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6747 new_crtc_state, i) { 6748 if (!intel_crtc_needs_modeset(new_crtc_state)) 6749 continue; 6750 6751 any_ms = true; 6752 6753 intel_release_shared_dplls(state, crtc); 6754 } 6755 6756 if (any_ms && !check_digital_port_conflicts(state)) { 6757 drm_dbg_kms(&dev_priv->drm, 6758 "rejecting conflicting digital port configuration\n"); 6759 ret = -EINVAL; 6760 goto fail; 6761 } 6762 6763 ret = drm_dp_mst_atomic_check(&state->base); 6764 if (ret) 6765 goto fail; 6766 6767 ret = intel_atomic_check_planes(state); 6768 if (ret) 6769 goto fail; 6770 6771 ret = intel_compute_global_watermarks(state); 6772 if (ret) 6773 goto fail; 6774 6775 ret = intel_bw_atomic_check(state); 6776 if (ret) 6777 goto fail; 6778 6779 ret = intel_cdclk_atomic_check(state, &any_ms); 6780 if (ret) 6781 goto fail; 6782 6783 if (intel_any_crtc_needs_modeset(state)) 6784 any_ms = true; 6785 6786 if (any_ms) { 6787 ret = intel_modeset_checks(state); 6788 if (ret) 6789 goto fail; 6790 6791 ret = intel_modeset_calc_cdclk(state); 6792 if (ret) 6793 return ret; 6794 } 6795 6796 ret = intel_atomic_check_crtcs(state); 6797 if (ret) 6798 goto fail; 6799 6800 ret = intel_fbc_atomic_check(state); 6801 if (ret) 6802 goto fail; 6803 6804 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6805 new_crtc_state, i) { 6806 intel_color_assert_luts(new_crtc_state); 6807 6808 ret = intel_async_flip_check_hw(state, crtc); 6809 if (ret) 6810 goto fail; 6811 6812 /* Either full modeset or fastset (or neither), never both */ 6813 drm_WARN_ON(&dev_priv->drm, 6814 intel_crtc_needs_modeset(new_crtc_state) && 6815 intel_crtc_needs_fastset(new_crtc_state)); 6816 6817 if (!intel_crtc_needs_modeset(new_crtc_state) && 6818 !intel_crtc_needs_fastset(new_crtc_state)) 6819 continue; 6820 6821 intel_crtc_state_dump(new_crtc_state, state, 6822 intel_crtc_needs_modeset(new_crtc_state) ? 6823 "modeset" : "fastset"); 6824 } 6825 6826 return 0; 6827 6828 fail: 6829 if (ret == -EDEADLK) 6830 return ret; 6831 6832 /* 6833 * FIXME would probably be nice to know which crtc specifically 6834 * caused the failure, in cases where we can pinpoint it. 6835 */ 6836 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6837 new_crtc_state, i) 6838 intel_crtc_state_dump(new_crtc_state, state, "failed"); 6839 6840 return ret; 6841 } 6842 6843 static int intel_atomic_prepare_commit(struct intel_atomic_state *state) 6844 { 6845 struct intel_crtc_state *crtc_state; 6846 struct intel_crtc *crtc; 6847 int i, ret; 6848 6849 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base); 6850 if (ret < 0) 6851 return ret; 6852 6853 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6854 if (intel_crtc_needs_color_update(crtc_state)) 6855 intel_color_prepare_commit(crtc_state); 6856 } 6857 6858 return 0; 6859 } 6860 6861 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 6862 struct intel_crtc_state *crtc_state) 6863 { 6864 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6865 6866 if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes) 6867 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 6868 6869 if (crtc_state->has_pch_encoder) { 6870 enum pipe pch_transcoder = 6871 intel_crtc_pch_transcoder(crtc); 6872 6873 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true); 6874 } 6875 } 6876 6877 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, 6878 const struct intel_crtc_state *new_crtc_state) 6879 { 6880 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 6881 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6882 6883 /* 6884 * Update pipe size and adjust fitter if needed: the reason for this is 6885 * that in compute_mode_changes we check the native mode (not the pfit 6886 * mode) to see if we can flip rather than do a full mode set. In the 6887 * fastboot case, we'll flip, but if we don't update the pipesrc and 6888 * pfit state, we'll end up with a big fb scanned out into the wrong 6889 * sized surface. 6890 */ 6891 intel_set_pipe_src_size(new_crtc_state); 6892 6893 /* on skylake this is done by detaching scalers */ 6894 if (DISPLAY_VER(dev_priv) >= 9) { 6895 if (new_crtc_state->pch_pfit.enabled) 6896 skl_pfit_enable(new_crtc_state); 6897 } else if (HAS_PCH_SPLIT(dev_priv)) { 6898 if (new_crtc_state->pch_pfit.enabled) 6899 ilk_pfit_enable(new_crtc_state); 6900 else if (old_crtc_state->pch_pfit.enabled) 6901 ilk_pfit_disable(old_crtc_state); 6902 } 6903 6904 /* 6905 * The register is supposedly single buffered so perhaps 6906 * not 100% correct to do this here. But SKL+ calculate 6907 * this based on the adjust pixel rate so pfit changes do 6908 * affect it and so it must be updated for fastsets. 6909 * HSW/BDW only really need this here for fastboot, after 6910 * that the value should not change without a full modeset. 6911 */ 6912 if (DISPLAY_VER(dev_priv) >= 9 || 6913 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 6914 hsw_set_linetime_wm(new_crtc_state); 6915 6916 if (new_crtc_state->seamless_m_n) 6917 intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder, 6918 &new_crtc_state->dp_m_n); 6919 } 6920 6921 static void commit_pipe_pre_planes(struct intel_atomic_state *state, 6922 struct intel_crtc *crtc) 6923 { 6924 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6925 const struct intel_crtc_state *old_crtc_state = 6926 intel_atomic_get_old_crtc_state(state, crtc); 6927 const struct intel_crtc_state *new_crtc_state = 6928 intel_atomic_get_new_crtc_state(state, crtc); 6929 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 6930 6931 /* 6932 * During modesets pipe configuration was programmed as the 6933 * CRTC was enabled. 6934 */ 6935 if (!modeset) { 6936 if (intel_crtc_needs_color_update(new_crtc_state)) 6937 intel_color_commit_arm(new_crtc_state); 6938 6939 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 6940 bdw_set_pipemisc(new_crtc_state); 6941 6942 if (intel_crtc_needs_fastset(new_crtc_state)) 6943 intel_pipe_fastset(old_crtc_state, new_crtc_state); 6944 } 6945 6946 intel_psr2_program_trans_man_trk_ctl(new_crtc_state); 6947 6948 intel_atomic_update_watermarks(state, crtc); 6949 } 6950 6951 static void commit_pipe_post_planes(struct intel_atomic_state *state, 6952 struct intel_crtc *crtc) 6953 { 6954 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6955 const struct intel_crtc_state *new_crtc_state = 6956 intel_atomic_get_new_crtc_state(state, crtc); 6957 6958 /* 6959 * Disable the scaler(s) after the plane(s) so that we don't 6960 * get a catastrophic underrun even if the two operations 6961 * end up happening in two different frames. 6962 */ 6963 if (DISPLAY_VER(dev_priv) >= 9 && 6964 !intel_crtc_needs_modeset(new_crtc_state)) 6965 skl_detach_scalers(new_crtc_state); 6966 } 6967 6968 static void intel_enable_crtc(struct intel_atomic_state *state, 6969 struct intel_crtc *crtc) 6970 { 6971 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6972 const struct intel_crtc_state *new_crtc_state = 6973 intel_atomic_get_new_crtc_state(state, crtc); 6974 6975 if (!intel_crtc_needs_modeset(new_crtc_state)) 6976 return; 6977 6978 intel_crtc_update_active_timings(new_crtc_state); 6979 6980 dev_priv->display.funcs.display->crtc_enable(state, crtc); 6981 6982 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 6983 return; 6984 6985 /* vblanks work again, re-enable pipe CRC. */ 6986 intel_crtc_enable_pipe_crc(crtc); 6987 } 6988 6989 static void intel_update_crtc(struct intel_atomic_state *state, 6990 struct intel_crtc *crtc) 6991 { 6992 struct drm_i915_private *i915 = to_i915(state->base.dev); 6993 const struct intel_crtc_state *old_crtc_state = 6994 intel_atomic_get_old_crtc_state(state, crtc); 6995 struct intel_crtc_state *new_crtc_state = 6996 intel_atomic_get_new_crtc_state(state, crtc); 6997 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 6998 6999 if (!modeset) { 7000 if (new_crtc_state->preload_luts && 7001 intel_crtc_needs_color_update(new_crtc_state)) 7002 intel_color_load_luts(new_crtc_state); 7003 7004 intel_pre_plane_update(state, crtc); 7005 7006 if (intel_crtc_needs_fastset(new_crtc_state)) 7007 intel_encoders_update_pipe(state, crtc); 7008 7009 if (DISPLAY_VER(i915) >= 11 && 7010 intel_crtc_needs_fastset(new_crtc_state)) 7011 icl_set_pipe_chicken(new_crtc_state); 7012 } 7013 7014 intel_fbc_update(state, crtc); 7015 7016 if (!modeset && 7017 intel_crtc_needs_color_update(new_crtc_state)) 7018 intel_color_commit_noarm(new_crtc_state); 7019 7020 intel_crtc_planes_update_noarm(state, crtc); 7021 7022 /* Perform vblank evasion around commit operation */ 7023 intel_pipe_update_start(new_crtc_state); 7024 7025 commit_pipe_pre_planes(state, crtc); 7026 7027 intel_crtc_planes_update_arm(state, crtc); 7028 7029 commit_pipe_post_planes(state, crtc); 7030 7031 intel_pipe_update_end(new_crtc_state); 7032 7033 /* 7034 * We usually enable FIFO underrun interrupts as part of the 7035 * CRTC enable sequence during modesets. But when we inherit a 7036 * valid pipe configuration from the BIOS we need to take care 7037 * of enabling them on the CRTC's first fastset. 7038 */ 7039 if (intel_crtc_needs_fastset(new_crtc_state) && !modeset && 7040 old_crtc_state->inherited) 7041 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state); 7042 } 7043 7044 static void intel_old_crtc_state_disables(struct intel_atomic_state *state, 7045 struct intel_crtc_state *old_crtc_state, 7046 struct intel_crtc_state *new_crtc_state, 7047 struct intel_crtc *crtc) 7048 { 7049 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7050 7051 /* 7052 * We need to disable pipe CRC before disabling the pipe, 7053 * or we race against vblank off. 7054 */ 7055 intel_crtc_disable_pipe_crc(crtc); 7056 7057 dev_priv->display.funcs.display->crtc_disable(state, crtc); 7058 crtc->active = false; 7059 intel_fbc_disable(crtc); 7060 intel_disable_shared_dpll(old_crtc_state); 7061 7062 if (!new_crtc_state->hw.active) 7063 intel_initial_watermarks(state, crtc); 7064 } 7065 7066 static void intel_commit_modeset_disables(struct intel_atomic_state *state) 7067 { 7068 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 7069 struct intel_crtc *crtc; 7070 u32 handled = 0; 7071 int i; 7072 7073 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7074 new_crtc_state, i) { 7075 if (!intel_crtc_needs_modeset(new_crtc_state)) 7076 continue; 7077 7078 if (!old_crtc_state->hw.active) 7079 continue; 7080 7081 intel_pre_plane_update(state, crtc); 7082 intel_crtc_disable_planes(state, crtc); 7083 } 7084 7085 /* Only disable port sync and MST slaves */ 7086 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7087 new_crtc_state, i) { 7088 if (!intel_crtc_needs_modeset(new_crtc_state)) 7089 continue; 7090 7091 if (!old_crtc_state->hw.active) 7092 continue; 7093 7094 /* In case of Transcoder port Sync master slave CRTCs can be 7095 * assigned in any order and we need to make sure that 7096 * slave CRTCs are disabled first and then master CRTC since 7097 * Slave vblanks are masked till Master Vblanks. 7098 */ 7099 if (!is_trans_port_sync_slave(old_crtc_state) && 7100 !intel_dp_mst_is_slave_trans(old_crtc_state) && 7101 !intel_crtc_is_bigjoiner_slave(old_crtc_state)) 7102 continue; 7103 7104 intel_old_crtc_state_disables(state, old_crtc_state, 7105 new_crtc_state, crtc); 7106 handled |= BIT(crtc->pipe); 7107 } 7108 7109 /* Disable everything else left on */ 7110 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7111 new_crtc_state, i) { 7112 if (!intel_crtc_needs_modeset(new_crtc_state) || 7113 (handled & BIT(crtc->pipe))) 7114 continue; 7115 7116 if (!old_crtc_state->hw.active) 7117 continue; 7118 7119 intel_old_crtc_state_disables(state, old_crtc_state, 7120 new_crtc_state, crtc); 7121 } 7122 } 7123 7124 static void intel_commit_modeset_enables(struct intel_atomic_state *state) 7125 { 7126 struct intel_crtc_state *new_crtc_state; 7127 struct intel_crtc *crtc; 7128 int i; 7129 7130 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7131 if (!new_crtc_state->hw.active) 7132 continue; 7133 7134 intel_enable_crtc(state, crtc); 7135 intel_update_crtc(state, crtc); 7136 } 7137 } 7138 7139 static void skl_commit_modeset_enables(struct intel_atomic_state *state) 7140 { 7141 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7142 struct intel_crtc *crtc; 7143 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7144 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; 7145 u8 update_pipes = 0, modeset_pipes = 0; 7146 int i; 7147 7148 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7149 enum pipe pipe = crtc->pipe; 7150 7151 if (!new_crtc_state->hw.active) 7152 continue; 7153 7154 /* ignore allocations for crtc's that have been turned off. */ 7155 if (!intel_crtc_needs_modeset(new_crtc_state)) { 7156 entries[pipe] = old_crtc_state->wm.skl.ddb; 7157 update_pipes |= BIT(pipe); 7158 } else { 7159 modeset_pipes |= BIT(pipe); 7160 } 7161 } 7162 7163 /* 7164 * Whenever the number of active pipes changes, we need to make sure we 7165 * update the pipes in the right order so that their ddb allocations 7166 * never overlap with each other between CRTC updates. Otherwise we'll 7167 * cause pipe underruns and other bad stuff. 7168 * 7169 * So first lets enable all pipes that do not need a fullmodeset as 7170 * those don't have any external dependency. 7171 */ 7172 while (update_pipes) { 7173 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7174 new_crtc_state, i) { 7175 enum pipe pipe = crtc->pipe; 7176 7177 if ((update_pipes & BIT(pipe)) == 0) 7178 continue; 7179 7180 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 7181 entries, I915_MAX_PIPES, pipe)) 7182 continue; 7183 7184 entries[pipe] = new_crtc_state->wm.skl.ddb; 7185 update_pipes &= ~BIT(pipe); 7186 7187 intel_update_crtc(state, crtc); 7188 7189 /* 7190 * If this is an already active pipe, it's DDB changed, 7191 * and this isn't the last pipe that needs updating 7192 * then we need to wait for a vblank to pass for the 7193 * new ddb allocation to take effect. 7194 */ 7195 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, 7196 &old_crtc_state->wm.skl.ddb) && 7197 (update_pipes | modeset_pipes)) 7198 intel_crtc_wait_for_next_vblank(crtc); 7199 } 7200 } 7201 7202 update_pipes = modeset_pipes; 7203 7204 /* 7205 * Enable all pipes that needs a modeset and do not depends on other 7206 * pipes 7207 */ 7208 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7209 enum pipe pipe = crtc->pipe; 7210 7211 if ((modeset_pipes & BIT(pipe)) == 0) 7212 continue; 7213 7214 if (intel_dp_mst_is_slave_trans(new_crtc_state) || 7215 is_trans_port_sync_master(new_crtc_state) || 7216 intel_crtc_is_bigjoiner_master(new_crtc_state)) 7217 continue; 7218 7219 modeset_pipes &= ~BIT(pipe); 7220 7221 intel_enable_crtc(state, crtc); 7222 } 7223 7224 /* 7225 * Then we enable all remaining pipes that depend on other 7226 * pipes: MST slaves and port sync masters, big joiner master 7227 */ 7228 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7229 enum pipe pipe = crtc->pipe; 7230 7231 if ((modeset_pipes & BIT(pipe)) == 0) 7232 continue; 7233 7234 modeset_pipes &= ~BIT(pipe); 7235 7236 intel_enable_crtc(state, crtc); 7237 } 7238 7239 /* 7240 * Finally we do the plane updates/etc. for all pipes that got enabled. 7241 */ 7242 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7243 enum pipe pipe = crtc->pipe; 7244 7245 if ((update_pipes & BIT(pipe)) == 0) 7246 continue; 7247 7248 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 7249 entries, I915_MAX_PIPES, pipe)); 7250 7251 entries[pipe] = new_crtc_state->wm.skl.ddb; 7252 update_pipes &= ~BIT(pipe); 7253 7254 intel_update_crtc(state, crtc); 7255 } 7256 7257 drm_WARN_ON(&dev_priv->drm, modeset_pipes); 7258 drm_WARN_ON(&dev_priv->drm, update_pipes); 7259 } 7260 7261 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) 7262 { 7263 struct intel_atomic_state *state, *next; 7264 struct llist_node *freed; 7265 7266 freed = llist_del_all(&dev_priv->display.atomic_helper.free_list); 7267 llist_for_each_entry_safe(state, next, freed, freed) 7268 drm_atomic_state_put(&state->base); 7269 } 7270 7271 static void intel_atomic_helper_free_state_worker(struct work_struct *work) 7272 { 7273 struct drm_i915_private *dev_priv = 7274 container_of(work, typeof(*dev_priv), display.atomic_helper.free_work); 7275 7276 intel_atomic_helper_free_state(dev_priv); 7277 } 7278 7279 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) 7280 { 7281 struct wait_queue_entry wait_fence, wait_reset; 7282 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); 7283 7284 init_wait_entry(&wait_fence, 0); 7285 init_wait_entry(&wait_reset, 0); 7286 for (;;) { 7287 prepare_to_wait(&intel_state->commit_ready.wait, 7288 &wait_fence, TASK_UNINTERRUPTIBLE); 7289 prepare_to_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 7290 I915_RESET_MODESET), 7291 &wait_reset, TASK_UNINTERRUPTIBLE); 7292 7293 7294 if (i915_sw_fence_done(&intel_state->commit_ready) || 7295 test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags)) 7296 break; 7297 7298 schedule(); 7299 } 7300 finish_wait(&intel_state->commit_ready.wait, &wait_fence); 7301 finish_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 7302 I915_RESET_MODESET), 7303 &wait_reset); 7304 } 7305 7306 static void intel_atomic_cleanup_work(struct work_struct *work) 7307 { 7308 struct intel_atomic_state *state = 7309 container_of(work, struct intel_atomic_state, base.commit_work); 7310 struct drm_i915_private *i915 = to_i915(state->base.dev); 7311 struct intel_crtc_state *old_crtc_state; 7312 struct intel_crtc *crtc; 7313 int i; 7314 7315 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) 7316 intel_color_cleanup_commit(old_crtc_state); 7317 7318 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base); 7319 drm_atomic_helper_commit_cleanup_done(&state->base); 7320 drm_atomic_state_put(&state->base); 7321 7322 intel_atomic_helper_free_state(i915); 7323 } 7324 7325 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state) 7326 { 7327 struct drm_i915_private *i915 = to_i915(state->base.dev); 7328 struct intel_plane *plane; 7329 struct intel_plane_state *plane_state; 7330 int i; 7331 7332 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 7333 struct drm_framebuffer *fb = plane_state->hw.fb; 7334 int cc_plane; 7335 int ret; 7336 7337 if (!fb) 7338 continue; 7339 7340 cc_plane = intel_fb_rc_ccs_cc_plane(fb); 7341 if (cc_plane < 0) 7342 continue; 7343 7344 /* 7345 * The layout of the fast clear color value expected by HW 7346 * (the DRM ABI requiring this value to be located in fb at 7347 * offset 0 of cc plane, plane #2 previous generations or 7348 * plane #1 for flat ccs): 7349 * - 4 x 4 bytes per-channel value 7350 * (in surface type specific float/int format provided by the fb user) 7351 * - 8 bytes native color value used by the display 7352 * (converted/written by GPU during a fast clear operation using the 7353 * above per-channel values) 7354 * 7355 * The commit's FB prepare hook already ensured that FB obj is pinned and the 7356 * caller made sure that the object is synced wrt. the related color clear value 7357 * GPU write on it. 7358 */ 7359 ret = i915_gem_object_read_from_page(intel_fb_obj(fb), 7360 fb->offsets[cc_plane] + 16, 7361 &plane_state->ccval, 7362 sizeof(plane_state->ccval)); 7363 /* The above could only fail if the FB obj has an unexpected backing store type. */ 7364 drm_WARN_ON(&i915->drm, ret); 7365 } 7366 } 7367 7368 static void intel_atomic_commit_tail(struct intel_atomic_state *state) 7369 { 7370 struct drm_device *dev = state->base.dev; 7371 struct drm_i915_private *dev_priv = to_i915(dev); 7372 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 7373 struct intel_crtc *crtc; 7374 struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {}; 7375 intel_wakeref_t wakeref = 0; 7376 int i; 7377 7378 intel_atomic_commit_fence_wait(state); 7379 7380 drm_atomic_helper_wait_for_dependencies(&state->base); 7381 drm_dp_mst_atomic_wait_for_dependencies(&state->base); 7382 7383 if (state->modeset) 7384 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); 7385 7386 intel_atomic_prepare_plane_clear_colors(state); 7387 7388 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7389 new_crtc_state, i) { 7390 if (intel_crtc_needs_modeset(new_crtc_state) || 7391 intel_crtc_needs_fastset(new_crtc_state)) 7392 intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]); 7393 } 7394 7395 intel_commit_modeset_disables(state); 7396 7397 /* FIXME: Eventually get rid of our crtc->config pointer */ 7398 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7399 crtc->config = new_crtc_state; 7400 7401 if (state->modeset) { 7402 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base); 7403 7404 intel_set_cdclk_pre_plane_update(state); 7405 7406 intel_modeset_verify_disabled(dev_priv, state); 7407 } 7408 7409 intel_sagv_pre_plane_update(state); 7410 7411 /* Complete the events for pipes that have now been disabled */ 7412 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7413 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 7414 7415 /* Complete events for now disable pipes here. */ 7416 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) { 7417 spin_lock_irq(&dev->event_lock); 7418 drm_crtc_send_vblank_event(&crtc->base, 7419 new_crtc_state->uapi.event); 7420 spin_unlock_irq(&dev->event_lock); 7421 7422 new_crtc_state->uapi.event = NULL; 7423 } 7424 } 7425 7426 intel_encoders_update_prepare(state); 7427 7428 intel_dbuf_pre_plane_update(state); 7429 intel_mbus_dbox_update(state); 7430 7431 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7432 if (new_crtc_state->do_async_flip) 7433 intel_crtc_enable_flip_done(state, crtc); 7434 } 7435 7436 /* Now enable the clocks, plane, pipe, and connectors that we set up. */ 7437 dev_priv->display.funcs.display->commit_modeset_enables(state); 7438 7439 intel_encoders_update_complete(state); 7440 7441 if (state->modeset) 7442 intel_set_cdclk_post_plane_update(state); 7443 7444 intel_wait_for_vblank_workers(state); 7445 7446 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here 7447 * already, but still need the state for the delayed optimization. To 7448 * fix this: 7449 * - wrap the optimization/post_plane_update stuff into a per-crtc work. 7450 * - schedule that vblank worker _before_ calling hw_done 7451 * - at the start of commit_tail, cancel it _synchrously 7452 * - switch over to the vblank wait helper in the core after that since 7453 * we don't need out special handling any more. 7454 */ 7455 drm_atomic_helper_wait_for_flip_done(dev, &state->base); 7456 7457 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7458 if (new_crtc_state->do_async_flip) 7459 intel_crtc_disable_flip_done(state, crtc); 7460 } 7461 7462 /* 7463 * Now that the vblank has passed, we can go ahead and program the 7464 * optimal watermarks on platforms that need two-step watermark 7465 * programming. 7466 * 7467 * TODO: Move this (and other cleanup) to an async worker eventually. 7468 */ 7469 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7470 new_crtc_state, i) { 7471 /* 7472 * Gen2 reports pipe underruns whenever all planes are disabled. 7473 * So re-enable underrun reporting after some planes get enabled. 7474 * 7475 * We do this before .optimize_watermarks() so that we have a 7476 * chance of catching underruns with the intermediate watermarks 7477 * vs. the new plane configuration. 7478 */ 7479 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state)) 7480 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 7481 7482 intel_optimize_watermarks(state, crtc); 7483 } 7484 7485 intel_dbuf_post_plane_update(state); 7486 intel_psr_post_plane_update(state); 7487 7488 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7489 intel_post_plane_update(state, crtc); 7490 7491 intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]); 7492 7493 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state); 7494 7495 /* Must be done after gamma readout due to HSW split gamma vs. IPS w/a */ 7496 hsw_ips_post_update(state, crtc); 7497 7498 /* 7499 * Activate DRRS after state readout to avoid 7500 * dp_m_n vs. dp_m2_n2 confusion on BDW+. 7501 */ 7502 intel_drrs_activate(new_crtc_state); 7503 7504 /* 7505 * DSB cleanup is done in cleanup_work aligning with framebuffer 7506 * cleanup. So copy and reset the dsb structure to sync with 7507 * commit_done and later do dsb cleanup in cleanup_work. 7508 * 7509 * FIXME get rid of this funny new->old swapping 7510 */ 7511 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb); 7512 } 7513 7514 /* Underruns don't always raise interrupts, so check manually */ 7515 intel_check_cpu_fifo_underruns(dev_priv); 7516 intel_check_pch_fifo_underruns(dev_priv); 7517 7518 if (state->modeset) 7519 intel_verify_planes(state); 7520 7521 intel_sagv_post_plane_update(state); 7522 7523 drm_atomic_helper_commit_hw_done(&state->base); 7524 7525 if (state->modeset) { 7526 /* As one of the primary mmio accessors, KMS has a high 7527 * likelihood of triggering bugs in unclaimed access. After we 7528 * finish modesetting, see if an error has been flagged, and if 7529 * so enable debugging for the next modeset - and hope we catch 7530 * the culprit. 7531 */ 7532 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); 7533 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref); 7534 } 7535 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7536 7537 /* 7538 * Defer the cleanup of the old state to a separate worker to not 7539 * impede the current task (userspace for blocking modesets) that 7540 * are executed inline. For out-of-line asynchronous modesets/flips, 7541 * deferring to a new worker seems overkill, but we would place a 7542 * schedule point (cond_resched()) here anyway to keep latencies 7543 * down. 7544 */ 7545 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work); 7546 queue_work(system_highpri_wq, &state->base.commit_work); 7547 } 7548 7549 static void intel_atomic_commit_work(struct work_struct *work) 7550 { 7551 struct intel_atomic_state *state = 7552 container_of(work, struct intel_atomic_state, base.commit_work); 7553 7554 intel_atomic_commit_tail(state); 7555 } 7556 7557 static int 7558 intel_atomic_commit_ready(struct i915_sw_fence *fence, 7559 enum i915_sw_fence_notify notify) 7560 { 7561 struct intel_atomic_state *state = 7562 container_of(fence, struct intel_atomic_state, commit_ready); 7563 7564 switch (notify) { 7565 case FENCE_COMPLETE: 7566 /* we do blocking waits in the worker, nothing to do here */ 7567 break; 7568 case FENCE_FREE: 7569 { 7570 struct intel_atomic_helper *helper = 7571 &to_i915(state->base.dev)->display.atomic_helper; 7572 7573 if (llist_add(&state->freed, &helper->free_list)) 7574 schedule_work(&helper->free_work); 7575 break; 7576 } 7577 } 7578 7579 return NOTIFY_DONE; 7580 } 7581 7582 static void intel_atomic_track_fbs(struct intel_atomic_state *state) 7583 { 7584 struct intel_plane_state *old_plane_state, *new_plane_state; 7585 struct intel_plane *plane; 7586 int i; 7587 7588 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 7589 new_plane_state, i) 7590 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), 7591 to_intel_frontbuffer(new_plane_state->hw.fb), 7592 plane->frontbuffer_bit); 7593 } 7594 7595 static int intel_atomic_commit(struct drm_device *dev, 7596 struct drm_atomic_state *_state, 7597 bool nonblock) 7598 { 7599 struct intel_atomic_state *state = to_intel_atomic_state(_state); 7600 struct drm_i915_private *dev_priv = to_i915(dev); 7601 int ret = 0; 7602 7603 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 7604 7605 drm_atomic_state_get(&state->base); 7606 i915_sw_fence_init(&state->commit_ready, 7607 intel_atomic_commit_ready); 7608 7609 /* 7610 * The intel_legacy_cursor_update() fast path takes care 7611 * of avoiding the vblank waits for simple cursor 7612 * movement and flips. For cursor on/off and size changes, 7613 * we want to perform the vblank waits so that watermark 7614 * updates happen during the correct frames. Gen9+ have 7615 * double buffered watermarks and so shouldn't need this. 7616 * 7617 * Unset state->legacy_cursor_update before the call to 7618 * drm_atomic_helper_setup_commit() because otherwise 7619 * drm_atomic_helper_wait_for_flip_done() is a noop and 7620 * we get FIFO underruns because we didn't wait 7621 * for vblank. 7622 * 7623 * FIXME doing watermarks and fb cleanup from a vblank worker 7624 * (assuming we had any) would solve these problems. 7625 */ 7626 if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) { 7627 struct intel_crtc_state *new_crtc_state; 7628 struct intel_crtc *crtc; 7629 int i; 7630 7631 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7632 if (new_crtc_state->wm.need_postvbl_update || 7633 new_crtc_state->update_wm_post) 7634 state->base.legacy_cursor_update = false; 7635 } 7636 7637 ret = intel_atomic_prepare_commit(state); 7638 if (ret) { 7639 drm_dbg_atomic(&dev_priv->drm, 7640 "Preparing state failed with %i\n", ret); 7641 i915_sw_fence_commit(&state->commit_ready); 7642 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7643 return ret; 7644 } 7645 7646 ret = drm_atomic_helper_setup_commit(&state->base, nonblock); 7647 if (!ret) 7648 ret = drm_atomic_helper_swap_state(&state->base, true); 7649 if (!ret) 7650 intel_atomic_swap_global_state(state); 7651 7652 if (ret) { 7653 struct intel_crtc_state *new_crtc_state; 7654 struct intel_crtc *crtc; 7655 int i; 7656 7657 i915_sw_fence_commit(&state->commit_ready); 7658 7659 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7660 intel_color_cleanup_commit(new_crtc_state); 7661 7662 drm_atomic_helper_cleanup_planes(dev, &state->base); 7663 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7664 return ret; 7665 } 7666 intel_shared_dpll_swap_state(state); 7667 intel_atomic_track_fbs(state); 7668 7669 drm_atomic_state_get(&state->base); 7670 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work); 7671 7672 i915_sw_fence_commit(&state->commit_ready); 7673 if (nonblock && state->modeset) { 7674 queue_work(dev_priv->display.wq.modeset, &state->base.commit_work); 7675 } else if (nonblock) { 7676 queue_work(dev_priv->display.wq.flip, &state->base.commit_work); 7677 } else { 7678 if (state->modeset) 7679 flush_workqueue(dev_priv->display.wq.modeset); 7680 intel_atomic_commit_tail(state); 7681 } 7682 7683 return 0; 7684 } 7685 7686 /** 7687 * intel_plane_destroy - destroy a plane 7688 * @plane: plane to destroy 7689 * 7690 * Common destruction function for all types of planes (primary, cursor, 7691 * sprite). 7692 */ 7693 void intel_plane_destroy(struct drm_plane *plane) 7694 { 7695 drm_plane_cleanup(plane); 7696 kfree(to_intel_plane(plane)); 7697 } 7698 7699 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv) 7700 { 7701 struct intel_plane *plane; 7702 7703 for_each_intel_plane(&dev_priv->drm, plane) { 7704 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, 7705 plane->pipe); 7706 7707 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base); 7708 } 7709 } 7710 7711 7712 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 7713 struct drm_file *file) 7714 { 7715 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; 7716 struct drm_crtc *drmmode_crtc; 7717 struct intel_crtc *crtc; 7718 7719 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id); 7720 if (!drmmode_crtc) 7721 return -ENOENT; 7722 7723 crtc = to_intel_crtc(drmmode_crtc); 7724 pipe_from_crtc_id->pipe = crtc->pipe; 7725 7726 return 0; 7727 } 7728 7729 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder) 7730 { 7731 struct drm_device *dev = encoder->base.dev; 7732 struct intel_encoder *source_encoder; 7733 u32 possible_clones = 0; 7734 7735 for_each_intel_encoder(dev, source_encoder) { 7736 if (encoders_cloneable(encoder, source_encoder)) 7737 possible_clones |= drm_encoder_mask(&source_encoder->base); 7738 } 7739 7740 return possible_clones; 7741 } 7742 7743 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder) 7744 { 7745 struct drm_device *dev = encoder->base.dev; 7746 struct intel_crtc *crtc; 7747 u32 possible_crtcs = 0; 7748 7749 for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask) 7750 possible_crtcs |= drm_crtc_mask(&crtc->base); 7751 7752 return possible_crtcs; 7753 } 7754 7755 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv) 7756 { 7757 if (!IS_MOBILE(dev_priv)) 7758 return false; 7759 7760 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0) 7761 return false; 7762 7763 if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE)) 7764 return false; 7765 7766 return true; 7767 } 7768 7769 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv) 7770 { 7771 if (DISPLAY_VER(dev_priv) >= 9) 7772 return false; 7773 7774 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) 7775 return false; 7776 7777 if (HAS_PCH_LPT_H(dev_priv) && 7778 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) 7779 return false; 7780 7781 /* DDI E can't be used if DDI A requires 4 lanes */ 7782 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 7783 return false; 7784 7785 if (!dev_priv->display.vbt.int_crt_support) 7786 return false; 7787 7788 return true; 7789 } 7790 7791 static void intel_setup_outputs(struct drm_i915_private *dev_priv) 7792 { 7793 struct intel_encoder *encoder; 7794 bool dpd_is_edp = false; 7795 7796 intel_pps_unlock_regs_wa(dev_priv); 7797 7798 if (!HAS_DISPLAY(dev_priv)) 7799 return; 7800 7801 if (IS_DG2(dev_priv)) { 7802 intel_ddi_init(dev_priv, PORT_A); 7803 intel_ddi_init(dev_priv, PORT_B); 7804 intel_ddi_init(dev_priv, PORT_C); 7805 intel_ddi_init(dev_priv, PORT_D_XELPD); 7806 intel_ddi_init(dev_priv, PORT_TC1); 7807 } else if (IS_ALDERLAKE_P(dev_priv)) { 7808 intel_ddi_init(dev_priv, PORT_A); 7809 intel_ddi_init(dev_priv, PORT_B); 7810 intel_ddi_init(dev_priv, PORT_TC1); 7811 intel_ddi_init(dev_priv, PORT_TC2); 7812 intel_ddi_init(dev_priv, PORT_TC3); 7813 intel_ddi_init(dev_priv, PORT_TC4); 7814 icl_dsi_init(dev_priv); 7815 } else if (IS_ALDERLAKE_S(dev_priv)) { 7816 intel_ddi_init(dev_priv, PORT_A); 7817 intel_ddi_init(dev_priv, PORT_TC1); 7818 intel_ddi_init(dev_priv, PORT_TC2); 7819 intel_ddi_init(dev_priv, PORT_TC3); 7820 intel_ddi_init(dev_priv, PORT_TC4); 7821 } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) { 7822 intel_ddi_init(dev_priv, PORT_A); 7823 intel_ddi_init(dev_priv, PORT_B); 7824 intel_ddi_init(dev_priv, PORT_TC1); 7825 intel_ddi_init(dev_priv, PORT_TC2); 7826 } else if (DISPLAY_VER(dev_priv) >= 12) { 7827 intel_ddi_init(dev_priv, PORT_A); 7828 intel_ddi_init(dev_priv, PORT_B); 7829 intel_ddi_init(dev_priv, PORT_TC1); 7830 intel_ddi_init(dev_priv, PORT_TC2); 7831 intel_ddi_init(dev_priv, PORT_TC3); 7832 intel_ddi_init(dev_priv, PORT_TC4); 7833 intel_ddi_init(dev_priv, PORT_TC5); 7834 intel_ddi_init(dev_priv, PORT_TC6); 7835 icl_dsi_init(dev_priv); 7836 } else if (IS_JSL_EHL(dev_priv)) { 7837 intel_ddi_init(dev_priv, PORT_A); 7838 intel_ddi_init(dev_priv, PORT_B); 7839 intel_ddi_init(dev_priv, PORT_C); 7840 intel_ddi_init(dev_priv, PORT_D); 7841 icl_dsi_init(dev_priv); 7842 } else if (DISPLAY_VER(dev_priv) == 11) { 7843 intel_ddi_init(dev_priv, PORT_A); 7844 intel_ddi_init(dev_priv, PORT_B); 7845 intel_ddi_init(dev_priv, PORT_C); 7846 intel_ddi_init(dev_priv, PORT_D); 7847 intel_ddi_init(dev_priv, PORT_E); 7848 intel_ddi_init(dev_priv, PORT_F); 7849 icl_dsi_init(dev_priv); 7850 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 7851 intel_ddi_init(dev_priv, PORT_A); 7852 intel_ddi_init(dev_priv, PORT_B); 7853 intel_ddi_init(dev_priv, PORT_C); 7854 vlv_dsi_init(dev_priv); 7855 } else if (DISPLAY_VER(dev_priv) >= 9) { 7856 intel_ddi_init(dev_priv, PORT_A); 7857 intel_ddi_init(dev_priv, PORT_B); 7858 intel_ddi_init(dev_priv, PORT_C); 7859 intel_ddi_init(dev_priv, PORT_D); 7860 intel_ddi_init(dev_priv, PORT_E); 7861 } else if (HAS_DDI(dev_priv)) { 7862 u32 found; 7863 7864 if (intel_ddi_crt_present(dev_priv)) 7865 intel_crt_init(dev_priv); 7866 7867 /* Haswell uses DDI functions to detect digital outputs. */ 7868 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 7869 if (found) 7870 intel_ddi_init(dev_priv, PORT_A); 7871 7872 found = intel_de_read(dev_priv, SFUSE_STRAP); 7873 if (found & SFUSE_STRAP_DDIB_DETECTED) 7874 intel_ddi_init(dev_priv, PORT_B); 7875 if (found & SFUSE_STRAP_DDIC_DETECTED) 7876 intel_ddi_init(dev_priv, PORT_C); 7877 if (found & SFUSE_STRAP_DDID_DETECTED) 7878 intel_ddi_init(dev_priv, PORT_D); 7879 if (found & SFUSE_STRAP_DDIF_DETECTED) 7880 intel_ddi_init(dev_priv, PORT_F); 7881 } else if (HAS_PCH_SPLIT(dev_priv)) { 7882 int found; 7883 7884 /* 7885 * intel_edp_init_connector() depends on this completing first, 7886 * to prevent the registration of both eDP and LVDS and the 7887 * incorrect sharing of the PPS. 7888 */ 7889 intel_lvds_init(dev_priv); 7890 intel_crt_init(dev_priv); 7891 7892 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D); 7893 7894 if (ilk_has_edp_a(dev_priv)) 7895 g4x_dp_init(dev_priv, DP_A, PORT_A); 7896 7897 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) { 7898 /* PCH SDVOB multiplex with HDMIB */ 7899 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); 7900 if (!found) 7901 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); 7902 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED)) 7903 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B); 7904 } 7905 7906 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED) 7907 g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); 7908 7909 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED) 7910 g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D); 7911 7912 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED) 7913 g4x_dp_init(dev_priv, PCH_DP_C, PORT_C); 7914 7915 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED) 7916 g4x_dp_init(dev_priv, PCH_DP_D, PORT_D); 7917 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 7918 bool has_edp, has_port; 7919 7920 if (IS_VALLEYVIEW(dev_priv) && dev_priv->display.vbt.int_crt_support) 7921 intel_crt_init(dev_priv); 7922 7923 /* 7924 * The DP_DETECTED bit is the latched state of the DDC 7925 * SDA pin at boot. However since eDP doesn't require DDC 7926 * (no way to plug in a DP->HDMI dongle) the DDC pins for 7927 * eDP ports may have been muxed to an alternate function. 7928 * Thus we can't rely on the DP_DETECTED bit alone to detect 7929 * eDP ports. Consult the VBT as well as DP_DETECTED to 7930 * detect eDP ports. 7931 * 7932 * Sadly the straps seem to be missing sometimes even for HDMI 7933 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap 7934 * and VBT for the presence of the port. Additionally we can't 7935 * trust the port type the VBT declares as we've seen at least 7936 * HDMI ports that the VBT claim are DP or eDP. 7937 */ 7938 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B); 7939 has_port = intel_bios_is_port_present(dev_priv, PORT_B); 7940 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port) 7941 has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B); 7942 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) 7943 g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); 7944 7945 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C); 7946 has_port = intel_bios_is_port_present(dev_priv, PORT_C); 7947 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port) 7948 has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C); 7949 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) 7950 g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); 7951 7952 if (IS_CHERRYVIEW(dev_priv)) { 7953 /* 7954 * eDP not supported on port D, 7955 * so no need to worry about it 7956 */ 7957 has_port = intel_bios_is_port_present(dev_priv, PORT_D); 7958 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port) 7959 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D); 7960 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port) 7961 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D); 7962 } 7963 7964 vlv_dsi_init(dev_priv); 7965 } else if (IS_PINEVIEW(dev_priv)) { 7966 intel_lvds_init(dev_priv); 7967 intel_crt_init(dev_priv); 7968 } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) { 7969 bool found = false; 7970 7971 if (IS_MOBILE(dev_priv)) 7972 intel_lvds_init(dev_priv); 7973 7974 intel_crt_init(dev_priv); 7975 7976 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 7977 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n"); 7978 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); 7979 if (!found && IS_G4X(dev_priv)) { 7980 drm_dbg_kms(&dev_priv->drm, 7981 "probing HDMI on SDVOB\n"); 7982 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); 7983 } 7984 7985 if (!found && IS_G4X(dev_priv)) 7986 g4x_dp_init(dev_priv, DP_B, PORT_B); 7987 } 7988 7989 /* Before G4X SDVOC doesn't have its own detect register */ 7990 7991 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 7992 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n"); 7993 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); 7994 } 7995 7996 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) { 7997 7998 if (IS_G4X(dev_priv)) { 7999 drm_dbg_kms(&dev_priv->drm, 8000 "probing HDMI on SDVOC\n"); 8001 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); 8002 } 8003 if (IS_G4X(dev_priv)) 8004 g4x_dp_init(dev_priv, DP_C, PORT_C); 8005 } 8006 8007 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED)) 8008 g4x_dp_init(dev_priv, DP_D, PORT_D); 8009 8010 if (SUPPORTS_TV(dev_priv)) 8011 intel_tv_init(dev_priv); 8012 } else if (DISPLAY_VER(dev_priv) == 2) { 8013 if (IS_I85X(dev_priv)) 8014 intel_lvds_init(dev_priv); 8015 8016 intel_crt_init(dev_priv); 8017 intel_dvo_init(dev_priv); 8018 } 8019 8020 for_each_intel_encoder(&dev_priv->drm, encoder) { 8021 encoder->base.possible_crtcs = 8022 intel_encoder_possible_crtcs(encoder); 8023 encoder->base.possible_clones = 8024 intel_encoder_possible_clones(encoder); 8025 } 8026 8027 intel_init_pch_refclk(dev_priv); 8028 8029 drm_helper_move_panel_connectors_to_head(&dev_priv->drm); 8030 } 8031 8032 static int max_dotclock(struct drm_i915_private *i915) 8033 { 8034 int max_dotclock = i915->max_dotclk_freq; 8035 8036 /* icl+ might use bigjoiner */ 8037 if (DISPLAY_VER(i915) >= 11) 8038 max_dotclock *= 2; 8039 8040 return max_dotclock; 8041 } 8042 8043 static enum drm_mode_status 8044 intel_mode_valid(struct drm_device *dev, 8045 const struct drm_display_mode *mode) 8046 { 8047 struct drm_i915_private *dev_priv = to_i915(dev); 8048 int hdisplay_max, htotal_max; 8049 int vdisplay_max, vtotal_max; 8050 8051 /* 8052 * Can't reject DBLSCAN here because Xorg ddxen can add piles 8053 * of DBLSCAN modes to the output's mode list when they detect 8054 * the scaling mode property on the connector. And they don't 8055 * ask the kernel to validate those modes in any way until 8056 * modeset time at which point the client gets a protocol error. 8057 * So in order to not upset those clients we silently ignore the 8058 * DBLSCAN flag on such connectors. For other connectors we will 8059 * reject modes with the DBLSCAN flag in encoder->compute_config(). 8060 * And we always reject DBLSCAN modes in connector->mode_valid() 8061 * as we never want such modes on the connector's mode list. 8062 */ 8063 8064 if (mode->vscan > 1) 8065 return MODE_NO_VSCAN; 8066 8067 if (mode->flags & DRM_MODE_FLAG_HSKEW) 8068 return MODE_H_ILLEGAL; 8069 8070 if (mode->flags & (DRM_MODE_FLAG_CSYNC | 8071 DRM_MODE_FLAG_NCSYNC | 8072 DRM_MODE_FLAG_PCSYNC)) 8073 return MODE_HSYNC; 8074 8075 if (mode->flags & (DRM_MODE_FLAG_BCAST | 8076 DRM_MODE_FLAG_PIXMUX | 8077 DRM_MODE_FLAG_CLKDIV2)) 8078 return MODE_BAD; 8079 8080 /* 8081 * Reject clearly excessive dotclocks early to 8082 * avoid having to worry about huge integers later. 8083 */ 8084 if (mode->clock > max_dotclock(dev_priv)) 8085 return MODE_CLOCK_HIGH; 8086 8087 /* Transcoder timing limits */ 8088 if (DISPLAY_VER(dev_priv) >= 11) { 8089 hdisplay_max = 16384; 8090 vdisplay_max = 8192; 8091 htotal_max = 16384; 8092 vtotal_max = 8192; 8093 } else if (DISPLAY_VER(dev_priv) >= 9 || 8094 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 8095 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ 8096 vdisplay_max = 4096; 8097 htotal_max = 8192; 8098 vtotal_max = 8192; 8099 } else if (DISPLAY_VER(dev_priv) >= 3) { 8100 hdisplay_max = 4096; 8101 vdisplay_max = 4096; 8102 htotal_max = 8192; 8103 vtotal_max = 8192; 8104 } else { 8105 hdisplay_max = 2048; 8106 vdisplay_max = 2048; 8107 htotal_max = 4096; 8108 vtotal_max = 4096; 8109 } 8110 8111 if (mode->hdisplay > hdisplay_max || 8112 mode->hsync_start > htotal_max || 8113 mode->hsync_end > htotal_max || 8114 mode->htotal > htotal_max) 8115 return MODE_H_ILLEGAL; 8116 8117 if (mode->vdisplay > vdisplay_max || 8118 mode->vsync_start > vtotal_max || 8119 mode->vsync_end > vtotal_max || 8120 mode->vtotal > vtotal_max) 8121 return MODE_V_ILLEGAL; 8122 8123 if (DISPLAY_VER(dev_priv) >= 5) { 8124 if (mode->hdisplay < 64 || 8125 mode->htotal - mode->hdisplay < 32) 8126 return MODE_H_ILLEGAL; 8127 8128 if (mode->vtotal - mode->vdisplay < 5) 8129 return MODE_V_ILLEGAL; 8130 } else { 8131 if (mode->htotal - mode->hdisplay < 32) 8132 return MODE_H_ILLEGAL; 8133 8134 if (mode->vtotal - mode->vdisplay < 3) 8135 return MODE_V_ILLEGAL; 8136 } 8137 8138 /* 8139 * Cantiga+ cannot handle modes with a hsync front porch of 0. 8140 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. 8141 */ 8142 if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) && 8143 mode->hsync_start == mode->hdisplay) 8144 return MODE_H_ILLEGAL; 8145 8146 return MODE_OK; 8147 } 8148 8149 enum drm_mode_status 8150 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 8151 const struct drm_display_mode *mode, 8152 bool bigjoiner) 8153 { 8154 int plane_width_max, plane_height_max; 8155 8156 /* 8157 * intel_mode_valid() should be 8158 * sufficient on older platforms. 8159 */ 8160 if (DISPLAY_VER(dev_priv) < 9) 8161 return MODE_OK; 8162 8163 /* 8164 * Most people will probably want a fullscreen 8165 * plane so let's not advertize modes that are 8166 * too big for that. 8167 */ 8168 if (DISPLAY_VER(dev_priv) >= 11) { 8169 plane_width_max = 5120 << bigjoiner; 8170 plane_height_max = 4320; 8171 } else { 8172 plane_width_max = 5120; 8173 plane_height_max = 4096; 8174 } 8175 8176 if (mode->hdisplay > plane_width_max) 8177 return MODE_H_ILLEGAL; 8178 8179 if (mode->vdisplay > plane_height_max) 8180 return MODE_V_ILLEGAL; 8181 8182 return MODE_OK; 8183 } 8184 8185 static const struct drm_mode_config_funcs intel_mode_funcs = { 8186 .fb_create = intel_user_framebuffer_create, 8187 .get_format_info = intel_fb_get_format_info, 8188 .output_poll_changed = intel_fbdev_output_poll_changed, 8189 .mode_valid = intel_mode_valid, 8190 .atomic_check = intel_atomic_check, 8191 .atomic_commit = intel_atomic_commit, 8192 .atomic_state_alloc = intel_atomic_state_alloc, 8193 .atomic_state_clear = intel_atomic_state_clear, 8194 .atomic_state_free = intel_atomic_state_free, 8195 }; 8196 8197 static const struct intel_display_funcs skl_display_funcs = { 8198 .get_pipe_config = hsw_get_pipe_config, 8199 .crtc_enable = hsw_crtc_enable, 8200 .crtc_disable = hsw_crtc_disable, 8201 .commit_modeset_enables = skl_commit_modeset_enables, 8202 .get_initial_plane_config = skl_get_initial_plane_config, 8203 }; 8204 8205 static const struct intel_display_funcs ddi_display_funcs = { 8206 .get_pipe_config = hsw_get_pipe_config, 8207 .crtc_enable = hsw_crtc_enable, 8208 .crtc_disable = hsw_crtc_disable, 8209 .commit_modeset_enables = intel_commit_modeset_enables, 8210 .get_initial_plane_config = i9xx_get_initial_plane_config, 8211 }; 8212 8213 static const struct intel_display_funcs pch_split_display_funcs = { 8214 .get_pipe_config = ilk_get_pipe_config, 8215 .crtc_enable = ilk_crtc_enable, 8216 .crtc_disable = ilk_crtc_disable, 8217 .commit_modeset_enables = intel_commit_modeset_enables, 8218 .get_initial_plane_config = i9xx_get_initial_plane_config, 8219 }; 8220 8221 static const struct intel_display_funcs vlv_display_funcs = { 8222 .get_pipe_config = i9xx_get_pipe_config, 8223 .crtc_enable = valleyview_crtc_enable, 8224 .crtc_disable = i9xx_crtc_disable, 8225 .commit_modeset_enables = intel_commit_modeset_enables, 8226 .get_initial_plane_config = i9xx_get_initial_plane_config, 8227 }; 8228 8229 static const struct intel_display_funcs i9xx_display_funcs = { 8230 .get_pipe_config = i9xx_get_pipe_config, 8231 .crtc_enable = i9xx_crtc_enable, 8232 .crtc_disable = i9xx_crtc_disable, 8233 .commit_modeset_enables = intel_commit_modeset_enables, 8234 .get_initial_plane_config = i9xx_get_initial_plane_config, 8235 }; 8236 8237 /** 8238 * intel_init_display_hooks - initialize the display modesetting hooks 8239 * @dev_priv: device private 8240 */ 8241 void intel_init_display_hooks(struct drm_i915_private *dev_priv) 8242 { 8243 if (!HAS_DISPLAY(dev_priv)) 8244 return; 8245 8246 intel_color_init_hooks(dev_priv); 8247 intel_init_cdclk_hooks(dev_priv); 8248 intel_audio_hooks_init(dev_priv); 8249 8250 intel_dpll_init_clock_hook(dev_priv); 8251 8252 if (DISPLAY_VER(dev_priv) >= 9) { 8253 dev_priv->display.funcs.display = &skl_display_funcs; 8254 } else if (HAS_DDI(dev_priv)) { 8255 dev_priv->display.funcs.display = &ddi_display_funcs; 8256 } else if (HAS_PCH_SPLIT(dev_priv)) { 8257 dev_priv->display.funcs.display = &pch_split_display_funcs; 8258 } else if (IS_CHERRYVIEW(dev_priv) || 8259 IS_VALLEYVIEW(dev_priv)) { 8260 dev_priv->display.funcs.display = &vlv_display_funcs; 8261 } else { 8262 dev_priv->display.funcs.display = &i9xx_display_funcs; 8263 } 8264 8265 intel_fdi_init_hook(dev_priv); 8266 } 8267 8268 void intel_modeset_init_hw(struct drm_i915_private *i915) 8269 { 8270 struct intel_cdclk_state *cdclk_state; 8271 8272 if (!HAS_DISPLAY(i915)) 8273 return; 8274 8275 cdclk_state = to_intel_cdclk_state(i915->display.cdclk.obj.state); 8276 8277 intel_update_cdclk(i915); 8278 intel_cdclk_dump_config(i915, &i915->display.cdclk.hw, "Current CDCLK"); 8279 cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw; 8280 } 8281 8282 static int intel_initial_commit(struct drm_device *dev) 8283 { 8284 struct drm_atomic_state *state = NULL; 8285 struct drm_modeset_acquire_ctx ctx; 8286 struct intel_crtc *crtc; 8287 int ret = 0; 8288 8289 state = drm_atomic_state_alloc(dev); 8290 if (!state) 8291 return -ENOMEM; 8292 8293 drm_modeset_acquire_init(&ctx, 0); 8294 8295 retry: 8296 state->acquire_ctx = &ctx; 8297 8298 for_each_intel_crtc(dev, crtc) { 8299 struct intel_crtc_state *crtc_state = 8300 intel_atomic_get_crtc_state(state, crtc); 8301 8302 if (IS_ERR(crtc_state)) { 8303 ret = PTR_ERR(crtc_state); 8304 goto out; 8305 } 8306 8307 if (crtc_state->hw.active) { 8308 struct intel_encoder *encoder; 8309 8310 /* 8311 * We've not yet detected sink capabilities 8312 * (audio,infoframes,etc.) and thus we don't want to 8313 * force a full state recomputation yet. We want that to 8314 * happen only for the first real commit from userspace. 8315 * So preserve the inherited flag for the time being. 8316 */ 8317 crtc_state->inherited = true; 8318 8319 ret = drm_atomic_add_affected_planes(state, &crtc->base); 8320 if (ret) 8321 goto out; 8322 8323 /* 8324 * FIXME hack to force a LUT update to avoid the 8325 * plane update forcing the pipe gamma on without 8326 * having a proper LUT loaded. Remove once we 8327 * have readout for pipe gamma enable. 8328 */ 8329 crtc_state->uapi.color_mgmt_changed = true; 8330 8331 for_each_intel_encoder_mask(dev, encoder, 8332 crtc_state->uapi.encoder_mask) { 8333 if (encoder->initial_fastset_check && 8334 !encoder->initial_fastset_check(encoder, crtc_state)) { 8335 ret = drm_atomic_add_affected_connectors(state, 8336 &crtc->base); 8337 if (ret) 8338 goto out; 8339 } 8340 } 8341 } 8342 } 8343 8344 ret = drm_atomic_commit(state); 8345 8346 out: 8347 if (ret == -EDEADLK) { 8348 drm_atomic_state_clear(state); 8349 drm_modeset_backoff(&ctx); 8350 goto retry; 8351 } 8352 8353 drm_atomic_state_put(state); 8354 8355 drm_modeset_drop_locks(&ctx); 8356 drm_modeset_acquire_fini(&ctx); 8357 8358 return ret; 8359 } 8360 8361 static const struct drm_mode_config_helper_funcs intel_mode_config_funcs = { 8362 .atomic_commit_setup = drm_dp_mst_atomic_setup_commit, 8363 }; 8364 8365 static void intel_mode_config_init(struct drm_i915_private *i915) 8366 { 8367 struct drm_mode_config *mode_config = &i915->drm.mode_config; 8368 8369 drm_mode_config_init(&i915->drm); 8370 INIT_LIST_HEAD(&i915->display.global.obj_list); 8371 8372 mode_config->min_width = 0; 8373 mode_config->min_height = 0; 8374 8375 mode_config->preferred_depth = 24; 8376 mode_config->prefer_shadow = 1; 8377 8378 mode_config->funcs = &intel_mode_funcs; 8379 mode_config->helper_private = &intel_mode_config_funcs; 8380 8381 mode_config->async_page_flip = HAS_ASYNC_FLIPS(i915); 8382 8383 /* 8384 * Maximum framebuffer dimensions, chosen to match 8385 * the maximum render engine surface size on gen4+. 8386 */ 8387 if (DISPLAY_VER(i915) >= 7) { 8388 mode_config->max_width = 16384; 8389 mode_config->max_height = 16384; 8390 } else if (DISPLAY_VER(i915) >= 4) { 8391 mode_config->max_width = 8192; 8392 mode_config->max_height = 8192; 8393 } else if (DISPLAY_VER(i915) == 3) { 8394 mode_config->max_width = 4096; 8395 mode_config->max_height = 4096; 8396 } else { 8397 mode_config->max_width = 2048; 8398 mode_config->max_height = 2048; 8399 } 8400 8401 if (IS_I845G(i915) || IS_I865G(i915)) { 8402 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512; 8403 mode_config->cursor_height = 1023; 8404 } else if (IS_I830(i915) || IS_I85X(i915) || 8405 IS_I915G(i915) || IS_I915GM(i915)) { 8406 mode_config->cursor_width = 64; 8407 mode_config->cursor_height = 64; 8408 } else { 8409 mode_config->cursor_width = 256; 8410 mode_config->cursor_height = 256; 8411 } 8412 } 8413 8414 static void intel_mode_config_cleanup(struct drm_i915_private *i915) 8415 { 8416 intel_atomic_global_obj_cleanup(i915); 8417 drm_mode_config_cleanup(&i915->drm); 8418 } 8419 8420 /* part #1: call before irq install */ 8421 int intel_modeset_init_noirq(struct drm_i915_private *i915) 8422 { 8423 int ret; 8424 8425 if (i915_inject_probe_failure(i915)) 8426 return -ENODEV; 8427 8428 if (HAS_DISPLAY(i915)) { 8429 ret = drm_vblank_init(&i915->drm, 8430 INTEL_NUM_PIPES(i915)); 8431 if (ret) 8432 return ret; 8433 } 8434 8435 intel_bios_init(i915); 8436 8437 ret = intel_vga_register(i915); 8438 if (ret) 8439 goto cleanup_bios; 8440 8441 /* FIXME: completely on the wrong abstraction layer */ 8442 ret = intel_power_domains_init(i915); 8443 if (ret < 0) 8444 goto cleanup_vga; 8445 8446 intel_power_domains_init_hw(i915, false); 8447 8448 if (!HAS_DISPLAY(i915)) 8449 return 0; 8450 8451 intel_dmc_init(i915); 8452 8453 i915->display.wq.modeset = alloc_ordered_workqueue("i915_modeset", 0); 8454 i915->display.wq.flip = alloc_workqueue("i915_flip", WQ_HIGHPRI | 8455 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE); 8456 8457 intel_mode_config_init(i915); 8458 8459 ret = intel_cdclk_init(i915); 8460 if (ret) 8461 goto cleanup_vga_client_pw_domain_dmc; 8462 8463 ret = intel_color_init(i915); 8464 if (ret) 8465 goto cleanup_vga_client_pw_domain_dmc; 8466 8467 ret = intel_dbuf_init(i915); 8468 if (ret) 8469 goto cleanup_vga_client_pw_domain_dmc; 8470 8471 ret = intel_bw_init(i915); 8472 if (ret) 8473 goto cleanup_vga_client_pw_domain_dmc; 8474 8475 init_llist_head(&i915->display.atomic_helper.free_list); 8476 INIT_WORK(&i915->display.atomic_helper.free_work, 8477 intel_atomic_helper_free_state_worker); 8478 8479 intel_init_quirks(i915); 8480 8481 intel_fbc_init(i915); 8482 8483 return 0; 8484 8485 cleanup_vga_client_pw_domain_dmc: 8486 intel_dmc_fini(i915); 8487 intel_power_domains_driver_remove(i915); 8488 cleanup_vga: 8489 intel_vga_unregister(i915); 8490 cleanup_bios: 8491 intel_bios_driver_remove(i915); 8492 8493 return ret; 8494 } 8495 8496 /* part #2: call after irq install, but before gem init */ 8497 int intel_modeset_init_nogem(struct drm_i915_private *i915) 8498 { 8499 struct drm_device *dev = &i915->drm; 8500 enum pipe pipe; 8501 struct intel_crtc *crtc; 8502 int ret; 8503 8504 if (!HAS_DISPLAY(i915)) 8505 return 0; 8506 8507 intel_wm_init(i915); 8508 8509 intel_panel_sanitize_ssc(i915); 8510 8511 intel_pps_setup(i915); 8512 8513 intel_gmbus_setup(i915); 8514 8515 drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n", 8516 INTEL_NUM_PIPES(i915), 8517 INTEL_NUM_PIPES(i915) > 1 ? "s" : ""); 8518 8519 for_each_pipe(i915, pipe) { 8520 ret = intel_crtc_init(i915, pipe); 8521 if (ret) { 8522 intel_mode_config_cleanup(i915); 8523 return ret; 8524 } 8525 } 8526 8527 intel_plane_possible_crtcs_init(i915); 8528 intel_shared_dpll_init(i915); 8529 intel_fdi_pll_freq_update(i915); 8530 8531 intel_update_czclk(i915); 8532 intel_modeset_init_hw(i915); 8533 intel_dpll_update_ref_clks(i915); 8534 8535 intel_hdcp_component_init(i915); 8536 8537 if (i915->display.cdclk.max_cdclk_freq == 0) 8538 intel_update_max_cdclk(i915); 8539 8540 intel_hti_init(i915); 8541 8542 /* Just disable it once at startup */ 8543 intel_vga_disable(i915); 8544 intel_setup_outputs(i915); 8545 8546 drm_modeset_lock_all(dev); 8547 intel_modeset_setup_hw_state(i915, dev->mode_config.acquire_ctx); 8548 intel_acpi_assign_connector_fwnodes(i915); 8549 drm_modeset_unlock_all(dev); 8550 8551 for_each_intel_crtc(dev, crtc) { 8552 if (!to_intel_crtc_state(crtc->base.state)->uapi.active) 8553 continue; 8554 intel_crtc_initial_plane_config(crtc); 8555 } 8556 8557 /* 8558 * Make sure hardware watermarks really match the state we read out. 8559 * Note that we need to do this after reconstructing the BIOS fb's 8560 * since the watermark calculation done here will use pstate->fb. 8561 */ 8562 if (!HAS_GMCH(i915)) 8563 ilk_wm_sanitize(i915); 8564 8565 return 0; 8566 } 8567 8568 /* part #3: call after gem init */ 8569 int intel_modeset_init(struct drm_i915_private *i915) 8570 { 8571 int ret; 8572 8573 if (!HAS_DISPLAY(i915)) 8574 return 0; 8575 8576 /* 8577 * Force all active planes to recompute their states. So that on 8578 * mode_setcrtc after probe, all the intel_plane_state variables 8579 * are already calculated and there is no assert_plane warnings 8580 * during bootup. 8581 */ 8582 ret = intel_initial_commit(&i915->drm); 8583 if (ret) 8584 drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret); 8585 8586 intel_overlay_setup(i915); 8587 8588 ret = intel_fbdev_init(&i915->drm); 8589 if (ret) 8590 return ret; 8591 8592 /* Only enable hotplug handling once the fbdev is fully set up. */ 8593 intel_hpd_init(i915); 8594 intel_hpd_poll_disable(i915); 8595 8596 skl_watermark_ipc_init(i915); 8597 8598 return 0; 8599 } 8600 8601 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 8602 { 8603 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 8604 /* 640x480@60Hz, ~25175 kHz */ 8605 struct dpll clock = { 8606 .m1 = 18, 8607 .m2 = 7, 8608 .p1 = 13, 8609 .p2 = 4, 8610 .n = 2, 8611 }; 8612 u32 dpll, fp; 8613 int i; 8614 8615 drm_WARN_ON(&dev_priv->drm, 8616 i9xx_calc_dpll_params(48000, &clock) != 25154); 8617 8618 drm_dbg_kms(&dev_priv->drm, 8619 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n", 8620 pipe_name(pipe), clock.vco, clock.dot); 8621 8622 fp = i9xx_dpll_compute_fp(&clock); 8623 dpll = DPLL_DVO_2X_MODE | 8624 DPLL_VGA_MODE_DIS | 8625 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | 8626 PLL_P2_DIVIDE_BY_4 | 8627 PLL_REF_INPUT_DREFCLK | 8628 DPLL_VCO_ENABLE; 8629 8630 intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16)); 8631 intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16)); 8632 intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16)); 8633 intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16)); 8634 intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16)); 8635 intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16)); 8636 intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1)); 8637 8638 intel_de_write(dev_priv, FP0(pipe), fp); 8639 intel_de_write(dev_priv, FP1(pipe), fp); 8640 8641 /* 8642 * Apparently we need to have VGA mode enabled prior to changing 8643 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 8644 * dividers, even though the register value does change. 8645 */ 8646 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); 8647 intel_de_write(dev_priv, DPLL(pipe), dpll); 8648 8649 /* Wait for the clocks to stabilize. */ 8650 intel_de_posting_read(dev_priv, DPLL(pipe)); 8651 udelay(150); 8652 8653 /* The pixel multiplier can only be updated once the 8654 * DPLL is enabled and the clocks are stable. 8655 * 8656 * So write it again. 8657 */ 8658 intel_de_write(dev_priv, DPLL(pipe), dpll); 8659 8660 /* We do this three times for luck */ 8661 for (i = 0; i < 3 ; i++) { 8662 intel_de_write(dev_priv, DPLL(pipe), dpll); 8663 intel_de_posting_read(dev_priv, DPLL(pipe)); 8664 udelay(150); /* wait for warmup */ 8665 } 8666 8667 intel_de_write(dev_priv, PIPECONF(pipe), PIPECONF_ENABLE); 8668 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 8669 8670 intel_wait_for_pipe_scanline_moving(crtc); 8671 } 8672 8673 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 8674 { 8675 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 8676 8677 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n", 8678 pipe_name(pipe)); 8679 8680 drm_WARN_ON(&dev_priv->drm, 8681 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE); 8682 drm_WARN_ON(&dev_priv->drm, 8683 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE); 8684 drm_WARN_ON(&dev_priv->drm, 8685 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE); 8686 drm_WARN_ON(&dev_priv->drm, 8687 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK); 8688 drm_WARN_ON(&dev_priv->drm, 8689 intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK); 8690 8691 intel_de_write(dev_priv, PIPECONF(pipe), 0); 8692 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 8693 8694 intel_wait_for_pipe_scanline_stopped(crtc); 8695 8696 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); 8697 intel_de_posting_read(dev_priv, DPLL(pipe)); 8698 } 8699 8700 void intel_display_resume(struct drm_device *dev) 8701 { 8702 struct drm_i915_private *i915 = to_i915(dev); 8703 struct drm_atomic_state *state = i915->display.restore.modeset_state; 8704 struct drm_modeset_acquire_ctx ctx; 8705 int ret; 8706 8707 if (!HAS_DISPLAY(i915)) 8708 return; 8709 8710 i915->display.restore.modeset_state = NULL; 8711 if (state) 8712 state->acquire_ctx = &ctx; 8713 8714 drm_modeset_acquire_init(&ctx, 0); 8715 8716 while (1) { 8717 ret = drm_modeset_lock_all_ctx(dev, &ctx); 8718 if (ret != -EDEADLK) 8719 break; 8720 8721 drm_modeset_backoff(&ctx); 8722 } 8723 8724 if (!ret) 8725 ret = __intel_display_resume(i915, state, &ctx); 8726 8727 skl_watermark_ipc_update(i915); 8728 drm_modeset_drop_locks(&ctx); 8729 drm_modeset_acquire_fini(&ctx); 8730 8731 if (ret) 8732 drm_err(&i915->drm, 8733 "Restoring old state failed with %i\n", ret); 8734 if (state) 8735 drm_atomic_state_put(state); 8736 } 8737 8738 static void intel_hpd_poll_fini(struct drm_i915_private *i915) 8739 { 8740 struct intel_connector *connector; 8741 struct drm_connector_list_iter conn_iter; 8742 8743 /* Kill all the work that may have been queued by hpd. */ 8744 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 8745 for_each_intel_connector_iter(connector, &conn_iter) { 8746 if (connector->modeset_retry_work.func) 8747 cancel_work_sync(&connector->modeset_retry_work); 8748 if (connector->hdcp.shim) { 8749 cancel_delayed_work_sync(&connector->hdcp.check_work); 8750 cancel_work_sync(&connector->hdcp.prop_work); 8751 } 8752 } 8753 drm_connector_list_iter_end(&conn_iter); 8754 } 8755 8756 /* part #1: call before irq uninstall */ 8757 void intel_modeset_driver_remove(struct drm_i915_private *i915) 8758 { 8759 if (!HAS_DISPLAY(i915)) 8760 return; 8761 8762 flush_workqueue(i915->display.wq.flip); 8763 flush_workqueue(i915->display.wq.modeset); 8764 8765 flush_work(&i915->display.atomic_helper.free_work); 8766 drm_WARN_ON(&i915->drm, !llist_empty(&i915->display.atomic_helper.free_list)); 8767 8768 /* 8769 * MST topology needs to be suspended so we don't have any calls to 8770 * fbdev after it's finalized. MST will be destroyed later as part of 8771 * drm_mode_config_cleanup() 8772 */ 8773 intel_dp_mst_suspend(i915); 8774 } 8775 8776 /* part #2: call after irq uninstall */ 8777 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915) 8778 { 8779 if (!HAS_DISPLAY(i915)) 8780 return; 8781 8782 /* 8783 * Due to the hpd irq storm handling the hotplug work can re-arm the 8784 * poll handlers. Hence disable polling after hpd handling is shut down. 8785 */ 8786 intel_hpd_poll_fini(i915); 8787 8788 /* poll work can call into fbdev, hence clean that up afterwards */ 8789 intel_fbdev_fini(i915); 8790 8791 intel_unregister_dsm_handler(); 8792 8793 /* flush any delayed tasks or pending work */ 8794 flush_scheduled_work(); 8795 8796 intel_hdcp_component_fini(i915); 8797 8798 intel_mode_config_cleanup(i915); 8799 8800 intel_overlay_cleanup(i915); 8801 8802 intel_gmbus_teardown(i915); 8803 8804 destroy_workqueue(i915->display.wq.flip); 8805 destroy_workqueue(i915->display.wq.modeset); 8806 8807 intel_fbc_cleanup(i915); 8808 } 8809 8810 /* part #3: call after gem init */ 8811 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915) 8812 { 8813 intel_dmc_fini(i915); 8814 8815 intel_power_domains_driver_remove(i915); 8816 8817 intel_vga_unregister(i915); 8818 8819 intel_bios_driver_remove(i915); 8820 } 8821 8822 bool intel_modeset_probe_defer(struct pci_dev *pdev) 8823 { 8824 struct drm_privacy_screen *privacy_screen; 8825 8826 /* 8827 * apple-gmux is needed on dual GPU MacBook Pro 8828 * to probe the panel if we're the inactive GPU. 8829 */ 8830 if (vga_switcheroo_client_probe_defer(pdev)) 8831 return true; 8832 8833 /* If the LCD panel has a privacy-screen, wait for it */ 8834 privacy_screen = drm_privacy_screen_get(&pdev->dev, NULL); 8835 if (IS_ERR(privacy_screen) && PTR_ERR(privacy_screen) == -EPROBE_DEFER) 8836 return true; 8837 8838 drm_privacy_screen_put(privacy_screen); 8839 8840 return false; 8841 } 8842 8843 void intel_display_driver_register(struct drm_i915_private *i915) 8844 { 8845 if (!HAS_DISPLAY(i915)) 8846 return; 8847 8848 intel_display_debugfs_register(i915); 8849 8850 /* Must be done after probing outputs */ 8851 intel_opregion_register(i915); 8852 intel_acpi_video_register(i915); 8853 8854 intel_audio_init(i915); 8855 8856 /* 8857 * Some ports require correctly set-up hpd registers for 8858 * detection to work properly (leading to ghost connected 8859 * connector status), e.g. VGA on gm45. Hence we can only set 8860 * up the initial fbdev config after hpd irqs are fully 8861 * enabled. We do it last so that the async config cannot run 8862 * before the connectors are registered. 8863 */ 8864 intel_fbdev_initial_config_async(i915); 8865 8866 /* 8867 * We need to coordinate the hotplugs with the asynchronous 8868 * fbdev configuration, for which we use the 8869 * fbdev->async_cookie. 8870 */ 8871 drm_kms_helper_poll_init(&i915->drm); 8872 } 8873 8874 void intel_display_driver_unregister(struct drm_i915_private *i915) 8875 { 8876 if (!HAS_DISPLAY(i915)) 8877 return; 8878 8879 intel_fbdev_unregister(i915); 8880 intel_audio_deinit(i915); 8881 8882 /* 8883 * After flushing the fbdev (incl. a late async config which 8884 * will have delayed queuing of a hotplug event), then flush 8885 * the hotplug events. 8886 */ 8887 drm_kms_helper_poll_fini(&i915->drm); 8888 drm_atomic_helper_shutdown(&i915->drm); 8889 8890 acpi_video_unregister(); 8891 intel_opregion_unregister(i915); 8892 } 8893 8894 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915) 8895 { 8896 return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915); 8897 } 8898