1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <linux/dma-resv.h> 28 #include <linux/i2c.h> 29 #include <linux/input.h> 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/slab.h> 33 #include <linux/string_helpers.h> 34 #include <linux/vga_switcheroo.h> 35 #include <acpi/video.h> 36 37 #include <drm/display/drm_dp_helper.h> 38 #include <drm/drm_atomic.h> 39 #include <drm/drm_atomic_helper.h> 40 #include <drm/drm_atomic_uapi.h> 41 #include <drm/drm_damage_helper.h> 42 #include <drm/drm_edid.h> 43 #include <drm/drm_fourcc.h> 44 #include <drm/drm_privacy_screen_consumer.h> 45 #include <drm/drm_probe_helper.h> 46 #include <drm/drm_rect.h> 47 48 #include "gem/i915_gem_lmem.h" 49 #include "gem/i915_gem_object.h" 50 51 #include "g4x_dp.h" 52 #include "g4x_hdmi.h" 53 #include "hsw_ips.h" 54 #include "i915_drv.h" 55 #include "i915_reg.h" 56 #include "i915_utils.h" 57 #include "i9xx_plane.h" 58 #include "i9xx_wm.h" 59 #include "icl_dsi.h" 60 #include "intel_acpi.h" 61 #include "intel_atomic.h" 62 #include "intel_atomic_plane.h" 63 #include "intel_audio.h" 64 #include "intel_bw.h" 65 #include "intel_cdclk.h" 66 #include "intel_color.h" 67 #include "intel_crt.h" 68 #include "intel_crtc.h" 69 #include "intel_crtc_state_dump.h" 70 #include "intel_ddi.h" 71 #include "intel_de.h" 72 #include "intel_display_debugfs.h" 73 #include "intel_display_power.h" 74 #include "intel_display_types.h" 75 #include "intel_dmc.h" 76 #include "intel_dp.h" 77 #include "intel_dp_link_training.h" 78 #include "intel_dp_mst.h" 79 #include "intel_dpio_phy.h" 80 #include "intel_dpll.h" 81 #include "intel_dpll_mgr.h" 82 #include "intel_dpt.h" 83 #include "intel_drrs.h" 84 #include "intel_dsi.h" 85 #include "intel_dvo.h" 86 #include "intel_fb.h" 87 #include "intel_fbc.h" 88 #include "intel_fbdev.h" 89 #include "intel_fdi.h" 90 #include "intel_fifo_underrun.h" 91 #include "intel_frontbuffer.h" 92 #include "intel_gmbus.h" 93 #include "intel_hdcp.h" 94 #include "intel_hdmi.h" 95 #include "intel_hotplug.h" 96 #include "intel_hti.h" 97 #include "intel_lvds.h" 98 #include "intel_lvds_regs.h" 99 #include "intel_modeset_setup.h" 100 #include "intel_modeset_verify.h" 101 #include "intel_overlay.h" 102 #include "intel_panel.h" 103 #include "intel_pch_display.h" 104 #include "intel_pch_refclk.h" 105 #include "intel_pcode.h" 106 #include "intel_pipe_crc.h" 107 #include "intel_plane_initial.h" 108 #include "intel_pm.h" 109 #include "intel_pps.h" 110 #include "intel_psr.h" 111 #include "intel_quirks.h" 112 #include "intel_sdvo.h" 113 #include "intel_snps_phy.h" 114 #include "intel_sprite.h" 115 #include "intel_tc.h" 116 #include "intel_tv.h" 117 #include "intel_vblank.h" 118 #include "intel_vdsc.h" 119 #include "intel_vga.h" 120 #include "intel_vrr.h" 121 #include "intel_wm.h" 122 #include "skl_scaler.h" 123 #include "skl_universal_plane.h" 124 #include "skl_watermark.h" 125 #include "vlv_dsi.h" 126 #include "vlv_dsi_pll.h" 127 #include "vlv_dsi_regs.h" 128 #include "vlv_sideband.h" 129 130 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state); 131 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state); 132 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state); 133 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state); 134 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state); 135 136 /* returns HPLL frequency in kHz */ 137 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) 138 { 139 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; 140 141 /* Obtain SKU information */ 142 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & 143 CCK_FUSE_HPLL_FREQ_MASK; 144 145 return vco_freq[hpll_freq] * 1000; 146 } 147 148 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 149 const char *name, u32 reg, int ref_freq) 150 { 151 u32 val; 152 int divider; 153 154 val = vlv_cck_read(dev_priv, reg); 155 divider = val & CCK_FREQUENCY_VALUES; 156 157 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != 158 (divider << CCK_FREQUENCY_STATUS_SHIFT), 159 "%s change in progress\n", name); 160 161 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); 162 } 163 164 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 165 const char *name, u32 reg) 166 { 167 int hpll; 168 169 vlv_cck_get(dev_priv); 170 171 if (dev_priv->hpll_freq == 0) 172 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); 173 174 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); 175 176 vlv_cck_put(dev_priv); 177 178 return hpll; 179 } 180 181 static void intel_update_czclk(struct drm_i915_private *dev_priv) 182 { 183 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) 184 return; 185 186 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", 187 CCK_CZ_CLOCK_CONTROL); 188 189 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", 190 dev_priv->czclk_freq); 191 } 192 193 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state) 194 { 195 return (crtc_state->active_planes & 196 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0; 197 } 198 199 /* WA Display #0827: Gen9:all */ 200 static void 201 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) 202 { 203 if (enable) 204 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 205 0, DUPS1_GATING_DIS | DUPS2_GATING_DIS); 206 else 207 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 208 DUPS1_GATING_DIS | DUPS2_GATING_DIS, 0); 209 } 210 211 /* Wa_2006604312:icl,ehl */ 212 static void 213 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 214 bool enable) 215 { 216 if (enable) 217 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 0, DPFR_GATING_DIS); 218 else 219 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), DPFR_GATING_DIS, 0); 220 } 221 222 /* Wa_1604331009:icl,jsl,ehl */ 223 static void 224 icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 225 bool enable) 226 { 227 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), CURSOR_GATING_DIS, 228 enable ? CURSOR_GATING_DIS : 0); 229 } 230 231 static bool 232 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state) 233 { 234 return crtc_state->master_transcoder != INVALID_TRANSCODER; 235 } 236 237 static bool 238 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state) 239 { 240 return crtc_state->sync_mode_slaves_mask != 0; 241 } 242 243 bool 244 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state) 245 { 246 return is_trans_port_sync_master(crtc_state) || 247 is_trans_port_sync_slave(crtc_state); 248 } 249 250 static enum pipe bigjoiner_master_pipe(const struct intel_crtc_state *crtc_state) 251 { 252 return ffs(crtc_state->bigjoiner_pipes) - 1; 253 } 254 255 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state) 256 { 257 if (crtc_state->bigjoiner_pipes) 258 return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state)); 259 else 260 return 0; 261 } 262 263 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state) 264 { 265 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 266 267 return crtc_state->bigjoiner_pipes && 268 crtc->pipe != bigjoiner_master_pipe(crtc_state); 269 } 270 271 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state) 272 { 273 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 274 275 return crtc_state->bigjoiner_pipes && 276 crtc->pipe == bigjoiner_master_pipe(crtc_state); 277 } 278 279 static int intel_bigjoiner_num_pipes(const struct intel_crtc_state *crtc_state) 280 { 281 return hweight8(crtc_state->bigjoiner_pipes); 282 } 283 284 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state) 285 { 286 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 287 288 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 289 return intel_crtc_for_pipe(i915, bigjoiner_master_pipe(crtc_state)); 290 else 291 return to_intel_crtc(crtc_state->uapi.crtc); 292 } 293 294 static void 295 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) 296 { 297 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 298 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 299 300 if (DISPLAY_VER(dev_priv) >= 4) { 301 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 302 303 /* Wait for the Pipe State to go off */ 304 if (intel_de_wait_for_clear(dev_priv, TRANSCONF(cpu_transcoder), 305 TRANSCONF_STATE_ENABLE, 100)) 306 drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n"); 307 } else { 308 intel_wait_for_pipe_scanline_stopped(crtc); 309 } 310 } 311 312 void assert_transcoder(struct drm_i915_private *dev_priv, 313 enum transcoder cpu_transcoder, bool state) 314 { 315 bool cur_state; 316 enum intel_display_power_domain power_domain; 317 intel_wakeref_t wakeref; 318 319 /* we keep both pipes enabled on 830 */ 320 if (IS_I830(dev_priv)) 321 state = true; 322 323 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 324 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 325 if (wakeref) { 326 u32 val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)); 327 cur_state = !!(val & TRANSCONF_ENABLE); 328 329 intel_display_power_put(dev_priv, power_domain, wakeref); 330 } else { 331 cur_state = false; 332 } 333 334 I915_STATE_WARN(cur_state != state, 335 "transcoder %s assertion failure (expected %s, current %s)\n", 336 transcoder_name(cpu_transcoder), 337 str_on_off(state), str_on_off(cur_state)); 338 } 339 340 static void assert_plane(struct intel_plane *plane, bool state) 341 { 342 enum pipe pipe; 343 bool cur_state; 344 345 cur_state = plane->get_hw_state(plane, &pipe); 346 347 I915_STATE_WARN(cur_state != state, 348 "%s assertion failure (expected %s, current %s)\n", 349 plane->base.name, str_on_off(state), 350 str_on_off(cur_state)); 351 } 352 353 #define assert_plane_enabled(p) assert_plane(p, true) 354 #define assert_plane_disabled(p) assert_plane(p, false) 355 356 static void assert_planes_disabled(struct intel_crtc *crtc) 357 { 358 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 359 struct intel_plane *plane; 360 361 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) 362 assert_plane_disabled(plane); 363 } 364 365 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 366 struct intel_digital_port *dig_port, 367 unsigned int expected_mask) 368 { 369 u32 port_mask; 370 i915_reg_t dpll_reg; 371 372 switch (dig_port->base.port) { 373 default: 374 MISSING_CASE(dig_port->base.port); 375 fallthrough; 376 case PORT_B: 377 port_mask = DPLL_PORTB_READY_MASK; 378 dpll_reg = DPLL(0); 379 break; 380 case PORT_C: 381 port_mask = DPLL_PORTC_READY_MASK; 382 dpll_reg = DPLL(0); 383 expected_mask <<= 4; 384 break; 385 case PORT_D: 386 port_mask = DPLL_PORTD_READY_MASK; 387 dpll_reg = DPIO_PHY_STATUS; 388 break; 389 } 390 391 if (intel_de_wait_for_register(dev_priv, dpll_reg, 392 port_mask, expected_mask, 1000)) 393 drm_WARN(&dev_priv->drm, 1, 394 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", 395 dig_port->base.base.base.id, dig_port->base.base.name, 396 intel_de_read(dev_priv, dpll_reg) & port_mask, 397 expected_mask); 398 } 399 400 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) 401 { 402 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 403 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 404 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 405 enum pipe pipe = crtc->pipe; 406 i915_reg_t reg; 407 u32 val; 408 409 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe)); 410 411 assert_planes_disabled(crtc); 412 413 /* 414 * A pipe without a PLL won't actually be able to drive bits from 415 * a plane. On ILK+ the pipe PLLs are integrated, so we don't 416 * need the check. 417 */ 418 if (HAS_GMCH(dev_priv)) { 419 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI)) 420 assert_dsi_pll_enabled(dev_priv); 421 else 422 assert_pll_enabled(dev_priv, pipe); 423 } else { 424 if (new_crtc_state->has_pch_encoder) { 425 /* if driving the PCH, we need FDI enabled */ 426 assert_fdi_rx_pll_enabled(dev_priv, 427 intel_crtc_pch_transcoder(crtc)); 428 assert_fdi_tx_pll_enabled(dev_priv, 429 (enum pipe) cpu_transcoder); 430 } 431 /* FIXME: assert CPU port conditions for SNB+ */ 432 } 433 434 /* Wa_22012358565:adl-p */ 435 if (DISPLAY_VER(dev_priv) == 13) 436 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe), 437 0, PIPE_ARB_USE_PROG_SLOTS); 438 439 reg = TRANSCONF(cpu_transcoder); 440 val = intel_de_read(dev_priv, reg); 441 if (val & TRANSCONF_ENABLE) { 442 /* we keep both pipes enabled on 830 */ 443 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv)); 444 return; 445 } 446 447 intel_de_write(dev_priv, reg, val | TRANSCONF_ENABLE); 448 intel_de_posting_read(dev_priv, reg); 449 450 /* 451 * Until the pipe starts PIPEDSL reads will return a stale value, 452 * which causes an apparent vblank timestamp jump when PIPEDSL 453 * resets to its proper value. That also messes up the frame count 454 * when it's derived from the timestamps. So let's wait for the 455 * pipe to start properly before we call drm_crtc_vblank_on() 456 */ 457 if (intel_crtc_max_vblank_count(new_crtc_state) == 0) 458 intel_wait_for_pipe_scanline_moving(crtc); 459 } 460 461 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) 462 { 463 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 464 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 465 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 466 enum pipe pipe = crtc->pipe; 467 i915_reg_t reg; 468 u32 val; 469 470 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe)); 471 472 /* 473 * Make sure planes won't keep trying to pump pixels to us, 474 * or we might hang the display. 475 */ 476 assert_planes_disabled(crtc); 477 478 reg = TRANSCONF(cpu_transcoder); 479 val = intel_de_read(dev_priv, reg); 480 if ((val & TRANSCONF_ENABLE) == 0) 481 return; 482 483 /* 484 * Double wide has implications for planes 485 * so best keep it disabled when not needed. 486 */ 487 if (old_crtc_state->double_wide) 488 val &= ~TRANSCONF_DOUBLE_WIDE; 489 490 /* Don't disable pipe or pipe PLLs if needed */ 491 if (!IS_I830(dev_priv)) 492 val &= ~TRANSCONF_ENABLE; 493 494 if (DISPLAY_VER(dev_priv) >= 14) 495 intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder), 496 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 497 else if (DISPLAY_VER(dev_priv) >= 12) 498 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 499 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 500 501 intel_de_write(dev_priv, reg, val); 502 if ((val & TRANSCONF_ENABLE) == 0) 503 intel_wait_for_pipe_off(old_crtc_state); 504 } 505 506 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) 507 { 508 unsigned int size = 0; 509 int i; 510 511 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) 512 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width; 513 514 return size; 515 } 516 517 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info) 518 { 519 unsigned int size = 0; 520 int i; 521 522 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) { 523 unsigned int plane_size; 524 525 if (rem_info->plane[i].linear) 526 plane_size = rem_info->plane[i].size; 527 else 528 plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height; 529 530 if (plane_size == 0) 531 continue; 532 533 if (rem_info->plane_alignment) 534 size = ALIGN(size, rem_info->plane_alignment); 535 536 size += plane_size; 537 } 538 539 return size; 540 } 541 542 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) 543 { 544 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 545 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 546 547 return DISPLAY_VER(dev_priv) < 4 || 548 (plane->fbc && 549 plane_state->view.gtt.type == I915_GTT_VIEW_NORMAL); 550 } 551 552 /* 553 * Convert the x/y offsets into a linear offset. 554 * Only valid with 0/180 degree rotation, which is fine since linear 555 * offset is only used with linear buffers on pre-hsw and tiled buffers 556 * with gen2/3, and 90/270 degree rotations isn't supported on any of them. 557 */ 558 u32 intel_fb_xy_to_linear(int x, int y, 559 const struct intel_plane_state *state, 560 int color_plane) 561 { 562 const struct drm_framebuffer *fb = state->hw.fb; 563 unsigned int cpp = fb->format->cpp[color_plane]; 564 unsigned int pitch = state->view.color_plane[color_plane].mapping_stride; 565 566 return y * pitch + x * cpp; 567 } 568 569 /* 570 * Add the x/y offsets derived from fb->offsets[] to the user 571 * specified plane src x/y offsets. The resulting x/y offsets 572 * specify the start of scanout from the beginning of the gtt mapping. 573 */ 574 void intel_add_fb_offsets(int *x, int *y, 575 const struct intel_plane_state *state, 576 int color_plane) 577 578 { 579 *x += state->view.color_plane[color_plane].x; 580 *y += state->view.color_plane[color_plane].y; 581 } 582 583 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 584 u32 pixel_format, u64 modifier) 585 { 586 struct intel_crtc *crtc; 587 struct intel_plane *plane; 588 589 if (!HAS_DISPLAY(dev_priv)) 590 return 0; 591 592 /* 593 * We assume the primary plane for pipe A has 594 * the highest stride limits of them all, 595 * if in case pipe A is disabled, use the first pipe from pipe_mask. 596 */ 597 crtc = intel_first_crtc(dev_priv); 598 if (!crtc) 599 return 0; 600 601 plane = to_intel_plane(crtc->base.primary); 602 603 return plane->max_stride(plane, pixel_format, modifier, 604 DRM_MODE_ROTATE_0); 605 } 606 607 void intel_set_plane_visible(struct intel_crtc_state *crtc_state, 608 struct intel_plane_state *plane_state, 609 bool visible) 610 { 611 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 612 613 plane_state->uapi.visible = visible; 614 615 if (visible) 616 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base); 617 else 618 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base); 619 } 620 621 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state) 622 { 623 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 624 struct drm_plane *plane; 625 626 /* 627 * Active_planes aliases if multiple "primary" or cursor planes 628 * have been used on the same (or wrong) pipe. plane_mask uses 629 * unique ids, hence we can use that to reconstruct active_planes. 630 */ 631 crtc_state->enabled_planes = 0; 632 crtc_state->active_planes = 0; 633 634 drm_for_each_plane_mask(plane, &dev_priv->drm, 635 crtc_state->uapi.plane_mask) { 636 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id); 637 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id); 638 } 639 } 640 641 void intel_plane_disable_noatomic(struct intel_crtc *crtc, 642 struct intel_plane *plane) 643 { 644 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 645 struct intel_crtc_state *crtc_state = 646 to_intel_crtc_state(crtc->base.state); 647 struct intel_plane_state *plane_state = 648 to_intel_plane_state(plane->base.state); 649 650 drm_dbg_kms(&dev_priv->drm, 651 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n", 652 plane->base.base.id, plane->base.name, 653 crtc->base.base.id, crtc->base.name); 654 655 intel_set_plane_visible(crtc_state, plane_state, false); 656 intel_plane_fixup_bitmasks(crtc_state); 657 crtc_state->data_rate[plane->id] = 0; 658 crtc_state->data_rate_y[plane->id] = 0; 659 crtc_state->rel_data_rate[plane->id] = 0; 660 crtc_state->rel_data_rate_y[plane->id] = 0; 661 crtc_state->min_cdclk[plane->id] = 0; 662 663 if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 && 664 hsw_ips_disable(crtc_state)) { 665 crtc_state->ips_enabled = false; 666 intel_crtc_wait_for_next_vblank(crtc); 667 } 668 669 /* 670 * Vblank time updates from the shadow to live plane control register 671 * are blocked if the memory self-refresh mode is active at that 672 * moment. So to make sure the plane gets truly disabled, disable 673 * first the self-refresh mode. The self-refresh enable bit in turn 674 * will be checked/applied by the HW only at the next frame start 675 * event which is after the vblank start event, so we need to have a 676 * wait-for-vblank between disabling the plane and the pipe. 677 */ 678 if (HAS_GMCH(dev_priv) && 679 intel_set_memory_cxsr(dev_priv, false)) 680 intel_crtc_wait_for_next_vblank(crtc); 681 682 /* 683 * Gen2 reports pipe underruns whenever all planes are disabled. 684 * So disable underrun reporting before all the planes get disabled. 685 */ 686 if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes) 687 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); 688 689 intel_plane_disable_arm(plane, crtc_state); 690 intel_crtc_wait_for_next_vblank(crtc); 691 } 692 693 unsigned int 694 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state) 695 { 696 int x = 0, y = 0; 697 698 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, 699 plane_state->view.color_plane[0].offset, 0); 700 701 return y; 702 } 703 704 static int 705 intel_display_commit_duplicated_state(struct intel_atomic_state *state, 706 struct drm_modeset_acquire_ctx *ctx) 707 { 708 struct drm_i915_private *i915 = to_i915(state->base.dev); 709 int ret; 710 711 ret = drm_atomic_helper_commit_duplicated_state(&state->base, ctx); 712 713 drm_WARN_ON(&i915->drm, ret == -EDEADLK); 714 715 return ret; 716 } 717 718 static int 719 __intel_display_resume(struct drm_i915_private *i915, 720 struct drm_atomic_state *state, 721 struct drm_modeset_acquire_ctx *ctx) 722 { 723 struct drm_crtc_state *crtc_state; 724 struct drm_crtc *crtc; 725 int i; 726 727 intel_modeset_setup_hw_state(i915, ctx); 728 intel_vga_redisable(i915); 729 730 if (!state) 731 return 0; 732 733 /* 734 * We've duplicated the state, pointers to the old state are invalid. 735 * 736 * Don't attempt to use the old state until we commit the duplicated state. 737 */ 738 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 739 /* 740 * Force recalculation even if we restore 741 * current state. With fast modeset this may not result 742 * in a modeset when the state is compatible. 743 */ 744 crtc_state->mode_changed = true; 745 } 746 747 /* ignore any reset values/BIOS leftovers in the WM registers */ 748 if (!HAS_GMCH(i915)) 749 to_intel_atomic_state(state)->skip_intermediate_wm = true; 750 751 return intel_display_commit_duplicated_state(to_intel_atomic_state(state), ctx); 752 } 753 754 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) 755 { 756 return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display && 757 intel_has_gpu_reset(to_gt(dev_priv))); 758 } 759 760 void intel_display_prepare_reset(struct drm_i915_private *dev_priv) 761 { 762 struct drm_modeset_acquire_ctx *ctx = &dev_priv->display.restore.reset_ctx; 763 struct drm_atomic_state *state; 764 int ret; 765 766 if (!HAS_DISPLAY(dev_priv)) 767 return; 768 769 /* reset doesn't touch the display */ 770 if (!dev_priv->params.force_reset_modeset_test && 771 !gpu_reset_clobbers_display(dev_priv)) 772 return; 773 774 /* We have a modeset vs reset deadlock, defensively unbreak it. */ 775 set_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags); 776 smp_mb__after_atomic(); 777 wake_up_bit(&to_gt(dev_priv)->reset.flags, I915_RESET_MODESET); 778 779 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) { 780 drm_dbg_kms(&dev_priv->drm, 781 "Modeset potentially stuck, unbreaking through wedging\n"); 782 intel_gt_set_wedged(to_gt(dev_priv)); 783 } 784 785 /* 786 * Need mode_config.mutex so that we don't 787 * trample ongoing ->detect() and whatnot. 788 */ 789 mutex_lock(&dev_priv->drm.mode_config.mutex); 790 drm_modeset_acquire_init(ctx, 0); 791 while (1) { 792 ret = drm_modeset_lock_all_ctx(&dev_priv->drm, ctx); 793 if (ret != -EDEADLK) 794 break; 795 796 drm_modeset_backoff(ctx); 797 } 798 /* 799 * Disabling the crtcs gracefully seems nicer. Also the 800 * g33 docs say we should at least disable all the planes. 801 */ 802 state = drm_atomic_helper_duplicate_state(&dev_priv->drm, ctx); 803 if (IS_ERR(state)) { 804 ret = PTR_ERR(state); 805 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n", 806 ret); 807 return; 808 } 809 810 ret = drm_atomic_helper_disable_all(&dev_priv->drm, ctx); 811 if (ret) { 812 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", 813 ret); 814 drm_atomic_state_put(state); 815 return; 816 } 817 818 dev_priv->display.restore.modeset_state = state; 819 state->acquire_ctx = ctx; 820 } 821 822 void intel_display_finish_reset(struct drm_i915_private *i915) 823 { 824 struct drm_modeset_acquire_ctx *ctx = &i915->display.restore.reset_ctx; 825 struct drm_atomic_state *state; 826 int ret; 827 828 if (!HAS_DISPLAY(i915)) 829 return; 830 831 /* reset doesn't touch the display */ 832 if (!test_bit(I915_RESET_MODESET, &to_gt(i915)->reset.flags)) 833 return; 834 835 state = fetch_and_zero(&i915->display.restore.modeset_state); 836 if (!state) 837 goto unlock; 838 839 /* reset doesn't touch the display */ 840 if (!gpu_reset_clobbers_display(i915)) { 841 /* for testing only restore the display */ 842 ret = intel_display_commit_duplicated_state(to_intel_atomic_state(state), ctx); 843 if (ret) 844 drm_err(&i915->drm, 845 "Restoring old state failed with %i\n", ret); 846 } else { 847 /* 848 * The display has been reset as well, 849 * so need a full re-initialization. 850 */ 851 intel_pps_unlock_regs_wa(i915); 852 intel_modeset_init_hw(i915); 853 intel_init_clock_gating(i915); 854 intel_hpd_init(i915); 855 856 ret = __intel_display_resume(i915, state, ctx); 857 if (ret) 858 drm_err(&i915->drm, 859 "Restoring old state failed with %i\n", ret); 860 861 intel_hpd_poll_disable(i915); 862 } 863 864 drm_atomic_state_put(state); 865 unlock: 866 drm_modeset_drop_locks(ctx); 867 drm_modeset_acquire_fini(ctx); 868 mutex_unlock(&i915->drm.mode_config.mutex); 869 870 clear_bit_unlock(I915_RESET_MODESET, &to_gt(i915)->reset.flags); 871 } 872 873 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) 874 { 875 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 876 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 877 enum pipe pipe = crtc->pipe; 878 u32 tmp; 879 880 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe)); 881 882 /* 883 * Display WA #1153: icl 884 * enable hardware to bypass the alpha math 885 * and rounding for per-pixel values 00 and 0xff 886 */ 887 tmp |= PER_PIXEL_ALPHA_BYPASS_EN; 888 /* 889 * Display WA # 1605353570: icl 890 * Set the pixel rounding bit to 1 for allowing 891 * passthrough of Frame buffer pixels unmodified 892 * across pipe 893 */ 894 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU; 895 896 /* 897 * Underrun recovery must always be disabled on display 13+. 898 * DG2 chicken bit meaning is inverted compared to other platforms. 899 */ 900 if (IS_DG2(dev_priv)) 901 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2; 902 else if (DISPLAY_VER(dev_priv) >= 13) 903 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP; 904 905 /* Wa_14010547955:dg2 */ 906 if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER)) 907 tmp |= DG2_RENDER_CCSTAG_4_3_EN; 908 909 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp); 910 } 911 912 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) 913 { 914 struct drm_crtc *crtc; 915 bool cleanup_done; 916 917 drm_for_each_crtc(crtc, &dev_priv->drm) { 918 struct drm_crtc_commit *commit; 919 spin_lock(&crtc->commit_lock); 920 commit = list_first_entry_or_null(&crtc->commit_list, 921 struct drm_crtc_commit, commit_entry); 922 cleanup_done = commit ? 923 try_wait_for_completion(&commit->cleanup_done) : true; 924 spin_unlock(&crtc->commit_lock); 925 926 if (cleanup_done) 927 continue; 928 929 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc)); 930 931 return true; 932 } 933 934 return false; 935 } 936 937 /* 938 * Finds the encoder associated with the given CRTC. This can only be 939 * used when we know that the CRTC isn't feeding multiple encoders! 940 */ 941 struct intel_encoder * 942 intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 943 const struct intel_crtc_state *crtc_state) 944 { 945 const struct drm_connector_state *connector_state; 946 const struct drm_connector *connector; 947 struct intel_encoder *encoder = NULL; 948 struct intel_crtc *master_crtc; 949 int num_encoders = 0; 950 int i; 951 952 master_crtc = intel_master_crtc(crtc_state); 953 954 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 955 if (connector_state->crtc != &master_crtc->base) 956 continue; 957 958 encoder = to_intel_encoder(connector_state->best_encoder); 959 num_encoders++; 960 } 961 962 drm_WARN(encoder->base.dev, num_encoders != 1, 963 "%d encoders for pipe %c\n", 964 num_encoders, pipe_name(master_crtc->pipe)); 965 966 return encoder; 967 } 968 969 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state) 970 { 971 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 972 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 973 const struct drm_rect *dst = &crtc_state->pch_pfit.dst; 974 enum pipe pipe = crtc->pipe; 975 int width = drm_rect_width(dst); 976 int height = drm_rect_height(dst); 977 int x = dst->x1; 978 int y = dst->y1; 979 980 if (!crtc_state->pch_pfit.enabled) 981 return; 982 983 /* Force use of hard-coded filter coefficients 984 * as some pre-programmed values are broken, 985 * e.g. x201. 986 */ 987 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) 988 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 989 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe)); 990 else 991 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 992 PF_FILTER_MED_3x3); 993 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), x << 16 | y); 994 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), width << 16 | height); 995 } 996 997 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc) 998 { 999 if (crtc->overlay) 1000 (void) intel_overlay_switch_off(crtc->overlay); 1001 1002 /* Let userspace switch the overlay on again. In most cases userspace 1003 * has to recompute where to put it anyway. 1004 */ 1005 } 1006 1007 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state) 1008 { 1009 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1010 1011 if (!crtc_state->nv12_planes) 1012 return false; 1013 1014 /* WA Display #0827: Gen9:all */ 1015 if (DISPLAY_VER(dev_priv) == 9) 1016 return true; 1017 1018 return false; 1019 } 1020 1021 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state) 1022 { 1023 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1024 1025 /* Wa_2006604312:icl,ehl */ 1026 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11) 1027 return true; 1028 1029 return false; 1030 } 1031 1032 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state) 1033 { 1034 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1035 1036 /* Wa_1604331009:icl,jsl,ehl */ 1037 if (is_hdr_mode(crtc_state) && 1038 crtc_state->active_planes & BIT(PLANE_CURSOR) && 1039 DISPLAY_VER(dev_priv) == 11) 1040 return true; 1041 1042 return false; 1043 } 1044 1045 static void intel_async_flip_vtd_wa(struct drm_i915_private *i915, 1046 enum pipe pipe, bool enable) 1047 { 1048 if (DISPLAY_VER(i915) == 9) { 1049 /* 1050 * "Plane N strech max must be programmed to 11b (x1) 1051 * when Async flips are enabled on that plane." 1052 */ 1053 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 1054 SKL_PLANE1_STRETCH_MAX_MASK, 1055 enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8); 1056 } else { 1057 /* Also needed on HSW/BDW albeit undocumented */ 1058 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 1059 HSW_PRI_STRETCH_MAX_MASK, 1060 enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8); 1061 } 1062 } 1063 1064 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state) 1065 { 1066 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1067 1068 return crtc_state->uapi.async_flip && i915_vtd_active(i915) && 1069 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915)); 1070 } 1071 1072 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state, 1073 const struct intel_crtc_state *new_crtc_state) 1074 { 1075 return (!old_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)) && 1076 new_crtc_state->active_planes; 1077 } 1078 1079 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state, 1080 const struct intel_crtc_state *new_crtc_state) 1081 { 1082 return old_crtc_state->active_planes && 1083 (!new_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)); 1084 } 1085 1086 static void intel_post_plane_update(struct intel_atomic_state *state, 1087 struct intel_crtc *crtc) 1088 { 1089 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1090 const struct intel_crtc_state *old_crtc_state = 1091 intel_atomic_get_old_crtc_state(state, crtc); 1092 const struct intel_crtc_state *new_crtc_state = 1093 intel_atomic_get_new_crtc_state(state, crtc); 1094 enum pipe pipe = crtc->pipe; 1095 1096 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); 1097 1098 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) 1099 intel_update_watermarks(dev_priv); 1100 1101 intel_fbc_post_update(state, crtc); 1102 1103 if (needs_async_flip_vtd_wa(old_crtc_state) && 1104 !needs_async_flip_vtd_wa(new_crtc_state)) 1105 intel_async_flip_vtd_wa(dev_priv, pipe, false); 1106 1107 if (needs_nv12_wa(old_crtc_state) && 1108 !needs_nv12_wa(new_crtc_state)) 1109 skl_wa_827(dev_priv, pipe, false); 1110 1111 if (needs_scalerclk_wa(old_crtc_state) && 1112 !needs_scalerclk_wa(new_crtc_state)) 1113 icl_wa_scalerclkgating(dev_priv, pipe, false); 1114 1115 if (needs_cursorclk_wa(old_crtc_state) && 1116 !needs_cursorclk_wa(new_crtc_state)) 1117 icl_wa_cursorclkgating(dev_priv, pipe, false); 1118 } 1119 1120 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state, 1121 struct intel_crtc *crtc) 1122 { 1123 const struct intel_crtc_state *crtc_state = 1124 intel_atomic_get_new_crtc_state(state, crtc); 1125 u8 update_planes = crtc_state->update_planes; 1126 const struct intel_plane_state *plane_state; 1127 struct intel_plane *plane; 1128 int i; 1129 1130 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1131 if (plane->pipe == crtc->pipe && 1132 update_planes & BIT(plane->id)) 1133 plane->enable_flip_done(plane); 1134 } 1135 } 1136 1137 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state, 1138 struct intel_crtc *crtc) 1139 { 1140 const struct intel_crtc_state *crtc_state = 1141 intel_atomic_get_new_crtc_state(state, crtc); 1142 u8 update_planes = crtc_state->update_planes; 1143 const struct intel_plane_state *plane_state; 1144 struct intel_plane *plane; 1145 int i; 1146 1147 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1148 if (plane->pipe == crtc->pipe && 1149 update_planes & BIT(plane->id)) 1150 plane->disable_flip_done(plane); 1151 } 1152 } 1153 1154 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state, 1155 struct intel_crtc *crtc) 1156 { 1157 const struct intel_crtc_state *old_crtc_state = 1158 intel_atomic_get_old_crtc_state(state, crtc); 1159 const struct intel_crtc_state *new_crtc_state = 1160 intel_atomic_get_new_crtc_state(state, crtc); 1161 u8 disable_async_flip_planes = old_crtc_state->async_flip_planes & 1162 ~new_crtc_state->async_flip_planes; 1163 const struct intel_plane_state *old_plane_state; 1164 struct intel_plane *plane; 1165 bool need_vbl_wait = false; 1166 int i; 1167 1168 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1169 if (plane->need_async_flip_disable_wa && 1170 plane->pipe == crtc->pipe && 1171 disable_async_flip_planes & BIT(plane->id)) { 1172 /* 1173 * Apart from the async flip bit we want to 1174 * preserve the old state for the plane. 1175 */ 1176 plane->async_flip(plane, old_crtc_state, 1177 old_plane_state, false); 1178 need_vbl_wait = true; 1179 } 1180 } 1181 1182 if (need_vbl_wait) 1183 intel_crtc_wait_for_next_vblank(crtc); 1184 } 1185 1186 static void intel_pre_plane_update(struct intel_atomic_state *state, 1187 struct intel_crtc *crtc) 1188 { 1189 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1190 const struct intel_crtc_state *old_crtc_state = 1191 intel_atomic_get_old_crtc_state(state, crtc); 1192 const struct intel_crtc_state *new_crtc_state = 1193 intel_atomic_get_new_crtc_state(state, crtc); 1194 enum pipe pipe = crtc->pipe; 1195 1196 intel_drrs_deactivate(old_crtc_state); 1197 1198 intel_psr_pre_plane_update(state, crtc); 1199 1200 if (hsw_ips_pre_update(state, crtc)) 1201 intel_crtc_wait_for_next_vblank(crtc); 1202 1203 if (intel_fbc_pre_update(state, crtc)) 1204 intel_crtc_wait_for_next_vblank(crtc); 1205 1206 if (!needs_async_flip_vtd_wa(old_crtc_state) && 1207 needs_async_flip_vtd_wa(new_crtc_state)) 1208 intel_async_flip_vtd_wa(dev_priv, pipe, true); 1209 1210 /* Display WA 827 */ 1211 if (!needs_nv12_wa(old_crtc_state) && 1212 needs_nv12_wa(new_crtc_state)) 1213 skl_wa_827(dev_priv, pipe, true); 1214 1215 /* Wa_2006604312:icl,ehl */ 1216 if (!needs_scalerclk_wa(old_crtc_state) && 1217 needs_scalerclk_wa(new_crtc_state)) 1218 icl_wa_scalerclkgating(dev_priv, pipe, true); 1219 1220 /* Wa_1604331009:icl,jsl,ehl */ 1221 if (!needs_cursorclk_wa(old_crtc_state) && 1222 needs_cursorclk_wa(new_crtc_state)) 1223 icl_wa_cursorclkgating(dev_priv, pipe, true); 1224 1225 /* 1226 * Vblank time updates from the shadow to live plane control register 1227 * are blocked if the memory self-refresh mode is active at that 1228 * moment. So to make sure the plane gets truly disabled, disable 1229 * first the self-refresh mode. The self-refresh enable bit in turn 1230 * will be checked/applied by the HW only at the next frame start 1231 * event which is after the vblank start event, so we need to have a 1232 * wait-for-vblank between disabling the plane and the pipe. 1233 */ 1234 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active && 1235 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) 1236 intel_crtc_wait_for_next_vblank(crtc); 1237 1238 /* 1239 * IVB workaround: must disable low power watermarks for at least 1240 * one frame before enabling scaling. LP watermarks can be re-enabled 1241 * when scaling is disabled. 1242 * 1243 * WaCxSRDisabledForSpriteScaling:ivb 1244 */ 1245 if (old_crtc_state->hw.active && 1246 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv)) 1247 intel_crtc_wait_for_next_vblank(crtc); 1248 1249 /* 1250 * If we're doing a modeset we don't need to do any 1251 * pre-vblank watermark programming here. 1252 */ 1253 if (!intel_crtc_needs_modeset(new_crtc_state)) { 1254 /* 1255 * For platforms that support atomic watermarks, program the 1256 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these 1257 * will be the intermediate values that are safe for both pre- and 1258 * post- vblank; when vblank happens, the 'active' values will be set 1259 * to the final 'target' values and we'll do this again to get the 1260 * optimal watermarks. For gen9+ platforms, the values we program here 1261 * will be the final target values which will get automatically latched 1262 * at vblank time; no further programming will be necessary. 1263 * 1264 * If a platform hasn't been transitioned to atomic watermarks yet, 1265 * we'll continue to update watermarks the old way, if flags tell 1266 * us to. 1267 */ 1268 if (!intel_initial_watermarks(state, crtc)) 1269 if (new_crtc_state->update_wm_pre) 1270 intel_update_watermarks(dev_priv); 1271 } 1272 1273 /* 1274 * Gen2 reports pipe underruns whenever all planes are disabled. 1275 * So disable underrun reporting before all the planes get disabled. 1276 * 1277 * We do this after .initial_watermarks() so that we have a 1278 * chance of catching underruns with the intermediate watermarks 1279 * vs. the old plane configuration. 1280 */ 1281 if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state)) 1282 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1283 1284 /* 1285 * WA for platforms where async address update enable bit 1286 * is double buffered and only latched at start of vblank. 1287 */ 1288 if (old_crtc_state->async_flip_planes & ~new_crtc_state->async_flip_planes) 1289 intel_crtc_async_flip_disable_wa(state, crtc); 1290 } 1291 1292 static void intel_crtc_disable_planes(struct intel_atomic_state *state, 1293 struct intel_crtc *crtc) 1294 { 1295 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1296 const struct intel_crtc_state *new_crtc_state = 1297 intel_atomic_get_new_crtc_state(state, crtc); 1298 unsigned int update_mask = new_crtc_state->update_planes; 1299 const struct intel_plane_state *old_plane_state; 1300 struct intel_plane *plane; 1301 unsigned fb_bits = 0; 1302 int i; 1303 1304 intel_crtc_dpms_overlay_disable(crtc); 1305 1306 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1307 if (crtc->pipe != plane->pipe || 1308 !(update_mask & BIT(plane->id))) 1309 continue; 1310 1311 intel_plane_disable_arm(plane, new_crtc_state); 1312 1313 if (old_plane_state->uapi.visible) 1314 fb_bits |= plane->frontbuffer_bit; 1315 } 1316 1317 intel_frontbuffer_flip(dev_priv, fb_bits); 1318 } 1319 1320 /* 1321 * intel_connector_primary_encoder - get the primary encoder for a connector 1322 * @connector: connector for which to return the encoder 1323 * 1324 * Returns the primary encoder for a connector. There is a 1:1 mapping from 1325 * all connectors to their encoder, except for DP-MST connectors which have 1326 * both a virtual and a primary encoder. These DP-MST primary encoders can be 1327 * pointed to by as many DP-MST connectors as there are pipes. 1328 */ 1329 static struct intel_encoder * 1330 intel_connector_primary_encoder(struct intel_connector *connector) 1331 { 1332 struct intel_encoder *encoder; 1333 1334 if (connector->mst_port) 1335 return &dp_to_dig_port(connector->mst_port)->base; 1336 1337 encoder = intel_attached_encoder(connector); 1338 drm_WARN_ON(connector->base.dev, !encoder); 1339 1340 return encoder; 1341 } 1342 1343 static void intel_encoders_update_prepare(struct intel_atomic_state *state) 1344 { 1345 struct drm_i915_private *i915 = to_i915(state->base.dev); 1346 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 1347 struct intel_crtc *crtc; 1348 struct drm_connector_state *new_conn_state; 1349 struct drm_connector *connector; 1350 int i; 1351 1352 /* 1353 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits. 1354 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook. 1355 */ 1356 if (i915->display.dpll.mgr) { 1357 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1358 if (intel_crtc_needs_modeset(new_crtc_state)) 1359 continue; 1360 1361 new_crtc_state->shared_dpll = old_crtc_state->shared_dpll; 1362 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state; 1363 } 1364 } 1365 1366 if (!state->modeset) 1367 return; 1368 1369 for_each_new_connector_in_state(&state->base, connector, new_conn_state, 1370 i) { 1371 struct intel_connector *intel_connector; 1372 struct intel_encoder *encoder; 1373 struct intel_crtc *crtc; 1374 1375 if (!intel_connector_needs_modeset(state, connector)) 1376 continue; 1377 1378 intel_connector = to_intel_connector(connector); 1379 encoder = intel_connector_primary_encoder(intel_connector); 1380 if (!encoder->update_prepare) 1381 continue; 1382 1383 crtc = new_conn_state->crtc ? 1384 to_intel_crtc(new_conn_state->crtc) : NULL; 1385 encoder->update_prepare(state, encoder, crtc); 1386 } 1387 } 1388 1389 static void intel_encoders_update_complete(struct intel_atomic_state *state) 1390 { 1391 struct drm_connector_state *new_conn_state; 1392 struct drm_connector *connector; 1393 int i; 1394 1395 if (!state->modeset) 1396 return; 1397 1398 for_each_new_connector_in_state(&state->base, connector, new_conn_state, 1399 i) { 1400 struct intel_connector *intel_connector; 1401 struct intel_encoder *encoder; 1402 struct intel_crtc *crtc; 1403 1404 if (!intel_connector_needs_modeset(state, connector)) 1405 continue; 1406 1407 intel_connector = to_intel_connector(connector); 1408 encoder = intel_connector_primary_encoder(intel_connector); 1409 if (!encoder->update_complete) 1410 continue; 1411 1412 crtc = new_conn_state->crtc ? 1413 to_intel_crtc(new_conn_state->crtc) : NULL; 1414 encoder->update_complete(state, encoder, crtc); 1415 } 1416 } 1417 1418 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state, 1419 struct intel_crtc *crtc) 1420 { 1421 const struct intel_crtc_state *crtc_state = 1422 intel_atomic_get_new_crtc_state(state, crtc); 1423 const struct drm_connector_state *conn_state; 1424 struct drm_connector *conn; 1425 int i; 1426 1427 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1428 struct intel_encoder *encoder = 1429 to_intel_encoder(conn_state->best_encoder); 1430 1431 if (conn_state->crtc != &crtc->base) 1432 continue; 1433 1434 if (encoder->pre_pll_enable) 1435 encoder->pre_pll_enable(state, encoder, 1436 crtc_state, conn_state); 1437 } 1438 } 1439 1440 static void intel_encoders_pre_enable(struct intel_atomic_state *state, 1441 struct intel_crtc *crtc) 1442 { 1443 const struct intel_crtc_state *crtc_state = 1444 intel_atomic_get_new_crtc_state(state, crtc); 1445 const struct drm_connector_state *conn_state; 1446 struct drm_connector *conn; 1447 int i; 1448 1449 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1450 struct intel_encoder *encoder = 1451 to_intel_encoder(conn_state->best_encoder); 1452 1453 if (conn_state->crtc != &crtc->base) 1454 continue; 1455 1456 if (encoder->pre_enable) 1457 encoder->pre_enable(state, encoder, 1458 crtc_state, conn_state); 1459 } 1460 } 1461 1462 static void intel_encoders_enable(struct intel_atomic_state *state, 1463 struct intel_crtc *crtc) 1464 { 1465 const struct intel_crtc_state *crtc_state = 1466 intel_atomic_get_new_crtc_state(state, crtc); 1467 const struct drm_connector_state *conn_state; 1468 struct drm_connector *conn; 1469 int i; 1470 1471 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1472 struct intel_encoder *encoder = 1473 to_intel_encoder(conn_state->best_encoder); 1474 1475 if (conn_state->crtc != &crtc->base) 1476 continue; 1477 1478 if (encoder->enable) 1479 encoder->enable(state, encoder, 1480 crtc_state, conn_state); 1481 intel_opregion_notify_encoder(encoder, true); 1482 } 1483 } 1484 1485 static void intel_encoders_disable(struct intel_atomic_state *state, 1486 struct intel_crtc *crtc) 1487 { 1488 const struct intel_crtc_state *old_crtc_state = 1489 intel_atomic_get_old_crtc_state(state, crtc); 1490 const struct drm_connector_state *old_conn_state; 1491 struct drm_connector *conn; 1492 int i; 1493 1494 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1495 struct intel_encoder *encoder = 1496 to_intel_encoder(old_conn_state->best_encoder); 1497 1498 if (old_conn_state->crtc != &crtc->base) 1499 continue; 1500 1501 intel_opregion_notify_encoder(encoder, false); 1502 if (encoder->disable) 1503 encoder->disable(state, encoder, 1504 old_crtc_state, old_conn_state); 1505 } 1506 } 1507 1508 static void intel_encoders_post_disable(struct intel_atomic_state *state, 1509 struct intel_crtc *crtc) 1510 { 1511 const struct intel_crtc_state *old_crtc_state = 1512 intel_atomic_get_old_crtc_state(state, crtc); 1513 const struct drm_connector_state *old_conn_state; 1514 struct drm_connector *conn; 1515 int i; 1516 1517 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1518 struct intel_encoder *encoder = 1519 to_intel_encoder(old_conn_state->best_encoder); 1520 1521 if (old_conn_state->crtc != &crtc->base) 1522 continue; 1523 1524 if (encoder->post_disable) 1525 encoder->post_disable(state, encoder, 1526 old_crtc_state, old_conn_state); 1527 } 1528 } 1529 1530 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state, 1531 struct intel_crtc *crtc) 1532 { 1533 const struct intel_crtc_state *old_crtc_state = 1534 intel_atomic_get_old_crtc_state(state, crtc); 1535 const struct drm_connector_state *old_conn_state; 1536 struct drm_connector *conn; 1537 int i; 1538 1539 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1540 struct intel_encoder *encoder = 1541 to_intel_encoder(old_conn_state->best_encoder); 1542 1543 if (old_conn_state->crtc != &crtc->base) 1544 continue; 1545 1546 if (encoder->post_pll_disable) 1547 encoder->post_pll_disable(state, encoder, 1548 old_crtc_state, old_conn_state); 1549 } 1550 } 1551 1552 static void intel_encoders_update_pipe(struct intel_atomic_state *state, 1553 struct intel_crtc *crtc) 1554 { 1555 const struct intel_crtc_state *crtc_state = 1556 intel_atomic_get_new_crtc_state(state, crtc); 1557 const struct drm_connector_state *conn_state; 1558 struct drm_connector *conn; 1559 int i; 1560 1561 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1562 struct intel_encoder *encoder = 1563 to_intel_encoder(conn_state->best_encoder); 1564 1565 if (conn_state->crtc != &crtc->base) 1566 continue; 1567 1568 if (encoder->update_pipe) 1569 encoder->update_pipe(state, encoder, 1570 crtc_state, conn_state); 1571 } 1572 } 1573 1574 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state) 1575 { 1576 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1577 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 1578 1579 plane->disable_arm(plane, crtc_state); 1580 } 1581 1582 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1583 { 1584 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1585 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1586 1587 if (crtc_state->has_pch_encoder) { 1588 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1589 &crtc_state->fdi_m_n); 1590 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1591 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1592 &crtc_state->dp_m_n); 1593 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1594 &crtc_state->dp_m2_n2); 1595 } 1596 1597 intel_set_transcoder_timings(crtc_state); 1598 1599 ilk_set_pipeconf(crtc_state); 1600 } 1601 1602 static void ilk_crtc_enable(struct intel_atomic_state *state, 1603 struct intel_crtc *crtc) 1604 { 1605 const struct intel_crtc_state *new_crtc_state = 1606 intel_atomic_get_new_crtc_state(state, crtc); 1607 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1608 enum pipe pipe = crtc->pipe; 1609 1610 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1611 return; 1612 1613 /* 1614 * Sometimes spurious CPU pipe underruns happen during FDI 1615 * training, at least with VGA+HDMI cloning. Suppress them. 1616 * 1617 * On ILK we get an occasional spurious CPU pipe underruns 1618 * between eDP port A enable and vdd enable. Also PCH port 1619 * enable seems to result in the occasional CPU pipe underrun. 1620 * 1621 * Spurious PCH underruns also occur during PCH enabling. 1622 */ 1623 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1624 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 1625 1626 ilk_configure_cpu_transcoder(new_crtc_state); 1627 1628 intel_set_pipe_src_size(new_crtc_state); 1629 1630 crtc->active = true; 1631 1632 intel_encoders_pre_enable(state, crtc); 1633 1634 if (new_crtc_state->has_pch_encoder) { 1635 ilk_pch_pre_enable(state, crtc); 1636 } else { 1637 assert_fdi_tx_disabled(dev_priv, pipe); 1638 assert_fdi_rx_disabled(dev_priv, pipe); 1639 } 1640 1641 ilk_pfit_enable(new_crtc_state); 1642 1643 /* 1644 * On ILK+ LUT must be loaded before the pipe is running but with 1645 * clocks enabled 1646 */ 1647 intel_color_load_luts(new_crtc_state); 1648 intel_color_commit_noarm(new_crtc_state); 1649 intel_color_commit_arm(new_crtc_state); 1650 /* update DSPCNTR to configure gamma for pipe bottom color */ 1651 intel_disable_primary_plane(new_crtc_state); 1652 1653 intel_initial_watermarks(state, crtc); 1654 intel_enable_transcoder(new_crtc_state); 1655 1656 if (new_crtc_state->has_pch_encoder) 1657 ilk_pch_enable(state, crtc); 1658 1659 intel_crtc_vblank_on(new_crtc_state); 1660 1661 intel_encoders_enable(state, crtc); 1662 1663 if (HAS_PCH_CPT(dev_priv)) 1664 intel_wait_for_pipe_scanline_moving(crtc); 1665 1666 /* 1667 * Must wait for vblank to avoid spurious PCH FIFO underruns. 1668 * And a second vblank wait is needed at least on ILK with 1669 * some interlaced HDMI modes. Let's do the double wait always 1670 * in case there are more corner cases we don't know about. 1671 */ 1672 if (new_crtc_state->has_pch_encoder) { 1673 intel_crtc_wait_for_next_vblank(crtc); 1674 intel_crtc_wait_for_next_vblank(crtc); 1675 } 1676 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1677 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 1678 } 1679 1680 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, 1681 enum pipe pipe, bool apply) 1682 { 1683 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)); 1684 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS; 1685 1686 if (apply) 1687 val |= mask; 1688 else 1689 val &= ~mask; 1690 1691 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val); 1692 } 1693 1694 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state) 1695 { 1696 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1697 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1698 1699 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe), 1700 HSW_LINETIME(crtc_state->linetime) | 1701 HSW_IPS_LINETIME(crtc_state->ips_linetime)); 1702 } 1703 1704 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) 1705 { 1706 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1707 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1708 enum transcoder transcoder = crtc_state->cpu_transcoder; 1709 i915_reg_t reg = DISPLAY_VER(dev_priv) >= 14 ? MTL_CHICKEN_TRANS(transcoder) : 1710 CHICKEN_TRANS(transcoder); 1711 1712 intel_de_rmw(dev_priv, reg, 1713 HSW_FRAME_START_DELAY_MASK, 1714 HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1)); 1715 } 1716 1717 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state, 1718 const struct intel_crtc_state *crtc_state) 1719 { 1720 struct intel_crtc *master_crtc = intel_master_crtc(crtc_state); 1721 1722 /* 1723 * Enable sequence steps 1-7 on bigjoiner master 1724 */ 1725 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1726 intel_encoders_pre_pll_enable(state, master_crtc); 1727 1728 if (crtc_state->shared_dpll) 1729 intel_enable_shared_dpll(crtc_state); 1730 1731 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1732 intel_encoders_pre_enable(state, master_crtc); 1733 } 1734 1735 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1736 { 1737 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1738 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1739 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1740 1741 if (crtc_state->has_pch_encoder) { 1742 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1743 &crtc_state->fdi_m_n); 1744 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1745 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1746 &crtc_state->dp_m_n); 1747 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1748 &crtc_state->dp_m2_n2); 1749 } 1750 1751 intel_set_transcoder_timings(crtc_state); 1752 1753 if (cpu_transcoder != TRANSCODER_EDP) 1754 intel_de_write(dev_priv, TRANS_MULT(cpu_transcoder), 1755 crtc_state->pixel_multiplier - 1); 1756 1757 hsw_set_frame_start_delay(crtc_state); 1758 1759 hsw_set_transconf(crtc_state); 1760 } 1761 1762 static void hsw_crtc_enable(struct intel_atomic_state *state, 1763 struct intel_crtc *crtc) 1764 { 1765 const struct intel_crtc_state *new_crtc_state = 1766 intel_atomic_get_new_crtc_state(state, crtc); 1767 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1768 enum pipe pipe = crtc->pipe, hsw_workaround_pipe; 1769 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 1770 bool psl_clkgate_wa; 1771 1772 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1773 return; 1774 1775 intel_dmc_enable_pipe(dev_priv, crtc->pipe); 1776 1777 if (!new_crtc_state->bigjoiner_pipes) { 1778 intel_encoders_pre_pll_enable(state, crtc); 1779 1780 if (new_crtc_state->shared_dpll) 1781 intel_enable_shared_dpll(new_crtc_state); 1782 1783 intel_encoders_pre_enable(state, crtc); 1784 } else { 1785 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state); 1786 } 1787 1788 intel_dsc_enable(new_crtc_state); 1789 1790 if (DISPLAY_VER(dev_priv) >= 13) 1791 intel_uncompressed_joiner_enable(new_crtc_state); 1792 1793 intel_set_pipe_src_size(new_crtc_state); 1794 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 1795 bdw_set_pipemisc(new_crtc_state); 1796 1797 if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) && 1798 !transcoder_is_dsi(cpu_transcoder)) 1799 hsw_configure_cpu_transcoder(new_crtc_state); 1800 1801 crtc->active = true; 1802 1803 /* Display WA #1180: WaDisableScalarClockGating: glk */ 1804 psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 && 1805 new_crtc_state->pch_pfit.enabled; 1806 if (psl_clkgate_wa) 1807 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true); 1808 1809 if (DISPLAY_VER(dev_priv) >= 9) 1810 skl_pfit_enable(new_crtc_state); 1811 else 1812 ilk_pfit_enable(new_crtc_state); 1813 1814 /* 1815 * On ILK+ LUT must be loaded before the pipe is running but with 1816 * clocks enabled 1817 */ 1818 intel_color_load_luts(new_crtc_state); 1819 intel_color_commit_noarm(new_crtc_state); 1820 intel_color_commit_arm(new_crtc_state); 1821 /* update DSPCNTR to configure gamma/csc for pipe bottom color */ 1822 if (DISPLAY_VER(dev_priv) < 9) 1823 intel_disable_primary_plane(new_crtc_state); 1824 1825 hsw_set_linetime_wm(new_crtc_state); 1826 1827 if (DISPLAY_VER(dev_priv) >= 11) 1828 icl_set_pipe_chicken(new_crtc_state); 1829 1830 intel_initial_watermarks(state, crtc); 1831 1832 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 1833 intel_crtc_vblank_on(new_crtc_state); 1834 1835 intel_encoders_enable(state, crtc); 1836 1837 if (psl_clkgate_wa) { 1838 intel_crtc_wait_for_next_vblank(crtc); 1839 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false); 1840 } 1841 1842 /* If we change the relative order between pipe/planes enabling, we need 1843 * to change the workaround. */ 1844 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe; 1845 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { 1846 struct intel_crtc *wa_crtc; 1847 1848 wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe); 1849 1850 intel_crtc_wait_for_next_vblank(wa_crtc); 1851 intel_crtc_wait_for_next_vblank(wa_crtc); 1852 } 1853 } 1854 1855 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state) 1856 { 1857 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1858 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1859 enum pipe pipe = crtc->pipe; 1860 1861 /* To avoid upsetting the power well on haswell only disable the pfit if 1862 * it's in use. The hw state code will make sure we get this right. */ 1863 if (!old_crtc_state->pch_pfit.enabled) 1864 return; 1865 1866 intel_de_write_fw(dev_priv, PF_CTL(pipe), 0); 1867 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0); 1868 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0); 1869 } 1870 1871 static void ilk_crtc_disable(struct intel_atomic_state *state, 1872 struct intel_crtc *crtc) 1873 { 1874 const struct intel_crtc_state *old_crtc_state = 1875 intel_atomic_get_old_crtc_state(state, crtc); 1876 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1877 enum pipe pipe = crtc->pipe; 1878 1879 /* 1880 * Sometimes spurious CPU pipe underruns happen when the 1881 * pipe is already disabled, but FDI RX/TX is still enabled. 1882 * Happens at least with VGA+HDMI cloning. Suppress them. 1883 */ 1884 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1885 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 1886 1887 intel_encoders_disable(state, crtc); 1888 1889 intel_crtc_vblank_off(old_crtc_state); 1890 1891 intel_disable_transcoder(old_crtc_state); 1892 1893 ilk_pfit_disable(old_crtc_state); 1894 1895 if (old_crtc_state->has_pch_encoder) 1896 ilk_pch_disable(state, crtc); 1897 1898 intel_encoders_post_disable(state, crtc); 1899 1900 if (old_crtc_state->has_pch_encoder) 1901 ilk_pch_post_disable(state, crtc); 1902 1903 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1904 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 1905 } 1906 1907 static void hsw_crtc_disable(struct intel_atomic_state *state, 1908 struct intel_crtc *crtc) 1909 { 1910 const struct intel_crtc_state *old_crtc_state = 1911 intel_atomic_get_old_crtc_state(state, crtc); 1912 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 1913 1914 /* 1915 * FIXME collapse everything to one hook. 1916 * Need care with mst->ddi interactions. 1917 */ 1918 if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) { 1919 intel_encoders_disable(state, crtc); 1920 intel_encoders_post_disable(state, crtc); 1921 } 1922 1923 intel_dmc_disable_pipe(i915, crtc->pipe); 1924 } 1925 1926 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) 1927 { 1928 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1929 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1930 1931 if (!crtc_state->gmch_pfit.control) 1932 return; 1933 1934 /* 1935 * The panel fitter should only be adjusted whilst the pipe is disabled, 1936 * according to register description and PRM. 1937 */ 1938 drm_WARN_ON(&dev_priv->drm, 1939 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE); 1940 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 1941 1942 intel_de_write(dev_priv, PFIT_PGM_RATIOS, 1943 crtc_state->gmch_pfit.pgm_ratios); 1944 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control); 1945 1946 /* Border color in case we don't scale up to the full screen. Black by 1947 * default, change to something else for debugging. */ 1948 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); 1949 } 1950 1951 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) 1952 { 1953 if (phy == PHY_NONE) 1954 return false; 1955 else if (IS_ALDERLAKE_S(dev_priv)) 1956 return phy <= PHY_E; 1957 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) 1958 return phy <= PHY_D; 1959 else if (IS_JSL_EHL(dev_priv)) 1960 return phy <= PHY_C; 1961 else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12)) 1962 return phy <= PHY_B; 1963 else 1964 /* 1965 * DG2 outputs labelled as "combo PHY" in the bspec use 1966 * SNPS PHYs with completely different programming, 1967 * hence we always return false here. 1968 */ 1969 return false; 1970 } 1971 1972 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) 1973 { 1974 if (IS_DG2(dev_priv)) 1975 /* DG2's "TC1" output uses a SNPS PHY */ 1976 return false; 1977 else if (IS_ALDERLAKE_P(dev_priv)) 1978 return phy >= PHY_F && phy <= PHY_I; 1979 else if (IS_TIGERLAKE(dev_priv)) 1980 return phy >= PHY_D && phy <= PHY_I; 1981 else if (IS_ICELAKE(dev_priv)) 1982 return phy >= PHY_C && phy <= PHY_F; 1983 else 1984 return false; 1985 } 1986 1987 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy) 1988 { 1989 if (phy == PHY_NONE) 1990 return false; 1991 else if (IS_DG2(dev_priv)) 1992 /* 1993 * All four "combo" ports and the TC1 port (PHY E) use 1994 * Synopsis PHYs. 1995 */ 1996 return phy <= PHY_E; 1997 1998 return false; 1999 } 2000 2001 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) 2002 { 2003 if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD) 2004 return PHY_D + port - PORT_D_XELPD; 2005 else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1) 2006 return PHY_F + port - PORT_TC1; 2007 else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1) 2008 return PHY_B + port - PORT_TC1; 2009 else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1) 2010 return PHY_C + port - PORT_TC1; 2011 else if (IS_JSL_EHL(i915) && port == PORT_D) 2012 return PHY_A; 2013 2014 return PHY_A + port - PORT_A; 2015 } 2016 2017 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) 2018 { 2019 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port))) 2020 return TC_PORT_NONE; 2021 2022 if (DISPLAY_VER(dev_priv) >= 12) 2023 return TC_PORT_1 + port - PORT_TC1; 2024 else 2025 return TC_PORT_1 + port - PORT_C; 2026 } 2027 2028 enum intel_display_power_domain 2029 intel_aux_power_domain(struct intel_digital_port *dig_port) 2030 { 2031 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 2032 2033 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 2034 return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch); 2035 2036 return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch); 2037 } 2038 2039 static void get_crtc_power_domains(struct intel_crtc_state *crtc_state, 2040 struct intel_power_domain_mask *mask) 2041 { 2042 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2043 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2044 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2045 struct drm_encoder *encoder; 2046 enum pipe pipe = crtc->pipe; 2047 2048 bitmap_zero(mask->bits, POWER_DOMAIN_NUM); 2049 2050 if (!crtc_state->hw.active) 2051 return; 2052 2053 set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits); 2054 set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits); 2055 if (crtc_state->pch_pfit.enabled || 2056 crtc_state->pch_pfit.force_thru) 2057 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits); 2058 2059 drm_for_each_encoder_mask(encoder, &dev_priv->drm, 2060 crtc_state->uapi.encoder_mask) { 2061 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2062 2063 set_bit(intel_encoder->power_domain, mask->bits); 2064 } 2065 2066 if (HAS_DDI(dev_priv) && crtc_state->has_audio) 2067 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits); 2068 2069 if (crtc_state->shared_dpll) 2070 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits); 2071 2072 if (crtc_state->dsc.compression_enable) 2073 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits); 2074 } 2075 2076 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, 2077 struct intel_power_domain_mask *old_domains) 2078 { 2079 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2080 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2081 enum intel_display_power_domain domain; 2082 struct intel_power_domain_mask domains, new_domains; 2083 2084 get_crtc_power_domains(crtc_state, &domains); 2085 2086 bitmap_andnot(new_domains.bits, 2087 domains.bits, 2088 crtc->enabled_power_domains.mask.bits, 2089 POWER_DOMAIN_NUM); 2090 bitmap_andnot(old_domains->bits, 2091 crtc->enabled_power_domains.mask.bits, 2092 domains.bits, 2093 POWER_DOMAIN_NUM); 2094 2095 for_each_power_domain(domain, &new_domains) 2096 intel_display_power_get_in_set(dev_priv, 2097 &crtc->enabled_power_domains, 2098 domain); 2099 } 2100 2101 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc, 2102 struct intel_power_domain_mask *domains) 2103 { 2104 intel_display_power_put_mask_in_set(to_i915(crtc->base.dev), 2105 &crtc->enabled_power_domains, 2106 domains); 2107 } 2108 2109 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 2110 { 2111 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2112 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2113 2114 if (intel_crtc_has_dp_encoder(crtc_state)) { 2115 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 2116 &crtc_state->dp_m_n); 2117 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 2118 &crtc_state->dp_m2_n2); 2119 } 2120 2121 intel_set_transcoder_timings(crtc_state); 2122 2123 i9xx_set_pipeconf(crtc_state); 2124 } 2125 2126 static void valleyview_crtc_enable(struct intel_atomic_state *state, 2127 struct intel_crtc *crtc) 2128 { 2129 const struct intel_crtc_state *new_crtc_state = 2130 intel_atomic_get_new_crtc_state(state, crtc); 2131 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2132 enum pipe pipe = crtc->pipe; 2133 2134 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 2135 return; 2136 2137 i9xx_configure_cpu_transcoder(new_crtc_state); 2138 2139 intel_set_pipe_src_size(new_crtc_state); 2140 2141 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 2142 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY); 2143 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0); 2144 } 2145 2146 crtc->active = true; 2147 2148 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2149 2150 intel_encoders_pre_pll_enable(state, crtc); 2151 2152 if (IS_CHERRYVIEW(dev_priv)) 2153 chv_enable_pll(new_crtc_state); 2154 else 2155 vlv_enable_pll(new_crtc_state); 2156 2157 intel_encoders_pre_enable(state, crtc); 2158 2159 i9xx_pfit_enable(new_crtc_state); 2160 2161 intel_color_load_luts(new_crtc_state); 2162 intel_color_commit_noarm(new_crtc_state); 2163 intel_color_commit_arm(new_crtc_state); 2164 /* update DSPCNTR to configure gamma for pipe bottom color */ 2165 intel_disable_primary_plane(new_crtc_state); 2166 2167 intel_initial_watermarks(state, crtc); 2168 intel_enable_transcoder(new_crtc_state); 2169 2170 intel_crtc_vblank_on(new_crtc_state); 2171 2172 intel_encoders_enable(state, crtc); 2173 } 2174 2175 static void i9xx_crtc_enable(struct intel_atomic_state *state, 2176 struct intel_crtc *crtc) 2177 { 2178 const struct intel_crtc_state *new_crtc_state = 2179 intel_atomic_get_new_crtc_state(state, crtc); 2180 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2181 enum pipe pipe = crtc->pipe; 2182 2183 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 2184 return; 2185 2186 i9xx_configure_cpu_transcoder(new_crtc_state); 2187 2188 intel_set_pipe_src_size(new_crtc_state); 2189 2190 crtc->active = true; 2191 2192 if (DISPLAY_VER(dev_priv) != 2) 2193 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2194 2195 intel_encoders_pre_enable(state, crtc); 2196 2197 i9xx_enable_pll(new_crtc_state); 2198 2199 i9xx_pfit_enable(new_crtc_state); 2200 2201 intel_color_load_luts(new_crtc_state); 2202 intel_color_commit_noarm(new_crtc_state); 2203 intel_color_commit_arm(new_crtc_state); 2204 /* update DSPCNTR to configure gamma for pipe bottom color */ 2205 intel_disable_primary_plane(new_crtc_state); 2206 2207 if (!intel_initial_watermarks(state, crtc)) 2208 intel_update_watermarks(dev_priv); 2209 intel_enable_transcoder(new_crtc_state); 2210 2211 intel_crtc_vblank_on(new_crtc_state); 2212 2213 intel_encoders_enable(state, crtc); 2214 2215 /* prevents spurious underruns */ 2216 if (DISPLAY_VER(dev_priv) == 2) 2217 intel_crtc_wait_for_next_vblank(crtc); 2218 } 2219 2220 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) 2221 { 2222 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 2223 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2224 2225 if (!old_crtc_state->gmch_pfit.control) 2226 return; 2227 2228 assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder); 2229 2230 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n", 2231 intel_de_read(dev_priv, PFIT_CONTROL)); 2232 intel_de_write(dev_priv, PFIT_CONTROL, 0); 2233 } 2234 2235 static void i9xx_crtc_disable(struct intel_atomic_state *state, 2236 struct intel_crtc *crtc) 2237 { 2238 struct intel_crtc_state *old_crtc_state = 2239 intel_atomic_get_old_crtc_state(state, crtc); 2240 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2241 enum pipe pipe = crtc->pipe; 2242 2243 /* 2244 * On gen2 planes are double buffered but the pipe isn't, so we must 2245 * wait for planes to fully turn off before disabling the pipe. 2246 */ 2247 if (DISPLAY_VER(dev_priv) == 2) 2248 intel_crtc_wait_for_next_vblank(crtc); 2249 2250 intel_encoders_disable(state, crtc); 2251 2252 intel_crtc_vblank_off(old_crtc_state); 2253 2254 intel_disable_transcoder(old_crtc_state); 2255 2256 i9xx_pfit_disable(old_crtc_state); 2257 2258 intel_encoders_post_disable(state, crtc); 2259 2260 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) { 2261 if (IS_CHERRYVIEW(dev_priv)) 2262 chv_disable_pll(dev_priv, pipe); 2263 else if (IS_VALLEYVIEW(dev_priv)) 2264 vlv_disable_pll(dev_priv, pipe); 2265 else 2266 i9xx_disable_pll(old_crtc_state); 2267 } 2268 2269 intel_encoders_post_pll_disable(state, crtc); 2270 2271 if (DISPLAY_VER(dev_priv) != 2) 2272 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 2273 2274 if (!dev_priv->display.funcs.wm->initial_watermarks) 2275 intel_update_watermarks(dev_priv); 2276 2277 /* clock the pipe down to 640x480@60 to potentially save power */ 2278 if (IS_I830(dev_priv)) 2279 i830_enable_pipe(dev_priv, pipe); 2280 } 2281 2282 2283 /* 2284 * turn all crtc's off, but do not adjust state 2285 * This has to be paired with a call to intel_modeset_setup_hw_state. 2286 */ 2287 int intel_display_suspend(struct drm_device *dev) 2288 { 2289 struct drm_i915_private *dev_priv = to_i915(dev); 2290 struct drm_atomic_state *state; 2291 int ret; 2292 2293 if (!HAS_DISPLAY(dev_priv)) 2294 return 0; 2295 2296 state = drm_atomic_helper_suspend(dev); 2297 ret = PTR_ERR_OR_ZERO(state); 2298 if (ret) 2299 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", 2300 ret); 2301 else 2302 dev_priv->display.restore.modeset_state = state; 2303 return ret; 2304 } 2305 2306 void intel_encoder_destroy(struct drm_encoder *encoder) 2307 { 2308 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2309 2310 drm_encoder_cleanup(encoder); 2311 kfree(intel_encoder); 2312 } 2313 2314 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) 2315 { 2316 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2317 2318 /* GDG double wide on either pipe, otherwise pipe A only */ 2319 return DISPLAY_VER(dev_priv) < 4 && 2320 (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); 2321 } 2322 2323 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) 2324 { 2325 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock; 2326 struct drm_rect src; 2327 2328 /* 2329 * We only use IF-ID interlacing. If we ever use 2330 * PF-ID we'll need to adjust the pixel_rate here. 2331 */ 2332 2333 if (!crtc_state->pch_pfit.enabled) 2334 return pixel_rate; 2335 2336 drm_rect_init(&src, 0, 0, 2337 drm_rect_width(&crtc_state->pipe_src) << 16, 2338 drm_rect_height(&crtc_state->pipe_src) << 16); 2339 2340 return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst, 2341 pixel_rate); 2342 } 2343 2344 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode, 2345 const struct drm_display_mode *timings) 2346 { 2347 mode->hdisplay = timings->crtc_hdisplay; 2348 mode->htotal = timings->crtc_htotal; 2349 mode->hsync_start = timings->crtc_hsync_start; 2350 mode->hsync_end = timings->crtc_hsync_end; 2351 2352 mode->vdisplay = timings->crtc_vdisplay; 2353 mode->vtotal = timings->crtc_vtotal; 2354 mode->vsync_start = timings->crtc_vsync_start; 2355 mode->vsync_end = timings->crtc_vsync_end; 2356 2357 mode->flags = timings->flags; 2358 mode->type = DRM_MODE_TYPE_DRIVER; 2359 2360 mode->clock = timings->crtc_clock; 2361 2362 drm_mode_set_name(mode); 2363 } 2364 2365 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) 2366 { 2367 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2368 2369 if (HAS_GMCH(dev_priv)) 2370 /* FIXME calculate proper pipe pixel rate for GMCH pfit */ 2371 crtc_state->pixel_rate = 2372 crtc_state->hw.pipe_mode.crtc_clock; 2373 else 2374 crtc_state->pixel_rate = 2375 ilk_pipe_pixel_rate(crtc_state); 2376 } 2377 2378 static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state *crtc_state, 2379 struct drm_display_mode *mode) 2380 { 2381 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2382 2383 if (num_pipes < 2) 2384 return; 2385 2386 mode->crtc_clock /= num_pipes; 2387 mode->crtc_hdisplay /= num_pipes; 2388 mode->crtc_hblank_start /= num_pipes; 2389 mode->crtc_hblank_end /= num_pipes; 2390 mode->crtc_hsync_start /= num_pipes; 2391 mode->crtc_hsync_end /= num_pipes; 2392 mode->crtc_htotal /= num_pipes; 2393 } 2394 2395 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state, 2396 struct drm_display_mode *mode) 2397 { 2398 int overlap = crtc_state->splitter.pixel_overlap; 2399 int n = crtc_state->splitter.link_count; 2400 2401 if (!crtc_state->splitter.enable) 2402 return; 2403 2404 /* 2405 * eDP MSO uses segment timings from EDID for transcoder 2406 * timings, but full mode for everything else. 2407 * 2408 * h_full = (h_segment - pixel_overlap) * link_count 2409 */ 2410 mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n; 2411 mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n; 2412 mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n; 2413 mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n; 2414 mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n; 2415 mode->crtc_htotal = (mode->crtc_htotal - overlap) * n; 2416 mode->crtc_clock *= n; 2417 } 2418 2419 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state) 2420 { 2421 struct drm_display_mode *mode = &crtc_state->hw.mode; 2422 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2423 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2424 2425 /* 2426 * Start with the adjusted_mode crtc timings, which 2427 * have been filled with the transcoder timings. 2428 */ 2429 drm_mode_copy(pipe_mode, adjusted_mode); 2430 2431 /* Expand MSO per-segment transcoder timings to full */ 2432 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2433 2434 /* 2435 * We want the full numbers in adjusted_mode normal timings, 2436 * adjusted_mode crtc timings are left with the raw transcoder 2437 * timings. 2438 */ 2439 intel_mode_from_crtc_timings(adjusted_mode, pipe_mode); 2440 2441 /* Populate the "user" mode with full numbers */ 2442 drm_mode_copy(mode, pipe_mode); 2443 intel_mode_from_crtc_timings(mode, mode); 2444 mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) * 2445 (intel_bigjoiner_num_pipes(crtc_state) ?: 1); 2446 mode->vdisplay = drm_rect_height(&crtc_state->pipe_src); 2447 2448 /* Derive per-pipe timings in case bigjoiner is used */ 2449 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2450 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2451 2452 intel_crtc_compute_pixel_rate(crtc_state); 2453 } 2454 2455 void intel_encoder_get_config(struct intel_encoder *encoder, 2456 struct intel_crtc_state *crtc_state) 2457 { 2458 encoder->get_config(encoder, crtc_state); 2459 2460 intel_crtc_readout_derived_state(crtc_state); 2461 } 2462 2463 static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state *crtc_state) 2464 { 2465 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2466 int width, height; 2467 2468 if (num_pipes < 2) 2469 return; 2470 2471 width = drm_rect_width(&crtc_state->pipe_src); 2472 height = drm_rect_height(&crtc_state->pipe_src); 2473 2474 drm_rect_init(&crtc_state->pipe_src, 0, 0, 2475 width / num_pipes, height); 2476 } 2477 2478 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state) 2479 { 2480 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2481 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2482 2483 intel_bigjoiner_compute_pipe_src(crtc_state); 2484 2485 /* 2486 * Pipe horizontal size must be even in: 2487 * - DVO ganged mode 2488 * - LVDS dual channel mode 2489 * - Double wide pipe 2490 */ 2491 if (drm_rect_width(&crtc_state->pipe_src) & 1) { 2492 if (crtc_state->double_wide) { 2493 drm_dbg_kms(&i915->drm, 2494 "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n", 2495 crtc->base.base.id, crtc->base.name); 2496 return -EINVAL; 2497 } 2498 2499 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 2500 intel_is_dual_link_lvds(i915)) { 2501 drm_dbg_kms(&i915->drm, 2502 "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n", 2503 crtc->base.base.id, crtc->base.name); 2504 return -EINVAL; 2505 } 2506 } 2507 2508 return 0; 2509 } 2510 2511 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state) 2512 { 2513 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2514 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2515 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2516 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2517 int clock_limit = i915->max_dotclk_freq; 2518 2519 /* 2520 * Start with the adjusted_mode crtc timings, which 2521 * have been filled with the transcoder timings. 2522 */ 2523 drm_mode_copy(pipe_mode, adjusted_mode); 2524 2525 /* Expand MSO per-segment transcoder timings to full */ 2526 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2527 2528 /* Derive per-pipe timings in case bigjoiner is used */ 2529 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2530 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2531 2532 if (DISPLAY_VER(i915) < 4) { 2533 clock_limit = i915->display.cdclk.max_cdclk_freq * 9 / 10; 2534 2535 /* 2536 * Enable double wide mode when the dot clock 2537 * is > 90% of the (display) core speed. 2538 */ 2539 if (intel_crtc_supports_double_wide(crtc) && 2540 pipe_mode->crtc_clock > clock_limit) { 2541 clock_limit = i915->max_dotclk_freq; 2542 crtc_state->double_wide = true; 2543 } 2544 } 2545 2546 if (pipe_mode->crtc_clock > clock_limit) { 2547 drm_dbg_kms(&i915->drm, 2548 "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", 2549 crtc->base.base.id, crtc->base.name, 2550 pipe_mode->crtc_clock, clock_limit, 2551 str_yes_no(crtc_state->double_wide)); 2552 return -EINVAL; 2553 } 2554 2555 return 0; 2556 } 2557 2558 static int intel_crtc_compute_config(struct intel_atomic_state *state, 2559 struct intel_crtc *crtc) 2560 { 2561 struct intel_crtc_state *crtc_state = 2562 intel_atomic_get_new_crtc_state(state, crtc); 2563 int ret; 2564 2565 ret = intel_dpll_crtc_compute_clock(state, crtc); 2566 if (ret) 2567 return ret; 2568 2569 ret = intel_crtc_compute_pipe_src(crtc_state); 2570 if (ret) 2571 return ret; 2572 2573 ret = intel_crtc_compute_pipe_mode(crtc_state); 2574 if (ret) 2575 return ret; 2576 2577 intel_crtc_compute_pixel_rate(crtc_state); 2578 2579 if (crtc_state->has_pch_encoder) 2580 return ilk_fdi_compute_config(crtc, crtc_state); 2581 2582 return 0; 2583 } 2584 2585 static void 2586 intel_reduce_m_n_ratio(u32 *num, u32 *den) 2587 { 2588 while (*num > DATA_LINK_M_N_MASK || 2589 *den > DATA_LINK_M_N_MASK) { 2590 *num >>= 1; 2591 *den >>= 1; 2592 } 2593 } 2594 2595 static void compute_m_n(u32 *ret_m, u32 *ret_n, 2596 u32 m, u32 n, u32 constant_n) 2597 { 2598 if (constant_n) 2599 *ret_n = constant_n; 2600 else 2601 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); 2602 2603 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n); 2604 intel_reduce_m_n_ratio(ret_m, ret_n); 2605 } 2606 2607 void 2608 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes, 2609 int pixel_clock, int link_clock, 2610 struct intel_link_m_n *m_n, 2611 bool fec_enable) 2612 { 2613 u32 data_clock = bits_per_pixel * pixel_clock; 2614 2615 if (fec_enable) 2616 data_clock = intel_dp_mode_to_fec_clock(data_clock); 2617 2618 /* 2619 * Windows/BIOS uses fixed M/N values always. Follow suit. 2620 * 2621 * Also several DP dongles in particular seem to be fussy 2622 * about too large link M/N values. Presumably the 20bit 2623 * value used by Windows/BIOS is acceptable to everyone. 2624 */ 2625 m_n->tu = 64; 2626 compute_m_n(&m_n->data_m, &m_n->data_n, 2627 data_clock, link_clock * nlanes * 8, 2628 0x8000000); 2629 2630 compute_m_n(&m_n->link_m, &m_n->link_n, 2631 pixel_clock, link_clock, 2632 0x80000); 2633 } 2634 2635 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv) 2636 { 2637 /* 2638 * There may be no VBT; and if the BIOS enabled SSC we can 2639 * just keep using it to avoid unnecessary flicker. Whereas if the 2640 * BIOS isn't using it, don't assume it will work even if the VBT 2641 * indicates as much. 2642 */ 2643 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { 2644 bool bios_lvds_use_ssc = intel_de_read(dev_priv, 2645 PCH_DREF_CONTROL) & 2646 DREF_SSC1_ENABLE; 2647 2648 if (dev_priv->display.vbt.lvds_use_ssc != bios_lvds_use_ssc) { 2649 drm_dbg_kms(&dev_priv->drm, 2650 "SSC %s by BIOS, overriding VBT which says %s\n", 2651 str_enabled_disabled(bios_lvds_use_ssc), 2652 str_enabled_disabled(dev_priv->display.vbt.lvds_use_ssc)); 2653 dev_priv->display.vbt.lvds_use_ssc = bios_lvds_use_ssc; 2654 } 2655 } 2656 } 2657 2658 void intel_zero_m_n(struct intel_link_m_n *m_n) 2659 { 2660 /* corresponds to 0 register value */ 2661 memset(m_n, 0, sizeof(*m_n)); 2662 m_n->tu = 1; 2663 } 2664 2665 void intel_set_m_n(struct drm_i915_private *i915, 2666 const struct intel_link_m_n *m_n, 2667 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 2668 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 2669 { 2670 intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); 2671 intel_de_write(i915, data_n_reg, m_n->data_n); 2672 intel_de_write(i915, link_m_reg, m_n->link_m); 2673 /* 2674 * On BDW+ writing LINK_N arms the double buffered update 2675 * of all the M/N registers, so it must be written last. 2676 */ 2677 intel_de_write(i915, link_n_reg, m_n->link_n); 2678 } 2679 2680 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, 2681 enum transcoder transcoder) 2682 { 2683 if (IS_HASWELL(dev_priv)) 2684 return transcoder == TRANSCODER_EDP; 2685 2686 return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv); 2687 } 2688 2689 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, 2690 enum transcoder transcoder, 2691 const struct intel_link_m_n *m_n) 2692 { 2693 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2694 enum pipe pipe = crtc->pipe; 2695 2696 if (DISPLAY_VER(dev_priv) >= 5) 2697 intel_set_m_n(dev_priv, m_n, 2698 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 2699 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 2700 else 2701 intel_set_m_n(dev_priv, m_n, 2702 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 2703 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 2704 } 2705 2706 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, 2707 enum transcoder transcoder, 2708 const struct intel_link_m_n *m_n) 2709 { 2710 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2711 2712 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 2713 return; 2714 2715 intel_set_m_n(dev_priv, m_n, 2716 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 2717 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 2718 } 2719 2720 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) 2721 { 2722 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2723 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2724 enum pipe pipe = crtc->pipe; 2725 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2726 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2727 u32 crtc_vtotal, crtc_vblank_end; 2728 int vsyncshift = 0; 2729 2730 /* We need to be careful not to changed the adjusted mode, for otherwise 2731 * the hw state checker will get angry at the mismatch. */ 2732 crtc_vtotal = adjusted_mode->crtc_vtotal; 2733 crtc_vblank_end = adjusted_mode->crtc_vblank_end; 2734 2735 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 2736 /* the chip adds 2 halflines automatically */ 2737 crtc_vtotal -= 1; 2738 crtc_vblank_end -= 1; 2739 2740 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 2741 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; 2742 else 2743 vsyncshift = adjusted_mode->crtc_hsync_start - 2744 adjusted_mode->crtc_htotal / 2; 2745 if (vsyncshift < 0) 2746 vsyncshift += adjusted_mode->crtc_htotal; 2747 } 2748 2749 if (DISPLAY_VER(dev_priv) > 3) 2750 intel_de_write(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder), 2751 vsyncshift); 2752 2753 intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder), 2754 (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16)); 2755 intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder), 2756 (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16)); 2757 intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder), 2758 (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16)); 2759 2760 intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder), 2761 (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16)); 2762 intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), 2763 (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16)); 2764 intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder), 2765 (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16)); 2766 2767 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be 2768 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is 2769 * documented on the DDI_FUNC_CTL register description, EDP Input Select 2770 * bits. */ 2771 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && 2772 (pipe == PIPE_B || pipe == PIPE_C)) 2773 intel_de_write(dev_priv, TRANS_VTOTAL(pipe), 2774 intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder))); 2775 2776 } 2777 2778 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) 2779 { 2780 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2781 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2782 int width = drm_rect_width(&crtc_state->pipe_src); 2783 int height = drm_rect_height(&crtc_state->pipe_src); 2784 enum pipe pipe = crtc->pipe; 2785 2786 /* pipesrc controls the size that is scaled from, which should 2787 * always be the user's requested size. 2788 */ 2789 intel_de_write(dev_priv, PIPESRC(pipe), 2790 PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1)); 2791 } 2792 2793 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) 2794 { 2795 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2796 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2797 2798 if (DISPLAY_VER(dev_priv) == 2) 2799 return false; 2800 2801 if (DISPLAY_VER(dev_priv) >= 9 || 2802 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2803 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW; 2804 else 2805 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK; 2806 } 2807 2808 static void intel_get_transcoder_timings(struct intel_crtc *crtc, 2809 struct intel_crtc_state *pipe_config) 2810 { 2811 struct drm_device *dev = crtc->base.dev; 2812 struct drm_i915_private *dev_priv = to_i915(dev); 2813 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 2814 u32 tmp; 2815 2816 tmp = intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder)); 2817 pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; 2818 pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; 2819 2820 if (!transcoder_is_dsi(cpu_transcoder)) { 2821 tmp = intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder)); 2822 pipe_config->hw.adjusted_mode.crtc_hblank_start = 2823 (tmp & 0xffff) + 1; 2824 pipe_config->hw.adjusted_mode.crtc_hblank_end = 2825 ((tmp >> 16) & 0xffff) + 1; 2826 } 2827 tmp = intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder)); 2828 pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; 2829 pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; 2830 2831 tmp = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder)); 2832 pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; 2833 pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; 2834 2835 if (!transcoder_is_dsi(cpu_transcoder)) { 2836 tmp = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder)); 2837 pipe_config->hw.adjusted_mode.crtc_vblank_start = 2838 (tmp & 0xffff) + 1; 2839 pipe_config->hw.adjusted_mode.crtc_vblank_end = 2840 ((tmp >> 16) & 0xffff) + 1; 2841 } 2842 tmp = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder)); 2843 pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; 2844 pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; 2845 2846 if (intel_pipe_is_interlaced(pipe_config)) { 2847 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; 2848 pipe_config->hw.adjusted_mode.crtc_vtotal += 1; 2849 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1; 2850 } 2851 } 2852 2853 static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state) 2854 { 2855 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2856 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2857 enum pipe master_pipe, pipe = crtc->pipe; 2858 int width; 2859 2860 if (num_pipes < 2) 2861 return; 2862 2863 master_pipe = bigjoiner_master_pipe(crtc_state); 2864 width = drm_rect_width(&crtc_state->pipe_src); 2865 2866 drm_rect_translate_to(&crtc_state->pipe_src, 2867 (pipe - master_pipe) * width, 0); 2868 } 2869 2870 static void intel_get_pipe_src_size(struct intel_crtc *crtc, 2871 struct intel_crtc_state *pipe_config) 2872 { 2873 struct drm_device *dev = crtc->base.dev; 2874 struct drm_i915_private *dev_priv = to_i915(dev); 2875 u32 tmp; 2876 2877 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe)); 2878 2879 drm_rect_init(&pipe_config->pipe_src, 0, 0, 2880 REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1, 2881 REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1); 2882 2883 intel_bigjoiner_adjust_pipe_src(pipe_config); 2884 } 2885 2886 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) 2887 { 2888 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2889 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2890 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2891 u32 val = 0; 2892 2893 /* 2894 * - We keep both pipes enabled on 830 2895 * - During modeset the pipe is still disabled and must remain so 2896 * - During fastset the pipe is already enabled and must remain so 2897 */ 2898 if (IS_I830(dev_priv) || !intel_crtc_needs_modeset(crtc_state)) 2899 val |= TRANSCONF_ENABLE; 2900 2901 if (crtc_state->double_wide) 2902 val |= TRANSCONF_DOUBLE_WIDE; 2903 2904 /* only g4x and later have fancy bpc/dither controls */ 2905 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 2906 IS_CHERRYVIEW(dev_priv)) { 2907 /* Bspec claims that we can't use dithering for 30bpp pipes. */ 2908 if (crtc_state->dither && crtc_state->pipe_bpp != 30) 2909 val |= TRANSCONF_DITHER_EN | 2910 TRANSCONF_DITHER_TYPE_SP; 2911 2912 switch (crtc_state->pipe_bpp) { 2913 default: 2914 /* Case prevented by intel_choose_pipe_bpp_dither. */ 2915 MISSING_CASE(crtc_state->pipe_bpp); 2916 fallthrough; 2917 case 18: 2918 val |= TRANSCONF_BPC_6; 2919 break; 2920 case 24: 2921 val |= TRANSCONF_BPC_8; 2922 break; 2923 case 30: 2924 val |= TRANSCONF_BPC_10; 2925 break; 2926 } 2927 } 2928 2929 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 2930 if (DISPLAY_VER(dev_priv) < 4 || 2931 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 2932 val |= TRANSCONF_INTERLACE_W_FIELD_INDICATION; 2933 else 2934 val |= TRANSCONF_INTERLACE_W_SYNC_SHIFT; 2935 } else { 2936 val |= TRANSCONF_INTERLACE_PROGRESSIVE; 2937 } 2938 2939 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 2940 crtc_state->limited_color_range) 2941 val |= TRANSCONF_COLOR_RANGE_SELECT; 2942 2943 val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode); 2944 2945 val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 2946 2947 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); 2948 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); 2949 } 2950 2951 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv) 2952 { 2953 if (IS_I830(dev_priv)) 2954 return false; 2955 2956 return DISPLAY_VER(dev_priv) >= 4 || 2957 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); 2958 } 2959 2960 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state) 2961 { 2962 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2963 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2964 u32 tmp; 2965 2966 if (!i9xx_has_pfit(dev_priv)) 2967 return; 2968 2969 tmp = intel_de_read(dev_priv, PFIT_CONTROL); 2970 if (!(tmp & PFIT_ENABLE)) 2971 return; 2972 2973 /* Check whether the pfit is attached to our pipe. */ 2974 if (DISPLAY_VER(dev_priv) < 4) { 2975 if (crtc->pipe != PIPE_B) 2976 return; 2977 } else { 2978 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) 2979 return; 2980 } 2981 2982 crtc_state->gmch_pfit.control = tmp; 2983 crtc_state->gmch_pfit.pgm_ratios = 2984 intel_de_read(dev_priv, PFIT_PGM_RATIOS); 2985 } 2986 2987 static void vlv_crtc_clock_get(struct intel_crtc *crtc, 2988 struct intel_crtc_state *pipe_config) 2989 { 2990 struct drm_device *dev = crtc->base.dev; 2991 struct drm_i915_private *dev_priv = to_i915(dev); 2992 enum pipe pipe = crtc->pipe; 2993 struct dpll clock; 2994 u32 mdiv; 2995 int refclk = 100000; 2996 2997 /* In case of DSI, DPLL will not be used */ 2998 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 2999 return; 3000 3001 vlv_dpio_get(dev_priv); 3002 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); 3003 vlv_dpio_put(dev_priv); 3004 3005 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; 3006 clock.m2 = mdiv & DPIO_M2DIV_MASK; 3007 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; 3008 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; 3009 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; 3010 3011 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); 3012 } 3013 3014 static void chv_crtc_clock_get(struct intel_crtc *crtc, 3015 struct intel_crtc_state *pipe_config) 3016 { 3017 struct drm_device *dev = crtc->base.dev; 3018 struct drm_i915_private *dev_priv = to_i915(dev); 3019 enum pipe pipe = crtc->pipe; 3020 enum dpio_channel port = vlv_pipe_to_channel(pipe); 3021 struct dpll clock; 3022 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; 3023 int refclk = 100000; 3024 3025 /* In case of DSI, DPLL will not be used */ 3026 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 3027 return; 3028 3029 vlv_dpio_get(dev_priv); 3030 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); 3031 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); 3032 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); 3033 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); 3034 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); 3035 vlv_dpio_put(dev_priv); 3036 3037 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; 3038 clock.m2 = (pll_dw0 & 0xff) << 22; 3039 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) 3040 clock.m2 |= pll_dw2 & 0x3fffff; 3041 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; 3042 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; 3043 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; 3044 3045 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); 3046 } 3047 3048 static enum intel_output_format 3049 bdw_get_pipemisc_output_format(struct intel_crtc *crtc) 3050 { 3051 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3052 u32 tmp; 3053 3054 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); 3055 3056 if (tmp & PIPEMISC_YUV420_ENABLE) { 3057 /* We support 4:2:0 in full blend mode only */ 3058 drm_WARN_ON(&dev_priv->drm, 3059 (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0); 3060 3061 return INTEL_OUTPUT_FORMAT_YCBCR420; 3062 } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) { 3063 return INTEL_OUTPUT_FORMAT_YCBCR444; 3064 } else { 3065 return INTEL_OUTPUT_FORMAT_RGB; 3066 } 3067 } 3068 3069 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state) 3070 { 3071 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3072 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 3073 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3074 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 3075 u32 tmp; 3076 3077 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); 3078 3079 if (tmp & DISP_PIPE_GAMMA_ENABLE) 3080 crtc_state->gamma_enable = true; 3081 3082 if (!HAS_GMCH(dev_priv) && 3083 tmp & DISP_PIPE_CSC_ENABLE) 3084 crtc_state->csc_enable = true; 3085 } 3086 3087 static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 3088 struct intel_crtc_state *pipe_config) 3089 { 3090 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3091 enum intel_display_power_domain power_domain; 3092 intel_wakeref_t wakeref; 3093 u32 tmp; 3094 bool ret; 3095 3096 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3097 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3098 if (!wakeref) 3099 return false; 3100 3101 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3102 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3103 pipe_config->shared_dpll = NULL; 3104 3105 ret = false; 3106 3107 tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder)); 3108 if (!(tmp & TRANSCONF_ENABLE)) 3109 goto out; 3110 3111 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 3112 IS_CHERRYVIEW(dev_priv)) { 3113 switch (tmp & TRANSCONF_BPC_MASK) { 3114 case TRANSCONF_BPC_6: 3115 pipe_config->pipe_bpp = 18; 3116 break; 3117 case TRANSCONF_BPC_8: 3118 pipe_config->pipe_bpp = 24; 3119 break; 3120 case TRANSCONF_BPC_10: 3121 pipe_config->pipe_bpp = 30; 3122 break; 3123 default: 3124 MISSING_CASE(tmp); 3125 break; 3126 } 3127 } 3128 3129 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 3130 (tmp & TRANSCONF_COLOR_RANGE_SELECT)) 3131 pipe_config->limited_color_range = true; 3132 3133 pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp); 3134 3135 pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1; 3136 3137 if (IS_CHERRYVIEW(dev_priv)) 3138 pipe_config->cgm_mode = intel_de_read(dev_priv, 3139 CGM_PIPE_MODE(crtc->pipe)); 3140 3141 i9xx_get_pipe_color_config(pipe_config); 3142 intel_color_get_config(pipe_config); 3143 3144 if (DISPLAY_VER(dev_priv) < 4) 3145 pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE; 3146 3147 intel_get_transcoder_timings(crtc, pipe_config); 3148 intel_get_pipe_src_size(crtc, pipe_config); 3149 3150 i9xx_get_pfit_config(pipe_config); 3151 3152 if (DISPLAY_VER(dev_priv) >= 4) { 3153 /* No way to read it out on pipes B and C */ 3154 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) 3155 tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe]; 3156 else 3157 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe)); 3158 pipe_config->pixel_multiplier = 3159 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) 3160 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; 3161 pipe_config->dpll_hw_state.dpll_md = tmp; 3162 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 3163 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 3164 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe)); 3165 pipe_config->pixel_multiplier = 3166 ((tmp & SDVO_MULTIPLIER_MASK) 3167 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; 3168 } else { 3169 /* Note that on i915G/GM the pixel multiplier is in the sdvo 3170 * port and will be fixed up in the encoder->get_config 3171 * function. */ 3172 pipe_config->pixel_multiplier = 1; 3173 } 3174 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv, 3175 DPLL(crtc->pipe)); 3176 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 3177 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv, 3178 FP0(crtc->pipe)); 3179 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv, 3180 FP1(crtc->pipe)); 3181 } else { 3182 /* Mask out read-only status bits. */ 3183 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | 3184 DPLL_PORTC_READY_MASK | 3185 DPLL_PORTB_READY_MASK); 3186 } 3187 3188 if (IS_CHERRYVIEW(dev_priv)) 3189 chv_crtc_clock_get(crtc, pipe_config); 3190 else if (IS_VALLEYVIEW(dev_priv)) 3191 vlv_crtc_clock_get(crtc, pipe_config); 3192 else 3193 i9xx_crtc_clock_get(crtc, pipe_config); 3194 3195 /* 3196 * Normally the dotclock is filled in by the encoder .get_config() 3197 * but in case the pipe is enabled w/o any ports we need a sane 3198 * default. 3199 */ 3200 pipe_config->hw.adjusted_mode.crtc_clock = 3201 pipe_config->port_clock / pipe_config->pixel_multiplier; 3202 3203 ret = true; 3204 3205 out: 3206 intel_display_power_put(dev_priv, power_domain, wakeref); 3207 3208 return ret; 3209 } 3210 3211 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) 3212 { 3213 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3214 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3215 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3216 u32 val = 0; 3217 3218 /* 3219 * - During modeset the pipe is still disabled and must remain so 3220 * - During fastset the pipe is already enabled and must remain so 3221 */ 3222 if (!intel_crtc_needs_modeset(crtc_state)) 3223 val |= TRANSCONF_ENABLE; 3224 3225 switch (crtc_state->pipe_bpp) { 3226 default: 3227 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3228 MISSING_CASE(crtc_state->pipe_bpp); 3229 fallthrough; 3230 case 18: 3231 val |= TRANSCONF_BPC_6; 3232 break; 3233 case 24: 3234 val |= TRANSCONF_BPC_8; 3235 break; 3236 case 30: 3237 val |= TRANSCONF_BPC_10; 3238 break; 3239 case 36: 3240 val |= TRANSCONF_BPC_12; 3241 break; 3242 } 3243 3244 if (crtc_state->dither) 3245 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP; 3246 3247 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3248 val |= TRANSCONF_INTERLACE_IF_ID_ILK; 3249 else 3250 val |= TRANSCONF_INTERLACE_PF_PD_ILK; 3251 3252 /* 3253 * This would end up with an odd purple hue over 3254 * the entire display. Make sure we don't do it. 3255 */ 3256 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 3257 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 3258 3259 if (crtc_state->limited_color_range && 3260 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3261 val |= TRANSCONF_COLOR_RANGE_SELECT; 3262 3263 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3264 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV709; 3265 3266 val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode); 3267 3268 val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3269 val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay); 3270 3271 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); 3272 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); 3273 } 3274 3275 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) 3276 { 3277 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3278 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3279 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3280 u32 val = 0; 3281 3282 /* 3283 * - During modeset the pipe is still disabled and must remain so 3284 * - During fastset the pipe is already enabled and must remain so 3285 */ 3286 if (!intel_crtc_needs_modeset(crtc_state)) 3287 val |= TRANSCONF_ENABLE; 3288 3289 if (IS_HASWELL(dev_priv) && crtc_state->dither) 3290 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP; 3291 3292 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3293 val |= TRANSCONF_INTERLACE_IF_ID_ILK; 3294 else 3295 val |= TRANSCONF_INTERLACE_PF_PD_ILK; 3296 3297 if (IS_HASWELL(dev_priv) && 3298 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3299 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW; 3300 3301 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); 3302 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); 3303 } 3304 3305 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) 3306 { 3307 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3308 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3309 u32 val = 0; 3310 3311 switch (crtc_state->pipe_bpp) { 3312 case 18: 3313 val |= PIPEMISC_BPC_6; 3314 break; 3315 case 24: 3316 val |= PIPEMISC_BPC_8; 3317 break; 3318 case 30: 3319 val |= PIPEMISC_BPC_10; 3320 break; 3321 case 36: 3322 /* Port output 12BPC defined for ADLP+ */ 3323 if (DISPLAY_VER(dev_priv) > 12) 3324 val |= PIPEMISC_BPC_12_ADLP; 3325 break; 3326 default: 3327 MISSING_CASE(crtc_state->pipe_bpp); 3328 break; 3329 } 3330 3331 if (crtc_state->dither) 3332 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; 3333 3334 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 3335 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 3336 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV; 3337 3338 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 3339 val |= PIPEMISC_YUV420_ENABLE | 3340 PIPEMISC_YUV420_MODE_FULL_BLEND; 3341 3342 if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state)) 3343 val |= PIPEMISC_HDR_MODE_PRECISION; 3344 3345 if (DISPLAY_VER(dev_priv) >= 12) 3346 val |= PIPEMISC_PIXEL_ROUNDING_TRUNC; 3347 3348 intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val); 3349 } 3350 3351 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) 3352 { 3353 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3354 u32 tmp; 3355 3356 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); 3357 3358 switch (tmp & PIPEMISC_BPC_MASK) { 3359 case PIPEMISC_BPC_6: 3360 return 18; 3361 case PIPEMISC_BPC_8: 3362 return 24; 3363 case PIPEMISC_BPC_10: 3364 return 30; 3365 /* 3366 * PORT OUTPUT 12 BPC defined for ADLP+. 3367 * 3368 * TODO: 3369 * For previous platforms with DSI interface, bits 5:7 3370 * are used for storing pipe_bpp irrespective of dithering. 3371 * Since the value of 12 BPC is not defined for these bits 3372 * on older platforms, need to find a workaround for 12 BPC 3373 * MIPI DSI HW readout. 3374 */ 3375 case PIPEMISC_BPC_12_ADLP: 3376 if (DISPLAY_VER(dev_priv) > 12) 3377 return 36; 3378 fallthrough; 3379 default: 3380 MISSING_CASE(tmp); 3381 return 0; 3382 } 3383 } 3384 3385 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) 3386 { 3387 /* 3388 * Account for spread spectrum to avoid 3389 * oversubscribing the link. Max center spread 3390 * is 2.5%; use 5% for safety's sake. 3391 */ 3392 u32 bps = target_clock * bpp * 21 / 20; 3393 return DIV_ROUND_UP(bps, link_bw * 8); 3394 } 3395 3396 void intel_get_m_n(struct drm_i915_private *i915, 3397 struct intel_link_m_n *m_n, 3398 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 3399 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 3400 { 3401 m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK; 3402 m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK; 3403 m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK; 3404 m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK; 3405 m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1; 3406 } 3407 3408 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, 3409 enum transcoder transcoder, 3410 struct intel_link_m_n *m_n) 3411 { 3412 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3413 enum pipe pipe = crtc->pipe; 3414 3415 if (DISPLAY_VER(dev_priv) >= 5) 3416 intel_get_m_n(dev_priv, m_n, 3417 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 3418 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 3419 else 3420 intel_get_m_n(dev_priv, m_n, 3421 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 3422 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 3423 } 3424 3425 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, 3426 enum transcoder transcoder, 3427 struct intel_link_m_n *m_n) 3428 { 3429 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3430 3431 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 3432 return; 3433 3434 intel_get_m_n(dev_priv, m_n, 3435 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 3436 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 3437 } 3438 3439 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state, 3440 u32 pos, u32 size) 3441 { 3442 drm_rect_init(&crtc_state->pch_pfit.dst, 3443 pos >> 16, pos & 0xffff, 3444 size >> 16, size & 0xffff); 3445 } 3446 3447 static void skl_get_pfit_config(struct intel_crtc_state *crtc_state) 3448 { 3449 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3450 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3451 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; 3452 int id = -1; 3453 int i; 3454 3455 /* find scaler attached to this pipe */ 3456 for (i = 0; i < crtc->num_scalers; i++) { 3457 u32 ctl, pos, size; 3458 3459 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i)); 3460 if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN) 3461 continue; 3462 3463 id = i; 3464 crtc_state->pch_pfit.enabled = true; 3465 3466 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i)); 3467 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i)); 3468 3469 ilk_get_pfit_pos_size(crtc_state, pos, size); 3470 3471 scaler_state->scalers[i].in_use = true; 3472 break; 3473 } 3474 3475 scaler_state->scaler_id = id; 3476 if (id >= 0) 3477 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); 3478 else 3479 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); 3480 } 3481 3482 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state) 3483 { 3484 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3485 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3486 u32 ctl, pos, size; 3487 3488 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe)); 3489 if ((ctl & PF_ENABLE) == 0) 3490 return; 3491 3492 crtc_state->pch_pfit.enabled = true; 3493 3494 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe)); 3495 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe)); 3496 3497 ilk_get_pfit_pos_size(crtc_state, pos, size); 3498 3499 /* 3500 * We currently do not free assignements of panel fitters on 3501 * ivb/hsw (since we don't use the higher upscaling modes which 3502 * differentiates them) so just WARN about this case for now. 3503 */ 3504 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 7 && 3505 (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe)); 3506 } 3507 3508 static bool ilk_get_pipe_config(struct intel_crtc *crtc, 3509 struct intel_crtc_state *pipe_config) 3510 { 3511 struct drm_device *dev = crtc->base.dev; 3512 struct drm_i915_private *dev_priv = to_i915(dev); 3513 enum intel_display_power_domain power_domain; 3514 intel_wakeref_t wakeref; 3515 u32 tmp; 3516 bool ret; 3517 3518 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3519 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3520 if (!wakeref) 3521 return false; 3522 3523 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3524 pipe_config->shared_dpll = NULL; 3525 3526 ret = false; 3527 tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder)); 3528 if (!(tmp & TRANSCONF_ENABLE)) 3529 goto out; 3530 3531 switch (tmp & TRANSCONF_BPC_MASK) { 3532 case TRANSCONF_BPC_6: 3533 pipe_config->pipe_bpp = 18; 3534 break; 3535 case TRANSCONF_BPC_8: 3536 pipe_config->pipe_bpp = 24; 3537 break; 3538 case TRANSCONF_BPC_10: 3539 pipe_config->pipe_bpp = 30; 3540 break; 3541 case TRANSCONF_BPC_12: 3542 pipe_config->pipe_bpp = 36; 3543 break; 3544 default: 3545 break; 3546 } 3547 3548 if (tmp & TRANSCONF_COLOR_RANGE_SELECT) 3549 pipe_config->limited_color_range = true; 3550 3551 switch (tmp & TRANSCONF_OUTPUT_COLORSPACE_MASK) { 3552 case TRANSCONF_OUTPUT_COLORSPACE_YUV601: 3553 case TRANSCONF_OUTPUT_COLORSPACE_YUV709: 3554 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3555 break; 3556 default: 3557 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3558 break; 3559 } 3560 3561 pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp); 3562 3563 pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1; 3564 3565 pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp); 3566 3567 pipe_config->csc_mode = intel_de_read(dev_priv, 3568 PIPE_CSC_MODE(crtc->pipe)); 3569 3570 i9xx_get_pipe_color_config(pipe_config); 3571 intel_color_get_config(pipe_config); 3572 3573 pipe_config->pixel_multiplier = 1; 3574 3575 ilk_pch_get_config(pipe_config); 3576 3577 intel_get_transcoder_timings(crtc, pipe_config); 3578 intel_get_pipe_src_size(crtc, pipe_config); 3579 3580 ilk_get_pfit_config(pipe_config); 3581 3582 ret = true; 3583 3584 out: 3585 intel_display_power_put(dev_priv, power_domain, wakeref); 3586 3587 return ret; 3588 } 3589 3590 static u8 bigjoiner_pipes(struct drm_i915_private *i915) 3591 { 3592 u8 pipes; 3593 3594 if (DISPLAY_VER(i915) >= 12) 3595 pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D); 3596 else if (DISPLAY_VER(i915) >= 11) 3597 pipes = BIT(PIPE_B) | BIT(PIPE_C); 3598 else 3599 pipes = 0; 3600 3601 return pipes & RUNTIME_INFO(i915)->pipe_mask; 3602 } 3603 3604 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv, 3605 enum transcoder cpu_transcoder) 3606 { 3607 enum intel_display_power_domain power_domain; 3608 intel_wakeref_t wakeref; 3609 u32 tmp = 0; 3610 3611 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3612 3613 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3614 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3615 3616 return tmp & TRANS_DDI_FUNC_ENABLE; 3617 } 3618 3619 static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv, 3620 u8 *master_pipes, u8 *slave_pipes) 3621 { 3622 struct intel_crtc *crtc; 3623 3624 *master_pipes = 0; 3625 *slave_pipes = 0; 3626 3627 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, 3628 bigjoiner_pipes(dev_priv)) { 3629 enum intel_display_power_domain power_domain; 3630 enum pipe pipe = crtc->pipe; 3631 intel_wakeref_t wakeref; 3632 3633 power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe); 3634 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3635 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3636 3637 if (!(tmp & BIG_JOINER_ENABLE)) 3638 continue; 3639 3640 if (tmp & MASTER_BIG_JOINER_ENABLE) 3641 *master_pipes |= BIT(pipe); 3642 else 3643 *slave_pipes |= BIT(pipe); 3644 } 3645 3646 if (DISPLAY_VER(dev_priv) < 13) 3647 continue; 3648 3649 power_domain = POWER_DOMAIN_PIPE(pipe); 3650 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3651 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3652 3653 if (tmp & UNCOMPRESSED_JOINER_MASTER) 3654 *master_pipes |= BIT(pipe); 3655 if (tmp & UNCOMPRESSED_JOINER_SLAVE) 3656 *slave_pipes |= BIT(pipe); 3657 } 3658 } 3659 3660 /* Bigjoiner pipes should always be consecutive master and slave */ 3661 drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1, 3662 "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n", 3663 *master_pipes, *slave_pipes); 3664 } 3665 3666 static enum pipe get_bigjoiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3667 { 3668 if ((slave_pipes & BIT(pipe)) == 0) 3669 return pipe; 3670 3671 /* ignore everything above our pipe */ 3672 master_pipes &= ~GENMASK(7, pipe); 3673 3674 /* highest remaining bit should be our master pipe */ 3675 return fls(master_pipes) - 1; 3676 } 3677 3678 static u8 get_bigjoiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3679 { 3680 enum pipe master_pipe, next_master_pipe; 3681 3682 master_pipe = get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes); 3683 3684 if ((master_pipes & BIT(master_pipe)) == 0) 3685 return 0; 3686 3687 /* ignore our master pipe and everything below it */ 3688 master_pipes &= ~GENMASK(master_pipe, 0); 3689 /* make sure a high bit is set for the ffs() */ 3690 master_pipes |= BIT(7); 3691 /* lowest remaining bit should be the next master pipe */ 3692 next_master_pipe = ffs(master_pipes) - 1; 3693 3694 return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe); 3695 } 3696 3697 static u8 hsw_panel_transcoders(struct drm_i915_private *i915) 3698 { 3699 u8 panel_transcoder_mask = BIT(TRANSCODER_EDP); 3700 3701 if (DISPLAY_VER(i915) >= 11) 3702 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); 3703 3704 return panel_transcoder_mask; 3705 } 3706 3707 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) 3708 { 3709 struct drm_device *dev = crtc->base.dev; 3710 struct drm_i915_private *dev_priv = to_i915(dev); 3711 u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv); 3712 enum transcoder cpu_transcoder; 3713 u8 master_pipes, slave_pipes; 3714 u8 enabled_transcoders = 0; 3715 3716 /* 3717 * XXX: Do intel_display_power_get_if_enabled before reading this (for 3718 * consistency and less surprising code; it's in always on power). 3719 */ 3720 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, 3721 panel_transcoder_mask) { 3722 enum intel_display_power_domain power_domain; 3723 intel_wakeref_t wakeref; 3724 enum pipe trans_pipe; 3725 u32 tmp = 0; 3726 3727 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3728 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3729 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3730 3731 if (!(tmp & TRANS_DDI_FUNC_ENABLE)) 3732 continue; 3733 3734 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 3735 default: 3736 drm_WARN(dev, 1, 3737 "unknown pipe linked to transcoder %s\n", 3738 transcoder_name(cpu_transcoder)); 3739 fallthrough; 3740 case TRANS_DDI_EDP_INPUT_A_ONOFF: 3741 case TRANS_DDI_EDP_INPUT_A_ON: 3742 trans_pipe = PIPE_A; 3743 break; 3744 case TRANS_DDI_EDP_INPUT_B_ONOFF: 3745 trans_pipe = PIPE_B; 3746 break; 3747 case TRANS_DDI_EDP_INPUT_C_ONOFF: 3748 trans_pipe = PIPE_C; 3749 break; 3750 case TRANS_DDI_EDP_INPUT_D_ONOFF: 3751 trans_pipe = PIPE_D; 3752 break; 3753 } 3754 3755 if (trans_pipe == crtc->pipe) 3756 enabled_transcoders |= BIT(cpu_transcoder); 3757 } 3758 3759 /* single pipe or bigjoiner master */ 3760 cpu_transcoder = (enum transcoder) crtc->pipe; 3761 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 3762 enabled_transcoders |= BIT(cpu_transcoder); 3763 3764 /* bigjoiner slave -> consider the master pipe's transcoder as well */ 3765 enabled_bigjoiner_pipes(dev_priv, &master_pipes, &slave_pipes); 3766 if (slave_pipes & BIT(crtc->pipe)) { 3767 cpu_transcoder = (enum transcoder) 3768 get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes); 3769 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 3770 enabled_transcoders |= BIT(cpu_transcoder); 3771 } 3772 3773 return enabled_transcoders; 3774 } 3775 3776 static bool has_edp_transcoders(u8 enabled_transcoders) 3777 { 3778 return enabled_transcoders & BIT(TRANSCODER_EDP); 3779 } 3780 3781 static bool has_dsi_transcoders(u8 enabled_transcoders) 3782 { 3783 return enabled_transcoders & (BIT(TRANSCODER_DSI_0) | 3784 BIT(TRANSCODER_DSI_1)); 3785 } 3786 3787 static bool has_pipe_transcoders(u8 enabled_transcoders) 3788 { 3789 return enabled_transcoders & ~(BIT(TRANSCODER_EDP) | 3790 BIT(TRANSCODER_DSI_0) | 3791 BIT(TRANSCODER_DSI_1)); 3792 } 3793 3794 static void assert_enabled_transcoders(struct drm_i915_private *i915, 3795 u8 enabled_transcoders) 3796 { 3797 /* Only one type of transcoder please */ 3798 drm_WARN_ON(&i915->drm, 3799 has_edp_transcoders(enabled_transcoders) + 3800 has_dsi_transcoders(enabled_transcoders) + 3801 has_pipe_transcoders(enabled_transcoders) > 1); 3802 3803 /* Only DSI transcoders can be ganged */ 3804 drm_WARN_ON(&i915->drm, 3805 !has_dsi_transcoders(enabled_transcoders) && 3806 !is_power_of_2(enabled_transcoders)); 3807 } 3808 3809 static bool hsw_get_transcoder_state(struct intel_crtc *crtc, 3810 struct intel_crtc_state *pipe_config, 3811 struct intel_display_power_domain_set *power_domain_set) 3812 { 3813 struct drm_device *dev = crtc->base.dev; 3814 struct drm_i915_private *dev_priv = to_i915(dev); 3815 unsigned long enabled_transcoders; 3816 u32 tmp; 3817 3818 enabled_transcoders = hsw_enabled_transcoders(crtc); 3819 if (!enabled_transcoders) 3820 return false; 3821 3822 assert_enabled_transcoders(dev_priv, enabled_transcoders); 3823 3824 /* 3825 * With the exception of DSI we should only ever have 3826 * a single enabled transcoder. With DSI let's just 3827 * pick the first one. 3828 */ 3829 pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1; 3830 3831 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 3832 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) 3833 return false; 3834 3835 if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) { 3836 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); 3837 3838 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF) 3839 pipe_config->pch_pfit.force_thru = true; 3840 } 3841 3842 tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder)); 3843 3844 return tmp & TRANSCONF_ENABLE; 3845 } 3846 3847 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, 3848 struct intel_crtc_state *pipe_config, 3849 struct intel_display_power_domain_set *power_domain_set) 3850 { 3851 struct drm_device *dev = crtc->base.dev; 3852 struct drm_i915_private *dev_priv = to_i915(dev); 3853 enum transcoder cpu_transcoder; 3854 enum port port; 3855 u32 tmp; 3856 3857 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { 3858 if (port == PORT_A) 3859 cpu_transcoder = TRANSCODER_DSI_A; 3860 else 3861 cpu_transcoder = TRANSCODER_DSI_C; 3862 3863 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 3864 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) 3865 continue; 3866 3867 /* 3868 * The PLL needs to be enabled with a valid divider 3869 * configuration, otherwise accessing DSI registers will hang 3870 * the machine. See BSpec North Display Engine 3871 * registers/MIPI[BXT]. We can break out here early, since we 3872 * need the same DSI PLL to be enabled for both DSI ports. 3873 */ 3874 if (!bxt_dsi_pll_is_enabled(dev_priv)) 3875 break; 3876 3877 /* XXX: this works for video mode only */ 3878 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); 3879 if (!(tmp & DPI_ENABLE)) 3880 continue; 3881 3882 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 3883 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) 3884 continue; 3885 3886 pipe_config->cpu_transcoder = cpu_transcoder; 3887 break; 3888 } 3889 3890 return transcoder_is_dsi(pipe_config->cpu_transcoder); 3891 } 3892 3893 static void intel_bigjoiner_get_config(struct intel_crtc_state *crtc_state) 3894 { 3895 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3896 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 3897 u8 master_pipes, slave_pipes; 3898 enum pipe pipe = crtc->pipe; 3899 3900 enabled_bigjoiner_pipes(i915, &master_pipes, &slave_pipes); 3901 3902 if (((master_pipes | slave_pipes) & BIT(pipe)) == 0) 3903 return; 3904 3905 crtc_state->bigjoiner_pipes = 3906 BIT(get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes)) | 3907 get_bigjoiner_slave_pipes(pipe, master_pipes, slave_pipes); 3908 } 3909 3910 static bool hsw_get_pipe_config(struct intel_crtc *crtc, 3911 struct intel_crtc_state *pipe_config) 3912 { 3913 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3914 bool active; 3915 u32 tmp; 3916 3917 if (!intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains, 3918 POWER_DOMAIN_PIPE(crtc->pipe))) 3919 return false; 3920 3921 pipe_config->shared_dpll = NULL; 3922 3923 active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains); 3924 3925 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 3926 bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) { 3927 drm_WARN_ON(&dev_priv->drm, active); 3928 active = true; 3929 } 3930 3931 if (!active) 3932 goto out; 3933 3934 intel_dsc_get_config(pipe_config); 3935 intel_bigjoiner_get_config(pipe_config); 3936 3937 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || 3938 DISPLAY_VER(dev_priv) >= 11) 3939 intel_get_transcoder_timings(crtc, pipe_config); 3940 3941 if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder)) 3942 intel_vrr_get_config(crtc, pipe_config); 3943 3944 intel_get_pipe_src_size(crtc, pipe_config); 3945 3946 if (IS_HASWELL(dev_priv)) { 3947 u32 tmp = intel_de_read(dev_priv, 3948 TRANSCONF(pipe_config->cpu_transcoder)); 3949 3950 if (tmp & TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW) 3951 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3952 else 3953 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3954 } else { 3955 pipe_config->output_format = 3956 bdw_get_pipemisc_output_format(crtc); 3957 } 3958 3959 pipe_config->gamma_mode = intel_de_read(dev_priv, 3960 GAMMA_MODE(crtc->pipe)); 3961 3962 pipe_config->csc_mode = intel_de_read(dev_priv, 3963 PIPE_CSC_MODE(crtc->pipe)); 3964 3965 if (DISPLAY_VER(dev_priv) >= 9) { 3966 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe)); 3967 3968 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE) 3969 pipe_config->gamma_enable = true; 3970 3971 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE) 3972 pipe_config->csc_enable = true; 3973 } else { 3974 i9xx_get_pipe_color_config(pipe_config); 3975 } 3976 3977 intel_color_get_config(pipe_config); 3978 3979 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe)); 3980 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); 3981 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 3982 pipe_config->ips_linetime = 3983 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); 3984 3985 if (intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains, 3986 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) { 3987 if (DISPLAY_VER(dev_priv) >= 9) 3988 skl_get_pfit_config(pipe_config); 3989 else 3990 ilk_get_pfit_config(pipe_config); 3991 } 3992 3993 hsw_ips_get_config(pipe_config); 3994 3995 if (pipe_config->cpu_transcoder != TRANSCODER_EDP && 3996 !transcoder_is_dsi(pipe_config->cpu_transcoder)) { 3997 pipe_config->pixel_multiplier = 3998 intel_de_read(dev_priv, 3999 TRANS_MULT(pipe_config->cpu_transcoder)) + 1; 4000 } else { 4001 pipe_config->pixel_multiplier = 1; 4002 } 4003 4004 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { 4005 tmp = intel_de_read(dev_priv, DISPLAY_VER(dev_priv) >= 14 ? 4006 MTL_CHICKEN_TRANS(pipe_config->cpu_transcoder) : 4007 CHICKEN_TRANS(pipe_config->cpu_transcoder)); 4008 4009 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1; 4010 } else { 4011 /* no idea if this is correct */ 4012 pipe_config->framestart_delay = 1; 4013 } 4014 4015 out: 4016 intel_display_power_put_all_in_set(dev_priv, &crtc->hw_readout_power_domains); 4017 4018 return active; 4019 } 4020 4021 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state) 4022 { 4023 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4024 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4025 4026 if (!i915->display.funcs.display->get_pipe_config(crtc, crtc_state)) 4027 return false; 4028 4029 crtc_state->hw.active = true; 4030 4031 intel_crtc_readout_derived_state(crtc_state); 4032 4033 return true; 4034 } 4035 4036 /* VESA 640x480x72Hz mode to set on the pipe */ 4037 static const struct drm_display_mode load_detect_mode = { 4038 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, 4039 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 4040 }; 4041 4042 static int intel_modeset_disable_planes(struct drm_atomic_state *state, 4043 struct drm_crtc *crtc) 4044 { 4045 struct drm_plane *plane; 4046 struct drm_plane_state *plane_state; 4047 int ret, i; 4048 4049 ret = drm_atomic_add_affected_planes(state, crtc); 4050 if (ret) 4051 return ret; 4052 4053 for_each_new_plane_in_state(state, plane, plane_state, i) { 4054 if (plane_state->crtc != crtc) 4055 continue; 4056 4057 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL); 4058 if (ret) 4059 return ret; 4060 4061 drm_atomic_set_fb_for_plane(plane_state, NULL); 4062 } 4063 4064 return 0; 4065 } 4066 4067 int intel_get_load_detect_pipe(struct drm_connector *connector, 4068 struct intel_load_detect_pipe *old, 4069 struct drm_modeset_acquire_ctx *ctx) 4070 { 4071 struct intel_encoder *encoder = 4072 intel_attached_encoder(to_intel_connector(connector)); 4073 struct intel_crtc *possible_crtc; 4074 struct intel_crtc *crtc = NULL; 4075 struct drm_device *dev = encoder->base.dev; 4076 struct drm_i915_private *dev_priv = to_i915(dev); 4077 struct drm_mode_config *config = &dev->mode_config; 4078 struct drm_atomic_state *state = NULL, *restore_state = NULL; 4079 struct drm_connector_state *connector_state; 4080 struct intel_crtc_state *crtc_state; 4081 int ret; 4082 4083 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 4084 connector->base.id, connector->name, 4085 encoder->base.base.id, encoder->base.name); 4086 4087 old->restore_state = NULL; 4088 4089 drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex)); 4090 4091 /* 4092 * Algorithm gets a little messy: 4093 * 4094 * - if the connector already has an assigned crtc, use it (but make 4095 * sure it's on first) 4096 * 4097 * - try to find the first unused crtc that can drive this connector, 4098 * and use that if we find one 4099 */ 4100 4101 /* See if we already have a CRTC for this connector */ 4102 if (connector->state->crtc) { 4103 crtc = to_intel_crtc(connector->state->crtc); 4104 4105 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4106 if (ret) 4107 goto fail; 4108 4109 /* Make sure the crtc and connector are running */ 4110 goto found; 4111 } 4112 4113 /* Find an unused one (if possible) */ 4114 for_each_intel_crtc(dev, possible_crtc) { 4115 if (!(encoder->base.possible_crtcs & 4116 drm_crtc_mask(&possible_crtc->base))) 4117 continue; 4118 4119 ret = drm_modeset_lock(&possible_crtc->base.mutex, ctx); 4120 if (ret) 4121 goto fail; 4122 4123 if (possible_crtc->base.state->enable) { 4124 drm_modeset_unlock(&possible_crtc->base.mutex); 4125 continue; 4126 } 4127 4128 crtc = possible_crtc; 4129 break; 4130 } 4131 4132 /* 4133 * If we didn't find an unused CRTC, don't use any. 4134 */ 4135 if (!crtc) { 4136 drm_dbg_kms(&dev_priv->drm, 4137 "no pipe available for load-detect\n"); 4138 ret = -ENODEV; 4139 goto fail; 4140 } 4141 4142 found: 4143 state = drm_atomic_state_alloc(dev); 4144 restore_state = drm_atomic_state_alloc(dev); 4145 if (!state || !restore_state) { 4146 ret = -ENOMEM; 4147 goto fail; 4148 } 4149 4150 state->acquire_ctx = ctx; 4151 restore_state->acquire_ctx = ctx; 4152 4153 connector_state = drm_atomic_get_connector_state(state, connector); 4154 if (IS_ERR(connector_state)) { 4155 ret = PTR_ERR(connector_state); 4156 goto fail; 4157 } 4158 4159 ret = drm_atomic_set_crtc_for_connector(connector_state, &crtc->base); 4160 if (ret) 4161 goto fail; 4162 4163 crtc_state = intel_atomic_get_crtc_state(state, crtc); 4164 if (IS_ERR(crtc_state)) { 4165 ret = PTR_ERR(crtc_state); 4166 goto fail; 4167 } 4168 4169 crtc_state->uapi.active = true; 4170 4171 ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi, 4172 &load_detect_mode); 4173 if (ret) 4174 goto fail; 4175 4176 ret = intel_modeset_disable_planes(state, &crtc->base); 4177 if (ret) 4178 goto fail; 4179 4180 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); 4181 if (!ret) 4182 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, &crtc->base)); 4183 if (!ret) 4184 ret = drm_atomic_add_affected_planes(restore_state, &crtc->base); 4185 if (ret) { 4186 drm_dbg_kms(&dev_priv->drm, 4187 "Failed to create a copy of old state to restore: %i\n", 4188 ret); 4189 goto fail; 4190 } 4191 4192 ret = drm_atomic_commit(state); 4193 if (ret) { 4194 drm_dbg_kms(&dev_priv->drm, 4195 "failed to set mode on load-detect pipe\n"); 4196 goto fail; 4197 } 4198 4199 old->restore_state = restore_state; 4200 drm_atomic_state_put(state); 4201 4202 /* let the connector get through one full cycle before testing */ 4203 intel_crtc_wait_for_next_vblank(crtc); 4204 4205 return true; 4206 4207 fail: 4208 if (state) { 4209 drm_atomic_state_put(state); 4210 state = NULL; 4211 } 4212 if (restore_state) { 4213 drm_atomic_state_put(restore_state); 4214 restore_state = NULL; 4215 } 4216 4217 if (ret == -EDEADLK) 4218 return ret; 4219 4220 return false; 4221 } 4222 4223 void intel_release_load_detect_pipe(struct drm_connector *connector, 4224 struct intel_load_detect_pipe *old, 4225 struct drm_modeset_acquire_ctx *ctx) 4226 { 4227 struct intel_encoder *intel_encoder = 4228 intel_attached_encoder(to_intel_connector(connector)); 4229 struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev); 4230 struct drm_encoder *encoder = &intel_encoder->base; 4231 struct drm_atomic_state *state = old->restore_state; 4232 int ret; 4233 4234 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 4235 connector->base.id, connector->name, 4236 encoder->base.id, encoder->name); 4237 4238 if (!state) 4239 return; 4240 4241 ret = drm_atomic_helper_commit_duplicated_state(state, ctx); 4242 if (ret) 4243 drm_dbg_kms(&i915->drm, 4244 "Couldn't release load detect pipe: %i\n", ret); 4245 drm_atomic_state_put(state); 4246 } 4247 4248 static int i9xx_pll_refclk(struct drm_device *dev, 4249 const struct intel_crtc_state *pipe_config) 4250 { 4251 struct drm_i915_private *dev_priv = to_i915(dev); 4252 u32 dpll = pipe_config->dpll_hw_state.dpll; 4253 4254 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) 4255 return dev_priv->display.vbt.lvds_ssc_freq; 4256 else if (HAS_PCH_SPLIT(dev_priv)) 4257 return 120000; 4258 else if (DISPLAY_VER(dev_priv) != 2) 4259 return 96000; 4260 else 4261 return 48000; 4262 } 4263 4264 /* Returns the clock of the currently programmed mode of the given pipe. */ 4265 void i9xx_crtc_clock_get(struct intel_crtc *crtc, 4266 struct intel_crtc_state *pipe_config) 4267 { 4268 struct drm_device *dev = crtc->base.dev; 4269 struct drm_i915_private *dev_priv = to_i915(dev); 4270 u32 dpll = pipe_config->dpll_hw_state.dpll; 4271 u32 fp; 4272 struct dpll clock; 4273 int port_clock; 4274 int refclk = i9xx_pll_refclk(dev, pipe_config); 4275 4276 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 4277 fp = pipe_config->dpll_hw_state.fp0; 4278 else 4279 fp = pipe_config->dpll_hw_state.fp1; 4280 4281 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 4282 if (IS_PINEVIEW(dev_priv)) { 4283 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; 4284 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; 4285 } else { 4286 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 4287 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 4288 } 4289 4290 if (DISPLAY_VER(dev_priv) != 2) { 4291 if (IS_PINEVIEW(dev_priv)) 4292 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> 4293 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); 4294 else 4295 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> 4296 DPLL_FPA01_P1_POST_DIV_SHIFT); 4297 4298 switch (dpll & DPLL_MODE_MASK) { 4299 case DPLLB_MODE_DAC_SERIAL: 4300 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 4301 5 : 10; 4302 break; 4303 case DPLLB_MODE_LVDS: 4304 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 4305 7 : 14; 4306 break; 4307 default: 4308 drm_dbg_kms(&dev_priv->drm, 4309 "Unknown DPLL mode %08x in programmed " 4310 "mode\n", (int)(dpll & DPLL_MODE_MASK)); 4311 return; 4312 } 4313 4314 if (IS_PINEVIEW(dev_priv)) 4315 port_clock = pnv_calc_dpll_params(refclk, &clock); 4316 else 4317 port_clock = i9xx_calc_dpll_params(refclk, &clock); 4318 } else { 4319 enum pipe lvds_pipe; 4320 4321 if (IS_I85X(dev_priv) && 4322 intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) && 4323 lvds_pipe == crtc->pipe) { 4324 u32 lvds = intel_de_read(dev_priv, LVDS); 4325 4326 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 4327 DPLL_FPA01_P1_POST_DIV_SHIFT); 4328 4329 if (lvds & LVDS_CLKB_POWER_UP) 4330 clock.p2 = 7; 4331 else 4332 clock.p2 = 14; 4333 } else { 4334 if (dpll & PLL_P1_DIVIDE_BY_TWO) 4335 clock.p1 = 2; 4336 else { 4337 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 4338 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 4339 } 4340 if (dpll & PLL_P2_DIVIDE_BY_4) 4341 clock.p2 = 4; 4342 else 4343 clock.p2 = 2; 4344 } 4345 4346 port_clock = i9xx_calc_dpll_params(refclk, &clock); 4347 } 4348 4349 /* 4350 * This value includes pixel_multiplier. We will use 4351 * port_clock to compute adjusted_mode.crtc_clock in the 4352 * encoder's get_config() function. 4353 */ 4354 pipe_config->port_clock = port_clock; 4355 } 4356 4357 int intel_dotclock_calculate(int link_freq, 4358 const struct intel_link_m_n *m_n) 4359 { 4360 /* 4361 * The calculation for the data clock is: 4362 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp 4363 * But we want to avoid losing precison if possible, so: 4364 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) 4365 * 4366 * and the link clock is simpler: 4367 * link_clock = (m * link_clock) / n 4368 */ 4369 4370 if (!m_n->link_n) 4371 return 0; 4372 4373 return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq), 4374 m_n->link_n); 4375 } 4376 4377 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config) 4378 { 4379 int dotclock; 4380 4381 if (intel_crtc_has_dp_encoder(pipe_config)) 4382 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 4383 &pipe_config->dp_m_n); 4384 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) 4385 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24, 4386 pipe_config->pipe_bpp); 4387 else 4388 dotclock = pipe_config->port_clock; 4389 4390 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 4391 !intel_crtc_has_dp_encoder(pipe_config)) 4392 dotclock *= 2; 4393 4394 if (pipe_config->pixel_multiplier) 4395 dotclock /= pipe_config->pixel_multiplier; 4396 4397 return dotclock; 4398 } 4399 4400 /* Returns the currently programmed mode of the given encoder. */ 4401 struct drm_display_mode * 4402 intel_encoder_current_mode(struct intel_encoder *encoder) 4403 { 4404 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4405 struct intel_crtc_state *crtc_state; 4406 struct drm_display_mode *mode; 4407 struct intel_crtc *crtc; 4408 enum pipe pipe; 4409 4410 if (!encoder->get_hw_state(encoder, &pipe)) 4411 return NULL; 4412 4413 crtc = intel_crtc_for_pipe(dev_priv, pipe); 4414 4415 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 4416 if (!mode) 4417 return NULL; 4418 4419 crtc_state = intel_crtc_state_alloc(crtc); 4420 if (!crtc_state) { 4421 kfree(mode); 4422 return NULL; 4423 } 4424 4425 if (!intel_crtc_get_pipe_config(crtc_state)) { 4426 kfree(crtc_state); 4427 kfree(mode); 4428 return NULL; 4429 } 4430 4431 intel_encoder_get_config(encoder, crtc_state); 4432 4433 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode); 4434 4435 kfree(crtc_state); 4436 4437 return mode; 4438 } 4439 4440 static bool encoders_cloneable(const struct intel_encoder *a, 4441 const struct intel_encoder *b) 4442 { 4443 /* masks could be asymmetric, so check both ways */ 4444 return a == b || (a->cloneable & BIT(b->type) && 4445 b->cloneable & BIT(a->type)); 4446 } 4447 4448 static bool check_single_encoder_cloning(struct intel_atomic_state *state, 4449 struct intel_crtc *crtc, 4450 struct intel_encoder *encoder) 4451 { 4452 struct intel_encoder *source_encoder; 4453 struct drm_connector *connector; 4454 struct drm_connector_state *connector_state; 4455 int i; 4456 4457 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4458 if (connector_state->crtc != &crtc->base) 4459 continue; 4460 4461 source_encoder = 4462 to_intel_encoder(connector_state->best_encoder); 4463 if (!encoders_cloneable(encoder, source_encoder)) 4464 return false; 4465 } 4466 4467 return true; 4468 } 4469 4470 static int icl_add_linked_planes(struct intel_atomic_state *state) 4471 { 4472 struct intel_plane *plane, *linked; 4473 struct intel_plane_state *plane_state, *linked_plane_state; 4474 int i; 4475 4476 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4477 linked = plane_state->planar_linked_plane; 4478 4479 if (!linked) 4480 continue; 4481 4482 linked_plane_state = intel_atomic_get_plane_state(state, linked); 4483 if (IS_ERR(linked_plane_state)) 4484 return PTR_ERR(linked_plane_state); 4485 4486 drm_WARN_ON(state->base.dev, 4487 linked_plane_state->planar_linked_plane != plane); 4488 drm_WARN_ON(state->base.dev, 4489 linked_plane_state->planar_slave == plane_state->planar_slave); 4490 } 4491 4492 return 0; 4493 } 4494 4495 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state) 4496 { 4497 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4498 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4499 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 4500 struct intel_plane *plane, *linked; 4501 struct intel_plane_state *plane_state; 4502 int i; 4503 4504 if (DISPLAY_VER(dev_priv) < 11) 4505 return 0; 4506 4507 /* 4508 * Destroy all old plane links and make the slave plane invisible 4509 * in the crtc_state->active_planes mask. 4510 */ 4511 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4512 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane) 4513 continue; 4514 4515 plane_state->planar_linked_plane = NULL; 4516 if (plane_state->planar_slave && !plane_state->uapi.visible) { 4517 crtc_state->enabled_planes &= ~BIT(plane->id); 4518 crtc_state->active_planes &= ~BIT(plane->id); 4519 crtc_state->update_planes |= BIT(plane->id); 4520 crtc_state->data_rate[plane->id] = 0; 4521 crtc_state->rel_data_rate[plane->id] = 0; 4522 } 4523 4524 plane_state->planar_slave = false; 4525 } 4526 4527 if (!crtc_state->nv12_planes) 4528 return 0; 4529 4530 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4531 struct intel_plane_state *linked_state = NULL; 4532 4533 if (plane->pipe != crtc->pipe || 4534 !(crtc_state->nv12_planes & BIT(plane->id))) 4535 continue; 4536 4537 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) { 4538 if (!icl_is_nv12_y_plane(dev_priv, linked->id)) 4539 continue; 4540 4541 if (crtc_state->active_planes & BIT(linked->id)) 4542 continue; 4543 4544 linked_state = intel_atomic_get_plane_state(state, linked); 4545 if (IS_ERR(linked_state)) 4546 return PTR_ERR(linked_state); 4547 4548 break; 4549 } 4550 4551 if (!linked_state) { 4552 drm_dbg_kms(&dev_priv->drm, 4553 "Need %d free Y planes for planar YUV\n", 4554 hweight8(crtc_state->nv12_planes)); 4555 4556 return -EINVAL; 4557 } 4558 4559 plane_state->planar_linked_plane = linked; 4560 4561 linked_state->planar_slave = true; 4562 linked_state->planar_linked_plane = plane; 4563 crtc_state->enabled_planes |= BIT(linked->id); 4564 crtc_state->active_planes |= BIT(linked->id); 4565 crtc_state->update_planes |= BIT(linked->id); 4566 crtc_state->data_rate[linked->id] = 4567 crtc_state->data_rate_y[plane->id]; 4568 crtc_state->rel_data_rate[linked->id] = 4569 crtc_state->rel_data_rate_y[plane->id]; 4570 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n", 4571 linked->base.name, plane->base.name); 4572 4573 /* Copy parameters to slave plane */ 4574 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE; 4575 linked_state->color_ctl = plane_state->color_ctl; 4576 linked_state->view = plane_state->view; 4577 linked_state->decrypt = plane_state->decrypt; 4578 4579 intel_plane_copy_hw_state(linked_state, plane_state); 4580 linked_state->uapi.src = plane_state->uapi.src; 4581 linked_state->uapi.dst = plane_state->uapi.dst; 4582 4583 if (icl_is_hdr_plane(dev_priv, plane->id)) { 4584 if (linked->id == PLANE_SPRITE5) 4585 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL; 4586 else if (linked->id == PLANE_SPRITE4) 4587 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL; 4588 else if (linked->id == PLANE_SPRITE3) 4589 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL; 4590 else if (linked->id == PLANE_SPRITE2) 4591 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL; 4592 else 4593 MISSING_CASE(linked->id); 4594 } 4595 } 4596 4597 return 0; 4598 } 4599 4600 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state) 4601 { 4602 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 4603 struct intel_atomic_state *state = 4604 to_intel_atomic_state(new_crtc_state->uapi.state); 4605 const struct intel_crtc_state *old_crtc_state = 4606 intel_atomic_get_old_crtc_state(state, crtc); 4607 4608 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes; 4609 } 4610 4611 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) 4612 { 4613 const struct drm_display_mode *pipe_mode = 4614 &crtc_state->hw.pipe_mode; 4615 int linetime_wm; 4616 4617 if (!crtc_state->hw.enable) 4618 return 0; 4619 4620 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4621 pipe_mode->crtc_clock); 4622 4623 return min(linetime_wm, 0x1ff); 4624 } 4625 4626 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, 4627 const struct intel_cdclk_state *cdclk_state) 4628 { 4629 const struct drm_display_mode *pipe_mode = 4630 &crtc_state->hw.pipe_mode; 4631 int linetime_wm; 4632 4633 if (!crtc_state->hw.enable) 4634 return 0; 4635 4636 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4637 cdclk_state->logical.cdclk); 4638 4639 return min(linetime_wm, 0x1ff); 4640 } 4641 4642 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) 4643 { 4644 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4645 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4646 const struct drm_display_mode *pipe_mode = 4647 &crtc_state->hw.pipe_mode; 4648 int linetime_wm; 4649 4650 if (!crtc_state->hw.enable) 4651 return 0; 4652 4653 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8, 4654 crtc_state->pixel_rate); 4655 4656 /* Display WA #1135: BXT:ALL GLK:ALL */ 4657 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 4658 skl_watermark_ipc_enabled(dev_priv)) 4659 linetime_wm /= 2; 4660 4661 return min(linetime_wm, 0x1ff); 4662 } 4663 4664 static int hsw_compute_linetime_wm(struct intel_atomic_state *state, 4665 struct intel_crtc *crtc) 4666 { 4667 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4668 struct intel_crtc_state *crtc_state = 4669 intel_atomic_get_new_crtc_state(state, crtc); 4670 const struct intel_cdclk_state *cdclk_state; 4671 4672 if (DISPLAY_VER(dev_priv) >= 9) 4673 crtc_state->linetime = skl_linetime_wm(crtc_state); 4674 else 4675 crtc_state->linetime = hsw_linetime_wm(crtc_state); 4676 4677 if (!hsw_crtc_supports_ips(crtc)) 4678 return 0; 4679 4680 cdclk_state = intel_atomic_get_cdclk_state(state); 4681 if (IS_ERR(cdclk_state)) 4682 return PTR_ERR(cdclk_state); 4683 4684 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state, 4685 cdclk_state); 4686 4687 return 0; 4688 } 4689 4690 static int intel_crtc_atomic_check(struct intel_atomic_state *state, 4691 struct intel_crtc *crtc) 4692 { 4693 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4694 struct intel_crtc_state *crtc_state = 4695 intel_atomic_get_new_crtc_state(state, crtc); 4696 int ret; 4697 4698 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) && 4699 intel_crtc_needs_modeset(crtc_state) && 4700 !crtc_state->hw.active) 4701 crtc_state->update_wm_post = true; 4702 4703 if (intel_crtc_needs_modeset(crtc_state)) { 4704 ret = intel_dpll_crtc_get_shared_dpll(state, crtc); 4705 if (ret) 4706 return ret; 4707 } 4708 4709 /* 4710 * May need to update pipe gamma enable bits 4711 * when C8 planes are getting enabled/disabled. 4712 */ 4713 if (c8_planes_changed(crtc_state)) 4714 crtc_state->uapi.color_mgmt_changed = true; 4715 4716 if (intel_crtc_needs_color_update(crtc_state)) { 4717 ret = intel_color_check(crtc_state); 4718 if (ret) 4719 return ret; 4720 } 4721 4722 ret = intel_compute_pipe_wm(state, crtc); 4723 if (ret) { 4724 drm_dbg_kms(&dev_priv->drm, 4725 "Target pipe watermarks are invalid\n"); 4726 return ret; 4727 } 4728 4729 /* 4730 * Calculate 'intermediate' watermarks that satisfy both the 4731 * old state and the new state. We can program these 4732 * immediately. 4733 */ 4734 ret = intel_compute_intermediate_wm(state, crtc); 4735 if (ret) { 4736 drm_dbg_kms(&dev_priv->drm, 4737 "No valid intermediate pipe watermarks are possible\n"); 4738 return ret; 4739 } 4740 4741 if (DISPLAY_VER(dev_priv) >= 9) { 4742 if (intel_crtc_needs_modeset(crtc_state) || 4743 intel_crtc_needs_fastset(crtc_state)) { 4744 ret = skl_update_scaler_crtc(crtc_state); 4745 if (ret) 4746 return ret; 4747 } 4748 4749 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state); 4750 if (ret) 4751 return ret; 4752 } 4753 4754 if (HAS_IPS(dev_priv)) { 4755 ret = hsw_ips_compute_config(state, crtc); 4756 if (ret) 4757 return ret; 4758 } 4759 4760 if (DISPLAY_VER(dev_priv) >= 9 || 4761 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 4762 ret = hsw_compute_linetime_wm(state, crtc); 4763 if (ret) 4764 return ret; 4765 4766 } 4767 4768 ret = intel_psr2_sel_fetch_update(state, crtc); 4769 if (ret) 4770 return ret; 4771 4772 return 0; 4773 } 4774 4775 static int 4776 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state, 4777 struct intel_crtc_state *crtc_state) 4778 { 4779 struct drm_connector *connector = conn_state->connector; 4780 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 4781 const struct drm_display_info *info = &connector->display_info; 4782 int bpp; 4783 4784 switch (conn_state->max_bpc) { 4785 case 6 ... 7: 4786 bpp = 6 * 3; 4787 break; 4788 case 8 ... 9: 4789 bpp = 8 * 3; 4790 break; 4791 case 10 ... 11: 4792 bpp = 10 * 3; 4793 break; 4794 case 12 ... 16: 4795 bpp = 12 * 3; 4796 break; 4797 default: 4798 MISSING_CASE(conn_state->max_bpc); 4799 return -EINVAL; 4800 } 4801 4802 if (bpp < crtc_state->pipe_bpp) { 4803 drm_dbg_kms(&i915->drm, 4804 "[CONNECTOR:%d:%s] Limiting display bpp to %d " 4805 "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n", 4806 connector->base.id, connector->name, 4807 bpp, 3 * info->bpc, 4808 3 * conn_state->max_requested_bpc, 4809 crtc_state->pipe_bpp); 4810 4811 crtc_state->pipe_bpp = bpp; 4812 } 4813 4814 return 0; 4815 } 4816 4817 static int 4818 compute_baseline_pipe_bpp(struct intel_atomic_state *state, 4819 struct intel_crtc *crtc) 4820 { 4821 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4822 struct intel_crtc_state *crtc_state = 4823 intel_atomic_get_new_crtc_state(state, crtc); 4824 struct drm_connector *connector; 4825 struct drm_connector_state *connector_state; 4826 int bpp, i; 4827 4828 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 4829 IS_CHERRYVIEW(dev_priv))) 4830 bpp = 10*3; 4831 else if (DISPLAY_VER(dev_priv) >= 5) 4832 bpp = 12*3; 4833 else 4834 bpp = 8*3; 4835 4836 crtc_state->pipe_bpp = bpp; 4837 4838 /* Clamp display bpp to connector max bpp */ 4839 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4840 int ret; 4841 4842 if (connector_state->crtc != &crtc->base) 4843 continue; 4844 4845 ret = compute_sink_pipe_bpp(connector_state, crtc_state); 4846 if (ret) 4847 return ret; 4848 } 4849 4850 return 0; 4851 } 4852 4853 static bool check_digital_port_conflicts(struct intel_atomic_state *state) 4854 { 4855 struct drm_device *dev = state->base.dev; 4856 struct drm_connector *connector; 4857 struct drm_connector_list_iter conn_iter; 4858 unsigned int used_ports = 0; 4859 unsigned int used_mst_ports = 0; 4860 bool ret = true; 4861 4862 /* 4863 * We're going to peek into connector->state, 4864 * hence connection_mutex must be held. 4865 */ 4866 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex); 4867 4868 /* 4869 * Walk the connector list instead of the encoder 4870 * list to detect the problem on ddi platforms 4871 * where there's just one encoder per digital port. 4872 */ 4873 drm_connector_list_iter_begin(dev, &conn_iter); 4874 drm_for_each_connector_iter(connector, &conn_iter) { 4875 struct drm_connector_state *connector_state; 4876 struct intel_encoder *encoder; 4877 4878 connector_state = 4879 drm_atomic_get_new_connector_state(&state->base, 4880 connector); 4881 if (!connector_state) 4882 connector_state = connector->state; 4883 4884 if (!connector_state->best_encoder) 4885 continue; 4886 4887 encoder = to_intel_encoder(connector_state->best_encoder); 4888 4889 drm_WARN_ON(dev, !connector_state->crtc); 4890 4891 switch (encoder->type) { 4892 case INTEL_OUTPUT_DDI: 4893 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev)))) 4894 break; 4895 fallthrough; 4896 case INTEL_OUTPUT_DP: 4897 case INTEL_OUTPUT_HDMI: 4898 case INTEL_OUTPUT_EDP: 4899 /* the same port mustn't appear more than once */ 4900 if (used_ports & BIT(encoder->port)) 4901 ret = false; 4902 4903 used_ports |= BIT(encoder->port); 4904 break; 4905 case INTEL_OUTPUT_DP_MST: 4906 used_mst_ports |= 4907 1 << encoder->port; 4908 break; 4909 default: 4910 break; 4911 } 4912 } 4913 drm_connector_list_iter_end(&conn_iter); 4914 4915 /* can't mix MST and SST/HDMI on the same port */ 4916 if (used_ports & used_mst_ports) 4917 return false; 4918 4919 return ret; 4920 } 4921 4922 static void 4923 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state, 4924 struct intel_crtc *crtc) 4925 { 4926 struct intel_crtc_state *crtc_state = 4927 intel_atomic_get_new_crtc_state(state, crtc); 4928 4929 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 4930 4931 drm_property_replace_blob(&crtc_state->hw.degamma_lut, 4932 crtc_state->uapi.degamma_lut); 4933 drm_property_replace_blob(&crtc_state->hw.gamma_lut, 4934 crtc_state->uapi.gamma_lut); 4935 drm_property_replace_blob(&crtc_state->hw.ctm, 4936 crtc_state->uapi.ctm); 4937 } 4938 4939 static void 4940 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state, 4941 struct intel_crtc *crtc) 4942 { 4943 struct intel_crtc_state *crtc_state = 4944 intel_atomic_get_new_crtc_state(state, crtc); 4945 4946 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 4947 4948 crtc_state->hw.enable = crtc_state->uapi.enable; 4949 crtc_state->hw.active = crtc_state->uapi.active; 4950 drm_mode_copy(&crtc_state->hw.mode, 4951 &crtc_state->uapi.mode); 4952 drm_mode_copy(&crtc_state->hw.adjusted_mode, 4953 &crtc_state->uapi.adjusted_mode); 4954 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter; 4955 4956 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 4957 } 4958 4959 static void 4960 copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state, 4961 struct intel_crtc *slave_crtc) 4962 { 4963 struct intel_crtc_state *slave_crtc_state = 4964 intel_atomic_get_new_crtc_state(state, slave_crtc); 4965 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 4966 const struct intel_crtc_state *master_crtc_state = 4967 intel_atomic_get_new_crtc_state(state, master_crtc); 4968 4969 drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut, 4970 master_crtc_state->hw.degamma_lut); 4971 drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut, 4972 master_crtc_state->hw.gamma_lut); 4973 drm_property_replace_blob(&slave_crtc_state->hw.ctm, 4974 master_crtc_state->hw.ctm); 4975 4976 slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed; 4977 } 4978 4979 static int 4980 copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state, 4981 struct intel_crtc *slave_crtc) 4982 { 4983 struct intel_crtc_state *slave_crtc_state = 4984 intel_atomic_get_new_crtc_state(state, slave_crtc); 4985 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 4986 const struct intel_crtc_state *master_crtc_state = 4987 intel_atomic_get_new_crtc_state(state, master_crtc); 4988 struct intel_crtc_state *saved_state; 4989 4990 WARN_ON(master_crtc_state->bigjoiner_pipes != 4991 slave_crtc_state->bigjoiner_pipes); 4992 4993 saved_state = kmemdup(master_crtc_state, sizeof(*saved_state), GFP_KERNEL); 4994 if (!saved_state) 4995 return -ENOMEM; 4996 4997 /* preserve some things from the slave's original crtc state */ 4998 saved_state->uapi = slave_crtc_state->uapi; 4999 saved_state->scaler_state = slave_crtc_state->scaler_state; 5000 saved_state->shared_dpll = slave_crtc_state->shared_dpll; 5001 saved_state->dpll_hw_state = slave_crtc_state->dpll_hw_state; 5002 saved_state->crc_enabled = slave_crtc_state->crc_enabled; 5003 5004 intel_crtc_free_hw_state(slave_crtc_state); 5005 memcpy(slave_crtc_state, saved_state, sizeof(*slave_crtc_state)); 5006 kfree(saved_state); 5007 5008 /* Re-init hw state */ 5009 memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw)); 5010 slave_crtc_state->hw.enable = master_crtc_state->hw.enable; 5011 slave_crtc_state->hw.active = master_crtc_state->hw.active; 5012 drm_mode_copy(&slave_crtc_state->hw.mode, 5013 &master_crtc_state->hw.mode); 5014 drm_mode_copy(&slave_crtc_state->hw.pipe_mode, 5015 &master_crtc_state->hw.pipe_mode); 5016 drm_mode_copy(&slave_crtc_state->hw.adjusted_mode, 5017 &master_crtc_state->hw.adjusted_mode); 5018 slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter; 5019 5020 copy_bigjoiner_crtc_state_nomodeset(state, slave_crtc); 5021 5022 slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed; 5023 slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed; 5024 slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed; 5025 5026 WARN_ON(master_crtc_state->bigjoiner_pipes != 5027 slave_crtc_state->bigjoiner_pipes); 5028 5029 return 0; 5030 } 5031 5032 static int 5033 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state, 5034 struct intel_crtc *crtc) 5035 { 5036 struct intel_crtc_state *crtc_state = 5037 intel_atomic_get_new_crtc_state(state, crtc); 5038 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5039 struct intel_crtc_state *saved_state; 5040 5041 saved_state = intel_crtc_state_alloc(crtc); 5042 if (!saved_state) 5043 return -ENOMEM; 5044 5045 /* free the old crtc_state->hw members */ 5046 intel_crtc_free_hw_state(crtc_state); 5047 5048 /* FIXME: before the switch to atomic started, a new pipe_config was 5049 * kzalloc'd. Code that depends on any field being zero should be 5050 * fixed, so that the crtc_state can be safely duplicated. For now, 5051 * only fields that are know to not cause problems are preserved. */ 5052 5053 saved_state->uapi = crtc_state->uapi; 5054 saved_state->scaler_state = crtc_state->scaler_state; 5055 saved_state->shared_dpll = crtc_state->shared_dpll; 5056 saved_state->dpll_hw_state = crtc_state->dpll_hw_state; 5057 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, 5058 sizeof(saved_state->icl_port_dplls)); 5059 saved_state->crc_enabled = crtc_state->crc_enabled; 5060 if (IS_G4X(dev_priv) || 5061 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5062 saved_state->wm = crtc_state->wm; 5063 5064 memcpy(crtc_state, saved_state, sizeof(*crtc_state)); 5065 kfree(saved_state); 5066 5067 intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc); 5068 5069 return 0; 5070 } 5071 5072 static int 5073 intel_modeset_pipe_config(struct intel_atomic_state *state, 5074 struct intel_crtc *crtc) 5075 { 5076 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 5077 struct intel_crtc_state *crtc_state = 5078 intel_atomic_get_new_crtc_state(state, crtc); 5079 struct drm_connector *connector; 5080 struct drm_connector_state *connector_state; 5081 int pipe_src_w, pipe_src_h; 5082 int base_bpp, ret, i; 5083 bool retry = true; 5084 5085 crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe; 5086 5087 crtc_state->framestart_delay = 1; 5088 5089 /* 5090 * Sanitize sync polarity flags based on requested ones. If neither 5091 * positive or negative polarity is requested, treat this as meaning 5092 * negative polarity. 5093 */ 5094 if (!(crtc_state->hw.adjusted_mode.flags & 5095 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) 5096 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; 5097 5098 if (!(crtc_state->hw.adjusted_mode.flags & 5099 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 5100 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; 5101 5102 ret = compute_baseline_pipe_bpp(state, crtc); 5103 if (ret) 5104 return ret; 5105 5106 base_bpp = crtc_state->pipe_bpp; 5107 5108 /* 5109 * Determine the real pipe dimensions. Note that stereo modes can 5110 * increase the actual pipe size due to the frame doubling and 5111 * insertion of additional space for blanks between the frame. This 5112 * is stored in the crtc timings. We use the requested mode to do this 5113 * computation to clearly distinguish it from the adjusted mode, which 5114 * can be changed by the connectors in the below retry loop. 5115 */ 5116 drm_mode_get_hv_timing(&crtc_state->hw.mode, 5117 &pipe_src_w, &pipe_src_h); 5118 drm_rect_init(&crtc_state->pipe_src, 0, 0, 5119 pipe_src_w, pipe_src_h); 5120 5121 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5122 struct intel_encoder *encoder = 5123 to_intel_encoder(connector_state->best_encoder); 5124 5125 if (connector_state->crtc != &crtc->base) 5126 continue; 5127 5128 if (!check_single_encoder_cloning(state, crtc, encoder)) { 5129 drm_dbg_kms(&i915->drm, 5130 "[ENCODER:%d:%s] rejecting invalid cloning configuration\n", 5131 encoder->base.base.id, encoder->base.name); 5132 return -EINVAL; 5133 } 5134 5135 /* 5136 * Determine output_types before calling the .compute_config() 5137 * hooks so that the hooks can use this information safely. 5138 */ 5139 if (encoder->compute_output_type) 5140 crtc_state->output_types |= 5141 BIT(encoder->compute_output_type(encoder, crtc_state, 5142 connector_state)); 5143 else 5144 crtc_state->output_types |= BIT(encoder->type); 5145 } 5146 5147 encoder_retry: 5148 /* Ensure the port clock defaults are reset when retrying. */ 5149 crtc_state->port_clock = 0; 5150 crtc_state->pixel_multiplier = 1; 5151 5152 /* Fill in default crtc timings, allow encoders to overwrite them. */ 5153 drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode, 5154 CRTC_STEREO_DOUBLE); 5155 5156 /* Pass our mode to the connectors and the CRTC to give them a chance to 5157 * adjust it according to limitations or connector properties, and also 5158 * a chance to reject the mode entirely. 5159 */ 5160 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5161 struct intel_encoder *encoder = 5162 to_intel_encoder(connector_state->best_encoder); 5163 5164 if (connector_state->crtc != &crtc->base) 5165 continue; 5166 5167 ret = encoder->compute_config(encoder, crtc_state, 5168 connector_state); 5169 if (ret == -EDEADLK) 5170 return ret; 5171 if (ret < 0) { 5172 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n", 5173 encoder->base.base.id, encoder->base.name, ret); 5174 return ret; 5175 } 5176 } 5177 5178 /* Set default port clock if not overwritten by the encoder. Needs to be 5179 * done afterwards in case the encoder adjusts the mode. */ 5180 if (!crtc_state->port_clock) 5181 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock 5182 * crtc_state->pixel_multiplier; 5183 5184 ret = intel_crtc_compute_config(state, crtc); 5185 if (ret == -EDEADLK) 5186 return ret; 5187 if (ret == -EAGAIN) { 5188 if (drm_WARN(&i915->drm, !retry, 5189 "[CRTC:%d:%s] loop in pipe configuration computation\n", 5190 crtc->base.base.id, crtc->base.name)) 5191 return -EINVAL; 5192 5193 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] bw constrained, retrying\n", 5194 crtc->base.base.id, crtc->base.name); 5195 retry = false; 5196 goto encoder_retry; 5197 } 5198 if (ret < 0) { 5199 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n", 5200 crtc->base.base.id, crtc->base.name, ret); 5201 return ret; 5202 } 5203 5204 /* Dithering seems to not pass-through bits correctly when it should, so 5205 * only enable it on 6bpc panels and when its not a compliance 5206 * test requesting 6bpc video pattern. 5207 */ 5208 crtc_state->dither = (crtc_state->pipe_bpp == 6*3) && 5209 !crtc_state->dither_force_disable; 5210 drm_dbg_kms(&i915->drm, 5211 "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n", 5212 crtc->base.base.id, crtc->base.name, 5213 base_bpp, crtc_state->pipe_bpp, crtc_state->dither); 5214 5215 return 0; 5216 } 5217 5218 static int 5219 intel_modeset_pipe_config_late(struct intel_atomic_state *state, 5220 struct intel_crtc *crtc) 5221 { 5222 struct intel_crtc_state *crtc_state = 5223 intel_atomic_get_new_crtc_state(state, crtc); 5224 struct drm_connector_state *conn_state; 5225 struct drm_connector *connector; 5226 int i; 5227 5228 intel_bigjoiner_adjust_pipe_src(crtc_state); 5229 5230 for_each_new_connector_in_state(&state->base, connector, 5231 conn_state, i) { 5232 struct intel_encoder *encoder = 5233 to_intel_encoder(conn_state->best_encoder); 5234 int ret; 5235 5236 if (conn_state->crtc != &crtc->base || 5237 !encoder->compute_config_late) 5238 continue; 5239 5240 ret = encoder->compute_config_late(encoder, crtc_state, 5241 conn_state); 5242 if (ret) 5243 return ret; 5244 } 5245 5246 return 0; 5247 } 5248 5249 bool intel_fuzzy_clock_check(int clock1, int clock2) 5250 { 5251 int diff; 5252 5253 if (clock1 == clock2) 5254 return true; 5255 5256 if (!clock1 || !clock2) 5257 return false; 5258 5259 diff = abs(clock1 - clock2); 5260 5261 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) 5262 return true; 5263 5264 return false; 5265 } 5266 5267 static bool 5268 intel_compare_link_m_n(const struct intel_link_m_n *m_n, 5269 const struct intel_link_m_n *m2_n2) 5270 { 5271 return m_n->tu == m2_n2->tu && 5272 m_n->data_m == m2_n2->data_m && 5273 m_n->data_n == m2_n2->data_n && 5274 m_n->link_m == m2_n2->link_m && 5275 m_n->link_n == m2_n2->link_n; 5276 } 5277 5278 static bool 5279 intel_compare_infoframe(const union hdmi_infoframe *a, 5280 const union hdmi_infoframe *b) 5281 { 5282 return memcmp(a, b, sizeof(*a)) == 0; 5283 } 5284 5285 static bool 5286 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a, 5287 const struct drm_dp_vsc_sdp *b) 5288 { 5289 return memcmp(a, b, sizeof(*a)) == 0; 5290 } 5291 5292 static bool 5293 intel_compare_buffer(const u8 *a, const u8 *b, size_t len) 5294 { 5295 return memcmp(a, b, len) == 0; 5296 } 5297 5298 static void 5299 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv, 5300 bool fastset, const char *name, 5301 const union hdmi_infoframe *a, 5302 const union hdmi_infoframe *b) 5303 { 5304 if (fastset) { 5305 if (!drm_debug_enabled(DRM_UT_KMS)) 5306 return; 5307 5308 drm_dbg_kms(&dev_priv->drm, 5309 "fastset mismatch in %s infoframe\n", name); 5310 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 5311 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a); 5312 drm_dbg_kms(&dev_priv->drm, "found:\n"); 5313 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b); 5314 } else { 5315 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name); 5316 drm_err(&dev_priv->drm, "expected:\n"); 5317 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a); 5318 drm_err(&dev_priv->drm, "found:\n"); 5319 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b); 5320 } 5321 } 5322 5323 static void 5324 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv, 5325 bool fastset, const char *name, 5326 const struct drm_dp_vsc_sdp *a, 5327 const struct drm_dp_vsc_sdp *b) 5328 { 5329 if (fastset) { 5330 if (!drm_debug_enabled(DRM_UT_KMS)) 5331 return; 5332 5333 drm_dbg_kms(&dev_priv->drm, 5334 "fastset mismatch in %s dp sdp\n", name); 5335 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 5336 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a); 5337 drm_dbg_kms(&dev_priv->drm, "found:\n"); 5338 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b); 5339 } else { 5340 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name); 5341 drm_err(&dev_priv->drm, "expected:\n"); 5342 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a); 5343 drm_err(&dev_priv->drm, "found:\n"); 5344 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b); 5345 } 5346 } 5347 5348 /* Returns the length up to and including the last differing byte */ 5349 static size_t 5350 memcmp_diff_len(const u8 *a, const u8 *b, size_t len) 5351 { 5352 int i; 5353 5354 for (i = len - 1; i >= 0; i--) { 5355 if (a[i] != b[i]) 5356 return i + 1; 5357 } 5358 5359 return 0; 5360 } 5361 5362 static void 5363 pipe_config_buffer_mismatch(struct drm_i915_private *dev_priv, 5364 bool fastset, const char *name, 5365 const u8 *a, const u8 *b, size_t len) 5366 { 5367 if (fastset) { 5368 if (!drm_debug_enabled(DRM_UT_KMS)) 5369 return; 5370 5371 /* only dump up to the last difference */ 5372 len = memcmp_diff_len(a, b, len); 5373 5374 drm_dbg_kms(&dev_priv->drm, 5375 "fastset mismatch in %s buffer\n", name); 5376 print_hex_dump(KERN_DEBUG, "expected: ", DUMP_PREFIX_NONE, 5377 16, 0, a, len, false); 5378 print_hex_dump(KERN_DEBUG, "found: ", DUMP_PREFIX_NONE, 5379 16, 0, b, len, false); 5380 } else { 5381 /* only dump up to the last difference */ 5382 len = memcmp_diff_len(a, b, len); 5383 5384 drm_err(&dev_priv->drm, "mismatch in %s buffer\n", name); 5385 print_hex_dump(KERN_ERR, "expected: ", DUMP_PREFIX_NONE, 5386 16, 0, a, len, false); 5387 print_hex_dump(KERN_ERR, "found: ", DUMP_PREFIX_NONE, 5388 16, 0, b, len, false); 5389 } 5390 } 5391 5392 static void __printf(4, 5) 5393 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc, 5394 const char *name, const char *format, ...) 5395 { 5396 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 5397 struct va_format vaf; 5398 va_list args; 5399 5400 va_start(args, format); 5401 vaf.fmt = format; 5402 vaf.va = &args; 5403 5404 if (fastset) 5405 drm_dbg_kms(&i915->drm, 5406 "[CRTC:%d:%s] fastset mismatch in %s %pV\n", 5407 crtc->base.base.id, crtc->base.name, name, &vaf); 5408 else 5409 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n", 5410 crtc->base.base.id, crtc->base.name, name, &vaf); 5411 5412 va_end(args); 5413 } 5414 5415 static bool fastboot_enabled(struct drm_i915_private *dev_priv) 5416 { 5417 if (dev_priv->params.fastboot != -1) 5418 return dev_priv->params.fastboot; 5419 5420 /* Enable fastboot by default on Skylake and newer */ 5421 if (DISPLAY_VER(dev_priv) >= 9) 5422 return true; 5423 5424 /* Enable fastboot by default on VLV and CHV */ 5425 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5426 return true; 5427 5428 /* Disabled by default on all others */ 5429 return false; 5430 } 5431 5432 bool 5433 intel_pipe_config_compare(const struct intel_crtc_state *current_config, 5434 const struct intel_crtc_state *pipe_config, 5435 bool fastset) 5436 { 5437 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev); 5438 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 5439 bool ret = true; 5440 bool fixup_inherited = fastset && 5441 current_config->inherited && !pipe_config->inherited; 5442 5443 if (fixup_inherited && !fastboot_enabled(dev_priv)) { 5444 drm_dbg_kms(&dev_priv->drm, 5445 "initial modeset and fastboot not set\n"); 5446 ret = false; 5447 } 5448 5449 #define PIPE_CONF_CHECK_X(name) do { \ 5450 if (current_config->name != pipe_config->name) { \ 5451 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5452 "(expected 0x%08x, found 0x%08x)", \ 5453 current_config->name, \ 5454 pipe_config->name); \ 5455 ret = false; \ 5456 } \ 5457 } while (0) 5458 5459 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \ 5460 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \ 5461 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5462 "(expected 0x%08x, found 0x%08x)", \ 5463 current_config->name & (mask), \ 5464 pipe_config->name & (mask)); \ 5465 ret = false; \ 5466 } \ 5467 } while (0) 5468 5469 #define PIPE_CONF_CHECK_I(name) do { \ 5470 if (current_config->name != pipe_config->name) { \ 5471 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5472 "(expected %i, found %i)", \ 5473 current_config->name, \ 5474 pipe_config->name); \ 5475 ret = false; \ 5476 } \ 5477 } while (0) 5478 5479 #define PIPE_CONF_CHECK_BOOL(name) do { \ 5480 if (current_config->name != pipe_config->name) { \ 5481 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5482 "(expected %s, found %s)", \ 5483 str_yes_no(current_config->name), \ 5484 str_yes_no(pipe_config->name)); \ 5485 ret = false; \ 5486 } \ 5487 } while (0) 5488 5489 /* 5490 * Checks state where we only read out the enabling, but not the entire 5491 * state itself (like full infoframes or ELD for audio). These states 5492 * require a full modeset on bootup to fix up. 5493 */ 5494 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \ 5495 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \ 5496 PIPE_CONF_CHECK_BOOL(name); \ 5497 } else { \ 5498 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5499 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \ 5500 str_yes_no(current_config->name), \ 5501 str_yes_no(pipe_config->name)); \ 5502 ret = false; \ 5503 } \ 5504 } while (0) 5505 5506 #define PIPE_CONF_CHECK_P(name) do { \ 5507 if (current_config->name != pipe_config->name) { \ 5508 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5509 "(expected %p, found %p)", \ 5510 current_config->name, \ 5511 pipe_config->name); \ 5512 ret = false; \ 5513 } \ 5514 } while (0) 5515 5516 #define PIPE_CONF_CHECK_M_N(name) do { \ 5517 if (!intel_compare_link_m_n(¤t_config->name, \ 5518 &pipe_config->name)) { \ 5519 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5520 "(expected tu %i data %i/%i link %i/%i, " \ 5521 "found tu %i, data %i/%i link %i/%i)", \ 5522 current_config->name.tu, \ 5523 current_config->name.data_m, \ 5524 current_config->name.data_n, \ 5525 current_config->name.link_m, \ 5526 current_config->name.link_n, \ 5527 pipe_config->name.tu, \ 5528 pipe_config->name.data_m, \ 5529 pipe_config->name.data_n, \ 5530 pipe_config->name.link_m, \ 5531 pipe_config->name.link_n); \ 5532 ret = false; \ 5533 } \ 5534 } while (0) 5535 5536 #define PIPE_CONF_CHECK_TIMINGS(name) do { \ 5537 PIPE_CONF_CHECK_I(name.crtc_hdisplay); \ 5538 PIPE_CONF_CHECK_I(name.crtc_htotal); \ 5539 PIPE_CONF_CHECK_I(name.crtc_hblank_start); \ 5540 PIPE_CONF_CHECK_I(name.crtc_hblank_end); \ 5541 PIPE_CONF_CHECK_I(name.crtc_hsync_start); \ 5542 PIPE_CONF_CHECK_I(name.crtc_hsync_end); \ 5543 PIPE_CONF_CHECK_I(name.crtc_vdisplay); \ 5544 PIPE_CONF_CHECK_I(name.crtc_vtotal); \ 5545 PIPE_CONF_CHECK_I(name.crtc_vblank_start); \ 5546 PIPE_CONF_CHECK_I(name.crtc_vblank_end); \ 5547 PIPE_CONF_CHECK_I(name.crtc_vsync_start); \ 5548 PIPE_CONF_CHECK_I(name.crtc_vsync_end); \ 5549 } while (0) 5550 5551 #define PIPE_CONF_CHECK_RECT(name) do { \ 5552 PIPE_CONF_CHECK_I(name.x1); \ 5553 PIPE_CONF_CHECK_I(name.x2); \ 5554 PIPE_CONF_CHECK_I(name.y1); \ 5555 PIPE_CONF_CHECK_I(name.y2); \ 5556 } while (0) 5557 5558 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \ 5559 if ((current_config->name ^ pipe_config->name) & (mask)) { \ 5560 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5561 "(%x) (expected %i, found %i)", \ 5562 (mask), \ 5563 current_config->name & (mask), \ 5564 pipe_config->name & (mask)); \ 5565 ret = false; \ 5566 } \ 5567 } while (0) 5568 5569 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \ 5570 if (!intel_compare_infoframe(¤t_config->infoframes.name, \ 5571 &pipe_config->infoframes.name)) { \ 5572 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \ 5573 ¤t_config->infoframes.name, \ 5574 &pipe_config->infoframes.name); \ 5575 ret = false; \ 5576 } \ 5577 } while (0) 5578 5579 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \ 5580 if (!current_config->has_psr && !pipe_config->has_psr && \ 5581 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \ 5582 &pipe_config->infoframes.name)) { \ 5583 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \ 5584 ¤t_config->infoframes.name, \ 5585 &pipe_config->infoframes.name); \ 5586 ret = false; \ 5587 } \ 5588 } while (0) 5589 5590 #define PIPE_CONF_CHECK_BUFFER(name, len) do { \ 5591 BUILD_BUG_ON(sizeof(current_config->name) != (len)); \ 5592 BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \ 5593 if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \ 5594 pipe_config_buffer_mismatch(dev_priv, fastset, __stringify(name), \ 5595 current_config->name, \ 5596 pipe_config->name, \ 5597 (len)); \ 5598 ret = false; \ 5599 } \ 5600 } while (0) 5601 5602 #define PIPE_CONF_CHECK_COLOR_LUT(lut, is_pre_csc_lut) do { \ 5603 if (current_config->gamma_mode == pipe_config->gamma_mode && \ 5604 !intel_color_lut_equal(current_config, \ 5605 current_config->lut, pipe_config->lut, \ 5606 is_pre_csc_lut)) { \ 5607 pipe_config_mismatch(fastset, crtc, __stringify(lut), \ 5608 "hw_state doesn't match sw_state"); \ 5609 ret = false; \ 5610 } \ 5611 } while (0) 5612 5613 #define PIPE_CONF_QUIRK(quirk) \ 5614 ((current_config->quirks | pipe_config->quirks) & (quirk)) 5615 5616 PIPE_CONF_CHECK_I(hw.enable); 5617 PIPE_CONF_CHECK_I(hw.active); 5618 5619 PIPE_CONF_CHECK_I(cpu_transcoder); 5620 PIPE_CONF_CHECK_I(mst_master_transcoder); 5621 5622 PIPE_CONF_CHECK_BOOL(has_pch_encoder); 5623 PIPE_CONF_CHECK_I(fdi_lanes); 5624 PIPE_CONF_CHECK_M_N(fdi_m_n); 5625 5626 PIPE_CONF_CHECK_I(lane_count); 5627 PIPE_CONF_CHECK_X(lane_lat_optim_mask); 5628 5629 if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) { 5630 if (!fastset || !pipe_config->seamless_m_n) 5631 PIPE_CONF_CHECK_M_N(dp_m_n); 5632 } else { 5633 PIPE_CONF_CHECK_M_N(dp_m_n); 5634 PIPE_CONF_CHECK_M_N(dp_m2_n2); 5635 } 5636 5637 PIPE_CONF_CHECK_X(output_types); 5638 5639 PIPE_CONF_CHECK_I(framestart_delay); 5640 PIPE_CONF_CHECK_I(msa_timing_delay); 5641 5642 PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode); 5643 PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode); 5644 5645 PIPE_CONF_CHECK_I(pixel_multiplier); 5646 5647 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5648 DRM_MODE_FLAG_INTERLACE); 5649 5650 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { 5651 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5652 DRM_MODE_FLAG_PHSYNC); 5653 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5654 DRM_MODE_FLAG_NHSYNC); 5655 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5656 DRM_MODE_FLAG_PVSYNC); 5657 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5658 DRM_MODE_FLAG_NVSYNC); 5659 } 5660 5661 PIPE_CONF_CHECK_I(output_format); 5662 PIPE_CONF_CHECK_BOOL(has_hdmi_sink); 5663 if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || 5664 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5665 PIPE_CONF_CHECK_BOOL(limited_color_range); 5666 5667 PIPE_CONF_CHECK_BOOL(hdmi_scrambling); 5668 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio); 5669 PIPE_CONF_CHECK_BOOL(has_infoframe); 5670 PIPE_CONF_CHECK_BOOL(fec_enable); 5671 5672 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio); 5673 PIPE_CONF_CHECK_BUFFER(eld, MAX_ELD_BYTES); 5674 5675 PIPE_CONF_CHECK_X(gmch_pfit.control); 5676 /* pfit ratios are autocomputed by the hw on gen4+ */ 5677 if (DISPLAY_VER(dev_priv) < 4) 5678 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); 5679 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); 5680 5681 /* 5682 * Changing the EDP transcoder input mux 5683 * (A_ONOFF vs. A_ON) requires a full modeset. 5684 */ 5685 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru); 5686 5687 if (!fastset) { 5688 PIPE_CONF_CHECK_RECT(pipe_src); 5689 5690 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled); 5691 PIPE_CONF_CHECK_RECT(pch_pfit.dst); 5692 5693 PIPE_CONF_CHECK_I(scaler_state.scaler_id); 5694 PIPE_CONF_CHECK_I(pixel_rate); 5695 5696 PIPE_CONF_CHECK_X(gamma_mode); 5697 if (IS_CHERRYVIEW(dev_priv)) 5698 PIPE_CONF_CHECK_X(cgm_mode); 5699 else 5700 PIPE_CONF_CHECK_X(csc_mode); 5701 PIPE_CONF_CHECK_BOOL(gamma_enable); 5702 PIPE_CONF_CHECK_BOOL(csc_enable); 5703 5704 PIPE_CONF_CHECK_I(linetime); 5705 PIPE_CONF_CHECK_I(ips_linetime); 5706 5707 PIPE_CONF_CHECK_COLOR_LUT(pre_csc_lut, true); 5708 PIPE_CONF_CHECK_COLOR_LUT(post_csc_lut, false); 5709 5710 if (current_config->active_planes) { 5711 PIPE_CONF_CHECK_BOOL(has_psr); 5712 PIPE_CONF_CHECK_BOOL(has_psr2); 5713 PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); 5714 PIPE_CONF_CHECK_I(dc3co_exitline); 5715 } 5716 } 5717 5718 PIPE_CONF_CHECK_BOOL(double_wide); 5719 5720 if (dev_priv->display.dpll.mgr) { 5721 PIPE_CONF_CHECK_P(shared_dpll); 5722 5723 PIPE_CONF_CHECK_X(dpll_hw_state.dpll); 5724 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); 5725 PIPE_CONF_CHECK_X(dpll_hw_state.fp0); 5726 PIPE_CONF_CHECK_X(dpll_hw_state.fp1); 5727 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); 5728 PIPE_CONF_CHECK_X(dpll_hw_state.spll); 5729 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); 5730 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); 5731 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); 5732 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); 5733 PIPE_CONF_CHECK_X(dpll_hw_state.div0); 5734 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); 5735 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); 5736 PIPE_CONF_CHECK_X(dpll_hw_state.pll0); 5737 PIPE_CONF_CHECK_X(dpll_hw_state.pll1); 5738 PIPE_CONF_CHECK_X(dpll_hw_state.pll2); 5739 PIPE_CONF_CHECK_X(dpll_hw_state.pll3); 5740 PIPE_CONF_CHECK_X(dpll_hw_state.pll6); 5741 PIPE_CONF_CHECK_X(dpll_hw_state.pll8); 5742 PIPE_CONF_CHECK_X(dpll_hw_state.pll9); 5743 PIPE_CONF_CHECK_X(dpll_hw_state.pll10); 5744 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); 5745 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl); 5746 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1); 5747 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl); 5748 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0); 5749 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1); 5750 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf); 5751 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock); 5752 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc); 5753 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias); 5754 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias); 5755 } 5756 5757 PIPE_CONF_CHECK_X(dsi_pll.ctrl); 5758 PIPE_CONF_CHECK_X(dsi_pll.div); 5759 5760 if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5) 5761 PIPE_CONF_CHECK_I(pipe_bpp); 5762 5763 if (!fastset || !pipe_config->seamless_m_n) { 5764 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock); 5765 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock); 5766 } 5767 PIPE_CONF_CHECK_I(port_clock); 5768 5769 PIPE_CONF_CHECK_I(min_voltage_level); 5770 5771 if (current_config->has_psr || pipe_config->has_psr) 5772 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable, 5773 ~intel_hdmi_infoframe_enable(DP_SDP_VSC)); 5774 else 5775 PIPE_CONF_CHECK_X(infoframes.enable); 5776 5777 PIPE_CONF_CHECK_X(infoframes.gcp); 5778 PIPE_CONF_CHECK_INFOFRAME(avi); 5779 PIPE_CONF_CHECK_INFOFRAME(spd); 5780 PIPE_CONF_CHECK_INFOFRAME(hdmi); 5781 PIPE_CONF_CHECK_INFOFRAME(drm); 5782 PIPE_CONF_CHECK_DP_VSC_SDP(vsc); 5783 5784 PIPE_CONF_CHECK_X(sync_mode_slaves_mask); 5785 PIPE_CONF_CHECK_I(master_transcoder); 5786 PIPE_CONF_CHECK_X(bigjoiner_pipes); 5787 5788 PIPE_CONF_CHECK_I(dsc.compression_enable); 5789 PIPE_CONF_CHECK_I(dsc.dsc_split); 5790 PIPE_CONF_CHECK_I(dsc.compressed_bpp); 5791 5792 PIPE_CONF_CHECK_BOOL(splitter.enable); 5793 PIPE_CONF_CHECK_I(splitter.link_count); 5794 PIPE_CONF_CHECK_I(splitter.pixel_overlap); 5795 5796 PIPE_CONF_CHECK_BOOL(vrr.enable); 5797 PIPE_CONF_CHECK_I(vrr.vmin); 5798 PIPE_CONF_CHECK_I(vrr.vmax); 5799 PIPE_CONF_CHECK_I(vrr.flipline); 5800 PIPE_CONF_CHECK_I(vrr.pipeline_full); 5801 PIPE_CONF_CHECK_I(vrr.guardband); 5802 5803 #undef PIPE_CONF_CHECK_X 5804 #undef PIPE_CONF_CHECK_I 5805 #undef PIPE_CONF_CHECK_BOOL 5806 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE 5807 #undef PIPE_CONF_CHECK_P 5808 #undef PIPE_CONF_CHECK_FLAGS 5809 #undef PIPE_CONF_CHECK_COLOR_LUT 5810 #undef PIPE_CONF_CHECK_TIMINGS 5811 #undef PIPE_CONF_CHECK_RECT 5812 #undef PIPE_CONF_QUIRK 5813 5814 return ret; 5815 } 5816 5817 static void 5818 intel_verify_planes(struct intel_atomic_state *state) 5819 { 5820 struct intel_plane *plane; 5821 const struct intel_plane_state *plane_state; 5822 int i; 5823 5824 for_each_new_intel_plane_in_state(state, plane, 5825 plane_state, i) 5826 assert_plane(plane, plane_state->planar_slave || 5827 plane_state->uapi.visible); 5828 } 5829 5830 int intel_modeset_all_pipes(struct intel_atomic_state *state, 5831 const char *reason) 5832 { 5833 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 5834 struct intel_crtc *crtc; 5835 5836 /* 5837 * Add all pipes to the state, and force 5838 * a modeset on all the active ones. 5839 */ 5840 for_each_intel_crtc(&dev_priv->drm, crtc) { 5841 struct intel_crtc_state *crtc_state; 5842 int ret; 5843 5844 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 5845 if (IS_ERR(crtc_state)) 5846 return PTR_ERR(crtc_state); 5847 5848 if (!crtc_state->hw.active || 5849 intel_crtc_needs_modeset(crtc_state)) 5850 continue; 5851 5852 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] Full modeset due to %s\n", 5853 crtc->base.base.id, crtc->base.name, reason); 5854 5855 crtc_state->uapi.mode_changed = true; 5856 crtc_state->update_pipe = false; 5857 5858 ret = drm_atomic_add_affected_connectors(&state->base, 5859 &crtc->base); 5860 if (ret) 5861 return ret; 5862 5863 ret = intel_atomic_add_affected_planes(state, crtc); 5864 if (ret) 5865 return ret; 5866 5867 crtc_state->update_planes |= crtc_state->active_planes; 5868 crtc_state->async_flip_planes = 0; 5869 crtc_state->do_async_flip = false; 5870 } 5871 5872 return 0; 5873 } 5874 5875 void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state) 5876 { 5877 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 5878 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5879 struct drm_display_mode adjusted_mode; 5880 5881 drm_mode_init(&adjusted_mode, &crtc_state->hw.adjusted_mode); 5882 5883 if (crtc_state->vrr.enable) { 5884 adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax; 5885 adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax; 5886 adjusted_mode.crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state); 5887 crtc->vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state); 5888 } 5889 5890 drm_calc_timestamping_constants(&crtc->base, &adjusted_mode); 5891 5892 crtc->mode_flags = crtc_state->mode_flags; 5893 5894 /* 5895 * The scanline counter increments at the leading edge of hsync. 5896 * 5897 * On most platforms it starts counting from vtotal-1 on the 5898 * first active line. That means the scanline counter value is 5899 * always one less than what we would expect. Ie. just after 5900 * start of vblank, which also occurs at start of hsync (on the 5901 * last active line), the scanline counter will read vblank_start-1. 5902 * 5903 * On gen2 the scanline counter starts counting from 1 instead 5904 * of vtotal-1, so we have to subtract one (or rather add vtotal-1 5905 * to keep the value positive), instead of adding one. 5906 * 5907 * On HSW+ the behaviour of the scanline counter depends on the output 5908 * type. For DP ports it behaves like most other platforms, but on HDMI 5909 * there's an extra 1 line difference. So we need to add two instead of 5910 * one to the value. 5911 * 5912 * On VLV/CHV DSI the scanline counter would appear to increment 5913 * approx. 1/3 of a scanline before start of vblank. Unfortunately 5914 * that means we can't tell whether we're in vblank or not while 5915 * we're on that particular line. We must still set scanline_offset 5916 * to 1 so that the vblank timestamps come out correct when we query 5917 * the scanline counter from within the vblank interrupt handler. 5918 * However if queried just before the start of vblank we'll get an 5919 * answer that's slightly in the future. 5920 */ 5921 if (DISPLAY_VER(dev_priv) == 2) { 5922 int vtotal; 5923 5924 vtotal = adjusted_mode.crtc_vtotal; 5925 if (adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 5926 vtotal /= 2; 5927 5928 crtc->scanline_offset = vtotal - 1; 5929 } else if (HAS_DDI(dev_priv) && 5930 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 5931 crtc->scanline_offset = 2; 5932 } else { 5933 crtc->scanline_offset = 1; 5934 } 5935 } 5936 5937 /* 5938 * This implements the workaround described in the "notes" section of the mode 5939 * set sequence documentation. When going from no pipes or single pipe to 5940 * multiple pipes, and planes are enabled after the pipe, we need to wait at 5941 * least 2 vblanks on the first pipe before enabling planes on the second pipe. 5942 */ 5943 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state) 5944 { 5945 struct intel_crtc_state *crtc_state; 5946 struct intel_crtc *crtc; 5947 struct intel_crtc_state *first_crtc_state = NULL; 5948 struct intel_crtc_state *other_crtc_state = NULL; 5949 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; 5950 int i; 5951 5952 /* look at all crtc's that are going to be enabled in during modeset */ 5953 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5954 if (!crtc_state->hw.active || 5955 !intel_crtc_needs_modeset(crtc_state)) 5956 continue; 5957 5958 if (first_crtc_state) { 5959 other_crtc_state = crtc_state; 5960 break; 5961 } else { 5962 first_crtc_state = crtc_state; 5963 first_pipe = crtc->pipe; 5964 } 5965 } 5966 5967 /* No workaround needed? */ 5968 if (!first_crtc_state) 5969 return 0; 5970 5971 /* w/a possibly needed, check how many crtc's are already enabled. */ 5972 for_each_intel_crtc(state->base.dev, crtc) { 5973 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 5974 if (IS_ERR(crtc_state)) 5975 return PTR_ERR(crtc_state); 5976 5977 crtc_state->hsw_workaround_pipe = INVALID_PIPE; 5978 5979 if (!crtc_state->hw.active || 5980 intel_crtc_needs_modeset(crtc_state)) 5981 continue; 5982 5983 /* 2 or more enabled crtcs means no need for w/a */ 5984 if (enabled_pipe != INVALID_PIPE) 5985 return 0; 5986 5987 enabled_pipe = crtc->pipe; 5988 } 5989 5990 if (enabled_pipe != INVALID_PIPE) 5991 first_crtc_state->hsw_workaround_pipe = enabled_pipe; 5992 else if (other_crtc_state) 5993 other_crtc_state->hsw_workaround_pipe = first_pipe; 5994 5995 return 0; 5996 } 5997 5998 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 5999 u8 active_pipes) 6000 { 6001 const struct intel_crtc_state *crtc_state; 6002 struct intel_crtc *crtc; 6003 int i; 6004 6005 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6006 if (crtc_state->hw.active) 6007 active_pipes |= BIT(crtc->pipe); 6008 else 6009 active_pipes &= ~BIT(crtc->pipe); 6010 } 6011 6012 return active_pipes; 6013 } 6014 6015 static int intel_modeset_checks(struct intel_atomic_state *state) 6016 { 6017 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6018 6019 state->modeset = true; 6020 6021 if (IS_HASWELL(dev_priv)) 6022 return hsw_mode_set_planes_workaround(state); 6023 6024 return 0; 6025 } 6026 6027 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state, 6028 struct intel_crtc_state *new_crtc_state) 6029 { 6030 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) 6031 return; 6032 6033 new_crtc_state->uapi.mode_changed = false; 6034 if (!intel_crtc_needs_modeset(new_crtc_state)) 6035 new_crtc_state->update_pipe = true; 6036 } 6037 6038 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state, 6039 struct intel_crtc *crtc, 6040 u8 plane_ids_mask) 6041 { 6042 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6043 struct intel_plane *plane; 6044 6045 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 6046 struct intel_plane_state *plane_state; 6047 6048 if ((plane_ids_mask & BIT(plane->id)) == 0) 6049 continue; 6050 6051 plane_state = intel_atomic_get_plane_state(state, plane); 6052 if (IS_ERR(plane_state)) 6053 return PTR_ERR(plane_state); 6054 } 6055 6056 return 0; 6057 } 6058 6059 int intel_atomic_add_affected_planes(struct intel_atomic_state *state, 6060 struct intel_crtc *crtc) 6061 { 6062 const struct intel_crtc_state *old_crtc_state = 6063 intel_atomic_get_old_crtc_state(state, crtc); 6064 const struct intel_crtc_state *new_crtc_state = 6065 intel_atomic_get_new_crtc_state(state, crtc); 6066 6067 return intel_crtc_add_planes_to_state(state, crtc, 6068 old_crtc_state->enabled_planes | 6069 new_crtc_state->enabled_planes); 6070 } 6071 6072 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv) 6073 { 6074 /* See {hsw,vlv,ivb}_plane_ratio() */ 6075 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) || 6076 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) || 6077 IS_IVYBRIDGE(dev_priv); 6078 } 6079 6080 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state, 6081 struct intel_crtc *crtc, 6082 struct intel_crtc *other) 6083 { 6084 const struct intel_plane_state *plane_state; 6085 struct intel_plane *plane; 6086 u8 plane_ids = 0; 6087 int i; 6088 6089 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 6090 if (plane->pipe == crtc->pipe) 6091 plane_ids |= BIT(plane->id); 6092 } 6093 6094 return intel_crtc_add_planes_to_state(state, other, plane_ids); 6095 } 6096 6097 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state) 6098 { 6099 struct drm_i915_private *i915 = to_i915(state->base.dev); 6100 const struct intel_crtc_state *crtc_state; 6101 struct intel_crtc *crtc; 6102 int i; 6103 6104 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6105 struct intel_crtc *other; 6106 6107 for_each_intel_crtc_in_pipe_mask(&i915->drm, other, 6108 crtc_state->bigjoiner_pipes) { 6109 int ret; 6110 6111 if (crtc == other) 6112 continue; 6113 6114 ret = intel_crtc_add_bigjoiner_planes(state, crtc, other); 6115 if (ret) 6116 return ret; 6117 } 6118 } 6119 6120 return 0; 6121 } 6122 6123 static int intel_atomic_check_planes(struct intel_atomic_state *state) 6124 { 6125 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6126 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6127 struct intel_plane_state *plane_state; 6128 struct intel_plane *plane; 6129 struct intel_crtc *crtc; 6130 int i, ret; 6131 6132 ret = icl_add_linked_planes(state); 6133 if (ret) 6134 return ret; 6135 6136 ret = intel_bigjoiner_add_affected_planes(state); 6137 if (ret) 6138 return ret; 6139 6140 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 6141 ret = intel_plane_atomic_check(state, plane); 6142 if (ret) { 6143 drm_dbg_atomic(&dev_priv->drm, 6144 "[PLANE:%d:%s] atomic driver check failed\n", 6145 plane->base.base.id, plane->base.name); 6146 return ret; 6147 } 6148 } 6149 6150 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6151 new_crtc_state, i) { 6152 u8 old_active_planes, new_active_planes; 6153 6154 ret = icl_check_nv12_planes(new_crtc_state); 6155 if (ret) 6156 return ret; 6157 6158 /* 6159 * On some platforms the number of active planes affects 6160 * the planes' minimum cdclk calculation. Add such planes 6161 * to the state before we compute the minimum cdclk. 6162 */ 6163 if (!active_planes_affects_min_cdclk(dev_priv)) 6164 continue; 6165 6166 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 6167 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 6168 6169 if (hweight8(old_active_planes) == hweight8(new_active_planes)) 6170 continue; 6171 6172 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes); 6173 if (ret) 6174 return ret; 6175 } 6176 6177 return 0; 6178 } 6179 6180 static int intel_atomic_check_crtcs(struct intel_atomic_state *state) 6181 { 6182 struct intel_crtc_state *crtc_state; 6183 struct intel_crtc *crtc; 6184 int i; 6185 6186 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6187 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 6188 int ret; 6189 6190 ret = intel_crtc_atomic_check(state, crtc); 6191 if (ret) { 6192 drm_dbg_atomic(&i915->drm, 6193 "[CRTC:%d:%s] atomic driver check failed\n", 6194 crtc->base.base.id, crtc->base.name); 6195 return ret; 6196 } 6197 } 6198 6199 return 0; 6200 } 6201 6202 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, 6203 u8 transcoders) 6204 { 6205 const struct intel_crtc_state *new_crtc_state; 6206 struct intel_crtc *crtc; 6207 int i; 6208 6209 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6210 if (new_crtc_state->hw.enable && 6211 transcoders & BIT(new_crtc_state->cpu_transcoder) && 6212 intel_crtc_needs_modeset(new_crtc_state)) 6213 return true; 6214 } 6215 6216 return false; 6217 } 6218 6219 static bool intel_pipes_need_modeset(struct intel_atomic_state *state, 6220 u8 pipes) 6221 { 6222 const struct intel_crtc_state *new_crtc_state; 6223 struct intel_crtc *crtc; 6224 int i; 6225 6226 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6227 if (new_crtc_state->hw.enable && 6228 pipes & BIT(crtc->pipe) && 6229 intel_crtc_needs_modeset(new_crtc_state)) 6230 return true; 6231 } 6232 6233 return false; 6234 } 6235 6236 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state, 6237 struct intel_crtc *master_crtc) 6238 { 6239 struct drm_i915_private *i915 = to_i915(state->base.dev); 6240 struct intel_crtc_state *master_crtc_state = 6241 intel_atomic_get_new_crtc_state(state, master_crtc); 6242 struct intel_crtc *slave_crtc; 6243 6244 if (!master_crtc_state->bigjoiner_pipes) 6245 return 0; 6246 6247 /* sanity check */ 6248 if (drm_WARN_ON(&i915->drm, 6249 master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state))) 6250 return -EINVAL; 6251 6252 if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) { 6253 drm_dbg_kms(&i915->drm, 6254 "[CRTC:%d:%s] Cannot act as big joiner master " 6255 "(need 0x%x as pipes, only 0x%x possible)\n", 6256 master_crtc->base.base.id, master_crtc->base.name, 6257 master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915)); 6258 return -EINVAL; 6259 } 6260 6261 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 6262 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 6263 struct intel_crtc_state *slave_crtc_state; 6264 int ret; 6265 6266 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc); 6267 if (IS_ERR(slave_crtc_state)) 6268 return PTR_ERR(slave_crtc_state); 6269 6270 /* master being enabled, slave was already configured? */ 6271 if (slave_crtc_state->uapi.enable) { 6272 drm_dbg_kms(&i915->drm, 6273 "[CRTC:%d:%s] Slave is enabled as normal CRTC, but " 6274 "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n", 6275 slave_crtc->base.base.id, slave_crtc->base.name, 6276 master_crtc->base.base.id, master_crtc->base.name); 6277 return -EINVAL; 6278 } 6279 6280 /* 6281 * The state copy logic assumes the master crtc gets processed 6282 * before the slave crtc during the main compute_config loop. 6283 * This works because the crtcs are created in pipe order, 6284 * and the hardware requires master pipe < slave pipe as well. 6285 * Should that change we need to rethink the logic. 6286 */ 6287 if (WARN_ON(drm_crtc_index(&master_crtc->base) > 6288 drm_crtc_index(&slave_crtc->base))) 6289 return -EINVAL; 6290 6291 drm_dbg_kms(&i915->drm, 6292 "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n", 6293 slave_crtc->base.base.id, slave_crtc->base.name, 6294 master_crtc->base.base.id, master_crtc->base.name); 6295 6296 slave_crtc_state->bigjoiner_pipes = 6297 master_crtc_state->bigjoiner_pipes; 6298 6299 ret = copy_bigjoiner_crtc_state_modeset(state, slave_crtc); 6300 if (ret) 6301 return ret; 6302 } 6303 6304 return 0; 6305 } 6306 6307 static void kill_bigjoiner_slave(struct intel_atomic_state *state, 6308 struct intel_crtc *master_crtc) 6309 { 6310 struct drm_i915_private *i915 = to_i915(state->base.dev); 6311 struct intel_crtc_state *master_crtc_state = 6312 intel_atomic_get_new_crtc_state(state, master_crtc); 6313 struct intel_crtc *slave_crtc; 6314 6315 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 6316 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 6317 struct intel_crtc_state *slave_crtc_state = 6318 intel_atomic_get_new_crtc_state(state, slave_crtc); 6319 6320 slave_crtc_state->bigjoiner_pipes = 0; 6321 6322 intel_crtc_copy_uapi_to_hw_state_modeset(state, slave_crtc); 6323 } 6324 6325 master_crtc_state->bigjoiner_pipes = 0; 6326 } 6327 6328 /** 6329 * DOC: asynchronous flip implementation 6330 * 6331 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC 6332 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL. 6333 * Correspondingly, support is currently added for primary plane only. 6334 * 6335 * Async flip can only change the plane surface address, so anything else 6336 * changing is rejected from the intel_async_flip_check_hw() function. 6337 * Once this check is cleared, flip done interrupt is enabled using 6338 * the intel_crtc_enable_flip_done() function. 6339 * 6340 * As soon as the surface address register is written, flip done interrupt is 6341 * generated and the requested events are sent to the usersapce in the interrupt 6342 * handler itself. The timestamp and sequence sent during the flip done event 6343 * correspond to the last vblank and have no relation to the actual time when 6344 * the flip done event was sent. 6345 */ 6346 static int intel_async_flip_check_uapi(struct intel_atomic_state *state, 6347 struct intel_crtc *crtc) 6348 { 6349 struct drm_i915_private *i915 = to_i915(state->base.dev); 6350 const struct intel_crtc_state *new_crtc_state = 6351 intel_atomic_get_new_crtc_state(state, crtc); 6352 const struct intel_plane_state *old_plane_state; 6353 struct intel_plane_state *new_plane_state; 6354 struct intel_plane *plane; 6355 int i; 6356 6357 if (!new_crtc_state->uapi.async_flip) 6358 return 0; 6359 6360 if (!new_crtc_state->uapi.active) { 6361 drm_dbg_kms(&i915->drm, 6362 "[CRTC:%d:%s] not active\n", 6363 crtc->base.base.id, crtc->base.name); 6364 return -EINVAL; 6365 } 6366 6367 if (intel_crtc_needs_modeset(new_crtc_state)) { 6368 drm_dbg_kms(&i915->drm, 6369 "[CRTC:%d:%s] modeset required\n", 6370 crtc->base.base.id, crtc->base.name); 6371 return -EINVAL; 6372 } 6373 6374 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 6375 new_plane_state, i) { 6376 if (plane->pipe != crtc->pipe) 6377 continue; 6378 6379 /* 6380 * TODO: Async flip is only supported through the page flip IOCTL 6381 * as of now. So support currently added for primary plane only. 6382 * Support for other planes on platforms on which supports 6383 * this(vlv/chv and icl+) should be added when async flip is 6384 * enabled in the atomic IOCTL path. 6385 */ 6386 if (!plane->async_flip) { 6387 drm_dbg_kms(&i915->drm, 6388 "[PLANE:%d:%s] async flip not supported\n", 6389 plane->base.base.id, plane->base.name); 6390 return -EINVAL; 6391 } 6392 6393 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) { 6394 drm_dbg_kms(&i915->drm, 6395 "[PLANE:%d:%s] no old or new framebuffer\n", 6396 plane->base.base.id, plane->base.name); 6397 return -EINVAL; 6398 } 6399 } 6400 6401 return 0; 6402 } 6403 6404 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc) 6405 { 6406 struct drm_i915_private *i915 = to_i915(state->base.dev); 6407 const struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6408 const struct intel_plane_state *new_plane_state, *old_plane_state; 6409 struct intel_plane *plane; 6410 int i; 6411 6412 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 6413 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6414 6415 if (!new_crtc_state->uapi.async_flip) 6416 return 0; 6417 6418 if (!new_crtc_state->hw.active) { 6419 drm_dbg_kms(&i915->drm, 6420 "[CRTC:%d:%s] not active\n", 6421 crtc->base.base.id, crtc->base.name); 6422 return -EINVAL; 6423 } 6424 6425 if (intel_crtc_needs_modeset(new_crtc_state)) { 6426 drm_dbg_kms(&i915->drm, 6427 "[CRTC:%d:%s] modeset required\n", 6428 crtc->base.base.id, crtc->base.name); 6429 return -EINVAL; 6430 } 6431 6432 if (old_crtc_state->active_planes != new_crtc_state->active_planes) { 6433 drm_dbg_kms(&i915->drm, 6434 "[CRTC:%d:%s] Active planes cannot be in async flip\n", 6435 crtc->base.base.id, crtc->base.name); 6436 return -EINVAL; 6437 } 6438 6439 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 6440 new_plane_state, i) { 6441 if (plane->pipe != crtc->pipe) 6442 continue; 6443 6444 /* 6445 * Only async flip capable planes should be in the state 6446 * if we're really about to ask the hardware to perform 6447 * an async flip. We should never get this far otherwise. 6448 */ 6449 if (drm_WARN_ON(&i915->drm, 6450 new_crtc_state->do_async_flip && !plane->async_flip)) 6451 return -EINVAL; 6452 6453 /* 6454 * Only check async flip capable planes other planes 6455 * may be involved in the initial commit due to 6456 * the wm0/ddb optimization. 6457 * 6458 * TODO maybe should track which planes actually 6459 * were requested to do the async flip... 6460 */ 6461 if (!plane->async_flip) 6462 continue; 6463 6464 /* 6465 * FIXME: This check is kept generic for all platforms. 6466 * Need to verify this for all gen9 platforms to enable 6467 * this selectively if required. 6468 */ 6469 switch (new_plane_state->hw.fb->modifier) { 6470 case I915_FORMAT_MOD_X_TILED: 6471 case I915_FORMAT_MOD_Y_TILED: 6472 case I915_FORMAT_MOD_Yf_TILED: 6473 case I915_FORMAT_MOD_4_TILED: 6474 break; 6475 default: 6476 drm_dbg_kms(&i915->drm, 6477 "[PLANE:%d:%s] Modifier does not support async flips\n", 6478 plane->base.base.id, plane->base.name); 6479 return -EINVAL; 6480 } 6481 6482 if (new_plane_state->hw.fb->format->num_planes > 1) { 6483 drm_dbg_kms(&i915->drm, 6484 "[PLANE:%d:%s] Planar formats do not support async flips\n", 6485 plane->base.base.id, plane->base.name); 6486 return -EINVAL; 6487 } 6488 6489 if (old_plane_state->view.color_plane[0].mapping_stride != 6490 new_plane_state->view.color_plane[0].mapping_stride) { 6491 drm_dbg_kms(&i915->drm, 6492 "[PLANE:%d:%s] Stride cannot be changed in async flip\n", 6493 plane->base.base.id, plane->base.name); 6494 return -EINVAL; 6495 } 6496 6497 if (old_plane_state->hw.fb->modifier != 6498 new_plane_state->hw.fb->modifier) { 6499 drm_dbg_kms(&i915->drm, 6500 "[PLANE:%d:%s] Modifier cannot be changed in async flip\n", 6501 plane->base.base.id, plane->base.name); 6502 return -EINVAL; 6503 } 6504 6505 if (old_plane_state->hw.fb->format != 6506 new_plane_state->hw.fb->format) { 6507 drm_dbg_kms(&i915->drm, 6508 "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n", 6509 plane->base.base.id, plane->base.name); 6510 return -EINVAL; 6511 } 6512 6513 if (old_plane_state->hw.rotation != 6514 new_plane_state->hw.rotation) { 6515 drm_dbg_kms(&i915->drm, 6516 "[PLANE:%d:%s] Rotation cannot be changed in async flip\n", 6517 plane->base.base.id, plane->base.name); 6518 return -EINVAL; 6519 } 6520 6521 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) || 6522 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) { 6523 drm_dbg_kms(&i915->drm, 6524 "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n", 6525 plane->base.base.id, plane->base.name); 6526 return -EINVAL; 6527 } 6528 6529 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) { 6530 drm_dbg_kms(&i915->drm, 6531 "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n", 6532 plane->base.base.id, plane->base.name); 6533 return -EINVAL; 6534 } 6535 6536 if (old_plane_state->hw.pixel_blend_mode != 6537 new_plane_state->hw.pixel_blend_mode) { 6538 drm_dbg_kms(&i915->drm, 6539 "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n", 6540 plane->base.base.id, plane->base.name); 6541 return -EINVAL; 6542 } 6543 6544 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) { 6545 drm_dbg_kms(&i915->drm, 6546 "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n", 6547 plane->base.base.id, plane->base.name); 6548 return -EINVAL; 6549 } 6550 6551 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) { 6552 drm_dbg_kms(&i915->drm, 6553 "[PLANE:%d:%s] Color range cannot be changed in async flip\n", 6554 plane->base.base.id, plane->base.name); 6555 return -EINVAL; 6556 } 6557 6558 /* plane decryption is allow to change only in synchronous flips */ 6559 if (old_plane_state->decrypt != new_plane_state->decrypt) { 6560 drm_dbg_kms(&i915->drm, 6561 "[PLANE:%d:%s] Decryption cannot be changed in async flip\n", 6562 plane->base.base.id, plane->base.name); 6563 return -EINVAL; 6564 } 6565 } 6566 6567 return 0; 6568 } 6569 6570 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state) 6571 { 6572 struct drm_i915_private *i915 = to_i915(state->base.dev); 6573 struct intel_crtc_state *crtc_state; 6574 struct intel_crtc *crtc; 6575 u8 affected_pipes = 0; 6576 u8 modeset_pipes = 0; 6577 int i; 6578 6579 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6580 affected_pipes |= crtc_state->bigjoiner_pipes; 6581 if (intel_crtc_needs_modeset(crtc_state)) 6582 modeset_pipes |= crtc_state->bigjoiner_pipes; 6583 } 6584 6585 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) { 6586 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6587 if (IS_ERR(crtc_state)) 6588 return PTR_ERR(crtc_state); 6589 } 6590 6591 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) { 6592 int ret; 6593 6594 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6595 6596 crtc_state->uapi.mode_changed = true; 6597 6598 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); 6599 if (ret) 6600 return ret; 6601 6602 ret = intel_atomic_add_affected_planes(state, crtc); 6603 if (ret) 6604 return ret; 6605 } 6606 6607 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6608 /* Kill old bigjoiner link, we may re-establish afterwards */ 6609 if (intel_crtc_needs_modeset(crtc_state) && 6610 intel_crtc_is_bigjoiner_master(crtc_state)) 6611 kill_bigjoiner_slave(state, crtc); 6612 } 6613 6614 return 0; 6615 } 6616 6617 /** 6618 * intel_atomic_check - validate state object 6619 * @dev: drm device 6620 * @_state: state to validate 6621 */ 6622 int intel_atomic_check(struct drm_device *dev, 6623 struct drm_atomic_state *_state) 6624 { 6625 struct drm_i915_private *dev_priv = to_i915(dev); 6626 struct intel_atomic_state *state = to_intel_atomic_state(_state); 6627 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6628 struct intel_crtc *crtc; 6629 int ret, i; 6630 bool any_ms = false; 6631 6632 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6633 new_crtc_state, i) { 6634 if (new_crtc_state->inherited != old_crtc_state->inherited) 6635 new_crtc_state->uapi.mode_changed = true; 6636 6637 if (new_crtc_state->uapi.scaling_filter != 6638 old_crtc_state->uapi.scaling_filter) 6639 new_crtc_state->uapi.mode_changed = true; 6640 } 6641 6642 intel_vrr_check_modeset(state); 6643 6644 ret = drm_atomic_helper_check_modeset(dev, &state->base); 6645 if (ret) 6646 goto fail; 6647 6648 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6649 ret = intel_async_flip_check_uapi(state, crtc); 6650 if (ret) 6651 return ret; 6652 } 6653 6654 ret = intel_bigjoiner_add_affected_crtcs(state); 6655 if (ret) 6656 goto fail; 6657 6658 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6659 new_crtc_state, i) { 6660 if (!intel_crtc_needs_modeset(new_crtc_state)) { 6661 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 6662 copy_bigjoiner_crtc_state_nomodeset(state, crtc); 6663 else 6664 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 6665 continue; 6666 } 6667 6668 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) { 6669 drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable); 6670 continue; 6671 } 6672 6673 ret = intel_crtc_prepare_cleared_state(state, crtc); 6674 if (ret) 6675 goto fail; 6676 6677 if (!new_crtc_state->hw.enable) 6678 continue; 6679 6680 ret = intel_modeset_pipe_config(state, crtc); 6681 if (ret) 6682 goto fail; 6683 6684 ret = intel_atomic_check_bigjoiner(state, crtc); 6685 if (ret) 6686 goto fail; 6687 } 6688 6689 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6690 new_crtc_state, i) { 6691 if (!intel_crtc_needs_modeset(new_crtc_state)) 6692 continue; 6693 6694 if (new_crtc_state->hw.enable) { 6695 ret = intel_modeset_pipe_config_late(state, crtc); 6696 if (ret) 6697 goto fail; 6698 } 6699 6700 intel_crtc_check_fastset(old_crtc_state, new_crtc_state); 6701 } 6702 6703 /** 6704 * Check if fastset is allowed by external dependencies like other 6705 * pipes and transcoders. 6706 * 6707 * Right now it only forces a fullmodeset when the MST master 6708 * transcoder did not changed but the pipe of the master transcoder 6709 * needs a fullmodeset so all slaves also needs to do a fullmodeset or 6710 * in case of port synced crtcs, if one of the synced crtcs 6711 * needs a full modeset, all other synced crtcs should be 6712 * forced a full modeset. 6713 */ 6714 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6715 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state)) 6716 continue; 6717 6718 if (intel_dp_mst_is_slave_trans(new_crtc_state)) { 6719 enum transcoder master = new_crtc_state->mst_master_transcoder; 6720 6721 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) { 6722 new_crtc_state->uapi.mode_changed = true; 6723 new_crtc_state->update_pipe = false; 6724 } 6725 } 6726 6727 if (is_trans_port_sync_mode(new_crtc_state)) { 6728 u8 trans = new_crtc_state->sync_mode_slaves_mask; 6729 6730 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER) 6731 trans |= BIT(new_crtc_state->master_transcoder); 6732 6733 if (intel_cpu_transcoders_need_modeset(state, trans)) { 6734 new_crtc_state->uapi.mode_changed = true; 6735 new_crtc_state->update_pipe = false; 6736 } 6737 } 6738 6739 if (new_crtc_state->bigjoiner_pipes) { 6740 if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) { 6741 new_crtc_state->uapi.mode_changed = true; 6742 new_crtc_state->update_pipe = false; 6743 } 6744 } 6745 } 6746 6747 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6748 new_crtc_state, i) { 6749 if (!intel_crtc_needs_modeset(new_crtc_state)) 6750 continue; 6751 6752 any_ms = true; 6753 6754 intel_release_shared_dplls(state, crtc); 6755 } 6756 6757 if (any_ms && !check_digital_port_conflicts(state)) { 6758 drm_dbg_kms(&dev_priv->drm, 6759 "rejecting conflicting digital port configuration\n"); 6760 ret = -EINVAL; 6761 goto fail; 6762 } 6763 6764 ret = drm_dp_mst_atomic_check(&state->base); 6765 if (ret) 6766 goto fail; 6767 6768 ret = intel_atomic_check_planes(state); 6769 if (ret) 6770 goto fail; 6771 6772 ret = intel_compute_global_watermarks(state); 6773 if (ret) 6774 goto fail; 6775 6776 ret = intel_bw_atomic_check(state); 6777 if (ret) 6778 goto fail; 6779 6780 ret = intel_cdclk_atomic_check(state, &any_ms); 6781 if (ret) 6782 goto fail; 6783 6784 if (intel_any_crtc_needs_modeset(state)) 6785 any_ms = true; 6786 6787 if (any_ms) { 6788 ret = intel_modeset_checks(state); 6789 if (ret) 6790 goto fail; 6791 6792 ret = intel_modeset_calc_cdclk(state); 6793 if (ret) 6794 return ret; 6795 } 6796 6797 ret = intel_atomic_check_crtcs(state); 6798 if (ret) 6799 goto fail; 6800 6801 ret = intel_fbc_atomic_check(state); 6802 if (ret) 6803 goto fail; 6804 6805 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6806 new_crtc_state, i) { 6807 intel_color_assert_luts(new_crtc_state); 6808 6809 ret = intel_async_flip_check_hw(state, crtc); 6810 if (ret) 6811 goto fail; 6812 6813 /* Either full modeset or fastset (or neither), never both */ 6814 drm_WARN_ON(&dev_priv->drm, 6815 intel_crtc_needs_modeset(new_crtc_state) && 6816 intel_crtc_needs_fastset(new_crtc_state)); 6817 6818 if (!intel_crtc_needs_modeset(new_crtc_state) && 6819 !intel_crtc_needs_fastset(new_crtc_state)) 6820 continue; 6821 6822 intel_crtc_state_dump(new_crtc_state, state, 6823 intel_crtc_needs_modeset(new_crtc_state) ? 6824 "modeset" : "fastset"); 6825 } 6826 6827 return 0; 6828 6829 fail: 6830 if (ret == -EDEADLK) 6831 return ret; 6832 6833 /* 6834 * FIXME would probably be nice to know which crtc specifically 6835 * caused the failure, in cases where we can pinpoint it. 6836 */ 6837 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6838 new_crtc_state, i) 6839 intel_crtc_state_dump(new_crtc_state, state, "failed"); 6840 6841 return ret; 6842 } 6843 6844 static int intel_atomic_prepare_commit(struct intel_atomic_state *state) 6845 { 6846 struct intel_crtc_state *crtc_state; 6847 struct intel_crtc *crtc; 6848 int i, ret; 6849 6850 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base); 6851 if (ret < 0) 6852 return ret; 6853 6854 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6855 if (intel_crtc_needs_color_update(crtc_state)) 6856 intel_color_prepare_commit(crtc_state); 6857 } 6858 6859 return 0; 6860 } 6861 6862 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 6863 struct intel_crtc_state *crtc_state) 6864 { 6865 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6866 6867 if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes) 6868 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 6869 6870 if (crtc_state->has_pch_encoder) { 6871 enum pipe pch_transcoder = 6872 intel_crtc_pch_transcoder(crtc); 6873 6874 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true); 6875 } 6876 } 6877 6878 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, 6879 const struct intel_crtc_state *new_crtc_state) 6880 { 6881 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 6882 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6883 6884 /* 6885 * Update pipe size and adjust fitter if needed: the reason for this is 6886 * that in compute_mode_changes we check the native mode (not the pfit 6887 * mode) to see if we can flip rather than do a full mode set. In the 6888 * fastboot case, we'll flip, but if we don't update the pipesrc and 6889 * pfit state, we'll end up with a big fb scanned out into the wrong 6890 * sized surface. 6891 */ 6892 intel_set_pipe_src_size(new_crtc_state); 6893 6894 /* on skylake this is done by detaching scalers */ 6895 if (DISPLAY_VER(dev_priv) >= 9) { 6896 if (new_crtc_state->pch_pfit.enabled) 6897 skl_pfit_enable(new_crtc_state); 6898 } else if (HAS_PCH_SPLIT(dev_priv)) { 6899 if (new_crtc_state->pch_pfit.enabled) 6900 ilk_pfit_enable(new_crtc_state); 6901 else if (old_crtc_state->pch_pfit.enabled) 6902 ilk_pfit_disable(old_crtc_state); 6903 } 6904 6905 /* 6906 * The register is supposedly single buffered so perhaps 6907 * not 100% correct to do this here. But SKL+ calculate 6908 * this based on the adjust pixel rate so pfit changes do 6909 * affect it and so it must be updated for fastsets. 6910 * HSW/BDW only really need this here for fastboot, after 6911 * that the value should not change without a full modeset. 6912 */ 6913 if (DISPLAY_VER(dev_priv) >= 9 || 6914 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 6915 hsw_set_linetime_wm(new_crtc_state); 6916 6917 if (new_crtc_state->seamless_m_n) 6918 intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder, 6919 &new_crtc_state->dp_m_n); 6920 } 6921 6922 static void commit_pipe_pre_planes(struct intel_atomic_state *state, 6923 struct intel_crtc *crtc) 6924 { 6925 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6926 const struct intel_crtc_state *old_crtc_state = 6927 intel_atomic_get_old_crtc_state(state, crtc); 6928 const struct intel_crtc_state *new_crtc_state = 6929 intel_atomic_get_new_crtc_state(state, crtc); 6930 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 6931 6932 /* 6933 * During modesets pipe configuration was programmed as the 6934 * CRTC was enabled. 6935 */ 6936 if (!modeset) { 6937 if (intel_crtc_needs_color_update(new_crtc_state)) 6938 intel_color_commit_arm(new_crtc_state); 6939 6940 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 6941 bdw_set_pipemisc(new_crtc_state); 6942 6943 if (intel_crtc_needs_fastset(new_crtc_state)) 6944 intel_pipe_fastset(old_crtc_state, new_crtc_state); 6945 } 6946 6947 intel_psr2_program_trans_man_trk_ctl(new_crtc_state); 6948 6949 intel_atomic_update_watermarks(state, crtc); 6950 } 6951 6952 static void commit_pipe_post_planes(struct intel_atomic_state *state, 6953 struct intel_crtc *crtc) 6954 { 6955 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6956 const struct intel_crtc_state *new_crtc_state = 6957 intel_atomic_get_new_crtc_state(state, crtc); 6958 6959 /* 6960 * Disable the scaler(s) after the plane(s) so that we don't 6961 * get a catastrophic underrun even if the two operations 6962 * end up happening in two different frames. 6963 */ 6964 if (DISPLAY_VER(dev_priv) >= 9 && 6965 !intel_crtc_needs_modeset(new_crtc_state)) 6966 skl_detach_scalers(new_crtc_state); 6967 } 6968 6969 static void intel_enable_crtc(struct intel_atomic_state *state, 6970 struct intel_crtc *crtc) 6971 { 6972 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6973 const struct intel_crtc_state *new_crtc_state = 6974 intel_atomic_get_new_crtc_state(state, crtc); 6975 6976 if (!intel_crtc_needs_modeset(new_crtc_state)) 6977 return; 6978 6979 intel_crtc_update_active_timings(new_crtc_state); 6980 6981 dev_priv->display.funcs.display->crtc_enable(state, crtc); 6982 6983 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 6984 return; 6985 6986 /* vblanks work again, re-enable pipe CRC. */ 6987 intel_crtc_enable_pipe_crc(crtc); 6988 } 6989 6990 static void intel_update_crtc(struct intel_atomic_state *state, 6991 struct intel_crtc *crtc) 6992 { 6993 struct drm_i915_private *i915 = to_i915(state->base.dev); 6994 const struct intel_crtc_state *old_crtc_state = 6995 intel_atomic_get_old_crtc_state(state, crtc); 6996 struct intel_crtc_state *new_crtc_state = 6997 intel_atomic_get_new_crtc_state(state, crtc); 6998 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 6999 7000 if (!modeset) { 7001 if (new_crtc_state->preload_luts && 7002 intel_crtc_needs_color_update(new_crtc_state)) 7003 intel_color_load_luts(new_crtc_state); 7004 7005 intel_pre_plane_update(state, crtc); 7006 7007 if (intel_crtc_needs_fastset(new_crtc_state)) 7008 intel_encoders_update_pipe(state, crtc); 7009 7010 if (DISPLAY_VER(i915) >= 11 && 7011 intel_crtc_needs_fastset(new_crtc_state)) 7012 icl_set_pipe_chicken(new_crtc_state); 7013 } 7014 7015 intel_fbc_update(state, crtc); 7016 7017 if (!modeset && 7018 intel_crtc_needs_color_update(new_crtc_state)) 7019 intel_color_commit_noarm(new_crtc_state); 7020 7021 intel_crtc_planes_update_noarm(state, crtc); 7022 7023 /* Perform vblank evasion around commit operation */ 7024 intel_pipe_update_start(new_crtc_state); 7025 7026 commit_pipe_pre_planes(state, crtc); 7027 7028 intel_crtc_planes_update_arm(state, crtc); 7029 7030 commit_pipe_post_planes(state, crtc); 7031 7032 intel_pipe_update_end(new_crtc_state); 7033 7034 /* 7035 * We usually enable FIFO underrun interrupts as part of the 7036 * CRTC enable sequence during modesets. But when we inherit a 7037 * valid pipe configuration from the BIOS we need to take care 7038 * of enabling them on the CRTC's first fastset. 7039 */ 7040 if (intel_crtc_needs_fastset(new_crtc_state) && !modeset && 7041 old_crtc_state->inherited) 7042 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state); 7043 } 7044 7045 static void intel_old_crtc_state_disables(struct intel_atomic_state *state, 7046 struct intel_crtc_state *old_crtc_state, 7047 struct intel_crtc_state *new_crtc_state, 7048 struct intel_crtc *crtc) 7049 { 7050 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7051 7052 /* 7053 * We need to disable pipe CRC before disabling the pipe, 7054 * or we race against vblank off. 7055 */ 7056 intel_crtc_disable_pipe_crc(crtc); 7057 7058 dev_priv->display.funcs.display->crtc_disable(state, crtc); 7059 crtc->active = false; 7060 intel_fbc_disable(crtc); 7061 intel_disable_shared_dpll(old_crtc_state); 7062 7063 if (!new_crtc_state->hw.active) 7064 intel_initial_watermarks(state, crtc); 7065 } 7066 7067 static void intel_commit_modeset_disables(struct intel_atomic_state *state) 7068 { 7069 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 7070 struct intel_crtc *crtc; 7071 u32 handled = 0; 7072 int i; 7073 7074 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7075 new_crtc_state, i) { 7076 if (!intel_crtc_needs_modeset(new_crtc_state)) 7077 continue; 7078 7079 if (!old_crtc_state->hw.active) 7080 continue; 7081 7082 intel_pre_plane_update(state, crtc); 7083 intel_crtc_disable_planes(state, crtc); 7084 } 7085 7086 /* Only disable port sync and MST slaves */ 7087 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7088 new_crtc_state, i) { 7089 if (!intel_crtc_needs_modeset(new_crtc_state)) 7090 continue; 7091 7092 if (!old_crtc_state->hw.active) 7093 continue; 7094 7095 /* In case of Transcoder port Sync master slave CRTCs can be 7096 * assigned in any order and we need to make sure that 7097 * slave CRTCs are disabled first and then master CRTC since 7098 * Slave vblanks are masked till Master Vblanks. 7099 */ 7100 if (!is_trans_port_sync_slave(old_crtc_state) && 7101 !intel_dp_mst_is_slave_trans(old_crtc_state) && 7102 !intel_crtc_is_bigjoiner_slave(old_crtc_state)) 7103 continue; 7104 7105 intel_old_crtc_state_disables(state, old_crtc_state, 7106 new_crtc_state, crtc); 7107 handled |= BIT(crtc->pipe); 7108 } 7109 7110 /* Disable everything else left on */ 7111 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7112 new_crtc_state, i) { 7113 if (!intel_crtc_needs_modeset(new_crtc_state) || 7114 (handled & BIT(crtc->pipe))) 7115 continue; 7116 7117 if (!old_crtc_state->hw.active) 7118 continue; 7119 7120 intel_old_crtc_state_disables(state, old_crtc_state, 7121 new_crtc_state, crtc); 7122 } 7123 } 7124 7125 static void intel_commit_modeset_enables(struct intel_atomic_state *state) 7126 { 7127 struct intel_crtc_state *new_crtc_state; 7128 struct intel_crtc *crtc; 7129 int i; 7130 7131 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7132 if (!new_crtc_state->hw.active) 7133 continue; 7134 7135 intel_enable_crtc(state, crtc); 7136 intel_update_crtc(state, crtc); 7137 } 7138 } 7139 7140 static void skl_commit_modeset_enables(struct intel_atomic_state *state) 7141 { 7142 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7143 struct intel_crtc *crtc; 7144 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7145 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; 7146 u8 update_pipes = 0, modeset_pipes = 0; 7147 int i; 7148 7149 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7150 enum pipe pipe = crtc->pipe; 7151 7152 if (!new_crtc_state->hw.active) 7153 continue; 7154 7155 /* ignore allocations for crtc's that have been turned off. */ 7156 if (!intel_crtc_needs_modeset(new_crtc_state)) { 7157 entries[pipe] = old_crtc_state->wm.skl.ddb; 7158 update_pipes |= BIT(pipe); 7159 } else { 7160 modeset_pipes |= BIT(pipe); 7161 } 7162 } 7163 7164 /* 7165 * Whenever the number of active pipes changes, we need to make sure we 7166 * update the pipes in the right order so that their ddb allocations 7167 * never overlap with each other between CRTC updates. Otherwise we'll 7168 * cause pipe underruns and other bad stuff. 7169 * 7170 * So first lets enable all pipes that do not need a fullmodeset as 7171 * those don't have any external dependency. 7172 */ 7173 while (update_pipes) { 7174 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7175 new_crtc_state, i) { 7176 enum pipe pipe = crtc->pipe; 7177 7178 if ((update_pipes & BIT(pipe)) == 0) 7179 continue; 7180 7181 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 7182 entries, I915_MAX_PIPES, pipe)) 7183 continue; 7184 7185 entries[pipe] = new_crtc_state->wm.skl.ddb; 7186 update_pipes &= ~BIT(pipe); 7187 7188 intel_update_crtc(state, crtc); 7189 7190 /* 7191 * If this is an already active pipe, it's DDB changed, 7192 * and this isn't the last pipe that needs updating 7193 * then we need to wait for a vblank to pass for the 7194 * new ddb allocation to take effect. 7195 */ 7196 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, 7197 &old_crtc_state->wm.skl.ddb) && 7198 (update_pipes | modeset_pipes)) 7199 intel_crtc_wait_for_next_vblank(crtc); 7200 } 7201 } 7202 7203 update_pipes = modeset_pipes; 7204 7205 /* 7206 * Enable all pipes that needs a modeset and do not depends on other 7207 * pipes 7208 */ 7209 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7210 enum pipe pipe = crtc->pipe; 7211 7212 if ((modeset_pipes & BIT(pipe)) == 0) 7213 continue; 7214 7215 if (intel_dp_mst_is_slave_trans(new_crtc_state) || 7216 is_trans_port_sync_master(new_crtc_state) || 7217 intel_crtc_is_bigjoiner_master(new_crtc_state)) 7218 continue; 7219 7220 modeset_pipes &= ~BIT(pipe); 7221 7222 intel_enable_crtc(state, crtc); 7223 } 7224 7225 /* 7226 * Then we enable all remaining pipes that depend on other 7227 * pipes: MST slaves and port sync masters, big joiner master 7228 */ 7229 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7230 enum pipe pipe = crtc->pipe; 7231 7232 if ((modeset_pipes & BIT(pipe)) == 0) 7233 continue; 7234 7235 modeset_pipes &= ~BIT(pipe); 7236 7237 intel_enable_crtc(state, crtc); 7238 } 7239 7240 /* 7241 * Finally we do the plane updates/etc. for all pipes that got enabled. 7242 */ 7243 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7244 enum pipe pipe = crtc->pipe; 7245 7246 if ((update_pipes & BIT(pipe)) == 0) 7247 continue; 7248 7249 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 7250 entries, I915_MAX_PIPES, pipe)); 7251 7252 entries[pipe] = new_crtc_state->wm.skl.ddb; 7253 update_pipes &= ~BIT(pipe); 7254 7255 intel_update_crtc(state, crtc); 7256 } 7257 7258 drm_WARN_ON(&dev_priv->drm, modeset_pipes); 7259 drm_WARN_ON(&dev_priv->drm, update_pipes); 7260 } 7261 7262 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) 7263 { 7264 struct intel_atomic_state *state, *next; 7265 struct llist_node *freed; 7266 7267 freed = llist_del_all(&dev_priv->display.atomic_helper.free_list); 7268 llist_for_each_entry_safe(state, next, freed, freed) 7269 drm_atomic_state_put(&state->base); 7270 } 7271 7272 static void intel_atomic_helper_free_state_worker(struct work_struct *work) 7273 { 7274 struct drm_i915_private *dev_priv = 7275 container_of(work, typeof(*dev_priv), display.atomic_helper.free_work); 7276 7277 intel_atomic_helper_free_state(dev_priv); 7278 } 7279 7280 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) 7281 { 7282 struct wait_queue_entry wait_fence, wait_reset; 7283 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); 7284 7285 init_wait_entry(&wait_fence, 0); 7286 init_wait_entry(&wait_reset, 0); 7287 for (;;) { 7288 prepare_to_wait(&intel_state->commit_ready.wait, 7289 &wait_fence, TASK_UNINTERRUPTIBLE); 7290 prepare_to_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 7291 I915_RESET_MODESET), 7292 &wait_reset, TASK_UNINTERRUPTIBLE); 7293 7294 7295 if (i915_sw_fence_done(&intel_state->commit_ready) || 7296 test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags)) 7297 break; 7298 7299 schedule(); 7300 } 7301 finish_wait(&intel_state->commit_ready.wait, &wait_fence); 7302 finish_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 7303 I915_RESET_MODESET), 7304 &wait_reset); 7305 } 7306 7307 static void intel_atomic_cleanup_work(struct work_struct *work) 7308 { 7309 struct intel_atomic_state *state = 7310 container_of(work, struct intel_atomic_state, base.commit_work); 7311 struct drm_i915_private *i915 = to_i915(state->base.dev); 7312 struct intel_crtc_state *old_crtc_state; 7313 struct intel_crtc *crtc; 7314 int i; 7315 7316 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) 7317 intel_color_cleanup_commit(old_crtc_state); 7318 7319 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base); 7320 drm_atomic_helper_commit_cleanup_done(&state->base); 7321 drm_atomic_state_put(&state->base); 7322 7323 intel_atomic_helper_free_state(i915); 7324 } 7325 7326 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state) 7327 { 7328 struct drm_i915_private *i915 = to_i915(state->base.dev); 7329 struct intel_plane *plane; 7330 struct intel_plane_state *plane_state; 7331 int i; 7332 7333 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 7334 struct drm_framebuffer *fb = plane_state->hw.fb; 7335 int cc_plane; 7336 int ret; 7337 7338 if (!fb) 7339 continue; 7340 7341 cc_plane = intel_fb_rc_ccs_cc_plane(fb); 7342 if (cc_plane < 0) 7343 continue; 7344 7345 /* 7346 * The layout of the fast clear color value expected by HW 7347 * (the DRM ABI requiring this value to be located in fb at 7348 * offset 0 of cc plane, plane #2 previous generations or 7349 * plane #1 for flat ccs): 7350 * - 4 x 4 bytes per-channel value 7351 * (in surface type specific float/int format provided by the fb user) 7352 * - 8 bytes native color value used by the display 7353 * (converted/written by GPU during a fast clear operation using the 7354 * above per-channel values) 7355 * 7356 * The commit's FB prepare hook already ensured that FB obj is pinned and the 7357 * caller made sure that the object is synced wrt. the related color clear value 7358 * GPU write on it. 7359 */ 7360 ret = i915_gem_object_read_from_page(intel_fb_obj(fb), 7361 fb->offsets[cc_plane] + 16, 7362 &plane_state->ccval, 7363 sizeof(plane_state->ccval)); 7364 /* The above could only fail if the FB obj has an unexpected backing store type. */ 7365 drm_WARN_ON(&i915->drm, ret); 7366 } 7367 } 7368 7369 static void intel_atomic_commit_tail(struct intel_atomic_state *state) 7370 { 7371 struct drm_device *dev = state->base.dev; 7372 struct drm_i915_private *dev_priv = to_i915(dev); 7373 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 7374 struct intel_crtc *crtc; 7375 struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {}; 7376 intel_wakeref_t wakeref = 0; 7377 int i; 7378 7379 intel_atomic_commit_fence_wait(state); 7380 7381 drm_atomic_helper_wait_for_dependencies(&state->base); 7382 drm_dp_mst_atomic_wait_for_dependencies(&state->base); 7383 7384 if (state->modeset) 7385 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); 7386 7387 intel_atomic_prepare_plane_clear_colors(state); 7388 7389 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7390 new_crtc_state, i) { 7391 if (intel_crtc_needs_modeset(new_crtc_state) || 7392 intel_crtc_needs_fastset(new_crtc_state)) 7393 intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]); 7394 } 7395 7396 intel_commit_modeset_disables(state); 7397 7398 /* FIXME: Eventually get rid of our crtc->config pointer */ 7399 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7400 crtc->config = new_crtc_state; 7401 7402 if (state->modeset) { 7403 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base); 7404 7405 intel_set_cdclk_pre_plane_update(state); 7406 7407 intel_modeset_verify_disabled(dev_priv, state); 7408 } 7409 7410 intel_sagv_pre_plane_update(state); 7411 7412 /* Complete the events for pipes that have now been disabled */ 7413 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7414 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 7415 7416 /* Complete events for now disable pipes here. */ 7417 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) { 7418 spin_lock_irq(&dev->event_lock); 7419 drm_crtc_send_vblank_event(&crtc->base, 7420 new_crtc_state->uapi.event); 7421 spin_unlock_irq(&dev->event_lock); 7422 7423 new_crtc_state->uapi.event = NULL; 7424 } 7425 } 7426 7427 intel_encoders_update_prepare(state); 7428 7429 intel_dbuf_pre_plane_update(state); 7430 intel_mbus_dbox_update(state); 7431 7432 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7433 if (new_crtc_state->do_async_flip) 7434 intel_crtc_enable_flip_done(state, crtc); 7435 } 7436 7437 /* Now enable the clocks, plane, pipe, and connectors that we set up. */ 7438 dev_priv->display.funcs.display->commit_modeset_enables(state); 7439 7440 intel_encoders_update_complete(state); 7441 7442 if (state->modeset) 7443 intel_set_cdclk_post_plane_update(state); 7444 7445 intel_wait_for_vblank_workers(state); 7446 7447 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here 7448 * already, but still need the state for the delayed optimization. To 7449 * fix this: 7450 * - wrap the optimization/post_plane_update stuff into a per-crtc work. 7451 * - schedule that vblank worker _before_ calling hw_done 7452 * - at the start of commit_tail, cancel it _synchrously 7453 * - switch over to the vblank wait helper in the core after that since 7454 * we don't need out special handling any more. 7455 */ 7456 drm_atomic_helper_wait_for_flip_done(dev, &state->base); 7457 7458 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7459 if (new_crtc_state->do_async_flip) 7460 intel_crtc_disable_flip_done(state, crtc); 7461 } 7462 7463 /* 7464 * Now that the vblank has passed, we can go ahead and program the 7465 * optimal watermarks on platforms that need two-step watermark 7466 * programming. 7467 * 7468 * TODO: Move this (and other cleanup) to an async worker eventually. 7469 */ 7470 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7471 new_crtc_state, i) { 7472 /* 7473 * Gen2 reports pipe underruns whenever all planes are disabled. 7474 * So re-enable underrun reporting after some planes get enabled. 7475 * 7476 * We do this before .optimize_watermarks() so that we have a 7477 * chance of catching underruns with the intermediate watermarks 7478 * vs. the new plane configuration. 7479 */ 7480 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state)) 7481 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 7482 7483 intel_optimize_watermarks(state, crtc); 7484 } 7485 7486 intel_dbuf_post_plane_update(state); 7487 intel_psr_post_plane_update(state); 7488 7489 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7490 intel_post_plane_update(state, crtc); 7491 7492 intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]); 7493 7494 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state); 7495 7496 /* Must be done after gamma readout due to HSW split gamma vs. IPS w/a */ 7497 hsw_ips_post_update(state, crtc); 7498 7499 /* 7500 * Activate DRRS after state readout to avoid 7501 * dp_m_n vs. dp_m2_n2 confusion on BDW+. 7502 */ 7503 intel_drrs_activate(new_crtc_state); 7504 7505 /* 7506 * DSB cleanup is done in cleanup_work aligning with framebuffer 7507 * cleanup. So copy and reset the dsb structure to sync with 7508 * commit_done and later do dsb cleanup in cleanup_work. 7509 * 7510 * FIXME get rid of this funny new->old swapping 7511 */ 7512 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb); 7513 } 7514 7515 /* Underruns don't always raise interrupts, so check manually */ 7516 intel_check_cpu_fifo_underruns(dev_priv); 7517 intel_check_pch_fifo_underruns(dev_priv); 7518 7519 if (state->modeset) 7520 intel_verify_planes(state); 7521 7522 intel_sagv_post_plane_update(state); 7523 7524 drm_atomic_helper_commit_hw_done(&state->base); 7525 7526 if (state->modeset) { 7527 /* As one of the primary mmio accessors, KMS has a high 7528 * likelihood of triggering bugs in unclaimed access. After we 7529 * finish modesetting, see if an error has been flagged, and if 7530 * so enable debugging for the next modeset - and hope we catch 7531 * the culprit. 7532 */ 7533 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); 7534 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref); 7535 } 7536 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7537 7538 /* 7539 * Defer the cleanup of the old state to a separate worker to not 7540 * impede the current task (userspace for blocking modesets) that 7541 * are executed inline. For out-of-line asynchronous modesets/flips, 7542 * deferring to a new worker seems overkill, but we would place a 7543 * schedule point (cond_resched()) here anyway to keep latencies 7544 * down. 7545 */ 7546 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work); 7547 queue_work(system_highpri_wq, &state->base.commit_work); 7548 } 7549 7550 static void intel_atomic_commit_work(struct work_struct *work) 7551 { 7552 struct intel_atomic_state *state = 7553 container_of(work, struct intel_atomic_state, base.commit_work); 7554 7555 intel_atomic_commit_tail(state); 7556 } 7557 7558 static int 7559 intel_atomic_commit_ready(struct i915_sw_fence *fence, 7560 enum i915_sw_fence_notify notify) 7561 { 7562 struct intel_atomic_state *state = 7563 container_of(fence, struct intel_atomic_state, commit_ready); 7564 7565 switch (notify) { 7566 case FENCE_COMPLETE: 7567 /* we do blocking waits in the worker, nothing to do here */ 7568 break; 7569 case FENCE_FREE: 7570 { 7571 struct intel_atomic_helper *helper = 7572 &to_i915(state->base.dev)->display.atomic_helper; 7573 7574 if (llist_add(&state->freed, &helper->free_list)) 7575 schedule_work(&helper->free_work); 7576 break; 7577 } 7578 } 7579 7580 return NOTIFY_DONE; 7581 } 7582 7583 static void intel_atomic_track_fbs(struct intel_atomic_state *state) 7584 { 7585 struct intel_plane_state *old_plane_state, *new_plane_state; 7586 struct intel_plane *plane; 7587 int i; 7588 7589 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 7590 new_plane_state, i) 7591 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), 7592 to_intel_frontbuffer(new_plane_state->hw.fb), 7593 plane->frontbuffer_bit); 7594 } 7595 7596 static int intel_atomic_commit(struct drm_device *dev, 7597 struct drm_atomic_state *_state, 7598 bool nonblock) 7599 { 7600 struct intel_atomic_state *state = to_intel_atomic_state(_state); 7601 struct drm_i915_private *dev_priv = to_i915(dev); 7602 int ret = 0; 7603 7604 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 7605 7606 drm_atomic_state_get(&state->base); 7607 i915_sw_fence_init(&state->commit_ready, 7608 intel_atomic_commit_ready); 7609 7610 /* 7611 * The intel_legacy_cursor_update() fast path takes care 7612 * of avoiding the vblank waits for simple cursor 7613 * movement and flips. For cursor on/off and size changes, 7614 * we want to perform the vblank waits so that watermark 7615 * updates happen during the correct frames. Gen9+ have 7616 * double buffered watermarks and so shouldn't need this. 7617 * 7618 * Unset state->legacy_cursor_update before the call to 7619 * drm_atomic_helper_setup_commit() because otherwise 7620 * drm_atomic_helper_wait_for_flip_done() is a noop and 7621 * we get FIFO underruns because we didn't wait 7622 * for vblank. 7623 * 7624 * FIXME doing watermarks and fb cleanup from a vblank worker 7625 * (assuming we had any) would solve these problems. 7626 */ 7627 if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) { 7628 struct intel_crtc_state *new_crtc_state; 7629 struct intel_crtc *crtc; 7630 int i; 7631 7632 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7633 if (new_crtc_state->wm.need_postvbl_update || 7634 new_crtc_state->update_wm_post) 7635 state->base.legacy_cursor_update = false; 7636 } 7637 7638 ret = intel_atomic_prepare_commit(state); 7639 if (ret) { 7640 drm_dbg_atomic(&dev_priv->drm, 7641 "Preparing state failed with %i\n", ret); 7642 i915_sw_fence_commit(&state->commit_ready); 7643 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7644 return ret; 7645 } 7646 7647 ret = drm_atomic_helper_setup_commit(&state->base, nonblock); 7648 if (!ret) 7649 ret = drm_atomic_helper_swap_state(&state->base, true); 7650 if (!ret) 7651 intel_atomic_swap_global_state(state); 7652 7653 if (ret) { 7654 struct intel_crtc_state *new_crtc_state; 7655 struct intel_crtc *crtc; 7656 int i; 7657 7658 i915_sw_fence_commit(&state->commit_ready); 7659 7660 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7661 intel_color_cleanup_commit(new_crtc_state); 7662 7663 drm_atomic_helper_cleanup_planes(dev, &state->base); 7664 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7665 return ret; 7666 } 7667 intel_shared_dpll_swap_state(state); 7668 intel_atomic_track_fbs(state); 7669 7670 drm_atomic_state_get(&state->base); 7671 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work); 7672 7673 i915_sw_fence_commit(&state->commit_ready); 7674 if (nonblock && state->modeset) { 7675 queue_work(dev_priv->display.wq.modeset, &state->base.commit_work); 7676 } else if (nonblock) { 7677 queue_work(dev_priv->display.wq.flip, &state->base.commit_work); 7678 } else { 7679 if (state->modeset) 7680 flush_workqueue(dev_priv->display.wq.modeset); 7681 intel_atomic_commit_tail(state); 7682 } 7683 7684 return 0; 7685 } 7686 7687 /** 7688 * intel_plane_destroy - destroy a plane 7689 * @plane: plane to destroy 7690 * 7691 * Common destruction function for all types of planes (primary, cursor, 7692 * sprite). 7693 */ 7694 void intel_plane_destroy(struct drm_plane *plane) 7695 { 7696 drm_plane_cleanup(plane); 7697 kfree(to_intel_plane(plane)); 7698 } 7699 7700 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv) 7701 { 7702 struct intel_plane *plane; 7703 7704 for_each_intel_plane(&dev_priv->drm, plane) { 7705 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, 7706 plane->pipe); 7707 7708 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base); 7709 } 7710 } 7711 7712 7713 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 7714 struct drm_file *file) 7715 { 7716 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; 7717 struct drm_crtc *drmmode_crtc; 7718 struct intel_crtc *crtc; 7719 7720 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id); 7721 if (!drmmode_crtc) 7722 return -ENOENT; 7723 7724 crtc = to_intel_crtc(drmmode_crtc); 7725 pipe_from_crtc_id->pipe = crtc->pipe; 7726 7727 return 0; 7728 } 7729 7730 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder) 7731 { 7732 struct drm_device *dev = encoder->base.dev; 7733 struct intel_encoder *source_encoder; 7734 u32 possible_clones = 0; 7735 7736 for_each_intel_encoder(dev, source_encoder) { 7737 if (encoders_cloneable(encoder, source_encoder)) 7738 possible_clones |= drm_encoder_mask(&source_encoder->base); 7739 } 7740 7741 return possible_clones; 7742 } 7743 7744 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder) 7745 { 7746 struct drm_device *dev = encoder->base.dev; 7747 struct intel_crtc *crtc; 7748 u32 possible_crtcs = 0; 7749 7750 for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask) 7751 possible_crtcs |= drm_crtc_mask(&crtc->base); 7752 7753 return possible_crtcs; 7754 } 7755 7756 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv) 7757 { 7758 if (!IS_MOBILE(dev_priv)) 7759 return false; 7760 7761 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0) 7762 return false; 7763 7764 if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE)) 7765 return false; 7766 7767 return true; 7768 } 7769 7770 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv) 7771 { 7772 if (DISPLAY_VER(dev_priv) >= 9) 7773 return false; 7774 7775 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) 7776 return false; 7777 7778 if (HAS_PCH_LPT_H(dev_priv) && 7779 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) 7780 return false; 7781 7782 /* DDI E can't be used if DDI A requires 4 lanes */ 7783 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 7784 return false; 7785 7786 if (!dev_priv->display.vbt.int_crt_support) 7787 return false; 7788 7789 return true; 7790 } 7791 7792 static void intel_setup_outputs(struct drm_i915_private *dev_priv) 7793 { 7794 struct intel_encoder *encoder; 7795 bool dpd_is_edp = false; 7796 7797 intel_pps_unlock_regs_wa(dev_priv); 7798 7799 if (!HAS_DISPLAY(dev_priv)) 7800 return; 7801 7802 if (IS_DG2(dev_priv)) { 7803 intel_ddi_init(dev_priv, PORT_A); 7804 intel_ddi_init(dev_priv, PORT_B); 7805 intel_ddi_init(dev_priv, PORT_C); 7806 intel_ddi_init(dev_priv, PORT_D_XELPD); 7807 intel_ddi_init(dev_priv, PORT_TC1); 7808 } else if (IS_ALDERLAKE_P(dev_priv)) { 7809 intel_ddi_init(dev_priv, PORT_A); 7810 intel_ddi_init(dev_priv, PORT_B); 7811 intel_ddi_init(dev_priv, PORT_TC1); 7812 intel_ddi_init(dev_priv, PORT_TC2); 7813 intel_ddi_init(dev_priv, PORT_TC3); 7814 intel_ddi_init(dev_priv, PORT_TC4); 7815 icl_dsi_init(dev_priv); 7816 } else if (IS_ALDERLAKE_S(dev_priv)) { 7817 intel_ddi_init(dev_priv, PORT_A); 7818 intel_ddi_init(dev_priv, PORT_TC1); 7819 intel_ddi_init(dev_priv, PORT_TC2); 7820 intel_ddi_init(dev_priv, PORT_TC3); 7821 intel_ddi_init(dev_priv, PORT_TC4); 7822 } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) { 7823 intel_ddi_init(dev_priv, PORT_A); 7824 intel_ddi_init(dev_priv, PORT_B); 7825 intel_ddi_init(dev_priv, PORT_TC1); 7826 intel_ddi_init(dev_priv, PORT_TC2); 7827 } else if (DISPLAY_VER(dev_priv) >= 12) { 7828 intel_ddi_init(dev_priv, PORT_A); 7829 intel_ddi_init(dev_priv, PORT_B); 7830 intel_ddi_init(dev_priv, PORT_TC1); 7831 intel_ddi_init(dev_priv, PORT_TC2); 7832 intel_ddi_init(dev_priv, PORT_TC3); 7833 intel_ddi_init(dev_priv, PORT_TC4); 7834 intel_ddi_init(dev_priv, PORT_TC5); 7835 intel_ddi_init(dev_priv, PORT_TC6); 7836 icl_dsi_init(dev_priv); 7837 } else if (IS_JSL_EHL(dev_priv)) { 7838 intel_ddi_init(dev_priv, PORT_A); 7839 intel_ddi_init(dev_priv, PORT_B); 7840 intel_ddi_init(dev_priv, PORT_C); 7841 intel_ddi_init(dev_priv, PORT_D); 7842 icl_dsi_init(dev_priv); 7843 } else if (DISPLAY_VER(dev_priv) == 11) { 7844 intel_ddi_init(dev_priv, PORT_A); 7845 intel_ddi_init(dev_priv, PORT_B); 7846 intel_ddi_init(dev_priv, PORT_C); 7847 intel_ddi_init(dev_priv, PORT_D); 7848 intel_ddi_init(dev_priv, PORT_E); 7849 intel_ddi_init(dev_priv, PORT_F); 7850 icl_dsi_init(dev_priv); 7851 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 7852 intel_ddi_init(dev_priv, PORT_A); 7853 intel_ddi_init(dev_priv, PORT_B); 7854 intel_ddi_init(dev_priv, PORT_C); 7855 vlv_dsi_init(dev_priv); 7856 } else if (DISPLAY_VER(dev_priv) >= 9) { 7857 intel_ddi_init(dev_priv, PORT_A); 7858 intel_ddi_init(dev_priv, PORT_B); 7859 intel_ddi_init(dev_priv, PORT_C); 7860 intel_ddi_init(dev_priv, PORT_D); 7861 intel_ddi_init(dev_priv, PORT_E); 7862 } else if (HAS_DDI(dev_priv)) { 7863 u32 found; 7864 7865 if (intel_ddi_crt_present(dev_priv)) 7866 intel_crt_init(dev_priv); 7867 7868 /* Haswell uses DDI functions to detect digital outputs. */ 7869 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 7870 if (found) 7871 intel_ddi_init(dev_priv, PORT_A); 7872 7873 found = intel_de_read(dev_priv, SFUSE_STRAP); 7874 if (found & SFUSE_STRAP_DDIB_DETECTED) 7875 intel_ddi_init(dev_priv, PORT_B); 7876 if (found & SFUSE_STRAP_DDIC_DETECTED) 7877 intel_ddi_init(dev_priv, PORT_C); 7878 if (found & SFUSE_STRAP_DDID_DETECTED) 7879 intel_ddi_init(dev_priv, PORT_D); 7880 if (found & SFUSE_STRAP_DDIF_DETECTED) 7881 intel_ddi_init(dev_priv, PORT_F); 7882 } else if (HAS_PCH_SPLIT(dev_priv)) { 7883 int found; 7884 7885 /* 7886 * intel_edp_init_connector() depends on this completing first, 7887 * to prevent the registration of both eDP and LVDS and the 7888 * incorrect sharing of the PPS. 7889 */ 7890 intel_lvds_init(dev_priv); 7891 intel_crt_init(dev_priv); 7892 7893 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D); 7894 7895 if (ilk_has_edp_a(dev_priv)) 7896 g4x_dp_init(dev_priv, DP_A, PORT_A); 7897 7898 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) { 7899 /* PCH SDVOB multiplex with HDMIB */ 7900 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); 7901 if (!found) 7902 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); 7903 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED)) 7904 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B); 7905 } 7906 7907 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED) 7908 g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); 7909 7910 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED) 7911 g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D); 7912 7913 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED) 7914 g4x_dp_init(dev_priv, PCH_DP_C, PORT_C); 7915 7916 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED) 7917 g4x_dp_init(dev_priv, PCH_DP_D, PORT_D); 7918 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 7919 bool has_edp, has_port; 7920 7921 if (IS_VALLEYVIEW(dev_priv) && dev_priv->display.vbt.int_crt_support) 7922 intel_crt_init(dev_priv); 7923 7924 /* 7925 * The DP_DETECTED bit is the latched state of the DDC 7926 * SDA pin at boot. However since eDP doesn't require DDC 7927 * (no way to plug in a DP->HDMI dongle) the DDC pins for 7928 * eDP ports may have been muxed to an alternate function. 7929 * Thus we can't rely on the DP_DETECTED bit alone to detect 7930 * eDP ports. Consult the VBT as well as DP_DETECTED to 7931 * detect eDP ports. 7932 * 7933 * Sadly the straps seem to be missing sometimes even for HDMI 7934 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap 7935 * and VBT for the presence of the port. Additionally we can't 7936 * trust the port type the VBT declares as we've seen at least 7937 * HDMI ports that the VBT claim are DP or eDP. 7938 */ 7939 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B); 7940 has_port = intel_bios_is_port_present(dev_priv, PORT_B); 7941 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port) 7942 has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B); 7943 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) 7944 g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); 7945 7946 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C); 7947 has_port = intel_bios_is_port_present(dev_priv, PORT_C); 7948 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port) 7949 has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C); 7950 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) 7951 g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); 7952 7953 if (IS_CHERRYVIEW(dev_priv)) { 7954 /* 7955 * eDP not supported on port D, 7956 * so no need to worry about it 7957 */ 7958 has_port = intel_bios_is_port_present(dev_priv, PORT_D); 7959 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port) 7960 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D); 7961 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port) 7962 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D); 7963 } 7964 7965 vlv_dsi_init(dev_priv); 7966 } else if (IS_PINEVIEW(dev_priv)) { 7967 intel_lvds_init(dev_priv); 7968 intel_crt_init(dev_priv); 7969 } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) { 7970 bool found = false; 7971 7972 if (IS_MOBILE(dev_priv)) 7973 intel_lvds_init(dev_priv); 7974 7975 intel_crt_init(dev_priv); 7976 7977 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 7978 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n"); 7979 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); 7980 if (!found && IS_G4X(dev_priv)) { 7981 drm_dbg_kms(&dev_priv->drm, 7982 "probing HDMI on SDVOB\n"); 7983 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); 7984 } 7985 7986 if (!found && IS_G4X(dev_priv)) 7987 g4x_dp_init(dev_priv, DP_B, PORT_B); 7988 } 7989 7990 /* Before G4X SDVOC doesn't have its own detect register */ 7991 7992 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 7993 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n"); 7994 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); 7995 } 7996 7997 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) { 7998 7999 if (IS_G4X(dev_priv)) { 8000 drm_dbg_kms(&dev_priv->drm, 8001 "probing HDMI on SDVOC\n"); 8002 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); 8003 } 8004 if (IS_G4X(dev_priv)) 8005 g4x_dp_init(dev_priv, DP_C, PORT_C); 8006 } 8007 8008 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED)) 8009 g4x_dp_init(dev_priv, DP_D, PORT_D); 8010 8011 if (SUPPORTS_TV(dev_priv)) 8012 intel_tv_init(dev_priv); 8013 } else if (DISPLAY_VER(dev_priv) == 2) { 8014 if (IS_I85X(dev_priv)) 8015 intel_lvds_init(dev_priv); 8016 8017 intel_crt_init(dev_priv); 8018 intel_dvo_init(dev_priv); 8019 } 8020 8021 for_each_intel_encoder(&dev_priv->drm, encoder) { 8022 encoder->base.possible_crtcs = 8023 intel_encoder_possible_crtcs(encoder); 8024 encoder->base.possible_clones = 8025 intel_encoder_possible_clones(encoder); 8026 } 8027 8028 intel_init_pch_refclk(dev_priv); 8029 8030 drm_helper_move_panel_connectors_to_head(&dev_priv->drm); 8031 } 8032 8033 static int max_dotclock(struct drm_i915_private *i915) 8034 { 8035 int max_dotclock = i915->max_dotclk_freq; 8036 8037 /* icl+ might use bigjoiner */ 8038 if (DISPLAY_VER(i915) >= 11) 8039 max_dotclock *= 2; 8040 8041 return max_dotclock; 8042 } 8043 8044 static enum drm_mode_status 8045 intel_mode_valid(struct drm_device *dev, 8046 const struct drm_display_mode *mode) 8047 { 8048 struct drm_i915_private *dev_priv = to_i915(dev); 8049 int hdisplay_max, htotal_max; 8050 int vdisplay_max, vtotal_max; 8051 8052 /* 8053 * Can't reject DBLSCAN here because Xorg ddxen can add piles 8054 * of DBLSCAN modes to the output's mode list when they detect 8055 * the scaling mode property on the connector. And they don't 8056 * ask the kernel to validate those modes in any way until 8057 * modeset time at which point the client gets a protocol error. 8058 * So in order to not upset those clients we silently ignore the 8059 * DBLSCAN flag on such connectors. For other connectors we will 8060 * reject modes with the DBLSCAN flag in encoder->compute_config(). 8061 * And we always reject DBLSCAN modes in connector->mode_valid() 8062 * as we never want such modes on the connector's mode list. 8063 */ 8064 8065 if (mode->vscan > 1) 8066 return MODE_NO_VSCAN; 8067 8068 if (mode->flags & DRM_MODE_FLAG_HSKEW) 8069 return MODE_H_ILLEGAL; 8070 8071 if (mode->flags & (DRM_MODE_FLAG_CSYNC | 8072 DRM_MODE_FLAG_NCSYNC | 8073 DRM_MODE_FLAG_PCSYNC)) 8074 return MODE_HSYNC; 8075 8076 if (mode->flags & (DRM_MODE_FLAG_BCAST | 8077 DRM_MODE_FLAG_PIXMUX | 8078 DRM_MODE_FLAG_CLKDIV2)) 8079 return MODE_BAD; 8080 8081 /* 8082 * Reject clearly excessive dotclocks early to 8083 * avoid having to worry about huge integers later. 8084 */ 8085 if (mode->clock > max_dotclock(dev_priv)) 8086 return MODE_CLOCK_HIGH; 8087 8088 /* Transcoder timing limits */ 8089 if (DISPLAY_VER(dev_priv) >= 11) { 8090 hdisplay_max = 16384; 8091 vdisplay_max = 8192; 8092 htotal_max = 16384; 8093 vtotal_max = 8192; 8094 } else if (DISPLAY_VER(dev_priv) >= 9 || 8095 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 8096 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ 8097 vdisplay_max = 4096; 8098 htotal_max = 8192; 8099 vtotal_max = 8192; 8100 } else if (DISPLAY_VER(dev_priv) >= 3) { 8101 hdisplay_max = 4096; 8102 vdisplay_max = 4096; 8103 htotal_max = 8192; 8104 vtotal_max = 8192; 8105 } else { 8106 hdisplay_max = 2048; 8107 vdisplay_max = 2048; 8108 htotal_max = 4096; 8109 vtotal_max = 4096; 8110 } 8111 8112 if (mode->hdisplay > hdisplay_max || 8113 mode->hsync_start > htotal_max || 8114 mode->hsync_end > htotal_max || 8115 mode->htotal > htotal_max) 8116 return MODE_H_ILLEGAL; 8117 8118 if (mode->vdisplay > vdisplay_max || 8119 mode->vsync_start > vtotal_max || 8120 mode->vsync_end > vtotal_max || 8121 mode->vtotal > vtotal_max) 8122 return MODE_V_ILLEGAL; 8123 8124 if (DISPLAY_VER(dev_priv) >= 5) { 8125 if (mode->hdisplay < 64 || 8126 mode->htotal - mode->hdisplay < 32) 8127 return MODE_H_ILLEGAL; 8128 8129 if (mode->vtotal - mode->vdisplay < 5) 8130 return MODE_V_ILLEGAL; 8131 } else { 8132 if (mode->htotal - mode->hdisplay < 32) 8133 return MODE_H_ILLEGAL; 8134 8135 if (mode->vtotal - mode->vdisplay < 3) 8136 return MODE_V_ILLEGAL; 8137 } 8138 8139 /* 8140 * Cantiga+ cannot handle modes with a hsync front porch of 0. 8141 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. 8142 */ 8143 if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) && 8144 mode->hsync_start == mode->hdisplay) 8145 return MODE_H_ILLEGAL; 8146 8147 return MODE_OK; 8148 } 8149 8150 enum drm_mode_status 8151 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 8152 const struct drm_display_mode *mode, 8153 bool bigjoiner) 8154 { 8155 int plane_width_max, plane_height_max; 8156 8157 /* 8158 * intel_mode_valid() should be 8159 * sufficient on older platforms. 8160 */ 8161 if (DISPLAY_VER(dev_priv) < 9) 8162 return MODE_OK; 8163 8164 /* 8165 * Most people will probably want a fullscreen 8166 * plane so let's not advertize modes that are 8167 * too big for that. 8168 */ 8169 if (DISPLAY_VER(dev_priv) >= 11) { 8170 plane_width_max = 5120 << bigjoiner; 8171 plane_height_max = 4320; 8172 } else { 8173 plane_width_max = 5120; 8174 plane_height_max = 4096; 8175 } 8176 8177 if (mode->hdisplay > plane_width_max) 8178 return MODE_H_ILLEGAL; 8179 8180 if (mode->vdisplay > plane_height_max) 8181 return MODE_V_ILLEGAL; 8182 8183 return MODE_OK; 8184 } 8185 8186 static const struct drm_mode_config_funcs intel_mode_funcs = { 8187 .fb_create = intel_user_framebuffer_create, 8188 .get_format_info = intel_fb_get_format_info, 8189 .output_poll_changed = intel_fbdev_output_poll_changed, 8190 .mode_valid = intel_mode_valid, 8191 .atomic_check = intel_atomic_check, 8192 .atomic_commit = intel_atomic_commit, 8193 .atomic_state_alloc = intel_atomic_state_alloc, 8194 .atomic_state_clear = intel_atomic_state_clear, 8195 .atomic_state_free = intel_atomic_state_free, 8196 }; 8197 8198 static const struct intel_display_funcs skl_display_funcs = { 8199 .get_pipe_config = hsw_get_pipe_config, 8200 .crtc_enable = hsw_crtc_enable, 8201 .crtc_disable = hsw_crtc_disable, 8202 .commit_modeset_enables = skl_commit_modeset_enables, 8203 .get_initial_plane_config = skl_get_initial_plane_config, 8204 }; 8205 8206 static const struct intel_display_funcs ddi_display_funcs = { 8207 .get_pipe_config = hsw_get_pipe_config, 8208 .crtc_enable = hsw_crtc_enable, 8209 .crtc_disable = hsw_crtc_disable, 8210 .commit_modeset_enables = intel_commit_modeset_enables, 8211 .get_initial_plane_config = i9xx_get_initial_plane_config, 8212 }; 8213 8214 static const struct intel_display_funcs pch_split_display_funcs = { 8215 .get_pipe_config = ilk_get_pipe_config, 8216 .crtc_enable = ilk_crtc_enable, 8217 .crtc_disable = ilk_crtc_disable, 8218 .commit_modeset_enables = intel_commit_modeset_enables, 8219 .get_initial_plane_config = i9xx_get_initial_plane_config, 8220 }; 8221 8222 static const struct intel_display_funcs vlv_display_funcs = { 8223 .get_pipe_config = i9xx_get_pipe_config, 8224 .crtc_enable = valleyview_crtc_enable, 8225 .crtc_disable = i9xx_crtc_disable, 8226 .commit_modeset_enables = intel_commit_modeset_enables, 8227 .get_initial_plane_config = i9xx_get_initial_plane_config, 8228 }; 8229 8230 static const struct intel_display_funcs i9xx_display_funcs = { 8231 .get_pipe_config = i9xx_get_pipe_config, 8232 .crtc_enable = i9xx_crtc_enable, 8233 .crtc_disable = i9xx_crtc_disable, 8234 .commit_modeset_enables = intel_commit_modeset_enables, 8235 .get_initial_plane_config = i9xx_get_initial_plane_config, 8236 }; 8237 8238 /** 8239 * intel_init_display_hooks - initialize the display modesetting hooks 8240 * @dev_priv: device private 8241 */ 8242 void intel_init_display_hooks(struct drm_i915_private *dev_priv) 8243 { 8244 if (!HAS_DISPLAY(dev_priv)) 8245 return; 8246 8247 intel_color_init_hooks(dev_priv); 8248 intel_init_cdclk_hooks(dev_priv); 8249 intel_audio_hooks_init(dev_priv); 8250 8251 intel_dpll_init_clock_hook(dev_priv); 8252 8253 if (DISPLAY_VER(dev_priv) >= 9) { 8254 dev_priv->display.funcs.display = &skl_display_funcs; 8255 } else if (HAS_DDI(dev_priv)) { 8256 dev_priv->display.funcs.display = &ddi_display_funcs; 8257 } else if (HAS_PCH_SPLIT(dev_priv)) { 8258 dev_priv->display.funcs.display = &pch_split_display_funcs; 8259 } else if (IS_CHERRYVIEW(dev_priv) || 8260 IS_VALLEYVIEW(dev_priv)) { 8261 dev_priv->display.funcs.display = &vlv_display_funcs; 8262 } else { 8263 dev_priv->display.funcs.display = &i9xx_display_funcs; 8264 } 8265 8266 intel_fdi_init_hook(dev_priv); 8267 } 8268 8269 void intel_modeset_init_hw(struct drm_i915_private *i915) 8270 { 8271 struct intel_cdclk_state *cdclk_state; 8272 8273 if (!HAS_DISPLAY(i915)) 8274 return; 8275 8276 cdclk_state = to_intel_cdclk_state(i915->display.cdclk.obj.state); 8277 8278 intel_update_cdclk(i915); 8279 intel_cdclk_dump_config(i915, &i915->display.cdclk.hw, "Current CDCLK"); 8280 cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw; 8281 } 8282 8283 static int intel_initial_commit(struct drm_device *dev) 8284 { 8285 struct drm_atomic_state *state = NULL; 8286 struct drm_modeset_acquire_ctx ctx; 8287 struct intel_crtc *crtc; 8288 int ret = 0; 8289 8290 state = drm_atomic_state_alloc(dev); 8291 if (!state) 8292 return -ENOMEM; 8293 8294 drm_modeset_acquire_init(&ctx, 0); 8295 8296 retry: 8297 state->acquire_ctx = &ctx; 8298 8299 for_each_intel_crtc(dev, crtc) { 8300 struct intel_crtc_state *crtc_state = 8301 intel_atomic_get_crtc_state(state, crtc); 8302 8303 if (IS_ERR(crtc_state)) { 8304 ret = PTR_ERR(crtc_state); 8305 goto out; 8306 } 8307 8308 if (crtc_state->hw.active) { 8309 struct intel_encoder *encoder; 8310 8311 /* 8312 * We've not yet detected sink capabilities 8313 * (audio,infoframes,etc.) and thus we don't want to 8314 * force a full state recomputation yet. We want that to 8315 * happen only for the first real commit from userspace. 8316 * So preserve the inherited flag for the time being. 8317 */ 8318 crtc_state->inherited = true; 8319 8320 ret = drm_atomic_add_affected_planes(state, &crtc->base); 8321 if (ret) 8322 goto out; 8323 8324 /* 8325 * FIXME hack to force a LUT update to avoid the 8326 * plane update forcing the pipe gamma on without 8327 * having a proper LUT loaded. Remove once we 8328 * have readout for pipe gamma enable. 8329 */ 8330 crtc_state->uapi.color_mgmt_changed = true; 8331 8332 for_each_intel_encoder_mask(dev, encoder, 8333 crtc_state->uapi.encoder_mask) { 8334 if (encoder->initial_fastset_check && 8335 !encoder->initial_fastset_check(encoder, crtc_state)) { 8336 ret = drm_atomic_add_affected_connectors(state, 8337 &crtc->base); 8338 if (ret) 8339 goto out; 8340 } 8341 } 8342 } 8343 } 8344 8345 ret = drm_atomic_commit(state); 8346 8347 out: 8348 if (ret == -EDEADLK) { 8349 drm_atomic_state_clear(state); 8350 drm_modeset_backoff(&ctx); 8351 goto retry; 8352 } 8353 8354 drm_atomic_state_put(state); 8355 8356 drm_modeset_drop_locks(&ctx); 8357 drm_modeset_acquire_fini(&ctx); 8358 8359 return ret; 8360 } 8361 8362 static const struct drm_mode_config_helper_funcs intel_mode_config_funcs = { 8363 .atomic_commit_setup = drm_dp_mst_atomic_setup_commit, 8364 }; 8365 8366 static void intel_mode_config_init(struct drm_i915_private *i915) 8367 { 8368 struct drm_mode_config *mode_config = &i915->drm.mode_config; 8369 8370 drm_mode_config_init(&i915->drm); 8371 INIT_LIST_HEAD(&i915->display.global.obj_list); 8372 8373 mode_config->min_width = 0; 8374 mode_config->min_height = 0; 8375 8376 mode_config->preferred_depth = 24; 8377 mode_config->prefer_shadow = 1; 8378 8379 mode_config->funcs = &intel_mode_funcs; 8380 mode_config->helper_private = &intel_mode_config_funcs; 8381 8382 mode_config->async_page_flip = HAS_ASYNC_FLIPS(i915); 8383 8384 /* 8385 * Maximum framebuffer dimensions, chosen to match 8386 * the maximum render engine surface size on gen4+. 8387 */ 8388 if (DISPLAY_VER(i915) >= 7) { 8389 mode_config->max_width = 16384; 8390 mode_config->max_height = 16384; 8391 } else if (DISPLAY_VER(i915) >= 4) { 8392 mode_config->max_width = 8192; 8393 mode_config->max_height = 8192; 8394 } else if (DISPLAY_VER(i915) == 3) { 8395 mode_config->max_width = 4096; 8396 mode_config->max_height = 4096; 8397 } else { 8398 mode_config->max_width = 2048; 8399 mode_config->max_height = 2048; 8400 } 8401 8402 if (IS_I845G(i915) || IS_I865G(i915)) { 8403 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512; 8404 mode_config->cursor_height = 1023; 8405 } else if (IS_I830(i915) || IS_I85X(i915) || 8406 IS_I915G(i915) || IS_I915GM(i915)) { 8407 mode_config->cursor_width = 64; 8408 mode_config->cursor_height = 64; 8409 } else { 8410 mode_config->cursor_width = 256; 8411 mode_config->cursor_height = 256; 8412 } 8413 } 8414 8415 static void intel_mode_config_cleanup(struct drm_i915_private *i915) 8416 { 8417 intel_atomic_global_obj_cleanup(i915); 8418 drm_mode_config_cleanup(&i915->drm); 8419 } 8420 8421 /* part #1: call before irq install */ 8422 int intel_modeset_init_noirq(struct drm_i915_private *i915) 8423 { 8424 int ret; 8425 8426 if (i915_inject_probe_failure(i915)) 8427 return -ENODEV; 8428 8429 if (HAS_DISPLAY(i915)) { 8430 ret = drm_vblank_init(&i915->drm, 8431 INTEL_NUM_PIPES(i915)); 8432 if (ret) 8433 return ret; 8434 } 8435 8436 intel_bios_init(i915); 8437 8438 ret = intel_vga_register(i915); 8439 if (ret) 8440 goto cleanup_bios; 8441 8442 /* FIXME: completely on the wrong abstraction layer */ 8443 ret = intel_power_domains_init(i915); 8444 if (ret < 0) 8445 goto cleanup_vga; 8446 8447 intel_power_domains_init_hw(i915, false); 8448 8449 if (!HAS_DISPLAY(i915)) 8450 return 0; 8451 8452 intel_dmc_init(i915); 8453 8454 i915->display.wq.modeset = alloc_ordered_workqueue("i915_modeset", 0); 8455 i915->display.wq.flip = alloc_workqueue("i915_flip", WQ_HIGHPRI | 8456 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE); 8457 8458 intel_mode_config_init(i915); 8459 8460 ret = intel_cdclk_init(i915); 8461 if (ret) 8462 goto cleanup_vga_client_pw_domain_dmc; 8463 8464 ret = intel_color_init(i915); 8465 if (ret) 8466 goto cleanup_vga_client_pw_domain_dmc; 8467 8468 ret = intel_dbuf_init(i915); 8469 if (ret) 8470 goto cleanup_vga_client_pw_domain_dmc; 8471 8472 ret = intel_bw_init(i915); 8473 if (ret) 8474 goto cleanup_vga_client_pw_domain_dmc; 8475 8476 init_llist_head(&i915->display.atomic_helper.free_list); 8477 INIT_WORK(&i915->display.atomic_helper.free_work, 8478 intel_atomic_helper_free_state_worker); 8479 8480 intel_init_quirks(i915); 8481 8482 intel_fbc_init(i915); 8483 8484 return 0; 8485 8486 cleanup_vga_client_pw_domain_dmc: 8487 intel_dmc_fini(i915); 8488 intel_power_domains_driver_remove(i915); 8489 cleanup_vga: 8490 intel_vga_unregister(i915); 8491 cleanup_bios: 8492 intel_bios_driver_remove(i915); 8493 8494 return ret; 8495 } 8496 8497 /* part #2: call after irq install, but before gem init */ 8498 int intel_modeset_init_nogem(struct drm_i915_private *i915) 8499 { 8500 struct drm_device *dev = &i915->drm; 8501 enum pipe pipe; 8502 struct intel_crtc *crtc; 8503 int ret; 8504 8505 if (!HAS_DISPLAY(i915)) 8506 return 0; 8507 8508 intel_wm_init(i915); 8509 8510 intel_panel_sanitize_ssc(i915); 8511 8512 intel_pps_setup(i915); 8513 8514 intel_gmbus_setup(i915); 8515 8516 drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n", 8517 INTEL_NUM_PIPES(i915), 8518 INTEL_NUM_PIPES(i915) > 1 ? "s" : ""); 8519 8520 for_each_pipe(i915, pipe) { 8521 ret = intel_crtc_init(i915, pipe); 8522 if (ret) { 8523 intel_mode_config_cleanup(i915); 8524 return ret; 8525 } 8526 } 8527 8528 intel_plane_possible_crtcs_init(i915); 8529 intel_shared_dpll_init(i915); 8530 intel_fdi_pll_freq_update(i915); 8531 8532 intel_update_czclk(i915); 8533 intel_modeset_init_hw(i915); 8534 intel_dpll_update_ref_clks(i915); 8535 8536 intel_hdcp_component_init(i915); 8537 8538 if (i915->display.cdclk.max_cdclk_freq == 0) 8539 intel_update_max_cdclk(i915); 8540 8541 intel_hti_init(i915); 8542 8543 /* Just disable it once at startup */ 8544 intel_vga_disable(i915); 8545 intel_setup_outputs(i915); 8546 8547 drm_modeset_lock_all(dev); 8548 intel_modeset_setup_hw_state(i915, dev->mode_config.acquire_ctx); 8549 intel_acpi_assign_connector_fwnodes(i915); 8550 drm_modeset_unlock_all(dev); 8551 8552 for_each_intel_crtc(dev, crtc) { 8553 if (!to_intel_crtc_state(crtc->base.state)->uapi.active) 8554 continue; 8555 intel_crtc_initial_plane_config(crtc); 8556 } 8557 8558 /* 8559 * Make sure hardware watermarks really match the state we read out. 8560 * Note that we need to do this after reconstructing the BIOS fb's 8561 * since the watermark calculation done here will use pstate->fb. 8562 */ 8563 if (!HAS_GMCH(i915)) 8564 ilk_wm_sanitize(i915); 8565 8566 return 0; 8567 } 8568 8569 /* part #3: call after gem init */ 8570 int intel_modeset_init(struct drm_i915_private *i915) 8571 { 8572 int ret; 8573 8574 if (!HAS_DISPLAY(i915)) 8575 return 0; 8576 8577 /* 8578 * Force all active planes to recompute their states. So that on 8579 * mode_setcrtc after probe, all the intel_plane_state variables 8580 * are already calculated and there is no assert_plane warnings 8581 * during bootup. 8582 */ 8583 ret = intel_initial_commit(&i915->drm); 8584 if (ret) 8585 drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret); 8586 8587 intel_overlay_setup(i915); 8588 8589 ret = intel_fbdev_init(&i915->drm); 8590 if (ret) 8591 return ret; 8592 8593 /* Only enable hotplug handling once the fbdev is fully set up. */ 8594 intel_hpd_init(i915); 8595 intel_hpd_poll_disable(i915); 8596 8597 skl_watermark_ipc_init(i915); 8598 8599 return 0; 8600 } 8601 8602 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 8603 { 8604 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 8605 enum transcoder cpu_transcoder = (enum transcoder)pipe; 8606 /* 640x480@60Hz, ~25175 kHz */ 8607 struct dpll clock = { 8608 .m1 = 18, 8609 .m2 = 7, 8610 .p1 = 13, 8611 .p2 = 4, 8612 .n = 2, 8613 }; 8614 u32 dpll, fp; 8615 int i; 8616 8617 drm_WARN_ON(&dev_priv->drm, 8618 i9xx_calc_dpll_params(48000, &clock) != 25154); 8619 8620 drm_dbg_kms(&dev_priv->drm, 8621 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n", 8622 pipe_name(pipe), clock.vco, clock.dot); 8623 8624 fp = i9xx_dpll_compute_fp(&clock); 8625 dpll = DPLL_DVO_2X_MODE | 8626 DPLL_VGA_MODE_DIS | 8627 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | 8628 PLL_P2_DIVIDE_BY_4 | 8629 PLL_REF_INPUT_DREFCLK | 8630 DPLL_VCO_ENABLE; 8631 8632 intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder), (640 - 1) | ((800 - 1) << 16)); 8633 intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder), (640 - 1) | ((800 - 1) << 16)); 8634 intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder), (656 - 1) | ((752 - 1) << 16)); 8635 intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder), (480 - 1) | ((525 - 1) << 16)); 8636 intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), (480 - 1) | ((525 - 1) << 16)); 8637 intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder), (490 - 1) | ((492 - 1) << 16)); 8638 intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1)); 8639 8640 intel_de_write(dev_priv, FP0(pipe), fp); 8641 intel_de_write(dev_priv, FP1(pipe), fp); 8642 8643 /* 8644 * Apparently we need to have VGA mode enabled prior to changing 8645 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 8646 * dividers, even though the register value does change. 8647 */ 8648 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); 8649 intel_de_write(dev_priv, DPLL(pipe), dpll); 8650 8651 /* Wait for the clocks to stabilize. */ 8652 intel_de_posting_read(dev_priv, DPLL(pipe)); 8653 udelay(150); 8654 8655 /* The pixel multiplier can only be updated once the 8656 * DPLL is enabled and the clocks are stable. 8657 * 8658 * So write it again. 8659 */ 8660 intel_de_write(dev_priv, DPLL(pipe), dpll); 8661 8662 /* We do this three times for luck */ 8663 for (i = 0; i < 3 ; i++) { 8664 intel_de_write(dev_priv, DPLL(pipe), dpll); 8665 intel_de_posting_read(dev_priv, DPLL(pipe)); 8666 udelay(150); /* wait for warmup */ 8667 } 8668 8669 intel_de_write(dev_priv, TRANSCONF(pipe), TRANSCONF_ENABLE); 8670 intel_de_posting_read(dev_priv, TRANSCONF(pipe)); 8671 8672 intel_wait_for_pipe_scanline_moving(crtc); 8673 } 8674 8675 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 8676 { 8677 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 8678 8679 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n", 8680 pipe_name(pipe)); 8681 8682 drm_WARN_ON(&dev_priv->drm, 8683 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE); 8684 drm_WARN_ON(&dev_priv->drm, 8685 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE); 8686 drm_WARN_ON(&dev_priv->drm, 8687 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE); 8688 drm_WARN_ON(&dev_priv->drm, 8689 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK); 8690 drm_WARN_ON(&dev_priv->drm, 8691 intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK); 8692 8693 intel_de_write(dev_priv, TRANSCONF(pipe), 0); 8694 intel_de_posting_read(dev_priv, TRANSCONF(pipe)); 8695 8696 intel_wait_for_pipe_scanline_stopped(crtc); 8697 8698 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); 8699 intel_de_posting_read(dev_priv, DPLL(pipe)); 8700 } 8701 8702 void intel_display_resume(struct drm_device *dev) 8703 { 8704 struct drm_i915_private *i915 = to_i915(dev); 8705 struct drm_atomic_state *state = i915->display.restore.modeset_state; 8706 struct drm_modeset_acquire_ctx ctx; 8707 int ret; 8708 8709 if (!HAS_DISPLAY(i915)) 8710 return; 8711 8712 i915->display.restore.modeset_state = NULL; 8713 if (state) 8714 state->acquire_ctx = &ctx; 8715 8716 drm_modeset_acquire_init(&ctx, 0); 8717 8718 while (1) { 8719 ret = drm_modeset_lock_all_ctx(dev, &ctx); 8720 if (ret != -EDEADLK) 8721 break; 8722 8723 drm_modeset_backoff(&ctx); 8724 } 8725 8726 if (!ret) 8727 ret = __intel_display_resume(i915, state, &ctx); 8728 8729 skl_watermark_ipc_update(i915); 8730 drm_modeset_drop_locks(&ctx); 8731 drm_modeset_acquire_fini(&ctx); 8732 8733 if (ret) 8734 drm_err(&i915->drm, 8735 "Restoring old state failed with %i\n", ret); 8736 if (state) 8737 drm_atomic_state_put(state); 8738 } 8739 8740 static void intel_hpd_poll_fini(struct drm_i915_private *i915) 8741 { 8742 struct intel_connector *connector; 8743 struct drm_connector_list_iter conn_iter; 8744 8745 /* Kill all the work that may have been queued by hpd. */ 8746 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 8747 for_each_intel_connector_iter(connector, &conn_iter) { 8748 if (connector->modeset_retry_work.func) 8749 cancel_work_sync(&connector->modeset_retry_work); 8750 if (connector->hdcp.shim) { 8751 cancel_delayed_work_sync(&connector->hdcp.check_work); 8752 cancel_work_sync(&connector->hdcp.prop_work); 8753 } 8754 } 8755 drm_connector_list_iter_end(&conn_iter); 8756 } 8757 8758 /* part #1: call before irq uninstall */ 8759 void intel_modeset_driver_remove(struct drm_i915_private *i915) 8760 { 8761 if (!HAS_DISPLAY(i915)) 8762 return; 8763 8764 flush_workqueue(i915->display.wq.flip); 8765 flush_workqueue(i915->display.wq.modeset); 8766 8767 flush_work(&i915->display.atomic_helper.free_work); 8768 drm_WARN_ON(&i915->drm, !llist_empty(&i915->display.atomic_helper.free_list)); 8769 8770 /* 8771 * MST topology needs to be suspended so we don't have any calls to 8772 * fbdev after it's finalized. MST will be destroyed later as part of 8773 * drm_mode_config_cleanup() 8774 */ 8775 intel_dp_mst_suspend(i915); 8776 } 8777 8778 /* part #2: call after irq uninstall */ 8779 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915) 8780 { 8781 if (!HAS_DISPLAY(i915)) 8782 return; 8783 8784 /* 8785 * Due to the hpd irq storm handling the hotplug work can re-arm the 8786 * poll handlers. Hence disable polling after hpd handling is shut down. 8787 */ 8788 intel_hpd_poll_fini(i915); 8789 8790 /* poll work can call into fbdev, hence clean that up afterwards */ 8791 intel_fbdev_fini(i915); 8792 8793 intel_unregister_dsm_handler(); 8794 8795 /* flush any delayed tasks or pending work */ 8796 flush_scheduled_work(); 8797 8798 intel_hdcp_component_fini(i915); 8799 8800 intel_mode_config_cleanup(i915); 8801 8802 intel_overlay_cleanup(i915); 8803 8804 intel_gmbus_teardown(i915); 8805 8806 destroy_workqueue(i915->display.wq.flip); 8807 destroy_workqueue(i915->display.wq.modeset); 8808 8809 intel_fbc_cleanup(i915); 8810 } 8811 8812 /* part #3: call after gem init */ 8813 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915) 8814 { 8815 intel_dmc_fini(i915); 8816 8817 intel_power_domains_driver_remove(i915); 8818 8819 intel_vga_unregister(i915); 8820 8821 intel_bios_driver_remove(i915); 8822 } 8823 8824 bool intel_modeset_probe_defer(struct pci_dev *pdev) 8825 { 8826 struct drm_privacy_screen *privacy_screen; 8827 8828 /* 8829 * apple-gmux is needed on dual GPU MacBook Pro 8830 * to probe the panel if we're the inactive GPU. 8831 */ 8832 if (vga_switcheroo_client_probe_defer(pdev)) 8833 return true; 8834 8835 /* If the LCD panel has a privacy-screen, wait for it */ 8836 privacy_screen = drm_privacy_screen_get(&pdev->dev, NULL); 8837 if (IS_ERR(privacy_screen) && PTR_ERR(privacy_screen) == -EPROBE_DEFER) 8838 return true; 8839 8840 drm_privacy_screen_put(privacy_screen); 8841 8842 return false; 8843 } 8844 8845 void intel_display_driver_register(struct drm_i915_private *i915) 8846 { 8847 if (!HAS_DISPLAY(i915)) 8848 return; 8849 8850 intel_display_debugfs_register(i915); 8851 8852 /* Must be done after probing outputs */ 8853 intel_opregion_register(i915); 8854 intel_acpi_video_register(i915); 8855 8856 intel_audio_init(i915); 8857 8858 /* 8859 * Some ports require correctly set-up hpd registers for 8860 * detection to work properly (leading to ghost connected 8861 * connector status), e.g. VGA on gm45. Hence we can only set 8862 * up the initial fbdev config after hpd irqs are fully 8863 * enabled. We do it last so that the async config cannot run 8864 * before the connectors are registered. 8865 */ 8866 intel_fbdev_initial_config_async(i915); 8867 8868 /* 8869 * We need to coordinate the hotplugs with the asynchronous 8870 * fbdev configuration, for which we use the 8871 * fbdev->async_cookie. 8872 */ 8873 drm_kms_helper_poll_init(&i915->drm); 8874 } 8875 8876 void intel_display_driver_unregister(struct drm_i915_private *i915) 8877 { 8878 if (!HAS_DISPLAY(i915)) 8879 return; 8880 8881 intel_fbdev_unregister(i915); 8882 intel_audio_deinit(i915); 8883 8884 /* 8885 * After flushing the fbdev (incl. a late async config which 8886 * will have delayed queuing of a hotplug event), then flush 8887 * the hotplug events. 8888 */ 8889 drm_kms_helper_poll_fini(&i915->drm); 8890 drm_atomic_helper_shutdown(&i915->drm); 8891 8892 acpi_video_unregister(); 8893 intel_opregion_unregister(i915); 8894 } 8895 8896 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915) 8897 { 8898 return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915); 8899 } 8900