1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <acpi/video.h> 28 #include <linux/i2c.h> 29 #include <linux/input.h> 30 #include <linux/intel-iommu.h> 31 #include <linux/kernel.h> 32 #include <linux/module.h> 33 #include <linux/dma-resv.h> 34 #include <linux/slab.h> 35 #include <linux/string_helpers.h> 36 #include <linux/vga_switcheroo.h> 37 38 #include <drm/drm_atomic.h> 39 #include <drm/drm_atomic_helper.h> 40 #include <drm/drm_atomic_uapi.h> 41 #include <drm/drm_damage_helper.h> 42 #include <drm/dp/drm_dp_helper.h> 43 #include <drm/drm_edid.h> 44 #include <drm/drm_fourcc.h> 45 #include <drm/drm_plane_helper.h> 46 #include <drm/drm_privacy_screen_consumer.h> 47 #include <drm/drm_probe_helper.h> 48 #include <drm/drm_rect.h> 49 50 #include "display/intel_audio.h" 51 #include "display/intel_crt.h" 52 #include "display/intel_ddi.h" 53 #include "display/intel_display_debugfs.h" 54 #include "display/intel_display_power.h" 55 #include "display/intel_dp.h" 56 #include "display/intel_dp_mst.h" 57 #include "display/intel_dpll.h" 58 #include "display/intel_dpll_mgr.h" 59 #include "display/intel_drrs.h" 60 #include "display/intel_dsi.h" 61 #include "display/intel_dvo.h" 62 #include "display/intel_fb.h" 63 #include "display/intel_gmbus.h" 64 #include "display/intel_hdmi.h" 65 #include "display/intel_lvds.h" 66 #include "display/intel_sdvo.h" 67 #include "display/intel_snps_phy.h" 68 #include "display/intel_tv.h" 69 #include "display/intel_vdsc.h" 70 #include "display/intel_vrr.h" 71 72 #include "gem/i915_gem_lmem.h" 73 #include "gem/i915_gem_object.h" 74 75 #include "gt/gen8_ppgtt.h" 76 77 #include "g4x_dp.h" 78 #include "g4x_hdmi.h" 79 #include "hsw_ips.h" 80 #include "i915_drv.h" 81 #include "i915_utils.h" 82 #include "icl_dsi.h" 83 #include "intel_acpi.h" 84 #include "intel_atomic.h" 85 #include "intel_atomic_plane.h" 86 #include "intel_bw.h" 87 #include "intel_cdclk.h" 88 #include "intel_color.h" 89 #include "intel_crtc.h" 90 #include "intel_de.h" 91 #include "intel_display_types.h" 92 #include "intel_dmc.h" 93 #include "intel_dp_link_training.h" 94 #include "intel_dpt.h" 95 #include "intel_fbc.h" 96 #include "intel_fbdev.h" 97 #include "intel_fdi.h" 98 #include "intel_fifo_underrun.h" 99 #include "intel_frontbuffer.h" 100 #include "intel_hdcp.h" 101 #include "intel_hotplug.h" 102 #include "intel_overlay.h" 103 #include "intel_panel.h" 104 #include "intel_pch_display.h" 105 #include "intel_pch_refclk.h" 106 #include "intel_pcode.h" 107 #include "intel_pipe_crc.h" 108 #include "intel_plane_initial.h" 109 #include "intel_pm.h" 110 #include "intel_pps.h" 111 #include "intel_psr.h" 112 #include "intel_quirks.h" 113 #include "intel_sprite.h" 114 #include "intel_tc.h" 115 #include "intel_vga.h" 116 #include "i9xx_plane.h" 117 #include "skl_scaler.h" 118 #include "skl_universal_plane.h" 119 #include "vlv_dsi.h" 120 #include "vlv_dsi_pll.h" 121 #include "vlv_dsi_regs.h" 122 #include "vlv_sideband.h" 123 124 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state); 125 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state); 126 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state); 127 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state); 128 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state); 129 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state); 130 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state); 131 static void intel_modeset_setup_hw_state(struct drm_device *dev, 132 struct drm_modeset_acquire_ctx *ctx); 133 134 /** 135 * intel_update_watermarks - update FIFO watermark values based on current modes 136 * @dev_priv: i915 device 137 * 138 * Calculate watermark values for the various WM regs based on current mode 139 * and plane configuration. 140 * 141 * There are several cases to deal with here: 142 * - normal (i.e. non-self-refresh) 143 * - self-refresh (SR) mode 144 * - lines are large relative to FIFO size (buffer can hold up to 2) 145 * - lines are small relative to FIFO size (buffer can hold more than 2 146 * lines), so need to account for TLB latency 147 * 148 * The normal calculation is: 149 * watermark = dotclock * bytes per pixel * latency 150 * where latency is platform & configuration dependent (we assume pessimal 151 * values here). 152 * 153 * The SR calculation is: 154 * watermark = (trunc(latency/line time)+1) * surface width * 155 * bytes per pixel 156 * where 157 * line time = htotal / dotclock 158 * surface width = hdisplay for normal plane and 64 for cursor 159 * and latency is assumed to be high, as above. 160 * 161 * The final value programmed to the register should always be rounded up, 162 * and include an extra 2 entries to account for clock crossings. 163 * 164 * We don't use the sprite, so we can ignore that. And on Crestline we have 165 * to set the non-SR watermarks to 8. 166 */ 167 static void intel_update_watermarks(struct drm_i915_private *dev_priv) 168 { 169 if (dev_priv->wm_disp->update_wm) 170 dev_priv->wm_disp->update_wm(dev_priv); 171 } 172 173 static int intel_compute_pipe_wm(struct intel_atomic_state *state, 174 struct intel_crtc *crtc) 175 { 176 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 177 if (dev_priv->wm_disp->compute_pipe_wm) 178 return dev_priv->wm_disp->compute_pipe_wm(state, crtc); 179 return 0; 180 } 181 182 static int intel_compute_intermediate_wm(struct intel_atomic_state *state, 183 struct intel_crtc *crtc) 184 { 185 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 186 if (!dev_priv->wm_disp->compute_intermediate_wm) 187 return 0; 188 if (drm_WARN_ON(&dev_priv->drm, 189 !dev_priv->wm_disp->compute_pipe_wm)) 190 return 0; 191 return dev_priv->wm_disp->compute_intermediate_wm(state, crtc); 192 } 193 194 static bool intel_initial_watermarks(struct intel_atomic_state *state, 195 struct intel_crtc *crtc) 196 { 197 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 198 if (dev_priv->wm_disp->initial_watermarks) { 199 dev_priv->wm_disp->initial_watermarks(state, crtc); 200 return true; 201 } 202 return false; 203 } 204 205 static void intel_atomic_update_watermarks(struct intel_atomic_state *state, 206 struct intel_crtc *crtc) 207 { 208 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 209 if (dev_priv->wm_disp->atomic_update_watermarks) 210 dev_priv->wm_disp->atomic_update_watermarks(state, crtc); 211 } 212 213 static void intel_optimize_watermarks(struct intel_atomic_state *state, 214 struct intel_crtc *crtc) 215 { 216 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 217 if (dev_priv->wm_disp->optimize_watermarks) 218 dev_priv->wm_disp->optimize_watermarks(state, crtc); 219 } 220 221 static int intel_compute_global_watermarks(struct intel_atomic_state *state) 222 { 223 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 224 if (dev_priv->wm_disp->compute_global_watermarks) 225 return dev_priv->wm_disp->compute_global_watermarks(state); 226 return 0; 227 } 228 229 /* returns HPLL frequency in kHz */ 230 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) 231 { 232 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; 233 234 /* Obtain SKU information */ 235 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & 236 CCK_FUSE_HPLL_FREQ_MASK; 237 238 return vco_freq[hpll_freq] * 1000; 239 } 240 241 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 242 const char *name, u32 reg, int ref_freq) 243 { 244 u32 val; 245 int divider; 246 247 val = vlv_cck_read(dev_priv, reg); 248 divider = val & CCK_FREQUENCY_VALUES; 249 250 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != 251 (divider << CCK_FREQUENCY_STATUS_SHIFT), 252 "%s change in progress\n", name); 253 254 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); 255 } 256 257 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 258 const char *name, u32 reg) 259 { 260 int hpll; 261 262 vlv_cck_get(dev_priv); 263 264 if (dev_priv->hpll_freq == 0) 265 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); 266 267 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); 268 269 vlv_cck_put(dev_priv); 270 271 return hpll; 272 } 273 274 static void intel_update_czclk(struct drm_i915_private *dev_priv) 275 { 276 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) 277 return; 278 279 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", 280 CCK_CZ_CLOCK_CONTROL); 281 282 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", 283 dev_priv->czclk_freq); 284 } 285 286 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state) 287 { 288 return (crtc_state->active_planes & 289 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0; 290 } 291 292 /* WA Display #0827: Gen9:all */ 293 static void 294 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) 295 { 296 if (enable) 297 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 298 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS); 299 else 300 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 301 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS)); 302 } 303 304 /* Wa_2006604312:icl,ehl */ 305 static void 306 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 307 bool enable) 308 { 309 if (enable) 310 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 311 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS); 312 else 313 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 314 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS); 315 } 316 317 /* Wa_1604331009:icl,jsl,ehl */ 318 static void 319 icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 320 bool enable) 321 { 322 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), CURSOR_GATING_DIS, 323 enable ? CURSOR_GATING_DIS : 0); 324 } 325 326 static bool 327 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state) 328 { 329 return crtc_state->master_transcoder != INVALID_TRANSCODER; 330 } 331 332 static bool 333 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state) 334 { 335 return crtc_state->sync_mode_slaves_mask != 0; 336 } 337 338 bool 339 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state) 340 { 341 return is_trans_port_sync_master(crtc_state) || 342 is_trans_port_sync_slave(crtc_state); 343 } 344 345 static enum pipe bigjoiner_master_pipe(const struct intel_crtc_state *crtc_state) 346 { 347 return ffs(crtc_state->bigjoiner_pipes) - 1; 348 } 349 350 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state) 351 { 352 if (crtc_state->bigjoiner_pipes) 353 return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state)); 354 else 355 return 0; 356 } 357 358 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state) 359 { 360 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 361 362 return crtc_state->bigjoiner_pipes && 363 crtc->pipe != bigjoiner_master_pipe(crtc_state); 364 } 365 366 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state) 367 { 368 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 369 370 return crtc_state->bigjoiner_pipes && 371 crtc->pipe == bigjoiner_master_pipe(crtc_state); 372 } 373 374 static int intel_bigjoiner_num_pipes(const struct intel_crtc_state *crtc_state) 375 { 376 return hweight8(crtc_state->bigjoiner_pipes); 377 } 378 379 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state) 380 { 381 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 382 383 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 384 return intel_crtc_for_pipe(i915, bigjoiner_master_pipe(crtc_state)); 385 else 386 return to_intel_crtc(crtc_state->uapi.crtc); 387 } 388 389 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv, 390 enum pipe pipe) 391 { 392 i915_reg_t reg = PIPEDSL(pipe); 393 u32 line1, line2; 394 395 line1 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK; 396 msleep(5); 397 line2 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK; 398 399 return line1 != line2; 400 } 401 402 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state) 403 { 404 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 405 enum pipe pipe = crtc->pipe; 406 407 /* Wait for the display line to settle/start moving */ 408 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100)) 409 drm_err(&dev_priv->drm, 410 "pipe %c scanline %s wait timed out\n", 411 pipe_name(pipe), str_on_off(state)); 412 } 413 414 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc) 415 { 416 wait_for_pipe_scanline_moving(crtc, false); 417 } 418 419 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc) 420 { 421 wait_for_pipe_scanline_moving(crtc, true); 422 } 423 424 static void 425 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) 426 { 427 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 428 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 429 430 if (DISPLAY_VER(dev_priv) >= 4) { 431 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 432 433 /* Wait for the Pipe State to go off */ 434 if (intel_de_wait_for_clear(dev_priv, PIPECONF(cpu_transcoder), 435 PIPECONF_STATE_ENABLE, 100)) 436 drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n"); 437 } else { 438 intel_wait_for_pipe_scanline_stopped(crtc); 439 } 440 } 441 442 void assert_transcoder(struct drm_i915_private *dev_priv, 443 enum transcoder cpu_transcoder, bool state) 444 { 445 bool cur_state; 446 enum intel_display_power_domain power_domain; 447 intel_wakeref_t wakeref; 448 449 /* we keep both pipes enabled on 830 */ 450 if (IS_I830(dev_priv)) 451 state = true; 452 453 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 454 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 455 if (wakeref) { 456 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); 457 cur_state = !!(val & PIPECONF_ENABLE); 458 459 intel_display_power_put(dev_priv, power_domain, wakeref); 460 } else { 461 cur_state = false; 462 } 463 464 I915_STATE_WARN(cur_state != state, 465 "transcoder %s assertion failure (expected %s, current %s)\n", 466 transcoder_name(cpu_transcoder), 467 str_on_off(state), str_on_off(cur_state)); 468 } 469 470 static void assert_plane(struct intel_plane *plane, bool state) 471 { 472 enum pipe pipe; 473 bool cur_state; 474 475 cur_state = plane->get_hw_state(plane, &pipe); 476 477 I915_STATE_WARN(cur_state != state, 478 "%s assertion failure (expected %s, current %s)\n", 479 plane->base.name, str_on_off(state), 480 str_on_off(cur_state)); 481 } 482 483 #define assert_plane_enabled(p) assert_plane(p, true) 484 #define assert_plane_disabled(p) assert_plane(p, false) 485 486 static void assert_planes_disabled(struct intel_crtc *crtc) 487 { 488 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 489 struct intel_plane *plane; 490 491 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) 492 assert_plane_disabled(plane); 493 } 494 495 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 496 struct intel_digital_port *dig_port, 497 unsigned int expected_mask) 498 { 499 u32 port_mask; 500 i915_reg_t dpll_reg; 501 502 switch (dig_port->base.port) { 503 case PORT_B: 504 port_mask = DPLL_PORTB_READY_MASK; 505 dpll_reg = DPLL(0); 506 break; 507 case PORT_C: 508 port_mask = DPLL_PORTC_READY_MASK; 509 dpll_reg = DPLL(0); 510 expected_mask <<= 4; 511 break; 512 case PORT_D: 513 port_mask = DPLL_PORTD_READY_MASK; 514 dpll_reg = DPIO_PHY_STATUS; 515 break; 516 default: 517 BUG(); 518 } 519 520 if (intel_de_wait_for_register(dev_priv, dpll_reg, 521 port_mask, expected_mask, 1000)) 522 drm_WARN(&dev_priv->drm, 1, 523 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", 524 dig_port->base.base.base.id, dig_port->base.base.name, 525 intel_de_read(dev_priv, dpll_reg) & port_mask, 526 expected_mask); 527 } 528 529 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) 530 { 531 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 532 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 533 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 534 enum pipe pipe = crtc->pipe; 535 i915_reg_t reg; 536 u32 val; 537 538 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe)); 539 540 assert_planes_disabled(crtc); 541 542 /* 543 * A pipe without a PLL won't actually be able to drive bits from 544 * a plane. On ILK+ the pipe PLLs are integrated, so we don't 545 * need the check. 546 */ 547 if (HAS_GMCH(dev_priv)) { 548 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI)) 549 assert_dsi_pll_enabled(dev_priv); 550 else 551 assert_pll_enabled(dev_priv, pipe); 552 } else { 553 if (new_crtc_state->has_pch_encoder) { 554 /* if driving the PCH, we need FDI enabled */ 555 assert_fdi_rx_pll_enabled(dev_priv, 556 intel_crtc_pch_transcoder(crtc)); 557 assert_fdi_tx_pll_enabled(dev_priv, 558 (enum pipe) cpu_transcoder); 559 } 560 /* FIXME: assert CPU port conditions for SNB+ */ 561 } 562 563 /* Wa_22012358565:adl-p */ 564 if (DISPLAY_VER(dev_priv) == 13) 565 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe), 566 0, PIPE_ARB_USE_PROG_SLOTS); 567 568 reg = PIPECONF(cpu_transcoder); 569 val = intel_de_read(dev_priv, reg); 570 if (val & PIPECONF_ENABLE) { 571 /* we keep both pipes enabled on 830 */ 572 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv)); 573 return; 574 } 575 576 intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE); 577 intel_de_posting_read(dev_priv, reg); 578 579 /* 580 * Until the pipe starts PIPEDSL reads will return a stale value, 581 * which causes an apparent vblank timestamp jump when PIPEDSL 582 * resets to its proper value. That also messes up the frame count 583 * when it's derived from the timestamps. So let's wait for the 584 * pipe to start properly before we call drm_crtc_vblank_on() 585 */ 586 if (intel_crtc_max_vblank_count(new_crtc_state) == 0) 587 intel_wait_for_pipe_scanline_moving(crtc); 588 } 589 590 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) 591 { 592 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 593 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 594 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 595 enum pipe pipe = crtc->pipe; 596 i915_reg_t reg; 597 u32 val; 598 599 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe)); 600 601 /* 602 * Make sure planes won't keep trying to pump pixels to us, 603 * or we might hang the display. 604 */ 605 assert_planes_disabled(crtc); 606 607 reg = PIPECONF(cpu_transcoder); 608 val = intel_de_read(dev_priv, reg); 609 if ((val & PIPECONF_ENABLE) == 0) 610 return; 611 612 /* 613 * Double wide has implications for planes 614 * so best keep it disabled when not needed. 615 */ 616 if (old_crtc_state->double_wide) 617 val &= ~PIPECONF_DOUBLE_WIDE; 618 619 /* Don't disable pipe or pipe PLLs if needed */ 620 if (!IS_I830(dev_priv)) 621 val &= ~PIPECONF_ENABLE; 622 623 if (DISPLAY_VER(dev_priv) >= 12) 624 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 625 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 626 627 intel_de_write(dev_priv, reg, val); 628 if ((val & PIPECONF_ENABLE) == 0) 629 intel_wait_for_pipe_off(old_crtc_state); 630 } 631 632 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) 633 { 634 unsigned int size = 0; 635 int i; 636 637 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) 638 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width; 639 640 return size; 641 } 642 643 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info) 644 { 645 unsigned int size = 0; 646 int i; 647 648 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) { 649 unsigned int plane_size; 650 651 if (rem_info->plane[i].linear) 652 plane_size = rem_info->plane[i].size; 653 else 654 plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height; 655 656 if (plane_size == 0) 657 continue; 658 659 if (rem_info->plane_alignment) 660 size = ALIGN(size, rem_info->plane_alignment); 661 662 size += plane_size; 663 } 664 665 return size; 666 } 667 668 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) 669 { 670 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 671 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 672 673 return DISPLAY_VER(dev_priv) < 4 || 674 (plane->fbc && 675 plane_state->view.gtt.type == I915_GGTT_VIEW_NORMAL); 676 } 677 678 /* 679 * Convert the x/y offsets into a linear offset. 680 * Only valid with 0/180 degree rotation, which is fine since linear 681 * offset is only used with linear buffers on pre-hsw and tiled buffers 682 * with gen2/3, and 90/270 degree rotations isn't supported on any of them. 683 */ 684 u32 intel_fb_xy_to_linear(int x, int y, 685 const struct intel_plane_state *state, 686 int color_plane) 687 { 688 const struct drm_framebuffer *fb = state->hw.fb; 689 unsigned int cpp = fb->format->cpp[color_plane]; 690 unsigned int pitch = state->view.color_plane[color_plane].mapping_stride; 691 692 return y * pitch + x * cpp; 693 } 694 695 /* 696 * Add the x/y offsets derived from fb->offsets[] to the user 697 * specified plane src x/y offsets. The resulting x/y offsets 698 * specify the start of scanout from the beginning of the gtt mapping. 699 */ 700 void intel_add_fb_offsets(int *x, int *y, 701 const struct intel_plane_state *state, 702 int color_plane) 703 704 { 705 *x += state->view.color_plane[color_plane].x; 706 *y += state->view.color_plane[color_plane].y; 707 } 708 709 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 710 u32 pixel_format, u64 modifier) 711 { 712 struct intel_crtc *crtc; 713 struct intel_plane *plane; 714 715 if (!HAS_DISPLAY(dev_priv)) 716 return 0; 717 718 /* 719 * We assume the primary plane for pipe A has 720 * the highest stride limits of them all, 721 * if in case pipe A is disabled, use the first pipe from pipe_mask. 722 */ 723 crtc = intel_first_crtc(dev_priv); 724 if (!crtc) 725 return 0; 726 727 plane = to_intel_plane(crtc->base.primary); 728 729 return plane->max_stride(plane, pixel_format, modifier, 730 DRM_MODE_ROTATE_0); 731 } 732 733 static void 734 intel_set_plane_visible(struct intel_crtc_state *crtc_state, 735 struct intel_plane_state *plane_state, 736 bool visible) 737 { 738 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 739 740 plane_state->uapi.visible = visible; 741 742 if (visible) 743 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base); 744 else 745 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base); 746 } 747 748 static void fixup_plane_bitmasks(struct intel_crtc_state *crtc_state) 749 { 750 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 751 struct drm_plane *plane; 752 753 /* 754 * Active_planes aliases if multiple "primary" or cursor planes 755 * have been used on the same (or wrong) pipe. plane_mask uses 756 * unique ids, hence we can use that to reconstruct active_planes. 757 */ 758 crtc_state->enabled_planes = 0; 759 crtc_state->active_planes = 0; 760 761 drm_for_each_plane_mask(plane, &dev_priv->drm, 762 crtc_state->uapi.plane_mask) { 763 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id); 764 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id); 765 } 766 } 767 768 void intel_plane_disable_noatomic(struct intel_crtc *crtc, 769 struct intel_plane *plane) 770 { 771 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 772 struct intel_crtc_state *crtc_state = 773 to_intel_crtc_state(crtc->base.state); 774 struct intel_plane_state *plane_state = 775 to_intel_plane_state(plane->base.state); 776 777 drm_dbg_kms(&dev_priv->drm, 778 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n", 779 plane->base.base.id, plane->base.name, 780 crtc->base.base.id, crtc->base.name); 781 782 intel_set_plane_visible(crtc_state, plane_state, false); 783 fixup_plane_bitmasks(crtc_state); 784 crtc_state->data_rate[plane->id] = 0; 785 crtc_state->data_rate_y[plane->id] = 0; 786 crtc_state->rel_data_rate[plane->id] = 0; 787 crtc_state->rel_data_rate_y[plane->id] = 0; 788 crtc_state->min_cdclk[plane->id] = 0; 789 790 if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 && 791 hsw_ips_disable(crtc_state)) { 792 crtc_state->ips_enabled = false; 793 intel_crtc_wait_for_next_vblank(crtc); 794 } 795 796 /* 797 * Vblank time updates from the shadow to live plane control register 798 * are blocked if the memory self-refresh mode is active at that 799 * moment. So to make sure the plane gets truly disabled, disable 800 * first the self-refresh mode. The self-refresh enable bit in turn 801 * will be checked/applied by the HW only at the next frame start 802 * event which is after the vblank start event, so we need to have a 803 * wait-for-vblank between disabling the plane and the pipe. 804 */ 805 if (HAS_GMCH(dev_priv) && 806 intel_set_memory_cxsr(dev_priv, false)) 807 intel_crtc_wait_for_next_vblank(crtc); 808 809 /* 810 * Gen2 reports pipe underruns whenever all planes are disabled. 811 * So disable underrun reporting before all the planes get disabled. 812 */ 813 if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes) 814 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); 815 816 intel_plane_disable_arm(plane, crtc_state); 817 intel_crtc_wait_for_next_vblank(crtc); 818 } 819 820 unsigned int 821 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state) 822 { 823 int x = 0, y = 0; 824 825 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, 826 plane_state->view.color_plane[0].offset, 0); 827 828 return y; 829 } 830 831 static int 832 __intel_display_resume(struct drm_device *dev, 833 struct drm_atomic_state *state, 834 struct drm_modeset_acquire_ctx *ctx) 835 { 836 struct drm_crtc_state *crtc_state; 837 struct drm_crtc *crtc; 838 int i, ret; 839 840 intel_modeset_setup_hw_state(dev, ctx); 841 intel_vga_redisable(to_i915(dev)); 842 843 if (!state) 844 return 0; 845 846 /* 847 * We've duplicated the state, pointers to the old state are invalid. 848 * 849 * Don't attempt to use the old state until we commit the duplicated state. 850 */ 851 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 852 /* 853 * Force recalculation even if we restore 854 * current state. With fast modeset this may not result 855 * in a modeset when the state is compatible. 856 */ 857 crtc_state->mode_changed = true; 858 } 859 860 /* ignore any reset values/BIOS leftovers in the WM registers */ 861 if (!HAS_GMCH(to_i915(dev))) 862 to_intel_atomic_state(state)->skip_intermediate_wm = true; 863 864 ret = drm_atomic_helper_commit_duplicated_state(state, ctx); 865 866 drm_WARN_ON(dev, ret == -EDEADLK); 867 return ret; 868 } 869 870 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) 871 { 872 return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display && 873 intel_has_gpu_reset(to_gt(dev_priv))); 874 } 875 876 void intel_display_prepare_reset(struct drm_i915_private *dev_priv) 877 { 878 struct drm_device *dev = &dev_priv->drm; 879 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; 880 struct drm_atomic_state *state; 881 int ret; 882 883 if (!HAS_DISPLAY(dev_priv)) 884 return; 885 886 /* reset doesn't touch the display */ 887 if (!dev_priv->params.force_reset_modeset_test && 888 !gpu_reset_clobbers_display(dev_priv)) 889 return; 890 891 /* We have a modeset vs reset deadlock, defensively unbreak it. */ 892 set_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags); 893 smp_mb__after_atomic(); 894 wake_up_bit(&to_gt(dev_priv)->reset.flags, I915_RESET_MODESET); 895 896 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) { 897 drm_dbg_kms(&dev_priv->drm, 898 "Modeset potentially stuck, unbreaking through wedging\n"); 899 intel_gt_set_wedged(to_gt(dev_priv)); 900 } 901 902 /* 903 * Need mode_config.mutex so that we don't 904 * trample ongoing ->detect() and whatnot. 905 */ 906 mutex_lock(&dev->mode_config.mutex); 907 drm_modeset_acquire_init(ctx, 0); 908 while (1) { 909 ret = drm_modeset_lock_all_ctx(dev, ctx); 910 if (ret != -EDEADLK) 911 break; 912 913 drm_modeset_backoff(ctx); 914 } 915 /* 916 * Disabling the crtcs gracefully seems nicer. Also the 917 * g33 docs say we should at least disable all the planes. 918 */ 919 state = drm_atomic_helper_duplicate_state(dev, ctx); 920 if (IS_ERR(state)) { 921 ret = PTR_ERR(state); 922 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n", 923 ret); 924 return; 925 } 926 927 ret = drm_atomic_helper_disable_all(dev, ctx); 928 if (ret) { 929 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", 930 ret); 931 drm_atomic_state_put(state); 932 return; 933 } 934 935 dev_priv->modeset_restore_state = state; 936 state->acquire_ctx = ctx; 937 } 938 939 void intel_display_finish_reset(struct drm_i915_private *dev_priv) 940 { 941 struct drm_device *dev = &dev_priv->drm; 942 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; 943 struct drm_atomic_state *state; 944 int ret; 945 946 if (!HAS_DISPLAY(dev_priv)) 947 return; 948 949 /* reset doesn't touch the display */ 950 if (!test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags)) 951 return; 952 953 state = fetch_and_zero(&dev_priv->modeset_restore_state); 954 if (!state) 955 goto unlock; 956 957 /* reset doesn't touch the display */ 958 if (!gpu_reset_clobbers_display(dev_priv)) { 959 /* for testing only restore the display */ 960 ret = __intel_display_resume(dev, state, ctx); 961 if (ret) 962 drm_err(&dev_priv->drm, 963 "Restoring old state failed with %i\n", ret); 964 } else { 965 /* 966 * The display has been reset as well, 967 * so need a full re-initialization. 968 */ 969 intel_pps_unlock_regs_wa(dev_priv); 970 intel_modeset_init_hw(dev_priv); 971 intel_init_clock_gating(dev_priv); 972 intel_hpd_init(dev_priv); 973 974 ret = __intel_display_resume(dev, state, ctx); 975 if (ret) 976 drm_err(&dev_priv->drm, 977 "Restoring old state failed with %i\n", ret); 978 979 intel_hpd_poll_disable(dev_priv); 980 } 981 982 drm_atomic_state_put(state); 983 unlock: 984 drm_modeset_drop_locks(ctx); 985 drm_modeset_acquire_fini(ctx); 986 mutex_unlock(&dev->mode_config.mutex); 987 988 clear_bit_unlock(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags); 989 } 990 991 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) 992 { 993 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 994 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 995 enum pipe pipe = crtc->pipe; 996 u32 tmp; 997 998 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe)); 999 1000 /* 1001 * Display WA #1153: icl 1002 * enable hardware to bypass the alpha math 1003 * and rounding for per-pixel values 00 and 0xff 1004 */ 1005 tmp |= PER_PIXEL_ALPHA_BYPASS_EN; 1006 /* 1007 * Display WA # 1605353570: icl 1008 * Set the pixel rounding bit to 1 for allowing 1009 * passthrough of Frame buffer pixels unmodified 1010 * across pipe 1011 */ 1012 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU; 1013 1014 /* 1015 * Underrun recovery must always be disabled on display 13+. 1016 * DG2 chicken bit meaning is inverted compared to other platforms. 1017 */ 1018 if (IS_DG2(dev_priv)) 1019 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2; 1020 else if (DISPLAY_VER(dev_priv) >= 13) 1021 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP; 1022 1023 /* Wa_14010547955:dg2 */ 1024 if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER)) 1025 tmp |= DG2_RENDER_CCSTAG_4_3_EN; 1026 1027 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp); 1028 } 1029 1030 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) 1031 { 1032 struct drm_crtc *crtc; 1033 bool cleanup_done; 1034 1035 drm_for_each_crtc(crtc, &dev_priv->drm) { 1036 struct drm_crtc_commit *commit; 1037 spin_lock(&crtc->commit_lock); 1038 commit = list_first_entry_or_null(&crtc->commit_list, 1039 struct drm_crtc_commit, commit_entry); 1040 cleanup_done = commit ? 1041 try_wait_for_completion(&commit->cleanup_done) : true; 1042 spin_unlock(&crtc->commit_lock); 1043 1044 if (cleanup_done) 1045 continue; 1046 1047 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc)); 1048 1049 return true; 1050 } 1051 1052 return false; 1053 } 1054 1055 /* 1056 * Finds the encoder associated with the given CRTC. This can only be 1057 * used when we know that the CRTC isn't feeding multiple encoders! 1058 */ 1059 struct intel_encoder * 1060 intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 1061 const struct intel_crtc_state *crtc_state) 1062 { 1063 const struct drm_connector_state *connector_state; 1064 const struct drm_connector *connector; 1065 struct intel_encoder *encoder = NULL; 1066 struct intel_crtc *master_crtc; 1067 int num_encoders = 0; 1068 int i; 1069 1070 master_crtc = intel_master_crtc(crtc_state); 1071 1072 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 1073 if (connector_state->crtc != &master_crtc->base) 1074 continue; 1075 1076 encoder = to_intel_encoder(connector_state->best_encoder); 1077 num_encoders++; 1078 } 1079 1080 drm_WARN(encoder->base.dev, num_encoders != 1, 1081 "%d encoders for pipe %c\n", 1082 num_encoders, pipe_name(master_crtc->pipe)); 1083 1084 return encoder; 1085 } 1086 1087 static void cpt_verify_modeset(struct drm_i915_private *dev_priv, 1088 enum pipe pipe) 1089 { 1090 i915_reg_t dslreg = PIPEDSL(pipe); 1091 u32 temp; 1092 1093 temp = intel_de_read(dev_priv, dslreg); 1094 udelay(500); 1095 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) { 1096 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) 1097 drm_err(&dev_priv->drm, 1098 "mode set failed: pipe %c stuck\n", 1099 pipe_name(pipe)); 1100 } 1101 } 1102 1103 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state) 1104 { 1105 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1106 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1107 const struct drm_rect *dst = &crtc_state->pch_pfit.dst; 1108 enum pipe pipe = crtc->pipe; 1109 int width = drm_rect_width(dst); 1110 int height = drm_rect_height(dst); 1111 int x = dst->x1; 1112 int y = dst->y1; 1113 1114 if (!crtc_state->pch_pfit.enabled) 1115 return; 1116 1117 /* Force use of hard-coded filter coefficients 1118 * as some pre-programmed values are broken, 1119 * e.g. x201. 1120 */ 1121 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) 1122 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 1123 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe)); 1124 else 1125 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 1126 PF_FILTER_MED_3x3); 1127 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), x << 16 | y); 1128 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), width << 16 | height); 1129 } 1130 1131 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc) 1132 { 1133 if (crtc->overlay) 1134 (void) intel_overlay_switch_off(crtc->overlay); 1135 1136 /* Let userspace switch the overlay on again. In most cases userspace 1137 * has to recompute where to put it anyway. 1138 */ 1139 } 1140 1141 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state) 1142 { 1143 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1144 1145 if (!crtc_state->nv12_planes) 1146 return false; 1147 1148 /* WA Display #0827: Gen9:all */ 1149 if (DISPLAY_VER(dev_priv) == 9) 1150 return true; 1151 1152 return false; 1153 } 1154 1155 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state) 1156 { 1157 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1158 1159 /* Wa_2006604312:icl,ehl */ 1160 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11) 1161 return true; 1162 1163 return false; 1164 } 1165 1166 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state) 1167 { 1168 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1169 1170 /* Wa_1604331009:icl,jsl,ehl */ 1171 if (is_hdr_mode(crtc_state) && 1172 crtc_state->active_planes & BIT(PLANE_CURSOR) && 1173 DISPLAY_VER(dev_priv) == 11) 1174 return true; 1175 1176 return false; 1177 } 1178 1179 static void intel_async_flip_vtd_wa(struct drm_i915_private *i915, 1180 enum pipe pipe, bool enable) 1181 { 1182 if (DISPLAY_VER(i915) == 9) { 1183 /* 1184 * "Plane N strech max must be programmed to 11b (x1) 1185 * when Async flips are enabled on that plane." 1186 */ 1187 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 1188 SKL_PLANE1_STRETCH_MAX_MASK, 1189 enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8); 1190 } else { 1191 /* Also needed on HSW/BDW albeit undocumented */ 1192 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 1193 HSW_PRI_STRETCH_MAX_MASK, 1194 enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8); 1195 } 1196 } 1197 1198 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state) 1199 { 1200 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1201 1202 return crtc_state->uapi.async_flip && i915_vtd_active(i915) && 1203 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915)); 1204 } 1205 1206 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state, 1207 const struct intel_crtc_state *new_crtc_state) 1208 { 1209 return (!old_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)) && 1210 new_crtc_state->active_planes; 1211 } 1212 1213 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state, 1214 const struct intel_crtc_state *new_crtc_state) 1215 { 1216 return old_crtc_state->active_planes && 1217 (!new_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)); 1218 } 1219 1220 static void intel_post_plane_update(struct intel_atomic_state *state, 1221 struct intel_crtc *crtc) 1222 { 1223 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1224 const struct intel_crtc_state *old_crtc_state = 1225 intel_atomic_get_old_crtc_state(state, crtc); 1226 const struct intel_crtc_state *new_crtc_state = 1227 intel_atomic_get_new_crtc_state(state, crtc); 1228 enum pipe pipe = crtc->pipe; 1229 1230 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); 1231 1232 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) 1233 intel_update_watermarks(dev_priv); 1234 1235 hsw_ips_post_update(state, crtc); 1236 intel_fbc_post_update(state, crtc); 1237 1238 if (needs_async_flip_vtd_wa(old_crtc_state) && 1239 !needs_async_flip_vtd_wa(new_crtc_state)) 1240 intel_async_flip_vtd_wa(dev_priv, pipe, false); 1241 1242 if (needs_nv12_wa(old_crtc_state) && 1243 !needs_nv12_wa(new_crtc_state)) 1244 skl_wa_827(dev_priv, pipe, false); 1245 1246 if (needs_scalerclk_wa(old_crtc_state) && 1247 !needs_scalerclk_wa(new_crtc_state)) 1248 icl_wa_scalerclkgating(dev_priv, pipe, false); 1249 1250 if (needs_cursorclk_wa(old_crtc_state) && 1251 !needs_cursorclk_wa(new_crtc_state)) 1252 icl_wa_cursorclkgating(dev_priv, pipe, false); 1253 1254 intel_drrs_activate(new_crtc_state); 1255 } 1256 1257 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state, 1258 struct intel_crtc *crtc) 1259 { 1260 const struct intel_crtc_state *crtc_state = 1261 intel_atomic_get_new_crtc_state(state, crtc); 1262 u8 update_planes = crtc_state->update_planes; 1263 const struct intel_plane_state *plane_state; 1264 struct intel_plane *plane; 1265 int i; 1266 1267 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1268 if (plane->pipe == crtc->pipe && 1269 update_planes & BIT(plane->id)) 1270 plane->enable_flip_done(plane); 1271 } 1272 } 1273 1274 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state, 1275 struct intel_crtc *crtc) 1276 { 1277 const struct intel_crtc_state *crtc_state = 1278 intel_atomic_get_new_crtc_state(state, crtc); 1279 u8 update_planes = crtc_state->update_planes; 1280 const struct intel_plane_state *plane_state; 1281 struct intel_plane *plane; 1282 int i; 1283 1284 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1285 if (plane->pipe == crtc->pipe && 1286 update_planes & BIT(plane->id)) 1287 plane->disable_flip_done(plane); 1288 } 1289 } 1290 1291 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state, 1292 struct intel_crtc *crtc) 1293 { 1294 const struct intel_crtc_state *old_crtc_state = 1295 intel_atomic_get_old_crtc_state(state, crtc); 1296 const struct intel_crtc_state *new_crtc_state = 1297 intel_atomic_get_new_crtc_state(state, crtc); 1298 u8 update_planes = new_crtc_state->update_planes; 1299 const struct intel_plane_state *old_plane_state; 1300 struct intel_plane *plane; 1301 bool need_vbl_wait = false; 1302 int i; 1303 1304 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1305 if (plane->need_async_flip_disable_wa && 1306 plane->pipe == crtc->pipe && 1307 update_planes & BIT(plane->id)) { 1308 /* 1309 * Apart from the async flip bit we want to 1310 * preserve the old state for the plane. 1311 */ 1312 plane->async_flip(plane, old_crtc_state, 1313 old_plane_state, false); 1314 need_vbl_wait = true; 1315 } 1316 } 1317 1318 if (need_vbl_wait) 1319 intel_crtc_wait_for_next_vblank(crtc); 1320 } 1321 1322 static void intel_pre_plane_update(struct intel_atomic_state *state, 1323 struct intel_crtc *crtc) 1324 { 1325 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1326 const struct intel_crtc_state *old_crtc_state = 1327 intel_atomic_get_old_crtc_state(state, crtc); 1328 const struct intel_crtc_state *new_crtc_state = 1329 intel_atomic_get_new_crtc_state(state, crtc); 1330 enum pipe pipe = crtc->pipe; 1331 1332 intel_drrs_deactivate(old_crtc_state); 1333 1334 intel_psr_pre_plane_update(state, crtc); 1335 1336 if (hsw_ips_pre_update(state, crtc)) 1337 intel_crtc_wait_for_next_vblank(crtc); 1338 1339 if (intel_fbc_pre_update(state, crtc)) 1340 intel_crtc_wait_for_next_vblank(crtc); 1341 1342 if (!needs_async_flip_vtd_wa(old_crtc_state) && 1343 needs_async_flip_vtd_wa(new_crtc_state)) 1344 intel_async_flip_vtd_wa(dev_priv, pipe, true); 1345 1346 /* Display WA 827 */ 1347 if (!needs_nv12_wa(old_crtc_state) && 1348 needs_nv12_wa(new_crtc_state)) 1349 skl_wa_827(dev_priv, pipe, true); 1350 1351 /* Wa_2006604312:icl,ehl */ 1352 if (!needs_scalerclk_wa(old_crtc_state) && 1353 needs_scalerclk_wa(new_crtc_state)) 1354 icl_wa_scalerclkgating(dev_priv, pipe, true); 1355 1356 /* Wa_1604331009:icl,jsl,ehl */ 1357 if (!needs_cursorclk_wa(old_crtc_state) && 1358 needs_cursorclk_wa(new_crtc_state)) 1359 icl_wa_cursorclkgating(dev_priv, pipe, true); 1360 1361 /* 1362 * Vblank time updates from the shadow to live plane control register 1363 * are blocked if the memory self-refresh mode is active at that 1364 * moment. So to make sure the plane gets truly disabled, disable 1365 * first the self-refresh mode. The self-refresh enable bit in turn 1366 * will be checked/applied by the HW only at the next frame start 1367 * event which is after the vblank start event, so we need to have a 1368 * wait-for-vblank between disabling the plane and the pipe. 1369 */ 1370 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active && 1371 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) 1372 intel_crtc_wait_for_next_vblank(crtc); 1373 1374 /* 1375 * IVB workaround: must disable low power watermarks for at least 1376 * one frame before enabling scaling. LP watermarks can be re-enabled 1377 * when scaling is disabled. 1378 * 1379 * WaCxSRDisabledForSpriteScaling:ivb 1380 */ 1381 if (old_crtc_state->hw.active && 1382 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv)) 1383 intel_crtc_wait_for_next_vblank(crtc); 1384 1385 /* 1386 * If we're doing a modeset we don't need to do any 1387 * pre-vblank watermark programming here. 1388 */ 1389 if (!intel_crtc_needs_modeset(new_crtc_state)) { 1390 /* 1391 * For platforms that support atomic watermarks, program the 1392 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these 1393 * will be the intermediate values that are safe for both pre- and 1394 * post- vblank; when vblank happens, the 'active' values will be set 1395 * to the final 'target' values and we'll do this again to get the 1396 * optimal watermarks. For gen9+ platforms, the values we program here 1397 * will be the final target values which will get automatically latched 1398 * at vblank time; no further programming will be necessary. 1399 * 1400 * If a platform hasn't been transitioned to atomic watermarks yet, 1401 * we'll continue to update watermarks the old way, if flags tell 1402 * us to. 1403 */ 1404 if (!intel_initial_watermarks(state, crtc)) 1405 if (new_crtc_state->update_wm_pre) 1406 intel_update_watermarks(dev_priv); 1407 } 1408 1409 /* 1410 * Gen2 reports pipe underruns whenever all planes are disabled. 1411 * So disable underrun reporting before all the planes get disabled. 1412 * 1413 * We do this after .initial_watermarks() so that we have a 1414 * chance of catching underruns with the intermediate watermarks 1415 * vs. the old plane configuration. 1416 */ 1417 if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state)) 1418 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1419 1420 /* 1421 * WA for platforms where async address update enable bit 1422 * is double buffered and only latched at start of vblank. 1423 */ 1424 if (old_crtc_state->uapi.async_flip && !new_crtc_state->uapi.async_flip) 1425 intel_crtc_async_flip_disable_wa(state, crtc); 1426 } 1427 1428 static void intel_crtc_disable_planes(struct intel_atomic_state *state, 1429 struct intel_crtc *crtc) 1430 { 1431 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1432 const struct intel_crtc_state *new_crtc_state = 1433 intel_atomic_get_new_crtc_state(state, crtc); 1434 unsigned int update_mask = new_crtc_state->update_planes; 1435 const struct intel_plane_state *old_plane_state; 1436 struct intel_plane *plane; 1437 unsigned fb_bits = 0; 1438 int i; 1439 1440 intel_crtc_dpms_overlay_disable(crtc); 1441 1442 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1443 if (crtc->pipe != plane->pipe || 1444 !(update_mask & BIT(plane->id))) 1445 continue; 1446 1447 intel_plane_disable_arm(plane, new_crtc_state); 1448 1449 if (old_plane_state->uapi.visible) 1450 fb_bits |= plane->frontbuffer_bit; 1451 } 1452 1453 intel_frontbuffer_flip(dev_priv, fb_bits); 1454 } 1455 1456 /* 1457 * intel_connector_primary_encoder - get the primary encoder for a connector 1458 * @connector: connector for which to return the encoder 1459 * 1460 * Returns the primary encoder for a connector. There is a 1:1 mapping from 1461 * all connectors to their encoder, except for DP-MST connectors which have 1462 * both a virtual and a primary encoder. These DP-MST primary encoders can be 1463 * pointed to by as many DP-MST connectors as there are pipes. 1464 */ 1465 static struct intel_encoder * 1466 intel_connector_primary_encoder(struct intel_connector *connector) 1467 { 1468 struct intel_encoder *encoder; 1469 1470 if (connector->mst_port) 1471 return &dp_to_dig_port(connector->mst_port)->base; 1472 1473 encoder = intel_attached_encoder(connector); 1474 drm_WARN_ON(connector->base.dev, !encoder); 1475 1476 return encoder; 1477 } 1478 1479 static void intel_encoders_update_prepare(struct intel_atomic_state *state) 1480 { 1481 struct drm_i915_private *i915 = to_i915(state->base.dev); 1482 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 1483 struct intel_crtc *crtc; 1484 struct drm_connector_state *new_conn_state; 1485 struct drm_connector *connector; 1486 int i; 1487 1488 /* 1489 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits. 1490 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook. 1491 */ 1492 if (i915->dpll.mgr) { 1493 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1494 if (intel_crtc_needs_modeset(new_crtc_state)) 1495 continue; 1496 1497 new_crtc_state->shared_dpll = old_crtc_state->shared_dpll; 1498 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state; 1499 } 1500 } 1501 1502 if (!state->modeset) 1503 return; 1504 1505 for_each_new_connector_in_state(&state->base, connector, new_conn_state, 1506 i) { 1507 struct intel_connector *intel_connector; 1508 struct intel_encoder *encoder; 1509 struct intel_crtc *crtc; 1510 1511 if (!intel_connector_needs_modeset(state, connector)) 1512 continue; 1513 1514 intel_connector = to_intel_connector(connector); 1515 encoder = intel_connector_primary_encoder(intel_connector); 1516 if (!encoder->update_prepare) 1517 continue; 1518 1519 crtc = new_conn_state->crtc ? 1520 to_intel_crtc(new_conn_state->crtc) : NULL; 1521 encoder->update_prepare(state, encoder, crtc); 1522 } 1523 } 1524 1525 static void intel_encoders_update_complete(struct intel_atomic_state *state) 1526 { 1527 struct drm_connector_state *new_conn_state; 1528 struct drm_connector *connector; 1529 int i; 1530 1531 if (!state->modeset) 1532 return; 1533 1534 for_each_new_connector_in_state(&state->base, connector, new_conn_state, 1535 i) { 1536 struct intel_connector *intel_connector; 1537 struct intel_encoder *encoder; 1538 struct intel_crtc *crtc; 1539 1540 if (!intel_connector_needs_modeset(state, connector)) 1541 continue; 1542 1543 intel_connector = to_intel_connector(connector); 1544 encoder = intel_connector_primary_encoder(intel_connector); 1545 if (!encoder->update_complete) 1546 continue; 1547 1548 crtc = new_conn_state->crtc ? 1549 to_intel_crtc(new_conn_state->crtc) : NULL; 1550 encoder->update_complete(state, encoder, crtc); 1551 } 1552 } 1553 1554 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state, 1555 struct intel_crtc *crtc) 1556 { 1557 const struct intel_crtc_state *crtc_state = 1558 intel_atomic_get_new_crtc_state(state, crtc); 1559 const struct drm_connector_state *conn_state; 1560 struct drm_connector *conn; 1561 int i; 1562 1563 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1564 struct intel_encoder *encoder = 1565 to_intel_encoder(conn_state->best_encoder); 1566 1567 if (conn_state->crtc != &crtc->base) 1568 continue; 1569 1570 if (encoder->pre_pll_enable) 1571 encoder->pre_pll_enable(state, encoder, 1572 crtc_state, conn_state); 1573 } 1574 } 1575 1576 static void intel_encoders_pre_enable(struct intel_atomic_state *state, 1577 struct intel_crtc *crtc) 1578 { 1579 const struct intel_crtc_state *crtc_state = 1580 intel_atomic_get_new_crtc_state(state, crtc); 1581 const struct drm_connector_state *conn_state; 1582 struct drm_connector *conn; 1583 int i; 1584 1585 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1586 struct intel_encoder *encoder = 1587 to_intel_encoder(conn_state->best_encoder); 1588 1589 if (conn_state->crtc != &crtc->base) 1590 continue; 1591 1592 if (encoder->pre_enable) 1593 encoder->pre_enable(state, encoder, 1594 crtc_state, conn_state); 1595 } 1596 } 1597 1598 static void intel_encoders_enable(struct intel_atomic_state *state, 1599 struct intel_crtc *crtc) 1600 { 1601 const struct intel_crtc_state *crtc_state = 1602 intel_atomic_get_new_crtc_state(state, crtc); 1603 const struct drm_connector_state *conn_state; 1604 struct drm_connector *conn; 1605 int i; 1606 1607 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1608 struct intel_encoder *encoder = 1609 to_intel_encoder(conn_state->best_encoder); 1610 1611 if (conn_state->crtc != &crtc->base) 1612 continue; 1613 1614 if (encoder->enable) 1615 encoder->enable(state, encoder, 1616 crtc_state, conn_state); 1617 intel_opregion_notify_encoder(encoder, true); 1618 } 1619 } 1620 1621 static void intel_encoders_disable(struct intel_atomic_state *state, 1622 struct intel_crtc *crtc) 1623 { 1624 const struct intel_crtc_state *old_crtc_state = 1625 intel_atomic_get_old_crtc_state(state, crtc); 1626 const struct drm_connector_state *old_conn_state; 1627 struct drm_connector *conn; 1628 int i; 1629 1630 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1631 struct intel_encoder *encoder = 1632 to_intel_encoder(old_conn_state->best_encoder); 1633 1634 if (old_conn_state->crtc != &crtc->base) 1635 continue; 1636 1637 intel_opregion_notify_encoder(encoder, false); 1638 if (encoder->disable) 1639 encoder->disable(state, encoder, 1640 old_crtc_state, old_conn_state); 1641 } 1642 } 1643 1644 static void intel_encoders_post_disable(struct intel_atomic_state *state, 1645 struct intel_crtc *crtc) 1646 { 1647 const struct intel_crtc_state *old_crtc_state = 1648 intel_atomic_get_old_crtc_state(state, crtc); 1649 const struct drm_connector_state *old_conn_state; 1650 struct drm_connector *conn; 1651 int i; 1652 1653 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1654 struct intel_encoder *encoder = 1655 to_intel_encoder(old_conn_state->best_encoder); 1656 1657 if (old_conn_state->crtc != &crtc->base) 1658 continue; 1659 1660 if (encoder->post_disable) 1661 encoder->post_disable(state, encoder, 1662 old_crtc_state, old_conn_state); 1663 } 1664 } 1665 1666 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state, 1667 struct intel_crtc *crtc) 1668 { 1669 const struct intel_crtc_state *old_crtc_state = 1670 intel_atomic_get_old_crtc_state(state, crtc); 1671 const struct drm_connector_state *old_conn_state; 1672 struct drm_connector *conn; 1673 int i; 1674 1675 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1676 struct intel_encoder *encoder = 1677 to_intel_encoder(old_conn_state->best_encoder); 1678 1679 if (old_conn_state->crtc != &crtc->base) 1680 continue; 1681 1682 if (encoder->post_pll_disable) 1683 encoder->post_pll_disable(state, encoder, 1684 old_crtc_state, old_conn_state); 1685 } 1686 } 1687 1688 static void intel_encoders_update_pipe(struct intel_atomic_state *state, 1689 struct intel_crtc *crtc) 1690 { 1691 const struct intel_crtc_state *crtc_state = 1692 intel_atomic_get_new_crtc_state(state, crtc); 1693 const struct drm_connector_state *conn_state; 1694 struct drm_connector *conn; 1695 int i; 1696 1697 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1698 struct intel_encoder *encoder = 1699 to_intel_encoder(conn_state->best_encoder); 1700 1701 if (conn_state->crtc != &crtc->base) 1702 continue; 1703 1704 if (encoder->update_pipe) 1705 encoder->update_pipe(state, encoder, 1706 crtc_state, conn_state); 1707 } 1708 } 1709 1710 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state) 1711 { 1712 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1713 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 1714 1715 plane->disable_arm(plane, crtc_state); 1716 } 1717 1718 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1719 { 1720 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1721 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1722 1723 if (crtc_state->has_pch_encoder) { 1724 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1725 &crtc_state->fdi_m_n); 1726 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1727 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1728 &crtc_state->dp_m_n); 1729 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1730 &crtc_state->dp_m2_n2); 1731 } 1732 1733 intel_set_transcoder_timings(crtc_state); 1734 1735 ilk_set_pipeconf(crtc_state); 1736 } 1737 1738 static void ilk_crtc_enable(struct intel_atomic_state *state, 1739 struct intel_crtc *crtc) 1740 { 1741 const struct intel_crtc_state *new_crtc_state = 1742 intel_atomic_get_new_crtc_state(state, crtc); 1743 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1744 enum pipe pipe = crtc->pipe; 1745 1746 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1747 return; 1748 1749 /* 1750 * Sometimes spurious CPU pipe underruns happen during FDI 1751 * training, at least with VGA+HDMI cloning. Suppress them. 1752 * 1753 * On ILK we get an occasional spurious CPU pipe underruns 1754 * between eDP port A enable and vdd enable. Also PCH port 1755 * enable seems to result in the occasional CPU pipe underrun. 1756 * 1757 * Spurious PCH underruns also occur during PCH enabling. 1758 */ 1759 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1760 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 1761 1762 ilk_configure_cpu_transcoder(new_crtc_state); 1763 1764 intel_set_pipe_src_size(new_crtc_state); 1765 1766 crtc->active = true; 1767 1768 intel_encoders_pre_enable(state, crtc); 1769 1770 if (new_crtc_state->has_pch_encoder) { 1771 ilk_pch_pre_enable(state, crtc); 1772 } else { 1773 assert_fdi_tx_disabled(dev_priv, pipe); 1774 assert_fdi_rx_disabled(dev_priv, pipe); 1775 } 1776 1777 ilk_pfit_enable(new_crtc_state); 1778 1779 /* 1780 * On ILK+ LUT must be loaded before the pipe is running but with 1781 * clocks enabled 1782 */ 1783 intel_color_load_luts(new_crtc_state); 1784 intel_color_commit_noarm(new_crtc_state); 1785 intel_color_commit_arm(new_crtc_state); 1786 /* update DSPCNTR to configure gamma for pipe bottom color */ 1787 intel_disable_primary_plane(new_crtc_state); 1788 1789 intel_initial_watermarks(state, crtc); 1790 intel_enable_transcoder(new_crtc_state); 1791 1792 if (new_crtc_state->has_pch_encoder) 1793 ilk_pch_enable(state, crtc); 1794 1795 intel_crtc_vblank_on(new_crtc_state); 1796 1797 intel_encoders_enable(state, crtc); 1798 1799 if (HAS_PCH_CPT(dev_priv)) 1800 cpt_verify_modeset(dev_priv, pipe); 1801 1802 /* 1803 * Must wait for vblank to avoid spurious PCH FIFO underruns. 1804 * And a second vblank wait is needed at least on ILK with 1805 * some interlaced HDMI modes. Let's do the double wait always 1806 * in case there are more corner cases we don't know about. 1807 */ 1808 if (new_crtc_state->has_pch_encoder) { 1809 intel_crtc_wait_for_next_vblank(crtc); 1810 intel_crtc_wait_for_next_vblank(crtc); 1811 } 1812 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1813 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 1814 } 1815 1816 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, 1817 enum pipe pipe, bool apply) 1818 { 1819 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)); 1820 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS; 1821 1822 if (apply) 1823 val |= mask; 1824 else 1825 val &= ~mask; 1826 1827 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val); 1828 } 1829 1830 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state) 1831 { 1832 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1833 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1834 1835 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe), 1836 HSW_LINETIME(crtc_state->linetime) | 1837 HSW_IPS_LINETIME(crtc_state->ips_linetime)); 1838 } 1839 1840 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) 1841 { 1842 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1843 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1844 i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder); 1845 u32 val; 1846 1847 val = intel_de_read(dev_priv, reg); 1848 val &= ~HSW_FRAME_START_DELAY_MASK; 1849 val |= HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 1850 intel_de_write(dev_priv, reg, val); 1851 } 1852 1853 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state, 1854 const struct intel_crtc_state *crtc_state) 1855 { 1856 struct intel_crtc *master_crtc = intel_master_crtc(crtc_state); 1857 1858 /* 1859 * Enable sequence steps 1-7 on bigjoiner master 1860 */ 1861 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1862 intel_encoders_pre_pll_enable(state, master_crtc); 1863 1864 if (crtc_state->shared_dpll) 1865 intel_enable_shared_dpll(crtc_state); 1866 1867 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1868 intel_encoders_pre_enable(state, master_crtc); 1869 } 1870 1871 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1872 { 1873 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1874 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1875 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1876 1877 if (crtc_state->has_pch_encoder) { 1878 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1879 &crtc_state->fdi_m_n); 1880 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1881 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1882 &crtc_state->dp_m_n); 1883 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1884 &crtc_state->dp_m2_n2); 1885 } 1886 1887 intel_set_transcoder_timings(crtc_state); 1888 1889 if (cpu_transcoder != TRANSCODER_EDP) 1890 intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder), 1891 crtc_state->pixel_multiplier - 1); 1892 1893 hsw_set_frame_start_delay(crtc_state); 1894 1895 hsw_set_transconf(crtc_state); 1896 } 1897 1898 static void hsw_crtc_enable(struct intel_atomic_state *state, 1899 struct intel_crtc *crtc) 1900 { 1901 const struct intel_crtc_state *new_crtc_state = 1902 intel_atomic_get_new_crtc_state(state, crtc); 1903 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1904 enum pipe pipe = crtc->pipe, hsw_workaround_pipe; 1905 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 1906 bool psl_clkgate_wa; 1907 1908 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1909 return; 1910 1911 if (!new_crtc_state->bigjoiner_pipes) { 1912 intel_encoders_pre_pll_enable(state, crtc); 1913 1914 if (new_crtc_state->shared_dpll) 1915 intel_enable_shared_dpll(new_crtc_state); 1916 1917 intel_encoders_pre_enable(state, crtc); 1918 } else { 1919 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state); 1920 } 1921 1922 intel_dsc_enable(new_crtc_state); 1923 1924 if (DISPLAY_VER(dev_priv) >= 13) 1925 intel_uncompressed_joiner_enable(new_crtc_state); 1926 1927 intel_set_pipe_src_size(new_crtc_state); 1928 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 1929 bdw_set_pipemisc(new_crtc_state); 1930 1931 if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) && 1932 !transcoder_is_dsi(cpu_transcoder)) 1933 hsw_configure_cpu_transcoder(new_crtc_state); 1934 1935 crtc->active = true; 1936 1937 /* Display WA #1180: WaDisableScalarClockGating: glk */ 1938 psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 && 1939 new_crtc_state->pch_pfit.enabled; 1940 if (psl_clkgate_wa) 1941 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true); 1942 1943 if (DISPLAY_VER(dev_priv) >= 9) 1944 skl_pfit_enable(new_crtc_state); 1945 else 1946 ilk_pfit_enable(new_crtc_state); 1947 1948 /* 1949 * On ILK+ LUT must be loaded before the pipe is running but with 1950 * clocks enabled 1951 */ 1952 intel_color_load_luts(new_crtc_state); 1953 intel_color_commit_noarm(new_crtc_state); 1954 intel_color_commit_arm(new_crtc_state); 1955 /* update DSPCNTR to configure gamma/csc for pipe bottom color */ 1956 if (DISPLAY_VER(dev_priv) < 9) 1957 intel_disable_primary_plane(new_crtc_state); 1958 1959 hsw_set_linetime_wm(new_crtc_state); 1960 1961 if (DISPLAY_VER(dev_priv) >= 11) 1962 icl_set_pipe_chicken(new_crtc_state); 1963 1964 intel_initial_watermarks(state, crtc); 1965 1966 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 1967 intel_crtc_vblank_on(new_crtc_state); 1968 1969 intel_encoders_enable(state, crtc); 1970 1971 if (psl_clkgate_wa) { 1972 intel_crtc_wait_for_next_vblank(crtc); 1973 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false); 1974 } 1975 1976 /* If we change the relative order between pipe/planes enabling, we need 1977 * to change the workaround. */ 1978 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe; 1979 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { 1980 struct intel_crtc *wa_crtc; 1981 1982 wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe); 1983 1984 intel_crtc_wait_for_next_vblank(wa_crtc); 1985 intel_crtc_wait_for_next_vblank(wa_crtc); 1986 } 1987 } 1988 1989 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state) 1990 { 1991 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1992 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1993 enum pipe pipe = crtc->pipe; 1994 1995 /* To avoid upsetting the power well on haswell only disable the pfit if 1996 * it's in use. The hw state code will make sure we get this right. */ 1997 if (!old_crtc_state->pch_pfit.enabled) 1998 return; 1999 2000 intel_de_write_fw(dev_priv, PF_CTL(pipe), 0); 2001 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0); 2002 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0); 2003 } 2004 2005 static void ilk_crtc_disable(struct intel_atomic_state *state, 2006 struct intel_crtc *crtc) 2007 { 2008 const struct intel_crtc_state *old_crtc_state = 2009 intel_atomic_get_old_crtc_state(state, crtc); 2010 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2011 enum pipe pipe = crtc->pipe; 2012 2013 /* 2014 * Sometimes spurious CPU pipe underruns happen when the 2015 * pipe is already disabled, but FDI RX/TX is still enabled. 2016 * Happens at least with VGA+HDMI cloning. Suppress them. 2017 */ 2018 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 2019 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 2020 2021 intel_encoders_disable(state, crtc); 2022 2023 intel_crtc_vblank_off(old_crtc_state); 2024 2025 intel_disable_transcoder(old_crtc_state); 2026 2027 ilk_pfit_disable(old_crtc_state); 2028 2029 if (old_crtc_state->has_pch_encoder) 2030 ilk_pch_disable(state, crtc); 2031 2032 intel_encoders_post_disable(state, crtc); 2033 2034 if (old_crtc_state->has_pch_encoder) 2035 ilk_pch_post_disable(state, crtc); 2036 2037 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2038 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 2039 } 2040 2041 static void hsw_crtc_disable(struct intel_atomic_state *state, 2042 struct intel_crtc *crtc) 2043 { 2044 const struct intel_crtc_state *old_crtc_state = 2045 intel_atomic_get_old_crtc_state(state, crtc); 2046 2047 /* 2048 * FIXME collapse everything to one hook. 2049 * Need care with mst->ddi interactions. 2050 */ 2051 if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) { 2052 intel_encoders_disable(state, crtc); 2053 intel_encoders_post_disable(state, crtc); 2054 } 2055 } 2056 2057 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) 2058 { 2059 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2060 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2061 2062 if (!crtc_state->gmch_pfit.control) 2063 return; 2064 2065 /* 2066 * The panel fitter should only be adjusted whilst the pipe is disabled, 2067 * according to register description and PRM. 2068 */ 2069 drm_WARN_ON(&dev_priv->drm, 2070 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE); 2071 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 2072 2073 intel_de_write(dev_priv, PFIT_PGM_RATIOS, 2074 crtc_state->gmch_pfit.pgm_ratios); 2075 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control); 2076 2077 /* Border color in case we don't scale up to the full screen. Black by 2078 * default, change to something else for debugging. */ 2079 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); 2080 } 2081 2082 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) 2083 { 2084 if (phy == PHY_NONE) 2085 return false; 2086 else if (IS_DG2(dev_priv)) 2087 /* 2088 * DG2 outputs labelled as "combo PHY" in the bspec use 2089 * SNPS PHYs with completely different programming, 2090 * hence we always return false here. 2091 */ 2092 return false; 2093 else if (IS_ALDERLAKE_S(dev_priv)) 2094 return phy <= PHY_E; 2095 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) 2096 return phy <= PHY_D; 2097 else if (IS_JSL_EHL(dev_priv)) 2098 return phy <= PHY_C; 2099 else if (DISPLAY_VER(dev_priv) >= 11) 2100 return phy <= PHY_B; 2101 else 2102 return false; 2103 } 2104 2105 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) 2106 { 2107 if (IS_DG2(dev_priv)) 2108 /* DG2's "TC1" output uses a SNPS PHY */ 2109 return false; 2110 else if (IS_ALDERLAKE_P(dev_priv)) 2111 return phy >= PHY_F && phy <= PHY_I; 2112 else if (IS_TIGERLAKE(dev_priv)) 2113 return phy >= PHY_D && phy <= PHY_I; 2114 else if (IS_ICELAKE(dev_priv)) 2115 return phy >= PHY_C && phy <= PHY_F; 2116 else 2117 return false; 2118 } 2119 2120 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy) 2121 { 2122 if (phy == PHY_NONE) 2123 return false; 2124 else if (IS_DG2(dev_priv)) 2125 /* 2126 * All four "combo" ports and the TC1 port (PHY E) use 2127 * Synopsis PHYs. 2128 */ 2129 return phy <= PHY_E; 2130 2131 return false; 2132 } 2133 2134 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) 2135 { 2136 if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD) 2137 return PHY_D + port - PORT_D_XELPD; 2138 else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1) 2139 return PHY_F + port - PORT_TC1; 2140 else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1) 2141 return PHY_B + port - PORT_TC1; 2142 else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1) 2143 return PHY_C + port - PORT_TC1; 2144 else if (IS_JSL_EHL(i915) && port == PORT_D) 2145 return PHY_A; 2146 2147 return PHY_A + port - PORT_A; 2148 } 2149 2150 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) 2151 { 2152 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port))) 2153 return TC_PORT_NONE; 2154 2155 if (DISPLAY_VER(dev_priv) >= 12) 2156 return TC_PORT_1 + port - PORT_TC1; 2157 else 2158 return TC_PORT_1 + port - PORT_C; 2159 } 2160 2161 enum intel_display_power_domain 2162 intel_aux_power_domain(struct intel_digital_port *dig_port) 2163 { 2164 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 2165 2166 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 2167 return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch); 2168 2169 return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch); 2170 } 2171 2172 static void get_crtc_power_domains(struct intel_crtc_state *crtc_state, 2173 struct intel_power_domain_mask *mask) 2174 { 2175 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2176 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2177 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2178 struct drm_encoder *encoder; 2179 enum pipe pipe = crtc->pipe; 2180 2181 bitmap_zero(mask->bits, POWER_DOMAIN_NUM); 2182 2183 if (!crtc_state->hw.active) 2184 return; 2185 2186 set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits); 2187 set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits); 2188 if (crtc_state->pch_pfit.enabled || 2189 crtc_state->pch_pfit.force_thru) 2190 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits); 2191 2192 drm_for_each_encoder_mask(encoder, &dev_priv->drm, 2193 crtc_state->uapi.encoder_mask) { 2194 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2195 2196 set_bit(intel_encoder->power_domain, mask->bits); 2197 } 2198 2199 if (HAS_DDI(dev_priv) && crtc_state->has_audio) 2200 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits); 2201 2202 if (crtc_state->shared_dpll) 2203 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits); 2204 2205 if (crtc_state->dsc.compression_enable) 2206 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits); 2207 } 2208 2209 static void 2210 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, 2211 struct intel_power_domain_mask *old_domains) 2212 { 2213 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2214 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2215 enum intel_display_power_domain domain; 2216 struct intel_power_domain_mask domains, new_domains; 2217 2218 get_crtc_power_domains(crtc_state, &domains); 2219 2220 bitmap_andnot(new_domains.bits, 2221 domains.bits, 2222 crtc->enabled_power_domains.mask.bits, 2223 POWER_DOMAIN_NUM); 2224 bitmap_andnot(old_domains->bits, 2225 crtc->enabled_power_domains.mask.bits, 2226 domains.bits, 2227 POWER_DOMAIN_NUM); 2228 2229 for_each_power_domain(domain, &new_domains) 2230 intel_display_power_get_in_set(dev_priv, 2231 &crtc->enabled_power_domains, 2232 domain); 2233 } 2234 2235 static void modeset_put_crtc_power_domains(struct intel_crtc *crtc, 2236 struct intel_power_domain_mask *domains) 2237 { 2238 intel_display_power_put_mask_in_set(to_i915(crtc->base.dev), 2239 &crtc->enabled_power_domains, 2240 domains); 2241 } 2242 2243 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 2244 { 2245 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2246 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2247 2248 if (intel_crtc_has_dp_encoder(crtc_state)) { 2249 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 2250 &crtc_state->dp_m_n); 2251 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 2252 &crtc_state->dp_m2_n2); 2253 } 2254 2255 intel_set_transcoder_timings(crtc_state); 2256 2257 i9xx_set_pipeconf(crtc_state); 2258 } 2259 2260 static void valleyview_crtc_enable(struct intel_atomic_state *state, 2261 struct intel_crtc *crtc) 2262 { 2263 const struct intel_crtc_state *new_crtc_state = 2264 intel_atomic_get_new_crtc_state(state, crtc); 2265 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2266 enum pipe pipe = crtc->pipe; 2267 2268 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 2269 return; 2270 2271 i9xx_configure_cpu_transcoder(new_crtc_state); 2272 2273 intel_set_pipe_src_size(new_crtc_state); 2274 2275 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 2276 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY); 2277 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0); 2278 } 2279 2280 crtc->active = true; 2281 2282 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2283 2284 intel_encoders_pre_pll_enable(state, crtc); 2285 2286 if (IS_CHERRYVIEW(dev_priv)) 2287 chv_enable_pll(new_crtc_state); 2288 else 2289 vlv_enable_pll(new_crtc_state); 2290 2291 intel_encoders_pre_enable(state, crtc); 2292 2293 i9xx_pfit_enable(new_crtc_state); 2294 2295 intel_color_load_luts(new_crtc_state); 2296 intel_color_commit_noarm(new_crtc_state); 2297 intel_color_commit_arm(new_crtc_state); 2298 /* update DSPCNTR to configure gamma for pipe bottom color */ 2299 intel_disable_primary_plane(new_crtc_state); 2300 2301 intel_initial_watermarks(state, crtc); 2302 intel_enable_transcoder(new_crtc_state); 2303 2304 intel_crtc_vblank_on(new_crtc_state); 2305 2306 intel_encoders_enable(state, crtc); 2307 } 2308 2309 static void i9xx_crtc_enable(struct intel_atomic_state *state, 2310 struct intel_crtc *crtc) 2311 { 2312 const struct intel_crtc_state *new_crtc_state = 2313 intel_atomic_get_new_crtc_state(state, crtc); 2314 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2315 enum pipe pipe = crtc->pipe; 2316 2317 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 2318 return; 2319 2320 i9xx_configure_cpu_transcoder(new_crtc_state); 2321 2322 intel_set_pipe_src_size(new_crtc_state); 2323 2324 crtc->active = true; 2325 2326 if (DISPLAY_VER(dev_priv) != 2) 2327 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2328 2329 intel_encoders_pre_enable(state, crtc); 2330 2331 i9xx_enable_pll(new_crtc_state); 2332 2333 i9xx_pfit_enable(new_crtc_state); 2334 2335 intel_color_load_luts(new_crtc_state); 2336 intel_color_commit_noarm(new_crtc_state); 2337 intel_color_commit_arm(new_crtc_state); 2338 /* update DSPCNTR to configure gamma for pipe bottom color */ 2339 intel_disable_primary_plane(new_crtc_state); 2340 2341 if (!intel_initial_watermarks(state, crtc)) 2342 intel_update_watermarks(dev_priv); 2343 intel_enable_transcoder(new_crtc_state); 2344 2345 intel_crtc_vblank_on(new_crtc_state); 2346 2347 intel_encoders_enable(state, crtc); 2348 2349 /* prevents spurious underruns */ 2350 if (DISPLAY_VER(dev_priv) == 2) 2351 intel_crtc_wait_for_next_vblank(crtc); 2352 } 2353 2354 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) 2355 { 2356 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 2357 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2358 2359 if (!old_crtc_state->gmch_pfit.control) 2360 return; 2361 2362 assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder); 2363 2364 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n", 2365 intel_de_read(dev_priv, PFIT_CONTROL)); 2366 intel_de_write(dev_priv, PFIT_CONTROL, 0); 2367 } 2368 2369 static void i9xx_crtc_disable(struct intel_atomic_state *state, 2370 struct intel_crtc *crtc) 2371 { 2372 struct intel_crtc_state *old_crtc_state = 2373 intel_atomic_get_old_crtc_state(state, crtc); 2374 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2375 enum pipe pipe = crtc->pipe; 2376 2377 /* 2378 * On gen2 planes are double buffered but the pipe isn't, so we must 2379 * wait for planes to fully turn off before disabling the pipe. 2380 */ 2381 if (DISPLAY_VER(dev_priv) == 2) 2382 intel_crtc_wait_for_next_vblank(crtc); 2383 2384 intel_encoders_disable(state, crtc); 2385 2386 intel_crtc_vblank_off(old_crtc_state); 2387 2388 intel_disable_transcoder(old_crtc_state); 2389 2390 i9xx_pfit_disable(old_crtc_state); 2391 2392 intel_encoders_post_disable(state, crtc); 2393 2394 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) { 2395 if (IS_CHERRYVIEW(dev_priv)) 2396 chv_disable_pll(dev_priv, pipe); 2397 else if (IS_VALLEYVIEW(dev_priv)) 2398 vlv_disable_pll(dev_priv, pipe); 2399 else 2400 i9xx_disable_pll(old_crtc_state); 2401 } 2402 2403 intel_encoders_post_pll_disable(state, crtc); 2404 2405 if (DISPLAY_VER(dev_priv) != 2) 2406 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 2407 2408 if (!dev_priv->wm_disp->initial_watermarks) 2409 intel_update_watermarks(dev_priv); 2410 2411 /* clock the pipe down to 640x480@60 to potentially save power */ 2412 if (IS_I830(dev_priv)) 2413 i830_enable_pipe(dev_priv, pipe); 2414 } 2415 2416 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, 2417 struct drm_modeset_acquire_ctx *ctx) 2418 { 2419 struct intel_encoder *encoder; 2420 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2421 struct intel_bw_state *bw_state = 2422 to_intel_bw_state(dev_priv->bw_obj.state); 2423 struct intel_cdclk_state *cdclk_state = 2424 to_intel_cdclk_state(dev_priv->cdclk.obj.state); 2425 struct intel_dbuf_state *dbuf_state = 2426 to_intel_dbuf_state(dev_priv->dbuf.obj.state); 2427 struct intel_crtc_state *crtc_state = 2428 to_intel_crtc_state(crtc->base.state); 2429 struct intel_plane *plane; 2430 struct drm_atomic_state *state; 2431 struct intel_crtc_state *temp_crtc_state; 2432 enum pipe pipe = crtc->pipe; 2433 int ret; 2434 2435 if (!crtc_state->hw.active) 2436 return; 2437 2438 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 2439 const struct intel_plane_state *plane_state = 2440 to_intel_plane_state(plane->base.state); 2441 2442 if (plane_state->uapi.visible) 2443 intel_plane_disable_noatomic(crtc, plane); 2444 } 2445 2446 state = drm_atomic_state_alloc(&dev_priv->drm); 2447 if (!state) { 2448 drm_dbg_kms(&dev_priv->drm, 2449 "failed to disable [CRTC:%d:%s], out of memory", 2450 crtc->base.base.id, crtc->base.name); 2451 return; 2452 } 2453 2454 state->acquire_ctx = ctx; 2455 2456 /* Everything's already locked, -EDEADLK can't happen. */ 2457 temp_crtc_state = intel_atomic_get_crtc_state(state, crtc); 2458 ret = drm_atomic_add_affected_connectors(state, &crtc->base); 2459 2460 drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret); 2461 2462 dev_priv->display->crtc_disable(to_intel_atomic_state(state), crtc); 2463 2464 drm_atomic_state_put(state); 2465 2466 drm_dbg_kms(&dev_priv->drm, 2467 "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", 2468 crtc->base.base.id, crtc->base.name); 2469 2470 crtc->active = false; 2471 crtc->base.enabled = false; 2472 2473 drm_WARN_ON(&dev_priv->drm, 2474 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0); 2475 crtc_state->uapi.active = false; 2476 crtc_state->uapi.connector_mask = 0; 2477 crtc_state->uapi.encoder_mask = 0; 2478 intel_crtc_free_hw_state(crtc_state); 2479 memset(&crtc_state->hw, 0, sizeof(crtc_state->hw)); 2480 2481 for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder) 2482 encoder->base.crtc = NULL; 2483 2484 intel_fbc_disable(crtc); 2485 intel_update_watermarks(dev_priv); 2486 intel_disable_shared_dpll(crtc_state); 2487 2488 intel_display_power_put_all_in_set(dev_priv, &crtc->enabled_power_domains); 2489 2490 cdclk_state->min_cdclk[pipe] = 0; 2491 cdclk_state->min_voltage_level[pipe] = 0; 2492 cdclk_state->active_pipes &= ~BIT(pipe); 2493 2494 dbuf_state->active_pipes &= ~BIT(pipe); 2495 2496 bw_state->data_rate[pipe] = 0; 2497 bw_state->num_active_planes[pipe] = 0; 2498 } 2499 2500 /* 2501 * turn all crtc's off, but do not adjust state 2502 * This has to be paired with a call to intel_modeset_setup_hw_state. 2503 */ 2504 int intel_display_suspend(struct drm_device *dev) 2505 { 2506 struct drm_i915_private *dev_priv = to_i915(dev); 2507 struct drm_atomic_state *state; 2508 int ret; 2509 2510 if (!HAS_DISPLAY(dev_priv)) 2511 return 0; 2512 2513 state = drm_atomic_helper_suspend(dev); 2514 ret = PTR_ERR_OR_ZERO(state); 2515 if (ret) 2516 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", 2517 ret); 2518 else 2519 dev_priv->modeset_restore_state = state; 2520 return ret; 2521 } 2522 2523 void intel_encoder_destroy(struct drm_encoder *encoder) 2524 { 2525 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2526 2527 drm_encoder_cleanup(encoder); 2528 kfree(intel_encoder); 2529 } 2530 2531 /* Cross check the actual hw state with our own modeset state tracking (and it's 2532 * internal consistency). */ 2533 static void intel_connector_verify_state(struct intel_crtc_state *crtc_state, 2534 struct drm_connector_state *conn_state) 2535 { 2536 struct intel_connector *connector = to_intel_connector(conn_state->connector); 2537 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2538 2539 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", 2540 connector->base.base.id, connector->base.name); 2541 2542 if (connector->get_hw_state(connector)) { 2543 struct intel_encoder *encoder = intel_attached_encoder(connector); 2544 2545 I915_STATE_WARN(!crtc_state, 2546 "connector enabled without attached crtc\n"); 2547 2548 if (!crtc_state) 2549 return; 2550 2551 I915_STATE_WARN(!crtc_state->hw.active, 2552 "connector is active, but attached crtc isn't\n"); 2553 2554 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) 2555 return; 2556 2557 I915_STATE_WARN(conn_state->best_encoder != &encoder->base, 2558 "atomic encoder doesn't match attached encoder\n"); 2559 2560 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, 2561 "attached encoder crtc differs from connector crtc\n"); 2562 } else { 2563 I915_STATE_WARN(crtc_state && crtc_state->hw.active, 2564 "attached crtc is active, but connector isn't\n"); 2565 I915_STATE_WARN(!crtc_state && conn_state->best_encoder, 2566 "best encoder set without crtc!\n"); 2567 } 2568 } 2569 2570 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) 2571 { 2572 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2573 2574 /* GDG double wide on either pipe, otherwise pipe A only */ 2575 return DISPLAY_VER(dev_priv) < 4 && 2576 (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); 2577 } 2578 2579 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) 2580 { 2581 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock; 2582 struct drm_rect src; 2583 2584 /* 2585 * We only use IF-ID interlacing. If we ever use 2586 * PF-ID we'll need to adjust the pixel_rate here. 2587 */ 2588 2589 if (!crtc_state->pch_pfit.enabled) 2590 return pixel_rate; 2591 2592 drm_rect_init(&src, 0, 0, 2593 drm_rect_width(&crtc_state->pipe_src) << 16, 2594 drm_rect_height(&crtc_state->pipe_src) << 16); 2595 2596 return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst, 2597 pixel_rate); 2598 } 2599 2600 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode, 2601 const struct drm_display_mode *timings) 2602 { 2603 mode->hdisplay = timings->crtc_hdisplay; 2604 mode->htotal = timings->crtc_htotal; 2605 mode->hsync_start = timings->crtc_hsync_start; 2606 mode->hsync_end = timings->crtc_hsync_end; 2607 2608 mode->vdisplay = timings->crtc_vdisplay; 2609 mode->vtotal = timings->crtc_vtotal; 2610 mode->vsync_start = timings->crtc_vsync_start; 2611 mode->vsync_end = timings->crtc_vsync_end; 2612 2613 mode->flags = timings->flags; 2614 mode->type = DRM_MODE_TYPE_DRIVER; 2615 2616 mode->clock = timings->crtc_clock; 2617 2618 drm_mode_set_name(mode); 2619 } 2620 2621 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) 2622 { 2623 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2624 2625 if (HAS_GMCH(dev_priv)) 2626 /* FIXME calculate proper pipe pixel rate for GMCH pfit */ 2627 crtc_state->pixel_rate = 2628 crtc_state->hw.pipe_mode.crtc_clock; 2629 else 2630 crtc_state->pixel_rate = 2631 ilk_pipe_pixel_rate(crtc_state); 2632 } 2633 2634 static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state *crtc_state, 2635 struct drm_display_mode *mode) 2636 { 2637 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2638 2639 if (num_pipes < 2) 2640 return; 2641 2642 mode->crtc_clock /= num_pipes; 2643 mode->crtc_hdisplay /= num_pipes; 2644 mode->crtc_hblank_start /= num_pipes; 2645 mode->crtc_hblank_end /= num_pipes; 2646 mode->crtc_hsync_start /= num_pipes; 2647 mode->crtc_hsync_end /= num_pipes; 2648 mode->crtc_htotal /= num_pipes; 2649 } 2650 2651 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state, 2652 struct drm_display_mode *mode) 2653 { 2654 int overlap = crtc_state->splitter.pixel_overlap; 2655 int n = crtc_state->splitter.link_count; 2656 2657 if (!crtc_state->splitter.enable) 2658 return; 2659 2660 /* 2661 * eDP MSO uses segment timings from EDID for transcoder 2662 * timings, but full mode for everything else. 2663 * 2664 * h_full = (h_segment - pixel_overlap) * link_count 2665 */ 2666 mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n; 2667 mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n; 2668 mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n; 2669 mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n; 2670 mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n; 2671 mode->crtc_htotal = (mode->crtc_htotal - overlap) * n; 2672 mode->crtc_clock *= n; 2673 } 2674 2675 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state) 2676 { 2677 struct drm_display_mode *mode = &crtc_state->hw.mode; 2678 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2679 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2680 2681 /* 2682 * Start with the adjusted_mode crtc timings, which 2683 * have been filled with the transcoder timings. 2684 */ 2685 drm_mode_copy(pipe_mode, adjusted_mode); 2686 2687 /* Expand MSO per-segment transcoder timings to full */ 2688 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2689 2690 /* 2691 * We want the full numbers in adjusted_mode normal timings, 2692 * adjusted_mode crtc timings are left with the raw transcoder 2693 * timings. 2694 */ 2695 intel_mode_from_crtc_timings(adjusted_mode, pipe_mode); 2696 2697 /* Populate the "user" mode with full numbers */ 2698 drm_mode_copy(mode, pipe_mode); 2699 intel_mode_from_crtc_timings(mode, mode); 2700 mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) * 2701 (intel_bigjoiner_num_pipes(crtc_state) ?: 1); 2702 mode->vdisplay = drm_rect_height(&crtc_state->pipe_src); 2703 2704 /* Derive per-pipe timings in case bigjoiner is used */ 2705 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2706 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2707 2708 intel_crtc_compute_pixel_rate(crtc_state); 2709 } 2710 2711 static void intel_encoder_get_config(struct intel_encoder *encoder, 2712 struct intel_crtc_state *crtc_state) 2713 { 2714 encoder->get_config(encoder, crtc_state); 2715 2716 intel_crtc_readout_derived_state(crtc_state); 2717 } 2718 2719 static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state *crtc_state) 2720 { 2721 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2722 int width, height; 2723 2724 if (num_pipes < 2) 2725 return; 2726 2727 width = drm_rect_width(&crtc_state->pipe_src); 2728 height = drm_rect_height(&crtc_state->pipe_src); 2729 2730 drm_rect_init(&crtc_state->pipe_src, 0, 0, 2731 width / num_pipes, height); 2732 } 2733 2734 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state) 2735 { 2736 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2737 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2738 2739 intel_bigjoiner_compute_pipe_src(crtc_state); 2740 2741 /* 2742 * Pipe horizontal size must be even in: 2743 * - DVO ganged mode 2744 * - LVDS dual channel mode 2745 * - Double wide pipe 2746 */ 2747 if (drm_rect_width(&crtc_state->pipe_src) & 1) { 2748 if (crtc_state->double_wide) { 2749 drm_dbg_kms(&i915->drm, 2750 "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n", 2751 crtc->base.base.id, crtc->base.name); 2752 return -EINVAL; 2753 } 2754 2755 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 2756 intel_is_dual_link_lvds(i915)) { 2757 drm_dbg_kms(&i915->drm, 2758 "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n", 2759 crtc->base.base.id, crtc->base.name); 2760 return -EINVAL; 2761 } 2762 } 2763 2764 return 0; 2765 } 2766 2767 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state) 2768 { 2769 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2770 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2771 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2772 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2773 int clock_limit = i915->max_dotclk_freq; 2774 2775 /* 2776 * Start with the adjusted_mode crtc timings, which 2777 * have been filled with the transcoder timings. 2778 */ 2779 drm_mode_copy(pipe_mode, adjusted_mode); 2780 2781 /* Expand MSO per-segment transcoder timings to full */ 2782 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2783 2784 /* Derive per-pipe timings in case bigjoiner is used */ 2785 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2786 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2787 2788 if (DISPLAY_VER(i915) < 4) { 2789 clock_limit = i915->max_cdclk_freq * 9 / 10; 2790 2791 /* 2792 * Enable double wide mode when the dot clock 2793 * is > 90% of the (display) core speed. 2794 */ 2795 if (intel_crtc_supports_double_wide(crtc) && 2796 pipe_mode->crtc_clock > clock_limit) { 2797 clock_limit = i915->max_dotclk_freq; 2798 crtc_state->double_wide = true; 2799 } 2800 } 2801 2802 if (pipe_mode->crtc_clock > clock_limit) { 2803 drm_dbg_kms(&i915->drm, 2804 "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", 2805 crtc->base.base.id, crtc->base.name, 2806 pipe_mode->crtc_clock, clock_limit, 2807 str_yes_no(crtc_state->double_wide)); 2808 return -EINVAL; 2809 } 2810 2811 return 0; 2812 } 2813 2814 static int intel_crtc_compute_config(struct intel_atomic_state *state, 2815 struct intel_crtc *crtc) 2816 { 2817 struct intel_crtc_state *crtc_state = 2818 intel_atomic_get_new_crtc_state(state, crtc); 2819 int ret; 2820 2821 ret = intel_crtc_compute_pipe_src(crtc_state); 2822 if (ret) 2823 return ret; 2824 2825 ret = intel_crtc_compute_pipe_mode(crtc_state); 2826 if (ret) 2827 return ret; 2828 2829 intel_crtc_compute_pixel_rate(crtc_state); 2830 2831 if (crtc_state->has_pch_encoder) 2832 return ilk_fdi_compute_config(crtc, crtc_state); 2833 2834 return 0; 2835 } 2836 2837 static void 2838 intel_reduce_m_n_ratio(u32 *num, u32 *den) 2839 { 2840 while (*num > DATA_LINK_M_N_MASK || 2841 *den > DATA_LINK_M_N_MASK) { 2842 *num >>= 1; 2843 *den >>= 1; 2844 } 2845 } 2846 2847 static void compute_m_n(unsigned int m, unsigned int n, 2848 u32 *ret_m, u32 *ret_n, 2849 bool constant_n) 2850 { 2851 /* 2852 * Several DP dongles in particular seem to be fussy about 2853 * too large link M/N values. Give N value as 0x8000 that 2854 * should be acceptable by specific devices. 0x8000 is the 2855 * specified fixed N value for asynchronous clock mode, 2856 * which the devices expect also in synchronous clock mode. 2857 */ 2858 if (constant_n) 2859 *ret_n = DP_LINK_CONSTANT_N_VALUE; 2860 else 2861 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); 2862 2863 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n); 2864 intel_reduce_m_n_ratio(ret_m, ret_n); 2865 } 2866 2867 void 2868 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes, 2869 int pixel_clock, int link_clock, 2870 struct intel_link_m_n *m_n, 2871 bool constant_n, bool fec_enable) 2872 { 2873 u32 data_clock = bits_per_pixel * pixel_clock; 2874 2875 if (fec_enable) 2876 data_clock = intel_dp_mode_to_fec_clock(data_clock); 2877 2878 m_n->tu = 64; 2879 compute_m_n(data_clock, 2880 link_clock * nlanes * 8, 2881 &m_n->data_m, &m_n->data_n, 2882 constant_n); 2883 2884 compute_m_n(pixel_clock, link_clock, 2885 &m_n->link_m, &m_n->link_n, 2886 constant_n); 2887 } 2888 2889 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv) 2890 { 2891 /* 2892 * There may be no VBT; and if the BIOS enabled SSC we can 2893 * just keep using it to avoid unnecessary flicker. Whereas if the 2894 * BIOS isn't using it, don't assume it will work even if the VBT 2895 * indicates as much. 2896 */ 2897 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { 2898 bool bios_lvds_use_ssc = intel_de_read(dev_priv, 2899 PCH_DREF_CONTROL) & 2900 DREF_SSC1_ENABLE; 2901 2902 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { 2903 drm_dbg_kms(&dev_priv->drm, 2904 "SSC %s by BIOS, overriding VBT which says %s\n", 2905 str_enabled_disabled(bios_lvds_use_ssc), 2906 str_enabled_disabled(dev_priv->vbt.lvds_use_ssc)); 2907 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; 2908 } 2909 } 2910 } 2911 2912 void intel_zero_m_n(struct intel_link_m_n *m_n) 2913 { 2914 /* corresponds to 0 register value */ 2915 memset(m_n, 0, sizeof(*m_n)); 2916 m_n->tu = 1; 2917 } 2918 2919 void intel_set_m_n(struct drm_i915_private *i915, 2920 const struct intel_link_m_n *m_n, 2921 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 2922 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 2923 { 2924 intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); 2925 intel_de_write(i915, data_n_reg, m_n->data_n); 2926 intel_de_write(i915, link_m_reg, m_n->link_m); 2927 /* 2928 * On BDW+ writing LINK_N arms the double buffered update 2929 * of all the M/N registers, so it must be written last. 2930 */ 2931 intel_de_write(i915, link_n_reg, m_n->link_n); 2932 } 2933 2934 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, 2935 enum transcoder transcoder) 2936 { 2937 if (IS_HASWELL(dev_priv)) 2938 return transcoder == TRANSCODER_EDP; 2939 2940 return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv); 2941 } 2942 2943 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, 2944 enum transcoder transcoder, 2945 const struct intel_link_m_n *m_n) 2946 { 2947 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2948 enum pipe pipe = crtc->pipe; 2949 2950 if (DISPLAY_VER(dev_priv) >= 5) 2951 intel_set_m_n(dev_priv, m_n, 2952 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 2953 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 2954 else 2955 intel_set_m_n(dev_priv, m_n, 2956 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 2957 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 2958 } 2959 2960 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, 2961 enum transcoder transcoder, 2962 const struct intel_link_m_n *m_n) 2963 { 2964 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2965 2966 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 2967 return; 2968 2969 intel_set_m_n(dev_priv, m_n, 2970 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 2971 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 2972 } 2973 2974 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) 2975 { 2976 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2977 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2978 enum pipe pipe = crtc->pipe; 2979 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2980 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2981 u32 crtc_vtotal, crtc_vblank_end; 2982 int vsyncshift = 0; 2983 2984 /* We need to be careful not to changed the adjusted mode, for otherwise 2985 * the hw state checker will get angry at the mismatch. */ 2986 crtc_vtotal = adjusted_mode->crtc_vtotal; 2987 crtc_vblank_end = adjusted_mode->crtc_vblank_end; 2988 2989 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 2990 /* the chip adds 2 halflines automatically */ 2991 crtc_vtotal -= 1; 2992 crtc_vblank_end -= 1; 2993 2994 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 2995 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; 2996 else 2997 vsyncshift = adjusted_mode->crtc_hsync_start - 2998 adjusted_mode->crtc_htotal / 2; 2999 if (vsyncshift < 0) 3000 vsyncshift += adjusted_mode->crtc_htotal; 3001 } 3002 3003 if (DISPLAY_VER(dev_priv) > 3) 3004 intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder), 3005 vsyncshift); 3006 3007 intel_de_write(dev_priv, HTOTAL(cpu_transcoder), 3008 (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16)); 3009 intel_de_write(dev_priv, HBLANK(cpu_transcoder), 3010 (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16)); 3011 intel_de_write(dev_priv, HSYNC(cpu_transcoder), 3012 (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16)); 3013 3014 intel_de_write(dev_priv, VTOTAL(cpu_transcoder), 3015 (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16)); 3016 intel_de_write(dev_priv, VBLANK(cpu_transcoder), 3017 (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16)); 3018 intel_de_write(dev_priv, VSYNC(cpu_transcoder), 3019 (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16)); 3020 3021 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be 3022 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is 3023 * documented on the DDI_FUNC_CTL register description, EDP Input Select 3024 * bits. */ 3025 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && 3026 (pipe == PIPE_B || pipe == PIPE_C)) 3027 intel_de_write(dev_priv, VTOTAL(pipe), 3028 intel_de_read(dev_priv, VTOTAL(cpu_transcoder))); 3029 3030 } 3031 3032 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) 3033 { 3034 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3035 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3036 int width = drm_rect_width(&crtc_state->pipe_src); 3037 int height = drm_rect_height(&crtc_state->pipe_src); 3038 enum pipe pipe = crtc->pipe; 3039 3040 /* pipesrc controls the size that is scaled from, which should 3041 * always be the user's requested size. 3042 */ 3043 intel_de_write(dev_priv, PIPESRC(pipe), 3044 PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1)); 3045 } 3046 3047 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) 3048 { 3049 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3050 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3051 3052 if (DISPLAY_VER(dev_priv) == 2) 3053 return false; 3054 3055 if (DISPLAY_VER(dev_priv) >= 9 || 3056 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 3057 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW; 3058 else 3059 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK; 3060 } 3061 3062 static void intel_get_transcoder_timings(struct intel_crtc *crtc, 3063 struct intel_crtc_state *pipe_config) 3064 { 3065 struct drm_device *dev = crtc->base.dev; 3066 struct drm_i915_private *dev_priv = to_i915(dev); 3067 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3068 u32 tmp; 3069 3070 tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder)); 3071 pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; 3072 pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; 3073 3074 if (!transcoder_is_dsi(cpu_transcoder)) { 3075 tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder)); 3076 pipe_config->hw.adjusted_mode.crtc_hblank_start = 3077 (tmp & 0xffff) + 1; 3078 pipe_config->hw.adjusted_mode.crtc_hblank_end = 3079 ((tmp >> 16) & 0xffff) + 1; 3080 } 3081 tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder)); 3082 pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; 3083 pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; 3084 3085 tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder)); 3086 pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; 3087 pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; 3088 3089 if (!transcoder_is_dsi(cpu_transcoder)) { 3090 tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder)); 3091 pipe_config->hw.adjusted_mode.crtc_vblank_start = 3092 (tmp & 0xffff) + 1; 3093 pipe_config->hw.adjusted_mode.crtc_vblank_end = 3094 ((tmp >> 16) & 0xffff) + 1; 3095 } 3096 tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder)); 3097 pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; 3098 pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; 3099 3100 if (intel_pipe_is_interlaced(pipe_config)) { 3101 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; 3102 pipe_config->hw.adjusted_mode.crtc_vtotal += 1; 3103 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1; 3104 } 3105 } 3106 3107 static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state) 3108 { 3109 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3110 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 3111 enum pipe master_pipe, pipe = crtc->pipe; 3112 int width; 3113 3114 if (num_pipes < 2) 3115 return; 3116 3117 master_pipe = bigjoiner_master_pipe(crtc_state); 3118 width = drm_rect_width(&crtc_state->pipe_src); 3119 3120 drm_rect_translate_to(&crtc_state->pipe_src, 3121 (pipe - master_pipe) * width, 0); 3122 } 3123 3124 static void intel_get_pipe_src_size(struct intel_crtc *crtc, 3125 struct intel_crtc_state *pipe_config) 3126 { 3127 struct drm_device *dev = crtc->base.dev; 3128 struct drm_i915_private *dev_priv = to_i915(dev); 3129 u32 tmp; 3130 3131 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe)); 3132 3133 drm_rect_init(&pipe_config->pipe_src, 0, 0, 3134 REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1, 3135 REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1); 3136 3137 intel_bigjoiner_adjust_pipe_src(pipe_config); 3138 } 3139 3140 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) 3141 { 3142 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3143 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3144 u32 pipeconf = 0; 3145 3146 /* we keep both pipes enabled on 830 */ 3147 if (IS_I830(dev_priv)) 3148 pipeconf |= PIPECONF_ENABLE; 3149 3150 if (crtc_state->double_wide) 3151 pipeconf |= PIPECONF_DOUBLE_WIDE; 3152 3153 /* only g4x and later have fancy bpc/dither controls */ 3154 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 3155 IS_CHERRYVIEW(dev_priv)) { 3156 /* Bspec claims that we can't use dithering for 30bpp pipes. */ 3157 if (crtc_state->dither && crtc_state->pipe_bpp != 30) 3158 pipeconf |= PIPECONF_DITHER_EN | 3159 PIPECONF_DITHER_TYPE_SP; 3160 3161 switch (crtc_state->pipe_bpp) { 3162 case 18: 3163 pipeconf |= PIPECONF_BPC_6; 3164 break; 3165 case 24: 3166 pipeconf |= PIPECONF_BPC_8; 3167 break; 3168 case 30: 3169 pipeconf |= PIPECONF_BPC_10; 3170 break; 3171 default: 3172 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3173 BUG(); 3174 } 3175 } 3176 3177 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 3178 if (DISPLAY_VER(dev_priv) < 4 || 3179 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3180 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; 3181 else 3182 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; 3183 } else { 3184 pipeconf |= PIPECONF_INTERLACE_PROGRESSIVE; 3185 } 3186 3187 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 3188 crtc_state->limited_color_range) 3189 pipeconf |= PIPECONF_COLOR_RANGE_SELECT; 3190 3191 pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); 3192 3193 pipeconf |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3194 3195 intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf); 3196 intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe)); 3197 } 3198 3199 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv) 3200 { 3201 if (IS_I830(dev_priv)) 3202 return false; 3203 3204 return DISPLAY_VER(dev_priv) >= 4 || 3205 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); 3206 } 3207 3208 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state) 3209 { 3210 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3211 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3212 u32 tmp; 3213 3214 if (!i9xx_has_pfit(dev_priv)) 3215 return; 3216 3217 tmp = intel_de_read(dev_priv, PFIT_CONTROL); 3218 if (!(tmp & PFIT_ENABLE)) 3219 return; 3220 3221 /* Check whether the pfit is attached to our pipe. */ 3222 if (DISPLAY_VER(dev_priv) < 4) { 3223 if (crtc->pipe != PIPE_B) 3224 return; 3225 } else { 3226 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) 3227 return; 3228 } 3229 3230 crtc_state->gmch_pfit.control = tmp; 3231 crtc_state->gmch_pfit.pgm_ratios = 3232 intel_de_read(dev_priv, PFIT_PGM_RATIOS); 3233 } 3234 3235 static void vlv_crtc_clock_get(struct intel_crtc *crtc, 3236 struct intel_crtc_state *pipe_config) 3237 { 3238 struct drm_device *dev = crtc->base.dev; 3239 struct drm_i915_private *dev_priv = to_i915(dev); 3240 enum pipe pipe = crtc->pipe; 3241 struct dpll clock; 3242 u32 mdiv; 3243 int refclk = 100000; 3244 3245 /* In case of DSI, DPLL will not be used */ 3246 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 3247 return; 3248 3249 vlv_dpio_get(dev_priv); 3250 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); 3251 vlv_dpio_put(dev_priv); 3252 3253 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; 3254 clock.m2 = mdiv & DPIO_M2DIV_MASK; 3255 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; 3256 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; 3257 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; 3258 3259 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); 3260 } 3261 3262 static void chv_crtc_clock_get(struct intel_crtc *crtc, 3263 struct intel_crtc_state *pipe_config) 3264 { 3265 struct drm_device *dev = crtc->base.dev; 3266 struct drm_i915_private *dev_priv = to_i915(dev); 3267 enum pipe pipe = crtc->pipe; 3268 enum dpio_channel port = vlv_pipe_to_channel(pipe); 3269 struct dpll clock; 3270 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; 3271 int refclk = 100000; 3272 3273 /* In case of DSI, DPLL will not be used */ 3274 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 3275 return; 3276 3277 vlv_dpio_get(dev_priv); 3278 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); 3279 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); 3280 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); 3281 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); 3282 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); 3283 vlv_dpio_put(dev_priv); 3284 3285 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; 3286 clock.m2 = (pll_dw0 & 0xff) << 22; 3287 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) 3288 clock.m2 |= pll_dw2 & 0x3fffff; 3289 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; 3290 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; 3291 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; 3292 3293 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); 3294 } 3295 3296 static enum intel_output_format 3297 bdw_get_pipemisc_output_format(struct intel_crtc *crtc) 3298 { 3299 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3300 u32 tmp; 3301 3302 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); 3303 3304 if (tmp & PIPEMISC_YUV420_ENABLE) { 3305 /* We support 4:2:0 in full blend mode only */ 3306 drm_WARN_ON(&dev_priv->drm, 3307 (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0); 3308 3309 return INTEL_OUTPUT_FORMAT_YCBCR420; 3310 } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) { 3311 return INTEL_OUTPUT_FORMAT_YCBCR444; 3312 } else { 3313 return INTEL_OUTPUT_FORMAT_RGB; 3314 } 3315 } 3316 3317 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state) 3318 { 3319 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3320 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 3321 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3322 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 3323 u32 tmp; 3324 3325 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); 3326 3327 if (tmp & DISP_PIPE_GAMMA_ENABLE) 3328 crtc_state->gamma_enable = true; 3329 3330 if (!HAS_GMCH(dev_priv) && 3331 tmp & DISP_PIPE_CSC_ENABLE) 3332 crtc_state->csc_enable = true; 3333 } 3334 3335 static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 3336 struct intel_crtc_state *pipe_config) 3337 { 3338 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3339 enum intel_display_power_domain power_domain; 3340 intel_wakeref_t wakeref; 3341 u32 tmp; 3342 bool ret; 3343 3344 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3345 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3346 if (!wakeref) 3347 return false; 3348 3349 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3350 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3351 pipe_config->shared_dpll = NULL; 3352 3353 ret = false; 3354 3355 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); 3356 if (!(tmp & PIPECONF_ENABLE)) 3357 goto out; 3358 3359 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 3360 IS_CHERRYVIEW(dev_priv)) { 3361 switch (tmp & PIPECONF_BPC_MASK) { 3362 case PIPECONF_BPC_6: 3363 pipe_config->pipe_bpp = 18; 3364 break; 3365 case PIPECONF_BPC_8: 3366 pipe_config->pipe_bpp = 24; 3367 break; 3368 case PIPECONF_BPC_10: 3369 pipe_config->pipe_bpp = 30; 3370 break; 3371 default: 3372 MISSING_CASE(tmp); 3373 break; 3374 } 3375 } 3376 3377 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 3378 (tmp & PIPECONF_COLOR_RANGE_SELECT)) 3379 pipe_config->limited_color_range = true; 3380 3381 pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_I9XX, tmp); 3382 3383 pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1; 3384 3385 if (IS_CHERRYVIEW(dev_priv)) 3386 pipe_config->cgm_mode = intel_de_read(dev_priv, 3387 CGM_PIPE_MODE(crtc->pipe)); 3388 3389 i9xx_get_pipe_color_config(pipe_config); 3390 intel_color_get_config(pipe_config); 3391 3392 if (DISPLAY_VER(dev_priv) < 4) 3393 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; 3394 3395 intel_get_transcoder_timings(crtc, pipe_config); 3396 intel_get_pipe_src_size(crtc, pipe_config); 3397 3398 i9xx_get_pfit_config(pipe_config); 3399 3400 if (DISPLAY_VER(dev_priv) >= 4) { 3401 /* No way to read it out on pipes B and C */ 3402 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) 3403 tmp = dev_priv->chv_dpll_md[crtc->pipe]; 3404 else 3405 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe)); 3406 pipe_config->pixel_multiplier = 3407 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) 3408 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; 3409 pipe_config->dpll_hw_state.dpll_md = tmp; 3410 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 3411 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 3412 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe)); 3413 pipe_config->pixel_multiplier = 3414 ((tmp & SDVO_MULTIPLIER_MASK) 3415 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; 3416 } else { 3417 /* Note that on i915G/GM the pixel multiplier is in the sdvo 3418 * port and will be fixed up in the encoder->get_config 3419 * function. */ 3420 pipe_config->pixel_multiplier = 1; 3421 } 3422 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv, 3423 DPLL(crtc->pipe)); 3424 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 3425 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv, 3426 FP0(crtc->pipe)); 3427 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv, 3428 FP1(crtc->pipe)); 3429 } else { 3430 /* Mask out read-only status bits. */ 3431 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | 3432 DPLL_PORTC_READY_MASK | 3433 DPLL_PORTB_READY_MASK); 3434 } 3435 3436 if (IS_CHERRYVIEW(dev_priv)) 3437 chv_crtc_clock_get(crtc, pipe_config); 3438 else if (IS_VALLEYVIEW(dev_priv)) 3439 vlv_crtc_clock_get(crtc, pipe_config); 3440 else 3441 i9xx_crtc_clock_get(crtc, pipe_config); 3442 3443 /* 3444 * Normally the dotclock is filled in by the encoder .get_config() 3445 * but in case the pipe is enabled w/o any ports we need a sane 3446 * default. 3447 */ 3448 pipe_config->hw.adjusted_mode.crtc_clock = 3449 pipe_config->port_clock / pipe_config->pixel_multiplier; 3450 3451 ret = true; 3452 3453 out: 3454 intel_display_power_put(dev_priv, power_domain, wakeref); 3455 3456 return ret; 3457 } 3458 3459 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) 3460 { 3461 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3462 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3463 enum pipe pipe = crtc->pipe; 3464 u32 val; 3465 3466 val = 0; 3467 3468 switch (crtc_state->pipe_bpp) { 3469 case 18: 3470 val |= PIPECONF_BPC_6; 3471 break; 3472 case 24: 3473 val |= PIPECONF_BPC_8; 3474 break; 3475 case 30: 3476 val |= PIPECONF_BPC_10; 3477 break; 3478 case 36: 3479 val |= PIPECONF_BPC_12; 3480 break; 3481 default: 3482 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3483 BUG(); 3484 } 3485 3486 if (crtc_state->dither) 3487 val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP; 3488 3489 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3490 val |= PIPECONF_INTERLACE_IF_ID_ILK; 3491 else 3492 val |= PIPECONF_INTERLACE_PF_PD_ILK; 3493 3494 /* 3495 * This would end up with an odd purple hue over 3496 * the entire display. Make sure we don't do it. 3497 */ 3498 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 3499 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 3500 3501 if (crtc_state->limited_color_range && 3502 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3503 val |= PIPECONF_COLOR_RANGE_SELECT; 3504 3505 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3506 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709; 3507 3508 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); 3509 3510 val |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3511 val |= PIPECONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay); 3512 3513 intel_de_write(dev_priv, PIPECONF(pipe), val); 3514 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 3515 } 3516 3517 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) 3518 { 3519 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3520 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3521 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3522 u32 val = 0; 3523 3524 if (IS_HASWELL(dev_priv) && crtc_state->dither) 3525 val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP; 3526 3527 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3528 val |= PIPECONF_INTERLACE_IF_ID_ILK; 3529 else 3530 val |= PIPECONF_INTERLACE_PF_PD_ILK; 3531 3532 if (IS_HASWELL(dev_priv) && 3533 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3534 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW; 3535 3536 intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val); 3537 intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder)); 3538 } 3539 3540 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) 3541 { 3542 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3543 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3544 u32 val = 0; 3545 3546 switch (crtc_state->pipe_bpp) { 3547 case 18: 3548 val |= PIPEMISC_BPC_6; 3549 break; 3550 case 24: 3551 val |= PIPEMISC_BPC_8; 3552 break; 3553 case 30: 3554 val |= PIPEMISC_BPC_10; 3555 break; 3556 case 36: 3557 /* Port output 12BPC defined for ADLP+ */ 3558 if (DISPLAY_VER(dev_priv) > 12) 3559 val |= PIPEMISC_BPC_12_ADLP; 3560 break; 3561 default: 3562 MISSING_CASE(crtc_state->pipe_bpp); 3563 break; 3564 } 3565 3566 if (crtc_state->dither) 3567 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; 3568 3569 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 3570 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 3571 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV; 3572 3573 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 3574 val |= PIPEMISC_YUV420_ENABLE | 3575 PIPEMISC_YUV420_MODE_FULL_BLEND; 3576 3577 if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state)) 3578 val |= PIPEMISC_HDR_MODE_PRECISION; 3579 3580 if (DISPLAY_VER(dev_priv) >= 12) 3581 val |= PIPEMISC_PIXEL_ROUNDING_TRUNC; 3582 3583 intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val); 3584 } 3585 3586 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) 3587 { 3588 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3589 u32 tmp; 3590 3591 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); 3592 3593 switch (tmp & PIPEMISC_BPC_MASK) { 3594 case PIPEMISC_BPC_6: 3595 return 18; 3596 case PIPEMISC_BPC_8: 3597 return 24; 3598 case PIPEMISC_BPC_10: 3599 return 30; 3600 /* 3601 * PORT OUTPUT 12 BPC defined for ADLP+. 3602 * 3603 * TODO: 3604 * For previous platforms with DSI interface, bits 5:7 3605 * are used for storing pipe_bpp irrespective of dithering. 3606 * Since the value of 12 BPC is not defined for these bits 3607 * on older platforms, need to find a workaround for 12 BPC 3608 * MIPI DSI HW readout. 3609 */ 3610 case PIPEMISC_BPC_12_ADLP: 3611 if (DISPLAY_VER(dev_priv) > 12) 3612 return 36; 3613 fallthrough; 3614 default: 3615 MISSING_CASE(tmp); 3616 return 0; 3617 } 3618 } 3619 3620 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) 3621 { 3622 /* 3623 * Account for spread spectrum to avoid 3624 * oversubscribing the link. Max center spread 3625 * is 2.5%; use 5% for safety's sake. 3626 */ 3627 u32 bps = target_clock * bpp * 21 / 20; 3628 return DIV_ROUND_UP(bps, link_bw * 8); 3629 } 3630 3631 void intel_get_m_n(struct drm_i915_private *i915, 3632 struct intel_link_m_n *m_n, 3633 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 3634 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 3635 { 3636 m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK; 3637 m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK; 3638 m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK; 3639 m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK; 3640 m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1; 3641 } 3642 3643 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, 3644 enum transcoder transcoder, 3645 struct intel_link_m_n *m_n) 3646 { 3647 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3648 enum pipe pipe = crtc->pipe; 3649 3650 if (DISPLAY_VER(dev_priv) >= 5) 3651 intel_get_m_n(dev_priv, m_n, 3652 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 3653 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 3654 else 3655 intel_get_m_n(dev_priv, m_n, 3656 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 3657 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 3658 } 3659 3660 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, 3661 enum transcoder transcoder, 3662 struct intel_link_m_n *m_n) 3663 { 3664 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3665 3666 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 3667 return; 3668 3669 intel_get_m_n(dev_priv, m_n, 3670 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 3671 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 3672 } 3673 3674 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state, 3675 u32 pos, u32 size) 3676 { 3677 drm_rect_init(&crtc_state->pch_pfit.dst, 3678 pos >> 16, pos & 0xffff, 3679 size >> 16, size & 0xffff); 3680 } 3681 3682 static void skl_get_pfit_config(struct intel_crtc_state *crtc_state) 3683 { 3684 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3685 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3686 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; 3687 int id = -1; 3688 int i; 3689 3690 /* find scaler attached to this pipe */ 3691 for (i = 0; i < crtc->num_scalers; i++) { 3692 u32 ctl, pos, size; 3693 3694 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i)); 3695 if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN) 3696 continue; 3697 3698 id = i; 3699 crtc_state->pch_pfit.enabled = true; 3700 3701 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i)); 3702 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i)); 3703 3704 ilk_get_pfit_pos_size(crtc_state, pos, size); 3705 3706 scaler_state->scalers[i].in_use = true; 3707 break; 3708 } 3709 3710 scaler_state->scaler_id = id; 3711 if (id >= 0) 3712 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); 3713 else 3714 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); 3715 } 3716 3717 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state) 3718 { 3719 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3720 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3721 u32 ctl, pos, size; 3722 3723 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe)); 3724 if ((ctl & PF_ENABLE) == 0) 3725 return; 3726 3727 crtc_state->pch_pfit.enabled = true; 3728 3729 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe)); 3730 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe)); 3731 3732 ilk_get_pfit_pos_size(crtc_state, pos, size); 3733 3734 /* 3735 * We currently do not free assignements of panel fitters on 3736 * ivb/hsw (since we don't use the higher upscaling modes which 3737 * differentiates them) so just WARN about this case for now. 3738 */ 3739 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 7 && 3740 (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe)); 3741 } 3742 3743 static bool ilk_get_pipe_config(struct intel_crtc *crtc, 3744 struct intel_crtc_state *pipe_config) 3745 { 3746 struct drm_device *dev = crtc->base.dev; 3747 struct drm_i915_private *dev_priv = to_i915(dev); 3748 enum intel_display_power_domain power_domain; 3749 intel_wakeref_t wakeref; 3750 u32 tmp; 3751 bool ret; 3752 3753 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3754 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3755 if (!wakeref) 3756 return false; 3757 3758 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3759 pipe_config->shared_dpll = NULL; 3760 3761 ret = false; 3762 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); 3763 if (!(tmp & PIPECONF_ENABLE)) 3764 goto out; 3765 3766 switch (tmp & PIPECONF_BPC_MASK) { 3767 case PIPECONF_BPC_6: 3768 pipe_config->pipe_bpp = 18; 3769 break; 3770 case PIPECONF_BPC_8: 3771 pipe_config->pipe_bpp = 24; 3772 break; 3773 case PIPECONF_BPC_10: 3774 pipe_config->pipe_bpp = 30; 3775 break; 3776 case PIPECONF_BPC_12: 3777 pipe_config->pipe_bpp = 36; 3778 break; 3779 default: 3780 break; 3781 } 3782 3783 if (tmp & PIPECONF_COLOR_RANGE_SELECT) 3784 pipe_config->limited_color_range = true; 3785 3786 switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) { 3787 case PIPECONF_OUTPUT_COLORSPACE_YUV601: 3788 case PIPECONF_OUTPUT_COLORSPACE_YUV709: 3789 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3790 break; 3791 default: 3792 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3793 break; 3794 } 3795 3796 pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_ILK, tmp); 3797 3798 pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1; 3799 3800 pipe_config->msa_timing_delay = REG_FIELD_GET(PIPECONF_MSA_TIMING_DELAY_MASK, tmp); 3801 3802 pipe_config->csc_mode = intel_de_read(dev_priv, 3803 PIPE_CSC_MODE(crtc->pipe)); 3804 3805 i9xx_get_pipe_color_config(pipe_config); 3806 intel_color_get_config(pipe_config); 3807 3808 pipe_config->pixel_multiplier = 1; 3809 3810 ilk_pch_get_config(pipe_config); 3811 3812 intel_get_transcoder_timings(crtc, pipe_config); 3813 intel_get_pipe_src_size(crtc, pipe_config); 3814 3815 ilk_get_pfit_config(pipe_config); 3816 3817 ret = true; 3818 3819 out: 3820 intel_display_power_put(dev_priv, power_domain, wakeref); 3821 3822 return ret; 3823 } 3824 3825 static u8 bigjoiner_pipes(struct drm_i915_private *i915) 3826 { 3827 if (DISPLAY_VER(i915) >= 12) 3828 return BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D); 3829 else if (DISPLAY_VER(i915) >= 11) 3830 return BIT(PIPE_B) | BIT(PIPE_C); 3831 else 3832 return 0; 3833 } 3834 3835 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv, 3836 enum transcoder cpu_transcoder) 3837 { 3838 enum intel_display_power_domain power_domain; 3839 intel_wakeref_t wakeref; 3840 u32 tmp = 0; 3841 3842 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3843 3844 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3845 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3846 3847 return tmp & TRANS_DDI_FUNC_ENABLE; 3848 } 3849 3850 static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv, 3851 u8 *master_pipes, u8 *slave_pipes) 3852 { 3853 struct intel_crtc *crtc; 3854 3855 *master_pipes = 0; 3856 *slave_pipes = 0; 3857 3858 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, 3859 bigjoiner_pipes(dev_priv)) { 3860 enum intel_display_power_domain power_domain; 3861 enum pipe pipe = crtc->pipe; 3862 intel_wakeref_t wakeref; 3863 3864 power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe); 3865 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3866 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3867 3868 if (!(tmp & BIG_JOINER_ENABLE)) 3869 continue; 3870 3871 if (tmp & MASTER_BIG_JOINER_ENABLE) 3872 *master_pipes |= BIT(pipe); 3873 else 3874 *slave_pipes |= BIT(pipe); 3875 } 3876 3877 if (DISPLAY_VER(dev_priv) < 13) 3878 continue; 3879 3880 power_domain = POWER_DOMAIN_PIPE(pipe); 3881 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3882 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3883 3884 if (tmp & UNCOMPRESSED_JOINER_MASTER) 3885 *master_pipes |= BIT(pipe); 3886 if (tmp & UNCOMPRESSED_JOINER_SLAVE) 3887 *slave_pipes |= BIT(pipe); 3888 } 3889 } 3890 3891 /* Bigjoiner pipes should always be consecutive master and slave */ 3892 drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1, 3893 "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n", 3894 *master_pipes, *slave_pipes); 3895 } 3896 3897 static enum pipe get_bigjoiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3898 { 3899 if ((slave_pipes & BIT(pipe)) == 0) 3900 return pipe; 3901 3902 /* ignore everything above our pipe */ 3903 master_pipes &= ~GENMASK(7, pipe); 3904 3905 /* highest remaining bit should be our master pipe */ 3906 return fls(master_pipes) - 1; 3907 } 3908 3909 static u8 get_bigjoiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3910 { 3911 enum pipe master_pipe, next_master_pipe; 3912 3913 master_pipe = get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes); 3914 3915 if ((master_pipes & BIT(master_pipe)) == 0) 3916 return 0; 3917 3918 /* ignore our master pipe and everything below it */ 3919 master_pipes &= ~GENMASK(master_pipe, 0); 3920 /* make sure a high bit is set for the ffs() */ 3921 master_pipes |= BIT(7); 3922 /* lowest remaining bit should be the next master pipe */ 3923 next_master_pipe = ffs(master_pipes) - 1; 3924 3925 return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe); 3926 } 3927 3928 static u8 hsw_panel_transcoders(struct drm_i915_private *i915) 3929 { 3930 u8 panel_transcoder_mask = BIT(TRANSCODER_EDP); 3931 3932 if (DISPLAY_VER(i915) >= 11) 3933 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); 3934 3935 return panel_transcoder_mask; 3936 } 3937 3938 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) 3939 { 3940 struct drm_device *dev = crtc->base.dev; 3941 struct drm_i915_private *dev_priv = to_i915(dev); 3942 u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv); 3943 enum transcoder cpu_transcoder; 3944 u8 master_pipes, slave_pipes; 3945 u8 enabled_transcoders = 0; 3946 3947 /* 3948 * XXX: Do intel_display_power_get_if_enabled before reading this (for 3949 * consistency and less surprising code; it's in always on power). 3950 */ 3951 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, 3952 panel_transcoder_mask) { 3953 enum intel_display_power_domain power_domain; 3954 intel_wakeref_t wakeref; 3955 enum pipe trans_pipe; 3956 u32 tmp = 0; 3957 3958 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3959 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3960 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3961 3962 if (!(tmp & TRANS_DDI_FUNC_ENABLE)) 3963 continue; 3964 3965 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 3966 default: 3967 drm_WARN(dev, 1, 3968 "unknown pipe linked to transcoder %s\n", 3969 transcoder_name(cpu_transcoder)); 3970 fallthrough; 3971 case TRANS_DDI_EDP_INPUT_A_ONOFF: 3972 case TRANS_DDI_EDP_INPUT_A_ON: 3973 trans_pipe = PIPE_A; 3974 break; 3975 case TRANS_DDI_EDP_INPUT_B_ONOFF: 3976 trans_pipe = PIPE_B; 3977 break; 3978 case TRANS_DDI_EDP_INPUT_C_ONOFF: 3979 trans_pipe = PIPE_C; 3980 break; 3981 case TRANS_DDI_EDP_INPUT_D_ONOFF: 3982 trans_pipe = PIPE_D; 3983 break; 3984 } 3985 3986 if (trans_pipe == crtc->pipe) 3987 enabled_transcoders |= BIT(cpu_transcoder); 3988 } 3989 3990 /* single pipe or bigjoiner master */ 3991 cpu_transcoder = (enum transcoder) crtc->pipe; 3992 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 3993 enabled_transcoders |= BIT(cpu_transcoder); 3994 3995 /* bigjoiner slave -> consider the master pipe's transcoder as well */ 3996 enabled_bigjoiner_pipes(dev_priv, &master_pipes, &slave_pipes); 3997 if (slave_pipes & BIT(crtc->pipe)) { 3998 cpu_transcoder = (enum transcoder) 3999 get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes); 4000 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 4001 enabled_transcoders |= BIT(cpu_transcoder); 4002 } 4003 4004 return enabled_transcoders; 4005 } 4006 4007 static bool has_edp_transcoders(u8 enabled_transcoders) 4008 { 4009 return enabled_transcoders & BIT(TRANSCODER_EDP); 4010 } 4011 4012 static bool has_dsi_transcoders(u8 enabled_transcoders) 4013 { 4014 return enabled_transcoders & (BIT(TRANSCODER_DSI_0) | 4015 BIT(TRANSCODER_DSI_1)); 4016 } 4017 4018 static bool has_pipe_transcoders(u8 enabled_transcoders) 4019 { 4020 return enabled_transcoders & ~(BIT(TRANSCODER_EDP) | 4021 BIT(TRANSCODER_DSI_0) | 4022 BIT(TRANSCODER_DSI_1)); 4023 } 4024 4025 static void assert_enabled_transcoders(struct drm_i915_private *i915, 4026 u8 enabled_transcoders) 4027 { 4028 /* Only one type of transcoder please */ 4029 drm_WARN_ON(&i915->drm, 4030 has_edp_transcoders(enabled_transcoders) + 4031 has_dsi_transcoders(enabled_transcoders) + 4032 has_pipe_transcoders(enabled_transcoders) > 1); 4033 4034 /* Only DSI transcoders can be ganged */ 4035 drm_WARN_ON(&i915->drm, 4036 !has_dsi_transcoders(enabled_transcoders) && 4037 !is_power_of_2(enabled_transcoders)); 4038 } 4039 4040 static bool hsw_get_transcoder_state(struct intel_crtc *crtc, 4041 struct intel_crtc_state *pipe_config, 4042 struct intel_display_power_domain_set *power_domain_set) 4043 { 4044 struct drm_device *dev = crtc->base.dev; 4045 struct drm_i915_private *dev_priv = to_i915(dev); 4046 unsigned long enabled_transcoders; 4047 u32 tmp; 4048 4049 enabled_transcoders = hsw_enabled_transcoders(crtc); 4050 if (!enabled_transcoders) 4051 return false; 4052 4053 assert_enabled_transcoders(dev_priv, enabled_transcoders); 4054 4055 /* 4056 * With the exception of DSI we should only ever have 4057 * a single enabled transcoder. With DSI let's just 4058 * pick the first one. 4059 */ 4060 pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1; 4061 4062 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 4063 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) 4064 return false; 4065 4066 if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) { 4067 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); 4068 4069 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF) 4070 pipe_config->pch_pfit.force_thru = true; 4071 } 4072 4073 tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder)); 4074 4075 return tmp & PIPECONF_ENABLE; 4076 } 4077 4078 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, 4079 struct intel_crtc_state *pipe_config, 4080 struct intel_display_power_domain_set *power_domain_set) 4081 { 4082 struct drm_device *dev = crtc->base.dev; 4083 struct drm_i915_private *dev_priv = to_i915(dev); 4084 enum transcoder cpu_transcoder; 4085 enum port port; 4086 u32 tmp; 4087 4088 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { 4089 if (port == PORT_A) 4090 cpu_transcoder = TRANSCODER_DSI_A; 4091 else 4092 cpu_transcoder = TRANSCODER_DSI_C; 4093 4094 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 4095 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) 4096 continue; 4097 4098 /* 4099 * The PLL needs to be enabled with a valid divider 4100 * configuration, otherwise accessing DSI registers will hang 4101 * the machine. See BSpec North Display Engine 4102 * registers/MIPI[BXT]. We can break out here early, since we 4103 * need the same DSI PLL to be enabled for both DSI ports. 4104 */ 4105 if (!bxt_dsi_pll_is_enabled(dev_priv)) 4106 break; 4107 4108 /* XXX: this works for video mode only */ 4109 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); 4110 if (!(tmp & DPI_ENABLE)) 4111 continue; 4112 4113 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 4114 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) 4115 continue; 4116 4117 pipe_config->cpu_transcoder = cpu_transcoder; 4118 break; 4119 } 4120 4121 return transcoder_is_dsi(pipe_config->cpu_transcoder); 4122 } 4123 4124 static void intel_bigjoiner_get_config(struct intel_crtc_state *crtc_state) 4125 { 4126 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4127 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4128 u8 master_pipes, slave_pipes; 4129 enum pipe pipe = crtc->pipe; 4130 4131 enabled_bigjoiner_pipes(i915, &master_pipes, &slave_pipes); 4132 4133 if (((master_pipes | slave_pipes) & BIT(pipe)) == 0) 4134 return; 4135 4136 crtc_state->bigjoiner_pipes = 4137 BIT(get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes)) | 4138 get_bigjoiner_slave_pipes(pipe, master_pipes, slave_pipes); 4139 } 4140 4141 static bool hsw_get_pipe_config(struct intel_crtc *crtc, 4142 struct intel_crtc_state *pipe_config) 4143 { 4144 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4145 struct intel_display_power_domain_set power_domain_set = { }; 4146 bool active; 4147 u32 tmp; 4148 4149 if (!intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set, 4150 POWER_DOMAIN_PIPE(crtc->pipe))) 4151 return false; 4152 4153 pipe_config->shared_dpll = NULL; 4154 4155 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_set); 4156 4157 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 4158 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_set)) { 4159 drm_WARN_ON(&dev_priv->drm, active); 4160 active = true; 4161 } 4162 4163 if (!active) 4164 goto out; 4165 4166 intel_dsc_get_config(pipe_config); 4167 intel_bigjoiner_get_config(pipe_config); 4168 4169 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || 4170 DISPLAY_VER(dev_priv) >= 11) 4171 intel_get_transcoder_timings(crtc, pipe_config); 4172 4173 if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder)) 4174 intel_vrr_get_config(crtc, pipe_config); 4175 4176 intel_get_pipe_src_size(crtc, pipe_config); 4177 4178 if (IS_HASWELL(dev_priv)) { 4179 u32 tmp = intel_de_read(dev_priv, 4180 PIPECONF(pipe_config->cpu_transcoder)); 4181 4182 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW) 4183 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 4184 else 4185 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 4186 } else { 4187 pipe_config->output_format = 4188 bdw_get_pipemisc_output_format(crtc); 4189 } 4190 4191 pipe_config->gamma_mode = intel_de_read(dev_priv, 4192 GAMMA_MODE(crtc->pipe)); 4193 4194 pipe_config->csc_mode = intel_de_read(dev_priv, 4195 PIPE_CSC_MODE(crtc->pipe)); 4196 4197 if (DISPLAY_VER(dev_priv) >= 9) { 4198 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe)); 4199 4200 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE) 4201 pipe_config->gamma_enable = true; 4202 4203 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE) 4204 pipe_config->csc_enable = true; 4205 } else { 4206 i9xx_get_pipe_color_config(pipe_config); 4207 } 4208 4209 intel_color_get_config(pipe_config); 4210 4211 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe)); 4212 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); 4213 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 4214 pipe_config->ips_linetime = 4215 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); 4216 4217 if (intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set, 4218 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) { 4219 if (DISPLAY_VER(dev_priv) >= 9) 4220 skl_get_pfit_config(pipe_config); 4221 else 4222 ilk_get_pfit_config(pipe_config); 4223 } 4224 4225 hsw_ips_get_config(pipe_config); 4226 4227 if (pipe_config->cpu_transcoder != TRANSCODER_EDP && 4228 !transcoder_is_dsi(pipe_config->cpu_transcoder)) { 4229 pipe_config->pixel_multiplier = 4230 intel_de_read(dev_priv, 4231 PIPE_MULT(pipe_config->cpu_transcoder)) + 1; 4232 } else { 4233 pipe_config->pixel_multiplier = 1; 4234 } 4235 4236 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { 4237 tmp = intel_de_read(dev_priv, CHICKEN_TRANS(pipe_config->cpu_transcoder)); 4238 4239 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1; 4240 } else { 4241 /* no idea if this is correct */ 4242 pipe_config->framestart_delay = 1; 4243 } 4244 4245 out: 4246 intel_display_power_put_all_in_set(dev_priv, &power_domain_set); 4247 4248 return active; 4249 } 4250 4251 static bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state) 4252 { 4253 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4254 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4255 4256 if (!i915->display->get_pipe_config(crtc, crtc_state)) 4257 return false; 4258 4259 crtc_state->hw.active = true; 4260 4261 intel_crtc_readout_derived_state(crtc_state); 4262 4263 return true; 4264 } 4265 4266 /* VESA 640x480x72Hz mode to set on the pipe */ 4267 static const struct drm_display_mode load_detect_mode = { 4268 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, 4269 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 4270 }; 4271 4272 static int intel_modeset_disable_planes(struct drm_atomic_state *state, 4273 struct drm_crtc *crtc) 4274 { 4275 struct drm_plane *plane; 4276 struct drm_plane_state *plane_state; 4277 int ret, i; 4278 4279 ret = drm_atomic_add_affected_planes(state, crtc); 4280 if (ret) 4281 return ret; 4282 4283 for_each_new_plane_in_state(state, plane, plane_state, i) { 4284 if (plane_state->crtc != crtc) 4285 continue; 4286 4287 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL); 4288 if (ret) 4289 return ret; 4290 4291 drm_atomic_set_fb_for_plane(plane_state, NULL); 4292 } 4293 4294 return 0; 4295 } 4296 4297 int intel_get_load_detect_pipe(struct drm_connector *connector, 4298 struct intel_load_detect_pipe *old, 4299 struct drm_modeset_acquire_ctx *ctx) 4300 { 4301 struct intel_encoder *encoder = 4302 intel_attached_encoder(to_intel_connector(connector)); 4303 struct intel_crtc *possible_crtc; 4304 struct intel_crtc *crtc = NULL; 4305 struct drm_device *dev = encoder->base.dev; 4306 struct drm_i915_private *dev_priv = to_i915(dev); 4307 struct drm_mode_config *config = &dev->mode_config; 4308 struct drm_atomic_state *state = NULL, *restore_state = NULL; 4309 struct drm_connector_state *connector_state; 4310 struct intel_crtc_state *crtc_state; 4311 int ret; 4312 4313 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 4314 connector->base.id, connector->name, 4315 encoder->base.base.id, encoder->base.name); 4316 4317 old->restore_state = NULL; 4318 4319 drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex)); 4320 4321 /* 4322 * Algorithm gets a little messy: 4323 * 4324 * - if the connector already has an assigned crtc, use it (but make 4325 * sure it's on first) 4326 * 4327 * - try to find the first unused crtc that can drive this connector, 4328 * and use that if we find one 4329 */ 4330 4331 /* See if we already have a CRTC for this connector */ 4332 if (connector->state->crtc) { 4333 crtc = to_intel_crtc(connector->state->crtc); 4334 4335 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4336 if (ret) 4337 goto fail; 4338 4339 /* Make sure the crtc and connector are running */ 4340 goto found; 4341 } 4342 4343 /* Find an unused one (if possible) */ 4344 for_each_intel_crtc(dev, possible_crtc) { 4345 if (!(encoder->base.possible_crtcs & 4346 drm_crtc_mask(&possible_crtc->base))) 4347 continue; 4348 4349 ret = drm_modeset_lock(&possible_crtc->base.mutex, ctx); 4350 if (ret) 4351 goto fail; 4352 4353 if (possible_crtc->base.state->enable) { 4354 drm_modeset_unlock(&possible_crtc->base.mutex); 4355 continue; 4356 } 4357 4358 crtc = possible_crtc; 4359 break; 4360 } 4361 4362 /* 4363 * If we didn't find an unused CRTC, don't use any. 4364 */ 4365 if (!crtc) { 4366 drm_dbg_kms(&dev_priv->drm, 4367 "no pipe available for load-detect\n"); 4368 ret = -ENODEV; 4369 goto fail; 4370 } 4371 4372 found: 4373 state = drm_atomic_state_alloc(dev); 4374 restore_state = drm_atomic_state_alloc(dev); 4375 if (!state || !restore_state) { 4376 ret = -ENOMEM; 4377 goto fail; 4378 } 4379 4380 state->acquire_ctx = ctx; 4381 restore_state->acquire_ctx = ctx; 4382 4383 connector_state = drm_atomic_get_connector_state(state, connector); 4384 if (IS_ERR(connector_state)) { 4385 ret = PTR_ERR(connector_state); 4386 goto fail; 4387 } 4388 4389 ret = drm_atomic_set_crtc_for_connector(connector_state, &crtc->base); 4390 if (ret) 4391 goto fail; 4392 4393 crtc_state = intel_atomic_get_crtc_state(state, crtc); 4394 if (IS_ERR(crtc_state)) { 4395 ret = PTR_ERR(crtc_state); 4396 goto fail; 4397 } 4398 4399 crtc_state->uapi.active = true; 4400 4401 ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi, 4402 &load_detect_mode); 4403 if (ret) 4404 goto fail; 4405 4406 ret = intel_modeset_disable_planes(state, &crtc->base); 4407 if (ret) 4408 goto fail; 4409 4410 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); 4411 if (!ret) 4412 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, &crtc->base)); 4413 if (!ret) 4414 ret = drm_atomic_add_affected_planes(restore_state, &crtc->base); 4415 if (ret) { 4416 drm_dbg_kms(&dev_priv->drm, 4417 "Failed to create a copy of old state to restore: %i\n", 4418 ret); 4419 goto fail; 4420 } 4421 4422 ret = drm_atomic_commit(state); 4423 if (ret) { 4424 drm_dbg_kms(&dev_priv->drm, 4425 "failed to set mode on load-detect pipe\n"); 4426 goto fail; 4427 } 4428 4429 old->restore_state = restore_state; 4430 drm_atomic_state_put(state); 4431 4432 /* let the connector get through one full cycle before testing */ 4433 intel_crtc_wait_for_next_vblank(crtc); 4434 4435 return true; 4436 4437 fail: 4438 if (state) { 4439 drm_atomic_state_put(state); 4440 state = NULL; 4441 } 4442 if (restore_state) { 4443 drm_atomic_state_put(restore_state); 4444 restore_state = NULL; 4445 } 4446 4447 if (ret == -EDEADLK) 4448 return ret; 4449 4450 return false; 4451 } 4452 4453 void intel_release_load_detect_pipe(struct drm_connector *connector, 4454 struct intel_load_detect_pipe *old, 4455 struct drm_modeset_acquire_ctx *ctx) 4456 { 4457 struct intel_encoder *intel_encoder = 4458 intel_attached_encoder(to_intel_connector(connector)); 4459 struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev); 4460 struct drm_encoder *encoder = &intel_encoder->base; 4461 struct drm_atomic_state *state = old->restore_state; 4462 int ret; 4463 4464 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 4465 connector->base.id, connector->name, 4466 encoder->base.id, encoder->name); 4467 4468 if (!state) 4469 return; 4470 4471 ret = drm_atomic_helper_commit_duplicated_state(state, ctx); 4472 if (ret) 4473 drm_dbg_kms(&i915->drm, 4474 "Couldn't release load detect pipe: %i\n", ret); 4475 drm_atomic_state_put(state); 4476 } 4477 4478 static int i9xx_pll_refclk(struct drm_device *dev, 4479 const struct intel_crtc_state *pipe_config) 4480 { 4481 struct drm_i915_private *dev_priv = to_i915(dev); 4482 u32 dpll = pipe_config->dpll_hw_state.dpll; 4483 4484 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) 4485 return dev_priv->vbt.lvds_ssc_freq; 4486 else if (HAS_PCH_SPLIT(dev_priv)) 4487 return 120000; 4488 else if (DISPLAY_VER(dev_priv) != 2) 4489 return 96000; 4490 else 4491 return 48000; 4492 } 4493 4494 /* Returns the clock of the currently programmed mode of the given pipe. */ 4495 void i9xx_crtc_clock_get(struct intel_crtc *crtc, 4496 struct intel_crtc_state *pipe_config) 4497 { 4498 struct drm_device *dev = crtc->base.dev; 4499 struct drm_i915_private *dev_priv = to_i915(dev); 4500 u32 dpll = pipe_config->dpll_hw_state.dpll; 4501 u32 fp; 4502 struct dpll clock; 4503 int port_clock; 4504 int refclk = i9xx_pll_refclk(dev, pipe_config); 4505 4506 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 4507 fp = pipe_config->dpll_hw_state.fp0; 4508 else 4509 fp = pipe_config->dpll_hw_state.fp1; 4510 4511 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 4512 if (IS_PINEVIEW(dev_priv)) { 4513 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; 4514 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; 4515 } else { 4516 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 4517 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 4518 } 4519 4520 if (DISPLAY_VER(dev_priv) != 2) { 4521 if (IS_PINEVIEW(dev_priv)) 4522 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> 4523 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); 4524 else 4525 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> 4526 DPLL_FPA01_P1_POST_DIV_SHIFT); 4527 4528 switch (dpll & DPLL_MODE_MASK) { 4529 case DPLLB_MODE_DAC_SERIAL: 4530 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 4531 5 : 10; 4532 break; 4533 case DPLLB_MODE_LVDS: 4534 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 4535 7 : 14; 4536 break; 4537 default: 4538 drm_dbg_kms(&dev_priv->drm, 4539 "Unknown DPLL mode %08x in programmed " 4540 "mode\n", (int)(dpll & DPLL_MODE_MASK)); 4541 return; 4542 } 4543 4544 if (IS_PINEVIEW(dev_priv)) 4545 port_clock = pnv_calc_dpll_params(refclk, &clock); 4546 else 4547 port_clock = i9xx_calc_dpll_params(refclk, &clock); 4548 } else { 4549 enum pipe lvds_pipe; 4550 4551 if (IS_I85X(dev_priv) && 4552 intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) && 4553 lvds_pipe == crtc->pipe) { 4554 u32 lvds = intel_de_read(dev_priv, LVDS); 4555 4556 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 4557 DPLL_FPA01_P1_POST_DIV_SHIFT); 4558 4559 if (lvds & LVDS_CLKB_POWER_UP) 4560 clock.p2 = 7; 4561 else 4562 clock.p2 = 14; 4563 } else { 4564 if (dpll & PLL_P1_DIVIDE_BY_TWO) 4565 clock.p1 = 2; 4566 else { 4567 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 4568 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 4569 } 4570 if (dpll & PLL_P2_DIVIDE_BY_4) 4571 clock.p2 = 4; 4572 else 4573 clock.p2 = 2; 4574 } 4575 4576 port_clock = i9xx_calc_dpll_params(refclk, &clock); 4577 } 4578 4579 /* 4580 * This value includes pixel_multiplier. We will use 4581 * port_clock to compute adjusted_mode.crtc_clock in the 4582 * encoder's get_config() function. 4583 */ 4584 pipe_config->port_clock = port_clock; 4585 } 4586 4587 int intel_dotclock_calculate(int link_freq, 4588 const struct intel_link_m_n *m_n) 4589 { 4590 /* 4591 * The calculation for the data clock is: 4592 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp 4593 * But we want to avoid losing precison if possible, so: 4594 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) 4595 * 4596 * and the link clock is simpler: 4597 * link_clock = (m * link_clock) / n 4598 */ 4599 4600 if (!m_n->link_n) 4601 return 0; 4602 4603 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n); 4604 } 4605 4606 /* Returns the currently programmed mode of the given encoder. */ 4607 struct drm_display_mode * 4608 intel_encoder_current_mode(struct intel_encoder *encoder) 4609 { 4610 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4611 struct intel_crtc_state *crtc_state; 4612 struct drm_display_mode *mode; 4613 struct intel_crtc *crtc; 4614 enum pipe pipe; 4615 4616 if (!encoder->get_hw_state(encoder, &pipe)) 4617 return NULL; 4618 4619 crtc = intel_crtc_for_pipe(dev_priv, pipe); 4620 4621 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 4622 if (!mode) 4623 return NULL; 4624 4625 crtc_state = intel_crtc_state_alloc(crtc); 4626 if (!crtc_state) { 4627 kfree(mode); 4628 return NULL; 4629 } 4630 4631 if (!intel_crtc_get_pipe_config(crtc_state)) { 4632 kfree(crtc_state); 4633 kfree(mode); 4634 return NULL; 4635 } 4636 4637 intel_encoder_get_config(encoder, crtc_state); 4638 4639 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode); 4640 4641 kfree(crtc_state); 4642 4643 return mode; 4644 } 4645 4646 static bool encoders_cloneable(const struct intel_encoder *a, 4647 const struct intel_encoder *b) 4648 { 4649 /* masks could be asymmetric, so check both ways */ 4650 return a == b || (a->cloneable & (1 << b->type) && 4651 b->cloneable & (1 << a->type)); 4652 } 4653 4654 static bool check_single_encoder_cloning(struct intel_atomic_state *state, 4655 struct intel_crtc *crtc, 4656 struct intel_encoder *encoder) 4657 { 4658 struct intel_encoder *source_encoder; 4659 struct drm_connector *connector; 4660 struct drm_connector_state *connector_state; 4661 int i; 4662 4663 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4664 if (connector_state->crtc != &crtc->base) 4665 continue; 4666 4667 source_encoder = 4668 to_intel_encoder(connector_state->best_encoder); 4669 if (!encoders_cloneable(encoder, source_encoder)) 4670 return false; 4671 } 4672 4673 return true; 4674 } 4675 4676 static int icl_add_linked_planes(struct intel_atomic_state *state) 4677 { 4678 struct intel_plane *plane, *linked; 4679 struct intel_plane_state *plane_state, *linked_plane_state; 4680 int i; 4681 4682 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4683 linked = plane_state->planar_linked_plane; 4684 4685 if (!linked) 4686 continue; 4687 4688 linked_plane_state = intel_atomic_get_plane_state(state, linked); 4689 if (IS_ERR(linked_plane_state)) 4690 return PTR_ERR(linked_plane_state); 4691 4692 drm_WARN_ON(state->base.dev, 4693 linked_plane_state->planar_linked_plane != plane); 4694 drm_WARN_ON(state->base.dev, 4695 linked_plane_state->planar_slave == plane_state->planar_slave); 4696 } 4697 4698 return 0; 4699 } 4700 4701 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state) 4702 { 4703 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4704 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4705 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 4706 struct intel_plane *plane, *linked; 4707 struct intel_plane_state *plane_state; 4708 int i; 4709 4710 if (DISPLAY_VER(dev_priv) < 11) 4711 return 0; 4712 4713 /* 4714 * Destroy all old plane links and make the slave plane invisible 4715 * in the crtc_state->active_planes mask. 4716 */ 4717 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4718 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane) 4719 continue; 4720 4721 plane_state->planar_linked_plane = NULL; 4722 if (plane_state->planar_slave && !plane_state->uapi.visible) { 4723 crtc_state->enabled_planes &= ~BIT(plane->id); 4724 crtc_state->active_planes &= ~BIT(plane->id); 4725 crtc_state->update_planes |= BIT(plane->id); 4726 crtc_state->data_rate[plane->id] = 0; 4727 crtc_state->rel_data_rate[plane->id] = 0; 4728 } 4729 4730 plane_state->planar_slave = false; 4731 } 4732 4733 if (!crtc_state->nv12_planes) 4734 return 0; 4735 4736 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4737 struct intel_plane_state *linked_state = NULL; 4738 4739 if (plane->pipe != crtc->pipe || 4740 !(crtc_state->nv12_planes & BIT(plane->id))) 4741 continue; 4742 4743 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) { 4744 if (!icl_is_nv12_y_plane(dev_priv, linked->id)) 4745 continue; 4746 4747 if (crtc_state->active_planes & BIT(linked->id)) 4748 continue; 4749 4750 linked_state = intel_atomic_get_plane_state(state, linked); 4751 if (IS_ERR(linked_state)) 4752 return PTR_ERR(linked_state); 4753 4754 break; 4755 } 4756 4757 if (!linked_state) { 4758 drm_dbg_kms(&dev_priv->drm, 4759 "Need %d free Y planes for planar YUV\n", 4760 hweight8(crtc_state->nv12_planes)); 4761 4762 return -EINVAL; 4763 } 4764 4765 plane_state->planar_linked_plane = linked; 4766 4767 linked_state->planar_slave = true; 4768 linked_state->planar_linked_plane = plane; 4769 crtc_state->enabled_planes |= BIT(linked->id); 4770 crtc_state->active_planes |= BIT(linked->id); 4771 crtc_state->update_planes |= BIT(linked->id); 4772 crtc_state->data_rate[linked->id] = 4773 crtc_state->data_rate_y[plane->id]; 4774 crtc_state->rel_data_rate[linked->id] = 4775 crtc_state->rel_data_rate_y[plane->id]; 4776 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n", 4777 linked->base.name, plane->base.name); 4778 4779 /* Copy parameters to slave plane */ 4780 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE; 4781 linked_state->color_ctl = plane_state->color_ctl; 4782 linked_state->view = plane_state->view; 4783 linked_state->decrypt = plane_state->decrypt; 4784 4785 intel_plane_copy_hw_state(linked_state, plane_state); 4786 linked_state->uapi.src = plane_state->uapi.src; 4787 linked_state->uapi.dst = plane_state->uapi.dst; 4788 4789 if (icl_is_hdr_plane(dev_priv, plane->id)) { 4790 if (linked->id == PLANE_SPRITE5) 4791 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL; 4792 else if (linked->id == PLANE_SPRITE4) 4793 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL; 4794 else if (linked->id == PLANE_SPRITE3) 4795 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL; 4796 else if (linked->id == PLANE_SPRITE2) 4797 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL; 4798 else 4799 MISSING_CASE(linked->id); 4800 } 4801 } 4802 4803 return 0; 4804 } 4805 4806 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state) 4807 { 4808 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 4809 struct intel_atomic_state *state = 4810 to_intel_atomic_state(new_crtc_state->uapi.state); 4811 const struct intel_crtc_state *old_crtc_state = 4812 intel_atomic_get_old_crtc_state(state, crtc); 4813 4814 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes; 4815 } 4816 4817 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) 4818 { 4819 const struct drm_display_mode *pipe_mode = 4820 &crtc_state->hw.pipe_mode; 4821 int linetime_wm; 4822 4823 if (!crtc_state->hw.enable) 4824 return 0; 4825 4826 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4827 pipe_mode->crtc_clock); 4828 4829 return min(linetime_wm, 0x1ff); 4830 } 4831 4832 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, 4833 const struct intel_cdclk_state *cdclk_state) 4834 { 4835 const struct drm_display_mode *pipe_mode = 4836 &crtc_state->hw.pipe_mode; 4837 int linetime_wm; 4838 4839 if (!crtc_state->hw.enable) 4840 return 0; 4841 4842 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4843 cdclk_state->logical.cdclk); 4844 4845 return min(linetime_wm, 0x1ff); 4846 } 4847 4848 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) 4849 { 4850 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4851 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4852 const struct drm_display_mode *pipe_mode = 4853 &crtc_state->hw.pipe_mode; 4854 int linetime_wm; 4855 4856 if (!crtc_state->hw.enable) 4857 return 0; 4858 4859 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8, 4860 crtc_state->pixel_rate); 4861 4862 /* Display WA #1135: BXT:ALL GLK:ALL */ 4863 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 4864 dev_priv->ipc_enabled) 4865 linetime_wm /= 2; 4866 4867 return min(linetime_wm, 0x1ff); 4868 } 4869 4870 static int hsw_compute_linetime_wm(struct intel_atomic_state *state, 4871 struct intel_crtc *crtc) 4872 { 4873 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4874 struct intel_crtc_state *crtc_state = 4875 intel_atomic_get_new_crtc_state(state, crtc); 4876 const struct intel_cdclk_state *cdclk_state; 4877 4878 if (DISPLAY_VER(dev_priv) >= 9) 4879 crtc_state->linetime = skl_linetime_wm(crtc_state); 4880 else 4881 crtc_state->linetime = hsw_linetime_wm(crtc_state); 4882 4883 if (!hsw_crtc_supports_ips(crtc)) 4884 return 0; 4885 4886 cdclk_state = intel_atomic_get_cdclk_state(state); 4887 if (IS_ERR(cdclk_state)) 4888 return PTR_ERR(cdclk_state); 4889 4890 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state, 4891 cdclk_state); 4892 4893 return 0; 4894 } 4895 4896 static int intel_crtc_atomic_check(struct intel_atomic_state *state, 4897 struct intel_crtc *crtc) 4898 { 4899 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4900 struct intel_crtc_state *crtc_state = 4901 intel_atomic_get_new_crtc_state(state, crtc); 4902 bool mode_changed = intel_crtc_needs_modeset(crtc_state); 4903 int ret; 4904 4905 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) && 4906 mode_changed && !crtc_state->hw.active) 4907 crtc_state->update_wm_post = true; 4908 4909 if (mode_changed) { 4910 ret = intel_dpll_crtc_compute_clock(state, crtc); 4911 if (ret) 4912 return ret; 4913 4914 ret = intel_dpll_crtc_get_shared_dpll(state, crtc); 4915 if (ret) 4916 return ret; 4917 } 4918 4919 /* 4920 * May need to update pipe gamma enable bits 4921 * when C8 planes are getting enabled/disabled. 4922 */ 4923 if (c8_planes_changed(crtc_state)) 4924 crtc_state->uapi.color_mgmt_changed = true; 4925 4926 if (mode_changed || crtc_state->update_pipe || 4927 crtc_state->uapi.color_mgmt_changed) { 4928 ret = intel_color_check(crtc_state); 4929 if (ret) 4930 return ret; 4931 } 4932 4933 ret = intel_compute_pipe_wm(state, crtc); 4934 if (ret) { 4935 drm_dbg_kms(&dev_priv->drm, 4936 "Target pipe watermarks are invalid\n"); 4937 return ret; 4938 } 4939 4940 /* 4941 * Calculate 'intermediate' watermarks that satisfy both the 4942 * old state and the new state. We can program these 4943 * immediately. 4944 */ 4945 ret = intel_compute_intermediate_wm(state, crtc); 4946 if (ret) { 4947 drm_dbg_kms(&dev_priv->drm, 4948 "No valid intermediate pipe watermarks are possible\n"); 4949 return ret; 4950 } 4951 4952 if (DISPLAY_VER(dev_priv) >= 9) { 4953 if (mode_changed || crtc_state->update_pipe) { 4954 ret = skl_update_scaler_crtc(crtc_state); 4955 if (ret) 4956 return ret; 4957 } 4958 4959 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state); 4960 if (ret) 4961 return ret; 4962 } 4963 4964 if (HAS_IPS(dev_priv)) { 4965 ret = hsw_ips_compute_config(state, crtc); 4966 if (ret) 4967 return ret; 4968 } 4969 4970 if (DISPLAY_VER(dev_priv) >= 9 || 4971 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 4972 ret = hsw_compute_linetime_wm(state, crtc); 4973 if (ret) 4974 return ret; 4975 4976 } 4977 4978 ret = intel_psr2_sel_fetch_update(state, crtc); 4979 if (ret) 4980 return ret; 4981 4982 return 0; 4983 } 4984 4985 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) 4986 { 4987 struct intel_connector *connector; 4988 struct drm_connector_list_iter conn_iter; 4989 4990 drm_connector_list_iter_begin(dev, &conn_iter); 4991 for_each_intel_connector_iter(connector, &conn_iter) { 4992 struct drm_connector_state *conn_state = connector->base.state; 4993 struct intel_encoder *encoder = 4994 to_intel_encoder(connector->base.encoder); 4995 4996 if (conn_state->crtc) 4997 drm_connector_put(&connector->base); 4998 4999 if (encoder) { 5000 struct intel_crtc *crtc = 5001 to_intel_crtc(encoder->base.crtc); 5002 const struct intel_crtc_state *crtc_state = 5003 to_intel_crtc_state(crtc->base.state); 5004 5005 conn_state->best_encoder = &encoder->base; 5006 conn_state->crtc = &crtc->base; 5007 conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3; 5008 5009 drm_connector_get(&connector->base); 5010 } else { 5011 conn_state->best_encoder = NULL; 5012 conn_state->crtc = NULL; 5013 } 5014 } 5015 drm_connector_list_iter_end(&conn_iter); 5016 } 5017 5018 static int 5019 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state, 5020 struct intel_crtc_state *pipe_config) 5021 { 5022 struct drm_connector *connector = conn_state->connector; 5023 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); 5024 const struct drm_display_info *info = &connector->display_info; 5025 int bpp; 5026 5027 switch (conn_state->max_bpc) { 5028 case 6 ... 7: 5029 bpp = 6 * 3; 5030 break; 5031 case 8 ... 9: 5032 bpp = 8 * 3; 5033 break; 5034 case 10 ... 11: 5035 bpp = 10 * 3; 5036 break; 5037 case 12 ... 16: 5038 bpp = 12 * 3; 5039 break; 5040 default: 5041 MISSING_CASE(conn_state->max_bpc); 5042 return -EINVAL; 5043 } 5044 5045 if (bpp < pipe_config->pipe_bpp) { 5046 drm_dbg_kms(&i915->drm, 5047 "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of " 5048 "EDID bpp %d, requested bpp %d, max platform bpp %d\n", 5049 connector->base.id, connector->name, 5050 bpp, 3 * info->bpc, 5051 3 * conn_state->max_requested_bpc, 5052 pipe_config->pipe_bpp); 5053 5054 pipe_config->pipe_bpp = bpp; 5055 } 5056 5057 return 0; 5058 } 5059 5060 static int 5061 compute_baseline_pipe_bpp(struct intel_atomic_state *state, 5062 struct intel_crtc *crtc) 5063 { 5064 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5065 struct intel_crtc_state *pipe_config = 5066 intel_atomic_get_new_crtc_state(state, crtc); 5067 struct drm_connector *connector; 5068 struct drm_connector_state *connector_state; 5069 int bpp, i; 5070 5071 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 5072 IS_CHERRYVIEW(dev_priv))) 5073 bpp = 10*3; 5074 else if (DISPLAY_VER(dev_priv) >= 5) 5075 bpp = 12*3; 5076 else 5077 bpp = 8*3; 5078 5079 pipe_config->pipe_bpp = bpp; 5080 5081 /* Clamp display bpp to connector max bpp */ 5082 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5083 int ret; 5084 5085 if (connector_state->crtc != &crtc->base) 5086 continue; 5087 5088 ret = compute_sink_pipe_bpp(connector_state, pipe_config); 5089 if (ret) 5090 return ret; 5091 } 5092 5093 return 0; 5094 } 5095 5096 static void intel_dump_crtc_timings(struct drm_i915_private *i915, 5097 const struct drm_display_mode *mode) 5098 { 5099 drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, " 5100 "type: 0x%x flags: 0x%x\n", 5101 mode->crtc_clock, 5102 mode->crtc_hdisplay, mode->crtc_hsync_start, 5103 mode->crtc_hsync_end, mode->crtc_htotal, 5104 mode->crtc_vdisplay, mode->crtc_vsync_start, 5105 mode->crtc_vsync_end, mode->crtc_vtotal, 5106 mode->type, mode->flags); 5107 } 5108 5109 static void 5110 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config, 5111 const char *id, unsigned int lane_count, 5112 const struct intel_link_m_n *m_n) 5113 { 5114 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); 5115 5116 drm_dbg_kms(&i915->drm, 5117 "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n", 5118 id, lane_count, 5119 m_n->data_m, m_n->data_n, 5120 m_n->link_m, m_n->link_n, m_n->tu); 5121 } 5122 5123 static void 5124 intel_dump_infoframe(struct drm_i915_private *dev_priv, 5125 const union hdmi_infoframe *frame) 5126 { 5127 if (!drm_debug_enabled(DRM_UT_KMS)) 5128 return; 5129 5130 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame); 5131 } 5132 5133 static void 5134 intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv, 5135 const struct drm_dp_vsc_sdp *vsc) 5136 { 5137 if (!drm_debug_enabled(DRM_UT_KMS)) 5138 return; 5139 5140 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc); 5141 } 5142 5143 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x 5144 5145 static const char * const output_type_str[] = { 5146 OUTPUT_TYPE(UNUSED), 5147 OUTPUT_TYPE(ANALOG), 5148 OUTPUT_TYPE(DVO), 5149 OUTPUT_TYPE(SDVO), 5150 OUTPUT_TYPE(LVDS), 5151 OUTPUT_TYPE(TVOUT), 5152 OUTPUT_TYPE(HDMI), 5153 OUTPUT_TYPE(DP), 5154 OUTPUT_TYPE(EDP), 5155 OUTPUT_TYPE(DSI), 5156 OUTPUT_TYPE(DDI), 5157 OUTPUT_TYPE(DP_MST), 5158 }; 5159 5160 #undef OUTPUT_TYPE 5161 5162 static void snprintf_output_types(char *buf, size_t len, 5163 unsigned int output_types) 5164 { 5165 char *str = buf; 5166 int i; 5167 5168 str[0] = '\0'; 5169 5170 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) { 5171 int r; 5172 5173 if ((output_types & BIT(i)) == 0) 5174 continue; 5175 5176 r = snprintf(str, len, "%s%s", 5177 str != buf ? "," : "", output_type_str[i]); 5178 if (r >= len) 5179 break; 5180 str += r; 5181 len -= r; 5182 5183 output_types &= ~BIT(i); 5184 } 5185 5186 WARN_ON_ONCE(output_types != 0); 5187 } 5188 5189 static const char * const output_format_str[] = { 5190 [INTEL_OUTPUT_FORMAT_RGB] = "RGB", 5191 [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0", 5192 [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4", 5193 }; 5194 5195 static const char *output_formats(enum intel_output_format format) 5196 { 5197 if (format >= ARRAY_SIZE(output_format_str)) 5198 return "invalid"; 5199 return output_format_str[format]; 5200 } 5201 5202 static void intel_dump_plane_state(const struct intel_plane_state *plane_state) 5203 { 5204 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 5205 struct drm_i915_private *i915 = to_i915(plane->base.dev); 5206 const struct drm_framebuffer *fb = plane_state->hw.fb; 5207 5208 if (!fb) { 5209 drm_dbg_kms(&i915->drm, 5210 "[PLANE:%d:%s] fb: [NOFB], visible: %s\n", 5211 plane->base.base.id, plane->base.name, 5212 str_yes_no(plane_state->uapi.visible)); 5213 return; 5214 } 5215 5216 drm_dbg_kms(&i915->drm, 5217 "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %p4cc modifier = 0x%llx, visible: %s\n", 5218 plane->base.base.id, plane->base.name, 5219 fb->base.id, fb->width, fb->height, &fb->format->format, 5220 fb->modifier, str_yes_no(plane_state->uapi.visible)); 5221 drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n", 5222 plane_state->hw.rotation, plane_state->scaler_id); 5223 if (plane_state->uapi.visible) 5224 drm_dbg_kms(&i915->drm, 5225 "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n", 5226 DRM_RECT_FP_ARG(&plane_state->uapi.src), 5227 DRM_RECT_ARG(&plane_state->uapi.dst)); 5228 } 5229 5230 static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, 5231 struct intel_atomic_state *state, 5232 const char *context) 5233 { 5234 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 5235 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5236 const struct intel_plane_state *plane_state; 5237 struct intel_plane *plane; 5238 char buf[64]; 5239 int i; 5240 5241 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n", 5242 crtc->base.base.id, crtc->base.name, 5243 str_yes_no(pipe_config->hw.enable), context); 5244 5245 if (!pipe_config->hw.enable) 5246 goto dump_planes; 5247 5248 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types); 5249 drm_dbg_kms(&dev_priv->drm, 5250 "active: %s, output_types: %s (0x%x), output format: %s\n", 5251 str_yes_no(pipe_config->hw.active), 5252 buf, pipe_config->output_types, 5253 output_formats(pipe_config->output_format)); 5254 5255 drm_dbg_kms(&dev_priv->drm, 5256 "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", 5257 transcoder_name(pipe_config->cpu_transcoder), 5258 pipe_config->pipe_bpp, pipe_config->dither); 5259 5260 drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n", 5261 transcoder_name(pipe_config->mst_master_transcoder)); 5262 5263 drm_dbg_kms(&dev_priv->drm, 5264 "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n", 5265 transcoder_name(pipe_config->master_transcoder), 5266 pipe_config->sync_mode_slaves_mask); 5267 5268 drm_dbg_kms(&dev_priv->drm, "bigjoiner: %s, pipes: 0x%x\n", 5269 intel_crtc_is_bigjoiner_slave(pipe_config) ? "slave" : 5270 intel_crtc_is_bigjoiner_master(pipe_config) ? "master" : "no", 5271 pipe_config->bigjoiner_pipes); 5272 5273 drm_dbg_kms(&dev_priv->drm, "splitter: %s, link count %d, overlap %d\n", 5274 str_enabled_disabled(pipe_config->splitter.enable), 5275 pipe_config->splitter.link_count, 5276 pipe_config->splitter.pixel_overlap); 5277 5278 if (pipe_config->has_pch_encoder) 5279 intel_dump_m_n_config(pipe_config, "fdi", 5280 pipe_config->fdi_lanes, 5281 &pipe_config->fdi_m_n); 5282 5283 if (intel_crtc_has_dp_encoder(pipe_config)) { 5284 intel_dump_m_n_config(pipe_config, "dp m_n", 5285 pipe_config->lane_count, 5286 &pipe_config->dp_m_n); 5287 intel_dump_m_n_config(pipe_config, "dp m2_n2", 5288 pipe_config->lane_count, 5289 &pipe_config->dp_m2_n2); 5290 } 5291 5292 drm_dbg_kms(&dev_priv->drm, "framestart delay: %d, MSA timing delay: %d\n", 5293 pipe_config->framestart_delay, pipe_config->msa_timing_delay); 5294 5295 drm_dbg_kms(&dev_priv->drm, 5296 "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n", 5297 pipe_config->has_audio, pipe_config->has_infoframe, 5298 pipe_config->infoframes.enable); 5299 5300 if (pipe_config->infoframes.enable & 5301 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) 5302 drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n", 5303 pipe_config->infoframes.gcp); 5304 if (pipe_config->infoframes.enable & 5305 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) 5306 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi); 5307 if (pipe_config->infoframes.enable & 5308 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD)) 5309 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd); 5310 if (pipe_config->infoframes.enable & 5311 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR)) 5312 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi); 5313 if (pipe_config->infoframes.enable & 5314 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) 5315 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); 5316 if (pipe_config->infoframes.enable & 5317 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA)) 5318 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); 5319 if (pipe_config->infoframes.enable & 5320 intel_hdmi_infoframe_enable(DP_SDP_VSC)) 5321 intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc); 5322 5323 drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n", 5324 str_yes_no(pipe_config->vrr.enable), 5325 pipe_config->vrr.vmin, pipe_config->vrr.vmax, 5326 pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband, 5327 pipe_config->vrr.flipline, 5328 intel_vrr_vmin_vblank_start(pipe_config), 5329 intel_vrr_vmax_vblank_start(pipe_config)); 5330 5331 drm_dbg_kms(&dev_priv->drm, "requested mode: " DRM_MODE_FMT "\n", 5332 DRM_MODE_ARG(&pipe_config->hw.mode)); 5333 drm_dbg_kms(&dev_priv->drm, "adjusted mode: " DRM_MODE_FMT "\n", 5334 DRM_MODE_ARG(&pipe_config->hw.adjusted_mode)); 5335 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode); 5336 drm_dbg_kms(&dev_priv->drm, "pipe mode: " DRM_MODE_FMT "\n", 5337 DRM_MODE_ARG(&pipe_config->hw.pipe_mode)); 5338 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode); 5339 drm_dbg_kms(&dev_priv->drm, 5340 "port clock: %d, pipe src: " DRM_RECT_FMT ", pixel rate %d\n", 5341 pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src), 5342 pipe_config->pixel_rate); 5343 5344 drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n", 5345 pipe_config->linetime, pipe_config->ips_linetime); 5346 5347 if (DISPLAY_VER(dev_priv) >= 9) 5348 drm_dbg_kms(&dev_priv->drm, 5349 "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", 5350 crtc->num_scalers, 5351 pipe_config->scaler_state.scaler_users, 5352 pipe_config->scaler_state.scaler_id); 5353 5354 if (HAS_GMCH(dev_priv)) 5355 drm_dbg_kms(&dev_priv->drm, 5356 "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", 5357 pipe_config->gmch_pfit.control, 5358 pipe_config->gmch_pfit.pgm_ratios, 5359 pipe_config->gmch_pfit.lvds_border_bits); 5360 else 5361 drm_dbg_kms(&dev_priv->drm, 5362 "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n", 5363 DRM_RECT_ARG(&pipe_config->pch_pfit.dst), 5364 str_enabled_disabled(pipe_config->pch_pfit.enabled), 5365 str_yes_no(pipe_config->pch_pfit.force_thru)); 5366 5367 drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i, drrs: %i\n", 5368 pipe_config->ips_enabled, pipe_config->double_wide, 5369 pipe_config->has_drrs); 5370 5371 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state); 5372 5373 if (IS_CHERRYVIEW(dev_priv)) 5374 drm_dbg_kms(&dev_priv->drm, 5375 "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", 5376 pipe_config->cgm_mode, pipe_config->gamma_mode, 5377 pipe_config->gamma_enable, pipe_config->csc_enable); 5378 else 5379 drm_dbg_kms(&dev_priv->drm, 5380 "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", 5381 pipe_config->csc_mode, pipe_config->gamma_mode, 5382 pipe_config->gamma_enable, pipe_config->csc_enable); 5383 5384 drm_dbg_kms(&dev_priv->drm, "degamma lut: %d entries, gamma lut: %d entries\n", 5385 pipe_config->hw.degamma_lut ? 5386 drm_color_lut_size(pipe_config->hw.degamma_lut) : 0, 5387 pipe_config->hw.gamma_lut ? 5388 drm_color_lut_size(pipe_config->hw.gamma_lut) : 0); 5389 5390 dump_planes: 5391 if (!state) 5392 return; 5393 5394 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 5395 if (plane->pipe == crtc->pipe) 5396 intel_dump_plane_state(plane_state); 5397 } 5398 } 5399 5400 static bool check_digital_port_conflicts(struct intel_atomic_state *state) 5401 { 5402 struct drm_device *dev = state->base.dev; 5403 struct drm_connector *connector; 5404 struct drm_connector_list_iter conn_iter; 5405 unsigned int used_ports = 0; 5406 unsigned int used_mst_ports = 0; 5407 bool ret = true; 5408 5409 /* 5410 * We're going to peek into connector->state, 5411 * hence connection_mutex must be held. 5412 */ 5413 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex); 5414 5415 /* 5416 * Walk the connector list instead of the encoder 5417 * list to detect the problem on ddi platforms 5418 * where there's just one encoder per digital port. 5419 */ 5420 drm_connector_list_iter_begin(dev, &conn_iter); 5421 drm_for_each_connector_iter(connector, &conn_iter) { 5422 struct drm_connector_state *connector_state; 5423 struct intel_encoder *encoder; 5424 5425 connector_state = 5426 drm_atomic_get_new_connector_state(&state->base, 5427 connector); 5428 if (!connector_state) 5429 connector_state = connector->state; 5430 5431 if (!connector_state->best_encoder) 5432 continue; 5433 5434 encoder = to_intel_encoder(connector_state->best_encoder); 5435 5436 drm_WARN_ON(dev, !connector_state->crtc); 5437 5438 switch (encoder->type) { 5439 case INTEL_OUTPUT_DDI: 5440 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev)))) 5441 break; 5442 fallthrough; 5443 case INTEL_OUTPUT_DP: 5444 case INTEL_OUTPUT_HDMI: 5445 case INTEL_OUTPUT_EDP: 5446 /* the same port mustn't appear more than once */ 5447 if (used_ports & BIT(encoder->port)) 5448 ret = false; 5449 5450 used_ports |= BIT(encoder->port); 5451 break; 5452 case INTEL_OUTPUT_DP_MST: 5453 used_mst_ports |= 5454 1 << encoder->port; 5455 break; 5456 default: 5457 break; 5458 } 5459 } 5460 drm_connector_list_iter_end(&conn_iter); 5461 5462 /* can't mix MST and SST/HDMI on the same port */ 5463 if (used_ports & used_mst_ports) 5464 return false; 5465 5466 return ret; 5467 } 5468 5469 static void 5470 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state, 5471 struct intel_crtc *crtc) 5472 { 5473 struct intel_crtc_state *crtc_state = 5474 intel_atomic_get_new_crtc_state(state, crtc); 5475 5476 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 5477 5478 drm_property_replace_blob(&crtc_state->hw.degamma_lut, 5479 crtc_state->uapi.degamma_lut); 5480 drm_property_replace_blob(&crtc_state->hw.gamma_lut, 5481 crtc_state->uapi.gamma_lut); 5482 drm_property_replace_blob(&crtc_state->hw.ctm, 5483 crtc_state->uapi.ctm); 5484 } 5485 5486 static void 5487 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state, 5488 struct intel_crtc *crtc) 5489 { 5490 struct intel_crtc_state *crtc_state = 5491 intel_atomic_get_new_crtc_state(state, crtc); 5492 5493 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 5494 5495 crtc_state->hw.enable = crtc_state->uapi.enable; 5496 crtc_state->hw.active = crtc_state->uapi.active; 5497 drm_mode_copy(&crtc_state->hw.mode, 5498 &crtc_state->uapi.mode); 5499 drm_mode_copy(&crtc_state->hw.adjusted_mode, 5500 &crtc_state->uapi.adjusted_mode); 5501 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter; 5502 5503 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 5504 } 5505 5506 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state) 5507 { 5508 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 5509 return; 5510 5511 crtc_state->uapi.enable = crtc_state->hw.enable; 5512 crtc_state->uapi.active = crtc_state->hw.active; 5513 drm_WARN_ON(crtc_state->uapi.crtc->dev, 5514 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0); 5515 5516 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode; 5517 crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter; 5518 5519 drm_property_replace_blob(&crtc_state->uapi.degamma_lut, 5520 crtc_state->hw.degamma_lut); 5521 drm_property_replace_blob(&crtc_state->uapi.gamma_lut, 5522 crtc_state->hw.gamma_lut); 5523 drm_property_replace_blob(&crtc_state->uapi.ctm, 5524 crtc_state->hw.ctm); 5525 } 5526 5527 static void 5528 copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state, 5529 struct intel_crtc *slave_crtc) 5530 { 5531 struct intel_crtc_state *slave_crtc_state = 5532 intel_atomic_get_new_crtc_state(state, slave_crtc); 5533 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 5534 const struct intel_crtc_state *master_crtc_state = 5535 intel_atomic_get_new_crtc_state(state, master_crtc); 5536 5537 drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut, 5538 master_crtc_state->hw.degamma_lut); 5539 drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut, 5540 master_crtc_state->hw.gamma_lut); 5541 drm_property_replace_blob(&slave_crtc_state->hw.ctm, 5542 master_crtc_state->hw.ctm); 5543 5544 slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed; 5545 } 5546 5547 static int 5548 copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state, 5549 struct intel_crtc *slave_crtc) 5550 { 5551 struct intel_crtc_state *slave_crtc_state = 5552 intel_atomic_get_new_crtc_state(state, slave_crtc); 5553 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 5554 const struct intel_crtc_state *master_crtc_state = 5555 intel_atomic_get_new_crtc_state(state, master_crtc); 5556 struct intel_crtc_state *saved_state; 5557 5558 WARN_ON(master_crtc_state->bigjoiner_pipes != 5559 slave_crtc_state->bigjoiner_pipes); 5560 5561 saved_state = kmemdup(master_crtc_state, sizeof(*saved_state), GFP_KERNEL); 5562 if (!saved_state) 5563 return -ENOMEM; 5564 5565 /* preserve some things from the slave's original crtc state */ 5566 saved_state->uapi = slave_crtc_state->uapi; 5567 saved_state->scaler_state = slave_crtc_state->scaler_state; 5568 saved_state->shared_dpll = slave_crtc_state->shared_dpll; 5569 saved_state->dpll_hw_state = slave_crtc_state->dpll_hw_state; 5570 saved_state->crc_enabled = slave_crtc_state->crc_enabled; 5571 5572 intel_crtc_free_hw_state(slave_crtc_state); 5573 memcpy(slave_crtc_state, saved_state, sizeof(*slave_crtc_state)); 5574 kfree(saved_state); 5575 5576 /* Re-init hw state */ 5577 memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw)); 5578 slave_crtc_state->hw.enable = master_crtc_state->hw.enable; 5579 slave_crtc_state->hw.active = master_crtc_state->hw.active; 5580 drm_mode_copy(&slave_crtc_state->hw.mode, 5581 &master_crtc_state->hw.mode); 5582 drm_mode_copy(&slave_crtc_state->hw.pipe_mode, 5583 &master_crtc_state->hw.pipe_mode); 5584 drm_mode_copy(&slave_crtc_state->hw.adjusted_mode, 5585 &master_crtc_state->hw.adjusted_mode); 5586 slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter; 5587 5588 copy_bigjoiner_crtc_state_nomodeset(state, slave_crtc); 5589 5590 slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed; 5591 slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed; 5592 slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed; 5593 5594 WARN_ON(master_crtc_state->bigjoiner_pipes != 5595 slave_crtc_state->bigjoiner_pipes); 5596 5597 return 0; 5598 } 5599 5600 static int 5601 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state, 5602 struct intel_crtc *crtc) 5603 { 5604 struct intel_crtc_state *crtc_state = 5605 intel_atomic_get_new_crtc_state(state, crtc); 5606 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5607 struct intel_crtc_state *saved_state; 5608 5609 saved_state = intel_crtc_state_alloc(crtc); 5610 if (!saved_state) 5611 return -ENOMEM; 5612 5613 /* free the old crtc_state->hw members */ 5614 intel_crtc_free_hw_state(crtc_state); 5615 5616 /* FIXME: before the switch to atomic started, a new pipe_config was 5617 * kzalloc'd. Code that depends on any field being zero should be 5618 * fixed, so that the crtc_state can be safely duplicated. For now, 5619 * only fields that are know to not cause problems are preserved. */ 5620 5621 saved_state->uapi = crtc_state->uapi; 5622 saved_state->scaler_state = crtc_state->scaler_state; 5623 saved_state->shared_dpll = crtc_state->shared_dpll; 5624 saved_state->dpll_hw_state = crtc_state->dpll_hw_state; 5625 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, 5626 sizeof(saved_state->icl_port_dplls)); 5627 saved_state->crc_enabled = crtc_state->crc_enabled; 5628 if (IS_G4X(dev_priv) || 5629 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5630 saved_state->wm = crtc_state->wm; 5631 5632 memcpy(crtc_state, saved_state, sizeof(*crtc_state)); 5633 kfree(saved_state); 5634 5635 intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc); 5636 5637 return 0; 5638 } 5639 5640 static int 5641 intel_modeset_pipe_config(struct intel_atomic_state *state, 5642 struct intel_crtc *crtc) 5643 { 5644 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 5645 struct intel_crtc_state *pipe_config = 5646 intel_atomic_get_new_crtc_state(state, crtc); 5647 struct drm_connector *connector; 5648 struct drm_connector_state *connector_state; 5649 int pipe_src_w, pipe_src_h; 5650 int base_bpp, ret, i; 5651 bool retry = true; 5652 5653 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 5654 5655 pipe_config->framestart_delay = 1; 5656 5657 /* 5658 * Sanitize sync polarity flags based on requested ones. If neither 5659 * positive or negative polarity is requested, treat this as meaning 5660 * negative polarity. 5661 */ 5662 if (!(pipe_config->hw.adjusted_mode.flags & 5663 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) 5664 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; 5665 5666 if (!(pipe_config->hw.adjusted_mode.flags & 5667 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 5668 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; 5669 5670 ret = compute_baseline_pipe_bpp(state, crtc); 5671 if (ret) 5672 return ret; 5673 5674 base_bpp = pipe_config->pipe_bpp; 5675 5676 /* 5677 * Determine the real pipe dimensions. Note that stereo modes can 5678 * increase the actual pipe size due to the frame doubling and 5679 * insertion of additional space for blanks between the frame. This 5680 * is stored in the crtc timings. We use the requested mode to do this 5681 * computation to clearly distinguish it from the adjusted mode, which 5682 * can be changed by the connectors in the below retry loop. 5683 */ 5684 drm_mode_get_hv_timing(&pipe_config->hw.mode, 5685 &pipe_src_w, &pipe_src_h); 5686 drm_rect_init(&pipe_config->pipe_src, 0, 0, 5687 pipe_src_w, pipe_src_h); 5688 5689 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5690 struct intel_encoder *encoder = 5691 to_intel_encoder(connector_state->best_encoder); 5692 5693 if (connector_state->crtc != &crtc->base) 5694 continue; 5695 5696 if (!check_single_encoder_cloning(state, crtc, encoder)) { 5697 drm_dbg_kms(&i915->drm, 5698 "rejecting invalid cloning configuration\n"); 5699 return -EINVAL; 5700 } 5701 5702 /* 5703 * Determine output_types before calling the .compute_config() 5704 * hooks so that the hooks can use this information safely. 5705 */ 5706 if (encoder->compute_output_type) 5707 pipe_config->output_types |= 5708 BIT(encoder->compute_output_type(encoder, pipe_config, 5709 connector_state)); 5710 else 5711 pipe_config->output_types |= BIT(encoder->type); 5712 } 5713 5714 encoder_retry: 5715 /* Ensure the port clock defaults are reset when retrying. */ 5716 pipe_config->port_clock = 0; 5717 pipe_config->pixel_multiplier = 1; 5718 5719 /* Fill in default crtc timings, allow encoders to overwrite them. */ 5720 drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode, 5721 CRTC_STEREO_DOUBLE); 5722 5723 /* Pass our mode to the connectors and the CRTC to give them a chance to 5724 * adjust it according to limitations or connector properties, and also 5725 * a chance to reject the mode entirely. 5726 */ 5727 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5728 struct intel_encoder *encoder = 5729 to_intel_encoder(connector_state->best_encoder); 5730 5731 if (connector_state->crtc != &crtc->base) 5732 continue; 5733 5734 ret = encoder->compute_config(encoder, pipe_config, 5735 connector_state); 5736 if (ret == -EDEADLK) 5737 return ret; 5738 if (ret < 0) { 5739 drm_dbg_kms(&i915->drm, "Encoder config failure: %d\n", ret); 5740 return ret; 5741 } 5742 } 5743 5744 /* Set default port clock if not overwritten by the encoder. Needs to be 5745 * done afterwards in case the encoder adjusts the mode. */ 5746 if (!pipe_config->port_clock) 5747 pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock 5748 * pipe_config->pixel_multiplier; 5749 5750 ret = intel_crtc_compute_config(state, crtc); 5751 if (ret == -EDEADLK) 5752 return ret; 5753 if (ret == -EAGAIN) { 5754 if (drm_WARN(&i915->drm, !retry, 5755 "loop in pipe configuration computation\n")) 5756 return -EINVAL; 5757 5758 drm_dbg_kms(&i915->drm, "CRTC bw constrained, retrying\n"); 5759 retry = false; 5760 goto encoder_retry; 5761 } 5762 if (ret < 0) { 5763 drm_dbg_kms(&i915->drm, "CRTC config failure: %d\n", ret); 5764 return ret; 5765 } 5766 5767 /* Dithering seems to not pass-through bits correctly when it should, so 5768 * only enable it on 6bpc panels and when its not a compliance 5769 * test requesting 6bpc video pattern. 5770 */ 5771 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) && 5772 !pipe_config->dither_force_disable; 5773 drm_dbg_kms(&i915->drm, 5774 "hw max bpp: %i, pipe bpp: %i, dithering: %i\n", 5775 base_bpp, pipe_config->pipe_bpp, pipe_config->dither); 5776 5777 return 0; 5778 } 5779 5780 static int 5781 intel_modeset_pipe_config_late(struct intel_atomic_state *state, 5782 struct intel_crtc *crtc) 5783 { 5784 struct intel_crtc_state *crtc_state = 5785 intel_atomic_get_new_crtc_state(state, crtc); 5786 struct drm_connector_state *conn_state; 5787 struct drm_connector *connector; 5788 int i; 5789 5790 intel_bigjoiner_adjust_pipe_src(crtc_state); 5791 5792 for_each_new_connector_in_state(&state->base, connector, 5793 conn_state, i) { 5794 struct intel_encoder *encoder = 5795 to_intel_encoder(conn_state->best_encoder); 5796 int ret; 5797 5798 if (conn_state->crtc != &crtc->base || 5799 !encoder->compute_config_late) 5800 continue; 5801 5802 ret = encoder->compute_config_late(encoder, crtc_state, 5803 conn_state); 5804 if (ret) 5805 return ret; 5806 } 5807 5808 return 0; 5809 } 5810 5811 bool intel_fuzzy_clock_check(int clock1, int clock2) 5812 { 5813 int diff; 5814 5815 if (clock1 == clock2) 5816 return true; 5817 5818 if (!clock1 || !clock2) 5819 return false; 5820 5821 diff = abs(clock1 - clock2); 5822 5823 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) 5824 return true; 5825 5826 return false; 5827 } 5828 5829 static bool 5830 intel_compare_m_n(unsigned int m, unsigned int n, 5831 unsigned int m2, unsigned int n2, 5832 bool exact) 5833 { 5834 if (m == m2 && n == n2) 5835 return true; 5836 5837 if (exact || !m || !n || !m2 || !n2) 5838 return false; 5839 5840 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); 5841 5842 if (n > n2) { 5843 while (n > n2) { 5844 m2 <<= 1; 5845 n2 <<= 1; 5846 } 5847 } else if (n < n2) { 5848 while (n < n2) { 5849 m <<= 1; 5850 n <<= 1; 5851 } 5852 } 5853 5854 if (n != n2) 5855 return false; 5856 5857 return intel_fuzzy_clock_check(m, m2); 5858 } 5859 5860 static bool 5861 intel_compare_link_m_n(const struct intel_link_m_n *m_n, 5862 const struct intel_link_m_n *m2_n2, 5863 bool exact) 5864 { 5865 return m_n->tu == m2_n2->tu && 5866 intel_compare_m_n(m_n->data_m, m_n->data_n, 5867 m2_n2->data_m, m2_n2->data_n, exact) && 5868 intel_compare_m_n(m_n->link_m, m_n->link_n, 5869 m2_n2->link_m, m2_n2->link_n, exact); 5870 } 5871 5872 static bool 5873 intel_compare_infoframe(const union hdmi_infoframe *a, 5874 const union hdmi_infoframe *b) 5875 { 5876 return memcmp(a, b, sizeof(*a)) == 0; 5877 } 5878 5879 static bool 5880 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a, 5881 const struct drm_dp_vsc_sdp *b) 5882 { 5883 return memcmp(a, b, sizeof(*a)) == 0; 5884 } 5885 5886 static void 5887 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv, 5888 bool fastset, const char *name, 5889 const union hdmi_infoframe *a, 5890 const union hdmi_infoframe *b) 5891 { 5892 if (fastset) { 5893 if (!drm_debug_enabled(DRM_UT_KMS)) 5894 return; 5895 5896 drm_dbg_kms(&dev_priv->drm, 5897 "fastset mismatch in %s infoframe\n", name); 5898 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 5899 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a); 5900 drm_dbg_kms(&dev_priv->drm, "found:\n"); 5901 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b); 5902 } else { 5903 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name); 5904 drm_err(&dev_priv->drm, "expected:\n"); 5905 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a); 5906 drm_err(&dev_priv->drm, "found:\n"); 5907 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b); 5908 } 5909 } 5910 5911 static void 5912 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv, 5913 bool fastset, const char *name, 5914 const struct drm_dp_vsc_sdp *a, 5915 const struct drm_dp_vsc_sdp *b) 5916 { 5917 if (fastset) { 5918 if (!drm_debug_enabled(DRM_UT_KMS)) 5919 return; 5920 5921 drm_dbg_kms(&dev_priv->drm, 5922 "fastset mismatch in %s dp sdp\n", name); 5923 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 5924 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a); 5925 drm_dbg_kms(&dev_priv->drm, "found:\n"); 5926 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b); 5927 } else { 5928 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name); 5929 drm_err(&dev_priv->drm, "expected:\n"); 5930 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a); 5931 drm_err(&dev_priv->drm, "found:\n"); 5932 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b); 5933 } 5934 } 5935 5936 static void __printf(4, 5) 5937 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc, 5938 const char *name, const char *format, ...) 5939 { 5940 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 5941 struct va_format vaf; 5942 va_list args; 5943 5944 va_start(args, format); 5945 vaf.fmt = format; 5946 vaf.va = &args; 5947 5948 if (fastset) 5949 drm_dbg_kms(&i915->drm, 5950 "[CRTC:%d:%s] fastset mismatch in %s %pV\n", 5951 crtc->base.base.id, crtc->base.name, name, &vaf); 5952 else 5953 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n", 5954 crtc->base.base.id, crtc->base.name, name, &vaf); 5955 5956 va_end(args); 5957 } 5958 5959 static bool fastboot_enabled(struct drm_i915_private *dev_priv) 5960 { 5961 if (dev_priv->params.fastboot != -1) 5962 return dev_priv->params.fastboot; 5963 5964 /* Enable fastboot by default on Skylake and newer */ 5965 if (DISPLAY_VER(dev_priv) >= 9) 5966 return true; 5967 5968 /* Enable fastboot by default on VLV and CHV */ 5969 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5970 return true; 5971 5972 /* Disabled by default on all others */ 5973 return false; 5974 } 5975 5976 static bool 5977 intel_pipe_config_compare(const struct intel_crtc_state *current_config, 5978 const struct intel_crtc_state *pipe_config, 5979 bool fastset) 5980 { 5981 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev); 5982 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 5983 bool ret = true; 5984 u32 bp_gamma = 0; 5985 bool fixup_inherited = fastset && 5986 current_config->inherited && !pipe_config->inherited; 5987 5988 if (fixup_inherited && !fastboot_enabled(dev_priv)) { 5989 drm_dbg_kms(&dev_priv->drm, 5990 "initial modeset and fastboot not set\n"); 5991 ret = false; 5992 } 5993 5994 #define PIPE_CONF_CHECK_X(name) do { \ 5995 if (current_config->name != pipe_config->name) { \ 5996 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5997 "(expected 0x%08x, found 0x%08x)", \ 5998 current_config->name, \ 5999 pipe_config->name); \ 6000 ret = false; \ 6001 } \ 6002 } while (0) 6003 6004 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \ 6005 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \ 6006 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6007 "(expected 0x%08x, found 0x%08x)", \ 6008 current_config->name & (mask), \ 6009 pipe_config->name & (mask)); \ 6010 ret = false; \ 6011 } \ 6012 } while (0) 6013 6014 #define PIPE_CONF_CHECK_I(name) do { \ 6015 if (current_config->name != pipe_config->name) { \ 6016 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6017 "(expected %i, found %i)", \ 6018 current_config->name, \ 6019 pipe_config->name); \ 6020 ret = false; \ 6021 } \ 6022 } while (0) 6023 6024 #define PIPE_CONF_CHECK_BOOL(name) do { \ 6025 if (current_config->name != pipe_config->name) { \ 6026 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6027 "(expected %s, found %s)", \ 6028 str_yes_no(current_config->name), \ 6029 str_yes_no(pipe_config->name)); \ 6030 ret = false; \ 6031 } \ 6032 } while (0) 6033 6034 /* 6035 * Checks state where we only read out the enabling, but not the entire 6036 * state itself (like full infoframes or ELD for audio). These states 6037 * require a full modeset on bootup to fix up. 6038 */ 6039 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \ 6040 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \ 6041 PIPE_CONF_CHECK_BOOL(name); \ 6042 } else { \ 6043 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6044 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \ 6045 str_yes_no(current_config->name), \ 6046 str_yes_no(pipe_config->name)); \ 6047 ret = false; \ 6048 } \ 6049 } while (0) 6050 6051 #define PIPE_CONF_CHECK_P(name) do { \ 6052 if (current_config->name != pipe_config->name) { \ 6053 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6054 "(expected %p, found %p)", \ 6055 current_config->name, \ 6056 pipe_config->name); \ 6057 ret = false; \ 6058 } \ 6059 } while (0) 6060 6061 #define PIPE_CONF_CHECK_M_N(name) do { \ 6062 if (!intel_compare_link_m_n(¤t_config->name, \ 6063 &pipe_config->name,\ 6064 !fastset)) { \ 6065 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6066 "(expected tu %i data %i/%i link %i/%i, " \ 6067 "found tu %i, data %i/%i link %i/%i)", \ 6068 current_config->name.tu, \ 6069 current_config->name.data_m, \ 6070 current_config->name.data_n, \ 6071 current_config->name.link_m, \ 6072 current_config->name.link_n, \ 6073 pipe_config->name.tu, \ 6074 pipe_config->name.data_m, \ 6075 pipe_config->name.data_n, \ 6076 pipe_config->name.link_m, \ 6077 pipe_config->name.link_n); \ 6078 ret = false; \ 6079 } \ 6080 } while (0) 6081 6082 #define PIPE_CONF_CHECK_TIMINGS(name) do { \ 6083 PIPE_CONF_CHECK_I(name.crtc_hdisplay); \ 6084 PIPE_CONF_CHECK_I(name.crtc_htotal); \ 6085 PIPE_CONF_CHECK_I(name.crtc_hblank_start); \ 6086 PIPE_CONF_CHECK_I(name.crtc_hblank_end); \ 6087 PIPE_CONF_CHECK_I(name.crtc_hsync_start); \ 6088 PIPE_CONF_CHECK_I(name.crtc_hsync_end); \ 6089 PIPE_CONF_CHECK_I(name.crtc_vdisplay); \ 6090 PIPE_CONF_CHECK_I(name.crtc_vtotal); \ 6091 PIPE_CONF_CHECK_I(name.crtc_vblank_start); \ 6092 PIPE_CONF_CHECK_I(name.crtc_vblank_end); \ 6093 PIPE_CONF_CHECK_I(name.crtc_vsync_start); \ 6094 PIPE_CONF_CHECK_I(name.crtc_vsync_end); \ 6095 } while (0) 6096 6097 #define PIPE_CONF_CHECK_RECT(name) do { \ 6098 PIPE_CONF_CHECK_I(name.x1); \ 6099 PIPE_CONF_CHECK_I(name.x2); \ 6100 PIPE_CONF_CHECK_I(name.y1); \ 6101 PIPE_CONF_CHECK_I(name.y2); \ 6102 } while (0) 6103 6104 /* This is required for BDW+ where there is only one set of registers for 6105 * switching between high and low RR. 6106 * This macro can be used whenever a comparison has to be made between one 6107 * hw state and multiple sw state variables. 6108 */ 6109 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \ 6110 if (!intel_compare_link_m_n(¤t_config->name, \ 6111 &pipe_config->name, !fastset) && \ 6112 !intel_compare_link_m_n(¤t_config->alt_name, \ 6113 &pipe_config->name, !fastset)) { \ 6114 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6115 "(expected tu %i data %i/%i link %i/%i, " \ 6116 "or tu %i data %i/%i link %i/%i, " \ 6117 "found tu %i, data %i/%i link %i/%i)", \ 6118 current_config->name.tu, \ 6119 current_config->name.data_m, \ 6120 current_config->name.data_n, \ 6121 current_config->name.link_m, \ 6122 current_config->name.link_n, \ 6123 current_config->alt_name.tu, \ 6124 current_config->alt_name.data_m, \ 6125 current_config->alt_name.data_n, \ 6126 current_config->alt_name.link_m, \ 6127 current_config->alt_name.link_n, \ 6128 pipe_config->name.tu, \ 6129 pipe_config->name.data_m, \ 6130 pipe_config->name.data_n, \ 6131 pipe_config->name.link_m, \ 6132 pipe_config->name.link_n); \ 6133 ret = false; \ 6134 } \ 6135 } while (0) 6136 6137 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \ 6138 if ((current_config->name ^ pipe_config->name) & (mask)) { \ 6139 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6140 "(%x) (expected %i, found %i)", \ 6141 (mask), \ 6142 current_config->name & (mask), \ 6143 pipe_config->name & (mask)); \ 6144 ret = false; \ 6145 } \ 6146 } while (0) 6147 6148 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \ 6149 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ 6150 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6151 "(expected %i, found %i)", \ 6152 current_config->name, \ 6153 pipe_config->name); \ 6154 ret = false; \ 6155 } \ 6156 } while (0) 6157 6158 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \ 6159 if (!intel_compare_infoframe(¤t_config->infoframes.name, \ 6160 &pipe_config->infoframes.name)) { \ 6161 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \ 6162 ¤t_config->infoframes.name, \ 6163 &pipe_config->infoframes.name); \ 6164 ret = false; \ 6165 } \ 6166 } while (0) 6167 6168 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \ 6169 if (!current_config->has_psr && !pipe_config->has_psr && \ 6170 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \ 6171 &pipe_config->infoframes.name)) { \ 6172 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \ 6173 ¤t_config->infoframes.name, \ 6174 &pipe_config->infoframes.name); \ 6175 ret = false; \ 6176 } \ 6177 } while (0) 6178 6179 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \ 6180 if (current_config->name1 != pipe_config->name1) { \ 6181 pipe_config_mismatch(fastset, crtc, __stringify(name1), \ 6182 "(expected %i, found %i, won't compare lut values)", \ 6183 current_config->name1, \ 6184 pipe_config->name1); \ 6185 ret = false;\ 6186 } else { \ 6187 if (!intel_color_lut_equal(current_config->name2, \ 6188 pipe_config->name2, pipe_config->name1, \ 6189 bit_precision)) { \ 6190 pipe_config_mismatch(fastset, crtc, __stringify(name2), \ 6191 "hw_state doesn't match sw_state"); \ 6192 ret = false; \ 6193 } \ 6194 } \ 6195 } while (0) 6196 6197 #define PIPE_CONF_QUIRK(quirk) \ 6198 ((current_config->quirks | pipe_config->quirks) & (quirk)) 6199 6200 PIPE_CONF_CHECK_I(cpu_transcoder); 6201 6202 PIPE_CONF_CHECK_BOOL(has_pch_encoder); 6203 PIPE_CONF_CHECK_I(fdi_lanes); 6204 PIPE_CONF_CHECK_M_N(fdi_m_n); 6205 6206 PIPE_CONF_CHECK_I(lane_count); 6207 PIPE_CONF_CHECK_X(lane_lat_optim_mask); 6208 6209 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) { 6210 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); 6211 } else { 6212 PIPE_CONF_CHECK_M_N(dp_m_n); 6213 PIPE_CONF_CHECK_M_N(dp_m2_n2); 6214 } 6215 6216 PIPE_CONF_CHECK_X(output_types); 6217 6218 PIPE_CONF_CHECK_I(framestart_delay); 6219 PIPE_CONF_CHECK_I(msa_timing_delay); 6220 6221 PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode); 6222 PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode); 6223 6224 PIPE_CONF_CHECK_I(pixel_multiplier); 6225 6226 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6227 DRM_MODE_FLAG_INTERLACE); 6228 6229 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { 6230 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6231 DRM_MODE_FLAG_PHSYNC); 6232 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6233 DRM_MODE_FLAG_NHSYNC); 6234 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6235 DRM_MODE_FLAG_PVSYNC); 6236 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6237 DRM_MODE_FLAG_NVSYNC); 6238 } 6239 6240 PIPE_CONF_CHECK_I(output_format); 6241 PIPE_CONF_CHECK_BOOL(has_hdmi_sink); 6242 if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || 6243 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 6244 PIPE_CONF_CHECK_BOOL(limited_color_range); 6245 6246 PIPE_CONF_CHECK_BOOL(hdmi_scrambling); 6247 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio); 6248 PIPE_CONF_CHECK_BOOL(has_infoframe); 6249 PIPE_CONF_CHECK_BOOL(fec_enable); 6250 6251 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio); 6252 6253 PIPE_CONF_CHECK_X(gmch_pfit.control); 6254 /* pfit ratios are autocomputed by the hw on gen4+ */ 6255 if (DISPLAY_VER(dev_priv) < 4) 6256 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); 6257 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); 6258 6259 /* 6260 * Changing the EDP transcoder input mux 6261 * (A_ONOFF vs. A_ON) requires a full modeset. 6262 */ 6263 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru); 6264 6265 if (!fastset) { 6266 PIPE_CONF_CHECK_RECT(pipe_src); 6267 6268 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled); 6269 PIPE_CONF_CHECK_RECT(pch_pfit.dst); 6270 6271 PIPE_CONF_CHECK_I(scaler_state.scaler_id); 6272 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate); 6273 6274 PIPE_CONF_CHECK_X(gamma_mode); 6275 if (IS_CHERRYVIEW(dev_priv)) 6276 PIPE_CONF_CHECK_X(cgm_mode); 6277 else 6278 PIPE_CONF_CHECK_X(csc_mode); 6279 PIPE_CONF_CHECK_BOOL(gamma_enable); 6280 PIPE_CONF_CHECK_BOOL(csc_enable); 6281 6282 PIPE_CONF_CHECK_I(linetime); 6283 PIPE_CONF_CHECK_I(ips_linetime); 6284 6285 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config); 6286 if (bp_gamma) 6287 PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma); 6288 6289 if (current_config->active_planes) { 6290 PIPE_CONF_CHECK_BOOL(has_psr); 6291 PIPE_CONF_CHECK_BOOL(has_psr2); 6292 PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); 6293 PIPE_CONF_CHECK_I(dc3co_exitline); 6294 } 6295 } 6296 6297 PIPE_CONF_CHECK_BOOL(double_wide); 6298 6299 if (dev_priv->dpll.mgr) { 6300 PIPE_CONF_CHECK_P(shared_dpll); 6301 6302 PIPE_CONF_CHECK_X(dpll_hw_state.dpll); 6303 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); 6304 PIPE_CONF_CHECK_X(dpll_hw_state.fp0); 6305 PIPE_CONF_CHECK_X(dpll_hw_state.fp1); 6306 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); 6307 PIPE_CONF_CHECK_X(dpll_hw_state.spll); 6308 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); 6309 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); 6310 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); 6311 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); 6312 PIPE_CONF_CHECK_X(dpll_hw_state.div0); 6313 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); 6314 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); 6315 PIPE_CONF_CHECK_X(dpll_hw_state.pll0); 6316 PIPE_CONF_CHECK_X(dpll_hw_state.pll1); 6317 PIPE_CONF_CHECK_X(dpll_hw_state.pll2); 6318 PIPE_CONF_CHECK_X(dpll_hw_state.pll3); 6319 PIPE_CONF_CHECK_X(dpll_hw_state.pll6); 6320 PIPE_CONF_CHECK_X(dpll_hw_state.pll8); 6321 PIPE_CONF_CHECK_X(dpll_hw_state.pll9); 6322 PIPE_CONF_CHECK_X(dpll_hw_state.pll10); 6323 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); 6324 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl); 6325 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1); 6326 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl); 6327 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0); 6328 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1); 6329 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf); 6330 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock); 6331 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc); 6332 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias); 6333 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias); 6334 } 6335 6336 PIPE_CONF_CHECK_X(dsi_pll.ctrl); 6337 PIPE_CONF_CHECK_X(dsi_pll.div); 6338 6339 if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5) 6340 PIPE_CONF_CHECK_I(pipe_bpp); 6341 6342 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock); 6343 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock); 6344 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); 6345 6346 PIPE_CONF_CHECK_I(min_voltage_level); 6347 6348 if (current_config->has_psr || pipe_config->has_psr) 6349 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable, 6350 ~intel_hdmi_infoframe_enable(DP_SDP_VSC)); 6351 else 6352 PIPE_CONF_CHECK_X(infoframes.enable); 6353 6354 PIPE_CONF_CHECK_X(infoframes.gcp); 6355 PIPE_CONF_CHECK_INFOFRAME(avi); 6356 PIPE_CONF_CHECK_INFOFRAME(spd); 6357 PIPE_CONF_CHECK_INFOFRAME(hdmi); 6358 PIPE_CONF_CHECK_INFOFRAME(drm); 6359 PIPE_CONF_CHECK_DP_VSC_SDP(vsc); 6360 6361 PIPE_CONF_CHECK_X(sync_mode_slaves_mask); 6362 PIPE_CONF_CHECK_I(master_transcoder); 6363 PIPE_CONF_CHECK_X(bigjoiner_pipes); 6364 6365 PIPE_CONF_CHECK_I(dsc.compression_enable); 6366 PIPE_CONF_CHECK_I(dsc.dsc_split); 6367 PIPE_CONF_CHECK_I(dsc.compressed_bpp); 6368 6369 PIPE_CONF_CHECK_BOOL(splitter.enable); 6370 PIPE_CONF_CHECK_I(splitter.link_count); 6371 PIPE_CONF_CHECK_I(splitter.pixel_overlap); 6372 6373 PIPE_CONF_CHECK_I(mst_master_transcoder); 6374 6375 PIPE_CONF_CHECK_BOOL(vrr.enable); 6376 PIPE_CONF_CHECK_I(vrr.vmin); 6377 PIPE_CONF_CHECK_I(vrr.vmax); 6378 PIPE_CONF_CHECK_I(vrr.flipline); 6379 PIPE_CONF_CHECK_I(vrr.pipeline_full); 6380 PIPE_CONF_CHECK_I(vrr.guardband); 6381 6382 #undef PIPE_CONF_CHECK_X 6383 #undef PIPE_CONF_CHECK_I 6384 #undef PIPE_CONF_CHECK_BOOL 6385 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE 6386 #undef PIPE_CONF_CHECK_P 6387 #undef PIPE_CONF_CHECK_FLAGS 6388 #undef PIPE_CONF_CHECK_CLOCK_FUZZY 6389 #undef PIPE_CONF_CHECK_COLOR_LUT 6390 #undef PIPE_CONF_CHECK_TIMINGS 6391 #undef PIPE_CONF_CHECK_RECT 6392 #undef PIPE_CONF_QUIRK 6393 6394 return ret; 6395 } 6396 6397 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, 6398 const struct intel_crtc_state *pipe_config) 6399 { 6400 if (pipe_config->has_pch_encoder) { 6401 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), 6402 &pipe_config->fdi_m_n); 6403 int dotclock = pipe_config->hw.adjusted_mode.crtc_clock; 6404 6405 /* 6406 * FDI already provided one idea for the dotclock. 6407 * Yell if the encoder disagrees. 6408 */ 6409 drm_WARN(&dev_priv->drm, 6410 !intel_fuzzy_clock_check(fdi_dotclock, dotclock), 6411 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", 6412 fdi_dotclock, dotclock); 6413 } 6414 } 6415 6416 static void verify_wm_state(struct intel_crtc *crtc, 6417 struct intel_crtc_state *new_crtc_state) 6418 { 6419 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6420 struct skl_hw_state { 6421 struct skl_ddb_entry ddb[I915_MAX_PLANES]; 6422 struct skl_ddb_entry ddb_y[I915_MAX_PLANES]; 6423 struct skl_pipe_wm wm; 6424 } *hw; 6425 const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal; 6426 int level, max_level = ilk_wm_max_level(dev_priv); 6427 struct intel_plane *plane; 6428 u8 hw_enabled_slices; 6429 6430 if (DISPLAY_VER(dev_priv) < 9 || !new_crtc_state->hw.active) 6431 return; 6432 6433 hw = kzalloc(sizeof(*hw), GFP_KERNEL); 6434 if (!hw) 6435 return; 6436 6437 skl_pipe_wm_get_hw_state(crtc, &hw->wm); 6438 6439 skl_pipe_ddb_get_hw_state(crtc, hw->ddb, hw->ddb_y); 6440 6441 hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv); 6442 6443 if (DISPLAY_VER(dev_priv) >= 11 && 6444 hw_enabled_slices != dev_priv->dbuf.enabled_slices) 6445 drm_err(&dev_priv->drm, 6446 "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n", 6447 dev_priv->dbuf.enabled_slices, 6448 hw_enabled_slices); 6449 6450 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 6451 const struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; 6452 const struct skl_wm_level *hw_wm_level, *sw_wm_level; 6453 6454 /* Watermarks */ 6455 for (level = 0; level <= max_level; level++) { 6456 hw_wm_level = &hw->wm.planes[plane->id].wm[level]; 6457 sw_wm_level = skl_plane_wm_level(sw_wm, plane->id, level); 6458 6459 if (skl_wm_level_equals(hw_wm_level, sw_wm_level)) 6460 continue; 6461 6462 drm_err(&dev_priv->drm, 6463 "[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 6464 plane->base.base.id, plane->base.name, level, 6465 sw_wm_level->enable, 6466 sw_wm_level->blocks, 6467 sw_wm_level->lines, 6468 hw_wm_level->enable, 6469 hw_wm_level->blocks, 6470 hw_wm_level->lines); 6471 } 6472 6473 hw_wm_level = &hw->wm.planes[plane->id].trans_wm; 6474 sw_wm_level = skl_plane_trans_wm(sw_wm, plane->id); 6475 6476 if (!skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 6477 drm_err(&dev_priv->drm, 6478 "[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 6479 plane->base.base.id, plane->base.name, 6480 sw_wm_level->enable, 6481 sw_wm_level->blocks, 6482 sw_wm_level->lines, 6483 hw_wm_level->enable, 6484 hw_wm_level->blocks, 6485 hw_wm_level->lines); 6486 } 6487 6488 hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0; 6489 sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0; 6490 6491 if (HAS_HW_SAGV_WM(dev_priv) && 6492 !skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 6493 drm_err(&dev_priv->drm, 6494 "[PLANE:%d:%s] mismatch in SAGV WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 6495 plane->base.base.id, plane->base.name, 6496 sw_wm_level->enable, 6497 sw_wm_level->blocks, 6498 sw_wm_level->lines, 6499 hw_wm_level->enable, 6500 hw_wm_level->blocks, 6501 hw_wm_level->lines); 6502 } 6503 6504 hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm; 6505 sw_wm_level = &sw_wm->planes[plane->id].sagv.trans_wm; 6506 6507 if (HAS_HW_SAGV_WM(dev_priv) && 6508 !skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 6509 drm_err(&dev_priv->drm, 6510 "[PLANE:%d:%s] mismatch in SAGV trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 6511 plane->base.base.id, plane->base.name, 6512 sw_wm_level->enable, 6513 sw_wm_level->blocks, 6514 sw_wm_level->lines, 6515 hw_wm_level->enable, 6516 hw_wm_level->blocks, 6517 hw_wm_level->lines); 6518 } 6519 6520 /* DDB */ 6521 hw_ddb_entry = &hw->ddb[PLANE_CURSOR]; 6522 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[PLANE_CURSOR]; 6523 6524 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { 6525 drm_err(&dev_priv->drm, 6526 "[PLANE:%d:%s] mismatch in DDB (expected (%u,%u), found (%u,%u))\n", 6527 plane->base.base.id, plane->base.name, 6528 sw_ddb_entry->start, sw_ddb_entry->end, 6529 hw_ddb_entry->start, hw_ddb_entry->end); 6530 } 6531 } 6532 6533 kfree(hw); 6534 } 6535 6536 static void 6537 verify_connector_state(struct intel_atomic_state *state, 6538 struct intel_crtc *crtc) 6539 { 6540 struct drm_connector *connector; 6541 struct drm_connector_state *new_conn_state; 6542 int i; 6543 6544 for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) { 6545 struct drm_encoder *encoder = connector->encoder; 6546 struct intel_crtc_state *crtc_state = NULL; 6547 6548 if (new_conn_state->crtc != &crtc->base) 6549 continue; 6550 6551 if (crtc) 6552 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6553 6554 intel_connector_verify_state(crtc_state, new_conn_state); 6555 6556 I915_STATE_WARN(new_conn_state->best_encoder != encoder, 6557 "connector's atomic encoder doesn't match legacy encoder\n"); 6558 } 6559 } 6560 6561 static void 6562 verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state) 6563 { 6564 struct intel_encoder *encoder; 6565 struct drm_connector *connector; 6566 struct drm_connector_state *old_conn_state, *new_conn_state; 6567 int i; 6568 6569 for_each_intel_encoder(&dev_priv->drm, encoder) { 6570 bool enabled = false, found = false; 6571 enum pipe pipe; 6572 6573 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n", 6574 encoder->base.base.id, 6575 encoder->base.name); 6576 6577 for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state, 6578 new_conn_state, i) { 6579 if (old_conn_state->best_encoder == &encoder->base) 6580 found = true; 6581 6582 if (new_conn_state->best_encoder != &encoder->base) 6583 continue; 6584 found = enabled = true; 6585 6586 I915_STATE_WARN(new_conn_state->crtc != 6587 encoder->base.crtc, 6588 "connector's crtc doesn't match encoder crtc\n"); 6589 } 6590 6591 if (!found) 6592 continue; 6593 6594 I915_STATE_WARN(!!encoder->base.crtc != enabled, 6595 "encoder's enabled state mismatch " 6596 "(expected %i, found %i)\n", 6597 !!encoder->base.crtc, enabled); 6598 6599 if (!encoder->base.crtc) { 6600 bool active; 6601 6602 active = encoder->get_hw_state(encoder, &pipe); 6603 I915_STATE_WARN(active, 6604 "encoder detached but still enabled on pipe %c.\n", 6605 pipe_name(pipe)); 6606 } 6607 } 6608 } 6609 6610 static void 6611 verify_crtc_state(struct intel_crtc *crtc, 6612 struct intel_crtc_state *old_crtc_state, 6613 struct intel_crtc_state *new_crtc_state) 6614 { 6615 struct drm_device *dev = crtc->base.dev; 6616 struct drm_i915_private *dev_priv = to_i915(dev); 6617 struct intel_encoder *encoder; 6618 struct intel_crtc_state *pipe_config = old_crtc_state; 6619 struct drm_atomic_state *state = old_crtc_state->uapi.state; 6620 struct intel_crtc *master_crtc; 6621 6622 __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi); 6623 intel_crtc_free_hw_state(old_crtc_state); 6624 intel_crtc_state_reset(old_crtc_state, crtc); 6625 old_crtc_state->uapi.state = state; 6626 6627 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id, 6628 crtc->base.name); 6629 6630 pipe_config->hw.enable = new_crtc_state->hw.enable; 6631 6632 intel_crtc_get_pipe_config(pipe_config); 6633 6634 /* we keep both pipes enabled on 830 */ 6635 if (IS_I830(dev_priv) && pipe_config->hw.active) 6636 pipe_config->hw.active = new_crtc_state->hw.active; 6637 6638 I915_STATE_WARN(new_crtc_state->hw.active != pipe_config->hw.active, 6639 "crtc active state doesn't match with hw state " 6640 "(expected %i, found %i)\n", 6641 new_crtc_state->hw.active, pipe_config->hw.active); 6642 6643 I915_STATE_WARN(crtc->active != new_crtc_state->hw.active, 6644 "transitional active state does not match atomic hw state " 6645 "(expected %i, found %i)\n", 6646 new_crtc_state->hw.active, crtc->active); 6647 6648 master_crtc = intel_master_crtc(new_crtc_state); 6649 6650 for_each_encoder_on_crtc(dev, &master_crtc->base, encoder) { 6651 enum pipe pipe; 6652 bool active; 6653 6654 active = encoder->get_hw_state(encoder, &pipe); 6655 I915_STATE_WARN(active != new_crtc_state->hw.active, 6656 "[ENCODER:%i] active %i with crtc active %i\n", 6657 encoder->base.base.id, active, 6658 new_crtc_state->hw.active); 6659 6660 I915_STATE_WARN(active && master_crtc->pipe != pipe, 6661 "Encoder connected to wrong pipe %c\n", 6662 pipe_name(pipe)); 6663 6664 if (active) 6665 intel_encoder_get_config(encoder, pipe_config); 6666 } 6667 6668 if (!new_crtc_state->hw.active) 6669 return; 6670 6671 intel_pipe_config_sanity_check(dev_priv, pipe_config); 6672 6673 if (!intel_pipe_config_compare(new_crtc_state, 6674 pipe_config, false)) { 6675 I915_STATE_WARN(1, "pipe state doesn't match!\n"); 6676 intel_dump_pipe_config(pipe_config, NULL, "[hw state]"); 6677 intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]"); 6678 } 6679 } 6680 6681 static void 6682 intel_verify_planes(struct intel_atomic_state *state) 6683 { 6684 struct intel_plane *plane; 6685 const struct intel_plane_state *plane_state; 6686 int i; 6687 6688 for_each_new_intel_plane_in_state(state, plane, 6689 plane_state, i) 6690 assert_plane(plane, plane_state->planar_slave || 6691 plane_state->uapi.visible); 6692 } 6693 6694 static void 6695 verify_single_dpll_state(struct drm_i915_private *dev_priv, 6696 struct intel_shared_dpll *pll, 6697 struct intel_crtc *crtc, 6698 struct intel_crtc_state *new_crtc_state) 6699 { 6700 struct intel_dpll_hw_state dpll_hw_state; 6701 u8 pipe_mask; 6702 bool active; 6703 6704 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); 6705 6706 drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name); 6707 6708 active = intel_dpll_get_hw_state(dev_priv, pll, &dpll_hw_state); 6709 6710 if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) { 6711 I915_STATE_WARN(!pll->on && pll->active_mask, 6712 "pll in active use but not on in sw tracking\n"); 6713 I915_STATE_WARN(pll->on && !pll->active_mask, 6714 "pll is on but not used by any active pipe\n"); 6715 I915_STATE_WARN(pll->on != active, 6716 "pll on state mismatch (expected %i, found %i)\n", 6717 pll->on, active); 6718 } 6719 6720 if (!crtc) { 6721 I915_STATE_WARN(pll->active_mask & ~pll->state.pipe_mask, 6722 "more active pll users than references: 0x%x vs 0x%x\n", 6723 pll->active_mask, pll->state.pipe_mask); 6724 6725 return; 6726 } 6727 6728 pipe_mask = BIT(crtc->pipe); 6729 6730 if (new_crtc_state->hw.active) 6731 I915_STATE_WARN(!(pll->active_mask & pipe_mask), 6732 "pll active mismatch (expected pipe %c in active mask 0x%x)\n", 6733 pipe_name(crtc->pipe), pll->active_mask); 6734 else 6735 I915_STATE_WARN(pll->active_mask & pipe_mask, 6736 "pll active mismatch (didn't expect pipe %c in active mask 0x%x)\n", 6737 pipe_name(crtc->pipe), pll->active_mask); 6738 6739 I915_STATE_WARN(!(pll->state.pipe_mask & pipe_mask), 6740 "pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n", 6741 pipe_mask, pll->state.pipe_mask); 6742 6743 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state, 6744 &dpll_hw_state, 6745 sizeof(dpll_hw_state)), 6746 "pll hw state mismatch\n"); 6747 } 6748 6749 static void 6750 verify_shared_dpll_state(struct intel_crtc *crtc, 6751 struct intel_crtc_state *old_crtc_state, 6752 struct intel_crtc_state *new_crtc_state) 6753 { 6754 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6755 6756 if (new_crtc_state->shared_dpll) 6757 verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state); 6758 6759 if (old_crtc_state->shared_dpll && 6760 old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) { 6761 u8 pipe_mask = BIT(crtc->pipe); 6762 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll; 6763 6764 I915_STATE_WARN(pll->active_mask & pipe_mask, 6765 "pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n", 6766 pipe_name(crtc->pipe), pll->active_mask); 6767 I915_STATE_WARN(pll->state.pipe_mask & pipe_mask, 6768 "pll enabled crtcs mismatch (found %x in enabled mask (0x%x))\n", 6769 pipe_name(crtc->pipe), pll->state.pipe_mask); 6770 } 6771 } 6772 6773 static void 6774 verify_mpllb_state(struct intel_atomic_state *state, 6775 struct intel_crtc_state *new_crtc_state) 6776 { 6777 struct drm_i915_private *i915 = to_i915(state->base.dev); 6778 struct intel_mpllb_state mpllb_hw_state = { 0 }; 6779 struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->mpllb_state; 6780 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 6781 struct intel_encoder *encoder; 6782 6783 if (!IS_DG2(i915)) 6784 return; 6785 6786 if (!new_crtc_state->hw.active) 6787 return; 6788 6789 encoder = intel_get_crtc_new_encoder(state, new_crtc_state); 6790 intel_mpllb_readout_hw_state(encoder, &mpllb_hw_state); 6791 6792 #define MPLLB_CHECK(name) do { \ 6793 if (mpllb_sw_state->name != mpllb_hw_state.name) { \ 6794 pipe_config_mismatch(false, crtc, "MPLLB:" __stringify(name), \ 6795 "(expected 0x%08x, found 0x%08x)", \ 6796 mpllb_sw_state->name, \ 6797 mpllb_hw_state.name); \ 6798 } \ 6799 } while (0) 6800 6801 MPLLB_CHECK(mpllb_cp); 6802 MPLLB_CHECK(mpllb_div); 6803 MPLLB_CHECK(mpllb_div2); 6804 MPLLB_CHECK(mpllb_fracn1); 6805 MPLLB_CHECK(mpllb_fracn2); 6806 MPLLB_CHECK(mpllb_sscen); 6807 MPLLB_CHECK(mpllb_sscstep); 6808 6809 /* 6810 * ref_control is handled by the hardware/firemware and never 6811 * programmed by the software, but the proper values are supplied 6812 * in the bspec for verification purposes. 6813 */ 6814 MPLLB_CHECK(ref_control); 6815 6816 #undef MPLLB_CHECK 6817 } 6818 6819 static void 6820 intel_modeset_verify_crtc(struct intel_crtc *crtc, 6821 struct intel_atomic_state *state, 6822 struct intel_crtc_state *old_crtc_state, 6823 struct intel_crtc_state *new_crtc_state) 6824 { 6825 if (!intel_crtc_needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe) 6826 return; 6827 6828 verify_wm_state(crtc, new_crtc_state); 6829 verify_connector_state(state, crtc); 6830 verify_crtc_state(crtc, old_crtc_state, new_crtc_state); 6831 verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state); 6832 verify_mpllb_state(state, new_crtc_state); 6833 } 6834 6835 static void 6836 verify_disabled_dpll_state(struct drm_i915_private *dev_priv) 6837 { 6838 int i; 6839 6840 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) 6841 verify_single_dpll_state(dev_priv, 6842 &dev_priv->dpll.shared_dplls[i], 6843 NULL, NULL); 6844 } 6845 6846 static void 6847 intel_modeset_verify_disabled(struct drm_i915_private *dev_priv, 6848 struct intel_atomic_state *state) 6849 { 6850 verify_encoder_state(dev_priv, state); 6851 verify_connector_state(state, NULL); 6852 verify_disabled_dpll_state(dev_priv); 6853 } 6854 6855 int intel_modeset_all_pipes(struct intel_atomic_state *state) 6856 { 6857 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6858 struct intel_crtc *crtc; 6859 6860 /* 6861 * Add all pipes to the state, and force 6862 * a modeset on all the active ones. 6863 */ 6864 for_each_intel_crtc(&dev_priv->drm, crtc) { 6865 struct intel_crtc_state *crtc_state; 6866 int ret; 6867 6868 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6869 if (IS_ERR(crtc_state)) 6870 return PTR_ERR(crtc_state); 6871 6872 if (!crtc_state->hw.active || 6873 drm_atomic_crtc_needs_modeset(&crtc_state->uapi)) 6874 continue; 6875 6876 crtc_state->uapi.mode_changed = true; 6877 6878 ret = drm_atomic_add_affected_connectors(&state->base, 6879 &crtc->base); 6880 if (ret) 6881 return ret; 6882 6883 ret = intel_atomic_add_affected_planes(state, crtc); 6884 if (ret) 6885 return ret; 6886 6887 crtc_state->update_planes |= crtc_state->active_planes; 6888 } 6889 6890 return 0; 6891 } 6892 6893 static void 6894 intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state) 6895 { 6896 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 6897 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6898 struct drm_display_mode adjusted_mode; 6899 6900 drm_mode_init(&adjusted_mode, &crtc_state->hw.adjusted_mode); 6901 6902 if (crtc_state->vrr.enable) { 6903 adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax; 6904 adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax; 6905 adjusted_mode.crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state); 6906 crtc->vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state); 6907 } 6908 6909 drm_calc_timestamping_constants(&crtc->base, &adjusted_mode); 6910 6911 crtc->mode_flags = crtc_state->mode_flags; 6912 6913 /* 6914 * The scanline counter increments at the leading edge of hsync. 6915 * 6916 * On most platforms it starts counting from vtotal-1 on the 6917 * first active line. That means the scanline counter value is 6918 * always one less than what we would expect. Ie. just after 6919 * start of vblank, which also occurs at start of hsync (on the 6920 * last active line), the scanline counter will read vblank_start-1. 6921 * 6922 * On gen2 the scanline counter starts counting from 1 instead 6923 * of vtotal-1, so we have to subtract one (or rather add vtotal-1 6924 * to keep the value positive), instead of adding one. 6925 * 6926 * On HSW+ the behaviour of the scanline counter depends on the output 6927 * type. For DP ports it behaves like most other platforms, but on HDMI 6928 * there's an extra 1 line difference. So we need to add two instead of 6929 * one to the value. 6930 * 6931 * On VLV/CHV DSI the scanline counter would appear to increment 6932 * approx. 1/3 of a scanline before start of vblank. Unfortunately 6933 * that means we can't tell whether we're in vblank or not while 6934 * we're on that particular line. We must still set scanline_offset 6935 * to 1 so that the vblank timestamps come out correct when we query 6936 * the scanline counter from within the vblank interrupt handler. 6937 * However if queried just before the start of vblank we'll get an 6938 * answer that's slightly in the future. 6939 */ 6940 if (DISPLAY_VER(dev_priv) == 2) { 6941 int vtotal; 6942 6943 vtotal = adjusted_mode.crtc_vtotal; 6944 if (adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 6945 vtotal /= 2; 6946 6947 crtc->scanline_offset = vtotal - 1; 6948 } else if (HAS_DDI(dev_priv) && 6949 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 6950 crtc->scanline_offset = 2; 6951 } else { 6952 crtc->scanline_offset = 1; 6953 } 6954 } 6955 6956 static void intel_modeset_clear_plls(struct intel_atomic_state *state) 6957 { 6958 struct intel_crtc_state *new_crtc_state; 6959 struct intel_crtc *crtc; 6960 int i; 6961 6962 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6963 if (!intel_crtc_needs_modeset(new_crtc_state)) 6964 continue; 6965 6966 intel_release_shared_dplls(state, crtc); 6967 } 6968 } 6969 6970 /* 6971 * This implements the workaround described in the "notes" section of the mode 6972 * set sequence documentation. When going from no pipes or single pipe to 6973 * multiple pipes, and planes are enabled after the pipe, we need to wait at 6974 * least 2 vblanks on the first pipe before enabling planes on the second pipe. 6975 */ 6976 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state) 6977 { 6978 struct intel_crtc_state *crtc_state; 6979 struct intel_crtc *crtc; 6980 struct intel_crtc_state *first_crtc_state = NULL; 6981 struct intel_crtc_state *other_crtc_state = NULL; 6982 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; 6983 int i; 6984 6985 /* look at all crtc's that are going to be enabled in during modeset */ 6986 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6987 if (!crtc_state->hw.active || 6988 !intel_crtc_needs_modeset(crtc_state)) 6989 continue; 6990 6991 if (first_crtc_state) { 6992 other_crtc_state = crtc_state; 6993 break; 6994 } else { 6995 first_crtc_state = crtc_state; 6996 first_pipe = crtc->pipe; 6997 } 6998 } 6999 7000 /* No workaround needed? */ 7001 if (!first_crtc_state) 7002 return 0; 7003 7004 /* w/a possibly needed, check how many crtc's are already enabled. */ 7005 for_each_intel_crtc(state->base.dev, crtc) { 7006 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 7007 if (IS_ERR(crtc_state)) 7008 return PTR_ERR(crtc_state); 7009 7010 crtc_state->hsw_workaround_pipe = INVALID_PIPE; 7011 7012 if (!crtc_state->hw.active || 7013 intel_crtc_needs_modeset(crtc_state)) 7014 continue; 7015 7016 /* 2 or more enabled crtcs means no need for w/a */ 7017 if (enabled_pipe != INVALID_PIPE) 7018 return 0; 7019 7020 enabled_pipe = crtc->pipe; 7021 } 7022 7023 if (enabled_pipe != INVALID_PIPE) 7024 first_crtc_state->hsw_workaround_pipe = enabled_pipe; 7025 else if (other_crtc_state) 7026 other_crtc_state->hsw_workaround_pipe = first_pipe; 7027 7028 return 0; 7029 } 7030 7031 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 7032 u8 active_pipes) 7033 { 7034 const struct intel_crtc_state *crtc_state; 7035 struct intel_crtc *crtc; 7036 int i; 7037 7038 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7039 if (crtc_state->hw.active) 7040 active_pipes |= BIT(crtc->pipe); 7041 else 7042 active_pipes &= ~BIT(crtc->pipe); 7043 } 7044 7045 return active_pipes; 7046 } 7047 7048 static int intel_modeset_checks(struct intel_atomic_state *state) 7049 { 7050 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7051 7052 state->modeset = true; 7053 7054 if (IS_HASWELL(dev_priv)) 7055 return hsw_mode_set_planes_workaround(state); 7056 7057 return 0; 7058 } 7059 7060 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state, 7061 struct intel_crtc_state *new_crtc_state) 7062 { 7063 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) 7064 return; 7065 7066 new_crtc_state->uapi.mode_changed = false; 7067 new_crtc_state->update_pipe = true; 7068 } 7069 7070 static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state, 7071 struct intel_crtc_state *new_crtc_state) 7072 { 7073 /* 7074 * If we're not doing the full modeset we want to 7075 * keep the current M/N values as they may be 7076 * sufficiently different to the computed values 7077 * to cause problems. 7078 * 7079 * FIXME: should really copy more fuzzy state here 7080 */ 7081 new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n; 7082 new_crtc_state->dp_m_n = old_crtc_state->dp_m_n; 7083 new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2; 7084 new_crtc_state->has_drrs = old_crtc_state->has_drrs; 7085 } 7086 7087 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state, 7088 struct intel_crtc *crtc, 7089 u8 plane_ids_mask) 7090 { 7091 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7092 struct intel_plane *plane; 7093 7094 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 7095 struct intel_plane_state *plane_state; 7096 7097 if ((plane_ids_mask & BIT(plane->id)) == 0) 7098 continue; 7099 7100 plane_state = intel_atomic_get_plane_state(state, plane); 7101 if (IS_ERR(plane_state)) 7102 return PTR_ERR(plane_state); 7103 } 7104 7105 return 0; 7106 } 7107 7108 int intel_atomic_add_affected_planes(struct intel_atomic_state *state, 7109 struct intel_crtc *crtc) 7110 { 7111 const struct intel_crtc_state *old_crtc_state = 7112 intel_atomic_get_old_crtc_state(state, crtc); 7113 const struct intel_crtc_state *new_crtc_state = 7114 intel_atomic_get_new_crtc_state(state, crtc); 7115 7116 return intel_crtc_add_planes_to_state(state, crtc, 7117 old_crtc_state->enabled_planes | 7118 new_crtc_state->enabled_planes); 7119 } 7120 7121 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv) 7122 { 7123 /* See {hsw,vlv,ivb}_plane_ratio() */ 7124 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) || 7125 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) || 7126 IS_IVYBRIDGE(dev_priv); 7127 } 7128 7129 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state, 7130 struct intel_crtc *crtc, 7131 struct intel_crtc *other) 7132 { 7133 const struct intel_plane_state *plane_state; 7134 struct intel_plane *plane; 7135 u8 plane_ids = 0; 7136 int i; 7137 7138 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 7139 if (plane->pipe == crtc->pipe) 7140 plane_ids |= BIT(plane->id); 7141 } 7142 7143 return intel_crtc_add_planes_to_state(state, other, plane_ids); 7144 } 7145 7146 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state) 7147 { 7148 struct drm_i915_private *i915 = to_i915(state->base.dev); 7149 const struct intel_crtc_state *crtc_state; 7150 struct intel_crtc *crtc; 7151 int i; 7152 7153 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7154 struct intel_crtc *other; 7155 7156 for_each_intel_crtc_in_pipe_mask(&i915->drm, other, 7157 crtc_state->bigjoiner_pipes) { 7158 int ret; 7159 7160 if (crtc == other) 7161 continue; 7162 7163 ret = intel_crtc_add_bigjoiner_planes(state, crtc, other); 7164 if (ret) 7165 return ret; 7166 } 7167 } 7168 7169 return 0; 7170 } 7171 7172 static int intel_atomic_check_planes(struct intel_atomic_state *state) 7173 { 7174 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7175 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7176 struct intel_plane_state *plane_state; 7177 struct intel_plane *plane; 7178 struct intel_crtc *crtc; 7179 int i, ret; 7180 7181 ret = icl_add_linked_planes(state); 7182 if (ret) 7183 return ret; 7184 7185 ret = intel_bigjoiner_add_affected_planes(state); 7186 if (ret) 7187 return ret; 7188 7189 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 7190 ret = intel_plane_atomic_check(state, plane); 7191 if (ret) { 7192 drm_dbg_atomic(&dev_priv->drm, 7193 "[PLANE:%d:%s] atomic driver check failed\n", 7194 plane->base.base.id, plane->base.name); 7195 return ret; 7196 } 7197 } 7198 7199 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7200 new_crtc_state, i) { 7201 u8 old_active_planes, new_active_planes; 7202 7203 ret = icl_check_nv12_planes(new_crtc_state); 7204 if (ret) 7205 return ret; 7206 7207 /* 7208 * On some platforms the number of active planes affects 7209 * the planes' minimum cdclk calculation. Add such planes 7210 * to the state before we compute the minimum cdclk. 7211 */ 7212 if (!active_planes_affects_min_cdclk(dev_priv)) 7213 continue; 7214 7215 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 7216 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 7217 7218 if (hweight8(old_active_planes) == hweight8(new_active_planes)) 7219 continue; 7220 7221 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes); 7222 if (ret) 7223 return ret; 7224 } 7225 7226 return 0; 7227 } 7228 7229 static int intel_atomic_check_crtcs(struct intel_atomic_state *state) 7230 { 7231 struct intel_crtc_state *crtc_state; 7232 struct intel_crtc *crtc; 7233 int i; 7234 7235 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7236 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 7237 int ret; 7238 7239 ret = intel_crtc_atomic_check(state, crtc); 7240 if (ret) { 7241 drm_dbg_atomic(&i915->drm, 7242 "[CRTC:%d:%s] atomic driver check failed\n", 7243 crtc->base.base.id, crtc->base.name); 7244 return ret; 7245 } 7246 } 7247 7248 return 0; 7249 } 7250 7251 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, 7252 u8 transcoders) 7253 { 7254 const struct intel_crtc_state *new_crtc_state; 7255 struct intel_crtc *crtc; 7256 int i; 7257 7258 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7259 if (new_crtc_state->hw.enable && 7260 transcoders & BIT(new_crtc_state->cpu_transcoder) && 7261 intel_crtc_needs_modeset(new_crtc_state)) 7262 return true; 7263 } 7264 7265 return false; 7266 } 7267 7268 static bool intel_pipes_need_modeset(struct intel_atomic_state *state, 7269 u8 pipes) 7270 { 7271 const struct intel_crtc_state *new_crtc_state; 7272 struct intel_crtc *crtc; 7273 int i; 7274 7275 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7276 if (new_crtc_state->hw.enable && 7277 pipes & BIT(crtc->pipe) && 7278 intel_crtc_needs_modeset(new_crtc_state)) 7279 return true; 7280 } 7281 7282 return false; 7283 } 7284 7285 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state, 7286 struct intel_crtc *master_crtc) 7287 { 7288 struct drm_i915_private *i915 = to_i915(state->base.dev); 7289 struct intel_crtc_state *master_crtc_state = 7290 intel_atomic_get_new_crtc_state(state, master_crtc); 7291 struct intel_crtc *slave_crtc; 7292 7293 if (!master_crtc_state->bigjoiner_pipes) 7294 return 0; 7295 7296 /* sanity check */ 7297 if (drm_WARN_ON(&i915->drm, 7298 master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state))) 7299 return -EINVAL; 7300 7301 if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) { 7302 drm_dbg_kms(&i915->drm, 7303 "[CRTC:%d:%s] Cannot act as big joiner master " 7304 "(need 0x%x as pipes, only 0x%x possible)\n", 7305 master_crtc->base.base.id, master_crtc->base.name, 7306 master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915)); 7307 return -EINVAL; 7308 } 7309 7310 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 7311 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 7312 struct intel_crtc_state *slave_crtc_state; 7313 int ret; 7314 7315 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc); 7316 if (IS_ERR(slave_crtc_state)) 7317 return PTR_ERR(slave_crtc_state); 7318 7319 /* master being enabled, slave was already configured? */ 7320 if (slave_crtc_state->uapi.enable) { 7321 drm_dbg_kms(&i915->drm, 7322 "[CRTC:%d:%s] Slave is enabled as normal CRTC, but " 7323 "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n", 7324 slave_crtc->base.base.id, slave_crtc->base.name, 7325 master_crtc->base.base.id, master_crtc->base.name); 7326 return -EINVAL; 7327 } 7328 7329 /* 7330 * The state copy logic assumes the master crtc gets processed 7331 * before the slave crtc during the main compute_config loop. 7332 * This works because the crtcs are created in pipe order, 7333 * and the hardware requires master pipe < slave pipe as well. 7334 * Should that change we need to rethink the logic. 7335 */ 7336 if (WARN_ON(drm_crtc_index(&master_crtc->base) > 7337 drm_crtc_index(&slave_crtc->base))) 7338 return -EINVAL; 7339 7340 drm_dbg_kms(&i915->drm, 7341 "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n", 7342 slave_crtc->base.base.id, slave_crtc->base.name, 7343 master_crtc->base.base.id, master_crtc->base.name); 7344 7345 slave_crtc_state->bigjoiner_pipes = 7346 master_crtc_state->bigjoiner_pipes; 7347 7348 ret = copy_bigjoiner_crtc_state_modeset(state, slave_crtc); 7349 if (ret) 7350 return ret; 7351 } 7352 7353 return 0; 7354 } 7355 7356 static void kill_bigjoiner_slave(struct intel_atomic_state *state, 7357 struct intel_crtc *master_crtc) 7358 { 7359 struct drm_i915_private *i915 = to_i915(state->base.dev); 7360 struct intel_crtc_state *master_crtc_state = 7361 intel_atomic_get_new_crtc_state(state, master_crtc); 7362 struct intel_crtc *slave_crtc; 7363 7364 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 7365 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 7366 struct intel_crtc_state *slave_crtc_state = 7367 intel_atomic_get_new_crtc_state(state, slave_crtc); 7368 7369 slave_crtc_state->bigjoiner_pipes = 0; 7370 7371 intel_crtc_copy_uapi_to_hw_state_modeset(state, slave_crtc); 7372 } 7373 7374 master_crtc_state->bigjoiner_pipes = 0; 7375 } 7376 7377 /** 7378 * DOC: asynchronous flip implementation 7379 * 7380 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC 7381 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL. 7382 * Correspondingly, support is currently added for primary plane only. 7383 * 7384 * Async flip can only change the plane surface address, so anything else 7385 * changing is rejected from the intel_async_flip_check_hw() function. 7386 * Once this check is cleared, flip done interrupt is enabled using 7387 * the intel_crtc_enable_flip_done() function. 7388 * 7389 * As soon as the surface address register is written, flip done interrupt is 7390 * generated and the requested events are sent to the usersapce in the interrupt 7391 * handler itself. The timestamp and sequence sent during the flip done event 7392 * correspond to the last vblank and have no relation to the actual time when 7393 * the flip done event was sent. 7394 */ 7395 static int intel_async_flip_check_uapi(struct intel_atomic_state *state, 7396 struct intel_crtc *crtc) 7397 { 7398 struct drm_i915_private *i915 = to_i915(state->base.dev); 7399 const struct intel_crtc_state *new_crtc_state = 7400 intel_atomic_get_new_crtc_state(state, crtc); 7401 const struct intel_plane_state *old_plane_state; 7402 struct intel_plane_state *new_plane_state; 7403 struct intel_plane *plane; 7404 int i; 7405 7406 if (!new_crtc_state->uapi.async_flip) 7407 return 0; 7408 7409 if (!new_crtc_state->uapi.active) { 7410 drm_dbg_kms(&i915->drm, 7411 "[CRTC:%d:%s] not active\n", 7412 crtc->base.base.id, crtc->base.name); 7413 return -EINVAL; 7414 } 7415 7416 if (intel_crtc_needs_modeset(new_crtc_state)) { 7417 drm_dbg_kms(&i915->drm, 7418 "[CRTC:%d:%s] modeset required\n", 7419 crtc->base.base.id, crtc->base.name); 7420 return -EINVAL; 7421 } 7422 7423 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 7424 new_plane_state, i) { 7425 if (plane->pipe != crtc->pipe) 7426 continue; 7427 7428 /* 7429 * TODO: Async flip is only supported through the page flip IOCTL 7430 * as of now. So support currently added for primary plane only. 7431 * Support for other planes on platforms on which supports 7432 * this(vlv/chv and icl+) should be added when async flip is 7433 * enabled in the atomic IOCTL path. 7434 */ 7435 if (!plane->async_flip) { 7436 drm_dbg_kms(&i915->drm, 7437 "[PLANE:%d:%s] async flip not supported\n", 7438 plane->base.base.id, plane->base.name); 7439 return -EINVAL; 7440 } 7441 7442 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) { 7443 drm_dbg_kms(&i915->drm, 7444 "[PLANE:%d:%s] no old or new framebuffer\n", 7445 plane->base.base.id, plane->base.name); 7446 return -EINVAL; 7447 } 7448 } 7449 7450 return 0; 7451 } 7452 7453 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc) 7454 { 7455 struct drm_i915_private *i915 = to_i915(state->base.dev); 7456 const struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7457 const struct intel_plane_state *new_plane_state, *old_plane_state; 7458 struct intel_plane *plane; 7459 int i; 7460 7461 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 7462 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 7463 7464 if (!new_crtc_state->uapi.async_flip) 7465 return 0; 7466 7467 if (!new_crtc_state->hw.active) { 7468 drm_dbg_kms(&i915->drm, 7469 "[CRTC:%d:%s] not active\n", 7470 crtc->base.base.id, crtc->base.name); 7471 return -EINVAL; 7472 } 7473 7474 if (intel_crtc_needs_modeset(new_crtc_state)) { 7475 drm_dbg_kms(&i915->drm, 7476 "[CRTC:%d:%s] modeset required\n", 7477 crtc->base.base.id, crtc->base.name); 7478 return -EINVAL; 7479 } 7480 7481 if (old_crtc_state->active_planes != new_crtc_state->active_planes) { 7482 drm_dbg_kms(&i915->drm, 7483 "[CRTC:%d:%s] Active planes cannot be in async flip\n", 7484 crtc->base.base.id, crtc->base.name); 7485 return -EINVAL; 7486 } 7487 7488 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 7489 new_plane_state, i) { 7490 if (plane->pipe != crtc->pipe) 7491 continue; 7492 7493 /* 7494 * Only async flip capable planes should be in the state 7495 * if we're really about to ask the hardware to perform 7496 * an async flip. We should never get this far otherwise. 7497 */ 7498 if (drm_WARN_ON(&i915->drm, 7499 new_crtc_state->do_async_flip && !plane->async_flip)) 7500 return -EINVAL; 7501 7502 /* 7503 * Only check async flip capable planes other planes 7504 * may be involved in the initial commit due to 7505 * the wm0/ddb optimization. 7506 * 7507 * TODO maybe should track which planes actually 7508 * were requested to do the async flip... 7509 */ 7510 if (!plane->async_flip) 7511 continue; 7512 7513 /* 7514 * FIXME: This check is kept generic for all platforms. 7515 * Need to verify this for all gen9 platforms to enable 7516 * this selectively if required. 7517 */ 7518 switch (new_plane_state->hw.fb->modifier) { 7519 case I915_FORMAT_MOD_X_TILED: 7520 case I915_FORMAT_MOD_Y_TILED: 7521 case I915_FORMAT_MOD_Yf_TILED: 7522 case I915_FORMAT_MOD_4_TILED: 7523 break; 7524 default: 7525 drm_dbg_kms(&i915->drm, 7526 "[PLANE:%d:%s] Modifier does not support async flips\n", 7527 plane->base.base.id, plane->base.name); 7528 return -EINVAL; 7529 } 7530 7531 if (new_plane_state->hw.fb->format->num_planes > 1) { 7532 drm_dbg_kms(&i915->drm, 7533 "[PLANE:%d:%s] Planar formats do not support async flips\n", 7534 plane->base.base.id, plane->base.name); 7535 return -EINVAL; 7536 } 7537 7538 if (old_plane_state->view.color_plane[0].mapping_stride != 7539 new_plane_state->view.color_plane[0].mapping_stride) { 7540 drm_dbg_kms(&i915->drm, 7541 "[PLANE:%d:%s] Stride cannot be changed in async flip\n", 7542 plane->base.base.id, plane->base.name); 7543 return -EINVAL; 7544 } 7545 7546 if (old_plane_state->hw.fb->modifier != 7547 new_plane_state->hw.fb->modifier) { 7548 drm_dbg_kms(&i915->drm, 7549 "[PLANE:%d:%s] Modifier cannot be changed in async flip\n", 7550 plane->base.base.id, plane->base.name); 7551 return -EINVAL; 7552 } 7553 7554 if (old_plane_state->hw.fb->format != 7555 new_plane_state->hw.fb->format) { 7556 drm_dbg_kms(&i915->drm, 7557 "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n", 7558 plane->base.base.id, plane->base.name); 7559 return -EINVAL; 7560 } 7561 7562 if (old_plane_state->hw.rotation != 7563 new_plane_state->hw.rotation) { 7564 drm_dbg_kms(&i915->drm, 7565 "[PLANE:%d:%s] Rotation cannot be changed in async flip\n", 7566 plane->base.base.id, plane->base.name); 7567 return -EINVAL; 7568 } 7569 7570 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) || 7571 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) { 7572 drm_dbg_kms(&i915->drm, 7573 "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n", 7574 plane->base.base.id, plane->base.name); 7575 return -EINVAL; 7576 } 7577 7578 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) { 7579 drm_dbg_kms(&i915->drm, 7580 "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n", 7581 plane->base.base.id, plane->base.name); 7582 return -EINVAL; 7583 } 7584 7585 if (old_plane_state->hw.pixel_blend_mode != 7586 new_plane_state->hw.pixel_blend_mode) { 7587 drm_dbg_kms(&i915->drm, 7588 "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n", 7589 plane->base.base.id, plane->base.name); 7590 return -EINVAL; 7591 } 7592 7593 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) { 7594 drm_dbg_kms(&i915->drm, 7595 "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n", 7596 plane->base.base.id, plane->base.name); 7597 return -EINVAL; 7598 } 7599 7600 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) { 7601 drm_dbg_kms(&i915->drm, 7602 "[PLANE:%d:%s] Color range cannot be changed in async flip\n", 7603 plane->base.base.id, plane->base.name); 7604 return -EINVAL; 7605 } 7606 7607 /* plane decryption is allow to change only in synchronous flips */ 7608 if (old_plane_state->decrypt != new_plane_state->decrypt) { 7609 drm_dbg_kms(&i915->drm, 7610 "[PLANE:%d:%s] Decryption cannot be changed in async flip\n", 7611 plane->base.base.id, plane->base.name); 7612 return -EINVAL; 7613 } 7614 } 7615 7616 return 0; 7617 } 7618 7619 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state) 7620 { 7621 struct drm_i915_private *i915 = to_i915(state->base.dev); 7622 struct intel_crtc_state *crtc_state; 7623 struct intel_crtc *crtc; 7624 u8 affected_pipes = 0; 7625 u8 modeset_pipes = 0; 7626 int i; 7627 7628 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7629 affected_pipes |= crtc_state->bigjoiner_pipes; 7630 if (intel_crtc_needs_modeset(crtc_state)) 7631 modeset_pipes |= crtc_state->bigjoiner_pipes; 7632 } 7633 7634 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) { 7635 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 7636 if (IS_ERR(crtc_state)) 7637 return PTR_ERR(crtc_state); 7638 } 7639 7640 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) { 7641 int ret; 7642 7643 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 7644 7645 crtc_state->uapi.mode_changed = true; 7646 7647 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); 7648 if (ret) 7649 return ret; 7650 7651 ret = intel_atomic_add_affected_planes(state, crtc); 7652 if (ret) 7653 return ret; 7654 } 7655 7656 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7657 /* Kill old bigjoiner link, we may re-establish afterwards */ 7658 if (intel_crtc_needs_modeset(crtc_state) && 7659 intel_crtc_is_bigjoiner_master(crtc_state)) 7660 kill_bigjoiner_slave(state, crtc); 7661 } 7662 7663 return 0; 7664 } 7665 7666 /** 7667 * intel_atomic_check - validate state object 7668 * @dev: drm device 7669 * @_state: state to validate 7670 */ 7671 static int intel_atomic_check(struct drm_device *dev, 7672 struct drm_atomic_state *_state) 7673 { 7674 struct drm_i915_private *dev_priv = to_i915(dev); 7675 struct intel_atomic_state *state = to_intel_atomic_state(_state); 7676 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7677 struct intel_crtc *crtc; 7678 int ret, i; 7679 bool any_ms = false; 7680 7681 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7682 new_crtc_state, i) { 7683 if (new_crtc_state->inherited != old_crtc_state->inherited) 7684 new_crtc_state->uapi.mode_changed = true; 7685 7686 if (new_crtc_state->uapi.scaling_filter != 7687 old_crtc_state->uapi.scaling_filter) 7688 new_crtc_state->uapi.mode_changed = true; 7689 } 7690 7691 intel_vrr_check_modeset(state); 7692 7693 ret = drm_atomic_helper_check_modeset(dev, &state->base); 7694 if (ret) 7695 goto fail; 7696 7697 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7698 ret = intel_async_flip_check_uapi(state, crtc); 7699 if (ret) 7700 return ret; 7701 } 7702 7703 ret = intel_bigjoiner_add_affected_crtcs(state); 7704 if (ret) 7705 goto fail; 7706 7707 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7708 new_crtc_state, i) { 7709 if (!intel_crtc_needs_modeset(new_crtc_state)) { 7710 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 7711 copy_bigjoiner_crtc_state_nomodeset(state, crtc); 7712 else 7713 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 7714 continue; 7715 } 7716 7717 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) { 7718 drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable); 7719 continue; 7720 } 7721 7722 ret = intel_crtc_prepare_cleared_state(state, crtc); 7723 if (ret) 7724 goto fail; 7725 7726 if (!new_crtc_state->hw.enable) 7727 continue; 7728 7729 ret = intel_modeset_pipe_config(state, crtc); 7730 if (ret) 7731 goto fail; 7732 7733 ret = intel_atomic_check_bigjoiner(state, crtc); 7734 if (ret) 7735 goto fail; 7736 } 7737 7738 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7739 new_crtc_state, i) { 7740 if (!intel_crtc_needs_modeset(new_crtc_state)) 7741 continue; 7742 7743 ret = intel_modeset_pipe_config_late(state, crtc); 7744 if (ret) 7745 goto fail; 7746 7747 intel_crtc_check_fastset(old_crtc_state, new_crtc_state); 7748 } 7749 7750 /** 7751 * Check if fastset is allowed by external dependencies like other 7752 * pipes and transcoders. 7753 * 7754 * Right now it only forces a fullmodeset when the MST master 7755 * transcoder did not changed but the pipe of the master transcoder 7756 * needs a fullmodeset so all slaves also needs to do a fullmodeset or 7757 * in case of port synced crtcs, if one of the synced crtcs 7758 * needs a full modeset, all other synced crtcs should be 7759 * forced a full modeset. 7760 */ 7761 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7762 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state)) 7763 continue; 7764 7765 if (intel_dp_mst_is_slave_trans(new_crtc_state)) { 7766 enum transcoder master = new_crtc_state->mst_master_transcoder; 7767 7768 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) { 7769 new_crtc_state->uapi.mode_changed = true; 7770 new_crtc_state->update_pipe = false; 7771 } 7772 } 7773 7774 if (is_trans_port_sync_mode(new_crtc_state)) { 7775 u8 trans = new_crtc_state->sync_mode_slaves_mask; 7776 7777 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER) 7778 trans |= BIT(new_crtc_state->master_transcoder); 7779 7780 if (intel_cpu_transcoders_need_modeset(state, trans)) { 7781 new_crtc_state->uapi.mode_changed = true; 7782 new_crtc_state->update_pipe = false; 7783 } 7784 } 7785 7786 if (new_crtc_state->bigjoiner_pipes) { 7787 if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) { 7788 new_crtc_state->uapi.mode_changed = true; 7789 new_crtc_state->update_pipe = false; 7790 } 7791 } 7792 } 7793 7794 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7795 new_crtc_state, i) { 7796 if (intel_crtc_needs_modeset(new_crtc_state)) { 7797 any_ms = true; 7798 continue; 7799 } 7800 7801 if (!new_crtc_state->update_pipe) 7802 continue; 7803 7804 intel_crtc_copy_fastset(old_crtc_state, new_crtc_state); 7805 } 7806 7807 if (any_ms && !check_digital_port_conflicts(state)) { 7808 drm_dbg_kms(&dev_priv->drm, 7809 "rejecting conflicting digital port configuration\n"); 7810 ret = -EINVAL; 7811 goto fail; 7812 } 7813 7814 ret = drm_dp_mst_atomic_check(&state->base); 7815 if (ret) 7816 goto fail; 7817 7818 ret = intel_atomic_check_planes(state); 7819 if (ret) 7820 goto fail; 7821 7822 ret = intel_compute_global_watermarks(state); 7823 if (ret) 7824 goto fail; 7825 7826 ret = intel_bw_atomic_check(state); 7827 if (ret) 7828 goto fail; 7829 7830 ret = intel_cdclk_atomic_check(state, &any_ms); 7831 if (ret) 7832 goto fail; 7833 7834 if (intel_any_crtc_needs_modeset(state)) 7835 any_ms = true; 7836 7837 if (any_ms) { 7838 ret = intel_modeset_checks(state); 7839 if (ret) 7840 goto fail; 7841 7842 ret = intel_modeset_calc_cdclk(state); 7843 if (ret) 7844 return ret; 7845 7846 intel_modeset_clear_plls(state); 7847 } 7848 7849 ret = intel_atomic_check_crtcs(state); 7850 if (ret) 7851 goto fail; 7852 7853 ret = intel_fbc_atomic_check(state); 7854 if (ret) 7855 goto fail; 7856 7857 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7858 new_crtc_state, i) { 7859 ret = intel_async_flip_check_hw(state, crtc); 7860 if (ret) 7861 goto fail; 7862 7863 if (!intel_crtc_needs_modeset(new_crtc_state) && 7864 !new_crtc_state->update_pipe) 7865 continue; 7866 7867 intel_dump_pipe_config(new_crtc_state, state, 7868 intel_crtc_needs_modeset(new_crtc_state) ? 7869 "[modeset]" : "[fastset]"); 7870 } 7871 7872 return 0; 7873 7874 fail: 7875 if (ret == -EDEADLK) 7876 return ret; 7877 7878 /* 7879 * FIXME would probably be nice to know which crtc specifically 7880 * caused the failure, in cases where we can pinpoint it. 7881 */ 7882 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7883 new_crtc_state, i) 7884 intel_dump_pipe_config(new_crtc_state, state, "[failed]"); 7885 7886 return ret; 7887 } 7888 7889 static int intel_atomic_prepare_commit(struct intel_atomic_state *state) 7890 { 7891 struct intel_crtc_state *crtc_state; 7892 struct intel_crtc *crtc; 7893 int i, ret; 7894 7895 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base); 7896 if (ret < 0) 7897 return ret; 7898 7899 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7900 bool mode_changed = intel_crtc_needs_modeset(crtc_state); 7901 7902 if (mode_changed || crtc_state->update_pipe || 7903 crtc_state->uapi.color_mgmt_changed) { 7904 intel_dsb_prepare(crtc_state); 7905 } 7906 } 7907 7908 return 0; 7909 } 7910 7911 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 7912 struct intel_crtc_state *crtc_state) 7913 { 7914 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 7915 7916 if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes) 7917 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 7918 7919 if (crtc_state->has_pch_encoder) { 7920 enum pipe pch_transcoder = 7921 intel_crtc_pch_transcoder(crtc); 7922 7923 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true); 7924 } 7925 } 7926 7927 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, 7928 const struct intel_crtc_state *new_crtc_state) 7929 { 7930 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 7931 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 7932 7933 /* 7934 * Update pipe size and adjust fitter if needed: the reason for this is 7935 * that in compute_mode_changes we check the native mode (not the pfit 7936 * mode) to see if we can flip rather than do a full mode set. In the 7937 * fastboot case, we'll flip, but if we don't update the pipesrc and 7938 * pfit state, we'll end up with a big fb scanned out into the wrong 7939 * sized surface. 7940 */ 7941 intel_set_pipe_src_size(new_crtc_state); 7942 7943 /* on skylake this is done by detaching scalers */ 7944 if (DISPLAY_VER(dev_priv) >= 9) { 7945 if (new_crtc_state->pch_pfit.enabled) 7946 skl_pfit_enable(new_crtc_state); 7947 } else if (HAS_PCH_SPLIT(dev_priv)) { 7948 if (new_crtc_state->pch_pfit.enabled) 7949 ilk_pfit_enable(new_crtc_state); 7950 else if (old_crtc_state->pch_pfit.enabled) 7951 ilk_pfit_disable(old_crtc_state); 7952 } 7953 7954 /* 7955 * The register is supposedly single buffered so perhaps 7956 * not 100% correct to do this here. But SKL+ calculate 7957 * this based on the adjust pixel rate so pfit changes do 7958 * affect it and so it must be updated for fastsets. 7959 * HSW/BDW only really need this here for fastboot, after 7960 * that the value should not change without a full modeset. 7961 */ 7962 if (DISPLAY_VER(dev_priv) >= 9 || 7963 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 7964 hsw_set_linetime_wm(new_crtc_state); 7965 } 7966 7967 static void commit_pipe_pre_planes(struct intel_atomic_state *state, 7968 struct intel_crtc *crtc) 7969 { 7970 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7971 const struct intel_crtc_state *old_crtc_state = 7972 intel_atomic_get_old_crtc_state(state, crtc); 7973 const struct intel_crtc_state *new_crtc_state = 7974 intel_atomic_get_new_crtc_state(state, crtc); 7975 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 7976 7977 /* 7978 * During modesets pipe configuration was programmed as the 7979 * CRTC was enabled. 7980 */ 7981 if (!modeset) { 7982 if (new_crtc_state->uapi.color_mgmt_changed || 7983 new_crtc_state->update_pipe) 7984 intel_color_commit_arm(new_crtc_state); 7985 7986 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 7987 bdw_set_pipemisc(new_crtc_state); 7988 7989 if (new_crtc_state->update_pipe) 7990 intel_pipe_fastset(old_crtc_state, new_crtc_state); 7991 } 7992 7993 intel_psr2_program_trans_man_trk_ctl(new_crtc_state); 7994 7995 intel_atomic_update_watermarks(state, crtc); 7996 } 7997 7998 static void commit_pipe_post_planes(struct intel_atomic_state *state, 7999 struct intel_crtc *crtc) 8000 { 8001 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8002 const struct intel_crtc_state *new_crtc_state = 8003 intel_atomic_get_new_crtc_state(state, crtc); 8004 8005 /* 8006 * Disable the scaler(s) after the plane(s) so that we don't 8007 * get a catastrophic underrun even if the two operations 8008 * end up happening in two different frames. 8009 */ 8010 if (DISPLAY_VER(dev_priv) >= 9 && 8011 !intel_crtc_needs_modeset(new_crtc_state)) 8012 skl_detach_scalers(new_crtc_state); 8013 } 8014 8015 static void intel_enable_crtc(struct intel_atomic_state *state, 8016 struct intel_crtc *crtc) 8017 { 8018 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8019 const struct intel_crtc_state *new_crtc_state = 8020 intel_atomic_get_new_crtc_state(state, crtc); 8021 8022 if (!intel_crtc_needs_modeset(new_crtc_state)) 8023 return; 8024 8025 intel_crtc_update_active_timings(new_crtc_state); 8026 8027 dev_priv->display->crtc_enable(state, crtc); 8028 8029 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 8030 return; 8031 8032 /* vblanks work again, re-enable pipe CRC. */ 8033 intel_crtc_enable_pipe_crc(crtc); 8034 } 8035 8036 static void intel_update_crtc(struct intel_atomic_state *state, 8037 struct intel_crtc *crtc) 8038 { 8039 struct drm_i915_private *i915 = to_i915(state->base.dev); 8040 const struct intel_crtc_state *old_crtc_state = 8041 intel_atomic_get_old_crtc_state(state, crtc); 8042 struct intel_crtc_state *new_crtc_state = 8043 intel_atomic_get_new_crtc_state(state, crtc); 8044 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 8045 8046 if (!modeset) { 8047 if (new_crtc_state->preload_luts && 8048 (new_crtc_state->uapi.color_mgmt_changed || 8049 new_crtc_state->update_pipe)) 8050 intel_color_load_luts(new_crtc_state); 8051 8052 intel_pre_plane_update(state, crtc); 8053 8054 if (new_crtc_state->update_pipe) 8055 intel_encoders_update_pipe(state, crtc); 8056 8057 if (DISPLAY_VER(i915) >= 11 && 8058 new_crtc_state->update_pipe) 8059 icl_set_pipe_chicken(new_crtc_state); 8060 } 8061 8062 intel_fbc_update(state, crtc); 8063 8064 if (!modeset && 8065 (new_crtc_state->uapi.color_mgmt_changed || 8066 new_crtc_state->update_pipe)) 8067 intel_color_commit_noarm(new_crtc_state); 8068 8069 intel_crtc_planes_update_noarm(state, crtc); 8070 8071 /* Perform vblank evasion around commit operation */ 8072 intel_pipe_update_start(new_crtc_state); 8073 8074 commit_pipe_pre_planes(state, crtc); 8075 8076 intel_crtc_planes_update_arm(state, crtc); 8077 8078 commit_pipe_post_planes(state, crtc); 8079 8080 intel_pipe_update_end(new_crtc_state); 8081 8082 /* 8083 * We usually enable FIFO underrun interrupts as part of the 8084 * CRTC enable sequence during modesets. But when we inherit a 8085 * valid pipe configuration from the BIOS we need to take care 8086 * of enabling them on the CRTC's first fastset. 8087 */ 8088 if (new_crtc_state->update_pipe && !modeset && 8089 old_crtc_state->inherited) 8090 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state); 8091 } 8092 8093 static void intel_old_crtc_state_disables(struct intel_atomic_state *state, 8094 struct intel_crtc_state *old_crtc_state, 8095 struct intel_crtc_state *new_crtc_state, 8096 struct intel_crtc *crtc) 8097 { 8098 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8099 8100 /* 8101 * We need to disable pipe CRC before disabling the pipe, 8102 * or we race against vblank off. 8103 */ 8104 intel_crtc_disable_pipe_crc(crtc); 8105 8106 dev_priv->display->crtc_disable(state, crtc); 8107 crtc->active = false; 8108 intel_fbc_disable(crtc); 8109 intel_disable_shared_dpll(old_crtc_state); 8110 8111 /* FIXME unify this for all platforms */ 8112 if (!new_crtc_state->hw.active && 8113 !HAS_GMCH(dev_priv)) 8114 intel_initial_watermarks(state, crtc); 8115 } 8116 8117 static void intel_commit_modeset_disables(struct intel_atomic_state *state) 8118 { 8119 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 8120 struct intel_crtc *crtc; 8121 u32 handled = 0; 8122 int i; 8123 8124 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8125 new_crtc_state, i) { 8126 if (!intel_crtc_needs_modeset(new_crtc_state)) 8127 continue; 8128 8129 if (!old_crtc_state->hw.active) 8130 continue; 8131 8132 intel_pre_plane_update(state, crtc); 8133 intel_crtc_disable_planes(state, crtc); 8134 } 8135 8136 /* Only disable port sync and MST slaves */ 8137 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8138 new_crtc_state, i) { 8139 if (!intel_crtc_needs_modeset(new_crtc_state)) 8140 continue; 8141 8142 if (!old_crtc_state->hw.active) 8143 continue; 8144 8145 /* In case of Transcoder port Sync master slave CRTCs can be 8146 * assigned in any order and we need to make sure that 8147 * slave CRTCs are disabled first and then master CRTC since 8148 * Slave vblanks are masked till Master Vblanks. 8149 */ 8150 if (!is_trans_port_sync_slave(old_crtc_state) && 8151 !intel_dp_mst_is_slave_trans(old_crtc_state) && 8152 !intel_crtc_is_bigjoiner_slave(old_crtc_state)) 8153 continue; 8154 8155 intel_old_crtc_state_disables(state, old_crtc_state, 8156 new_crtc_state, crtc); 8157 handled |= BIT(crtc->pipe); 8158 } 8159 8160 /* Disable everything else left on */ 8161 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8162 new_crtc_state, i) { 8163 if (!intel_crtc_needs_modeset(new_crtc_state) || 8164 (handled & BIT(crtc->pipe))) 8165 continue; 8166 8167 if (!old_crtc_state->hw.active) 8168 continue; 8169 8170 intel_old_crtc_state_disables(state, old_crtc_state, 8171 new_crtc_state, crtc); 8172 } 8173 } 8174 8175 static void intel_commit_modeset_enables(struct intel_atomic_state *state) 8176 { 8177 struct intel_crtc_state *new_crtc_state; 8178 struct intel_crtc *crtc; 8179 int i; 8180 8181 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8182 if (!new_crtc_state->hw.active) 8183 continue; 8184 8185 intel_enable_crtc(state, crtc); 8186 intel_update_crtc(state, crtc); 8187 } 8188 } 8189 8190 static void skl_commit_modeset_enables(struct intel_atomic_state *state) 8191 { 8192 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8193 struct intel_crtc *crtc; 8194 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 8195 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; 8196 u8 update_pipes = 0, modeset_pipes = 0; 8197 int i; 8198 8199 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 8200 enum pipe pipe = crtc->pipe; 8201 8202 if (!new_crtc_state->hw.active) 8203 continue; 8204 8205 /* ignore allocations for crtc's that have been turned off. */ 8206 if (!intel_crtc_needs_modeset(new_crtc_state)) { 8207 entries[pipe] = old_crtc_state->wm.skl.ddb; 8208 update_pipes |= BIT(pipe); 8209 } else { 8210 modeset_pipes |= BIT(pipe); 8211 } 8212 } 8213 8214 /* 8215 * Whenever the number of active pipes changes, we need to make sure we 8216 * update the pipes in the right order so that their ddb allocations 8217 * never overlap with each other between CRTC updates. Otherwise we'll 8218 * cause pipe underruns and other bad stuff. 8219 * 8220 * So first lets enable all pipes that do not need a fullmodeset as 8221 * those don't have any external dependency. 8222 */ 8223 while (update_pipes) { 8224 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8225 new_crtc_state, i) { 8226 enum pipe pipe = crtc->pipe; 8227 8228 if ((update_pipes & BIT(pipe)) == 0) 8229 continue; 8230 8231 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 8232 entries, I915_MAX_PIPES, pipe)) 8233 continue; 8234 8235 entries[pipe] = new_crtc_state->wm.skl.ddb; 8236 update_pipes &= ~BIT(pipe); 8237 8238 intel_update_crtc(state, crtc); 8239 8240 /* 8241 * If this is an already active pipe, it's DDB changed, 8242 * and this isn't the last pipe that needs updating 8243 * then we need to wait for a vblank to pass for the 8244 * new ddb allocation to take effect. 8245 */ 8246 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, 8247 &old_crtc_state->wm.skl.ddb) && 8248 (update_pipes | modeset_pipes)) 8249 intel_crtc_wait_for_next_vblank(crtc); 8250 } 8251 } 8252 8253 update_pipes = modeset_pipes; 8254 8255 /* 8256 * Enable all pipes that needs a modeset and do not depends on other 8257 * pipes 8258 */ 8259 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8260 enum pipe pipe = crtc->pipe; 8261 8262 if ((modeset_pipes & BIT(pipe)) == 0) 8263 continue; 8264 8265 if (intel_dp_mst_is_slave_trans(new_crtc_state) || 8266 is_trans_port_sync_master(new_crtc_state) || 8267 intel_crtc_is_bigjoiner_master(new_crtc_state)) 8268 continue; 8269 8270 modeset_pipes &= ~BIT(pipe); 8271 8272 intel_enable_crtc(state, crtc); 8273 } 8274 8275 /* 8276 * Then we enable all remaining pipes that depend on other 8277 * pipes: MST slaves and port sync masters, big joiner master 8278 */ 8279 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8280 enum pipe pipe = crtc->pipe; 8281 8282 if ((modeset_pipes & BIT(pipe)) == 0) 8283 continue; 8284 8285 modeset_pipes &= ~BIT(pipe); 8286 8287 intel_enable_crtc(state, crtc); 8288 } 8289 8290 /* 8291 * Finally we do the plane updates/etc. for all pipes that got enabled. 8292 */ 8293 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8294 enum pipe pipe = crtc->pipe; 8295 8296 if ((update_pipes & BIT(pipe)) == 0) 8297 continue; 8298 8299 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 8300 entries, I915_MAX_PIPES, pipe)); 8301 8302 entries[pipe] = new_crtc_state->wm.skl.ddb; 8303 update_pipes &= ~BIT(pipe); 8304 8305 intel_update_crtc(state, crtc); 8306 } 8307 8308 drm_WARN_ON(&dev_priv->drm, modeset_pipes); 8309 drm_WARN_ON(&dev_priv->drm, update_pipes); 8310 } 8311 8312 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) 8313 { 8314 struct intel_atomic_state *state, *next; 8315 struct llist_node *freed; 8316 8317 freed = llist_del_all(&dev_priv->atomic_helper.free_list); 8318 llist_for_each_entry_safe(state, next, freed, freed) 8319 drm_atomic_state_put(&state->base); 8320 } 8321 8322 static void intel_atomic_helper_free_state_worker(struct work_struct *work) 8323 { 8324 struct drm_i915_private *dev_priv = 8325 container_of(work, typeof(*dev_priv), atomic_helper.free_work); 8326 8327 intel_atomic_helper_free_state(dev_priv); 8328 } 8329 8330 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) 8331 { 8332 struct wait_queue_entry wait_fence, wait_reset; 8333 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); 8334 8335 init_wait_entry(&wait_fence, 0); 8336 init_wait_entry(&wait_reset, 0); 8337 for (;;) { 8338 prepare_to_wait(&intel_state->commit_ready.wait, 8339 &wait_fence, TASK_UNINTERRUPTIBLE); 8340 prepare_to_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 8341 I915_RESET_MODESET), 8342 &wait_reset, TASK_UNINTERRUPTIBLE); 8343 8344 8345 if (i915_sw_fence_done(&intel_state->commit_ready) || 8346 test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags)) 8347 break; 8348 8349 schedule(); 8350 } 8351 finish_wait(&intel_state->commit_ready.wait, &wait_fence); 8352 finish_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 8353 I915_RESET_MODESET), 8354 &wait_reset); 8355 } 8356 8357 static void intel_cleanup_dsbs(struct intel_atomic_state *state) 8358 { 8359 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 8360 struct intel_crtc *crtc; 8361 int i; 8362 8363 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8364 new_crtc_state, i) 8365 intel_dsb_cleanup(old_crtc_state); 8366 } 8367 8368 static void intel_atomic_cleanup_work(struct work_struct *work) 8369 { 8370 struct intel_atomic_state *state = 8371 container_of(work, struct intel_atomic_state, base.commit_work); 8372 struct drm_i915_private *i915 = to_i915(state->base.dev); 8373 8374 intel_cleanup_dsbs(state); 8375 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base); 8376 drm_atomic_helper_commit_cleanup_done(&state->base); 8377 drm_atomic_state_put(&state->base); 8378 8379 intel_atomic_helper_free_state(i915); 8380 } 8381 8382 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state) 8383 { 8384 struct drm_i915_private *i915 = to_i915(state->base.dev); 8385 struct intel_plane *plane; 8386 struct intel_plane_state *plane_state; 8387 int i; 8388 8389 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 8390 struct drm_framebuffer *fb = plane_state->hw.fb; 8391 int cc_plane; 8392 int ret; 8393 8394 if (!fb) 8395 continue; 8396 8397 cc_plane = intel_fb_rc_ccs_cc_plane(fb); 8398 if (cc_plane < 0) 8399 continue; 8400 8401 /* 8402 * The layout of the fast clear color value expected by HW 8403 * (the DRM ABI requiring this value to be located in fb at 8404 * offset 0 of cc plane, plane #2 previous generations or 8405 * plane #1 for flat ccs): 8406 * - 4 x 4 bytes per-channel value 8407 * (in surface type specific float/int format provided by the fb user) 8408 * - 8 bytes native color value used by the display 8409 * (converted/written by GPU during a fast clear operation using the 8410 * above per-channel values) 8411 * 8412 * The commit's FB prepare hook already ensured that FB obj is pinned and the 8413 * caller made sure that the object is synced wrt. the related color clear value 8414 * GPU write on it. 8415 */ 8416 ret = i915_gem_object_read_from_page(intel_fb_obj(fb), 8417 fb->offsets[cc_plane] + 16, 8418 &plane_state->ccval, 8419 sizeof(plane_state->ccval)); 8420 /* The above could only fail if the FB obj has an unexpected backing store type. */ 8421 drm_WARN_ON(&i915->drm, ret); 8422 } 8423 } 8424 8425 static void intel_atomic_commit_tail(struct intel_atomic_state *state) 8426 { 8427 struct drm_device *dev = state->base.dev; 8428 struct drm_i915_private *dev_priv = to_i915(dev); 8429 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 8430 struct intel_crtc *crtc; 8431 struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {}; 8432 intel_wakeref_t wakeref = 0; 8433 int i; 8434 8435 intel_atomic_commit_fence_wait(state); 8436 8437 drm_atomic_helper_wait_for_dependencies(&state->base); 8438 8439 if (state->modeset) 8440 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); 8441 8442 intel_atomic_prepare_plane_clear_colors(state); 8443 8444 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8445 new_crtc_state, i) { 8446 if (intel_crtc_needs_modeset(new_crtc_state) || 8447 new_crtc_state->update_pipe) { 8448 modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]); 8449 } 8450 } 8451 8452 intel_commit_modeset_disables(state); 8453 8454 /* FIXME: Eventually get rid of our crtc->config pointer */ 8455 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 8456 crtc->config = new_crtc_state; 8457 8458 if (state->modeset) { 8459 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base); 8460 8461 intel_set_cdclk_pre_plane_update(state); 8462 8463 intel_modeset_verify_disabled(dev_priv, state); 8464 } 8465 8466 intel_sagv_pre_plane_update(state); 8467 8468 /* Complete the events for pipes that have now been disabled */ 8469 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8470 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 8471 8472 /* Complete events for now disable pipes here. */ 8473 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) { 8474 spin_lock_irq(&dev->event_lock); 8475 drm_crtc_send_vblank_event(&crtc->base, 8476 new_crtc_state->uapi.event); 8477 spin_unlock_irq(&dev->event_lock); 8478 8479 new_crtc_state->uapi.event = NULL; 8480 } 8481 } 8482 8483 intel_encoders_update_prepare(state); 8484 8485 intel_dbuf_pre_plane_update(state); 8486 intel_mbus_dbox_update(state); 8487 8488 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8489 if (new_crtc_state->do_async_flip) 8490 intel_crtc_enable_flip_done(state, crtc); 8491 } 8492 8493 /* Now enable the clocks, plane, pipe, and connectors that we set up. */ 8494 dev_priv->display->commit_modeset_enables(state); 8495 8496 intel_encoders_update_complete(state); 8497 8498 if (state->modeset) 8499 intel_set_cdclk_post_plane_update(state); 8500 8501 intel_wait_for_vblank_workers(state); 8502 8503 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here 8504 * already, but still need the state for the delayed optimization. To 8505 * fix this: 8506 * - wrap the optimization/post_plane_update stuff into a per-crtc work. 8507 * - schedule that vblank worker _before_ calling hw_done 8508 * - at the start of commit_tail, cancel it _synchrously 8509 * - switch over to the vblank wait helper in the core after that since 8510 * we don't need out special handling any more. 8511 */ 8512 drm_atomic_helper_wait_for_flip_done(dev, &state->base); 8513 8514 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8515 if (new_crtc_state->do_async_flip) 8516 intel_crtc_disable_flip_done(state, crtc); 8517 } 8518 8519 /* 8520 * Now that the vblank has passed, we can go ahead and program the 8521 * optimal watermarks on platforms that need two-step watermark 8522 * programming. 8523 * 8524 * TODO: Move this (and other cleanup) to an async worker eventually. 8525 */ 8526 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8527 new_crtc_state, i) { 8528 /* 8529 * Gen2 reports pipe underruns whenever all planes are disabled. 8530 * So re-enable underrun reporting after some planes get enabled. 8531 * 8532 * We do this before .optimize_watermarks() so that we have a 8533 * chance of catching underruns with the intermediate watermarks 8534 * vs. the new plane configuration. 8535 */ 8536 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state)) 8537 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 8538 8539 intel_optimize_watermarks(state, crtc); 8540 } 8541 8542 intel_dbuf_post_plane_update(state); 8543 intel_psr_post_plane_update(state); 8544 8545 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 8546 intel_post_plane_update(state, crtc); 8547 8548 modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]); 8549 8550 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state); 8551 8552 /* 8553 * DSB cleanup is done in cleanup_work aligning with framebuffer 8554 * cleanup. So copy and reset the dsb structure to sync with 8555 * commit_done and later do dsb cleanup in cleanup_work. 8556 */ 8557 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb); 8558 } 8559 8560 /* Underruns don't always raise interrupts, so check manually */ 8561 intel_check_cpu_fifo_underruns(dev_priv); 8562 intel_check_pch_fifo_underruns(dev_priv); 8563 8564 if (state->modeset) 8565 intel_verify_planes(state); 8566 8567 intel_sagv_post_plane_update(state); 8568 8569 drm_atomic_helper_commit_hw_done(&state->base); 8570 8571 if (state->modeset) { 8572 /* As one of the primary mmio accessors, KMS has a high 8573 * likelihood of triggering bugs in unclaimed access. After we 8574 * finish modesetting, see if an error has been flagged, and if 8575 * so enable debugging for the next modeset - and hope we catch 8576 * the culprit. 8577 */ 8578 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); 8579 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref); 8580 } 8581 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 8582 8583 /* 8584 * Defer the cleanup of the old state to a separate worker to not 8585 * impede the current task (userspace for blocking modesets) that 8586 * are executed inline. For out-of-line asynchronous modesets/flips, 8587 * deferring to a new worker seems overkill, but we would place a 8588 * schedule point (cond_resched()) here anyway to keep latencies 8589 * down. 8590 */ 8591 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work); 8592 queue_work(system_highpri_wq, &state->base.commit_work); 8593 } 8594 8595 static void intel_atomic_commit_work(struct work_struct *work) 8596 { 8597 struct intel_atomic_state *state = 8598 container_of(work, struct intel_atomic_state, base.commit_work); 8599 8600 intel_atomic_commit_tail(state); 8601 } 8602 8603 static int 8604 intel_atomic_commit_ready(struct i915_sw_fence *fence, 8605 enum i915_sw_fence_notify notify) 8606 { 8607 struct intel_atomic_state *state = 8608 container_of(fence, struct intel_atomic_state, commit_ready); 8609 8610 switch (notify) { 8611 case FENCE_COMPLETE: 8612 /* we do blocking waits in the worker, nothing to do here */ 8613 break; 8614 case FENCE_FREE: 8615 { 8616 struct intel_atomic_helper *helper = 8617 &to_i915(state->base.dev)->atomic_helper; 8618 8619 if (llist_add(&state->freed, &helper->free_list)) 8620 schedule_work(&helper->free_work); 8621 break; 8622 } 8623 } 8624 8625 return NOTIFY_DONE; 8626 } 8627 8628 static void intel_atomic_track_fbs(struct intel_atomic_state *state) 8629 { 8630 struct intel_plane_state *old_plane_state, *new_plane_state; 8631 struct intel_plane *plane; 8632 int i; 8633 8634 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 8635 new_plane_state, i) 8636 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), 8637 to_intel_frontbuffer(new_plane_state->hw.fb), 8638 plane->frontbuffer_bit); 8639 } 8640 8641 static int intel_atomic_commit(struct drm_device *dev, 8642 struct drm_atomic_state *_state, 8643 bool nonblock) 8644 { 8645 struct intel_atomic_state *state = to_intel_atomic_state(_state); 8646 struct drm_i915_private *dev_priv = to_i915(dev); 8647 int ret = 0; 8648 8649 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 8650 8651 drm_atomic_state_get(&state->base); 8652 i915_sw_fence_init(&state->commit_ready, 8653 intel_atomic_commit_ready); 8654 8655 /* 8656 * The intel_legacy_cursor_update() fast path takes care 8657 * of avoiding the vblank waits for simple cursor 8658 * movement and flips. For cursor on/off and size changes, 8659 * we want to perform the vblank waits so that watermark 8660 * updates happen during the correct frames. Gen9+ have 8661 * double buffered watermarks and so shouldn't need this. 8662 * 8663 * Unset state->legacy_cursor_update before the call to 8664 * drm_atomic_helper_setup_commit() because otherwise 8665 * drm_atomic_helper_wait_for_flip_done() is a noop and 8666 * we get FIFO underruns because we didn't wait 8667 * for vblank. 8668 * 8669 * FIXME doing watermarks and fb cleanup from a vblank worker 8670 * (assuming we had any) would solve these problems. 8671 */ 8672 if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) { 8673 struct intel_crtc_state *new_crtc_state; 8674 struct intel_crtc *crtc; 8675 int i; 8676 8677 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 8678 if (new_crtc_state->wm.need_postvbl_update || 8679 new_crtc_state->update_wm_post) 8680 state->base.legacy_cursor_update = false; 8681 } 8682 8683 ret = intel_atomic_prepare_commit(state); 8684 if (ret) { 8685 drm_dbg_atomic(&dev_priv->drm, 8686 "Preparing state failed with %i\n", ret); 8687 i915_sw_fence_commit(&state->commit_ready); 8688 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 8689 return ret; 8690 } 8691 8692 ret = drm_atomic_helper_setup_commit(&state->base, nonblock); 8693 if (!ret) 8694 ret = drm_atomic_helper_swap_state(&state->base, true); 8695 if (!ret) 8696 intel_atomic_swap_global_state(state); 8697 8698 if (ret) { 8699 struct intel_crtc_state *new_crtc_state; 8700 struct intel_crtc *crtc; 8701 int i; 8702 8703 i915_sw_fence_commit(&state->commit_ready); 8704 8705 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 8706 intel_dsb_cleanup(new_crtc_state); 8707 8708 drm_atomic_helper_cleanup_planes(dev, &state->base); 8709 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 8710 return ret; 8711 } 8712 intel_shared_dpll_swap_state(state); 8713 intel_atomic_track_fbs(state); 8714 8715 drm_atomic_state_get(&state->base); 8716 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work); 8717 8718 i915_sw_fence_commit(&state->commit_ready); 8719 if (nonblock && state->modeset) { 8720 queue_work(dev_priv->modeset_wq, &state->base.commit_work); 8721 } else if (nonblock) { 8722 queue_work(dev_priv->flip_wq, &state->base.commit_work); 8723 } else { 8724 if (state->modeset) 8725 flush_workqueue(dev_priv->modeset_wq); 8726 intel_atomic_commit_tail(state); 8727 } 8728 8729 return 0; 8730 } 8731 8732 /** 8733 * intel_plane_destroy - destroy a plane 8734 * @plane: plane to destroy 8735 * 8736 * Common destruction function for all types of planes (primary, cursor, 8737 * sprite). 8738 */ 8739 void intel_plane_destroy(struct drm_plane *plane) 8740 { 8741 drm_plane_cleanup(plane); 8742 kfree(to_intel_plane(plane)); 8743 } 8744 8745 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv) 8746 { 8747 struct intel_plane *plane; 8748 8749 for_each_intel_plane(&dev_priv->drm, plane) { 8750 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, 8751 plane->pipe); 8752 8753 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base); 8754 } 8755 } 8756 8757 8758 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 8759 struct drm_file *file) 8760 { 8761 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; 8762 struct drm_crtc *drmmode_crtc; 8763 struct intel_crtc *crtc; 8764 8765 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id); 8766 if (!drmmode_crtc) 8767 return -ENOENT; 8768 8769 crtc = to_intel_crtc(drmmode_crtc); 8770 pipe_from_crtc_id->pipe = crtc->pipe; 8771 8772 return 0; 8773 } 8774 8775 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder) 8776 { 8777 struct drm_device *dev = encoder->base.dev; 8778 struct intel_encoder *source_encoder; 8779 u32 possible_clones = 0; 8780 8781 for_each_intel_encoder(dev, source_encoder) { 8782 if (encoders_cloneable(encoder, source_encoder)) 8783 possible_clones |= drm_encoder_mask(&source_encoder->base); 8784 } 8785 8786 return possible_clones; 8787 } 8788 8789 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder) 8790 { 8791 struct drm_device *dev = encoder->base.dev; 8792 struct intel_crtc *crtc; 8793 u32 possible_crtcs = 0; 8794 8795 for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask) 8796 possible_crtcs |= drm_crtc_mask(&crtc->base); 8797 8798 return possible_crtcs; 8799 } 8800 8801 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv) 8802 { 8803 if (!IS_MOBILE(dev_priv)) 8804 return false; 8805 8806 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0) 8807 return false; 8808 8809 if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE)) 8810 return false; 8811 8812 return true; 8813 } 8814 8815 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv) 8816 { 8817 if (DISPLAY_VER(dev_priv) >= 9) 8818 return false; 8819 8820 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) 8821 return false; 8822 8823 if (HAS_PCH_LPT_H(dev_priv) && 8824 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) 8825 return false; 8826 8827 /* DDI E can't be used if DDI A requires 4 lanes */ 8828 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 8829 return false; 8830 8831 if (!dev_priv->vbt.int_crt_support) 8832 return false; 8833 8834 return true; 8835 } 8836 8837 static void intel_setup_outputs(struct drm_i915_private *dev_priv) 8838 { 8839 struct intel_encoder *encoder; 8840 bool dpd_is_edp = false; 8841 8842 intel_pps_unlock_regs_wa(dev_priv); 8843 8844 if (!HAS_DISPLAY(dev_priv)) 8845 return; 8846 8847 if (IS_DG2(dev_priv)) { 8848 intel_ddi_init(dev_priv, PORT_A); 8849 intel_ddi_init(dev_priv, PORT_B); 8850 intel_ddi_init(dev_priv, PORT_C); 8851 intel_ddi_init(dev_priv, PORT_D_XELPD); 8852 intel_ddi_init(dev_priv, PORT_TC1); 8853 } else if (IS_ALDERLAKE_P(dev_priv)) { 8854 intel_ddi_init(dev_priv, PORT_A); 8855 intel_ddi_init(dev_priv, PORT_B); 8856 intel_ddi_init(dev_priv, PORT_TC1); 8857 intel_ddi_init(dev_priv, PORT_TC2); 8858 intel_ddi_init(dev_priv, PORT_TC3); 8859 intel_ddi_init(dev_priv, PORT_TC4); 8860 icl_dsi_init(dev_priv); 8861 } else if (IS_ALDERLAKE_S(dev_priv)) { 8862 intel_ddi_init(dev_priv, PORT_A); 8863 intel_ddi_init(dev_priv, PORT_TC1); 8864 intel_ddi_init(dev_priv, PORT_TC2); 8865 intel_ddi_init(dev_priv, PORT_TC3); 8866 intel_ddi_init(dev_priv, PORT_TC4); 8867 } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) { 8868 intel_ddi_init(dev_priv, PORT_A); 8869 intel_ddi_init(dev_priv, PORT_B); 8870 intel_ddi_init(dev_priv, PORT_TC1); 8871 intel_ddi_init(dev_priv, PORT_TC2); 8872 } else if (DISPLAY_VER(dev_priv) >= 12) { 8873 intel_ddi_init(dev_priv, PORT_A); 8874 intel_ddi_init(dev_priv, PORT_B); 8875 intel_ddi_init(dev_priv, PORT_TC1); 8876 intel_ddi_init(dev_priv, PORT_TC2); 8877 intel_ddi_init(dev_priv, PORT_TC3); 8878 intel_ddi_init(dev_priv, PORT_TC4); 8879 intel_ddi_init(dev_priv, PORT_TC5); 8880 intel_ddi_init(dev_priv, PORT_TC6); 8881 icl_dsi_init(dev_priv); 8882 } else if (IS_JSL_EHL(dev_priv)) { 8883 intel_ddi_init(dev_priv, PORT_A); 8884 intel_ddi_init(dev_priv, PORT_B); 8885 intel_ddi_init(dev_priv, PORT_C); 8886 intel_ddi_init(dev_priv, PORT_D); 8887 icl_dsi_init(dev_priv); 8888 } else if (DISPLAY_VER(dev_priv) == 11) { 8889 intel_ddi_init(dev_priv, PORT_A); 8890 intel_ddi_init(dev_priv, PORT_B); 8891 intel_ddi_init(dev_priv, PORT_C); 8892 intel_ddi_init(dev_priv, PORT_D); 8893 intel_ddi_init(dev_priv, PORT_E); 8894 intel_ddi_init(dev_priv, PORT_F); 8895 icl_dsi_init(dev_priv); 8896 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 8897 intel_ddi_init(dev_priv, PORT_A); 8898 intel_ddi_init(dev_priv, PORT_B); 8899 intel_ddi_init(dev_priv, PORT_C); 8900 vlv_dsi_init(dev_priv); 8901 } else if (DISPLAY_VER(dev_priv) >= 9) { 8902 intel_ddi_init(dev_priv, PORT_A); 8903 intel_ddi_init(dev_priv, PORT_B); 8904 intel_ddi_init(dev_priv, PORT_C); 8905 intel_ddi_init(dev_priv, PORT_D); 8906 intel_ddi_init(dev_priv, PORT_E); 8907 } else if (HAS_DDI(dev_priv)) { 8908 u32 found; 8909 8910 if (intel_ddi_crt_present(dev_priv)) 8911 intel_crt_init(dev_priv); 8912 8913 /* Haswell uses DDI functions to detect digital outputs. */ 8914 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 8915 if (found) 8916 intel_ddi_init(dev_priv, PORT_A); 8917 8918 found = intel_de_read(dev_priv, SFUSE_STRAP); 8919 if (found & SFUSE_STRAP_DDIB_DETECTED) 8920 intel_ddi_init(dev_priv, PORT_B); 8921 if (found & SFUSE_STRAP_DDIC_DETECTED) 8922 intel_ddi_init(dev_priv, PORT_C); 8923 if (found & SFUSE_STRAP_DDID_DETECTED) 8924 intel_ddi_init(dev_priv, PORT_D); 8925 if (found & SFUSE_STRAP_DDIF_DETECTED) 8926 intel_ddi_init(dev_priv, PORT_F); 8927 } else if (HAS_PCH_SPLIT(dev_priv)) { 8928 int found; 8929 8930 /* 8931 * intel_edp_init_connector() depends on this completing first, 8932 * to prevent the registration of both eDP and LVDS and the 8933 * incorrect sharing of the PPS. 8934 */ 8935 intel_lvds_init(dev_priv); 8936 intel_crt_init(dev_priv); 8937 8938 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D); 8939 8940 if (ilk_has_edp_a(dev_priv)) 8941 g4x_dp_init(dev_priv, DP_A, PORT_A); 8942 8943 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) { 8944 /* PCH SDVOB multiplex with HDMIB */ 8945 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); 8946 if (!found) 8947 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); 8948 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED)) 8949 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B); 8950 } 8951 8952 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED) 8953 g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); 8954 8955 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED) 8956 g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D); 8957 8958 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED) 8959 g4x_dp_init(dev_priv, PCH_DP_C, PORT_C); 8960 8961 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED) 8962 g4x_dp_init(dev_priv, PCH_DP_D, PORT_D); 8963 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 8964 bool has_edp, has_port; 8965 8966 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support) 8967 intel_crt_init(dev_priv); 8968 8969 /* 8970 * The DP_DETECTED bit is the latched state of the DDC 8971 * SDA pin at boot. However since eDP doesn't require DDC 8972 * (no way to plug in a DP->HDMI dongle) the DDC pins for 8973 * eDP ports may have been muxed to an alternate function. 8974 * Thus we can't rely on the DP_DETECTED bit alone to detect 8975 * eDP ports. Consult the VBT as well as DP_DETECTED to 8976 * detect eDP ports. 8977 * 8978 * Sadly the straps seem to be missing sometimes even for HDMI 8979 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap 8980 * and VBT for the presence of the port. Additionally we can't 8981 * trust the port type the VBT declares as we've seen at least 8982 * HDMI ports that the VBT claim are DP or eDP. 8983 */ 8984 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B); 8985 has_port = intel_bios_is_port_present(dev_priv, PORT_B); 8986 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port) 8987 has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B); 8988 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) 8989 g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); 8990 8991 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C); 8992 has_port = intel_bios_is_port_present(dev_priv, PORT_C); 8993 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port) 8994 has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C); 8995 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) 8996 g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); 8997 8998 if (IS_CHERRYVIEW(dev_priv)) { 8999 /* 9000 * eDP not supported on port D, 9001 * so no need to worry about it 9002 */ 9003 has_port = intel_bios_is_port_present(dev_priv, PORT_D); 9004 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port) 9005 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D); 9006 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port) 9007 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D); 9008 } 9009 9010 vlv_dsi_init(dev_priv); 9011 } else if (IS_PINEVIEW(dev_priv)) { 9012 intel_lvds_init(dev_priv); 9013 intel_crt_init(dev_priv); 9014 } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) { 9015 bool found = false; 9016 9017 if (IS_MOBILE(dev_priv)) 9018 intel_lvds_init(dev_priv); 9019 9020 intel_crt_init(dev_priv); 9021 9022 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 9023 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n"); 9024 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); 9025 if (!found && IS_G4X(dev_priv)) { 9026 drm_dbg_kms(&dev_priv->drm, 9027 "probing HDMI on SDVOB\n"); 9028 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); 9029 } 9030 9031 if (!found && IS_G4X(dev_priv)) 9032 g4x_dp_init(dev_priv, DP_B, PORT_B); 9033 } 9034 9035 /* Before G4X SDVOC doesn't have its own detect register */ 9036 9037 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 9038 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n"); 9039 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); 9040 } 9041 9042 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) { 9043 9044 if (IS_G4X(dev_priv)) { 9045 drm_dbg_kms(&dev_priv->drm, 9046 "probing HDMI on SDVOC\n"); 9047 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); 9048 } 9049 if (IS_G4X(dev_priv)) 9050 g4x_dp_init(dev_priv, DP_C, PORT_C); 9051 } 9052 9053 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED)) 9054 g4x_dp_init(dev_priv, DP_D, PORT_D); 9055 9056 if (SUPPORTS_TV(dev_priv)) 9057 intel_tv_init(dev_priv); 9058 } else if (DISPLAY_VER(dev_priv) == 2) { 9059 if (IS_I85X(dev_priv)) 9060 intel_lvds_init(dev_priv); 9061 9062 intel_crt_init(dev_priv); 9063 intel_dvo_init(dev_priv); 9064 } 9065 9066 for_each_intel_encoder(&dev_priv->drm, encoder) { 9067 encoder->base.possible_crtcs = 9068 intel_encoder_possible_crtcs(encoder); 9069 encoder->base.possible_clones = 9070 intel_encoder_possible_clones(encoder); 9071 } 9072 9073 intel_init_pch_refclk(dev_priv); 9074 9075 drm_helper_move_panel_connectors_to_head(&dev_priv->drm); 9076 } 9077 9078 static enum drm_mode_status 9079 intel_mode_valid(struct drm_device *dev, 9080 const struct drm_display_mode *mode) 9081 { 9082 struct drm_i915_private *dev_priv = to_i915(dev); 9083 int hdisplay_max, htotal_max; 9084 int vdisplay_max, vtotal_max; 9085 9086 /* 9087 * Can't reject DBLSCAN here because Xorg ddxen can add piles 9088 * of DBLSCAN modes to the output's mode list when they detect 9089 * the scaling mode property on the connector. And they don't 9090 * ask the kernel to validate those modes in any way until 9091 * modeset time at which point the client gets a protocol error. 9092 * So in order to not upset those clients we silently ignore the 9093 * DBLSCAN flag on such connectors. For other connectors we will 9094 * reject modes with the DBLSCAN flag in encoder->compute_config(). 9095 * And we always reject DBLSCAN modes in connector->mode_valid() 9096 * as we never want such modes on the connector's mode list. 9097 */ 9098 9099 if (mode->vscan > 1) 9100 return MODE_NO_VSCAN; 9101 9102 if (mode->flags & DRM_MODE_FLAG_HSKEW) 9103 return MODE_H_ILLEGAL; 9104 9105 if (mode->flags & (DRM_MODE_FLAG_CSYNC | 9106 DRM_MODE_FLAG_NCSYNC | 9107 DRM_MODE_FLAG_PCSYNC)) 9108 return MODE_HSYNC; 9109 9110 if (mode->flags & (DRM_MODE_FLAG_BCAST | 9111 DRM_MODE_FLAG_PIXMUX | 9112 DRM_MODE_FLAG_CLKDIV2)) 9113 return MODE_BAD; 9114 9115 /* Transcoder timing limits */ 9116 if (DISPLAY_VER(dev_priv) >= 11) { 9117 hdisplay_max = 16384; 9118 vdisplay_max = 8192; 9119 htotal_max = 16384; 9120 vtotal_max = 8192; 9121 } else if (DISPLAY_VER(dev_priv) >= 9 || 9122 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 9123 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ 9124 vdisplay_max = 4096; 9125 htotal_max = 8192; 9126 vtotal_max = 8192; 9127 } else if (DISPLAY_VER(dev_priv) >= 3) { 9128 hdisplay_max = 4096; 9129 vdisplay_max = 4096; 9130 htotal_max = 8192; 9131 vtotal_max = 8192; 9132 } else { 9133 hdisplay_max = 2048; 9134 vdisplay_max = 2048; 9135 htotal_max = 4096; 9136 vtotal_max = 4096; 9137 } 9138 9139 if (mode->hdisplay > hdisplay_max || 9140 mode->hsync_start > htotal_max || 9141 mode->hsync_end > htotal_max || 9142 mode->htotal > htotal_max) 9143 return MODE_H_ILLEGAL; 9144 9145 if (mode->vdisplay > vdisplay_max || 9146 mode->vsync_start > vtotal_max || 9147 mode->vsync_end > vtotal_max || 9148 mode->vtotal > vtotal_max) 9149 return MODE_V_ILLEGAL; 9150 9151 if (DISPLAY_VER(dev_priv) >= 5) { 9152 if (mode->hdisplay < 64 || 9153 mode->htotal - mode->hdisplay < 32) 9154 return MODE_H_ILLEGAL; 9155 9156 if (mode->vtotal - mode->vdisplay < 5) 9157 return MODE_V_ILLEGAL; 9158 } else { 9159 if (mode->htotal - mode->hdisplay < 32) 9160 return MODE_H_ILLEGAL; 9161 9162 if (mode->vtotal - mode->vdisplay < 3) 9163 return MODE_V_ILLEGAL; 9164 } 9165 9166 /* 9167 * Cantiga+ cannot handle modes with a hsync front porch of 0. 9168 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. 9169 */ 9170 if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) && 9171 mode->hsync_start == mode->hdisplay) 9172 return MODE_H_ILLEGAL; 9173 9174 return MODE_OK; 9175 } 9176 9177 enum drm_mode_status 9178 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 9179 const struct drm_display_mode *mode, 9180 bool bigjoiner) 9181 { 9182 int plane_width_max, plane_height_max; 9183 9184 /* 9185 * intel_mode_valid() should be 9186 * sufficient on older platforms. 9187 */ 9188 if (DISPLAY_VER(dev_priv) < 9) 9189 return MODE_OK; 9190 9191 /* 9192 * Most people will probably want a fullscreen 9193 * plane so let's not advertize modes that are 9194 * too big for that. 9195 */ 9196 if (DISPLAY_VER(dev_priv) >= 11) { 9197 plane_width_max = 5120 << bigjoiner; 9198 plane_height_max = 4320; 9199 } else { 9200 plane_width_max = 5120; 9201 plane_height_max = 4096; 9202 } 9203 9204 if (mode->hdisplay > plane_width_max) 9205 return MODE_H_ILLEGAL; 9206 9207 if (mode->vdisplay > plane_height_max) 9208 return MODE_V_ILLEGAL; 9209 9210 return MODE_OK; 9211 } 9212 9213 static const struct drm_mode_config_funcs intel_mode_funcs = { 9214 .fb_create = intel_user_framebuffer_create, 9215 .get_format_info = intel_fb_get_format_info, 9216 .output_poll_changed = intel_fbdev_output_poll_changed, 9217 .mode_valid = intel_mode_valid, 9218 .atomic_check = intel_atomic_check, 9219 .atomic_commit = intel_atomic_commit, 9220 .atomic_state_alloc = intel_atomic_state_alloc, 9221 .atomic_state_clear = intel_atomic_state_clear, 9222 .atomic_state_free = intel_atomic_state_free, 9223 }; 9224 9225 static const struct drm_i915_display_funcs skl_display_funcs = { 9226 .get_pipe_config = hsw_get_pipe_config, 9227 .crtc_enable = hsw_crtc_enable, 9228 .crtc_disable = hsw_crtc_disable, 9229 .commit_modeset_enables = skl_commit_modeset_enables, 9230 .get_initial_plane_config = skl_get_initial_plane_config, 9231 }; 9232 9233 static const struct drm_i915_display_funcs ddi_display_funcs = { 9234 .get_pipe_config = hsw_get_pipe_config, 9235 .crtc_enable = hsw_crtc_enable, 9236 .crtc_disable = hsw_crtc_disable, 9237 .commit_modeset_enables = intel_commit_modeset_enables, 9238 .get_initial_plane_config = i9xx_get_initial_plane_config, 9239 }; 9240 9241 static const struct drm_i915_display_funcs pch_split_display_funcs = { 9242 .get_pipe_config = ilk_get_pipe_config, 9243 .crtc_enable = ilk_crtc_enable, 9244 .crtc_disable = ilk_crtc_disable, 9245 .commit_modeset_enables = intel_commit_modeset_enables, 9246 .get_initial_plane_config = i9xx_get_initial_plane_config, 9247 }; 9248 9249 static const struct drm_i915_display_funcs vlv_display_funcs = { 9250 .get_pipe_config = i9xx_get_pipe_config, 9251 .crtc_enable = valleyview_crtc_enable, 9252 .crtc_disable = i9xx_crtc_disable, 9253 .commit_modeset_enables = intel_commit_modeset_enables, 9254 .get_initial_plane_config = i9xx_get_initial_plane_config, 9255 }; 9256 9257 static const struct drm_i915_display_funcs i9xx_display_funcs = { 9258 .get_pipe_config = i9xx_get_pipe_config, 9259 .crtc_enable = i9xx_crtc_enable, 9260 .crtc_disable = i9xx_crtc_disable, 9261 .commit_modeset_enables = intel_commit_modeset_enables, 9262 .get_initial_plane_config = i9xx_get_initial_plane_config, 9263 }; 9264 9265 /** 9266 * intel_init_display_hooks - initialize the display modesetting hooks 9267 * @dev_priv: device private 9268 */ 9269 void intel_init_display_hooks(struct drm_i915_private *dev_priv) 9270 { 9271 if (!HAS_DISPLAY(dev_priv)) 9272 return; 9273 9274 intel_init_cdclk_hooks(dev_priv); 9275 intel_audio_hooks_init(dev_priv); 9276 9277 intel_dpll_init_clock_hook(dev_priv); 9278 9279 if (DISPLAY_VER(dev_priv) >= 9) { 9280 dev_priv->display = &skl_display_funcs; 9281 } else if (HAS_DDI(dev_priv)) { 9282 dev_priv->display = &ddi_display_funcs; 9283 } else if (HAS_PCH_SPLIT(dev_priv)) { 9284 dev_priv->display = &pch_split_display_funcs; 9285 } else if (IS_CHERRYVIEW(dev_priv) || 9286 IS_VALLEYVIEW(dev_priv)) { 9287 dev_priv->display = &vlv_display_funcs; 9288 } else { 9289 dev_priv->display = &i9xx_display_funcs; 9290 } 9291 9292 intel_fdi_init_hook(dev_priv); 9293 } 9294 9295 void intel_modeset_init_hw(struct drm_i915_private *i915) 9296 { 9297 struct intel_cdclk_state *cdclk_state; 9298 9299 if (!HAS_DISPLAY(i915)) 9300 return; 9301 9302 cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state); 9303 9304 intel_update_cdclk(i915); 9305 intel_cdclk_dump_config(i915, &i915->cdclk.hw, "Current CDCLK"); 9306 cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw; 9307 } 9308 9309 static int sanitize_watermarks_add_affected(struct drm_atomic_state *state) 9310 { 9311 struct drm_plane *plane; 9312 struct intel_crtc *crtc; 9313 9314 for_each_intel_crtc(state->dev, crtc) { 9315 struct intel_crtc_state *crtc_state; 9316 9317 crtc_state = intel_atomic_get_crtc_state(state, crtc); 9318 if (IS_ERR(crtc_state)) 9319 return PTR_ERR(crtc_state); 9320 9321 if (crtc_state->hw.active) { 9322 /* 9323 * Preserve the inherited flag to avoid 9324 * taking the full modeset path. 9325 */ 9326 crtc_state->inherited = true; 9327 } 9328 } 9329 9330 drm_for_each_plane(plane, state->dev) { 9331 struct drm_plane_state *plane_state; 9332 9333 plane_state = drm_atomic_get_plane_state(state, plane); 9334 if (IS_ERR(plane_state)) 9335 return PTR_ERR(plane_state); 9336 } 9337 9338 return 0; 9339 } 9340 9341 /* 9342 * Calculate what we think the watermarks should be for the state we've read 9343 * out of the hardware and then immediately program those watermarks so that 9344 * we ensure the hardware settings match our internal state. 9345 * 9346 * We can calculate what we think WM's should be by creating a duplicate of the 9347 * current state (which was constructed during hardware readout) and running it 9348 * through the atomic check code to calculate new watermark values in the 9349 * state object. 9350 */ 9351 static void sanitize_watermarks(struct drm_i915_private *dev_priv) 9352 { 9353 struct drm_atomic_state *state; 9354 struct intel_atomic_state *intel_state; 9355 struct intel_crtc *crtc; 9356 struct intel_crtc_state *crtc_state; 9357 struct drm_modeset_acquire_ctx ctx; 9358 int ret; 9359 int i; 9360 9361 /* Only supported on platforms that use atomic watermark design */ 9362 if (!dev_priv->wm_disp->optimize_watermarks) 9363 return; 9364 9365 state = drm_atomic_state_alloc(&dev_priv->drm); 9366 if (drm_WARN_ON(&dev_priv->drm, !state)) 9367 return; 9368 9369 intel_state = to_intel_atomic_state(state); 9370 9371 drm_modeset_acquire_init(&ctx, 0); 9372 9373 retry: 9374 state->acquire_ctx = &ctx; 9375 9376 /* 9377 * Hardware readout is the only time we don't want to calculate 9378 * intermediate watermarks (since we don't trust the current 9379 * watermarks). 9380 */ 9381 if (!HAS_GMCH(dev_priv)) 9382 intel_state->skip_intermediate_wm = true; 9383 9384 ret = sanitize_watermarks_add_affected(state); 9385 if (ret) 9386 goto fail; 9387 9388 ret = intel_atomic_check(&dev_priv->drm, state); 9389 if (ret) 9390 goto fail; 9391 9392 /* Write calculated watermark values back */ 9393 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) { 9394 crtc_state->wm.need_postvbl_update = true; 9395 intel_optimize_watermarks(intel_state, crtc); 9396 9397 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm; 9398 } 9399 9400 fail: 9401 if (ret == -EDEADLK) { 9402 drm_atomic_state_clear(state); 9403 drm_modeset_backoff(&ctx); 9404 goto retry; 9405 } 9406 9407 /* 9408 * If we fail here, it means that the hardware appears to be 9409 * programmed in a way that shouldn't be possible, given our 9410 * understanding of watermark requirements. This might mean a 9411 * mistake in the hardware readout code or a mistake in the 9412 * watermark calculations for a given platform. Raise a WARN 9413 * so that this is noticeable. 9414 * 9415 * If this actually happens, we'll have to just leave the 9416 * BIOS-programmed watermarks untouched and hope for the best. 9417 */ 9418 drm_WARN(&dev_priv->drm, ret, 9419 "Could not determine valid watermarks for inherited state\n"); 9420 9421 drm_atomic_state_put(state); 9422 9423 drm_modeset_drop_locks(&ctx); 9424 drm_modeset_acquire_fini(&ctx); 9425 } 9426 9427 static int intel_initial_commit(struct drm_device *dev) 9428 { 9429 struct drm_atomic_state *state = NULL; 9430 struct drm_modeset_acquire_ctx ctx; 9431 struct intel_crtc *crtc; 9432 int ret = 0; 9433 9434 state = drm_atomic_state_alloc(dev); 9435 if (!state) 9436 return -ENOMEM; 9437 9438 drm_modeset_acquire_init(&ctx, 0); 9439 9440 retry: 9441 state->acquire_ctx = &ctx; 9442 9443 for_each_intel_crtc(dev, crtc) { 9444 struct intel_crtc_state *crtc_state = 9445 intel_atomic_get_crtc_state(state, crtc); 9446 9447 if (IS_ERR(crtc_state)) { 9448 ret = PTR_ERR(crtc_state); 9449 goto out; 9450 } 9451 9452 if (crtc_state->hw.active) { 9453 struct intel_encoder *encoder; 9454 9455 /* 9456 * We've not yet detected sink capabilities 9457 * (audio,infoframes,etc.) and thus we don't want to 9458 * force a full state recomputation yet. We want that to 9459 * happen only for the first real commit from userspace. 9460 * So preserve the inherited flag for the time being. 9461 */ 9462 crtc_state->inherited = true; 9463 9464 ret = drm_atomic_add_affected_planes(state, &crtc->base); 9465 if (ret) 9466 goto out; 9467 9468 /* 9469 * FIXME hack to force a LUT update to avoid the 9470 * plane update forcing the pipe gamma on without 9471 * having a proper LUT loaded. Remove once we 9472 * have readout for pipe gamma enable. 9473 */ 9474 crtc_state->uapi.color_mgmt_changed = true; 9475 9476 for_each_intel_encoder_mask(dev, encoder, 9477 crtc_state->uapi.encoder_mask) { 9478 if (encoder->initial_fastset_check && 9479 !encoder->initial_fastset_check(encoder, crtc_state)) { 9480 ret = drm_atomic_add_affected_connectors(state, 9481 &crtc->base); 9482 if (ret) 9483 goto out; 9484 } 9485 } 9486 } 9487 } 9488 9489 ret = drm_atomic_commit(state); 9490 9491 out: 9492 if (ret == -EDEADLK) { 9493 drm_atomic_state_clear(state); 9494 drm_modeset_backoff(&ctx); 9495 goto retry; 9496 } 9497 9498 drm_atomic_state_put(state); 9499 9500 drm_modeset_drop_locks(&ctx); 9501 drm_modeset_acquire_fini(&ctx); 9502 9503 return ret; 9504 } 9505 9506 static void intel_mode_config_init(struct drm_i915_private *i915) 9507 { 9508 struct drm_mode_config *mode_config = &i915->drm.mode_config; 9509 9510 drm_mode_config_init(&i915->drm); 9511 INIT_LIST_HEAD(&i915->global_obj_list); 9512 9513 mode_config->min_width = 0; 9514 mode_config->min_height = 0; 9515 9516 mode_config->preferred_depth = 24; 9517 mode_config->prefer_shadow = 1; 9518 9519 mode_config->funcs = &intel_mode_funcs; 9520 9521 mode_config->async_page_flip = HAS_ASYNC_FLIPS(i915); 9522 9523 /* 9524 * Maximum framebuffer dimensions, chosen to match 9525 * the maximum render engine surface size on gen4+. 9526 */ 9527 if (DISPLAY_VER(i915) >= 7) { 9528 mode_config->max_width = 16384; 9529 mode_config->max_height = 16384; 9530 } else if (DISPLAY_VER(i915) >= 4) { 9531 mode_config->max_width = 8192; 9532 mode_config->max_height = 8192; 9533 } else if (DISPLAY_VER(i915) == 3) { 9534 mode_config->max_width = 4096; 9535 mode_config->max_height = 4096; 9536 } else { 9537 mode_config->max_width = 2048; 9538 mode_config->max_height = 2048; 9539 } 9540 9541 if (IS_I845G(i915) || IS_I865G(i915)) { 9542 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512; 9543 mode_config->cursor_height = 1023; 9544 } else if (IS_I830(i915) || IS_I85X(i915) || 9545 IS_I915G(i915) || IS_I915GM(i915)) { 9546 mode_config->cursor_width = 64; 9547 mode_config->cursor_height = 64; 9548 } else { 9549 mode_config->cursor_width = 256; 9550 mode_config->cursor_height = 256; 9551 } 9552 } 9553 9554 static void intel_mode_config_cleanup(struct drm_i915_private *i915) 9555 { 9556 intel_atomic_global_obj_cleanup(i915); 9557 drm_mode_config_cleanup(&i915->drm); 9558 } 9559 9560 /* part #1: call before irq install */ 9561 int intel_modeset_init_noirq(struct drm_i915_private *i915) 9562 { 9563 int ret; 9564 9565 if (i915_inject_probe_failure(i915)) 9566 return -ENODEV; 9567 9568 if (HAS_DISPLAY(i915)) { 9569 ret = drm_vblank_init(&i915->drm, 9570 INTEL_NUM_PIPES(i915)); 9571 if (ret) 9572 return ret; 9573 } 9574 9575 intel_bios_init(i915); 9576 9577 ret = intel_vga_register(i915); 9578 if (ret) 9579 goto cleanup_bios; 9580 9581 /* FIXME: completely on the wrong abstraction layer */ 9582 intel_power_domains_init_hw(i915, false); 9583 9584 if (!HAS_DISPLAY(i915)) 9585 return 0; 9586 9587 intel_dmc_ucode_init(i915); 9588 9589 i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0); 9590 i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI | 9591 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE); 9592 9593 i915->window2_delay = 0; /* No DSB so no window2 delay */ 9594 9595 intel_mode_config_init(i915); 9596 9597 ret = intel_cdclk_init(i915); 9598 if (ret) 9599 goto cleanup_vga_client_pw_domain_dmc; 9600 9601 ret = intel_dbuf_init(i915); 9602 if (ret) 9603 goto cleanup_vga_client_pw_domain_dmc; 9604 9605 ret = intel_bw_init(i915); 9606 if (ret) 9607 goto cleanup_vga_client_pw_domain_dmc; 9608 9609 init_llist_head(&i915->atomic_helper.free_list); 9610 INIT_WORK(&i915->atomic_helper.free_work, 9611 intel_atomic_helper_free_state_worker); 9612 9613 intel_init_quirks(i915); 9614 9615 intel_fbc_init(i915); 9616 9617 return 0; 9618 9619 cleanup_vga_client_pw_domain_dmc: 9620 intel_dmc_ucode_fini(i915); 9621 intel_power_domains_driver_remove(i915); 9622 intel_vga_unregister(i915); 9623 cleanup_bios: 9624 intel_bios_driver_remove(i915); 9625 9626 return ret; 9627 } 9628 9629 /* part #2: call after irq install, but before gem init */ 9630 int intel_modeset_init_nogem(struct drm_i915_private *i915) 9631 { 9632 struct drm_device *dev = &i915->drm; 9633 enum pipe pipe; 9634 struct intel_crtc *crtc; 9635 int ret; 9636 9637 if (!HAS_DISPLAY(i915)) 9638 return 0; 9639 9640 intel_init_pm(i915); 9641 9642 intel_panel_sanitize_ssc(i915); 9643 9644 intel_pps_setup(i915); 9645 9646 intel_gmbus_setup(i915); 9647 9648 drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n", 9649 INTEL_NUM_PIPES(i915), 9650 INTEL_NUM_PIPES(i915) > 1 ? "s" : ""); 9651 9652 for_each_pipe(i915, pipe) { 9653 ret = intel_crtc_init(i915, pipe); 9654 if (ret) { 9655 intel_mode_config_cleanup(i915); 9656 return ret; 9657 } 9658 } 9659 9660 intel_plane_possible_crtcs_init(i915); 9661 intel_shared_dpll_init(i915); 9662 intel_fdi_pll_freq_update(i915); 9663 9664 intel_update_czclk(i915); 9665 intel_modeset_init_hw(i915); 9666 intel_dpll_update_ref_clks(i915); 9667 9668 intel_hdcp_component_init(i915); 9669 9670 if (i915->max_cdclk_freq == 0) 9671 intel_update_max_cdclk(i915); 9672 9673 /* 9674 * If the platform has HTI, we need to find out whether it has reserved 9675 * any display resources before we create our display outputs. 9676 */ 9677 if (INTEL_INFO(i915)->display.has_hti) 9678 i915->hti_state = intel_de_read(i915, HDPORT_STATE); 9679 9680 /* Just disable it once at startup */ 9681 intel_vga_disable(i915); 9682 intel_setup_outputs(i915); 9683 9684 drm_modeset_lock_all(dev); 9685 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx); 9686 intel_acpi_assign_connector_fwnodes(i915); 9687 drm_modeset_unlock_all(dev); 9688 9689 for_each_intel_crtc(dev, crtc) { 9690 if (!to_intel_crtc_state(crtc->base.state)->uapi.active) 9691 continue; 9692 intel_crtc_initial_plane_config(crtc); 9693 } 9694 9695 /* 9696 * Make sure hardware watermarks really match the state we read out. 9697 * Note that we need to do this after reconstructing the BIOS fb's 9698 * since the watermark calculation done here will use pstate->fb. 9699 */ 9700 if (!HAS_GMCH(i915)) 9701 sanitize_watermarks(i915); 9702 9703 return 0; 9704 } 9705 9706 /* part #3: call after gem init */ 9707 int intel_modeset_init(struct drm_i915_private *i915) 9708 { 9709 int ret; 9710 9711 if (!HAS_DISPLAY(i915)) 9712 return 0; 9713 9714 /* 9715 * Force all active planes to recompute their states. So that on 9716 * mode_setcrtc after probe, all the intel_plane_state variables 9717 * are already calculated and there is no assert_plane warnings 9718 * during bootup. 9719 */ 9720 ret = intel_initial_commit(&i915->drm); 9721 if (ret) 9722 drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret); 9723 9724 intel_overlay_setup(i915); 9725 9726 ret = intel_fbdev_init(&i915->drm); 9727 if (ret) 9728 return ret; 9729 9730 /* Only enable hotplug handling once the fbdev is fully set up. */ 9731 intel_hpd_init(i915); 9732 intel_hpd_poll_disable(i915); 9733 9734 intel_init_ipc(i915); 9735 9736 return 0; 9737 } 9738 9739 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 9740 { 9741 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 9742 /* 640x480@60Hz, ~25175 kHz */ 9743 struct dpll clock = { 9744 .m1 = 18, 9745 .m2 = 7, 9746 .p1 = 13, 9747 .p2 = 4, 9748 .n = 2, 9749 }; 9750 u32 dpll, fp; 9751 int i; 9752 9753 drm_WARN_ON(&dev_priv->drm, 9754 i9xx_calc_dpll_params(48000, &clock) != 25154); 9755 9756 drm_dbg_kms(&dev_priv->drm, 9757 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n", 9758 pipe_name(pipe), clock.vco, clock.dot); 9759 9760 fp = i9xx_dpll_compute_fp(&clock); 9761 dpll = DPLL_DVO_2X_MODE | 9762 DPLL_VGA_MODE_DIS | 9763 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | 9764 PLL_P2_DIVIDE_BY_4 | 9765 PLL_REF_INPUT_DREFCLK | 9766 DPLL_VCO_ENABLE; 9767 9768 intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16)); 9769 intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16)); 9770 intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16)); 9771 intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16)); 9772 intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16)); 9773 intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16)); 9774 intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1)); 9775 9776 intel_de_write(dev_priv, FP0(pipe), fp); 9777 intel_de_write(dev_priv, FP1(pipe), fp); 9778 9779 /* 9780 * Apparently we need to have VGA mode enabled prior to changing 9781 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 9782 * dividers, even though the register value does change. 9783 */ 9784 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); 9785 intel_de_write(dev_priv, DPLL(pipe), dpll); 9786 9787 /* Wait for the clocks to stabilize. */ 9788 intel_de_posting_read(dev_priv, DPLL(pipe)); 9789 udelay(150); 9790 9791 /* The pixel multiplier can only be updated once the 9792 * DPLL is enabled and the clocks are stable. 9793 * 9794 * So write it again. 9795 */ 9796 intel_de_write(dev_priv, DPLL(pipe), dpll); 9797 9798 /* We do this three times for luck */ 9799 for (i = 0; i < 3 ; i++) { 9800 intel_de_write(dev_priv, DPLL(pipe), dpll); 9801 intel_de_posting_read(dev_priv, DPLL(pipe)); 9802 udelay(150); /* wait for warmup */ 9803 } 9804 9805 intel_de_write(dev_priv, PIPECONF(pipe), PIPECONF_ENABLE); 9806 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 9807 9808 intel_wait_for_pipe_scanline_moving(crtc); 9809 } 9810 9811 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 9812 { 9813 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 9814 9815 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n", 9816 pipe_name(pipe)); 9817 9818 drm_WARN_ON(&dev_priv->drm, 9819 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE); 9820 drm_WARN_ON(&dev_priv->drm, 9821 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE); 9822 drm_WARN_ON(&dev_priv->drm, 9823 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE); 9824 drm_WARN_ON(&dev_priv->drm, 9825 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK); 9826 drm_WARN_ON(&dev_priv->drm, 9827 intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK); 9828 9829 intel_de_write(dev_priv, PIPECONF(pipe), 0); 9830 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 9831 9832 intel_wait_for_pipe_scanline_stopped(crtc); 9833 9834 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); 9835 intel_de_posting_read(dev_priv, DPLL(pipe)); 9836 } 9837 9838 static void 9839 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv) 9840 { 9841 struct intel_crtc *crtc; 9842 9843 if (DISPLAY_VER(dev_priv) >= 4) 9844 return; 9845 9846 for_each_intel_crtc(&dev_priv->drm, crtc) { 9847 struct intel_plane *plane = 9848 to_intel_plane(crtc->base.primary); 9849 struct intel_crtc *plane_crtc; 9850 enum pipe pipe; 9851 9852 if (!plane->get_hw_state(plane, &pipe)) 9853 continue; 9854 9855 if (pipe == crtc->pipe) 9856 continue; 9857 9858 drm_dbg_kms(&dev_priv->drm, 9859 "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n", 9860 plane->base.base.id, plane->base.name); 9861 9862 plane_crtc = intel_crtc_for_pipe(dev_priv, pipe); 9863 intel_plane_disable_noatomic(plane_crtc, plane); 9864 } 9865 } 9866 9867 static bool intel_crtc_has_encoders(struct intel_crtc *crtc) 9868 { 9869 struct drm_device *dev = crtc->base.dev; 9870 struct intel_encoder *encoder; 9871 9872 for_each_encoder_on_crtc(dev, &crtc->base, encoder) 9873 return true; 9874 9875 return false; 9876 } 9877 9878 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) 9879 { 9880 struct drm_device *dev = encoder->base.dev; 9881 struct intel_connector *connector; 9882 9883 for_each_connector_on_encoder(dev, &encoder->base, connector) 9884 return connector; 9885 9886 return NULL; 9887 } 9888 9889 static void intel_sanitize_crtc(struct intel_crtc *crtc, 9890 struct drm_modeset_acquire_ctx *ctx) 9891 { 9892 struct drm_device *dev = crtc->base.dev; 9893 struct drm_i915_private *dev_priv = to_i915(dev); 9894 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); 9895 9896 if (crtc_state->hw.active) { 9897 struct intel_plane *plane; 9898 9899 /* Disable everything but the primary plane */ 9900 for_each_intel_plane_on_crtc(dev, crtc, plane) { 9901 const struct intel_plane_state *plane_state = 9902 to_intel_plane_state(plane->base.state); 9903 9904 if (plane_state->uapi.visible && 9905 plane->base.type != DRM_PLANE_TYPE_PRIMARY) 9906 intel_plane_disable_noatomic(crtc, plane); 9907 } 9908 9909 /* Disable any background color/etc. set by the BIOS */ 9910 intel_color_commit_noarm(crtc_state); 9911 intel_color_commit_arm(crtc_state); 9912 } 9913 9914 /* Adjust the state of the output pipe according to whether we 9915 * have active connectors/encoders. */ 9916 if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) && 9917 !intel_crtc_is_bigjoiner_slave(crtc_state)) 9918 intel_crtc_disable_noatomic(crtc, ctx); 9919 9920 if (crtc_state->hw.active || HAS_GMCH(dev_priv)) { 9921 /* 9922 * We start out with underrun reporting disabled to avoid races. 9923 * For correct bookkeeping mark this on active crtcs. 9924 * 9925 * Also on gmch platforms we dont have any hardware bits to 9926 * disable the underrun reporting. Which means we need to start 9927 * out with underrun reporting disabled also on inactive pipes, 9928 * since otherwise we'll complain about the garbage we read when 9929 * e.g. coming up after runtime pm. 9930 * 9931 * No protection against concurrent access is required - at 9932 * worst a fifo underrun happens which also sets this to false. 9933 */ 9934 crtc->cpu_fifo_underrun_disabled = true; 9935 /* 9936 * We track the PCH trancoder underrun reporting state 9937 * within the crtc. With crtc for pipe A housing the underrun 9938 * reporting state for PCH transcoder A, crtc for pipe B housing 9939 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, 9940 * and marking underrun reporting as disabled for the non-existing 9941 * PCH transcoders B and C would prevent enabling the south 9942 * error interrupt (see cpt_can_enable_serr_int()). 9943 */ 9944 if (intel_has_pch_trancoder(dev_priv, crtc->pipe)) 9945 crtc->pch_fifo_underrun_disabled = true; 9946 } 9947 } 9948 9949 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state) 9950 { 9951 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 9952 9953 /* 9954 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram 9955 * the hardware when a high res displays plugged in. DPLL P 9956 * divider is zero, and the pipe timings are bonkers. We'll 9957 * try to disable everything in that case. 9958 * 9959 * FIXME would be nice to be able to sanitize this state 9960 * without several WARNs, but for now let's take the easy 9961 * road. 9962 */ 9963 return IS_SANDYBRIDGE(dev_priv) && 9964 crtc_state->hw.active && 9965 crtc_state->shared_dpll && 9966 crtc_state->port_clock == 0; 9967 } 9968 9969 static void intel_sanitize_encoder(struct intel_encoder *encoder) 9970 { 9971 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 9972 struct intel_connector *connector; 9973 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 9974 struct intel_crtc_state *crtc_state = crtc ? 9975 to_intel_crtc_state(crtc->base.state) : NULL; 9976 9977 /* We need to check both for a crtc link (meaning that the 9978 * encoder is active and trying to read from a pipe) and the 9979 * pipe itself being active. */ 9980 bool has_active_crtc = crtc_state && 9981 crtc_state->hw.active; 9982 9983 if (crtc_state && has_bogus_dpll_config(crtc_state)) { 9984 drm_dbg_kms(&dev_priv->drm, 9985 "BIOS has misprogrammed the hardware. Disabling pipe %c\n", 9986 pipe_name(crtc->pipe)); 9987 has_active_crtc = false; 9988 } 9989 9990 connector = intel_encoder_find_connector(encoder); 9991 if (connector && !has_active_crtc) { 9992 drm_dbg_kms(&dev_priv->drm, 9993 "[ENCODER:%d:%s] has active connectors but no active pipe!\n", 9994 encoder->base.base.id, 9995 encoder->base.name); 9996 9997 /* Connector is active, but has no active pipe. This is 9998 * fallout from our resume register restoring. Disable 9999 * the encoder manually again. */ 10000 if (crtc_state) { 10001 struct drm_encoder *best_encoder; 10002 10003 drm_dbg_kms(&dev_priv->drm, 10004 "[ENCODER:%d:%s] manually disabled\n", 10005 encoder->base.base.id, 10006 encoder->base.name); 10007 10008 /* avoid oopsing in case the hooks consult best_encoder */ 10009 best_encoder = connector->base.state->best_encoder; 10010 connector->base.state->best_encoder = &encoder->base; 10011 10012 /* FIXME NULL atomic state passed! */ 10013 if (encoder->disable) 10014 encoder->disable(NULL, encoder, crtc_state, 10015 connector->base.state); 10016 if (encoder->post_disable) 10017 encoder->post_disable(NULL, encoder, crtc_state, 10018 connector->base.state); 10019 10020 connector->base.state->best_encoder = best_encoder; 10021 } 10022 encoder->base.crtc = NULL; 10023 10024 /* Inconsistent output/port/pipe state happens presumably due to 10025 * a bug in one of the get_hw_state functions. Or someplace else 10026 * in our code, like the register restore mess on resume. Clamp 10027 * things to off as a safer default. */ 10028 10029 connector->base.dpms = DRM_MODE_DPMS_OFF; 10030 connector->base.encoder = NULL; 10031 } 10032 10033 /* notify opregion of the sanitized encoder state */ 10034 intel_opregion_notify_encoder(encoder, connector && has_active_crtc); 10035 10036 if (HAS_DDI(dev_priv)) 10037 intel_ddi_sanitize_encoder_pll_mapping(encoder); 10038 } 10039 10040 /* FIXME read out full plane state for all planes */ 10041 static void readout_plane_state(struct drm_i915_private *dev_priv) 10042 { 10043 struct intel_plane *plane; 10044 struct intel_crtc *crtc; 10045 10046 for_each_intel_plane(&dev_priv->drm, plane) { 10047 struct intel_plane_state *plane_state = 10048 to_intel_plane_state(plane->base.state); 10049 struct intel_crtc_state *crtc_state; 10050 enum pipe pipe = PIPE_A; 10051 bool visible; 10052 10053 visible = plane->get_hw_state(plane, &pipe); 10054 10055 crtc = intel_crtc_for_pipe(dev_priv, pipe); 10056 crtc_state = to_intel_crtc_state(crtc->base.state); 10057 10058 intel_set_plane_visible(crtc_state, plane_state, visible); 10059 10060 drm_dbg_kms(&dev_priv->drm, 10061 "[PLANE:%d:%s] hw state readout: %s, pipe %c\n", 10062 plane->base.base.id, plane->base.name, 10063 str_enabled_disabled(visible), pipe_name(pipe)); 10064 } 10065 10066 for_each_intel_crtc(&dev_priv->drm, crtc) { 10067 struct intel_crtc_state *crtc_state = 10068 to_intel_crtc_state(crtc->base.state); 10069 10070 fixup_plane_bitmasks(crtc_state); 10071 } 10072 } 10073 10074 static void intel_modeset_readout_hw_state(struct drm_device *dev) 10075 { 10076 struct drm_i915_private *dev_priv = to_i915(dev); 10077 struct intel_cdclk_state *cdclk_state = 10078 to_intel_cdclk_state(dev_priv->cdclk.obj.state); 10079 struct intel_dbuf_state *dbuf_state = 10080 to_intel_dbuf_state(dev_priv->dbuf.obj.state); 10081 enum pipe pipe; 10082 struct intel_crtc *crtc; 10083 struct intel_encoder *encoder; 10084 struct intel_connector *connector; 10085 struct drm_connector_list_iter conn_iter; 10086 u8 active_pipes = 0; 10087 10088 for_each_intel_crtc(dev, crtc) { 10089 struct intel_crtc_state *crtc_state = 10090 to_intel_crtc_state(crtc->base.state); 10091 10092 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi); 10093 intel_crtc_free_hw_state(crtc_state); 10094 intel_crtc_state_reset(crtc_state, crtc); 10095 10096 intel_crtc_get_pipe_config(crtc_state); 10097 10098 crtc_state->hw.enable = crtc_state->hw.active; 10099 10100 crtc->base.enabled = crtc_state->hw.enable; 10101 crtc->active = crtc_state->hw.active; 10102 10103 if (crtc_state->hw.active) 10104 active_pipes |= BIT(crtc->pipe); 10105 10106 drm_dbg_kms(&dev_priv->drm, 10107 "[CRTC:%d:%s] hw state readout: %s\n", 10108 crtc->base.base.id, crtc->base.name, 10109 str_enabled_disabled(crtc_state->hw.active)); 10110 } 10111 10112 cdclk_state->active_pipes = dbuf_state->active_pipes = active_pipes; 10113 10114 readout_plane_state(dev_priv); 10115 10116 for_each_intel_encoder(dev, encoder) { 10117 struct intel_crtc_state *crtc_state = NULL; 10118 10119 pipe = 0; 10120 10121 if (encoder->get_hw_state(encoder, &pipe)) { 10122 crtc = intel_crtc_for_pipe(dev_priv, pipe); 10123 crtc_state = to_intel_crtc_state(crtc->base.state); 10124 10125 encoder->base.crtc = &crtc->base; 10126 intel_encoder_get_config(encoder, crtc_state); 10127 10128 /* read out to slave crtc as well for bigjoiner */ 10129 if (crtc_state->bigjoiner_pipes) { 10130 struct intel_crtc *slave_crtc; 10131 10132 /* encoder should read be linked to bigjoiner master */ 10133 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 10134 10135 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc, 10136 intel_crtc_bigjoiner_slave_pipes(crtc_state)) { 10137 struct intel_crtc_state *slave_crtc_state; 10138 10139 slave_crtc_state = to_intel_crtc_state(slave_crtc->base.state); 10140 intel_encoder_get_config(encoder, slave_crtc_state); 10141 } 10142 } 10143 } else { 10144 encoder->base.crtc = NULL; 10145 } 10146 10147 if (encoder->sync_state) 10148 encoder->sync_state(encoder, crtc_state); 10149 10150 drm_dbg_kms(&dev_priv->drm, 10151 "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", 10152 encoder->base.base.id, encoder->base.name, 10153 str_enabled_disabled(encoder->base.crtc), 10154 pipe_name(pipe)); 10155 } 10156 10157 intel_dpll_readout_hw_state(dev_priv); 10158 10159 drm_connector_list_iter_begin(dev, &conn_iter); 10160 for_each_intel_connector_iter(connector, &conn_iter) { 10161 if (connector->get_hw_state(connector)) { 10162 struct intel_crtc_state *crtc_state; 10163 struct intel_crtc *crtc; 10164 10165 connector->base.dpms = DRM_MODE_DPMS_ON; 10166 10167 encoder = intel_attached_encoder(connector); 10168 connector->base.encoder = &encoder->base; 10169 10170 crtc = to_intel_crtc(encoder->base.crtc); 10171 crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL; 10172 10173 if (crtc_state && crtc_state->hw.active) { 10174 /* 10175 * This has to be done during hardware readout 10176 * because anything calling .crtc_disable may 10177 * rely on the connector_mask being accurate. 10178 */ 10179 crtc_state->uapi.connector_mask |= 10180 drm_connector_mask(&connector->base); 10181 crtc_state->uapi.encoder_mask |= 10182 drm_encoder_mask(&encoder->base); 10183 } 10184 } else { 10185 connector->base.dpms = DRM_MODE_DPMS_OFF; 10186 connector->base.encoder = NULL; 10187 } 10188 drm_dbg_kms(&dev_priv->drm, 10189 "[CONNECTOR:%d:%s] hw state readout: %s\n", 10190 connector->base.base.id, connector->base.name, 10191 str_enabled_disabled(connector->base.encoder)); 10192 } 10193 drm_connector_list_iter_end(&conn_iter); 10194 10195 for_each_intel_crtc(dev, crtc) { 10196 struct intel_bw_state *bw_state = 10197 to_intel_bw_state(dev_priv->bw_obj.state); 10198 struct intel_crtc_state *crtc_state = 10199 to_intel_crtc_state(crtc->base.state); 10200 struct intel_plane *plane; 10201 int min_cdclk = 0; 10202 10203 if (crtc_state->hw.active) { 10204 /* 10205 * The initial mode needs to be set in order to keep 10206 * the atomic core happy. It wants a valid mode if the 10207 * crtc's enabled, so we do the above call. 10208 * 10209 * But we don't set all the derived state fully, hence 10210 * set a flag to indicate that a full recalculation is 10211 * needed on the next commit. 10212 */ 10213 crtc_state->inherited = true; 10214 10215 intel_crtc_update_active_timings(crtc_state); 10216 10217 intel_crtc_copy_hw_to_uapi_state(crtc_state); 10218 } 10219 10220 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 10221 const struct intel_plane_state *plane_state = 10222 to_intel_plane_state(plane->base.state); 10223 10224 /* 10225 * FIXME don't have the fb yet, so can't 10226 * use intel_plane_data_rate() :( 10227 */ 10228 if (plane_state->uapi.visible) 10229 crtc_state->data_rate[plane->id] = 10230 4 * crtc_state->pixel_rate; 10231 /* 10232 * FIXME don't have the fb yet, so can't 10233 * use plane->min_cdclk() :( 10234 */ 10235 if (plane_state->uapi.visible && plane->min_cdclk) { 10236 if (crtc_state->double_wide || DISPLAY_VER(dev_priv) >= 10) 10237 crtc_state->min_cdclk[plane->id] = 10238 DIV_ROUND_UP(crtc_state->pixel_rate, 2); 10239 else 10240 crtc_state->min_cdclk[plane->id] = 10241 crtc_state->pixel_rate; 10242 } 10243 drm_dbg_kms(&dev_priv->drm, 10244 "[PLANE:%d:%s] min_cdclk %d kHz\n", 10245 plane->base.base.id, plane->base.name, 10246 crtc_state->min_cdclk[plane->id]); 10247 } 10248 10249 if (crtc_state->hw.active) { 10250 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); 10251 if (drm_WARN_ON(dev, min_cdclk < 0)) 10252 min_cdclk = 0; 10253 } 10254 10255 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; 10256 cdclk_state->min_voltage_level[crtc->pipe] = 10257 crtc_state->min_voltage_level; 10258 10259 intel_bw_crtc_update(bw_state, crtc_state); 10260 10261 intel_pipe_config_sanity_check(dev_priv, crtc_state); 10262 } 10263 } 10264 10265 static void 10266 get_encoder_power_domains(struct drm_i915_private *dev_priv) 10267 { 10268 struct intel_encoder *encoder; 10269 10270 for_each_intel_encoder(&dev_priv->drm, encoder) { 10271 struct intel_crtc_state *crtc_state; 10272 10273 if (!encoder->get_power_domains) 10274 continue; 10275 10276 /* 10277 * MST-primary and inactive encoders don't have a crtc state 10278 * and neither of these require any power domain references. 10279 */ 10280 if (!encoder->base.crtc) 10281 continue; 10282 10283 crtc_state = to_intel_crtc_state(encoder->base.crtc->state); 10284 encoder->get_power_domains(encoder, crtc_state); 10285 } 10286 } 10287 10288 static void intel_early_display_was(struct drm_i915_private *dev_priv) 10289 { 10290 /* 10291 * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl 10292 * Also known as Wa_14010480278. 10293 */ 10294 if (IS_DISPLAY_VER(dev_priv, 10, 12)) 10295 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0, 10296 intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS); 10297 10298 if (IS_HASWELL(dev_priv)) { 10299 /* 10300 * WaRsPkgCStateDisplayPMReq:hsw 10301 * System hang if this isn't done before disabling all planes! 10302 */ 10303 intel_de_write(dev_priv, CHICKEN_PAR1_1, 10304 intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); 10305 } 10306 10307 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) { 10308 /* Display WA #1142:kbl,cfl,cml */ 10309 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 10310 KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22); 10311 intel_de_rmw(dev_priv, CHICKEN_MISC_2, 10312 KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14, 10313 KBL_ARB_FILL_SPARE_14); 10314 } 10315 } 10316 10317 10318 /* Scan out the current hw modeset state, 10319 * and sanitizes it to the current state 10320 */ 10321 static void 10322 intel_modeset_setup_hw_state(struct drm_device *dev, 10323 struct drm_modeset_acquire_ctx *ctx) 10324 { 10325 struct drm_i915_private *dev_priv = to_i915(dev); 10326 struct intel_encoder *encoder; 10327 struct intel_crtc *crtc; 10328 intel_wakeref_t wakeref; 10329 10330 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 10331 10332 intel_early_display_was(dev_priv); 10333 intel_modeset_readout_hw_state(dev); 10334 10335 /* HW state is read out, now we need to sanitize this mess. */ 10336 get_encoder_power_domains(dev_priv); 10337 10338 intel_pch_sanitize(dev_priv); 10339 10340 /* 10341 * intel_sanitize_plane_mapping() may need to do vblank 10342 * waits, so we need vblank interrupts restored beforehand. 10343 */ 10344 for_each_intel_crtc(&dev_priv->drm, crtc) { 10345 struct intel_crtc_state *crtc_state = 10346 to_intel_crtc_state(crtc->base.state); 10347 10348 drm_crtc_vblank_reset(&crtc->base); 10349 10350 if (crtc_state->hw.active) 10351 intel_crtc_vblank_on(crtc_state); 10352 } 10353 10354 intel_fbc_sanitize(dev_priv); 10355 10356 intel_sanitize_plane_mapping(dev_priv); 10357 10358 for_each_intel_encoder(dev, encoder) 10359 intel_sanitize_encoder(encoder); 10360 10361 for_each_intel_crtc(&dev_priv->drm, crtc) { 10362 struct intel_crtc_state *crtc_state = 10363 to_intel_crtc_state(crtc->base.state); 10364 10365 intel_sanitize_crtc(crtc, ctx); 10366 intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]"); 10367 } 10368 10369 intel_modeset_update_connector_atomic_state(dev); 10370 10371 intel_dpll_sanitize_state(dev_priv); 10372 10373 if (IS_G4X(dev_priv)) { 10374 g4x_wm_get_hw_state(dev_priv); 10375 g4x_wm_sanitize(dev_priv); 10376 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 10377 vlv_wm_get_hw_state(dev_priv); 10378 vlv_wm_sanitize(dev_priv); 10379 } else if (DISPLAY_VER(dev_priv) >= 9) { 10380 skl_wm_get_hw_state(dev_priv); 10381 skl_wm_sanitize(dev_priv); 10382 } else if (HAS_PCH_SPLIT(dev_priv)) { 10383 ilk_wm_get_hw_state(dev_priv); 10384 } 10385 10386 for_each_intel_crtc(dev, crtc) { 10387 struct intel_crtc_state *crtc_state = 10388 to_intel_crtc_state(crtc->base.state); 10389 struct intel_power_domain_mask put_domains; 10390 10391 modeset_get_crtc_power_domains(crtc_state, &put_domains); 10392 if (drm_WARN_ON(dev, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM))) 10393 modeset_put_crtc_power_domains(crtc, &put_domains); 10394 } 10395 10396 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref); 10397 10398 intel_power_domains_sanitize_state(dev_priv); 10399 } 10400 10401 void intel_display_resume(struct drm_device *dev) 10402 { 10403 struct drm_i915_private *dev_priv = to_i915(dev); 10404 struct drm_atomic_state *state = dev_priv->modeset_restore_state; 10405 struct drm_modeset_acquire_ctx ctx; 10406 int ret; 10407 10408 if (!HAS_DISPLAY(dev_priv)) 10409 return; 10410 10411 dev_priv->modeset_restore_state = NULL; 10412 if (state) 10413 state->acquire_ctx = &ctx; 10414 10415 drm_modeset_acquire_init(&ctx, 0); 10416 10417 while (1) { 10418 ret = drm_modeset_lock_all_ctx(dev, &ctx); 10419 if (ret != -EDEADLK) 10420 break; 10421 10422 drm_modeset_backoff(&ctx); 10423 } 10424 10425 if (!ret) 10426 ret = __intel_display_resume(dev, state, &ctx); 10427 10428 intel_enable_ipc(dev_priv); 10429 drm_modeset_drop_locks(&ctx); 10430 drm_modeset_acquire_fini(&ctx); 10431 10432 if (ret) 10433 drm_err(&dev_priv->drm, 10434 "Restoring old state failed with %i\n", ret); 10435 if (state) 10436 drm_atomic_state_put(state); 10437 } 10438 10439 static void intel_hpd_poll_fini(struct drm_i915_private *i915) 10440 { 10441 struct intel_connector *connector; 10442 struct drm_connector_list_iter conn_iter; 10443 10444 /* Kill all the work that may have been queued by hpd. */ 10445 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 10446 for_each_intel_connector_iter(connector, &conn_iter) { 10447 if (connector->modeset_retry_work.func) 10448 cancel_work_sync(&connector->modeset_retry_work); 10449 if (connector->hdcp.shim) { 10450 cancel_delayed_work_sync(&connector->hdcp.check_work); 10451 cancel_work_sync(&connector->hdcp.prop_work); 10452 } 10453 } 10454 drm_connector_list_iter_end(&conn_iter); 10455 } 10456 10457 /* part #1: call before irq uninstall */ 10458 void intel_modeset_driver_remove(struct drm_i915_private *i915) 10459 { 10460 if (!HAS_DISPLAY(i915)) 10461 return; 10462 10463 flush_workqueue(i915->flip_wq); 10464 flush_workqueue(i915->modeset_wq); 10465 10466 flush_work(&i915->atomic_helper.free_work); 10467 drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list)); 10468 } 10469 10470 /* part #2: call after irq uninstall */ 10471 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915) 10472 { 10473 if (!HAS_DISPLAY(i915)) 10474 return; 10475 10476 /* 10477 * Due to the hpd irq storm handling the hotplug work can re-arm the 10478 * poll handlers. Hence disable polling after hpd handling is shut down. 10479 */ 10480 intel_hpd_poll_fini(i915); 10481 10482 /* 10483 * MST topology needs to be suspended so we don't have any calls to 10484 * fbdev after it's finalized. MST will be destroyed later as part of 10485 * drm_mode_config_cleanup() 10486 */ 10487 intel_dp_mst_suspend(i915); 10488 10489 /* poll work can call into fbdev, hence clean that up afterwards */ 10490 intel_fbdev_fini(i915); 10491 10492 intel_unregister_dsm_handler(); 10493 10494 /* flush any delayed tasks or pending work */ 10495 flush_scheduled_work(); 10496 10497 intel_hdcp_component_fini(i915); 10498 10499 intel_mode_config_cleanup(i915); 10500 10501 intel_overlay_cleanup(i915); 10502 10503 intel_gmbus_teardown(i915); 10504 10505 destroy_workqueue(i915->flip_wq); 10506 destroy_workqueue(i915->modeset_wq); 10507 10508 intel_fbc_cleanup(i915); 10509 } 10510 10511 /* part #3: call after gem init */ 10512 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915) 10513 { 10514 intel_dmc_ucode_fini(i915); 10515 10516 intel_power_domains_driver_remove(i915); 10517 10518 intel_vga_unregister(i915); 10519 10520 intel_bios_driver_remove(i915); 10521 } 10522 10523 bool intel_modeset_probe_defer(struct pci_dev *pdev) 10524 { 10525 struct drm_privacy_screen *privacy_screen; 10526 10527 /* 10528 * apple-gmux is needed on dual GPU MacBook Pro 10529 * to probe the panel if we're the inactive GPU. 10530 */ 10531 if (vga_switcheroo_client_probe_defer(pdev)) 10532 return true; 10533 10534 /* If the LCD panel has a privacy-screen, wait for it */ 10535 privacy_screen = drm_privacy_screen_get(&pdev->dev, NULL); 10536 if (IS_ERR(privacy_screen) && PTR_ERR(privacy_screen) == -EPROBE_DEFER) 10537 return true; 10538 10539 drm_privacy_screen_put(privacy_screen); 10540 10541 return false; 10542 } 10543 10544 void intel_display_driver_register(struct drm_i915_private *i915) 10545 { 10546 if (!HAS_DISPLAY(i915)) 10547 return; 10548 10549 intel_display_debugfs_register(i915); 10550 10551 /* Must be done after probing outputs */ 10552 intel_opregion_register(i915); 10553 acpi_video_register(); 10554 10555 intel_audio_init(i915); 10556 10557 /* 10558 * Some ports require correctly set-up hpd registers for 10559 * detection to work properly (leading to ghost connected 10560 * connector status), e.g. VGA on gm45. Hence we can only set 10561 * up the initial fbdev config after hpd irqs are fully 10562 * enabled. We do it last so that the async config cannot run 10563 * before the connectors are registered. 10564 */ 10565 intel_fbdev_initial_config_async(&i915->drm); 10566 10567 /* 10568 * We need to coordinate the hotplugs with the asynchronous 10569 * fbdev configuration, for which we use the 10570 * fbdev->async_cookie. 10571 */ 10572 drm_kms_helper_poll_init(&i915->drm); 10573 } 10574 10575 void intel_display_driver_unregister(struct drm_i915_private *i915) 10576 { 10577 if (!HAS_DISPLAY(i915)) 10578 return; 10579 10580 intel_fbdev_unregister(i915); 10581 intel_audio_deinit(i915); 10582 10583 /* 10584 * After flushing the fbdev (incl. a late async config which 10585 * will have delayed queuing of a hotplug event), then flush 10586 * the hotplug events. 10587 */ 10588 drm_kms_helper_poll_fini(&i915->drm); 10589 drm_atomic_helper_shutdown(&i915->drm); 10590 10591 acpi_video_unregister(); 10592 intel_opregion_unregister(i915); 10593 } 10594 10595 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915) 10596 { 10597 return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915); 10598 } 10599