1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <acpi/video.h> 28 #include <linux/i2c.h> 29 #include <linux/input.h> 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/dma-resv.h> 33 #include <linux/slab.h> 34 #include <linux/string_helpers.h> 35 #include <linux/vga_switcheroo.h> 36 37 #include <drm/display/drm_dp_helper.h> 38 #include <drm/drm_atomic.h> 39 #include <drm/drm_atomic_helper.h> 40 #include <drm/drm_atomic_uapi.h> 41 #include <drm/drm_damage_helper.h> 42 #include <drm/drm_edid.h> 43 #include <drm/drm_fourcc.h> 44 #include <drm/drm_plane_helper.h> 45 #include <drm/drm_privacy_screen_consumer.h> 46 #include <drm/drm_probe_helper.h> 47 #include <drm/drm_rect.h> 48 49 #include "display/intel_audio.h" 50 #include "display/intel_crt.h" 51 #include "display/intel_ddi.h" 52 #include "display/intel_display_debugfs.h" 53 #include "display/intel_display_power.h" 54 #include "display/intel_dp.h" 55 #include "display/intel_dp_mst.h" 56 #include "display/intel_dpll.h" 57 #include "display/intel_dpll_mgr.h" 58 #include "display/intel_drrs.h" 59 #include "display/intel_dsi.h" 60 #include "display/intel_dvo.h" 61 #include "display/intel_fb.h" 62 #include "display/intel_gmbus.h" 63 #include "display/intel_hdmi.h" 64 #include "display/intel_lvds.h" 65 #include "display/intel_sdvo.h" 66 #include "display/intel_snps_phy.h" 67 #include "display/intel_tv.h" 68 #include "display/intel_vdsc.h" 69 #include "display/intel_vrr.h" 70 71 #include "gem/i915_gem_lmem.h" 72 #include "gem/i915_gem_object.h" 73 74 #include "gt/gen8_ppgtt.h" 75 76 #include "g4x_dp.h" 77 #include "g4x_hdmi.h" 78 #include "hsw_ips.h" 79 #include "i915_drv.h" 80 #include "i915_utils.h" 81 #include "icl_dsi.h" 82 #include "intel_acpi.h" 83 #include "intel_atomic.h" 84 #include "intel_atomic_plane.h" 85 #include "intel_bw.h" 86 #include "intel_cdclk.h" 87 #include "intel_color.h" 88 #include "intel_crtc.h" 89 #include "intel_de.h" 90 #include "intel_display_types.h" 91 #include "intel_dmc.h" 92 #include "intel_dp_link_training.h" 93 #include "intel_dpt.h" 94 #include "intel_fbc.h" 95 #include "intel_fbdev.h" 96 #include "intel_fdi.h" 97 #include "intel_fifo_underrun.h" 98 #include "intel_frontbuffer.h" 99 #include "intel_hdcp.h" 100 #include "intel_hotplug.h" 101 #include "intel_overlay.h" 102 #include "intel_panel.h" 103 #include "intel_pch_display.h" 104 #include "intel_pch_refclk.h" 105 #include "intel_pcode.h" 106 #include "intel_pipe_crc.h" 107 #include "intel_plane_initial.h" 108 #include "intel_pm.h" 109 #include "intel_pps.h" 110 #include "intel_psr.h" 111 #include "intel_quirks.h" 112 #include "intel_sprite.h" 113 #include "intel_tc.h" 114 #include "intel_vga.h" 115 #include "i9xx_plane.h" 116 #include "skl_scaler.h" 117 #include "skl_universal_plane.h" 118 #include "vlv_dsi.h" 119 #include "vlv_dsi_pll.h" 120 #include "vlv_dsi_regs.h" 121 #include "vlv_sideband.h" 122 123 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state); 124 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state); 125 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state); 126 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state); 127 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state); 128 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state); 129 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state); 130 static void intel_modeset_setup_hw_state(struct drm_device *dev, 131 struct drm_modeset_acquire_ctx *ctx); 132 133 /** 134 * intel_update_watermarks - update FIFO watermark values based on current modes 135 * @dev_priv: i915 device 136 * 137 * Calculate watermark values for the various WM regs based on current mode 138 * and plane configuration. 139 * 140 * There are several cases to deal with here: 141 * - normal (i.e. non-self-refresh) 142 * - self-refresh (SR) mode 143 * - lines are large relative to FIFO size (buffer can hold up to 2) 144 * - lines are small relative to FIFO size (buffer can hold more than 2 145 * lines), so need to account for TLB latency 146 * 147 * The normal calculation is: 148 * watermark = dotclock * bytes per pixel * latency 149 * where latency is platform & configuration dependent (we assume pessimal 150 * values here). 151 * 152 * The SR calculation is: 153 * watermark = (trunc(latency/line time)+1) * surface width * 154 * bytes per pixel 155 * where 156 * line time = htotal / dotclock 157 * surface width = hdisplay for normal plane and 64 for cursor 158 * and latency is assumed to be high, as above. 159 * 160 * The final value programmed to the register should always be rounded up, 161 * and include an extra 2 entries to account for clock crossings. 162 * 163 * We don't use the sprite, so we can ignore that. And on Crestline we have 164 * to set the non-SR watermarks to 8. 165 */ 166 static void intel_update_watermarks(struct drm_i915_private *dev_priv) 167 { 168 if (dev_priv->wm_disp->update_wm) 169 dev_priv->wm_disp->update_wm(dev_priv); 170 } 171 172 static int intel_compute_pipe_wm(struct intel_atomic_state *state, 173 struct intel_crtc *crtc) 174 { 175 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 176 if (dev_priv->wm_disp->compute_pipe_wm) 177 return dev_priv->wm_disp->compute_pipe_wm(state, crtc); 178 return 0; 179 } 180 181 static int intel_compute_intermediate_wm(struct intel_atomic_state *state, 182 struct intel_crtc *crtc) 183 { 184 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 185 if (!dev_priv->wm_disp->compute_intermediate_wm) 186 return 0; 187 if (drm_WARN_ON(&dev_priv->drm, 188 !dev_priv->wm_disp->compute_pipe_wm)) 189 return 0; 190 return dev_priv->wm_disp->compute_intermediate_wm(state, crtc); 191 } 192 193 static bool intel_initial_watermarks(struct intel_atomic_state *state, 194 struct intel_crtc *crtc) 195 { 196 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 197 if (dev_priv->wm_disp->initial_watermarks) { 198 dev_priv->wm_disp->initial_watermarks(state, crtc); 199 return true; 200 } 201 return false; 202 } 203 204 static void intel_atomic_update_watermarks(struct intel_atomic_state *state, 205 struct intel_crtc *crtc) 206 { 207 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 208 if (dev_priv->wm_disp->atomic_update_watermarks) 209 dev_priv->wm_disp->atomic_update_watermarks(state, crtc); 210 } 211 212 static void intel_optimize_watermarks(struct intel_atomic_state *state, 213 struct intel_crtc *crtc) 214 { 215 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 216 if (dev_priv->wm_disp->optimize_watermarks) 217 dev_priv->wm_disp->optimize_watermarks(state, crtc); 218 } 219 220 static int intel_compute_global_watermarks(struct intel_atomic_state *state) 221 { 222 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 223 if (dev_priv->wm_disp->compute_global_watermarks) 224 return dev_priv->wm_disp->compute_global_watermarks(state); 225 return 0; 226 } 227 228 /* returns HPLL frequency in kHz */ 229 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) 230 { 231 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; 232 233 /* Obtain SKU information */ 234 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & 235 CCK_FUSE_HPLL_FREQ_MASK; 236 237 return vco_freq[hpll_freq] * 1000; 238 } 239 240 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 241 const char *name, u32 reg, int ref_freq) 242 { 243 u32 val; 244 int divider; 245 246 val = vlv_cck_read(dev_priv, reg); 247 divider = val & CCK_FREQUENCY_VALUES; 248 249 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != 250 (divider << CCK_FREQUENCY_STATUS_SHIFT), 251 "%s change in progress\n", name); 252 253 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); 254 } 255 256 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 257 const char *name, u32 reg) 258 { 259 int hpll; 260 261 vlv_cck_get(dev_priv); 262 263 if (dev_priv->hpll_freq == 0) 264 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); 265 266 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); 267 268 vlv_cck_put(dev_priv); 269 270 return hpll; 271 } 272 273 static void intel_update_czclk(struct drm_i915_private *dev_priv) 274 { 275 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) 276 return; 277 278 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", 279 CCK_CZ_CLOCK_CONTROL); 280 281 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", 282 dev_priv->czclk_freq); 283 } 284 285 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state) 286 { 287 return (crtc_state->active_planes & 288 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0; 289 } 290 291 /* WA Display #0827: Gen9:all */ 292 static void 293 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) 294 { 295 if (enable) 296 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 297 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS); 298 else 299 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 300 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS)); 301 } 302 303 /* Wa_2006604312:icl,ehl */ 304 static void 305 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 306 bool enable) 307 { 308 if (enable) 309 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 310 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS); 311 else 312 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 313 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS); 314 } 315 316 /* Wa_1604331009:icl,jsl,ehl */ 317 static void 318 icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 319 bool enable) 320 { 321 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), CURSOR_GATING_DIS, 322 enable ? CURSOR_GATING_DIS : 0); 323 } 324 325 static bool 326 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state) 327 { 328 return crtc_state->master_transcoder != INVALID_TRANSCODER; 329 } 330 331 static bool 332 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state) 333 { 334 return crtc_state->sync_mode_slaves_mask != 0; 335 } 336 337 bool 338 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state) 339 { 340 return is_trans_port_sync_master(crtc_state) || 341 is_trans_port_sync_slave(crtc_state); 342 } 343 344 static enum pipe bigjoiner_master_pipe(const struct intel_crtc_state *crtc_state) 345 { 346 return ffs(crtc_state->bigjoiner_pipes) - 1; 347 } 348 349 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state) 350 { 351 if (crtc_state->bigjoiner_pipes) 352 return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state)); 353 else 354 return 0; 355 } 356 357 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state) 358 { 359 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 360 361 return crtc_state->bigjoiner_pipes && 362 crtc->pipe != bigjoiner_master_pipe(crtc_state); 363 } 364 365 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state) 366 { 367 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 368 369 return crtc_state->bigjoiner_pipes && 370 crtc->pipe == bigjoiner_master_pipe(crtc_state); 371 } 372 373 static int intel_bigjoiner_num_pipes(const struct intel_crtc_state *crtc_state) 374 { 375 return hweight8(crtc_state->bigjoiner_pipes); 376 } 377 378 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state) 379 { 380 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 381 382 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 383 return intel_crtc_for_pipe(i915, bigjoiner_master_pipe(crtc_state)); 384 else 385 return to_intel_crtc(crtc_state->uapi.crtc); 386 } 387 388 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv, 389 enum pipe pipe) 390 { 391 i915_reg_t reg = PIPEDSL(pipe); 392 u32 line1, line2; 393 394 line1 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK; 395 msleep(5); 396 line2 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK; 397 398 return line1 != line2; 399 } 400 401 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state) 402 { 403 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 404 enum pipe pipe = crtc->pipe; 405 406 /* Wait for the display line to settle/start moving */ 407 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100)) 408 drm_err(&dev_priv->drm, 409 "pipe %c scanline %s wait timed out\n", 410 pipe_name(pipe), str_on_off(state)); 411 } 412 413 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc) 414 { 415 wait_for_pipe_scanline_moving(crtc, false); 416 } 417 418 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc) 419 { 420 wait_for_pipe_scanline_moving(crtc, true); 421 } 422 423 static void 424 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) 425 { 426 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 427 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 428 429 if (DISPLAY_VER(dev_priv) >= 4) { 430 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 431 432 /* Wait for the Pipe State to go off */ 433 if (intel_de_wait_for_clear(dev_priv, PIPECONF(cpu_transcoder), 434 PIPECONF_STATE_ENABLE, 100)) 435 drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n"); 436 } else { 437 intel_wait_for_pipe_scanline_stopped(crtc); 438 } 439 } 440 441 void assert_transcoder(struct drm_i915_private *dev_priv, 442 enum transcoder cpu_transcoder, bool state) 443 { 444 bool cur_state; 445 enum intel_display_power_domain power_domain; 446 intel_wakeref_t wakeref; 447 448 /* we keep both pipes enabled on 830 */ 449 if (IS_I830(dev_priv)) 450 state = true; 451 452 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 453 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 454 if (wakeref) { 455 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); 456 cur_state = !!(val & PIPECONF_ENABLE); 457 458 intel_display_power_put(dev_priv, power_domain, wakeref); 459 } else { 460 cur_state = false; 461 } 462 463 I915_STATE_WARN(cur_state != state, 464 "transcoder %s assertion failure (expected %s, current %s)\n", 465 transcoder_name(cpu_transcoder), 466 str_on_off(state), str_on_off(cur_state)); 467 } 468 469 static void assert_plane(struct intel_plane *plane, bool state) 470 { 471 enum pipe pipe; 472 bool cur_state; 473 474 cur_state = plane->get_hw_state(plane, &pipe); 475 476 I915_STATE_WARN(cur_state != state, 477 "%s assertion failure (expected %s, current %s)\n", 478 plane->base.name, str_on_off(state), 479 str_on_off(cur_state)); 480 } 481 482 #define assert_plane_enabled(p) assert_plane(p, true) 483 #define assert_plane_disabled(p) assert_plane(p, false) 484 485 static void assert_planes_disabled(struct intel_crtc *crtc) 486 { 487 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 488 struct intel_plane *plane; 489 490 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) 491 assert_plane_disabled(plane); 492 } 493 494 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 495 struct intel_digital_port *dig_port, 496 unsigned int expected_mask) 497 { 498 u32 port_mask; 499 i915_reg_t dpll_reg; 500 501 switch (dig_port->base.port) { 502 case PORT_B: 503 port_mask = DPLL_PORTB_READY_MASK; 504 dpll_reg = DPLL(0); 505 break; 506 case PORT_C: 507 port_mask = DPLL_PORTC_READY_MASK; 508 dpll_reg = DPLL(0); 509 expected_mask <<= 4; 510 break; 511 case PORT_D: 512 port_mask = DPLL_PORTD_READY_MASK; 513 dpll_reg = DPIO_PHY_STATUS; 514 break; 515 default: 516 BUG(); 517 } 518 519 if (intel_de_wait_for_register(dev_priv, dpll_reg, 520 port_mask, expected_mask, 1000)) 521 drm_WARN(&dev_priv->drm, 1, 522 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", 523 dig_port->base.base.base.id, dig_port->base.base.name, 524 intel_de_read(dev_priv, dpll_reg) & port_mask, 525 expected_mask); 526 } 527 528 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) 529 { 530 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 531 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 532 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 533 enum pipe pipe = crtc->pipe; 534 i915_reg_t reg; 535 u32 val; 536 537 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe)); 538 539 assert_planes_disabled(crtc); 540 541 /* 542 * A pipe without a PLL won't actually be able to drive bits from 543 * a plane. On ILK+ the pipe PLLs are integrated, so we don't 544 * need the check. 545 */ 546 if (HAS_GMCH(dev_priv)) { 547 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI)) 548 assert_dsi_pll_enabled(dev_priv); 549 else 550 assert_pll_enabled(dev_priv, pipe); 551 } else { 552 if (new_crtc_state->has_pch_encoder) { 553 /* if driving the PCH, we need FDI enabled */ 554 assert_fdi_rx_pll_enabled(dev_priv, 555 intel_crtc_pch_transcoder(crtc)); 556 assert_fdi_tx_pll_enabled(dev_priv, 557 (enum pipe) cpu_transcoder); 558 } 559 /* FIXME: assert CPU port conditions for SNB+ */ 560 } 561 562 /* Wa_22012358565:adl-p */ 563 if (DISPLAY_VER(dev_priv) == 13) 564 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe), 565 0, PIPE_ARB_USE_PROG_SLOTS); 566 567 reg = PIPECONF(cpu_transcoder); 568 val = intel_de_read(dev_priv, reg); 569 if (val & PIPECONF_ENABLE) { 570 /* we keep both pipes enabled on 830 */ 571 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv)); 572 return; 573 } 574 575 intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE); 576 intel_de_posting_read(dev_priv, reg); 577 578 /* 579 * Until the pipe starts PIPEDSL reads will return a stale value, 580 * which causes an apparent vblank timestamp jump when PIPEDSL 581 * resets to its proper value. That also messes up the frame count 582 * when it's derived from the timestamps. So let's wait for the 583 * pipe to start properly before we call drm_crtc_vblank_on() 584 */ 585 if (intel_crtc_max_vblank_count(new_crtc_state) == 0) 586 intel_wait_for_pipe_scanline_moving(crtc); 587 } 588 589 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) 590 { 591 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 592 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 593 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 594 enum pipe pipe = crtc->pipe; 595 i915_reg_t reg; 596 u32 val; 597 598 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe)); 599 600 /* 601 * Make sure planes won't keep trying to pump pixels to us, 602 * or we might hang the display. 603 */ 604 assert_planes_disabled(crtc); 605 606 reg = PIPECONF(cpu_transcoder); 607 val = intel_de_read(dev_priv, reg); 608 if ((val & PIPECONF_ENABLE) == 0) 609 return; 610 611 /* 612 * Double wide has implications for planes 613 * so best keep it disabled when not needed. 614 */ 615 if (old_crtc_state->double_wide) 616 val &= ~PIPECONF_DOUBLE_WIDE; 617 618 /* Don't disable pipe or pipe PLLs if needed */ 619 if (!IS_I830(dev_priv)) 620 val &= ~PIPECONF_ENABLE; 621 622 if (DISPLAY_VER(dev_priv) >= 12) 623 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 624 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 625 626 intel_de_write(dev_priv, reg, val); 627 if ((val & PIPECONF_ENABLE) == 0) 628 intel_wait_for_pipe_off(old_crtc_state); 629 } 630 631 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) 632 { 633 unsigned int size = 0; 634 int i; 635 636 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) 637 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width; 638 639 return size; 640 } 641 642 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info) 643 { 644 unsigned int size = 0; 645 int i; 646 647 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) { 648 unsigned int plane_size; 649 650 if (rem_info->plane[i].linear) 651 plane_size = rem_info->plane[i].size; 652 else 653 plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height; 654 655 if (plane_size == 0) 656 continue; 657 658 if (rem_info->plane_alignment) 659 size = ALIGN(size, rem_info->plane_alignment); 660 661 size += plane_size; 662 } 663 664 return size; 665 } 666 667 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) 668 { 669 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 670 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 671 672 return DISPLAY_VER(dev_priv) < 4 || 673 (plane->fbc && 674 plane_state->view.gtt.type == I915_GGTT_VIEW_NORMAL); 675 } 676 677 /* 678 * Convert the x/y offsets into a linear offset. 679 * Only valid with 0/180 degree rotation, which is fine since linear 680 * offset is only used with linear buffers on pre-hsw and tiled buffers 681 * with gen2/3, and 90/270 degree rotations isn't supported on any of them. 682 */ 683 u32 intel_fb_xy_to_linear(int x, int y, 684 const struct intel_plane_state *state, 685 int color_plane) 686 { 687 const struct drm_framebuffer *fb = state->hw.fb; 688 unsigned int cpp = fb->format->cpp[color_plane]; 689 unsigned int pitch = state->view.color_plane[color_plane].mapping_stride; 690 691 return y * pitch + x * cpp; 692 } 693 694 /* 695 * Add the x/y offsets derived from fb->offsets[] to the user 696 * specified plane src x/y offsets. The resulting x/y offsets 697 * specify the start of scanout from the beginning of the gtt mapping. 698 */ 699 void intel_add_fb_offsets(int *x, int *y, 700 const struct intel_plane_state *state, 701 int color_plane) 702 703 { 704 *x += state->view.color_plane[color_plane].x; 705 *y += state->view.color_plane[color_plane].y; 706 } 707 708 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 709 u32 pixel_format, u64 modifier) 710 { 711 struct intel_crtc *crtc; 712 struct intel_plane *plane; 713 714 if (!HAS_DISPLAY(dev_priv)) 715 return 0; 716 717 /* 718 * We assume the primary plane for pipe A has 719 * the highest stride limits of them all, 720 * if in case pipe A is disabled, use the first pipe from pipe_mask. 721 */ 722 crtc = intel_first_crtc(dev_priv); 723 if (!crtc) 724 return 0; 725 726 plane = to_intel_plane(crtc->base.primary); 727 728 return plane->max_stride(plane, pixel_format, modifier, 729 DRM_MODE_ROTATE_0); 730 } 731 732 static void 733 intel_set_plane_visible(struct intel_crtc_state *crtc_state, 734 struct intel_plane_state *plane_state, 735 bool visible) 736 { 737 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 738 739 plane_state->uapi.visible = visible; 740 741 if (visible) 742 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base); 743 else 744 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base); 745 } 746 747 static void fixup_plane_bitmasks(struct intel_crtc_state *crtc_state) 748 { 749 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 750 struct drm_plane *plane; 751 752 /* 753 * Active_planes aliases if multiple "primary" or cursor planes 754 * have been used on the same (or wrong) pipe. plane_mask uses 755 * unique ids, hence we can use that to reconstruct active_planes. 756 */ 757 crtc_state->enabled_planes = 0; 758 crtc_state->active_planes = 0; 759 760 drm_for_each_plane_mask(plane, &dev_priv->drm, 761 crtc_state->uapi.plane_mask) { 762 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id); 763 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id); 764 } 765 } 766 767 void intel_plane_disable_noatomic(struct intel_crtc *crtc, 768 struct intel_plane *plane) 769 { 770 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 771 struct intel_crtc_state *crtc_state = 772 to_intel_crtc_state(crtc->base.state); 773 struct intel_plane_state *plane_state = 774 to_intel_plane_state(plane->base.state); 775 776 drm_dbg_kms(&dev_priv->drm, 777 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n", 778 plane->base.base.id, plane->base.name, 779 crtc->base.base.id, crtc->base.name); 780 781 intel_set_plane_visible(crtc_state, plane_state, false); 782 fixup_plane_bitmasks(crtc_state); 783 crtc_state->data_rate[plane->id] = 0; 784 crtc_state->data_rate_y[plane->id] = 0; 785 crtc_state->rel_data_rate[plane->id] = 0; 786 crtc_state->rel_data_rate_y[plane->id] = 0; 787 crtc_state->min_cdclk[plane->id] = 0; 788 789 if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 && 790 hsw_ips_disable(crtc_state)) { 791 crtc_state->ips_enabled = false; 792 intel_crtc_wait_for_next_vblank(crtc); 793 } 794 795 /* 796 * Vblank time updates from the shadow to live plane control register 797 * are blocked if the memory self-refresh mode is active at that 798 * moment. So to make sure the plane gets truly disabled, disable 799 * first the self-refresh mode. The self-refresh enable bit in turn 800 * will be checked/applied by the HW only at the next frame start 801 * event which is after the vblank start event, so we need to have a 802 * wait-for-vblank between disabling the plane and the pipe. 803 */ 804 if (HAS_GMCH(dev_priv) && 805 intel_set_memory_cxsr(dev_priv, false)) 806 intel_crtc_wait_for_next_vblank(crtc); 807 808 /* 809 * Gen2 reports pipe underruns whenever all planes are disabled. 810 * So disable underrun reporting before all the planes get disabled. 811 */ 812 if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes) 813 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); 814 815 intel_plane_disable_arm(plane, crtc_state); 816 intel_crtc_wait_for_next_vblank(crtc); 817 } 818 819 unsigned int 820 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state) 821 { 822 int x = 0, y = 0; 823 824 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, 825 plane_state->view.color_plane[0].offset, 0); 826 827 return y; 828 } 829 830 static int 831 __intel_display_resume(struct drm_device *dev, 832 struct drm_atomic_state *state, 833 struct drm_modeset_acquire_ctx *ctx) 834 { 835 struct drm_crtc_state *crtc_state; 836 struct drm_crtc *crtc; 837 int i, ret; 838 839 intel_modeset_setup_hw_state(dev, ctx); 840 intel_vga_redisable(to_i915(dev)); 841 842 if (!state) 843 return 0; 844 845 /* 846 * We've duplicated the state, pointers to the old state are invalid. 847 * 848 * Don't attempt to use the old state until we commit the duplicated state. 849 */ 850 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 851 /* 852 * Force recalculation even if we restore 853 * current state. With fast modeset this may not result 854 * in a modeset when the state is compatible. 855 */ 856 crtc_state->mode_changed = true; 857 } 858 859 /* ignore any reset values/BIOS leftovers in the WM registers */ 860 if (!HAS_GMCH(to_i915(dev))) 861 to_intel_atomic_state(state)->skip_intermediate_wm = true; 862 863 ret = drm_atomic_helper_commit_duplicated_state(state, ctx); 864 865 drm_WARN_ON(dev, ret == -EDEADLK); 866 return ret; 867 } 868 869 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) 870 { 871 return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display && 872 intel_has_gpu_reset(to_gt(dev_priv))); 873 } 874 875 void intel_display_prepare_reset(struct drm_i915_private *dev_priv) 876 { 877 struct drm_device *dev = &dev_priv->drm; 878 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; 879 struct drm_atomic_state *state; 880 int ret; 881 882 if (!HAS_DISPLAY(dev_priv)) 883 return; 884 885 /* reset doesn't touch the display */ 886 if (!dev_priv->params.force_reset_modeset_test && 887 !gpu_reset_clobbers_display(dev_priv)) 888 return; 889 890 /* We have a modeset vs reset deadlock, defensively unbreak it. */ 891 set_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags); 892 smp_mb__after_atomic(); 893 wake_up_bit(&to_gt(dev_priv)->reset.flags, I915_RESET_MODESET); 894 895 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) { 896 drm_dbg_kms(&dev_priv->drm, 897 "Modeset potentially stuck, unbreaking through wedging\n"); 898 intel_gt_set_wedged(to_gt(dev_priv)); 899 } 900 901 /* 902 * Need mode_config.mutex so that we don't 903 * trample ongoing ->detect() and whatnot. 904 */ 905 mutex_lock(&dev->mode_config.mutex); 906 drm_modeset_acquire_init(ctx, 0); 907 while (1) { 908 ret = drm_modeset_lock_all_ctx(dev, ctx); 909 if (ret != -EDEADLK) 910 break; 911 912 drm_modeset_backoff(ctx); 913 } 914 /* 915 * Disabling the crtcs gracefully seems nicer. Also the 916 * g33 docs say we should at least disable all the planes. 917 */ 918 state = drm_atomic_helper_duplicate_state(dev, ctx); 919 if (IS_ERR(state)) { 920 ret = PTR_ERR(state); 921 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n", 922 ret); 923 return; 924 } 925 926 ret = drm_atomic_helper_disable_all(dev, ctx); 927 if (ret) { 928 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", 929 ret); 930 drm_atomic_state_put(state); 931 return; 932 } 933 934 dev_priv->modeset_restore_state = state; 935 state->acquire_ctx = ctx; 936 } 937 938 void intel_display_finish_reset(struct drm_i915_private *dev_priv) 939 { 940 struct drm_device *dev = &dev_priv->drm; 941 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; 942 struct drm_atomic_state *state; 943 int ret; 944 945 if (!HAS_DISPLAY(dev_priv)) 946 return; 947 948 /* reset doesn't touch the display */ 949 if (!test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags)) 950 return; 951 952 state = fetch_and_zero(&dev_priv->modeset_restore_state); 953 if (!state) 954 goto unlock; 955 956 /* reset doesn't touch the display */ 957 if (!gpu_reset_clobbers_display(dev_priv)) { 958 /* for testing only restore the display */ 959 ret = __intel_display_resume(dev, state, ctx); 960 if (ret) 961 drm_err(&dev_priv->drm, 962 "Restoring old state failed with %i\n", ret); 963 } else { 964 /* 965 * The display has been reset as well, 966 * so need a full re-initialization. 967 */ 968 intel_pps_unlock_regs_wa(dev_priv); 969 intel_modeset_init_hw(dev_priv); 970 intel_init_clock_gating(dev_priv); 971 intel_hpd_init(dev_priv); 972 973 ret = __intel_display_resume(dev, state, ctx); 974 if (ret) 975 drm_err(&dev_priv->drm, 976 "Restoring old state failed with %i\n", ret); 977 978 intel_hpd_poll_disable(dev_priv); 979 } 980 981 drm_atomic_state_put(state); 982 unlock: 983 drm_modeset_drop_locks(ctx); 984 drm_modeset_acquire_fini(ctx); 985 mutex_unlock(&dev->mode_config.mutex); 986 987 clear_bit_unlock(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags); 988 } 989 990 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) 991 { 992 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 993 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 994 enum pipe pipe = crtc->pipe; 995 u32 tmp; 996 997 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe)); 998 999 /* 1000 * Display WA #1153: icl 1001 * enable hardware to bypass the alpha math 1002 * and rounding for per-pixel values 00 and 0xff 1003 */ 1004 tmp |= PER_PIXEL_ALPHA_BYPASS_EN; 1005 /* 1006 * Display WA # 1605353570: icl 1007 * Set the pixel rounding bit to 1 for allowing 1008 * passthrough of Frame buffer pixels unmodified 1009 * across pipe 1010 */ 1011 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU; 1012 1013 /* 1014 * Underrun recovery must always be disabled on display 13+. 1015 * DG2 chicken bit meaning is inverted compared to other platforms. 1016 */ 1017 if (IS_DG2(dev_priv)) 1018 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2; 1019 else if (DISPLAY_VER(dev_priv) >= 13) 1020 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP; 1021 1022 /* Wa_14010547955:dg2 */ 1023 if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER)) 1024 tmp |= DG2_RENDER_CCSTAG_4_3_EN; 1025 1026 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp); 1027 } 1028 1029 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) 1030 { 1031 struct drm_crtc *crtc; 1032 bool cleanup_done; 1033 1034 drm_for_each_crtc(crtc, &dev_priv->drm) { 1035 struct drm_crtc_commit *commit; 1036 spin_lock(&crtc->commit_lock); 1037 commit = list_first_entry_or_null(&crtc->commit_list, 1038 struct drm_crtc_commit, commit_entry); 1039 cleanup_done = commit ? 1040 try_wait_for_completion(&commit->cleanup_done) : true; 1041 spin_unlock(&crtc->commit_lock); 1042 1043 if (cleanup_done) 1044 continue; 1045 1046 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc)); 1047 1048 return true; 1049 } 1050 1051 return false; 1052 } 1053 1054 /* 1055 * Finds the encoder associated with the given CRTC. This can only be 1056 * used when we know that the CRTC isn't feeding multiple encoders! 1057 */ 1058 struct intel_encoder * 1059 intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 1060 const struct intel_crtc_state *crtc_state) 1061 { 1062 const struct drm_connector_state *connector_state; 1063 const struct drm_connector *connector; 1064 struct intel_encoder *encoder = NULL; 1065 struct intel_crtc *master_crtc; 1066 int num_encoders = 0; 1067 int i; 1068 1069 master_crtc = intel_master_crtc(crtc_state); 1070 1071 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 1072 if (connector_state->crtc != &master_crtc->base) 1073 continue; 1074 1075 encoder = to_intel_encoder(connector_state->best_encoder); 1076 num_encoders++; 1077 } 1078 1079 drm_WARN(encoder->base.dev, num_encoders != 1, 1080 "%d encoders for pipe %c\n", 1081 num_encoders, pipe_name(master_crtc->pipe)); 1082 1083 return encoder; 1084 } 1085 1086 static void cpt_verify_modeset(struct drm_i915_private *dev_priv, 1087 enum pipe pipe) 1088 { 1089 i915_reg_t dslreg = PIPEDSL(pipe); 1090 u32 temp; 1091 1092 temp = intel_de_read(dev_priv, dslreg); 1093 udelay(500); 1094 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) { 1095 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) 1096 drm_err(&dev_priv->drm, 1097 "mode set failed: pipe %c stuck\n", 1098 pipe_name(pipe)); 1099 } 1100 } 1101 1102 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state) 1103 { 1104 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1105 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1106 const struct drm_rect *dst = &crtc_state->pch_pfit.dst; 1107 enum pipe pipe = crtc->pipe; 1108 int width = drm_rect_width(dst); 1109 int height = drm_rect_height(dst); 1110 int x = dst->x1; 1111 int y = dst->y1; 1112 1113 if (!crtc_state->pch_pfit.enabled) 1114 return; 1115 1116 /* Force use of hard-coded filter coefficients 1117 * as some pre-programmed values are broken, 1118 * e.g. x201. 1119 */ 1120 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) 1121 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 1122 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe)); 1123 else 1124 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 1125 PF_FILTER_MED_3x3); 1126 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), x << 16 | y); 1127 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), width << 16 | height); 1128 } 1129 1130 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc) 1131 { 1132 if (crtc->overlay) 1133 (void) intel_overlay_switch_off(crtc->overlay); 1134 1135 /* Let userspace switch the overlay on again. In most cases userspace 1136 * has to recompute where to put it anyway. 1137 */ 1138 } 1139 1140 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state) 1141 { 1142 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1143 1144 if (!crtc_state->nv12_planes) 1145 return false; 1146 1147 /* WA Display #0827: Gen9:all */ 1148 if (DISPLAY_VER(dev_priv) == 9) 1149 return true; 1150 1151 return false; 1152 } 1153 1154 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state) 1155 { 1156 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1157 1158 /* Wa_2006604312:icl,ehl */ 1159 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11) 1160 return true; 1161 1162 return false; 1163 } 1164 1165 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state) 1166 { 1167 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1168 1169 /* Wa_1604331009:icl,jsl,ehl */ 1170 if (is_hdr_mode(crtc_state) && 1171 crtc_state->active_planes & BIT(PLANE_CURSOR) && 1172 DISPLAY_VER(dev_priv) == 11) 1173 return true; 1174 1175 return false; 1176 } 1177 1178 static void intel_async_flip_vtd_wa(struct drm_i915_private *i915, 1179 enum pipe pipe, bool enable) 1180 { 1181 if (DISPLAY_VER(i915) == 9) { 1182 /* 1183 * "Plane N strech max must be programmed to 11b (x1) 1184 * when Async flips are enabled on that plane." 1185 */ 1186 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 1187 SKL_PLANE1_STRETCH_MAX_MASK, 1188 enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8); 1189 } else { 1190 /* Also needed on HSW/BDW albeit undocumented */ 1191 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 1192 HSW_PRI_STRETCH_MAX_MASK, 1193 enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8); 1194 } 1195 } 1196 1197 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state) 1198 { 1199 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1200 1201 return crtc_state->uapi.async_flip && i915_vtd_active(i915) && 1202 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915)); 1203 } 1204 1205 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state, 1206 const struct intel_crtc_state *new_crtc_state) 1207 { 1208 return (!old_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)) && 1209 new_crtc_state->active_planes; 1210 } 1211 1212 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state, 1213 const struct intel_crtc_state *new_crtc_state) 1214 { 1215 return old_crtc_state->active_planes && 1216 (!new_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)); 1217 } 1218 1219 static void intel_post_plane_update(struct intel_atomic_state *state, 1220 struct intel_crtc *crtc) 1221 { 1222 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1223 const struct intel_crtc_state *old_crtc_state = 1224 intel_atomic_get_old_crtc_state(state, crtc); 1225 const struct intel_crtc_state *new_crtc_state = 1226 intel_atomic_get_new_crtc_state(state, crtc); 1227 enum pipe pipe = crtc->pipe; 1228 1229 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); 1230 1231 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) 1232 intel_update_watermarks(dev_priv); 1233 1234 hsw_ips_post_update(state, crtc); 1235 intel_fbc_post_update(state, crtc); 1236 1237 if (needs_async_flip_vtd_wa(old_crtc_state) && 1238 !needs_async_flip_vtd_wa(new_crtc_state)) 1239 intel_async_flip_vtd_wa(dev_priv, pipe, false); 1240 1241 if (needs_nv12_wa(old_crtc_state) && 1242 !needs_nv12_wa(new_crtc_state)) 1243 skl_wa_827(dev_priv, pipe, false); 1244 1245 if (needs_scalerclk_wa(old_crtc_state) && 1246 !needs_scalerclk_wa(new_crtc_state)) 1247 icl_wa_scalerclkgating(dev_priv, pipe, false); 1248 1249 if (needs_cursorclk_wa(old_crtc_state) && 1250 !needs_cursorclk_wa(new_crtc_state)) 1251 icl_wa_cursorclkgating(dev_priv, pipe, false); 1252 1253 intel_drrs_activate(new_crtc_state); 1254 } 1255 1256 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state, 1257 struct intel_crtc *crtc) 1258 { 1259 const struct intel_crtc_state *crtc_state = 1260 intel_atomic_get_new_crtc_state(state, crtc); 1261 u8 update_planes = crtc_state->update_planes; 1262 const struct intel_plane_state *plane_state; 1263 struct intel_plane *plane; 1264 int i; 1265 1266 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1267 if (plane->pipe == crtc->pipe && 1268 update_planes & BIT(plane->id)) 1269 plane->enable_flip_done(plane); 1270 } 1271 } 1272 1273 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state, 1274 struct intel_crtc *crtc) 1275 { 1276 const struct intel_crtc_state *crtc_state = 1277 intel_atomic_get_new_crtc_state(state, crtc); 1278 u8 update_planes = crtc_state->update_planes; 1279 const struct intel_plane_state *plane_state; 1280 struct intel_plane *plane; 1281 int i; 1282 1283 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1284 if (plane->pipe == crtc->pipe && 1285 update_planes & BIT(plane->id)) 1286 plane->disable_flip_done(plane); 1287 } 1288 } 1289 1290 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state, 1291 struct intel_crtc *crtc) 1292 { 1293 const struct intel_crtc_state *old_crtc_state = 1294 intel_atomic_get_old_crtc_state(state, crtc); 1295 const struct intel_crtc_state *new_crtc_state = 1296 intel_atomic_get_new_crtc_state(state, crtc); 1297 u8 update_planes = new_crtc_state->update_planes; 1298 const struct intel_plane_state *old_plane_state; 1299 struct intel_plane *plane; 1300 bool need_vbl_wait = false; 1301 int i; 1302 1303 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1304 if (plane->need_async_flip_disable_wa && 1305 plane->pipe == crtc->pipe && 1306 update_planes & BIT(plane->id)) { 1307 /* 1308 * Apart from the async flip bit we want to 1309 * preserve the old state for the plane. 1310 */ 1311 plane->async_flip(plane, old_crtc_state, 1312 old_plane_state, false); 1313 need_vbl_wait = true; 1314 } 1315 } 1316 1317 if (need_vbl_wait) 1318 intel_crtc_wait_for_next_vblank(crtc); 1319 } 1320 1321 static void intel_pre_plane_update(struct intel_atomic_state *state, 1322 struct intel_crtc *crtc) 1323 { 1324 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1325 const struct intel_crtc_state *old_crtc_state = 1326 intel_atomic_get_old_crtc_state(state, crtc); 1327 const struct intel_crtc_state *new_crtc_state = 1328 intel_atomic_get_new_crtc_state(state, crtc); 1329 enum pipe pipe = crtc->pipe; 1330 1331 intel_drrs_deactivate(old_crtc_state); 1332 1333 intel_psr_pre_plane_update(state, crtc); 1334 1335 if (hsw_ips_pre_update(state, crtc)) 1336 intel_crtc_wait_for_next_vblank(crtc); 1337 1338 if (intel_fbc_pre_update(state, crtc)) 1339 intel_crtc_wait_for_next_vblank(crtc); 1340 1341 if (!needs_async_flip_vtd_wa(old_crtc_state) && 1342 needs_async_flip_vtd_wa(new_crtc_state)) 1343 intel_async_flip_vtd_wa(dev_priv, pipe, true); 1344 1345 /* Display WA 827 */ 1346 if (!needs_nv12_wa(old_crtc_state) && 1347 needs_nv12_wa(new_crtc_state)) 1348 skl_wa_827(dev_priv, pipe, true); 1349 1350 /* Wa_2006604312:icl,ehl */ 1351 if (!needs_scalerclk_wa(old_crtc_state) && 1352 needs_scalerclk_wa(new_crtc_state)) 1353 icl_wa_scalerclkgating(dev_priv, pipe, true); 1354 1355 /* Wa_1604331009:icl,jsl,ehl */ 1356 if (!needs_cursorclk_wa(old_crtc_state) && 1357 needs_cursorclk_wa(new_crtc_state)) 1358 icl_wa_cursorclkgating(dev_priv, pipe, true); 1359 1360 /* 1361 * Vblank time updates from the shadow to live plane control register 1362 * are blocked if the memory self-refresh mode is active at that 1363 * moment. So to make sure the plane gets truly disabled, disable 1364 * first the self-refresh mode. The self-refresh enable bit in turn 1365 * will be checked/applied by the HW only at the next frame start 1366 * event which is after the vblank start event, so we need to have a 1367 * wait-for-vblank between disabling the plane and the pipe. 1368 */ 1369 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active && 1370 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) 1371 intel_crtc_wait_for_next_vblank(crtc); 1372 1373 /* 1374 * IVB workaround: must disable low power watermarks for at least 1375 * one frame before enabling scaling. LP watermarks can be re-enabled 1376 * when scaling is disabled. 1377 * 1378 * WaCxSRDisabledForSpriteScaling:ivb 1379 */ 1380 if (old_crtc_state->hw.active && 1381 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv)) 1382 intel_crtc_wait_for_next_vblank(crtc); 1383 1384 /* 1385 * If we're doing a modeset we don't need to do any 1386 * pre-vblank watermark programming here. 1387 */ 1388 if (!intel_crtc_needs_modeset(new_crtc_state)) { 1389 /* 1390 * For platforms that support atomic watermarks, program the 1391 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these 1392 * will be the intermediate values that are safe for both pre- and 1393 * post- vblank; when vblank happens, the 'active' values will be set 1394 * to the final 'target' values and we'll do this again to get the 1395 * optimal watermarks. For gen9+ platforms, the values we program here 1396 * will be the final target values which will get automatically latched 1397 * at vblank time; no further programming will be necessary. 1398 * 1399 * If a platform hasn't been transitioned to atomic watermarks yet, 1400 * we'll continue to update watermarks the old way, if flags tell 1401 * us to. 1402 */ 1403 if (!intel_initial_watermarks(state, crtc)) 1404 if (new_crtc_state->update_wm_pre) 1405 intel_update_watermarks(dev_priv); 1406 } 1407 1408 /* 1409 * Gen2 reports pipe underruns whenever all planes are disabled. 1410 * So disable underrun reporting before all the planes get disabled. 1411 * 1412 * We do this after .initial_watermarks() so that we have a 1413 * chance of catching underruns with the intermediate watermarks 1414 * vs. the old plane configuration. 1415 */ 1416 if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state)) 1417 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1418 1419 /* 1420 * WA for platforms where async address update enable bit 1421 * is double buffered and only latched at start of vblank. 1422 */ 1423 if (old_crtc_state->uapi.async_flip && !new_crtc_state->uapi.async_flip) 1424 intel_crtc_async_flip_disable_wa(state, crtc); 1425 } 1426 1427 static void intel_crtc_disable_planes(struct intel_atomic_state *state, 1428 struct intel_crtc *crtc) 1429 { 1430 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1431 const struct intel_crtc_state *new_crtc_state = 1432 intel_atomic_get_new_crtc_state(state, crtc); 1433 unsigned int update_mask = new_crtc_state->update_planes; 1434 const struct intel_plane_state *old_plane_state; 1435 struct intel_plane *plane; 1436 unsigned fb_bits = 0; 1437 int i; 1438 1439 intel_crtc_dpms_overlay_disable(crtc); 1440 1441 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1442 if (crtc->pipe != plane->pipe || 1443 !(update_mask & BIT(plane->id))) 1444 continue; 1445 1446 intel_plane_disable_arm(plane, new_crtc_state); 1447 1448 if (old_plane_state->uapi.visible) 1449 fb_bits |= plane->frontbuffer_bit; 1450 } 1451 1452 intel_frontbuffer_flip(dev_priv, fb_bits); 1453 } 1454 1455 /* 1456 * intel_connector_primary_encoder - get the primary encoder for a connector 1457 * @connector: connector for which to return the encoder 1458 * 1459 * Returns the primary encoder for a connector. There is a 1:1 mapping from 1460 * all connectors to their encoder, except for DP-MST connectors which have 1461 * both a virtual and a primary encoder. These DP-MST primary encoders can be 1462 * pointed to by as many DP-MST connectors as there are pipes. 1463 */ 1464 static struct intel_encoder * 1465 intel_connector_primary_encoder(struct intel_connector *connector) 1466 { 1467 struct intel_encoder *encoder; 1468 1469 if (connector->mst_port) 1470 return &dp_to_dig_port(connector->mst_port)->base; 1471 1472 encoder = intel_attached_encoder(connector); 1473 drm_WARN_ON(connector->base.dev, !encoder); 1474 1475 return encoder; 1476 } 1477 1478 static void intel_encoders_update_prepare(struct intel_atomic_state *state) 1479 { 1480 struct drm_i915_private *i915 = to_i915(state->base.dev); 1481 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 1482 struct intel_crtc *crtc; 1483 struct drm_connector_state *new_conn_state; 1484 struct drm_connector *connector; 1485 int i; 1486 1487 /* 1488 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits. 1489 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook. 1490 */ 1491 if (i915->dpll.mgr) { 1492 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1493 if (intel_crtc_needs_modeset(new_crtc_state)) 1494 continue; 1495 1496 new_crtc_state->shared_dpll = old_crtc_state->shared_dpll; 1497 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state; 1498 } 1499 } 1500 1501 if (!state->modeset) 1502 return; 1503 1504 for_each_new_connector_in_state(&state->base, connector, new_conn_state, 1505 i) { 1506 struct intel_connector *intel_connector; 1507 struct intel_encoder *encoder; 1508 struct intel_crtc *crtc; 1509 1510 if (!intel_connector_needs_modeset(state, connector)) 1511 continue; 1512 1513 intel_connector = to_intel_connector(connector); 1514 encoder = intel_connector_primary_encoder(intel_connector); 1515 if (!encoder->update_prepare) 1516 continue; 1517 1518 crtc = new_conn_state->crtc ? 1519 to_intel_crtc(new_conn_state->crtc) : NULL; 1520 encoder->update_prepare(state, encoder, crtc); 1521 } 1522 } 1523 1524 static void intel_encoders_update_complete(struct intel_atomic_state *state) 1525 { 1526 struct drm_connector_state *new_conn_state; 1527 struct drm_connector *connector; 1528 int i; 1529 1530 if (!state->modeset) 1531 return; 1532 1533 for_each_new_connector_in_state(&state->base, connector, new_conn_state, 1534 i) { 1535 struct intel_connector *intel_connector; 1536 struct intel_encoder *encoder; 1537 struct intel_crtc *crtc; 1538 1539 if (!intel_connector_needs_modeset(state, connector)) 1540 continue; 1541 1542 intel_connector = to_intel_connector(connector); 1543 encoder = intel_connector_primary_encoder(intel_connector); 1544 if (!encoder->update_complete) 1545 continue; 1546 1547 crtc = new_conn_state->crtc ? 1548 to_intel_crtc(new_conn_state->crtc) : NULL; 1549 encoder->update_complete(state, encoder, crtc); 1550 } 1551 } 1552 1553 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state, 1554 struct intel_crtc *crtc) 1555 { 1556 const struct intel_crtc_state *crtc_state = 1557 intel_atomic_get_new_crtc_state(state, crtc); 1558 const struct drm_connector_state *conn_state; 1559 struct drm_connector *conn; 1560 int i; 1561 1562 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1563 struct intel_encoder *encoder = 1564 to_intel_encoder(conn_state->best_encoder); 1565 1566 if (conn_state->crtc != &crtc->base) 1567 continue; 1568 1569 if (encoder->pre_pll_enable) 1570 encoder->pre_pll_enable(state, encoder, 1571 crtc_state, conn_state); 1572 } 1573 } 1574 1575 static void intel_encoders_pre_enable(struct intel_atomic_state *state, 1576 struct intel_crtc *crtc) 1577 { 1578 const struct intel_crtc_state *crtc_state = 1579 intel_atomic_get_new_crtc_state(state, crtc); 1580 const struct drm_connector_state *conn_state; 1581 struct drm_connector *conn; 1582 int i; 1583 1584 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1585 struct intel_encoder *encoder = 1586 to_intel_encoder(conn_state->best_encoder); 1587 1588 if (conn_state->crtc != &crtc->base) 1589 continue; 1590 1591 if (encoder->pre_enable) 1592 encoder->pre_enable(state, encoder, 1593 crtc_state, conn_state); 1594 } 1595 } 1596 1597 static void intel_encoders_enable(struct intel_atomic_state *state, 1598 struct intel_crtc *crtc) 1599 { 1600 const struct intel_crtc_state *crtc_state = 1601 intel_atomic_get_new_crtc_state(state, crtc); 1602 const struct drm_connector_state *conn_state; 1603 struct drm_connector *conn; 1604 int i; 1605 1606 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1607 struct intel_encoder *encoder = 1608 to_intel_encoder(conn_state->best_encoder); 1609 1610 if (conn_state->crtc != &crtc->base) 1611 continue; 1612 1613 if (encoder->enable) 1614 encoder->enable(state, encoder, 1615 crtc_state, conn_state); 1616 intel_opregion_notify_encoder(encoder, true); 1617 } 1618 } 1619 1620 static void intel_encoders_disable(struct intel_atomic_state *state, 1621 struct intel_crtc *crtc) 1622 { 1623 const struct intel_crtc_state *old_crtc_state = 1624 intel_atomic_get_old_crtc_state(state, crtc); 1625 const struct drm_connector_state *old_conn_state; 1626 struct drm_connector *conn; 1627 int i; 1628 1629 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1630 struct intel_encoder *encoder = 1631 to_intel_encoder(old_conn_state->best_encoder); 1632 1633 if (old_conn_state->crtc != &crtc->base) 1634 continue; 1635 1636 intel_opregion_notify_encoder(encoder, false); 1637 if (encoder->disable) 1638 encoder->disable(state, encoder, 1639 old_crtc_state, old_conn_state); 1640 } 1641 } 1642 1643 static void intel_encoders_post_disable(struct intel_atomic_state *state, 1644 struct intel_crtc *crtc) 1645 { 1646 const struct intel_crtc_state *old_crtc_state = 1647 intel_atomic_get_old_crtc_state(state, crtc); 1648 const struct drm_connector_state *old_conn_state; 1649 struct drm_connector *conn; 1650 int i; 1651 1652 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1653 struct intel_encoder *encoder = 1654 to_intel_encoder(old_conn_state->best_encoder); 1655 1656 if (old_conn_state->crtc != &crtc->base) 1657 continue; 1658 1659 if (encoder->post_disable) 1660 encoder->post_disable(state, encoder, 1661 old_crtc_state, old_conn_state); 1662 } 1663 } 1664 1665 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state, 1666 struct intel_crtc *crtc) 1667 { 1668 const struct intel_crtc_state *old_crtc_state = 1669 intel_atomic_get_old_crtc_state(state, crtc); 1670 const struct drm_connector_state *old_conn_state; 1671 struct drm_connector *conn; 1672 int i; 1673 1674 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1675 struct intel_encoder *encoder = 1676 to_intel_encoder(old_conn_state->best_encoder); 1677 1678 if (old_conn_state->crtc != &crtc->base) 1679 continue; 1680 1681 if (encoder->post_pll_disable) 1682 encoder->post_pll_disable(state, encoder, 1683 old_crtc_state, old_conn_state); 1684 } 1685 } 1686 1687 static void intel_encoders_update_pipe(struct intel_atomic_state *state, 1688 struct intel_crtc *crtc) 1689 { 1690 const struct intel_crtc_state *crtc_state = 1691 intel_atomic_get_new_crtc_state(state, crtc); 1692 const struct drm_connector_state *conn_state; 1693 struct drm_connector *conn; 1694 int i; 1695 1696 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1697 struct intel_encoder *encoder = 1698 to_intel_encoder(conn_state->best_encoder); 1699 1700 if (conn_state->crtc != &crtc->base) 1701 continue; 1702 1703 if (encoder->update_pipe) 1704 encoder->update_pipe(state, encoder, 1705 crtc_state, conn_state); 1706 } 1707 } 1708 1709 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state) 1710 { 1711 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1712 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 1713 1714 plane->disable_arm(plane, crtc_state); 1715 } 1716 1717 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1718 { 1719 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1720 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1721 1722 if (crtc_state->has_pch_encoder) { 1723 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1724 &crtc_state->fdi_m_n); 1725 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1726 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1727 &crtc_state->dp_m_n); 1728 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1729 &crtc_state->dp_m2_n2); 1730 } 1731 1732 intel_set_transcoder_timings(crtc_state); 1733 1734 ilk_set_pipeconf(crtc_state); 1735 } 1736 1737 static void ilk_crtc_enable(struct intel_atomic_state *state, 1738 struct intel_crtc *crtc) 1739 { 1740 const struct intel_crtc_state *new_crtc_state = 1741 intel_atomic_get_new_crtc_state(state, crtc); 1742 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1743 enum pipe pipe = crtc->pipe; 1744 1745 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1746 return; 1747 1748 /* 1749 * Sometimes spurious CPU pipe underruns happen during FDI 1750 * training, at least with VGA+HDMI cloning. Suppress them. 1751 * 1752 * On ILK we get an occasional spurious CPU pipe underruns 1753 * between eDP port A enable and vdd enable. Also PCH port 1754 * enable seems to result in the occasional CPU pipe underrun. 1755 * 1756 * Spurious PCH underruns also occur during PCH enabling. 1757 */ 1758 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1759 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 1760 1761 ilk_configure_cpu_transcoder(new_crtc_state); 1762 1763 intel_set_pipe_src_size(new_crtc_state); 1764 1765 crtc->active = true; 1766 1767 intel_encoders_pre_enable(state, crtc); 1768 1769 if (new_crtc_state->has_pch_encoder) { 1770 ilk_pch_pre_enable(state, crtc); 1771 } else { 1772 assert_fdi_tx_disabled(dev_priv, pipe); 1773 assert_fdi_rx_disabled(dev_priv, pipe); 1774 } 1775 1776 ilk_pfit_enable(new_crtc_state); 1777 1778 /* 1779 * On ILK+ LUT must be loaded before the pipe is running but with 1780 * clocks enabled 1781 */ 1782 intel_color_load_luts(new_crtc_state); 1783 intel_color_commit_noarm(new_crtc_state); 1784 intel_color_commit_arm(new_crtc_state); 1785 /* update DSPCNTR to configure gamma for pipe bottom color */ 1786 intel_disable_primary_plane(new_crtc_state); 1787 1788 intel_initial_watermarks(state, crtc); 1789 intel_enable_transcoder(new_crtc_state); 1790 1791 if (new_crtc_state->has_pch_encoder) 1792 ilk_pch_enable(state, crtc); 1793 1794 intel_crtc_vblank_on(new_crtc_state); 1795 1796 intel_encoders_enable(state, crtc); 1797 1798 if (HAS_PCH_CPT(dev_priv)) 1799 cpt_verify_modeset(dev_priv, pipe); 1800 1801 /* 1802 * Must wait for vblank to avoid spurious PCH FIFO underruns. 1803 * And a second vblank wait is needed at least on ILK with 1804 * some interlaced HDMI modes. Let's do the double wait always 1805 * in case there are more corner cases we don't know about. 1806 */ 1807 if (new_crtc_state->has_pch_encoder) { 1808 intel_crtc_wait_for_next_vblank(crtc); 1809 intel_crtc_wait_for_next_vblank(crtc); 1810 } 1811 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1812 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 1813 } 1814 1815 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, 1816 enum pipe pipe, bool apply) 1817 { 1818 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)); 1819 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS; 1820 1821 if (apply) 1822 val |= mask; 1823 else 1824 val &= ~mask; 1825 1826 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val); 1827 } 1828 1829 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state) 1830 { 1831 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1832 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1833 1834 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe), 1835 HSW_LINETIME(crtc_state->linetime) | 1836 HSW_IPS_LINETIME(crtc_state->ips_linetime)); 1837 } 1838 1839 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) 1840 { 1841 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1842 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1843 i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder); 1844 u32 val; 1845 1846 val = intel_de_read(dev_priv, reg); 1847 val &= ~HSW_FRAME_START_DELAY_MASK; 1848 val |= HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 1849 intel_de_write(dev_priv, reg, val); 1850 } 1851 1852 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state, 1853 const struct intel_crtc_state *crtc_state) 1854 { 1855 struct intel_crtc *master_crtc = intel_master_crtc(crtc_state); 1856 1857 /* 1858 * Enable sequence steps 1-7 on bigjoiner master 1859 */ 1860 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1861 intel_encoders_pre_pll_enable(state, master_crtc); 1862 1863 if (crtc_state->shared_dpll) 1864 intel_enable_shared_dpll(crtc_state); 1865 1866 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1867 intel_encoders_pre_enable(state, master_crtc); 1868 } 1869 1870 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1871 { 1872 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1873 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1874 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1875 1876 if (crtc_state->has_pch_encoder) { 1877 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1878 &crtc_state->fdi_m_n); 1879 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1880 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1881 &crtc_state->dp_m_n); 1882 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1883 &crtc_state->dp_m2_n2); 1884 } 1885 1886 intel_set_transcoder_timings(crtc_state); 1887 1888 if (cpu_transcoder != TRANSCODER_EDP) 1889 intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder), 1890 crtc_state->pixel_multiplier - 1); 1891 1892 hsw_set_frame_start_delay(crtc_state); 1893 1894 hsw_set_transconf(crtc_state); 1895 } 1896 1897 static void hsw_crtc_enable(struct intel_atomic_state *state, 1898 struct intel_crtc *crtc) 1899 { 1900 const struct intel_crtc_state *new_crtc_state = 1901 intel_atomic_get_new_crtc_state(state, crtc); 1902 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1903 enum pipe pipe = crtc->pipe, hsw_workaround_pipe; 1904 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 1905 bool psl_clkgate_wa; 1906 1907 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1908 return; 1909 1910 if (!new_crtc_state->bigjoiner_pipes) { 1911 intel_encoders_pre_pll_enable(state, crtc); 1912 1913 if (new_crtc_state->shared_dpll) 1914 intel_enable_shared_dpll(new_crtc_state); 1915 1916 intel_encoders_pre_enable(state, crtc); 1917 } else { 1918 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state); 1919 } 1920 1921 intel_dsc_enable(new_crtc_state); 1922 1923 if (DISPLAY_VER(dev_priv) >= 13) 1924 intel_uncompressed_joiner_enable(new_crtc_state); 1925 1926 intel_set_pipe_src_size(new_crtc_state); 1927 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 1928 bdw_set_pipemisc(new_crtc_state); 1929 1930 if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) && 1931 !transcoder_is_dsi(cpu_transcoder)) 1932 hsw_configure_cpu_transcoder(new_crtc_state); 1933 1934 crtc->active = true; 1935 1936 /* Display WA #1180: WaDisableScalarClockGating: glk */ 1937 psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 && 1938 new_crtc_state->pch_pfit.enabled; 1939 if (psl_clkgate_wa) 1940 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true); 1941 1942 if (DISPLAY_VER(dev_priv) >= 9) 1943 skl_pfit_enable(new_crtc_state); 1944 else 1945 ilk_pfit_enable(new_crtc_state); 1946 1947 /* 1948 * On ILK+ LUT must be loaded before the pipe is running but with 1949 * clocks enabled 1950 */ 1951 intel_color_load_luts(new_crtc_state); 1952 intel_color_commit_noarm(new_crtc_state); 1953 intel_color_commit_arm(new_crtc_state); 1954 /* update DSPCNTR to configure gamma/csc for pipe bottom color */ 1955 if (DISPLAY_VER(dev_priv) < 9) 1956 intel_disable_primary_plane(new_crtc_state); 1957 1958 hsw_set_linetime_wm(new_crtc_state); 1959 1960 if (DISPLAY_VER(dev_priv) >= 11) 1961 icl_set_pipe_chicken(new_crtc_state); 1962 1963 intel_initial_watermarks(state, crtc); 1964 1965 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 1966 intel_crtc_vblank_on(new_crtc_state); 1967 1968 intel_encoders_enable(state, crtc); 1969 1970 if (psl_clkgate_wa) { 1971 intel_crtc_wait_for_next_vblank(crtc); 1972 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false); 1973 } 1974 1975 /* If we change the relative order between pipe/planes enabling, we need 1976 * to change the workaround. */ 1977 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe; 1978 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { 1979 struct intel_crtc *wa_crtc; 1980 1981 wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe); 1982 1983 intel_crtc_wait_for_next_vblank(wa_crtc); 1984 intel_crtc_wait_for_next_vblank(wa_crtc); 1985 } 1986 } 1987 1988 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state) 1989 { 1990 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1991 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1992 enum pipe pipe = crtc->pipe; 1993 1994 /* To avoid upsetting the power well on haswell only disable the pfit if 1995 * it's in use. The hw state code will make sure we get this right. */ 1996 if (!old_crtc_state->pch_pfit.enabled) 1997 return; 1998 1999 intel_de_write_fw(dev_priv, PF_CTL(pipe), 0); 2000 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0); 2001 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0); 2002 } 2003 2004 static void ilk_crtc_disable(struct intel_atomic_state *state, 2005 struct intel_crtc *crtc) 2006 { 2007 const struct intel_crtc_state *old_crtc_state = 2008 intel_atomic_get_old_crtc_state(state, crtc); 2009 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2010 enum pipe pipe = crtc->pipe; 2011 2012 /* 2013 * Sometimes spurious CPU pipe underruns happen when the 2014 * pipe is already disabled, but FDI RX/TX is still enabled. 2015 * Happens at least with VGA+HDMI cloning. Suppress them. 2016 */ 2017 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 2018 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 2019 2020 intel_encoders_disable(state, crtc); 2021 2022 intel_crtc_vblank_off(old_crtc_state); 2023 2024 intel_disable_transcoder(old_crtc_state); 2025 2026 ilk_pfit_disable(old_crtc_state); 2027 2028 if (old_crtc_state->has_pch_encoder) 2029 ilk_pch_disable(state, crtc); 2030 2031 intel_encoders_post_disable(state, crtc); 2032 2033 if (old_crtc_state->has_pch_encoder) 2034 ilk_pch_post_disable(state, crtc); 2035 2036 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2037 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 2038 } 2039 2040 static void hsw_crtc_disable(struct intel_atomic_state *state, 2041 struct intel_crtc *crtc) 2042 { 2043 const struct intel_crtc_state *old_crtc_state = 2044 intel_atomic_get_old_crtc_state(state, crtc); 2045 2046 /* 2047 * FIXME collapse everything to one hook. 2048 * Need care with mst->ddi interactions. 2049 */ 2050 if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) { 2051 intel_encoders_disable(state, crtc); 2052 intel_encoders_post_disable(state, crtc); 2053 } 2054 } 2055 2056 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) 2057 { 2058 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2059 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2060 2061 if (!crtc_state->gmch_pfit.control) 2062 return; 2063 2064 /* 2065 * The panel fitter should only be adjusted whilst the pipe is disabled, 2066 * according to register description and PRM. 2067 */ 2068 drm_WARN_ON(&dev_priv->drm, 2069 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE); 2070 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 2071 2072 intel_de_write(dev_priv, PFIT_PGM_RATIOS, 2073 crtc_state->gmch_pfit.pgm_ratios); 2074 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control); 2075 2076 /* Border color in case we don't scale up to the full screen. Black by 2077 * default, change to something else for debugging. */ 2078 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); 2079 } 2080 2081 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) 2082 { 2083 if (phy == PHY_NONE) 2084 return false; 2085 else if (IS_DG2(dev_priv)) 2086 /* 2087 * DG2 outputs labelled as "combo PHY" in the bspec use 2088 * SNPS PHYs with completely different programming, 2089 * hence we always return false here. 2090 */ 2091 return false; 2092 else if (IS_ALDERLAKE_S(dev_priv)) 2093 return phy <= PHY_E; 2094 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) 2095 return phy <= PHY_D; 2096 else if (IS_JSL_EHL(dev_priv)) 2097 return phy <= PHY_C; 2098 else if (DISPLAY_VER(dev_priv) >= 11) 2099 return phy <= PHY_B; 2100 else 2101 return false; 2102 } 2103 2104 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) 2105 { 2106 if (IS_DG2(dev_priv)) 2107 /* DG2's "TC1" output uses a SNPS PHY */ 2108 return false; 2109 else if (IS_ALDERLAKE_P(dev_priv)) 2110 return phy >= PHY_F && phy <= PHY_I; 2111 else if (IS_TIGERLAKE(dev_priv)) 2112 return phy >= PHY_D && phy <= PHY_I; 2113 else if (IS_ICELAKE(dev_priv)) 2114 return phy >= PHY_C && phy <= PHY_F; 2115 else 2116 return false; 2117 } 2118 2119 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy) 2120 { 2121 if (phy == PHY_NONE) 2122 return false; 2123 else if (IS_DG2(dev_priv)) 2124 /* 2125 * All four "combo" ports and the TC1 port (PHY E) use 2126 * Synopsis PHYs. 2127 */ 2128 return phy <= PHY_E; 2129 2130 return false; 2131 } 2132 2133 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) 2134 { 2135 if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD) 2136 return PHY_D + port - PORT_D_XELPD; 2137 else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1) 2138 return PHY_F + port - PORT_TC1; 2139 else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1) 2140 return PHY_B + port - PORT_TC1; 2141 else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1) 2142 return PHY_C + port - PORT_TC1; 2143 else if (IS_JSL_EHL(i915) && port == PORT_D) 2144 return PHY_A; 2145 2146 return PHY_A + port - PORT_A; 2147 } 2148 2149 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) 2150 { 2151 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port))) 2152 return TC_PORT_NONE; 2153 2154 if (DISPLAY_VER(dev_priv) >= 12) 2155 return TC_PORT_1 + port - PORT_TC1; 2156 else 2157 return TC_PORT_1 + port - PORT_C; 2158 } 2159 2160 enum intel_display_power_domain 2161 intel_aux_power_domain(struct intel_digital_port *dig_port) 2162 { 2163 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 2164 2165 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 2166 return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch); 2167 2168 return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch); 2169 } 2170 2171 static void get_crtc_power_domains(struct intel_crtc_state *crtc_state, 2172 struct intel_power_domain_mask *mask) 2173 { 2174 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2175 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2176 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2177 struct drm_encoder *encoder; 2178 enum pipe pipe = crtc->pipe; 2179 2180 bitmap_zero(mask->bits, POWER_DOMAIN_NUM); 2181 2182 if (!crtc_state->hw.active) 2183 return; 2184 2185 set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits); 2186 set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits); 2187 if (crtc_state->pch_pfit.enabled || 2188 crtc_state->pch_pfit.force_thru) 2189 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits); 2190 2191 drm_for_each_encoder_mask(encoder, &dev_priv->drm, 2192 crtc_state->uapi.encoder_mask) { 2193 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2194 2195 set_bit(intel_encoder->power_domain, mask->bits); 2196 } 2197 2198 if (HAS_DDI(dev_priv) && crtc_state->has_audio) 2199 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits); 2200 2201 if (crtc_state->shared_dpll) 2202 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits); 2203 2204 if (crtc_state->dsc.compression_enable) 2205 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits); 2206 } 2207 2208 static void 2209 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, 2210 struct intel_power_domain_mask *old_domains) 2211 { 2212 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2213 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2214 enum intel_display_power_domain domain; 2215 struct intel_power_domain_mask domains, new_domains; 2216 2217 get_crtc_power_domains(crtc_state, &domains); 2218 2219 bitmap_andnot(new_domains.bits, 2220 domains.bits, 2221 crtc->enabled_power_domains.mask.bits, 2222 POWER_DOMAIN_NUM); 2223 bitmap_andnot(old_domains->bits, 2224 crtc->enabled_power_domains.mask.bits, 2225 domains.bits, 2226 POWER_DOMAIN_NUM); 2227 2228 for_each_power_domain(domain, &new_domains) 2229 intel_display_power_get_in_set(dev_priv, 2230 &crtc->enabled_power_domains, 2231 domain); 2232 } 2233 2234 static void modeset_put_crtc_power_domains(struct intel_crtc *crtc, 2235 struct intel_power_domain_mask *domains) 2236 { 2237 intel_display_power_put_mask_in_set(to_i915(crtc->base.dev), 2238 &crtc->enabled_power_domains, 2239 domains); 2240 } 2241 2242 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 2243 { 2244 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2245 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2246 2247 if (intel_crtc_has_dp_encoder(crtc_state)) { 2248 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 2249 &crtc_state->dp_m_n); 2250 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 2251 &crtc_state->dp_m2_n2); 2252 } 2253 2254 intel_set_transcoder_timings(crtc_state); 2255 2256 i9xx_set_pipeconf(crtc_state); 2257 } 2258 2259 static void valleyview_crtc_enable(struct intel_atomic_state *state, 2260 struct intel_crtc *crtc) 2261 { 2262 const struct intel_crtc_state *new_crtc_state = 2263 intel_atomic_get_new_crtc_state(state, crtc); 2264 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2265 enum pipe pipe = crtc->pipe; 2266 2267 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 2268 return; 2269 2270 i9xx_configure_cpu_transcoder(new_crtc_state); 2271 2272 intel_set_pipe_src_size(new_crtc_state); 2273 2274 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 2275 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY); 2276 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0); 2277 } 2278 2279 crtc->active = true; 2280 2281 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2282 2283 intel_encoders_pre_pll_enable(state, crtc); 2284 2285 if (IS_CHERRYVIEW(dev_priv)) 2286 chv_enable_pll(new_crtc_state); 2287 else 2288 vlv_enable_pll(new_crtc_state); 2289 2290 intel_encoders_pre_enable(state, crtc); 2291 2292 i9xx_pfit_enable(new_crtc_state); 2293 2294 intel_color_load_luts(new_crtc_state); 2295 intel_color_commit_noarm(new_crtc_state); 2296 intel_color_commit_arm(new_crtc_state); 2297 /* update DSPCNTR to configure gamma for pipe bottom color */ 2298 intel_disable_primary_plane(new_crtc_state); 2299 2300 intel_initial_watermarks(state, crtc); 2301 intel_enable_transcoder(new_crtc_state); 2302 2303 intel_crtc_vblank_on(new_crtc_state); 2304 2305 intel_encoders_enable(state, crtc); 2306 } 2307 2308 static void i9xx_crtc_enable(struct intel_atomic_state *state, 2309 struct intel_crtc *crtc) 2310 { 2311 const struct intel_crtc_state *new_crtc_state = 2312 intel_atomic_get_new_crtc_state(state, crtc); 2313 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2314 enum pipe pipe = crtc->pipe; 2315 2316 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 2317 return; 2318 2319 i9xx_configure_cpu_transcoder(new_crtc_state); 2320 2321 intel_set_pipe_src_size(new_crtc_state); 2322 2323 crtc->active = true; 2324 2325 if (DISPLAY_VER(dev_priv) != 2) 2326 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2327 2328 intel_encoders_pre_enable(state, crtc); 2329 2330 i9xx_enable_pll(new_crtc_state); 2331 2332 i9xx_pfit_enable(new_crtc_state); 2333 2334 intel_color_load_luts(new_crtc_state); 2335 intel_color_commit_noarm(new_crtc_state); 2336 intel_color_commit_arm(new_crtc_state); 2337 /* update DSPCNTR to configure gamma for pipe bottom color */ 2338 intel_disable_primary_plane(new_crtc_state); 2339 2340 if (!intel_initial_watermarks(state, crtc)) 2341 intel_update_watermarks(dev_priv); 2342 intel_enable_transcoder(new_crtc_state); 2343 2344 intel_crtc_vblank_on(new_crtc_state); 2345 2346 intel_encoders_enable(state, crtc); 2347 2348 /* prevents spurious underruns */ 2349 if (DISPLAY_VER(dev_priv) == 2) 2350 intel_crtc_wait_for_next_vblank(crtc); 2351 } 2352 2353 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) 2354 { 2355 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 2356 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2357 2358 if (!old_crtc_state->gmch_pfit.control) 2359 return; 2360 2361 assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder); 2362 2363 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n", 2364 intel_de_read(dev_priv, PFIT_CONTROL)); 2365 intel_de_write(dev_priv, PFIT_CONTROL, 0); 2366 } 2367 2368 static void i9xx_crtc_disable(struct intel_atomic_state *state, 2369 struct intel_crtc *crtc) 2370 { 2371 struct intel_crtc_state *old_crtc_state = 2372 intel_atomic_get_old_crtc_state(state, crtc); 2373 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2374 enum pipe pipe = crtc->pipe; 2375 2376 /* 2377 * On gen2 planes are double buffered but the pipe isn't, so we must 2378 * wait for planes to fully turn off before disabling the pipe. 2379 */ 2380 if (DISPLAY_VER(dev_priv) == 2) 2381 intel_crtc_wait_for_next_vblank(crtc); 2382 2383 intel_encoders_disable(state, crtc); 2384 2385 intel_crtc_vblank_off(old_crtc_state); 2386 2387 intel_disable_transcoder(old_crtc_state); 2388 2389 i9xx_pfit_disable(old_crtc_state); 2390 2391 intel_encoders_post_disable(state, crtc); 2392 2393 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) { 2394 if (IS_CHERRYVIEW(dev_priv)) 2395 chv_disable_pll(dev_priv, pipe); 2396 else if (IS_VALLEYVIEW(dev_priv)) 2397 vlv_disable_pll(dev_priv, pipe); 2398 else 2399 i9xx_disable_pll(old_crtc_state); 2400 } 2401 2402 intel_encoders_post_pll_disable(state, crtc); 2403 2404 if (DISPLAY_VER(dev_priv) != 2) 2405 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 2406 2407 if (!dev_priv->wm_disp->initial_watermarks) 2408 intel_update_watermarks(dev_priv); 2409 2410 /* clock the pipe down to 640x480@60 to potentially save power */ 2411 if (IS_I830(dev_priv)) 2412 i830_enable_pipe(dev_priv, pipe); 2413 } 2414 2415 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, 2416 struct drm_modeset_acquire_ctx *ctx) 2417 { 2418 struct intel_encoder *encoder; 2419 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2420 struct intel_bw_state *bw_state = 2421 to_intel_bw_state(dev_priv->bw_obj.state); 2422 struct intel_cdclk_state *cdclk_state = 2423 to_intel_cdclk_state(dev_priv->cdclk.obj.state); 2424 struct intel_dbuf_state *dbuf_state = 2425 to_intel_dbuf_state(dev_priv->dbuf.obj.state); 2426 struct intel_crtc_state *crtc_state = 2427 to_intel_crtc_state(crtc->base.state); 2428 struct intel_plane *plane; 2429 struct drm_atomic_state *state; 2430 struct intel_crtc_state *temp_crtc_state; 2431 enum pipe pipe = crtc->pipe; 2432 int ret; 2433 2434 if (!crtc_state->hw.active) 2435 return; 2436 2437 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 2438 const struct intel_plane_state *plane_state = 2439 to_intel_plane_state(plane->base.state); 2440 2441 if (plane_state->uapi.visible) 2442 intel_plane_disable_noatomic(crtc, plane); 2443 } 2444 2445 state = drm_atomic_state_alloc(&dev_priv->drm); 2446 if (!state) { 2447 drm_dbg_kms(&dev_priv->drm, 2448 "failed to disable [CRTC:%d:%s], out of memory", 2449 crtc->base.base.id, crtc->base.name); 2450 return; 2451 } 2452 2453 state->acquire_ctx = ctx; 2454 2455 /* Everything's already locked, -EDEADLK can't happen. */ 2456 temp_crtc_state = intel_atomic_get_crtc_state(state, crtc); 2457 ret = drm_atomic_add_affected_connectors(state, &crtc->base); 2458 2459 drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret); 2460 2461 dev_priv->display->crtc_disable(to_intel_atomic_state(state), crtc); 2462 2463 drm_atomic_state_put(state); 2464 2465 drm_dbg_kms(&dev_priv->drm, 2466 "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", 2467 crtc->base.base.id, crtc->base.name); 2468 2469 crtc->active = false; 2470 crtc->base.enabled = false; 2471 2472 drm_WARN_ON(&dev_priv->drm, 2473 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0); 2474 crtc_state->uapi.active = false; 2475 crtc_state->uapi.connector_mask = 0; 2476 crtc_state->uapi.encoder_mask = 0; 2477 intel_crtc_free_hw_state(crtc_state); 2478 memset(&crtc_state->hw, 0, sizeof(crtc_state->hw)); 2479 2480 for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder) 2481 encoder->base.crtc = NULL; 2482 2483 intel_fbc_disable(crtc); 2484 intel_update_watermarks(dev_priv); 2485 intel_disable_shared_dpll(crtc_state); 2486 2487 intel_display_power_put_all_in_set(dev_priv, &crtc->enabled_power_domains); 2488 2489 cdclk_state->min_cdclk[pipe] = 0; 2490 cdclk_state->min_voltage_level[pipe] = 0; 2491 cdclk_state->active_pipes &= ~BIT(pipe); 2492 2493 dbuf_state->active_pipes &= ~BIT(pipe); 2494 2495 bw_state->data_rate[pipe] = 0; 2496 bw_state->num_active_planes[pipe] = 0; 2497 } 2498 2499 /* 2500 * turn all crtc's off, but do not adjust state 2501 * This has to be paired with a call to intel_modeset_setup_hw_state. 2502 */ 2503 int intel_display_suspend(struct drm_device *dev) 2504 { 2505 struct drm_i915_private *dev_priv = to_i915(dev); 2506 struct drm_atomic_state *state; 2507 int ret; 2508 2509 if (!HAS_DISPLAY(dev_priv)) 2510 return 0; 2511 2512 state = drm_atomic_helper_suspend(dev); 2513 ret = PTR_ERR_OR_ZERO(state); 2514 if (ret) 2515 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", 2516 ret); 2517 else 2518 dev_priv->modeset_restore_state = state; 2519 return ret; 2520 } 2521 2522 void intel_encoder_destroy(struct drm_encoder *encoder) 2523 { 2524 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2525 2526 drm_encoder_cleanup(encoder); 2527 kfree(intel_encoder); 2528 } 2529 2530 /* Cross check the actual hw state with our own modeset state tracking (and it's 2531 * internal consistency). */ 2532 static void intel_connector_verify_state(struct intel_crtc_state *crtc_state, 2533 struct drm_connector_state *conn_state) 2534 { 2535 struct intel_connector *connector = to_intel_connector(conn_state->connector); 2536 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2537 2538 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", 2539 connector->base.base.id, connector->base.name); 2540 2541 if (connector->get_hw_state(connector)) { 2542 struct intel_encoder *encoder = intel_attached_encoder(connector); 2543 2544 I915_STATE_WARN(!crtc_state, 2545 "connector enabled without attached crtc\n"); 2546 2547 if (!crtc_state) 2548 return; 2549 2550 I915_STATE_WARN(!crtc_state->hw.active, 2551 "connector is active, but attached crtc isn't\n"); 2552 2553 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) 2554 return; 2555 2556 I915_STATE_WARN(conn_state->best_encoder != &encoder->base, 2557 "atomic encoder doesn't match attached encoder\n"); 2558 2559 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, 2560 "attached encoder crtc differs from connector crtc\n"); 2561 } else { 2562 I915_STATE_WARN(crtc_state && crtc_state->hw.active, 2563 "attached crtc is active, but connector isn't\n"); 2564 I915_STATE_WARN(!crtc_state && conn_state->best_encoder, 2565 "best encoder set without crtc!\n"); 2566 } 2567 } 2568 2569 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) 2570 { 2571 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2572 2573 /* GDG double wide on either pipe, otherwise pipe A only */ 2574 return DISPLAY_VER(dev_priv) < 4 && 2575 (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); 2576 } 2577 2578 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) 2579 { 2580 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock; 2581 struct drm_rect src; 2582 2583 /* 2584 * We only use IF-ID interlacing. If we ever use 2585 * PF-ID we'll need to adjust the pixel_rate here. 2586 */ 2587 2588 if (!crtc_state->pch_pfit.enabled) 2589 return pixel_rate; 2590 2591 drm_rect_init(&src, 0, 0, 2592 drm_rect_width(&crtc_state->pipe_src) << 16, 2593 drm_rect_height(&crtc_state->pipe_src) << 16); 2594 2595 return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst, 2596 pixel_rate); 2597 } 2598 2599 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode, 2600 const struct drm_display_mode *timings) 2601 { 2602 mode->hdisplay = timings->crtc_hdisplay; 2603 mode->htotal = timings->crtc_htotal; 2604 mode->hsync_start = timings->crtc_hsync_start; 2605 mode->hsync_end = timings->crtc_hsync_end; 2606 2607 mode->vdisplay = timings->crtc_vdisplay; 2608 mode->vtotal = timings->crtc_vtotal; 2609 mode->vsync_start = timings->crtc_vsync_start; 2610 mode->vsync_end = timings->crtc_vsync_end; 2611 2612 mode->flags = timings->flags; 2613 mode->type = DRM_MODE_TYPE_DRIVER; 2614 2615 mode->clock = timings->crtc_clock; 2616 2617 drm_mode_set_name(mode); 2618 } 2619 2620 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) 2621 { 2622 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2623 2624 if (HAS_GMCH(dev_priv)) 2625 /* FIXME calculate proper pipe pixel rate for GMCH pfit */ 2626 crtc_state->pixel_rate = 2627 crtc_state->hw.pipe_mode.crtc_clock; 2628 else 2629 crtc_state->pixel_rate = 2630 ilk_pipe_pixel_rate(crtc_state); 2631 } 2632 2633 static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state *crtc_state, 2634 struct drm_display_mode *mode) 2635 { 2636 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2637 2638 if (num_pipes < 2) 2639 return; 2640 2641 mode->crtc_clock /= num_pipes; 2642 mode->crtc_hdisplay /= num_pipes; 2643 mode->crtc_hblank_start /= num_pipes; 2644 mode->crtc_hblank_end /= num_pipes; 2645 mode->crtc_hsync_start /= num_pipes; 2646 mode->crtc_hsync_end /= num_pipes; 2647 mode->crtc_htotal /= num_pipes; 2648 } 2649 2650 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state, 2651 struct drm_display_mode *mode) 2652 { 2653 int overlap = crtc_state->splitter.pixel_overlap; 2654 int n = crtc_state->splitter.link_count; 2655 2656 if (!crtc_state->splitter.enable) 2657 return; 2658 2659 /* 2660 * eDP MSO uses segment timings from EDID for transcoder 2661 * timings, but full mode for everything else. 2662 * 2663 * h_full = (h_segment - pixel_overlap) * link_count 2664 */ 2665 mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n; 2666 mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n; 2667 mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n; 2668 mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n; 2669 mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n; 2670 mode->crtc_htotal = (mode->crtc_htotal - overlap) * n; 2671 mode->crtc_clock *= n; 2672 } 2673 2674 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state) 2675 { 2676 struct drm_display_mode *mode = &crtc_state->hw.mode; 2677 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2678 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2679 2680 /* 2681 * Start with the adjusted_mode crtc timings, which 2682 * have been filled with the transcoder timings. 2683 */ 2684 drm_mode_copy(pipe_mode, adjusted_mode); 2685 2686 /* Expand MSO per-segment transcoder timings to full */ 2687 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2688 2689 /* 2690 * We want the full numbers in adjusted_mode normal timings, 2691 * adjusted_mode crtc timings are left with the raw transcoder 2692 * timings. 2693 */ 2694 intel_mode_from_crtc_timings(adjusted_mode, pipe_mode); 2695 2696 /* Populate the "user" mode with full numbers */ 2697 drm_mode_copy(mode, pipe_mode); 2698 intel_mode_from_crtc_timings(mode, mode); 2699 mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) * 2700 (intel_bigjoiner_num_pipes(crtc_state) ?: 1); 2701 mode->vdisplay = drm_rect_height(&crtc_state->pipe_src); 2702 2703 /* Derive per-pipe timings in case bigjoiner is used */ 2704 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2705 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2706 2707 intel_crtc_compute_pixel_rate(crtc_state); 2708 } 2709 2710 static void intel_encoder_get_config(struct intel_encoder *encoder, 2711 struct intel_crtc_state *crtc_state) 2712 { 2713 encoder->get_config(encoder, crtc_state); 2714 2715 intel_crtc_readout_derived_state(crtc_state); 2716 } 2717 2718 static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state *crtc_state) 2719 { 2720 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2721 int width, height; 2722 2723 if (num_pipes < 2) 2724 return; 2725 2726 width = drm_rect_width(&crtc_state->pipe_src); 2727 height = drm_rect_height(&crtc_state->pipe_src); 2728 2729 drm_rect_init(&crtc_state->pipe_src, 0, 0, 2730 width / num_pipes, height); 2731 } 2732 2733 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state) 2734 { 2735 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2736 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2737 2738 intel_bigjoiner_compute_pipe_src(crtc_state); 2739 2740 /* 2741 * Pipe horizontal size must be even in: 2742 * - DVO ganged mode 2743 * - LVDS dual channel mode 2744 * - Double wide pipe 2745 */ 2746 if (drm_rect_width(&crtc_state->pipe_src) & 1) { 2747 if (crtc_state->double_wide) { 2748 drm_dbg_kms(&i915->drm, 2749 "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n", 2750 crtc->base.base.id, crtc->base.name); 2751 return -EINVAL; 2752 } 2753 2754 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 2755 intel_is_dual_link_lvds(i915)) { 2756 drm_dbg_kms(&i915->drm, 2757 "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n", 2758 crtc->base.base.id, crtc->base.name); 2759 return -EINVAL; 2760 } 2761 } 2762 2763 return 0; 2764 } 2765 2766 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state) 2767 { 2768 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2769 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2770 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2771 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2772 int clock_limit = i915->max_dotclk_freq; 2773 2774 /* 2775 * Start with the adjusted_mode crtc timings, which 2776 * have been filled with the transcoder timings. 2777 */ 2778 drm_mode_copy(pipe_mode, adjusted_mode); 2779 2780 /* Expand MSO per-segment transcoder timings to full */ 2781 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2782 2783 /* Derive per-pipe timings in case bigjoiner is used */ 2784 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2785 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2786 2787 if (DISPLAY_VER(i915) < 4) { 2788 clock_limit = i915->max_cdclk_freq * 9 / 10; 2789 2790 /* 2791 * Enable double wide mode when the dot clock 2792 * is > 90% of the (display) core speed. 2793 */ 2794 if (intel_crtc_supports_double_wide(crtc) && 2795 pipe_mode->crtc_clock > clock_limit) { 2796 clock_limit = i915->max_dotclk_freq; 2797 crtc_state->double_wide = true; 2798 } 2799 } 2800 2801 if (pipe_mode->crtc_clock > clock_limit) { 2802 drm_dbg_kms(&i915->drm, 2803 "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", 2804 crtc->base.base.id, crtc->base.name, 2805 pipe_mode->crtc_clock, clock_limit, 2806 str_yes_no(crtc_state->double_wide)); 2807 return -EINVAL; 2808 } 2809 2810 return 0; 2811 } 2812 2813 static int intel_crtc_compute_config(struct intel_crtc *crtc, 2814 struct intel_crtc_state *crtc_state) 2815 { 2816 int ret; 2817 2818 ret = intel_crtc_compute_pipe_src(crtc_state); 2819 if (ret) 2820 return ret; 2821 2822 ret = intel_crtc_compute_pipe_mode(crtc_state); 2823 if (ret) 2824 return ret; 2825 2826 intel_crtc_compute_pixel_rate(crtc_state); 2827 2828 if (crtc_state->has_pch_encoder) 2829 return ilk_fdi_compute_config(crtc, crtc_state); 2830 2831 return 0; 2832 } 2833 2834 static void 2835 intel_reduce_m_n_ratio(u32 *num, u32 *den) 2836 { 2837 while (*num > DATA_LINK_M_N_MASK || 2838 *den > DATA_LINK_M_N_MASK) { 2839 *num >>= 1; 2840 *den >>= 1; 2841 } 2842 } 2843 2844 static void compute_m_n(unsigned int m, unsigned int n, 2845 u32 *ret_m, u32 *ret_n, 2846 bool constant_n) 2847 { 2848 /* 2849 * Several DP dongles in particular seem to be fussy about 2850 * too large link M/N values. Give N value as 0x8000 that 2851 * should be acceptable by specific devices. 0x8000 is the 2852 * specified fixed N value for asynchronous clock mode, 2853 * which the devices expect also in synchronous clock mode. 2854 */ 2855 if (constant_n) 2856 *ret_n = DP_LINK_CONSTANT_N_VALUE; 2857 else 2858 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); 2859 2860 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n); 2861 intel_reduce_m_n_ratio(ret_m, ret_n); 2862 } 2863 2864 void 2865 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes, 2866 int pixel_clock, int link_clock, 2867 struct intel_link_m_n *m_n, 2868 bool constant_n, bool fec_enable) 2869 { 2870 u32 data_clock = bits_per_pixel * pixel_clock; 2871 2872 if (fec_enable) 2873 data_clock = intel_dp_mode_to_fec_clock(data_clock); 2874 2875 m_n->tu = 64; 2876 compute_m_n(data_clock, 2877 link_clock * nlanes * 8, 2878 &m_n->data_m, &m_n->data_n, 2879 constant_n); 2880 2881 compute_m_n(pixel_clock, link_clock, 2882 &m_n->link_m, &m_n->link_n, 2883 constant_n); 2884 } 2885 2886 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv) 2887 { 2888 /* 2889 * There may be no VBT; and if the BIOS enabled SSC we can 2890 * just keep using it to avoid unnecessary flicker. Whereas if the 2891 * BIOS isn't using it, don't assume it will work even if the VBT 2892 * indicates as much. 2893 */ 2894 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { 2895 bool bios_lvds_use_ssc = intel_de_read(dev_priv, 2896 PCH_DREF_CONTROL) & 2897 DREF_SSC1_ENABLE; 2898 2899 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { 2900 drm_dbg_kms(&dev_priv->drm, 2901 "SSC %s by BIOS, overriding VBT which says %s\n", 2902 str_enabled_disabled(bios_lvds_use_ssc), 2903 str_enabled_disabled(dev_priv->vbt.lvds_use_ssc)); 2904 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; 2905 } 2906 } 2907 } 2908 2909 void intel_zero_m_n(struct intel_link_m_n *m_n) 2910 { 2911 /* corresponds to 0 register value */ 2912 memset(m_n, 0, sizeof(*m_n)); 2913 m_n->tu = 1; 2914 } 2915 2916 void intel_set_m_n(struct drm_i915_private *i915, 2917 const struct intel_link_m_n *m_n, 2918 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 2919 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 2920 { 2921 intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); 2922 intel_de_write(i915, data_n_reg, m_n->data_n); 2923 intel_de_write(i915, link_m_reg, m_n->link_m); 2924 /* 2925 * On BDW+ writing LINK_N arms the double buffered update 2926 * of all the M/N registers, so it must be written last. 2927 */ 2928 intel_de_write(i915, link_n_reg, m_n->link_n); 2929 } 2930 2931 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, 2932 enum transcoder transcoder) 2933 { 2934 if (IS_HASWELL(dev_priv)) 2935 return transcoder == TRANSCODER_EDP; 2936 2937 return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv); 2938 } 2939 2940 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, 2941 enum transcoder transcoder, 2942 const struct intel_link_m_n *m_n) 2943 { 2944 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2945 enum pipe pipe = crtc->pipe; 2946 2947 if (DISPLAY_VER(dev_priv) >= 5) 2948 intel_set_m_n(dev_priv, m_n, 2949 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 2950 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 2951 else 2952 intel_set_m_n(dev_priv, m_n, 2953 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 2954 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 2955 } 2956 2957 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, 2958 enum transcoder transcoder, 2959 const struct intel_link_m_n *m_n) 2960 { 2961 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2962 2963 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 2964 return; 2965 2966 intel_set_m_n(dev_priv, m_n, 2967 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 2968 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 2969 } 2970 2971 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) 2972 { 2973 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2974 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2975 enum pipe pipe = crtc->pipe; 2976 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2977 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2978 u32 crtc_vtotal, crtc_vblank_end; 2979 int vsyncshift = 0; 2980 2981 /* We need to be careful not to changed the adjusted mode, for otherwise 2982 * the hw state checker will get angry at the mismatch. */ 2983 crtc_vtotal = adjusted_mode->crtc_vtotal; 2984 crtc_vblank_end = adjusted_mode->crtc_vblank_end; 2985 2986 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 2987 /* the chip adds 2 halflines automatically */ 2988 crtc_vtotal -= 1; 2989 crtc_vblank_end -= 1; 2990 2991 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 2992 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; 2993 else 2994 vsyncshift = adjusted_mode->crtc_hsync_start - 2995 adjusted_mode->crtc_htotal / 2; 2996 if (vsyncshift < 0) 2997 vsyncshift += adjusted_mode->crtc_htotal; 2998 } 2999 3000 if (DISPLAY_VER(dev_priv) > 3) 3001 intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder), 3002 vsyncshift); 3003 3004 intel_de_write(dev_priv, HTOTAL(cpu_transcoder), 3005 (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16)); 3006 intel_de_write(dev_priv, HBLANK(cpu_transcoder), 3007 (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16)); 3008 intel_de_write(dev_priv, HSYNC(cpu_transcoder), 3009 (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16)); 3010 3011 intel_de_write(dev_priv, VTOTAL(cpu_transcoder), 3012 (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16)); 3013 intel_de_write(dev_priv, VBLANK(cpu_transcoder), 3014 (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16)); 3015 intel_de_write(dev_priv, VSYNC(cpu_transcoder), 3016 (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16)); 3017 3018 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be 3019 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is 3020 * documented on the DDI_FUNC_CTL register description, EDP Input Select 3021 * bits. */ 3022 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && 3023 (pipe == PIPE_B || pipe == PIPE_C)) 3024 intel_de_write(dev_priv, VTOTAL(pipe), 3025 intel_de_read(dev_priv, VTOTAL(cpu_transcoder))); 3026 3027 } 3028 3029 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) 3030 { 3031 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3032 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3033 int width = drm_rect_width(&crtc_state->pipe_src); 3034 int height = drm_rect_height(&crtc_state->pipe_src); 3035 enum pipe pipe = crtc->pipe; 3036 3037 /* pipesrc controls the size that is scaled from, which should 3038 * always be the user's requested size. 3039 */ 3040 intel_de_write(dev_priv, PIPESRC(pipe), 3041 PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1)); 3042 } 3043 3044 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) 3045 { 3046 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3047 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3048 3049 if (DISPLAY_VER(dev_priv) == 2) 3050 return false; 3051 3052 if (DISPLAY_VER(dev_priv) >= 9 || 3053 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 3054 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW; 3055 else 3056 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK; 3057 } 3058 3059 static void intel_get_transcoder_timings(struct intel_crtc *crtc, 3060 struct intel_crtc_state *pipe_config) 3061 { 3062 struct drm_device *dev = crtc->base.dev; 3063 struct drm_i915_private *dev_priv = to_i915(dev); 3064 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3065 u32 tmp; 3066 3067 tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder)); 3068 pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; 3069 pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; 3070 3071 if (!transcoder_is_dsi(cpu_transcoder)) { 3072 tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder)); 3073 pipe_config->hw.adjusted_mode.crtc_hblank_start = 3074 (tmp & 0xffff) + 1; 3075 pipe_config->hw.adjusted_mode.crtc_hblank_end = 3076 ((tmp >> 16) & 0xffff) + 1; 3077 } 3078 tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder)); 3079 pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; 3080 pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; 3081 3082 tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder)); 3083 pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; 3084 pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; 3085 3086 if (!transcoder_is_dsi(cpu_transcoder)) { 3087 tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder)); 3088 pipe_config->hw.adjusted_mode.crtc_vblank_start = 3089 (tmp & 0xffff) + 1; 3090 pipe_config->hw.adjusted_mode.crtc_vblank_end = 3091 ((tmp >> 16) & 0xffff) + 1; 3092 } 3093 tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder)); 3094 pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; 3095 pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; 3096 3097 if (intel_pipe_is_interlaced(pipe_config)) { 3098 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; 3099 pipe_config->hw.adjusted_mode.crtc_vtotal += 1; 3100 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1; 3101 } 3102 } 3103 3104 static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state) 3105 { 3106 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3107 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 3108 enum pipe master_pipe, pipe = crtc->pipe; 3109 int width; 3110 3111 if (num_pipes < 2) 3112 return; 3113 3114 master_pipe = bigjoiner_master_pipe(crtc_state); 3115 width = drm_rect_width(&crtc_state->pipe_src); 3116 3117 drm_rect_translate_to(&crtc_state->pipe_src, 3118 (pipe - master_pipe) * width, 0); 3119 } 3120 3121 static void intel_get_pipe_src_size(struct intel_crtc *crtc, 3122 struct intel_crtc_state *pipe_config) 3123 { 3124 struct drm_device *dev = crtc->base.dev; 3125 struct drm_i915_private *dev_priv = to_i915(dev); 3126 u32 tmp; 3127 3128 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe)); 3129 3130 drm_rect_init(&pipe_config->pipe_src, 0, 0, 3131 REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1, 3132 REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1); 3133 3134 intel_bigjoiner_adjust_pipe_src(pipe_config); 3135 } 3136 3137 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) 3138 { 3139 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3140 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3141 u32 pipeconf = 0; 3142 3143 /* we keep both pipes enabled on 830 */ 3144 if (IS_I830(dev_priv)) 3145 pipeconf |= PIPECONF_ENABLE; 3146 3147 if (crtc_state->double_wide) 3148 pipeconf |= PIPECONF_DOUBLE_WIDE; 3149 3150 /* only g4x and later have fancy bpc/dither controls */ 3151 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 3152 IS_CHERRYVIEW(dev_priv)) { 3153 /* Bspec claims that we can't use dithering for 30bpp pipes. */ 3154 if (crtc_state->dither && crtc_state->pipe_bpp != 30) 3155 pipeconf |= PIPECONF_DITHER_EN | 3156 PIPECONF_DITHER_TYPE_SP; 3157 3158 switch (crtc_state->pipe_bpp) { 3159 case 18: 3160 pipeconf |= PIPECONF_BPC_6; 3161 break; 3162 case 24: 3163 pipeconf |= PIPECONF_BPC_8; 3164 break; 3165 case 30: 3166 pipeconf |= PIPECONF_BPC_10; 3167 break; 3168 default: 3169 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3170 BUG(); 3171 } 3172 } 3173 3174 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 3175 if (DISPLAY_VER(dev_priv) < 4 || 3176 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3177 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; 3178 else 3179 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; 3180 } else { 3181 pipeconf |= PIPECONF_INTERLACE_PROGRESSIVE; 3182 } 3183 3184 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 3185 crtc_state->limited_color_range) 3186 pipeconf |= PIPECONF_COLOR_RANGE_SELECT; 3187 3188 pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); 3189 3190 pipeconf |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3191 3192 intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf); 3193 intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe)); 3194 } 3195 3196 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv) 3197 { 3198 if (IS_I830(dev_priv)) 3199 return false; 3200 3201 return DISPLAY_VER(dev_priv) >= 4 || 3202 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); 3203 } 3204 3205 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state) 3206 { 3207 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3208 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3209 u32 tmp; 3210 3211 if (!i9xx_has_pfit(dev_priv)) 3212 return; 3213 3214 tmp = intel_de_read(dev_priv, PFIT_CONTROL); 3215 if (!(tmp & PFIT_ENABLE)) 3216 return; 3217 3218 /* Check whether the pfit is attached to our pipe. */ 3219 if (DISPLAY_VER(dev_priv) < 4) { 3220 if (crtc->pipe != PIPE_B) 3221 return; 3222 } else { 3223 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) 3224 return; 3225 } 3226 3227 crtc_state->gmch_pfit.control = tmp; 3228 crtc_state->gmch_pfit.pgm_ratios = 3229 intel_de_read(dev_priv, PFIT_PGM_RATIOS); 3230 } 3231 3232 static void vlv_crtc_clock_get(struct intel_crtc *crtc, 3233 struct intel_crtc_state *pipe_config) 3234 { 3235 struct drm_device *dev = crtc->base.dev; 3236 struct drm_i915_private *dev_priv = to_i915(dev); 3237 enum pipe pipe = crtc->pipe; 3238 struct dpll clock; 3239 u32 mdiv; 3240 int refclk = 100000; 3241 3242 /* In case of DSI, DPLL will not be used */ 3243 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 3244 return; 3245 3246 vlv_dpio_get(dev_priv); 3247 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); 3248 vlv_dpio_put(dev_priv); 3249 3250 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; 3251 clock.m2 = mdiv & DPIO_M2DIV_MASK; 3252 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; 3253 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; 3254 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; 3255 3256 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); 3257 } 3258 3259 static void chv_crtc_clock_get(struct intel_crtc *crtc, 3260 struct intel_crtc_state *pipe_config) 3261 { 3262 struct drm_device *dev = crtc->base.dev; 3263 struct drm_i915_private *dev_priv = to_i915(dev); 3264 enum pipe pipe = crtc->pipe; 3265 enum dpio_channel port = vlv_pipe_to_channel(pipe); 3266 struct dpll clock; 3267 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; 3268 int refclk = 100000; 3269 3270 /* In case of DSI, DPLL will not be used */ 3271 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 3272 return; 3273 3274 vlv_dpio_get(dev_priv); 3275 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); 3276 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); 3277 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); 3278 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); 3279 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); 3280 vlv_dpio_put(dev_priv); 3281 3282 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; 3283 clock.m2 = (pll_dw0 & 0xff) << 22; 3284 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) 3285 clock.m2 |= pll_dw2 & 0x3fffff; 3286 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; 3287 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; 3288 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; 3289 3290 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); 3291 } 3292 3293 static enum intel_output_format 3294 bdw_get_pipemisc_output_format(struct intel_crtc *crtc) 3295 { 3296 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3297 u32 tmp; 3298 3299 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); 3300 3301 if (tmp & PIPEMISC_YUV420_ENABLE) { 3302 /* We support 4:2:0 in full blend mode only */ 3303 drm_WARN_ON(&dev_priv->drm, 3304 (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0); 3305 3306 return INTEL_OUTPUT_FORMAT_YCBCR420; 3307 } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) { 3308 return INTEL_OUTPUT_FORMAT_YCBCR444; 3309 } else { 3310 return INTEL_OUTPUT_FORMAT_RGB; 3311 } 3312 } 3313 3314 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state) 3315 { 3316 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3317 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 3318 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3319 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 3320 u32 tmp; 3321 3322 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); 3323 3324 if (tmp & DISP_PIPE_GAMMA_ENABLE) 3325 crtc_state->gamma_enable = true; 3326 3327 if (!HAS_GMCH(dev_priv) && 3328 tmp & DISP_PIPE_CSC_ENABLE) 3329 crtc_state->csc_enable = true; 3330 } 3331 3332 static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 3333 struct intel_crtc_state *pipe_config) 3334 { 3335 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3336 enum intel_display_power_domain power_domain; 3337 intel_wakeref_t wakeref; 3338 u32 tmp; 3339 bool ret; 3340 3341 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3342 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3343 if (!wakeref) 3344 return false; 3345 3346 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3347 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3348 pipe_config->shared_dpll = NULL; 3349 3350 ret = false; 3351 3352 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); 3353 if (!(tmp & PIPECONF_ENABLE)) 3354 goto out; 3355 3356 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 3357 IS_CHERRYVIEW(dev_priv)) { 3358 switch (tmp & PIPECONF_BPC_MASK) { 3359 case PIPECONF_BPC_6: 3360 pipe_config->pipe_bpp = 18; 3361 break; 3362 case PIPECONF_BPC_8: 3363 pipe_config->pipe_bpp = 24; 3364 break; 3365 case PIPECONF_BPC_10: 3366 pipe_config->pipe_bpp = 30; 3367 break; 3368 default: 3369 MISSING_CASE(tmp); 3370 break; 3371 } 3372 } 3373 3374 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 3375 (tmp & PIPECONF_COLOR_RANGE_SELECT)) 3376 pipe_config->limited_color_range = true; 3377 3378 pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_I9XX, tmp); 3379 3380 pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1; 3381 3382 if (IS_CHERRYVIEW(dev_priv)) 3383 pipe_config->cgm_mode = intel_de_read(dev_priv, 3384 CGM_PIPE_MODE(crtc->pipe)); 3385 3386 i9xx_get_pipe_color_config(pipe_config); 3387 intel_color_get_config(pipe_config); 3388 3389 if (DISPLAY_VER(dev_priv) < 4) 3390 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; 3391 3392 intel_get_transcoder_timings(crtc, pipe_config); 3393 intel_get_pipe_src_size(crtc, pipe_config); 3394 3395 i9xx_get_pfit_config(pipe_config); 3396 3397 if (DISPLAY_VER(dev_priv) >= 4) { 3398 /* No way to read it out on pipes B and C */ 3399 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) 3400 tmp = dev_priv->chv_dpll_md[crtc->pipe]; 3401 else 3402 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe)); 3403 pipe_config->pixel_multiplier = 3404 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) 3405 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; 3406 pipe_config->dpll_hw_state.dpll_md = tmp; 3407 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 3408 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 3409 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe)); 3410 pipe_config->pixel_multiplier = 3411 ((tmp & SDVO_MULTIPLIER_MASK) 3412 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; 3413 } else { 3414 /* Note that on i915G/GM the pixel multiplier is in the sdvo 3415 * port and will be fixed up in the encoder->get_config 3416 * function. */ 3417 pipe_config->pixel_multiplier = 1; 3418 } 3419 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv, 3420 DPLL(crtc->pipe)); 3421 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 3422 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv, 3423 FP0(crtc->pipe)); 3424 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv, 3425 FP1(crtc->pipe)); 3426 } else { 3427 /* Mask out read-only status bits. */ 3428 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | 3429 DPLL_PORTC_READY_MASK | 3430 DPLL_PORTB_READY_MASK); 3431 } 3432 3433 if (IS_CHERRYVIEW(dev_priv)) 3434 chv_crtc_clock_get(crtc, pipe_config); 3435 else if (IS_VALLEYVIEW(dev_priv)) 3436 vlv_crtc_clock_get(crtc, pipe_config); 3437 else 3438 i9xx_crtc_clock_get(crtc, pipe_config); 3439 3440 /* 3441 * Normally the dotclock is filled in by the encoder .get_config() 3442 * but in case the pipe is enabled w/o any ports we need a sane 3443 * default. 3444 */ 3445 pipe_config->hw.adjusted_mode.crtc_clock = 3446 pipe_config->port_clock / pipe_config->pixel_multiplier; 3447 3448 ret = true; 3449 3450 out: 3451 intel_display_power_put(dev_priv, power_domain, wakeref); 3452 3453 return ret; 3454 } 3455 3456 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) 3457 { 3458 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3459 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3460 enum pipe pipe = crtc->pipe; 3461 u32 val; 3462 3463 val = 0; 3464 3465 switch (crtc_state->pipe_bpp) { 3466 case 18: 3467 val |= PIPECONF_BPC_6; 3468 break; 3469 case 24: 3470 val |= PIPECONF_BPC_8; 3471 break; 3472 case 30: 3473 val |= PIPECONF_BPC_10; 3474 break; 3475 case 36: 3476 val |= PIPECONF_BPC_12; 3477 break; 3478 default: 3479 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3480 BUG(); 3481 } 3482 3483 if (crtc_state->dither) 3484 val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP; 3485 3486 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3487 val |= PIPECONF_INTERLACE_IF_ID_ILK; 3488 else 3489 val |= PIPECONF_INTERLACE_PF_PD_ILK; 3490 3491 /* 3492 * This would end up with an odd purple hue over 3493 * the entire display. Make sure we don't do it. 3494 */ 3495 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 3496 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 3497 3498 if (crtc_state->limited_color_range && 3499 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3500 val |= PIPECONF_COLOR_RANGE_SELECT; 3501 3502 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3503 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709; 3504 3505 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); 3506 3507 val |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3508 val |= PIPECONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay); 3509 3510 intel_de_write(dev_priv, PIPECONF(pipe), val); 3511 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 3512 } 3513 3514 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) 3515 { 3516 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3517 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3518 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3519 u32 val = 0; 3520 3521 if (IS_HASWELL(dev_priv) && crtc_state->dither) 3522 val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP; 3523 3524 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3525 val |= PIPECONF_INTERLACE_IF_ID_ILK; 3526 else 3527 val |= PIPECONF_INTERLACE_PF_PD_ILK; 3528 3529 if (IS_HASWELL(dev_priv) && 3530 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3531 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW; 3532 3533 intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val); 3534 intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder)); 3535 } 3536 3537 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) 3538 { 3539 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3540 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3541 u32 val = 0; 3542 3543 switch (crtc_state->pipe_bpp) { 3544 case 18: 3545 val |= PIPEMISC_BPC_6; 3546 break; 3547 case 24: 3548 val |= PIPEMISC_BPC_8; 3549 break; 3550 case 30: 3551 val |= PIPEMISC_BPC_10; 3552 break; 3553 case 36: 3554 /* Port output 12BPC defined for ADLP+ */ 3555 if (DISPLAY_VER(dev_priv) > 12) 3556 val |= PIPEMISC_BPC_12_ADLP; 3557 break; 3558 default: 3559 MISSING_CASE(crtc_state->pipe_bpp); 3560 break; 3561 } 3562 3563 if (crtc_state->dither) 3564 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; 3565 3566 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 3567 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 3568 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV; 3569 3570 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 3571 val |= PIPEMISC_YUV420_ENABLE | 3572 PIPEMISC_YUV420_MODE_FULL_BLEND; 3573 3574 if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state)) 3575 val |= PIPEMISC_HDR_MODE_PRECISION; 3576 3577 if (DISPLAY_VER(dev_priv) >= 12) 3578 val |= PIPEMISC_PIXEL_ROUNDING_TRUNC; 3579 3580 intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val); 3581 } 3582 3583 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) 3584 { 3585 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3586 u32 tmp; 3587 3588 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); 3589 3590 switch (tmp & PIPEMISC_BPC_MASK) { 3591 case PIPEMISC_BPC_6: 3592 return 18; 3593 case PIPEMISC_BPC_8: 3594 return 24; 3595 case PIPEMISC_BPC_10: 3596 return 30; 3597 /* 3598 * PORT OUTPUT 12 BPC defined for ADLP+. 3599 * 3600 * TODO: 3601 * For previous platforms with DSI interface, bits 5:7 3602 * are used for storing pipe_bpp irrespective of dithering. 3603 * Since the value of 12 BPC is not defined for these bits 3604 * on older platforms, need to find a workaround for 12 BPC 3605 * MIPI DSI HW readout. 3606 */ 3607 case PIPEMISC_BPC_12_ADLP: 3608 if (DISPLAY_VER(dev_priv) > 12) 3609 return 36; 3610 fallthrough; 3611 default: 3612 MISSING_CASE(tmp); 3613 return 0; 3614 } 3615 } 3616 3617 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) 3618 { 3619 /* 3620 * Account for spread spectrum to avoid 3621 * oversubscribing the link. Max center spread 3622 * is 2.5%; use 5% for safety's sake. 3623 */ 3624 u32 bps = target_clock * bpp * 21 / 20; 3625 return DIV_ROUND_UP(bps, link_bw * 8); 3626 } 3627 3628 void intel_get_m_n(struct drm_i915_private *i915, 3629 struct intel_link_m_n *m_n, 3630 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 3631 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 3632 { 3633 m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK; 3634 m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK; 3635 m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK; 3636 m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK; 3637 m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1; 3638 } 3639 3640 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, 3641 enum transcoder transcoder, 3642 struct intel_link_m_n *m_n) 3643 { 3644 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3645 enum pipe pipe = crtc->pipe; 3646 3647 if (DISPLAY_VER(dev_priv) >= 5) 3648 intel_get_m_n(dev_priv, m_n, 3649 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 3650 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 3651 else 3652 intel_get_m_n(dev_priv, m_n, 3653 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 3654 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 3655 } 3656 3657 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, 3658 enum transcoder transcoder, 3659 struct intel_link_m_n *m_n) 3660 { 3661 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3662 3663 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 3664 return; 3665 3666 intel_get_m_n(dev_priv, m_n, 3667 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 3668 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 3669 } 3670 3671 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state, 3672 u32 pos, u32 size) 3673 { 3674 drm_rect_init(&crtc_state->pch_pfit.dst, 3675 pos >> 16, pos & 0xffff, 3676 size >> 16, size & 0xffff); 3677 } 3678 3679 static void skl_get_pfit_config(struct intel_crtc_state *crtc_state) 3680 { 3681 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3682 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3683 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; 3684 int id = -1; 3685 int i; 3686 3687 /* find scaler attached to this pipe */ 3688 for (i = 0; i < crtc->num_scalers; i++) { 3689 u32 ctl, pos, size; 3690 3691 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i)); 3692 if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN) 3693 continue; 3694 3695 id = i; 3696 crtc_state->pch_pfit.enabled = true; 3697 3698 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i)); 3699 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i)); 3700 3701 ilk_get_pfit_pos_size(crtc_state, pos, size); 3702 3703 scaler_state->scalers[i].in_use = true; 3704 break; 3705 } 3706 3707 scaler_state->scaler_id = id; 3708 if (id >= 0) 3709 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); 3710 else 3711 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); 3712 } 3713 3714 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state) 3715 { 3716 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3717 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3718 u32 ctl, pos, size; 3719 3720 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe)); 3721 if ((ctl & PF_ENABLE) == 0) 3722 return; 3723 3724 crtc_state->pch_pfit.enabled = true; 3725 3726 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe)); 3727 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe)); 3728 3729 ilk_get_pfit_pos_size(crtc_state, pos, size); 3730 3731 /* 3732 * We currently do not free assignements of panel fitters on 3733 * ivb/hsw (since we don't use the higher upscaling modes which 3734 * differentiates them) so just WARN about this case for now. 3735 */ 3736 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 7 && 3737 (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe)); 3738 } 3739 3740 static bool ilk_get_pipe_config(struct intel_crtc *crtc, 3741 struct intel_crtc_state *pipe_config) 3742 { 3743 struct drm_device *dev = crtc->base.dev; 3744 struct drm_i915_private *dev_priv = to_i915(dev); 3745 enum intel_display_power_domain power_domain; 3746 intel_wakeref_t wakeref; 3747 u32 tmp; 3748 bool ret; 3749 3750 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3751 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3752 if (!wakeref) 3753 return false; 3754 3755 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3756 pipe_config->shared_dpll = NULL; 3757 3758 ret = false; 3759 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); 3760 if (!(tmp & PIPECONF_ENABLE)) 3761 goto out; 3762 3763 switch (tmp & PIPECONF_BPC_MASK) { 3764 case PIPECONF_BPC_6: 3765 pipe_config->pipe_bpp = 18; 3766 break; 3767 case PIPECONF_BPC_8: 3768 pipe_config->pipe_bpp = 24; 3769 break; 3770 case PIPECONF_BPC_10: 3771 pipe_config->pipe_bpp = 30; 3772 break; 3773 case PIPECONF_BPC_12: 3774 pipe_config->pipe_bpp = 36; 3775 break; 3776 default: 3777 break; 3778 } 3779 3780 if (tmp & PIPECONF_COLOR_RANGE_SELECT) 3781 pipe_config->limited_color_range = true; 3782 3783 switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) { 3784 case PIPECONF_OUTPUT_COLORSPACE_YUV601: 3785 case PIPECONF_OUTPUT_COLORSPACE_YUV709: 3786 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3787 break; 3788 default: 3789 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3790 break; 3791 } 3792 3793 pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_ILK, tmp); 3794 3795 pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1; 3796 3797 pipe_config->msa_timing_delay = REG_FIELD_GET(PIPECONF_MSA_TIMING_DELAY_MASK, tmp); 3798 3799 pipe_config->csc_mode = intel_de_read(dev_priv, 3800 PIPE_CSC_MODE(crtc->pipe)); 3801 3802 i9xx_get_pipe_color_config(pipe_config); 3803 intel_color_get_config(pipe_config); 3804 3805 pipe_config->pixel_multiplier = 1; 3806 3807 ilk_pch_get_config(pipe_config); 3808 3809 intel_get_transcoder_timings(crtc, pipe_config); 3810 intel_get_pipe_src_size(crtc, pipe_config); 3811 3812 ilk_get_pfit_config(pipe_config); 3813 3814 ret = true; 3815 3816 out: 3817 intel_display_power_put(dev_priv, power_domain, wakeref); 3818 3819 return ret; 3820 } 3821 3822 static u8 bigjoiner_pipes(struct drm_i915_private *i915) 3823 { 3824 if (DISPLAY_VER(i915) >= 12) 3825 return BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D); 3826 else if (DISPLAY_VER(i915) >= 11) 3827 return BIT(PIPE_B) | BIT(PIPE_C); 3828 else 3829 return 0; 3830 } 3831 3832 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv, 3833 enum transcoder cpu_transcoder) 3834 { 3835 enum intel_display_power_domain power_domain; 3836 intel_wakeref_t wakeref; 3837 u32 tmp = 0; 3838 3839 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3840 3841 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3842 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3843 3844 return tmp & TRANS_DDI_FUNC_ENABLE; 3845 } 3846 3847 static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv, 3848 u8 *master_pipes, u8 *slave_pipes) 3849 { 3850 struct intel_crtc *crtc; 3851 3852 *master_pipes = 0; 3853 *slave_pipes = 0; 3854 3855 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, 3856 bigjoiner_pipes(dev_priv)) { 3857 enum intel_display_power_domain power_domain; 3858 enum pipe pipe = crtc->pipe; 3859 intel_wakeref_t wakeref; 3860 3861 power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe); 3862 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3863 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3864 3865 if (!(tmp & BIG_JOINER_ENABLE)) 3866 continue; 3867 3868 if (tmp & MASTER_BIG_JOINER_ENABLE) 3869 *master_pipes |= BIT(pipe); 3870 else 3871 *slave_pipes |= BIT(pipe); 3872 } 3873 3874 if (DISPLAY_VER(dev_priv) < 13) 3875 continue; 3876 3877 power_domain = POWER_DOMAIN_PIPE(pipe); 3878 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3879 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3880 3881 if (tmp & UNCOMPRESSED_JOINER_MASTER) 3882 *master_pipes |= BIT(pipe); 3883 if (tmp & UNCOMPRESSED_JOINER_SLAVE) 3884 *slave_pipes |= BIT(pipe); 3885 } 3886 } 3887 3888 /* Bigjoiner pipes should always be consecutive master and slave */ 3889 drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1, 3890 "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n", 3891 *master_pipes, *slave_pipes); 3892 } 3893 3894 static enum pipe get_bigjoiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3895 { 3896 if ((slave_pipes & BIT(pipe)) == 0) 3897 return pipe; 3898 3899 /* ignore everything above our pipe */ 3900 master_pipes &= ~GENMASK(7, pipe); 3901 3902 /* highest remaining bit should be our master pipe */ 3903 return fls(master_pipes) - 1; 3904 } 3905 3906 static u8 get_bigjoiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3907 { 3908 enum pipe master_pipe, next_master_pipe; 3909 3910 master_pipe = get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes); 3911 3912 if ((master_pipes & BIT(master_pipe)) == 0) 3913 return 0; 3914 3915 /* ignore our master pipe and everything below it */ 3916 master_pipes &= ~GENMASK(master_pipe, 0); 3917 /* make sure a high bit is set for the ffs() */ 3918 master_pipes |= BIT(7); 3919 /* lowest remaining bit should be the next master pipe */ 3920 next_master_pipe = ffs(master_pipes) - 1; 3921 3922 return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe); 3923 } 3924 3925 static u8 hsw_panel_transcoders(struct drm_i915_private *i915) 3926 { 3927 u8 panel_transcoder_mask = BIT(TRANSCODER_EDP); 3928 3929 if (DISPLAY_VER(i915) >= 11) 3930 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); 3931 3932 return panel_transcoder_mask; 3933 } 3934 3935 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) 3936 { 3937 struct drm_device *dev = crtc->base.dev; 3938 struct drm_i915_private *dev_priv = to_i915(dev); 3939 u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv); 3940 enum transcoder cpu_transcoder; 3941 u8 master_pipes, slave_pipes; 3942 u8 enabled_transcoders = 0; 3943 3944 /* 3945 * XXX: Do intel_display_power_get_if_enabled before reading this (for 3946 * consistency and less surprising code; it's in always on power). 3947 */ 3948 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, 3949 panel_transcoder_mask) { 3950 enum intel_display_power_domain power_domain; 3951 intel_wakeref_t wakeref; 3952 enum pipe trans_pipe; 3953 u32 tmp = 0; 3954 3955 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3956 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3957 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3958 3959 if (!(tmp & TRANS_DDI_FUNC_ENABLE)) 3960 continue; 3961 3962 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 3963 default: 3964 drm_WARN(dev, 1, 3965 "unknown pipe linked to transcoder %s\n", 3966 transcoder_name(cpu_transcoder)); 3967 fallthrough; 3968 case TRANS_DDI_EDP_INPUT_A_ONOFF: 3969 case TRANS_DDI_EDP_INPUT_A_ON: 3970 trans_pipe = PIPE_A; 3971 break; 3972 case TRANS_DDI_EDP_INPUT_B_ONOFF: 3973 trans_pipe = PIPE_B; 3974 break; 3975 case TRANS_DDI_EDP_INPUT_C_ONOFF: 3976 trans_pipe = PIPE_C; 3977 break; 3978 case TRANS_DDI_EDP_INPUT_D_ONOFF: 3979 trans_pipe = PIPE_D; 3980 break; 3981 } 3982 3983 if (trans_pipe == crtc->pipe) 3984 enabled_transcoders |= BIT(cpu_transcoder); 3985 } 3986 3987 /* single pipe or bigjoiner master */ 3988 cpu_transcoder = (enum transcoder) crtc->pipe; 3989 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 3990 enabled_transcoders |= BIT(cpu_transcoder); 3991 3992 /* bigjoiner slave -> consider the master pipe's transcoder as well */ 3993 enabled_bigjoiner_pipes(dev_priv, &master_pipes, &slave_pipes); 3994 if (slave_pipes & BIT(crtc->pipe)) { 3995 cpu_transcoder = (enum transcoder) 3996 get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes); 3997 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 3998 enabled_transcoders |= BIT(cpu_transcoder); 3999 } 4000 4001 return enabled_transcoders; 4002 } 4003 4004 static bool has_edp_transcoders(u8 enabled_transcoders) 4005 { 4006 return enabled_transcoders & BIT(TRANSCODER_EDP); 4007 } 4008 4009 static bool has_dsi_transcoders(u8 enabled_transcoders) 4010 { 4011 return enabled_transcoders & (BIT(TRANSCODER_DSI_0) | 4012 BIT(TRANSCODER_DSI_1)); 4013 } 4014 4015 static bool has_pipe_transcoders(u8 enabled_transcoders) 4016 { 4017 return enabled_transcoders & ~(BIT(TRANSCODER_EDP) | 4018 BIT(TRANSCODER_DSI_0) | 4019 BIT(TRANSCODER_DSI_1)); 4020 } 4021 4022 static void assert_enabled_transcoders(struct drm_i915_private *i915, 4023 u8 enabled_transcoders) 4024 { 4025 /* Only one type of transcoder please */ 4026 drm_WARN_ON(&i915->drm, 4027 has_edp_transcoders(enabled_transcoders) + 4028 has_dsi_transcoders(enabled_transcoders) + 4029 has_pipe_transcoders(enabled_transcoders) > 1); 4030 4031 /* Only DSI transcoders can be ganged */ 4032 drm_WARN_ON(&i915->drm, 4033 !has_dsi_transcoders(enabled_transcoders) && 4034 !is_power_of_2(enabled_transcoders)); 4035 } 4036 4037 static bool hsw_get_transcoder_state(struct intel_crtc *crtc, 4038 struct intel_crtc_state *pipe_config, 4039 struct intel_display_power_domain_set *power_domain_set) 4040 { 4041 struct drm_device *dev = crtc->base.dev; 4042 struct drm_i915_private *dev_priv = to_i915(dev); 4043 unsigned long enabled_transcoders; 4044 u32 tmp; 4045 4046 enabled_transcoders = hsw_enabled_transcoders(crtc); 4047 if (!enabled_transcoders) 4048 return false; 4049 4050 assert_enabled_transcoders(dev_priv, enabled_transcoders); 4051 4052 /* 4053 * With the exception of DSI we should only ever have 4054 * a single enabled transcoder. With DSI let's just 4055 * pick the first one. 4056 */ 4057 pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1; 4058 4059 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 4060 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) 4061 return false; 4062 4063 if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) { 4064 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); 4065 4066 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF) 4067 pipe_config->pch_pfit.force_thru = true; 4068 } 4069 4070 tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder)); 4071 4072 return tmp & PIPECONF_ENABLE; 4073 } 4074 4075 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, 4076 struct intel_crtc_state *pipe_config, 4077 struct intel_display_power_domain_set *power_domain_set) 4078 { 4079 struct drm_device *dev = crtc->base.dev; 4080 struct drm_i915_private *dev_priv = to_i915(dev); 4081 enum transcoder cpu_transcoder; 4082 enum port port; 4083 u32 tmp; 4084 4085 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { 4086 if (port == PORT_A) 4087 cpu_transcoder = TRANSCODER_DSI_A; 4088 else 4089 cpu_transcoder = TRANSCODER_DSI_C; 4090 4091 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 4092 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) 4093 continue; 4094 4095 /* 4096 * The PLL needs to be enabled with a valid divider 4097 * configuration, otherwise accessing DSI registers will hang 4098 * the machine. See BSpec North Display Engine 4099 * registers/MIPI[BXT]. We can break out here early, since we 4100 * need the same DSI PLL to be enabled for both DSI ports. 4101 */ 4102 if (!bxt_dsi_pll_is_enabled(dev_priv)) 4103 break; 4104 4105 /* XXX: this works for video mode only */ 4106 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); 4107 if (!(tmp & DPI_ENABLE)) 4108 continue; 4109 4110 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 4111 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) 4112 continue; 4113 4114 pipe_config->cpu_transcoder = cpu_transcoder; 4115 break; 4116 } 4117 4118 return transcoder_is_dsi(pipe_config->cpu_transcoder); 4119 } 4120 4121 static void intel_bigjoiner_get_config(struct intel_crtc_state *crtc_state) 4122 { 4123 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4124 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4125 u8 master_pipes, slave_pipes; 4126 enum pipe pipe = crtc->pipe; 4127 4128 enabled_bigjoiner_pipes(i915, &master_pipes, &slave_pipes); 4129 4130 if (((master_pipes | slave_pipes) & BIT(pipe)) == 0) 4131 return; 4132 4133 crtc_state->bigjoiner_pipes = 4134 BIT(get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes)) | 4135 get_bigjoiner_slave_pipes(pipe, master_pipes, slave_pipes); 4136 } 4137 4138 static bool hsw_get_pipe_config(struct intel_crtc *crtc, 4139 struct intel_crtc_state *pipe_config) 4140 { 4141 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4142 struct intel_display_power_domain_set power_domain_set = { }; 4143 bool active; 4144 u32 tmp; 4145 4146 if (!intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set, 4147 POWER_DOMAIN_PIPE(crtc->pipe))) 4148 return false; 4149 4150 pipe_config->shared_dpll = NULL; 4151 4152 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_set); 4153 4154 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 4155 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_set)) { 4156 drm_WARN_ON(&dev_priv->drm, active); 4157 active = true; 4158 } 4159 4160 if (!active) 4161 goto out; 4162 4163 intel_dsc_get_config(pipe_config); 4164 intel_bigjoiner_get_config(pipe_config); 4165 4166 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || 4167 DISPLAY_VER(dev_priv) >= 11) 4168 intel_get_transcoder_timings(crtc, pipe_config); 4169 4170 if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder)) 4171 intel_vrr_get_config(crtc, pipe_config); 4172 4173 intel_get_pipe_src_size(crtc, pipe_config); 4174 4175 if (IS_HASWELL(dev_priv)) { 4176 u32 tmp = intel_de_read(dev_priv, 4177 PIPECONF(pipe_config->cpu_transcoder)); 4178 4179 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW) 4180 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 4181 else 4182 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 4183 } else { 4184 pipe_config->output_format = 4185 bdw_get_pipemisc_output_format(crtc); 4186 } 4187 4188 pipe_config->gamma_mode = intel_de_read(dev_priv, 4189 GAMMA_MODE(crtc->pipe)); 4190 4191 pipe_config->csc_mode = intel_de_read(dev_priv, 4192 PIPE_CSC_MODE(crtc->pipe)); 4193 4194 if (DISPLAY_VER(dev_priv) >= 9) { 4195 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe)); 4196 4197 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE) 4198 pipe_config->gamma_enable = true; 4199 4200 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE) 4201 pipe_config->csc_enable = true; 4202 } else { 4203 i9xx_get_pipe_color_config(pipe_config); 4204 } 4205 4206 intel_color_get_config(pipe_config); 4207 4208 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe)); 4209 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); 4210 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 4211 pipe_config->ips_linetime = 4212 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); 4213 4214 if (intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set, 4215 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) { 4216 if (DISPLAY_VER(dev_priv) >= 9) 4217 skl_get_pfit_config(pipe_config); 4218 else 4219 ilk_get_pfit_config(pipe_config); 4220 } 4221 4222 hsw_ips_get_config(pipe_config); 4223 4224 if (pipe_config->cpu_transcoder != TRANSCODER_EDP && 4225 !transcoder_is_dsi(pipe_config->cpu_transcoder)) { 4226 pipe_config->pixel_multiplier = 4227 intel_de_read(dev_priv, 4228 PIPE_MULT(pipe_config->cpu_transcoder)) + 1; 4229 } else { 4230 pipe_config->pixel_multiplier = 1; 4231 } 4232 4233 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { 4234 tmp = intel_de_read(dev_priv, CHICKEN_TRANS(pipe_config->cpu_transcoder)); 4235 4236 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1; 4237 } else { 4238 /* no idea if this is correct */ 4239 pipe_config->framestart_delay = 1; 4240 } 4241 4242 out: 4243 intel_display_power_put_all_in_set(dev_priv, &power_domain_set); 4244 4245 return active; 4246 } 4247 4248 static bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state) 4249 { 4250 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4251 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4252 4253 if (!i915->display->get_pipe_config(crtc, crtc_state)) 4254 return false; 4255 4256 crtc_state->hw.active = true; 4257 4258 intel_crtc_readout_derived_state(crtc_state); 4259 4260 return true; 4261 } 4262 4263 /* VESA 640x480x72Hz mode to set on the pipe */ 4264 static const struct drm_display_mode load_detect_mode = { 4265 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, 4266 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 4267 }; 4268 4269 static int intel_modeset_disable_planes(struct drm_atomic_state *state, 4270 struct drm_crtc *crtc) 4271 { 4272 struct drm_plane *plane; 4273 struct drm_plane_state *plane_state; 4274 int ret, i; 4275 4276 ret = drm_atomic_add_affected_planes(state, crtc); 4277 if (ret) 4278 return ret; 4279 4280 for_each_new_plane_in_state(state, plane, plane_state, i) { 4281 if (plane_state->crtc != crtc) 4282 continue; 4283 4284 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL); 4285 if (ret) 4286 return ret; 4287 4288 drm_atomic_set_fb_for_plane(plane_state, NULL); 4289 } 4290 4291 return 0; 4292 } 4293 4294 int intel_get_load_detect_pipe(struct drm_connector *connector, 4295 struct intel_load_detect_pipe *old, 4296 struct drm_modeset_acquire_ctx *ctx) 4297 { 4298 struct intel_encoder *encoder = 4299 intel_attached_encoder(to_intel_connector(connector)); 4300 struct intel_crtc *possible_crtc; 4301 struct intel_crtc *crtc = NULL; 4302 struct drm_device *dev = encoder->base.dev; 4303 struct drm_i915_private *dev_priv = to_i915(dev); 4304 struct drm_mode_config *config = &dev->mode_config; 4305 struct drm_atomic_state *state = NULL, *restore_state = NULL; 4306 struct drm_connector_state *connector_state; 4307 struct intel_crtc_state *crtc_state; 4308 int ret; 4309 4310 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 4311 connector->base.id, connector->name, 4312 encoder->base.base.id, encoder->base.name); 4313 4314 old->restore_state = NULL; 4315 4316 drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex)); 4317 4318 /* 4319 * Algorithm gets a little messy: 4320 * 4321 * - if the connector already has an assigned crtc, use it (but make 4322 * sure it's on first) 4323 * 4324 * - try to find the first unused crtc that can drive this connector, 4325 * and use that if we find one 4326 */ 4327 4328 /* See if we already have a CRTC for this connector */ 4329 if (connector->state->crtc) { 4330 crtc = to_intel_crtc(connector->state->crtc); 4331 4332 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4333 if (ret) 4334 goto fail; 4335 4336 /* Make sure the crtc and connector are running */ 4337 goto found; 4338 } 4339 4340 /* Find an unused one (if possible) */ 4341 for_each_intel_crtc(dev, possible_crtc) { 4342 if (!(encoder->base.possible_crtcs & 4343 drm_crtc_mask(&possible_crtc->base))) 4344 continue; 4345 4346 ret = drm_modeset_lock(&possible_crtc->base.mutex, ctx); 4347 if (ret) 4348 goto fail; 4349 4350 if (possible_crtc->base.state->enable) { 4351 drm_modeset_unlock(&possible_crtc->base.mutex); 4352 continue; 4353 } 4354 4355 crtc = possible_crtc; 4356 break; 4357 } 4358 4359 /* 4360 * If we didn't find an unused CRTC, don't use any. 4361 */ 4362 if (!crtc) { 4363 drm_dbg_kms(&dev_priv->drm, 4364 "no pipe available for load-detect\n"); 4365 ret = -ENODEV; 4366 goto fail; 4367 } 4368 4369 found: 4370 state = drm_atomic_state_alloc(dev); 4371 restore_state = drm_atomic_state_alloc(dev); 4372 if (!state || !restore_state) { 4373 ret = -ENOMEM; 4374 goto fail; 4375 } 4376 4377 state->acquire_ctx = ctx; 4378 restore_state->acquire_ctx = ctx; 4379 4380 connector_state = drm_atomic_get_connector_state(state, connector); 4381 if (IS_ERR(connector_state)) { 4382 ret = PTR_ERR(connector_state); 4383 goto fail; 4384 } 4385 4386 ret = drm_atomic_set_crtc_for_connector(connector_state, &crtc->base); 4387 if (ret) 4388 goto fail; 4389 4390 crtc_state = intel_atomic_get_crtc_state(state, crtc); 4391 if (IS_ERR(crtc_state)) { 4392 ret = PTR_ERR(crtc_state); 4393 goto fail; 4394 } 4395 4396 crtc_state->uapi.active = true; 4397 4398 ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi, 4399 &load_detect_mode); 4400 if (ret) 4401 goto fail; 4402 4403 ret = intel_modeset_disable_planes(state, &crtc->base); 4404 if (ret) 4405 goto fail; 4406 4407 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); 4408 if (!ret) 4409 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, &crtc->base)); 4410 if (!ret) 4411 ret = drm_atomic_add_affected_planes(restore_state, &crtc->base); 4412 if (ret) { 4413 drm_dbg_kms(&dev_priv->drm, 4414 "Failed to create a copy of old state to restore: %i\n", 4415 ret); 4416 goto fail; 4417 } 4418 4419 ret = drm_atomic_commit(state); 4420 if (ret) { 4421 drm_dbg_kms(&dev_priv->drm, 4422 "failed to set mode on load-detect pipe\n"); 4423 goto fail; 4424 } 4425 4426 old->restore_state = restore_state; 4427 drm_atomic_state_put(state); 4428 4429 /* let the connector get through one full cycle before testing */ 4430 intel_crtc_wait_for_next_vblank(crtc); 4431 4432 return true; 4433 4434 fail: 4435 if (state) { 4436 drm_atomic_state_put(state); 4437 state = NULL; 4438 } 4439 if (restore_state) { 4440 drm_atomic_state_put(restore_state); 4441 restore_state = NULL; 4442 } 4443 4444 if (ret == -EDEADLK) 4445 return ret; 4446 4447 return false; 4448 } 4449 4450 void intel_release_load_detect_pipe(struct drm_connector *connector, 4451 struct intel_load_detect_pipe *old, 4452 struct drm_modeset_acquire_ctx *ctx) 4453 { 4454 struct intel_encoder *intel_encoder = 4455 intel_attached_encoder(to_intel_connector(connector)); 4456 struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev); 4457 struct drm_encoder *encoder = &intel_encoder->base; 4458 struct drm_atomic_state *state = old->restore_state; 4459 int ret; 4460 4461 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 4462 connector->base.id, connector->name, 4463 encoder->base.id, encoder->name); 4464 4465 if (!state) 4466 return; 4467 4468 ret = drm_atomic_helper_commit_duplicated_state(state, ctx); 4469 if (ret) 4470 drm_dbg_kms(&i915->drm, 4471 "Couldn't release load detect pipe: %i\n", ret); 4472 drm_atomic_state_put(state); 4473 } 4474 4475 static int i9xx_pll_refclk(struct drm_device *dev, 4476 const struct intel_crtc_state *pipe_config) 4477 { 4478 struct drm_i915_private *dev_priv = to_i915(dev); 4479 u32 dpll = pipe_config->dpll_hw_state.dpll; 4480 4481 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) 4482 return dev_priv->vbt.lvds_ssc_freq; 4483 else if (HAS_PCH_SPLIT(dev_priv)) 4484 return 120000; 4485 else if (DISPLAY_VER(dev_priv) != 2) 4486 return 96000; 4487 else 4488 return 48000; 4489 } 4490 4491 /* Returns the clock of the currently programmed mode of the given pipe. */ 4492 void i9xx_crtc_clock_get(struct intel_crtc *crtc, 4493 struct intel_crtc_state *pipe_config) 4494 { 4495 struct drm_device *dev = crtc->base.dev; 4496 struct drm_i915_private *dev_priv = to_i915(dev); 4497 u32 dpll = pipe_config->dpll_hw_state.dpll; 4498 u32 fp; 4499 struct dpll clock; 4500 int port_clock; 4501 int refclk = i9xx_pll_refclk(dev, pipe_config); 4502 4503 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 4504 fp = pipe_config->dpll_hw_state.fp0; 4505 else 4506 fp = pipe_config->dpll_hw_state.fp1; 4507 4508 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 4509 if (IS_PINEVIEW(dev_priv)) { 4510 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; 4511 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; 4512 } else { 4513 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 4514 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 4515 } 4516 4517 if (DISPLAY_VER(dev_priv) != 2) { 4518 if (IS_PINEVIEW(dev_priv)) 4519 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> 4520 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); 4521 else 4522 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> 4523 DPLL_FPA01_P1_POST_DIV_SHIFT); 4524 4525 switch (dpll & DPLL_MODE_MASK) { 4526 case DPLLB_MODE_DAC_SERIAL: 4527 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 4528 5 : 10; 4529 break; 4530 case DPLLB_MODE_LVDS: 4531 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 4532 7 : 14; 4533 break; 4534 default: 4535 drm_dbg_kms(&dev_priv->drm, 4536 "Unknown DPLL mode %08x in programmed " 4537 "mode\n", (int)(dpll & DPLL_MODE_MASK)); 4538 return; 4539 } 4540 4541 if (IS_PINEVIEW(dev_priv)) 4542 port_clock = pnv_calc_dpll_params(refclk, &clock); 4543 else 4544 port_clock = i9xx_calc_dpll_params(refclk, &clock); 4545 } else { 4546 enum pipe lvds_pipe; 4547 4548 if (IS_I85X(dev_priv) && 4549 intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) && 4550 lvds_pipe == crtc->pipe) { 4551 u32 lvds = intel_de_read(dev_priv, LVDS); 4552 4553 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 4554 DPLL_FPA01_P1_POST_DIV_SHIFT); 4555 4556 if (lvds & LVDS_CLKB_POWER_UP) 4557 clock.p2 = 7; 4558 else 4559 clock.p2 = 14; 4560 } else { 4561 if (dpll & PLL_P1_DIVIDE_BY_TWO) 4562 clock.p1 = 2; 4563 else { 4564 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 4565 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 4566 } 4567 if (dpll & PLL_P2_DIVIDE_BY_4) 4568 clock.p2 = 4; 4569 else 4570 clock.p2 = 2; 4571 } 4572 4573 port_clock = i9xx_calc_dpll_params(refclk, &clock); 4574 } 4575 4576 /* 4577 * This value includes pixel_multiplier. We will use 4578 * port_clock to compute adjusted_mode.crtc_clock in the 4579 * encoder's get_config() function. 4580 */ 4581 pipe_config->port_clock = port_clock; 4582 } 4583 4584 int intel_dotclock_calculate(int link_freq, 4585 const struct intel_link_m_n *m_n) 4586 { 4587 /* 4588 * The calculation for the data clock is: 4589 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp 4590 * But we want to avoid losing precison if possible, so: 4591 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) 4592 * 4593 * and the link clock is simpler: 4594 * link_clock = (m * link_clock) / n 4595 */ 4596 4597 if (!m_n->link_n) 4598 return 0; 4599 4600 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n); 4601 } 4602 4603 /* Returns the currently programmed mode of the given encoder. */ 4604 struct drm_display_mode * 4605 intel_encoder_current_mode(struct intel_encoder *encoder) 4606 { 4607 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4608 struct intel_crtc_state *crtc_state; 4609 struct drm_display_mode *mode; 4610 struct intel_crtc *crtc; 4611 enum pipe pipe; 4612 4613 if (!encoder->get_hw_state(encoder, &pipe)) 4614 return NULL; 4615 4616 crtc = intel_crtc_for_pipe(dev_priv, pipe); 4617 4618 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 4619 if (!mode) 4620 return NULL; 4621 4622 crtc_state = intel_crtc_state_alloc(crtc); 4623 if (!crtc_state) { 4624 kfree(mode); 4625 return NULL; 4626 } 4627 4628 if (!intel_crtc_get_pipe_config(crtc_state)) { 4629 kfree(crtc_state); 4630 kfree(mode); 4631 return NULL; 4632 } 4633 4634 intel_encoder_get_config(encoder, crtc_state); 4635 4636 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode); 4637 4638 kfree(crtc_state); 4639 4640 return mode; 4641 } 4642 4643 static bool encoders_cloneable(const struct intel_encoder *a, 4644 const struct intel_encoder *b) 4645 { 4646 /* masks could be asymmetric, so check both ways */ 4647 return a == b || (a->cloneable & (1 << b->type) && 4648 b->cloneable & (1 << a->type)); 4649 } 4650 4651 static bool check_single_encoder_cloning(struct intel_atomic_state *state, 4652 struct intel_crtc *crtc, 4653 struct intel_encoder *encoder) 4654 { 4655 struct intel_encoder *source_encoder; 4656 struct drm_connector *connector; 4657 struct drm_connector_state *connector_state; 4658 int i; 4659 4660 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4661 if (connector_state->crtc != &crtc->base) 4662 continue; 4663 4664 source_encoder = 4665 to_intel_encoder(connector_state->best_encoder); 4666 if (!encoders_cloneable(encoder, source_encoder)) 4667 return false; 4668 } 4669 4670 return true; 4671 } 4672 4673 static int icl_add_linked_planes(struct intel_atomic_state *state) 4674 { 4675 struct intel_plane *plane, *linked; 4676 struct intel_plane_state *plane_state, *linked_plane_state; 4677 int i; 4678 4679 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4680 linked = plane_state->planar_linked_plane; 4681 4682 if (!linked) 4683 continue; 4684 4685 linked_plane_state = intel_atomic_get_plane_state(state, linked); 4686 if (IS_ERR(linked_plane_state)) 4687 return PTR_ERR(linked_plane_state); 4688 4689 drm_WARN_ON(state->base.dev, 4690 linked_plane_state->planar_linked_plane != plane); 4691 drm_WARN_ON(state->base.dev, 4692 linked_plane_state->planar_slave == plane_state->planar_slave); 4693 } 4694 4695 return 0; 4696 } 4697 4698 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state) 4699 { 4700 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4701 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4702 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 4703 struct intel_plane *plane, *linked; 4704 struct intel_plane_state *plane_state; 4705 int i; 4706 4707 if (DISPLAY_VER(dev_priv) < 11) 4708 return 0; 4709 4710 /* 4711 * Destroy all old plane links and make the slave plane invisible 4712 * in the crtc_state->active_planes mask. 4713 */ 4714 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4715 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane) 4716 continue; 4717 4718 plane_state->planar_linked_plane = NULL; 4719 if (plane_state->planar_slave && !plane_state->uapi.visible) { 4720 crtc_state->enabled_planes &= ~BIT(plane->id); 4721 crtc_state->active_planes &= ~BIT(plane->id); 4722 crtc_state->update_planes |= BIT(plane->id); 4723 crtc_state->data_rate[plane->id] = 0; 4724 crtc_state->rel_data_rate[plane->id] = 0; 4725 } 4726 4727 plane_state->planar_slave = false; 4728 } 4729 4730 if (!crtc_state->nv12_planes) 4731 return 0; 4732 4733 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4734 struct intel_plane_state *linked_state = NULL; 4735 4736 if (plane->pipe != crtc->pipe || 4737 !(crtc_state->nv12_planes & BIT(plane->id))) 4738 continue; 4739 4740 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) { 4741 if (!icl_is_nv12_y_plane(dev_priv, linked->id)) 4742 continue; 4743 4744 if (crtc_state->active_planes & BIT(linked->id)) 4745 continue; 4746 4747 linked_state = intel_atomic_get_plane_state(state, linked); 4748 if (IS_ERR(linked_state)) 4749 return PTR_ERR(linked_state); 4750 4751 break; 4752 } 4753 4754 if (!linked_state) { 4755 drm_dbg_kms(&dev_priv->drm, 4756 "Need %d free Y planes for planar YUV\n", 4757 hweight8(crtc_state->nv12_planes)); 4758 4759 return -EINVAL; 4760 } 4761 4762 plane_state->planar_linked_plane = linked; 4763 4764 linked_state->planar_slave = true; 4765 linked_state->planar_linked_plane = plane; 4766 crtc_state->enabled_planes |= BIT(linked->id); 4767 crtc_state->active_planes |= BIT(linked->id); 4768 crtc_state->update_planes |= BIT(linked->id); 4769 crtc_state->data_rate[linked->id] = 4770 crtc_state->data_rate_y[plane->id]; 4771 crtc_state->rel_data_rate[linked->id] = 4772 crtc_state->rel_data_rate_y[plane->id]; 4773 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n", 4774 linked->base.name, plane->base.name); 4775 4776 /* Copy parameters to slave plane */ 4777 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE; 4778 linked_state->color_ctl = plane_state->color_ctl; 4779 linked_state->view = plane_state->view; 4780 linked_state->decrypt = plane_state->decrypt; 4781 4782 intel_plane_copy_hw_state(linked_state, plane_state); 4783 linked_state->uapi.src = plane_state->uapi.src; 4784 linked_state->uapi.dst = plane_state->uapi.dst; 4785 4786 if (icl_is_hdr_plane(dev_priv, plane->id)) { 4787 if (linked->id == PLANE_SPRITE5) 4788 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL; 4789 else if (linked->id == PLANE_SPRITE4) 4790 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL; 4791 else if (linked->id == PLANE_SPRITE3) 4792 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL; 4793 else if (linked->id == PLANE_SPRITE2) 4794 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL; 4795 else 4796 MISSING_CASE(linked->id); 4797 } 4798 } 4799 4800 return 0; 4801 } 4802 4803 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state) 4804 { 4805 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 4806 struct intel_atomic_state *state = 4807 to_intel_atomic_state(new_crtc_state->uapi.state); 4808 const struct intel_crtc_state *old_crtc_state = 4809 intel_atomic_get_old_crtc_state(state, crtc); 4810 4811 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes; 4812 } 4813 4814 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) 4815 { 4816 const struct drm_display_mode *pipe_mode = 4817 &crtc_state->hw.pipe_mode; 4818 int linetime_wm; 4819 4820 if (!crtc_state->hw.enable) 4821 return 0; 4822 4823 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4824 pipe_mode->crtc_clock); 4825 4826 return min(linetime_wm, 0x1ff); 4827 } 4828 4829 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, 4830 const struct intel_cdclk_state *cdclk_state) 4831 { 4832 const struct drm_display_mode *pipe_mode = 4833 &crtc_state->hw.pipe_mode; 4834 int linetime_wm; 4835 4836 if (!crtc_state->hw.enable) 4837 return 0; 4838 4839 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4840 cdclk_state->logical.cdclk); 4841 4842 return min(linetime_wm, 0x1ff); 4843 } 4844 4845 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) 4846 { 4847 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4848 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4849 const struct drm_display_mode *pipe_mode = 4850 &crtc_state->hw.pipe_mode; 4851 int linetime_wm; 4852 4853 if (!crtc_state->hw.enable) 4854 return 0; 4855 4856 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8, 4857 crtc_state->pixel_rate); 4858 4859 /* Display WA #1135: BXT:ALL GLK:ALL */ 4860 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 4861 dev_priv->ipc_enabled) 4862 linetime_wm /= 2; 4863 4864 return min(linetime_wm, 0x1ff); 4865 } 4866 4867 static int hsw_compute_linetime_wm(struct intel_atomic_state *state, 4868 struct intel_crtc *crtc) 4869 { 4870 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4871 struct intel_crtc_state *crtc_state = 4872 intel_atomic_get_new_crtc_state(state, crtc); 4873 const struct intel_cdclk_state *cdclk_state; 4874 4875 if (DISPLAY_VER(dev_priv) >= 9) 4876 crtc_state->linetime = skl_linetime_wm(crtc_state); 4877 else 4878 crtc_state->linetime = hsw_linetime_wm(crtc_state); 4879 4880 if (!hsw_crtc_supports_ips(crtc)) 4881 return 0; 4882 4883 cdclk_state = intel_atomic_get_cdclk_state(state); 4884 if (IS_ERR(cdclk_state)) 4885 return PTR_ERR(cdclk_state); 4886 4887 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state, 4888 cdclk_state); 4889 4890 return 0; 4891 } 4892 4893 static int intel_crtc_atomic_check(struct intel_atomic_state *state, 4894 struct intel_crtc *crtc) 4895 { 4896 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4897 struct intel_crtc_state *crtc_state = 4898 intel_atomic_get_new_crtc_state(state, crtc); 4899 bool mode_changed = intel_crtc_needs_modeset(crtc_state); 4900 int ret; 4901 4902 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) && 4903 mode_changed && !crtc_state->hw.active) 4904 crtc_state->update_wm_post = true; 4905 4906 if (mode_changed) { 4907 ret = intel_dpll_crtc_compute_clock(state, crtc); 4908 if (ret) 4909 return ret; 4910 4911 ret = intel_dpll_crtc_get_shared_dpll(state, crtc); 4912 if (ret) 4913 return ret; 4914 } 4915 4916 /* 4917 * May need to update pipe gamma enable bits 4918 * when C8 planes are getting enabled/disabled. 4919 */ 4920 if (c8_planes_changed(crtc_state)) 4921 crtc_state->uapi.color_mgmt_changed = true; 4922 4923 if (mode_changed || crtc_state->update_pipe || 4924 crtc_state->uapi.color_mgmt_changed) { 4925 ret = intel_color_check(crtc_state); 4926 if (ret) 4927 return ret; 4928 } 4929 4930 ret = intel_compute_pipe_wm(state, crtc); 4931 if (ret) { 4932 drm_dbg_kms(&dev_priv->drm, 4933 "Target pipe watermarks are invalid\n"); 4934 return ret; 4935 } 4936 4937 /* 4938 * Calculate 'intermediate' watermarks that satisfy both the 4939 * old state and the new state. We can program these 4940 * immediately. 4941 */ 4942 ret = intel_compute_intermediate_wm(state, crtc); 4943 if (ret) { 4944 drm_dbg_kms(&dev_priv->drm, 4945 "No valid intermediate pipe watermarks are possible\n"); 4946 return ret; 4947 } 4948 4949 if (DISPLAY_VER(dev_priv) >= 9) { 4950 if (mode_changed || crtc_state->update_pipe) { 4951 ret = skl_update_scaler_crtc(crtc_state); 4952 if (ret) 4953 return ret; 4954 } 4955 4956 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state); 4957 if (ret) 4958 return ret; 4959 } 4960 4961 if (HAS_IPS(dev_priv)) { 4962 ret = hsw_ips_compute_config(state, crtc); 4963 if (ret) 4964 return ret; 4965 } 4966 4967 if (DISPLAY_VER(dev_priv) >= 9 || 4968 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 4969 ret = hsw_compute_linetime_wm(state, crtc); 4970 if (ret) 4971 return ret; 4972 4973 } 4974 4975 ret = intel_psr2_sel_fetch_update(state, crtc); 4976 if (ret) 4977 return ret; 4978 4979 return 0; 4980 } 4981 4982 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) 4983 { 4984 struct intel_connector *connector; 4985 struct drm_connector_list_iter conn_iter; 4986 4987 drm_connector_list_iter_begin(dev, &conn_iter); 4988 for_each_intel_connector_iter(connector, &conn_iter) { 4989 struct drm_connector_state *conn_state = connector->base.state; 4990 struct intel_encoder *encoder = 4991 to_intel_encoder(connector->base.encoder); 4992 4993 if (conn_state->crtc) 4994 drm_connector_put(&connector->base); 4995 4996 if (encoder) { 4997 struct intel_crtc *crtc = 4998 to_intel_crtc(encoder->base.crtc); 4999 const struct intel_crtc_state *crtc_state = 5000 to_intel_crtc_state(crtc->base.state); 5001 5002 conn_state->best_encoder = &encoder->base; 5003 conn_state->crtc = &crtc->base; 5004 conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3; 5005 5006 drm_connector_get(&connector->base); 5007 } else { 5008 conn_state->best_encoder = NULL; 5009 conn_state->crtc = NULL; 5010 } 5011 } 5012 drm_connector_list_iter_end(&conn_iter); 5013 } 5014 5015 static int 5016 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state, 5017 struct intel_crtc_state *pipe_config) 5018 { 5019 struct drm_connector *connector = conn_state->connector; 5020 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); 5021 const struct drm_display_info *info = &connector->display_info; 5022 int bpp; 5023 5024 switch (conn_state->max_bpc) { 5025 case 6 ... 7: 5026 bpp = 6 * 3; 5027 break; 5028 case 8 ... 9: 5029 bpp = 8 * 3; 5030 break; 5031 case 10 ... 11: 5032 bpp = 10 * 3; 5033 break; 5034 case 12 ... 16: 5035 bpp = 12 * 3; 5036 break; 5037 default: 5038 MISSING_CASE(conn_state->max_bpc); 5039 return -EINVAL; 5040 } 5041 5042 if (bpp < pipe_config->pipe_bpp) { 5043 drm_dbg_kms(&i915->drm, 5044 "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of " 5045 "EDID bpp %d, requested bpp %d, max platform bpp %d\n", 5046 connector->base.id, connector->name, 5047 bpp, 3 * info->bpc, 5048 3 * conn_state->max_requested_bpc, 5049 pipe_config->pipe_bpp); 5050 5051 pipe_config->pipe_bpp = bpp; 5052 } 5053 5054 return 0; 5055 } 5056 5057 static int 5058 compute_baseline_pipe_bpp(struct intel_crtc *crtc, 5059 struct intel_crtc_state *pipe_config) 5060 { 5061 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5062 struct drm_atomic_state *state = pipe_config->uapi.state; 5063 struct drm_connector *connector; 5064 struct drm_connector_state *connector_state; 5065 int bpp, i; 5066 5067 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 5068 IS_CHERRYVIEW(dev_priv))) 5069 bpp = 10*3; 5070 else if (DISPLAY_VER(dev_priv) >= 5) 5071 bpp = 12*3; 5072 else 5073 bpp = 8*3; 5074 5075 pipe_config->pipe_bpp = bpp; 5076 5077 /* Clamp display bpp to connector max bpp */ 5078 for_each_new_connector_in_state(state, connector, connector_state, i) { 5079 int ret; 5080 5081 if (connector_state->crtc != &crtc->base) 5082 continue; 5083 5084 ret = compute_sink_pipe_bpp(connector_state, pipe_config); 5085 if (ret) 5086 return ret; 5087 } 5088 5089 return 0; 5090 } 5091 5092 static void intel_dump_crtc_timings(struct drm_i915_private *i915, 5093 const struct drm_display_mode *mode) 5094 { 5095 drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, " 5096 "type: 0x%x flags: 0x%x\n", 5097 mode->crtc_clock, 5098 mode->crtc_hdisplay, mode->crtc_hsync_start, 5099 mode->crtc_hsync_end, mode->crtc_htotal, 5100 mode->crtc_vdisplay, mode->crtc_vsync_start, 5101 mode->crtc_vsync_end, mode->crtc_vtotal, 5102 mode->type, mode->flags); 5103 } 5104 5105 static void 5106 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config, 5107 const char *id, unsigned int lane_count, 5108 const struct intel_link_m_n *m_n) 5109 { 5110 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); 5111 5112 drm_dbg_kms(&i915->drm, 5113 "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n", 5114 id, lane_count, 5115 m_n->data_m, m_n->data_n, 5116 m_n->link_m, m_n->link_n, m_n->tu); 5117 } 5118 5119 static void 5120 intel_dump_infoframe(struct drm_i915_private *dev_priv, 5121 const union hdmi_infoframe *frame) 5122 { 5123 if (!drm_debug_enabled(DRM_UT_KMS)) 5124 return; 5125 5126 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame); 5127 } 5128 5129 static void 5130 intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv, 5131 const struct drm_dp_vsc_sdp *vsc) 5132 { 5133 if (!drm_debug_enabled(DRM_UT_KMS)) 5134 return; 5135 5136 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc); 5137 } 5138 5139 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x 5140 5141 static const char * const output_type_str[] = { 5142 OUTPUT_TYPE(UNUSED), 5143 OUTPUT_TYPE(ANALOG), 5144 OUTPUT_TYPE(DVO), 5145 OUTPUT_TYPE(SDVO), 5146 OUTPUT_TYPE(LVDS), 5147 OUTPUT_TYPE(TVOUT), 5148 OUTPUT_TYPE(HDMI), 5149 OUTPUT_TYPE(DP), 5150 OUTPUT_TYPE(EDP), 5151 OUTPUT_TYPE(DSI), 5152 OUTPUT_TYPE(DDI), 5153 OUTPUT_TYPE(DP_MST), 5154 }; 5155 5156 #undef OUTPUT_TYPE 5157 5158 static void snprintf_output_types(char *buf, size_t len, 5159 unsigned int output_types) 5160 { 5161 char *str = buf; 5162 int i; 5163 5164 str[0] = '\0'; 5165 5166 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) { 5167 int r; 5168 5169 if ((output_types & BIT(i)) == 0) 5170 continue; 5171 5172 r = snprintf(str, len, "%s%s", 5173 str != buf ? "," : "", output_type_str[i]); 5174 if (r >= len) 5175 break; 5176 str += r; 5177 len -= r; 5178 5179 output_types &= ~BIT(i); 5180 } 5181 5182 WARN_ON_ONCE(output_types != 0); 5183 } 5184 5185 static const char * const output_format_str[] = { 5186 [INTEL_OUTPUT_FORMAT_RGB] = "RGB", 5187 [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0", 5188 [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4", 5189 }; 5190 5191 static const char *output_formats(enum intel_output_format format) 5192 { 5193 if (format >= ARRAY_SIZE(output_format_str)) 5194 return "invalid"; 5195 return output_format_str[format]; 5196 } 5197 5198 static void intel_dump_plane_state(const struct intel_plane_state *plane_state) 5199 { 5200 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 5201 struct drm_i915_private *i915 = to_i915(plane->base.dev); 5202 const struct drm_framebuffer *fb = plane_state->hw.fb; 5203 5204 if (!fb) { 5205 drm_dbg_kms(&i915->drm, 5206 "[PLANE:%d:%s] fb: [NOFB], visible: %s\n", 5207 plane->base.base.id, plane->base.name, 5208 str_yes_no(plane_state->uapi.visible)); 5209 return; 5210 } 5211 5212 drm_dbg_kms(&i915->drm, 5213 "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %p4cc modifier = 0x%llx, visible: %s\n", 5214 plane->base.base.id, plane->base.name, 5215 fb->base.id, fb->width, fb->height, &fb->format->format, 5216 fb->modifier, str_yes_no(plane_state->uapi.visible)); 5217 drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n", 5218 plane_state->hw.rotation, plane_state->scaler_id); 5219 if (plane_state->uapi.visible) 5220 drm_dbg_kms(&i915->drm, 5221 "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n", 5222 DRM_RECT_FP_ARG(&plane_state->uapi.src), 5223 DRM_RECT_ARG(&plane_state->uapi.dst)); 5224 } 5225 5226 static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, 5227 struct intel_atomic_state *state, 5228 const char *context) 5229 { 5230 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 5231 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5232 const struct intel_plane_state *plane_state; 5233 struct intel_plane *plane; 5234 char buf[64]; 5235 int i; 5236 5237 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n", 5238 crtc->base.base.id, crtc->base.name, 5239 str_yes_no(pipe_config->hw.enable), context); 5240 5241 if (!pipe_config->hw.enable) 5242 goto dump_planes; 5243 5244 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types); 5245 drm_dbg_kms(&dev_priv->drm, 5246 "active: %s, output_types: %s (0x%x), output format: %s\n", 5247 str_yes_no(pipe_config->hw.active), 5248 buf, pipe_config->output_types, 5249 output_formats(pipe_config->output_format)); 5250 5251 drm_dbg_kms(&dev_priv->drm, 5252 "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", 5253 transcoder_name(pipe_config->cpu_transcoder), 5254 pipe_config->pipe_bpp, pipe_config->dither); 5255 5256 drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n", 5257 transcoder_name(pipe_config->mst_master_transcoder)); 5258 5259 drm_dbg_kms(&dev_priv->drm, 5260 "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n", 5261 transcoder_name(pipe_config->master_transcoder), 5262 pipe_config->sync_mode_slaves_mask); 5263 5264 drm_dbg_kms(&dev_priv->drm, "bigjoiner: %s, pipes: 0x%x\n", 5265 intel_crtc_is_bigjoiner_slave(pipe_config) ? "slave" : 5266 intel_crtc_is_bigjoiner_master(pipe_config) ? "master" : "no", 5267 pipe_config->bigjoiner_pipes); 5268 5269 drm_dbg_kms(&dev_priv->drm, "splitter: %s, link count %d, overlap %d\n", 5270 str_enabled_disabled(pipe_config->splitter.enable), 5271 pipe_config->splitter.link_count, 5272 pipe_config->splitter.pixel_overlap); 5273 5274 if (pipe_config->has_pch_encoder) 5275 intel_dump_m_n_config(pipe_config, "fdi", 5276 pipe_config->fdi_lanes, 5277 &pipe_config->fdi_m_n); 5278 5279 if (intel_crtc_has_dp_encoder(pipe_config)) { 5280 intel_dump_m_n_config(pipe_config, "dp m_n", 5281 pipe_config->lane_count, 5282 &pipe_config->dp_m_n); 5283 intel_dump_m_n_config(pipe_config, "dp m2_n2", 5284 pipe_config->lane_count, 5285 &pipe_config->dp_m2_n2); 5286 } 5287 5288 drm_dbg_kms(&dev_priv->drm, "framestart delay: %d, MSA timing delay: %d\n", 5289 pipe_config->framestart_delay, pipe_config->msa_timing_delay); 5290 5291 drm_dbg_kms(&dev_priv->drm, 5292 "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n", 5293 pipe_config->has_audio, pipe_config->has_infoframe, 5294 pipe_config->infoframes.enable); 5295 5296 if (pipe_config->infoframes.enable & 5297 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) 5298 drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n", 5299 pipe_config->infoframes.gcp); 5300 if (pipe_config->infoframes.enable & 5301 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) 5302 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi); 5303 if (pipe_config->infoframes.enable & 5304 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD)) 5305 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd); 5306 if (pipe_config->infoframes.enable & 5307 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR)) 5308 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi); 5309 if (pipe_config->infoframes.enable & 5310 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) 5311 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); 5312 if (pipe_config->infoframes.enable & 5313 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA)) 5314 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); 5315 if (pipe_config->infoframes.enable & 5316 intel_hdmi_infoframe_enable(DP_SDP_VSC)) 5317 intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc); 5318 5319 drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n", 5320 str_yes_no(pipe_config->vrr.enable), 5321 pipe_config->vrr.vmin, pipe_config->vrr.vmax, 5322 pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband, 5323 pipe_config->vrr.flipline, 5324 intel_vrr_vmin_vblank_start(pipe_config), 5325 intel_vrr_vmax_vblank_start(pipe_config)); 5326 5327 drm_dbg_kms(&dev_priv->drm, "requested mode: " DRM_MODE_FMT "\n", 5328 DRM_MODE_ARG(&pipe_config->hw.mode)); 5329 drm_dbg_kms(&dev_priv->drm, "adjusted mode: " DRM_MODE_FMT "\n", 5330 DRM_MODE_ARG(&pipe_config->hw.adjusted_mode)); 5331 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode); 5332 drm_dbg_kms(&dev_priv->drm, "pipe mode: " DRM_MODE_FMT "\n", 5333 DRM_MODE_ARG(&pipe_config->hw.pipe_mode)); 5334 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode); 5335 drm_dbg_kms(&dev_priv->drm, 5336 "port clock: %d, pipe src: " DRM_RECT_FMT ", pixel rate %d\n", 5337 pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src), 5338 pipe_config->pixel_rate); 5339 5340 drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n", 5341 pipe_config->linetime, pipe_config->ips_linetime); 5342 5343 if (DISPLAY_VER(dev_priv) >= 9) 5344 drm_dbg_kms(&dev_priv->drm, 5345 "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", 5346 crtc->num_scalers, 5347 pipe_config->scaler_state.scaler_users, 5348 pipe_config->scaler_state.scaler_id); 5349 5350 if (HAS_GMCH(dev_priv)) 5351 drm_dbg_kms(&dev_priv->drm, 5352 "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", 5353 pipe_config->gmch_pfit.control, 5354 pipe_config->gmch_pfit.pgm_ratios, 5355 pipe_config->gmch_pfit.lvds_border_bits); 5356 else 5357 drm_dbg_kms(&dev_priv->drm, 5358 "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n", 5359 DRM_RECT_ARG(&pipe_config->pch_pfit.dst), 5360 str_enabled_disabled(pipe_config->pch_pfit.enabled), 5361 str_yes_no(pipe_config->pch_pfit.force_thru)); 5362 5363 drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i, drrs: %i\n", 5364 pipe_config->ips_enabled, pipe_config->double_wide, 5365 pipe_config->has_drrs); 5366 5367 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state); 5368 5369 if (IS_CHERRYVIEW(dev_priv)) 5370 drm_dbg_kms(&dev_priv->drm, 5371 "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", 5372 pipe_config->cgm_mode, pipe_config->gamma_mode, 5373 pipe_config->gamma_enable, pipe_config->csc_enable); 5374 else 5375 drm_dbg_kms(&dev_priv->drm, 5376 "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", 5377 pipe_config->csc_mode, pipe_config->gamma_mode, 5378 pipe_config->gamma_enable, pipe_config->csc_enable); 5379 5380 drm_dbg_kms(&dev_priv->drm, "degamma lut: %d entries, gamma lut: %d entries\n", 5381 pipe_config->hw.degamma_lut ? 5382 drm_color_lut_size(pipe_config->hw.degamma_lut) : 0, 5383 pipe_config->hw.gamma_lut ? 5384 drm_color_lut_size(pipe_config->hw.gamma_lut) : 0); 5385 5386 dump_planes: 5387 if (!state) 5388 return; 5389 5390 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 5391 if (plane->pipe == crtc->pipe) 5392 intel_dump_plane_state(plane_state); 5393 } 5394 } 5395 5396 static bool check_digital_port_conflicts(struct intel_atomic_state *state) 5397 { 5398 struct drm_device *dev = state->base.dev; 5399 struct drm_connector *connector; 5400 struct drm_connector_list_iter conn_iter; 5401 unsigned int used_ports = 0; 5402 unsigned int used_mst_ports = 0; 5403 bool ret = true; 5404 5405 /* 5406 * We're going to peek into connector->state, 5407 * hence connection_mutex must be held. 5408 */ 5409 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex); 5410 5411 /* 5412 * Walk the connector list instead of the encoder 5413 * list to detect the problem on ddi platforms 5414 * where there's just one encoder per digital port. 5415 */ 5416 drm_connector_list_iter_begin(dev, &conn_iter); 5417 drm_for_each_connector_iter(connector, &conn_iter) { 5418 struct drm_connector_state *connector_state; 5419 struct intel_encoder *encoder; 5420 5421 connector_state = 5422 drm_atomic_get_new_connector_state(&state->base, 5423 connector); 5424 if (!connector_state) 5425 connector_state = connector->state; 5426 5427 if (!connector_state->best_encoder) 5428 continue; 5429 5430 encoder = to_intel_encoder(connector_state->best_encoder); 5431 5432 drm_WARN_ON(dev, !connector_state->crtc); 5433 5434 switch (encoder->type) { 5435 case INTEL_OUTPUT_DDI: 5436 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev)))) 5437 break; 5438 fallthrough; 5439 case INTEL_OUTPUT_DP: 5440 case INTEL_OUTPUT_HDMI: 5441 case INTEL_OUTPUT_EDP: 5442 /* the same port mustn't appear more than once */ 5443 if (used_ports & BIT(encoder->port)) 5444 ret = false; 5445 5446 used_ports |= BIT(encoder->port); 5447 break; 5448 case INTEL_OUTPUT_DP_MST: 5449 used_mst_ports |= 5450 1 << encoder->port; 5451 break; 5452 default: 5453 break; 5454 } 5455 } 5456 drm_connector_list_iter_end(&conn_iter); 5457 5458 /* can't mix MST and SST/HDMI on the same port */ 5459 if (used_ports & used_mst_ports) 5460 return false; 5461 5462 return ret; 5463 } 5464 5465 static void 5466 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state, 5467 struct intel_crtc *crtc) 5468 { 5469 struct intel_crtc_state *crtc_state = 5470 intel_atomic_get_new_crtc_state(state, crtc); 5471 5472 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 5473 5474 drm_property_replace_blob(&crtc_state->hw.degamma_lut, 5475 crtc_state->uapi.degamma_lut); 5476 drm_property_replace_blob(&crtc_state->hw.gamma_lut, 5477 crtc_state->uapi.gamma_lut); 5478 drm_property_replace_blob(&crtc_state->hw.ctm, 5479 crtc_state->uapi.ctm); 5480 } 5481 5482 static void 5483 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state, 5484 struct intel_crtc *crtc) 5485 { 5486 struct intel_crtc_state *crtc_state = 5487 intel_atomic_get_new_crtc_state(state, crtc); 5488 5489 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 5490 5491 crtc_state->hw.enable = crtc_state->uapi.enable; 5492 crtc_state->hw.active = crtc_state->uapi.active; 5493 drm_mode_copy(&crtc_state->hw.mode, 5494 &crtc_state->uapi.mode); 5495 drm_mode_copy(&crtc_state->hw.adjusted_mode, 5496 &crtc_state->uapi.adjusted_mode); 5497 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter; 5498 5499 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 5500 } 5501 5502 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state) 5503 { 5504 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 5505 return; 5506 5507 crtc_state->uapi.enable = crtc_state->hw.enable; 5508 crtc_state->uapi.active = crtc_state->hw.active; 5509 drm_WARN_ON(crtc_state->uapi.crtc->dev, 5510 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0); 5511 5512 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode; 5513 crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter; 5514 5515 drm_property_replace_blob(&crtc_state->uapi.degamma_lut, 5516 crtc_state->hw.degamma_lut); 5517 drm_property_replace_blob(&crtc_state->uapi.gamma_lut, 5518 crtc_state->hw.gamma_lut); 5519 drm_property_replace_blob(&crtc_state->uapi.ctm, 5520 crtc_state->hw.ctm); 5521 } 5522 5523 static void 5524 copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state, 5525 struct intel_crtc *slave_crtc) 5526 { 5527 struct intel_crtc_state *slave_crtc_state = 5528 intel_atomic_get_new_crtc_state(state, slave_crtc); 5529 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 5530 const struct intel_crtc_state *master_crtc_state = 5531 intel_atomic_get_new_crtc_state(state, master_crtc); 5532 5533 drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut, 5534 master_crtc_state->hw.degamma_lut); 5535 drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut, 5536 master_crtc_state->hw.gamma_lut); 5537 drm_property_replace_blob(&slave_crtc_state->hw.ctm, 5538 master_crtc_state->hw.ctm); 5539 5540 slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed; 5541 } 5542 5543 static int 5544 copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state, 5545 struct intel_crtc *slave_crtc) 5546 { 5547 struct intel_crtc_state *slave_crtc_state = 5548 intel_atomic_get_new_crtc_state(state, slave_crtc); 5549 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 5550 const struct intel_crtc_state *master_crtc_state = 5551 intel_atomic_get_new_crtc_state(state, master_crtc); 5552 struct intel_crtc_state *saved_state; 5553 5554 WARN_ON(master_crtc_state->bigjoiner_pipes != 5555 slave_crtc_state->bigjoiner_pipes); 5556 5557 saved_state = kmemdup(master_crtc_state, sizeof(*saved_state), GFP_KERNEL); 5558 if (!saved_state) 5559 return -ENOMEM; 5560 5561 /* preserve some things from the slave's original crtc state */ 5562 saved_state->uapi = slave_crtc_state->uapi; 5563 saved_state->scaler_state = slave_crtc_state->scaler_state; 5564 saved_state->shared_dpll = slave_crtc_state->shared_dpll; 5565 saved_state->dpll_hw_state = slave_crtc_state->dpll_hw_state; 5566 saved_state->crc_enabled = slave_crtc_state->crc_enabled; 5567 5568 intel_crtc_free_hw_state(slave_crtc_state); 5569 memcpy(slave_crtc_state, saved_state, sizeof(*slave_crtc_state)); 5570 kfree(saved_state); 5571 5572 /* Re-init hw state */ 5573 memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw)); 5574 slave_crtc_state->hw.enable = master_crtc_state->hw.enable; 5575 slave_crtc_state->hw.active = master_crtc_state->hw.active; 5576 drm_mode_copy(&slave_crtc_state->hw.mode, 5577 &master_crtc_state->hw.mode); 5578 drm_mode_copy(&slave_crtc_state->hw.pipe_mode, 5579 &master_crtc_state->hw.pipe_mode); 5580 drm_mode_copy(&slave_crtc_state->hw.adjusted_mode, 5581 &master_crtc_state->hw.adjusted_mode); 5582 slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter; 5583 5584 copy_bigjoiner_crtc_state_nomodeset(state, slave_crtc); 5585 5586 slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed; 5587 slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed; 5588 slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed; 5589 5590 WARN_ON(master_crtc_state->bigjoiner_pipes != 5591 slave_crtc_state->bigjoiner_pipes); 5592 5593 return 0; 5594 } 5595 5596 static int 5597 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state, 5598 struct intel_crtc *crtc) 5599 { 5600 struct intel_crtc_state *crtc_state = 5601 intel_atomic_get_new_crtc_state(state, crtc); 5602 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5603 struct intel_crtc_state *saved_state; 5604 5605 saved_state = intel_crtc_state_alloc(crtc); 5606 if (!saved_state) 5607 return -ENOMEM; 5608 5609 /* free the old crtc_state->hw members */ 5610 intel_crtc_free_hw_state(crtc_state); 5611 5612 /* FIXME: before the switch to atomic started, a new pipe_config was 5613 * kzalloc'd. Code that depends on any field being zero should be 5614 * fixed, so that the crtc_state can be safely duplicated. For now, 5615 * only fields that are know to not cause problems are preserved. */ 5616 5617 saved_state->uapi = crtc_state->uapi; 5618 saved_state->scaler_state = crtc_state->scaler_state; 5619 saved_state->shared_dpll = crtc_state->shared_dpll; 5620 saved_state->dpll_hw_state = crtc_state->dpll_hw_state; 5621 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, 5622 sizeof(saved_state->icl_port_dplls)); 5623 saved_state->crc_enabled = crtc_state->crc_enabled; 5624 if (IS_G4X(dev_priv) || 5625 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5626 saved_state->wm = crtc_state->wm; 5627 5628 memcpy(crtc_state, saved_state, sizeof(*crtc_state)); 5629 kfree(saved_state); 5630 5631 intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc); 5632 5633 return 0; 5634 } 5635 5636 static int 5637 intel_modeset_pipe_config(struct intel_atomic_state *state, 5638 struct intel_crtc_state *pipe_config) 5639 { 5640 struct drm_crtc *crtc = pipe_config->uapi.crtc; 5641 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); 5642 struct drm_connector *connector; 5643 struct drm_connector_state *connector_state; 5644 int pipe_src_w, pipe_src_h; 5645 int base_bpp, ret, i; 5646 bool retry = true; 5647 5648 pipe_config->cpu_transcoder = 5649 (enum transcoder) to_intel_crtc(crtc)->pipe; 5650 5651 pipe_config->framestart_delay = 1; 5652 5653 /* 5654 * Sanitize sync polarity flags based on requested ones. If neither 5655 * positive or negative polarity is requested, treat this as meaning 5656 * negative polarity. 5657 */ 5658 if (!(pipe_config->hw.adjusted_mode.flags & 5659 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) 5660 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; 5661 5662 if (!(pipe_config->hw.adjusted_mode.flags & 5663 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 5664 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; 5665 5666 ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc), 5667 pipe_config); 5668 if (ret) 5669 return ret; 5670 5671 base_bpp = pipe_config->pipe_bpp; 5672 5673 /* 5674 * Determine the real pipe dimensions. Note that stereo modes can 5675 * increase the actual pipe size due to the frame doubling and 5676 * insertion of additional space for blanks between the frame. This 5677 * is stored in the crtc timings. We use the requested mode to do this 5678 * computation to clearly distinguish it from the adjusted mode, which 5679 * can be changed by the connectors in the below retry loop. 5680 */ 5681 drm_mode_get_hv_timing(&pipe_config->hw.mode, 5682 &pipe_src_w, &pipe_src_h); 5683 drm_rect_init(&pipe_config->pipe_src, 0, 0, 5684 pipe_src_w, pipe_src_h); 5685 5686 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5687 struct intel_encoder *encoder = 5688 to_intel_encoder(connector_state->best_encoder); 5689 5690 if (connector_state->crtc != crtc) 5691 continue; 5692 5693 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) { 5694 drm_dbg_kms(&i915->drm, 5695 "rejecting invalid cloning configuration\n"); 5696 return -EINVAL; 5697 } 5698 5699 /* 5700 * Determine output_types before calling the .compute_config() 5701 * hooks so that the hooks can use this information safely. 5702 */ 5703 if (encoder->compute_output_type) 5704 pipe_config->output_types |= 5705 BIT(encoder->compute_output_type(encoder, pipe_config, 5706 connector_state)); 5707 else 5708 pipe_config->output_types |= BIT(encoder->type); 5709 } 5710 5711 encoder_retry: 5712 /* Ensure the port clock defaults are reset when retrying. */ 5713 pipe_config->port_clock = 0; 5714 pipe_config->pixel_multiplier = 1; 5715 5716 /* Fill in default crtc timings, allow encoders to overwrite them. */ 5717 drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode, 5718 CRTC_STEREO_DOUBLE); 5719 5720 /* Pass our mode to the connectors and the CRTC to give them a chance to 5721 * adjust it according to limitations or connector properties, and also 5722 * a chance to reject the mode entirely. 5723 */ 5724 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5725 struct intel_encoder *encoder = 5726 to_intel_encoder(connector_state->best_encoder); 5727 5728 if (connector_state->crtc != crtc) 5729 continue; 5730 5731 ret = encoder->compute_config(encoder, pipe_config, 5732 connector_state); 5733 if (ret == -EDEADLK) 5734 return ret; 5735 if (ret < 0) { 5736 drm_dbg_kms(&i915->drm, "Encoder config failure: %d\n", ret); 5737 return ret; 5738 } 5739 } 5740 5741 /* Set default port clock if not overwritten by the encoder. Needs to be 5742 * done afterwards in case the encoder adjusts the mode. */ 5743 if (!pipe_config->port_clock) 5744 pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock 5745 * pipe_config->pixel_multiplier; 5746 5747 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); 5748 if (ret == -EDEADLK) 5749 return ret; 5750 if (ret == -EAGAIN) { 5751 if (drm_WARN(&i915->drm, !retry, 5752 "loop in pipe configuration computation\n")) 5753 return -EINVAL; 5754 5755 drm_dbg_kms(&i915->drm, "CRTC bw constrained, retrying\n"); 5756 retry = false; 5757 goto encoder_retry; 5758 } 5759 if (ret < 0) { 5760 drm_dbg_kms(&i915->drm, "CRTC config failure: %d\n", ret); 5761 return ret; 5762 } 5763 5764 /* Dithering seems to not pass-through bits correctly when it should, so 5765 * only enable it on 6bpc panels and when its not a compliance 5766 * test requesting 6bpc video pattern. 5767 */ 5768 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) && 5769 !pipe_config->dither_force_disable; 5770 drm_dbg_kms(&i915->drm, 5771 "hw max bpp: %i, pipe bpp: %i, dithering: %i\n", 5772 base_bpp, pipe_config->pipe_bpp, pipe_config->dither); 5773 5774 return 0; 5775 } 5776 5777 static int 5778 intel_modeset_pipe_config_late(struct intel_crtc_state *crtc_state) 5779 { 5780 struct intel_atomic_state *state = 5781 to_intel_atomic_state(crtc_state->uapi.state); 5782 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 5783 struct drm_connector_state *conn_state; 5784 struct drm_connector *connector; 5785 int i; 5786 5787 intel_bigjoiner_adjust_pipe_src(crtc_state); 5788 5789 for_each_new_connector_in_state(&state->base, connector, 5790 conn_state, i) { 5791 struct intel_encoder *encoder = 5792 to_intel_encoder(conn_state->best_encoder); 5793 int ret; 5794 5795 if (conn_state->crtc != &crtc->base || 5796 !encoder->compute_config_late) 5797 continue; 5798 5799 ret = encoder->compute_config_late(encoder, crtc_state, 5800 conn_state); 5801 if (ret) 5802 return ret; 5803 } 5804 5805 return 0; 5806 } 5807 5808 bool intel_fuzzy_clock_check(int clock1, int clock2) 5809 { 5810 int diff; 5811 5812 if (clock1 == clock2) 5813 return true; 5814 5815 if (!clock1 || !clock2) 5816 return false; 5817 5818 diff = abs(clock1 - clock2); 5819 5820 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) 5821 return true; 5822 5823 return false; 5824 } 5825 5826 static bool 5827 intel_compare_m_n(unsigned int m, unsigned int n, 5828 unsigned int m2, unsigned int n2, 5829 bool exact) 5830 { 5831 if (m == m2 && n == n2) 5832 return true; 5833 5834 if (exact || !m || !n || !m2 || !n2) 5835 return false; 5836 5837 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); 5838 5839 if (n > n2) { 5840 while (n > n2) { 5841 m2 <<= 1; 5842 n2 <<= 1; 5843 } 5844 } else if (n < n2) { 5845 while (n < n2) { 5846 m <<= 1; 5847 n <<= 1; 5848 } 5849 } 5850 5851 if (n != n2) 5852 return false; 5853 5854 return intel_fuzzy_clock_check(m, m2); 5855 } 5856 5857 static bool 5858 intel_compare_link_m_n(const struct intel_link_m_n *m_n, 5859 const struct intel_link_m_n *m2_n2, 5860 bool exact) 5861 { 5862 return m_n->tu == m2_n2->tu && 5863 intel_compare_m_n(m_n->data_m, m_n->data_n, 5864 m2_n2->data_m, m2_n2->data_n, exact) && 5865 intel_compare_m_n(m_n->link_m, m_n->link_n, 5866 m2_n2->link_m, m2_n2->link_n, exact); 5867 } 5868 5869 static bool 5870 intel_compare_infoframe(const union hdmi_infoframe *a, 5871 const union hdmi_infoframe *b) 5872 { 5873 return memcmp(a, b, sizeof(*a)) == 0; 5874 } 5875 5876 static bool 5877 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a, 5878 const struct drm_dp_vsc_sdp *b) 5879 { 5880 return memcmp(a, b, sizeof(*a)) == 0; 5881 } 5882 5883 static void 5884 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv, 5885 bool fastset, const char *name, 5886 const union hdmi_infoframe *a, 5887 const union hdmi_infoframe *b) 5888 { 5889 if (fastset) { 5890 if (!drm_debug_enabled(DRM_UT_KMS)) 5891 return; 5892 5893 drm_dbg_kms(&dev_priv->drm, 5894 "fastset mismatch in %s infoframe\n", name); 5895 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 5896 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a); 5897 drm_dbg_kms(&dev_priv->drm, "found:\n"); 5898 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b); 5899 } else { 5900 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name); 5901 drm_err(&dev_priv->drm, "expected:\n"); 5902 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a); 5903 drm_err(&dev_priv->drm, "found:\n"); 5904 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b); 5905 } 5906 } 5907 5908 static void 5909 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv, 5910 bool fastset, const char *name, 5911 const struct drm_dp_vsc_sdp *a, 5912 const struct drm_dp_vsc_sdp *b) 5913 { 5914 if (fastset) { 5915 if (!drm_debug_enabled(DRM_UT_KMS)) 5916 return; 5917 5918 drm_dbg_kms(&dev_priv->drm, 5919 "fastset mismatch in %s dp sdp\n", name); 5920 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 5921 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a); 5922 drm_dbg_kms(&dev_priv->drm, "found:\n"); 5923 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b); 5924 } else { 5925 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name); 5926 drm_err(&dev_priv->drm, "expected:\n"); 5927 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a); 5928 drm_err(&dev_priv->drm, "found:\n"); 5929 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b); 5930 } 5931 } 5932 5933 static void __printf(4, 5) 5934 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc, 5935 const char *name, const char *format, ...) 5936 { 5937 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 5938 struct va_format vaf; 5939 va_list args; 5940 5941 va_start(args, format); 5942 vaf.fmt = format; 5943 vaf.va = &args; 5944 5945 if (fastset) 5946 drm_dbg_kms(&i915->drm, 5947 "[CRTC:%d:%s] fastset mismatch in %s %pV\n", 5948 crtc->base.base.id, crtc->base.name, name, &vaf); 5949 else 5950 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n", 5951 crtc->base.base.id, crtc->base.name, name, &vaf); 5952 5953 va_end(args); 5954 } 5955 5956 static bool fastboot_enabled(struct drm_i915_private *dev_priv) 5957 { 5958 if (dev_priv->params.fastboot != -1) 5959 return dev_priv->params.fastboot; 5960 5961 /* Enable fastboot by default on Skylake and newer */ 5962 if (DISPLAY_VER(dev_priv) >= 9) 5963 return true; 5964 5965 /* Enable fastboot by default on VLV and CHV */ 5966 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5967 return true; 5968 5969 /* Disabled by default on all others */ 5970 return false; 5971 } 5972 5973 static bool 5974 intel_pipe_config_compare(const struct intel_crtc_state *current_config, 5975 const struct intel_crtc_state *pipe_config, 5976 bool fastset) 5977 { 5978 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev); 5979 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 5980 bool ret = true; 5981 u32 bp_gamma = 0; 5982 bool fixup_inherited = fastset && 5983 current_config->inherited && !pipe_config->inherited; 5984 5985 if (fixup_inherited && !fastboot_enabled(dev_priv)) { 5986 drm_dbg_kms(&dev_priv->drm, 5987 "initial modeset and fastboot not set\n"); 5988 ret = false; 5989 } 5990 5991 #define PIPE_CONF_CHECK_X(name) do { \ 5992 if (current_config->name != pipe_config->name) { \ 5993 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5994 "(expected 0x%08x, found 0x%08x)", \ 5995 current_config->name, \ 5996 pipe_config->name); \ 5997 ret = false; \ 5998 } \ 5999 } while (0) 6000 6001 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \ 6002 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \ 6003 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6004 "(expected 0x%08x, found 0x%08x)", \ 6005 current_config->name & (mask), \ 6006 pipe_config->name & (mask)); \ 6007 ret = false; \ 6008 } \ 6009 } while (0) 6010 6011 #define PIPE_CONF_CHECK_I(name) do { \ 6012 if (current_config->name != pipe_config->name) { \ 6013 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6014 "(expected %i, found %i)", \ 6015 current_config->name, \ 6016 pipe_config->name); \ 6017 ret = false; \ 6018 } \ 6019 } while (0) 6020 6021 #define PIPE_CONF_CHECK_BOOL(name) do { \ 6022 if (current_config->name != pipe_config->name) { \ 6023 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6024 "(expected %s, found %s)", \ 6025 str_yes_no(current_config->name), \ 6026 str_yes_no(pipe_config->name)); \ 6027 ret = false; \ 6028 } \ 6029 } while (0) 6030 6031 /* 6032 * Checks state where we only read out the enabling, but not the entire 6033 * state itself (like full infoframes or ELD for audio). These states 6034 * require a full modeset on bootup to fix up. 6035 */ 6036 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \ 6037 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \ 6038 PIPE_CONF_CHECK_BOOL(name); \ 6039 } else { \ 6040 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6041 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \ 6042 str_yes_no(current_config->name), \ 6043 str_yes_no(pipe_config->name)); \ 6044 ret = false; \ 6045 } \ 6046 } while (0) 6047 6048 #define PIPE_CONF_CHECK_P(name) do { \ 6049 if (current_config->name != pipe_config->name) { \ 6050 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6051 "(expected %p, found %p)", \ 6052 current_config->name, \ 6053 pipe_config->name); \ 6054 ret = false; \ 6055 } \ 6056 } while (0) 6057 6058 #define PIPE_CONF_CHECK_M_N(name) do { \ 6059 if (!intel_compare_link_m_n(¤t_config->name, \ 6060 &pipe_config->name,\ 6061 !fastset)) { \ 6062 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6063 "(expected tu %i data %i/%i link %i/%i, " \ 6064 "found tu %i, data %i/%i link %i/%i)", \ 6065 current_config->name.tu, \ 6066 current_config->name.data_m, \ 6067 current_config->name.data_n, \ 6068 current_config->name.link_m, \ 6069 current_config->name.link_n, \ 6070 pipe_config->name.tu, \ 6071 pipe_config->name.data_m, \ 6072 pipe_config->name.data_n, \ 6073 pipe_config->name.link_m, \ 6074 pipe_config->name.link_n); \ 6075 ret = false; \ 6076 } \ 6077 } while (0) 6078 6079 /* This is required for BDW+ where there is only one set of registers for 6080 * switching between high and low RR. 6081 * This macro can be used whenever a comparison has to be made between one 6082 * hw state and multiple sw state variables. 6083 */ 6084 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \ 6085 if (!intel_compare_link_m_n(¤t_config->name, \ 6086 &pipe_config->name, !fastset) && \ 6087 !intel_compare_link_m_n(¤t_config->alt_name, \ 6088 &pipe_config->name, !fastset)) { \ 6089 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6090 "(expected tu %i data %i/%i link %i/%i, " \ 6091 "or tu %i data %i/%i link %i/%i, " \ 6092 "found tu %i, data %i/%i link %i/%i)", \ 6093 current_config->name.tu, \ 6094 current_config->name.data_m, \ 6095 current_config->name.data_n, \ 6096 current_config->name.link_m, \ 6097 current_config->name.link_n, \ 6098 current_config->alt_name.tu, \ 6099 current_config->alt_name.data_m, \ 6100 current_config->alt_name.data_n, \ 6101 current_config->alt_name.link_m, \ 6102 current_config->alt_name.link_n, \ 6103 pipe_config->name.tu, \ 6104 pipe_config->name.data_m, \ 6105 pipe_config->name.data_n, \ 6106 pipe_config->name.link_m, \ 6107 pipe_config->name.link_n); \ 6108 ret = false; \ 6109 } \ 6110 } while (0) 6111 6112 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \ 6113 if ((current_config->name ^ pipe_config->name) & (mask)) { \ 6114 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6115 "(%x) (expected %i, found %i)", \ 6116 (mask), \ 6117 current_config->name & (mask), \ 6118 pipe_config->name & (mask)); \ 6119 ret = false; \ 6120 } \ 6121 } while (0) 6122 6123 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \ 6124 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ 6125 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6126 "(expected %i, found %i)", \ 6127 current_config->name, \ 6128 pipe_config->name); \ 6129 ret = false; \ 6130 } \ 6131 } while (0) 6132 6133 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \ 6134 if (!intel_compare_infoframe(¤t_config->infoframes.name, \ 6135 &pipe_config->infoframes.name)) { \ 6136 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \ 6137 ¤t_config->infoframes.name, \ 6138 &pipe_config->infoframes.name); \ 6139 ret = false; \ 6140 } \ 6141 } while (0) 6142 6143 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \ 6144 if (!current_config->has_psr && !pipe_config->has_psr && \ 6145 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \ 6146 &pipe_config->infoframes.name)) { \ 6147 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \ 6148 ¤t_config->infoframes.name, \ 6149 &pipe_config->infoframes.name); \ 6150 ret = false; \ 6151 } \ 6152 } while (0) 6153 6154 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \ 6155 if (current_config->name1 != pipe_config->name1) { \ 6156 pipe_config_mismatch(fastset, crtc, __stringify(name1), \ 6157 "(expected %i, found %i, won't compare lut values)", \ 6158 current_config->name1, \ 6159 pipe_config->name1); \ 6160 ret = false;\ 6161 } else { \ 6162 if (!intel_color_lut_equal(current_config->name2, \ 6163 pipe_config->name2, pipe_config->name1, \ 6164 bit_precision)) { \ 6165 pipe_config_mismatch(fastset, crtc, __stringify(name2), \ 6166 "hw_state doesn't match sw_state"); \ 6167 ret = false; \ 6168 } \ 6169 } \ 6170 } while (0) 6171 6172 #define PIPE_CONF_QUIRK(quirk) \ 6173 ((current_config->quirks | pipe_config->quirks) & (quirk)) 6174 6175 PIPE_CONF_CHECK_I(cpu_transcoder); 6176 6177 PIPE_CONF_CHECK_BOOL(has_pch_encoder); 6178 PIPE_CONF_CHECK_I(fdi_lanes); 6179 PIPE_CONF_CHECK_M_N(fdi_m_n); 6180 6181 PIPE_CONF_CHECK_I(lane_count); 6182 PIPE_CONF_CHECK_X(lane_lat_optim_mask); 6183 6184 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) { 6185 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); 6186 } else { 6187 PIPE_CONF_CHECK_M_N(dp_m_n); 6188 PIPE_CONF_CHECK_M_N(dp_m2_n2); 6189 } 6190 6191 PIPE_CONF_CHECK_X(output_types); 6192 6193 PIPE_CONF_CHECK_I(framestart_delay); 6194 PIPE_CONF_CHECK_I(msa_timing_delay); 6195 6196 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay); 6197 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_htotal); 6198 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_start); 6199 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_end); 6200 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_start); 6201 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_end); 6202 6203 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vdisplay); 6204 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vtotal); 6205 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_start); 6206 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_end); 6207 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_start); 6208 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_end); 6209 6210 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay); 6211 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal); 6212 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start); 6213 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end); 6214 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start); 6215 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end); 6216 6217 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay); 6218 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal); 6219 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start); 6220 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end); 6221 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start); 6222 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end); 6223 6224 PIPE_CONF_CHECK_I(pixel_multiplier); 6225 6226 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6227 DRM_MODE_FLAG_INTERLACE); 6228 6229 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { 6230 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6231 DRM_MODE_FLAG_PHSYNC); 6232 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6233 DRM_MODE_FLAG_NHSYNC); 6234 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6235 DRM_MODE_FLAG_PVSYNC); 6236 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6237 DRM_MODE_FLAG_NVSYNC); 6238 } 6239 6240 PIPE_CONF_CHECK_I(output_format); 6241 PIPE_CONF_CHECK_BOOL(has_hdmi_sink); 6242 if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || 6243 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 6244 PIPE_CONF_CHECK_BOOL(limited_color_range); 6245 6246 PIPE_CONF_CHECK_BOOL(hdmi_scrambling); 6247 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio); 6248 PIPE_CONF_CHECK_BOOL(has_infoframe); 6249 PIPE_CONF_CHECK_BOOL(fec_enable); 6250 6251 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio); 6252 6253 PIPE_CONF_CHECK_X(gmch_pfit.control); 6254 /* pfit ratios are autocomputed by the hw on gen4+ */ 6255 if (DISPLAY_VER(dev_priv) < 4) 6256 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); 6257 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); 6258 6259 /* 6260 * Changing the EDP transcoder input mux 6261 * (A_ONOFF vs. A_ON) requires a full modeset. 6262 */ 6263 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru); 6264 6265 if (!fastset) { 6266 PIPE_CONF_CHECK_I(pipe_src.x1); 6267 PIPE_CONF_CHECK_I(pipe_src.y1); 6268 PIPE_CONF_CHECK_I(pipe_src.x2); 6269 PIPE_CONF_CHECK_I(pipe_src.y2); 6270 6271 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled); 6272 if (current_config->pch_pfit.enabled) { 6273 PIPE_CONF_CHECK_I(pch_pfit.dst.x1); 6274 PIPE_CONF_CHECK_I(pch_pfit.dst.y1); 6275 PIPE_CONF_CHECK_I(pch_pfit.dst.x2); 6276 PIPE_CONF_CHECK_I(pch_pfit.dst.y2); 6277 } 6278 6279 PIPE_CONF_CHECK_I(scaler_state.scaler_id); 6280 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate); 6281 6282 PIPE_CONF_CHECK_X(gamma_mode); 6283 if (IS_CHERRYVIEW(dev_priv)) 6284 PIPE_CONF_CHECK_X(cgm_mode); 6285 else 6286 PIPE_CONF_CHECK_X(csc_mode); 6287 PIPE_CONF_CHECK_BOOL(gamma_enable); 6288 PIPE_CONF_CHECK_BOOL(csc_enable); 6289 6290 PIPE_CONF_CHECK_I(linetime); 6291 PIPE_CONF_CHECK_I(ips_linetime); 6292 6293 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config); 6294 if (bp_gamma) 6295 PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma); 6296 6297 if (current_config->active_planes) { 6298 PIPE_CONF_CHECK_BOOL(has_psr); 6299 PIPE_CONF_CHECK_BOOL(has_psr2); 6300 PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); 6301 PIPE_CONF_CHECK_I(dc3co_exitline); 6302 } 6303 } 6304 6305 PIPE_CONF_CHECK_BOOL(double_wide); 6306 6307 if (dev_priv->dpll.mgr) { 6308 PIPE_CONF_CHECK_P(shared_dpll); 6309 6310 PIPE_CONF_CHECK_X(dpll_hw_state.dpll); 6311 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); 6312 PIPE_CONF_CHECK_X(dpll_hw_state.fp0); 6313 PIPE_CONF_CHECK_X(dpll_hw_state.fp1); 6314 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); 6315 PIPE_CONF_CHECK_X(dpll_hw_state.spll); 6316 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); 6317 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); 6318 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); 6319 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); 6320 PIPE_CONF_CHECK_X(dpll_hw_state.div0); 6321 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); 6322 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); 6323 PIPE_CONF_CHECK_X(dpll_hw_state.pll0); 6324 PIPE_CONF_CHECK_X(dpll_hw_state.pll1); 6325 PIPE_CONF_CHECK_X(dpll_hw_state.pll2); 6326 PIPE_CONF_CHECK_X(dpll_hw_state.pll3); 6327 PIPE_CONF_CHECK_X(dpll_hw_state.pll6); 6328 PIPE_CONF_CHECK_X(dpll_hw_state.pll8); 6329 PIPE_CONF_CHECK_X(dpll_hw_state.pll9); 6330 PIPE_CONF_CHECK_X(dpll_hw_state.pll10); 6331 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); 6332 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl); 6333 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1); 6334 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl); 6335 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0); 6336 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1); 6337 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf); 6338 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock); 6339 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc); 6340 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias); 6341 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias); 6342 } 6343 6344 PIPE_CONF_CHECK_X(dsi_pll.ctrl); 6345 PIPE_CONF_CHECK_X(dsi_pll.div); 6346 6347 if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5) 6348 PIPE_CONF_CHECK_I(pipe_bpp); 6349 6350 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock); 6351 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock); 6352 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); 6353 6354 PIPE_CONF_CHECK_I(min_voltage_level); 6355 6356 if (current_config->has_psr || pipe_config->has_psr) 6357 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable, 6358 ~intel_hdmi_infoframe_enable(DP_SDP_VSC)); 6359 else 6360 PIPE_CONF_CHECK_X(infoframes.enable); 6361 6362 PIPE_CONF_CHECK_X(infoframes.gcp); 6363 PIPE_CONF_CHECK_INFOFRAME(avi); 6364 PIPE_CONF_CHECK_INFOFRAME(spd); 6365 PIPE_CONF_CHECK_INFOFRAME(hdmi); 6366 PIPE_CONF_CHECK_INFOFRAME(drm); 6367 PIPE_CONF_CHECK_DP_VSC_SDP(vsc); 6368 6369 PIPE_CONF_CHECK_X(sync_mode_slaves_mask); 6370 PIPE_CONF_CHECK_I(master_transcoder); 6371 PIPE_CONF_CHECK_X(bigjoiner_pipes); 6372 6373 PIPE_CONF_CHECK_I(dsc.compression_enable); 6374 PIPE_CONF_CHECK_I(dsc.dsc_split); 6375 PIPE_CONF_CHECK_I(dsc.compressed_bpp); 6376 6377 PIPE_CONF_CHECK_BOOL(splitter.enable); 6378 PIPE_CONF_CHECK_I(splitter.link_count); 6379 PIPE_CONF_CHECK_I(splitter.pixel_overlap); 6380 6381 PIPE_CONF_CHECK_I(mst_master_transcoder); 6382 6383 PIPE_CONF_CHECK_BOOL(vrr.enable); 6384 PIPE_CONF_CHECK_I(vrr.vmin); 6385 PIPE_CONF_CHECK_I(vrr.vmax); 6386 PIPE_CONF_CHECK_I(vrr.flipline); 6387 PIPE_CONF_CHECK_I(vrr.pipeline_full); 6388 PIPE_CONF_CHECK_I(vrr.guardband); 6389 6390 #undef PIPE_CONF_CHECK_X 6391 #undef PIPE_CONF_CHECK_I 6392 #undef PIPE_CONF_CHECK_BOOL 6393 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE 6394 #undef PIPE_CONF_CHECK_P 6395 #undef PIPE_CONF_CHECK_FLAGS 6396 #undef PIPE_CONF_CHECK_CLOCK_FUZZY 6397 #undef PIPE_CONF_CHECK_COLOR_LUT 6398 #undef PIPE_CONF_QUIRK 6399 6400 return ret; 6401 } 6402 6403 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, 6404 const struct intel_crtc_state *pipe_config) 6405 { 6406 if (pipe_config->has_pch_encoder) { 6407 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), 6408 &pipe_config->fdi_m_n); 6409 int dotclock = pipe_config->hw.adjusted_mode.crtc_clock; 6410 6411 /* 6412 * FDI already provided one idea for the dotclock. 6413 * Yell if the encoder disagrees. 6414 */ 6415 drm_WARN(&dev_priv->drm, 6416 !intel_fuzzy_clock_check(fdi_dotclock, dotclock), 6417 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", 6418 fdi_dotclock, dotclock); 6419 } 6420 } 6421 6422 static void verify_wm_state(struct intel_crtc *crtc, 6423 struct intel_crtc_state *new_crtc_state) 6424 { 6425 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6426 struct skl_hw_state { 6427 struct skl_ddb_entry ddb[I915_MAX_PLANES]; 6428 struct skl_ddb_entry ddb_y[I915_MAX_PLANES]; 6429 struct skl_pipe_wm wm; 6430 } *hw; 6431 const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal; 6432 int level, max_level = ilk_wm_max_level(dev_priv); 6433 struct intel_plane *plane; 6434 u8 hw_enabled_slices; 6435 6436 if (DISPLAY_VER(dev_priv) < 9 || !new_crtc_state->hw.active) 6437 return; 6438 6439 hw = kzalloc(sizeof(*hw), GFP_KERNEL); 6440 if (!hw) 6441 return; 6442 6443 skl_pipe_wm_get_hw_state(crtc, &hw->wm); 6444 6445 skl_pipe_ddb_get_hw_state(crtc, hw->ddb, hw->ddb_y); 6446 6447 hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv); 6448 6449 if (DISPLAY_VER(dev_priv) >= 11 && 6450 hw_enabled_slices != dev_priv->dbuf.enabled_slices) 6451 drm_err(&dev_priv->drm, 6452 "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n", 6453 dev_priv->dbuf.enabled_slices, 6454 hw_enabled_slices); 6455 6456 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 6457 const struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; 6458 const struct skl_wm_level *hw_wm_level, *sw_wm_level; 6459 6460 /* Watermarks */ 6461 for (level = 0; level <= max_level; level++) { 6462 hw_wm_level = &hw->wm.planes[plane->id].wm[level]; 6463 sw_wm_level = skl_plane_wm_level(sw_wm, plane->id, level); 6464 6465 if (skl_wm_level_equals(hw_wm_level, sw_wm_level)) 6466 continue; 6467 6468 drm_err(&dev_priv->drm, 6469 "[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 6470 plane->base.base.id, plane->base.name, level, 6471 sw_wm_level->enable, 6472 sw_wm_level->blocks, 6473 sw_wm_level->lines, 6474 hw_wm_level->enable, 6475 hw_wm_level->blocks, 6476 hw_wm_level->lines); 6477 } 6478 6479 hw_wm_level = &hw->wm.planes[plane->id].trans_wm; 6480 sw_wm_level = skl_plane_trans_wm(sw_wm, plane->id); 6481 6482 if (!skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 6483 drm_err(&dev_priv->drm, 6484 "[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 6485 plane->base.base.id, plane->base.name, 6486 sw_wm_level->enable, 6487 sw_wm_level->blocks, 6488 sw_wm_level->lines, 6489 hw_wm_level->enable, 6490 hw_wm_level->blocks, 6491 hw_wm_level->lines); 6492 } 6493 6494 hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0; 6495 sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0; 6496 6497 if (HAS_HW_SAGV_WM(dev_priv) && 6498 !skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 6499 drm_err(&dev_priv->drm, 6500 "[PLANE:%d:%s] mismatch in SAGV WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 6501 plane->base.base.id, plane->base.name, 6502 sw_wm_level->enable, 6503 sw_wm_level->blocks, 6504 sw_wm_level->lines, 6505 hw_wm_level->enable, 6506 hw_wm_level->blocks, 6507 hw_wm_level->lines); 6508 } 6509 6510 hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm; 6511 sw_wm_level = &sw_wm->planes[plane->id].sagv.trans_wm; 6512 6513 if (HAS_HW_SAGV_WM(dev_priv) && 6514 !skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 6515 drm_err(&dev_priv->drm, 6516 "[PLANE:%d:%s] mismatch in SAGV trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 6517 plane->base.base.id, plane->base.name, 6518 sw_wm_level->enable, 6519 sw_wm_level->blocks, 6520 sw_wm_level->lines, 6521 hw_wm_level->enable, 6522 hw_wm_level->blocks, 6523 hw_wm_level->lines); 6524 } 6525 6526 /* DDB */ 6527 hw_ddb_entry = &hw->ddb[PLANE_CURSOR]; 6528 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[PLANE_CURSOR]; 6529 6530 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { 6531 drm_err(&dev_priv->drm, 6532 "[PLANE:%d:%s] mismatch in DDB (expected (%u,%u), found (%u,%u))\n", 6533 plane->base.base.id, plane->base.name, 6534 sw_ddb_entry->start, sw_ddb_entry->end, 6535 hw_ddb_entry->start, hw_ddb_entry->end); 6536 } 6537 } 6538 6539 kfree(hw); 6540 } 6541 6542 static void 6543 verify_connector_state(struct intel_atomic_state *state, 6544 struct intel_crtc *crtc) 6545 { 6546 struct drm_connector *connector; 6547 struct drm_connector_state *new_conn_state; 6548 int i; 6549 6550 for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) { 6551 struct drm_encoder *encoder = connector->encoder; 6552 struct intel_crtc_state *crtc_state = NULL; 6553 6554 if (new_conn_state->crtc != &crtc->base) 6555 continue; 6556 6557 if (crtc) 6558 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6559 6560 intel_connector_verify_state(crtc_state, new_conn_state); 6561 6562 I915_STATE_WARN(new_conn_state->best_encoder != encoder, 6563 "connector's atomic encoder doesn't match legacy encoder\n"); 6564 } 6565 } 6566 6567 static void 6568 verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state) 6569 { 6570 struct intel_encoder *encoder; 6571 struct drm_connector *connector; 6572 struct drm_connector_state *old_conn_state, *new_conn_state; 6573 int i; 6574 6575 for_each_intel_encoder(&dev_priv->drm, encoder) { 6576 bool enabled = false, found = false; 6577 enum pipe pipe; 6578 6579 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n", 6580 encoder->base.base.id, 6581 encoder->base.name); 6582 6583 for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state, 6584 new_conn_state, i) { 6585 if (old_conn_state->best_encoder == &encoder->base) 6586 found = true; 6587 6588 if (new_conn_state->best_encoder != &encoder->base) 6589 continue; 6590 found = enabled = true; 6591 6592 I915_STATE_WARN(new_conn_state->crtc != 6593 encoder->base.crtc, 6594 "connector's crtc doesn't match encoder crtc\n"); 6595 } 6596 6597 if (!found) 6598 continue; 6599 6600 I915_STATE_WARN(!!encoder->base.crtc != enabled, 6601 "encoder's enabled state mismatch " 6602 "(expected %i, found %i)\n", 6603 !!encoder->base.crtc, enabled); 6604 6605 if (!encoder->base.crtc) { 6606 bool active; 6607 6608 active = encoder->get_hw_state(encoder, &pipe); 6609 I915_STATE_WARN(active, 6610 "encoder detached but still enabled on pipe %c.\n", 6611 pipe_name(pipe)); 6612 } 6613 } 6614 } 6615 6616 static void 6617 verify_crtc_state(struct intel_crtc *crtc, 6618 struct intel_crtc_state *old_crtc_state, 6619 struct intel_crtc_state *new_crtc_state) 6620 { 6621 struct drm_device *dev = crtc->base.dev; 6622 struct drm_i915_private *dev_priv = to_i915(dev); 6623 struct intel_encoder *encoder; 6624 struct intel_crtc_state *pipe_config = old_crtc_state; 6625 struct drm_atomic_state *state = old_crtc_state->uapi.state; 6626 struct intel_crtc *master_crtc; 6627 6628 __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi); 6629 intel_crtc_free_hw_state(old_crtc_state); 6630 intel_crtc_state_reset(old_crtc_state, crtc); 6631 old_crtc_state->uapi.state = state; 6632 6633 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id, 6634 crtc->base.name); 6635 6636 pipe_config->hw.enable = new_crtc_state->hw.enable; 6637 6638 intel_crtc_get_pipe_config(pipe_config); 6639 6640 /* we keep both pipes enabled on 830 */ 6641 if (IS_I830(dev_priv) && pipe_config->hw.active) 6642 pipe_config->hw.active = new_crtc_state->hw.active; 6643 6644 I915_STATE_WARN(new_crtc_state->hw.active != pipe_config->hw.active, 6645 "crtc active state doesn't match with hw state " 6646 "(expected %i, found %i)\n", 6647 new_crtc_state->hw.active, pipe_config->hw.active); 6648 6649 I915_STATE_WARN(crtc->active != new_crtc_state->hw.active, 6650 "transitional active state does not match atomic hw state " 6651 "(expected %i, found %i)\n", 6652 new_crtc_state->hw.active, crtc->active); 6653 6654 master_crtc = intel_master_crtc(new_crtc_state); 6655 6656 for_each_encoder_on_crtc(dev, &master_crtc->base, encoder) { 6657 enum pipe pipe; 6658 bool active; 6659 6660 active = encoder->get_hw_state(encoder, &pipe); 6661 I915_STATE_WARN(active != new_crtc_state->hw.active, 6662 "[ENCODER:%i] active %i with crtc active %i\n", 6663 encoder->base.base.id, active, 6664 new_crtc_state->hw.active); 6665 6666 I915_STATE_WARN(active && master_crtc->pipe != pipe, 6667 "Encoder connected to wrong pipe %c\n", 6668 pipe_name(pipe)); 6669 6670 if (active) 6671 intel_encoder_get_config(encoder, pipe_config); 6672 } 6673 6674 if (!new_crtc_state->hw.active) 6675 return; 6676 6677 intel_pipe_config_sanity_check(dev_priv, pipe_config); 6678 6679 if (!intel_pipe_config_compare(new_crtc_state, 6680 pipe_config, false)) { 6681 I915_STATE_WARN(1, "pipe state doesn't match!\n"); 6682 intel_dump_pipe_config(pipe_config, NULL, "[hw state]"); 6683 intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]"); 6684 } 6685 } 6686 6687 static void 6688 intel_verify_planes(struct intel_atomic_state *state) 6689 { 6690 struct intel_plane *plane; 6691 const struct intel_plane_state *plane_state; 6692 int i; 6693 6694 for_each_new_intel_plane_in_state(state, plane, 6695 plane_state, i) 6696 assert_plane(plane, plane_state->planar_slave || 6697 plane_state->uapi.visible); 6698 } 6699 6700 static void 6701 verify_single_dpll_state(struct drm_i915_private *dev_priv, 6702 struct intel_shared_dpll *pll, 6703 struct intel_crtc *crtc, 6704 struct intel_crtc_state *new_crtc_state) 6705 { 6706 struct intel_dpll_hw_state dpll_hw_state; 6707 u8 pipe_mask; 6708 bool active; 6709 6710 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); 6711 6712 drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name); 6713 6714 active = intel_dpll_get_hw_state(dev_priv, pll, &dpll_hw_state); 6715 6716 if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) { 6717 I915_STATE_WARN(!pll->on && pll->active_mask, 6718 "pll in active use but not on in sw tracking\n"); 6719 I915_STATE_WARN(pll->on && !pll->active_mask, 6720 "pll is on but not used by any active pipe\n"); 6721 I915_STATE_WARN(pll->on != active, 6722 "pll on state mismatch (expected %i, found %i)\n", 6723 pll->on, active); 6724 } 6725 6726 if (!crtc) { 6727 I915_STATE_WARN(pll->active_mask & ~pll->state.pipe_mask, 6728 "more active pll users than references: 0x%x vs 0x%x\n", 6729 pll->active_mask, pll->state.pipe_mask); 6730 6731 return; 6732 } 6733 6734 pipe_mask = BIT(crtc->pipe); 6735 6736 if (new_crtc_state->hw.active) 6737 I915_STATE_WARN(!(pll->active_mask & pipe_mask), 6738 "pll active mismatch (expected pipe %c in active mask 0x%x)\n", 6739 pipe_name(crtc->pipe), pll->active_mask); 6740 else 6741 I915_STATE_WARN(pll->active_mask & pipe_mask, 6742 "pll active mismatch (didn't expect pipe %c in active mask 0x%x)\n", 6743 pipe_name(crtc->pipe), pll->active_mask); 6744 6745 I915_STATE_WARN(!(pll->state.pipe_mask & pipe_mask), 6746 "pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n", 6747 pipe_mask, pll->state.pipe_mask); 6748 6749 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state, 6750 &dpll_hw_state, 6751 sizeof(dpll_hw_state)), 6752 "pll hw state mismatch\n"); 6753 } 6754 6755 static void 6756 verify_shared_dpll_state(struct intel_crtc *crtc, 6757 struct intel_crtc_state *old_crtc_state, 6758 struct intel_crtc_state *new_crtc_state) 6759 { 6760 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6761 6762 if (new_crtc_state->shared_dpll) 6763 verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state); 6764 6765 if (old_crtc_state->shared_dpll && 6766 old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) { 6767 u8 pipe_mask = BIT(crtc->pipe); 6768 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll; 6769 6770 I915_STATE_WARN(pll->active_mask & pipe_mask, 6771 "pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n", 6772 pipe_name(crtc->pipe), pll->active_mask); 6773 I915_STATE_WARN(pll->state.pipe_mask & pipe_mask, 6774 "pll enabled crtcs mismatch (found %x in enabled mask (0x%x))\n", 6775 pipe_name(crtc->pipe), pll->state.pipe_mask); 6776 } 6777 } 6778 6779 static void 6780 verify_mpllb_state(struct intel_atomic_state *state, 6781 struct intel_crtc_state *new_crtc_state) 6782 { 6783 struct drm_i915_private *i915 = to_i915(state->base.dev); 6784 struct intel_mpllb_state mpllb_hw_state = { 0 }; 6785 struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->mpllb_state; 6786 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 6787 struct intel_encoder *encoder; 6788 6789 if (!IS_DG2(i915)) 6790 return; 6791 6792 if (!new_crtc_state->hw.active) 6793 return; 6794 6795 encoder = intel_get_crtc_new_encoder(state, new_crtc_state); 6796 intel_mpllb_readout_hw_state(encoder, &mpllb_hw_state); 6797 6798 #define MPLLB_CHECK(name) do { \ 6799 if (mpllb_sw_state->name != mpllb_hw_state.name) { \ 6800 pipe_config_mismatch(false, crtc, "MPLLB:" __stringify(name), \ 6801 "(expected 0x%08x, found 0x%08x)", \ 6802 mpllb_sw_state->name, \ 6803 mpllb_hw_state.name); \ 6804 } \ 6805 } while (0) 6806 6807 MPLLB_CHECK(mpllb_cp); 6808 MPLLB_CHECK(mpllb_div); 6809 MPLLB_CHECK(mpllb_div2); 6810 MPLLB_CHECK(mpllb_fracn1); 6811 MPLLB_CHECK(mpllb_fracn2); 6812 MPLLB_CHECK(mpllb_sscen); 6813 MPLLB_CHECK(mpllb_sscstep); 6814 6815 /* 6816 * ref_control is handled by the hardware/firemware and never 6817 * programmed by the software, but the proper values are supplied 6818 * in the bspec for verification purposes. 6819 */ 6820 MPLLB_CHECK(ref_control); 6821 6822 #undef MPLLB_CHECK 6823 } 6824 6825 static void 6826 intel_modeset_verify_crtc(struct intel_crtc *crtc, 6827 struct intel_atomic_state *state, 6828 struct intel_crtc_state *old_crtc_state, 6829 struct intel_crtc_state *new_crtc_state) 6830 { 6831 if (!intel_crtc_needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe) 6832 return; 6833 6834 verify_wm_state(crtc, new_crtc_state); 6835 verify_connector_state(state, crtc); 6836 verify_crtc_state(crtc, old_crtc_state, new_crtc_state); 6837 verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state); 6838 verify_mpllb_state(state, new_crtc_state); 6839 } 6840 6841 static void 6842 verify_disabled_dpll_state(struct drm_i915_private *dev_priv) 6843 { 6844 int i; 6845 6846 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) 6847 verify_single_dpll_state(dev_priv, 6848 &dev_priv->dpll.shared_dplls[i], 6849 NULL, NULL); 6850 } 6851 6852 static void 6853 intel_modeset_verify_disabled(struct drm_i915_private *dev_priv, 6854 struct intel_atomic_state *state) 6855 { 6856 verify_encoder_state(dev_priv, state); 6857 verify_connector_state(state, NULL); 6858 verify_disabled_dpll_state(dev_priv); 6859 } 6860 6861 int intel_modeset_all_pipes(struct intel_atomic_state *state) 6862 { 6863 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6864 struct intel_crtc *crtc; 6865 6866 /* 6867 * Add all pipes to the state, and force 6868 * a modeset on all the active ones. 6869 */ 6870 for_each_intel_crtc(&dev_priv->drm, crtc) { 6871 struct intel_crtc_state *crtc_state; 6872 int ret; 6873 6874 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6875 if (IS_ERR(crtc_state)) 6876 return PTR_ERR(crtc_state); 6877 6878 if (!crtc_state->hw.active || 6879 drm_atomic_crtc_needs_modeset(&crtc_state->uapi)) 6880 continue; 6881 6882 crtc_state->uapi.mode_changed = true; 6883 6884 ret = drm_atomic_add_affected_connectors(&state->base, 6885 &crtc->base); 6886 if (ret) 6887 return ret; 6888 6889 ret = intel_atomic_add_affected_planes(state, crtc); 6890 if (ret) 6891 return ret; 6892 6893 crtc_state->update_planes |= crtc_state->active_planes; 6894 } 6895 6896 return 0; 6897 } 6898 6899 static void 6900 intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state) 6901 { 6902 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 6903 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6904 struct drm_display_mode adjusted_mode; 6905 6906 drm_mode_init(&adjusted_mode, &crtc_state->hw.adjusted_mode); 6907 6908 if (crtc_state->vrr.enable) { 6909 adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax; 6910 adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax; 6911 adjusted_mode.crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state); 6912 crtc->vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state); 6913 } 6914 6915 drm_calc_timestamping_constants(&crtc->base, &adjusted_mode); 6916 6917 crtc->mode_flags = crtc_state->mode_flags; 6918 6919 /* 6920 * The scanline counter increments at the leading edge of hsync. 6921 * 6922 * On most platforms it starts counting from vtotal-1 on the 6923 * first active line. That means the scanline counter value is 6924 * always one less than what we would expect. Ie. just after 6925 * start of vblank, which also occurs at start of hsync (on the 6926 * last active line), the scanline counter will read vblank_start-1. 6927 * 6928 * On gen2 the scanline counter starts counting from 1 instead 6929 * of vtotal-1, so we have to subtract one (or rather add vtotal-1 6930 * to keep the value positive), instead of adding one. 6931 * 6932 * On HSW+ the behaviour of the scanline counter depends on the output 6933 * type. For DP ports it behaves like most other platforms, but on HDMI 6934 * there's an extra 1 line difference. So we need to add two instead of 6935 * one to the value. 6936 * 6937 * On VLV/CHV DSI the scanline counter would appear to increment 6938 * approx. 1/3 of a scanline before start of vblank. Unfortunately 6939 * that means we can't tell whether we're in vblank or not while 6940 * we're on that particular line. We must still set scanline_offset 6941 * to 1 so that the vblank timestamps come out correct when we query 6942 * the scanline counter from within the vblank interrupt handler. 6943 * However if queried just before the start of vblank we'll get an 6944 * answer that's slightly in the future. 6945 */ 6946 if (DISPLAY_VER(dev_priv) == 2) { 6947 int vtotal; 6948 6949 vtotal = adjusted_mode.crtc_vtotal; 6950 if (adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 6951 vtotal /= 2; 6952 6953 crtc->scanline_offset = vtotal - 1; 6954 } else if (HAS_DDI(dev_priv) && 6955 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 6956 crtc->scanline_offset = 2; 6957 } else { 6958 crtc->scanline_offset = 1; 6959 } 6960 } 6961 6962 static void intel_modeset_clear_plls(struct intel_atomic_state *state) 6963 { 6964 struct intel_crtc_state *new_crtc_state; 6965 struct intel_crtc *crtc; 6966 int i; 6967 6968 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6969 if (!intel_crtc_needs_modeset(new_crtc_state)) 6970 continue; 6971 6972 intel_release_shared_dplls(state, crtc); 6973 } 6974 } 6975 6976 /* 6977 * This implements the workaround described in the "notes" section of the mode 6978 * set sequence documentation. When going from no pipes or single pipe to 6979 * multiple pipes, and planes are enabled after the pipe, we need to wait at 6980 * least 2 vblanks on the first pipe before enabling planes on the second pipe. 6981 */ 6982 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state) 6983 { 6984 struct intel_crtc_state *crtc_state; 6985 struct intel_crtc *crtc; 6986 struct intel_crtc_state *first_crtc_state = NULL; 6987 struct intel_crtc_state *other_crtc_state = NULL; 6988 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; 6989 int i; 6990 6991 /* look at all crtc's that are going to be enabled in during modeset */ 6992 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6993 if (!crtc_state->hw.active || 6994 !intel_crtc_needs_modeset(crtc_state)) 6995 continue; 6996 6997 if (first_crtc_state) { 6998 other_crtc_state = crtc_state; 6999 break; 7000 } else { 7001 first_crtc_state = crtc_state; 7002 first_pipe = crtc->pipe; 7003 } 7004 } 7005 7006 /* No workaround needed? */ 7007 if (!first_crtc_state) 7008 return 0; 7009 7010 /* w/a possibly needed, check how many crtc's are already enabled. */ 7011 for_each_intel_crtc(state->base.dev, crtc) { 7012 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 7013 if (IS_ERR(crtc_state)) 7014 return PTR_ERR(crtc_state); 7015 7016 crtc_state->hsw_workaround_pipe = INVALID_PIPE; 7017 7018 if (!crtc_state->hw.active || 7019 intel_crtc_needs_modeset(crtc_state)) 7020 continue; 7021 7022 /* 2 or more enabled crtcs means no need for w/a */ 7023 if (enabled_pipe != INVALID_PIPE) 7024 return 0; 7025 7026 enabled_pipe = crtc->pipe; 7027 } 7028 7029 if (enabled_pipe != INVALID_PIPE) 7030 first_crtc_state->hsw_workaround_pipe = enabled_pipe; 7031 else if (other_crtc_state) 7032 other_crtc_state->hsw_workaround_pipe = first_pipe; 7033 7034 return 0; 7035 } 7036 7037 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 7038 u8 active_pipes) 7039 { 7040 const struct intel_crtc_state *crtc_state; 7041 struct intel_crtc *crtc; 7042 int i; 7043 7044 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7045 if (crtc_state->hw.active) 7046 active_pipes |= BIT(crtc->pipe); 7047 else 7048 active_pipes &= ~BIT(crtc->pipe); 7049 } 7050 7051 return active_pipes; 7052 } 7053 7054 static int intel_modeset_checks(struct intel_atomic_state *state) 7055 { 7056 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7057 7058 state->modeset = true; 7059 7060 if (IS_HASWELL(dev_priv)) 7061 return hsw_mode_set_planes_workaround(state); 7062 7063 return 0; 7064 } 7065 7066 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state, 7067 struct intel_crtc_state *new_crtc_state) 7068 { 7069 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) 7070 return; 7071 7072 new_crtc_state->uapi.mode_changed = false; 7073 new_crtc_state->update_pipe = true; 7074 } 7075 7076 static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state, 7077 struct intel_crtc_state *new_crtc_state) 7078 { 7079 /* 7080 * If we're not doing the full modeset we want to 7081 * keep the current M/N values as they may be 7082 * sufficiently different to the computed values 7083 * to cause problems. 7084 * 7085 * FIXME: should really copy more fuzzy state here 7086 */ 7087 new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n; 7088 new_crtc_state->dp_m_n = old_crtc_state->dp_m_n; 7089 new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2; 7090 new_crtc_state->has_drrs = old_crtc_state->has_drrs; 7091 } 7092 7093 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state, 7094 struct intel_crtc *crtc, 7095 u8 plane_ids_mask) 7096 { 7097 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7098 struct intel_plane *plane; 7099 7100 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 7101 struct intel_plane_state *plane_state; 7102 7103 if ((plane_ids_mask & BIT(plane->id)) == 0) 7104 continue; 7105 7106 plane_state = intel_atomic_get_plane_state(state, plane); 7107 if (IS_ERR(plane_state)) 7108 return PTR_ERR(plane_state); 7109 } 7110 7111 return 0; 7112 } 7113 7114 int intel_atomic_add_affected_planes(struct intel_atomic_state *state, 7115 struct intel_crtc *crtc) 7116 { 7117 const struct intel_crtc_state *old_crtc_state = 7118 intel_atomic_get_old_crtc_state(state, crtc); 7119 const struct intel_crtc_state *new_crtc_state = 7120 intel_atomic_get_new_crtc_state(state, crtc); 7121 7122 return intel_crtc_add_planes_to_state(state, crtc, 7123 old_crtc_state->enabled_planes | 7124 new_crtc_state->enabled_planes); 7125 } 7126 7127 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv) 7128 { 7129 /* See {hsw,vlv,ivb}_plane_ratio() */ 7130 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) || 7131 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) || 7132 IS_IVYBRIDGE(dev_priv); 7133 } 7134 7135 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state, 7136 struct intel_crtc *crtc, 7137 struct intel_crtc *other) 7138 { 7139 const struct intel_plane_state *plane_state; 7140 struct intel_plane *plane; 7141 u8 plane_ids = 0; 7142 int i; 7143 7144 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 7145 if (plane->pipe == crtc->pipe) 7146 plane_ids |= BIT(plane->id); 7147 } 7148 7149 return intel_crtc_add_planes_to_state(state, other, plane_ids); 7150 } 7151 7152 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state) 7153 { 7154 struct drm_i915_private *i915 = to_i915(state->base.dev); 7155 const struct intel_crtc_state *crtc_state; 7156 struct intel_crtc *crtc; 7157 int i; 7158 7159 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7160 struct intel_crtc *other; 7161 7162 for_each_intel_crtc_in_pipe_mask(&i915->drm, other, 7163 crtc_state->bigjoiner_pipes) { 7164 int ret; 7165 7166 if (crtc == other) 7167 continue; 7168 7169 ret = intel_crtc_add_bigjoiner_planes(state, crtc, other); 7170 if (ret) 7171 return ret; 7172 } 7173 } 7174 7175 return 0; 7176 } 7177 7178 static int intel_atomic_check_planes(struct intel_atomic_state *state) 7179 { 7180 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7181 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7182 struct intel_plane_state *plane_state; 7183 struct intel_plane *plane; 7184 struct intel_crtc *crtc; 7185 int i, ret; 7186 7187 ret = icl_add_linked_planes(state); 7188 if (ret) 7189 return ret; 7190 7191 ret = intel_bigjoiner_add_affected_planes(state); 7192 if (ret) 7193 return ret; 7194 7195 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 7196 ret = intel_plane_atomic_check(state, plane); 7197 if (ret) { 7198 drm_dbg_atomic(&dev_priv->drm, 7199 "[PLANE:%d:%s] atomic driver check failed\n", 7200 plane->base.base.id, plane->base.name); 7201 return ret; 7202 } 7203 } 7204 7205 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7206 new_crtc_state, i) { 7207 u8 old_active_planes, new_active_planes; 7208 7209 ret = icl_check_nv12_planes(new_crtc_state); 7210 if (ret) 7211 return ret; 7212 7213 /* 7214 * On some platforms the number of active planes affects 7215 * the planes' minimum cdclk calculation. Add such planes 7216 * to the state before we compute the minimum cdclk. 7217 */ 7218 if (!active_planes_affects_min_cdclk(dev_priv)) 7219 continue; 7220 7221 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 7222 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 7223 7224 if (hweight8(old_active_planes) == hweight8(new_active_planes)) 7225 continue; 7226 7227 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes); 7228 if (ret) 7229 return ret; 7230 } 7231 7232 return 0; 7233 } 7234 7235 static int intel_atomic_check_crtcs(struct intel_atomic_state *state) 7236 { 7237 struct intel_crtc_state *crtc_state; 7238 struct intel_crtc *crtc; 7239 int i; 7240 7241 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7242 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 7243 int ret; 7244 7245 ret = intel_crtc_atomic_check(state, crtc); 7246 if (ret) { 7247 drm_dbg_atomic(&i915->drm, 7248 "[CRTC:%d:%s] atomic driver check failed\n", 7249 crtc->base.base.id, crtc->base.name); 7250 return ret; 7251 } 7252 } 7253 7254 return 0; 7255 } 7256 7257 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, 7258 u8 transcoders) 7259 { 7260 const struct intel_crtc_state *new_crtc_state; 7261 struct intel_crtc *crtc; 7262 int i; 7263 7264 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7265 if (new_crtc_state->hw.enable && 7266 transcoders & BIT(new_crtc_state->cpu_transcoder) && 7267 intel_crtc_needs_modeset(new_crtc_state)) 7268 return true; 7269 } 7270 7271 return false; 7272 } 7273 7274 static bool intel_pipes_need_modeset(struct intel_atomic_state *state, 7275 u8 pipes) 7276 { 7277 const struct intel_crtc_state *new_crtc_state; 7278 struct intel_crtc *crtc; 7279 int i; 7280 7281 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7282 if (new_crtc_state->hw.enable && 7283 pipes & BIT(crtc->pipe) && 7284 intel_crtc_needs_modeset(new_crtc_state)) 7285 return true; 7286 } 7287 7288 return false; 7289 } 7290 7291 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state, 7292 struct intel_crtc *master_crtc) 7293 { 7294 struct drm_i915_private *i915 = to_i915(state->base.dev); 7295 struct intel_crtc_state *master_crtc_state = 7296 intel_atomic_get_new_crtc_state(state, master_crtc); 7297 struct intel_crtc *slave_crtc; 7298 7299 if (!master_crtc_state->bigjoiner_pipes) 7300 return 0; 7301 7302 /* sanity check */ 7303 if (drm_WARN_ON(&i915->drm, 7304 master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state))) 7305 return -EINVAL; 7306 7307 if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) { 7308 drm_dbg_kms(&i915->drm, 7309 "[CRTC:%d:%s] Cannot act as big joiner master " 7310 "(need 0x%x as pipes, only 0x%x possible)\n", 7311 master_crtc->base.base.id, master_crtc->base.name, 7312 master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915)); 7313 return -EINVAL; 7314 } 7315 7316 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 7317 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 7318 struct intel_crtc_state *slave_crtc_state; 7319 int ret; 7320 7321 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc); 7322 if (IS_ERR(slave_crtc_state)) 7323 return PTR_ERR(slave_crtc_state); 7324 7325 /* master being enabled, slave was already configured? */ 7326 if (slave_crtc_state->uapi.enable) { 7327 drm_dbg_kms(&i915->drm, 7328 "[CRTC:%d:%s] Slave is enabled as normal CRTC, but " 7329 "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n", 7330 slave_crtc->base.base.id, slave_crtc->base.name, 7331 master_crtc->base.base.id, master_crtc->base.name); 7332 return -EINVAL; 7333 } 7334 7335 /* 7336 * The state copy logic assumes the master crtc gets processed 7337 * before the slave crtc during the main compute_config loop. 7338 * This works because the crtcs are created in pipe order, 7339 * and the hardware requires master pipe < slave pipe as well. 7340 * Should that change we need to rethink the logic. 7341 */ 7342 if (WARN_ON(drm_crtc_index(&master_crtc->base) > 7343 drm_crtc_index(&slave_crtc->base))) 7344 return -EINVAL; 7345 7346 drm_dbg_kms(&i915->drm, 7347 "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n", 7348 slave_crtc->base.base.id, slave_crtc->base.name, 7349 master_crtc->base.base.id, master_crtc->base.name); 7350 7351 slave_crtc_state->bigjoiner_pipes = 7352 master_crtc_state->bigjoiner_pipes; 7353 7354 ret = copy_bigjoiner_crtc_state_modeset(state, slave_crtc); 7355 if (ret) 7356 return ret; 7357 } 7358 7359 return 0; 7360 } 7361 7362 static void kill_bigjoiner_slave(struct intel_atomic_state *state, 7363 struct intel_crtc *master_crtc) 7364 { 7365 struct drm_i915_private *i915 = to_i915(state->base.dev); 7366 struct intel_crtc_state *master_crtc_state = 7367 intel_atomic_get_new_crtc_state(state, master_crtc); 7368 struct intel_crtc *slave_crtc; 7369 7370 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 7371 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 7372 struct intel_crtc_state *slave_crtc_state = 7373 intel_atomic_get_new_crtc_state(state, slave_crtc); 7374 7375 slave_crtc_state->bigjoiner_pipes = 0; 7376 7377 intel_crtc_copy_uapi_to_hw_state_modeset(state, slave_crtc); 7378 } 7379 7380 master_crtc_state->bigjoiner_pipes = 0; 7381 } 7382 7383 /** 7384 * DOC: asynchronous flip implementation 7385 * 7386 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC 7387 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL. 7388 * Correspondingly, support is currently added for primary plane only. 7389 * 7390 * Async flip can only change the plane surface address, so anything else 7391 * changing is rejected from the intel_async_flip_check_hw() function. 7392 * Once this check is cleared, flip done interrupt is enabled using 7393 * the intel_crtc_enable_flip_done() function. 7394 * 7395 * As soon as the surface address register is written, flip done interrupt is 7396 * generated and the requested events are sent to the usersapce in the interrupt 7397 * handler itself. The timestamp and sequence sent during the flip done event 7398 * correspond to the last vblank and have no relation to the actual time when 7399 * the flip done event was sent. 7400 */ 7401 static int intel_async_flip_check_uapi(struct intel_atomic_state *state, 7402 struct intel_crtc *crtc) 7403 { 7404 struct drm_i915_private *i915 = to_i915(state->base.dev); 7405 const struct intel_crtc_state *new_crtc_state = 7406 intel_atomic_get_new_crtc_state(state, crtc); 7407 const struct intel_plane_state *old_plane_state; 7408 struct intel_plane_state *new_plane_state; 7409 struct intel_plane *plane; 7410 int i; 7411 7412 if (!new_crtc_state->uapi.async_flip) 7413 return 0; 7414 7415 if (!new_crtc_state->uapi.active) { 7416 drm_dbg_kms(&i915->drm, 7417 "[CRTC:%d:%s] not active\n", 7418 crtc->base.base.id, crtc->base.name); 7419 return -EINVAL; 7420 } 7421 7422 if (intel_crtc_needs_modeset(new_crtc_state)) { 7423 drm_dbg_kms(&i915->drm, 7424 "[CRTC:%d:%s] modeset required\n", 7425 crtc->base.base.id, crtc->base.name); 7426 return -EINVAL; 7427 } 7428 7429 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 7430 new_plane_state, i) { 7431 if (plane->pipe != crtc->pipe) 7432 continue; 7433 7434 /* 7435 * TODO: Async flip is only supported through the page flip IOCTL 7436 * as of now. So support currently added for primary plane only. 7437 * Support for other planes on platforms on which supports 7438 * this(vlv/chv and icl+) should be added when async flip is 7439 * enabled in the atomic IOCTL path. 7440 */ 7441 if (!plane->async_flip) { 7442 drm_dbg_kms(&i915->drm, 7443 "[PLANE:%d:%s] async flip not supported\n", 7444 plane->base.base.id, plane->base.name); 7445 return -EINVAL; 7446 } 7447 7448 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) { 7449 drm_dbg_kms(&i915->drm, 7450 "[PLANE:%d:%s] no old or new framebuffer\n", 7451 plane->base.base.id, plane->base.name); 7452 return -EINVAL; 7453 } 7454 } 7455 7456 return 0; 7457 } 7458 7459 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc) 7460 { 7461 struct drm_i915_private *i915 = to_i915(state->base.dev); 7462 const struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7463 const struct intel_plane_state *new_plane_state, *old_plane_state; 7464 struct intel_plane *plane; 7465 int i; 7466 7467 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 7468 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 7469 7470 if (!new_crtc_state->uapi.async_flip) 7471 return 0; 7472 7473 if (!new_crtc_state->hw.active) { 7474 drm_dbg_kms(&i915->drm, 7475 "[CRTC:%d:%s] not active\n", 7476 crtc->base.base.id, crtc->base.name); 7477 return -EINVAL; 7478 } 7479 7480 if (intel_crtc_needs_modeset(new_crtc_state)) { 7481 drm_dbg_kms(&i915->drm, 7482 "[CRTC:%d:%s] modeset required\n", 7483 crtc->base.base.id, crtc->base.name); 7484 return -EINVAL; 7485 } 7486 7487 if (old_crtc_state->active_planes != new_crtc_state->active_planes) { 7488 drm_dbg_kms(&i915->drm, 7489 "[CRTC:%d:%s] Active planes cannot be in async flip\n", 7490 crtc->base.base.id, crtc->base.name); 7491 return -EINVAL; 7492 } 7493 7494 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 7495 new_plane_state, i) { 7496 if (plane->pipe != crtc->pipe) 7497 continue; 7498 7499 /* 7500 * Only async flip capable planes should be in the state 7501 * if we're really about to ask the hardware to perform 7502 * an async flip. We should never get this far otherwise. 7503 */ 7504 if (drm_WARN_ON(&i915->drm, 7505 new_crtc_state->do_async_flip && !plane->async_flip)) 7506 return -EINVAL; 7507 7508 /* 7509 * Only check async flip capable planes other planes 7510 * may be involved in the initial commit due to 7511 * the wm0/ddb optimization. 7512 * 7513 * TODO maybe should track which planes actually 7514 * were requested to do the async flip... 7515 */ 7516 if (!plane->async_flip) 7517 continue; 7518 7519 /* 7520 * FIXME: This check is kept generic for all platforms. 7521 * Need to verify this for all gen9 platforms to enable 7522 * this selectively if required. 7523 */ 7524 switch (new_plane_state->hw.fb->modifier) { 7525 case I915_FORMAT_MOD_X_TILED: 7526 case I915_FORMAT_MOD_Y_TILED: 7527 case I915_FORMAT_MOD_Yf_TILED: 7528 case I915_FORMAT_MOD_4_TILED: 7529 break; 7530 default: 7531 drm_dbg_kms(&i915->drm, 7532 "[PLANE:%d:%s] Modifier does not support async flips\n", 7533 plane->base.base.id, plane->base.name); 7534 return -EINVAL; 7535 } 7536 7537 if (new_plane_state->hw.fb->format->num_planes > 1) { 7538 drm_dbg_kms(&i915->drm, 7539 "[PLANE:%d:%s] Planar formats do not support async flips\n", 7540 plane->base.base.id, plane->base.name); 7541 return -EINVAL; 7542 } 7543 7544 if (old_plane_state->view.color_plane[0].mapping_stride != 7545 new_plane_state->view.color_plane[0].mapping_stride) { 7546 drm_dbg_kms(&i915->drm, 7547 "[PLANE:%d:%s] Stride cannot be changed in async flip\n", 7548 plane->base.base.id, plane->base.name); 7549 return -EINVAL; 7550 } 7551 7552 if (old_plane_state->hw.fb->modifier != 7553 new_plane_state->hw.fb->modifier) { 7554 drm_dbg_kms(&i915->drm, 7555 "[PLANE:%d:%s] Modifier cannot be changed in async flip\n", 7556 plane->base.base.id, plane->base.name); 7557 return -EINVAL; 7558 } 7559 7560 if (old_plane_state->hw.fb->format != 7561 new_plane_state->hw.fb->format) { 7562 drm_dbg_kms(&i915->drm, 7563 "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n", 7564 plane->base.base.id, plane->base.name); 7565 return -EINVAL; 7566 } 7567 7568 if (old_plane_state->hw.rotation != 7569 new_plane_state->hw.rotation) { 7570 drm_dbg_kms(&i915->drm, 7571 "[PLANE:%d:%s] Rotation cannot be changed in async flip\n", 7572 plane->base.base.id, plane->base.name); 7573 return -EINVAL; 7574 } 7575 7576 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) || 7577 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) { 7578 drm_dbg_kms(&i915->drm, 7579 "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n", 7580 plane->base.base.id, plane->base.name); 7581 return -EINVAL; 7582 } 7583 7584 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) { 7585 drm_dbg_kms(&i915->drm, 7586 "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n", 7587 plane->base.base.id, plane->base.name); 7588 return -EINVAL; 7589 } 7590 7591 if (old_plane_state->hw.pixel_blend_mode != 7592 new_plane_state->hw.pixel_blend_mode) { 7593 drm_dbg_kms(&i915->drm, 7594 "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n", 7595 plane->base.base.id, plane->base.name); 7596 return -EINVAL; 7597 } 7598 7599 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) { 7600 drm_dbg_kms(&i915->drm, 7601 "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n", 7602 plane->base.base.id, plane->base.name); 7603 return -EINVAL; 7604 } 7605 7606 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) { 7607 drm_dbg_kms(&i915->drm, 7608 "[PLANE:%d:%s] Color range cannot be changed in async flip\n", 7609 plane->base.base.id, plane->base.name); 7610 return -EINVAL; 7611 } 7612 7613 /* plane decryption is allow to change only in synchronous flips */ 7614 if (old_plane_state->decrypt != new_plane_state->decrypt) { 7615 drm_dbg_kms(&i915->drm, 7616 "[PLANE:%d:%s] Decryption cannot be changed in async flip\n", 7617 plane->base.base.id, plane->base.name); 7618 return -EINVAL; 7619 } 7620 } 7621 7622 return 0; 7623 } 7624 7625 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state) 7626 { 7627 struct drm_i915_private *i915 = to_i915(state->base.dev); 7628 struct intel_crtc_state *crtc_state; 7629 struct intel_crtc *crtc; 7630 u8 affected_pipes = 0; 7631 u8 modeset_pipes = 0; 7632 int i; 7633 7634 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7635 affected_pipes |= crtc_state->bigjoiner_pipes; 7636 if (intel_crtc_needs_modeset(crtc_state)) 7637 modeset_pipes |= crtc_state->bigjoiner_pipes; 7638 } 7639 7640 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) { 7641 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 7642 if (IS_ERR(crtc_state)) 7643 return PTR_ERR(crtc_state); 7644 } 7645 7646 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) { 7647 int ret; 7648 7649 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 7650 7651 crtc_state->uapi.mode_changed = true; 7652 7653 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); 7654 if (ret) 7655 return ret; 7656 7657 ret = intel_atomic_add_affected_planes(state, crtc); 7658 if (ret) 7659 return ret; 7660 } 7661 7662 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7663 /* Kill old bigjoiner link, we may re-establish afterwards */ 7664 if (intel_crtc_needs_modeset(crtc_state) && 7665 intel_crtc_is_bigjoiner_master(crtc_state)) 7666 kill_bigjoiner_slave(state, crtc); 7667 } 7668 7669 return 0; 7670 } 7671 7672 /** 7673 * intel_atomic_check - validate state object 7674 * @dev: drm device 7675 * @_state: state to validate 7676 */ 7677 static int intel_atomic_check(struct drm_device *dev, 7678 struct drm_atomic_state *_state) 7679 { 7680 struct drm_i915_private *dev_priv = to_i915(dev); 7681 struct intel_atomic_state *state = to_intel_atomic_state(_state); 7682 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7683 struct intel_crtc *crtc; 7684 int ret, i; 7685 bool any_ms = false; 7686 7687 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7688 new_crtc_state, i) { 7689 if (new_crtc_state->inherited != old_crtc_state->inherited) 7690 new_crtc_state->uapi.mode_changed = true; 7691 7692 if (new_crtc_state->uapi.scaling_filter != 7693 old_crtc_state->uapi.scaling_filter) 7694 new_crtc_state->uapi.mode_changed = true; 7695 } 7696 7697 intel_vrr_check_modeset(state); 7698 7699 ret = drm_atomic_helper_check_modeset(dev, &state->base); 7700 if (ret) 7701 goto fail; 7702 7703 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7704 ret = intel_async_flip_check_uapi(state, crtc); 7705 if (ret) 7706 return ret; 7707 } 7708 7709 ret = intel_bigjoiner_add_affected_crtcs(state); 7710 if (ret) 7711 goto fail; 7712 7713 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7714 new_crtc_state, i) { 7715 if (!intel_crtc_needs_modeset(new_crtc_state)) { 7716 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 7717 copy_bigjoiner_crtc_state_nomodeset(state, crtc); 7718 else 7719 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 7720 continue; 7721 } 7722 7723 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) { 7724 drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable); 7725 continue; 7726 } 7727 7728 ret = intel_crtc_prepare_cleared_state(state, crtc); 7729 if (ret) 7730 goto fail; 7731 7732 if (!new_crtc_state->hw.enable) 7733 continue; 7734 7735 ret = intel_modeset_pipe_config(state, new_crtc_state); 7736 if (ret) 7737 goto fail; 7738 7739 ret = intel_atomic_check_bigjoiner(state, crtc); 7740 if (ret) 7741 goto fail; 7742 } 7743 7744 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7745 new_crtc_state, i) { 7746 if (!intel_crtc_needs_modeset(new_crtc_state)) 7747 continue; 7748 7749 ret = intel_modeset_pipe_config_late(new_crtc_state); 7750 if (ret) 7751 goto fail; 7752 7753 intel_crtc_check_fastset(old_crtc_state, new_crtc_state); 7754 } 7755 7756 /** 7757 * Check if fastset is allowed by external dependencies like other 7758 * pipes and transcoders. 7759 * 7760 * Right now it only forces a fullmodeset when the MST master 7761 * transcoder did not changed but the pipe of the master transcoder 7762 * needs a fullmodeset so all slaves also needs to do a fullmodeset or 7763 * in case of port synced crtcs, if one of the synced crtcs 7764 * needs a full modeset, all other synced crtcs should be 7765 * forced a full modeset. 7766 */ 7767 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7768 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state)) 7769 continue; 7770 7771 if (intel_dp_mst_is_slave_trans(new_crtc_state)) { 7772 enum transcoder master = new_crtc_state->mst_master_transcoder; 7773 7774 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) { 7775 new_crtc_state->uapi.mode_changed = true; 7776 new_crtc_state->update_pipe = false; 7777 } 7778 } 7779 7780 if (is_trans_port_sync_mode(new_crtc_state)) { 7781 u8 trans = new_crtc_state->sync_mode_slaves_mask; 7782 7783 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER) 7784 trans |= BIT(new_crtc_state->master_transcoder); 7785 7786 if (intel_cpu_transcoders_need_modeset(state, trans)) { 7787 new_crtc_state->uapi.mode_changed = true; 7788 new_crtc_state->update_pipe = false; 7789 } 7790 } 7791 7792 if (new_crtc_state->bigjoiner_pipes) { 7793 if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) { 7794 new_crtc_state->uapi.mode_changed = true; 7795 new_crtc_state->update_pipe = false; 7796 } 7797 } 7798 } 7799 7800 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7801 new_crtc_state, i) { 7802 if (intel_crtc_needs_modeset(new_crtc_state)) { 7803 any_ms = true; 7804 continue; 7805 } 7806 7807 if (!new_crtc_state->update_pipe) 7808 continue; 7809 7810 intel_crtc_copy_fastset(old_crtc_state, new_crtc_state); 7811 } 7812 7813 if (any_ms && !check_digital_port_conflicts(state)) { 7814 drm_dbg_kms(&dev_priv->drm, 7815 "rejecting conflicting digital port configuration\n"); 7816 ret = -EINVAL; 7817 goto fail; 7818 } 7819 7820 ret = drm_dp_mst_atomic_check(&state->base); 7821 if (ret) 7822 goto fail; 7823 7824 ret = intel_atomic_check_planes(state); 7825 if (ret) 7826 goto fail; 7827 7828 ret = intel_compute_global_watermarks(state); 7829 if (ret) 7830 goto fail; 7831 7832 ret = intel_bw_atomic_check(state); 7833 if (ret) 7834 goto fail; 7835 7836 ret = intel_cdclk_atomic_check(state, &any_ms); 7837 if (ret) 7838 goto fail; 7839 7840 if (intel_any_crtc_needs_modeset(state)) 7841 any_ms = true; 7842 7843 if (any_ms) { 7844 ret = intel_modeset_checks(state); 7845 if (ret) 7846 goto fail; 7847 7848 ret = intel_modeset_calc_cdclk(state); 7849 if (ret) 7850 return ret; 7851 7852 intel_modeset_clear_plls(state); 7853 } 7854 7855 ret = intel_atomic_check_crtcs(state); 7856 if (ret) 7857 goto fail; 7858 7859 ret = intel_fbc_atomic_check(state); 7860 if (ret) 7861 goto fail; 7862 7863 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7864 new_crtc_state, i) { 7865 ret = intel_async_flip_check_hw(state, crtc); 7866 if (ret) 7867 goto fail; 7868 7869 if (!intel_crtc_needs_modeset(new_crtc_state) && 7870 !new_crtc_state->update_pipe) 7871 continue; 7872 7873 intel_dump_pipe_config(new_crtc_state, state, 7874 intel_crtc_needs_modeset(new_crtc_state) ? 7875 "[modeset]" : "[fastset]"); 7876 } 7877 7878 return 0; 7879 7880 fail: 7881 if (ret == -EDEADLK) 7882 return ret; 7883 7884 /* 7885 * FIXME would probably be nice to know which crtc specifically 7886 * caused the failure, in cases where we can pinpoint it. 7887 */ 7888 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7889 new_crtc_state, i) 7890 intel_dump_pipe_config(new_crtc_state, state, "[failed]"); 7891 7892 return ret; 7893 } 7894 7895 static int intel_atomic_prepare_commit(struct intel_atomic_state *state) 7896 { 7897 struct intel_crtc_state *crtc_state; 7898 struct intel_crtc *crtc; 7899 int i, ret; 7900 7901 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base); 7902 if (ret < 0) 7903 return ret; 7904 7905 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7906 bool mode_changed = intel_crtc_needs_modeset(crtc_state); 7907 7908 if (mode_changed || crtc_state->update_pipe || 7909 crtc_state->uapi.color_mgmt_changed) { 7910 intel_dsb_prepare(crtc_state); 7911 } 7912 } 7913 7914 return 0; 7915 } 7916 7917 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 7918 struct intel_crtc_state *crtc_state) 7919 { 7920 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 7921 7922 if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes) 7923 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 7924 7925 if (crtc_state->has_pch_encoder) { 7926 enum pipe pch_transcoder = 7927 intel_crtc_pch_transcoder(crtc); 7928 7929 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true); 7930 } 7931 } 7932 7933 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, 7934 const struct intel_crtc_state *new_crtc_state) 7935 { 7936 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 7937 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 7938 7939 /* 7940 * Update pipe size and adjust fitter if needed: the reason for this is 7941 * that in compute_mode_changes we check the native mode (not the pfit 7942 * mode) to see if we can flip rather than do a full mode set. In the 7943 * fastboot case, we'll flip, but if we don't update the pipesrc and 7944 * pfit state, we'll end up with a big fb scanned out into the wrong 7945 * sized surface. 7946 */ 7947 intel_set_pipe_src_size(new_crtc_state); 7948 7949 /* on skylake this is done by detaching scalers */ 7950 if (DISPLAY_VER(dev_priv) >= 9) { 7951 if (new_crtc_state->pch_pfit.enabled) 7952 skl_pfit_enable(new_crtc_state); 7953 } else if (HAS_PCH_SPLIT(dev_priv)) { 7954 if (new_crtc_state->pch_pfit.enabled) 7955 ilk_pfit_enable(new_crtc_state); 7956 else if (old_crtc_state->pch_pfit.enabled) 7957 ilk_pfit_disable(old_crtc_state); 7958 } 7959 7960 /* 7961 * The register is supposedly single buffered so perhaps 7962 * not 100% correct to do this here. But SKL+ calculate 7963 * this based on the adjust pixel rate so pfit changes do 7964 * affect it and so it must be updated for fastsets. 7965 * HSW/BDW only really need this here for fastboot, after 7966 * that the value should not change without a full modeset. 7967 */ 7968 if (DISPLAY_VER(dev_priv) >= 9 || 7969 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 7970 hsw_set_linetime_wm(new_crtc_state); 7971 } 7972 7973 static void commit_pipe_pre_planes(struct intel_atomic_state *state, 7974 struct intel_crtc *crtc) 7975 { 7976 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7977 const struct intel_crtc_state *old_crtc_state = 7978 intel_atomic_get_old_crtc_state(state, crtc); 7979 const struct intel_crtc_state *new_crtc_state = 7980 intel_atomic_get_new_crtc_state(state, crtc); 7981 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 7982 7983 /* 7984 * During modesets pipe configuration was programmed as the 7985 * CRTC was enabled. 7986 */ 7987 if (!modeset) { 7988 if (new_crtc_state->uapi.color_mgmt_changed || 7989 new_crtc_state->update_pipe) 7990 intel_color_commit_arm(new_crtc_state); 7991 7992 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 7993 bdw_set_pipemisc(new_crtc_state); 7994 7995 if (new_crtc_state->update_pipe) 7996 intel_pipe_fastset(old_crtc_state, new_crtc_state); 7997 } 7998 7999 intel_psr2_program_trans_man_trk_ctl(new_crtc_state); 8000 8001 intel_atomic_update_watermarks(state, crtc); 8002 } 8003 8004 static void commit_pipe_post_planes(struct intel_atomic_state *state, 8005 struct intel_crtc *crtc) 8006 { 8007 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8008 const struct intel_crtc_state *new_crtc_state = 8009 intel_atomic_get_new_crtc_state(state, crtc); 8010 8011 /* 8012 * Disable the scaler(s) after the plane(s) so that we don't 8013 * get a catastrophic underrun even if the two operations 8014 * end up happening in two different frames. 8015 */ 8016 if (DISPLAY_VER(dev_priv) >= 9 && 8017 !intel_crtc_needs_modeset(new_crtc_state)) 8018 skl_detach_scalers(new_crtc_state); 8019 } 8020 8021 static void intel_enable_crtc(struct intel_atomic_state *state, 8022 struct intel_crtc *crtc) 8023 { 8024 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8025 const struct intel_crtc_state *new_crtc_state = 8026 intel_atomic_get_new_crtc_state(state, crtc); 8027 8028 if (!intel_crtc_needs_modeset(new_crtc_state)) 8029 return; 8030 8031 intel_crtc_update_active_timings(new_crtc_state); 8032 8033 dev_priv->display->crtc_enable(state, crtc); 8034 8035 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 8036 return; 8037 8038 /* vblanks work again, re-enable pipe CRC. */ 8039 intel_crtc_enable_pipe_crc(crtc); 8040 } 8041 8042 static void intel_update_crtc(struct intel_atomic_state *state, 8043 struct intel_crtc *crtc) 8044 { 8045 struct drm_i915_private *i915 = to_i915(state->base.dev); 8046 const struct intel_crtc_state *old_crtc_state = 8047 intel_atomic_get_old_crtc_state(state, crtc); 8048 struct intel_crtc_state *new_crtc_state = 8049 intel_atomic_get_new_crtc_state(state, crtc); 8050 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 8051 8052 if (!modeset) { 8053 if (new_crtc_state->preload_luts && 8054 (new_crtc_state->uapi.color_mgmt_changed || 8055 new_crtc_state->update_pipe)) 8056 intel_color_load_luts(new_crtc_state); 8057 8058 intel_pre_plane_update(state, crtc); 8059 8060 if (new_crtc_state->update_pipe) 8061 intel_encoders_update_pipe(state, crtc); 8062 8063 if (DISPLAY_VER(i915) >= 11 && 8064 new_crtc_state->update_pipe) 8065 icl_set_pipe_chicken(new_crtc_state); 8066 } 8067 8068 intel_fbc_update(state, crtc); 8069 8070 if (!modeset && 8071 (new_crtc_state->uapi.color_mgmt_changed || 8072 new_crtc_state->update_pipe)) 8073 intel_color_commit_noarm(new_crtc_state); 8074 8075 intel_crtc_planes_update_noarm(state, crtc); 8076 8077 /* Perform vblank evasion around commit operation */ 8078 intel_pipe_update_start(new_crtc_state); 8079 8080 commit_pipe_pre_planes(state, crtc); 8081 8082 intel_crtc_planes_update_arm(state, crtc); 8083 8084 commit_pipe_post_planes(state, crtc); 8085 8086 intel_pipe_update_end(new_crtc_state); 8087 8088 /* 8089 * We usually enable FIFO underrun interrupts as part of the 8090 * CRTC enable sequence during modesets. But when we inherit a 8091 * valid pipe configuration from the BIOS we need to take care 8092 * of enabling them on the CRTC's first fastset. 8093 */ 8094 if (new_crtc_state->update_pipe && !modeset && 8095 old_crtc_state->inherited) 8096 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state); 8097 } 8098 8099 static void intel_old_crtc_state_disables(struct intel_atomic_state *state, 8100 struct intel_crtc_state *old_crtc_state, 8101 struct intel_crtc_state *new_crtc_state, 8102 struct intel_crtc *crtc) 8103 { 8104 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8105 8106 /* 8107 * We need to disable pipe CRC before disabling the pipe, 8108 * or we race against vblank off. 8109 */ 8110 intel_crtc_disable_pipe_crc(crtc); 8111 8112 dev_priv->display->crtc_disable(state, crtc); 8113 crtc->active = false; 8114 intel_fbc_disable(crtc); 8115 intel_disable_shared_dpll(old_crtc_state); 8116 8117 /* FIXME unify this for all platforms */ 8118 if (!new_crtc_state->hw.active && 8119 !HAS_GMCH(dev_priv)) 8120 intel_initial_watermarks(state, crtc); 8121 } 8122 8123 static void intel_commit_modeset_disables(struct intel_atomic_state *state) 8124 { 8125 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 8126 struct intel_crtc *crtc; 8127 u32 handled = 0; 8128 int i; 8129 8130 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8131 new_crtc_state, i) { 8132 if (!intel_crtc_needs_modeset(new_crtc_state)) 8133 continue; 8134 8135 if (!old_crtc_state->hw.active) 8136 continue; 8137 8138 intel_pre_plane_update(state, crtc); 8139 intel_crtc_disable_planes(state, crtc); 8140 } 8141 8142 /* Only disable port sync and MST slaves */ 8143 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8144 new_crtc_state, i) { 8145 if (!intel_crtc_needs_modeset(new_crtc_state)) 8146 continue; 8147 8148 if (!old_crtc_state->hw.active) 8149 continue; 8150 8151 /* In case of Transcoder port Sync master slave CRTCs can be 8152 * assigned in any order and we need to make sure that 8153 * slave CRTCs are disabled first and then master CRTC since 8154 * Slave vblanks are masked till Master Vblanks. 8155 */ 8156 if (!is_trans_port_sync_slave(old_crtc_state) && 8157 !intel_dp_mst_is_slave_trans(old_crtc_state) && 8158 !intel_crtc_is_bigjoiner_slave(old_crtc_state)) 8159 continue; 8160 8161 intel_old_crtc_state_disables(state, old_crtc_state, 8162 new_crtc_state, crtc); 8163 handled |= BIT(crtc->pipe); 8164 } 8165 8166 /* Disable everything else left on */ 8167 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8168 new_crtc_state, i) { 8169 if (!intel_crtc_needs_modeset(new_crtc_state) || 8170 (handled & BIT(crtc->pipe))) 8171 continue; 8172 8173 if (!old_crtc_state->hw.active) 8174 continue; 8175 8176 intel_old_crtc_state_disables(state, old_crtc_state, 8177 new_crtc_state, crtc); 8178 } 8179 } 8180 8181 static void intel_commit_modeset_enables(struct intel_atomic_state *state) 8182 { 8183 struct intel_crtc_state *new_crtc_state; 8184 struct intel_crtc *crtc; 8185 int i; 8186 8187 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8188 if (!new_crtc_state->hw.active) 8189 continue; 8190 8191 intel_enable_crtc(state, crtc); 8192 intel_update_crtc(state, crtc); 8193 } 8194 } 8195 8196 static void skl_commit_modeset_enables(struct intel_atomic_state *state) 8197 { 8198 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8199 struct intel_crtc *crtc; 8200 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 8201 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; 8202 u8 update_pipes = 0, modeset_pipes = 0; 8203 int i; 8204 8205 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 8206 enum pipe pipe = crtc->pipe; 8207 8208 if (!new_crtc_state->hw.active) 8209 continue; 8210 8211 /* ignore allocations for crtc's that have been turned off. */ 8212 if (!intel_crtc_needs_modeset(new_crtc_state)) { 8213 entries[pipe] = old_crtc_state->wm.skl.ddb; 8214 update_pipes |= BIT(pipe); 8215 } else { 8216 modeset_pipes |= BIT(pipe); 8217 } 8218 } 8219 8220 /* 8221 * Whenever the number of active pipes changes, we need to make sure we 8222 * update the pipes in the right order so that their ddb allocations 8223 * never overlap with each other between CRTC updates. Otherwise we'll 8224 * cause pipe underruns and other bad stuff. 8225 * 8226 * So first lets enable all pipes that do not need a fullmodeset as 8227 * those don't have any external dependency. 8228 */ 8229 while (update_pipes) { 8230 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8231 new_crtc_state, i) { 8232 enum pipe pipe = crtc->pipe; 8233 8234 if ((update_pipes & BIT(pipe)) == 0) 8235 continue; 8236 8237 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 8238 entries, I915_MAX_PIPES, pipe)) 8239 continue; 8240 8241 entries[pipe] = new_crtc_state->wm.skl.ddb; 8242 update_pipes &= ~BIT(pipe); 8243 8244 intel_update_crtc(state, crtc); 8245 8246 /* 8247 * If this is an already active pipe, it's DDB changed, 8248 * and this isn't the last pipe that needs updating 8249 * then we need to wait for a vblank to pass for the 8250 * new ddb allocation to take effect. 8251 */ 8252 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, 8253 &old_crtc_state->wm.skl.ddb) && 8254 (update_pipes | modeset_pipes)) 8255 intel_crtc_wait_for_next_vblank(crtc); 8256 } 8257 } 8258 8259 update_pipes = modeset_pipes; 8260 8261 /* 8262 * Enable all pipes that needs a modeset and do not depends on other 8263 * pipes 8264 */ 8265 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8266 enum pipe pipe = crtc->pipe; 8267 8268 if ((modeset_pipes & BIT(pipe)) == 0) 8269 continue; 8270 8271 if (intel_dp_mst_is_slave_trans(new_crtc_state) || 8272 is_trans_port_sync_master(new_crtc_state) || 8273 intel_crtc_is_bigjoiner_master(new_crtc_state)) 8274 continue; 8275 8276 modeset_pipes &= ~BIT(pipe); 8277 8278 intel_enable_crtc(state, crtc); 8279 } 8280 8281 /* 8282 * Then we enable all remaining pipes that depend on other 8283 * pipes: MST slaves and port sync masters, big joiner master 8284 */ 8285 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8286 enum pipe pipe = crtc->pipe; 8287 8288 if ((modeset_pipes & BIT(pipe)) == 0) 8289 continue; 8290 8291 modeset_pipes &= ~BIT(pipe); 8292 8293 intel_enable_crtc(state, crtc); 8294 } 8295 8296 /* 8297 * Finally we do the plane updates/etc. for all pipes that got enabled. 8298 */ 8299 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8300 enum pipe pipe = crtc->pipe; 8301 8302 if ((update_pipes & BIT(pipe)) == 0) 8303 continue; 8304 8305 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 8306 entries, I915_MAX_PIPES, pipe)); 8307 8308 entries[pipe] = new_crtc_state->wm.skl.ddb; 8309 update_pipes &= ~BIT(pipe); 8310 8311 intel_update_crtc(state, crtc); 8312 } 8313 8314 drm_WARN_ON(&dev_priv->drm, modeset_pipes); 8315 drm_WARN_ON(&dev_priv->drm, update_pipes); 8316 } 8317 8318 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) 8319 { 8320 struct intel_atomic_state *state, *next; 8321 struct llist_node *freed; 8322 8323 freed = llist_del_all(&dev_priv->atomic_helper.free_list); 8324 llist_for_each_entry_safe(state, next, freed, freed) 8325 drm_atomic_state_put(&state->base); 8326 } 8327 8328 static void intel_atomic_helper_free_state_worker(struct work_struct *work) 8329 { 8330 struct drm_i915_private *dev_priv = 8331 container_of(work, typeof(*dev_priv), atomic_helper.free_work); 8332 8333 intel_atomic_helper_free_state(dev_priv); 8334 } 8335 8336 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) 8337 { 8338 struct wait_queue_entry wait_fence, wait_reset; 8339 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); 8340 8341 init_wait_entry(&wait_fence, 0); 8342 init_wait_entry(&wait_reset, 0); 8343 for (;;) { 8344 prepare_to_wait(&intel_state->commit_ready.wait, 8345 &wait_fence, TASK_UNINTERRUPTIBLE); 8346 prepare_to_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 8347 I915_RESET_MODESET), 8348 &wait_reset, TASK_UNINTERRUPTIBLE); 8349 8350 8351 if (i915_sw_fence_done(&intel_state->commit_ready) || 8352 test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags)) 8353 break; 8354 8355 schedule(); 8356 } 8357 finish_wait(&intel_state->commit_ready.wait, &wait_fence); 8358 finish_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 8359 I915_RESET_MODESET), 8360 &wait_reset); 8361 } 8362 8363 static void intel_cleanup_dsbs(struct intel_atomic_state *state) 8364 { 8365 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 8366 struct intel_crtc *crtc; 8367 int i; 8368 8369 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8370 new_crtc_state, i) 8371 intel_dsb_cleanup(old_crtc_state); 8372 } 8373 8374 static void intel_atomic_cleanup_work(struct work_struct *work) 8375 { 8376 struct intel_atomic_state *state = 8377 container_of(work, struct intel_atomic_state, base.commit_work); 8378 struct drm_i915_private *i915 = to_i915(state->base.dev); 8379 8380 intel_cleanup_dsbs(state); 8381 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base); 8382 drm_atomic_helper_commit_cleanup_done(&state->base); 8383 drm_atomic_state_put(&state->base); 8384 8385 intel_atomic_helper_free_state(i915); 8386 } 8387 8388 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state) 8389 { 8390 struct drm_i915_private *i915 = to_i915(state->base.dev); 8391 struct intel_plane *plane; 8392 struct intel_plane_state *plane_state; 8393 int i; 8394 8395 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 8396 struct drm_framebuffer *fb = plane_state->hw.fb; 8397 int cc_plane; 8398 int ret; 8399 8400 if (!fb) 8401 continue; 8402 8403 cc_plane = intel_fb_rc_ccs_cc_plane(fb); 8404 if (cc_plane < 0) 8405 continue; 8406 8407 /* 8408 * The layout of the fast clear color value expected by HW 8409 * (the DRM ABI requiring this value to be located in fb at 8410 * offset 0 of cc plane, plane #2 previous generations or 8411 * plane #1 for flat ccs): 8412 * - 4 x 4 bytes per-channel value 8413 * (in surface type specific float/int format provided by the fb user) 8414 * - 8 bytes native color value used by the display 8415 * (converted/written by GPU during a fast clear operation using the 8416 * above per-channel values) 8417 * 8418 * The commit's FB prepare hook already ensured that FB obj is pinned and the 8419 * caller made sure that the object is synced wrt. the related color clear value 8420 * GPU write on it. 8421 */ 8422 ret = i915_gem_object_read_from_page(intel_fb_obj(fb), 8423 fb->offsets[cc_plane] + 16, 8424 &plane_state->ccval, 8425 sizeof(plane_state->ccval)); 8426 /* The above could only fail if the FB obj has an unexpected backing store type. */ 8427 drm_WARN_ON(&i915->drm, ret); 8428 } 8429 } 8430 8431 static void intel_atomic_commit_tail(struct intel_atomic_state *state) 8432 { 8433 struct drm_device *dev = state->base.dev; 8434 struct drm_i915_private *dev_priv = to_i915(dev); 8435 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 8436 struct intel_crtc *crtc; 8437 struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {}; 8438 intel_wakeref_t wakeref = 0; 8439 int i; 8440 8441 intel_atomic_commit_fence_wait(state); 8442 8443 drm_atomic_helper_wait_for_dependencies(&state->base); 8444 8445 if (state->modeset) 8446 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); 8447 8448 intel_atomic_prepare_plane_clear_colors(state); 8449 8450 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8451 new_crtc_state, i) { 8452 if (intel_crtc_needs_modeset(new_crtc_state) || 8453 new_crtc_state->update_pipe) { 8454 modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]); 8455 } 8456 } 8457 8458 intel_commit_modeset_disables(state); 8459 8460 /* FIXME: Eventually get rid of our crtc->config pointer */ 8461 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 8462 crtc->config = new_crtc_state; 8463 8464 if (state->modeset) { 8465 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base); 8466 8467 intel_set_cdclk_pre_plane_update(state); 8468 8469 intel_modeset_verify_disabled(dev_priv, state); 8470 } 8471 8472 intel_sagv_pre_plane_update(state); 8473 8474 /* Complete the events for pipes that have now been disabled */ 8475 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8476 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 8477 8478 /* Complete events for now disable pipes here. */ 8479 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) { 8480 spin_lock_irq(&dev->event_lock); 8481 drm_crtc_send_vblank_event(&crtc->base, 8482 new_crtc_state->uapi.event); 8483 spin_unlock_irq(&dev->event_lock); 8484 8485 new_crtc_state->uapi.event = NULL; 8486 } 8487 } 8488 8489 intel_encoders_update_prepare(state); 8490 8491 intel_dbuf_pre_plane_update(state); 8492 intel_mbus_dbox_update(state); 8493 8494 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8495 if (new_crtc_state->do_async_flip) 8496 intel_crtc_enable_flip_done(state, crtc); 8497 } 8498 8499 /* Now enable the clocks, plane, pipe, and connectors that we set up. */ 8500 dev_priv->display->commit_modeset_enables(state); 8501 8502 intel_encoders_update_complete(state); 8503 8504 if (state->modeset) 8505 intel_set_cdclk_post_plane_update(state); 8506 8507 intel_wait_for_vblank_workers(state); 8508 8509 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here 8510 * already, but still need the state for the delayed optimization. To 8511 * fix this: 8512 * - wrap the optimization/post_plane_update stuff into a per-crtc work. 8513 * - schedule that vblank worker _before_ calling hw_done 8514 * - at the start of commit_tail, cancel it _synchrously 8515 * - switch over to the vblank wait helper in the core after that since 8516 * we don't need out special handling any more. 8517 */ 8518 drm_atomic_helper_wait_for_flip_done(dev, &state->base); 8519 8520 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8521 if (new_crtc_state->do_async_flip) 8522 intel_crtc_disable_flip_done(state, crtc); 8523 } 8524 8525 /* 8526 * Now that the vblank has passed, we can go ahead and program the 8527 * optimal watermarks on platforms that need two-step watermark 8528 * programming. 8529 * 8530 * TODO: Move this (and other cleanup) to an async worker eventually. 8531 */ 8532 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8533 new_crtc_state, i) { 8534 /* 8535 * Gen2 reports pipe underruns whenever all planes are disabled. 8536 * So re-enable underrun reporting after some planes get enabled. 8537 * 8538 * We do this before .optimize_watermarks() so that we have a 8539 * chance of catching underruns with the intermediate watermarks 8540 * vs. the new plane configuration. 8541 */ 8542 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state)) 8543 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 8544 8545 intel_optimize_watermarks(state, crtc); 8546 } 8547 8548 intel_dbuf_post_plane_update(state); 8549 intel_psr_post_plane_update(state); 8550 8551 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 8552 intel_post_plane_update(state, crtc); 8553 8554 modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]); 8555 8556 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state); 8557 8558 /* 8559 * DSB cleanup is done in cleanup_work aligning with framebuffer 8560 * cleanup. So copy and reset the dsb structure to sync with 8561 * commit_done and later do dsb cleanup in cleanup_work. 8562 */ 8563 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb); 8564 } 8565 8566 /* Underruns don't always raise interrupts, so check manually */ 8567 intel_check_cpu_fifo_underruns(dev_priv); 8568 intel_check_pch_fifo_underruns(dev_priv); 8569 8570 if (state->modeset) 8571 intel_verify_planes(state); 8572 8573 intel_sagv_post_plane_update(state); 8574 8575 drm_atomic_helper_commit_hw_done(&state->base); 8576 8577 if (state->modeset) { 8578 /* As one of the primary mmio accessors, KMS has a high 8579 * likelihood of triggering bugs in unclaimed access. After we 8580 * finish modesetting, see if an error has been flagged, and if 8581 * so enable debugging for the next modeset - and hope we catch 8582 * the culprit. 8583 */ 8584 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); 8585 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref); 8586 } 8587 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 8588 8589 /* 8590 * Defer the cleanup of the old state to a separate worker to not 8591 * impede the current task (userspace for blocking modesets) that 8592 * are executed inline. For out-of-line asynchronous modesets/flips, 8593 * deferring to a new worker seems overkill, but we would place a 8594 * schedule point (cond_resched()) here anyway to keep latencies 8595 * down. 8596 */ 8597 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work); 8598 queue_work(system_highpri_wq, &state->base.commit_work); 8599 } 8600 8601 static void intel_atomic_commit_work(struct work_struct *work) 8602 { 8603 struct intel_atomic_state *state = 8604 container_of(work, struct intel_atomic_state, base.commit_work); 8605 8606 intel_atomic_commit_tail(state); 8607 } 8608 8609 static int 8610 intel_atomic_commit_ready(struct i915_sw_fence *fence, 8611 enum i915_sw_fence_notify notify) 8612 { 8613 struct intel_atomic_state *state = 8614 container_of(fence, struct intel_atomic_state, commit_ready); 8615 8616 switch (notify) { 8617 case FENCE_COMPLETE: 8618 /* we do blocking waits in the worker, nothing to do here */ 8619 break; 8620 case FENCE_FREE: 8621 { 8622 struct intel_atomic_helper *helper = 8623 &to_i915(state->base.dev)->atomic_helper; 8624 8625 if (llist_add(&state->freed, &helper->free_list)) 8626 schedule_work(&helper->free_work); 8627 break; 8628 } 8629 } 8630 8631 return NOTIFY_DONE; 8632 } 8633 8634 static void intel_atomic_track_fbs(struct intel_atomic_state *state) 8635 { 8636 struct intel_plane_state *old_plane_state, *new_plane_state; 8637 struct intel_plane *plane; 8638 int i; 8639 8640 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 8641 new_plane_state, i) 8642 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), 8643 to_intel_frontbuffer(new_plane_state->hw.fb), 8644 plane->frontbuffer_bit); 8645 } 8646 8647 static int intel_atomic_commit(struct drm_device *dev, 8648 struct drm_atomic_state *_state, 8649 bool nonblock) 8650 { 8651 struct intel_atomic_state *state = to_intel_atomic_state(_state); 8652 struct drm_i915_private *dev_priv = to_i915(dev); 8653 int ret = 0; 8654 8655 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 8656 8657 drm_atomic_state_get(&state->base); 8658 i915_sw_fence_init(&state->commit_ready, 8659 intel_atomic_commit_ready); 8660 8661 /* 8662 * The intel_legacy_cursor_update() fast path takes care 8663 * of avoiding the vblank waits for simple cursor 8664 * movement and flips. For cursor on/off and size changes, 8665 * we want to perform the vblank waits so that watermark 8666 * updates happen during the correct frames. Gen9+ have 8667 * double buffered watermarks and so shouldn't need this. 8668 * 8669 * Unset state->legacy_cursor_update before the call to 8670 * drm_atomic_helper_setup_commit() because otherwise 8671 * drm_atomic_helper_wait_for_flip_done() is a noop and 8672 * we get FIFO underruns because we didn't wait 8673 * for vblank. 8674 * 8675 * FIXME doing watermarks and fb cleanup from a vblank worker 8676 * (assuming we had any) would solve these problems. 8677 */ 8678 if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) { 8679 struct intel_crtc_state *new_crtc_state; 8680 struct intel_crtc *crtc; 8681 int i; 8682 8683 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 8684 if (new_crtc_state->wm.need_postvbl_update || 8685 new_crtc_state->update_wm_post) 8686 state->base.legacy_cursor_update = false; 8687 } 8688 8689 ret = intel_atomic_prepare_commit(state); 8690 if (ret) { 8691 drm_dbg_atomic(&dev_priv->drm, 8692 "Preparing state failed with %i\n", ret); 8693 i915_sw_fence_commit(&state->commit_ready); 8694 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 8695 return ret; 8696 } 8697 8698 ret = drm_atomic_helper_setup_commit(&state->base, nonblock); 8699 if (!ret) 8700 ret = drm_atomic_helper_swap_state(&state->base, true); 8701 if (!ret) 8702 intel_atomic_swap_global_state(state); 8703 8704 if (ret) { 8705 struct intel_crtc_state *new_crtc_state; 8706 struct intel_crtc *crtc; 8707 int i; 8708 8709 i915_sw_fence_commit(&state->commit_ready); 8710 8711 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 8712 intel_dsb_cleanup(new_crtc_state); 8713 8714 drm_atomic_helper_cleanup_planes(dev, &state->base); 8715 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 8716 return ret; 8717 } 8718 intel_shared_dpll_swap_state(state); 8719 intel_atomic_track_fbs(state); 8720 8721 drm_atomic_state_get(&state->base); 8722 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work); 8723 8724 i915_sw_fence_commit(&state->commit_ready); 8725 if (nonblock && state->modeset) { 8726 queue_work(dev_priv->modeset_wq, &state->base.commit_work); 8727 } else if (nonblock) { 8728 queue_work(dev_priv->flip_wq, &state->base.commit_work); 8729 } else { 8730 if (state->modeset) 8731 flush_workqueue(dev_priv->modeset_wq); 8732 intel_atomic_commit_tail(state); 8733 } 8734 8735 return 0; 8736 } 8737 8738 /** 8739 * intel_plane_destroy - destroy a plane 8740 * @plane: plane to destroy 8741 * 8742 * Common destruction function for all types of planes (primary, cursor, 8743 * sprite). 8744 */ 8745 void intel_plane_destroy(struct drm_plane *plane) 8746 { 8747 drm_plane_cleanup(plane); 8748 kfree(to_intel_plane(plane)); 8749 } 8750 8751 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv) 8752 { 8753 struct intel_plane *plane; 8754 8755 for_each_intel_plane(&dev_priv->drm, plane) { 8756 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, 8757 plane->pipe); 8758 8759 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base); 8760 } 8761 } 8762 8763 8764 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 8765 struct drm_file *file) 8766 { 8767 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; 8768 struct drm_crtc *drmmode_crtc; 8769 struct intel_crtc *crtc; 8770 8771 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id); 8772 if (!drmmode_crtc) 8773 return -ENOENT; 8774 8775 crtc = to_intel_crtc(drmmode_crtc); 8776 pipe_from_crtc_id->pipe = crtc->pipe; 8777 8778 return 0; 8779 } 8780 8781 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder) 8782 { 8783 struct drm_device *dev = encoder->base.dev; 8784 struct intel_encoder *source_encoder; 8785 u32 possible_clones = 0; 8786 8787 for_each_intel_encoder(dev, source_encoder) { 8788 if (encoders_cloneable(encoder, source_encoder)) 8789 possible_clones |= drm_encoder_mask(&source_encoder->base); 8790 } 8791 8792 return possible_clones; 8793 } 8794 8795 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder) 8796 { 8797 struct drm_device *dev = encoder->base.dev; 8798 struct intel_crtc *crtc; 8799 u32 possible_crtcs = 0; 8800 8801 for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask) 8802 possible_crtcs |= drm_crtc_mask(&crtc->base); 8803 8804 return possible_crtcs; 8805 } 8806 8807 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv) 8808 { 8809 if (!IS_MOBILE(dev_priv)) 8810 return false; 8811 8812 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0) 8813 return false; 8814 8815 if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE)) 8816 return false; 8817 8818 return true; 8819 } 8820 8821 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv) 8822 { 8823 if (DISPLAY_VER(dev_priv) >= 9) 8824 return false; 8825 8826 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) 8827 return false; 8828 8829 if (HAS_PCH_LPT_H(dev_priv) && 8830 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) 8831 return false; 8832 8833 /* DDI E can't be used if DDI A requires 4 lanes */ 8834 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 8835 return false; 8836 8837 if (!dev_priv->vbt.int_crt_support) 8838 return false; 8839 8840 return true; 8841 } 8842 8843 static void intel_setup_outputs(struct drm_i915_private *dev_priv) 8844 { 8845 struct intel_encoder *encoder; 8846 bool dpd_is_edp = false; 8847 8848 intel_pps_unlock_regs_wa(dev_priv); 8849 8850 if (!HAS_DISPLAY(dev_priv)) 8851 return; 8852 8853 if (IS_DG2(dev_priv)) { 8854 intel_ddi_init(dev_priv, PORT_A); 8855 intel_ddi_init(dev_priv, PORT_B); 8856 intel_ddi_init(dev_priv, PORT_C); 8857 intel_ddi_init(dev_priv, PORT_D_XELPD); 8858 intel_ddi_init(dev_priv, PORT_TC1); 8859 } else if (IS_ALDERLAKE_P(dev_priv)) { 8860 intel_ddi_init(dev_priv, PORT_A); 8861 intel_ddi_init(dev_priv, PORT_B); 8862 intel_ddi_init(dev_priv, PORT_TC1); 8863 intel_ddi_init(dev_priv, PORT_TC2); 8864 intel_ddi_init(dev_priv, PORT_TC3); 8865 intel_ddi_init(dev_priv, PORT_TC4); 8866 icl_dsi_init(dev_priv); 8867 } else if (IS_ALDERLAKE_S(dev_priv)) { 8868 intel_ddi_init(dev_priv, PORT_A); 8869 intel_ddi_init(dev_priv, PORT_TC1); 8870 intel_ddi_init(dev_priv, PORT_TC2); 8871 intel_ddi_init(dev_priv, PORT_TC3); 8872 intel_ddi_init(dev_priv, PORT_TC4); 8873 } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) { 8874 intel_ddi_init(dev_priv, PORT_A); 8875 intel_ddi_init(dev_priv, PORT_B); 8876 intel_ddi_init(dev_priv, PORT_TC1); 8877 intel_ddi_init(dev_priv, PORT_TC2); 8878 } else if (DISPLAY_VER(dev_priv) >= 12) { 8879 intel_ddi_init(dev_priv, PORT_A); 8880 intel_ddi_init(dev_priv, PORT_B); 8881 intel_ddi_init(dev_priv, PORT_TC1); 8882 intel_ddi_init(dev_priv, PORT_TC2); 8883 intel_ddi_init(dev_priv, PORT_TC3); 8884 intel_ddi_init(dev_priv, PORT_TC4); 8885 intel_ddi_init(dev_priv, PORT_TC5); 8886 intel_ddi_init(dev_priv, PORT_TC6); 8887 icl_dsi_init(dev_priv); 8888 } else if (IS_JSL_EHL(dev_priv)) { 8889 intel_ddi_init(dev_priv, PORT_A); 8890 intel_ddi_init(dev_priv, PORT_B); 8891 intel_ddi_init(dev_priv, PORT_C); 8892 intel_ddi_init(dev_priv, PORT_D); 8893 icl_dsi_init(dev_priv); 8894 } else if (DISPLAY_VER(dev_priv) == 11) { 8895 intel_ddi_init(dev_priv, PORT_A); 8896 intel_ddi_init(dev_priv, PORT_B); 8897 intel_ddi_init(dev_priv, PORT_C); 8898 intel_ddi_init(dev_priv, PORT_D); 8899 intel_ddi_init(dev_priv, PORT_E); 8900 intel_ddi_init(dev_priv, PORT_F); 8901 icl_dsi_init(dev_priv); 8902 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 8903 intel_ddi_init(dev_priv, PORT_A); 8904 intel_ddi_init(dev_priv, PORT_B); 8905 intel_ddi_init(dev_priv, PORT_C); 8906 vlv_dsi_init(dev_priv); 8907 } else if (DISPLAY_VER(dev_priv) >= 9) { 8908 intel_ddi_init(dev_priv, PORT_A); 8909 intel_ddi_init(dev_priv, PORT_B); 8910 intel_ddi_init(dev_priv, PORT_C); 8911 intel_ddi_init(dev_priv, PORT_D); 8912 intel_ddi_init(dev_priv, PORT_E); 8913 } else if (HAS_DDI(dev_priv)) { 8914 u32 found; 8915 8916 if (intel_ddi_crt_present(dev_priv)) 8917 intel_crt_init(dev_priv); 8918 8919 /* Haswell uses DDI functions to detect digital outputs. */ 8920 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 8921 if (found) 8922 intel_ddi_init(dev_priv, PORT_A); 8923 8924 found = intel_de_read(dev_priv, SFUSE_STRAP); 8925 if (found & SFUSE_STRAP_DDIB_DETECTED) 8926 intel_ddi_init(dev_priv, PORT_B); 8927 if (found & SFUSE_STRAP_DDIC_DETECTED) 8928 intel_ddi_init(dev_priv, PORT_C); 8929 if (found & SFUSE_STRAP_DDID_DETECTED) 8930 intel_ddi_init(dev_priv, PORT_D); 8931 if (found & SFUSE_STRAP_DDIF_DETECTED) 8932 intel_ddi_init(dev_priv, PORT_F); 8933 } else if (HAS_PCH_SPLIT(dev_priv)) { 8934 int found; 8935 8936 /* 8937 * intel_edp_init_connector() depends on this completing first, 8938 * to prevent the registration of both eDP and LVDS and the 8939 * incorrect sharing of the PPS. 8940 */ 8941 intel_lvds_init(dev_priv); 8942 intel_crt_init(dev_priv); 8943 8944 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D); 8945 8946 if (ilk_has_edp_a(dev_priv)) 8947 g4x_dp_init(dev_priv, DP_A, PORT_A); 8948 8949 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) { 8950 /* PCH SDVOB multiplex with HDMIB */ 8951 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); 8952 if (!found) 8953 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); 8954 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED)) 8955 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B); 8956 } 8957 8958 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED) 8959 g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); 8960 8961 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED) 8962 g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D); 8963 8964 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED) 8965 g4x_dp_init(dev_priv, PCH_DP_C, PORT_C); 8966 8967 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED) 8968 g4x_dp_init(dev_priv, PCH_DP_D, PORT_D); 8969 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 8970 bool has_edp, has_port; 8971 8972 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support) 8973 intel_crt_init(dev_priv); 8974 8975 /* 8976 * The DP_DETECTED bit is the latched state of the DDC 8977 * SDA pin at boot. However since eDP doesn't require DDC 8978 * (no way to plug in a DP->HDMI dongle) the DDC pins for 8979 * eDP ports may have been muxed to an alternate function. 8980 * Thus we can't rely on the DP_DETECTED bit alone to detect 8981 * eDP ports. Consult the VBT as well as DP_DETECTED to 8982 * detect eDP ports. 8983 * 8984 * Sadly the straps seem to be missing sometimes even for HDMI 8985 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap 8986 * and VBT for the presence of the port. Additionally we can't 8987 * trust the port type the VBT declares as we've seen at least 8988 * HDMI ports that the VBT claim are DP or eDP. 8989 */ 8990 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B); 8991 has_port = intel_bios_is_port_present(dev_priv, PORT_B); 8992 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port) 8993 has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B); 8994 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) 8995 g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); 8996 8997 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C); 8998 has_port = intel_bios_is_port_present(dev_priv, PORT_C); 8999 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port) 9000 has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C); 9001 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) 9002 g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); 9003 9004 if (IS_CHERRYVIEW(dev_priv)) { 9005 /* 9006 * eDP not supported on port D, 9007 * so no need to worry about it 9008 */ 9009 has_port = intel_bios_is_port_present(dev_priv, PORT_D); 9010 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port) 9011 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D); 9012 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port) 9013 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D); 9014 } 9015 9016 vlv_dsi_init(dev_priv); 9017 } else if (IS_PINEVIEW(dev_priv)) { 9018 intel_lvds_init(dev_priv); 9019 intel_crt_init(dev_priv); 9020 } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) { 9021 bool found = false; 9022 9023 if (IS_MOBILE(dev_priv)) 9024 intel_lvds_init(dev_priv); 9025 9026 intel_crt_init(dev_priv); 9027 9028 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 9029 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n"); 9030 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); 9031 if (!found && IS_G4X(dev_priv)) { 9032 drm_dbg_kms(&dev_priv->drm, 9033 "probing HDMI on SDVOB\n"); 9034 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); 9035 } 9036 9037 if (!found && IS_G4X(dev_priv)) 9038 g4x_dp_init(dev_priv, DP_B, PORT_B); 9039 } 9040 9041 /* Before G4X SDVOC doesn't have its own detect register */ 9042 9043 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 9044 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n"); 9045 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); 9046 } 9047 9048 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) { 9049 9050 if (IS_G4X(dev_priv)) { 9051 drm_dbg_kms(&dev_priv->drm, 9052 "probing HDMI on SDVOC\n"); 9053 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); 9054 } 9055 if (IS_G4X(dev_priv)) 9056 g4x_dp_init(dev_priv, DP_C, PORT_C); 9057 } 9058 9059 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED)) 9060 g4x_dp_init(dev_priv, DP_D, PORT_D); 9061 9062 if (SUPPORTS_TV(dev_priv)) 9063 intel_tv_init(dev_priv); 9064 } else if (DISPLAY_VER(dev_priv) == 2) { 9065 if (IS_I85X(dev_priv)) 9066 intel_lvds_init(dev_priv); 9067 9068 intel_crt_init(dev_priv); 9069 intel_dvo_init(dev_priv); 9070 } 9071 9072 for_each_intel_encoder(&dev_priv->drm, encoder) { 9073 encoder->base.possible_crtcs = 9074 intel_encoder_possible_crtcs(encoder); 9075 encoder->base.possible_clones = 9076 intel_encoder_possible_clones(encoder); 9077 } 9078 9079 intel_init_pch_refclk(dev_priv); 9080 9081 drm_helper_move_panel_connectors_to_head(&dev_priv->drm); 9082 } 9083 9084 static enum drm_mode_status 9085 intel_mode_valid(struct drm_device *dev, 9086 const struct drm_display_mode *mode) 9087 { 9088 struct drm_i915_private *dev_priv = to_i915(dev); 9089 int hdisplay_max, htotal_max; 9090 int vdisplay_max, vtotal_max; 9091 9092 /* 9093 * Can't reject DBLSCAN here because Xorg ddxen can add piles 9094 * of DBLSCAN modes to the output's mode list when they detect 9095 * the scaling mode property on the connector. And they don't 9096 * ask the kernel to validate those modes in any way until 9097 * modeset time at which point the client gets a protocol error. 9098 * So in order to not upset those clients we silently ignore the 9099 * DBLSCAN flag on such connectors. For other connectors we will 9100 * reject modes with the DBLSCAN flag in encoder->compute_config(). 9101 * And we always reject DBLSCAN modes in connector->mode_valid() 9102 * as we never want such modes on the connector's mode list. 9103 */ 9104 9105 if (mode->vscan > 1) 9106 return MODE_NO_VSCAN; 9107 9108 if (mode->flags & DRM_MODE_FLAG_HSKEW) 9109 return MODE_H_ILLEGAL; 9110 9111 if (mode->flags & (DRM_MODE_FLAG_CSYNC | 9112 DRM_MODE_FLAG_NCSYNC | 9113 DRM_MODE_FLAG_PCSYNC)) 9114 return MODE_HSYNC; 9115 9116 if (mode->flags & (DRM_MODE_FLAG_BCAST | 9117 DRM_MODE_FLAG_PIXMUX | 9118 DRM_MODE_FLAG_CLKDIV2)) 9119 return MODE_BAD; 9120 9121 /* Transcoder timing limits */ 9122 if (DISPLAY_VER(dev_priv) >= 11) { 9123 hdisplay_max = 16384; 9124 vdisplay_max = 8192; 9125 htotal_max = 16384; 9126 vtotal_max = 8192; 9127 } else if (DISPLAY_VER(dev_priv) >= 9 || 9128 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 9129 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ 9130 vdisplay_max = 4096; 9131 htotal_max = 8192; 9132 vtotal_max = 8192; 9133 } else if (DISPLAY_VER(dev_priv) >= 3) { 9134 hdisplay_max = 4096; 9135 vdisplay_max = 4096; 9136 htotal_max = 8192; 9137 vtotal_max = 8192; 9138 } else { 9139 hdisplay_max = 2048; 9140 vdisplay_max = 2048; 9141 htotal_max = 4096; 9142 vtotal_max = 4096; 9143 } 9144 9145 if (mode->hdisplay > hdisplay_max || 9146 mode->hsync_start > htotal_max || 9147 mode->hsync_end > htotal_max || 9148 mode->htotal > htotal_max) 9149 return MODE_H_ILLEGAL; 9150 9151 if (mode->vdisplay > vdisplay_max || 9152 mode->vsync_start > vtotal_max || 9153 mode->vsync_end > vtotal_max || 9154 mode->vtotal > vtotal_max) 9155 return MODE_V_ILLEGAL; 9156 9157 if (DISPLAY_VER(dev_priv) >= 5) { 9158 if (mode->hdisplay < 64 || 9159 mode->htotal - mode->hdisplay < 32) 9160 return MODE_H_ILLEGAL; 9161 9162 if (mode->vtotal - mode->vdisplay < 5) 9163 return MODE_V_ILLEGAL; 9164 } else { 9165 if (mode->htotal - mode->hdisplay < 32) 9166 return MODE_H_ILLEGAL; 9167 9168 if (mode->vtotal - mode->vdisplay < 3) 9169 return MODE_V_ILLEGAL; 9170 } 9171 9172 /* 9173 * Cantiga+ cannot handle modes with a hsync front porch of 0. 9174 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. 9175 */ 9176 if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) && 9177 mode->hsync_start == mode->hdisplay) 9178 return MODE_H_ILLEGAL; 9179 9180 return MODE_OK; 9181 } 9182 9183 enum drm_mode_status 9184 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 9185 const struct drm_display_mode *mode, 9186 bool bigjoiner) 9187 { 9188 int plane_width_max, plane_height_max; 9189 9190 /* 9191 * intel_mode_valid() should be 9192 * sufficient on older platforms. 9193 */ 9194 if (DISPLAY_VER(dev_priv) < 9) 9195 return MODE_OK; 9196 9197 /* 9198 * Most people will probably want a fullscreen 9199 * plane so let's not advertize modes that are 9200 * too big for that. 9201 */ 9202 if (DISPLAY_VER(dev_priv) >= 11) { 9203 plane_width_max = 5120 << bigjoiner; 9204 plane_height_max = 4320; 9205 } else { 9206 plane_width_max = 5120; 9207 plane_height_max = 4096; 9208 } 9209 9210 if (mode->hdisplay > plane_width_max) 9211 return MODE_H_ILLEGAL; 9212 9213 if (mode->vdisplay > plane_height_max) 9214 return MODE_V_ILLEGAL; 9215 9216 return MODE_OK; 9217 } 9218 9219 static const struct drm_mode_config_funcs intel_mode_funcs = { 9220 .fb_create = intel_user_framebuffer_create, 9221 .get_format_info = intel_fb_get_format_info, 9222 .output_poll_changed = intel_fbdev_output_poll_changed, 9223 .mode_valid = intel_mode_valid, 9224 .atomic_check = intel_atomic_check, 9225 .atomic_commit = intel_atomic_commit, 9226 .atomic_state_alloc = intel_atomic_state_alloc, 9227 .atomic_state_clear = intel_atomic_state_clear, 9228 .atomic_state_free = intel_atomic_state_free, 9229 }; 9230 9231 static const struct drm_i915_display_funcs skl_display_funcs = { 9232 .get_pipe_config = hsw_get_pipe_config, 9233 .crtc_enable = hsw_crtc_enable, 9234 .crtc_disable = hsw_crtc_disable, 9235 .commit_modeset_enables = skl_commit_modeset_enables, 9236 .get_initial_plane_config = skl_get_initial_plane_config, 9237 }; 9238 9239 static const struct drm_i915_display_funcs ddi_display_funcs = { 9240 .get_pipe_config = hsw_get_pipe_config, 9241 .crtc_enable = hsw_crtc_enable, 9242 .crtc_disable = hsw_crtc_disable, 9243 .commit_modeset_enables = intel_commit_modeset_enables, 9244 .get_initial_plane_config = i9xx_get_initial_plane_config, 9245 }; 9246 9247 static const struct drm_i915_display_funcs pch_split_display_funcs = { 9248 .get_pipe_config = ilk_get_pipe_config, 9249 .crtc_enable = ilk_crtc_enable, 9250 .crtc_disable = ilk_crtc_disable, 9251 .commit_modeset_enables = intel_commit_modeset_enables, 9252 .get_initial_plane_config = i9xx_get_initial_plane_config, 9253 }; 9254 9255 static const struct drm_i915_display_funcs vlv_display_funcs = { 9256 .get_pipe_config = i9xx_get_pipe_config, 9257 .crtc_enable = valleyview_crtc_enable, 9258 .crtc_disable = i9xx_crtc_disable, 9259 .commit_modeset_enables = intel_commit_modeset_enables, 9260 .get_initial_plane_config = i9xx_get_initial_plane_config, 9261 }; 9262 9263 static const struct drm_i915_display_funcs i9xx_display_funcs = { 9264 .get_pipe_config = i9xx_get_pipe_config, 9265 .crtc_enable = i9xx_crtc_enable, 9266 .crtc_disable = i9xx_crtc_disable, 9267 .commit_modeset_enables = intel_commit_modeset_enables, 9268 .get_initial_plane_config = i9xx_get_initial_plane_config, 9269 }; 9270 9271 /** 9272 * intel_init_display_hooks - initialize the display modesetting hooks 9273 * @dev_priv: device private 9274 */ 9275 void intel_init_display_hooks(struct drm_i915_private *dev_priv) 9276 { 9277 if (!HAS_DISPLAY(dev_priv)) 9278 return; 9279 9280 intel_init_cdclk_hooks(dev_priv); 9281 intel_audio_hooks_init(dev_priv); 9282 9283 intel_dpll_init_clock_hook(dev_priv); 9284 9285 if (DISPLAY_VER(dev_priv) >= 9) { 9286 dev_priv->display = &skl_display_funcs; 9287 } else if (HAS_DDI(dev_priv)) { 9288 dev_priv->display = &ddi_display_funcs; 9289 } else if (HAS_PCH_SPLIT(dev_priv)) { 9290 dev_priv->display = &pch_split_display_funcs; 9291 } else if (IS_CHERRYVIEW(dev_priv) || 9292 IS_VALLEYVIEW(dev_priv)) { 9293 dev_priv->display = &vlv_display_funcs; 9294 } else { 9295 dev_priv->display = &i9xx_display_funcs; 9296 } 9297 9298 intel_fdi_init_hook(dev_priv); 9299 } 9300 9301 void intel_modeset_init_hw(struct drm_i915_private *i915) 9302 { 9303 struct intel_cdclk_state *cdclk_state; 9304 9305 if (!HAS_DISPLAY(i915)) 9306 return; 9307 9308 cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state); 9309 9310 intel_update_cdclk(i915); 9311 intel_cdclk_dump_config(i915, &i915->cdclk.hw, "Current CDCLK"); 9312 cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw; 9313 } 9314 9315 static int sanitize_watermarks_add_affected(struct drm_atomic_state *state) 9316 { 9317 struct drm_plane *plane; 9318 struct intel_crtc *crtc; 9319 9320 for_each_intel_crtc(state->dev, crtc) { 9321 struct intel_crtc_state *crtc_state; 9322 9323 crtc_state = intel_atomic_get_crtc_state(state, crtc); 9324 if (IS_ERR(crtc_state)) 9325 return PTR_ERR(crtc_state); 9326 9327 if (crtc_state->hw.active) { 9328 /* 9329 * Preserve the inherited flag to avoid 9330 * taking the full modeset path. 9331 */ 9332 crtc_state->inherited = true; 9333 } 9334 } 9335 9336 drm_for_each_plane(plane, state->dev) { 9337 struct drm_plane_state *plane_state; 9338 9339 plane_state = drm_atomic_get_plane_state(state, plane); 9340 if (IS_ERR(plane_state)) 9341 return PTR_ERR(plane_state); 9342 } 9343 9344 return 0; 9345 } 9346 9347 /* 9348 * Calculate what we think the watermarks should be for the state we've read 9349 * out of the hardware and then immediately program those watermarks so that 9350 * we ensure the hardware settings match our internal state. 9351 * 9352 * We can calculate what we think WM's should be by creating a duplicate of the 9353 * current state (which was constructed during hardware readout) and running it 9354 * through the atomic check code to calculate new watermark values in the 9355 * state object. 9356 */ 9357 static void sanitize_watermarks(struct drm_i915_private *dev_priv) 9358 { 9359 struct drm_atomic_state *state; 9360 struct intel_atomic_state *intel_state; 9361 struct intel_crtc *crtc; 9362 struct intel_crtc_state *crtc_state; 9363 struct drm_modeset_acquire_ctx ctx; 9364 int ret; 9365 int i; 9366 9367 /* Only supported on platforms that use atomic watermark design */ 9368 if (!dev_priv->wm_disp->optimize_watermarks) 9369 return; 9370 9371 state = drm_atomic_state_alloc(&dev_priv->drm); 9372 if (drm_WARN_ON(&dev_priv->drm, !state)) 9373 return; 9374 9375 intel_state = to_intel_atomic_state(state); 9376 9377 drm_modeset_acquire_init(&ctx, 0); 9378 9379 retry: 9380 state->acquire_ctx = &ctx; 9381 9382 /* 9383 * Hardware readout is the only time we don't want to calculate 9384 * intermediate watermarks (since we don't trust the current 9385 * watermarks). 9386 */ 9387 if (!HAS_GMCH(dev_priv)) 9388 intel_state->skip_intermediate_wm = true; 9389 9390 ret = sanitize_watermarks_add_affected(state); 9391 if (ret) 9392 goto fail; 9393 9394 ret = intel_atomic_check(&dev_priv->drm, state); 9395 if (ret) 9396 goto fail; 9397 9398 /* Write calculated watermark values back */ 9399 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) { 9400 crtc_state->wm.need_postvbl_update = true; 9401 intel_optimize_watermarks(intel_state, crtc); 9402 9403 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm; 9404 } 9405 9406 fail: 9407 if (ret == -EDEADLK) { 9408 drm_atomic_state_clear(state); 9409 drm_modeset_backoff(&ctx); 9410 goto retry; 9411 } 9412 9413 /* 9414 * If we fail here, it means that the hardware appears to be 9415 * programmed in a way that shouldn't be possible, given our 9416 * understanding of watermark requirements. This might mean a 9417 * mistake in the hardware readout code or a mistake in the 9418 * watermark calculations for a given platform. Raise a WARN 9419 * so that this is noticeable. 9420 * 9421 * If this actually happens, we'll have to just leave the 9422 * BIOS-programmed watermarks untouched and hope for the best. 9423 */ 9424 drm_WARN(&dev_priv->drm, ret, 9425 "Could not determine valid watermarks for inherited state\n"); 9426 9427 drm_atomic_state_put(state); 9428 9429 drm_modeset_drop_locks(&ctx); 9430 drm_modeset_acquire_fini(&ctx); 9431 } 9432 9433 static int intel_initial_commit(struct drm_device *dev) 9434 { 9435 struct drm_atomic_state *state = NULL; 9436 struct drm_modeset_acquire_ctx ctx; 9437 struct intel_crtc *crtc; 9438 int ret = 0; 9439 9440 state = drm_atomic_state_alloc(dev); 9441 if (!state) 9442 return -ENOMEM; 9443 9444 drm_modeset_acquire_init(&ctx, 0); 9445 9446 retry: 9447 state->acquire_ctx = &ctx; 9448 9449 for_each_intel_crtc(dev, crtc) { 9450 struct intel_crtc_state *crtc_state = 9451 intel_atomic_get_crtc_state(state, crtc); 9452 9453 if (IS_ERR(crtc_state)) { 9454 ret = PTR_ERR(crtc_state); 9455 goto out; 9456 } 9457 9458 if (crtc_state->hw.active) { 9459 struct intel_encoder *encoder; 9460 9461 /* 9462 * We've not yet detected sink capabilities 9463 * (audio,infoframes,etc.) and thus we don't want to 9464 * force a full state recomputation yet. We want that to 9465 * happen only for the first real commit from userspace. 9466 * So preserve the inherited flag for the time being. 9467 */ 9468 crtc_state->inherited = true; 9469 9470 ret = drm_atomic_add_affected_planes(state, &crtc->base); 9471 if (ret) 9472 goto out; 9473 9474 /* 9475 * FIXME hack to force a LUT update to avoid the 9476 * plane update forcing the pipe gamma on without 9477 * having a proper LUT loaded. Remove once we 9478 * have readout for pipe gamma enable. 9479 */ 9480 crtc_state->uapi.color_mgmt_changed = true; 9481 9482 for_each_intel_encoder_mask(dev, encoder, 9483 crtc_state->uapi.encoder_mask) { 9484 if (encoder->initial_fastset_check && 9485 !encoder->initial_fastset_check(encoder, crtc_state)) { 9486 ret = drm_atomic_add_affected_connectors(state, 9487 &crtc->base); 9488 if (ret) 9489 goto out; 9490 } 9491 } 9492 } 9493 } 9494 9495 ret = drm_atomic_commit(state); 9496 9497 out: 9498 if (ret == -EDEADLK) { 9499 drm_atomic_state_clear(state); 9500 drm_modeset_backoff(&ctx); 9501 goto retry; 9502 } 9503 9504 drm_atomic_state_put(state); 9505 9506 drm_modeset_drop_locks(&ctx); 9507 drm_modeset_acquire_fini(&ctx); 9508 9509 return ret; 9510 } 9511 9512 static void intel_mode_config_init(struct drm_i915_private *i915) 9513 { 9514 struct drm_mode_config *mode_config = &i915->drm.mode_config; 9515 9516 drm_mode_config_init(&i915->drm); 9517 INIT_LIST_HEAD(&i915->global_obj_list); 9518 9519 mode_config->min_width = 0; 9520 mode_config->min_height = 0; 9521 9522 mode_config->preferred_depth = 24; 9523 mode_config->prefer_shadow = 1; 9524 9525 mode_config->funcs = &intel_mode_funcs; 9526 9527 mode_config->async_page_flip = HAS_ASYNC_FLIPS(i915); 9528 9529 /* 9530 * Maximum framebuffer dimensions, chosen to match 9531 * the maximum render engine surface size on gen4+. 9532 */ 9533 if (DISPLAY_VER(i915) >= 7) { 9534 mode_config->max_width = 16384; 9535 mode_config->max_height = 16384; 9536 } else if (DISPLAY_VER(i915) >= 4) { 9537 mode_config->max_width = 8192; 9538 mode_config->max_height = 8192; 9539 } else if (DISPLAY_VER(i915) == 3) { 9540 mode_config->max_width = 4096; 9541 mode_config->max_height = 4096; 9542 } else { 9543 mode_config->max_width = 2048; 9544 mode_config->max_height = 2048; 9545 } 9546 9547 if (IS_I845G(i915) || IS_I865G(i915)) { 9548 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512; 9549 mode_config->cursor_height = 1023; 9550 } else if (IS_I830(i915) || IS_I85X(i915) || 9551 IS_I915G(i915) || IS_I915GM(i915)) { 9552 mode_config->cursor_width = 64; 9553 mode_config->cursor_height = 64; 9554 } else { 9555 mode_config->cursor_width = 256; 9556 mode_config->cursor_height = 256; 9557 } 9558 } 9559 9560 static void intel_mode_config_cleanup(struct drm_i915_private *i915) 9561 { 9562 intel_atomic_global_obj_cleanup(i915); 9563 drm_mode_config_cleanup(&i915->drm); 9564 } 9565 9566 /* part #1: call before irq install */ 9567 int intel_modeset_init_noirq(struct drm_i915_private *i915) 9568 { 9569 int ret; 9570 9571 if (i915_inject_probe_failure(i915)) 9572 return -ENODEV; 9573 9574 if (HAS_DISPLAY(i915)) { 9575 ret = drm_vblank_init(&i915->drm, 9576 INTEL_NUM_PIPES(i915)); 9577 if (ret) 9578 return ret; 9579 } 9580 9581 intel_bios_init(i915); 9582 9583 ret = intel_vga_register(i915); 9584 if (ret) 9585 goto cleanup_bios; 9586 9587 /* FIXME: completely on the wrong abstraction layer */ 9588 intel_power_domains_init_hw(i915, false); 9589 9590 if (!HAS_DISPLAY(i915)) 9591 return 0; 9592 9593 intel_dmc_ucode_init(i915); 9594 9595 i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0); 9596 i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI | 9597 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE); 9598 9599 i915->window2_delay = 0; /* No DSB so no window2 delay */ 9600 9601 intel_mode_config_init(i915); 9602 9603 ret = intel_cdclk_init(i915); 9604 if (ret) 9605 goto cleanup_vga_client_pw_domain_dmc; 9606 9607 ret = intel_dbuf_init(i915); 9608 if (ret) 9609 goto cleanup_vga_client_pw_domain_dmc; 9610 9611 ret = intel_bw_init(i915); 9612 if (ret) 9613 goto cleanup_vga_client_pw_domain_dmc; 9614 9615 init_llist_head(&i915->atomic_helper.free_list); 9616 INIT_WORK(&i915->atomic_helper.free_work, 9617 intel_atomic_helper_free_state_worker); 9618 9619 intel_init_quirks(i915); 9620 9621 intel_fbc_init(i915); 9622 9623 return 0; 9624 9625 cleanup_vga_client_pw_domain_dmc: 9626 intel_dmc_ucode_fini(i915); 9627 intel_power_domains_driver_remove(i915); 9628 intel_vga_unregister(i915); 9629 cleanup_bios: 9630 intel_bios_driver_remove(i915); 9631 9632 return ret; 9633 } 9634 9635 /* part #2: call after irq install, but before gem init */ 9636 int intel_modeset_init_nogem(struct drm_i915_private *i915) 9637 { 9638 struct drm_device *dev = &i915->drm; 9639 enum pipe pipe; 9640 struct intel_crtc *crtc; 9641 int ret; 9642 9643 if (!HAS_DISPLAY(i915)) 9644 return 0; 9645 9646 intel_init_pm(i915); 9647 9648 intel_panel_sanitize_ssc(i915); 9649 9650 intel_pps_setup(i915); 9651 9652 intel_gmbus_setup(i915); 9653 9654 drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n", 9655 INTEL_NUM_PIPES(i915), 9656 INTEL_NUM_PIPES(i915) > 1 ? "s" : ""); 9657 9658 for_each_pipe(i915, pipe) { 9659 ret = intel_crtc_init(i915, pipe); 9660 if (ret) { 9661 intel_mode_config_cleanup(i915); 9662 return ret; 9663 } 9664 } 9665 9666 intel_plane_possible_crtcs_init(i915); 9667 intel_shared_dpll_init(i915); 9668 intel_fdi_pll_freq_update(i915); 9669 9670 intel_update_czclk(i915); 9671 intel_modeset_init_hw(i915); 9672 intel_dpll_update_ref_clks(i915); 9673 9674 intel_hdcp_component_init(i915); 9675 9676 if (i915->max_cdclk_freq == 0) 9677 intel_update_max_cdclk(i915); 9678 9679 /* 9680 * If the platform has HTI, we need to find out whether it has reserved 9681 * any display resources before we create our display outputs. 9682 */ 9683 if (INTEL_INFO(i915)->display.has_hti) 9684 i915->hti_state = intel_de_read(i915, HDPORT_STATE); 9685 9686 /* Just disable it once at startup */ 9687 intel_vga_disable(i915); 9688 intel_setup_outputs(i915); 9689 9690 drm_modeset_lock_all(dev); 9691 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx); 9692 intel_acpi_assign_connector_fwnodes(i915); 9693 drm_modeset_unlock_all(dev); 9694 9695 for_each_intel_crtc(dev, crtc) { 9696 if (!to_intel_crtc_state(crtc->base.state)->uapi.active) 9697 continue; 9698 intel_crtc_initial_plane_config(crtc); 9699 } 9700 9701 /* 9702 * Make sure hardware watermarks really match the state we read out. 9703 * Note that we need to do this after reconstructing the BIOS fb's 9704 * since the watermark calculation done here will use pstate->fb. 9705 */ 9706 if (!HAS_GMCH(i915)) 9707 sanitize_watermarks(i915); 9708 9709 return 0; 9710 } 9711 9712 /* part #3: call after gem init */ 9713 int intel_modeset_init(struct drm_i915_private *i915) 9714 { 9715 int ret; 9716 9717 if (!HAS_DISPLAY(i915)) 9718 return 0; 9719 9720 /* 9721 * Force all active planes to recompute their states. So that on 9722 * mode_setcrtc after probe, all the intel_plane_state variables 9723 * are already calculated and there is no assert_plane warnings 9724 * during bootup. 9725 */ 9726 ret = intel_initial_commit(&i915->drm); 9727 if (ret) 9728 drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret); 9729 9730 intel_overlay_setup(i915); 9731 9732 ret = intel_fbdev_init(&i915->drm); 9733 if (ret) 9734 return ret; 9735 9736 /* Only enable hotplug handling once the fbdev is fully set up. */ 9737 intel_hpd_init(i915); 9738 intel_hpd_poll_disable(i915); 9739 9740 intel_init_ipc(i915); 9741 9742 return 0; 9743 } 9744 9745 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 9746 { 9747 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 9748 /* 640x480@60Hz, ~25175 kHz */ 9749 struct dpll clock = { 9750 .m1 = 18, 9751 .m2 = 7, 9752 .p1 = 13, 9753 .p2 = 4, 9754 .n = 2, 9755 }; 9756 u32 dpll, fp; 9757 int i; 9758 9759 drm_WARN_ON(&dev_priv->drm, 9760 i9xx_calc_dpll_params(48000, &clock) != 25154); 9761 9762 drm_dbg_kms(&dev_priv->drm, 9763 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n", 9764 pipe_name(pipe), clock.vco, clock.dot); 9765 9766 fp = i9xx_dpll_compute_fp(&clock); 9767 dpll = DPLL_DVO_2X_MODE | 9768 DPLL_VGA_MODE_DIS | 9769 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | 9770 PLL_P2_DIVIDE_BY_4 | 9771 PLL_REF_INPUT_DREFCLK | 9772 DPLL_VCO_ENABLE; 9773 9774 intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16)); 9775 intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16)); 9776 intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16)); 9777 intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16)); 9778 intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16)); 9779 intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16)); 9780 intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1)); 9781 9782 intel_de_write(dev_priv, FP0(pipe), fp); 9783 intel_de_write(dev_priv, FP1(pipe), fp); 9784 9785 /* 9786 * Apparently we need to have VGA mode enabled prior to changing 9787 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 9788 * dividers, even though the register value does change. 9789 */ 9790 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); 9791 intel_de_write(dev_priv, DPLL(pipe), dpll); 9792 9793 /* Wait for the clocks to stabilize. */ 9794 intel_de_posting_read(dev_priv, DPLL(pipe)); 9795 udelay(150); 9796 9797 /* The pixel multiplier can only be updated once the 9798 * DPLL is enabled and the clocks are stable. 9799 * 9800 * So write it again. 9801 */ 9802 intel_de_write(dev_priv, DPLL(pipe), dpll); 9803 9804 /* We do this three times for luck */ 9805 for (i = 0; i < 3 ; i++) { 9806 intel_de_write(dev_priv, DPLL(pipe), dpll); 9807 intel_de_posting_read(dev_priv, DPLL(pipe)); 9808 udelay(150); /* wait for warmup */ 9809 } 9810 9811 intel_de_write(dev_priv, PIPECONF(pipe), PIPECONF_ENABLE); 9812 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 9813 9814 intel_wait_for_pipe_scanline_moving(crtc); 9815 } 9816 9817 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 9818 { 9819 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 9820 9821 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n", 9822 pipe_name(pipe)); 9823 9824 drm_WARN_ON(&dev_priv->drm, 9825 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE); 9826 drm_WARN_ON(&dev_priv->drm, 9827 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE); 9828 drm_WARN_ON(&dev_priv->drm, 9829 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE); 9830 drm_WARN_ON(&dev_priv->drm, 9831 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK); 9832 drm_WARN_ON(&dev_priv->drm, 9833 intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK); 9834 9835 intel_de_write(dev_priv, PIPECONF(pipe), 0); 9836 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 9837 9838 intel_wait_for_pipe_scanline_stopped(crtc); 9839 9840 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); 9841 intel_de_posting_read(dev_priv, DPLL(pipe)); 9842 } 9843 9844 static void 9845 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv) 9846 { 9847 struct intel_crtc *crtc; 9848 9849 if (DISPLAY_VER(dev_priv) >= 4) 9850 return; 9851 9852 for_each_intel_crtc(&dev_priv->drm, crtc) { 9853 struct intel_plane *plane = 9854 to_intel_plane(crtc->base.primary); 9855 struct intel_crtc *plane_crtc; 9856 enum pipe pipe; 9857 9858 if (!plane->get_hw_state(plane, &pipe)) 9859 continue; 9860 9861 if (pipe == crtc->pipe) 9862 continue; 9863 9864 drm_dbg_kms(&dev_priv->drm, 9865 "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n", 9866 plane->base.base.id, plane->base.name); 9867 9868 plane_crtc = intel_crtc_for_pipe(dev_priv, pipe); 9869 intel_plane_disable_noatomic(plane_crtc, plane); 9870 } 9871 } 9872 9873 static bool intel_crtc_has_encoders(struct intel_crtc *crtc) 9874 { 9875 struct drm_device *dev = crtc->base.dev; 9876 struct intel_encoder *encoder; 9877 9878 for_each_encoder_on_crtc(dev, &crtc->base, encoder) 9879 return true; 9880 9881 return false; 9882 } 9883 9884 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) 9885 { 9886 struct drm_device *dev = encoder->base.dev; 9887 struct intel_connector *connector; 9888 9889 for_each_connector_on_encoder(dev, &encoder->base, connector) 9890 return connector; 9891 9892 return NULL; 9893 } 9894 9895 static void intel_sanitize_crtc(struct intel_crtc *crtc, 9896 struct drm_modeset_acquire_ctx *ctx) 9897 { 9898 struct drm_device *dev = crtc->base.dev; 9899 struct drm_i915_private *dev_priv = to_i915(dev); 9900 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); 9901 9902 if (crtc_state->hw.active) { 9903 struct intel_plane *plane; 9904 9905 /* Disable everything but the primary plane */ 9906 for_each_intel_plane_on_crtc(dev, crtc, plane) { 9907 const struct intel_plane_state *plane_state = 9908 to_intel_plane_state(plane->base.state); 9909 9910 if (plane_state->uapi.visible && 9911 plane->base.type != DRM_PLANE_TYPE_PRIMARY) 9912 intel_plane_disable_noatomic(crtc, plane); 9913 } 9914 9915 /* Disable any background color/etc. set by the BIOS */ 9916 intel_color_commit_noarm(crtc_state); 9917 intel_color_commit_arm(crtc_state); 9918 } 9919 9920 /* Adjust the state of the output pipe according to whether we 9921 * have active connectors/encoders. */ 9922 if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) && 9923 !intel_crtc_is_bigjoiner_slave(crtc_state)) 9924 intel_crtc_disable_noatomic(crtc, ctx); 9925 9926 if (crtc_state->hw.active || HAS_GMCH(dev_priv)) { 9927 /* 9928 * We start out with underrun reporting disabled to avoid races. 9929 * For correct bookkeeping mark this on active crtcs. 9930 * 9931 * Also on gmch platforms we dont have any hardware bits to 9932 * disable the underrun reporting. Which means we need to start 9933 * out with underrun reporting disabled also on inactive pipes, 9934 * since otherwise we'll complain about the garbage we read when 9935 * e.g. coming up after runtime pm. 9936 * 9937 * No protection against concurrent access is required - at 9938 * worst a fifo underrun happens which also sets this to false. 9939 */ 9940 crtc->cpu_fifo_underrun_disabled = true; 9941 /* 9942 * We track the PCH trancoder underrun reporting state 9943 * within the crtc. With crtc for pipe A housing the underrun 9944 * reporting state for PCH transcoder A, crtc for pipe B housing 9945 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, 9946 * and marking underrun reporting as disabled for the non-existing 9947 * PCH transcoders B and C would prevent enabling the south 9948 * error interrupt (see cpt_can_enable_serr_int()). 9949 */ 9950 if (intel_has_pch_trancoder(dev_priv, crtc->pipe)) 9951 crtc->pch_fifo_underrun_disabled = true; 9952 } 9953 } 9954 9955 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state) 9956 { 9957 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 9958 9959 /* 9960 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram 9961 * the hardware when a high res displays plugged in. DPLL P 9962 * divider is zero, and the pipe timings are bonkers. We'll 9963 * try to disable everything in that case. 9964 * 9965 * FIXME would be nice to be able to sanitize this state 9966 * without several WARNs, but for now let's take the easy 9967 * road. 9968 */ 9969 return IS_SANDYBRIDGE(dev_priv) && 9970 crtc_state->hw.active && 9971 crtc_state->shared_dpll && 9972 crtc_state->port_clock == 0; 9973 } 9974 9975 static void intel_sanitize_encoder(struct intel_encoder *encoder) 9976 { 9977 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 9978 struct intel_connector *connector; 9979 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 9980 struct intel_crtc_state *crtc_state = crtc ? 9981 to_intel_crtc_state(crtc->base.state) : NULL; 9982 9983 /* We need to check both for a crtc link (meaning that the 9984 * encoder is active and trying to read from a pipe) and the 9985 * pipe itself being active. */ 9986 bool has_active_crtc = crtc_state && 9987 crtc_state->hw.active; 9988 9989 if (crtc_state && has_bogus_dpll_config(crtc_state)) { 9990 drm_dbg_kms(&dev_priv->drm, 9991 "BIOS has misprogrammed the hardware. Disabling pipe %c\n", 9992 pipe_name(crtc->pipe)); 9993 has_active_crtc = false; 9994 } 9995 9996 connector = intel_encoder_find_connector(encoder); 9997 if (connector && !has_active_crtc) { 9998 drm_dbg_kms(&dev_priv->drm, 9999 "[ENCODER:%d:%s] has active connectors but no active pipe!\n", 10000 encoder->base.base.id, 10001 encoder->base.name); 10002 10003 /* Connector is active, but has no active pipe. This is 10004 * fallout from our resume register restoring. Disable 10005 * the encoder manually again. */ 10006 if (crtc_state) { 10007 struct drm_encoder *best_encoder; 10008 10009 drm_dbg_kms(&dev_priv->drm, 10010 "[ENCODER:%d:%s] manually disabled\n", 10011 encoder->base.base.id, 10012 encoder->base.name); 10013 10014 /* avoid oopsing in case the hooks consult best_encoder */ 10015 best_encoder = connector->base.state->best_encoder; 10016 connector->base.state->best_encoder = &encoder->base; 10017 10018 /* FIXME NULL atomic state passed! */ 10019 if (encoder->disable) 10020 encoder->disable(NULL, encoder, crtc_state, 10021 connector->base.state); 10022 if (encoder->post_disable) 10023 encoder->post_disable(NULL, encoder, crtc_state, 10024 connector->base.state); 10025 10026 connector->base.state->best_encoder = best_encoder; 10027 } 10028 encoder->base.crtc = NULL; 10029 10030 /* Inconsistent output/port/pipe state happens presumably due to 10031 * a bug in one of the get_hw_state functions. Or someplace else 10032 * in our code, like the register restore mess on resume. Clamp 10033 * things to off as a safer default. */ 10034 10035 connector->base.dpms = DRM_MODE_DPMS_OFF; 10036 connector->base.encoder = NULL; 10037 } 10038 10039 /* notify opregion of the sanitized encoder state */ 10040 intel_opregion_notify_encoder(encoder, connector && has_active_crtc); 10041 10042 if (HAS_DDI(dev_priv)) 10043 intel_ddi_sanitize_encoder_pll_mapping(encoder); 10044 } 10045 10046 /* FIXME read out full plane state for all planes */ 10047 static void readout_plane_state(struct drm_i915_private *dev_priv) 10048 { 10049 struct intel_plane *plane; 10050 struct intel_crtc *crtc; 10051 10052 for_each_intel_plane(&dev_priv->drm, plane) { 10053 struct intel_plane_state *plane_state = 10054 to_intel_plane_state(plane->base.state); 10055 struct intel_crtc_state *crtc_state; 10056 enum pipe pipe = PIPE_A; 10057 bool visible; 10058 10059 visible = plane->get_hw_state(plane, &pipe); 10060 10061 crtc = intel_crtc_for_pipe(dev_priv, pipe); 10062 crtc_state = to_intel_crtc_state(crtc->base.state); 10063 10064 intel_set_plane_visible(crtc_state, plane_state, visible); 10065 10066 drm_dbg_kms(&dev_priv->drm, 10067 "[PLANE:%d:%s] hw state readout: %s, pipe %c\n", 10068 plane->base.base.id, plane->base.name, 10069 str_enabled_disabled(visible), pipe_name(pipe)); 10070 } 10071 10072 for_each_intel_crtc(&dev_priv->drm, crtc) { 10073 struct intel_crtc_state *crtc_state = 10074 to_intel_crtc_state(crtc->base.state); 10075 10076 fixup_plane_bitmasks(crtc_state); 10077 } 10078 } 10079 10080 static void intel_modeset_readout_hw_state(struct drm_device *dev) 10081 { 10082 struct drm_i915_private *dev_priv = to_i915(dev); 10083 struct intel_cdclk_state *cdclk_state = 10084 to_intel_cdclk_state(dev_priv->cdclk.obj.state); 10085 struct intel_dbuf_state *dbuf_state = 10086 to_intel_dbuf_state(dev_priv->dbuf.obj.state); 10087 enum pipe pipe; 10088 struct intel_crtc *crtc; 10089 struct intel_encoder *encoder; 10090 struct intel_connector *connector; 10091 struct drm_connector_list_iter conn_iter; 10092 u8 active_pipes = 0; 10093 10094 for_each_intel_crtc(dev, crtc) { 10095 struct intel_crtc_state *crtc_state = 10096 to_intel_crtc_state(crtc->base.state); 10097 10098 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi); 10099 intel_crtc_free_hw_state(crtc_state); 10100 intel_crtc_state_reset(crtc_state, crtc); 10101 10102 intel_crtc_get_pipe_config(crtc_state); 10103 10104 crtc_state->hw.enable = crtc_state->hw.active; 10105 10106 crtc->base.enabled = crtc_state->hw.enable; 10107 crtc->active = crtc_state->hw.active; 10108 10109 if (crtc_state->hw.active) 10110 active_pipes |= BIT(crtc->pipe); 10111 10112 drm_dbg_kms(&dev_priv->drm, 10113 "[CRTC:%d:%s] hw state readout: %s\n", 10114 crtc->base.base.id, crtc->base.name, 10115 str_enabled_disabled(crtc_state->hw.active)); 10116 } 10117 10118 cdclk_state->active_pipes = dbuf_state->active_pipes = active_pipes; 10119 10120 readout_plane_state(dev_priv); 10121 10122 for_each_intel_encoder(dev, encoder) { 10123 struct intel_crtc_state *crtc_state = NULL; 10124 10125 pipe = 0; 10126 10127 if (encoder->get_hw_state(encoder, &pipe)) { 10128 crtc = intel_crtc_for_pipe(dev_priv, pipe); 10129 crtc_state = to_intel_crtc_state(crtc->base.state); 10130 10131 encoder->base.crtc = &crtc->base; 10132 intel_encoder_get_config(encoder, crtc_state); 10133 10134 /* read out to slave crtc as well for bigjoiner */ 10135 if (crtc_state->bigjoiner_pipes) { 10136 struct intel_crtc *slave_crtc; 10137 10138 /* encoder should read be linked to bigjoiner master */ 10139 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 10140 10141 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc, 10142 intel_crtc_bigjoiner_slave_pipes(crtc_state)) { 10143 struct intel_crtc_state *slave_crtc_state; 10144 10145 slave_crtc_state = to_intel_crtc_state(slave_crtc->base.state); 10146 intel_encoder_get_config(encoder, slave_crtc_state); 10147 } 10148 } 10149 } else { 10150 encoder->base.crtc = NULL; 10151 } 10152 10153 if (encoder->sync_state) 10154 encoder->sync_state(encoder, crtc_state); 10155 10156 drm_dbg_kms(&dev_priv->drm, 10157 "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", 10158 encoder->base.base.id, encoder->base.name, 10159 str_enabled_disabled(encoder->base.crtc), 10160 pipe_name(pipe)); 10161 } 10162 10163 intel_dpll_readout_hw_state(dev_priv); 10164 10165 drm_connector_list_iter_begin(dev, &conn_iter); 10166 for_each_intel_connector_iter(connector, &conn_iter) { 10167 if (connector->get_hw_state(connector)) { 10168 struct intel_crtc_state *crtc_state; 10169 struct intel_crtc *crtc; 10170 10171 connector->base.dpms = DRM_MODE_DPMS_ON; 10172 10173 encoder = intel_attached_encoder(connector); 10174 connector->base.encoder = &encoder->base; 10175 10176 crtc = to_intel_crtc(encoder->base.crtc); 10177 crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL; 10178 10179 if (crtc_state && crtc_state->hw.active) { 10180 /* 10181 * This has to be done during hardware readout 10182 * because anything calling .crtc_disable may 10183 * rely on the connector_mask being accurate. 10184 */ 10185 crtc_state->uapi.connector_mask |= 10186 drm_connector_mask(&connector->base); 10187 crtc_state->uapi.encoder_mask |= 10188 drm_encoder_mask(&encoder->base); 10189 } 10190 } else { 10191 connector->base.dpms = DRM_MODE_DPMS_OFF; 10192 connector->base.encoder = NULL; 10193 } 10194 drm_dbg_kms(&dev_priv->drm, 10195 "[CONNECTOR:%d:%s] hw state readout: %s\n", 10196 connector->base.base.id, connector->base.name, 10197 str_enabled_disabled(connector->base.encoder)); 10198 } 10199 drm_connector_list_iter_end(&conn_iter); 10200 10201 for_each_intel_crtc(dev, crtc) { 10202 struct intel_bw_state *bw_state = 10203 to_intel_bw_state(dev_priv->bw_obj.state); 10204 struct intel_crtc_state *crtc_state = 10205 to_intel_crtc_state(crtc->base.state); 10206 struct intel_plane *plane; 10207 int min_cdclk = 0; 10208 10209 if (crtc_state->hw.active) { 10210 /* 10211 * The initial mode needs to be set in order to keep 10212 * the atomic core happy. It wants a valid mode if the 10213 * crtc's enabled, so we do the above call. 10214 * 10215 * But we don't set all the derived state fully, hence 10216 * set a flag to indicate that a full recalculation is 10217 * needed on the next commit. 10218 */ 10219 crtc_state->inherited = true; 10220 10221 intel_crtc_update_active_timings(crtc_state); 10222 10223 intel_crtc_copy_hw_to_uapi_state(crtc_state); 10224 } 10225 10226 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 10227 const struct intel_plane_state *plane_state = 10228 to_intel_plane_state(plane->base.state); 10229 10230 /* 10231 * FIXME don't have the fb yet, so can't 10232 * use intel_plane_data_rate() :( 10233 */ 10234 if (plane_state->uapi.visible) 10235 crtc_state->data_rate[plane->id] = 10236 4 * crtc_state->pixel_rate; 10237 /* 10238 * FIXME don't have the fb yet, so can't 10239 * use plane->min_cdclk() :( 10240 */ 10241 if (plane_state->uapi.visible && plane->min_cdclk) { 10242 if (crtc_state->double_wide || DISPLAY_VER(dev_priv) >= 10) 10243 crtc_state->min_cdclk[plane->id] = 10244 DIV_ROUND_UP(crtc_state->pixel_rate, 2); 10245 else 10246 crtc_state->min_cdclk[plane->id] = 10247 crtc_state->pixel_rate; 10248 } 10249 drm_dbg_kms(&dev_priv->drm, 10250 "[PLANE:%d:%s] min_cdclk %d kHz\n", 10251 plane->base.base.id, plane->base.name, 10252 crtc_state->min_cdclk[plane->id]); 10253 } 10254 10255 if (crtc_state->hw.active) { 10256 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); 10257 if (drm_WARN_ON(dev, min_cdclk < 0)) 10258 min_cdclk = 0; 10259 } 10260 10261 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; 10262 cdclk_state->min_voltage_level[crtc->pipe] = 10263 crtc_state->min_voltage_level; 10264 10265 intel_bw_crtc_update(bw_state, crtc_state); 10266 10267 intel_pipe_config_sanity_check(dev_priv, crtc_state); 10268 } 10269 } 10270 10271 static void 10272 get_encoder_power_domains(struct drm_i915_private *dev_priv) 10273 { 10274 struct intel_encoder *encoder; 10275 10276 for_each_intel_encoder(&dev_priv->drm, encoder) { 10277 struct intel_crtc_state *crtc_state; 10278 10279 if (!encoder->get_power_domains) 10280 continue; 10281 10282 /* 10283 * MST-primary and inactive encoders don't have a crtc state 10284 * and neither of these require any power domain references. 10285 */ 10286 if (!encoder->base.crtc) 10287 continue; 10288 10289 crtc_state = to_intel_crtc_state(encoder->base.crtc->state); 10290 encoder->get_power_domains(encoder, crtc_state); 10291 } 10292 } 10293 10294 static void intel_early_display_was(struct drm_i915_private *dev_priv) 10295 { 10296 /* 10297 * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl 10298 * Also known as Wa_14010480278. 10299 */ 10300 if (IS_DISPLAY_VER(dev_priv, 10, 12)) 10301 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0, 10302 intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS); 10303 10304 if (IS_HASWELL(dev_priv)) { 10305 /* 10306 * WaRsPkgCStateDisplayPMReq:hsw 10307 * System hang if this isn't done before disabling all planes! 10308 */ 10309 intel_de_write(dev_priv, CHICKEN_PAR1_1, 10310 intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); 10311 } 10312 10313 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) { 10314 /* Display WA #1142:kbl,cfl,cml */ 10315 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 10316 KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22); 10317 intel_de_rmw(dev_priv, CHICKEN_MISC_2, 10318 KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14, 10319 KBL_ARB_FILL_SPARE_14); 10320 } 10321 } 10322 10323 10324 /* Scan out the current hw modeset state, 10325 * and sanitizes it to the current state 10326 */ 10327 static void 10328 intel_modeset_setup_hw_state(struct drm_device *dev, 10329 struct drm_modeset_acquire_ctx *ctx) 10330 { 10331 struct drm_i915_private *dev_priv = to_i915(dev); 10332 struct intel_encoder *encoder; 10333 struct intel_crtc *crtc; 10334 intel_wakeref_t wakeref; 10335 10336 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 10337 10338 intel_early_display_was(dev_priv); 10339 intel_modeset_readout_hw_state(dev); 10340 10341 /* HW state is read out, now we need to sanitize this mess. */ 10342 get_encoder_power_domains(dev_priv); 10343 10344 intel_pch_sanitize(dev_priv); 10345 10346 /* 10347 * intel_sanitize_plane_mapping() may need to do vblank 10348 * waits, so we need vblank interrupts restored beforehand. 10349 */ 10350 for_each_intel_crtc(&dev_priv->drm, crtc) { 10351 struct intel_crtc_state *crtc_state = 10352 to_intel_crtc_state(crtc->base.state); 10353 10354 drm_crtc_vblank_reset(&crtc->base); 10355 10356 if (crtc_state->hw.active) 10357 intel_crtc_vblank_on(crtc_state); 10358 } 10359 10360 intel_fbc_sanitize(dev_priv); 10361 10362 intel_sanitize_plane_mapping(dev_priv); 10363 10364 for_each_intel_encoder(dev, encoder) 10365 intel_sanitize_encoder(encoder); 10366 10367 for_each_intel_crtc(&dev_priv->drm, crtc) { 10368 struct intel_crtc_state *crtc_state = 10369 to_intel_crtc_state(crtc->base.state); 10370 10371 intel_sanitize_crtc(crtc, ctx); 10372 intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]"); 10373 } 10374 10375 intel_modeset_update_connector_atomic_state(dev); 10376 10377 intel_dpll_sanitize_state(dev_priv); 10378 10379 if (IS_G4X(dev_priv)) { 10380 g4x_wm_get_hw_state(dev_priv); 10381 g4x_wm_sanitize(dev_priv); 10382 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 10383 vlv_wm_get_hw_state(dev_priv); 10384 vlv_wm_sanitize(dev_priv); 10385 } else if (DISPLAY_VER(dev_priv) >= 9) { 10386 skl_wm_get_hw_state(dev_priv); 10387 skl_wm_sanitize(dev_priv); 10388 } else if (HAS_PCH_SPLIT(dev_priv)) { 10389 ilk_wm_get_hw_state(dev_priv); 10390 } 10391 10392 for_each_intel_crtc(dev, crtc) { 10393 struct intel_crtc_state *crtc_state = 10394 to_intel_crtc_state(crtc->base.state); 10395 struct intel_power_domain_mask put_domains; 10396 10397 modeset_get_crtc_power_domains(crtc_state, &put_domains); 10398 if (drm_WARN_ON(dev, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM))) 10399 modeset_put_crtc_power_domains(crtc, &put_domains); 10400 } 10401 10402 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref); 10403 10404 intel_power_domains_sanitize_state(dev_priv); 10405 } 10406 10407 void intel_display_resume(struct drm_device *dev) 10408 { 10409 struct drm_i915_private *dev_priv = to_i915(dev); 10410 struct drm_atomic_state *state = dev_priv->modeset_restore_state; 10411 struct drm_modeset_acquire_ctx ctx; 10412 int ret; 10413 10414 if (!HAS_DISPLAY(dev_priv)) 10415 return; 10416 10417 dev_priv->modeset_restore_state = NULL; 10418 if (state) 10419 state->acquire_ctx = &ctx; 10420 10421 drm_modeset_acquire_init(&ctx, 0); 10422 10423 while (1) { 10424 ret = drm_modeset_lock_all_ctx(dev, &ctx); 10425 if (ret != -EDEADLK) 10426 break; 10427 10428 drm_modeset_backoff(&ctx); 10429 } 10430 10431 if (!ret) 10432 ret = __intel_display_resume(dev, state, &ctx); 10433 10434 intel_enable_ipc(dev_priv); 10435 drm_modeset_drop_locks(&ctx); 10436 drm_modeset_acquire_fini(&ctx); 10437 10438 if (ret) 10439 drm_err(&dev_priv->drm, 10440 "Restoring old state failed with %i\n", ret); 10441 if (state) 10442 drm_atomic_state_put(state); 10443 } 10444 10445 static void intel_hpd_poll_fini(struct drm_i915_private *i915) 10446 { 10447 struct intel_connector *connector; 10448 struct drm_connector_list_iter conn_iter; 10449 10450 /* Kill all the work that may have been queued by hpd. */ 10451 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 10452 for_each_intel_connector_iter(connector, &conn_iter) { 10453 if (connector->modeset_retry_work.func) 10454 cancel_work_sync(&connector->modeset_retry_work); 10455 if (connector->hdcp.shim) { 10456 cancel_delayed_work_sync(&connector->hdcp.check_work); 10457 cancel_work_sync(&connector->hdcp.prop_work); 10458 } 10459 } 10460 drm_connector_list_iter_end(&conn_iter); 10461 } 10462 10463 /* part #1: call before irq uninstall */ 10464 void intel_modeset_driver_remove(struct drm_i915_private *i915) 10465 { 10466 if (!HAS_DISPLAY(i915)) 10467 return; 10468 10469 flush_workqueue(i915->flip_wq); 10470 flush_workqueue(i915->modeset_wq); 10471 10472 flush_work(&i915->atomic_helper.free_work); 10473 drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list)); 10474 } 10475 10476 /* part #2: call after irq uninstall */ 10477 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915) 10478 { 10479 if (!HAS_DISPLAY(i915)) 10480 return; 10481 10482 /* 10483 * Due to the hpd irq storm handling the hotplug work can re-arm the 10484 * poll handlers. Hence disable polling after hpd handling is shut down. 10485 */ 10486 intel_hpd_poll_fini(i915); 10487 10488 /* 10489 * MST topology needs to be suspended so we don't have any calls to 10490 * fbdev after it's finalized. MST will be destroyed later as part of 10491 * drm_mode_config_cleanup() 10492 */ 10493 intel_dp_mst_suspend(i915); 10494 10495 /* poll work can call into fbdev, hence clean that up afterwards */ 10496 intel_fbdev_fini(i915); 10497 10498 intel_unregister_dsm_handler(); 10499 10500 /* flush any delayed tasks or pending work */ 10501 flush_scheduled_work(); 10502 10503 intel_hdcp_component_fini(i915); 10504 10505 intel_mode_config_cleanup(i915); 10506 10507 intel_overlay_cleanup(i915); 10508 10509 intel_gmbus_teardown(i915); 10510 10511 destroy_workqueue(i915->flip_wq); 10512 destroy_workqueue(i915->modeset_wq); 10513 10514 intel_fbc_cleanup(i915); 10515 } 10516 10517 /* part #3: call after gem init */ 10518 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915) 10519 { 10520 intel_dmc_ucode_fini(i915); 10521 10522 intel_power_domains_driver_remove(i915); 10523 10524 intel_vga_unregister(i915); 10525 10526 intel_bios_driver_remove(i915); 10527 } 10528 10529 bool intel_modeset_probe_defer(struct pci_dev *pdev) 10530 { 10531 struct drm_privacy_screen *privacy_screen; 10532 10533 /* 10534 * apple-gmux is needed on dual GPU MacBook Pro 10535 * to probe the panel if we're the inactive GPU. 10536 */ 10537 if (vga_switcheroo_client_probe_defer(pdev)) 10538 return true; 10539 10540 /* If the LCD panel has a privacy-screen, wait for it */ 10541 privacy_screen = drm_privacy_screen_get(&pdev->dev, NULL); 10542 if (IS_ERR(privacy_screen) && PTR_ERR(privacy_screen) == -EPROBE_DEFER) 10543 return true; 10544 10545 drm_privacy_screen_put(privacy_screen); 10546 10547 return false; 10548 } 10549 10550 void intel_display_driver_register(struct drm_i915_private *i915) 10551 { 10552 if (!HAS_DISPLAY(i915)) 10553 return; 10554 10555 intel_display_debugfs_register(i915); 10556 10557 /* Must be done after probing outputs */ 10558 intel_opregion_register(i915); 10559 acpi_video_register(); 10560 10561 intel_audio_init(i915); 10562 10563 /* 10564 * Some ports require correctly set-up hpd registers for 10565 * detection to work properly (leading to ghost connected 10566 * connector status), e.g. VGA on gm45. Hence we can only set 10567 * up the initial fbdev config after hpd irqs are fully 10568 * enabled. We do it last so that the async config cannot run 10569 * before the connectors are registered. 10570 */ 10571 intel_fbdev_initial_config_async(&i915->drm); 10572 10573 /* 10574 * We need to coordinate the hotplugs with the asynchronous 10575 * fbdev configuration, for which we use the 10576 * fbdev->async_cookie. 10577 */ 10578 drm_kms_helper_poll_init(&i915->drm); 10579 } 10580 10581 void intel_display_driver_unregister(struct drm_i915_private *i915) 10582 { 10583 if (!HAS_DISPLAY(i915)) 10584 return; 10585 10586 intel_fbdev_unregister(i915); 10587 intel_audio_deinit(i915); 10588 10589 /* 10590 * After flushing the fbdev (incl. a late async config which 10591 * will have delayed queuing of a hotplug event), then flush 10592 * the hotplug events. 10593 */ 10594 drm_kms_helper_poll_fini(&i915->drm); 10595 drm_atomic_helper_shutdown(&i915->drm); 10596 10597 acpi_video_unregister(); 10598 intel_opregion_unregister(i915); 10599 } 10600 10601 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915) 10602 { 10603 return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915); 10604 } 10605