1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <linux/dma-resv.h> 28 #include <linux/i2c.h> 29 #include <linux/input.h> 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/slab.h> 33 #include <linux/string_helpers.h> 34 35 #include <drm/display/drm_dp_helper.h> 36 #include <drm/drm_atomic.h> 37 #include <drm/drm_atomic_helper.h> 38 #include <drm/drm_atomic_uapi.h> 39 #include <drm/drm_damage_helper.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_fourcc.h> 42 #include <drm/drm_probe_helper.h> 43 #include <drm/drm_rect.h> 44 45 #include "gem/i915_gem_lmem.h" 46 #include "gem/i915_gem_object.h" 47 48 #include "g4x_dp.h" 49 #include "g4x_hdmi.h" 50 #include "hsw_ips.h" 51 #include "i915_drv.h" 52 #include "i915_reg.h" 53 #include "i915_utils.h" 54 #include "i9xx_plane.h" 55 #include "i9xx_wm.h" 56 #include "icl_dsi.h" 57 #include "intel_atomic.h" 58 #include "intel_atomic_plane.h" 59 #include "intel_audio.h" 60 #include "intel_bw.h" 61 #include "intel_cdclk.h" 62 #include "intel_clock_gating.h" 63 #include "intel_color.h" 64 #include "intel_crt.h" 65 #include "intel_crtc.h" 66 #include "intel_crtc_state_dump.h" 67 #include "intel_ddi.h" 68 #include "intel_de.h" 69 #include "intel_display_driver.h" 70 #include "intel_display_power.h" 71 #include "intel_display_types.h" 72 #include "intel_dmc.h" 73 #include "intel_dp.h" 74 #include "intel_dp_link_training.h" 75 #include "intel_dp_mst.h" 76 #include "intel_dpio_phy.h" 77 #include "intel_dpll.h" 78 #include "intel_dpll_mgr.h" 79 #include "intel_dpt.h" 80 #include "intel_drrs.h" 81 #include "intel_dsi.h" 82 #include "intel_dvo.h" 83 #include "intel_fb.h" 84 #include "intel_fbc.h" 85 #include "intel_fbdev.h" 86 #include "intel_fdi.h" 87 #include "intel_fifo_underrun.h" 88 #include "intel_frontbuffer.h" 89 #include "intel_hdmi.h" 90 #include "intel_hotplug.h" 91 #include "intel_lvds.h" 92 #include "intel_lvds_regs.h" 93 #include "intel_modeset_setup.h" 94 #include "intel_modeset_verify.h" 95 #include "intel_overlay.h" 96 #include "intel_panel.h" 97 #include "intel_pch_display.h" 98 #include "intel_pch_refclk.h" 99 #include "intel_pcode.h" 100 #include "intel_pipe_crc.h" 101 #include "intel_plane_initial.h" 102 #include "intel_pps.h" 103 #include "intel_psr.h" 104 #include "intel_sdvo.h" 105 #include "intel_snps_phy.h" 106 #include "intel_tc.h" 107 #include "intel_tv.h" 108 #include "intel_vblank.h" 109 #include "intel_vdsc.h" 110 #include "intel_vdsc_regs.h" 111 #include "intel_vga.h" 112 #include "intel_vrr.h" 113 #include "intel_wm.h" 114 #include "skl_scaler.h" 115 #include "skl_universal_plane.h" 116 #include "skl_watermark.h" 117 #include "vlv_dsi.h" 118 #include "vlv_dsi_pll.h" 119 #include "vlv_dsi_regs.h" 120 #include "vlv_sideband.h" 121 122 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state); 123 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state); 124 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state); 125 static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state); 126 127 /* returns HPLL frequency in kHz */ 128 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) 129 { 130 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; 131 132 /* Obtain SKU information */ 133 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & 134 CCK_FUSE_HPLL_FREQ_MASK; 135 136 return vco_freq[hpll_freq] * 1000; 137 } 138 139 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 140 const char *name, u32 reg, int ref_freq) 141 { 142 u32 val; 143 int divider; 144 145 val = vlv_cck_read(dev_priv, reg); 146 divider = val & CCK_FREQUENCY_VALUES; 147 148 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != 149 (divider << CCK_FREQUENCY_STATUS_SHIFT), 150 "%s change in progress\n", name); 151 152 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); 153 } 154 155 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 156 const char *name, u32 reg) 157 { 158 int hpll; 159 160 vlv_cck_get(dev_priv); 161 162 if (dev_priv->hpll_freq == 0) 163 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); 164 165 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); 166 167 vlv_cck_put(dev_priv); 168 169 return hpll; 170 } 171 172 void intel_update_czclk(struct drm_i915_private *dev_priv) 173 { 174 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) 175 return; 176 177 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", 178 CCK_CZ_CLOCK_CONTROL); 179 180 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", 181 dev_priv->czclk_freq); 182 } 183 184 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state) 185 { 186 return (crtc_state->active_planes & 187 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0; 188 } 189 190 /* WA Display #0827: Gen9:all */ 191 static void 192 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) 193 { 194 if (enable) 195 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 196 0, DUPS1_GATING_DIS | DUPS2_GATING_DIS); 197 else 198 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 199 DUPS1_GATING_DIS | DUPS2_GATING_DIS, 0); 200 } 201 202 /* Wa_2006604312:icl,ehl */ 203 static void 204 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 205 bool enable) 206 { 207 if (enable) 208 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 0, DPFR_GATING_DIS); 209 else 210 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), DPFR_GATING_DIS, 0); 211 } 212 213 /* Wa_1604331009:icl,jsl,ehl */ 214 static void 215 icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 216 bool enable) 217 { 218 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), CURSOR_GATING_DIS, 219 enable ? CURSOR_GATING_DIS : 0); 220 } 221 222 static bool 223 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state) 224 { 225 return crtc_state->master_transcoder != INVALID_TRANSCODER; 226 } 227 228 bool 229 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state) 230 { 231 return crtc_state->sync_mode_slaves_mask != 0; 232 } 233 234 bool 235 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state) 236 { 237 return is_trans_port_sync_master(crtc_state) || 238 is_trans_port_sync_slave(crtc_state); 239 } 240 241 static enum pipe bigjoiner_master_pipe(const struct intel_crtc_state *crtc_state) 242 { 243 return ffs(crtc_state->bigjoiner_pipes) - 1; 244 } 245 246 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state) 247 { 248 if (crtc_state->bigjoiner_pipes) 249 return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state)); 250 else 251 return 0; 252 } 253 254 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state) 255 { 256 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 257 258 return crtc_state->bigjoiner_pipes && 259 crtc->pipe != bigjoiner_master_pipe(crtc_state); 260 } 261 262 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state) 263 { 264 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 265 266 return crtc_state->bigjoiner_pipes && 267 crtc->pipe == bigjoiner_master_pipe(crtc_state); 268 } 269 270 static int intel_bigjoiner_num_pipes(const struct intel_crtc_state *crtc_state) 271 { 272 return hweight8(crtc_state->bigjoiner_pipes); 273 } 274 275 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state) 276 { 277 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 278 279 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 280 return intel_crtc_for_pipe(i915, bigjoiner_master_pipe(crtc_state)); 281 else 282 return to_intel_crtc(crtc_state->uapi.crtc); 283 } 284 285 static void 286 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) 287 { 288 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 289 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 290 291 if (DISPLAY_VER(dev_priv) >= 4) { 292 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 293 294 /* Wait for the Pipe State to go off */ 295 if (intel_de_wait_for_clear(dev_priv, TRANSCONF(cpu_transcoder), 296 TRANSCONF_STATE_ENABLE, 100)) 297 drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n"); 298 } else { 299 intel_wait_for_pipe_scanline_stopped(crtc); 300 } 301 } 302 303 void assert_transcoder(struct drm_i915_private *dev_priv, 304 enum transcoder cpu_transcoder, bool state) 305 { 306 bool cur_state; 307 enum intel_display_power_domain power_domain; 308 intel_wakeref_t wakeref; 309 310 /* we keep both pipes enabled on 830 */ 311 if (IS_I830(dev_priv)) 312 state = true; 313 314 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 315 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 316 if (wakeref) { 317 u32 val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)); 318 cur_state = !!(val & TRANSCONF_ENABLE); 319 320 intel_display_power_put(dev_priv, power_domain, wakeref); 321 } else { 322 cur_state = false; 323 } 324 325 I915_STATE_WARN(dev_priv, cur_state != state, 326 "transcoder %s assertion failure (expected %s, current %s)\n", 327 transcoder_name(cpu_transcoder), str_on_off(state), 328 str_on_off(cur_state)); 329 } 330 331 static void assert_plane(struct intel_plane *plane, bool state) 332 { 333 struct drm_i915_private *i915 = to_i915(plane->base.dev); 334 enum pipe pipe; 335 bool cur_state; 336 337 cur_state = plane->get_hw_state(plane, &pipe); 338 339 I915_STATE_WARN(i915, cur_state != state, 340 "%s assertion failure (expected %s, current %s)\n", 341 plane->base.name, str_on_off(state), 342 str_on_off(cur_state)); 343 } 344 345 #define assert_plane_enabled(p) assert_plane(p, true) 346 #define assert_plane_disabled(p) assert_plane(p, false) 347 348 static void assert_planes_disabled(struct intel_crtc *crtc) 349 { 350 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 351 struct intel_plane *plane; 352 353 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) 354 assert_plane_disabled(plane); 355 } 356 357 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 358 struct intel_digital_port *dig_port, 359 unsigned int expected_mask) 360 { 361 u32 port_mask; 362 i915_reg_t dpll_reg; 363 364 switch (dig_port->base.port) { 365 default: 366 MISSING_CASE(dig_port->base.port); 367 fallthrough; 368 case PORT_B: 369 port_mask = DPLL_PORTB_READY_MASK; 370 dpll_reg = DPLL(0); 371 break; 372 case PORT_C: 373 port_mask = DPLL_PORTC_READY_MASK; 374 dpll_reg = DPLL(0); 375 expected_mask <<= 4; 376 break; 377 case PORT_D: 378 port_mask = DPLL_PORTD_READY_MASK; 379 dpll_reg = DPIO_PHY_STATUS; 380 break; 381 } 382 383 if (intel_de_wait_for_register(dev_priv, dpll_reg, 384 port_mask, expected_mask, 1000)) 385 drm_WARN(&dev_priv->drm, 1, 386 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", 387 dig_port->base.base.base.id, dig_port->base.base.name, 388 intel_de_read(dev_priv, dpll_reg) & port_mask, 389 expected_mask); 390 } 391 392 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) 393 { 394 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 395 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 396 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 397 enum pipe pipe = crtc->pipe; 398 i915_reg_t reg; 399 u32 val; 400 401 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe)); 402 403 assert_planes_disabled(crtc); 404 405 /* 406 * A pipe without a PLL won't actually be able to drive bits from 407 * a plane. On ILK+ the pipe PLLs are integrated, so we don't 408 * need the check. 409 */ 410 if (HAS_GMCH(dev_priv)) { 411 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI)) 412 assert_dsi_pll_enabled(dev_priv); 413 else 414 assert_pll_enabled(dev_priv, pipe); 415 } else { 416 if (new_crtc_state->has_pch_encoder) { 417 /* if driving the PCH, we need FDI enabled */ 418 assert_fdi_rx_pll_enabled(dev_priv, 419 intel_crtc_pch_transcoder(crtc)); 420 assert_fdi_tx_pll_enabled(dev_priv, 421 (enum pipe) cpu_transcoder); 422 } 423 /* FIXME: assert CPU port conditions for SNB+ */ 424 } 425 426 /* Wa_22012358565:adl-p */ 427 if (DISPLAY_VER(dev_priv) == 13) 428 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe), 429 0, PIPE_ARB_USE_PROG_SLOTS); 430 431 reg = TRANSCONF(cpu_transcoder); 432 val = intel_de_read(dev_priv, reg); 433 if (val & TRANSCONF_ENABLE) { 434 /* we keep both pipes enabled on 830 */ 435 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv)); 436 return; 437 } 438 439 intel_de_write(dev_priv, reg, val | TRANSCONF_ENABLE); 440 intel_de_posting_read(dev_priv, reg); 441 442 /* 443 * Until the pipe starts PIPEDSL reads will return a stale value, 444 * which causes an apparent vblank timestamp jump when PIPEDSL 445 * resets to its proper value. That also messes up the frame count 446 * when it's derived from the timestamps. So let's wait for the 447 * pipe to start properly before we call drm_crtc_vblank_on() 448 */ 449 if (intel_crtc_max_vblank_count(new_crtc_state) == 0) 450 intel_wait_for_pipe_scanline_moving(crtc); 451 } 452 453 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) 454 { 455 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 456 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 457 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 458 enum pipe pipe = crtc->pipe; 459 i915_reg_t reg; 460 u32 val; 461 462 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe)); 463 464 /* 465 * Make sure planes won't keep trying to pump pixels to us, 466 * or we might hang the display. 467 */ 468 assert_planes_disabled(crtc); 469 470 reg = TRANSCONF(cpu_transcoder); 471 val = intel_de_read(dev_priv, reg); 472 if ((val & TRANSCONF_ENABLE) == 0) 473 return; 474 475 /* 476 * Double wide has implications for planes 477 * so best keep it disabled when not needed. 478 */ 479 if (old_crtc_state->double_wide) 480 val &= ~TRANSCONF_DOUBLE_WIDE; 481 482 /* Don't disable pipe or pipe PLLs if needed */ 483 if (!IS_I830(dev_priv)) 484 val &= ~TRANSCONF_ENABLE; 485 486 if (DISPLAY_VER(dev_priv) >= 14) 487 intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder), 488 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 489 else if (DISPLAY_VER(dev_priv) >= 12) 490 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 491 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 492 493 intel_de_write(dev_priv, reg, val); 494 if ((val & TRANSCONF_ENABLE) == 0) 495 intel_wait_for_pipe_off(old_crtc_state); 496 } 497 498 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) 499 { 500 unsigned int size = 0; 501 int i; 502 503 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) 504 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width; 505 506 return size; 507 } 508 509 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info) 510 { 511 unsigned int size = 0; 512 int i; 513 514 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) { 515 unsigned int plane_size; 516 517 if (rem_info->plane[i].linear) 518 plane_size = rem_info->plane[i].size; 519 else 520 plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height; 521 522 if (plane_size == 0) 523 continue; 524 525 if (rem_info->plane_alignment) 526 size = ALIGN(size, rem_info->plane_alignment); 527 528 size += plane_size; 529 } 530 531 return size; 532 } 533 534 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) 535 { 536 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 537 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 538 539 return DISPLAY_VER(dev_priv) < 4 || 540 (plane->fbc && 541 plane_state->view.gtt.type == I915_GTT_VIEW_NORMAL); 542 } 543 544 /* 545 * Convert the x/y offsets into a linear offset. 546 * Only valid with 0/180 degree rotation, which is fine since linear 547 * offset is only used with linear buffers on pre-hsw and tiled buffers 548 * with gen2/3, and 90/270 degree rotations isn't supported on any of them. 549 */ 550 u32 intel_fb_xy_to_linear(int x, int y, 551 const struct intel_plane_state *state, 552 int color_plane) 553 { 554 const struct drm_framebuffer *fb = state->hw.fb; 555 unsigned int cpp = fb->format->cpp[color_plane]; 556 unsigned int pitch = state->view.color_plane[color_plane].mapping_stride; 557 558 return y * pitch + x * cpp; 559 } 560 561 /* 562 * Add the x/y offsets derived from fb->offsets[] to the user 563 * specified plane src x/y offsets. The resulting x/y offsets 564 * specify the start of scanout from the beginning of the gtt mapping. 565 */ 566 void intel_add_fb_offsets(int *x, int *y, 567 const struct intel_plane_state *state, 568 int color_plane) 569 570 { 571 *x += state->view.color_plane[color_plane].x; 572 *y += state->view.color_plane[color_plane].y; 573 } 574 575 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 576 u32 pixel_format, u64 modifier) 577 { 578 struct intel_crtc *crtc; 579 struct intel_plane *plane; 580 581 if (!HAS_DISPLAY(dev_priv)) 582 return 0; 583 584 /* 585 * We assume the primary plane for pipe A has 586 * the highest stride limits of them all, 587 * if in case pipe A is disabled, use the first pipe from pipe_mask. 588 */ 589 crtc = intel_first_crtc(dev_priv); 590 if (!crtc) 591 return 0; 592 593 plane = to_intel_plane(crtc->base.primary); 594 595 return plane->max_stride(plane, pixel_format, modifier, 596 DRM_MODE_ROTATE_0); 597 } 598 599 void intel_set_plane_visible(struct intel_crtc_state *crtc_state, 600 struct intel_plane_state *plane_state, 601 bool visible) 602 { 603 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 604 605 plane_state->uapi.visible = visible; 606 607 if (visible) 608 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base); 609 else 610 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base); 611 } 612 613 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state) 614 { 615 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 616 struct drm_plane *plane; 617 618 /* 619 * Active_planes aliases if multiple "primary" or cursor planes 620 * have been used on the same (or wrong) pipe. plane_mask uses 621 * unique ids, hence we can use that to reconstruct active_planes. 622 */ 623 crtc_state->enabled_planes = 0; 624 crtc_state->active_planes = 0; 625 626 drm_for_each_plane_mask(plane, &dev_priv->drm, 627 crtc_state->uapi.plane_mask) { 628 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id); 629 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id); 630 } 631 } 632 633 void intel_plane_disable_noatomic(struct intel_crtc *crtc, 634 struct intel_plane *plane) 635 { 636 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 637 struct intel_crtc_state *crtc_state = 638 to_intel_crtc_state(crtc->base.state); 639 struct intel_plane_state *plane_state = 640 to_intel_plane_state(plane->base.state); 641 642 drm_dbg_kms(&dev_priv->drm, 643 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n", 644 plane->base.base.id, plane->base.name, 645 crtc->base.base.id, crtc->base.name); 646 647 intel_set_plane_visible(crtc_state, plane_state, false); 648 intel_plane_fixup_bitmasks(crtc_state); 649 crtc_state->data_rate[plane->id] = 0; 650 crtc_state->data_rate_y[plane->id] = 0; 651 crtc_state->rel_data_rate[plane->id] = 0; 652 crtc_state->rel_data_rate_y[plane->id] = 0; 653 crtc_state->min_cdclk[plane->id] = 0; 654 655 if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 && 656 hsw_ips_disable(crtc_state)) { 657 crtc_state->ips_enabled = false; 658 intel_crtc_wait_for_next_vblank(crtc); 659 } 660 661 /* 662 * Vblank time updates from the shadow to live plane control register 663 * are blocked if the memory self-refresh mode is active at that 664 * moment. So to make sure the plane gets truly disabled, disable 665 * first the self-refresh mode. The self-refresh enable bit in turn 666 * will be checked/applied by the HW only at the next frame start 667 * event which is after the vblank start event, so we need to have a 668 * wait-for-vblank between disabling the plane and the pipe. 669 */ 670 if (HAS_GMCH(dev_priv) && 671 intel_set_memory_cxsr(dev_priv, false)) 672 intel_crtc_wait_for_next_vblank(crtc); 673 674 /* 675 * Gen2 reports pipe underruns whenever all planes are disabled. 676 * So disable underrun reporting before all the planes get disabled. 677 */ 678 if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes) 679 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); 680 681 intel_plane_disable_arm(plane, crtc_state); 682 intel_crtc_wait_for_next_vblank(crtc); 683 } 684 685 unsigned int 686 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state) 687 { 688 int x = 0, y = 0; 689 690 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, 691 plane_state->view.color_plane[0].offset, 0); 692 693 return y; 694 } 695 696 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) 697 { 698 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 699 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 700 enum pipe pipe = crtc->pipe; 701 u32 tmp; 702 703 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe)); 704 705 /* 706 * Display WA #1153: icl 707 * enable hardware to bypass the alpha math 708 * and rounding for per-pixel values 00 and 0xff 709 */ 710 tmp |= PER_PIXEL_ALPHA_BYPASS_EN; 711 /* 712 * Display WA # 1605353570: icl 713 * Set the pixel rounding bit to 1 for allowing 714 * passthrough of Frame buffer pixels unmodified 715 * across pipe 716 */ 717 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU; 718 719 /* 720 * Underrun recovery must always be disabled on display 13+. 721 * DG2 chicken bit meaning is inverted compared to other platforms. 722 */ 723 if (IS_DG2(dev_priv)) 724 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2; 725 else if (DISPLAY_VER(dev_priv) >= 13) 726 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP; 727 728 /* Wa_14010547955:dg2 */ 729 if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER)) 730 tmp |= DG2_RENDER_CCSTAG_4_3_EN; 731 732 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp); 733 } 734 735 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) 736 { 737 struct drm_crtc *crtc; 738 bool cleanup_done; 739 740 drm_for_each_crtc(crtc, &dev_priv->drm) { 741 struct drm_crtc_commit *commit; 742 spin_lock(&crtc->commit_lock); 743 commit = list_first_entry_or_null(&crtc->commit_list, 744 struct drm_crtc_commit, commit_entry); 745 cleanup_done = commit ? 746 try_wait_for_completion(&commit->cleanup_done) : true; 747 spin_unlock(&crtc->commit_lock); 748 749 if (cleanup_done) 750 continue; 751 752 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc)); 753 754 return true; 755 } 756 757 return false; 758 } 759 760 /* 761 * Finds the encoder associated with the given CRTC. This can only be 762 * used when we know that the CRTC isn't feeding multiple encoders! 763 */ 764 struct intel_encoder * 765 intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 766 const struct intel_crtc_state *crtc_state) 767 { 768 const struct drm_connector_state *connector_state; 769 const struct drm_connector *connector; 770 struct intel_encoder *encoder = NULL; 771 struct intel_crtc *master_crtc; 772 int num_encoders = 0; 773 int i; 774 775 master_crtc = intel_master_crtc(crtc_state); 776 777 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 778 if (connector_state->crtc != &master_crtc->base) 779 continue; 780 781 encoder = to_intel_encoder(connector_state->best_encoder); 782 num_encoders++; 783 } 784 785 drm_WARN(state->base.dev, num_encoders != 1, 786 "%d encoders for pipe %c\n", 787 num_encoders, pipe_name(master_crtc->pipe)); 788 789 return encoder; 790 } 791 792 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state) 793 { 794 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 795 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 796 const struct drm_rect *dst = &crtc_state->pch_pfit.dst; 797 enum pipe pipe = crtc->pipe; 798 int width = drm_rect_width(dst); 799 int height = drm_rect_height(dst); 800 int x = dst->x1; 801 int y = dst->y1; 802 803 if (!crtc_state->pch_pfit.enabled) 804 return; 805 806 /* Force use of hard-coded filter coefficients 807 * as some pre-programmed values are broken, 808 * e.g. x201. 809 */ 810 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) 811 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 812 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe)); 813 else 814 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 815 PF_FILTER_MED_3x3); 816 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 817 PF_WIN_XPOS(x) | PF_WIN_YPOS(y)); 818 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 819 PF_WIN_XSIZE(width) | PF_WIN_YSIZE(height)); 820 } 821 822 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc) 823 { 824 if (crtc->overlay) 825 (void) intel_overlay_switch_off(crtc->overlay); 826 827 /* Let userspace switch the overlay on again. In most cases userspace 828 * has to recompute where to put it anyway. 829 */ 830 } 831 832 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state) 833 { 834 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 835 836 if (!crtc_state->nv12_planes) 837 return false; 838 839 /* WA Display #0827: Gen9:all */ 840 if (DISPLAY_VER(dev_priv) == 9) 841 return true; 842 843 return false; 844 } 845 846 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state) 847 { 848 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 849 850 /* Wa_2006604312:icl,ehl */ 851 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11) 852 return true; 853 854 return false; 855 } 856 857 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state) 858 { 859 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 860 861 /* Wa_1604331009:icl,jsl,ehl */ 862 if (is_hdr_mode(crtc_state) && 863 crtc_state->active_planes & BIT(PLANE_CURSOR) && 864 DISPLAY_VER(dev_priv) == 11) 865 return true; 866 867 return false; 868 } 869 870 static void intel_async_flip_vtd_wa(struct drm_i915_private *i915, 871 enum pipe pipe, bool enable) 872 { 873 if (DISPLAY_VER(i915) == 9) { 874 /* 875 * "Plane N strech max must be programmed to 11b (x1) 876 * when Async flips are enabled on that plane." 877 */ 878 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 879 SKL_PLANE1_STRETCH_MAX_MASK, 880 enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8); 881 } else { 882 /* Also needed on HSW/BDW albeit undocumented */ 883 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 884 HSW_PRI_STRETCH_MAX_MASK, 885 enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8); 886 } 887 } 888 889 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state) 890 { 891 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 892 893 return crtc_state->uapi.async_flip && i915_vtd_active(i915) && 894 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915)); 895 } 896 897 #define is_enabling(feature, old_crtc_state, new_crtc_state) \ 898 ((!(old_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)) && \ 899 (new_crtc_state)->feature) 900 #define is_disabling(feature, old_crtc_state, new_crtc_state) \ 901 ((old_crtc_state)->feature && \ 902 (!(new_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state))) 903 904 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state, 905 const struct intel_crtc_state *new_crtc_state) 906 { 907 return is_enabling(active_planes, old_crtc_state, new_crtc_state); 908 } 909 910 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state, 911 const struct intel_crtc_state *new_crtc_state) 912 { 913 return is_disabling(active_planes, old_crtc_state, new_crtc_state); 914 } 915 916 static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state, 917 const struct intel_crtc_state *new_crtc_state) 918 { 919 return is_enabling(vrr.enable, old_crtc_state, new_crtc_state); 920 } 921 922 static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state, 923 const struct intel_crtc_state *new_crtc_state) 924 { 925 return is_disabling(vrr.enable, old_crtc_state, new_crtc_state); 926 } 927 928 #undef is_disabling 929 #undef is_enabling 930 931 static void intel_post_plane_update(struct intel_atomic_state *state, 932 struct intel_crtc *crtc) 933 { 934 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 935 const struct intel_crtc_state *old_crtc_state = 936 intel_atomic_get_old_crtc_state(state, crtc); 937 const struct intel_crtc_state *new_crtc_state = 938 intel_atomic_get_new_crtc_state(state, crtc); 939 enum pipe pipe = crtc->pipe; 940 941 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); 942 943 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) 944 intel_update_watermarks(dev_priv); 945 946 intel_fbc_post_update(state, crtc); 947 948 if (needs_async_flip_vtd_wa(old_crtc_state) && 949 !needs_async_flip_vtd_wa(new_crtc_state)) 950 intel_async_flip_vtd_wa(dev_priv, pipe, false); 951 952 if (needs_nv12_wa(old_crtc_state) && 953 !needs_nv12_wa(new_crtc_state)) 954 skl_wa_827(dev_priv, pipe, false); 955 956 if (needs_scalerclk_wa(old_crtc_state) && 957 !needs_scalerclk_wa(new_crtc_state)) 958 icl_wa_scalerclkgating(dev_priv, pipe, false); 959 960 if (needs_cursorclk_wa(old_crtc_state) && 961 !needs_cursorclk_wa(new_crtc_state)) 962 icl_wa_cursorclkgating(dev_priv, pipe, false); 963 964 if (intel_crtc_needs_color_update(new_crtc_state)) 965 intel_color_post_update(new_crtc_state); 966 } 967 968 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state, 969 struct intel_crtc *crtc) 970 { 971 const struct intel_crtc_state *crtc_state = 972 intel_atomic_get_new_crtc_state(state, crtc); 973 u8 update_planes = crtc_state->update_planes; 974 const struct intel_plane_state *plane_state; 975 struct intel_plane *plane; 976 int i; 977 978 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 979 if (plane->pipe == crtc->pipe && 980 update_planes & BIT(plane->id)) 981 plane->enable_flip_done(plane); 982 } 983 } 984 985 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state, 986 struct intel_crtc *crtc) 987 { 988 const struct intel_crtc_state *crtc_state = 989 intel_atomic_get_new_crtc_state(state, crtc); 990 u8 update_planes = crtc_state->update_planes; 991 const struct intel_plane_state *plane_state; 992 struct intel_plane *plane; 993 int i; 994 995 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 996 if (plane->pipe == crtc->pipe && 997 update_planes & BIT(plane->id)) 998 plane->disable_flip_done(plane); 999 } 1000 } 1001 1002 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state, 1003 struct intel_crtc *crtc) 1004 { 1005 const struct intel_crtc_state *old_crtc_state = 1006 intel_atomic_get_old_crtc_state(state, crtc); 1007 const struct intel_crtc_state *new_crtc_state = 1008 intel_atomic_get_new_crtc_state(state, crtc); 1009 u8 disable_async_flip_planes = old_crtc_state->async_flip_planes & 1010 ~new_crtc_state->async_flip_planes; 1011 const struct intel_plane_state *old_plane_state; 1012 struct intel_plane *plane; 1013 bool need_vbl_wait = false; 1014 int i; 1015 1016 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1017 if (plane->need_async_flip_disable_wa && 1018 plane->pipe == crtc->pipe && 1019 disable_async_flip_planes & BIT(plane->id)) { 1020 /* 1021 * Apart from the async flip bit we want to 1022 * preserve the old state for the plane. 1023 */ 1024 plane->async_flip(plane, old_crtc_state, 1025 old_plane_state, false); 1026 need_vbl_wait = true; 1027 } 1028 } 1029 1030 if (need_vbl_wait) 1031 intel_crtc_wait_for_next_vblank(crtc); 1032 } 1033 1034 static void intel_pre_plane_update(struct intel_atomic_state *state, 1035 struct intel_crtc *crtc) 1036 { 1037 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1038 const struct intel_crtc_state *old_crtc_state = 1039 intel_atomic_get_old_crtc_state(state, crtc); 1040 const struct intel_crtc_state *new_crtc_state = 1041 intel_atomic_get_new_crtc_state(state, crtc); 1042 enum pipe pipe = crtc->pipe; 1043 1044 if (vrr_disabling(old_crtc_state, new_crtc_state)) { 1045 intel_vrr_disable(old_crtc_state); 1046 intel_crtc_update_active_timings(old_crtc_state, false); 1047 } 1048 1049 intel_drrs_deactivate(old_crtc_state); 1050 1051 intel_psr_pre_plane_update(state, crtc); 1052 1053 if (hsw_ips_pre_update(state, crtc)) 1054 intel_crtc_wait_for_next_vblank(crtc); 1055 1056 if (intel_fbc_pre_update(state, crtc)) 1057 intel_crtc_wait_for_next_vblank(crtc); 1058 1059 if (!needs_async_flip_vtd_wa(old_crtc_state) && 1060 needs_async_flip_vtd_wa(new_crtc_state)) 1061 intel_async_flip_vtd_wa(dev_priv, pipe, true); 1062 1063 /* Display WA 827 */ 1064 if (!needs_nv12_wa(old_crtc_state) && 1065 needs_nv12_wa(new_crtc_state)) 1066 skl_wa_827(dev_priv, pipe, true); 1067 1068 /* Wa_2006604312:icl,ehl */ 1069 if (!needs_scalerclk_wa(old_crtc_state) && 1070 needs_scalerclk_wa(new_crtc_state)) 1071 icl_wa_scalerclkgating(dev_priv, pipe, true); 1072 1073 /* Wa_1604331009:icl,jsl,ehl */ 1074 if (!needs_cursorclk_wa(old_crtc_state) && 1075 needs_cursorclk_wa(new_crtc_state)) 1076 icl_wa_cursorclkgating(dev_priv, pipe, true); 1077 1078 /* 1079 * Vblank time updates from the shadow to live plane control register 1080 * are blocked if the memory self-refresh mode is active at that 1081 * moment. So to make sure the plane gets truly disabled, disable 1082 * first the self-refresh mode. The self-refresh enable bit in turn 1083 * will be checked/applied by the HW only at the next frame start 1084 * event which is after the vblank start event, so we need to have a 1085 * wait-for-vblank between disabling the plane and the pipe. 1086 */ 1087 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active && 1088 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) 1089 intel_crtc_wait_for_next_vblank(crtc); 1090 1091 /* 1092 * IVB workaround: must disable low power watermarks for at least 1093 * one frame before enabling scaling. LP watermarks can be re-enabled 1094 * when scaling is disabled. 1095 * 1096 * WaCxSRDisabledForSpriteScaling:ivb 1097 */ 1098 if (old_crtc_state->hw.active && 1099 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv)) 1100 intel_crtc_wait_for_next_vblank(crtc); 1101 1102 /* 1103 * If we're doing a modeset we don't need to do any 1104 * pre-vblank watermark programming here. 1105 */ 1106 if (!intel_crtc_needs_modeset(new_crtc_state)) { 1107 /* 1108 * For platforms that support atomic watermarks, program the 1109 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these 1110 * will be the intermediate values that are safe for both pre- and 1111 * post- vblank; when vblank happens, the 'active' values will be set 1112 * to the final 'target' values and we'll do this again to get the 1113 * optimal watermarks. For gen9+ platforms, the values we program here 1114 * will be the final target values which will get automatically latched 1115 * at vblank time; no further programming will be necessary. 1116 * 1117 * If a platform hasn't been transitioned to atomic watermarks yet, 1118 * we'll continue to update watermarks the old way, if flags tell 1119 * us to. 1120 */ 1121 if (!intel_initial_watermarks(state, crtc)) 1122 if (new_crtc_state->update_wm_pre) 1123 intel_update_watermarks(dev_priv); 1124 } 1125 1126 /* 1127 * Gen2 reports pipe underruns whenever all planes are disabled. 1128 * So disable underrun reporting before all the planes get disabled. 1129 * 1130 * We do this after .initial_watermarks() so that we have a 1131 * chance of catching underruns with the intermediate watermarks 1132 * vs. the old plane configuration. 1133 */ 1134 if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state)) 1135 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1136 1137 /* 1138 * WA for platforms where async address update enable bit 1139 * is double buffered and only latched at start of vblank. 1140 */ 1141 if (old_crtc_state->async_flip_planes & ~new_crtc_state->async_flip_planes) 1142 intel_crtc_async_flip_disable_wa(state, crtc); 1143 } 1144 1145 static void intel_crtc_disable_planes(struct intel_atomic_state *state, 1146 struct intel_crtc *crtc) 1147 { 1148 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1149 const struct intel_crtc_state *new_crtc_state = 1150 intel_atomic_get_new_crtc_state(state, crtc); 1151 unsigned int update_mask = new_crtc_state->update_planes; 1152 const struct intel_plane_state *old_plane_state; 1153 struct intel_plane *plane; 1154 unsigned fb_bits = 0; 1155 int i; 1156 1157 intel_crtc_dpms_overlay_disable(crtc); 1158 1159 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1160 if (crtc->pipe != plane->pipe || 1161 !(update_mask & BIT(plane->id))) 1162 continue; 1163 1164 intel_plane_disable_arm(plane, new_crtc_state); 1165 1166 if (old_plane_state->uapi.visible) 1167 fb_bits |= plane->frontbuffer_bit; 1168 } 1169 1170 intel_frontbuffer_flip(dev_priv, fb_bits); 1171 } 1172 1173 static void intel_encoders_update_prepare(struct intel_atomic_state *state) 1174 { 1175 struct drm_i915_private *i915 = to_i915(state->base.dev); 1176 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 1177 struct intel_crtc *crtc; 1178 int i; 1179 1180 /* 1181 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits. 1182 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook. 1183 */ 1184 if (i915->display.dpll.mgr) { 1185 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1186 if (intel_crtc_needs_modeset(new_crtc_state)) 1187 continue; 1188 1189 new_crtc_state->shared_dpll = old_crtc_state->shared_dpll; 1190 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state; 1191 } 1192 } 1193 } 1194 1195 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state, 1196 struct intel_crtc *crtc) 1197 { 1198 const struct intel_crtc_state *crtc_state = 1199 intel_atomic_get_new_crtc_state(state, crtc); 1200 const struct drm_connector_state *conn_state; 1201 struct drm_connector *conn; 1202 int i; 1203 1204 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1205 struct intel_encoder *encoder = 1206 to_intel_encoder(conn_state->best_encoder); 1207 1208 if (conn_state->crtc != &crtc->base) 1209 continue; 1210 1211 if (encoder->pre_pll_enable) 1212 encoder->pre_pll_enable(state, encoder, 1213 crtc_state, conn_state); 1214 } 1215 } 1216 1217 static void intel_encoders_pre_enable(struct intel_atomic_state *state, 1218 struct intel_crtc *crtc) 1219 { 1220 const struct intel_crtc_state *crtc_state = 1221 intel_atomic_get_new_crtc_state(state, crtc); 1222 const struct drm_connector_state *conn_state; 1223 struct drm_connector *conn; 1224 int i; 1225 1226 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1227 struct intel_encoder *encoder = 1228 to_intel_encoder(conn_state->best_encoder); 1229 1230 if (conn_state->crtc != &crtc->base) 1231 continue; 1232 1233 if (encoder->pre_enable) 1234 encoder->pre_enable(state, encoder, 1235 crtc_state, conn_state); 1236 } 1237 } 1238 1239 static void intel_encoders_enable(struct intel_atomic_state *state, 1240 struct intel_crtc *crtc) 1241 { 1242 const struct intel_crtc_state *crtc_state = 1243 intel_atomic_get_new_crtc_state(state, crtc); 1244 const struct drm_connector_state *conn_state; 1245 struct drm_connector *conn; 1246 int i; 1247 1248 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1249 struct intel_encoder *encoder = 1250 to_intel_encoder(conn_state->best_encoder); 1251 1252 if (conn_state->crtc != &crtc->base) 1253 continue; 1254 1255 if (encoder->enable) 1256 encoder->enable(state, encoder, 1257 crtc_state, conn_state); 1258 intel_opregion_notify_encoder(encoder, true); 1259 } 1260 } 1261 1262 static void intel_encoders_disable(struct intel_atomic_state *state, 1263 struct intel_crtc *crtc) 1264 { 1265 const struct intel_crtc_state *old_crtc_state = 1266 intel_atomic_get_old_crtc_state(state, crtc); 1267 const struct drm_connector_state *old_conn_state; 1268 struct drm_connector *conn; 1269 int i; 1270 1271 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1272 struct intel_encoder *encoder = 1273 to_intel_encoder(old_conn_state->best_encoder); 1274 1275 if (old_conn_state->crtc != &crtc->base) 1276 continue; 1277 1278 intel_opregion_notify_encoder(encoder, false); 1279 if (encoder->disable) 1280 encoder->disable(state, encoder, 1281 old_crtc_state, old_conn_state); 1282 } 1283 } 1284 1285 static void intel_encoders_post_disable(struct intel_atomic_state *state, 1286 struct intel_crtc *crtc) 1287 { 1288 const struct intel_crtc_state *old_crtc_state = 1289 intel_atomic_get_old_crtc_state(state, crtc); 1290 const struct drm_connector_state *old_conn_state; 1291 struct drm_connector *conn; 1292 int i; 1293 1294 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1295 struct intel_encoder *encoder = 1296 to_intel_encoder(old_conn_state->best_encoder); 1297 1298 if (old_conn_state->crtc != &crtc->base) 1299 continue; 1300 1301 if (encoder->post_disable) 1302 encoder->post_disable(state, encoder, 1303 old_crtc_state, old_conn_state); 1304 } 1305 } 1306 1307 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state, 1308 struct intel_crtc *crtc) 1309 { 1310 const struct intel_crtc_state *old_crtc_state = 1311 intel_atomic_get_old_crtc_state(state, crtc); 1312 const struct drm_connector_state *old_conn_state; 1313 struct drm_connector *conn; 1314 int i; 1315 1316 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1317 struct intel_encoder *encoder = 1318 to_intel_encoder(old_conn_state->best_encoder); 1319 1320 if (old_conn_state->crtc != &crtc->base) 1321 continue; 1322 1323 if (encoder->post_pll_disable) 1324 encoder->post_pll_disable(state, encoder, 1325 old_crtc_state, old_conn_state); 1326 } 1327 } 1328 1329 static void intel_encoders_update_pipe(struct intel_atomic_state *state, 1330 struct intel_crtc *crtc) 1331 { 1332 const struct intel_crtc_state *crtc_state = 1333 intel_atomic_get_new_crtc_state(state, crtc); 1334 const struct drm_connector_state *conn_state; 1335 struct drm_connector *conn; 1336 int i; 1337 1338 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1339 struct intel_encoder *encoder = 1340 to_intel_encoder(conn_state->best_encoder); 1341 1342 if (conn_state->crtc != &crtc->base) 1343 continue; 1344 1345 if (encoder->update_pipe) 1346 encoder->update_pipe(state, encoder, 1347 crtc_state, conn_state); 1348 } 1349 } 1350 1351 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state) 1352 { 1353 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1354 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 1355 1356 plane->disable_arm(plane, crtc_state); 1357 } 1358 1359 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1360 { 1361 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1362 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1363 1364 if (crtc_state->has_pch_encoder) { 1365 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1366 &crtc_state->fdi_m_n); 1367 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1368 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1369 &crtc_state->dp_m_n); 1370 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1371 &crtc_state->dp_m2_n2); 1372 } 1373 1374 intel_set_transcoder_timings(crtc_state); 1375 1376 ilk_set_pipeconf(crtc_state); 1377 } 1378 1379 static void ilk_crtc_enable(struct intel_atomic_state *state, 1380 struct intel_crtc *crtc) 1381 { 1382 const struct intel_crtc_state *new_crtc_state = 1383 intel_atomic_get_new_crtc_state(state, crtc); 1384 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1385 enum pipe pipe = crtc->pipe; 1386 1387 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1388 return; 1389 1390 /* 1391 * Sometimes spurious CPU pipe underruns happen during FDI 1392 * training, at least with VGA+HDMI cloning. Suppress them. 1393 * 1394 * On ILK we get an occasional spurious CPU pipe underruns 1395 * between eDP port A enable and vdd enable. Also PCH port 1396 * enable seems to result in the occasional CPU pipe underrun. 1397 * 1398 * Spurious PCH underruns also occur during PCH enabling. 1399 */ 1400 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1401 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 1402 1403 ilk_configure_cpu_transcoder(new_crtc_state); 1404 1405 intel_set_pipe_src_size(new_crtc_state); 1406 1407 crtc->active = true; 1408 1409 intel_encoders_pre_enable(state, crtc); 1410 1411 if (new_crtc_state->has_pch_encoder) { 1412 ilk_pch_pre_enable(state, crtc); 1413 } else { 1414 assert_fdi_tx_disabled(dev_priv, pipe); 1415 assert_fdi_rx_disabled(dev_priv, pipe); 1416 } 1417 1418 ilk_pfit_enable(new_crtc_state); 1419 1420 /* 1421 * On ILK+ LUT must be loaded before the pipe is running but with 1422 * clocks enabled 1423 */ 1424 intel_color_load_luts(new_crtc_state); 1425 intel_color_commit_noarm(new_crtc_state); 1426 intel_color_commit_arm(new_crtc_state); 1427 /* update DSPCNTR to configure gamma for pipe bottom color */ 1428 intel_disable_primary_plane(new_crtc_state); 1429 1430 intel_initial_watermarks(state, crtc); 1431 intel_enable_transcoder(new_crtc_state); 1432 1433 if (new_crtc_state->has_pch_encoder) 1434 ilk_pch_enable(state, crtc); 1435 1436 intel_crtc_vblank_on(new_crtc_state); 1437 1438 intel_encoders_enable(state, crtc); 1439 1440 if (HAS_PCH_CPT(dev_priv)) 1441 intel_wait_for_pipe_scanline_moving(crtc); 1442 1443 /* 1444 * Must wait for vblank to avoid spurious PCH FIFO underruns. 1445 * And a second vblank wait is needed at least on ILK with 1446 * some interlaced HDMI modes. Let's do the double wait always 1447 * in case there are more corner cases we don't know about. 1448 */ 1449 if (new_crtc_state->has_pch_encoder) { 1450 intel_crtc_wait_for_next_vblank(crtc); 1451 intel_crtc_wait_for_next_vblank(crtc); 1452 } 1453 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1454 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 1455 } 1456 1457 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, 1458 enum pipe pipe, bool apply) 1459 { 1460 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)); 1461 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS; 1462 1463 if (apply) 1464 val |= mask; 1465 else 1466 val &= ~mask; 1467 1468 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val); 1469 } 1470 1471 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state) 1472 { 1473 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1474 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1475 1476 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe), 1477 HSW_LINETIME(crtc_state->linetime) | 1478 HSW_IPS_LINETIME(crtc_state->ips_linetime)); 1479 } 1480 1481 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) 1482 { 1483 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1484 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1485 enum transcoder transcoder = crtc_state->cpu_transcoder; 1486 i915_reg_t reg = DISPLAY_VER(dev_priv) >= 14 ? MTL_CHICKEN_TRANS(transcoder) : 1487 CHICKEN_TRANS(transcoder); 1488 1489 intel_de_rmw(dev_priv, reg, 1490 HSW_FRAME_START_DELAY_MASK, 1491 HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1)); 1492 } 1493 1494 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state, 1495 const struct intel_crtc_state *crtc_state) 1496 { 1497 struct intel_crtc *master_crtc = intel_master_crtc(crtc_state); 1498 1499 /* 1500 * Enable sequence steps 1-7 on bigjoiner master 1501 */ 1502 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1503 intel_encoders_pre_pll_enable(state, master_crtc); 1504 1505 if (crtc_state->shared_dpll) 1506 intel_enable_shared_dpll(crtc_state); 1507 1508 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1509 intel_encoders_pre_enable(state, master_crtc); 1510 } 1511 1512 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1513 { 1514 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1515 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1516 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1517 1518 if (crtc_state->has_pch_encoder) { 1519 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1520 &crtc_state->fdi_m_n); 1521 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1522 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1523 &crtc_state->dp_m_n); 1524 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1525 &crtc_state->dp_m2_n2); 1526 } 1527 1528 intel_set_transcoder_timings(crtc_state); 1529 if (HAS_VRR(dev_priv)) 1530 intel_vrr_set_transcoder_timings(crtc_state); 1531 1532 if (cpu_transcoder != TRANSCODER_EDP) 1533 intel_de_write(dev_priv, TRANS_MULT(cpu_transcoder), 1534 crtc_state->pixel_multiplier - 1); 1535 1536 hsw_set_frame_start_delay(crtc_state); 1537 1538 hsw_set_transconf(crtc_state); 1539 } 1540 1541 static void hsw_crtc_enable(struct intel_atomic_state *state, 1542 struct intel_crtc *crtc) 1543 { 1544 const struct intel_crtc_state *new_crtc_state = 1545 intel_atomic_get_new_crtc_state(state, crtc); 1546 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1547 enum pipe pipe = crtc->pipe, hsw_workaround_pipe; 1548 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 1549 bool psl_clkgate_wa; 1550 1551 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1552 return; 1553 1554 intel_dmc_enable_pipe(dev_priv, crtc->pipe); 1555 1556 if (!new_crtc_state->bigjoiner_pipes) { 1557 intel_encoders_pre_pll_enable(state, crtc); 1558 1559 if (new_crtc_state->shared_dpll) 1560 intel_enable_shared_dpll(new_crtc_state); 1561 1562 intel_encoders_pre_enable(state, crtc); 1563 } else { 1564 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state); 1565 } 1566 1567 intel_dsc_enable(new_crtc_state); 1568 1569 if (DISPLAY_VER(dev_priv) >= 13) 1570 intel_uncompressed_joiner_enable(new_crtc_state); 1571 1572 intel_set_pipe_src_size(new_crtc_state); 1573 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 1574 bdw_set_pipe_misc(new_crtc_state); 1575 1576 if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) && 1577 !transcoder_is_dsi(cpu_transcoder)) 1578 hsw_configure_cpu_transcoder(new_crtc_state); 1579 1580 crtc->active = true; 1581 1582 /* Display WA #1180: WaDisableScalarClockGating: glk */ 1583 psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 && 1584 new_crtc_state->pch_pfit.enabled; 1585 if (psl_clkgate_wa) 1586 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true); 1587 1588 if (DISPLAY_VER(dev_priv) >= 9) 1589 skl_pfit_enable(new_crtc_state); 1590 else 1591 ilk_pfit_enable(new_crtc_state); 1592 1593 /* 1594 * On ILK+ LUT must be loaded before the pipe is running but with 1595 * clocks enabled 1596 */ 1597 intel_color_load_luts(new_crtc_state); 1598 intel_color_commit_noarm(new_crtc_state); 1599 intel_color_commit_arm(new_crtc_state); 1600 /* update DSPCNTR to configure gamma/csc for pipe bottom color */ 1601 if (DISPLAY_VER(dev_priv) < 9) 1602 intel_disable_primary_plane(new_crtc_state); 1603 1604 hsw_set_linetime_wm(new_crtc_state); 1605 1606 if (DISPLAY_VER(dev_priv) >= 11) 1607 icl_set_pipe_chicken(new_crtc_state); 1608 1609 intel_initial_watermarks(state, crtc); 1610 1611 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 1612 intel_crtc_vblank_on(new_crtc_state); 1613 1614 intel_encoders_enable(state, crtc); 1615 1616 if (psl_clkgate_wa) { 1617 intel_crtc_wait_for_next_vblank(crtc); 1618 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false); 1619 } 1620 1621 /* If we change the relative order between pipe/planes enabling, we need 1622 * to change the workaround. */ 1623 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe; 1624 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { 1625 struct intel_crtc *wa_crtc; 1626 1627 wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe); 1628 1629 intel_crtc_wait_for_next_vblank(wa_crtc); 1630 intel_crtc_wait_for_next_vblank(wa_crtc); 1631 } 1632 } 1633 1634 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state) 1635 { 1636 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1637 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1638 enum pipe pipe = crtc->pipe; 1639 1640 /* To avoid upsetting the power well on haswell only disable the pfit if 1641 * it's in use. The hw state code will make sure we get this right. */ 1642 if (!old_crtc_state->pch_pfit.enabled) 1643 return; 1644 1645 intel_de_write_fw(dev_priv, PF_CTL(pipe), 0); 1646 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0); 1647 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0); 1648 } 1649 1650 static void ilk_crtc_disable(struct intel_atomic_state *state, 1651 struct intel_crtc *crtc) 1652 { 1653 const struct intel_crtc_state *old_crtc_state = 1654 intel_atomic_get_old_crtc_state(state, crtc); 1655 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1656 enum pipe pipe = crtc->pipe; 1657 1658 /* 1659 * Sometimes spurious CPU pipe underruns happen when the 1660 * pipe is already disabled, but FDI RX/TX is still enabled. 1661 * Happens at least with VGA+HDMI cloning. Suppress them. 1662 */ 1663 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1664 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 1665 1666 intel_encoders_disable(state, crtc); 1667 1668 intel_crtc_vblank_off(old_crtc_state); 1669 1670 intel_disable_transcoder(old_crtc_state); 1671 1672 ilk_pfit_disable(old_crtc_state); 1673 1674 if (old_crtc_state->has_pch_encoder) 1675 ilk_pch_disable(state, crtc); 1676 1677 intel_encoders_post_disable(state, crtc); 1678 1679 if (old_crtc_state->has_pch_encoder) 1680 ilk_pch_post_disable(state, crtc); 1681 1682 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1683 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 1684 1685 intel_disable_shared_dpll(old_crtc_state); 1686 } 1687 1688 static void hsw_crtc_disable(struct intel_atomic_state *state, 1689 struct intel_crtc *crtc) 1690 { 1691 const struct intel_crtc_state *old_crtc_state = 1692 intel_atomic_get_old_crtc_state(state, crtc); 1693 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 1694 1695 /* 1696 * FIXME collapse everything to one hook. 1697 * Need care with mst->ddi interactions. 1698 */ 1699 if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) { 1700 intel_encoders_disable(state, crtc); 1701 intel_encoders_post_disable(state, crtc); 1702 } 1703 1704 intel_disable_shared_dpll(old_crtc_state); 1705 1706 if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) { 1707 struct intel_crtc *slave_crtc; 1708 1709 intel_encoders_post_pll_disable(state, crtc); 1710 1711 intel_dmc_disable_pipe(i915, crtc->pipe); 1712 1713 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 1714 intel_crtc_bigjoiner_slave_pipes(old_crtc_state)) 1715 intel_dmc_disable_pipe(i915, slave_crtc->pipe); 1716 } 1717 } 1718 1719 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) 1720 { 1721 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1722 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1723 1724 if (!crtc_state->gmch_pfit.control) 1725 return; 1726 1727 /* 1728 * The panel fitter should only be adjusted whilst the pipe is disabled, 1729 * according to register description and PRM. 1730 */ 1731 drm_WARN_ON(&dev_priv->drm, 1732 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE); 1733 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 1734 1735 intel_de_write(dev_priv, PFIT_PGM_RATIOS, 1736 crtc_state->gmch_pfit.pgm_ratios); 1737 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control); 1738 1739 /* Border color in case we don't scale up to the full screen. Black by 1740 * default, change to something else for debugging. */ 1741 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); 1742 } 1743 1744 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) 1745 { 1746 if (phy == PHY_NONE) 1747 return false; 1748 else if (IS_ALDERLAKE_S(dev_priv)) 1749 return phy <= PHY_E; 1750 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) 1751 return phy <= PHY_D; 1752 else if (IS_JSL_EHL(dev_priv)) 1753 return phy <= PHY_C; 1754 else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12)) 1755 return phy <= PHY_B; 1756 else 1757 /* 1758 * DG2 outputs labelled as "combo PHY" in the bspec use 1759 * SNPS PHYs with completely different programming, 1760 * hence we always return false here. 1761 */ 1762 return false; 1763 } 1764 1765 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) 1766 { 1767 if (IS_DG2(dev_priv)) 1768 /* DG2's "TC1" output uses a SNPS PHY */ 1769 return false; 1770 else if (IS_ALDERLAKE_P(dev_priv) || IS_METEORLAKE(dev_priv)) 1771 return phy >= PHY_F && phy <= PHY_I; 1772 else if (IS_TIGERLAKE(dev_priv)) 1773 return phy >= PHY_D && phy <= PHY_I; 1774 else if (IS_ICELAKE(dev_priv)) 1775 return phy >= PHY_C && phy <= PHY_F; 1776 else 1777 return false; 1778 } 1779 1780 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy) 1781 { 1782 if (phy == PHY_NONE) 1783 return false; 1784 else if (IS_DG2(dev_priv)) 1785 /* 1786 * All four "combo" ports and the TC1 port (PHY E) use 1787 * Synopsis PHYs. 1788 */ 1789 return phy <= PHY_E; 1790 1791 return false; 1792 } 1793 1794 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) 1795 { 1796 if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD) 1797 return PHY_D + port - PORT_D_XELPD; 1798 else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1) 1799 return PHY_F + port - PORT_TC1; 1800 else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1) 1801 return PHY_B + port - PORT_TC1; 1802 else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1) 1803 return PHY_C + port - PORT_TC1; 1804 else if (IS_JSL_EHL(i915) && port == PORT_D) 1805 return PHY_A; 1806 1807 return PHY_A + port - PORT_A; 1808 } 1809 1810 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) 1811 { 1812 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port))) 1813 return TC_PORT_NONE; 1814 1815 if (DISPLAY_VER(dev_priv) >= 12) 1816 return TC_PORT_1 + port - PORT_TC1; 1817 else 1818 return TC_PORT_1 + port - PORT_C; 1819 } 1820 1821 enum intel_display_power_domain 1822 intel_aux_power_domain(struct intel_digital_port *dig_port) 1823 { 1824 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1825 1826 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 1827 return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch); 1828 1829 return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch); 1830 } 1831 1832 static void get_crtc_power_domains(struct intel_crtc_state *crtc_state, 1833 struct intel_power_domain_mask *mask) 1834 { 1835 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1836 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1837 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1838 struct drm_encoder *encoder; 1839 enum pipe pipe = crtc->pipe; 1840 1841 bitmap_zero(mask->bits, POWER_DOMAIN_NUM); 1842 1843 if (!crtc_state->hw.active) 1844 return; 1845 1846 set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits); 1847 set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits); 1848 if (crtc_state->pch_pfit.enabled || 1849 crtc_state->pch_pfit.force_thru) 1850 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits); 1851 1852 drm_for_each_encoder_mask(encoder, &dev_priv->drm, 1853 crtc_state->uapi.encoder_mask) { 1854 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 1855 1856 set_bit(intel_encoder->power_domain, mask->bits); 1857 } 1858 1859 if (HAS_DDI(dev_priv) && crtc_state->has_audio) 1860 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits); 1861 1862 if (crtc_state->shared_dpll) 1863 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits); 1864 1865 if (crtc_state->dsc.compression_enable) 1866 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits); 1867 } 1868 1869 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, 1870 struct intel_power_domain_mask *old_domains) 1871 { 1872 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1873 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1874 enum intel_display_power_domain domain; 1875 struct intel_power_domain_mask domains, new_domains; 1876 1877 get_crtc_power_domains(crtc_state, &domains); 1878 1879 bitmap_andnot(new_domains.bits, 1880 domains.bits, 1881 crtc->enabled_power_domains.mask.bits, 1882 POWER_DOMAIN_NUM); 1883 bitmap_andnot(old_domains->bits, 1884 crtc->enabled_power_domains.mask.bits, 1885 domains.bits, 1886 POWER_DOMAIN_NUM); 1887 1888 for_each_power_domain(domain, &new_domains) 1889 intel_display_power_get_in_set(dev_priv, 1890 &crtc->enabled_power_domains, 1891 domain); 1892 } 1893 1894 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc, 1895 struct intel_power_domain_mask *domains) 1896 { 1897 intel_display_power_put_mask_in_set(to_i915(crtc->base.dev), 1898 &crtc->enabled_power_domains, 1899 domains); 1900 } 1901 1902 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1903 { 1904 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1905 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1906 1907 if (intel_crtc_has_dp_encoder(crtc_state)) { 1908 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1909 &crtc_state->dp_m_n); 1910 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1911 &crtc_state->dp_m2_n2); 1912 } 1913 1914 intel_set_transcoder_timings(crtc_state); 1915 1916 i9xx_set_pipeconf(crtc_state); 1917 } 1918 1919 static void valleyview_crtc_enable(struct intel_atomic_state *state, 1920 struct intel_crtc *crtc) 1921 { 1922 const struct intel_crtc_state *new_crtc_state = 1923 intel_atomic_get_new_crtc_state(state, crtc); 1924 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1925 enum pipe pipe = crtc->pipe; 1926 1927 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1928 return; 1929 1930 i9xx_configure_cpu_transcoder(new_crtc_state); 1931 1932 intel_set_pipe_src_size(new_crtc_state); 1933 1934 intel_de_write(dev_priv, VLV_PIPE_MSA_MISC(pipe), 0); 1935 1936 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 1937 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY); 1938 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0); 1939 } 1940 1941 crtc->active = true; 1942 1943 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1944 1945 intel_encoders_pre_pll_enable(state, crtc); 1946 1947 if (IS_CHERRYVIEW(dev_priv)) 1948 chv_enable_pll(new_crtc_state); 1949 else 1950 vlv_enable_pll(new_crtc_state); 1951 1952 intel_encoders_pre_enable(state, crtc); 1953 1954 i9xx_pfit_enable(new_crtc_state); 1955 1956 intel_color_load_luts(new_crtc_state); 1957 intel_color_commit_noarm(new_crtc_state); 1958 intel_color_commit_arm(new_crtc_state); 1959 /* update DSPCNTR to configure gamma for pipe bottom color */ 1960 intel_disable_primary_plane(new_crtc_state); 1961 1962 intel_initial_watermarks(state, crtc); 1963 intel_enable_transcoder(new_crtc_state); 1964 1965 intel_crtc_vblank_on(new_crtc_state); 1966 1967 intel_encoders_enable(state, crtc); 1968 } 1969 1970 static void i9xx_crtc_enable(struct intel_atomic_state *state, 1971 struct intel_crtc *crtc) 1972 { 1973 const struct intel_crtc_state *new_crtc_state = 1974 intel_atomic_get_new_crtc_state(state, crtc); 1975 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1976 enum pipe pipe = crtc->pipe; 1977 1978 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1979 return; 1980 1981 i9xx_configure_cpu_transcoder(new_crtc_state); 1982 1983 intel_set_pipe_src_size(new_crtc_state); 1984 1985 crtc->active = true; 1986 1987 if (DISPLAY_VER(dev_priv) != 2) 1988 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1989 1990 intel_encoders_pre_enable(state, crtc); 1991 1992 i9xx_enable_pll(new_crtc_state); 1993 1994 i9xx_pfit_enable(new_crtc_state); 1995 1996 intel_color_load_luts(new_crtc_state); 1997 intel_color_commit_noarm(new_crtc_state); 1998 intel_color_commit_arm(new_crtc_state); 1999 /* update DSPCNTR to configure gamma for pipe bottom color */ 2000 intel_disable_primary_plane(new_crtc_state); 2001 2002 if (!intel_initial_watermarks(state, crtc)) 2003 intel_update_watermarks(dev_priv); 2004 intel_enable_transcoder(new_crtc_state); 2005 2006 intel_crtc_vblank_on(new_crtc_state); 2007 2008 intel_encoders_enable(state, crtc); 2009 2010 /* prevents spurious underruns */ 2011 if (DISPLAY_VER(dev_priv) == 2) 2012 intel_crtc_wait_for_next_vblank(crtc); 2013 } 2014 2015 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) 2016 { 2017 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 2018 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2019 2020 if (!old_crtc_state->gmch_pfit.control) 2021 return; 2022 2023 assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder); 2024 2025 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n", 2026 intel_de_read(dev_priv, PFIT_CONTROL)); 2027 intel_de_write(dev_priv, PFIT_CONTROL, 0); 2028 } 2029 2030 static void i9xx_crtc_disable(struct intel_atomic_state *state, 2031 struct intel_crtc *crtc) 2032 { 2033 struct intel_crtc_state *old_crtc_state = 2034 intel_atomic_get_old_crtc_state(state, crtc); 2035 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2036 enum pipe pipe = crtc->pipe; 2037 2038 /* 2039 * On gen2 planes are double buffered but the pipe isn't, so we must 2040 * wait for planes to fully turn off before disabling the pipe. 2041 */ 2042 if (DISPLAY_VER(dev_priv) == 2) 2043 intel_crtc_wait_for_next_vblank(crtc); 2044 2045 intel_encoders_disable(state, crtc); 2046 2047 intel_crtc_vblank_off(old_crtc_state); 2048 2049 intel_disable_transcoder(old_crtc_state); 2050 2051 i9xx_pfit_disable(old_crtc_state); 2052 2053 intel_encoders_post_disable(state, crtc); 2054 2055 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) { 2056 if (IS_CHERRYVIEW(dev_priv)) 2057 chv_disable_pll(dev_priv, pipe); 2058 else if (IS_VALLEYVIEW(dev_priv)) 2059 vlv_disable_pll(dev_priv, pipe); 2060 else 2061 i9xx_disable_pll(old_crtc_state); 2062 } 2063 2064 intel_encoders_post_pll_disable(state, crtc); 2065 2066 if (DISPLAY_VER(dev_priv) != 2) 2067 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 2068 2069 if (!dev_priv->display.funcs.wm->initial_watermarks) 2070 intel_update_watermarks(dev_priv); 2071 2072 /* clock the pipe down to 640x480@60 to potentially save power */ 2073 if (IS_I830(dev_priv)) 2074 i830_enable_pipe(dev_priv, pipe); 2075 } 2076 2077 void intel_encoder_destroy(struct drm_encoder *encoder) 2078 { 2079 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2080 2081 drm_encoder_cleanup(encoder); 2082 kfree(intel_encoder); 2083 } 2084 2085 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) 2086 { 2087 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2088 2089 /* GDG double wide on either pipe, otherwise pipe A only */ 2090 return DISPLAY_VER(dev_priv) < 4 && 2091 (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); 2092 } 2093 2094 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) 2095 { 2096 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock; 2097 struct drm_rect src; 2098 2099 /* 2100 * We only use IF-ID interlacing. If we ever use 2101 * PF-ID we'll need to adjust the pixel_rate here. 2102 */ 2103 2104 if (!crtc_state->pch_pfit.enabled) 2105 return pixel_rate; 2106 2107 drm_rect_init(&src, 0, 0, 2108 drm_rect_width(&crtc_state->pipe_src) << 16, 2109 drm_rect_height(&crtc_state->pipe_src) << 16); 2110 2111 return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst, 2112 pixel_rate); 2113 } 2114 2115 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode, 2116 const struct drm_display_mode *timings) 2117 { 2118 mode->hdisplay = timings->crtc_hdisplay; 2119 mode->htotal = timings->crtc_htotal; 2120 mode->hsync_start = timings->crtc_hsync_start; 2121 mode->hsync_end = timings->crtc_hsync_end; 2122 2123 mode->vdisplay = timings->crtc_vdisplay; 2124 mode->vtotal = timings->crtc_vtotal; 2125 mode->vsync_start = timings->crtc_vsync_start; 2126 mode->vsync_end = timings->crtc_vsync_end; 2127 2128 mode->flags = timings->flags; 2129 mode->type = DRM_MODE_TYPE_DRIVER; 2130 2131 mode->clock = timings->crtc_clock; 2132 2133 drm_mode_set_name(mode); 2134 } 2135 2136 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) 2137 { 2138 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2139 2140 if (HAS_GMCH(dev_priv)) 2141 /* FIXME calculate proper pipe pixel rate for GMCH pfit */ 2142 crtc_state->pixel_rate = 2143 crtc_state->hw.pipe_mode.crtc_clock; 2144 else 2145 crtc_state->pixel_rate = 2146 ilk_pipe_pixel_rate(crtc_state); 2147 } 2148 2149 static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state *crtc_state, 2150 struct drm_display_mode *mode) 2151 { 2152 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2153 2154 if (num_pipes < 2) 2155 return; 2156 2157 mode->crtc_clock /= num_pipes; 2158 mode->crtc_hdisplay /= num_pipes; 2159 mode->crtc_hblank_start /= num_pipes; 2160 mode->crtc_hblank_end /= num_pipes; 2161 mode->crtc_hsync_start /= num_pipes; 2162 mode->crtc_hsync_end /= num_pipes; 2163 mode->crtc_htotal /= num_pipes; 2164 } 2165 2166 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state, 2167 struct drm_display_mode *mode) 2168 { 2169 int overlap = crtc_state->splitter.pixel_overlap; 2170 int n = crtc_state->splitter.link_count; 2171 2172 if (!crtc_state->splitter.enable) 2173 return; 2174 2175 /* 2176 * eDP MSO uses segment timings from EDID for transcoder 2177 * timings, but full mode for everything else. 2178 * 2179 * h_full = (h_segment - pixel_overlap) * link_count 2180 */ 2181 mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n; 2182 mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n; 2183 mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n; 2184 mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n; 2185 mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n; 2186 mode->crtc_htotal = (mode->crtc_htotal - overlap) * n; 2187 mode->crtc_clock *= n; 2188 } 2189 2190 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state) 2191 { 2192 struct drm_display_mode *mode = &crtc_state->hw.mode; 2193 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2194 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2195 2196 /* 2197 * Start with the adjusted_mode crtc timings, which 2198 * have been filled with the transcoder timings. 2199 */ 2200 drm_mode_copy(pipe_mode, adjusted_mode); 2201 2202 /* Expand MSO per-segment transcoder timings to full */ 2203 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2204 2205 /* 2206 * We want the full numbers in adjusted_mode normal timings, 2207 * adjusted_mode crtc timings are left with the raw transcoder 2208 * timings. 2209 */ 2210 intel_mode_from_crtc_timings(adjusted_mode, pipe_mode); 2211 2212 /* Populate the "user" mode with full numbers */ 2213 drm_mode_copy(mode, pipe_mode); 2214 intel_mode_from_crtc_timings(mode, mode); 2215 mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) * 2216 (intel_bigjoiner_num_pipes(crtc_state) ?: 1); 2217 mode->vdisplay = drm_rect_height(&crtc_state->pipe_src); 2218 2219 /* Derive per-pipe timings in case bigjoiner is used */ 2220 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2221 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2222 2223 intel_crtc_compute_pixel_rate(crtc_state); 2224 } 2225 2226 void intel_encoder_get_config(struct intel_encoder *encoder, 2227 struct intel_crtc_state *crtc_state) 2228 { 2229 encoder->get_config(encoder, crtc_state); 2230 2231 intel_crtc_readout_derived_state(crtc_state); 2232 } 2233 2234 static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state *crtc_state) 2235 { 2236 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2237 int width, height; 2238 2239 if (num_pipes < 2) 2240 return; 2241 2242 width = drm_rect_width(&crtc_state->pipe_src); 2243 height = drm_rect_height(&crtc_state->pipe_src); 2244 2245 drm_rect_init(&crtc_state->pipe_src, 0, 0, 2246 width / num_pipes, height); 2247 } 2248 2249 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state) 2250 { 2251 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2252 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2253 2254 intel_bigjoiner_compute_pipe_src(crtc_state); 2255 2256 /* 2257 * Pipe horizontal size must be even in: 2258 * - DVO ganged mode 2259 * - LVDS dual channel mode 2260 * - Double wide pipe 2261 */ 2262 if (drm_rect_width(&crtc_state->pipe_src) & 1) { 2263 if (crtc_state->double_wide) { 2264 drm_dbg_kms(&i915->drm, 2265 "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n", 2266 crtc->base.base.id, crtc->base.name); 2267 return -EINVAL; 2268 } 2269 2270 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 2271 intel_is_dual_link_lvds(i915)) { 2272 drm_dbg_kms(&i915->drm, 2273 "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n", 2274 crtc->base.base.id, crtc->base.name); 2275 return -EINVAL; 2276 } 2277 } 2278 2279 return 0; 2280 } 2281 2282 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state) 2283 { 2284 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2285 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2286 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2287 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2288 int clock_limit = i915->max_dotclk_freq; 2289 2290 /* 2291 * Start with the adjusted_mode crtc timings, which 2292 * have been filled with the transcoder timings. 2293 */ 2294 drm_mode_copy(pipe_mode, adjusted_mode); 2295 2296 /* Expand MSO per-segment transcoder timings to full */ 2297 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2298 2299 /* Derive per-pipe timings in case bigjoiner is used */ 2300 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2301 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2302 2303 if (DISPLAY_VER(i915) < 4) { 2304 clock_limit = i915->display.cdclk.max_cdclk_freq * 9 / 10; 2305 2306 /* 2307 * Enable double wide mode when the dot clock 2308 * is > 90% of the (display) core speed. 2309 */ 2310 if (intel_crtc_supports_double_wide(crtc) && 2311 pipe_mode->crtc_clock > clock_limit) { 2312 clock_limit = i915->max_dotclk_freq; 2313 crtc_state->double_wide = true; 2314 } 2315 } 2316 2317 if (pipe_mode->crtc_clock > clock_limit) { 2318 drm_dbg_kms(&i915->drm, 2319 "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", 2320 crtc->base.base.id, crtc->base.name, 2321 pipe_mode->crtc_clock, clock_limit, 2322 str_yes_no(crtc_state->double_wide)); 2323 return -EINVAL; 2324 } 2325 2326 return 0; 2327 } 2328 2329 static int intel_crtc_compute_config(struct intel_atomic_state *state, 2330 struct intel_crtc *crtc) 2331 { 2332 struct intel_crtc_state *crtc_state = 2333 intel_atomic_get_new_crtc_state(state, crtc); 2334 int ret; 2335 2336 ret = intel_dpll_crtc_compute_clock(state, crtc); 2337 if (ret) 2338 return ret; 2339 2340 ret = intel_crtc_compute_pipe_src(crtc_state); 2341 if (ret) 2342 return ret; 2343 2344 ret = intel_crtc_compute_pipe_mode(crtc_state); 2345 if (ret) 2346 return ret; 2347 2348 intel_crtc_compute_pixel_rate(crtc_state); 2349 2350 if (crtc_state->has_pch_encoder) 2351 return ilk_fdi_compute_config(crtc, crtc_state); 2352 2353 return 0; 2354 } 2355 2356 static void 2357 intel_reduce_m_n_ratio(u32 *num, u32 *den) 2358 { 2359 while (*num > DATA_LINK_M_N_MASK || 2360 *den > DATA_LINK_M_N_MASK) { 2361 *num >>= 1; 2362 *den >>= 1; 2363 } 2364 } 2365 2366 static void compute_m_n(u32 *ret_m, u32 *ret_n, 2367 u32 m, u32 n, u32 constant_n) 2368 { 2369 if (constant_n) 2370 *ret_n = constant_n; 2371 else 2372 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); 2373 2374 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n); 2375 intel_reduce_m_n_ratio(ret_m, ret_n); 2376 } 2377 2378 void 2379 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes, 2380 int pixel_clock, int link_clock, 2381 struct intel_link_m_n *m_n, 2382 bool fec_enable) 2383 { 2384 u32 data_clock = bits_per_pixel * pixel_clock; 2385 2386 if (fec_enable) 2387 data_clock = intel_dp_mode_to_fec_clock(data_clock); 2388 2389 /* 2390 * Windows/BIOS uses fixed M/N values always. Follow suit. 2391 * 2392 * Also several DP dongles in particular seem to be fussy 2393 * about too large link M/N values. Presumably the 20bit 2394 * value used by Windows/BIOS is acceptable to everyone. 2395 */ 2396 m_n->tu = 64; 2397 compute_m_n(&m_n->data_m, &m_n->data_n, 2398 data_clock, link_clock * nlanes * 8, 2399 0x8000000); 2400 2401 compute_m_n(&m_n->link_m, &m_n->link_n, 2402 pixel_clock, link_clock, 2403 0x80000); 2404 } 2405 2406 void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv) 2407 { 2408 /* 2409 * There may be no VBT; and if the BIOS enabled SSC we can 2410 * just keep using it to avoid unnecessary flicker. Whereas if the 2411 * BIOS isn't using it, don't assume it will work even if the VBT 2412 * indicates as much. 2413 */ 2414 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { 2415 bool bios_lvds_use_ssc = intel_de_read(dev_priv, 2416 PCH_DREF_CONTROL) & 2417 DREF_SSC1_ENABLE; 2418 2419 if (dev_priv->display.vbt.lvds_use_ssc != bios_lvds_use_ssc) { 2420 drm_dbg_kms(&dev_priv->drm, 2421 "SSC %s by BIOS, overriding VBT which says %s\n", 2422 str_enabled_disabled(bios_lvds_use_ssc), 2423 str_enabled_disabled(dev_priv->display.vbt.lvds_use_ssc)); 2424 dev_priv->display.vbt.lvds_use_ssc = bios_lvds_use_ssc; 2425 } 2426 } 2427 } 2428 2429 void intel_zero_m_n(struct intel_link_m_n *m_n) 2430 { 2431 /* corresponds to 0 register value */ 2432 memset(m_n, 0, sizeof(*m_n)); 2433 m_n->tu = 1; 2434 } 2435 2436 void intel_set_m_n(struct drm_i915_private *i915, 2437 const struct intel_link_m_n *m_n, 2438 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 2439 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 2440 { 2441 intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); 2442 intel_de_write(i915, data_n_reg, m_n->data_n); 2443 intel_de_write(i915, link_m_reg, m_n->link_m); 2444 /* 2445 * On BDW+ writing LINK_N arms the double buffered update 2446 * of all the M/N registers, so it must be written last. 2447 */ 2448 intel_de_write(i915, link_n_reg, m_n->link_n); 2449 } 2450 2451 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, 2452 enum transcoder transcoder) 2453 { 2454 if (IS_HASWELL(dev_priv)) 2455 return transcoder == TRANSCODER_EDP; 2456 2457 return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv); 2458 } 2459 2460 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, 2461 enum transcoder transcoder, 2462 const struct intel_link_m_n *m_n) 2463 { 2464 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2465 enum pipe pipe = crtc->pipe; 2466 2467 if (DISPLAY_VER(dev_priv) >= 5) 2468 intel_set_m_n(dev_priv, m_n, 2469 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 2470 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 2471 else 2472 intel_set_m_n(dev_priv, m_n, 2473 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 2474 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 2475 } 2476 2477 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, 2478 enum transcoder transcoder, 2479 const struct intel_link_m_n *m_n) 2480 { 2481 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2482 2483 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 2484 return; 2485 2486 intel_set_m_n(dev_priv, m_n, 2487 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 2488 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 2489 } 2490 2491 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) 2492 { 2493 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2494 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2495 enum pipe pipe = crtc->pipe; 2496 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2497 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2498 u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end; 2499 int vsyncshift = 0; 2500 2501 /* We need to be careful not to changed the adjusted mode, for otherwise 2502 * the hw state checker will get angry at the mismatch. */ 2503 crtc_vdisplay = adjusted_mode->crtc_vdisplay; 2504 crtc_vtotal = adjusted_mode->crtc_vtotal; 2505 crtc_vblank_start = adjusted_mode->crtc_vblank_start; 2506 crtc_vblank_end = adjusted_mode->crtc_vblank_end; 2507 2508 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 2509 /* the chip adds 2 halflines automatically */ 2510 crtc_vtotal -= 1; 2511 crtc_vblank_end -= 1; 2512 2513 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 2514 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; 2515 else 2516 vsyncshift = adjusted_mode->crtc_hsync_start - 2517 adjusted_mode->crtc_htotal / 2; 2518 if (vsyncshift < 0) 2519 vsyncshift += adjusted_mode->crtc_htotal; 2520 } 2521 2522 /* 2523 * VBLANK_START no longer works on ADL+, instead we must use 2524 * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start. 2525 */ 2526 if (DISPLAY_VER(dev_priv) >= 13) { 2527 intel_de_write(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder), 2528 crtc_vblank_start - crtc_vdisplay); 2529 2530 /* 2531 * VBLANK_START not used by hw, just clear it 2532 * to make it stand out in register dumps. 2533 */ 2534 crtc_vblank_start = 1; 2535 } 2536 2537 if (DISPLAY_VER(dev_priv) > 3) 2538 intel_de_write(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder), 2539 vsyncshift); 2540 2541 intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder), 2542 HACTIVE(adjusted_mode->crtc_hdisplay - 1) | 2543 HTOTAL(adjusted_mode->crtc_htotal - 1)); 2544 intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder), 2545 HBLANK_START(adjusted_mode->crtc_hblank_start - 1) | 2546 HBLANK_END(adjusted_mode->crtc_hblank_end - 1)); 2547 intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder), 2548 HSYNC_START(adjusted_mode->crtc_hsync_start - 1) | 2549 HSYNC_END(adjusted_mode->crtc_hsync_end - 1)); 2550 2551 intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder), 2552 VACTIVE(crtc_vdisplay - 1) | 2553 VTOTAL(crtc_vtotal - 1)); 2554 intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), 2555 VBLANK_START(crtc_vblank_start - 1) | 2556 VBLANK_END(crtc_vblank_end - 1)); 2557 intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder), 2558 VSYNC_START(adjusted_mode->crtc_vsync_start - 1) | 2559 VSYNC_END(adjusted_mode->crtc_vsync_end - 1)); 2560 2561 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be 2562 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is 2563 * documented on the DDI_FUNC_CTL register description, EDP Input Select 2564 * bits. */ 2565 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && 2566 (pipe == PIPE_B || pipe == PIPE_C)) 2567 intel_de_write(dev_priv, TRANS_VTOTAL(pipe), 2568 VACTIVE(crtc_vdisplay - 1) | 2569 VTOTAL(crtc_vtotal - 1)); 2570 } 2571 2572 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) 2573 { 2574 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2575 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2576 int width = drm_rect_width(&crtc_state->pipe_src); 2577 int height = drm_rect_height(&crtc_state->pipe_src); 2578 enum pipe pipe = crtc->pipe; 2579 2580 /* pipesrc controls the size that is scaled from, which should 2581 * always be the user's requested size. 2582 */ 2583 intel_de_write(dev_priv, PIPESRC(pipe), 2584 PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1)); 2585 } 2586 2587 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) 2588 { 2589 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2590 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2591 2592 if (DISPLAY_VER(dev_priv) == 2) 2593 return false; 2594 2595 if (DISPLAY_VER(dev_priv) >= 9 || 2596 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2597 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW; 2598 else 2599 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK; 2600 } 2601 2602 static void intel_get_transcoder_timings(struct intel_crtc *crtc, 2603 struct intel_crtc_state *pipe_config) 2604 { 2605 struct drm_device *dev = crtc->base.dev; 2606 struct drm_i915_private *dev_priv = to_i915(dev); 2607 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 2608 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2609 u32 tmp; 2610 2611 tmp = intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder)); 2612 adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1; 2613 adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1; 2614 2615 if (!transcoder_is_dsi(cpu_transcoder)) { 2616 tmp = intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder)); 2617 adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1; 2618 adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1; 2619 } 2620 2621 tmp = intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder)); 2622 adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1; 2623 adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1; 2624 2625 tmp = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder)); 2626 adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1; 2627 adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1; 2628 2629 /* FIXME TGL+ DSI transcoders have this! */ 2630 if (!transcoder_is_dsi(cpu_transcoder)) { 2631 tmp = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder)); 2632 adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1; 2633 adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1; 2634 } 2635 tmp = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder)); 2636 adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1; 2637 adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1; 2638 2639 if (intel_pipe_is_interlaced(pipe_config)) { 2640 adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE; 2641 adjusted_mode->crtc_vtotal += 1; 2642 adjusted_mode->crtc_vblank_end += 1; 2643 } 2644 2645 if (DISPLAY_VER(dev_priv) >= 13 && !transcoder_is_dsi(cpu_transcoder)) 2646 adjusted_mode->crtc_vblank_start = 2647 adjusted_mode->crtc_vdisplay + 2648 intel_de_read(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder)); 2649 } 2650 2651 static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state) 2652 { 2653 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2654 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2655 enum pipe master_pipe, pipe = crtc->pipe; 2656 int width; 2657 2658 if (num_pipes < 2) 2659 return; 2660 2661 master_pipe = bigjoiner_master_pipe(crtc_state); 2662 width = drm_rect_width(&crtc_state->pipe_src); 2663 2664 drm_rect_translate_to(&crtc_state->pipe_src, 2665 (pipe - master_pipe) * width, 0); 2666 } 2667 2668 static void intel_get_pipe_src_size(struct intel_crtc *crtc, 2669 struct intel_crtc_state *pipe_config) 2670 { 2671 struct drm_device *dev = crtc->base.dev; 2672 struct drm_i915_private *dev_priv = to_i915(dev); 2673 u32 tmp; 2674 2675 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe)); 2676 2677 drm_rect_init(&pipe_config->pipe_src, 0, 0, 2678 REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1, 2679 REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1); 2680 2681 intel_bigjoiner_adjust_pipe_src(pipe_config); 2682 } 2683 2684 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) 2685 { 2686 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2687 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2688 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2689 u32 val = 0; 2690 2691 /* 2692 * - We keep both pipes enabled on 830 2693 * - During modeset the pipe is still disabled and must remain so 2694 * - During fastset the pipe is already enabled and must remain so 2695 */ 2696 if (IS_I830(dev_priv) || !intel_crtc_needs_modeset(crtc_state)) 2697 val |= TRANSCONF_ENABLE; 2698 2699 if (crtc_state->double_wide) 2700 val |= TRANSCONF_DOUBLE_WIDE; 2701 2702 /* only g4x and later have fancy bpc/dither controls */ 2703 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 2704 IS_CHERRYVIEW(dev_priv)) { 2705 /* Bspec claims that we can't use dithering for 30bpp pipes. */ 2706 if (crtc_state->dither && crtc_state->pipe_bpp != 30) 2707 val |= TRANSCONF_DITHER_EN | 2708 TRANSCONF_DITHER_TYPE_SP; 2709 2710 switch (crtc_state->pipe_bpp) { 2711 default: 2712 /* Case prevented by intel_choose_pipe_bpp_dither. */ 2713 MISSING_CASE(crtc_state->pipe_bpp); 2714 fallthrough; 2715 case 18: 2716 val |= TRANSCONF_BPC_6; 2717 break; 2718 case 24: 2719 val |= TRANSCONF_BPC_8; 2720 break; 2721 case 30: 2722 val |= TRANSCONF_BPC_10; 2723 break; 2724 } 2725 } 2726 2727 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 2728 if (DISPLAY_VER(dev_priv) < 4 || 2729 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 2730 val |= TRANSCONF_INTERLACE_W_FIELD_INDICATION; 2731 else 2732 val |= TRANSCONF_INTERLACE_W_SYNC_SHIFT; 2733 } else { 2734 val |= TRANSCONF_INTERLACE_PROGRESSIVE; 2735 } 2736 2737 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 2738 crtc_state->limited_color_range) 2739 val |= TRANSCONF_COLOR_RANGE_SELECT; 2740 2741 val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode); 2742 2743 val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 2744 2745 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); 2746 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); 2747 } 2748 2749 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv) 2750 { 2751 if (IS_I830(dev_priv)) 2752 return false; 2753 2754 return DISPLAY_VER(dev_priv) >= 4 || 2755 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); 2756 } 2757 2758 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state) 2759 { 2760 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2761 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2762 enum pipe pipe; 2763 u32 tmp; 2764 2765 if (!i9xx_has_pfit(dev_priv)) 2766 return; 2767 2768 tmp = intel_de_read(dev_priv, PFIT_CONTROL); 2769 if (!(tmp & PFIT_ENABLE)) 2770 return; 2771 2772 /* Check whether the pfit is attached to our pipe. */ 2773 if (DISPLAY_VER(dev_priv) >= 4) 2774 pipe = REG_FIELD_GET(PFIT_PIPE_MASK, tmp); 2775 else 2776 pipe = PIPE_B; 2777 2778 if (pipe != crtc->pipe) 2779 return; 2780 2781 crtc_state->gmch_pfit.control = tmp; 2782 crtc_state->gmch_pfit.pgm_ratios = 2783 intel_de_read(dev_priv, PFIT_PGM_RATIOS); 2784 } 2785 2786 static void vlv_crtc_clock_get(struct intel_crtc *crtc, 2787 struct intel_crtc_state *pipe_config) 2788 { 2789 struct drm_device *dev = crtc->base.dev; 2790 struct drm_i915_private *dev_priv = to_i915(dev); 2791 enum pipe pipe = crtc->pipe; 2792 struct dpll clock; 2793 u32 mdiv; 2794 int refclk = 100000; 2795 2796 /* In case of DSI, DPLL will not be used */ 2797 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 2798 return; 2799 2800 vlv_dpio_get(dev_priv); 2801 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); 2802 vlv_dpio_put(dev_priv); 2803 2804 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; 2805 clock.m2 = mdiv & DPIO_M2DIV_MASK; 2806 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; 2807 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; 2808 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; 2809 2810 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); 2811 } 2812 2813 static void chv_crtc_clock_get(struct intel_crtc *crtc, 2814 struct intel_crtc_state *pipe_config) 2815 { 2816 struct drm_device *dev = crtc->base.dev; 2817 struct drm_i915_private *dev_priv = to_i915(dev); 2818 enum pipe pipe = crtc->pipe; 2819 enum dpio_channel port = vlv_pipe_to_channel(pipe); 2820 struct dpll clock; 2821 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; 2822 int refclk = 100000; 2823 2824 /* In case of DSI, DPLL will not be used */ 2825 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 2826 return; 2827 2828 vlv_dpio_get(dev_priv); 2829 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); 2830 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); 2831 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); 2832 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); 2833 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); 2834 vlv_dpio_put(dev_priv); 2835 2836 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; 2837 clock.m2 = (pll_dw0 & 0xff) << 22; 2838 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) 2839 clock.m2 |= pll_dw2 & 0x3fffff; 2840 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; 2841 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; 2842 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; 2843 2844 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); 2845 } 2846 2847 static enum intel_output_format 2848 bdw_get_pipe_misc_output_format(struct intel_crtc *crtc) 2849 { 2850 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2851 u32 tmp; 2852 2853 tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe)); 2854 2855 if (tmp & PIPE_MISC_YUV420_ENABLE) { 2856 /* We support 4:2:0 in full blend mode only */ 2857 drm_WARN_ON(&dev_priv->drm, 2858 (tmp & PIPE_MISC_YUV420_MODE_FULL_BLEND) == 0); 2859 2860 return INTEL_OUTPUT_FORMAT_YCBCR420; 2861 } else if (tmp & PIPE_MISC_OUTPUT_COLORSPACE_YUV) { 2862 return INTEL_OUTPUT_FORMAT_YCBCR444; 2863 } else { 2864 return INTEL_OUTPUT_FORMAT_RGB; 2865 } 2866 } 2867 2868 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state) 2869 { 2870 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2871 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 2872 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2873 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 2874 u32 tmp; 2875 2876 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); 2877 2878 if (tmp & DISP_PIPE_GAMMA_ENABLE) 2879 crtc_state->gamma_enable = true; 2880 2881 if (!HAS_GMCH(dev_priv) && 2882 tmp & DISP_PIPE_CSC_ENABLE) 2883 crtc_state->csc_enable = true; 2884 } 2885 2886 static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 2887 struct intel_crtc_state *pipe_config) 2888 { 2889 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2890 enum intel_display_power_domain power_domain; 2891 intel_wakeref_t wakeref; 2892 u32 tmp; 2893 bool ret; 2894 2895 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 2896 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 2897 if (!wakeref) 2898 return false; 2899 2900 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 2901 pipe_config->sink_format = pipe_config->output_format; 2902 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 2903 pipe_config->shared_dpll = NULL; 2904 2905 ret = false; 2906 2907 tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder)); 2908 if (!(tmp & TRANSCONF_ENABLE)) 2909 goto out; 2910 2911 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 2912 IS_CHERRYVIEW(dev_priv)) { 2913 switch (tmp & TRANSCONF_BPC_MASK) { 2914 case TRANSCONF_BPC_6: 2915 pipe_config->pipe_bpp = 18; 2916 break; 2917 case TRANSCONF_BPC_8: 2918 pipe_config->pipe_bpp = 24; 2919 break; 2920 case TRANSCONF_BPC_10: 2921 pipe_config->pipe_bpp = 30; 2922 break; 2923 default: 2924 MISSING_CASE(tmp); 2925 break; 2926 } 2927 } 2928 2929 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 2930 (tmp & TRANSCONF_COLOR_RANGE_SELECT)) 2931 pipe_config->limited_color_range = true; 2932 2933 pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp); 2934 2935 pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1; 2936 2937 if (IS_CHERRYVIEW(dev_priv)) 2938 pipe_config->cgm_mode = intel_de_read(dev_priv, 2939 CGM_PIPE_MODE(crtc->pipe)); 2940 2941 i9xx_get_pipe_color_config(pipe_config); 2942 intel_color_get_config(pipe_config); 2943 2944 if (DISPLAY_VER(dev_priv) < 4) 2945 pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE; 2946 2947 intel_get_transcoder_timings(crtc, pipe_config); 2948 intel_get_pipe_src_size(crtc, pipe_config); 2949 2950 i9xx_get_pfit_config(pipe_config); 2951 2952 if (DISPLAY_VER(dev_priv) >= 4) { 2953 /* No way to read it out on pipes B and C */ 2954 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) 2955 tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe]; 2956 else 2957 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe)); 2958 pipe_config->pixel_multiplier = 2959 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) 2960 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; 2961 pipe_config->dpll_hw_state.dpll_md = tmp; 2962 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 2963 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 2964 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe)); 2965 pipe_config->pixel_multiplier = 2966 ((tmp & SDVO_MULTIPLIER_MASK) 2967 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; 2968 } else { 2969 /* Note that on i915G/GM the pixel multiplier is in the sdvo 2970 * port and will be fixed up in the encoder->get_config 2971 * function. */ 2972 pipe_config->pixel_multiplier = 1; 2973 } 2974 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv, 2975 DPLL(crtc->pipe)); 2976 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 2977 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv, 2978 FP0(crtc->pipe)); 2979 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv, 2980 FP1(crtc->pipe)); 2981 } else { 2982 /* Mask out read-only status bits. */ 2983 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | 2984 DPLL_PORTC_READY_MASK | 2985 DPLL_PORTB_READY_MASK); 2986 } 2987 2988 if (IS_CHERRYVIEW(dev_priv)) 2989 chv_crtc_clock_get(crtc, pipe_config); 2990 else if (IS_VALLEYVIEW(dev_priv)) 2991 vlv_crtc_clock_get(crtc, pipe_config); 2992 else 2993 i9xx_crtc_clock_get(crtc, pipe_config); 2994 2995 /* 2996 * Normally the dotclock is filled in by the encoder .get_config() 2997 * but in case the pipe is enabled w/o any ports we need a sane 2998 * default. 2999 */ 3000 pipe_config->hw.adjusted_mode.crtc_clock = 3001 pipe_config->port_clock / pipe_config->pixel_multiplier; 3002 3003 ret = true; 3004 3005 out: 3006 intel_display_power_put(dev_priv, power_domain, wakeref); 3007 3008 return ret; 3009 } 3010 3011 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) 3012 { 3013 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3014 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3015 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3016 u32 val = 0; 3017 3018 /* 3019 * - During modeset the pipe is still disabled and must remain so 3020 * - During fastset the pipe is already enabled and must remain so 3021 */ 3022 if (!intel_crtc_needs_modeset(crtc_state)) 3023 val |= TRANSCONF_ENABLE; 3024 3025 switch (crtc_state->pipe_bpp) { 3026 default: 3027 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3028 MISSING_CASE(crtc_state->pipe_bpp); 3029 fallthrough; 3030 case 18: 3031 val |= TRANSCONF_BPC_6; 3032 break; 3033 case 24: 3034 val |= TRANSCONF_BPC_8; 3035 break; 3036 case 30: 3037 val |= TRANSCONF_BPC_10; 3038 break; 3039 case 36: 3040 val |= TRANSCONF_BPC_12; 3041 break; 3042 } 3043 3044 if (crtc_state->dither) 3045 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP; 3046 3047 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3048 val |= TRANSCONF_INTERLACE_IF_ID_ILK; 3049 else 3050 val |= TRANSCONF_INTERLACE_PF_PD_ILK; 3051 3052 /* 3053 * This would end up with an odd purple hue over 3054 * the entire display. Make sure we don't do it. 3055 */ 3056 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 3057 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 3058 3059 if (crtc_state->limited_color_range && 3060 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3061 val |= TRANSCONF_COLOR_RANGE_SELECT; 3062 3063 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3064 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV709; 3065 3066 val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode); 3067 3068 val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3069 val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay); 3070 3071 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); 3072 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); 3073 } 3074 3075 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) 3076 { 3077 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3078 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3079 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3080 u32 val = 0; 3081 3082 /* 3083 * - During modeset the pipe is still disabled and must remain so 3084 * - During fastset the pipe is already enabled and must remain so 3085 */ 3086 if (!intel_crtc_needs_modeset(crtc_state)) 3087 val |= TRANSCONF_ENABLE; 3088 3089 if (IS_HASWELL(dev_priv) && crtc_state->dither) 3090 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP; 3091 3092 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3093 val |= TRANSCONF_INTERLACE_IF_ID_ILK; 3094 else 3095 val |= TRANSCONF_INTERLACE_PF_PD_ILK; 3096 3097 if (IS_HASWELL(dev_priv) && 3098 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3099 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW; 3100 3101 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); 3102 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); 3103 } 3104 3105 static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state) 3106 { 3107 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3108 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3109 u32 val = 0; 3110 3111 switch (crtc_state->pipe_bpp) { 3112 case 18: 3113 val |= PIPE_MISC_BPC_6; 3114 break; 3115 case 24: 3116 val |= PIPE_MISC_BPC_8; 3117 break; 3118 case 30: 3119 val |= PIPE_MISC_BPC_10; 3120 break; 3121 case 36: 3122 /* Port output 12BPC defined for ADLP+ */ 3123 if (DISPLAY_VER(dev_priv) > 12) 3124 val |= PIPE_MISC_BPC_12_ADLP; 3125 break; 3126 default: 3127 MISSING_CASE(crtc_state->pipe_bpp); 3128 break; 3129 } 3130 3131 if (crtc_state->dither) 3132 val |= PIPE_MISC_DITHER_ENABLE | PIPE_MISC_DITHER_TYPE_SP; 3133 3134 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 3135 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 3136 val |= PIPE_MISC_OUTPUT_COLORSPACE_YUV; 3137 3138 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 3139 val |= PIPE_MISC_YUV420_ENABLE | 3140 PIPE_MISC_YUV420_MODE_FULL_BLEND; 3141 3142 if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state)) 3143 val |= PIPE_MISC_HDR_MODE_PRECISION; 3144 3145 if (DISPLAY_VER(dev_priv) >= 12) 3146 val |= PIPE_MISC_PIXEL_ROUNDING_TRUNC; 3147 3148 intel_de_write(dev_priv, PIPE_MISC(crtc->pipe), val); 3149 } 3150 3151 int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc) 3152 { 3153 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3154 u32 tmp; 3155 3156 tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe)); 3157 3158 switch (tmp & PIPE_MISC_BPC_MASK) { 3159 case PIPE_MISC_BPC_6: 3160 return 18; 3161 case PIPE_MISC_BPC_8: 3162 return 24; 3163 case PIPE_MISC_BPC_10: 3164 return 30; 3165 /* 3166 * PORT OUTPUT 12 BPC defined for ADLP+. 3167 * 3168 * TODO: 3169 * For previous platforms with DSI interface, bits 5:7 3170 * are used for storing pipe_bpp irrespective of dithering. 3171 * Since the value of 12 BPC is not defined for these bits 3172 * on older platforms, need to find a workaround for 12 BPC 3173 * MIPI DSI HW readout. 3174 */ 3175 case PIPE_MISC_BPC_12_ADLP: 3176 if (DISPLAY_VER(dev_priv) > 12) 3177 return 36; 3178 fallthrough; 3179 default: 3180 MISSING_CASE(tmp); 3181 return 0; 3182 } 3183 } 3184 3185 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) 3186 { 3187 /* 3188 * Account for spread spectrum to avoid 3189 * oversubscribing the link. Max center spread 3190 * is 2.5%; use 5% for safety's sake. 3191 */ 3192 u32 bps = target_clock * bpp * 21 / 20; 3193 return DIV_ROUND_UP(bps, link_bw * 8); 3194 } 3195 3196 void intel_get_m_n(struct drm_i915_private *i915, 3197 struct intel_link_m_n *m_n, 3198 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 3199 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 3200 { 3201 m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK; 3202 m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK; 3203 m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK; 3204 m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK; 3205 m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1; 3206 } 3207 3208 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, 3209 enum transcoder transcoder, 3210 struct intel_link_m_n *m_n) 3211 { 3212 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3213 enum pipe pipe = crtc->pipe; 3214 3215 if (DISPLAY_VER(dev_priv) >= 5) 3216 intel_get_m_n(dev_priv, m_n, 3217 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 3218 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 3219 else 3220 intel_get_m_n(dev_priv, m_n, 3221 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 3222 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 3223 } 3224 3225 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, 3226 enum transcoder transcoder, 3227 struct intel_link_m_n *m_n) 3228 { 3229 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3230 3231 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 3232 return; 3233 3234 intel_get_m_n(dev_priv, m_n, 3235 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 3236 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 3237 } 3238 3239 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state) 3240 { 3241 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3242 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3243 u32 ctl, pos, size; 3244 enum pipe pipe; 3245 3246 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe)); 3247 if ((ctl & PF_ENABLE) == 0) 3248 return; 3249 3250 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) 3251 pipe = REG_FIELD_GET(PF_PIPE_SEL_MASK_IVB, ctl); 3252 else 3253 pipe = crtc->pipe; 3254 3255 crtc_state->pch_pfit.enabled = true; 3256 3257 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe)); 3258 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe)); 3259 3260 drm_rect_init(&crtc_state->pch_pfit.dst, 3261 REG_FIELD_GET(PF_WIN_XPOS_MASK, pos), 3262 REG_FIELD_GET(PF_WIN_YPOS_MASK, pos), 3263 REG_FIELD_GET(PF_WIN_XSIZE_MASK, size), 3264 REG_FIELD_GET(PF_WIN_YSIZE_MASK, size)); 3265 3266 /* 3267 * We currently do not free assignements of panel fitters on 3268 * ivb/hsw (since we don't use the higher upscaling modes which 3269 * differentiates them) so just WARN about this case for now. 3270 */ 3271 drm_WARN_ON(&dev_priv->drm, pipe != crtc->pipe); 3272 } 3273 3274 static bool ilk_get_pipe_config(struct intel_crtc *crtc, 3275 struct intel_crtc_state *pipe_config) 3276 { 3277 struct drm_device *dev = crtc->base.dev; 3278 struct drm_i915_private *dev_priv = to_i915(dev); 3279 enum intel_display_power_domain power_domain; 3280 intel_wakeref_t wakeref; 3281 u32 tmp; 3282 bool ret; 3283 3284 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3285 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3286 if (!wakeref) 3287 return false; 3288 3289 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3290 pipe_config->shared_dpll = NULL; 3291 3292 ret = false; 3293 tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder)); 3294 if (!(tmp & TRANSCONF_ENABLE)) 3295 goto out; 3296 3297 switch (tmp & TRANSCONF_BPC_MASK) { 3298 case TRANSCONF_BPC_6: 3299 pipe_config->pipe_bpp = 18; 3300 break; 3301 case TRANSCONF_BPC_8: 3302 pipe_config->pipe_bpp = 24; 3303 break; 3304 case TRANSCONF_BPC_10: 3305 pipe_config->pipe_bpp = 30; 3306 break; 3307 case TRANSCONF_BPC_12: 3308 pipe_config->pipe_bpp = 36; 3309 break; 3310 default: 3311 break; 3312 } 3313 3314 if (tmp & TRANSCONF_COLOR_RANGE_SELECT) 3315 pipe_config->limited_color_range = true; 3316 3317 switch (tmp & TRANSCONF_OUTPUT_COLORSPACE_MASK) { 3318 case TRANSCONF_OUTPUT_COLORSPACE_YUV601: 3319 case TRANSCONF_OUTPUT_COLORSPACE_YUV709: 3320 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3321 break; 3322 default: 3323 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3324 break; 3325 } 3326 3327 pipe_config->sink_format = pipe_config->output_format; 3328 3329 pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp); 3330 3331 pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1; 3332 3333 pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp); 3334 3335 pipe_config->csc_mode = intel_de_read(dev_priv, 3336 PIPE_CSC_MODE(crtc->pipe)); 3337 3338 i9xx_get_pipe_color_config(pipe_config); 3339 intel_color_get_config(pipe_config); 3340 3341 pipe_config->pixel_multiplier = 1; 3342 3343 ilk_pch_get_config(pipe_config); 3344 3345 intel_get_transcoder_timings(crtc, pipe_config); 3346 intel_get_pipe_src_size(crtc, pipe_config); 3347 3348 ilk_get_pfit_config(pipe_config); 3349 3350 ret = true; 3351 3352 out: 3353 intel_display_power_put(dev_priv, power_domain, wakeref); 3354 3355 return ret; 3356 } 3357 3358 static u8 bigjoiner_pipes(struct drm_i915_private *i915) 3359 { 3360 u8 pipes; 3361 3362 if (DISPLAY_VER(i915) >= 12) 3363 pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D); 3364 else if (DISPLAY_VER(i915) >= 11) 3365 pipes = BIT(PIPE_B) | BIT(PIPE_C); 3366 else 3367 pipes = 0; 3368 3369 return pipes & DISPLAY_RUNTIME_INFO(i915)->pipe_mask; 3370 } 3371 3372 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv, 3373 enum transcoder cpu_transcoder) 3374 { 3375 enum intel_display_power_domain power_domain; 3376 intel_wakeref_t wakeref; 3377 u32 tmp = 0; 3378 3379 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3380 3381 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3382 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3383 3384 return tmp & TRANS_DDI_FUNC_ENABLE; 3385 } 3386 3387 static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv, 3388 u8 *master_pipes, u8 *slave_pipes) 3389 { 3390 struct intel_crtc *crtc; 3391 3392 *master_pipes = 0; 3393 *slave_pipes = 0; 3394 3395 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, 3396 bigjoiner_pipes(dev_priv)) { 3397 enum intel_display_power_domain power_domain; 3398 enum pipe pipe = crtc->pipe; 3399 intel_wakeref_t wakeref; 3400 3401 power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe); 3402 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3403 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3404 3405 if (!(tmp & BIG_JOINER_ENABLE)) 3406 continue; 3407 3408 if (tmp & MASTER_BIG_JOINER_ENABLE) 3409 *master_pipes |= BIT(pipe); 3410 else 3411 *slave_pipes |= BIT(pipe); 3412 } 3413 3414 if (DISPLAY_VER(dev_priv) < 13) 3415 continue; 3416 3417 power_domain = POWER_DOMAIN_PIPE(pipe); 3418 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3419 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3420 3421 if (tmp & UNCOMPRESSED_JOINER_MASTER) 3422 *master_pipes |= BIT(pipe); 3423 if (tmp & UNCOMPRESSED_JOINER_SLAVE) 3424 *slave_pipes |= BIT(pipe); 3425 } 3426 } 3427 3428 /* Bigjoiner pipes should always be consecutive master and slave */ 3429 drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1, 3430 "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n", 3431 *master_pipes, *slave_pipes); 3432 } 3433 3434 static enum pipe get_bigjoiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3435 { 3436 if ((slave_pipes & BIT(pipe)) == 0) 3437 return pipe; 3438 3439 /* ignore everything above our pipe */ 3440 master_pipes &= ~GENMASK(7, pipe); 3441 3442 /* highest remaining bit should be our master pipe */ 3443 return fls(master_pipes) - 1; 3444 } 3445 3446 static u8 get_bigjoiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3447 { 3448 enum pipe master_pipe, next_master_pipe; 3449 3450 master_pipe = get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes); 3451 3452 if ((master_pipes & BIT(master_pipe)) == 0) 3453 return 0; 3454 3455 /* ignore our master pipe and everything below it */ 3456 master_pipes &= ~GENMASK(master_pipe, 0); 3457 /* make sure a high bit is set for the ffs() */ 3458 master_pipes |= BIT(7); 3459 /* lowest remaining bit should be the next master pipe */ 3460 next_master_pipe = ffs(master_pipes) - 1; 3461 3462 return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe); 3463 } 3464 3465 static u8 hsw_panel_transcoders(struct drm_i915_private *i915) 3466 { 3467 u8 panel_transcoder_mask = BIT(TRANSCODER_EDP); 3468 3469 if (DISPLAY_VER(i915) >= 11) 3470 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); 3471 3472 return panel_transcoder_mask; 3473 } 3474 3475 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) 3476 { 3477 struct drm_device *dev = crtc->base.dev; 3478 struct drm_i915_private *dev_priv = to_i915(dev); 3479 u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv); 3480 enum transcoder cpu_transcoder; 3481 u8 master_pipes, slave_pipes; 3482 u8 enabled_transcoders = 0; 3483 3484 /* 3485 * XXX: Do intel_display_power_get_if_enabled before reading this (for 3486 * consistency and less surprising code; it's in always on power). 3487 */ 3488 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, 3489 panel_transcoder_mask) { 3490 enum intel_display_power_domain power_domain; 3491 intel_wakeref_t wakeref; 3492 enum pipe trans_pipe; 3493 u32 tmp = 0; 3494 3495 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3496 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3497 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3498 3499 if (!(tmp & TRANS_DDI_FUNC_ENABLE)) 3500 continue; 3501 3502 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 3503 default: 3504 drm_WARN(dev, 1, 3505 "unknown pipe linked to transcoder %s\n", 3506 transcoder_name(cpu_transcoder)); 3507 fallthrough; 3508 case TRANS_DDI_EDP_INPUT_A_ONOFF: 3509 case TRANS_DDI_EDP_INPUT_A_ON: 3510 trans_pipe = PIPE_A; 3511 break; 3512 case TRANS_DDI_EDP_INPUT_B_ONOFF: 3513 trans_pipe = PIPE_B; 3514 break; 3515 case TRANS_DDI_EDP_INPUT_C_ONOFF: 3516 trans_pipe = PIPE_C; 3517 break; 3518 case TRANS_DDI_EDP_INPUT_D_ONOFF: 3519 trans_pipe = PIPE_D; 3520 break; 3521 } 3522 3523 if (trans_pipe == crtc->pipe) 3524 enabled_transcoders |= BIT(cpu_transcoder); 3525 } 3526 3527 /* single pipe or bigjoiner master */ 3528 cpu_transcoder = (enum transcoder) crtc->pipe; 3529 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 3530 enabled_transcoders |= BIT(cpu_transcoder); 3531 3532 /* bigjoiner slave -> consider the master pipe's transcoder as well */ 3533 enabled_bigjoiner_pipes(dev_priv, &master_pipes, &slave_pipes); 3534 if (slave_pipes & BIT(crtc->pipe)) { 3535 cpu_transcoder = (enum transcoder) 3536 get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes); 3537 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 3538 enabled_transcoders |= BIT(cpu_transcoder); 3539 } 3540 3541 return enabled_transcoders; 3542 } 3543 3544 static bool has_edp_transcoders(u8 enabled_transcoders) 3545 { 3546 return enabled_transcoders & BIT(TRANSCODER_EDP); 3547 } 3548 3549 static bool has_dsi_transcoders(u8 enabled_transcoders) 3550 { 3551 return enabled_transcoders & (BIT(TRANSCODER_DSI_0) | 3552 BIT(TRANSCODER_DSI_1)); 3553 } 3554 3555 static bool has_pipe_transcoders(u8 enabled_transcoders) 3556 { 3557 return enabled_transcoders & ~(BIT(TRANSCODER_EDP) | 3558 BIT(TRANSCODER_DSI_0) | 3559 BIT(TRANSCODER_DSI_1)); 3560 } 3561 3562 static void assert_enabled_transcoders(struct drm_i915_private *i915, 3563 u8 enabled_transcoders) 3564 { 3565 /* Only one type of transcoder please */ 3566 drm_WARN_ON(&i915->drm, 3567 has_edp_transcoders(enabled_transcoders) + 3568 has_dsi_transcoders(enabled_transcoders) + 3569 has_pipe_transcoders(enabled_transcoders) > 1); 3570 3571 /* Only DSI transcoders can be ganged */ 3572 drm_WARN_ON(&i915->drm, 3573 !has_dsi_transcoders(enabled_transcoders) && 3574 !is_power_of_2(enabled_transcoders)); 3575 } 3576 3577 static bool hsw_get_transcoder_state(struct intel_crtc *crtc, 3578 struct intel_crtc_state *pipe_config, 3579 struct intel_display_power_domain_set *power_domain_set) 3580 { 3581 struct drm_device *dev = crtc->base.dev; 3582 struct drm_i915_private *dev_priv = to_i915(dev); 3583 unsigned long enabled_transcoders; 3584 u32 tmp; 3585 3586 enabled_transcoders = hsw_enabled_transcoders(crtc); 3587 if (!enabled_transcoders) 3588 return false; 3589 3590 assert_enabled_transcoders(dev_priv, enabled_transcoders); 3591 3592 /* 3593 * With the exception of DSI we should only ever have 3594 * a single enabled transcoder. With DSI let's just 3595 * pick the first one. 3596 */ 3597 pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1; 3598 3599 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 3600 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) 3601 return false; 3602 3603 if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) { 3604 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); 3605 3606 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF) 3607 pipe_config->pch_pfit.force_thru = true; 3608 } 3609 3610 tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder)); 3611 3612 return tmp & TRANSCONF_ENABLE; 3613 } 3614 3615 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, 3616 struct intel_crtc_state *pipe_config, 3617 struct intel_display_power_domain_set *power_domain_set) 3618 { 3619 struct drm_device *dev = crtc->base.dev; 3620 struct drm_i915_private *dev_priv = to_i915(dev); 3621 enum transcoder cpu_transcoder; 3622 enum port port; 3623 u32 tmp; 3624 3625 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { 3626 if (port == PORT_A) 3627 cpu_transcoder = TRANSCODER_DSI_A; 3628 else 3629 cpu_transcoder = TRANSCODER_DSI_C; 3630 3631 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 3632 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) 3633 continue; 3634 3635 /* 3636 * The PLL needs to be enabled with a valid divider 3637 * configuration, otherwise accessing DSI registers will hang 3638 * the machine. See BSpec North Display Engine 3639 * registers/MIPI[BXT]. We can break out here early, since we 3640 * need the same DSI PLL to be enabled for both DSI ports. 3641 */ 3642 if (!bxt_dsi_pll_is_enabled(dev_priv)) 3643 break; 3644 3645 /* XXX: this works for video mode only */ 3646 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); 3647 if (!(tmp & DPI_ENABLE)) 3648 continue; 3649 3650 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 3651 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) 3652 continue; 3653 3654 pipe_config->cpu_transcoder = cpu_transcoder; 3655 break; 3656 } 3657 3658 return transcoder_is_dsi(pipe_config->cpu_transcoder); 3659 } 3660 3661 static void intel_bigjoiner_get_config(struct intel_crtc_state *crtc_state) 3662 { 3663 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3664 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 3665 u8 master_pipes, slave_pipes; 3666 enum pipe pipe = crtc->pipe; 3667 3668 enabled_bigjoiner_pipes(i915, &master_pipes, &slave_pipes); 3669 3670 if (((master_pipes | slave_pipes) & BIT(pipe)) == 0) 3671 return; 3672 3673 crtc_state->bigjoiner_pipes = 3674 BIT(get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes)) | 3675 get_bigjoiner_slave_pipes(pipe, master_pipes, slave_pipes); 3676 } 3677 3678 static bool hsw_get_pipe_config(struct intel_crtc *crtc, 3679 struct intel_crtc_state *pipe_config) 3680 { 3681 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3682 bool active; 3683 u32 tmp; 3684 3685 if (!intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains, 3686 POWER_DOMAIN_PIPE(crtc->pipe))) 3687 return false; 3688 3689 pipe_config->shared_dpll = NULL; 3690 3691 active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains); 3692 3693 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 3694 bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) { 3695 drm_WARN_ON(&dev_priv->drm, active); 3696 active = true; 3697 } 3698 3699 if (!active) 3700 goto out; 3701 3702 intel_dsc_get_config(pipe_config); 3703 intel_bigjoiner_get_config(pipe_config); 3704 3705 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || 3706 DISPLAY_VER(dev_priv) >= 11) 3707 intel_get_transcoder_timings(crtc, pipe_config); 3708 3709 if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder)) 3710 intel_vrr_get_config(pipe_config); 3711 3712 intel_get_pipe_src_size(crtc, pipe_config); 3713 3714 if (IS_HASWELL(dev_priv)) { 3715 u32 tmp = intel_de_read(dev_priv, 3716 TRANSCONF(pipe_config->cpu_transcoder)); 3717 3718 if (tmp & TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW) 3719 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3720 else 3721 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3722 } else { 3723 pipe_config->output_format = 3724 bdw_get_pipe_misc_output_format(crtc); 3725 } 3726 3727 pipe_config->sink_format = pipe_config->output_format; 3728 3729 pipe_config->gamma_mode = intel_de_read(dev_priv, 3730 GAMMA_MODE(crtc->pipe)); 3731 3732 pipe_config->csc_mode = intel_de_read(dev_priv, 3733 PIPE_CSC_MODE(crtc->pipe)); 3734 3735 if (DISPLAY_VER(dev_priv) >= 9) { 3736 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe)); 3737 3738 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE) 3739 pipe_config->gamma_enable = true; 3740 3741 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE) 3742 pipe_config->csc_enable = true; 3743 } else { 3744 i9xx_get_pipe_color_config(pipe_config); 3745 } 3746 3747 intel_color_get_config(pipe_config); 3748 3749 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe)); 3750 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); 3751 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 3752 pipe_config->ips_linetime = 3753 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); 3754 3755 if (intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains, 3756 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) { 3757 if (DISPLAY_VER(dev_priv) >= 9) 3758 skl_scaler_get_config(pipe_config); 3759 else 3760 ilk_get_pfit_config(pipe_config); 3761 } 3762 3763 hsw_ips_get_config(pipe_config); 3764 3765 if (pipe_config->cpu_transcoder != TRANSCODER_EDP && 3766 !transcoder_is_dsi(pipe_config->cpu_transcoder)) { 3767 pipe_config->pixel_multiplier = 3768 intel_de_read(dev_priv, 3769 TRANS_MULT(pipe_config->cpu_transcoder)) + 1; 3770 } else { 3771 pipe_config->pixel_multiplier = 1; 3772 } 3773 3774 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { 3775 tmp = intel_de_read(dev_priv, DISPLAY_VER(dev_priv) >= 14 ? 3776 MTL_CHICKEN_TRANS(pipe_config->cpu_transcoder) : 3777 CHICKEN_TRANS(pipe_config->cpu_transcoder)); 3778 3779 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1; 3780 } else { 3781 /* no idea if this is correct */ 3782 pipe_config->framestart_delay = 1; 3783 } 3784 3785 out: 3786 intel_display_power_put_all_in_set(dev_priv, &crtc->hw_readout_power_domains); 3787 3788 return active; 3789 } 3790 3791 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state) 3792 { 3793 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3794 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 3795 3796 if (!i915->display.funcs.display->get_pipe_config(crtc, crtc_state)) 3797 return false; 3798 3799 crtc_state->hw.active = true; 3800 3801 intel_crtc_readout_derived_state(crtc_state); 3802 3803 return true; 3804 } 3805 3806 static int i9xx_pll_refclk(struct drm_device *dev, 3807 const struct intel_crtc_state *pipe_config) 3808 { 3809 struct drm_i915_private *dev_priv = to_i915(dev); 3810 u32 dpll = pipe_config->dpll_hw_state.dpll; 3811 3812 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) 3813 return dev_priv->display.vbt.lvds_ssc_freq; 3814 else if (HAS_PCH_SPLIT(dev_priv)) 3815 return 120000; 3816 else if (DISPLAY_VER(dev_priv) != 2) 3817 return 96000; 3818 else 3819 return 48000; 3820 } 3821 3822 /* Returns the clock of the currently programmed mode of the given pipe. */ 3823 void i9xx_crtc_clock_get(struct intel_crtc *crtc, 3824 struct intel_crtc_state *pipe_config) 3825 { 3826 struct drm_device *dev = crtc->base.dev; 3827 struct drm_i915_private *dev_priv = to_i915(dev); 3828 u32 dpll = pipe_config->dpll_hw_state.dpll; 3829 u32 fp; 3830 struct dpll clock; 3831 int port_clock; 3832 int refclk = i9xx_pll_refclk(dev, pipe_config); 3833 3834 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 3835 fp = pipe_config->dpll_hw_state.fp0; 3836 else 3837 fp = pipe_config->dpll_hw_state.fp1; 3838 3839 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 3840 if (IS_PINEVIEW(dev_priv)) { 3841 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; 3842 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; 3843 } else { 3844 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 3845 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 3846 } 3847 3848 if (DISPLAY_VER(dev_priv) != 2) { 3849 if (IS_PINEVIEW(dev_priv)) 3850 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> 3851 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); 3852 else 3853 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> 3854 DPLL_FPA01_P1_POST_DIV_SHIFT); 3855 3856 switch (dpll & DPLL_MODE_MASK) { 3857 case DPLLB_MODE_DAC_SERIAL: 3858 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 3859 5 : 10; 3860 break; 3861 case DPLLB_MODE_LVDS: 3862 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 3863 7 : 14; 3864 break; 3865 default: 3866 drm_dbg_kms(&dev_priv->drm, 3867 "Unknown DPLL mode %08x in programmed " 3868 "mode\n", (int)(dpll & DPLL_MODE_MASK)); 3869 return; 3870 } 3871 3872 if (IS_PINEVIEW(dev_priv)) 3873 port_clock = pnv_calc_dpll_params(refclk, &clock); 3874 else 3875 port_clock = i9xx_calc_dpll_params(refclk, &clock); 3876 } else { 3877 enum pipe lvds_pipe; 3878 3879 if (IS_I85X(dev_priv) && 3880 intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) && 3881 lvds_pipe == crtc->pipe) { 3882 u32 lvds = intel_de_read(dev_priv, LVDS); 3883 3884 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 3885 DPLL_FPA01_P1_POST_DIV_SHIFT); 3886 3887 if (lvds & LVDS_CLKB_POWER_UP) 3888 clock.p2 = 7; 3889 else 3890 clock.p2 = 14; 3891 } else { 3892 if (dpll & PLL_P1_DIVIDE_BY_TWO) 3893 clock.p1 = 2; 3894 else { 3895 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 3896 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 3897 } 3898 if (dpll & PLL_P2_DIVIDE_BY_4) 3899 clock.p2 = 4; 3900 else 3901 clock.p2 = 2; 3902 } 3903 3904 port_clock = i9xx_calc_dpll_params(refclk, &clock); 3905 } 3906 3907 /* 3908 * This value includes pixel_multiplier. We will use 3909 * port_clock to compute adjusted_mode.crtc_clock in the 3910 * encoder's get_config() function. 3911 */ 3912 pipe_config->port_clock = port_clock; 3913 } 3914 3915 int intel_dotclock_calculate(int link_freq, 3916 const struct intel_link_m_n *m_n) 3917 { 3918 /* 3919 * The calculation for the data clock is: 3920 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp 3921 * But we want to avoid losing precison if possible, so: 3922 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) 3923 * 3924 * and the link clock is simpler: 3925 * link_clock = (m * link_clock) / n 3926 */ 3927 3928 if (!m_n->link_n) 3929 return 0; 3930 3931 return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq), 3932 m_n->link_n); 3933 } 3934 3935 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config) 3936 { 3937 int dotclock; 3938 3939 if (intel_crtc_has_dp_encoder(pipe_config)) 3940 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 3941 &pipe_config->dp_m_n); 3942 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) 3943 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24, 3944 pipe_config->pipe_bpp); 3945 else 3946 dotclock = pipe_config->port_clock; 3947 3948 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 3949 !intel_crtc_has_dp_encoder(pipe_config)) 3950 dotclock *= 2; 3951 3952 if (pipe_config->pixel_multiplier) 3953 dotclock /= pipe_config->pixel_multiplier; 3954 3955 return dotclock; 3956 } 3957 3958 /* Returns the currently programmed mode of the given encoder. */ 3959 struct drm_display_mode * 3960 intel_encoder_current_mode(struct intel_encoder *encoder) 3961 { 3962 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3963 struct intel_crtc_state *crtc_state; 3964 struct drm_display_mode *mode; 3965 struct intel_crtc *crtc; 3966 enum pipe pipe; 3967 3968 if (!encoder->get_hw_state(encoder, &pipe)) 3969 return NULL; 3970 3971 crtc = intel_crtc_for_pipe(dev_priv, pipe); 3972 3973 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 3974 if (!mode) 3975 return NULL; 3976 3977 crtc_state = intel_crtc_state_alloc(crtc); 3978 if (!crtc_state) { 3979 kfree(mode); 3980 return NULL; 3981 } 3982 3983 if (!intel_crtc_get_pipe_config(crtc_state)) { 3984 kfree(crtc_state); 3985 kfree(mode); 3986 return NULL; 3987 } 3988 3989 intel_encoder_get_config(encoder, crtc_state); 3990 3991 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode); 3992 3993 kfree(crtc_state); 3994 3995 return mode; 3996 } 3997 3998 static bool encoders_cloneable(const struct intel_encoder *a, 3999 const struct intel_encoder *b) 4000 { 4001 /* masks could be asymmetric, so check both ways */ 4002 return a == b || (a->cloneable & BIT(b->type) && 4003 b->cloneable & BIT(a->type)); 4004 } 4005 4006 static bool check_single_encoder_cloning(struct intel_atomic_state *state, 4007 struct intel_crtc *crtc, 4008 struct intel_encoder *encoder) 4009 { 4010 struct intel_encoder *source_encoder; 4011 struct drm_connector *connector; 4012 struct drm_connector_state *connector_state; 4013 int i; 4014 4015 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4016 if (connector_state->crtc != &crtc->base) 4017 continue; 4018 4019 source_encoder = 4020 to_intel_encoder(connector_state->best_encoder); 4021 if (!encoders_cloneable(encoder, source_encoder)) 4022 return false; 4023 } 4024 4025 return true; 4026 } 4027 4028 static int icl_add_linked_planes(struct intel_atomic_state *state) 4029 { 4030 struct intel_plane *plane, *linked; 4031 struct intel_plane_state *plane_state, *linked_plane_state; 4032 int i; 4033 4034 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4035 linked = plane_state->planar_linked_plane; 4036 4037 if (!linked) 4038 continue; 4039 4040 linked_plane_state = intel_atomic_get_plane_state(state, linked); 4041 if (IS_ERR(linked_plane_state)) 4042 return PTR_ERR(linked_plane_state); 4043 4044 drm_WARN_ON(state->base.dev, 4045 linked_plane_state->planar_linked_plane != plane); 4046 drm_WARN_ON(state->base.dev, 4047 linked_plane_state->planar_slave == plane_state->planar_slave); 4048 } 4049 4050 return 0; 4051 } 4052 4053 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state) 4054 { 4055 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4056 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4057 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 4058 struct intel_plane *plane, *linked; 4059 struct intel_plane_state *plane_state; 4060 int i; 4061 4062 if (DISPLAY_VER(dev_priv) < 11) 4063 return 0; 4064 4065 /* 4066 * Destroy all old plane links and make the slave plane invisible 4067 * in the crtc_state->active_planes mask. 4068 */ 4069 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4070 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane) 4071 continue; 4072 4073 plane_state->planar_linked_plane = NULL; 4074 if (plane_state->planar_slave && !plane_state->uapi.visible) { 4075 crtc_state->enabled_planes &= ~BIT(plane->id); 4076 crtc_state->active_planes &= ~BIT(plane->id); 4077 crtc_state->update_planes |= BIT(plane->id); 4078 crtc_state->data_rate[plane->id] = 0; 4079 crtc_state->rel_data_rate[plane->id] = 0; 4080 } 4081 4082 plane_state->planar_slave = false; 4083 } 4084 4085 if (!crtc_state->nv12_planes) 4086 return 0; 4087 4088 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4089 struct intel_plane_state *linked_state = NULL; 4090 4091 if (plane->pipe != crtc->pipe || 4092 !(crtc_state->nv12_planes & BIT(plane->id))) 4093 continue; 4094 4095 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) { 4096 if (!icl_is_nv12_y_plane(dev_priv, linked->id)) 4097 continue; 4098 4099 if (crtc_state->active_planes & BIT(linked->id)) 4100 continue; 4101 4102 linked_state = intel_atomic_get_plane_state(state, linked); 4103 if (IS_ERR(linked_state)) 4104 return PTR_ERR(linked_state); 4105 4106 break; 4107 } 4108 4109 if (!linked_state) { 4110 drm_dbg_kms(&dev_priv->drm, 4111 "Need %d free Y planes for planar YUV\n", 4112 hweight8(crtc_state->nv12_planes)); 4113 4114 return -EINVAL; 4115 } 4116 4117 plane_state->planar_linked_plane = linked; 4118 4119 linked_state->planar_slave = true; 4120 linked_state->planar_linked_plane = plane; 4121 crtc_state->enabled_planes |= BIT(linked->id); 4122 crtc_state->active_planes |= BIT(linked->id); 4123 crtc_state->update_planes |= BIT(linked->id); 4124 crtc_state->data_rate[linked->id] = 4125 crtc_state->data_rate_y[plane->id]; 4126 crtc_state->rel_data_rate[linked->id] = 4127 crtc_state->rel_data_rate_y[plane->id]; 4128 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n", 4129 linked->base.name, plane->base.name); 4130 4131 /* Copy parameters to slave plane */ 4132 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE; 4133 linked_state->color_ctl = plane_state->color_ctl; 4134 linked_state->view = plane_state->view; 4135 linked_state->decrypt = plane_state->decrypt; 4136 4137 intel_plane_copy_hw_state(linked_state, plane_state); 4138 linked_state->uapi.src = plane_state->uapi.src; 4139 linked_state->uapi.dst = plane_state->uapi.dst; 4140 4141 if (icl_is_hdr_plane(dev_priv, plane->id)) { 4142 if (linked->id == PLANE_SPRITE5) 4143 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL; 4144 else if (linked->id == PLANE_SPRITE4) 4145 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL; 4146 else if (linked->id == PLANE_SPRITE3) 4147 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL; 4148 else if (linked->id == PLANE_SPRITE2) 4149 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL; 4150 else 4151 MISSING_CASE(linked->id); 4152 } 4153 } 4154 4155 return 0; 4156 } 4157 4158 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state) 4159 { 4160 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 4161 struct intel_atomic_state *state = 4162 to_intel_atomic_state(new_crtc_state->uapi.state); 4163 const struct intel_crtc_state *old_crtc_state = 4164 intel_atomic_get_old_crtc_state(state, crtc); 4165 4166 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes; 4167 } 4168 4169 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) 4170 { 4171 const struct drm_display_mode *pipe_mode = 4172 &crtc_state->hw.pipe_mode; 4173 int linetime_wm; 4174 4175 if (!crtc_state->hw.enable) 4176 return 0; 4177 4178 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4179 pipe_mode->crtc_clock); 4180 4181 return min(linetime_wm, 0x1ff); 4182 } 4183 4184 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, 4185 const struct intel_cdclk_state *cdclk_state) 4186 { 4187 const struct drm_display_mode *pipe_mode = 4188 &crtc_state->hw.pipe_mode; 4189 int linetime_wm; 4190 4191 if (!crtc_state->hw.enable) 4192 return 0; 4193 4194 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4195 cdclk_state->logical.cdclk); 4196 4197 return min(linetime_wm, 0x1ff); 4198 } 4199 4200 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) 4201 { 4202 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4203 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4204 const struct drm_display_mode *pipe_mode = 4205 &crtc_state->hw.pipe_mode; 4206 int linetime_wm; 4207 4208 if (!crtc_state->hw.enable) 4209 return 0; 4210 4211 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8, 4212 crtc_state->pixel_rate); 4213 4214 /* Display WA #1135: BXT:ALL GLK:ALL */ 4215 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 4216 skl_watermark_ipc_enabled(dev_priv)) 4217 linetime_wm /= 2; 4218 4219 return min(linetime_wm, 0x1ff); 4220 } 4221 4222 static int hsw_compute_linetime_wm(struct intel_atomic_state *state, 4223 struct intel_crtc *crtc) 4224 { 4225 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4226 struct intel_crtc_state *crtc_state = 4227 intel_atomic_get_new_crtc_state(state, crtc); 4228 const struct intel_cdclk_state *cdclk_state; 4229 4230 if (DISPLAY_VER(dev_priv) >= 9) 4231 crtc_state->linetime = skl_linetime_wm(crtc_state); 4232 else 4233 crtc_state->linetime = hsw_linetime_wm(crtc_state); 4234 4235 if (!hsw_crtc_supports_ips(crtc)) 4236 return 0; 4237 4238 cdclk_state = intel_atomic_get_cdclk_state(state); 4239 if (IS_ERR(cdclk_state)) 4240 return PTR_ERR(cdclk_state); 4241 4242 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state, 4243 cdclk_state); 4244 4245 return 0; 4246 } 4247 4248 static int intel_crtc_atomic_check(struct intel_atomic_state *state, 4249 struct intel_crtc *crtc) 4250 { 4251 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4252 struct intel_crtc_state *crtc_state = 4253 intel_atomic_get_new_crtc_state(state, crtc); 4254 int ret; 4255 4256 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) && 4257 intel_crtc_needs_modeset(crtc_state) && 4258 !crtc_state->hw.active) 4259 crtc_state->update_wm_post = true; 4260 4261 if (intel_crtc_needs_modeset(crtc_state)) { 4262 ret = intel_dpll_crtc_get_shared_dpll(state, crtc); 4263 if (ret) 4264 return ret; 4265 } 4266 4267 /* 4268 * May need to update pipe gamma enable bits 4269 * when C8 planes are getting enabled/disabled. 4270 */ 4271 if (c8_planes_changed(crtc_state)) 4272 crtc_state->uapi.color_mgmt_changed = true; 4273 4274 if (intel_crtc_needs_color_update(crtc_state)) { 4275 ret = intel_color_check(crtc_state); 4276 if (ret) 4277 return ret; 4278 } 4279 4280 ret = intel_compute_pipe_wm(state, crtc); 4281 if (ret) { 4282 drm_dbg_kms(&dev_priv->drm, 4283 "Target pipe watermarks are invalid\n"); 4284 return ret; 4285 } 4286 4287 /* 4288 * Calculate 'intermediate' watermarks that satisfy both the 4289 * old state and the new state. We can program these 4290 * immediately. 4291 */ 4292 ret = intel_compute_intermediate_wm(state, crtc); 4293 if (ret) { 4294 drm_dbg_kms(&dev_priv->drm, 4295 "No valid intermediate pipe watermarks are possible\n"); 4296 return ret; 4297 } 4298 4299 if (DISPLAY_VER(dev_priv) >= 9) { 4300 if (intel_crtc_needs_modeset(crtc_state) || 4301 intel_crtc_needs_fastset(crtc_state)) { 4302 ret = skl_update_scaler_crtc(crtc_state); 4303 if (ret) 4304 return ret; 4305 } 4306 4307 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state); 4308 if (ret) 4309 return ret; 4310 } 4311 4312 if (HAS_IPS(dev_priv)) { 4313 ret = hsw_ips_compute_config(state, crtc); 4314 if (ret) 4315 return ret; 4316 } 4317 4318 if (DISPLAY_VER(dev_priv) >= 9 || 4319 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 4320 ret = hsw_compute_linetime_wm(state, crtc); 4321 if (ret) 4322 return ret; 4323 4324 } 4325 4326 ret = intel_psr2_sel_fetch_update(state, crtc); 4327 if (ret) 4328 return ret; 4329 4330 return 0; 4331 } 4332 4333 static int 4334 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state, 4335 struct intel_crtc_state *crtc_state) 4336 { 4337 struct drm_connector *connector = conn_state->connector; 4338 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 4339 const struct drm_display_info *info = &connector->display_info; 4340 int bpp; 4341 4342 switch (conn_state->max_bpc) { 4343 case 6 ... 7: 4344 bpp = 6 * 3; 4345 break; 4346 case 8 ... 9: 4347 bpp = 8 * 3; 4348 break; 4349 case 10 ... 11: 4350 bpp = 10 * 3; 4351 break; 4352 case 12 ... 16: 4353 bpp = 12 * 3; 4354 break; 4355 default: 4356 MISSING_CASE(conn_state->max_bpc); 4357 return -EINVAL; 4358 } 4359 4360 if (bpp < crtc_state->pipe_bpp) { 4361 drm_dbg_kms(&i915->drm, 4362 "[CONNECTOR:%d:%s] Limiting display bpp to %d " 4363 "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n", 4364 connector->base.id, connector->name, 4365 bpp, 3 * info->bpc, 4366 3 * conn_state->max_requested_bpc, 4367 crtc_state->pipe_bpp); 4368 4369 crtc_state->pipe_bpp = bpp; 4370 } 4371 4372 return 0; 4373 } 4374 4375 static int 4376 compute_baseline_pipe_bpp(struct intel_atomic_state *state, 4377 struct intel_crtc *crtc) 4378 { 4379 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4380 struct intel_crtc_state *crtc_state = 4381 intel_atomic_get_new_crtc_state(state, crtc); 4382 struct drm_connector *connector; 4383 struct drm_connector_state *connector_state; 4384 int bpp, i; 4385 4386 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 4387 IS_CHERRYVIEW(dev_priv))) 4388 bpp = 10*3; 4389 else if (DISPLAY_VER(dev_priv) >= 5) 4390 bpp = 12*3; 4391 else 4392 bpp = 8*3; 4393 4394 crtc_state->pipe_bpp = bpp; 4395 4396 /* Clamp display bpp to connector max bpp */ 4397 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4398 int ret; 4399 4400 if (connector_state->crtc != &crtc->base) 4401 continue; 4402 4403 ret = compute_sink_pipe_bpp(connector_state, crtc_state); 4404 if (ret) 4405 return ret; 4406 } 4407 4408 return 0; 4409 } 4410 4411 static bool check_digital_port_conflicts(struct intel_atomic_state *state) 4412 { 4413 struct drm_device *dev = state->base.dev; 4414 struct drm_connector *connector; 4415 struct drm_connector_list_iter conn_iter; 4416 unsigned int used_ports = 0; 4417 unsigned int used_mst_ports = 0; 4418 bool ret = true; 4419 4420 /* 4421 * We're going to peek into connector->state, 4422 * hence connection_mutex must be held. 4423 */ 4424 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex); 4425 4426 /* 4427 * Walk the connector list instead of the encoder 4428 * list to detect the problem on ddi platforms 4429 * where there's just one encoder per digital port. 4430 */ 4431 drm_connector_list_iter_begin(dev, &conn_iter); 4432 drm_for_each_connector_iter(connector, &conn_iter) { 4433 struct drm_connector_state *connector_state; 4434 struct intel_encoder *encoder; 4435 4436 connector_state = 4437 drm_atomic_get_new_connector_state(&state->base, 4438 connector); 4439 if (!connector_state) 4440 connector_state = connector->state; 4441 4442 if (!connector_state->best_encoder) 4443 continue; 4444 4445 encoder = to_intel_encoder(connector_state->best_encoder); 4446 4447 drm_WARN_ON(dev, !connector_state->crtc); 4448 4449 switch (encoder->type) { 4450 case INTEL_OUTPUT_DDI: 4451 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev)))) 4452 break; 4453 fallthrough; 4454 case INTEL_OUTPUT_DP: 4455 case INTEL_OUTPUT_HDMI: 4456 case INTEL_OUTPUT_EDP: 4457 /* the same port mustn't appear more than once */ 4458 if (used_ports & BIT(encoder->port)) 4459 ret = false; 4460 4461 used_ports |= BIT(encoder->port); 4462 break; 4463 case INTEL_OUTPUT_DP_MST: 4464 used_mst_ports |= 4465 1 << encoder->port; 4466 break; 4467 default: 4468 break; 4469 } 4470 } 4471 drm_connector_list_iter_end(&conn_iter); 4472 4473 /* can't mix MST and SST/HDMI on the same port */ 4474 if (used_ports & used_mst_ports) 4475 return false; 4476 4477 return ret; 4478 } 4479 4480 static void 4481 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state, 4482 struct intel_crtc *crtc) 4483 { 4484 struct intel_crtc_state *crtc_state = 4485 intel_atomic_get_new_crtc_state(state, crtc); 4486 4487 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 4488 4489 drm_property_replace_blob(&crtc_state->hw.degamma_lut, 4490 crtc_state->uapi.degamma_lut); 4491 drm_property_replace_blob(&crtc_state->hw.gamma_lut, 4492 crtc_state->uapi.gamma_lut); 4493 drm_property_replace_blob(&crtc_state->hw.ctm, 4494 crtc_state->uapi.ctm); 4495 } 4496 4497 static void 4498 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state, 4499 struct intel_crtc *crtc) 4500 { 4501 struct intel_crtc_state *crtc_state = 4502 intel_atomic_get_new_crtc_state(state, crtc); 4503 4504 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 4505 4506 crtc_state->hw.enable = crtc_state->uapi.enable; 4507 crtc_state->hw.active = crtc_state->uapi.active; 4508 drm_mode_copy(&crtc_state->hw.mode, 4509 &crtc_state->uapi.mode); 4510 drm_mode_copy(&crtc_state->hw.adjusted_mode, 4511 &crtc_state->uapi.adjusted_mode); 4512 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter; 4513 4514 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 4515 } 4516 4517 static void 4518 copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state, 4519 struct intel_crtc *slave_crtc) 4520 { 4521 struct intel_crtc_state *slave_crtc_state = 4522 intel_atomic_get_new_crtc_state(state, slave_crtc); 4523 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 4524 const struct intel_crtc_state *master_crtc_state = 4525 intel_atomic_get_new_crtc_state(state, master_crtc); 4526 4527 drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut, 4528 master_crtc_state->hw.degamma_lut); 4529 drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut, 4530 master_crtc_state->hw.gamma_lut); 4531 drm_property_replace_blob(&slave_crtc_state->hw.ctm, 4532 master_crtc_state->hw.ctm); 4533 4534 slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed; 4535 } 4536 4537 static int 4538 copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state, 4539 struct intel_crtc *slave_crtc) 4540 { 4541 struct intel_crtc_state *slave_crtc_state = 4542 intel_atomic_get_new_crtc_state(state, slave_crtc); 4543 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 4544 const struct intel_crtc_state *master_crtc_state = 4545 intel_atomic_get_new_crtc_state(state, master_crtc); 4546 struct intel_crtc_state *saved_state; 4547 4548 WARN_ON(master_crtc_state->bigjoiner_pipes != 4549 slave_crtc_state->bigjoiner_pipes); 4550 4551 saved_state = kmemdup(master_crtc_state, sizeof(*saved_state), GFP_KERNEL); 4552 if (!saved_state) 4553 return -ENOMEM; 4554 4555 /* preserve some things from the slave's original crtc state */ 4556 saved_state->uapi = slave_crtc_state->uapi; 4557 saved_state->scaler_state = slave_crtc_state->scaler_state; 4558 saved_state->shared_dpll = slave_crtc_state->shared_dpll; 4559 saved_state->dpll_hw_state = slave_crtc_state->dpll_hw_state; 4560 saved_state->crc_enabled = slave_crtc_state->crc_enabled; 4561 4562 intel_crtc_free_hw_state(slave_crtc_state); 4563 memcpy(slave_crtc_state, saved_state, sizeof(*slave_crtc_state)); 4564 kfree(saved_state); 4565 4566 /* Re-init hw state */ 4567 memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw)); 4568 slave_crtc_state->hw.enable = master_crtc_state->hw.enable; 4569 slave_crtc_state->hw.active = master_crtc_state->hw.active; 4570 drm_mode_copy(&slave_crtc_state->hw.mode, 4571 &master_crtc_state->hw.mode); 4572 drm_mode_copy(&slave_crtc_state->hw.pipe_mode, 4573 &master_crtc_state->hw.pipe_mode); 4574 drm_mode_copy(&slave_crtc_state->hw.adjusted_mode, 4575 &master_crtc_state->hw.adjusted_mode); 4576 slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter; 4577 4578 copy_bigjoiner_crtc_state_nomodeset(state, slave_crtc); 4579 4580 slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed; 4581 slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed; 4582 slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed; 4583 4584 WARN_ON(master_crtc_state->bigjoiner_pipes != 4585 slave_crtc_state->bigjoiner_pipes); 4586 4587 return 0; 4588 } 4589 4590 static int 4591 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state, 4592 struct intel_crtc *crtc) 4593 { 4594 struct intel_crtc_state *crtc_state = 4595 intel_atomic_get_new_crtc_state(state, crtc); 4596 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4597 struct intel_crtc_state *saved_state; 4598 4599 saved_state = intel_crtc_state_alloc(crtc); 4600 if (!saved_state) 4601 return -ENOMEM; 4602 4603 /* free the old crtc_state->hw members */ 4604 intel_crtc_free_hw_state(crtc_state); 4605 4606 /* FIXME: before the switch to atomic started, a new pipe_config was 4607 * kzalloc'd. Code that depends on any field being zero should be 4608 * fixed, so that the crtc_state can be safely duplicated. For now, 4609 * only fields that are know to not cause problems are preserved. */ 4610 4611 saved_state->uapi = crtc_state->uapi; 4612 saved_state->inherited = crtc_state->inherited; 4613 saved_state->scaler_state = crtc_state->scaler_state; 4614 saved_state->shared_dpll = crtc_state->shared_dpll; 4615 saved_state->dpll_hw_state = crtc_state->dpll_hw_state; 4616 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, 4617 sizeof(saved_state->icl_port_dplls)); 4618 saved_state->crc_enabled = crtc_state->crc_enabled; 4619 if (IS_G4X(dev_priv) || 4620 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 4621 saved_state->wm = crtc_state->wm; 4622 4623 memcpy(crtc_state, saved_state, sizeof(*crtc_state)); 4624 kfree(saved_state); 4625 4626 intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc); 4627 4628 return 0; 4629 } 4630 4631 static int 4632 intel_modeset_pipe_config(struct intel_atomic_state *state, 4633 struct intel_crtc *crtc) 4634 { 4635 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4636 struct intel_crtc_state *crtc_state = 4637 intel_atomic_get_new_crtc_state(state, crtc); 4638 struct drm_connector *connector; 4639 struct drm_connector_state *connector_state; 4640 int pipe_src_w, pipe_src_h; 4641 int base_bpp, ret, i; 4642 bool retry = true; 4643 4644 crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe; 4645 4646 crtc_state->framestart_delay = 1; 4647 4648 /* 4649 * Sanitize sync polarity flags based on requested ones. If neither 4650 * positive or negative polarity is requested, treat this as meaning 4651 * negative polarity. 4652 */ 4653 if (!(crtc_state->hw.adjusted_mode.flags & 4654 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) 4655 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; 4656 4657 if (!(crtc_state->hw.adjusted_mode.flags & 4658 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 4659 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; 4660 4661 ret = compute_baseline_pipe_bpp(state, crtc); 4662 if (ret) 4663 return ret; 4664 4665 base_bpp = crtc_state->pipe_bpp; 4666 4667 /* 4668 * Determine the real pipe dimensions. Note that stereo modes can 4669 * increase the actual pipe size due to the frame doubling and 4670 * insertion of additional space for blanks between the frame. This 4671 * is stored in the crtc timings. We use the requested mode to do this 4672 * computation to clearly distinguish it from the adjusted mode, which 4673 * can be changed by the connectors in the below retry loop. 4674 */ 4675 drm_mode_get_hv_timing(&crtc_state->hw.mode, 4676 &pipe_src_w, &pipe_src_h); 4677 drm_rect_init(&crtc_state->pipe_src, 0, 0, 4678 pipe_src_w, pipe_src_h); 4679 4680 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4681 struct intel_encoder *encoder = 4682 to_intel_encoder(connector_state->best_encoder); 4683 4684 if (connector_state->crtc != &crtc->base) 4685 continue; 4686 4687 if (!check_single_encoder_cloning(state, crtc, encoder)) { 4688 drm_dbg_kms(&i915->drm, 4689 "[ENCODER:%d:%s] rejecting invalid cloning configuration\n", 4690 encoder->base.base.id, encoder->base.name); 4691 return -EINVAL; 4692 } 4693 4694 /* 4695 * Determine output_types before calling the .compute_config() 4696 * hooks so that the hooks can use this information safely. 4697 */ 4698 if (encoder->compute_output_type) 4699 crtc_state->output_types |= 4700 BIT(encoder->compute_output_type(encoder, crtc_state, 4701 connector_state)); 4702 else 4703 crtc_state->output_types |= BIT(encoder->type); 4704 } 4705 4706 encoder_retry: 4707 /* Ensure the port clock defaults are reset when retrying. */ 4708 crtc_state->port_clock = 0; 4709 crtc_state->pixel_multiplier = 1; 4710 4711 /* Fill in default crtc timings, allow encoders to overwrite them. */ 4712 drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode, 4713 CRTC_STEREO_DOUBLE); 4714 4715 /* Pass our mode to the connectors and the CRTC to give them a chance to 4716 * adjust it according to limitations or connector properties, and also 4717 * a chance to reject the mode entirely. 4718 */ 4719 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4720 struct intel_encoder *encoder = 4721 to_intel_encoder(connector_state->best_encoder); 4722 4723 if (connector_state->crtc != &crtc->base) 4724 continue; 4725 4726 ret = encoder->compute_config(encoder, crtc_state, 4727 connector_state); 4728 if (ret == -EDEADLK) 4729 return ret; 4730 if (ret < 0) { 4731 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n", 4732 encoder->base.base.id, encoder->base.name, ret); 4733 return ret; 4734 } 4735 } 4736 4737 /* Set default port clock if not overwritten by the encoder. Needs to be 4738 * done afterwards in case the encoder adjusts the mode. */ 4739 if (!crtc_state->port_clock) 4740 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock 4741 * crtc_state->pixel_multiplier; 4742 4743 ret = intel_crtc_compute_config(state, crtc); 4744 if (ret == -EDEADLK) 4745 return ret; 4746 if (ret == -EAGAIN) { 4747 if (drm_WARN(&i915->drm, !retry, 4748 "[CRTC:%d:%s] loop in pipe configuration computation\n", 4749 crtc->base.base.id, crtc->base.name)) 4750 return -EINVAL; 4751 4752 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] bw constrained, retrying\n", 4753 crtc->base.base.id, crtc->base.name); 4754 retry = false; 4755 goto encoder_retry; 4756 } 4757 if (ret < 0) { 4758 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n", 4759 crtc->base.base.id, crtc->base.name, ret); 4760 return ret; 4761 } 4762 4763 /* Dithering seems to not pass-through bits correctly when it should, so 4764 * only enable it on 6bpc panels and when its not a compliance 4765 * test requesting 6bpc video pattern. 4766 */ 4767 crtc_state->dither = (crtc_state->pipe_bpp == 6*3) && 4768 !crtc_state->dither_force_disable; 4769 drm_dbg_kms(&i915->drm, 4770 "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n", 4771 crtc->base.base.id, crtc->base.name, 4772 base_bpp, crtc_state->pipe_bpp, crtc_state->dither); 4773 4774 return 0; 4775 } 4776 4777 static int 4778 intel_modeset_pipe_config_late(struct intel_atomic_state *state, 4779 struct intel_crtc *crtc) 4780 { 4781 struct intel_crtc_state *crtc_state = 4782 intel_atomic_get_new_crtc_state(state, crtc); 4783 struct drm_connector_state *conn_state; 4784 struct drm_connector *connector; 4785 int i; 4786 4787 intel_bigjoiner_adjust_pipe_src(crtc_state); 4788 4789 for_each_new_connector_in_state(&state->base, connector, 4790 conn_state, i) { 4791 struct intel_encoder *encoder = 4792 to_intel_encoder(conn_state->best_encoder); 4793 int ret; 4794 4795 if (conn_state->crtc != &crtc->base || 4796 !encoder->compute_config_late) 4797 continue; 4798 4799 ret = encoder->compute_config_late(encoder, crtc_state, 4800 conn_state); 4801 if (ret) 4802 return ret; 4803 } 4804 4805 return 0; 4806 } 4807 4808 bool intel_fuzzy_clock_check(int clock1, int clock2) 4809 { 4810 int diff; 4811 4812 if (clock1 == clock2) 4813 return true; 4814 4815 if (!clock1 || !clock2) 4816 return false; 4817 4818 diff = abs(clock1 - clock2); 4819 4820 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) 4821 return true; 4822 4823 return false; 4824 } 4825 4826 static bool 4827 intel_compare_link_m_n(const struct intel_link_m_n *m_n, 4828 const struct intel_link_m_n *m2_n2) 4829 { 4830 return m_n->tu == m2_n2->tu && 4831 m_n->data_m == m2_n2->data_m && 4832 m_n->data_n == m2_n2->data_n && 4833 m_n->link_m == m2_n2->link_m && 4834 m_n->link_n == m2_n2->link_n; 4835 } 4836 4837 static bool 4838 intel_compare_infoframe(const union hdmi_infoframe *a, 4839 const union hdmi_infoframe *b) 4840 { 4841 return memcmp(a, b, sizeof(*a)) == 0; 4842 } 4843 4844 static bool 4845 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a, 4846 const struct drm_dp_vsc_sdp *b) 4847 { 4848 return memcmp(a, b, sizeof(*a)) == 0; 4849 } 4850 4851 static bool 4852 intel_compare_buffer(const u8 *a, const u8 *b, size_t len) 4853 { 4854 return memcmp(a, b, len) == 0; 4855 } 4856 4857 static void 4858 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv, 4859 bool fastset, const char *name, 4860 const union hdmi_infoframe *a, 4861 const union hdmi_infoframe *b) 4862 { 4863 if (fastset) { 4864 if (!drm_debug_enabled(DRM_UT_KMS)) 4865 return; 4866 4867 drm_dbg_kms(&dev_priv->drm, 4868 "fastset requirement not met in %s infoframe\n", name); 4869 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 4870 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a); 4871 drm_dbg_kms(&dev_priv->drm, "found:\n"); 4872 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b); 4873 } else { 4874 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name); 4875 drm_err(&dev_priv->drm, "expected:\n"); 4876 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a); 4877 drm_err(&dev_priv->drm, "found:\n"); 4878 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b); 4879 } 4880 } 4881 4882 static void 4883 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv, 4884 bool fastset, const char *name, 4885 const struct drm_dp_vsc_sdp *a, 4886 const struct drm_dp_vsc_sdp *b) 4887 { 4888 if (fastset) { 4889 if (!drm_debug_enabled(DRM_UT_KMS)) 4890 return; 4891 4892 drm_dbg_kms(&dev_priv->drm, 4893 "fastset requirement not met in %s dp sdp\n", name); 4894 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 4895 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a); 4896 drm_dbg_kms(&dev_priv->drm, "found:\n"); 4897 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b); 4898 } else { 4899 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name); 4900 drm_err(&dev_priv->drm, "expected:\n"); 4901 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a); 4902 drm_err(&dev_priv->drm, "found:\n"); 4903 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b); 4904 } 4905 } 4906 4907 /* Returns the length up to and including the last differing byte */ 4908 static size_t 4909 memcmp_diff_len(const u8 *a, const u8 *b, size_t len) 4910 { 4911 int i; 4912 4913 for (i = len - 1; i >= 0; i--) { 4914 if (a[i] != b[i]) 4915 return i + 1; 4916 } 4917 4918 return 0; 4919 } 4920 4921 static void 4922 pipe_config_buffer_mismatch(struct drm_i915_private *dev_priv, 4923 bool fastset, const char *name, 4924 const u8 *a, const u8 *b, size_t len) 4925 { 4926 if (fastset) { 4927 if (!drm_debug_enabled(DRM_UT_KMS)) 4928 return; 4929 4930 /* only dump up to the last difference */ 4931 len = memcmp_diff_len(a, b, len); 4932 4933 drm_dbg_kms(&dev_priv->drm, 4934 "fastset requirement not met in %s buffer\n", name); 4935 print_hex_dump(KERN_DEBUG, "expected: ", DUMP_PREFIX_NONE, 4936 16, 0, a, len, false); 4937 print_hex_dump(KERN_DEBUG, "found: ", DUMP_PREFIX_NONE, 4938 16, 0, b, len, false); 4939 } else { 4940 /* only dump up to the last difference */ 4941 len = memcmp_diff_len(a, b, len); 4942 4943 drm_err(&dev_priv->drm, "mismatch in %s buffer\n", name); 4944 print_hex_dump(KERN_ERR, "expected: ", DUMP_PREFIX_NONE, 4945 16, 0, a, len, false); 4946 print_hex_dump(KERN_ERR, "found: ", DUMP_PREFIX_NONE, 4947 16, 0, b, len, false); 4948 } 4949 } 4950 4951 static void __printf(4, 5) 4952 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc, 4953 const char *name, const char *format, ...) 4954 { 4955 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4956 struct va_format vaf; 4957 va_list args; 4958 4959 va_start(args, format); 4960 vaf.fmt = format; 4961 vaf.va = &args; 4962 4963 if (fastset) 4964 drm_dbg_kms(&i915->drm, 4965 "[CRTC:%d:%s] fastset requirement not met in %s %pV\n", 4966 crtc->base.base.id, crtc->base.name, name, &vaf); 4967 else 4968 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n", 4969 crtc->base.base.id, crtc->base.name, name, &vaf); 4970 4971 va_end(args); 4972 } 4973 4974 static bool fastboot_enabled(struct drm_i915_private *dev_priv) 4975 { 4976 if (dev_priv->params.fastboot != -1) 4977 return dev_priv->params.fastboot; 4978 4979 /* Enable fastboot by default on Skylake and newer */ 4980 if (DISPLAY_VER(dev_priv) >= 9) 4981 return true; 4982 4983 /* Enable fastboot by default on VLV and CHV */ 4984 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 4985 return true; 4986 4987 /* Disabled by default on all others */ 4988 return false; 4989 } 4990 4991 bool 4992 intel_pipe_config_compare(const struct intel_crtc_state *current_config, 4993 const struct intel_crtc_state *pipe_config, 4994 bool fastset) 4995 { 4996 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev); 4997 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4998 bool ret = true; 4999 bool fixup_inherited = fastset && 5000 current_config->inherited && !pipe_config->inherited; 5001 5002 if (fixup_inherited && !fastboot_enabled(dev_priv)) { 5003 drm_dbg_kms(&dev_priv->drm, 5004 "initial modeset and fastboot not set\n"); 5005 ret = false; 5006 } 5007 5008 #define PIPE_CONF_CHECK_X(name) do { \ 5009 if (current_config->name != pipe_config->name) { \ 5010 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5011 "(expected 0x%08x, found 0x%08x)", \ 5012 current_config->name, \ 5013 pipe_config->name); \ 5014 ret = false; \ 5015 } \ 5016 } while (0) 5017 5018 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \ 5019 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \ 5020 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5021 "(expected 0x%08x, found 0x%08x)", \ 5022 current_config->name & (mask), \ 5023 pipe_config->name & (mask)); \ 5024 ret = false; \ 5025 } \ 5026 } while (0) 5027 5028 #define PIPE_CONF_CHECK_I(name) do { \ 5029 if (current_config->name != pipe_config->name) { \ 5030 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5031 "(expected %i, found %i)", \ 5032 current_config->name, \ 5033 pipe_config->name); \ 5034 ret = false; \ 5035 } \ 5036 } while (0) 5037 5038 #define PIPE_CONF_CHECK_BOOL(name) do { \ 5039 if (current_config->name != pipe_config->name) { \ 5040 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5041 "(expected %s, found %s)", \ 5042 str_yes_no(current_config->name), \ 5043 str_yes_no(pipe_config->name)); \ 5044 ret = false; \ 5045 } \ 5046 } while (0) 5047 5048 /* 5049 * Checks state where we only read out the enabling, but not the entire 5050 * state itself (like full infoframes or ELD for audio). These states 5051 * require a full modeset on bootup to fix up. 5052 */ 5053 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \ 5054 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \ 5055 PIPE_CONF_CHECK_BOOL(name); \ 5056 } else { \ 5057 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5058 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \ 5059 str_yes_no(current_config->name), \ 5060 str_yes_no(pipe_config->name)); \ 5061 ret = false; \ 5062 } \ 5063 } while (0) 5064 5065 #define PIPE_CONF_CHECK_P(name) do { \ 5066 if (current_config->name != pipe_config->name) { \ 5067 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5068 "(expected %p, found %p)", \ 5069 current_config->name, \ 5070 pipe_config->name); \ 5071 ret = false; \ 5072 } \ 5073 } while (0) 5074 5075 #define PIPE_CONF_CHECK_M_N(name) do { \ 5076 if (!intel_compare_link_m_n(¤t_config->name, \ 5077 &pipe_config->name)) { \ 5078 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5079 "(expected tu %i data %i/%i link %i/%i, " \ 5080 "found tu %i, data %i/%i link %i/%i)", \ 5081 current_config->name.tu, \ 5082 current_config->name.data_m, \ 5083 current_config->name.data_n, \ 5084 current_config->name.link_m, \ 5085 current_config->name.link_n, \ 5086 pipe_config->name.tu, \ 5087 pipe_config->name.data_m, \ 5088 pipe_config->name.data_n, \ 5089 pipe_config->name.link_m, \ 5090 pipe_config->name.link_n); \ 5091 ret = false; \ 5092 } \ 5093 } while (0) 5094 5095 #define PIPE_CONF_CHECK_TIMINGS(name) do { \ 5096 PIPE_CONF_CHECK_I(name.crtc_hdisplay); \ 5097 PIPE_CONF_CHECK_I(name.crtc_htotal); \ 5098 PIPE_CONF_CHECK_I(name.crtc_hblank_start); \ 5099 PIPE_CONF_CHECK_I(name.crtc_hblank_end); \ 5100 PIPE_CONF_CHECK_I(name.crtc_hsync_start); \ 5101 PIPE_CONF_CHECK_I(name.crtc_hsync_end); \ 5102 PIPE_CONF_CHECK_I(name.crtc_vdisplay); \ 5103 PIPE_CONF_CHECK_I(name.crtc_vtotal); \ 5104 PIPE_CONF_CHECK_I(name.crtc_vblank_start); \ 5105 PIPE_CONF_CHECK_I(name.crtc_vblank_end); \ 5106 PIPE_CONF_CHECK_I(name.crtc_vsync_start); \ 5107 PIPE_CONF_CHECK_I(name.crtc_vsync_end); \ 5108 } while (0) 5109 5110 #define PIPE_CONF_CHECK_RECT(name) do { \ 5111 PIPE_CONF_CHECK_I(name.x1); \ 5112 PIPE_CONF_CHECK_I(name.x2); \ 5113 PIPE_CONF_CHECK_I(name.y1); \ 5114 PIPE_CONF_CHECK_I(name.y2); \ 5115 } while (0) 5116 5117 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \ 5118 if ((current_config->name ^ pipe_config->name) & (mask)) { \ 5119 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5120 "(%x) (expected %i, found %i)", \ 5121 (mask), \ 5122 current_config->name & (mask), \ 5123 pipe_config->name & (mask)); \ 5124 ret = false; \ 5125 } \ 5126 } while (0) 5127 5128 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \ 5129 if (!intel_compare_infoframe(¤t_config->infoframes.name, \ 5130 &pipe_config->infoframes.name)) { \ 5131 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \ 5132 ¤t_config->infoframes.name, \ 5133 &pipe_config->infoframes.name); \ 5134 ret = false; \ 5135 } \ 5136 } while (0) 5137 5138 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \ 5139 if (!current_config->has_psr && !pipe_config->has_psr && \ 5140 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \ 5141 &pipe_config->infoframes.name)) { \ 5142 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \ 5143 ¤t_config->infoframes.name, \ 5144 &pipe_config->infoframes.name); \ 5145 ret = false; \ 5146 } \ 5147 } while (0) 5148 5149 #define PIPE_CONF_CHECK_BUFFER(name, len) do { \ 5150 BUILD_BUG_ON(sizeof(current_config->name) != (len)); \ 5151 BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \ 5152 if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \ 5153 pipe_config_buffer_mismatch(dev_priv, fastset, __stringify(name), \ 5154 current_config->name, \ 5155 pipe_config->name, \ 5156 (len)); \ 5157 ret = false; \ 5158 } \ 5159 } while (0) 5160 5161 #define PIPE_CONF_CHECK_COLOR_LUT(lut, is_pre_csc_lut) do { \ 5162 if (current_config->gamma_mode == pipe_config->gamma_mode && \ 5163 !intel_color_lut_equal(current_config, \ 5164 current_config->lut, pipe_config->lut, \ 5165 is_pre_csc_lut)) { \ 5166 pipe_config_mismatch(fastset, crtc, __stringify(lut), \ 5167 "hw_state doesn't match sw_state"); \ 5168 ret = false; \ 5169 } \ 5170 } while (0) 5171 5172 #define PIPE_CONF_CHECK_CSC(name) do { \ 5173 PIPE_CONF_CHECK_X(name.preoff[0]); \ 5174 PIPE_CONF_CHECK_X(name.preoff[1]); \ 5175 PIPE_CONF_CHECK_X(name.preoff[2]); \ 5176 PIPE_CONF_CHECK_X(name.coeff[0]); \ 5177 PIPE_CONF_CHECK_X(name.coeff[1]); \ 5178 PIPE_CONF_CHECK_X(name.coeff[2]); \ 5179 PIPE_CONF_CHECK_X(name.coeff[3]); \ 5180 PIPE_CONF_CHECK_X(name.coeff[4]); \ 5181 PIPE_CONF_CHECK_X(name.coeff[5]); \ 5182 PIPE_CONF_CHECK_X(name.coeff[6]); \ 5183 PIPE_CONF_CHECK_X(name.coeff[7]); \ 5184 PIPE_CONF_CHECK_X(name.coeff[8]); \ 5185 PIPE_CONF_CHECK_X(name.postoff[0]); \ 5186 PIPE_CONF_CHECK_X(name.postoff[1]); \ 5187 PIPE_CONF_CHECK_X(name.postoff[2]); \ 5188 } while (0) 5189 5190 #define PIPE_CONF_QUIRK(quirk) \ 5191 ((current_config->quirks | pipe_config->quirks) & (quirk)) 5192 5193 PIPE_CONF_CHECK_I(hw.enable); 5194 PIPE_CONF_CHECK_I(hw.active); 5195 5196 PIPE_CONF_CHECK_I(cpu_transcoder); 5197 PIPE_CONF_CHECK_I(mst_master_transcoder); 5198 5199 PIPE_CONF_CHECK_BOOL(has_pch_encoder); 5200 PIPE_CONF_CHECK_I(fdi_lanes); 5201 PIPE_CONF_CHECK_M_N(fdi_m_n); 5202 5203 PIPE_CONF_CHECK_I(lane_count); 5204 PIPE_CONF_CHECK_X(lane_lat_optim_mask); 5205 5206 if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) { 5207 if (!fastset || !pipe_config->seamless_m_n) 5208 PIPE_CONF_CHECK_M_N(dp_m_n); 5209 } else { 5210 PIPE_CONF_CHECK_M_N(dp_m_n); 5211 PIPE_CONF_CHECK_M_N(dp_m2_n2); 5212 } 5213 5214 PIPE_CONF_CHECK_X(output_types); 5215 5216 PIPE_CONF_CHECK_I(framestart_delay); 5217 PIPE_CONF_CHECK_I(msa_timing_delay); 5218 5219 PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode); 5220 PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode); 5221 5222 PIPE_CONF_CHECK_I(pixel_multiplier); 5223 5224 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5225 DRM_MODE_FLAG_INTERLACE); 5226 5227 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { 5228 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5229 DRM_MODE_FLAG_PHSYNC); 5230 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5231 DRM_MODE_FLAG_NHSYNC); 5232 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5233 DRM_MODE_FLAG_PVSYNC); 5234 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5235 DRM_MODE_FLAG_NVSYNC); 5236 } 5237 5238 PIPE_CONF_CHECK_I(output_format); 5239 PIPE_CONF_CHECK_BOOL(has_hdmi_sink); 5240 if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || 5241 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5242 PIPE_CONF_CHECK_BOOL(limited_color_range); 5243 5244 PIPE_CONF_CHECK_BOOL(hdmi_scrambling); 5245 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio); 5246 PIPE_CONF_CHECK_BOOL(has_infoframe); 5247 PIPE_CONF_CHECK_BOOL(fec_enable); 5248 5249 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio); 5250 PIPE_CONF_CHECK_BUFFER(eld, MAX_ELD_BYTES); 5251 5252 PIPE_CONF_CHECK_X(gmch_pfit.control); 5253 /* pfit ratios are autocomputed by the hw on gen4+ */ 5254 if (DISPLAY_VER(dev_priv) < 4) 5255 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); 5256 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); 5257 5258 /* 5259 * Changing the EDP transcoder input mux 5260 * (A_ONOFF vs. A_ON) requires a full modeset. 5261 */ 5262 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru); 5263 5264 if (!fastset) { 5265 PIPE_CONF_CHECK_RECT(pipe_src); 5266 5267 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled); 5268 PIPE_CONF_CHECK_RECT(pch_pfit.dst); 5269 5270 PIPE_CONF_CHECK_I(scaler_state.scaler_id); 5271 PIPE_CONF_CHECK_I(pixel_rate); 5272 5273 PIPE_CONF_CHECK_X(gamma_mode); 5274 if (IS_CHERRYVIEW(dev_priv)) 5275 PIPE_CONF_CHECK_X(cgm_mode); 5276 else 5277 PIPE_CONF_CHECK_X(csc_mode); 5278 PIPE_CONF_CHECK_BOOL(gamma_enable); 5279 PIPE_CONF_CHECK_BOOL(csc_enable); 5280 5281 PIPE_CONF_CHECK_I(linetime); 5282 PIPE_CONF_CHECK_I(ips_linetime); 5283 5284 PIPE_CONF_CHECK_COLOR_LUT(pre_csc_lut, true); 5285 PIPE_CONF_CHECK_COLOR_LUT(post_csc_lut, false); 5286 5287 PIPE_CONF_CHECK_CSC(csc); 5288 PIPE_CONF_CHECK_CSC(output_csc); 5289 5290 if (current_config->active_planes) { 5291 PIPE_CONF_CHECK_BOOL(has_psr); 5292 PIPE_CONF_CHECK_BOOL(has_psr2); 5293 PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); 5294 PIPE_CONF_CHECK_I(dc3co_exitline); 5295 } 5296 } 5297 5298 PIPE_CONF_CHECK_BOOL(double_wide); 5299 5300 if (dev_priv->display.dpll.mgr) { 5301 PIPE_CONF_CHECK_P(shared_dpll); 5302 5303 PIPE_CONF_CHECK_X(dpll_hw_state.dpll); 5304 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); 5305 PIPE_CONF_CHECK_X(dpll_hw_state.fp0); 5306 PIPE_CONF_CHECK_X(dpll_hw_state.fp1); 5307 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); 5308 PIPE_CONF_CHECK_X(dpll_hw_state.spll); 5309 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); 5310 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); 5311 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); 5312 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); 5313 PIPE_CONF_CHECK_X(dpll_hw_state.div0); 5314 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); 5315 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); 5316 PIPE_CONF_CHECK_X(dpll_hw_state.pll0); 5317 PIPE_CONF_CHECK_X(dpll_hw_state.pll1); 5318 PIPE_CONF_CHECK_X(dpll_hw_state.pll2); 5319 PIPE_CONF_CHECK_X(dpll_hw_state.pll3); 5320 PIPE_CONF_CHECK_X(dpll_hw_state.pll6); 5321 PIPE_CONF_CHECK_X(dpll_hw_state.pll8); 5322 PIPE_CONF_CHECK_X(dpll_hw_state.pll9); 5323 PIPE_CONF_CHECK_X(dpll_hw_state.pll10); 5324 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); 5325 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl); 5326 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1); 5327 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl); 5328 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0); 5329 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1); 5330 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf); 5331 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock); 5332 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc); 5333 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias); 5334 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias); 5335 } 5336 5337 PIPE_CONF_CHECK_X(dsi_pll.ctrl); 5338 PIPE_CONF_CHECK_X(dsi_pll.div); 5339 5340 if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5) 5341 PIPE_CONF_CHECK_I(pipe_bpp); 5342 5343 if (!fastset || !pipe_config->seamless_m_n) { 5344 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock); 5345 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock); 5346 } 5347 PIPE_CONF_CHECK_I(port_clock); 5348 5349 PIPE_CONF_CHECK_I(min_voltage_level); 5350 5351 if (current_config->has_psr || pipe_config->has_psr) 5352 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable, 5353 ~intel_hdmi_infoframe_enable(DP_SDP_VSC)); 5354 else 5355 PIPE_CONF_CHECK_X(infoframes.enable); 5356 5357 PIPE_CONF_CHECK_X(infoframes.gcp); 5358 PIPE_CONF_CHECK_INFOFRAME(avi); 5359 PIPE_CONF_CHECK_INFOFRAME(spd); 5360 PIPE_CONF_CHECK_INFOFRAME(hdmi); 5361 PIPE_CONF_CHECK_INFOFRAME(drm); 5362 PIPE_CONF_CHECK_DP_VSC_SDP(vsc); 5363 5364 PIPE_CONF_CHECK_X(sync_mode_slaves_mask); 5365 PIPE_CONF_CHECK_I(master_transcoder); 5366 PIPE_CONF_CHECK_X(bigjoiner_pipes); 5367 5368 PIPE_CONF_CHECK_I(dsc.compression_enable); 5369 PIPE_CONF_CHECK_I(dsc.dsc_split); 5370 PIPE_CONF_CHECK_I(dsc.compressed_bpp); 5371 5372 PIPE_CONF_CHECK_BOOL(splitter.enable); 5373 PIPE_CONF_CHECK_I(splitter.link_count); 5374 PIPE_CONF_CHECK_I(splitter.pixel_overlap); 5375 5376 if (!fastset) 5377 PIPE_CONF_CHECK_BOOL(vrr.enable); 5378 PIPE_CONF_CHECK_I(vrr.vmin); 5379 PIPE_CONF_CHECK_I(vrr.vmax); 5380 PIPE_CONF_CHECK_I(vrr.flipline); 5381 PIPE_CONF_CHECK_I(vrr.pipeline_full); 5382 PIPE_CONF_CHECK_I(vrr.guardband); 5383 5384 #undef PIPE_CONF_CHECK_X 5385 #undef PIPE_CONF_CHECK_I 5386 #undef PIPE_CONF_CHECK_BOOL 5387 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE 5388 #undef PIPE_CONF_CHECK_P 5389 #undef PIPE_CONF_CHECK_FLAGS 5390 #undef PIPE_CONF_CHECK_COLOR_LUT 5391 #undef PIPE_CONF_CHECK_TIMINGS 5392 #undef PIPE_CONF_CHECK_RECT 5393 #undef PIPE_CONF_QUIRK 5394 5395 return ret; 5396 } 5397 5398 static void 5399 intel_verify_planes(struct intel_atomic_state *state) 5400 { 5401 struct intel_plane *plane; 5402 const struct intel_plane_state *plane_state; 5403 int i; 5404 5405 for_each_new_intel_plane_in_state(state, plane, 5406 plane_state, i) 5407 assert_plane(plane, plane_state->planar_slave || 5408 plane_state->uapi.visible); 5409 } 5410 5411 int intel_modeset_all_pipes(struct intel_atomic_state *state, 5412 const char *reason) 5413 { 5414 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 5415 struct intel_crtc *crtc; 5416 5417 /* 5418 * Add all pipes to the state, and force 5419 * a modeset on all the active ones. 5420 */ 5421 for_each_intel_crtc(&dev_priv->drm, crtc) { 5422 struct intel_crtc_state *crtc_state; 5423 int ret; 5424 5425 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 5426 if (IS_ERR(crtc_state)) 5427 return PTR_ERR(crtc_state); 5428 5429 if (!crtc_state->hw.active || 5430 intel_crtc_needs_modeset(crtc_state)) 5431 continue; 5432 5433 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] Full modeset due to %s\n", 5434 crtc->base.base.id, crtc->base.name, reason); 5435 5436 crtc_state->uapi.mode_changed = true; 5437 crtc_state->update_pipe = false; 5438 5439 ret = drm_atomic_add_affected_connectors(&state->base, 5440 &crtc->base); 5441 if (ret) 5442 return ret; 5443 5444 ret = intel_dp_mst_add_topology_state_for_crtc(state, crtc); 5445 if (ret) 5446 return ret; 5447 5448 ret = intel_atomic_add_affected_planes(state, crtc); 5449 if (ret) 5450 return ret; 5451 5452 crtc_state->update_planes |= crtc_state->active_planes; 5453 crtc_state->async_flip_planes = 0; 5454 crtc_state->do_async_flip = false; 5455 } 5456 5457 return 0; 5458 } 5459 5460 /* 5461 * This implements the workaround described in the "notes" section of the mode 5462 * set sequence documentation. When going from no pipes or single pipe to 5463 * multiple pipes, and planes are enabled after the pipe, we need to wait at 5464 * least 2 vblanks on the first pipe before enabling planes on the second pipe. 5465 */ 5466 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state) 5467 { 5468 struct intel_crtc_state *crtc_state; 5469 struct intel_crtc *crtc; 5470 struct intel_crtc_state *first_crtc_state = NULL; 5471 struct intel_crtc_state *other_crtc_state = NULL; 5472 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; 5473 int i; 5474 5475 /* look at all crtc's that are going to be enabled in during modeset */ 5476 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5477 if (!crtc_state->hw.active || 5478 !intel_crtc_needs_modeset(crtc_state)) 5479 continue; 5480 5481 if (first_crtc_state) { 5482 other_crtc_state = crtc_state; 5483 break; 5484 } else { 5485 first_crtc_state = crtc_state; 5486 first_pipe = crtc->pipe; 5487 } 5488 } 5489 5490 /* No workaround needed? */ 5491 if (!first_crtc_state) 5492 return 0; 5493 5494 /* w/a possibly needed, check how many crtc's are already enabled. */ 5495 for_each_intel_crtc(state->base.dev, crtc) { 5496 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 5497 if (IS_ERR(crtc_state)) 5498 return PTR_ERR(crtc_state); 5499 5500 crtc_state->hsw_workaround_pipe = INVALID_PIPE; 5501 5502 if (!crtc_state->hw.active || 5503 intel_crtc_needs_modeset(crtc_state)) 5504 continue; 5505 5506 /* 2 or more enabled crtcs means no need for w/a */ 5507 if (enabled_pipe != INVALID_PIPE) 5508 return 0; 5509 5510 enabled_pipe = crtc->pipe; 5511 } 5512 5513 if (enabled_pipe != INVALID_PIPE) 5514 first_crtc_state->hsw_workaround_pipe = enabled_pipe; 5515 else if (other_crtc_state) 5516 other_crtc_state->hsw_workaround_pipe = first_pipe; 5517 5518 return 0; 5519 } 5520 5521 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 5522 u8 active_pipes) 5523 { 5524 const struct intel_crtc_state *crtc_state; 5525 struct intel_crtc *crtc; 5526 int i; 5527 5528 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5529 if (crtc_state->hw.active) 5530 active_pipes |= BIT(crtc->pipe); 5531 else 5532 active_pipes &= ~BIT(crtc->pipe); 5533 } 5534 5535 return active_pipes; 5536 } 5537 5538 static int intel_modeset_checks(struct intel_atomic_state *state) 5539 { 5540 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 5541 5542 state->modeset = true; 5543 5544 if (IS_HASWELL(dev_priv)) 5545 return hsw_mode_set_planes_workaround(state); 5546 5547 return 0; 5548 } 5549 5550 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state, 5551 struct intel_crtc_state *new_crtc_state) 5552 { 5553 struct drm_i915_private *i915 = to_i915(old_crtc_state->uapi.crtc->dev); 5554 5555 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) { 5556 drm_dbg_kms(&i915->drm, "fastset requirement not met, forcing full modeset\n"); 5557 5558 return; 5559 } 5560 5561 new_crtc_state->uapi.mode_changed = false; 5562 if (!intel_crtc_needs_modeset(new_crtc_state)) 5563 new_crtc_state->update_pipe = true; 5564 } 5565 5566 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state, 5567 struct intel_crtc *crtc, 5568 u8 plane_ids_mask) 5569 { 5570 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 5571 struct intel_plane *plane; 5572 5573 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 5574 struct intel_plane_state *plane_state; 5575 5576 if ((plane_ids_mask & BIT(plane->id)) == 0) 5577 continue; 5578 5579 plane_state = intel_atomic_get_plane_state(state, plane); 5580 if (IS_ERR(plane_state)) 5581 return PTR_ERR(plane_state); 5582 } 5583 5584 return 0; 5585 } 5586 5587 int intel_atomic_add_affected_planes(struct intel_atomic_state *state, 5588 struct intel_crtc *crtc) 5589 { 5590 const struct intel_crtc_state *old_crtc_state = 5591 intel_atomic_get_old_crtc_state(state, crtc); 5592 const struct intel_crtc_state *new_crtc_state = 5593 intel_atomic_get_new_crtc_state(state, crtc); 5594 5595 return intel_crtc_add_planes_to_state(state, crtc, 5596 old_crtc_state->enabled_planes | 5597 new_crtc_state->enabled_planes); 5598 } 5599 5600 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv) 5601 { 5602 /* See {hsw,vlv,ivb}_plane_ratio() */ 5603 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) || 5604 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) || 5605 IS_IVYBRIDGE(dev_priv); 5606 } 5607 5608 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state, 5609 struct intel_crtc *crtc, 5610 struct intel_crtc *other) 5611 { 5612 const struct intel_plane_state *plane_state; 5613 struct intel_plane *plane; 5614 u8 plane_ids = 0; 5615 int i; 5616 5617 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 5618 if (plane->pipe == crtc->pipe) 5619 plane_ids |= BIT(plane->id); 5620 } 5621 5622 return intel_crtc_add_planes_to_state(state, other, plane_ids); 5623 } 5624 5625 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state) 5626 { 5627 struct drm_i915_private *i915 = to_i915(state->base.dev); 5628 const struct intel_crtc_state *crtc_state; 5629 struct intel_crtc *crtc; 5630 int i; 5631 5632 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5633 struct intel_crtc *other; 5634 5635 for_each_intel_crtc_in_pipe_mask(&i915->drm, other, 5636 crtc_state->bigjoiner_pipes) { 5637 int ret; 5638 5639 if (crtc == other) 5640 continue; 5641 5642 ret = intel_crtc_add_bigjoiner_planes(state, crtc, other); 5643 if (ret) 5644 return ret; 5645 } 5646 } 5647 5648 return 0; 5649 } 5650 5651 static int intel_atomic_check_planes(struct intel_atomic_state *state) 5652 { 5653 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 5654 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 5655 struct intel_plane_state *plane_state; 5656 struct intel_plane *plane; 5657 struct intel_crtc *crtc; 5658 int i, ret; 5659 5660 ret = icl_add_linked_planes(state); 5661 if (ret) 5662 return ret; 5663 5664 ret = intel_bigjoiner_add_affected_planes(state); 5665 if (ret) 5666 return ret; 5667 5668 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 5669 ret = intel_plane_atomic_check(state, plane); 5670 if (ret) { 5671 drm_dbg_atomic(&dev_priv->drm, 5672 "[PLANE:%d:%s] atomic driver check failed\n", 5673 plane->base.base.id, plane->base.name); 5674 return ret; 5675 } 5676 } 5677 5678 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 5679 new_crtc_state, i) { 5680 u8 old_active_planes, new_active_planes; 5681 5682 ret = icl_check_nv12_planes(new_crtc_state); 5683 if (ret) 5684 return ret; 5685 5686 /* 5687 * On some platforms the number of active planes affects 5688 * the planes' minimum cdclk calculation. Add such planes 5689 * to the state before we compute the minimum cdclk. 5690 */ 5691 if (!active_planes_affects_min_cdclk(dev_priv)) 5692 continue; 5693 5694 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 5695 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 5696 5697 if (hweight8(old_active_planes) == hweight8(new_active_planes)) 5698 continue; 5699 5700 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes); 5701 if (ret) 5702 return ret; 5703 } 5704 5705 return 0; 5706 } 5707 5708 static int intel_atomic_check_crtcs(struct intel_atomic_state *state) 5709 { 5710 struct intel_crtc_state *crtc_state; 5711 struct intel_crtc *crtc; 5712 int i; 5713 5714 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5715 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 5716 int ret; 5717 5718 ret = intel_crtc_atomic_check(state, crtc); 5719 if (ret) { 5720 drm_dbg_atomic(&i915->drm, 5721 "[CRTC:%d:%s] atomic driver check failed\n", 5722 crtc->base.base.id, crtc->base.name); 5723 return ret; 5724 } 5725 } 5726 5727 return 0; 5728 } 5729 5730 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, 5731 u8 transcoders) 5732 { 5733 const struct intel_crtc_state *new_crtc_state; 5734 struct intel_crtc *crtc; 5735 int i; 5736 5737 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 5738 if (new_crtc_state->hw.enable && 5739 transcoders & BIT(new_crtc_state->cpu_transcoder) && 5740 intel_crtc_needs_modeset(new_crtc_state)) 5741 return true; 5742 } 5743 5744 return false; 5745 } 5746 5747 static bool intel_pipes_need_modeset(struct intel_atomic_state *state, 5748 u8 pipes) 5749 { 5750 const struct intel_crtc_state *new_crtc_state; 5751 struct intel_crtc *crtc; 5752 int i; 5753 5754 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 5755 if (new_crtc_state->hw.enable && 5756 pipes & BIT(crtc->pipe) && 5757 intel_crtc_needs_modeset(new_crtc_state)) 5758 return true; 5759 } 5760 5761 return false; 5762 } 5763 5764 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state, 5765 struct intel_crtc *master_crtc) 5766 { 5767 struct drm_i915_private *i915 = to_i915(state->base.dev); 5768 struct intel_crtc_state *master_crtc_state = 5769 intel_atomic_get_new_crtc_state(state, master_crtc); 5770 struct intel_crtc *slave_crtc; 5771 5772 if (!master_crtc_state->bigjoiner_pipes) 5773 return 0; 5774 5775 /* sanity check */ 5776 if (drm_WARN_ON(&i915->drm, 5777 master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state))) 5778 return -EINVAL; 5779 5780 if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) { 5781 drm_dbg_kms(&i915->drm, 5782 "[CRTC:%d:%s] Cannot act as big joiner master " 5783 "(need 0x%x as pipes, only 0x%x possible)\n", 5784 master_crtc->base.base.id, master_crtc->base.name, 5785 master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915)); 5786 return -EINVAL; 5787 } 5788 5789 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 5790 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 5791 struct intel_crtc_state *slave_crtc_state; 5792 int ret; 5793 5794 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc); 5795 if (IS_ERR(slave_crtc_state)) 5796 return PTR_ERR(slave_crtc_state); 5797 5798 /* master being enabled, slave was already configured? */ 5799 if (slave_crtc_state->uapi.enable) { 5800 drm_dbg_kms(&i915->drm, 5801 "[CRTC:%d:%s] Slave is enabled as normal CRTC, but " 5802 "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n", 5803 slave_crtc->base.base.id, slave_crtc->base.name, 5804 master_crtc->base.base.id, master_crtc->base.name); 5805 return -EINVAL; 5806 } 5807 5808 /* 5809 * The state copy logic assumes the master crtc gets processed 5810 * before the slave crtc during the main compute_config loop. 5811 * This works because the crtcs are created in pipe order, 5812 * and the hardware requires master pipe < slave pipe as well. 5813 * Should that change we need to rethink the logic. 5814 */ 5815 if (WARN_ON(drm_crtc_index(&master_crtc->base) > 5816 drm_crtc_index(&slave_crtc->base))) 5817 return -EINVAL; 5818 5819 drm_dbg_kms(&i915->drm, 5820 "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n", 5821 slave_crtc->base.base.id, slave_crtc->base.name, 5822 master_crtc->base.base.id, master_crtc->base.name); 5823 5824 slave_crtc_state->bigjoiner_pipes = 5825 master_crtc_state->bigjoiner_pipes; 5826 5827 ret = copy_bigjoiner_crtc_state_modeset(state, slave_crtc); 5828 if (ret) 5829 return ret; 5830 } 5831 5832 return 0; 5833 } 5834 5835 static void kill_bigjoiner_slave(struct intel_atomic_state *state, 5836 struct intel_crtc *master_crtc) 5837 { 5838 struct drm_i915_private *i915 = to_i915(state->base.dev); 5839 struct intel_crtc_state *master_crtc_state = 5840 intel_atomic_get_new_crtc_state(state, master_crtc); 5841 struct intel_crtc *slave_crtc; 5842 5843 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 5844 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 5845 struct intel_crtc_state *slave_crtc_state = 5846 intel_atomic_get_new_crtc_state(state, slave_crtc); 5847 5848 slave_crtc_state->bigjoiner_pipes = 0; 5849 5850 intel_crtc_copy_uapi_to_hw_state_modeset(state, slave_crtc); 5851 } 5852 5853 master_crtc_state->bigjoiner_pipes = 0; 5854 } 5855 5856 /** 5857 * DOC: asynchronous flip implementation 5858 * 5859 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC 5860 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL. 5861 * Correspondingly, support is currently added for primary plane only. 5862 * 5863 * Async flip can only change the plane surface address, so anything else 5864 * changing is rejected from the intel_async_flip_check_hw() function. 5865 * Once this check is cleared, flip done interrupt is enabled using 5866 * the intel_crtc_enable_flip_done() function. 5867 * 5868 * As soon as the surface address register is written, flip done interrupt is 5869 * generated and the requested events are sent to the usersapce in the interrupt 5870 * handler itself. The timestamp and sequence sent during the flip done event 5871 * correspond to the last vblank and have no relation to the actual time when 5872 * the flip done event was sent. 5873 */ 5874 static int intel_async_flip_check_uapi(struct intel_atomic_state *state, 5875 struct intel_crtc *crtc) 5876 { 5877 struct drm_i915_private *i915 = to_i915(state->base.dev); 5878 const struct intel_crtc_state *new_crtc_state = 5879 intel_atomic_get_new_crtc_state(state, crtc); 5880 const struct intel_plane_state *old_plane_state; 5881 struct intel_plane_state *new_plane_state; 5882 struct intel_plane *plane; 5883 int i; 5884 5885 if (!new_crtc_state->uapi.async_flip) 5886 return 0; 5887 5888 if (!new_crtc_state->uapi.active) { 5889 drm_dbg_kms(&i915->drm, 5890 "[CRTC:%d:%s] not active\n", 5891 crtc->base.base.id, crtc->base.name); 5892 return -EINVAL; 5893 } 5894 5895 if (intel_crtc_needs_modeset(new_crtc_state)) { 5896 drm_dbg_kms(&i915->drm, 5897 "[CRTC:%d:%s] modeset required\n", 5898 crtc->base.base.id, crtc->base.name); 5899 return -EINVAL; 5900 } 5901 5902 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 5903 new_plane_state, i) { 5904 if (plane->pipe != crtc->pipe) 5905 continue; 5906 5907 /* 5908 * TODO: Async flip is only supported through the page flip IOCTL 5909 * as of now. So support currently added for primary plane only. 5910 * Support for other planes on platforms on which supports 5911 * this(vlv/chv and icl+) should be added when async flip is 5912 * enabled in the atomic IOCTL path. 5913 */ 5914 if (!plane->async_flip) { 5915 drm_dbg_kms(&i915->drm, 5916 "[PLANE:%d:%s] async flip not supported\n", 5917 plane->base.base.id, plane->base.name); 5918 return -EINVAL; 5919 } 5920 5921 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) { 5922 drm_dbg_kms(&i915->drm, 5923 "[PLANE:%d:%s] no old or new framebuffer\n", 5924 plane->base.base.id, plane->base.name); 5925 return -EINVAL; 5926 } 5927 } 5928 5929 return 0; 5930 } 5931 5932 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc) 5933 { 5934 struct drm_i915_private *i915 = to_i915(state->base.dev); 5935 const struct intel_crtc_state *old_crtc_state, *new_crtc_state; 5936 const struct intel_plane_state *new_plane_state, *old_plane_state; 5937 struct intel_plane *plane; 5938 int i; 5939 5940 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 5941 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 5942 5943 if (!new_crtc_state->uapi.async_flip) 5944 return 0; 5945 5946 if (!new_crtc_state->hw.active) { 5947 drm_dbg_kms(&i915->drm, 5948 "[CRTC:%d:%s] not active\n", 5949 crtc->base.base.id, crtc->base.name); 5950 return -EINVAL; 5951 } 5952 5953 if (intel_crtc_needs_modeset(new_crtc_state)) { 5954 drm_dbg_kms(&i915->drm, 5955 "[CRTC:%d:%s] modeset required\n", 5956 crtc->base.base.id, crtc->base.name); 5957 return -EINVAL; 5958 } 5959 5960 if (old_crtc_state->active_planes != new_crtc_state->active_planes) { 5961 drm_dbg_kms(&i915->drm, 5962 "[CRTC:%d:%s] Active planes cannot be in async flip\n", 5963 crtc->base.base.id, crtc->base.name); 5964 return -EINVAL; 5965 } 5966 5967 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 5968 new_plane_state, i) { 5969 if (plane->pipe != crtc->pipe) 5970 continue; 5971 5972 /* 5973 * Only async flip capable planes should be in the state 5974 * if we're really about to ask the hardware to perform 5975 * an async flip. We should never get this far otherwise. 5976 */ 5977 if (drm_WARN_ON(&i915->drm, 5978 new_crtc_state->do_async_flip && !plane->async_flip)) 5979 return -EINVAL; 5980 5981 /* 5982 * Only check async flip capable planes other planes 5983 * may be involved in the initial commit due to 5984 * the wm0/ddb optimization. 5985 * 5986 * TODO maybe should track which planes actually 5987 * were requested to do the async flip... 5988 */ 5989 if (!plane->async_flip) 5990 continue; 5991 5992 /* 5993 * FIXME: This check is kept generic for all platforms. 5994 * Need to verify this for all gen9 platforms to enable 5995 * this selectively if required. 5996 */ 5997 switch (new_plane_state->hw.fb->modifier) { 5998 case DRM_FORMAT_MOD_LINEAR: 5999 /* 6000 * FIXME: Async on Linear buffer is supported on ICL as 6001 * but with additional alignment and fbc restrictions 6002 * need to be taken care of. These aren't applicable for 6003 * gen12+. 6004 */ 6005 if (DISPLAY_VER(i915) < 12) { 6006 drm_dbg_kms(&i915->drm, 6007 "[PLANE:%d:%s] Modifier does not support async flips\n", 6008 plane->base.base.id, plane->base.name); 6009 return -EINVAL; 6010 } 6011 break; 6012 6013 case I915_FORMAT_MOD_X_TILED: 6014 case I915_FORMAT_MOD_Y_TILED: 6015 case I915_FORMAT_MOD_Yf_TILED: 6016 case I915_FORMAT_MOD_4_TILED: 6017 break; 6018 default: 6019 drm_dbg_kms(&i915->drm, 6020 "[PLANE:%d:%s] Modifier does not support async flips\n", 6021 plane->base.base.id, plane->base.name); 6022 return -EINVAL; 6023 } 6024 6025 if (new_plane_state->hw.fb->format->num_planes > 1) { 6026 drm_dbg_kms(&i915->drm, 6027 "[PLANE:%d:%s] Planar formats do not support async flips\n", 6028 plane->base.base.id, plane->base.name); 6029 return -EINVAL; 6030 } 6031 6032 if (old_plane_state->view.color_plane[0].mapping_stride != 6033 new_plane_state->view.color_plane[0].mapping_stride) { 6034 drm_dbg_kms(&i915->drm, 6035 "[PLANE:%d:%s] Stride cannot be changed in async flip\n", 6036 plane->base.base.id, plane->base.name); 6037 return -EINVAL; 6038 } 6039 6040 if (old_plane_state->hw.fb->modifier != 6041 new_plane_state->hw.fb->modifier) { 6042 drm_dbg_kms(&i915->drm, 6043 "[PLANE:%d:%s] Modifier cannot be changed in async flip\n", 6044 plane->base.base.id, plane->base.name); 6045 return -EINVAL; 6046 } 6047 6048 if (old_plane_state->hw.fb->format != 6049 new_plane_state->hw.fb->format) { 6050 drm_dbg_kms(&i915->drm, 6051 "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n", 6052 plane->base.base.id, plane->base.name); 6053 return -EINVAL; 6054 } 6055 6056 if (old_plane_state->hw.rotation != 6057 new_plane_state->hw.rotation) { 6058 drm_dbg_kms(&i915->drm, 6059 "[PLANE:%d:%s] Rotation cannot be changed in async flip\n", 6060 plane->base.base.id, plane->base.name); 6061 return -EINVAL; 6062 } 6063 6064 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) || 6065 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) { 6066 drm_dbg_kms(&i915->drm, 6067 "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n", 6068 plane->base.base.id, plane->base.name); 6069 return -EINVAL; 6070 } 6071 6072 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) { 6073 drm_dbg_kms(&i915->drm, 6074 "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n", 6075 plane->base.base.id, plane->base.name); 6076 return -EINVAL; 6077 } 6078 6079 if (old_plane_state->hw.pixel_blend_mode != 6080 new_plane_state->hw.pixel_blend_mode) { 6081 drm_dbg_kms(&i915->drm, 6082 "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n", 6083 plane->base.base.id, plane->base.name); 6084 return -EINVAL; 6085 } 6086 6087 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) { 6088 drm_dbg_kms(&i915->drm, 6089 "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n", 6090 plane->base.base.id, plane->base.name); 6091 return -EINVAL; 6092 } 6093 6094 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) { 6095 drm_dbg_kms(&i915->drm, 6096 "[PLANE:%d:%s] Color range cannot be changed in async flip\n", 6097 plane->base.base.id, plane->base.name); 6098 return -EINVAL; 6099 } 6100 6101 /* plane decryption is allow to change only in synchronous flips */ 6102 if (old_plane_state->decrypt != new_plane_state->decrypt) { 6103 drm_dbg_kms(&i915->drm, 6104 "[PLANE:%d:%s] Decryption cannot be changed in async flip\n", 6105 plane->base.base.id, plane->base.name); 6106 return -EINVAL; 6107 } 6108 } 6109 6110 return 0; 6111 } 6112 6113 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state) 6114 { 6115 struct drm_i915_private *i915 = to_i915(state->base.dev); 6116 struct intel_crtc_state *crtc_state; 6117 struct intel_crtc *crtc; 6118 u8 affected_pipes = 0; 6119 u8 modeset_pipes = 0; 6120 int i; 6121 6122 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6123 affected_pipes |= crtc_state->bigjoiner_pipes; 6124 if (intel_crtc_needs_modeset(crtc_state)) 6125 modeset_pipes |= crtc_state->bigjoiner_pipes; 6126 } 6127 6128 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) { 6129 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6130 if (IS_ERR(crtc_state)) 6131 return PTR_ERR(crtc_state); 6132 } 6133 6134 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) { 6135 int ret; 6136 6137 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6138 6139 crtc_state->uapi.mode_changed = true; 6140 6141 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); 6142 if (ret) 6143 return ret; 6144 6145 ret = intel_atomic_add_affected_planes(state, crtc); 6146 if (ret) 6147 return ret; 6148 } 6149 6150 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6151 /* Kill old bigjoiner link, we may re-establish afterwards */ 6152 if (intel_crtc_needs_modeset(crtc_state) && 6153 intel_crtc_is_bigjoiner_master(crtc_state)) 6154 kill_bigjoiner_slave(state, crtc); 6155 } 6156 6157 return 0; 6158 } 6159 6160 /** 6161 * intel_atomic_check - validate state object 6162 * @dev: drm device 6163 * @_state: state to validate 6164 */ 6165 int intel_atomic_check(struct drm_device *dev, 6166 struct drm_atomic_state *_state) 6167 { 6168 struct drm_i915_private *dev_priv = to_i915(dev); 6169 struct intel_atomic_state *state = to_intel_atomic_state(_state); 6170 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6171 struct intel_crtc *crtc; 6172 int ret, i; 6173 bool any_ms = false; 6174 6175 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6176 new_crtc_state, i) { 6177 /* 6178 * crtc's state no longer considered to be inherited 6179 * after the first userspace/client initiated commit. 6180 */ 6181 if (!state->internal) 6182 new_crtc_state->inherited = false; 6183 6184 if (new_crtc_state->inherited != old_crtc_state->inherited) 6185 new_crtc_state->uapi.mode_changed = true; 6186 6187 if (new_crtc_state->uapi.scaling_filter != 6188 old_crtc_state->uapi.scaling_filter) 6189 new_crtc_state->uapi.mode_changed = true; 6190 } 6191 6192 intel_vrr_check_modeset(state); 6193 6194 ret = drm_atomic_helper_check_modeset(dev, &state->base); 6195 if (ret) 6196 goto fail; 6197 6198 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6199 ret = intel_async_flip_check_uapi(state, crtc); 6200 if (ret) 6201 return ret; 6202 } 6203 6204 ret = intel_bigjoiner_add_affected_crtcs(state); 6205 if (ret) 6206 goto fail; 6207 6208 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6209 new_crtc_state, i) { 6210 if (!intel_crtc_needs_modeset(new_crtc_state)) { 6211 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 6212 copy_bigjoiner_crtc_state_nomodeset(state, crtc); 6213 else 6214 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 6215 continue; 6216 } 6217 6218 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) { 6219 drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable); 6220 continue; 6221 } 6222 6223 ret = intel_crtc_prepare_cleared_state(state, crtc); 6224 if (ret) 6225 goto fail; 6226 6227 if (!new_crtc_state->hw.enable) 6228 continue; 6229 6230 ret = intel_modeset_pipe_config(state, crtc); 6231 if (ret) 6232 goto fail; 6233 6234 ret = intel_atomic_check_bigjoiner(state, crtc); 6235 if (ret) 6236 goto fail; 6237 } 6238 6239 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6240 new_crtc_state, i) { 6241 if (!intel_crtc_needs_modeset(new_crtc_state)) 6242 continue; 6243 6244 if (new_crtc_state->hw.enable) { 6245 ret = intel_modeset_pipe_config_late(state, crtc); 6246 if (ret) 6247 goto fail; 6248 } 6249 6250 intel_crtc_check_fastset(old_crtc_state, new_crtc_state); 6251 } 6252 6253 /** 6254 * Check if fastset is allowed by external dependencies like other 6255 * pipes and transcoders. 6256 * 6257 * Right now it only forces a fullmodeset when the MST master 6258 * transcoder did not changed but the pipe of the master transcoder 6259 * needs a fullmodeset so all slaves also needs to do a fullmodeset or 6260 * in case of port synced crtcs, if one of the synced crtcs 6261 * needs a full modeset, all other synced crtcs should be 6262 * forced a full modeset. 6263 */ 6264 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6265 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state)) 6266 continue; 6267 6268 if (intel_dp_mst_is_slave_trans(new_crtc_state)) { 6269 enum transcoder master = new_crtc_state->mst_master_transcoder; 6270 6271 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) { 6272 new_crtc_state->uapi.mode_changed = true; 6273 new_crtc_state->update_pipe = false; 6274 } 6275 } 6276 6277 if (is_trans_port_sync_mode(new_crtc_state)) { 6278 u8 trans = new_crtc_state->sync_mode_slaves_mask; 6279 6280 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER) 6281 trans |= BIT(new_crtc_state->master_transcoder); 6282 6283 if (intel_cpu_transcoders_need_modeset(state, trans)) { 6284 new_crtc_state->uapi.mode_changed = true; 6285 new_crtc_state->update_pipe = false; 6286 } 6287 } 6288 6289 if (new_crtc_state->bigjoiner_pipes) { 6290 if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) { 6291 new_crtc_state->uapi.mode_changed = true; 6292 new_crtc_state->update_pipe = false; 6293 } 6294 } 6295 } 6296 6297 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6298 new_crtc_state, i) { 6299 if (!intel_crtc_needs_modeset(new_crtc_state)) 6300 continue; 6301 6302 any_ms = true; 6303 6304 intel_release_shared_dplls(state, crtc); 6305 } 6306 6307 if (any_ms && !check_digital_port_conflicts(state)) { 6308 drm_dbg_kms(&dev_priv->drm, 6309 "rejecting conflicting digital port configuration\n"); 6310 ret = -EINVAL; 6311 goto fail; 6312 } 6313 6314 ret = drm_dp_mst_atomic_check(&state->base); 6315 if (ret) 6316 goto fail; 6317 6318 ret = intel_atomic_check_planes(state); 6319 if (ret) 6320 goto fail; 6321 6322 ret = intel_compute_global_watermarks(state); 6323 if (ret) 6324 goto fail; 6325 6326 ret = intel_bw_atomic_check(state); 6327 if (ret) 6328 goto fail; 6329 6330 ret = intel_cdclk_atomic_check(state, &any_ms); 6331 if (ret) 6332 goto fail; 6333 6334 if (intel_any_crtc_needs_modeset(state)) 6335 any_ms = true; 6336 6337 if (any_ms) { 6338 ret = intel_modeset_checks(state); 6339 if (ret) 6340 goto fail; 6341 6342 ret = intel_modeset_calc_cdclk(state); 6343 if (ret) 6344 return ret; 6345 } 6346 6347 ret = intel_atomic_check_crtcs(state); 6348 if (ret) 6349 goto fail; 6350 6351 ret = intel_fbc_atomic_check(state); 6352 if (ret) 6353 goto fail; 6354 6355 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6356 new_crtc_state, i) { 6357 intel_color_assert_luts(new_crtc_state); 6358 6359 ret = intel_async_flip_check_hw(state, crtc); 6360 if (ret) 6361 goto fail; 6362 6363 /* Either full modeset or fastset (or neither), never both */ 6364 drm_WARN_ON(&dev_priv->drm, 6365 intel_crtc_needs_modeset(new_crtc_state) && 6366 intel_crtc_needs_fastset(new_crtc_state)); 6367 6368 if (!intel_crtc_needs_modeset(new_crtc_state) && 6369 !intel_crtc_needs_fastset(new_crtc_state)) 6370 continue; 6371 6372 intel_crtc_state_dump(new_crtc_state, state, 6373 intel_crtc_needs_modeset(new_crtc_state) ? 6374 "modeset" : "fastset"); 6375 } 6376 6377 return 0; 6378 6379 fail: 6380 if (ret == -EDEADLK) 6381 return ret; 6382 6383 /* 6384 * FIXME would probably be nice to know which crtc specifically 6385 * caused the failure, in cases where we can pinpoint it. 6386 */ 6387 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6388 new_crtc_state, i) 6389 intel_crtc_state_dump(new_crtc_state, state, "failed"); 6390 6391 return ret; 6392 } 6393 6394 static int intel_atomic_prepare_commit(struct intel_atomic_state *state) 6395 { 6396 struct intel_crtc_state *crtc_state; 6397 struct intel_crtc *crtc; 6398 int i, ret; 6399 6400 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base); 6401 if (ret < 0) 6402 return ret; 6403 6404 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6405 if (intel_crtc_needs_color_update(crtc_state)) 6406 intel_color_prepare_commit(crtc_state); 6407 } 6408 6409 return 0; 6410 } 6411 6412 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 6413 struct intel_crtc_state *crtc_state) 6414 { 6415 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6416 6417 if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes) 6418 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 6419 6420 if (crtc_state->has_pch_encoder) { 6421 enum pipe pch_transcoder = 6422 intel_crtc_pch_transcoder(crtc); 6423 6424 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true); 6425 } 6426 } 6427 6428 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, 6429 const struct intel_crtc_state *new_crtc_state) 6430 { 6431 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 6432 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6433 6434 /* 6435 * Update pipe size and adjust fitter if needed: the reason for this is 6436 * that in compute_mode_changes we check the native mode (not the pfit 6437 * mode) to see if we can flip rather than do a full mode set. In the 6438 * fastboot case, we'll flip, but if we don't update the pipesrc and 6439 * pfit state, we'll end up with a big fb scanned out into the wrong 6440 * sized surface. 6441 */ 6442 intel_set_pipe_src_size(new_crtc_state); 6443 6444 /* on skylake this is done by detaching scalers */ 6445 if (DISPLAY_VER(dev_priv) >= 9) { 6446 if (new_crtc_state->pch_pfit.enabled) 6447 skl_pfit_enable(new_crtc_state); 6448 } else if (HAS_PCH_SPLIT(dev_priv)) { 6449 if (new_crtc_state->pch_pfit.enabled) 6450 ilk_pfit_enable(new_crtc_state); 6451 else if (old_crtc_state->pch_pfit.enabled) 6452 ilk_pfit_disable(old_crtc_state); 6453 } 6454 6455 /* 6456 * The register is supposedly single buffered so perhaps 6457 * not 100% correct to do this here. But SKL+ calculate 6458 * this based on the adjust pixel rate so pfit changes do 6459 * affect it and so it must be updated for fastsets. 6460 * HSW/BDW only really need this here for fastboot, after 6461 * that the value should not change without a full modeset. 6462 */ 6463 if (DISPLAY_VER(dev_priv) >= 9 || 6464 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 6465 hsw_set_linetime_wm(new_crtc_state); 6466 6467 if (new_crtc_state->seamless_m_n) 6468 intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder, 6469 &new_crtc_state->dp_m_n); 6470 } 6471 6472 static void commit_pipe_pre_planes(struct intel_atomic_state *state, 6473 struct intel_crtc *crtc) 6474 { 6475 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6476 const struct intel_crtc_state *old_crtc_state = 6477 intel_atomic_get_old_crtc_state(state, crtc); 6478 const struct intel_crtc_state *new_crtc_state = 6479 intel_atomic_get_new_crtc_state(state, crtc); 6480 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 6481 6482 /* 6483 * During modesets pipe configuration was programmed as the 6484 * CRTC was enabled. 6485 */ 6486 if (!modeset) { 6487 if (intel_crtc_needs_color_update(new_crtc_state)) 6488 intel_color_commit_arm(new_crtc_state); 6489 6490 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 6491 bdw_set_pipe_misc(new_crtc_state); 6492 6493 if (intel_crtc_needs_fastset(new_crtc_state)) 6494 intel_pipe_fastset(old_crtc_state, new_crtc_state); 6495 } 6496 6497 intel_psr2_program_trans_man_trk_ctl(new_crtc_state); 6498 6499 intel_atomic_update_watermarks(state, crtc); 6500 } 6501 6502 static void commit_pipe_post_planes(struct intel_atomic_state *state, 6503 struct intel_crtc *crtc) 6504 { 6505 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6506 const struct intel_crtc_state *new_crtc_state = 6507 intel_atomic_get_new_crtc_state(state, crtc); 6508 6509 /* 6510 * Disable the scaler(s) after the plane(s) so that we don't 6511 * get a catastrophic underrun even if the two operations 6512 * end up happening in two different frames. 6513 */ 6514 if (DISPLAY_VER(dev_priv) >= 9 && 6515 !intel_crtc_needs_modeset(new_crtc_state)) 6516 skl_detach_scalers(new_crtc_state); 6517 } 6518 6519 static void intel_enable_crtc(struct intel_atomic_state *state, 6520 struct intel_crtc *crtc) 6521 { 6522 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6523 const struct intel_crtc_state *new_crtc_state = 6524 intel_atomic_get_new_crtc_state(state, crtc); 6525 6526 if (!intel_crtc_needs_modeset(new_crtc_state)) 6527 return; 6528 6529 /* VRR will be enable later, if required */ 6530 intel_crtc_update_active_timings(new_crtc_state, false); 6531 6532 dev_priv->display.funcs.display->crtc_enable(state, crtc); 6533 6534 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 6535 return; 6536 6537 /* vblanks work again, re-enable pipe CRC. */ 6538 intel_crtc_enable_pipe_crc(crtc); 6539 } 6540 6541 static void intel_update_crtc(struct intel_atomic_state *state, 6542 struct intel_crtc *crtc) 6543 { 6544 struct drm_i915_private *i915 = to_i915(state->base.dev); 6545 const struct intel_crtc_state *old_crtc_state = 6546 intel_atomic_get_old_crtc_state(state, crtc); 6547 struct intel_crtc_state *new_crtc_state = 6548 intel_atomic_get_new_crtc_state(state, crtc); 6549 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 6550 6551 if (old_crtc_state->inherited || 6552 intel_crtc_needs_modeset(new_crtc_state)) { 6553 if (HAS_DPT(i915)) 6554 intel_dpt_configure(crtc); 6555 } 6556 6557 if (vrr_enabling(old_crtc_state, new_crtc_state)) { 6558 intel_vrr_enable(new_crtc_state); 6559 intel_crtc_update_active_timings(new_crtc_state, 6560 new_crtc_state->vrr.enable); 6561 } 6562 6563 if (!modeset) { 6564 if (new_crtc_state->preload_luts && 6565 intel_crtc_needs_color_update(new_crtc_state)) 6566 intel_color_load_luts(new_crtc_state); 6567 6568 intel_pre_plane_update(state, crtc); 6569 6570 if (intel_crtc_needs_fastset(new_crtc_state)) 6571 intel_encoders_update_pipe(state, crtc); 6572 6573 if (DISPLAY_VER(i915) >= 11 && 6574 intel_crtc_needs_fastset(new_crtc_state)) 6575 icl_set_pipe_chicken(new_crtc_state); 6576 } 6577 6578 intel_fbc_update(state, crtc); 6579 6580 drm_WARN_ON(&i915->drm, !intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF)); 6581 6582 if (!modeset && 6583 intel_crtc_needs_color_update(new_crtc_state)) 6584 intel_color_commit_noarm(new_crtc_state); 6585 6586 intel_crtc_planes_update_noarm(state, crtc); 6587 6588 /* Perform vblank evasion around commit operation */ 6589 intel_pipe_update_start(new_crtc_state); 6590 6591 commit_pipe_pre_planes(state, crtc); 6592 6593 intel_crtc_planes_update_arm(state, crtc); 6594 6595 commit_pipe_post_planes(state, crtc); 6596 6597 intel_pipe_update_end(new_crtc_state); 6598 6599 /* 6600 * We usually enable FIFO underrun interrupts as part of the 6601 * CRTC enable sequence during modesets. But when we inherit a 6602 * valid pipe configuration from the BIOS we need to take care 6603 * of enabling them on the CRTC's first fastset. 6604 */ 6605 if (intel_crtc_needs_fastset(new_crtc_state) && !modeset && 6606 old_crtc_state->inherited) 6607 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state); 6608 } 6609 6610 static void intel_old_crtc_state_disables(struct intel_atomic_state *state, 6611 struct intel_crtc_state *old_crtc_state, 6612 struct intel_crtc_state *new_crtc_state, 6613 struct intel_crtc *crtc) 6614 { 6615 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6616 6617 /* 6618 * We need to disable pipe CRC before disabling the pipe, 6619 * or we race against vblank off. 6620 */ 6621 intel_crtc_disable_pipe_crc(crtc); 6622 6623 dev_priv->display.funcs.display->crtc_disable(state, crtc); 6624 crtc->active = false; 6625 intel_fbc_disable(crtc); 6626 6627 if (!new_crtc_state->hw.active) 6628 intel_initial_watermarks(state, crtc); 6629 } 6630 6631 static void intel_commit_modeset_disables(struct intel_atomic_state *state) 6632 { 6633 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 6634 struct intel_crtc *crtc; 6635 u32 handled = 0; 6636 int i; 6637 6638 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6639 new_crtc_state, i) { 6640 if (!intel_crtc_needs_modeset(new_crtc_state)) 6641 continue; 6642 6643 if (!old_crtc_state->hw.active) 6644 continue; 6645 6646 intel_pre_plane_update(state, crtc); 6647 intel_crtc_disable_planes(state, crtc); 6648 } 6649 6650 /* Only disable port sync and MST slaves */ 6651 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6652 new_crtc_state, i) { 6653 if (!intel_crtc_needs_modeset(new_crtc_state)) 6654 continue; 6655 6656 if (!old_crtc_state->hw.active) 6657 continue; 6658 6659 /* In case of Transcoder port Sync master slave CRTCs can be 6660 * assigned in any order and we need to make sure that 6661 * slave CRTCs are disabled first and then master CRTC since 6662 * Slave vblanks are masked till Master Vblanks. 6663 */ 6664 if (!is_trans_port_sync_slave(old_crtc_state) && 6665 !intel_dp_mst_is_slave_trans(old_crtc_state) && 6666 !intel_crtc_is_bigjoiner_slave(old_crtc_state)) 6667 continue; 6668 6669 intel_old_crtc_state_disables(state, old_crtc_state, 6670 new_crtc_state, crtc); 6671 handled |= BIT(crtc->pipe); 6672 } 6673 6674 /* Disable everything else left on */ 6675 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6676 new_crtc_state, i) { 6677 if (!intel_crtc_needs_modeset(new_crtc_state) || 6678 (handled & BIT(crtc->pipe))) 6679 continue; 6680 6681 if (!old_crtc_state->hw.active) 6682 continue; 6683 6684 intel_old_crtc_state_disables(state, old_crtc_state, 6685 new_crtc_state, crtc); 6686 } 6687 } 6688 6689 static void intel_commit_modeset_enables(struct intel_atomic_state *state) 6690 { 6691 struct intel_crtc_state *new_crtc_state; 6692 struct intel_crtc *crtc; 6693 int i; 6694 6695 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6696 if (!new_crtc_state->hw.active) 6697 continue; 6698 6699 intel_enable_crtc(state, crtc); 6700 intel_update_crtc(state, crtc); 6701 } 6702 } 6703 6704 static void skl_commit_modeset_enables(struct intel_atomic_state *state) 6705 { 6706 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6707 struct intel_crtc *crtc; 6708 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6709 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; 6710 u8 update_pipes = 0, modeset_pipes = 0; 6711 int i; 6712 6713 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6714 enum pipe pipe = crtc->pipe; 6715 6716 if (!new_crtc_state->hw.active) 6717 continue; 6718 6719 /* ignore allocations for crtc's that have been turned off. */ 6720 if (!intel_crtc_needs_modeset(new_crtc_state)) { 6721 entries[pipe] = old_crtc_state->wm.skl.ddb; 6722 update_pipes |= BIT(pipe); 6723 } else { 6724 modeset_pipes |= BIT(pipe); 6725 } 6726 } 6727 6728 /* 6729 * Whenever the number of active pipes changes, we need to make sure we 6730 * update the pipes in the right order so that their ddb allocations 6731 * never overlap with each other between CRTC updates. Otherwise we'll 6732 * cause pipe underruns and other bad stuff. 6733 * 6734 * So first lets enable all pipes that do not need a fullmodeset as 6735 * those don't have any external dependency. 6736 */ 6737 while (update_pipes) { 6738 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6739 new_crtc_state, i) { 6740 enum pipe pipe = crtc->pipe; 6741 6742 if ((update_pipes & BIT(pipe)) == 0) 6743 continue; 6744 6745 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 6746 entries, I915_MAX_PIPES, pipe)) 6747 continue; 6748 6749 entries[pipe] = new_crtc_state->wm.skl.ddb; 6750 update_pipes &= ~BIT(pipe); 6751 6752 intel_update_crtc(state, crtc); 6753 6754 /* 6755 * If this is an already active pipe, it's DDB changed, 6756 * and this isn't the last pipe that needs updating 6757 * then we need to wait for a vblank to pass for the 6758 * new ddb allocation to take effect. 6759 */ 6760 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, 6761 &old_crtc_state->wm.skl.ddb) && 6762 (update_pipes | modeset_pipes)) 6763 intel_crtc_wait_for_next_vblank(crtc); 6764 } 6765 } 6766 6767 update_pipes = modeset_pipes; 6768 6769 /* 6770 * Enable all pipes that needs a modeset and do not depends on other 6771 * pipes 6772 */ 6773 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6774 enum pipe pipe = crtc->pipe; 6775 6776 if ((modeset_pipes & BIT(pipe)) == 0) 6777 continue; 6778 6779 if (intel_dp_mst_is_slave_trans(new_crtc_state) || 6780 is_trans_port_sync_master(new_crtc_state) || 6781 intel_crtc_is_bigjoiner_master(new_crtc_state)) 6782 continue; 6783 6784 modeset_pipes &= ~BIT(pipe); 6785 6786 intel_enable_crtc(state, crtc); 6787 } 6788 6789 /* 6790 * Then we enable all remaining pipes that depend on other 6791 * pipes: MST slaves and port sync masters, big joiner master 6792 */ 6793 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6794 enum pipe pipe = crtc->pipe; 6795 6796 if ((modeset_pipes & BIT(pipe)) == 0) 6797 continue; 6798 6799 modeset_pipes &= ~BIT(pipe); 6800 6801 intel_enable_crtc(state, crtc); 6802 } 6803 6804 /* 6805 * Finally we do the plane updates/etc. for all pipes that got enabled. 6806 */ 6807 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6808 enum pipe pipe = crtc->pipe; 6809 6810 if ((update_pipes & BIT(pipe)) == 0) 6811 continue; 6812 6813 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 6814 entries, I915_MAX_PIPES, pipe)); 6815 6816 entries[pipe] = new_crtc_state->wm.skl.ddb; 6817 update_pipes &= ~BIT(pipe); 6818 6819 intel_update_crtc(state, crtc); 6820 } 6821 6822 drm_WARN_ON(&dev_priv->drm, modeset_pipes); 6823 drm_WARN_ON(&dev_priv->drm, update_pipes); 6824 } 6825 6826 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) 6827 { 6828 struct intel_atomic_state *state, *next; 6829 struct llist_node *freed; 6830 6831 freed = llist_del_all(&dev_priv->display.atomic_helper.free_list); 6832 llist_for_each_entry_safe(state, next, freed, freed) 6833 drm_atomic_state_put(&state->base); 6834 } 6835 6836 void intel_atomic_helper_free_state_worker(struct work_struct *work) 6837 { 6838 struct drm_i915_private *dev_priv = 6839 container_of(work, typeof(*dev_priv), display.atomic_helper.free_work); 6840 6841 intel_atomic_helper_free_state(dev_priv); 6842 } 6843 6844 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) 6845 { 6846 struct wait_queue_entry wait_fence, wait_reset; 6847 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); 6848 6849 init_wait_entry(&wait_fence, 0); 6850 init_wait_entry(&wait_reset, 0); 6851 for (;;) { 6852 prepare_to_wait(&intel_state->commit_ready.wait, 6853 &wait_fence, TASK_UNINTERRUPTIBLE); 6854 prepare_to_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 6855 I915_RESET_MODESET), 6856 &wait_reset, TASK_UNINTERRUPTIBLE); 6857 6858 6859 if (i915_sw_fence_done(&intel_state->commit_ready) || 6860 test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags)) 6861 break; 6862 6863 schedule(); 6864 } 6865 finish_wait(&intel_state->commit_ready.wait, &wait_fence); 6866 finish_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 6867 I915_RESET_MODESET), 6868 &wait_reset); 6869 } 6870 6871 static void intel_atomic_cleanup_work(struct work_struct *work) 6872 { 6873 struct intel_atomic_state *state = 6874 container_of(work, struct intel_atomic_state, base.commit_work); 6875 struct drm_i915_private *i915 = to_i915(state->base.dev); 6876 struct intel_crtc_state *old_crtc_state; 6877 struct intel_crtc *crtc; 6878 int i; 6879 6880 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) 6881 intel_color_cleanup_commit(old_crtc_state); 6882 6883 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base); 6884 drm_atomic_helper_commit_cleanup_done(&state->base); 6885 drm_atomic_state_put(&state->base); 6886 6887 intel_atomic_helper_free_state(i915); 6888 } 6889 6890 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state) 6891 { 6892 struct drm_i915_private *i915 = to_i915(state->base.dev); 6893 struct intel_plane *plane; 6894 struct intel_plane_state *plane_state; 6895 int i; 6896 6897 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 6898 struct drm_framebuffer *fb = plane_state->hw.fb; 6899 int cc_plane; 6900 int ret; 6901 6902 if (!fb) 6903 continue; 6904 6905 cc_plane = intel_fb_rc_ccs_cc_plane(fb); 6906 if (cc_plane < 0) 6907 continue; 6908 6909 /* 6910 * The layout of the fast clear color value expected by HW 6911 * (the DRM ABI requiring this value to be located in fb at 6912 * offset 0 of cc plane, plane #2 previous generations or 6913 * plane #1 for flat ccs): 6914 * - 4 x 4 bytes per-channel value 6915 * (in surface type specific float/int format provided by the fb user) 6916 * - 8 bytes native color value used by the display 6917 * (converted/written by GPU during a fast clear operation using the 6918 * above per-channel values) 6919 * 6920 * The commit's FB prepare hook already ensured that FB obj is pinned and the 6921 * caller made sure that the object is synced wrt. the related color clear value 6922 * GPU write on it. 6923 */ 6924 ret = i915_gem_object_read_from_page(intel_fb_obj(fb), 6925 fb->offsets[cc_plane] + 16, 6926 &plane_state->ccval, 6927 sizeof(plane_state->ccval)); 6928 /* The above could only fail if the FB obj has an unexpected backing store type. */ 6929 drm_WARN_ON(&i915->drm, ret); 6930 } 6931 } 6932 6933 static void intel_atomic_commit_tail(struct intel_atomic_state *state) 6934 { 6935 struct drm_device *dev = state->base.dev; 6936 struct drm_i915_private *dev_priv = to_i915(dev); 6937 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 6938 struct intel_crtc *crtc; 6939 struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {}; 6940 intel_wakeref_t wakeref = 0; 6941 int i; 6942 6943 intel_atomic_commit_fence_wait(state); 6944 6945 drm_atomic_helper_wait_for_dependencies(&state->base); 6946 drm_dp_mst_atomic_wait_for_dependencies(&state->base); 6947 6948 /* 6949 * During full modesets we write a lot of registers, wait 6950 * for PLLs, etc. Doing that while DC states are enabled 6951 * is not a good idea. 6952 * 6953 * During fastsets and other updates we also need to 6954 * disable DC states due to the following scenario: 6955 * 1. DC5 exit and PSR exit happen 6956 * 2. Some or all _noarm() registers are written 6957 * 3. Due to some long delay PSR is re-entered 6958 * 4. DC5 entry -> DMC saves the already written new 6959 * _noarm() registers and the old not yet written 6960 * _arm() registers 6961 * 5. DC5 exit -> DMC restores a mixture of old and 6962 * new register values and arms the update 6963 * 6. PSR exit -> hardware latches a mixture of old and 6964 * new register values -> corrupted frame, or worse 6965 * 7. New _arm() registers are finally written 6966 * 8. Hardware finally latches a complete set of new 6967 * register values, and subsequent frames will be OK again 6968 * 6969 * Also note that due to the pipe CSC hardware issues on 6970 * SKL/GLK DC states must remain off until the pipe CSC 6971 * state readout has happened. Otherwise we risk corrupting 6972 * the CSC latched register values with the readout (see 6973 * skl_read_csc() and skl_color_commit_noarm()). 6974 */ 6975 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DC_OFF); 6976 6977 intel_atomic_prepare_plane_clear_colors(state); 6978 6979 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6980 new_crtc_state, i) { 6981 if (intel_crtc_needs_modeset(new_crtc_state) || 6982 intel_crtc_needs_fastset(new_crtc_state)) 6983 intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]); 6984 } 6985 6986 intel_commit_modeset_disables(state); 6987 6988 /* FIXME: Eventually get rid of our crtc->config pointer */ 6989 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 6990 crtc->config = new_crtc_state; 6991 6992 if (state->modeset) { 6993 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base); 6994 6995 intel_set_cdclk_pre_plane_update(state); 6996 6997 intel_modeset_verify_disabled(dev_priv, state); 6998 } 6999 7000 intel_sagv_pre_plane_update(state); 7001 7002 /* Complete the events for pipes that have now been disabled */ 7003 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7004 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 7005 7006 /* Complete events for now disable pipes here. */ 7007 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) { 7008 spin_lock_irq(&dev->event_lock); 7009 drm_crtc_send_vblank_event(&crtc->base, 7010 new_crtc_state->uapi.event); 7011 spin_unlock_irq(&dev->event_lock); 7012 7013 new_crtc_state->uapi.event = NULL; 7014 } 7015 } 7016 7017 intel_encoders_update_prepare(state); 7018 7019 intel_dbuf_pre_plane_update(state); 7020 intel_mbus_dbox_update(state); 7021 7022 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7023 if (new_crtc_state->do_async_flip) 7024 intel_crtc_enable_flip_done(state, crtc); 7025 } 7026 7027 /* Now enable the clocks, plane, pipe, and connectors that we set up. */ 7028 dev_priv->display.funcs.display->commit_modeset_enables(state); 7029 7030 if (state->modeset) 7031 intel_set_cdclk_post_plane_update(state); 7032 7033 intel_wait_for_vblank_workers(state); 7034 7035 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here 7036 * already, but still need the state for the delayed optimization. To 7037 * fix this: 7038 * - wrap the optimization/post_plane_update stuff into a per-crtc work. 7039 * - schedule that vblank worker _before_ calling hw_done 7040 * - at the start of commit_tail, cancel it _synchrously 7041 * - switch over to the vblank wait helper in the core after that since 7042 * we don't need out special handling any more. 7043 */ 7044 drm_atomic_helper_wait_for_flip_done(dev, &state->base); 7045 7046 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7047 if (new_crtc_state->do_async_flip) 7048 intel_crtc_disable_flip_done(state, crtc); 7049 } 7050 7051 /* 7052 * Now that the vblank has passed, we can go ahead and program the 7053 * optimal watermarks on platforms that need two-step watermark 7054 * programming. 7055 * 7056 * TODO: Move this (and other cleanup) to an async worker eventually. 7057 */ 7058 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7059 new_crtc_state, i) { 7060 /* 7061 * Gen2 reports pipe underruns whenever all planes are disabled. 7062 * So re-enable underrun reporting after some planes get enabled. 7063 * 7064 * We do this before .optimize_watermarks() so that we have a 7065 * chance of catching underruns with the intermediate watermarks 7066 * vs. the new plane configuration. 7067 */ 7068 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state)) 7069 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 7070 7071 intel_optimize_watermarks(state, crtc); 7072 } 7073 7074 intel_dbuf_post_plane_update(state); 7075 intel_psr_post_plane_update(state); 7076 7077 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7078 intel_post_plane_update(state, crtc); 7079 7080 intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]); 7081 7082 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state); 7083 7084 /* Must be done after gamma readout due to HSW split gamma vs. IPS w/a */ 7085 hsw_ips_post_update(state, crtc); 7086 7087 /* 7088 * Activate DRRS after state readout to avoid 7089 * dp_m_n vs. dp_m2_n2 confusion on BDW+. 7090 */ 7091 intel_drrs_activate(new_crtc_state); 7092 7093 /* 7094 * DSB cleanup is done in cleanup_work aligning with framebuffer 7095 * cleanup. So copy and reset the dsb structure to sync with 7096 * commit_done and later do dsb cleanup in cleanup_work. 7097 * 7098 * FIXME get rid of this funny new->old swapping 7099 */ 7100 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb); 7101 } 7102 7103 /* Underruns don't always raise interrupts, so check manually */ 7104 intel_check_cpu_fifo_underruns(dev_priv); 7105 intel_check_pch_fifo_underruns(dev_priv); 7106 7107 if (state->modeset) 7108 intel_verify_planes(state); 7109 7110 intel_sagv_post_plane_update(state); 7111 7112 drm_atomic_helper_commit_hw_done(&state->base); 7113 7114 if (state->modeset) { 7115 /* As one of the primary mmio accessors, KMS has a high 7116 * likelihood of triggering bugs in unclaimed access. After we 7117 * finish modesetting, see if an error has been flagged, and if 7118 * so enable debugging for the next modeset - and hope we catch 7119 * the culprit. 7120 */ 7121 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); 7122 } 7123 intel_display_power_put(dev_priv, POWER_DOMAIN_DC_OFF, wakeref); 7124 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7125 7126 /* 7127 * Defer the cleanup of the old state to a separate worker to not 7128 * impede the current task (userspace for blocking modesets) that 7129 * are executed inline. For out-of-line asynchronous modesets/flips, 7130 * deferring to a new worker seems overkill, but we would place a 7131 * schedule point (cond_resched()) here anyway to keep latencies 7132 * down. 7133 */ 7134 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work); 7135 queue_work(system_highpri_wq, &state->base.commit_work); 7136 } 7137 7138 static void intel_atomic_commit_work(struct work_struct *work) 7139 { 7140 struct intel_atomic_state *state = 7141 container_of(work, struct intel_atomic_state, base.commit_work); 7142 7143 intel_atomic_commit_tail(state); 7144 } 7145 7146 static int 7147 intel_atomic_commit_ready(struct i915_sw_fence *fence, 7148 enum i915_sw_fence_notify notify) 7149 { 7150 struct intel_atomic_state *state = 7151 container_of(fence, struct intel_atomic_state, commit_ready); 7152 7153 switch (notify) { 7154 case FENCE_COMPLETE: 7155 /* we do blocking waits in the worker, nothing to do here */ 7156 break; 7157 case FENCE_FREE: 7158 { 7159 struct intel_atomic_helper *helper = 7160 &to_i915(state->base.dev)->display.atomic_helper; 7161 7162 if (llist_add(&state->freed, &helper->free_list)) 7163 schedule_work(&helper->free_work); 7164 break; 7165 } 7166 } 7167 7168 return NOTIFY_DONE; 7169 } 7170 7171 static void intel_atomic_track_fbs(struct intel_atomic_state *state) 7172 { 7173 struct intel_plane_state *old_plane_state, *new_plane_state; 7174 struct intel_plane *plane; 7175 int i; 7176 7177 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 7178 new_plane_state, i) 7179 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), 7180 to_intel_frontbuffer(new_plane_state->hw.fb), 7181 plane->frontbuffer_bit); 7182 } 7183 7184 int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state, 7185 bool nonblock) 7186 { 7187 struct intel_atomic_state *state = to_intel_atomic_state(_state); 7188 struct drm_i915_private *dev_priv = to_i915(dev); 7189 int ret = 0; 7190 7191 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 7192 7193 drm_atomic_state_get(&state->base); 7194 i915_sw_fence_init(&state->commit_ready, 7195 intel_atomic_commit_ready); 7196 7197 /* 7198 * The intel_legacy_cursor_update() fast path takes care 7199 * of avoiding the vblank waits for simple cursor 7200 * movement and flips. For cursor on/off and size changes, 7201 * we want to perform the vblank waits so that watermark 7202 * updates happen during the correct frames. Gen9+ have 7203 * double buffered watermarks and so shouldn't need this. 7204 * 7205 * Unset state->legacy_cursor_update before the call to 7206 * drm_atomic_helper_setup_commit() because otherwise 7207 * drm_atomic_helper_wait_for_flip_done() is a noop and 7208 * we get FIFO underruns because we didn't wait 7209 * for vblank. 7210 * 7211 * FIXME doing watermarks and fb cleanup from a vblank worker 7212 * (assuming we had any) would solve these problems. 7213 */ 7214 if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) { 7215 struct intel_crtc_state *new_crtc_state; 7216 struct intel_crtc *crtc; 7217 int i; 7218 7219 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7220 if (new_crtc_state->wm.need_postvbl_update || 7221 new_crtc_state->update_wm_post) 7222 state->base.legacy_cursor_update = false; 7223 } 7224 7225 ret = intel_atomic_prepare_commit(state); 7226 if (ret) { 7227 drm_dbg_atomic(&dev_priv->drm, 7228 "Preparing state failed with %i\n", ret); 7229 i915_sw_fence_commit(&state->commit_ready); 7230 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7231 return ret; 7232 } 7233 7234 ret = drm_atomic_helper_setup_commit(&state->base, nonblock); 7235 if (!ret) 7236 ret = drm_atomic_helper_swap_state(&state->base, true); 7237 if (!ret) 7238 intel_atomic_swap_global_state(state); 7239 7240 if (ret) { 7241 struct intel_crtc_state *new_crtc_state; 7242 struct intel_crtc *crtc; 7243 int i; 7244 7245 i915_sw_fence_commit(&state->commit_ready); 7246 7247 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7248 intel_color_cleanup_commit(new_crtc_state); 7249 7250 drm_atomic_helper_cleanup_planes(dev, &state->base); 7251 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7252 return ret; 7253 } 7254 intel_shared_dpll_swap_state(state); 7255 intel_atomic_track_fbs(state); 7256 7257 drm_atomic_state_get(&state->base); 7258 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work); 7259 7260 i915_sw_fence_commit(&state->commit_ready); 7261 if (nonblock && state->modeset) { 7262 queue_work(dev_priv->display.wq.modeset, &state->base.commit_work); 7263 } else if (nonblock) { 7264 queue_work(dev_priv->display.wq.flip, &state->base.commit_work); 7265 } else { 7266 if (state->modeset) 7267 flush_workqueue(dev_priv->display.wq.modeset); 7268 intel_atomic_commit_tail(state); 7269 } 7270 7271 return 0; 7272 } 7273 7274 /** 7275 * intel_plane_destroy - destroy a plane 7276 * @plane: plane to destroy 7277 * 7278 * Common destruction function for all types of planes (primary, cursor, 7279 * sprite). 7280 */ 7281 void intel_plane_destroy(struct drm_plane *plane) 7282 { 7283 drm_plane_cleanup(plane); 7284 kfree(to_intel_plane(plane)); 7285 } 7286 7287 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 7288 struct drm_file *file) 7289 { 7290 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; 7291 struct drm_crtc *drmmode_crtc; 7292 struct intel_crtc *crtc; 7293 7294 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id); 7295 if (!drmmode_crtc) 7296 return -ENOENT; 7297 7298 crtc = to_intel_crtc(drmmode_crtc); 7299 pipe_from_crtc_id->pipe = crtc->pipe; 7300 7301 return 0; 7302 } 7303 7304 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder) 7305 { 7306 struct drm_device *dev = encoder->base.dev; 7307 struct intel_encoder *source_encoder; 7308 u32 possible_clones = 0; 7309 7310 for_each_intel_encoder(dev, source_encoder) { 7311 if (encoders_cloneable(encoder, source_encoder)) 7312 possible_clones |= drm_encoder_mask(&source_encoder->base); 7313 } 7314 7315 return possible_clones; 7316 } 7317 7318 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder) 7319 { 7320 struct drm_device *dev = encoder->base.dev; 7321 struct intel_crtc *crtc; 7322 u32 possible_crtcs = 0; 7323 7324 for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask) 7325 possible_crtcs |= drm_crtc_mask(&crtc->base); 7326 7327 return possible_crtcs; 7328 } 7329 7330 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv) 7331 { 7332 if (!IS_MOBILE(dev_priv)) 7333 return false; 7334 7335 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0) 7336 return false; 7337 7338 if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE)) 7339 return false; 7340 7341 return true; 7342 } 7343 7344 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv) 7345 { 7346 if (DISPLAY_VER(dev_priv) >= 9) 7347 return false; 7348 7349 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) 7350 return false; 7351 7352 if (HAS_PCH_LPT_H(dev_priv) && 7353 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) 7354 return false; 7355 7356 /* DDI E can't be used if DDI A requires 4 lanes */ 7357 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 7358 return false; 7359 7360 if (!dev_priv->display.vbt.int_crt_support) 7361 return false; 7362 7363 return true; 7364 } 7365 7366 void intel_setup_outputs(struct drm_i915_private *dev_priv) 7367 { 7368 struct intel_encoder *encoder; 7369 bool dpd_is_edp = false; 7370 7371 intel_pps_unlock_regs_wa(dev_priv); 7372 7373 if (!HAS_DISPLAY(dev_priv)) 7374 return; 7375 7376 if (IS_METEORLAKE(dev_priv)) { 7377 intel_ddi_init(dev_priv, PORT_A); 7378 intel_ddi_init(dev_priv, PORT_B); 7379 intel_ddi_init(dev_priv, PORT_TC1); 7380 intel_ddi_init(dev_priv, PORT_TC2); 7381 intel_ddi_init(dev_priv, PORT_TC3); 7382 intel_ddi_init(dev_priv, PORT_TC4); 7383 } else if (IS_DG2(dev_priv)) { 7384 intel_ddi_init(dev_priv, PORT_A); 7385 intel_ddi_init(dev_priv, PORT_B); 7386 intel_ddi_init(dev_priv, PORT_C); 7387 intel_ddi_init(dev_priv, PORT_D_XELPD); 7388 intel_ddi_init(dev_priv, PORT_TC1); 7389 } else if (IS_ALDERLAKE_P(dev_priv)) { 7390 intel_ddi_init(dev_priv, PORT_A); 7391 intel_ddi_init(dev_priv, PORT_B); 7392 intel_ddi_init(dev_priv, PORT_TC1); 7393 intel_ddi_init(dev_priv, PORT_TC2); 7394 intel_ddi_init(dev_priv, PORT_TC3); 7395 intel_ddi_init(dev_priv, PORT_TC4); 7396 icl_dsi_init(dev_priv); 7397 } else if (IS_ALDERLAKE_S(dev_priv)) { 7398 intel_ddi_init(dev_priv, PORT_A); 7399 intel_ddi_init(dev_priv, PORT_TC1); 7400 intel_ddi_init(dev_priv, PORT_TC2); 7401 intel_ddi_init(dev_priv, PORT_TC3); 7402 intel_ddi_init(dev_priv, PORT_TC4); 7403 } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) { 7404 intel_ddi_init(dev_priv, PORT_A); 7405 intel_ddi_init(dev_priv, PORT_B); 7406 intel_ddi_init(dev_priv, PORT_TC1); 7407 intel_ddi_init(dev_priv, PORT_TC2); 7408 } else if (DISPLAY_VER(dev_priv) >= 12) { 7409 intel_ddi_init(dev_priv, PORT_A); 7410 intel_ddi_init(dev_priv, PORT_B); 7411 intel_ddi_init(dev_priv, PORT_TC1); 7412 intel_ddi_init(dev_priv, PORT_TC2); 7413 intel_ddi_init(dev_priv, PORT_TC3); 7414 intel_ddi_init(dev_priv, PORT_TC4); 7415 intel_ddi_init(dev_priv, PORT_TC5); 7416 intel_ddi_init(dev_priv, PORT_TC6); 7417 icl_dsi_init(dev_priv); 7418 } else if (IS_JSL_EHL(dev_priv)) { 7419 intel_ddi_init(dev_priv, PORT_A); 7420 intel_ddi_init(dev_priv, PORT_B); 7421 intel_ddi_init(dev_priv, PORT_C); 7422 intel_ddi_init(dev_priv, PORT_D); 7423 icl_dsi_init(dev_priv); 7424 } else if (DISPLAY_VER(dev_priv) == 11) { 7425 intel_ddi_init(dev_priv, PORT_A); 7426 intel_ddi_init(dev_priv, PORT_B); 7427 intel_ddi_init(dev_priv, PORT_C); 7428 intel_ddi_init(dev_priv, PORT_D); 7429 intel_ddi_init(dev_priv, PORT_E); 7430 intel_ddi_init(dev_priv, PORT_F); 7431 icl_dsi_init(dev_priv); 7432 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 7433 intel_ddi_init(dev_priv, PORT_A); 7434 intel_ddi_init(dev_priv, PORT_B); 7435 intel_ddi_init(dev_priv, PORT_C); 7436 vlv_dsi_init(dev_priv); 7437 } else if (DISPLAY_VER(dev_priv) >= 9) { 7438 intel_ddi_init(dev_priv, PORT_A); 7439 intel_ddi_init(dev_priv, PORT_B); 7440 intel_ddi_init(dev_priv, PORT_C); 7441 intel_ddi_init(dev_priv, PORT_D); 7442 intel_ddi_init(dev_priv, PORT_E); 7443 } else if (HAS_DDI(dev_priv)) { 7444 u32 found; 7445 7446 if (intel_ddi_crt_present(dev_priv)) 7447 intel_crt_init(dev_priv); 7448 7449 /* Haswell uses DDI functions to detect digital outputs. */ 7450 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 7451 if (found) 7452 intel_ddi_init(dev_priv, PORT_A); 7453 7454 found = intel_de_read(dev_priv, SFUSE_STRAP); 7455 if (found & SFUSE_STRAP_DDIB_DETECTED) 7456 intel_ddi_init(dev_priv, PORT_B); 7457 if (found & SFUSE_STRAP_DDIC_DETECTED) 7458 intel_ddi_init(dev_priv, PORT_C); 7459 if (found & SFUSE_STRAP_DDID_DETECTED) 7460 intel_ddi_init(dev_priv, PORT_D); 7461 if (found & SFUSE_STRAP_DDIF_DETECTED) 7462 intel_ddi_init(dev_priv, PORT_F); 7463 } else if (HAS_PCH_SPLIT(dev_priv)) { 7464 int found; 7465 7466 /* 7467 * intel_edp_init_connector() depends on this completing first, 7468 * to prevent the registration of both eDP and LVDS and the 7469 * incorrect sharing of the PPS. 7470 */ 7471 intel_lvds_init(dev_priv); 7472 intel_crt_init(dev_priv); 7473 7474 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D); 7475 7476 if (ilk_has_edp_a(dev_priv)) 7477 g4x_dp_init(dev_priv, DP_A, PORT_A); 7478 7479 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) { 7480 /* PCH SDVOB multiplex with HDMIB */ 7481 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); 7482 if (!found) 7483 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); 7484 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED)) 7485 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B); 7486 } 7487 7488 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED) 7489 g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); 7490 7491 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED) 7492 g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D); 7493 7494 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED) 7495 g4x_dp_init(dev_priv, PCH_DP_C, PORT_C); 7496 7497 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED) 7498 g4x_dp_init(dev_priv, PCH_DP_D, PORT_D); 7499 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 7500 bool has_edp, has_port; 7501 7502 if (IS_VALLEYVIEW(dev_priv) && dev_priv->display.vbt.int_crt_support) 7503 intel_crt_init(dev_priv); 7504 7505 /* 7506 * The DP_DETECTED bit is the latched state of the DDC 7507 * SDA pin at boot. However since eDP doesn't require DDC 7508 * (no way to plug in a DP->HDMI dongle) the DDC pins for 7509 * eDP ports may have been muxed to an alternate function. 7510 * Thus we can't rely on the DP_DETECTED bit alone to detect 7511 * eDP ports. Consult the VBT as well as DP_DETECTED to 7512 * detect eDP ports. 7513 * 7514 * Sadly the straps seem to be missing sometimes even for HDMI 7515 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap 7516 * and VBT for the presence of the port. Additionally we can't 7517 * trust the port type the VBT declares as we've seen at least 7518 * HDMI ports that the VBT claim are DP or eDP. 7519 */ 7520 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B); 7521 has_port = intel_bios_is_port_present(dev_priv, PORT_B); 7522 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port) 7523 has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B); 7524 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) 7525 g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); 7526 7527 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C); 7528 has_port = intel_bios_is_port_present(dev_priv, PORT_C); 7529 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port) 7530 has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C); 7531 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) 7532 g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); 7533 7534 if (IS_CHERRYVIEW(dev_priv)) { 7535 /* 7536 * eDP not supported on port D, 7537 * so no need to worry about it 7538 */ 7539 has_port = intel_bios_is_port_present(dev_priv, PORT_D); 7540 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port) 7541 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D); 7542 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port) 7543 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D); 7544 } 7545 7546 vlv_dsi_init(dev_priv); 7547 } else if (IS_PINEVIEW(dev_priv)) { 7548 intel_lvds_init(dev_priv); 7549 intel_crt_init(dev_priv); 7550 } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) { 7551 bool found = false; 7552 7553 if (IS_MOBILE(dev_priv)) 7554 intel_lvds_init(dev_priv); 7555 7556 intel_crt_init(dev_priv); 7557 7558 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 7559 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n"); 7560 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); 7561 if (!found && IS_G4X(dev_priv)) { 7562 drm_dbg_kms(&dev_priv->drm, 7563 "probing HDMI on SDVOB\n"); 7564 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); 7565 } 7566 7567 if (!found && IS_G4X(dev_priv)) 7568 g4x_dp_init(dev_priv, DP_B, PORT_B); 7569 } 7570 7571 /* Before G4X SDVOC doesn't have its own detect register */ 7572 7573 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 7574 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n"); 7575 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); 7576 } 7577 7578 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) { 7579 7580 if (IS_G4X(dev_priv)) { 7581 drm_dbg_kms(&dev_priv->drm, 7582 "probing HDMI on SDVOC\n"); 7583 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); 7584 } 7585 if (IS_G4X(dev_priv)) 7586 g4x_dp_init(dev_priv, DP_C, PORT_C); 7587 } 7588 7589 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED)) 7590 g4x_dp_init(dev_priv, DP_D, PORT_D); 7591 7592 if (SUPPORTS_TV(dev_priv)) 7593 intel_tv_init(dev_priv); 7594 } else if (DISPLAY_VER(dev_priv) == 2) { 7595 if (IS_I85X(dev_priv)) 7596 intel_lvds_init(dev_priv); 7597 7598 intel_crt_init(dev_priv); 7599 intel_dvo_init(dev_priv); 7600 } 7601 7602 for_each_intel_encoder(&dev_priv->drm, encoder) { 7603 encoder->base.possible_crtcs = 7604 intel_encoder_possible_crtcs(encoder); 7605 encoder->base.possible_clones = 7606 intel_encoder_possible_clones(encoder); 7607 } 7608 7609 intel_init_pch_refclk(dev_priv); 7610 7611 drm_helper_move_panel_connectors_to_head(&dev_priv->drm); 7612 } 7613 7614 static int max_dotclock(struct drm_i915_private *i915) 7615 { 7616 int max_dotclock = i915->max_dotclk_freq; 7617 7618 /* icl+ might use bigjoiner */ 7619 if (DISPLAY_VER(i915) >= 11) 7620 max_dotclock *= 2; 7621 7622 return max_dotclock; 7623 } 7624 7625 enum drm_mode_status intel_mode_valid(struct drm_device *dev, 7626 const struct drm_display_mode *mode) 7627 { 7628 struct drm_i915_private *dev_priv = to_i915(dev); 7629 int hdisplay_max, htotal_max; 7630 int vdisplay_max, vtotal_max; 7631 7632 /* 7633 * Can't reject DBLSCAN here because Xorg ddxen can add piles 7634 * of DBLSCAN modes to the output's mode list when they detect 7635 * the scaling mode property on the connector. And they don't 7636 * ask the kernel to validate those modes in any way until 7637 * modeset time at which point the client gets a protocol error. 7638 * So in order to not upset those clients we silently ignore the 7639 * DBLSCAN flag on such connectors. For other connectors we will 7640 * reject modes with the DBLSCAN flag in encoder->compute_config(). 7641 * And we always reject DBLSCAN modes in connector->mode_valid() 7642 * as we never want such modes on the connector's mode list. 7643 */ 7644 7645 if (mode->vscan > 1) 7646 return MODE_NO_VSCAN; 7647 7648 if (mode->flags & DRM_MODE_FLAG_HSKEW) 7649 return MODE_H_ILLEGAL; 7650 7651 if (mode->flags & (DRM_MODE_FLAG_CSYNC | 7652 DRM_MODE_FLAG_NCSYNC | 7653 DRM_MODE_FLAG_PCSYNC)) 7654 return MODE_HSYNC; 7655 7656 if (mode->flags & (DRM_MODE_FLAG_BCAST | 7657 DRM_MODE_FLAG_PIXMUX | 7658 DRM_MODE_FLAG_CLKDIV2)) 7659 return MODE_BAD; 7660 7661 /* 7662 * Reject clearly excessive dotclocks early to 7663 * avoid having to worry about huge integers later. 7664 */ 7665 if (mode->clock > max_dotclock(dev_priv)) 7666 return MODE_CLOCK_HIGH; 7667 7668 /* Transcoder timing limits */ 7669 if (DISPLAY_VER(dev_priv) >= 11) { 7670 hdisplay_max = 16384; 7671 vdisplay_max = 8192; 7672 htotal_max = 16384; 7673 vtotal_max = 8192; 7674 } else if (DISPLAY_VER(dev_priv) >= 9 || 7675 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 7676 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ 7677 vdisplay_max = 4096; 7678 htotal_max = 8192; 7679 vtotal_max = 8192; 7680 } else if (DISPLAY_VER(dev_priv) >= 3) { 7681 hdisplay_max = 4096; 7682 vdisplay_max = 4096; 7683 htotal_max = 8192; 7684 vtotal_max = 8192; 7685 } else { 7686 hdisplay_max = 2048; 7687 vdisplay_max = 2048; 7688 htotal_max = 4096; 7689 vtotal_max = 4096; 7690 } 7691 7692 if (mode->hdisplay > hdisplay_max || 7693 mode->hsync_start > htotal_max || 7694 mode->hsync_end > htotal_max || 7695 mode->htotal > htotal_max) 7696 return MODE_H_ILLEGAL; 7697 7698 if (mode->vdisplay > vdisplay_max || 7699 mode->vsync_start > vtotal_max || 7700 mode->vsync_end > vtotal_max || 7701 mode->vtotal > vtotal_max) 7702 return MODE_V_ILLEGAL; 7703 7704 if (DISPLAY_VER(dev_priv) >= 5) { 7705 if (mode->hdisplay < 64 || 7706 mode->htotal - mode->hdisplay < 32) 7707 return MODE_H_ILLEGAL; 7708 7709 if (mode->vtotal - mode->vdisplay < 5) 7710 return MODE_V_ILLEGAL; 7711 } else { 7712 if (mode->htotal - mode->hdisplay < 32) 7713 return MODE_H_ILLEGAL; 7714 7715 if (mode->vtotal - mode->vdisplay < 3) 7716 return MODE_V_ILLEGAL; 7717 } 7718 7719 /* 7720 * Cantiga+ cannot handle modes with a hsync front porch of 0. 7721 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. 7722 */ 7723 if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) && 7724 mode->hsync_start == mode->hdisplay) 7725 return MODE_H_ILLEGAL; 7726 7727 return MODE_OK; 7728 } 7729 7730 enum drm_mode_status 7731 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 7732 const struct drm_display_mode *mode, 7733 bool bigjoiner) 7734 { 7735 int plane_width_max, plane_height_max; 7736 7737 /* 7738 * intel_mode_valid() should be 7739 * sufficient on older platforms. 7740 */ 7741 if (DISPLAY_VER(dev_priv) < 9) 7742 return MODE_OK; 7743 7744 /* 7745 * Most people will probably want a fullscreen 7746 * plane so let's not advertize modes that are 7747 * too big for that. 7748 */ 7749 if (DISPLAY_VER(dev_priv) >= 11) { 7750 plane_width_max = 5120 << bigjoiner; 7751 plane_height_max = 4320; 7752 } else { 7753 plane_width_max = 5120; 7754 plane_height_max = 4096; 7755 } 7756 7757 if (mode->hdisplay > plane_width_max) 7758 return MODE_H_ILLEGAL; 7759 7760 if (mode->vdisplay > plane_height_max) 7761 return MODE_V_ILLEGAL; 7762 7763 return MODE_OK; 7764 } 7765 7766 static const struct intel_display_funcs skl_display_funcs = { 7767 .get_pipe_config = hsw_get_pipe_config, 7768 .crtc_enable = hsw_crtc_enable, 7769 .crtc_disable = hsw_crtc_disable, 7770 .commit_modeset_enables = skl_commit_modeset_enables, 7771 .get_initial_plane_config = skl_get_initial_plane_config, 7772 }; 7773 7774 static const struct intel_display_funcs ddi_display_funcs = { 7775 .get_pipe_config = hsw_get_pipe_config, 7776 .crtc_enable = hsw_crtc_enable, 7777 .crtc_disable = hsw_crtc_disable, 7778 .commit_modeset_enables = intel_commit_modeset_enables, 7779 .get_initial_plane_config = i9xx_get_initial_plane_config, 7780 }; 7781 7782 static const struct intel_display_funcs pch_split_display_funcs = { 7783 .get_pipe_config = ilk_get_pipe_config, 7784 .crtc_enable = ilk_crtc_enable, 7785 .crtc_disable = ilk_crtc_disable, 7786 .commit_modeset_enables = intel_commit_modeset_enables, 7787 .get_initial_plane_config = i9xx_get_initial_plane_config, 7788 }; 7789 7790 static const struct intel_display_funcs vlv_display_funcs = { 7791 .get_pipe_config = i9xx_get_pipe_config, 7792 .crtc_enable = valleyview_crtc_enable, 7793 .crtc_disable = i9xx_crtc_disable, 7794 .commit_modeset_enables = intel_commit_modeset_enables, 7795 .get_initial_plane_config = i9xx_get_initial_plane_config, 7796 }; 7797 7798 static const struct intel_display_funcs i9xx_display_funcs = { 7799 .get_pipe_config = i9xx_get_pipe_config, 7800 .crtc_enable = i9xx_crtc_enable, 7801 .crtc_disable = i9xx_crtc_disable, 7802 .commit_modeset_enables = intel_commit_modeset_enables, 7803 .get_initial_plane_config = i9xx_get_initial_plane_config, 7804 }; 7805 7806 /** 7807 * intel_init_display_hooks - initialize the display modesetting hooks 7808 * @dev_priv: device private 7809 */ 7810 void intel_init_display_hooks(struct drm_i915_private *dev_priv) 7811 { 7812 if (DISPLAY_VER(dev_priv) >= 9) { 7813 dev_priv->display.funcs.display = &skl_display_funcs; 7814 } else if (HAS_DDI(dev_priv)) { 7815 dev_priv->display.funcs.display = &ddi_display_funcs; 7816 } else if (HAS_PCH_SPLIT(dev_priv)) { 7817 dev_priv->display.funcs.display = &pch_split_display_funcs; 7818 } else if (IS_CHERRYVIEW(dev_priv) || 7819 IS_VALLEYVIEW(dev_priv)) { 7820 dev_priv->display.funcs.display = &vlv_display_funcs; 7821 } else { 7822 dev_priv->display.funcs.display = &i9xx_display_funcs; 7823 } 7824 } 7825 7826 int intel_initial_commit(struct drm_device *dev) 7827 { 7828 struct drm_atomic_state *state = NULL; 7829 struct drm_modeset_acquire_ctx ctx; 7830 struct intel_crtc *crtc; 7831 int ret = 0; 7832 7833 state = drm_atomic_state_alloc(dev); 7834 if (!state) 7835 return -ENOMEM; 7836 7837 drm_modeset_acquire_init(&ctx, 0); 7838 7839 state->acquire_ctx = &ctx; 7840 to_intel_atomic_state(state)->internal = true; 7841 7842 retry: 7843 for_each_intel_crtc(dev, crtc) { 7844 struct intel_crtc_state *crtc_state = 7845 intel_atomic_get_crtc_state(state, crtc); 7846 7847 if (IS_ERR(crtc_state)) { 7848 ret = PTR_ERR(crtc_state); 7849 goto out; 7850 } 7851 7852 if (crtc_state->hw.active) { 7853 struct intel_encoder *encoder; 7854 7855 ret = drm_atomic_add_affected_planes(state, &crtc->base); 7856 if (ret) 7857 goto out; 7858 7859 /* 7860 * FIXME hack to force a LUT update to avoid the 7861 * plane update forcing the pipe gamma on without 7862 * having a proper LUT loaded. Remove once we 7863 * have readout for pipe gamma enable. 7864 */ 7865 crtc_state->uapi.color_mgmt_changed = true; 7866 7867 for_each_intel_encoder_mask(dev, encoder, 7868 crtc_state->uapi.encoder_mask) { 7869 if (encoder->initial_fastset_check && 7870 !encoder->initial_fastset_check(encoder, crtc_state)) { 7871 ret = drm_atomic_add_affected_connectors(state, 7872 &crtc->base); 7873 if (ret) 7874 goto out; 7875 } 7876 } 7877 } 7878 } 7879 7880 ret = drm_atomic_commit(state); 7881 7882 out: 7883 if (ret == -EDEADLK) { 7884 drm_atomic_state_clear(state); 7885 drm_modeset_backoff(&ctx); 7886 goto retry; 7887 } 7888 7889 drm_atomic_state_put(state); 7890 7891 drm_modeset_drop_locks(&ctx); 7892 drm_modeset_acquire_fini(&ctx); 7893 7894 return ret; 7895 } 7896 7897 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 7898 { 7899 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 7900 enum transcoder cpu_transcoder = (enum transcoder)pipe; 7901 /* 640x480@60Hz, ~25175 kHz */ 7902 struct dpll clock = { 7903 .m1 = 18, 7904 .m2 = 7, 7905 .p1 = 13, 7906 .p2 = 4, 7907 .n = 2, 7908 }; 7909 u32 dpll, fp; 7910 int i; 7911 7912 drm_WARN_ON(&dev_priv->drm, 7913 i9xx_calc_dpll_params(48000, &clock) != 25154); 7914 7915 drm_dbg_kms(&dev_priv->drm, 7916 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n", 7917 pipe_name(pipe), clock.vco, clock.dot); 7918 7919 fp = i9xx_dpll_compute_fp(&clock); 7920 dpll = DPLL_DVO_2X_MODE | 7921 DPLL_VGA_MODE_DIS | 7922 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | 7923 PLL_P2_DIVIDE_BY_4 | 7924 PLL_REF_INPUT_DREFCLK | 7925 DPLL_VCO_ENABLE; 7926 7927 intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder), 7928 HACTIVE(640 - 1) | HTOTAL(800 - 1)); 7929 intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder), 7930 HBLANK_START(640 - 1) | HBLANK_END(800 - 1)); 7931 intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder), 7932 HSYNC_START(656 - 1) | HSYNC_END(752 - 1)); 7933 intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder), 7934 VACTIVE(480 - 1) | VTOTAL(525 - 1)); 7935 intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), 7936 VBLANK_START(480 - 1) | VBLANK_END(525 - 1)); 7937 intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder), 7938 VSYNC_START(490 - 1) | VSYNC_END(492 - 1)); 7939 intel_de_write(dev_priv, PIPESRC(pipe), 7940 PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1)); 7941 7942 intel_de_write(dev_priv, FP0(pipe), fp); 7943 intel_de_write(dev_priv, FP1(pipe), fp); 7944 7945 /* 7946 * Apparently we need to have VGA mode enabled prior to changing 7947 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 7948 * dividers, even though the register value does change. 7949 */ 7950 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); 7951 intel_de_write(dev_priv, DPLL(pipe), dpll); 7952 7953 /* Wait for the clocks to stabilize. */ 7954 intel_de_posting_read(dev_priv, DPLL(pipe)); 7955 udelay(150); 7956 7957 /* The pixel multiplier can only be updated once the 7958 * DPLL is enabled and the clocks are stable. 7959 * 7960 * So write it again. 7961 */ 7962 intel_de_write(dev_priv, DPLL(pipe), dpll); 7963 7964 /* We do this three times for luck */ 7965 for (i = 0; i < 3 ; i++) { 7966 intel_de_write(dev_priv, DPLL(pipe), dpll); 7967 intel_de_posting_read(dev_priv, DPLL(pipe)); 7968 udelay(150); /* wait for warmup */ 7969 } 7970 7971 intel_de_write(dev_priv, TRANSCONF(pipe), TRANSCONF_ENABLE); 7972 intel_de_posting_read(dev_priv, TRANSCONF(pipe)); 7973 7974 intel_wait_for_pipe_scanline_moving(crtc); 7975 } 7976 7977 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 7978 { 7979 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 7980 7981 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n", 7982 pipe_name(pipe)); 7983 7984 drm_WARN_ON(&dev_priv->drm, 7985 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE); 7986 drm_WARN_ON(&dev_priv->drm, 7987 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE); 7988 drm_WARN_ON(&dev_priv->drm, 7989 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE); 7990 drm_WARN_ON(&dev_priv->drm, 7991 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK); 7992 drm_WARN_ON(&dev_priv->drm, 7993 intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK); 7994 7995 intel_de_write(dev_priv, TRANSCONF(pipe), 0); 7996 intel_de_posting_read(dev_priv, TRANSCONF(pipe)); 7997 7998 intel_wait_for_pipe_scanline_stopped(crtc); 7999 8000 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); 8001 intel_de_posting_read(dev_priv, DPLL(pipe)); 8002 } 8003 8004 void intel_hpd_poll_fini(struct drm_i915_private *i915) 8005 { 8006 struct intel_connector *connector; 8007 struct drm_connector_list_iter conn_iter; 8008 8009 /* Kill all the work that may have been queued by hpd. */ 8010 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 8011 for_each_intel_connector_iter(connector, &conn_iter) { 8012 if (connector->modeset_retry_work.func) 8013 cancel_work_sync(&connector->modeset_retry_work); 8014 if (connector->hdcp.shim) { 8015 cancel_delayed_work_sync(&connector->hdcp.check_work); 8016 cancel_work_sync(&connector->hdcp.prop_work); 8017 } 8018 } 8019 drm_connector_list_iter_end(&conn_iter); 8020 } 8021 8022 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915) 8023 { 8024 return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915); 8025 } 8026