1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <acpi/video.h> 28 #include <linux/i2c.h> 29 #include <linux/input.h> 30 #include <linux/intel-iommu.h> 31 #include <linux/kernel.h> 32 #include <linux/module.h> 33 #include <linux/dma-resv.h> 34 #include <linux/slab.h> 35 #include <linux/vga_switcheroo.h> 36 37 #include <drm/drm_atomic.h> 38 #include <drm/drm_atomic_helper.h> 39 #include <drm/drm_atomic_uapi.h> 40 #include <drm/drm_damage_helper.h> 41 #include <drm/dp/drm_dp_helper.h> 42 #include <drm/drm_edid.h> 43 #include <drm/drm_fourcc.h> 44 #include <drm/drm_plane_helper.h> 45 #include <drm/drm_privacy_screen_consumer.h> 46 #include <drm/drm_probe_helper.h> 47 #include <drm/drm_rect.h> 48 49 #include "display/intel_audio.h" 50 #include "display/intel_crt.h" 51 #include "display/intel_ddi.h" 52 #include "display/intel_display_debugfs.h" 53 #include "display/intel_dp.h" 54 #include "display/intel_dp_mst.h" 55 #include "display/intel_dpll.h" 56 #include "display/intel_dpll_mgr.h" 57 #include "display/intel_drrs.h" 58 #include "display/intel_dsi.h" 59 #include "display/intel_dvo.h" 60 #include "display/intel_fb.h" 61 #include "display/intel_gmbus.h" 62 #include "display/intel_hdmi.h" 63 #include "display/intel_lvds.h" 64 #include "display/intel_sdvo.h" 65 #include "display/intel_snps_phy.h" 66 #include "display/intel_tv.h" 67 #include "display/intel_vdsc.h" 68 #include "display/intel_vrr.h" 69 70 #include "gem/i915_gem_lmem.h" 71 #include "gem/i915_gem_object.h" 72 73 #include "gt/gen8_ppgtt.h" 74 75 #include "g4x_dp.h" 76 #include "g4x_hdmi.h" 77 #include "i915_drv.h" 78 #include "icl_dsi.h" 79 #include "intel_acpi.h" 80 #include "intel_atomic.h" 81 #include "intel_atomic_plane.h" 82 #include "intel_bw.h" 83 #include "intel_cdclk.h" 84 #include "intel_color.h" 85 #include "intel_crtc.h" 86 #include "intel_de.h" 87 #include "intel_display_types.h" 88 #include "intel_dmc.h" 89 #include "intel_dp_link_training.h" 90 #include "intel_dpt.h" 91 #include "intel_fbc.h" 92 #include "intel_fbdev.h" 93 #include "intel_fdi.h" 94 #include "intel_fifo_underrun.h" 95 #include "intel_frontbuffer.h" 96 #include "intel_hdcp.h" 97 #include "intel_hotplug.h" 98 #include "intel_overlay.h" 99 #include "intel_panel.h" 100 #include "intel_pch_display.h" 101 #include "intel_pch_refclk.h" 102 #include "intel_pcode.h" 103 #include "intel_pipe_crc.h" 104 #include "intel_plane_initial.h" 105 #include "intel_pm.h" 106 #include "intel_pps.h" 107 #include "intel_psr.h" 108 #include "intel_quirks.h" 109 #include "intel_sprite.h" 110 #include "intel_tc.h" 111 #include "intel_vga.h" 112 #include "i9xx_plane.h" 113 #include "skl_scaler.h" 114 #include "skl_universal_plane.h" 115 #include "vlv_dsi_pll.h" 116 #include "vlv_sideband.h" 117 #include "vlv_dsi.h" 118 119 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state); 120 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state); 121 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state); 122 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state); 123 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state); 124 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state); 125 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state); 126 static void intel_modeset_setup_hw_state(struct drm_device *dev, 127 struct drm_modeset_acquire_ctx *ctx); 128 129 /** 130 * intel_update_watermarks - update FIFO watermark values based on current modes 131 * @dev_priv: i915 device 132 * 133 * Calculate watermark values for the various WM regs based on current mode 134 * and plane configuration. 135 * 136 * There are several cases to deal with here: 137 * - normal (i.e. non-self-refresh) 138 * - self-refresh (SR) mode 139 * - lines are large relative to FIFO size (buffer can hold up to 2) 140 * - lines are small relative to FIFO size (buffer can hold more than 2 141 * lines), so need to account for TLB latency 142 * 143 * The normal calculation is: 144 * watermark = dotclock * bytes per pixel * latency 145 * where latency is platform & configuration dependent (we assume pessimal 146 * values here). 147 * 148 * The SR calculation is: 149 * watermark = (trunc(latency/line time)+1) * surface width * 150 * bytes per pixel 151 * where 152 * line time = htotal / dotclock 153 * surface width = hdisplay for normal plane and 64 for cursor 154 * and latency is assumed to be high, as above. 155 * 156 * The final value programmed to the register should always be rounded up, 157 * and include an extra 2 entries to account for clock crossings. 158 * 159 * We don't use the sprite, so we can ignore that. And on Crestline we have 160 * to set the non-SR watermarks to 8. 161 */ 162 static void intel_update_watermarks(struct drm_i915_private *dev_priv) 163 { 164 if (dev_priv->wm_disp->update_wm) 165 dev_priv->wm_disp->update_wm(dev_priv); 166 } 167 168 static int intel_compute_pipe_wm(struct intel_atomic_state *state, 169 struct intel_crtc *crtc) 170 { 171 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 172 if (dev_priv->wm_disp->compute_pipe_wm) 173 return dev_priv->wm_disp->compute_pipe_wm(state, crtc); 174 return 0; 175 } 176 177 static int intel_compute_intermediate_wm(struct intel_atomic_state *state, 178 struct intel_crtc *crtc) 179 { 180 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 181 if (!dev_priv->wm_disp->compute_intermediate_wm) 182 return 0; 183 if (drm_WARN_ON(&dev_priv->drm, 184 !dev_priv->wm_disp->compute_pipe_wm)) 185 return 0; 186 return dev_priv->wm_disp->compute_intermediate_wm(state, crtc); 187 } 188 189 static bool intel_initial_watermarks(struct intel_atomic_state *state, 190 struct intel_crtc *crtc) 191 { 192 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 193 if (dev_priv->wm_disp->initial_watermarks) { 194 dev_priv->wm_disp->initial_watermarks(state, crtc); 195 return true; 196 } 197 return false; 198 } 199 200 static void intel_atomic_update_watermarks(struct intel_atomic_state *state, 201 struct intel_crtc *crtc) 202 { 203 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 204 if (dev_priv->wm_disp->atomic_update_watermarks) 205 dev_priv->wm_disp->atomic_update_watermarks(state, crtc); 206 } 207 208 static void intel_optimize_watermarks(struct intel_atomic_state *state, 209 struct intel_crtc *crtc) 210 { 211 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 212 if (dev_priv->wm_disp->optimize_watermarks) 213 dev_priv->wm_disp->optimize_watermarks(state, crtc); 214 } 215 216 static int intel_compute_global_watermarks(struct intel_atomic_state *state) 217 { 218 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 219 if (dev_priv->wm_disp->compute_global_watermarks) 220 return dev_priv->wm_disp->compute_global_watermarks(state); 221 return 0; 222 } 223 224 /* returns HPLL frequency in kHz */ 225 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) 226 { 227 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; 228 229 /* Obtain SKU information */ 230 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & 231 CCK_FUSE_HPLL_FREQ_MASK; 232 233 return vco_freq[hpll_freq] * 1000; 234 } 235 236 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 237 const char *name, u32 reg, int ref_freq) 238 { 239 u32 val; 240 int divider; 241 242 val = vlv_cck_read(dev_priv, reg); 243 divider = val & CCK_FREQUENCY_VALUES; 244 245 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != 246 (divider << CCK_FREQUENCY_STATUS_SHIFT), 247 "%s change in progress\n", name); 248 249 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); 250 } 251 252 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 253 const char *name, u32 reg) 254 { 255 int hpll; 256 257 vlv_cck_get(dev_priv); 258 259 if (dev_priv->hpll_freq == 0) 260 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); 261 262 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); 263 264 vlv_cck_put(dev_priv); 265 266 return hpll; 267 } 268 269 static void intel_update_czclk(struct drm_i915_private *dev_priv) 270 { 271 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) 272 return; 273 274 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", 275 CCK_CZ_CLOCK_CONTROL); 276 277 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", 278 dev_priv->czclk_freq); 279 } 280 281 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state) 282 { 283 return (crtc_state->active_planes & 284 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0; 285 } 286 287 /* WA Display #0827: Gen9:all */ 288 static void 289 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) 290 { 291 if (enable) 292 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 293 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS); 294 else 295 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 296 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS)); 297 } 298 299 /* Wa_2006604312:icl,ehl */ 300 static void 301 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 302 bool enable) 303 { 304 if (enable) 305 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 306 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS); 307 else 308 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 309 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS); 310 } 311 312 /* Wa_1604331009:icl,jsl,ehl */ 313 static void 314 icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 315 bool enable) 316 { 317 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), CURSOR_GATING_DIS, 318 enable ? CURSOR_GATING_DIS : 0); 319 } 320 321 static bool 322 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state) 323 { 324 return crtc_state->master_transcoder != INVALID_TRANSCODER; 325 } 326 327 static bool 328 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state) 329 { 330 return crtc_state->sync_mode_slaves_mask != 0; 331 } 332 333 bool 334 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state) 335 { 336 return is_trans_port_sync_master(crtc_state) || 337 is_trans_port_sync_slave(crtc_state); 338 } 339 340 static struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state) 341 { 342 if (crtc_state->bigjoiner_slave) 343 return crtc_state->bigjoiner_linked_crtc; 344 else 345 return to_intel_crtc(crtc_state->uapi.crtc); 346 } 347 348 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv, 349 enum pipe pipe) 350 { 351 i915_reg_t reg = PIPEDSL(pipe); 352 u32 line1, line2; 353 354 line1 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK; 355 msleep(5); 356 line2 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK; 357 358 return line1 != line2; 359 } 360 361 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state) 362 { 363 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 364 enum pipe pipe = crtc->pipe; 365 366 /* Wait for the display line to settle/start moving */ 367 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100)) 368 drm_err(&dev_priv->drm, 369 "pipe %c scanline %s wait timed out\n", 370 pipe_name(pipe), onoff(state)); 371 } 372 373 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc) 374 { 375 wait_for_pipe_scanline_moving(crtc, false); 376 } 377 378 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc) 379 { 380 wait_for_pipe_scanline_moving(crtc, true); 381 } 382 383 static void 384 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) 385 { 386 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 387 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 388 389 if (DISPLAY_VER(dev_priv) >= 4) { 390 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 391 392 /* Wait for the Pipe State to go off */ 393 if (intel_de_wait_for_clear(dev_priv, PIPECONF(cpu_transcoder), 394 PIPECONF_STATE_ENABLE, 100)) 395 drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n"); 396 } else { 397 intel_wait_for_pipe_scanline_stopped(crtc); 398 } 399 } 400 401 void assert_transcoder(struct drm_i915_private *dev_priv, 402 enum transcoder cpu_transcoder, bool state) 403 { 404 bool cur_state; 405 enum intel_display_power_domain power_domain; 406 intel_wakeref_t wakeref; 407 408 /* we keep both pipes enabled on 830 */ 409 if (IS_I830(dev_priv)) 410 state = true; 411 412 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 413 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 414 if (wakeref) { 415 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); 416 cur_state = !!(val & PIPECONF_ENABLE); 417 418 intel_display_power_put(dev_priv, power_domain, wakeref); 419 } else { 420 cur_state = false; 421 } 422 423 I915_STATE_WARN(cur_state != state, 424 "transcoder %s assertion failure (expected %s, current %s)\n", 425 transcoder_name(cpu_transcoder), 426 onoff(state), onoff(cur_state)); 427 } 428 429 static void assert_plane(struct intel_plane *plane, bool state) 430 { 431 enum pipe pipe; 432 bool cur_state; 433 434 cur_state = plane->get_hw_state(plane, &pipe); 435 436 I915_STATE_WARN(cur_state != state, 437 "%s assertion failure (expected %s, current %s)\n", 438 plane->base.name, onoff(state), onoff(cur_state)); 439 } 440 441 #define assert_plane_enabled(p) assert_plane(p, true) 442 #define assert_plane_disabled(p) assert_plane(p, false) 443 444 static void assert_planes_disabled(struct intel_crtc *crtc) 445 { 446 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 447 struct intel_plane *plane; 448 449 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) 450 assert_plane_disabled(plane); 451 } 452 453 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 454 struct intel_digital_port *dig_port, 455 unsigned int expected_mask) 456 { 457 u32 port_mask; 458 i915_reg_t dpll_reg; 459 460 switch (dig_port->base.port) { 461 case PORT_B: 462 port_mask = DPLL_PORTB_READY_MASK; 463 dpll_reg = DPLL(0); 464 break; 465 case PORT_C: 466 port_mask = DPLL_PORTC_READY_MASK; 467 dpll_reg = DPLL(0); 468 expected_mask <<= 4; 469 break; 470 case PORT_D: 471 port_mask = DPLL_PORTD_READY_MASK; 472 dpll_reg = DPIO_PHY_STATUS; 473 break; 474 default: 475 BUG(); 476 } 477 478 if (intel_de_wait_for_register(dev_priv, dpll_reg, 479 port_mask, expected_mask, 1000)) 480 drm_WARN(&dev_priv->drm, 1, 481 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", 482 dig_port->base.base.base.id, dig_port->base.base.name, 483 intel_de_read(dev_priv, dpll_reg) & port_mask, 484 expected_mask); 485 } 486 487 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc) 488 { 489 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 490 491 if (HAS_PCH_LPT(dev_priv)) 492 return PIPE_A; 493 else 494 return crtc->pipe; 495 } 496 497 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) 498 { 499 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 500 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 501 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 502 enum pipe pipe = crtc->pipe; 503 i915_reg_t reg; 504 u32 val; 505 506 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe)); 507 508 assert_planes_disabled(crtc); 509 510 /* 511 * A pipe without a PLL won't actually be able to drive bits from 512 * a plane. On ILK+ the pipe PLLs are integrated, so we don't 513 * need the check. 514 */ 515 if (HAS_GMCH(dev_priv)) { 516 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI)) 517 assert_dsi_pll_enabled(dev_priv); 518 else 519 assert_pll_enabled(dev_priv, pipe); 520 } else { 521 if (new_crtc_state->has_pch_encoder) { 522 /* if driving the PCH, we need FDI enabled */ 523 assert_fdi_rx_pll_enabled(dev_priv, 524 intel_crtc_pch_transcoder(crtc)); 525 assert_fdi_tx_pll_enabled(dev_priv, 526 (enum pipe) cpu_transcoder); 527 } 528 /* FIXME: assert CPU port conditions for SNB+ */ 529 } 530 531 /* Wa_22012358565:adl-p */ 532 if (DISPLAY_VER(dev_priv) == 13) 533 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe), 534 0, PIPE_ARB_USE_PROG_SLOTS); 535 536 reg = PIPECONF(cpu_transcoder); 537 val = intel_de_read(dev_priv, reg); 538 if (val & PIPECONF_ENABLE) { 539 /* we keep both pipes enabled on 830 */ 540 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv)); 541 return; 542 } 543 544 intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE); 545 intel_de_posting_read(dev_priv, reg); 546 547 /* 548 * Until the pipe starts PIPEDSL reads will return a stale value, 549 * which causes an apparent vblank timestamp jump when PIPEDSL 550 * resets to its proper value. That also messes up the frame count 551 * when it's derived from the timestamps. So let's wait for the 552 * pipe to start properly before we call drm_crtc_vblank_on() 553 */ 554 if (intel_crtc_max_vblank_count(new_crtc_state) == 0) 555 intel_wait_for_pipe_scanline_moving(crtc); 556 } 557 558 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) 559 { 560 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 561 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 562 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 563 enum pipe pipe = crtc->pipe; 564 i915_reg_t reg; 565 u32 val; 566 567 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe)); 568 569 /* 570 * Make sure planes won't keep trying to pump pixels to us, 571 * or we might hang the display. 572 */ 573 assert_planes_disabled(crtc); 574 575 reg = PIPECONF(cpu_transcoder); 576 val = intel_de_read(dev_priv, reg); 577 if ((val & PIPECONF_ENABLE) == 0) 578 return; 579 580 /* 581 * Double wide has implications for planes 582 * so best keep it disabled when not needed. 583 */ 584 if (old_crtc_state->double_wide) 585 val &= ~PIPECONF_DOUBLE_WIDE; 586 587 /* Don't disable pipe or pipe PLLs if needed */ 588 if (!IS_I830(dev_priv)) 589 val &= ~PIPECONF_ENABLE; 590 591 if (DISPLAY_VER(dev_priv) >= 12) 592 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 593 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 594 595 intel_de_write(dev_priv, reg, val); 596 if ((val & PIPECONF_ENABLE) == 0) 597 intel_wait_for_pipe_off(old_crtc_state); 598 } 599 600 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) 601 { 602 unsigned int size = 0; 603 int i; 604 605 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) 606 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width; 607 608 return size; 609 } 610 611 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info) 612 { 613 unsigned int size = 0; 614 int i; 615 616 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) { 617 unsigned int plane_size; 618 619 if (rem_info->plane[i].linear) 620 plane_size = rem_info->plane[i].size; 621 else 622 plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height; 623 624 if (plane_size == 0) 625 continue; 626 627 if (rem_info->plane_alignment) 628 size = ALIGN(size, rem_info->plane_alignment); 629 630 size += plane_size; 631 } 632 633 return size; 634 } 635 636 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) 637 { 638 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 639 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 640 641 return DISPLAY_VER(dev_priv) < 4 || 642 (plane->fbc && 643 plane_state->view.gtt.type == I915_GGTT_VIEW_NORMAL); 644 } 645 646 /* 647 * Convert the x/y offsets into a linear offset. 648 * Only valid with 0/180 degree rotation, which is fine since linear 649 * offset is only used with linear buffers on pre-hsw and tiled buffers 650 * with gen2/3, and 90/270 degree rotations isn't supported on any of them. 651 */ 652 u32 intel_fb_xy_to_linear(int x, int y, 653 const struct intel_plane_state *state, 654 int color_plane) 655 { 656 const struct drm_framebuffer *fb = state->hw.fb; 657 unsigned int cpp = fb->format->cpp[color_plane]; 658 unsigned int pitch = state->view.color_plane[color_plane].mapping_stride; 659 660 return y * pitch + x * cpp; 661 } 662 663 /* 664 * Add the x/y offsets derived from fb->offsets[] to the user 665 * specified plane src x/y offsets. The resulting x/y offsets 666 * specify the start of scanout from the beginning of the gtt mapping. 667 */ 668 void intel_add_fb_offsets(int *x, int *y, 669 const struct intel_plane_state *state, 670 int color_plane) 671 672 { 673 *x += state->view.color_plane[color_plane].x; 674 *y += state->view.color_plane[color_plane].y; 675 } 676 677 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 678 u32 pixel_format, u64 modifier) 679 { 680 struct intel_crtc *crtc; 681 struct intel_plane *plane; 682 683 if (!HAS_DISPLAY(dev_priv)) 684 return 0; 685 686 /* 687 * We assume the primary plane for pipe A has 688 * the highest stride limits of them all, 689 * if in case pipe A is disabled, use the first pipe from pipe_mask. 690 */ 691 crtc = intel_first_crtc(dev_priv); 692 if (!crtc) 693 return 0; 694 695 plane = to_intel_plane(crtc->base.primary); 696 697 return plane->max_stride(plane, pixel_format, modifier, 698 DRM_MODE_ROTATE_0); 699 } 700 701 static void 702 intel_set_plane_visible(struct intel_crtc_state *crtc_state, 703 struct intel_plane_state *plane_state, 704 bool visible) 705 { 706 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 707 708 plane_state->uapi.visible = visible; 709 710 if (visible) 711 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base); 712 else 713 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base); 714 } 715 716 static void fixup_plane_bitmasks(struct intel_crtc_state *crtc_state) 717 { 718 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 719 struct drm_plane *plane; 720 721 /* 722 * Active_planes aliases if multiple "primary" or cursor planes 723 * have been used on the same (or wrong) pipe. plane_mask uses 724 * unique ids, hence we can use that to reconstruct active_planes. 725 */ 726 crtc_state->enabled_planes = 0; 727 crtc_state->active_planes = 0; 728 729 drm_for_each_plane_mask(plane, &dev_priv->drm, 730 crtc_state->uapi.plane_mask) { 731 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id); 732 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id); 733 } 734 } 735 736 void intel_plane_disable_noatomic(struct intel_crtc *crtc, 737 struct intel_plane *plane) 738 { 739 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 740 struct intel_crtc_state *crtc_state = 741 to_intel_crtc_state(crtc->base.state); 742 struct intel_plane_state *plane_state = 743 to_intel_plane_state(plane->base.state); 744 745 drm_dbg_kms(&dev_priv->drm, 746 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n", 747 plane->base.base.id, plane->base.name, 748 crtc->base.base.id, crtc->base.name); 749 750 intel_set_plane_visible(crtc_state, plane_state, false); 751 fixup_plane_bitmasks(crtc_state); 752 crtc_state->data_rate[plane->id] = 0; 753 crtc_state->min_cdclk[plane->id] = 0; 754 755 if (plane->id == PLANE_PRIMARY) 756 hsw_disable_ips(crtc_state); 757 758 /* 759 * Vblank time updates from the shadow to live plane control register 760 * are blocked if the memory self-refresh mode is active at that 761 * moment. So to make sure the plane gets truly disabled, disable 762 * first the self-refresh mode. The self-refresh enable bit in turn 763 * will be checked/applied by the HW only at the next frame start 764 * event which is after the vblank start event, so we need to have a 765 * wait-for-vblank between disabling the plane and the pipe. 766 */ 767 if (HAS_GMCH(dev_priv) && 768 intel_set_memory_cxsr(dev_priv, false)) 769 intel_crtc_wait_for_next_vblank(crtc); 770 771 /* 772 * Gen2 reports pipe underruns whenever all planes are disabled. 773 * So disable underrun reporting before all the planes get disabled. 774 */ 775 if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes) 776 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); 777 778 intel_plane_disable_arm(plane, crtc_state); 779 intel_crtc_wait_for_next_vblank(crtc); 780 } 781 782 unsigned int 783 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state) 784 { 785 int x = 0, y = 0; 786 787 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, 788 plane_state->view.color_plane[0].offset, 0); 789 790 return y; 791 } 792 793 static int 794 __intel_display_resume(struct drm_device *dev, 795 struct drm_atomic_state *state, 796 struct drm_modeset_acquire_ctx *ctx) 797 { 798 struct drm_crtc_state *crtc_state; 799 struct drm_crtc *crtc; 800 int i, ret; 801 802 intel_modeset_setup_hw_state(dev, ctx); 803 intel_vga_redisable(to_i915(dev)); 804 805 if (!state) 806 return 0; 807 808 /* 809 * We've duplicated the state, pointers to the old state are invalid. 810 * 811 * Don't attempt to use the old state until we commit the duplicated state. 812 */ 813 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 814 /* 815 * Force recalculation even if we restore 816 * current state. With fast modeset this may not result 817 * in a modeset when the state is compatible. 818 */ 819 crtc_state->mode_changed = true; 820 } 821 822 /* ignore any reset values/BIOS leftovers in the WM registers */ 823 if (!HAS_GMCH(to_i915(dev))) 824 to_intel_atomic_state(state)->skip_intermediate_wm = true; 825 826 ret = drm_atomic_helper_commit_duplicated_state(state, ctx); 827 828 drm_WARN_ON(dev, ret == -EDEADLK); 829 return ret; 830 } 831 832 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) 833 { 834 return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display && 835 intel_has_gpu_reset(to_gt(dev_priv))); 836 } 837 838 void intel_display_prepare_reset(struct drm_i915_private *dev_priv) 839 { 840 struct drm_device *dev = &dev_priv->drm; 841 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; 842 struct drm_atomic_state *state; 843 int ret; 844 845 if (!HAS_DISPLAY(dev_priv)) 846 return; 847 848 /* reset doesn't touch the display */ 849 if (!dev_priv->params.force_reset_modeset_test && 850 !gpu_reset_clobbers_display(dev_priv)) 851 return; 852 853 /* We have a modeset vs reset deadlock, defensively unbreak it. */ 854 set_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags); 855 smp_mb__after_atomic(); 856 wake_up_bit(&to_gt(dev_priv)->reset.flags, I915_RESET_MODESET); 857 858 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) { 859 drm_dbg_kms(&dev_priv->drm, 860 "Modeset potentially stuck, unbreaking through wedging\n"); 861 intel_gt_set_wedged(to_gt(dev_priv)); 862 } 863 864 /* 865 * Need mode_config.mutex so that we don't 866 * trample ongoing ->detect() and whatnot. 867 */ 868 mutex_lock(&dev->mode_config.mutex); 869 drm_modeset_acquire_init(ctx, 0); 870 while (1) { 871 ret = drm_modeset_lock_all_ctx(dev, ctx); 872 if (ret != -EDEADLK) 873 break; 874 875 drm_modeset_backoff(ctx); 876 } 877 /* 878 * Disabling the crtcs gracefully seems nicer. Also the 879 * g33 docs say we should at least disable all the planes. 880 */ 881 state = drm_atomic_helper_duplicate_state(dev, ctx); 882 if (IS_ERR(state)) { 883 ret = PTR_ERR(state); 884 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n", 885 ret); 886 return; 887 } 888 889 ret = drm_atomic_helper_disable_all(dev, ctx); 890 if (ret) { 891 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", 892 ret); 893 drm_atomic_state_put(state); 894 return; 895 } 896 897 dev_priv->modeset_restore_state = state; 898 state->acquire_ctx = ctx; 899 } 900 901 void intel_display_finish_reset(struct drm_i915_private *dev_priv) 902 { 903 struct drm_device *dev = &dev_priv->drm; 904 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; 905 struct drm_atomic_state *state; 906 int ret; 907 908 if (!HAS_DISPLAY(dev_priv)) 909 return; 910 911 /* reset doesn't touch the display */ 912 if (!test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags)) 913 return; 914 915 state = fetch_and_zero(&dev_priv->modeset_restore_state); 916 if (!state) 917 goto unlock; 918 919 /* reset doesn't touch the display */ 920 if (!gpu_reset_clobbers_display(dev_priv)) { 921 /* for testing only restore the display */ 922 ret = __intel_display_resume(dev, state, ctx); 923 if (ret) 924 drm_err(&dev_priv->drm, 925 "Restoring old state failed with %i\n", ret); 926 } else { 927 /* 928 * The display has been reset as well, 929 * so need a full re-initialization. 930 */ 931 intel_pps_unlock_regs_wa(dev_priv); 932 intel_modeset_init_hw(dev_priv); 933 intel_init_clock_gating(dev_priv); 934 intel_hpd_init(dev_priv); 935 936 ret = __intel_display_resume(dev, state, ctx); 937 if (ret) 938 drm_err(&dev_priv->drm, 939 "Restoring old state failed with %i\n", ret); 940 941 intel_hpd_poll_disable(dev_priv); 942 } 943 944 drm_atomic_state_put(state); 945 unlock: 946 drm_modeset_drop_locks(ctx); 947 drm_modeset_acquire_fini(ctx); 948 mutex_unlock(&dev->mode_config.mutex); 949 950 clear_bit_unlock(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags); 951 } 952 953 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) 954 { 955 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 956 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 957 enum pipe pipe = crtc->pipe; 958 u32 tmp; 959 960 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe)); 961 962 /* 963 * Display WA #1153: icl 964 * enable hardware to bypass the alpha math 965 * and rounding for per-pixel values 00 and 0xff 966 */ 967 tmp |= PER_PIXEL_ALPHA_BYPASS_EN; 968 /* 969 * Display WA # 1605353570: icl 970 * Set the pixel rounding bit to 1 for allowing 971 * passthrough of Frame buffer pixels unmodified 972 * across pipe 973 */ 974 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU; 975 976 /* 977 * Underrun recovery must always be disabled on display 13+. 978 * DG2 chicken bit meaning is inverted compared to other platforms. 979 */ 980 if (IS_DG2(dev_priv)) 981 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2; 982 else if (DISPLAY_VER(dev_priv) >= 13) 983 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP; 984 985 /* Wa_14010547955:dg2 */ 986 if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER)) 987 tmp |= DG2_RENDER_CCSTAG_4_3_EN; 988 989 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp); 990 } 991 992 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) 993 { 994 struct drm_crtc *crtc; 995 bool cleanup_done; 996 997 drm_for_each_crtc(crtc, &dev_priv->drm) { 998 struct drm_crtc_commit *commit; 999 spin_lock(&crtc->commit_lock); 1000 commit = list_first_entry_or_null(&crtc->commit_list, 1001 struct drm_crtc_commit, commit_entry); 1002 cleanup_done = commit ? 1003 try_wait_for_completion(&commit->cleanup_done) : true; 1004 spin_unlock(&crtc->commit_lock); 1005 1006 if (cleanup_done) 1007 continue; 1008 1009 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc)); 1010 1011 return true; 1012 } 1013 1014 return false; 1015 } 1016 1017 /* 1018 * Finds the encoder associated with the given CRTC. This can only be 1019 * used when we know that the CRTC isn't feeding multiple encoders! 1020 */ 1021 struct intel_encoder * 1022 intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 1023 const struct intel_crtc_state *crtc_state) 1024 { 1025 const struct drm_connector_state *connector_state; 1026 const struct drm_connector *connector; 1027 struct intel_encoder *encoder = NULL; 1028 struct intel_crtc *master_crtc; 1029 int num_encoders = 0; 1030 int i; 1031 1032 master_crtc = intel_master_crtc(crtc_state); 1033 1034 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 1035 if (connector_state->crtc != &master_crtc->base) 1036 continue; 1037 1038 encoder = to_intel_encoder(connector_state->best_encoder); 1039 num_encoders++; 1040 } 1041 1042 drm_WARN(encoder->base.dev, num_encoders != 1, 1043 "%d encoders for pipe %c\n", 1044 num_encoders, pipe_name(master_crtc->pipe)); 1045 1046 return encoder; 1047 } 1048 1049 static void cpt_verify_modeset(struct drm_i915_private *dev_priv, 1050 enum pipe pipe) 1051 { 1052 i915_reg_t dslreg = PIPEDSL(pipe); 1053 u32 temp; 1054 1055 temp = intel_de_read(dev_priv, dslreg); 1056 udelay(500); 1057 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) { 1058 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) 1059 drm_err(&dev_priv->drm, 1060 "mode set failed: pipe %c stuck\n", 1061 pipe_name(pipe)); 1062 } 1063 } 1064 1065 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state) 1066 { 1067 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1068 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1069 const struct drm_rect *dst = &crtc_state->pch_pfit.dst; 1070 enum pipe pipe = crtc->pipe; 1071 int width = drm_rect_width(dst); 1072 int height = drm_rect_height(dst); 1073 int x = dst->x1; 1074 int y = dst->y1; 1075 1076 if (!crtc_state->pch_pfit.enabled) 1077 return; 1078 1079 /* Force use of hard-coded filter coefficients 1080 * as some pre-programmed values are broken, 1081 * e.g. x201. 1082 */ 1083 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) 1084 intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE | 1085 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe)); 1086 else 1087 intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE | 1088 PF_FILTER_MED_3x3); 1089 intel_de_write(dev_priv, PF_WIN_POS(pipe), x << 16 | y); 1090 intel_de_write(dev_priv, PF_WIN_SZ(pipe), width << 16 | height); 1091 } 1092 1093 void hsw_enable_ips(const struct intel_crtc_state *crtc_state) 1094 { 1095 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1096 struct drm_device *dev = crtc->base.dev; 1097 struct drm_i915_private *dev_priv = to_i915(dev); 1098 1099 if (!crtc_state->ips_enabled) 1100 return; 1101 1102 /* 1103 * We can only enable IPS after we enable a plane and wait for a vblank 1104 * This function is called from post_plane_update, which is run after 1105 * a vblank wait. 1106 */ 1107 drm_WARN_ON(dev, !(crtc_state->active_planes & ~BIT(PLANE_CURSOR))); 1108 1109 if (IS_BROADWELL(dev_priv)) { 1110 drm_WARN_ON(dev, snb_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 1111 IPS_ENABLE | IPS_PCODE_CONTROL)); 1112 /* Quoting Art Runyan: "its not safe to expect any particular 1113 * value in IPS_CTL bit 31 after enabling IPS through the 1114 * mailbox." Moreover, the mailbox may return a bogus state, 1115 * so we need to just enable it and continue on. 1116 */ 1117 } else { 1118 intel_de_write(dev_priv, IPS_CTL, IPS_ENABLE); 1119 /* The bit only becomes 1 in the next vblank, so this wait here 1120 * is essentially intel_wait_for_vblank. If we don't have this 1121 * and don't wait for vblanks until the end of crtc_enable, then 1122 * the HW state readout code will complain that the expected 1123 * IPS_CTL value is not the one we read. */ 1124 if (intel_de_wait_for_set(dev_priv, IPS_CTL, IPS_ENABLE, 50)) 1125 drm_err(&dev_priv->drm, 1126 "Timed out waiting for IPS enable\n"); 1127 } 1128 } 1129 1130 void hsw_disable_ips(const struct intel_crtc_state *crtc_state) 1131 { 1132 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1133 struct drm_device *dev = crtc->base.dev; 1134 struct drm_i915_private *dev_priv = to_i915(dev); 1135 1136 if (!crtc_state->ips_enabled) 1137 return; 1138 1139 if (IS_BROADWELL(dev_priv)) { 1140 drm_WARN_ON(dev, 1141 snb_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); 1142 /* 1143 * Wait for PCODE to finish disabling IPS. The BSpec specified 1144 * 42ms timeout value leads to occasional timeouts so use 100ms 1145 * instead. 1146 */ 1147 if (intel_de_wait_for_clear(dev_priv, IPS_CTL, IPS_ENABLE, 100)) 1148 drm_err(&dev_priv->drm, 1149 "Timed out waiting for IPS disable\n"); 1150 } else { 1151 intel_de_write(dev_priv, IPS_CTL, 0); 1152 intel_de_posting_read(dev_priv, IPS_CTL); 1153 } 1154 1155 /* We need to wait for a vblank before we can disable the plane. */ 1156 intel_crtc_wait_for_next_vblank(crtc); 1157 } 1158 1159 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc) 1160 { 1161 if (crtc->overlay) 1162 (void) intel_overlay_switch_off(crtc->overlay); 1163 1164 /* Let userspace switch the overlay on again. In most cases userspace 1165 * has to recompute where to put it anyway. 1166 */ 1167 } 1168 1169 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state, 1170 const struct intel_crtc_state *new_crtc_state) 1171 { 1172 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 1173 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1174 1175 if (!old_crtc_state->ips_enabled) 1176 return false; 1177 1178 if (intel_crtc_needs_modeset(new_crtc_state)) 1179 return true; 1180 1181 /* 1182 * Workaround : Do not read or write the pipe palette/gamma data while 1183 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. 1184 * 1185 * Disable IPS before we program the LUT. 1186 */ 1187 if (IS_HASWELL(dev_priv) && 1188 (new_crtc_state->uapi.color_mgmt_changed || 1189 new_crtc_state->update_pipe) && 1190 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) 1191 return true; 1192 1193 return !new_crtc_state->ips_enabled; 1194 } 1195 1196 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state, 1197 const struct intel_crtc_state *new_crtc_state) 1198 { 1199 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 1200 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1201 1202 if (!new_crtc_state->ips_enabled) 1203 return false; 1204 1205 if (intel_crtc_needs_modeset(new_crtc_state)) 1206 return true; 1207 1208 /* 1209 * Workaround : Do not read or write the pipe palette/gamma data while 1210 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. 1211 * 1212 * Re-enable IPS after the LUT has been programmed. 1213 */ 1214 if (IS_HASWELL(dev_priv) && 1215 (new_crtc_state->uapi.color_mgmt_changed || 1216 new_crtc_state->update_pipe) && 1217 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) 1218 return true; 1219 1220 /* 1221 * We can't read out IPS on broadwell, assume the worst and 1222 * forcibly enable IPS on the first fastset. 1223 */ 1224 if (new_crtc_state->update_pipe && old_crtc_state->inherited) 1225 return true; 1226 1227 return !old_crtc_state->ips_enabled; 1228 } 1229 1230 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state) 1231 { 1232 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1233 1234 if (!crtc_state->nv12_planes) 1235 return false; 1236 1237 /* WA Display #0827: Gen9:all */ 1238 if (DISPLAY_VER(dev_priv) == 9) 1239 return true; 1240 1241 return false; 1242 } 1243 1244 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state) 1245 { 1246 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1247 1248 /* Wa_2006604312:icl,ehl */ 1249 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11) 1250 return true; 1251 1252 return false; 1253 } 1254 1255 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state) 1256 { 1257 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1258 1259 /* Wa_1604331009:icl,jsl,ehl */ 1260 if (is_hdr_mode(crtc_state) && 1261 crtc_state->active_planes & BIT(PLANE_CURSOR) && 1262 DISPLAY_VER(dev_priv) == 11) 1263 return true; 1264 1265 return false; 1266 } 1267 1268 static void intel_async_flip_vtd_wa(struct drm_i915_private *i915, 1269 enum pipe pipe, bool enable) 1270 { 1271 if (DISPLAY_VER(i915) == 9) { 1272 /* 1273 * "Plane N strech max must be programmed to 11b (x1) 1274 * when Async flips are enabled on that plane." 1275 */ 1276 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 1277 SKL_PLANE1_STRETCH_MAX_MASK, 1278 enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8); 1279 } else { 1280 /* Also needed on HSW/BDW albeit undocumented */ 1281 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 1282 HSW_PRI_STRETCH_MAX_MASK, 1283 enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8); 1284 } 1285 } 1286 1287 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state) 1288 { 1289 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1290 1291 return crtc_state->uapi.async_flip && intel_vtd_active(i915) && 1292 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915)); 1293 } 1294 1295 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state, 1296 const struct intel_crtc_state *new_crtc_state) 1297 { 1298 return (!old_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)) && 1299 new_crtc_state->active_planes; 1300 } 1301 1302 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state, 1303 const struct intel_crtc_state *new_crtc_state) 1304 { 1305 return old_crtc_state->active_planes && 1306 (!new_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)); 1307 } 1308 1309 static void intel_post_plane_update(struct intel_atomic_state *state, 1310 struct intel_crtc *crtc) 1311 { 1312 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1313 const struct intel_crtc_state *old_crtc_state = 1314 intel_atomic_get_old_crtc_state(state, crtc); 1315 const struct intel_crtc_state *new_crtc_state = 1316 intel_atomic_get_new_crtc_state(state, crtc); 1317 enum pipe pipe = crtc->pipe; 1318 1319 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); 1320 1321 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) 1322 intel_update_watermarks(dev_priv); 1323 1324 if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state)) 1325 hsw_enable_ips(new_crtc_state); 1326 1327 intel_fbc_post_update(state, crtc); 1328 intel_drrs_page_flip(state, crtc); 1329 1330 if (needs_async_flip_vtd_wa(old_crtc_state) && 1331 !needs_async_flip_vtd_wa(new_crtc_state)) 1332 intel_async_flip_vtd_wa(dev_priv, pipe, false); 1333 1334 if (needs_nv12_wa(old_crtc_state) && 1335 !needs_nv12_wa(new_crtc_state)) 1336 skl_wa_827(dev_priv, pipe, false); 1337 1338 if (needs_scalerclk_wa(old_crtc_state) && 1339 !needs_scalerclk_wa(new_crtc_state)) 1340 icl_wa_scalerclkgating(dev_priv, pipe, false); 1341 1342 if (needs_cursorclk_wa(old_crtc_state) && 1343 !needs_cursorclk_wa(new_crtc_state)) 1344 icl_wa_cursorclkgating(dev_priv, pipe, false); 1345 1346 } 1347 1348 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state, 1349 struct intel_crtc *crtc) 1350 { 1351 const struct intel_crtc_state *crtc_state = 1352 intel_atomic_get_new_crtc_state(state, crtc); 1353 u8 update_planes = crtc_state->update_planes; 1354 const struct intel_plane_state *plane_state; 1355 struct intel_plane *plane; 1356 int i; 1357 1358 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1359 if (plane->enable_flip_done && 1360 plane->pipe == crtc->pipe && 1361 update_planes & BIT(plane->id) && 1362 plane_state->do_async_flip) 1363 plane->enable_flip_done(plane); 1364 } 1365 } 1366 1367 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state, 1368 struct intel_crtc *crtc) 1369 { 1370 const struct intel_crtc_state *crtc_state = 1371 intel_atomic_get_new_crtc_state(state, crtc); 1372 u8 update_planes = crtc_state->update_planes; 1373 const struct intel_plane_state *plane_state; 1374 struct intel_plane *plane; 1375 int i; 1376 1377 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1378 if (plane->disable_flip_done && 1379 plane->pipe == crtc->pipe && 1380 update_planes & BIT(plane->id) && 1381 plane_state->do_async_flip) 1382 plane->disable_flip_done(plane); 1383 } 1384 } 1385 1386 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state, 1387 struct intel_crtc *crtc) 1388 { 1389 const struct intel_crtc_state *old_crtc_state = 1390 intel_atomic_get_old_crtc_state(state, crtc); 1391 const struct intel_crtc_state *new_crtc_state = 1392 intel_atomic_get_new_crtc_state(state, crtc); 1393 u8 update_planes = new_crtc_state->update_planes; 1394 const struct intel_plane_state *old_plane_state; 1395 struct intel_plane *plane; 1396 bool need_vbl_wait = false; 1397 int i; 1398 1399 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1400 if (plane->need_async_flip_disable_wa && 1401 plane->pipe == crtc->pipe && 1402 update_planes & BIT(plane->id)) { 1403 /* 1404 * Apart from the async flip bit we want to 1405 * preserve the old state for the plane. 1406 */ 1407 plane->async_flip(plane, old_crtc_state, 1408 old_plane_state, false); 1409 need_vbl_wait = true; 1410 } 1411 } 1412 1413 if (need_vbl_wait) 1414 intel_crtc_wait_for_next_vblank(crtc); 1415 } 1416 1417 static void intel_pre_plane_update(struct intel_atomic_state *state, 1418 struct intel_crtc *crtc) 1419 { 1420 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1421 const struct intel_crtc_state *old_crtc_state = 1422 intel_atomic_get_old_crtc_state(state, crtc); 1423 const struct intel_crtc_state *new_crtc_state = 1424 intel_atomic_get_new_crtc_state(state, crtc); 1425 enum pipe pipe = crtc->pipe; 1426 1427 intel_psr_pre_plane_update(state, crtc); 1428 1429 if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state)) 1430 hsw_disable_ips(old_crtc_state); 1431 1432 if (intel_fbc_pre_update(state, crtc)) 1433 intel_crtc_wait_for_next_vblank(crtc); 1434 1435 if (!needs_async_flip_vtd_wa(old_crtc_state) && 1436 needs_async_flip_vtd_wa(new_crtc_state)) 1437 intel_async_flip_vtd_wa(dev_priv, pipe, true); 1438 1439 /* Display WA 827 */ 1440 if (!needs_nv12_wa(old_crtc_state) && 1441 needs_nv12_wa(new_crtc_state)) 1442 skl_wa_827(dev_priv, pipe, true); 1443 1444 /* Wa_2006604312:icl,ehl */ 1445 if (!needs_scalerclk_wa(old_crtc_state) && 1446 needs_scalerclk_wa(new_crtc_state)) 1447 icl_wa_scalerclkgating(dev_priv, pipe, true); 1448 1449 /* Wa_1604331009:icl,jsl,ehl */ 1450 if (!needs_cursorclk_wa(old_crtc_state) && 1451 needs_cursorclk_wa(new_crtc_state)) 1452 icl_wa_cursorclkgating(dev_priv, pipe, true); 1453 1454 /* 1455 * Vblank time updates from the shadow to live plane control register 1456 * are blocked if the memory self-refresh mode is active at that 1457 * moment. So to make sure the plane gets truly disabled, disable 1458 * first the self-refresh mode. The self-refresh enable bit in turn 1459 * will be checked/applied by the HW only at the next frame start 1460 * event which is after the vblank start event, so we need to have a 1461 * wait-for-vblank between disabling the plane and the pipe. 1462 */ 1463 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active && 1464 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) 1465 intel_crtc_wait_for_next_vblank(crtc); 1466 1467 /* 1468 * IVB workaround: must disable low power watermarks for at least 1469 * one frame before enabling scaling. LP watermarks can be re-enabled 1470 * when scaling is disabled. 1471 * 1472 * WaCxSRDisabledForSpriteScaling:ivb 1473 */ 1474 if (old_crtc_state->hw.active && 1475 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv)) 1476 intel_crtc_wait_for_next_vblank(crtc); 1477 1478 /* 1479 * If we're doing a modeset we don't need to do any 1480 * pre-vblank watermark programming here. 1481 */ 1482 if (!intel_crtc_needs_modeset(new_crtc_state)) { 1483 /* 1484 * For platforms that support atomic watermarks, program the 1485 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these 1486 * will be the intermediate values that are safe for both pre- and 1487 * post- vblank; when vblank happens, the 'active' values will be set 1488 * to the final 'target' values and we'll do this again to get the 1489 * optimal watermarks. For gen9+ platforms, the values we program here 1490 * will be the final target values which will get automatically latched 1491 * at vblank time; no further programming will be necessary. 1492 * 1493 * If a platform hasn't been transitioned to atomic watermarks yet, 1494 * we'll continue to update watermarks the old way, if flags tell 1495 * us to. 1496 */ 1497 if (!intel_initial_watermarks(state, crtc)) 1498 if (new_crtc_state->update_wm_pre) 1499 intel_update_watermarks(dev_priv); 1500 } 1501 1502 /* 1503 * Gen2 reports pipe underruns whenever all planes are disabled. 1504 * So disable underrun reporting before all the planes get disabled. 1505 * 1506 * We do this after .initial_watermarks() so that we have a 1507 * chance of catching underruns with the intermediate watermarks 1508 * vs. the old plane configuration. 1509 */ 1510 if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state)) 1511 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1512 1513 /* 1514 * WA for platforms where async address update enable bit 1515 * is double buffered and only latched at start of vblank. 1516 */ 1517 if (old_crtc_state->uapi.async_flip && !new_crtc_state->uapi.async_flip) 1518 intel_crtc_async_flip_disable_wa(state, crtc); 1519 } 1520 1521 static void intel_crtc_disable_planes(struct intel_atomic_state *state, 1522 struct intel_crtc *crtc) 1523 { 1524 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1525 const struct intel_crtc_state *new_crtc_state = 1526 intel_atomic_get_new_crtc_state(state, crtc); 1527 unsigned int update_mask = new_crtc_state->update_planes; 1528 const struct intel_plane_state *old_plane_state; 1529 struct intel_plane *plane; 1530 unsigned fb_bits = 0; 1531 int i; 1532 1533 intel_crtc_dpms_overlay_disable(crtc); 1534 1535 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1536 if (crtc->pipe != plane->pipe || 1537 !(update_mask & BIT(plane->id))) 1538 continue; 1539 1540 intel_plane_disable_arm(plane, new_crtc_state); 1541 1542 if (old_plane_state->uapi.visible) 1543 fb_bits |= plane->frontbuffer_bit; 1544 } 1545 1546 intel_frontbuffer_flip(dev_priv, fb_bits); 1547 } 1548 1549 /* 1550 * intel_connector_primary_encoder - get the primary encoder for a connector 1551 * @connector: connector for which to return the encoder 1552 * 1553 * Returns the primary encoder for a connector. There is a 1:1 mapping from 1554 * all connectors to their encoder, except for DP-MST connectors which have 1555 * both a virtual and a primary encoder. These DP-MST primary encoders can be 1556 * pointed to by as many DP-MST connectors as there are pipes. 1557 */ 1558 static struct intel_encoder * 1559 intel_connector_primary_encoder(struct intel_connector *connector) 1560 { 1561 struct intel_encoder *encoder; 1562 1563 if (connector->mst_port) 1564 return &dp_to_dig_port(connector->mst_port)->base; 1565 1566 encoder = intel_attached_encoder(connector); 1567 drm_WARN_ON(connector->base.dev, !encoder); 1568 1569 return encoder; 1570 } 1571 1572 static void intel_encoders_update_prepare(struct intel_atomic_state *state) 1573 { 1574 struct drm_i915_private *i915 = to_i915(state->base.dev); 1575 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 1576 struct intel_crtc *crtc; 1577 struct drm_connector_state *new_conn_state; 1578 struct drm_connector *connector; 1579 int i; 1580 1581 /* 1582 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits. 1583 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook. 1584 */ 1585 if (i915->dpll.mgr) { 1586 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1587 if (intel_crtc_needs_modeset(new_crtc_state)) 1588 continue; 1589 1590 new_crtc_state->shared_dpll = old_crtc_state->shared_dpll; 1591 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state; 1592 } 1593 } 1594 1595 if (!state->modeset) 1596 return; 1597 1598 for_each_new_connector_in_state(&state->base, connector, new_conn_state, 1599 i) { 1600 struct intel_connector *intel_connector; 1601 struct intel_encoder *encoder; 1602 struct intel_crtc *crtc; 1603 1604 if (!intel_connector_needs_modeset(state, connector)) 1605 continue; 1606 1607 intel_connector = to_intel_connector(connector); 1608 encoder = intel_connector_primary_encoder(intel_connector); 1609 if (!encoder->update_prepare) 1610 continue; 1611 1612 crtc = new_conn_state->crtc ? 1613 to_intel_crtc(new_conn_state->crtc) : NULL; 1614 encoder->update_prepare(state, encoder, crtc); 1615 } 1616 } 1617 1618 static void intel_encoders_update_complete(struct intel_atomic_state *state) 1619 { 1620 struct drm_connector_state *new_conn_state; 1621 struct drm_connector *connector; 1622 int i; 1623 1624 if (!state->modeset) 1625 return; 1626 1627 for_each_new_connector_in_state(&state->base, connector, new_conn_state, 1628 i) { 1629 struct intel_connector *intel_connector; 1630 struct intel_encoder *encoder; 1631 struct intel_crtc *crtc; 1632 1633 if (!intel_connector_needs_modeset(state, connector)) 1634 continue; 1635 1636 intel_connector = to_intel_connector(connector); 1637 encoder = intel_connector_primary_encoder(intel_connector); 1638 if (!encoder->update_complete) 1639 continue; 1640 1641 crtc = new_conn_state->crtc ? 1642 to_intel_crtc(new_conn_state->crtc) : NULL; 1643 encoder->update_complete(state, encoder, crtc); 1644 } 1645 } 1646 1647 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state, 1648 struct intel_crtc *crtc) 1649 { 1650 const struct intel_crtc_state *crtc_state = 1651 intel_atomic_get_new_crtc_state(state, crtc); 1652 const struct drm_connector_state *conn_state; 1653 struct drm_connector *conn; 1654 int i; 1655 1656 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1657 struct intel_encoder *encoder = 1658 to_intel_encoder(conn_state->best_encoder); 1659 1660 if (conn_state->crtc != &crtc->base) 1661 continue; 1662 1663 if (encoder->pre_pll_enable) 1664 encoder->pre_pll_enable(state, encoder, 1665 crtc_state, conn_state); 1666 } 1667 } 1668 1669 static void intel_encoders_pre_enable(struct intel_atomic_state *state, 1670 struct intel_crtc *crtc) 1671 { 1672 const struct intel_crtc_state *crtc_state = 1673 intel_atomic_get_new_crtc_state(state, crtc); 1674 const struct drm_connector_state *conn_state; 1675 struct drm_connector *conn; 1676 int i; 1677 1678 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1679 struct intel_encoder *encoder = 1680 to_intel_encoder(conn_state->best_encoder); 1681 1682 if (conn_state->crtc != &crtc->base) 1683 continue; 1684 1685 if (encoder->pre_enable) 1686 encoder->pre_enable(state, encoder, 1687 crtc_state, conn_state); 1688 } 1689 } 1690 1691 static void intel_encoders_enable(struct intel_atomic_state *state, 1692 struct intel_crtc *crtc) 1693 { 1694 const struct intel_crtc_state *crtc_state = 1695 intel_atomic_get_new_crtc_state(state, crtc); 1696 const struct drm_connector_state *conn_state; 1697 struct drm_connector *conn; 1698 int i; 1699 1700 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1701 struct intel_encoder *encoder = 1702 to_intel_encoder(conn_state->best_encoder); 1703 1704 if (conn_state->crtc != &crtc->base) 1705 continue; 1706 1707 if (encoder->enable) 1708 encoder->enable(state, encoder, 1709 crtc_state, conn_state); 1710 intel_opregion_notify_encoder(encoder, true); 1711 } 1712 } 1713 1714 static void intel_encoders_disable(struct intel_atomic_state *state, 1715 struct intel_crtc *crtc) 1716 { 1717 const struct intel_crtc_state *old_crtc_state = 1718 intel_atomic_get_old_crtc_state(state, crtc); 1719 const struct drm_connector_state *old_conn_state; 1720 struct drm_connector *conn; 1721 int i; 1722 1723 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1724 struct intel_encoder *encoder = 1725 to_intel_encoder(old_conn_state->best_encoder); 1726 1727 if (old_conn_state->crtc != &crtc->base) 1728 continue; 1729 1730 intel_opregion_notify_encoder(encoder, false); 1731 if (encoder->disable) 1732 encoder->disable(state, encoder, 1733 old_crtc_state, old_conn_state); 1734 } 1735 } 1736 1737 static void intel_encoders_post_disable(struct intel_atomic_state *state, 1738 struct intel_crtc *crtc) 1739 { 1740 const struct intel_crtc_state *old_crtc_state = 1741 intel_atomic_get_old_crtc_state(state, crtc); 1742 const struct drm_connector_state *old_conn_state; 1743 struct drm_connector *conn; 1744 int i; 1745 1746 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1747 struct intel_encoder *encoder = 1748 to_intel_encoder(old_conn_state->best_encoder); 1749 1750 if (old_conn_state->crtc != &crtc->base) 1751 continue; 1752 1753 if (encoder->post_disable) 1754 encoder->post_disable(state, encoder, 1755 old_crtc_state, old_conn_state); 1756 } 1757 } 1758 1759 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state, 1760 struct intel_crtc *crtc) 1761 { 1762 const struct intel_crtc_state *old_crtc_state = 1763 intel_atomic_get_old_crtc_state(state, crtc); 1764 const struct drm_connector_state *old_conn_state; 1765 struct drm_connector *conn; 1766 int i; 1767 1768 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1769 struct intel_encoder *encoder = 1770 to_intel_encoder(old_conn_state->best_encoder); 1771 1772 if (old_conn_state->crtc != &crtc->base) 1773 continue; 1774 1775 if (encoder->post_pll_disable) 1776 encoder->post_pll_disable(state, encoder, 1777 old_crtc_state, old_conn_state); 1778 } 1779 } 1780 1781 static void intel_encoders_update_pipe(struct intel_atomic_state *state, 1782 struct intel_crtc *crtc) 1783 { 1784 const struct intel_crtc_state *crtc_state = 1785 intel_atomic_get_new_crtc_state(state, crtc); 1786 const struct drm_connector_state *conn_state; 1787 struct drm_connector *conn; 1788 int i; 1789 1790 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1791 struct intel_encoder *encoder = 1792 to_intel_encoder(conn_state->best_encoder); 1793 1794 if (conn_state->crtc != &crtc->base) 1795 continue; 1796 1797 if (encoder->update_pipe) 1798 encoder->update_pipe(state, encoder, 1799 crtc_state, conn_state); 1800 } 1801 } 1802 1803 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state) 1804 { 1805 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1806 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 1807 1808 plane->disable_arm(plane, crtc_state); 1809 } 1810 1811 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1812 { 1813 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1814 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1815 1816 if (crtc_state->has_pch_encoder) { 1817 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1818 &crtc_state->fdi_m_n); 1819 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1820 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1821 &crtc_state->dp_m_n); 1822 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1823 &crtc_state->dp_m2_n2); 1824 } 1825 1826 intel_set_transcoder_timings(crtc_state); 1827 1828 ilk_set_pipeconf(crtc_state); 1829 } 1830 1831 static void ilk_crtc_enable(struct intel_atomic_state *state, 1832 struct intel_crtc *crtc) 1833 { 1834 const struct intel_crtc_state *new_crtc_state = 1835 intel_atomic_get_new_crtc_state(state, crtc); 1836 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1837 enum pipe pipe = crtc->pipe; 1838 1839 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1840 return; 1841 1842 /* 1843 * Sometimes spurious CPU pipe underruns happen during FDI 1844 * training, at least with VGA+HDMI cloning. Suppress them. 1845 * 1846 * On ILK we get an occasional spurious CPU pipe underruns 1847 * between eDP port A enable and vdd enable. Also PCH port 1848 * enable seems to result in the occasional CPU pipe underrun. 1849 * 1850 * Spurious PCH underruns also occur during PCH enabling. 1851 */ 1852 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1853 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 1854 1855 ilk_configure_cpu_transcoder(new_crtc_state); 1856 1857 intel_set_pipe_src_size(new_crtc_state); 1858 1859 crtc->active = true; 1860 1861 intel_encoders_pre_enable(state, crtc); 1862 1863 if (new_crtc_state->has_pch_encoder) { 1864 ilk_pch_pre_enable(state, crtc); 1865 } else { 1866 assert_fdi_tx_disabled(dev_priv, pipe); 1867 assert_fdi_rx_disabled(dev_priv, pipe); 1868 } 1869 1870 ilk_pfit_enable(new_crtc_state); 1871 1872 /* 1873 * On ILK+ LUT must be loaded before the pipe is running but with 1874 * clocks enabled 1875 */ 1876 intel_color_load_luts(new_crtc_state); 1877 intel_color_commit(new_crtc_state); 1878 /* update DSPCNTR to configure gamma for pipe bottom color */ 1879 intel_disable_primary_plane(new_crtc_state); 1880 1881 intel_initial_watermarks(state, crtc); 1882 intel_enable_transcoder(new_crtc_state); 1883 1884 if (new_crtc_state->has_pch_encoder) 1885 ilk_pch_enable(state, crtc); 1886 1887 intel_crtc_vblank_on(new_crtc_state); 1888 1889 intel_encoders_enable(state, crtc); 1890 1891 if (HAS_PCH_CPT(dev_priv)) 1892 cpt_verify_modeset(dev_priv, pipe); 1893 1894 /* 1895 * Must wait for vblank to avoid spurious PCH FIFO underruns. 1896 * And a second vblank wait is needed at least on ILK with 1897 * some interlaced HDMI modes. Let's do the double wait always 1898 * in case there are more corner cases we don't know about. 1899 */ 1900 if (new_crtc_state->has_pch_encoder) { 1901 intel_crtc_wait_for_next_vblank(crtc); 1902 intel_crtc_wait_for_next_vblank(crtc); 1903 } 1904 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1905 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 1906 } 1907 1908 /* IPS only exists on ULT machines and is tied to pipe A. */ 1909 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) 1910 { 1911 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A; 1912 } 1913 1914 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, 1915 enum pipe pipe, bool apply) 1916 { 1917 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)); 1918 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS; 1919 1920 if (apply) 1921 val |= mask; 1922 else 1923 val &= ~mask; 1924 1925 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val); 1926 } 1927 1928 static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool joined_mbus) 1929 { 1930 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1931 enum pipe pipe = crtc->pipe; 1932 u32 val; 1933 1934 /* Wa_22010947358:adl-p */ 1935 if (IS_ALDERLAKE_P(dev_priv)) 1936 val = joined_mbus ? MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4); 1937 else 1938 val = MBUS_DBOX_A_CREDIT(2); 1939 1940 if (DISPLAY_VER(dev_priv) >= 12) { 1941 val |= MBUS_DBOX_BW_CREDIT(2); 1942 val |= MBUS_DBOX_B_CREDIT(12); 1943 } else { 1944 val |= MBUS_DBOX_BW_CREDIT(1); 1945 val |= MBUS_DBOX_B_CREDIT(8); 1946 } 1947 1948 intel_de_write(dev_priv, PIPE_MBUS_DBOX_CTL(pipe), val); 1949 } 1950 1951 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state) 1952 { 1953 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1954 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1955 1956 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe), 1957 HSW_LINETIME(crtc_state->linetime) | 1958 HSW_IPS_LINETIME(crtc_state->ips_linetime)); 1959 } 1960 1961 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) 1962 { 1963 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1964 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1965 i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder); 1966 u32 val; 1967 1968 val = intel_de_read(dev_priv, reg); 1969 val &= ~HSW_FRAME_START_DELAY_MASK; 1970 val |= HSW_FRAME_START_DELAY(dev_priv->framestart_delay - 1); 1971 intel_de_write(dev_priv, reg, val); 1972 } 1973 1974 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state, 1975 const struct intel_crtc_state *crtc_state) 1976 { 1977 struct intel_crtc_state *master_crtc_state; 1978 struct intel_crtc *master_crtc; 1979 struct drm_connector_state *conn_state; 1980 struct drm_connector *conn; 1981 struct intel_encoder *encoder = NULL; 1982 int i; 1983 1984 master_crtc = intel_master_crtc(crtc_state); 1985 master_crtc_state = intel_atomic_get_new_crtc_state(state, master_crtc); 1986 1987 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1988 if (conn_state->crtc != &master_crtc->base) 1989 continue; 1990 1991 encoder = to_intel_encoder(conn_state->best_encoder); 1992 break; 1993 } 1994 1995 /* 1996 * Enable sequence steps 1-7 on bigjoiner master 1997 */ 1998 if (crtc_state->bigjoiner_slave) 1999 intel_encoders_pre_pll_enable(state, master_crtc); 2000 2001 if (crtc_state->shared_dpll) 2002 intel_enable_shared_dpll(crtc_state); 2003 2004 if (crtc_state->bigjoiner_slave) 2005 intel_encoders_pre_enable(state, master_crtc); 2006 } 2007 2008 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 2009 { 2010 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2011 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2012 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2013 2014 if (crtc_state->has_pch_encoder) { 2015 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 2016 &crtc_state->fdi_m_n); 2017 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 2018 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 2019 &crtc_state->dp_m_n); 2020 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 2021 &crtc_state->dp_m2_n2); 2022 } 2023 2024 intel_set_transcoder_timings(crtc_state); 2025 2026 if (cpu_transcoder != TRANSCODER_EDP) 2027 intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder), 2028 crtc_state->pixel_multiplier - 1); 2029 2030 hsw_set_frame_start_delay(crtc_state); 2031 2032 hsw_set_transconf(crtc_state); 2033 } 2034 2035 static void hsw_crtc_enable(struct intel_atomic_state *state, 2036 struct intel_crtc *crtc) 2037 { 2038 const struct intel_crtc_state *new_crtc_state = 2039 intel_atomic_get_new_crtc_state(state, crtc); 2040 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2041 enum pipe pipe = crtc->pipe, hsw_workaround_pipe; 2042 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 2043 bool psl_clkgate_wa; 2044 2045 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 2046 return; 2047 2048 if (!new_crtc_state->bigjoiner) { 2049 intel_encoders_pre_pll_enable(state, crtc); 2050 2051 if (new_crtc_state->shared_dpll) 2052 intel_enable_shared_dpll(new_crtc_state); 2053 2054 intel_encoders_pre_enable(state, crtc); 2055 } else { 2056 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state); 2057 } 2058 2059 intel_dsc_enable(new_crtc_state); 2060 2061 if (DISPLAY_VER(dev_priv) >= 13) 2062 intel_uncompressed_joiner_enable(new_crtc_state); 2063 2064 intel_set_pipe_src_size(new_crtc_state); 2065 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 2066 bdw_set_pipemisc(new_crtc_state); 2067 2068 if (!new_crtc_state->bigjoiner_slave && !transcoder_is_dsi(cpu_transcoder)) 2069 hsw_configure_cpu_transcoder(new_crtc_state); 2070 2071 crtc->active = true; 2072 2073 /* Display WA #1180: WaDisableScalarClockGating: glk */ 2074 psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 && 2075 new_crtc_state->pch_pfit.enabled; 2076 if (psl_clkgate_wa) 2077 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true); 2078 2079 if (DISPLAY_VER(dev_priv) >= 9) 2080 skl_pfit_enable(new_crtc_state); 2081 else 2082 ilk_pfit_enable(new_crtc_state); 2083 2084 /* 2085 * On ILK+ LUT must be loaded before the pipe is running but with 2086 * clocks enabled 2087 */ 2088 intel_color_load_luts(new_crtc_state); 2089 intel_color_commit(new_crtc_state); 2090 /* update DSPCNTR to configure gamma/csc for pipe bottom color */ 2091 if (DISPLAY_VER(dev_priv) < 9) 2092 intel_disable_primary_plane(new_crtc_state); 2093 2094 hsw_set_linetime_wm(new_crtc_state); 2095 2096 if (DISPLAY_VER(dev_priv) >= 11) 2097 icl_set_pipe_chicken(new_crtc_state); 2098 2099 intel_initial_watermarks(state, crtc); 2100 2101 if (DISPLAY_VER(dev_priv) >= 11) { 2102 const struct intel_dbuf_state *dbuf_state = 2103 intel_atomic_get_new_dbuf_state(state); 2104 2105 icl_pipe_mbus_enable(crtc, dbuf_state->joined_mbus); 2106 } 2107 2108 if (new_crtc_state->bigjoiner_slave) 2109 intel_crtc_vblank_on(new_crtc_state); 2110 2111 intel_encoders_enable(state, crtc); 2112 2113 if (psl_clkgate_wa) { 2114 intel_crtc_wait_for_next_vblank(crtc); 2115 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false); 2116 } 2117 2118 /* If we change the relative order between pipe/planes enabling, we need 2119 * to change the workaround. */ 2120 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe; 2121 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { 2122 struct intel_crtc *wa_crtc; 2123 2124 wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe); 2125 2126 intel_crtc_wait_for_next_vblank(wa_crtc); 2127 intel_crtc_wait_for_next_vblank(wa_crtc); 2128 } 2129 } 2130 2131 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state) 2132 { 2133 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 2134 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2135 enum pipe pipe = crtc->pipe; 2136 2137 /* To avoid upsetting the power well on haswell only disable the pfit if 2138 * it's in use. The hw state code will make sure we get this right. */ 2139 if (!old_crtc_state->pch_pfit.enabled) 2140 return; 2141 2142 intel_de_write(dev_priv, PF_CTL(pipe), 0); 2143 intel_de_write(dev_priv, PF_WIN_POS(pipe), 0); 2144 intel_de_write(dev_priv, PF_WIN_SZ(pipe), 0); 2145 } 2146 2147 static void ilk_crtc_disable(struct intel_atomic_state *state, 2148 struct intel_crtc *crtc) 2149 { 2150 const struct intel_crtc_state *old_crtc_state = 2151 intel_atomic_get_old_crtc_state(state, crtc); 2152 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2153 enum pipe pipe = crtc->pipe; 2154 2155 /* 2156 * Sometimes spurious CPU pipe underruns happen when the 2157 * pipe is already disabled, but FDI RX/TX is still enabled. 2158 * Happens at least with VGA+HDMI cloning. Suppress them. 2159 */ 2160 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 2161 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 2162 2163 intel_encoders_disable(state, crtc); 2164 2165 intel_crtc_vblank_off(old_crtc_state); 2166 2167 intel_disable_transcoder(old_crtc_state); 2168 2169 ilk_pfit_disable(old_crtc_state); 2170 2171 if (old_crtc_state->has_pch_encoder) 2172 ilk_pch_disable(state, crtc); 2173 2174 intel_encoders_post_disable(state, crtc); 2175 2176 if (old_crtc_state->has_pch_encoder) 2177 ilk_pch_post_disable(state, crtc); 2178 2179 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2180 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 2181 } 2182 2183 static void hsw_crtc_disable(struct intel_atomic_state *state, 2184 struct intel_crtc *crtc) 2185 { 2186 const struct intel_crtc_state *old_crtc_state = 2187 intel_atomic_get_old_crtc_state(state, crtc); 2188 2189 /* 2190 * FIXME collapse everything to one hook. 2191 * Need care with mst->ddi interactions. 2192 */ 2193 if (!old_crtc_state->bigjoiner_slave) { 2194 intel_encoders_disable(state, crtc); 2195 intel_encoders_post_disable(state, crtc); 2196 } 2197 } 2198 2199 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) 2200 { 2201 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2202 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2203 2204 if (!crtc_state->gmch_pfit.control) 2205 return; 2206 2207 /* 2208 * The panel fitter should only be adjusted whilst the pipe is disabled, 2209 * according to register description and PRM. 2210 */ 2211 drm_WARN_ON(&dev_priv->drm, 2212 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE); 2213 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 2214 2215 intel_de_write(dev_priv, PFIT_PGM_RATIOS, 2216 crtc_state->gmch_pfit.pgm_ratios); 2217 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control); 2218 2219 /* Border color in case we don't scale up to the full screen. Black by 2220 * default, change to something else for debugging. */ 2221 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); 2222 } 2223 2224 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) 2225 { 2226 if (phy == PHY_NONE) 2227 return false; 2228 else if (IS_DG2(dev_priv)) 2229 /* 2230 * DG2 outputs labelled as "combo PHY" in the bspec use 2231 * SNPS PHYs with completely different programming, 2232 * hence we always return false here. 2233 */ 2234 return false; 2235 else if (IS_ALDERLAKE_S(dev_priv)) 2236 return phy <= PHY_E; 2237 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) 2238 return phy <= PHY_D; 2239 else if (IS_JSL_EHL(dev_priv)) 2240 return phy <= PHY_C; 2241 else if (DISPLAY_VER(dev_priv) >= 11) 2242 return phy <= PHY_B; 2243 else 2244 return false; 2245 } 2246 2247 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) 2248 { 2249 if (IS_DG2(dev_priv)) 2250 /* DG2's "TC1" output uses a SNPS PHY */ 2251 return false; 2252 else if (IS_ALDERLAKE_P(dev_priv)) 2253 return phy >= PHY_F && phy <= PHY_I; 2254 else if (IS_TIGERLAKE(dev_priv)) 2255 return phy >= PHY_D && phy <= PHY_I; 2256 else if (IS_ICELAKE(dev_priv)) 2257 return phy >= PHY_C && phy <= PHY_F; 2258 else 2259 return false; 2260 } 2261 2262 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy) 2263 { 2264 if (phy == PHY_NONE) 2265 return false; 2266 else if (IS_DG2(dev_priv)) 2267 /* 2268 * All four "combo" ports and the TC1 port (PHY E) use 2269 * Synopsis PHYs. 2270 */ 2271 return phy <= PHY_E; 2272 2273 return false; 2274 } 2275 2276 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) 2277 { 2278 if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD) 2279 return PHY_D + port - PORT_D_XELPD; 2280 else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1) 2281 return PHY_F + port - PORT_TC1; 2282 else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1) 2283 return PHY_B + port - PORT_TC1; 2284 else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1) 2285 return PHY_C + port - PORT_TC1; 2286 else if (IS_JSL_EHL(i915) && port == PORT_D) 2287 return PHY_A; 2288 2289 return PHY_A + port - PORT_A; 2290 } 2291 2292 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) 2293 { 2294 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port))) 2295 return TC_PORT_NONE; 2296 2297 if (DISPLAY_VER(dev_priv) >= 12) 2298 return TC_PORT_1 + port - PORT_TC1; 2299 else 2300 return TC_PORT_1 + port - PORT_C; 2301 } 2302 2303 enum intel_display_power_domain intel_port_to_power_domain(enum port port) 2304 { 2305 switch (port) { 2306 case PORT_A: 2307 return POWER_DOMAIN_PORT_DDI_A_LANES; 2308 case PORT_B: 2309 return POWER_DOMAIN_PORT_DDI_B_LANES; 2310 case PORT_C: 2311 return POWER_DOMAIN_PORT_DDI_C_LANES; 2312 case PORT_D: 2313 return POWER_DOMAIN_PORT_DDI_D_LANES; 2314 case PORT_E: 2315 return POWER_DOMAIN_PORT_DDI_E_LANES; 2316 case PORT_F: 2317 return POWER_DOMAIN_PORT_DDI_F_LANES; 2318 case PORT_G: 2319 return POWER_DOMAIN_PORT_DDI_G_LANES; 2320 case PORT_H: 2321 return POWER_DOMAIN_PORT_DDI_H_LANES; 2322 case PORT_I: 2323 return POWER_DOMAIN_PORT_DDI_I_LANES; 2324 default: 2325 MISSING_CASE(port); 2326 return POWER_DOMAIN_PORT_OTHER; 2327 } 2328 } 2329 2330 enum intel_display_power_domain 2331 intel_aux_power_domain(struct intel_digital_port *dig_port) 2332 { 2333 if (intel_tc_port_in_tbt_alt_mode(dig_port)) { 2334 switch (dig_port->aux_ch) { 2335 case AUX_CH_C: 2336 return POWER_DOMAIN_AUX_C_TBT; 2337 case AUX_CH_D: 2338 return POWER_DOMAIN_AUX_D_TBT; 2339 case AUX_CH_E: 2340 return POWER_DOMAIN_AUX_E_TBT; 2341 case AUX_CH_F: 2342 return POWER_DOMAIN_AUX_F_TBT; 2343 case AUX_CH_G: 2344 return POWER_DOMAIN_AUX_G_TBT; 2345 case AUX_CH_H: 2346 return POWER_DOMAIN_AUX_H_TBT; 2347 case AUX_CH_I: 2348 return POWER_DOMAIN_AUX_I_TBT; 2349 default: 2350 MISSING_CASE(dig_port->aux_ch); 2351 return POWER_DOMAIN_AUX_C_TBT; 2352 } 2353 } 2354 2355 return intel_legacy_aux_to_power_domain(dig_port->aux_ch); 2356 } 2357 2358 /* 2359 * Converts aux_ch to power_domain without caring about TBT ports for that use 2360 * intel_aux_power_domain() 2361 */ 2362 enum intel_display_power_domain 2363 intel_legacy_aux_to_power_domain(enum aux_ch aux_ch) 2364 { 2365 switch (aux_ch) { 2366 case AUX_CH_A: 2367 return POWER_DOMAIN_AUX_A; 2368 case AUX_CH_B: 2369 return POWER_DOMAIN_AUX_B; 2370 case AUX_CH_C: 2371 return POWER_DOMAIN_AUX_C; 2372 case AUX_CH_D: 2373 return POWER_DOMAIN_AUX_D; 2374 case AUX_CH_E: 2375 return POWER_DOMAIN_AUX_E; 2376 case AUX_CH_F: 2377 return POWER_DOMAIN_AUX_F; 2378 case AUX_CH_G: 2379 return POWER_DOMAIN_AUX_G; 2380 case AUX_CH_H: 2381 return POWER_DOMAIN_AUX_H; 2382 case AUX_CH_I: 2383 return POWER_DOMAIN_AUX_I; 2384 default: 2385 MISSING_CASE(aux_ch); 2386 return POWER_DOMAIN_AUX_A; 2387 } 2388 } 2389 2390 static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state) 2391 { 2392 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2393 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2394 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2395 struct drm_encoder *encoder; 2396 enum pipe pipe = crtc->pipe; 2397 u64 mask; 2398 2399 if (!crtc_state->hw.active) 2400 return 0; 2401 2402 mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe)); 2403 mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 2404 if (crtc_state->pch_pfit.enabled || 2405 crtc_state->pch_pfit.force_thru) 2406 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); 2407 2408 drm_for_each_encoder_mask(encoder, &dev_priv->drm, 2409 crtc_state->uapi.encoder_mask) { 2410 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2411 2412 mask |= BIT_ULL(intel_encoder->power_domain); 2413 } 2414 2415 if (HAS_DDI(dev_priv) && crtc_state->has_audio) 2416 mask |= BIT_ULL(POWER_DOMAIN_AUDIO_MMIO); 2417 2418 if (crtc_state->shared_dpll) 2419 mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE); 2420 2421 if (crtc_state->dsc.compression_enable) 2422 mask |= BIT_ULL(intel_dsc_power_domain(crtc, cpu_transcoder)); 2423 2424 return mask; 2425 } 2426 2427 static u64 2428 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state) 2429 { 2430 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2431 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2432 enum intel_display_power_domain domain; 2433 u64 domains, new_domains, old_domains; 2434 2435 domains = get_crtc_power_domains(crtc_state); 2436 2437 new_domains = domains & ~crtc->enabled_power_domains.mask; 2438 old_domains = crtc->enabled_power_domains.mask & ~domains; 2439 2440 for_each_power_domain(domain, new_domains) 2441 intel_display_power_get_in_set(dev_priv, 2442 &crtc->enabled_power_domains, 2443 domain); 2444 2445 return old_domains; 2446 } 2447 2448 static void modeset_put_crtc_power_domains(struct intel_crtc *crtc, 2449 u64 domains) 2450 { 2451 intel_display_power_put_mask_in_set(to_i915(crtc->base.dev), 2452 &crtc->enabled_power_domains, 2453 domains); 2454 } 2455 2456 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 2457 { 2458 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2459 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2460 2461 if (intel_crtc_has_dp_encoder(crtc_state)) { 2462 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 2463 &crtc_state->dp_m_n); 2464 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 2465 &crtc_state->dp_m2_n2); 2466 } 2467 2468 intel_set_transcoder_timings(crtc_state); 2469 2470 i9xx_set_pipeconf(crtc_state); 2471 } 2472 2473 static void valleyview_crtc_enable(struct intel_atomic_state *state, 2474 struct intel_crtc *crtc) 2475 { 2476 const struct intel_crtc_state *new_crtc_state = 2477 intel_atomic_get_new_crtc_state(state, crtc); 2478 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2479 enum pipe pipe = crtc->pipe; 2480 2481 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 2482 return; 2483 2484 i9xx_configure_cpu_transcoder(new_crtc_state); 2485 2486 intel_set_pipe_src_size(new_crtc_state); 2487 2488 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 2489 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY); 2490 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0); 2491 } 2492 2493 crtc->active = true; 2494 2495 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2496 2497 intel_encoders_pre_pll_enable(state, crtc); 2498 2499 if (IS_CHERRYVIEW(dev_priv)) 2500 chv_enable_pll(new_crtc_state); 2501 else 2502 vlv_enable_pll(new_crtc_state); 2503 2504 intel_encoders_pre_enable(state, crtc); 2505 2506 i9xx_pfit_enable(new_crtc_state); 2507 2508 intel_color_load_luts(new_crtc_state); 2509 intel_color_commit(new_crtc_state); 2510 /* update DSPCNTR to configure gamma for pipe bottom color */ 2511 intel_disable_primary_plane(new_crtc_state); 2512 2513 intel_initial_watermarks(state, crtc); 2514 intel_enable_transcoder(new_crtc_state); 2515 2516 intel_crtc_vblank_on(new_crtc_state); 2517 2518 intel_encoders_enable(state, crtc); 2519 } 2520 2521 static void i9xx_crtc_enable(struct intel_atomic_state *state, 2522 struct intel_crtc *crtc) 2523 { 2524 const struct intel_crtc_state *new_crtc_state = 2525 intel_atomic_get_new_crtc_state(state, crtc); 2526 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2527 enum pipe pipe = crtc->pipe; 2528 2529 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 2530 return; 2531 2532 i9xx_configure_cpu_transcoder(new_crtc_state); 2533 2534 intel_set_pipe_src_size(new_crtc_state); 2535 2536 crtc->active = true; 2537 2538 if (DISPLAY_VER(dev_priv) != 2) 2539 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2540 2541 intel_encoders_pre_enable(state, crtc); 2542 2543 i9xx_enable_pll(new_crtc_state); 2544 2545 i9xx_pfit_enable(new_crtc_state); 2546 2547 intel_color_load_luts(new_crtc_state); 2548 intel_color_commit(new_crtc_state); 2549 /* update DSPCNTR to configure gamma for pipe bottom color */ 2550 intel_disable_primary_plane(new_crtc_state); 2551 2552 if (!intel_initial_watermarks(state, crtc)) 2553 intel_update_watermarks(dev_priv); 2554 intel_enable_transcoder(new_crtc_state); 2555 2556 intel_crtc_vblank_on(new_crtc_state); 2557 2558 intel_encoders_enable(state, crtc); 2559 2560 /* prevents spurious underruns */ 2561 if (DISPLAY_VER(dev_priv) == 2) 2562 intel_crtc_wait_for_next_vblank(crtc); 2563 } 2564 2565 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) 2566 { 2567 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 2568 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2569 2570 if (!old_crtc_state->gmch_pfit.control) 2571 return; 2572 2573 assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder); 2574 2575 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n", 2576 intel_de_read(dev_priv, PFIT_CONTROL)); 2577 intel_de_write(dev_priv, PFIT_CONTROL, 0); 2578 } 2579 2580 static void i9xx_crtc_disable(struct intel_atomic_state *state, 2581 struct intel_crtc *crtc) 2582 { 2583 struct intel_crtc_state *old_crtc_state = 2584 intel_atomic_get_old_crtc_state(state, crtc); 2585 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2586 enum pipe pipe = crtc->pipe; 2587 2588 /* 2589 * On gen2 planes are double buffered but the pipe isn't, so we must 2590 * wait for planes to fully turn off before disabling the pipe. 2591 */ 2592 if (DISPLAY_VER(dev_priv) == 2) 2593 intel_crtc_wait_for_next_vblank(crtc); 2594 2595 intel_encoders_disable(state, crtc); 2596 2597 intel_crtc_vblank_off(old_crtc_state); 2598 2599 intel_disable_transcoder(old_crtc_state); 2600 2601 i9xx_pfit_disable(old_crtc_state); 2602 2603 intel_encoders_post_disable(state, crtc); 2604 2605 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) { 2606 if (IS_CHERRYVIEW(dev_priv)) 2607 chv_disable_pll(dev_priv, pipe); 2608 else if (IS_VALLEYVIEW(dev_priv)) 2609 vlv_disable_pll(dev_priv, pipe); 2610 else 2611 i9xx_disable_pll(old_crtc_state); 2612 } 2613 2614 intel_encoders_post_pll_disable(state, crtc); 2615 2616 if (DISPLAY_VER(dev_priv) != 2) 2617 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 2618 2619 if (!dev_priv->wm_disp->initial_watermarks) 2620 intel_update_watermarks(dev_priv); 2621 2622 /* clock the pipe down to 640x480@60 to potentially save power */ 2623 if (IS_I830(dev_priv)) 2624 i830_enable_pipe(dev_priv, pipe); 2625 } 2626 2627 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, 2628 struct drm_modeset_acquire_ctx *ctx) 2629 { 2630 struct intel_encoder *encoder; 2631 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2632 struct intel_bw_state *bw_state = 2633 to_intel_bw_state(dev_priv->bw_obj.state); 2634 struct intel_cdclk_state *cdclk_state = 2635 to_intel_cdclk_state(dev_priv->cdclk.obj.state); 2636 struct intel_dbuf_state *dbuf_state = 2637 to_intel_dbuf_state(dev_priv->dbuf.obj.state); 2638 struct intel_crtc_state *crtc_state = 2639 to_intel_crtc_state(crtc->base.state); 2640 struct intel_plane *plane; 2641 struct drm_atomic_state *state; 2642 struct intel_crtc_state *temp_crtc_state; 2643 enum pipe pipe = crtc->pipe; 2644 int ret; 2645 2646 if (!crtc_state->hw.active) 2647 return; 2648 2649 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 2650 const struct intel_plane_state *plane_state = 2651 to_intel_plane_state(plane->base.state); 2652 2653 if (plane_state->uapi.visible) 2654 intel_plane_disable_noatomic(crtc, plane); 2655 } 2656 2657 state = drm_atomic_state_alloc(&dev_priv->drm); 2658 if (!state) { 2659 drm_dbg_kms(&dev_priv->drm, 2660 "failed to disable [CRTC:%d:%s], out of memory", 2661 crtc->base.base.id, crtc->base.name); 2662 return; 2663 } 2664 2665 state->acquire_ctx = ctx; 2666 2667 /* Everything's already locked, -EDEADLK can't happen. */ 2668 temp_crtc_state = intel_atomic_get_crtc_state(state, crtc); 2669 ret = drm_atomic_add_affected_connectors(state, &crtc->base); 2670 2671 drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret); 2672 2673 dev_priv->display->crtc_disable(to_intel_atomic_state(state), crtc); 2674 2675 drm_atomic_state_put(state); 2676 2677 drm_dbg_kms(&dev_priv->drm, 2678 "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", 2679 crtc->base.base.id, crtc->base.name); 2680 2681 crtc->active = false; 2682 crtc->base.enabled = false; 2683 2684 drm_WARN_ON(&dev_priv->drm, 2685 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0); 2686 crtc_state->uapi.active = false; 2687 crtc_state->uapi.connector_mask = 0; 2688 crtc_state->uapi.encoder_mask = 0; 2689 intel_crtc_free_hw_state(crtc_state); 2690 memset(&crtc_state->hw, 0, sizeof(crtc_state->hw)); 2691 2692 for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder) 2693 encoder->base.crtc = NULL; 2694 2695 intel_fbc_disable(crtc); 2696 intel_update_watermarks(dev_priv); 2697 intel_disable_shared_dpll(crtc_state); 2698 2699 intel_display_power_put_all_in_set(dev_priv, &crtc->enabled_power_domains); 2700 2701 cdclk_state->min_cdclk[pipe] = 0; 2702 cdclk_state->min_voltage_level[pipe] = 0; 2703 cdclk_state->active_pipes &= ~BIT(pipe); 2704 2705 dbuf_state->active_pipes &= ~BIT(pipe); 2706 2707 bw_state->data_rate[pipe] = 0; 2708 bw_state->num_active_planes[pipe] = 0; 2709 } 2710 2711 /* 2712 * turn all crtc's off, but do not adjust state 2713 * This has to be paired with a call to intel_modeset_setup_hw_state. 2714 */ 2715 int intel_display_suspend(struct drm_device *dev) 2716 { 2717 struct drm_i915_private *dev_priv = to_i915(dev); 2718 struct drm_atomic_state *state; 2719 int ret; 2720 2721 if (!HAS_DISPLAY(dev_priv)) 2722 return 0; 2723 2724 state = drm_atomic_helper_suspend(dev); 2725 ret = PTR_ERR_OR_ZERO(state); 2726 if (ret) 2727 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", 2728 ret); 2729 else 2730 dev_priv->modeset_restore_state = state; 2731 return ret; 2732 } 2733 2734 void intel_encoder_destroy(struct drm_encoder *encoder) 2735 { 2736 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2737 2738 drm_encoder_cleanup(encoder); 2739 kfree(intel_encoder); 2740 } 2741 2742 /* Cross check the actual hw state with our own modeset state tracking (and it's 2743 * internal consistency). */ 2744 static void intel_connector_verify_state(struct intel_crtc_state *crtc_state, 2745 struct drm_connector_state *conn_state) 2746 { 2747 struct intel_connector *connector = to_intel_connector(conn_state->connector); 2748 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2749 2750 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", 2751 connector->base.base.id, connector->base.name); 2752 2753 if (connector->get_hw_state(connector)) { 2754 struct intel_encoder *encoder = intel_attached_encoder(connector); 2755 2756 I915_STATE_WARN(!crtc_state, 2757 "connector enabled without attached crtc\n"); 2758 2759 if (!crtc_state) 2760 return; 2761 2762 I915_STATE_WARN(!crtc_state->hw.active, 2763 "connector is active, but attached crtc isn't\n"); 2764 2765 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) 2766 return; 2767 2768 I915_STATE_WARN(conn_state->best_encoder != &encoder->base, 2769 "atomic encoder doesn't match attached encoder\n"); 2770 2771 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, 2772 "attached encoder crtc differs from connector crtc\n"); 2773 } else { 2774 I915_STATE_WARN(crtc_state && crtc_state->hw.active, 2775 "attached crtc is active, but connector isn't\n"); 2776 I915_STATE_WARN(!crtc_state && conn_state->best_encoder, 2777 "best encoder set without crtc!\n"); 2778 } 2779 } 2780 2781 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state) 2782 { 2783 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2784 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2785 2786 /* IPS only exists on ULT machines and is tied to pipe A. */ 2787 if (!hsw_crtc_supports_ips(crtc)) 2788 return false; 2789 2790 if (!dev_priv->params.enable_ips) 2791 return false; 2792 2793 if (crtc_state->pipe_bpp > 24) 2794 return false; 2795 2796 /* 2797 * We compare against max which means we must take 2798 * the increased cdclk requirement into account when 2799 * calculating the new cdclk. 2800 * 2801 * Should measure whether using a lower cdclk w/o IPS 2802 */ 2803 if (IS_BROADWELL(dev_priv) && 2804 crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100) 2805 return false; 2806 2807 return true; 2808 } 2809 2810 static int hsw_compute_ips_config(struct intel_crtc_state *crtc_state) 2811 { 2812 struct drm_i915_private *dev_priv = 2813 to_i915(crtc_state->uapi.crtc->dev); 2814 struct intel_atomic_state *state = 2815 to_intel_atomic_state(crtc_state->uapi.state); 2816 2817 crtc_state->ips_enabled = false; 2818 2819 if (!hsw_crtc_state_ips_capable(crtc_state)) 2820 return 0; 2821 2822 /* 2823 * When IPS gets enabled, the pipe CRC changes. Since IPS gets 2824 * enabled and disabled dynamically based on package C states, 2825 * user space can't make reliable use of the CRCs, so let's just 2826 * completely disable it. 2827 */ 2828 if (crtc_state->crc_enabled) 2829 return 0; 2830 2831 /* IPS should be fine as long as at least one plane is enabled. */ 2832 if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR))) 2833 return 0; 2834 2835 if (IS_BROADWELL(dev_priv)) { 2836 const struct intel_cdclk_state *cdclk_state; 2837 2838 cdclk_state = intel_atomic_get_cdclk_state(state); 2839 if (IS_ERR(cdclk_state)) 2840 return PTR_ERR(cdclk_state); 2841 2842 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ 2843 if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100) 2844 return 0; 2845 } 2846 2847 crtc_state->ips_enabled = true; 2848 2849 return 0; 2850 } 2851 2852 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) 2853 { 2854 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2855 2856 /* GDG double wide on either pipe, otherwise pipe A only */ 2857 return DISPLAY_VER(dev_priv) < 4 && 2858 (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); 2859 } 2860 2861 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) 2862 { 2863 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock; 2864 struct drm_rect src; 2865 2866 /* 2867 * We only use IF-ID interlacing. If we ever use 2868 * PF-ID we'll need to adjust the pixel_rate here. 2869 */ 2870 2871 if (!crtc_state->pch_pfit.enabled) 2872 return pixel_rate; 2873 2874 drm_rect_init(&src, 0, 0, 2875 crtc_state->pipe_src_w << 16, 2876 crtc_state->pipe_src_h << 16); 2877 2878 return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst, 2879 pixel_rate); 2880 } 2881 2882 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode, 2883 const struct drm_display_mode *timings) 2884 { 2885 mode->hdisplay = timings->crtc_hdisplay; 2886 mode->htotal = timings->crtc_htotal; 2887 mode->hsync_start = timings->crtc_hsync_start; 2888 mode->hsync_end = timings->crtc_hsync_end; 2889 2890 mode->vdisplay = timings->crtc_vdisplay; 2891 mode->vtotal = timings->crtc_vtotal; 2892 mode->vsync_start = timings->crtc_vsync_start; 2893 mode->vsync_end = timings->crtc_vsync_end; 2894 2895 mode->flags = timings->flags; 2896 mode->type = DRM_MODE_TYPE_DRIVER; 2897 2898 mode->clock = timings->crtc_clock; 2899 2900 drm_mode_set_name(mode); 2901 } 2902 2903 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) 2904 { 2905 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2906 2907 if (HAS_GMCH(dev_priv)) 2908 /* FIXME calculate proper pipe pixel rate for GMCH pfit */ 2909 crtc_state->pixel_rate = 2910 crtc_state->hw.pipe_mode.crtc_clock; 2911 else 2912 crtc_state->pixel_rate = 2913 ilk_pipe_pixel_rate(crtc_state); 2914 } 2915 2916 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state) 2917 { 2918 struct drm_display_mode *mode = &crtc_state->hw.mode; 2919 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2920 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2921 2922 drm_mode_copy(pipe_mode, adjusted_mode); 2923 2924 if (crtc_state->bigjoiner) { 2925 /* 2926 * transcoder is programmed to the full mode, 2927 * but pipe timings are half of the transcoder mode 2928 */ 2929 pipe_mode->crtc_hdisplay /= 2; 2930 pipe_mode->crtc_hblank_start /= 2; 2931 pipe_mode->crtc_hblank_end /= 2; 2932 pipe_mode->crtc_hsync_start /= 2; 2933 pipe_mode->crtc_hsync_end /= 2; 2934 pipe_mode->crtc_htotal /= 2; 2935 pipe_mode->crtc_clock /= 2; 2936 } 2937 2938 if (crtc_state->splitter.enable) { 2939 int n = crtc_state->splitter.link_count; 2940 int overlap = crtc_state->splitter.pixel_overlap; 2941 2942 /* 2943 * eDP MSO uses segment timings from EDID for transcoder 2944 * timings, but full mode for everything else. 2945 * 2946 * h_full = (h_segment - pixel_overlap) * link_count 2947 */ 2948 pipe_mode->crtc_hdisplay = (pipe_mode->crtc_hdisplay - overlap) * n; 2949 pipe_mode->crtc_hblank_start = (pipe_mode->crtc_hblank_start - overlap) * n; 2950 pipe_mode->crtc_hblank_end = (pipe_mode->crtc_hblank_end - overlap) * n; 2951 pipe_mode->crtc_hsync_start = (pipe_mode->crtc_hsync_start - overlap) * n; 2952 pipe_mode->crtc_hsync_end = (pipe_mode->crtc_hsync_end - overlap) * n; 2953 pipe_mode->crtc_htotal = (pipe_mode->crtc_htotal - overlap) * n; 2954 pipe_mode->crtc_clock *= n; 2955 2956 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2957 intel_mode_from_crtc_timings(adjusted_mode, pipe_mode); 2958 } else { 2959 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2960 intel_mode_from_crtc_timings(adjusted_mode, adjusted_mode); 2961 } 2962 2963 intel_crtc_compute_pixel_rate(crtc_state); 2964 2965 drm_mode_copy(mode, adjusted_mode); 2966 mode->hdisplay = crtc_state->pipe_src_w << crtc_state->bigjoiner; 2967 mode->vdisplay = crtc_state->pipe_src_h; 2968 } 2969 2970 static void intel_encoder_get_config(struct intel_encoder *encoder, 2971 struct intel_crtc_state *crtc_state) 2972 { 2973 encoder->get_config(encoder, crtc_state); 2974 2975 intel_crtc_readout_derived_state(crtc_state); 2976 } 2977 2978 static int intel_crtc_compute_config(struct intel_crtc *crtc, 2979 struct intel_crtc_state *pipe_config) 2980 { 2981 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2982 struct drm_display_mode *pipe_mode = &pipe_config->hw.pipe_mode; 2983 int clock_limit = dev_priv->max_dotclk_freq; 2984 2985 drm_mode_copy(pipe_mode, &pipe_config->hw.adjusted_mode); 2986 2987 /* Adjust pipe_mode for bigjoiner, with half the horizontal mode */ 2988 if (pipe_config->bigjoiner) { 2989 pipe_mode->crtc_clock /= 2; 2990 pipe_mode->crtc_hdisplay /= 2; 2991 pipe_mode->crtc_hblank_start /= 2; 2992 pipe_mode->crtc_hblank_end /= 2; 2993 pipe_mode->crtc_hsync_start /= 2; 2994 pipe_mode->crtc_hsync_end /= 2; 2995 pipe_mode->crtc_htotal /= 2; 2996 pipe_config->pipe_src_w /= 2; 2997 } 2998 2999 if (pipe_config->splitter.enable) { 3000 int n = pipe_config->splitter.link_count; 3001 int overlap = pipe_config->splitter.pixel_overlap; 3002 3003 pipe_mode->crtc_hdisplay = (pipe_mode->crtc_hdisplay - overlap) * n; 3004 pipe_mode->crtc_hblank_start = (pipe_mode->crtc_hblank_start - overlap) * n; 3005 pipe_mode->crtc_hblank_end = (pipe_mode->crtc_hblank_end - overlap) * n; 3006 pipe_mode->crtc_hsync_start = (pipe_mode->crtc_hsync_start - overlap) * n; 3007 pipe_mode->crtc_hsync_end = (pipe_mode->crtc_hsync_end - overlap) * n; 3008 pipe_mode->crtc_htotal = (pipe_mode->crtc_htotal - overlap) * n; 3009 pipe_mode->crtc_clock *= n; 3010 } 3011 3012 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 3013 3014 if (DISPLAY_VER(dev_priv) < 4) { 3015 clock_limit = dev_priv->max_cdclk_freq * 9 / 10; 3016 3017 /* 3018 * Enable double wide mode when the dot clock 3019 * is > 90% of the (display) core speed. 3020 */ 3021 if (intel_crtc_supports_double_wide(crtc) && 3022 pipe_mode->crtc_clock > clock_limit) { 3023 clock_limit = dev_priv->max_dotclk_freq; 3024 pipe_config->double_wide = true; 3025 } 3026 } 3027 3028 if (pipe_mode->crtc_clock > clock_limit) { 3029 drm_dbg_kms(&dev_priv->drm, 3030 "requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", 3031 pipe_mode->crtc_clock, clock_limit, 3032 yesno(pipe_config->double_wide)); 3033 return -EINVAL; 3034 } 3035 3036 /* 3037 * Pipe horizontal size must be even in: 3038 * - DVO ganged mode 3039 * - LVDS dual channel mode 3040 * - Double wide pipe 3041 */ 3042 if (pipe_config->pipe_src_w & 1) { 3043 if (pipe_config->double_wide) { 3044 drm_dbg_kms(&dev_priv->drm, 3045 "Odd pipe source width not supported with double wide pipe\n"); 3046 return -EINVAL; 3047 } 3048 3049 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) && 3050 intel_is_dual_link_lvds(dev_priv)) { 3051 drm_dbg_kms(&dev_priv->drm, 3052 "Odd pipe source width not supported with dual link LVDS\n"); 3053 return -EINVAL; 3054 } 3055 } 3056 3057 intel_crtc_compute_pixel_rate(pipe_config); 3058 3059 if (pipe_config->has_pch_encoder) 3060 return ilk_fdi_compute_config(crtc, pipe_config); 3061 3062 return 0; 3063 } 3064 3065 static void 3066 intel_reduce_m_n_ratio(u32 *num, u32 *den) 3067 { 3068 while (*num > DATA_LINK_M_N_MASK || 3069 *den > DATA_LINK_M_N_MASK) { 3070 *num >>= 1; 3071 *den >>= 1; 3072 } 3073 } 3074 3075 static void compute_m_n(unsigned int m, unsigned int n, 3076 u32 *ret_m, u32 *ret_n, 3077 bool constant_n) 3078 { 3079 /* 3080 * Several DP dongles in particular seem to be fussy about 3081 * too large link M/N values. Give N value as 0x8000 that 3082 * should be acceptable by specific devices. 0x8000 is the 3083 * specified fixed N value for asynchronous clock mode, 3084 * which the devices expect also in synchronous clock mode. 3085 */ 3086 if (constant_n) 3087 *ret_n = DP_LINK_CONSTANT_N_VALUE; 3088 else 3089 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); 3090 3091 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n); 3092 intel_reduce_m_n_ratio(ret_m, ret_n); 3093 } 3094 3095 void 3096 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes, 3097 int pixel_clock, int link_clock, 3098 struct intel_link_m_n *m_n, 3099 bool constant_n, bool fec_enable) 3100 { 3101 u32 data_clock = bits_per_pixel * pixel_clock; 3102 3103 if (fec_enable) 3104 data_clock = intel_dp_mode_to_fec_clock(data_clock); 3105 3106 m_n->tu = 64; 3107 compute_m_n(data_clock, 3108 link_clock * nlanes * 8, 3109 &m_n->data_m, &m_n->data_n, 3110 constant_n); 3111 3112 compute_m_n(pixel_clock, link_clock, 3113 &m_n->link_m, &m_n->link_n, 3114 constant_n); 3115 } 3116 3117 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv) 3118 { 3119 /* 3120 * There may be no VBT; and if the BIOS enabled SSC we can 3121 * just keep using it to avoid unnecessary flicker. Whereas if the 3122 * BIOS isn't using it, don't assume it will work even if the VBT 3123 * indicates as much. 3124 */ 3125 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { 3126 bool bios_lvds_use_ssc = intel_de_read(dev_priv, 3127 PCH_DREF_CONTROL) & 3128 DREF_SSC1_ENABLE; 3129 3130 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { 3131 drm_dbg_kms(&dev_priv->drm, 3132 "SSC %s by BIOS, overriding VBT which says %s\n", 3133 enableddisabled(bios_lvds_use_ssc), 3134 enableddisabled(dev_priv->vbt.lvds_use_ssc)); 3135 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; 3136 } 3137 } 3138 } 3139 3140 void intel_zero_m_n(struct intel_link_m_n *m_n) 3141 { 3142 /* corresponds to 0 register value */ 3143 memset(m_n, 0, sizeof(*m_n)); 3144 m_n->tu = 1; 3145 } 3146 3147 void intel_set_m_n(struct drm_i915_private *i915, 3148 const struct intel_link_m_n *m_n, 3149 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 3150 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 3151 { 3152 intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); 3153 intel_de_write(i915, data_n_reg, m_n->data_n); 3154 intel_de_write(i915, link_m_reg, m_n->link_m); 3155 /* 3156 * On BDW+ writing LINK_N arms the double buffered update 3157 * of all the M/N registers, so it must be written last. 3158 */ 3159 intel_de_write(i915, link_n_reg, m_n->link_n); 3160 } 3161 3162 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, 3163 enum transcoder transcoder) 3164 { 3165 if (IS_HASWELL(dev_priv)) 3166 return transcoder == TRANSCODER_EDP; 3167 3168 return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv); 3169 } 3170 3171 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, 3172 enum transcoder transcoder, 3173 const struct intel_link_m_n *m_n) 3174 { 3175 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3176 enum pipe pipe = crtc->pipe; 3177 3178 if (DISPLAY_VER(dev_priv) >= 5) 3179 intel_set_m_n(dev_priv, m_n, 3180 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 3181 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 3182 else 3183 intel_set_m_n(dev_priv, m_n, 3184 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 3185 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 3186 } 3187 3188 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, 3189 enum transcoder transcoder, 3190 const struct intel_link_m_n *m_n) 3191 { 3192 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3193 3194 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 3195 return; 3196 3197 intel_set_m_n(dev_priv, m_n, 3198 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 3199 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 3200 } 3201 3202 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) 3203 { 3204 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3205 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3206 enum pipe pipe = crtc->pipe; 3207 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3208 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 3209 u32 crtc_vtotal, crtc_vblank_end; 3210 int vsyncshift = 0; 3211 3212 /* We need to be careful not to changed the adjusted mode, for otherwise 3213 * the hw state checker will get angry at the mismatch. */ 3214 crtc_vtotal = adjusted_mode->crtc_vtotal; 3215 crtc_vblank_end = adjusted_mode->crtc_vblank_end; 3216 3217 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 3218 /* the chip adds 2 halflines automatically */ 3219 crtc_vtotal -= 1; 3220 crtc_vblank_end -= 1; 3221 3222 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3223 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; 3224 else 3225 vsyncshift = adjusted_mode->crtc_hsync_start - 3226 adjusted_mode->crtc_htotal / 2; 3227 if (vsyncshift < 0) 3228 vsyncshift += adjusted_mode->crtc_htotal; 3229 } 3230 3231 if (DISPLAY_VER(dev_priv) > 3) 3232 intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder), 3233 vsyncshift); 3234 3235 intel_de_write(dev_priv, HTOTAL(cpu_transcoder), 3236 (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16)); 3237 intel_de_write(dev_priv, HBLANK(cpu_transcoder), 3238 (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16)); 3239 intel_de_write(dev_priv, HSYNC(cpu_transcoder), 3240 (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16)); 3241 3242 intel_de_write(dev_priv, VTOTAL(cpu_transcoder), 3243 (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16)); 3244 intel_de_write(dev_priv, VBLANK(cpu_transcoder), 3245 (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16)); 3246 intel_de_write(dev_priv, VSYNC(cpu_transcoder), 3247 (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16)); 3248 3249 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be 3250 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is 3251 * documented on the DDI_FUNC_CTL register description, EDP Input Select 3252 * bits. */ 3253 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && 3254 (pipe == PIPE_B || pipe == PIPE_C)) 3255 intel_de_write(dev_priv, VTOTAL(pipe), 3256 intel_de_read(dev_priv, VTOTAL(cpu_transcoder))); 3257 3258 } 3259 3260 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) 3261 { 3262 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3263 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3264 enum pipe pipe = crtc->pipe; 3265 3266 /* pipesrc controls the size that is scaled from, which should 3267 * always be the user's requested size. 3268 */ 3269 intel_de_write(dev_priv, PIPESRC(pipe), 3270 PIPESRC_WIDTH(crtc_state->pipe_src_w - 1) | 3271 PIPESRC_HEIGHT(crtc_state->pipe_src_h - 1)); 3272 } 3273 3274 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) 3275 { 3276 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3277 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3278 3279 if (DISPLAY_VER(dev_priv) == 2) 3280 return false; 3281 3282 if (DISPLAY_VER(dev_priv) >= 9 || 3283 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 3284 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW; 3285 else 3286 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK; 3287 } 3288 3289 static void intel_get_transcoder_timings(struct intel_crtc *crtc, 3290 struct intel_crtc_state *pipe_config) 3291 { 3292 struct drm_device *dev = crtc->base.dev; 3293 struct drm_i915_private *dev_priv = to_i915(dev); 3294 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3295 u32 tmp; 3296 3297 tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder)); 3298 pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; 3299 pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; 3300 3301 if (!transcoder_is_dsi(cpu_transcoder)) { 3302 tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder)); 3303 pipe_config->hw.adjusted_mode.crtc_hblank_start = 3304 (tmp & 0xffff) + 1; 3305 pipe_config->hw.adjusted_mode.crtc_hblank_end = 3306 ((tmp >> 16) & 0xffff) + 1; 3307 } 3308 tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder)); 3309 pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; 3310 pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; 3311 3312 tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder)); 3313 pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; 3314 pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; 3315 3316 if (!transcoder_is_dsi(cpu_transcoder)) { 3317 tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder)); 3318 pipe_config->hw.adjusted_mode.crtc_vblank_start = 3319 (tmp & 0xffff) + 1; 3320 pipe_config->hw.adjusted_mode.crtc_vblank_end = 3321 ((tmp >> 16) & 0xffff) + 1; 3322 } 3323 tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder)); 3324 pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; 3325 pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; 3326 3327 if (intel_pipe_is_interlaced(pipe_config)) { 3328 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; 3329 pipe_config->hw.adjusted_mode.crtc_vtotal += 1; 3330 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1; 3331 } 3332 } 3333 3334 static void intel_get_pipe_src_size(struct intel_crtc *crtc, 3335 struct intel_crtc_state *pipe_config) 3336 { 3337 struct drm_device *dev = crtc->base.dev; 3338 struct drm_i915_private *dev_priv = to_i915(dev); 3339 u32 tmp; 3340 3341 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe)); 3342 pipe_config->pipe_src_w = REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1; 3343 pipe_config->pipe_src_h = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1; 3344 } 3345 3346 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) 3347 { 3348 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3349 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3350 u32 pipeconf; 3351 3352 pipeconf = 0; 3353 3354 /* we keep both pipes enabled on 830 */ 3355 if (IS_I830(dev_priv)) 3356 pipeconf |= intel_de_read(dev_priv, PIPECONF(crtc->pipe)) & PIPECONF_ENABLE; 3357 3358 if (crtc_state->double_wide) 3359 pipeconf |= PIPECONF_DOUBLE_WIDE; 3360 3361 /* only g4x and later have fancy bpc/dither controls */ 3362 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 3363 IS_CHERRYVIEW(dev_priv)) { 3364 /* Bspec claims that we can't use dithering for 30bpp pipes. */ 3365 if (crtc_state->dither && crtc_state->pipe_bpp != 30) 3366 pipeconf |= PIPECONF_DITHER_EN | 3367 PIPECONF_DITHER_TYPE_SP; 3368 3369 switch (crtc_state->pipe_bpp) { 3370 case 18: 3371 pipeconf |= PIPECONF_BPC_6; 3372 break; 3373 case 24: 3374 pipeconf |= PIPECONF_BPC_8; 3375 break; 3376 case 30: 3377 pipeconf |= PIPECONF_BPC_10; 3378 break; 3379 default: 3380 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3381 BUG(); 3382 } 3383 } 3384 3385 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 3386 if (DISPLAY_VER(dev_priv) < 4 || 3387 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3388 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; 3389 else 3390 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; 3391 } else { 3392 pipeconf |= PIPECONF_INTERLACE_PROGRESSIVE; 3393 } 3394 3395 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 3396 crtc_state->limited_color_range) 3397 pipeconf |= PIPECONF_COLOR_RANGE_SELECT; 3398 3399 pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); 3400 3401 pipeconf |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay - 1); 3402 3403 intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf); 3404 intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe)); 3405 } 3406 3407 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv) 3408 { 3409 if (IS_I830(dev_priv)) 3410 return false; 3411 3412 return DISPLAY_VER(dev_priv) >= 4 || 3413 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); 3414 } 3415 3416 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state) 3417 { 3418 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3419 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3420 u32 tmp; 3421 3422 if (!i9xx_has_pfit(dev_priv)) 3423 return; 3424 3425 tmp = intel_de_read(dev_priv, PFIT_CONTROL); 3426 if (!(tmp & PFIT_ENABLE)) 3427 return; 3428 3429 /* Check whether the pfit is attached to our pipe. */ 3430 if (DISPLAY_VER(dev_priv) < 4) { 3431 if (crtc->pipe != PIPE_B) 3432 return; 3433 } else { 3434 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) 3435 return; 3436 } 3437 3438 crtc_state->gmch_pfit.control = tmp; 3439 crtc_state->gmch_pfit.pgm_ratios = 3440 intel_de_read(dev_priv, PFIT_PGM_RATIOS); 3441 } 3442 3443 static void vlv_crtc_clock_get(struct intel_crtc *crtc, 3444 struct intel_crtc_state *pipe_config) 3445 { 3446 struct drm_device *dev = crtc->base.dev; 3447 struct drm_i915_private *dev_priv = to_i915(dev); 3448 enum pipe pipe = crtc->pipe; 3449 struct dpll clock; 3450 u32 mdiv; 3451 int refclk = 100000; 3452 3453 /* In case of DSI, DPLL will not be used */ 3454 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 3455 return; 3456 3457 vlv_dpio_get(dev_priv); 3458 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); 3459 vlv_dpio_put(dev_priv); 3460 3461 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; 3462 clock.m2 = mdiv & DPIO_M2DIV_MASK; 3463 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; 3464 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; 3465 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; 3466 3467 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); 3468 } 3469 3470 static void chv_crtc_clock_get(struct intel_crtc *crtc, 3471 struct intel_crtc_state *pipe_config) 3472 { 3473 struct drm_device *dev = crtc->base.dev; 3474 struct drm_i915_private *dev_priv = to_i915(dev); 3475 enum pipe pipe = crtc->pipe; 3476 enum dpio_channel port = vlv_pipe_to_channel(pipe); 3477 struct dpll clock; 3478 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; 3479 int refclk = 100000; 3480 3481 /* In case of DSI, DPLL will not be used */ 3482 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 3483 return; 3484 3485 vlv_dpio_get(dev_priv); 3486 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); 3487 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); 3488 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); 3489 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); 3490 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); 3491 vlv_dpio_put(dev_priv); 3492 3493 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; 3494 clock.m2 = (pll_dw0 & 0xff) << 22; 3495 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) 3496 clock.m2 |= pll_dw2 & 0x3fffff; 3497 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; 3498 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; 3499 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; 3500 3501 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); 3502 } 3503 3504 static enum intel_output_format 3505 bdw_get_pipemisc_output_format(struct intel_crtc *crtc) 3506 { 3507 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3508 u32 tmp; 3509 3510 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); 3511 3512 if (tmp & PIPEMISC_YUV420_ENABLE) { 3513 /* We support 4:2:0 in full blend mode only */ 3514 drm_WARN_ON(&dev_priv->drm, 3515 (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0); 3516 3517 return INTEL_OUTPUT_FORMAT_YCBCR420; 3518 } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) { 3519 return INTEL_OUTPUT_FORMAT_YCBCR444; 3520 } else { 3521 return INTEL_OUTPUT_FORMAT_RGB; 3522 } 3523 } 3524 3525 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state) 3526 { 3527 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3528 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 3529 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3530 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 3531 u32 tmp; 3532 3533 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); 3534 3535 if (tmp & DISP_PIPE_GAMMA_ENABLE) 3536 crtc_state->gamma_enable = true; 3537 3538 if (!HAS_GMCH(dev_priv) && 3539 tmp & DISP_PIPE_CSC_ENABLE) 3540 crtc_state->csc_enable = true; 3541 } 3542 3543 static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 3544 struct intel_crtc_state *pipe_config) 3545 { 3546 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3547 enum intel_display_power_domain power_domain; 3548 intel_wakeref_t wakeref; 3549 u32 tmp; 3550 bool ret; 3551 3552 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3553 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3554 if (!wakeref) 3555 return false; 3556 3557 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3558 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3559 pipe_config->shared_dpll = NULL; 3560 3561 ret = false; 3562 3563 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); 3564 if (!(tmp & PIPECONF_ENABLE)) 3565 goto out; 3566 3567 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 3568 IS_CHERRYVIEW(dev_priv)) { 3569 switch (tmp & PIPECONF_BPC_MASK) { 3570 case PIPECONF_BPC_6: 3571 pipe_config->pipe_bpp = 18; 3572 break; 3573 case PIPECONF_BPC_8: 3574 pipe_config->pipe_bpp = 24; 3575 break; 3576 case PIPECONF_BPC_10: 3577 pipe_config->pipe_bpp = 30; 3578 break; 3579 default: 3580 MISSING_CASE(tmp); 3581 break; 3582 } 3583 } 3584 3585 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 3586 (tmp & PIPECONF_COLOR_RANGE_SELECT)) 3587 pipe_config->limited_color_range = true; 3588 3589 pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_I9XX, tmp); 3590 3591 if (IS_CHERRYVIEW(dev_priv)) 3592 pipe_config->cgm_mode = intel_de_read(dev_priv, 3593 CGM_PIPE_MODE(crtc->pipe)); 3594 3595 i9xx_get_pipe_color_config(pipe_config); 3596 intel_color_get_config(pipe_config); 3597 3598 if (DISPLAY_VER(dev_priv) < 4) 3599 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; 3600 3601 intel_get_transcoder_timings(crtc, pipe_config); 3602 intel_get_pipe_src_size(crtc, pipe_config); 3603 3604 i9xx_get_pfit_config(pipe_config); 3605 3606 if (DISPLAY_VER(dev_priv) >= 4) { 3607 /* No way to read it out on pipes B and C */ 3608 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) 3609 tmp = dev_priv->chv_dpll_md[crtc->pipe]; 3610 else 3611 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe)); 3612 pipe_config->pixel_multiplier = 3613 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) 3614 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; 3615 pipe_config->dpll_hw_state.dpll_md = tmp; 3616 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 3617 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 3618 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe)); 3619 pipe_config->pixel_multiplier = 3620 ((tmp & SDVO_MULTIPLIER_MASK) 3621 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; 3622 } else { 3623 /* Note that on i915G/GM the pixel multiplier is in the sdvo 3624 * port and will be fixed up in the encoder->get_config 3625 * function. */ 3626 pipe_config->pixel_multiplier = 1; 3627 } 3628 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv, 3629 DPLL(crtc->pipe)); 3630 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 3631 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv, 3632 FP0(crtc->pipe)); 3633 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv, 3634 FP1(crtc->pipe)); 3635 } else { 3636 /* Mask out read-only status bits. */ 3637 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | 3638 DPLL_PORTC_READY_MASK | 3639 DPLL_PORTB_READY_MASK); 3640 } 3641 3642 if (IS_CHERRYVIEW(dev_priv)) 3643 chv_crtc_clock_get(crtc, pipe_config); 3644 else if (IS_VALLEYVIEW(dev_priv)) 3645 vlv_crtc_clock_get(crtc, pipe_config); 3646 else 3647 i9xx_crtc_clock_get(crtc, pipe_config); 3648 3649 /* 3650 * Normally the dotclock is filled in by the encoder .get_config() 3651 * but in case the pipe is enabled w/o any ports we need a sane 3652 * default. 3653 */ 3654 pipe_config->hw.adjusted_mode.crtc_clock = 3655 pipe_config->port_clock / pipe_config->pixel_multiplier; 3656 3657 ret = true; 3658 3659 out: 3660 intel_display_power_put(dev_priv, power_domain, wakeref); 3661 3662 return ret; 3663 } 3664 3665 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) 3666 { 3667 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3668 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3669 enum pipe pipe = crtc->pipe; 3670 u32 val; 3671 3672 val = 0; 3673 3674 switch (crtc_state->pipe_bpp) { 3675 case 18: 3676 val |= PIPECONF_BPC_6; 3677 break; 3678 case 24: 3679 val |= PIPECONF_BPC_8; 3680 break; 3681 case 30: 3682 val |= PIPECONF_BPC_10; 3683 break; 3684 case 36: 3685 val |= PIPECONF_BPC_12; 3686 break; 3687 default: 3688 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3689 BUG(); 3690 } 3691 3692 if (crtc_state->dither) 3693 val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP; 3694 3695 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3696 val |= PIPECONF_INTERLACE_IF_ID_ILK; 3697 else 3698 val |= PIPECONF_INTERLACE_PF_PD_ILK; 3699 3700 /* 3701 * This would end up with an odd purple hue over 3702 * the entire display. Make sure we don't do it. 3703 */ 3704 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 3705 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 3706 3707 if (crtc_state->limited_color_range && 3708 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3709 val |= PIPECONF_COLOR_RANGE_SELECT; 3710 3711 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3712 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709; 3713 3714 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); 3715 3716 val |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay - 1); 3717 3718 intel_de_write(dev_priv, PIPECONF(pipe), val); 3719 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 3720 } 3721 3722 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) 3723 { 3724 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3725 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3726 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3727 u32 val = 0; 3728 3729 if (IS_HASWELL(dev_priv) && crtc_state->dither) 3730 val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP; 3731 3732 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3733 val |= PIPECONF_INTERLACE_IF_ID_ILK; 3734 else 3735 val |= PIPECONF_INTERLACE_PF_PD_ILK; 3736 3737 if (IS_HASWELL(dev_priv) && 3738 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3739 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW; 3740 3741 intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val); 3742 intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder)); 3743 } 3744 3745 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) 3746 { 3747 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3748 const struct intel_crtc_scaler_state *scaler_state = 3749 &crtc_state->scaler_state; 3750 3751 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3752 u32 val = 0; 3753 int i; 3754 3755 switch (crtc_state->pipe_bpp) { 3756 case 18: 3757 val |= PIPEMISC_BPC_6; 3758 break; 3759 case 24: 3760 val |= PIPEMISC_BPC_8; 3761 break; 3762 case 30: 3763 val |= PIPEMISC_BPC_10; 3764 break; 3765 case 36: 3766 /* Port output 12BPC defined for ADLP+ */ 3767 if (DISPLAY_VER(dev_priv) > 12) 3768 val |= PIPEMISC_BPC_12_ADLP; 3769 break; 3770 default: 3771 MISSING_CASE(crtc_state->pipe_bpp); 3772 break; 3773 } 3774 3775 if (crtc_state->dither) 3776 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; 3777 3778 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 3779 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 3780 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV; 3781 3782 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 3783 val |= PIPEMISC_YUV420_ENABLE | 3784 PIPEMISC_YUV420_MODE_FULL_BLEND; 3785 3786 if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state)) 3787 val |= PIPEMISC_HDR_MODE_PRECISION; 3788 3789 if (DISPLAY_VER(dev_priv) >= 12) 3790 val |= PIPEMISC_PIXEL_ROUNDING_TRUNC; 3791 3792 if (IS_ALDERLAKE_P(dev_priv)) { 3793 bool scaler_in_use = false; 3794 3795 for (i = 0; i < crtc->num_scalers; i++) { 3796 if (!scaler_state->scalers[i].in_use) 3797 continue; 3798 3799 scaler_in_use = true; 3800 break; 3801 } 3802 3803 intel_de_rmw(dev_priv, PIPE_MISC2(crtc->pipe), 3804 PIPE_MISC2_BUBBLE_COUNTER_MASK, 3805 scaler_in_use ? PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN : 3806 PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS); 3807 } 3808 3809 intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val); 3810 } 3811 3812 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) 3813 { 3814 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3815 u32 tmp; 3816 3817 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); 3818 3819 switch (tmp & PIPEMISC_BPC_MASK) { 3820 case PIPEMISC_BPC_6: 3821 return 18; 3822 case PIPEMISC_BPC_8: 3823 return 24; 3824 case PIPEMISC_BPC_10: 3825 return 30; 3826 /* 3827 * PORT OUTPUT 12 BPC defined for ADLP+. 3828 * 3829 * TODO: 3830 * For previous platforms with DSI interface, bits 5:7 3831 * are used for storing pipe_bpp irrespective of dithering. 3832 * Since the value of 12 BPC is not defined for these bits 3833 * on older platforms, need to find a workaround for 12 BPC 3834 * MIPI DSI HW readout. 3835 */ 3836 case PIPEMISC_BPC_12_ADLP: 3837 if (DISPLAY_VER(dev_priv) > 12) 3838 return 36; 3839 fallthrough; 3840 default: 3841 MISSING_CASE(tmp); 3842 return 0; 3843 } 3844 } 3845 3846 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) 3847 { 3848 /* 3849 * Account for spread spectrum to avoid 3850 * oversubscribing the link. Max center spread 3851 * is 2.5%; use 5% for safety's sake. 3852 */ 3853 u32 bps = target_clock * bpp * 21 / 20; 3854 return DIV_ROUND_UP(bps, link_bw * 8); 3855 } 3856 3857 void intel_get_m_n(struct drm_i915_private *i915, 3858 struct intel_link_m_n *m_n, 3859 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 3860 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 3861 { 3862 m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK; 3863 m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK; 3864 m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK; 3865 m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK; 3866 m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1; 3867 } 3868 3869 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, 3870 enum transcoder transcoder, 3871 struct intel_link_m_n *m_n) 3872 { 3873 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3874 enum pipe pipe = crtc->pipe; 3875 3876 if (DISPLAY_VER(dev_priv) >= 5) 3877 intel_get_m_n(dev_priv, m_n, 3878 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 3879 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 3880 else 3881 intel_get_m_n(dev_priv, m_n, 3882 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 3883 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 3884 } 3885 3886 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, 3887 enum transcoder transcoder, 3888 struct intel_link_m_n *m_n) 3889 { 3890 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3891 3892 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 3893 return; 3894 3895 intel_get_m_n(dev_priv, m_n, 3896 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 3897 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 3898 } 3899 3900 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state, 3901 u32 pos, u32 size) 3902 { 3903 drm_rect_init(&crtc_state->pch_pfit.dst, 3904 pos >> 16, pos & 0xffff, 3905 size >> 16, size & 0xffff); 3906 } 3907 3908 static void skl_get_pfit_config(struct intel_crtc_state *crtc_state) 3909 { 3910 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3911 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3912 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; 3913 int id = -1; 3914 int i; 3915 3916 /* find scaler attached to this pipe */ 3917 for (i = 0; i < crtc->num_scalers; i++) { 3918 u32 ctl, pos, size; 3919 3920 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i)); 3921 if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN) 3922 continue; 3923 3924 id = i; 3925 crtc_state->pch_pfit.enabled = true; 3926 3927 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i)); 3928 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i)); 3929 3930 ilk_get_pfit_pos_size(crtc_state, pos, size); 3931 3932 scaler_state->scalers[i].in_use = true; 3933 break; 3934 } 3935 3936 scaler_state->scaler_id = id; 3937 if (id >= 0) 3938 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); 3939 else 3940 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); 3941 } 3942 3943 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state) 3944 { 3945 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3946 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3947 u32 ctl, pos, size; 3948 3949 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe)); 3950 if ((ctl & PF_ENABLE) == 0) 3951 return; 3952 3953 crtc_state->pch_pfit.enabled = true; 3954 3955 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe)); 3956 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe)); 3957 3958 ilk_get_pfit_pos_size(crtc_state, pos, size); 3959 3960 /* 3961 * We currently do not free assignements of panel fitters on 3962 * ivb/hsw (since we don't use the higher upscaling modes which 3963 * differentiates them) so just WARN about this case for now. 3964 */ 3965 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 7 && 3966 (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe)); 3967 } 3968 3969 static bool ilk_get_pipe_config(struct intel_crtc *crtc, 3970 struct intel_crtc_state *pipe_config) 3971 { 3972 struct drm_device *dev = crtc->base.dev; 3973 struct drm_i915_private *dev_priv = to_i915(dev); 3974 enum intel_display_power_domain power_domain; 3975 intel_wakeref_t wakeref; 3976 u32 tmp; 3977 bool ret; 3978 3979 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3980 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3981 if (!wakeref) 3982 return false; 3983 3984 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3985 pipe_config->shared_dpll = NULL; 3986 3987 ret = false; 3988 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); 3989 if (!(tmp & PIPECONF_ENABLE)) 3990 goto out; 3991 3992 switch (tmp & PIPECONF_BPC_MASK) { 3993 case PIPECONF_BPC_6: 3994 pipe_config->pipe_bpp = 18; 3995 break; 3996 case PIPECONF_BPC_8: 3997 pipe_config->pipe_bpp = 24; 3998 break; 3999 case PIPECONF_BPC_10: 4000 pipe_config->pipe_bpp = 30; 4001 break; 4002 case PIPECONF_BPC_12: 4003 pipe_config->pipe_bpp = 36; 4004 break; 4005 default: 4006 break; 4007 } 4008 4009 if (tmp & PIPECONF_COLOR_RANGE_SELECT) 4010 pipe_config->limited_color_range = true; 4011 4012 switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) { 4013 case PIPECONF_OUTPUT_COLORSPACE_YUV601: 4014 case PIPECONF_OUTPUT_COLORSPACE_YUV709: 4015 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 4016 break; 4017 default: 4018 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 4019 break; 4020 } 4021 4022 pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_ILK, tmp); 4023 4024 pipe_config->csc_mode = intel_de_read(dev_priv, 4025 PIPE_CSC_MODE(crtc->pipe)); 4026 4027 i9xx_get_pipe_color_config(pipe_config); 4028 intel_color_get_config(pipe_config); 4029 4030 pipe_config->pixel_multiplier = 1; 4031 4032 ilk_pch_get_config(pipe_config); 4033 4034 intel_get_transcoder_timings(crtc, pipe_config); 4035 intel_get_pipe_src_size(crtc, pipe_config); 4036 4037 ilk_get_pfit_config(pipe_config); 4038 4039 ret = true; 4040 4041 out: 4042 intel_display_power_put(dev_priv, power_domain, wakeref); 4043 4044 return ret; 4045 } 4046 4047 static u8 bigjoiner_pipes(struct drm_i915_private *i915) 4048 { 4049 if (DISPLAY_VER(i915) >= 12) 4050 return BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D); 4051 else if (DISPLAY_VER(i915) >= 11) 4052 return BIT(PIPE_B) | BIT(PIPE_C); 4053 else 4054 return 0; 4055 } 4056 4057 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv, 4058 enum transcoder cpu_transcoder) 4059 { 4060 enum intel_display_power_domain power_domain; 4061 intel_wakeref_t wakeref; 4062 u32 tmp = 0; 4063 4064 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 4065 4066 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 4067 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 4068 4069 return tmp & TRANS_DDI_FUNC_ENABLE; 4070 } 4071 4072 static u8 enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv) 4073 { 4074 u8 master_pipes = 0, slave_pipes = 0; 4075 struct intel_crtc *crtc; 4076 4077 for_each_intel_crtc(&dev_priv->drm, crtc) { 4078 enum intel_display_power_domain power_domain; 4079 enum pipe pipe = crtc->pipe; 4080 intel_wakeref_t wakeref; 4081 4082 if ((bigjoiner_pipes(dev_priv) & BIT(pipe)) == 0) 4083 continue; 4084 4085 power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe); 4086 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 4087 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 4088 4089 if (!(tmp & BIG_JOINER_ENABLE)) 4090 continue; 4091 4092 if (tmp & MASTER_BIG_JOINER_ENABLE) 4093 master_pipes |= BIT(pipe); 4094 else 4095 slave_pipes |= BIT(pipe); 4096 } 4097 4098 if (DISPLAY_VER(dev_priv) < 13) 4099 continue; 4100 4101 power_domain = POWER_DOMAIN_PIPE(pipe); 4102 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 4103 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 4104 4105 if (tmp & UNCOMPRESSED_JOINER_MASTER) 4106 master_pipes |= BIT(pipe); 4107 if (tmp & UNCOMPRESSED_JOINER_SLAVE) 4108 slave_pipes |= BIT(pipe); 4109 } 4110 } 4111 4112 /* Bigjoiner pipes should always be consecutive master and slave */ 4113 drm_WARN(&dev_priv->drm, slave_pipes != master_pipes << 1, 4114 "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n", 4115 master_pipes, slave_pipes); 4116 4117 return slave_pipes; 4118 } 4119 4120 static u8 hsw_panel_transcoders(struct drm_i915_private *i915) 4121 { 4122 u8 panel_transcoder_mask = BIT(TRANSCODER_EDP); 4123 4124 if (DISPLAY_VER(i915) >= 11) 4125 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); 4126 4127 return panel_transcoder_mask; 4128 } 4129 4130 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) 4131 { 4132 struct drm_device *dev = crtc->base.dev; 4133 struct drm_i915_private *dev_priv = to_i915(dev); 4134 u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv); 4135 enum transcoder cpu_transcoder; 4136 u8 enabled_transcoders = 0; 4137 4138 /* 4139 * XXX: Do intel_display_power_get_if_enabled before reading this (for 4140 * consistency and less surprising code; it's in always on power). 4141 */ 4142 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, 4143 panel_transcoder_mask) { 4144 enum intel_display_power_domain power_domain; 4145 intel_wakeref_t wakeref; 4146 enum pipe trans_pipe; 4147 u32 tmp = 0; 4148 4149 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 4150 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 4151 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 4152 4153 if (!(tmp & TRANS_DDI_FUNC_ENABLE)) 4154 continue; 4155 4156 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 4157 default: 4158 drm_WARN(dev, 1, 4159 "unknown pipe linked to transcoder %s\n", 4160 transcoder_name(cpu_transcoder)); 4161 fallthrough; 4162 case TRANS_DDI_EDP_INPUT_A_ONOFF: 4163 case TRANS_DDI_EDP_INPUT_A_ON: 4164 trans_pipe = PIPE_A; 4165 break; 4166 case TRANS_DDI_EDP_INPUT_B_ONOFF: 4167 trans_pipe = PIPE_B; 4168 break; 4169 case TRANS_DDI_EDP_INPUT_C_ONOFF: 4170 trans_pipe = PIPE_C; 4171 break; 4172 case TRANS_DDI_EDP_INPUT_D_ONOFF: 4173 trans_pipe = PIPE_D; 4174 break; 4175 } 4176 4177 if (trans_pipe == crtc->pipe) 4178 enabled_transcoders |= BIT(cpu_transcoder); 4179 } 4180 4181 /* single pipe or bigjoiner master */ 4182 cpu_transcoder = (enum transcoder) crtc->pipe; 4183 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 4184 enabled_transcoders |= BIT(cpu_transcoder); 4185 4186 /* bigjoiner slave -> consider the master pipe's transcoder as well */ 4187 if (enabled_bigjoiner_pipes(dev_priv) & BIT(crtc->pipe)) { 4188 cpu_transcoder = (enum transcoder) crtc->pipe - 1; 4189 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 4190 enabled_transcoders |= BIT(cpu_transcoder); 4191 } 4192 4193 return enabled_transcoders; 4194 } 4195 4196 static bool has_edp_transcoders(u8 enabled_transcoders) 4197 { 4198 return enabled_transcoders & BIT(TRANSCODER_EDP); 4199 } 4200 4201 static bool has_dsi_transcoders(u8 enabled_transcoders) 4202 { 4203 return enabled_transcoders & (BIT(TRANSCODER_DSI_0) | 4204 BIT(TRANSCODER_DSI_1)); 4205 } 4206 4207 static bool has_pipe_transcoders(u8 enabled_transcoders) 4208 { 4209 return enabled_transcoders & ~(BIT(TRANSCODER_EDP) | 4210 BIT(TRANSCODER_DSI_0) | 4211 BIT(TRANSCODER_DSI_1)); 4212 } 4213 4214 static void assert_enabled_transcoders(struct drm_i915_private *i915, 4215 u8 enabled_transcoders) 4216 { 4217 /* Only one type of transcoder please */ 4218 drm_WARN_ON(&i915->drm, 4219 has_edp_transcoders(enabled_transcoders) + 4220 has_dsi_transcoders(enabled_transcoders) + 4221 has_pipe_transcoders(enabled_transcoders) > 1); 4222 4223 /* Only DSI transcoders can be ganged */ 4224 drm_WARN_ON(&i915->drm, 4225 !has_dsi_transcoders(enabled_transcoders) && 4226 !is_power_of_2(enabled_transcoders)); 4227 } 4228 4229 static bool hsw_get_transcoder_state(struct intel_crtc *crtc, 4230 struct intel_crtc_state *pipe_config, 4231 struct intel_display_power_domain_set *power_domain_set) 4232 { 4233 struct drm_device *dev = crtc->base.dev; 4234 struct drm_i915_private *dev_priv = to_i915(dev); 4235 unsigned long enabled_transcoders; 4236 u32 tmp; 4237 4238 enabled_transcoders = hsw_enabled_transcoders(crtc); 4239 if (!enabled_transcoders) 4240 return false; 4241 4242 assert_enabled_transcoders(dev_priv, enabled_transcoders); 4243 4244 /* 4245 * With the exception of DSI we should only ever have 4246 * a single enabled transcoder. With DSI let's just 4247 * pick the first one. 4248 */ 4249 pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1; 4250 4251 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 4252 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) 4253 return false; 4254 4255 if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) { 4256 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); 4257 4258 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF) 4259 pipe_config->pch_pfit.force_thru = true; 4260 } 4261 4262 tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder)); 4263 4264 return tmp & PIPECONF_ENABLE; 4265 } 4266 4267 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, 4268 struct intel_crtc_state *pipe_config, 4269 struct intel_display_power_domain_set *power_domain_set) 4270 { 4271 struct drm_device *dev = crtc->base.dev; 4272 struct drm_i915_private *dev_priv = to_i915(dev); 4273 enum transcoder cpu_transcoder; 4274 enum port port; 4275 u32 tmp; 4276 4277 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { 4278 if (port == PORT_A) 4279 cpu_transcoder = TRANSCODER_DSI_A; 4280 else 4281 cpu_transcoder = TRANSCODER_DSI_C; 4282 4283 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 4284 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) 4285 continue; 4286 4287 /* 4288 * The PLL needs to be enabled with a valid divider 4289 * configuration, otherwise accessing DSI registers will hang 4290 * the machine. See BSpec North Display Engine 4291 * registers/MIPI[BXT]. We can break out here early, since we 4292 * need the same DSI PLL to be enabled for both DSI ports. 4293 */ 4294 if (!bxt_dsi_pll_is_enabled(dev_priv)) 4295 break; 4296 4297 /* XXX: this works for video mode only */ 4298 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); 4299 if (!(tmp & DPI_ENABLE)) 4300 continue; 4301 4302 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 4303 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) 4304 continue; 4305 4306 pipe_config->cpu_transcoder = cpu_transcoder; 4307 break; 4308 } 4309 4310 return transcoder_is_dsi(pipe_config->cpu_transcoder); 4311 } 4312 4313 static bool hsw_get_pipe_config(struct intel_crtc *crtc, 4314 struct intel_crtc_state *pipe_config) 4315 { 4316 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4317 struct intel_display_power_domain_set power_domain_set = { }; 4318 bool active; 4319 u32 tmp; 4320 4321 if (!intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set, 4322 POWER_DOMAIN_PIPE(crtc->pipe))) 4323 return false; 4324 4325 pipe_config->shared_dpll = NULL; 4326 4327 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_set); 4328 4329 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 4330 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_set)) { 4331 drm_WARN_ON(&dev_priv->drm, active); 4332 active = true; 4333 } 4334 4335 if (!active) 4336 goto out; 4337 4338 intel_dsc_get_config(pipe_config); 4339 if (DISPLAY_VER(dev_priv) >= 13 && !pipe_config->dsc.compression_enable) 4340 intel_uncompressed_joiner_get_config(pipe_config); 4341 4342 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || 4343 DISPLAY_VER(dev_priv) >= 11) 4344 intel_get_transcoder_timings(crtc, pipe_config); 4345 4346 if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder)) 4347 intel_vrr_get_config(crtc, pipe_config); 4348 4349 intel_get_pipe_src_size(crtc, pipe_config); 4350 4351 if (IS_HASWELL(dev_priv)) { 4352 u32 tmp = intel_de_read(dev_priv, 4353 PIPECONF(pipe_config->cpu_transcoder)); 4354 4355 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW) 4356 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 4357 else 4358 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 4359 } else { 4360 pipe_config->output_format = 4361 bdw_get_pipemisc_output_format(crtc); 4362 } 4363 4364 pipe_config->gamma_mode = intel_de_read(dev_priv, 4365 GAMMA_MODE(crtc->pipe)); 4366 4367 pipe_config->csc_mode = intel_de_read(dev_priv, 4368 PIPE_CSC_MODE(crtc->pipe)); 4369 4370 if (DISPLAY_VER(dev_priv) >= 9) { 4371 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe)); 4372 4373 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE) 4374 pipe_config->gamma_enable = true; 4375 4376 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE) 4377 pipe_config->csc_enable = true; 4378 } else { 4379 i9xx_get_pipe_color_config(pipe_config); 4380 } 4381 4382 intel_color_get_config(pipe_config); 4383 4384 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe)); 4385 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); 4386 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 4387 pipe_config->ips_linetime = 4388 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); 4389 4390 if (intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set, 4391 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) { 4392 if (DISPLAY_VER(dev_priv) >= 9) 4393 skl_get_pfit_config(pipe_config); 4394 else 4395 ilk_get_pfit_config(pipe_config); 4396 } 4397 4398 if (hsw_crtc_supports_ips(crtc)) { 4399 if (IS_HASWELL(dev_priv)) 4400 pipe_config->ips_enabled = intel_de_read(dev_priv, 4401 IPS_CTL) & IPS_ENABLE; 4402 else { 4403 /* 4404 * We cannot readout IPS state on broadwell, set to 4405 * true so we can set it to a defined state on first 4406 * commit. 4407 */ 4408 pipe_config->ips_enabled = true; 4409 } 4410 } 4411 4412 if (pipe_config->cpu_transcoder != TRANSCODER_EDP && 4413 !transcoder_is_dsi(pipe_config->cpu_transcoder)) { 4414 pipe_config->pixel_multiplier = 4415 intel_de_read(dev_priv, 4416 PIPE_MULT(pipe_config->cpu_transcoder)) + 1; 4417 } else { 4418 pipe_config->pixel_multiplier = 1; 4419 } 4420 4421 out: 4422 intel_display_power_put_all_in_set(dev_priv, &power_domain_set); 4423 4424 return active; 4425 } 4426 4427 static bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state) 4428 { 4429 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4430 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4431 4432 if (!i915->display->get_pipe_config(crtc, crtc_state)) 4433 return false; 4434 4435 crtc_state->hw.active = true; 4436 4437 intel_crtc_readout_derived_state(crtc_state); 4438 4439 return true; 4440 } 4441 4442 /* VESA 640x480x72Hz mode to set on the pipe */ 4443 static const struct drm_display_mode load_detect_mode = { 4444 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, 4445 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 4446 }; 4447 4448 static int intel_modeset_disable_planes(struct drm_atomic_state *state, 4449 struct drm_crtc *crtc) 4450 { 4451 struct drm_plane *plane; 4452 struct drm_plane_state *plane_state; 4453 int ret, i; 4454 4455 ret = drm_atomic_add_affected_planes(state, crtc); 4456 if (ret) 4457 return ret; 4458 4459 for_each_new_plane_in_state(state, plane, plane_state, i) { 4460 if (plane_state->crtc != crtc) 4461 continue; 4462 4463 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL); 4464 if (ret) 4465 return ret; 4466 4467 drm_atomic_set_fb_for_plane(plane_state, NULL); 4468 } 4469 4470 return 0; 4471 } 4472 4473 int intel_get_load_detect_pipe(struct drm_connector *connector, 4474 struct intel_load_detect_pipe *old, 4475 struct drm_modeset_acquire_ctx *ctx) 4476 { 4477 struct intel_encoder *encoder = 4478 intel_attached_encoder(to_intel_connector(connector)); 4479 struct intel_crtc *possible_crtc; 4480 struct intel_crtc *crtc = NULL; 4481 struct drm_device *dev = encoder->base.dev; 4482 struct drm_i915_private *dev_priv = to_i915(dev); 4483 struct drm_mode_config *config = &dev->mode_config; 4484 struct drm_atomic_state *state = NULL, *restore_state = NULL; 4485 struct drm_connector_state *connector_state; 4486 struct intel_crtc_state *crtc_state; 4487 int ret; 4488 4489 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 4490 connector->base.id, connector->name, 4491 encoder->base.base.id, encoder->base.name); 4492 4493 old->restore_state = NULL; 4494 4495 drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex)); 4496 4497 /* 4498 * Algorithm gets a little messy: 4499 * 4500 * - if the connector already has an assigned crtc, use it (but make 4501 * sure it's on first) 4502 * 4503 * - try to find the first unused crtc that can drive this connector, 4504 * and use that if we find one 4505 */ 4506 4507 /* See if we already have a CRTC for this connector */ 4508 if (connector->state->crtc) { 4509 crtc = to_intel_crtc(connector->state->crtc); 4510 4511 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4512 if (ret) 4513 goto fail; 4514 4515 /* Make sure the crtc and connector are running */ 4516 goto found; 4517 } 4518 4519 /* Find an unused one (if possible) */ 4520 for_each_intel_crtc(dev, possible_crtc) { 4521 if (!(encoder->base.possible_crtcs & 4522 drm_crtc_mask(&possible_crtc->base))) 4523 continue; 4524 4525 ret = drm_modeset_lock(&possible_crtc->base.mutex, ctx); 4526 if (ret) 4527 goto fail; 4528 4529 if (possible_crtc->base.state->enable) { 4530 drm_modeset_unlock(&possible_crtc->base.mutex); 4531 continue; 4532 } 4533 4534 crtc = possible_crtc; 4535 break; 4536 } 4537 4538 /* 4539 * If we didn't find an unused CRTC, don't use any. 4540 */ 4541 if (!crtc) { 4542 drm_dbg_kms(&dev_priv->drm, 4543 "no pipe available for load-detect\n"); 4544 ret = -ENODEV; 4545 goto fail; 4546 } 4547 4548 found: 4549 state = drm_atomic_state_alloc(dev); 4550 restore_state = drm_atomic_state_alloc(dev); 4551 if (!state || !restore_state) { 4552 ret = -ENOMEM; 4553 goto fail; 4554 } 4555 4556 state->acquire_ctx = ctx; 4557 restore_state->acquire_ctx = ctx; 4558 4559 connector_state = drm_atomic_get_connector_state(state, connector); 4560 if (IS_ERR(connector_state)) { 4561 ret = PTR_ERR(connector_state); 4562 goto fail; 4563 } 4564 4565 ret = drm_atomic_set_crtc_for_connector(connector_state, &crtc->base); 4566 if (ret) 4567 goto fail; 4568 4569 crtc_state = intel_atomic_get_crtc_state(state, crtc); 4570 if (IS_ERR(crtc_state)) { 4571 ret = PTR_ERR(crtc_state); 4572 goto fail; 4573 } 4574 4575 crtc_state->uapi.active = true; 4576 4577 ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi, 4578 &load_detect_mode); 4579 if (ret) 4580 goto fail; 4581 4582 ret = intel_modeset_disable_planes(state, &crtc->base); 4583 if (ret) 4584 goto fail; 4585 4586 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); 4587 if (!ret) 4588 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, &crtc->base)); 4589 if (!ret) 4590 ret = drm_atomic_add_affected_planes(restore_state, &crtc->base); 4591 if (ret) { 4592 drm_dbg_kms(&dev_priv->drm, 4593 "Failed to create a copy of old state to restore: %i\n", 4594 ret); 4595 goto fail; 4596 } 4597 4598 ret = drm_atomic_commit(state); 4599 if (ret) { 4600 drm_dbg_kms(&dev_priv->drm, 4601 "failed to set mode on load-detect pipe\n"); 4602 goto fail; 4603 } 4604 4605 old->restore_state = restore_state; 4606 drm_atomic_state_put(state); 4607 4608 /* let the connector get through one full cycle before testing */ 4609 intel_crtc_wait_for_next_vblank(crtc); 4610 4611 return true; 4612 4613 fail: 4614 if (state) { 4615 drm_atomic_state_put(state); 4616 state = NULL; 4617 } 4618 if (restore_state) { 4619 drm_atomic_state_put(restore_state); 4620 restore_state = NULL; 4621 } 4622 4623 if (ret == -EDEADLK) 4624 return ret; 4625 4626 return false; 4627 } 4628 4629 void intel_release_load_detect_pipe(struct drm_connector *connector, 4630 struct intel_load_detect_pipe *old, 4631 struct drm_modeset_acquire_ctx *ctx) 4632 { 4633 struct intel_encoder *intel_encoder = 4634 intel_attached_encoder(to_intel_connector(connector)); 4635 struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev); 4636 struct drm_encoder *encoder = &intel_encoder->base; 4637 struct drm_atomic_state *state = old->restore_state; 4638 int ret; 4639 4640 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 4641 connector->base.id, connector->name, 4642 encoder->base.id, encoder->name); 4643 4644 if (!state) 4645 return; 4646 4647 ret = drm_atomic_helper_commit_duplicated_state(state, ctx); 4648 if (ret) 4649 drm_dbg_kms(&i915->drm, 4650 "Couldn't release load detect pipe: %i\n", ret); 4651 drm_atomic_state_put(state); 4652 } 4653 4654 static int i9xx_pll_refclk(struct drm_device *dev, 4655 const struct intel_crtc_state *pipe_config) 4656 { 4657 struct drm_i915_private *dev_priv = to_i915(dev); 4658 u32 dpll = pipe_config->dpll_hw_state.dpll; 4659 4660 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) 4661 return dev_priv->vbt.lvds_ssc_freq; 4662 else if (HAS_PCH_SPLIT(dev_priv)) 4663 return 120000; 4664 else if (DISPLAY_VER(dev_priv) != 2) 4665 return 96000; 4666 else 4667 return 48000; 4668 } 4669 4670 /* Returns the clock of the currently programmed mode of the given pipe. */ 4671 void i9xx_crtc_clock_get(struct intel_crtc *crtc, 4672 struct intel_crtc_state *pipe_config) 4673 { 4674 struct drm_device *dev = crtc->base.dev; 4675 struct drm_i915_private *dev_priv = to_i915(dev); 4676 u32 dpll = pipe_config->dpll_hw_state.dpll; 4677 u32 fp; 4678 struct dpll clock; 4679 int port_clock; 4680 int refclk = i9xx_pll_refclk(dev, pipe_config); 4681 4682 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 4683 fp = pipe_config->dpll_hw_state.fp0; 4684 else 4685 fp = pipe_config->dpll_hw_state.fp1; 4686 4687 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 4688 if (IS_PINEVIEW(dev_priv)) { 4689 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; 4690 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; 4691 } else { 4692 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 4693 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 4694 } 4695 4696 if (DISPLAY_VER(dev_priv) != 2) { 4697 if (IS_PINEVIEW(dev_priv)) 4698 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> 4699 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); 4700 else 4701 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> 4702 DPLL_FPA01_P1_POST_DIV_SHIFT); 4703 4704 switch (dpll & DPLL_MODE_MASK) { 4705 case DPLLB_MODE_DAC_SERIAL: 4706 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 4707 5 : 10; 4708 break; 4709 case DPLLB_MODE_LVDS: 4710 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 4711 7 : 14; 4712 break; 4713 default: 4714 drm_dbg_kms(&dev_priv->drm, 4715 "Unknown DPLL mode %08x in programmed " 4716 "mode\n", (int)(dpll & DPLL_MODE_MASK)); 4717 return; 4718 } 4719 4720 if (IS_PINEVIEW(dev_priv)) 4721 port_clock = pnv_calc_dpll_params(refclk, &clock); 4722 else 4723 port_clock = i9xx_calc_dpll_params(refclk, &clock); 4724 } else { 4725 enum pipe lvds_pipe; 4726 4727 if (IS_I85X(dev_priv) && 4728 intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) && 4729 lvds_pipe == crtc->pipe) { 4730 u32 lvds = intel_de_read(dev_priv, LVDS); 4731 4732 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 4733 DPLL_FPA01_P1_POST_DIV_SHIFT); 4734 4735 if (lvds & LVDS_CLKB_POWER_UP) 4736 clock.p2 = 7; 4737 else 4738 clock.p2 = 14; 4739 } else { 4740 if (dpll & PLL_P1_DIVIDE_BY_TWO) 4741 clock.p1 = 2; 4742 else { 4743 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 4744 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 4745 } 4746 if (dpll & PLL_P2_DIVIDE_BY_4) 4747 clock.p2 = 4; 4748 else 4749 clock.p2 = 2; 4750 } 4751 4752 port_clock = i9xx_calc_dpll_params(refclk, &clock); 4753 } 4754 4755 /* 4756 * This value includes pixel_multiplier. We will use 4757 * port_clock to compute adjusted_mode.crtc_clock in the 4758 * encoder's get_config() function. 4759 */ 4760 pipe_config->port_clock = port_clock; 4761 } 4762 4763 int intel_dotclock_calculate(int link_freq, 4764 const struct intel_link_m_n *m_n) 4765 { 4766 /* 4767 * The calculation for the data clock is: 4768 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp 4769 * But we want to avoid losing precison if possible, so: 4770 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) 4771 * 4772 * and the link clock is simpler: 4773 * link_clock = (m * link_clock) / n 4774 */ 4775 4776 if (!m_n->link_n) 4777 return 0; 4778 4779 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n); 4780 } 4781 4782 /* Returns the currently programmed mode of the given encoder. */ 4783 struct drm_display_mode * 4784 intel_encoder_current_mode(struct intel_encoder *encoder) 4785 { 4786 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4787 struct intel_crtc_state *crtc_state; 4788 struct drm_display_mode *mode; 4789 struct intel_crtc *crtc; 4790 enum pipe pipe; 4791 4792 if (!encoder->get_hw_state(encoder, &pipe)) 4793 return NULL; 4794 4795 crtc = intel_crtc_for_pipe(dev_priv, pipe); 4796 4797 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 4798 if (!mode) 4799 return NULL; 4800 4801 crtc_state = intel_crtc_state_alloc(crtc); 4802 if (!crtc_state) { 4803 kfree(mode); 4804 return NULL; 4805 } 4806 4807 if (!intel_crtc_get_pipe_config(crtc_state)) { 4808 kfree(crtc_state); 4809 kfree(mode); 4810 return NULL; 4811 } 4812 4813 intel_encoder_get_config(encoder, crtc_state); 4814 4815 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode); 4816 4817 kfree(crtc_state); 4818 4819 return mode; 4820 } 4821 4822 /** 4823 * intel_wm_need_update - Check whether watermarks need updating 4824 * @cur: current plane state 4825 * @new: new plane state 4826 * 4827 * Check current plane state versus the new one to determine whether 4828 * watermarks need to be recalculated. 4829 * 4830 * Returns true or false. 4831 */ 4832 static bool intel_wm_need_update(const struct intel_plane_state *cur, 4833 struct intel_plane_state *new) 4834 { 4835 /* Update watermarks on tiling or size changes. */ 4836 if (new->uapi.visible != cur->uapi.visible) 4837 return true; 4838 4839 if (!cur->hw.fb || !new->hw.fb) 4840 return false; 4841 4842 if (cur->hw.fb->modifier != new->hw.fb->modifier || 4843 cur->hw.rotation != new->hw.rotation || 4844 drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) || 4845 drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) || 4846 drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) || 4847 drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst)) 4848 return true; 4849 4850 return false; 4851 } 4852 4853 static bool needs_scaling(const struct intel_plane_state *state) 4854 { 4855 int src_w = drm_rect_width(&state->uapi.src) >> 16; 4856 int src_h = drm_rect_height(&state->uapi.src) >> 16; 4857 int dst_w = drm_rect_width(&state->uapi.dst); 4858 int dst_h = drm_rect_height(&state->uapi.dst); 4859 4860 return (src_w != dst_w || src_h != dst_h); 4861 } 4862 4863 static bool intel_plane_do_async_flip(struct intel_plane *plane, 4864 const struct intel_crtc_state *old_crtc_state, 4865 const struct intel_crtc_state *new_crtc_state) 4866 { 4867 struct drm_i915_private *i915 = to_i915(plane->base.dev); 4868 4869 if (!plane->async_flip) 4870 return false; 4871 4872 if (!new_crtc_state->uapi.async_flip) 4873 return false; 4874 4875 /* 4876 * In platforms after DISPLAY13, we might need to override 4877 * first async flip in order to change watermark levels 4878 * as part of optimization. 4879 * So for those, we are checking if this is a first async flip. 4880 * For platforms earlier than DISPLAY13 we always do async flip. 4881 */ 4882 return DISPLAY_VER(i915) < 13 || old_crtc_state->uapi.async_flip; 4883 } 4884 4885 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state, 4886 struct intel_crtc_state *new_crtc_state, 4887 const struct intel_plane_state *old_plane_state, 4888 struct intel_plane_state *new_plane_state) 4889 { 4890 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 4891 struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane); 4892 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4893 bool mode_changed = intel_crtc_needs_modeset(new_crtc_state); 4894 bool was_crtc_enabled = old_crtc_state->hw.active; 4895 bool is_crtc_enabled = new_crtc_state->hw.active; 4896 bool turn_off, turn_on, visible, was_visible; 4897 int ret; 4898 4899 if (DISPLAY_VER(dev_priv) >= 9 && plane->id != PLANE_CURSOR) { 4900 ret = skl_update_scaler_plane(new_crtc_state, new_plane_state); 4901 if (ret) 4902 return ret; 4903 } 4904 4905 was_visible = old_plane_state->uapi.visible; 4906 visible = new_plane_state->uapi.visible; 4907 4908 if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible)) 4909 was_visible = false; 4910 4911 /* 4912 * Visibility is calculated as if the crtc was on, but 4913 * after scaler setup everything depends on it being off 4914 * when the crtc isn't active. 4915 * 4916 * FIXME this is wrong for watermarks. Watermarks should also 4917 * be computed as if the pipe would be active. Perhaps move 4918 * per-plane wm computation to the .check_plane() hook, and 4919 * only combine the results from all planes in the current place? 4920 */ 4921 if (!is_crtc_enabled) { 4922 intel_plane_set_invisible(new_crtc_state, new_plane_state); 4923 visible = false; 4924 } 4925 4926 if (!was_visible && !visible) 4927 return 0; 4928 4929 turn_off = was_visible && (!visible || mode_changed); 4930 turn_on = visible && (!was_visible || mode_changed); 4931 4932 drm_dbg_atomic(&dev_priv->drm, 4933 "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n", 4934 crtc->base.base.id, crtc->base.name, 4935 plane->base.base.id, plane->base.name, 4936 was_visible, visible, 4937 turn_off, turn_on, mode_changed); 4938 4939 if (turn_on) { 4940 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) 4941 new_crtc_state->update_wm_pre = true; 4942 4943 /* must disable cxsr around plane enable/disable */ 4944 if (plane->id != PLANE_CURSOR) 4945 new_crtc_state->disable_cxsr = true; 4946 } else if (turn_off) { 4947 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) 4948 new_crtc_state->update_wm_post = true; 4949 4950 /* must disable cxsr around plane enable/disable */ 4951 if (plane->id != PLANE_CURSOR) 4952 new_crtc_state->disable_cxsr = true; 4953 } else if (intel_wm_need_update(old_plane_state, new_plane_state)) { 4954 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) { 4955 /* FIXME bollocks */ 4956 new_crtc_state->update_wm_pre = true; 4957 new_crtc_state->update_wm_post = true; 4958 } 4959 } 4960 4961 if (visible || was_visible) 4962 new_crtc_state->fb_bits |= plane->frontbuffer_bit; 4963 4964 /* 4965 * ILK/SNB DVSACNTR/Sprite Enable 4966 * IVB SPR_CTL/Sprite Enable 4967 * "When in Self Refresh Big FIFO mode, a write to enable the 4968 * plane will be internally buffered and delayed while Big FIFO 4969 * mode is exiting." 4970 * 4971 * Which means that enabling the sprite can take an extra frame 4972 * when we start in big FIFO mode (LP1+). Thus we need to drop 4973 * down to LP0 and wait for vblank in order to make sure the 4974 * sprite gets enabled on the next vblank after the register write. 4975 * Doing otherwise would risk enabling the sprite one frame after 4976 * we've already signalled flip completion. We can resume LP1+ 4977 * once the sprite has been enabled. 4978 * 4979 * 4980 * WaCxSRDisabledForSpriteScaling:ivb 4981 * IVB SPR_SCALE/Scaling Enable 4982 * "Low Power watermarks must be disabled for at least one 4983 * frame before enabling sprite scaling, and kept disabled 4984 * until sprite scaling is disabled." 4985 * 4986 * ILK/SNB DVSASCALE/Scaling Enable 4987 * "When in Self Refresh Big FIFO mode, scaling enable will be 4988 * masked off while Big FIFO mode is exiting." 4989 * 4990 * Despite the w/a only being listed for IVB we assume that 4991 * the ILK/SNB note has similar ramifications, hence we apply 4992 * the w/a on all three platforms. 4993 * 4994 * With experimental results seems this is needed also for primary 4995 * plane, not only sprite plane. 4996 */ 4997 if (plane->id != PLANE_CURSOR && 4998 (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv) || 4999 IS_IVYBRIDGE(dev_priv)) && 5000 (turn_on || (!needs_scaling(old_plane_state) && 5001 needs_scaling(new_plane_state)))) 5002 new_crtc_state->disable_lp_wm = true; 5003 5004 if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state)) 5005 new_plane_state->do_async_flip = true; 5006 5007 return 0; 5008 } 5009 5010 static bool encoders_cloneable(const struct intel_encoder *a, 5011 const struct intel_encoder *b) 5012 { 5013 /* masks could be asymmetric, so check both ways */ 5014 return a == b || (a->cloneable & (1 << b->type) && 5015 b->cloneable & (1 << a->type)); 5016 } 5017 5018 static bool check_single_encoder_cloning(struct intel_atomic_state *state, 5019 struct intel_crtc *crtc, 5020 struct intel_encoder *encoder) 5021 { 5022 struct intel_encoder *source_encoder; 5023 struct drm_connector *connector; 5024 struct drm_connector_state *connector_state; 5025 int i; 5026 5027 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5028 if (connector_state->crtc != &crtc->base) 5029 continue; 5030 5031 source_encoder = 5032 to_intel_encoder(connector_state->best_encoder); 5033 if (!encoders_cloneable(encoder, source_encoder)) 5034 return false; 5035 } 5036 5037 return true; 5038 } 5039 5040 static int icl_add_linked_planes(struct intel_atomic_state *state) 5041 { 5042 struct intel_plane *plane, *linked; 5043 struct intel_plane_state *plane_state, *linked_plane_state; 5044 int i; 5045 5046 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 5047 linked = plane_state->planar_linked_plane; 5048 5049 if (!linked) 5050 continue; 5051 5052 linked_plane_state = intel_atomic_get_plane_state(state, linked); 5053 if (IS_ERR(linked_plane_state)) 5054 return PTR_ERR(linked_plane_state); 5055 5056 drm_WARN_ON(state->base.dev, 5057 linked_plane_state->planar_linked_plane != plane); 5058 drm_WARN_ON(state->base.dev, 5059 linked_plane_state->planar_slave == plane_state->planar_slave); 5060 } 5061 5062 return 0; 5063 } 5064 5065 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state) 5066 { 5067 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 5068 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5069 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 5070 struct intel_plane *plane, *linked; 5071 struct intel_plane_state *plane_state; 5072 int i; 5073 5074 if (DISPLAY_VER(dev_priv) < 11) 5075 return 0; 5076 5077 /* 5078 * Destroy all old plane links and make the slave plane invisible 5079 * in the crtc_state->active_planes mask. 5080 */ 5081 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 5082 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane) 5083 continue; 5084 5085 plane_state->planar_linked_plane = NULL; 5086 if (plane_state->planar_slave && !plane_state->uapi.visible) { 5087 crtc_state->enabled_planes &= ~BIT(plane->id); 5088 crtc_state->active_planes &= ~BIT(plane->id); 5089 crtc_state->update_planes |= BIT(plane->id); 5090 } 5091 5092 plane_state->planar_slave = false; 5093 } 5094 5095 if (!crtc_state->nv12_planes) 5096 return 0; 5097 5098 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 5099 struct intel_plane_state *linked_state = NULL; 5100 5101 if (plane->pipe != crtc->pipe || 5102 !(crtc_state->nv12_planes & BIT(plane->id))) 5103 continue; 5104 5105 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) { 5106 if (!icl_is_nv12_y_plane(dev_priv, linked->id)) 5107 continue; 5108 5109 if (crtc_state->active_planes & BIT(linked->id)) 5110 continue; 5111 5112 linked_state = intel_atomic_get_plane_state(state, linked); 5113 if (IS_ERR(linked_state)) 5114 return PTR_ERR(linked_state); 5115 5116 break; 5117 } 5118 5119 if (!linked_state) { 5120 drm_dbg_kms(&dev_priv->drm, 5121 "Need %d free Y planes for planar YUV\n", 5122 hweight8(crtc_state->nv12_planes)); 5123 5124 return -EINVAL; 5125 } 5126 5127 plane_state->planar_linked_plane = linked; 5128 5129 linked_state->planar_slave = true; 5130 linked_state->planar_linked_plane = plane; 5131 crtc_state->enabled_planes |= BIT(linked->id); 5132 crtc_state->active_planes |= BIT(linked->id); 5133 crtc_state->update_planes |= BIT(linked->id); 5134 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n", 5135 linked->base.name, plane->base.name); 5136 5137 /* Copy parameters to slave plane */ 5138 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE; 5139 linked_state->color_ctl = plane_state->color_ctl; 5140 linked_state->view = plane_state->view; 5141 linked_state->decrypt = plane_state->decrypt; 5142 5143 intel_plane_copy_hw_state(linked_state, plane_state); 5144 linked_state->uapi.src = plane_state->uapi.src; 5145 linked_state->uapi.dst = plane_state->uapi.dst; 5146 5147 if (icl_is_hdr_plane(dev_priv, plane->id)) { 5148 if (linked->id == PLANE_SPRITE5) 5149 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL; 5150 else if (linked->id == PLANE_SPRITE4) 5151 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL; 5152 else if (linked->id == PLANE_SPRITE3) 5153 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL; 5154 else if (linked->id == PLANE_SPRITE2) 5155 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL; 5156 else 5157 MISSING_CASE(linked->id); 5158 } 5159 } 5160 5161 return 0; 5162 } 5163 5164 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state) 5165 { 5166 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 5167 struct intel_atomic_state *state = 5168 to_intel_atomic_state(new_crtc_state->uapi.state); 5169 const struct intel_crtc_state *old_crtc_state = 5170 intel_atomic_get_old_crtc_state(state, crtc); 5171 5172 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes; 5173 } 5174 5175 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) 5176 { 5177 const struct drm_display_mode *pipe_mode = 5178 &crtc_state->hw.pipe_mode; 5179 int linetime_wm; 5180 5181 if (!crtc_state->hw.enable) 5182 return 0; 5183 5184 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 5185 pipe_mode->crtc_clock); 5186 5187 return min(linetime_wm, 0x1ff); 5188 } 5189 5190 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, 5191 const struct intel_cdclk_state *cdclk_state) 5192 { 5193 const struct drm_display_mode *pipe_mode = 5194 &crtc_state->hw.pipe_mode; 5195 int linetime_wm; 5196 5197 if (!crtc_state->hw.enable) 5198 return 0; 5199 5200 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 5201 cdclk_state->logical.cdclk); 5202 5203 return min(linetime_wm, 0x1ff); 5204 } 5205 5206 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) 5207 { 5208 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 5209 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5210 const struct drm_display_mode *pipe_mode = 5211 &crtc_state->hw.pipe_mode; 5212 int linetime_wm; 5213 5214 if (!crtc_state->hw.enable) 5215 return 0; 5216 5217 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8, 5218 crtc_state->pixel_rate); 5219 5220 /* Display WA #1135: BXT:ALL GLK:ALL */ 5221 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 5222 dev_priv->ipc_enabled) 5223 linetime_wm /= 2; 5224 5225 return min(linetime_wm, 0x1ff); 5226 } 5227 5228 static int hsw_compute_linetime_wm(struct intel_atomic_state *state, 5229 struct intel_crtc *crtc) 5230 { 5231 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5232 struct intel_crtc_state *crtc_state = 5233 intel_atomic_get_new_crtc_state(state, crtc); 5234 const struct intel_cdclk_state *cdclk_state; 5235 5236 if (DISPLAY_VER(dev_priv) >= 9) 5237 crtc_state->linetime = skl_linetime_wm(crtc_state); 5238 else 5239 crtc_state->linetime = hsw_linetime_wm(crtc_state); 5240 5241 if (!hsw_crtc_supports_ips(crtc)) 5242 return 0; 5243 5244 cdclk_state = intel_atomic_get_cdclk_state(state); 5245 if (IS_ERR(cdclk_state)) 5246 return PTR_ERR(cdclk_state); 5247 5248 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state, 5249 cdclk_state); 5250 5251 return 0; 5252 } 5253 5254 static int intel_crtc_atomic_check(struct intel_atomic_state *state, 5255 struct intel_crtc *crtc) 5256 { 5257 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5258 struct intel_crtc_state *crtc_state = 5259 intel_atomic_get_new_crtc_state(state, crtc); 5260 bool mode_changed = intel_crtc_needs_modeset(crtc_state); 5261 int ret; 5262 5263 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) && 5264 mode_changed && !crtc_state->hw.active) 5265 crtc_state->update_wm_post = true; 5266 5267 if (mode_changed && crtc_state->hw.enable && 5268 !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) { 5269 ret = dev_priv->dpll_funcs->crtc_compute_clock(crtc_state); 5270 if (ret) 5271 return ret; 5272 } 5273 5274 /* 5275 * May need to update pipe gamma enable bits 5276 * when C8 planes are getting enabled/disabled. 5277 */ 5278 if (c8_planes_changed(crtc_state)) 5279 crtc_state->uapi.color_mgmt_changed = true; 5280 5281 if (mode_changed || crtc_state->update_pipe || 5282 crtc_state->uapi.color_mgmt_changed) { 5283 ret = intel_color_check(crtc_state); 5284 if (ret) 5285 return ret; 5286 } 5287 5288 ret = intel_compute_pipe_wm(state, crtc); 5289 if (ret) { 5290 drm_dbg_kms(&dev_priv->drm, 5291 "Target pipe watermarks are invalid\n"); 5292 return ret; 5293 } 5294 5295 /* 5296 * Calculate 'intermediate' watermarks that satisfy both the 5297 * old state and the new state. We can program these 5298 * immediately. 5299 */ 5300 ret = intel_compute_intermediate_wm(state, crtc); 5301 if (ret) { 5302 drm_dbg_kms(&dev_priv->drm, 5303 "No valid intermediate pipe watermarks are possible\n"); 5304 return ret; 5305 } 5306 5307 if (DISPLAY_VER(dev_priv) >= 9) { 5308 if (mode_changed || crtc_state->update_pipe) { 5309 ret = skl_update_scaler_crtc(crtc_state); 5310 if (ret) 5311 return ret; 5312 } 5313 5314 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state); 5315 if (ret) 5316 return ret; 5317 } 5318 5319 if (HAS_IPS(dev_priv)) { 5320 ret = hsw_compute_ips_config(crtc_state); 5321 if (ret) 5322 return ret; 5323 } 5324 5325 if (DISPLAY_VER(dev_priv) >= 9 || 5326 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 5327 ret = hsw_compute_linetime_wm(state, crtc); 5328 if (ret) 5329 return ret; 5330 5331 } 5332 5333 ret = intel_psr2_sel_fetch_update(state, crtc); 5334 if (ret) 5335 return ret; 5336 5337 return 0; 5338 } 5339 5340 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) 5341 { 5342 struct intel_connector *connector; 5343 struct drm_connector_list_iter conn_iter; 5344 5345 drm_connector_list_iter_begin(dev, &conn_iter); 5346 for_each_intel_connector_iter(connector, &conn_iter) { 5347 struct drm_connector_state *conn_state = connector->base.state; 5348 struct intel_encoder *encoder = 5349 to_intel_encoder(connector->base.encoder); 5350 5351 if (conn_state->crtc) 5352 drm_connector_put(&connector->base); 5353 5354 if (encoder) { 5355 struct intel_crtc *crtc = 5356 to_intel_crtc(encoder->base.crtc); 5357 const struct intel_crtc_state *crtc_state = 5358 to_intel_crtc_state(crtc->base.state); 5359 5360 conn_state->best_encoder = &encoder->base; 5361 conn_state->crtc = &crtc->base; 5362 conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3; 5363 5364 drm_connector_get(&connector->base); 5365 } else { 5366 conn_state->best_encoder = NULL; 5367 conn_state->crtc = NULL; 5368 } 5369 } 5370 drm_connector_list_iter_end(&conn_iter); 5371 } 5372 5373 static int 5374 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state, 5375 struct intel_crtc_state *pipe_config) 5376 { 5377 struct drm_connector *connector = conn_state->connector; 5378 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); 5379 const struct drm_display_info *info = &connector->display_info; 5380 int bpp; 5381 5382 switch (conn_state->max_bpc) { 5383 case 6 ... 7: 5384 bpp = 6 * 3; 5385 break; 5386 case 8 ... 9: 5387 bpp = 8 * 3; 5388 break; 5389 case 10 ... 11: 5390 bpp = 10 * 3; 5391 break; 5392 case 12 ... 16: 5393 bpp = 12 * 3; 5394 break; 5395 default: 5396 MISSING_CASE(conn_state->max_bpc); 5397 return -EINVAL; 5398 } 5399 5400 if (bpp < pipe_config->pipe_bpp) { 5401 drm_dbg_kms(&i915->drm, 5402 "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of " 5403 "EDID bpp %d, requested bpp %d, max platform bpp %d\n", 5404 connector->base.id, connector->name, 5405 bpp, 3 * info->bpc, 5406 3 * conn_state->max_requested_bpc, 5407 pipe_config->pipe_bpp); 5408 5409 pipe_config->pipe_bpp = bpp; 5410 } 5411 5412 return 0; 5413 } 5414 5415 static int 5416 compute_baseline_pipe_bpp(struct intel_crtc *crtc, 5417 struct intel_crtc_state *pipe_config) 5418 { 5419 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5420 struct drm_atomic_state *state = pipe_config->uapi.state; 5421 struct drm_connector *connector; 5422 struct drm_connector_state *connector_state; 5423 int bpp, i; 5424 5425 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 5426 IS_CHERRYVIEW(dev_priv))) 5427 bpp = 10*3; 5428 else if (DISPLAY_VER(dev_priv) >= 5) 5429 bpp = 12*3; 5430 else 5431 bpp = 8*3; 5432 5433 pipe_config->pipe_bpp = bpp; 5434 5435 /* Clamp display bpp to connector max bpp */ 5436 for_each_new_connector_in_state(state, connector, connector_state, i) { 5437 int ret; 5438 5439 if (connector_state->crtc != &crtc->base) 5440 continue; 5441 5442 ret = compute_sink_pipe_bpp(connector_state, pipe_config); 5443 if (ret) 5444 return ret; 5445 } 5446 5447 return 0; 5448 } 5449 5450 static void intel_dump_crtc_timings(struct drm_i915_private *i915, 5451 const struct drm_display_mode *mode) 5452 { 5453 drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, " 5454 "type: 0x%x flags: 0x%x\n", 5455 mode->crtc_clock, 5456 mode->crtc_hdisplay, mode->crtc_hsync_start, 5457 mode->crtc_hsync_end, mode->crtc_htotal, 5458 mode->crtc_vdisplay, mode->crtc_vsync_start, 5459 mode->crtc_vsync_end, mode->crtc_vtotal, 5460 mode->type, mode->flags); 5461 } 5462 5463 static void 5464 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config, 5465 const char *id, unsigned int lane_count, 5466 const struct intel_link_m_n *m_n) 5467 { 5468 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); 5469 5470 drm_dbg_kms(&i915->drm, 5471 "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n", 5472 id, lane_count, 5473 m_n->data_m, m_n->data_n, 5474 m_n->link_m, m_n->link_n, m_n->tu); 5475 } 5476 5477 static void 5478 intel_dump_infoframe(struct drm_i915_private *dev_priv, 5479 const union hdmi_infoframe *frame) 5480 { 5481 if (!drm_debug_enabled(DRM_UT_KMS)) 5482 return; 5483 5484 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame); 5485 } 5486 5487 static void 5488 intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv, 5489 const struct drm_dp_vsc_sdp *vsc) 5490 { 5491 if (!drm_debug_enabled(DRM_UT_KMS)) 5492 return; 5493 5494 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc); 5495 } 5496 5497 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x 5498 5499 static const char * const output_type_str[] = { 5500 OUTPUT_TYPE(UNUSED), 5501 OUTPUT_TYPE(ANALOG), 5502 OUTPUT_TYPE(DVO), 5503 OUTPUT_TYPE(SDVO), 5504 OUTPUT_TYPE(LVDS), 5505 OUTPUT_TYPE(TVOUT), 5506 OUTPUT_TYPE(HDMI), 5507 OUTPUT_TYPE(DP), 5508 OUTPUT_TYPE(EDP), 5509 OUTPUT_TYPE(DSI), 5510 OUTPUT_TYPE(DDI), 5511 OUTPUT_TYPE(DP_MST), 5512 }; 5513 5514 #undef OUTPUT_TYPE 5515 5516 static void snprintf_output_types(char *buf, size_t len, 5517 unsigned int output_types) 5518 { 5519 char *str = buf; 5520 int i; 5521 5522 str[0] = '\0'; 5523 5524 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) { 5525 int r; 5526 5527 if ((output_types & BIT(i)) == 0) 5528 continue; 5529 5530 r = snprintf(str, len, "%s%s", 5531 str != buf ? "," : "", output_type_str[i]); 5532 if (r >= len) 5533 break; 5534 str += r; 5535 len -= r; 5536 5537 output_types &= ~BIT(i); 5538 } 5539 5540 WARN_ON_ONCE(output_types != 0); 5541 } 5542 5543 static const char * const output_format_str[] = { 5544 [INTEL_OUTPUT_FORMAT_RGB] = "RGB", 5545 [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0", 5546 [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4", 5547 }; 5548 5549 static const char *output_formats(enum intel_output_format format) 5550 { 5551 if (format >= ARRAY_SIZE(output_format_str)) 5552 return "invalid"; 5553 return output_format_str[format]; 5554 } 5555 5556 static void intel_dump_plane_state(const struct intel_plane_state *plane_state) 5557 { 5558 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 5559 struct drm_i915_private *i915 = to_i915(plane->base.dev); 5560 const struct drm_framebuffer *fb = plane_state->hw.fb; 5561 5562 if (!fb) { 5563 drm_dbg_kms(&i915->drm, 5564 "[PLANE:%d:%s] fb: [NOFB], visible: %s\n", 5565 plane->base.base.id, plane->base.name, 5566 yesno(plane_state->uapi.visible)); 5567 return; 5568 } 5569 5570 drm_dbg_kms(&i915->drm, 5571 "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %p4cc modifier = 0x%llx, visible: %s\n", 5572 plane->base.base.id, plane->base.name, 5573 fb->base.id, fb->width, fb->height, &fb->format->format, 5574 fb->modifier, yesno(plane_state->uapi.visible)); 5575 drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n", 5576 plane_state->hw.rotation, plane_state->scaler_id); 5577 if (plane_state->uapi.visible) 5578 drm_dbg_kms(&i915->drm, 5579 "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n", 5580 DRM_RECT_FP_ARG(&plane_state->uapi.src), 5581 DRM_RECT_ARG(&plane_state->uapi.dst)); 5582 } 5583 5584 static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, 5585 struct intel_atomic_state *state, 5586 const char *context) 5587 { 5588 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 5589 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5590 const struct intel_plane_state *plane_state; 5591 struct intel_plane *plane; 5592 char buf[64]; 5593 int i; 5594 5595 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n", 5596 crtc->base.base.id, crtc->base.name, 5597 yesno(pipe_config->hw.enable), context); 5598 5599 if (!pipe_config->hw.enable) 5600 goto dump_planes; 5601 5602 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types); 5603 drm_dbg_kms(&dev_priv->drm, 5604 "active: %s, output_types: %s (0x%x), output format: %s\n", 5605 yesno(pipe_config->hw.active), 5606 buf, pipe_config->output_types, 5607 output_formats(pipe_config->output_format)); 5608 5609 drm_dbg_kms(&dev_priv->drm, 5610 "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", 5611 transcoder_name(pipe_config->cpu_transcoder), 5612 pipe_config->pipe_bpp, pipe_config->dither); 5613 5614 drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n", 5615 transcoder_name(pipe_config->mst_master_transcoder)); 5616 5617 drm_dbg_kms(&dev_priv->drm, 5618 "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n", 5619 transcoder_name(pipe_config->master_transcoder), 5620 pipe_config->sync_mode_slaves_mask); 5621 5622 drm_dbg_kms(&dev_priv->drm, "bigjoiner: %s\n", 5623 pipe_config->bigjoiner_slave ? "slave" : 5624 pipe_config->bigjoiner ? "master" : "no"); 5625 5626 drm_dbg_kms(&dev_priv->drm, "splitter: %s, link count %d, overlap %d\n", 5627 enableddisabled(pipe_config->splitter.enable), 5628 pipe_config->splitter.link_count, 5629 pipe_config->splitter.pixel_overlap); 5630 5631 if (pipe_config->has_pch_encoder) 5632 intel_dump_m_n_config(pipe_config, "fdi", 5633 pipe_config->fdi_lanes, 5634 &pipe_config->fdi_m_n); 5635 5636 if (intel_crtc_has_dp_encoder(pipe_config)) { 5637 intel_dump_m_n_config(pipe_config, "dp m_n", 5638 pipe_config->lane_count, 5639 &pipe_config->dp_m_n); 5640 intel_dump_m_n_config(pipe_config, "dp m2_n2", 5641 pipe_config->lane_count, 5642 &pipe_config->dp_m2_n2); 5643 } 5644 5645 drm_dbg_kms(&dev_priv->drm, 5646 "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n", 5647 pipe_config->has_audio, pipe_config->has_infoframe, 5648 pipe_config->infoframes.enable); 5649 5650 if (pipe_config->infoframes.enable & 5651 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) 5652 drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n", 5653 pipe_config->infoframes.gcp); 5654 if (pipe_config->infoframes.enable & 5655 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) 5656 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi); 5657 if (pipe_config->infoframes.enable & 5658 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD)) 5659 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd); 5660 if (pipe_config->infoframes.enable & 5661 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR)) 5662 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi); 5663 if (pipe_config->infoframes.enable & 5664 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) 5665 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); 5666 if (pipe_config->infoframes.enable & 5667 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA)) 5668 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); 5669 if (pipe_config->infoframes.enable & 5670 intel_hdmi_infoframe_enable(DP_SDP_VSC)) 5671 intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc); 5672 5673 drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n", 5674 yesno(pipe_config->vrr.enable), 5675 pipe_config->vrr.vmin, pipe_config->vrr.vmax, 5676 pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband, 5677 pipe_config->vrr.flipline, 5678 intel_vrr_vmin_vblank_start(pipe_config), 5679 intel_vrr_vmax_vblank_start(pipe_config)); 5680 5681 drm_dbg_kms(&dev_priv->drm, "requested mode:\n"); 5682 drm_mode_debug_printmodeline(&pipe_config->hw.mode); 5683 drm_dbg_kms(&dev_priv->drm, "adjusted mode:\n"); 5684 drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode); 5685 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode); 5686 drm_dbg_kms(&dev_priv->drm, "pipe mode:\n"); 5687 drm_mode_debug_printmodeline(&pipe_config->hw.pipe_mode); 5688 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode); 5689 drm_dbg_kms(&dev_priv->drm, 5690 "port clock: %d, pipe src size: %dx%d, pixel rate %d\n", 5691 pipe_config->port_clock, 5692 pipe_config->pipe_src_w, pipe_config->pipe_src_h, 5693 pipe_config->pixel_rate); 5694 5695 drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n", 5696 pipe_config->linetime, pipe_config->ips_linetime); 5697 5698 if (DISPLAY_VER(dev_priv) >= 9) 5699 drm_dbg_kms(&dev_priv->drm, 5700 "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", 5701 crtc->num_scalers, 5702 pipe_config->scaler_state.scaler_users, 5703 pipe_config->scaler_state.scaler_id); 5704 5705 if (HAS_GMCH(dev_priv)) 5706 drm_dbg_kms(&dev_priv->drm, 5707 "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", 5708 pipe_config->gmch_pfit.control, 5709 pipe_config->gmch_pfit.pgm_ratios, 5710 pipe_config->gmch_pfit.lvds_border_bits); 5711 else 5712 drm_dbg_kms(&dev_priv->drm, 5713 "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n", 5714 DRM_RECT_ARG(&pipe_config->pch_pfit.dst), 5715 enableddisabled(pipe_config->pch_pfit.enabled), 5716 yesno(pipe_config->pch_pfit.force_thru)); 5717 5718 drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i\n", 5719 pipe_config->ips_enabled, pipe_config->double_wide); 5720 5721 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state); 5722 5723 if (IS_CHERRYVIEW(dev_priv)) 5724 drm_dbg_kms(&dev_priv->drm, 5725 "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", 5726 pipe_config->cgm_mode, pipe_config->gamma_mode, 5727 pipe_config->gamma_enable, pipe_config->csc_enable); 5728 else 5729 drm_dbg_kms(&dev_priv->drm, 5730 "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", 5731 pipe_config->csc_mode, pipe_config->gamma_mode, 5732 pipe_config->gamma_enable, pipe_config->csc_enable); 5733 5734 drm_dbg_kms(&dev_priv->drm, "degamma lut: %d entries, gamma lut: %d entries\n", 5735 pipe_config->hw.degamma_lut ? 5736 drm_color_lut_size(pipe_config->hw.degamma_lut) : 0, 5737 pipe_config->hw.gamma_lut ? 5738 drm_color_lut_size(pipe_config->hw.gamma_lut) : 0); 5739 5740 dump_planes: 5741 if (!state) 5742 return; 5743 5744 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 5745 if (plane->pipe == crtc->pipe) 5746 intel_dump_plane_state(plane_state); 5747 } 5748 } 5749 5750 static bool check_digital_port_conflicts(struct intel_atomic_state *state) 5751 { 5752 struct drm_device *dev = state->base.dev; 5753 struct drm_connector *connector; 5754 struct drm_connector_list_iter conn_iter; 5755 unsigned int used_ports = 0; 5756 unsigned int used_mst_ports = 0; 5757 bool ret = true; 5758 5759 /* 5760 * We're going to peek into connector->state, 5761 * hence connection_mutex must be held. 5762 */ 5763 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex); 5764 5765 /* 5766 * Walk the connector list instead of the encoder 5767 * list to detect the problem on ddi platforms 5768 * where there's just one encoder per digital port. 5769 */ 5770 drm_connector_list_iter_begin(dev, &conn_iter); 5771 drm_for_each_connector_iter(connector, &conn_iter) { 5772 struct drm_connector_state *connector_state; 5773 struct intel_encoder *encoder; 5774 5775 connector_state = 5776 drm_atomic_get_new_connector_state(&state->base, 5777 connector); 5778 if (!connector_state) 5779 connector_state = connector->state; 5780 5781 if (!connector_state->best_encoder) 5782 continue; 5783 5784 encoder = to_intel_encoder(connector_state->best_encoder); 5785 5786 drm_WARN_ON(dev, !connector_state->crtc); 5787 5788 switch (encoder->type) { 5789 case INTEL_OUTPUT_DDI: 5790 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev)))) 5791 break; 5792 fallthrough; 5793 case INTEL_OUTPUT_DP: 5794 case INTEL_OUTPUT_HDMI: 5795 case INTEL_OUTPUT_EDP: 5796 /* the same port mustn't appear more than once */ 5797 if (used_ports & BIT(encoder->port)) 5798 ret = false; 5799 5800 used_ports |= BIT(encoder->port); 5801 break; 5802 case INTEL_OUTPUT_DP_MST: 5803 used_mst_ports |= 5804 1 << encoder->port; 5805 break; 5806 default: 5807 break; 5808 } 5809 } 5810 drm_connector_list_iter_end(&conn_iter); 5811 5812 /* can't mix MST and SST/HDMI on the same port */ 5813 if (used_ports & used_mst_ports) 5814 return false; 5815 5816 return ret; 5817 } 5818 5819 static void 5820 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state, 5821 struct intel_crtc_state *crtc_state) 5822 { 5823 const struct intel_crtc_state *master_crtc_state; 5824 struct intel_crtc *master_crtc; 5825 5826 master_crtc = intel_master_crtc(crtc_state); 5827 master_crtc_state = intel_atomic_get_new_crtc_state(state, master_crtc); 5828 5829 /* No need to copy state if the master state is unchanged */ 5830 if (master_crtc_state) 5831 intel_crtc_copy_color_blobs(crtc_state, master_crtc_state); 5832 } 5833 5834 static void 5835 intel_crtc_copy_uapi_to_hw_state(struct intel_atomic_state *state, 5836 struct intel_crtc_state *crtc_state) 5837 { 5838 crtc_state->hw.enable = crtc_state->uapi.enable; 5839 crtc_state->hw.active = crtc_state->uapi.active; 5840 crtc_state->hw.mode = crtc_state->uapi.mode; 5841 crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode; 5842 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter; 5843 5844 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc_state); 5845 } 5846 5847 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state) 5848 { 5849 if (crtc_state->bigjoiner_slave) 5850 return; 5851 5852 crtc_state->uapi.enable = crtc_state->hw.enable; 5853 crtc_state->uapi.active = crtc_state->hw.active; 5854 drm_WARN_ON(crtc_state->uapi.crtc->dev, 5855 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0); 5856 5857 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode; 5858 crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter; 5859 5860 /* copy color blobs to uapi */ 5861 drm_property_replace_blob(&crtc_state->uapi.degamma_lut, 5862 crtc_state->hw.degamma_lut); 5863 drm_property_replace_blob(&crtc_state->uapi.gamma_lut, 5864 crtc_state->hw.gamma_lut); 5865 drm_property_replace_blob(&crtc_state->uapi.ctm, 5866 crtc_state->hw.ctm); 5867 } 5868 5869 static int 5870 copy_bigjoiner_crtc_state(struct intel_crtc_state *crtc_state, 5871 const struct intel_crtc_state *from_crtc_state) 5872 { 5873 struct intel_crtc_state *saved_state; 5874 5875 saved_state = kmemdup(from_crtc_state, sizeof(*saved_state), GFP_KERNEL); 5876 if (!saved_state) 5877 return -ENOMEM; 5878 5879 saved_state->uapi = crtc_state->uapi; 5880 saved_state->scaler_state = crtc_state->scaler_state; 5881 saved_state->shared_dpll = crtc_state->shared_dpll; 5882 saved_state->dpll_hw_state = crtc_state->dpll_hw_state; 5883 saved_state->crc_enabled = crtc_state->crc_enabled; 5884 5885 intel_crtc_free_hw_state(crtc_state); 5886 memcpy(crtc_state, saved_state, sizeof(*crtc_state)); 5887 kfree(saved_state); 5888 5889 /* Re-init hw state */ 5890 memset(&crtc_state->hw, 0, sizeof(saved_state->hw)); 5891 crtc_state->hw.enable = from_crtc_state->hw.enable; 5892 crtc_state->hw.active = from_crtc_state->hw.active; 5893 crtc_state->hw.pipe_mode = from_crtc_state->hw.pipe_mode; 5894 crtc_state->hw.adjusted_mode = from_crtc_state->hw.adjusted_mode; 5895 5896 /* Some fixups */ 5897 crtc_state->uapi.mode_changed = from_crtc_state->uapi.mode_changed; 5898 crtc_state->uapi.connectors_changed = from_crtc_state->uapi.connectors_changed; 5899 crtc_state->uapi.active_changed = from_crtc_state->uapi.active_changed; 5900 crtc_state->nv12_planes = crtc_state->c8_planes = crtc_state->update_planes = 0; 5901 crtc_state->bigjoiner_linked_crtc = to_intel_crtc(from_crtc_state->uapi.crtc); 5902 crtc_state->bigjoiner_slave = true; 5903 crtc_state->cpu_transcoder = from_crtc_state->cpu_transcoder; 5904 crtc_state->has_audio = from_crtc_state->has_audio; 5905 5906 return 0; 5907 } 5908 5909 static int 5910 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state, 5911 struct intel_crtc_state *crtc_state) 5912 { 5913 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 5914 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5915 struct intel_crtc_state *saved_state; 5916 5917 saved_state = intel_crtc_state_alloc(crtc); 5918 if (!saved_state) 5919 return -ENOMEM; 5920 5921 /* free the old crtc_state->hw members */ 5922 intel_crtc_free_hw_state(crtc_state); 5923 5924 /* FIXME: before the switch to atomic started, a new pipe_config was 5925 * kzalloc'd. Code that depends on any field being zero should be 5926 * fixed, so that the crtc_state can be safely duplicated. For now, 5927 * only fields that are know to not cause problems are preserved. */ 5928 5929 saved_state->uapi = crtc_state->uapi; 5930 saved_state->scaler_state = crtc_state->scaler_state; 5931 saved_state->shared_dpll = crtc_state->shared_dpll; 5932 saved_state->dpll_hw_state = crtc_state->dpll_hw_state; 5933 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, 5934 sizeof(saved_state->icl_port_dplls)); 5935 saved_state->crc_enabled = crtc_state->crc_enabled; 5936 if (IS_G4X(dev_priv) || 5937 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5938 saved_state->wm = crtc_state->wm; 5939 5940 memcpy(crtc_state, saved_state, sizeof(*crtc_state)); 5941 kfree(saved_state); 5942 5943 intel_crtc_copy_uapi_to_hw_state(state, crtc_state); 5944 5945 return 0; 5946 } 5947 5948 static int 5949 intel_modeset_pipe_config(struct intel_atomic_state *state, 5950 struct intel_crtc_state *pipe_config) 5951 { 5952 struct drm_crtc *crtc = pipe_config->uapi.crtc; 5953 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); 5954 struct drm_connector *connector; 5955 struct drm_connector_state *connector_state; 5956 int base_bpp, ret, i; 5957 bool retry = true; 5958 5959 pipe_config->cpu_transcoder = 5960 (enum transcoder) to_intel_crtc(crtc)->pipe; 5961 5962 /* 5963 * Sanitize sync polarity flags based on requested ones. If neither 5964 * positive or negative polarity is requested, treat this as meaning 5965 * negative polarity. 5966 */ 5967 if (!(pipe_config->hw.adjusted_mode.flags & 5968 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) 5969 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; 5970 5971 if (!(pipe_config->hw.adjusted_mode.flags & 5972 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 5973 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; 5974 5975 ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc), 5976 pipe_config); 5977 if (ret) 5978 return ret; 5979 5980 base_bpp = pipe_config->pipe_bpp; 5981 5982 /* 5983 * Determine the real pipe dimensions. Note that stereo modes can 5984 * increase the actual pipe size due to the frame doubling and 5985 * insertion of additional space for blanks between the frame. This 5986 * is stored in the crtc timings. We use the requested mode to do this 5987 * computation to clearly distinguish it from the adjusted mode, which 5988 * can be changed by the connectors in the below retry loop. 5989 */ 5990 drm_mode_get_hv_timing(&pipe_config->hw.mode, 5991 &pipe_config->pipe_src_w, 5992 &pipe_config->pipe_src_h); 5993 5994 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5995 struct intel_encoder *encoder = 5996 to_intel_encoder(connector_state->best_encoder); 5997 5998 if (connector_state->crtc != crtc) 5999 continue; 6000 6001 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) { 6002 drm_dbg_kms(&i915->drm, 6003 "rejecting invalid cloning configuration\n"); 6004 return -EINVAL; 6005 } 6006 6007 /* 6008 * Determine output_types before calling the .compute_config() 6009 * hooks so that the hooks can use this information safely. 6010 */ 6011 if (encoder->compute_output_type) 6012 pipe_config->output_types |= 6013 BIT(encoder->compute_output_type(encoder, pipe_config, 6014 connector_state)); 6015 else 6016 pipe_config->output_types |= BIT(encoder->type); 6017 } 6018 6019 encoder_retry: 6020 /* Ensure the port clock defaults are reset when retrying. */ 6021 pipe_config->port_clock = 0; 6022 pipe_config->pixel_multiplier = 1; 6023 6024 /* Fill in default crtc timings, allow encoders to overwrite them. */ 6025 drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode, 6026 CRTC_STEREO_DOUBLE); 6027 6028 /* Pass our mode to the connectors and the CRTC to give them a chance to 6029 * adjust it according to limitations or connector properties, and also 6030 * a chance to reject the mode entirely. 6031 */ 6032 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 6033 struct intel_encoder *encoder = 6034 to_intel_encoder(connector_state->best_encoder); 6035 6036 if (connector_state->crtc != crtc) 6037 continue; 6038 6039 ret = encoder->compute_config(encoder, pipe_config, 6040 connector_state); 6041 if (ret == -EDEADLK) 6042 return ret; 6043 if (ret < 0) { 6044 drm_dbg_kms(&i915->drm, "Encoder config failure: %d\n", ret); 6045 return ret; 6046 } 6047 } 6048 6049 /* Set default port clock if not overwritten by the encoder. Needs to be 6050 * done afterwards in case the encoder adjusts the mode. */ 6051 if (!pipe_config->port_clock) 6052 pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock 6053 * pipe_config->pixel_multiplier; 6054 6055 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); 6056 if (ret == -EDEADLK) 6057 return ret; 6058 if (ret == -EAGAIN) { 6059 if (drm_WARN(&i915->drm, !retry, 6060 "loop in pipe configuration computation\n")) 6061 return -EINVAL; 6062 6063 drm_dbg_kms(&i915->drm, "CRTC bw constrained, retrying\n"); 6064 retry = false; 6065 goto encoder_retry; 6066 } 6067 if (ret < 0) { 6068 drm_dbg_kms(&i915->drm, "CRTC config failure: %d\n", ret); 6069 return ret; 6070 } 6071 6072 /* Dithering seems to not pass-through bits correctly when it should, so 6073 * only enable it on 6bpc panels and when its not a compliance 6074 * test requesting 6bpc video pattern. 6075 */ 6076 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) && 6077 !pipe_config->dither_force_disable; 6078 drm_dbg_kms(&i915->drm, 6079 "hw max bpp: %i, pipe bpp: %i, dithering: %i\n", 6080 base_bpp, pipe_config->pipe_bpp, pipe_config->dither); 6081 6082 return 0; 6083 } 6084 6085 static int 6086 intel_modeset_pipe_config_late(struct intel_crtc_state *crtc_state) 6087 { 6088 struct intel_atomic_state *state = 6089 to_intel_atomic_state(crtc_state->uapi.state); 6090 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 6091 struct drm_connector_state *conn_state; 6092 struct drm_connector *connector; 6093 int i; 6094 6095 for_each_new_connector_in_state(&state->base, connector, 6096 conn_state, i) { 6097 struct intel_encoder *encoder = 6098 to_intel_encoder(conn_state->best_encoder); 6099 int ret; 6100 6101 if (conn_state->crtc != &crtc->base || 6102 !encoder->compute_config_late) 6103 continue; 6104 6105 ret = encoder->compute_config_late(encoder, crtc_state, 6106 conn_state); 6107 if (ret) 6108 return ret; 6109 } 6110 6111 return 0; 6112 } 6113 6114 bool intel_fuzzy_clock_check(int clock1, int clock2) 6115 { 6116 int diff; 6117 6118 if (clock1 == clock2) 6119 return true; 6120 6121 if (!clock1 || !clock2) 6122 return false; 6123 6124 diff = abs(clock1 - clock2); 6125 6126 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) 6127 return true; 6128 6129 return false; 6130 } 6131 6132 static bool 6133 intel_compare_m_n(unsigned int m, unsigned int n, 6134 unsigned int m2, unsigned int n2, 6135 bool exact) 6136 { 6137 if (m == m2 && n == n2) 6138 return true; 6139 6140 if (exact || !m || !n || !m2 || !n2) 6141 return false; 6142 6143 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); 6144 6145 if (n > n2) { 6146 while (n > n2) { 6147 m2 <<= 1; 6148 n2 <<= 1; 6149 } 6150 } else if (n < n2) { 6151 while (n < n2) { 6152 m <<= 1; 6153 n <<= 1; 6154 } 6155 } 6156 6157 if (n != n2) 6158 return false; 6159 6160 return intel_fuzzy_clock_check(m, m2); 6161 } 6162 6163 static bool 6164 intel_compare_link_m_n(const struct intel_link_m_n *m_n, 6165 const struct intel_link_m_n *m2_n2, 6166 bool exact) 6167 { 6168 return m_n->tu == m2_n2->tu && 6169 intel_compare_m_n(m_n->data_m, m_n->data_n, 6170 m2_n2->data_m, m2_n2->data_n, exact) && 6171 intel_compare_m_n(m_n->link_m, m_n->link_n, 6172 m2_n2->link_m, m2_n2->link_n, exact); 6173 } 6174 6175 static bool 6176 intel_compare_infoframe(const union hdmi_infoframe *a, 6177 const union hdmi_infoframe *b) 6178 { 6179 return memcmp(a, b, sizeof(*a)) == 0; 6180 } 6181 6182 static bool 6183 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a, 6184 const struct drm_dp_vsc_sdp *b) 6185 { 6186 return memcmp(a, b, sizeof(*a)) == 0; 6187 } 6188 6189 static void 6190 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv, 6191 bool fastset, const char *name, 6192 const union hdmi_infoframe *a, 6193 const union hdmi_infoframe *b) 6194 { 6195 if (fastset) { 6196 if (!drm_debug_enabled(DRM_UT_KMS)) 6197 return; 6198 6199 drm_dbg_kms(&dev_priv->drm, 6200 "fastset mismatch in %s infoframe\n", name); 6201 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 6202 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a); 6203 drm_dbg_kms(&dev_priv->drm, "found:\n"); 6204 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b); 6205 } else { 6206 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name); 6207 drm_err(&dev_priv->drm, "expected:\n"); 6208 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a); 6209 drm_err(&dev_priv->drm, "found:\n"); 6210 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b); 6211 } 6212 } 6213 6214 static void 6215 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv, 6216 bool fastset, const char *name, 6217 const struct drm_dp_vsc_sdp *a, 6218 const struct drm_dp_vsc_sdp *b) 6219 { 6220 if (fastset) { 6221 if (!drm_debug_enabled(DRM_UT_KMS)) 6222 return; 6223 6224 drm_dbg_kms(&dev_priv->drm, 6225 "fastset mismatch in %s dp sdp\n", name); 6226 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 6227 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a); 6228 drm_dbg_kms(&dev_priv->drm, "found:\n"); 6229 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b); 6230 } else { 6231 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name); 6232 drm_err(&dev_priv->drm, "expected:\n"); 6233 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a); 6234 drm_err(&dev_priv->drm, "found:\n"); 6235 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b); 6236 } 6237 } 6238 6239 static void __printf(4, 5) 6240 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc, 6241 const char *name, const char *format, ...) 6242 { 6243 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 6244 struct va_format vaf; 6245 va_list args; 6246 6247 va_start(args, format); 6248 vaf.fmt = format; 6249 vaf.va = &args; 6250 6251 if (fastset) 6252 drm_dbg_kms(&i915->drm, 6253 "[CRTC:%d:%s] fastset mismatch in %s %pV\n", 6254 crtc->base.base.id, crtc->base.name, name, &vaf); 6255 else 6256 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n", 6257 crtc->base.base.id, crtc->base.name, name, &vaf); 6258 6259 va_end(args); 6260 } 6261 6262 static bool fastboot_enabled(struct drm_i915_private *dev_priv) 6263 { 6264 if (dev_priv->params.fastboot != -1) 6265 return dev_priv->params.fastboot; 6266 6267 /* Enable fastboot by default on Skylake and newer */ 6268 if (DISPLAY_VER(dev_priv) >= 9) 6269 return true; 6270 6271 /* Enable fastboot by default on VLV and CHV */ 6272 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 6273 return true; 6274 6275 /* Disabled by default on all others */ 6276 return false; 6277 } 6278 6279 static bool 6280 intel_pipe_config_compare(const struct intel_crtc_state *current_config, 6281 const struct intel_crtc_state *pipe_config, 6282 bool fastset) 6283 { 6284 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev); 6285 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 6286 bool ret = true; 6287 u32 bp_gamma = 0; 6288 bool fixup_inherited = fastset && 6289 current_config->inherited && !pipe_config->inherited; 6290 6291 if (fixup_inherited && !fastboot_enabled(dev_priv)) { 6292 drm_dbg_kms(&dev_priv->drm, 6293 "initial modeset and fastboot not set\n"); 6294 ret = false; 6295 } 6296 6297 #define PIPE_CONF_CHECK_X(name) do { \ 6298 if (current_config->name != pipe_config->name) { \ 6299 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6300 "(expected 0x%08x, found 0x%08x)", \ 6301 current_config->name, \ 6302 pipe_config->name); \ 6303 ret = false; \ 6304 } \ 6305 } while (0) 6306 6307 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \ 6308 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \ 6309 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6310 "(expected 0x%08x, found 0x%08x)", \ 6311 current_config->name & (mask), \ 6312 pipe_config->name & (mask)); \ 6313 ret = false; \ 6314 } \ 6315 } while (0) 6316 6317 #define PIPE_CONF_CHECK_I(name) do { \ 6318 if (current_config->name != pipe_config->name) { \ 6319 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6320 "(expected %i, found %i)", \ 6321 current_config->name, \ 6322 pipe_config->name); \ 6323 ret = false; \ 6324 } \ 6325 } while (0) 6326 6327 #define PIPE_CONF_CHECK_BOOL(name) do { \ 6328 if (current_config->name != pipe_config->name) { \ 6329 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6330 "(expected %s, found %s)", \ 6331 yesno(current_config->name), \ 6332 yesno(pipe_config->name)); \ 6333 ret = false; \ 6334 } \ 6335 } while (0) 6336 6337 /* 6338 * Checks state where we only read out the enabling, but not the entire 6339 * state itself (like full infoframes or ELD for audio). These states 6340 * require a full modeset on bootup to fix up. 6341 */ 6342 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \ 6343 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \ 6344 PIPE_CONF_CHECK_BOOL(name); \ 6345 } else { \ 6346 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6347 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \ 6348 yesno(current_config->name), \ 6349 yesno(pipe_config->name)); \ 6350 ret = false; \ 6351 } \ 6352 } while (0) 6353 6354 #define PIPE_CONF_CHECK_P(name) do { \ 6355 if (current_config->name != pipe_config->name) { \ 6356 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6357 "(expected %p, found %p)", \ 6358 current_config->name, \ 6359 pipe_config->name); \ 6360 ret = false; \ 6361 } \ 6362 } while (0) 6363 6364 #define PIPE_CONF_CHECK_M_N(name) do { \ 6365 if (!intel_compare_link_m_n(¤t_config->name, \ 6366 &pipe_config->name,\ 6367 !fastset)) { \ 6368 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6369 "(expected tu %i data %i/%i link %i/%i, " \ 6370 "found tu %i, data %i/%i link %i/%i)", \ 6371 current_config->name.tu, \ 6372 current_config->name.data_m, \ 6373 current_config->name.data_n, \ 6374 current_config->name.link_m, \ 6375 current_config->name.link_n, \ 6376 pipe_config->name.tu, \ 6377 pipe_config->name.data_m, \ 6378 pipe_config->name.data_n, \ 6379 pipe_config->name.link_m, \ 6380 pipe_config->name.link_n); \ 6381 ret = false; \ 6382 } \ 6383 } while (0) 6384 6385 /* This is required for BDW+ where there is only one set of registers for 6386 * switching between high and low RR. 6387 * This macro can be used whenever a comparison has to be made between one 6388 * hw state and multiple sw state variables. 6389 */ 6390 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \ 6391 if (!intel_compare_link_m_n(¤t_config->name, \ 6392 &pipe_config->name, !fastset) && \ 6393 !intel_compare_link_m_n(¤t_config->alt_name, \ 6394 &pipe_config->name, !fastset)) { \ 6395 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6396 "(expected tu %i data %i/%i link %i/%i, " \ 6397 "or tu %i data %i/%i link %i/%i, " \ 6398 "found tu %i, data %i/%i link %i/%i)", \ 6399 current_config->name.tu, \ 6400 current_config->name.data_m, \ 6401 current_config->name.data_n, \ 6402 current_config->name.link_m, \ 6403 current_config->name.link_n, \ 6404 current_config->alt_name.tu, \ 6405 current_config->alt_name.data_m, \ 6406 current_config->alt_name.data_n, \ 6407 current_config->alt_name.link_m, \ 6408 current_config->alt_name.link_n, \ 6409 pipe_config->name.tu, \ 6410 pipe_config->name.data_m, \ 6411 pipe_config->name.data_n, \ 6412 pipe_config->name.link_m, \ 6413 pipe_config->name.link_n); \ 6414 ret = false; \ 6415 } \ 6416 } while (0) 6417 6418 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \ 6419 if ((current_config->name ^ pipe_config->name) & (mask)) { \ 6420 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6421 "(%x) (expected %i, found %i)", \ 6422 (mask), \ 6423 current_config->name & (mask), \ 6424 pipe_config->name & (mask)); \ 6425 ret = false; \ 6426 } \ 6427 } while (0) 6428 6429 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \ 6430 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ 6431 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6432 "(expected %i, found %i)", \ 6433 current_config->name, \ 6434 pipe_config->name); \ 6435 ret = false; \ 6436 } \ 6437 } while (0) 6438 6439 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \ 6440 if (!intel_compare_infoframe(¤t_config->infoframes.name, \ 6441 &pipe_config->infoframes.name)) { \ 6442 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \ 6443 ¤t_config->infoframes.name, \ 6444 &pipe_config->infoframes.name); \ 6445 ret = false; \ 6446 } \ 6447 } while (0) 6448 6449 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \ 6450 if (!current_config->has_psr && !pipe_config->has_psr && \ 6451 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \ 6452 &pipe_config->infoframes.name)) { \ 6453 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \ 6454 ¤t_config->infoframes.name, \ 6455 &pipe_config->infoframes.name); \ 6456 ret = false; \ 6457 } \ 6458 } while (0) 6459 6460 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \ 6461 if (current_config->name1 != pipe_config->name1) { \ 6462 pipe_config_mismatch(fastset, crtc, __stringify(name1), \ 6463 "(expected %i, found %i, won't compare lut values)", \ 6464 current_config->name1, \ 6465 pipe_config->name1); \ 6466 ret = false;\ 6467 } else { \ 6468 if (!intel_color_lut_equal(current_config->name2, \ 6469 pipe_config->name2, pipe_config->name1, \ 6470 bit_precision)) { \ 6471 pipe_config_mismatch(fastset, crtc, __stringify(name2), \ 6472 "hw_state doesn't match sw_state"); \ 6473 ret = false; \ 6474 } \ 6475 } \ 6476 } while (0) 6477 6478 #define PIPE_CONF_QUIRK(quirk) \ 6479 ((current_config->quirks | pipe_config->quirks) & (quirk)) 6480 6481 PIPE_CONF_CHECK_I(cpu_transcoder); 6482 6483 PIPE_CONF_CHECK_BOOL(has_pch_encoder); 6484 PIPE_CONF_CHECK_I(fdi_lanes); 6485 PIPE_CONF_CHECK_M_N(fdi_m_n); 6486 6487 PIPE_CONF_CHECK_I(lane_count); 6488 PIPE_CONF_CHECK_X(lane_lat_optim_mask); 6489 6490 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) { 6491 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); 6492 } else { 6493 PIPE_CONF_CHECK_M_N(dp_m_n); 6494 PIPE_CONF_CHECK_M_N(dp_m2_n2); 6495 } 6496 6497 PIPE_CONF_CHECK_X(output_types); 6498 6499 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay); 6500 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_htotal); 6501 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_start); 6502 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_end); 6503 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_start); 6504 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_end); 6505 6506 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vdisplay); 6507 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vtotal); 6508 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_start); 6509 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_end); 6510 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_start); 6511 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_end); 6512 6513 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay); 6514 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal); 6515 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start); 6516 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end); 6517 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start); 6518 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end); 6519 6520 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay); 6521 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal); 6522 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start); 6523 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end); 6524 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start); 6525 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end); 6526 6527 PIPE_CONF_CHECK_I(pixel_multiplier); 6528 6529 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6530 DRM_MODE_FLAG_INTERLACE); 6531 6532 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { 6533 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6534 DRM_MODE_FLAG_PHSYNC); 6535 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6536 DRM_MODE_FLAG_NHSYNC); 6537 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6538 DRM_MODE_FLAG_PVSYNC); 6539 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6540 DRM_MODE_FLAG_NVSYNC); 6541 } 6542 6543 PIPE_CONF_CHECK_I(output_format); 6544 PIPE_CONF_CHECK_BOOL(has_hdmi_sink); 6545 if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || 6546 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 6547 PIPE_CONF_CHECK_BOOL(limited_color_range); 6548 6549 PIPE_CONF_CHECK_BOOL(hdmi_scrambling); 6550 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio); 6551 PIPE_CONF_CHECK_BOOL(has_infoframe); 6552 PIPE_CONF_CHECK_BOOL(fec_enable); 6553 6554 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio); 6555 6556 PIPE_CONF_CHECK_X(gmch_pfit.control); 6557 /* pfit ratios are autocomputed by the hw on gen4+ */ 6558 if (DISPLAY_VER(dev_priv) < 4) 6559 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); 6560 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); 6561 6562 /* 6563 * Changing the EDP transcoder input mux 6564 * (A_ONOFF vs. A_ON) requires a full modeset. 6565 */ 6566 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru); 6567 6568 if (!fastset) { 6569 PIPE_CONF_CHECK_I(pipe_src_w); 6570 PIPE_CONF_CHECK_I(pipe_src_h); 6571 6572 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled); 6573 if (current_config->pch_pfit.enabled) { 6574 PIPE_CONF_CHECK_I(pch_pfit.dst.x1); 6575 PIPE_CONF_CHECK_I(pch_pfit.dst.y1); 6576 PIPE_CONF_CHECK_I(pch_pfit.dst.x2); 6577 PIPE_CONF_CHECK_I(pch_pfit.dst.y2); 6578 } 6579 6580 PIPE_CONF_CHECK_I(scaler_state.scaler_id); 6581 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate); 6582 6583 PIPE_CONF_CHECK_X(gamma_mode); 6584 if (IS_CHERRYVIEW(dev_priv)) 6585 PIPE_CONF_CHECK_X(cgm_mode); 6586 else 6587 PIPE_CONF_CHECK_X(csc_mode); 6588 PIPE_CONF_CHECK_BOOL(gamma_enable); 6589 PIPE_CONF_CHECK_BOOL(csc_enable); 6590 6591 PIPE_CONF_CHECK_I(linetime); 6592 PIPE_CONF_CHECK_I(ips_linetime); 6593 6594 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config); 6595 if (bp_gamma) 6596 PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma); 6597 6598 if (current_config->active_planes) { 6599 PIPE_CONF_CHECK_BOOL(has_psr); 6600 PIPE_CONF_CHECK_BOOL(has_psr2); 6601 PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); 6602 PIPE_CONF_CHECK_I(dc3co_exitline); 6603 } 6604 } 6605 6606 PIPE_CONF_CHECK_BOOL(double_wide); 6607 6608 if (dev_priv->dpll.mgr) { 6609 PIPE_CONF_CHECK_P(shared_dpll); 6610 6611 PIPE_CONF_CHECK_X(dpll_hw_state.dpll); 6612 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); 6613 PIPE_CONF_CHECK_X(dpll_hw_state.fp0); 6614 PIPE_CONF_CHECK_X(dpll_hw_state.fp1); 6615 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); 6616 PIPE_CONF_CHECK_X(dpll_hw_state.spll); 6617 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); 6618 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); 6619 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); 6620 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); 6621 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); 6622 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); 6623 PIPE_CONF_CHECK_X(dpll_hw_state.pll0); 6624 PIPE_CONF_CHECK_X(dpll_hw_state.pll1); 6625 PIPE_CONF_CHECK_X(dpll_hw_state.pll2); 6626 PIPE_CONF_CHECK_X(dpll_hw_state.pll3); 6627 PIPE_CONF_CHECK_X(dpll_hw_state.pll6); 6628 PIPE_CONF_CHECK_X(dpll_hw_state.pll8); 6629 PIPE_CONF_CHECK_X(dpll_hw_state.pll9); 6630 PIPE_CONF_CHECK_X(dpll_hw_state.pll10); 6631 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); 6632 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl); 6633 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1); 6634 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl); 6635 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0); 6636 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1); 6637 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf); 6638 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock); 6639 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc); 6640 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias); 6641 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias); 6642 } 6643 6644 PIPE_CONF_CHECK_X(dsi_pll.ctrl); 6645 PIPE_CONF_CHECK_X(dsi_pll.div); 6646 6647 if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5) 6648 PIPE_CONF_CHECK_I(pipe_bpp); 6649 6650 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock); 6651 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock); 6652 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); 6653 6654 PIPE_CONF_CHECK_I(min_voltage_level); 6655 6656 if (current_config->has_psr || pipe_config->has_psr) 6657 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable, 6658 ~intel_hdmi_infoframe_enable(DP_SDP_VSC)); 6659 else 6660 PIPE_CONF_CHECK_X(infoframes.enable); 6661 6662 PIPE_CONF_CHECK_X(infoframes.gcp); 6663 PIPE_CONF_CHECK_INFOFRAME(avi); 6664 PIPE_CONF_CHECK_INFOFRAME(spd); 6665 PIPE_CONF_CHECK_INFOFRAME(hdmi); 6666 PIPE_CONF_CHECK_INFOFRAME(drm); 6667 PIPE_CONF_CHECK_DP_VSC_SDP(vsc); 6668 6669 PIPE_CONF_CHECK_X(sync_mode_slaves_mask); 6670 PIPE_CONF_CHECK_I(master_transcoder); 6671 PIPE_CONF_CHECK_BOOL(bigjoiner); 6672 PIPE_CONF_CHECK_BOOL(bigjoiner_slave); 6673 PIPE_CONF_CHECK_P(bigjoiner_linked_crtc); 6674 6675 PIPE_CONF_CHECK_I(dsc.compression_enable); 6676 PIPE_CONF_CHECK_I(dsc.dsc_split); 6677 PIPE_CONF_CHECK_I(dsc.compressed_bpp); 6678 6679 PIPE_CONF_CHECK_BOOL(splitter.enable); 6680 PIPE_CONF_CHECK_I(splitter.link_count); 6681 PIPE_CONF_CHECK_I(splitter.pixel_overlap); 6682 6683 PIPE_CONF_CHECK_I(mst_master_transcoder); 6684 6685 PIPE_CONF_CHECK_BOOL(vrr.enable); 6686 PIPE_CONF_CHECK_I(vrr.vmin); 6687 PIPE_CONF_CHECK_I(vrr.vmax); 6688 PIPE_CONF_CHECK_I(vrr.flipline); 6689 PIPE_CONF_CHECK_I(vrr.pipeline_full); 6690 PIPE_CONF_CHECK_I(vrr.guardband); 6691 6692 #undef PIPE_CONF_CHECK_X 6693 #undef PIPE_CONF_CHECK_I 6694 #undef PIPE_CONF_CHECK_BOOL 6695 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE 6696 #undef PIPE_CONF_CHECK_P 6697 #undef PIPE_CONF_CHECK_FLAGS 6698 #undef PIPE_CONF_CHECK_CLOCK_FUZZY 6699 #undef PIPE_CONF_CHECK_COLOR_LUT 6700 #undef PIPE_CONF_QUIRK 6701 6702 return ret; 6703 } 6704 6705 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, 6706 const struct intel_crtc_state *pipe_config) 6707 { 6708 if (pipe_config->has_pch_encoder) { 6709 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), 6710 &pipe_config->fdi_m_n); 6711 int dotclock = pipe_config->hw.adjusted_mode.crtc_clock; 6712 6713 /* 6714 * FDI already provided one idea for the dotclock. 6715 * Yell if the encoder disagrees. 6716 */ 6717 drm_WARN(&dev_priv->drm, 6718 !intel_fuzzy_clock_check(fdi_dotclock, dotclock), 6719 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", 6720 fdi_dotclock, dotclock); 6721 } 6722 } 6723 6724 static void verify_wm_state(struct intel_crtc *crtc, 6725 struct intel_crtc_state *new_crtc_state) 6726 { 6727 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6728 struct skl_hw_state { 6729 struct skl_ddb_entry ddb_y[I915_MAX_PLANES]; 6730 struct skl_ddb_entry ddb_uv[I915_MAX_PLANES]; 6731 struct skl_pipe_wm wm; 6732 } *hw; 6733 const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal; 6734 int level, max_level = ilk_wm_max_level(dev_priv); 6735 struct intel_plane *plane; 6736 u8 hw_enabled_slices; 6737 6738 if (DISPLAY_VER(dev_priv) < 9 || !new_crtc_state->hw.active) 6739 return; 6740 6741 hw = kzalloc(sizeof(*hw), GFP_KERNEL); 6742 if (!hw) 6743 return; 6744 6745 skl_pipe_wm_get_hw_state(crtc, &hw->wm); 6746 6747 skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv); 6748 6749 hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv); 6750 6751 if (DISPLAY_VER(dev_priv) >= 11 && 6752 hw_enabled_slices != dev_priv->dbuf.enabled_slices) 6753 drm_err(&dev_priv->drm, 6754 "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n", 6755 dev_priv->dbuf.enabled_slices, 6756 hw_enabled_slices); 6757 6758 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 6759 const struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; 6760 const struct skl_wm_level *hw_wm_level, *sw_wm_level; 6761 6762 /* Watermarks */ 6763 for (level = 0; level <= max_level; level++) { 6764 hw_wm_level = &hw->wm.planes[plane->id].wm[level]; 6765 sw_wm_level = skl_plane_wm_level(sw_wm, plane->id, level); 6766 6767 if (skl_wm_level_equals(hw_wm_level, sw_wm_level)) 6768 continue; 6769 6770 drm_err(&dev_priv->drm, 6771 "[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 6772 plane->base.base.id, plane->base.name, level, 6773 sw_wm_level->enable, 6774 sw_wm_level->blocks, 6775 sw_wm_level->lines, 6776 hw_wm_level->enable, 6777 hw_wm_level->blocks, 6778 hw_wm_level->lines); 6779 } 6780 6781 hw_wm_level = &hw->wm.planes[plane->id].trans_wm; 6782 sw_wm_level = skl_plane_trans_wm(sw_wm, plane->id); 6783 6784 if (!skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 6785 drm_err(&dev_priv->drm, 6786 "[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 6787 plane->base.base.id, plane->base.name, 6788 sw_wm_level->enable, 6789 sw_wm_level->blocks, 6790 sw_wm_level->lines, 6791 hw_wm_level->enable, 6792 hw_wm_level->blocks, 6793 hw_wm_level->lines); 6794 } 6795 6796 hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0; 6797 sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0; 6798 6799 if (HAS_HW_SAGV_WM(dev_priv) && 6800 !skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 6801 drm_err(&dev_priv->drm, 6802 "[PLANE:%d:%s] mismatch in SAGV WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 6803 plane->base.base.id, plane->base.name, 6804 sw_wm_level->enable, 6805 sw_wm_level->blocks, 6806 sw_wm_level->lines, 6807 hw_wm_level->enable, 6808 hw_wm_level->blocks, 6809 hw_wm_level->lines); 6810 } 6811 6812 hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm; 6813 sw_wm_level = &sw_wm->planes[plane->id].sagv.trans_wm; 6814 6815 if (HAS_HW_SAGV_WM(dev_priv) && 6816 !skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 6817 drm_err(&dev_priv->drm, 6818 "[PLANE:%d:%s] mismatch in SAGV trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 6819 plane->base.base.id, plane->base.name, 6820 sw_wm_level->enable, 6821 sw_wm_level->blocks, 6822 sw_wm_level->lines, 6823 hw_wm_level->enable, 6824 hw_wm_level->blocks, 6825 hw_wm_level->lines); 6826 } 6827 6828 /* DDB */ 6829 hw_ddb_entry = &hw->ddb_y[plane->id]; 6830 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane->id]; 6831 6832 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { 6833 drm_err(&dev_priv->drm, 6834 "[PLANE:%d:%s] mismatch in DDB (expected (%u,%u), found (%u,%u))\n", 6835 plane->base.base.id, plane->base.name, 6836 sw_ddb_entry->start, sw_ddb_entry->end, 6837 hw_ddb_entry->start, hw_ddb_entry->end); 6838 } 6839 } 6840 6841 kfree(hw); 6842 } 6843 6844 static void 6845 verify_connector_state(struct intel_atomic_state *state, 6846 struct intel_crtc *crtc) 6847 { 6848 struct drm_connector *connector; 6849 struct drm_connector_state *new_conn_state; 6850 int i; 6851 6852 for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) { 6853 struct drm_encoder *encoder = connector->encoder; 6854 struct intel_crtc_state *crtc_state = NULL; 6855 6856 if (new_conn_state->crtc != &crtc->base) 6857 continue; 6858 6859 if (crtc) 6860 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6861 6862 intel_connector_verify_state(crtc_state, new_conn_state); 6863 6864 I915_STATE_WARN(new_conn_state->best_encoder != encoder, 6865 "connector's atomic encoder doesn't match legacy encoder\n"); 6866 } 6867 } 6868 6869 static void 6870 verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state) 6871 { 6872 struct intel_encoder *encoder; 6873 struct drm_connector *connector; 6874 struct drm_connector_state *old_conn_state, *new_conn_state; 6875 int i; 6876 6877 for_each_intel_encoder(&dev_priv->drm, encoder) { 6878 bool enabled = false, found = false; 6879 enum pipe pipe; 6880 6881 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n", 6882 encoder->base.base.id, 6883 encoder->base.name); 6884 6885 for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state, 6886 new_conn_state, i) { 6887 if (old_conn_state->best_encoder == &encoder->base) 6888 found = true; 6889 6890 if (new_conn_state->best_encoder != &encoder->base) 6891 continue; 6892 found = enabled = true; 6893 6894 I915_STATE_WARN(new_conn_state->crtc != 6895 encoder->base.crtc, 6896 "connector's crtc doesn't match encoder crtc\n"); 6897 } 6898 6899 if (!found) 6900 continue; 6901 6902 I915_STATE_WARN(!!encoder->base.crtc != enabled, 6903 "encoder's enabled state mismatch " 6904 "(expected %i, found %i)\n", 6905 !!encoder->base.crtc, enabled); 6906 6907 if (!encoder->base.crtc) { 6908 bool active; 6909 6910 active = encoder->get_hw_state(encoder, &pipe); 6911 I915_STATE_WARN(active, 6912 "encoder detached but still enabled on pipe %c.\n", 6913 pipe_name(pipe)); 6914 } 6915 } 6916 } 6917 6918 static void 6919 verify_crtc_state(struct intel_crtc *crtc, 6920 struct intel_crtc_state *old_crtc_state, 6921 struct intel_crtc_state *new_crtc_state) 6922 { 6923 struct drm_device *dev = crtc->base.dev; 6924 struct drm_i915_private *dev_priv = to_i915(dev); 6925 struct intel_encoder *encoder; 6926 struct intel_crtc_state *pipe_config = old_crtc_state; 6927 struct drm_atomic_state *state = old_crtc_state->uapi.state; 6928 struct intel_crtc *master_crtc; 6929 6930 __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi); 6931 intel_crtc_free_hw_state(old_crtc_state); 6932 intel_crtc_state_reset(old_crtc_state, crtc); 6933 old_crtc_state->uapi.state = state; 6934 6935 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id, 6936 crtc->base.name); 6937 6938 pipe_config->hw.enable = new_crtc_state->hw.enable; 6939 6940 intel_crtc_get_pipe_config(pipe_config); 6941 6942 /* we keep both pipes enabled on 830 */ 6943 if (IS_I830(dev_priv) && pipe_config->hw.active) 6944 pipe_config->hw.active = new_crtc_state->hw.active; 6945 6946 I915_STATE_WARN(new_crtc_state->hw.active != pipe_config->hw.active, 6947 "crtc active state doesn't match with hw state " 6948 "(expected %i, found %i)\n", 6949 new_crtc_state->hw.active, pipe_config->hw.active); 6950 6951 I915_STATE_WARN(crtc->active != new_crtc_state->hw.active, 6952 "transitional active state does not match atomic hw state " 6953 "(expected %i, found %i)\n", 6954 new_crtc_state->hw.active, crtc->active); 6955 6956 master_crtc = intel_master_crtc(new_crtc_state); 6957 6958 for_each_encoder_on_crtc(dev, &master_crtc->base, encoder) { 6959 enum pipe pipe; 6960 bool active; 6961 6962 active = encoder->get_hw_state(encoder, &pipe); 6963 I915_STATE_WARN(active != new_crtc_state->hw.active, 6964 "[ENCODER:%i] active %i with crtc active %i\n", 6965 encoder->base.base.id, active, 6966 new_crtc_state->hw.active); 6967 6968 I915_STATE_WARN(active && master_crtc->pipe != pipe, 6969 "Encoder connected to wrong pipe %c\n", 6970 pipe_name(pipe)); 6971 6972 if (active) 6973 intel_encoder_get_config(encoder, pipe_config); 6974 } 6975 6976 if (!new_crtc_state->hw.active) 6977 return; 6978 6979 intel_pipe_config_sanity_check(dev_priv, pipe_config); 6980 6981 if (!intel_pipe_config_compare(new_crtc_state, 6982 pipe_config, false)) { 6983 I915_STATE_WARN(1, "pipe state doesn't match!\n"); 6984 intel_dump_pipe_config(pipe_config, NULL, "[hw state]"); 6985 intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]"); 6986 } 6987 } 6988 6989 static void 6990 intel_verify_planes(struct intel_atomic_state *state) 6991 { 6992 struct intel_plane *plane; 6993 const struct intel_plane_state *plane_state; 6994 int i; 6995 6996 for_each_new_intel_plane_in_state(state, plane, 6997 plane_state, i) 6998 assert_plane(plane, plane_state->planar_slave || 6999 plane_state->uapi.visible); 7000 } 7001 7002 static void 7003 verify_single_dpll_state(struct drm_i915_private *dev_priv, 7004 struct intel_shared_dpll *pll, 7005 struct intel_crtc *crtc, 7006 struct intel_crtc_state *new_crtc_state) 7007 { 7008 struct intel_dpll_hw_state dpll_hw_state; 7009 u8 pipe_mask; 7010 bool active; 7011 7012 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); 7013 7014 drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name); 7015 7016 active = intel_dpll_get_hw_state(dev_priv, pll, &dpll_hw_state); 7017 7018 if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) { 7019 I915_STATE_WARN(!pll->on && pll->active_mask, 7020 "pll in active use but not on in sw tracking\n"); 7021 I915_STATE_WARN(pll->on && !pll->active_mask, 7022 "pll is on but not used by any active pipe\n"); 7023 I915_STATE_WARN(pll->on != active, 7024 "pll on state mismatch (expected %i, found %i)\n", 7025 pll->on, active); 7026 } 7027 7028 if (!crtc) { 7029 I915_STATE_WARN(pll->active_mask & ~pll->state.pipe_mask, 7030 "more active pll users than references: 0x%x vs 0x%x\n", 7031 pll->active_mask, pll->state.pipe_mask); 7032 7033 return; 7034 } 7035 7036 pipe_mask = BIT(crtc->pipe); 7037 7038 if (new_crtc_state->hw.active) 7039 I915_STATE_WARN(!(pll->active_mask & pipe_mask), 7040 "pll active mismatch (expected pipe %c in active mask 0x%x)\n", 7041 pipe_name(crtc->pipe), pll->active_mask); 7042 else 7043 I915_STATE_WARN(pll->active_mask & pipe_mask, 7044 "pll active mismatch (didn't expect pipe %c in active mask 0x%x)\n", 7045 pipe_name(crtc->pipe), pll->active_mask); 7046 7047 I915_STATE_WARN(!(pll->state.pipe_mask & pipe_mask), 7048 "pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n", 7049 pipe_mask, pll->state.pipe_mask); 7050 7051 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state, 7052 &dpll_hw_state, 7053 sizeof(dpll_hw_state)), 7054 "pll hw state mismatch\n"); 7055 } 7056 7057 static void 7058 verify_shared_dpll_state(struct intel_crtc *crtc, 7059 struct intel_crtc_state *old_crtc_state, 7060 struct intel_crtc_state *new_crtc_state) 7061 { 7062 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 7063 7064 if (new_crtc_state->shared_dpll) 7065 verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state); 7066 7067 if (old_crtc_state->shared_dpll && 7068 old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) { 7069 u8 pipe_mask = BIT(crtc->pipe); 7070 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll; 7071 7072 I915_STATE_WARN(pll->active_mask & pipe_mask, 7073 "pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n", 7074 pipe_name(crtc->pipe), pll->active_mask); 7075 I915_STATE_WARN(pll->state.pipe_mask & pipe_mask, 7076 "pll enabled crtcs mismatch (found %x in enabled mask (0x%x))\n", 7077 pipe_name(crtc->pipe), pll->state.pipe_mask); 7078 } 7079 } 7080 7081 static void 7082 verify_mpllb_state(struct intel_atomic_state *state, 7083 struct intel_crtc_state *new_crtc_state) 7084 { 7085 struct drm_i915_private *i915 = to_i915(state->base.dev); 7086 struct intel_mpllb_state mpllb_hw_state = { 0 }; 7087 struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->mpllb_state; 7088 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 7089 struct intel_encoder *encoder; 7090 7091 if (!IS_DG2(i915)) 7092 return; 7093 7094 if (!new_crtc_state->hw.active) 7095 return; 7096 7097 encoder = intel_get_crtc_new_encoder(state, new_crtc_state); 7098 intel_mpllb_readout_hw_state(encoder, &mpllb_hw_state); 7099 7100 #define MPLLB_CHECK(name) do { \ 7101 if (mpllb_sw_state->name != mpllb_hw_state.name) { \ 7102 pipe_config_mismatch(false, crtc, "MPLLB:" __stringify(name), \ 7103 "(expected 0x%08x, found 0x%08x)", \ 7104 mpllb_sw_state->name, \ 7105 mpllb_hw_state.name); \ 7106 } \ 7107 } while (0) 7108 7109 MPLLB_CHECK(mpllb_cp); 7110 MPLLB_CHECK(mpllb_div); 7111 MPLLB_CHECK(mpllb_div2); 7112 MPLLB_CHECK(mpllb_fracn1); 7113 MPLLB_CHECK(mpllb_fracn2); 7114 MPLLB_CHECK(mpllb_sscen); 7115 MPLLB_CHECK(mpllb_sscstep); 7116 7117 /* 7118 * ref_control is handled by the hardware/firemware and never 7119 * programmed by the software, but the proper values are supplied 7120 * in the bspec for verification purposes. 7121 */ 7122 MPLLB_CHECK(ref_control); 7123 7124 #undef MPLLB_CHECK 7125 } 7126 7127 static void 7128 intel_modeset_verify_crtc(struct intel_crtc *crtc, 7129 struct intel_atomic_state *state, 7130 struct intel_crtc_state *old_crtc_state, 7131 struct intel_crtc_state *new_crtc_state) 7132 { 7133 if (!intel_crtc_needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe) 7134 return; 7135 7136 verify_wm_state(crtc, new_crtc_state); 7137 verify_connector_state(state, crtc); 7138 verify_crtc_state(crtc, old_crtc_state, new_crtc_state); 7139 verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state); 7140 verify_mpllb_state(state, new_crtc_state); 7141 } 7142 7143 static void 7144 verify_disabled_dpll_state(struct drm_i915_private *dev_priv) 7145 { 7146 int i; 7147 7148 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) 7149 verify_single_dpll_state(dev_priv, 7150 &dev_priv->dpll.shared_dplls[i], 7151 NULL, NULL); 7152 } 7153 7154 static void 7155 intel_modeset_verify_disabled(struct drm_i915_private *dev_priv, 7156 struct intel_atomic_state *state) 7157 { 7158 verify_encoder_state(dev_priv, state); 7159 verify_connector_state(state, NULL); 7160 verify_disabled_dpll_state(dev_priv); 7161 } 7162 7163 int intel_modeset_all_pipes(struct intel_atomic_state *state) 7164 { 7165 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7166 struct intel_crtc *crtc; 7167 7168 /* 7169 * Add all pipes to the state, and force 7170 * a modeset on all the active ones. 7171 */ 7172 for_each_intel_crtc(&dev_priv->drm, crtc) { 7173 struct intel_crtc_state *crtc_state; 7174 int ret; 7175 7176 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 7177 if (IS_ERR(crtc_state)) 7178 return PTR_ERR(crtc_state); 7179 7180 if (!crtc_state->hw.active || 7181 drm_atomic_crtc_needs_modeset(&crtc_state->uapi)) 7182 continue; 7183 7184 crtc_state->uapi.mode_changed = true; 7185 7186 ret = drm_atomic_add_affected_connectors(&state->base, 7187 &crtc->base); 7188 if (ret) 7189 return ret; 7190 7191 ret = intel_atomic_add_affected_planes(state, crtc); 7192 if (ret) 7193 return ret; 7194 7195 crtc_state->update_planes |= crtc_state->active_planes; 7196 } 7197 7198 return 0; 7199 } 7200 7201 static void 7202 intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state) 7203 { 7204 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 7205 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 7206 struct drm_display_mode adjusted_mode = 7207 crtc_state->hw.adjusted_mode; 7208 7209 if (crtc_state->vrr.enable) { 7210 adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax; 7211 adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax; 7212 adjusted_mode.crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state); 7213 crtc->vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state); 7214 } 7215 7216 drm_calc_timestamping_constants(&crtc->base, &adjusted_mode); 7217 7218 crtc->mode_flags = crtc_state->mode_flags; 7219 7220 /* 7221 * The scanline counter increments at the leading edge of hsync. 7222 * 7223 * On most platforms it starts counting from vtotal-1 on the 7224 * first active line. That means the scanline counter value is 7225 * always one less than what we would expect. Ie. just after 7226 * start of vblank, which also occurs at start of hsync (on the 7227 * last active line), the scanline counter will read vblank_start-1. 7228 * 7229 * On gen2 the scanline counter starts counting from 1 instead 7230 * of vtotal-1, so we have to subtract one (or rather add vtotal-1 7231 * to keep the value positive), instead of adding one. 7232 * 7233 * On HSW+ the behaviour of the scanline counter depends on the output 7234 * type. For DP ports it behaves like most other platforms, but on HDMI 7235 * there's an extra 1 line difference. So we need to add two instead of 7236 * one to the value. 7237 * 7238 * On VLV/CHV DSI the scanline counter would appear to increment 7239 * approx. 1/3 of a scanline before start of vblank. Unfortunately 7240 * that means we can't tell whether we're in vblank or not while 7241 * we're on that particular line. We must still set scanline_offset 7242 * to 1 so that the vblank timestamps come out correct when we query 7243 * the scanline counter from within the vblank interrupt handler. 7244 * However if queried just before the start of vblank we'll get an 7245 * answer that's slightly in the future. 7246 */ 7247 if (DISPLAY_VER(dev_priv) == 2) { 7248 int vtotal; 7249 7250 vtotal = adjusted_mode.crtc_vtotal; 7251 if (adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 7252 vtotal /= 2; 7253 7254 crtc->scanline_offset = vtotal - 1; 7255 } else if (HAS_DDI(dev_priv) && 7256 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 7257 crtc->scanline_offset = 2; 7258 } else { 7259 crtc->scanline_offset = 1; 7260 } 7261 } 7262 7263 static void intel_modeset_clear_plls(struct intel_atomic_state *state) 7264 { 7265 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7266 struct intel_crtc_state *new_crtc_state; 7267 struct intel_crtc *crtc; 7268 int i; 7269 7270 if (!dev_priv->dpll_funcs) 7271 return; 7272 7273 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7274 if (!intel_crtc_needs_modeset(new_crtc_state)) 7275 continue; 7276 7277 intel_release_shared_dplls(state, crtc); 7278 } 7279 } 7280 7281 /* 7282 * This implements the workaround described in the "notes" section of the mode 7283 * set sequence documentation. When going from no pipes or single pipe to 7284 * multiple pipes, and planes are enabled after the pipe, we need to wait at 7285 * least 2 vblanks on the first pipe before enabling planes on the second pipe. 7286 */ 7287 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state) 7288 { 7289 struct intel_crtc_state *crtc_state; 7290 struct intel_crtc *crtc; 7291 struct intel_crtc_state *first_crtc_state = NULL; 7292 struct intel_crtc_state *other_crtc_state = NULL; 7293 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; 7294 int i; 7295 7296 /* look at all crtc's that are going to be enabled in during modeset */ 7297 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7298 if (!crtc_state->hw.active || 7299 !intel_crtc_needs_modeset(crtc_state)) 7300 continue; 7301 7302 if (first_crtc_state) { 7303 other_crtc_state = crtc_state; 7304 break; 7305 } else { 7306 first_crtc_state = crtc_state; 7307 first_pipe = crtc->pipe; 7308 } 7309 } 7310 7311 /* No workaround needed? */ 7312 if (!first_crtc_state) 7313 return 0; 7314 7315 /* w/a possibly needed, check how many crtc's are already enabled. */ 7316 for_each_intel_crtc(state->base.dev, crtc) { 7317 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 7318 if (IS_ERR(crtc_state)) 7319 return PTR_ERR(crtc_state); 7320 7321 crtc_state->hsw_workaround_pipe = INVALID_PIPE; 7322 7323 if (!crtc_state->hw.active || 7324 intel_crtc_needs_modeset(crtc_state)) 7325 continue; 7326 7327 /* 2 or more enabled crtcs means no need for w/a */ 7328 if (enabled_pipe != INVALID_PIPE) 7329 return 0; 7330 7331 enabled_pipe = crtc->pipe; 7332 } 7333 7334 if (enabled_pipe != INVALID_PIPE) 7335 first_crtc_state->hsw_workaround_pipe = enabled_pipe; 7336 else if (other_crtc_state) 7337 other_crtc_state->hsw_workaround_pipe = first_pipe; 7338 7339 return 0; 7340 } 7341 7342 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 7343 u8 active_pipes) 7344 { 7345 const struct intel_crtc_state *crtc_state; 7346 struct intel_crtc *crtc; 7347 int i; 7348 7349 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7350 if (crtc_state->hw.active) 7351 active_pipes |= BIT(crtc->pipe); 7352 else 7353 active_pipes &= ~BIT(crtc->pipe); 7354 } 7355 7356 return active_pipes; 7357 } 7358 7359 static int intel_modeset_checks(struct intel_atomic_state *state) 7360 { 7361 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7362 7363 state->modeset = true; 7364 7365 if (IS_HASWELL(dev_priv)) 7366 return hsw_mode_set_planes_workaround(state); 7367 7368 return 0; 7369 } 7370 7371 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state, 7372 struct intel_crtc_state *new_crtc_state) 7373 { 7374 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) 7375 return; 7376 7377 new_crtc_state->uapi.mode_changed = false; 7378 new_crtc_state->update_pipe = true; 7379 } 7380 7381 static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state, 7382 struct intel_crtc_state *new_crtc_state) 7383 { 7384 /* 7385 * If we're not doing the full modeset we want to 7386 * keep the current M/N values as they may be 7387 * sufficiently different to the computed values 7388 * to cause problems. 7389 * 7390 * FIXME: should really copy more fuzzy state here 7391 */ 7392 new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n; 7393 new_crtc_state->dp_m_n = old_crtc_state->dp_m_n; 7394 new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2; 7395 new_crtc_state->has_drrs = old_crtc_state->has_drrs; 7396 } 7397 7398 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state, 7399 struct intel_crtc *crtc, 7400 u8 plane_ids_mask) 7401 { 7402 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7403 struct intel_plane *plane; 7404 7405 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 7406 struct intel_plane_state *plane_state; 7407 7408 if ((plane_ids_mask & BIT(plane->id)) == 0) 7409 continue; 7410 7411 plane_state = intel_atomic_get_plane_state(state, plane); 7412 if (IS_ERR(plane_state)) 7413 return PTR_ERR(plane_state); 7414 } 7415 7416 return 0; 7417 } 7418 7419 int intel_atomic_add_affected_planes(struct intel_atomic_state *state, 7420 struct intel_crtc *crtc) 7421 { 7422 const struct intel_crtc_state *old_crtc_state = 7423 intel_atomic_get_old_crtc_state(state, crtc); 7424 const struct intel_crtc_state *new_crtc_state = 7425 intel_atomic_get_new_crtc_state(state, crtc); 7426 7427 return intel_crtc_add_planes_to_state(state, crtc, 7428 old_crtc_state->enabled_planes | 7429 new_crtc_state->enabled_planes); 7430 } 7431 7432 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv) 7433 { 7434 /* See {hsw,vlv,ivb}_plane_ratio() */ 7435 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) || 7436 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) || 7437 IS_IVYBRIDGE(dev_priv); 7438 } 7439 7440 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state, 7441 struct intel_crtc *crtc, 7442 struct intel_crtc *other) 7443 { 7444 const struct intel_plane_state *plane_state; 7445 struct intel_plane *plane; 7446 u8 plane_ids = 0; 7447 int i; 7448 7449 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 7450 if (plane->pipe == crtc->pipe) 7451 plane_ids |= BIT(plane->id); 7452 } 7453 7454 return intel_crtc_add_planes_to_state(state, other, plane_ids); 7455 } 7456 7457 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state) 7458 { 7459 const struct intel_crtc_state *crtc_state; 7460 struct intel_crtc *crtc; 7461 int i; 7462 7463 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7464 int ret; 7465 7466 if (!crtc_state->bigjoiner) 7467 continue; 7468 7469 ret = intel_crtc_add_bigjoiner_planes(state, crtc, 7470 crtc_state->bigjoiner_linked_crtc); 7471 if (ret) 7472 return ret; 7473 } 7474 7475 return 0; 7476 } 7477 7478 static int intel_atomic_check_planes(struct intel_atomic_state *state) 7479 { 7480 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7481 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7482 struct intel_plane_state *plane_state; 7483 struct intel_plane *plane; 7484 struct intel_crtc *crtc; 7485 int i, ret; 7486 7487 ret = icl_add_linked_planes(state); 7488 if (ret) 7489 return ret; 7490 7491 ret = intel_bigjoiner_add_affected_planes(state); 7492 if (ret) 7493 return ret; 7494 7495 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 7496 ret = intel_plane_atomic_check(state, plane); 7497 if (ret) { 7498 drm_dbg_atomic(&dev_priv->drm, 7499 "[PLANE:%d:%s] atomic driver check failed\n", 7500 plane->base.base.id, plane->base.name); 7501 return ret; 7502 } 7503 } 7504 7505 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7506 new_crtc_state, i) { 7507 u8 old_active_planes, new_active_planes; 7508 7509 ret = icl_check_nv12_planes(new_crtc_state); 7510 if (ret) 7511 return ret; 7512 7513 /* 7514 * On some platforms the number of active planes affects 7515 * the planes' minimum cdclk calculation. Add such planes 7516 * to the state before we compute the minimum cdclk. 7517 */ 7518 if (!active_planes_affects_min_cdclk(dev_priv)) 7519 continue; 7520 7521 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 7522 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 7523 7524 if (hweight8(old_active_planes) == hweight8(new_active_planes)) 7525 continue; 7526 7527 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes); 7528 if (ret) 7529 return ret; 7530 } 7531 7532 return 0; 7533 } 7534 7535 static int intel_atomic_check_crtcs(struct intel_atomic_state *state) 7536 { 7537 struct intel_crtc_state *crtc_state; 7538 struct intel_crtc *crtc; 7539 int i; 7540 7541 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7542 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 7543 int ret; 7544 7545 ret = intel_crtc_atomic_check(state, crtc); 7546 if (ret) { 7547 drm_dbg_atomic(&i915->drm, 7548 "[CRTC:%d:%s] atomic driver check failed\n", 7549 crtc->base.base.id, crtc->base.name); 7550 return ret; 7551 } 7552 } 7553 7554 return 0; 7555 } 7556 7557 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, 7558 u8 transcoders) 7559 { 7560 const struct intel_crtc_state *new_crtc_state; 7561 struct intel_crtc *crtc; 7562 int i; 7563 7564 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7565 if (new_crtc_state->hw.enable && 7566 transcoders & BIT(new_crtc_state->cpu_transcoder) && 7567 intel_crtc_needs_modeset(new_crtc_state)) 7568 return true; 7569 } 7570 7571 return false; 7572 } 7573 7574 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state, 7575 struct intel_crtc *crtc, 7576 struct intel_crtc_state *old_crtc_state, 7577 struct intel_crtc_state *new_crtc_state) 7578 { 7579 struct drm_i915_private *i915 = to_i915(state->base.dev); 7580 struct intel_crtc_state *slave_crtc_state, *master_crtc_state; 7581 struct intel_crtc *slave_crtc, *master_crtc; 7582 7583 /* slave being enabled, is master is still claiming this crtc? */ 7584 if (old_crtc_state->bigjoiner_slave) { 7585 slave_crtc = crtc; 7586 master_crtc = old_crtc_state->bigjoiner_linked_crtc; 7587 master_crtc_state = intel_atomic_get_new_crtc_state(state, master_crtc); 7588 if (!master_crtc_state || !intel_crtc_needs_modeset(master_crtc_state)) 7589 goto claimed; 7590 } 7591 7592 if (!new_crtc_state->bigjoiner) 7593 return 0; 7594 7595 slave_crtc = intel_dsc_get_bigjoiner_secondary(crtc); 7596 if (!slave_crtc) { 7597 drm_dbg_kms(&i915->drm, 7598 "[CRTC:%d:%s] Big joiner configuration requires " 7599 "CRTC + 1 to be used, doesn't exist\n", 7600 crtc->base.base.id, crtc->base.name); 7601 return -EINVAL; 7602 } 7603 7604 new_crtc_state->bigjoiner_linked_crtc = slave_crtc; 7605 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc); 7606 master_crtc = crtc; 7607 if (IS_ERR(slave_crtc_state)) 7608 return PTR_ERR(slave_crtc_state); 7609 7610 /* master being enabled, slave was already configured? */ 7611 if (slave_crtc_state->uapi.enable) 7612 goto claimed; 7613 7614 drm_dbg_kms(&i915->drm, 7615 "[CRTC:%d:%s] Used as slave for big joiner\n", 7616 slave_crtc->base.base.id, slave_crtc->base.name); 7617 7618 return copy_bigjoiner_crtc_state(slave_crtc_state, new_crtc_state); 7619 7620 claimed: 7621 drm_dbg_kms(&i915->drm, 7622 "[CRTC:%d:%s] Slave is enabled as normal CRTC, but " 7623 "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n", 7624 slave_crtc->base.base.id, slave_crtc->base.name, 7625 master_crtc->base.base.id, master_crtc->base.name); 7626 return -EINVAL; 7627 } 7628 7629 static void kill_bigjoiner_slave(struct intel_atomic_state *state, 7630 struct intel_crtc_state *master_crtc_state) 7631 { 7632 struct intel_crtc_state *slave_crtc_state = 7633 intel_atomic_get_new_crtc_state(state, master_crtc_state->bigjoiner_linked_crtc); 7634 7635 slave_crtc_state->bigjoiner = master_crtc_state->bigjoiner = false; 7636 slave_crtc_state->bigjoiner_slave = master_crtc_state->bigjoiner_slave = false; 7637 slave_crtc_state->bigjoiner_linked_crtc = master_crtc_state->bigjoiner_linked_crtc = NULL; 7638 intel_crtc_copy_uapi_to_hw_state(state, slave_crtc_state); 7639 } 7640 7641 /** 7642 * DOC: asynchronous flip implementation 7643 * 7644 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC 7645 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL. 7646 * Correspondingly, support is currently added for primary plane only. 7647 * 7648 * Async flip can only change the plane surface address, so anything else 7649 * changing is rejected from the intel_atomic_check_async() function. 7650 * Once this check is cleared, flip done interrupt is enabled using 7651 * the intel_crtc_enable_flip_done() function. 7652 * 7653 * As soon as the surface address register is written, flip done interrupt is 7654 * generated and the requested events are sent to the usersapce in the interrupt 7655 * handler itself. The timestamp and sequence sent during the flip done event 7656 * correspond to the last vblank and have no relation to the actual time when 7657 * the flip done event was sent. 7658 */ 7659 static int intel_atomic_check_async(struct intel_atomic_state *state, struct intel_crtc *crtc) 7660 { 7661 struct drm_i915_private *i915 = to_i915(state->base.dev); 7662 const struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7663 const struct intel_plane_state *new_plane_state, *old_plane_state; 7664 struct intel_plane *plane; 7665 int i; 7666 7667 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 7668 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 7669 7670 if (intel_crtc_needs_modeset(new_crtc_state)) { 7671 drm_dbg_kms(&i915->drm, "Modeset Required. Async flip not supported\n"); 7672 return -EINVAL; 7673 } 7674 7675 if (!new_crtc_state->hw.active) { 7676 drm_dbg_kms(&i915->drm, "CRTC inactive\n"); 7677 return -EINVAL; 7678 } 7679 if (old_crtc_state->active_planes != new_crtc_state->active_planes) { 7680 drm_dbg_kms(&i915->drm, 7681 "Active planes cannot be changed during async flip\n"); 7682 return -EINVAL; 7683 } 7684 7685 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 7686 new_plane_state, i) { 7687 if (plane->pipe != crtc->pipe) 7688 continue; 7689 7690 /* 7691 * TODO: Async flip is only supported through the page flip IOCTL 7692 * as of now. So support currently added for primary plane only. 7693 * Support for other planes on platforms on which supports 7694 * this(vlv/chv and icl+) should be added when async flip is 7695 * enabled in the atomic IOCTL path. 7696 */ 7697 if (!plane->async_flip) 7698 return -EINVAL; 7699 7700 /* 7701 * FIXME: This check is kept generic for all platforms. 7702 * Need to verify this for all gen9 platforms to enable 7703 * this selectively if required. 7704 */ 7705 switch (new_plane_state->hw.fb->modifier) { 7706 case I915_FORMAT_MOD_X_TILED: 7707 case I915_FORMAT_MOD_Y_TILED: 7708 case I915_FORMAT_MOD_Yf_TILED: 7709 break; 7710 default: 7711 drm_dbg_kms(&i915->drm, 7712 "Linear memory/CCS does not support async flips\n"); 7713 return -EINVAL; 7714 } 7715 7716 if (new_plane_state->hw.fb->format->num_planes > 1) { 7717 drm_dbg_kms(&i915->drm, 7718 "Planar formats not supported with async flips\n"); 7719 return -EINVAL; 7720 } 7721 7722 if (old_plane_state->view.color_plane[0].mapping_stride != 7723 new_plane_state->view.color_plane[0].mapping_stride) { 7724 drm_dbg_kms(&i915->drm, "Stride cannot be changed in async flip\n"); 7725 return -EINVAL; 7726 } 7727 7728 if (old_plane_state->hw.fb->modifier != 7729 new_plane_state->hw.fb->modifier) { 7730 drm_dbg_kms(&i915->drm, 7731 "Framebuffer modifiers cannot be changed in async flip\n"); 7732 return -EINVAL; 7733 } 7734 7735 if (old_plane_state->hw.fb->format != 7736 new_plane_state->hw.fb->format) { 7737 drm_dbg_kms(&i915->drm, 7738 "Framebuffer format cannot be changed in async flip\n"); 7739 return -EINVAL; 7740 } 7741 7742 if (old_plane_state->hw.rotation != 7743 new_plane_state->hw.rotation) { 7744 drm_dbg_kms(&i915->drm, "Rotation cannot be changed in async flip\n"); 7745 return -EINVAL; 7746 } 7747 7748 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) || 7749 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) { 7750 drm_dbg_kms(&i915->drm, 7751 "Plane size/co-ordinates cannot be changed in async flip\n"); 7752 return -EINVAL; 7753 } 7754 7755 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) { 7756 drm_dbg_kms(&i915->drm, "Alpha value cannot be changed in async flip\n"); 7757 return -EINVAL; 7758 } 7759 7760 if (old_plane_state->hw.pixel_blend_mode != 7761 new_plane_state->hw.pixel_blend_mode) { 7762 drm_dbg_kms(&i915->drm, 7763 "Pixel blend mode cannot be changed in async flip\n"); 7764 return -EINVAL; 7765 } 7766 7767 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) { 7768 drm_dbg_kms(&i915->drm, 7769 "Color encoding cannot be changed in async flip\n"); 7770 return -EINVAL; 7771 } 7772 7773 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) { 7774 drm_dbg_kms(&i915->drm, "Color range cannot be changed in async flip\n"); 7775 return -EINVAL; 7776 } 7777 7778 /* plane decryption is allow to change only in synchronous flips */ 7779 if (old_plane_state->decrypt != new_plane_state->decrypt) 7780 return -EINVAL; 7781 } 7782 7783 return 0; 7784 } 7785 7786 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state) 7787 { 7788 struct intel_crtc_state *crtc_state; 7789 struct intel_crtc *crtc; 7790 int i; 7791 7792 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7793 struct intel_crtc_state *linked_crtc_state; 7794 struct intel_crtc *linked_crtc; 7795 int ret; 7796 7797 if (!crtc_state->bigjoiner) 7798 continue; 7799 7800 linked_crtc = crtc_state->bigjoiner_linked_crtc; 7801 linked_crtc_state = intel_atomic_get_crtc_state(&state->base, linked_crtc); 7802 if (IS_ERR(linked_crtc_state)) 7803 return PTR_ERR(linked_crtc_state); 7804 7805 if (!intel_crtc_needs_modeset(crtc_state)) 7806 continue; 7807 7808 linked_crtc_state->uapi.mode_changed = true; 7809 7810 ret = drm_atomic_add_affected_connectors(&state->base, 7811 &linked_crtc->base); 7812 if (ret) 7813 return ret; 7814 7815 ret = intel_atomic_add_affected_planes(state, linked_crtc); 7816 if (ret) 7817 return ret; 7818 } 7819 7820 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7821 /* Kill old bigjoiner link, we may re-establish afterwards */ 7822 if (intel_crtc_needs_modeset(crtc_state) && 7823 crtc_state->bigjoiner && !crtc_state->bigjoiner_slave) 7824 kill_bigjoiner_slave(state, crtc_state); 7825 } 7826 7827 return 0; 7828 } 7829 7830 /** 7831 * intel_atomic_check - validate state object 7832 * @dev: drm device 7833 * @_state: state to validate 7834 */ 7835 static int intel_atomic_check(struct drm_device *dev, 7836 struct drm_atomic_state *_state) 7837 { 7838 struct drm_i915_private *dev_priv = to_i915(dev); 7839 struct intel_atomic_state *state = to_intel_atomic_state(_state); 7840 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7841 struct intel_crtc *crtc; 7842 int ret, i; 7843 bool any_ms = false; 7844 7845 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7846 new_crtc_state, i) { 7847 if (new_crtc_state->inherited != old_crtc_state->inherited) 7848 new_crtc_state->uapi.mode_changed = true; 7849 } 7850 7851 intel_vrr_check_modeset(state); 7852 7853 ret = drm_atomic_helper_check_modeset(dev, &state->base); 7854 if (ret) 7855 goto fail; 7856 7857 ret = intel_bigjoiner_add_affected_crtcs(state); 7858 if (ret) 7859 goto fail; 7860 7861 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7862 new_crtc_state, i) { 7863 if (!intel_crtc_needs_modeset(new_crtc_state)) { 7864 /* Light copy */ 7865 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, new_crtc_state); 7866 7867 continue; 7868 } 7869 7870 if (!new_crtc_state->uapi.enable) { 7871 if (!new_crtc_state->bigjoiner_slave) { 7872 intel_crtc_copy_uapi_to_hw_state(state, new_crtc_state); 7873 any_ms = true; 7874 } 7875 continue; 7876 } 7877 7878 ret = intel_crtc_prepare_cleared_state(state, new_crtc_state); 7879 if (ret) 7880 goto fail; 7881 7882 ret = intel_modeset_pipe_config(state, new_crtc_state); 7883 if (ret) 7884 goto fail; 7885 7886 ret = intel_atomic_check_bigjoiner(state, crtc, old_crtc_state, 7887 new_crtc_state); 7888 if (ret) 7889 goto fail; 7890 } 7891 7892 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7893 new_crtc_state, i) { 7894 if (!intel_crtc_needs_modeset(new_crtc_state)) 7895 continue; 7896 7897 ret = intel_modeset_pipe_config_late(new_crtc_state); 7898 if (ret) 7899 goto fail; 7900 7901 intel_crtc_check_fastset(old_crtc_state, new_crtc_state); 7902 } 7903 7904 /** 7905 * Check if fastset is allowed by external dependencies like other 7906 * pipes and transcoders. 7907 * 7908 * Right now it only forces a fullmodeset when the MST master 7909 * transcoder did not changed but the pipe of the master transcoder 7910 * needs a fullmodeset so all slaves also needs to do a fullmodeset or 7911 * in case of port synced crtcs, if one of the synced crtcs 7912 * needs a full modeset, all other synced crtcs should be 7913 * forced a full modeset. 7914 */ 7915 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7916 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state)) 7917 continue; 7918 7919 if (intel_dp_mst_is_slave_trans(new_crtc_state)) { 7920 enum transcoder master = new_crtc_state->mst_master_transcoder; 7921 7922 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) { 7923 new_crtc_state->uapi.mode_changed = true; 7924 new_crtc_state->update_pipe = false; 7925 } 7926 } 7927 7928 if (is_trans_port_sync_mode(new_crtc_state)) { 7929 u8 trans = new_crtc_state->sync_mode_slaves_mask; 7930 7931 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER) 7932 trans |= BIT(new_crtc_state->master_transcoder); 7933 7934 if (intel_cpu_transcoders_need_modeset(state, trans)) { 7935 new_crtc_state->uapi.mode_changed = true; 7936 new_crtc_state->update_pipe = false; 7937 } 7938 } 7939 7940 if (new_crtc_state->bigjoiner) { 7941 struct intel_crtc_state *linked_crtc_state = 7942 intel_atomic_get_new_crtc_state(state, new_crtc_state->bigjoiner_linked_crtc); 7943 7944 if (intel_crtc_needs_modeset(linked_crtc_state)) { 7945 new_crtc_state->uapi.mode_changed = true; 7946 new_crtc_state->update_pipe = false; 7947 } 7948 } 7949 } 7950 7951 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7952 new_crtc_state, i) { 7953 if (intel_crtc_needs_modeset(new_crtc_state)) { 7954 any_ms = true; 7955 continue; 7956 } 7957 7958 if (!new_crtc_state->update_pipe) 7959 continue; 7960 7961 intel_crtc_copy_fastset(old_crtc_state, new_crtc_state); 7962 } 7963 7964 if (any_ms && !check_digital_port_conflicts(state)) { 7965 drm_dbg_kms(&dev_priv->drm, 7966 "rejecting conflicting digital port configuration\n"); 7967 ret = -EINVAL; 7968 goto fail; 7969 } 7970 7971 ret = drm_dp_mst_atomic_check(&state->base); 7972 if (ret) 7973 goto fail; 7974 7975 ret = intel_atomic_check_planes(state); 7976 if (ret) 7977 goto fail; 7978 7979 ret = intel_compute_global_watermarks(state); 7980 if (ret) 7981 goto fail; 7982 7983 ret = intel_bw_atomic_check(state); 7984 if (ret) 7985 goto fail; 7986 7987 ret = intel_cdclk_atomic_check(state, &any_ms); 7988 if (ret) 7989 goto fail; 7990 7991 if (intel_any_crtc_needs_modeset(state)) 7992 any_ms = true; 7993 7994 if (any_ms) { 7995 ret = intel_modeset_checks(state); 7996 if (ret) 7997 goto fail; 7998 7999 ret = intel_modeset_calc_cdclk(state); 8000 if (ret) 8001 return ret; 8002 8003 intel_modeset_clear_plls(state); 8004 } 8005 8006 ret = intel_atomic_check_crtcs(state); 8007 if (ret) 8008 goto fail; 8009 8010 ret = intel_fbc_atomic_check(state); 8011 if (ret) 8012 goto fail; 8013 8014 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8015 new_crtc_state, i) { 8016 if (new_crtc_state->uapi.async_flip) { 8017 ret = intel_atomic_check_async(state, crtc); 8018 if (ret) 8019 goto fail; 8020 } 8021 8022 if (!intel_crtc_needs_modeset(new_crtc_state) && 8023 !new_crtc_state->update_pipe) 8024 continue; 8025 8026 intel_dump_pipe_config(new_crtc_state, state, 8027 intel_crtc_needs_modeset(new_crtc_state) ? 8028 "[modeset]" : "[fastset]"); 8029 } 8030 8031 return 0; 8032 8033 fail: 8034 if (ret == -EDEADLK) 8035 return ret; 8036 8037 /* 8038 * FIXME would probably be nice to know which crtc specifically 8039 * caused the failure, in cases where we can pinpoint it. 8040 */ 8041 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8042 new_crtc_state, i) 8043 intel_dump_pipe_config(new_crtc_state, state, "[failed]"); 8044 8045 return ret; 8046 } 8047 8048 static int intel_atomic_prepare_commit(struct intel_atomic_state *state) 8049 { 8050 struct intel_crtc_state *crtc_state; 8051 struct intel_crtc *crtc; 8052 int i, ret; 8053 8054 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base); 8055 if (ret < 0) 8056 return ret; 8057 8058 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 8059 bool mode_changed = intel_crtc_needs_modeset(crtc_state); 8060 8061 if (mode_changed || crtc_state->update_pipe || 8062 crtc_state->uapi.color_mgmt_changed) { 8063 intel_dsb_prepare(crtc_state); 8064 } 8065 } 8066 8067 return 0; 8068 } 8069 8070 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 8071 struct intel_crtc_state *crtc_state) 8072 { 8073 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 8074 8075 if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes) 8076 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 8077 8078 if (crtc_state->has_pch_encoder) { 8079 enum pipe pch_transcoder = 8080 intel_crtc_pch_transcoder(crtc); 8081 8082 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true); 8083 } 8084 } 8085 8086 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, 8087 const struct intel_crtc_state *new_crtc_state) 8088 { 8089 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 8090 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 8091 8092 /* 8093 * Update pipe size and adjust fitter if needed: the reason for this is 8094 * that in compute_mode_changes we check the native mode (not the pfit 8095 * mode) to see if we can flip rather than do a full mode set. In the 8096 * fastboot case, we'll flip, but if we don't update the pipesrc and 8097 * pfit state, we'll end up with a big fb scanned out into the wrong 8098 * sized surface. 8099 */ 8100 intel_set_pipe_src_size(new_crtc_state); 8101 8102 /* on skylake this is done by detaching scalers */ 8103 if (DISPLAY_VER(dev_priv) >= 9) { 8104 if (new_crtc_state->pch_pfit.enabled) 8105 skl_pfit_enable(new_crtc_state); 8106 } else if (HAS_PCH_SPLIT(dev_priv)) { 8107 if (new_crtc_state->pch_pfit.enabled) 8108 ilk_pfit_enable(new_crtc_state); 8109 else if (old_crtc_state->pch_pfit.enabled) 8110 ilk_pfit_disable(old_crtc_state); 8111 } 8112 8113 /* 8114 * The register is supposedly single buffered so perhaps 8115 * not 100% correct to do this here. But SKL+ calculate 8116 * this based on the adjust pixel rate so pfit changes do 8117 * affect it and so it must be updated for fastsets. 8118 * HSW/BDW only really need this here for fastboot, after 8119 * that the value should not change without a full modeset. 8120 */ 8121 if (DISPLAY_VER(dev_priv) >= 9 || 8122 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 8123 hsw_set_linetime_wm(new_crtc_state); 8124 8125 if (DISPLAY_VER(dev_priv) >= 11) 8126 icl_set_pipe_chicken(new_crtc_state); 8127 } 8128 8129 static void commit_pipe_pre_planes(struct intel_atomic_state *state, 8130 struct intel_crtc *crtc) 8131 { 8132 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8133 const struct intel_crtc_state *old_crtc_state = 8134 intel_atomic_get_old_crtc_state(state, crtc); 8135 const struct intel_crtc_state *new_crtc_state = 8136 intel_atomic_get_new_crtc_state(state, crtc); 8137 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 8138 8139 /* 8140 * During modesets pipe configuration was programmed as the 8141 * CRTC was enabled. 8142 */ 8143 if (!modeset) { 8144 if (new_crtc_state->uapi.color_mgmt_changed || 8145 new_crtc_state->update_pipe) 8146 intel_color_commit(new_crtc_state); 8147 8148 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 8149 bdw_set_pipemisc(new_crtc_state); 8150 8151 if (new_crtc_state->update_pipe) 8152 intel_pipe_fastset(old_crtc_state, new_crtc_state); 8153 } 8154 8155 intel_psr2_program_trans_man_trk_ctl(new_crtc_state); 8156 8157 intel_atomic_update_watermarks(state, crtc); 8158 } 8159 8160 static void commit_pipe_post_planes(struct intel_atomic_state *state, 8161 struct intel_crtc *crtc) 8162 { 8163 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8164 const struct intel_crtc_state *new_crtc_state = 8165 intel_atomic_get_new_crtc_state(state, crtc); 8166 8167 /* 8168 * Disable the scaler(s) after the plane(s) so that we don't 8169 * get a catastrophic underrun even if the two operations 8170 * end up happening in two different frames. 8171 */ 8172 if (DISPLAY_VER(dev_priv) >= 9 && 8173 !intel_crtc_needs_modeset(new_crtc_state)) 8174 skl_detach_scalers(new_crtc_state); 8175 } 8176 8177 static void intel_enable_crtc(struct intel_atomic_state *state, 8178 struct intel_crtc *crtc) 8179 { 8180 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8181 const struct intel_crtc_state *new_crtc_state = 8182 intel_atomic_get_new_crtc_state(state, crtc); 8183 8184 if (!intel_crtc_needs_modeset(new_crtc_state)) 8185 return; 8186 8187 intel_crtc_update_active_timings(new_crtc_state); 8188 8189 dev_priv->display->crtc_enable(state, crtc); 8190 8191 if (new_crtc_state->bigjoiner_slave) 8192 return; 8193 8194 /* vblanks work again, re-enable pipe CRC. */ 8195 intel_crtc_enable_pipe_crc(crtc); 8196 } 8197 8198 static void intel_update_crtc(struct intel_atomic_state *state, 8199 struct intel_crtc *crtc) 8200 { 8201 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8202 const struct intel_crtc_state *old_crtc_state = 8203 intel_atomic_get_old_crtc_state(state, crtc); 8204 struct intel_crtc_state *new_crtc_state = 8205 intel_atomic_get_new_crtc_state(state, crtc); 8206 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 8207 8208 if (!modeset) { 8209 if (new_crtc_state->preload_luts && 8210 (new_crtc_state->uapi.color_mgmt_changed || 8211 new_crtc_state->update_pipe)) 8212 intel_color_load_luts(new_crtc_state); 8213 8214 intel_pre_plane_update(state, crtc); 8215 8216 if (new_crtc_state->update_pipe) 8217 intel_encoders_update_pipe(state, crtc); 8218 } 8219 8220 intel_fbc_update(state, crtc); 8221 8222 intel_update_planes_on_crtc(state, crtc); 8223 8224 /* Perform vblank evasion around commit operation */ 8225 intel_pipe_update_start(new_crtc_state); 8226 8227 commit_pipe_pre_planes(state, crtc); 8228 8229 if (DISPLAY_VER(dev_priv) >= 9) 8230 skl_arm_planes_on_crtc(state, crtc); 8231 else 8232 i9xx_arm_planes_on_crtc(state, crtc); 8233 8234 commit_pipe_post_planes(state, crtc); 8235 8236 intel_pipe_update_end(new_crtc_state); 8237 8238 /* 8239 * We usually enable FIFO underrun interrupts as part of the 8240 * CRTC enable sequence during modesets. But when we inherit a 8241 * valid pipe configuration from the BIOS we need to take care 8242 * of enabling them on the CRTC's first fastset. 8243 */ 8244 if (new_crtc_state->update_pipe && !modeset && 8245 old_crtc_state->inherited) 8246 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state); 8247 } 8248 8249 static void intel_old_crtc_state_disables(struct intel_atomic_state *state, 8250 struct intel_crtc_state *old_crtc_state, 8251 struct intel_crtc_state *new_crtc_state, 8252 struct intel_crtc *crtc) 8253 { 8254 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8255 8256 /* 8257 * We need to disable pipe CRC before disabling the pipe, 8258 * or we race against vblank off. 8259 */ 8260 intel_crtc_disable_pipe_crc(crtc); 8261 8262 dev_priv->display->crtc_disable(state, crtc); 8263 crtc->active = false; 8264 intel_fbc_disable(crtc); 8265 intel_disable_shared_dpll(old_crtc_state); 8266 8267 /* FIXME unify this for all platforms */ 8268 if (!new_crtc_state->hw.active && 8269 !HAS_GMCH(dev_priv)) 8270 intel_initial_watermarks(state, crtc); 8271 } 8272 8273 static void intel_commit_modeset_disables(struct intel_atomic_state *state) 8274 { 8275 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 8276 struct intel_crtc *crtc; 8277 u32 handled = 0; 8278 int i; 8279 8280 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8281 new_crtc_state, i) { 8282 if (!intel_crtc_needs_modeset(new_crtc_state)) 8283 continue; 8284 8285 if (!old_crtc_state->hw.active) 8286 continue; 8287 8288 intel_pre_plane_update(state, crtc); 8289 intel_crtc_disable_planes(state, crtc); 8290 } 8291 8292 /* Only disable port sync and MST slaves */ 8293 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8294 new_crtc_state, i) { 8295 if (!intel_crtc_needs_modeset(new_crtc_state)) 8296 continue; 8297 8298 if (!old_crtc_state->hw.active) 8299 continue; 8300 8301 /* In case of Transcoder port Sync master slave CRTCs can be 8302 * assigned in any order and we need to make sure that 8303 * slave CRTCs are disabled first and then master CRTC since 8304 * Slave vblanks are masked till Master Vblanks. 8305 */ 8306 if (!is_trans_port_sync_slave(old_crtc_state) && 8307 !intel_dp_mst_is_slave_trans(old_crtc_state) && 8308 !old_crtc_state->bigjoiner_slave) 8309 continue; 8310 8311 intel_old_crtc_state_disables(state, old_crtc_state, 8312 new_crtc_state, crtc); 8313 handled |= BIT(crtc->pipe); 8314 } 8315 8316 /* Disable everything else left on */ 8317 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8318 new_crtc_state, i) { 8319 if (!intel_crtc_needs_modeset(new_crtc_state) || 8320 (handled & BIT(crtc->pipe))) 8321 continue; 8322 8323 if (!old_crtc_state->hw.active) 8324 continue; 8325 8326 intel_old_crtc_state_disables(state, old_crtc_state, 8327 new_crtc_state, crtc); 8328 } 8329 } 8330 8331 static void intel_commit_modeset_enables(struct intel_atomic_state *state) 8332 { 8333 struct intel_crtc_state *new_crtc_state; 8334 struct intel_crtc *crtc; 8335 int i; 8336 8337 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8338 if (!new_crtc_state->hw.active) 8339 continue; 8340 8341 intel_enable_crtc(state, crtc); 8342 intel_update_crtc(state, crtc); 8343 } 8344 } 8345 8346 static void skl_commit_modeset_enables(struct intel_atomic_state *state) 8347 { 8348 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8349 struct intel_crtc *crtc; 8350 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 8351 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; 8352 u8 update_pipes = 0, modeset_pipes = 0; 8353 int i; 8354 8355 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 8356 enum pipe pipe = crtc->pipe; 8357 8358 if (!new_crtc_state->hw.active) 8359 continue; 8360 8361 /* ignore allocations for crtc's that have been turned off. */ 8362 if (!intel_crtc_needs_modeset(new_crtc_state)) { 8363 entries[pipe] = old_crtc_state->wm.skl.ddb; 8364 update_pipes |= BIT(pipe); 8365 } else { 8366 modeset_pipes |= BIT(pipe); 8367 } 8368 } 8369 8370 /* 8371 * Whenever the number of active pipes changes, we need to make sure we 8372 * update the pipes in the right order so that their ddb allocations 8373 * never overlap with each other between CRTC updates. Otherwise we'll 8374 * cause pipe underruns and other bad stuff. 8375 * 8376 * So first lets enable all pipes that do not need a fullmodeset as 8377 * those don't have any external dependency. 8378 */ 8379 while (update_pipes) { 8380 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8381 new_crtc_state, i) { 8382 enum pipe pipe = crtc->pipe; 8383 8384 if ((update_pipes & BIT(pipe)) == 0) 8385 continue; 8386 8387 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 8388 entries, I915_MAX_PIPES, pipe)) 8389 continue; 8390 8391 entries[pipe] = new_crtc_state->wm.skl.ddb; 8392 update_pipes &= ~BIT(pipe); 8393 8394 intel_update_crtc(state, crtc); 8395 8396 /* 8397 * If this is an already active pipe, it's DDB changed, 8398 * and this isn't the last pipe that needs updating 8399 * then we need to wait for a vblank to pass for the 8400 * new ddb allocation to take effect. 8401 */ 8402 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, 8403 &old_crtc_state->wm.skl.ddb) && 8404 (update_pipes | modeset_pipes)) 8405 intel_crtc_wait_for_next_vblank(crtc); 8406 } 8407 } 8408 8409 update_pipes = modeset_pipes; 8410 8411 /* 8412 * Enable all pipes that needs a modeset and do not depends on other 8413 * pipes 8414 */ 8415 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8416 enum pipe pipe = crtc->pipe; 8417 8418 if ((modeset_pipes & BIT(pipe)) == 0) 8419 continue; 8420 8421 if (intel_dp_mst_is_slave_trans(new_crtc_state) || 8422 is_trans_port_sync_master(new_crtc_state) || 8423 (new_crtc_state->bigjoiner && !new_crtc_state->bigjoiner_slave)) 8424 continue; 8425 8426 modeset_pipes &= ~BIT(pipe); 8427 8428 intel_enable_crtc(state, crtc); 8429 } 8430 8431 /* 8432 * Then we enable all remaining pipes that depend on other 8433 * pipes: MST slaves and port sync masters, big joiner master 8434 */ 8435 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8436 enum pipe pipe = crtc->pipe; 8437 8438 if ((modeset_pipes & BIT(pipe)) == 0) 8439 continue; 8440 8441 modeset_pipes &= ~BIT(pipe); 8442 8443 intel_enable_crtc(state, crtc); 8444 } 8445 8446 /* 8447 * Finally we do the plane updates/etc. for all pipes that got enabled. 8448 */ 8449 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8450 enum pipe pipe = crtc->pipe; 8451 8452 if ((update_pipes & BIT(pipe)) == 0) 8453 continue; 8454 8455 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 8456 entries, I915_MAX_PIPES, pipe)); 8457 8458 entries[pipe] = new_crtc_state->wm.skl.ddb; 8459 update_pipes &= ~BIT(pipe); 8460 8461 intel_update_crtc(state, crtc); 8462 } 8463 8464 drm_WARN_ON(&dev_priv->drm, modeset_pipes); 8465 drm_WARN_ON(&dev_priv->drm, update_pipes); 8466 } 8467 8468 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) 8469 { 8470 struct intel_atomic_state *state, *next; 8471 struct llist_node *freed; 8472 8473 freed = llist_del_all(&dev_priv->atomic_helper.free_list); 8474 llist_for_each_entry_safe(state, next, freed, freed) 8475 drm_atomic_state_put(&state->base); 8476 } 8477 8478 static void intel_atomic_helper_free_state_worker(struct work_struct *work) 8479 { 8480 struct drm_i915_private *dev_priv = 8481 container_of(work, typeof(*dev_priv), atomic_helper.free_work); 8482 8483 intel_atomic_helper_free_state(dev_priv); 8484 } 8485 8486 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) 8487 { 8488 struct wait_queue_entry wait_fence, wait_reset; 8489 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); 8490 8491 init_wait_entry(&wait_fence, 0); 8492 init_wait_entry(&wait_reset, 0); 8493 for (;;) { 8494 prepare_to_wait(&intel_state->commit_ready.wait, 8495 &wait_fence, TASK_UNINTERRUPTIBLE); 8496 prepare_to_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 8497 I915_RESET_MODESET), 8498 &wait_reset, TASK_UNINTERRUPTIBLE); 8499 8500 8501 if (i915_sw_fence_done(&intel_state->commit_ready) || 8502 test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags)) 8503 break; 8504 8505 schedule(); 8506 } 8507 finish_wait(&intel_state->commit_ready.wait, &wait_fence); 8508 finish_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 8509 I915_RESET_MODESET), 8510 &wait_reset); 8511 } 8512 8513 static void intel_cleanup_dsbs(struct intel_atomic_state *state) 8514 { 8515 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 8516 struct intel_crtc *crtc; 8517 int i; 8518 8519 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8520 new_crtc_state, i) 8521 intel_dsb_cleanup(old_crtc_state); 8522 } 8523 8524 static void intel_atomic_cleanup_work(struct work_struct *work) 8525 { 8526 struct intel_atomic_state *state = 8527 container_of(work, struct intel_atomic_state, base.commit_work); 8528 struct drm_i915_private *i915 = to_i915(state->base.dev); 8529 8530 intel_cleanup_dsbs(state); 8531 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base); 8532 drm_atomic_helper_commit_cleanup_done(&state->base); 8533 drm_atomic_state_put(&state->base); 8534 8535 intel_atomic_helper_free_state(i915); 8536 } 8537 8538 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state) 8539 { 8540 struct drm_i915_private *i915 = to_i915(state->base.dev); 8541 struct intel_plane *plane; 8542 struct intel_plane_state *plane_state; 8543 int i; 8544 8545 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 8546 struct drm_framebuffer *fb = plane_state->hw.fb; 8547 int cc_plane; 8548 int ret; 8549 8550 if (!fb) 8551 continue; 8552 8553 cc_plane = intel_fb_rc_ccs_cc_plane(fb); 8554 if (cc_plane < 0) 8555 continue; 8556 8557 /* 8558 * The layout of the fast clear color value expected by HW 8559 * (the DRM ABI requiring this value to be located in fb at offset 0 of plane#2): 8560 * - 4 x 4 bytes per-channel value 8561 * (in surface type specific float/int format provided by the fb user) 8562 * - 8 bytes native color value used by the display 8563 * (converted/written by GPU during a fast clear operation using the 8564 * above per-channel values) 8565 * 8566 * The commit's FB prepare hook already ensured that FB obj is pinned and the 8567 * caller made sure that the object is synced wrt. the related color clear value 8568 * GPU write on it. 8569 */ 8570 ret = i915_gem_object_read_from_page(intel_fb_obj(fb), 8571 fb->offsets[cc_plane] + 16, 8572 &plane_state->ccval, 8573 sizeof(plane_state->ccval)); 8574 /* The above could only fail if the FB obj has an unexpected backing store type. */ 8575 drm_WARN_ON(&i915->drm, ret); 8576 } 8577 } 8578 8579 static void intel_atomic_commit_tail(struct intel_atomic_state *state) 8580 { 8581 struct drm_device *dev = state->base.dev; 8582 struct drm_i915_private *dev_priv = to_i915(dev); 8583 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 8584 struct intel_crtc *crtc; 8585 u64 put_domains[I915_MAX_PIPES] = {}; 8586 intel_wakeref_t wakeref = 0; 8587 int i; 8588 8589 intel_atomic_commit_fence_wait(state); 8590 8591 drm_atomic_helper_wait_for_dependencies(&state->base); 8592 8593 if (state->modeset) 8594 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); 8595 8596 intel_atomic_prepare_plane_clear_colors(state); 8597 8598 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8599 new_crtc_state, i) { 8600 if (intel_crtc_needs_modeset(new_crtc_state) || 8601 new_crtc_state->update_pipe) { 8602 8603 put_domains[crtc->pipe] = 8604 modeset_get_crtc_power_domains(new_crtc_state); 8605 } 8606 } 8607 8608 intel_commit_modeset_disables(state); 8609 8610 /* FIXME: Eventually get rid of our crtc->config pointer */ 8611 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 8612 crtc->config = new_crtc_state; 8613 8614 if (state->modeset) { 8615 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base); 8616 8617 intel_set_cdclk_pre_plane_update(state); 8618 8619 intel_modeset_verify_disabled(dev_priv, state); 8620 } 8621 8622 intel_sagv_pre_plane_update(state); 8623 8624 /* Complete the events for pipes that have now been disabled */ 8625 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8626 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 8627 8628 /* Complete events for now disable pipes here. */ 8629 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) { 8630 spin_lock_irq(&dev->event_lock); 8631 drm_crtc_send_vblank_event(&crtc->base, 8632 new_crtc_state->uapi.event); 8633 spin_unlock_irq(&dev->event_lock); 8634 8635 new_crtc_state->uapi.event = NULL; 8636 } 8637 } 8638 8639 intel_encoders_update_prepare(state); 8640 8641 intel_dbuf_pre_plane_update(state); 8642 8643 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8644 if (new_crtc_state->uapi.async_flip) 8645 intel_crtc_enable_flip_done(state, crtc); 8646 } 8647 8648 /* Now enable the clocks, plane, pipe, and connectors that we set up. */ 8649 dev_priv->display->commit_modeset_enables(state); 8650 8651 intel_encoders_update_complete(state); 8652 8653 if (state->modeset) 8654 intel_set_cdclk_post_plane_update(state); 8655 8656 intel_wait_for_vblank_workers(state); 8657 8658 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here 8659 * already, but still need the state for the delayed optimization. To 8660 * fix this: 8661 * - wrap the optimization/post_plane_update stuff into a per-crtc work. 8662 * - schedule that vblank worker _before_ calling hw_done 8663 * - at the start of commit_tail, cancel it _synchrously 8664 * - switch over to the vblank wait helper in the core after that since 8665 * we don't need out special handling any more. 8666 */ 8667 drm_atomic_helper_wait_for_flip_done(dev, &state->base); 8668 8669 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8670 if (new_crtc_state->uapi.async_flip) 8671 intel_crtc_disable_flip_done(state, crtc); 8672 } 8673 8674 /* 8675 * Now that the vblank has passed, we can go ahead and program the 8676 * optimal watermarks on platforms that need two-step watermark 8677 * programming. 8678 * 8679 * TODO: Move this (and other cleanup) to an async worker eventually. 8680 */ 8681 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8682 new_crtc_state, i) { 8683 /* 8684 * Gen2 reports pipe underruns whenever all planes are disabled. 8685 * So re-enable underrun reporting after some planes get enabled. 8686 * 8687 * We do this before .optimize_watermarks() so that we have a 8688 * chance of catching underruns with the intermediate watermarks 8689 * vs. the new plane configuration. 8690 */ 8691 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state)) 8692 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 8693 8694 intel_optimize_watermarks(state, crtc); 8695 } 8696 8697 intel_dbuf_post_plane_update(state); 8698 intel_psr_post_plane_update(state); 8699 8700 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 8701 intel_post_plane_update(state, crtc); 8702 8703 modeset_put_crtc_power_domains(crtc, put_domains[crtc->pipe]); 8704 8705 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state); 8706 8707 /* 8708 * DSB cleanup is done in cleanup_work aligning with framebuffer 8709 * cleanup. So copy and reset the dsb structure to sync with 8710 * commit_done and later do dsb cleanup in cleanup_work. 8711 */ 8712 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb); 8713 } 8714 8715 /* Underruns don't always raise interrupts, so check manually */ 8716 intel_check_cpu_fifo_underruns(dev_priv); 8717 intel_check_pch_fifo_underruns(dev_priv); 8718 8719 if (state->modeset) 8720 intel_verify_planes(state); 8721 8722 intel_sagv_post_plane_update(state); 8723 8724 drm_atomic_helper_commit_hw_done(&state->base); 8725 8726 if (state->modeset) { 8727 /* As one of the primary mmio accessors, KMS has a high 8728 * likelihood of triggering bugs in unclaimed access. After we 8729 * finish modesetting, see if an error has been flagged, and if 8730 * so enable debugging for the next modeset - and hope we catch 8731 * the culprit. 8732 */ 8733 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); 8734 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref); 8735 } 8736 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 8737 8738 /* 8739 * Defer the cleanup of the old state to a separate worker to not 8740 * impede the current task (userspace for blocking modesets) that 8741 * are executed inline. For out-of-line asynchronous modesets/flips, 8742 * deferring to a new worker seems overkill, but we would place a 8743 * schedule point (cond_resched()) here anyway to keep latencies 8744 * down. 8745 */ 8746 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work); 8747 queue_work(system_highpri_wq, &state->base.commit_work); 8748 } 8749 8750 static void intel_atomic_commit_work(struct work_struct *work) 8751 { 8752 struct intel_atomic_state *state = 8753 container_of(work, struct intel_atomic_state, base.commit_work); 8754 8755 intel_atomic_commit_tail(state); 8756 } 8757 8758 static int 8759 intel_atomic_commit_ready(struct i915_sw_fence *fence, 8760 enum i915_sw_fence_notify notify) 8761 { 8762 struct intel_atomic_state *state = 8763 container_of(fence, struct intel_atomic_state, commit_ready); 8764 8765 switch (notify) { 8766 case FENCE_COMPLETE: 8767 /* we do blocking waits in the worker, nothing to do here */ 8768 break; 8769 case FENCE_FREE: 8770 { 8771 struct intel_atomic_helper *helper = 8772 &to_i915(state->base.dev)->atomic_helper; 8773 8774 if (llist_add(&state->freed, &helper->free_list)) 8775 schedule_work(&helper->free_work); 8776 break; 8777 } 8778 } 8779 8780 return NOTIFY_DONE; 8781 } 8782 8783 static void intel_atomic_track_fbs(struct intel_atomic_state *state) 8784 { 8785 struct intel_plane_state *old_plane_state, *new_plane_state; 8786 struct intel_plane *plane; 8787 int i; 8788 8789 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 8790 new_plane_state, i) 8791 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), 8792 to_intel_frontbuffer(new_plane_state->hw.fb), 8793 plane->frontbuffer_bit); 8794 } 8795 8796 static int intel_atomic_commit(struct drm_device *dev, 8797 struct drm_atomic_state *_state, 8798 bool nonblock) 8799 { 8800 struct intel_atomic_state *state = to_intel_atomic_state(_state); 8801 struct drm_i915_private *dev_priv = to_i915(dev); 8802 int ret = 0; 8803 8804 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 8805 8806 drm_atomic_state_get(&state->base); 8807 i915_sw_fence_init(&state->commit_ready, 8808 intel_atomic_commit_ready); 8809 8810 /* 8811 * The intel_legacy_cursor_update() fast path takes care 8812 * of avoiding the vblank waits for simple cursor 8813 * movement and flips. For cursor on/off and size changes, 8814 * we want to perform the vblank waits so that watermark 8815 * updates happen during the correct frames. Gen9+ have 8816 * double buffered watermarks and so shouldn't need this. 8817 * 8818 * Unset state->legacy_cursor_update before the call to 8819 * drm_atomic_helper_setup_commit() because otherwise 8820 * drm_atomic_helper_wait_for_flip_done() is a noop and 8821 * we get FIFO underruns because we didn't wait 8822 * for vblank. 8823 * 8824 * FIXME doing watermarks and fb cleanup from a vblank worker 8825 * (assuming we had any) would solve these problems. 8826 */ 8827 if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) { 8828 struct intel_crtc_state *new_crtc_state; 8829 struct intel_crtc *crtc; 8830 int i; 8831 8832 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 8833 if (new_crtc_state->wm.need_postvbl_update || 8834 new_crtc_state->update_wm_post) 8835 state->base.legacy_cursor_update = false; 8836 } 8837 8838 ret = intel_atomic_prepare_commit(state); 8839 if (ret) { 8840 drm_dbg_atomic(&dev_priv->drm, 8841 "Preparing state failed with %i\n", ret); 8842 i915_sw_fence_commit(&state->commit_ready); 8843 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 8844 return ret; 8845 } 8846 8847 ret = drm_atomic_helper_setup_commit(&state->base, nonblock); 8848 if (!ret) 8849 ret = drm_atomic_helper_swap_state(&state->base, true); 8850 if (!ret) 8851 intel_atomic_swap_global_state(state); 8852 8853 if (ret) { 8854 struct intel_crtc_state *new_crtc_state; 8855 struct intel_crtc *crtc; 8856 int i; 8857 8858 i915_sw_fence_commit(&state->commit_ready); 8859 8860 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 8861 intel_dsb_cleanup(new_crtc_state); 8862 8863 drm_atomic_helper_cleanup_planes(dev, &state->base); 8864 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 8865 return ret; 8866 } 8867 intel_shared_dpll_swap_state(state); 8868 intel_atomic_track_fbs(state); 8869 8870 drm_atomic_state_get(&state->base); 8871 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work); 8872 8873 i915_sw_fence_commit(&state->commit_ready); 8874 if (nonblock && state->modeset) { 8875 queue_work(dev_priv->modeset_wq, &state->base.commit_work); 8876 } else if (nonblock) { 8877 queue_work(dev_priv->flip_wq, &state->base.commit_work); 8878 } else { 8879 if (state->modeset) 8880 flush_workqueue(dev_priv->modeset_wq); 8881 intel_atomic_commit_tail(state); 8882 } 8883 8884 return 0; 8885 } 8886 8887 /** 8888 * intel_plane_destroy - destroy a plane 8889 * @plane: plane to destroy 8890 * 8891 * Common destruction function for all types of planes (primary, cursor, 8892 * sprite). 8893 */ 8894 void intel_plane_destroy(struct drm_plane *plane) 8895 { 8896 drm_plane_cleanup(plane); 8897 kfree(to_intel_plane(plane)); 8898 } 8899 8900 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv) 8901 { 8902 struct intel_plane *plane; 8903 8904 for_each_intel_plane(&dev_priv->drm, plane) { 8905 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, 8906 plane->pipe); 8907 8908 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base); 8909 } 8910 } 8911 8912 8913 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 8914 struct drm_file *file) 8915 { 8916 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; 8917 struct drm_crtc *drmmode_crtc; 8918 struct intel_crtc *crtc; 8919 8920 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id); 8921 if (!drmmode_crtc) 8922 return -ENOENT; 8923 8924 crtc = to_intel_crtc(drmmode_crtc); 8925 pipe_from_crtc_id->pipe = crtc->pipe; 8926 8927 return 0; 8928 } 8929 8930 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder) 8931 { 8932 struct drm_device *dev = encoder->base.dev; 8933 struct intel_encoder *source_encoder; 8934 u32 possible_clones = 0; 8935 8936 for_each_intel_encoder(dev, source_encoder) { 8937 if (encoders_cloneable(encoder, source_encoder)) 8938 possible_clones |= drm_encoder_mask(&source_encoder->base); 8939 } 8940 8941 return possible_clones; 8942 } 8943 8944 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder) 8945 { 8946 struct drm_device *dev = encoder->base.dev; 8947 struct intel_crtc *crtc; 8948 u32 possible_crtcs = 0; 8949 8950 for_each_intel_crtc(dev, crtc) { 8951 if (encoder->pipe_mask & BIT(crtc->pipe)) 8952 possible_crtcs |= drm_crtc_mask(&crtc->base); 8953 } 8954 8955 return possible_crtcs; 8956 } 8957 8958 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv) 8959 { 8960 if (!IS_MOBILE(dev_priv)) 8961 return false; 8962 8963 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0) 8964 return false; 8965 8966 if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE)) 8967 return false; 8968 8969 return true; 8970 } 8971 8972 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv) 8973 { 8974 if (DISPLAY_VER(dev_priv) >= 9) 8975 return false; 8976 8977 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) 8978 return false; 8979 8980 if (HAS_PCH_LPT_H(dev_priv) && 8981 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) 8982 return false; 8983 8984 /* DDI E can't be used if DDI A requires 4 lanes */ 8985 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 8986 return false; 8987 8988 if (!dev_priv->vbt.int_crt_support) 8989 return false; 8990 8991 return true; 8992 } 8993 8994 static void intel_setup_outputs(struct drm_i915_private *dev_priv) 8995 { 8996 struct intel_encoder *encoder; 8997 bool dpd_is_edp = false; 8998 8999 intel_pps_unlock_regs_wa(dev_priv); 9000 9001 if (!HAS_DISPLAY(dev_priv)) 9002 return; 9003 9004 if (IS_DG2(dev_priv)) { 9005 intel_ddi_init(dev_priv, PORT_A); 9006 intel_ddi_init(dev_priv, PORT_B); 9007 intel_ddi_init(dev_priv, PORT_C); 9008 intel_ddi_init(dev_priv, PORT_D_XELPD); 9009 } else if (IS_ALDERLAKE_P(dev_priv)) { 9010 intel_ddi_init(dev_priv, PORT_A); 9011 intel_ddi_init(dev_priv, PORT_B); 9012 intel_ddi_init(dev_priv, PORT_TC1); 9013 intel_ddi_init(dev_priv, PORT_TC2); 9014 intel_ddi_init(dev_priv, PORT_TC3); 9015 intel_ddi_init(dev_priv, PORT_TC4); 9016 icl_dsi_init(dev_priv); 9017 } else if (IS_ALDERLAKE_S(dev_priv)) { 9018 intel_ddi_init(dev_priv, PORT_A); 9019 intel_ddi_init(dev_priv, PORT_TC1); 9020 intel_ddi_init(dev_priv, PORT_TC2); 9021 intel_ddi_init(dev_priv, PORT_TC3); 9022 intel_ddi_init(dev_priv, PORT_TC4); 9023 } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) { 9024 intel_ddi_init(dev_priv, PORT_A); 9025 intel_ddi_init(dev_priv, PORT_B); 9026 intel_ddi_init(dev_priv, PORT_TC1); 9027 intel_ddi_init(dev_priv, PORT_TC2); 9028 } else if (DISPLAY_VER(dev_priv) >= 12) { 9029 intel_ddi_init(dev_priv, PORT_A); 9030 intel_ddi_init(dev_priv, PORT_B); 9031 intel_ddi_init(dev_priv, PORT_TC1); 9032 intel_ddi_init(dev_priv, PORT_TC2); 9033 intel_ddi_init(dev_priv, PORT_TC3); 9034 intel_ddi_init(dev_priv, PORT_TC4); 9035 intel_ddi_init(dev_priv, PORT_TC5); 9036 intel_ddi_init(dev_priv, PORT_TC6); 9037 icl_dsi_init(dev_priv); 9038 } else if (IS_JSL_EHL(dev_priv)) { 9039 intel_ddi_init(dev_priv, PORT_A); 9040 intel_ddi_init(dev_priv, PORT_B); 9041 intel_ddi_init(dev_priv, PORT_C); 9042 intel_ddi_init(dev_priv, PORT_D); 9043 icl_dsi_init(dev_priv); 9044 } else if (DISPLAY_VER(dev_priv) == 11) { 9045 intel_ddi_init(dev_priv, PORT_A); 9046 intel_ddi_init(dev_priv, PORT_B); 9047 intel_ddi_init(dev_priv, PORT_C); 9048 intel_ddi_init(dev_priv, PORT_D); 9049 intel_ddi_init(dev_priv, PORT_E); 9050 intel_ddi_init(dev_priv, PORT_F); 9051 icl_dsi_init(dev_priv); 9052 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 9053 intel_ddi_init(dev_priv, PORT_A); 9054 intel_ddi_init(dev_priv, PORT_B); 9055 intel_ddi_init(dev_priv, PORT_C); 9056 vlv_dsi_init(dev_priv); 9057 } else if (DISPLAY_VER(dev_priv) >= 9) { 9058 intel_ddi_init(dev_priv, PORT_A); 9059 intel_ddi_init(dev_priv, PORT_B); 9060 intel_ddi_init(dev_priv, PORT_C); 9061 intel_ddi_init(dev_priv, PORT_D); 9062 intel_ddi_init(dev_priv, PORT_E); 9063 } else if (HAS_DDI(dev_priv)) { 9064 u32 found; 9065 9066 if (intel_ddi_crt_present(dev_priv)) 9067 intel_crt_init(dev_priv); 9068 9069 /* Haswell uses DDI functions to detect digital outputs. */ 9070 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 9071 if (found) 9072 intel_ddi_init(dev_priv, PORT_A); 9073 9074 found = intel_de_read(dev_priv, SFUSE_STRAP); 9075 if (found & SFUSE_STRAP_DDIB_DETECTED) 9076 intel_ddi_init(dev_priv, PORT_B); 9077 if (found & SFUSE_STRAP_DDIC_DETECTED) 9078 intel_ddi_init(dev_priv, PORT_C); 9079 if (found & SFUSE_STRAP_DDID_DETECTED) 9080 intel_ddi_init(dev_priv, PORT_D); 9081 if (found & SFUSE_STRAP_DDIF_DETECTED) 9082 intel_ddi_init(dev_priv, PORT_F); 9083 } else if (HAS_PCH_SPLIT(dev_priv)) { 9084 int found; 9085 9086 /* 9087 * intel_edp_init_connector() depends on this completing first, 9088 * to prevent the registration of both eDP and LVDS and the 9089 * incorrect sharing of the PPS. 9090 */ 9091 intel_lvds_init(dev_priv); 9092 intel_crt_init(dev_priv); 9093 9094 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D); 9095 9096 if (ilk_has_edp_a(dev_priv)) 9097 g4x_dp_init(dev_priv, DP_A, PORT_A); 9098 9099 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) { 9100 /* PCH SDVOB multiplex with HDMIB */ 9101 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); 9102 if (!found) 9103 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); 9104 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED)) 9105 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B); 9106 } 9107 9108 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED) 9109 g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); 9110 9111 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED) 9112 g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D); 9113 9114 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED) 9115 g4x_dp_init(dev_priv, PCH_DP_C, PORT_C); 9116 9117 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED) 9118 g4x_dp_init(dev_priv, PCH_DP_D, PORT_D); 9119 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 9120 bool has_edp, has_port; 9121 9122 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support) 9123 intel_crt_init(dev_priv); 9124 9125 /* 9126 * The DP_DETECTED bit is the latched state of the DDC 9127 * SDA pin at boot. However since eDP doesn't require DDC 9128 * (no way to plug in a DP->HDMI dongle) the DDC pins for 9129 * eDP ports may have been muxed to an alternate function. 9130 * Thus we can't rely on the DP_DETECTED bit alone to detect 9131 * eDP ports. Consult the VBT as well as DP_DETECTED to 9132 * detect eDP ports. 9133 * 9134 * Sadly the straps seem to be missing sometimes even for HDMI 9135 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap 9136 * and VBT for the presence of the port. Additionally we can't 9137 * trust the port type the VBT declares as we've seen at least 9138 * HDMI ports that the VBT claim are DP or eDP. 9139 */ 9140 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B); 9141 has_port = intel_bios_is_port_present(dev_priv, PORT_B); 9142 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port) 9143 has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B); 9144 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) 9145 g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); 9146 9147 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C); 9148 has_port = intel_bios_is_port_present(dev_priv, PORT_C); 9149 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port) 9150 has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C); 9151 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) 9152 g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); 9153 9154 if (IS_CHERRYVIEW(dev_priv)) { 9155 /* 9156 * eDP not supported on port D, 9157 * so no need to worry about it 9158 */ 9159 has_port = intel_bios_is_port_present(dev_priv, PORT_D); 9160 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port) 9161 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D); 9162 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port) 9163 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D); 9164 } 9165 9166 vlv_dsi_init(dev_priv); 9167 } else if (IS_PINEVIEW(dev_priv)) { 9168 intel_lvds_init(dev_priv); 9169 intel_crt_init(dev_priv); 9170 } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) { 9171 bool found = false; 9172 9173 if (IS_MOBILE(dev_priv)) 9174 intel_lvds_init(dev_priv); 9175 9176 intel_crt_init(dev_priv); 9177 9178 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 9179 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n"); 9180 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); 9181 if (!found && IS_G4X(dev_priv)) { 9182 drm_dbg_kms(&dev_priv->drm, 9183 "probing HDMI on SDVOB\n"); 9184 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); 9185 } 9186 9187 if (!found && IS_G4X(dev_priv)) 9188 g4x_dp_init(dev_priv, DP_B, PORT_B); 9189 } 9190 9191 /* Before G4X SDVOC doesn't have its own detect register */ 9192 9193 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 9194 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n"); 9195 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); 9196 } 9197 9198 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) { 9199 9200 if (IS_G4X(dev_priv)) { 9201 drm_dbg_kms(&dev_priv->drm, 9202 "probing HDMI on SDVOC\n"); 9203 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); 9204 } 9205 if (IS_G4X(dev_priv)) 9206 g4x_dp_init(dev_priv, DP_C, PORT_C); 9207 } 9208 9209 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED)) 9210 g4x_dp_init(dev_priv, DP_D, PORT_D); 9211 9212 if (SUPPORTS_TV(dev_priv)) 9213 intel_tv_init(dev_priv); 9214 } else if (DISPLAY_VER(dev_priv) == 2) { 9215 if (IS_I85X(dev_priv)) 9216 intel_lvds_init(dev_priv); 9217 9218 intel_crt_init(dev_priv); 9219 intel_dvo_init(dev_priv); 9220 } 9221 9222 for_each_intel_encoder(&dev_priv->drm, encoder) { 9223 encoder->base.possible_crtcs = 9224 intel_encoder_possible_crtcs(encoder); 9225 encoder->base.possible_clones = 9226 intel_encoder_possible_clones(encoder); 9227 } 9228 9229 intel_init_pch_refclk(dev_priv); 9230 9231 drm_helper_move_panel_connectors_to_head(&dev_priv->drm); 9232 } 9233 9234 static enum drm_mode_status 9235 intel_mode_valid(struct drm_device *dev, 9236 const struct drm_display_mode *mode) 9237 { 9238 struct drm_i915_private *dev_priv = to_i915(dev); 9239 int hdisplay_max, htotal_max; 9240 int vdisplay_max, vtotal_max; 9241 9242 /* 9243 * Can't reject DBLSCAN here because Xorg ddxen can add piles 9244 * of DBLSCAN modes to the output's mode list when they detect 9245 * the scaling mode property on the connector. And they don't 9246 * ask the kernel to validate those modes in any way until 9247 * modeset time at which point the client gets a protocol error. 9248 * So in order to not upset those clients we silently ignore the 9249 * DBLSCAN flag on such connectors. For other connectors we will 9250 * reject modes with the DBLSCAN flag in encoder->compute_config(). 9251 * And we always reject DBLSCAN modes in connector->mode_valid() 9252 * as we never want such modes on the connector's mode list. 9253 */ 9254 9255 if (mode->vscan > 1) 9256 return MODE_NO_VSCAN; 9257 9258 if (mode->flags & DRM_MODE_FLAG_HSKEW) 9259 return MODE_H_ILLEGAL; 9260 9261 if (mode->flags & (DRM_MODE_FLAG_CSYNC | 9262 DRM_MODE_FLAG_NCSYNC | 9263 DRM_MODE_FLAG_PCSYNC)) 9264 return MODE_HSYNC; 9265 9266 if (mode->flags & (DRM_MODE_FLAG_BCAST | 9267 DRM_MODE_FLAG_PIXMUX | 9268 DRM_MODE_FLAG_CLKDIV2)) 9269 return MODE_BAD; 9270 9271 /* Transcoder timing limits */ 9272 if (DISPLAY_VER(dev_priv) >= 11) { 9273 hdisplay_max = 16384; 9274 vdisplay_max = 8192; 9275 htotal_max = 16384; 9276 vtotal_max = 8192; 9277 } else if (DISPLAY_VER(dev_priv) >= 9 || 9278 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 9279 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ 9280 vdisplay_max = 4096; 9281 htotal_max = 8192; 9282 vtotal_max = 8192; 9283 } else if (DISPLAY_VER(dev_priv) >= 3) { 9284 hdisplay_max = 4096; 9285 vdisplay_max = 4096; 9286 htotal_max = 8192; 9287 vtotal_max = 8192; 9288 } else { 9289 hdisplay_max = 2048; 9290 vdisplay_max = 2048; 9291 htotal_max = 4096; 9292 vtotal_max = 4096; 9293 } 9294 9295 if (mode->hdisplay > hdisplay_max || 9296 mode->hsync_start > htotal_max || 9297 mode->hsync_end > htotal_max || 9298 mode->htotal > htotal_max) 9299 return MODE_H_ILLEGAL; 9300 9301 if (mode->vdisplay > vdisplay_max || 9302 mode->vsync_start > vtotal_max || 9303 mode->vsync_end > vtotal_max || 9304 mode->vtotal > vtotal_max) 9305 return MODE_V_ILLEGAL; 9306 9307 if (DISPLAY_VER(dev_priv) >= 5) { 9308 if (mode->hdisplay < 64 || 9309 mode->htotal - mode->hdisplay < 32) 9310 return MODE_H_ILLEGAL; 9311 9312 if (mode->vtotal - mode->vdisplay < 5) 9313 return MODE_V_ILLEGAL; 9314 } else { 9315 if (mode->htotal - mode->hdisplay < 32) 9316 return MODE_H_ILLEGAL; 9317 9318 if (mode->vtotal - mode->vdisplay < 3) 9319 return MODE_V_ILLEGAL; 9320 } 9321 9322 /* 9323 * Cantiga+ cannot handle modes with a hsync front porch of 0. 9324 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. 9325 */ 9326 if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) && 9327 mode->hsync_start == mode->hdisplay) 9328 return MODE_H_ILLEGAL; 9329 9330 return MODE_OK; 9331 } 9332 9333 enum drm_mode_status 9334 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 9335 const struct drm_display_mode *mode, 9336 bool bigjoiner) 9337 { 9338 int plane_width_max, plane_height_max; 9339 9340 /* 9341 * intel_mode_valid() should be 9342 * sufficient on older platforms. 9343 */ 9344 if (DISPLAY_VER(dev_priv) < 9) 9345 return MODE_OK; 9346 9347 /* 9348 * Most people will probably want a fullscreen 9349 * plane so let's not advertize modes that are 9350 * too big for that. 9351 */ 9352 if (DISPLAY_VER(dev_priv) >= 11) { 9353 plane_width_max = 5120 << bigjoiner; 9354 plane_height_max = 4320; 9355 } else { 9356 plane_width_max = 5120; 9357 plane_height_max = 4096; 9358 } 9359 9360 if (mode->hdisplay > plane_width_max) 9361 return MODE_H_ILLEGAL; 9362 9363 if (mode->vdisplay > plane_height_max) 9364 return MODE_V_ILLEGAL; 9365 9366 return MODE_OK; 9367 } 9368 9369 static const struct drm_mode_config_funcs intel_mode_funcs = { 9370 .fb_create = intel_user_framebuffer_create, 9371 .get_format_info = intel_fb_get_format_info, 9372 .output_poll_changed = intel_fbdev_output_poll_changed, 9373 .mode_valid = intel_mode_valid, 9374 .atomic_check = intel_atomic_check, 9375 .atomic_commit = intel_atomic_commit, 9376 .atomic_state_alloc = intel_atomic_state_alloc, 9377 .atomic_state_clear = intel_atomic_state_clear, 9378 .atomic_state_free = intel_atomic_state_free, 9379 }; 9380 9381 static const struct drm_i915_display_funcs skl_display_funcs = { 9382 .get_pipe_config = hsw_get_pipe_config, 9383 .crtc_enable = hsw_crtc_enable, 9384 .crtc_disable = hsw_crtc_disable, 9385 .commit_modeset_enables = skl_commit_modeset_enables, 9386 .get_initial_plane_config = skl_get_initial_plane_config, 9387 }; 9388 9389 static const struct drm_i915_display_funcs ddi_display_funcs = { 9390 .get_pipe_config = hsw_get_pipe_config, 9391 .crtc_enable = hsw_crtc_enable, 9392 .crtc_disable = hsw_crtc_disable, 9393 .commit_modeset_enables = intel_commit_modeset_enables, 9394 .get_initial_plane_config = i9xx_get_initial_plane_config, 9395 }; 9396 9397 static const struct drm_i915_display_funcs pch_split_display_funcs = { 9398 .get_pipe_config = ilk_get_pipe_config, 9399 .crtc_enable = ilk_crtc_enable, 9400 .crtc_disable = ilk_crtc_disable, 9401 .commit_modeset_enables = intel_commit_modeset_enables, 9402 .get_initial_plane_config = i9xx_get_initial_plane_config, 9403 }; 9404 9405 static const struct drm_i915_display_funcs vlv_display_funcs = { 9406 .get_pipe_config = i9xx_get_pipe_config, 9407 .crtc_enable = valleyview_crtc_enable, 9408 .crtc_disable = i9xx_crtc_disable, 9409 .commit_modeset_enables = intel_commit_modeset_enables, 9410 .get_initial_plane_config = i9xx_get_initial_plane_config, 9411 }; 9412 9413 static const struct drm_i915_display_funcs i9xx_display_funcs = { 9414 .get_pipe_config = i9xx_get_pipe_config, 9415 .crtc_enable = i9xx_crtc_enable, 9416 .crtc_disable = i9xx_crtc_disable, 9417 .commit_modeset_enables = intel_commit_modeset_enables, 9418 .get_initial_plane_config = i9xx_get_initial_plane_config, 9419 }; 9420 9421 /** 9422 * intel_init_display_hooks - initialize the display modesetting hooks 9423 * @dev_priv: device private 9424 */ 9425 void intel_init_display_hooks(struct drm_i915_private *dev_priv) 9426 { 9427 if (!HAS_DISPLAY(dev_priv)) 9428 return; 9429 9430 intel_init_cdclk_hooks(dev_priv); 9431 intel_audio_hooks_init(dev_priv); 9432 9433 intel_dpll_init_clock_hook(dev_priv); 9434 9435 if (DISPLAY_VER(dev_priv) >= 9) { 9436 dev_priv->display = &skl_display_funcs; 9437 } else if (HAS_DDI(dev_priv)) { 9438 dev_priv->display = &ddi_display_funcs; 9439 } else if (HAS_PCH_SPLIT(dev_priv)) { 9440 dev_priv->display = &pch_split_display_funcs; 9441 } else if (IS_CHERRYVIEW(dev_priv) || 9442 IS_VALLEYVIEW(dev_priv)) { 9443 dev_priv->display = &vlv_display_funcs; 9444 } else { 9445 dev_priv->display = &i9xx_display_funcs; 9446 } 9447 9448 intel_fdi_init_hook(dev_priv); 9449 } 9450 9451 void intel_modeset_init_hw(struct drm_i915_private *i915) 9452 { 9453 struct intel_cdclk_state *cdclk_state; 9454 9455 if (!HAS_DISPLAY(i915)) 9456 return; 9457 9458 cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state); 9459 9460 intel_update_cdclk(i915); 9461 intel_cdclk_dump_config(i915, &i915->cdclk.hw, "Current CDCLK"); 9462 cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw; 9463 } 9464 9465 static int sanitize_watermarks_add_affected(struct drm_atomic_state *state) 9466 { 9467 struct drm_plane *plane; 9468 struct intel_crtc *crtc; 9469 9470 for_each_intel_crtc(state->dev, crtc) { 9471 struct intel_crtc_state *crtc_state; 9472 9473 crtc_state = intel_atomic_get_crtc_state(state, crtc); 9474 if (IS_ERR(crtc_state)) 9475 return PTR_ERR(crtc_state); 9476 9477 if (crtc_state->hw.active) { 9478 /* 9479 * Preserve the inherited flag to avoid 9480 * taking the full modeset path. 9481 */ 9482 crtc_state->inherited = true; 9483 } 9484 } 9485 9486 drm_for_each_plane(plane, state->dev) { 9487 struct drm_plane_state *plane_state; 9488 9489 plane_state = drm_atomic_get_plane_state(state, plane); 9490 if (IS_ERR(plane_state)) 9491 return PTR_ERR(plane_state); 9492 } 9493 9494 return 0; 9495 } 9496 9497 /* 9498 * Calculate what we think the watermarks should be for the state we've read 9499 * out of the hardware and then immediately program those watermarks so that 9500 * we ensure the hardware settings match our internal state. 9501 * 9502 * We can calculate what we think WM's should be by creating a duplicate of the 9503 * current state (which was constructed during hardware readout) and running it 9504 * through the atomic check code to calculate new watermark values in the 9505 * state object. 9506 */ 9507 static void sanitize_watermarks(struct drm_i915_private *dev_priv) 9508 { 9509 struct drm_atomic_state *state; 9510 struct intel_atomic_state *intel_state; 9511 struct intel_crtc *crtc; 9512 struct intel_crtc_state *crtc_state; 9513 struct drm_modeset_acquire_ctx ctx; 9514 int ret; 9515 int i; 9516 9517 /* Only supported on platforms that use atomic watermark design */ 9518 if (!dev_priv->wm_disp->optimize_watermarks) 9519 return; 9520 9521 state = drm_atomic_state_alloc(&dev_priv->drm); 9522 if (drm_WARN_ON(&dev_priv->drm, !state)) 9523 return; 9524 9525 intel_state = to_intel_atomic_state(state); 9526 9527 drm_modeset_acquire_init(&ctx, 0); 9528 9529 retry: 9530 state->acquire_ctx = &ctx; 9531 9532 /* 9533 * Hardware readout is the only time we don't want to calculate 9534 * intermediate watermarks (since we don't trust the current 9535 * watermarks). 9536 */ 9537 if (!HAS_GMCH(dev_priv)) 9538 intel_state->skip_intermediate_wm = true; 9539 9540 ret = sanitize_watermarks_add_affected(state); 9541 if (ret) 9542 goto fail; 9543 9544 ret = intel_atomic_check(&dev_priv->drm, state); 9545 if (ret) 9546 goto fail; 9547 9548 /* Write calculated watermark values back */ 9549 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) { 9550 crtc_state->wm.need_postvbl_update = true; 9551 intel_optimize_watermarks(intel_state, crtc); 9552 9553 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm; 9554 } 9555 9556 fail: 9557 if (ret == -EDEADLK) { 9558 drm_atomic_state_clear(state); 9559 drm_modeset_backoff(&ctx); 9560 goto retry; 9561 } 9562 9563 /* 9564 * If we fail here, it means that the hardware appears to be 9565 * programmed in a way that shouldn't be possible, given our 9566 * understanding of watermark requirements. This might mean a 9567 * mistake in the hardware readout code or a mistake in the 9568 * watermark calculations for a given platform. Raise a WARN 9569 * so that this is noticeable. 9570 * 9571 * If this actually happens, we'll have to just leave the 9572 * BIOS-programmed watermarks untouched and hope for the best. 9573 */ 9574 drm_WARN(&dev_priv->drm, ret, 9575 "Could not determine valid watermarks for inherited state\n"); 9576 9577 drm_atomic_state_put(state); 9578 9579 drm_modeset_drop_locks(&ctx); 9580 drm_modeset_acquire_fini(&ctx); 9581 } 9582 9583 static int intel_initial_commit(struct drm_device *dev) 9584 { 9585 struct drm_atomic_state *state = NULL; 9586 struct drm_modeset_acquire_ctx ctx; 9587 struct intel_crtc *crtc; 9588 int ret = 0; 9589 9590 state = drm_atomic_state_alloc(dev); 9591 if (!state) 9592 return -ENOMEM; 9593 9594 drm_modeset_acquire_init(&ctx, 0); 9595 9596 retry: 9597 state->acquire_ctx = &ctx; 9598 9599 for_each_intel_crtc(dev, crtc) { 9600 struct intel_crtc_state *crtc_state = 9601 intel_atomic_get_crtc_state(state, crtc); 9602 9603 if (IS_ERR(crtc_state)) { 9604 ret = PTR_ERR(crtc_state); 9605 goto out; 9606 } 9607 9608 if (crtc_state->hw.active) { 9609 struct intel_encoder *encoder; 9610 9611 /* 9612 * We've not yet detected sink capabilities 9613 * (audio,infoframes,etc.) and thus we don't want to 9614 * force a full state recomputation yet. We want that to 9615 * happen only for the first real commit from userspace. 9616 * So preserve the inherited flag for the time being. 9617 */ 9618 crtc_state->inherited = true; 9619 9620 ret = drm_atomic_add_affected_planes(state, &crtc->base); 9621 if (ret) 9622 goto out; 9623 9624 /* 9625 * FIXME hack to force a LUT update to avoid the 9626 * plane update forcing the pipe gamma on without 9627 * having a proper LUT loaded. Remove once we 9628 * have readout for pipe gamma enable. 9629 */ 9630 crtc_state->uapi.color_mgmt_changed = true; 9631 9632 for_each_intel_encoder_mask(dev, encoder, 9633 crtc_state->uapi.encoder_mask) { 9634 if (encoder->initial_fastset_check && 9635 !encoder->initial_fastset_check(encoder, crtc_state)) { 9636 ret = drm_atomic_add_affected_connectors(state, 9637 &crtc->base); 9638 if (ret) 9639 goto out; 9640 } 9641 } 9642 } 9643 } 9644 9645 ret = drm_atomic_commit(state); 9646 9647 out: 9648 if (ret == -EDEADLK) { 9649 drm_atomic_state_clear(state); 9650 drm_modeset_backoff(&ctx); 9651 goto retry; 9652 } 9653 9654 drm_atomic_state_put(state); 9655 9656 drm_modeset_drop_locks(&ctx); 9657 drm_modeset_acquire_fini(&ctx); 9658 9659 return ret; 9660 } 9661 9662 static void intel_mode_config_init(struct drm_i915_private *i915) 9663 { 9664 struct drm_mode_config *mode_config = &i915->drm.mode_config; 9665 9666 drm_mode_config_init(&i915->drm); 9667 INIT_LIST_HEAD(&i915->global_obj_list); 9668 9669 mode_config->min_width = 0; 9670 mode_config->min_height = 0; 9671 9672 mode_config->preferred_depth = 24; 9673 mode_config->prefer_shadow = 1; 9674 9675 mode_config->funcs = &intel_mode_funcs; 9676 9677 mode_config->async_page_flip = HAS_ASYNC_FLIPS(i915); 9678 9679 /* 9680 * Maximum framebuffer dimensions, chosen to match 9681 * the maximum render engine surface size on gen4+. 9682 */ 9683 if (DISPLAY_VER(i915) >= 7) { 9684 mode_config->max_width = 16384; 9685 mode_config->max_height = 16384; 9686 } else if (DISPLAY_VER(i915) >= 4) { 9687 mode_config->max_width = 8192; 9688 mode_config->max_height = 8192; 9689 } else if (DISPLAY_VER(i915) == 3) { 9690 mode_config->max_width = 4096; 9691 mode_config->max_height = 4096; 9692 } else { 9693 mode_config->max_width = 2048; 9694 mode_config->max_height = 2048; 9695 } 9696 9697 if (IS_I845G(i915) || IS_I865G(i915)) { 9698 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512; 9699 mode_config->cursor_height = 1023; 9700 } else if (IS_I830(i915) || IS_I85X(i915) || 9701 IS_I915G(i915) || IS_I915GM(i915)) { 9702 mode_config->cursor_width = 64; 9703 mode_config->cursor_height = 64; 9704 } else { 9705 mode_config->cursor_width = 256; 9706 mode_config->cursor_height = 256; 9707 } 9708 } 9709 9710 static void intel_mode_config_cleanup(struct drm_i915_private *i915) 9711 { 9712 intel_atomic_global_obj_cleanup(i915); 9713 drm_mode_config_cleanup(&i915->drm); 9714 } 9715 9716 /* part #1: call before irq install */ 9717 int intel_modeset_init_noirq(struct drm_i915_private *i915) 9718 { 9719 int ret; 9720 9721 if (i915_inject_probe_failure(i915)) 9722 return -ENODEV; 9723 9724 if (HAS_DISPLAY(i915)) { 9725 ret = drm_vblank_init(&i915->drm, 9726 INTEL_NUM_PIPES(i915)); 9727 if (ret) 9728 return ret; 9729 } 9730 9731 intel_bios_init(i915); 9732 9733 ret = intel_vga_register(i915); 9734 if (ret) 9735 goto cleanup_bios; 9736 9737 /* FIXME: completely on the wrong abstraction layer */ 9738 intel_power_domains_init_hw(i915, false); 9739 9740 if (!HAS_DISPLAY(i915)) 9741 return 0; 9742 9743 intel_dmc_ucode_init(i915); 9744 9745 i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0); 9746 i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI | 9747 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE); 9748 9749 i915->framestart_delay = 1; /* 1-4 */ 9750 9751 i915->window2_delay = 0; /* No DSB so no window2 delay */ 9752 9753 intel_mode_config_init(i915); 9754 9755 ret = intel_cdclk_init(i915); 9756 if (ret) 9757 goto cleanup_vga_client_pw_domain_dmc; 9758 9759 ret = intel_dbuf_init(i915); 9760 if (ret) 9761 goto cleanup_vga_client_pw_domain_dmc; 9762 9763 ret = intel_bw_init(i915); 9764 if (ret) 9765 goto cleanup_vga_client_pw_domain_dmc; 9766 9767 init_llist_head(&i915->atomic_helper.free_list); 9768 INIT_WORK(&i915->atomic_helper.free_work, 9769 intel_atomic_helper_free_state_worker); 9770 9771 intel_init_quirks(i915); 9772 9773 intel_fbc_init(i915); 9774 9775 return 0; 9776 9777 cleanup_vga_client_pw_domain_dmc: 9778 intel_dmc_ucode_fini(i915); 9779 intel_power_domains_driver_remove(i915); 9780 intel_vga_unregister(i915); 9781 cleanup_bios: 9782 intel_bios_driver_remove(i915); 9783 9784 return ret; 9785 } 9786 9787 /* part #2: call after irq install, but before gem init */ 9788 int intel_modeset_init_nogem(struct drm_i915_private *i915) 9789 { 9790 struct drm_device *dev = &i915->drm; 9791 enum pipe pipe; 9792 struct intel_crtc *crtc; 9793 int ret; 9794 9795 if (!HAS_DISPLAY(i915)) 9796 return 0; 9797 9798 intel_init_pm(i915); 9799 9800 intel_panel_sanitize_ssc(i915); 9801 9802 intel_pps_setup(i915); 9803 9804 intel_gmbus_setup(i915); 9805 9806 drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n", 9807 INTEL_NUM_PIPES(i915), 9808 INTEL_NUM_PIPES(i915) > 1 ? "s" : ""); 9809 9810 for_each_pipe(i915, pipe) { 9811 ret = intel_crtc_init(i915, pipe); 9812 if (ret) { 9813 intel_mode_config_cleanup(i915); 9814 return ret; 9815 } 9816 } 9817 9818 intel_plane_possible_crtcs_init(i915); 9819 intel_shared_dpll_init(dev); 9820 intel_fdi_pll_freq_update(i915); 9821 9822 intel_update_czclk(i915); 9823 intel_modeset_init_hw(i915); 9824 intel_dpll_update_ref_clks(i915); 9825 9826 intel_hdcp_component_init(i915); 9827 9828 if (i915->max_cdclk_freq == 0) 9829 intel_update_max_cdclk(i915); 9830 9831 /* 9832 * If the platform has HTI, we need to find out whether it has reserved 9833 * any display resources before we create our display outputs. 9834 */ 9835 if (INTEL_INFO(i915)->display.has_hti) 9836 i915->hti_state = intel_de_read(i915, HDPORT_STATE); 9837 9838 /* Just disable it once at startup */ 9839 intel_vga_disable(i915); 9840 intel_setup_outputs(i915); 9841 9842 drm_modeset_lock_all(dev); 9843 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx); 9844 intel_acpi_assign_connector_fwnodes(i915); 9845 drm_modeset_unlock_all(dev); 9846 9847 for_each_intel_crtc(dev, crtc) { 9848 if (!to_intel_crtc_state(crtc->base.state)->uapi.active) 9849 continue; 9850 intel_crtc_initial_plane_config(crtc); 9851 } 9852 9853 /* 9854 * Make sure hardware watermarks really match the state we read out. 9855 * Note that we need to do this after reconstructing the BIOS fb's 9856 * since the watermark calculation done here will use pstate->fb. 9857 */ 9858 if (!HAS_GMCH(i915)) 9859 sanitize_watermarks(i915); 9860 9861 return 0; 9862 } 9863 9864 /* part #3: call after gem init */ 9865 int intel_modeset_init(struct drm_i915_private *i915) 9866 { 9867 int ret; 9868 9869 if (!HAS_DISPLAY(i915)) 9870 return 0; 9871 9872 /* 9873 * Force all active planes to recompute their states. So that on 9874 * mode_setcrtc after probe, all the intel_plane_state variables 9875 * are already calculated and there is no assert_plane warnings 9876 * during bootup. 9877 */ 9878 ret = intel_initial_commit(&i915->drm); 9879 if (ret) 9880 drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret); 9881 9882 intel_overlay_setup(i915); 9883 9884 ret = intel_fbdev_init(&i915->drm); 9885 if (ret) 9886 return ret; 9887 9888 /* Only enable hotplug handling once the fbdev is fully set up. */ 9889 intel_hpd_init(i915); 9890 intel_hpd_poll_disable(i915); 9891 9892 intel_init_ipc(i915); 9893 9894 return 0; 9895 } 9896 9897 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 9898 { 9899 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 9900 /* 640x480@60Hz, ~25175 kHz */ 9901 struct dpll clock = { 9902 .m1 = 18, 9903 .m2 = 7, 9904 .p1 = 13, 9905 .p2 = 4, 9906 .n = 2, 9907 }; 9908 u32 dpll, fp; 9909 int i; 9910 9911 drm_WARN_ON(&dev_priv->drm, 9912 i9xx_calc_dpll_params(48000, &clock) != 25154); 9913 9914 drm_dbg_kms(&dev_priv->drm, 9915 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n", 9916 pipe_name(pipe), clock.vco, clock.dot); 9917 9918 fp = i9xx_dpll_compute_fp(&clock); 9919 dpll = DPLL_DVO_2X_MODE | 9920 DPLL_VGA_MODE_DIS | 9921 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | 9922 PLL_P2_DIVIDE_BY_4 | 9923 PLL_REF_INPUT_DREFCLK | 9924 DPLL_VCO_ENABLE; 9925 9926 intel_de_write(dev_priv, FP0(pipe), fp); 9927 intel_de_write(dev_priv, FP1(pipe), fp); 9928 9929 intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16)); 9930 intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16)); 9931 intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16)); 9932 intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16)); 9933 intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16)); 9934 intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16)); 9935 intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1)); 9936 9937 /* 9938 * Apparently we need to have VGA mode enabled prior to changing 9939 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 9940 * dividers, even though the register value does change. 9941 */ 9942 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); 9943 intel_de_write(dev_priv, DPLL(pipe), dpll); 9944 9945 /* Wait for the clocks to stabilize. */ 9946 intel_de_posting_read(dev_priv, DPLL(pipe)); 9947 udelay(150); 9948 9949 /* The pixel multiplier can only be updated once the 9950 * DPLL is enabled and the clocks are stable. 9951 * 9952 * So write it again. 9953 */ 9954 intel_de_write(dev_priv, DPLL(pipe), dpll); 9955 9956 /* We do this three times for luck */ 9957 for (i = 0; i < 3 ; i++) { 9958 intel_de_write(dev_priv, DPLL(pipe), dpll); 9959 intel_de_posting_read(dev_priv, DPLL(pipe)); 9960 udelay(150); /* wait for warmup */ 9961 } 9962 9963 intel_de_write(dev_priv, PIPECONF(pipe), PIPECONF_ENABLE); 9964 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 9965 9966 intel_wait_for_pipe_scanline_moving(crtc); 9967 } 9968 9969 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 9970 { 9971 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 9972 9973 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n", 9974 pipe_name(pipe)); 9975 9976 drm_WARN_ON(&dev_priv->drm, 9977 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE); 9978 drm_WARN_ON(&dev_priv->drm, 9979 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE); 9980 drm_WARN_ON(&dev_priv->drm, 9981 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE); 9982 drm_WARN_ON(&dev_priv->drm, 9983 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK); 9984 drm_WARN_ON(&dev_priv->drm, 9985 intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK); 9986 9987 intel_de_write(dev_priv, PIPECONF(pipe), 0); 9988 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 9989 9990 intel_wait_for_pipe_scanline_stopped(crtc); 9991 9992 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); 9993 intel_de_posting_read(dev_priv, DPLL(pipe)); 9994 } 9995 9996 static void 9997 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv) 9998 { 9999 struct intel_crtc *crtc; 10000 10001 if (DISPLAY_VER(dev_priv) >= 4) 10002 return; 10003 10004 for_each_intel_crtc(&dev_priv->drm, crtc) { 10005 struct intel_plane *plane = 10006 to_intel_plane(crtc->base.primary); 10007 struct intel_crtc *plane_crtc; 10008 enum pipe pipe; 10009 10010 if (!plane->get_hw_state(plane, &pipe)) 10011 continue; 10012 10013 if (pipe == crtc->pipe) 10014 continue; 10015 10016 drm_dbg_kms(&dev_priv->drm, 10017 "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n", 10018 plane->base.base.id, plane->base.name); 10019 10020 plane_crtc = intel_crtc_for_pipe(dev_priv, pipe); 10021 intel_plane_disable_noatomic(plane_crtc, plane); 10022 } 10023 } 10024 10025 static bool intel_crtc_has_encoders(struct intel_crtc *crtc) 10026 { 10027 struct drm_device *dev = crtc->base.dev; 10028 struct intel_encoder *encoder; 10029 10030 for_each_encoder_on_crtc(dev, &crtc->base, encoder) 10031 return true; 10032 10033 return false; 10034 } 10035 10036 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) 10037 { 10038 struct drm_device *dev = encoder->base.dev; 10039 struct intel_connector *connector; 10040 10041 for_each_connector_on_encoder(dev, &encoder->base, connector) 10042 return connector; 10043 10044 return NULL; 10045 } 10046 10047 static bool has_pch_trancoder(struct drm_i915_private *dev_priv, 10048 enum pipe pch_transcoder) 10049 { 10050 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || 10051 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A); 10052 } 10053 10054 static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc_state) 10055 { 10056 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 10057 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 10058 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 10059 10060 if (DISPLAY_VER(dev_priv) >= 9 || 10061 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 10062 i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder); 10063 u32 val; 10064 10065 if (transcoder_is_dsi(cpu_transcoder)) 10066 return; 10067 10068 val = intel_de_read(dev_priv, reg); 10069 val &= ~HSW_FRAME_START_DELAY_MASK; 10070 val |= HSW_FRAME_START_DELAY(dev_priv->framestart_delay - 1); 10071 intel_de_write(dev_priv, reg, val); 10072 } else { 10073 i915_reg_t reg = PIPECONF(cpu_transcoder); 10074 u32 val; 10075 10076 val = intel_de_read(dev_priv, reg); 10077 val &= ~PIPECONF_FRAME_START_DELAY_MASK; 10078 val |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay - 1); 10079 intel_de_write(dev_priv, reg, val); 10080 } 10081 10082 if (!crtc_state->has_pch_encoder) 10083 return; 10084 10085 if (HAS_PCH_IBX(dev_priv)) { 10086 i915_reg_t reg = PCH_TRANSCONF(crtc->pipe); 10087 u32 val; 10088 10089 val = intel_de_read(dev_priv, reg); 10090 val &= ~TRANS_FRAME_START_DELAY_MASK; 10091 val |= TRANS_FRAME_START_DELAY(dev_priv->framestart_delay - 1); 10092 intel_de_write(dev_priv, reg, val); 10093 } else { 10094 enum pipe pch_transcoder = intel_crtc_pch_transcoder(crtc); 10095 i915_reg_t reg = TRANS_CHICKEN2(pch_transcoder); 10096 u32 val; 10097 10098 val = intel_de_read(dev_priv, reg); 10099 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; 10100 val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1); 10101 intel_de_write(dev_priv, reg, val); 10102 } 10103 } 10104 10105 static void intel_sanitize_crtc(struct intel_crtc *crtc, 10106 struct drm_modeset_acquire_ctx *ctx) 10107 { 10108 struct drm_device *dev = crtc->base.dev; 10109 struct drm_i915_private *dev_priv = to_i915(dev); 10110 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); 10111 10112 if (crtc_state->hw.active) { 10113 struct intel_plane *plane; 10114 10115 /* Clear any frame start delays used for debugging left by the BIOS */ 10116 intel_sanitize_frame_start_delay(crtc_state); 10117 10118 /* Disable everything but the primary plane */ 10119 for_each_intel_plane_on_crtc(dev, crtc, plane) { 10120 const struct intel_plane_state *plane_state = 10121 to_intel_plane_state(plane->base.state); 10122 10123 if (plane_state->uapi.visible && 10124 plane->base.type != DRM_PLANE_TYPE_PRIMARY) 10125 intel_plane_disable_noatomic(crtc, plane); 10126 } 10127 10128 /* Disable any background color/etc. set by the BIOS */ 10129 intel_color_commit(crtc_state); 10130 } 10131 10132 /* Adjust the state of the output pipe according to whether we 10133 * have active connectors/encoders. */ 10134 if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) && 10135 !crtc_state->bigjoiner_slave) 10136 intel_crtc_disable_noatomic(crtc, ctx); 10137 10138 if (crtc_state->hw.active || HAS_GMCH(dev_priv)) { 10139 /* 10140 * We start out with underrun reporting disabled to avoid races. 10141 * For correct bookkeeping mark this on active crtcs. 10142 * 10143 * Also on gmch platforms we dont have any hardware bits to 10144 * disable the underrun reporting. Which means we need to start 10145 * out with underrun reporting disabled also on inactive pipes, 10146 * since otherwise we'll complain about the garbage we read when 10147 * e.g. coming up after runtime pm. 10148 * 10149 * No protection against concurrent access is required - at 10150 * worst a fifo underrun happens which also sets this to false. 10151 */ 10152 crtc->cpu_fifo_underrun_disabled = true; 10153 /* 10154 * We track the PCH trancoder underrun reporting state 10155 * within the crtc. With crtc for pipe A housing the underrun 10156 * reporting state for PCH transcoder A, crtc for pipe B housing 10157 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, 10158 * and marking underrun reporting as disabled for the non-existing 10159 * PCH transcoders B and C would prevent enabling the south 10160 * error interrupt (see cpt_can_enable_serr_int()). 10161 */ 10162 if (has_pch_trancoder(dev_priv, crtc->pipe)) 10163 crtc->pch_fifo_underrun_disabled = true; 10164 } 10165 } 10166 10167 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state) 10168 { 10169 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 10170 10171 /* 10172 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram 10173 * the hardware when a high res displays plugged in. DPLL P 10174 * divider is zero, and the pipe timings are bonkers. We'll 10175 * try to disable everything in that case. 10176 * 10177 * FIXME would be nice to be able to sanitize this state 10178 * without several WARNs, but for now let's take the easy 10179 * road. 10180 */ 10181 return IS_SANDYBRIDGE(dev_priv) && 10182 crtc_state->hw.active && 10183 crtc_state->shared_dpll && 10184 crtc_state->port_clock == 0; 10185 } 10186 10187 static void intel_sanitize_encoder(struct intel_encoder *encoder) 10188 { 10189 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 10190 struct intel_connector *connector; 10191 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 10192 struct intel_crtc_state *crtc_state = crtc ? 10193 to_intel_crtc_state(crtc->base.state) : NULL; 10194 10195 /* We need to check both for a crtc link (meaning that the 10196 * encoder is active and trying to read from a pipe) and the 10197 * pipe itself being active. */ 10198 bool has_active_crtc = crtc_state && 10199 crtc_state->hw.active; 10200 10201 if (crtc_state && has_bogus_dpll_config(crtc_state)) { 10202 drm_dbg_kms(&dev_priv->drm, 10203 "BIOS has misprogrammed the hardware. Disabling pipe %c\n", 10204 pipe_name(crtc->pipe)); 10205 has_active_crtc = false; 10206 } 10207 10208 connector = intel_encoder_find_connector(encoder); 10209 if (connector && !has_active_crtc) { 10210 drm_dbg_kms(&dev_priv->drm, 10211 "[ENCODER:%d:%s] has active connectors but no active pipe!\n", 10212 encoder->base.base.id, 10213 encoder->base.name); 10214 10215 /* Connector is active, but has no active pipe. This is 10216 * fallout from our resume register restoring. Disable 10217 * the encoder manually again. */ 10218 if (crtc_state) { 10219 struct drm_encoder *best_encoder; 10220 10221 drm_dbg_kms(&dev_priv->drm, 10222 "[ENCODER:%d:%s] manually disabled\n", 10223 encoder->base.base.id, 10224 encoder->base.name); 10225 10226 /* avoid oopsing in case the hooks consult best_encoder */ 10227 best_encoder = connector->base.state->best_encoder; 10228 connector->base.state->best_encoder = &encoder->base; 10229 10230 /* FIXME NULL atomic state passed! */ 10231 if (encoder->disable) 10232 encoder->disable(NULL, encoder, crtc_state, 10233 connector->base.state); 10234 if (encoder->post_disable) 10235 encoder->post_disable(NULL, encoder, crtc_state, 10236 connector->base.state); 10237 10238 connector->base.state->best_encoder = best_encoder; 10239 } 10240 encoder->base.crtc = NULL; 10241 10242 /* Inconsistent output/port/pipe state happens presumably due to 10243 * a bug in one of the get_hw_state functions. Or someplace else 10244 * in our code, like the register restore mess on resume. Clamp 10245 * things to off as a safer default. */ 10246 10247 connector->base.dpms = DRM_MODE_DPMS_OFF; 10248 connector->base.encoder = NULL; 10249 } 10250 10251 /* notify opregion of the sanitized encoder state */ 10252 intel_opregion_notify_encoder(encoder, connector && has_active_crtc); 10253 10254 if (HAS_DDI(dev_priv)) 10255 intel_ddi_sanitize_encoder_pll_mapping(encoder); 10256 } 10257 10258 /* FIXME read out full plane state for all planes */ 10259 static void readout_plane_state(struct drm_i915_private *dev_priv) 10260 { 10261 struct intel_plane *plane; 10262 struct intel_crtc *crtc; 10263 10264 for_each_intel_plane(&dev_priv->drm, plane) { 10265 struct intel_plane_state *plane_state = 10266 to_intel_plane_state(plane->base.state); 10267 struct intel_crtc_state *crtc_state; 10268 enum pipe pipe = PIPE_A; 10269 bool visible; 10270 10271 visible = plane->get_hw_state(plane, &pipe); 10272 10273 crtc = intel_crtc_for_pipe(dev_priv, pipe); 10274 crtc_state = to_intel_crtc_state(crtc->base.state); 10275 10276 intel_set_plane_visible(crtc_state, plane_state, visible); 10277 10278 drm_dbg_kms(&dev_priv->drm, 10279 "[PLANE:%d:%s] hw state readout: %s, pipe %c\n", 10280 plane->base.base.id, plane->base.name, 10281 enableddisabled(visible), pipe_name(pipe)); 10282 } 10283 10284 for_each_intel_crtc(&dev_priv->drm, crtc) { 10285 struct intel_crtc_state *crtc_state = 10286 to_intel_crtc_state(crtc->base.state); 10287 10288 fixup_plane_bitmasks(crtc_state); 10289 } 10290 } 10291 10292 static void intel_modeset_readout_hw_state(struct drm_device *dev) 10293 { 10294 struct drm_i915_private *dev_priv = to_i915(dev); 10295 struct intel_cdclk_state *cdclk_state = 10296 to_intel_cdclk_state(dev_priv->cdclk.obj.state); 10297 struct intel_dbuf_state *dbuf_state = 10298 to_intel_dbuf_state(dev_priv->dbuf.obj.state); 10299 enum pipe pipe; 10300 struct intel_crtc *crtc; 10301 struct intel_encoder *encoder; 10302 struct intel_connector *connector; 10303 struct drm_connector_list_iter conn_iter; 10304 u8 active_pipes = 0; 10305 10306 for_each_intel_crtc(dev, crtc) { 10307 struct intel_crtc_state *crtc_state = 10308 to_intel_crtc_state(crtc->base.state); 10309 10310 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi); 10311 intel_crtc_free_hw_state(crtc_state); 10312 intel_crtc_state_reset(crtc_state, crtc); 10313 10314 intel_crtc_get_pipe_config(crtc_state); 10315 10316 crtc_state->hw.enable = crtc_state->hw.active; 10317 10318 crtc->base.enabled = crtc_state->hw.enable; 10319 crtc->active = crtc_state->hw.active; 10320 10321 if (crtc_state->hw.active) 10322 active_pipes |= BIT(crtc->pipe); 10323 10324 drm_dbg_kms(&dev_priv->drm, 10325 "[CRTC:%d:%s] hw state readout: %s\n", 10326 crtc->base.base.id, crtc->base.name, 10327 enableddisabled(crtc_state->hw.active)); 10328 } 10329 10330 cdclk_state->active_pipes = dbuf_state->active_pipes = active_pipes; 10331 10332 readout_plane_state(dev_priv); 10333 10334 for_each_intel_encoder(dev, encoder) { 10335 struct intel_crtc_state *crtc_state = NULL; 10336 10337 pipe = 0; 10338 10339 if (encoder->get_hw_state(encoder, &pipe)) { 10340 crtc = intel_crtc_for_pipe(dev_priv, pipe); 10341 crtc_state = to_intel_crtc_state(crtc->base.state); 10342 10343 encoder->base.crtc = &crtc->base; 10344 intel_encoder_get_config(encoder, crtc_state); 10345 10346 /* read out to slave crtc as well for bigjoiner */ 10347 if (crtc_state->bigjoiner) { 10348 /* encoder should read be linked to bigjoiner master */ 10349 WARN_ON(crtc_state->bigjoiner_slave); 10350 10351 crtc = crtc_state->bigjoiner_linked_crtc; 10352 crtc_state = to_intel_crtc_state(crtc->base.state); 10353 intel_encoder_get_config(encoder, crtc_state); 10354 } 10355 } else { 10356 encoder->base.crtc = NULL; 10357 } 10358 10359 if (encoder->sync_state) 10360 encoder->sync_state(encoder, crtc_state); 10361 10362 drm_dbg_kms(&dev_priv->drm, 10363 "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", 10364 encoder->base.base.id, encoder->base.name, 10365 enableddisabled(encoder->base.crtc), 10366 pipe_name(pipe)); 10367 } 10368 10369 intel_dpll_readout_hw_state(dev_priv); 10370 10371 drm_connector_list_iter_begin(dev, &conn_iter); 10372 for_each_intel_connector_iter(connector, &conn_iter) { 10373 if (connector->get_hw_state(connector)) { 10374 struct intel_crtc_state *crtc_state; 10375 struct intel_crtc *crtc; 10376 10377 connector->base.dpms = DRM_MODE_DPMS_ON; 10378 10379 encoder = intel_attached_encoder(connector); 10380 connector->base.encoder = &encoder->base; 10381 10382 crtc = to_intel_crtc(encoder->base.crtc); 10383 crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL; 10384 10385 if (crtc_state && crtc_state->hw.active) { 10386 /* 10387 * This has to be done during hardware readout 10388 * because anything calling .crtc_disable may 10389 * rely on the connector_mask being accurate. 10390 */ 10391 crtc_state->uapi.connector_mask |= 10392 drm_connector_mask(&connector->base); 10393 crtc_state->uapi.encoder_mask |= 10394 drm_encoder_mask(&encoder->base); 10395 } 10396 } else { 10397 connector->base.dpms = DRM_MODE_DPMS_OFF; 10398 connector->base.encoder = NULL; 10399 } 10400 drm_dbg_kms(&dev_priv->drm, 10401 "[CONNECTOR:%d:%s] hw state readout: %s\n", 10402 connector->base.base.id, connector->base.name, 10403 enableddisabled(connector->base.encoder)); 10404 } 10405 drm_connector_list_iter_end(&conn_iter); 10406 10407 for_each_intel_crtc(dev, crtc) { 10408 struct intel_bw_state *bw_state = 10409 to_intel_bw_state(dev_priv->bw_obj.state); 10410 struct intel_crtc_state *crtc_state = 10411 to_intel_crtc_state(crtc->base.state); 10412 struct intel_plane *plane; 10413 int min_cdclk = 0; 10414 10415 if (crtc_state->hw.active) { 10416 /* 10417 * The initial mode needs to be set in order to keep 10418 * the atomic core happy. It wants a valid mode if the 10419 * crtc's enabled, so we do the above call. 10420 * 10421 * But we don't set all the derived state fully, hence 10422 * set a flag to indicate that a full recalculation is 10423 * needed on the next commit. 10424 */ 10425 crtc_state->inherited = true; 10426 10427 intel_crtc_update_active_timings(crtc_state); 10428 10429 intel_crtc_copy_hw_to_uapi_state(crtc_state); 10430 } 10431 10432 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 10433 const struct intel_plane_state *plane_state = 10434 to_intel_plane_state(plane->base.state); 10435 10436 /* 10437 * FIXME don't have the fb yet, so can't 10438 * use intel_plane_data_rate() :( 10439 */ 10440 if (plane_state->uapi.visible) 10441 crtc_state->data_rate[plane->id] = 10442 4 * crtc_state->pixel_rate; 10443 /* 10444 * FIXME don't have the fb yet, so can't 10445 * use plane->min_cdclk() :( 10446 */ 10447 if (plane_state->uapi.visible && plane->min_cdclk) { 10448 if (crtc_state->double_wide || DISPLAY_VER(dev_priv) >= 10) 10449 crtc_state->min_cdclk[plane->id] = 10450 DIV_ROUND_UP(crtc_state->pixel_rate, 2); 10451 else 10452 crtc_state->min_cdclk[plane->id] = 10453 crtc_state->pixel_rate; 10454 } 10455 drm_dbg_kms(&dev_priv->drm, 10456 "[PLANE:%d:%s] min_cdclk %d kHz\n", 10457 plane->base.base.id, plane->base.name, 10458 crtc_state->min_cdclk[plane->id]); 10459 } 10460 10461 if (crtc_state->hw.active) { 10462 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); 10463 if (drm_WARN_ON(dev, min_cdclk < 0)) 10464 min_cdclk = 0; 10465 } 10466 10467 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; 10468 cdclk_state->min_voltage_level[crtc->pipe] = 10469 crtc_state->min_voltage_level; 10470 10471 intel_bw_crtc_update(bw_state, crtc_state); 10472 10473 intel_pipe_config_sanity_check(dev_priv, crtc_state); 10474 } 10475 } 10476 10477 static void 10478 get_encoder_power_domains(struct drm_i915_private *dev_priv) 10479 { 10480 struct intel_encoder *encoder; 10481 10482 for_each_intel_encoder(&dev_priv->drm, encoder) { 10483 struct intel_crtc_state *crtc_state; 10484 10485 if (!encoder->get_power_domains) 10486 continue; 10487 10488 /* 10489 * MST-primary and inactive encoders don't have a crtc state 10490 * and neither of these require any power domain references. 10491 */ 10492 if (!encoder->base.crtc) 10493 continue; 10494 10495 crtc_state = to_intel_crtc_state(encoder->base.crtc->state); 10496 encoder->get_power_domains(encoder, crtc_state); 10497 } 10498 } 10499 10500 static void intel_early_display_was(struct drm_i915_private *dev_priv) 10501 { 10502 /* 10503 * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl 10504 * Also known as Wa_14010480278. 10505 */ 10506 if (IS_DISPLAY_VER(dev_priv, 10, 12)) 10507 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0, 10508 intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS); 10509 10510 if (IS_HASWELL(dev_priv)) { 10511 /* 10512 * WaRsPkgCStateDisplayPMReq:hsw 10513 * System hang if this isn't done before disabling all planes! 10514 */ 10515 intel_de_write(dev_priv, CHICKEN_PAR1_1, 10516 intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); 10517 } 10518 10519 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) { 10520 /* Display WA #1142:kbl,cfl,cml */ 10521 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 10522 KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22); 10523 intel_de_rmw(dev_priv, CHICKEN_MISC_2, 10524 KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14, 10525 KBL_ARB_FILL_SPARE_14); 10526 } 10527 } 10528 10529 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv, 10530 enum port port, i915_reg_t hdmi_reg) 10531 { 10532 u32 val = intel_de_read(dev_priv, hdmi_reg); 10533 10534 if (val & SDVO_ENABLE || 10535 (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A)) 10536 return; 10537 10538 drm_dbg_kms(&dev_priv->drm, 10539 "Sanitizing transcoder select for HDMI %c\n", 10540 port_name(port)); 10541 10542 val &= ~SDVO_PIPE_SEL_MASK; 10543 val |= SDVO_PIPE_SEL(PIPE_A); 10544 10545 intel_de_write(dev_priv, hdmi_reg, val); 10546 } 10547 10548 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv, 10549 enum port port, i915_reg_t dp_reg) 10550 { 10551 u32 val = intel_de_read(dev_priv, dp_reg); 10552 10553 if (val & DP_PORT_EN || 10554 (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A)) 10555 return; 10556 10557 drm_dbg_kms(&dev_priv->drm, 10558 "Sanitizing transcoder select for DP %c\n", 10559 port_name(port)); 10560 10561 val &= ~DP_PIPE_SEL_MASK; 10562 val |= DP_PIPE_SEL(PIPE_A); 10563 10564 intel_de_write(dev_priv, dp_reg, val); 10565 } 10566 10567 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv) 10568 { 10569 /* 10570 * The BIOS may select transcoder B on some of the PCH 10571 * ports even it doesn't enable the port. This would trip 10572 * assert_pch_dp_disabled() and assert_pch_hdmi_disabled(). 10573 * Sanitize the transcoder select bits to prevent that. We 10574 * assume that the BIOS never actually enabled the port, 10575 * because if it did we'd actually have to toggle the port 10576 * on and back off to make the transcoder A select stick 10577 * (see. intel_dp_link_down(), intel_disable_hdmi(), 10578 * intel_disable_sdvo()). 10579 */ 10580 ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B); 10581 ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C); 10582 ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D); 10583 10584 /* PCH SDVOB multiplex with HDMIB */ 10585 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB); 10586 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC); 10587 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID); 10588 } 10589 10590 /* Scan out the current hw modeset state, 10591 * and sanitizes it to the current state 10592 */ 10593 static void 10594 intel_modeset_setup_hw_state(struct drm_device *dev, 10595 struct drm_modeset_acquire_ctx *ctx) 10596 { 10597 struct drm_i915_private *dev_priv = to_i915(dev); 10598 struct intel_encoder *encoder; 10599 struct intel_crtc *crtc; 10600 intel_wakeref_t wakeref; 10601 10602 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 10603 10604 intel_early_display_was(dev_priv); 10605 intel_modeset_readout_hw_state(dev); 10606 10607 /* HW state is read out, now we need to sanitize this mess. */ 10608 get_encoder_power_domains(dev_priv); 10609 10610 if (HAS_PCH_IBX(dev_priv)) 10611 ibx_sanitize_pch_ports(dev_priv); 10612 10613 /* 10614 * intel_sanitize_plane_mapping() may need to do vblank 10615 * waits, so we need vblank interrupts restored beforehand. 10616 */ 10617 for_each_intel_crtc(&dev_priv->drm, crtc) { 10618 struct intel_crtc_state *crtc_state = 10619 to_intel_crtc_state(crtc->base.state); 10620 10621 drm_crtc_vblank_reset(&crtc->base); 10622 10623 if (crtc_state->hw.active) 10624 intel_crtc_vblank_on(crtc_state); 10625 } 10626 10627 intel_sanitize_plane_mapping(dev_priv); 10628 10629 for_each_intel_encoder(dev, encoder) 10630 intel_sanitize_encoder(encoder); 10631 10632 for_each_intel_crtc(&dev_priv->drm, crtc) { 10633 struct intel_crtc_state *crtc_state = 10634 to_intel_crtc_state(crtc->base.state); 10635 10636 intel_sanitize_crtc(crtc, ctx); 10637 intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]"); 10638 } 10639 10640 intel_modeset_update_connector_atomic_state(dev); 10641 10642 intel_dpll_sanitize_state(dev_priv); 10643 10644 if (IS_G4X(dev_priv)) { 10645 g4x_wm_get_hw_state(dev_priv); 10646 g4x_wm_sanitize(dev_priv); 10647 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 10648 vlv_wm_get_hw_state(dev_priv); 10649 vlv_wm_sanitize(dev_priv); 10650 } else if (DISPLAY_VER(dev_priv) >= 9) { 10651 skl_wm_get_hw_state(dev_priv); 10652 skl_wm_sanitize(dev_priv); 10653 } else if (HAS_PCH_SPLIT(dev_priv)) { 10654 ilk_wm_get_hw_state(dev_priv); 10655 } 10656 10657 for_each_intel_crtc(dev, crtc) { 10658 struct intel_crtc_state *crtc_state = 10659 to_intel_crtc_state(crtc->base.state); 10660 u64 put_domains; 10661 10662 put_domains = modeset_get_crtc_power_domains(crtc_state); 10663 if (drm_WARN_ON(dev, put_domains)) 10664 modeset_put_crtc_power_domains(crtc, put_domains); 10665 } 10666 10667 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref); 10668 10669 intel_power_domains_sanitize_state(dev_priv); 10670 } 10671 10672 void intel_display_resume(struct drm_device *dev) 10673 { 10674 struct drm_i915_private *dev_priv = to_i915(dev); 10675 struct drm_atomic_state *state = dev_priv->modeset_restore_state; 10676 struct drm_modeset_acquire_ctx ctx; 10677 int ret; 10678 10679 if (!HAS_DISPLAY(dev_priv)) 10680 return; 10681 10682 dev_priv->modeset_restore_state = NULL; 10683 if (state) 10684 state->acquire_ctx = &ctx; 10685 10686 drm_modeset_acquire_init(&ctx, 0); 10687 10688 while (1) { 10689 ret = drm_modeset_lock_all_ctx(dev, &ctx); 10690 if (ret != -EDEADLK) 10691 break; 10692 10693 drm_modeset_backoff(&ctx); 10694 } 10695 10696 if (!ret) 10697 ret = __intel_display_resume(dev, state, &ctx); 10698 10699 intel_enable_ipc(dev_priv); 10700 drm_modeset_drop_locks(&ctx); 10701 drm_modeset_acquire_fini(&ctx); 10702 10703 if (ret) 10704 drm_err(&dev_priv->drm, 10705 "Restoring old state failed with %i\n", ret); 10706 if (state) 10707 drm_atomic_state_put(state); 10708 } 10709 10710 static void intel_hpd_poll_fini(struct drm_i915_private *i915) 10711 { 10712 struct intel_connector *connector; 10713 struct drm_connector_list_iter conn_iter; 10714 10715 /* Kill all the work that may have been queued by hpd. */ 10716 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 10717 for_each_intel_connector_iter(connector, &conn_iter) { 10718 if (connector->modeset_retry_work.func) 10719 cancel_work_sync(&connector->modeset_retry_work); 10720 if (connector->hdcp.shim) { 10721 cancel_delayed_work_sync(&connector->hdcp.check_work); 10722 cancel_work_sync(&connector->hdcp.prop_work); 10723 } 10724 } 10725 drm_connector_list_iter_end(&conn_iter); 10726 } 10727 10728 /* part #1: call before irq uninstall */ 10729 void intel_modeset_driver_remove(struct drm_i915_private *i915) 10730 { 10731 if (!HAS_DISPLAY(i915)) 10732 return; 10733 10734 flush_workqueue(i915->flip_wq); 10735 flush_workqueue(i915->modeset_wq); 10736 10737 flush_work(&i915->atomic_helper.free_work); 10738 drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list)); 10739 } 10740 10741 /* part #2: call after irq uninstall */ 10742 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915) 10743 { 10744 if (!HAS_DISPLAY(i915)) 10745 return; 10746 10747 /* 10748 * Due to the hpd irq storm handling the hotplug work can re-arm the 10749 * poll handlers. Hence disable polling after hpd handling is shut down. 10750 */ 10751 intel_hpd_poll_fini(i915); 10752 10753 /* 10754 * MST topology needs to be suspended so we don't have any calls to 10755 * fbdev after it's finalized. MST will be destroyed later as part of 10756 * drm_mode_config_cleanup() 10757 */ 10758 intel_dp_mst_suspend(i915); 10759 10760 /* poll work can call into fbdev, hence clean that up afterwards */ 10761 intel_fbdev_fini(i915); 10762 10763 intel_unregister_dsm_handler(); 10764 10765 intel_fbc_global_disable(i915); 10766 10767 /* flush any delayed tasks or pending work */ 10768 flush_scheduled_work(); 10769 10770 intel_hdcp_component_fini(i915); 10771 10772 intel_mode_config_cleanup(i915); 10773 10774 intel_overlay_cleanup(i915); 10775 10776 intel_gmbus_teardown(i915); 10777 10778 destroy_workqueue(i915->flip_wq); 10779 destroy_workqueue(i915->modeset_wq); 10780 10781 intel_fbc_cleanup(i915); 10782 } 10783 10784 /* part #3: call after gem init */ 10785 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915) 10786 { 10787 intel_dmc_ucode_fini(i915); 10788 10789 intel_power_domains_driver_remove(i915); 10790 10791 intel_vga_unregister(i915); 10792 10793 intel_bios_driver_remove(i915); 10794 } 10795 10796 bool intel_modeset_probe_defer(struct pci_dev *pdev) 10797 { 10798 struct drm_privacy_screen *privacy_screen; 10799 10800 /* 10801 * apple-gmux is needed on dual GPU MacBook Pro 10802 * to probe the panel if we're the inactive GPU. 10803 */ 10804 if (vga_switcheroo_client_probe_defer(pdev)) 10805 return true; 10806 10807 /* If the LCD panel has a privacy-screen, wait for it */ 10808 privacy_screen = drm_privacy_screen_get(&pdev->dev, NULL); 10809 if (IS_ERR(privacy_screen) && PTR_ERR(privacy_screen) == -EPROBE_DEFER) 10810 return true; 10811 10812 drm_privacy_screen_put(privacy_screen); 10813 10814 return false; 10815 } 10816 10817 void intel_display_driver_register(struct drm_i915_private *i915) 10818 { 10819 if (!HAS_DISPLAY(i915)) 10820 return; 10821 10822 intel_display_debugfs_register(i915); 10823 10824 /* Must be done after probing outputs */ 10825 intel_opregion_register(i915); 10826 acpi_video_register(); 10827 10828 intel_audio_init(i915); 10829 10830 /* 10831 * Some ports require correctly set-up hpd registers for 10832 * detection to work properly (leading to ghost connected 10833 * connector status), e.g. VGA on gm45. Hence we can only set 10834 * up the initial fbdev config after hpd irqs are fully 10835 * enabled. We do it last so that the async config cannot run 10836 * before the connectors are registered. 10837 */ 10838 intel_fbdev_initial_config_async(&i915->drm); 10839 10840 /* 10841 * We need to coordinate the hotplugs with the asynchronous 10842 * fbdev configuration, for which we use the 10843 * fbdev->async_cookie. 10844 */ 10845 drm_kms_helper_poll_init(&i915->drm); 10846 } 10847 10848 void intel_display_driver_unregister(struct drm_i915_private *i915) 10849 { 10850 if (!HAS_DISPLAY(i915)) 10851 return; 10852 10853 intel_fbdev_unregister(i915); 10854 intel_audio_deinit(i915); 10855 10856 /* 10857 * After flushing the fbdev (incl. a late async config which 10858 * will have delayed queuing of a hotplug event), then flush 10859 * the hotplug events. 10860 */ 10861 drm_kms_helper_poll_fini(&i915->drm); 10862 drm_atomic_helper_shutdown(&i915->drm); 10863 10864 acpi_video_unregister(); 10865 intel_opregion_unregister(i915); 10866 } 10867