1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <acpi/video.h> 28 #include <linux/i2c.h> 29 #include <linux/input.h> 30 #include <linux/intel-iommu.h> 31 #include <linux/kernel.h> 32 #include <linux/module.h> 33 #include <linux/dma-resv.h> 34 #include <linux/slab.h> 35 #include <linux/string_helpers.h> 36 #include <linux/vga_switcheroo.h> 37 38 #include <drm/drm_atomic.h> 39 #include <drm/drm_atomic_helper.h> 40 #include <drm/drm_atomic_uapi.h> 41 #include <drm/drm_damage_helper.h> 42 #include <drm/dp/drm_dp_helper.h> 43 #include <drm/drm_edid.h> 44 #include <drm/drm_fourcc.h> 45 #include <drm/drm_plane_helper.h> 46 #include <drm/drm_privacy_screen_consumer.h> 47 #include <drm/drm_probe_helper.h> 48 #include <drm/drm_rect.h> 49 50 #include "display/intel_audio.h" 51 #include "display/intel_crt.h" 52 #include "display/intel_ddi.h" 53 #include "display/intel_display_debugfs.h" 54 #include "display/intel_display_power.h" 55 #include "display/intel_dp.h" 56 #include "display/intel_dp_mst.h" 57 #include "display/intel_dpll.h" 58 #include "display/intel_dpll_mgr.h" 59 #include "display/intel_drrs.h" 60 #include "display/intel_dsi.h" 61 #include "display/intel_dvo.h" 62 #include "display/intel_fb.h" 63 #include "display/intel_gmbus.h" 64 #include "display/intel_hdmi.h" 65 #include "display/intel_lvds.h" 66 #include "display/intel_sdvo.h" 67 #include "display/intel_snps_phy.h" 68 #include "display/intel_tv.h" 69 #include "display/intel_vdsc.h" 70 #include "display/intel_vrr.h" 71 72 #include "gem/i915_gem_lmem.h" 73 #include "gem/i915_gem_object.h" 74 75 #include "gt/gen8_ppgtt.h" 76 77 #include "g4x_dp.h" 78 #include "g4x_hdmi.h" 79 #include "hsw_ips.h" 80 #include "i915_drv.h" 81 #include "i915_utils.h" 82 #include "icl_dsi.h" 83 #include "intel_acpi.h" 84 #include "intel_atomic.h" 85 #include "intel_atomic_plane.h" 86 #include "intel_bw.h" 87 #include "intel_cdclk.h" 88 #include "intel_color.h" 89 #include "intel_crtc.h" 90 #include "intel_crtc_state_dump.h" 91 #include "intel_de.h" 92 #include "intel_display_types.h" 93 #include "intel_dmc.h" 94 #include "intel_dp_link_training.h" 95 #include "intel_dpt.h" 96 #include "intel_fbc.h" 97 #include "intel_fbdev.h" 98 #include "intel_fdi.h" 99 #include "intel_fifo_underrun.h" 100 #include "intel_frontbuffer.h" 101 #include "intel_hdcp.h" 102 #include "intel_hotplug.h" 103 #include "intel_modeset_verify.h" 104 #include "intel_modeset_setup.h" 105 #include "intel_overlay.h" 106 #include "intel_panel.h" 107 #include "intel_pch_display.h" 108 #include "intel_pch_refclk.h" 109 #include "intel_pcode.h" 110 #include "intel_pipe_crc.h" 111 #include "intel_plane_initial.h" 112 #include "intel_pm.h" 113 #include "intel_pps.h" 114 #include "intel_psr.h" 115 #include "intel_quirks.h" 116 #include "intel_sprite.h" 117 #include "intel_tc.h" 118 #include "intel_vga.h" 119 #include "i9xx_plane.h" 120 #include "skl_scaler.h" 121 #include "skl_universal_plane.h" 122 #include "vlv_dsi.h" 123 #include "vlv_dsi_pll.h" 124 #include "vlv_dsi_regs.h" 125 #include "vlv_sideband.h" 126 127 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state); 128 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state); 129 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state); 130 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state); 131 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state); 132 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state); 133 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state); 134 135 /** 136 * intel_update_watermarks - update FIFO watermark values based on current modes 137 * @dev_priv: i915 device 138 * 139 * Calculate watermark values for the various WM regs based on current mode 140 * and plane configuration. 141 * 142 * There are several cases to deal with here: 143 * - normal (i.e. non-self-refresh) 144 * - self-refresh (SR) mode 145 * - lines are large relative to FIFO size (buffer can hold up to 2) 146 * - lines are small relative to FIFO size (buffer can hold more than 2 147 * lines), so need to account for TLB latency 148 * 149 * The normal calculation is: 150 * watermark = dotclock * bytes per pixel * latency 151 * where latency is platform & configuration dependent (we assume pessimal 152 * values here). 153 * 154 * The SR calculation is: 155 * watermark = (trunc(latency/line time)+1) * surface width * 156 * bytes per pixel 157 * where 158 * line time = htotal / dotclock 159 * surface width = hdisplay for normal plane and 64 for cursor 160 * and latency is assumed to be high, as above. 161 * 162 * The final value programmed to the register should always be rounded up, 163 * and include an extra 2 entries to account for clock crossings. 164 * 165 * We don't use the sprite, so we can ignore that. And on Crestline we have 166 * to set the non-SR watermarks to 8. 167 */ 168 void intel_update_watermarks(struct drm_i915_private *dev_priv) 169 { 170 if (dev_priv->wm_disp->update_wm) 171 dev_priv->wm_disp->update_wm(dev_priv); 172 } 173 174 static int intel_compute_pipe_wm(struct intel_atomic_state *state, 175 struct intel_crtc *crtc) 176 { 177 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 178 if (dev_priv->wm_disp->compute_pipe_wm) 179 return dev_priv->wm_disp->compute_pipe_wm(state, crtc); 180 return 0; 181 } 182 183 static int intel_compute_intermediate_wm(struct intel_atomic_state *state, 184 struct intel_crtc *crtc) 185 { 186 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 187 if (!dev_priv->wm_disp->compute_intermediate_wm) 188 return 0; 189 if (drm_WARN_ON(&dev_priv->drm, 190 !dev_priv->wm_disp->compute_pipe_wm)) 191 return 0; 192 return dev_priv->wm_disp->compute_intermediate_wm(state, crtc); 193 } 194 195 static bool intel_initial_watermarks(struct intel_atomic_state *state, 196 struct intel_crtc *crtc) 197 { 198 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 199 if (dev_priv->wm_disp->initial_watermarks) { 200 dev_priv->wm_disp->initial_watermarks(state, crtc); 201 return true; 202 } 203 return false; 204 } 205 206 static void intel_atomic_update_watermarks(struct intel_atomic_state *state, 207 struct intel_crtc *crtc) 208 { 209 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 210 if (dev_priv->wm_disp->atomic_update_watermarks) 211 dev_priv->wm_disp->atomic_update_watermarks(state, crtc); 212 } 213 214 static void intel_optimize_watermarks(struct intel_atomic_state *state, 215 struct intel_crtc *crtc) 216 { 217 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 218 if (dev_priv->wm_disp->optimize_watermarks) 219 dev_priv->wm_disp->optimize_watermarks(state, crtc); 220 } 221 222 static int intel_compute_global_watermarks(struct intel_atomic_state *state) 223 { 224 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 225 if (dev_priv->wm_disp->compute_global_watermarks) 226 return dev_priv->wm_disp->compute_global_watermarks(state); 227 return 0; 228 } 229 230 /* returns HPLL frequency in kHz */ 231 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) 232 { 233 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; 234 235 /* Obtain SKU information */ 236 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & 237 CCK_FUSE_HPLL_FREQ_MASK; 238 239 return vco_freq[hpll_freq] * 1000; 240 } 241 242 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 243 const char *name, u32 reg, int ref_freq) 244 { 245 u32 val; 246 int divider; 247 248 val = vlv_cck_read(dev_priv, reg); 249 divider = val & CCK_FREQUENCY_VALUES; 250 251 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != 252 (divider << CCK_FREQUENCY_STATUS_SHIFT), 253 "%s change in progress\n", name); 254 255 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); 256 } 257 258 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 259 const char *name, u32 reg) 260 { 261 int hpll; 262 263 vlv_cck_get(dev_priv); 264 265 if (dev_priv->hpll_freq == 0) 266 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); 267 268 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); 269 270 vlv_cck_put(dev_priv); 271 272 return hpll; 273 } 274 275 static void intel_update_czclk(struct drm_i915_private *dev_priv) 276 { 277 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) 278 return; 279 280 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", 281 CCK_CZ_CLOCK_CONTROL); 282 283 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", 284 dev_priv->czclk_freq); 285 } 286 287 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state) 288 { 289 return (crtc_state->active_planes & 290 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0; 291 } 292 293 /* WA Display #0827: Gen9:all */ 294 static void 295 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) 296 { 297 if (enable) 298 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 299 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS); 300 else 301 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 302 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS)); 303 } 304 305 /* Wa_2006604312:icl,ehl */ 306 static void 307 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 308 bool enable) 309 { 310 if (enable) 311 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 312 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS); 313 else 314 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 315 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS); 316 } 317 318 /* Wa_1604331009:icl,jsl,ehl */ 319 static void 320 icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 321 bool enable) 322 { 323 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), CURSOR_GATING_DIS, 324 enable ? CURSOR_GATING_DIS : 0); 325 } 326 327 static bool 328 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state) 329 { 330 return crtc_state->master_transcoder != INVALID_TRANSCODER; 331 } 332 333 static bool 334 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state) 335 { 336 return crtc_state->sync_mode_slaves_mask != 0; 337 } 338 339 bool 340 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state) 341 { 342 return is_trans_port_sync_master(crtc_state) || 343 is_trans_port_sync_slave(crtc_state); 344 } 345 346 static enum pipe bigjoiner_master_pipe(const struct intel_crtc_state *crtc_state) 347 { 348 return ffs(crtc_state->bigjoiner_pipes) - 1; 349 } 350 351 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state) 352 { 353 if (crtc_state->bigjoiner_pipes) 354 return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state)); 355 else 356 return 0; 357 } 358 359 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state) 360 { 361 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 362 363 return crtc_state->bigjoiner_pipes && 364 crtc->pipe != bigjoiner_master_pipe(crtc_state); 365 } 366 367 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state) 368 { 369 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 370 371 return crtc_state->bigjoiner_pipes && 372 crtc->pipe == bigjoiner_master_pipe(crtc_state); 373 } 374 375 static int intel_bigjoiner_num_pipes(const struct intel_crtc_state *crtc_state) 376 { 377 return hweight8(crtc_state->bigjoiner_pipes); 378 } 379 380 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state) 381 { 382 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 383 384 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 385 return intel_crtc_for_pipe(i915, bigjoiner_master_pipe(crtc_state)); 386 else 387 return to_intel_crtc(crtc_state->uapi.crtc); 388 } 389 390 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv, 391 enum pipe pipe) 392 { 393 i915_reg_t reg = PIPEDSL(pipe); 394 u32 line1, line2; 395 396 line1 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK; 397 msleep(5); 398 line2 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK; 399 400 return line1 != line2; 401 } 402 403 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state) 404 { 405 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 406 enum pipe pipe = crtc->pipe; 407 408 /* Wait for the display line to settle/start moving */ 409 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100)) 410 drm_err(&dev_priv->drm, 411 "pipe %c scanline %s wait timed out\n", 412 pipe_name(pipe), str_on_off(state)); 413 } 414 415 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc) 416 { 417 wait_for_pipe_scanline_moving(crtc, false); 418 } 419 420 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc) 421 { 422 wait_for_pipe_scanline_moving(crtc, true); 423 } 424 425 static void 426 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) 427 { 428 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 429 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 430 431 if (DISPLAY_VER(dev_priv) >= 4) { 432 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 433 434 /* Wait for the Pipe State to go off */ 435 if (intel_de_wait_for_clear(dev_priv, PIPECONF(cpu_transcoder), 436 PIPECONF_STATE_ENABLE, 100)) 437 drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n"); 438 } else { 439 intel_wait_for_pipe_scanline_stopped(crtc); 440 } 441 } 442 443 void assert_transcoder(struct drm_i915_private *dev_priv, 444 enum transcoder cpu_transcoder, bool state) 445 { 446 bool cur_state; 447 enum intel_display_power_domain power_domain; 448 intel_wakeref_t wakeref; 449 450 /* we keep both pipes enabled on 830 */ 451 if (IS_I830(dev_priv)) 452 state = true; 453 454 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 455 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 456 if (wakeref) { 457 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); 458 cur_state = !!(val & PIPECONF_ENABLE); 459 460 intel_display_power_put(dev_priv, power_domain, wakeref); 461 } else { 462 cur_state = false; 463 } 464 465 I915_STATE_WARN(cur_state != state, 466 "transcoder %s assertion failure (expected %s, current %s)\n", 467 transcoder_name(cpu_transcoder), 468 str_on_off(state), str_on_off(cur_state)); 469 } 470 471 static void assert_plane(struct intel_plane *plane, bool state) 472 { 473 enum pipe pipe; 474 bool cur_state; 475 476 cur_state = plane->get_hw_state(plane, &pipe); 477 478 I915_STATE_WARN(cur_state != state, 479 "%s assertion failure (expected %s, current %s)\n", 480 plane->base.name, str_on_off(state), 481 str_on_off(cur_state)); 482 } 483 484 #define assert_plane_enabled(p) assert_plane(p, true) 485 #define assert_plane_disabled(p) assert_plane(p, false) 486 487 static void assert_planes_disabled(struct intel_crtc *crtc) 488 { 489 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 490 struct intel_plane *plane; 491 492 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) 493 assert_plane_disabled(plane); 494 } 495 496 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 497 struct intel_digital_port *dig_port, 498 unsigned int expected_mask) 499 { 500 u32 port_mask; 501 i915_reg_t dpll_reg; 502 503 switch (dig_port->base.port) { 504 default: 505 MISSING_CASE(dig_port->base.port); 506 fallthrough; 507 case PORT_B: 508 port_mask = DPLL_PORTB_READY_MASK; 509 dpll_reg = DPLL(0); 510 break; 511 case PORT_C: 512 port_mask = DPLL_PORTC_READY_MASK; 513 dpll_reg = DPLL(0); 514 expected_mask <<= 4; 515 break; 516 case PORT_D: 517 port_mask = DPLL_PORTD_READY_MASK; 518 dpll_reg = DPIO_PHY_STATUS; 519 break; 520 } 521 522 if (intel_de_wait_for_register(dev_priv, dpll_reg, 523 port_mask, expected_mask, 1000)) 524 drm_WARN(&dev_priv->drm, 1, 525 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", 526 dig_port->base.base.base.id, dig_port->base.base.name, 527 intel_de_read(dev_priv, dpll_reg) & port_mask, 528 expected_mask); 529 } 530 531 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) 532 { 533 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 534 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 535 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 536 enum pipe pipe = crtc->pipe; 537 i915_reg_t reg; 538 u32 val; 539 540 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe)); 541 542 assert_planes_disabled(crtc); 543 544 /* 545 * A pipe without a PLL won't actually be able to drive bits from 546 * a plane. On ILK+ the pipe PLLs are integrated, so we don't 547 * need the check. 548 */ 549 if (HAS_GMCH(dev_priv)) { 550 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI)) 551 assert_dsi_pll_enabled(dev_priv); 552 else 553 assert_pll_enabled(dev_priv, pipe); 554 } else { 555 if (new_crtc_state->has_pch_encoder) { 556 /* if driving the PCH, we need FDI enabled */ 557 assert_fdi_rx_pll_enabled(dev_priv, 558 intel_crtc_pch_transcoder(crtc)); 559 assert_fdi_tx_pll_enabled(dev_priv, 560 (enum pipe) cpu_transcoder); 561 } 562 /* FIXME: assert CPU port conditions for SNB+ */ 563 } 564 565 /* Wa_22012358565:adl-p */ 566 if (DISPLAY_VER(dev_priv) == 13) 567 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe), 568 0, PIPE_ARB_USE_PROG_SLOTS); 569 570 reg = PIPECONF(cpu_transcoder); 571 val = intel_de_read(dev_priv, reg); 572 if (val & PIPECONF_ENABLE) { 573 /* we keep both pipes enabled on 830 */ 574 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv)); 575 return; 576 } 577 578 intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE); 579 intel_de_posting_read(dev_priv, reg); 580 581 /* 582 * Until the pipe starts PIPEDSL reads will return a stale value, 583 * which causes an apparent vblank timestamp jump when PIPEDSL 584 * resets to its proper value. That also messes up the frame count 585 * when it's derived from the timestamps. So let's wait for the 586 * pipe to start properly before we call drm_crtc_vblank_on() 587 */ 588 if (intel_crtc_max_vblank_count(new_crtc_state) == 0) 589 intel_wait_for_pipe_scanline_moving(crtc); 590 } 591 592 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) 593 { 594 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 595 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 596 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 597 enum pipe pipe = crtc->pipe; 598 i915_reg_t reg; 599 u32 val; 600 601 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe)); 602 603 /* 604 * Make sure planes won't keep trying to pump pixels to us, 605 * or we might hang the display. 606 */ 607 assert_planes_disabled(crtc); 608 609 reg = PIPECONF(cpu_transcoder); 610 val = intel_de_read(dev_priv, reg); 611 if ((val & PIPECONF_ENABLE) == 0) 612 return; 613 614 /* 615 * Double wide has implications for planes 616 * so best keep it disabled when not needed. 617 */ 618 if (old_crtc_state->double_wide) 619 val &= ~PIPECONF_DOUBLE_WIDE; 620 621 /* Don't disable pipe or pipe PLLs if needed */ 622 if (!IS_I830(dev_priv)) 623 val &= ~PIPECONF_ENABLE; 624 625 if (DISPLAY_VER(dev_priv) >= 12) 626 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 627 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 628 629 intel_de_write(dev_priv, reg, val); 630 if ((val & PIPECONF_ENABLE) == 0) 631 intel_wait_for_pipe_off(old_crtc_state); 632 } 633 634 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) 635 { 636 unsigned int size = 0; 637 int i; 638 639 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) 640 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width; 641 642 return size; 643 } 644 645 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info) 646 { 647 unsigned int size = 0; 648 int i; 649 650 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) { 651 unsigned int plane_size; 652 653 if (rem_info->plane[i].linear) 654 plane_size = rem_info->plane[i].size; 655 else 656 plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height; 657 658 if (plane_size == 0) 659 continue; 660 661 if (rem_info->plane_alignment) 662 size = ALIGN(size, rem_info->plane_alignment); 663 664 size += plane_size; 665 } 666 667 return size; 668 } 669 670 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) 671 { 672 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 673 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 674 675 return DISPLAY_VER(dev_priv) < 4 || 676 (plane->fbc && 677 plane_state->view.gtt.type == I915_GGTT_VIEW_NORMAL); 678 } 679 680 /* 681 * Convert the x/y offsets into a linear offset. 682 * Only valid with 0/180 degree rotation, which is fine since linear 683 * offset is only used with linear buffers on pre-hsw and tiled buffers 684 * with gen2/3, and 90/270 degree rotations isn't supported on any of them. 685 */ 686 u32 intel_fb_xy_to_linear(int x, int y, 687 const struct intel_plane_state *state, 688 int color_plane) 689 { 690 const struct drm_framebuffer *fb = state->hw.fb; 691 unsigned int cpp = fb->format->cpp[color_plane]; 692 unsigned int pitch = state->view.color_plane[color_plane].mapping_stride; 693 694 return y * pitch + x * cpp; 695 } 696 697 /* 698 * Add the x/y offsets derived from fb->offsets[] to the user 699 * specified plane src x/y offsets. The resulting x/y offsets 700 * specify the start of scanout from the beginning of the gtt mapping. 701 */ 702 void intel_add_fb_offsets(int *x, int *y, 703 const struct intel_plane_state *state, 704 int color_plane) 705 706 { 707 *x += state->view.color_plane[color_plane].x; 708 *y += state->view.color_plane[color_plane].y; 709 } 710 711 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 712 u32 pixel_format, u64 modifier) 713 { 714 struct intel_crtc *crtc; 715 struct intel_plane *plane; 716 717 if (!HAS_DISPLAY(dev_priv)) 718 return 0; 719 720 /* 721 * We assume the primary plane for pipe A has 722 * the highest stride limits of them all, 723 * if in case pipe A is disabled, use the first pipe from pipe_mask. 724 */ 725 crtc = intel_first_crtc(dev_priv); 726 if (!crtc) 727 return 0; 728 729 plane = to_intel_plane(crtc->base.primary); 730 731 return plane->max_stride(plane, pixel_format, modifier, 732 DRM_MODE_ROTATE_0); 733 } 734 735 void intel_set_plane_visible(struct intel_crtc_state *crtc_state, 736 struct intel_plane_state *plane_state, 737 bool visible) 738 { 739 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 740 741 plane_state->uapi.visible = visible; 742 743 if (visible) 744 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base); 745 else 746 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base); 747 } 748 749 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state) 750 { 751 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 752 struct drm_plane *plane; 753 754 /* 755 * Active_planes aliases if multiple "primary" or cursor planes 756 * have been used on the same (or wrong) pipe. plane_mask uses 757 * unique ids, hence we can use that to reconstruct active_planes. 758 */ 759 crtc_state->enabled_planes = 0; 760 crtc_state->active_planes = 0; 761 762 drm_for_each_plane_mask(plane, &dev_priv->drm, 763 crtc_state->uapi.plane_mask) { 764 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id); 765 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id); 766 } 767 } 768 769 void intel_plane_disable_noatomic(struct intel_crtc *crtc, 770 struct intel_plane *plane) 771 { 772 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 773 struct intel_crtc_state *crtc_state = 774 to_intel_crtc_state(crtc->base.state); 775 struct intel_plane_state *plane_state = 776 to_intel_plane_state(plane->base.state); 777 778 drm_dbg_kms(&dev_priv->drm, 779 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n", 780 plane->base.base.id, plane->base.name, 781 crtc->base.base.id, crtc->base.name); 782 783 intel_set_plane_visible(crtc_state, plane_state, false); 784 intel_plane_fixup_bitmasks(crtc_state); 785 crtc_state->data_rate[plane->id] = 0; 786 crtc_state->data_rate_y[plane->id] = 0; 787 crtc_state->rel_data_rate[plane->id] = 0; 788 crtc_state->rel_data_rate_y[plane->id] = 0; 789 crtc_state->min_cdclk[plane->id] = 0; 790 791 if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 && 792 hsw_ips_disable(crtc_state)) { 793 crtc_state->ips_enabled = false; 794 intel_crtc_wait_for_next_vblank(crtc); 795 } 796 797 /* 798 * Vblank time updates from the shadow to live plane control register 799 * are blocked if the memory self-refresh mode is active at that 800 * moment. So to make sure the plane gets truly disabled, disable 801 * first the self-refresh mode. The self-refresh enable bit in turn 802 * will be checked/applied by the HW only at the next frame start 803 * event which is after the vblank start event, so we need to have a 804 * wait-for-vblank between disabling the plane and the pipe. 805 */ 806 if (HAS_GMCH(dev_priv) && 807 intel_set_memory_cxsr(dev_priv, false)) 808 intel_crtc_wait_for_next_vblank(crtc); 809 810 /* 811 * Gen2 reports pipe underruns whenever all planes are disabled. 812 * So disable underrun reporting before all the planes get disabled. 813 */ 814 if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes) 815 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); 816 817 intel_plane_disable_arm(plane, crtc_state); 818 intel_crtc_wait_for_next_vblank(crtc); 819 } 820 821 unsigned int 822 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state) 823 { 824 int x = 0, y = 0; 825 826 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, 827 plane_state->view.color_plane[0].offset, 0); 828 829 return y; 830 } 831 832 static int 833 __intel_display_resume(struct drm_i915_private *i915, 834 struct drm_atomic_state *state, 835 struct drm_modeset_acquire_ctx *ctx) 836 { 837 struct drm_crtc_state *crtc_state; 838 struct drm_crtc *crtc; 839 int i, ret; 840 841 intel_modeset_setup_hw_state(&i915->drm, ctx); 842 intel_vga_redisable(i915); 843 844 if (!state) 845 return 0; 846 847 /* 848 * We've duplicated the state, pointers to the old state are invalid. 849 * 850 * Don't attempt to use the old state until we commit the duplicated state. 851 */ 852 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 853 /* 854 * Force recalculation even if we restore 855 * current state. With fast modeset this may not result 856 * in a modeset when the state is compatible. 857 */ 858 crtc_state->mode_changed = true; 859 } 860 861 /* ignore any reset values/BIOS leftovers in the WM registers */ 862 if (!HAS_GMCH(i915)) 863 to_intel_atomic_state(state)->skip_intermediate_wm = true; 864 865 ret = drm_atomic_helper_commit_duplicated_state(state, ctx); 866 867 drm_WARN_ON(&i915->drm, ret == -EDEADLK); 868 869 return ret; 870 } 871 872 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) 873 { 874 return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display && 875 intel_has_gpu_reset(to_gt(dev_priv))); 876 } 877 878 void intel_display_prepare_reset(struct drm_i915_private *dev_priv) 879 { 880 struct drm_device *dev = &dev_priv->drm; 881 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; 882 struct drm_atomic_state *state; 883 int ret; 884 885 if (!HAS_DISPLAY(dev_priv)) 886 return; 887 888 /* reset doesn't touch the display */ 889 if (!dev_priv->params.force_reset_modeset_test && 890 !gpu_reset_clobbers_display(dev_priv)) 891 return; 892 893 /* We have a modeset vs reset deadlock, defensively unbreak it. */ 894 set_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags); 895 smp_mb__after_atomic(); 896 wake_up_bit(&to_gt(dev_priv)->reset.flags, I915_RESET_MODESET); 897 898 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) { 899 drm_dbg_kms(&dev_priv->drm, 900 "Modeset potentially stuck, unbreaking through wedging\n"); 901 intel_gt_set_wedged(to_gt(dev_priv)); 902 } 903 904 /* 905 * Need mode_config.mutex so that we don't 906 * trample ongoing ->detect() and whatnot. 907 */ 908 mutex_lock(&dev->mode_config.mutex); 909 drm_modeset_acquire_init(ctx, 0); 910 while (1) { 911 ret = drm_modeset_lock_all_ctx(dev, ctx); 912 if (ret != -EDEADLK) 913 break; 914 915 drm_modeset_backoff(ctx); 916 } 917 /* 918 * Disabling the crtcs gracefully seems nicer. Also the 919 * g33 docs say we should at least disable all the planes. 920 */ 921 state = drm_atomic_helper_duplicate_state(dev, ctx); 922 if (IS_ERR(state)) { 923 ret = PTR_ERR(state); 924 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n", 925 ret); 926 return; 927 } 928 929 ret = drm_atomic_helper_disable_all(dev, ctx); 930 if (ret) { 931 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", 932 ret); 933 drm_atomic_state_put(state); 934 return; 935 } 936 937 dev_priv->modeset_restore_state = state; 938 state->acquire_ctx = ctx; 939 } 940 941 void intel_display_finish_reset(struct drm_i915_private *i915) 942 { 943 struct drm_modeset_acquire_ctx *ctx = &i915->reset_ctx; 944 struct drm_atomic_state *state; 945 int ret; 946 947 if (!HAS_DISPLAY(i915)) 948 return; 949 950 /* reset doesn't touch the display */ 951 if (!test_bit(I915_RESET_MODESET, &to_gt(i915)->reset.flags)) 952 return; 953 954 state = fetch_and_zero(&i915->modeset_restore_state); 955 if (!state) 956 goto unlock; 957 958 /* reset doesn't touch the display */ 959 if (!gpu_reset_clobbers_display(i915)) { 960 /* for testing only restore the display */ 961 ret = __intel_display_resume(i915, state, ctx); 962 if (ret) 963 drm_err(&i915->drm, 964 "Restoring old state failed with %i\n", ret); 965 } else { 966 /* 967 * The display has been reset as well, 968 * so need a full re-initialization. 969 */ 970 intel_pps_unlock_regs_wa(i915); 971 intel_modeset_init_hw(i915); 972 intel_init_clock_gating(i915); 973 intel_hpd_init(i915); 974 975 ret = __intel_display_resume(i915, state, ctx); 976 if (ret) 977 drm_err(&i915->drm, 978 "Restoring old state failed with %i\n", ret); 979 980 intel_hpd_poll_disable(i915); 981 } 982 983 drm_atomic_state_put(state); 984 unlock: 985 drm_modeset_drop_locks(ctx); 986 drm_modeset_acquire_fini(ctx); 987 mutex_unlock(&i915->drm.mode_config.mutex); 988 989 clear_bit_unlock(I915_RESET_MODESET, &to_gt(i915)->reset.flags); 990 } 991 992 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) 993 { 994 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 995 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 996 enum pipe pipe = crtc->pipe; 997 u32 tmp; 998 999 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe)); 1000 1001 /* 1002 * Display WA #1153: icl 1003 * enable hardware to bypass the alpha math 1004 * and rounding for per-pixel values 00 and 0xff 1005 */ 1006 tmp |= PER_PIXEL_ALPHA_BYPASS_EN; 1007 /* 1008 * Display WA # 1605353570: icl 1009 * Set the pixel rounding bit to 1 for allowing 1010 * passthrough of Frame buffer pixels unmodified 1011 * across pipe 1012 */ 1013 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU; 1014 1015 /* 1016 * Underrun recovery must always be disabled on display 13+. 1017 * DG2 chicken bit meaning is inverted compared to other platforms. 1018 */ 1019 if (IS_DG2(dev_priv)) 1020 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2; 1021 else if (DISPLAY_VER(dev_priv) >= 13) 1022 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP; 1023 1024 /* Wa_14010547955:dg2 */ 1025 if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER)) 1026 tmp |= DG2_RENDER_CCSTAG_4_3_EN; 1027 1028 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp); 1029 } 1030 1031 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) 1032 { 1033 struct drm_crtc *crtc; 1034 bool cleanup_done; 1035 1036 drm_for_each_crtc(crtc, &dev_priv->drm) { 1037 struct drm_crtc_commit *commit; 1038 spin_lock(&crtc->commit_lock); 1039 commit = list_first_entry_or_null(&crtc->commit_list, 1040 struct drm_crtc_commit, commit_entry); 1041 cleanup_done = commit ? 1042 try_wait_for_completion(&commit->cleanup_done) : true; 1043 spin_unlock(&crtc->commit_lock); 1044 1045 if (cleanup_done) 1046 continue; 1047 1048 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc)); 1049 1050 return true; 1051 } 1052 1053 return false; 1054 } 1055 1056 /* 1057 * Finds the encoder associated with the given CRTC. This can only be 1058 * used when we know that the CRTC isn't feeding multiple encoders! 1059 */ 1060 struct intel_encoder * 1061 intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 1062 const struct intel_crtc_state *crtc_state) 1063 { 1064 const struct drm_connector_state *connector_state; 1065 const struct drm_connector *connector; 1066 struct intel_encoder *encoder = NULL; 1067 struct intel_crtc *master_crtc; 1068 int num_encoders = 0; 1069 int i; 1070 1071 master_crtc = intel_master_crtc(crtc_state); 1072 1073 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 1074 if (connector_state->crtc != &master_crtc->base) 1075 continue; 1076 1077 encoder = to_intel_encoder(connector_state->best_encoder); 1078 num_encoders++; 1079 } 1080 1081 drm_WARN(encoder->base.dev, num_encoders != 1, 1082 "%d encoders for pipe %c\n", 1083 num_encoders, pipe_name(master_crtc->pipe)); 1084 1085 return encoder; 1086 } 1087 1088 static void cpt_verify_modeset(struct drm_i915_private *dev_priv, 1089 enum pipe pipe) 1090 { 1091 i915_reg_t dslreg = PIPEDSL(pipe); 1092 u32 temp; 1093 1094 temp = intel_de_read(dev_priv, dslreg); 1095 udelay(500); 1096 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) { 1097 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) 1098 drm_err(&dev_priv->drm, 1099 "mode set failed: pipe %c stuck\n", 1100 pipe_name(pipe)); 1101 } 1102 } 1103 1104 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state) 1105 { 1106 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1107 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1108 const struct drm_rect *dst = &crtc_state->pch_pfit.dst; 1109 enum pipe pipe = crtc->pipe; 1110 int width = drm_rect_width(dst); 1111 int height = drm_rect_height(dst); 1112 int x = dst->x1; 1113 int y = dst->y1; 1114 1115 if (!crtc_state->pch_pfit.enabled) 1116 return; 1117 1118 /* Force use of hard-coded filter coefficients 1119 * as some pre-programmed values are broken, 1120 * e.g. x201. 1121 */ 1122 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) 1123 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 1124 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe)); 1125 else 1126 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 1127 PF_FILTER_MED_3x3); 1128 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), x << 16 | y); 1129 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), width << 16 | height); 1130 } 1131 1132 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc) 1133 { 1134 if (crtc->overlay) 1135 (void) intel_overlay_switch_off(crtc->overlay); 1136 1137 /* Let userspace switch the overlay on again. In most cases userspace 1138 * has to recompute where to put it anyway. 1139 */ 1140 } 1141 1142 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state) 1143 { 1144 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1145 1146 if (!crtc_state->nv12_planes) 1147 return false; 1148 1149 /* WA Display #0827: Gen9:all */ 1150 if (DISPLAY_VER(dev_priv) == 9) 1151 return true; 1152 1153 return false; 1154 } 1155 1156 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state) 1157 { 1158 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1159 1160 /* Wa_2006604312:icl,ehl */ 1161 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11) 1162 return true; 1163 1164 return false; 1165 } 1166 1167 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state) 1168 { 1169 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1170 1171 /* Wa_1604331009:icl,jsl,ehl */ 1172 if (is_hdr_mode(crtc_state) && 1173 crtc_state->active_planes & BIT(PLANE_CURSOR) && 1174 DISPLAY_VER(dev_priv) == 11) 1175 return true; 1176 1177 return false; 1178 } 1179 1180 static void intel_async_flip_vtd_wa(struct drm_i915_private *i915, 1181 enum pipe pipe, bool enable) 1182 { 1183 if (DISPLAY_VER(i915) == 9) { 1184 /* 1185 * "Plane N strech max must be programmed to 11b (x1) 1186 * when Async flips are enabled on that plane." 1187 */ 1188 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 1189 SKL_PLANE1_STRETCH_MAX_MASK, 1190 enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8); 1191 } else { 1192 /* Also needed on HSW/BDW albeit undocumented */ 1193 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 1194 HSW_PRI_STRETCH_MAX_MASK, 1195 enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8); 1196 } 1197 } 1198 1199 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state) 1200 { 1201 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1202 1203 return crtc_state->uapi.async_flip && i915_vtd_active(i915) && 1204 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915)); 1205 } 1206 1207 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state, 1208 const struct intel_crtc_state *new_crtc_state) 1209 { 1210 return (!old_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)) && 1211 new_crtc_state->active_planes; 1212 } 1213 1214 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state, 1215 const struct intel_crtc_state *new_crtc_state) 1216 { 1217 return old_crtc_state->active_planes && 1218 (!new_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)); 1219 } 1220 1221 static void intel_post_plane_update(struct intel_atomic_state *state, 1222 struct intel_crtc *crtc) 1223 { 1224 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1225 const struct intel_crtc_state *old_crtc_state = 1226 intel_atomic_get_old_crtc_state(state, crtc); 1227 const struct intel_crtc_state *new_crtc_state = 1228 intel_atomic_get_new_crtc_state(state, crtc); 1229 enum pipe pipe = crtc->pipe; 1230 1231 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); 1232 1233 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) 1234 intel_update_watermarks(dev_priv); 1235 1236 hsw_ips_post_update(state, crtc); 1237 intel_fbc_post_update(state, crtc); 1238 1239 if (needs_async_flip_vtd_wa(old_crtc_state) && 1240 !needs_async_flip_vtd_wa(new_crtc_state)) 1241 intel_async_flip_vtd_wa(dev_priv, pipe, false); 1242 1243 if (needs_nv12_wa(old_crtc_state) && 1244 !needs_nv12_wa(new_crtc_state)) 1245 skl_wa_827(dev_priv, pipe, false); 1246 1247 if (needs_scalerclk_wa(old_crtc_state) && 1248 !needs_scalerclk_wa(new_crtc_state)) 1249 icl_wa_scalerclkgating(dev_priv, pipe, false); 1250 1251 if (needs_cursorclk_wa(old_crtc_state) && 1252 !needs_cursorclk_wa(new_crtc_state)) 1253 icl_wa_cursorclkgating(dev_priv, pipe, false); 1254 1255 intel_drrs_activate(new_crtc_state); 1256 } 1257 1258 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state, 1259 struct intel_crtc *crtc) 1260 { 1261 const struct intel_crtc_state *crtc_state = 1262 intel_atomic_get_new_crtc_state(state, crtc); 1263 u8 update_planes = crtc_state->update_planes; 1264 const struct intel_plane_state *plane_state; 1265 struct intel_plane *plane; 1266 int i; 1267 1268 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1269 if (plane->pipe == crtc->pipe && 1270 update_planes & BIT(plane->id)) 1271 plane->enable_flip_done(plane); 1272 } 1273 } 1274 1275 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state, 1276 struct intel_crtc *crtc) 1277 { 1278 const struct intel_crtc_state *crtc_state = 1279 intel_atomic_get_new_crtc_state(state, crtc); 1280 u8 update_planes = crtc_state->update_planes; 1281 const struct intel_plane_state *plane_state; 1282 struct intel_plane *plane; 1283 int i; 1284 1285 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1286 if (plane->pipe == crtc->pipe && 1287 update_planes & BIT(plane->id)) 1288 plane->disable_flip_done(plane); 1289 } 1290 } 1291 1292 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state, 1293 struct intel_crtc *crtc) 1294 { 1295 const struct intel_crtc_state *old_crtc_state = 1296 intel_atomic_get_old_crtc_state(state, crtc); 1297 const struct intel_crtc_state *new_crtc_state = 1298 intel_atomic_get_new_crtc_state(state, crtc); 1299 u8 update_planes = new_crtc_state->update_planes; 1300 const struct intel_plane_state *old_plane_state; 1301 struct intel_plane *plane; 1302 bool need_vbl_wait = false; 1303 int i; 1304 1305 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1306 if (plane->need_async_flip_disable_wa && 1307 plane->pipe == crtc->pipe && 1308 update_planes & BIT(plane->id)) { 1309 /* 1310 * Apart from the async flip bit we want to 1311 * preserve the old state for the plane. 1312 */ 1313 plane->async_flip(plane, old_crtc_state, 1314 old_plane_state, false); 1315 need_vbl_wait = true; 1316 } 1317 } 1318 1319 if (need_vbl_wait) 1320 intel_crtc_wait_for_next_vblank(crtc); 1321 } 1322 1323 static void intel_pre_plane_update(struct intel_atomic_state *state, 1324 struct intel_crtc *crtc) 1325 { 1326 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1327 const struct intel_crtc_state *old_crtc_state = 1328 intel_atomic_get_old_crtc_state(state, crtc); 1329 const struct intel_crtc_state *new_crtc_state = 1330 intel_atomic_get_new_crtc_state(state, crtc); 1331 enum pipe pipe = crtc->pipe; 1332 1333 intel_drrs_deactivate(old_crtc_state); 1334 1335 intel_psr_pre_plane_update(state, crtc); 1336 1337 if (hsw_ips_pre_update(state, crtc)) 1338 intel_crtc_wait_for_next_vblank(crtc); 1339 1340 if (intel_fbc_pre_update(state, crtc)) 1341 intel_crtc_wait_for_next_vblank(crtc); 1342 1343 if (!needs_async_flip_vtd_wa(old_crtc_state) && 1344 needs_async_flip_vtd_wa(new_crtc_state)) 1345 intel_async_flip_vtd_wa(dev_priv, pipe, true); 1346 1347 /* Display WA 827 */ 1348 if (!needs_nv12_wa(old_crtc_state) && 1349 needs_nv12_wa(new_crtc_state)) 1350 skl_wa_827(dev_priv, pipe, true); 1351 1352 /* Wa_2006604312:icl,ehl */ 1353 if (!needs_scalerclk_wa(old_crtc_state) && 1354 needs_scalerclk_wa(new_crtc_state)) 1355 icl_wa_scalerclkgating(dev_priv, pipe, true); 1356 1357 /* Wa_1604331009:icl,jsl,ehl */ 1358 if (!needs_cursorclk_wa(old_crtc_state) && 1359 needs_cursorclk_wa(new_crtc_state)) 1360 icl_wa_cursorclkgating(dev_priv, pipe, true); 1361 1362 /* 1363 * Vblank time updates from the shadow to live plane control register 1364 * are blocked if the memory self-refresh mode is active at that 1365 * moment. So to make sure the plane gets truly disabled, disable 1366 * first the self-refresh mode. The self-refresh enable bit in turn 1367 * will be checked/applied by the HW only at the next frame start 1368 * event which is after the vblank start event, so we need to have a 1369 * wait-for-vblank between disabling the plane and the pipe. 1370 */ 1371 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active && 1372 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) 1373 intel_crtc_wait_for_next_vblank(crtc); 1374 1375 /* 1376 * IVB workaround: must disable low power watermarks for at least 1377 * one frame before enabling scaling. LP watermarks can be re-enabled 1378 * when scaling is disabled. 1379 * 1380 * WaCxSRDisabledForSpriteScaling:ivb 1381 */ 1382 if (old_crtc_state->hw.active && 1383 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv)) 1384 intel_crtc_wait_for_next_vblank(crtc); 1385 1386 /* 1387 * If we're doing a modeset we don't need to do any 1388 * pre-vblank watermark programming here. 1389 */ 1390 if (!intel_crtc_needs_modeset(new_crtc_state)) { 1391 /* 1392 * For platforms that support atomic watermarks, program the 1393 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these 1394 * will be the intermediate values that are safe for both pre- and 1395 * post- vblank; when vblank happens, the 'active' values will be set 1396 * to the final 'target' values and we'll do this again to get the 1397 * optimal watermarks. For gen9+ platforms, the values we program here 1398 * will be the final target values which will get automatically latched 1399 * at vblank time; no further programming will be necessary. 1400 * 1401 * If a platform hasn't been transitioned to atomic watermarks yet, 1402 * we'll continue to update watermarks the old way, if flags tell 1403 * us to. 1404 */ 1405 if (!intel_initial_watermarks(state, crtc)) 1406 if (new_crtc_state->update_wm_pre) 1407 intel_update_watermarks(dev_priv); 1408 } 1409 1410 /* 1411 * Gen2 reports pipe underruns whenever all planes are disabled. 1412 * So disable underrun reporting before all the planes get disabled. 1413 * 1414 * We do this after .initial_watermarks() so that we have a 1415 * chance of catching underruns with the intermediate watermarks 1416 * vs. the old plane configuration. 1417 */ 1418 if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state)) 1419 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1420 1421 /* 1422 * WA for platforms where async address update enable bit 1423 * is double buffered and only latched at start of vblank. 1424 */ 1425 if (old_crtc_state->uapi.async_flip && !new_crtc_state->uapi.async_flip) 1426 intel_crtc_async_flip_disable_wa(state, crtc); 1427 } 1428 1429 static void intel_crtc_disable_planes(struct intel_atomic_state *state, 1430 struct intel_crtc *crtc) 1431 { 1432 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1433 const struct intel_crtc_state *new_crtc_state = 1434 intel_atomic_get_new_crtc_state(state, crtc); 1435 unsigned int update_mask = new_crtc_state->update_planes; 1436 const struct intel_plane_state *old_plane_state; 1437 struct intel_plane *plane; 1438 unsigned fb_bits = 0; 1439 int i; 1440 1441 intel_crtc_dpms_overlay_disable(crtc); 1442 1443 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1444 if (crtc->pipe != plane->pipe || 1445 !(update_mask & BIT(plane->id))) 1446 continue; 1447 1448 intel_plane_disable_arm(plane, new_crtc_state); 1449 1450 if (old_plane_state->uapi.visible) 1451 fb_bits |= plane->frontbuffer_bit; 1452 } 1453 1454 intel_frontbuffer_flip(dev_priv, fb_bits); 1455 } 1456 1457 /* 1458 * intel_connector_primary_encoder - get the primary encoder for a connector 1459 * @connector: connector for which to return the encoder 1460 * 1461 * Returns the primary encoder for a connector. There is a 1:1 mapping from 1462 * all connectors to their encoder, except for DP-MST connectors which have 1463 * both a virtual and a primary encoder. These DP-MST primary encoders can be 1464 * pointed to by as many DP-MST connectors as there are pipes. 1465 */ 1466 static struct intel_encoder * 1467 intel_connector_primary_encoder(struct intel_connector *connector) 1468 { 1469 struct intel_encoder *encoder; 1470 1471 if (connector->mst_port) 1472 return &dp_to_dig_port(connector->mst_port)->base; 1473 1474 encoder = intel_attached_encoder(connector); 1475 drm_WARN_ON(connector->base.dev, !encoder); 1476 1477 return encoder; 1478 } 1479 1480 static void intel_encoders_update_prepare(struct intel_atomic_state *state) 1481 { 1482 struct drm_i915_private *i915 = to_i915(state->base.dev); 1483 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 1484 struct intel_crtc *crtc; 1485 struct drm_connector_state *new_conn_state; 1486 struct drm_connector *connector; 1487 int i; 1488 1489 /* 1490 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits. 1491 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook. 1492 */ 1493 if (i915->dpll.mgr) { 1494 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1495 if (intel_crtc_needs_modeset(new_crtc_state)) 1496 continue; 1497 1498 new_crtc_state->shared_dpll = old_crtc_state->shared_dpll; 1499 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state; 1500 } 1501 } 1502 1503 if (!state->modeset) 1504 return; 1505 1506 for_each_new_connector_in_state(&state->base, connector, new_conn_state, 1507 i) { 1508 struct intel_connector *intel_connector; 1509 struct intel_encoder *encoder; 1510 struct intel_crtc *crtc; 1511 1512 if (!intel_connector_needs_modeset(state, connector)) 1513 continue; 1514 1515 intel_connector = to_intel_connector(connector); 1516 encoder = intel_connector_primary_encoder(intel_connector); 1517 if (!encoder->update_prepare) 1518 continue; 1519 1520 crtc = new_conn_state->crtc ? 1521 to_intel_crtc(new_conn_state->crtc) : NULL; 1522 encoder->update_prepare(state, encoder, crtc); 1523 } 1524 } 1525 1526 static void intel_encoders_update_complete(struct intel_atomic_state *state) 1527 { 1528 struct drm_connector_state *new_conn_state; 1529 struct drm_connector *connector; 1530 int i; 1531 1532 if (!state->modeset) 1533 return; 1534 1535 for_each_new_connector_in_state(&state->base, connector, new_conn_state, 1536 i) { 1537 struct intel_connector *intel_connector; 1538 struct intel_encoder *encoder; 1539 struct intel_crtc *crtc; 1540 1541 if (!intel_connector_needs_modeset(state, connector)) 1542 continue; 1543 1544 intel_connector = to_intel_connector(connector); 1545 encoder = intel_connector_primary_encoder(intel_connector); 1546 if (!encoder->update_complete) 1547 continue; 1548 1549 crtc = new_conn_state->crtc ? 1550 to_intel_crtc(new_conn_state->crtc) : NULL; 1551 encoder->update_complete(state, encoder, crtc); 1552 } 1553 } 1554 1555 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state, 1556 struct intel_crtc *crtc) 1557 { 1558 const struct intel_crtc_state *crtc_state = 1559 intel_atomic_get_new_crtc_state(state, crtc); 1560 const struct drm_connector_state *conn_state; 1561 struct drm_connector *conn; 1562 int i; 1563 1564 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1565 struct intel_encoder *encoder = 1566 to_intel_encoder(conn_state->best_encoder); 1567 1568 if (conn_state->crtc != &crtc->base) 1569 continue; 1570 1571 if (encoder->pre_pll_enable) 1572 encoder->pre_pll_enable(state, encoder, 1573 crtc_state, conn_state); 1574 } 1575 } 1576 1577 static void intel_encoders_pre_enable(struct intel_atomic_state *state, 1578 struct intel_crtc *crtc) 1579 { 1580 const struct intel_crtc_state *crtc_state = 1581 intel_atomic_get_new_crtc_state(state, crtc); 1582 const struct drm_connector_state *conn_state; 1583 struct drm_connector *conn; 1584 int i; 1585 1586 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1587 struct intel_encoder *encoder = 1588 to_intel_encoder(conn_state->best_encoder); 1589 1590 if (conn_state->crtc != &crtc->base) 1591 continue; 1592 1593 if (encoder->pre_enable) 1594 encoder->pre_enable(state, encoder, 1595 crtc_state, conn_state); 1596 } 1597 } 1598 1599 static void intel_encoders_enable(struct intel_atomic_state *state, 1600 struct intel_crtc *crtc) 1601 { 1602 const struct intel_crtc_state *crtc_state = 1603 intel_atomic_get_new_crtc_state(state, crtc); 1604 const struct drm_connector_state *conn_state; 1605 struct drm_connector *conn; 1606 int i; 1607 1608 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1609 struct intel_encoder *encoder = 1610 to_intel_encoder(conn_state->best_encoder); 1611 1612 if (conn_state->crtc != &crtc->base) 1613 continue; 1614 1615 if (encoder->enable) 1616 encoder->enable(state, encoder, 1617 crtc_state, conn_state); 1618 intel_opregion_notify_encoder(encoder, true); 1619 } 1620 } 1621 1622 static void intel_encoders_disable(struct intel_atomic_state *state, 1623 struct intel_crtc *crtc) 1624 { 1625 const struct intel_crtc_state *old_crtc_state = 1626 intel_atomic_get_old_crtc_state(state, crtc); 1627 const struct drm_connector_state *old_conn_state; 1628 struct drm_connector *conn; 1629 int i; 1630 1631 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1632 struct intel_encoder *encoder = 1633 to_intel_encoder(old_conn_state->best_encoder); 1634 1635 if (old_conn_state->crtc != &crtc->base) 1636 continue; 1637 1638 intel_opregion_notify_encoder(encoder, false); 1639 if (encoder->disable) 1640 encoder->disable(state, encoder, 1641 old_crtc_state, old_conn_state); 1642 } 1643 } 1644 1645 static void intel_encoders_post_disable(struct intel_atomic_state *state, 1646 struct intel_crtc *crtc) 1647 { 1648 const struct intel_crtc_state *old_crtc_state = 1649 intel_atomic_get_old_crtc_state(state, crtc); 1650 const struct drm_connector_state *old_conn_state; 1651 struct drm_connector *conn; 1652 int i; 1653 1654 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1655 struct intel_encoder *encoder = 1656 to_intel_encoder(old_conn_state->best_encoder); 1657 1658 if (old_conn_state->crtc != &crtc->base) 1659 continue; 1660 1661 if (encoder->post_disable) 1662 encoder->post_disable(state, encoder, 1663 old_crtc_state, old_conn_state); 1664 } 1665 } 1666 1667 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state, 1668 struct intel_crtc *crtc) 1669 { 1670 const struct intel_crtc_state *old_crtc_state = 1671 intel_atomic_get_old_crtc_state(state, crtc); 1672 const struct drm_connector_state *old_conn_state; 1673 struct drm_connector *conn; 1674 int i; 1675 1676 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1677 struct intel_encoder *encoder = 1678 to_intel_encoder(old_conn_state->best_encoder); 1679 1680 if (old_conn_state->crtc != &crtc->base) 1681 continue; 1682 1683 if (encoder->post_pll_disable) 1684 encoder->post_pll_disable(state, encoder, 1685 old_crtc_state, old_conn_state); 1686 } 1687 } 1688 1689 static void intel_encoders_update_pipe(struct intel_atomic_state *state, 1690 struct intel_crtc *crtc) 1691 { 1692 const struct intel_crtc_state *crtc_state = 1693 intel_atomic_get_new_crtc_state(state, crtc); 1694 const struct drm_connector_state *conn_state; 1695 struct drm_connector *conn; 1696 int i; 1697 1698 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1699 struct intel_encoder *encoder = 1700 to_intel_encoder(conn_state->best_encoder); 1701 1702 if (conn_state->crtc != &crtc->base) 1703 continue; 1704 1705 if (encoder->update_pipe) 1706 encoder->update_pipe(state, encoder, 1707 crtc_state, conn_state); 1708 } 1709 } 1710 1711 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state) 1712 { 1713 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1714 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 1715 1716 plane->disable_arm(plane, crtc_state); 1717 } 1718 1719 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1720 { 1721 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1722 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1723 1724 if (crtc_state->has_pch_encoder) { 1725 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1726 &crtc_state->fdi_m_n); 1727 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1728 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1729 &crtc_state->dp_m_n); 1730 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1731 &crtc_state->dp_m2_n2); 1732 } 1733 1734 intel_set_transcoder_timings(crtc_state); 1735 1736 ilk_set_pipeconf(crtc_state); 1737 } 1738 1739 static void ilk_crtc_enable(struct intel_atomic_state *state, 1740 struct intel_crtc *crtc) 1741 { 1742 const struct intel_crtc_state *new_crtc_state = 1743 intel_atomic_get_new_crtc_state(state, crtc); 1744 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1745 enum pipe pipe = crtc->pipe; 1746 1747 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1748 return; 1749 1750 /* 1751 * Sometimes spurious CPU pipe underruns happen during FDI 1752 * training, at least with VGA+HDMI cloning. Suppress them. 1753 * 1754 * On ILK we get an occasional spurious CPU pipe underruns 1755 * between eDP port A enable and vdd enable. Also PCH port 1756 * enable seems to result in the occasional CPU pipe underrun. 1757 * 1758 * Spurious PCH underruns also occur during PCH enabling. 1759 */ 1760 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1761 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 1762 1763 ilk_configure_cpu_transcoder(new_crtc_state); 1764 1765 intel_set_pipe_src_size(new_crtc_state); 1766 1767 crtc->active = true; 1768 1769 intel_encoders_pre_enable(state, crtc); 1770 1771 if (new_crtc_state->has_pch_encoder) { 1772 ilk_pch_pre_enable(state, crtc); 1773 } else { 1774 assert_fdi_tx_disabled(dev_priv, pipe); 1775 assert_fdi_rx_disabled(dev_priv, pipe); 1776 } 1777 1778 ilk_pfit_enable(new_crtc_state); 1779 1780 /* 1781 * On ILK+ LUT must be loaded before the pipe is running but with 1782 * clocks enabled 1783 */ 1784 intel_color_load_luts(new_crtc_state); 1785 intel_color_commit_noarm(new_crtc_state); 1786 intel_color_commit_arm(new_crtc_state); 1787 /* update DSPCNTR to configure gamma for pipe bottom color */ 1788 intel_disable_primary_plane(new_crtc_state); 1789 1790 intel_initial_watermarks(state, crtc); 1791 intel_enable_transcoder(new_crtc_state); 1792 1793 if (new_crtc_state->has_pch_encoder) 1794 ilk_pch_enable(state, crtc); 1795 1796 intel_crtc_vblank_on(new_crtc_state); 1797 1798 intel_encoders_enable(state, crtc); 1799 1800 if (HAS_PCH_CPT(dev_priv)) 1801 cpt_verify_modeset(dev_priv, pipe); 1802 1803 /* 1804 * Must wait for vblank to avoid spurious PCH FIFO underruns. 1805 * And a second vblank wait is needed at least on ILK with 1806 * some interlaced HDMI modes. Let's do the double wait always 1807 * in case there are more corner cases we don't know about. 1808 */ 1809 if (new_crtc_state->has_pch_encoder) { 1810 intel_crtc_wait_for_next_vblank(crtc); 1811 intel_crtc_wait_for_next_vblank(crtc); 1812 } 1813 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1814 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 1815 } 1816 1817 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, 1818 enum pipe pipe, bool apply) 1819 { 1820 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)); 1821 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS; 1822 1823 if (apply) 1824 val |= mask; 1825 else 1826 val &= ~mask; 1827 1828 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val); 1829 } 1830 1831 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state) 1832 { 1833 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1834 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1835 1836 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe), 1837 HSW_LINETIME(crtc_state->linetime) | 1838 HSW_IPS_LINETIME(crtc_state->ips_linetime)); 1839 } 1840 1841 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) 1842 { 1843 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1844 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1845 i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder); 1846 u32 val; 1847 1848 val = intel_de_read(dev_priv, reg); 1849 val &= ~HSW_FRAME_START_DELAY_MASK; 1850 val |= HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 1851 intel_de_write(dev_priv, reg, val); 1852 } 1853 1854 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state, 1855 const struct intel_crtc_state *crtc_state) 1856 { 1857 struct intel_crtc *master_crtc = intel_master_crtc(crtc_state); 1858 1859 /* 1860 * Enable sequence steps 1-7 on bigjoiner master 1861 */ 1862 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1863 intel_encoders_pre_pll_enable(state, master_crtc); 1864 1865 if (crtc_state->shared_dpll) 1866 intel_enable_shared_dpll(crtc_state); 1867 1868 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1869 intel_encoders_pre_enable(state, master_crtc); 1870 } 1871 1872 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1873 { 1874 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1875 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1876 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1877 1878 if (crtc_state->has_pch_encoder) { 1879 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1880 &crtc_state->fdi_m_n); 1881 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1882 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1883 &crtc_state->dp_m_n); 1884 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1885 &crtc_state->dp_m2_n2); 1886 } 1887 1888 intel_set_transcoder_timings(crtc_state); 1889 1890 if (cpu_transcoder != TRANSCODER_EDP) 1891 intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder), 1892 crtc_state->pixel_multiplier - 1); 1893 1894 hsw_set_frame_start_delay(crtc_state); 1895 1896 hsw_set_transconf(crtc_state); 1897 } 1898 1899 static void hsw_crtc_enable(struct intel_atomic_state *state, 1900 struct intel_crtc *crtc) 1901 { 1902 const struct intel_crtc_state *new_crtc_state = 1903 intel_atomic_get_new_crtc_state(state, crtc); 1904 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1905 enum pipe pipe = crtc->pipe, hsw_workaround_pipe; 1906 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 1907 bool psl_clkgate_wa; 1908 1909 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1910 return; 1911 1912 if (!new_crtc_state->bigjoiner_pipes) { 1913 intel_encoders_pre_pll_enable(state, crtc); 1914 1915 if (new_crtc_state->shared_dpll) 1916 intel_enable_shared_dpll(new_crtc_state); 1917 1918 intel_encoders_pre_enable(state, crtc); 1919 } else { 1920 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state); 1921 } 1922 1923 intel_dsc_enable(new_crtc_state); 1924 1925 if (DISPLAY_VER(dev_priv) >= 13) 1926 intel_uncompressed_joiner_enable(new_crtc_state); 1927 1928 intel_set_pipe_src_size(new_crtc_state); 1929 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 1930 bdw_set_pipemisc(new_crtc_state); 1931 1932 if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) && 1933 !transcoder_is_dsi(cpu_transcoder)) 1934 hsw_configure_cpu_transcoder(new_crtc_state); 1935 1936 crtc->active = true; 1937 1938 /* Display WA #1180: WaDisableScalarClockGating: glk */ 1939 psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 && 1940 new_crtc_state->pch_pfit.enabled; 1941 if (psl_clkgate_wa) 1942 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true); 1943 1944 if (DISPLAY_VER(dev_priv) >= 9) 1945 skl_pfit_enable(new_crtc_state); 1946 else 1947 ilk_pfit_enable(new_crtc_state); 1948 1949 /* 1950 * On ILK+ LUT must be loaded before the pipe is running but with 1951 * clocks enabled 1952 */ 1953 intel_color_load_luts(new_crtc_state); 1954 intel_color_commit_noarm(new_crtc_state); 1955 intel_color_commit_arm(new_crtc_state); 1956 /* update DSPCNTR to configure gamma/csc for pipe bottom color */ 1957 if (DISPLAY_VER(dev_priv) < 9) 1958 intel_disable_primary_plane(new_crtc_state); 1959 1960 hsw_set_linetime_wm(new_crtc_state); 1961 1962 if (DISPLAY_VER(dev_priv) >= 11) 1963 icl_set_pipe_chicken(new_crtc_state); 1964 1965 intel_initial_watermarks(state, crtc); 1966 1967 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 1968 intel_crtc_vblank_on(new_crtc_state); 1969 1970 intel_encoders_enable(state, crtc); 1971 1972 if (psl_clkgate_wa) { 1973 intel_crtc_wait_for_next_vblank(crtc); 1974 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false); 1975 } 1976 1977 /* If we change the relative order between pipe/planes enabling, we need 1978 * to change the workaround. */ 1979 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe; 1980 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { 1981 struct intel_crtc *wa_crtc; 1982 1983 wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe); 1984 1985 intel_crtc_wait_for_next_vblank(wa_crtc); 1986 intel_crtc_wait_for_next_vblank(wa_crtc); 1987 } 1988 } 1989 1990 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state) 1991 { 1992 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1993 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1994 enum pipe pipe = crtc->pipe; 1995 1996 /* To avoid upsetting the power well on haswell only disable the pfit if 1997 * it's in use. The hw state code will make sure we get this right. */ 1998 if (!old_crtc_state->pch_pfit.enabled) 1999 return; 2000 2001 intel_de_write_fw(dev_priv, PF_CTL(pipe), 0); 2002 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0); 2003 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0); 2004 } 2005 2006 static void ilk_crtc_disable(struct intel_atomic_state *state, 2007 struct intel_crtc *crtc) 2008 { 2009 const struct intel_crtc_state *old_crtc_state = 2010 intel_atomic_get_old_crtc_state(state, crtc); 2011 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2012 enum pipe pipe = crtc->pipe; 2013 2014 /* 2015 * Sometimes spurious CPU pipe underruns happen when the 2016 * pipe is already disabled, but FDI RX/TX is still enabled. 2017 * Happens at least with VGA+HDMI cloning. Suppress them. 2018 */ 2019 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 2020 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 2021 2022 intel_encoders_disable(state, crtc); 2023 2024 intel_crtc_vblank_off(old_crtc_state); 2025 2026 intel_disable_transcoder(old_crtc_state); 2027 2028 ilk_pfit_disable(old_crtc_state); 2029 2030 if (old_crtc_state->has_pch_encoder) 2031 ilk_pch_disable(state, crtc); 2032 2033 intel_encoders_post_disable(state, crtc); 2034 2035 if (old_crtc_state->has_pch_encoder) 2036 ilk_pch_post_disable(state, crtc); 2037 2038 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2039 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 2040 } 2041 2042 static void hsw_crtc_disable(struct intel_atomic_state *state, 2043 struct intel_crtc *crtc) 2044 { 2045 const struct intel_crtc_state *old_crtc_state = 2046 intel_atomic_get_old_crtc_state(state, crtc); 2047 2048 /* 2049 * FIXME collapse everything to one hook. 2050 * Need care with mst->ddi interactions. 2051 */ 2052 if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) { 2053 intel_encoders_disable(state, crtc); 2054 intel_encoders_post_disable(state, crtc); 2055 } 2056 } 2057 2058 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) 2059 { 2060 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2061 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2062 2063 if (!crtc_state->gmch_pfit.control) 2064 return; 2065 2066 /* 2067 * The panel fitter should only be adjusted whilst the pipe is disabled, 2068 * according to register description and PRM. 2069 */ 2070 drm_WARN_ON(&dev_priv->drm, 2071 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE); 2072 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 2073 2074 intel_de_write(dev_priv, PFIT_PGM_RATIOS, 2075 crtc_state->gmch_pfit.pgm_ratios); 2076 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control); 2077 2078 /* Border color in case we don't scale up to the full screen. Black by 2079 * default, change to something else for debugging. */ 2080 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); 2081 } 2082 2083 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) 2084 { 2085 if (phy == PHY_NONE) 2086 return false; 2087 else if (IS_DG2(dev_priv)) 2088 /* 2089 * DG2 outputs labelled as "combo PHY" in the bspec use 2090 * SNPS PHYs with completely different programming, 2091 * hence we always return false here. 2092 */ 2093 return false; 2094 else if (IS_ALDERLAKE_S(dev_priv)) 2095 return phy <= PHY_E; 2096 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) 2097 return phy <= PHY_D; 2098 else if (IS_JSL_EHL(dev_priv)) 2099 return phy <= PHY_C; 2100 else if (DISPLAY_VER(dev_priv) >= 11) 2101 return phy <= PHY_B; 2102 else 2103 return false; 2104 } 2105 2106 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) 2107 { 2108 if (IS_DG2(dev_priv)) 2109 /* DG2's "TC1" output uses a SNPS PHY */ 2110 return false; 2111 else if (IS_ALDERLAKE_P(dev_priv)) 2112 return phy >= PHY_F && phy <= PHY_I; 2113 else if (IS_TIGERLAKE(dev_priv)) 2114 return phy >= PHY_D && phy <= PHY_I; 2115 else if (IS_ICELAKE(dev_priv)) 2116 return phy >= PHY_C && phy <= PHY_F; 2117 else 2118 return false; 2119 } 2120 2121 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy) 2122 { 2123 if (phy == PHY_NONE) 2124 return false; 2125 else if (IS_DG2(dev_priv)) 2126 /* 2127 * All four "combo" ports and the TC1 port (PHY E) use 2128 * Synopsis PHYs. 2129 */ 2130 return phy <= PHY_E; 2131 2132 return false; 2133 } 2134 2135 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) 2136 { 2137 if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD) 2138 return PHY_D + port - PORT_D_XELPD; 2139 else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1) 2140 return PHY_F + port - PORT_TC1; 2141 else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1) 2142 return PHY_B + port - PORT_TC1; 2143 else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1) 2144 return PHY_C + port - PORT_TC1; 2145 else if (IS_JSL_EHL(i915) && port == PORT_D) 2146 return PHY_A; 2147 2148 return PHY_A + port - PORT_A; 2149 } 2150 2151 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) 2152 { 2153 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port))) 2154 return TC_PORT_NONE; 2155 2156 if (DISPLAY_VER(dev_priv) >= 12) 2157 return TC_PORT_1 + port - PORT_TC1; 2158 else 2159 return TC_PORT_1 + port - PORT_C; 2160 } 2161 2162 enum intel_display_power_domain 2163 intel_aux_power_domain(struct intel_digital_port *dig_port) 2164 { 2165 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 2166 2167 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 2168 return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch); 2169 2170 return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch); 2171 } 2172 2173 static void get_crtc_power_domains(struct intel_crtc_state *crtc_state, 2174 struct intel_power_domain_mask *mask) 2175 { 2176 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2177 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2178 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2179 struct drm_encoder *encoder; 2180 enum pipe pipe = crtc->pipe; 2181 2182 bitmap_zero(mask->bits, POWER_DOMAIN_NUM); 2183 2184 if (!crtc_state->hw.active) 2185 return; 2186 2187 set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits); 2188 set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits); 2189 if (crtc_state->pch_pfit.enabled || 2190 crtc_state->pch_pfit.force_thru) 2191 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits); 2192 2193 drm_for_each_encoder_mask(encoder, &dev_priv->drm, 2194 crtc_state->uapi.encoder_mask) { 2195 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2196 2197 set_bit(intel_encoder->power_domain, mask->bits); 2198 } 2199 2200 if (HAS_DDI(dev_priv) && crtc_state->has_audio) 2201 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits); 2202 2203 if (crtc_state->shared_dpll) 2204 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits); 2205 2206 if (crtc_state->dsc.compression_enable) 2207 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits); 2208 } 2209 2210 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, 2211 struct intel_power_domain_mask *old_domains) 2212 { 2213 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2214 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2215 enum intel_display_power_domain domain; 2216 struct intel_power_domain_mask domains, new_domains; 2217 2218 get_crtc_power_domains(crtc_state, &domains); 2219 2220 bitmap_andnot(new_domains.bits, 2221 domains.bits, 2222 crtc->enabled_power_domains.mask.bits, 2223 POWER_DOMAIN_NUM); 2224 bitmap_andnot(old_domains->bits, 2225 crtc->enabled_power_domains.mask.bits, 2226 domains.bits, 2227 POWER_DOMAIN_NUM); 2228 2229 for_each_power_domain(domain, &new_domains) 2230 intel_display_power_get_in_set(dev_priv, 2231 &crtc->enabled_power_domains, 2232 domain); 2233 } 2234 2235 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc, 2236 struct intel_power_domain_mask *domains) 2237 { 2238 intel_display_power_put_mask_in_set(to_i915(crtc->base.dev), 2239 &crtc->enabled_power_domains, 2240 domains); 2241 } 2242 2243 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 2244 { 2245 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2246 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2247 2248 if (intel_crtc_has_dp_encoder(crtc_state)) { 2249 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 2250 &crtc_state->dp_m_n); 2251 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 2252 &crtc_state->dp_m2_n2); 2253 } 2254 2255 intel_set_transcoder_timings(crtc_state); 2256 2257 i9xx_set_pipeconf(crtc_state); 2258 } 2259 2260 static void valleyview_crtc_enable(struct intel_atomic_state *state, 2261 struct intel_crtc *crtc) 2262 { 2263 const struct intel_crtc_state *new_crtc_state = 2264 intel_atomic_get_new_crtc_state(state, crtc); 2265 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2266 enum pipe pipe = crtc->pipe; 2267 2268 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 2269 return; 2270 2271 i9xx_configure_cpu_transcoder(new_crtc_state); 2272 2273 intel_set_pipe_src_size(new_crtc_state); 2274 2275 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 2276 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY); 2277 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0); 2278 } 2279 2280 crtc->active = true; 2281 2282 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2283 2284 intel_encoders_pre_pll_enable(state, crtc); 2285 2286 if (IS_CHERRYVIEW(dev_priv)) 2287 chv_enable_pll(new_crtc_state); 2288 else 2289 vlv_enable_pll(new_crtc_state); 2290 2291 intel_encoders_pre_enable(state, crtc); 2292 2293 i9xx_pfit_enable(new_crtc_state); 2294 2295 intel_color_load_luts(new_crtc_state); 2296 intel_color_commit_noarm(new_crtc_state); 2297 intel_color_commit_arm(new_crtc_state); 2298 /* update DSPCNTR to configure gamma for pipe bottom color */ 2299 intel_disable_primary_plane(new_crtc_state); 2300 2301 intel_initial_watermarks(state, crtc); 2302 intel_enable_transcoder(new_crtc_state); 2303 2304 intel_crtc_vblank_on(new_crtc_state); 2305 2306 intel_encoders_enable(state, crtc); 2307 } 2308 2309 static void i9xx_crtc_enable(struct intel_atomic_state *state, 2310 struct intel_crtc *crtc) 2311 { 2312 const struct intel_crtc_state *new_crtc_state = 2313 intel_atomic_get_new_crtc_state(state, crtc); 2314 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2315 enum pipe pipe = crtc->pipe; 2316 2317 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 2318 return; 2319 2320 i9xx_configure_cpu_transcoder(new_crtc_state); 2321 2322 intel_set_pipe_src_size(new_crtc_state); 2323 2324 crtc->active = true; 2325 2326 if (DISPLAY_VER(dev_priv) != 2) 2327 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2328 2329 intel_encoders_pre_enable(state, crtc); 2330 2331 i9xx_enable_pll(new_crtc_state); 2332 2333 i9xx_pfit_enable(new_crtc_state); 2334 2335 intel_color_load_luts(new_crtc_state); 2336 intel_color_commit_noarm(new_crtc_state); 2337 intel_color_commit_arm(new_crtc_state); 2338 /* update DSPCNTR to configure gamma for pipe bottom color */ 2339 intel_disable_primary_plane(new_crtc_state); 2340 2341 if (!intel_initial_watermarks(state, crtc)) 2342 intel_update_watermarks(dev_priv); 2343 intel_enable_transcoder(new_crtc_state); 2344 2345 intel_crtc_vblank_on(new_crtc_state); 2346 2347 intel_encoders_enable(state, crtc); 2348 2349 /* prevents spurious underruns */ 2350 if (DISPLAY_VER(dev_priv) == 2) 2351 intel_crtc_wait_for_next_vblank(crtc); 2352 } 2353 2354 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) 2355 { 2356 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 2357 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2358 2359 if (!old_crtc_state->gmch_pfit.control) 2360 return; 2361 2362 assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder); 2363 2364 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n", 2365 intel_de_read(dev_priv, PFIT_CONTROL)); 2366 intel_de_write(dev_priv, PFIT_CONTROL, 0); 2367 } 2368 2369 static void i9xx_crtc_disable(struct intel_atomic_state *state, 2370 struct intel_crtc *crtc) 2371 { 2372 struct intel_crtc_state *old_crtc_state = 2373 intel_atomic_get_old_crtc_state(state, crtc); 2374 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2375 enum pipe pipe = crtc->pipe; 2376 2377 /* 2378 * On gen2 planes are double buffered but the pipe isn't, so we must 2379 * wait for planes to fully turn off before disabling the pipe. 2380 */ 2381 if (DISPLAY_VER(dev_priv) == 2) 2382 intel_crtc_wait_for_next_vblank(crtc); 2383 2384 intel_encoders_disable(state, crtc); 2385 2386 intel_crtc_vblank_off(old_crtc_state); 2387 2388 intel_disable_transcoder(old_crtc_state); 2389 2390 i9xx_pfit_disable(old_crtc_state); 2391 2392 intel_encoders_post_disable(state, crtc); 2393 2394 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) { 2395 if (IS_CHERRYVIEW(dev_priv)) 2396 chv_disable_pll(dev_priv, pipe); 2397 else if (IS_VALLEYVIEW(dev_priv)) 2398 vlv_disable_pll(dev_priv, pipe); 2399 else 2400 i9xx_disable_pll(old_crtc_state); 2401 } 2402 2403 intel_encoders_post_pll_disable(state, crtc); 2404 2405 if (DISPLAY_VER(dev_priv) != 2) 2406 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 2407 2408 if (!dev_priv->wm_disp->initial_watermarks) 2409 intel_update_watermarks(dev_priv); 2410 2411 /* clock the pipe down to 640x480@60 to potentially save power */ 2412 if (IS_I830(dev_priv)) 2413 i830_enable_pipe(dev_priv, pipe); 2414 } 2415 2416 2417 /* 2418 * turn all crtc's off, but do not adjust state 2419 * This has to be paired with a call to intel_modeset_setup_hw_state. 2420 */ 2421 int intel_display_suspend(struct drm_device *dev) 2422 { 2423 struct drm_i915_private *dev_priv = to_i915(dev); 2424 struct drm_atomic_state *state; 2425 int ret; 2426 2427 if (!HAS_DISPLAY(dev_priv)) 2428 return 0; 2429 2430 state = drm_atomic_helper_suspend(dev); 2431 ret = PTR_ERR_OR_ZERO(state); 2432 if (ret) 2433 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", 2434 ret); 2435 else 2436 dev_priv->modeset_restore_state = state; 2437 return ret; 2438 } 2439 2440 void intel_encoder_destroy(struct drm_encoder *encoder) 2441 { 2442 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2443 2444 drm_encoder_cleanup(encoder); 2445 kfree(intel_encoder); 2446 } 2447 2448 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) 2449 { 2450 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2451 2452 /* GDG double wide on either pipe, otherwise pipe A only */ 2453 return DISPLAY_VER(dev_priv) < 4 && 2454 (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); 2455 } 2456 2457 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) 2458 { 2459 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock; 2460 struct drm_rect src; 2461 2462 /* 2463 * We only use IF-ID interlacing. If we ever use 2464 * PF-ID we'll need to adjust the pixel_rate here. 2465 */ 2466 2467 if (!crtc_state->pch_pfit.enabled) 2468 return pixel_rate; 2469 2470 drm_rect_init(&src, 0, 0, 2471 drm_rect_width(&crtc_state->pipe_src) << 16, 2472 drm_rect_height(&crtc_state->pipe_src) << 16); 2473 2474 return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst, 2475 pixel_rate); 2476 } 2477 2478 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode, 2479 const struct drm_display_mode *timings) 2480 { 2481 mode->hdisplay = timings->crtc_hdisplay; 2482 mode->htotal = timings->crtc_htotal; 2483 mode->hsync_start = timings->crtc_hsync_start; 2484 mode->hsync_end = timings->crtc_hsync_end; 2485 2486 mode->vdisplay = timings->crtc_vdisplay; 2487 mode->vtotal = timings->crtc_vtotal; 2488 mode->vsync_start = timings->crtc_vsync_start; 2489 mode->vsync_end = timings->crtc_vsync_end; 2490 2491 mode->flags = timings->flags; 2492 mode->type = DRM_MODE_TYPE_DRIVER; 2493 2494 mode->clock = timings->crtc_clock; 2495 2496 drm_mode_set_name(mode); 2497 } 2498 2499 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) 2500 { 2501 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2502 2503 if (HAS_GMCH(dev_priv)) 2504 /* FIXME calculate proper pipe pixel rate for GMCH pfit */ 2505 crtc_state->pixel_rate = 2506 crtc_state->hw.pipe_mode.crtc_clock; 2507 else 2508 crtc_state->pixel_rate = 2509 ilk_pipe_pixel_rate(crtc_state); 2510 } 2511 2512 static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state *crtc_state, 2513 struct drm_display_mode *mode) 2514 { 2515 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2516 2517 if (num_pipes < 2) 2518 return; 2519 2520 mode->crtc_clock /= num_pipes; 2521 mode->crtc_hdisplay /= num_pipes; 2522 mode->crtc_hblank_start /= num_pipes; 2523 mode->crtc_hblank_end /= num_pipes; 2524 mode->crtc_hsync_start /= num_pipes; 2525 mode->crtc_hsync_end /= num_pipes; 2526 mode->crtc_htotal /= num_pipes; 2527 } 2528 2529 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state, 2530 struct drm_display_mode *mode) 2531 { 2532 int overlap = crtc_state->splitter.pixel_overlap; 2533 int n = crtc_state->splitter.link_count; 2534 2535 if (!crtc_state->splitter.enable) 2536 return; 2537 2538 /* 2539 * eDP MSO uses segment timings from EDID for transcoder 2540 * timings, but full mode for everything else. 2541 * 2542 * h_full = (h_segment - pixel_overlap) * link_count 2543 */ 2544 mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n; 2545 mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n; 2546 mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n; 2547 mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n; 2548 mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n; 2549 mode->crtc_htotal = (mode->crtc_htotal - overlap) * n; 2550 mode->crtc_clock *= n; 2551 } 2552 2553 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state) 2554 { 2555 struct drm_display_mode *mode = &crtc_state->hw.mode; 2556 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2557 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2558 2559 /* 2560 * Start with the adjusted_mode crtc timings, which 2561 * have been filled with the transcoder timings. 2562 */ 2563 drm_mode_copy(pipe_mode, adjusted_mode); 2564 2565 /* Expand MSO per-segment transcoder timings to full */ 2566 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2567 2568 /* 2569 * We want the full numbers in adjusted_mode normal timings, 2570 * adjusted_mode crtc timings are left with the raw transcoder 2571 * timings. 2572 */ 2573 intel_mode_from_crtc_timings(adjusted_mode, pipe_mode); 2574 2575 /* Populate the "user" mode with full numbers */ 2576 drm_mode_copy(mode, pipe_mode); 2577 intel_mode_from_crtc_timings(mode, mode); 2578 mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) * 2579 (intel_bigjoiner_num_pipes(crtc_state) ?: 1); 2580 mode->vdisplay = drm_rect_height(&crtc_state->pipe_src); 2581 2582 /* Derive per-pipe timings in case bigjoiner is used */ 2583 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2584 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2585 2586 intel_crtc_compute_pixel_rate(crtc_state); 2587 } 2588 2589 void intel_encoder_get_config(struct intel_encoder *encoder, 2590 struct intel_crtc_state *crtc_state) 2591 { 2592 encoder->get_config(encoder, crtc_state); 2593 2594 intel_crtc_readout_derived_state(crtc_state); 2595 } 2596 2597 static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state *crtc_state) 2598 { 2599 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2600 int width, height; 2601 2602 if (num_pipes < 2) 2603 return; 2604 2605 width = drm_rect_width(&crtc_state->pipe_src); 2606 height = drm_rect_height(&crtc_state->pipe_src); 2607 2608 drm_rect_init(&crtc_state->pipe_src, 0, 0, 2609 width / num_pipes, height); 2610 } 2611 2612 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state) 2613 { 2614 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2615 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2616 2617 intel_bigjoiner_compute_pipe_src(crtc_state); 2618 2619 /* 2620 * Pipe horizontal size must be even in: 2621 * - DVO ganged mode 2622 * - LVDS dual channel mode 2623 * - Double wide pipe 2624 */ 2625 if (drm_rect_width(&crtc_state->pipe_src) & 1) { 2626 if (crtc_state->double_wide) { 2627 drm_dbg_kms(&i915->drm, 2628 "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n", 2629 crtc->base.base.id, crtc->base.name); 2630 return -EINVAL; 2631 } 2632 2633 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 2634 intel_is_dual_link_lvds(i915)) { 2635 drm_dbg_kms(&i915->drm, 2636 "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n", 2637 crtc->base.base.id, crtc->base.name); 2638 return -EINVAL; 2639 } 2640 } 2641 2642 return 0; 2643 } 2644 2645 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state) 2646 { 2647 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2648 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2649 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2650 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2651 int clock_limit = i915->max_dotclk_freq; 2652 2653 /* 2654 * Start with the adjusted_mode crtc timings, which 2655 * have been filled with the transcoder timings. 2656 */ 2657 drm_mode_copy(pipe_mode, adjusted_mode); 2658 2659 /* Expand MSO per-segment transcoder timings to full */ 2660 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2661 2662 /* Derive per-pipe timings in case bigjoiner is used */ 2663 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2664 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2665 2666 if (DISPLAY_VER(i915) < 4) { 2667 clock_limit = i915->max_cdclk_freq * 9 / 10; 2668 2669 /* 2670 * Enable double wide mode when the dot clock 2671 * is > 90% of the (display) core speed. 2672 */ 2673 if (intel_crtc_supports_double_wide(crtc) && 2674 pipe_mode->crtc_clock > clock_limit) { 2675 clock_limit = i915->max_dotclk_freq; 2676 crtc_state->double_wide = true; 2677 } 2678 } 2679 2680 if (pipe_mode->crtc_clock > clock_limit) { 2681 drm_dbg_kms(&i915->drm, 2682 "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", 2683 crtc->base.base.id, crtc->base.name, 2684 pipe_mode->crtc_clock, clock_limit, 2685 str_yes_no(crtc_state->double_wide)); 2686 return -EINVAL; 2687 } 2688 2689 return 0; 2690 } 2691 2692 static int intel_crtc_compute_config(struct intel_atomic_state *state, 2693 struct intel_crtc *crtc) 2694 { 2695 struct intel_crtc_state *crtc_state = 2696 intel_atomic_get_new_crtc_state(state, crtc); 2697 int ret; 2698 2699 ret = intel_crtc_compute_pipe_src(crtc_state); 2700 if (ret) 2701 return ret; 2702 2703 ret = intel_crtc_compute_pipe_mode(crtc_state); 2704 if (ret) 2705 return ret; 2706 2707 intel_crtc_compute_pixel_rate(crtc_state); 2708 2709 if (crtc_state->has_pch_encoder) 2710 return ilk_fdi_compute_config(crtc, crtc_state); 2711 2712 return 0; 2713 } 2714 2715 static void 2716 intel_reduce_m_n_ratio(u32 *num, u32 *den) 2717 { 2718 while (*num > DATA_LINK_M_N_MASK || 2719 *den > DATA_LINK_M_N_MASK) { 2720 *num >>= 1; 2721 *den >>= 1; 2722 } 2723 } 2724 2725 static void compute_m_n(unsigned int m, unsigned int n, 2726 u32 *ret_m, u32 *ret_n, 2727 bool constant_n) 2728 { 2729 /* 2730 * Several DP dongles in particular seem to be fussy about 2731 * too large link M/N values. Give N value as 0x8000 that 2732 * should be acceptable by specific devices. 0x8000 is the 2733 * specified fixed N value for asynchronous clock mode, 2734 * which the devices expect also in synchronous clock mode. 2735 */ 2736 if (constant_n) 2737 *ret_n = DP_LINK_CONSTANT_N_VALUE; 2738 else 2739 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); 2740 2741 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n); 2742 intel_reduce_m_n_ratio(ret_m, ret_n); 2743 } 2744 2745 void 2746 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes, 2747 int pixel_clock, int link_clock, 2748 struct intel_link_m_n *m_n, 2749 bool constant_n, bool fec_enable) 2750 { 2751 u32 data_clock = bits_per_pixel * pixel_clock; 2752 2753 if (fec_enable) 2754 data_clock = intel_dp_mode_to_fec_clock(data_clock); 2755 2756 m_n->tu = 64; 2757 compute_m_n(data_clock, 2758 link_clock * nlanes * 8, 2759 &m_n->data_m, &m_n->data_n, 2760 constant_n); 2761 2762 compute_m_n(pixel_clock, link_clock, 2763 &m_n->link_m, &m_n->link_n, 2764 constant_n); 2765 } 2766 2767 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv) 2768 { 2769 /* 2770 * There may be no VBT; and if the BIOS enabled SSC we can 2771 * just keep using it to avoid unnecessary flicker. Whereas if the 2772 * BIOS isn't using it, don't assume it will work even if the VBT 2773 * indicates as much. 2774 */ 2775 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { 2776 bool bios_lvds_use_ssc = intel_de_read(dev_priv, 2777 PCH_DREF_CONTROL) & 2778 DREF_SSC1_ENABLE; 2779 2780 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { 2781 drm_dbg_kms(&dev_priv->drm, 2782 "SSC %s by BIOS, overriding VBT which says %s\n", 2783 str_enabled_disabled(bios_lvds_use_ssc), 2784 str_enabled_disabled(dev_priv->vbt.lvds_use_ssc)); 2785 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; 2786 } 2787 } 2788 } 2789 2790 void intel_zero_m_n(struct intel_link_m_n *m_n) 2791 { 2792 /* corresponds to 0 register value */ 2793 memset(m_n, 0, sizeof(*m_n)); 2794 m_n->tu = 1; 2795 } 2796 2797 void intel_set_m_n(struct drm_i915_private *i915, 2798 const struct intel_link_m_n *m_n, 2799 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 2800 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 2801 { 2802 intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); 2803 intel_de_write(i915, data_n_reg, m_n->data_n); 2804 intel_de_write(i915, link_m_reg, m_n->link_m); 2805 /* 2806 * On BDW+ writing LINK_N arms the double buffered update 2807 * of all the M/N registers, so it must be written last. 2808 */ 2809 intel_de_write(i915, link_n_reg, m_n->link_n); 2810 } 2811 2812 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, 2813 enum transcoder transcoder) 2814 { 2815 if (IS_HASWELL(dev_priv)) 2816 return transcoder == TRANSCODER_EDP; 2817 2818 return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv); 2819 } 2820 2821 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, 2822 enum transcoder transcoder, 2823 const struct intel_link_m_n *m_n) 2824 { 2825 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2826 enum pipe pipe = crtc->pipe; 2827 2828 if (DISPLAY_VER(dev_priv) >= 5) 2829 intel_set_m_n(dev_priv, m_n, 2830 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 2831 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 2832 else 2833 intel_set_m_n(dev_priv, m_n, 2834 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 2835 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 2836 } 2837 2838 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, 2839 enum transcoder transcoder, 2840 const struct intel_link_m_n *m_n) 2841 { 2842 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2843 2844 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 2845 return; 2846 2847 intel_set_m_n(dev_priv, m_n, 2848 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 2849 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 2850 } 2851 2852 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) 2853 { 2854 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2855 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2856 enum pipe pipe = crtc->pipe; 2857 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2858 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2859 u32 crtc_vtotal, crtc_vblank_end; 2860 int vsyncshift = 0; 2861 2862 /* We need to be careful not to changed the adjusted mode, for otherwise 2863 * the hw state checker will get angry at the mismatch. */ 2864 crtc_vtotal = adjusted_mode->crtc_vtotal; 2865 crtc_vblank_end = adjusted_mode->crtc_vblank_end; 2866 2867 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 2868 /* the chip adds 2 halflines automatically */ 2869 crtc_vtotal -= 1; 2870 crtc_vblank_end -= 1; 2871 2872 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 2873 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; 2874 else 2875 vsyncshift = adjusted_mode->crtc_hsync_start - 2876 adjusted_mode->crtc_htotal / 2; 2877 if (vsyncshift < 0) 2878 vsyncshift += adjusted_mode->crtc_htotal; 2879 } 2880 2881 if (DISPLAY_VER(dev_priv) > 3) 2882 intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder), 2883 vsyncshift); 2884 2885 intel_de_write(dev_priv, HTOTAL(cpu_transcoder), 2886 (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16)); 2887 intel_de_write(dev_priv, HBLANK(cpu_transcoder), 2888 (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16)); 2889 intel_de_write(dev_priv, HSYNC(cpu_transcoder), 2890 (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16)); 2891 2892 intel_de_write(dev_priv, VTOTAL(cpu_transcoder), 2893 (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16)); 2894 intel_de_write(dev_priv, VBLANK(cpu_transcoder), 2895 (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16)); 2896 intel_de_write(dev_priv, VSYNC(cpu_transcoder), 2897 (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16)); 2898 2899 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be 2900 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is 2901 * documented on the DDI_FUNC_CTL register description, EDP Input Select 2902 * bits. */ 2903 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && 2904 (pipe == PIPE_B || pipe == PIPE_C)) 2905 intel_de_write(dev_priv, VTOTAL(pipe), 2906 intel_de_read(dev_priv, VTOTAL(cpu_transcoder))); 2907 2908 } 2909 2910 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) 2911 { 2912 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2913 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2914 int width = drm_rect_width(&crtc_state->pipe_src); 2915 int height = drm_rect_height(&crtc_state->pipe_src); 2916 enum pipe pipe = crtc->pipe; 2917 2918 /* pipesrc controls the size that is scaled from, which should 2919 * always be the user's requested size. 2920 */ 2921 intel_de_write(dev_priv, PIPESRC(pipe), 2922 PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1)); 2923 } 2924 2925 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) 2926 { 2927 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2928 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2929 2930 if (DISPLAY_VER(dev_priv) == 2) 2931 return false; 2932 2933 if (DISPLAY_VER(dev_priv) >= 9 || 2934 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2935 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW; 2936 else 2937 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK; 2938 } 2939 2940 static void intel_get_transcoder_timings(struct intel_crtc *crtc, 2941 struct intel_crtc_state *pipe_config) 2942 { 2943 struct drm_device *dev = crtc->base.dev; 2944 struct drm_i915_private *dev_priv = to_i915(dev); 2945 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 2946 u32 tmp; 2947 2948 tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder)); 2949 pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; 2950 pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; 2951 2952 if (!transcoder_is_dsi(cpu_transcoder)) { 2953 tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder)); 2954 pipe_config->hw.adjusted_mode.crtc_hblank_start = 2955 (tmp & 0xffff) + 1; 2956 pipe_config->hw.adjusted_mode.crtc_hblank_end = 2957 ((tmp >> 16) & 0xffff) + 1; 2958 } 2959 tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder)); 2960 pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; 2961 pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; 2962 2963 tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder)); 2964 pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; 2965 pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; 2966 2967 if (!transcoder_is_dsi(cpu_transcoder)) { 2968 tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder)); 2969 pipe_config->hw.adjusted_mode.crtc_vblank_start = 2970 (tmp & 0xffff) + 1; 2971 pipe_config->hw.adjusted_mode.crtc_vblank_end = 2972 ((tmp >> 16) & 0xffff) + 1; 2973 } 2974 tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder)); 2975 pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; 2976 pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; 2977 2978 if (intel_pipe_is_interlaced(pipe_config)) { 2979 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; 2980 pipe_config->hw.adjusted_mode.crtc_vtotal += 1; 2981 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1; 2982 } 2983 } 2984 2985 static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state) 2986 { 2987 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2988 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2989 enum pipe master_pipe, pipe = crtc->pipe; 2990 int width; 2991 2992 if (num_pipes < 2) 2993 return; 2994 2995 master_pipe = bigjoiner_master_pipe(crtc_state); 2996 width = drm_rect_width(&crtc_state->pipe_src); 2997 2998 drm_rect_translate_to(&crtc_state->pipe_src, 2999 (pipe - master_pipe) * width, 0); 3000 } 3001 3002 static void intel_get_pipe_src_size(struct intel_crtc *crtc, 3003 struct intel_crtc_state *pipe_config) 3004 { 3005 struct drm_device *dev = crtc->base.dev; 3006 struct drm_i915_private *dev_priv = to_i915(dev); 3007 u32 tmp; 3008 3009 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe)); 3010 3011 drm_rect_init(&pipe_config->pipe_src, 0, 0, 3012 REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1, 3013 REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1); 3014 3015 intel_bigjoiner_adjust_pipe_src(pipe_config); 3016 } 3017 3018 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) 3019 { 3020 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3021 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3022 u32 pipeconf = 0; 3023 3024 /* we keep both pipes enabled on 830 */ 3025 if (IS_I830(dev_priv)) 3026 pipeconf |= PIPECONF_ENABLE; 3027 3028 if (crtc_state->double_wide) 3029 pipeconf |= PIPECONF_DOUBLE_WIDE; 3030 3031 /* only g4x and later have fancy bpc/dither controls */ 3032 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 3033 IS_CHERRYVIEW(dev_priv)) { 3034 /* Bspec claims that we can't use dithering for 30bpp pipes. */ 3035 if (crtc_state->dither && crtc_state->pipe_bpp != 30) 3036 pipeconf |= PIPECONF_DITHER_EN | 3037 PIPECONF_DITHER_TYPE_SP; 3038 3039 switch (crtc_state->pipe_bpp) { 3040 default: 3041 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3042 MISSING_CASE(crtc_state->pipe_bpp); 3043 fallthrough; 3044 case 18: 3045 pipeconf |= PIPECONF_BPC_6; 3046 break; 3047 case 24: 3048 pipeconf |= PIPECONF_BPC_8; 3049 break; 3050 case 30: 3051 pipeconf |= PIPECONF_BPC_10; 3052 break; 3053 } 3054 } 3055 3056 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 3057 if (DISPLAY_VER(dev_priv) < 4 || 3058 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3059 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; 3060 else 3061 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; 3062 } else { 3063 pipeconf |= PIPECONF_INTERLACE_PROGRESSIVE; 3064 } 3065 3066 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 3067 crtc_state->limited_color_range) 3068 pipeconf |= PIPECONF_COLOR_RANGE_SELECT; 3069 3070 pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); 3071 3072 pipeconf |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3073 3074 intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf); 3075 intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe)); 3076 } 3077 3078 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv) 3079 { 3080 if (IS_I830(dev_priv)) 3081 return false; 3082 3083 return DISPLAY_VER(dev_priv) >= 4 || 3084 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); 3085 } 3086 3087 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state) 3088 { 3089 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3090 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3091 u32 tmp; 3092 3093 if (!i9xx_has_pfit(dev_priv)) 3094 return; 3095 3096 tmp = intel_de_read(dev_priv, PFIT_CONTROL); 3097 if (!(tmp & PFIT_ENABLE)) 3098 return; 3099 3100 /* Check whether the pfit is attached to our pipe. */ 3101 if (DISPLAY_VER(dev_priv) < 4) { 3102 if (crtc->pipe != PIPE_B) 3103 return; 3104 } else { 3105 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) 3106 return; 3107 } 3108 3109 crtc_state->gmch_pfit.control = tmp; 3110 crtc_state->gmch_pfit.pgm_ratios = 3111 intel_de_read(dev_priv, PFIT_PGM_RATIOS); 3112 } 3113 3114 static void vlv_crtc_clock_get(struct intel_crtc *crtc, 3115 struct intel_crtc_state *pipe_config) 3116 { 3117 struct drm_device *dev = crtc->base.dev; 3118 struct drm_i915_private *dev_priv = to_i915(dev); 3119 enum pipe pipe = crtc->pipe; 3120 struct dpll clock; 3121 u32 mdiv; 3122 int refclk = 100000; 3123 3124 /* In case of DSI, DPLL will not be used */ 3125 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 3126 return; 3127 3128 vlv_dpio_get(dev_priv); 3129 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); 3130 vlv_dpio_put(dev_priv); 3131 3132 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; 3133 clock.m2 = mdiv & DPIO_M2DIV_MASK; 3134 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; 3135 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; 3136 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; 3137 3138 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); 3139 } 3140 3141 static void chv_crtc_clock_get(struct intel_crtc *crtc, 3142 struct intel_crtc_state *pipe_config) 3143 { 3144 struct drm_device *dev = crtc->base.dev; 3145 struct drm_i915_private *dev_priv = to_i915(dev); 3146 enum pipe pipe = crtc->pipe; 3147 enum dpio_channel port = vlv_pipe_to_channel(pipe); 3148 struct dpll clock; 3149 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; 3150 int refclk = 100000; 3151 3152 /* In case of DSI, DPLL will not be used */ 3153 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 3154 return; 3155 3156 vlv_dpio_get(dev_priv); 3157 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); 3158 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); 3159 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); 3160 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); 3161 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); 3162 vlv_dpio_put(dev_priv); 3163 3164 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; 3165 clock.m2 = (pll_dw0 & 0xff) << 22; 3166 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) 3167 clock.m2 |= pll_dw2 & 0x3fffff; 3168 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; 3169 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; 3170 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; 3171 3172 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); 3173 } 3174 3175 static enum intel_output_format 3176 bdw_get_pipemisc_output_format(struct intel_crtc *crtc) 3177 { 3178 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3179 u32 tmp; 3180 3181 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); 3182 3183 if (tmp & PIPEMISC_YUV420_ENABLE) { 3184 /* We support 4:2:0 in full blend mode only */ 3185 drm_WARN_ON(&dev_priv->drm, 3186 (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0); 3187 3188 return INTEL_OUTPUT_FORMAT_YCBCR420; 3189 } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) { 3190 return INTEL_OUTPUT_FORMAT_YCBCR444; 3191 } else { 3192 return INTEL_OUTPUT_FORMAT_RGB; 3193 } 3194 } 3195 3196 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state) 3197 { 3198 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3199 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 3200 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3201 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 3202 u32 tmp; 3203 3204 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); 3205 3206 if (tmp & DISP_PIPE_GAMMA_ENABLE) 3207 crtc_state->gamma_enable = true; 3208 3209 if (!HAS_GMCH(dev_priv) && 3210 tmp & DISP_PIPE_CSC_ENABLE) 3211 crtc_state->csc_enable = true; 3212 } 3213 3214 static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 3215 struct intel_crtc_state *pipe_config) 3216 { 3217 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3218 enum intel_display_power_domain power_domain; 3219 intel_wakeref_t wakeref; 3220 u32 tmp; 3221 bool ret; 3222 3223 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3224 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3225 if (!wakeref) 3226 return false; 3227 3228 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3229 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3230 pipe_config->shared_dpll = NULL; 3231 3232 ret = false; 3233 3234 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); 3235 if (!(tmp & PIPECONF_ENABLE)) 3236 goto out; 3237 3238 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 3239 IS_CHERRYVIEW(dev_priv)) { 3240 switch (tmp & PIPECONF_BPC_MASK) { 3241 case PIPECONF_BPC_6: 3242 pipe_config->pipe_bpp = 18; 3243 break; 3244 case PIPECONF_BPC_8: 3245 pipe_config->pipe_bpp = 24; 3246 break; 3247 case PIPECONF_BPC_10: 3248 pipe_config->pipe_bpp = 30; 3249 break; 3250 default: 3251 MISSING_CASE(tmp); 3252 break; 3253 } 3254 } 3255 3256 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 3257 (tmp & PIPECONF_COLOR_RANGE_SELECT)) 3258 pipe_config->limited_color_range = true; 3259 3260 pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_I9XX, tmp); 3261 3262 pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1; 3263 3264 if (IS_CHERRYVIEW(dev_priv)) 3265 pipe_config->cgm_mode = intel_de_read(dev_priv, 3266 CGM_PIPE_MODE(crtc->pipe)); 3267 3268 i9xx_get_pipe_color_config(pipe_config); 3269 intel_color_get_config(pipe_config); 3270 3271 if (DISPLAY_VER(dev_priv) < 4) 3272 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; 3273 3274 intel_get_transcoder_timings(crtc, pipe_config); 3275 intel_get_pipe_src_size(crtc, pipe_config); 3276 3277 i9xx_get_pfit_config(pipe_config); 3278 3279 if (DISPLAY_VER(dev_priv) >= 4) { 3280 /* No way to read it out on pipes B and C */ 3281 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) 3282 tmp = dev_priv->chv_dpll_md[crtc->pipe]; 3283 else 3284 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe)); 3285 pipe_config->pixel_multiplier = 3286 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) 3287 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; 3288 pipe_config->dpll_hw_state.dpll_md = tmp; 3289 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 3290 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 3291 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe)); 3292 pipe_config->pixel_multiplier = 3293 ((tmp & SDVO_MULTIPLIER_MASK) 3294 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; 3295 } else { 3296 /* Note that on i915G/GM the pixel multiplier is in the sdvo 3297 * port and will be fixed up in the encoder->get_config 3298 * function. */ 3299 pipe_config->pixel_multiplier = 1; 3300 } 3301 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv, 3302 DPLL(crtc->pipe)); 3303 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 3304 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv, 3305 FP0(crtc->pipe)); 3306 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv, 3307 FP1(crtc->pipe)); 3308 } else { 3309 /* Mask out read-only status bits. */ 3310 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | 3311 DPLL_PORTC_READY_MASK | 3312 DPLL_PORTB_READY_MASK); 3313 } 3314 3315 if (IS_CHERRYVIEW(dev_priv)) 3316 chv_crtc_clock_get(crtc, pipe_config); 3317 else if (IS_VALLEYVIEW(dev_priv)) 3318 vlv_crtc_clock_get(crtc, pipe_config); 3319 else 3320 i9xx_crtc_clock_get(crtc, pipe_config); 3321 3322 /* 3323 * Normally the dotclock is filled in by the encoder .get_config() 3324 * but in case the pipe is enabled w/o any ports we need a sane 3325 * default. 3326 */ 3327 pipe_config->hw.adjusted_mode.crtc_clock = 3328 pipe_config->port_clock / pipe_config->pixel_multiplier; 3329 3330 ret = true; 3331 3332 out: 3333 intel_display_power_put(dev_priv, power_domain, wakeref); 3334 3335 return ret; 3336 } 3337 3338 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) 3339 { 3340 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3341 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3342 enum pipe pipe = crtc->pipe; 3343 u32 val; 3344 3345 val = 0; 3346 3347 switch (crtc_state->pipe_bpp) { 3348 default: 3349 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3350 MISSING_CASE(crtc_state->pipe_bpp); 3351 fallthrough; 3352 case 18: 3353 val |= PIPECONF_BPC_6; 3354 break; 3355 case 24: 3356 val |= PIPECONF_BPC_8; 3357 break; 3358 case 30: 3359 val |= PIPECONF_BPC_10; 3360 break; 3361 case 36: 3362 val |= PIPECONF_BPC_12; 3363 break; 3364 } 3365 3366 if (crtc_state->dither) 3367 val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP; 3368 3369 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3370 val |= PIPECONF_INTERLACE_IF_ID_ILK; 3371 else 3372 val |= PIPECONF_INTERLACE_PF_PD_ILK; 3373 3374 /* 3375 * This would end up with an odd purple hue over 3376 * the entire display. Make sure we don't do it. 3377 */ 3378 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 3379 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 3380 3381 if (crtc_state->limited_color_range && 3382 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3383 val |= PIPECONF_COLOR_RANGE_SELECT; 3384 3385 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3386 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709; 3387 3388 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); 3389 3390 val |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3391 val |= PIPECONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay); 3392 3393 intel_de_write(dev_priv, PIPECONF(pipe), val); 3394 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 3395 } 3396 3397 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) 3398 { 3399 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3400 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3401 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3402 u32 val = 0; 3403 3404 if (IS_HASWELL(dev_priv) && crtc_state->dither) 3405 val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP; 3406 3407 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3408 val |= PIPECONF_INTERLACE_IF_ID_ILK; 3409 else 3410 val |= PIPECONF_INTERLACE_PF_PD_ILK; 3411 3412 if (IS_HASWELL(dev_priv) && 3413 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3414 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW; 3415 3416 intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val); 3417 intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder)); 3418 } 3419 3420 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) 3421 { 3422 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3423 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3424 u32 val = 0; 3425 3426 switch (crtc_state->pipe_bpp) { 3427 case 18: 3428 val |= PIPEMISC_BPC_6; 3429 break; 3430 case 24: 3431 val |= PIPEMISC_BPC_8; 3432 break; 3433 case 30: 3434 val |= PIPEMISC_BPC_10; 3435 break; 3436 case 36: 3437 /* Port output 12BPC defined for ADLP+ */ 3438 if (DISPLAY_VER(dev_priv) > 12) 3439 val |= PIPEMISC_BPC_12_ADLP; 3440 break; 3441 default: 3442 MISSING_CASE(crtc_state->pipe_bpp); 3443 break; 3444 } 3445 3446 if (crtc_state->dither) 3447 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; 3448 3449 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 3450 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 3451 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV; 3452 3453 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 3454 val |= PIPEMISC_YUV420_ENABLE | 3455 PIPEMISC_YUV420_MODE_FULL_BLEND; 3456 3457 if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state)) 3458 val |= PIPEMISC_HDR_MODE_PRECISION; 3459 3460 if (DISPLAY_VER(dev_priv) >= 12) 3461 val |= PIPEMISC_PIXEL_ROUNDING_TRUNC; 3462 3463 intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val); 3464 } 3465 3466 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) 3467 { 3468 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3469 u32 tmp; 3470 3471 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); 3472 3473 switch (tmp & PIPEMISC_BPC_MASK) { 3474 case PIPEMISC_BPC_6: 3475 return 18; 3476 case PIPEMISC_BPC_8: 3477 return 24; 3478 case PIPEMISC_BPC_10: 3479 return 30; 3480 /* 3481 * PORT OUTPUT 12 BPC defined for ADLP+. 3482 * 3483 * TODO: 3484 * For previous platforms with DSI interface, bits 5:7 3485 * are used for storing pipe_bpp irrespective of dithering. 3486 * Since the value of 12 BPC is not defined for these bits 3487 * on older platforms, need to find a workaround for 12 BPC 3488 * MIPI DSI HW readout. 3489 */ 3490 case PIPEMISC_BPC_12_ADLP: 3491 if (DISPLAY_VER(dev_priv) > 12) 3492 return 36; 3493 fallthrough; 3494 default: 3495 MISSING_CASE(tmp); 3496 return 0; 3497 } 3498 } 3499 3500 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) 3501 { 3502 /* 3503 * Account for spread spectrum to avoid 3504 * oversubscribing the link. Max center spread 3505 * is 2.5%; use 5% for safety's sake. 3506 */ 3507 u32 bps = target_clock * bpp * 21 / 20; 3508 return DIV_ROUND_UP(bps, link_bw * 8); 3509 } 3510 3511 void intel_get_m_n(struct drm_i915_private *i915, 3512 struct intel_link_m_n *m_n, 3513 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 3514 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 3515 { 3516 m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK; 3517 m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK; 3518 m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK; 3519 m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK; 3520 m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1; 3521 } 3522 3523 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, 3524 enum transcoder transcoder, 3525 struct intel_link_m_n *m_n) 3526 { 3527 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3528 enum pipe pipe = crtc->pipe; 3529 3530 if (DISPLAY_VER(dev_priv) >= 5) 3531 intel_get_m_n(dev_priv, m_n, 3532 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 3533 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 3534 else 3535 intel_get_m_n(dev_priv, m_n, 3536 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 3537 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 3538 } 3539 3540 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, 3541 enum transcoder transcoder, 3542 struct intel_link_m_n *m_n) 3543 { 3544 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3545 3546 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 3547 return; 3548 3549 intel_get_m_n(dev_priv, m_n, 3550 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 3551 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 3552 } 3553 3554 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state, 3555 u32 pos, u32 size) 3556 { 3557 drm_rect_init(&crtc_state->pch_pfit.dst, 3558 pos >> 16, pos & 0xffff, 3559 size >> 16, size & 0xffff); 3560 } 3561 3562 static void skl_get_pfit_config(struct intel_crtc_state *crtc_state) 3563 { 3564 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3565 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3566 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; 3567 int id = -1; 3568 int i; 3569 3570 /* find scaler attached to this pipe */ 3571 for (i = 0; i < crtc->num_scalers; i++) { 3572 u32 ctl, pos, size; 3573 3574 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i)); 3575 if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN) 3576 continue; 3577 3578 id = i; 3579 crtc_state->pch_pfit.enabled = true; 3580 3581 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i)); 3582 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i)); 3583 3584 ilk_get_pfit_pos_size(crtc_state, pos, size); 3585 3586 scaler_state->scalers[i].in_use = true; 3587 break; 3588 } 3589 3590 scaler_state->scaler_id = id; 3591 if (id >= 0) 3592 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); 3593 else 3594 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); 3595 } 3596 3597 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state) 3598 { 3599 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3600 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3601 u32 ctl, pos, size; 3602 3603 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe)); 3604 if ((ctl & PF_ENABLE) == 0) 3605 return; 3606 3607 crtc_state->pch_pfit.enabled = true; 3608 3609 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe)); 3610 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe)); 3611 3612 ilk_get_pfit_pos_size(crtc_state, pos, size); 3613 3614 /* 3615 * We currently do not free assignements of panel fitters on 3616 * ivb/hsw (since we don't use the higher upscaling modes which 3617 * differentiates them) so just WARN about this case for now. 3618 */ 3619 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 7 && 3620 (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe)); 3621 } 3622 3623 static bool ilk_get_pipe_config(struct intel_crtc *crtc, 3624 struct intel_crtc_state *pipe_config) 3625 { 3626 struct drm_device *dev = crtc->base.dev; 3627 struct drm_i915_private *dev_priv = to_i915(dev); 3628 enum intel_display_power_domain power_domain; 3629 intel_wakeref_t wakeref; 3630 u32 tmp; 3631 bool ret; 3632 3633 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3634 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3635 if (!wakeref) 3636 return false; 3637 3638 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3639 pipe_config->shared_dpll = NULL; 3640 3641 ret = false; 3642 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); 3643 if (!(tmp & PIPECONF_ENABLE)) 3644 goto out; 3645 3646 switch (tmp & PIPECONF_BPC_MASK) { 3647 case PIPECONF_BPC_6: 3648 pipe_config->pipe_bpp = 18; 3649 break; 3650 case PIPECONF_BPC_8: 3651 pipe_config->pipe_bpp = 24; 3652 break; 3653 case PIPECONF_BPC_10: 3654 pipe_config->pipe_bpp = 30; 3655 break; 3656 case PIPECONF_BPC_12: 3657 pipe_config->pipe_bpp = 36; 3658 break; 3659 default: 3660 break; 3661 } 3662 3663 if (tmp & PIPECONF_COLOR_RANGE_SELECT) 3664 pipe_config->limited_color_range = true; 3665 3666 switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) { 3667 case PIPECONF_OUTPUT_COLORSPACE_YUV601: 3668 case PIPECONF_OUTPUT_COLORSPACE_YUV709: 3669 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3670 break; 3671 default: 3672 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3673 break; 3674 } 3675 3676 pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_ILK, tmp); 3677 3678 pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1; 3679 3680 pipe_config->msa_timing_delay = REG_FIELD_GET(PIPECONF_MSA_TIMING_DELAY_MASK, tmp); 3681 3682 pipe_config->csc_mode = intel_de_read(dev_priv, 3683 PIPE_CSC_MODE(crtc->pipe)); 3684 3685 i9xx_get_pipe_color_config(pipe_config); 3686 intel_color_get_config(pipe_config); 3687 3688 pipe_config->pixel_multiplier = 1; 3689 3690 ilk_pch_get_config(pipe_config); 3691 3692 intel_get_transcoder_timings(crtc, pipe_config); 3693 intel_get_pipe_src_size(crtc, pipe_config); 3694 3695 ilk_get_pfit_config(pipe_config); 3696 3697 ret = true; 3698 3699 out: 3700 intel_display_power_put(dev_priv, power_domain, wakeref); 3701 3702 return ret; 3703 } 3704 3705 static u8 bigjoiner_pipes(struct drm_i915_private *i915) 3706 { 3707 if (DISPLAY_VER(i915) >= 12) 3708 return BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D); 3709 else if (DISPLAY_VER(i915) >= 11) 3710 return BIT(PIPE_B) | BIT(PIPE_C); 3711 else 3712 return 0; 3713 } 3714 3715 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv, 3716 enum transcoder cpu_transcoder) 3717 { 3718 enum intel_display_power_domain power_domain; 3719 intel_wakeref_t wakeref; 3720 u32 tmp = 0; 3721 3722 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3723 3724 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3725 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3726 3727 return tmp & TRANS_DDI_FUNC_ENABLE; 3728 } 3729 3730 static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv, 3731 u8 *master_pipes, u8 *slave_pipes) 3732 { 3733 struct intel_crtc *crtc; 3734 3735 *master_pipes = 0; 3736 *slave_pipes = 0; 3737 3738 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, 3739 bigjoiner_pipes(dev_priv)) { 3740 enum intel_display_power_domain power_domain; 3741 enum pipe pipe = crtc->pipe; 3742 intel_wakeref_t wakeref; 3743 3744 power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe); 3745 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3746 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3747 3748 if (!(tmp & BIG_JOINER_ENABLE)) 3749 continue; 3750 3751 if (tmp & MASTER_BIG_JOINER_ENABLE) 3752 *master_pipes |= BIT(pipe); 3753 else 3754 *slave_pipes |= BIT(pipe); 3755 } 3756 3757 if (DISPLAY_VER(dev_priv) < 13) 3758 continue; 3759 3760 power_domain = POWER_DOMAIN_PIPE(pipe); 3761 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3762 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3763 3764 if (tmp & UNCOMPRESSED_JOINER_MASTER) 3765 *master_pipes |= BIT(pipe); 3766 if (tmp & UNCOMPRESSED_JOINER_SLAVE) 3767 *slave_pipes |= BIT(pipe); 3768 } 3769 } 3770 3771 /* Bigjoiner pipes should always be consecutive master and slave */ 3772 drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1, 3773 "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n", 3774 *master_pipes, *slave_pipes); 3775 } 3776 3777 static enum pipe get_bigjoiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3778 { 3779 if ((slave_pipes & BIT(pipe)) == 0) 3780 return pipe; 3781 3782 /* ignore everything above our pipe */ 3783 master_pipes &= ~GENMASK(7, pipe); 3784 3785 /* highest remaining bit should be our master pipe */ 3786 return fls(master_pipes) - 1; 3787 } 3788 3789 static u8 get_bigjoiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3790 { 3791 enum pipe master_pipe, next_master_pipe; 3792 3793 master_pipe = get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes); 3794 3795 if ((master_pipes & BIT(master_pipe)) == 0) 3796 return 0; 3797 3798 /* ignore our master pipe and everything below it */ 3799 master_pipes &= ~GENMASK(master_pipe, 0); 3800 /* make sure a high bit is set for the ffs() */ 3801 master_pipes |= BIT(7); 3802 /* lowest remaining bit should be the next master pipe */ 3803 next_master_pipe = ffs(master_pipes) - 1; 3804 3805 return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe); 3806 } 3807 3808 static u8 hsw_panel_transcoders(struct drm_i915_private *i915) 3809 { 3810 u8 panel_transcoder_mask = BIT(TRANSCODER_EDP); 3811 3812 if (DISPLAY_VER(i915) >= 11) 3813 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); 3814 3815 return panel_transcoder_mask; 3816 } 3817 3818 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) 3819 { 3820 struct drm_device *dev = crtc->base.dev; 3821 struct drm_i915_private *dev_priv = to_i915(dev); 3822 u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv); 3823 enum transcoder cpu_transcoder; 3824 u8 master_pipes, slave_pipes; 3825 u8 enabled_transcoders = 0; 3826 3827 /* 3828 * XXX: Do intel_display_power_get_if_enabled before reading this (for 3829 * consistency and less surprising code; it's in always on power). 3830 */ 3831 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, 3832 panel_transcoder_mask) { 3833 enum intel_display_power_domain power_domain; 3834 intel_wakeref_t wakeref; 3835 enum pipe trans_pipe; 3836 u32 tmp = 0; 3837 3838 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3839 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3840 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3841 3842 if (!(tmp & TRANS_DDI_FUNC_ENABLE)) 3843 continue; 3844 3845 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 3846 default: 3847 drm_WARN(dev, 1, 3848 "unknown pipe linked to transcoder %s\n", 3849 transcoder_name(cpu_transcoder)); 3850 fallthrough; 3851 case TRANS_DDI_EDP_INPUT_A_ONOFF: 3852 case TRANS_DDI_EDP_INPUT_A_ON: 3853 trans_pipe = PIPE_A; 3854 break; 3855 case TRANS_DDI_EDP_INPUT_B_ONOFF: 3856 trans_pipe = PIPE_B; 3857 break; 3858 case TRANS_DDI_EDP_INPUT_C_ONOFF: 3859 trans_pipe = PIPE_C; 3860 break; 3861 case TRANS_DDI_EDP_INPUT_D_ONOFF: 3862 trans_pipe = PIPE_D; 3863 break; 3864 } 3865 3866 if (trans_pipe == crtc->pipe) 3867 enabled_transcoders |= BIT(cpu_transcoder); 3868 } 3869 3870 /* single pipe or bigjoiner master */ 3871 cpu_transcoder = (enum transcoder) crtc->pipe; 3872 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 3873 enabled_transcoders |= BIT(cpu_transcoder); 3874 3875 /* bigjoiner slave -> consider the master pipe's transcoder as well */ 3876 enabled_bigjoiner_pipes(dev_priv, &master_pipes, &slave_pipes); 3877 if (slave_pipes & BIT(crtc->pipe)) { 3878 cpu_transcoder = (enum transcoder) 3879 get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes); 3880 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 3881 enabled_transcoders |= BIT(cpu_transcoder); 3882 } 3883 3884 return enabled_transcoders; 3885 } 3886 3887 static bool has_edp_transcoders(u8 enabled_transcoders) 3888 { 3889 return enabled_transcoders & BIT(TRANSCODER_EDP); 3890 } 3891 3892 static bool has_dsi_transcoders(u8 enabled_transcoders) 3893 { 3894 return enabled_transcoders & (BIT(TRANSCODER_DSI_0) | 3895 BIT(TRANSCODER_DSI_1)); 3896 } 3897 3898 static bool has_pipe_transcoders(u8 enabled_transcoders) 3899 { 3900 return enabled_transcoders & ~(BIT(TRANSCODER_EDP) | 3901 BIT(TRANSCODER_DSI_0) | 3902 BIT(TRANSCODER_DSI_1)); 3903 } 3904 3905 static void assert_enabled_transcoders(struct drm_i915_private *i915, 3906 u8 enabled_transcoders) 3907 { 3908 /* Only one type of transcoder please */ 3909 drm_WARN_ON(&i915->drm, 3910 has_edp_transcoders(enabled_transcoders) + 3911 has_dsi_transcoders(enabled_transcoders) + 3912 has_pipe_transcoders(enabled_transcoders) > 1); 3913 3914 /* Only DSI transcoders can be ganged */ 3915 drm_WARN_ON(&i915->drm, 3916 !has_dsi_transcoders(enabled_transcoders) && 3917 !is_power_of_2(enabled_transcoders)); 3918 } 3919 3920 static bool hsw_get_transcoder_state(struct intel_crtc *crtc, 3921 struct intel_crtc_state *pipe_config, 3922 struct intel_display_power_domain_set *power_domain_set) 3923 { 3924 struct drm_device *dev = crtc->base.dev; 3925 struct drm_i915_private *dev_priv = to_i915(dev); 3926 unsigned long enabled_transcoders; 3927 u32 tmp; 3928 3929 enabled_transcoders = hsw_enabled_transcoders(crtc); 3930 if (!enabled_transcoders) 3931 return false; 3932 3933 assert_enabled_transcoders(dev_priv, enabled_transcoders); 3934 3935 /* 3936 * With the exception of DSI we should only ever have 3937 * a single enabled transcoder. With DSI let's just 3938 * pick the first one. 3939 */ 3940 pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1; 3941 3942 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 3943 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) 3944 return false; 3945 3946 if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) { 3947 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); 3948 3949 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF) 3950 pipe_config->pch_pfit.force_thru = true; 3951 } 3952 3953 tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder)); 3954 3955 return tmp & PIPECONF_ENABLE; 3956 } 3957 3958 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, 3959 struct intel_crtc_state *pipe_config, 3960 struct intel_display_power_domain_set *power_domain_set) 3961 { 3962 struct drm_device *dev = crtc->base.dev; 3963 struct drm_i915_private *dev_priv = to_i915(dev); 3964 enum transcoder cpu_transcoder; 3965 enum port port; 3966 u32 tmp; 3967 3968 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { 3969 if (port == PORT_A) 3970 cpu_transcoder = TRANSCODER_DSI_A; 3971 else 3972 cpu_transcoder = TRANSCODER_DSI_C; 3973 3974 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 3975 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) 3976 continue; 3977 3978 /* 3979 * The PLL needs to be enabled with a valid divider 3980 * configuration, otherwise accessing DSI registers will hang 3981 * the machine. See BSpec North Display Engine 3982 * registers/MIPI[BXT]. We can break out here early, since we 3983 * need the same DSI PLL to be enabled for both DSI ports. 3984 */ 3985 if (!bxt_dsi_pll_is_enabled(dev_priv)) 3986 break; 3987 3988 /* XXX: this works for video mode only */ 3989 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); 3990 if (!(tmp & DPI_ENABLE)) 3991 continue; 3992 3993 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 3994 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) 3995 continue; 3996 3997 pipe_config->cpu_transcoder = cpu_transcoder; 3998 break; 3999 } 4000 4001 return transcoder_is_dsi(pipe_config->cpu_transcoder); 4002 } 4003 4004 static void intel_bigjoiner_get_config(struct intel_crtc_state *crtc_state) 4005 { 4006 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4007 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4008 u8 master_pipes, slave_pipes; 4009 enum pipe pipe = crtc->pipe; 4010 4011 enabled_bigjoiner_pipes(i915, &master_pipes, &slave_pipes); 4012 4013 if (((master_pipes | slave_pipes) & BIT(pipe)) == 0) 4014 return; 4015 4016 crtc_state->bigjoiner_pipes = 4017 BIT(get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes)) | 4018 get_bigjoiner_slave_pipes(pipe, master_pipes, slave_pipes); 4019 } 4020 4021 static bool hsw_get_pipe_config(struct intel_crtc *crtc, 4022 struct intel_crtc_state *pipe_config) 4023 { 4024 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4025 struct intel_display_power_domain_set power_domain_set = { }; 4026 bool active; 4027 u32 tmp; 4028 4029 if (!intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set, 4030 POWER_DOMAIN_PIPE(crtc->pipe))) 4031 return false; 4032 4033 pipe_config->shared_dpll = NULL; 4034 4035 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_set); 4036 4037 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 4038 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_set)) { 4039 drm_WARN_ON(&dev_priv->drm, active); 4040 active = true; 4041 } 4042 4043 if (!active) 4044 goto out; 4045 4046 intel_dsc_get_config(pipe_config); 4047 intel_bigjoiner_get_config(pipe_config); 4048 4049 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || 4050 DISPLAY_VER(dev_priv) >= 11) 4051 intel_get_transcoder_timings(crtc, pipe_config); 4052 4053 if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder)) 4054 intel_vrr_get_config(crtc, pipe_config); 4055 4056 intel_get_pipe_src_size(crtc, pipe_config); 4057 4058 if (IS_HASWELL(dev_priv)) { 4059 u32 tmp = intel_de_read(dev_priv, 4060 PIPECONF(pipe_config->cpu_transcoder)); 4061 4062 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW) 4063 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 4064 else 4065 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 4066 } else { 4067 pipe_config->output_format = 4068 bdw_get_pipemisc_output_format(crtc); 4069 } 4070 4071 pipe_config->gamma_mode = intel_de_read(dev_priv, 4072 GAMMA_MODE(crtc->pipe)); 4073 4074 pipe_config->csc_mode = intel_de_read(dev_priv, 4075 PIPE_CSC_MODE(crtc->pipe)); 4076 4077 if (DISPLAY_VER(dev_priv) >= 9) { 4078 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe)); 4079 4080 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE) 4081 pipe_config->gamma_enable = true; 4082 4083 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE) 4084 pipe_config->csc_enable = true; 4085 } else { 4086 i9xx_get_pipe_color_config(pipe_config); 4087 } 4088 4089 intel_color_get_config(pipe_config); 4090 4091 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe)); 4092 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); 4093 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 4094 pipe_config->ips_linetime = 4095 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); 4096 4097 if (intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set, 4098 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) { 4099 if (DISPLAY_VER(dev_priv) >= 9) 4100 skl_get_pfit_config(pipe_config); 4101 else 4102 ilk_get_pfit_config(pipe_config); 4103 } 4104 4105 hsw_ips_get_config(pipe_config); 4106 4107 if (pipe_config->cpu_transcoder != TRANSCODER_EDP && 4108 !transcoder_is_dsi(pipe_config->cpu_transcoder)) { 4109 pipe_config->pixel_multiplier = 4110 intel_de_read(dev_priv, 4111 PIPE_MULT(pipe_config->cpu_transcoder)) + 1; 4112 } else { 4113 pipe_config->pixel_multiplier = 1; 4114 } 4115 4116 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { 4117 tmp = intel_de_read(dev_priv, CHICKEN_TRANS(pipe_config->cpu_transcoder)); 4118 4119 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1; 4120 } else { 4121 /* no idea if this is correct */ 4122 pipe_config->framestart_delay = 1; 4123 } 4124 4125 out: 4126 intel_display_power_put_all_in_set(dev_priv, &power_domain_set); 4127 4128 return active; 4129 } 4130 4131 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state) 4132 { 4133 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4134 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4135 4136 if (!i915->display->get_pipe_config(crtc, crtc_state)) 4137 return false; 4138 4139 crtc_state->hw.active = true; 4140 4141 intel_crtc_readout_derived_state(crtc_state); 4142 4143 return true; 4144 } 4145 4146 /* VESA 640x480x72Hz mode to set on the pipe */ 4147 static const struct drm_display_mode load_detect_mode = { 4148 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, 4149 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 4150 }; 4151 4152 static int intel_modeset_disable_planes(struct drm_atomic_state *state, 4153 struct drm_crtc *crtc) 4154 { 4155 struct drm_plane *plane; 4156 struct drm_plane_state *plane_state; 4157 int ret, i; 4158 4159 ret = drm_atomic_add_affected_planes(state, crtc); 4160 if (ret) 4161 return ret; 4162 4163 for_each_new_plane_in_state(state, plane, plane_state, i) { 4164 if (plane_state->crtc != crtc) 4165 continue; 4166 4167 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL); 4168 if (ret) 4169 return ret; 4170 4171 drm_atomic_set_fb_for_plane(plane_state, NULL); 4172 } 4173 4174 return 0; 4175 } 4176 4177 int intel_get_load_detect_pipe(struct drm_connector *connector, 4178 struct intel_load_detect_pipe *old, 4179 struct drm_modeset_acquire_ctx *ctx) 4180 { 4181 struct intel_encoder *encoder = 4182 intel_attached_encoder(to_intel_connector(connector)); 4183 struct intel_crtc *possible_crtc; 4184 struct intel_crtc *crtc = NULL; 4185 struct drm_device *dev = encoder->base.dev; 4186 struct drm_i915_private *dev_priv = to_i915(dev); 4187 struct drm_mode_config *config = &dev->mode_config; 4188 struct drm_atomic_state *state = NULL, *restore_state = NULL; 4189 struct drm_connector_state *connector_state; 4190 struct intel_crtc_state *crtc_state; 4191 int ret; 4192 4193 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 4194 connector->base.id, connector->name, 4195 encoder->base.base.id, encoder->base.name); 4196 4197 old->restore_state = NULL; 4198 4199 drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex)); 4200 4201 /* 4202 * Algorithm gets a little messy: 4203 * 4204 * - if the connector already has an assigned crtc, use it (but make 4205 * sure it's on first) 4206 * 4207 * - try to find the first unused crtc that can drive this connector, 4208 * and use that if we find one 4209 */ 4210 4211 /* See if we already have a CRTC for this connector */ 4212 if (connector->state->crtc) { 4213 crtc = to_intel_crtc(connector->state->crtc); 4214 4215 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4216 if (ret) 4217 goto fail; 4218 4219 /* Make sure the crtc and connector are running */ 4220 goto found; 4221 } 4222 4223 /* Find an unused one (if possible) */ 4224 for_each_intel_crtc(dev, possible_crtc) { 4225 if (!(encoder->base.possible_crtcs & 4226 drm_crtc_mask(&possible_crtc->base))) 4227 continue; 4228 4229 ret = drm_modeset_lock(&possible_crtc->base.mutex, ctx); 4230 if (ret) 4231 goto fail; 4232 4233 if (possible_crtc->base.state->enable) { 4234 drm_modeset_unlock(&possible_crtc->base.mutex); 4235 continue; 4236 } 4237 4238 crtc = possible_crtc; 4239 break; 4240 } 4241 4242 /* 4243 * If we didn't find an unused CRTC, don't use any. 4244 */ 4245 if (!crtc) { 4246 drm_dbg_kms(&dev_priv->drm, 4247 "no pipe available for load-detect\n"); 4248 ret = -ENODEV; 4249 goto fail; 4250 } 4251 4252 found: 4253 state = drm_atomic_state_alloc(dev); 4254 restore_state = drm_atomic_state_alloc(dev); 4255 if (!state || !restore_state) { 4256 ret = -ENOMEM; 4257 goto fail; 4258 } 4259 4260 state->acquire_ctx = ctx; 4261 restore_state->acquire_ctx = ctx; 4262 4263 connector_state = drm_atomic_get_connector_state(state, connector); 4264 if (IS_ERR(connector_state)) { 4265 ret = PTR_ERR(connector_state); 4266 goto fail; 4267 } 4268 4269 ret = drm_atomic_set_crtc_for_connector(connector_state, &crtc->base); 4270 if (ret) 4271 goto fail; 4272 4273 crtc_state = intel_atomic_get_crtc_state(state, crtc); 4274 if (IS_ERR(crtc_state)) { 4275 ret = PTR_ERR(crtc_state); 4276 goto fail; 4277 } 4278 4279 crtc_state->uapi.active = true; 4280 4281 ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi, 4282 &load_detect_mode); 4283 if (ret) 4284 goto fail; 4285 4286 ret = intel_modeset_disable_planes(state, &crtc->base); 4287 if (ret) 4288 goto fail; 4289 4290 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); 4291 if (!ret) 4292 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, &crtc->base)); 4293 if (!ret) 4294 ret = drm_atomic_add_affected_planes(restore_state, &crtc->base); 4295 if (ret) { 4296 drm_dbg_kms(&dev_priv->drm, 4297 "Failed to create a copy of old state to restore: %i\n", 4298 ret); 4299 goto fail; 4300 } 4301 4302 ret = drm_atomic_commit(state); 4303 if (ret) { 4304 drm_dbg_kms(&dev_priv->drm, 4305 "failed to set mode on load-detect pipe\n"); 4306 goto fail; 4307 } 4308 4309 old->restore_state = restore_state; 4310 drm_atomic_state_put(state); 4311 4312 /* let the connector get through one full cycle before testing */ 4313 intel_crtc_wait_for_next_vblank(crtc); 4314 4315 return true; 4316 4317 fail: 4318 if (state) { 4319 drm_atomic_state_put(state); 4320 state = NULL; 4321 } 4322 if (restore_state) { 4323 drm_atomic_state_put(restore_state); 4324 restore_state = NULL; 4325 } 4326 4327 if (ret == -EDEADLK) 4328 return ret; 4329 4330 return false; 4331 } 4332 4333 void intel_release_load_detect_pipe(struct drm_connector *connector, 4334 struct intel_load_detect_pipe *old, 4335 struct drm_modeset_acquire_ctx *ctx) 4336 { 4337 struct intel_encoder *intel_encoder = 4338 intel_attached_encoder(to_intel_connector(connector)); 4339 struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev); 4340 struct drm_encoder *encoder = &intel_encoder->base; 4341 struct drm_atomic_state *state = old->restore_state; 4342 int ret; 4343 4344 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 4345 connector->base.id, connector->name, 4346 encoder->base.id, encoder->name); 4347 4348 if (!state) 4349 return; 4350 4351 ret = drm_atomic_helper_commit_duplicated_state(state, ctx); 4352 if (ret) 4353 drm_dbg_kms(&i915->drm, 4354 "Couldn't release load detect pipe: %i\n", ret); 4355 drm_atomic_state_put(state); 4356 } 4357 4358 static int i9xx_pll_refclk(struct drm_device *dev, 4359 const struct intel_crtc_state *pipe_config) 4360 { 4361 struct drm_i915_private *dev_priv = to_i915(dev); 4362 u32 dpll = pipe_config->dpll_hw_state.dpll; 4363 4364 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) 4365 return dev_priv->vbt.lvds_ssc_freq; 4366 else if (HAS_PCH_SPLIT(dev_priv)) 4367 return 120000; 4368 else if (DISPLAY_VER(dev_priv) != 2) 4369 return 96000; 4370 else 4371 return 48000; 4372 } 4373 4374 /* Returns the clock of the currently programmed mode of the given pipe. */ 4375 void i9xx_crtc_clock_get(struct intel_crtc *crtc, 4376 struct intel_crtc_state *pipe_config) 4377 { 4378 struct drm_device *dev = crtc->base.dev; 4379 struct drm_i915_private *dev_priv = to_i915(dev); 4380 u32 dpll = pipe_config->dpll_hw_state.dpll; 4381 u32 fp; 4382 struct dpll clock; 4383 int port_clock; 4384 int refclk = i9xx_pll_refclk(dev, pipe_config); 4385 4386 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 4387 fp = pipe_config->dpll_hw_state.fp0; 4388 else 4389 fp = pipe_config->dpll_hw_state.fp1; 4390 4391 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 4392 if (IS_PINEVIEW(dev_priv)) { 4393 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; 4394 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; 4395 } else { 4396 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 4397 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 4398 } 4399 4400 if (DISPLAY_VER(dev_priv) != 2) { 4401 if (IS_PINEVIEW(dev_priv)) 4402 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> 4403 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); 4404 else 4405 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> 4406 DPLL_FPA01_P1_POST_DIV_SHIFT); 4407 4408 switch (dpll & DPLL_MODE_MASK) { 4409 case DPLLB_MODE_DAC_SERIAL: 4410 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 4411 5 : 10; 4412 break; 4413 case DPLLB_MODE_LVDS: 4414 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 4415 7 : 14; 4416 break; 4417 default: 4418 drm_dbg_kms(&dev_priv->drm, 4419 "Unknown DPLL mode %08x in programmed " 4420 "mode\n", (int)(dpll & DPLL_MODE_MASK)); 4421 return; 4422 } 4423 4424 if (IS_PINEVIEW(dev_priv)) 4425 port_clock = pnv_calc_dpll_params(refclk, &clock); 4426 else 4427 port_clock = i9xx_calc_dpll_params(refclk, &clock); 4428 } else { 4429 enum pipe lvds_pipe; 4430 4431 if (IS_I85X(dev_priv) && 4432 intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) && 4433 lvds_pipe == crtc->pipe) { 4434 u32 lvds = intel_de_read(dev_priv, LVDS); 4435 4436 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 4437 DPLL_FPA01_P1_POST_DIV_SHIFT); 4438 4439 if (lvds & LVDS_CLKB_POWER_UP) 4440 clock.p2 = 7; 4441 else 4442 clock.p2 = 14; 4443 } else { 4444 if (dpll & PLL_P1_DIVIDE_BY_TWO) 4445 clock.p1 = 2; 4446 else { 4447 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 4448 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 4449 } 4450 if (dpll & PLL_P2_DIVIDE_BY_4) 4451 clock.p2 = 4; 4452 else 4453 clock.p2 = 2; 4454 } 4455 4456 port_clock = i9xx_calc_dpll_params(refclk, &clock); 4457 } 4458 4459 /* 4460 * This value includes pixel_multiplier. We will use 4461 * port_clock to compute adjusted_mode.crtc_clock in the 4462 * encoder's get_config() function. 4463 */ 4464 pipe_config->port_clock = port_clock; 4465 } 4466 4467 int intel_dotclock_calculate(int link_freq, 4468 const struct intel_link_m_n *m_n) 4469 { 4470 /* 4471 * The calculation for the data clock is: 4472 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp 4473 * But we want to avoid losing precison if possible, so: 4474 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) 4475 * 4476 * and the link clock is simpler: 4477 * link_clock = (m * link_clock) / n 4478 */ 4479 4480 if (!m_n->link_n) 4481 return 0; 4482 4483 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n); 4484 } 4485 4486 /* Returns the currently programmed mode of the given encoder. */ 4487 struct drm_display_mode * 4488 intel_encoder_current_mode(struct intel_encoder *encoder) 4489 { 4490 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4491 struct intel_crtc_state *crtc_state; 4492 struct drm_display_mode *mode; 4493 struct intel_crtc *crtc; 4494 enum pipe pipe; 4495 4496 if (!encoder->get_hw_state(encoder, &pipe)) 4497 return NULL; 4498 4499 crtc = intel_crtc_for_pipe(dev_priv, pipe); 4500 4501 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 4502 if (!mode) 4503 return NULL; 4504 4505 crtc_state = intel_crtc_state_alloc(crtc); 4506 if (!crtc_state) { 4507 kfree(mode); 4508 return NULL; 4509 } 4510 4511 if (!intel_crtc_get_pipe_config(crtc_state)) { 4512 kfree(crtc_state); 4513 kfree(mode); 4514 return NULL; 4515 } 4516 4517 intel_encoder_get_config(encoder, crtc_state); 4518 4519 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode); 4520 4521 kfree(crtc_state); 4522 4523 return mode; 4524 } 4525 4526 static bool encoders_cloneable(const struct intel_encoder *a, 4527 const struct intel_encoder *b) 4528 { 4529 /* masks could be asymmetric, so check both ways */ 4530 return a == b || (a->cloneable & (1 << b->type) && 4531 b->cloneable & (1 << a->type)); 4532 } 4533 4534 static bool check_single_encoder_cloning(struct intel_atomic_state *state, 4535 struct intel_crtc *crtc, 4536 struct intel_encoder *encoder) 4537 { 4538 struct intel_encoder *source_encoder; 4539 struct drm_connector *connector; 4540 struct drm_connector_state *connector_state; 4541 int i; 4542 4543 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4544 if (connector_state->crtc != &crtc->base) 4545 continue; 4546 4547 source_encoder = 4548 to_intel_encoder(connector_state->best_encoder); 4549 if (!encoders_cloneable(encoder, source_encoder)) 4550 return false; 4551 } 4552 4553 return true; 4554 } 4555 4556 static int icl_add_linked_planes(struct intel_atomic_state *state) 4557 { 4558 struct intel_plane *plane, *linked; 4559 struct intel_plane_state *plane_state, *linked_plane_state; 4560 int i; 4561 4562 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4563 linked = plane_state->planar_linked_plane; 4564 4565 if (!linked) 4566 continue; 4567 4568 linked_plane_state = intel_atomic_get_plane_state(state, linked); 4569 if (IS_ERR(linked_plane_state)) 4570 return PTR_ERR(linked_plane_state); 4571 4572 drm_WARN_ON(state->base.dev, 4573 linked_plane_state->planar_linked_plane != plane); 4574 drm_WARN_ON(state->base.dev, 4575 linked_plane_state->planar_slave == plane_state->planar_slave); 4576 } 4577 4578 return 0; 4579 } 4580 4581 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state) 4582 { 4583 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4584 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4585 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 4586 struct intel_plane *plane, *linked; 4587 struct intel_plane_state *plane_state; 4588 int i; 4589 4590 if (DISPLAY_VER(dev_priv) < 11) 4591 return 0; 4592 4593 /* 4594 * Destroy all old plane links and make the slave plane invisible 4595 * in the crtc_state->active_planes mask. 4596 */ 4597 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4598 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane) 4599 continue; 4600 4601 plane_state->planar_linked_plane = NULL; 4602 if (plane_state->planar_slave && !plane_state->uapi.visible) { 4603 crtc_state->enabled_planes &= ~BIT(plane->id); 4604 crtc_state->active_planes &= ~BIT(plane->id); 4605 crtc_state->update_planes |= BIT(plane->id); 4606 crtc_state->data_rate[plane->id] = 0; 4607 crtc_state->rel_data_rate[plane->id] = 0; 4608 } 4609 4610 plane_state->planar_slave = false; 4611 } 4612 4613 if (!crtc_state->nv12_planes) 4614 return 0; 4615 4616 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4617 struct intel_plane_state *linked_state = NULL; 4618 4619 if (plane->pipe != crtc->pipe || 4620 !(crtc_state->nv12_planes & BIT(plane->id))) 4621 continue; 4622 4623 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) { 4624 if (!icl_is_nv12_y_plane(dev_priv, linked->id)) 4625 continue; 4626 4627 if (crtc_state->active_planes & BIT(linked->id)) 4628 continue; 4629 4630 linked_state = intel_atomic_get_plane_state(state, linked); 4631 if (IS_ERR(linked_state)) 4632 return PTR_ERR(linked_state); 4633 4634 break; 4635 } 4636 4637 if (!linked_state) { 4638 drm_dbg_kms(&dev_priv->drm, 4639 "Need %d free Y planes for planar YUV\n", 4640 hweight8(crtc_state->nv12_planes)); 4641 4642 return -EINVAL; 4643 } 4644 4645 plane_state->planar_linked_plane = linked; 4646 4647 linked_state->planar_slave = true; 4648 linked_state->planar_linked_plane = plane; 4649 crtc_state->enabled_planes |= BIT(linked->id); 4650 crtc_state->active_planes |= BIT(linked->id); 4651 crtc_state->update_planes |= BIT(linked->id); 4652 crtc_state->data_rate[linked->id] = 4653 crtc_state->data_rate_y[plane->id]; 4654 crtc_state->rel_data_rate[linked->id] = 4655 crtc_state->rel_data_rate_y[plane->id]; 4656 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n", 4657 linked->base.name, plane->base.name); 4658 4659 /* Copy parameters to slave plane */ 4660 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE; 4661 linked_state->color_ctl = plane_state->color_ctl; 4662 linked_state->view = plane_state->view; 4663 linked_state->decrypt = plane_state->decrypt; 4664 4665 intel_plane_copy_hw_state(linked_state, plane_state); 4666 linked_state->uapi.src = plane_state->uapi.src; 4667 linked_state->uapi.dst = plane_state->uapi.dst; 4668 4669 if (icl_is_hdr_plane(dev_priv, plane->id)) { 4670 if (linked->id == PLANE_SPRITE5) 4671 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL; 4672 else if (linked->id == PLANE_SPRITE4) 4673 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL; 4674 else if (linked->id == PLANE_SPRITE3) 4675 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL; 4676 else if (linked->id == PLANE_SPRITE2) 4677 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL; 4678 else 4679 MISSING_CASE(linked->id); 4680 } 4681 } 4682 4683 return 0; 4684 } 4685 4686 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state) 4687 { 4688 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 4689 struct intel_atomic_state *state = 4690 to_intel_atomic_state(new_crtc_state->uapi.state); 4691 const struct intel_crtc_state *old_crtc_state = 4692 intel_atomic_get_old_crtc_state(state, crtc); 4693 4694 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes; 4695 } 4696 4697 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) 4698 { 4699 const struct drm_display_mode *pipe_mode = 4700 &crtc_state->hw.pipe_mode; 4701 int linetime_wm; 4702 4703 if (!crtc_state->hw.enable) 4704 return 0; 4705 4706 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4707 pipe_mode->crtc_clock); 4708 4709 return min(linetime_wm, 0x1ff); 4710 } 4711 4712 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, 4713 const struct intel_cdclk_state *cdclk_state) 4714 { 4715 const struct drm_display_mode *pipe_mode = 4716 &crtc_state->hw.pipe_mode; 4717 int linetime_wm; 4718 4719 if (!crtc_state->hw.enable) 4720 return 0; 4721 4722 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4723 cdclk_state->logical.cdclk); 4724 4725 return min(linetime_wm, 0x1ff); 4726 } 4727 4728 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) 4729 { 4730 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4731 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4732 const struct drm_display_mode *pipe_mode = 4733 &crtc_state->hw.pipe_mode; 4734 int linetime_wm; 4735 4736 if (!crtc_state->hw.enable) 4737 return 0; 4738 4739 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8, 4740 crtc_state->pixel_rate); 4741 4742 /* Display WA #1135: BXT:ALL GLK:ALL */ 4743 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 4744 dev_priv->ipc_enabled) 4745 linetime_wm /= 2; 4746 4747 return min(linetime_wm, 0x1ff); 4748 } 4749 4750 static int hsw_compute_linetime_wm(struct intel_atomic_state *state, 4751 struct intel_crtc *crtc) 4752 { 4753 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4754 struct intel_crtc_state *crtc_state = 4755 intel_atomic_get_new_crtc_state(state, crtc); 4756 const struct intel_cdclk_state *cdclk_state; 4757 4758 if (DISPLAY_VER(dev_priv) >= 9) 4759 crtc_state->linetime = skl_linetime_wm(crtc_state); 4760 else 4761 crtc_state->linetime = hsw_linetime_wm(crtc_state); 4762 4763 if (!hsw_crtc_supports_ips(crtc)) 4764 return 0; 4765 4766 cdclk_state = intel_atomic_get_cdclk_state(state); 4767 if (IS_ERR(cdclk_state)) 4768 return PTR_ERR(cdclk_state); 4769 4770 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state, 4771 cdclk_state); 4772 4773 return 0; 4774 } 4775 4776 static int intel_crtc_atomic_check(struct intel_atomic_state *state, 4777 struct intel_crtc *crtc) 4778 { 4779 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4780 struct intel_crtc_state *crtc_state = 4781 intel_atomic_get_new_crtc_state(state, crtc); 4782 bool mode_changed = intel_crtc_needs_modeset(crtc_state); 4783 int ret; 4784 4785 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) && 4786 mode_changed && !crtc_state->hw.active) 4787 crtc_state->update_wm_post = true; 4788 4789 if (mode_changed) { 4790 ret = intel_dpll_crtc_compute_clock(state, crtc); 4791 if (ret) 4792 return ret; 4793 4794 ret = intel_dpll_crtc_get_shared_dpll(state, crtc); 4795 if (ret) 4796 return ret; 4797 } 4798 4799 /* 4800 * May need to update pipe gamma enable bits 4801 * when C8 planes are getting enabled/disabled. 4802 */ 4803 if (c8_planes_changed(crtc_state)) 4804 crtc_state->uapi.color_mgmt_changed = true; 4805 4806 if (mode_changed || crtc_state->update_pipe || 4807 crtc_state->uapi.color_mgmt_changed) { 4808 ret = intel_color_check(crtc_state); 4809 if (ret) 4810 return ret; 4811 } 4812 4813 ret = intel_compute_pipe_wm(state, crtc); 4814 if (ret) { 4815 drm_dbg_kms(&dev_priv->drm, 4816 "Target pipe watermarks are invalid\n"); 4817 return ret; 4818 } 4819 4820 /* 4821 * Calculate 'intermediate' watermarks that satisfy both the 4822 * old state and the new state. We can program these 4823 * immediately. 4824 */ 4825 ret = intel_compute_intermediate_wm(state, crtc); 4826 if (ret) { 4827 drm_dbg_kms(&dev_priv->drm, 4828 "No valid intermediate pipe watermarks are possible\n"); 4829 return ret; 4830 } 4831 4832 if (DISPLAY_VER(dev_priv) >= 9) { 4833 if (mode_changed || crtc_state->update_pipe) { 4834 ret = skl_update_scaler_crtc(crtc_state); 4835 if (ret) 4836 return ret; 4837 } 4838 4839 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state); 4840 if (ret) 4841 return ret; 4842 } 4843 4844 if (HAS_IPS(dev_priv)) { 4845 ret = hsw_ips_compute_config(state, crtc); 4846 if (ret) 4847 return ret; 4848 } 4849 4850 if (DISPLAY_VER(dev_priv) >= 9 || 4851 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 4852 ret = hsw_compute_linetime_wm(state, crtc); 4853 if (ret) 4854 return ret; 4855 4856 } 4857 4858 ret = intel_psr2_sel_fetch_update(state, crtc); 4859 if (ret) 4860 return ret; 4861 4862 return 0; 4863 } 4864 4865 static int 4866 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state, 4867 struct intel_crtc_state *crtc_state) 4868 { 4869 struct drm_connector *connector = conn_state->connector; 4870 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 4871 const struct drm_display_info *info = &connector->display_info; 4872 int bpp; 4873 4874 switch (conn_state->max_bpc) { 4875 case 6 ... 7: 4876 bpp = 6 * 3; 4877 break; 4878 case 8 ... 9: 4879 bpp = 8 * 3; 4880 break; 4881 case 10 ... 11: 4882 bpp = 10 * 3; 4883 break; 4884 case 12 ... 16: 4885 bpp = 12 * 3; 4886 break; 4887 default: 4888 MISSING_CASE(conn_state->max_bpc); 4889 return -EINVAL; 4890 } 4891 4892 if (bpp < crtc_state->pipe_bpp) { 4893 drm_dbg_kms(&i915->drm, 4894 "[CONNECTOR:%d:%s] Limiting display bpp to %d " 4895 "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n", 4896 connector->base.id, connector->name, 4897 bpp, 3 * info->bpc, 4898 3 * conn_state->max_requested_bpc, 4899 crtc_state->pipe_bpp); 4900 4901 crtc_state->pipe_bpp = bpp; 4902 } 4903 4904 return 0; 4905 } 4906 4907 static int 4908 compute_baseline_pipe_bpp(struct intel_atomic_state *state, 4909 struct intel_crtc *crtc) 4910 { 4911 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4912 struct intel_crtc_state *crtc_state = 4913 intel_atomic_get_new_crtc_state(state, crtc); 4914 struct drm_connector *connector; 4915 struct drm_connector_state *connector_state; 4916 int bpp, i; 4917 4918 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 4919 IS_CHERRYVIEW(dev_priv))) 4920 bpp = 10*3; 4921 else if (DISPLAY_VER(dev_priv) >= 5) 4922 bpp = 12*3; 4923 else 4924 bpp = 8*3; 4925 4926 crtc_state->pipe_bpp = bpp; 4927 4928 /* Clamp display bpp to connector max bpp */ 4929 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4930 int ret; 4931 4932 if (connector_state->crtc != &crtc->base) 4933 continue; 4934 4935 ret = compute_sink_pipe_bpp(connector_state, crtc_state); 4936 if (ret) 4937 return ret; 4938 } 4939 4940 return 0; 4941 } 4942 4943 static bool check_digital_port_conflicts(struct intel_atomic_state *state) 4944 { 4945 struct drm_device *dev = state->base.dev; 4946 struct drm_connector *connector; 4947 struct drm_connector_list_iter conn_iter; 4948 unsigned int used_ports = 0; 4949 unsigned int used_mst_ports = 0; 4950 bool ret = true; 4951 4952 /* 4953 * We're going to peek into connector->state, 4954 * hence connection_mutex must be held. 4955 */ 4956 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex); 4957 4958 /* 4959 * Walk the connector list instead of the encoder 4960 * list to detect the problem on ddi platforms 4961 * where there's just one encoder per digital port. 4962 */ 4963 drm_connector_list_iter_begin(dev, &conn_iter); 4964 drm_for_each_connector_iter(connector, &conn_iter) { 4965 struct drm_connector_state *connector_state; 4966 struct intel_encoder *encoder; 4967 4968 connector_state = 4969 drm_atomic_get_new_connector_state(&state->base, 4970 connector); 4971 if (!connector_state) 4972 connector_state = connector->state; 4973 4974 if (!connector_state->best_encoder) 4975 continue; 4976 4977 encoder = to_intel_encoder(connector_state->best_encoder); 4978 4979 drm_WARN_ON(dev, !connector_state->crtc); 4980 4981 switch (encoder->type) { 4982 case INTEL_OUTPUT_DDI: 4983 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev)))) 4984 break; 4985 fallthrough; 4986 case INTEL_OUTPUT_DP: 4987 case INTEL_OUTPUT_HDMI: 4988 case INTEL_OUTPUT_EDP: 4989 /* the same port mustn't appear more than once */ 4990 if (used_ports & BIT(encoder->port)) 4991 ret = false; 4992 4993 used_ports |= BIT(encoder->port); 4994 break; 4995 case INTEL_OUTPUT_DP_MST: 4996 used_mst_ports |= 4997 1 << encoder->port; 4998 break; 4999 default: 5000 break; 5001 } 5002 } 5003 drm_connector_list_iter_end(&conn_iter); 5004 5005 /* can't mix MST and SST/HDMI on the same port */ 5006 if (used_ports & used_mst_ports) 5007 return false; 5008 5009 return ret; 5010 } 5011 5012 static void 5013 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state, 5014 struct intel_crtc *crtc) 5015 { 5016 struct intel_crtc_state *crtc_state = 5017 intel_atomic_get_new_crtc_state(state, crtc); 5018 5019 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 5020 5021 drm_property_replace_blob(&crtc_state->hw.degamma_lut, 5022 crtc_state->uapi.degamma_lut); 5023 drm_property_replace_blob(&crtc_state->hw.gamma_lut, 5024 crtc_state->uapi.gamma_lut); 5025 drm_property_replace_blob(&crtc_state->hw.ctm, 5026 crtc_state->uapi.ctm); 5027 } 5028 5029 static void 5030 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state, 5031 struct intel_crtc *crtc) 5032 { 5033 struct intel_crtc_state *crtc_state = 5034 intel_atomic_get_new_crtc_state(state, crtc); 5035 5036 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 5037 5038 crtc_state->hw.enable = crtc_state->uapi.enable; 5039 crtc_state->hw.active = crtc_state->uapi.active; 5040 drm_mode_copy(&crtc_state->hw.mode, 5041 &crtc_state->uapi.mode); 5042 drm_mode_copy(&crtc_state->hw.adjusted_mode, 5043 &crtc_state->uapi.adjusted_mode); 5044 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter; 5045 5046 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 5047 } 5048 5049 static void 5050 copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state, 5051 struct intel_crtc *slave_crtc) 5052 { 5053 struct intel_crtc_state *slave_crtc_state = 5054 intel_atomic_get_new_crtc_state(state, slave_crtc); 5055 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 5056 const struct intel_crtc_state *master_crtc_state = 5057 intel_atomic_get_new_crtc_state(state, master_crtc); 5058 5059 drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut, 5060 master_crtc_state->hw.degamma_lut); 5061 drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut, 5062 master_crtc_state->hw.gamma_lut); 5063 drm_property_replace_blob(&slave_crtc_state->hw.ctm, 5064 master_crtc_state->hw.ctm); 5065 5066 slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed; 5067 } 5068 5069 static int 5070 copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state, 5071 struct intel_crtc *slave_crtc) 5072 { 5073 struct intel_crtc_state *slave_crtc_state = 5074 intel_atomic_get_new_crtc_state(state, slave_crtc); 5075 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 5076 const struct intel_crtc_state *master_crtc_state = 5077 intel_atomic_get_new_crtc_state(state, master_crtc); 5078 struct intel_crtc_state *saved_state; 5079 5080 WARN_ON(master_crtc_state->bigjoiner_pipes != 5081 slave_crtc_state->bigjoiner_pipes); 5082 5083 saved_state = kmemdup(master_crtc_state, sizeof(*saved_state), GFP_KERNEL); 5084 if (!saved_state) 5085 return -ENOMEM; 5086 5087 /* preserve some things from the slave's original crtc state */ 5088 saved_state->uapi = slave_crtc_state->uapi; 5089 saved_state->scaler_state = slave_crtc_state->scaler_state; 5090 saved_state->shared_dpll = slave_crtc_state->shared_dpll; 5091 saved_state->dpll_hw_state = slave_crtc_state->dpll_hw_state; 5092 saved_state->crc_enabled = slave_crtc_state->crc_enabled; 5093 5094 intel_crtc_free_hw_state(slave_crtc_state); 5095 memcpy(slave_crtc_state, saved_state, sizeof(*slave_crtc_state)); 5096 kfree(saved_state); 5097 5098 /* Re-init hw state */ 5099 memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw)); 5100 slave_crtc_state->hw.enable = master_crtc_state->hw.enable; 5101 slave_crtc_state->hw.active = master_crtc_state->hw.active; 5102 drm_mode_copy(&slave_crtc_state->hw.mode, 5103 &master_crtc_state->hw.mode); 5104 drm_mode_copy(&slave_crtc_state->hw.pipe_mode, 5105 &master_crtc_state->hw.pipe_mode); 5106 drm_mode_copy(&slave_crtc_state->hw.adjusted_mode, 5107 &master_crtc_state->hw.adjusted_mode); 5108 slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter; 5109 5110 copy_bigjoiner_crtc_state_nomodeset(state, slave_crtc); 5111 5112 slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed; 5113 slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed; 5114 slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed; 5115 5116 WARN_ON(master_crtc_state->bigjoiner_pipes != 5117 slave_crtc_state->bigjoiner_pipes); 5118 5119 return 0; 5120 } 5121 5122 static int 5123 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state, 5124 struct intel_crtc *crtc) 5125 { 5126 struct intel_crtc_state *crtc_state = 5127 intel_atomic_get_new_crtc_state(state, crtc); 5128 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5129 struct intel_crtc_state *saved_state; 5130 5131 saved_state = intel_crtc_state_alloc(crtc); 5132 if (!saved_state) 5133 return -ENOMEM; 5134 5135 /* free the old crtc_state->hw members */ 5136 intel_crtc_free_hw_state(crtc_state); 5137 5138 /* FIXME: before the switch to atomic started, a new pipe_config was 5139 * kzalloc'd. Code that depends on any field being zero should be 5140 * fixed, so that the crtc_state can be safely duplicated. For now, 5141 * only fields that are know to not cause problems are preserved. */ 5142 5143 saved_state->uapi = crtc_state->uapi; 5144 saved_state->scaler_state = crtc_state->scaler_state; 5145 saved_state->shared_dpll = crtc_state->shared_dpll; 5146 saved_state->dpll_hw_state = crtc_state->dpll_hw_state; 5147 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, 5148 sizeof(saved_state->icl_port_dplls)); 5149 saved_state->crc_enabled = crtc_state->crc_enabled; 5150 if (IS_G4X(dev_priv) || 5151 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5152 saved_state->wm = crtc_state->wm; 5153 5154 memcpy(crtc_state, saved_state, sizeof(*crtc_state)); 5155 kfree(saved_state); 5156 5157 intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc); 5158 5159 return 0; 5160 } 5161 5162 static int 5163 intel_modeset_pipe_config(struct intel_atomic_state *state, 5164 struct intel_crtc *crtc) 5165 { 5166 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 5167 struct intel_crtc_state *crtc_state = 5168 intel_atomic_get_new_crtc_state(state, crtc); 5169 struct drm_connector *connector; 5170 struct drm_connector_state *connector_state; 5171 int pipe_src_w, pipe_src_h; 5172 int base_bpp, ret, i; 5173 bool retry = true; 5174 5175 crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe; 5176 5177 crtc_state->framestart_delay = 1; 5178 5179 /* 5180 * Sanitize sync polarity flags based on requested ones. If neither 5181 * positive or negative polarity is requested, treat this as meaning 5182 * negative polarity. 5183 */ 5184 if (!(crtc_state->hw.adjusted_mode.flags & 5185 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) 5186 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; 5187 5188 if (!(crtc_state->hw.adjusted_mode.flags & 5189 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 5190 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; 5191 5192 ret = compute_baseline_pipe_bpp(state, crtc); 5193 if (ret) 5194 return ret; 5195 5196 base_bpp = crtc_state->pipe_bpp; 5197 5198 /* 5199 * Determine the real pipe dimensions. Note that stereo modes can 5200 * increase the actual pipe size due to the frame doubling and 5201 * insertion of additional space for blanks between the frame. This 5202 * is stored in the crtc timings. We use the requested mode to do this 5203 * computation to clearly distinguish it from the adjusted mode, which 5204 * can be changed by the connectors in the below retry loop. 5205 */ 5206 drm_mode_get_hv_timing(&crtc_state->hw.mode, 5207 &pipe_src_w, &pipe_src_h); 5208 drm_rect_init(&crtc_state->pipe_src, 0, 0, 5209 pipe_src_w, pipe_src_h); 5210 5211 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5212 struct intel_encoder *encoder = 5213 to_intel_encoder(connector_state->best_encoder); 5214 5215 if (connector_state->crtc != &crtc->base) 5216 continue; 5217 5218 if (!check_single_encoder_cloning(state, crtc, encoder)) { 5219 drm_dbg_kms(&i915->drm, 5220 "[ENCODER:%d:%s] rejecting invalid cloning configuration\n", 5221 encoder->base.base.id, encoder->base.name); 5222 return -EINVAL; 5223 } 5224 5225 /* 5226 * Determine output_types before calling the .compute_config() 5227 * hooks so that the hooks can use this information safely. 5228 */ 5229 if (encoder->compute_output_type) 5230 crtc_state->output_types |= 5231 BIT(encoder->compute_output_type(encoder, crtc_state, 5232 connector_state)); 5233 else 5234 crtc_state->output_types |= BIT(encoder->type); 5235 } 5236 5237 encoder_retry: 5238 /* Ensure the port clock defaults are reset when retrying. */ 5239 crtc_state->port_clock = 0; 5240 crtc_state->pixel_multiplier = 1; 5241 5242 /* Fill in default crtc timings, allow encoders to overwrite them. */ 5243 drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode, 5244 CRTC_STEREO_DOUBLE); 5245 5246 /* Pass our mode to the connectors and the CRTC to give them a chance to 5247 * adjust it according to limitations or connector properties, and also 5248 * a chance to reject the mode entirely. 5249 */ 5250 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5251 struct intel_encoder *encoder = 5252 to_intel_encoder(connector_state->best_encoder); 5253 5254 if (connector_state->crtc != &crtc->base) 5255 continue; 5256 5257 ret = encoder->compute_config(encoder, crtc_state, 5258 connector_state); 5259 if (ret == -EDEADLK) 5260 return ret; 5261 if (ret < 0) { 5262 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n", 5263 encoder->base.base.id, encoder->base.name, ret); 5264 return ret; 5265 } 5266 } 5267 5268 /* Set default port clock if not overwritten by the encoder. Needs to be 5269 * done afterwards in case the encoder adjusts the mode. */ 5270 if (!crtc_state->port_clock) 5271 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock 5272 * crtc_state->pixel_multiplier; 5273 5274 ret = intel_crtc_compute_config(state, crtc); 5275 if (ret == -EDEADLK) 5276 return ret; 5277 if (ret == -EAGAIN) { 5278 if (drm_WARN(&i915->drm, !retry, 5279 "[CRTC:%d:%s] loop in pipe configuration computation\n", 5280 crtc->base.base.id, crtc->base.name)) 5281 return -EINVAL; 5282 5283 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] bw constrained, retrying\n", 5284 crtc->base.base.id, crtc->base.name); 5285 retry = false; 5286 goto encoder_retry; 5287 } 5288 if (ret < 0) { 5289 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n", 5290 crtc->base.base.id, crtc->base.name, ret); 5291 return ret; 5292 } 5293 5294 /* Dithering seems to not pass-through bits correctly when it should, so 5295 * only enable it on 6bpc panels and when its not a compliance 5296 * test requesting 6bpc video pattern. 5297 */ 5298 crtc_state->dither = (crtc_state->pipe_bpp == 6*3) && 5299 !crtc_state->dither_force_disable; 5300 drm_dbg_kms(&i915->drm, 5301 "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n", 5302 crtc->base.base.id, crtc->base.name, 5303 base_bpp, crtc_state->pipe_bpp, crtc_state->dither); 5304 5305 return 0; 5306 } 5307 5308 static int 5309 intel_modeset_pipe_config_late(struct intel_atomic_state *state, 5310 struct intel_crtc *crtc) 5311 { 5312 struct intel_crtc_state *crtc_state = 5313 intel_atomic_get_new_crtc_state(state, crtc); 5314 struct drm_connector_state *conn_state; 5315 struct drm_connector *connector; 5316 int i; 5317 5318 intel_bigjoiner_adjust_pipe_src(crtc_state); 5319 5320 for_each_new_connector_in_state(&state->base, connector, 5321 conn_state, i) { 5322 struct intel_encoder *encoder = 5323 to_intel_encoder(conn_state->best_encoder); 5324 int ret; 5325 5326 if (conn_state->crtc != &crtc->base || 5327 !encoder->compute_config_late) 5328 continue; 5329 5330 ret = encoder->compute_config_late(encoder, crtc_state, 5331 conn_state); 5332 if (ret) 5333 return ret; 5334 } 5335 5336 return 0; 5337 } 5338 5339 bool intel_fuzzy_clock_check(int clock1, int clock2) 5340 { 5341 int diff; 5342 5343 if (clock1 == clock2) 5344 return true; 5345 5346 if (!clock1 || !clock2) 5347 return false; 5348 5349 diff = abs(clock1 - clock2); 5350 5351 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) 5352 return true; 5353 5354 return false; 5355 } 5356 5357 static bool 5358 intel_compare_m_n(unsigned int m, unsigned int n, 5359 unsigned int m2, unsigned int n2, 5360 bool exact) 5361 { 5362 if (m == m2 && n == n2) 5363 return true; 5364 5365 if (exact || !m || !n || !m2 || !n2) 5366 return false; 5367 5368 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); 5369 5370 if (n > n2) { 5371 while (n > n2) { 5372 m2 <<= 1; 5373 n2 <<= 1; 5374 } 5375 } else if (n < n2) { 5376 while (n < n2) { 5377 m <<= 1; 5378 n <<= 1; 5379 } 5380 } 5381 5382 if (n != n2) 5383 return false; 5384 5385 return intel_fuzzy_clock_check(m, m2); 5386 } 5387 5388 static bool 5389 intel_compare_link_m_n(const struct intel_link_m_n *m_n, 5390 const struct intel_link_m_n *m2_n2, 5391 bool exact) 5392 { 5393 return m_n->tu == m2_n2->tu && 5394 intel_compare_m_n(m_n->data_m, m_n->data_n, 5395 m2_n2->data_m, m2_n2->data_n, exact) && 5396 intel_compare_m_n(m_n->link_m, m_n->link_n, 5397 m2_n2->link_m, m2_n2->link_n, exact); 5398 } 5399 5400 static bool 5401 intel_compare_infoframe(const union hdmi_infoframe *a, 5402 const union hdmi_infoframe *b) 5403 { 5404 return memcmp(a, b, sizeof(*a)) == 0; 5405 } 5406 5407 static bool 5408 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a, 5409 const struct drm_dp_vsc_sdp *b) 5410 { 5411 return memcmp(a, b, sizeof(*a)) == 0; 5412 } 5413 5414 static void 5415 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv, 5416 bool fastset, const char *name, 5417 const union hdmi_infoframe *a, 5418 const union hdmi_infoframe *b) 5419 { 5420 if (fastset) { 5421 if (!drm_debug_enabled(DRM_UT_KMS)) 5422 return; 5423 5424 drm_dbg_kms(&dev_priv->drm, 5425 "fastset mismatch in %s infoframe\n", name); 5426 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 5427 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a); 5428 drm_dbg_kms(&dev_priv->drm, "found:\n"); 5429 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b); 5430 } else { 5431 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name); 5432 drm_err(&dev_priv->drm, "expected:\n"); 5433 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a); 5434 drm_err(&dev_priv->drm, "found:\n"); 5435 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b); 5436 } 5437 } 5438 5439 static void 5440 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv, 5441 bool fastset, const char *name, 5442 const struct drm_dp_vsc_sdp *a, 5443 const struct drm_dp_vsc_sdp *b) 5444 { 5445 if (fastset) { 5446 if (!drm_debug_enabled(DRM_UT_KMS)) 5447 return; 5448 5449 drm_dbg_kms(&dev_priv->drm, 5450 "fastset mismatch in %s dp sdp\n", name); 5451 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 5452 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a); 5453 drm_dbg_kms(&dev_priv->drm, "found:\n"); 5454 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b); 5455 } else { 5456 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name); 5457 drm_err(&dev_priv->drm, "expected:\n"); 5458 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a); 5459 drm_err(&dev_priv->drm, "found:\n"); 5460 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b); 5461 } 5462 } 5463 5464 static void __printf(4, 5) 5465 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc, 5466 const char *name, const char *format, ...) 5467 { 5468 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 5469 struct va_format vaf; 5470 va_list args; 5471 5472 va_start(args, format); 5473 vaf.fmt = format; 5474 vaf.va = &args; 5475 5476 if (fastset) 5477 drm_dbg_kms(&i915->drm, 5478 "[CRTC:%d:%s] fastset mismatch in %s %pV\n", 5479 crtc->base.base.id, crtc->base.name, name, &vaf); 5480 else 5481 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n", 5482 crtc->base.base.id, crtc->base.name, name, &vaf); 5483 5484 va_end(args); 5485 } 5486 5487 static bool fastboot_enabled(struct drm_i915_private *dev_priv) 5488 { 5489 if (dev_priv->params.fastboot != -1) 5490 return dev_priv->params.fastboot; 5491 5492 /* Enable fastboot by default on Skylake and newer */ 5493 if (DISPLAY_VER(dev_priv) >= 9) 5494 return true; 5495 5496 /* Enable fastboot by default on VLV and CHV */ 5497 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5498 return true; 5499 5500 /* Disabled by default on all others */ 5501 return false; 5502 } 5503 5504 bool 5505 intel_pipe_config_compare(const struct intel_crtc_state *current_config, 5506 const struct intel_crtc_state *pipe_config, 5507 bool fastset) 5508 { 5509 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev); 5510 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 5511 bool ret = true; 5512 u32 bp_gamma = 0; 5513 bool fixup_inherited = fastset && 5514 current_config->inherited && !pipe_config->inherited; 5515 5516 if (fixup_inherited && !fastboot_enabled(dev_priv)) { 5517 drm_dbg_kms(&dev_priv->drm, 5518 "initial modeset and fastboot not set\n"); 5519 ret = false; 5520 } 5521 5522 #define PIPE_CONF_CHECK_X(name) do { \ 5523 if (current_config->name != pipe_config->name) { \ 5524 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5525 "(expected 0x%08x, found 0x%08x)", \ 5526 current_config->name, \ 5527 pipe_config->name); \ 5528 ret = false; \ 5529 } \ 5530 } while (0) 5531 5532 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \ 5533 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \ 5534 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5535 "(expected 0x%08x, found 0x%08x)", \ 5536 current_config->name & (mask), \ 5537 pipe_config->name & (mask)); \ 5538 ret = false; \ 5539 } \ 5540 } while (0) 5541 5542 #define PIPE_CONF_CHECK_I(name) do { \ 5543 if (current_config->name != pipe_config->name) { \ 5544 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5545 "(expected %i, found %i)", \ 5546 current_config->name, \ 5547 pipe_config->name); \ 5548 ret = false; \ 5549 } \ 5550 } while (0) 5551 5552 #define PIPE_CONF_CHECK_BOOL(name) do { \ 5553 if (current_config->name != pipe_config->name) { \ 5554 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5555 "(expected %s, found %s)", \ 5556 str_yes_no(current_config->name), \ 5557 str_yes_no(pipe_config->name)); \ 5558 ret = false; \ 5559 } \ 5560 } while (0) 5561 5562 /* 5563 * Checks state where we only read out the enabling, but not the entire 5564 * state itself (like full infoframes or ELD for audio). These states 5565 * require a full modeset on bootup to fix up. 5566 */ 5567 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \ 5568 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \ 5569 PIPE_CONF_CHECK_BOOL(name); \ 5570 } else { \ 5571 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5572 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \ 5573 str_yes_no(current_config->name), \ 5574 str_yes_no(pipe_config->name)); \ 5575 ret = false; \ 5576 } \ 5577 } while (0) 5578 5579 #define PIPE_CONF_CHECK_P(name) do { \ 5580 if (current_config->name != pipe_config->name) { \ 5581 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5582 "(expected %p, found %p)", \ 5583 current_config->name, \ 5584 pipe_config->name); \ 5585 ret = false; \ 5586 } \ 5587 } while (0) 5588 5589 #define PIPE_CONF_CHECK_M_N(name) do { \ 5590 if (!intel_compare_link_m_n(¤t_config->name, \ 5591 &pipe_config->name,\ 5592 !fastset)) { \ 5593 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5594 "(expected tu %i data %i/%i link %i/%i, " \ 5595 "found tu %i, data %i/%i link %i/%i)", \ 5596 current_config->name.tu, \ 5597 current_config->name.data_m, \ 5598 current_config->name.data_n, \ 5599 current_config->name.link_m, \ 5600 current_config->name.link_n, \ 5601 pipe_config->name.tu, \ 5602 pipe_config->name.data_m, \ 5603 pipe_config->name.data_n, \ 5604 pipe_config->name.link_m, \ 5605 pipe_config->name.link_n); \ 5606 ret = false; \ 5607 } \ 5608 } while (0) 5609 5610 #define PIPE_CONF_CHECK_TIMINGS(name) do { \ 5611 PIPE_CONF_CHECK_I(name.crtc_hdisplay); \ 5612 PIPE_CONF_CHECK_I(name.crtc_htotal); \ 5613 PIPE_CONF_CHECK_I(name.crtc_hblank_start); \ 5614 PIPE_CONF_CHECK_I(name.crtc_hblank_end); \ 5615 PIPE_CONF_CHECK_I(name.crtc_hsync_start); \ 5616 PIPE_CONF_CHECK_I(name.crtc_hsync_end); \ 5617 PIPE_CONF_CHECK_I(name.crtc_vdisplay); \ 5618 PIPE_CONF_CHECK_I(name.crtc_vtotal); \ 5619 PIPE_CONF_CHECK_I(name.crtc_vblank_start); \ 5620 PIPE_CONF_CHECK_I(name.crtc_vblank_end); \ 5621 PIPE_CONF_CHECK_I(name.crtc_vsync_start); \ 5622 PIPE_CONF_CHECK_I(name.crtc_vsync_end); \ 5623 } while (0) 5624 5625 #define PIPE_CONF_CHECK_RECT(name) do { \ 5626 PIPE_CONF_CHECK_I(name.x1); \ 5627 PIPE_CONF_CHECK_I(name.x2); \ 5628 PIPE_CONF_CHECK_I(name.y1); \ 5629 PIPE_CONF_CHECK_I(name.y2); \ 5630 } while (0) 5631 5632 /* This is required for BDW+ where there is only one set of registers for 5633 * switching between high and low RR. 5634 * This macro can be used whenever a comparison has to be made between one 5635 * hw state and multiple sw state variables. 5636 */ 5637 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \ 5638 if (!intel_compare_link_m_n(¤t_config->name, \ 5639 &pipe_config->name, !fastset) && \ 5640 !intel_compare_link_m_n(¤t_config->alt_name, \ 5641 &pipe_config->name, !fastset)) { \ 5642 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5643 "(expected tu %i data %i/%i link %i/%i, " \ 5644 "or tu %i data %i/%i link %i/%i, " \ 5645 "found tu %i, data %i/%i link %i/%i)", \ 5646 current_config->name.tu, \ 5647 current_config->name.data_m, \ 5648 current_config->name.data_n, \ 5649 current_config->name.link_m, \ 5650 current_config->name.link_n, \ 5651 current_config->alt_name.tu, \ 5652 current_config->alt_name.data_m, \ 5653 current_config->alt_name.data_n, \ 5654 current_config->alt_name.link_m, \ 5655 current_config->alt_name.link_n, \ 5656 pipe_config->name.tu, \ 5657 pipe_config->name.data_m, \ 5658 pipe_config->name.data_n, \ 5659 pipe_config->name.link_m, \ 5660 pipe_config->name.link_n); \ 5661 ret = false; \ 5662 } \ 5663 } while (0) 5664 5665 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \ 5666 if ((current_config->name ^ pipe_config->name) & (mask)) { \ 5667 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5668 "(%x) (expected %i, found %i)", \ 5669 (mask), \ 5670 current_config->name & (mask), \ 5671 pipe_config->name & (mask)); \ 5672 ret = false; \ 5673 } \ 5674 } while (0) 5675 5676 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \ 5677 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ 5678 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5679 "(expected %i, found %i)", \ 5680 current_config->name, \ 5681 pipe_config->name); \ 5682 ret = false; \ 5683 } \ 5684 } while (0) 5685 5686 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \ 5687 if (!intel_compare_infoframe(¤t_config->infoframes.name, \ 5688 &pipe_config->infoframes.name)) { \ 5689 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \ 5690 ¤t_config->infoframes.name, \ 5691 &pipe_config->infoframes.name); \ 5692 ret = false; \ 5693 } \ 5694 } while (0) 5695 5696 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \ 5697 if (!current_config->has_psr && !pipe_config->has_psr && \ 5698 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \ 5699 &pipe_config->infoframes.name)) { \ 5700 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \ 5701 ¤t_config->infoframes.name, \ 5702 &pipe_config->infoframes.name); \ 5703 ret = false; \ 5704 } \ 5705 } while (0) 5706 5707 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \ 5708 if (current_config->name1 != pipe_config->name1) { \ 5709 pipe_config_mismatch(fastset, crtc, __stringify(name1), \ 5710 "(expected %i, found %i, won't compare lut values)", \ 5711 current_config->name1, \ 5712 pipe_config->name1); \ 5713 ret = false;\ 5714 } else { \ 5715 if (!intel_color_lut_equal(current_config->name2, \ 5716 pipe_config->name2, pipe_config->name1, \ 5717 bit_precision)) { \ 5718 pipe_config_mismatch(fastset, crtc, __stringify(name2), \ 5719 "hw_state doesn't match sw_state"); \ 5720 ret = false; \ 5721 } \ 5722 } \ 5723 } while (0) 5724 5725 #define PIPE_CONF_QUIRK(quirk) \ 5726 ((current_config->quirks | pipe_config->quirks) & (quirk)) 5727 5728 PIPE_CONF_CHECK_I(hw.enable); 5729 PIPE_CONF_CHECK_I(hw.active); 5730 5731 PIPE_CONF_CHECK_I(cpu_transcoder); 5732 PIPE_CONF_CHECK_I(mst_master_transcoder); 5733 5734 PIPE_CONF_CHECK_BOOL(has_pch_encoder); 5735 PIPE_CONF_CHECK_I(fdi_lanes); 5736 PIPE_CONF_CHECK_M_N(fdi_m_n); 5737 5738 PIPE_CONF_CHECK_I(lane_count); 5739 PIPE_CONF_CHECK_X(lane_lat_optim_mask); 5740 5741 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) { 5742 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); 5743 } else { 5744 PIPE_CONF_CHECK_M_N(dp_m_n); 5745 PIPE_CONF_CHECK_M_N(dp_m2_n2); 5746 } 5747 5748 PIPE_CONF_CHECK_X(output_types); 5749 5750 PIPE_CONF_CHECK_I(framestart_delay); 5751 PIPE_CONF_CHECK_I(msa_timing_delay); 5752 5753 PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode); 5754 PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode); 5755 5756 PIPE_CONF_CHECK_I(pixel_multiplier); 5757 5758 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5759 DRM_MODE_FLAG_INTERLACE); 5760 5761 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { 5762 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5763 DRM_MODE_FLAG_PHSYNC); 5764 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5765 DRM_MODE_FLAG_NHSYNC); 5766 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5767 DRM_MODE_FLAG_PVSYNC); 5768 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5769 DRM_MODE_FLAG_NVSYNC); 5770 } 5771 5772 PIPE_CONF_CHECK_I(output_format); 5773 PIPE_CONF_CHECK_BOOL(has_hdmi_sink); 5774 if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || 5775 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5776 PIPE_CONF_CHECK_BOOL(limited_color_range); 5777 5778 PIPE_CONF_CHECK_BOOL(hdmi_scrambling); 5779 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio); 5780 PIPE_CONF_CHECK_BOOL(has_infoframe); 5781 PIPE_CONF_CHECK_BOOL(fec_enable); 5782 5783 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio); 5784 5785 PIPE_CONF_CHECK_X(gmch_pfit.control); 5786 /* pfit ratios are autocomputed by the hw on gen4+ */ 5787 if (DISPLAY_VER(dev_priv) < 4) 5788 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); 5789 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); 5790 5791 /* 5792 * Changing the EDP transcoder input mux 5793 * (A_ONOFF vs. A_ON) requires a full modeset. 5794 */ 5795 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru); 5796 5797 if (!fastset) { 5798 PIPE_CONF_CHECK_RECT(pipe_src); 5799 5800 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled); 5801 PIPE_CONF_CHECK_RECT(pch_pfit.dst); 5802 5803 PIPE_CONF_CHECK_I(scaler_state.scaler_id); 5804 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate); 5805 5806 PIPE_CONF_CHECK_X(gamma_mode); 5807 if (IS_CHERRYVIEW(dev_priv)) 5808 PIPE_CONF_CHECK_X(cgm_mode); 5809 else 5810 PIPE_CONF_CHECK_X(csc_mode); 5811 PIPE_CONF_CHECK_BOOL(gamma_enable); 5812 PIPE_CONF_CHECK_BOOL(csc_enable); 5813 5814 PIPE_CONF_CHECK_I(linetime); 5815 PIPE_CONF_CHECK_I(ips_linetime); 5816 5817 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config); 5818 if (bp_gamma) 5819 PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma); 5820 5821 if (current_config->active_planes) { 5822 PIPE_CONF_CHECK_BOOL(has_psr); 5823 PIPE_CONF_CHECK_BOOL(has_psr2); 5824 PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); 5825 PIPE_CONF_CHECK_I(dc3co_exitline); 5826 } 5827 } 5828 5829 PIPE_CONF_CHECK_BOOL(double_wide); 5830 5831 if (dev_priv->dpll.mgr) { 5832 PIPE_CONF_CHECK_P(shared_dpll); 5833 5834 PIPE_CONF_CHECK_X(dpll_hw_state.dpll); 5835 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); 5836 PIPE_CONF_CHECK_X(dpll_hw_state.fp0); 5837 PIPE_CONF_CHECK_X(dpll_hw_state.fp1); 5838 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); 5839 PIPE_CONF_CHECK_X(dpll_hw_state.spll); 5840 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); 5841 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); 5842 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); 5843 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); 5844 PIPE_CONF_CHECK_X(dpll_hw_state.div0); 5845 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); 5846 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); 5847 PIPE_CONF_CHECK_X(dpll_hw_state.pll0); 5848 PIPE_CONF_CHECK_X(dpll_hw_state.pll1); 5849 PIPE_CONF_CHECK_X(dpll_hw_state.pll2); 5850 PIPE_CONF_CHECK_X(dpll_hw_state.pll3); 5851 PIPE_CONF_CHECK_X(dpll_hw_state.pll6); 5852 PIPE_CONF_CHECK_X(dpll_hw_state.pll8); 5853 PIPE_CONF_CHECK_X(dpll_hw_state.pll9); 5854 PIPE_CONF_CHECK_X(dpll_hw_state.pll10); 5855 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); 5856 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl); 5857 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1); 5858 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl); 5859 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0); 5860 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1); 5861 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf); 5862 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock); 5863 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc); 5864 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias); 5865 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias); 5866 } 5867 5868 PIPE_CONF_CHECK_X(dsi_pll.ctrl); 5869 PIPE_CONF_CHECK_X(dsi_pll.div); 5870 5871 if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5) 5872 PIPE_CONF_CHECK_I(pipe_bpp); 5873 5874 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock); 5875 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock); 5876 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); 5877 5878 PIPE_CONF_CHECK_I(min_voltage_level); 5879 5880 if (current_config->has_psr || pipe_config->has_psr) 5881 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable, 5882 ~intel_hdmi_infoframe_enable(DP_SDP_VSC)); 5883 else 5884 PIPE_CONF_CHECK_X(infoframes.enable); 5885 5886 PIPE_CONF_CHECK_X(infoframes.gcp); 5887 PIPE_CONF_CHECK_INFOFRAME(avi); 5888 PIPE_CONF_CHECK_INFOFRAME(spd); 5889 PIPE_CONF_CHECK_INFOFRAME(hdmi); 5890 PIPE_CONF_CHECK_INFOFRAME(drm); 5891 PIPE_CONF_CHECK_DP_VSC_SDP(vsc); 5892 5893 PIPE_CONF_CHECK_X(sync_mode_slaves_mask); 5894 PIPE_CONF_CHECK_I(master_transcoder); 5895 PIPE_CONF_CHECK_X(bigjoiner_pipes); 5896 5897 PIPE_CONF_CHECK_I(dsc.compression_enable); 5898 PIPE_CONF_CHECK_I(dsc.dsc_split); 5899 PIPE_CONF_CHECK_I(dsc.compressed_bpp); 5900 5901 PIPE_CONF_CHECK_BOOL(splitter.enable); 5902 PIPE_CONF_CHECK_I(splitter.link_count); 5903 PIPE_CONF_CHECK_I(splitter.pixel_overlap); 5904 5905 PIPE_CONF_CHECK_BOOL(vrr.enable); 5906 PIPE_CONF_CHECK_I(vrr.vmin); 5907 PIPE_CONF_CHECK_I(vrr.vmax); 5908 PIPE_CONF_CHECK_I(vrr.flipline); 5909 PIPE_CONF_CHECK_I(vrr.pipeline_full); 5910 PIPE_CONF_CHECK_I(vrr.guardband); 5911 5912 #undef PIPE_CONF_CHECK_X 5913 #undef PIPE_CONF_CHECK_I 5914 #undef PIPE_CONF_CHECK_BOOL 5915 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE 5916 #undef PIPE_CONF_CHECK_P 5917 #undef PIPE_CONF_CHECK_FLAGS 5918 #undef PIPE_CONF_CHECK_CLOCK_FUZZY 5919 #undef PIPE_CONF_CHECK_COLOR_LUT 5920 #undef PIPE_CONF_CHECK_TIMINGS 5921 #undef PIPE_CONF_CHECK_RECT 5922 #undef PIPE_CONF_QUIRK 5923 5924 return ret; 5925 } 5926 5927 static void 5928 intel_verify_planes(struct intel_atomic_state *state) 5929 { 5930 struct intel_plane *plane; 5931 const struct intel_plane_state *plane_state; 5932 int i; 5933 5934 for_each_new_intel_plane_in_state(state, plane, 5935 plane_state, i) 5936 assert_plane(plane, plane_state->planar_slave || 5937 plane_state->uapi.visible); 5938 } 5939 5940 int intel_modeset_all_pipes(struct intel_atomic_state *state) 5941 { 5942 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 5943 struct intel_crtc *crtc; 5944 5945 /* 5946 * Add all pipes to the state, and force 5947 * a modeset on all the active ones. 5948 */ 5949 for_each_intel_crtc(&dev_priv->drm, crtc) { 5950 struct intel_crtc_state *crtc_state; 5951 int ret; 5952 5953 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 5954 if (IS_ERR(crtc_state)) 5955 return PTR_ERR(crtc_state); 5956 5957 if (!crtc_state->hw.active || 5958 drm_atomic_crtc_needs_modeset(&crtc_state->uapi)) 5959 continue; 5960 5961 crtc_state->uapi.mode_changed = true; 5962 5963 ret = drm_atomic_add_affected_connectors(&state->base, 5964 &crtc->base); 5965 if (ret) 5966 return ret; 5967 5968 ret = intel_atomic_add_affected_planes(state, crtc); 5969 if (ret) 5970 return ret; 5971 5972 crtc_state->update_planes |= crtc_state->active_planes; 5973 } 5974 5975 return 0; 5976 } 5977 5978 void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state) 5979 { 5980 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 5981 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5982 struct drm_display_mode adjusted_mode; 5983 5984 drm_mode_init(&adjusted_mode, &crtc_state->hw.adjusted_mode); 5985 5986 if (crtc_state->vrr.enable) { 5987 adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax; 5988 adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax; 5989 adjusted_mode.crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state); 5990 crtc->vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state); 5991 } 5992 5993 drm_calc_timestamping_constants(&crtc->base, &adjusted_mode); 5994 5995 crtc->mode_flags = crtc_state->mode_flags; 5996 5997 /* 5998 * The scanline counter increments at the leading edge of hsync. 5999 * 6000 * On most platforms it starts counting from vtotal-1 on the 6001 * first active line. That means the scanline counter value is 6002 * always one less than what we would expect. Ie. just after 6003 * start of vblank, which also occurs at start of hsync (on the 6004 * last active line), the scanline counter will read vblank_start-1. 6005 * 6006 * On gen2 the scanline counter starts counting from 1 instead 6007 * of vtotal-1, so we have to subtract one (or rather add vtotal-1 6008 * to keep the value positive), instead of adding one. 6009 * 6010 * On HSW+ the behaviour of the scanline counter depends on the output 6011 * type. For DP ports it behaves like most other platforms, but on HDMI 6012 * there's an extra 1 line difference. So we need to add two instead of 6013 * one to the value. 6014 * 6015 * On VLV/CHV DSI the scanline counter would appear to increment 6016 * approx. 1/3 of a scanline before start of vblank. Unfortunately 6017 * that means we can't tell whether we're in vblank or not while 6018 * we're on that particular line. We must still set scanline_offset 6019 * to 1 so that the vblank timestamps come out correct when we query 6020 * the scanline counter from within the vblank interrupt handler. 6021 * However if queried just before the start of vblank we'll get an 6022 * answer that's slightly in the future. 6023 */ 6024 if (DISPLAY_VER(dev_priv) == 2) { 6025 int vtotal; 6026 6027 vtotal = adjusted_mode.crtc_vtotal; 6028 if (adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 6029 vtotal /= 2; 6030 6031 crtc->scanline_offset = vtotal - 1; 6032 } else if (HAS_DDI(dev_priv) && 6033 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 6034 crtc->scanline_offset = 2; 6035 } else { 6036 crtc->scanline_offset = 1; 6037 } 6038 } 6039 6040 static void intel_modeset_clear_plls(struct intel_atomic_state *state) 6041 { 6042 struct intel_crtc_state *new_crtc_state; 6043 struct intel_crtc *crtc; 6044 int i; 6045 6046 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6047 if (!intel_crtc_needs_modeset(new_crtc_state)) 6048 continue; 6049 6050 intel_release_shared_dplls(state, crtc); 6051 } 6052 } 6053 6054 /* 6055 * This implements the workaround described in the "notes" section of the mode 6056 * set sequence documentation. When going from no pipes or single pipe to 6057 * multiple pipes, and planes are enabled after the pipe, we need to wait at 6058 * least 2 vblanks on the first pipe before enabling planes on the second pipe. 6059 */ 6060 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state) 6061 { 6062 struct intel_crtc_state *crtc_state; 6063 struct intel_crtc *crtc; 6064 struct intel_crtc_state *first_crtc_state = NULL; 6065 struct intel_crtc_state *other_crtc_state = NULL; 6066 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; 6067 int i; 6068 6069 /* look at all crtc's that are going to be enabled in during modeset */ 6070 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6071 if (!crtc_state->hw.active || 6072 !intel_crtc_needs_modeset(crtc_state)) 6073 continue; 6074 6075 if (first_crtc_state) { 6076 other_crtc_state = crtc_state; 6077 break; 6078 } else { 6079 first_crtc_state = crtc_state; 6080 first_pipe = crtc->pipe; 6081 } 6082 } 6083 6084 /* No workaround needed? */ 6085 if (!first_crtc_state) 6086 return 0; 6087 6088 /* w/a possibly needed, check how many crtc's are already enabled. */ 6089 for_each_intel_crtc(state->base.dev, crtc) { 6090 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6091 if (IS_ERR(crtc_state)) 6092 return PTR_ERR(crtc_state); 6093 6094 crtc_state->hsw_workaround_pipe = INVALID_PIPE; 6095 6096 if (!crtc_state->hw.active || 6097 intel_crtc_needs_modeset(crtc_state)) 6098 continue; 6099 6100 /* 2 or more enabled crtcs means no need for w/a */ 6101 if (enabled_pipe != INVALID_PIPE) 6102 return 0; 6103 6104 enabled_pipe = crtc->pipe; 6105 } 6106 6107 if (enabled_pipe != INVALID_PIPE) 6108 first_crtc_state->hsw_workaround_pipe = enabled_pipe; 6109 else if (other_crtc_state) 6110 other_crtc_state->hsw_workaround_pipe = first_pipe; 6111 6112 return 0; 6113 } 6114 6115 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 6116 u8 active_pipes) 6117 { 6118 const struct intel_crtc_state *crtc_state; 6119 struct intel_crtc *crtc; 6120 int i; 6121 6122 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6123 if (crtc_state->hw.active) 6124 active_pipes |= BIT(crtc->pipe); 6125 else 6126 active_pipes &= ~BIT(crtc->pipe); 6127 } 6128 6129 return active_pipes; 6130 } 6131 6132 static int intel_modeset_checks(struct intel_atomic_state *state) 6133 { 6134 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6135 6136 state->modeset = true; 6137 6138 if (IS_HASWELL(dev_priv)) 6139 return hsw_mode_set_planes_workaround(state); 6140 6141 return 0; 6142 } 6143 6144 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state, 6145 struct intel_crtc_state *new_crtc_state) 6146 { 6147 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) 6148 return; 6149 6150 new_crtc_state->uapi.mode_changed = false; 6151 new_crtc_state->update_pipe = true; 6152 } 6153 6154 static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state, 6155 struct intel_crtc_state *new_crtc_state) 6156 { 6157 /* 6158 * If we're not doing the full modeset we want to 6159 * keep the current M/N values as they may be 6160 * sufficiently different to the computed values 6161 * to cause problems. 6162 * 6163 * FIXME: should really copy more fuzzy state here 6164 */ 6165 new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n; 6166 new_crtc_state->dp_m_n = old_crtc_state->dp_m_n; 6167 new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2; 6168 new_crtc_state->has_drrs = old_crtc_state->has_drrs; 6169 } 6170 6171 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state, 6172 struct intel_crtc *crtc, 6173 u8 plane_ids_mask) 6174 { 6175 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6176 struct intel_plane *plane; 6177 6178 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 6179 struct intel_plane_state *plane_state; 6180 6181 if ((plane_ids_mask & BIT(plane->id)) == 0) 6182 continue; 6183 6184 plane_state = intel_atomic_get_plane_state(state, plane); 6185 if (IS_ERR(plane_state)) 6186 return PTR_ERR(plane_state); 6187 } 6188 6189 return 0; 6190 } 6191 6192 int intel_atomic_add_affected_planes(struct intel_atomic_state *state, 6193 struct intel_crtc *crtc) 6194 { 6195 const struct intel_crtc_state *old_crtc_state = 6196 intel_atomic_get_old_crtc_state(state, crtc); 6197 const struct intel_crtc_state *new_crtc_state = 6198 intel_atomic_get_new_crtc_state(state, crtc); 6199 6200 return intel_crtc_add_planes_to_state(state, crtc, 6201 old_crtc_state->enabled_planes | 6202 new_crtc_state->enabled_planes); 6203 } 6204 6205 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv) 6206 { 6207 /* See {hsw,vlv,ivb}_plane_ratio() */ 6208 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) || 6209 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) || 6210 IS_IVYBRIDGE(dev_priv); 6211 } 6212 6213 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state, 6214 struct intel_crtc *crtc, 6215 struct intel_crtc *other) 6216 { 6217 const struct intel_plane_state *plane_state; 6218 struct intel_plane *plane; 6219 u8 plane_ids = 0; 6220 int i; 6221 6222 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 6223 if (plane->pipe == crtc->pipe) 6224 plane_ids |= BIT(plane->id); 6225 } 6226 6227 return intel_crtc_add_planes_to_state(state, other, plane_ids); 6228 } 6229 6230 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state) 6231 { 6232 struct drm_i915_private *i915 = to_i915(state->base.dev); 6233 const struct intel_crtc_state *crtc_state; 6234 struct intel_crtc *crtc; 6235 int i; 6236 6237 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6238 struct intel_crtc *other; 6239 6240 for_each_intel_crtc_in_pipe_mask(&i915->drm, other, 6241 crtc_state->bigjoiner_pipes) { 6242 int ret; 6243 6244 if (crtc == other) 6245 continue; 6246 6247 ret = intel_crtc_add_bigjoiner_planes(state, crtc, other); 6248 if (ret) 6249 return ret; 6250 } 6251 } 6252 6253 return 0; 6254 } 6255 6256 static int intel_atomic_check_planes(struct intel_atomic_state *state) 6257 { 6258 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6259 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6260 struct intel_plane_state *plane_state; 6261 struct intel_plane *plane; 6262 struct intel_crtc *crtc; 6263 int i, ret; 6264 6265 ret = icl_add_linked_planes(state); 6266 if (ret) 6267 return ret; 6268 6269 ret = intel_bigjoiner_add_affected_planes(state); 6270 if (ret) 6271 return ret; 6272 6273 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 6274 ret = intel_plane_atomic_check(state, plane); 6275 if (ret) { 6276 drm_dbg_atomic(&dev_priv->drm, 6277 "[PLANE:%d:%s] atomic driver check failed\n", 6278 plane->base.base.id, plane->base.name); 6279 return ret; 6280 } 6281 } 6282 6283 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6284 new_crtc_state, i) { 6285 u8 old_active_planes, new_active_planes; 6286 6287 ret = icl_check_nv12_planes(new_crtc_state); 6288 if (ret) 6289 return ret; 6290 6291 /* 6292 * On some platforms the number of active planes affects 6293 * the planes' minimum cdclk calculation. Add such planes 6294 * to the state before we compute the minimum cdclk. 6295 */ 6296 if (!active_planes_affects_min_cdclk(dev_priv)) 6297 continue; 6298 6299 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 6300 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 6301 6302 if (hweight8(old_active_planes) == hweight8(new_active_planes)) 6303 continue; 6304 6305 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes); 6306 if (ret) 6307 return ret; 6308 } 6309 6310 return 0; 6311 } 6312 6313 static int intel_atomic_check_crtcs(struct intel_atomic_state *state) 6314 { 6315 struct intel_crtc_state *crtc_state; 6316 struct intel_crtc *crtc; 6317 int i; 6318 6319 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6320 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 6321 int ret; 6322 6323 ret = intel_crtc_atomic_check(state, crtc); 6324 if (ret) { 6325 drm_dbg_atomic(&i915->drm, 6326 "[CRTC:%d:%s] atomic driver check failed\n", 6327 crtc->base.base.id, crtc->base.name); 6328 return ret; 6329 } 6330 } 6331 6332 return 0; 6333 } 6334 6335 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, 6336 u8 transcoders) 6337 { 6338 const struct intel_crtc_state *new_crtc_state; 6339 struct intel_crtc *crtc; 6340 int i; 6341 6342 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6343 if (new_crtc_state->hw.enable && 6344 transcoders & BIT(new_crtc_state->cpu_transcoder) && 6345 intel_crtc_needs_modeset(new_crtc_state)) 6346 return true; 6347 } 6348 6349 return false; 6350 } 6351 6352 static bool intel_pipes_need_modeset(struct intel_atomic_state *state, 6353 u8 pipes) 6354 { 6355 const struct intel_crtc_state *new_crtc_state; 6356 struct intel_crtc *crtc; 6357 int i; 6358 6359 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6360 if (new_crtc_state->hw.enable && 6361 pipes & BIT(crtc->pipe) && 6362 intel_crtc_needs_modeset(new_crtc_state)) 6363 return true; 6364 } 6365 6366 return false; 6367 } 6368 6369 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state, 6370 struct intel_crtc *master_crtc) 6371 { 6372 struct drm_i915_private *i915 = to_i915(state->base.dev); 6373 struct intel_crtc_state *master_crtc_state = 6374 intel_atomic_get_new_crtc_state(state, master_crtc); 6375 struct intel_crtc *slave_crtc; 6376 6377 if (!master_crtc_state->bigjoiner_pipes) 6378 return 0; 6379 6380 /* sanity check */ 6381 if (drm_WARN_ON(&i915->drm, 6382 master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state))) 6383 return -EINVAL; 6384 6385 if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) { 6386 drm_dbg_kms(&i915->drm, 6387 "[CRTC:%d:%s] Cannot act as big joiner master " 6388 "(need 0x%x as pipes, only 0x%x possible)\n", 6389 master_crtc->base.base.id, master_crtc->base.name, 6390 master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915)); 6391 return -EINVAL; 6392 } 6393 6394 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 6395 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 6396 struct intel_crtc_state *slave_crtc_state; 6397 int ret; 6398 6399 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc); 6400 if (IS_ERR(slave_crtc_state)) 6401 return PTR_ERR(slave_crtc_state); 6402 6403 /* master being enabled, slave was already configured? */ 6404 if (slave_crtc_state->uapi.enable) { 6405 drm_dbg_kms(&i915->drm, 6406 "[CRTC:%d:%s] Slave is enabled as normal CRTC, but " 6407 "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n", 6408 slave_crtc->base.base.id, slave_crtc->base.name, 6409 master_crtc->base.base.id, master_crtc->base.name); 6410 return -EINVAL; 6411 } 6412 6413 /* 6414 * The state copy logic assumes the master crtc gets processed 6415 * before the slave crtc during the main compute_config loop. 6416 * This works because the crtcs are created in pipe order, 6417 * and the hardware requires master pipe < slave pipe as well. 6418 * Should that change we need to rethink the logic. 6419 */ 6420 if (WARN_ON(drm_crtc_index(&master_crtc->base) > 6421 drm_crtc_index(&slave_crtc->base))) 6422 return -EINVAL; 6423 6424 drm_dbg_kms(&i915->drm, 6425 "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n", 6426 slave_crtc->base.base.id, slave_crtc->base.name, 6427 master_crtc->base.base.id, master_crtc->base.name); 6428 6429 slave_crtc_state->bigjoiner_pipes = 6430 master_crtc_state->bigjoiner_pipes; 6431 6432 ret = copy_bigjoiner_crtc_state_modeset(state, slave_crtc); 6433 if (ret) 6434 return ret; 6435 } 6436 6437 return 0; 6438 } 6439 6440 static void kill_bigjoiner_slave(struct intel_atomic_state *state, 6441 struct intel_crtc *master_crtc) 6442 { 6443 struct drm_i915_private *i915 = to_i915(state->base.dev); 6444 struct intel_crtc_state *master_crtc_state = 6445 intel_atomic_get_new_crtc_state(state, master_crtc); 6446 struct intel_crtc *slave_crtc; 6447 6448 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 6449 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 6450 struct intel_crtc_state *slave_crtc_state = 6451 intel_atomic_get_new_crtc_state(state, slave_crtc); 6452 6453 slave_crtc_state->bigjoiner_pipes = 0; 6454 6455 intel_crtc_copy_uapi_to_hw_state_modeset(state, slave_crtc); 6456 } 6457 6458 master_crtc_state->bigjoiner_pipes = 0; 6459 } 6460 6461 /** 6462 * DOC: asynchronous flip implementation 6463 * 6464 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC 6465 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL. 6466 * Correspondingly, support is currently added for primary plane only. 6467 * 6468 * Async flip can only change the plane surface address, so anything else 6469 * changing is rejected from the intel_async_flip_check_hw() function. 6470 * Once this check is cleared, flip done interrupt is enabled using 6471 * the intel_crtc_enable_flip_done() function. 6472 * 6473 * As soon as the surface address register is written, flip done interrupt is 6474 * generated and the requested events are sent to the usersapce in the interrupt 6475 * handler itself. The timestamp and sequence sent during the flip done event 6476 * correspond to the last vblank and have no relation to the actual time when 6477 * the flip done event was sent. 6478 */ 6479 static int intel_async_flip_check_uapi(struct intel_atomic_state *state, 6480 struct intel_crtc *crtc) 6481 { 6482 struct drm_i915_private *i915 = to_i915(state->base.dev); 6483 const struct intel_crtc_state *new_crtc_state = 6484 intel_atomic_get_new_crtc_state(state, crtc); 6485 const struct intel_plane_state *old_plane_state; 6486 struct intel_plane_state *new_plane_state; 6487 struct intel_plane *plane; 6488 int i; 6489 6490 if (!new_crtc_state->uapi.async_flip) 6491 return 0; 6492 6493 if (!new_crtc_state->uapi.active) { 6494 drm_dbg_kms(&i915->drm, 6495 "[CRTC:%d:%s] not active\n", 6496 crtc->base.base.id, crtc->base.name); 6497 return -EINVAL; 6498 } 6499 6500 if (intel_crtc_needs_modeset(new_crtc_state)) { 6501 drm_dbg_kms(&i915->drm, 6502 "[CRTC:%d:%s] modeset required\n", 6503 crtc->base.base.id, crtc->base.name); 6504 return -EINVAL; 6505 } 6506 6507 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 6508 new_plane_state, i) { 6509 if (plane->pipe != crtc->pipe) 6510 continue; 6511 6512 /* 6513 * TODO: Async flip is only supported through the page flip IOCTL 6514 * as of now. So support currently added for primary plane only. 6515 * Support for other planes on platforms on which supports 6516 * this(vlv/chv and icl+) should be added when async flip is 6517 * enabled in the atomic IOCTL path. 6518 */ 6519 if (!plane->async_flip) { 6520 drm_dbg_kms(&i915->drm, 6521 "[PLANE:%d:%s] async flip not supported\n", 6522 plane->base.base.id, plane->base.name); 6523 return -EINVAL; 6524 } 6525 6526 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) { 6527 drm_dbg_kms(&i915->drm, 6528 "[PLANE:%d:%s] no old or new framebuffer\n", 6529 plane->base.base.id, plane->base.name); 6530 return -EINVAL; 6531 } 6532 } 6533 6534 return 0; 6535 } 6536 6537 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc) 6538 { 6539 struct drm_i915_private *i915 = to_i915(state->base.dev); 6540 const struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6541 const struct intel_plane_state *new_plane_state, *old_plane_state; 6542 struct intel_plane *plane; 6543 int i; 6544 6545 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 6546 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6547 6548 if (!new_crtc_state->uapi.async_flip) 6549 return 0; 6550 6551 if (!new_crtc_state->hw.active) { 6552 drm_dbg_kms(&i915->drm, 6553 "[CRTC:%d:%s] not active\n", 6554 crtc->base.base.id, crtc->base.name); 6555 return -EINVAL; 6556 } 6557 6558 if (intel_crtc_needs_modeset(new_crtc_state)) { 6559 drm_dbg_kms(&i915->drm, 6560 "[CRTC:%d:%s] modeset required\n", 6561 crtc->base.base.id, crtc->base.name); 6562 return -EINVAL; 6563 } 6564 6565 if (old_crtc_state->active_planes != new_crtc_state->active_planes) { 6566 drm_dbg_kms(&i915->drm, 6567 "[CRTC:%d:%s] Active planes cannot be in async flip\n", 6568 crtc->base.base.id, crtc->base.name); 6569 return -EINVAL; 6570 } 6571 6572 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 6573 new_plane_state, i) { 6574 if (plane->pipe != crtc->pipe) 6575 continue; 6576 6577 /* 6578 * Only async flip capable planes should be in the state 6579 * if we're really about to ask the hardware to perform 6580 * an async flip. We should never get this far otherwise. 6581 */ 6582 if (drm_WARN_ON(&i915->drm, 6583 new_crtc_state->do_async_flip && !plane->async_flip)) 6584 return -EINVAL; 6585 6586 /* 6587 * Only check async flip capable planes other planes 6588 * may be involved in the initial commit due to 6589 * the wm0/ddb optimization. 6590 * 6591 * TODO maybe should track which planes actually 6592 * were requested to do the async flip... 6593 */ 6594 if (!plane->async_flip) 6595 continue; 6596 6597 /* 6598 * FIXME: This check is kept generic for all platforms. 6599 * Need to verify this for all gen9 platforms to enable 6600 * this selectively if required. 6601 */ 6602 switch (new_plane_state->hw.fb->modifier) { 6603 case I915_FORMAT_MOD_X_TILED: 6604 case I915_FORMAT_MOD_Y_TILED: 6605 case I915_FORMAT_MOD_Yf_TILED: 6606 case I915_FORMAT_MOD_4_TILED: 6607 break; 6608 default: 6609 drm_dbg_kms(&i915->drm, 6610 "[PLANE:%d:%s] Modifier does not support async flips\n", 6611 plane->base.base.id, plane->base.name); 6612 return -EINVAL; 6613 } 6614 6615 if (new_plane_state->hw.fb->format->num_planes > 1) { 6616 drm_dbg_kms(&i915->drm, 6617 "[PLANE:%d:%s] Planar formats do not support async flips\n", 6618 plane->base.base.id, plane->base.name); 6619 return -EINVAL; 6620 } 6621 6622 if (old_plane_state->view.color_plane[0].mapping_stride != 6623 new_plane_state->view.color_plane[0].mapping_stride) { 6624 drm_dbg_kms(&i915->drm, 6625 "[PLANE:%d:%s] Stride cannot be changed in async flip\n", 6626 plane->base.base.id, plane->base.name); 6627 return -EINVAL; 6628 } 6629 6630 if (old_plane_state->hw.fb->modifier != 6631 new_plane_state->hw.fb->modifier) { 6632 drm_dbg_kms(&i915->drm, 6633 "[PLANE:%d:%s] Modifier cannot be changed in async flip\n", 6634 plane->base.base.id, plane->base.name); 6635 return -EINVAL; 6636 } 6637 6638 if (old_plane_state->hw.fb->format != 6639 new_plane_state->hw.fb->format) { 6640 drm_dbg_kms(&i915->drm, 6641 "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n", 6642 plane->base.base.id, plane->base.name); 6643 return -EINVAL; 6644 } 6645 6646 if (old_plane_state->hw.rotation != 6647 new_plane_state->hw.rotation) { 6648 drm_dbg_kms(&i915->drm, 6649 "[PLANE:%d:%s] Rotation cannot be changed in async flip\n", 6650 plane->base.base.id, plane->base.name); 6651 return -EINVAL; 6652 } 6653 6654 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) || 6655 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) { 6656 drm_dbg_kms(&i915->drm, 6657 "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n", 6658 plane->base.base.id, plane->base.name); 6659 return -EINVAL; 6660 } 6661 6662 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) { 6663 drm_dbg_kms(&i915->drm, 6664 "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n", 6665 plane->base.base.id, plane->base.name); 6666 return -EINVAL; 6667 } 6668 6669 if (old_plane_state->hw.pixel_blend_mode != 6670 new_plane_state->hw.pixel_blend_mode) { 6671 drm_dbg_kms(&i915->drm, 6672 "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n", 6673 plane->base.base.id, plane->base.name); 6674 return -EINVAL; 6675 } 6676 6677 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) { 6678 drm_dbg_kms(&i915->drm, 6679 "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n", 6680 plane->base.base.id, plane->base.name); 6681 return -EINVAL; 6682 } 6683 6684 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) { 6685 drm_dbg_kms(&i915->drm, 6686 "[PLANE:%d:%s] Color range cannot be changed in async flip\n", 6687 plane->base.base.id, plane->base.name); 6688 return -EINVAL; 6689 } 6690 6691 /* plane decryption is allow to change only in synchronous flips */ 6692 if (old_plane_state->decrypt != new_plane_state->decrypt) { 6693 drm_dbg_kms(&i915->drm, 6694 "[PLANE:%d:%s] Decryption cannot be changed in async flip\n", 6695 plane->base.base.id, plane->base.name); 6696 return -EINVAL; 6697 } 6698 } 6699 6700 return 0; 6701 } 6702 6703 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state) 6704 { 6705 struct drm_i915_private *i915 = to_i915(state->base.dev); 6706 struct intel_crtc_state *crtc_state; 6707 struct intel_crtc *crtc; 6708 u8 affected_pipes = 0; 6709 u8 modeset_pipes = 0; 6710 int i; 6711 6712 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6713 affected_pipes |= crtc_state->bigjoiner_pipes; 6714 if (intel_crtc_needs_modeset(crtc_state)) 6715 modeset_pipes |= crtc_state->bigjoiner_pipes; 6716 } 6717 6718 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) { 6719 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6720 if (IS_ERR(crtc_state)) 6721 return PTR_ERR(crtc_state); 6722 } 6723 6724 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) { 6725 int ret; 6726 6727 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6728 6729 crtc_state->uapi.mode_changed = true; 6730 6731 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); 6732 if (ret) 6733 return ret; 6734 6735 ret = intel_atomic_add_affected_planes(state, crtc); 6736 if (ret) 6737 return ret; 6738 } 6739 6740 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6741 /* Kill old bigjoiner link, we may re-establish afterwards */ 6742 if (intel_crtc_needs_modeset(crtc_state) && 6743 intel_crtc_is_bigjoiner_master(crtc_state)) 6744 kill_bigjoiner_slave(state, crtc); 6745 } 6746 6747 return 0; 6748 } 6749 6750 /** 6751 * intel_atomic_check - validate state object 6752 * @dev: drm device 6753 * @_state: state to validate 6754 */ 6755 static int intel_atomic_check(struct drm_device *dev, 6756 struct drm_atomic_state *_state) 6757 { 6758 struct drm_i915_private *dev_priv = to_i915(dev); 6759 struct intel_atomic_state *state = to_intel_atomic_state(_state); 6760 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6761 struct intel_crtc *crtc; 6762 int ret, i; 6763 bool any_ms = false; 6764 6765 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6766 new_crtc_state, i) { 6767 if (new_crtc_state->inherited != old_crtc_state->inherited) 6768 new_crtc_state->uapi.mode_changed = true; 6769 6770 if (new_crtc_state->uapi.scaling_filter != 6771 old_crtc_state->uapi.scaling_filter) 6772 new_crtc_state->uapi.mode_changed = true; 6773 } 6774 6775 intel_vrr_check_modeset(state); 6776 6777 ret = drm_atomic_helper_check_modeset(dev, &state->base); 6778 if (ret) 6779 goto fail; 6780 6781 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6782 ret = intel_async_flip_check_uapi(state, crtc); 6783 if (ret) 6784 return ret; 6785 } 6786 6787 ret = intel_bigjoiner_add_affected_crtcs(state); 6788 if (ret) 6789 goto fail; 6790 6791 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6792 new_crtc_state, i) { 6793 if (!intel_crtc_needs_modeset(new_crtc_state)) { 6794 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 6795 copy_bigjoiner_crtc_state_nomodeset(state, crtc); 6796 else 6797 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 6798 continue; 6799 } 6800 6801 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) { 6802 drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable); 6803 continue; 6804 } 6805 6806 ret = intel_crtc_prepare_cleared_state(state, crtc); 6807 if (ret) 6808 goto fail; 6809 6810 if (!new_crtc_state->hw.enable) 6811 continue; 6812 6813 ret = intel_modeset_pipe_config(state, crtc); 6814 if (ret) 6815 goto fail; 6816 6817 ret = intel_atomic_check_bigjoiner(state, crtc); 6818 if (ret) 6819 goto fail; 6820 } 6821 6822 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6823 new_crtc_state, i) { 6824 if (!intel_crtc_needs_modeset(new_crtc_state)) 6825 continue; 6826 6827 ret = intel_modeset_pipe_config_late(state, crtc); 6828 if (ret) 6829 goto fail; 6830 6831 intel_crtc_check_fastset(old_crtc_state, new_crtc_state); 6832 } 6833 6834 /** 6835 * Check if fastset is allowed by external dependencies like other 6836 * pipes and transcoders. 6837 * 6838 * Right now it only forces a fullmodeset when the MST master 6839 * transcoder did not changed but the pipe of the master transcoder 6840 * needs a fullmodeset so all slaves also needs to do a fullmodeset or 6841 * in case of port synced crtcs, if one of the synced crtcs 6842 * needs a full modeset, all other synced crtcs should be 6843 * forced a full modeset. 6844 */ 6845 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6846 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state)) 6847 continue; 6848 6849 if (intel_dp_mst_is_slave_trans(new_crtc_state)) { 6850 enum transcoder master = new_crtc_state->mst_master_transcoder; 6851 6852 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) { 6853 new_crtc_state->uapi.mode_changed = true; 6854 new_crtc_state->update_pipe = false; 6855 } 6856 } 6857 6858 if (is_trans_port_sync_mode(new_crtc_state)) { 6859 u8 trans = new_crtc_state->sync_mode_slaves_mask; 6860 6861 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER) 6862 trans |= BIT(new_crtc_state->master_transcoder); 6863 6864 if (intel_cpu_transcoders_need_modeset(state, trans)) { 6865 new_crtc_state->uapi.mode_changed = true; 6866 new_crtc_state->update_pipe = false; 6867 } 6868 } 6869 6870 if (new_crtc_state->bigjoiner_pipes) { 6871 if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) { 6872 new_crtc_state->uapi.mode_changed = true; 6873 new_crtc_state->update_pipe = false; 6874 } 6875 } 6876 } 6877 6878 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6879 new_crtc_state, i) { 6880 if (intel_crtc_needs_modeset(new_crtc_state)) { 6881 any_ms = true; 6882 continue; 6883 } 6884 6885 if (!new_crtc_state->update_pipe) 6886 continue; 6887 6888 intel_crtc_copy_fastset(old_crtc_state, new_crtc_state); 6889 } 6890 6891 if (any_ms && !check_digital_port_conflicts(state)) { 6892 drm_dbg_kms(&dev_priv->drm, 6893 "rejecting conflicting digital port configuration\n"); 6894 ret = -EINVAL; 6895 goto fail; 6896 } 6897 6898 ret = drm_dp_mst_atomic_check(&state->base); 6899 if (ret) 6900 goto fail; 6901 6902 ret = intel_atomic_check_planes(state); 6903 if (ret) 6904 goto fail; 6905 6906 ret = intel_compute_global_watermarks(state); 6907 if (ret) 6908 goto fail; 6909 6910 ret = intel_bw_atomic_check(state); 6911 if (ret) 6912 goto fail; 6913 6914 ret = intel_cdclk_atomic_check(state, &any_ms); 6915 if (ret) 6916 goto fail; 6917 6918 if (intel_any_crtc_needs_modeset(state)) 6919 any_ms = true; 6920 6921 if (any_ms) { 6922 ret = intel_modeset_checks(state); 6923 if (ret) 6924 goto fail; 6925 6926 ret = intel_modeset_calc_cdclk(state); 6927 if (ret) 6928 return ret; 6929 6930 intel_modeset_clear_plls(state); 6931 } 6932 6933 ret = intel_atomic_check_crtcs(state); 6934 if (ret) 6935 goto fail; 6936 6937 ret = intel_fbc_atomic_check(state); 6938 if (ret) 6939 goto fail; 6940 6941 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6942 new_crtc_state, i) { 6943 ret = intel_async_flip_check_hw(state, crtc); 6944 if (ret) 6945 goto fail; 6946 6947 if (!intel_crtc_needs_modeset(new_crtc_state) && 6948 !new_crtc_state->update_pipe) 6949 continue; 6950 6951 intel_crtc_state_dump(new_crtc_state, state, 6952 intel_crtc_needs_modeset(new_crtc_state) ? 6953 "modeset" : "fastset"); 6954 } 6955 6956 return 0; 6957 6958 fail: 6959 if (ret == -EDEADLK) 6960 return ret; 6961 6962 /* 6963 * FIXME would probably be nice to know which crtc specifically 6964 * caused the failure, in cases where we can pinpoint it. 6965 */ 6966 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6967 new_crtc_state, i) 6968 intel_crtc_state_dump(new_crtc_state, state, "failed"); 6969 6970 return ret; 6971 } 6972 6973 static int intel_atomic_prepare_commit(struct intel_atomic_state *state) 6974 { 6975 struct intel_crtc_state *crtc_state; 6976 struct intel_crtc *crtc; 6977 int i, ret; 6978 6979 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base); 6980 if (ret < 0) 6981 return ret; 6982 6983 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6984 bool mode_changed = intel_crtc_needs_modeset(crtc_state); 6985 6986 if (mode_changed || crtc_state->update_pipe || 6987 crtc_state->uapi.color_mgmt_changed) { 6988 intel_dsb_prepare(crtc_state); 6989 } 6990 } 6991 6992 return 0; 6993 } 6994 6995 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 6996 struct intel_crtc_state *crtc_state) 6997 { 6998 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6999 7000 if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes) 7001 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 7002 7003 if (crtc_state->has_pch_encoder) { 7004 enum pipe pch_transcoder = 7005 intel_crtc_pch_transcoder(crtc); 7006 7007 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true); 7008 } 7009 } 7010 7011 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, 7012 const struct intel_crtc_state *new_crtc_state) 7013 { 7014 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 7015 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 7016 7017 /* 7018 * Update pipe size and adjust fitter if needed: the reason for this is 7019 * that in compute_mode_changes we check the native mode (not the pfit 7020 * mode) to see if we can flip rather than do a full mode set. In the 7021 * fastboot case, we'll flip, but if we don't update the pipesrc and 7022 * pfit state, we'll end up with a big fb scanned out into the wrong 7023 * sized surface. 7024 */ 7025 intel_set_pipe_src_size(new_crtc_state); 7026 7027 /* on skylake this is done by detaching scalers */ 7028 if (DISPLAY_VER(dev_priv) >= 9) { 7029 if (new_crtc_state->pch_pfit.enabled) 7030 skl_pfit_enable(new_crtc_state); 7031 } else if (HAS_PCH_SPLIT(dev_priv)) { 7032 if (new_crtc_state->pch_pfit.enabled) 7033 ilk_pfit_enable(new_crtc_state); 7034 else if (old_crtc_state->pch_pfit.enabled) 7035 ilk_pfit_disable(old_crtc_state); 7036 } 7037 7038 /* 7039 * The register is supposedly single buffered so perhaps 7040 * not 100% correct to do this here. But SKL+ calculate 7041 * this based on the adjust pixel rate so pfit changes do 7042 * affect it and so it must be updated for fastsets. 7043 * HSW/BDW only really need this here for fastboot, after 7044 * that the value should not change without a full modeset. 7045 */ 7046 if (DISPLAY_VER(dev_priv) >= 9 || 7047 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 7048 hsw_set_linetime_wm(new_crtc_state); 7049 } 7050 7051 static void commit_pipe_pre_planes(struct intel_atomic_state *state, 7052 struct intel_crtc *crtc) 7053 { 7054 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7055 const struct intel_crtc_state *old_crtc_state = 7056 intel_atomic_get_old_crtc_state(state, crtc); 7057 const struct intel_crtc_state *new_crtc_state = 7058 intel_atomic_get_new_crtc_state(state, crtc); 7059 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 7060 7061 /* 7062 * During modesets pipe configuration was programmed as the 7063 * CRTC was enabled. 7064 */ 7065 if (!modeset) { 7066 if (new_crtc_state->uapi.color_mgmt_changed || 7067 new_crtc_state->update_pipe) 7068 intel_color_commit_arm(new_crtc_state); 7069 7070 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 7071 bdw_set_pipemisc(new_crtc_state); 7072 7073 if (new_crtc_state->update_pipe) 7074 intel_pipe_fastset(old_crtc_state, new_crtc_state); 7075 } 7076 7077 intel_psr2_program_trans_man_trk_ctl(new_crtc_state); 7078 7079 intel_atomic_update_watermarks(state, crtc); 7080 } 7081 7082 static void commit_pipe_post_planes(struct intel_atomic_state *state, 7083 struct intel_crtc *crtc) 7084 { 7085 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7086 const struct intel_crtc_state *new_crtc_state = 7087 intel_atomic_get_new_crtc_state(state, crtc); 7088 7089 /* 7090 * Disable the scaler(s) after the plane(s) so that we don't 7091 * get a catastrophic underrun even if the two operations 7092 * end up happening in two different frames. 7093 */ 7094 if (DISPLAY_VER(dev_priv) >= 9 && 7095 !intel_crtc_needs_modeset(new_crtc_state)) 7096 skl_detach_scalers(new_crtc_state); 7097 } 7098 7099 static void intel_enable_crtc(struct intel_atomic_state *state, 7100 struct intel_crtc *crtc) 7101 { 7102 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7103 const struct intel_crtc_state *new_crtc_state = 7104 intel_atomic_get_new_crtc_state(state, crtc); 7105 7106 if (!intel_crtc_needs_modeset(new_crtc_state)) 7107 return; 7108 7109 intel_crtc_update_active_timings(new_crtc_state); 7110 7111 dev_priv->display->crtc_enable(state, crtc); 7112 7113 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 7114 return; 7115 7116 /* vblanks work again, re-enable pipe CRC. */ 7117 intel_crtc_enable_pipe_crc(crtc); 7118 } 7119 7120 static void intel_update_crtc(struct intel_atomic_state *state, 7121 struct intel_crtc *crtc) 7122 { 7123 struct drm_i915_private *i915 = to_i915(state->base.dev); 7124 const struct intel_crtc_state *old_crtc_state = 7125 intel_atomic_get_old_crtc_state(state, crtc); 7126 struct intel_crtc_state *new_crtc_state = 7127 intel_atomic_get_new_crtc_state(state, crtc); 7128 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 7129 7130 if (!modeset) { 7131 if (new_crtc_state->preload_luts && 7132 (new_crtc_state->uapi.color_mgmt_changed || 7133 new_crtc_state->update_pipe)) 7134 intel_color_load_luts(new_crtc_state); 7135 7136 intel_pre_plane_update(state, crtc); 7137 7138 if (new_crtc_state->update_pipe) 7139 intel_encoders_update_pipe(state, crtc); 7140 7141 if (DISPLAY_VER(i915) >= 11 && 7142 new_crtc_state->update_pipe) 7143 icl_set_pipe_chicken(new_crtc_state); 7144 } 7145 7146 intel_fbc_update(state, crtc); 7147 7148 if (!modeset && 7149 (new_crtc_state->uapi.color_mgmt_changed || 7150 new_crtc_state->update_pipe)) 7151 intel_color_commit_noarm(new_crtc_state); 7152 7153 intel_crtc_planes_update_noarm(state, crtc); 7154 7155 /* Perform vblank evasion around commit operation */ 7156 intel_pipe_update_start(new_crtc_state); 7157 7158 commit_pipe_pre_planes(state, crtc); 7159 7160 intel_crtc_planes_update_arm(state, crtc); 7161 7162 commit_pipe_post_planes(state, crtc); 7163 7164 intel_pipe_update_end(new_crtc_state); 7165 7166 /* 7167 * We usually enable FIFO underrun interrupts as part of the 7168 * CRTC enable sequence during modesets. But when we inherit a 7169 * valid pipe configuration from the BIOS we need to take care 7170 * of enabling them on the CRTC's first fastset. 7171 */ 7172 if (new_crtc_state->update_pipe && !modeset && 7173 old_crtc_state->inherited) 7174 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state); 7175 } 7176 7177 static void intel_old_crtc_state_disables(struct intel_atomic_state *state, 7178 struct intel_crtc_state *old_crtc_state, 7179 struct intel_crtc_state *new_crtc_state, 7180 struct intel_crtc *crtc) 7181 { 7182 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7183 7184 /* 7185 * We need to disable pipe CRC before disabling the pipe, 7186 * or we race against vblank off. 7187 */ 7188 intel_crtc_disable_pipe_crc(crtc); 7189 7190 dev_priv->display->crtc_disable(state, crtc); 7191 crtc->active = false; 7192 intel_fbc_disable(crtc); 7193 intel_disable_shared_dpll(old_crtc_state); 7194 7195 /* FIXME unify this for all platforms */ 7196 if (!new_crtc_state->hw.active && 7197 !HAS_GMCH(dev_priv)) 7198 intel_initial_watermarks(state, crtc); 7199 } 7200 7201 static void intel_commit_modeset_disables(struct intel_atomic_state *state) 7202 { 7203 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 7204 struct intel_crtc *crtc; 7205 u32 handled = 0; 7206 int i; 7207 7208 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7209 new_crtc_state, i) { 7210 if (!intel_crtc_needs_modeset(new_crtc_state)) 7211 continue; 7212 7213 if (!old_crtc_state->hw.active) 7214 continue; 7215 7216 intel_pre_plane_update(state, crtc); 7217 intel_crtc_disable_planes(state, crtc); 7218 } 7219 7220 /* Only disable port sync and MST slaves */ 7221 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7222 new_crtc_state, i) { 7223 if (!intel_crtc_needs_modeset(new_crtc_state)) 7224 continue; 7225 7226 if (!old_crtc_state->hw.active) 7227 continue; 7228 7229 /* In case of Transcoder port Sync master slave CRTCs can be 7230 * assigned in any order and we need to make sure that 7231 * slave CRTCs are disabled first and then master CRTC since 7232 * Slave vblanks are masked till Master Vblanks. 7233 */ 7234 if (!is_trans_port_sync_slave(old_crtc_state) && 7235 !intel_dp_mst_is_slave_trans(old_crtc_state) && 7236 !intel_crtc_is_bigjoiner_slave(old_crtc_state)) 7237 continue; 7238 7239 intel_old_crtc_state_disables(state, old_crtc_state, 7240 new_crtc_state, crtc); 7241 handled |= BIT(crtc->pipe); 7242 } 7243 7244 /* Disable everything else left on */ 7245 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7246 new_crtc_state, i) { 7247 if (!intel_crtc_needs_modeset(new_crtc_state) || 7248 (handled & BIT(crtc->pipe))) 7249 continue; 7250 7251 if (!old_crtc_state->hw.active) 7252 continue; 7253 7254 intel_old_crtc_state_disables(state, old_crtc_state, 7255 new_crtc_state, crtc); 7256 } 7257 } 7258 7259 static void intel_commit_modeset_enables(struct intel_atomic_state *state) 7260 { 7261 struct intel_crtc_state *new_crtc_state; 7262 struct intel_crtc *crtc; 7263 int i; 7264 7265 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7266 if (!new_crtc_state->hw.active) 7267 continue; 7268 7269 intel_enable_crtc(state, crtc); 7270 intel_update_crtc(state, crtc); 7271 } 7272 } 7273 7274 static void skl_commit_modeset_enables(struct intel_atomic_state *state) 7275 { 7276 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7277 struct intel_crtc *crtc; 7278 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7279 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; 7280 u8 update_pipes = 0, modeset_pipes = 0; 7281 int i; 7282 7283 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7284 enum pipe pipe = crtc->pipe; 7285 7286 if (!new_crtc_state->hw.active) 7287 continue; 7288 7289 /* ignore allocations for crtc's that have been turned off. */ 7290 if (!intel_crtc_needs_modeset(new_crtc_state)) { 7291 entries[pipe] = old_crtc_state->wm.skl.ddb; 7292 update_pipes |= BIT(pipe); 7293 } else { 7294 modeset_pipes |= BIT(pipe); 7295 } 7296 } 7297 7298 /* 7299 * Whenever the number of active pipes changes, we need to make sure we 7300 * update the pipes in the right order so that their ddb allocations 7301 * never overlap with each other between CRTC updates. Otherwise we'll 7302 * cause pipe underruns and other bad stuff. 7303 * 7304 * So first lets enable all pipes that do not need a fullmodeset as 7305 * those don't have any external dependency. 7306 */ 7307 while (update_pipes) { 7308 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7309 new_crtc_state, i) { 7310 enum pipe pipe = crtc->pipe; 7311 7312 if ((update_pipes & BIT(pipe)) == 0) 7313 continue; 7314 7315 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 7316 entries, I915_MAX_PIPES, pipe)) 7317 continue; 7318 7319 entries[pipe] = new_crtc_state->wm.skl.ddb; 7320 update_pipes &= ~BIT(pipe); 7321 7322 intel_update_crtc(state, crtc); 7323 7324 /* 7325 * If this is an already active pipe, it's DDB changed, 7326 * and this isn't the last pipe that needs updating 7327 * then we need to wait for a vblank to pass for the 7328 * new ddb allocation to take effect. 7329 */ 7330 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, 7331 &old_crtc_state->wm.skl.ddb) && 7332 (update_pipes | modeset_pipes)) 7333 intel_crtc_wait_for_next_vblank(crtc); 7334 } 7335 } 7336 7337 update_pipes = modeset_pipes; 7338 7339 /* 7340 * Enable all pipes that needs a modeset and do not depends on other 7341 * pipes 7342 */ 7343 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7344 enum pipe pipe = crtc->pipe; 7345 7346 if ((modeset_pipes & BIT(pipe)) == 0) 7347 continue; 7348 7349 if (intel_dp_mst_is_slave_trans(new_crtc_state) || 7350 is_trans_port_sync_master(new_crtc_state) || 7351 intel_crtc_is_bigjoiner_master(new_crtc_state)) 7352 continue; 7353 7354 modeset_pipes &= ~BIT(pipe); 7355 7356 intel_enable_crtc(state, crtc); 7357 } 7358 7359 /* 7360 * Then we enable all remaining pipes that depend on other 7361 * pipes: MST slaves and port sync masters, big joiner master 7362 */ 7363 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7364 enum pipe pipe = crtc->pipe; 7365 7366 if ((modeset_pipes & BIT(pipe)) == 0) 7367 continue; 7368 7369 modeset_pipes &= ~BIT(pipe); 7370 7371 intel_enable_crtc(state, crtc); 7372 } 7373 7374 /* 7375 * Finally we do the plane updates/etc. for all pipes that got enabled. 7376 */ 7377 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7378 enum pipe pipe = crtc->pipe; 7379 7380 if ((update_pipes & BIT(pipe)) == 0) 7381 continue; 7382 7383 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 7384 entries, I915_MAX_PIPES, pipe)); 7385 7386 entries[pipe] = new_crtc_state->wm.skl.ddb; 7387 update_pipes &= ~BIT(pipe); 7388 7389 intel_update_crtc(state, crtc); 7390 } 7391 7392 drm_WARN_ON(&dev_priv->drm, modeset_pipes); 7393 drm_WARN_ON(&dev_priv->drm, update_pipes); 7394 } 7395 7396 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) 7397 { 7398 struct intel_atomic_state *state, *next; 7399 struct llist_node *freed; 7400 7401 freed = llist_del_all(&dev_priv->atomic_helper.free_list); 7402 llist_for_each_entry_safe(state, next, freed, freed) 7403 drm_atomic_state_put(&state->base); 7404 } 7405 7406 static void intel_atomic_helper_free_state_worker(struct work_struct *work) 7407 { 7408 struct drm_i915_private *dev_priv = 7409 container_of(work, typeof(*dev_priv), atomic_helper.free_work); 7410 7411 intel_atomic_helper_free_state(dev_priv); 7412 } 7413 7414 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) 7415 { 7416 struct wait_queue_entry wait_fence, wait_reset; 7417 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); 7418 7419 init_wait_entry(&wait_fence, 0); 7420 init_wait_entry(&wait_reset, 0); 7421 for (;;) { 7422 prepare_to_wait(&intel_state->commit_ready.wait, 7423 &wait_fence, TASK_UNINTERRUPTIBLE); 7424 prepare_to_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 7425 I915_RESET_MODESET), 7426 &wait_reset, TASK_UNINTERRUPTIBLE); 7427 7428 7429 if (i915_sw_fence_done(&intel_state->commit_ready) || 7430 test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags)) 7431 break; 7432 7433 schedule(); 7434 } 7435 finish_wait(&intel_state->commit_ready.wait, &wait_fence); 7436 finish_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 7437 I915_RESET_MODESET), 7438 &wait_reset); 7439 } 7440 7441 static void intel_cleanup_dsbs(struct intel_atomic_state *state) 7442 { 7443 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7444 struct intel_crtc *crtc; 7445 int i; 7446 7447 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7448 new_crtc_state, i) 7449 intel_dsb_cleanup(old_crtc_state); 7450 } 7451 7452 static void intel_atomic_cleanup_work(struct work_struct *work) 7453 { 7454 struct intel_atomic_state *state = 7455 container_of(work, struct intel_atomic_state, base.commit_work); 7456 struct drm_i915_private *i915 = to_i915(state->base.dev); 7457 7458 intel_cleanup_dsbs(state); 7459 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base); 7460 drm_atomic_helper_commit_cleanup_done(&state->base); 7461 drm_atomic_state_put(&state->base); 7462 7463 intel_atomic_helper_free_state(i915); 7464 } 7465 7466 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state) 7467 { 7468 struct drm_i915_private *i915 = to_i915(state->base.dev); 7469 struct intel_plane *plane; 7470 struct intel_plane_state *plane_state; 7471 int i; 7472 7473 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 7474 struct drm_framebuffer *fb = plane_state->hw.fb; 7475 int cc_plane; 7476 int ret; 7477 7478 if (!fb) 7479 continue; 7480 7481 cc_plane = intel_fb_rc_ccs_cc_plane(fb); 7482 if (cc_plane < 0) 7483 continue; 7484 7485 /* 7486 * The layout of the fast clear color value expected by HW 7487 * (the DRM ABI requiring this value to be located in fb at 7488 * offset 0 of cc plane, plane #2 previous generations or 7489 * plane #1 for flat ccs): 7490 * - 4 x 4 bytes per-channel value 7491 * (in surface type specific float/int format provided by the fb user) 7492 * - 8 bytes native color value used by the display 7493 * (converted/written by GPU during a fast clear operation using the 7494 * above per-channel values) 7495 * 7496 * The commit's FB prepare hook already ensured that FB obj is pinned and the 7497 * caller made sure that the object is synced wrt. the related color clear value 7498 * GPU write on it. 7499 */ 7500 ret = i915_gem_object_read_from_page(intel_fb_obj(fb), 7501 fb->offsets[cc_plane] + 16, 7502 &plane_state->ccval, 7503 sizeof(plane_state->ccval)); 7504 /* The above could only fail if the FB obj has an unexpected backing store type. */ 7505 drm_WARN_ON(&i915->drm, ret); 7506 } 7507 } 7508 7509 static void intel_atomic_commit_tail(struct intel_atomic_state *state) 7510 { 7511 struct drm_device *dev = state->base.dev; 7512 struct drm_i915_private *dev_priv = to_i915(dev); 7513 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 7514 struct intel_crtc *crtc; 7515 struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {}; 7516 intel_wakeref_t wakeref = 0; 7517 int i; 7518 7519 intel_atomic_commit_fence_wait(state); 7520 7521 drm_atomic_helper_wait_for_dependencies(&state->base); 7522 7523 if (state->modeset) 7524 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); 7525 7526 intel_atomic_prepare_plane_clear_colors(state); 7527 7528 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7529 new_crtc_state, i) { 7530 if (intel_crtc_needs_modeset(new_crtc_state) || 7531 new_crtc_state->update_pipe) { 7532 intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]); 7533 } 7534 } 7535 7536 intel_commit_modeset_disables(state); 7537 7538 /* FIXME: Eventually get rid of our crtc->config pointer */ 7539 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7540 crtc->config = new_crtc_state; 7541 7542 if (state->modeset) { 7543 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base); 7544 7545 intel_set_cdclk_pre_plane_update(state); 7546 7547 intel_modeset_verify_disabled(dev_priv, state); 7548 } 7549 7550 intel_sagv_pre_plane_update(state); 7551 7552 /* Complete the events for pipes that have now been disabled */ 7553 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7554 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 7555 7556 /* Complete events for now disable pipes here. */ 7557 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) { 7558 spin_lock_irq(&dev->event_lock); 7559 drm_crtc_send_vblank_event(&crtc->base, 7560 new_crtc_state->uapi.event); 7561 spin_unlock_irq(&dev->event_lock); 7562 7563 new_crtc_state->uapi.event = NULL; 7564 } 7565 } 7566 7567 intel_encoders_update_prepare(state); 7568 7569 intel_dbuf_pre_plane_update(state); 7570 intel_mbus_dbox_update(state); 7571 7572 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7573 if (new_crtc_state->do_async_flip) 7574 intel_crtc_enable_flip_done(state, crtc); 7575 } 7576 7577 /* Now enable the clocks, plane, pipe, and connectors that we set up. */ 7578 dev_priv->display->commit_modeset_enables(state); 7579 7580 intel_encoders_update_complete(state); 7581 7582 if (state->modeset) 7583 intel_set_cdclk_post_plane_update(state); 7584 7585 intel_wait_for_vblank_workers(state); 7586 7587 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here 7588 * already, but still need the state for the delayed optimization. To 7589 * fix this: 7590 * - wrap the optimization/post_plane_update stuff into a per-crtc work. 7591 * - schedule that vblank worker _before_ calling hw_done 7592 * - at the start of commit_tail, cancel it _synchrously 7593 * - switch over to the vblank wait helper in the core after that since 7594 * we don't need out special handling any more. 7595 */ 7596 drm_atomic_helper_wait_for_flip_done(dev, &state->base); 7597 7598 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7599 if (new_crtc_state->do_async_flip) 7600 intel_crtc_disable_flip_done(state, crtc); 7601 } 7602 7603 /* 7604 * Now that the vblank has passed, we can go ahead and program the 7605 * optimal watermarks on platforms that need two-step watermark 7606 * programming. 7607 * 7608 * TODO: Move this (and other cleanup) to an async worker eventually. 7609 */ 7610 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7611 new_crtc_state, i) { 7612 /* 7613 * Gen2 reports pipe underruns whenever all planes are disabled. 7614 * So re-enable underrun reporting after some planes get enabled. 7615 * 7616 * We do this before .optimize_watermarks() so that we have a 7617 * chance of catching underruns with the intermediate watermarks 7618 * vs. the new plane configuration. 7619 */ 7620 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state)) 7621 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 7622 7623 intel_optimize_watermarks(state, crtc); 7624 } 7625 7626 intel_dbuf_post_plane_update(state); 7627 intel_psr_post_plane_update(state); 7628 7629 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7630 intel_post_plane_update(state, crtc); 7631 7632 intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]); 7633 7634 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state); 7635 7636 /* 7637 * DSB cleanup is done in cleanup_work aligning with framebuffer 7638 * cleanup. So copy and reset the dsb structure to sync with 7639 * commit_done and later do dsb cleanup in cleanup_work. 7640 */ 7641 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb); 7642 } 7643 7644 /* Underruns don't always raise interrupts, so check manually */ 7645 intel_check_cpu_fifo_underruns(dev_priv); 7646 intel_check_pch_fifo_underruns(dev_priv); 7647 7648 if (state->modeset) 7649 intel_verify_planes(state); 7650 7651 intel_sagv_post_plane_update(state); 7652 7653 drm_atomic_helper_commit_hw_done(&state->base); 7654 7655 if (state->modeset) { 7656 /* As one of the primary mmio accessors, KMS has a high 7657 * likelihood of triggering bugs in unclaimed access. After we 7658 * finish modesetting, see if an error has been flagged, and if 7659 * so enable debugging for the next modeset - and hope we catch 7660 * the culprit. 7661 */ 7662 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); 7663 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref); 7664 } 7665 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7666 7667 /* 7668 * Defer the cleanup of the old state to a separate worker to not 7669 * impede the current task (userspace for blocking modesets) that 7670 * are executed inline. For out-of-line asynchronous modesets/flips, 7671 * deferring to a new worker seems overkill, but we would place a 7672 * schedule point (cond_resched()) here anyway to keep latencies 7673 * down. 7674 */ 7675 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work); 7676 queue_work(system_highpri_wq, &state->base.commit_work); 7677 } 7678 7679 static void intel_atomic_commit_work(struct work_struct *work) 7680 { 7681 struct intel_atomic_state *state = 7682 container_of(work, struct intel_atomic_state, base.commit_work); 7683 7684 intel_atomic_commit_tail(state); 7685 } 7686 7687 static int 7688 intel_atomic_commit_ready(struct i915_sw_fence *fence, 7689 enum i915_sw_fence_notify notify) 7690 { 7691 struct intel_atomic_state *state = 7692 container_of(fence, struct intel_atomic_state, commit_ready); 7693 7694 switch (notify) { 7695 case FENCE_COMPLETE: 7696 /* we do blocking waits in the worker, nothing to do here */ 7697 break; 7698 case FENCE_FREE: 7699 { 7700 struct intel_atomic_helper *helper = 7701 &to_i915(state->base.dev)->atomic_helper; 7702 7703 if (llist_add(&state->freed, &helper->free_list)) 7704 schedule_work(&helper->free_work); 7705 break; 7706 } 7707 } 7708 7709 return NOTIFY_DONE; 7710 } 7711 7712 static void intel_atomic_track_fbs(struct intel_atomic_state *state) 7713 { 7714 struct intel_plane_state *old_plane_state, *new_plane_state; 7715 struct intel_plane *plane; 7716 int i; 7717 7718 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 7719 new_plane_state, i) 7720 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), 7721 to_intel_frontbuffer(new_plane_state->hw.fb), 7722 plane->frontbuffer_bit); 7723 } 7724 7725 static int intel_atomic_commit(struct drm_device *dev, 7726 struct drm_atomic_state *_state, 7727 bool nonblock) 7728 { 7729 struct intel_atomic_state *state = to_intel_atomic_state(_state); 7730 struct drm_i915_private *dev_priv = to_i915(dev); 7731 int ret = 0; 7732 7733 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 7734 7735 drm_atomic_state_get(&state->base); 7736 i915_sw_fence_init(&state->commit_ready, 7737 intel_atomic_commit_ready); 7738 7739 /* 7740 * The intel_legacy_cursor_update() fast path takes care 7741 * of avoiding the vblank waits for simple cursor 7742 * movement and flips. For cursor on/off and size changes, 7743 * we want to perform the vblank waits so that watermark 7744 * updates happen during the correct frames. Gen9+ have 7745 * double buffered watermarks and so shouldn't need this. 7746 * 7747 * Unset state->legacy_cursor_update before the call to 7748 * drm_atomic_helper_setup_commit() because otherwise 7749 * drm_atomic_helper_wait_for_flip_done() is a noop and 7750 * we get FIFO underruns because we didn't wait 7751 * for vblank. 7752 * 7753 * FIXME doing watermarks and fb cleanup from a vblank worker 7754 * (assuming we had any) would solve these problems. 7755 */ 7756 if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) { 7757 struct intel_crtc_state *new_crtc_state; 7758 struct intel_crtc *crtc; 7759 int i; 7760 7761 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7762 if (new_crtc_state->wm.need_postvbl_update || 7763 new_crtc_state->update_wm_post) 7764 state->base.legacy_cursor_update = false; 7765 } 7766 7767 ret = intel_atomic_prepare_commit(state); 7768 if (ret) { 7769 drm_dbg_atomic(&dev_priv->drm, 7770 "Preparing state failed with %i\n", ret); 7771 i915_sw_fence_commit(&state->commit_ready); 7772 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7773 return ret; 7774 } 7775 7776 ret = drm_atomic_helper_setup_commit(&state->base, nonblock); 7777 if (!ret) 7778 ret = drm_atomic_helper_swap_state(&state->base, true); 7779 if (!ret) 7780 intel_atomic_swap_global_state(state); 7781 7782 if (ret) { 7783 struct intel_crtc_state *new_crtc_state; 7784 struct intel_crtc *crtc; 7785 int i; 7786 7787 i915_sw_fence_commit(&state->commit_ready); 7788 7789 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7790 intel_dsb_cleanup(new_crtc_state); 7791 7792 drm_atomic_helper_cleanup_planes(dev, &state->base); 7793 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7794 return ret; 7795 } 7796 intel_shared_dpll_swap_state(state); 7797 intel_atomic_track_fbs(state); 7798 7799 drm_atomic_state_get(&state->base); 7800 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work); 7801 7802 i915_sw_fence_commit(&state->commit_ready); 7803 if (nonblock && state->modeset) { 7804 queue_work(dev_priv->modeset_wq, &state->base.commit_work); 7805 } else if (nonblock) { 7806 queue_work(dev_priv->flip_wq, &state->base.commit_work); 7807 } else { 7808 if (state->modeset) 7809 flush_workqueue(dev_priv->modeset_wq); 7810 intel_atomic_commit_tail(state); 7811 } 7812 7813 return 0; 7814 } 7815 7816 /** 7817 * intel_plane_destroy - destroy a plane 7818 * @plane: plane to destroy 7819 * 7820 * Common destruction function for all types of planes (primary, cursor, 7821 * sprite). 7822 */ 7823 void intel_plane_destroy(struct drm_plane *plane) 7824 { 7825 drm_plane_cleanup(plane); 7826 kfree(to_intel_plane(plane)); 7827 } 7828 7829 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv) 7830 { 7831 struct intel_plane *plane; 7832 7833 for_each_intel_plane(&dev_priv->drm, plane) { 7834 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, 7835 plane->pipe); 7836 7837 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base); 7838 } 7839 } 7840 7841 7842 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 7843 struct drm_file *file) 7844 { 7845 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; 7846 struct drm_crtc *drmmode_crtc; 7847 struct intel_crtc *crtc; 7848 7849 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id); 7850 if (!drmmode_crtc) 7851 return -ENOENT; 7852 7853 crtc = to_intel_crtc(drmmode_crtc); 7854 pipe_from_crtc_id->pipe = crtc->pipe; 7855 7856 return 0; 7857 } 7858 7859 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder) 7860 { 7861 struct drm_device *dev = encoder->base.dev; 7862 struct intel_encoder *source_encoder; 7863 u32 possible_clones = 0; 7864 7865 for_each_intel_encoder(dev, source_encoder) { 7866 if (encoders_cloneable(encoder, source_encoder)) 7867 possible_clones |= drm_encoder_mask(&source_encoder->base); 7868 } 7869 7870 return possible_clones; 7871 } 7872 7873 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder) 7874 { 7875 struct drm_device *dev = encoder->base.dev; 7876 struct intel_crtc *crtc; 7877 u32 possible_crtcs = 0; 7878 7879 for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask) 7880 possible_crtcs |= drm_crtc_mask(&crtc->base); 7881 7882 return possible_crtcs; 7883 } 7884 7885 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv) 7886 { 7887 if (!IS_MOBILE(dev_priv)) 7888 return false; 7889 7890 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0) 7891 return false; 7892 7893 if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE)) 7894 return false; 7895 7896 return true; 7897 } 7898 7899 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv) 7900 { 7901 if (DISPLAY_VER(dev_priv) >= 9) 7902 return false; 7903 7904 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) 7905 return false; 7906 7907 if (HAS_PCH_LPT_H(dev_priv) && 7908 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) 7909 return false; 7910 7911 /* DDI E can't be used if DDI A requires 4 lanes */ 7912 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 7913 return false; 7914 7915 if (!dev_priv->vbt.int_crt_support) 7916 return false; 7917 7918 return true; 7919 } 7920 7921 static void intel_setup_outputs(struct drm_i915_private *dev_priv) 7922 { 7923 struct intel_encoder *encoder; 7924 bool dpd_is_edp = false; 7925 7926 intel_pps_unlock_regs_wa(dev_priv); 7927 7928 if (!HAS_DISPLAY(dev_priv)) 7929 return; 7930 7931 if (IS_DG2(dev_priv)) { 7932 intel_ddi_init(dev_priv, PORT_A); 7933 intel_ddi_init(dev_priv, PORT_B); 7934 intel_ddi_init(dev_priv, PORT_C); 7935 intel_ddi_init(dev_priv, PORT_D_XELPD); 7936 intel_ddi_init(dev_priv, PORT_TC1); 7937 } else if (IS_ALDERLAKE_P(dev_priv)) { 7938 intel_ddi_init(dev_priv, PORT_A); 7939 intel_ddi_init(dev_priv, PORT_B); 7940 intel_ddi_init(dev_priv, PORT_TC1); 7941 intel_ddi_init(dev_priv, PORT_TC2); 7942 intel_ddi_init(dev_priv, PORT_TC3); 7943 intel_ddi_init(dev_priv, PORT_TC4); 7944 icl_dsi_init(dev_priv); 7945 } else if (IS_ALDERLAKE_S(dev_priv)) { 7946 intel_ddi_init(dev_priv, PORT_A); 7947 intel_ddi_init(dev_priv, PORT_TC1); 7948 intel_ddi_init(dev_priv, PORT_TC2); 7949 intel_ddi_init(dev_priv, PORT_TC3); 7950 intel_ddi_init(dev_priv, PORT_TC4); 7951 } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) { 7952 intel_ddi_init(dev_priv, PORT_A); 7953 intel_ddi_init(dev_priv, PORT_B); 7954 intel_ddi_init(dev_priv, PORT_TC1); 7955 intel_ddi_init(dev_priv, PORT_TC2); 7956 } else if (DISPLAY_VER(dev_priv) >= 12) { 7957 intel_ddi_init(dev_priv, PORT_A); 7958 intel_ddi_init(dev_priv, PORT_B); 7959 intel_ddi_init(dev_priv, PORT_TC1); 7960 intel_ddi_init(dev_priv, PORT_TC2); 7961 intel_ddi_init(dev_priv, PORT_TC3); 7962 intel_ddi_init(dev_priv, PORT_TC4); 7963 intel_ddi_init(dev_priv, PORT_TC5); 7964 intel_ddi_init(dev_priv, PORT_TC6); 7965 icl_dsi_init(dev_priv); 7966 } else if (IS_JSL_EHL(dev_priv)) { 7967 intel_ddi_init(dev_priv, PORT_A); 7968 intel_ddi_init(dev_priv, PORT_B); 7969 intel_ddi_init(dev_priv, PORT_C); 7970 intel_ddi_init(dev_priv, PORT_D); 7971 icl_dsi_init(dev_priv); 7972 } else if (DISPLAY_VER(dev_priv) == 11) { 7973 intel_ddi_init(dev_priv, PORT_A); 7974 intel_ddi_init(dev_priv, PORT_B); 7975 intel_ddi_init(dev_priv, PORT_C); 7976 intel_ddi_init(dev_priv, PORT_D); 7977 intel_ddi_init(dev_priv, PORT_E); 7978 intel_ddi_init(dev_priv, PORT_F); 7979 icl_dsi_init(dev_priv); 7980 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 7981 intel_ddi_init(dev_priv, PORT_A); 7982 intel_ddi_init(dev_priv, PORT_B); 7983 intel_ddi_init(dev_priv, PORT_C); 7984 vlv_dsi_init(dev_priv); 7985 } else if (DISPLAY_VER(dev_priv) >= 9) { 7986 intel_ddi_init(dev_priv, PORT_A); 7987 intel_ddi_init(dev_priv, PORT_B); 7988 intel_ddi_init(dev_priv, PORT_C); 7989 intel_ddi_init(dev_priv, PORT_D); 7990 intel_ddi_init(dev_priv, PORT_E); 7991 } else if (HAS_DDI(dev_priv)) { 7992 u32 found; 7993 7994 if (intel_ddi_crt_present(dev_priv)) 7995 intel_crt_init(dev_priv); 7996 7997 /* Haswell uses DDI functions to detect digital outputs. */ 7998 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 7999 if (found) 8000 intel_ddi_init(dev_priv, PORT_A); 8001 8002 found = intel_de_read(dev_priv, SFUSE_STRAP); 8003 if (found & SFUSE_STRAP_DDIB_DETECTED) 8004 intel_ddi_init(dev_priv, PORT_B); 8005 if (found & SFUSE_STRAP_DDIC_DETECTED) 8006 intel_ddi_init(dev_priv, PORT_C); 8007 if (found & SFUSE_STRAP_DDID_DETECTED) 8008 intel_ddi_init(dev_priv, PORT_D); 8009 if (found & SFUSE_STRAP_DDIF_DETECTED) 8010 intel_ddi_init(dev_priv, PORT_F); 8011 } else if (HAS_PCH_SPLIT(dev_priv)) { 8012 int found; 8013 8014 /* 8015 * intel_edp_init_connector() depends on this completing first, 8016 * to prevent the registration of both eDP and LVDS and the 8017 * incorrect sharing of the PPS. 8018 */ 8019 intel_lvds_init(dev_priv); 8020 intel_crt_init(dev_priv); 8021 8022 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D); 8023 8024 if (ilk_has_edp_a(dev_priv)) 8025 g4x_dp_init(dev_priv, DP_A, PORT_A); 8026 8027 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) { 8028 /* PCH SDVOB multiplex with HDMIB */ 8029 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); 8030 if (!found) 8031 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); 8032 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED)) 8033 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B); 8034 } 8035 8036 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED) 8037 g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); 8038 8039 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED) 8040 g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D); 8041 8042 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED) 8043 g4x_dp_init(dev_priv, PCH_DP_C, PORT_C); 8044 8045 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED) 8046 g4x_dp_init(dev_priv, PCH_DP_D, PORT_D); 8047 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 8048 bool has_edp, has_port; 8049 8050 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support) 8051 intel_crt_init(dev_priv); 8052 8053 /* 8054 * The DP_DETECTED bit is the latched state of the DDC 8055 * SDA pin at boot. However since eDP doesn't require DDC 8056 * (no way to plug in a DP->HDMI dongle) the DDC pins for 8057 * eDP ports may have been muxed to an alternate function. 8058 * Thus we can't rely on the DP_DETECTED bit alone to detect 8059 * eDP ports. Consult the VBT as well as DP_DETECTED to 8060 * detect eDP ports. 8061 * 8062 * Sadly the straps seem to be missing sometimes even for HDMI 8063 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap 8064 * and VBT for the presence of the port. Additionally we can't 8065 * trust the port type the VBT declares as we've seen at least 8066 * HDMI ports that the VBT claim are DP or eDP. 8067 */ 8068 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B); 8069 has_port = intel_bios_is_port_present(dev_priv, PORT_B); 8070 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port) 8071 has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B); 8072 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) 8073 g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); 8074 8075 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C); 8076 has_port = intel_bios_is_port_present(dev_priv, PORT_C); 8077 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port) 8078 has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C); 8079 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) 8080 g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); 8081 8082 if (IS_CHERRYVIEW(dev_priv)) { 8083 /* 8084 * eDP not supported on port D, 8085 * so no need to worry about it 8086 */ 8087 has_port = intel_bios_is_port_present(dev_priv, PORT_D); 8088 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port) 8089 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D); 8090 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port) 8091 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D); 8092 } 8093 8094 vlv_dsi_init(dev_priv); 8095 } else if (IS_PINEVIEW(dev_priv)) { 8096 intel_lvds_init(dev_priv); 8097 intel_crt_init(dev_priv); 8098 } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) { 8099 bool found = false; 8100 8101 if (IS_MOBILE(dev_priv)) 8102 intel_lvds_init(dev_priv); 8103 8104 intel_crt_init(dev_priv); 8105 8106 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 8107 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n"); 8108 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); 8109 if (!found && IS_G4X(dev_priv)) { 8110 drm_dbg_kms(&dev_priv->drm, 8111 "probing HDMI on SDVOB\n"); 8112 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); 8113 } 8114 8115 if (!found && IS_G4X(dev_priv)) 8116 g4x_dp_init(dev_priv, DP_B, PORT_B); 8117 } 8118 8119 /* Before G4X SDVOC doesn't have its own detect register */ 8120 8121 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 8122 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n"); 8123 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); 8124 } 8125 8126 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) { 8127 8128 if (IS_G4X(dev_priv)) { 8129 drm_dbg_kms(&dev_priv->drm, 8130 "probing HDMI on SDVOC\n"); 8131 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); 8132 } 8133 if (IS_G4X(dev_priv)) 8134 g4x_dp_init(dev_priv, DP_C, PORT_C); 8135 } 8136 8137 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED)) 8138 g4x_dp_init(dev_priv, DP_D, PORT_D); 8139 8140 if (SUPPORTS_TV(dev_priv)) 8141 intel_tv_init(dev_priv); 8142 } else if (DISPLAY_VER(dev_priv) == 2) { 8143 if (IS_I85X(dev_priv)) 8144 intel_lvds_init(dev_priv); 8145 8146 intel_crt_init(dev_priv); 8147 intel_dvo_init(dev_priv); 8148 } 8149 8150 for_each_intel_encoder(&dev_priv->drm, encoder) { 8151 encoder->base.possible_crtcs = 8152 intel_encoder_possible_crtcs(encoder); 8153 encoder->base.possible_clones = 8154 intel_encoder_possible_clones(encoder); 8155 } 8156 8157 intel_init_pch_refclk(dev_priv); 8158 8159 drm_helper_move_panel_connectors_to_head(&dev_priv->drm); 8160 } 8161 8162 static enum drm_mode_status 8163 intel_mode_valid(struct drm_device *dev, 8164 const struct drm_display_mode *mode) 8165 { 8166 struct drm_i915_private *dev_priv = to_i915(dev); 8167 int hdisplay_max, htotal_max; 8168 int vdisplay_max, vtotal_max; 8169 8170 /* 8171 * Can't reject DBLSCAN here because Xorg ddxen can add piles 8172 * of DBLSCAN modes to the output's mode list when they detect 8173 * the scaling mode property on the connector. And they don't 8174 * ask the kernel to validate those modes in any way until 8175 * modeset time at which point the client gets a protocol error. 8176 * So in order to not upset those clients we silently ignore the 8177 * DBLSCAN flag on such connectors. For other connectors we will 8178 * reject modes with the DBLSCAN flag in encoder->compute_config(). 8179 * And we always reject DBLSCAN modes in connector->mode_valid() 8180 * as we never want such modes on the connector's mode list. 8181 */ 8182 8183 if (mode->vscan > 1) 8184 return MODE_NO_VSCAN; 8185 8186 if (mode->flags & DRM_MODE_FLAG_HSKEW) 8187 return MODE_H_ILLEGAL; 8188 8189 if (mode->flags & (DRM_MODE_FLAG_CSYNC | 8190 DRM_MODE_FLAG_NCSYNC | 8191 DRM_MODE_FLAG_PCSYNC)) 8192 return MODE_HSYNC; 8193 8194 if (mode->flags & (DRM_MODE_FLAG_BCAST | 8195 DRM_MODE_FLAG_PIXMUX | 8196 DRM_MODE_FLAG_CLKDIV2)) 8197 return MODE_BAD; 8198 8199 /* Transcoder timing limits */ 8200 if (DISPLAY_VER(dev_priv) >= 11) { 8201 hdisplay_max = 16384; 8202 vdisplay_max = 8192; 8203 htotal_max = 16384; 8204 vtotal_max = 8192; 8205 } else if (DISPLAY_VER(dev_priv) >= 9 || 8206 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 8207 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ 8208 vdisplay_max = 4096; 8209 htotal_max = 8192; 8210 vtotal_max = 8192; 8211 } else if (DISPLAY_VER(dev_priv) >= 3) { 8212 hdisplay_max = 4096; 8213 vdisplay_max = 4096; 8214 htotal_max = 8192; 8215 vtotal_max = 8192; 8216 } else { 8217 hdisplay_max = 2048; 8218 vdisplay_max = 2048; 8219 htotal_max = 4096; 8220 vtotal_max = 4096; 8221 } 8222 8223 if (mode->hdisplay > hdisplay_max || 8224 mode->hsync_start > htotal_max || 8225 mode->hsync_end > htotal_max || 8226 mode->htotal > htotal_max) 8227 return MODE_H_ILLEGAL; 8228 8229 if (mode->vdisplay > vdisplay_max || 8230 mode->vsync_start > vtotal_max || 8231 mode->vsync_end > vtotal_max || 8232 mode->vtotal > vtotal_max) 8233 return MODE_V_ILLEGAL; 8234 8235 if (DISPLAY_VER(dev_priv) >= 5) { 8236 if (mode->hdisplay < 64 || 8237 mode->htotal - mode->hdisplay < 32) 8238 return MODE_H_ILLEGAL; 8239 8240 if (mode->vtotal - mode->vdisplay < 5) 8241 return MODE_V_ILLEGAL; 8242 } else { 8243 if (mode->htotal - mode->hdisplay < 32) 8244 return MODE_H_ILLEGAL; 8245 8246 if (mode->vtotal - mode->vdisplay < 3) 8247 return MODE_V_ILLEGAL; 8248 } 8249 8250 /* 8251 * Cantiga+ cannot handle modes with a hsync front porch of 0. 8252 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. 8253 */ 8254 if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) && 8255 mode->hsync_start == mode->hdisplay) 8256 return MODE_H_ILLEGAL; 8257 8258 return MODE_OK; 8259 } 8260 8261 enum drm_mode_status 8262 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 8263 const struct drm_display_mode *mode, 8264 bool bigjoiner) 8265 { 8266 int plane_width_max, plane_height_max; 8267 8268 /* 8269 * intel_mode_valid() should be 8270 * sufficient on older platforms. 8271 */ 8272 if (DISPLAY_VER(dev_priv) < 9) 8273 return MODE_OK; 8274 8275 /* 8276 * Most people will probably want a fullscreen 8277 * plane so let's not advertize modes that are 8278 * too big for that. 8279 */ 8280 if (DISPLAY_VER(dev_priv) >= 11) { 8281 plane_width_max = 5120 << bigjoiner; 8282 plane_height_max = 4320; 8283 } else { 8284 plane_width_max = 5120; 8285 plane_height_max = 4096; 8286 } 8287 8288 if (mode->hdisplay > plane_width_max) 8289 return MODE_H_ILLEGAL; 8290 8291 if (mode->vdisplay > plane_height_max) 8292 return MODE_V_ILLEGAL; 8293 8294 return MODE_OK; 8295 } 8296 8297 static const struct drm_mode_config_funcs intel_mode_funcs = { 8298 .fb_create = intel_user_framebuffer_create, 8299 .get_format_info = intel_fb_get_format_info, 8300 .output_poll_changed = intel_fbdev_output_poll_changed, 8301 .mode_valid = intel_mode_valid, 8302 .atomic_check = intel_atomic_check, 8303 .atomic_commit = intel_atomic_commit, 8304 .atomic_state_alloc = intel_atomic_state_alloc, 8305 .atomic_state_clear = intel_atomic_state_clear, 8306 .atomic_state_free = intel_atomic_state_free, 8307 }; 8308 8309 static const struct drm_i915_display_funcs skl_display_funcs = { 8310 .get_pipe_config = hsw_get_pipe_config, 8311 .crtc_enable = hsw_crtc_enable, 8312 .crtc_disable = hsw_crtc_disable, 8313 .commit_modeset_enables = skl_commit_modeset_enables, 8314 .get_initial_plane_config = skl_get_initial_plane_config, 8315 }; 8316 8317 static const struct drm_i915_display_funcs ddi_display_funcs = { 8318 .get_pipe_config = hsw_get_pipe_config, 8319 .crtc_enable = hsw_crtc_enable, 8320 .crtc_disable = hsw_crtc_disable, 8321 .commit_modeset_enables = intel_commit_modeset_enables, 8322 .get_initial_plane_config = i9xx_get_initial_plane_config, 8323 }; 8324 8325 static const struct drm_i915_display_funcs pch_split_display_funcs = { 8326 .get_pipe_config = ilk_get_pipe_config, 8327 .crtc_enable = ilk_crtc_enable, 8328 .crtc_disable = ilk_crtc_disable, 8329 .commit_modeset_enables = intel_commit_modeset_enables, 8330 .get_initial_plane_config = i9xx_get_initial_plane_config, 8331 }; 8332 8333 static const struct drm_i915_display_funcs vlv_display_funcs = { 8334 .get_pipe_config = i9xx_get_pipe_config, 8335 .crtc_enable = valleyview_crtc_enable, 8336 .crtc_disable = i9xx_crtc_disable, 8337 .commit_modeset_enables = intel_commit_modeset_enables, 8338 .get_initial_plane_config = i9xx_get_initial_plane_config, 8339 }; 8340 8341 static const struct drm_i915_display_funcs i9xx_display_funcs = { 8342 .get_pipe_config = i9xx_get_pipe_config, 8343 .crtc_enable = i9xx_crtc_enable, 8344 .crtc_disable = i9xx_crtc_disable, 8345 .commit_modeset_enables = intel_commit_modeset_enables, 8346 .get_initial_plane_config = i9xx_get_initial_plane_config, 8347 }; 8348 8349 /** 8350 * intel_init_display_hooks - initialize the display modesetting hooks 8351 * @dev_priv: device private 8352 */ 8353 void intel_init_display_hooks(struct drm_i915_private *dev_priv) 8354 { 8355 if (!HAS_DISPLAY(dev_priv)) 8356 return; 8357 8358 intel_init_cdclk_hooks(dev_priv); 8359 intel_audio_hooks_init(dev_priv); 8360 8361 intel_dpll_init_clock_hook(dev_priv); 8362 8363 if (DISPLAY_VER(dev_priv) >= 9) { 8364 dev_priv->display = &skl_display_funcs; 8365 } else if (HAS_DDI(dev_priv)) { 8366 dev_priv->display = &ddi_display_funcs; 8367 } else if (HAS_PCH_SPLIT(dev_priv)) { 8368 dev_priv->display = &pch_split_display_funcs; 8369 } else if (IS_CHERRYVIEW(dev_priv) || 8370 IS_VALLEYVIEW(dev_priv)) { 8371 dev_priv->display = &vlv_display_funcs; 8372 } else { 8373 dev_priv->display = &i9xx_display_funcs; 8374 } 8375 8376 intel_fdi_init_hook(dev_priv); 8377 } 8378 8379 void intel_modeset_init_hw(struct drm_i915_private *i915) 8380 { 8381 struct intel_cdclk_state *cdclk_state; 8382 8383 if (!HAS_DISPLAY(i915)) 8384 return; 8385 8386 cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state); 8387 8388 intel_update_cdclk(i915); 8389 intel_cdclk_dump_config(i915, &i915->cdclk.hw, "Current CDCLK"); 8390 cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw; 8391 } 8392 8393 static int sanitize_watermarks_add_affected(struct drm_atomic_state *state) 8394 { 8395 struct drm_plane *plane; 8396 struct intel_crtc *crtc; 8397 8398 for_each_intel_crtc(state->dev, crtc) { 8399 struct intel_crtc_state *crtc_state; 8400 8401 crtc_state = intel_atomic_get_crtc_state(state, crtc); 8402 if (IS_ERR(crtc_state)) 8403 return PTR_ERR(crtc_state); 8404 8405 if (crtc_state->hw.active) { 8406 /* 8407 * Preserve the inherited flag to avoid 8408 * taking the full modeset path. 8409 */ 8410 crtc_state->inherited = true; 8411 } 8412 } 8413 8414 drm_for_each_plane(plane, state->dev) { 8415 struct drm_plane_state *plane_state; 8416 8417 plane_state = drm_atomic_get_plane_state(state, plane); 8418 if (IS_ERR(plane_state)) 8419 return PTR_ERR(plane_state); 8420 } 8421 8422 return 0; 8423 } 8424 8425 /* 8426 * Calculate what we think the watermarks should be for the state we've read 8427 * out of the hardware and then immediately program those watermarks so that 8428 * we ensure the hardware settings match our internal state. 8429 * 8430 * We can calculate what we think WM's should be by creating a duplicate of the 8431 * current state (which was constructed during hardware readout) and running it 8432 * through the atomic check code to calculate new watermark values in the 8433 * state object. 8434 */ 8435 static void sanitize_watermarks(struct drm_i915_private *dev_priv) 8436 { 8437 struct drm_atomic_state *state; 8438 struct intel_atomic_state *intel_state; 8439 struct intel_crtc *crtc; 8440 struct intel_crtc_state *crtc_state; 8441 struct drm_modeset_acquire_ctx ctx; 8442 int ret; 8443 int i; 8444 8445 /* Only supported on platforms that use atomic watermark design */ 8446 if (!dev_priv->wm_disp->optimize_watermarks) 8447 return; 8448 8449 state = drm_atomic_state_alloc(&dev_priv->drm); 8450 if (drm_WARN_ON(&dev_priv->drm, !state)) 8451 return; 8452 8453 intel_state = to_intel_atomic_state(state); 8454 8455 drm_modeset_acquire_init(&ctx, 0); 8456 8457 retry: 8458 state->acquire_ctx = &ctx; 8459 8460 /* 8461 * Hardware readout is the only time we don't want to calculate 8462 * intermediate watermarks (since we don't trust the current 8463 * watermarks). 8464 */ 8465 if (!HAS_GMCH(dev_priv)) 8466 intel_state->skip_intermediate_wm = true; 8467 8468 ret = sanitize_watermarks_add_affected(state); 8469 if (ret) 8470 goto fail; 8471 8472 ret = intel_atomic_check(&dev_priv->drm, state); 8473 if (ret) 8474 goto fail; 8475 8476 /* Write calculated watermark values back */ 8477 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) { 8478 crtc_state->wm.need_postvbl_update = true; 8479 intel_optimize_watermarks(intel_state, crtc); 8480 8481 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm; 8482 } 8483 8484 fail: 8485 if (ret == -EDEADLK) { 8486 drm_atomic_state_clear(state); 8487 drm_modeset_backoff(&ctx); 8488 goto retry; 8489 } 8490 8491 /* 8492 * If we fail here, it means that the hardware appears to be 8493 * programmed in a way that shouldn't be possible, given our 8494 * understanding of watermark requirements. This might mean a 8495 * mistake in the hardware readout code or a mistake in the 8496 * watermark calculations for a given platform. Raise a WARN 8497 * so that this is noticeable. 8498 * 8499 * If this actually happens, we'll have to just leave the 8500 * BIOS-programmed watermarks untouched and hope for the best. 8501 */ 8502 drm_WARN(&dev_priv->drm, ret, 8503 "Could not determine valid watermarks for inherited state\n"); 8504 8505 drm_atomic_state_put(state); 8506 8507 drm_modeset_drop_locks(&ctx); 8508 drm_modeset_acquire_fini(&ctx); 8509 } 8510 8511 static int intel_initial_commit(struct drm_device *dev) 8512 { 8513 struct drm_atomic_state *state = NULL; 8514 struct drm_modeset_acquire_ctx ctx; 8515 struct intel_crtc *crtc; 8516 int ret = 0; 8517 8518 state = drm_atomic_state_alloc(dev); 8519 if (!state) 8520 return -ENOMEM; 8521 8522 drm_modeset_acquire_init(&ctx, 0); 8523 8524 retry: 8525 state->acquire_ctx = &ctx; 8526 8527 for_each_intel_crtc(dev, crtc) { 8528 struct intel_crtc_state *crtc_state = 8529 intel_atomic_get_crtc_state(state, crtc); 8530 8531 if (IS_ERR(crtc_state)) { 8532 ret = PTR_ERR(crtc_state); 8533 goto out; 8534 } 8535 8536 if (crtc_state->hw.active) { 8537 struct intel_encoder *encoder; 8538 8539 /* 8540 * We've not yet detected sink capabilities 8541 * (audio,infoframes,etc.) and thus we don't want to 8542 * force a full state recomputation yet. We want that to 8543 * happen only for the first real commit from userspace. 8544 * So preserve the inherited flag for the time being. 8545 */ 8546 crtc_state->inherited = true; 8547 8548 ret = drm_atomic_add_affected_planes(state, &crtc->base); 8549 if (ret) 8550 goto out; 8551 8552 /* 8553 * FIXME hack to force a LUT update to avoid the 8554 * plane update forcing the pipe gamma on without 8555 * having a proper LUT loaded. Remove once we 8556 * have readout for pipe gamma enable. 8557 */ 8558 crtc_state->uapi.color_mgmt_changed = true; 8559 8560 for_each_intel_encoder_mask(dev, encoder, 8561 crtc_state->uapi.encoder_mask) { 8562 if (encoder->initial_fastset_check && 8563 !encoder->initial_fastset_check(encoder, crtc_state)) { 8564 ret = drm_atomic_add_affected_connectors(state, 8565 &crtc->base); 8566 if (ret) 8567 goto out; 8568 } 8569 } 8570 } 8571 } 8572 8573 ret = drm_atomic_commit(state); 8574 8575 out: 8576 if (ret == -EDEADLK) { 8577 drm_atomic_state_clear(state); 8578 drm_modeset_backoff(&ctx); 8579 goto retry; 8580 } 8581 8582 drm_atomic_state_put(state); 8583 8584 drm_modeset_drop_locks(&ctx); 8585 drm_modeset_acquire_fini(&ctx); 8586 8587 return ret; 8588 } 8589 8590 static void intel_mode_config_init(struct drm_i915_private *i915) 8591 { 8592 struct drm_mode_config *mode_config = &i915->drm.mode_config; 8593 8594 drm_mode_config_init(&i915->drm); 8595 INIT_LIST_HEAD(&i915->global_obj_list); 8596 8597 mode_config->min_width = 0; 8598 mode_config->min_height = 0; 8599 8600 mode_config->preferred_depth = 24; 8601 mode_config->prefer_shadow = 1; 8602 8603 mode_config->funcs = &intel_mode_funcs; 8604 8605 mode_config->async_page_flip = HAS_ASYNC_FLIPS(i915); 8606 8607 /* 8608 * Maximum framebuffer dimensions, chosen to match 8609 * the maximum render engine surface size on gen4+. 8610 */ 8611 if (DISPLAY_VER(i915) >= 7) { 8612 mode_config->max_width = 16384; 8613 mode_config->max_height = 16384; 8614 } else if (DISPLAY_VER(i915) >= 4) { 8615 mode_config->max_width = 8192; 8616 mode_config->max_height = 8192; 8617 } else if (DISPLAY_VER(i915) == 3) { 8618 mode_config->max_width = 4096; 8619 mode_config->max_height = 4096; 8620 } else { 8621 mode_config->max_width = 2048; 8622 mode_config->max_height = 2048; 8623 } 8624 8625 if (IS_I845G(i915) || IS_I865G(i915)) { 8626 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512; 8627 mode_config->cursor_height = 1023; 8628 } else if (IS_I830(i915) || IS_I85X(i915) || 8629 IS_I915G(i915) || IS_I915GM(i915)) { 8630 mode_config->cursor_width = 64; 8631 mode_config->cursor_height = 64; 8632 } else { 8633 mode_config->cursor_width = 256; 8634 mode_config->cursor_height = 256; 8635 } 8636 } 8637 8638 static void intel_mode_config_cleanup(struct drm_i915_private *i915) 8639 { 8640 intel_atomic_global_obj_cleanup(i915); 8641 drm_mode_config_cleanup(&i915->drm); 8642 } 8643 8644 /* part #1: call before irq install */ 8645 int intel_modeset_init_noirq(struct drm_i915_private *i915) 8646 { 8647 int ret; 8648 8649 if (i915_inject_probe_failure(i915)) 8650 return -ENODEV; 8651 8652 if (HAS_DISPLAY(i915)) { 8653 ret = drm_vblank_init(&i915->drm, 8654 INTEL_NUM_PIPES(i915)); 8655 if (ret) 8656 return ret; 8657 } 8658 8659 intel_bios_init(i915); 8660 8661 ret = intel_vga_register(i915); 8662 if (ret) 8663 goto cleanup_bios; 8664 8665 /* FIXME: completely on the wrong abstraction layer */ 8666 intel_power_domains_init_hw(i915, false); 8667 8668 if (!HAS_DISPLAY(i915)) 8669 return 0; 8670 8671 intel_dmc_ucode_init(i915); 8672 8673 i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0); 8674 i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI | 8675 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE); 8676 8677 i915->window2_delay = 0; /* No DSB so no window2 delay */ 8678 8679 intel_mode_config_init(i915); 8680 8681 ret = intel_cdclk_init(i915); 8682 if (ret) 8683 goto cleanup_vga_client_pw_domain_dmc; 8684 8685 ret = intel_dbuf_init(i915); 8686 if (ret) 8687 goto cleanup_vga_client_pw_domain_dmc; 8688 8689 ret = intel_bw_init(i915); 8690 if (ret) 8691 goto cleanup_vga_client_pw_domain_dmc; 8692 8693 init_llist_head(&i915->atomic_helper.free_list); 8694 INIT_WORK(&i915->atomic_helper.free_work, 8695 intel_atomic_helper_free_state_worker); 8696 8697 intel_init_quirks(i915); 8698 8699 intel_fbc_init(i915); 8700 8701 return 0; 8702 8703 cleanup_vga_client_pw_domain_dmc: 8704 intel_dmc_ucode_fini(i915); 8705 intel_power_domains_driver_remove(i915); 8706 intel_vga_unregister(i915); 8707 cleanup_bios: 8708 intel_bios_driver_remove(i915); 8709 8710 return ret; 8711 } 8712 8713 /* part #2: call after irq install, but before gem init */ 8714 int intel_modeset_init_nogem(struct drm_i915_private *i915) 8715 { 8716 struct drm_device *dev = &i915->drm; 8717 enum pipe pipe; 8718 struct intel_crtc *crtc; 8719 int ret; 8720 8721 if (!HAS_DISPLAY(i915)) 8722 return 0; 8723 8724 intel_init_pm(i915); 8725 8726 intel_panel_sanitize_ssc(i915); 8727 8728 intel_pps_setup(i915); 8729 8730 intel_gmbus_setup(i915); 8731 8732 drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n", 8733 INTEL_NUM_PIPES(i915), 8734 INTEL_NUM_PIPES(i915) > 1 ? "s" : ""); 8735 8736 for_each_pipe(i915, pipe) { 8737 ret = intel_crtc_init(i915, pipe); 8738 if (ret) { 8739 intel_mode_config_cleanup(i915); 8740 return ret; 8741 } 8742 } 8743 8744 intel_plane_possible_crtcs_init(i915); 8745 intel_shared_dpll_init(i915); 8746 intel_fdi_pll_freq_update(i915); 8747 8748 intel_update_czclk(i915); 8749 intel_modeset_init_hw(i915); 8750 intel_dpll_update_ref_clks(i915); 8751 8752 intel_hdcp_component_init(i915); 8753 8754 if (i915->max_cdclk_freq == 0) 8755 intel_update_max_cdclk(i915); 8756 8757 /* 8758 * If the platform has HTI, we need to find out whether it has reserved 8759 * any display resources before we create our display outputs. 8760 */ 8761 if (INTEL_INFO(i915)->display.has_hti) 8762 i915->hti_state = intel_de_read(i915, HDPORT_STATE); 8763 8764 /* Just disable it once at startup */ 8765 intel_vga_disable(i915); 8766 intel_setup_outputs(i915); 8767 8768 drm_modeset_lock_all(dev); 8769 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx); 8770 intel_acpi_assign_connector_fwnodes(i915); 8771 drm_modeset_unlock_all(dev); 8772 8773 for_each_intel_crtc(dev, crtc) { 8774 if (!to_intel_crtc_state(crtc->base.state)->uapi.active) 8775 continue; 8776 intel_crtc_initial_plane_config(crtc); 8777 } 8778 8779 /* 8780 * Make sure hardware watermarks really match the state we read out. 8781 * Note that we need to do this after reconstructing the BIOS fb's 8782 * since the watermark calculation done here will use pstate->fb. 8783 */ 8784 if (!HAS_GMCH(i915)) 8785 sanitize_watermarks(i915); 8786 8787 return 0; 8788 } 8789 8790 /* part #3: call after gem init */ 8791 int intel_modeset_init(struct drm_i915_private *i915) 8792 { 8793 int ret; 8794 8795 if (!HAS_DISPLAY(i915)) 8796 return 0; 8797 8798 /* 8799 * Force all active planes to recompute their states. So that on 8800 * mode_setcrtc after probe, all the intel_plane_state variables 8801 * are already calculated and there is no assert_plane warnings 8802 * during bootup. 8803 */ 8804 ret = intel_initial_commit(&i915->drm); 8805 if (ret) 8806 drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret); 8807 8808 intel_overlay_setup(i915); 8809 8810 ret = intel_fbdev_init(&i915->drm); 8811 if (ret) 8812 return ret; 8813 8814 /* Only enable hotplug handling once the fbdev is fully set up. */ 8815 intel_hpd_init(i915); 8816 intel_hpd_poll_disable(i915); 8817 8818 intel_init_ipc(i915); 8819 8820 return 0; 8821 } 8822 8823 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 8824 { 8825 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 8826 /* 640x480@60Hz, ~25175 kHz */ 8827 struct dpll clock = { 8828 .m1 = 18, 8829 .m2 = 7, 8830 .p1 = 13, 8831 .p2 = 4, 8832 .n = 2, 8833 }; 8834 u32 dpll, fp; 8835 int i; 8836 8837 drm_WARN_ON(&dev_priv->drm, 8838 i9xx_calc_dpll_params(48000, &clock) != 25154); 8839 8840 drm_dbg_kms(&dev_priv->drm, 8841 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n", 8842 pipe_name(pipe), clock.vco, clock.dot); 8843 8844 fp = i9xx_dpll_compute_fp(&clock); 8845 dpll = DPLL_DVO_2X_MODE | 8846 DPLL_VGA_MODE_DIS | 8847 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | 8848 PLL_P2_DIVIDE_BY_4 | 8849 PLL_REF_INPUT_DREFCLK | 8850 DPLL_VCO_ENABLE; 8851 8852 intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16)); 8853 intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16)); 8854 intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16)); 8855 intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16)); 8856 intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16)); 8857 intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16)); 8858 intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1)); 8859 8860 intel_de_write(dev_priv, FP0(pipe), fp); 8861 intel_de_write(dev_priv, FP1(pipe), fp); 8862 8863 /* 8864 * Apparently we need to have VGA mode enabled prior to changing 8865 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 8866 * dividers, even though the register value does change. 8867 */ 8868 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); 8869 intel_de_write(dev_priv, DPLL(pipe), dpll); 8870 8871 /* Wait for the clocks to stabilize. */ 8872 intel_de_posting_read(dev_priv, DPLL(pipe)); 8873 udelay(150); 8874 8875 /* The pixel multiplier can only be updated once the 8876 * DPLL is enabled and the clocks are stable. 8877 * 8878 * So write it again. 8879 */ 8880 intel_de_write(dev_priv, DPLL(pipe), dpll); 8881 8882 /* We do this three times for luck */ 8883 for (i = 0; i < 3 ; i++) { 8884 intel_de_write(dev_priv, DPLL(pipe), dpll); 8885 intel_de_posting_read(dev_priv, DPLL(pipe)); 8886 udelay(150); /* wait for warmup */ 8887 } 8888 8889 intel_de_write(dev_priv, PIPECONF(pipe), PIPECONF_ENABLE); 8890 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 8891 8892 intel_wait_for_pipe_scanline_moving(crtc); 8893 } 8894 8895 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 8896 { 8897 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 8898 8899 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n", 8900 pipe_name(pipe)); 8901 8902 drm_WARN_ON(&dev_priv->drm, 8903 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE); 8904 drm_WARN_ON(&dev_priv->drm, 8905 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE); 8906 drm_WARN_ON(&dev_priv->drm, 8907 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE); 8908 drm_WARN_ON(&dev_priv->drm, 8909 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK); 8910 drm_WARN_ON(&dev_priv->drm, 8911 intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK); 8912 8913 intel_de_write(dev_priv, PIPECONF(pipe), 0); 8914 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 8915 8916 intel_wait_for_pipe_scanline_stopped(crtc); 8917 8918 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); 8919 intel_de_posting_read(dev_priv, DPLL(pipe)); 8920 } 8921 8922 void intel_display_resume(struct drm_device *dev) 8923 { 8924 struct drm_i915_private *i915 = to_i915(dev); 8925 struct drm_atomic_state *state = i915->modeset_restore_state; 8926 struct drm_modeset_acquire_ctx ctx; 8927 int ret; 8928 8929 if (!HAS_DISPLAY(i915)) 8930 return; 8931 8932 i915->modeset_restore_state = NULL; 8933 if (state) 8934 state->acquire_ctx = &ctx; 8935 8936 drm_modeset_acquire_init(&ctx, 0); 8937 8938 while (1) { 8939 ret = drm_modeset_lock_all_ctx(dev, &ctx); 8940 if (ret != -EDEADLK) 8941 break; 8942 8943 drm_modeset_backoff(&ctx); 8944 } 8945 8946 if (!ret) 8947 ret = __intel_display_resume(i915, state, &ctx); 8948 8949 intel_enable_ipc(i915); 8950 drm_modeset_drop_locks(&ctx); 8951 drm_modeset_acquire_fini(&ctx); 8952 8953 if (ret) 8954 drm_err(&i915->drm, 8955 "Restoring old state failed with %i\n", ret); 8956 if (state) 8957 drm_atomic_state_put(state); 8958 } 8959 8960 static void intel_hpd_poll_fini(struct drm_i915_private *i915) 8961 { 8962 struct intel_connector *connector; 8963 struct drm_connector_list_iter conn_iter; 8964 8965 /* Kill all the work that may have been queued by hpd. */ 8966 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 8967 for_each_intel_connector_iter(connector, &conn_iter) { 8968 if (connector->modeset_retry_work.func) 8969 cancel_work_sync(&connector->modeset_retry_work); 8970 if (connector->hdcp.shim) { 8971 cancel_delayed_work_sync(&connector->hdcp.check_work); 8972 cancel_work_sync(&connector->hdcp.prop_work); 8973 } 8974 } 8975 drm_connector_list_iter_end(&conn_iter); 8976 } 8977 8978 /* part #1: call before irq uninstall */ 8979 void intel_modeset_driver_remove(struct drm_i915_private *i915) 8980 { 8981 if (!HAS_DISPLAY(i915)) 8982 return; 8983 8984 flush_workqueue(i915->flip_wq); 8985 flush_workqueue(i915->modeset_wq); 8986 8987 flush_work(&i915->atomic_helper.free_work); 8988 drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list)); 8989 } 8990 8991 /* part #2: call after irq uninstall */ 8992 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915) 8993 { 8994 if (!HAS_DISPLAY(i915)) 8995 return; 8996 8997 /* 8998 * Due to the hpd irq storm handling the hotplug work can re-arm the 8999 * poll handlers. Hence disable polling after hpd handling is shut down. 9000 */ 9001 intel_hpd_poll_fini(i915); 9002 9003 /* 9004 * MST topology needs to be suspended so we don't have any calls to 9005 * fbdev after it's finalized. MST will be destroyed later as part of 9006 * drm_mode_config_cleanup() 9007 */ 9008 intel_dp_mst_suspend(i915); 9009 9010 /* poll work can call into fbdev, hence clean that up afterwards */ 9011 intel_fbdev_fini(i915); 9012 9013 intel_unregister_dsm_handler(); 9014 9015 /* flush any delayed tasks or pending work */ 9016 flush_scheduled_work(); 9017 9018 intel_hdcp_component_fini(i915); 9019 9020 intel_mode_config_cleanup(i915); 9021 9022 intel_overlay_cleanup(i915); 9023 9024 intel_gmbus_teardown(i915); 9025 9026 destroy_workqueue(i915->flip_wq); 9027 destroy_workqueue(i915->modeset_wq); 9028 9029 intel_fbc_cleanup(i915); 9030 } 9031 9032 /* part #3: call after gem init */ 9033 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915) 9034 { 9035 intel_dmc_ucode_fini(i915); 9036 9037 intel_power_domains_driver_remove(i915); 9038 9039 intel_vga_unregister(i915); 9040 9041 intel_bios_driver_remove(i915); 9042 } 9043 9044 bool intel_modeset_probe_defer(struct pci_dev *pdev) 9045 { 9046 struct drm_privacy_screen *privacy_screen; 9047 9048 /* 9049 * apple-gmux is needed on dual GPU MacBook Pro 9050 * to probe the panel if we're the inactive GPU. 9051 */ 9052 if (vga_switcheroo_client_probe_defer(pdev)) 9053 return true; 9054 9055 /* If the LCD panel has a privacy-screen, wait for it */ 9056 privacy_screen = drm_privacy_screen_get(&pdev->dev, NULL); 9057 if (IS_ERR(privacy_screen) && PTR_ERR(privacy_screen) == -EPROBE_DEFER) 9058 return true; 9059 9060 drm_privacy_screen_put(privacy_screen); 9061 9062 return false; 9063 } 9064 9065 void intel_display_driver_register(struct drm_i915_private *i915) 9066 { 9067 if (!HAS_DISPLAY(i915)) 9068 return; 9069 9070 intel_display_debugfs_register(i915); 9071 9072 /* Must be done after probing outputs */ 9073 intel_opregion_register(i915); 9074 acpi_video_register(); 9075 9076 intel_audio_init(i915); 9077 9078 /* 9079 * Some ports require correctly set-up hpd registers for 9080 * detection to work properly (leading to ghost connected 9081 * connector status), e.g. VGA on gm45. Hence we can only set 9082 * up the initial fbdev config after hpd irqs are fully 9083 * enabled. We do it last so that the async config cannot run 9084 * before the connectors are registered. 9085 */ 9086 intel_fbdev_initial_config_async(&i915->drm); 9087 9088 /* 9089 * We need to coordinate the hotplugs with the asynchronous 9090 * fbdev configuration, for which we use the 9091 * fbdev->async_cookie. 9092 */ 9093 drm_kms_helper_poll_init(&i915->drm); 9094 } 9095 9096 void intel_display_driver_unregister(struct drm_i915_private *i915) 9097 { 9098 if (!HAS_DISPLAY(i915)) 9099 return; 9100 9101 intel_fbdev_unregister(i915); 9102 intel_audio_deinit(i915); 9103 9104 /* 9105 * After flushing the fbdev (incl. a late async config which 9106 * will have delayed queuing of a hotplug event), then flush 9107 * the hotplug events. 9108 */ 9109 drm_kms_helper_poll_fini(&i915->drm); 9110 drm_atomic_helper_shutdown(&i915->drm); 9111 9112 acpi_video_unregister(); 9113 intel_opregion_unregister(i915); 9114 } 9115 9116 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915) 9117 { 9118 return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915); 9119 } 9120