1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <acpi/video.h> 28 #include <linux/i2c.h> 29 #include <linux/input.h> 30 #include <linux/intel-iommu.h> 31 #include <linux/kernel.h> 32 #include <linux/module.h> 33 #include <linux/dma-resv.h> 34 #include <linux/slab.h> 35 #include <linux/string_helpers.h> 36 #include <linux/vga_switcheroo.h> 37 38 #include <drm/drm_atomic.h> 39 #include <drm/drm_atomic_helper.h> 40 #include <drm/drm_atomic_uapi.h> 41 #include <drm/drm_damage_helper.h> 42 #include <drm/dp/drm_dp_helper.h> 43 #include <drm/drm_edid.h> 44 #include <drm/drm_fourcc.h> 45 #include <drm/drm_plane_helper.h> 46 #include <drm/drm_privacy_screen_consumer.h> 47 #include <drm/drm_probe_helper.h> 48 #include <drm/drm_rect.h> 49 50 #include "display/intel_audio.h" 51 #include "display/intel_crt.h" 52 #include "display/intel_ddi.h" 53 #include "display/intel_display_debugfs.h" 54 #include "display/intel_display_power.h" 55 #include "display/intel_dp.h" 56 #include "display/intel_dp_mst.h" 57 #include "display/intel_dpll.h" 58 #include "display/intel_dpll_mgr.h" 59 #include "display/intel_drrs.h" 60 #include "display/intel_dsi.h" 61 #include "display/intel_dvo.h" 62 #include "display/intel_fb.h" 63 #include "display/intel_gmbus.h" 64 #include "display/intel_hdmi.h" 65 #include "display/intel_lvds.h" 66 #include "display/intel_sdvo.h" 67 #include "display/intel_snps_phy.h" 68 #include "display/intel_tv.h" 69 #include "display/intel_vdsc.h" 70 #include "display/intel_vrr.h" 71 72 #include "gem/i915_gem_lmem.h" 73 #include "gem/i915_gem_object.h" 74 75 #include "gt/gen8_ppgtt.h" 76 77 #include "g4x_dp.h" 78 #include "g4x_hdmi.h" 79 #include "hsw_ips.h" 80 #include "i915_drv.h" 81 #include "i915_utils.h" 82 #include "icl_dsi.h" 83 #include "intel_acpi.h" 84 #include "intel_atomic.h" 85 #include "intel_atomic_plane.h" 86 #include "intel_bw.h" 87 #include "intel_cdclk.h" 88 #include "intel_color.h" 89 #include "intel_crtc.h" 90 #include "intel_de.h" 91 #include "intel_display_types.h" 92 #include "intel_dmc.h" 93 #include "intel_dp_link_training.h" 94 #include "intel_dpt.h" 95 #include "intel_fbc.h" 96 #include "intel_fbdev.h" 97 #include "intel_fdi.h" 98 #include "intel_fifo_underrun.h" 99 #include "intel_frontbuffer.h" 100 #include "intel_hdcp.h" 101 #include "intel_hotplug.h" 102 #include "intel_overlay.h" 103 #include "intel_panel.h" 104 #include "intel_pch_display.h" 105 #include "intel_pch_refclk.h" 106 #include "intel_pcode.h" 107 #include "intel_pipe_crc.h" 108 #include "intel_plane_initial.h" 109 #include "intel_pm.h" 110 #include "intel_pps.h" 111 #include "intel_psr.h" 112 #include "intel_quirks.h" 113 #include "intel_sprite.h" 114 #include "intel_tc.h" 115 #include "intel_vga.h" 116 #include "i9xx_plane.h" 117 #include "skl_scaler.h" 118 #include "skl_universal_plane.h" 119 #include "vlv_dsi.h" 120 #include "vlv_dsi_pll.h" 121 #include "vlv_dsi_regs.h" 122 #include "vlv_sideband.h" 123 124 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state); 125 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state); 126 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state); 127 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state); 128 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state); 129 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state); 130 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state); 131 static void intel_modeset_setup_hw_state(struct drm_device *dev, 132 struct drm_modeset_acquire_ctx *ctx); 133 134 /** 135 * intel_update_watermarks - update FIFO watermark values based on current modes 136 * @dev_priv: i915 device 137 * 138 * Calculate watermark values for the various WM regs based on current mode 139 * and plane configuration. 140 * 141 * There are several cases to deal with here: 142 * - normal (i.e. non-self-refresh) 143 * - self-refresh (SR) mode 144 * - lines are large relative to FIFO size (buffer can hold up to 2) 145 * - lines are small relative to FIFO size (buffer can hold more than 2 146 * lines), so need to account for TLB latency 147 * 148 * The normal calculation is: 149 * watermark = dotclock * bytes per pixel * latency 150 * where latency is platform & configuration dependent (we assume pessimal 151 * values here). 152 * 153 * The SR calculation is: 154 * watermark = (trunc(latency/line time)+1) * surface width * 155 * bytes per pixel 156 * where 157 * line time = htotal / dotclock 158 * surface width = hdisplay for normal plane and 64 for cursor 159 * and latency is assumed to be high, as above. 160 * 161 * The final value programmed to the register should always be rounded up, 162 * and include an extra 2 entries to account for clock crossings. 163 * 164 * We don't use the sprite, so we can ignore that. And on Crestline we have 165 * to set the non-SR watermarks to 8. 166 */ 167 static void intel_update_watermarks(struct drm_i915_private *dev_priv) 168 { 169 if (dev_priv->wm_disp->update_wm) 170 dev_priv->wm_disp->update_wm(dev_priv); 171 } 172 173 static int intel_compute_pipe_wm(struct intel_atomic_state *state, 174 struct intel_crtc *crtc) 175 { 176 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 177 if (dev_priv->wm_disp->compute_pipe_wm) 178 return dev_priv->wm_disp->compute_pipe_wm(state, crtc); 179 return 0; 180 } 181 182 static int intel_compute_intermediate_wm(struct intel_atomic_state *state, 183 struct intel_crtc *crtc) 184 { 185 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 186 if (!dev_priv->wm_disp->compute_intermediate_wm) 187 return 0; 188 if (drm_WARN_ON(&dev_priv->drm, 189 !dev_priv->wm_disp->compute_pipe_wm)) 190 return 0; 191 return dev_priv->wm_disp->compute_intermediate_wm(state, crtc); 192 } 193 194 static bool intel_initial_watermarks(struct intel_atomic_state *state, 195 struct intel_crtc *crtc) 196 { 197 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 198 if (dev_priv->wm_disp->initial_watermarks) { 199 dev_priv->wm_disp->initial_watermarks(state, crtc); 200 return true; 201 } 202 return false; 203 } 204 205 static void intel_atomic_update_watermarks(struct intel_atomic_state *state, 206 struct intel_crtc *crtc) 207 { 208 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 209 if (dev_priv->wm_disp->atomic_update_watermarks) 210 dev_priv->wm_disp->atomic_update_watermarks(state, crtc); 211 } 212 213 static void intel_optimize_watermarks(struct intel_atomic_state *state, 214 struct intel_crtc *crtc) 215 { 216 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 217 if (dev_priv->wm_disp->optimize_watermarks) 218 dev_priv->wm_disp->optimize_watermarks(state, crtc); 219 } 220 221 static int intel_compute_global_watermarks(struct intel_atomic_state *state) 222 { 223 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 224 if (dev_priv->wm_disp->compute_global_watermarks) 225 return dev_priv->wm_disp->compute_global_watermarks(state); 226 return 0; 227 } 228 229 /* returns HPLL frequency in kHz */ 230 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) 231 { 232 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; 233 234 /* Obtain SKU information */ 235 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & 236 CCK_FUSE_HPLL_FREQ_MASK; 237 238 return vco_freq[hpll_freq] * 1000; 239 } 240 241 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 242 const char *name, u32 reg, int ref_freq) 243 { 244 u32 val; 245 int divider; 246 247 val = vlv_cck_read(dev_priv, reg); 248 divider = val & CCK_FREQUENCY_VALUES; 249 250 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != 251 (divider << CCK_FREQUENCY_STATUS_SHIFT), 252 "%s change in progress\n", name); 253 254 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); 255 } 256 257 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 258 const char *name, u32 reg) 259 { 260 int hpll; 261 262 vlv_cck_get(dev_priv); 263 264 if (dev_priv->hpll_freq == 0) 265 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); 266 267 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); 268 269 vlv_cck_put(dev_priv); 270 271 return hpll; 272 } 273 274 static void intel_update_czclk(struct drm_i915_private *dev_priv) 275 { 276 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) 277 return; 278 279 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", 280 CCK_CZ_CLOCK_CONTROL); 281 282 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", 283 dev_priv->czclk_freq); 284 } 285 286 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state) 287 { 288 return (crtc_state->active_planes & 289 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0; 290 } 291 292 /* WA Display #0827: Gen9:all */ 293 static void 294 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) 295 { 296 if (enable) 297 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 298 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS); 299 else 300 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 301 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS)); 302 } 303 304 /* Wa_2006604312:icl,ehl */ 305 static void 306 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 307 bool enable) 308 { 309 if (enable) 310 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 311 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS); 312 else 313 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), 314 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS); 315 } 316 317 /* Wa_1604331009:icl,jsl,ehl */ 318 static void 319 icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 320 bool enable) 321 { 322 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), CURSOR_GATING_DIS, 323 enable ? CURSOR_GATING_DIS : 0); 324 } 325 326 static bool 327 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state) 328 { 329 return crtc_state->master_transcoder != INVALID_TRANSCODER; 330 } 331 332 static bool 333 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state) 334 { 335 return crtc_state->sync_mode_slaves_mask != 0; 336 } 337 338 bool 339 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state) 340 { 341 return is_trans_port_sync_master(crtc_state) || 342 is_trans_port_sync_slave(crtc_state); 343 } 344 345 static enum pipe bigjoiner_master_pipe(const struct intel_crtc_state *crtc_state) 346 { 347 return ffs(crtc_state->bigjoiner_pipes) - 1; 348 } 349 350 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state) 351 { 352 if (crtc_state->bigjoiner_pipes) 353 return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state)); 354 else 355 return 0; 356 } 357 358 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state) 359 { 360 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 361 362 return crtc_state->bigjoiner_pipes && 363 crtc->pipe != bigjoiner_master_pipe(crtc_state); 364 } 365 366 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state) 367 { 368 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 369 370 return crtc_state->bigjoiner_pipes && 371 crtc->pipe == bigjoiner_master_pipe(crtc_state); 372 } 373 374 static int intel_bigjoiner_num_pipes(const struct intel_crtc_state *crtc_state) 375 { 376 return hweight8(crtc_state->bigjoiner_pipes); 377 } 378 379 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state) 380 { 381 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 382 383 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 384 return intel_crtc_for_pipe(i915, bigjoiner_master_pipe(crtc_state)); 385 else 386 return to_intel_crtc(crtc_state->uapi.crtc); 387 } 388 389 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv, 390 enum pipe pipe) 391 { 392 i915_reg_t reg = PIPEDSL(pipe); 393 u32 line1, line2; 394 395 line1 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK; 396 msleep(5); 397 line2 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK; 398 399 return line1 != line2; 400 } 401 402 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state) 403 { 404 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 405 enum pipe pipe = crtc->pipe; 406 407 /* Wait for the display line to settle/start moving */ 408 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100)) 409 drm_err(&dev_priv->drm, 410 "pipe %c scanline %s wait timed out\n", 411 pipe_name(pipe), str_on_off(state)); 412 } 413 414 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc) 415 { 416 wait_for_pipe_scanline_moving(crtc, false); 417 } 418 419 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc) 420 { 421 wait_for_pipe_scanline_moving(crtc, true); 422 } 423 424 static void 425 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) 426 { 427 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 428 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 429 430 if (DISPLAY_VER(dev_priv) >= 4) { 431 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 432 433 /* Wait for the Pipe State to go off */ 434 if (intel_de_wait_for_clear(dev_priv, PIPECONF(cpu_transcoder), 435 PIPECONF_STATE_ENABLE, 100)) 436 drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n"); 437 } else { 438 intel_wait_for_pipe_scanline_stopped(crtc); 439 } 440 } 441 442 void assert_transcoder(struct drm_i915_private *dev_priv, 443 enum transcoder cpu_transcoder, bool state) 444 { 445 bool cur_state; 446 enum intel_display_power_domain power_domain; 447 intel_wakeref_t wakeref; 448 449 /* we keep both pipes enabled on 830 */ 450 if (IS_I830(dev_priv)) 451 state = true; 452 453 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 454 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 455 if (wakeref) { 456 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); 457 cur_state = !!(val & PIPECONF_ENABLE); 458 459 intel_display_power_put(dev_priv, power_domain, wakeref); 460 } else { 461 cur_state = false; 462 } 463 464 I915_STATE_WARN(cur_state != state, 465 "transcoder %s assertion failure (expected %s, current %s)\n", 466 transcoder_name(cpu_transcoder), 467 str_on_off(state), str_on_off(cur_state)); 468 } 469 470 static void assert_plane(struct intel_plane *plane, bool state) 471 { 472 enum pipe pipe; 473 bool cur_state; 474 475 cur_state = plane->get_hw_state(plane, &pipe); 476 477 I915_STATE_WARN(cur_state != state, 478 "%s assertion failure (expected %s, current %s)\n", 479 plane->base.name, str_on_off(state), 480 str_on_off(cur_state)); 481 } 482 483 #define assert_plane_enabled(p) assert_plane(p, true) 484 #define assert_plane_disabled(p) assert_plane(p, false) 485 486 static void assert_planes_disabled(struct intel_crtc *crtc) 487 { 488 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 489 struct intel_plane *plane; 490 491 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) 492 assert_plane_disabled(plane); 493 } 494 495 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 496 struct intel_digital_port *dig_port, 497 unsigned int expected_mask) 498 { 499 u32 port_mask; 500 i915_reg_t dpll_reg; 501 502 switch (dig_port->base.port) { 503 case PORT_B: 504 port_mask = DPLL_PORTB_READY_MASK; 505 dpll_reg = DPLL(0); 506 break; 507 case PORT_C: 508 port_mask = DPLL_PORTC_READY_MASK; 509 dpll_reg = DPLL(0); 510 expected_mask <<= 4; 511 break; 512 case PORT_D: 513 port_mask = DPLL_PORTD_READY_MASK; 514 dpll_reg = DPIO_PHY_STATUS; 515 break; 516 default: 517 BUG(); 518 } 519 520 if (intel_de_wait_for_register(dev_priv, dpll_reg, 521 port_mask, expected_mask, 1000)) 522 drm_WARN(&dev_priv->drm, 1, 523 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", 524 dig_port->base.base.base.id, dig_port->base.base.name, 525 intel_de_read(dev_priv, dpll_reg) & port_mask, 526 expected_mask); 527 } 528 529 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) 530 { 531 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 532 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 533 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 534 enum pipe pipe = crtc->pipe; 535 i915_reg_t reg; 536 u32 val; 537 538 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe)); 539 540 assert_planes_disabled(crtc); 541 542 /* 543 * A pipe without a PLL won't actually be able to drive bits from 544 * a plane. On ILK+ the pipe PLLs are integrated, so we don't 545 * need the check. 546 */ 547 if (HAS_GMCH(dev_priv)) { 548 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI)) 549 assert_dsi_pll_enabled(dev_priv); 550 else 551 assert_pll_enabled(dev_priv, pipe); 552 } else { 553 if (new_crtc_state->has_pch_encoder) { 554 /* if driving the PCH, we need FDI enabled */ 555 assert_fdi_rx_pll_enabled(dev_priv, 556 intel_crtc_pch_transcoder(crtc)); 557 assert_fdi_tx_pll_enabled(dev_priv, 558 (enum pipe) cpu_transcoder); 559 } 560 /* FIXME: assert CPU port conditions for SNB+ */ 561 } 562 563 /* Wa_22012358565:adl-p */ 564 if (DISPLAY_VER(dev_priv) == 13) 565 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe), 566 0, PIPE_ARB_USE_PROG_SLOTS); 567 568 reg = PIPECONF(cpu_transcoder); 569 val = intel_de_read(dev_priv, reg); 570 if (val & PIPECONF_ENABLE) { 571 /* we keep both pipes enabled on 830 */ 572 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv)); 573 return; 574 } 575 576 intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE); 577 intel_de_posting_read(dev_priv, reg); 578 579 /* 580 * Until the pipe starts PIPEDSL reads will return a stale value, 581 * which causes an apparent vblank timestamp jump when PIPEDSL 582 * resets to its proper value. That also messes up the frame count 583 * when it's derived from the timestamps. So let's wait for the 584 * pipe to start properly before we call drm_crtc_vblank_on() 585 */ 586 if (intel_crtc_max_vblank_count(new_crtc_state) == 0) 587 intel_wait_for_pipe_scanline_moving(crtc); 588 } 589 590 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) 591 { 592 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 593 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 594 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 595 enum pipe pipe = crtc->pipe; 596 i915_reg_t reg; 597 u32 val; 598 599 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe)); 600 601 /* 602 * Make sure planes won't keep trying to pump pixels to us, 603 * or we might hang the display. 604 */ 605 assert_planes_disabled(crtc); 606 607 reg = PIPECONF(cpu_transcoder); 608 val = intel_de_read(dev_priv, reg); 609 if ((val & PIPECONF_ENABLE) == 0) 610 return; 611 612 /* 613 * Double wide has implications for planes 614 * so best keep it disabled when not needed. 615 */ 616 if (old_crtc_state->double_wide) 617 val &= ~PIPECONF_DOUBLE_WIDE; 618 619 /* Don't disable pipe or pipe PLLs if needed */ 620 if (!IS_I830(dev_priv)) 621 val &= ~PIPECONF_ENABLE; 622 623 if (DISPLAY_VER(dev_priv) >= 12) 624 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 625 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 626 627 intel_de_write(dev_priv, reg, val); 628 if ((val & PIPECONF_ENABLE) == 0) 629 intel_wait_for_pipe_off(old_crtc_state); 630 } 631 632 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) 633 { 634 unsigned int size = 0; 635 int i; 636 637 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) 638 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width; 639 640 return size; 641 } 642 643 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info) 644 { 645 unsigned int size = 0; 646 int i; 647 648 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) { 649 unsigned int plane_size; 650 651 if (rem_info->plane[i].linear) 652 plane_size = rem_info->plane[i].size; 653 else 654 plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height; 655 656 if (plane_size == 0) 657 continue; 658 659 if (rem_info->plane_alignment) 660 size = ALIGN(size, rem_info->plane_alignment); 661 662 size += plane_size; 663 } 664 665 return size; 666 } 667 668 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) 669 { 670 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 671 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 672 673 return DISPLAY_VER(dev_priv) < 4 || 674 (plane->fbc && 675 plane_state->view.gtt.type == I915_GGTT_VIEW_NORMAL); 676 } 677 678 /* 679 * Convert the x/y offsets into a linear offset. 680 * Only valid with 0/180 degree rotation, which is fine since linear 681 * offset is only used with linear buffers on pre-hsw and tiled buffers 682 * with gen2/3, and 90/270 degree rotations isn't supported on any of them. 683 */ 684 u32 intel_fb_xy_to_linear(int x, int y, 685 const struct intel_plane_state *state, 686 int color_plane) 687 { 688 const struct drm_framebuffer *fb = state->hw.fb; 689 unsigned int cpp = fb->format->cpp[color_plane]; 690 unsigned int pitch = state->view.color_plane[color_plane].mapping_stride; 691 692 return y * pitch + x * cpp; 693 } 694 695 /* 696 * Add the x/y offsets derived from fb->offsets[] to the user 697 * specified plane src x/y offsets. The resulting x/y offsets 698 * specify the start of scanout from the beginning of the gtt mapping. 699 */ 700 void intel_add_fb_offsets(int *x, int *y, 701 const struct intel_plane_state *state, 702 int color_plane) 703 704 { 705 *x += state->view.color_plane[color_plane].x; 706 *y += state->view.color_plane[color_plane].y; 707 } 708 709 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 710 u32 pixel_format, u64 modifier) 711 { 712 struct intel_crtc *crtc; 713 struct intel_plane *plane; 714 715 if (!HAS_DISPLAY(dev_priv)) 716 return 0; 717 718 /* 719 * We assume the primary plane for pipe A has 720 * the highest stride limits of them all, 721 * if in case pipe A is disabled, use the first pipe from pipe_mask. 722 */ 723 crtc = intel_first_crtc(dev_priv); 724 if (!crtc) 725 return 0; 726 727 plane = to_intel_plane(crtc->base.primary); 728 729 return plane->max_stride(plane, pixel_format, modifier, 730 DRM_MODE_ROTATE_0); 731 } 732 733 static void 734 intel_set_plane_visible(struct intel_crtc_state *crtc_state, 735 struct intel_plane_state *plane_state, 736 bool visible) 737 { 738 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 739 740 plane_state->uapi.visible = visible; 741 742 if (visible) 743 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base); 744 else 745 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base); 746 } 747 748 static void fixup_plane_bitmasks(struct intel_crtc_state *crtc_state) 749 { 750 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 751 struct drm_plane *plane; 752 753 /* 754 * Active_planes aliases if multiple "primary" or cursor planes 755 * have been used on the same (or wrong) pipe. plane_mask uses 756 * unique ids, hence we can use that to reconstruct active_planes. 757 */ 758 crtc_state->enabled_planes = 0; 759 crtc_state->active_planes = 0; 760 761 drm_for_each_plane_mask(plane, &dev_priv->drm, 762 crtc_state->uapi.plane_mask) { 763 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id); 764 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id); 765 } 766 } 767 768 void intel_plane_disable_noatomic(struct intel_crtc *crtc, 769 struct intel_plane *plane) 770 { 771 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 772 struct intel_crtc_state *crtc_state = 773 to_intel_crtc_state(crtc->base.state); 774 struct intel_plane_state *plane_state = 775 to_intel_plane_state(plane->base.state); 776 777 drm_dbg_kms(&dev_priv->drm, 778 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n", 779 plane->base.base.id, plane->base.name, 780 crtc->base.base.id, crtc->base.name); 781 782 intel_set_plane_visible(crtc_state, plane_state, false); 783 fixup_plane_bitmasks(crtc_state); 784 crtc_state->data_rate[plane->id] = 0; 785 crtc_state->data_rate_y[plane->id] = 0; 786 crtc_state->rel_data_rate[plane->id] = 0; 787 crtc_state->rel_data_rate_y[plane->id] = 0; 788 crtc_state->min_cdclk[plane->id] = 0; 789 790 if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 && 791 hsw_ips_disable(crtc_state)) { 792 crtc_state->ips_enabled = false; 793 intel_crtc_wait_for_next_vblank(crtc); 794 } 795 796 /* 797 * Vblank time updates from the shadow to live plane control register 798 * are blocked if the memory self-refresh mode is active at that 799 * moment. So to make sure the plane gets truly disabled, disable 800 * first the self-refresh mode. The self-refresh enable bit in turn 801 * will be checked/applied by the HW only at the next frame start 802 * event which is after the vblank start event, so we need to have a 803 * wait-for-vblank between disabling the plane and the pipe. 804 */ 805 if (HAS_GMCH(dev_priv) && 806 intel_set_memory_cxsr(dev_priv, false)) 807 intel_crtc_wait_for_next_vblank(crtc); 808 809 /* 810 * Gen2 reports pipe underruns whenever all planes are disabled. 811 * So disable underrun reporting before all the planes get disabled. 812 */ 813 if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes) 814 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); 815 816 intel_plane_disable_arm(plane, crtc_state); 817 intel_crtc_wait_for_next_vblank(crtc); 818 } 819 820 unsigned int 821 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state) 822 { 823 int x = 0, y = 0; 824 825 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, 826 plane_state->view.color_plane[0].offset, 0); 827 828 return y; 829 } 830 831 static int 832 __intel_display_resume(struct drm_device *dev, 833 struct drm_atomic_state *state, 834 struct drm_modeset_acquire_ctx *ctx) 835 { 836 struct drm_crtc_state *crtc_state; 837 struct drm_crtc *crtc; 838 int i, ret; 839 840 intel_modeset_setup_hw_state(dev, ctx); 841 intel_vga_redisable(to_i915(dev)); 842 843 if (!state) 844 return 0; 845 846 /* 847 * We've duplicated the state, pointers to the old state are invalid. 848 * 849 * Don't attempt to use the old state until we commit the duplicated state. 850 */ 851 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 852 /* 853 * Force recalculation even if we restore 854 * current state. With fast modeset this may not result 855 * in a modeset when the state is compatible. 856 */ 857 crtc_state->mode_changed = true; 858 } 859 860 /* ignore any reset values/BIOS leftovers in the WM registers */ 861 if (!HAS_GMCH(to_i915(dev))) 862 to_intel_atomic_state(state)->skip_intermediate_wm = true; 863 864 ret = drm_atomic_helper_commit_duplicated_state(state, ctx); 865 866 drm_WARN_ON(dev, ret == -EDEADLK); 867 return ret; 868 } 869 870 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) 871 { 872 return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display && 873 intel_has_gpu_reset(to_gt(dev_priv))); 874 } 875 876 void intel_display_prepare_reset(struct drm_i915_private *dev_priv) 877 { 878 struct drm_device *dev = &dev_priv->drm; 879 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; 880 struct drm_atomic_state *state; 881 int ret; 882 883 if (!HAS_DISPLAY(dev_priv)) 884 return; 885 886 /* reset doesn't touch the display */ 887 if (!dev_priv->params.force_reset_modeset_test && 888 !gpu_reset_clobbers_display(dev_priv)) 889 return; 890 891 /* We have a modeset vs reset deadlock, defensively unbreak it. */ 892 set_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags); 893 smp_mb__after_atomic(); 894 wake_up_bit(&to_gt(dev_priv)->reset.flags, I915_RESET_MODESET); 895 896 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) { 897 drm_dbg_kms(&dev_priv->drm, 898 "Modeset potentially stuck, unbreaking through wedging\n"); 899 intel_gt_set_wedged(to_gt(dev_priv)); 900 } 901 902 /* 903 * Need mode_config.mutex so that we don't 904 * trample ongoing ->detect() and whatnot. 905 */ 906 mutex_lock(&dev->mode_config.mutex); 907 drm_modeset_acquire_init(ctx, 0); 908 while (1) { 909 ret = drm_modeset_lock_all_ctx(dev, ctx); 910 if (ret != -EDEADLK) 911 break; 912 913 drm_modeset_backoff(ctx); 914 } 915 /* 916 * Disabling the crtcs gracefully seems nicer. Also the 917 * g33 docs say we should at least disable all the planes. 918 */ 919 state = drm_atomic_helper_duplicate_state(dev, ctx); 920 if (IS_ERR(state)) { 921 ret = PTR_ERR(state); 922 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n", 923 ret); 924 return; 925 } 926 927 ret = drm_atomic_helper_disable_all(dev, ctx); 928 if (ret) { 929 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", 930 ret); 931 drm_atomic_state_put(state); 932 return; 933 } 934 935 dev_priv->modeset_restore_state = state; 936 state->acquire_ctx = ctx; 937 } 938 939 void intel_display_finish_reset(struct drm_i915_private *dev_priv) 940 { 941 struct drm_device *dev = &dev_priv->drm; 942 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; 943 struct drm_atomic_state *state; 944 int ret; 945 946 if (!HAS_DISPLAY(dev_priv)) 947 return; 948 949 /* reset doesn't touch the display */ 950 if (!test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags)) 951 return; 952 953 state = fetch_and_zero(&dev_priv->modeset_restore_state); 954 if (!state) 955 goto unlock; 956 957 /* reset doesn't touch the display */ 958 if (!gpu_reset_clobbers_display(dev_priv)) { 959 /* for testing only restore the display */ 960 ret = __intel_display_resume(dev, state, ctx); 961 if (ret) 962 drm_err(&dev_priv->drm, 963 "Restoring old state failed with %i\n", ret); 964 } else { 965 /* 966 * The display has been reset as well, 967 * so need a full re-initialization. 968 */ 969 intel_pps_unlock_regs_wa(dev_priv); 970 intel_modeset_init_hw(dev_priv); 971 intel_init_clock_gating(dev_priv); 972 intel_hpd_init(dev_priv); 973 974 ret = __intel_display_resume(dev, state, ctx); 975 if (ret) 976 drm_err(&dev_priv->drm, 977 "Restoring old state failed with %i\n", ret); 978 979 intel_hpd_poll_disable(dev_priv); 980 } 981 982 drm_atomic_state_put(state); 983 unlock: 984 drm_modeset_drop_locks(ctx); 985 drm_modeset_acquire_fini(ctx); 986 mutex_unlock(&dev->mode_config.mutex); 987 988 clear_bit_unlock(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags); 989 } 990 991 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) 992 { 993 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 994 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 995 enum pipe pipe = crtc->pipe; 996 u32 tmp; 997 998 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe)); 999 1000 /* 1001 * Display WA #1153: icl 1002 * enable hardware to bypass the alpha math 1003 * and rounding for per-pixel values 00 and 0xff 1004 */ 1005 tmp |= PER_PIXEL_ALPHA_BYPASS_EN; 1006 /* 1007 * Display WA # 1605353570: icl 1008 * Set the pixel rounding bit to 1 for allowing 1009 * passthrough of Frame buffer pixels unmodified 1010 * across pipe 1011 */ 1012 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU; 1013 1014 /* 1015 * Underrun recovery must always be disabled on display 13+. 1016 * DG2 chicken bit meaning is inverted compared to other platforms. 1017 */ 1018 if (IS_DG2(dev_priv)) 1019 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2; 1020 else if (DISPLAY_VER(dev_priv) >= 13) 1021 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP; 1022 1023 /* Wa_14010547955:dg2 */ 1024 if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER)) 1025 tmp |= DG2_RENDER_CCSTAG_4_3_EN; 1026 1027 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp); 1028 } 1029 1030 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) 1031 { 1032 struct drm_crtc *crtc; 1033 bool cleanup_done; 1034 1035 drm_for_each_crtc(crtc, &dev_priv->drm) { 1036 struct drm_crtc_commit *commit; 1037 spin_lock(&crtc->commit_lock); 1038 commit = list_first_entry_or_null(&crtc->commit_list, 1039 struct drm_crtc_commit, commit_entry); 1040 cleanup_done = commit ? 1041 try_wait_for_completion(&commit->cleanup_done) : true; 1042 spin_unlock(&crtc->commit_lock); 1043 1044 if (cleanup_done) 1045 continue; 1046 1047 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc)); 1048 1049 return true; 1050 } 1051 1052 return false; 1053 } 1054 1055 /* 1056 * Finds the encoder associated with the given CRTC. This can only be 1057 * used when we know that the CRTC isn't feeding multiple encoders! 1058 */ 1059 struct intel_encoder * 1060 intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 1061 const struct intel_crtc_state *crtc_state) 1062 { 1063 const struct drm_connector_state *connector_state; 1064 const struct drm_connector *connector; 1065 struct intel_encoder *encoder = NULL; 1066 struct intel_crtc *master_crtc; 1067 int num_encoders = 0; 1068 int i; 1069 1070 master_crtc = intel_master_crtc(crtc_state); 1071 1072 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 1073 if (connector_state->crtc != &master_crtc->base) 1074 continue; 1075 1076 encoder = to_intel_encoder(connector_state->best_encoder); 1077 num_encoders++; 1078 } 1079 1080 drm_WARN(encoder->base.dev, num_encoders != 1, 1081 "%d encoders for pipe %c\n", 1082 num_encoders, pipe_name(master_crtc->pipe)); 1083 1084 return encoder; 1085 } 1086 1087 static void cpt_verify_modeset(struct drm_i915_private *dev_priv, 1088 enum pipe pipe) 1089 { 1090 i915_reg_t dslreg = PIPEDSL(pipe); 1091 u32 temp; 1092 1093 temp = intel_de_read(dev_priv, dslreg); 1094 udelay(500); 1095 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) { 1096 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) 1097 drm_err(&dev_priv->drm, 1098 "mode set failed: pipe %c stuck\n", 1099 pipe_name(pipe)); 1100 } 1101 } 1102 1103 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state) 1104 { 1105 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1106 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1107 const struct drm_rect *dst = &crtc_state->pch_pfit.dst; 1108 enum pipe pipe = crtc->pipe; 1109 int width = drm_rect_width(dst); 1110 int height = drm_rect_height(dst); 1111 int x = dst->x1; 1112 int y = dst->y1; 1113 1114 if (!crtc_state->pch_pfit.enabled) 1115 return; 1116 1117 /* Force use of hard-coded filter coefficients 1118 * as some pre-programmed values are broken, 1119 * e.g. x201. 1120 */ 1121 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) 1122 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 1123 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe)); 1124 else 1125 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 1126 PF_FILTER_MED_3x3); 1127 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), x << 16 | y); 1128 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), width << 16 | height); 1129 } 1130 1131 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc) 1132 { 1133 if (crtc->overlay) 1134 (void) intel_overlay_switch_off(crtc->overlay); 1135 1136 /* Let userspace switch the overlay on again. In most cases userspace 1137 * has to recompute where to put it anyway. 1138 */ 1139 } 1140 1141 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state) 1142 { 1143 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1144 1145 if (!crtc_state->nv12_planes) 1146 return false; 1147 1148 /* WA Display #0827: Gen9:all */ 1149 if (DISPLAY_VER(dev_priv) == 9) 1150 return true; 1151 1152 return false; 1153 } 1154 1155 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state) 1156 { 1157 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1158 1159 /* Wa_2006604312:icl,ehl */ 1160 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11) 1161 return true; 1162 1163 return false; 1164 } 1165 1166 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state) 1167 { 1168 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1169 1170 /* Wa_1604331009:icl,jsl,ehl */ 1171 if (is_hdr_mode(crtc_state) && 1172 crtc_state->active_planes & BIT(PLANE_CURSOR) && 1173 DISPLAY_VER(dev_priv) == 11) 1174 return true; 1175 1176 return false; 1177 } 1178 1179 static void intel_async_flip_vtd_wa(struct drm_i915_private *i915, 1180 enum pipe pipe, bool enable) 1181 { 1182 if (DISPLAY_VER(i915) == 9) { 1183 /* 1184 * "Plane N strech max must be programmed to 11b (x1) 1185 * when Async flips are enabled on that plane." 1186 */ 1187 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 1188 SKL_PLANE1_STRETCH_MAX_MASK, 1189 enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8); 1190 } else { 1191 /* Also needed on HSW/BDW albeit undocumented */ 1192 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 1193 HSW_PRI_STRETCH_MAX_MASK, 1194 enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8); 1195 } 1196 } 1197 1198 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state) 1199 { 1200 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1201 1202 return crtc_state->uapi.async_flip && i915_vtd_active(i915) && 1203 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915)); 1204 } 1205 1206 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state, 1207 const struct intel_crtc_state *new_crtc_state) 1208 { 1209 return (!old_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)) && 1210 new_crtc_state->active_planes; 1211 } 1212 1213 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state, 1214 const struct intel_crtc_state *new_crtc_state) 1215 { 1216 return old_crtc_state->active_planes && 1217 (!new_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)); 1218 } 1219 1220 static void intel_post_plane_update(struct intel_atomic_state *state, 1221 struct intel_crtc *crtc) 1222 { 1223 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1224 const struct intel_crtc_state *old_crtc_state = 1225 intel_atomic_get_old_crtc_state(state, crtc); 1226 const struct intel_crtc_state *new_crtc_state = 1227 intel_atomic_get_new_crtc_state(state, crtc); 1228 enum pipe pipe = crtc->pipe; 1229 1230 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); 1231 1232 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) 1233 intel_update_watermarks(dev_priv); 1234 1235 hsw_ips_post_update(state, crtc); 1236 intel_fbc_post_update(state, crtc); 1237 1238 if (needs_async_flip_vtd_wa(old_crtc_state) && 1239 !needs_async_flip_vtd_wa(new_crtc_state)) 1240 intel_async_flip_vtd_wa(dev_priv, pipe, false); 1241 1242 if (needs_nv12_wa(old_crtc_state) && 1243 !needs_nv12_wa(new_crtc_state)) 1244 skl_wa_827(dev_priv, pipe, false); 1245 1246 if (needs_scalerclk_wa(old_crtc_state) && 1247 !needs_scalerclk_wa(new_crtc_state)) 1248 icl_wa_scalerclkgating(dev_priv, pipe, false); 1249 1250 if (needs_cursorclk_wa(old_crtc_state) && 1251 !needs_cursorclk_wa(new_crtc_state)) 1252 icl_wa_cursorclkgating(dev_priv, pipe, false); 1253 1254 intel_drrs_activate(new_crtc_state); 1255 } 1256 1257 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state, 1258 struct intel_crtc *crtc) 1259 { 1260 const struct intel_crtc_state *crtc_state = 1261 intel_atomic_get_new_crtc_state(state, crtc); 1262 u8 update_planes = crtc_state->update_planes; 1263 const struct intel_plane_state *plane_state; 1264 struct intel_plane *plane; 1265 int i; 1266 1267 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1268 if (plane->pipe == crtc->pipe && 1269 update_planes & BIT(plane->id)) 1270 plane->enable_flip_done(plane); 1271 } 1272 } 1273 1274 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state, 1275 struct intel_crtc *crtc) 1276 { 1277 const struct intel_crtc_state *crtc_state = 1278 intel_atomic_get_new_crtc_state(state, crtc); 1279 u8 update_planes = crtc_state->update_planes; 1280 const struct intel_plane_state *plane_state; 1281 struct intel_plane *plane; 1282 int i; 1283 1284 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1285 if (plane->pipe == crtc->pipe && 1286 update_planes & BIT(plane->id)) 1287 plane->disable_flip_done(plane); 1288 } 1289 } 1290 1291 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state, 1292 struct intel_crtc *crtc) 1293 { 1294 const struct intel_crtc_state *old_crtc_state = 1295 intel_atomic_get_old_crtc_state(state, crtc); 1296 const struct intel_crtc_state *new_crtc_state = 1297 intel_atomic_get_new_crtc_state(state, crtc); 1298 u8 update_planes = new_crtc_state->update_planes; 1299 const struct intel_plane_state *old_plane_state; 1300 struct intel_plane *plane; 1301 bool need_vbl_wait = false; 1302 int i; 1303 1304 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1305 if (plane->need_async_flip_disable_wa && 1306 plane->pipe == crtc->pipe && 1307 update_planes & BIT(plane->id)) { 1308 /* 1309 * Apart from the async flip bit we want to 1310 * preserve the old state for the plane. 1311 */ 1312 plane->async_flip(plane, old_crtc_state, 1313 old_plane_state, false); 1314 need_vbl_wait = true; 1315 } 1316 } 1317 1318 if (need_vbl_wait) 1319 intel_crtc_wait_for_next_vblank(crtc); 1320 } 1321 1322 static void intel_pre_plane_update(struct intel_atomic_state *state, 1323 struct intel_crtc *crtc) 1324 { 1325 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1326 const struct intel_crtc_state *old_crtc_state = 1327 intel_atomic_get_old_crtc_state(state, crtc); 1328 const struct intel_crtc_state *new_crtc_state = 1329 intel_atomic_get_new_crtc_state(state, crtc); 1330 enum pipe pipe = crtc->pipe; 1331 1332 intel_drrs_deactivate(old_crtc_state); 1333 1334 intel_psr_pre_plane_update(state, crtc); 1335 1336 if (hsw_ips_pre_update(state, crtc)) 1337 intel_crtc_wait_for_next_vblank(crtc); 1338 1339 if (intel_fbc_pre_update(state, crtc)) 1340 intel_crtc_wait_for_next_vblank(crtc); 1341 1342 if (!needs_async_flip_vtd_wa(old_crtc_state) && 1343 needs_async_flip_vtd_wa(new_crtc_state)) 1344 intel_async_flip_vtd_wa(dev_priv, pipe, true); 1345 1346 /* Display WA 827 */ 1347 if (!needs_nv12_wa(old_crtc_state) && 1348 needs_nv12_wa(new_crtc_state)) 1349 skl_wa_827(dev_priv, pipe, true); 1350 1351 /* Wa_2006604312:icl,ehl */ 1352 if (!needs_scalerclk_wa(old_crtc_state) && 1353 needs_scalerclk_wa(new_crtc_state)) 1354 icl_wa_scalerclkgating(dev_priv, pipe, true); 1355 1356 /* Wa_1604331009:icl,jsl,ehl */ 1357 if (!needs_cursorclk_wa(old_crtc_state) && 1358 needs_cursorclk_wa(new_crtc_state)) 1359 icl_wa_cursorclkgating(dev_priv, pipe, true); 1360 1361 /* 1362 * Vblank time updates from the shadow to live plane control register 1363 * are blocked if the memory self-refresh mode is active at that 1364 * moment. So to make sure the plane gets truly disabled, disable 1365 * first the self-refresh mode. The self-refresh enable bit in turn 1366 * will be checked/applied by the HW only at the next frame start 1367 * event which is after the vblank start event, so we need to have a 1368 * wait-for-vblank between disabling the plane and the pipe. 1369 */ 1370 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active && 1371 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) 1372 intel_crtc_wait_for_next_vblank(crtc); 1373 1374 /* 1375 * IVB workaround: must disable low power watermarks for at least 1376 * one frame before enabling scaling. LP watermarks can be re-enabled 1377 * when scaling is disabled. 1378 * 1379 * WaCxSRDisabledForSpriteScaling:ivb 1380 */ 1381 if (old_crtc_state->hw.active && 1382 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv)) 1383 intel_crtc_wait_for_next_vblank(crtc); 1384 1385 /* 1386 * If we're doing a modeset we don't need to do any 1387 * pre-vblank watermark programming here. 1388 */ 1389 if (!intel_crtc_needs_modeset(new_crtc_state)) { 1390 /* 1391 * For platforms that support atomic watermarks, program the 1392 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these 1393 * will be the intermediate values that are safe for both pre- and 1394 * post- vblank; when vblank happens, the 'active' values will be set 1395 * to the final 'target' values and we'll do this again to get the 1396 * optimal watermarks. For gen9+ platforms, the values we program here 1397 * will be the final target values which will get automatically latched 1398 * at vblank time; no further programming will be necessary. 1399 * 1400 * If a platform hasn't been transitioned to atomic watermarks yet, 1401 * we'll continue to update watermarks the old way, if flags tell 1402 * us to. 1403 */ 1404 if (!intel_initial_watermarks(state, crtc)) 1405 if (new_crtc_state->update_wm_pre) 1406 intel_update_watermarks(dev_priv); 1407 } 1408 1409 /* 1410 * Gen2 reports pipe underruns whenever all planes are disabled. 1411 * So disable underrun reporting before all the planes get disabled. 1412 * 1413 * We do this after .initial_watermarks() so that we have a 1414 * chance of catching underruns with the intermediate watermarks 1415 * vs. the old plane configuration. 1416 */ 1417 if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state)) 1418 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1419 1420 /* 1421 * WA for platforms where async address update enable bit 1422 * is double buffered and only latched at start of vblank. 1423 */ 1424 if (old_crtc_state->uapi.async_flip && !new_crtc_state->uapi.async_flip) 1425 intel_crtc_async_flip_disable_wa(state, crtc); 1426 } 1427 1428 static void intel_crtc_disable_planes(struct intel_atomic_state *state, 1429 struct intel_crtc *crtc) 1430 { 1431 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1432 const struct intel_crtc_state *new_crtc_state = 1433 intel_atomic_get_new_crtc_state(state, crtc); 1434 unsigned int update_mask = new_crtc_state->update_planes; 1435 const struct intel_plane_state *old_plane_state; 1436 struct intel_plane *plane; 1437 unsigned fb_bits = 0; 1438 int i; 1439 1440 intel_crtc_dpms_overlay_disable(crtc); 1441 1442 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1443 if (crtc->pipe != plane->pipe || 1444 !(update_mask & BIT(plane->id))) 1445 continue; 1446 1447 intel_plane_disable_arm(plane, new_crtc_state); 1448 1449 if (old_plane_state->uapi.visible) 1450 fb_bits |= plane->frontbuffer_bit; 1451 } 1452 1453 intel_frontbuffer_flip(dev_priv, fb_bits); 1454 } 1455 1456 /* 1457 * intel_connector_primary_encoder - get the primary encoder for a connector 1458 * @connector: connector for which to return the encoder 1459 * 1460 * Returns the primary encoder for a connector. There is a 1:1 mapping from 1461 * all connectors to their encoder, except for DP-MST connectors which have 1462 * both a virtual and a primary encoder. These DP-MST primary encoders can be 1463 * pointed to by as many DP-MST connectors as there are pipes. 1464 */ 1465 static struct intel_encoder * 1466 intel_connector_primary_encoder(struct intel_connector *connector) 1467 { 1468 struct intel_encoder *encoder; 1469 1470 if (connector->mst_port) 1471 return &dp_to_dig_port(connector->mst_port)->base; 1472 1473 encoder = intel_attached_encoder(connector); 1474 drm_WARN_ON(connector->base.dev, !encoder); 1475 1476 return encoder; 1477 } 1478 1479 static void intel_encoders_update_prepare(struct intel_atomic_state *state) 1480 { 1481 struct drm_i915_private *i915 = to_i915(state->base.dev); 1482 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 1483 struct intel_crtc *crtc; 1484 struct drm_connector_state *new_conn_state; 1485 struct drm_connector *connector; 1486 int i; 1487 1488 /* 1489 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits. 1490 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook. 1491 */ 1492 if (i915->dpll.mgr) { 1493 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1494 if (intel_crtc_needs_modeset(new_crtc_state)) 1495 continue; 1496 1497 new_crtc_state->shared_dpll = old_crtc_state->shared_dpll; 1498 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state; 1499 } 1500 } 1501 1502 if (!state->modeset) 1503 return; 1504 1505 for_each_new_connector_in_state(&state->base, connector, new_conn_state, 1506 i) { 1507 struct intel_connector *intel_connector; 1508 struct intel_encoder *encoder; 1509 struct intel_crtc *crtc; 1510 1511 if (!intel_connector_needs_modeset(state, connector)) 1512 continue; 1513 1514 intel_connector = to_intel_connector(connector); 1515 encoder = intel_connector_primary_encoder(intel_connector); 1516 if (!encoder->update_prepare) 1517 continue; 1518 1519 crtc = new_conn_state->crtc ? 1520 to_intel_crtc(new_conn_state->crtc) : NULL; 1521 encoder->update_prepare(state, encoder, crtc); 1522 } 1523 } 1524 1525 static void intel_encoders_update_complete(struct intel_atomic_state *state) 1526 { 1527 struct drm_connector_state *new_conn_state; 1528 struct drm_connector *connector; 1529 int i; 1530 1531 if (!state->modeset) 1532 return; 1533 1534 for_each_new_connector_in_state(&state->base, connector, new_conn_state, 1535 i) { 1536 struct intel_connector *intel_connector; 1537 struct intel_encoder *encoder; 1538 struct intel_crtc *crtc; 1539 1540 if (!intel_connector_needs_modeset(state, connector)) 1541 continue; 1542 1543 intel_connector = to_intel_connector(connector); 1544 encoder = intel_connector_primary_encoder(intel_connector); 1545 if (!encoder->update_complete) 1546 continue; 1547 1548 crtc = new_conn_state->crtc ? 1549 to_intel_crtc(new_conn_state->crtc) : NULL; 1550 encoder->update_complete(state, encoder, crtc); 1551 } 1552 } 1553 1554 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state, 1555 struct intel_crtc *crtc) 1556 { 1557 const struct intel_crtc_state *crtc_state = 1558 intel_atomic_get_new_crtc_state(state, crtc); 1559 const struct drm_connector_state *conn_state; 1560 struct drm_connector *conn; 1561 int i; 1562 1563 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1564 struct intel_encoder *encoder = 1565 to_intel_encoder(conn_state->best_encoder); 1566 1567 if (conn_state->crtc != &crtc->base) 1568 continue; 1569 1570 if (encoder->pre_pll_enable) 1571 encoder->pre_pll_enable(state, encoder, 1572 crtc_state, conn_state); 1573 } 1574 } 1575 1576 static void intel_encoders_pre_enable(struct intel_atomic_state *state, 1577 struct intel_crtc *crtc) 1578 { 1579 const struct intel_crtc_state *crtc_state = 1580 intel_atomic_get_new_crtc_state(state, crtc); 1581 const struct drm_connector_state *conn_state; 1582 struct drm_connector *conn; 1583 int i; 1584 1585 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1586 struct intel_encoder *encoder = 1587 to_intel_encoder(conn_state->best_encoder); 1588 1589 if (conn_state->crtc != &crtc->base) 1590 continue; 1591 1592 if (encoder->pre_enable) 1593 encoder->pre_enable(state, encoder, 1594 crtc_state, conn_state); 1595 } 1596 } 1597 1598 static void intel_encoders_enable(struct intel_atomic_state *state, 1599 struct intel_crtc *crtc) 1600 { 1601 const struct intel_crtc_state *crtc_state = 1602 intel_atomic_get_new_crtc_state(state, crtc); 1603 const struct drm_connector_state *conn_state; 1604 struct drm_connector *conn; 1605 int i; 1606 1607 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1608 struct intel_encoder *encoder = 1609 to_intel_encoder(conn_state->best_encoder); 1610 1611 if (conn_state->crtc != &crtc->base) 1612 continue; 1613 1614 if (encoder->enable) 1615 encoder->enable(state, encoder, 1616 crtc_state, conn_state); 1617 intel_opregion_notify_encoder(encoder, true); 1618 } 1619 } 1620 1621 static void intel_encoders_disable(struct intel_atomic_state *state, 1622 struct intel_crtc *crtc) 1623 { 1624 const struct intel_crtc_state *old_crtc_state = 1625 intel_atomic_get_old_crtc_state(state, crtc); 1626 const struct drm_connector_state *old_conn_state; 1627 struct drm_connector *conn; 1628 int i; 1629 1630 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1631 struct intel_encoder *encoder = 1632 to_intel_encoder(old_conn_state->best_encoder); 1633 1634 if (old_conn_state->crtc != &crtc->base) 1635 continue; 1636 1637 intel_opregion_notify_encoder(encoder, false); 1638 if (encoder->disable) 1639 encoder->disable(state, encoder, 1640 old_crtc_state, old_conn_state); 1641 } 1642 } 1643 1644 static void intel_encoders_post_disable(struct intel_atomic_state *state, 1645 struct intel_crtc *crtc) 1646 { 1647 const struct intel_crtc_state *old_crtc_state = 1648 intel_atomic_get_old_crtc_state(state, crtc); 1649 const struct drm_connector_state *old_conn_state; 1650 struct drm_connector *conn; 1651 int i; 1652 1653 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1654 struct intel_encoder *encoder = 1655 to_intel_encoder(old_conn_state->best_encoder); 1656 1657 if (old_conn_state->crtc != &crtc->base) 1658 continue; 1659 1660 if (encoder->post_disable) 1661 encoder->post_disable(state, encoder, 1662 old_crtc_state, old_conn_state); 1663 } 1664 } 1665 1666 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state, 1667 struct intel_crtc *crtc) 1668 { 1669 const struct intel_crtc_state *old_crtc_state = 1670 intel_atomic_get_old_crtc_state(state, crtc); 1671 const struct drm_connector_state *old_conn_state; 1672 struct drm_connector *conn; 1673 int i; 1674 1675 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1676 struct intel_encoder *encoder = 1677 to_intel_encoder(old_conn_state->best_encoder); 1678 1679 if (old_conn_state->crtc != &crtc->base) 1680 continue; 1681 1682 if (encoder->post_pll_disable) 1683 encoder->post_pll_disable(state, encoder, 1684 old_crtc_state, old_conn_state); 1685 } 1686 } 1687 1688 static void intel_encoders_update_pipe(struct intel_atomic_state *state, 1689 struct intel_crtc *crtc) 1690 { 1691 const struct intel_crtc_state *crtc_state = 1692 intel_atomic_get_new_crtc_state(state, crtc); 1693 const struct drm_connector_state *conn_state; 1694 struct drm_connector *conn; 1695 int i; 1696 1697 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1698 struct intel_encoder *encoder = 1699 to_intel_encoder(conn_state->best_encoder); 1700 1701 if (conn_state->crtc != &crtc->base) 1702 continue; 1703 1704 if (encoder->update_pipe) 1705 encoder->update_pipe(state, encoder, 1706 crtc_state, conn_state); 1707 } 1708 } 1709 1710 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state) 1711 { 1712 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1713 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 1714 1715 plane->disable_arm(plane, crtc_state); 1716 } 1717 1718 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1719 { 1720 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1721 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1722 1723 if (crtc_state->has_pch_encoder) { 1724 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1725 &crtc_state->fdi_m_n); 1726 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1727 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1728 &crtc_state->dp_m_n); 1729 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1730 &crtc_state->dp_m2_n2); 1731 } 1732 1733 intel_set_transcoder_timings(crtc_state); 1734 1735 ilk_set_pipeconf(crtc_state); 1736 } 1737 1738 static void ilk_crtc_enable(struct intel_atomic_state *state, 1739 struct intel_crtc *crtc) 1740 { 1741 const struct intel_crtc_state *new_crtc_state = 1742 intel_atomic_get_new_crtc_state(state, crtc); 1743 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1744 enum pipe pipe = crtc->pipe; 1745 1746 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1747 return; 1748 1749 /* 1750 * Sometimes spurious CPU pipe underruns happen during FDI 1751 * training, at least with VGA+HDMI cloning. Suppress them. 1752 * 1753 * On ILK we get an occasional spurious CPU pipe underruns 1754 * between eDP port A enable and vdd enable. Also PCH port 1755 * enable seems to result in the occasional CPU pipe underrun. 1756 * 1757 * Spurious PCH underruns also occur during PCH enabling. 1758 */ 1759 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1760 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 1761 1762 ilk_configure_cpu_transcoder(new_crtc_state); 1763 1764 intel_set_pipe_src_size(new_crtc_state); 1765 1766 crtc->active = true; 1767 1768 intel_encoders_pre_enable(state, crtc); 1769 1770 if (new_crtc_state->has_pch_encoder) { 1771 ilk_pch_pre_enable(state, crtc); 1772 } else { 1773 assert_fdi_tx_disabled(dev_priv, pipe); 1774 assert_fdi_rx_disabled(dev_priv, pipe); 1775 } 1776 1777 ilk_pfit_enable(new_crtc_state); 1778 1779 /* 1780 * On ILK+ LUT must be loaded before the pipe is running but with 1781 * clocks enabled 1782 */ 1783 intel_color_load_luts(new_crtc_state); 1784 intel_color_commit_noarm(new_crtc_state); 1785 intel_color_commit_arm(new_crtc_state); 1786 /* update DSPCNTR to configure gamma for pipe bottom color */ 1787 intel_disable_primary_plane(new_crtc_state); 1788 1789 intel_initial_watermarks(state, crtc); 1790 intel_enable_transcoder(new_crtc_state); 1791 1792 if (new_crtc_state->has_pch_encoder) 1793 ilk_pch_enable(state, crtc); 1794 1795 intel_crtc_vblank_on(new_crtc_state); 1796 1797 intel_encoders_enable(state, crtc); 1798 1799 if (HAS_PCH_CPT(dev_priv)) 1800 cpt_verify_modeset(dev_priv, pipe); 1801 1802 /* 1803 * Must wait for vblank to avoid spurious PCH FIFO underruns. 1804 * And a second vblank wait is needed at least on ILK with 1805 * some interlaced HDMI modes. Let's do the double wait always 1806 * in case there are more corner cases we don't know about. 1807 */ 1808 if (new_crtc_state->has_pch_encoder) { 1809 intel_crtc_wait_for_next_vblank(crtc); 1810 intel_crtc_wait_for_next_vblank(crtc); 1811 } 1812 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1813 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 1814 } 1815 1816 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, 1817 enum pipe pipe, bool apply) 1818 { 1819 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)); 1820 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS; 1821 1822 if (apply) 1823 val |= mask; 1824 else 1825 val &= ~mask; 1826 1827 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val); 1828 } 1829 1830 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state) 1831 { 1832 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1833 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1834 1835 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe), 1836 HSW_LINETIME(crtc_state->linetime) | 1837 HSW_IPS_LINETIME(crtc_state->ips_linetime)); 1838 } 1839 1840 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) 1841 { 1842 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1843 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1844 i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder); 1845 u32 val; 1846 1847 val = intel_de_read(dev_priv, reg); 1848 val &= ~HSW_FRAME_START_DELAY_MASK; 1849 val |= HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 1850 intel_de_write(dev_priv, reg, val); 1851 } 1852 1853 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state, 1854 const struct intel_crtc_state *crtc_state) 1855 { 1856 struct intel_crtc *master_crtc = intel_master_crtc(crtc_state); 1857 1858 /* 1859 * Enable sequence steps 1-7 on bigjoiner master 1860 */ 1861 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1862 intel_encoders_pre_pll_enable(state, master_crtc); 1863 1864 if (crtc_state->shared_dpll) 1865 intel_enable_shared_dpll(crtc_state); 1866 1867 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1868 intel_encoders_pre_enable(state, master_crtc); 1869 } 1870 1871 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1872 { 1873 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1874 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1875 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1876 1877 if (crtc_state->has_pch_encoder) { 1878 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1879 &crtc_state->fdi_m_n); 1880 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1881 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1882 &crtc_state->dp_m_n); 1883 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1884 &crtc_state->dp_m2_n2); 1885 } 1886 1887 intel_set_transcoder_timings(crtc_state); 1888 1889 if (cpu_transcoder != TRANSCODER_EDP) 1890 intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder), 1891 crtc_state->pixel_multiplier - 1); 1892 1893 hsw_set_frame_start_delay(crtc_state); 1894 1895 hsw_set_transconf(crtc_state); 1896 } 1897 1898 static void hsw_crtc_enable(struct intel_atomic_state *state, 1899 struct intel_crtc *crtc) 1900 { 1901 const struct intel_crtc_state *new_crtc_state = 1902 intel_atomic_get_new_crtc_state(state, crtc); 1903 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1904 enum pipe pipe = crtc->pipe, hsw_workaround_pipe; 1905 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 1906 bool psl_clkgate_wa; 1907 1908 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1909 return; 1910 1911 if (!new_crtc_state->bigjoiner_pipes) { 1912 intel_encoders_pre_pll_enable(state, crtc); 1913 1914 if (new_crtc_state->shared_dpll) 1915 intel_enable_shared_dpll(new_crtc_state); 1916 1917 intel_encoders_pre_enable(state, crtc); 1918 } else { 1919 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state); 1920 } 1921 1922 intel_dsc_enable(new_crtc_state); 1923 1924 if (DISPLAY_VER(dev_priv) >= 13) 1925 intel_uncompressed_joiner_enable(new_crtc_state); 1926 1927 intel_set_pipe_src_size(new_crtc_state); 1928 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 1929 bdw_set_pipemisc(new_crtc_state); 1930 1931 if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) && 1932 !transcoder_is_dsi(cpu_transcoder)) 1933 hsw_configure_cpu_transcoder(new_crtc_state); 1934 1935 crtc->active = true; 1936 1937 /* Display WA #1180: WaDisableScalarClockGating: glk */ 1938 psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 && 1939 new_crtc_state->pch_pfit.enabled; 1940 if (psl_clkgate_wa) 1941 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true); 1942 1943 if (DISPLAY_VER(dev_priv) >= 9) 1944 skl_pfit_enable(new_crtc_state); 1945 else 1946 ilk_pfit_enable(new_crtc_state); 1947 1948 /* 1949 * On ILK+ LUT must be loaded before the pipe is running but with 1950 * clocks enabled 1951 */ 1952 intel_color_load_luts(new_crtc_state); 1953 intel_color_commit_noarm(new_crtc_state); 1954 intel_color_commit_arm(new_crtc_state); 1955 /* update DSPCNTR to configure gamma/csc for pipe bottom color */ 1956 if (DISPLAY_VER(dev_priv) < 9) 1957 intel_disable_primary_plane(new_crtc_state); 1958 1959 hsw_set_linetime_wm(new_crtc_state); 1960 1961 if (DISPLAY_VER(dev_priv) >= 11) 1962 icl_set_pipe_chicken(new_crtc_state); 1963 1964 intel_initial_watermarks(state, crtc); 1965 1966 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 1967 intel_crtc_vblank_on(new_crtc_state); 1968 1969 intel_encoders_enable(state, crtc); 1970 1971 if (psl_clkgate_wa) { 1972 intel_crtc_wait_for_next_vblank(crtc); 1973 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false); 1974 } 1975 1976 /* If we change the relative order between pipe/planes enabling, we need 1977 * to change the workaround. */ 1978 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe; 1979 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { 1980 struct intel_crtc *wa_crtc; 1981 1982 wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe); 1983 1984 intel_crtc_wait_for_next_vblank(wa_crtc); 1985 intel_crtc_wait_for_next_vblank(wa_crtc); 1986 } 1987 } 1988 1989 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state) 1990 { 1991 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1992 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1993 enum pipe pipe = crtc->pipe; 1994 1995 /* To avoid upsetting the power well on haswell only disable the pfit if 1996 * it's in use. The hw state code will make sure we get this right. */ 1997 if (!old_crtc_state->pch_pfit.enabled) 1998 return; 1999 2000 intel_de_write_fw(dev_priv, PF_CTL(pipe), 0); 2001 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0); 2002 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0); 2003 } 2004 2005 static void ilk_crtc_disable(struct intel_atomic_state *state, 2006 struct intel_crtc *crtc) 2007 { 2008 const struct intel_crtc_state *old_crtc_state = 2009 intel_atomic_get_old_crtc_state(state, crtc); 2010 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2011 enum pipe pipe = crtc->pipe; 2012 2013 /* 2014 * Sometimes spurious CPU pipe underruns happen when the 2015 * pipe is already disabled, but FDI RX/TX is still enabled. 2016 * Happens at least with VGA+HDMI cloning. Suppress them. 2017 */ 2018 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 2019 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 2020 2021 intel_encoders_disable(state, crtc); 2022 2023 intel_crtc_vblank_off(old_crtc_state); 2024 2025 intel_disable_transcoder(old_crtc_state); 2026 2027 ilk_pfit_disable(old_crtc_state); 2028 2029 if (old_crtc_state->has_pch_encoder) 2030 ilk_pch_disable(state, crtc); 2031 2032 intel_encoders_post_disable(state, crtc); 2033 2034 if (old_crtc_state->has_pch_encoder) 2035 ilk_pch_post_disable(state, crtc); 2036 2037 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2038 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 2039 } 2040 2041 static void hsw_crtc_disable(struct intel_atomic_state *state, 2042 struct intel_crtc *crtc) 2043 { 2044 const struct intel_crtc_state *old_crtc_state = 2045 intel_atomic_get_old_crtc_state(state, crtc); 2046 2047 /* 2048 * FIXME collapse everything to one hook. 2049 * Need care with mst->ddi interactions. 2050 */ 2051 if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) { 2052 intel_encoders_disable(state, crtc); 2053 intel_encoders_post_disable(state, crtc); 2054 } 2055 } 2056 2057 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) 2058 { 2059 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2060 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2061 2062 if (!crtc_state->gmch_pfit.control) 2063 return; 2064 2065 /* 2066 * The panel fitter should only be adjusted whilst the pipe is disabled, 2067 * according to register description and PRM. 2068 */ 2069 drm_WARN_ON(&dev_priv->drm, 2070 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE); 2071 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 2072 2073 intel_de_write(dev_priv, PFIT_PGM_RATIOS, 2074 crtc_state->gmch_pfit.pgm_ratios); 2075 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control); 2076 2077 /* Border color in case we don't scale up to the full screen. Black by 2078 * default, change to something else for debugging. */ 2079 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); 2080 } 2081 2082 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) 2083 { 2084 if (phy == PHY_NONE) 2085 return false; 2086 else if (IS_DG2(dev_priv)) 2087 /* 2088 * DG2 outputs labelled as "combo PHY" in the bspec use 2089 * SNPS PHYs with completely different programming, 2090 * hence we always return false here. 2091 */ 2092 return false; 2093 else if (IS_ALDERLAKE_S(dev_priv)) 2094 return phy <= PHY_E; 2095 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) 2096 return phy <= PHY_D; 2097 else if (IS_JSL_EHL(dev_priv)) 2098 return phy <= PHY_C; 2099 else if (DISPLAY_VER(dev_priv) >= 11) 2100 return phy <= PHY_B; 2101 else 2102 return false; 2103 } 2104 2105 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) 2106 { 2107 if (IS_DG2(dev_priv)) 2108 /* DG2's "TC1" output uses a SNPS PHY */ 2109 return false; 2110 else if (IS_ALDERLAKE_P(dev_priv)) 2111 return phy >= PHY_F && phy <= PHY_I; 2112 else if (IS_TIGERLAKE(dev_priv)) 2113 return phy >= PHY_D && phy <= PHY_I; 2114 else if (IS_ICELAKE(dev_priv)) 2115 return phy >= PHY_C && phy <= PHY_F; 2116 else 2117 return false; 2118 } 2119 2120 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy) 2121 { 2122 if (phy == PHY_NONE) 2123 return false; 2124 else if (IS_DG2(dev_priv)) 2125 /* 2126 * All four "combo" ports and the TC1 port (PHY E) use 2127 * Synopsis PHYs. 2128 */ 2129 return phy <= PHY_E; 2130 2131 return false; 2132 } 2133 2134 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) 2135 { 2136 if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD) 2137 return PHY_D + port - PORT_D_XELPD; 2138 else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1) 2139 return PHY_F + port - PORT_TC1; 2140 else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1) 2141 return PHY_B + port - PORT_TC1; 2142 else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1) 2143 return PHY_C + port - PORT_TC1; 2144 else if (IS_JSL_EHL(i915) && port == PORT_D) 2145 return PHY_A; 2146 2147 return PHY_A + port - PORT_A; 2148 } 2149 2150 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) 2151 { 2152 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port))) 2153 return TC_PORT_NONE; 2154 2155 if (DISPLAY_VER(dev_priv) >= 12) 2156 return TC_PORT_1 + port - PORT_TC1; 2157 else 2158 return TC_PORT_1 + port - PORT_C; 2159 } 2160 2161 enum intel_display_power_domain 2162 intel_aux_power_domain(struct intel_digital_port *dig_port) 2163 { 2164 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 2165 2166 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 2167 return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch); 2168 2169 return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch); 2170 } 2171 2172 static void get_crtc_power_domains(struct intel_crtc_state *crtc_state, 2173 struct intel_power_domain_mask *mask) 2174 { 2175 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2176 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2177 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2178 struct drm_encoder *encoder; 2179 enum pipe pipe = crtc->pipe; 2180 2181 bitmap_zero(mask->bits, POWER_DOMAIN_NUM); 2182 2183 if (!crtc_state->hw.active) 2184 return; 2185 2186 set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits); 2187 set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits); 2188 if (crtc_state->pch_pfit.enabled || 2189 crtc_state->pch_pfit.force_thru) 2190 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits); 2191 2192 drm_for_each_encoder_mask(encoder, &dev_priv->drm, 2193 crtc_state->uapi.encoder_mask) { 2194 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2195 2196 set_bit(intel_encoder->power_domain, mask->bits); 2197 } 2198 2199 if (HAS_DDI(dev_priv) && crtc_state->has_audio) 2200 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits); 2201 2202 if (crtc_state->shared_dpll) 2203 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits); 2204 2205 if (crtc_state->dsc.compression_enable) 2206 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits); 2207 } 2208 2209 static void 2210 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, 2211 struct intel_power_domain_mask *old_domains) 2212 { 2213 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2214 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2215 enum intel_display_power_domain domain; 2216 struct intel_power_domain_mask domains, new_domains; 2217 2218 get_crtc_power_domains(crtc_state, &domains); 2219 2220 bitmap_andnot(new_domains.bits, 2221 domains.bits, 2222 crtc->enabled_power_domains.mask.bits, 2223 POWER_DOMAIN_NUM); 2224 bitmap_andnot(old_domains->bits, 2225 crtc->enabled_power_domains.mask.bits, 2226 domains.bits, 2227 POWER_DOMAIN_NUM); 2228 2229 for_each_power_domain(domain, &new_domains) 2230 intel_display_power_get_in_set(dev_priv, 2231 &crtc->enabled_power_domains, 2232 domain); 2233 } 2234 2235 static void modeset_put_crtc_power_domains(struct intel_crtc *crtc, 2236 struct intel_power_domain_mask *domains) 2237 { 2238 intel_display_power_put_mask_in_set(to_i915(crtc->base.dev), 2239 &crtc->enabled_power_domains, 2240 domains); 2241 } 2242 2243 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 2244 { 2245 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2246 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2247 2248 if (intel_crtc_has_dp_encoder(crtc_state)) { 2249 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 2250 &crtc_state->dp_m_n); 2251 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 2252 &crtc_state->dp_m2_n2); 2253 } 2254 2255 intel_set_transcoder_timings(crtc_state); 2256 2257 i9xx_set_pipeconf(crtc_state); 2258 } 2259 2260 static void valleyview_crtc_enable(struct intel_atomic_state *state, 2261 struct intel_crtc *crtc) 2262 { 2263 const struct intel_crtc_state *new_crtc_state = 2264 intel_atomic_get_new_crtc_state(state, crtc); 2265 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2266 enum pipe pipe = crtc->pipe; 2267 2268 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 2269 return; 2270 2271 i9xx_configure_cpu_transcoder(new_crtc_state); 2272 2273 intel_set_pipe_src_size(new_crtc_state); 2274 2275 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 2276 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY); 2277 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0); 2278 } 2279 2280 crtc->active = true; 2281 2282 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2283 2284 intel_encoders_pre_pll_enable(state, crtc); 2285 2286 if (IS_CHERRYVIEW(dev_priv)) 2287 chv_enable_pll(new_crtc_state); 2288 else 2289 vlv_enable_pll(new_crtc_state); 2290 2291 intel_encoders_pre_enable(state, crtc); 2292 2293 i9xx_pfit_enable(new_crtc_state); 2294 2295 intel_color_load_luts(new_crtc_state); 2296 intel_color_commit_noarm(new_crtc_state); 2297 intel_color_commit_arm(new_crtc_state); 2298 /* update DSPCNTR to configure gamma for pipe bottom color */ 2299 intel_disable_primary_plane(new_crtc_state); 2300 2301 intel_initial_watermarks(state, crtc); 2302 intel_enable_transcoder(new_crtc_state); 2303 2304 intel_crtc_vblank_on(new_crtc_state); 2305 2306 intel_encoders_enable(state, crtc); 2307 } 2308 2309 static void i9xx_crtc_enable(struct intel_atomic_state *state, 2310 struct intel_crtc *crtc) 2311 { 2312 const struct intel_crtc_state *new_crtc_state = 2313 intel_atomic_get_new_crtc_state(state, crtc); 2314 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2315 enum pipe pipe = crtc->pipe; 2316 2317 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 2318 return; 2319 2320 i9xx_configure_cpu_transcoder(new_crtc_state); 2321 2322 intel_set_pipe_src_size(new_crtc_state); 2323 2324 crtc->active = true; 2325 2326 if (DISPLAY_VER(dev_priv) != 2) 2327 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2328 2329 intel_encoders_pre_enable(state, crtc); 2330 2331 i9xx_enable_pll(new_crtc_state); 2332 2333 i9xx_pfit_enable(new_crtc_state); 2334 2335 intel_color_load_luts(new_crtc_state); 2336 intel_color_commit_noarm(new_crtc_state); 2337 intel_color_commit_arm(new_crtc_state); 2338 /* update DSPCNTR to configure gamma for pipe bottom color */ 2339 intel_disable_primary_plane(new_crtc_state); 2340 2341 if (!intel_initial_watermarks(state, crtc)) 2342 intel_update_watermarks(dev_priv); 2343 intel_enable_transcoder(new_crtc_state); 2344 2345 intel_crtc_vblank_on(new_crtc_state); 2346 2347 intel_encoders_enable(state, crtc); 2348 2349 /* prevents spurious underruns */ 2350 if (DISPLAY_VER(dev_priv) == 2) 2351 intel_crtc_wait_for_next_vblank(crtc); 2352 } 2353 2354 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) 2355 { 2356 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 2357 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2358 2359 if (!old_crtc_state->gmch_pfit.control) 2360 return; 2361 2362 assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder); 2363 2364 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n", 2365 intel_de_read(dev_priv, PFIT_CONTROL)); 2366 intel_de_write(dev_priv, PFIT_CONTROL, 0); 2367 } 2368 2369 static void i9xx_crtc_disable(struct intel_atomic_state *state, 2370 struct intel_crtc *crtc) 2371 { 2372 struct intel_crtc_state *old_crtc_state = 2373 intel_atomic_get_old_crtc_state(state, crtc); 2374 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2375 enum pipe pipe = crtc->pipe; 2376 2377 /* 2378 * On gen2 planes are double buffered but the pipe isn't, so we must 2379 * wait for planes to fully turn off before disabling the pipe. 2380 */ 2381 if (DISPLAY_VER(dev_priv) == 2) 2382 intel_crtc_wait_for_next_vblank(crtc); 2383 2384 intel_encoders_disable(state, crtc); 2385 2386 intel_crtc_vblank_off(old_crtc_state); 2387 2388 intel_disable_transcoder(old_crtc_state); 2389 2390 i9xx_pfit_disable(old_crtc_state); 2391 2392 intel_encoders_post_disable(state, crtc); 2393 2394 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) { 2395 if (IS_CHERRYVIEW(dev_priv)) 2396 chv_disable_pll(dev_priv, pipe); 2397 else if (IS_VALLEYVIEW(dev_priv)) 2398 vlv_disable_pll(dev_priv, pipe); 2399 else 2400 i9xx_disable_pll(old_crtc_state); 2401 } 2402 2403 intel_encoders_post_pll_disable(state, crtc); 2404 2405 if (DISPLAY_VER(dev_priv) != 2) 2406 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 2407 2408 if (!dev_priv->wm_disp->initial_watermarks) 2409 intel_update_watermarks(dev_priv); 2410 2411 /* clock the pipe down to 640x480@60 to potentially save power */ 2412 if (IS_I830(dev_priv)) 2413 i830_enable_pipe(dev_priv, pipe); 2414 } 2415 2416 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, 2417 struct drm_modeset_acquire_ctx *ctx) 2418 { 2419 struct intel_encoder *encoder; 2420 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2421 struct intel_bw_state *bw_state = 2422 to_intel_bw_state(dev_priv->bw_obj.state); 2423 struct intel_cdclk_state *cdclk_state = 2424 to_intel_cdclk_state(dev_priv->cdclk.obj.state); 2425 struct intel_dbuf_state *dbuf_state = 2426 to_intel_dbuf_state(dev_priv->dbuf.obj.state); 2427 struct intel_crtc_state *crtc_state = 2428 to_intel_crtc_state(crtc->base.state); 2429 struct intel_plane *plane; 2430 struct drm_atomic_state *state; 2431 struct intel_crtc_state *temp_crtc_state; 2432 enum pipe pipe = crtc->pipe; 2433 int ret; 2434 2435 if (!crtc_state->hw.active) 2436 return; 2437 2438 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 2439 const struct intel_plane_state *plane_state = 2440 to_intel_plane_state(plane->base.state); 2441 2442 if (plane_state->uapi.visible) 2443 intel_plane_disable_noatomic(crtc, plane); 2444 } 2445 2446 state = drm_atomic_state_alloc(&dev_priv->drm); 2447 if (!state) { 2448 drm_dbg_kms(&dev_priv->drm, 2449 "failed to disable [CRTC:%d:%s], out of memory", 2450 crtc->base.base.id, crtc->base.name); 2451 return; 2452 } 2453 2454 state->acquire_ctx = ctx; 2455 2456 /* Everything's already locked, -EDEADLK can't happen. */ 2457 temp_crtc_state = intel_atomic_get_crtc_state(state, crtc); 2458 ret = drm_atomic_add_affected_connectors(state, &crtc->base); 2459 2460 drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret); 2461 2462 dev_priv->display->crtc_disable(to_intel_atomic_state(state), crtc); 2463 2464 drm_atomic_state_put(state); 2465 2466 drm_dbg_kms(&dev_priv->drm, 2467 "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", 2468 crtc->base.base.id, crtc->base.name); 2469 2470 crtc->active = false; 2471 crtc->base.enabled = false; 2472 2473 drm_WARN_ON(&dev_priv->drm, 2474 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0); 2475 crtc_state->uapi.active = false; 2476 crtc_state->uapi.connector_mask = 0; 2477 crtc_state->uapi.encoder_mask = 0; 2478 intel_crtc_free_hw_state(crtc_state); 2479 memset(&crtc_state->hw, 0, sizeof(crtc_state->hw)); 2480 2481 for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder) 2482 encoder->base.crtc = NULL; 2483 2484 intel_fbc_disable(crtc); 2485 intel_update_watermarks(dev_priv); 2486 intel_disable_shared_dpll(crtc_state); 2487 2488 intel_display_power_put_all_in_set(dev_priv, &crtc->enabled_power_domains); 2489 2490 cdclk_state->min_cdclk[pipe] = 0; 2491 cdclk_state->min_voltage_level[pipe] = 0; 2492 cdclk_state->active_pipes &= ~BIT(pipe); 2493 2494 dbuf_state->active_pipes &= ~BIT(pipe); 2495 2496 bw_state->data_rate[pipe] = 0; 2497 bw_state->num_active_planes[pipe] = 0; 2498 } 2499 2500 /* 2501 * turn all crtc's off, but do not adjust state 2502 * This has to be paired with a call to intel_modeset_setup_hw_state. 2503 */ 2504 int intel_display_suspend(struct drm_device *dev) 2505 { 2506 struct drm_i915_private *dev_priv = to_i915(dev); 2507 struct drm_atomic_state *state; 2508 int ret; 2509 2510 if (!HAS_DISPLAY(dev_priv)) 2511 return 0; 2512 2513 state = drm_atomic_helper_suspend(dev); 2514 ret = PTR_ERR_OR_ZERO(state); 2515 if (ret) 2516 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", 2517 ret); 2518 else 2519 dev_priv->modeset_restore_state = state; 2520 return ret; 2521 } 2522 2523 void intel_encoder_destroy(struct drm_encoder *encoder) 2524 { 2525 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2526 2527 drm_encoder_cleanup(encoder); 2528 kfree(intel_encoder); 2529 } 2530 2531 /* Cross check the actual hw state with our own modeset state tracking (and it's 2532 * internal consistency). */ 2533 static void intel_connector_verify_state(struct intel_crtc_state *crtc_state, 2534 struct drm_connector_state *conn_state) 2535 { 2536 struct intel_connector *connector = to_intel_connector(conn_state->connector); 2537 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2538 2539 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", 2540 connector->base.base.id, connector->base.name); 2541 2542 if (connector->get_hw_state(connector)) { 2543 struct intel_encoder *encoder = intel_attached_encoder(connector); 2544 2545 I915_STATE_WARN(!crtc_state, 2546 "connector enabled without attached crtc\n"); 2547 2548 if (!crtc_state) 2549 return; 2550 2551 I915_STATE_WARN(!crtc_state->hw.active, 2552 "connector is active, but attached crtc isn't\n"); 2553 2554 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) 2555 return; 2556 2557 I915_STATE_WARN(conn_state->best_encoder != &encoder->base, 2558 "atomic encoder doesn't match attached encoder\n"); 2559 2560 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, 2561 "attached encoder crtc differs from connector crtc\n"); 2562 } else { 2563 I915_STATE_WARN(crtc_state && crtc_state->hw.active, 2564 "attached crtc is active, but connector isn't\n"); 2565 I915_STATE_WARN(!crtc_state && conn_state->best_encoder, 2566 "best encoder set without crtc!\n"); 2567 } 2568 } 2569 2570 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) 2571 { 2572 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2573 2574 /* GDG double wide on either pipe, otherwise pipe A only */ 2575 return DISPLAY_VER(dev_priv) < 4 && 2576 (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); 2577 } 2578 2579 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) 2580 { 2581 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock; 2582 struct drm_rect src; 2583 2584 /* 2585 * We only use IF-ID interlacing. If we ever use 2586 * PF-ID we'll need to adjust the pixel_rate here. 2587 */ 2588 2589 if (!crtc_state->pch_pfit.enabled) 2590 return pixel_rate; 2591 2592 drm_rect_init(&src, 0, 0, 2593 drm_rect_width(&crtc_state->pipe_src) << 16, 2594 drm_rect_height(&crtc_state->pipe_src) << 16); 2595 2596 return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst, 2597 pixel_rate); 2598 } 2599 2600 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode, 2601 const struct drm_display_mode *timings) 2602 { 2603 mode->hdisplay = timings->crtc_hdisplay; 2604 mode->htotal = timings->crtc_htotal; 2605 mode->hsync_start = timings->crtc_hsync_start; 2606 mode->hsync_end = timings->crtc_hsync_end; 2607 2608 mode->vdisplay = timings->crtc_vdisplay; 2609 mode->vtotal = timings->crtc_vtotal; 2610 mode->vsync_start = timings->crtc_vsync_start; 2611 mode->vsync_end = timings->crtc_vsync_end; 2612 2613 mode->flags = timings->flags; 2614 mode->type = DRM_MODE_TYPE_DRIVER; 2615 2616 mode->clock = timings->crtc_clock; 2617 2618 drm_mode_set_name(mode); 2619 } 2620 2621 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) 2622 { 2623 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2624 2625 if (HAS_GMCH(dev_priv)) 2626 /* FIXME calculate proper pipe pixel rate for GMCH pfit */ 2627 crtc_state->pixel_rate = 2628 crtc_state->hw.pipe_mode.crtc_clock; 2629 else 2630 crtc_state->pixel_rate = 2631 ilk_pipe_pixel_rate(crtc_state); 2632 } 2633 2634 static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state *crtc_state, 2635 struct drm_display_mode *mode) 2636 { 2637 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2638 2639 if (num_pipes < 2) 2640 return; 2641 2642 mode->crtc_clock /= num_pipes; 2643 mode->crtc_hdisplay /= num_pipes; 2644 mode->crtc_hblank_start /= num_pipes; 2645 mode->crtc_hblank_end /= num_pipes; 2646 mode->crtc_hsync_start /= num_pipes; 2647 mode->crtc_hsync_end /= num_pipes; 2648 mode->crtc_htotal /= num_pipes; 2649 } 2650 2651 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state, 2652 struct drm_display_mode *mode) 2653 { 2654 int overlap = crtc_state->splitter.pixel_overlap; 2655 int n = crtc_state->splitter.link_count; 2656 2657 if (!crtc_state->splitter.enable) 2658 return; 2659 2660 /* 2661 * eDP MSO uses segment timings from EDID for transcoder 2662 * timings, but full mode for everything else. 2663 * 2664 * h_full = (h_segment - pixel_overlap) * link_count 2665 */ 2666 mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n; 2667 mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n; 2668 mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n; 2669 mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n; 2670 mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n; 2671 mode->crtc_htotal = (mode->crtc_htotal - overlap) * n; 2672 mode->crtc_clock *= n; 2673 } 2674 2675 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state) 2676 { 2677 struct drm_display_mode *mode = &crtc_state->hw.mode; 2678 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2679 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2680 2681 /* 2682 * Start with the adjusted_mode crtc timings, which 2683 * have been filled with the transcoder timings. 2684 */ 2685 drm_mode_copy(pipe_mode, adjusted_mode); 2686 2687 /* Expand MSO per-segment transcoder timings to full */ 2688 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2689 2690 /* 2691 * We want the full numbers in adjusted_mode normal timings, 2692 * adjusted_mode crtc timings are left with the raw transcoder 2693 * timings. 2694 */ 2695 intel_mode_from_crtc_timings(adjusted_mode, pipe_mode); 2696 2697 /* Populate the "user" mode with full numbers */ 2698 drm_mode_copy(mode, pipe_mode); 2699 intel_mode_from_crtc_timings(mode, mode); 2700 mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) * 2701 (intel_bigjoiner_num_pipes(crtc_state) ?: 1); 2702 mode->vdisplay = drm_rect_height(&crtc_state->pipe_src); 2703 2704 /* Derive per-pipe timings in case bigjoiner is used */ 2705 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2706 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2707 2708 intel_crtc_compute_pixel_rate(crtc_state); 2709 } 2710 2711 static void intel_encoder_get_config(struct intel_encoder *encoder, 2712 struct intel_crtc_state *crtc_state) 2713 { 2714 encoder->get_config(encoder, crtc_state); 2715 2716 intel_crtc_readout_derived_state(crtc_state); 2717 } 2718 2719 static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state *crtc_state) 2720 { 2721 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2722 int width, height; 2723 2724 if (num_pipes < 2) 2725 return; 2726 2727 width = drm_rect_width(&crtc_state->pipe_src); 2728 height = drm_rect_height(&crtc_state->pipe_src); 2729 2730 drm_rect_init(&crtc_state->pipe_src, 0, 0, 2731 width / num_pipes, height); 2732 } 2733 2734 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state) 2735 { 2736 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2737 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2738 2739 intel_bigjoiner_compute_pipe_src(crtc_state); 2740 2741 /* 2742 * Pipe horizontal size must be even in: 2743 * - DVO ganged mode 2744 * - LVDS dual channel mode 2745 * - Double wide pipe 2746 */ 2747 if (drm_rect_width(&crtc_state->pipe_src) & 1) { 2748 if (crtc_state->double_wide) { 2749 drm_dbg_kms(&i915->drm, 2750 "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n", 2751 crtc->base.base.id, crtc->base.name); 2752 return -EINVAL; 2753 } 2754 2755 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 2756 intel_is_dual_link_lvds(i915)) { 2757 drm_dbg_kms(&i915->drm, 2758 "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n", 2759 crtc->base.base.id, crtc->base.name); 2760 return -EINVAL; 2761 } 2762 } 2763 2764 return 0; 2765 } 2766 2767 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state) 2768 { 2769 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2770 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2771 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2772 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2773 int clock_limit = i915->max_dotclk_freq; 2774 2775 /* 2776 * Start with the adjusted_mode crtc timings, which 2777 * have been filled with the transcoder timings. 2778 */ 2779 drm_mode_copy(pipe_mode, adjusted_mode); 2780 2781 /* Expand MSO per-segment transcoder timings to full */ 2782 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2783 2784 /* Derive per-pipe timings in case bigjoiner is used */ 2785 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2786 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2787 2788 if (DISPLAY_VER(i915) < 4) { 2789 clock_limit = i915->max_cdclk_freq * 9 / 10; 2790 2791 /* 2792 * Enable double wide mode when the dot clock 2793 * is > 90% of the (display) core speed. 2794 */ 2795 if (intel_crtc_supports_double_wide(crtc) && 2796 pipe_mode->crtc_clock > clock_limit) { 2797 clock_limit = i915->max_dotclk_freq; 2798 crtc_state->double_wide = true; 2799 } 2800 } 2801 2802 if (pipe_mode->crtc_clock > clock_limit) { 2803 drm_dbg_kms(&i915->drm, 2804 "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", 2805 crtc->base.base.id, crtc->base.name, 2806 pipe_mode->crtc_clock, clock_limit, 2807 str_yes_no(crtc_state->double_wide)); 2808 return -EINVAL; 2809 } 2810 2811 return 0; 2812 } 2813 2814 static int intel_crtc_compute_config(struct intel_crtc *crtc, 2815 struct intel_crtc_state *crtc_state) 2816 { 2817 int ret; 2818 2819 ret = intel_crtc_compute_pipe_src(crtc_state); 2820 if (ret) 2821 return ret; 2822 2823 ret = intel_crtc_compute_pipe_mode(crtc_state); 2824 if (ret) 2825 return ret; 2826 2827 intel_crtc_compute_pixel_rate(crtc_state); 2828 2829 if (crtc_state->has_pch_encoder) 2830 return ilk_fdi_compute_config(crtc, crtc_state); 2831 2832 return 0; 2833 } 2834 2835 static void 2836 intel_reduce_m_n_ratio(u32 *num, u32 *den) 2837 { 2838 while (*num > DATA_LINK_M_N_MASK || 2839 *den > DATA_LINK_M_N_MASK) { 2840 *num >>= 1; 2841 *den >>= 1; 2842 } 2843 } 2844 2845 static void compute_m_n(unsigned int m, unsigned int n, 2846 u32 *ret_m, u32 *ret_n, 2847 bool constant_n) 2848 { 2849 /* 2850 * Several DP dongles in particular seem to be fussy about 2851 * too large link M/N values. Give N value as 0x8000 that 2852 * should be acceptable by specific devices. 0x8000 is the 2853 * specified fixed N value for asynchronous clock mode, 2854 * which the devices expect also in synchronous clock mode. 2855 */ 2856 if (constant_n) 2857 *ret_n = DP_LINK_CONSTANT_N_VALUE; 2858 else 2859 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); 2860 2861 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n); 2862 intel_reduce_m_n_ratio(ret_m, ret_n); 2863 } 2864 2865 void 2866 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes, 2867 int pixel_clock, int link_clock, 2868 struct intel_link_m_n *m_n, 2869 bool constant_n, bool fec_enable) 2870 { 2871 u32 data_clock = bits_per_pixel * pixel_clock; 2872 2873 if (fec_enable) 2874 data_clock = intel_dp_mode_to_fec_clock(data_clock); 2875 2876 m_n->tu = 64; 2877 compute_m_n(data_clock, 2878 link_clock * nlanes * 8, 2879 &m_n->data_m, &m_n->data_n, 2880 constant_n); 2881 2882 compute_m_n(pixel_clock, link_clock, 2883 &m_n->link_m, &m_n->link_n, 2884 constant_n); 2885 } 2886 2887 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv) 2888 { 2889 /* 2890 * There may be no VBT; and if the BIOS enabled SSC we can 2891 * just keep using it to avoid unnecessary flicker. Whereas if the 2892 * BIOS isn't using it, don't assume it will work even if the VBT 2893 * indicates as much. 2894 */ 2895 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { 2896 bool bios_lvds_use_ssc = intel_de_read(dev_priv, 2897 PCH_DREF_CONTROL) & 2898 DREF_SSC1_ENABLE; 2899 2900 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { 2901 drm_dbg_kms(&dev_priv->drm, 2902 "SSC %s by BIOS, overriding VBT which says %s\n", 2903 str_enabled_disabled(bios_lvds_use_ssc), 2904 str_enabled_disabled(dev_priv->vbt.lvds_use_ssc)); 2905 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; 2906 } 2907 } 2908 } 2909 2910 void intel_zero_m_n(struct intel_link_m_n *m_n) 2911 { 2912 /* corresponds to 0 register value */ 2913 memset(m_n, 0, sizeof(*m_n)); 2914 m_n->tu = 1; 2915 } 2916 2917 void intel_set_m_n(struct drm_i915_private *i915, 2918 const struct intel_link_m_n *m_n, 2919 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 2920 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 2921 { 2922 intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); 2923 intel_de_write(i915, data_n_reg, m_n->data_n); 2924 intel_de_write(i915, link_m_reg, m_n->link_m); 2925 /* 2926 * On BDW+ writing LINK_N arms the double buffered update 2927 * of all the M/N registers, so it must be written last. 2928 */ 2929 intel_de_write(i915, link_n_reg, m_n->link_n); 2930 } 2931 2932 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, 2933 enum transcoder transcoder) 2934 { 2935 if (IS_HASWELL(dev_priv)) 2936 return transcoder == TRANSCODER_EDP; 2937 2938 return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv); 2939 } 2940 2941 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, 2942 enum transcoder transcoder, 2943 const struct intel_link_m_n *m_n) 2944 { 2945 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2946 enum pipe pipe = crtc->pipe; 2947 2948 if (DISPLAY_VER(dev_priv) >= 5) 2949 intel_set_m_n(dev_priv, m_n, 2950 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 2951 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 2952 else 2953 intel_set_m_n(dev_priv, m_n, 2954 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 2955 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 2956 } 2957 2958 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, 2959 enum transcoder transcoder, 2960 const struct intel_link_m_n *m_n) 2961 { 2962 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2963 2964 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 2965 return; 2966 2967 intel_set_m_n(dev_priv, m_n, 2968 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 2969 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 2970 } 2971 2972 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) 2973 { 2974 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2975 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2976 enum pipe pipe = crtc->pipe; 2977 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2978 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2979 u32 crtc_vtotal, crtc_vblank_end; 2980 int vsyncshift = 0; 2981 2982 /* We need to be careful not to changed the adjusted mode, for otherwise 2983 * the hw state checker will get angry at the mismatch. */ 2984 crtc_vtotal = adjusted_mode->crtc_vtotal; 2985 crtc_vblank_end = adjusted_mode->crtc_vblank_end; 2986 2987 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 2988 /* the chip adds 2 halflines automatically */ 2989 crtc_vtotal -= 1; 2990 crtc_vblank_end -= 1; 2991 2992 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 2993 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; 2994 else 2995 vsyncshift = adjusted_mode->crtc_hsync_start - 2996 adjusted_mode->crtc_htotal / 2; 2997 if (vsyncshift < 0) 2998 vsyncshift += adjusted_mode->crtc_htotal; 2999 } 3000 3001 if (DISPLAY_VER(dev_priv) > 3) 3002 intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder), 3003 vsyncshift); 3004 3005 intel_de_write(dev_priv, HTOTAL(cpu_transcoder), 3006 (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16)); 3007 intel_de_write(dev_priv, HBLANK(cpu_transcoder), 3008 (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16)); 3009 intel_de_write(dev_priv, HSYNC(cpu_transcoder), 3010 (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16)); 3011 3012 intel_de_write(dev_priv, VTOTAL(cpu_transcoder), 3013 (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16)); 3014 intel_de_write(dev_priv, VBLANK(cpu_transcoder), 3015 (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16)); 3016 intel_de_write(dev_priv, VSYNC(cpu_transcoder), 3017 (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16)); 3018 3019 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be 3020 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is 3021 * documented on the DDI_FUNC_CTL register description, EDP Input Select 3022 * bits. */ 3023 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && 3024 (pipe == PIPE_B || pipe == PIPE_C)) 3025 intel_de_write(dev_priv, VTOTAL(pipe), 3026 intel_de_read(dev_priv, VTOTAL(cpu_transcoder))); 3027 3028 } 3029 3030 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) 3031 { 3032 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3033 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3034 int width = drm_rect_width(&crtc_state->pipe_src); 3035 int height = drm_rect_height(&crtc_state->pipe_src); 3036 enum pipe pipe = crtc->pipe; 3037 3038 /* pipesrc controls the size that is scaled from, which should 3039 * always be the user's requested size. 3040 */ 3041 intel_de_write(dev_priv, PIPESRC(pipe), 3042 PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1)); 3043 } 3044 3045 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) 3046 { 3047 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3048 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3049 3050 if (DISPLAY_VER(dev_priv) == 2) 3051 return false; 3052 3053 if (DISPLAY_VER(dev_priv) >= 9 || 3054 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 3055 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW; 3056 else 3057 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK; 3058 } 3059 3060 static void intel_get_transcoder_timings(struct intel_crtc *crtc, 3061 struct intel_crtc_state *pipe_config) 3062 { 3063 struct drm_device *dev = crtc->base.dev; 3064 struct drm_i915_private *dev_priv = to_i915(dev); 3065 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3066 u32 tmp; 3067 3068 tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder)); 3069 pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; 3070 pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; 3071 3072 if (!transcoder_is_dsi(cpu_transcoder)) { 3073 tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder)); 3074 pipe_config->hw.adjusted_mode.crtc_hblank_start = 3075 (tmp & 0xffff) + 1; 3076 pipe_config->hw.adjusted_mode.crtc_hblank_end = 3077 ((tmp >> 16) & 0xffff) + 1; 3078 } 3079 tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder)); 3080 pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; 3081 pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; 3082 3083 tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder)); 3084 pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; 3085 pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; 3086 3087 if (!transcoder_is_dsi(cpu_transcoder)) { 3088 tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder)); 3089 pipe_config->hw.adjusted_mode.crtc_vblank_start = 3090 (tmp & 0xffff) + 1; 3091 pipe_config->hw.adjusted_mode.crtc_vblank_end = 3092 ((tmp >> 16) & 0xffff) + 1; 3093 } 3094 tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder)); 3095 pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; 3096 pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; 3097 3098 if (intel_pipe_is_interlaced(pipe_config)) { 3099 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; 3100 pipe_config->hw.adjusted_mode.crtc_vtotal += 1; 3101 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1; 3102 } 3103 } 3104 3105 static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state) 3106 { 3107 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3108 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 3109 enum pipe master_pipe, pipe = crtc->pipe; 3110 int width; 3111 3112 if (num_pipes < 2) 3113 return; 3114 3115 master_pipe = bigjoiner_master_pipe(crtc_state); 3116 width = drm_rect_width(&crtc_state->pipe_src); 3117 3118 drm_rect_translate_to(&crtc_state->pipe_src, 3119 (pipe - master_pipe) * width, 0); 3120 } 3121 3122 static void intel_get_pipe_src_size(struct intel_crtc *crtc, 3123 struct intel_crtc_state *pipe_config) 3124 { 3125 struct drm_device *dev = crtc->base.dev; 3126 struct drm_i915_private *dev_priv = to_i915(dev); 3127 u32 tmp; 3128 3129 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe)); 3130 3131 drm_rect_init(&pipe_config->pipe_src, 0, 0, 3132 REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1, 3133 REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1); 3134 3135 intel_bigjoiner_adjust_pipe_src(pipe_config); 3136 } 3137 3138 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) 3139 { 3140 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3141 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3142 u32 pipeconf = 0; 3143 3144 /* we keep both pipes enabled on 830 */ 3145 if (IS_I830(dev_priv)) 3146 pipeconf |= PIPECONF_ENABLE; 3147 3148 if (crtc_state->double_wide) 3149 pipeconf |= PIPECONF_DOUBLE_WIDE; 3150 3151 /* only g4x and later have fancy bpc/dither controls */ 3152 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 3153 IS_CHERRYVIEW(dev_priv)) { 3154 /* Bspec claims that we can't use dithering for 30bpp pipes. */ 3155 if (crtc_state->dither && crtc_state->pipe_bpp != 30) 3156 pipeconf |= PIPECONF_DITHER_EN | 3157 PIPECONF_DITHER_TYPE_SP; 3158 3159 switch (crtc_state->pipe_bpp) { 3160 case 18: 3161 pipeconf |= PIPECONF_BPC_6; 3162 break; 3163 case 24: 3164 pipeconf |= PIPECONF_BPC_8; 3165 break; 3166 case 30: 3167 pipeconf |= PIPECONF_BPC_10; 3168 break; 3169 default: 3170 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3171 BUG(); 3172 } 3173 } 3174 3175 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 3176 if (DISPLAY_VER(dev_priv) < 4 || 3177 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3178 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; 3179 else 3180 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; 3181 } else { 3182 pipeconf |= PIPECONF_INTERLACE_PROGRESSIVE; 3183 } 3184 3185 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 3186 crtc_state->limited_color_range) 3187 pipeconf |= PIPECONF_COLOR_RANGE_SELECT; 3188 3189 pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); 3190 3191 pipeconf |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3192 3193 intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf); 3194 intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe)); 3195 } 3196 3197 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv) 3198 { 3199 if (IS_I830(dev_priv)) 3200 return false; 3201 3202 return DISPLAY_VER(dev_priv) >= 4 || 3203 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); 3204 } 3205 3206 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state) 3207 { 3208 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3209 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3210 u32 tmp; 3211 3212 if (!i9xx_has_pfit(dev_priv)) 3213 return; 3214 3215 tmp = intel_de_read(dev_priv, PFIT_CONTROL); 3216 if (!(tmp & PFIT_ENABLE)) 3217 return; 3218 3219 /* Check whether the pfit is attached to our pipe. */ 3220 if (DISPLAY_VER(dev_priv) < 4) { 3221 if (crtc->pipe != PIPE_B) 3222 return; 3223 } else { 3224 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) 3225 return; 3226 } 3227 3228 crtc_state->gmch_pfit.control = tmp; 3229 crtc_state->gmch_pfit.pgm_ratios = 3230 intel_de_read(dev_priv, PFIT_PGM_RATIOS); 3231 } 3232 3233 static void vlv_crtc_clock_get(struct intel_crtc *crtc, 3234 struct intel_crtc_state *pipe_config) 3235 { 3236 struct drm_device *dev = crtc->base.dev; 3237 struct drm_i915_private *dev_priv = to_i915(dev); 3238 enum pipe pipe = crtc->pipe; 3239 struct dpll clock; 3240 u32 mdiv; 3241 int refclk = 100000; 3242 3243 /* In case of DSI, DPLL will not be used */ 3244 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 3245 return; 3246 3247 vlv_dpio_get(dev_priv); 3248 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); 3249 vlv_dpio_put(dev_priv); 3250 3251 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; 3252 clock.m2 = mdiv & DPIO_M2DIV_MASK; 3253 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; 3254 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; 3255 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; 3256 3257 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); 3258 } 3259 3260 static void chv_crtc_clock_get(struct intel_crtc *crtc, 3261 struct intel_crtc_state *pipe_config) 3262 { 3263 struct drm_device *dev = crtc->base.dev; 3264 struct drm_i915_private *dev_priv = to_i915(dev); 3265 enum pipe pipe = crtc->pipe; 3266 enum dpio_channel port = vlv_pipe_to_channel(pipe); 3267 struct dpll clock; 3268 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; 3269 int refclk = 100000; 3270 3271 /* In case of DSI, DPLL will not be used */ 3272 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 3273 return; 3274 3275 vlv_dpio_get(dev_priv); 3276 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); 3277 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); 3278 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); 3279 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); 3280 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); 3281 vlv_dpio_put(dev_priv); 3282 3283 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; 3284 clock.m2 = (pll_dw0 & 0xff) << 22; 3285 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) 3286 clock.m2 |= pll_dw2 & 0x3fffff; 3287 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; 3288 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; 3289 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; 3290 3291 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); 3292 } 3293 3294 static enum intel_output_format 3295 bdw_get_pipemisc_output_format(struct intel_crtc *crtc) 3296 { 3297 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3298 u32 tmp; 3299 3300 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); 3301 3302 if (tmp & PIPEMISC_YUV420_ENABLE) { 3303 /* We support 4:2:0 in full blend mode only */ 3304 drm_WARN_ON(&dev_priv->drm, 3305 (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0); 3306 3307 return INTEL_OUTPUT_FORMAT_YCBCR420; 3308 } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) { 3309 return INTEL_OUTPUT_FORMAT_YCBCR444; 3310 } else { 3311 return INTEL_OUTPUT_FORMAT_RGB; 3312 } 3313 } 3314 3315 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state) 3316 { 3317 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3318 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 3319 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3320 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 3321 u32 tmp; 3322 3323 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); 3324 3325 if (tmp & DISP_PIPE_GAMMA_ENABLE) 3326 crtc_state->gamma_enable = true; 3327 3328 if (!HAS_GMCH(dev_priv) && 3329 tmp & DISP_PIPE_CSC_ENABLE) 3330 crtc_state->csc_enable = true; 3331 } 3332 3333 static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 3334 struct intel_crtc_state *pipe_config) 3335 { 3336 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3337 enum intel_display_power_domain power_domain; 3338 intel_wakeref_t wakeref; 3339 u32 tmp; 3340 bool ret; 3341 3342 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3343 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3344 if (!wakeref) 3345 return false; 3346 3347 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3348 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3349 pipe_config->shared_dpll = NULL; 3350 3351 ret = false; 3352 3353 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); 3354 if (!(tmp & PIPECONF_ENABLE)) 3355 goto out; 3356 3357 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 3358 IS_CHERRYVIEW(dev_priv)) { 3359 switch (tmp & PIPECONF_BPC_MASK) { 3360 case PIPECONF_BPC_6: 3361 pipe_config->pipe_bpp = 18; 3362 break; 3363 case PIPECONF_BPC_8: 3364 pipe_config->pipe_bpp = 24; 3365 break; 3366 case PIPECONF_BPC_10: 3367 pipe_config->pipe_bpp = 30; 3368 break; 3369 default: 3370 MISSING_CASE(tmp); 3371 break; 3372 } 3373 } 3374 3375 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 3376 (tmp & PIPECONF_COLOR_RANGE_SELECT)) 3377 pipe_config->limited_color_range = true; 3378 3379 pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_I9XX, tmp); 3380 3381 pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1; 3382 3383 if (IS_CHERRYVIEW(dev_priv)) 3384 pipe_config->cgm_mode = intel_de_read(dev_priv, 3385 CGM_PIPE_MODE(crtc->pipe)); 3386 3387 i9xx_get_pipe_color_config(pipe_config); 3388 intel_color_get_config(pipe_config); 3389 3390 if (DISPLAY_VER(dev_priv) < 4) 3391 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; 3392 3393 intel_get_transcoder_timings(crtc, pipe_config); 3394 intel_get_pipe_src_size(crtc, pipe_config); 3395 3396 i9xx_get_pfit_config(pipe_config); 3397 3398 if (DISPLAY_VER(dev_priv) >= 4) { 3399 /* No way to read it out on pipes B and C */ 3400 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) 3401 tmp = dev_priv->chv_dpll_md[crtc->pipe]; 3402 else 3403 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe)); 3404 pipe_config->pixel_multiplier = 3405 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) 3406 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; 3407 pipe_config->dpll_hw_state.dpll_md = tmp; 3408 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 3409 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 3410 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe)); 3411 pipe_config->pixel_multiplier = 3412 ((tmp & SDVO_MULTIPLIER_MASK) 3413 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; 3414 } else { 3415 /* Note that on i915G/GM the pixel multiplier is in the sdvo 3416 * port and will be fixed up in the encoder->get_config 3417 * function. */ 3418 pipe_config->pixel_multiplier = 1; 3419 } 3420 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv, 3421 DPLL(crtc->pipe)); 3422 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 3423 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv, 3424 FP0(crtc->pipe)); 3425 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv, 3426 FP1(crtc->pipe)); 3427 } else { 3428 /* Mask out read-only status bits. */ 3429 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | 3430 DPLL_PORTC_READY_MASK | 3431 DPLL_PORTB_READY_MASK); 3432 } 3433 3434 if (IS_CHERRYVIEW(dev_priv)) 3435 chv_crtc_clock_get(crtc, pipe_config); 3436 else if (IS_VALLEYVIEW(dev_priv)) 3437 vlv_crtc_clock_get(crtc, pipe_config); 3438 else 3439 i9xx_crtc_clock_get(crtc, pipe_config); 3440 3441 /* 3442 * Normally the dotclock is filled in by the encoder .get_config() 3443 * but in case the pipe is enabled w/o any ports we need a sane 3444 * default. 3445 */ 3446 pipe_config->hw.adjusted_mode.crtc_clock = 3447 pipe_config->port_clock / pipe_config->pixel_multiplier; 3448 3449 ret = true; 3450 3451 out: 3452 intel_display_power_put(dev_priv, power_domain, wakeref); 3453 3454 return ret; 3455 } 3456 3457 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) 3458 { 3459 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3460 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3461 enum pipe pipe = crtc->pipe; 3462 u32 val; 3463 3464 val = 0; 3465 3466 switch (crtc_state->pipe_bpp) { 3467 case 18: 3468 val |= PIPECONF_BPC_6; 3469 break; 3470 case 24: 3471 val |= PIPECONF_BPC_8; 3472 break; 3473 case 30: 3474 val |= PIPECONF_BPC_10; 3475 break; 3476 case 36: 3477 val |= PIPECONF_BPC_12; 3478 break; 3479 default: 3480 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3481 BUG(); 3482 } 3483 3484 if (crtc_state->dither) 3485 val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP; 3486 3487 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3488 val |= PIPECONF_INTERLACE_IF_ID_ILK; 3489 else 3490 val |= PIPECONF_INTERLACE_PF_PD_ILK; 3491 3492 /* 3493 * This would end up with an odd purple hue over 3494 * the entire display. Make sure we don't do it. 3495 */ 3496 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 3497 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 3498 3499 if (crtc_state->limited_color_range && 3500 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3501 val |= PIPECONF_COLOR_RANGE_SELECT; 3502 3503 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3504 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709; 3505 3506 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); 3507 3508 val |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3509 val |= PIPECONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay); 3510 3511 intel_de_write(dev_priv, PIPECONF(pipe), val); 3512 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 3513 } 3514 3515 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) 3516 { 3517 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3518 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3519 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3520 u32 val = 0; 3521 3522 if (IS_HASWELL(dev_priv) && crtc_state->dither) 3523 val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP; 3524 3525 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3526 val |= PIPECONF_INTERLACE_IF_ID_ILK; 3527 else 3528 val |= PIPECONF_INTERLACE_PF_PD_ILK; 3529 3530 if (IS_HASWELL(dev_priv) && 3531 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3532 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW; 3533 3534 intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val); 3535 intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder)); 3536 } 3537 3538 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) 3539 { 3540 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3541 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3542 u32 val = 0; 3543 3544 switch (crtc_state->pipe_bpp) { 3545 case 18: 3546 val |= PIPEMISC_BPC_6; 3547 break; 3548 case 24: 3549 val |= PIPEMISC_BPC_8; 3550 break; 3551 case 30: 3552 val |= PIPEMISC_BPC_10; 3553 break; 3554 case 36: 3555 /* Port output 12BPC defined for ADLP+ */ 3556 if (DISPLAY_VER(dev_priv) > 12) 3557 val |= PIPEMISC_BPC_12_ADLP; 3558 break; 3559 default: 3560 MISSING_CASE(crtc_state->pipe_bpp); 3561 break; 3562 } 3563 3564 if (crtc_state->dither) 3565 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; 3566 3567 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 3568 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 3569 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV; 3570 3571 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 3572 val |= PIPEMISC_YUV420_ENABLE | 3573 PIPEMISC_YUV420_MODE_FULL_BLEND; 3574 3575 if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state)) 3576 val |= PIPEMISC_HDR_MODE_PRECISION; 3577 3578 if (DISPLAY_VER(dev_priv) >= 12) 3579 val |= PIPEMISC_PIXEL_ROUNDING_TRUNC; 3580 3581 intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val); 3582 } 3583 3584 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) 3585 { 3586 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3587 u32 tmp; 3588 3589 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); 3590 3591 switch (tmp & PIPEMISC_BPC_MASK) { 3592 case PIPEMISC_BPC_6: 3593 return 18; 3594 case PIPEMISC_BPC_8: 3595 return 24; 3596 case PIPEMISC_BPC_10: 3597 return 30; 3598 /* 3599 * PORT OUTPUT 12 BPC defined for ADLP+. 3600 * 3601 * TODO: 3602 * For previous platforms with DSI interface, bits 5:7 3603 * are used for storing pipe_bpp irrespective of dithering. 3604 * Since the value of 12 BPC is not defined for these bits 3605 * on older platforms, need to find a workaround for 12 BPC 3606 * MIPI DSI HW readout. 3607 */ 3608 case PIPEMISC_BPC_12_ADLP: 3609 if (DISPLAY_VER(dev_priv) > 12) 3610 return 36; 3611 fallthrough; 3612 default: 3613 MISSING_CASE(tmp); 3614 return 0; 3615 } 3616 } 3617 3618 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) 3619 { 3620 /* 3621 * Account for spread spectrum to avoid 3622 * oversubscribing the link. Max center spread 3623 * is 2.5%; use 5% for safety's sake. 3624 */ 3625 u32 bps = target_clock * bpp * 21 / 20; 3626 return DIV_ROUND_UP(bps, link_bw * 8); 3627 } 3628 3629 void intel_get_m_n(struct drm_i915_private *i915, 3630 struct intel_link_m_n *m_n, 3631 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 3632 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 3633 { 3634 m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK; 3635 m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK; 3636 m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK; 3637 m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK; 3638 m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1; 3639 } 3640 3641 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, 3642 enum transcoder transcoder, 3643 struct intel_link_m_n *m_n) 3644 { 3645 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3646 enum pipe pipe = crtc->pipe; 3647 3648 if (DISPLAY_VER(dev_priv) >= 5) 3649 intel_get_m_n(dev_priv, m_n, 3650 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 3651 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 3652 else 3653 intel_get_m_n(dev_priv, m_n, 3654 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 3655 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 3656 } 3657 3658 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, 3659 enum transcoder transcoder, 3660 struct intel_link_m_n *m_n) 3661 { 3662 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3663 3664 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 3665 return; 3666 3667 intel_get_m_n(dev_priv, m_n, 3668 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 3669 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 3670 } 3671 3672 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state, 3673 u32 pos, u32 size) 3674 { 3675 drm_rect_init(&crtc_state->pch_pfit.dst, 3676 pos >> 16, pos & 0xffff, 3677 size >> 16, size & 0xffff); 3678 } 3679 3680 static void skl_get_pfit_config(struct intel_crtc_state *crtc_state) 3681 { 3682 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3683 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3684 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; 3685 int id = -1; 3686 int i; 3687 3688 /* find scaler attached to this pipe */ 3689 for (i = 0; i < crtc->num_scalers; i++) { 3690 u32 ctl, pos, size; 3691 3692 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i)); 3693 if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN) 3694 continue; 3695 3696 id = i; 3697 crtc_state->pch_pfit.enabled = true; 3698 3699 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i)); 3700 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i)); 3701 3702 ilk_get_pfit_pos_size(crtc_state, pos, size); 3703 3704 scaler_state->scalers[i].in_use = true; 3705 break; 3706 } 3707 3708 scaler_state->scaler_id = id; 3709 if (id >= 0) 3710 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); 3711 else 3712 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); 3713 } 3714 3715 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state) 3716 { 3717 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3718 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3719 u32 ctl, pos, size; 3720 3721 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe)); 3722 if ((ctl & PF_ENABLE) == 0) 3723 return; 3724 3725 crtc_state->pch_pfit.enabled = true; 3726 3727 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe)); 3728 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe)); 3729 3730 ilk_get_pfit_pos_size(crtc_state, pos, size); 3731 3732 /* 3733 * We currently do not free assignements of panel fitters on 3734 * ivb/hsw (since we don't use the higher upscaling modes which 3735 * differentiates them) so just WARN about this case for now. 3736 */ 3737 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 7 && 3738 (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe)); 3739 } 3740 3741 static bool ilk_get_pipe_config(struct intel_crtc *crtc, 3742 struct intel_crtc_state *pipe_config) 3743 { 3744 struct drm_device *dev = crtc->base.dev; 3745 struct drm_i915_private *dev_priv = to_i915(dev); 3746 enum intel_display_power_domain power_domain; 3747 intel_wakeref_t wakeref; 3748 u32 tmp; 3749 bool ret; 3750 3751 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3752 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3753 if (!wakeref) 3754 return false; 3755 3756 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3757 pipe_config->shared_dpll = NULL; 3758 3759 ret = false; 3760 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); 3761 if (!(tmp & PIPECONF_ENABLE)) 3762 goto out; 3763 3764 switch (tmp & PIPECONF_BPC_MASK) { 3765 case PIPECONF_BPC_6: 3766 pipe_config->pipe_bpp = 18; 3767 break; 3768 case PIPECONF_BPC_8: 3769 pipe_config->pipe_bpp = 24; 3770 break; 3771 case PIPECONF_BPC_10: 3772 pipe_config->pipe_bpp = 30; 3773 break; 3774 case PIPECONF_BPC_12: 3775 pipe_config->pipe_bpp = 36; 3776 break; 3777 default: 3778 break; 3779 } 3780 3781 if (tmp & PIPECONF_COLOR_RANGE_SELECT) 3782 pipe_config->limited_color_range = true; 3783 3784 switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) { 3785 case PIPECONF_OUTPUT_COLORSPACE_YUV601: 3786 case PIPECONF_OUTPUT_COLORSPACE_YUV709: 3787 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3788 break; 3789 default: 3790 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3791 break; 3792 } 3793 3794 pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_ILK, tmp); 3795 3796 pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1; 3797 3798 pipe_config->msa_timing_delay = REG_FIELD_GET(PIPECONF_MSA_TIMING_DELAY_MASK, tmp); 3799 3800 pipe_config->csc_mode = intel_de_read(dev_priv, 3801 PIPE_CSC_MODE(crtc->pipe)); 3802 3803 i9xx_get_pipe_color_config(pipe_config); 3804 intel_color_get_config(pipe_config); 3805 3806 pipe_config->pixel_multiplier = 1; 3807 3808 ilk_pch_get_config(pipe_config); 3809 3810 intel_get_transcoder_timings(crtc, pipe_config); 3811 intel_get_pipe_src_size(crtc, pipe_config); 3812 3813 ilk_get_pfit_config(pipe_config); 3814 3815 ret = true; 3816 3817 out: 3818 intel_display_power_put(dev_priv, power_domain, wakeref); 3819 3820 return ret; 3821 } 3822 3823 static u8 bigjoiner_pipes(struct drm_i915_private *i915) 3824 { 3825 if (DISPLAY_VER(i915) >= 12) 3826 return BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D); 3827 else if (DISPLAY_VER(i915) >= 11) 3828 return BIT(PIPE_B) | BIT(PIPE_C); 3829 else 3830 return 0; 3831 } 3832 3833 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv, 3834 enum transcoder cpu_transcoder) 3835 { 3836 enum intel_display_power_domain power_domain; 3837 intel_wakeref_t wakeref; 3838 u32 tmp = 0; 3839 3840 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3841 3842 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3843 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3844 3845 return tmp & TRANS_DDI_FUNC_ENABLE; 3846 } 3847 3848 static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv, 3849 u8 *master_pipes, u8 *slave_pipes) 3850 { 3851 struct intel_crtc *crtc; 3852 3853 *master_pipes = 0; 3854 *slave_pipes = 0; 3855 3856 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, 3857 bigjoiner_pipes(dev_priv)) { 3858 enum intel_display_power_domain power_domain; 3859 enum pipe pipe = crtc->pipe; 3860 intel_wakeref_t wakeref; 3861 3862 power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe); 3863 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3864 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3865 3866 if (!(tmp & BIG_JOINER_ENABLE)) 3867 continue; 3868 3869 if (tmp & MASTER_BIG_JOINER_ENABLE) 3870 *master_pipes |= BIT(pipe); 3871 else 3872 *slave_pipes |= BIT(pipe); 3873 } 3874 3875 if (DISPLAY_VER(dev_priv) < 13) 3876 continue; 3877 3878 power_domain = POWER_DOMAIN_PIPE(pipe); 3879 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3880 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3881 3882 if (tmp & UNCOMPRESSED_JOINER_MASTER) 3883 *master_pipes |= BIT(pipe); 3884 if (tmp & UNCOMPRESSED_JOINER_SLAVE) 3885 *slave_pipes |= BIT(pipe); 3886 } 3887 } 3888 3889 /* Bigjoiner pipes should always be consecutive master and slave */ 3890 drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1, 3891 "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n", 3892 *master_pipes, *slave_pipes); 3893 } 3894 3895 static enum pipe get_bigjoiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3896 { 3897 if ((slave_pipes & BIT(pipe)) == 0) 3898 return pipe; 3899 3900 /* ignore everything above our pipe */ 3901 master_pipes &= ~GENMASK(7, pipe); 3902 3903 /* highest remaining bit should be our master pipe */ 3904 return fls(master_pipes) - 1; 3905 } 3906 3907 static u8 get_bigjoiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3908 { 3909 enum pipe master_pipe, next_master_pipe; 3910 3911 master_pipe = get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes); 3912 3913 if ((master_pipes & BIT(master_pipe)) == 0) 3914 return 0; 3915 3916 /* ignore our master pipe and everything below it */ 3917 master_pipes &= ~GENMASK(master_pipe, 0); 3918 /* make sure a high bit is set for the ffs() */ 3919 master_pipes |= BIT(7); 3920 /* lowest remaining bit should be the next master pipe */ 3921 next_master_pipe = ffs(master_pipes) - 1; 3922 3923 return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe); 3924 } 3925 3926 static u8 hsw_panel_transcoders(struct drm_i915_private *i915) 3927 { 3928 u8 panel_transcoder_mask = BIT(TRANSCODER_EDP); 3929 3930 if (DISPLAY_VER(i915) >= 11) 3931 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); 3932 3933 return panel_transcoder_mask; 3934 } 3935 3936 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) 3937 { 3938 struct drm_device *dev = crtc->base.dev; 3939 struct drm_i915_private *dev_priv = to_i915(dev); 3940 u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv); 3941 enum transcoder cpu_transcoder; 3942 u8 master_pipes, slave_pipes; 3943 u8 enabled_transcoders = 0; 3944 3945 /* 3946 * XXX: Do intel_display_power_get_if_enabled before reading this (for 3947 * consistency and less surprising code; it's in always on power). 3948 */ 3949 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, 3950 panel_transcoder_mask) { 3951 enum intel_display_power_domain power_domain; 3952 intel_wakeref_t wakeref; 3953 enum pipe trans_pipe; 3954 u32 tmp = 0; 3955 3956 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3957 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3958 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3959 3960 if (!(tmp & TRANS_DDI_FUNC_ENABLE)) 3961 continue; 3962 3963 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 3964 default: 3965 drm_WARN(dev, 1, 3966 "unknown pipe linked to transcoder %s\n", 3967 transcoder_name(cpu_transcoder)); 3968 fallthrough; 3969 case TRANS_DDI_EDP_INPUT_A_ONOFF: 3970 case TRANS_DDI_EDP_INPUT_A_ON: 3971 trans_pipe = PIPE_A; 3972 break; 3973 case TRANS_DDI_EDP_INPUT_B_ONOFF: 3974 trans_pipe = PIPE_B; 3975 break; 3976 case TRANS_DDI_EDP_INPUT_C_ONOFF: 3977 trans_pipe = PIPE_C; 3978 break; 3979 case TRANS_DDI_EDP_INPUT_D_ONOFF: 3980 trans_pipe = PIPE_D; 3981 break; 3982 } 3983 3984 if (trans_pipe == crtc->pipe) 3985 enabled_transcoders |= BIT(cpu_transcoder); 3986 } 3987 3988 /* single pipe or bigjoiner master */ 3989 cpu_transcoder = (enum transcoder) crtc->pipe; 3990 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 3991 enabled_transcoders |= BIT(cpu_transcoder); 3992 3993 /* bigjoiner slave -> consider the master pipe's transcoder as well */ 3994 enabled_bigjoiner_pipes(dev_priv, &master_pipes, &slave_pipes); 3995 if (slave_pipes & BIT(crtc->pipe)) { 3996 cpu_transcoder = (enum transcoder) 3997 get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes); 3998 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 3999 enabled_transcoders |= BIT(cpu_transcoder); 4000 } 4001 4002 return enabled_transcoders; 4003 } 4004 4005 static bool has_edp_transcoders(u8 enabled_transcoders) 4006 { 4007 return enabled_transcoders & BIT(TRANSCODER_EDP); 4008 } 4009 4010 static bool has_dsi_transcoders(u8 enabled_transcoders) 4011 { 4012 return enabled_transcoders & (BIT(TRANSCODER_DSI_0) | 4013 BIT(TRANSCODER_DSI_1)); 4014 } 4015 4016 static bool has_pipe_transcoders(u8 enabled_transcoders) 4017 { 4018 return enabled_transcoders & ~(BIT(TRANSCODER_EDP) | 4019 BIT(TRANSCODER_DSI_0) | 4020 BIT(TRANSCODER_DSI_1)); 4021 } 4022 4023 static void assert_enabled_transcoders(struct drm_i915_private *i915, 4024 u8 enabled_transcoders) 4025 { 4026 /* Only one type of transcoder please */ 4027 drm_WARN_ON(&i915->drm, 4028 has_edp_transcoders(enabled_transcoders) + 4029 has_dsi_transcoders(enabled_transcoders) + 4030 has_pipe_transcoders(enabled_transcoders) > 1); 4031 4032 /* Only DSI transcoders can be ganged */ 4033 drm_WARN_ON(&i915->drm, 4034 !has_dsi_transcoders(enabled_transcoders) && 4035 !is_power_of_2(enabled_transcoders)); 4036 } 4037 4038 static bool hsw_get_transcoder_state(struct intel_crtc *crtc, 4039 struct intel_crtc_state *pipe_config, 4040 struct intel_display_power_domain_set *power_domain_set) 4041 { 4042 struct drm_device *dev = crtc->base.dev; 4043 struct drm_i915_private *dev_priv = to_i915(dev); 4044 unsigned long enabled_transcoders; 4045 u32 tmp; 4046 4047 enabled_transcoders = hsw_enabled_transcoders(crtc); 4048 if (!enabled_transcoders) 4049 return false; 4050 4051 assert_enabled_transcoders(dev_priv, enabled_transcoders); 4052 4053 /* 4054 * With the exception of DSI we should only ever have 4055 * a single enabled transcoder. With DSI let's just 4056 * pick the first one. 4057 */ 4058 pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1; 4059 4060 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 4061 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) 4062 return false; 4063 4064 if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) { 4065 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); 4066 4067 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF) 4068 pipe_config->pch_pfit.force_thru = true; 4069 } 4070 4071 tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder)); 4072 4073 return tmp & PIPECONF_ENABLE; 4074 } 4075 4076 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, 4077 struct intel_crtc_state *pipe_config, 4078 struct intel_display_power_domain_set *power_domain_set) 4079 { 4080 struct drm_device *dev = crtc->base.dev; 4081 struct drm_i915_private *dev_priv = to_i915(dev); 4082 enum transcoder cpu_transcoder; 4083 enum port port; 4084 u32 tmp; 4085 4086 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { 4087 if (port == PORT_A) 4088 cpu_transcoder = TRANSCODER_DSI_A; 4089 else 4090 cpu_transcoder = TRANSCODER_DSI_C; 4091 4092 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 4093 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) 4094 continue; 4095 4096 /* 4097 * The PLL needs to be enabled with a valid divider 4098 * configuration, otherwise accessing DSI registers will hang 4099 * the machine. See BSpec North Display Engine 4100 * registers/MIPI[BXT]. We can break out here early, since we 4101 * need the same DSI PLL to be enabled for both DSI ports. 4102 */ 4103 if (!bxt_dsi_pll_is_enabled(dev_priv)) 4104 break; 4105 4106 /* XXX: this works for video mode only */ 4107 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); 4108 if (!(tmp & DPI_ENABLE)) 4109 continue; 4110 4111 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 4112 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) 4113 continue; 4114 4115 pipe_config->cpu_transcoder = cpu_transcoder; 4116 break; 4117 } 4118 4119 return transcoder_is_dsi(pipe_config->cpu_transcoder); 4120 } 4121 4122 static void intel_bigjoiner_get_config(struct intel_crtc_state *crtc_state) 4123 { 4124 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4125 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4126 u8 master_pipes, slave_pipes; 4127 enum pipe pipe = crtc->pipe; 4128 4129 enabled_bigjoiner_pipes(i915, &master_pipes, &slave_pipes); 4130 4131 if (((master_pipes | slave_pipes) & BIT(pipe)) == 0) 4132 return; 4133 4134 crtc_state->bigjoiner_pipes = 4135 BIT(get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes)) | 4136 get_bigjoiner_slave_pipes(pipe, master_pipes, slave_pipes); 4137 } 4138 4139 static bool hsw_get_pipe_config(struct intel_crtc *crtc, 4140 struct intel_crtc_state *pipe_config) 4141 { 4142 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4143 struct intel_display_power_domain_set power_domain_set = { }; 4144 bool active; 4145 u32 tmp; 4146 4147 if (!intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set, 4148 POWER_DOMAIN_PIPE(crtc->pipe))) 4149 return false; 4150 4151 pipe_config->shared_dpll = NULL; 4152 4153 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_set); 4154 4155 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 4156 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_set)) { 4157 drm_WARN_ON(&dev_priv->drm, active); 4158 active = true; 4159 } 4160 4161 if (!active) 4162 goto out; 4163 4164 intel_dsc_get_config(pipe_config); 4165 intel_bigjoiner_get_config(pipe_config); 4166 4167 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || 4168 DISPLAY_VER(dev_priv) >= 11) 4169 intel_get_transcoder_timings(crtc, pipe_config); 4170 4171 if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder)) 4172 intel_vrr_get_config(crtc, pipe_config); 4173 4174 intel_get_pipe_src_size(crtc, pipe_config); 4175 4176 if (IS_HASWELL(dev_priv)) { 4177 u32 tmp = intel_de_read(dev_priv, 4178 PIPECONF(pipe_config->cpu_transcoder)); 4179 4180 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW) 4181 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 4182 else 4183 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 4184 } else { 4185 pipe_config->output_format = 4186 bdw_get_pipemisc_output_format(crtc); 4187 } 4188 4189 pipe_config->gamma_mode = intel_de_read(dev_priv, 4190 GAMMA_MODE(crtc->pipe)); 4191 4192 pipe_config->csc_mode = intel_de_read(dev_priv, 4193 PIPE_CSC_MODE(crtc->pipe)); 4194 4195 if (DISPLAY_VER(dev_priv) >= 9) { 4196 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe)); 4197 4198 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE) 4199 pipe_config->gamma_enable = true; 4200 4201 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE) 4202 pipe_config->csc_enable = true; 4203 } else { 4204 i9xx_get_pipe_color_config(pipe_config); 4205 } 4206 4207 intel_color_get_config(pipe_config); 4208 4209 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe)); 4210 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); 4211 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 4212 pipe_config->ips_linetime = 4213 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); 4214 4215 if (intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set, 4216 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) { 4217 if (DISPLAY_VER(dev_priv) >= 9) 4218 skl_get_pfit_config(pipe_config); 4219 else 4220 ilk_get_pfit_config(pipe_config); 4221 } 4222 4223 hsw_ips_get_config(pipe_config); 4224 4225 if (pipe_config->cpu_transcoder != TRANSCODER_EDP && 4226 !transcoder_is_dsi(pipe_config->cpu_transcoder)) { 4227 pipe_config->pixel_multiplier = 4228 intel_de_read(dev_priv, 4229 PIPE_MULT(pipe_config->cpu_transcoder)) + 1; 4230 } else { 4231 pipe_config->pixel_multiplier = 1; 4232 } 4233 4234 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { 4235 tmp = intel_de_read(dev_priv, CHICKEN_TRANS(pipe_config->cpu_transcoder)); 4236 4237 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1; 4238 } else { 4239 /* no idea if this is correct */ 4240 pipe_config->framestart_delay = 1; 4241 } 4242 4243 out: 4244 intel_display_power_put_all_in_set(dev_priv, &power_domain_set); 4245 4246 return active; 4247 } 4248 4249 static bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state) 4250 { 4251 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4252 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4253 4254 if (!i915->display->get_pipe_config(crtc, crtc_state)) 4255 return false; 4256 4257 crtc_state->hw.active = true; 4258 4259 intel_crtc_readout_derived_state(crtc_state); 4260 4261 return true; 4262 } 4263 4264 /* VESA 640x480x72Hz mode to set on the pipe */ 4265 static const struct drm_display_mode load_detect_mode = { 4266 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, 4267 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 4268 }; 4269 4270 static int intel_modeset_disable_planes(struct drm_atomic_state *state, 4271 struct drm_crtc *crtc) 4272 { 4273 struct drm_plane *plane; 4274 struct drm_plane_state *plane_state; 4275 int ret, i; 4276 4277 ret = drm_atomic_add_affected_planes(state, crtc); 4278 if (ret) 4279 return ret; 4280 4281 for_each_new_plane_in_state(state, plane, plane_state, i) { 4282 if (plane_state->crtc != crtc) 4283 continue; 4284 4285 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL); 4286 if (ret) 4287 return ret; 4288 4289 drm_atomic_set_fb_for_plane(plane_state, NULL); 4290 } 4291 4292 return 0; 4293 } 4294 4295 int intel_get_load_detect_pipe(struct drm_connector *connector, 4296 struct intel_load_detect_pipe *old, 4297 struct drm_modeset_acquire_ctx *ctx) 4298 { 4299 struct intel_encoder *encoder = 4300 intel_attached_encoder(to_intel_connector(connector)); 4301 struct intel_crtc *possible_crtc; 4302 struct intel_crtc *crtc = NULL; 4303 struct drm_device *dev = encoder->base.dev; 4304 struct drm_i915_private *dev_priv = to_i915(dev); 4305 struct drm_mode_config *config = &dev->mode_config; 4306 struct drm_atomic_state *state = NULL, *restore_state = NULL; 4307 struct drm_connector_state *connector_state; 4308 struct intel_crtc_state *crtc_state; 4309 int ret; 4310 4311 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 4312 connector->base.id, connector->name, 4313 encoder->base.base.id, encoder->base.name); 4314 4315 old->restore_state = NULL; 4316 4317 drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex)); 4318 4319 /* 4320 * Algorithm gets a little messy: 4321 * 4322 * - if the connector already has an assigned crtc, use it (but make 4323 * sure it's on first) 4324 * 4325 * - try to find the first unused crtc that can drive this connector, 4326 * and use that if we find one 4327 */ 4328 4329 /* See if we already have a CRTC for this connector */ 4330 if (connector->state->crtc) { 4331 crtc = to_intel_crtc(connector->state->crtc); 4332 4333 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4334 if (ret) 4335 goto fail; 4336 4337 /* Make sure the crtc and connector are running */ 4338 goto found; 4339 } 4340 4341 /* Find an unused one (if possible) */ 4342 for_each_intel_crtc(dev, possible_crtc) { 4343 if (!(encoder->base.possible_crtcs & 4344 drm_crtc_mask(&possible_crtc->base))) 4345 continue; 4346 4347 ret = drm_modeset_lock(&possible_crtc->base.mutex, ctx); 4348 if (ret) 4349 goto fail; 4350 4351 if (possible_crtc->base.state->enable) { 4352 drm_modeset_unlock(&possible_crtc->base.mutex); 4353 continue; 4354 } 4355 4356 crtc = possible_crtc; 4357 break; 4358 } 4359 4360 /* 4361 * If we didn't find an unused CRTC, don't use any. 4362 */ 4363 if (!crtc) { 4364 drm_dbg_kms(&dev_priv->drm, 4365 "no pipe available for load-detect\n"); 4366 ret = -ENODEV; 4367 goto fail; 4368 } 4369 4370 found: 4371 state = drm_atomic_state_alloc(dev); 4372 restore_state = drm_atomic_state_alloc(dev); 4373 if (!state || !restore_state) { 4374 ret = -ENOMEM; 4375 goto fail; 4376 } 4377 4378 state->acquire_ctx = ctx; 4379 restore_state->acquire_ctx = ctx; 4380 4381 connector_state = drm_atomic_get_connector_state(state, connector); 4382 if (IS_ERR(connector_state)) { 4383 ret = PTR_ERR(connector_state); 4384 goto fail; 4385 } 4386 4387 ret = drm_atomic_set_crtc_for_connector(connector_state, &crtc->base); 4388 if (ret) 4389 goto fail; 4390 4391 crtc_state = intel_atomic_get_crtc_state(state, crtc); 4392 if (IS_ERR(crtc_state)) { 4393 ret = PTR_ERR(crtc_state); 4394 goto fail; 4395 } 4396 4397 crtc_state->uapi.active = true; 4398 4399 ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi, 4400 &load_detect_mode); 4401 if (ret) 4402 goto fail; 4403 4404 ret = intel_modeset_disable_planes(state, &crtc->base); 4405 if (ret) 4406 goto fail; 4407 4408 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); 4409 if (!ret) 4410 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, &crtc->base)); 4411 if (!ret) 4412 ret = drm_atomic_add_affected_planes(restore_state, &crtc->base); 4413 if (ret) { 4414 drm_dbg_kms(&dev_priv->drm, 4415 "Failed to create a copy of old state to restore: %i\n", 4416 ret); 4417 goto fail; 4418 } 4419 4420 ret = drm_atomic_commit(state); 4421 if (ret) { 4422 drm_dbg_kms(&dev_priv->drm, 4423 "failed to set mode on load-detect pipe\n"); 4424 goto fail; 4425 } 4426 4427 old->restore_state = restore_state; 4428 drm_atomic_state_put(state); 4429 4430 /* let the connector get through one full cycle before testing */ 4431 intel_crtc_wait_for_next_vblank(crtc); 4432 4433 return true; 4434 4435 fail: 4436 if (state) { 4437 drm_atomic_state_put(state); 4438 state = NULL; 4439 } 4440 if (restore_state) { 4441 drm_atomic_state_put(restore_state); 4442 restore_state = NULL; 4443 } 4444 4445 if (ret == -EDEADLK) 4446 return ret; 4447 4448 return false; 4449 } 4450 4451 void intel_release_load_detect_pipe(struct drm_connector *connector, 4452 struct intel_load_detect_pipe *old, 4453 struct drm_modeset_acquire_ctx *ctx) 4454 { 4455 struct intel_encoder *intel_encoder = 4456 intel_attached_encoder(to_intel_connector(connector)); 4457 struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev); 4458 struct drm_encoder *encoder = &intel_encoder->base; 4459 struct drm_atomic_state *state = old->restore_state; 4460 int ret; 4461 4462 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 4463 connector->base.id, connector->name, 4464 encoder->base.id, encoder->name); 4465 4466 if (!state) 4467 return; 4468 4469 ret = drm_atomic_helper_commit_duplicated_state(state, ctx); 4470 if (ret) 4471 drm_dbg_kms(&i915->drm, 4472 "Couldn't release load detect pipe: %i\n", ret); 4473 drm_atomic_state_put(state); 4474 } 4475 4476 static int i9xx_pll_refclk(struct drm_device *dev, 4477 const struct intel_crtc_state *pipe_config) 4478 { 4479 struct drm_i915_private *dev_priv = to_i915(dev); 4480 u32 dpll = pipe_config->dpll_hw_state.dpll; 4481 4482 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) 4483 return dev_priv->vbt.lvds_ssc_freq; 4484 else if (HAS_PCH_SPLIT(dev_priv)) 4485 return 120000; 4486 else if (DISPLAY_VER(dev_priv) != 2) 4487 return 96000; 4488 else 4489 return 48000; 4490 } 4491 4492 /* Returns the clock of the currently programmed mode of the given pipe. */ 4493 void i9xx_crtc_clock_get(struct intel_crtc *crtc, 4494 struct intel_crtc_state *pipe_config) 4495 { 4496 struct drm_device *dev = crtc->base.dev; 4497 struct drm_i915_private *dev_priv = to_i915(dev); 4498 u32 dpll = pipe_config->dpll_hw_state.dpll; 4499 u32 fp; 4500 struct dpll clock; 4501 int port_clock; 4502 int refclk = i9xx_pll_refclk(dev, pipe_config); 4503 4504 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 4505 fp = pipe_config->dpll_hw_state.fp0; 4506 else 4507 fp = pipe_config->dpll_hw_state.fp1; 4508 4509 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 4510 if (IS_PINEVIEW(dev_priv)) { 4511 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; 4512 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; 4513 } else { 4514 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 4515 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 4516 } 4517 4518 if (DISPLAY_VER(dev_priv) != 2) { 4519 if (IS_PINEVIEW(dev_priv)) 4520 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> 4521 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); 4522 else 4523 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> 4524 DPLL_FPA01_P1_POST_DIV_SHIFT); 4525 4526 switch (dpll & DPLL_MODE_MASK) { 4527 case DPLLB_MODE_DAC_SERIAL: 4528 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 4529 5 : 10; 4530 break; 4531 case DPLLB_MODE_LVDS: 4532 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 4533 7 : 14; 4534 break; 4535 default: 4536 drm_dbg_kms(&dev_priv->drm, 4537 "Unknown DPLL mode %08x in programmed " 4538 "mode\n", (int)(dpll & DPLL_MODE_MASK)); 4539 return; 4540 } 4541 4542 if (IS_PINEVIEW(dev_priv)) 4543 port_clock = pnv_calc_dpll_params(refclk, &clock); 4544 else 4545 port_clock = i9xx_calc_dpll_params(refclk, &clock); 4546 } else { 4547 enum pipe lvds_pipe; 4548 4549 if (IS_I85X(dev_priv) && 4550 intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) && 4551 lvds_pipe == crtc->pipe) { 4552 u32 lvds = intel_de_read(dev_priv, LVDS); 4553 4554 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 4555 DPLL_FPA01_P1_POST_DIV_SHIFT); 4556 4557 if (lvds & LVDS_CLKB_POWER_UP) 4558 clock.p2 = 7; 4559 else 4560 clock.p2 = 14; 4561 } else { 4562 if (dpll & PLL_P1_DIVIDE_BY_TWO) 4563 clock.p1 = 2; 4564 else { 4565 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 4566 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 4567 } 4568 if (dpll & PLL_P2_DIVIDE_BY_4) 4569 clock.p2 = 4; 4570 else 4571 clock.p2 = 2; 4572 } 4573 4574 port_clock = i9xx_calc_dpll_params(refclk, &clock); 4575 } 4576 4577 /* 4578 * This value includes pixel_multiplier. We will use 4579 * port_clock to compute adjusted_mode.crtc_clock in the 4580 * encoder's get_config() function. 4581 */ 4582 pipe_config->port_clock = port_clock; 4583 } 4584 4585 int intel_dotclock_calculate(int link_freq, 4586 const struct intel_link_m_n *m_n) 4587 { 4588 /* 4589 * The calculation for the data clock is: 4590 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp 4591 * But we want to avoid losing precison if possible, so: 4592 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) 4593 * 4594 * and the link clock is simpler: 4595 * link_clock = (m * link_clock) / n 4596 */ 4597 4598 if (!m_n->link_n) 4599 return 0; 4600 4601 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n); 4602 } 4603 4604 /* Returns the currently programmed mode of the given encoder. */ 4605 struct drm_display_mode * 4606 intel_encoder_current_mode(struct intel_encoder *encoder) 4607 { 4608 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4609 struct intel_crtc_state *crtc_state; 4610 struct drm_display_mode *mode; 4611 struct intel_crtc *crtc; 4612 enum pipe pipe; 4613 4614 if (!encoder->get_hw_state(encoder, &pipe)) 4615 return NULL; 4616 4617 crtc = intel_crtc_for_pipe(dev_priv, pipe); 4618 4619 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 4620 if (!mode) 4621 return NULL; 4622 4623 crtc_state = intel_crtc_state_alloc(crtc); 4624 if (!crtc_state) { 4625 kfree(mode); 4626 return NULL; 4627 } 4628 4629 if (!intel_crtc_get_pipe_config(crtc_state)) { 4630 kfree(crtc_state); 4631 kfree(mode); 4632 return NULL; 4633 } 4634 4635 intel_encoder_get_config(encoder, crtc_state); 4636 4637 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode); 4638 4639 kfree(crtc_state); 4640 4641 return mode; 4642 } 4643 4644 static bool encoders_cloneable(const struct intel_encoder *a, 4645 const struct intel_encoder *b) 4646 { 4647 /* masks could be asymmetric, so check both ways */ 4648 return a == b || (a->cloneable & (1 << b->type) && 4649 b->cloneable & (1 << a->type)); 4650 } 4651 4652 static bool check_single_encoder_cloning(struct intel_atomic_state *state, 4653 struct intel_crtc *crtc, 4654 struct intel_encoder *encoder) 4655 { 4656 struct intel_encoder *source_encoder; 4657 struct drm_connector *connector; 4658 struct drm_connector_state *connector_state; 4659 int i; 4660 4661 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4662 if (connector_state->crtc != &crtc->base) 4663 continue; 4664 4665 source_encoder = 4666 to_intel_encoder(connector_state->best_encoder); 4667 if (!encoders_cloneable(encoder, source_encoder)) 4668 return false; 4669 } 4670 4671 return true; 4672 } 4673 4674 static int icl_add_linked_planes(struct intel_atomic_state *state) 4675 { 4676 struct intel_plane *plane, *linked; 4677 struct intel_plane_state *plane_state, *linked_plane_state; 4678 int i; 4679 4680 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4681 linked = plane_state->planar_linked_plane; 4682 4683 if (!linked) 4684 continue; 4685 4686 linked_plane_state = intel_atomic_get_plane_state(state, linked); 4687 if (IS_ERR(linked_plane_state)) 4688 return PTR_ERR(linked_plane_state); 4689 4690 drm_WARN_ON(state->base.dev, 4691 linked_plane_state->planar_linked_plane != plane); 4692 drm_WARN_ON(state->base.dev, 4693 linked_plane_state->planar_slave == plane_state->planar_slave); 4694 } 4695 4696 return 0; 4697 } 4698 4699 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state) 4700 { 4701 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4702 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4703 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 4704 struct intel_plane *plane, *linked; 4705 struct intel_plane_state *plane_state; 4706 int i; 4707 4708 if (DISPLAY_VER(dev_priv) < 11) 4709 return 0; 4710 4711 /* 4712 * Destroy all old plane links and make the slave plane invisible 4713 * in the crtc_state->active_planes mask. 4714 */ 4715 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4716 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane) 4717 continue; 4718 4719 plane_state->planar_linked_plane = NULL; 4720 if (plane_state->planar_slave && !plane_state->uapi.visible) { 4721 crtc_state->enabled_planes &= ~BIT(plane->id); 4722 crtc_state->active_planes &= ~BIT(plane->id); 4723 crtc_state->update_planes |= BIT(plane->id); 4724 crtc_state->data_rate[plane->id] = 0; 4725 crtc_state->rel_data_rate[plane->id] = 0; 4726 } 4727 4728 plane_state->planar_slave = false; 4729 } 4730 4731 if (!crtc_state->nv12_planes) 4732 return 0; 4733 4734 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4735 struct intel_plane_state *linked_state = NULL; 4736 4737 if (plane->pipe != crtc->pipe || 4738 !(crtc_state->nv12_planes & BIT(plane->id))) 4739 continue; 4740 4741 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) { 4742 if (!icl_is_nv12_y_plane(dev_priv, linked->id)) 4743 continue; 4744 4745 if (crtc_state->active_planes & BIT(linked->id)) 4746 continue; 4747 4748 linked_state = intel_atomic_get_plane_state(state, linked); 4749 if (IS_ERR(linked_state)) 4750 return PTR_ERR(linked_state); 4751 4752 break; 4753 } 4754 4755 if (!linked_state) { 4756 drm_dbg_kms(&dev_priv->drm, 4757 "Need %d free Y planes for planar YUV\n", 4758 hweight8(crtc_state->nv12_planes)); 4759 4760 return -EINVAL; 4761 } 4762 4763 plane_state->planar_linked_plane = linked; 4764 4765 linked_state->planar_slave = true; 4766 linked_state->planar_linked_plane = plane; 4767 crtc_state->enabled_planes |= BIT(linked->id); 4768 crtc_state->active_planes |= BIT(linked->id); 4769 crtc_state->update_planes |= BIT(linked->id); 4770 crtc_state->data_rate[linked->id] = 4771 crtc_state->data_rate_y[plane->id]; 4772 crtc_state->rel_data_rate[linked->id] = 4773 crtc_state->rel_data_rate_y[plane->id]; 4774 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n", 4775 linked->base.name, plane->base.name); 4776 4777 /* Copy parameters to slave plane */ 4778 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE; 4779 linked_state->color_ctl = plane_state->color_ctl; 4780 linked_state->view = plane_state->view; 4781 linked_state->decrypt = plane_state->decrypt; 4782 4783 intel_plane_copy_hw_state(linked_state, plane_state); 4784 linked_state->uapi.src = plane_state->uapi.src; 4785 linked_state->uapi.dst = plane_state->uapi.dst; 4786 4787 if (icl_is_hdr_plane(dev_priv, plane->id)) { 4788 if (linked->id == PLANE_SPRITE5) 4789 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL; 4790 else if (linked->id == PLANE_SPRITE4) 4791 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL; 4792 else if (linked->id == PLANE_SPRITE3) 4793 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL; 4794 else if (linked->id == PLANE_SPRITE2) 4795 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL; 4796 else 4797 MISSING_CASE(linked->id); 4798 } 4799 } 4800 4801 return 0; 4802 } 4803 4804 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state) 4805 { 4806 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 4807 struct intel_atomic_state *state = 4808 to_intel_atomic_state(new_crtc_state->uapi.state); 4809 const struct intel_crtc_state *old_crtc_state = 4810 intel_atomic_get_old_crtc_state(state, crtc); 4811 4812 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes; 4813 } 4814 4815 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) 4816 { 4817 const struct drm_display_mode *pipe_mode = 4818 &crtc_state->hw.pipe_mode; 4819 int linetime_wm; 4820 4821 if (!crtc_state->hw.enable) 4822 return 0; 4823 4824 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4825 pipe_mode->crtc_clock); 4826 4827 return min(linetime_wm, 0x1ff); 4828 } 4829 4830 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, 4831 const struct intel_cdclk_state *cdclk_state) 4832 { 4833 const struct drm_display_mode *pipe_mode = 4834 &crtc_state->hw.pipe_mode; 4835 int linetime_wm; 4836 4837 if (!crtc_state->hw.enable) 4838 return 0; 4839 4840 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4841 cdclk_state->logical.cdclk); 4842 4843 return min(linetime_wm, 0x1ff); 4844 } 4845 4846 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) 4847 { 4848 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4849 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4850 const struct drm_display_mode *pipe_mode = 4851 &crtc_state->hw.pipe_mode; 4852 int linetime_wm; 4853 4854 if (!crtc_state->hw.enable) 4855 return 0; 4856 4857 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8, 4858 crtc_state->pixel_rate); 4859 4860 /* Display WA #1135: BXT:ALL GLK:ALL */ 4861 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 4862 dev_priv->ipc_enabled) 4863 linetime_wm /= 2; 4864 4865 return min(linetime_wm, 0x1ff); 4866 } 4867 4868 static int hsw_compute_linetime_wm(struct intel_atomic_state *state, 4869 struct intel_crtc *crtc) 4870 { 4871 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4872 struct intel_crtc_state *crtc_state = 4873 intel_atomic_get_new_crtc_state(state, crtc); 4874 const struct intel_cdclk_state *cdclk_state; 4875 4876 if (DISPLAY_VER(dev_priv) >= 9) 4877 crtc_state->linetime = skl_linetime_wm(crtc_state); 4878 else 4879 crtc_state->linetime = hsw_linetime_wm(crtc_state); 4880 4881 if (!hsw_crtc_supports_ips(crtc)) 4882 return 0; 4883 4884 cdclk_state = intel_atomic_get_cdclk_state(state); 4885 if (IS_ERR(cdclk_state)) 4886 return PTR_ERR(cdclk_state); 4887 4888 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state, 4889 cdclk_state); 4890 4891 return 0; 4892 } 4893 4894 static int intel_crtc_atomic_check(struct intel_atomic_state *state, 4895 struct intel_crtc *crtc) 4896 { 4897 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4898 struct intel_crtc_state *crtc_state = 4899 intel_atomic_get_new_crtc_state(state, crtc); 4900 bool mode_changed = intel_crtc_needs_modeset(crtc_state); 4901 int ret; 4902 4903 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) && 4904 mode_changed && !crtc_state->hw.active) 4905 crtc_state->update_wm_post = true; 4906 4907 if (mode_changed) { 4908 ret = intel_dpll_crtc_compute_clock(state, crtc); 4909 if (ret) 4910 return ret; 4911 } 4912 4913 /* 4914 * May need to update pipe gamma enable bits 4915 * when C8 planes are getting enabled/disabled. 4916 */ 4917 if (c8_planes_changed(crtc_state)) 4918 crtc_state->uapi.color_mgmt_changed = true; 4919 4920 if (mode_changed || crtc_state->update_pipe || 4921 crtc_state->uapi.color_mgmt_changed) { 4922 ret = intel_color_check(crtc_state); 4923 if (ret) 4924 return ret; 4925 } 4926 4927 ret = intel_compute_pipe_wm(state, crtc); 4928 if (ret) { 4929 drm_dbg_kms(&dev_priv->drm, 4930 "Target pipe watermarks are invalid\n"); 4931 return ret; 4932 } 4933 4934 /* 4935 * Calculate 'intermediate' watermarks that satisfy both the 4936 * old state and the new state. We can program these 4937 * immediately. 4938 */ 4939 ret = intel_compute_intermediate_wm(state, crtc); 4940 if (ret) { 4941 drm_dbg_kms(&dev_priv->drm, 4942 "No valid intermediate pipe watermarks are possible\n"); 4943 return ret; 4944 } 4945 4946 if (DISPLAY_VER(dev_priv) >= 9) { 4947 if (mode_changed || crtc_state->update_pipe) { 4948 ret = skl_update_scaler_crtc(crtc_state); 4949 if (ret) 4950 return ret; 4951 } 4952 4953 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state); 4954 if (ret) 4955 return ret; 4956 } 4957 4958 if (HAS_IPS(dev_priv)) { 4959 ret = hsw_ips_compute_config(state, crtc); 4960 if (ret) 4961 return ret; 4962 } 4963 4964 if (DISPLAY_VER(dev_priv) >= 9 || 4965 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 4966 ret = hsw_compute_linetime_wm(state, crtc); 4967 if (ret) 4968 return ret; 4969 4970 } 4971 4972 ret = intel_psr2_sel_fetch_update(state, crtc); 4973 if (ret) 4974 return ret; 4975 4976 return 0; 4977 } 4978 4979 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) 4980 { 4981 struct intel_connector *connector; 4982 struct drm_connector_list_iter conn_iter; 4983 4984 drm_connector_list_iter_begin(dev, &conn_iter); 4985 for_each_intel_connector_iter(connector, &conn_iter) { 4986 struct drm_connector_state *conn_state = connector->base.state; 4987 struct intel_encoder *encoder = 4988 to_intel_encoder(connector->base.encoder); 4989 4990 if (conn_state->crtc) 4991 drm_connector_put(&connector->base); 4992 4993 if (encoder) { 4994 struct intel_crtc *crtc = 4995 to_intel_crtc(encoder->base.crtc); 4996 const struct intel_crtc_state *crtc_state = 4997 to_intel_crtc_state(crtc->base.state); 4998 4999 conn_state->best_encoder = &encoder->base; 5000 conn_state->crtc = &crtc->base; 5001 conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3; 5002 5003 drm_connector_get(&connector->base); 5004 } else { 5005 conn_state->best_encoder = NULL; 5006 conn_state->crtc = NULL; 5007 } 5008 } 5009 drm_connector_list_iter_end(&conn_iter); 5010 } 5011 5012 static int 5013 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state, 5014 struct intel_crtc_state *pipe_config) 5015 { 5016 struct drm_connector *connector = conn_state->connector; 5017 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); 5018 const struct drm_display_info *info = &connector->display_info; 5019 int bpp; 5020 5021 switch (conn_state->max_bpc) { 5022 case 6 ... 7: 5023 bpp = 6 * 3; 5024 break; 5025 case 8 ... 9: 5026 bpp = 8 * 3; 5027 break; 5028 case 10 ... 11: 5029 bpp = 10 * 3; 5030 break; 5031 case 12 ... 16: 5032 bpp = 12 * 3; 5033 break; 5034 default: 5035 MISSING_CASE(conn_state->max_bpc); 5036 return -EINVAL; 5037 } 5038 5039 if (bpp < pipe_config->pipe_bpp) { 5040 drm_dbg_kms(&i915->drm, 5041 "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of " 5042 "EDID bpp %d, requested bpp %d, max platform bpp %d\n", 5043 connector->base.id, connector->name, 5044 bpp, 3 * info->bpc, 5045 3 * conn_state->max_requested_bpc, 5046 pipe_config->pipe_bpp); 5047 5048 pipe_config->pipe_bpp = bpp; 5049 } 5050 5051 return 0; 5052 } 5053 5054 static int 5055 compute_baseline_pipe_bpp(struct intel_crtc *crtc, 5056 struct intel_crtc_state *pipe_config) 5057 { 5058 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5059 struct drm_atomic_state *state = pipe_config->uapi.state; 5060 struct drm_connector *connector; 5061 struct drm_connector_state *connector_state; 5062 int bpp, i; 5063 5064 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 5065 IS_CHERRYVIEW(dev_priv))) 5066 bpp = 10*3; 5067 else if (DISPLAY_VER(dev_priv) >= 5) 5068 bpp = 12*3; 5069 else 5070 bpp = 8*3; 5071 5072 pipe_config->pipe_bpp = bpp; 5073 5074 /* Clamp display bpp to connector max bpp */ 5075 for_each_new_connector_in_state(state, connector, connector_state, i) { 5076 int ret; 5077 5078 if (connector_state->crtc != &crtc->base) 5079 continue; 5080 5081 ret = compute_sink_pipe_bpp(connector_state, pipe_config); 5082 if (ret) 5083 return ret; 5084 } 5085 5086 return 0; 5087 } 5088 5089 static void intel_dump_crtc_timings(struct drm_i915_private *i915, 5090 const struct drm_display_mode *mode) 5091 { 5092 drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, " 5093 "type: 0x%x flags: 0x%x\n", 5094 mode->crtc_clock, 5095 mode->crtc_hdisplay, mode->crtc_hsync_start, 5096 mode->crtc_hsync_end, mode->crtc_htotal, 5097 mode->crtc_vdisplay, mode->crtc_vsync_start, 5098 mode->crtc_vsync_end, mode->crtc_vtotal, 5099 mode->type, mode->flags); 5100 } 5101 5102 static void 5103 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config, 5104 const char *id, unsigned int lane_count, 5105 const struct intel_link_m_n *m_n) 5106 { 5107 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); 5108 5109 drm_dbg_kms(&i915->drm, 5110 "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n", 5111 id, lane_count, 5112 m_n->data_m, m_n->data_n, 5113 m_n->link_m, m_n->link_n, m_n->tu); 5114 } 5115 5116 static void 5117 intel_dump_infoframe(struct drm_i915_private *dev_priv, 5118 const union hdmi_infoframe *frame) 5119 { 5120 if (!drm_debug_enabled(DRM_UT_KMS)) 5121 return; 5122 5123 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame); 5124 } 5125 5126 static void 5127 intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv, 5128 const struct drm_dp_vsc_sdp *vsc) 5129 { 5130 if (!drm_debug_enabled(DRM_UT_KMS)) 5131 return; 5132 5133 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc); 5134 } 5135 5136 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x 5137 5138 static const char * const output_type_str[] = { 5139 OUTPUT_TYPE(UNUSED), 5140 OUTPUT_TYPE(ANALOG), 5141 OUTPUT_TYPE(DVO), 5142 OUTPUT_TYPE(SDVO), 5143 OUTPUT_TYPE(LVDS), 5144 OUTPUT_TYPE(TVOUT), 5145 OUTPUT_TYPE(HDMI), 5146 OUTPUT_TYPE(DP), 5147 OUTPUT_TYPE(EDP), 5148 OUTPUT_TYPE(DSI), 5149 OUTPUT_TYPE(DDI), 5150 OUTPUT_TYPE(DP_MST), 5151 }; 5152 5153 #undef OUTPUT_TYPE 5154 5155 static void snprintf_output_types(char *buf, size_t len, 5156 unsigned int output_types) 5157 { 5158 char *str = buf; 5159 int i; 5160 5161 str[0] = '\0'; 5162 5163 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) { 5164 int r; 5165 5166 if ((output_types & BIT(i)) == 0) 5167 continue; 5168 5169 r = snprintf(str, len, "%s%s", 5170 str != buf ? "," : "", output_type_str[i]); 5171 if (r >= len) 5172 break; 5173 str += r; 5174 len -= r; 5175 5176 output_types &= ~BIT(i); 5177 } 5178 5179 WARN_ON_ONCE(output_types != 0); 5180 } 5181 5182 static const char * const output_format_str[] = { 5183 [INTEL_OUTPUT_FORMAT_RGB] = "RGB", 5184 [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0", 5185 [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4", 5186 }; 5187 5188 static const char *output_formats(enum intel_output_format format) 5189 { 5190 if (format >= ARRAY_SIZE(output_format_str)) 5191 return "invalid"; 5192 return output_format_str[format]; 5193 } 5194 5195 static void intel_dump_plane_state(const struct intel_plane_state *plane_state) 5196 { 5197 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 5198 struct drm_i915_private *i915 = to_i915(plane->base.dev); 5199 const struct drm_framebuffer *fb = plane_state->hw.fb; 5200 5201 if (!fb) { 5202 drm_dbg_kms(&i915->drm, 5203 "[PLANE:%d:%s] fb: [NOFB], visible: %s\n", 5204 plane->base.base.id, plane->base.name, 5205 str_yes_no(plane_state->uapi.visible)); 5206 return; 5207 } 5208 5209 drm_dbg_kms(&i915->drm, 5210 "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %p4cc modifier = 0x%llx, visible: %s\n", 5211 plane->base.base.id, plane->base.name, 5212 fb->base.id, fb->width, fb->height, &fb->format->format, 5213 fb->modifier, str_yes_no(plane_state->uapi.visible)); 5214 drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n", 5215 plane_state->hw.rotation, plane_state->scaler_id); 5216 if (plane_state->uapi.visible) 5217 drm_dbg_kms(&i915->drm, 5218 "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n", 5219 DRM_RECT_FP_ARG(&plane_state->uapi.src), 5220 DRM_RECT_ARG(&plane_state->uapi.dst)); 5221 } 5222 5223 static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, 5224 struct intel_atomic_state *state, 5225 const char *context) 5226 { 5227 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 5228 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5229 const struct intel_plane_state *plane_state; 5230 struct intel_plane *plane; 5231 char buf[64]; 5232 int i; 5233 5234 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n", 5235 crtc->base.base.id, crtc->base.name, 5236 str_yes_no(pipe_config->hw.enable), context); 5237 5238 if (!pipe_config->hw.enable) 5239 goto dump_planes; 5240 5241 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types); 5242 drm_dbg_kms(&dev_priv->drm, 5243 "active: %s, output_types: %s (0x%x), output format: %s\n", 5244 str_yes_no(pipe_config->hw.active), 5245 buf, pipe_config->output_types, 5246 output_formats(pipe_config->output_format)); 5247 5248 drm_dbg_kms(&dev_priv->drm, 5249 "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", 5250 transcoder_name(pipe_config->cpu_transcoder), 5251 pipe_config->pipe_bpp, pipe_config->dither); 5252 5253 drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n", 5254 transcoder_name(pipe_config->mst_master_transcoder)); 5255 5256 drm_dbg_kms(&dev_priv->drm, 5257 "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n", 5258 transcoder_name(pipe_config->master_transcoder), 5259 pipe_config->sync_mode_slaves_mask); 5260 5261 drm_dbg_kms(&dev_priv->drm, "bigjoiner: %s, pipes: 0x%x\n", 5262 intel_crtc_is_bigjoiner_slave(pipe_config) ? "slave" : 5263 intel_crtc_is_bigjoiner_master(pipe_config) ? "master" : "no", 5264 pipe_config->bigjoiner_pipes); 5265 5266 drm_dbg_kms(&dev_priv->drm, "splitter: %s, link count %d, overlap %d\n", 5267 str_enabled_disabled(pipe_config->splitter.enable), 5268 pipe_config->splitter.link_count, 5269 pipe_config->splitter.pixel_overlap); 5270 5271 if (pipe_config->has_pch_encoder) 5272 intel_dump_m_n_config(pipe_config, "fdi", 5273 pipe_config->fdi_lanes, 5274 &pipe_config->fdi_m_n); 5275 5276 if (intel_crtc_has_dp_encoder(pipe_config)) { 5277 intel_dump_m_n_config(pipe_config, "dp m_n", 5278 pipe_config->lane_count, 5279 &pipe_config->dp_m_n); 5280 intel_dump_m_n_config(pipe_config, "dp m2_n2", 5281 pipe_config->lane_count, 5282 &pipe_config->dp_m2_n2); 5283 } 5284 5285 drm_dbg_kms(&dev_priv->drm, "framestart delay: %d, MSA timing delay: %d\n", 5286 pipe_config->framestart_delay, pipe_config->msa_timing_delay); 5287 5288 drm_dbg_kms(&dev_priv->drm, 5289 "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n", 5290 pipe_config->has_audio, pipe_config->has_infoframe, 5291 pipe_config->infoframes.enable); 5292 5293 if (pipe_config->infoframes.enable & 5294 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) 5295 drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n", 5296 pipe_config->infoframes.gcp); 5297 if (pipe_config->infoframes.enable & 5298 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) 5299 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi); 5300 if (pipe_config->infoframes.enable & 5301 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD)) 5302 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd); 5303 if (pipe_config->infoframes.enable & 5304 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR)) 5305 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi); 5306 if (pipe_config->infoframes.enable & 5307 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) 5308 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); 5309 if (pipe_config->infoframes.enable & 5310 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA)) 5311 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); 5312 if (pipe_config->infoframes.enable & 5313 intel_hdmi_infoframe_enable(DP_SDP_VSC)) 5314 intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc); 5315 5316 drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n", 5317 str_yes_no(pipe_config->vrr.enable), 5318 pipe_config->vrr.vmin, pipe_config->vrr.vmax, 5319 pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband, 5320 pipe_config->vrr.flipline, 5321 intel_vrr_vmin_vblank_start(pipe_config), 5322 intel_vrr_vmax_vblank_start(pipe_config)); 5323 5324 drm_dbg_kms(&dev_priv->drm, "requested mode: " DRM_MODE_FMT "\n", 5325 DRM_MODE_ARG(&pipe_config->hw.mode)); 5326 drm_dbg_kms(&dev_priv->drm, "adjusted mode: " DRM_MODE_FMT "\n", 5327 DRM_MODE_ARG(&pipe_config->hw.adjusted_mode)); 5328 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode); 5329 drm_dbg_kms(&dev_priv->drm, "pipe mode: " DRM_MODE_FMT "\n", 5330 DRM_MODE_ARG(&pipe_config->hw.pipe_mode)); 5331 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode); 5332 drm_dbg_kms(&dev_priv->drm, 5333 "port clock: %d, pipe src: " DRM_RECT_FMT ", pixel rate %d\n", 5334 pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src), 5335 pipe_config->pixel_rate); 5336 5337 drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n", 5338 pipe_config->linetime, pipe_config->ips_linetime); 5339 5340 if (DISPLAY_VER(dev_priv) >= 9) 5341 drm_dbg_kms(&dev_priv->drm, 5342 "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", 5343 crtc->num_scalers, 5344 pipe_config->scaler_state.scaler_users, 5345 pipe_config->scaler_state.scaler_id); 5346 5347 if (HAS_GMCH(dev_priv)) 5348 drm_dbg_kms(&dev_priv->drm, 5349 "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", 5350 pipe_config->gmch_pfit.control, 5351 pipe_config->gmch_pfit.pgm_ratios, 5352 pipe_config->gmch_pfit.lvds_border_bits); 5353 else 5354 drm_dbg_kms(&dev_priv->drm, 5355 "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n", 5356 DRM_RECT_ARG(&pipe_config->pch_pfit.dst), 5357 str_enabled_disabled(pipe_config->pch_pfit.enabled), 5358 str_yes_no(pipe_config->pch_pfit.force_thru)); 5359 5360 drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i, drrs: %i\n", 5361 pipe_config->ips_enabled, pipe_config->double_wide, 5362 pipe_config->has_drrs); 5363 5364 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state); 5365 5366 if (IS_CHERRYVIEW(dev_priv)) 5367 drm_dbg_kms(&dev_priv->drm, 5368 "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", 5369 pipe_config->cgm_mode, pipe_config->gamma_mode, 5370 pipe_config->gamma_enable, pipe_config->csc_enable); 5371 else 5372 drm_dbg_kms(&dev_priv->drm, 5373 "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", 5374 pipe_config->csc_mode, pipe_config->gamma_mode, 5375 pipe_config->gamma_enable, pipe_config->csc_enable); 5376 5377 drm_dbg_kms(&dev_priv->drm, "degamma lut: %d entries, gamma lut: %d entries\n", 5378 pipe_config->hw.degamma_lut ? 5379 drm_color_lut_size(pipe_config->hw.degamma_lut) : 0, 5380 pipe_config->hw.gamma_lut ? 5381 drm_color_lut_size(pipe_config->hw.gamma_lut) : 0); 5382 5383 dump_planes: 5384 if (!state) 5385 return; 5386 5387 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 5388 if (plane->pipe == crtc->pipe) 5389 intel_dump_plane_state(plane_state); 5390 } 5391 } 5392 5393 static bool check_digital_port_conflicts(struct intel_atomic_state *state) 5394 { 5395 struct drm_device *dev = state->base.dev; 5396 struct drm_connector *connector; 5397 struct drm_connector_list_iter conn_iter; 5398 unsigned int used_ports = 0; 5399 unsigned int used_mst_ports = 0; 5400 bool ret = true; 5401 5402 /* 5403 * We're going to peek into connector->state, 5404 * hence connection_mutex must be held. 5405 */ 5406 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex); 5407 5408 /* 5409 * Walk the connector list instead of the encoder 5410 * list to detect the problem on ddi platforms 5411 * where there's just one encoder per digital port. 5412 */ 5413 drm_connector_list_iter_begin(dev, &conn_iter); 5414 drm_for_each_connector_iter(connector, &conn_iter) { 5415 struct drm_connector_state *connector_state; 5416 struct intel_encoder *encoder; 5417 5418 connector_state = 5419 drm_atomic_get_new_connector_state(&state->base, 5420 connector); 5421 if (!connector_state) 5422 connector_state = connector->state; 5423 5424 if (!connector_state->best_encoder) 5425 continue; 5426 5427 encoder = to_intel_encoder(connector_state->best_encoder); 5428 5429 drm_WARN_ON(dev, !connector_state->crtc); 5430 5431 switch (encoder->type) { 5432 case INTEL_OUTPUT_DDI: 5433 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev)))) 5434 break; 5435 fallthrough; 5436 case INTEL_OUTPUT_DP: 5437 case INTEL_OUTPUT_HDMI: 5438 case INTEL_OUTPUT_EDP: 5439 /* the same port mustn't appear more than once */ 5440 if (used_ports & BIT(encoder->port)) 5441 ret = false; 5442 5443 used_ports |= BIT(encoder->port); 5444 break; 5445 case INTEL_OUTPUT_DP_MST: 5446 used_mst_ports |= 5447 1 << encoder->port; 5448 break; 5449 default: 5450 break; 5451 } 5452 } 5453 drm_connector_list_iter_end(&conn_iter); 5454 5455 /* can't mix MST and SST/HDMI on the same port */ 5456 if (used_ports & used_mst_ports) 5457 return false; 5458 5459 return ret; 5460 } 5461 5462 static void 5463 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state, 5464 struct intel_crtc *crtc) 5465 { 5466 struct intel_crtc_state *crtc_state = 5467 intel_atomic_get_new_crtc_state(state, crtc); 5468 5469 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 5470 5471 drm_property_replace_blob(&crtc_state->hw.degamma_lut, 5472 crtc_state->uapi.degamma_lut); 5473 drm_property_replace_blob(&crtc_state->hw.gamma_lut, 5474 crtc_state->uapi.gamma_lut); 5475 drm_property_replace_blob(&crtc_state->hw.ctm, 5476 crtc_state->uapi.ctm); 5477 } 5478 5479 static void 5480 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state, 5481 struct intel_crtc *crtc) 5482 { 5483 struct intel_crtc_state *crtc_state = 5484 intel_atomic_get_new_crtc_state(state, crtc); 5485 5486 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 5487 5488 crtc_state->hw.enable = crtc_state->uapi.enable; 5489 crtc_state->hw.active = crtc_state->uapi.active; 5490 drm_mode_copy(&crtc_state->hw.mode, 5491 &crtc_state->uapi.mode); 5492 drm_mode_copy(&crtc_state->hw.adjusted_mode, 5493 &crtc_state->uapi.adjusted_mode); 5494 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter; 5495 5496 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 5497 } 5498 5499 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state) 5500 { 5501 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 5502 return; 5503 5504 crtc_state->uapi.enable = crtc_state->hw.enable; 5505 crtc_state->uapi.active = crtc_state->hw.active; 5506 drm_WARN_ON(crtc_state->uapi.crtc->dev, 5507 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0); 5508 5509 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode; 5510 crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter; 5511 5512 drm_property_replace_blob(&crtc_state->uapi.degamma_lut, 5513 crtc_state->hw.degamma_lut); 5514 drm_property_replace_blob(&crtc_state->uapi.gamma_lut, 5515 crtc_state->hw.gamma_lut); 5516 drm_property_replace_blob(&crtc_state->uapi.ctm, 5517 crtc_state->hw.ctm); 5518 } 5519 5520 static void 5521 copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state, 5522 struct intel_crtc *slave_crtc) 5523 { 5524 struct intel_crtc_state *slave_crtc_state = 5525 intel_atomic_get_new_crtc_state(state, slave_crtc); 5526 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 5527 const struct intel_crtc_state *master_crtc_state = 5528 intel_atomic_get_new_crtc_state(state, master_crtc); 5529 5530 drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut, 5531 master_crtc_state->hw.degamma_lut); 5532 drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut, 5533 master_crtc_state->hw.gamma_lut); 5534 drm_property_replace_blob(&slave_crtc_state->hw.ctm, 5535 master_crtc_state->hw.ctm); 5536 5537 slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed; 5538 } 5539 5540 static int 5541 copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state, 5542 struct intel_crtc *slave_crtc) 5543 { 5544 struct intel_crtc_state *slave_crtc_state = 5545 intel_atomic_get_new_crtc_state(state, slave_crtc); 5546 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 5547 const struct intel_crtc_state *master_crtc_state = 5548 intel_atomic_get_new_crtc_state(state, master_crtc); 5549 struct intel_crtc_state *saved_state; 5550 5551 WARN_ON(master_crtc_state->bigjoiner_pipes != 5552 slave_crtc_state->bigjoiner_pipes); 5553 5554 saved_state = kmemdup(master_crtc_state, sizeof(*saved_state), GFP_KERNEL); 5555 if (!saved_state) 5556 return -ENOMEM; 5557 5558 /* preserve some things from the slave's original crtc state */ 5559 saved_state->uapi = slave_crtc_state->uapi; 5560 saved_state->scaler_state = slave_crtc_state->scaler_state; 5561 saved_state->shared_dpll = slave_crtc_state->shared_dpll; 5562 saved_state->dpll_hw_state = slave_crtc_state->dpll_hw_state; 5563 saved_state->crc_enabled = slave_crtc_state->crc_enabled; 5564 5565 intel_crtc_free_hw_state(slave_crtc_state); 5566 memcpy(slave_crtc_state, saved_state, sizeof(*slave_crtc_state)); 5567 kfree(saved_state); 5568 5569 /* Re-init hw state */ 5570 memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw)); 5571 slave_crtc_state->hw.enable = master_crtc_state->hw.enable; 5572 slave_crtc_state->hw.active = master_crtc_state->hw.active; 5573 drm_mode_copy(&slave_crtc_state->hw.mode, 5574 &master_crtc_state->hw.mode); 5575 drm_mode_copy(&slave_crtc_state->hw.pipe_mode, 5576 &master_crtc_state->hw.pipe_mode); 5577 drm_mode_copy(&slave_crtc_state->hw.adjusted_mode, 5578 &master_crtc_state->hw.adjusted_mode); 5579 slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter; 5580 5581 copy_bigjoiner_crtc_state_nomodeset(state, slave_crtc); 5582 5583 slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed; 5584 slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed; 5585 slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed; 5586 5587 WARN_ON(master_crtc_state->bigjoiner_pipes != 5588 slave_crtc_state->bigjoiner_pipes); 5589 5590 return 0; 5591 } 5592 5593 static int 5594 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state, 5595 struct intel_crtc *crtc) 5596 { 5597 struct intel_crtc_state *crtc_state = 5598 intel_atomic_get_new_crtc_state(state, crtc); 5599 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5600 struct intel_crtc_state *saved_state; 5601 5602 saved_state = intel_crtc_state_alloc(crtc); 5603 if (!saved_state) 5604 return -ENOMEM; 5605 5606 /* free the old crtc_state->hw members */ 5607 intel_crtc_free_hw_state(crtc_state); 5608 5609 /* FIXME: before the switch to atomic started, a new pipe_config was 5610 * kzalloc'd. Code that depends on any field being zero should be 5611 * fixed, so that the crtc_state can be safely duplicated. For now, 5612 * only fields that are know to not cause problems are preserved. */ 5613 5614 saved_state->uapi = crtc_state->uapi; 5615 saved_state->scaler_state = crtc_state->scaler_state; 5616 saved_state->shared_dpll = crtc_state->shared_dpll; 5617 saved_state->dpll_hw_state = crtc_state->dpll_hw_state; 5618 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, 5619 sizeof(saved_state->icl_port_dplls)); 5620 saved_state->crc_enabled = crtc_state->crc_enabled; 5621 if (IS_G4X(dev_priv) || 5622 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5623 saved_state->wm = crtc_state->wm; 5624 5625 memcpy(crtc_state, saved_state, sizeof(*crtc_state)); 5626 kfree(saved_state); 5627 5628 intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc); 5629 5630 return 0; 5631 } 5632 5633 static int 5634 intel_modeset_pipe_config(struct intel_atomic_state *state, 5635 struct intel_crtc_state *pipe_config) 5636 { 5637 struct drm_crtc *crtc = pipe_config->uapi.crtc; 5638 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); 5639 struct drm_connector *connector; 5640 struct drm_connector_state *connector_state; 5641 int pipe_src_w, pipe_src_h; 5642 int base_bpp, ret, i; 5643 bool retry = true; 5644 5645 pipe_config->cpu_transcoder = 5646 (enum transcoder) to_intel_crtc(crtc)->pipe; 5647 5648 pipe_config->framestart_delay = 1; 5649 5650 /* 5651 * Sanitize sync polarity flags based on requested ones. If neither 5652 * positive or negative polarity is requested, treat this as meaning 5653 * negative polarity. 5654 */ 5655 if (!(pipe_config->hw.adjusted_mode.flags & 5656 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) 5657 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; 5658 5659 if (!(pipe_config->hw.adjusted_mode.flags & 5660 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 5661 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; 5662 5663 ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc), 5664 pipe_config); 5665 if (ret) 5666 return ret; 5667 5668 base_bpp = pipe_config->pipe_bpp; 5669 5670 /* 5671 * Determine the real pipe dimensions. Note that stereo modes can 5672 * increase the actual pipe size due to the frame doubling and 5673 * insertion of additional space for blanks between the frame. This 5674 * is stored in the crtc timings. We use the requested mode to do this 5675 * computation to clearly distinguish it from the adjusted mode, which 5676 * can be changed by the connectors in the below retry loop. 5677 */ 5678 drm_mode_get_hv_timing(&pipe_config->hw.mode, 5679 &pipe_src_w, &pipe_src_h); 5680 drm_rect_init(&pipe_config->pipe_src, 0, 0, 5681 pipe_src_w, pipe_src_h); 5682 5683 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5684 struct intel_encoder *encoder = 5685 to_intel_encoder(connector_state->best_encoder); 5686 5687 if (connector_state->crtc != crtc) 5688 continue; 5689 5690 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) { 5691 drm_dbg_kms(&i915->drm, 5692 "rejecting invalid cloning configuration\n"); 5693 return -EINVAL; 5694 } 5695 5696 /* 5697 * Determine output_types before calling the .compute_config() 5698 * hooks so that the hooks can use this information safely. 5699 */ 5700 if (encoder->compute_output_type) 5701 pipe_config->output_types |= 5702 BIT(encoder->compute_output_type(encoder, pipe_config, 5703 connector_state)); 5704 else 5705 pipe_config->output_types |= BIT(encoder->type); 5706 } 5707 5708 encoder_retry: 5709 /* Ensure the port clock defaults are reset when retrying. */ 5710 pipe_config->port_clock = 0; 5711 pipe_config->pixel_multiplier = 1; 5712 5713 /* Fill in default crtc timings, allow encoders to overwrite them. */ 5714 drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode, 5715 CRTC_STEREO_DOUBLE); 5716 5717 /* Pass our mode to the connectors and the CRTC to give them a chance to 5718 * adjust it according to limitations or connector properties, and also 5719 * a chance to reject the mode entirely. 5720 */ 5721 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5722 struct intel_encoder *encoder = 5723 to_intel_encoder(connector_state->best_encoder); 5724 5725 if (connector_state->crtc != crtc) 5726 continue; 5727 5728 ret = encoder->compute_config(encoder, pipe_config, 5729 connector_state); 5730 if (ret == -EDEADLK) 5731 return ret; 5732 if (ret < 0) { 5733 drm_dbg_kms(&i915->drm, "Encoder config failure: %d\n", ret); 5734 return ret; 5735 } 5736 } 5737 5738 /* Set default port clock if not overwritten by the encoder. Needs to be 5739 * done afterwards in case the encoder adjusts the mode. */ 5740 if (!pipe_config->port_clock) 5741 pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock 5742 * pipe_config->pixel_multiplier; 5743 5744 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); 5745 if (ret == -EDEADLK) 5746 return ret; 5747 if (ret == -EAGAIN) { 5748 if (drm_WARN(&i915->drm, !retry, 5749 "loop in pipe configuration computation\n")) 5750 return -EINVAL; 5751 5752 drm_dbg_kms(&i915->drm, "CRTC bw constrained, retrying\n"); 5753 retry = false; 5754 goto encoder_retry; 5755 } 5756 if (ret < 0) { 5757 drm_dbg_kms(&i915->drm, "CRTC config failure: %d\n", ret); 5758 return ret; 5759 } 5760 5761 /* Dithering seems to not pass-through bits correctly when it should, so 5762 * only enable it on 6bpc panels and when its not a compliance 5763 * test requesting 6bpc video pattern. 5764 */ 5765 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) && 5766 !pipe_config->dither_force_disable; 5767 drm_dbg_kms(&i915->drm, 5768 "hw max bpp: %i, pipe bpp: %i, dithering: %i\n", 5769 base_bpp, pipe_config->pipe_bpp, pipe_config->dither); 5770 5771 return 0; 5772 } 5773 5774 static int 5775 intel_modeset_pipe_config_late(struct intel_crtc_state *crtc_state) 5776 { 5777 struct intel_atomic_state *state = 5778 to_intel_atomic_state(crtc_state->uapi.state); 5779 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 5780 struct drm_connector_state *conn_state; 5781 struct drm_connector *connector; 5782 int i; 5783 5784 intel_bigjoiner_adjust_pipe_src(crtc_state); 5785 5786 for_each_new_connector_in_state(&state->base, connector, 5787 conn_state, i) { 5788 struct intel_encoder *encoder = 5789 to_intel_encoder(conn_state->best_encoder); 5790 int ret; 5791 5792 if (conn_state->crtc != &crtc->base || 5793 !encoder->compute_config_late) 5794 continue; 5795 5796 ret = encoder->compute_config_late(encoder, crtc_state, 5797 conn_state); 5798 if (ret) 5799 return ret; 5800 } 5801 5802 return 0; 5803 } 5804 5805 bool intel_fuzzy_clock_check(int clock1, int clock2) 5806 { 5807 int diff; 5808 5809 if (clock1 == clock2) 5810 return true; 5811 5812 if (!clock1 || !clock2) 5813 return false; 5814 5815 diff = abs(clock1 - clock2); 5816 5817 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) 5818 return true; 5819 5820 return false; 5821 } 5822 5823 static bool 5824 intel_compare_m_n(unsigned int m, unsigned int n, 5825 unsigned int m2, unsigned int n2, 5826 bool exact) 5827 { 5828 if (m == m2 && n == n2) 5829 return true; 5830 5831 if (exact || !m || !n || !m2 || !n2) 5832 return false; 5833 5834 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); 5835 5836 if (n > n2) { 5837 while (n > n2) { 5838 m2 <<= 1; 5839 n2 <<= 1; 5840 } 5841 } else if (n < n2) { 5842 while (n < n2) { 5843 m <<= 1; 5844 n <<= 1; 5845 } 5846 } 5847 5848 if (n != n2) 5849 return false; 5850 5851 return intel_fuzzy_clock_check(m, m2); 5852 } 5853 5854 static bool 5855 intel_compare_link_m_n(const struct intel_link_m_n *m_n, 5856 const struct intel_link_m_n *m2_n2, 5857 bool exact) 5858 { 5859 return m_n->tu == m2_n2->tu && 5860 intel_compare_m_n(m_n->data_m, m_n->data_n, 5861 m2_n2->data_m, m2_n2->data_n, exact) && 5862 intel_compare_m_n(m_n->link_m, m_n->link_n, 5863 m2_n2->link_m, m2_n2->link_n, exact); 5864 } 5865 5866 static bool 5867 intel_compare_infoframe(const union hdmi_infoframe *a, 5868 const union hdmi_infoframe *b) 5869 { 5870 return memcmp(a, b, sizeof(*a)) == 0; 5871 } 5872 5873 static bool 5874 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a, 5875 const struct drm_dp_vsc_sdp *b) 5876 { 5877 return memcmp(a, b, sizeof(*a)) == 0; 5878 } 5879 5880 static void 5881 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv, 5882 bool fastset, const char *name, 5883 const union hdmi_infoframe *a, 5884 const union hdmi_infoframe *b) 5885 { 5886 if (fastset) { 5887 if (!drm_debug_enabled(DRM_UT_KMS)) 5888 return; 5889 5890 drm_dbg_kms(&dev_priv->drm, 5891 "fastset mismatch in %s infoframe\n", name); 5892 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 5893 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a); 5894 drm_dbg_kms(&dev_priv->drm, "found:\n"); 5895 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b); 5896 } else { 5897 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name); 5898 drm_err(&dev_priv->drm, "expected:\n"); 5899 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a); 5900 drm_err(&dev_priv->drm, "found:\n"); 5901 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b); 5902 } 5903 } 5904 5905 static void 5906 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv, 5907 bool fastset, const char *name, 5908 const struct drm_dp_vsc_sdp *a, 5909 const struct drm_dp_vsc_sdp *b) 5910 { 5911 if (fastset) { 5912 if (!drm_debug_enabled(DRM_UT_KMS)) 5913 return; 5914 5915 drm_dbg_kms(&dev_priv->drm, 5916 "fastset mismatch in %s dp sdp\n", name); 5917 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 5918 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a); 5919 drm_dbg_kms(&dev_priv->drm, "found:\n"); 5920 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b); 5921 } else { 5922 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name); 5923 drm_err(&dev_priv->drm, "expected:\n"); 5924 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a); 5925 drm_err(&dev_priv->drm, "found:\n"); 5926 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b); 5927 } 5928 } 5929 5930 static void __printf(4, 5) 5931 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc, 5932 const char *name, const char *format, ...) 5933 { 5934 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 5935 struct va_format vaf; 5936 va_list args; 5937 5938 va_start(args, format); 5939 vaf.fmt = format; 5940 vaf.va = &args; 5941 5942 if (fastset) 5943 drm_dbg_kms(&i915->drm, 5944 "[CRTC:%d:%s] fastset mismatch in %s %pV\n", 5945 crtc->base.base.id, crtc->base.name, name, &vaf); 5946 else 5947 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n", 5948 crtc->base.base.id, crtc->base.name, name, &vaf); 5949 5950 va_end(args); 5951 } 5952 5953 static bool fastboot_enabled(struct drm_i915_private *dev_priv) 5954 { 5955 if (dev_priv->params.fastboot != -1) 5956 return dev_priv->params.fastboot; 5957 5958 /* Enable fastboot by default on Skylake and newer */ 5959 if (DISPLAY_VER(dev_priv) >= 9) 5960 return true; 5961 5962 /* Enable fastboot by default on VLV and CHV */ 5963 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5964 return true; 5965 5966 /* Disabled by default on all others */ 5967 return false; 5968 } 5969 5970 static bool 5971 intel_pipe_config_compare(const struct intel_crtc_state *current_config, 5972 const struct intel_crtc_state *pipe_config, 5973 bool fastset) 5974 { 5975 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev); 5976 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 5977 bool ret = true; 5978 u32 bp_gamma = 0; 5979 bool fixup_inherited = fastset && 5980 current_config->inherited && !pipe_config->inherited; 5981 5982 if (fixup_inherited && !fastboot_enabled(dev_priv)) { 5983 drm_dbg_kms(&dev_priv->drm, 5984 "initial modeset and fastboot not set\n"); 5985 ret = false; 5986 } 5987 5988 #define PIPE_CONF_CHECK_X(name) do { \ 5989 if (current_config->name != pipe_config->name) { \ 5990 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5991 "(expected 0x%08x, found 0x%08x)", \ 5992 current_config->name, \ 5993 pipe_config->name); \ 5994 ret = false; \ 5995 } \ 5996 } while (0) 5997 5998 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \ 5999 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \ 6000 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6001 "(expected 0x%08x, found 0x%08x)", \ 6002 current_config->name & (mask), \ 6003 pipe_config->name & (mask)); \ 6004 ret = false; \ 6005 } \ 6006 } while (0) 6007 6008 #define PIPE_CONF_CHECK_I(name) do { \ 6009 if (current_config->name != pipe_config->name) { \ 6010 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6011 "(expected %i, found %i)", \ 6012 current_config->name, \ 6013 pipe_config->name); \ 6014 ret = false; \ 6015 } \ 6016 } while (0) 6017 6018 #define PIPE_CONF_CHECK_BOOL(name) do { \ 6019 if (current_config->name != pipe_config->name) { \ 6020 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6021 "(expected %s, found %s)", \ 6022 str_yes_no(current_config->name), \ 6023 str_yes_no(pipe_config->name)); \ 6024 ret = false; \ 6025 } \ 6026 } while (0) 6027 6028 /* 6029 * Checks state where we only read out the enabling, but not the entire 6030 * state itself (like full infoframes or ELD for audio). These states 6031 * require a full modeset on bootup to fix up. 6032 */ 6033 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \ 6034 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \ 6035 PIPE_CONF_CHECK_BOOL(name); \ 6036 } else { \ 6037 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6038 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \ 6039 str_yes_no(current_config->name), \ 6040 str_yes_no(pipe_config->name)); \ 6041 ret = false; \ 6042 } \ 6043 } while (0) 6044 6045 #define PIPE_CONF_CHECK_P(name) do { \ 6046 if (current_config->name != pipe_config->name) { \ 6047 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6048 "(expected %p, found %p)", \ 6049 current_config->name, \ 6050 pipe_config->name); \ 6051 ret = false; \ 6052 } \ 6053 } while (0) 6054 6055 #define PIPE_CONF_CHECK_M_N(name) do { \ 6056 if (!intel_compare_link_m_n(¤t_config->name, \ 6057 &pipe_config->name,\ 6058 !fastset)) { \ 6059 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6060 "(expected tu %i data %i/%i link %i/%i, " \ 6061 "found tu %i, data %i/%i link %i/%i)", \ 6062 current_config->name.tu, \ 6063 current_config->name.data_m, \ 6064 current_config->name.data_n, \ 6065 current_config->name.link_m, \ 6066 current_config->name.link_n, \ 6067 pipe_config->name.tu, \ 6068 pipe_config->name.data_m, \ 6069 pipe_config->name.data_n, \ 6070 pipe_config->name.link_m, \ 6071 pipe_config->name.link_n); \ 6072 ret = false; \ 6073 } \ 6074 } while (0) 6075 6076 /* This is required for BDW+ where there is only one set of registers for 6077 * switching between high and low RR. 6078 * This macro can be used whenever a comparison has to be made between one 6079 * hw state and multiple sw state variables. 6080 */ 6081 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \ 6082 if (!intel_compare_link_m_n(¤t_config->name, \ 6083 &pipe_config->name, !fastset) && \ 6084 !intel_compare_link_m_n(¤t_config->alt_name, \ 6085 &pipe_config->name, !fastset)) { \ 6086 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6087 "(expected tu %i data %i/%i link %i/%i, " \ 6088 "or tu %i data %i/%i link %i/%i, " \ 6089 "found tu %i, data %i/%i link %i/%i)", \ 6090 current_config->name.tu, \ 6091 current_config->name.data_m, \ 6092 current_config->name.data_n, \ 6093 current_config->name.link_m, \ 6094 current_config->name.link_n, \ 6095 current_config->alt_name.tu, \ 6096 current_config->alt_name.data_m, \ 6097 current_config->alt_name.data_n, \ 6098 current_config->alt_name.link_m, \ 6099 current_config->alt_name.link_n, \ 6100 pipe_config->name.tu, \ 6101 pipe_config->name.data_m, \ 6102 pipe_config->name.data_n, \ 6103 pipe_config->name.link_m, \ 6104 pipe_config->name.link_n); \ 6105 ret = false; \ 6106 } \ 6107 } while (0) 6108 6109 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \ 6110 if ((current_config->name ^ pipe_config->name) & (mask)) { \ 6111 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6112 "(%x) (expected %i, found %i)", \ 6113 (mask), \ 6114 current_config->name & (mask), \ 6115 pipe_config->name & (mask)); \ 6116 ret = false; \ 6117 } \ 6118 } while (0) 6119 6120 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \ 6121 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ 6122 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 6123 "(expected %i, found %i)", \ 6124 current_config->name, \ 6125 pipe_config->name); \ 6126 ret = false; \ 6127 } \ 6128 } while (0) 6129 6130 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \ 6131 if (!intel_compare_infoframe(¤t_config->infoframes.name, \ 6132 &pipe_config->infoframes.name)) { \ 6133 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \ 6134 ¤t_config->infoframes.name, \ 6135 &pipe_config->infoframes.name); \ 6136 ret = false; \ 6137 } \ 6138 } while (0) 6139 6140 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \ 6141 if (!current_config->has_psr && !pipe_config->has_psr && \ 6142 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \ 6143 &pipe_config->infoframes.name)) { \ 6144 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \ 6145 ¤t_config->infoframes.name, \ 6146 &pipe_config->infoframes.name); \ 6147 ret = false; \ 6148 } \ 6149 } while (0) 6150 6151 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \ 6152 if (current_config->name1 != pipe_config->name1) { \ 6153 pipe_config_mismatch(fastset, crtc, __stringify(name1), \ 6154 "(expected %i, found %i, won't compare lut values)", \ 6155 current_config->name1, \ 6156 pipe_config->name1); \ 6157 ret = false;\ 6158 } else { \ 6159 if (!intel_color_lut_equal(current_config->name2, \ 6160 pipe_config->name2, pipe_config->name1, \ 6161 bit_precision)) { \ 6162 pipe_config_mismatch(fastset, crtc, __stringify(name2), \ 6163 "hw_state doesn't match sw_state"); \ 6164 ret = false; \ 6165 } \ 6166 } \ 6167 } while (0) 6168 6169 #define PIPE_CONF_QUIRK(quirk) \ 6170 ((current_config->quirks | pipe_config->quirks) & (quirk)) 6171 6172 PIPE_CONF_CHECK_I(cpu_transcoder); 6173 6174 PIPE_CONF_CHECK_BOOL(has_pch_encoder); 6175 PIPE_CONF_CHECK_I(fdi_lanes); 6176 PIPE_CONF_CHECK_M_N(fdi_m_n); 6177 6178 PIPE_CONF_CHECK_I(lane_count); 6179 PIPE_CONF_CHECK_X(lane_lat_optim_mask); 6180 6181 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) { 6182 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); 6183 } else { 6184 PIPE_CONF_CHECK_M_N(dp_m_n); 6185 PIPE_CONF_CHECK_M_N(dp_m2_n2); 6186 } 6187 6188 PIPE_CONF_CHECK_X(output_types); 6189 6190 PIPE_CONF_CHECK_I(framestart_delay); 6191 PIPE_CONF_CHECK_I(msa_timing_delay); 6192 6193 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay); 6194 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_htotal); 6195 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_start); 6196 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_end); 6197 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_start); 6198 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_end); 6199 6200 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vdisplay); 6201 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vtotal); 6202 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_start); 6203 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_end); 6204 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_start); 6205 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_end); 6206 6207 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay); 6208 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal); 6209 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start); 6210 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end); 6211 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start); 6212 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end); 6213 6214 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay); 6215 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal); 6216 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start); 6217 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end); 6218 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start); 6219 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end); 6220 6221 PIPE_CONF_CHECK_I(pixel_multiplier); 6222 6223 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6224 DRM_MODE_FLAG_INTERLACE); 6225 6226 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { 6227 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6228 DRM_MODE_FLAG_PHSYNC); 6229 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6230 DRM_MODE_FLAG_NHSYNC); 6231 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6232 DRM_MODE_FLAG_PVSYNC); 6233 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 6234 DRM_MODE_FLAG_NVSYNC); 6235 } 6236 6237 PIPE_CONF_CHECK_I(output_format); 6238 PIPE_CONF_CHECK_BOOL(has_hdmi_sink); 6239 if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || 6240 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 6241 PIPE_CONF_CHECK_BOOL(limited_color_range); 6242 6243 PIPE_CONF_CHECK_BOOL(hdmi_scrambling); 6244 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio); 6245 PIPE_CONF_CHECK_BOOL(has_infoframe); 6246 PIPE_CONF_CHECK_BOOL(fec_enable); 6247 6248 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio); 6249 6250 PIPE_CONF_CHECK_X(gmch_pfit.control); 6251 /* pfit ratios are autocomputed by the hw on gen4+ */ 6252 if (DISPLAY_VER(dev_priv) < 4) 6253 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); 6254 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); 6255 6256 /* 6257 * Changing the EDP transcoder input mux 6258 * (A_ONOFF vs. A_ON) requires a full modeset. 6259 */ 6260 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru); 6261 6262 if (!fastset) { 6263 PIPE_CONF_CHECK_I(pipe_src.x1); 6264 PIPE_CONF_CHECK_I(pipe_src.y1); 6265 PIPE_CONF_CHECK_I(pipe_src.x2); 6266 PIPE_CONF_CHECK_I(pipe_src.y2); 6267 6268 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled); 6269 if (current_config->pch_pfit.enabled) { 6270 PIPE_CONF_CHECK_I(pch_pfit.dst.x1); 6271 PIPE_CONF_CHECK_I(pch_pfit.dst.y1); 6272 PIPE_CONF_CHECK_I(pch_pfit.dst.x2); 6273 PIPE_CONF_CHECK_I(pch_pfit.dst.y2); 6274 } 6275 6276 PIPE_CONF_CHECK_I(scaler_state.scaler_id); 6277 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate); 6278 6279 PIPE_CONF_CHECK_X(gamma_mode); 6280 if (IS_CHERRYVIEW(dev_priv)) 6281 PIPE_CONF_CHECK_X(cgm_mode); 6282 else 6283 PIPE_CONF_CHECK_X(csc_mode); 6284 PIPE_CONF_CHECK_BOOL(gamma_enable); 6285 PIPE_CONF_CHECK_BOOL(csc_enable); 6286 6287 PIPE_CONF_CHECK_I(linetime); 6288 PIPE_CONF_CHECK_I(ips_linetime); 6289 6290 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config); 6291 if (bp_gamma) 6292 PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma); 6293 6294 if (current_config->active_planes) { 6295 PIPE_CONF_CHECK_BOOL(has_psr); 6296 PIPE_CONF_CHECK_BOOL(has_psr2); 6297 PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); 6298 PIPE_CONF_CHECK_I(dc3co_exitline); 6299 } 6300 } 6301 6302 PIPE_CONF_CHECK_BOOL(double_wide); 6303 6304 if (dev_priv->dpll.mgr) { 6305 PIPE_CONF_CHECK_P(shared_dpll); 6306 6307 PIPE_CONF_CHECK_X(dpll_hw_state.dpll); 6308 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); 6309 PIPE_CONF_CHECK_X(dpll_hw_state.fp0); 6310 PIPE_CONF_CHECK_X(dpll_hw_state.fp1); 6311 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); 6312 PIPE_CONF_CHECK_X(dpll_hw_state.spll); 6313 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); 6314 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); 6315 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); 6316 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); 6317 PIPE_CONF_CHECK_X(dpll_hw_state.div0); 6318 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); 6319 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); 6320 PIPE_CONF_CHECK_X(dpll_hw_state.pll0); 6321 PIPE_CONF_CHECK_X(dpll_hw_state.pll1); 6322 PIPE_CONF_CHECK_X(dpll_hw_state.pll2); 6323 PIPE_CONF_CHECK_X(dpll_hw_state.pll3); 6324 PIPE_CONF_CHECK_X(dpll_hw_state.pll6); 6325 PIPE_CONF_CHECK_X(dpll_hw_state.pll8); 6326 PIPE_CONF_CHECK_X(dpll_hw_state.pll9); 6327 PIPE_CONF_CHECK_X(dpll_hw_state.pll10); 6328 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); 6329 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl); 6330 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1); 6331 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl); 6332 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0); 6333 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1); 6334 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf); 6335 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock); 6336 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc); 6337 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias); 6338 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias); 6339 } 6340 6341 PIPE_CONF_CHECK_X(dsi_pll.ctrl); 6342 PIPE_CONF_CHECK_X(dsi_pll.div); 6343 6344 if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5) 6345 PIPE_CONF_CHECK_I(pipe_bpp); 6346 6347 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock); 6348 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock); 6349 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); 6350 6351 PIPE_CONF_CHECK_I(min_voltage_level); 6352 6353 if (current_config->has_psr || pipe_config->has_psr) 6354 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable, 6355 ~intel_hdmi_infoframe_enable(DP_SDP_VSC)); 6356 else 6357 PIPE_CONF_CHECK_X(infoframes.enable); 6358 6359 PIPE_CONF_CHECK_X(infoframes.gcp); 6360 PIPE_CONF_CHECK_INFOFRAME(avi); 6361 PIPE_CONF_CHECK_INFOFRAME(spd); 6362 PIPE_CONF_CHECK_INFOFRAME(hdmi); 6363 PIPE_CONF_CHECK_INFOFRAME(drm); 6364 PIPE_CONF_CHECK_DP_VSC_SDP(vsc); 6365 6366 PIPE_CONF_CHECK_X(sync_mode_slaves_mask); 6367 PIPE_CONF_CHECK_I(master_transcoder); 6368 PIPE_CONF_CHECK_X(bigjoiner_pipes); 6369 6370 PIPE_CONF_CHECK_I(dsc.compression_enable); 6371 PIPE_CONF_CHECK_I(dsc.dsc_split); 6372 PIPE_CONF_CHECK_I(dsc.compressed_bpp); 6373 6374 PIPE_CONF_CHECK_BOOL(splitter.enable); 6375 PIPE_CONF_CHECK_I(splitter.link_count); 6376 PIPE_CONF_CHECK_I(splitter.pixel_overlap); 6377 6378 PIPE_CONF_CHECK_I(mst_master_transcoder); 6379 6380 PIPE_CONF_CHECK_BOOL(vrr.enable); 6381 PIPE_CONF_CHECK_I(vrr.vmin); 6382 PIPE_CONF_CHECK_I(vrr.vmax); 6383 PIPE_CONF_CHECK_I(vrr.flipline); 6384 PIPE_CONF_CHECK_I(vrr.pipeline_full); 6385 PIPE_CONF_CHECK_I(vrr.guardband); 6386 6387 #undef PIPE_CONF_CHECK_X 6388 #undef PIPE_CONF_CHECK_I 6389 #undef PIPE_CONF_CHECK_BOOL 6390 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE 6391 #undef PIPE_CONF_CHECK_P 6392 #undef PIPE_CONF_CHECK_FLAGS 6393 #undef PIPE_CONF_CHECK_CLOCK_FUZZY 6394 #undef PIPE_CONF_CHECK_COLOR_LUT 6395 #undef PIPE_CONF_QUIRK 6396 6397 return ret; 6398 } 6399 6400 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, 6401 const struct intel_crtc_state *pipe_config) 6402 { 6403 if (pipe_config->has_pch_encoder) { 6404 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), 6405 &pipe_config->fdi_m_n); 6406 int dotclock = pipe_config->hw.adjusted_mode.crtc_clock; 6407 6408 /* 6409 * FDI already provided one idea for the dotclock. 6410 * Yell if the encoder disagrees. 6411 */ 6412 drm_WARN(&dev_priv->drm, 6413 !intel_fuzzy_clock_check(fdi_dotclock, dotclock), 6414 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", 6415 fdi_dotclock, dotclock); 6416 } 6417 } 6418 6419 static void verify_wm_state(struct intel_crtc *crtc, 6420 struct intel_crtc_state *new_crtc_state) 6421 { 6422 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6423 struct skl_hw_state { 6424 struct skl_ddb_entry ddb[I915_MAX_PLANES]; 6425 struct skl_ddb_entry ddb_y[I915_MAX_PLANES]; 6426 struct skl_pipe_wm wm; 6427 } *hw; 6428 const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal; 6429 int level, max_level = ilk_wm_max_level(dev_priv); 6430 struct intel_plane *plane; 6431 u8 hw_enabled_slices; 6432 6433 if (DISPLAY_VER(dev_priv) < 9 || !new_crtc_state->hw.active) 6434 return; 6435 6436 hw = kzalloc(sizeof(*hw), GFP_KERNEL); 6437 if (!hw) 6438 return; 6439 6440 skl_pipe_wm_get_hw_state(crtc, &hw->wm); 6441 6442 skl_pipe_ddb_get_hw_state(crtc, hw->ddb, hw->ddb_y); 6443 6444 hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv); 6445 6446 if (DISPLAY_VER(dev_priv) >= 11 && 6447 hw_enabled_slices != dev_priv->dbuf.enabled_slices) 6448 drm_err(&dev_priv->drm, 6449 "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n", 6450 dev_priv->dbuf.enabled_slices, 6451 hw_enabled_slices); 6452 6453 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 6454 const struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; 6455 const struct skl_wm_level *hw_wm_level, *sw_wm_level; 6456 6457 /* Watermarks */ 6458 for (level = 0; level <= max_level; level++) { 6459 hw_wm_level = &hw->wm.planes[plane->id].wm[level]; 6460 sw_wm_level = skl_plane_wm_level(sw_wm, plane->id, level); 6461 6462 if (skl_wm_level_equals(hw_wm_level, sw_wm_level)) 6463 continue; 6464 6465 drm_err(&dev_priv->drm, 6466 "[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 6467 plane->base.base.id, plane->base.name, level, 6468 sw_wm_level->enable, 6469 sw_wm_level->blocks, 6470 sw_wm_level->lines, 6471 hw_wm_level->enable, 6472 hw_wm_level->blocks, 6473 hw_wm_level->lines); 6474 } 6475 6476 hw_wm_level = &hw->wm.planes[plane->id].trans_wm; 6477 sw_wm_level = skl_plane_trans_wm(sw_wm, plane->id); 6478 6479 if (!skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 6480 drm_err(&dev_priv->drm, 6481 "[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 6482 plane->base.base.id, plane->base.name, 6483 sw_wm_level->enable, 6484 sw_wm_level->blocks, 6485 sw_wm_level->lines, 6486 hw_wm_level->enable, 6487 hw_wm_level->blocks, 6488 hw_wm_level->lines); 6489 } 6490 6491 hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0; 6492 sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0; 6493 6494 if (HAS_HW_SAGV_WM(dev_priv) && 6495 !skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 6496 drm_err(&dev_priv->drm, 6497 "[PLANE:%d:%s] mismatch in SAGV WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 6498 plane->base.base.id, plane->base.name, 6499 sw_wm_level->enable, 6500 sw_wm_level->blocks, 6501 sw_wm_level->lines, 6502 hw_wm_level->enable, 6503 hw_wm_level->blocks, 6504 hw_wm_level->lines); 6505 } 6506 6507 hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm; 6508 sw_wm_level = &sw_wm->planes[plane->id].sagv.trans_wm; 6509 6510 if (HAS_HW_SAGV_WM(dev_priv) && 6511 !skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 6512 drm_err(&dev_priv->drm, 6513 "[PLANE:%d:%s] mismatch in SAGV trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 6514 plane->base.base.id, plane->base.name, 6515 sw_wm_level->enable, 6516 sw_wm_level->blocks, 6517 sw_wm_level->lines, 6518 hw_wm_level->enable, 6519 hw_wm_level->blocks, 6520 hw_wm_level->lines); 6521 } 6522 6523 /* DDB */ 6524 hw_ddb_entry = &hw->ddb[PLANE_CURSOR]; 6525 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[PLANE_CURSOR]; 6526 6527 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { 6528 drm_err(&dev_priv->drm, 6529 "[PLANE:%d:%s] mismatch in DDB (expected (%u,%u), found (%u,%u))\n", 6530 plane->base.base.id, plane->base.name, 6531 sw_ddb_entry->start, sw_ddb_entry->end, 6532 hw_ddb_entry->start, hw_ddb_entry->end); 6533 } 6534 } 6535 6536 kfree(hw); 6537 } 6538 6539 static void 6540 verify_connector_state(struct intel_atomic_state *state, 6541 struct intel_crtc *crtc) 6542 { 6543 struct drm_connector *connector; 6544 struct drm_connector_state *new_conn_state; 6545 int i; 6546 6547 for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) { 6548 struct drm_encoder *encoder = connector->encoder; 6549 struct intel_crtc_state *crtc_state = NULL; 6550 6551 if (new_conn_state->crtc != &crtc->base) 6552 continue; 6553 6554 if (crtc) 6555 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6556 6557 intel_connector_verify_state(crtc_state, new_conn_state); 6558 6559 I915_STATE_WARN(new_conn_state->best_encoder != encoder, 6560 "connector's atomic encoder doesn't match legacy encoder\n"); 6561 } 6562 } 6563 6564 static void 6565 verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state) 6566 { 6567 struct intel_encoder *encoder; 6568 struct drm_connector *connector; 6569 struct drm_connector_state *old_conn_state, *new_conn_state; 6570 int i; 6571 6572 for_each_intel_encoder(&dev_priv->drm, encoder) { 6573 bool enabled = false, found = false; 6574 enum pipe pipe; 6575 6576 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n", 6577 encoder->base.base.id, 6578 encoder->base.name); 6579 6580 for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state, 6581 new_conn_state, i) { 6582 if (old_conn_state->best_encoder == &encoder->base) 6583 found = true; 6584 6585 if (new_conn_state->best_encoder != &encoder->base) 6586 continue; 6587 found = enabled = true; 6588 6589 I915_STATE_WARN(new_conn_state->crtc != 6590 encoder->base.crtc, 6591 "connector's crtc doesn't match encoder crtc\n"); 6592 } 6593 6594 if (!found) 6595 continue; 6596 6597 I915_STATE_WARN(!!encoder->base.crtc != enabled, 6598 "encoder's enabled state mismatch " 6599 "(expected %i, found %i)\n", 6600 !!encoder->base.crtc, enabled); 6601 6602 if (!encoder->base.crtc) { 6603 bool active; 6604 6605 active = encoder->get_hw_state(encoder, &pipe); 6606 I915_STATE_WARN(active, 6607 "encoder detached but still enabled on pipe %c.\n", 6608 pipe_name(pipe)); 6609 } 6610 } 6611 } 6612 6613 static void 6614 verify_crtc_state(struct intel_crtc *crtc, 6615 struct intel_crtc_state *old_crtc_state, 6616 struct intel_crtc_state *new_crtc_state) 6617 { 6618 struct drm_device *dev = crtc->base.dev; 6619 struct drm_i915_private *dev_priv = to_i915(dev); 6620 struct intel_encoder *encoder; 6621 struct intel_crtc_state *pipe_config = old_crtc_state; 6622 struct drm_atomic_state *state = old_crtc_state->uapi.state; 6623 struct intel_crtc *master_crtc; 6624 6625 __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi); 6626 intel_crtc_free_hw_state(old_crtc_state); 6627 intel_crtc_state_reset(old_crtc_state, crtc); 6628 old_crtc_state->uapi.state = state; 6629 6630 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id, 6631 crtc->base.name); 6632 6633 pipe_config->hw.enable = new_crtc_state->hw.enable; 6634 6635 intel_crtc_get_pipe_config(pipe_config); 6636 6637 /* we keep both pipes enabled on 830 */ 6638 if (IS_I830(dev_priv) && pipe_config->hw.active) 6639 pipe_config->hw.active = new_crtc_state->hw.active; 6640 6641 I915_STATE_WARN(new_crtc_state->hw.active != pipe_config->hw.active, 6642 "crtc active state doesn't match with hw state " 6643 "(expected %i, found %i)\n", 6644 new_crtc_state->hw.active, pipe_config->hw.active); 6645 6646 I915_STATE_WARN(crtc->active != new_crtc_state->hw.active, 6647 "transitional active state does not match atomic hw state " 6648 "(expected %i, found %i)\n", 6649 new_crtc_state->hw.active, crtc->active); 6650 6651 master_crtc = intel_master_crtc(new_crtc_state); 6652 6653 for_each_encoder_on_crtc(dev, &master_crtc->base, encoder) { 6654 enum pipe pipe; 6655 bool active; 6656 6657 active = encoder->get_hw_state(encoder, &pipe); 6658 I915_STATE_WARN(active != new_crtc_state->hw.active, 6659 "[ENCODER:%i] active %i with crtc active %i\n", 6660 encoder->base.base.id, active, 6661 new_crtc_state->hw.active); 6662 6663 I915_STATE_WARN(active && master_crtc->pipe != pipe, 6664 "Encoder connected to wrong pipe %c\n", 6665 pipe_name(pipe)); 6666 6667 if (active) 6668 intel_encoder_get_config(encoder, pipe_config); 6669 } 6670 6671 if (!new_crtc_state->hw.active) 6672 return; 6673 6674 intel_pipe_config_sanity_check(dev_priv, pipe_config); 6675 6676 if (!intel_pipe_config_compare(new_crtc_state, 6677 pipe_config, false)) { 6678 I915_STATE_WARN(1, "pipe state doesn't match!\n"); 6679 intel_dump_pipe_config(pipe_config, NULL, "[hw state]"); 6680 intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]"); 6681 } 6682 } 6683 6684 static void 6685 intel_verify_planes(struct intel_atomic_state *state) 6686 { 6687 struct intel_plane *plane; 6688 const struct intel_plane_state *plane_state; 6689 int i; 6690 6691 for_each_new_intel_plane_in_state(state, plane, 6692 plane_state, i) 6693 assert_plane(plane, plane_state->planar_slave || 6694 plane_state->uapi.visible); 6695 } 6696 6697 static void 6698 verify_single_dpll_state(struct drm_i915_private *dev_priv, 6699 struct intel_shared_dpll *pll, 6700 struct intel_crtc *crtc, 6701 struct intel_crtc_state *new_crtc_state) 6702 { 6703 struct intel_dpll_hw_state dpll_hw_state; 6704 u8 pipe_mask; 6705 bool active; 6706 6707 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); 6708 6709 drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name); 6710 6711 active = intel_dpll_get_hw_state(dev_priv, pll, &dpll_hw_state); 6712 6713 if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) { 6714 I915_STATE_WARN(!pll->on && pll->active_mask, 6715 "pll in active use but not on in sw tracking\n"); 6716 I915_STATE_WARN(pll->on && !pll->active_mask, 6717 "pll is on but not used by any active pipe\n"); 6718 I915_STATE_WARN(pll->on != active, 6719 "pll on state mismatch (expected %i, found %i)\n", 6720 pll->on, active); 6721 } 6722 6723 if (!crtc) { 6724 I915_STATE_WARN(pll->active_mask & ~pll->state.pipe_mask, 6725 "more active pll users than references: 0x%x vs 0x%x\n", 6726 pll->active_mask, pll->state.pipe_mask); 6727 6728 return; 6729 } 6730 6731 pipe_mask = BIT(crtc->pipe); 6732 6733 if (new_crtc_state->hw.active) 6734 I915_STATE_WARN(!(pll->active_mask & pipe_mask), 6735 "pll active mismatch (expected pipe %c in active mask 0x%x)\n", 6736 pipe_name(crtc->pipe), pll->active_mask); 6737 else 6738 I915_STATE_WARN(pll->active_mask & pipe_mask, 6739 "pll active mismatch (didn't expect pipe %c in active mask 0x%x)\n", 6740 pipe_name(crtc->pipe), pll->active_mask); 6741 6742 I915_STATE_WARN(!(pll->state.pipe_mask & pipe_mask), 6743 "pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n", 6744 pipe_mask, pll->state.pipe_mask); 6745 6746 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state, 6747 &dpll_hw_state, 6748 sizeof(dpll_hw_state)), 6749 "pll hw state mismatch\n"); 6750 } 6751 6752 static void 6753 verify_shared_dpll_state(struct intel_crtc *crtc, 6754 struct intel_crtc_state *old_crtc_state, 6755 struct intel_crtc_state *new_crtc_state) 6756 { 6757 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6758 6759 if (new_crtc_state->shared_dpll) 6760 verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state); 6761 6762 if (old_crtc_state->shared_dpll && 6763 old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) { 6764 u8 pipe_mask = BIT(crtc->pipe); 6765 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll; 6766 6767 I915_STATE_WARN(pll->active_mask & pipe_mask, 6768 "pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n", 6769 pipe_name(crtc->pipe), pll->active_mask); 6770 I915_STATE_WARN(pll->state.pipe_mask & pipe_mask, 6771 "pll enabled crtcs mismatch (found %x in enabled mask (0x%x))\n", 6772 pipe_name(crtc->pipe), pll->state.pipe_mask); 6773 } 6774 } 6775 6776 static void 6777 verify_mpllb_state(struct intel_atomic_state *state, 6778 struct intel_crtc_state *new_crtc_state) 6779 { 6780 struct drm_i915_private *i915 = to_i915(state->base.dev); 6781 struct intel_mpllb_state mpllb_hw_state = { 0 }; 6782 struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->mpllb_state; 6783 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 6784 struct intel_encoder *encoder; 6785 6786 if (!IS_DG2(i915)) 6787 return; 6788 6789 if (!new_crtc_state->hw.active) 6790 return; 6791 6792 encoder = intel_get_crtc_new_encoder(state, new_crtc_state); 6793 intel_mpllb_readout_hw_state(encoder, &mpllb_hw_state); 6794 6795 #define MPLLB_CHECK(name) do { \ 6796 if (mpllb_sw_state->name != mpllb_hw_state.name) { \ 6797 pipe_config_mismatch(false, crtc, "MPLLB:" __stringify(name), \ 6798 "(expected 0x%08x, found 0x%08x)", \ 6799 mpllb_sw_state->name, \ 6800 mpllb_hw_state.name); \ 6801 } \ 6802 } while (0) 6803 6804 MPLLB_CHECK(mpllb_cp); 6805 MPLLB_CHECK(mpllb_div); 6806 MPLLB_CHECK(mpllb_div2); 6807 MPLLB_CHECK(mpllb_fracn1); 6808 MPLLB_CHECK(mpllb_fracn2); 6809 MPLLB_CHECK(mpllb_sscen); 6810 MPLLB_CHECK(mpllb_sscstep); 6811 6812 /* 6813 * ref_control is handled by the hardware/firemware and never 6814 * programmed by the software, but the proper values are supplied 6815 * in the bspec for verification purposes. 6816 */ 6817 MPLLB_CHECK(ref_control); 6818 6819 #undef MPLLB_CHECK 6820 } 6821 6822 static void 6823 intel_modeset_verify_crtc(struct intel_crtc *crtc, 6824 struct intel_atomic_state *state, 6825 struct intel_crtc_state *old_crtc_state, 6826 struct intel_crtc_state *new_crtc_state) 6827 { 6828 if (!intel_crtc_needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe) 6829 return; 6830 6831 verify_wm_state(crtc, new_crtc_state); 6832 verify_connector_state(state, crtc); 6833 verify_crtc_state(crtc, old_crtc_state, new_crtc_state); 6834 verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state); 6835 verify_mpllb_state(state, new_crtc_state); 6836 } 6837 6838 static void 6839 verify_disabled_dpll_state(struct drm_i915_private *dev_priv) 6840 { 6841 int i; 6842 6843 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) 6844 verify_single_dpll_state(dev_priv, 6845 &dev_priv->dpll.shared_dplls[i], 6846 NULL, NULL); 6847 } 6848 6849 static void 6850 intel_modeset_verify_disabled(struct drm_i915_private *dev_priv, 6851 struct intel_atomic_state *state) 6852 { 6853 verify_encoder_state(dev_priv, state); 6854 verify_connector_state(state, NULL); 6855 verify_disabled_dpll_state(dev_priv); 6856 } 6857 6858 int intel_modeset_all_pipes(struct intel_atomic_state *state) 6859 { 6860 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6861 struct intel_crtc *crtc; 6862 6863 /* 6864 * Add all pipes to the state, and force 6865 * a modeset on all the active ones. 6866 */ 6867 for_each_intel_crtc(&dev_priv->drm, crtc) { 6868 struct intel_crtc_state *crtc_state; 6869 int ret; 6870 6871 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6872 if (IS_ERR(crtc_state)) 6873 return PTR_ERR(crtc_state); 6874 6875 if (!crtc_state->hw.active || 6876 drm_atomic_crtc_needs_modeset(&crtc_state->uapi)) 6877 continue; 6878 6879 crtc_state->uapi.mode_changed = true; 6880 6881 ret = drm_atomic_add_affected_connectors(&state->base, 6882 &crtc->base); 6883 if (ret) 6884 return ret; 6885 6886 ret = intel_atomic_add_affected_planes(state, crtc); 6887 if (ret) 6888 return ret; 6889 6890 crtc_state->update_planes |= crtc_state->active_planes; 6891 } 6892 6893 return 0; 6894 } 6895 6896 static void 6897 intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state) 6898 { 6899 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 6900 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6901 struct drm_display_mode adjusted_mode = 6902 crtc_state->hw.adjusted_mode; 6903 6904 if (crtc_state->vrr.enable) { 6905 adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax; 6906 adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax; 6907 adjusted_mode.crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state); 6908 crtc->vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state); 6909 } 6910 6911 drm_calc_timestamping_constants(&crtc->base, &adjusted_mode); 6912 6913 crtc->mode_flags = crtc_state->mode_flags; 6914 6915 /* 6916 * The scanline counter increments at the leading edge of hsync. 6917 * 6918 * On most platforms it starts counting from vtotal-1 on the 6919 * first active line. That means the scanline counter value is 6920 * always one less than what we would expect. Ie. just after 6921 * start of vblank, which also occurs at start of hsync (on the 6922 * last active line), the scanline counter will read vblank_start-1. 6923 * 6924 * On gen2 the scanline counter starts counting from 1 instead 6925 * of vtotal-1, so we have to subtract one (or rather add vtotal-1 6926 * to keep the value positive), instead of adding one. 6927 * 6928 * On HSW+ the behaviour of the scanline counter depends on the output 6929 * type. For DP ports it behaves like most other platforms, but on HDMI 6930 * there's an extra 1 line difference. So we need to add two instead of 6931 * one to the value. 6932 * 6933 * On VLV/CHV DSI the scanline counter would appear to increment 6934 * approx. 1/3 of a scanline before start of vblank. Unfortunately 6935 * that means we can't tell whether we're in vblank or not while 6936 * we're on that particular line. We must still set scanline_offset 6937 * to 1 so that the vblank timestamps come out correct when we query 6938 * the scanline counter from within the vblank interrupt handler. 6939 * However if queried just before the start of vblank we'll get an 6940 * answer that's slightly in the future. 6941 */ 6942 if (DISPLAY_VER(dev_priv) == 2) { 6943 int vtotal; 6944 6945 vtotal = adjusted_mode.crtc_vtotal; 6946 if (adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 6947 vtotal /= 2; 6948 6949 crtc->scanline_offset = vtotal - 1; 6950 } else if (HAS_DDI(dev_priv) && 6951 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 6952 crtc->scanline_offset = 2; 6953 } else { 6954 crtc->scanline_offset = 1; 6955 } 6956 } 6957 6958 static void intel_modeset_clear_plls(struct intel_atomic_state *state) 6959 { 6960 struct intel_crtc_state *new_crtc_state; 6961 struct intel_crtc *crtc; 6962 int i; 6963 6964 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6965 if (!intel_crtc_needs_modeset(new_crtc_state)) 6966 continue; 6967 6968 intel_release_shared_dplls(state, crtc); 6969 } 6970 } 6971 6972 /* 6973 * This implements the workaround described in the "notes" section of the mode 6974 * set sequence documentation. When going from no pipes or single pipe to 6975 * multiple pipes, and planes are enabled after the pipe, we need to wait at 6976 * least 2 vblanks on the first pipe before enabling planes on the second pipe. 6977 */ 6978 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state) 6979 { 6980 struct intel_crtc_state *crtc_state; 6981 struct intel_crtc *crtc; 6982 struct intel_crtc_state *first_crtc_state = NULL; 6983 struct intel_crtc_state *other_crtc_state = NULL; 6984 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; 6985 int i; 6986 6987 /* look at all crtc's that are going to be enabled in during modeset */ 6988 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6989 if (!crtc_state->hw.active || 6990 !intel_crtc_needs_modeset(crtc_state)) 6991 continue; 6992 6993 if (first_crtc_state) { 6994 other_crtc_state = crtc_state; 6995 break; 6996 } else { 6997 first_crtc_state = crtc_state; 6998 first_pipe = crtc->pipe; 6999 } 7000 } 7001 7002 /* No workaround needed? */ 7003 if (!first_crtc_state) 7004 return 0; 7005 7006 /* w/a possibly needed, check how many crtc's are already enabled. */ 7007 for_each_intel_crtc(state->base.dev, crtc) { 7008 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 7009 if (IS_ERR(crtc_state)) 7010 return PTR_ERR(crtc_state); 7011 7012 crtc_state->hsw_workaround_pipe = INVALID_PIPE; 7013 7014 if (!crtc_state->hw.active || 7015 intel_crtc_needs_modeset(crtc_state)) 7016 continue; 7017 7018 /* 2 or more enabled crtcs means no need for w/a */ 7019 if (enabled_pipe != INVALID_PIPE) 7020 return 0; 7021 7022 enabled_pipe = crtc->pipe; 7023 } 7024 7025 if (enabled_pipe != INVALID_PIPE) 7026 first_crtc_state->hsw_workaround_pipe = enabled_pipe; 7027 else if (other_crtc_state) 7028 other_crtc_state->hsw_workaround_pipe = first_pipe; 7029 7030 return 0; 7031 } 7032 7033 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 7034 u8 active_pipes) 7035 { 7036 const struct intel_crtc_state *crtc_state; 7037 struct intel_crtc *crtc; 7038 int i; 7039 7040 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7041 if (crtc_state->hw.active) 7042 active_pipes |= BIT(crtc->pipe); 7043 else 7044 active_pipes &= ~BIT(crtc->pipe); 7045 } 7046 7047 return active_pipes; 7048 } 7049 7050 static int intel_modeset_checks(struct intel_atomic_state *state) 7051 { 7052 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7053 7054 state->modeset = true; 7055 7056 if (IS_HASWELL(dev_priv)) 7057 return hsw_mode_set_planes_workaround(state); 7058 7059 return 0; 7060 } 7061 7062 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state, 7063 struct intel_crtc_state *new_crtc_state) 7064 { 7065 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) 7066 return; 7067 7068 new_crtc_state->uapi.mode_changed = false; 7069 new_crtc_state->update_pipe = true; 7070 } 7071 7072 static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state, 7073 struct intel_crtc_state *new_crtc_state) 7074 { 7075 /* 7076 * If we're not doing the full modeset we want to 7077 * keep the current M/N values as they may be 7078 * sufficiently different to the computed values 7079 * to cause problems. 7080 * 7081 * FIXME: should really copy more fuzzy state here 7082 */ 7083 new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n; 7084 new_crtc_state->dp_m_n = old_crtc_state->dp_m_n; 7085 new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2; 7086 new_crtc_state->has_drrs = old_crtc_state->has_drrs; 7087 } 7088 7089 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state, 7090 struct intel_crtc *crtc, 7091 u8 plane_ids_mask) 7092 { 7093 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7094 struct intel_plane *plane; 7095 7096 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 7097 struct intel_plane_state *plane_state; 7098 7099 if ((plane_ids_mask & BIT(plane->id)) == 0) 7100 continue; 7101 7102 plane_state = intel_atomic_get_plane_state(state, plane); 7103 if (IS_ERR(plane_state)) 7104 return PTR_ERR(plane_state); 7105 } 7106 7107 return 0; 7108 } 7109 7110 int intel_atomic_add_affected_planes(struct intel_atomic_state *state, 7111 struct intel_crtc *crtc) 7112 { 7113 const struct intel_crtc_state *old_crtc_state = 7114 intel_atomic_get_old_crtc_state(state, crtc); 7115 const struct intel_crtc_state *new_crtc_state = 7116 intel_atomic_get_new_crtc_state(state, crtc); 7117 7118 return intel_crtc_add_planes_to_state(state, crtc, 7119 old_crtc_state->enabled_planes | 7120 new_crtc_state->enabled_planes); 7121 } 7122 7123 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv) 7124 { 7125 /* See {hsw,vlv,ivb}_plane_ratio() */ 7126 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) || 7127 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) || 7128 IS_IVYBRIDGE(dev_priv); 7129 } 7130 7131 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state, 7132 struct intel_crtc *crtc, 7133 struct intel_crtc *other) 7134 { 7135 const struct intel_plane_state *plane_state; 7136 struct intel_plane *plane; 7137 u8 plane_ids = 0; 7138 int i; 7139 7140 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 7141 if (plane->pipe == crtc->pipe) 7142 plane_ids |= BIT(plane->id); 7143 } 7144 7145 return intel_crtc_add_planes_to_state(state, other, plane_ids); 7146 } 7147 7148 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state) 7149 { 7150 struct drm_i915_private *i915 = to_i915(state->base.dev); 7151 const struct intel_crtc_state *crtc_state; 7152 struct intel_crtc *crtc; 7153 int i; 7154 7155 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7156 struct intel_crtc *other; 7157 7158 for_each_intel_crtc_in_pipe_mask(&i915->drm, other, 7159 crtc_state->bigjoiner_pipes) { 7160 int ret; 7161 7162 if (crtc == other) 7163 continue; 7164 7165 ret = intel_crtc_add_bigjoiner_planes(state, crtc, other); 7166 if (ret) 7167 return ret; 7168 } 7169 } 7170 7171 return 0; 7172 } 7173 7174 static int intel_atomic_check_planes(struct intel_atomic_state *state) 7175 { 7176 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7177 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7178 struct intel_plane_state *plane_state; 7179 struct intel_plane *plane; 7180 struct intel_crtc *crtc; 7181 int i, ret; 7182 7183 ret = icl_add_linked_planes(state); 7184 if (ret) 7185 return ret; 7186 7187 ret = intel_bigjoiner_add_affected_planes(state); 7188 if (ret) 7189 return ret; 7190 7191 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 7192 ret = intel_plane_atomic_check(state, plane); 7193 if (ret) { 7194 drm_dbg_atomic(&dev_priv->drm, 7195 "[PLANE:%d:%s] atomic driver check failed\n", 7196 plane->base.base.id, plane->base.name); 7197 return ret; 7198 } 7199 } 7200 7201 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7202 new_crtc_state, i) { 7203 u8 old_active_planes, new_active_planes; 7204 7205 ret = icl_check_nv12_planes(new_crtc_state); 7206 if (ret) 7207 return ret; 7208 7209 /* 7210 * On some platforms the number of active planes affects 7211 * the planes' minimum cdclk calculation. Add such planes 7212 * to the state before we compute the minimum cdclk. 7213 */ 7214 if (!active_planes_affects_min_cdclk(dev_priv)) 7215 continue; 7216 7217 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 7218 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 7219 7220 if (hweight8(old_active_planes) == hweight8(new_active_planes)) 7221 continue; 7222 7223 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes); 7224 if (ret) 7225 return ret; 7226 } 7227 7228 return 0; 7229 } 7230 7231 static int intel_atomic_check_crtcs(struct intel_atomic_state *state) 7232 { 7233 struct intel_crtc_state *crtc_state; 7234 struct intel_crtc *crtc; 7235 int i; 7236 7237 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7238 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 7239 int ret; 7240 7241 ret = intel_crtc_atomic_check(state, crtc); 7242 if (ret) { 7243 drm_dbg_atomic(&i915->drm, 7244 "[CRTC:%d:%s] atomic driver check failed\n", 7245 crtc->base.base.id, crtc->base.name); 7246 return ret; 7247 } 7248 } 7249 7250 return 0; 7251 } 7252 7253 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, 7254 u8 transcoders) 7255 { 7256 const struct intel_crtc_state *new_crtc_state; 7257 struct intel_crtc *crtc; 7258 int i; 7259 7260 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7261 if (new_crtc_state->hw.enable && 7262 transcoders & BIT(new_crtc_state->cpu_transcoder) && 7263 intel_crtc_needs_modeset(new_crtc_state)) 7264 return true; 7265 } 7266 7267 return false; 7268 } 7269 7270 static bool intel_pipes_need_modeset(struct intel_atomic_state *state, 7271 u8 pipes) 7272 { 7273 const struct intel_crtc_state *new_crtc_state; 7274 struct intel_crtc *crtc; 7275 int i; 7276 7277 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7278 if (new_crtc_state->hw.enable && 7279 pipes & BIT(crtc->pipe) && 7280 intel_crtc_needs_modeset(new_crtc_state)) 7281 return true; 7282 } 7283 7284 return false; 7285 } 7286 7287 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state, 7288 struct intel_crtc *master_crtc) 7289 { 7290 struct drm_i915_private *i915 = to_i915(state->base.dev); 7291 struct intel_crtc_state *master_crtc_state = 7292 intel_atomic_get_new_crtc_state(state, master_crtc); 7293 struct intel_crtc *slave_crtc; 7294 7295 if (!master_crtc_state->bigjoiner_pipes) 7296 return 0; 7297 7298 /* sanity check */ 7299 if (drm_WARN_ON(&i915->drm, 7300 master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state))) 7301 return -EINVAL; 7302 7303 if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) { 7304 drm_dbg_kms(&i915->drm, 7305 "[CRTC:%d:%s] Cannot act as big joiner master " 7306 "(need 0x%x as pipes, only 0x%x possible)\n", 7307 master_crtc->base.base.id, master_crtc->base.name, 7308 master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915)); 7309 return -EINVAL; 7310 } 7311 7312 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 7313 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 7314 struct intel_crtc_state *slave_crtc_state; 7315 int ret; 7316 7317 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc); 7318 if (IS_ERR(slave_crtc_state)) 7319 return PTR_ERR(slave_crtc_state); 7320 7321 /* master being enabled, slave was already configured? */ 7322 if (slave_crtc_state->uapi.enable) { 7323 drm_dbg_kms(&i915->drm, 7324 "[CRTC:%d:%s] Slave is enabled as normal CRTC, but " 7325 "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n", 7326 slave_crtc->base.base.id, slave_crtc->base.name, 7327 master_crtc->base.base.id, master_crtc->base.name); 7328 return -EINVAL; 7329 } 7330 7331 /* 7332 * The state copy logic assumes the master crtc gets processed 7333 * before the slave crtc during the main compute_config loop. 7334 * This works because the crtcs are created in pipe order, 7335 * and the hardware requires master pipe < slave pipe as well. 7336 * Should that change we need to rethink the logic. 7337 */ 7338 if (WARN_ON(drm_crtc_index(&master_crtc->base) > 7339 drm_crtc_index(&slave_crtc->base))) 7340 return -EINVAL; 7341 7342 drm_dbg_kms(&i915->drm, 7343 "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n", 7344 slave_crtc->base.base.id, slave_crtc->base.name, 7345 master_crtc->base.base.id, master_crtc->base.name); 7346 7347 slave_crtc_state->bigjoiner_pipes = 7348 master_crtc_state->bigjoiner_pipes; 7349 7350 ret = copy_bigjoiner_crtc_state_modeset(state, slave_crtc); 7351 if (ret) 7352 return ret; 7353 } 7354 7355 return 0; 7356 } 7357 7358 static void kill_bigjoiner_slave(struct intel_atomic_state *state, 7359 struct intel_crtc *master_crtc) 7360 { 7361 struct drm_i915_private *i915 = to_i915(state->base.dev); 7362 struct intel_crtc_state *master_crtc_state = 7363 intel_atomic_get_new_crtc_state(state, master_crtc); 7364 struct intel_crtc *slave_crtc; 7365 7366 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 7367 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 7368 struct intel_crtc_state *slave_crtc_state = 7369 intel_atomic_get_new_crtc_state(state, slave_crtc); 7370 7371 slave_crtc_state->bigjoiner_pipes = 0; 7372 7373 intel_crtc_copy_uapi_to_hw_state_modeset(state, slave_crtc); 7374 } 7375 7376 master_crtc_state->bigjoiner_pipes = 0; 7377 } 7378 7379 /** 7380 * DOC: asynchronous flip implementation 7381 * 7382 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC 7383 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL. 7384 * Correspondingly, support is currently added for primary plane only. 7385 * 7386 * Async flip can only change the plane surface address, so anything else 7387 * changing is rejected from the intel_async_flip_check_hw() function. 7388 * Once this check is cleared, flip done interrupt is enabled using 7389 * the intel_crtc_enable_flip_done() function. 7390 * 7391 * As soon as the surface address register is written, flip done interrupt is 7392 * generated and the requested events are sent to the usersapce in the interrupt 7393 * handler itself. The timestamp and sequence sent during the flip done event 7394 * correspond to the last vblank and have no relation to the actual time when 7395 * the flip done event was sent. 7396 */ 7397 static int intel_async_flip_check_uapi(struct intel_atomic_state *state, 7398 struct intel_crtc *crtc) 7399 { 7400 struct drm_i915_private *i915 = to_i915(state->base.dev); 7401 const struct intel_crtc_state *new_crtc_state = 7402 intel_atomic_get_new_crtc_state(state, crtc); 7403 const struct intel_plane_state *old_plane_state; 7404 struct intel_plane_state *new_plane_state; 7405 struct intel_plane *plane; 7406 int i; 7407 7408 if (!new_crtc_state->uapi.async_flip) 7409 return 0; 7410 7411 if (!new_crtc_state->uapi.active) { 7412 drm_dbg_kms(&i915->drm, 7413 "[CRTC:%d:%s] not active\n", 7414 crtc->base.base.id, crtc->base.name); 7415 return -EINVAL; 7416 } 7417 7418 if (intel_crtc_needs_modeset(new_crtc_state)) { 7419 drm_dbg_kms(&i915->drm, 7420 "[CRTC:%d:%s] modeset required\n", 7421 crtc->base.base.id, crtc->base.name); 7422 return -EINVAL; 7423 } 7424 7425 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 7426 new_plane_state, i) { 7427 if (plane->pipe != crtc->pipe) 7428 continue; 7429 7430 /* 7431 * TODO: Async flip is only supported through the page flip IOCTL 7432 * as of now. So support currently added for primary plane only. 7433 * Support for other planes on platforms on which supports 7434 * this(vlv/chv and icl+) should be added when async flip is 7435 * enabled in the atomic IOCTL path. 7436 */ 7437 if (!plane->async_flip) { 7438 drm_dbg_kms(&i915->drm, 7439 "[PLANE:%d:%s] async flip not supported\n", 7440 plane->base.base.id, plane->base.name); 7441 return -EINVAL; 7442 } 7443 7444 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) { 7445 drm_dbg_kms(&i915->drm, 7446 "[PLANE:%d:%s] no old or new framebuffer\n", 7447 plane->base.base.id, plane->base.name); 7448 return -EINVAL; 7449 } 7450 } 7451 7452 return 0; 7453 } 7454 7455 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc) 7456 { 7457 struct drm_i915_private *i915 = to_i915(state->base.dev); 7458 const struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7459 const struct intel_plane_state *new_plane_state, *old_plane_state; 7460 struct intel_plane *plane; 7461 int i; 7462 7463 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 7464 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 7465 7466 if (!new_crtc_state->uapi.async_flip) 7467 return 0; 7468 7469 if (!new_crtc_state->hw.active) { 7470 drm_dbg_kms(&i915->drm, 7471 "[CRTC:%d:%s] not active\n", 7472 crtc->base.base.id, crtc->base.name); 7473 return -EINVAL; 7474 } 7475 7476 if (intel_crtc_needs_modeset(new_crtc_state)) { 7477 drm_dbg_kms(&i915->drm, 7478 "[CRTC:%d:%s] modeset required\n", 7479 crtc->base.base.id, crtc->base.name); 7480 return -EINVAL; 7481 } 7482 7483 if (old_crtc_state->active_planes != new_crtc_state->active_planes) { 7484 drm_dbg_kms(&i915->drm, 7485 "[CRTC:%d:%s] Active planes cannot be in async flip\n", 7486 crtc->base.base.id, crtc->base.name); 7487 return -EINVAL; 7488 } 7489 7490 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 7491 new_plane_state, i) { 7492 if (plane->pipe != crtc->pipe) 7493 continue; 7494 7495 /* 7496 * Only async flip capable planes should be in the state 7497 * if we're really about to ask the hardware to perform 7498 * an async flip. We should never get this far otherwise. 7499 */ 7500 if (drm_WARN_ON(&i915->drm, 7501 new_crtc_state->do_async_flip && !plane->async_flip)) 7502 return -EINVAL; 7503 7504 /* 7505 * Only check async flip capable planes other planes 7506 * may be involved in the initial commit due to 7507 * the wm0/ddb optimization. 7508 * 7509 * TODO maybe should track which planes actually 7510 * were requested to do the async flip... 7511 */ 7512 if (!plane->async_flip) 7513 continue; 7514 7515 /* 7516 * FIXME: This check is kept generic for all platforms. 7517 * Need to verify this for all gen9 platforms to enable 7518 * this selectively if required. 7519 */ 7520 switch (new_plane_state->hw.fb->modifier) { 7521 case I915_FORMAT_MOD_X_TILED: 7522 case I915_FORMAT_MOD_Y_TILED: 7523 case I915_FORMAT_MOD_Yf_TILED: 7524 case I915_FORMAT_MOD_4_TILED: 7525 break; 7526 default: 7527 drm_dbg_kms(&i915->drm, 7528 "[PLANE:%d:%s] Modifier does not support async flips\n", 7529 plane->base.base.id, plane->base.name); 7530 return -EINVAL; 7531 } 7532 7533 if (new_plane_state->hw.fb->format->num_planes > 1) { 7534 drm_dbg_kms(&i915->drm, 7535 "[PLANE:%d:%s] Planar formats do not support async flips\n", 7536 plane->base.base.id, plane->base.name); 7537 return -EINVAL; 7538 } 7539 7540 if (old_plane_state->view.color_plane[0].mapping_stride != 7541 new_plane_state->view.color_plane[0].mapping_stride) { 7542 drm_dbg_kms(&i915->drm, 7543 "[PLANE:%d:%s] Stride cannot be changed in async flip\n", 7544 plane->base.base.id, plane->base.name); 7545 return -EINVAL; 7546 } 7547 7548 if (old_plane_state->hw.fb->modifier != 7549 new_plane_state->hw.fb->modifier) { 7550 drm_dbg_kms(&i915->drm, 7551 "[PLANE:%d:%s] Modifier cannot be changed in async flip\n", 7552 plane->base.base.id, plane->base.name); 7553 return -EINVAL; 7554 } 7555 7556 if (old_plane_state->hw.fb->format != 7557 new_plane_state->hw.fb->format) { 7558 drm_dbg_kms(&i915->drm, 7559 "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n", 7560 plane->base.base.id, plane->base.name); 7561 return -EINVAL; 7562 } 7563 7564 if (old_plane_state->hw.rotation != 7565 new_plane_state->hw.rotation) { 7566 drm_dbg_kms(&i915->drm, 7567 "[PLANE:%d:%s] Rotation cannot be changed in async flip\n", 7568 plane->base.base.id, plane->base.name); 7569 return -EINVAL; 7570 } 7571 7572 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) || 7573 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) { 7574 drm_dbg_kms(&i915->drm, 7575 "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n", 7576 plane->base.base.id, plane->base.name); 7577 return -EINVAL; 7578 } 7579 7580 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) { 7581 drm_dbg_kms(&i915->drm, 7582 "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n", 7583 plane->base.base.id, plane->base.name); 7584 return -EINVAL; 7585 } 7586 7587 if (old_plane_state->hw.pixel_blend_mode != 7588 new_plane_state->hw.pixel_blend_mode) { 7589 drm_dbg_kms(&i915->drm, 7590 "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n", 7591 plane->base.base.id, plane->base.name); 7592 return -EINVAL; 7593 } 7594 7595 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) { 7596 drm_dbg_kms(&i915->drm, 7597 "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n", 7598 plane->base.base.id, plane->base.name); 7599 return -EINVAL; 7600 } 7601 7602 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) { 7603 drm_dbg_kms(&i915->drm, 7604 "[PLANE:%d:%s] Color range cannot be changed in async flip\n", 7605 plane->base.base.id, plane->base.name); 7606 return -EINVAL; 7607 } 7608 7609 /* plane decryption is allow to change only in synchronous flips */ 7610 if (old_plane_state->decrypt != new_plane_state->decrypt) { 7611 drm_dbg_kms(&i915->drm, 7612 "[PLANE:%d:%s] Decryption cannot be changed in async flip\n", 7613 plane->base.base.id, plane->base.name); 7614 return -EINVAL; 7615 } 7616 } 7617 7618 return 0; 7619 } 7620 7621 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state) 7622 { 7623 struct drm_i915_private *i915 = to_i915(state->base.dev); 7624 struct intel_crtc_state *crtc_state; 7625 struct intel_crtc *crtc; 7626 u8 affected_pipes = 0; 7627 u8 modeset_pipes = 0; 7628 int i; 7629 7630 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7631 affected_pipes |= crtc_state->bigjoiner_pipes; 7632 if (intel_crtc_needs_modeset(crtc_state)) 7633 modeset_pipes |= crtc_state->bigjoiner_pipes; 7634 } 7635 7636 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) { 7637 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 7638 if (IS_ERR(crtc_state)) 7639 return PTR_ERR(crtc_state); 7640 } 7641 7642 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) { 7643 int ret; 7644 7645 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 7646 7647 crtc_state->uapi.mode_changed = true; 7648 7649 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); 7650 if (ret) 7651 return ret; 7652 7653 ret = intel_atomic_add_affected_planes(state, crtc); 7654 if (ret) 7655 return ret; 7656 } 7657 7658 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7659 /* Kill old bigjoiner link, we may re-establish afterwards */ 7660 if (intel_crtc_needs_modeset(crtc_state) && 7661 intel_crtc_is_bigjoiner_master(crtc_state)) 7662 kill_bigjoiner_slave(state, crtc); 7663 } 7664 7665 return 0; 7666 } 7667 7668 /** 7669 * intel_atomic_check - validate state object 7670 * @dev: drm device 7671 * @_state: state to validate 7672 */ 7673 static int intel_atomic_check(struct drm_device *dev, 7674 struct drm_atomic_state *_state) 7675 { 7676 struct drm_i915_private *dev_priv = to_i915(dev); 7677 struct intel_atomic_state *state = to_intel_atomic_state(_state); 7678 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7679 struct intel_crtc *crtc; 7680 int ret, i; 7681 bool any_ms = false; 7682 7683 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7684 new_crtc_state, i) { 7685 if (new_crtc_state->inherited != old_crtc_state->inherited) 7686 new_crtc_state->uapi.mode_changed = true; 7687 7688 if (new_crtc_state->uapi.scaling_filter != 7689 old_crtc_state->uapi.scaling_filter) 7690 new_crtc_state->uapi.mode_changed = true; 7691 } 7692 7693 intel_vrr_check_modeset(state); 7694 7695 ret = drm_atomic_helper_check_modeset(dev, &state->base); 7696 if (ret) 7697 goto fail; 7698 7699 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7700 ret = intel_async_flip_check_uapi(state, crtc); 7701 if (ret) 7702 return ret; 7703 } 7704 7705 ret = intel_bigjoiner_add_affected_crtcs(state); 7706 if (ret) 7707 goto fail; 7708 7709 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7710 new_crtc_state, i) { 7711 if (!intel_crtc_needs_modeset(new_crtc_state)) { 7712 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 7713 copy_bigjoiner_crtc_state_nomodeset(state, crtc); 7714 else 7715 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 7716 continue; 7717 } 7718 7719 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) { 7720 drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable); 7721 continue; 7722 } 7723 7724 ret = intel_crtc_prepare_cleared_state(state, crtc); 7725 if (ret) 7726 goto fail; 7727 7728 if (!new_crtc_state->hw.enable) 7729 continue; 7730 7731 ret = intel_modeset_pipe_config(state, new_crtc_state); 7732 if (ret) 7733 goto fail; 7734 7735 ret = intel_atomic_check_bigjoiner(state, crtc); 7736 if (ret) 7737 goto fail; 7738 } 7739 7740 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7741 new_crtc_state, i) { 7742 if (!intel_crtc_needs_modeset(new_crtc_state)) 7743 continue; 7744 7745 ret = intel_modeset_pipe_config_late(new_crtc_state); 7746 if (ret) 7747 goto fail; 7748 7749 intel_crtc_check_fastset(old_crtc_state, new_crtc_state); 7750 } 7751 7752 /** 7753 * Check if fastset is allowed by external dependencies like other 7754 * pipes and transcoders. 7755 * 7756 * Right now it only forces a fullmodeset when the MST master 7757 * transcoder did not changed but the pipe of the master transcoder 7758 * needs a fullmodeset so all slaves also needs to do a fullmodeset or 7759 * in case of port synced crtcs, if one of the synced crtcs 7760 * needs a full modeset, all other synced crtcs should be 7761 * forced a full modeset. 7762 */ 7763 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7764 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state)) 7765 continue; 7766 7767 if (intel_dp_mst_is_slave_trans(new_crtc_state)) { 7768 enum transcoder master = new_crtc_state->mst_master_transcoder; 7769 7770 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) { 7771 new_crtc_state->uapi.mode_changed = true; 7772 new_crtc_state->update_pipe = false; 7773 } 7774 } 7775 7776 if (is_trans_port_sync_mode(new_crtc_state)) { 7777 u8 trans = new_crtc_state->sync_mode_slaves_mask; 7778 7779 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER) 7780 trans |= BIT(new_crtc_state->master_transcoder); 7781 7782 if (intel_cpu_transcoders_need_modeset(state, trans)) { 7783 new_crtc_state->uapi.mode_changed = true; 7784 new_crtc_state->update_pipe = false; 7785 } 7786 } 7787 7788 if (new_crtc_state->bigjoiner_pipes) { 7789 if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) { 7790 new_crtc_state->uapi.mode_changed = true; 7791 new_crtc_state->update_pipe = false; 7792 } 7793 } 7794 } 7795 7796 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7797 new_crtc_state, i) { 7798 if (intel_crtc_needs_modeset(new_crtc_state)) { 7799 any_ms = true; 7800 continue; 7801 } 7802 7803 if (!new_crtc_state->update_pipe) 7804 continue; 7805 7806 intel_crtc_copy_fastset(old_crtc_state, new_crtc_state); 7807 } 7808 7809 if (any_ms && !check_digital_port_conflicts(state)) { 7810 drm_dbg_kms(&dev_priv->drm, 7811 "rejecting conflicting digital port configuration\n"); 7812 ret = -EINVAL; 7813 goto fail; 7814 } 7815 7816 ret = drm_dp_mst_atomic_check(&state->base); 7817 if (ret) 7818 goto fail; 7819 7820 ret = intel_atomic_check_planes(state); 7821 if (ret) 7822 goto fail; 7823 7824 ret = intel_compute_global_watermarks(state); 7825 if (ret) 7826 goto fail; 7827 7828 ret = intel_bw_atomic_check(state); 7829 if (ret) 7830 goto fail; 7831 7832 ret = intel_cdclk_atomic_check(state, &any_ms); 7833 if (ret) 7834 goto fail; 7835 7836 if (intel_any_crtc_needs_modeset(state)) 7837 any_ms = true; 7838 7839 if (any_ms) { 7840 ret = intel_modeset_checks(state); 7841 if (ret) 7842 goto fail; 7843 7844 ret = intel_modeset_calc_cdclk(state); 7845 if (ret) 7846 return ret; 7847 7848 intel_modeset_clear_plls(state); 7849 } 7850 7851 ret = intel_atomic_check_crtcs(state); 7852 if (ret) 7853 goto fail; 7854 7855 ret = intel_fbc_atomic_check(state); 7856 if (ret) 7857 goto fail; 7858 7859 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7860 new_crtc_state, i) { 7861 ret = intel_async_flip_check_hw(state, crtc); 7862 if (ret) 7863 goto fail; 7864 7865 if (!intel_crtc_needs_modeset(new_crtc_state) && 7866 !new_crtc_state->update_pipe) 7867 continue; 7868 7869 intel_dump_pipe_config(new_crtc_state, state, 7870 intel_crtc_needs_modeset(new_crtc_state) ? 7871 "[modeset]" : "[fastset]"); 7872 } 7873 7874 return 0; 7875 7876 fail: 7877 if (ret == -EDEADLK) 7878 return ret; 7879 7880 /* 7881 * FIXME would probably be nice to know which crtc specifically 7882 * caused the failure, in cases where we can pinpoint it. 7883 */ 7884 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7885 new_crtc_state, i) 7886 intel_dump_pipe_config(new_crtc_state, state, "[failed]"); 7887 7888 return ret; 7889 } 7890 7891 static int intel_atomic_prepare_commit(struct intel_atomic_state *state) 7892 { 7893 struct intel_crtc_state *crtc_state; 7894 struct intel_crtc *crtc; 7895 int i, ret; 7896 7897 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base); 7898 if (ret < 0) 7899 return ret; 7900 7901 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 7902 bool mode_changed = intel_crtc_needs_modeset(crtc_state); 7903 7904 if (mode_changed || crtc_state->update_pipe || 7905 crtc_state->uapi.color_mgmt_changed) { 7906 intel_dsb_prepare(crtc_state); 7907 } 7908 } 7909 7910 return 0; 7911 } 7912 7913 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 7914 struct intel_crtc_state *crtc_state) 7915 { 7916 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 7917 7918 if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes) 7919 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 7920 7921 if (crtc_state->has_pch_encoder) { 7922 enum pipe pch_transcoder = 7923 intel_crtc_pch_transcoder(crtc); 7924 7925 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true); 7926 } 7927 } 7928 7929 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, 7930 const struct intel_crtc_state *new_crtc_state) 7931 { 7932 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 7933 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 7934 7935 /* 7936 * Update pipe size and adjust fitter if needed: the reason for this is 7937 * that in compute_mode_changes we check the native mode (not the pfit 7938 * mode) to see if we can flip rather than do a full mode set. In the 7939 * fastboot case, we'll flip, but if we don't update the pipesrc and 7940 * pfit state, we'll end up with a big fb scanned out into the wrong 7941 * sized surface. 7942 */ 7943 intel_set_pipe_src_size(new_crtc_state); 7944 7945 /* on skylake this is done by detaching scalers */ 7946 if (DISPLAY_VER(dev_priv) >= 9) { 7947 if (new_crtc_state->pch_pfit.enabled) 7948 skl_pfit_enable(new_crtc_state); 7949 } else if (HAS_PCH_SPLIT(dev_priv)) { 7950 if (new_crtc_state->pch_pfit.enabled) 7951 ilk_pfit_enable(new_crtc_state); 7952 else if (old_crtc_state->pch_pfit.enabled) 7953 ilk_pfit_disable(old_crtc_state); 7954 } 7955 7956 /* 7957 * The register is supposedly single buffered so perhaps 7958 * not 100% correct to do this here. But SKL+ calculate 7959 * this based on the adjust pixel rate so pfit changes do 7960 * affect it and so it must be updated for fastsets. 7961 * HSW/BDW only really need this here for fastboot, after 7962 * that the value should not change without a full modeset. 7963 */ 7964 if (DISPLAY_VER(dev_priv) >= 9 || 7965 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 7966 hsw_set_linetime_wm(new_crtc_state); 7967 } 7968 7969 static void commit_pipe_pre_planes(struct intel_atomic_state *state, 7970 struct intel_crtc *crtc) 7971 { 7972 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7973 const struct intel_crtc_state *old_crtc_state = 7974 intel_atomic_get_old_crtc_state(state, crtc); 7975 const struct intel_crtc_state *new_crtc_state = 7976 intel_atomic_get_new_crtc_state(state, crtc); 7977 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 7978 7979 /* 7980 * During modesets pipe configuration was programmed as the 7981 * CRTC was enabled. 7982 */ 7983 if (!modeset) { 7984 if (new_crtc_state->uapi.color_mgmt_changed || 7985 new_crtc_state->update_pipe) 7986 intel_color_commit_arm(new_crtc_state); 7987 7988 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 7989 bdw_set_pipemisc(new_crtc_state); 7990 7991 if (new_crtc_state->update_pipe) 7992 intel_pipe_fastset(old_crtc_state, new_crtc_state); 7993 } 7994 7995 intel_psr2_program_trans_man_trk_ctl(new_crtc_state); 7996 7997 intel_atomic_update_watermarks(state, crtc); 7998 } 7999 8000 static void commit_pipe_post_planes(struct intel_atomic_state *state, 8001 struct intel_crtc *crtc) 8002 { 8003 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8004 const struct intel_crtc_state *new_crtc_state = 8005 intel_atomic_get_new_crtc_state(state, crtc); 8006 8007 /* 8008 * Disable the scaler(s) after the plane(s) so that we don't 8009 * get a catastrophic underrun even if the two operations 8010 * end up happening in two different frames. 8011 */ 8012 if (DISPLAY_VER(dev_priv) >= 9 && 8013 !intel_crtc_needs_modeset(new_crtc_state)) 8014 skl_detach_scalers(new_crtc_state); 8015 } 8016 8017 static void intel_enable_crtc(struct intel_atomic_state *state, 8018 struct intel_crtc *crtc) 8019 { 8020 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8021 const struct intel_crtc_state *new_crtc_state = 8022 intel_atomic_get_new_crtc_state(state, crtc); 8023 8024 if (!intel_crtc_needs_modeset(new_crtc_state)) 8025 return; 8026 8027 intel_crtc_update_active_timings(new_crtc_state); 8028 8029 dev_priv->display->crtc_enable(state, crtc); 8030 8031 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 8032 return; 8033 8034 /* vblanks work again, re-enable pipe CRC. */ 8035 intel_crtc_enable_pipe_crc(crtc); 8036 } 8037 8038 static void intel_update_crtc(struct intel_atomic_state *state, 8039 struct intel_crtc *crtc) 8040 { 8041 struct drm_i915_private *i915 = to_i915(state->base.dev); 8042 const struct intel_crtc_state *old_crtc_state = 8043 intel_atomic_get_old_crtc_state(state, crtc); 8044 struct intel_crtc_state *new_crtc_state = 8045 intel_atomic_get_new_crtc_state(state, crtc); 8046 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 8047 8048 if (!modeset) { 8049 if (new_crtc_state->preload_luts && 8050 (new_crtc_state->uapi.color_mgmt_changed || 8051 new_crtc_state->update_pipe)) 8052 intel_color_load_luts(new_crtc_state); 8053 8054 intel_pre_plane_update(state, crtc); 8055 8056 if (new_crtc_state->update_pipe) 8057 intel_encoders_update_pipe(state, crtc); 8058 8059 if (DISPLAY_VER(i915) >= 11 && 8060 new_crtc_state->update_pipe) 8061 icl_set_pipe_chicken(new_crtc_state); 8062 } 8063 8064 intel_fbc_update(state, crtc); 8065 8066 if (!modeset && 8067 (new_crtc_state->uapi.color_mgmt_changed || 8068 new_crtc_state->update_pipe)) 8069 intel_color_commit_noarm(new_crtc_state); 8070 8071 intel_crtc_planes_update_noarm(state, crtc); 8072 8073 /* Perform vblank evasion around commit operation */ 8074 intel_pipe_update_start(new_crtc_state); 8075 8076 commit_pipe_pre_planes(state, crtc); 8077 8078 intel_crtc_planes_update_arm(state, crtc); 8079 8080 commit_pipe_post_planes(state, crtc); 8081 8082 intel_pipe_update_end(new_crtc_state); 8083 8084 /* 8085 * We usually enable FIFO underrun interrupts as part of the 8086 * CRTC enable sequence during modesets. But when we inherit a 8087 * valid pipe configuration from the BIOS we need to take care 8088 * of enabling them on the CRTC's first fastset. 8089 */ 8090 if (new_crtc_state->update_pipe && !modeset && 8091 old_crtc_state->inherited) 8092 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state); 8093 } 8094 8095 static void intel_old_crtc_state_disables(struct intel_atomic_state *state, 8096 struct intel_crtc_state *old_crtc_state, 8097 struct intel_crtc_state *new_crtc_state, 8098 struct intel_crtc *crtc) 8099 { 8100 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8101 8102 /* 8103 * We need to disable pipe CRC before disabling the pipe, 8104 * or we race against vblank off. 8105 */ 8106 intel_crtc_disable_pipe_crc(crtc); 8107 8108 dev_priv->display->crtc_disable(state, crtc); 8109 crtc->active = false; 8110 intel_fbc_disable(crtc); 8111 intel_disable_shared_dpll(old_crtc_state); 8112 8113 /* FIXME unify this for all platforms */ 8114 if (!new_crtc_state->hw.active && 8115 !HAS_GMCH(dev_priv)) 8116 intel_initial_watermarks(state, crtc); 8117 } 8118 8119 static void intel_commit_modeset_disables(struct intel_atomic_state *state) 8120 { 8121 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 8122 struct intel_crtc *crtc; 8123 u32 handled = 0; 8124 int i; 8125 8126 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8127 new_crtc_state, i) { 8128 if (!intel_crtc_needs_modeset(new_crtc_state)) 8129 continue; 8130 8131 if (!old_crtc_state->hw.active) 8132 continue; 8133 8134 intel_pre_plane_update(state, crtc); 8135 intel_crtc_disable_planes(state, crtc); 8136 } 8137 8138 /* Only disable port sync and MST slaves */ 8139 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8140 new_crtc_state, i) { 8141 if (!intel_crtc_needs_modeset(new_crtc_state)) 8142 continue; 8143 8144 if (!old_crtc_state->hw.active) 8145 continue; 8146 8147 /* In case of Transcoder port Sync master slave CRTCs can be 8148 * assigned in any order and we need to make sure that 8149 * slave CRTCs are disabled first and then master CRTC since 8150 * Slave vblanks are masked till Master Vblanks. 8151 */ 8152 if (!is_trans_port_sync_slave(old_crtc_state) && 8153 !intel_dp_mst_is_slave_trans(old_crtc_state) && 8154 !intel_crtc_is_bigjoiner_slave(old_crtc_state)) 8155 continue; 8156 8157 intel_old_crtc_state_disables(state, old_crtc_state, 8158 new_crtc_state, crtc); 8159 handled |= BIT(crtc->pipe); 8160 } 8161 8162 /* Disable everything else left on */ 8163 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8164 new_crtc_state, i) { 8165 if (!intel_crtc_needs_modeset(new_crtc_state) || 8166 (handled & BIT(crtc->pipe))) 8167 continue; 8168 8169 if (!old_crtc_state->hw.active) 8170 continue; 8171 8172 intel_old_crtc_state_disables(state, old_crtc_state, 8173 new_crtc_state, crtc); 8174 } 8175 } 8176 8177 static void intel_commit_modeset_enables(struct intel_atomic_state *state) 8178 { 8179 struct intel_crtc_state *new_crtc_state; 8180 struct intel_crtc *crtc; 8181 int i; 8182 8183 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8184 if (!new_crtc_state->hw.active) 8185 continue; 8186 8187 intel_enable_crtc(state, crtc); 8188 intel_update_crtc(state, crtc); 8189 } 8190 } 8191 8192 static void skl_commit_modeset_enables(struct intel_atomic_state *state) 8193 { 8194 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 8195 struct intel_crtc *crtc; 8196 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 8197 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; 8198 u8 update_pipes = 0, modeset_pipes = 0; 8199 int i; 8200 8201 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 8202 enum pipe pipe = crtc->pipe; 8203 8204 if (!new_crtc_state->hw.active) 8205 continue; 8206 8207 /* ignore allocations for crtc's that have been turned off. */ 8208 if (!intel_crtc_needs_modeset(new_crtc_state)) { 8209 entries[pipe] = old_crtc_state->wm.skl.ddb; 8210 update_pipes |= BIT(pipe); 8211 } else { 8212 modeset_pipes |= BIT(pipe); 8213 } 8214 } 8215 8216 /* 8217 * Whenever the number of active pipes changes, we need to make sure we 8218 * update the pipes in the right order so that their ddb allocations 8219 * never overlap with each other between CRTC updates. Otherwise we'll 8220 * cause pipe underruns and other bad stuff. 8221 * 8222 * So first lets enable all pipes that do not need a fullmodeset as 8223 * those don't have any external dependency. 8224 */ 8225 while (update_pipes) { 8226 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8227 new_crtc_state, i) { 8228 enum pipe pipe = crtc->pipe; 8229 8230 if ((update_pipes & BIT(pipe)) == 0) 8231 continue; 8232 8233 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 8234 entries, I915_MAX_PIPES, pipe)) 8235 continue; 8236 8237 entries[pipe] = new_crtc_state->wm.skl.ddb; 8238 update_pipes &= ~BIT(pipe); 8239 8240 intel_update_crtc(state, crtc); 8241 8242 /* 8243 * If this is an already active pipe, it's DDB changed, 8244 * and this isn't the last pipe that needs updating 8245 * then we need to wait for a vblank to pass for the 8246 * new ddb allocation to take effect. 8247 */ 8248 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, 8249 &old_crtc_state->wm.skl.ddb) && 8250 (update_pipes | modeset_pipes)) 8251 intel_crtc_wait_for_next_vblank(crtc); 8252 } 8253 } 8254 8255 update_pipes = modeset_pipes; 8256 8257 /* 8258 * Enable all pipes that needs a modeset and do not depends on other 8259 * pipes 8260 */ 8261 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8262 enum pipe pipe = crtc->pipe; 8263 8264 if ((modeset_pipes & BIT(pipe)) == 0) 8265 continue; 8266 8267 if (intel_dp_mst_is_slave_trans(new_crtc_state) || 8268 is_trans_port_sync_master(new_crtc_state) || 8269 intel_crtc_is_bigjoiner_master(new_crtc_state)) 8270 continue; 8271 8272 modeset_pipes &= ~BIT(pipe); 8273 8274 intel_enable_crtc(state, crtc); 8275 } 8276 8277 /* 8278 * Then we enable all remaining pipes that depend on other 8279 * pipes: MST slaves and port sync masters, big joiner master 8280 */ 8281 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8282 enum pipe pipe = crtc->pipe; 8283 8284 if ((modeset_pipes & BIT(pipe)) == 0) 8285 continue; 8286 8287 modeset_pipes &= ~BIT(pipe); 8288 8289 intel_enable_crtc(state, crtc); 8290 } 8291 8292 /* 8293 * Finally we do the plane updates/etc. for all pipes that got enabled. 8294 */ 8295 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8296 enum pipe pipe = crtc->pipe; 8297 8298 if ((update_pipes & BIT(pipe)) == 0) 8299 continue; 8300 8301 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 8302 entries, I915_MAX_PIPES, pipe)); 8303 8304 entries[pipe] = new_crtc_state->wm.skl.ddb; 8305 update_pipes &= ~BIT(pipe); 8306 8307 intel_update_crtc(state, crtc); 8308 } 8309 8310 drm_WARN_ON(&dev_priv->drm, modeset_pipes); 8311 drm_WARN_ON(&dev_priv->drm, update_pipes); 8312 } 8313 8314 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) 8315 { 8316 struct intel_atomic_state *state, *next; 8317 struct llist_node *freed; 8318 8319 freed = llist_del_all(&dev_priv->atomic_helper.free_list); 8320 llist_for_each_entry_safe(state, next, freed, freed) 8321 drm_atomic_state_put(&state->base); 8322 } 8323 8324 static void intel_atomic_helper_free_state_worker(struct work_struct *work) 8325 { 8326 struct drm_i915_private *dev_priv = 8327 container_of(work, typeof(*dev_priv), atomic_helper.free_work); 8328 8329 intel_atomic_helper_free_state(dev_priv); 8330 } 8331 8332 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) 8333 { 8334 struct wait_queue_entry wait_fence, wait_reset; 8335 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); 8336 8337 init_wait_entry(&wait_fence, 0); 8338 init_wait_entry(&wait_reset, 0); 8339 for (;;) { 8340 prepare_to_wait(&intel_state->commit_ready.wait, 8341 &wait_fence, TASK_UNINTERRUPTIBLE); 8342 prepare_to_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 8343 I915_RESET_MODESET), 8344 &wait_reset, TASK_UNINTERRUPTIBLE); 8345 8346 8347 if (i915_sw_fence_done(&intel_state->commit_ready) || 8348 test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags)) 8349 break; 8350 8351 schedule(); 8352 } 8353 finish_wait(&intel_state->commit_ready.wait, &wait_fence); 8354 finish_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 8355 I915_RESET_MODESET), 8356 &wait_reset); 8357 } 8358 8359 static void intel_cleanup_dsbs(struct intel_atomic_state *state) 8360 { 8361 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 8362 struct intel_crtc *crtc; 8363 int i; 8364 8365 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8366 new_crtc_state, i) 8367 intel_dsb_cleanup(old_crtc_state); 8368 } 8369 8370 static void intel_atomic_cleanup_work(struct work_struct *work) 8371 { 8372 struct intel_atomic_state *state = 8373 container_of(work, struct intel_atomic_state, base.commit_work); 8374 struct drm_i915_private *i915 = to_i915(state->base.dev); 8375 8376 intel_cleanup_dsbs(state); 8377 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base); 8378 drm_atomic_helper_commit_cleanup_done(&state->base); 8379 drm_atomic_state_put(&state->base); 8380 8381 intel_atomic_helper_free_state(i915); 8382 } 8383 8384 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state) 8385 { 8386 struct drm_i915_private *i915 = to_i915(state->base.dev); 8387 struct intel_plane *plane; 8388 struct intel_plane_state *plane_state; 8389 int i; 8390 8391 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 8392 struct drm_framebuffer *fb = plane_state->hw.fb; 8393 int cc_plane; 8394 int ret; 8395 8396 if (!fb) 8397 continue; 8398 8399 cc_plane = intel_fb_rc_ccs_cc_plane(fb); 8400 if (cc_plane < 0) 8401 continue; 8402 8403 /* 8404 * The layout of the fast clear color value expected by HW 8405 * (the DRM ABI requiring this value to be located in fb at 8406 * offset 0 of cc plane, plane #2 previous generations or 8407 * plane #1 for flat ccs): 8408 * - 4 x 4 bytes per-channel value 8409 * (in surface type specific float/int format provided by the fb user) 8410 * - 8 bytes native color value used by the display 8411 * (converted/written by GPU during a fast clear operation using the 8412 * above per-channel values) 8413 * 8414 * The commit's FB prepare hook already ensured that FB obj is pinned and the 8415 * caller made sure that the object is synced wrt. the related color clear value 8416 * GPU write on it. 8417 */ 8418 ret = i915_gem_object_read_from_page(intel_fb_obj(fb), 8419 fb->offsets[cc_plane] + 16, 8420 &plane_state->ccval, 8421 sizeof(plane_state->ccval)); 8422 /* The above could only fail if the FB obj has an unexpected backing store type. */ 8423 drm_WARN_ON(&i915->drm, ret); 8424 } 8425 } 8426 8427 static void intel_atomic_commit_tail(struct intel_atomic_state *state) 8428 { 8429 struct drm_device *dev = state->base.dev; 8430 struct drm_i915_private *dev_priv = to_i915(dev); 8431 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 8432 struct intel_crtc *crtc; 8433 struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {}; 8434 intel_wakeref_t wakeref = 0; 8435 int i; 8436 8437 intel_atomic_commit_fence_wait(state); 8438 8439 drm_atomic_helper_wait_for_dependencies(&state->base); 8440 8441 if (state->modeset) 8442 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); 8443 8444 intel_atomic_prepare_plane_clear_colors(state); 8445 8446 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8447 new_crtc_state, i) { 8448 if (intel_crtc_needs_modeset(new_crtc_state) || 8449 new_crtc_state->update_pipe) { 8450 modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]); 8451 } 8452 } 8453 8454 intel_commit_modeset_disables(state); 8455 8456 /* FIXME: Eventually get rid of our crtc->config pointer */ 8457 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 8458 crtc->config = new_crtc_state; 8459 8460 if (state->modeset) { 8461 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base); 8462 8463 intel_set_cdclk_pre_plane_update(state); 8464 8465 intel_modeset_verify_disabled(dev_priv, state); 8466 } 8467 8468 intel_sagv_pre_plane_update(state); 8469 8470 /* Complete the events for pipes that have now been disabled */ 8471 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8472 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 8473 8474 /* Complete events for now disable pipes here. */ 8475 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) { 8476 spin_lock_irq(&dev->event_lock); 8477 drm_crtc_send_vblank_event(&crtc->base, 8478 new_crtc_state->uapi.event); 8479 spin_unlock_irq(&dev->event_lock); 8480 8481 new_crtc_state->uapi.event = NULL; 8482 } 8483 } 8484 8485 intel_encoders_update_prepare(state); 8486 8487 intel_dbuf_pre_plane_update(state); 8488 intel_mbus_dbox_update(state); 8489 8490 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8491 if (new_crtc_state->do_async_flip) 8492 intel_crtc_enable_flip_done(state, crtc); 8493 } 8494 8495 /* Now enable the clocks, plane, pipe, and connectors that we set up. */ 8496 dev_priv->display->commit_modeset_enables(state); 8497 8498 intel_encoders_update_complete(state); 8499 8500 if (state->modeset) 8501 intel_set_cdclk_post_plane_update(state); 8502 8503 intel_wait_for_vblank_workers(state); 8504 8505 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here 8506 * already, but still need the state for the delayed optimization. To 8507 * fix this: 8508 * - wrap the optimization/post_plane_update stuff into a per-crtc work. 8509 * - schedule that vblank worker _before_ calling hw_done 8510 * - at the start of commit_tail, cancel it _synchrously 8511 * - switch over to the vblank wait helper in the core after that since 8512 * we don't need out special handling any more. 8513 */ 8514 drm_atomic_helper_wait_for_flip_done(dev, &state->base); 8515 8516 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 8517 if (new_crtc_state->do_async_flip) 8518 intel_crtc_disable_flip_done(state, crtc); 8519 } 8520 8521 /* 8522 * Now that the vblank has passed, we can go ahead and program the 8523 * optimal watermarks on platforms that need two-step watermark 8524 * programming. 8525 * 8526 * TODO: Move this (and other cleanup) to an async worker eventually. 8527 */ 8528 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 8529 new_crtc_state, i) { 8530 /* 8531 * Gen2 reports pipe underruns whenever all planes are disabled. 8532 * So re-enable underrun reporting after some planes get enabled. 8533 * 8534 * We do this before .optimize_watermarks() so that we have a 8535 * chance of catching underruns with the intermediate watermarks 8536 * vs. the new plane configuration. 8537 */ 8538 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state)) 8539 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 8540 8541 intel_optimize_watermarks(state, crtc); 8542 } 8543 8544 intel_dbuf_post_plane_update(state); 8545 intel_psr_post_plane_update(state); 8546 8547 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 8548 intel_post_plane_update(state, crtc); 8549 8550 modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]); 8551 8552 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state); 8553 8554 /* 8555 * DSB cleanup is done in cleanup_work aligning with framebuffer 8556 * cleanup. So copy and reset the dsb structure to sync with 8557 * commit_done and later do dsb cleanup in cleanup_work. 8558 */ 8559 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb); 8560 } 8561 8562 /* Underruns don't always raise interrupts, so check manually */ 8563 intel_check_cpu_fifo_underruns(dev_priv); 8564 intel_check_pch_fifo_underruns(dev_priv); 8565 8566 if (state->modeset) 8567 intel_verify_planes(state); 8568 8569 intel_sagv_post_plane_update(state); 8570 8571 drm_atomic_helper_commit_hw_done(&state->base); 8572 8573 if (state->modeset) { 8574 /* As one of the primary mmio accessors, KMS has a high 8575 * likelihood of triggering bugs in unclaimed access. After we 8576 * finish modesetting, see if an error has been flagged, and if 8577 * so enable debugging for the next modeset - and hope we catch 8578 * the culprit. 8579 */ 8580 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); 8581 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref); 8582 } 8583 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 8584 8585 /* 8586 * Defer the cleanup of the old state to a separate worker to not 8587 * impede the current task (userspace for blocking modesets) that 8588 * are executed inline. For out-of-line asynchronous modesets/flips, 8589 * deferring to a new worker seems overkill, but we would place a 8590 * schedule point (cond_resched()) here anyway to keep latencies 8591 * down. 8592 */ 8593 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work); 8594 queue_work(system_highpri_wq, &state->base.commit_work); 8595 } 8596 8597 static void intel_atomic_commit_work(struct work_struct *work) 8598 { 8599 struct intel_atomic_state *state = 8600 container_of(work, struct intel_atomic_state, base.commit_work); 8601 8602 intel_atomic_commit_tail(state); 8603 } 8604 8605 static int 8606 intel_atomic_commit_ready(struct i915_sw_fence *fence, 8607 enum i915_sw_fence_notify notify) 8608 { 8609 struct intel_atomic_state *state = 8610 container_of(fence, struct intel_atomic_state, commit_ready); 8611 8612 switch (notify) { 8613 case FENCE_COMPLETE: 8614 /* we do blocking waits in the worker, nothing to do here */ 8615 break; 8616 case FENCE_FREE: 8617 { 8618 struct intel_atomic_helper *helper = 8619 &to_i915(state->base.dev)->atomic_helper; 8620 8621 if (llist_add(&state->freed, &helper->free_list)) 8622 schedule_work(&helper->free_work); 8623 break; 8624 } 8625 } 8626 8627 return NOTIFY_DONE; 8628 } 8629 8630 static void intel_atomic_track_fbs(struct intel_atomic_state *state) 8631 { 8632 struct intel_plane_state *old_plane_state, *new_plane_state; 8633 struct intel_plane *plane; 8634 int i; 8635 8636 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 8637 new_plane_state, i) 8638 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), 8639 to_intel_frontbuffer(new_plane_state->hw.fb), 8640 plane->frontbuffer_bit); 8641 } 8642 8643 static int intel_atomic_commit(struct drm_device *dev, 8644 struct drm_atomic_state *_state, 8645 bool nonblock) 8646 { 8647 struct intel_atomic_state *state = to_intel_atomic_state(_state); 8648 struct drm_i915_private *dev_priv = to_i915(dev); 8649 int ret = 0; 8650 8651 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 8652 8653 drm_atomic_state_get(&state->base); 8654 i915_sw_fence_init(&state->commit_ready, 8655 intel_atomic_commit_ready); 8656 8657 /* 8658 * The intel_legacy_cursor_update() fast path takes care 8659 * of avoiding the vblank waits for simple cursor 8660 * movement and flips. For cursor on/off and size changes, 8661 * we want to perform the vblank waits so that watermark 8662 * updates happen during the correct frames. Gen9+ have 8663 * double buffered watermarks and so shouldn't need this. 8664 * 8665 * Unset state->legacy_cursor_update before the call to 8666 * drm_atomic_helper_setup_commit() because otherwise 8667 * drm_atomic_helper_wait_for_flip_done() is a noop and 8668 * we get FIFO underruns because we didn't wait 8669 * for vblank. 8670 * 8671 * FIXME doing watermarks and fb cleanup from a vblank worker 8672 * (assuming we had any) would solve these problems. 8673 */ 8674 if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) { 8675 struct intel_crtc_state *new_crtc_state; 8676 struct intel_crtc *crtc; 8677 int i; 8678 8679 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 8680 if (new_crtc_state->wm.need_postvbl_update || 8681 new_crtc_state->update_wm_post) 8682 state->base.legacy_cursor_update = false; 8683 } 8684 8685 ret = intel_atomic_prepare_commit(state); 8686 if (ret) { 8687 drm_dbg_atomic(&dev_priv->drm, 8688 "Preparing state failed with %i\n", ret); 8689 i915_sw_fence_commit(&state->commit_ready); 8690 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 8691 return ret; 8692 } 8693 8694 ret = drm_atomic_helper_setup_commit(&state->base, nonblock); 8695 if (!ret) 8696 ret = drm_atomic_helper_swap_state(&state->base, true); 8697 if (!ret) 8698 intel_atomic_swap_global_state(state); 8699 8700 if (ret) { 8701 struct intel_crtc_state *new_crtc_state; 8702 struct intel_crtc *crtc; 8703 int i; 8704 8705 i915_sw_fence_commit(&state->commit_ready); 8706 8707 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 8708 intel_dsb_cleanup(new_crtc_state); 8709 8710 drm_atomic_helper_cleanup_planes(dev, &state->base); 8711 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 8712 return ret; 8713 } 8714 intel_shared_dpll_swap_state(state); 8715 intel_atomic_track_fbs(state); 8716 8717 drm_atomic_state_get(&state->base); 8718 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work); 8719 8720 i915_sw_fence_commit(&state->commit_ready); 8721 if (nonblock && state->modeset) { 8722 queue_work(dev_priv->modeset_wq, &state->base.commit_work); 8723 } else if (nonblock) { 8724 queue_work(dev_priv->flip_wq, &state->base.commit_work); 8725 } else { 8726 if (state->modeset) 8727 flush_workqueue(dev_priv->modeset_wq); 8728 intel_atomic_commit_tail(state); 8729 } 8730 8731 return 0; 8732 } 8733 8734 /** 8735 * intel_plane_destroy - destroy a plane 8736 * @plane: plane to destroy 8737 * 8738 * Common destruction function for all types of planes (primary, cursor, 8739 * sprite). 8740 */ 8741 void intel_plane_destroy(struct drm_plane *plane) 8742 { 8743 drm_plane_cleanup(plane); 8744 kfree(to_intel_plane(plane)); 8745 } 8746 8747 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv) 8748 { 8749 struct intel_plane *plane; 8750 8751 for_each_intel_plane(&dev_priv->drm, plane) { 8752 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, 8753 plane->pipe); 8754 8755 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base); 8756 } 8757 } 8758 8759 8760 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 8761 struct drm_file *file) 8762 { 8763 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; 8764 struct drm_crtc *drmmode_crtc; 8765 struct intel_crtc *crtc; 8766 8767 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id); 8768 if (!drmmode_crtc) 8769 return -ENOENT; 8770 8771 crtc = to_intel_crtc(drmmode_crtc); 8772 pipe_from_crtc_id->pipe = crtc->pipe; 8773 8774 return 0; 8775 } 8776 8777 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder) 8778 { 8779 struct drm_device *dev = encoder->base.dev; 8780 struct intel_encoder *source_encoder; 8781 u32 possible_clones = 0; 8782 8783 for_each_intel_encoder(dev, source_encoder) { 8784 if (encoders_cloneable(encoder, source_encoder)) 8785 possible_clones |= drm_encoder_mask(&source_encoder->base); 8786 } 8787 8788 return possible_clones; 8789 } 8790 8791 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder) 8792 { 8793 struct drm_device *dev = encoder->base.dev; 8794 struct intel_crtc *crtc; 8795 u32 possible_crtcs = 0; 8796 8797 for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask) 8798 possible_crtcs |= drm_crtc_mask(&crtc->base); 8799 8800 return possible_crtcs; 8801 } 8802 8803 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv) 8804 { 8805 if (!IS_MOBILE(dev_priv)) 8806 return false; 8807 8808 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0) 8809 return false; 8810 8811 if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE)) 8812 return false; 8813 8814 return true; 8815 } 8816 8817 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv) 8818 { 8819 if (DISPLAY_VER(dev_priv) >= 9) 8820 return false; 8821 8822 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) 8823 return false; 8824 8825 if (HAS_PCH_LPT_H(dev_priv) && 8826 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) 8827 return false; 8828 8829 /* DDI E can't be used if DDI A requires 4 lanes */ 8830 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 8831 return false; 8832 8833 if (!dev_priv->vbt.int_crt_support) 8834 return false; 8835 8836 return true; 8837 } 8838 8839 static void intel_setup_outputs(struct drm_i915_private *dev_priv) 8840 { 8841 struct intel_encoder *encoder; 8842 bool dpd_is_edp = false; 8843 8844 intel_pps_unlock_regs_wa(dev_priv); 8845 8846 if (!HAS_DISPLAY(dev_priv)) 8847 return; 8848 8849 if (IS_DG2(dev_priv)) { 8850 intel_ddi_init(dev_priv, PORT_A); 8851 intel_ddi_init(dev_priv, PORT_B); 8852 intel_ddi_init(dev_priv, PORT_C); 8853 intel_ddi_init(dev_priv, PORT_D_XELPD); 8854 intel_ddi_init(dev_priv, PORT_TC1); 8855 } else if (IS_ALDERLAKE_P(dev_priv)) { 8856 intel_ddi_init(dev_priv, PORT_A); 8857 intel_ddi_init(dev_priv, PORT_B); 8858 intel_ddi_init(dev_priv, PORT_TC1); 8859 intel_ddi_init(dev_priv, PORT_TC2); 8860 intel_ddi_init(dev_priv, PORT_TC3); 8861 intel_ddi_init(dev_priv, PORT_TC4); 8862 icl_dsi_init(dev_priv); 8863 } else if (IS_ALDERLAKE_S(dev_priv)) { 8864 intel_ddi_init(dev_priv, PORT_A); 8865 intel_ddi_init(dev_priv, PORT_TC1); 8866 intel_ddi_init(dev_priv, PORT_TC2); 8867 intel_ddi_init(dev_priv, PORT_TC3); 8868 intel_ddi_init(dev_priv, PORT_TC4); 8869 } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) { 8870 intel_ddi_init(dev_priv, PORT_A); 8871 intel_ddi_init(dev_priv, PORT_B); 8872 intel_ddi_init(dev_priv, PORT_TC1); 8873 intel_ddi_init(dev_priv, PORT_TC2); 8874 } else if (DISPLAY_VER(dev_priv) >= 12) { 8875 intel_ddi_init(dev_priv, PORT_A); 8876 intel_ddi_init(dev_priv, PORT_B); 8877 intel_ddi_init(dev_priv, PORT_TC1); 8878 intel_ddi_init(dev_priv, PORT_TC2); 8879 intel_ddi_init(dev_priv, PORT_TC3); 8880 intel_ddi_init(dev_priv, PORT_TC4); 8881 intel_ddi_init(dev_priv, PORT_TC5); 8882 intel_ddi_init(dev_priv, PORT_TC6); 8883 icl_dsi_init(dev_priv); 8884 } else if (IS_JSL_EHL(dev_priv)) { 8885 intel_ddi_init(dev_priv, PORT_A); 8886 intel_ddi_init(dev_priv, PORT_B); 8887 intel_ddi_init(dev_priv, PORT_C); 8888 intel_ddi_init(dev_priv, PORT_D); 8889 icl_dsi_init(dev_priv); 8890 } else if (DISPLAY_VER(dev_priv) == 11) { 8891 intel_ddi_init(dev_priv, PORT_A); 8892 intel_ddi_init(dev_priv, PORT_B); 8893 intel_ddi_init(dev_priv, PORT_C); 8894 intel_ddi_init(dev_priv, PORT_D); 8895 intel_ddi_init(dev_priv, PORT_E); 8896 intel_ddi_init(dev_priv, PORT_F); 8897 icl_dsi_init(dev_priv); 8898 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 8899 intel_ddi_init(dev_priv, PORT_A); 8900 intel_ddi_init(dev_priv, PORT_B); 8901 intel_ddi_init(dev_priv, PORT_C); 8902 vlv_dsi_init(dev_priv); 8903 } else if (DISPLAY_VER(dev_priv) >= 9) { 8904 intel_ddi_init(dev_priv, PORT_A); 8905 intel_ddi_init(dev_priv, PORT_B); 8906 intel_ddi_init(dev_priv, PORT_C); 8907 intel_ddi_init(dev_priv, PORT_D); 8908 intel_ddi_init(dev_priv, PORT_E); 8909 } else if (HAS_DDI(dev_priv)) { 8910 u32 found; 8911 8912 if (intel_ddi_crt_present(dev_priv)) 8913 intel_crt_init(dev_priv); 8914 8915 /* Haswell uses DDI functions to detect digital outputs. */ 8916 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 8917 if (found) 8918 intel_ddi_init(dev_priv, PORT_A); 8919 8920 found = intel_de_read(dev_priv, SFUSE_STRAP); 8921 if (found & SFUSE_STRAP_DDIB_DETECTED) 8922 intel_ddi_init(dev_priv, PORT_B); 8923 if (found & SFUSE_STRAP_DDIC_DETECTED) 8924 intel_ddi_init(dev_priv, PORT_C); 8925 if (found & SFUSE_STRAP_DDID_DETECTED) 8926 intel_ddi_init(dev_priv, PORT_D); 8927 if (found & SFUSE_STRAP_DDIF_DETECTED) 8928 intel_ddi_init(dev_priv, PORT_F); 8929 } else if (HAS_PCH_SPLIT(dev_priv)) { 8930 int found; 8931 8932 /* 8933 * intel_edp_init_connector() depends on this completing first, 8934 * to prevent the registration of both eDP and LVDS and the 8935 * incorrect sharing of the PPS. 8936 */ 8937 intel_lvds_init(dev_priv); 8938 intel_crt_init(dev_priv); 8939 8940 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D); 8941 8942 if (ilk_has_edp_a(dev_priv)) 8943 g4x_dp_init(dev_priv, DP_A, PORT_A); 8944 8945 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) { 8946 /* PCH SDVOB multiplex with HDMIB */ 8947 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); 8948 if (!found) 8949 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); 8950 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED)) 8951 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B); 8952 } 8953 8954 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED) 8955 g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); 8956 8957 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED) 8958 g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D); 8959 8960 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED) 8961 g4x_dp_init(dev_priv, PCH_DP_C, PORT_C); 8962 8963 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED) 8964 g4x_dp_init(dev_priv, PCH_DP_D, PORT_D); 8965 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 8966 bool has_edp, has_port; 8967 8968 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support) 8969 intel_crt_init(dev_priv); 8970 8971 /* 8972 * The DP_DETECTED bit is the latched state of the DDC 8973 * SDA pin at boot. However since eDP doesn't require DDC 8974 * (no way to plug in a DP->HDMI dongle) the DDC pins for 8975 * eDP ports may have been muxed to an alternate function. 8976 * Thus we can't rely on the DP_DETECTED bit alone to detect 8977 * eDP ports. Consult the VBT as well as DP_DETECTED to 8978 * detect eDP ports. 8979 * 8980 * Sadly the straps seem to be missing sometimes even for HDMI 8981 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap 8982 * and VBT for the presence of the port. Additionally we can't 8983 * trust the port type the VBT declares as we've seen at least 8984 * HDMI ports that the VBT claim are DP or eDP. 8985 */ 8986 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B); 8987 has_port = intel_bios_is_port_present(dev_priv, PORT_B); 8988 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port) 8989 has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B); 8990 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) 8991 g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); 8992 8993 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C); 8994 has_port = intel_bios_is_port_present(dev_priv, PORT_C); 8995 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port) 8996 has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C); 8997 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) 8998 g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); 8999 9000 if (IS_CHERRYVIEW(dev_priv)) { 9001 /* 9002 * eDP not supported on port D, 9003 * so no need to worry about it 9004 */ 9005 has_port = intel_bios_is_port_present(dev_priv, PORT_D); 9006 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port) 9007 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D); 9008 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port) 9009 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D); 9010 } 9011 9012 vlv_dsi_init(dev_priv); 9013 } else if (IS_PINEVIEW(dev_priv)) { 9014 intel_lvds_init(dev_priv); 9015 intel_crt_init(dev_priv); 9016 } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) { 9017 bool found = false; 9018 9019 if (IS_MOBILE(dev_priv)) 9020 intel_lvds_init(dev_priv); 9021 9022 intel_crt_init(dev_priv); 9023 9024 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 9025 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n"); 9026 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); 9027 if (!found && IS_G4X(dev_priv)) { 9028 drm_dbg_kms(&dev_priv->drm, 9029 "probing HDMI on SDVOB\n"); 9030 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); 9031 } 9032 9033 if (!found && IS_G4X(dev_priv)) 9034 g4x_dp_init(dev_priv, DP_B, PORT_B); 9035 } 9036 9037 /* Before G4X SDVOC doesn't have its own detect register */ 9038 9039 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 9040 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n"); 9041 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); 9042 } 9043 9044 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) { 9045 9046 if (IS_G4X(dev_priv)) { 9047 drm_dbg_kms(&dev_priv->drm, 9048 "probing HDMI on SDVOC\n"); 9049 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); 9050 } 9051 if (IS_G4X(dev_priv)) 9052 g4x_dp_init(dev_priv, DP_C, PORT_C); 9053 } 9054 9055 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED)) 9056 g4x_dp_init(dev_priv, DP_D, PORT_D); 9057 9058 if (SUPPORTS_TV(dev_priv)) 9059 intel_tv_init(dev_priv); 9060 } else if (DISPLAY_VER(dev_priv) == 2) { 9061 if (IS_I85X(dev_priv)) 9062 intel_lvds_init(dev_priv); 9063 9064 intel_crt_init(dev_priv); 9065 intel_dvo_init(dev_priv); 9066 } 9067 9068 for_each_intel_encoder(&dev_priv->drm, encoder) { 9069 encoder->base.possible_crtcs = 9070 intel_encoder_possible_crtcs(encoder); 9071 encoder->base.possible_clones = 9072 intel_encoder_possible_clones(encoder); 9073 } 9074 9075 intel_init_pch_refclk(dev_priv); 9076 9077 drm_helper_move_panel_connectors_to_head(&dev_priv->drm); 9078 } 9079 9080 static enum drm_mode_status 9081 intel_mode_valid(struct drm_device *dev, 9082 const struct drm_display_mode *mode) 9083 { 9084 struct drm_i915_private *dev_priv = to_i915(dev); 9085 int hdisplay_max, htotal_max; 9086 int vdisplay_max, vtotal_max; 9087 9088 /* 9089 * Can't reject DBLSCAN here because Xorg ddxen can add piles 9090 * of DBLSCAN modes to the output's mode list when they detect 9091 * the scaling mode property on the connector. And they don't 9092 * ask the kernel to validate those modes in any way until 9093 * modeset time at which point the client gets a protocol error. 9094 * So in order to not upset those clients we silently ignore the 9095 * DBLSCAN flag on such connectors. For other connectors we will 9096 * reject modes with the DBLSCAN flag in encoder->compute_config(). 9097 * And we always reject DBLSCAN modes in connector->mode_valid() 9098 * as we never want such modes on the connector's mode list. 9099 */ 9100 9101 if (mode->vscan > 1) 9102 return MODE_NO_VSCAN; 9103 9104 if (mode->flags & DRM_MODE_FLAG_HSKEW) 9105 return MODE_H_ILLEGAL; 9106 9107 if (mode->flags & (DRM_MODE_FLAG_CSYNC | 9108 DRM_MODE_FLAG_NCSYNC | 9109 DRM_MODE_FLAG_PCSYNC)) 9110 return MODE_HSYNC; 9111 9112 if (mode->flags & (DRM_MODE_FLAG_BCAST | 9113 DRM_MODE_FLAG_PIXMUX | 9114 DRM_MODE_FLAG_CLKDIV2)) 9115 return MODE_BAD; 9116 9117 /* Transcoder timing limits */ 9118 if (DISPLAY_VER(dev_priv) >= 11) { 9119 hdisplay_max = 16384; 9120 vdisplay_max = 8192; 9121 htotal_max = 16384; 9122 vtotal_max = 8192; 9123 } else if (DISPLAY_VER(dev_priv) >= 9 || 9124 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 9125 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ 9126 vdisplay_max = 4096; 9127 htotal_max = 8192; 9128 vtotal_max = 8192; 9129 } else if (DISPLAY_VER(dev_priv) >= 3) { 9130 hdisplay_max = 4096; 9131 vdisplay_max = 4096; 9132 htotal_max = 8192; 9133 vtotal_max = 8192; 9134 } else { 9135 hdisplay_max = 2048; 9136 vdisplay_max = 2048; 9137 htotal_max = 4096; 9138 vtotal_max = 4096; 9139 } 9140 9141 if (mode->hdisplay > hdisplay_max || 9142 mode->hsync_start > htotal_max || 9143 mode->hsync_end > htotal_max || 9144 mode->htotal > htotal_max) 9145 return MODE_H_ILLEGAL; 9146 9147 if (mode->vdisplay > vdisplay_max || 9148 mode->vsync_start > vtotal_max || 9149 mode->vsync_end > vtotal_max || 9150 mode->vtotal > vtotal_max) 9151 return MODE_V_ILLEGAL; 9152 9153 if (DISPLAY_VER(dev_priv) >= 5) { 9154 if (mode->hdisplay < 64 || 9155 mode->htotal - mode->hdisplay < 32) 9156 return MODE_H_ILLEGAL; 9157 9158 if (mode->vtotal - mode->vdisplay < 5) 9159 return MODE_V_ILLEGAL; 9160 } else { 9161 if (mode->htotal - mode->hdisplay < 32) 9162 return MODE_H_ILLEGAL; 9163 9164 if (mode->vtotal - mode->vdisplay < 3) 9165 return MODE_V_ILLEGAL; 9166 } 9167 9168 /* 9169 * Cantiga+ cannot handle modes with a hsync front porch of 0. 9170 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. 9171 */ 9172 if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) && 9173 mode->hsync_start == mode->hdisplay) 9174 return MODE_H_ILLEGAL; 9175 9176 return MODE_OK; 9177 } 9178 9179 enum drm_mode_status 9180 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 9181 const struct drm_display_mode *mode, 9182 bool bigjoiner) 9183 { 9184 int plane_width_max, plane_height_max; 9185 9186 /* 9187 * intel_mode_valid() should be 9188 * sufficient on older platforms. 9189 */ 9190 if (DISPLAY_VER(dev_priv) < 9) 9191 return MODE_OK; 9192 9193 /* 9194 * Most people will probably want a fullscreen 9195 * plane so let's not advertize modes that are 9196 * too big for that. 9197 */ 9198 if (DISPLAY_VER(dev_priv) >= 11) { 9199 plane_width_max = 5120 << bigjoiner; 9200 plane_height_max = 4320; 9201 } else { 9202 plane_width_max = 5120; 9203 plane_height_max = 4096; 9204 } 9205 9206 if (mode->hdisplay > plane_width_max) 9207 return MODE_H_ILLEGAL; 9208 9209 if (mode->vdisplay > plane_height_max) 9210 return MODE_V_ILLEGAL; 9211 9212 return MODE_OK; 9213 } 9214 9215 static const struct drm_mode_config_funcs intel_mode_funcs = { 9216 .fb_create = intel_user_framebuffer_create, 9217 .get_format_info = intel_fb_get_format_info, 9218 .output_poll_changed = intel_fbdev_output_poll_changed, 9219 .mode_valid = intel_mode_valid, 9220 .atomic_check = intel_atomic_check, 9221 .atomic_commit = intel_atomic_commit, 9222 .atomic_state_alloc = intel_atomic_state_alloc, 9223 .atomic_state_clear = intel_atomic_state_clear, 9224 .atomic_state_free = intel_atomic_state_free, 9225 }; 9226 9227 static const struct drm_i915_display_funcs skl_display_funcs = { 9228 .get_pipe_config = hsw_get_pipe_config, 9229 .crtc_enable = hsw_crtc_enable, 9230 .crtc_disable = hsw_crtc_disable, 9231 .commit_modeset_enables = skl_commit_modeset_enables, 9232 .get_initial_plane_config = skl_get_initial_plane_config, 9233 }; 9234 9235 static const struct drm_i915_display_funcs ddi_display_funcs = { 9236 .get_pipe_config = hsw_get_pipe_config, 9237 .crtc_enable = hsw_crtc_enable, 9238 .crtc_disable = hsw_crtc_disable, 9239 .commit_modeset_enables = intel_commit_modeset_enables, 9240 .get_initial_plane_config = i9xx_get_initial_plane_config, 9241 }; 9242 9243 static const struct drm_i915_display_funcs pch_split_display_funcs = { 9244 .get_pipe_config = ilk_get_pipe_config, 9245 .crtc_enable = ilk_crtc_enable, 9246 .crtc_disable = ilk_crtc_disable, 9247 .commit_modeset_enables = intel_commit_modeset_enables, 9248 .get_initial_plane_config = i9xx_get_initial_plane_config, 9249 }; 9250 9251 static const struct drm_i915_display_funcs vlv_display_funcs = { 9252 .get_pipe_config = i9xx_get_pipe_config, 9253 .crtc_enable = valleyview_crtc_enable, 9254 .crtc_disable = i9xx_crtc_disable, 9255 .commit_modeset_enables = intel_commit_modeset_enables, 9256 .get_initial_plane_config = i9xx_get_initial_plane_config, 9257 }; 9258 9259 static const struct drm_i915_display_funcs i9xx_display_funcs = { 9260 .get_pipe_config = i9xx_get_pipe_config, 9261 .crtc_enable = i9xx_crtc_enable, 9262 .crtc_disable = i9xx_crtc_disable, 9263 .commit_modeset_enables = intel_commit_modeset_enables, 9264 .get_initial_plane_config = i9xx_get_initial_plane_config, 9265 }; 9266 9267 /** 9268 * intel_init_display_hooks - initialize the display modesetting hooks 9269 * @dev_priv: device private 9270 */ 9271 void intel_init_display_hooks(struct drm_i915_private *dev_priv) 9272 { 9273 if (!HAS_DISPLAY(dev_priv)) 9274 return; 9275 9276 intel_init_cdclk_hooks(dev_priv); 9277 intel_audio_hooks_init(dev_priv); 9278 9279 intel_dpll_init_clock_hook(dev_priv); 9280 9281 if (DISPLAY_VER(dev_priv) >= 9) { 9282 dev_priv->display = &skl_display_funcs; 9283 } else if (HAS_DDI(dev_priv)) { 9284 dev_priv->display = &ddi_display_funcs; 9285 } else if (HAS_PCH_SPLIT(dev_priv)) { 9286 dev_priv->display = &pch_split_display_funcs; 9287 } else if (IS_CHERRYVIEW(dev_priv) || 9288 IS_VALLEYVIEW(dev_priv)) { 9289 dev_priv->display = &vlv_display_funcs; 9290 } else { 9291 dev_priv->display = &i9xx_display_funcs; 9292 } 9293 9294 intel_fdi_init_hook(dev_priv); 9295 } 9296 9297 void intel_modeset_init_hw(struct drm_i915_private *i915) 9298 { 9299 struct intel_cdclk_state *cdclk_state; 9300 9301 if (!HAS_DISPLAY(i915)) 9302 return; 9303 9304 cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state); 9305 9306 intel_update_cdclk(i915); 9307 intel_cdclk_dump_config(i915, &i915->cdclk.hw, "Current CDCLK"); 9308 cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw; 9309 } 9310 9311 static int sanitize_watermarks_add_affected(struct drm_atomic_state *state) 9312 { 9313 struct drm_plane *plane; 9314 struct intel_crtc *crtc; 9315 9316 for_each_intel_crtc(state->dev, crtc) { 9317 struct intel_crtc_state *crtc_state; 9318 9319 crtc_state = intel_atomic_get_crtc_state(state, crtc); 9320 if (IS_ERR(crtc_state)) 9321 return PTR_ERR(crtc_state); 9322 9323 if (crtc_state->hw.active) { 9324 /* 9325 * Preserve the inherited flag to avoid 9326 * taking the full modeset path. 9327 */ 9328 crtc_state->inherited = true; 9329 } 9330 } 9331 9332 drm_for_each_plane(plane, state->dev) { 9333 struct drm_plane_state *plane_state; 9334 9335 plane_state = drm_atomic_get_plane_state(state, plane); 9336 if (IS_ERR(plane_state)) 9337 return PTR_ERR(plane_state); 9338 } 9339 9340 return 0; 9341 } 9342 9343 /* 9344 * Calculate what we think the watermarks should be for the state we've read 9345 * out of the hardware and then immediately program those watermarks so that 9346 * we ensure the hardware settings match our internal state. 9347 * 9348 * We can calculate what we think WM's should be by creating a duplicate of the 9349 * current state (which was constructed during hardware readout) and running it 9350 * through the atomic check code to calculate new watermark values in the 9351 * state object. 9352 */ 9353 static void sanitize_watermarks(struct drm_i915_private *dev_priv) 9354 { 9355 struct drm_atomic_state *state; 9356 struct intel_atomic_state *intel_state; 9357 struct intel_crtc *crtc; 9358 struct intel_crtc_state *crtc_state; 9359 struct drm_modeset_acquire_ctx ctx; 9360 int ret; 9361 int i; 9362 9363 /* Only supported on platforms that use atomic watermark design */ 9364 if (!dev_priv->wm_disp->optimize_watermarks) 9365 return; 9366 9367 state = drm_atomic_state_alloc(&dev_priv->drm); 9368 if (drm_WARN_ON(&dev_priv->drm, !state)) 9369 return; 9370 9371 intel_state = to_intel_atomic_state(state); 9372 9373 drm_modeset_acquire_init(&ctx, 0); 9374 9375 retry: 9376 state->acquire_ctx = &ctx; 9377 9378 /* 9379 * Hardware readout is the only time we don't want to calculate 9380 * intermediate watermarks (since we don't trust the current 9381 * watermarks). 9382 */ 9383 if (!HAS_GMCH(dev_priv)) 9384 intel_state->skip_intermediate_wm = true; 9385 9386 ret = sanitize_watermarks_add_affected(state); 9387 if (ret) 9388 goto fail; 9389 9390 ret = intel_atomic_check(&dev_priv->drm, state); 9391 if (ret) 9392 goto fail; 9393 9394 /* Write calculated watermark values back */ 9395 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) { 9396 crtc_state->wm.need_postvbl_update = true; 9397 intel_optimize_watermarks(intel_state, crtc); 9398 9399 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm; 9400 } 9401 9402 fail: 9403 if (ret == -EDEADLK) { 9404 drm_atomic_state_clear(state); 9405 drm_modeset_backoff(&ctx); 9406 goto retry; 9407 } 9408 9409 /* 9410 * If we fail here, it means that the hardware appears to be 9411 * programmed in a way that shouldn't be possible, given our 9412 * understanding of watermark requirements. This might mean a 9413 * mistake in the hardware readout code or a mistake in the 9414 * watermark calculations for a given platform. Raise a WARN 9415 * so that this is noticeable. 9416 * 9417 * If this actually happens, we'll have to just leave the 9418 * BIOS-programmed watermarks untouched and hope for the best. 9419 */ 9420 drm_WARN(&dev_priv->drm, ret, 9421 "Could not determine valid watermarks for inherited state\n"); 9422 9423 drm_atomic_state_put(state); 9424 9425 drm_modeset_drop_locks(&ctx); 9426 drm_modeset_acquire_fini(&ctx); 9427 } 9428 9429 static int intel_initial_commit(struct drm_device *dev) 9430 { 9431 struct drm_atomic_state *state = NULL; 9432 struct drm_modeset_acquire_ctx ctx; 9433 struct intel_crtc *crtc; 9434 int ret = 0; 9435 9436 state = drm_atomic_state_alloc(dev); 9437 if (!state) 9438 return -ENOMEM; 9439 9440 drm_modeset_acquire_init(&ctx, 0); 9441 9442 retry: 9443 state->acquire_ctx = &ctx; 9444 9445 for_each_intel_crtc(dev, crtc) { 9446 struct intel_crtc_state *crtc_state = 9447 intel_atomic_get_crtc_state(state, crtc); 9448 9449 if (IS_ERR(crtc_state)) { 9450 ret = PTR_ERR(crtc_state); 9451 goto out; 9452 } 9453 9454 if (crtc_state->hw.active) { 9455 struct intel_encoder *encoder; 9456 9457 /* 9458 * We've not yet detected sink capabilities 9459 * (audio,infoframes,etc.) and thus we don't want to 9460 * force a full state recomputation yet. We want that to 9461 * happen only for the first real commit from userspace. 9462 * So preserve the inherited flag for the time being. 9463 */ 9464 crtc_state->inherited = true; 9465 9466 ret = drm_atomic_add_affected_planes(state, &crtc->base); 9467 if (ret) 9468 goto out; 9469 9470 /* 9471 * FIXME hack to force a LUT update to avoid the 9472 * plane update forcing the pipe gamma on without 9473 * having a proper LUT loaded. Remove once we 9474 * have readout for pipe gamma enable. 9475 */ 9476 crtc_state->uapi.color_mgmt_changed = true; 9477 9478 for_each_intel_encoder_mask(dev, encoder, 9479 crtc_state->uapi.encoder_mask) { 9480 if (encoder->initial_fastset_check && 9481 !encoder->initial_fastset_check(encoder, crtc_state)) { 9482 ret = drm_atomic_add_affected_connectors(state, 9483 &crtc->base); 9484 if (ret) 9485 goto out; 9486 } 9487 } 9488 } 9489 } 9490 9491 ret = drm_atomic_commit(state); 9492 9493 out: 9494 if (ret == -EDEADLK) { 9495 drm_atomic_state_clear(state); 9496 drm_modeset_backoff(&ctx); 9497 goto retry; 9498 } 9499 9500 drm_atomic_state_put(state); 9501 9502 drm_modeset_drop_locks(&ctx); 9503 drm_modeset_acquire_fini(&ctx); 9504 9505 return ret; 9506 } 9507 9508 static void intel_mode_config_init(struct drm_i915_private *i915) 9509 { 9510 struct drm_mode_config *mode_config = &i915->drm.mode_config; 9511 9512 drm_mode_config_init(&i915->drm); 9513 INIT_LIST_HEAD(&i915->global_obj_list); 9514 9515 mode_config->min_width = 0; 9516 mode_config->min_height = 0; 9517 9518 mode_config->preferred_depth = 24; 9519 mode_config->prefer_shadow = 1; 9520 9521 mode_config->funcs = &intel_mode_funcs; 9522 9523 mode_config->async_page_flip = HAS_ASYNC_FLIPS(i915); 9524 9525 /* 9526 * Maximum framebuffer dimensions, chosen to match 9527 * the maximum render engine surface size on gen4+. 9528 */ 9529 if (DISPLAY_VER(i915) >= 7) { 9530 mode_config->max_width = 16384; 9531 mode_config->max_height = 16384; 9532 } else if (DISPLAY_VER(i915) >= 4) { 9533 mode_config->max_width = 8192; 9534 mode_config->max_height = 8192; 9535 } else if (DISPLAY_VER(i915) == 3) { 9536 mode_config->max_width = 4096; 9537 mode_config->max_height = 4096; 9538 } else { 9539 mode_config->max_width = 2048; 9540 mode_config->max_height = 2048; 9541 } 9542 9543 if (IS_I845G(i915) || IS_I865G(i915)) { 9544 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512; 9545 mode_config->cursor_height = 1023; 9546 } else if (IS_I830(i915) || IS_I85X(i915) || 9547 IS_I915G(i915) || IS_I915GM(i915)) { 9548 mode_config->cursor_width = 64; 9549 mode_config->cursor_height = 64; 9550 } else { 9551 mode_config->cursor_width = 256; 9552 mode_config->cursor_height = 256; 9553 } 9554 } 9555 9556 static void intel_mode_config_cleanup(struct drm_i915_private *i915) 9557 { 9558 intel_atomic_global_obj_cleanup(i915); 9559 drm_mode_config_cleanup(&i915->drm); 9560 } 9561 9562 /* part #1: call before irq install */ 9563 int intel_modeset_init_noirq(struct drm_i915_private *i915) 9564 { 9565 int ret; 9566 9567 if (i915_inject_probe_failure(i915)) 9568 return -ENODEV; 9569 9570 if (HAS_DISPLAY(i915)) { 9571 ret = drm_vblank_init(&i915->drm, 9572 INTEL_NUM_PIPES(i915)); 9573 if (ret) 9574 return ret; 9575 } 9576 9577 intel_bios_init(i915); 9578 9579 ret = intel_vga_register(i915); 9580 if (ret) 9581 goto cleanup_bios; 9582 9583 /* FIXME: completely on the wrong abstraction layer */ 9584 intel_power_domains_init_hw(i915, false); 9585 9586 if (!HAS_DISPLAY(i915)) 9587 return 0; 9588 9589 intel_dmc_ucode_init(i915); 9590 9591 i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0); 9592 i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI | 9593 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE); 9594 9595 i915->window2_delay = 0; /* No DSB so no window2 delay */ 9596 9597 intel_mode_config_init(i915); 9598 9599 ret = intel_cdclk_init(i915); 9600 if (ret) 9601 goto cleanup_vga_client_pw_domain_dmc; 9602 9603 ret = intel_dbuf_init(i915); 9604 if (ret) 9605 goto cleanup_vga_client_pw_domain_dmc; 9606 9607 ret = intel_bw_init(i915); 9608 if (ret) 9609 goto cleanup_vga_client_pw_domain_dmc; 9610 9611 init_llist_head(&i915->atomic_helper.free_list); 9612 INIT_WORK(&i915->atomic_helper.free_work, 9613 intel_atomic_helper_free_state_worker); 9614 9615 intel_init_quirks(i915); 9616 9617 intel_fbc_init(i915); 9618 9619 return 0; 9620 9621 cleanup_vga_client_pw_domain_dmc: 9622 intel_dmc_ucode_fini(i915); 9623 intel_power_domains_driver_remove(i915); 9624 intel_vga_unregister(i915); 9625 cleanup_bios: 9626 intel_bios_driver_remove(i915); 9627 9628 return ret; 9629 } 9630 9631 /* part #2: call after irq install, but before gem init */ 9632 int intel_modeset_init_nogem(struct drm_i915_private *i915) 9633 { 9634 struct drm_device *dev = &i915->drm; 9635 enum pipe pipe; 9636 struct intel_crtc *crtc; 9637 int ret; 9638 9639 if (!HAS_DISPLAY(i915)) 9640 return 0; 9641 9642 intel_init_pm(i915); 9643 9644 intel_panel_sanitize_ssc(i915); 9645 9646 intel_pps_setup(i915); 9647 9648 intel_gmbus_setup(i915); 9649 9650 drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n", 9651 INTEL_NUM_PIPES(i915), 9652 INTEL_NUM_PIPES(i915) > 1 ? "s" : ""); 9653 9654 for_each_pipe(i915, pipe) { 9655 ret = intel_crtc_init(i915, pipe); 9656 if (ret) { 9657 intel_mode_config_cleanup(i915); 9658 return ret; 9659 } 9660 } 9661 9662 intel_plane_possible_crtcs_init(i915); 9663 intel_shared_dpll_init(i915); 9664 intel_fdi_pll_freq_update(i915); 9665 9666 intel_update_czclk(i915); 9667 intel_modeset_init_hw(i915); 9668 intel_dpll_update_ref_clks(i915); 9669 9670 intel_hdcp_component_init(i915); 9671 9672 if (i915->max_cdclk_freq == 0) 9673 intel_update_max_cdclk(i915); 9674 9675 /* 9676 * If the platform has HTI, we need to find out whether it has reserved 9677 * any display resources before we create our display outputs. 9678 */ 9679 if (INTEL_INFO(i915)->display.has_hti) 9680 i915->hti_state = intel_de_read(i915, HDPORT_STATE); 9681 9682 /* Just disable it once at startup */ 9683 intel_vga_disable(i915); 9684 intel_setup_outputs(i915); 9685 9686 drm_modeset_lock_all(dev); 9687 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx); 9688 intel_acpi_assign_connector_fwnodes(i915); 9689 drm_modeset_unlock_all(dev); 9690 9691 for_each_intel_crtc(dev, crtc) { 9692 if (!to_intel_crtc_state(crtc->base.state)->uapi.active) 9693 continue; 9694 intel_crtc_initial_plane_config(crtc); 9695 } 9696 9697 /* 9698 * Make sure hardware watermarks really match the state we read out. 9699 * Note that we need to do this after reconstructing the BIOS fb's 9700 * since the watermark calculation done here will use pstate->fb. 9701 */ 9702 if (!HAS_GMCH(i915)) 9703 sanitize_watermarks(i915); 9704 9705 return 0; 9706 } 9707 9708 /* part #3: call after gem init */ 9709 int intel_modeset_init(struct drm_i915_private *i915) 9710 { 9711 int ret; 9712 9713 if (!HAS_DISPLAY(i915)) 9714 return 0; 9715 9716 /* 9717 * Force all active planes to recompute their states. So that on 9718 * mode_setcrtc after probe, all the intel_plane_state variables 9719 * are already calculated and there is no assert_plane warnings 9720 * during bootup. 9721 */ 9722 ret = intel_initial_commit(&i915->drm); 9723 if (ret) 9724 drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret); 9725 9726 intel_overlay_setup(i915); 9727 9728 ret = intel_fbdev_init(&i915->drm); 9729 if (ret) 9730 return ret; 9731 9732 /* Only enable hotplug handling once the fbdev is fully set up. */ 9733 intel_hpd_init(i915); 9734 intel_hpd_poll_disable(i915); 9735 9736 intel_init_ipc(i915); 9737 9738 return 0; 9739 } 9740 9741 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 9742 { 9743 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 9744 /* 640x480@60Hz, ~25175 kHz */ 9745 struct dpll clock = { 9746 .m1 = 18, 9747 .m2 = 7, 9748 .p1 = 13, 9749 .p2 = 4, 9750 .n = 2, 9751 }; 9752 u32 dpll, fp; 9753 int i; 9754 9755 drm_WARN_ON(&dev_priv->drm, 9756 i9xx_calc_dpll_params(48000, &clock) != 25154); 9757 9758 drm_dbg_kms(&dev_priv->drm, 9759 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n", 9760 pipe_name(pipe), clock.vco, clock.dot); 9761 9762 fp = i9xx_dpll_compute_fp(&clock); 9763 dpll = DPLL_DVO_2X_MODE | 9764 DPLL_VGA_MODE_DIS | 9765 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | 9766 PLL_P2_DIVIDE_BY_4 | 9767 PLL_REF_INPUT_DREFCLK | 9768 DPLL_VCO_ENABLE; 9769 9770 intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16)); 9771 intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16)); 9772 intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16)); 9773 intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16)); 9774 intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16)); 9775 intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16)); 9776 intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1)); 9777 9778 intel_de_write(dev_priv, FP0(pipe), fp); 9779 intel_de_write(dev_priv, FP1(pipe), fp); 9780 9781 /* 9782 * Apparently we need to have VGA mode enabled prior to changing 9783 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 9784 * dividers, even though the register value does change. 9785 */ 9786 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); 9787 intel_de_write(dev_priv, DPLL(pipe), dpll); 9788 9789 /* Wait for the clocks to stabilize. */ 9790 intel_de_posting_read(dev_priv, DPLL(pipe)); 9791 udelay(150); 9792 9793 /* The pixel multiplier can only be updated once the 9794 * DPLL is enabled and the clocks are stable. 9795 * 9796 * So write it again. 9797 */ 9798 intel_de_write(dev_priv, DPLL(pipe), dpll); 9799 9800 /* We do this three times for luck */ 9801 for (i = 0; i < 3 ; i++) { 9802 intel_de_write(dev_priv, DPLL(pipe), dpll); 9803 intel_de_posting_read(dev_priv, DPLL(pipe)); 9804 udelay(150); /* wait for warmup */ 9805 } 9806 9807 intel_de_write(dev_priv, PIPECONF(pipe), PIPECONF_ENABLE); 9808 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 9809 9810 intel_wait_for_pipe_scanline_moving(crtc); 9811 } 9812 9813 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 9814 { 9815 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 9816 9817 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n", 9818 pipe_name(pipe)); 9819 9820 drm_WARN_ON(&dev_priv->drm, 9821 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE); 9822 drm_WARN_ON(&dev_priv->drm, 9823 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE); 9824 drm_WARN_ON(&dev_priv->drm, 9825 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE); 9826 drm_WARN_ON(&dev_priv->drm, 9827 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK); 9828 drm_WARN_ON(&dev_priv->drm, 9829 intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK); 9830 9831 intel_de_write(dev_priv, PIPECONF(pipe), 0); 9832 intel_de_posting_read(dev_priv, PIPECONF(pipe)); 9833 9834 intel_wait_for_pipe_scanline_stopped(crtc); 9835 9836 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); 9837 intel_de_posting_read(dev_priv, DPLL(pipe)); 9838 } 9839 9840 static void 9841 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv) 9842 { 9843 struct intel_crtc *crtc; 9844 9845 if (DISPLAY_VER(dev_priv) >= 4) 9846 return; 9847 9848 for_each_intel_crtc(&dev_priv->drm, crtc) { 9849 struct intel_plane *plane = 9850 to_intel_plane(crtc->base.primary); 9851 struct intel_crtc *plane_crtc; 9852 enum pipe pipe; 9853 9854 if (!plane->get_hw_state(plane, &pipe)) 9855 continue; 9856 9857 if (pipe == crtc->pipe) 9858 continue; 9859 9860 drm_dbg_kms(&dev_priv->drm, 9861 "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n", 9862 plane->base.base.id, plane->base.name); 9863 9864 plane_crtc = intel_crtc_for_pipe(dev_priv, pipe); 9865 intel_plane_disable_noatomic(plane_crtc, plane); 9866 } 9867 } 9868 9869 static bool intel_crtc_has_encoders(struct intel_crtc *crtc) 9870 { 9871 struct drm_device *dev = crtc->base.dev; 9872 struct intel_encoder *encoder; 9873 9874 for_each_encoder_on_crtc(dev, &crtc->base, encoder) 9875 return true; 9876 9877 return false; 9878 } 9879 9880 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) 9881 { 9882 struct drm_device *dev = encoder->base.dev; 9883 struct intel_connector *connector; 9884 9885 for_each_connector_on_encoder(dev, &encoder->base, connector) 9886 return connector; 9887 9888 return NULL; 9889 } 9890 9891 static void intel_sanitize_crtc(struct intel_crtc *crtc, 9892 struct drm_modeset_acquire_ctx *ctx) 9893 { 9894 struct drm_device *dev = crtc->base.dev; 9895 struct drm_i915_private *dev_priv = to_i915(dev); 9896 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); 9897 9898 if (crtc_state->hw.active) { 9899 struct intel_plane *plane; 9900 9901 /* Disable everything but the primary plane */ 9902 for_each_intel_plane_on_crtc(dev, crtc, plane) { 9903 const struct intel_plane_state *plane_state = 9904 to_intel_plane_state(plane->base.state); 9905 9906 if (plane_state->uapi.visible && 9907 plane->base.type != DRM_PLANE_TYPE_PRIMARY) 9908 intel_plane_disable_noatomic(crtc, plane); 9909 } 9910 9911 /* Disable any background color/etc. set by the BIOS */ 9912 intel_color_commit_noarm(crtc_state); 9913 intel_color_commit_arm(crtc_state); 9914 } 9915 9916 /* Adjust the state of the output pipe according to whether we 9917 * have active connectors/encoders. */ 9918 if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) && 9919 !intel_crtc_is_bigjoiner_slave(crtc_state)) 9920 intel_crtc_disable_noatomic(crtc, ctx); 9921 9922 if (crtc_state->hw.active || HAS_GMCH(dev_priv)) { 9923 /* 9924 * We start out with underrun reporting disabled to avoid races. 9925 * For correct bookkeeping mark this on active crtcs. 9926 * 9927 * Also on gmch platforms we dont have any hardware bits to 9928 * disable the underrun reporting. Which means we need to start 9929 * out with underrun reporting disabled also on inactive pipes, 9930 * since otherwise we'll complain about the garbage we read when 9931 * e.g. coming up after runtime pm. 9932 * 9933 * No protection against concurrent access is required - at 9934 * worst a fifo underrun happens which also sets this to false. 9935 */ 9936 crtc->cpu_fifo_underrun_disabled = true; 9937 /* 9938 * We track the PCH trancoder underrun reporting state 9939 * within the crtc. With crtc for pipe A housing the underrun 9940 * reporting state for PCH transcoder A, crtc for pipe B housing 9941 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, 9942 * and marking underrun reporting as disabled for the non-existing 9943 * PCH transcoders B and C would prevent enabling the south 9944 * error interrupt (see cpt_can_enable_serr_int()). 9945 */ 9946 if (intel_has_pch_trancoder(dev_priv, crtc->pipe)) 9947 crtc->pch_fifo_underrun_disabled = true; 9948 } 9949 } 9950 9951 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state) 9952 { 9953 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 9954 9955 /* 9956 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram 9957 * the hardware when a high res displays plugged in. DPLL P 9958 * divider is zero, and the pipe timings are bonkers. We'll 9959 * try to disable everything in that case. 9960 * 9961 * FIXME would be nice to be able to sanitize this state 9962 * without several WARNs, but for now let's take the easy 9963 * road. 9964 */ 9965 return IS_SANDYBRIDGE(dev_priv) && 9966 crtc_state->hw.active && 9967 crtc_state->shared_dpll && 9968 crtc_state->port_clock == 0; 9969 } 9970 9971 static void intel_sanitize_encoder(struct intel_encoder *encoder) 9972 { 9973 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 9974 struct intel_connector *connector; 9975 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 9976 struct intel_crtc_state *crtc_state = crtc ? 9977 to_intel_crtc_state(crtc->base.state) : NULL; 9978 9979 /* We need to check both for a crtc link (meaning that the 9980 * encoder is active and trying to read from a pipe) and the 9981 * pipe itself being active. */ 9982 bool has_active_crtc = crtc_state && 9983 crtc_state->hw.active; 9984 9985 if (crtc_state && has_bogus_dpll_config(crtc_state)) { 9986 drm_dbg_kms(&dev_priv->drm, 9987 "BIOS has misprogrammed the hardware. Disabling pipe %c\n", 9988 pipe_name(crtc->pipe)); 9989 has_active_crtc = false; 9990 } 9991 9992 connector = intel_encoder_find_connector(encoder); 9993 if (connector && !has_active_crtc) { 9994 drm_dbg_kms(&dev_priv->drm, 9995 "[ENCODER:%d:%s] has active connectors but no active pipe!\n", 9996 encoder->base.base.id, 9997 encoder->base.name); 9998 9999 /* Connector is active, but has no active pipe. This is 10000 * fallout from our resume register restoring. Disable 10001 * the encoder manually again. */ 10002 if (crtc_state) { 10003 struct drm_encoder *best_encoder; 10004 10005 drm_dbg_kms(&dev_priv->drm, 10006 "[ENCODER:%d:%s] manually disabled\n", 10007 encoder->base.base.id, 10008 encoder->base.name); 10009 10010 /* avoid oopsing in case the hooks consult best_encoder */ 10011 best_encoder = connector->base.state->best_encoder; 10012 connector->base.state->best_encoder = &encoder->base; 10013 10014 /* FIXME NULL atomic state passed! */ 10015 if (encoder->disable) 10016 encoder->disable(NULL, encoder, crtc_state, 10017 connector->base.state); 10018 if (encoder->post_disable) 10019 encoder->post_disable(NULL, encoder, crtc_state, 10020 connector->base.state); 10021 10022 connector->base.state->best_encoder = best_encoder; 10023 } 10024 encoder->base.crtc = NULL; 10025 10026 /* Inconsistent output/port/pipe state happens presumably due to 10027 * a bug in one of the get_hw_state functions. Or someplace else 10028 * in our code, like the register restore mess on resume. Clamp 10029 * things to off as a safer default. */ 10030 10031 connector->base.dpms = DRM_MODE_DPMS_OFF; 10032 connector->base.encoder = NULL; 10033 } 10034 10035 /* notify opregion of the sanitized encoder state */ 10036 intel_opregion_notify_encoder(encoder, connector && has_active_crtc); 10037 10038 if (HAS_DDI(dev_priv)) 10039 intel_ddi_sanitize_encoder_pll_mapping(encoder); 10040 } 10041 10042 /* FIXME read out full plane state for all planes */ 10043 static void readout_plane_state(struct drm_i915_private *dev_priv) 10044 { 10045 struct intel_plane *plane; 10046 struct intel_crtc *crtc; 10047 10048 for_each_intel_plane(&dev_priv->drm, plane) { 10049 struct intel_plane_state *plane_state = 10050 to_intel_plane_state(plane->base.state); 10051 struct intel_crtc_state *crtc_state; 10052 enum pipe pipe = PIPE_A; 10053 bool visible; 10054 10055 visible = plane->get_hw_state(plane, &pipe); 10056 10057 crtc = intel_crtc_for_pipe(dev_priv, pipe); 10058 crtc_state = to_intel_crtc_state(crtc->base.state); 10059 10060 intel_set_plane_visible(crtc_state, plane_state, visible); 10061 10062 drm_dbg_kms(&dev_priv->drm, 10063 "[PLANE:%d:%s] hw state readout: %s, pipe %c\n", 10064 plane->base.base.id, plane->base.name, 10065 str_enabled_disabled(visible), pipe_name(pipe)); 10066 } 10067 10068 for_each_intel_crtc(&dev_priv->drm, crtc) { 10069 struct intel_crtc_state *crtc_state = 10070 to_intel_crtc_state(crtc->base.state); 10071 10072 fixup_plane_bitmasks(crtc_state); 10073 } 10074 } 10075 10076 static void intel_modeset_readout_hw_state(struct drm_device *dev) 10077 { 10078 struct drm_i915_private *dev_priv = to_i915(dev); 10079 struct intel_cdclk_state *cdclk_state = 10080 to_intel_cdclk_state(dev_priv->cdclk.obj.state); 10081 struct intel_dbuf_state *dbuf_state = 10082 to_intel_dbuf_state(dev_priv->dbuf.obj.state); 10083 enum pipe pipe; 10084 struct intel_crtc *crtc; 10085 struct intel_encoder *encoder; 10086 struct intel_connector *connector; 10087 struct drm_connector_list_iter conn_iter; 10088 u8 active_pipes = 0; 10089 10090 for_each_intel_crtc(dev, crtc) { 10091 struct intel_crtc_state *crtc_state = 10092 to_intel_crtc_state(crtc->base.state); 10093 10094 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi); 10095 intel_crtc_free_hw_state(crtc_state); 10096 intel_crtc_state_reset(crtc_state, crtc); 10097 10098 intel_crtc_get_pipe_config(crtc_state); 10099 10100 crtc_state->hw.enable = crtc_state->hw.active; 10101 10102 crtc->base.enabled = crtc_state->hw.enable; 10103 crtc->active = crtc_state->hw.active; 10104 10105 if (crtc_state->hw.active) 10106 active_pipes |= BIT(crtc->pipe); 10107 10108 drm_dbg_kms(&dev_priv->drm, 10109 "[CRTC:%d:%s] hw state readout: %s\n", 10110 crtc->base.base.id, crtc->base.name, 10111 str_enabled_disabled(crtc_state->hw.active)); 10112 } 10113 10114 cdclk_state->active_pipes = dbuf_state->active_pipes = active_pipes; 10115 10116 readout_plane_state(dev_priv); 10117 10118 for_each_intel_encoder(dev, encoder) { 10119 struct intel_crtc_state *crtc_state = NULL; 10120 10121 pipe = 0; 10122 10123 if (encoder->get_hw_state(encoder, &pipe)) { 10124 crtc = intel_crtc_for_pipe(dev_priv, pipe); 10125 crtc_state = to_intel_crtc_state(crtc->base.state); 10126 10127 encoder->base.crtc = &crtc->base; 10128 intel_encoder_get_config(encoder, crtc_state); 10129 10130 /* read out to slave crtc as well for bigjoiner */ 10131 if (crtc_state->bigjoiner_pipes) { 10132 struct intel_crtc *slave_crtc; 10133 10134 /* encoder should read be linked to bigjoiner master */ 10135 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 10136 10137 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc, 10138 intel_crtc_bigjoiner_slave_pipes(crtc_state)) { 10139 struct intel_crtc_state *slave_crtc_state; 10140 10141 slave_crtc_state = to_intel_crtc_state(slave_crtc->base.state); 10142 intel_encoder_get_config(encoder, slave_crtc_state); 10143 } 10144 } 10145 } else { 10146 encoder->base.crtc = NULL; 10147 } 10148 10149 if (encoder->sync_state) 10150 encoder->sync_state(encoder, crtc_state); 10151 10152 drm_dbg_kms(&dev_priv->drm, 10153 "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", 10154 encoder->base.base.id, encoder->base.name, 10155 str_enabled_disabled(encoder->base.crtc), 10156 pipe_name(pipe)); 10157 } 10158 10159 intel_dpll_readout_hw_state(dev_priv); 10160 10161 drm_connector_list_iter_begin(dev, &conn_iter); 10162 for_each_intel_connector_iter(connector, &conn_iter) { 10163 if (connector->get_hw_state(connector)) { 10164 struct intel_crtc_state *crtc_state; 10165 struct intel_crtc *crtc; 10166 10167 connector->base.dpms = DRM_MODE_DPMS_ON; 10168 10169 encoder = intel_attached_encoder(connector); 10170 connector->base.encoder = &encoder->base; 10171 10172 crtc = to_intel_crtc(encoder->base.crtc); 10173 crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL; 10174 10175 if (crtc_state && crtc_state->hw.active) { 10176 /* 10177 * This has to be done during hardware readout 10178 * because anything calling .crtc_disable may 10179 * rely on the connector_mask being accurate. 10180 */ 10181 crtc_state->uapi.connector_mask |= 10182 drm_connector_mask(&connector->base); 10183 crtc_state->uapi.encoder_mask |= 10184 drm_encoder_mask(&encoder->base); 10185 } 10186 } else { 10187 connector->base.dpms = DRM_MODE_DPMS_OFF; 10188 connector->base.encoder = NULL; 10189 } 10190 drm_dbg_kms(&dev_priv->drm, 10191 "[CONNECTOR:%d:%s] hw state readout: %s\n", 10192 connector->base.base.id, connector->base.name, 10193 str_enabled_disabled(connector->base.encoder)); 10194 } 10195 drm_connector_list_iter_end(&conn_iter); 10196 10197 for_each_intel_crtc(dev, crtc) { 10198 struct intel_bw_state *bw_state = 10199 to_intel_bw_state(dev_priv->bw_obj.state); 10200 struct intel_crtc_state *crtc_state = 10201 to_intel_crtc_state(crtc->base.state); 10202 struct intel_plane *plane; 10203 int min_cdclk = 0; 10204 10205 if (crtc_state->hw.active) { 10206 /* 10207 * The initial mode needs to be set in order to keep 10208 * the atomic core happy. It wants a valid mode if the 10209 * crtc's enabled, so we do the above call. 10210 * 10211 * But we don't set all the derived state fully, hence 10212 * set a flag to indicate that a full recalculation is 10213 * needed on the next commit. 10214 */ 10215 crtc_state->inherited = true; 10216 10217 intel_crtc_update_active_timings(crtc_state); 10218 10219 intel_crtc_copy_hw_to_uapi_state(crtc_state); 10220 } 10221 10222 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 10223 const struct intel_plane_state *plane_state = 10224 to_intel_plane_state(plane->base.state); 10225 10226 /* 10227 * FIXME don't have the fb yet, so can't 10228 * use intel_plane_data_rate() :( 10229 */ 10230 if (plane_state->uapi.visible) 10231 crtc_state->data_rate[plane->id] = 10232 4 * crtc_state->pixel_rate; 10233 /* 10234 * FIXME don't have the fb yet, so can't 10235 * use plane->min_cdclk() :( 10236 */ 10237 if (plane_state->uapi.visible && plane->min_cdclk) { 10238 if (crtc_state->double_wide || DISPLAY_VER(dev_priv) >= 10) 10239 crtc_state->min_cdclk[plane->id] = 10240 DIV_ROUND_UP(crtc_state->pixel_rate, 2); 10241 else 10242 crtc_state->min_cdclk[plane->id] = 10243 crtc_state->pixel_rate; 10244 } 10245 drm_dbg_kms(&dev_priv->drm, 10246 "[PLANE:%d:%s] min_cdclk %d kHz\n", 10247 plane->base.base.id, plane->base.name, 10248 crtc_state->min_cdclk[plane->id]); 10249 } 10250 10251 if (crtc_state->hw.active) { 10252 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); 10253 if (drm_WARN_ON(dev, min_cdclk < 0)) 10254 min_cdclk = 0; 10255 } 10256 10257 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; 10258 cdclk_state->min_voltage_level[crtc->pipe] = 10259 crtc_state->min_voltage_level; 10260 10261 intel_bw_crtc_update(bw_state, crtc_state); 10262 10263 intel_pipe_config_sanity_check(dev_priv, crtc_state); 10264 } 10265 } 10266 10267 static void 10268 get_encoder_power_domains(struct drm_i915_private *dev_priv) 10269 { 10270 struct intel_encoder *encoder; 10271 10272 for_each_intel_encoder(&dev_priv->drm, encoder) { 10273 struct intel_crtc_state *crtc_state; 10274 10275 if (!encoder->get_power_domains) 10276 continue; 10277 10278 /* 10279 * MST-primary and inactive encoders don't have a crtc state 10280 * and neither of these require any power domain references. 10281 */ 10282 if (!encoder->base.crtc) 10283 continue; 10284 10285 crtc_state = to_intel_crtc_state(encoder->base.crtc->state); 10286 encoder->get_power_domains(encoder, crtc_state); 10287 } 10288 } 10289 10290 static void intel_early_display_was(struct drm_i915_private *dev_priv) 10291 { 10292 /* 10293 * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl 10294 * Also known as Wa_14010480278. 10295 */ 10296 if (IS_DISPLAY_VER(dev_priv, 10, 12)) 10297 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0, 10298 intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS); 10299 10300 if (IS_HASWELL(dev_priv)) { 10301 /* 10302 * WaRsPkgCStateDisplayPMReq:hsw 10303 * System hang if this isn't done before disabling all planes! 10304 */ 10305 intel_de_write(dev_priv, CHICKEN_PAR1_1, 10306 intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); 10307 } 10308 10309 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) { 10310 /* Display WA #1142:kbl,cfl,cml */ 10311 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 10312 KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22); 10313 intel_de_rmw(dev_priv, CHICKEN_MISC_2, 10314 KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14, 10315 KBL_ARB_FILL_SPARE_14); 10316 } 10317 } 10318 10319 10320 /* Scan out the current hw modeset state, 10321 * and sanitizes it to the current state 10322 */ 10323 static void 10324 intel_modeset_setup_hw_state(struct drm_device *dev, 10325 struct drm_modeset_acquire_ctx *ctx) 10326 { 10327 struct drm_i915_private *dev_priv = to_i915(dev); 10328 struct intel_encoder *encoder; 10329 struct intel_crtc *crtc; 10330 intel_wakeref_t wakeref; 10331 10332 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 10333 10334 intel_early_display_was(dev_priv); 10335 intel_modeset_readout_hw_state(dev); 10336 10337 /* HW state is read out, now we need to sanitize this mess. */ 10338 get_encoder_power_domains(dev_priv); 10339 10340 intel_pch_sanitize(dev_priv); 10341 10342 /* 10343 * intel_sanitize_plane_mapping() may need to do vblank 10344 * waits, so we need vblank interrupts restored beforehand. 10345 */ 10346 for_each_intel_crtc(&dev_priv->drm, crtc) { 10347 struct intel_crtc_state *crtc_state = 10348 to_intel_crtc_state(crtc->base.state); 10349 10350 drm_crtc_vblank_reset(&crtc->base); 10351 10352 if (crtc_state->hw.active) 10353 intel_crtc_vblank_on(crtc_state); 10354 } 10355 10356 intel_fbc_sanitize(dev_priv); 10357 10358 intel_sanitize_plane_mapping(dev_priv); 10359 10360 for_each_intel_encoder(dev, encoder) 10361 intel_sanitize_encoder(encoder); 10362 10363 for_each_intel_crtc(&dev_priv->drm, crtc) { 10364 struct intel_crtc_state *crtc_state = 10365 to_intel_crtc_state(crtc->base.state); 10366 10367 intel_sanitize_crtc(crtc, ctx); 10368 intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]"); 10369 } 10370 10371 intel_modeset_update_connector_atomic_state(dev); 10372 10373 intel_dpll_sanitize_state(dev_priv); 10374 10375 if (IS_G4X(dev_priv)) { 10376 g4x_wm_get_hw_state(dev_priv); 10377 g4x_wm_sanitize(dev_priv); 10378 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 10379 vlv_wm_get_hw_state(dev_priv); 10380 vlv_wm_sanitize(dev_priv); 10381 } else if (DISPLAY_VER(dev_priv) >= 9) { 10382 skl_wm_get_hw_state(dev_priv); 10383 skl_wm_sanitize(dev_priv); 10384 } else if (HAS_PCH_SPLIT(dev_priv)) { 10385 ilk_wm_get_hw_state(dev_priv); 10386 } 10387 10388 for_each_intel_crtc(dev, crtc) { 10389 struct intel_crtc_state *crtc_state = 10390 to_intel_crtc_state(crtc->base.state); 10391 struct intel_power_domain_mask put_domains; 10392 10393 modeset_get_crtc_power_domains(crtc_state, &put_domains); 10394 if (drm_WARN_ON(dev, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM))) 10395 modeset_put_crtc_power_domains(crtc, &put_domains); 10396 } 10397 10398 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref); 10399 10400 intel_power_domains_sanitize_state(dev_priv); 10401 } 10402 10403 void intel_display_resume(struct drm_device *dev) 10404 { 10405 struct drm_i915_private *dev_priv = to_i915(dev); 10406 struct drm_atomic_state *state = dev_priv->modeset_restore_state; 10407 struct drm_modeset_acquire_ctx ctx; 10408 int ret; 10409 10410 if (!HAS_DISPLAY(dev_priv)) 10411 return; 10412 10413 dev_priv->modeset_restore_state = NULL; 10414 if (state) 10415 state->acquire_ctx = &ctx; 10416 10417 drm_modeset_acquire_init(&ctx, 0); 10418 10419 while (1) { 10420 ret = drm_modeset_lock_all_ctx(dev, &ctx); 10421 if (ret != -EDEADLK) 10422 break; 10423 10424 drm_modeset_backoff(&ctx); 10425 } 10426 10427 if (!ret) 10428 ret = __intel_display_resume(dev, state, &ctx); 10429 10430 intel_enable_ipc(dev_priv); 10431 drm_modeset_drop_locks(&ctx); 10432 drm_modeset_acquire_fini(&ctx); 10433 10434 if (ret) 10435 drm_err(&dev_priv->drm, 10436 "Restoring old state failed with %i\n", ret); 10437 if (state) 10438 drm_atomic_state_put(state); 10439 } 10440 10441 static void intel_hpd_poll_fini(struct drm_i915_private *i915) 10442 { 10443 struct intel_connector *connector; 10444 struct drm_connector_list_iter conn_iter; 10445 10446 /* Kill all the work that may have been queued by hpd. */ 10447 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 10448 for_each_intel_connector_iter(connector, &conn_iter) { 10449 if (connector->modeset_retry_work.func) 10450 cancel_work_sync(&connector->modeset_retry_work); 10451 if (connector->hdcp.shim) { 10452 cancel_delayed_work_sync(&connector->hdcp.check_work); 10453 cancel_work_sync(&connector->hdcp.prop_work); 10454 } 10455 } 10456 drm_connector_list_iter_end(&conn_iter); 10457 } 10458 10459 /* part #1: call before irq uninstall */ 10460 void intel_modeset_driver_remove(struct drm_i915_private *i915) 10461 { 10462 if (!HAS_DISPLAY(i915)) 10463 return; 10464 10465 flush_workqueue(i915->flip_wq); 10466 flush_workqueue(i915->modeset_wq); 10467 10468 flush_work(&i915->atomic_helper.free_work); 10469 drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list)); 10470 } 10471 10472 /* part #2: call after irq uninstall */ 10473 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915) 10474 { 10475 if (!HAS_DISPLAY(i915)) 10476 return; 10477 10478 /* 10479 * Due to the hpd irq storm handling the hotplug work can re-arm the 10480 * poll handlers. Hence disable polling after hpd handling is shut down. 10481 */ 10482 intel_hpd_poll_fini(i915); 10483 10484 /* 10485 * MST topology needs to be suspended so we don't have any calls to 10486 * fbdev after it's finalized. MST will be destroyed later as part of 10487 * drm_mode_config_cleanup() 10488 */ 10489 intel_dp_mst_suspend(i915); 10490 10491 /* poll work can call into fbdev, hence clean that up afterwards */ 10492 intel_fbdev_fini(i915); 10493 10494 intel_unregister_dsm_handler(); 10495 10496 /* flush any delayed tasks or pending work */ 10497 flush_scheduled_work(); 10498 10499 intel_hdcp_component_fini(i915); 10500 10501 intel_mode_config_cleanup(i915); 10502 10503 intel_overlay_cleanup(i915); 10504 10505 intel_gmbus_teardown(i915); 10506 10507 destroy_workqueue(i915->flip_wq); 10508 destroy_workqueue(i915->modeset_wq); 10509 10510 intel_fbc_cleanup(i915); 10511 } 10512 10513 /* part #3: call after gem init */ 10514 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915) 10515 { 10516 intel_dmc_ucode_fini(i915); 10517 10518 intel_power_domains_driver_remove(i915); 10519 10520 intel_vga_unregister(i915); 10521 10522 intel_bios_driver_remove(i915); 10523 } 10524 10525 bool intel_modeset_probe_defer(struct pci_dev *pdev) 10526 { 10527 struct drm_privacy_screen *privacy_screen; 10528 10529 /* 10530 * apple-gmux is needed on dual GPU MacBook Pro 10531 * to probe the panel if we're the inactive GPU. 10532 */ 10533 if (vga_switcheroo_client_probe_defer(pdev)) 10534 return true; 10535 10536 /* If the LCD panel has a privacy-screen, wait for it */ 10537 privacy_screen = drm_privacy_screen_get(&pdev->dev, NULL); 10538 if (IS_ERR(privacy_screen) && PTR_ERR(privacy_screen) == -EPROBE_DEFER) 10539 return true; 10540 10541 drm_privacy_screen_put(privacy_screen); 10542 10543 return false; 10544 } 10545 10546 void intel_display_driver_register(struct drm_i915_private *i915) 10547 { 10548 if (!HAS_DISPLAY(i915)) 10549 return; 10550 10551 intel_display_debugfs_register(i915); 10552 10553 /* Must be done after probing outputs */ 10554 intel_opregion_register(i915); 10555 acpi_video_register(); 10556 10557 intel_audio_init(i915); 10558 10559 /* 10560 * Some ports require correctly set-up hpd registers for 10561 * detection to work properly (leading to ghost connected 10562 * connector status), e.g. VGA on gm45. Hence we can only set 10563 * up the initial fbdev config after hpd irqs are fully 10564 * enabled. We do it last so that the async config cannot run 10565 * before the connectors are registered. 10566 */ 10567 intel_fbdev_initial_config_async(&i915->drm); 10568 10569 /* 10570 * We need to coordinate the hotplugs with the asynchronous 10571 * fbdev configuration, for which we use the 10572 * fbdev->async_cookie. 10573 */ 10574 drm_kms_helper_poll_init(&i915->drm); 10575 } 10576 10577 void intel_display_driver_unregister(struct drm_i915_private *i915) 10578 { 10579 if (!HAS_DISPLAY(i915)) 10580 return; 10581 10582 intel_fbdev_unregister(i915); 10583 intel_audio_deinit(i915); 10584 10585 /* 10586 * After flushing the fbdev (incl. a late async config which 10587 * will have delayed queuing of a hotplug event), then flush 10588 * the hotplug events. 10589 */ 10590 drm_kms_helper_poll_fini(&i915->drm); 10591 drm_atomic_helper_shutdown(&i915->drm); 10592 10593 acpi_video_unregister(); 10594 intel_opregion_unregister(i915); 10595 } 10596 10597 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915) 10598 { 10599 return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915); 10600 } 10601