1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <linux/dma-resv.h> 28 #include <linux/i2c.h> 29 #include <linux/input.h> 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/slab.h> 33 #include <linux/string_helpers.h> 34 #include <linux/vga_switcheroo.h> 35 #include <acpi/video.h> 36 37 #include <drm/display/drm_dp_helper.h> 38 #include <drm/drm_atomic.h> 39 #include <drm/drm_atomic_helper.h> 40 #include <drm/drm_atomic_uapi.h> 41 #include <drm/drm_damage_helper.h> 42 #include <drm/drm_edid.h> 43 #include <drm/drm_fourcc.h> 44 #include <drm/drm_privacy_screen_consumer.h> 45 #include <drm/drm_probe_helper.h> 46 #include <drm/drm_rect.h> 47 48 #include "gem/i915_gem_lmem.h" 49 #include "gem/i915_gem_object.h" 50 51 #include "g4x_dp.h" 52 #include "g4x_hdmi.h" 53 #include "hsw_ips.h" 54 #include "i915_drv.h" 55 #include "i915_reg.h" 56 #include "i915_utils.h" 57 #include "i9xx_plane.h" 58 #include "i9xx_wm.h" 59 #include "icl_dsi.h" 60 #include "intel_acpi.h" 61 #include "intel_atomic.h" 62 #include "intel_atomic_plane.h" 63 #include "intel_audio.h" 64 #include "intel_bw.h" 65 #include "intel_cdclk.h" 66 #include "intel_color.h" 67 #include "intel_crt.h" 68 #include "intel_crtc.h" 69 #include "intel_crtc_state_dump.h" 70 #include "intel_ddi.h" 71 #include "intel_de.h" 72 #include "intel_display_debugfs.h" 73 #include "intel_display_power.h" 74 #include "intel_display_types.h" 75 #include "intel_dmc.h" 76 #include "intel_dp.h" 77 #include "intel_dp_link_training.h" 78 #include "intel_dp_mst.h" 79 #include "intel_dpio_phy.h" 80 #include "intel_dpll.h" 81 #include "intel_dpll_mgr.h" 82 #include "intel_dpt.h" 83 #include "intel_drrs.h" 84 #include "intel_dsi.h" 85 #include "intel_dvo.h" 86 #include "intel_fb.h" 87 #include "intel_fbc.h" 88 #include "intel_fbdev.h" 89 #include "intel_fdi.h" 90 #include "intel_fifo_underrun.h" 91 #include "intel_frontbuffer.h" 92 #include "intel_gmbus.h" 93 #include "intel_hdcp.h" 94 #include "intel_hdmi.h" 95 #include "intel_hotplug.h" 96 #include "intel_hti.h" 97 #include "intel_lvds.h" 98 #include "intel_lvds_regs.h" 99 #include "intel_modeset_setup.h" 100 #include "intel_modeset_verify.h" 101 #include "intel_overlay.h" 102 #include "intel_panel.h" 103 #include "intel_pch_display.h" 104 #include "intel_pch_refclk.h" 105 #include "intel_pcode.h" 106 #include "intel_pipe_crc.h" 107 #include "intel_plane_initial.h" 108 #include "intel_pm.h" 109 #include "intel_pps.h" 110 #include "intel_psr.h" 111 #include "intel_quirks.h" 112 #include "intel_sdvo.h" 113 #include "intel_snps_phy.h" 114 #include "intel_sprite.h" 115 #include "intel_tc.h" 116 #include "intel_tv.h" 117 #include "intel_vblank.h" 118 #include "intel_vdsc.h" 119 #include "intel_vga.h" 120 #include "intel_vrr.h" 121 #include "intel_wm.h" 122 #include "skl_scaler.h" 123 #include "skl_universal_plane.h" 124 #include "skl_watermark.h" 125 #include "vlv_dsi.h" 126 #include "vlv_dsi_pll.h" 127 #include "vlv_dsi_regs.h" 128 #include "vlv_sideband.h" 129 130 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state); 131 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state); 132 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state); 133 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state); 134 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state); 135 136 /* returns HPLL frequency in kHz */ 137 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) 138 { 139 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; 140 141 /* Obtain SKU information */ 142 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & 143 CCK_FUSE_HPLL_FREQ_MASK; 144 145 return vco_freq[hpll_freq] * 1000; 146 } 147 148 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 149 const char *name, u32 reg, int ref_freq) 150 { 151 u32 val; 152 int divider; 153 154 val = vlv_cck_read(dev_priv, reg); 155 divider = val & CCK_FREQUENCY_VALUES; 156 157 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != 158 (divider << CCK_FREQUENCY_STATUS_SHIFT), 159 "%s change in progress\n", name); 160 161 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); 162 } 163 164 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 165 const char *name, u32 reg) 166 { 167 int hpll; 168 169 vlv_cck_get(dev_priv); 170 171 if (dev_priv->hpll_freq == 0) 172 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); 173 174 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); 175 176 vlv_cck_put(dev_priv); 177 178 return hpll; 179 } 180 181 static void intel_update_czclk(struct drm_i915_private *dev_priv) 182 { 183 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) 184 return; 185 186 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", 187 CCK_CZ_CLOCK_CONTROL); 188 189 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", 190 dev_priv->czclk_freq); 191 } 192 193 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state) 194 { 195 return (crtc_state->active_planes & 196 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0; 197 } 198 199 /* WA Display #0827: Gen9:all */ 200 static void 201 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) 202 { 203 if (enable) 204 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 205 0, DUPS1_GATING_DIS | DUPS2_GATING_DIS); 206 else 207 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 208 DUPS1_GATING_DIS | DUPS2_GATING_DIS, 0); 209 } 210 211 /* Wa_2006604312:icl,ehl */ 212 static void 213 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 214 bool enable) 215 { 216 if (enable) 217 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 0, DPFR_GATING_DIS); 218 else 219 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), DPFR_GATING_DIS, 0); 220 } 221 222 /* Wa_1604331009:icl,jsl,ehl */ 223 static void 224 icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 225 bool enable) 226 { 227 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), CURSOR_GATING_DIS, 228 enable ? CURSOR_GATING_DIS : 0); 229 } 230 231 static bool 232 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state) 233 { 234 return crtc_state->master_transcoder != INVALID_TRANSCODER; 235 } 236 237 static bool 238 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state) 239 { 240 return crtc_state->sync_mode_slaves_mask != 0; 241 } 242 243 bool 244 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state) 245 { 246 return is_trans_port_sync_master(crtc_state) || 247 is_trans_port_sync_slave(crtc_state); 248 } 249 250 static enum pipe bigjoiner_master_pipe(const struct intel_crtc_state *crtc_state) 251 { 252 return ffs(crtc_state->bigjoiner_pipes) - 1; 253 } 254 255 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state) 256 { 257 if (crtc_state->bigjoiner_pipes) 258 return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state)); 259 else 260 return 0; 261 } 262 263 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state) 264 { 265 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 266 267 return crtc_state->bigjoiner_pipes && 268 crtc->pipe != bigjoiner_master_pipe(crtc_state); 269 } 270 271 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state) 272 { 273 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 274 275 return crtc_state->bigjoiner_pipes && 276 crtc->pipe == bigjoiner_master_pipe(crtc_state); 277 } 278 279 static int intel_bigjoiner_num_pipes(const struct intel_crtc_state *crtc_state) 280 { 281 return hweight8(crtc_state->bigjoiner_pipes); 282 } 283 284 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state) 285 { 286 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 287 288 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 289 return intel_crtc_for_pipe(i915, bigjoiner_master_pipe(crtc_state)); 290 else 291 return to_intel_crtc(crtc_state->uapi.crtc); 292 } 293 294 static void 295 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) 296 { 297 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 298 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 299 300 if (DISPLAY_VER(dev_priv) >= 4) { 301 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 302 303 /* Wait for the Pipe State to go off */ 304 if (intel_de_wait_for_clear(dev_priv, TRANSCONF(cpu_transcoder), 305 TRANSCONF_STATE_ENABLE, 100)) 306 drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n"); 307 } else { 308 intel_wait_for_pipe_scanline_stopped(crtc); 309 } 310 } 311 312 void assert_transcoder(struct drm_i915_private *dev_priv, 313 enum transcoder cpu_transcoder, bool state) 314 { 315 bool cur_state; 316 enum intel_display_power_domain power_domain; 317 intel_wakeref_t wakeref; 318 319 /* we keep both pipes enabled on 830 */ 320 if (IS_I830(dev_priv)) 321 state = true; 322 323 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 324 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 325 if (wakeref) { 326 u32 val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)); 327 cur_state = !!(val & TRANSCONF_ENABLE); 328 329 intel_display_power_put(dev_priv, power_domain, wakeref); 330 } else { 331 cur_state = false; 332 } 333 334 I915_STATE_WARN(cur_state != state, 335 "transcoder %s assertion failure (expected %s, current %s)\n", 336 transcoder_name(cpu_transcoder), 337 str_on_off(state), str_on_off(cur_state)); 338 } 339 340 static void assert_plane(struct intel_plane *plane, bool state) 341 { 342 enum pipe pipe; 343 bool cur_state; 344 345 cur_state = plane->get_hw_state(plane, &pipe); 346 347 I915_STATE_WARN(cur_state != state, 348 "%s assertion failure (expected %s, current %s)\n", 349 plane->base.name, str_on_off(state), 350 str_on_off(cur_state)); 351 } 352 353 #define assert_plane_enabled(p) assert_plane(p, true) 354 #define assert_plane_disabled(p) assert_plane(p, false) 355 356 static void assert_planes_disabled(struct intel_crtc *crtc) 357 { 358 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 359 struct intel_plane *plane; 360 361 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) 362 assert_plane_disabled(plane); 363 } 364 365 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 366 struct intel_digital_port *dig_port, 367 unsigned int expected_mask) 368 { 369 u32 port_mask; 370 i915_reg_t dpll_reg; 371 372 switch (dig_port->base.port) { 373 default: 374 MISSING_CASE(dig_port->base.port); 375 fallthrough; 376 case PORT_B: 377 port_mask = DPLL_PORTB_READY_MASK; 378 dpll_reg = DPLL(0); 379 break; 380 case PORT_C: 381 port_mask = DPLL_PORTC_READY_MASK; 382 dpll_reg = DPLL(0); 383 expected_mask <<= 4; 384 break; 385 case PORT_D: 386 port_mask = DPLL_PORTD_READY_MASK; 387 dpll_reg = DPIO_PHY_STATUS; 388 break; 389 } 390 391 if (intel_de_wait_for_register(dev_priv, dpll_reg, 392 port_mask, expected_mask, 1000)) 393 drm_WARN(&dev_priv->drm, 1, 394 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", 395 dig_port->base.base.base.id, dig_port->base.base.name, 396 intel_de_read(dev_priv, dpll_reg) & port_mask, 397 expected_mask); 398 } 399 400 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) 401 { 402 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 403 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 404 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 405 enum pipe pipe = crtc->pipe; 406 i915_reg_t reg; 407 u32 val; 408 409 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe)); 410 411 assert_planes_disabled(crtc); 412 413 /* 414 * A pipe without a PLL won't actually be able to drive bits from 415 * a plane. On ILK+ the pipe PLLs are integrated, so we don't 416 * need the check. 417 */ 418 if (HAS_GMCH(dev_priv)) { 419 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI)) 420 assert_dsi_pll_enabled(dev_priv); 421 else 422 assert_pll_enabled(dev_priv, pipe); 423 } else { 424 if (new_crtc_state->has_pch_encoder) { 425 /* if driving the PCH, we need FDI enabled */ 426 assert_fdi_rx_pll_enabled(dev_priv, 427 intel_crtc_pch_transcoder(crtc)); 428 assert_fdi_tx_pll_enabled(dev_priv, 429 (enum pipe) cpu_transcoder); 430 } 431 /* FIXME: assert CPU port conditions for SNB+ */ 432 } 433 434 /* Wa_22012358565:adl-p */ 435 if (DISPLAY_VER(dev_priv) == 13) 436 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe), 437 0, PIPE_ARB_USE_PROG_SLOTS); 438 439 reg = TRANSCONF(cpu_transcoder); 440 val = intel_de_read(dev_priv, reg); 441 if (val & TRANSCONF_ENABLE) { 442 /* we keep both pipes enabled on 830 */ 443 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv)); 444 return; 445 } 446 447 intel_de_write(dev_priv, reg, val | TRANSCONF_ENABLE); 448 intel_de_posting_read(dev_priv, reg); 449 450 /* 451 * Until the pipe starts PIPEDSL reads will return a stale value, 452 * which causes an apparent vblank timestamp jump when PIPEDSL 453 * resets to its proper value. That also messes up the frame count 454 * when it's derived from the timestamps. So let's wait for the 455 * pipe to start properly before we call drm_crtc_vblank_on() 456 */ 457 if (intel_crtc_max_vblank_count(new_crtc_state) == 0) 458 intel_wait_for_pipe_scanline_moving(crtc); 459 } 460 461 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) 462 { 463 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 464 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 465 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 466 enum pipe pipe = crtc->pipe; 467 i915_reg_t reg; 468 u32 val; 469 470 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe)); 471 472 /* 473 * Make sure planes won't keep trying to pump pixels to us, 474 * or we might hang the display. 475 */ 476 assert_planes_disabled(crtc); 477 478 reg = TRANSCONF(cpu_transcoder); 479 val = intel_de_read(dev_priv, reg); 480 if ((val & TRANSCONF_ENABLE) == 0) 481 return; 482 483 /* 484 * Double wide has implications for planes 485 * so best keep it disabled when not needed. 486 */ 487 if (old_crtc_state->double_wide) 488 val &= ~TRANSCONF_DOUBLE_WIDE; 489 490 /* Don't disable pipe or pipe PLLs if needed */ 491 if (!IS_I830(dev_priv)) 492 val &= ~TRANSCONF_ENABLE; 493 494 if (DISPLAY_VER(dev_priv) >= 14) 495 intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder), 496 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 497 else if (DISPLAY_VER(dev_priv) >= 12) 498 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 499 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 500 501 intel_de_write(dev_priv, reg, val); 502 if ((val & TRANSCONF_ENABLE) == 0) 503 intel_wait_for_pipe_off(old_crtc_state); 504 } 505 506 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) 507 { 508 unsigned int size = 0; 509 int i; 510 511 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) 512 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width; 513 514 return size; 515 } 516 517 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info) 518 { 519 unsigned int size = 0; 520 int i; 521 522 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) { 523 unsigned int plane_size; 524 525 if (rem_info->plane[i].linear) 526 plane_size = rem_info->plane[i].size; 527 else 528 plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height; 529 530 if (plane_size == 0) 531 continue; 532 533 if (rem_info->plane_alignment) 534 size = ALIGN(size, rem_info->plane_alignment); 535 536 size += plane_size; 537 } 538 539 return size; 540 } 541 542 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) 543 { 544 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 545 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 546 547 return DISPLAY_VER(dev_priv) < 4 || 548 (plane->fbc && 549 plane_state->view.gtt.type == I915_GTT_VIEW_NORMAL); 550 } 551 552 /* 553 * Convert the x/y offsets into a linear offset. 554 * Only valid with 0/180 degree rotation, which is fine since linear 555 * offset is only used with linear buffers on pre-hsw and tiled buffers 556 * with gen2/3, and 90/270 degree rotations isn't supported on any of them. 557 */ 558 u32 intel_fb_xy_to_linear(int x, int y, 559 const struct intel_plane_state *state, 560 int color_plane) 561 { 562 const struct drm_framebuffer *fb = state->hw.fb; 563 unsigned int cpp = fb->format->cpp[color_plane]; 564 unsigned int pitch = state->view.color_plane[color_plane].mapping_stride; 565 566 return y * pitch + x * cpp; 567 } 568 569 /* 570 * Add the x/y offsets derived from fb->offsets[] to the user 571 * specified plane src x/y offsets. The resulting x/y offsets 572 * specify the start of scanout from the beginning of the gtt mapping. 573 */ 574 void intel_add_fb_offsets(int *x, int *y, 575 const struct intel_plane_state *state, 576 int color_plane) 577 578 { 579 *x += state->view.color_plane[color_plane].x; 580 *y += state->view.color_plane[color_plane].y; 581 } 582 583 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 584 u32 pixel_format, u64 modifier) 585 { 586 struct intel_crtc *crtc; 587 struct intel_plane *plane; 588 589 if (!HAS_DISPLAY(dev_priv)) 590 return 0; 591 592 /* 593 * We assume the primary plane for pipe A has 594 * the highest stride limits of them all, 595 * if in case pipe A is disabled, use the first pipe from pipe_mask. 596 */ 597 crtc = intel_first_crtc(dev_priv); 598 if (!crtc) 599 return 0; 600 601 plane = to_intel_plane(crtc->base.primary); 602 603 return plane->max_stride(plane, pixel_format, modifier, 604 DRM_MODE_ROTATE_0); 605 } 606 607 void intel_set_plane_visible(struct intel_crtc_state *crtc_state, 608 struct intel_plane_state *plane_state, 609 bool visible) 610 { 611 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 612 613 plane_state->uapi.visible = visible; 614 615 if (visible) 616 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base); 617 else 618 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base); 619 } 620 621 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state) 622 { 623 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 624 struct drm_plane *plane; 625 626 /* 627 * Active_planes aliases if multiple "primary" or cursor planes 628 * have been used on the same (or wrong) pipe. plane_mask uses 629 * unique ids, hence we can use that to reconstruct active_planes. 630 */ 631 crtc_state->enabled_planes = 0; 632 crtc_state->active_planes = 0; 633 634 drm_for_each_plane_mask(plane, &dev_priv->drm, 635 crtc_state->uapi.plane_mask) { 636 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id); 637 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id); 638 } 639 } 640 641 void intel_plane_disable_noatomic(struct intel_crtc *crtc, 642 struct intel_plane *plane) 643 { 644 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 645 struct intel_crtc_state *crtc_state = 646 to_intel_crtc_state(crtc->base.state); 647 struct intel_plane_state *plane_state = 648 to_intel_plane_state(plane->base.state); 649 650 drm_dbg_kms(&dev_priv->drm, 651 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n", 652 plane->base.base.id, plane->base.name, 653 crtc->base.base.id, crtc->base.name); 654 655 intel_set_plane_visible(crtc_state, plane_state, false); 656 intel_plane_fixup_bitmasks(crtc_state); 657 crtc_state->data_rate[plane->id] = 0; 658 crtc_state->data_rate_y[plane->id] = 0; 659 crtc_state->rel_data_rate[plane->id] = 0; 660 crtc_state->rel_data_rate_y[plane->id] = 0; 661 crtc_state->min_cdclk[plane->id] = 0; 662 663 if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 && 664 hsw_ips_disable(crtc_state)) { 665 crtc_state->ips_enabled = false; 666 intel_crtc_wait_for_next_vblank(crtc); 667 } 668 669 /* 670 * Vblank time updates from the shadow to live plane control register 671 * are blocked if the memory self-refresh mode is active at that 672 * moment. So to make sure the plane gets truly disabled, disable 673 * first the self-refresh mode. The self-refresh enable bit in turn 674 * will be checked/applied by the HW only at the next frame start 675 * event which is after the vblank start event, so we need to have a 676 * wait-for-vblank between disabling the plane and the pipe. 677 */ 678 if (HAS_GMCH(dev_priv) && 679 intel_set_memory_cxsr(dev_priv, false)) 680 intel_crtc_wait_for_next_vblank(crtc); 681 682 /* 683 * Gen2 reports pipe underruns whenever all planes are disabled. 684 * So disable underrun reporting before all the planes get disabled. 685 */ 686 if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes) 687 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); 688 689 intel_plane_disable_arm(plane, crtc_state); 690 intel_crtc_wait_for_next_vblank(crtc); 691 } 692 693 unsigned int 694 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state) 695 { 696 int x = 0, y = 0; 697 698 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, 699 plane_state->view.color_plane[0].offset, 0); 700 701 return y; 702 } 703 704 static int 705 intel_display_commit_duplicated_state(struct intel_atomic_state *state, 706 struct drm_modeset_acquire_ctx *ctx) 707 { 708 struct drm_i915_private *i915 = to_i915(state->base.dev); 709 int ret; 710 711 ret = drm_atomic_helper_commit_duplicated_state(&state->base, ctx); 712 713 drm_WARN_ON(&i915->drm, ret == -EDEADLK); 714 715 return ret; 716 } 717 718 static int 719 __intel_display_resume(struct drm_i915_private *i915, 720 struct drm_atomic_state *state, 721 struct drm_modeset_acquire_ctx *ctx) 722 { 723 struct drm_crtc_state *crtc_state; 724 struct drm_crtc *crtc; 725 int i; 726 727 intel_modeset_setup_hw_state(i915, ctx); 728 intel_vga_redisable(i915); 729 730 if (!state) 731 return 0; 732 733 /* 734 * We've duplicated the state, pointers to the old state are invalid. 735 * 736 * Don't attempt to use the old state until we commit the duplicated state. 737 */ 738 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 739 /* 740 * Force recalculation even if we restore 741 * current state. With fast modeset this may not result 742 * in a modeset when the state is compatible. 743 */ 744 crtc_state->mode_changed = true; 745 } 746 747 /* ignore any reset values/BIOS leftovers in the WM registers */ 748 if (!HAS_GMCH(i915)) 749 to_intel_atomic_state(state)->skip_intermediate_wm = true; 750 751 return intel_display_commit_duplicated_state(to_intel_atomic_state(state), ctx); 752 } 753 754 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) 755 { 756 return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display && 757 intel_has_gpu_reset(to_gt(dev_priv))); 758 } 759 760 void intel_display_prepare_reset(struct drm_i915_private *dev_priv) 761 { 762 struct drm_modeset_acquire_ctx *ctx = &dev_priv->display.restore.reset_ctx; 763 struct drm_atomic_state *state; 764 int ret; 765 766 if (!HAS_DISPLAY(dev_priv)) 767 return; 768 769 /* reset doesn't touch the display */ 770 if (!dev_priv->params.force_reset_modeset_test && 771 !gpu_reset_clobbers_display(dev_priv)) 772 return; 773 774 /* We have a modeset vs reset deadlock, defensively unbreak it. */ 775 set_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags); 776 smp_mb__after_atomic(); 777 wake_up_bit(&to_gt(dev_priv)->reset.flags, I915_RESET_MODESET); 778 779 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) { 780 drm_dbg_kms(&dev_priv->drm, 781 "Modeset potentially stuck, unbreaking through wedging\n"); 782 intel_gt_set_wedged(to_gt(dev_priv)); 783 } 784 785 /* 786 * Need mode_config.mutex so that we don't 787 * trample ongoing ->detect() and whatnot. 788 */ 789 mutex_lock(&dev_priv->drm.mode_config.mutex); 790 drm_modeset_acquire_init(ctx, 0); 791 while (1) { 792 ret = drm_modeset_lock_all_ctx(&dev_priv->drm, ctx); 793 if (ret != -EDEADLK) 794 break; 795 796 drm_modeset_backoff(ctx); 797 } 798 /* 799 * Disabling the crtcs gracefully seems nicer. Also the 800 * g33 docs say we should at least disable all the planes. 801 */ 802 state = drm_atomic_helper_duplicate_state(&dev_priv->drm, ctx); 803 if (IS_ERR(state)) { 804 ret = PTR_ERR(state); 805 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n", 806 ret); 807 return; 808 } 809 810 ret = drm_atomic_helper_disable_all(&dev_priv->drm, ctx); 811 if (ret) { 812 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", 813 ret); 814 drm_atomic_state_put(state); 815 return; 816 } 817 818 dev_priv->display.restore.modeset_state = state; 819 state->acquire_ctx = ctx; 820 } 821 822 void intel_display_finish_reset(struct drm_i915_private *i915) 823 { 824 struct drm_modeset_acquire_ctx *ctx = &i915->display.restore.reset_ctx; 825 struct drm_atomic_state *state; 826 int ret; 827 828 if (!HAS_DISPLAY(i915)) 829 return; 830 831 /* reset doesn't touch the display */ 832 if (!test_bit(I915_RESET_MODESET, &to_gt(i915)->reset.flags)) 833 return; 834 835 state = fetch_and_zero(&i915->display.restore.modeset_state); 836 if (!state) 837 goto unlock; 838 839 /* reset doesn't touch the display */ 840 if (!gpu_reset_clobbers_display(i915)) { 841 /* for testing only restore the display */ 842 ret = intel_display_commit_duplicated_state(to_intel_atomic_state(state), ctx); 843 if (ret) 844 drm_err(&i915->drm, 845 "Restoring old state failed with %i\n", ret); 846 } else { 847 /* 848 * The display has been reset as well, 849 * so need a full re-initialization. 850 */ 851 intel_pps_unlock_regs_wa(i915); 852 intel_modeset_init_hw(i915); 853 intel_init_clock_gating(i915); 854 intel_hpd_init(i915); 855 856 ret = __intel_display_resume(i915, state, ctx); 857 if (ret) 858 drm_err(&i915->drm, 859 "Restoring old state failed with %i\n", ret); 860 861 intel_hpd_poll_disable(i915); 862 } 863 864 drm_atomic_state_put(state); 865 unlock: 866 drm_modeset_drop_locks(ctx); 867 drm_modeset_acquire_fini(ctx); 868 mutex_unlock(&i915->drm.mode_config.mutex); 869 870 clear_bit_unlock(I915_RESET_MODESET, &to_gt(i915)->reset.flags); 871 } 872 873 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) 874 { 875 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 876 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 877 enum pipe pipe = crtc->pipe; 878 u32 tmp; 879 880 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe)); 881 882 /* 883 * Display WA #1153: icl 884 * enable hardware to bypass the alpha math 885 * and rounding for per-pixel values 00 and 0xff 886 */ 887 tmp |= PER_PIXEL_ALPHA_BYPASS_EN; 888 /* 889 * Display WA # 1605353570: icl 890 * Set the pixel rounding bit to 1 for allowing 891 * passthrough of Frame buffer pixels unmodified 892 * across pipe 893 */ 894 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU; 895 896 /* 897 * Underrun recovery must always be disabled on display 13+. 898 * DG2 chicken bit meaning is inverted compared to other platforms. 899 */ 900 if (IS_DG2(dev_priv)) 901 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2; 902 else if (DISPLAY_VER(dev_priv) >= 13) 903 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP; 904 905 /* Wa_14010547955:dg2 */ 906 if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER)) 907 tmp |= DG2_RENDER_CCSTAG_4_3_EN; 908 909 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp); 910 } 911 912 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) 913 { 914 struct drm_crtc *crtc; 915 bool cleanup_done; 916 917 drm_for_each_crtc(crtc, &dev_priv->drm) { 918 struct drm_crtc_commit *commit; 919 spin_lock(&crtc->commit_lock); 920 commit = list_first_entry_or_null(&crtc->commit_list, 921 struct drm_crtc_commit, commit_entry); 922 cleanup_done = commit ? 923 try_wait_for_completion(&commit->cleanup_done) : true; 924 spin_unlock(&crtc->commit_lock); 925 926 if (cleanup_done) 927 continue; 928 929 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc)); 930 931 return true; 932 } 933 934 return false; 935 } 936 937 /* 938 * Finds the encoder associated with the given CRTC. This can only be 939 * used when we know that the CRTC isn't feeding multiple encoders! 940 */ 941 struct intel_encoder * 942 intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 943 const struct intel_crtc_state *crtc_state) 944 { 945 const struct drm_connector_state *connector_state; 946 const struct drm_connector *connector; 947 struct intel_encoder *encoder = NULL; 948 struct intel_crtc *master_crtc; 949 int num_encoders = 0; 950 int i; 951 952 master_crtc = intel_master_crtc(crtc_state); 953 954 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 955 if (connector_state->crtc != &master_crtc->base) 956 continue; 957 958 encoder = to_intel_encoder(connector_state->best_encoder); 959 num_encoders++; 960 } 961 962 drm_WARN(encoder->base.dev, num_encoders != 1, 963 "%d encoders for pipe %c\n", 964 num_encoders, pipe_name(master_crtc->pipe)); 965 966 return encoder; 967 } 968 969 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state) 970 { 971 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 972 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 973 const struct drm_rect *dst = &crtc_state->pch_pfit.dst; 974 enum pipe pipe = crtc->pipe; 975 int width = drm_rect_width(dst); 976 int height = drm_rect_height(dst); 977 int x = dst->x1; 978 int y = dst->y1; 979 980 if (!crtc_state->pch_pfit.enabled) 981 return; 982 983 /* Force use of hard-coded filter coefficients 984 * as some pre-programmed values are broken, 985 * e.g. x201. 986 */ 987 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) 988 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 989 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe)); 990 else 991 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 992 PF_FILTER_MED_3x3); 993 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), x << 16 | y); 994 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), width << 16 | height); 995 } 996 997 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc) 998 { 999 if (crtc->overlay) 1000 (void) intel_overlay_switch_off(crtc->overlay); 1001 1002 /* Let userspace switch the overlay on again. In most cases userspace 1003 * has to recompute where to put it anyway. 1004 */ 1005 } 1006 1007 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state) 1008 { 1009 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1010 1011 if (!crtc_state->nv12_planes) 1012 return false; 1013 1014 /* WA Display #0827: Gen9:all */ 1015 if (DISPLAY_VER(dev_priv) == 9) 1016 return true; 1017 1018 return false; 1019 } 1020 1021 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state) 1022 { 1023 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1024 1025 /* Wa_2006604312:icl,ehl */ 1026 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11) 1027 return true; 1028 1029 return false; 1030 } 1031 1032 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state) 1033 { 1034 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1035 1036 /* Wa_1604331009:icl,jsl,ehl */ 1037 if (is_hdr_mode(crtc_state) && 1038 crtc_state->active_planes & BIT(PLANE_CURSOR) && 1039 DISPLAY_VER(dev_priv) == 11) 1040 return true; 1041 1042 return false; 1043 } 1044 1045 static void intel_async_flip_vtd_wa(struct drm_i915_private *i915, 1046 enum pipe pipe, bool enable) 1047 { 1048 if (DISPLAY_VER(i915) == 9) { 1049 /* 1050 * "Plane N strech max must be programmed to 11b (x1) 1051 * when Async flips are enabled on that plane." 1052 */ 1053 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 1054 SKL_PLANE1_STRETCH_MAX_MASK, 1055 enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8); 1056 } else { 1057 /* Also needed on HSW/BDW albeit undocumented */ 1058 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 1059 HSW_PRI_STRETCH_MAX_MASK, 1060 enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8); 1061 } 1062 } 1063 1064 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state) 1065 { 1066 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1067 1068 return crtc_state->uapi.async_flip && i915_vtd_active(i915) && 1069 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915)); 1070 } 1071 1072 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state, 1073 const struct intel_crtc_state *new_crtc_state) 1074 { 1075 return (!old_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)) && 1076 new_crtc_state->active_planes; 1077 } 1078 1079 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state, 1080 const struct intel_crtc_state *new_crtc_state) 1081 { 1082 return old_crtc_state->active_planes && 1083 (!new_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)); 1084 } 1085 1086 static void intel_post_plane_update(struct intel_atomic_state *state, 1087 struct intel_crtc *crtc) 1088 { 1089 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1090 const struct intel_crtc_state *old_crtc_state = 1091 intel_atomic_get_old_crtc_state(state, crtc); 1092 const struct intel_crtc_state *new_crtc_state = 1093 intel_atomic_get_new_crtc_state(state, crtc); 1094 enum pipe pipe = crtc->pipe; 1095 1096 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); 1097 1098 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) 1099 intel_update_watermarks(dev_priv); 1100 1101 intel_fbc_post_update(state, crtc); 1102 1103 if (needs_async_flip_vtd_wa(old_crtc_state) && 1104 !needs_async_flip_vtd_wa(new_crtc_state)) 1105 intel_async_flip_vtd_wa(dev_priv, pipe, false); 1106 1107 if (needs_nv12_wa(old_crtc_state) && 1108 !needs_nv12_wa(new_crtc_state)) 1109 skl_wa_827(dev_priv, pipe, false); 1110 1111 if (needs_scalerclk_wa(old_crtc_state) && 1112 !needs_scalerclk_wa(new_crtc_state)) 1113 icl_wa_scalerclkgating(dev_priv, pipe, false); 1114 1115 if (needs_cursorclk_wa(old_crtc_state) && 1116 !needs_cursorclk_wa(new_crtc_state)) 1117 icl_wa_cursorclkgating(dev_priv, pipe, false); 1118 } 1119 1120 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state, 1121 struct intel_crtc *crtc) 1122 { 1123 const struct intel_crtc_state *crtc_state = 1124 intel_atomic_get_new_crtc_state(state, crtc); 1125 u8 update_planes = crtc_state->update_planes; 1126 const struct intel_plane_state *plane_state; 1127 struct intel_plane *plane; 1128 int i; 1129 1130 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1131 if (plane->pipe == crtc->pipe && 1132 update_planes & BIT(plane->id)) 1133 plane->enable_flip_done(plane); 1134 } 1135 } 1136 1137 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state, 1138 struct intel_crtc *crtc) 1139 { 1140 const struct intel_crtc_state *crtc_state = 1141 intel_atomic_get_new_crtc_state(state, crtc); 1142 u8 update_planes = crtc_state->update_planes; 1143 const struct intel_plane_state *plane_state; 1144 struct intel_plane *plane; 1145 int i; 1146 1147 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1148 if (plane->pipe == crtc->pipe && 1149 update_planes & BIT(plane->id)) 1150 plane->disable_flip_done(plane); 1151 } 1152 } 1153 1154 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state, 1155 struct intel_crtc *crtc) 1156 { 1157 const struct intel_crtc_state *old_crtc_state = 1158 intel_atomic_get_old_crtc_state(state, crtc); 1159 const struct intel_crtc_state *new_crtc_state = 1160 intel_atomic_get_new_crtc_state(state, crtc); 1161 u8 disable_async_flip_planes = old_crtc_state->async_flip_planes & 1162 ~new_crtc_state->async_flip_planes; 1163 const struct intel_plane_state *old_plane_state; 1164 struct intel_plane *plane; 1165 bool need_vbl_wait = false; 1166 int i; 1167 1168 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1169 if (plane->need_async_flip_disable_wa && 1170 plane->pipe == crtc->pipe && 1171 disable_async_flip_planes & BIT(plane->id)) { 1172 /* 1173 * Apart from the async flip bit we want to 1174 * preserve the old state for the plane. 1175 */ 1176 plane->async_flip(plane, old_crtc_state, 1177 old_plane_state, false); 1178 need_vbl_wait = true; 1179 } 1180 } 1181 1182 if (need_vbl_wait) 1183 intel_crtc_wait_for_next_vblank(crtc); 1184 } 1185 1186 static void intel_pre_plane_update(struct intel_atomic_state *state, 1187 struct intel_crtc *crtc) 1188 { 1189 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1190 const struct intel_crtc_state *old_crtc_state = 1191 intel_atomic_get_old_crtc_state(state, crtc); 1192 const struct intel_crtc_state *new_crtc_state = 1193 intel_atomic_get_new_crtc_state(state, crtc); 1194 enum pipe pipe = crtc->pipe; 1195 1196 intel_drrs_deactivate(old_crtc_state); 1197 1198 intel_psr_pre_plane_update(state, crtc); 1199 1200 if (hsw_ips_pre_update(state, crtc)) 1201 intel_crtc_wait_for_next_vblank(crtc); 1202 1203 if (intel_fbc_pre_update(state, crtc)) 1204 intel_crtc_wait_for_next_vblank(crtc); 1205 1206 if (!needs_async_flip_vtd_wa(old_crtc_state) && 1207 needs_async_flip_vtd_wa(new_crtc_state)) 1208 intel_async_flip_vtd_wa(dev_priv, pipe, true); 1209 1210 /* Display WA 827 */ 1211 if (!needs_nv12_wa(old_crtc_state) && 1212 needs_nv12_wa(new_crtc_state)) 1213 skl_wa_827(dev_priv, pipe, true); 1214 1215 /* Wa_2006604312:icl,ehl */ 1216 if (!needs_scalerclk_wa(old_crtc_state) && 1217 needs_scalerclk_wa(new_crtc_state)) 1218 icl_wa_scalerclkgating(dev_priv, pipe, true); 1219 1220 /* Wa_1604331009:icl,jsl,ehl */ 1221 if (!needs_cursorclk_wa(old_crtc_state) && 1222 needs_cursorclk_wa(new_crtc_state)) 1223 icl_wa_cursorclkgating(dev_priv, pipe, true); 1224 1225 /* 1226 * Vblank time updates from the shadow to live plane control register 1227 * are blocked if the memory self-refresh mode is active at that 1228 * moment. So to make sure the plane gets truly disabled, disable 1229 * first the self-refresh mode. The self-refresh enable bit in turn 1230 * will be checked/applied by the HW only at the next frame start 1231 * event which is after the vblank start event, so we need to have a 1232 * wait-for-vblank between disabling the plane and the pipe. 1233 */ 1234 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active && 1235 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) 1236 intel_crtc_wait_for_next_vblank(crtc); 1237 1238 /* 1239 * IVB workaround: must disable low power watermarks for at least 1240 * one frame before enabling scaling. LP watermarks can be re-enabled 1241 * when scaling is disabled. 1242 * 1243 * WaCxSRDisabledForSpriteScaling:ivb 1244 */ 1245 if (old_crtc_state->hw.active && 1246 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv)) 1247 intel_crtc_wait_for_next_vblank(crtc); 1248 1249 /* 1250 * If we're doing a modeset we don't need to do any 1251 * pre-vblank watermark programming here. 1252 */ 1253 if (!intel_crtc_needs_modeset(new_crtc_state)) { 1254 /* 1255 * For platforms that support atomic watermarks, program the 1256 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these 1257 * will be the intermediate values that are safe for both pre- and 1258 * post- vblank; when vblank happens, the 'active' values will be set 1259 * to the final 'target' values and we'll do this again to get the 1260 * optimal watermarks. For gen9+ platforms, the values we program here 1261 * will be the final target values which will get automatically latched 1262 * at vblank time; no further programming will be necessary. 1263 * 1264 * If a platform hasn't been transitioned to atomic watermarks yet, 1265 * we'll continue to update watermarks the old way, if flags tell 1266 * us to. 1267 */ 1268 if (!intel_initial_watermarks(state, crtc)) 1269 if (new_crtc_state->update_wm_pre) 1270 intel_update_watermarks(dev_priv); 1271 } 1272 1273 /* 1274 * Gen2 reports pipe underruns whenever all planes are disabled. 1275 * So disable underrun reporting before all the planes get disabled. 1276 * 1277 * We do this after .initial_watermarks() so that we have a 1278 * chance of catching underruns with the intermediate watermarks 1279 * vs. the old plane configuration. 1280 */ 1281 if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state)) 1282 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1283 1284 /* 1285 * WA for platforms where async address update enable bit 1286 * is double buffered and only latched at start of vblank. 1287 */ 1288 if (old_crtc_state->async_flip_planes & ~new_crtc_state->async_flip_planes) 1289 intel_crtc_async_flip_disable_wa(state, crtc); 1290 } 1291 1292 static void intel_crtc_disable_planes(struct intel_atomic_state *state, 1293 struct intel_crtc *crtc) 1294 { 1295 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1296 const struct intel_crtc_state *new_crtc_state = 1297 intel_atomic_get_new_crtc_state(state, crtc); 1298 unsigned int update_mask = new_crtc_state->update_planes; 1299 const struct intel_plane_state *old_plane_state; 1300 struct intel_plane *plane; 1301 unsigned fb_bits = 0; 1302 int i; 1303 1304 intel_crtc_dpms_overlay_disable(crtc); 1305 1306 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1307 if (crtc->pipe != plane->pipe || 1308 !(update_mask & BIT(plane->id))) 1309 continue; 1310 1311 intel_plane_disable_arm(plane, new_crtc_state); 1312 1313 if (old_plane_state->uapi.visible) 1314 fb_bits |= plane->frontbuffer_bit; 1315 } 1316 1317 intel_frontbuffer_flip(dev_priv, fb_bits); 1318 } 1319 1320 /* 1321 * intel_connector_primary_encoder - get the primary encoder for a connector 1322 * @connector: connector for which to return the encoder 1323 * 1324 * Returns the primary encoder for a connector. There is a 1:1 mapping from 1325 * all connectors to their encoder, except for DP-MST connectors which have 1326 * both a virtual and a primary encoder. These DP-MST primary encoders can be 1327 * pointed to by as many DP-MST connectors as there are pipes. 1328 */ 1329 static struct intel_encoder * 1330 intel_connector_primary_encoder(struct intel_connector *connector) 1331 { 1332 struct intel_encoder *encoder; 1333 1334 if (connector->mst_port) 1335 return &dp_to_dig_port(connector->mst_port)->base; 1336 1337 encoder = intel_attached_encoder(connector); 1338 drm_WARN_ON(connector->base.dev, !encoder); 1339 1340 return encoder; 1341 } 1342 1343 static void intel_encoders_update_prepare(struct intel_atomic_state *state) 1344 { 1345 struct drm_i915_private *i915 = to_i915(state->base.dev); 1346 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 1347 struct intel_crtc *crtc; 1348 struct drm_connector_state *new_conn_state; 1349 struct drm_connector *connector; 1350 int i; 1351 1352 /* 1353 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits. 1354 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook. 1355 */ 1356 if (i915->display.dpll.mgr) { 1357 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1358 if (intel_crtc_needs_modeset(new_crtc_state)) 1359 continue; 1360 1361 new_crtc_state->shared_dpll = old_crtc_state->shared_dpll; 1362 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state; 1363 } 1364 } 1365 1366 if (!state->modeset) 1367 return; 1368 1369 for_each_new_connector_in_state(&state->base, connector, new_conn_state, 1370 i) { 1371 struct intel_connector *intel_connector; 1372 struct intel_encoder *encoder; 1373 struct intel_crtc *crtc; 1374 1375 if (!intel_connector_needs_modeset(state, connector)) 1376 continue; 1377 1378 intel_connector = to_intel_connector(connector); 1379 encoder = intel_connector_primary_encoder(intel_connector); 1380 if (!encoder->update_prepare) 1381 continue; 1382 1383 crtc = new_conn_state->crtc ? 1384 to_intel_crtc(new_conn_state->crtc) : NULL; 1385 encoder->update_prepare(state, encoder, crtc); 1386 } 1387 } 1388 1389 static void intel_encoders_update_complete(struct intel_atomic_state *state) 1390 { 1391 struct drm_connector_state *new_conn_state; 1392 struct drm_connector *connector; 1393 int i; 1394 1395 if (!state->modeset) 1396 return; 1397 1398 for_each_new_connector_in_state(&state->base, connector, new_conn_state, 1399 i) { 1400 struct intel_connector *intel_connector; 1401 struct intel_encoder *encoder; 1402 struct intel_crtc *crtc; 1403 1404 if (!intel_connector_needs_modeset(state, connector)) 1405 continue; 1406 1407 intel_connector = to_intel_connector(connector); 1408 encoder = intel_connector_primary_encoder(intel_connector); 1409 if (!encoder->update_complete) 1410 continue; 1411 1412 crtc = new_conn_state->crtc ? 1413 to_intel_crtc(new_conn_state->crtc) : NULL; 1414 encoder->update_complete(state, encoder, crtc); 1415 } 1416 } 1417 1418 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state, 1419 struct intel_crtc *crtc) 1420 { 1421 const struct intel_crtc_state *crtc_state = 1422 intel_atomic_get_new_crtc_state(state, crtc); 1423 const struct drm_connector_state *conn_state; 1424 struct drm_connector *conn; 1425 int i; 1426 1427 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1428 struct intel_encoder *encoder = 1429 to_intel_encoder(conn_state->best_encoder); 1430 1431 if (conn_state->crtc != &crtc->base) 1432 continue; 1433 1434 if (encoder->pre_pll_enable) 1435 encoder->pre_pll_enable(state, encoder, 1436 crtc_state, conn_state); 1437 } 1438 } 1439 1440 static void intel_encoders_pre_enable(struct intel_atomic_state *state, 1441 struct intel_crtc *crtc) 1442 { 1443 const struct intel_crtc_state *crtc_state = 1444 intel_atomic_get_new_crtc_state(state, crtc); 1445 const struct drm_connector_state *conn_state; 1446 struct drm_connector *conn; 1447 int i; 1448 1449 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1450 struct intel_encoder *encoder = 1451 to_intel_encoder(conn_state->best_encoder); 1452 1453 if (conn_state->crtc != &crtc->base) 1454 continue; 1455 1456 if (encoder->pre_enable) 1457 encoder->pre_enable(state, encoder, 1458 crtc_state, conn_state); 1459 } 1460 } 1461 1462 static void intel_encoders_enable(struct intel_atomic_state *state, 1463 struct intel_crtc *crtc) 1464 { 1465 const struct intel_crtc_state *crtc_state = 1466 intel_atomic_get_new_crtc_state(state, crtc); 1467 const struct drm_connector_state *conn_state; 1468 struct drm_connector *conn; 1469 int i; 1470 1471 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1472 struct intel_encoder *encoder = 1473 to_intel_encoder(conn_state->best_encoder); 1474 1475 if (conn_state->crtc != &crtc->base) 1476 continue; 1477 1478 if (encoder->enable) 1479 encoder->enable(state, encoder, 1480 crtc_state, conn_state); 1481 intel_opregion_notify_encoder(encoder, true); 1482 } 1483 } 1484 1485 static void intel_encoders_disable(struct intel_atomic_state *state, 1486 struct intel_crtc *crtc) 1487 { 1488 const struct intel_crtc_state *old_crtc_state = 1489 intel_atomic_get_old_crtc_state(state, crtc); 1490 const struct drm_connector_state *old_conn_state; 1491 struct drm_connector *conn; 1492 int i; 1493 1494 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1495 struct intel_encoder *encoder = 1496 to_intel_encoder(old_conn_state->best_encoder); 1497 1498 if (old_conn_state->crtc != &crtc->base) 1499 continue; 1500 1501 intel_opregion_notify_encoder(encoder, false); 1502 if (encoder->disable) 1503 encoder->disable(state, encoder, 1504 old_crtc_state, old_conn_state); 1505 } 1506 } 1507 1508 static void intel_encoders_post_disable(struct intel_atomic_state *state, 1509 struct intel_crtc *crtc) 1510 { 1511 const struct intel_crtc_state *old_crtc_state = 1512 intel_atomic_get_old_crtc_state(state, crtc); 1513 const struct drm_connector_state *old_conn_state; 1514 struct drm_connector *conn; 1515 int i; 1516 1517 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1518 struct intel_encoder *encoder = 1519 to_intel_encoder(old_conn_state->best_encoder); 1520 1521 if (old_conn_state->crtc != &crtc->base) 1522 continue; 1523 1524 if (encoder->post_disable) 1525 encoder->post_disable(state, encoder, 1526 old_crtc_state, old_conn_state); 1527 } 1528 } 1529 1530 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state, 1531 struct intel_crtc *crtc) 1532 { 1533 const struct intel_crtc_state *old_crtc_state = 1534 intel_atomic_get_old_crtc_state(state, crtc); 1535 const struct drm_connector_state *old_conn_state; 1536 struct drm_connector *conn; 1537 int i; 1538 1539 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1540 struct intel_encoder *encoder = 1541 to_intel_encoder(old_conn_state->best_encoder); 1542 1543 if (old_conn_state->crtc != &crtc->base) 1544 continue; 1545 1546 if (encoder->post_pll_disable) 1547 encoder->post_pll_disable(state, encoder, 1548 old_crtc_state, old_conn_state); 1549 } 1550 } 1551 1552 static void intel_encoders_update_pipe(struct intel_atomic_state *state, 1553 struct intel_crtc *crtc) 1554 { 1555 const struct intel_crtc_state *crtc_state = 1556 intel_atomic_get_new_crtc_state(state, crtc); 1557 const struct drm_connector_state *conn_state; 1558 struct drm_connector *conn; 1559 int i; 1560 1561 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1562 struct intel_encoder *encoder = 1563 to_intel_encoder(conn_state->best_encoder); 1564 1565 if (conn_state->crtc != &crtc->base) 1566 continue; 1567 1568 if (encoder->update_pipe) 1569 encoder->update_pipe(state, encoder, 1570 crtc_state, conn_state); 1571 } 1572 } 1573 1574 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state) 1575 { 1576 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1577 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 1578 1579 plane->disable_arm(plane, crtc_state); 1580 } 1581 1582 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1583 { 1584 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1585 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1586 1587 if (crtc_state->has_pch_encoder) { 1588 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1589 &crtc_state->fdi_m_n); 1590 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1591 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1592 &crtc_state->dp_m_n); 1593 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1594 &crtc_state->dp_m2_n2); 1595 } 1596 1597 intel_set_transcoder_timings(crtc_state); 1598 1599 ilk_set_pipeconf(crtc_state); 1600 } 1601 1602 static void ilk_crtc_enable(struct intel_atomic_state *state, 1603 struct intel_crtc *crtc) 1604 { 1605 const struct intel_crtc_state *new_crtc_state = 1606 intel_atomic_get_new_crtc_state(state, crtc); 1607 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1608 enum pipe pipe = crtc->pipe; 1609 1610 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1611 return; 1612 1613 /* 1614 * Sometimes spurious CPU pipe underruns happen during FDI 1615 * training, at least with VGA+HDMI cloning. Suppress them. 1616 * 1617 * On ILK we get an occasional spurious CPU pipe underruns 1618 * between eDP port A enable and vdd enable. Also PCH port 1619 * enable seems to result in the occasional CPU pipe underrun. 1620 * 1621 * Spurious PCH underruns also occur during PCH enabling. 1622 */ 1623 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1624 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 1625 1626 ilk_configure_cpu_transcoder(new_crtc_state); 1627 1628 intel_set_pipe_src_size(new_crtc_state); 1629 1630 crtc->active = true; 1631 1632 intel_encoders_pre_enable(state, crtc); 1633 1634 if (new_crtc_state->has_pch_encoder) { 1635 ilk_pch_pre_enable(state, crtc); 1636 } else { 1637 assert_fdi_tx_disabled(dev_priv, pipe); 1638 assert_fdi_rx_disabled(dev_priv, pipe); 1639 } 1640 1641 ilk_pfit_enable(new_crtc_state); 1642 1643 /* 1644 * On ILK+ LUT must be loaded before the pipe is running but with 1645 * clocks enabled 1646 */ 1647 intel_color_load_luts(new_crtc_state); 1648 intel_color_commit_noarm(new_crtc_state); 1649 intel_color_commit_arm(new_crtc_state); 1650 /* update DSPCNTR to configure gamma for pipe bottom color */ 1651 intel_disable_primary_plane(new_crtc_state); 1652 1653 intel_initial_watermarks(state, crtc); 1654 intel_enable_transcoder(new_crtc_state); 1655 1656 if (new_crtc_state->has_pch_encoder) 1657 ilk_pch_enable(state, crtc); 1658 1659 intel_crtc_vblank_on(new_crtc_state); 1660 1661 intel_encoders_enable(state, crtc); 1662 1663 if (HAS_PCH_CPT(dev_priv)) 1664 intel_wait_for_pipe_scanline_moving(crtc); 1665 1666 /* 1667 * Must wait for vblank to avoid spurious PCH FIFO underruns. 1668 * And a second vblank wait is needed at least on ILK with 1669 * some interlaced HDMI modes. Let's do the double wait always 1670 * in case there are more corner cases we don't know about. 1671 */ 1672 if (new_crtc_state->has_pch_encoder) { 1673 intel_crtc_wait_for_next_vblank(crtc); 1674 intel_crtc_wait_for_next_vblank(crtc); 1675 } 1676 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1677 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 1678 } 1679 1680 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, 1681 enum pipe pipe, bool apply) 1682 { 1683 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)); 1684 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS; 1685 1686 if (apply) 1687 val |= mask; 1688 else 1689 val &= ~mask; 1690 1691 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val); 1692 } 1693 1694 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state) 1695 { 1696 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1697 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1698 1699 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe), 1700 HSW_LINETIME(crtc_state->linetime) | 1701 HSW_IPS_LINETIME(crtc_state->ips_linetime)); 1702 } 1703 1704 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) 1705 { 1706 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1707 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1708 enum transcoder transcoder = crtc_state->cpu_transcoder; 1709 i915_reg_t reg = DISPLAY_VER(dev_priv) >= 14 ? MTL_CHICKEN_TRANS(transcoder) : 1710 CHICKEN_TRANS(transcoder); 1711 1712 intel_de_rmw(dev_priv, reg, 1713 HSW_FRAME_START_DELAY_MASK, 1714 HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1)); 1715 } 1716 1717 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state, 1718 const struct intel_crtc_state *crtc_state) 1719 { 1720 struct intel_crtc *master_crtc = intel_master_crtc(crtc_state); 1721 1722 /* 1723 * Enable sequence steps 1-7 on bigjoiner master 1724 */ 1725 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1726 intel_encoders_pre_pll_enable(state, master_crtc); 1727 1728 if (crtc_state->shared_dpll) 1729 intel_enable_shared_dpll(crtc_state); 1730 1731 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1732 intel_encoders_pre_enable(state, master_crtc); 1733 } 1734 1735 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1736 { 1737 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1738 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1739 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1740 1741 if (crtc_state->has_pch_encoder) { 1742 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1743 &crtc_state->fdi_m_n); 1744 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1745 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1746 &crtc_state->dp_m_n); 1747 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1748 &crtc_state->dp_m2_n2); 1749 } 1750 1751 intel_set_transcoder_timings(crtc_state); 1752 1753 if (cpu_transcoder != TRANSCODER_EDP) 1754 intel_de_write(dev_priv, TRANS_MULT(cpu_transcoder), 1755 crtc_state->pixel_multiplier - 1); 1756 1757 hsw_set_frame_start_delay(crtc_state); 1758 1759 hsw_set_transconf(crtc_state); 1760 } 1761 1762 static void hsw_crtc_enable(struct intel_atomic_state *state, 1763 struct intel_crtc *crtc) 1764 { 1765 const struct intel_crtc_state *new_crtc_state = 1766 intel_atomic_get_new_crtc_state(state, crtc); 1767 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1768 enum pipe pipe = crtc->pipe, hsw_workaround_pipe; 1769 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 1770 bool psl_clkgate_wa; 1771 1772 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1773 return; 1774 1775 intel_dmc_enable_pipe(dev_priv, crtc->pipe); 1776 1777 if (!new_crtc_state->bigjoiner_pipes) { 1778 intel_encoders_pre_pll_enable(state, crtc); 1779 1780 if (new_crtc_state->shared_dpll) 1781 intel_enable_shared_dpll(new_crtc_state); 1782 1783 intel_encoders_pre_enable(state, crtc); 1784 } else { 1785 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state); 1786 } 1787 1788 intel_dsc_enable(new_crtc_state); 1789 1790 if (DISPLAY_VER(dev_priv) >= 13) 1791 intel_uncompressed_joiner_enable(new_crtc_state); 1792 1793 intel_set_pipe_src_size(new_crtc_state); 1794 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 1795 bdw_set_pipemisc(new_crtc_state); 1796 1797 if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) && 1798 !transcoder_is_dsi(cpu_transcoder)) 1799 hsw_configure_cpu_transcoder(new_crtc_state); 1800 1801 crtc->active = true; 1802 1803 /* Display WA #1180: WaDisableScalarClockGating: glk */ 1804 psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 && 1805 new_crtc_state->pch_pfit.enabled; 1806 if (psl_clkgate_wa) 1807 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true); 1808 1809 if (DISPLAY_VER(dev_priv) >= 9) 1810 skl_pfit_enable(new_crtc_state); 1811 else 1812 ilk_pfit_enable(new_crtc_state); 1813 1814 /* 1815 * On ILK+ LUT must be loaded before the pipe is running but with 1816 * clocks enabled 1817 */ 1818 intel_color_load_luts(new_crtc_state); 1819 intel_color_commit_noarm(new_crtc_state); 1820 intel_color_commit_arm(new_crtc_state); 1821 /* update DSPCNTR to configure gamma/csc for pipe bottom color */ 1822 if (DISPLAY_VER(dev_priv) < 9) 1823 intel_disable_primary_plane(new_crtc_state); 1824 1825 hsw_set_linetime_wm(new_crtc_state); 1826 1827 if (DISPLAY_VER(dev_priv) >= 11) 1828 icl_set_pipe_chicken(new_crtc_state); 1829 1830 intel_initial_watermarks(state, crtc); 1831 1832 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 1833 intel_crtc_vblank_on(new_crtc_state); 1834 1835 intel_encoders_enable(state, crtc); 1836 1837 if (psl_clkgate_wa) { 1838 intel_crtc_wait_for_next_vblank(crtc); 1839 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false); 1840 } 1841 1842 /* If we change the relative order between pipe/planes enabling, we need 1843 * to change the workaround. */ 1844 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe; 1845 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { 1846 struct intel_crtc *wa_crtc; 1847 1848 wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe); 1849 1850 intel_crtc_wait_for_next_vblank(wa_crtc); 1851 intel_crtc_wait_for_next_vblank(wa_crtc); 1852 } 1853 } 1854 1855 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state) 1856 { 1857 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1858 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1859 enum pipe pipe = crtc->pipe; 1860 1861 /* To avoid upsetting the power well on haswell only disable the pfit if 1862 * it's in use. The hw state code will make sure we get this right. */ 1863 if (!old_crtc_state->pch_pfit.enabled) 1864 return; 1865 1866 intel_de_write_fw(dev_priv, PF_CTL(pipe), 0); 1867 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0); 1868 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0); 1869 } 1870 1871 static void ilk_crtc_disable(struct intel_atomic_state *state, 1872 struct intel_crtc *crtc) 1873 { 1874 const struct intel_crtc_state *old_crtc_state = 1875 intel_atomic_get_old_crtc_state(state, crtc); 1876 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1877 enum pipe pipe = crtc->pipe; 1878 1879 /* 1880 * Sometimes spurious CPU pipe underruns happen when the 1881 * pipe is already disabled, but FDI RX/TX is still enabled. 1882 * Happens at least with VGA+HDMI cloning. Suppress them. 1883 */ 1884 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1885 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 1886 1887 intel_encoders_disable(state, crtc); 1888 1889 intel_crtc_vblank_off(old_crtc_state); 1890 1891 intel_disable_transcoder(old_crtc_state); 1892 1893 ilk_pfit_disable(old_crtc_state); 1894 1895 if (old_crtc_state->has_pch_encoder) 1896 ilk_pch_disable(state, crtc); 1897 1898 intel_encoders_post_disable(state, crtc); 1899 1900 if (old_crtc_state->has_pch_encoder) 1901 ilk_pch_post_disable(state, crtc); 1902 1903 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1904 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 1905 } 1906 1907 static void hsw_crtc_disable(struct intel_atomic_state *state, 1908 struct intel_crtc *crtc) 1909 { 1910 const struct intel_crtc_state *old_crtc_state = 1911 intel_atomic_get_old_crtc_state(state, crtc); 1912 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 1913 1914 /* 1915 * FIXME collapse everything to one hook. 1916 * Need care with mst->ddi interactions. 1917 */ 1918 if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) { 1919 intel_encoders_disable(state, crtc); 1920 intel_encoders_post_disable(state, crtc); 1921 } 1922 1923 intel_dmc_disable_pipe(i915, crtc->pipe); 1924 } 1925 1926 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) 1927 { 1928 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1929 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1930 1931 if (!crtc_state->gmch_pfit.control) 1932 return; 1933 1934 /* 1935 * The panel fitter should only be adjusted whilst the pipe is disabled, 1936 * according to register description and PRM. 1937 */ 1938 drm_WARN_ON(&dev_priv->drm, 1939 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE); 1940 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 1941 1942 intel_de_write(dev_priv, PFIT_PGM_RATIOS, 1943 crtc_state->gmch_pfit.pgm_ratios); 1944 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control); 1945 1946 /* Border color in case we don't scale up to the full screen. Black by 1947 * default, change to something else for debugging. */ 1948 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); 1949 } 1950 1951 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) 1952 { 1953 if (phy == PHY_NONE) 1954 return false; 1955 else if (IS_ALDERLAKE_S(dev_priv)) 1956 return phy <= PHY_E; 1957 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) 1958 return phy <= PHY_D; 1959 else if (IS_JSL_EHL(dev_priv)) 1960 return phy <= PHY_C; 1961 else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12)) 1962 return phy <= PHY_B; 1963 else 1964 /* 1965 * DG2 outputs labelled as "combo PHY" in the bspec use 1966 * SNPS PHYs with completely different programming, 1967 * hence we always return false here. 1968 */ 1969 return false; 1970 } 1971 1972 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) 1973 { 1974 if (IS_DG2(dev_priv)) 1975 /* DG2's "TC1" output uses a SNPS PHY */ 1976 return false; 1977 else if (IS_ALDERLAKE_P(dev_priv)) 1978 return phy >= PHY_F && phy <= PHY_I; 1979 else if (IS_TIGERLAKE(dev_priv)) 1980 return phy >= PHY_D && phy <= PHY_I; 1981 else if (IS_ICELAKE(dev_priv)) 1982 return phy >= PHY_C && phy <= PHY_F; 1983 else 1984 return false; 1985 } 1986 1987 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy) 1988 { 1989 if (phy == PHY_NONE) 1990 return false; 1991 else if (IS_DG2(dev_priv)) 1992 /* 1993 * All four "combo" ports and the TC1 port (PHY E) use 1994 * Synopsis PHYs. 1995 */ 1996 return phy <= PHY_E; 1997 1998 return false; 1999 } 2000 2001 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) 2002 { 2003 if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD) 2004 return PHY_D + port - PORT_D_XELPD; 2005 else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1) 2006 return PHY_F + port - PORT_TC1; 2007 else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1) 2008 return PHY_B + port - PORT_TC1; 2009 else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1) 2010 return PHY_C + port - PORT_TC1; 2011 else if (IS_JSL_EHL(i915) && port == PORT_D) 2012 return PHY_A; 2013 2014 return PHY_A + port - PORT_A; 2015 } 2016 2017 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) 2018 { 2019 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port))) 2020 return TC_PORT_NONE; 2021 2022 if (DISPLAY_VER(dev_priv) >= 12) 2023 return TC_PORT_1 + port - PORT_TC1; 2024 else 2025 return TC_PORT_1 + port - PORT_C; 2026 } 2027 2028 enum intel_display_power_domain 2029 intel_aux_power_domain(struct intel_digital_port *dig_port) 2030 { 2031 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 2032 2033 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 2034 return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch); 2035 2036 return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch); 2037 } 2038 2039 static void get_crtc_power_domains(struct intel_crtc_state *crtc_state, 2040 struct intel_power_domain_mask *mask) 2041 { 2042 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2043 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2044 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2045 struct drm_encoder *encoder; 2046 enum pipe pipe = crtc->pipe; 2047 2048 bitmap_zero(mask->bits, POWER_DOMAIN_NUM); 2049 2050 if (!crtc_state->hw.active) 2051 return; 2052 2053 set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits); 2054 set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits); 2055 if (crtc_state->pch_pfit.enabled || 2056 crtc_state->pch_pfit.force_thru) 2057 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits); 2058 2059 drm_for_each_encoder_mask(encoder, &dev_priv->drm, 2060 crtc_state->uapi.encoder_mask) { 2061 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2062 2063 set_bit(intel_encoder->power_domain, mask->bits); 2064 } 2065 2066 if (HAS_DDI(dev_priv) && crtc_state->has_audio) 2067 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits); 2068 2069 if (crtc_state->shared_dpll) 2070 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits); 2071 2072 if (crtc_state->dsc.compression_enable) 2073 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits); 2074 } 2075 2076 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, 2077 struct intel_power_domain_mask *old_domains) 2078 { 2079 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2080 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2081 enum intel_display_power_domain domain; 2082 struct intel_power_domain_mask domains, new_domains; 2083 2084 get_crtc_power_domains(crtc_state, &domains); 2085 2086 bitmap_andnot(new_domains.bits, 2087 domains.bits, 2088 crtc->enabled_power_domains.mask.bits, 2089 POWER_DOMAIN_NUM); 2090 bitmap_andnot(old_domains->bits, 2091 crtc->enabled_power_domains.mask.bits, 2092 domains.bits, 2093 POWER_DOMAIN_NUM); 2094 2095 for_each_power_domain(domain, &new_domains) 2096 intel_display_power_get_in_set(dev_priv, 2097 &crtc->enabled_power_domains, 2098 domain); 2099 } 2100 2101 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc, 2102 struct intel_power_domain_mask *domains) 2103 { 2104 intel_display_power_put_mask_in_set(to_i915(crtc->base.dev), 2105 &crtc->enabled_power_domains, 2106 domains); 2107 } 2108 2109 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 2110 { 2111 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2112 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2113 2114 if (intel_crtc_has_dp_encoder(crtc_state)) { 2115 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 2116 &crtc_state->dp_m_n); 2117 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 2118 &crtc_state->dp_m2_n2); 2119 } 2120 2121 intel_set_transcoder_timings(crtc_state); 2122 2123 i9xx_set_pipeconf(crtc_state); 2124 } 2125 2126 static void valleyview_crtc_enable(struct intel_atomic_state *state, 2127 struct intel_crtc *crtc) 2128 { 2129 const struct intel_crtc_state *new_crtc_state = 2130 intel_atomic_get_new_crtc_state(state, crtc); 2131 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2132 enum pipe pipe = crtc->pipe; 2133 2134 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 2135 return; 2136 2137 i9xx_configure_cpu_transcoder(new_crtc_state); 2138 2139 intel_set_pipe_src_size(new_crtc_state); 2140 2141 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 2142 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY); 2143 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0); 2144 } 2145 2146 crtc->active = true; 2147 2148 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2149 2150 intel_encoders_pre_pll_enable(state, crtc); 2151 2152 if (IS_CHERRYVIEW(dev_priv)) 2153 chv_enable_pll(new_crtc_state); 2154 else 2155 vlv_enable_pll(new_crtc_state); 2156 2157 intel_encoders_pre_enable(state, crtc); 2158 2159 i9xx_pfit_enable(new_crtc_state); 2160 2161 intel_color_load_luts(new_crtc_state); 2162 intel_color_commit_noarm(new_crtc_state); 2163 intel_color_commit_arm(new_crtc_state); 2164 /* update DSPCNTR to configure gamma for pipe bottom color */ 2165 intel_disable_primary_plane(new_crtc_state); 2166 2167 intel_initial_watermarks(state, crtc); 2168 intel_enable_transcoder(new_crtc_state); 2169 2170 intel_crtc_vblank_on(new_crtc_state); 2171 2172 intel_encoders_enable(state, crtc); 2173 } 2174 2175 static void i9xx_crtc_enable(struct intel_atomic_state *state, 2176 struct intel_crtc *crtc) 2177 { 2178 const struct intel_crtc_state *new_crtc_state = 2179 intel_atomic_get_new_crtc_state(state, crtc); 2180 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2181 enum pipe pipe = crtc->pipe; 2182 2183 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 2184 return; 2185 2186 i9xx_configure_cpu_transcoder(new_crtc_state); 2187 2188 intel_set_pipe_src_size(new_crtc_state); 2189 2190 crtc->active = true; 2191 2192 if (DISPLAY_VER(dev_priv) != 2) 2193 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2194 2195 intel_encoders_pre_enable(state, crtc); 2196 2197 i9xx_enable_pll(new_crtc_state); 2198 2199 i9xx_pfit_enable(new_crtc_state); 2200 2201 intel_color_load_luts(new_crtc_state); 2202 intel_color_commit_noarm(new_crtc_state); 2203 intel_color_commit_arm(new_crtc_state); 2204 /* update DSPCNTR to configure gamma for pipe bottom color */ 2205 intel_disable_primary_plane(new_crtc_state); 2206 2207 if (!intel_initial_watermarks(state, crtc)) 2208 intel_update_watermarks(dev_priv); 2209 intel_enable_transcoder(new_crtc_state); 2210 2211 intel_crtc_vblank_on(new_crtc_state); 2212 2213 intel_encoders_enable(state, crtc); 2214 2215 /* prevents spurious underruns */ 2216 if (DISPLAY_VER(dev_priv) == 2) 2217 intel_crtc_wait_for_next_vblank(crtc); 2218 } 2219 2220 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) 2221 { 2222 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 2223 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2224 2225 if (!old_crtc_state->gmch_pfit.control) 2226 return; 2227 2228 assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder); 2229 2230 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n", 2231 intel_de_read(dev_priv, PFIT_CONTROL)); 2232 intel_de_write(dev_priv, PFIT_CONTROL, 0); 2233 } 2234 2235 static void i9xx_crtc_disable(struct intel_atomic_state *state, 2236 struct intel_crtc *crtc) 2237 { 2238 struct intel_crtc_state *old_crtc_state = 2239 intel_atomic_get_old_crtc_state(state, crtc); 2240 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2241 enum pipe pipe = crtc->pipe; 2242 2243 /* 2244 * On gen2 planes are double buffered but the pipe isn't, so we must 2245 * wait for planes to fully turn off before disabling the pipe. 2246 */ 2247 if (DISPLAY_VER(dev_priv) == 2) 2248 intel_crtc_wait_for_next_vblank(crtc); 2249 2250 intel_encoders_disable(state, crtc); 2251 2252 intel_crtc_vblank_off(old_crtc_state); 2253 2254 intel_disable_transcoder(old_crtc_state); 2255 2256 i9xx_pfit_disable(old_crtc_state); 2257 2258 intel_encoders_post_disable(state, crtc); 2259 2260 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) { 2261 if (IS_CHERRYVIEW(dev_priv)) 2262 chv_disable_pll(dev_priv, pipe); 2263 else if (IS_VALLEYVIEW(dev_priv)) 2264 vlv_disable_pll(dev_priv, pipe); 2265 else 2266 i9xx_disable_pll(old_crtc_state); 2267 } 2268 2269 intel_encoders_post_pll_disable(state, crtc); 2270 2271 if (DISPLAY_VER(dev_priv) != 2) 2272 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 2273 2274 if (!dev_priv->display.funcs.wm->initial_watermarks) 2275 intel_update_watermarks(dev_priv); 2276 2277 /* clock the pipe down to 640x480@60 to potentially save power */ 2278 if (IS_I830(dev_priv)) 2279 i830_enable_pipe(dev_priv, pipe); 2280 } 2281 2282 2283 /* 2284 * turn all crtc's off, but do not adjust state 2285 * This has to be paired with a call to intel_modeset_setup_hw_state. 2286 */ 2287 int intel_display_suspend(struct drm_device *dev) 2288 { 2289 struct drm_i915_private *dev_priv = to_i915(dev); 2290 struct drm_atomic_state *state; 2291 int ret; 2292 2293 if (!HAS_DISPLAY(dev_priv)) 2294 return 0; 2295 2296 state = drm_atomic_helper_suspend(dev); 2297 ret = PTR_ERR_OR_ZERO(state); 2298 if (ret) 2299 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", 2300 ret); 2301 else 2302 dev_priv->display.restore.modeset_state = state; 2303 return ret; 2304 } 2305 2306 void intel_encoder_destroy(struct drm_encoder *encoder) 2307 { 2308 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2309 2310 drm_encoder_cleanup(encoder); 2311 kfree(intel_encoder); 2312 } 2313 2314 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) 2315 { 2316 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2317 2318 /* GDG double wide on either pipe, otherwise pipe A only */ 2319 return DISPLAY_VER(dev_priv) < 4 && 2320 (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); 2321 } 2322 2323 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) 2324 { 2325 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock; 2326 struct drm_rect src; 2327 2328 /* 2329 * We only use IF-ID interlacing. If we ever use 2330 * PF-ID we'll need to adjust the pixel_rate here. 2331 */ 2332 2333 if (!crtc_state->pch_pfit.enabled) 2334 return pixel_rate; 2335 2336 drm_rect_init(&src, 0, 0, 2337 drm_rect_width(&crtc_state->pipe_src) << 16, 2338 drm_rect_height(&crtc_state->pipe_src) << 16); 2339 2340 return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst, 2341 pixel_rate); 2342 } 2343 2344 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode, 2345 const struct drm_display_mode *timings) 2346 { 2347 mode->hdisplay = timings->crtc_hdisplay; 2348 mode->htotal = timings->crtc_htotal; 2349 mode->hsync_start = timings->crtc_hsync_start; 2350 mode->hsync_end = timings->crtc_hsync_end; 2351 2352 mode->vdisplay = timings->crtc_vdisplay; 2353 mode->vtotal = timings->crtc_vtotal; 2354 mode->vsync_start = timings->crtc_vsync_start; 2355 mode->vsync_end = timings->crtc_vsync_end; 2356 2357 mode->flags = timings->flags; 2358 mode->type = DRM_MODE_TYPE_DRIVER; 2359 2360 mode->clock = timings->crtc_clock; 2361 2362 drm_mode_set_name(mode); 2363 } 2364 2365 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) 2366 { 2367 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2368 2369 if (HAS_GMCH(dev_priv)) 2370 /* FIXME calculate proper pipe pixel rate for GMCH pfit */ 2371 crtc_state->pixel_rate = 2372 crtc_state->hw.pipe_mode.crtc_clock; 2373 else 2374 crtc_state->pixel_rate = 2375 ilk_pipe_pixel_rate(crtc_state); 2376 } 2377 2378 static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state *crtc_state, 2379 struct drm_display_mode *mode) 2380 { 2381 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2382 2383 if (num_pipes < 2) 2384 return; 2385 2386 mode->crtc_clock /= num_pipes; 2387 mode->crtc_hdisplay /= num_pipes; 2388 mode->crtc_hblank_start /= num_pipes; 2389 mode->crtc_hblank_end /= num_pipes; 2390 mode->crtc_hsync_start /= num_pipes; 2391 mode->crtc_hsync_end /= num_pipes; 2392 mode->crtc_htotal /= num_pipes; 2393 } 2394 2395 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state, 2396 struct drm_display_mode *mode) 2397 { 2398 int overlap = crtc_state->splitter.pixel_overlap; 2399 int n = crtc_state->splitter.link_count; 2400 2401 if (!crtc_state->splitter.enable) 2402 return; 2403 2404 /* 2405 * eDP MSO uses segment timings from EDID for transcoder 2406 * timings, but full mode for everything else. 2407 * 2408 * h_full = (h_segment - pixel_overlap) * link_count 2409 */ 2410 mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n; 2411 mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n; 2412 mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n; 2413 mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n; 2414 mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n; 2415 mode->crtc_htotal = (mode->crtc_htotal - overlap) * n; 2416 mode->crtc_clock *= n; 2417 } 2418 2419 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state) 2420 { 2421 struct drm_display_mode *mode = &crtc_state->hw.mode; 2422 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2423 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2424 2425 /* 2426 * Start with the adjusted_mode crtc timings, which 2427 * have been filled with the transcoder timings. 2428 */ 2429 drm_mode_copy(pipe_mode, adjusted_mode); 2430 2431 /* Expand MSO per-segment transcoder timings to full */ 2432 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2433 2434 /* 2435 * We want the full numbers in adjusted_mode normal timings, 2436 * adjusted_mode crtc timings are left with the raw transcoder 2437 * timings. 2438 */ 2439 intel_mode_from_crtc_timings(adjusted_mode, pipe_mode); 2440 2441 /* Populate the "user" mode with full numbers */ 2442 drm_mode_copy(mode, pipe_mode); 2443 intel_mode_from_crtc_timings(mode, mode); 2444 mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) * 2445 (intel_bigjoiner_num_pipes(crtc_state) ?: 1); 2446 mode->vdisplay = drm_rect_height(&crtc_state->pipe_src); 2447 2448 /* Derive per-pipe timings in case bigjoiner is used */ 2449 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2450 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2451 2452 intel_crtc_compute_pixel_rate(crtc_state); 2453 } 2454 2455 void intel_encoder_get_config(struct intel_encoder *encoder, 2456 struct intel_crtc_state *crtc_state) 2457 { 2458 encoder->get_config(encoder, crtc_state); 2459 2460 intel_crtc_readout_derived_state(crtc_state); 2461 } 2462 2463 static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state *crtc_state) 2464 { 2465 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2466 int width, height; 2467 2468 if (num_pipes < 2) 2469 return; 2470 2471 width = drm_rect_width(&crtc_state->pipe_src); 2472 height = drm_rect_height(&crtc_state->pipe_src); 2473 2474 drm_rect_init(&crtc_state->pipe_src, 0, 0, 2475 width / num_pipes, height); 2476 } 2477 2478 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state) 2479 { 2480 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2481 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2482 2483 intel_bigjoiner_compute_pipe_src(crtc_state); 2484 2485 /* 2486 * Pipe horizontal size must be even in: 2487 * - DVO ganged mode 2488 * - LVDS dual channel mode 2489 * - Double wide pipe 2490 */ 2491 if (drm_rect_width(&crtc_state->pipe_src) & 1) { 2492 if (crtc_state->double_wide) { 2493 drm_dbg_kms(&i915->drm, 2494 "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n", 2495 crtc->base.base.id, crtc->base.name); 2496 return -EINVAL; 2497 } 2498 2499 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 2500 intel_is_dual_link_lvds(i915)) { 2501 drm_dbg_kms(&i915->drm, 2502 "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n", 2503 crtc->base.base.id, crtc->base.name); 2504 return -EINVAL; 2505 } 2506 } 2507 2508 return 0; 2509 } 2510 2511 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state) 2512 { 2513 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2514 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2515 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2516 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2517 int clock_limit = i915->max_dotclk_freq; 2518 2519 /* 2520 * Start with the adjusted_mode crtc timings, which 2521 * have been filled with the transcoder timings. 2522 */ 2523 drm_mode_copy(pipe_mode, adjusted_mode); 2524 2525 /* Expand MSO per-segment transcoder timings to full */ 2526 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2527 2528 /* Derive per-pipe timings in case bigjoiner is used */ 2529 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2530 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2531 2532 if (DISPLAY_VER(i915) < 4) { 2533 clock_limit = i915->display.cdclk.max_cdclk_freq * 9 / 10; 2534 2535 /* 2536 * Enable double wide mode when the dot clock 2537 * is > 90% of the (display) core speed. 2538 */ 2539 if (intel_crtc_supports_double_wide(crtc) && 2540 pipe_mode->crtc_clock > clock_limit) { 2541 clock_limit = i915->max_dotclk_freq; 2542 crtc_state->double_wide = true; 2543 } 2544 } 2545 2546 if (pipe_mode->crtc_clock > clock_limit) { 2547 drm_dbg_kms(&i915->drm, 2548 "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", 2549 crtc->base.base.id, crtc->base.name, 2550 pipe_mode->crtc_clock, clock_limit, 2551 str_yes_no(crtc_state->double_wide)); 2552 return -EINVAL; 2553 } 2554 2555 return 0; 2556 } 2557 2558 static int intel_crtc_compute_config(struct intel_atomic_state *state, 2559 struct intel_crtc *crtc) 2560 { 2561 struct intel_crtc_state *crtc_state = 2562 intel_atomic_get_new_crtc_state(state, crtc); 2563 int ret; 2564 2565 ret = intel_dpll_crtc_compute_clock(state, crtc); 2566 if (ret) 2567 return ret; 2568 2569 ret = intel_crtc_compute_pipe_src(crtc_state); 2570 if (ret) 2571 return ret; 2572 2573 ret = intel_crtc_compute_pipe_mode(crtc_state); 2574 if (ret) 2575 return ret; 2576 2577 intel_crtc_compute_pixel_rate(crtc_state); 2578 2579 if (crtc_state->has_pch_encoder) 2580 return ilk_fdi_compute_config(crtc, crtc_state); 2581 2582 return 0; 2583 } 2584 2585 static void 2586 intel_reduce_m_n_ratio(u32 *num, u32 *den) 2587 { 2588 while (*num > DATA_LINK_M_N_MASK || 2589 *den > DATA_LINK_M_N_MASK) { 2590 *num >>= 1; 2591 *den >>= 1; 2592 } 2593 } 2594 2595 static void compute_m_n(u32 *ret_m, u32 *ret_n, 2596 u32 m, u32 n, u32 constant_n) 2597 { 2598 if (constant_n) 2599 *ret_n = constant_n; 2600 else 2601 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); 2602 2603 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n); 2604 intel_reduce_m_n_ratio(ret_m, ret_n); 2605 } 2606 2607 void 2608 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes, 2609 int pixel_clock, int link_clock, 2610 struct intel_link_m_n *m_n, 2611 bool fec_enable) 2612 { 2613 u32 data_clock = bits_per_pixel * pixel_clock; 2614 2615 if (fec_enable) 2616 data_clock = intel_dp_mode_to_fec_clock(data_clock); 2617 2618 /* 2619 * Windows/BIOS uses fixed M/N values always. Follow suit. 2620 * 2621 * Also several DP dongles in particular seem to be fussy 2622 * about too large link M/N values. Presumably the 20bit 2623 * value used by Windows/BIOS is acceptable to everyone. 2624 */ 2625 m_n->tu = 64; 2626 compute_m_n(&m_n->data_m, &m_n->data_n, 2627 data_clock, link_clock * nlanes * 8, 2628 0x8000000); 2629 2630 compute_m_n(&m_n->link_m, &m_n->link_n, 2631 pixel_clock, link_clock, 2632 0x80000); 2633 } 2634 2635 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv) 2636 { 2637 /* 2638 * There may be no VBT; and if the BIOS enabled SSC we can 2639 * just keep using it to avoid unnecessary flicker. Whereas if the 2640 * BIOS isn't using it, don't assume it will work even if the VBT 2641 * indicates as much. 2642 */ 2643 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { 2644 bool bios_lvds_use_ssc = intel_de_read(dev_priv, 2645 PCH_DREF_CONTROL) & 2646 DREF_SSC1_ENABLE; 2647 2648 if (dev_priv->display.vbt.lvds_use_ssc != bios_lvds_use_ssc) { 2649 drm_dbg_kms(&dev_priv->drm, 2650 "SSC %s by BIOS, overriding VBT which says %s\n", 2651 str_enabled_disabled(bios_lvds_use_ssc), 2652 str_enabled_disabled(dev_priv->display.vbt.lvds_use_ssc)); 2653 dev_priv->display.vbt.lvds_use_ssc = bios_lvds_use_ssc; 2654 } 2655 } 2656 } 2657 2658 void intel_zero_m_n(struct intel_link_m_n *m_n) 2659 { 2660 /* corresponds to 0 register value */ 2661 memset(m_n, 0, sizeof(*m_n)); 2662 m_n->tu = 1; 2663 } 2664 2665 void intel_set_m_n(struct drm_i915_private *i915, 2666 const struct intel_link_m_n *m_n, 2667 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 2668 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 2669 { 2670 intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); 2671 intel_de_write(i915, data_n_reg, m_n->data_n); 2672 intel_de_write(i915, link_m_reg, m_n->link_m); 2673 /* 2674 * On BDW+ writing LINK_N arms the double buffered update 2675 * of all the M/N registers, so it must be written last. 2676 */ 2677 intel_de_write(i915, link_n_reg, m_n->link_n); 2678 } 2679 2680 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, 2681 enum transcoder transcoder) 2682 { 2683 if (IS_HASWELL(dev_priv)) 2684 return transcoder == TRANSCODER_EDP; 2685 2686 return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv); 2687 } 2688 2689 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, 2690 enum transcoder transcoder, 2691 const struct intel_link_m_n *m_n) 2692 { 2693 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2694 enum pipe pipe = crtc->pipe; 2695 2696 if (DISPLAY_VER(dev_priv) >= 5) 2697 intel_set_m_n(dev_priv, m_n, 2698 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 2699 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 2700 else 2701 intel_set_m_n(dev_priv, m_n, 2702 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 2703 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 2704 } 2705 2706 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, 2707 enum transcoder transcoder, 2708 const struct intel_link_m_n *m_n) 2709 { 2710 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2711 2712 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 2713 return; 2714 2715 intel_set_m_n(dev_priv, m_n, 2716 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 2717 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 2718 } 2719 2720 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) 2721 { 2722 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2723 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2724 enum pipe pipe = crtc->pipe; 2725 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2726 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2727 u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end; 2728 int vsyncshift = 0; 2729 2730 /* We need to be careful not to changed the adjusted mode, for otherwise 2731 * the hw state checker will get angry at the mismatch. */ 2732 crtc_vdisplay = adjusted_mode->crtc_vdisplay; 2733 crtc_vtotal = adjusted_mode->crtc_vtotal; 2734 crtc_vblank_start = adjusted_mode->crtc_vblank_start; 2735 crtc_vblank_end = adjusted_mode->crtc_vblank_end; 2736 2737 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 2738 /* the chip adds 2 halflines automatically */ 2739 crtc_vtotal -= 1; 2740 crtc_vblank_end -= 1; 2741 2742 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 2743 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; 2744 else 2745 vsyncshift = adjusted_mode->crtc_hsync_start - 2746 adjusted_mode->crtc_htotal / 2; 2747 if (vsyncshift < 0) 2748 vsyncshift += adjusted_mode->crtc_htotal; 2749 } 2750 2751 /* 2752 * VBLANK_START no longer works on ADL+, instead we must use 2753 * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start. 2754 */ 2755 if (DISPLAY_VER(dev_priv) >= 13) { 2756 intel_de_write(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder), 2757 crtc_vblank_start - crtc_vdisplay); 2758 2759 /* 2760 * VBLANK_START not used by hw, just clear it 2761 * to make it stand out in register dumps. 2762 */ 2763 crtc_vblank_start = 1; 2764 } 2765 2766 if (DISPLAY_VER(dev_priv) > 3) 2767 intel_de_write(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder), 2768 vsyncshift); 2769 2770 intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder), 2771 HACTIVE(adjusted_mode->crtc_hdisplay - 1) | 2772 HTOTAL(adjusted_mode->crtc_htotal - 1)); 2773 intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder), 2774 HBLANK_START(adjusted_mode->crtc_hblank_start - 1) | 2775 HBLANK_END(adjusted_mode->crtc_hblank_end - 1)); 2776 intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder), 2777 HSYNC_START(adjusted_mode->crtc_hsync_start - 1) | 2778 HSYNC_END(adjusted_mode->crtc_hsync_end - 1)); 2779 2780 intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder), 2781 VACTIVE(crtc_vdisplay - 1) | 2782 VTOTAL(crtc_vtotal - 1)); 2783 intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), 2784 VBLANK_START(crtc_vblank_start - 1) | 2785 VBLANK_END(crtc_vblank_end - 1)); 2786 intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder), 2787 VSYNC_START(adjusted_mode->crtc_vsync_start - 1) | 2788 VSYNC_END(adjusted_mode->crtc_vsync_end - 1)); 2789 2790 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be 2791 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is 2792 * documented on the DDI_FUNC_CTL register description, EDP Input Select 2793 * bits. */ 2794 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && 2795 (pipe == PIPE_B || pipe == PIPE_C)) 2796 intel_de_write(dev_priv, TRANS_VTOTAL(pipe), 2797 intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder))); 2798 2799 } 2800 2801 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) 2802 { 2803 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2804 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2805 int width = drm_rect_width(&crtc_state->pipe_src); 2806 int height = drm_rect_height(&crtc_state->pipe_src); 2807 enum pipe pipe = crtc->pipe; 2808 2809 /* pipesrc controls the size that is scaled from, which should 2810 * always be the user's requested size. 2811 */ 2812 intel_de_write(dev_priv, PIPESRC(pipe), 2813 PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1)); 2814 } 2815 2816 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) 2817 { 2818 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2819 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2820 2821 if (DISPLAY_VER(dev_priv) == 2) 2822 return false; 2823 2824 if (DISPLAY_VER(dev_priv) >= 9 || 2825 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2826 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW; 2827 else 2828 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK; 2829 } 2830 2831 static void intel_get_transcoder_timings(struct intel_crtc *crtc, 2832 struct intel_crtc_state *pipe_config) 2833 { 2834 struct drm_device *dev = crtc->base.dev; 2835 struct drm_i915_private *dev_priv = to_i915(dev); 2836 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 2837 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2838 u32 tmp; 2839 2840 tmp = intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder)); 2841 adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1; 2842 adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1; 2843 2844 if (!transcoder_is_dsi(cpu_transcoder)) { 2845 tmp = intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder)); 2846 adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1; 2847 adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1; 2848 } 2849 2850 tmp = intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder)); 2851 adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1; 2852 adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1; 2853 2854 tmp = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder)); 2855 adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1; 2856 adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1; 2857 2858 /* FIXME TGL+ DSI transcoders have this! */ 2859 if (!transcoder_is_dsi(cpu_transcoder)) { 2860 tmp = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder)); 2861 adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1; 2862 adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1; 2863 } 2864 tmp = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder)); 2865 adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1; 2866 adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1; 2867 2868 if (intel_pipe_is_interlaced(pipe_config)) { 2869 adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE; 2870 adjusted_mode->crtc_vtotal += 1; 2871 adjusted_mode->crtc_vblank_end += 1; 2872 } 2873 2874 if (DISPLAY_VER(dev_priv) >= 13 && !transcoder_is_dsi(cpu_transcoder)) 2875 adjusted_mode->crtc_vblank_start = 2876 adjusted_mode->crtc_vdisplay + 2877 intel_de_read(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder)); 2878 } 2879 2880 static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state) 2881 { 2882 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2883 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2884 enum pipe master_pipe, pipe = crtc->pipe; 2885 int width; 2886 2887 if (num_pipes < 2) 2888 return; 2889 2890 master_pipe = bigjoiner_master_pipe(crtc_state); 2891 width = drm_rect_width(&crtc_state->pipe_src); 2892 2893 drm_rect_translate_to(&crtc_state->pipe_src, 2894 (pipe - master_pipe) * width, 0); 2895 } 2896 2897 static void intel_get_pipe_src_size(struct intel_crtc *crtc, 2898 struct intel_crtc_state *pipe_config) 2899 { 2900 struct drm_device *dev = crtc->base.dev; 2901 struct drm_i915_private *dev_priv = to_i915(dev); 2902 u32 tmp; 2903 2904 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe)); 2905 2906 drm_rect_init(&pipe_config->pipe_src, 0, 0, 2907 REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1, 2908 REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1); 2909 2910 intel_bigjoiner_adjust_pipe_src(pipe_config); 2911 } 2912 2913 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) 2914 { 2915 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2916 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2917 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2918 u32 val = 0; 2919 2920 /* 2921 * - We keep both pipes enabled on 830 2922 * - During modeset the pipe is still disabled and must remain so 2923 * - During fastset the pipe is already enabled and must remain so 2924 */ 2925 if (IS_I830(dev_priv) || !intel_crtc_needs_modeset(crtc_state)) 2926 val |= TRANSCONF_ENABLE; 2927 2928 if (crtc_state->double_wide) 2929 val |= TRANSCONF_DOUBLE_WIDE; 2930 2931 /* only g4x and later have fancy bpc/dither controls */ 2932 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 2933 IS_CHERRYVIEW(dev_priv)) { 2934 /* Bspec claims that we can't use dithering for 30bpp pipes. */ 2935 if (crtc_state->dither && crtc_state->pipe_bpp != 30) 2936 val |= TRANSCONF_DITHER_EN | 2937 TRANSCONF_DITHER_TYPE_SP; 2938 2939 switch (crtc_state->pipe_bpp) { 2940 default: 2941 /* Case prevented by intel_choose_pipe_bpp_dither. */ 2942 MISSING_CASE(crtc_state->pipe_bpp); 2943 fallthrough; 2944 case 18: 2945 val |= TRANSCONF_BPC_6; 2946 break; 2947 case 24: 2948 val |= TRANSCONF_BPC_8; 2949 break; 2950 case 30: 2951 val |= TRANSCONF_BPC_10; 2952 break; 2953 } 2954 } 2955 2956 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 2957 if (DISPLAY_VER(dev_priv) < 4 || 2958 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 2959 val |= TRANSCONF_INTERLACE_W_FIELD_INDICATION; 2960 else 2961 val |= TRANSCONF_INTERLACE_W_SYNC_SHIFT; 2962 } else { 2963 val |= TRANSCONF_INTERLACE_PROGRESSIVE; 2964 } 2965 2966 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 2967 crtc_state->limited_color_range) 2968 val |= TRANSCONF_COLOR_RANGE_SELECT; 2969 2970 val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode); 2971 2972 val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 2973 2974 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); 2975 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); 2976 } 2977 2978 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv) 2979 { 2980 if (IS_I830(dev_priv)) 2981 return false; 2982 2983 return DISPLAY_VER(dev_priv) >= 4 || 2984 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); 2985 } 2986 2987 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state) 2988 { 2989 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2990 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2991 u32 tmp; 2992 2993 if (!i9xx_has_pfit(dev_priv)) 2994 return; 2995 2996 tmp = intel_de_read(dev_priv, PFIT_CONTROL); 2997 if (!(tmp & PFIT_ENABLE)) 2998 return; 2999 3000 /* Check whether the pfit is attached to our pipe. */ 3001 if (DISPLAY_VER(dev_priv) < 4) { 3002 if (crtc->pipe != PIPE_B) 3003 return; 3004 } else { 3005 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) 3006 return; 3007 } 3008 3009 crtc_state->gmch_pfit.control = tmp; 3010 crtc_state->gmch_pfit.pgm_ratios = 3011 intel_de_read(dev_priv, PFIT_PGM_RATIOS); 3012 } 3013 3014 static void vlv_crtc_clock_get(struct intel_crtc *crtc, 3015 struct intel_crtc_state *pipe_config) 3016 { 3017 struct drm_device *dev = crtc->base.dev; 3018 struct drm_i915_private *dev_priv = to_i915(dev); 3019 enum pipe pipe = crtc->pipe; 3020 struct dpll clock; 3021 u32 mdiv; 3022 int refclk = 100000; 3023 3024 /* In case of DSI, DPLL will not be used */ 3025 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 3026 return; 3027 3028 vlv_dpio_get(dev_priv); 3029 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); 3030 vlv_dpio_put(dev_priv); 3031 3032 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; 3033 clock.m2 = mdiv & DPIO_M2DIV_MASK; 3034 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; 3035 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; 3036 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; 3037 3038 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); 3039 } 3040 3041 static void chv_crtc_clock_get(struct intel_crtc *crtc, 3042 struct intel_crtc_state *pipe_config) 3043 { 3044 struct drm_device *dev = crtc->base.dev; 3045 struct drm_i915_private *dev_priv = to_i915(dev); 3046 enum pipe pipe = crtc->pipe; 3047 enum dpio_channel port = vlv_pipe_to_channel(pipe); 3048 struct dpll clock; 3049 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; 3050 int refclk = 100000; 3051 3052 /* In case of DSI, DPLL will not be used */ 3053 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 3054 return; 3055 3056 vlv_dpio_get(dev_priv); 3057 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); 3058 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); 3059 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); 3060 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); 3061 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); 3062 vlv_dpio_put(dev_priv); 3063 3064 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; 3065 clock.m2 = (pll_dw0 & 0xff) << 22; 3066 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) 3067 clock.m2 |= pll_dw2 & 0x3fffff; 3068 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; 3069 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; 3070 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; 3071 3072 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); 3073 } 3074 3075 static enum intel_output_format 3076 bdw_get_pipemisc_output_format(struct intel_crtc *crtc) 3077 { 3078 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3079 u32 tmp; 3080 3081 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); 3082 3083 if (tmp & PIPEMISC_YUV420_ENABLE) { 3084 /* We support 4:2:0 in full blend mode only */ 3085 drm_WARN_ON(&dev_priv->drm, 3086 (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0); 3087 3088 return INTEL_OUTPUT_FORMAT_YCBCR420; 3089 } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) { 3090 return INTEL_OUTPUT_FORMAT_YCBCR444; 3091 } else { 3092 return INTEL_OUTPUT_FORMAT_RGB; 3093 } 3094 } 3095 3096 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state) 3097 { 3098 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3099 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 3100 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3101 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 3102 u32 tmp; 3103 3104 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); 3105 3106 if (tmp & DISP_PIPE_GAMMA_ENABLE) 3107 crtc_state->gamma_enable = true; 3108 3109 if (!HAS_GMCH(dev_priv) && 3110 tmp & DISP_PIPE_CSC_ENABLE) 3111 crtc_state->csc_enable = true; 3112 } 3113 3114 static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 3115 struct intel_crtc_state *pipe_config) 3116 { 3117 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3118 enum intel_display_power_domain power_domain; 3119 intel_wakeref_t wakeref; 3120 u32 tmp; 3121 bool ret; 3122 3123 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3124 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3125 if (!wakeref) 3126 return false; 3127 3128 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3129 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3130 pipe_config->shared_dpll = NULL; 3131 3132 ret = false; 3133 3134 tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder)); 3135 if (!(tmp & TRANSCONF_ENABLE)) 3136 goto out; 3137 3138 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 3139 IS_CHERRYVIEW(dev_priv)) { 3140 switch (tmp & TRANSCONF_BPC_MASK) { 3141 case TRANSCONF_BPC_6: 3142 pipe_config->pipe_bpp = 18; 3143 break; 3144 case TRANSCONF_BPC_8: 3145 pipe_config->pipe_bpp = 24; 3146 break; 3147 case TRANSCONF_BPC_10: 3148 pipe_config->pipe_bpp = 30; 3149 break; 3150 default: 3151 MISSING_CASE(tmp); 3152 break; 3153 } 3154 } 3155 3156 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 3157 (tmp & TRANSCONF_COLOR_RANGE_SELECT)) 3158 pipe_config->limited_color_range = true; 3159 3160 pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp); 3161 3162 pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1; 3163 3164 if (IS_CHERRYVIEW(dev_priv)) 3165 pipe_config->cgm_mode = intel_de_read(dev_priv, 3166 CGM_PIPE_MODE(crtc->pipe)); 3167 3168 i9xx_get_pipe_color_config(pipe_config); 3169 intel_color_get_config(pipe_config); 3170 3171 if (DISPLAY_VER(dev_priv) < 4) 3172 pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE; 3173 3174 intel_get_transcoder_timings(crtc, pipe_config); 3175 intel_get_pipe_src_size(crtc, pipe_config); 3176 3177 i9xx_get_pfit_config(pipe_config); 3178 3179 if (DISPLAY_VER(dev_priv) >= 4) { 3180 /* No way to read it out on pipes B and C */ 3181 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) 3182 tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe]; 3183 else 3184 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe)); 3185 pipe_config->pixel_multiplier = 3186 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) 3187 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; 3188 pipe_config->dpll_hw_state.dpll_md = tmp; 3189 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 3190 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 3191 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe)); 3192 pipe_config->pixel_multiplier = 3193 ((tmp & SDVO_MULTIPLIER_MASK) 3194 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; 3195 } else { 3196 /* Note that on i915G/GM the pixel multiplier is in the sdvo 3197 * port and will be fixed up in the encoder->get_config 3198 * function. */ 3199 pipe_config->pixel_multiplier = 1; 3200 } 3201 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv, 3202 DPLL(crtc->pipe)); 3203 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 3204 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv, 3205 FP0(crtc->pipe)); 3206 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv, 3207 FP1(crtc->pipe)); 3208 } else { 3209 /* Mask out read-only status bits. */ 3210 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | 3211 DPLL_PORTC_READY_MASK | 3212 DPLL_PORTB_READY_MASK); 3213 } 3214 3215 if (IS_CHERRYVIEW(dev_priv)) 3216 chv_crtc_clock_get(crtc, pipe_config); 3217 else if (IS_VALLEYVIEW(dev_priv)) 3218 vlv_crtc_clock_get(crtc, pipe_config); 3219 else 3220 i9xx_crtc_clock_get(crtc, pipe_config); 3221 3222 /* 3223 * Normally the dotclock is filled in by the encoder .get_config() 3224 * but in case the pipe is enabled w/o any ports we need a sane 3225 * default. 3226 */ 3227 pipe_config->hw.adjusted_mode.crtc_clock = 3228 pipe_config->port_clock / pipe_config->pixel_multiplier; 3229 3230 ret = true; 3231 3232 out: 3233 intel_display_power_put(dev_priv, power_domain, wakeref); 3234 3235 return ret; 3236 } 3237 3238 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) 3239 { 3240 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3241 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3242 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3243 u32 val = 0; 3244 3245 /* 3246 * - During modeset the pipe is still disabled and must remain so 3247 * - During fastset the pipe is already enabled and must remain so 3248 */ 3249 if (!intel_crtc_needs_modeset(crtc_state)) 3250 val |= TRANSCONF_ENABLE; 3251 3252 switch (crtc_state->pipe_bpp) { 3253 default: 3254 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3255 MISSING_CASE(crtc_state->pipe_bpp); 3256 fallthrough; 3257 case 18: 3258 val |= TRANSCONF_BPC_6; 3259 break; 3260 case 24: 3261 val |= TRANSCONF_BPC_8; 3262 break; 3263 case 30: 3264 val |= TRANSCONF_BPC_10; 3265 break; 3266 case 36: 3267 val |= TRANSCONF_BPC_12; 3268 break; 3269 } 3270 3271 if (crtc_state->dither) 3272 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP; 3273 3274 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3275 val |= TRANSCONF_INTERLACE_IF_ID_ILK; 3276 else 3277 val |= TRANSCONF_INTERLACE_PF_PD_ILK; 3278 3279 /* 3280 * This would end up with an odd purple hue over 3281 * the entire display. Make sure we don't do it. 3282 */ 3283 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 3284 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 3285 3286 if (crtc_state->limited_color_range && 3287 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3288 val |= TRANSCONF_COLOR_RANGE_SELECT; 3289 3290 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3291 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV709; 3292 3293 val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode); 3294 3295 val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3296 val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay); 3297 3298 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); 3299 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); 3300 } 3301 3302 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) 3303 { 3304 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3305 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3306 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3307 u32 val = 0; 3308 3309 /* 3310 * - During modeset the pipe is still disabled and must remain so 3311 * - During fastset the pipe is already enabled and must remain so 3312 */ 3313 if (!intel_crtc_needs_modeset(crtc_state)) 3314 val |= TRANSCONF_ENABLE; 3315 3316 if (IS_HASWELL(dev_priv) && crtc_state->dither) 3317 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP; 3318 3319 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3320 val |= TRANSCONF_INTERLACE_IF_ID_ILK; 3321 else 3322 val |= TRANSCONF_INTERLACE_PF_PD_ILK; 3323 3324 if (IS_HASWELL(dev_priv) && 3325 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3326 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW; 3327 3328 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); 3329 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); 3330 } 3331 3332 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) 3333 { 3334 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3335 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3336 u32 val = 0; 3337 3338 switch (crtc_state->pipe_bpp) { 3339 case 18: 3340 val |= PIPEMISC_BPC_6; 3341 break; 3342 case 24: 3343 val |= PIPEMISC_BPC_8; 3344 break; 3345 case 30: 3346 val |= PIPEMISC_BPC_10; 3347 break; 3348 case 36: 3349 /* Port output 12BPC defined for ADLP+ */ 3350 if (DISPLAY_VER(dev_priv) > 12) 3351 val |= PIPEMISC_BPC_12_ADLP; 3352 break; 3353 default: 3354 MISSING_CASE(crtc_state->pipe_bpp); 3355 break; 3356 } 3357 3358 if (crtc_state->dither) 3359 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; 3360 3361 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 3362 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 3363 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV; 3364 3365 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 3366 val |= PIPEMISC_YUV420_ENABLE | 3367 PIPEMISC_YUV420_MODE_FULL_BLEND; 3368 3369 if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state)) 3370 val |= PIPEMISC_HDR_MODE_PRECISION; 3371 3372 if (DISPLAY_VER(dev_priv) >= 12) 3373 val |= PIPEMISC_PIXEL_ROUNDING_TRUNC; 3374 3375 intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val); 3376 } 3377 3378 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) 3379 { 3380 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3381 u32 tmp; 3382 3383 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); 3384 3385 switch (tmp & PIPEMISC_BPC_MASK) { 3386 case PIPEMISC_BPC_6: 3387 return 18; 3388 case PIPEMISC_BPC_8: 3389 return 24; 3390 case PIPEMISC_BPC_10: 3391 return 30; 3392 /* 3393 * PORT OUTPUT 12 BPC defined for ADLP+. 3394 * 3395 * TODO: 3396 * For previous platforms with DSI interface, bits 5:7 3397 * are used for storing pipe_bpp irrespective of dithering. 3398 * Since the value of 12 BPC is not defined for these bits 3399 * on older platforms, need to find a workaround for 12 BPC 3400 * MIPI DSI HW readout. 3401 */ 3402 case PIPEMISC_BPC_12_ADLP: 3403 if (DISPLAY_VER(dev_priv) > 12) 3404 return 36; 3405 fallthrough; 3406 default: 3407 MISSING_CASE(tmp); 3408 return 0; 3409 } 3410 } 3411 3412 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) 3413 { 3414 /* 3415 * Account for spread spectrum to avoid 3416 * oversubscribing the link. Max center spread 3417 * is 2.5%; use 5% for safety's sake. 3418 */ 3419 u32 bps = target_clock * bpp * 21 / 20; 3420 return DIV_ROUND_UP(bps, link_bw * 8); 3421 } 3422 3423 void intel_get_m_n(struct drm_i915_private *i915, 3424 struct intel_link_m_n *m_n, 3425 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 3426 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 3427 { 3428 m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK; 3429 m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK; 3430 m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK; 3431 m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK; 3432 m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1; 3433 } 3434 3435 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, 3436 enum transcoder transcoder, 3437 struct intel_link_m_n *m_n) 3438 { 3439 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3440 enum pipe pipe = crtc->pipe; 3441 3442 if (DISPLAY_VER(dev_priv) >= 5) 3443 intel_get_m_n(dev_priv, m_n, 3444 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 3445 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 3446 else 3447 intel_get_m_n(dev_priv, m_n, 3448 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 3449 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 3450 } 3451 3452 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, 3453 enum transcoder transcoder, 3454 struct intel_link_m_n *m_n) 3455 { 3456 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3457 3458 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 3459 return; 3460 3461 intel_get_m_n(dev_priv, m_n, 3462 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 3463 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 3464 } 3465 3466 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state, 3467 u32 pos, u32 size) 3468 { 3469 drm_rect_init(&crtc_state->pch_pfit.dst, 3470 pos >> 16, pos & 0xffff, 3471 size >> 16, size & 0xffff); 3472 } 3473 3474 static void skl_get_pfit_config(struct intel_crtc_state *crtc_state) 3475 { 3476 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3477 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3478 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; 3479 int id = -1; 3480 int i; 3481 3482 /* find scaler attached to this pipe */ 3483 for (i = 0; i < crtc->num_scalers; i++) { 3484 u32 ctl, pos, size; 3485 3486 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i)); 3487 if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN) 3488 continue; 3489 3490 id = i; 3491 crtc_state->pch_pfit.enabled = true; 3492 3493 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i)); 3494 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i)); 3495 3496 ilk_get_pfit_pos_size(crtc_state, pos, size); 3497 3498 scaler_state->scalers[i].in_use = true; 3499 break; 3500 } 3501 3502 scaler_state->scaler_id = id; 3503 if (id >= 0) 3504 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); 3505 else 3506 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); 3507 } 3508 3509 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state) 3510 { 3511 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3512 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3513 u32 ctl, pos, size; 3514 3515 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe)); 3516 if ((ctl & PF_ENABLE) == 0) 3517 return; 3518 3519 crtc_state->pch_pfit.enabled = true; 3520 3521 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe)); 3522 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe)); 3523 3524 ilk_get_pfit_pos_size(crtc_state, pos, size); 3525 3526 /* 3527 * We currently do not free assignements of panel fitters on 3528 * ivb/hsw (since we don't use the higher upscaling modes which 3529 * differentiates them) so just WARN about this case for now. 3530 */ 3531 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 7 && 3532 (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe)); 3533 } 3534 3535 static bool ilk_get_pipe_config(struct intel_crtc *crtc, 3536 struct intel_crtc_state *pipe_config) 3537 { 3538 struct drm_device *dev = crtc->base.dev; 3539 struct drm_i915_private *dev_priv = to_i915(dev); 3540 enum intel_display_power_domain power_domain; 3541 intel_wakeref_t wakeref; 3542 u32 tmp; 3543 bool ret; 3544 3545 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3546 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3547 if (!wakeref) 3548 return false; 3549 3550 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3551 pipe_config->shared_dpll = NULL; 3552 3553 ret = false; 3554 tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder)); 3555 if (!(tmp & TRANSCONF_ENABLE)) 3556 goto out; 3557 3558 switch (tmp & TRANSCONF_BPC_MASK) { 3559 case TRANSCONF_BPC_6: 3560 pipe_config->pipe_bpp = 18; 3561 break; 3562 case TRANSCONF_BPC_8: 3563 pipe_config->pipe_bpp = 24; 3564 break; 3565 case TRANSCONF_BPC_10: 3566 pipe_config->pipe_bpp = 30; 3567 break; 3568 case TRANSCONF_BPC_12: 3569 pipe_config->pipe_bpp = 36; 3570 break; 3571 default: 3572 break; 3573 } 3574 3575 if (tmp & TRANSCONF_COLOR_RANGE_SELECT) 3576 pipe_config->limited_color_range = true; 3577 3578 switch (tmp & TRANSCONF_OUTPUT_COLORSPACE_MASK) { 3579 case TRANSCONF_OUTPUT_COLORSPACE_YUV601: 3580 case TRANSCONF_OUTPUT_COLORSPACE_YUV709: 3581 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3582 break; 3583 default: 3584 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3585 break; 3586 } 3587 3588 pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp); 3589 3590 pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1; 3591 3592 pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp); 3593 3594 pipe_config->csc_mode = intel_de_read(dev_priv, 3595 PIPE_CSC_MODE(crtc->pipe)); 3596 3597 i9xx_get_pipe_color_config(pipe_config); 3598 intel_color_get_config(pipe_config); 3599 3600 pipe_config->pixel_multiplier = 1; 3601 3602 ilk_pch_get_config(pipe_config); 3603 3604 intel_get_transcoder_timings(crtc, pipe_config); 3605 intel_get_pipe_src_size(crtc, pipe_config); 3606 3607 ilk_get_pfit_config(pipe_config); 3608 3609 ret = true; 3610 3611 out: 3612 intel_display_power_put(dev_priv, power_domain, wakeref); 3613 3614 return ret; 3615 } 3616 3617 static u8 bigjoiner_pipes(struct drm_i915_private *i915) 3618 { 3619 u8 pipes; 3620 3621 if (DISPLAY_VER(i915) >= 12) 3622 pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D); 3623 else if (DISPLAY_VER(i915) >= 11) 3624 pipes = BIT(PIPE_B) | BIT(PIPE_C); 3625 else 3626 pipes = 0; 3627 3628 return pipes & RUNTIME_INFO(i915)->pipe_mask; 3629 } 3630 3631 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv, 3632 enum transcoder cpu_transcoder) 3633 { 3634 enum intel_display_power_domain power_domain; 3635 intel_wakeref_t wakeref; 3636 u32 tmp = 0; 3637 3638 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3639 3640 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3641 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3642 3643 return tmp & TRANS_DDI_FUNC_ENABLE; 3644 } 3645 3646 static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv, 3647 u8 *master_pipes, u8 *slave_pipes) 3648 { 3649 struct intel_crtc *crtc; 3650 3651 *master_pipes = 0; 3652 *slave_pipes = 0; 3653 3654 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, 3655 bigjoiner_pipes(dev_priv)) { 3656 enum intel_display_power_domain power_domain; 3657 enum pipe pipe = crtc->pipe; 3658 intel_wakeref_t wakeref; 3659 3660 power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe); 3661 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3662 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3663 3664 if (!(tmp & BIG_JOINER_ENABLE)) 3665 continue; 3666 3667 if (tmp & MASTER_BIG_JOINER_ENABLE) 3668 *master_pipes |= BIT(pipe); 3669 else 3670 *slave_pipes |= BIT(pipe); 3671 } 3672 3673 if (DISPLAY_VER(dev_priv) < 13) 3674 continue; 3675 3676 power_domain = POWER_DOMAIN_PIPE(pipe); 3677 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3678 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3679 3680 if (tmp & UNCOMPRESSED_JOINER_MASTER) 3681 *master_pipes |= BIT(pipe); 3682 if (tmp & UNCOMPRESSED_JOINER_SLAVE) 3683 *slave_pipes |= BIT(pipe); 3684 } 3685 } 3686 3687 /* Bigjoiner pipes should always be consecutive master and slave */ 3688 drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1, 3689 "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n", 3690 *master_pipes, *slave_pipes); 3691 } 3692 3693 static enum pipe get_bigjoiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3694 { 3695 if ((slave_pipes & BIT(pipe)) == 0) 3696 return pipe; 3697 3698 /* ignore everything above our pipe */ 3699 master_pipes &= ~GENMASK(7, pipe); 3700 3701 /* highest remaining bit should be our master pipe */ 3702 return fls(master_pipes) - 1; 3703 } 3704 3705 static u8 get_bigjoiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3706 { 3707 enum pipe master_pipe, next_master_pipe; 3708 3709 master_pipe = get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes); 3710 3711 if ((master_pipes & BIT(master_pipe)) == 0) 3712 return 0; 3713 3714 /* ignore our master pipe and everything below it */ 3715 master_pipes &= ~GENMASK(master_pipe, 0); 3716 /* make sure a high bit is set for the ffs() */ 3717 master_pipes |= BIT(7); 3718 /* lowest remaining bit should be the next master pipe */ 3719 next_master_pipe = ffs(master_pipes) - 1; 3720 3721 return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe); 3722 } 3723 3724 static u8 hsw_panel_transcoders(struct drm_i915_private *i915) 3725 { 3726 u8 panel_transcoder_mask = BIT(TRANSCODER_EDP); 3727 3728 if (DISPLAY_VER(i915) >= 11) 3729 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); 3730 3731 return panel_transcoder_mask; 3732 } 3733 3734 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) 3735 { 3736 struct drm_device *dev = crtc->base.dev; 3737 struct drm_i915_private *dev_priv = to_i915(dev); 3738 u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv); 3739 enum transcoder cpu_transcoder; 3740 u8 master_pipes, slave_pipes; 3741 u8 enabled_transcoders = 0; 3742 3743 /* 3744 * XXX: Do intel_display_power_get_if_enabled before reading this (for 3745 * consistency and less surprising code; it's in always on power). 3746 */ 3747 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, 3748 panel_transcoder_mask) { 3749 enum intel_display_power_domain power_domain; 3750 intel_wakeref_t wakeref; 3751 enum pipe trans_pipe; 3752 u32 tmp = 0; 3753 3754 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3755 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3756 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3757 3758 if (!(tmp & TRANS_DDI_FUNC_ENABLE)) 3759 continue; 3760 3761 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 3762 default: 3763 drm_WARN(dev, 1, 3764 "unknown pipe linked to transcoder %s\n", 3765 transcoder_name(cpu_transcoder)); 3766 fallthrough; 3767 case TRANS_DDI_EDP_INPUT_A_ONOFF: 3768 case TRANS_DDI_EDP_INPUT_A_ON: 3769 trans_pipe = PIPE_A; 3770 break; 3771 case TRANS_DDI_EDP_INPUT_B_ONOFF: 3772 trans_pipe = PIPE_B; 3773 break; 3774 case TRANS_DDI_EDP_INPUT_C_ONOFF: 3775 trans_pipe = PIPE_C; 3776 break; 3777 case TRANS_DDI_EDP_INPUT_D_ONOFF: 3778 trans_pipe = PIPE_D; 3779 break; 3780 } 3781 3782 if (trans_pipe == crtc->pipe) 3783 enabled_transcoders |= BIT(cpu_transcoder); 3784 } 3785 3786 /* single pipe or bigjoiner master */ 3787 cpu_transcoder = (enum transcoder) crtc->pipe; 3788 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 3789 enabled_transcoders |= BIT(cpu_transcoder); 3790 3791 /* bigjoiner slave -> consider the master pipe's transcoder as well */ 3792 enabled_bigjoiner_pipes(dev_priv, &master_pipes, &slave_pipes); 3793 if (slave_pipes & BIT(crtc->pipe)) { 3794 cpu_transcoder = (enum transcoder) 3795 get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes); 3796 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 3797 enabled_transcoders |= BIT(cpu_transcoder); 3798 } 3799 3800 return enabled_transcoders; 3801 } 3802 3803 static bool has_edp_transcoders(u8 enabled_transcoders) 3804 { 3805 return enabled_transcoders & BIT(TRANSCODER_EDP); 3806 } 3807 3808 static bool has_dsi_transcoders(u8 enabled_transcoders) 3809 { 3810 return enabled_transcoders & (BIT(TRANSCODER_DSI_0) | 3811 BIT(TRANSCODER_DSI_1)); 3812 } 3813 3814 static bool has_pipe_transcoders(u8 enabled_transcoders) 3815 { 3816 return enabled_transcoders & ~(BIT(TRANSCODER_EDP) | 3817 BIT(TRANSCODER_DSI_0) | 3818 BIT(TRANSCODER_DSI_1)); 3819 } 3820 3821 static void assert_enabled_transcoders(struct drm_i915_private *i915, 3822 u8 enabled_transcoders) 3823 { 3824 /* Only one type of transcoder please */ 3825 drm_WARN_ON(&i915->drm, 3826 has_edp_transcoders(enabled_transcoders) + 3827 has_dsi_transcoders(enabled_transcoders) + 3828 has_pipe_transcoders(enabled_transcoders) > 1); 3829 3830 /* Only DSI transcoders can be ganged */ 3831 drm_WARN_ON(&i915->drm, 3832 !has_dsi_transcoders(enabled_transcoders) && 3833 !is_power_of_2(enabled_transcoders)); 3834 } 3835 3836 static bool hsw_get_transcoder_state(struct intel_crtc *crtc, 3837 struct intel_crtc_state *pipe_config, 3838 struct intel_display_power_domain_set *power_domain_set) 3839 { 3840 struct drm_device *dev = crtc->base.dev; 3841 struct drm_i915_private *dev_priv = to_i915(dev); 3842 unsigned long enabled_transcoders; 3843 u32 tmp; 3844 3845 enabled_transcoders = hsw_enabled_transcoders(crtc); 3846 if (!enabled_transcoders) 3847 return false; 3848 3849 assert_enabled_transcoders(dev_priv, enabled_transcoders); 3850 3851 /* 3852 * With the exception of DSI we should only ever have 3853 * a single enabled transcoder. With DSI let's just 3854 * pick the first one. 3855 */ 3856 pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1; 3857 3858 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 3859 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) 3860 return false; 3861 3862 if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) { 3863 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); 3864 3865 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF) 3866 pipe_config->pch_pfit.force_thru = true; 3867 } 3868 3869 tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder)); 3870 3871 return tmp & TRANSCONF_ENABLE; 3872 } 3873 3874 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, 3875 struct intel_crtc_state *pipe_config, 3876 struct intel_display_power_domain_set *power_domain_set) 3877 { 3878 struct drm_device *dev = crtc->base.dev; 3879 struct drm_i915_private *dev_priv = to_i915(dev); 3880 enum transcoder cpu_transcoder; 3881 enum port port; 3882 u32 tmp; 3883 3884 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { 3885 if (port == PORT_A) 3886 cpu_transcoder = TRANSCODER_DSI_A; 3887 else 3888 cpu_transcoder = TRANSCODER_DSI_C; 3889 3890 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 3891 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) 3892 continue; 3893 3894 /* 3895 * The PLL needs to be enabled with a valid divider 3896 * configuration, otherwise accessing DSI registers will hang 3897 * the machine. See BSpec North Display Engine 3898 * registers/MIPI[BXT]. We can break out here early, since we 3899 * need the same DSI PLL to be enabled for both DSI ports. 3900 */ 3901 if (!bxt_dsi_pll_is_enabled(dev_priv)) 3902 break; 3903 3904 /* XXX: this works for video mode only */ 3905 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); 3906 if (!(tmp & DPI_ENABLE)) 3907 continue; 3908 3909 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 3910 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) 3911 continue; 3912 3913 pipe_config->cpu_transcoder = cpu_transcoder; 3914 break; 3915 } 3916 3917 return transcoder_is_dsi(pipe_config->cpu_transcoder); 3918 } 3919 3920 static void intel_bigjoiner_get_config(struct intel_crtc_state *crtc_state) 3921 { 3922 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3923 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 3924 u8 master_pipes, slave_pipes; 3925 enum pipe pipe = crtc->pipe; 3926 3927 enabled_bigjoiner_pipes(i915, &master_pipes, &slave_pipes); 3928 3929 if (((master_pipes | slave_pipes) & BIT(pipe)) == 0) 3930 return; 3931 3932 crtc_state->bigjoiner_pipes = 3933 BIT(get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes)) | 3934 get_bigjoiner_slave_pipes(pipe, master_pipes, slave_pipes); 3935 } 3936 3937 static bool hsw_get_pipe_config(struct intel_crtc *crtc, 3938 struct intel_crtc_state *pipe_config) 3939 { 3940 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3941 bool active; 3942 u32 tmp; 3943 3944 if (!intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains, 3945 POWER_DOMAIN_PIPE(crtc->pipe))) 3946 return false; 3947 3948 pipe_config->shared_dpll = NULL; 3949 3950 active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains); 3951 3952 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 3953 bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) { 3954 drm_WARN_ON(&dev_priv->drm, active); 3955 active = true; 3956 } 3957 3958 if (!active) 3959 goto out; 3960 3961 intel_dsc_get_config(pipe_config); 3962 intel_bigjoiner_get_config(pipe_config); 3963 3964 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || 3965 DISPLAY_VER(dev_priv) >= 11) 3966 intel_get_transcoder_timings(crtc, pipe_config); 3967 3968 if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder)) 3969 intel_vrr_get_config(crtc, pipe_config); 3970 3971 intel_get_pipe_src_size(crtc, pipe_config); 3972 3973 if (IS_HASWELL(dev_priv)) { 3974 u32 tmp = intel_de_read(dev_priv, 3975 TRANSCONF(pipe_config->cpu_transcoder)); 3976 3977 if (tmp & TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW) 3978 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3979 else 3980 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3981 } else { 3982 pipe_config->output_format = 3983 bdw_get_pipemisc_output_format(crtc); 3984 } 3985 3986 pipe_config->gamma_mode = intel_de_read(dev_priv, 3987 GAMMA_MODE(crtc->pipe)); 3988 3989 pipe_config->csc_mode = intel_de_read(dev_priv, 3990 PIPE_CSC_MODE(crtc->pipe)); 3991 3992 if (DISPLAY_VER(dev_priv) >= 9) { 3993 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe)); 3994 3995 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE) 3996 pipe_config->gamma_enable = true; 3997 3998 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE) 3999 pipe_config->csc_enable = true; 4000 } else { 4001 i9xx_get_pipe_color_config(pipe_config); 4002 } 4003 4004 intel_color_get_config(pipe_config); 4005 4006 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe)); 4007 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); 4008 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 4009 pipe_config->ips_linetime = 4010 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); 4011 4012 if (intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains, 4013 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) { 4014 if (DISPLAY_VER(dev_priv) >= 9) 4015 skl_get_pfit_config(pipe_config); 4016 else 4017 ilk_get_pfit_config(pipe_config); 4018 } 4019 4020 hsw_ips_get_config(pipe_config); 4021 4022 if (pipe_config->cpu_transcoder != TRANSCODER_EDP && 4023 !transcoder_is_dsi(pipe_config->cpu_transcoder)) { 4024 pipe_config->pixel_multiplier = 4025 intel_de_read(dev_priv, 4026 TRANS_MULT(pipe_config->cpu_transcoder)) + 1; 4027 } else { 4028 pipe_config->pixel_multiplier = 1; 4029 } 4030 4031 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { 4032 tmp = intel_de_read(dev_priv, DISPLAY_VER(dev_priv) >= 14 ? 4033 MTL_CHICKEN_TRANS(pipe_config->cpu_transcoder) : 4034 CHICKEN_TRANS(pipe_config->cpu_transcoder)); 4035 4036 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1; 4037 } else { 4038 /* no idea if this is correct */ 4039 pipe_config->framestart_delay = 1; 4040 } 4041 4042 out: 4043 intel_display_power_put_all_in_set(dev_priv, &crtc->hw_readout_power_domains); 4044 4045 return active; 4046 } 4047 4048 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state) 4049 { 4050 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4051 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4052 4053 if (!i915->display.funcs.display->get_pipe_config(crtc, crtc_state)) 4054 return false; 4055 4056 crtc_state->hw.active = true; 4057 4058 intel_crtc_readout_derived_state(crtc_state); 4059 4060 return true; 4061 } 4062 4063 /* VESA 640x480x72Hz mode to set on the pipe */ 4064 static const struct drm_display_mode load_detect_mode = { 4065 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, 4066 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 4067 }; 4068 4069 static int intel_modeset_disable_planes(struct drm_atomic_state *state, 4070 struct drm_crtc *crtc) 4071 { 4072 struct drm_plane *plane; 4073 struct drm_plane_state *plane_state; 4074 int ret, i; 4075 4076 ret = drm_atomic_add_affected_planes(state, crtc); 4077 if (ret) 4078 return ret; 4079 4080 for_each_new_plane_in_state(state, plane, plane_state, i) { 4081 if (plane_state->crtc != crtc) 4082 continue; 4083 4084 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL); 4085 if (ret) 4086 return ret; 4087 4088 drm_atomic_set_fb_for_plane(plane_state, NULL); 4089 } 4090 4091 return 0; 4092 } 4093 4094 int intel_get_load_detect_pipe(struct drm_connector *connector, 4095 struct intel_load_detect_pipe *old, 4096 struct drm_modeset_acquire_ctx *ctx) 4097 { 4098 struct intel_encoder *encoder = 4099 intel_attached_encoder(to_intel_connector(connector)); 4100 struct intel_crtc *possible_crtc; 4101 struct intel_crtc *crtc = NULL; 4102 struct drm_device *dev = encoder->base.dev; 4103 struct drm_i915_private *dev_priv = to_i915(dev); 4104 struct drm_mode_config *config = &dev->mode_config; 4105 struct drm_atomic_state *state = NULL, *restore_state = NULL; 4106 struct drm_connector_state *connector_state; 4107 struct intel_crtc_state *crtc_state; 4108 int ret; 4109 4110 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 4111 connector->base.id, connector->name, 4112 encoder->base.base.id, encoder->base.name); 4113 4114 old->restore_state = NULL; 4115 4116 drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex)); 4117 4118 /* 4119 * Algorithm gets a little messy: 4120 * 4121 * - if the connector already has an assigned crtc, use it (but make 4122 * sure it's on first) 4123 * 4124 * - try to find the first unused crtc that can drive this connector, 4125 * and use that if we find one 4126 */ 4127 4128 /* See if we already have a CRTC for this connector */ 4129 if (connector->state->crtc) { 4130 crtc = to_intel_crtc(connector->state->crtc); 4131 4132 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4133 if (ret) 4134 goto fail; 4135 4136 /* Make sure the crtc and connector are running */ 4137 goto found; 4138 } 4139 4140 /* Find an unused one (if possible) */ 4141 for_each_intel_crtc(dev, possible_crtc) { 4142 if (!(encoder->base.possible_crtcs & 4143 drm_crtc_mask(&possible_crtc->base))) 4144 continue; 4145 4146 ret = drm_modeset_lock(&possible_crtc->base.mutex, ctx); 4147 if (ret) 4148 goto fail; 4149 4150 if (possible_crtc->base.state->enable) { 4151 drm_modeset_unlock(&possible_crtc->base.mutex); 4152 continue; 4153 } 4154 4155 crtc = possible_crtc; 4156 break; 4157 } 4158 4159 /* 4160 * If we didn't find an unused CRTC, don't use any. 4161 */ 4162 if (!crtc) { 4163 drm_dbg_kms(&dev_priv->drm, 4164 "no pipe available for load-detect\n"); 4165 ret = -ENODEV; 4166 goto fail; 4167 } 4168 4169 found: 4170 state = drm_atomic_state_alloc(dev); 4171 restore_state = drm_atomic_state_alloc(dev); 4172 if (!state || !restore_state) { 4173 ret = -ENOMEM; 4174 goto fail; 4175 } 4176 4177 state->acquire_ctx = ctx; 4178 restore_state->acquire_ctx = ctx; 4179 4180 connector_state = drm_atomic_get_connector_state(state, connector); 4181 if (IS_ERR(connector_state)) { 4182 ret = PTR_ERR(connector_state); 4183 goto fail; 4184 } 4185 4186 ret = drm_atomic_set_crtc_for_connector(connector_state, &crtc->base); 4187 if (ret) 4188 goto fail; 4189 4190 crtc_state = intel_atomic_get_crtc_state(state, crtc); 4191 if (IS_ERR(crtc_state)) { 4192 ret = PTR_ERR(crtc_state); 4193 goto fail; 4194 } 4195 4196 crtc_state->uapi.active = true; 4197 4198 ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi, 4199 &load_detect_mode); 4200 if (ret) 4201 goto fail; 4202 4203 ret = intel_modeset_disable_planes(state, &crtc->base); 4204 if (ret) 4205 goto fail; 4206 4207 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); 4208 if (!ret) 4209 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, &crtc->base)); 4210 if (!ret) 4211 ret = drm_atomic_add_affected_planes(restore_state, &crtc->base); 4212 if (ret) { 4213 drm_dbg_kms(&dev_priv->drm, 4214 "Failed to create a copy of old state to restore: %i\n", 4215 ret); 4216 goto fail; 4217 } 4218 4219 ret = drm_atomic_commit(state); 4220 if (ret) { 4221 drm_dbg_kms(&dev_priv->drm, 4222 "failed to set mode on load-detect pipe\n"); 4223 goto fail; 4224 } 4225 4226 old->restore_state = restore_state; 4227 drm_atomic_state_put(state); 4228 4229 /* let the connector get through one full cycle before testing */ 4230 intel_crtc_wait_for_next_vblank(crtc); 4231 4232 return true; 4233 4234 fail: 4235 if (state) { 4236 drm_atomic_state_put(state); 4237 state = NULL; 4238 } 4239 if (restore_state) { 4240 drm_atomic_state_put(restore_state); 4241 restore_state = NULL; 4242 } 4243 4244 if (ret == -EDEADLK) 4245 return ret; 4246 4247 return false; 4248 } 4249 4250 void intel_release_load_detect_pipe(struct drm_connector *connector, 4251 struct intel_load_detect_pipe *old, 4252 struct drm_modeset_acquire_ctx *ctx) 4253 { 4254 struct intel_encoder *intel_encoder = 4255 intel_attached_encoder(to_intel_connector(connector)); 4256 struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev); 4257 struct drm_encoder *encoder = &intel_encoder->base; 4258 struct drm_atomic_state *state = old->restore_state; 4259 int ret; 4260 4261 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 4262 connector->base.id, connector->name, 4263 encoder->base.id, encoder->name); 4264 4265 if (!state) 4266 return; 4267 4268 ret = drm_atomic_helper_commit_duplicated_state(state, ctx); 4269 if (ret) 4270 drm_dbg_kms(&i915->drm, 4271 "Couldn't release load detect pipe: %i\n", ret); 4272 drm_atomic_state_put(state); 4273 } 4274 4275 static int i9xx_pll_refclk(struct drm_device *dev, 4276 const struct intel_crtc_state *pipe_config) 4277 { 4278 struct drm_i915_private *dev_priv = to_i915(dev); 4279 u32 dpll = pipe_config->dpll_hw_state.dpll; 4280 4281 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) 4282 return dev_priv->display.vbt.lvds_ssc_freq; 4283 else if (HAS_PCH_SPLIT(dev_priv)) 4284 return 120000; 4285 else if (DISPLAY_VER(dev_priv) != 2) 4286 return 96000; 4287 else 4288 return 48000; 4289 } 4290 4291 /* Returns the clock of the currently programmed mode of the given pipe. */ 4292 void i9xx_crtc_clock_get(struct intel_crtc *crtc, 4293 struct intel_crtc_state *pipe_config) 4294 { 4295 struct drm_device *dev = crtc->base.dev; 4296 struct drm_i915_private *dev_priv = to_i915(dev); 4297 u32 dpll = pipe_config->dpll_hw_state.dpll; 4298 u32 fp; 4299 struct dpll clock; 4300 int port_clock; 4301 int refclk = i9xx_pll_refclk(dev, pipe_config); 4302 4303 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 4304 fp = pipe_config->dpll_hw_state.fp0; 4305 else 4306 fp = pipe_config->dpll_hw_state.fp1; 4307 4308 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 4309 if (IS_PINEVIEW(dev_priv)) { 4310 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; 4311 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; 4312 } else { 4313 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 4314 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 4315 } 4316 4317 if (DISPLAY_VER(dev_priv) != 2) { 4318 if (IS_PINEVIEW(dev_priv)) 4319 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> 4320 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); 4321 else 4322 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> 4323 DPLL_FPA01_P1_POST_DIV_SHIFT); 4324 4325 switch (dpll & DPLL_MODE_MASK) { 4326 case DPLLB_MODE_DAC_SERIAL: 4327 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 4328 5 : 10; 4329 break; 4330 case DPLLB_MODE_LVDS: 4331 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 4332 7 : 14; 4333 break; 4334 default: 4335 drm_dbg_kms(&dev_priv->drm, 4336 "Unknown DPLL mode %08x in programmed " 4337 "mode\n", (int)(dpll & DPLL_MODE_MASK)); 4338 return; 4339 } 4340 4341 if (IS_PINEVIEW(dev_priv)) 4342 port_clock = pnv_calc_dpll_params(refclk, &clock); 4343 else 4344 port_clock = i9xx_calc_dpll_params(refclk, &clock); 4345 } else { 4346 enum pipe lvds_pipe; 4347 4348 if (IS_I85X(dev_priv) && 4349 intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) && 4350 lvds_pipe == crtc->pipe) { 4351 u32 lvds = intel_de_read(dev_priv, LVDS); 4352 4353 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 4354 DPLL_FPA01_P1_POST_DIV_SHIFT); 4355 4356 if (lvds & LVDS_CLKB_POWER_UP) 4357 clock.p2 = 7; 4358 else 4359 clock.p2 = 14; 4360 } else { 4361 if (dpll & PLL_P1_DIVIDE_BY_TWO) 4362 clock.p1 = 2; 4363 else { 4364 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 4365 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 4366 } 4367 if (dpll & PLL_P2_DIVIDE_BY_4) 4368 clock.p2 = 4; 4369 else 4370 clock.p2 = 2; 4371 } 4372 4373 port_clock = i9xx_calc_dpll_params(refclk, &clock); 4374 } 4375 4376 /* 4377 * This value includes pixel_multiplier. We will use 4378 * port_clock to compute adjusted_mode.crtc_clock in the 4379 * encoder's get_config() function. 4380 */ 4381 pipe_config->port_clock = port_clock; 4382 } 4383 4384 int intel_dotclock_calculate(int link_freq, 4385 const struct intel_link_m_n *m_n) 4386 { 4387 /* 4388 * The calculation for the data clock is: 4389 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp 4390 * But we want to avoid losing precison if possible, so: 4391 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) 4392 * 4393 * and the link clock is simpler: 4394 * link_clock = (m * link_clock) / n 4395 */ 4396 4397 if (!m_n->link_n) 4398 return 0; 4399 4400 return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq), 4401 m_n->link_n); 4402 } 4403 4404 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config) 4405 { 4406 int dotclock; 4407 4408 if (intel_crtc_has_dp_encoder(pipe_config)) 4409 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 4410 &pipe_config->dp_m_n); 4411 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) 4412 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24, 4413 pipe_config->pipe_bpp); 4414 else 4415 dotclock = pipe_config->port_clock; 4416 4417 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 4418 !intel_crtc_has_dp_encoder(pipe_config)) 4419 dotclock *= 2; 4420 4421 if (pipe_config->pixel_multiplier) 4422 dotclock /= pipe_config->pixel_multiplier; 4423 4424 return dotclock; 4425 } 4426 4427 /* Returns the currently programmed mode of the given encoder. */ 4428 struct drm_display_mode * 4429 intel_encoder_current_mode(struct intel_encoder *encoder) 4430 { 4431 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4432 struct intel_crtc_state *crtc_state; 4433 struct drm_display_mode *mode; 4434 struct intel_crtc *crtc; 4435 enum pipe pipe; 4436 4437 if (!encoder->get_hw_state(encoder, &pipe)) 4438 return NULL; 4439 4440 crtc = intel_crtc_for_pipe(dev_priv, pipe); 4441 4442 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 4443 if (!mode) 4444 return NULL; 4445 4446 crtc_state = intel_crtc_state_alloc(crtc); 4447 if (!crtc_state) { 4448 kfree(mode); 4449 return NULL; 4450 } 4451 4452 if (!intel_crtc_get_pipe_config(crtc_state)) { 4453 kfree(crtc_state); 4454 kfree(mode); 4455 return NULL; 4456 } 4457 4458 intel_encoder_get_config(encoder, crtc_state); 4459 4460 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode); 4461 4462 kfree(crtc_state); 4463 4464 return mode; 4465 } 4466 4467 static bool encoders_cloneable(const struct intel_encoder *a, 4468 const struct intel_encoder *b) 4469 { 4470 /* masks could be asymmetric, so check both ways */ 4471 return a == b || (a->cloneable & BIT(b->type) && 4472 b->cloneable & BIT(a->type)); 4473 } 4474 4475 static bool check_single_encoder_cloning(struct intel_atomic_state *state, 4476 struct intel_crtc *crtc, 4477 struct intel_encoder *encoder) 4478 { 4479 struct intel_encoder *source_encoder; 4480 struct drm_connector *connector; 4481 struct drm_connector_state *connector_state; 4482 int i; 4483 4484 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4485 if (connector_state->crtc != &crtc->base) 4486 continue; 4487 4488 source_encoder = 4489 to_intel_encoder(connector_state->best_encoder); 4490 if (!encoders_cloneable(encoder, source_encoder)) 4491 return false; 4492 } 4493 4494 return true; 4495 } 4496 4497 static int icl_add_linked_planes(struct intel_atomic_state *state) 4498 { 4499 struct intel_plane *plane, *linked; 4500 struct intel_plane_state *plane_state, *linked_plane_state; 4501 int i; 4502 4503 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4504 linked = plane_state->planar_linked_plane; 4505 4506 if (!linked) 4507 continue; 4508 4509 linked_plane_state = intel_atomic_get_plane_state(state, linked); 4510 if (IS_ERR(linked_plane_state)) 4511 return PTR_ERR(linked_plane_state); 4512 4513 drm_WARN_ON(state->base.dev, 4514 linked_plane_state->planar_linked_plane != plane); 4515 drm_WARN_ON(state->base.dev, 4516 linked_plane_state->planar_slave == plane_state->planar_slave); 4517 } 4518 4519 return 0; 4520 } 4521 4522 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state) 4523 { 4524 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4525 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4526 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 4527 struct intel_plane *plane, *linked; 4528 struct intel_plane_state *plane_state; 4529 int i; 4530 4531 if (DISPLAY_VER(dev_priv) < 11) 4532 return 0; 4533 4534 /* 4535 * Destroy all old plane links and make the slave plane invisible 4536 * in the crtc_state->active_planes mask. 4537 */ 4538 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4539 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane) 4540 continue; 4541 4542 plane_state->planar_linked_plane = NULL; 4543 if (plane_state->planar_slave && !plane_state->uapi.visible) { 4544 crtc_state->enabled_planes &= ~BIT(plane->id); 4545 crtc_state->active_planes &= ~BIT(plane->id); 4546 crtc_state->update_planes |= BIT(plane->id); 4547 crtc_state->data_rate[plane->id] = 0; 4548 crtc_state->rel_data_rate[plane->id] = 0; 4549 } 4550 4551 plane_state->planar_slave = false; 4552 } 4553 4554 if (!crtc_state->nv12_planes) 4555 return 0; 4556 4557 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4558 struct intel_plane_state *linked_state = NULL; 4559 4560 if (plane->pipe != crtc->pipe || 4561 !(crtc_state->nv12_planes & BIT(plane->id))) 4562 continue; 4563 4564 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) { 4565 if (!icl_is_nv12_y_plane(dev_priv, linked->id)) 4566 continue; 4567 4568 if (crtc_state->active_planes & BIT(linked->id)) 4569 continue; 4570 4571 linked_state = intel_atomic_get_plane_state(state, linked); 4572 if (IS_ERR(linked_state)) 4573 return PTR_ERR(linked_state); 4574 4575 break; 4576 } 4577 4578 if (!linked_state) { 4579 drm_dbg_kms(&dev_priv->drm, 4580 "Need %d free Y planes for planar YUV\n", 4581 hweight8(crtc_state->nv12_planes)); 4582 4583 return -EINVAL; 4584 } 4585 4586 plane_state->planar_linked_plane = linked; 4587 4588 linked_state->planar_slave = true; 4589 linked_state->planar_linked_plane = plane; 4590 crtc_state->enabled_planes |= BIT(linked->id); 4591 crtc_state->active_planes |= BIT(linked->id); 4592 crtc_state->update_planes |= BIT(linked->id); 4593 crtc_state->data_rate[linked->id] = 4594 crtc_state->data_rate_y[plane->id]; 4595 crtc_state->rel_data_rate[linked->id] = 4596 crtc_state->rel_data_rate_y[plane->id]; 4597 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n", 4598 linked->base.name, plane->base.name); 4599 4600 /* Copy parameters to slave plane */ 4601 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE; 4602 linked_state->color_ctl = plane_state->color_ctl; 4603 linked_state->view = plane_state->view; 4604 linked_state->decrypt = plane_state->decrypt; 4605 4606 intel_plane_copy_hw_state(linked_state, plane_state); 4607 linked_state->uapi.src = plane_state->uapi.src; 4608 linked_state->uapi.dst = plane_state->uapi.dst; 4609 4610 if (icl_is_hdr_plane(dev_priv, plane->id)) { 4611 if (linked->id == PLANE_SPRITE5) 4612 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL; 4613 else if (linked->id == PLANE_SPRITE4) 4614 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL; 4615 else if (linked->id == PLANE_SPRITE3) 4616 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL; 4617 else if (linked->id == PLANE_SPRITE2) 4618 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL; 4619 else 4620 MISSING_CASE(linked->id); 4621 } 4622 } 4623 4624 return 0; 4625 } 4626 4627 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state) 4628 { 4629 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 4630 struct intel_atomic_state *state = 4631 to_intel_atomic_state(new_crtc_state->uapi.state); 4632 const struct intel_crtc_state *old_crtc_state = 4633 intel_atomic_get_old_crtc_state(state, crtc); 4634 4635 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes; 4636 } 4637 4638 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) 4639 { 4640 const struct drm_display_mode *pipe_mode = 4641 &crtc_state->hw.pipe_mode; 4642 int linetime_wm; 4643 4644 if (!crtc_state->hw.enable) 4645 return 0; 4646 4647 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4648 pipe_mode->crtc_clock); 4649 4650 return min(linetime_wm, 0x1ff); 4651 } 4652 4653 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, 4654 const struct intel_cdclk_state *cdclk_state) 4655 { 4656 const struct drm_display_mode *pipe_mode = 4657 &crtc_state->hw.pipe_mode; 4658 int linetime_wm; 4659 4660 if (!crtc_state->hw.enable) 4661 return 0; 4662 4663 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4664 cdclk_state->logical.cdclk); 4665 4666 return min(linetime_wm, 0x1ff); 4667 } 4668 4669 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) 4670 { 4671 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4672 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4673 const struct drm_display_mode *pipe_mode = 4674 &crtc_state->hw.pipe_mode; 4675 int linetime_wm; 4676 4677 if (!crtc_state->hw.enable) 4678 return 0; 4679 4680 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8, 4681 crtc_state->pixel_rate); 4682 4683 /* Display WA #1135: BXT:ALL GLK:ALL */ 4684 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 4685 skl_watermark_ipc_enabled(dev_priv)) 4686 linetime_wm /= 2; 4687 4688 return min(linetime_wm, 0x1ff); 4689 } 4690 4691 static int hsw_compute_linetime_wm(struct intel_atomic_state *state, 4692 struct intel_crtc *crtc) 4693 { 4694 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4695 struct intel_crtc_state *crtc_state = 4696 intel_atomic_get_new_crtc_state(state, crtc); 4697 const struct intel_cdclk_state *cdclk_state; 4698 4699 if (DISPLAY_VER(dev_priv) >= 9) 4700 crtc_state->linetime = skl_linetime_wm(crtc_state); 4701 else 4702 crtc_state->linetime = hsw_linetime_wm(crtc_state); 4703 4704 if (!hsw_crtc_supports_ips(crtc)) 4705 return 0; 4706 4707 cdclk_state = intel_atomic_get_cdclk_state(state); 4708 if (IS_ERR(cdclk_state)) 4709 return PTR_ERR(cdclk_state); 4710 4711 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state, 4712 cdclk_state); 4713 4714 return 0; 4715 } 4716 4717 static int intel_crtc_atomic_check(struct intel_atomic_state *state, 4718 struct intel_crtc *crtc) 4719 { 4720 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4721 struct intel_crtc_state *crtc_state = 4722 intel_atomic_get_new_crtc_state(state, crtc); 4723 int ret; 4724 4725 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) && 4726 intel_crtc_needs_modeset(crtc_state) && 4727 !crtc_state->hw.active) 4728 crtc_state->update_wm_post = true; 4729 4730 if (intel_crtc_needs_modeset(crtc_state)) { 4731 ret = intel_dpll_crtc_get_shared_dpll(state, crtc); 4732 if (ret) 4733 return ret; 4734 } 4735 4736 /* 4737 * May need to update pipe gamma enable bits 4738 * when C8 planes are getting enabled/disabled. 4739 */ 4740 if (c8_planes_changed(crtc_state)) 4741 crtc_state->uapi.color_mgmt_changed = true; 4742 4743 if (intel_crtc_needs_color_update(crtc_state)) { 4744 ret = intel_color_check(crtc_state); 4745 if (ret) 4746 return ret; 4747 } 4748 4749 ret = intel_compute_pipe_wm(state, crtc); 4750 if (ret) { 4751 drm_dbg_kms(&dev_priv->drm, 4752 "Target pipe watermarks are invalid\n"); 4753 return ret; 4754 } 4755 4756 /* 4757 * Calculate 'intermediate' watermarks that satisfy both the 4758 * old state and the new state. We can program these 4759 * immediately. 4760 */ 4761 ret = intel_compute_intermediate_wm(state, crtc); 4762 if (ret) { 4763 drm_dbg_kms(&dev_priv->drm, 4764 "No valid intermediate pipe watermarks are possible\n"); 4765 return ret; 4766 } 4767 4768 if (DISPLAY_VER(dev_priv) >= 9) { 4769 if (intel_crtc_needs_modeset(crtc_state) || 4770 intel_crtc_needs_fastset(crtc_state)) { 4771 ret = skl_update_scaler_crtc(crtc_state); 4772 if (ret) 4773 return ret; 4774 } 4775 4776 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state); 4777 if (ret) 4778 return ret; 4779 } 4780 4781 if (HAS_IPS(dev_priv)) { 4782 ret = hsw_ips_compute_config(state, crtc); 4783 if (ret) 4784 return ret; 4785 } 4786 4787 if (DISPLAY_VER(dev_priv) >= 9 || 4788 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 4789 ret = hsw_compute_linetime_wm(state, crtc); 4790 if (ret) 4791 return ret; 4792 4793 } 4794 4795 ret = intel_psr2_sel_fetch_update(state, crtc); 4796 if (ret) 4797 return ret; 4798 4799 return 0; 4800 } 4801 4802 static int 4803 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state, 4804 struct intel_crtc_state *crtc_state) 4805 { 4806 struct drm_connector *connector = conn_state->connector; 4807 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 4808 const struct drm_display_info *info = &connector->display_info; 4809 int bpp; 4810 4811 switch (conn_state->max_bpc) { 4812 case 6 ... 7: 4813 bpp = 6 * 3; 4814 break; 4815 case 8 ... 9: 4816 bpp = 8 * 3; 4817 break; 4818 case 10 ... 11: 4819 bpp = 10 * 3; 4820 break; 4821 case 12 ... 16: 4822 bpp = 12 * 3; 4823 break; 4824 default: 4825 MISSING_CASE(conn_state->max_bpc); 4826 return -EINVAL; 4827 } 4828 4829 if (bpp < crtc_state->pipe_bpp) { 4830 drm_dbg_kms(&i915->drm, 4831 "[CONNECTOR:%d:%s] Limiting display bpp to %d " 4832 "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n", 4833 connector->base.id, connector->name, 4834 bpp, 3 * info->bpc, 4835 3 * conn_state->max_requested_bpc, 4836 crtc_state->pipe_bpp); 4837 4838 crtc_state->pipe_bpp = bpp; 4839 } 4840 4841 return 0; 4842 } 4843 4844 static int 4845 compute_baseline_pipe_bpp(struct intel_atomic_state *state, 4846 struct intel_crtc *crtc) 4847 { 4848 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4849 struct intel_crtc_state *crtc_state = 4850 intel_atomic_get_new_crtc_state(state, crtc); 4851 struct drm_connector *connector; 4852 struct drm_connector_state *connector_state; 4853 int bpp, i; 4854 4855 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 4856 IS_CHERRYVIEW(dev_priv))) 4857 bpp = 10*3; 4858 else if (DISPLAY_VER(dev_priv) >= 5) 4859 bpp = 12*3; 4860 else 4861 bpp = 8*3; 4862 4863 crtc_state->pipe_bpp = bpp; 4864 4865 /* Clamp display bpp to connector max bpp */ 4866 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4867 int ret; 4868 4869 if (connector_state->crtc != &crtc->base) 4870 continue; 4871 4872 ret = compute_sink_pipe_bpp(connector_state, crtc_state); 4873 if (ret) 4874 return ret; 4875 } 4876 4877 return 0; 4878 } 4879 4880 static bool check_digital_port_conflicts(struct intel_atomic_state *state) 4881 { 4882 struct drm_device *dev = state->base.dev; 4883 struct drm_connector *connector; 4884 struct drm_connector_list_iter conn_iter; 4885 unsigned int used_ports = 0; 4886 unsigned int used_mst_ports = 0; 4887 bool ret = true; 4888 4889 /* 4890 * We're going to peek into connector->state, 4891 * hence connection_mutex must be held. 4892 */ 4893 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex); 4894 4895 /* 4896 * Walk the connector list instead of the encoder 4897 * list to detect the problem on ddi platforms 4898 * where there's just one encoder per digital port. 4899 */ 4900 drm_connector_list_iter_begin(dev, &conn_iter); 4901 drm_for_each_connector_iter(connector, &conn_iter) { 4902 struct drm_connector_state *connector_state; 4903 struct intel_encoder *encoder; 4904 4905 connector_state = 4906 drm_atomic_get_new_connector_state(&state->base, 4907 connector); 4908 if (!connector_state) 4909 connector_state = connector->state; 4910 4911 if (!connector_state->best_encoder) 4912 continue; 4913 4914 encoder = to_intel_encoder(connector_state->best_encoder); 4915 4916 drm_WARN_ON(dev, !connector_state->crtc); 4917 4918 switch (encoder->type) { 4919 case INTEL_OUTPUT_DDI: 4920 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev)))) 4921 break; 4922 fallthrough; 4923 case INTEL_OUTPUT_DP: 4924 case INTEL_OUTPUT_HDMI: 4925 case INTEL_OUTPUT_EDP: 4926 /* the same port mustn't appear more than once */ 4927 if (used_ports & BIT(encoder->port)) 4928 ret = false; 4929 4930 used_ports |= BIT(encoder->port); 4931 break; 4932 case INTEL_OUTPUT_DP_MST: 4933 used_mst_ports |= 4934 1 << encoder->port; 4935 break; 4936 default: 4937 break; 4938 } 4939 } 4940 drm_connector_list_iter_end(&conn_iter); 4941 4942 /* can't mix MST and SST/HDMI on the same port */ 4943 if (used_ports & used_mst_ports) 4944 return false; 4945 4946 return ret; 4947 } 4948 4949 static void 4950 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state, 4951 struct intel_crtc *crtc) 4952 { 4953 struct intel_crtc_state *crtc_state = 4954 intel_atomic_get_new_crtc_state(state, crtc); 4955 4956 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 4957 4958 drm_property_replace_blob(&crtc_state->hw.degamma_lut, 4959 crtc_state->uapi.degamma_lut); 4960 drm_property_replace_blob(&crtc_state->hw.gamma_lut, 4961 crtc_state->uapi.gamma_lut); 4962 drm_property_replace_blob(&crtc_state->hw.ctm, 4963 crtc_state->uapi.ctm); 4964 } 4965 4966 static void 4967 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state, 4968 struct intel_crtc *crtc) 4969 { 4970 struct intel_crtc_state *crtc_state = 4971 intel_atomic_get_new_crtc_state(state, crtc); 4972 4973 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 4974 4975 crtc_state->hw.enable = crtc_state->uapi.enable; 4976 crtc_state->hw.active = crtc_state->uapi.active; 4977 drm_mode_copy(&crtc_state->hw.mode, 4978 &crtc_state->uapi.mode); 4979 drm_mode_copy(&crtc_state->hw.adjusted_mode, 4980 &crtc_state->uapi.adjusted_mode); 4981 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter; 4982 4983 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 4984 } 4985 4986 static void 4987 copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state, 4988 struct intel_crtc *slave_crtc) 4989 { 4990 struct intel_crtc_state *slave_crtc_state = 4991 intel_atomic_get_new_crtc_state(state, slave_crtc); 4992 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 4993 const struct intel_crtc_state *master_crtc_state = 4994 intel_atomic_get_new_crtc_state(state, master_crtc); 4995 4996 drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut, 4997 master_crtc_state->hw.degamma_lut); 4998 drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut, 4999 master_crtc_state->hw.gamma_lut); 5000 drm_property_replace_blob(&slave_crtc_state->hw.ctm, 5001 master_crtc_state->hw.ctm); 5002 5003 slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed; 5004 } 5005 5006 static int 5007 copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state, 5008 struct intel_crtc *slave_crtc) 5009 { 5010 struct intel_crtc_state *slave_crtc_state = 5011 intel_atomic_get_new_crtc_state(state, slave_crtc); 5012 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 5013 const struct intel_crtc_state *master_crtc_state = 5014 intel_atomic_get_new_crtc_state(state, master_crtc); 5015 struct intel_crtc_state *saved_state; 5016 5017 WARN_ON(master_crtc_state->bigjoiner_pipes != 5018 slave_crtc_state->bigjoiner_pipes); 5019 5020 saved_state = kmemdup(master_crtc_state, sizeof(*saved_state), GFP_KERNEL); 5021 if (!saved_state) 5022 return -ENOMEM; 5023 5024 /* preserve some things from the slave's original crtc state */ 5025 saved_state->uapi = slave_crtc_state->uapi; 5026 saved_state->scaler_state = slave_crtc_state->scaler_state; 5027 saved_state->shared_dpll = slave_crtc_state->shared_dpll; 5028 saved_state->dpll_hw_state = slave_crtc_state->dpll_hw_state; 5029 saved_state->crc_enabled = slave_crtc_state->crc_enabled; 5030 5031 intel_crtc_free_hw_state(slave_crtc_state); 5032 memcpy(slave_crtc_state, saved_state, sizeof(*slave_crtc_state)); 5033 kfree(saved_state); 5034 5035 /* Re-init hw state */ 5036 memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw)); 5037 slave_crtc_state->hw.enable = master_crtc_state->hw.enable; 5038 slave_crtc_state->hw.active = master_crtc_state->hw.active; 5039 drm_mode_copy(&slave_crtc_state->hw.mode, 5040 &master_crtc_state->hw.mode); 5041 drm_mode_copy(&slave_crtc_state->hw.pipe_mode, 5042 &master_crtc_state->hw.pipe_mode); 5043 drm_mode_copy(&slave_crtc_state->hw.adjusted_mode, 5044 &master_crtc_state->hw.adjusted_mode); 5045 slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter; 5046 5047 copy_bigjoiner_crtc_state_nomodeset(state, slave_crtc); 5048 5049 slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed; 5050 slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed; 5051 slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed; 5052 5053 WARN_ON(master_crtc_state->bigjoiner_pipes != 5054 slave_crtc_state->bigjoiner_pipes); 5055 5056 return 0; 5057 } 5058 5059 static int 5060 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state, 5061 struct intel_crtc *crtc) 5062 { 5063 struct intel_crtc_state *crtc_state = 5064 intel_atomic_get_new_crtc_state(state, crtc); 5065 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5066 struct intel_crtc_state *saved_state; 5067 5068 saved_state = intel_crtc_state_alloc(crtc); 5069 if (!saved_state) 5070 return -ENOMEM; 5071 5072 /* free the old crtc_state->hw members */ 5073 intel_crtc_free_hw_state(crtc_state); 5074 5075 /* FIXME: before the switch to atomic started, a new pipe_config was 5076 * kzalloc'd. Code that depends on any field being zero should be 5077 * fixed, so that the crtc_state can be safely duplicated. For now, 5078 * only fields that are know to not cause problems are preserved. */ 5079 5080 saved_state->uapi = crtc_state->uapi; 5081 saved_state->scaler_state = crtc_state->scaler_state; 5082 saved_state->shared_dpll = crtc_state->shared_dpll; 5083 saved_state->dpll_hw_state = crtc_state->dpll_hw_state; 5084 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, 5085 sizeof(saved_state->icl_port_dplls)); 5086 saved_state->crc_enabled = crtc_state->crc_enabled; 5087 if (IS_G4X(dev_priv) || 5088 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5089 saved_state->wm = crtc_state->wm; 5090 5091 memcpy(crtc_state, saved_state, sizeof(*crtc_state)); 5092 kfree(saved_state); 5093 5094 intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc); 5095 5096 return 0; 5097 } 5098 5099 static int 5100 intel_modeset_pipe_config(struct intel_atomic_state *state, 5101 struct intel_crtc *crtc) 5102 { 5103 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 5104 struct intel_crtc_state *crtc_state = 5105 intel_atomic_get_new_crtc_state(state, crtc); 5106 struct drm_connector *connector; 5107 struct drm_connector_state *connector_state; 5108 int pipe_src_w, pipe_src_h; 5109 int base_bpp, ret, i; 5110 bool retry = true; 5111 5112 crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe; 5113 5114 crtc_state->framestart_delay = 1; 5115 5116 /* 5117 * Sanitize sync polarity flags based on requested ones. If neither 5118 * positive or negative polarity is requested, treat this as meaning 5119 * negative polarity. 5120 */ 5121 if (!(crtc_state->hw.adjusted_mode.flags & 5122 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) 5123 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; 5124 5125 if (!(crtc_state->hw.adjusted_mode.flags & 5126 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 5127 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; 5128 5129 ret = compute_baseline_pipe_bpp(state, crtc); 5130 if (ret) 5131 return ret; 5132 5133 base_bpp = crtc_state->pipe_bpp; 5134 5135 /* 5136 * Determine the real pipe dimensions. Note that stereo modes can 5137 * increase the actual pipe size due to the frame doubling and 5138 * insertion of additional space for blanks between the frame. This 5139 * is stored in the crtc timings. We use the requested mode to do this 5140 * computation to clearly distinguish it from the adjusted mode, which 5141 * can be changed by the connectors in the below retry loop. 5142 */ 5143 drm_mode_get_hv_timing(&crtc_state->hw.mode, 5144 &pipe_src_w, &pipe_src_h); 5145 drm_rect_init(&crtc_state->pipe_src, 0, 0, 5146 pipe_src_w, pipe_src_h); 5147 5148 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5149 struct intel_encoder *encoder = 5150 to_intel_encoder(connector_state->best_encoder); 5151 5152 if (connector_state->crtc != &crtc->base) 5153 continue; 5154 5155 if (!check_single_encoder_cloning(state, crtc, encoder)) { 5156 drm_dbg_kms(&i915->drm, 5157 "[ENCODER:%d:%s] rejecting invalid cloning configuration\n", 5158 encoder->base.base.id, encoder->base.name); 5159 return -EINVAL; 5160 } 5161 5162 /* 5163 * Determine output_types before calling the .compute_config() 5164 * hooks so that the hooks can use this information safely. 5165 */ 5166 if (encoder->compute_output_type) 5167 crtc_state->output_types |= 5168 BIT(encoder->compute_output_type(encoder, crtc_state, 5169 connector_state)); 5170 else 5171 crtc_state->output_types |= BIT(encoder->type); 5172 } 5173 5174 encoder_retry: 5175 /* Ensure the port clock defaults are reset when retrying. */ 5176 crtc_state->port_clock = 0; 5177 crtc_state->pixel_multiplier = 1; 5178 5179 /* Fill in default crtc timings, allow encoders to overwrite them. */ 5180 drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode, 5181 CRTC_STEREO_DOUBLE); 5182 5183 /* Pass our mode to the connectors and the CRTC to give them a chance to 5184 * adjust it according to limitations or connector properties, and also 5185 * a chance to reject the mode entirely. 5186 */ 5187 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5188 struct intel_encoder *encoder = 5189 to_intel_encoder(connector_state->best_encoder); 5190 5191 if (connector_state->crtc != &crtc->base) 5192 continue; 5193 5194 ret = encoder->compute_config(encoder, crtc_state, 5195 connector_state); 5196 if (ret == -EDEADLK) 5197 return ret; 5198 if (ret < 0) { 5199 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n", 5200 encoder->base.base.id, encoder->base.name, ret); 5201 return ret; 5202 } 5203 } 5204 5205 /* Set default port clock if not overwritten by the encoder. Needs to be 5206 * done afterwards in case the encoder adjusts the mode. */ 5207 if (!crtc_state->port_clock) 5208 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock 5209 * crtc_state->pixel_multiplier; 5210 5211 ret = intel_crtc_compute_config(state, crtc); 5212 if (ret == -EDEADLK) 5213 return ret; 5214 if (ret == -EAGAIN) { 5215 if (drm_WARN(&i915->drm, !retry, 5216 "[CRTC:%d:%s] loop in pipe configuration computation\n", 5217 crtc->base.base.id, crtc->base.name)) 5218 return -EINVAL; 5219 5220 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] bw constrained, retrying\n", 5221 crtc->base.base.id, crtc->base.name); 5222 retry = false; 5223 goto encoder_retry; 5224 } 5225 if (ret < 0) { 5226 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n", 5227 crtc->base.base.id, crtc->base.name, ret); 5228 return ret; 5229 } 5230 5231 /* Dithering seems to not pass-through bits correctly when it should, so 5232 * only enable it on 6bpc panels and when its not a compliance 5233 * test requesting 6bpc video pattern. 5234 */ 5235 crtc_state->dither = (crtc_state->pipe_bpp == 6*3) && 5236 !crtc_state->dither_force_disable; 5237 drm_dbg_kms(&i915->drm, 5238 "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n", 5239 crtc->base.base.id, crtc->base.name, 5240 base_bpp, crtc_state->pipe_bpp, crtc_state->dither); 5241 5242 return 0; 5243 } 5244 5245 static int 5246 intel_modeset_pipe_config_late(struct intel_atomic_state *state, 5247 struct intel_crtc *crtc) 5248 { 5249 struct intel_crtc_state *crtc_state = 5250 intel_atomic_get_new_crtc_state(state, crtc); 5251 struct drm_connector_state *conn_state; 5252 struct drm_connector *connector; 5253 int i; 5254 5255 intel_bigjoiner_adjust_pipe_src(crtc_state); 5256 5257 for_each_new_connector_in_state(&state->base, connector, 5258 conn_state, i) { 5259 struct intel_encoder *encoder = 5260 to_intel_encoder(conn_state->best_encoder); 5261 int ret; 5262 5263 if (conn_state->crtc != &crtc->base || 5264 !encoder->compute_config_late) 5265 continue; 5266 5267 ret = encoder->compute_config_late(encoder, crtc_state, 5268 conn_state); 5269 if (ret) 5270 return ret; 5271 } 5272 5273 return 0; 5274 } 5275 5276 bool intel_fuzzy_clock_check(int clock1, int clock2) 5277 { 5278 int diff; 5279 5280 if (clock1 == clock2) 5281 return true; 5282 5283 if (!clock1 || !clock2) 5284 return false; 5285 5286 diff = abs(clock1 - clock2); 5287 5288 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) 5289 return true; 5290 5291 return false; 5292 } 5293 5294 static bool 5295 intel_compare_link_m_n(const struct intel_link_m_n *m_n, 5296 const struct intel_link_m_n *m2_n2) 5297 { 5298 return m_n->tu == m2_n2->tu && 5299 m_n->data_m == m2_n2->data_m && 5300 m_n->data_n == m2_n2->data_n && 5301 m_n->link_m == m2_n2->link_m && 5302 m_n->link_n == m2_n2->link_n; 5303 } 5304 5305 static bool 5306 intel_compare_infoframe(const union hdmi_infoframe *a, 5307 const union hdmi_infoframe *b) 5308 { 5309 return memcmp(a, b, sizeof(*a)) == 0; 5310 } 5311 5312 static bool 5313 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a, 5314 const struct drm_dp_vsc_sdp *b) 5315 { 5316 return memcmp(a, b, sizeof(*a)) == 0; 5317 } 5318 5319 static bool 5320 intel_compare_buffer(const u8 *a, const u8 *b, size_t len) 5321 { 5322 return memcmp(a, b, len) == 0; 5323 } 5324 5325 static void 5326 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv, 5327 bool fastset, const char *name, 5328 const union hdmi_infoframe *a, 5329 const union hdmi_infoframe *b) 5330 { 5331 if (fastset) { 5332 if (!drm_debug_enabled(DRM_UT_KMS)) 5333 return; 5334 5335 drm_dbg_kms(&dev_priv->drm, 5336 "fastset mismatch in %s infoframe\n", name); 5337 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 5338 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a); 5339 drm_dbg_kms(&dev_priv->drm, "found:\n"); 5340 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b); 5341 } else { 5342 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name); 5343 drm_err(&dev_priv->drm, "expected:\n"); 5344 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a); 5345 drm_err(&dev_priv->drm, "found:\n"); 5346 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b); 5347 } 5348 } 5349 5350 static void 5351 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv, 5352 bool fastset, const char *name, 5353 const struct drm_dp_vsc_sdp *a, 5354 const struct drm_dp_vsc_sdp *b) 5355 { 5356 if (fastset) { 5357 if (!drm_debug_enabled(DRM_UT_KMS)) 5358 return; 5359 5360 drm_dbg_kms(&dev_priv->drm, 5361 "fastset mismatch in %s dp sdp\n", name); 5362 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 5363 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a); 5364 drm_dbg_kms(&dev_priv->drm, "found:\n"); 5365 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b); 5366 } else { 5367 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name); 5368 drm_err(&dev_priv->drm, "expected:\n"); 5369 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a); 5370 drm_err(&dev_priv->drm, "found:\n"); 5371 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b); 5372 } 5373 } 5374 5375 /* Returns the length up to and including the last differing byte */ 5376 static size_t 5377 memcmp_diff_len(const u8 *a, const u8 *b, size_t len) 5378 { 5379 int i; 5380 5381 for (i = len - 1; i >= 0; i--) { 5382 if (a[i] != b[i]) 5383 return i + 1; 5384 } 5385 5386 return 0; 5387 } 5388 5389 static void 5390 pipe_config_buffer_mismatch(struct drm_i915_private *dev_priv, 5391 bool fastset, const char *name, 5392 const u8 *a, const u8 *b, size_t len) 5393 { 5394 if (fastset) { 5395 if (!drm_debug_enabled(DRM_UT_KMS)) 5396 return; 5397 5398 /* only dump up to the last difference */ 5399 len = memcmp_diff_len(a, b, len); 5400 5401 drm_dbg_kms(&dev_priv->drm, 5402 "fastset mismatch in %s buffer\n", name); 5403 print_hex_dump(KERN_DEBUG, "expected: ", DUMP_PREFIX_NONE, 5404 16, 0, a, len, false); 5405 print_hex_dump(KERN_DEBUG, "found: ", DUMP_PREFIX_NONE, 5406 16, 0, b, len, false); 5407 } else { 5408 /* only dump up to the last difference */ 5409 len = memcmp_diff_len(a, b, len); 5410 5411 drm_err(&dev_priv->drm, "mismatch in %s buffer\n", name); 5412 print_hex_dump(KERN_ERR, "expected: ", DUMP_PREFIX_NONE, 5413 16, 0, a, len, false); 5414 print_hex_dump(KERN_ERR, "found: ", DUMP_PREFIX_NONE, 5415 16, 0, b, len, false); 5416 } 5417 } 5418 5419 static void __printf(4, 5) 5420 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc, 5421 const char *name, const char *format, ...) 5422 { 5423 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 5424 struct va_format vaf; 5425 va_list args; 5426 5427 va_start(args, format); 5428 vaf.fmt = format; 5429 vaf.va = &args; 5430 5431 if (fastset) 5432 drm_dbg_kms(&i915->drm, 5433 "[CRTC:%d:%s] fastset mismatch in %s %pV\n", 5434 crtc->base.base.id, crtc->base.name, name, &vaf); 5435 else 5436 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n", 5437 crtc->base.base.id, crtc->base.name, name, &vaf); 5438 5439 va_end(args); 5440 } 5441 5442 static bool fastboot_enabled(struct drm_i915_private *dev_priv) 5443 { 5444 if (dev_priv->params.fastboot != -1) 5445 return dev_priv->params.fastboot; 5446 5447 /* Enable fastboot by default on Skylake and newer */ 5448 if (DISPLAY_VER(dev_priv) >= 9) 5449 return true; 5450 5451 /* Enable fastboot by default on VLV and CHV */ 5452 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5453 return true; 5454 5455 /* Disabled by default on all others */ 5456 return false; 5457 } 5458 5459 bool 5460 intel_pipe_config_compare(const struct intel_crtc_state *current_config, 5461 const struct intel_crtc_state *pipe_config, 5462 bool fastset) 5463 { 5464 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev); 5465 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 5466 bool ret = true; 5467 bool fixup_inherited = fastset && 5468 current_config->inherited && !pipe_config->inherited; 5469 5470 if (fixup_inherited && !fastboot_enabled(dev_priv)) { 5471 drm_dbg_kms(&dev_priv->drm, 5472 "initial modeset and fastboot not set\n"); 5473 ret = false; 5474 } 5475 5476 #define PIPE_CONF_CHECK_X(name) do { \ 5477 if (current_config->name != pipe_config->name) { \ 5478 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5479 "(expected 0x%08x, found 0x%08x)", \ 5480 current_config->name, \ 5481 pipe_config->name); \ 5482 ret = false; \ 5483 } \ 5484 } while (0) 5485 5486 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \ 5487 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \ 5488 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5489 "(expected 0x%08x, found 0x%08x)", \ 5490 current_config->name & (mask), \ 5491 pipe_config->name & (mask)); \ 5492 ret = false; \ 5493 } \ 5494 } while (0) 5495 5496 #define PIPE_CONF_CHECK_I(name) do { \ 5497 if (current_config->name != pipe_config->name) { \ 5498 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5499 "(expected %i, found %i)", \ 5500 current_config->name, \ 5501 pipe_config->name); \ 5502 ret = false; \ 5503 } \ 5504 } while (0) 5505 5506 #define PIPE_CONF_CHECK_BOOL(name) do { \ 5507 if (current_config->name != pipe_config->name) { \ 5508 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5509 "(expected %s, found %s)", \ 5510 str_yes_no(current_config->name), \ 5511 str_yes_no(pipe_config->name)); \ 5512 ret = false; \ 5513 } \ 5514 } while (0) 5515 5516 /* 5517 * Checks state where we only read out the enabling, but not the entire 5518 * state itself (like full infoframes or ELD for audio). These states 5519 * require a full modeset on bootup to fix up. 5520 */ 5521 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \ 5522 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \ 5523 PIPE_CONF_CHECK_BOOL(name); \ 5524 } else { \ 5525 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5526 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \ 5527 str_yes_no(current_config->name), \ 5528 str_yes_no(pipe_config->name)); \ 5529 ret = false; \ 5530 } \ 5531 } while (0) 5532 5533 #define PIPE_CONF_CHECK_P(name) do { \ 5534 if (current_config->name != pipe_config->name) { \ 5535 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5536 "(expected %p, found %p)", \ 5537 current_config->name, \ 5538 pipe_config->name); \ 5539 ret = false; \ 5540 } \ 5541 } while (0) 5542 5543 #define PIPE_CONF_CHECK_M_N(name) do { \ 5544 if (!intel_compare_link_m_n(¤t_config->name, \ 5545 &pipe_config->name)) { \ 5546 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5547 "(expected tu %i data %i/%i link %i/%i, " \ 5548 "found tu %i, data %i/%i link %i/%i)", \ 5549 current_config->name.tu, \ 5550 current_config->name.data_m, \ 5551 current_config->name.data_n, \ 5552 current_config->name.link_m, \ 5553 current_config->name.link_n, \ 5554 pipe_config->name.tu, \ 5555 pipe_config->name.data_m, \ 5556 pipe_config->name.data_n, \ 5557 pipe_config->name.link_m, \ 5558 pipe_config->name.link_n); \ 5559 ret = false; \ 5560 } \ 5561 } while (0) 5562 5563 #define PIPE_CONF_CHECK_TIMINGS(name) do { \ 5564 PIPE_CONF_CHECK_I(name.crtc_hdisplay); \ 5565 PIPE_CONF_CHECK_I(name.crtc_htotal); \ 5566 PIPE_CONF_CHECK_I(name.crtc_hblank_start); \ 5567 PIPE_CONF_CHECK_I(name.crtc_hblank_end); \ 5568 PIPE_CONF_CHECK_I(name.crtc_hsync_start); \ 5569 PIPE_CONF_CHECK_I(name.crtc_hsync_end); \ 5570 PIPE_CONF_CHECK_I(name.crtc_vdisplay); \ 5571 PIPE_CONF_CHECK_I(name.crtc_vtotal); \ 5572 PIPE_CONF_CHECK_I(name.crtc_vblank_start); \ 5573 PIPE_CONF_CHECK_I(name.crtc_vblank_end); \ 5574 PIPE_CONF_CHECK_I(name.crtc_vsync_start); \ 5575 PIPE_CONF_CHECK_I(name.crtc_vsync_end); \ 5576 } while (0) 5577 5578 #define PIPE_CONF_CHECK_RECT(name) do { \ 5579 PIPE_CONF_CHECK_I(name.x1); \ 5580 PIPE_CONF_CHECK_I(name.x2); \ 5581 PIPE_CONF_CHECK_I(name.y1); \ 5582 PIPE_CONF_CHECK_I(name.y2); \ 5583 } while (0) 5584 5585 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \ 5586 if ((current_config->name ^ pipe_config->name) & (mask)) { \ 5587 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5588 "(%x) (expected %i, found %i)", \ 5589 (mask), \ 5590 current_config->name & (mask), \ 5591 pipe_config->name & (mask)); \ 5592 ret = false; \ 5593 } \ 5594 } while (0) 5595 5596 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \ 5597 if (!intel_compare_infoframe(¤t_config->infoframes.name, \ 5598 &pipe_config->infoframes.name)) { \ 5599 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \ 5600 ¤t_config->infoframes.name, \ 5601 &pipe_config->infoframes.name); \ 5602 ret = false; \ 5603 } \ 5604 } while (0) 5605 5606 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \ 5607 if (!current_config->has_psr && !pipe_config->has_psr && \ 5608 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \ 5609 &pipe_config->infoframes.name)) { \ 5610 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \ 5611 ¤t_config->infoframes.name, \ 5612 &pipe_config->infoframes.name); \ 5613 ret = false; \ 5614 } \ 5615 } while (0) 5616 5617 #define PIPE_CONF_CHECK_BUFFER(name, len) do { \ 5618 BUILD_BUG_ON(sizeof(current_config->name) != (len)); \ 5619 BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \ 5620 if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \ 5621 pipe_config_buffer_mismatch(dev_priv, fastset, __stringify(name), \ 5622 current_config->name, \ 5623 pipe_config->name, \ 5624 (len)); \ 5625 ret = false; \ 5626 } \ 5627 } while (0) 5628 5629 #define PIPE_CONF_CHECK_COLOR_LUT(lut, is_pre_csc_lut) do { \ 5630 if (current_config->gamma_mode == pipe_config->gamma_mode && \ 5631 !intel_color_lut_equal(current_config, \ 5632 current_config->lut, pipe_config->lut, \ 5633 is_pre_csc_lut)) { \ 5634 pipe_config_mismatch(fastset, crtc, __stringify(lut), \ 5635 "hw_state doesn't match sw_state"); \ 5636 ret = false; \ 5637 } \ 5638 } while (0) 5639 5640 #define PIPE_CONF_QUIRK(quirk) \ 5641 ((current_config->quirks | pipe_config->quirks) & (quirk)) 5642 5643 PIPE_CONF_CHECK_I(hw.enable); 5644 PIPE_CONF_CHECK_I(hw.active); 5645 5646 PIPE_CONF_CHECK_I(cpu_transcoder); 5647 PIPE_CONF_CHECK_I(mst_master_transcoder); 5648 5649 PIPE_CONF_CHECK_BOOL(has_pch_encoder); 5650 PIPE_CONF_CHECK_I(fdi_lanes); 5651 PIPE_CONF_CHECK_M_N(fdi_m_n); 5652 5653 PIPE_CONF_CHECK_I(lane_count); 5654 PIPE_CONF_CHECK_X(lane_lat_optim_mask); 5655 5656 if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) { 5657 if (!fastset || !pipe_config->seamless_m_n) 5658 PIPE_CONF_CHECK_M_N(dp_m_n); 5659 } else { 5660 PIPE_CONF_CHECK_M_N(dp_m_n); 5661 PIPE_CONF_CHECK_M_N(dp_m2_n2); 5662 } 5663 5664 PIPE_CONF_CHECK_X(output_types); 5665 5666 PIPE_CONF_CHECK_I(framestart_delay); 5667 PIPE_CONF_CHECK_I(msa_timing_delay); 5668 5669 PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode); 5670 PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode); 5671 5672 PIPE_CONF_CHECK_I(pixel_multiplier); 5673 5674 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5675 DRM_MODE_FLAG_INTERLACE); 5676 5677 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { 5678 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5679 DRM_MODE_FLAG_PHSYNC); 5680 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5681 DRM_MODE_FLAG_NHSYNC); 5682 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5683 DRM_MODE_FLAG_PVSYNC); 5684 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5685 DRM_MODE_FLAG_NVSYNC); 5686 } 5687 5688 PIPE_CONF_CHECK_I(output_format); 5689 PIPE_CONF_CHECK_BOOL(has_hdmi_sink); 5690 if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || 5691 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5692 PIPE_CONF_CHECK_BOOL(limited_color_range); 5693 5694 PIPE_CONF_CHECK_BOOL(hdmi_scrambling); 5695 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio); 5696 PIPE_CONF_CHECK_BOOL(has_infoframe); 5697 PIPE_CONF_CHECK_BOOL(fec_enable); 5698 5699 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio); 5700 PIPE_CONF_CHECK_BUFFER(eld, MAX_ELD_BYTES); 5701 5702 PIPE_CONF_CHECK_X(gmch_pfit.control); 5703 /* pfit ratios are autocomputed by the hw on gen4+ */ 5704 if (DISPLAY_VER(dev_priv) < 4) 5705 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); 5706 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); 5707 5708 /* 5709 * Changing the EDP transcoder input mux 5710 * (A_ONOFF vs. A_ON) requires a full modeset. 5711 */ 5712 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru); 5713 5714 if (!fastset) { 5715 PIPE_CONF_CHECK_RECT(pipe_src); 5716 5717 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled); 5718 PIPE_CONF_CHECK_RECT(pch_pfit.dst); 5719 5720 PIPE_CONF_CHECK_I(scaler_state.scaler_id); 5721 PIPE_CONF_CHECK_I(pixel_rate); 5722 5723 PIPE_CONF_CHECK_X(gamma_mode); 5724 if (IS_CHERRYVIEW(dev_priv)) 5725 PIPE_CONF_CHECK_X(cgm_mode); 5726 else 5727 PIPE_CONF_CHECK_X(csc_mode); 5728 PIPE_CONF_CHECK_BOOL(gamma_enable); 5729 PIPE_CONF_CHECK_BOOL(csc_enable); 5730 5731 PIPE_CONF_CHECK_I(linetime); 5732 PIPE_CONF_CHECK_I(ips_linetime); 5733 5734 PIPE_CONF_CHECK_COLOR_LUT(pre_csc_lut, true); 5735 PIPE_CONF_CHECK_COLOR_LUT(post_csc_lut, false); 5736 5737 if (current_config->active_planes) { 5738 PIPE_CONF_CHECK_BOOL(has_psr); 5739 PIPE_CONF_CHECK_BOOL(has_psr2); 5740 PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); 5741 PIPE_CONF_CHECK_I(dc3co_exitline); 5742 } 5743 } 5744 5745 PIPE_CONF_CHECK_BOOL(double_wide); 5746 5747 if (dev_priv->display.dpll.mgr) { 5748 PIPE_CONF_CHECK_P(shared_dpll); 5749 5750 PIPE_CONF_CHECK_X(dpll_hw_state.dpll); 5751 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); 5752 PIPE_CONF_CHECK_X(dpll_hw_state.fp0); 5753 PIPE_CONF_CHECK_X(dpll_hw_state.fp1); 5754 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); 5755 PIPE_CONF_CHECK_X(dpll_hw_state.spll); 5756 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); 5757 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); 5758 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); 5759 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); 5760 PIPE_CONF_CHECK_X(dpll_hw_state.div0); 5761 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); 5762 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); 5763 PIPE_CONF_CHECK_X(dpll_hw_state.pll0); 5764 PIPE_CONF_CHECK_X(dpll_hw_state.pll1); 5765 PIPE_CONF_CHECK_X(dpll_hw_state.pll2); 5766 PIPE_CONF_CHECK_X(dpll_hw_state.pll3); 5767 PIPE_CONF_CHECK_X(dpll_hw_state.pll6); 5768 PIPE_CONF_CHECK_X(dpll_hw_state.pll8); 5769 PIPE_CONF_CHECK_X(dpll_hw_state.pll9); 5770 PIPE_CONF_CHECK_X(dpll_hw_state.pll10); 5771 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); 5772 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl); 5773 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1); 5774 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl); 5775 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0); 5776 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1); 5777 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf); 5778 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock); 5779 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc); 5780 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias); 5781 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias); 5782 } 5783 5784 PIPE_CONF_CHECK_X(dsi_pll.ctrl); 5785 PIPE_CONF_CHECK_X(dsi_pll.div); 5786 5787 if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5) 5788 PIPE_CONF_CHECK_I(pipe_bpp); 5789 5790 if (!fastset || !pipe_config->seamless_m_n) { 5791 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock); 5792 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock); 5793 } 5794 PIPE_CONF_CHECK_I(port_clock); 5795 5796 PIPE_CONF_CHECK_I(min_voltage_level); 5797 5798 if (current_config->has_psr || pipe_config->has_psr) 5799 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable, 5800 ~intel_hdmi_infoframe_enable(DP_SDP_VSC)); 5801 else 5802 PIPE_CONF_CHECK_X(infoframes.enable); 5803 5804 PIPE_CONF_CHECK_X(infoframes.gcp); 5805 PIPE_CONF_CHECK_INFOFRAME(avi); 5806 PIPE_CONF_CHECK_INFOFRAME(spd); 5807 PIPE_CONF_CHECK_INFOFRAME(hdmi); 5808 PIPE_CONF_CHECK_INFOFRAME(drm); 5809 PIPE_CONF_CHECK_DP_VSC_SDP(vsc); 5810 5811 PIPE_CONF_CHECK_X(sync_mode_slaves_mask); 5812 PIPE_CONF_CHECK_I(master_transcoder); 5813 PIPE_CONF_CHECK_X(bigjoiner_pipes); 5814 5815 PIPE_CONF_CHECK_I(dsc.compression_enable); 5816 PIPE_CONF_CHECK_I(dsc.dsc_split); 5817 PIPE_CONF_CHECK_I(dsc.compressed_bpp); 5818 5819 PIPE_CONF_CHECK_BOOL(splitter.enable); 5820 PIPE_CONF_CHECK_I(splitter.link_count); 5821 PIPE_CONF_CHECK_I(splitter.pixel_overlap); 5822 5823 PIPE_CONF_CHECK_BOOL(vrr.enable); 5824 PIPE_CONF_CHECK_I(vrr.vmin); 5825 PIPE_CONF_CHECK_I(vrr.vmax); 5826 PIPE_CONF_CHECK_I(vrr.flipline); 5827 PIPE_CONF_CHECK_I(vrr.pipeline_full); 5828 PIPE_CONF_CHECK_I(vrr.guardband); 5829 5830 #undef PIPE_CONF_CHECK_X 5831 #undef PIPE_CONF_CHECK_I 5832 #undef PIPE_CONF_CHECK_BOOL 5833 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE 5834 #undef PIPE_CONF_CHECK_P 5835 #undef PIPE_CONF_CHECK_FLAGS 5836 #undef PIPE_CONF_CHECK_COLOR_LUT 5837 #undef PIPE_CONF_CHECK_TIMINGS 5838 #undef PIPE_CONF_CHECK_RECT 5839 #undef PIPE_CONF_QUIRK 5840 5841 return ret; 5842 } 5843 5844 static void 5845 intel_verify_planes(struct intel_atomic_state *state) 5846 { 5847 struct intel_plane *plane; 5848 const struct intel_plane_state *plane_state; 5849 int i; 5850 5851 for_each_new_intel_plane_in_state(state, plane, 5852 plane_state, i) 5853 assert_plane(plane, plane_state->planar_slave || 5854 plane_state->uapi.visible); 5855 } 5856 5857 int intel_modeset_all_pipes(struct intel_atomic_state *state, 5858 const char *reason) 5859 { 5860 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 5861 struct intel_crtc *crtc; 5862 5863 /* 5864 * Add all pipes to the state, and force 5865 * a modeset on all the active ones. 5866 */ 5867 for_each_intel_crtc(&dev_priv->drm, crtc) { 5868 struct intel_crtc_state *crtc_state; 5869 int ret; 5870 5871 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 5872 if (IS_ERR(crtc_state)) 5873 return PTR_ERR(crtc_state); 5874 5875 if (!crtc_state->hw.active || 5876 intel_crtc_needs_modeset(crtc_state)) 5877 continue; 5878 5879 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] Full modeset due to %s\n", 5880 crtc->base.base.id, crtc->base.name, reason); 5881 5882 crtc_state->uapi.mode_changed = true; 5883 crtc_state->update_pipe = false; 5884 5885 ret = drm_atomic_add_affected_connectors(&state->base, 5886 &crtc->base); 5887 if (ret) 5888 return ret; 5889 5890 ret = intel_atomic_add_affected_planes(state, crtc); 5891 if (ret) 5892 return ret; 5893 5894 crtc_state->update_planes |= crtc_state->active_planes; 5895 crtc_state->async_flip_planes = 0; 5896 crtc_state->do_async_flip = false; 5897 } 5898 5899 return 0; 5900 } 5901 5902 void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state) 5903 { 5904 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 5905 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5906 struct drm_display_mode adjusted_mode; 5907 5908 drm_mode_init(&adjusted_mode, &crtc_state->hw.adjusted_mode); 5909 5910 if (crtc_state->vrr.enable) { 5911 adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax; 5912 adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax; 5913 adjusted_mode.crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state); 5914 crtc->vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state); 5915 } 5916 5917 drm_calc_timestamping_constants(&crtc->base, &adjusted_mode); 5918 5919 crtc->mode_flags = crtc_state->mode_flags; 5920 5921 /* 5922 * The scanline counter increments at the leading edge of hsync. 5923 * 5924 * On most platforms it starts counting from vtotal-1 on the 5925 * first active line. That means the scanline counter value is 5926 * always one less than what we would expect. Ie. just after 5927 * start of vblank, which also occurs at start of hsync (on the 5928 * last active line), the scanline counter will read vblank_start-1. 5929 * 5930 * On gen2 the scanline counter starts counting from 1 instead 5931 * of vtotal-1, so we have to subtract one (or rather add vtotal-1 5932 * to keep the value positive), instead of adding one. 5933 * 5934 * On HSW+ the behaviour of the scanline counter depends on the output 5935 * type. For DP ports it behaves like most other platforms, but on HDMI 5936 * there's an extra 1 line difference. So we need to add two instead of 5937 * one to the value. 5938 * 5939 * On VLV/CHV DSI the scanline counter would appear to increment 5940 * approx. 1/3 of a scanline before start of vblank. Unfortunately 5941 * that means we can't tell whether we're in vblank or not while 5942 * we're on that particular line. We must still set scanline_offset 5943 * to 1 so that the vblank timestamps come out correct when we query 5944 * the scanline counter from within the vblank interrupt handler. 5945 * However if queried just before the start of vblank we'll get an 5946 * answer that's slightly in the future. 5947 */ 5948 if (DISPLAY_VER(dev_priv) == 2) { 5949 int vtotal; 5950 5951 vtotal = adjusted_mode.crtc_vtotal; 5952 if (adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 5953 vtotal /= 2; 5954 5955 crtc->scanline_offset = vtotal - 1; 5956 } else if (HAS_DDI(dev_priv) && 5957 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 5958 crtc->scanline_offset = 2; 5959 } else { 5960 crtc->scanline_offset = 1; 5961 } 5962 } 5963 5964 /* 5965 * This implements the workaround described in the "notes" section of the mode 5966 * set sequence documentation. When going from no pipes or single pipe to 5967 * multiple pipes, and planes are enabled after the pipe, we need to wait at 5968 * least 2 vblanks on the first pipe before enabling planes on the second pipe. 5969 */ 5970 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state) 5971 { 5972 struct intel_crtc_state *crtc_state; 5973 struct intel_crtc *crtc; 5974 struct intel_crtc_state *first_crtc_state = NULL; 5975 struct intel_crtc_state *other_crtc_state = NULL; 5976 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; 5977 int i; 5978 5979 /* look at all crtc's that are going to be enabled in during modeset */ 5980 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5981 if (!crtc_state->hw.active || 5982 !intel_crtc_needs_modeset(crtc_state)) 5983 continue; 5984 5985 if (first_crtc_state) { 5986 other_crtc_state = crtc_state; 5987 break; 5988 } else { 5989 first_crtc_state = crtc_state; 5990 first_pipe = crtc->pipe; 5991 } 5992 } 5993 5994 /* No workaround needed? */ 5995 if (!first_crtc_state) 5996 return 0; 5997 5998 /* w/a possibly needed, check how many crtc's are already enabled. */ 5999 for_each_intel_crtc(state->base.dev, crtc) { 6000 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6001 if (IS_ERR(crtc_state)) 6002 return PTR_ERR(crtc_state); 6003 6004 crtc_state->hsw_workaround_pipe = INVALID_PIPE; 6005 6006 if (!crtc_state->hw.active || 6007 intel_crtc_needs_modeset(crtc_state)) 6008 continue; 6009 6010 /* 2 or more enabled crtcs means no need for w/a */ 6011 if (enabled_pipe != INVALID_PIPE) 6012 return 0; 6013 6014 enabled_pipe = crtc->pipe; 6015 } 6016 6017 if (enabled_pipe != INVALID_PIPE) 6018 first_crtc_state->hsw_workaround_pipe = enabled_pipe; 6019 else if (other_crtc_state) 6020 other_crtc_state->hsw_workaround_pipe = first_pipe; 6021 6022 return 0; 6023 } 6024 6025 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 6026 u8 active_pipes) 6027 { 6028 const struct intel_crtc_state *crtc_state; 6029 struct intel_crtc *crtc; 6030 int i; 6031 6032 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6033 if (crtc_state->hw.active) 6034 active_pipes |= BIT(crtc->pipe); 6035 else 6036 active_pipes &= ~BIT(crtc->pipe); 6037 } 6038 6039 return active_pipes; 6040 } 6041 6042 static int intel_modeset_checks(struct intel_atomic_state *state) 6043 { 6044 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6045 6046 state->modeset = true; 6047 6048 if (IS_HASWELL(dev_priv)) 6049 return hsw_mode_set_planes_workaround(state); 6050 6051 return 0; 6052 } 6053 6054 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state, 6055 struct intel_crtc_state *new_crtc_state) 6056 { 6057 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) 6058 return; 6059 6060 new_crtc_state->uapi.mode_changed = false; 6061 if (!intel_crtc_needs_modeset(new_crtc_state)) 6062 new_crtc_state->update_pipe = true; 6063 } 6064 6065 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state, 6066 struct intel_crtc *crtc, 6067 u8 plane_ids_mask) 6068 { 6069 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6070 struct intel_plane *plane; 6071 6072 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 6073 struct intel_plane_state *plane_state; 6074 6075 if ((plane_ids_mask & BIT(plane->id)) == 0) 6076 continue; 6077 6078 plane_state = intel_atomic_get_plane_state(state, plane); 6079 if (IS_ERR(plane_state)) 6080 return PTR_ERR(plane_state); 6081 } 6082 6083 return 0; 6084 } 6085 6086 int intel_atomic_add_affected_planes(struct intel_atomic_state *state, 6087 struct intel_crtc *crtc) 6088 { 6089 const struct intel_crtc_state *old_crtc_state = 6090 intel_atomic_get_old_crtc_state(state, crtc); 6091 const struct intel_crtc_state *new_crtc_state = 6092 intel_atomic_get_new_crtc_state(state, crtc); 6093 6094 return intel_crtc_add_planes_to_state(state, crtc, 6095 old_crtc_state->enabled_planes | 6096 new_crtc_state->enabled_planes); 6097 } 6098 6099 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv) 6100 { 6101 /* See {hsw,vlv,ivb}_plane_ratio() */ 6102 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) || 6103 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) || 6104 IS_IVYBRIDGE(dev_priv); 6105 } 6106 6107 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state, 6108 struct intel_crtc *crtc, 6109 struct intel_crtc *other) 6110 { 6111 const struct intel_plane_state *plane_state; 6112 struct intel_plane *plane; 6113 u8 plane_ids = 0; 6114 int i; 6115 6116 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 6117 if (plane->pipe == crtc->pipe) 6118 plane_ids |= BIT(plane->id); 6119 } 6120 6121 return intel_crtc_add_planes_to_state(state, other, plane_ids); 6122 } 6123 6124 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state) 6125 { 6126 struct drm_i915_private *i915 = to_i915(state->base.dev); 6127 const struct intel_crtc_state *crtc_state; 6128 struct intel_crtc *crtc; 6129 int i; 6130 6131 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6132 struct intel_crtc *other; 6133 6134 for_each_intel_crtc_in_pipe_mask(&i915->drm, other, 6135 crtc_state->bigjoiner_pipes) { 6136 int ret; 6137 6138 if (crtc == other) 6139 continue; 6140 6141 ret = intel_crtc_add_bigjoiner_planes(state, crtc, other); 6142 if (ret) 6143 return ret; 6144 } 6145 } 6146 6147 return 0; 6148 } 6149 6150 static int intel_atomic_check_planes(struct intel_atomic_state *state) 6151 { 6152 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6153 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6154 struct intel_plane_state *plane_state; 6155 struct intel_plane *plane; 6156 struct intel_crtc *crtc; 6157 int i, ret; 6158 6159 ret = icl_add_linked_planes(state); 6160 if (ret) 6161 return ret; 6162 6163 ret = intel_bigjoiner_add_affected_planes(state); 6164 if (ret) 6165 return ret; 6166 6167 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 6168 ret = intel_plane_atomic_check(state, plane); 6169 if (ret) { 6170 drm_dbg_atomic(&dev_priv->drm, 6171 "[PLANE:%d:%s] atomic driver check failed\n", 6172 plane->base.base.id, plane->base.name); 6173 return ret; 6174 } 6175 } 6176 6177 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6178 new_crtc_state, i) { 6179 u8 old_active_planes, new_active_planes; 6180 6181 ret = icl_check_nv12_planes(new_crtc_state); 6182 if (ret) 6183 return ret; 6184 6185 /* 6186 * On some platforms the number of active planes affects 6187 * the planes' minimum cdclk calculation. Add such planes 6188 * to the state before we compute the minimum cdclk. 6189 */ 6190 if (!active_planes_affects_min_cdclk(dev_priv)) 6191 continue; 6192 6193 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 6194 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 6195 6196 if (hweight8(old_active_planes) == hweight8(new_active_planes)) 6197 continue; 6198 6199 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes); 6200 if (ret) 6201 return ret; 6202 } 6203 6204 return 0; 6205 } 6206 6207 static int intel_atomic_check_crtcs(struct intel_atomic_state *state) 6208 { 6209 struct intel_crtc_state *crtc_state; 6210 struct intel_crtc *crtc; 6211 int i; 6212 6213 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6214 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 6215 int ret; 6216 6217 ret = intel_crtc_atomic_check(state, crtc); 6218 if (ret) { 6219 drm_dbg_atomic(&i915->drm, 6220 "[CRTC:%d:%s] atomic driver check failed\n", 6221 crtc->base.base.id, crtc->base.name); 6222 return ret; 6223 } 6224 } 6225 6226 return 0; 6227 } 6228 6229 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, 6230 u8 transcoders) 6231 { 6232 const struct intel_crtc_state *new_crtc_state; 6233 struct intel_crtc *crtc; 6234 int i; 6235 6236 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6237 if (new_crtc_state->hw.enable && 6238 transcoders & BIT(new_crtc_state->cpu_transcoder) && 6239 intel_crtc_needs_modeset(new_crtc_state)) 6240 return true; 6241 } 6242 6243 return false; 6244 } 6245 6246 static bool intel_pipes_need_modeset(struct intel_atomic_state *state, 6247 u8 pipes) 6248 { 6249 const struct intel_crtc_state *new_crtc_state; 6250 struct intel_crtc *crtc; 6251 int i; 6252 6253 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6254 if (new_crtc_state->hw.enable && 6255 pipes & BIT(crtc->pipe) && 6256 intel_crtc_needs_modeset(new_crtc_state)) 6257 return true; 6258 } 6259 6260 return false; 6261 } 6262 6263 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state, 6264 struct intel_crtc *master_crtc) 6265 { 6266 struct drm_i915_private *i915 = to_i915(state->base.dev); 6267 struct intel_crtc_state *master_crtc_state = 6268 intel_atomic_get_new_crtc_state(state, master_crtc); 6269 struct intel_crtc *slave_crtc; 6270 6271 if (!master_crtc_state->bigjoiner_pipes) 6272 return 0; 6273 6274 /* sanity check */ 6275 if (drm_WARN_ON(&i915->drm, 6276 master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state))) 6277 return -EINVAL; 6278 6279 if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) { 6280 drm_dbg_kms(&i915->drm, 6281 "[CRTC:%d:%s] Cannot act as big joiner master " 6282 "(need 0x%x as pipes, only 0x%x possible)\n", 6283 master_crtc->base.base.id, master_crtc->base.name, 6284 master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915)); 6285 return -EINVAL; 6286 } 6287 6288 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 6289 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 6290 struct intel_crtc_state *slave_crtc_state; 6291 int ret; 6292 6293 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc); 6294 if (IS_ERR(slave_crtc_state)) 6295 return PTR_ERR(slave_crtc_state); 6296 6297 /* master being enabled, slave was already configured? */ 6298 if (slave_crtc_state->uapi.enable) { 6299 drm_dbg_kms(&i915->drm, 6300 "[CRTC:%d:%s] Slave is enabled as normal CRTC, but " 6301 "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n", 6302 slave_crtc->base.base.id, slave_crtc->base.name, 6303 master_crtc->base.base.id, master_crtc->base.name); 6304 return -EINVAL; 6305 } 6306 6307 /* 6308 * The state copy logic assumes the master crtc gets processed 6309 * before the slave crtc during the main compute_config loop. 6310 * This works because the crtcs are created in pipe order, 6311 * and the hardware requires master pipe < slave pipe as well. 6312 * Should that change we need to rethink the logic. 6313 */ 6314 if (WARN_ON(drm_crtc_index(&master_crtc->base) > 6315 drm_crtc_index(&slave_crtc->base))) 6316 return -EINVAL; 6317 6318 drm_dbg_kms(&i915->drm, 6319 "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n", 6320 slave_crtc->base.base.id, slave_crtc->base.name, 6321 master_crtc->base.base.id, master_crtc->base.name); 6322 6323 slave_crtc_state->bigjoiner_pipes = 6324 master_crtc_state->bigjoiner_pipes; 6325 6326 ret = copy_bigjoiner_crtc_state_modeset(state, slave_crtc); 6327 if (ret) 6328 return ret; 6329 } 6330 6331 return 0; 6332 } 6333 6334 static void kill_bigjoiner_slave(struct intel_atomic_state *state, 6335 struct intel_crtc *master_crtc) 6336 { 6337 struct drm_i915_private *i915 = to_i915(state->base.dev); 6338 struct intel_crtc_state *master_crtc_state = 6339 intel_atomic_get_new_crtc_state(state, master_crtc); 6340 struct intel_crtc *slave_crtc; 6341 6342 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 6343 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 6344 struct intel_crtc_state *slave_crtc_state = 6345 intel_atomic_get_new_crtc_state(state, slave_crtc); 6346 6347 slave_crtc_state->bigjoiner_pipes = 0; 6348 6349 intel_crtc_copy_uapi_to_hw_state_modeset(state, slave_crtc); 6350 } 6351 6352 master_crtc_state->bigjoiner_pipes = 0; 6353 } 6354 6355 /** 6356 * DOC: asynchronous flip implementation 6357 * 6358 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC 6359 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL. 6360 * Correspondingly, support is currently added for primary plane only. 6361 * 6362 * Async flip can only change the plane surface address, so anything else 6363 * changing is rejected from the intel_async_flip_check_hw() function. 6364 * Once this check is cleared, flip done interrupt is enabled using 6365 * the intel_crtc_enable_flip_done() function. 6366 * 6367 * As soon as the surface address register is written, flip done interrupt is 6368 * generated and the requested events are sent to the usersapce in the interrupt 6369 * handler itself. The timestamp and sequence sent during the flip done event 6370 * correspond to the last vblank and have no relation to the actual time when 6371 * the flip done event was sent. 6372 */ 6373 static int intel_async_flip_check_uapi(struct intel_atomic_state *state, 6374 struct intel_crtc *crtc) 6375 { 6376 struct drm_i915_private *i915 = to_i915(state->base.dev); 6377 const struct intel_crtc_state *new_crtc_state = 6378 intel_atomic_get_new_crtc_state(state, crtc); 6379 const struct intel_plane_state *old_plane_state; 6380 struct intel_plane_state *new_plane_state; 6381 struct intel_plane *plane; 6382 int i; 6383 6384 if (!new_crtc_state->uapi.async_flip) 6385 return 0; 6386 6387 if (!new_crtc_state->uapi.active) { 6388 drm_dbg_kms(&i915->drm, 6389 "[CRTC:%d:%s] not active\n", 6390 crtc->base.base.id, crtc->base.name); 6391 return -EINVAL; 6392 } 6393 6394 if (intel_crtc_needs_modeset(new_crtc_state)) { 6395 drm_dbg_kms(&i915->drm, 6396 "[CRTC:%d:%s] modeset required\n", 6397 crtc->base.base.id, crtc->base.name); 6398 return -EINVAL; 6399 } 6400 6401 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 6402 new_plane_state, i) { 6403 if (plane->pipe != crtc->pipe) 6404 continue; 6405 6406 /* 6407 * TODO: Async flip is only supported through the page flip IOCTL 6408 * as of now. So support currently added for primary plane only. 6409 * Support for other planes on platforms on which supports 6410 * this(vlv/chv and icl+) should be added when async flip is 6411 * enabled in the atomic IOCTL path. 6412 */ 6413 if (!plane->async_flip) { 6414 drm_dbg_kms(&i915->drm, 6415 "[PLANE:%d:%s] async flip not supported\n", 6416 plane->base.base.id, plane->base.name); 6417 return -EINVAL; 6418 } 6419 6420 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) { 6421 drm_dbg_kms(&i915->drm, 6422 "[PLANE:%d:%s] no old or new framebuffer\n", 6423 plane->base.base.id, plane->base.name); 6424 return -EINVAL; 6425 } 6426 } 6427 6428 return 0; 6429 } 6430 6431 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc) 6432 { 6433 struct drm_i915_private *i915 = to_i915(state->base.dev); 6434 const struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6435 const struct intel_plane_state *new_plane_state, *old_plane_state; 6436 struct intel_plane *plane; 6437 int i; 6438 6439 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 6440 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6441 6442 if (!new_crtc_state->uapi.async_flip) 6443 return 0; 6444 6445 if (!new_crtc_state->hw.active) { 6446 drm_dbg_kms(&i915->drm, 6447 "[CRTC:%d:%s] not active\n", 6448 crtc->base.base.id, crtc->base.name); 6449 return -EINVAL; 6450 } 6451 6452 if (intel_crtc_needs_modeset(new_crtc_state)) { 6453 drm_dbg_kms(&i915->drm, 6454 "[CRTC:%d:%s] modeset required\n", 6455 crtc->base.base.id, crtc->base.name); 6456 return -EINVAL; 6457 } 6458 6459 if (old_crtc_state->active_planes != new_crtc_state->active_planes) { 6460 drm_dbg_kms(&i915->drm, 6461 "[CRTC:%d:%s] Active planes cannot be in async flip\n", 6462 crtc->base.base.id, crtc->base.name); 6463 return -EINVAL; 6464 } 6465 6466 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 6467 new_plane_state, i) { 6468 if (plane->pipe != crtc->pipe) 6469 continue; 6470 6471 /* 6472 * Only async flip capable planes should be in the state 6473 * if we're really about to ask the hardware to perform 6474 * an async flip. We should never get this far otherwise. 6475 */ 6476 if (drm_WARN_ON(&i915->drm, 6477 new_crtc_state->do_async_flip && !plane->async_flip)) 6478 return -EINVAL; 6479 6480 /* 6481 * Only check async flip capable planes other planes 6482 * may be involved in the initial commit due to 6483 * the wm0/ddb optimization. 6484 * 6485 * TODO maybe should track which planes actually 6486 * were requested to do the async flip... 6487 */ 6488 if (!plane->async_flip) 6489 continue; 6490 6491 /* 6492 * FIXME: This check is kept generic for all platforms. 6493 * Need to verify this for all gen9 platforms to enable 6494 * this selectively if required. 6495 */ 6496 switch (new_plane_state->hw.fb->modifier) { 6497 case I915_FORMAT_MOD_X_TILED: 6498 case I915_FORMAT_MOD_Y_TILED: 6499 case I915_FORMAT_MOD_Yf_TILED: 6500 case I915_FORMAT_MOD_4_TILED: 6501 break; 6502 default: 6503 drm_dbg_kms(&i915->drm, 6504 "[PLANE:%d:%s] Modifier does not support async flips\n", 6505 plane->base.base.id, plane->base.name); 6506 return -EINVAL; 6507 } 6508 6509 if (new_plane_state->hw.fb->format->num_planes > 1) { 6510 drm_dbg_kms(&i915->drm, 6511 "[PLANE:%d:%s] Planar formats do not support async flips\n", 6512 plane->base.base.id, plane->base.name); 6513 return -EINVAL; 6514 } 6515 6516 if (old_plane_state->view.color_plane[0].mapping_stride != 6517 new_plane_state->view.color_plane[0].mapping_stride) { 6518 drm_dbg_kms(&i915->drm, 6519 "[PLANE:%d:%s] Stride cannot be changed in async flip\n", 6520 plane->base.base.id, plane->base.name); 6521 return -EINVAL; 6522 } 6523 6524 if (old_plane_state->hw.fb->modifier != 6525 new_plane_state->hw.fb->modifier) { 6526 drm_dbg_kms(&i915->drm, 6527 "[PLANE:%d:%s] Modifier cannot be changed in async flip\n", 6528 plane->base.base.id, plane->base.name); 6529 return -EINVAL; 6530 } 6531 6532 if (old_plane_state->hw.fb->format != 6533 new_plane_state->hw.fb->format) { 6534 drm_dbg_kms(&i915->drm, 6535 "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n", 6536 plane->base.base.id, plane->base.name); 6537 return -EINVAL; 6538 } 6539 6540 if (old_plane_state->hw.rotation != 6541 new_plane_state->hw.rotation) { 6542 drm_dbg_kms(&i915->drm, 6543 "[PLANE:%d:%s] Rotation cannot be changed in async flip\n", 6544 plane->base.base.id, plane->base.name); 6545 return -EINVAL; 6546 } 6547 6548 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) || 6549 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) { 6550 drm_dbg_kms(&i915->drm, 6551 "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n", 6552 plane->base.base.id, plane->base.name); 6553 return -EINVAL; 6554 } 6555 6556 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) { 6557 drm_dbg_kms(&i915->drm, 6558 "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n", 6559 plane->base.base.id, plane->base.name); 6560 return -EINVAL; 6561 } 6562 6563 if (old_plane_state->hw.pixel_blend_mode != 6564 new_plane_state->hw.pixel_blend_mode) { 6565 drm_dbg_kms(&i915->drm, 6566 "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n", 6567 plane->base.base.id, plane->base.name); 6568 return -EINVAL; 6569 } 6570 6571 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) { 6572 drm_dbg_kms(&i915->drm, 6573 "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n", 6574 plane->base.base.id, plane->base.name); 6575 return -EINVAL; 6576 } 6577 6578 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) { 6579 drm_dbg_kms(&i915->drm, 6580 "[PLANE:%d:%s] Color range cannot be changed in async flip\n", 6581 plane->base.base.id, plane->base.name); 6582 return -EINVAL; 6583 } 6584 6585 /* plane decryption is allow to change only in synchronous flips */ 6586 if (old_plane_state->decrypt != new_plane_state->decrypt) { 6587 drm_dbg_kms(&i915->drm, 6588 "[PLANE:%d:%s] Decryption cannot be changed in async flip\n", 6589 plane->base.base.id, plane->base.name); 6590 return -EINVAL; 6591 } 6592 } 6593 6594 return 0; 6595 } 6596 6597 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state) 6598 { 6599 struct drm_i915_private *i915 = to_i915(state->base.dev); 6600 struct intel_crtc_state *crtc_state; 6601 struct intel_crtc *crtc; 6602 u8 affected_pipes = 0; 6603 u8 modeset_pipes = 0; 6604 int i; 6605 6606 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6607 affected_pipes |= crtc_state->bigjoiner_pipes; 6608 if (intel_crtc_needs_modeset(crtc_state)) 6609 modeset_pipes |= crtc_state->bigjoiner_pipes; 6610 } 6611 6612 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) { 6613 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6614 if (IS_ERR(crtc_state)) 6615 return PTR_ERR(crtc_state); 6616 } 6617 6618 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) { 6619 int ret; 6620 6621 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6622 6623 crtc_state->uapi.mode_changed = true; 6624 6625 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); 6626 if (ret) 6627 return ret; 6628 6629 ret = intel_atomic_add_affected_planes(state, crtc); 6630 if (ret) 6631 return ret; 6632 } 6633 6634 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6635 /* Kill old bigjoiner link, we may re-establish afterwards */ 6636 if (intel_crtc_needs_modeset(crtc_state) && 6637 intel_crtc_is_bigjoiner_master(crtc_state)) 6638 kill_bigjoiner_slave(state, crtc); 6639 } 6640 6641 return 0; 6642 } 6643 6644 /** 6645 * intel_atomic_check - validate state object 6646 * @dev: drm device 6647 * @_state: state to validate 6648 */ 6649 int intel_atomic_check(struct drm_device *dev, 6650 struct drm_atomic_state *_state) 6651 { 6652 struct drm_i915_private *dev_priv = to_i915(dev); 6653 struct intel_atomic_state *state = to_intel_atomic_state(_state); 6654 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6655 struct intel_crtc *crtc; 6656 int ret, i; 6657 bool any_ms = false; 6658 6659 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6660 new_crtc_state, i) { 6661 if (new_crtc_state->inherited != old_crtc_state->inherited) 6662 new_crtc_state->uapi.mode_changed = true; 6663 6664 if (new_crtc_state->uapi.scaling_filter != 6665 old_crtc_state->uapi.scaling_filter) 6666 new_crtc_state->uapi.mode_changed = true; 6667 } 6668 6669 intel_vrr_check_modeset(state); 6670 6671 ret = drm_atomic_helper_check_modeset(dev, &state->base); 6672 if (ret) 6673 goto fail; 6674 6675 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6676 ret = intel_async_flip_check_uapi(state, crtc); 6677 if (ret) 6678 return ret; 6679 } 6680 6681 ret = intel_bigjoiner_add_affected_crtcs(state); 6682 if (ret) 6683 goto fail; 6684 6685 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6686 new_crtc_state, i) { 6687 if (!intel_crtc_needs_modeset(new_crtc_state)) { 6688 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 6689 copy_bigjoiner_crtc_state_nomodeset(state, crtc); 6690 else 6691 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 6692 continue; 6693 } 6694 6695 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) { 6696 drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable); 6697 continue; 6698 } 6699 6700 ret = intel_crtc_prepare_cleared_state(state, crtc); 6701 if (ret) 6702 goto fail; 6703 6704 if (!new_crtc_state->hw.enable) 6705 continue; 6706 6707 ret = intel_modeset_pipe_config(state, crtc); 6708 if (ret) 6709 goto fail; 6710 6711 ret = intel_atomic_check_bigjoiner(state, crtc); 6712 if (ret) 6713 goto fail; 6714 } 6715 6716 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6717 new_crtc_state, i) { 6718 if (!intel_crtc_needs_modeset(new_crtc_state)) 6719 continue; 6720 6721 if (new_crtc_state->hw.enable) { 6722 ret = intel_modeset_pipe_config_late(state, crtc); 6723 if (ret) 6724 goto fail; 6725 } 6726 6727 intel_crtc_check_fastset(old_crtc_state, new_crtc_state); 6728 } 6729 6730 /** 6731 * Check if fastset is allowed by external dependencies like other 6732 * pipes and transcoders. 6733 * 6734 * Right now it only forces a fullmodeset when the MST master 6735 * transcoder did not changed but the pipe of the master transcoder 6736 * needs a fullmodeset so all slaves also needs to do a fullmodeset or 6737 * in case of port synced crtcs, if one of the synced crtcs 6738 * needs a full modeset, all other synced crtcs should be 6739 * forced a full modeset. 6740 */ 6741 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6742 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state)) 6743 continue; 6744 6745 if (intel_dp_mst_is_slave_trans(new_crtc_state)) { 6746 enum transcoder master = new_crtc_state->mst_master_transcoder; 6747 6748 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) { 6749 new_crtc_state->uapi.mode_changed = true; 6750 new_crtc_state->update_pipe = false; 6751 } 6752 } 6753 6754 if (is_trans_port_sync_mode(new_crtc_state)) { 6755 u8 trans = new_crtc_state->sync_mode_slaves_mask; 6756 6757 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER) 6758 trans |= BIT(new_crtc_state->master_transcoder); 6759 6760 if (intel_cpu_transcoders_need_modeset(state, trans)) { 6761 new_crtc_state->uapi.mode_changed = true; 6762 new_crtc_state->update_pipe = false; 6763 } 6764 } 6765 6766 if (new_crtc_state->bigjoiner_pipes) { 6767 if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) { 6768 new_crtc_state->uapi.mode_changed = true; 6769 new_crtc_state->update_pipe = false; 6770 } 6771 } 6772 } 6773 6774 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6775 new_crtc_state, i) { 6776 if (!intel_crtc_needs_modeset(new_crtc_state)) 6777 continue; 6778 6779 any_ms = true; 6780 6781 intel_release_shared_dplls(state, crtc); 6782 } 6783 6784 if (any_ms && !check_digital_port_conflicts(state)) { 6785 drm_dbg_kms(&dev_priv->drm, 6786 "rejecting conflicting digital port configuration\n"); 6787 ret = -EINVAL; 6788 goto fail; 6789 } 6790 6791 ret = drm_dp_mst_atomic_check(&state->base); 6792 if (ret) 6793 goto fail; 6794 6795 ret = intel_atomic_check_planes(state); 6796 if (ret) 6797 goto fail; 6798 6799 ret = intel_compute_global_watermarks(state); 6800 if (ret) 6801 goto fail; 6802 6803 ret = intel_bw_atomic_check(state); 6804 if (ret) 6805 goto fail; 6806 6807 ret = intel_cdclk_atomic_check(state, &any_ms); 6808 if (ret) 6809 goto fail; 6810 6811 if (intel_any_crtc_needs_modeset(state)) 6812 any_ms = true; 6813 6814 if (any_ms) { 6815 ret = intel_modeset_checks(state); 6816 if (ret) 6817 goto fail; 6818 6819 ret = intel_modeset_calc_cdclk(state); 6820 if (ret) 6821 return ret; 6822 } 6823 6824 ret = intel_atomic_check_crtcs(state); 6825 if (ret) 6826 goto fail; 6827 6828 ret = intel_fbc_atomic_check(state); 6829 if (ret) 6830 goto fail; 6831 6832 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6833 new_crtc_state, i) { 6834 intel_color_assert_luts(new_crtc_state); 6835 6836 ret = intel_async_flip_check_hw(state, crtc); 6837 if (ret) 6838 goto fail; 6839 6840 /* Either full modeset or fastset (or neither), never both */ 6841 drm_WARN_ON(&dev_priv->drm, 6842 intel_crtc_needs_modeset(new_crtc_state) && 6843 intel_crtc_needs_fastset(new_crtc_state)); 6844 6845 if (!intel_crtc_needs_modeset(new_crtc_state) && 6846 !intel_crtc_needs_fastset(new_crtc_state)) 6847 continue; 6848 6849 intel_crtc_state_dump(new_crtc_state, state, 6850 intel_crtc_needs_modeset(new_crtc_state) ? 6851 "modeset" : "fastset"); 6852 } 6853 6854 return 0; 6855 6856 fail: 6857 if (ret == -EDEADLK) 6858 return ret; 6859 6860 /* 6861 * FIXME would probably be nice to know which crtc specifically 6862 * caused the failure, in cases where we can pinpoint it. 6863 */ 6864 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6865 new_crtc_state, i) 6866 intel_crtc_state_dump(new_crtc_state, state, "failed"); 6867 6868 return ret; 6869 } 6870 6871 static int intel_atomic_prepare_commit(struct intel_atomic_state *state) 6872 { 6873 struct intel_crtc_state *crtc_state; 6874 struct intel_crtc *crtc; 6875 int i, ret; 6876 6877 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base); 6878 if (ret < 0) 6879 return ret; 6880 6881 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6882 if (intel_crtc_needs_color_update(crtc_state)) 6883 intel_color_prepare_commit(crtc_state); 6884 } 6885 6886 return 0; 6887 } 6888 6889 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 6890 struct intel_crtc_state *crtc_state) 6891 { 6892 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6893 6894 if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes) 6895 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 6896 6897 if (crtc_state->has_pch_encoder) { 6898 enum pipe pch_transcoder = 6899 intel_crtc_pch_transcoder(crtc); 6900 6901 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true); 6902 } 6903 } 6904 6905 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, 6906 const struct intel_crtc_state *new_crtc_state) 6907 { 6908 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 6909 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6910 6911 /* 6912 * Update pipe size and adjust fitter if needed: the reason for this is 6913 * that in compute_mode_changes we check the native mode (not the pfit 6914 * mode) to see if we can flip rather than do a full mode set. In the 6915 * fastboot case, we'll flip, but if we don't update the pipesrc and 6916 * pfit state, we'll end up with a big fb scanned out into the wrong 6917 * sized surface. 6918 */ 6919 intel_set_pipe_src_size(new_crtc_state); 6920 6921 /* on skylake this is done by detaching scalers */ 6922 if (DISPLAY_VER(dev_priv) >= 9) { 6923 if (new_crtc_state->pch_pfit.enabled) 6924 skl_pfit_enable(new_crtc_state); 6925 } else if (HAS_PCH_SPLIT(dev_priv)) { 6926 if (new_crtc_state->pch_pfit.enabled) 6927 ilk_pfit_enable(new_crtc_state); 6928 else if (old_crtc_state->pch_pfit.enabled) 6929 ilk_pfit_disable(old_crtc_state); 6930 } 6931 6932 /* 6933 * The register is supposedly single buffered so perhaps 6934 * not 100% correct to do this here. But SKL+ calculate 6935 * this based on the adjust pixel rate so pfit changes do 6936 * affect it and so it must be updated for fastsets. 6937 * HSW/BDW only really need this here for fastboot, after 6938 * that the value should not change without a full modeset. 6939 */ 6940 if (DISPLAY_VER(dev_priv) >= 9 || 6941 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 6942 hsw_set_linetime_wm(new_crtc_state); 6943 6944 if (new_crtc_state->seamless_m_n) 6945 intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder, 6946 &new_crtc_state->dp_m_n); 6947 } 6948 6949 static void commit_pipe_pre_planes(struct intel_atomic_state *state, 6950 struct intel_crtc *crtc) 6951 { 6952 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6953 const struct intel_crtc_state *old_crtc_state = 6954 intel_atomic_get_old_crtc_state(state, crtc); 6955 const struct intel_crtc_state *new_crtc_state = 6956 intel_atomic_get_new_crtc_state(state, crtc); 6957 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 6958 6959 /* 6960 * During modesets pipe configuration was programmed as the 6961 * CRTC was enabled. 6962 */ 6963 if (!modeset) { 6964 if (intel_crtc_needs_color_update(new_crtc_state)) 6965 intel_color_commit_arm(new_crtc_state); 6966 6967 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 6968 bdw_set_pipemisc(new_crtc_state); 6969 6970 if (intel_crtc_needs_fastset(new_crtc_state)) 6971 intel_pipe_fastset(old_crtc_state, new_crtc_state); 6972 } 6973 6974 intel_psr2_program_trans_man_trk_ctl(new_crtc_state); 6975 6976 intel_atomic_update_watermarks(state, crtc); 6977 } 6978 6979 static void commit_pipe_post_planes(struct intel_atomic_state *state, 6980 struct intel_crtc *crtc) 6981 { 6982 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6983 const struct intel_crtc_state *new_crtc_state = 6984 intel_atomic_get_new_crtc_state(state, crtc); 6985 6986 /* 6987 * Disable the scaler(s) after the plane(s) so that we don't 6988 * get a catastrophic underrun even if the two operations 6989 * end up happening in two different frames. 6990 */ 6991 if (DISPLAY_VER(dev_priv) >= 9 && 6992 !intel_crtc_needs_modeset(new_crtc_state)) 6993 skl_detach_scalers(new_crtc_state); 6994 } 6995 6996 static void intel_enable_crtc(struct intel_atomic_state *state, 6997 struct intel_crtc *crtc) 6998 { 6999 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7000 const struct intel_crtc_state *new_crtc_state = 7001 intel_atomic_get_new_crtc_state(state, crtc); 7002 7003 if (!intel_crtc_needs_modeset(new_crtc_state)) 7004 return; 7005 7006 intel_crtc_update_active_timings(new_crtc_state); 7007 7008 dev_priv->display.funcs.display->crtc_enable(state, crtc); 7009 7010 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 7011 return; 7012 7013 /* vblanks work again, re-enable pipe CRC. */ 7014 intel_crtc_enable_pipe_crc(crtc); 7015 } 7016 7017 static void intel_update_crtc(struct intel_atomic_state *state, 7018 struct intel_crtc *crtc) 7019 { 7020 struct drm_i915_private *i915 = to_i915(state->base.dev); 7021 const struct intel_crtc_state *old_crtc_state = 7022 intel_atomic_get_old_crtc_state(state, crtc); 7023 struct intel_crtc_state *new_crtc_state = 7024 intel_atomic_get_new_crtc_state(state, crtc); 7025 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 7026 7027 if (!modeset) { 7028 if (new_crtc_state->preload_luts && 7029 intel_crtc_needs_color_update(new_crtc_state)) 7030 intel_color_load_luts(new_crtc_state); 7031 7032 intel_pre_plane_update(state, crtc); 7033 7034 if (intel_crtc_needs_fastset(new_crtc_state)) 7035 intel_encoders_update_pipe(state, crtc); 7036 7037 if (DISPLAY_VER(i915) >= 11 && 7038 intel_crtc_needs_fastset(new_crtc_state)) 7039 icl_set_pipe_chicken(new_crtc_state); 7040 } 7041 7042 intel_fbc_update(state, crtc); 7043 7044 if (!modeset && 7045 intel_crtc_needs_color_update(new_crtc_state)) 7046 intel_color_commit_noarm(new_crtc_state); 7047 7048 intel_crtc_planes_update_noarm(state, crtc); 7049 7050 /* Perform vblank evasion around commit operation */ 7051 intel_pipe_update_start(new_crtc_state); 7052 7053 commit_pipe_pre_planes(state, crtc); 7054 7055 intel_crtc_planes_update_arm(state, crtc); 7056 7057 commit_pipe_post_planes(state, crtc); 7058 7059 intel_pipe_update_end(new_crtc_state); 7060 7061 /* 7062 * We usually enable FIFO underrun interrupts as part of the 7063 * CRTC enable sequence during modesets. But when we inherit a 7064 * valid pipe configuration from the BIOS we need to take care 7065 * of enabling them on the CRTC's first fastset. 7066 */ 7067 if (intel_crtc_needs_fastset(new_crtc_state) && !modeset && 7068 old_crtc_state->inherited) 7069 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state); 7070 } 7071 7072 static void intel_old_crtc_state_disables(struct intel_atomic_state *state, 7073 struct intel_crtc_state *old_crtc_state, 7074 struct intel_crtc_state *new_crtc_state, 7075 struct intel_crtc *crtc) 7076 { 7077 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7078 7079 /* 7080 * We need to disable pipe CRC before disabling the pipe, 7081 * or we race against vblank off. 7082 */ 7083 intel_crtc_disable_pipe_crc(crtc); 7084 7085 dev_priv->display.funcs.display->crtc_disable(state, crtc); 7086 crtc->active = false; 7087 intel_fbc_disable(crtc); 7088 intel_disable_shared_dpll(old_crtc_state); 7089 7090 if (!new_crtc_state->hw.active) 7091 intel_initial_watermarks(state, crtc); 7092 } 7093 7094 static void intel_commit_modeset_disables(struct intel_atomic_state *state) 7095 { 7096 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 7097 struct intel_crtc *crtc; 7098 u32 handled = 0; 7099 int i; 7100 7101 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7102 new_crtc_state, i) { 7103 if (!intel_crtc_needs_modeset(new_crtc_state)) 7104 continue; 7105 7106 if (!old_crtc_state->hw.active) 7107 continue; 7108 7109 intel_pre_plane_update(state, crtc); 7110 intel_crtc_disable_planes(state, crtc); 7111 } 7112 7113 /* Only disable port sync and MST slaves */ 7114 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7115 new_crtc_state, i) { 7116 if (!intel_crtc_needs_modeset(new_crtc_state)) 7117 continue; 7118 7119 if (!old_crtc_state->hw.active) 7120 continue; 7121 7122 /* In case of Transcoder port Sync master slave CRTCs can be 7123 * assigned in any order and we need to make sure that 7124 * slave CRTCs are disabled first and then master CRTC since 7125 * Slave vblanks are masked till Master Vblanks. 7126 */ 7127 if (!is_trans_port_sync_slave(old_crtc_state) && 7128 !intel_dp_mst_is_slave_trans(old_crtc_state) && 7129 !intel_crtc_is_bigjoiner_slave(old_crtc_state)) 7130 continue; 7131 7132 intel_old_crtc_state_disables(state, old_crtc_state, 7133 new_crtc_state, crtc); 7134 handled |= BIT(crtc->pipe); 7135 } 7136 7137 /* Disable everything else left on */ 7138 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7139 new_crtc_state, i) { 7140 if (!intel_crtc_needs_modeset(new_crtc_state) || 7141 (handled & BIT(crtc->pipe))) 7142 continue; 7143 7144 if (!old_crtc_state->hw.active) 7145 continue; 7146 7147 intel_old_crtc_state_disables(state, old_crtc_state, 7148 new_crtc_state, crtc); 7149 } 7150 } 7151 7152 static void intel_commit_modeset_enables(struct intel_atomic_state *state) 7153 { 7154 struct intel_crtc_state *new_crtc_state; 7155 struct intel_crtc *crtc; 7156 int i; 7157 7158 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7159 if (!new_crtc_state->hw.active) 7160 continue; 7161 7162 intel_enable_crtc(state, crtc); 7163 intel_update_crtc(state, crtc); 7164 } 7165 } 7166 7167 static void skl_commit_modeset_enables(struct intel_atomic_state *state) 7168 { 7169 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7170 struct intel_crtc *crtc; 7171 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7172 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; 7173 u8 update_pipes = 0, modeset_pipes = 0; 7174 int i; 7175 7176 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7177 enum pipe pipe = crtc->pipe; 7178 7179 if (!new_crtc_state->hw.active) 7180 continue; 7181 7182 /* ignore allocations for crtc's that have been turned off. */ 7183 if (!intel_crtc_needs_modeset(new_crtc_state)) { 7184 entries[pipe] = old_crtc_state->wm.skl.ddb; 7185 update_pipes |= BIT(pipe); 7186 } else { 7187 modeset_pipes |= BIT(pipe); 7188 } 7189 } 7190 7191 /* 7192 * Whenever the number of active pipes changes, we need to make sure we 7193 * update the pipes in the right order so that their ddb allocations 7194 * never overlap with each other between CRTC updates. Otherwise we'll 7195 * cause pipe underruns and other bad stuff. 7196 * 7197 * So first lets enable all pipes that do not need a fullmodeset as 7198 * those don't have any external dependency. 7199 */ 7200 while (update_pipes) { 7201 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7202 new_crtc_state, i) { 7203 enum pipe pipe = crtc->pipe; 7204 7205 if ((update_pipes & BIT(pipe)) == 0) 7206 continue; 7207 7208 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 7209 entries, I915_MAX_PIPES, pipe)) 7210 continue; 7211 7212 entries[pipe] = new_crtc_state->wm.skl.ddb; 7213 update_pipes &= ~BIT(pipe); 7214 7215 intel_update_crtc(state, crtc); 7216 7217 /* 7218 * If this is an already active pipe, it's DDB changed, 7219 * and this isn't the last pipe that needs updating 7220 * then we need to wait for a vblank to pass for the 7221 * new ddb allocation to take effect. 7222 */ 7223 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, 7224 &old_crtc_state->wm.skl.ddb) && 7225 (update_pipes | modeset_pipes)) 7226 intel_crtc_wait_for_next_vblank(crtc); 7227 } 7228 } 7229 7230 update_pipes = modeset_pipes; 7231 7232 /* 7233 * Enable all pipes that needs a modeset and do not depends on other 7234 * pipes 7235 */ 7236 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7237 enum pipe pipe = crtc->pipe; 7238 7239 if ((modeset_pipes & BIT(pipe)) == 0) 7240 continue; 7241 7242 if (intel_dp_mst_is_slave_trans(new_crtc_state) || 7243 is_trans_port_sync_master(new_crtc_state) || 7244 intel_crtc_is_bigjoiner_master(new_crtc_state)) 7245 continue; 7246 7247 modeset_pipes &= ~BIT(pipe); 7248 7249 intel_enable_crtc(state, crtc); 7250 } 7251 7252 /* 7253 * Then we enable all remaining pipes that depend on other 7254 * pipes: MST slaves and port sync masters, big joiner master 7255 */ 7256 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7257 enum pipe pipe = crtc->pipe; 7258 7259 if ((modeset_pipes & BIT(pipe)) == 0) 7260 continue; 7261 7262 modeset_pipes &= ~BIT(pipe); 7263 7264 intel_enable_crtc(state, crtc); 7265 } 7266 7267 /* 7268 * Finally we do the plane updates/etc. for all pipes that got enabled. 7269 */ 7270 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7271 enum pipe pipe = crtc->pipe; 7272 7273 if ((update_pipes & BIT(pipe)) == 0) 7274 continue; 7275 7276 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 7277 entries, I915_MAX_PIPES, pipe)); 7278 7279 entries[pipe] = new_crtc_state->wm.skl.ddb; 7280 update_pipes &= ~BIT(pipe); 7281 7282 intel_update_crtc(state, crtc); 7283 } 7284 7285 drm_WARN_ON(&dev_priv->drm, modeset_pipes); 7286 drm_WARN_ON(&dev_priv->drm, update_pipes); 7287 } 7288 7289 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) 7290 { 7291 struct intel_atomic_state *state, *next; 7292 struct llist_node *freed; 7293 7294 freed = llist_del_all(&dev_priv->display.atomic_helper.free_list); 7295 llist_for_each_entry_safe(state, next, freed, freed) 7296 drm_atomic_state_put(&state->base); 7297 } 7298 7299 static void intel_atomic_helper_free_state_worker(struct work_struct *work) 7300 { 7301 struct drm_i915_private *dev_priv = 7302 container_of(work, typeof(*dev_priv), display.atomic_helper.free_work); 7303 7304 intel_atomic_helper_free_state(dev_priv); 7305 } 7306 7307 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) 7308 { 7309 struct wait_queue_entry wait_fence, wait_reset; 7310 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); 7311 7312 init_wait_entry(&wait_fence, 0); 7313 init_wait_entry(&wait_reset, 0); 7314 for (;;) { 7315 prepare_to_wait(&intel_state->commit_ready.wait, 7316 &wait_fence, TASK_UNINTERRUPTIBLE); 7317 prepare_to_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 7318 I915_RESET_MODESET), 7319 &wait_reset, TASK_UNINTERRUPTIBLE); 7320 7321 7322 if (i915_sw_fence_done(&intel_state->commit_ready) || 7323 test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags)) 7324 break; 7325 7326 schedule(); 7327 } 7328 finish_wait(&intel_state->commit_ready.wait, &wait_fence); 7329 finish_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 7330 I915_RESET_MODESET), 7331 &wait_reset); 7332 } 7333 7334 static void intel_atomic_cleanup_work(struct work_struct *work) 7335 { 7336 struct intel_atomic_state *state = 7337 container_of(work, struct intel_atomic_state, base.commit_work); 7338 struct drm_i915_private *i915 = to_i915(state->base.dev); 7339 struct intel_crtc_state *old_crtc_state; 7340 struct intel_crtc *crtc; 7341 int i; 7342 7343 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) 7344 intel_color_cleanup_commit(old_crtc_state); 7345 7346 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base); 7347 drm_atomic_helper_commit_cleanup_done(&state->base); 7348 drm_atomic_state_put(&state->base); 7349 7350 intel_atomic_helper_free_state(i915); 7351 } 7352 7353 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state) 7354 { 7355 struct drm_i915_private *i915 = to_i915(state->base.dev); 7356 struct intel_plane *plane; 7357 struct intel_plane_state *plane_state; 7358 int i; 7359 7360 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 7361 struct drm_framebuffer *fb = plane_state->hw.fb; 7362 int cc_plane; 7363 int ret; 7364 7365 if (!fb) 7366 continue; 7367 7368 cc_plane = intel_fb_rc_ccs_cc_plane(fb); 7369 if (cc_plane < 0) 7370 continue; 7371 7372 /* 7373 * The layout of the fast clear color value expected by HW 7374 * (the DRM ABI requiring this value to be located in fb at 7375 * offset 0 of cc plane, plane #2 previous generations or 7376 * plane #1 for flat ccs): 7377 * - 4 x 4 bytes per-channel value 7378 * (in surface type specific float/int format provided by the fb user) 7379 * - 8 bytes native color value used by the display 7380 * (converted/written by GPU during a fast clear operation using the 7381 * above per-channel values) 7382 * 7383 * The commit's FB prepare hook already ensured that FB obj is pinned and the 7384 * caller made sure that the object is synced wrt. the related color clear value 7385 * GPU write on it. 7386 */ 7387 ret = i915_gem_object_read_from_page(intel_fb_obj(fb), 7388 fb->offsets[cc_plane] + 16, 7389 &plane_state->ccval, 7390 sizeof(plane_state->ccval)); 7391 /* The above could only fail if the FB obj has an unexpected backing store type. */ 7392 drm_WARN_ON(&i915->drm, ret); 7393 } 7394 } 7395 7396 static void intel_atomic_commit_tail(struct intel_atomic_state *state) 7397 { 7398 struct drm_device *dev = state->base.dev; 7399 struct drm_i915_private *dev_priv = to_i915(dev); 7400 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 7401 struct intel_crtc *crtc; 7402 struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {}; 7403 intel_wakeref_t wakeref = 0; 7404 int i; 7405 7406 intel_atomic_commit_fence_wait(state); 7407 7408 drm_atomic_helper_wait_for_dependencies(&state->base); 7409 drm_dp_mst_atomic_wait_for_dependencies(&state->base); 7410 7411 if (state->modeset) 7412 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); 7413 7414 intel_atomic_prepare_plane_clear_colors(state); 7415 7416 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7417 new_crtc_state, i) { 7418 if (intel_crtc_needs_modeset(new_crtc_state) || 7419 intel_crtc_needs_fastset(new_crtc_state)) 7420 intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]); 7421 } 7422 7423 intel_commit_modeset_disables(state); 7424 7425 /* FIXME: Eventually get rid of our crtc->config pointer */ 7426 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7427 crtc->config = new_crtc_state; 7428 7429 if (state->modeset) { 7430 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base); 7431 7432 intel_set_cdclk_pre_plane_update(state); 7433 7434 intel_modeset_verify_disabled(dev_priv, state); 7435 } 7436 7437 intel_sagv_pre_plane_update(state); 7438 7439 /* Complete the events for pipes that have now been disabled */ 7440 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7441 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 7442 7443 /* Complete events for now disable pipes here. */ 7444 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) { 7445 spin_lock_irq(&dev->event_lock); 7446 drm_crtc_send_vblank_event(&crtc->base, 7447 new_crtc_state->uapi.event); 7448 spin_unlock_irq(&dev->event_lock); 7449 7450 new_crtc_state->uapi.event = NULL; 7451 } 7452 } 7453 7454 intel_encoders_update_prepare(state); 7455 7456 intel_dbuf_pre_plane_update(state); 7457 intel_mbus_dbox_update(state); 7458 7459 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7460 if (new_crtc_state->do_async_flip) 7461 intel_crtc_enable_flip_done(state, crtc); 7462 } 7463 7464 /* Now enable the clocks, plane, pipe, and connectors that we set up. */ 7465 dev_priv->display.funcs.display->commit_modeset_enables(state); 7466 7467 intel_encoders_update_complete(state); 7468 7469 if (state->modeset) 7470 intel_set_cdclk_post_plane_update(state); 7471 7472 intel_wait_for_vblank_workers(state); 7473 7474 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here 7475 * already, but still need the state for the delayed optimization. To 7476 * fix this: 7477 * - wrap the optimization/post_plane_update stuff into a per-crtc work. 7478 * - schedule that vblank worker _before_ calling hw_done 7479 * - at the start of commit_tail, cancel it _synchrously 7480 * - switch over to the vblank wait helper in the core after that since 7481 * we don't need out special handling any more. 7482 */ 7483 drm_atomic_helper_wait_for_flip_done(dev, &state->base); 7484 7485 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7486 if (new_crtc_state->do_async_flip) 7487 intel_crtc_disable_flip_done(state, crtc); 7488 } 7489 7490 /* 7491 * Now that the vblank has passed, we can go ahead and program the 7492 * optimal watermarks on platforms that need two-step watermark 7493 * programming. 7494 * 7495 * TODO: Move this (and other cleanup) to an async worker eventually. 7496 */ 7497 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7498 new_crtc_state, i) { 7499 /* 7500 * Gen2 reports pipe underruns whenever all planes are disabled. 7501 * So re-enable underrun reporting after some planes get enabled. 7502 * 7503 * We do this before .optimize_watermarks() so that we have a 7504 * chance of catching underruns with the intermediate watermarks 7505 * vs. the new plane configuration. 7506 */ 7507 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state)) 7508 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 7509 7510 intel_optimize_watermarks(state, crtc); 7511 } 7512 7513 intel_dbuf_post_plane_update(state); 7514 intel_psr_post_plane_update(state); 7515 7516 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7517 intel_post_plane_update(state, crtc); 7518 7519 intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]); 7520 7521 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state); 7522 7523 /* Must be done after gamma readout due to HSW split gamma vs. IPS w/a */ 7524 hsw_ips_post_update(state, crtc); 7525 7526 /* 7527 * Activate DRRS after state readout to avoid 7528 * dp_m_n vs. dp_m2_n2 confusion on BDW+. 7529 */ 7530 intel_drrs_activate(new_crtc_state); 7531 7532 /* 7533 * DSB cleanup is done in cleanup_work aligning with framebuffer 7534 * cleanup. So copy and reset the dsb structure to sync with 7535 * commit_done and later do dsb cleanup in cleanup_work. 7536 * 7537 * FIXME get rid of this funny new->old swapping 7538 */ 7539 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb); 7540 } 7541 7542 /* Underruns don't always raise interrupts, so check manually */ 7543 intel_check_cpu_fifo_underruns(dev_priv); 7544 intel_check_pch_fifo_underruns(dev_priv); 7545 7546 if (state->modeset) 7547 intel_verify_planes(state); 7548 7549 intel_sagv_post_plane_update(state); 7550 7551 drm_atomic_helper_commit_hw_done(&state->base); 7552 7553 if (state->modeset) { 7554 /* As one of the primary mmio accessors, KMS has a high 7555 * likelihood of triggering bugs in unclaimed access. After we 7556 * finish modesetting, see if an error has been flagged, and if 7557 * so enable debugging for the next modeset - and hope we catch 7558 * the culprit. 7559 */ 7560 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); 7561 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref); 7562 } 7563 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7564 7565 /* 7566 * Defer the cleanup of the old state to a separate worker to not 7567 * impede the current task (userspace for blocking modesets) that 7568 * are executed inline. For out-of-line asynchronous modesets/flips, 7569 * deferring to a new worker seems overkill, but we would place a 7570 * schedule point (cond_resched()) here anyway to keep latencies 7571 * down. 7572 */ 7573 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work); 7574 queue_work(system_highpri_wq, &state->base.commit_work); 7575 } 7576 7577 static void intel_atomic_commit_work(struct work_struct *work) 7578 { 7579 struct intel_atomic_state *state = 7580 container_of(work, struct intel_atomic_state, base.commit_work); 7581 7582 intel_atomic_commit_tail(state); 7583 } 7584 7585 static int 7586 intel_atomic_commit_ready(struct i915_sw_fence *fence, 7587 enum i915_sw_fence_notify notify) 7588 { 7589 struct intel_atomic_state *state = 7590 container_of(fence, struct intel_atomic_state, commit_ready); 7591 7592 switch (notify) { 7593 case FENCE_COMPLETE: 7594 /* we do blocking waits in the worker, nothing to do here */ 7595 break; 7596 case FENCE_FREE: 7597 { 7598 struct intel_atomic_helper *helper = 7599 &to_i915(state->base.dev)->display.atomic_helper; 7600 7601 if (llist_add(&state->freed, &helper->free_list)) 7602 schedule_work(&helper->free_work); 7603 break; 7604 } 7605 } 7606 7607 return NOTIFY_DONE; 7608 } 7609 7610 static void intel_atomic_track_fbs(struct intel_atomic_state *state) 7611 { 7612 struct intel_plane_state *old_plane_state, *new_plane_state; 7613 struct intel_plane *plane; 7614 int i; 7615 7616 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 7617 new_plane_state, i) 7618 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), 7619 to_intel_frontbuffer(new_plane_state->hw.fb), 7620 plane->frontbuffer_bit); 7621 } 7622 7623 static int intel_atomic_commit(struct drm_device *dev, 7624 struct drm_atomic_state *_state, 7625 bool nonblock) 7626 { 7627 struct intel_atomic_state *state = to_intel_atomic_state(_state); 7628 struct drm_i915_private *dev_priv = to_i915(dev); 7629 int ret = 0; 7630 7631 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 7632 7633 drm_atomic_state_get(&state->base); 7634 i915_sw_fence_init(&state->commit_ready, 7635 intel_atomic_commit_ready); 7636 7637 /* 7638 * The intel_legacy_cursor_update() fast path takes care 7639 * of avoiding the vblank waits for simple cursor 7640 * movement and flips. For cursor on/off and size changes, 7641 * we want to perform the vblank waits so that watermark 7642 * updates happen during the correct frames. Gen9+ have 7643 * double buffered watermarks and so shouldn't need this. 7644 * 7645 * Unset state->legacy_cursor_update before the call to 7646 * drm_atomic_helper_setup_commit() because otherwise 7647 * drm_atomic_helper_wait_for_flip_done() is a noop and 7648 * we get FIFO underruns because we didn't wait 7649 * for vblank. 7650 * 7651 * FIXME doing watermarks and fb cleanup from a vblank worker 7652 * (assuming we had any) would solve these problems. 7653 */ 7654 if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) { 7655 struct intel_crtc_state *new_crtc_state; 7656 struct intel_crtc *crtc; 7657 int i; 7658 7659 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7660 if (new_crtc_state->wm.need_postvbl_update || 7661 new_crtc_state->update_wm_post) 7662 state->base.legacy_cursor_update = false; 7663 } 7664 7665 ret = intel_atomic_prepare_commit(state); 7666 if (ret) { 7667 drm_dbg_atomic(&dev_priv->drm, 7668 "Preparing state failed with %i\n", ret); 7669 i915_sw_fence_commit(&state->commit_ready); 7670 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7671 return ret; 7672 } 7673 7674 ret = drm_atomic_helper_setup_commit(&state->base, nonblock); 7675 if (!ret) 7676 ret = drm_atomic_helper_swap_state(&state->base, true); 7677 if (!ret) 7678 intel_atomic_swap_global_state(state); 7679 7680 if (ret) { 7681 struct intel_crtc_state *new_crtc_state; 7682 struct intel_crtc *crtc; 7683 int i; 7684 7685 i915_sw_fence_commit(&state->commit_ready); 7686 7687 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7688 intel_color_cleanup_commit(new_crtc_state); 7689 7690 drm_atomic_helper_cleanup_planes(dev, &state->base); 7691 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7692 return ret; 7693 } 7694 intel_shared_dpll_swap_state(state); 7695 intel_atomic_track_fbs(state); 7696 7697 drm_atomic_state_get(&state->base); 7698 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work); 7699 7700 i915_sw_fence_commit(&state->commit_ready); 7701 if (nonblock && state->modeset) { 7702 queue_work(dev_priv->display.wq.modeset, &state->base.commit_work); 7703 } else if (nonblock) { 7704 queue_work(dev_priv->display.wq.flip, &state->base.commit_work); 7705 } else { 7706 if (state->modeset) 7707 flush_workqueue(dev_priv->display.wq.modeset); 7708 intel_atomic_commit_tail(state); 7709 } 7710 7711 return 0; 7712 } 7713 7714 /** 7715 * intel_plane_destroy - destroy a plane 7716 * @plane: plane to destroy 7717 * 7718 * Common destruction function for all types of planes (primary, cursor, 7719 * sprite). 7720 */ 7721 void intel_plane_destroy(struct drm_plane *plane) 7722 { 7723 drm_plane_cleanup(plane); 7724 kfree(to_intel_plane(plane)); 7725 } 7726 7727 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv) 7728 { 7729 struct intel_plane *plane; 7730 7731 for_each_intel_plane(&dev_priv->drm, plane) { 7732 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, 7733 plane->pipe); 7734 7735 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base); 7736 } 7737 } 7738 7739 7740 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 7741 struct drm_file *file) 7742 { 7743 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; 7744 struct drm_crtc *drmmode_crtc; 7745 struct intel_crtc *crtc; 7746 7747 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id); 7748 if (!drmmode_crtc) 7749 return -ENOENT; 7750 7751 crtc = to_intel_crtc(drmmode_crtc); 7752 pipe_from_crtc_id->pipe = crtc->pipe; 7753 7754 return 0; 7755 } 7756 7757 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder) 7758 { 7759 struct drm_device *dev = encoder->base.dev; 7760 struct intel_encoder *source_encoder; 7761 u32 possible_clones = 0; 7762 7763 for_each_intel_encoder(dev, source_encoder) { 7764 if (encoders_cloneable(encoder, source_encoder)) 7765 possible_clones |= drm_encoder_mask(&source_encoder->base); 7766 } 7767 7768 return possible_clones; 7769 } 7770 7771 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder) 7772 { 7773 struct drm_device *dev = encoder->base.dev; 7774 struct intel_crtc *crtc; 7775 u32 possible_crtcs = 0; 7776 7777 for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask) 7778 possible_crtcs |= drm_crtc_mask(&crtc->base); 7779 7780 return possible_crtcs; 7781 } 7782 7783 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv) 7784 { 7785 if (!IS_MOBILE(dev_priv)) 7786 return false; 7787 7788 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0) 7789 return false; 7790 7791 if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE)) 7792 return false; 7793 7794 return true; 7795 } 7796 7797 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv) 7798 { 7799 if (DISPLAY_VER(dev_priv) >= 9) 7800 return false; 7801 7802 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) 7803 return false; 7804 7805 if (HAS_PCH_LPT_H(dev_priv) && 7806 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) 7807 return false; 7808 7809 /* DDI E can't be used if DDI A requires 4 lanes */ 7810 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 7811 return false; 7812 7813 if (!dev_priv->display.vbt.int_crt_support) 7814 return false; 7815 7816 return true; 7817 } 7818 7819 static void intel_setup_outputs(struct drm_i915_private *dev_priv) 7820 { 7821 struct intel_encoder *encoder; 7822 bool dpd_is_edp = false; 7823 7824 intel_pps_unlock_regs_wa(dev_priv); 7825 7826 if (!HAS_DISPLAY(dev_priv)) 7827 return; 7828 7829 if (IS_DG2(dev_priv)) { 7830 intel_ddi_init(dev_priv, PORT_A); 7831 intel_ddi_init(dev_priv, PORT_B); 7832 intel_ddi_init(dev_priv, PORT_C); 7833 intel_ddi_init(dev_priv, PORT_D_XELPD); 7834 intel_ddi_init(dev_priv, PORT_TC1); 7835 } else if (IS_ALDERLAKE_P(dev_priv)) { 7836 intel_ddi_init(dev_priv, PORT_A); 7837 intel_ddi_init(dev_priv, PORT_B); 7838 intel_ddi_init(dev_priv, PORT_TC1); 7839 intel_ddi_init(dev_priv, PORT_TC2); 7840 intel_ddi_init(dev_priv, PORT_TC3); 7841 intel_ddi_init(dev_priv, PORT_TC4); 7842 icl_dsi_init(dev_priv); 7843 } else if (IS_ALDERLAKE_S(dev_priv)) { 7844 intel_ddi_init(dev_priv, PORT_A); 7845 intel_ddi_init(dev_priv, PORT_TC1); 7846 intel_ddi_init(dev_priv, PORT_TC2); 7847 intel_ddi_init(dev_priv, PORT_TC3); 7848 intel_ddi_init(dev_priv, PORT_TC4); 7849 } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) { 7850 intel_ddi_init(dev_priv, PORT_A); 7851 intel_ddi_init(dev_priv, PORT_B); 7852 intel_ddi_init(dev_priv, PORT_TC1); 7853 intel_ddi_init(dev_priv, PORT_TC2); 7854 } else if (DISPLAY_VER(dev_priv) >= 12) { 7855 intel_ddi_init(dev_priv, PORT_A); 7856 intel_ddi_init(dev_priv, PORT_B); 7857 intel_ddi_init(dev_priv, PORT_TC1); 7858 intel_ddi_init(dev_priv, PORT_TC2); 7859 intel_ddi_init(dev_priv, PORT_TC3); 7860 intel_ddi_init(dev_priv, PORT_TC4); 7861 intel_ddi_init(dev_priv, PORT_TC5); 7862 intel_ddi_init(dev_priv, PORT_TC6); 7863 icl_dsi_init(dev_priv); 7864 } else if (IS_JSL_EHL(dev_priv)) { 7865 intel_ddi_init(dev_priv, PORT_A); 7866 intel_ddi_init(dev_priv, PORT_B); 7867 intel_ddi_init(dev_priv, PORT_C); 7868 intel_ddi_init(dev_priv, PORT_D); 7869 icl_dsi_init(dev_priv); 7870 } else if (DISPLAY_VER(dev_priv) == 11) { 7871 intel_ddi_init(dev_priv, PORT_A); 7872 intel_ddi_init(dev_priv, PORT_B); 7873 intel_ddi_init(dev_priv, PORT_C); 7874 intel_ddi_init(dev_priv, PORT_D); 7875 intel_ddi_init(dev_priv, PORT_E); 7876 intel_ddi_init(dev_priv, PORT_F); 7877 icl_dsi_init(dev_priv); 7878 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 7879 intel_ddi_init(dev_priv, PORT_A); 7880 intel_ddi_init(dev_priv, PORT_B); 7881 intel_ddi_init(dev_priv, PORT_C); 7882 vlv_dsi_init(dev_priv); 7883 } else if (DISPLAY_VER(dev_priv) >= 9) { 7884 intel_ddi_init(dev_priv, PORT_A); 7885 intel_ddi_init(dev_priv, PORT_B); 7886 intel_ddi_init(dev_priv, PORT_C); 7887 intel_ddi_init(dev_priv, PORT_D); 7888 intel_ddi_init(dev_priv, PORT_E); 7889 } else if (HAS_DDI(dev_priv)) { 7890 u32 found; 7891 7892 if (intel_ddi_crt_present(dev_priv)) 7893 intel_crt_init(dev_priv); 7894 7895 /* Haswell uses DDI functions to detect digital outputs. */ 7896 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 7897 if (found) 7898 intel_ddi_init(dev_priv, PORT_A); 7899 7900 found = intel_de_read(dev_priv, SFUSE_STRAP); 7901 if (found & SFUSE_STRAP_DDIB_DETECTED) 7902 intel_ddi_init(dev_priv, PORT_B); 7903 if (found & SFUSE_STRAP_DDIC_DETECTED) 7904 intel_ddi_init(dev_priv, PORT_C); 7905 if (found & SFUSE_STRAP_DDID_DETECTED) 7906 intel_ddi_init(dev_priv, PORT_D); 7907 if (found & SFUSE_STRAP_DDIF_DETECTED) 7908 intel_ddi_init(dev_priv, PORT_F); 7909 } else if (HAS_PCH_SPLIT(dev_priv)) { 7910 int found; 7911 7912 /* 7913 * intel_edp_init_connector() depends on this completing first, 7914 * to prevent the registration of both eDP and LVDS and the 7915 * incorrect sharing of the PPS. 7916 */ 7917 intel_lvds_init(dev_priv); 7918 intel_crt_init(dev_priv); 7919 7920 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D); 7921 7922 if (ilk_has_edp_a(dev_priv)) 7923 g4x_dp_init(dev_priv, DP_A, PORT_A); 7924 7925 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) { 7926 /* PCH SDVOB multiplex with HDMIB */ 7927 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); 7928 if (!found) 7929 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); 7930 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED)) 7931 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B); 7932 } 7933 7934 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED) 7935 g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); 7936 7937 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED) 7938 g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D); 7939 7940 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED) 7941 g4x_dp_init(dev_priv, PCH_DP_C, PORT_C); 7942 7943 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED) 7944 g4x_dp_init(dev_priv, PCH_DP_D, PORT_D); 7945 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 7946 bool has_edp, has_port; 7947 7948 if (IS_VALLEYVIEW(dev_priv) && dev_priv->display.vbt.int_crt_support) 7949 intel_crt_init(dev_priv); 7950 7951 /* 7952 * The DP_DETECTED bit is the latched state of the DDC 7953 * SDA pin at boot. However since eDP doesn't require DDC 7954 * (no way to plug in a DP->HDMI dongle) the DDC pins for 7955 * eDP ports may have been muxed to an alternate function. 7956 * Thus we can't rely on the DP_DETECTED bit alone to detect 7957 * eDP ports. Consult the VBT as well as DP_DETECTED to 7958 * detect eDP ports. 7959 * 7960 * Sadly the straps seem to be missing sometimes even for HDMI 7961 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap 7962 * and VBT for the presence of the port. Additionally we can't 7963 * trust the port type the VBT declares as we've seen at least 7964 * HDMI ports that the VBT claim are DP or eDP. 7965 */ 7966 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B); 7967 has_port = intel_bios_is_port_present(dev_priv, PORT_B); 7968 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port) 7969 has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B); 7970 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) 7971 g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); 7972 7973 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C); 7974 has_port = intel_bios_is_port_present(dev_priv, PORT_C); 7975 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port) 7976 has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C); 7977 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) 7978 g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); 7979 7980 if (IS_CHERRYVIEW(dev_priv)) { 7981 /* 7982 * eDP not supported on port D, 7983 * so no need to worry about it 7984 */ 7985 has_port = intel_bios_is_port_present(dev_priv, PORT_D); 7986 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port) 7987 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D); 7988 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port) 7989 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D); 7990 } 7991 7992 vlv_dsi_init(dev_priv); 7993 } else if (IS_PINEVIEW(dev_priv)) { 7994 intel_lvds_init(dev_priv); 7995 intel_crt_init(dev_priv); 7996 } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) { 7997 bool found = false; 7998 7999 if (IS_MOBILE(dev_priv)) 8000 intel_lvds_init(dev_priv); 8001 8002 intel_crt_init(dev_priv); 8003 8004 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 8005 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n"); 8006 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); 8007 if (!found && IS_G4X(dev_priv)) { 8008 drm_dbg_kms(&dev_priv->drm, 8009 "probing HDMI on SDVOB\n"); 8010 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); 8011 } 8012 8013 if (!found && IS_G4X(dev_priv)) 8014 g4x_dp_init(dev_priv, DP_B, PORT_B); 8015 } 8016 8017 /* Before G4X SDVOC doesn't have its own detect register */ 8018 8019 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 8020 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n"); 8021 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); 8022 } 8023 8024 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) { 8025 8026 if (IS_G4X(dev_priv)) { 8027 drm_dbg_kms(&dev_priv->drm, 8028 "probing HDMI on SDVOC\n"); 8029 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); 8030 } 8031 if (IS_G4X(dev_priv)) 8032 g4x_dp_init(dev_priv, DP_C, PORT_C); 8033 } 8034 8035 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED)) 8036 g4x_dp_init(dev_priv, DP_D, PORT_D); 8037 8038 if (SUPPORTS_TV(dev_priv)) 8039 intel_tv_init(dev_priv); 8040 } else if (DISPLAY_VER(dev_priv) == 2) { 8041 if (IS_I85X(dev_priv)) 8042 intel_lvds_init(dev_priv); 8043 8044 intel_crt_init(dev_priv); 8045 intel_dvo_init(dev_priv); 8046 } 8047 8048 for_each_intel_encoder(&dev_priv->drm, encoder) { 8049 encoder->base.possible_crtcs = 8050 intel_encoder_possible_crtcs(encoder); 8051 encoder->base.possible_clones = 8052 intel_encoder_possible_clones(encoder); 8053 } 8054 8055 intel_init_pch_refclk(dev_priv); 8056 8057 drm_helper_move_panel_connectors_to_head(&dev_priv->drm); 8058 } 8059 8060 static int max_dotclock(struct drm_i915_private *i915) 8061 { 8062 int max_dotclock = i915->max_dotclk_freq; 8063 8064 /* icl+ might use bigjoiner */ 8065 if (DISPLAY_VER(i915) >= 11) 8066 max_dotclock *= 2; 8067 8068 return max_dotclock; 8069 } 8070 8071 static enum drm_mode_status 8072 intel_mode_valid(struct drm_device *dev, 8073 const struct drm_display_mode *mode) 8074 { 8075 struct drm_i915_private *dev_priv = to_i915(dev); 8076 int hdisplay_max, htotal_max; 8077 int vdisplay_max, vtotal_max; 8078 8079 /* 8080 * Can't reject DBLSCAN here because Xorg ddxen can add piles 8081 * of DBLSCAN modes to the output's mode list when they detect 8082 * the scaling mode property on the connector. And they don't 8083 * ask the kernel to validate those modes in any way until 8084 * modeset time at which point the client gets a protocol error. 8085 * So in order to not upset those clients we silently ignore the 8086 * DBLSCAN flag on such connectors. For other connectors we will 8087 * reject modes with the DBLSCAN flag in encoder->compute_config(). 8088 * And we always reject DBLSCAN modes in connector->mode_valid() 8089 * as we never want such modes on the connector's mode list. 8090 */ 8091 8092 if (mode->vscan > 1) 8093 return MODE_NO_VSCAN; 8094 8095 if (mode->flags & DRM_MODE_FLAG_HSKEW) 8096 return MODE_H_ILLEGAL; 8097 8098 if (mode->flags & (DRM_MODE_FLAG_CSYNC | 8099 DRM_MODE_FLAG_NCSYNC | 8100 DRM_MODE_FLAG_PCSYNC)) 8101 return MODE_HSYNC; 8102 8103 if (mode->flags & (DRM_MODE_FLAG_BCAST | 8104 DRM_MODE_FLAG_PIXMUX | 8105 DRM_MODE_FLAG_CLKDIV2)) 8106 return MODE_BAD; 8107 8108 /* 8109 * Reject clearly excessive dotclocks early to 8110 * avoid having to worry about huge integers later. 8111 */ 8112 if (mode->clock > max_dotclock(dev_priv)) 8113 return MODE_CLOCK_HIGH; 8114 8115 /* Transcoder timing limits */ 8116 if (DISPLAY_VER(dev_priv) >= 11) { 8117 hdisplay_max = 16384; 8118 vdisplay_max = 8192; 8119 htotal_max = 16384; 8120 vtotal_max = 8192; 8121 } else if (DISPLAY_VER(dev_priv) >= 9 || 8122 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 8123 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ 8124 vdisplay_max = 4096; 8125 htotal_max = 8192; 8126 vtotal_max = 8192; 8127 } else if (DISPLAY_VER(dev_priv) >= 3) { 8128 hdisplay_max = 4096; 8129 vdisplay_max = 4096; 8130 htotal_max = 8192; 8131 vtotal_max = 8192; 8132 } else { 8133 hdisplay_max = 2048; 8134 vdisplay_max = 2048; 8135 htotal_max = 4096; 8136 vtotal_max = 4096; 8137 } 8138 8139 if (mode->hdisplay > hdisplay_max || 8140 mode->hsync_start > htotal_max || 8141 mode->hsync_end > htotal_max || 8142 mode->htotal > htotal_max) 8143 return MODE_H_ILLEGAL; 8144 8145 if (mode->vdisplay > vdisplay_max || 8146 mode->vsync_start > vtotal_max || 8147 mode->vsync_end > vtotal_max || 8148 mode->vtotal > vtotal_max) 8149 return MODE_V_ILLEGAL; 8150 8151 if (DISPLAY_VER(dev_priv) >= 5) { 8152 if (mode->hdisplay < 64 || 8153 mode->htotal - mode->hdisplay < 32) 8154 return MODE_H_ILLEGAL; 8155 8156 if (mode->vtotal - mode->vdisplay < 5) 8157 return MODE_V_ILLEGAL; 8158 } else { 8159 if (mode->htotal - mode->hdisplay < 32) 8160 return MODE_H_ILLEGAL; 8161 8162 if (mode->vtotal - mode->vdisplay < 3) 8163 return MODE_V_ILLEGAL; 8164 } 8165 8166 /* 8167 * Cantiga+ cannot handle modes with a hsync front porch of 0. 8168 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. 8169 */ 8170 if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) && 8171 mode->hsync_start == mode->hdisplay) 8172 return MODE_H_ILLEGAL; 8173 8174 return MODE_OK; 8175 } 8176 8177 enum drm_mode_status 8178 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 8179 const struct drm_display_mode *mode, 8180 bool bigjoiner) 8181 { 8182 int plane_width_max, plane_height_max; 8183 8184 /* 8185 * intel_mode_valid() should be 8186 * sufficient on older platforms. 8187 */ 8188 if (DISPLAY_VER(dev_priv) < 9) 8189 return MODE_OK; 8190 8191 /* 8192 * Most people will probably want a fullscreen 8193 * plane so let's not advertize modes that are 8194 * too big for that. 8195 */ 8196 if (DISPLAY_VER(dev_priv) >= 11) { 8197 plane_width_max = 5120 << bigjoiner; 8198 plane_height_max = 4320; 8199 } else { 8200 plane_width_max = 5120; 8201 plane_height_max = 4096; 8202 } 8203 8204 if (mode->hdisplay > plane_width_max) 8205 return MODE_H_ILLEGAL; 8206 8207 if (mode->vdisplay > plane_height_max) 8208 return MODE_V_ILLEGAL; 8209 8210 return MODE_OK; 8211 } 8212 8213 static const struct drm_mode_config_funcs intel_mode_funcs = { 8214 .fb_create = intel_user_framebuffer_create, 8215 .get_format_info = intel_fb_get_format_info, 8216 .output_poll_changed = intel_fbdev_output_poll_changed, 8217 .mode_valid = intel_mode_valid, 8218 .atomic_check = intel_atomic_check, 8219 .atomic_commit = intel_atomic_commit, 8220 .atomic_state_alloc = intel_atomic_state_alloc, 8221 .atomic_state_clear = intel_atomic_state_clear, 8222 .atomic_state_free = intel_atomic_state_free, 8223 }; 8224 8225 static const struct intel_display_funcs skl_display_funcs = { 8226 .get_pipe_config = hsw_get_pipe_config, 8227 .crtc_enable = hsw_crtc_enable, 8228 .crtc_disable = hsw_crtc_disable, 8229 .commit_modeset_enables = skl_commit_modeset_enables, 8230 .get_initial_plane_config = skl_get_initial_plane_config, 8231 }; 8232 8233 static const struct intel_display_funcs ddi_display_funcs = { 8234 .get_pipe_config = hsw_get_pipe_config, 8235 .crtc_enable = hsw_crtc_enable, 8236 .crtc_disable = hsw_crtc_disable, 8237 .commit_modeset_enables = intel_commit_modeset_enables, 8238 .get_initial_plane_config = i9xx_get_initial_plane_config, 8239 }; 8240 8241 static const struct intel_display_funcs pch_split_display_funcs = { 8242 .get_pipe_config = ilk_get_pipe_config, 8243 .crtc_enable = ilk_crtc_enable, 8244 .crtc_disable = ilk_crtc_disable, 8245 .commit_modeset_enables = intel_commit_modeset_enables, 8246 .get_initial_plane_config = i9xx_get_initial_plane_config, 8247 }; 8248 8249 static const struct intel_display_funcs vlv_display_funcs = { 8250 .get_pipe_config = i9xx_get_pipe_config, 8251 .crtc_enable = valleyview_crtc_enable, 8252 .crtc_disable = i9xx_crtc_disable, 8253 .commit_modeset_enables = intel_commit_modeset_enables, 8254 .get_initial_plane_config = i9xx_get_initial_plane_config, 8255 }; 8256 8257 static const struct intel_display_funcs i9xx_display_funcs = { 8258 .get_pipe_config = i9xx_get_pipe_config, 8259 .crtc_enable = i9xx_crtc_enable, 8260 .crtc_disable = i9xx_crtc_disable, 8261 .commit_modeset_enables = intel_commit_modeset_enables, 8262 .get_initial_plane_config = i9xx_get_initial_plane_config, 8263 }; 8264 8265 /** 8266 * intel_init_display_hooks - initialize the display modesetting hooks 8267 * @dev_priv: device private 8268 */ 8269 void intel_init_display_hooks(struct drm_i915_private *dev_priv) 8270 { 8271 if (!HAS_DISPLAY(dev_priv)) 8272 return; 8273 8274 intel_color_init_hooks(dev_priv); 8275 intel_init_cdclk_hooks(dev_priv); 8276 intel_audio_hooks_init(dev_priv); 8277 8278 intel_dpll_init_clock_hook(dev_priv); 8279 8280 if (DISPLAY_VER(dev_priv) >= 9) { 8281 dev_priv->display.funcs.display = &skl_display_funcs; 8282 } else if (HAS_DDI(dev_priv)) { 8283 dev_priv->display.funcs.display = &ddi_display_funcs; 8284 } else if (HAS_PCH_SPLIT(dev_priv)) { 8285 dev_priv->display.funcs.display = &pch_split_display_funcs; 8286 } else if (IS_CHERRYVIEW(dev_priv) || 8287 IS_VALLEYVIEW(dev_priv)) { 8288 dev_priv->display.funcs.display = &vlv_display_funcs; 8289 } else { 8290 dev_priv->display.funcs.display = &i9xx_display_funcs; 8291 } 8292 8293 intel_fdi_init_hook(dev_priv); 8294 } 8295 8296 void intel_modeset_init_hw(struct drm_i915_private *i915) 8297 { 8298 struct intel_cdclk_state *cdclk_state; 8299 8300 if (!HAS_DISPLAY(i915)) 8301 return; 8302 8303 cdclk_state = to_intel_cdclk_state(i915->display.cdclk.obj.state); 8304 8305 intel_update_cdclk(i915); 8306 intel_cdclk_dump_config(i915, &i915->display.cdclk.hw, "Current CDCLK"); 8307 cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw; 8308 } 8309 8310 static int intel_initial_commit(struct drm_device *dev) 8311 { 8312 struct drm_atomic_state *state = NULL; 8313 struct drm_modeset_acquire_ctx ctx; 8314 struct intel_crtc *crtc; 8315 int ret = 0; 8316 8317 state = drm_atomic_state_alloc(dev); 8318 if (!state) 8319 return -ENOMEM; 8320 8321 drm_modeset_acquire_init(&ctx, 0); 8322 8323 retry: 8324 state->acquire_ctx = &ctx; 8325 8326 for_each_intel_crtc(dev, crtc) { 8327 struct intel_crtc_state *crtc_state = 8328 intel_atomic_get_crtc_state(state, crtc); 8329 8330 if (IS_ERR(crtc_state)) { 8331 ret = PTR_ERR(crtc_state); 8332 goto out; 8333 } 8334 8335 if (crtc_state->hw.active) { 8336 struct intel_encoder *encoder; 8337 8338 /* 8339 * We've not yet detected sink capabilities 8340 * (audio,infoframes,etc.) and thus we don't want to 8341 * force a full state recomputation yet. We want that to 8342 * happen only for the first real commit from userspace. 8343 * So preserve the inherited flag for the time being. 8344 */ 8345 crtc_state->inherited = true; 8346 8347 ret = drm_atomic_add_affected_planes(state, &crtc->base); 8348 if (ret) 8349 goto out; 8350 8351 /* 8352 * FIXME hack to force a LUT update to avoid the 8353 * plane update forcing the pipe gamma on without 8354 * having a proper LUT loaded. Remove once we 8355 * have readout for pipe gamma enable. 8356 */ 8357 crtc_state->uapi.color_mgmt_changed = true; 8358 8359 for_each_intel_encoder_mask(dev, encoder, 8360 crtc_state->uapi.encoder_mask) { 8361 if (encoder->initial_fastset_check && 8362 !encoder->initial_fastset_check(encoder, crtc_state)) { 8363 ret = drm_atomic_add_affected_connectors(state, 8364 &crtc->base); 8365 if (ret) 8366 goto out; 8367 } 8368 } 8369 } 8370 } 8371 8372 ret = drm_atomic_commit(state); 8373 8374 out: 8375 if (ret == -EDEADLK) { 8376 drm_atomic_state_clear(state); 8377 drm_modeset_backoff(&ctx); 8378 goto retry; 8379 } 8380 8381 drm_atomic_state_put(state); 8382 8383 drm_modeset_drop_locks(&ctx); 8384 drm_modeset_acquire_fini(&ctx); 8385 8386 return ret; 8387 } 8388 8389 static const struct drm_mode_config_helper_funcs intel_mode_config_funcs = { 8390 .atomic_commit_setup = drm_dp_mst_atomic_setup_commit, 8391 }; 8392 8393 static void intel_mode_config_init(struct drm_i915_private *i915) 8394 { 8395 struct drm_mode_config *mode_config = &i915->drm.mode_config; 8396 8397 drm_mode_config_init(&i915->drm); 8398 INIT_LIST_HEAD(&i915->display.global.obj_list); 8399 8400 mode_config->min_width = 0; 8401 mode_config->min_height = 0; 8402 8403 mode_config->preferred_depth = 24; 8404 mode_config->prefer_shadow = 1; 8405 8406 mode_config->funcs = &intel_mode_funcs; 8407 mode_config->helper_private = &intel_mode_config_funcs; 8408 8409 mode_config->async_page_flip = HAS_ASYNC_FLIPS(i915); 8410 8411 /* 8412 * Maximum framebuffer dimensions, chosen to match 8413 * the maximum render engine surface size on gen4+. 8414 */ 8415 if (DISPLAY_VER(i915) >= 7) { 8416 mode_config->max_width = 16384; 8417 mode_config->max_height = 16384; 8418 } else if (DISPLAY_VER(i915) >= 4) { 8419 mode_config->max_width = 8192; 8420 mode_config->max_height = 8192; 8421 } else if (DISPLAY_VER(i915) == 3) { 8422 mode_config->max_width = 4096; 8423 mode_config->max_height = 4096; 8424 } else { 8425 mode_config->max_width = 2048; 8426 mode_config->max_height = 2048; 8427 } 8428 8429 if (IS_I845G(i915) || IS_I865G(i915)) { 8430 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512; 8431 mode_config->cursor_height = 1023; 8432 } else if (IS_I830(i915) || IS_I85X(i915) || 8433 IS_I915G(i915) || IS_I915GM(i915)) { 8434 mode_config->cursor_width = 64; 8435 mode_config->cursor_height = 64; 8436 } else { 8437 mode_config->cursor_width = 256; 8438 mode_config->cursor_height = 256; 8439 } 8440 } 8441 8442 static void intel_mode_config_cleanup(struct drm_i915_private *i915) 8443 { 8444 intel_atomic_global_obj_cleanup(i915); 8445 drm_mode_config_cleanup(&i915->drm); 8446 } 8447 8448 /* part #1: call before irq install */ 8449 int intel_modeset_init_noirq(struct drm_i915_private *i915) 8450 { 8451 int ret; 8452 8453 if (i915_inject_probe_failure(i915)) 8454 return -ENODEV; 8455 8456 if (HAS_DISPLAY(i915)) { 8457 ret = drm_vblank_init(&i915->drm, 8458 INTEL_NUM_PIPES(i915)); 8459 if (ret) 8460 return ret; 8461 } 8462 8463 intel_bios_init(i915); 8464 8465 ret = intel_vga_register(i915); 8466 if (ret) 8467 goto cleanup_bios; 8468 8469 /* FIXME: completely on the wrong abstraction layer */ 8470 ret = intel_power_domains_init(i915); 8471 if (ret < 0) 8472 goto cleanup_vga; 8473 8474 intel_power_domains_init_hw(i915, false); 8475 8476 if (!HAS_DISPLAY(i915)) 8477 return 0; 8478 8479 intel_dmc_init(i915); 8480 8481 i915->display.wq.modeset = alloc_ordered_workqueue("i915_modeset", 0); 8482 i915->display.wq.flip = alloc_workqueue("i915_flip", WQ_HIGHPRI | 8483 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE); 8484 8485 intel_mode_config_init(i915); 8486 8487 ret = intel_cdclk_init(i915); 8488 if (ret) 8489 goto cleanup_vga_client_pw_domain_dmc; 8490 8491 ret = intel_color_init(i915); 8492 if (ret) 8493 goto cleanup_vga_client_pw_domain_dmc; 8494 8495 ret = intel_dbuf_init(i915); 8496 if (ret) 8497 goto cleanup_vga_client_pw_domain_dmc; 8498 8499 ret = intel_bw_init(i915); 8500 if (ret) 8501 goto cleanup_vga_client_pw_domain_dmc; 8502 8503 init_llist_head(&i915->display.atomic_helper.free_list); 8504 INIT_WORK(&i915->display.atomic_helper.free_work, 8505 intel_atomic_helper_free_state_worker); 8506 8507 intel_init_quirks(i915); 8508 8509 intel_fbc_init(i915); 8510 8511 return 0; 8512 8513 cleanup_vga_client_pw_domain_dmc: 8514 intel_dmc_fini(i915); 8515 intel_power_domains_driver_remove(i915); 8516 cleanup_vga: 8517 intel_vga_unregister(i915); 8518 cleanup_bios: 8519 intel_bios_driver_remove(i915); 8520 8521 return ret; 8522 } 8523 8524 /* part #2: call after irq install, but before gem init */ 8525 int intel_modeset_init_nogem(struct drm_i915_private *i915) 8526 { 8527 struct drm_device *dev = &i915->drm; 8528 enum pipe pipe; 8529 struct intel_crtc *crtc; 8530 int ret; 8531 8532 if (!HAS_DISPLAY(i915)) 8533 return 0; 8534 8535 intel_wm_init(i915); 8536 8537 intel_panel_sanitize_ssc(i915); 8538 8539 intel_pps_setup(i915); 8540 8541 intel_gmbus_setup(i915); 8542 8543 drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n", 8544 INTEL_NUM_PIPES(i915), 8545 INTEL_NUM_PIPES(i915) > 1 ? "s" : ""); 8546 8547 for_each_pipe(i915, pipe) { 8548 ret = intel_crtc_init(i915, pipe); 8549 if (ret) { 8550 intel_mode_config_cleanup(i915); 8551 return ret; 8552 } 8553 } 8554 8555 intel_plane_possible_crtcs_init(i915); 8556 intel_shared_dpll_init(i915); 8557 intel_fdi_pll_freq_update(i915); 8558 8559 intel_update_czclk(i915); 8560 intel_modeset_init_hw(i915); 8561 intel_dpll_update_ref_clks(i915); 8562 8563 intel_hdcp_component_init(i915); 8564 8565 if (i915->display.cdclk.max_cdclk_freq == 0) 8566 intel_update_max_cdclk(i915); 8567 8568 intel_hti_init(i915); 8569 8570 /* Just disable it once at startup */ 8571 intel_vga_disable(i915); 8572 intel_setup_outputs(i915); 8573 8574 drm_modeset_lock_all(dev); 8575 intel_modeset_setup_hw_state(i915, dev->mode_config.acquire_ctx); 8576 intel_acpi_assign_connector_fwnodes(i915); 8577 drm_modeset_unlock_all(dev); 8578 8579 for_each_intel_crtc(dev, crtc) { 8580 if (!to_intel_crtc_state(crtc->base.state)->uapi.active) 8581 continue; 8582 intel_crtc_initial_plane_config(crtc); 8583 } 8584 8585 /* 8586 * Make sure hardware watermarks really match the state we read out. 8587 * Note that we need to do this after reconstructing the BIOS fb's 8588 * since the watermark calculation done here will use pstate->fb. 8589 */ 8590 if (!HAS_GMCH(i915)) 8591 ilk_wm_sanitize(i915); 8592 8593 return 0; 8594 } 8595 8596 /* part #3: call after gem init */ 8597 int intel_modeset_init(struct drm_i915_private *i915) 8598 { 8599 int ret; 8600 8601 if (!HAS_DISPLAY(i915)) 8602 return 0; 8603 8604 /* 8605 * Force all active planes to recompute their states. So that on 8606 * mode_setcrtc after probe, all the intel_plane_state variables 8607 * are already calculated and there is no assert_plane warnings 8608 * during bootup. 8609 */ 8610 ret = intel_initial_commit(&i915->drm); 8611 if (ret) 8612 drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret); 8613 8614 intel_overlay_setup(i915); 8615 8616 ret = intel_fbdev_init(&i915->drm); 8617 if (ret) 8618 return ret; 8619 8620 /* Only enable hotplug handling once the fbdev is fully set up. */ 8621 intel_hpd_init(i915); 8622 intel_hpd_poll_disable(i915); 8623 8624 skl_watermark_ipc_init(i915); 8625 8626 return 0; 8627 } 8628 8629 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 8630 { 8631 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 8632 enum transcoder cpu_transcoder = (enum transcoder)pipe; 8633 /* 640x480@60Hz, ~25175 kHz */ 8634 struct dpll clock = { 8635 .m1 = 18, 8636 .m2 = 7, 8637 .p1 = 13, 8638 .p2 = 4, 8639 .n = 2, 8640 }; 8641 u32 dpll, fp; 8642 int i; 8643 8644 drm_WARN_ON(&dev_priv->drm, 8645 i9xx_calc_dpll_params(48000, &clock) != 25154); 8646 8647 drm_dbg_kms(&dev_priv->drm, 8648 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n", 8649 pipe_name(pipe), clock.vco, clock.dot); 8650 8651 fp = i9xx_dpll_compute_fp(&clock); 8652 dpll = DPLL_DVO_2X_MODE | 8653 DPLL_VGA_MODE_DIS | 8654 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | 8655 PLL_P2_DIVIDE_BY_4 | 8656 PLL_REF_INPUT_DREFCLK | 8657 DPLL_VCO_ENABLE; 8658 8659 intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder), 8660 HACTIVE(640 - 1) | HTOTAL(800 - 1)); 8661 intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder), 8662 HBLANK_START(640 - 1) | HBLANK_END(800 - 1)); 8663 intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder), 8664 HSYNC_START(656 - 1) | HSYNC_END(752 - 1)); 8665 intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder), 8666 VACTIVE(480 - 1) | VTOTAL(525 - 1)); 8667 intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), 8668 VBLANK_START(480 - 1) | VBLANK_END(525 - 1)); 8669 intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder), 8670 VSYNC_START(490 - 1) | VSYNC_END(492 - 1)); 8671 intel_de_write(dev_priv, PIPESRC(pipe), 8672 PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1)); 8673 8674 intel_de_write(dev_priv, FP0(pipe), fp); 8675 intel_de_write(dev_priv, FP1(pipe), fp); 8676 8677 /* 8678 * Apparently we need to have VGA mode enabled prior to changing 8679 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 8680 * dividers, even though the register value does change. 8681 */ 8682 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); 8683 intel_de_write(dev_priv, DPLL(pipe), dpll); 8684 8685 /* Wait for the clocks to stabilize. */ 8686 intel_de_posting_read(dev_priv, DPLL(pipe)); 8687 udelay(150); 8688 8689 /* The pixel multiplier can only be updated once the 8690 * DPLL is enabled and the clocks are stable. 8691 * 8692 * So write it again. 8693 */ 8694 intel_de_write(dev_priv, DPLL(pipe), dpll); 8695 8696 /* We do this three times for luck */ 8697 for (i = 0; i < 3 ; i++) { 8698 intel_de_write(dev_priv, DPLL(pipe), dpll); 8699 intel_de_posting_read(dev_priv, DPLL(pipe)); 8700 udelay(150); /* wait for warmup */ 8701 } 8702 8703 intel_de_write(dev_priv, TRANSCONF(pipe), TRANSCONF_ENABLE); 8704 intel_de_posting_read(dev_priv, TRANSCONF(pipe)); 8705 8706 intel_wait_for_pipe_scanline_moving(crtc); 8707 } 8708 8709 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 8710 { 8711 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 8712 8713 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n", 8714 pipe_name(pipe)); 8715 8716 drm_WARN_ON(&dev_priv->drm, 8717 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE); 8718 drm_WARN_ON(&dev_priv->drm, 8719 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE); 8720 drm_WARN_ON(&dev_priv->drm, 8721 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE); 8722 drm_WARN_ON(&dev_priv->drm, 8723 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK); 8724 drm_WARN_ON(&dev_priv->drm, 8725 intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK); 8726 8727 intel_de_write(dev_priv, TRANSCONF(pipe), 0); 8728 intel_de_posting_read(dev_priv, TRANSCONF(pipe)); 8729 8730 intel_wait_for_pipe_scanline_stopped(crtc); 8731 8732 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); 8733 intel_de_posting_read(dev_priv, DPLL(pipe)); 8734 } 8735 8736 void intel_display_resume(struct drm_device *dev) 8737 { 8738 struct drm_i915_private *i915 = to_i915(dev); 8739 struct drm_atomic_state *state = i915->display.restore.modeset_state; 8740 struct drm_modeset_acquire_ctx ctx; 8741 int ret; 8742 8743 if (!HAS_DISPLAY(i915)) 8744 return; 8745 8746 i915->display.restore.modeset_state = NULL; 8747 if (state) 8748 state->acquire_ctx = &ctx; 8749 8750 drm_modeset_acquire_init(&ctx, 0); 8751 8752 while (1) { 8753 ret = drm_modeset_lock_all_ctx(dev, &ctx); 8754 if (ret != -EDEADLK) 8755 break; 8756 8757 drm_modeset_backoff(&ctx); 8758 } 8759 8760 if (!ret) 8761 ret = __intel_display_resume(i915, state, &ctx); 8762 8763 skl_watermark_ipc_update(i915); 8764 drm_modeset_drop_locks(&ctx); 8765 drm_modeset_acquire_fini(&ctx); 8766 8767 if (ret) 8768 drm_err(&i915->drm, 8769 "Restoring old state failed with %i\n", ret); 8770 if (state) 8771 drm_atomic_state_put(state); 8772 } 8773 8774 static void intel_hpd_poll_fini(struct drm_i915_private *i915) 8775 { 8776 struct intel_connector *connector; 8777 struct drm_connector_list_iter conn_iter; 8778 8779 /* Kill all the work that may have been queued by hpd. */ 8780 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 8781 for_each_intel_connector_iter(connector, &conn_iter) { 8782 if (connector->modeset_retry_work.func) 8783 cancel_work_sync(&connector->modeset_retry_work); 8784 if (connector->hdcp.shim) { 8785 cancel_delayed_work_sync(&connector->hdcp.check_work); 8786 cancel_work_sync(&connector->hdcp.prop_work); 8787 } 8788 } 8789 drm_connector_list_iter_end(&conn_iter); 8790 } 8791 8792 /* part #1: call before irq uninstall */ 8793 void intel_modeset_driver_remove(struct drm_i915_private *i915) 8794 { 8795 if (!HAS_DISPLAY(i915)) 8796 return; 8797 8798 flush_workqueue(i915->display.wq.flip); 8799 flush_workqueue(i915->display.wq.modeset); 8800 8801 flush_work(&i915->display.atomic_helper.free_work); 8802 drm_WARN_ON(&i915->drm, !llist_empty(&i915->display.atomic_helper.free_list)); 8803 8804 /* 8805 * MST topology needs to be suspended so we don't have any calls to 8806 * fbdev after it's finalized. MST will be destroyed later as part of 8807 * drm_mode_config_cleanup() 8808 */ 8809 intel_dp_mst_suspend(i915); 8810 } 8811 8812 /* part #2: call after irq uninstall */ 8813 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915) 8814 { 8815 if (!HAS_DISPLAY(i915)) 8816 return; 8817 8818 /* 8819 * Due to the hpd irq storm handling the hotplug work can re-arm the 8820 * poll handlers. Hence disable polling after hpd handling is shut down. 8821 */ 8822 intel_hpd_poll_fini(i915); 8823 8824 /* poll work can call into fbdev, hence clean that up afterwards */ 8825 intel_fbdev_fini(i915); 8826 8827 intel_unregister_dsm_handler(); 8828 8829 /* flush any delayed tasks or pending work */ 8830 flush_scheduled_work(); 8831 8832 intel_hdcp_component_fini(i915); 8833 8834 intel_mode_config_cleanup(i915); 8835 8836 intel_overlay_cleanup(i915); 8837 8838 intel_gmbus_teardown(i915); 8839 8840 destroy_workqueue(i915->display.wq.flip); 8841 destroy_workqueue(i915->display.wq.modeset); 8842 8843 intel_fbc_cleanup(i915); 8844 } 8845 8846 /* part #3: call after gem init */ 8847 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915) 8848 { 8849 intel_dmc_fini(i915); 8850 8851 intel_power_domains_driver_remove(i915); 8852 8853 intel_vga_unregister(i915); 8854 8855 intel_bios_driver_remove(i915); 8856 } 8857 8858 bool intel_modeset_probe_defer(struct pci_dev *pdev) 8859 { 8860 struct drm_privacy_screen *privacy_screen; 8861 8862 /* 8863 * apple-gmux is needed on dual GPU MacBook Pro 8864 * to probe the panel if we're the inactive GPU. 8865 */ 8866 if (vga_switcheroo_client_probe_defer(pdev)) 8867 return true; 8868 8869 /* If the LCD panel has a privacy-screen, wait for it */ 8870 privacy_screen = drm_privacy_screen_get(&pdev->dev, NULL); 8871 if (IS_ERR(privacy_screen) && PTR_ERR(privacy_screen) == -EPROBE_DEFER) 8872 return true; 8873 8874 drm_privacy_screen_put(privacy_screen); 8875 8876 return false; 8877 } 8878 8879 void intel_display_driver_register(struct drm_i915_private *i915) 8880 { 8881 if (!HAS_DISPLAY(i915)) 8882 return; 8883 8884 intel_display_debugfs_register(i915); 8885 8886 /* Must be done after probing outputs */ 8887 intel_opregion_register(i915); 8888 intel_acpi_video_register(i915); 8889 8890 intel_audio_init(i915); 8891 8892 /* 8893 * Some ports require correctly set-up hpd registers for 8894 * detection to work properly (leading to ghost connected 8895 * connector status), e.g. VGA on gm45. Hence we can only set 8896 * up the initial fbdev config after hpd irqs are fully 8897 * enabled. We do it last so that the async config cannot run 8898 * before the connectors are registered. 8899 */ 8900 intel_fbdev_initial_config_async(i915); 8901 8902 /* 8903 * We need to coordinate the hotplugs with the asynchronous 8904 * fbdev configuration, for which we use the 8905 * fbdev->async_cookie. 8906 */ 8907 drm_kms_helper_poll_init(&i915->drm); 8908 } 8909 8910 void intel_display_driver_unregister(struct drm_i915_private *i915) 8911 { 8912 if (!HAS_DISPLAY(i915)) 8913 return; 8914 8915 intel_fbdev_unregister(i915); 8916 intel_audio_deinit(i915); 8917 8918 /* 8919 * After flushing the fbdev (incl. a late async config which 8920 * will have delayed queuing of a hotplug event), then flush 8921 * the hotplug events. 8922 */ 8923 drm_kms_helper_poll_fini(&i915->drm); 8924 drm_atomic_helper_shutdown(&i915->drm); 8925 8926 acpi_video_unregister(); 8927 intel_opregion_unregister(i915); 8928 } 8929 8930 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915) 8931 { 8932 return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915); 8933 } 8934