1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <linux/dma-resv.h> 28 #include <linux/i2c.h> 29 #include <linux/input.h> 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/slab.h> 33 #include <linux/string_helpers.h> 34 #include <linux/vga_switcheroo.h> 35 #include <acpi/video.h> 36 37 #include <drm/display/drm_dp_helper.h> 38 #include <drm/drm_atomic.h> 39 #include <drm/drm_atomic_helper.h> 40 #include <drm/drm_atomic_uapi.h> 41 #include <drm/drm_damage_helper.h> 42 #include <drm/drm_edid.h> 43 #include <drm/drm_fourcc.h> 44 #include <drm/drm_privacy_screen_consumer.h> 45 #include <drm/drm_probe_helper.h> 46 #include <drm/drm_rect.h> 47 48 #include "gem/i915_gem_lmem.h" 49 #include "gem/i915_gem_object.h" 50 51 #include "g4x_dp.h" 52 #include "g4x_hdmi.h" 53 #include "hsw_ips.h" 54 #include "i915_drv.h" 55 #include "i915_reg.h" 56 #include "i915_utils.h" 57 #include "i9xx_plane.h" 58 #include "i9xx_wm.h" 59 #include "icl_dsi.h" 60 #include "intel_acpi.h" 61 #include "intel_atomic.h" 62 #include "intel_atomic_plane.h" 63 #include "intel_audio.h" 64 #include "intel_bw.h" 65 #include "intel_cdclk.h" 66 #include "intel_color.h" 67 #include "intel_crt.h" 68 #include "intel_crtc.h" 69 #include "intel_crtc_state_dump.h" 70 #include "intel_ddi.h" 71 #include "intel_de.h" 72 #include "intel_display_debugfs.h" 73 #include "intel_display_power.h" 74 #include "intel_display_types.h" 75 #include "intel_dmc.h" 76 #include "intel_dp.h" 77 #include "intel_dp_link_training.h" 78 #include "intel_dp_mst.h" 79 #include "intel_dpio_phy.h" 80 #include "intel_dpll.h" 81 #include "intel_dpll_mgr.h" 82 #include "intel_dpt.h" 83 #include "intel_drrs.h" 84 #include "intel_dsi.h" 85 #include "intel_dvo.h" 86 #include "intel_fb.h" 87 #include "intel_fbc.h" 88 #include "intel_fbdev.h" 89 #include "intel_fdi.h" 90 #include "intel_fifo_underrun.h" 91 #include "intel_frontbuffer.h" 92 #include "intel_gmbus.h" 93 #include "intel_hdcp.h" 94 #include "intel_hdmi.h" 95 #include "intel_hotplug.h" 96 #include "intel_hti.h" 97 #include "intel_lvds.h" 98 #include "intel_lvds_regs.h" 99 #include "intel_modeset_setup.h" 100 #include "intel_modeset_verify.h" 101 #include "intel_overlay.h" 102 #include "intel_panel.h" 103 #include "intel_pch_display.h" 104 #include "intel_pch_refclk.h" 105 #include "intel_pcode.h" 106 #include "intel_pipe_crc.h" 107 #include "intel_plane_initial.h" 108 #include "intel_pm.h" 109 #include "intel_pps.h" 110 #include "intel_psr.h" 111 #include "intel_quirks.h" 112 #include "intel_sdvo.h" 113 #include "intel_snps_phy.h" 114 #include "intel_tc.h" 115 #include "intel_tv.h" 116 #include "intel_vblank.h" 117 #include "intel_vdsc.h" 118 #include "intel_vdsc_regs.h" 119 #include "intel_vga.h" 120 #include "intel_vrr.h" 121 #include "intel_wm.h" 122 #include "skl_scaler.h" 123 #include "skl_universal_plane.h" 124 #include "skl_watermark.h" 125 #include "vlv_dsi.h" 126 #include "vlv_dsi_pll.h" 127 #include "vlv_dsi_regs.h" 128 #include "vlv_sideband.h" 129 130 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state); 131 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state); 132 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state); 133 static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state); 134 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state); 135 136 /* returns HPLL frequency in kHz */ 137 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) 138 { 139 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; 140 141 /* Obtain SKU information */ 142 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & 143 CCK_FUSE_HPLL_FREQ_MASK; 144 145 return vco_freq[hpll_freq] * 1000; 146 } 147 148 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 149 const char *name, u32 reg, int ref_freq) 150 { 151 u32 val; 152 int divider; 153 154 val = vlv_cck_read(dev_priv, reg); 155 divider = val & CCK_FREQUENCY_VALUES; 156 157 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != 158 (divider << CCK_FREQUENCY_STATUS_SHIFT), 159 "%s change in progress\n", name); 160 161 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); 162 } 163 164 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 165 const char *name, u32 reg) 166 { 167 int hpll; 168 169 vlv_cck_get(dev_priv); 170 171 if (dev_priv->hpll_freq == 0) 172 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); 173 174 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); 175 176 vlv_cck_put(dev_priv); 177 178 return hpll; 179 } 180 181 static void intel_update_czclk(struct drm_i915_private *dev_priv) 182 { 183 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) 184 return; 185 186 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", 187 CCK_CZ_CLOCK_CONTROL); 188 189 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", 190 dev_priv->czclk_freq); 191 } 192 193 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state) 194 { 195 return (crtc_state->active_planes & 196 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0; 197 } 198 199 /* WA Display #0827: Gen9:all */ 200 static void 201 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) 202 { 203 if (enable) 204 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 205 0, DUPS1_GATING_DIS | DUPS2_GATING_DIS); 206 else 207 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 208 DUPS1_GATING_DIS | DUPS2_GATING_DIS, 0); 209 } 210 211 /* Wa_2006604312:icl,ehl */ 212 static void 213 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 214 bool enable) 215 { 216 if (enable) 217 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 0, DPFR_GATING_DIS); 218 else 219 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), DPFR_GATING_DIS, 0); 220 } 221 222 /* Wa_1604331009:icl,jsl,ehl */ 223 static void 224 icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 225 bool enable) 226 { 227 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), CURSOR_GATING_DIS, 228 enable ? CURSOR_GATING_DIS : 0); 229 } 230 231 static bool 232 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state) 233 { 234 return crtc_state->master_transcoder != INVALID_TRANSCODER; 235 } 236 237 static bool 238 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state) 239 { 240 return crtc_state->sync_mode_slaves_mask != 0; 241 } 242 243 bool 244 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state) 245 { 246 return is_trans_port_sync_master(crtc_state) || 247 is_trans_port_sync_slave(crtc_state); 248 } 249 250 static enum pipe bigjoiner_master_pipe(const struct intel_crtc_state *crtc_state) 251 { 252 return ffs(crtc_state->bigjoiner_pipes) - 1; 253 } 254 255 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state) 256 { 257 if (crtc_state->bigjoiner_pipes) 258 return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state)); 259 else 260 return 0; 261 } 262 263 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state) 264 { 265 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 266 267 return crtc_state->bigjoiner_pipes && 268 crtc->pipe != bigjoiner_master_pipe(crtc_state); 269 } 270 271 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state) 272 { 273 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 274 275 return crtc_state->bigjoiner_pipes && 276 crtc->pipe == bigjoiner_master_pipe(crtc_state); 277 } 278 279 static int intel_bigjoiner_num_pipes(const struct intel_crtc_state *crtc_state) 280 { 281 return hweight8(crtc_state->bigjoiner_pipes); 282 } 283 284 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state) 285 { 286 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 287 288 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 289 return intel_crtc_for_pipe(i915, bigjoiner_master_pipe(crtc_state)); 290 else 291 return to_intel_crtc(crtc_state->uapi.crtc); 292 } 293 294 static void 295 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) 296 { 297 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 298 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 299 300 if (DISPLAY_VER(dev_priv) >= 4) { 301 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 302 303 /* Wait for the Pipe State to go off */ 304 if (intel_de_wait_for_clear(dev_priv, TRANSCONF(cpu_transcoder), 305 TRANSCONF_STATE_ENABLE, 100)) 306 drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n"); 307 } else { 308 intel_wait_for_pipe_scanline_stopped(crtc); 309 } 310 } 311 312 void assert_transcoder(struct drm_i915_private *dev_priv, 313 enum transcoder cpu_transcoder, bool state) 314 { 315 bool cur_state; 316 enum intel_display_power_domain power_domain; 317 intel_wakeref_t wakeref; 318 319 /* we keep both pipes enabled on 830 */ 320 if (IS_I830(dev_priv)) 321 state = true; 322 323 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 324 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 325 if (wakeref) { 326 u32 val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)); 327 cur_state = !!(val & TRANSCONF_ENABLE); 328 329 intel_display_power_put(dev_priv, power_domain, wakeref); 330 } else { 331 cur_state = false; 332 } 333 334 I915_STATE_WARN(cur_state != state, 335 "transcoder %s assertion failure (expected %s, current %s)\n", 336 transcoder_name(cpu_transcoder), 337 str_on_off(state), str_on_off(cur_state)); 338 } 339 340 static void assert_plane(struct intel_plane *plane, bool state) 341 { 342 enum pipe pipe; 343 bool cur_state; 344 345 cur_state = plane->get_hw_state(plane, &pipe); 346 347 I915_STATE_WARN(cur_state != state, 348 "%s assertion failure (expected %s, current %s)\n", 349 plane->base.name, str_on_off(state), 350 str_on_off(cur_state)); 351 } 352 353 #define assert_plane_enabled(p) assert_plane(p, true) 354 #define assert_plane_disabled(p) assert_plane(p, false) 355 356 static void assert_planes_disabled(struct intel_crtc *crtc) 357 { 358 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 359 struct intel_plane *plane; 360 361 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) 362 assert_plane_disabled(plane); 363 } 364 365 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 366 struct intel_digital_port *dig_port, 367 unsigned int expected_mask) 368 { 369 u32 port_mask; 370 i915_reg_t dpll_reg; 371 372 switch (dig_port->base.port) { 373 default: 374 MISSING_CASE(dig_port->base.port); 375 fallthrough; 376 case PORT_B: 377 port_mask = DPLL_PORTB_READY_MASK; 378 dpll_reg = DPLL(0); 379 break; 380 case PORT_C: 381 port_mask = DPLL_PORTC_READY_MASK; 382 dpll_reg = DPLL(0); 383 expected_mask <<= 4; 384 break; 385 case PORT_D: 386 port_mask = DPLL_PORTD_READY_MASK; 387 dpll_reg = DPIO_PHY_STATUS; 388 break; 389 } 390 391 if (intel_de_wait_for_register(dev_priv, dpll_reg, 392 port_mask, expected_mask, 1000)) 393 drm_WARN(&dev_priv->drm, 1, 394 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", 395 dig_port->base.base.base.id, dig_port->base.base.name, 396 intel_de_read(dev_priv, dpll_reg) & port_mask, 397 expected_mask); 398 } 399 400 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) 401 { 402 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 403 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 404 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 405 enum pipe pipe = crtc->pipe; 406 i915_reg_t reg; 407 u32 val; 408 409 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe)); 410 411 assert_planes_disabled(crtc); 412 413 /* 414 * A pipe without a PLL won't actually be able to drive bits from 415 * a plane. On ILK+ the pipe PLLs are integrated, so we don't 416 * need the check. 417 */ 418 if (HAS_GMCH(dev_priv)) { 419 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI)) 420 assert_dsi_pll_enabled(dev_priv); 421 else 422 assert_pll_enabled(dev_priv, pipe); 423 } else { 424 if (new_crtc_state->has_pch_encoder) { 425 /* if driving the PCH, we need FDI enabled */ 426 assert_fdi_rx_pll_enabled(dev_priv, 427 intel_crtc_pch_transcoder(crtc)); 428 assert_fdi_tx_pll_enabled(dev_priv, 429 (enum pipe) cpu_transcoder); 430 } 431 /* FIXME: assert CPU port conditions for SNB+ */ 432 } 433 434 /* Wa_22012358565:adl-p */ 435 if (DISPLAY_VER(dev_priv) == 13) 436 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe), 437 0, PIPE_ARB_USE_PROG_SLOTS); 438 439 reg = TRANSCONF(cpu_transcoder); 440 val = intel_de_read(dev_priv, reg); 441 if (val & TRANSCONF_ENABLE) { 442 /* we keep both pipes enabled on 830 */ 443 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv)); 444 return; 445 } 446 447 intel_de_write(dev_priv, reg, val | TRANSCONF_ENABLE); 448 intel_de_posting_read(dev_priv, reg); 449 450 /* 451 * Until the pipe starts PIPEDSL reads will return a stale value, 452 * which causes an apparent vblank timestamp jump when PIPEDSL 453 * resets to its proper value. That also messes up the frame count 454 * when it's derived from the timestamps. So let's wait for the 455 * pipe to start properly before we call drm_crtc_vblank_on() 456 */ 457 if (intel_crtc_max_vblank_count(new_crtc_state) == 0) 458 intel_wait_for_pipe_scanline_moving(crtc); 459 } 460 461 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) 462 { 463 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 464 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 465 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 466 enum pipe pipe = crtc->pipe; 467 i915_reg_t reg; 468 u32 val; 469 470 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe)); 471 472 /* 473 * Make sure planes won't keep trying to pump pixels to us, 474 * or we might hang the display. 475 */ 476 assert_planes_disabled(crtc); 477 478 reg = TRANSCONF(cpu_transcoder); 479 val = intel_de_read(dev_priv, reg); 480 if ((val & TRANSCONF_ENABLE) == 0) 481 return; 482 483 /* 484 * Double wide has implications for planes 485 * so best keep it disabled when not needed. 486 */ 487 if (old_crtc_state->double_wide) 488 val &= ~TRANSCONF_DOUBLE_WIDE; 489 490 /* Don't disable pipe or pipe PLLs if needed */ 491 if (!IS_I830(dev_priv)) 492 val &= ~TRANSCONF_ENABLE; 493 494 if (DISPLAY_VER(dev_priv) >= 14) 495 intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder), 496 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 497 else if (DISPLAY_VER(dev_priv) >= 12) 498 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 499 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 500 501 intel_de_write(dev_priv, reg, val); 502 if ((val & TRANSCONF_ENABLE) == 0) 503 intel_wait_for_pipe_off(old_crtc_state); 504 } 505 506 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) 507 { 508 unsigned int size = 0; 509 int i; 510 511 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) 512 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width; 513 514 return size; 515 } 516 517 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info) 518 { 519 unsigned int size = 0; 520 int i; 521 522 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) { 523 unsigned int plane_size; 524 525 if (rem_info->plane[i].linear) 526 plane_size = rem_info->plane[i].size; 527 else 528 plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height; 529 530 if (plane_size == 0) 531 continue; 532 533 if (rem_info->plane_alignment) 534 size = ALIGN(size, rem_info->plane_alignment); 535 536 size += plane_size; 537 } 538 539 return size; 540 } 541 542 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) 543 { 544 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 545 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 546 547 return DISPLAY_VER(dev_priv) < 4 || 548 (plane->fbc && 549 plane_state->view.gtt.type == I915_GTT_VIEW_NORMAL); 550 } 551 552 /* 553 * Convert the x/y offsets into a linear offset. 554 * Only valid with 0/180 degree rotation, which is fine since linear 555 * offset is only used with linear buffers on pre-hsw and tiled buffers 556 * with gen2/3, and 90/270 degree rotations isn't supported on any of them. 557 */ 558 u32 intel_fb_xy_to_linear(int x, int y, 559 const struct intel_plane_state *state, 560 int color_plane) 561 { 562 const struct drm_framebuffer *fb = state->hw.fb; 563 unsigned int cpp = fb->format->cpp[color_plane]; 564 unsigned int pitch = state->view.color_plane[color_plane].mapping_stride; 565 566 return y * pitch + x * cpp; 567 } 568 569 /* 570 * Add the x/y offsets derived from fb->offsets[] to the user 571 * specified plane src x/y offsets. The resulting x/y offsets 572 * specify the start of scanout from the beginning of the gtt mapping. 573 */ 574 void intel_add_fb_offsets(int *x, int *y, 575 const struct intel_plane_state *state, 576 int color_plane) 577 578 { 579 *x += state->view.color_plane[color_plane].x; 580 *y += state->view.color_plane[color_plane].y; 581 } 582 583 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 584 u32 pixel_format, u64 modifier) 585 { 586 struct intel_crtc *crtc; 587 struct intel_plane *plane; 588 589 if (!HAS_DISPLAY(dev_priv)) 590 return 0; 591 592 /* 593 * We assume the primary plane for pipe A has 594 * the highest stride limits of them all, 595 * if in case pipe A is disabled, use the first pipe from pipe_mask. 596 */ 597 crtc = intel_first_crtc(dev_priv); 598 if (!crtc) 599 return 0; 600 601 plane = to_intel_plane(crtc->base.primary); 602 603 return plane->max_stride(plane, pixel_format, modifier, 604 DRM_MODE_ROTATE_0); 605 } 606 607 void intel_set_plane_visible(struct intel_crtc_state *crtc_state, 608 struct intel_plane_state *plane_state, 609 bool visible) 610 { 611 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 612 613 plane_state->uapi.visible = visible; 614 615 if (visible) 616 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base); 617 else 618 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base); 619 } 620 621 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state) 622 { 623 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 624 struct drm_plane *plane; 625 626 /* 627 * Active_planes aliases if multiple "primary" or cursor planes 628 * have been used on the same (or wrong) pipe. plane_mask uses 629 * unique ids, hence we can use that to reconstruct active_planes. 630 */ 631 crtc_state->enabled_planes = 0; 632 crtc_state->active_planes = 0; 633 634 drm_for_each_plane_mask(plane, &dev_priv->drm, 635 crtc_state->uapi.plane_mask) { 636 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id); 637 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id); 638 } 639 } 640 641 void intel_plane_disable_noatomic(struct intel_crtc *crtc, 642 struct intel_plane *plane) 643 { 644 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 645 struct intel_crtc_state *crtc_state = 646 to_intel_crtc_state(crtc->base.state); 647 struct intel_plane_state *plane_state = 648 to_intel_plane_state(plane->base.state); 649 650 drm_dbg_kms(&dev_priv->drm, 651 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n", 652 plane->base.base.id, plane->base.name, 653 crtc->base.base.id, crtc->base.name); 654 655 intel_set_plane_visible(crtc_state, plane_state, false); 656 intel_plane_fixup_bitmasks(crtc_state); 657 crtc_state->data_rate[plane->id] = 0; 658 crtc_state->data_rate_y[plane->id] = 0; 659 crtc_state->rel_data_rate[plane->id] = 0; 660 crtc_state->rel_data_rate_y[plane->id] = 0; 661 crtc_state->min_cdclk[plane->id] = 0; 662 663 if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 && 664 hsw_ips_disable(crtc_state)) { 665 crtc_state->ips_enabled = false; 666 intel_crtc_wait_for_next_vblank(crtc); 667 } 668 669 /* 670 * Vblank time updates from the shadow to live plane control register 671 * are blocked if the memory self-refresh mode is active at that 672 * moment. So to make sure the plane gets truly disabled, disable 673 * first the self-refresh mode. The self-refresh enable bit in turn 674 * will be checked/applied by the HW only at the next frame start 675 * event which is after the vblank start event, so we need to have a 676 * wait-for-vblank between disabling the plane and the pipe. 677 */ 678 if (HAS_GMCH(dev_priv) && 679 intel_set_memory_cxsr(dev_priv, false)) 680 intel_crtc_wait_for_next_vblank(crtc); 681 682 /* 683 * Gen2 reports pipe underruns whenever all planes are disabled. 684 * So disable underrun reporting before all the planes get disabled. 685 */ 686 if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes) 687 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); 688 689 intel_plane_disable_arm(plane, crtc_state); 690 intel_crtc_wait_for_next_vblank(crtc); 691 } 692 693 unsigned int 694 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state) 695 { 696 int x = 0, y = 0; 697 698 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, 699 plane_state->view.color_plane[0].offset, 0); 700 701 return y; 702 } 703 704 static int 705 intel_display_commit_duplicated_state(struct intel_atomic_state *state, 706 struct drm_modeset_acquire_ctx *ctx) 707 { 708 struct drm_i915_private *i915 = to_i915(state->base.dev); 709 int ret; 710 711 ret = drm_atomic_helper_commit_duplicated_state(&state->base, ctx); 712 713 drm_WARN_ON(&i915->drm, ret == -EDEADLK); 714 715 return ret; 716 } 717 718 static int 719 __intel_display_resume(struct drm_i915_private *i915, 720 struct drm_atomic_state *state, 721 struct drm_modeset_acquire_ctx *ctx) 722 { 723 struct drm_crtc_state *crtc_state; 724 struct drm_crtc *crtc; 725 int i; 726 727 intel_modeset_setup_hw_state(i915, ctx); 728 intel_vga_redisable(i915); 729 730 if (!state) 731 return 0; 732 733 /* 734 * We've duplicated the state, pointers to the old state are invalid. 735 * 736 * Don't attempt to use the old state until we commit the duplicated state. 737 */ 738 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 739 /* 740 * Force recalculation even if we restore 741 * current state. With fast modeset this may not result 742 * in a modeset when the state is compatible. 743 */ 744 crtc_state->mode_changed = true; 745 } 746 747 /* ignore any reset values/BIOS leftovers in the WM registers */ 748 if (!HAS_GMCH(i915)) 749 to_intel_atomic_state(state)->skip_intermediate_wm = true; 750 751 return intel_display_commit_duplicated_state(to_intel_atomic_state(state), ctx); 752 } 753 754 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) 755 { 756 return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display && 757 intel_has_gpu_reset(to_gt(dev_priv))); 758 } 759 760 void intel_display_prepare_reset(struct drm_i915_private *dev_priv) 761 { 762 struct drm_modeset_acquire_ctx *ctx = &dev_priv->display.restore.reset_ctx; 763 struct drm_atomic_state *state; 764 int ret; 765 766 if (!HAS_DISPLAY(dev_priv)) 767 return; 768 769 /* reset doesn't touch the display */ 770 if (!dev_priv->params.force_reset_modeset_test && 771 !gpu_reset_clobbers_display(dev_priv)) 772 return; 773 774 /* We have a modeset vs reset deadlock, defensively unbreak it. */ 775 set_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags); 776 smp_mb__after_atomic(); 777 wake_up_bit(&to_gt(dev_priv)->reset.flags, I915_RESET_MODESET); 778 779 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) { 780 drm_dbg_kms(&dev_priv->drm, 781 "Modeset potentially stuck, unbreaking through wedging\n"); 782 intel_gt_set_wedged(to_gt(dev_priv)); 783 } 784 785 /* 786 * Need mode_config.mutex so that we don't 787 * trample ongoing ->detect() and whatnot. 788 */ 789 mutex_lock(&dev_priv->drm.mode_config.mutex); 790 drm_modeset_acquire_init(ctx, 0); 791 while (1) { 792 ret = drm_modeset_lock_all_ctx(&dev_priv->drm, ctx); 793 if (ret != -EDEADLK) 794 break; 795 796 drm_modeset_backoff(ctx); 797 } 798 /* 799 * Disabling the crtcs gracefully seems nicer. Also the 800 * g33 docs say we should at least disable all the planes. 801 */ 802 state = drm_atomic_helper_duplicate_state(&dev_priv->drm, ctx); 803 if (IS_ERR(state)) { 804 ret = PTR_ERR(state); 805 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n", 806 ret); 807 return; 808 } 809 810 ret = drm_atomic_helper_disable_all(&dev_priv->drm, ctx); 811 if (ret) { 812 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", 813 ret); 814 drm_atomic_state_put(state); 815 return; 816 } 817 818 dev_priv->display.restore.modeset_state = state; 819 state->acquire_ctx = ctx; 820 } 821 822 void intel_display_finish_reset(struct drm_i915_private *i915) 823 { 824 struct drm_modeset_acquire_ctx *ctx = &i915->display.restore.reset_ctx; 825 struct drm_atomic_state *state; 826 int ret; 827 828 if (!HAS_DISPLAY(i915)) 829 return; 830 831 /* reset doesn't touch the display */ 832 if (!test_bit(I915_RESET_MODESET, &to_gt(i915)->reset.flags)) 833 return; 834 835 state = fetch_and_zero(&i915->display.restore.modeset_state); 836 if (!state) 837 goto unlock; 838 839 /* reset doesn't touch the display */ 840 if (!gpu_reset_clobbers_display(i915)) { 841 /* for testing only restore the display */ 842 ret = intel_display_commit_duplicated_state(to_intel_atomic_state(state), ctx); 843 if (ret) 844 drm_err(&i915->drm, 845 "Restoring old state failed with %i\n", ret); 846 } else { 847 /* 848 * The display has been reset as well, 849 * so need a full re-initialization. 850 */ 851 intel_pps_unlock_regs_wa(i915); 852 intel_modeset_init_hw(i915); 853 intel_init_clock_gating(i915); 854 intel_hpd_init(i915); 855 856 ret = __intel_display_resume(i915, state, ctx); 857 if (ret) 858 drm_err(&i915->drm, 859 "Restoring old state failed with %i\n", ret); 860 861 intel_hpd_poll_disable(i915); 862 } 863 864 drm_atomic_state_put(state); 865 unlock: 866 drm_modeset_drop_locks(ctx); 867 drm_modeset_acquire_fini(ctx); 868 mutex_unlock(&i915->drm.mode_config.mutex); 869 870 clear_bit_unlock(I915_RESET_MODESET, &to_gt(i915)->reset.flags); 871 } 872 873 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) 874 { 875 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 876 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 877 enum pipe pipe = crtc->pipe; 878 u32 tmp; 879 880 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe)); 881 882 /* 883 * Display WA #1153: icl 884 * enable hardware to bypass the alpha math 885 * and rounding for per-pixel values 00 and 0xff 886 */ 887 tmp |= PER_PIXEL_ALPHA_BYPASS_EN; 888 /* 889 * Display WA # 1605353570: icl 890 * Set the pixel rounding bit to 1 for allowing 891 * passthrough of Frame buffer pixels unmodified 892 * across pipe 893 */ 894 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU; 895 896 /* 897 * Underrun recovery must always be disabled on display 13+. 898 * DG2 chicken bit meaning is inverted compared to other platforms. 899 */ 900 if (IS_DG2(dev_priv)) 901 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2; 902 else if (DISPLAY_VER(dev_priv) >= 13) 903 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP; 904 905 /* Wa_14010547955:dg2 */ 906 if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER)) 907 tmp |= DG2_RENDER_CCSTAG_4_3_EN; 908 909 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp); 910 } 911 912 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) 913 { 914 struct drm_crtc *crtc; 915 bool cleanup_done; 916 917 drm_for_each_crtc(crtc, &dev_priv->drm) { 918 struct drm_crtc_commit *commit; 919 spin_lock(&crtc->commit_lock); 920 commit = list_first_entry_or_null(&crtc->commit_list, 921 struct drm_crtc_commit, commit_entry); 922 cleanup_done = commit ? 923 try_wait_for_completion(&commit->cleanup_done) : true; 924 spin_unlock(&crtc->commit_lock); 925 926 if (cleanup_done) 927 continue; 928 929 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc)); 930 931 return true; 932 } 933 934 return false; 935 } 936 937 /* 938 * Finds the encoder associated with the given CRTC. This can only be 939 * used when we know that the CRTC isn't feeding multiple encoders! 940 */ 941 struct intel_encoder * 942 intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 943 const struct intel_crtc_state *crtc_state) 944 { 945 const struct drm_connector_state *connector_state; 946 const struct drm_connector *connector; 947 struct intel_encoder *encoder = NULL; 948 struct intel_crtc *master_crtc; 949 int num_encoders = 0; 950 int i; 951 952 master_crtc = intel_master_crtc(crtc_state); 953 954 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 955 if (connector_state->crtc != &master_crtc->base) 956 continue; 957 958 encoder = to_intel_encoder(connector_state->best_encoder); 959 num_encoders++; 960 } 961 962 drm_WARN(encoder->base.dev, num_encoders != 1, 963 "%d encoders for pipe %c\n", 964 num_encoders, pipe_name(master_crtc->pipe)); 965 966 return encoder; 967 } 968 969 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state) 970 { 971 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 972 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 973 const struct drm_rect *dst = &crtc_state->pch_pfit.dst; 974 enum pipe pipe = crtc->pipe; 975 int width = drm_rect_width(dst); 976 int height = drm_rect_height(dst); 977 int x = dst->x1; 978 int y = dst->y1; 979 980 if (!crtc_state->pch_pfit.enabled) 981 return; 982 983 /* Force use of hard-coded filter coefficients 984 * as some pre-programmed values are broken, 985 * e.g. x201. 986 */ 987 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) 988 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 989 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe)); 990 else 991 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 992 PF_FILTER_MED_3x3); 993 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), x << 16 | y); 994 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), width << 16 | height); 995 } 996 997 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc) 998 { 999 if (crtc->overlay) 1000 (void) intel_overlay_switch_off(crtc->overlay); 1001 1002 /* Let userspace switch the overlay on again. In most cases userspace 1003 * has to recompute where to put it anyway. 1004 */ 1005 } 1006 1007 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state) 1008 { 1009 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1010 1011 if (!crtc_state->nv12_planes) 1012 return false; 1013 1014 /* WA Display #0827: Gen9:all */ 1015 if (DISPLAY_VER(dev_priv) == 9) 1016 return true; 1017 1018 return false; 1019 } 1020 1021 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state) 1022 { 1023 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1024 1025 /* Wa_2006604312:icl,ehl */ 1026 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11) 1027 return true; 1028 1029 return false; 1030 } 1031 1032 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state) 1033 { 1034 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1035 1036 /* Wa_1604331009:icl,jsl,ehl */ 1037 if (is_hdr_mode(crtc_state) && 1038 crtc_state->active_planes & BIT(PLANE_CURSOR) && 1039 DISPLAY_VER(dev_priv) == 11) 1040 return true; 1041 1042 return false; 1043 } 1044 1045 static void intel_async_flip_vtd_wa(struct drm_i915_private *i915, 1046 enum pipe pipe, bool enable) 1047 { 1048 if (DISPLAY_VER(i915) == 9) { 1049 /* 1050 * "Plane N strech max must be programmed to 11b (x1) 1051 * when Async flips are enabled on that plane." 1052 */ 1053 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 1054 SKL_PLANE1_STRETCH_MAX_MASK, 1055 enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8); 1056 } else { 1057 /* Also needed on HSW/BDW albeit undocumented */ 1058 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 1059 HSW_PRI_STRETCH_MAX_MASK, 1060 enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8); 1061 } 1062 } 1063 1064 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state) 1065 { 1066 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1067 1068 return crtc_state->uapi.async_flip && i915_vtd_active(i915) && 1069 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915)); 1070 } 1071 1072 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state, 1073 const struct intel_crtc_state *new_crtc_state) 1074 { 1075 return (!old_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)) && 1076 new_crtc_state->active_planes; 1077 } 1078 1079 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state, 1080 const struct intel_crtc_state *new_crtc_state) 1081 { 1082 return old_crtc_state->active_planes && 1083 (!new_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)); 1084 } 1085 1086 static void intel_post_plane_update(struct intel_atomic_state *state, 1087 struct intel_crtc *crtc) 1088 { 1089 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1090 const struct intel_crtc_state *old_crtc_state = 1091 intel_atomic_get_old_crtc_state(state, crtc); 1092 const struct intel_crtc_state *new_crtc_state = 1093 intel_atomic_get_new_crtc_state(state, crtc); 1094 enum pipe pipe = crtc->pipe; 1095 1096 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); 1097 1098 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) 1099 intel_update_watermarks(dev_priv); 1100 1101 intel_fbc_post_update(state, crtc); 1102 1103 if (needs_async_flip_vtd_wa(old_crtc_state) && 1104 !needs_async_flip_vtd_wa(new_crtc_state)) 1105 intel_async_flip_vtd_wa(dev_priv, pipe, false); 1106 1107 if (needs_nv12_wa(old_crtc_state) && 1108 !needs_nv12_wa(new_crtc_state)) 1109 skl_wa_827(dev_priv, pipe, false); 1110 1111 if (needs_scalerclk_wa(old_crtc_state) && 1112 !needs_scalerclk_wa(new_crtc_state)) 1113 icl_wa_scalerclkgating(dev_priv, pipe, false); 1114 1115 if (needs_cursorclk_wa(old_crtc_state) && 1116 !needs_cursorclk_wa(new_crtc_state)) 1117 icl_wa_cursorclkgating(dev_priv, pipe, false); 1118 } 1119 1120 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state, 1121 struct intel_crtc *crtc) 1122 { 1123 const struct intel_crtc_state *crtc_state = 1124 intel_atomic_get_new_crtc_state(state, crtc); 1125 u8 update_planes = crtc_state->update_planes; 1126 const struct intel_plane_state *plane_state; 1127 struct intel_plane *plane; 1128 int i; 1129 1130 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1131 if (plane->pipe == crtc->pipe && 1132 update_planes & BIT(plane->id)) 1133 plane->enable_flip_done(plane); 1134 } 1135 } 1136 1137 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state, 1138 struct intel_crtc *crtc) 1139 { 1140 const struct intel_crtc_state *crtc_state = 1141 intel_atomic_get_new_crtc_state(state, crtc); 1142 u8 update_planes = crtc_state->update_planes; 1143 const struct intel_plane_state *plane_state; 1144 struct intel_plane *plane; 1145 int i; 1146 1147 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1148 if (plane->pipe == crtc->pipe && 1149 update_planes & BIT(plane->id)) 1150 plane->disable_flip_done(plane); 1151 } 1152 } 1153 1154 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state, 1155 struct intel_crtc *crtc) 1156 { 1157 const struct intel_crtc_state *old_crtc_state = 1158 intel_atomic_get_old_crtc_state(state, crtc); 1159 const struct intel_crtc_state *new_crtc_state = 1160 intel_atomic_get_new_crtc_state(state, crtc); 1161 u8 disable_async_flip_planes = old_crtc_state->async_flip_planes & 1162 ~new_crtc_state->async_flip_planes; 1163 const struct intel_plane_state *old_plane_state; 1164 struct intel_plane *plane; 1165 bool need_vbl_wait = false; 1166 int i; 1167 1168 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1169 if (plane->need_async_flip_disable_wa && 1170 plane->pipe == crtc->pipe && 1171 disable_async_flip_planes & BIT(plane->id)) { 1172 /* 1173 * Apart from the async flip bit we want to 1174 * preserve the old state for the plane. 1175 */ 1176 plane->async_flip(plane, old_crtc_state, 1177 old_plane_state, false); 1178 need_vbl_wait = true; 1179 } 1180 } 1181 1182 if (need_vbl_wait) 1183 intel_crtc_wait_for_next_vblank(crtc); 1184 } 1185 1186 static void intel_pre_plane_update(struct intel_atomic_state *state, 1187 struct intel_crtc *crtc) 1188 { 1189 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1190 const struct intel_crtc_state *old_crtc_state = 1191 intel_atomic_get_old_crtc_state(state, crtc); 1192 const struct intel_crtc_state *new_crtc_state = 1193 intel_atomic_get_new_crtc_state(state, crtc); 1194 enum pipe pipe = crtc->pipe; 1195 1196 intel_drrs_deactivate(old_crtc_state); 1197 1198 intel_psr_pre_plane_update(state, crtc); 1199 1200 if (hsw_ips_pre_update(state, crtc)) 1201 intel_crtc_wait_for_next_vblank(crtc); 1202 1203 if (intel_fbc_pre_update(state, crtc)) 1204 intel_crtc_wait_for_next_vblank(crtc); 1205 1206 if (!needs_async_flip_vtd_wa(old_crtc_state) && 1207 needs_async_flip_vtd_wa(new_crtc_state)) 1208 intel_async_flip_vtd_wa(dev_priv, pipe, true); 1209 1210 /* Display WA 827 */ 1211 if (!needs_nv12_wa(old_crtc_state) && 1212 needs_nv12_wa(new_crtc_state)) 1213 skl_wa_827(dev_priv, pipe, true); 1214 1215 /* Wa_2006604312:icl,ehl */ 1216 if (!needs_scalerclk_wa(old_crtc_state) && 1217 needs_scalerclk_wa(new_crtc_state)) 1218 icl_wa_scalerclkgating(dev_priv, pipe, true); 1219 1220 /* Wa_1604331009:icl,jsl,ehl */ 1221 if (!needs_cursorclk_wa(old_crtc_state) && 1222 needs_cursorclk_wa(new_crtc_state)) 1223 icl_wa_cursorclkgating(dev_priv, pipe, true); 1224 1225 /* 1226 * Vblank time updates from the shadow to live plane control register 1227 * are blocked if the memory self-refresh mode is active at that 1228 * moment. So to make sure the plane gets truly disabled, disable 1229 * first the self-refresh mode. The self-refresh enable bit in turn 1230 * will be checked/applied by the HW only at the next frame start 1231 * event which is after the vblank start event, so we need to have a 1232 * wait-for-vblank between disabling the plane and the pipe. 1233 */ 1234 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active && 1235 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) 1236 intel_crtc_wait_for_next_vblank(crtc); 1237 1238 /* 1239 * IVB workaround: must disable low power watermarks for at least 1240 * one frame before enabling scaling. LP watermarks can be re-enabled 1241 * when scaling is disabled. 1242 * 1243 * WaCxSRDisabledForSpriteScaling:ivb 1244 */ 1245 if (old_crtc_state->hw.active && 1246 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv)) 1247 intel_crtc_wait_for_next_vblank(crtc); 1248 1249 /* 1250 * If we're doing a modeset we don't need to do any 1251 * pre-vblank watermark programming here. 1252 */ 1253 if (!intel_crtc_needs_modeset(new_crtc_state)) { 1254 /* 1255 * For platforms that support atomic watermarks, program the 1256 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these 1257 * will be the intermediate values that are safe for both pre- and 1258 * post- vblank; when vblank happens, the 'active' values will be set 1259 * to the final 'target' values and we'll do this again to get the 1260 * optimal watermarks. For gen9+ platforms, the values we program here 1261 * will be the final target values which will get automatically latched 1262 * at vblank time; no further programming will be necessary. 1263 * 1264 * If a platform hasn't been transitioned to atomic watermarks yet, 1265 * we'll continue to update watermarks the old way, if flags tell 1266 * us to. 1267 */ 1268 if (!intel_initial_watermarks(state, crtc)) 1269 if (new_crtc_state->update_wm_pre) 1270 intel_update_watermarks(dev_priv); 1271 } 1272 1273 /* 1274 * Gen2 reports pipe underruns whenever all planes are disabled. 1275 * So disable underrun reporting before all the planes get disabled. 1276 * 1277 * We do this after .initial_watermarks() so that we have a 1278 * chance of catching underruns with the intermediate watermarks 1279 * vs. the old plane configuration. 1280 */ 1281 if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state)) 1282 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1283 1284 /* 1285 * WA for platforms where async address update enable bit 1286 * is double buffered and only latched at start of vblank. 1287 */ 1288 if (old_crtc_state->async_flip_planes & ~new_crtc_state->async_flip_planes) 1289 intel_crtc_async_flip_disable_wa(state, crtc); 1290 } 1291 1292 static void intel_crtc_disable_planes(struct intel_atomic_state *state, 1293 struct intel_crtc *crtc) 1294 { 1295 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1296 const struct intel_crtc_state *new_crtc_state = 1297 intel_atomic_get_new_crtc_state(state, crtc); 1298 unsigned int update_mask = new_crtc_state->update_planes; 1299 const struct intel_plane_state *old_plane_state; 1300 struct intel_plane *plane; 1301 unsigned fb_bits = 0; 1302 int i; 1303 1304 intel_crtc_dpms_overlay_disable(crtc); 1305 1306 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1307 if (crtc->pipe != plane->pipe || 1308 !(update_mask & BIT(plane->id))) 1309 continue; 1310 1311 intel_plane_disable_arm(plane, new_crtc_state); 1312 1313 if (old_plane_state->uapi.visible) 1314 fb_bits |= plane->frontbuffer_bit; 1315 } 1316 1317 intel_frontbuffer_flip(dev_priv, fb_bits); 1318 } 1319 1320 /* 1321 * intel_connector_primary_encoder - get the primary encoder for a connector 1322 * @connector: connector for which to return the encoder 1323 * 1324 * Returns the primary encoder for a connector. There is a 1:1 mapping from 1325 * all connectors to their encoder, except for DP-MST connectors which have 1326 * both a virtual and a primary encoder. These DP-MST primary encoders can be 1327 * pointed to by as many DP-MST connectors as there are pipes. 1328 */ 1329 static struct intel_encoder * 1330 intel_connector_primary_encoder(struct intel_connector *connector) 1331 { 1332 struct intel_encoder *encoder; 1333 1334 if (connector->mst_port) 1335 return &dp_to_dig_port(connector->mst_port)->base; 1336 1337 encoder = intel_attached_encoder(connector); 1338 drm_WARN_ON(connector->base.dev, !encoder); 1339 1340 return encoder; 1341 } 1342 1343 static void intel_encoders_update_prepare(struct intel_atomic_state *state) 1344 { 1345 struct drm_i915_private *i915 = to_i915(state->base.dev); 1346 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 1347 struct intel_crtc *crtc; 1348 struct drm_connector_state *new_conn_state; 1349 struct drm_connector *connector; 1350 int i; 1351 1352 /* 1353 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits. 1354 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook. 1355 */ 1356 if (i915->display.dpll.mgr) { 1357 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1358 if (intel_crtc_needs_modeset(new_crtc_state)) 1359 continue; 1360 1361 new_crtc_state->shared_dpll = old_crtc_state->shared_dpll; 1362 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state; 1363 } 1364 } 1365 1366 if (!state->modeset) 1367 return; 1368 1369 for_each_new_connector_in_state(&state->base, connector, new_conn_state, 1370 i) { 1371 struct intel_connector *intel_connector; 1372 struct intel_encoder *encoder; 1373 struct intel_crtc *crtc; 1374 1375 if (!intel_connector_needs_modeset(state, connector)) 1376 continue; 1377 1378 intel_connector = to_intel_connector(connector); 1379 encoder = intel_connector_primary_encoder(intel_connector); 1380 if (!encoder->update_prepare) 1381 continue; 1382 1383 crtc = new_conn_state->crtc ? 1384 to_intel_crtc(new_conn_state->crtc) : NULL; 1385 encoder->update_prepare(state, encoder, crtc); 1386 } 1387 } 1388 1389 static void intel_encoders_update_complete(struct intel_atomic_state *state) 1390 { 1391 struct drm_connector_state *new_conn_state; 1392 struct drm_connector *connector; 1393 int i; 1394 1395 if (!state->modeset) 1396 return; 1397 1398 for_each_new_connector_in_state(&state->base, connector, new_conn_state, 1399 i) { 1400 struct intel_connector *intel_connector; 1401 struct intel_encoder *encoder; 1402 struct intel_crtc *crtc; 1403 1404 if (!intel_connector_needs_modeset(state, connector)) 1405 continue; 1406 1407 intel_connector = to_intel_connector(connector); 1408 encoder = intel_connector_primary_encoder(intel_connector); 1409 if (!encoder->update_complete) 1410 continue; 1411 1412 crtc = new_conn_state->crtc ? 1413 to_intel_crtc(new_conn_state->crtc) : NULL; 1414 encoder->update_complete(state, encoder, crtc); 1415 } 1416 } 1417 1418 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state, 1419 struct intel_crtc *crtc) 1420 { 1421 const struct intel_crtc_state *crtc_state = 1422 intel_atomic_get_new_crtc_state(state, crtc); 1423 const struct drm_connector_state *conn_state; 1424 struct drm_connector *conn; 1425 int i; 1426 1427 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1428 struct intel_encoder *encoder = 1429 to_intel_encoder(conn_state->best_encoder); 1430 1431 if (conn_state->crtc != &crtc->base) 1432 continue; 1433 1434 if (encoder->pre_pll_enable) 1435 encoder->pre_pll_enable(state, encoder, 1436 crtc_state, conn_state); 1437 } 1438 } 1439 1440 static void intel_encoders_pre_enable(struct intel_atomic_state *state, 1441 struct intel_crtc *crtc) 1442 { 1443 const struct intel_crtc_state *crtc_state = 1444 intel_atomic_get_new_crtc_state(state, crtc); 1445 const struct drm_connector_state *conn_state; 1446 struct drm_connector *conn; 1447 int i; 1448 1449 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1450 struct intel_encoder *encoder = 1451 to_intel_encoder(conn_state->best_encoder); 1452 1453 if (conn_state->crtc != &crtc->base) 1454 continue; 1455 1456 if (encoder->pre_enable) 1457 encoder->pre_enable(state, encoder, 1458 crtc_state, conn_state); 1459 } 1460 } 1461 1462 static void intel_encoders_enable(struct intel_atomic_state *state, 1463 struct intel_crtc *crtc) 1464 { 1465 const struct intel_crtc_state *crtc_state = 1466 intel_atomic_get_new_crtc_state(state, crtc); 1467 const struct drm_connector_state *conn_state; 1468 struct drm_connector *conn; 1469 int i; 1470 1471 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1472 struct intel_encoder *encoder = 1473 to_intel_encoder(conn_state->best_encoder); 1474 1475 if (conn_state->crtc != &crtc->base) 1476 continue; 1477 1478 if (encoder->enable) 1479 encoder->enable(state, encoder, 1480 crtc_state, conn_state); 1481 intel_opregion_notify_encoder(encoder, true); 1482 } 1483 } 1484 1485 static void intel_encoders_disable(struct intel_atomic_state *state, 1486 struct intel_crtc *crtc) 1487 { 1488 const struct intel_crtc_state *old_crtc_state = 1489 intel_atomic_get_old_crtc_state(state, crtc); 1490 const struct drm_connector_state *old_conn_state; 1491 struct drm_connector *conn; 1492 int i; 1493 1494 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1495 struct intel_encoder *encoder = 1496 to_intel_encoder(old_conn_state->best_encoder); 1497 1498 if (old_conn_state->crtc != &crtc->base) 1499 continue; 1500 1501 intel_opregion_notify_encoder(encoder, false); 1502 if (encoder->disable) 1503 encoder->disable(state, encoder, 1504 old_crtc_state, old_conn_state); 1505 } 1506 } 1507 1508 static void intel_encoders_post_disable(struct intel_atomic_state *state, 1509 struct intel_crtc *crtc) 1510 { 1511 const struct intel_crtc_state *old_crtc_state = 1512 intel_atomic_get_old_crtc_state(state, crtc); 1513 const struct drm_connector_state *old_conn_state; 1514 struct drm_connector *conn; 1515 int i; 1516 1517 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1518 struct intel_encoder *encoder = 1519 to_intel_encoder(old_conn_state->best_encoder); 1520 1521 if (old_conn_state->crtc != &crtc->base) 1522 continue; 1523 1524 if (encoder->post_disable) 1525 encoder->post_disable(state, encoder, 1526 old_crtc_state, old_conn_state); 1527 } 1528 } 1529 1530 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state, 1531 struct intel_crtc *crtc) 1532 { 1533 const struct intel_crtc_state *old_crtc_state = 1534 intel_atomic_get_old_crtc_state(state, crtc); 1535 const struct drm_connector_state *old_conn_state; 1536 struct drm_connector *conn; 1537 int i; 1538 1539 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1540 struct intel_encoder *encoder = 1541 to_intel_encoder(old_conn_state->best_encoder); 1542 1543 if (old_conn_state->crtc != &crtc->base) 1544 continue; 1545 1546 if (encoder->post_pll_disable) 1547 encoder->post_pll_disable(state, encoder, 1548 old_crtc_state, old_conn_state); 1549 } 1550 } 1551 1552 static void intel_encoders_update_pipe(struct intel_atomic_state *state, 1553 struct intel_crtc *crtc) 1554 { 1555 const struct intel_crtc_state *crtc_state = 1556 intel_atomic_get_new_crtc_state(state, crtc); 1557 const struct drm_connector_state *conn_state; 1558 struct drm_connector *conn; 1559 int i; 1560 1561 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1562 struct intel_encoder *encoder = 1563 to_intel_encoder(conn_state->best_encoder); 1564 1565 if (conn_state->crtc != &crtc->base) 1566 continue; 1567 1568 if (encoder->update_pipe) 1569 encoder->update_pipe(state, encoder, 1570 crtc_state, conn_state); 1571 } 1572 } 1573 1574 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state) 1575 { 1576 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1577 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 1578 1579 plane->disable_arm(plane, crtc_state); 1580 } 1581 1582 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1583 { 1584 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1585 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1586 1587 if (crtc_state->has_pch_encoder) { 1588 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1589 &crtc_state->fdi_m_n); 1590 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1591 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1592 &crtc_state->dp_m_n); 1593 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1594 &crtc_state->dp_m2_n2); 1595 } 1596 1597 intel_set_transcoder_timings(crtc_state); 1598 1599 ilk_set_pipeconf(crtc_state); 1600 } 1601 1602 static void ilk_crtc_enable(struct intel_atomic_state *state, 1603 struct intel_crtc *crtc) 1604 { 1605 const struct intel_crtc_state *new_crtc_state = 1606 intel_atomic_get_new_crtc_state(state, crtc); 1607 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1608 enum pipe pipe = crtc->pipe; 1609 1610 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1611 return; 1612 1613 /* 1614 * Sometimes spurious CPU pipe underruns happen during FDI 1615 * training, at least with VGA+HDMI cloning. Suppress them. 1616 * 1617 * On ILK we get an occasional spurious CPU pipe underruns 1618 * between eDP port A enable and vdd enable. Also PCH port 1619 * enable seems to result in the occasional CPU pipe underrun. 1620 * 1621 * Spurious PCH underruns also occur during PCH enabling. 1622 */ 1623 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1624 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 1625 1626 ilk_configure_cpu_transcoder(new_crtc_state); 1627 1628 intel_set_pipe_src_size(new_crtc_state); 1629 1630 crtc->active = true; 1631 1632 intel_encoders_pre_enable(state, crtc); 1633 1634 if (new_crtc_state->has_pch_encoder) { 1635 ilk_pch_pre_enable(state, crtc); 1636 } else { 1637 assert_fdi_tx_disabled(dev_priv, pipe); 1638 assert_fdi_rx_disabled(dev_priv, pipe); 1639 } 1640 1641 ilk_pfit_enable(new_crtc_state); 1642 1643 /* 1644 * On ILK+ LUT must be loaded before the pipe is running but with 1645 * clocks enabled 1646 */ 1647 intel_color_load_luts(new_crtc_state); 1648 intel_color_commit_noarm(new_crtc_state); 1649 intel_color_commit_arm(new_crtc_state); 1650 /* update DSPCNTR to configure gamma for pipe bottom color */ 1651 intel_disable_primary_plane(new_crtc_state); 1652 1653 intel_initial_watermarks(state, crtc); 1654 intel_enable_transcoder(new_crtc_state); 1655 1656 if (new_crtc_state->has_pch_encoder) 1657 ilk_pch_enable(state, crtc); 1658 1659 intel_crtc_vblank_on(new_crtc_state); 1660 1661 intel_encoders_enable(state, crtc); 1662 1663 if (HAS_PCH_CPT(dev_priv)) 1664 intel_wait_for_pipe_scanline_moving(crtc); 1665 1666 /* 1667 * Must wait for vblank to avoid spurious PCH FIFO underruns. 1668 * And a second vblank wait is needed at least on ILK with 1669 * some interlaced HDMI modes. Let's do the double wait always 1670 * in case there are more corner cases we don't know about. 1671 */ 1672 if (new_crtc_state->has_pch_encoder) { 1673 intel_crtc_wait_for_next_vblank(crtc); 1674 intel_crtc_wait_for_next_vblank(crtc); 1675 } 1676 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1677 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 1678 } 1679 1680 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, 1681 enum pipe pipe, bool apply) 1682 { 1683 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)); 1684 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS; 1685 1686 if (apply) 1687 val |= mask; 1688 else 1689 val &= ~mask; 1690 1691 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val); 1692 } 1693 1694 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state) 1695 { 1696 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1697 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1698 1699 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe), 1700 HSW_LINETIME(crtc_state->linetime) | 1701 HSW_IPS_LINETIME(crtc_state->ips_linetime)); 1702 } 1703 1704 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) 1705 { 1706 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1707 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1708 enum transcoder transcoder = crtc_state->cpu_transcoder; 1709 i915_reg_t reg = DISPLAY_VER(dev_priv) >= 14 ? MTL_CHICKEN_TRANS(transcoder) : 1710 CHICKEN_TRANS(transcoder); 1711 1712 intel_de_rmw(dev_priv, reg, 1713 HSW_FRAME_START_DELAY_MASK, 1714 HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1)); 1715 } 1716 1717 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state, 1718 const struct intel_crtc_state *crtc_state) 1719 { 1720 struct intel_crtc *master_crtc = intel_master_crtc(crtc_state); 1721 1722 /* 1723 * Enable sequence steps 1-7 on bigjoiner master 1724 */ 1725 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1726 intel_encoders_pre_pll_enable(state, master_crtc); 1727 1728 if (crtc_state->shared_dpll) 1729 intel_enable_shared_dpll(crtc_state); 1730 1731 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1732 intel_encoders_pre_enable(state, master_crtc); 1733 } 1734 1735 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1736 { 1737 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1738 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1739 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1740 1741 if (crtc_state->has_pch_encoder) { 1742 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1743 &crtc_state->fdi_m_n); 1744 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1745 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1746 &crtc_state->dp_m_n); 1747 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1748 &crtc_state->dp_m2_n2); 1749 } 1750 1751 intel_set_transcoder_timings(crtc_state); 1752 1753 if (cpu_transcoder != TRANSCODER_EDP) 1754 intel_de_write(dev_priv, TRANS_MULT(cpu_transcoder), 1755 crtc_state->pixel_multiplier - 1); 1756 1757 hsw_set_frame_start_delay(crtc_state); 1758 1759 hsw_set_transconf(crtc_state); 1760 } 1761 1762 static void hsw_crtc_enable(struct intel_atomic_state *state, 1763 struct intel_crtc *crtc) 1764 { 1765 const struct intel_crtc_state *new_crtc_state = 1766 intel_atomic_get_new_crtc_state(state, crtc); 1767 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1768 enum pipe pipe = crtc->pipe, hsw_workaround_pipe; 1769 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 1770 bool psl_clkgate_wa; 1771 1772 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1773 return; 1774 1775 intel_dmc_enable_pipe(dev_priv, crtc->pipe); 1776 1777 if (!new_crtc_state->bigjoiner_pipes) { 1778 intel_encoders_pre_pll_enable(state, crtc); 1779 1780 if (new_crtc_state->shared_dpll) 1781 intel_enable_shared_dpll(new_crtc_state); 1782 1783 intel_encoders_pre_enable(state, crtc); 1784 } else { 1785 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state); 1786 } 1787 1788 intel_dsc_enable(new_crtc_state); 1789 1790 if (DISPLAY_VER(dev_priv) >= 13) 1791 intel_uncompressed_joiner_enable(new_crtc_state); 1792 1793 intel_set_pipe_src_size(new_crtc_state); 1794 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 1795 bdw_set_pipe_misc(new_crtc_state); 1796 1797 if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) && 1798 !transcoder_is_dsi(cpu_transcoder)) 1799 hsw_configure_cpu_transcoder(new_crtc_state); 1800 1801 crtc->active = true; 1802 1803 /* Display WA #1180: WaDisableScalarClockGating: glk */ 1804 psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 && 1805 new_crtc_state->pch_pfit.enabled; 1806 if (psl_clkgate_wa) 1807 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true); 1808 1809 if (DISPLAY_VER(dev_priv) >= 9) 1810 skl_pfit_enable(new_crtc_state); 1811 else 1812 ilk_pfit_enable(new_crtc_state); 1813 1814 /* 1815 * On ILK+ LUT must be loaded before the pipe is running but with 1816 * clocks enabled 1817 */ 1818 intel_color_load_luts(new_crtc_state); 1819 intel_color_commit_noarm(new_crtc_state); 1820 intel_color_commit_arm(new_crtc_state); 1821 /* update DSPCNTR to configure gamma/csc for pipe bottom color */ 1822 if (DISPLAY_VER(dev_priv) < 9) 1823 intel_disable_primary_plane(new_crtc_state); 1824 1825 hsw_set_linetime_wm(new_crtc_state); 1826 1827 if (DISPLAY_VER(dev_priv) >= 11) 1828 icl_set_pipe_chicken(new_crtc_state); 1829 1830 intel_initial_watermarks(state, crtc); 1831 1832 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 1833 intel_crtc_vblank_on(new_crtc_state); 1834 1835 intel_encoders_enable(state, crtc); 1836 1837 if (psl_clkgate_wa) { 1838 intel_crtc_wait_for_next_vblank(crtc); 1839 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false); 1840 } 1841 1842 /* If we change the relative order between pipe/planes enabling, we need 1843 * to change the workaround. */ 1844 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe; 1845 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { 1846 struct intel_crtc *wa_crtc; 1847 1848 wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe); 1849 1850 intel_crtc_wait_for_next_vblank(wa_crtc); 1851 intel_crtc_wait_for_next_vblank(wa_crtc); 1852 } 1853 } 1854 1855 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state) 1856 { 1857 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1858 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1859 enum pipe pipe = crtc->pipe; 1860 1861 /* To avoid upsetting the power well on haswell only disable the pfit if 1862 * it's in use. The hw state code will make sure we get this right. */ 1863 if (!old_crtc_state->pch_pfit.enabled) 1864 return; 1865 1866 intel_de_write_fw(dev_priv, PF_CTL(pipe), 0); 1867 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0); 1868 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0); 1869 } 1870 1871 static void ilk_crtc_disable(struct intel_atomic_state *state, 1872 struct intel_crtc *crtc) 1873 { 1874 const struct intel_crtc_state *old_crtc_state = 1875 intel_atomic_get_old_crtc_state(state, crtc); 1876 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1877 enum pipe pipe = crtc->pipe; 1878 1879 /* 1880 * Sometimes spurious CPU pipe underruns happen when the 1881 * pipe is already disabled, but FDI RX/TX is still enabled. 1882 * Happens at least with VGA+HDMI cloning. Suppress them. 1883 */ 1884 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1885 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 1886 1887 intel_encoders_disable(state, crtc); 1888 1889 intel_crtc_vblank_off(old_crtc_state); 1890 1891 intel_disable_transcoder(old_crtc_state); 1892 1893 ilk_pfit_disable(old_crtc_state); 1894 1895 if (old_crtc_state->has_pch_encoder) 1896 ilk_pch_disable(state, crtc); 1897 1898 intel_encoders_post_disable(state, crtc); 1899 1900 if (old_crtc_state->has_pch_encoder) 1901 ilk_pch_post_disable(state, crtc); 1902 1903 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1904 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 1905 } 1906 1907 static void hsw_crtc_disable(struct intel_atomic_state *state, 1908 struct intel_crtc *crtc) 1909 { 1910 const struct intel_crtc_state *old_crtc_state = 1911 intel_atomic_get_old_crtc_state(state, crtc); 1912 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 1913 1914 /* 1915 * FIXME collapse everything to one hook. 1916 * Need care with mst->ddi interactions. 1917 */ 1918 if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) { 1919 intel_encoders_disable(state, crtc); 1920 intel_encoders_post_disable(state, crtc); 1921 } 1922 1923 intel_dmc_disable_pipe(i915, crtc->pipe); 1924 } 1925 1926 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) 1927 { 1928 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1929 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1930 1931 if (!crtc_state->gmch_pfit.control) 1932 return; 1933 1934 /* 1935 * The panel fitter should only be adjusted whilst the pipe is disabled, 1936 * according to register description and PRM. 1937 */ 1938 drm_WARN_ON(&dev_priv->drm, 1939 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE); 1940 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 1941 1942 intel_de_write(dev_priv, PFIT_PGM_RATIOS, 1943 crtc_state->gmch_pfit.pgm_ratios); 1944 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control); 1945 1946 /* Border color in case we don't scale up to the full screen. Black by 1947 * default, change to something else for debugging. */ 1948 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); 1949 } 1950 1951 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) 1952 { 1953 if (phy == PHY_NONE) 1954 return false; 1955 else if (IS_ALDERLAKE_S(dev_priv)) 1956 return phy <= PHY_E; 1957 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) 1958 return phy <= PHY_D; 1959 else if (IS_JSL_EHL(dev_priv)) 1960 return phy <= PHY_C; 1961 else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12)) 1962 return phy <= PHY_B; 1963 else 1964 /* 1965 * DG2 outputs labelled as "combo PHY" in the bspec use 1966 * SNPS PHYs with completely different programming, 1967 * hence we always return false here. 1968 */ 1969 return false; 1970 } 1971 1972 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) 1973 { 1974 if (IS_DG2(dev_priv)) 1975 /* DG2's "TC1" output uses a SNPS PHY */ 1976 return false; 1977 else if (IS_ALDERLAKE_P(dev_priv)) 1978 return phy >= PHY_F && phy <= PHY_I; 1979 else if (IS_TIGERLAKE(dev_priv)) 1980 return phy >= PHY_D && phy <= PHY_I; 1981 else if (IS_ICELAKE(dev_priv)) 1982 return phy >= PHY_C && phy <= PHY_F; 1983 else 1984 return false; 1985 } 1986 1987 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy) 1988 { 1989 if (phy == PHY_NONE) 1990 return false; 1991 else if (IS_DG2(dev_priv)) 1992 /* 1993 * All four "combo" ports and the TC1 port (PHY E) use 1994 * Synopsis PHYs. 1995 */ 1996 return phy <= PHY_E; 1997 1998 return false; 1999 } 2000 2001 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) 2002 { 2003 if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD) 2004 return PHY_D + port - PORT_D_XELPD; 2005 else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1) 2006 return PHY_F + port - PORT_TC1; 2007 else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1) 2008 return PHY_B + port - PORT_TC1; 2009 else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1) 2010 return PHY_C + port - PORT_TC1; 2011 else if (IS_JSL_EHL(i915) && port == PORT_D) 2012 return PHY_A; 2013 2014 return PHY_A + port - PORT_A; 2015 } 2016 2017 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) 2018 { 2019 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port))) 2020 return TC_PORT_NONE; 2021 2022 if (DISPLAY_VER(dev_priv) >= 12) 2023 return TC_PORT_1 + port - PORT_TC1; 2024 else 2025 return TC_PORT_1 + port - PORT_C; 2026 } 2027 2028 enum intel_display_power_domain 2029 intel_aux_power_domain(struct intel_digital_port *dig_port) 2030 { 2031 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 2032 2033 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 2034 return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch); 2035 2036 return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch); 2037 } 2038 2039 static void get_crtc_power_domains(struct intel_crtc_state *crtc_state, 2040 struct intel_power_domain_mask *mask) 2041 { 2042 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2043 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2044 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2045 struct drm_encoder *encoder; 2046 enum pipe pipe = crtc->pipe; 2047 2048 bitmap_zero(mask->bits, POWER_DOMAIN_NUM); 2049 2050 if (!crtc_state->hw.active) 2051 return; 2052 2053 set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits); 2054 set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits); 2055 if (crtc_state->pch_pfit.enabled || 2056 crtc_state->pch_pfit.force_thru) 2057 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits); 2058 2059 drm_for_each_encoder_mask(encoder, &dev_priv->drm, 2060 crtc_state->uapi.encoder_mask) { 2061 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2062 2063 set_bit(intel_encoder->power_domain, mask->bits); 2064 } 2065 2066 if (HAS_DDI(dev_priv) && crtc_state->has_audio) 2067 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits); 2068 2069 if (crtc_state->shared_dpll) 2070 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits); 2071 2072 if (crtc_state->dsc.compression_enable) 2073 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits); 2074 } 2075 2076 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, 2077 struct intel_power_domain_mask *old_domains) 2078 { 2079 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2080 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2081 enum intel_display_power_domain domain; 2082 struct intel_power_domain_mask domains, new_domains; 2083 2084 get_crtc_power_domains(crtc_state, &domains); 2085 2086 bitmap_andnot(new_domains.bits, 2087 domains.bits, 2088 crtc->enabled_power_domains.mask.bits, 2089 POWER_DOMAIN_NUM); 2090 bitmap_andnot(old_domains->bits, 2091 crtc->enabled_power_domains.mask.bits, 2092 domains.bits, 2093 POWER_DOMAIN_NUM); 2094 2095 for_each_power_domain(domain, &new_domains) 2096 intel_display_power_get_in_set(dev_priv, 2097 &crtc->enabled_power_domains, 2098 domain); 2099 } 2100 2101 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc, 2102 struct intel_power_domain_mask *domains) 2103 { 2104 intel_display_power_put_mask_in_set(to_i915(crtc->base.dev), 2105 &crtc->enabled_power_domains, 2106 domains); 2107 } 2108 2109 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 2110 { 2111 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2112 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2113 2114 if (intel_crtc_has_dp_encoder(crtc_state)) { 2115 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 2116 &crtc_state->dp_m_n); 2117 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 2118 &crtc_state->dp_m2_n2); 2119 } 2120 2121 intel_set_transcoder_timings(crtc_state); 2122 2123 i9xx_set_pipeconf(crtc_state); 2124 } 2125 2126 static void valleyview_crtc_enable(struct intel_atomic_state *state, 2127 struct intel_crtc *crtc) 2128 { 2129 const struct intel_crtc_state *new_crtc_state = 2130 intel_atomic_get_new_crtc_state(state, crtc); 2131 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2132 enum pipe pipe = crtc->pipe; 2133 2134 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 2135 return; 2136 2137 i9xx_configure_cpu_transcoder(new_crtc_state); 2138 2139 intel_set_pipe_src_size(new_crtc_state); 2140 2141 intel_de_write(dev_priv, VLV_PIPE_MSA_MISC(pipe), 0); 2142 2143 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 2144 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY); 2145 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0); 2146 } 2147 2148 crtc->active = true; 2149 2150 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2151 2152 intel_encoders_pre_pll_enable(state, crtc); 2153 2154 if (IS_CHERRYVIEW(dev_priv)) 2155 chv_enable_pll(new_crtc_state); 2156 else 2157 vlv_enable_pll(new_crtc_state); 2158 2159 intel_encoders_pre_enable(state, crtc); 2160 2161 i9xx_pfit_enable(new_crtc_state); 2162 2163 intel_color_load_luts(new_crtc_state); 2164 intel_color_commit_noarm(new_crtc_state); 2165 intel_color_commit_arm(new_crtc_state); 2166 /* update DSPCNTR to configure gamma for pipe bottom color */ 2167 intel_disable_primary_plane(new_crtc_state); 2168 2169 intel_initial_watermarks(state, crtc); 2170 intel_enable_transcoder(new_crtc_state); 2171 2172 intel_crtc_vblank_on(new_crtc_state); 2173 2174 intel_encoders_enable(state, crtc); 2175 } 2176 2177 static void i9xx_crtc_enable(struct intel_atomic_state *state, 2178 struct intel_crtc *crtc) 2179 { 2180 const struct intel_crtc_state *new_crtc_state = 2181 intel_atomic_get_new_crtc_state(state, crtc); 2182 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2183 enum pipe pipe = crtc->pipe; 2184 2185 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 2186 return; 2187 2188 i9xx_configure_cpu_transcoder(new_crtc_state); 2189 2190 intel_set_pipe_src_size(new_crtc_state); 2191 2192 crtc->active = true; 2193 2194 if (DISPLAY_VER(dev_priv) != 2) 2195 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2196 2197 intel_encoders_pre_enable(state, crtc); 2198 2199 i9xx_enable_pll(new_crtc_state); 2200 2201 i9xx_pfit_enable(new_crtc_state); 2202 2203 intel_color_load_luts(new_crtc_state); 2204 intel_color_commit_noarm(new_crtc_state); 2205 intel_color_commit_arm(new_crtc_state); 2206 /* update DSPCNTR to configure gamma for pipe bottom color */ 2207 intel_disable_primary_plane(new_crtc_state); 2208 2209 if (!intel_initial_watermarks(state, crtc)) 2210 intel_update_watermarks(dev_priv); 2211 intel_enable_transcoder(new_crtc_state); 2212 2213 intel_crtc_vblank_on(new_crtc_state); 2214 2215 intel_encoders_enable(state, crtc); 2216 2217 /* prevents spurious underruns */ 2218 if (DISPLAY_VER(dev_priv) == 2) 2219 intel_crtc_wait_for_next_vblank(crtc); 2220 } 2221 2222 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) 2223 { 2224 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 2225 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2226 2227 if (!old_crtc_state->gmch_pfit.control) 2228 return; 2229 2230 assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder); 2231 2232 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n", 2233 intel_de_read(dev_priv, PFIT_CONTROL)); 2234 intel_de_write(dev_priv, PFIT_CONTROL, 0); 2235 } 2236 2237 static void i9xx_crtc_disable(struct intel_atomic_state *state, 2238 struct intel_crtc *crtc) 2239 { 2240 struct intel_crtc_state *old_crtc_state = 2241 intel_atomic_get_old_crtc_state(state, crtc); 2242 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2243 enum pipe pipe = crtc->pipe; 2244 2245 /* 2246 * On gen2 planes are double buffered but the pipe isn't, so we must 2247 * wait for planes to fully turn off before disabling the pipe. 2248 */ 2249 if (DISPLAY_VER(dev_priv) == 2) 2250 intel_crtc_wait_for_next_vblank(crtc); 2251 2252 intel_encoders_disable(state, crtc); 2253 2254 intel_crtc_vblank_off(old_crtc_state); 2255 2256 intel_disable_transcoder(old_crtc_state); 2257 2258 i9xx_pfit_disable(old_crtc_state); 2259 2260 intel_encoders_post_disable(state, crtc); 2261 2262 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) { 2263 if (IS_CHERRYVIEW(dev_priv)) 2264 chv_disable_pll(dev_priv, pipe); 2265 else if (IS_VALLEYVIEW(dev_priv)) 2266 vlv_disable_pll(dev_priv, pipe); 2267 else 2268 i9xx_disable_pll(old_crtc_state); 2269 } 2270 2271 intel_encoders_post_pll_disable(state, crtc); 2272 2273 if (DISPLAY_VER(dev_priv) != 2) 2274 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 2275 2276 if (!dev_priv->display.funcs.wm->initial_watermarks) 2277 intel_update_watermarks(dev_priv); 2278 2279 /* clock the pipe down to 640x480@60 to potentially save power */ 2280 if (IS_I830(dev_priv)) 2281 i830_enable_pipe(dev_priv, pipe); 2282 } 2283 2284 2285 /* 2286 * turn all crtc's off, but do not adjust state 2287 * This has to be paired with a call to intel_modeset_setup_hw_state. 2288 */ 2289 int intel_display_suspend(struct drm_device *dev) 2290 { 2291 struct drm_i915_private *dev_priv = to_i915(dev); 2292 struct drm_atomic_state *state; 2293 int ret; 2294 2295 if (!HAS_DISPLAY(dev_priv)) 2296 return 0; 2297 2298 state = drm_atomic_helper_suspend(dev); 2299 ret = PTR_ERR_OR_ZERO(state); 2300 if (ret) 2301 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", 2302 ret); 2303 else 2304 dev_priv->display.restore.modeset_state = state; 2305 return ret; 2306 } 2307 2308 void intel_encoder_destroy(struct drm_encoder *encoder) 2309 { 2310 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2311 2312 drm_encoder_cleanup(encoder); 2313 kfree(intel_encoder); 2314 } 2315 2316 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) 2317 { 2318 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2319 2320 /* GDG double wide on either pipe, otherwise pipe A only */ 2321 return DISPLAY_VER(dev_priv) < 4 && 2322 (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); 2323 } 2324 2325 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) 2326 { 2327 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock; 2328 struct drm_rect src; 2329 2330 /* 2331 * We only use IF-ID interlacing. If we ever use 2332 * PF-ID we'll need to adjust the pixel_rate here. 2333 */ 2334 2335 if (!crtc_state->pch_pfit.enabled) 2336 return pixel_rate; 2337 2338 drm_rect_init(&src, 0, 0, 2339 drm_rect_width(&crtc_state->pipe_src) << 16, 2340 drm_rect_height(&crtc_state->pipe_src) << 16); 2341 2342 return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst, 2343 pixel_rate); 2344 } 2345 2346 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode, 2347 const struct drm_display_mode *timings) 2348 { 2349 mode->hdisplay = timings->crtc_hdisplay; 2350 mode->htotal = timings->crtc_htotal; 2351 mode->hsync_start = timings->crtc_hsync_start; 2352 mode->hsync_end = timings->crtc_hsync_end; 2353 2354 mode->vdisplay = timings->crtc_vdisplay; 2355 mode->vtotal = timings->crtc_vtotal; 2356 mode->vsync_start = timings->crtc_vsync_start; 2357 mode->vsync_end = timings->crtc_vsync_end; 2358 2359 mode->flags = timings->flags; 2360 mode->type = DRM_MODE_TYPE_DRIVER; 2361 2362 mode->clock = timings->crtc_clock; 2363 2364 drm_mode_set_name(mode); 2365 } 2366 2367 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) 2368 { 2369 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2370 2371 if (HAS_GMCH(dev_priv)) 2372 /* FIXME calculate proper pipe pixel rate for GMCH pfit */ 2373 crtc_state->pixel_rate = 2374 crtc_state->hw.pipe_mode.crtc_clock; 2375 else 2376 crtc_state->pixel_rate = 2377 ilk_pipe_pixel_rate(crtc_state); 2378 } 2379 2380 static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state *crtc_state, 2381 struct drm_display_mode *mode) 2382 { 2383 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2384 2385 if (num_pipes < 2) 2386 return; 2387 2388 mode->crtc_clock /= num_pipes; 2389 mode->crtc_hdisplay /= num_pipes; 2390 mode->crtc_hblank_start /= num_pipes; 2391 mode->crtc_hblank_end /= num_pipes; 2392 mode->crtc_hsync_start /= num_pipes; 2393 mode->crtc_hsync_end /= num_pipes; 2394 mode->crtc_htotal /= num_pipes; 2395 } 2396 2397 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state, 2398 struct drm_display_mode *mode) 2399 { 2400 int overlap = crtc_state->splitter.pixel_overlap; 2401 int n = crtc_state->splitter.link_count; 2402 2403 if (!crtc_state->splitter.enable) 2404 return; 2405 2406 /* 2407 * eDP MSO uses segment timings from EDID for transcoder 2408 * timings, but full mode for everything else. 2409 * 2410 * h_full = (h_segment - pixel_overlap) * link_count 2411 */ 2412 mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n; 2413 mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n; 2414 mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n; 2415 mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n; 2416 mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n; 2417 mode->crtc_htotal = (mode->crtc_htotal - overlap) * n; 2418 mode->crtc_clock *= n; 2419 } 2420 2421 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state) 2422 { 2423 struct drm_display_mode *mode = &crtc_state->hw.mode; 2424 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2425 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2426 2427 /* 2428 * Start with the adjusted_mode crtc timings, which 2429 * have been filled with the transcoder timings. 2430 */ 2431 drm_mode_copy(pipe_mode, adjusted_mode); 2432 2433 /* Expand MSO per-segment transcoder timings to full */ 2434 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2435 2436 /* 2437 * We want the full numbers in adjusted_mode normal timings, 2438 * adjusted_mode crtc timings are left with the raw transcoder 2439 * timings. 2440 */ 2441 intel_mode_from_crtc_timings(adjusted_mode, pipe_mode); 2442 2443 /* Populate the "user" mode with full numbers */ 2444 drm_mode_copy(mode, pipe_mode); 2445 intel_mode_from_crtc_timings(mode, mode); 2446 mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) * 2447 (intel_bigjoiner_num_pipes(crtc_state) ?: 1); 2448 mode->vdisplay = drm_rect_height(&crtc_state->pipe_src); 2449 2450 /* Derive per-pipe timings in case bigjoiner is used */ 2451 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2452 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2453 2454 intel_crtc_compute_pixel_rate(crtc_state); 2455 } 2456 2457 void intel_encoder_get_config(struct intel_encoder *encoder, 2458 struct intel_crtc_state *crtc_state) 2459 { 2460 encoder->get_config(encoder, crtc_state); 2461 2462 intel_crtc_readout_derived_state(crtc_state); 2463 } 2464 2465 static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state *crtc_state) 2466 { 2467 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2468 int width, height; 2469 2470 if (num_pipes < 2) 2471 return; 2472 2473 width = drm_rect_width(&crtc_state->pipe_src); 2474 height = drm_rect_height(&crtc_state->pipe_src); 2475 2476 drm_rect_init(&crtc_state->pipe_src, 0, 0, 2477 width / num_pipes, height); 2478 } 2479 2480 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state) 2481 { 2482 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2483 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2484 2485 intel_bigjoiner_compute_pipe_src(crtc_state); 2486 2487 /* 2488 * Pipe horizontal size must be even in: 2489 * - DVO ganged mode 2490 * - LVDS dual channel mode 2491 * - Double wide pipe 2492 */ 2493 if (drm_rect_width(&crtc_state->pipe_src) & 1) { 2494 if (crtc_state->double_wide) { 2495 drm_dbg_kms(&i915->drm, 2496 "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n", 2497 crtc->base.base.id, crtc->base.name); 2498 return -EINVAL; 2499 } 2500 2501 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 2502 intel_is_dual_link_lvds(i915)) { 2503 drm_dbg_kms(&i915->drm, 2504 "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n", 2505 crtc->base.base.id, crtc->base.name); 2506 return -EINVAL; 2507 } 2508 } 2509 2510 return 0; 2511 } 2512 2513 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state) 2514 { 2515 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2516 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2517 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2518 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2519 int clock_limit = i915->max_dotclk_freq; 2520 2521 /* 2522 * Start with the adjusted_mode crtc timings, which 2523 * have been filled with the transcoder timings. 2524 */ 2525 drm_mode_copy(pipe_mode, adjusted_mode); 2526 2527 /* Expand MSO per-segment transcoder timings to full */ 2528 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2529 2530 /* Derive per-pipe timings in case bigjoiner is used */ 2531 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2532 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2533 2534 if (DISPLAY_VER(i915) < 4) { 2535 clock_limit = i915->display.cdclk.max_cdclk_freq * 9 / 10; 2536 2537 /* 2538 * Enable double wide mode when the dot clock 2539 * is > 90% of the (display) core speed. 2540 */ 2541 if (intel_crtc_supports_double_wide(crtc) && 2542 pipe_mode->crtc_clock > clock_limit) { 2543 clock_limit = i915->max_dotclk_freq; 2544 crtc_state->double_wide = true; 2545 } 2546 } 2547 2548 if (pipe_mode->crtc_clock > clock_limit) { 2549 drm_dbg_kms(&i915->drm, 2550 "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", 2551 crtc->base.base.id, crtc->base.name, 2552 pipe_mode->crtc_clock, clock_limit, 2553 str_yes_no(crtc_state->double_wide)); 2554 return -EINVAL; 2555 } 2556 2557 return 0; 2558 } 2559 2560 static int intel_crtc_compute_config(struct intel_atomic_state *state, 2561 struct intel_crtc *crtc) 2562 { 2563 struct intel_crtc_state *crtc_state = 2564 intel_atomic_get_new_crtc_state(state, crtc); 2565 int ret; 2566 2567 ret = intel_dpll_crtc_compute_clock(state, crtc); 2568 if (ret) 2569 return ret; 2570 2571 ret = intel_crtc_compute_pipe_src(crtc_state); 2572 if (ret) 2573 return ret; 2574 2575 ret = intel_crtc_compute_pipe_mode(crtc_state); 2576 if (ret) 2577 return ret; 2578 2579 intel_crtc_compute_pixel_rate(crtc_state); 2580 2581 if (crtc_state->has_pch_encoder) 2582 return ilk_fdi_compute_config(crtc, crtc_state); 2583 2584 return 0; 2585 } 2586 2587 static void 2588 intel_reduce_m_n_ratio(u32 *num, u32 *den) 2589 { 2590 while (*num > DATA_LINK_M_N_MASK || 2591 *den > DATA_LINK_M_N_MASK) { 2592 *num >>= 1; 2593 *den >>= 1; 2594 } 2595 } 2596 2597 static void compute_m_n(u32 *ret_m, u32 *ret_n, 2598 u32 m, u32 n, u32 constant_n) 2599 { 2600 if (constant_n) 2601 *ret_n = constant_n; 2602 else 2603 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); 2604 2605 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n); 2606 intel_reduce_m_n_ratio(ret_m, ret_n); 2607 } 2608 2609 void 2610 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes, 2611 int pixel_clock, int link_clock, 2612 struct intel_link_m_n *m_n, 2613 bool fec_enable) 2614 { 2615 u32 data_clock = bits_per_pixel * pixel_clock; 2616 2617 if (fec_enable) 2618 data_clock = intel_dp_mode_to_fec_clock(data_clock); 2619 2620 /* 2621 * Windows/BIOS uses fixed M/N values always. Follow suit. 2622 * 2623 * Also several DP dongles in particular seem to be fussy 2624 * about too large link M/N values. Presumably the 20bit 2625 * value used by Windows/BIOS is acceptable to everyone. 2626 */ 2627 m_n->tu = 64; 2628 compute_m_n(&m_n->data_m, &m_n->data_n, 2629 data_clock, link_clock * nlanes * 8, 2630 0x8000000); 2631 2632 compute_m_n(&m_n->link_m, &m_n->link_n, 2633 pixel_clock, link_clock, 2634 0x80000); 2635 } 2636 2637 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv) 2638 { 2639 /* 2640 * There may be no VBT; and if the BIOS enabled SSC we can 2641 * just keep using it to avoid unnecessary flicker. Whereas if the 2642 * BIOS isn't using it, don't assume it will work even if the VBT 2643 * indicates as much. 2644 */ 2645 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { 2646 bool bios_lvds_use_ssc = intel_de_read(dev_priv, 2647 PCH_DREF_CONTROL) & 2648 DREF_SSC1_ENABLE; 2649 2650 if (dev_priv->display.vbt.lvds_use_ssc != bios_lvds_use_ssc) { 2651 drm_dbg_kms(&dev_priv->drm, 2652 "SSC %s by BIOS, overriding VBT which says %s\n", 2653 str_enabled_disabled(bios_lvds_use_ssc), 2654 str_enabled_disabled(dev_priv->display.vbt.lvds_use_ssc)); 2655 dev_priv->display.vbt.lvds_use_ssc = bios_lvds_use_ssc; 2656 } 2657 } 2658 } 2659 2660 void intel_zero_m_n(struct intel_link_m_n *m_n) 2661 { 2662 /* corresponds to 0 register value */ 2663 memset(m_n, 0, sizeof(*m_n)); 2664 m_n->tu = 1; 2665 } 2666 2667 void intel_set_m_n(struct drm_i915_private *i915, 2668 const struct intel_link_m_n *m_n, 2669 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 2670 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 2671 { 2672 intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); 2673 intel_de_write(i915, data_n_reg, m_n->data_n); 2674 intel_de_write(i915, link_m_reg, m_n->link_m); 2675 /* 2676 * On BDW+ writing LINK_N arms the double buffered update 2677 * of all the M/N registers, so it must be written last. 2678 */ 2679 intel_de_write(i915, link_n_reg, m_n->link_n); 2680 } 2681 2682 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, 2683 enum transcoder transcoder) 2684 { 2685 if (IS_HASWELL(dev_priv)) 2686 return transcoder == TRANSCODER_EDP; 2687 2688 return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv); 2689 } 2690 2691 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, 2692 enum transcoder transcoder, 2693 const struct intel_link_m_n *m_n) 2694 { 2695 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2696 enum pipe pipe = crtc->pipe; 2697 2698 if (DISPLAY_VER(dev_priv) >= 5) 2699 intel_set_m_n(dev_priv, m_n, 2700 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 2701 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 2702 else 2703 intel_set_m_n(dev_priv, m_n, 2704 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 2705 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 2706 } 2707 2708 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, 2709 enum transcoder transcoder, 2710 const struct intel_link_m_n *m_n) 2711 { 2712 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2713 2714 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 2715 return; 2716 2717 intel_set_m_n(dev_priv, m_n, 2718 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 2719 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 2720 } 2721 2722 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) 2723 { 2724 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2725 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2726 enum pipe pipe = crtc->pipe; 2727 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2728 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2729 u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end; 2730 int vsyncshift = 0; 2731 2732 /* We need to be careful not to changed the adjusted mode, for otherwise 2733 * the hw state checker will get angry at the mismatch. */ 2734 crtc_vdisplay = adjusted_mode->crtc_vdisplay; 2735 crtc_vtotal = adjusted_mode->crtc_vtotal; 2736 crtc_vblank_start = adjusted_mode->crtc_vblank_start; 2737 crtc_vblank_end = adjusted_mode->crtc_vblank_end; 2738 2739 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 2740 /* the chip adds 2 halflines automatically */ 2741 crtc_vtotal -= 1; 2742 crtc_vblank_end -= 1; 2743 2744 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 2745 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; 2746 else 2747 vsyncshift = adjusted_mode->crtc_hsync_start - 2748 adjusted_mode->crtc_htotal / 2; 2749 if (vsyncshift < 0) 2750 vsyncshift += adjusted_mode->crtc_htotal; 2751 } 2752 2753 /* 2754 * VBLANK_START no longer works on ADL+, instead we must use 2755 * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start. 2756 */ 2757 if (DISPLAY_VER(dev_priv) >= 13) { 2758 intel_de_write(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder), 2759 crtc_vblank_start - crtc_vdisplay); 2760 2761 /* 2762 * VBLANK_START not used by hw, just clear it 2763 * to make it stand out in register dumps. 2764 */ 2765 crtc_vblank_start = 1; 2766 } 2767 2768 if (DISPLAY_VER(dev_priv) > 3) 2769 intel_de_write(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder), 2770 vsyncshift); 2771 2772 intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder), 2773 HACTIVE(adjusted_mode->crtc_hdisplay - 1) | 2774 HTOTAL(adjusted_mode->crtc_htotal - 1)); 2775 intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder), 2776 HBLANK_START(adjusted_mode->crtc_hblank_start - 1) | 2777 HBLANK_END(adjusted_mode->crtc_hblank_end - 1)); 2778 intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder), 2779 HSYNC_START(adjusted_mode->crtc_hsync_start - 1) | 2780 HSYNC_END(adjusted_mode->crtc_hsync_end - 1)); 2781 2782 intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder), 2783 VACTIVE(crtc_vdisplay - 1) | 2784 VTOTAL(crtc_vtotal - 1)); 2785 intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), 2786 VBLANK_START(crtc_vblank_start - 1) | 2787 VBLANK_END(crtc_vblank_end - 1)); 2788 intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder), 2789 VSYNC_START(adjusted_mode->crtc_vsync_start - 1) | 2790 VSYNC_END(adjusted_mode->crtc_vsync_end - 1)); 2791 2792 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be 2793 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is 2794 * documented on the DDI_FUNC_CTL register description, EDP Input Select 2795 * bits. */ 2796 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && 2797 (pipe == PIPE_B || pipe == PIPE_C)) 2798 intel_de_write(dev_priv, TRANS_VTOTAL(pipe), 2799 VACTIVE(crtc_vdisplay - 1) | 2800 VTOTAL(crtc_vtotal - 1)); 2801 } 2802 2803 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) 2804 { 2805 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2806 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2807 int width = drm_rect_width(&crtc_state->pipe_src); 2808 int height = drm_rect_height(&crtc_state->pipe_src); 2809 enum pipe pipe = crtc->pipe; 2810 2811 /* pipesrc controls the size that is scaled from, which should 2812 * always be the user's requested size. 2813 */ 2814 intel_de_write(dev_priv, PIPESRC(pipe), 2815 PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1)); 2816 } 2817 2818 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) 2819 { 2820 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2821 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2822 2823 if (DISPLAY_VER(dev_priv) == 2) 2824 return false; 2825 2826 if (DISPLAY_VER(dev_priv) >= 9 || 2827 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2828 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW; 2829 else 2830 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK; 2831 } 2832 2833 static void intel_get_transcoder_timings(struct intel_crtc *crtc, 2834 struct intel_crtc_state *pipe_config) 2835 { 2836 struct drm_device *dev = crtc->base.dev; 2837 struct drm_i915_private *dev_priv = to_i915(dev); 2838 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 2839 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2840 u32 tmp; 2841 2842 tmp = intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder)); 2843 adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1; 2844 adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1; 2845 2846 if (!transcoder_is_dsi(cpu_transcoder)) { 2847 tmp = intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder)); 2848 adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1; 2849 adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1; 2850 } 2851 2852 tmp = intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder)); 2853 adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1; 2854 adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1; 2855 2856 tmp = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder)); 2857 adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1; 2858 adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1; 2859 2860 /* FIXME TGL+ DSI transcoders have this! */ 2861 if (!transcoder_is_dsi(cpu_transcoder)) { 2862 tmp = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder)); 2863 adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1; 2864 adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1; 2865 } 2866 tmp = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder)); 2867 adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1; 2868 adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1; 2869 2870 if (intel_pipe_is_interlaced(pipe_config)) { 2871 adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE; 2872 adjusted_mode->crtc_vtotal += 1; 2873 adjusted_mode->crtc_vblank_end += 1; 2874 } 2875 2876 if (DISPLAY_VER(dev_priv) >= 13 && !transcoder_is_dsi(cpu_transcoder)) 2877 adjusted_mode->crtc_vblank_start = 2878 adjusted_mode->crtc_vdisplay + 2879 intel_de_read(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder)); 2880 } 2881 2882 static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state) 2883 { 2884 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2885 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2886 enum pipe master_pipe, pipe = crtc->pipe; 2887 int width; 2888 2889 if (num_pipes < 2) 2890 return; 2891 2892 master_pipe = bigjoiner_master_pipe(crtc_state); 2893 width = drm_rect_width(&crtc_state->pipe_src); 2894 2895 drm_rect_translate_to(&crtc_state->pipe_src, 2896 (pipe - master_pipe) * width, 0); 2897 } 2898 2899 static void intel_get_pipe_src_size(struct intel_crtc *crtc, 2900 struct intel_crtc_state *pipe_config) 2901 { 2902 struct drm_device *dev = crtc->base.dev; 2903 struct drm_i915_private *dev_priv = to_i915(dev); 2904 u32 tmp; 2905 2906 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe)); 2907 2908 drm_rect_init(&pipe_config->pipe_src, 0, 0, 2909 REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1, 2910 REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1); 2911 2912 intel_bigjoiner_adjust_pipe_src(pipe_config); 2913 } 2914 2915 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) 2916 { 2917 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2918 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2919 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2920 u32 val = 0; 2921 2922 /* 2923 * - We keep both pipes enabled on 830 2924 * - During modeset the pipe is still disabled and must remain so 2925 * - During fastset the pipe is already enabled and must remain so 2926 */ 2927 if (IS_I830(dev_priv) || !intel_crtc_needs_modeset(crtc_state)) 2928 val |= TRANSCONF_ENABLE; 2929 2930 if (crtc_state->double_wide) 2931 val |= TRANSCONF_DOUBLE_WIDE; 2932 2933 /* only g4x and later have fancy bpc/dither controls */ 2934 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 2935 IS_CHERRYVIEW(dev_priv)) { 2936 /* Bspec claims that we can't use dithering for 30bpp pipes. */ 2937 if (crtc_state->dither && crtc_state->pipe_bpp != 30) 2938 val |= TRANSCONF_DITHER_EN | 2939 TRANSCONF_DITHER_TYPE_SP; 2940 2941 switch (crtc_state->pipe_bpp) { 2942 default: 2943 /* Case prevented by intel_choose_pipe_bpp_dither. */ 2944 MISSING_CASE(crtc_state->pipe_bpp); 2945 fallthrough; 2946 case 18: 2947 val |= TRANSCONF_BPC_6; 2948 break; 2949 case 24: 2950 val |= TRANSCONF_BPC_8; 2951 break; 2952 case 30: 2953 val |= TRANSCONF_BPC_10; 2954 break; 2955 } 2956 } 2957 2958 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 2959 if (DISPLAY_VER(dev_priv) < 4 || 2960 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 2961 val |= TRANSCONF_INTERLACE_W_FIELD_INDICATION; 2962 else 2963 val |= TRANSCONF_INTERLACE_W_SYNC_SHIFT; 2964 } else { 2965 val |= TRANSCONF_INTERLACE_PROGRESSIVE; 2966 } 2967 2968 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 2969 crtc_state->limited_color_range) 2970 val |= TRANSCONF_COLOR_RANGE_SELECT; 2971 2972 val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode); 2973 2974 val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 2975 2976 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); 2977 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); 2978 } 2979 2980 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv) 2981 { 2982 if (IS_I830(dev_priv)) 2983 return false; 2984 2985 return DISPLAY_VER(dev_priv) >= 4 || 2986 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); 2987 } 2988 2989 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state) 2990 { 2991 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2992 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2993 u32 tmp; 2994 2995 if (!i9xx_has_pfit(dev_priv)) 2996 return; 2997 2998 tmp = intel_de_read(dev_priv, PFIT_CONTROL); 2999 if (!(tmp & PFIT_ENABLE)) 3000 return; 3001 3002 /* Check whether the pfit is attached to our pipe. */ 3003 if (DISPLAY_VER(dev_priv) < 4) { 3004 if (crtc->pipe != PIPE_B) 3005 return; 3006 } else { 3007 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) 3008 return; 3009 } 3010 3011 crtc_state->gmch_pfit.control = tmp; 3012 crtc_state->gmch_pfit.pgm_ratios = 3013 intel_de_read(dev_priv, PFIT_PGM_RATIOS); 3014 } 3015 3016 static void vlv_crtc_clock_get(struct intel_crtc *crtc, 3017 struct intel_crtc_state *pipe_config) 3018 { 3019 struct drm_device *dev = crtc->base.dev; 3020 struct drm_i915_private *dev_priv = to_i915(dev); 3021 enum pipe pipe = crtc->pipe; 3022 struct dpll clock; 3023 u32 mdiv; 3024 int refclk = 100000; 3025 3026 /* In case of DSI, DPLL will not be used */ 3027 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 3028 return; 3029 3030 vlv_dpio_get(dev_priv); 3031 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); 3032 vlv_dpio_put(dev_priv); 3033 3034 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; 3035 clock.m2 = mdiv & DPIO_M2DIV_MASK; 3036 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; 3037 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; 3038 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; 3039 3040 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); 3041 } 3042 3043 static void chv_crtc_clock_get(struct intel_crtc *crtc, 3044 struct intel_crtc_state *pipe_config) 3045 { 3046 struct drm_device *dev = crtc->base.dev; 3047 struct drm_i915_private *dev_priv = to_i915(dev); 3048 enum pipe pipe = crtc->pipe; 3049 enum dpio_channel port = vlv_pipe_to_channel(pipe); 3050 struct dpll clock; 3051 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; 3052 int refclk = 100000; 3053 3054 /* In case of DSI, DPLL will not be used */ 3055 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 3056 return; 3057 3058 vlv_dpio_get(dev_priv); 3059 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); 3060 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); 3061 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); 3062 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); 3063 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); 3064 vlv_dpio_put(dev_priv); 3065 3066 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; 3067 clock.m2 = (pll_dw0 & 0xff) << 22; 3068 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) 3069 clock.m2 |= pll_dw2 & 0x3fffff; 3070 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; 3071 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; 3072 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; 3073 3074 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); 3075 } 3076 3077 static enum intel_output_format 3078 bdw_get_pipe_misc_output_format(struct intel_crtc *crtc) 3079 { 3080 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3081 u32 tmp; 3082 3083 tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe)); 3084 3085 if (tmp & PIPE_MISC_YUV420_ENABLE) { 3086 /* We support 4:2:0 in full blend mode only */ 3087 drm_WARN_ON(&dev_priv->drm, 3088 (tmp & PIPE_MISC_YUV420_MODE_FULL_BLEND) == 0); 3089 3090 return INTEL_OUTPUT_FORMAT_YCBCR420; 3091 } else if (tmp & PIPE_MISC_OUTPUT_COLORSPACE_YUV) { 3092 return INTEL_OUTPUT_FORMAT_YCBCR444; 3093 } else { 3094 return INTEL_OUTPUT_FORMAT_RGB; 3095 } 3096 } 3097 3098 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state) 3099 { 3100 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3101 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 3102 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3103 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 3104 u32 tmp; 3105 3106 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); 3107 3108 if (tmp & DISP_PIPE_GAMMA_ENABLE) 3109 crtc_state->gamma_enable = true; 3110 3111 if (!HAS_GMCH(dev_priv) && 3112 tmp & DISP_PIPE_CSC_ENABLE) 3113 crtc_state->csc_enable = true; 3114 } 3115 3116 static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 3117 struct intel_crtc_state *pipe_config) 3118 { 3119 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3120 enum intel_display_power_domain power_domain; 3121 intel_wakeref_t wakeref; 3122 u32 tmp; 3123 bool ret; 3124 3125 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3126 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3127 if (!wakeref) 3128 return false; 3129 3130 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3131 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3132 pipe_config->shared_dpll = NULL; 3133 3134 ret = false; 3135 3136 tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder)); 3137 if (!(tmp & TRANSCONF_ENABLE)) 3138 goto out; 3139 3140 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 3141 IS_CHERRYVIEW(dev_priv)) { 3142 switch (tmp & TRANSCONF_BPC_MASK) { 3143 case TRANSCONF_BPC_6: 3144 pipe_config->pipe_bpp = 18; 3145 break; 3146 case TRANSCONF_BPC_8: 3147 pipe_config->pipe_bpp = 24; 3148 break; 3149 case TRANSCONF_BPC_10: 3150 pipe_config->pipe_bpp = 30; 3151 break; 3152 default: 3153 MISSING_CASE(tmp); 3154 break; 3155 } 3156 } 3157 3158 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 3159 (tmp & TRANSCONF_COLOR_RANGE_SELECT)) 3160 pipe_config->limited_color_range = true; 3161 3162 pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp); 3163 3164 pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1; 3165 3166 if (IS_CHERRYVIEW(dev_priv)) 3167 pipe_config->cgm_mode = intel_de_read(dev_priv, 3168 CGM_PIPE_MODE(crtc->pipe)); 3169 3170 i9xx_get_pipe_color_config(pipe_config); 3171 intel_color_get_config(pipe_config); 3172 3173 if (DISPLAY_VER(dev_priv) < 4) 3174 pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE; 3175 3176 intel_get_transcoder_timings(crtc, pipe_config); 3177 intel_get_pipe_src_size(crtc, pipe_config); 3178 3179 i9xx_get_pfit_config(pipe_config); 3180 3181 if (DISPLAY_VER(dev_priv) >= 4) { 3182 /* No way to read it out on pipes B and C */ 3183 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) 3184 tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe]; 3185 else 3186 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe)); 3187 pipe_config->pixel_multiplier = 3188 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) 3189 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; 3190 pipe_config->dpll_hw_state.dpll_md = tmp; 3191 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 3192 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 3193 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe)); 3194 pipe_config->pixel_multiplier = 3195 ((tmp & SDVO_MULTIPLIER_MASK) 3196 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; 3197 } else { 3198 /* Note that on i915G/GM the pixel multiplier is in the sdvo 3199 * port and will be fixed up in the encoder->get_config 3200 * function. */ 3201 pipe_config->pixel_multiplier = 1; 3202 } 3203 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv, 3204 DPLL(crtc->pipe)); 3205 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 3206 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv, 3207 FP0(crtc->pipe)); 3208 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv, 3209 FP1(crtc->pipe)); 3210 } else { 3211 /* Mask out read-only status bits. */ 3212 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | 3213 DPLL_PORTC_READY_MASK | 3214 DPLL_PORTB_READY_MASK); 3215 } 3216 3217 if (IS_CHERRYVIEW(dev_priv)) 3218 chv_crtc_clock_get(crtc, pipe_config); 3219 else if (IS_VALLEYVIEW(dev_priv)) 3220 vlv_crtc_clock_get(crtc, pipe_config); 3221 else 3222 i9xx_crtc_clock_get(crtc, pipe_config); 3223 3224 /* 3225 * Normally the dotclock is filled in by the encoder .get_config() 3226 * but in case the pipe is enabled w/o any ports we need a sane 3227 * default. 3228 */ 3229 pipe_config->hw.adjusted_mode.crtc_clock = 3230 pipe_config->port_clock / pipe_config->pixel_multiplier; 3231 3232 ret = true; 3233 3234 out: 3235 intel_display_power_put(dev_priv, power_domain, wakeref); 3236 3237 return ret; 3238 } 3239 3240 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) 3241 { 3242 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3243 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3244 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3245 u32 val = 0; 3246 3247 /* 3248 * - During modeset the pipe is still disabled and must remain so 3249 * - During fastset the pipe is already enabled and must remain so 3250 */ 3251 if (!intel_crtc_needs_modeset(crtc_state)) 3252 val |= TRANSCONF_ENABLE; 3253 3254 switch (crtc_state->pipe_bpp) { 3255 default: 3256 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3257 MISSING_CASE(crtc_state->pipe_bpp); 3258 fallthrough; 3259 case 18: 3260 val |= TRANSCONF_BPC_6; 3261 break; 3262 case 24: 3263 val |= TRANSCONF_BPC_8; 3264 break; 3265 case 30: 3266 val |= TRANSCONF_BPC_10; 3267 break; 3268 case 36: 3269 val |= TRANSCONF_BPC_12; 3270 break; 3271 } 3272 3273 if (crtc_state->dither) 3274 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP; 3275 3276 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3277 val |= TRANSCONF_INTERLACE_IF_ID_ILK; 3278 else 3279 val |= TRANSCONF_INTERLACE_PF_PD_ILK; 3280 3281 /* 3282 * This would end up with an odd purple hue over 3283 * the entire display. Make sure we don't do it. 3284 */ 3285 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 3286 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 3287 3288 if (crtc_state->limited_color_range && 3289 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3290 val |= TRANSCONF_COLOR_RANGE_SELECT; 3291 3292 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3293 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV709; 3294 3295 val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode); 3296 3297 val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3298 val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay); 3299 3300 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); 3301 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); 3302 } 3303 3304 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) 3305 { 3306 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3307 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3308 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3309 u32 val = 0; 3310 3311 /* 3312 * - During modeset the pipe is still disabled and must remain so 3313 * - During fastset the pipe is already enabled and must remain so 3314 */ 3315 if (!intel_crtc_needs_modeset(crtc_state)) 3316 val |= TRANSCONF_ENABLE; 3317 3318 if (IS_HASWELL(dev_priv) && crtc_state->dither) 3319 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP; 3320 3321 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3322 val |= TRANSCONF_INTERLACE_IF_ID_ILK; 3323 else 3324 val |= TRANSCONF_INTERLACE_PF_PD_ILK; 3325 3326 if (IS_HASWELL(dev_priv) && 3327 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3328 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW; 3329 3330 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); 3331 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); 3332 } 3333 3334 static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state) 3335 { 3336 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3337 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3338 u32 val = 0; 3339 3340 switch (crtc_state->pipe_bpp) { 3341 case 18: 3342 val |= PIPE_MISC_BPC_6; 3343 break; 3344 case 24: 3345 val |= PIPE_MISC_BPC_8; 3346 break; 3347 case 30: 3348 val |= PIPE_MISC_BPC_10; 3349 break; 3350 case 36: 3351 /* Port output 12BPC defined for ADLP+ */ 3352 if (DISPLAY_VER(dev_priv) > 12) 3353 val |= PIPE_MISC_BPC_12_ADLP; 3354 break; 3355 default: 3356 MISSING_CASE(crtc_state->pipe_bpp); 3357 break; 3358 } 3359 3360 if (crtc_state->dither) 3361 val |= PIPE_MISC_DITHER_ENABLE | PIPE_MISC_DITHER_TYPE_SP; 3362 3363 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 3364 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 3365 val |= PIPE_MISC_OUTPUT_COLORSPACE_YUV; 3366 3367 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 3368 val |= PIPE_MISC_YUV420_ENABLE | 3369 PIPE_MISC_YUV420_MODE_FULL_BLEND; 3370 3371 if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state)) 3372 val |= PIPE_MISC_HDR_MODE_PRECISION; 3373 3374 if (DISPLAY_VER(dev_priv) >= 12) 3375 val |= PIPE_MISC_PIXEL_ROUNDING_TRUNC; 3376 3377 intel_de_write(dev_priv, PIPE_MISC(crtc->pipe), val); 3378 } 3379 3380 int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc) 3381 { 3382 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3383 u32 tmp; 3384 3385 tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe)); 3386 3387 switch (tmp & PIPE_MISC_BPC_MASK) { 3388 case PIPE_MISC_BPC_6: 3389 return 18; 3390 case PIPE_MISC_BPC_8: 3391 return 24; 3392 case PIPE_MISC_BPC_10: 3393 return 30; 3394 /* 3395 * PORT OUTPUT 12 BPC defined for ADLP+. 3396 * 3397 * TODO: 3398 * For previous platforms with DSI interface, bits 5:7 3399 * are used for storing pipe_bpp irrespective of dithering. 3400 * Since the value of 12 BPC is not defined for these bits 3401 * on older platforms, need to find a workaround for 12 BPC 3402 * MIPI DSI HW readout. 3403 */ 3404 case PIPE_MISC_BPC_12_ADLP: 3405 if (DISPLAY_VER(dev_priv) > 12) 3406 return 36; 3407 fallthrough; 3408 default: 3409 MISSING_CASE(tmp); 3410 return 0; 3411 } 3412 } 3413 3414 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) 3415 { 3416 /* 3417 * Account for spread spectrum to avoid 3418 * oversubscribing the link. Max center spread 3419 * is 2.5%; use 5% for safety's sake. 3420 */ 3421 u32 bps = target_clock * bpp * 21 / 20; 3422 return DIV_ROUND_UP(bps, link_bw * 8); 3423 } 3424 3425 void intel_get_m_n(struct drm_i915_private *i915, 3426 struct intel_link_m_n *m_n, 3427 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 3428 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 3429 { 3430 m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK; 3431 m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK; 3432 m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK; 3433 m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK; 3434 m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1; 3435 } 3436 3437 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, 3438 enum transcoder transcoder, 3439 struct intel_link_m_n *m_n) 3440 { 3441 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3442 enum pipe pipe = crtc->pipe; 3443 3444 if (DISPLAY_VER(dev_priv) >= 5) 3445 intel_get_m_n(dev_priv, m_n, 3446 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 3447 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 3448 else 3449 intel_get_m_n(dev_priv, m_n, 3450 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 3451 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 3452 } 3453 3454 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, 3455 enum transcoder transcoder, 3456 struct intel_link_m_n *m_n) 3457 { 3458 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3459 3460 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 3461 return; 3462 3463 intel_get_m_n(dev_priv, m_n, 3464 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 3465 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 3466 } 3467 3468 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state, 3469 u32 pos, u32 size) 3470 { 3471 drm_rect_init(&crtc_state->pch_pfit.dst, 3472 pos >> 16, pos & 0xffff, 3473 size >> 16, size & 0xffff); 3474 } 3475 3476 static void skl_get_pfit_config(struct intel_crtc_state *crtc_state) 3477 { 3478 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3479 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3480 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; 3481 int id = -1; 3482 int i; 3483 3484 /* find scaler attached to this pipe */ 3485 for (i = 0; i < crtc->num_scalers; i++) { 3486 u32 ctl, pos, size; 3487 3488 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i)); 3489 if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN) 3490 continue; 3491 3492 id = i; 3493 crtc_state->pch_pfit.enabled = true; 3494 3495 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i)); 3496 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i)); 3497 3498 ilk_get_pfit_pos_size(crtc_state, pos, size); 3499 3500 scaler_state->scalers[i].in_use = true; 3501 break; 3502 } 3503 3504 scaler_state->scaler_id = id; 3505 if (id >= 0) 3506 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); 3507 else 3508 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); 3509 } 3510 3511 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state) 3512 { 3513 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3514 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3515 u32 ctl, pos, size; 3516 3517 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe)); 3518 if ((ctl & PF_ENABLE) == 0) 3519 return; 3520 3521 crtc_state->pch_pfit.enabled = true; 3522 3523 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe)); 3524 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe)); 3525 3526 ilk_get_pfit_pos_size(crtc_state, pos, size); 3527 3528 /* 3529 * We currently do not free assignements of panel fitters on 3530 * ivb/hsw (since we don't use the higher upscaling modes which 3531 * differentiates them) so just WARN about this case for now. 3532 */ 3533 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 7 && 3534 (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe)); 3535 } 3536 3537 static bool ilk_get_pipe_config(struct intel_crtc *crtc, 3538 struct intel_crtc_state *pipe_config) 3539 { 3540 struct drm_device *dev = crtc->base.dev; 3541 struct drm_i915_private *dev_priv = to_i915(dev); 3542 enum intel_display_power_domain power_domain; 3543 intel_wakeref_t wakeref; 3544 u32 tmp; 3545 bool ret; 3546 3547 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3548 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3549 if (!wakeref) 3550 return false; 3551 3552 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3553 pipe_config->shared_dpll = NULL; 3554 3555 ret = false; 3556 tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder)); 3557 if (!(tmp & TRANSCONF_ENABLE)) 3558 goto out; 3559 3560 switch (tmp & TRANSCONF_BPC_MASK) { 3561 case TRANSCONF_BPC_6: 3562 pipe_config->pipe_bpp = 18; 3563 break; 3564 case TRANSCONF_BPC_8: 3565 pipe_config->pipe_bpp = 24; 3566 break; 3567 case TRANSCONF_BPC_10: 3568 pipe_config->pipe_bpp = 30; 3569 break; 3570 case TRANSCONF_BPC_12: 3571 pipe_config->pipe_bpp = 36; 3572 break; 3573 default: 3574 break; 3575 } 3576 3577 if (tmp & TRANSCONF_COLOR_RANGE_SELECT) 3578 pipe_config->limited_color_range = true; 3579 3580 switch (tmp & TRANSCONF_OUTPUT_COLORSPACE_MASK) { 3581 case TRANSCONF_OUTPUT_COLORSPACE_YUV601: 3582 case TRANSCONF_OUTPUT_COLORSPACE_YUV709: 3583 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3584 break; 3585 default: 3586 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3587 break; 3588 } 3589 3590 pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp); 3591 3592 pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1; 3593 3594 pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp); 3595 3596 pipe_config->csc_mode = intel_de_read(dev_priv, 3597 PIPE_CSC_MODE(crtc->pipe)); 3598 3599 i9xx_get_pipe_color_config(pipe_config); 3600 intel_color_get_config(pipe_config); 3601 3602 pipe_config->pixel_multiplier = 1; 3603 3604 ilk_pch_get_config(pipe_config); 3605 3606 intel_get_transcoder_timings(crtc, pipe_config); 3607 intel_get_pipe_src_size(crtc, pipe_config); 3608 3609 ilk_get_pfit_config(pipe_config); 3610 3611 ret = true; 3612 3613 out: 3614 intel_display_power_put(dev_priv, power_domain, wakeref); 3615 3616 return ret; 3617 } 3618 3619 static u8 bigjoiner_pipes(struct drm_i915_private *i915) 3620 { 3621 u8 pipes; 3622 3623 if (DISPLAY_VER(i915) >= 12) 3624 pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D); 3625 else if (DISPLAY_VER(i915) >= 11) 3626 pipes = BIT(PIPE_B) | BIT(PIPE_C); 3627 else 3628 pipes = 0; 3629 3630 return pipes & RUNTIME_INFO(i915)->pipe_mask; 3631 } 3632 3633 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv, 3634 enum transcoder cpu_transcoder) 3635 { 3636 enum intel_display_power_domain power_domain; 3637 intel_wakeref_t wakeref; 3638 u32 tmp = 0; 3639 3640 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3641 3642 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3643 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3644 3645 return tmp & TRANS_DDI_FUNC_ENABLE; 3646 } 3647 3648 static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv, 3649 u8 *master_pipes, u8 *slave_pipes) 3650 { 3651 struct intel_crtc *crtc; 3652 3653 *master_pipes = 0; 3654 *slave_pipes = 0; 3655 3656 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, 3657 bigjoiner_pipes(dev_priv)) { 3658 enum intel_display_power_domain power_domain; 3659 enum pipe pipe = crtc->pipe; 3660 intel_wakeref_t wakeref; 3661 3662 power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe); 3663 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3664 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3665 3666 if (!(tmp & BIG_JOINER_ENABLE)) 3667 continue; 3668 3669 if (tmp & MASTER_BIG_JOINER_ENABLE) 3670 *master_pipes |= BIT(pipe); 3671 else 3672 *slave_pipes |= BIT(pipe); 3673 } 3674 3675 if (DISPLAY_VER(dev_priv) < 13) 3676 continue; 3677 3678 power_domain = POWER_DOMAIN_PIPE(pipe); 3679 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3680 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3681 3682 if (tmp & UNCOMPRESSED_JOINER_MASTER) 3683 *master_pipes |= BIT(pipe); 3684 if (tmp & UNCOMPRESSED_JOINER_SLAVE) 3685 *slave_pipes |= BIT(pipe); 3686 } 3687 } 3688 3689 /* Bigjoiner pipes should always be consecutive master and slave */ 3690 drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1, 3691 "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n", 3692 *master_pipes, *slave_pipes); 3693 } 3694 3695 static enum pipe get_bigjoiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3696 { 3697 if ((slave_pipes & BIT(pipe)) == 0) 3698 return pipe; 3699 3700 /* ignore everything above our pipe */ 3701 master_pipes &= ~GENMASK(7, pipe); 3702 3703 /* highest remaining bit should be our master pipe */ 3704 return fls(master_pipes) - 1; 3705 } 3706 3707 static u8 get_bigjoiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3708 { 3709 enum pipe master_pipe, next_master_pipe; 3710 3711 master_pipe = get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes); 3712 3713 if ((master_pipes & BIT(master_pipe)) == 0) 3714 return 0; 3715 3716 /* ignore our master pipe and everything below it */ 3717 master_pipes &= ~GENMASK(master_pipe, 0); 3718 /* make sure a high bit is set for the ffs() */ 3719 master_pipes |= BIT(7); 3720 /* lowest remaining bit should be the next master pipe */ 3721 next_master_pipe = ffs(master_pipes) - 1; 3722 3723 return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe); 3724 } 3725 3726 static u8 hsw_panel_transcoders(struct drm_i915_private *i915) 3727 { 3728 u8 panel_transcoder_mask = BIT(TRANSCODER_EDP); 3729 3730 if (DISPLAY_VER(i915) >= 11) 3731 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); 3732 3733 return panel_transcoder_mask; 3734 } 3735 3736 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) 3737 { 3738 struct drm_device *dev = crtc->base.dev; 3739 struct drm_i915_private *dev_priv = to_i915(dev); 3740 u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv); 3741 enum transcoder cpu_transcoder; 3742 u8 master_pipes, slave_pipes; 3743 u8 enabled_transcoders = 0; 3744 3745 /* 3746 * XXX: Do intel_display_power_get_if_enabled before reading this (for 3747 * consistency and less surprising code; it's in always on power). 3748 */ 3749 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, 3750 panel_transcoder_mask) { 3751 enum intel_display_power_domain power_domain; 3752 intel_wakeref_t wakeref; 3753 enum pipe trans_pipe; 3754 u32 tmp = 0; 3755 3756 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3757 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3758 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3759 3760 if (!(tmp & TRANS_DDI_FUNC_ENABLE)) 3761 continue; 3762 3763 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 3764 default: 3765 drm_WARN(dev, 1, 3766 "unknown pipe linked to transcoder %s\n", 3767 transcoder_name(cpu_transcoder)); 3768 fallthrough; 3769 case TRANS_DDI_EDP_INPUT_A_ONOFF: 3770 case TRANS_DDI_EDP_INPUT_A_ON: 3771 trans_pipe = PIPE_A; 3772 break; 3773 case TRANS_DDI_EDP_INPUT_B_ONOFF: 3774 trans_pipe = PIPE_B; 3775 break; 3776 case TRANS_DDI_EDP_INPUT_C_ONOFF: 3777 trans_pipe = PIPE_C; 3778 break; 3779 case TRANS_DDI_EDP_INPUT_D_ONOFF: 3780 trans_pipe = PIPE_D; 3781 break; 3782 } 3783 3784 if (trans_pipe == crtc->pipe) 3785 enabled_transcoders |= BIT(cpu_transcoder); 3786 } 3787 3788 /* single pipe or bigjoiner master */ 3789 cpu_transcoder = (enum transcoder) crtc->pipe; 3790 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 3791 enabled_transcoders |= BIT(cpu_transcoder); 3792 3793 /* bigjoiner slave -> consider the master pipe's transcoder as well */ 3794 enabled_bigjoiner_pipes(dev_priv, &master_pipes, &slave_pipes); 3795 if (slave_pipes & BIT(crtc->pipe)) { 3796 cpu_transcoder = (enum transcoder) 3797 get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes); 3798 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 3799 enabled_transcoders |= BIT(cpu_transcoder); 3800 } 3801 3802 return enabled_transcoders; 3803 } 3804 3805 static bool has_edp_transcoders(u8 enabled_transcoders) 3806 { 3807 return enabled_transcoders & BIT(TRANSCODER_EDP); 3808 } 3809 3810 static bool has_dsi_transcoders(u8 enabled_transcoders) 3811 { 3812 return enabled_transcoders & (BIT(TRANSCODER_DSI_0) | 3813 BIT(TRANSCODER_DSI_1)); 3814 } 3815 3816 static bool has_pipe_transcoders(u8 enabled_transcoders) 3817 { 3818 return enabled_transcoders & ~(BIT(TRANSCODER_EDP) | 3819 BIT(TRANSCODER_DSI_0) | 3820 BIT(TRANSCODER_DSI_1)); 3821 } 3822 3823 static void assert_enabled_transcoders(struct drm_i915_private *i915, 3824 u8 enabled_transcoders) 3825 { 3826 /* Only one type of transcoder please */ 3827 drm_WARN_ON(&i915->drm, 3828 has_edp_transcoders(enabled_transcoders) + 3829 has_dsi_transcoders(enabled_transcoders) + 3830 has_pipe_transcoders(enabled_transcoders) > 1); 3831 3832 /* Only DSI transcoders can be ganged */ 3833 drm_WARN_ON(&i915->drm, 3834 !has_dsi_transcoders(enabled_transcoders) && 3835 !is_power_of_2(enabled_transcoders)); 3836 } 3837 3838 static bool hsw_get_transcoder_state(struct intel_crtc *crtc, 3839 struct intel_crtc_state *pipe_config, 3840 struct intel_display_power_domain_set *power_domain_set) 3841 { 3842 struct drm_device *dev = crtc->base.dev; 3843 struct drm_i915_private *dev_priv = to_i915(dev); 3844 unsigned long enabled_transcoders; 3845 u32 tmp; 3846 3847 enabled_transcoders = hsw_enabled_transcoders(crtc); 3848 if (!enabled_transcoders) 3849 return false; 3850 3851 assert_enabled_transcoders(dev_priv, enabled_transcoders); 3852 3853 /* 3854 * With the exception of DSI we should only ever have 3855 * a single enabled transcoder. With DSI let's just 3856 * pick the first one. 3857 */ 3858 pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1; 3859 3860 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 3861 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) 3862 return false; 3863 3864 if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) { 3865 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); 3866 3867 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF) 3868 pipe_config->pch_pfit.force_thru = true; 3869 } 3870 3871 tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder)); 3872 3873 return tmp & TRANSCONF_ENABLE; 3874 } 3875 3876 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, 3877 struct intel_crtc_state *pipe_config, 3878 struct intel_display_power_domain_set *power_domain_set) 3879 { 3880 struct drm_device *dev = crtc->base.dev; 3881 struct drm_i915_private *dev_priv = to_i915(dev); 3882 enum transcoder cpu_transcoder; 3883 enum port port; 3884 u32 tmp; 3885 3886 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { 3887 if (port == PORT_A) 3888 cpu_transcoder = TRANSCODER_DSI_A; 3889 else 3890 cpu_transcoder = TRANSCODER_DSI_C; 3891 3892 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 3893 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) 3894 continue; 3895 3896 /* 3897 * The PLL needs to be enabled with a valid divider 3898 * configuration, otherwise accessing DSI registers will hang 3899 * the machine. See BSpec North Display Engine 3900 * registers/MIPI[BXT]. We can break out here early, since we 3901 * need the same DSI PLL to be enabled for both DSI ports. 3902 */ 3903 if (!bxt_dsi_pll_is_enabled(dev_priv)) 3904 break; 3905 3906 /* XXX: this works for video mode only */ 3907 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); 3908 if (!(tmp & DPI_ENABLE)) 3909 continue; 3910 3911 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 3912 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) 3913 continue; 3914 3915 pipe_config->cpu_transcoder = cpu_transcoder; 3916 break; 3917 } 3918 3919 return transcoder_is_dsi(pipe_config->cpu_transcoder); 3920 } 3921 3922 static void intel_bigjoiner_get_config(struct intel_crtc_state *crtc_state) 3923 { 3924 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3925 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 3926 u8 master_pipes, slave_pipes; 3927 enum pipe pipe = crtc->pipe; 3928 3929 enabled_bigjoiner_pipes(i915, &master_pipes, &slave_pipes); 3930 3931 if (((master_pipes | slave_pipes) & BIT(pipe)) == 0) 3932 return; 3933 3934 crtc_state->bigjoiner_pipes = 3935 BIT(get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes)) | 3936 get_bigjoiner_slave_pipes(pipe, master_pipes, slave_pipes); 3937 } 3938 3939 static bool hsw_get_pipe_config(struct intel_crtc *crtc, 3940 struct intel_crtc_state *pipe_config) 3941 { 3942 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3943 bool active; 3944 u32 tmp; 3945 3946 if (!intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains, 3947 POWER_DOMAIN_PIPE(crtc->pipe))) 3948 return false; 3949 3950 pipe_config->shared_dpll = NULL; 3951 3952 active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains); 3953 3954 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 3955 bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) { 3956 drm_WARN_ON(&dev_priv->drm, active); 3957 active = true; 3958 } 3959 3960 if (!active) 3961 goto out; 3962 3963 intel_dsc_get_config(pipe_config); 3964 intel_bigjoiner_get_config(pipe_config); 3965 3966 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || 3967 DISPLAY_VER(dev_priv) >= 11) 3968 intel_get_transcoder_timings(crtc, pipe_config); 3969 3970 if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder)) 3971 intel_vrr_get_config(crtc, pipe_config); 3972 3973 intel_get_pipe_src_size(crtc, pipe_config); 3974 3975 if (IS_HASWELL(dev_priv)) { 3976 u32 tmp = intel_de_read(dev_priv, 3977 TRANSCONF(pipe_config->cpu_transcoder)); 3978 3979 if (tmp & TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW) 3980 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3981 else 3982 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3983 } else { 3984 pipe_config->output_format = 3985 bdw_get_pipe_misc_output_format(crtc); 3986 } 3987 3988 pipe_config->gamma_mode = intel_de_read(dev_priv, 3989 GAMMA_MODE(crtc->pipe)); 3990 3991 pipe_config->csc_mode = intel_de_read(dev_priv, 3992 PIPE_CSC_MODE(crtc->pipe)); 3993 3994 if (DISPLAY_VER(dev_priv) >= 9) { 3995 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe)); 3996 3997 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE) 3998 pipe_config->gamma_enable = true; 3999 4000 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE) 4001 pipe_config->csc_enable = true; 4002 } else { 4003 i9xx_get_pipe_color_config(pipe_config); 4004 } 4005 4006 intel_color_get_config(pipe_config); 4007 4008 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe)); 4009 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); 4010 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 4011 pipe_config->ips_linetime = 4012 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); 4013 4014 if (intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains, 4015 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) { 4016 if (DISPLAY_VER(dev_priv) >= 9) 4017 skl_get_pfit_config(pipe_config); 4018 else 4019 ilk_get_pfit_config(pipe_config); 4020 } 4021 4022 hsw_ips_get_config(pipe_config); 4023 4024 if (pipe_config->cpu_transcoder != TRANSCODER_EDP && 4025 !transcoder_is_dsi(pipe_config->cpu_transcoder)) { 4026 pipe_config->pixel_multiplier = 4027 intel_de_read(dev_priv, 4028 TRANS_MULT(pipe_config->cpu_transcoder)) + 1; 4029 } else { 4030 pipe_config->pixel_multiplier = 1; 4031 } 4032 4033 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { 4034 tmp = intel_de_read(dev_priv, DISPLAY_VER(dev_priv) >= 14 ? 4035 MTL_CHICKEN_TRANS(pipe_config->cpu_transcoder) : 4036 CHICKEN_TRANS(pipe_config->cpu_transcoder)); 4037 4038 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1; 4039 } else { 4040 /* no idea if this is correct */ 4041 pipe_config->framestart_delay = 1; 4042 } 4043 4044 out: 4045 intel_display_power_put_all_in_set(dev_priv, &crtc->hw_readout_power_domains); 4046 4047 return active; 4048 } 4049 4050 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state) 4051 { 4052 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4053 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4054 4055 if (!i915->display.funcs.display->get_pipe_config(crtc, crtc_state)) 4056 return false; 4057 4058 crtc_state->hw.active = true; 4059 4060 intel_crtc_readout_derived_state(crtc_state); 4061 4062 return true; 4063 } 4064 4065 /* VESA 640x480x72Hz mode to set on the pipe */ 4066 static const struct drm_display_mode load_detect_mode = { 4067 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, 4068 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 4069 }; 4070 4071 static int intel_modeset_disable_planes(struct drm_atomic_state *state, 4072 struct drm_crtc *crtc) 4073 { 4074 struct drm_plane *plane; 4075 struct drm_plane_state *plane_state; 4076 int ret, i; 4077 4078 ret = drm_atomic_add_affected_planes(state, crtc); 4079 if (ret) 4080 return ret; 4081 4082 for_each_new_plane_in_state(state, plane, plane_state, i) { 4083 if (plane_state->crtc != crtc) 4084 continue; 4085 4086 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL); 4087 if (ret) 4088 return ret; 4089 4090 drm_atomic_set_fb_for_plane(plane_state, NULL); 4091 } 4092 4093 return 0; 4094 } 4095 4096 int intel_get_load_detect_pipe(struct drm_connector *connector, 4097 struct intel_load_detect_pipe *old, 4098 struct drm_modeset_acquire_ctx *ctx) 4099 { 4100 struct intel_encoder *encoder = 4101 intel_attached_encoder(to_intel_connector(connector)); 4102 struct intel_crtc *possible_crtc; 4103 struct intel_crtc *crtc = NULL; 4104 struct drm_device *dev = encoder->base.dev; 4105 struct drm_i915_private *dev_priv = to_i915(dev); 4106 struct drm_mode_config *config = &dev->mode_config; 4107 struct drm_atomic_state *state = NULL, *restore_state = NULL; 4108 struct drm_connector_state *connector_state; 4109 struct intel_crtc_state *crtc_state; 4110 int ret; 4111 4112 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 4113 connector->base.id, connector->name, 4114 encoder->base.base.id, encoder->base.name); 4115 4116 old->restore_state = NULL; 4117 4118 drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex)); 4119 4120 /* 4121 * Algorithm gets a little messy: 4122 * 4123 * - if the connector already has an assigned crtc, use it (but make 4124 * sure it's on first) 4125 * 4126 * - try to find the first unused crtc that can drive this connector, 4127 * and use that if we find one 4128 */ 4129 4130 /* See if we already have a CRTC for this connector */ 4131 if (connector->state->crtc) { 4132 crtc = to_intel_crtc(connector->state->crtc); 4133 4134 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4135 if (ret) 4136 goto fail; 4137 4138 /* Make sure the crtc and connector are running */ 4139 goto found; 4140 } 4141 4142 /* Find an unused one (if possible) */ 4143 for_each_intel_crtc(dev, possible_crtc) { 4144 if (!(encoder->base.possible_crtcs & 4145 drm_crtc_mask(&possible_crtc->base))) 4146 continue; 4147 4148 ret = drm_modeset_lock(&possible_crtc->base.mutex, ctx); 4149 if (ret) 4150 goto fail; 4151 4152 if (possible_crtc->base.state->enable) { 4153 drm_modeset_unlock(&possible_crtc->base.mutex); 4154 continue; 4155 } 4156 4157 crtc = possible_crtc; 4158 break; 4159 } 4160 4161 /* 4162 * If we didn't find an unused CRTC, don't use any. 4163 */ 4164 if (!crtc) { 4165 drm_dbg_kms(&dev_priv->drm, 4166 "no pipe available for load-detect\n"); 4167 ret = -ENODEV; 4168 goto fail; 4169 } 4170 4171 found: 4172 state = drm_atomic_state_alloc(dev); 4173 restore_state = drm_atomic_state_alloc(dev); 4174 if (!state || !restore_state) { 4175 ret = -ENOMEM; 4176 goto fail; 4177 } 4178 4179 state->acquire_ctx = ctx; 4180 restore_state->acquire_ctx = ctx; 4181 4182 connector_state = drm_atomic_get_connector_state(state, connector); 4183 if (IS_ERR(connector_state)) { 4184 ret = PTR_ERR(connector_state); 4185 goto fail; 4186 } 4187 4188 ret = drm_atomic_set_crtc_for_connector(connector_state, &crtc->base); 4189 if (ret) 4190 goto fail; 4191 4192 crtc_state = intel_atomic_get_crtc_state(state, crtc); 4193 if (IS_ERR(crtc_state)) { 4194 ret = PTR_ERR(crtc_state); 4195 goto fail; 4196 } 4197 4198 crtc_state->uapi.active = true; 4199 4200 ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi, 4201 &load_detect_mode); 4202 if (ret) 4203 goto fail; 4204 4205 ret = intel_modeset_disable_planes(state, &crtc->base); 4206 if (ret) 4207 goto fail; 4208 4209 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); 4210 if (!ret) 4211 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, &crtc->base)); 4212 if (!ret) 4213 ret = drm_atomic_add_affected_planes(restore_state, &crtc->base); 4214 if (ret) { 4215 drm_dbg_kms(&dev_priv->drm, 4216 "Failed to create a copy of old state to restore: %i\n", 4217 ret); 4218 goto fail; 4219 } 4220 4221 ret = drm_atomic_commit(state); 4222 if (ret) { 4223 drm_dbg_kms(&dev_priv->drm, 4224 "failed to set mode on load-detect pipe\n"); 4225 goto fail; 4226 } 4227 4228 old->restore_state = restore_state; 4229 drm_atomic_state_put(state); 4230 4231 /* let the connector get through one full cycle before testing */ 4232 intel_crtc_wait_for_next_vblank(crtc); 4233 4234 return true; 4235 4236 fail: 4237 if (state) { 4238 drm_atomic_state_put(state); 4239 state = NULL; 4240 } 4241 if (restore_state) { 4242 drm_atomic_state_put(restore_state); 4243 restore_state = NULL; 4244 } 4245 4246 if (ret == -EDEADLK) 4247 return ret; 4248 4249 return false; 4250 } 4251 4252 void intel_release_load_detect_pipe(struct drm_connector *connector, 4253 struct intel_load_detect_pipe *old, 4254 struct drm_modeset_acquire_ctx *ctx) 4255 { 4256 struct intel_encoder *intel_encoder = 4257 intel_attached_encoder(to_intel_connector(connector)); 4258 struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev); 4259 struct drm_encoder *encoder = &intel_encoder->base; 4260 struct drm_atomic_state *state = old->restore_state; 4261 int ret; 4262 4263 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 4264 connector->base.id, connector->name, 4265 encoder->base.id, encoder->name); 4266 4267 if (!state) 4268 return; 4269 4270 ret = drm_atomic_helper_commit_duplicated_state(state, ctx); 4271 if (ret) 4272 drm_dbg_kms(&i915->drm, 4273 "Couldn't release load detect pipe: %i\n", ret); 4274 drm_atomic_state_put(state); 4275 } 4276 4277 static int i9xx_pll_refclk(struct drm_device *dev, 4278 const struct intel_crtc_state *pipe_config) 4279 { 4280 struct drm_i915_private *dev_priv = to_i915(dev); 4281 u32 dpll = pipe_config->dpll_hw_state.dpll; 4282 4283 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) 4284 return dev_priv->display.vbt.lvds_ssc_freq; 4285 else if (HAS_PCH_SPLIT(dev_priv)) 4286 return 120000; 4287 else if (DISPLAY_VER(dev_priv) != 2) 4288 return 96000; 4289 else 4290 return 48000; 4291 } 4292 4293 /* Returns the clock of the currently programmed mode of the given pipe. */ 4294 void i9xx_crtc_clock_get(struct intel_crtc *crtc, 4295 struct intel_crtc_state *pipe_config) 4296 { 4297 struct drm_device *dev = crtc->base.dev; 4298 struct drm_i915_private *dev_priv = to_i915(dev); 4299 u32 dpll = pipe_config->dpll_hw_state.dpll; 4300 u32 fp; 4301 struct dpll clock; 4302 int port_clock; 4303 int refclk = i9xx_pll_refclk(dev, pipe_config); 4304 4305 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 4306 fp = pipe_config->dpll_hw_state.fp0; 4307 else 4308 fp = pipe_config->dpll_hw_state.fp1; 4309 4310 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 4311 if (IS_PINEVIEW(dev_priv)) { 4312 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; 4313 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; 4314 } else { 4315 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 4316 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 4317 } 4318 4319 if (DISPLAY_VER(dev_priv) != 2) { 4320 if (IS_PINEVIEW(dev_priv)) 4321 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> 4322 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); 4323 else 4324 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> 4325 DPLL_FPA01_P1_POST_DIV_SHIFT); 4326 4327 switch (dpll & DPLL_MODE_MASK) { 4328 case DPLLB_MODE_DAC_SERIAL: 4329 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 4330 5 : 10; 4331 break; 4332 case DPLLB_MODE_LVDS: 4333 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 4334 7 : 14; 4335 break; 4336 default: 4337 drm_dbg_kms(&dev_priv->drm, 4338 "Unknown DPLL mode %08x in programmed " 4339 "mode\n", (int)(dpll & DPLL_MODE_MASK)); 4340 return; 4341 } 4342 4343 if (IS_PINEVIEW(dev_priv)) 4344 port_clock = pnv_calc_dpll_params(refclk, &clock); 4345 else 4346 port_clock = i9xx_calc_dpll_params(refclk, &clock); 4347 } else { 4348 enum pipe lvds_pipe; 4349 4350 if (IS_I85X(dev_priv) && 4351 intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) && 4352 lvds_pipe == crtc->pipe) { 4353 u32 lvds = intel_de_read(dev_priv, LVDS); 4354 4355 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 4356 DPLL_FPA01_P1_POST_DIV_SHIFT); 4357 4358 if (lvds & LVDS_CLKB_POWER_UP) 4359 clock.p2 = 7; 4360 else 4361 clock.p2 = 14; 4362 } else { 4363 if (dpll & PLL_P1_DIVIDE_BY_TWO) 4364 clock.p1 = 2; 4365 else { 4366 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 4367 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 4368 } 4369 if (dpll & PLL_P2_DIVIDE_BY_4) 4370 clock.p2 = 4; 4371 else 4372 clock.p2 = 2; 4373 } 4374 4375 port_clock = i9xx_calc_dpll_params(refclk, &clock); 4376 } 4377 4378 /* 4379 * This value includes pixel_multiplier. We will use 4380 * port_clock to compute adjusted_mode.crtc_clock in the 4381 * encoder's get_config() function. 4382 */ 4383 pipe_config->port_clock = port_clock; 4384 } 4385 4386 int intel_dotclock_calculate(int link_freq, 4387 const struct intel_link_m_n *m_n) 4388 { 4389 /* 4390 * The calculation for the data clock is: 4391 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp 4392 * But we want to avoid losing precison if possible, so: 4393 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) 4394 * 4395 * and the link clock is simpler: 4396 * link_clock = (m * link_clock) / n 4397 */ 4398 4399 if (!m_n->link_n) 4400 return 0; 4401 4402 return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq), 4403 m_n->link_n); 4404 } 4405 4406 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config) 4407 { 4408 int dotclock; 4409 4410 if (intel_crtc_has_dp_encoder(pipe_config)) 4411 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 4412 &pipe_config->dp_m_n); 4413 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) 4414 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24, 4415 pipe_config->pipe_bpp); 4416 else 4417 dotclock = pipe_config->port_clock; 4418 4419 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 4420 !intel_crtc_has_dp_encoder(pipe_config)) 4421 dotclock *= 2; 4422 4423 if (pipe_config->pixel_multiplier) 4424 dotclock /= pipe_config->pixel_multiplier; 4425 4426 return dotclock; 4427 } 4428 4429 /* Returns the currently programmed mode of the given encoder. */ 4430 struct drm_display_mode * 4431 intel_encoder_current_mode(struct intel_encoder *encoder) 4432 { 4433 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4434 struct intel_crtc_state *crtc_state; 4435 struct drm_display_mode *mode; 4436 struct intel_crtc *crtc; 4437 enum pipe pipe; 4438 4439 if (!encoder->get_hw_state(encoder, &pipe)) 4440 return NULL; 4441 4442 crtc = intel_crtc_for_pipe(dev_priv, pipe); 4443 4444 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 4445 if (!mode) 4446 return NULL; 4447 4448 crtc_state = intel_crtc_state_alloc(crtc); 4449 if (!crtc_state) { 4450 kfree(mode); 4451 return NULL; 4452 } 4453 4454 if (!intel_crtc_get_pipe_config(crtc_state)) { 4455 kfree(crtc_state); 4456 kfree(mode); 4457 return NULL; 4458 } 4459 4460 intel_encoder_get_config(encoder, crtc_state); 4461 4462 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode); 4463 4464 kfree(crtc_state); 4465 4466 return mode; 4467 } 4468 4469 static bool encoders_cloneable(const struct intel_encoder *a, 4470 const struct intel_encoder *b) 4471 { 4472 /* masks could be asymmetric, so check both ways */ 4473 return a == b || (a->cloneable & BIT(b->type) && 4474 b->cloneable & BIT(a->type)); 4475 } 4476 4477 static bool check_single_encoder_cloning(struct intel_atomic_state *state, 4478 struct intel_crtc *crtc, 4479 struct intel_encoder *encoder) 4480 { 4481 struct intel_encoder *source_encoder; 4482 struct drm_connector *connector; 4483 struct drm_connector_state *connector_state; 4484 int i; 4485 4486 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4487 if (connector_state->crtc != &crtc->base) 4488 continue; 4489 4490 source_encoder = 4491 to_intel_encoder(connector_state->best_encoder); 4492 if (!encoders_cloneable(encoder, source_encoder)) 4493 return false; 4494 } 4495 4496 return true; 4497 } 4498 4499 static int icl_add_linked_planes(struct intel_atomic_state *state) 4500 { 4501 struct intel_plane *plane, *linked; 4502 struct intel_plane_state *plane_state, *linked_plane_state; 4503 int i; 4504 4505 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4506 linked = plane_state->planar_linked_plane; 4507 4508 if (!linked) 4509 continue; 4510 4511 linked_plane_state = intel_atomic_get_plane_state(state, linked); 4512 if (IS_ERR(linked_plane_state)) 4513 return PTR_ERR(linked_plane_state); 4514 4515 drm_WARN_ON(state->base.dev, 4516 linked_plane_state->planar_linked_plane != plane); 4517 drm_WARN_ON(state->base.dev, 4518 linked_plane_state->planar_slave == plane_state->planar_slave); 4519 } 4520 4521 return 0; 4522 } 4523 4524 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state) 4525 { 4526 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4527 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4528 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 4529 struct intel_plane *plane, *linked; 4530 struct intel_plane_state *plane_state; 4531 int i; 4532 4533 if (DISPLAY_VER(dev_priv) < 11) 4534 return 0; 4535 4536 /* 4537 * Destroy all old plane links and make the slave plane invisible 4538 * in the crtc_state->active_planes mask. 4539 */ 4540 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4541 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane) 4542 continue; 4543 4544 plane_state->planar_linked_plane = NULL; 4545 if (plane_state->planar_slave && !plane_state->uapi.visible) { 4546 crtc_state->enabled_planes &= ~BIT(plane->id); 4547 crtc_state->active_planes &= ~BIT(plane->id); 4548 crtc_state->update_planes |= BIT(plane->id); 4549 crtc_state->data_rate[plane->id] = 0; 4550 crtc_state->rel_data_rate[plane->id] = 0; 4551 } 4552 4553 plane_state->planar_slave = false; 4554 } 4555 4556 if (!crtc_state->nv12_planes) 4557 return 0; 4558 4559 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4560 struct intel_plane_state *linked_state = NULL; 4561 4562 if (plane->pipe != crtc->pipe || 4563 !(crtc_state->nv12_planes & BIT(plane->id))) 4564 continue; 4565 4566 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) { 4567 if (!icl_is_nv12_y_plane(dev_priv, linked->id)) 4568 continue; 4569 4570 if (crtc_state->active_planes & BIT(linked->id)) 4571 continue; 4572 4573 linked_state = intel_atomic_get_plane_state(state, linked); 4574 if (IS_ERR(linked_state)) 4575 return PTR_ERR(linked_state); 4576 4577 break; 4578 } 4579 4580 if (!linked_state) { 4581 drm_dbg_kms(&dev_priv->drm, 4582 "Need %d free Y planes for planar YUV\n", 4583 hweight8(crtc_state->nv12_planes)); 4584 4585 return -EINVAL; 4586 } 4587 4588 plane_state->planar_linked_plane = linked; 4589 4590 linked_state->planar_slave = true; 4591 linked_state->planar_linked_plane = plane; 4592 crtc_state->enabled_planes |= BIT(linked->id); 4593 crtc_state->active_planes |= BIT(linked->id); 4594 crtc_state->update_planes |= BIT(linked->id); 4595 crtc_state->data_rate[linked->id] = 4596 crtc_state->data_rate_y[plane->id]; 4597 crtc_state->rel_data_rate[linked->id] = 4598 crtc_state->rel_data_rate_y[plane->id]; 4599 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n", 4600 linked->base.name, plane->base.name); 4601 4602 /* Copy parameters to slave plane */ 4603 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE; 4604 linked_state->color_ctl = plane_state->color_ctl; 4605 linked_state->view = plane_state->view; 4606 linked_state->decrypt = plane_state->decrypt; 4607 4608 intel_plane_copy_hw_state(linked_state, plane_state); 4609 linked_state->uapi.src = plane_state->uapi.src; 4610 linked_state->uapi.dst = plane_state->uapi.dst; 4611 4612 if (icl_is_hdr_plane(dev_priv, plane->id)) { 4613 if (linked->id == PLANE_SPRITE5) 4614 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL; 4615 else if (linked->id == PLANE_SPRITE4) 4616 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL; 4617 else if (linked->id == PLANE_SPRITE3) 4618 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL; 4619 else if (linked->id == PLANE_SPRITE2) 4620 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL; 4621 else 4622 MISSING_CASE(linked->id); 4623 } 4624 } 4625 4626 return 0; 4627 } 4628 4629 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state) 4630 { 4631 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 4632 struct intel_atomic_state *state = 4633 to_intel_atomic_state(new_crtc_state->uapi.state); 4634 const struct intel_crtc_state *old_crtc_state = 4635 intel_atomic_get_old_crtc_state(state, crtc); 4636 4637 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes; 4638 } 4639 4640 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) 4641 { 4642 const struct drm_display_mode *pipe_mode = 4643 &crtc_state->hw.pipe_mode; 4644 int linetime_wm; 4645 4646 if (!crtc_state->hw.enable) 4647 return 0; 4648 4649 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4650 pipe_mode->crtc_clock); 4651 4652 return min(linetime_wm, 0x1ff); 4653 } 4654 4655 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, 4656 const struct intel_cdclk_state *cdclk_state) 4657 { 4658 const struct drm_display_mode *pipe_mode = 4659 &crtc_state->hw.pipe_mode; 4660 int linetime_wm; 4661 4662 if (!crtc_state->hw.enable) 4663 return 0; 4664 4665 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4666 cdclk_state->logical.cdclk); 4667 4668 return min(linetime_wm, 0x1ff); 4669 } 4670 4671 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) 4672 { 4673 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4674 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4675 const struct drm_display_mode *pipe_mode = 4676 &crtc_state->hw.pipe_mode; 4677 int linetime_wm; 4678 4679 if (!crtc_state->hw.enable) 4680 return 0; 4681 4682 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8, 4683 crtc_state->pixel_rate); 4684 4685 /* Display WA #1135: BXT:ALL GLK:ALL */ 4686 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 4687 skl_watermark_ipc_enabled(dev_priv)) 4688 linetime_wm /= 2; 4689 4690 return min(linetime_wm, 0x1ff); 4691 } 4692 4693 static int hsw_compute_linetime_wm(struct intel_atomic_state *state, 4694 struct intel_crtc *crtc) 4695 { 4696 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4697 struct intel_crtc_state *crtc_state = 4698 intel_atomic_get_new_crtc_state(state, crtc); 4699 const struct intel_cdclk_state *cdclk_state; 4700 4701 if (DISPLAY_VER(dev_priv) >= 9) 4702 crtc_state->linetime = skl_linetime_wm(crtc_state); 4703 else 4704 crtc_state->linetime = hsw_linetime_wm(crtc_state); 4705 4706 if (!hsw_crtc_supports_ips(crtc)) 4707 return 0; 4708 4709 cdclk_state = intel_atomic_get_cdclk_state(state); 4710 if (IS_ERR(cdclk_state)) 4711 return PTR_ERR(cdclk_state); 4712 4713 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state, 4714 cdclk_state); 4715 4716 return 0; 4717 } 4718 4719 static int intel_crtc_atomic_check(struct intel_atomic_state *state, 4720 struct intel_crtc *crtc) 4721 { 4722 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4723 struct intel_crtc_state *crtc_state = 4724 intel_atomic_get_new_crtc_state(state, crtc); 4725 int ret; 4726 4727 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) && 4728 intel_crtc_needs_modeset(crtc_state) && 4729 !crtc_state->hw.active) 4730 crtc_state->update_wm_post = true; 4731 4732 if (intel_crtc_needs_modeset(crtc_state)) { 4733 ret = intel_dpll_crtc_get_shared_dpll(state, crtc); 4734 if (ret) 4735 return ret; 4736 } 4737 4738 /* 4739 * May need to update pipe gamma enable bits 4740 * when C8 planes are getting enabled/disabled. 4741 */ 4742 if (c8_planes_changed(crtc_state)) 4743 crtc_state->uapi.color_mgmt_changed = true; 4744 4745 if (intel_crtc_needs_color_update(crtc_state)) { 4746 ret = intel_color_check(crtc_state); 4747 if (ret) 4748 return ret; 4749 } 4750 4751 ret = intel_compute_pipe_wm(state, crtc); 4752 if (ret) { 4753 drm_dbg_kms(&dev_priv->drm, 4754 "Target pipe watermarks are invalid\n"); 4755 return ret; 4756 } 4757 4758 /* 4759 * Calculate 'intermediate' watermarks that satisfy both the 4760 * old state and the new state. We can program these 4761 * immediately. 4762 */ 4763 ret = intel_compute_intermediate_wm(state, crtc); 4764 if (ret) { 4765 drm_dbg_kms(&dev_priv->drm, 4766 "No valid intermediate pipe watermarks are possible\n"); 4767 return ret; 4768 } 4769 4770 if (DISPLAY_VER(dev_priv) >= 9) { 4771 if (intel_crtc_needs_modeset(crtc_state) || 4772 intel_crtc_needs_fastset(crtc_state)) { 4773 ret = skl_update_scaler_crtc(crtc_state); 4774 if (ret) 4775 return ret; 4776 } 4777 4778 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state); 4779 if (ret) 4780 return ret; 4781 } 4782 4783 if (HAS_IPS(dev_priv)) { 4784 ret = hsw_ips_compute_config(state, crtc); 4785 if (ret) 4786 return ret; 4787 } 4788 4789 if (DISPLAY_VER(dev_priv) >= 9 || 4790 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 4791 ret = hsw_compute_linetime_wm(state, crtc); 4792 if (ret) 4793 return ret; 4794 4795 } 4796 4797 ret = intel_psr2_sel_fetch_update(state, crtc); 4798 if (ret) 4799 return ret; 4800 4801 return 0; 4802 } 4803 4804 static int 4805 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state, 4806 struct intel_crtc_state *crtc_state) 4807 { 4808 struct drm_connector *connector = conn_state->connector; 4809 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 4810 const struct drm_display_info *info = &connector->display_info; 4811 int bpp; 4812 4813 switch (conn_state->max_bpc) { 4814 case 6 ... 7: 4815 bpp = 6 * 3; 4816 break; 4817 case 8 ... 9: 4818 bpp = 8 * 3; 4819 break; 4820 case 10 ... 11: 4821 bpp = 10 * 3; 4822 break; 4823 case 12 ... 16: 4824 bpp = 12 * 3; 4825 break; 4826 default: 4827 MISSING_CASE(conn_state->max_bpc); 4828 return -EINVAL; 4829 } 4830 4831 if (bpp < crtc_state->pipe_bpp) { 4832 drm_dbg_kms(&i915->drm, 4833 "[CONNECTOR:%d:%s] Limiting display bpp to %d " 4834 "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n", 4835 connector->base.id, connector->name, 4836 bpp, 3 * info->bpc, 4837 3 * conn_state->max_requested_bpc, 4838 crtc_state->pipe_bpp); 4839 4840 crtc_state->pipe_bpp = bpp; 4841 } 4842 4843 return 0; 4844 } 4845 4846 static int 4847 compute_baseline_pipe_bpp(struct intel_atomic_state *state, 4848 struct intel_crtc *crtc) 4849 { 4850 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4851 struct intel_crtc_state *crtc_state = 4852 intel_atomic_get_new_crtc_state(state, crtc); 4853 struct drm_connector *connector; 4854 struct drm_connector_state *connector_state; 4855 int bpp, i; 4856 4857 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 4858 IS_CHERRYVIEW(dev_priv))) 4859 bpp = 10*3; 4860 else if (DISPLAY_VER(dev_priv) >= 5) 4861 bpp = 12*3; 4862 else 4863 bpp = 8*3; 4864 4865 crtc_state->pipe_bpp = bpp; 4866 4867 /* Clamp display bpp to connector max bpp */ 4868 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4869 int ret; 4870 4871 if (connector_state->crtc != &crtc->base) 4872 continue; 4873 4874 ret = compute_sink_pipe_bpp(connector_state, crtc_state); 4875 if (ret) 4876 return ret; 4877 } 4878 4879 return 0; 4880 } 4881 4882 static bool check_digital_port_conflicts(struct intel_atomic_state *state) 4883 { 4884 struct drm_device *dev = state->base.dev; 4885 struct drm_connector *connector; 4886 struct drm_connector_list_iter conn_iter; 4887 unsigned int used_ports = 0; 4888 unsigned int used_mst_ports = 0; 4889 bool ret = true; 4890 4891 /* 4892 * We're going to peek into connector->state, 4893 * hence connection_mutex must be held. 4894 */ 4895 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex); 4896 4897 /* 4898 * Walk the connector list instead of the encoder 4899 * list to detect the problem on ddi platforms 4900 * where there's just one encoder per digital port. 4901 */ 4902 drm_connector_list_iter_begin(dev, &conn_iter); 4903 drm_for_each_connector_iter(connector, &conn_iter) { 4904 struct drm_connector_state *connector_state; 4905 struct intel_encoder *encoder; 4906 4907 connector_state = 4908 drm_atomic_get_new_connector_state(&state->base, 4909 connector); 4910 if (!connector_state) 4911 connector_state = connector->state; 4912 4913 if (!connector_state->best_encoder) 4914 continue; 4915 4916 encoder = to_intel_encoder(connector_state->best_encoder); 4917 4918 drm_WARN_ON(dev, !connector_state->crtc); 4919 4920 switch (encoder->type) { 4921 case INTEL_OUTPUT_DDI: 4922 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev)))) 4923 break; 4924 fallthrough; 4925 case INTEL_OUTPUT_DP: 4926 case INTEL_OUTPUT_HDMI: 4927 case INTEL_OUTPUT_EDP: 4928 /* the same port mustn't appear more than once */ 4929 if (used_ports & BIT(encoder->port)) 4930 ret = false; 4931 4932 used_ports |= BIT(encoder->port); 4933 break; 4934 case INTEL_OUTPUT_DP_MST: 4935 used_mst_ports |= 4936 1 << encoder->port; 4937 break; 4938 default: 4939 break; 4940 } 4941 } 4942 drm_connector_list_iter_end(&conn_iter); 4943 4944 /* can't mix MST and SST/HDMI on the same port */ 4945 if (used_ports & used_mst_ports) 4946 return false; 4947 4948 return ret; 4949 } 4950 4951 static void 4952 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state, 4953 struct intel_crtc *crtc) 4954 { 4955 struct intel_crtc_state *crtc_state = 4956 intel_atomic_get_new_crtc_state(state, crtc); 4957 4958 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 4959 4960 drm_property_replace_blob(&crtc_state->hw.degamma_lut, 4961 crtc_state->uapi.degamma_lut); 4962 drm_property_replace_blob(&crtc_state->hw.gamma_lut, 4963 crtc_state->uapi.gamma_lut); 4964 drm_property_replace_blob(&crtc_state->hw.ctm, 4965 crtc_state->uapi.ctm); 4966 } 4967 4968 static void 4969 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state, 4970 struct intel_crtc *crtc) 4971 { 4972 struct intel_crtc_state *crtc_state = 4973 intel_atomic_get_new_crtc_state(state, crtc); 4974 4975 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 4976 4977 crtc_state->hw.enable = crtc_state->uapi.enable; 4978 crtc_state->hw.active = crtc_state->uapi.active; 4979 drm_mode_copy(&crtc_state->hw.mode, 4980 &crtc_state->uapi.mode); 4981 drm_mode_copy(&crtc_state->hw.adjusted_mode, 4982 &crtc_state->uapi.adjusted_mode); 4983 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter; 4984 4985 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 4986 } 4987 4988 static void 4989 copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state, 4990 struct intel_crtc *slave_crtc) 4991 { 4992 struct intel_crtc_state *slave_crtc_state = 4993 intel_atomic_get_new_crtc_state(state, slave_crtc); 4994 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 4995 const struct intel_crtc_state *master_crtc_state = 4996 intel_atomic_get_new_crtc_state(state, master_crtc); 4997 4998 drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut, 4999 master_crtc_state->hw.degamma_lut); 5000 drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut, 5001 master_crtc_state->hw.gamma_lut); 5002 drm_property_replace_blob(&slave_crtc_state->hw.ctm, 5003 master_crtc_state->hw.ctm); 5004 5005 slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed; 5006 } 5007 5008 static int 5009 copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state, 5010 struct intel_crtc *slave_crtc) 5011 { 5012 struct intel_crtc_state *slave_crtc_state = 5013 intel_atomic_get_new_crtc_state(state, slave_crtc); 5014 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 5015 const struct intel_crtc_state *master_crtc_state = 5016 intel_atomic_get_new_crtc_state(state, master_crtc); 5017 struct intel_crtc_state *saved_state; 5018 5019 WARN_ON(master_crtc_state->bigjoiner_pipes != 5020 slave_crtc_state->bigjoiner_pipes); 5021 5022 saved_state = kmemdup(master_crtc_state, sizeof(*saved_state), GFP_KERNEL); 5023 if (!saved_state) 5024 return -ENOMEM; 5025 5026 /* preserve some things from the slave's original crtc state */ 5027 saved_state->uapi = slave_crtc_state->uapi; 5028 saved_state->scaler_state = slave_crtc_state->scaler_state; 5029 saved_state->shared_dpll = slave_crtc_state->shared_dpll; 5030 saved_state->dpll_hw_state = slave_crtc_state->dpll_hw_state; 5031 saved_state->crc_enabled = slave_crtc_state->crc_enabled; 5032 5033 intel_crtc_free_hw_state(slave_crtc_state); 5034 memcpy(slave_crtc_state, saved_state, sizeof(*slave_crtc_state)); 5035 kfree(saved_state); 5036 5037 /* Re-init hw state */ 5038 memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw)); 5039 slave_crtc_state->hw.enable = master_crtc_state->hw.enable; 5040 slave_crtc_state->hw.active = master_crtc_state->hw.active; 5041 drm_mode_copy(&slave_crtc_state->hw.mode, 5042 &master_crtc_state->hw.mode); 5043 drm_mode_copy(&slave_crtc_state->hw.pipe_mode, 5044 &master_crtc_state->hw.pipe_mode); 5045 drm_mode_copy(&slave_crtc_state->hw.adjusted_mode, 5046 &master_crtc_state->hw.adjusted_mode); 5047 slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter; 5048 5049 copy_bigjoiner_crtc_state_nomodeset(state, slave_crtc); 5050 5051 slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed; 5052 slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed; 5053 slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed; 5054 5055 WARN_ON(master_crtc_state->bigjoiner_pipes != 5056 slave_crtc_state->bigjoiner_pipes); 5057 5058 return 0; 5059 } 5060 5061 static int 5062 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state, 5063 struct intel_crtc *crtc) 5064 { 5065 struct intel_crtc_state *crtc_state = 5066 intel_atomic_get_new_crtc_state(state, crtc); 5067 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5068 struct intel_crtc_state *saved_state; 5069 5070 saved_state = intel_crtc_state_alloc(crtc); 5071 if (!saved_state) 5072 return -ENOMEM; 5073 5074 /* free the old crtc_state->hw members */ 5075 intel_crtc_free_hw_state(crtc_state); 5076 5077 /* FIXME: before the switch to atomic started, a new pipe_config was 5078 * kzalloc'd. Code that depends on any field being zero should be 5079 * fixed, so that the crtc_state can be safely duplicated. For now, 5080 * only fields that are know to not cause problems are preserved. */ 5081 5082 saved_state->uapi = crtc_state->uapi; 5083 saved_state->inherited = crtc_state->inherited; 5084 saved_state->scaler_state = crtc_state->scaler_state; 5085 saved_state->shared_dpll = crtc_state->shared_dpll; 5086 saved_state->dpll_hw_state = crtc_state->dpll_hw_state; 5087 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, 5088 sizeof(saved_state->icl_port_dplls)); 5089 saved_state->crc_enabled = crtc_state->crc_enabled; 5090 if (IS_G4X(dev_priv) || 5091 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5092 saved_state->wm = crtc_state->wm; 5093 5094 memcpy(crtc_state, saved_state, sizeof(*crtc_state)); 5095 kfree(saved_state); 5096 5097 intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc); 5098 5099 return 0; 5100 } 5101 5102 static int 5103 intel_modeset_pipe_config(struct intel_atomic_state *state, 5104 struct intel_crtc *crtc) 5105 { 5106 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 5107 struct intel_crtc_state *crtc_state = 5108 intel_atomic_get_new_crtc_state(state, crtc); 5109 struct drm_connector *connector; 5110 struct drm_connector_state *connector_state; 5111 int pipe_src_w, pipe_src_h; 5112 int base_bpp, ret, i; 5113 bool retry = true; 5114 5115 crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe; 5116 5117 crtc_state->framestart_delay = 1; 5118 5119 /* 5120 * Sanitize sync polarity flags based on requested ones. If neither 5121 * positive or negative polarity is requested, treat this as meaning 5122 * negative polarity. 5123 */ 5124 if (!(crtc_state->hw.adjusted_mode.flags & 5125 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) 5126 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; 5127 5128 if (!(crtc_state->hw.adjusted_mode.flags & 5129 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 5130 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; 5131 5132 ret = compute_baseline_pipe_bpp(state, crtc); 5133 if (ret) 5134 return ret; 5135 5136 base_bpp = crtc_state->pipe_bpp; 5137 5138 /* 5139 * Determine the real pipe dimensions. Note that stereo modes can 5140 * increase the actual pipe size due to the frame doubling and 5141 * insertion of additional space for blanks between the frame. This 5142 * is stored in the crtc timings. We use the requested mode to do this 5143 * computation to clearly distinguish it from the adjusted mode, which 5144 * can be changed by the connectors in the below retry loop. 5145 */ 5146 drm_mode_get_hv_timing(&crtc_state->hw.mode, 5147 &pipe_src_w, &pipe_src_h); 5148 drm_rect_init(&crtc_state->pipe_src, 0, 0, 5149 pipe_src_w, pipe_src_h); 5150 5151 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5152 struct intel_encoder *encoder = 5153 to_intel_encoder(connector_state->best_encoder); 5154 5155 if (connector_state->crtc != &crtc->base) 5156 continue; 5157 5158 if (!check_single_encoder_cloning(state, crtc, encoder)) { 5159 drm_dbg_kms(&i915->drm, 5160 "[ENCODER:%d:%s] rejecting invalid cloning configuration\n", 5161 encoder->base.base.id, encoder->base.name); 5162 return -EINVAL; 5163 } 5164 5165 /* 5166 * Determine output_types before calling the .compute_config() 5167 * hooks so that the hooks can use this information safely. 5168 */ 5169 if (encoder->compute_output_type) 5170 crtc_state->output_types |= 5171 BIT(encoder->compute_output_type(encoder, crtc_state, 5172 connector_state)); 5173 else 5174 crtc_state->output_types |= BIT(encoder->type); 5175 } 5176 5177 encoder_retry: 5178 /* Ensure the port clock defaults are reset when retrying. */ 5179 crtc_state->port_clock = 0; 5180 crtc_state->pixel_multiplier = 1; 5181 5182 /* Fill in default crtc timings, allow encoders to overwrite them. */ 5183 drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode, 5184 CRTC_STEREO_DOUBLE); 5185 5186 /* Pass our mode to the connectors and the CRTC to give them a chance to 5187 * adjust it according to limitations or connector properties, and also 5188 * a chance to reject the mode entirely. 5189 */ 5190 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 5191 struct intel_encoder *encoder = 5192 to_intel_encoder(connector_state->best_encoder); 5193 5194 if (connector_state->crtc != &crtc->base) 5195 continue; 5196 5197 ret = encoder->compute_config(encoder, crtc_state, 5198 connector_state); 5199 if (ret == -EDEADLK) 5200 return ret; 5201 if (ret < 0) { 5202 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n", 5203 encoder->base.base.id, encoder->base.name, ret); 5204 return ret; 5205 } 5206 } 5207 5208 /* Set default port clock if not overwritten by the encoder. Needs to be 5209 * done afterwards in case the encoder adjusts the mode. */ 5210 if (!crtc_state->port_clock) 5211 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock 5212 * crtc_state->pixel_multiplier; 5213 5214 ret = intel_crtc_compute_config(state, crtc); 5215 if (ret == -EDEADLK) 5216 return ret; 5217 if (ret == -EAGAIN) { 5218 if (drm_WARN(&i915->drm, !retry, 5219 "[CRTC:%d:%s] loop in pipe configuration computation\n", 5220 crtc->base.base.id, crtc->base.name)) 5221 return -EINVAL; 5222 5223 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] bw constrained, retrying\n", 5224 crtc->base.base.id, crtc->base.name); 5225 retry = false; 5226 goto encoder_retry; 5227 } 5228 if (ret < 0) { 5229 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n", 5230 crtc->base.base.id, crtc->base.name, ret); 5231 return ret; 5232 } 5233 5234 /* Dithering seems to not pass-through bits correctly when it should, so 5235 * only enable it on 6bpc panels and when its not a compliance 5236 * test requesting 6bpc video pattern. 5237 */ 5238 crtc_state->dither = (crtc_state->pipe_bpp == 6*3) && 5239 !crtc_state->dither_force_disable; 5240 drm_dbg_kms(&i915->drm, 5241 "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n", 5242 crtc->base.base.id, crtc->base.name, 5243 base_bpp, crtc_state->pipe_bpp, crtc_state->dither); 5244 5245 return 0; 5246 } 5247 5248 static int 5249 intel_modeset_pipe_config_late(struct intel_atomic_state *state, 5250 struct intel_crtc *crtc) 5251 { 5252 struct intel_crtc_state *crtc_state = 5253 intel_atomic_get_new_crtc_state(state, crtc); 5254 struct drm_connector_state *conn_state; 5255 struct drm_connector *connector; 5256 int i; 5257 5258 intel_bigjoiner_adjust_pipe_src(crtc_state); 5259 5260 for_each_new_connector_in_state(&state->base, connector, 5261 conn_state, i) { 5262 struct intel_encoder *encoder = 5263 to_intel_encoder(conn_state->best_encoder); 5264 int ret; 5265 5266 if (conn_state->crtc != &crtc->base || 5267 !encoder->compute_config_late) 5268 continue; 5269 5270 ret = encoder->compute_config_late(encoder, crtc_state, 5271 conn_state); 5272 if (ret) 5273 return ret; 5274 } 5275 5276 return 0; 5277 } 5278 5279 bool intel_fuzzy_clock_check(int clock1, int clock2) 5280 { 5281 int diff; 5282 5283 if (clock1 == clock2) 5284 return true; 5285 5286 if (!clock1 || !clock2) 5287 return false; 5288 5289 diff = abs(clock1 - clock2); 5290 5291 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) 5292 return true; 5293 5294 return false; 5295 } 5296 5297 static bool 5298 intel_compare_link_m_n(const struct intel_link_m_n *m_n, 5299 const struct intel_link_m_n *m2_n2) 5300 { 5301 return m_n->tu == m2_n2->tu && 5302 m_n->data_m == m2_n2->data_m && 5303 m_n->data_n == m2_n2->data_n && 5304 m_n->link_m == m2_n2->link_m && 5305 m_n->link_n == m2_n2->link_n; 5306 } 5307 5308 static bool 5309 intel_compare_infoframe(const union hdmi_infoframe *a, 5310 const union hdmi_infoframe *b) 5311 { 5312 return memcmp(a, b, sizeof(*a)) == 0; 5313 } 5314 5315 static bool 5316 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a, 5317 const struct drm_dp_vsc_sdp *b) 5318 { 5319 return memcmp(a, b, sizeof(*a)) == 0; 5320 } 5321 5322 static bool 5323 intel_compare_buffer(const u8 *a, const u8 *b, size_t len) 5324 { 5325 return memcmp(a, b, len) == 0; 5326 } 5327 5328 static void 5329 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv, 5330 bool fastset, const char *name, 5331 const union hdmi_infoframe *a, 5332 const union hdmi_infoframe *b) 5333 { 5334 if (fastset) { 5335 if (!drm_debug_enabled(DRM_UT_KMS)) 5336 return; 5337 5338 drm_dbg_kms(&dev_priv->drm, 5339 "fastset mismatch in %s infoframe\n", name); 5340 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 5341 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a); 5342 drm_dbg_kms(&dev_priv->drm, "found:\n"); 5343 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b); 5344 } else { 5345 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name); 5346 drm_err(&dev_priv->drm, "expected:\n"); 5347 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a); 5348 drm_err(&dev_priv->drm, "found:\n"); 5349 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b); 5350 } 5351 } 5352 5353 static void 5354 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv, 5355 bool fastset, const char *name, 5356 const struct drm_dp_vsc_sdp *a, 5357 const struct drm_dp_vsc_sdp *b) 5358 { 5359 if (fastset) { 5360 if (!drm_debug_enabled(DRM_UT_KMS)) 5361 return; 5362 5363 drm_dbg_kms(&dev_priv->drm, 5364 "fastset mismatch in %s dp sdp\n", name); 5365 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 5366 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a); 5367 drm_dbg_kms(&dev_priv->drm, "found:\n"); 5368 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b); 5369 } else { 5370 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name); 5371 drm_err(&dev_priv->drm, "expected:\n"); 5372 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a); 5373 drm_err(&dev_priv->drm, "found:\n"); 5374 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b); 5375 } 5376 } 5377 5378 /* Returns the length up to and including the last differing byte */ 5379 static size_t 5380 memcmp_diff_len(const u8 *a, const u8 *b, size_t len) 5381 { 5382 int i; 5383 5384 for (i = len - 1; i >= 0; i--) { 5385 if (a[i] != b[i]) 5386 return i + 1; 5387 } 5388 5389 return 0; 5390 } 5391 5392 static void 5393 pipe_config_buffer_mismatch(struct drm_i915_private *dev_priv, 5394 bool fastset, const char *name, 5395 const u8 *a, const u8 *b, size_t len) 5396 { 5397 if (fastset) { 5398 if (!drm_debug_enabled(DRM_UT_KMS)) 5399 return; 5400 5401 /* only dump up to the last difference */ 5402 len = memcmp_diff_len(a, b, len); 5403 5404 drm_dbg_kms(&dev_priv->drm, 5405 "fastset mismatch in %s buffer\n", name); 5406 print_hex_dump(KERN_DEBUG, "expected: ", DUMP_PREFIX_NONE, 5407 16, 0, a, len, false); 5408 print_hex_dump(KERN_DEBUG, "found: ", DUMP_PREFIX_NONE, 5409 16, 0, b, len, false); 5410 } else { 5411 /* only dump up to the last difference */ 5412 len = memcmp_diff_len(a, b, len); 5413 5414 drm_err(&dev_priv->drm, "mismatch in %s buffer\n", name); 5415 print_hex_dump(KERN_ERR, "expected: ", DUMP_PREFIX_NONE, 5416 16, 0, a, len, false); 5417 print_hex_dump(KERN_ERR, "found: ", DUMP_PREFIX_NONE, 5418 16, 0, b, len, false); 5419 } 5420 } 5421 5422 static void __printf(4, 5) 5423 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc, 5424 const char *name, const char *format, ...) 5425 { 5426 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 5427 struct va_format vaf; 5428 va_list args; 5429 5430 va_start(args, format); 5431 vaf.fmt = format; 5432 vaf.va = &args; 5433 5434 if (fastset) 5435 drm_dbg_kms(&i915->drm, 5436 "[CRTC:%d:%s] fastset mismatch in %s %pV\n", 5437 crtc->base.base.id, crtc->base.name, name, &vaf); 5438 else 5439 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n", 5440 crtc->base.base.id, crtc->base.name, name, &vaf); 5441 5442 va_end(args); 5443 } 5444 5445 static bool fastboot_enabled(struct drm_i915_private *dev_priv) 5446 { 5447 if (dev_priv->params.fastboot != -1) 5448 return dev_priv->params.fastboot; 5449 5450 /* Enable fastboot by default on Skylake and newer */ 5451 if (DISPLAY_VER(dev_priv) >= 9) 5452 return true; 5453 5454 /* Enable fastboot by default on VLV and CHV */ 5455 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5456 return true; 5457 5458 /* Disabled by default on all others */ 5459 return false; 5460 } 5461 5462 bool 5463 intel_pipe_config_compare(const struct intel_crtc_state *current_config, 5464 const struct intel_crtc_state *pipe_config, 5465 bool fastset) 5466 { 5467 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev); 5468 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 5469 bool ret = true; 5470 bool fixup_inherited = fastset && 5471 current_config->inherited && !pipe_config->inherited; 5472 5473 if (fixup_inherited && !fastboot_enabled(dev_priv)) { 5474 drm_dbg_kms(&dev_priv->drm, 5475 "initial modeset and fastboot not set\n"); 5476 ret = false; 5477 } 5478 5479 #define PIPE_CONF_CHECK_X(name) do { \ 5480 if (current_config->name != pipe_config->name) { \ 5481 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5482 "(expected 0x%08x, found 0x%08x)", \ 5483 current_config->name, \ 5484 pipe_config->name); \ 5485 ret = false; \ 5486 } \ 5487 } while (0) 5488 5489 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \ 5490 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \ 5491 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5492 "(expected 0x%08x, found 0x%08x)", \ 5493 current_config->name & (mask), \ 5494 pipe_config->name & (mask)); \ 5495 ret = false; \ 5496 } \ 5497 } while (0) 5498 5499 #define PIPE_CONF_CHECK_I(name) do { \ 5500 if (current_config->name != pipe_config->name) { \ 5501 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5502 "(expected %i, found %i)", \ 5503 current_config->name, \ 5504 pipe_config->name); \ 5505 ret = false; \ 5506 } \ 5507 } while (0) 5508 5509 #define PIPE_CONF_CHECK_BOOL(name) do { \ 5510 if (current_config->name != pipe_config->name) { \ 5511 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5512 "(expected %s, found %s)", \ 5513 str_yes_no(current_config->name), \ 5514 str_yes_no(pipe_config->name)); \ 5515 ret = false; \ 5516 } \ 5517 } while (0) 5518 5519 /* 5520 * Checks state where we only read out the enabling, but not the entire 5521 * state itself (like full infoframes or ELD for audio). These states 5522 * require a full modeset on bootup to fix up. 5523 */ 5524 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \ 5525 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \ 5526 PIPE_CONF_CHECK_BOOL(name); \ 5527 } else { \ 5528 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5529 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \ 5530 str_yes_no(current_config->name), \ 5531 str_yes_no(pipe_config->name)); \ 5532 ret = false; \ 5533 } \ 5534 } while (0) 5535 5536 #define PIPE_CONF_CHECK_P(name) do { \ 5537 if (current_config->name != pipe_config->name) { \ 5538 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5539 "(expected %p, found %p)", \ 5540 current_config->name, \ 5541 pipe_config->name); \ 5542 ret = false; \ 5543 } \ 5544 } while (0) 5545 5546 #define PIPE_CONF_CHECK_M_N(name) do { \ 5547 if (!intel_compare_link_m_n(¤t_config->name, \ 5548 &pipe_config->name)) { \ 5549 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5550 "(expected tu %i data %i/%i link %i/%i, " \ 5551 "found tu %i, data %i/%i link %i/%i)", \ 5552 current_config->name.tu, \ 5553 current_config->name.data_m, \ 5554 current_config->name.data_n, \ 5555 current_config->name.link_m, \ 5556 current_config->name.link_n, \ 5557 pipe_config->name.tu, \ 5558 pipe_config->name.data_m, \ 5559 pipe_config->name.data_n, \ 5560 pipe_config->name.link_m, \ 5561 pipe_config->name.link_n); \ 5562 ret = false; \ 5563 } \ 5564 } while (0) 5565 5566 #define PIPE_CONF_CHECK_TIMINGS(name) do { \ 5567 PIPE_CONF_CHECK_I(name.crtc_hdisplay); \ 5568 PIPE_CONF_CHECK_I(name.crtc_htotal); \ 5569 PIPE_CONF_CHECK_I(name.crtc_hblank_start); \ 5570 PIPE_CONF_CHECK_I(name.crtc_hblank_end); \ 5571 PIPE_CONF_CHECK_I(name.crtc_hsync_start); \ 5572 PIPE_CONF_CHECK_I(name.crtc_hsync_end); \ 5573 PIPE_CONF_CHECK_I(name.crtc_vdisplay); \ 5574 PIPE_CONF_CHECK_I(name.crtc_vtotal); \ 5575 PIPE_CONF_CHECK_I(name.crtc_vblank_start); \ 5576 PIPE_CONF_CHECK_I(name.crtc_vblank_end); \ 5577 PIPE_CONF_CHECK_I(name.crtc_vsync_start); \ 5578 PIPE_CONF_CHECK_I(name.crtc_vsync_end); \ 5579 } while (0) 5580 5581 #define PIPE_CONF_CHECK_RECT(name) do { \ 5582 PIPE_CONF_CHECK_I(name.x1); \ 5583 PIPE_CONF_CHECK_I(name.x2); \ 5584 PIPE_CONF_CHECK_I(name.y1); \ 5585 PIPE_CONF_CHECK_I(name.y2); \ 5586 } while (0) 5587 5588 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \ 5589 if ((current_config->name ^ pipe_config->name) & (mask)) { \ 5590 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5591 "(%x) (expected %i, found %i)", \ 5592 (mask), \ 5593 current_config->name & (mask), \ 5594 pipe_config->name & (mask)); \ 5595 ret = false; \ 5596 } \ 5597 } while (0) 5598 5599 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \ 5600 if (!intel_compare_infoframe(¤t_config->infoframes.name, \ 5601 &pipe_config->infoframes.name)) { \ 5602 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \ 5603 ¤t_config->infoframes.name, \ 5604 &pipe_config->infoframes.name); \ 5605 ret = false; \ 5606 } \ 5607 } while (0) 5608 5609 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \ 5610 if (!current_config->has_psr && !pipe_config->has_psr && \ 5611 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \ 5612 &pipe_config->infoframes.name)) { \ 5613 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \ 5614 ¤t_config->infoframes.name, \ 5615 &pipe_config->infoframes.name); \ 5616 ret = false; \ 5617 } \ 5618 } while (0) 5619 5620 #define PIPE_CONF_CHECK_BUFFER(name, len) do { \ 5621 BUILD_BUG_ON(sizeof(current_config->name) != (len)); \ 5622 BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \ 5623 if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \ 5624 pipe_config_buffer_mismatch(dev_priv, fastset, __stringify(name), \ 5625 current_config->name, \ 5626 pipe_config->name, \ 5627 (len)); \ 5628 ret = false; \ 5629 } \ 5630 } while (0) 5631 5632 #define PIPE_CONF_CHECK_COLOR_LUT(lut, is_pre_csc_lut) do { \ 5633 if (current_config->gamma_mode == pipe_config->gamma_mode && \ 5634 !intel_color_lut_equal(current_config, \ 5635 current_config->lut, pipe_config->lut, \ 5636 is_pre_csc_lut)) { \ 5637 pipe_config_mismatch(fastset, crtc, __stringify(lut), \ 5638 "hw_state doesn't match sw_state"); \ 5639 ret = false; \ 5640 } \ 5641 } while (0) 5642 5643 #define PIPE_CONF_QUIRK(quirk) \ 5644 ((current_config->quirks | pipe_config->quirks) & (quirk)) 5645 5646 PIPE_CONF_CHECK_I(hw.enable); 5647 PIPE_CONF_CHECK_I(hw.active); 5648 5649 PIPE_CONF_CHECK_I(cpu_transcoder); 5650 PIPE_CONF_CHECK_I(mst_master_transcoder); 5651 5652 PIPE_CONF_CHECK_BOOL(has_pch_encoder); 5653 PIPE_CONF_CHECK_I(fdi_lanes); 5654 PIPE_CONF_CHECK_M_N(fdi_m_n); 5655 5656 PIPE_CONF_CHECK_I(lane_count); 5657 PIPE_CONF_CHECK_X(lane_lat_optim_mask); 5658 5659 if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) { 5660 if (!fastset || !pipe_config->seamless_m_n) 5661 PIPE_CONF_CHECK_M_N(dp_m_n); 5662 } else { 5663 PIPE_CONF_CHECK_M_N(dp_m_n); 5664 PIPE_CONF_CHECK_M_N(dp_m2_n2); 5665 } 5666 5667 PIPE_CONF_CHECK_X(output_types); 5668 5669 PIPE_CONF_CHECK_I(framestart_delay); 5670 PIPE_CONF_CHECK_I(msa_timing_delay); 5671 5672 PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode); 5673 PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode); 5674 5675 PIPE_CONF_CHECK_I(pixel_multiplier); 5676 5677 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5678 DRM_MODE_FLAG_INTERLACE); 5679 5680 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { 5681 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5682 DRM_MODE_FLAG_PHSYNC); 5683 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5684 DRM_MODE_FLAG_NHSYNC); 5685 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5686 DRM_MODE_FLAG_PVSYNC); 5687 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5688 DRM_MODE_FLAG_NVSYNC); 5689 } 5690 5691 PIPE_CONF_CHECK_I(output_format); 5692 PIPE_CONF_CHECK_BOOL(has_hdmi_sink); 5693 if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || 5694 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5695 PIPE_CONF_CHECK_BOOL(limited_color_range); 5696 5697 PIPE_CONF_CHECK_BOOL(hdmi_scrambling); 5698 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio); 5699 PIPE_CONF_CHECK_BOOL(has_infoframe); 5700 PIPE_CONF_CHECK_BOOL(fec_enable); 5701 5702 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio); 5703 PIPE_CONF_CHECK_BUFFER(eld, MAX_ELD_BYTES); 5704 5705 PIPE_CONF_CHECK_X(gmch_pfit.control); 5706 /* pfit ratios are autocomputed by the hw on gen4+ */ 5707 if (DISPLAY_VER(dev_priv) < 4) 5708 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); 5709 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); 5710 5711 /* 5712 * Changing the EDP transcoder input mux 5713 * (A_ONOFF vs. A_ON) requires a full modeset. 5714 */ 5715 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru); 5716 5717 if (!fastset) { 5718 PIPE_CONF_CHECK_RECT(pipe_src); 5719 5720 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled); 5721 PIPE_CONF_CHECK_RECT(pch_pfit.dst); 5722 5723 PIPE_CONF_CHECK_I(scaler_state.scaler_id); 5724 PIPE_CONF_CHECK_I(pixel_rate); 5725 5726 PIPE_CONF_CHECK_X(gamma_mode); 5727 if (IS_CHERRYVIEW(dev_priv)) 5728 PIPE_CONF_CHECK_X(cgm_mode); 5729 else 5730 PIPE_CONF_CHECK_X(csc_mode); 5731 PIPE_CONF_CHECK_BOOL(gamma_enable); 5732 PIPE_CONF_CHECK_BOOL(csc_enable); 5733 5734 PIPE_CONF_CHECK_I(linetime); 5735 PIPE_CONF_CHECK_I(ips_linetime); 5736 5737 PIPE_CONF_CHECK_COLOR_LUT(pre_csc_lut, true); 5738 PIPE_CONF_CHECK_COLOR_LUT(post_csc_lut, false); 5739 5740 if (current_config->active_planes) { 5741 PIPE_CONF_CHECK_BOOL(has_psr); 5742 PIPE_CONF_CHECK_BOOL(has_psr2); 5743 PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); 5744 PIPE_CONF_CHECK_I(dc3co_exitline); 5745 } 5746 } 5747 5748 PIPE_CONF_CHECK_BOOL(double_wide); 5749 5750 if (dev_priv->display.dpll.mgr) { 5751 PIPE_CONF_CHECK_P(shared_dpll); 5752 5753 PIPE_CONF_CHECK_X(dpll_hw_state.dpll); 5754 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); 5755 PIPE_CONF_CHECK_X(dpll_hw_state.fp0); 5756 PIPE_CONF_CHECK_X(dpll_hw_state.fp1); 5757 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); 5758 PIPE_CONF_CHECK_X(dpll_hw_state.spll); 5759 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); 5760 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); 5761 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); 5762 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); 5763 PIPE_CONF_CHECK_X(dpll_hw_state.div0); 5764 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); 5765 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); 5766 PIPE_CONF_CHECK_X(dpll_hw_state.pll0); 5767 PIPE_CONF_CHECK_X(dpll_hw_state.pll1); 5768 PIPE_CONF_CHECK_X(dpll_hw_state.pll2); 5769 PIPE_CONF_CHECK_X(dpll_hw_state.pll3); 5770 PIPE_CONF_CHECK_X(dpll_hw_state.pll6); 5771 PIPE_CONF_CHECK_X(dpll_hw_state.pll8); 5772 PIPE_CONF_CHECK_X(dpll_hw_state.pll9); 5773 PIPE_CONF_CHECK_X(dpll_hw_state.pll10); 5774 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); 5775 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl); 5776 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1); 5777 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl); 5778 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0); 5779 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1); 5780 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf); 5781 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock); 5782 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc); 5783 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias); 5784 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias); 5785 } 5786 5787 PIPE_CONF_CHECK_X(dsi_pll.ctrl); 5788 PIPE_CONF_CHECK_X(dsi_pll.div); 5789 5790 if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5) 5791 PIPE_CONF_CHECK_I(pipe_bpp); 5792 5793 if (!fastset || !pipe_config->seamless_m_n) { 5794 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock); 5795 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock); 5796 } 5797 PIPE_CONF_CHECK_I(port_clock); 5798 5799 PIPE_CONF_CHECK_I(min_voltage_level); 5800 5801 if (current_config->has_psr || pipe_config->has_psr) 5802 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable, 5803 ~intel_hdmi_infoframe_enable(DP_SDP_VSC)); 5804 else 5805 PIPE_CONF_CHECK_X(infoframes.enable); 5806 5807 PIPE_CONF_CHECK_X(infoframes.gcp); 5808 PIPE_CONF_CHECK_INFOFRAME(avi); 5809 PIPE_CONF_CHECK_INFOFRAME(spd); 5810 PIPE_CONF_CHECK_INFOFRAME(hdmi); 5811 PIPE_CONF_CHECK_INFOFRAME(drm); 5812 PIPE_CONF_CHECK_DP_VSC_SDP(vsc); 5813 5814 PIPE_CONF_CHECK_X(sync_mode_slaves_mask); 5815 PIPE_CONF_CHECK_I(master_transcoder); 5816 PIPE_CONF_CHECK_X(bigjoiner_pipes); 5817 5818 PIPE_CONF_CHECK_I(dsc.compression_enable); 5819 PIPE_CONF_CHECK_I(dsc.dsc_split); 5820 PIPE_CONF_CHECK_I(dsc.compressed_bpp); 5821 5822 PIPE_CONF_CHECK_BOOL(splitter.enable); 5823 PIPE_CONF_CHECK_I(splitter.link_count); 5824 PIPE_CONF_CHECK_I(splitter.pixel_overlap); 5825 5826 PIPE_CONF_CHECK_BOOL(vrr.enable); 5827 PIPE_CONF_CHECK_I(vrr.vmin); 5828 PIPE_CONF_CHECK_I(vrr.vmax); 5829 PIPE_CONF_CHECK_I(vrr.flipline); 5830 PIPE_CONF_CHECK_I(vrr.pipeline_full); 5831 PIPE_CONF_CHECK_I(vrr.guardband); 5832 5833 #undef PIPE_CONF_CHECK_X 5834 #undef PIPE_CONF_CHECK_I 5835 #undef PIPE_CONF_CHECK_BOOL 5836 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE 5837 #undef PIPE_CONF_CHECK_P 5838 #undef PIPE_CONF_CHECK_FLAGS 5839 #undef PIPE_CONF_CHECK_COLOR_LUT 5840 #undef PIPE_CONF_CHECK_TIMINGS 5841 #undef PIPE_CONF_CHECK_RECT 5842 #undef PIPE_CONF_QUIRK 5843 5844 return ret; 5845 } 5846 5847 static void 5848 intel_verify_planes(struct intel_atomic_state *state) 5849 { 5850 struct intel_plane *plane; 5851 const struct intel_plane_state *plane_state; 5852 int i; 5853 5854 for_each_new_intel_plane_in_state(state, plane, 5855 plane_state, i) 5856 assert_plane(plane, plane_state->planar_slave || 5857 plane_state->uapi.visible); 5858 } 5859 5860 int intel_modeset_all_pipes(struct intel_atomic_state *state, 5861 const char *reason) 5862 { 5863 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 5864 struct intel_crtc *crtc; 5865 5866 /* 5867 * Add all pipes to the state, and force 5868 * a modeset on all the active ones. 5869 */ 5870 for_each_intel_crtc(&dev_priv->drm, crtc) { 5871 struct intel_crtc_state *crtc_state; 5872 int ret; 5873 5874 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 5875 if (IS_ERR(crtc_state)) 5876 return PTR_ERR(crtc_state); 5877 5878 if (!crtc_state->hw.active || 5879 intel_crtc_needs_modeset(crtc_state)) 5880 continue; 5881 5882 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] Full modeset due to %s\n", 5883 crtc->base.base.id, crtc->base.name, reason); 5884 5885 crtc_state->uapi.mode_changed = true; 5886 crtc_state->update_pipe = false; 5887 5888 ret = drm_atomic_add_affected_connectors(&state->base, 5889 &crtc->base); 5890 if (ret) 5891 return ret; 5892 5893 ret = intel_atomic_add_affected_planes(state, crtc); 5894 if (ret) 5895 return ret; 5896 5897 crtc_state->update_planes |= crtc_state->active_planes; 5898 crtc_state->async_flip_planes = 0; 5899 crtc_state->do_async_flip = false; 5900 } 5901 5902 return 0; 5903 } 5904 5905 void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state) 5906 { 5907 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 5908 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 5909 struct drm_display_mode adjusted_mode; 5910 5911 drm_mode_init(&adjusted_mode, &crtc_state->hw.adjusted_mode); 5912 5913 if (crtc_state->vrr.enable) { 5914 adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax; 5915 adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax; 5916 adjusted_mode.crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state); 5917 crtc->vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state); 5918 } 5919 5920 drm_calc_timestamping_constants(&crtc->base, &adjusted_mode); 5921 5922 crtc->mode_flags = crtc_state->mode_flags; 5923 5924 /* 5925 * The scanline counter increments at the leading edge of hsync. 5926 * 5927 * On most platforms it starts counting from vtotal-1 on the 5928 * first active line. That means the scanline counter value is 5929 * always one less than what we would expect. Ie. just after 5930 * start of vblank, which also occurs at start of hsync (on the 5931 * last active line), the scanline counter will read vblank_start-1. 5932 * 5933 * On gen2 the scanline counter starts counting from 1 instead 5934 * of vtotal-1, so we have to subtract one (or rather add vtotal-1 5935 * to keep the value positive), instead of adding one. 5936 * 5937 * On HSW+ the behaviour of the scanline counter depends on the output 5938 * type. For DP ports it behaves like most other platforms, but on HDMI 5939 * there's an extra 1 line difference. So we need to add two instead of 5940 * one to the value. 5941 * 5942 * On VLV/CHV DSI the scanline counter would appear to increment 5943 * approx. 1/3 of a scanline before start of vblank. Unfortunately 5944 * that means we can't tell whether we're in vblank or not while 5945 * we're on that particular line. We must still set scanline_offset 5946 * to 1 so that the vblank timestamps come out correct when we query 5947 * the scanline counter from within the vblank interrupt handler. 5948 * However if queried just before the start of vblank we'll get an 5949 * answer that's slightly in the future. 5950 */ 5951 if (DISPLAY_VER(dev_priv) == 2) { 5952 int vtotal; 5953 5954 vtotal = adjusted_mode.crtc_vtotal; 5955 if (adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 5956 vtotal /= 2; 5957 5958 crtc->scanline_offset = vtotal - 1; 5959 } else if (HAS_DDI(dev_priv) && 5960 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 5961 crtc->scanline_offset = 2; 5962 } else { 5963 crtc->scanline_offset = 1; 5964 } 5965 } 5966 5967 /* 5968 * This implements the workaround described in the "notes" section of the mode 5969 * set sequence documentation. When going from no pipes or single pipe to 5970 * multiple pipes, and planes are enabled after the pipe, we need to wait at 5971 * least 2 vblanks on the first pipe before enabling planes on the second pipe. 5972 */ 5973 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state) 5974 { 5975 struct intel_crtc_state *crtc_state; 5976 struct intel_crtc *crtc; 5977 struct intel_crtc_state *first_crtc_state = NULL; 5978 struct intel_crtc_state *other_crtc_state = NULL; 5979 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; 5980 int i; 5981 5982 /* look at all crtc's that are going to be enabled in during modeset */ 5983 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5984 if (!crtc_state->hw.active || 5985 !intel_crtc_needs_modeset(crtc_state)) 5986 continue; 5987 5988 if (first_crtc_state) { 5989 other_crtc_state = crtc_state; 5990 break; 5991 } else { 5992 first_crtc_state = crtc_state; 5993 first_pipe = crtc->pipe; 5994 } 5995 } 5996 5997 /* No workaround needed? */ 5998 if (!first_crtc_state) 5999 return 0; 6000 6001 /* w/a possibly needed, check how many crtc's are already enabled. */ 6002 for_each_intel_crtc(state->base.dev, crtc) { 6003 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6004 if (IS_ERR(crtc_state)) 6005 return PTR_ERR(crtc_state); 6006 6007 crtc_state->hsw_workaround_pipe = INVALID_PIPE; 6008 6009 if (!crtc_state->hw.active || 6010 intel_crtc_needs_modeset(crtc_state)) 6011 continue; 6012 6013 /* 2 or more enabled crtcs means no need for w/a */ 6014 if (enabled_pipe != INVALID_PIPE) 6015 return 0; 6016 6017 enabled_pipe = crtc->pipe; 6018 } 6019 6020 if (enabled_pipe != INVALID_PIPE) 6021 first_crtc_state->hsw_workaround_pipe = enabled_pipe; 6022 else if (other_crtc_state) 6023 other_crtc_state->hsw_workaround_pipe = first_pipe; 6024 6025 return 0; 6026 } 6027 6028 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 6029 u8 active_pipes) 6030 { 6031 const struct intel_crtc_state *crtc_state; 6032 struct intel_crtc *crtc; 6033 int i; 6034 6035 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6036 if (crtc_state->hw.active) 6037 active_pipes |= BIT(crtc->pipe); 6038 else 6039 active_pipes &= ~BIT(crtc->pipe); 6040 } 6041 6042 return active_pipes; 6043 } 6044 6045 static int intel_modeset_checks(struct intel_atomic_state *state) 6046 { 6047 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6048 6049 state->modeset = true; 6050 6051 if (IS_HASWELL(dev_priv)) 6052 return hsw_mode_set_planes_workaround(state); 6053 6054 return 0; 6055 } 6056 6057 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state, 6058 struct intel_crtc_state *new_crtc_state) 6059 { 6060 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) 6061 return; 6062 6063 new_crtc_state->uapi.mode_changed = false; 6064 if (!intel_crtc_needs_modeset(new_crtc_state)) 6065 new_crtc_state->update_pipe = true; 6066 } 6067 6068 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state, 6069 struct intel_crtc *crtc, 6070 u8 plane_ids_mask) 6071 { 6072 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6073 struct intel_plane *plane; 6074 6075 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 6076 struct intel_plane_state *plane_state; 6077 6078 if ((plane_ids_mask & BIT(plane->id)) == 0) 6079 continue; 6080 6081 plane_state = intel_atomic_get_plane_state(state, plane); 6082 if (IS_ERR(plane_state)) 6083 return PTR_ERR(plane_state); 6084 } 6085 6086 return 0; 6087 } 6088 6089 int intel_atomic_add_affected_planes(struct intel_atomic_state *state, 6090 struct intel_crtc *crtc) 6091 { 6092 const struct intel_crtc_state *old_crtc_state = 6093 intel_atomic_get_old_crtc_state(state, crtc); 6094 const struct intel_crtc_state *new_crtc_state = 6095 intel_atomic_get_new_crtc_state(state, crtc); 6096 6097 return intel_crtc_add_planes_to_state(state, crtc, 6098 old_crtc_state->enabled_planes | 6099 new_crtc_state->enabled_planes); 6100 } 6101 6102 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv) 6103 { 6104 /* See {hsw,vlv,ivb}_plane_ratio() */ 6105 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) || 6106 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) || 6107 IS_IVYBRIDGE(dev_priv); 6108 } 6109 6110 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state, 6111 struct intel_crtc *crtc, 6112 struct intel_crtc *other) 6113 { 6114 const struct intel_plane_state *plane_state; 6115 struct intel_plane *plane; 6116 u8 plane_ids = 0; 6117 int i; 6118 6119 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 6120 if (plane->pipe == crtc->pipe) 6121 plane_ids |= BIT(plane->id); 6122 } 6123 6124 return intel_crtc_add_planes_to_state(state, other, plane_ids); 6125 } 6126 6127 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state) 6128 { 6129 struct drm_i915_private *i915 = to_i915(state->base.dev); 6130 const struct intel_crtc_state *crtc_state; 6131 struct intel_crtc *crtc; 6132 int i; 6133 6134 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6135 struct intel_crtc *other; 6136 6137 for_each_intel_crtc_in_pipe_mask(&i915->drm, other, 6138 crtc_state->bigjoiner_pipes) { 6139 int ret; 6140 6141 if (crtc == other) 6142 continue; 6143 6144 ret = intel_crtc_add_bigjoiner_planes(state, crtc, other); 6145 if (ret) 6146 return ret; 6147 } 6148 } 6149 6150 return 0; 6151 } 6152 6153 static int intel_atomic_check_planes(struct intel_atomic_state *state) 6154 { 6155 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6156 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6157 struct intel_plane_state *plane_state; 6158 struct intel_plane *plane; 6159 struct intel_crtc *crtc; 6160 int i, ret; 6161 6162 ret = icl_add_linked_planes(state); 6163 if (ret) 6164 return ret; 6165 6166 ret = intel_bigjoiner_add_affected_planes(state); 6167 if (ret) 6168 return ret; 6169 6170 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 6171 ret = intel_plane_atomic_check(state, plane); 6172 if (ret) { 6173 drm_dbg_atomic(&dev_priv->drm, 6174 "[PLANE:%d:%s] atomic driver check failed\n", 6175 plane->base.base.id, plane->base.name); 6176 return ret; 6177 } 6178 } 6179 6180 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6181 new_crtc_state, i) { 6182 u8 old_active_planes, new_active_planes; 6183 6184 ret = icl_check_nv12_planes(new_crtc_state); 6185 if (ret) 6186 return ret; 6187 6188 /* 6189 * On some platforms the number of active planes affects 6190 * the planes' minimum cdclk calculation. Add such planes 6191 * to the state before we compute the minimum cdclk. 6192 */ 6193 if (!active_planes_affects_min_cdclk(dev_priv)) 6194 continue; 6195 6196 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 6197 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 6198 6199 if (hweight8(old_active_planes) == hweight8(new_active_planes)) 6200 continue; 6201 6202 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes); 6203 if (ret) 6204 return ret; 6205 } 6206 6207 return 0; 6208 } 6209 6210 static int intel_atomic_check_crtcs(struct intel_atomic_state *state) 6211 { 6212 struct intel_crtc_state *crtc_state; 6213 struct intel_crtc *crtc; 6214 int i; 6215 6216 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6217 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 6218 int ret; 6219 6220 ret = intel_crtc_atomic_check(state, crtc); 6221 if (ret) { 6222 drm_dbg_atomic(&i915->drm, 6223 "[CRTC:%d:%s] atomic driver check failed\n", 6224 crtc->base.base.id, crtc->base.name); 6225 return ret; 6226 } 6227 } 6228 6229 return 0; 6230 } 6231 6232 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, 6233 u8 transcoders) 6234 { 6235 const struct intel_crtc_state *new_crtc_state; 6236 struct intel_crtc *crtc; 6237 int i; 6238 6239 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6240 if (new_crtc_state->hw.enable && 6241 transcoders & BIT(new_crtc_state->cpu_transcoder) && 6242 intel_crtc_needs_modeset(new_crtc_state)) 6243 return true; 6244 } 6245 6246 return false; 6247 } 6248 6249 static bool intel_pipes_need_modeset(struct intel_atomic_state *state, 6250 u8 pipes) 6251 { 6252 const struct intel_crtc_state *new_crtc_state; 6253 struct intel_crtc *crtc; 6254 int i; 6255 6256 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6257 if (new_crtc_state->hw.enable && 6258 pipes & BIT(crtc->pipe) && 6259 intel_crtc_needs_modeset(new_crtc_state)) 6260 return true; 6261 } 6262 6263 return false; 6264 } 6265 6266 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state, 6267 struct intel_crtc *master_crtc) 6268 { 6269 struct drm_i915_private *i915 = to_i915(state->base.dev); 6270 struct intel_crtc_state *master_crtc_state = 6271 intel_atomic_get_new_crtc_state(state, master_crtc); 6272 struct intel_crtc *slave_crtc; 6273 6274 if (!master_crtc_state->bigjoiner_pipes) 6275 return 0; 6276 6277 /* sanity check */ 6278 if (drm_WARN_ON(&i915->drm, 6279 master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state))) 6280 return -EINVAL; 6281 6282 if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) { 6283 drm_dbg_kms(&i915->drm, 6284 "[CRTC:%d:%s] Cannot act as big joiner master " 6285 "(need 0x%x as pipes, only 0x%x possible)\n", 6286 master_crtc->base.base.id, master_crtc->base.name, 6287 master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915)); 6288 return -EINVAL; 6289 } 6290 6291 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 6292 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 6293 struct intel_crtc_state *slave_crtc_state; 6294 int ret; 6295 6296 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc); 6297 if (IS_ERR(slave_crtc_state)) 6298 return PTR_ERR(slave_crtc_state); 6299 6300 /* master being enabled, slave was already configured? */ 6301 if (slave_crtc_state->uapi.enable) { 6302 drm_dbg_kms(&i915->drm, 6303 "[CRTC:%d:%s] Slave is enabled as normal CRTC, but " 6304 "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n", 6305 slave_crtc->base.base.id, slave_crtc->base.name, 6306 master_crtc->base.base.id, master_crtc->base.name); 6307 return -EINVAL; 6308 } 6309 6310 /* 6311 * The state copy logic assumes the master crtc gets processed 6312 * before the slave crtc during the main compute_config loop. 6313 * This works because the crtcs are created in pipe order, 6314 * and the hardware requires master pipe < slave pipe as well. 6315 * Should that change we need to rethink the logic. 6316 */ 6317 if (WARN_ON(drm_crtc_index(&master_crtc->base) > 6318 drm_crtc_index(&slave_crtc->base))) 6319 return -EINVAL; 6320 6321 drm_dbg_kms(&i915->drm, 6322 "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n", 6323 slave_crtc->base.base.id, slave_crtc->base.name, 6324 master_crtc->base.base.id, master_crtc->base.name); 6325 6326 slave_crtc_state->bigjoiner_pipes = 6327 master_crtc_state->bigjoiner_pipes; 6328 6329 ret = copy_bigjoiner_crtc_state_modeset(state, slave_crtc); 6330 if (ret) 6331 return ret; 6332 } 6333 6334 return 0; 6335 } 6336 6337 static void kill_bigjoiner_slave(struct intel_atomic_state *state, 6338 struct intel_crtc *master_crtc) 6339 { 6340 struct drm_i915_private *i915 = to_i915(state->base.dev); 6341 struct intel_crtc_state *master_crtc_state = 6342 intel_atomic_get_new_crtc_state(state, master_crtc); 6343 struct intel_crtc *slave_crtc; 6344 6345 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 6346 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 6347 struct intel_crtc_state *slave_crtc_state = 6348 intel_atomic_get_new_crtc_state(state, slave_crtc); 6349 6350 slave_crtc_state->bigjoiner_pipes = 0; 6351 6352 intel_crtc_copy_uapi_to_hw_state_modeset(state, slave_crtc); 6353 } 6354 6355 master_crtc_state->bigjoiner_pipes = 0; 6356 } 6357 6358 /** 6359 * DOC: asynchronous flip implementation 6360 * 6361 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC 6362 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL. 6363 * Correspondingly, support is currently added for primary plane only. 6364 * 6365 * Async flip can only change the plane surface address, so anything else 6366 * changing is rejected from the intel_async_flip_check_hw() function. 6367 * Once this check is cleared, flip done interrupt is enabled using 6368 * the intel_crtc_enable_flip_done() function. 6369 * 6370 * As soon as the surface address register is written, flip done interrupt is 6371 * generated and the requested events are sent to the usersapce in the interrupt 6372 * handler itself. The timestamp and sequence sent during the flip done event 6373 * correspond to the last vblank and have no relation to the actual time when 6374 * the flip done event was sent. 6375 */ 6376 static int intel_async_flip_check_uapi(struct intel_atomic_state *state, 6377 struct intel_crtc *crtc) 6378 { 6379 struct drm_i915_private *i915 = to_i915(state->base.dev); 6380 const struct intel_crtc_state *new_crtc_state = 6381 intel_atomic_get_new_crtc_state(state, crtc); 6382 const struct intel_plane_state *old_plane_state; 6383 struct intel_plane_state *new_plane_state; 6384 struct intel_plane *plane; 6385 int i; 6386 6387 if (!new_crtc_state->uapi.async_flip) 6388 return 0; 6389 6390 if (!new_crtc_state->uapi.active) { 6391 drm_dbg_kms(&i915->drm, 6392 "[CRTC:%d:%s] not active\n", 6393 crtc->base.base.id, crtc->base.name); 6394 return -EINVAL; 6395 } 6396 6397 if (intel_crtc_needs_modeset(new_crtc_state)) { 6398 drm_dbg_kms(&i915->drm, 6399 "[CRTC:%d:%s] modeset required\n", 6400 crtc->base.base.id, crtc->base.name); 6401 return -EINVAL; 6402 } 6403 6404 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 6405 new_plane_state, i) { 6406 if (plane->pipe != crtc->pipe) 6407 continue; 6408 6409 /* 6410 * TODO: Async flip is only supported through the page flip IOCTL 6411 * as of now. So support currently added for primary plane only. 6412 * Support for other planes on platforms on which supports 6413 * this(vlv/chv and icl+) should be added when async flip is 6414 * enabled in the atomic IOCTL path. 6415 */ 6416 if (!plane->async_flip) { 6417 drm_dbg_kms(&i915->drm, 6418 "[PLANE:%d:%s] async flip not supported\n", 6419 plane->base.base.id, plane->base.name); 6420 return -EINVAL; 6421 } 6422 6423 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) { 6424 drm_dbg_kms(&i915->drm, 6425 "[PLANE:%d:%s] no old or new framebuffer\n", 6426 plane->base.base.id, plane->base.name); 6427 return -EINVAL; 6428 } 6429 } 6430 6431 return 0; 6432 } 6433 6434 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc) 6435 { 6436 struct drm_i915_private *i915 = to_i915(state->base.dev); 6437 const struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6438 const struct intel_plane_state *new_plane_state, *old_plane_state; 6439 struct intel_plane *plane; 6440 int i; 6441 6442 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 6443 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6444 6445 if (!new_crtc_state->uapi.async_flip) 6446 return 0; 6447 6448 if (!new_crtc_state->hw.active) { 6449 drm_dbg_kms(&i915->drm, 6450 "[CRTC:%d:%s] not active\n", 6451 crtc->base.base.id, crtc->base.name); 6452 return -EINVAL; 6453 } 6454 6455 if (intel_crtc_needs_modeset(new_crtc_state)) { 6456 drm_dbg_kms(&i915->drm, 6457 "[CRTC:%d:%s] modeset required\n", 6458 crtc->base.base.id, crtc->base.name); 6459 return -EINVAL; 6460 } 6461 6462 if (old_crtc_state->active_planes != new_crtc_state->active_planes) { 6463 drm_dbg_kms(&i915->drm, 6464 "[CRTC:%d:%s] Active planes cannot be in async flip\n", 6465 crtc->base.base.id, crtc->base.name); 6466 return -EINVAL; 6467 } 6468 6469 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 6470 new_plane_state, i) { 6471 if (plane->pipe != crtc->pipe) 6472 continue; 6473 6474 /* 6475 * Only async flip capable planes should be in the state 6476 * if we're really about to ask the hardware to perform 6477 * an async flip. We should never get this far otherwise. 6478 */ 6479 if (drm_WARN_ON(&i915->drm, 6480 new_crtc_state->do_async_flip && !plane->async_flip)) 6481 return -EINVAL; 6482 6483 /* 6484 * Only check async flip capable planes other planes 6485 * may be involved in the initial commit due to 6486 * the wm0/ddb optimization. 6487 * 6488 * TODO maybe should track which planes actually 6489 * were requested to do the async flip... 6490 */ 6491 if (!plane->async_flip) 6492 continue; 6493 6494 /* 6495 * FIXME: This check is kept generic for all platforms. 6496 * Need to verify this for all gen9 platforms to enable 6497 * this selectively if required. 6498 */ 6499 switch (new_plane_state->hw.fb->modifier) { 6500 case I915_FORMAT_MOD_X_TILED: 6501 case I915_FORMAT_MOD_Y_TILED: 6502 case I915_FORMAT_MOD_Yf_TILED: 6503 case I915_FORMAT_MOD_4_TILED: 6504 break; 6505 default: 6506 drm_dbg_kms(&i915->drm, 6507 "[PLANE:%d:%s] Modifier does not support async flips\n", 6508 plane->base.base.id, plane->base.name); 6509 return -EINVAL; 6510 } 6511 6512 if (new_plane_state->hw.fb->format->num_planes > 1) { 6513 drm_dbg_kms(&i915->drm, 6514 "[PLANE:%d:%s] Planar formats do not support async flips\n", 6515 plane->base.base.id, plane->base.name); 6516 return -EINVAL; 6517 } 6518 6519 if (old_plane_state->view.color_plane[0].mapping_stride != 6520 new_plane_state->view.color_plane[0].mapping_stride) { 6521 drm_dbg_kms(&i915->drm, 6522 "[PLANE:%d:%s] Stride cannot be changed in async flip\n", 6523 plane->base.base.id, plane->base.name); 6524 return -EINVAL; 6525 } 6526 6527 if (old_plane_state->hw.fb->modifier != 6528 new_plane_state->hw.fb->modifier) { 6529 drm_dbg_kms(&i915->drm, 6530 "[PLANE:%d:%s] Modifier cannot be changed in async flip\n", 6531 plane->base.base.id, plane->base.name); 6532 return -EINVAL; 6533 } 6534 6535 if (old_plane_state->hw.fb->format != 6536 new_plane_state->hw.fb->format) { 6537 drm_dbg_kms(&i915->drm, 6538 "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n", 6539 plane->base.base.id, plane->base.name); 6540 return -EINVAL; 6541 } 6542 6543 if (old_plane_state->hw.rotation != 6544 new_plane_state->hw.rotation) { 6545 drm_dbg_kms(&i915->drm, 6546 "[PLANE:%d:%s] Rotation cannot be changed in async flip\n", 6547 plane->base.base.id, plane->base.name); 6548 return -EINVAL; 6549 } 6550 6551 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) || 6552 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) { 6553 drm_dbg_kms(&i915->drm, 6554 "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n", 6555 plane->base.base.id, plane->base.name); 6556 return -EINVAL; 6557 } 6558 6559 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) { 6560 drm_dbg_kms(&i915->drm, 6561 "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n", 6562 plane->base.base.id, plane->base.name); 6563 return -EINVAL; 6564 } 6565 6566 if (old_plane_state->hw.pixel_blend_mode != 6567 new_plane_state->hw.pixel_blend_mode) { 6568 drm_dbg_kms(&i915->drm, 6569 "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n", 6570 plane->base.base.id, plane->base.name); 6571 return -EINVAL; 6572 } 6573 6574 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) { 6575 drm_dbg_kms(&i915->drm, 6576 "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n", 6577 plane->base.base.id, plane->base.name); 6578 return -EINVAL; 6579 } 6580 6581 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) { 6582 drm_dbg_kms(&i915->drm, 6583 "[PLANE:%d:%s] Color range cannot be changed in async flip\n", 6584 plane->base.base.id, plane->base.name); 6585 return -EINVAL; 6586 } 6587 6588 /* plane decryption is allow to change only in synchronous flips */ 6589 if (old_plane_state->decrypt != new_plane_state->decrypt) { 6590 drm_dbg_kms(&i915->drm, 6591 "[PLANE:%d:%s] Decryption cannot be changed in async flip\n", 6592 plane->base.base.id, plane->base.name); 6593 return -EINVAL; 6594 } 6595 } 6596 6597 return 0; 6598 } 6599 6600 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state) 6601 { 6602 struct drm_i915_private *i915 = to_i915(state->base.dev); 6603 struct intel_crtc_state *crtc_state; 6604 struct intel_crtc *crtc; 6605 u8 affected_pipes = 0; 6606 u8 modeset_pipes = 0; 6607 int i; 6608 6609 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6610 affected_pipes |= crtc_state->bigjoiner_pipes; 6611 if (intel_crtc_needs_modeset(crtc_state)) 6612 modeset_pipes |= crtc_state->bigjoiner_pipes; 6613 } 6614 6615 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) { 6616 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6617 if (IS_ERR(crtc_state)) 6618 return PTR_ERR(crtc_state); 6619 } 6620 6621 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) { 6622 int ret; 6623 6624 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6625 6626 crtc_state->uapi.mode_changed = true; 6627 6628 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); 6629 if (ret) 6630 return ret; 6631 6632 ret = intel_atomic_add_affected_planes(state, crtc); 6633 if (ret) 6634 return ret; 6635 } 6636 6637 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6638 /* Kill old bigjoiner link, we may re-establish afterwards */ 6639 if (intel_crtc_needs_modeset(crtc_state) && 6640 intel_crtc_is_bigjoiner_master(crtc_state)) 6641 kill_bigjoiner_slave(state, crtc); 6642 } 6643 6644 return 0; 6645 } 6646 6647 /** 6648 * intel_atomic_check - validate state object 6649 * @dev: drm device 6650 * @_state: state to validate 6651 */ 6652 int intel_atomic_check(struct drm_device *dev, 6653 struct drm_atomic_state *_state) 6654 { 6655 struct drm_i915_private *dev_priv = to_i915(dev); 6656 struct intel_atomic_state *state = to_intel_atomic_state(_state); 6657 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6658 struct intel_crtc *crtc; 6659 int ret, i; 6660 bool any_ms = false; 6661 6662 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6663 new_crtc_state, i) { 6664 if (new_crtc_state->inherited != old_crtc_state->inherited) 6665 new_crtc_state->uapi.mode_changed = true; 6666 6667 if (new_crtc_state->uapi.scaling_filter != 6668 old_crtc_state->uapi.scaling_filter) 6669 new_crtc_state->uapi.mode_changed = true; 6670 } 6671 6672 intel_vrr_check_modeset(state); 6673 6674 ret = drm_atomic_helper_check_modeset(dev, &state->base); 6675 if (ret) 6676 goto fail; 6677 6678 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6679 ret = intel_async_flip_check_uapi(state, crtc); 6680 if (ret) 6681 return ret; 6682 } 6683 6684 ret = intel_bigjoiner_add_affected_crtcs(state); 6685 if (ret) 6686 goto fail; 6687 6688 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6689 new_crtc_state, i) { 6690 if (!intel_crtc_needs_modeset(new_crtc_state)) { 6691 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 6692 copy_bigjoiner_crtc_state_nomodeset(state, crtc); 6693 else 6694 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 6695 continue; 6696 } 6697 6698 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) { 6699 drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable); 6700 continue; 6701 } 6702 6703 ret = intel_crtc_prepare_cleared_state(state, crtc); 6704 if (ret) 6705 goto fail; 6706 6707 if (!new_crtc_state->hw.enable) 6708 continue; 6709 6710 ret = intel_modeset_pipe_config(state, crtc); 6711 if (ret) 6712 goto fail; 6713 6714 ret = intel_atomic_check_bigjoiner(state, crtc); 6715 if (ret) 6716 goto fail; 6717 } 6718 6719 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6720 new_crtc_state, i) { 6721 if (!intel_crtc_needs_modeset(new_crtc_state)) 6722 continue; 6723 6724 if (new_crtc_state->hw.enable) { 6725 ret = intel_modeset_pipe_config_late(state, crtc); 6726 if (ret) 6727 goto fail; 6728 } 6729 6730 intel_crtc_check_fastset(old_crtc_state, new_crtc_state); 6731 } 6732 6733 /** 6734 * Check if fastset is allowed by external dependencies like other 6735 * pipes and transcoders. 6736 * 6737 * Right now it only forces a fullmodeset when the MST master 6738 * transcoder did not changed but the pipe of the master transcoder 6739 * needs a fullmodeset so all slaves also needs to do a fullmodeset or 6740 * in case of port synced crtcs, if one of the synced crtcs 6741 * needs a full modeset, all other synced crtcs should be 6742 * forced a full modeset. 6743 */ 6744 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6745 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state)) 6746 continue; 6747 6748 if (intel_dp_mst_is_slave_trans(new_crtc_state)) { 6749 enum transcoder master = new_crtc_state->mst_master_transcoder; 6750 6751 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) { 6752 new_crtc_state->uapi.mode_changed = true; 6753 new_crtc_state->update_pipe = false; 6754 } 6755 } 6756 6757 if (is_trans_port_sync_mode(new_crtc_state)) { 6758 u8 trans = new_crtc_state->sync_mode_slaves_mask; 6759 6760 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER) 6761 trans |= BIT(new_crtc_state->master_transcoder); 6762 6763 if (intel_cpu_transcoders_need_modeset(state, trans)) { 6764 new_crtc_state->uapi.mode_changed = true; 6765 new_crtc_state->update_pipe = false; 6766 } 6767 } 6768 6769 if (new_crtc_state->bigjoiner_pipes) { 6770 if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) { 6771 new_crtc_state->uapi.mode_changed = true; 6772 new_crtc_state->update_pipe = false; 6773 } 6774 } 6775 } 6776 6777 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6778 new_crtc_state, i) { 6779 if (!intel_crtc_needs_modeset(new_crtc_state)) 6780 continue; 6781 6782 any_ms = true; 6783 6784 intel_release_shared_dplls(state, crtc); 6785 } 6786 6787 if (any_ms && !check_digital_port_conflicts(state)) { 6788 drm_dbg_kms(&dev_priv->drm, 6789 "rejecting conflicting digital port configuration\n"); 6790 ret = -EINVAL; 6791 goto fail; 6792 } 6793 6794 ret = drm_dp_mst_atomic_check(&state->base); 6795 if (ret) 6796 goto fail; 6797 6798 ret = intel_atomic_check_planes(state); 6799 if (ret) 6800 goto fail; 6801 6802 ret = intel_compute_global_watermarks(state); 6803 if (ret) 6804 goto fail; 6805 6806 ret = intel_bw_atomic_check(state); 6807 if (ret) 6808 goto fail; 6809 6810 ret = intel_cdclk_atomic_check(state, &any_ms); 6811 if (ret) 6812 goto fail; 6813 6814 if (intel_any_crtc_needs_modeset(state)) 6815 any_ms = true; 6816 6817 if (any_ms) { 6818 ret = intel_modeset_checks(state); 6819 if (ret) 6820 goto fail; 6821 6822 ret = intel_modeset_calc_cdclk(state); 6823 if (ret) 6824 return ret; 6825 } 6826 6827 ret = intel_atomic_check_crtcs(state); 6828 if (ret) 6829 goto fail; 6830 6831 ret = intel_fbc_atomic_check(state); 6832 if (ret) 6833 goto fail; 6834 6835 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6836 new_crtc_state, i) { 6837 intel_color_assert_luts(new_crtc_state); 6838 6839 ret = intel_async_flip_check_hw(state, crtc); 6840 if (ret) 6841 goto fail; 6842 6843 /* Either full modeset or fastset (or neither), never both */ 6844 drm_WARN_ON(&dev_priv->drm, 6845 intel_crtc_needs_modeset(new_crtc_state) && 6846 intel_crtc_needs_fastset(new_crtc_state)); 6847 6848 if (!intel_crtc_needs_modeset(new_crtc_state) && 6849 !intel_crtc_needs_fastset(new_crtc_state)) 6850 continue; 6851 6852 intel_crtc_state_dump(new_crtc_state, state, 6853 intel_crtc_needs_modeset(new_crtc_state) ? 6854 "modeset" : "fastset"); 6855 } 6856 6857 return 0; 6858 6859 fail: 6860 if (ret == -EDEADLK) 6861 return ret; 6862 6863 /* 6864 * FIXME would probably be nice to know which crtc specifically 6865 * caused the failure, in cases where we can pinpoint it. 6866 */ 6867 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6868 new_crtc_state, i) 6869 intel_crtc_state_dump(new_crtc_state, state, "failed"); 6870 6871 return ret; 6872 } 6873 6874 static int intel_atomic_prepare_commit(struct intel_atomic_state *state) 6875 { 6876 struct intel_crtc_state *crtc_state; 6877 struct intel_crtc *crtc; 6878 int i, ret; 6879 6880 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base); 6881 if (ret < 0) 6882 return ret; 6883 6884 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6885 if (intel_crtc_needs_color_update(crtc_state)) 6886 intel_color_prepare_commit(crtc_state); 6887 } 6888 6889 return 0; 6890 } 6891 6892 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 6893 struct intel_crtc_state *crtc_state) 6894 { 6895 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6896 6897 if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes) 6898 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 6899 6900 if (crtc_state->has_pch_encoder) { 6901 enum pipe pch_transcoder = 6902 intel_crtc_pch_transcoder(crtc); 6903 6904 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true); 6905 } 6906 } 6907 6908 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, 6909 const struct intel_crtc_state *new_crtc_state) 6910 { 6911 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 6912 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6913 6914 /* 6915 * Update pipe size and adjust fitter if needed: the reason for this is 6916 * that in compute_mode_changes we check the native mode (not the pfit 6917 * mode) to see if we can flip rather than do a full mode set. In the 6918 * fastboot case, we'll flip, but if we don't update the pipesrc and 6919 * pfit state, we'll end up with a big fb scanned out into the wrong 6920 * sized surface. 6921 */ 6922 intel_set_pipe_src_size(new_crtc_state); 6923 6924 /* on skylake this is done by detaching scalers */ 6925 if (DISPLAY_VER(dev_priv) >= 9) { 6926 if (new_crtc_state->pch_pfit.enabled) 6927 skl_pfit_enable(new_crtc_state); 6928 } else if (HAS_PCH_SPLIT(dev_priv)) { 6929 if (new_crtc_state->pch_pfit.enabled) 6930 ilk_pfit_enable(new_crtc_state); 6931 else if (old_crtc_state->pch_pfit.enabled) 6932 ilk_pfit_disable(old_crtc_state); 6933 } 6934 6935 /* 6936 * The register is supposedly single buffered so perhaps 6937 * not 100% correct to do this here. But SKL+ calculate 6938 * this based on the adjust pixel rate so pfit changes do 6939 * affect it and so it must be updated for fastsets. 6940 * HSW/BDW only really need this here for fastboot, after 6941 * that the value should not change without a full modeset. 6942 */ 6943 if (DISPLAY_VER(dev_priv) >= 9 || 6944 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 6945 hsw_set_linetime_wm(new_crtc_state); 6946 6947 if (new_crtc_state->seamless_m_n) 6948 intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder, 6949 &new_crtc_state->dp_m_n); 6950 } 6951 6952 static void commit_pipe_pre_planes(struct intel_atomic_state *state, 6953 struct intel_crtc *crtc) 6954 { 6955 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6956 const struct intel_crtc_state *old_crtc_state = 6957 intel_atomic_get_old_crtc_state(state, crtc); 6958 const struct intel_crtc_state *new_crtc_state = 6959 intel_atomic_get_new_crtc_state(state, crtc); 6960 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 6961 6962 /* 6963 * During modesets pipe configuration was programmed as the 6964 * CRTC was enabled. 6965 */ 6966 if (!modeset) { 6967 if (intel_crtc_needs_color_update(new_crtc_state)) 6968 intel_color_commit_arm(new_crtc_state); 6969 6970 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 6971 bdw_set_pipe_misc(new_crtc_state); 6972 6973 if (intel_crtc_needs_fastset(new_crtc_state)) 6974 intel_pipe_fastset(old_crtc_state, new_crtc_state); 6975 } 6976 6977 intel_psr2_program_trans_man_trk_ctl(new_crtc_state); 6978 6979 intel_atomic_update_watermarks(state, crtc); 6980 } 6981 6982 static void commit_pipe_post_planes(struct intel_atomic_state *state, 6983 struct intel_crtc *crtc) 6984 { 6985 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6986 const struct intel_crtc_state *new_crtc_state = 6987 intel_atomic_get_new_crtc_state(state, crtc); 6988 6989 /* 6990 * Disable the scaler(s) after the plane(s) so that we don't 6991 * get a catastrophic underrun even if the two operations 6992 * end up happening in two different frames. 6993 */ 6994 if (DISPLAY_VER(dev_priv) >= 9 && 6995 !intel_crtc_needs_modeset(new_crtc_state)) 6996 skl_detach_scalers(new_crtc_state); 6997 } 6998 6999 static void intel_enable_crtc(struct intel_atomic_state *state, 7000 struct intel_crtc *crtc) 7001 { 7002 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7003 const struct intel_crtc_state *new_crtc_state = 7004 intel_atomic_get_new_crtc_state(state, crtc); 7005 7006 if (!intel_crtc_needs_modeset(new_crtc_state)) 7007 return; 7008 7009 intel_crtc_update_active_timings(new_crtc_state); 7010 7011 dev_priv->display.funcs.display->crtc_enable(state, crtc); 7012 7013 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 7014 return; 7015 7016 /* vblanks work again, re-enable pipe CRC. */ 7017 intel_crtc_enable_pipe_crc(crtc); 7018 } 7019 7020 static void intel_update_crtc(struct intel_atomic_state *state, 7021 struct intel_crtc *crtc) 7022 { 7023 struct drm_i915_private *i915 = to_i915(state->base.dev); 7024 const struct intel_crtc_state *old_crtc_state = 7025 intel_atomic_get_old_crtc_state(state, crtc); 7026 struct intel_crtc_state *new_crtc_state = 7027 intel_atomic_get_new_crtc_state(state, crtc); 7028 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 7029 7030 if (!modeset) { 7031 if (new_crtc_state->preload_luts && 7032 intel_crtc_needs_color_update(new_crtc_state)) 7033 intel_color_load_luts(new_crtc_state); 7034 7035 intel_pre_plane_update(state, crtc); 7036 7037 if (intel_crtc_needs_fastset(new_crtc_state)) 7038 intel_encoders_update_pipe(state, crtc); 7039 7040 if (DISPLAY_VER(i915) >= 11 && 7041 intel_crtc_needs_fastset(new_crtc_state)) 7042 icl_set_pipe_chicken(new_crtc_state); 7043 } 7044 7045 intel_fbc_update(state, crtc); 7046 7047 if (!modeset && 7048 intel_crtc_needs_color_update(new_crtc_state)) 7049 intel_color_commit_noarm(new_crtc_state); 7050 7051 intel_crtc_planes_update_noarm(state, crtc); 7052 7053 /* Perform vblank evasion around commit operation */ 7054 intel_pipe_update_start(new_crtc_state); 7055 7056 commit_pipe_pre_planes(state, crtc); 7057 7058 intel_crtc_planes_update_arm(state, crtc); 7059 7060 commit_pipe_post_planes(state, crtc); 7061 7062 intel_pipe_update_end(new_crtc_state); 7063 7064 /* 7065 * We usually enable FIFO underrun interrupts as part of the 7066 * CRTC enable sequence during modesets. But when we inherit a 7067 * valid pipe configuration from the BIOS we need to take care 7068 * of enabling them on the CRTC's first fastset. 7069 */ 7070 if (intel_crtc_needs_fastset(new_crtc_state) && !modeset && 7071 old_crtc_state->inherited) 7072 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state); 7073 } 7074 7075 static void intel_old_crtc_state_disables(struct intel_atomic_state *state, 7076 struct intel_crtc_state *old_crtc_state, 7077 struct intel_crtc_state *new_crtc_state, 7078 struct intel_crtc *crtc) 7079 { 7080 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7081 7082 /* 7083 * We need to disable pipe CRC before disabling the pipe, 7084 * or we race against vblank off. 7085 */ 7086 intel_crtc_disable_pipe_crc(crtc); 7087 7088 dev_priv->display.funcs.display->crtc_disable(state, crtc); 7089 crtc->active = false; 7090 intel_fbc_disable(crtc); 7091 intel_disable_shared_dpll(old_crtc_state); 7092 7093 if (!new_crtc_state->hw.active) 7094 intel_initial_watermarks(state, crtc); 7095 } 7096 7097 static void intel_commit_modeset_disables(struct intel_atomic_state *state) 7098 { 7099 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 7100 struct intel_crtc *crtc; 7101 u32 handled = 0; 7102 int i; 7103 7104 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7105 new_crtc_state, i) { 7106 if (!intel_crtc_needs_modeset(new_crtc_state)) 7107 continue; 7108 7109 if (!old_crtc_state->hw.active) 7110 continue; 7111 7112 intel_pre_plane_update(state, crtc); 7113 intel_crtc_disable_planes(state, crtc); 7114 } 7115 7116 /* Only disable port sync and MST slaves */ 7117 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7118 new_crtc_state, i) { 7119 if (!intel_crtc_needs_modeset(new_crtc_state)) 7120 continue; 7121 7122 if (!old_crtc_state->hw.active) 7123 continue; 7124 7125 /* In case of Transcoder port Sync master slave CRTCs can be 7126 * assigned in any order and we need to make sure that 7127 * slave CRTCs are disabled first and then master CRTC since 7128 * Slave vblanks are masked till Master Vblanks. 7129 */ 7130 if (!is_trans_port_sync_slave(old_crtc_state) && 7131 !intel_dp_mst_is_slave_trans(old_crtc_state) && 7132 !intel_crtc_is_bigjoiner_slave(old_crtc_state)) 7133 continue; 7134 7135 intel_old_crtc_state_disables(state, old_crtc_state, 7136 new_crtc_state, crtc); 7137 handled |= BIT(crtc->pipe); 7138 } 7139 7140 /* Disable everything else left on */ 7141 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7142 new_crtc_state, i) { 7143 if (!intel_crtc_needs_modeset(new_crtc_state) || 7144 (handled & BIT(crtc->pipe))) 7145 continue; 7146 7147 if (!old_crtc_state->hw.active) 7148 continue; 7149 7150 intel_old_crtc_state_disables(state, old_crtc_state, 7151 new_crtc_state, crtc); 7152 } 7153 } 7154 7155 static void intel_commit_modeset_enables(struct intel_atomic_state *state) 7156 { 7157 struct intel_crtc_state *new_crtc_state; 7158 struct intel_crtc *crtc; 7159 int i; 7160 7161 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7162 if (!new_crtc_state->hw.active) 7163 continue; 7164 7165 intel_enable_crtc(state, crtc); 7166 intel_update_crtc(state, crtc); 7167 } 7168 } 7169 7170 static void skl_commit_modeset_enables(struct intel_atomic_state *state) 7171 { 7172 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 7173 struct intel_crtc *crtc; 7174 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7175 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; 7176 u8 update_pipes = 0, modeset_pipes = 0; 7177 int i; 7178 7179 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7180 enum pipe pipe = crtc->pipe; 7181 7182 if (!new_crtc_state->hw.active) 7183 continue; 7184 7185 /* ignore allocations for crtc's that have been turned off. */ 7186 if (!intel_crtc_needs_modeset(new_crtc_state)) { 7187 entries[pipe] = old_crtc_state->wm.skl.ddb; 7188 update_pipes |= BIT(pipe); 7189 } else { 7190 modeset_pipes |= BIT(pipe); 7191 } 7192 } 7193 7194 /* 7195 * Whenever the number of active pipes changes, we need to make sure we 7196 * update the pipes in the right order so that their ddb allocations 7197 * never overlap with each other between CRTC updates. Otherwise we'll 7198 * cause pipe underruns and other bad stuff. 7199 * 7200 * So first lets enable all pipes that do not need a fullmodeset as 7201 * those don't have any external dependency. 7202 */ 7203 while (update_pipes) { 7204 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7205 new_crtc_state, i) { 7206 enum pipe pipe = crtc->pipe; 7207 7208 if ((update_pipes & BIT(pipe)) == 0) 7209 continue; 7210 7211 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 7212 entries, I915_MAX_PIPES, pipe)) 7213 continue; 7214 7215 entries[pipe] = new_crtc_state->wm.skl.ddb; 7216 update_pipes &= ~BIT(pipe); 7217 7218 intel_update_crtc(state, crtc); 7219 7220 /* 7221 * If this is an already active pipe, it's DDB changed, 7222 * and this isn't the last pipe that needs updating 7223 * then we need to wait for a vblank to pass for the 7224 * new ddb allocation to take effect. 7225 */ 7226 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, 7227 &old_crtc_state->wm.skl.ddb) && 7228 (update_pipes | modeset_pipes)) 7229 intel_crtc_wait_for_next_vblank(crtc); 7230 } 7231 } 7232 7233 update_pipes = modeset_pipes; 7234 7235 /* 7236 * Enable all pipes that needs a modeset and do not depends on other 7237 * pipes 7238 */ 7239 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7240 enum pipe pipe = crtc->pipe; 7241 7242 if ((modeset_pipes & BIT(pipe)) == 0) 7243 continue; 7244 7245 if (intel_dp_mst_is_slave_trans(new_crtc_state) || 7246 is_trans_port_sync_master(new_crtc_state) || 7247 intel_crtc_is_bigjoiner_master(new_crtc_state)) 7248 continue; 7249 7250 modeset_pipes &= ~BIT(pipe); 7251 7252 intel_enable_crtc(state, crtc); 7253 } 7254 7255 /* 7256 * Then we enable all remaining pipes that depend on other 7257 * pipes: MST slaves and port sync masters, big joiner master 7258 */ 7259 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7260 enum pipe pipe = crtc->pipe; 7261 7262 if ((modeset_pipes & BIT(pipe)) == 0) 7263 continue; 7264 7265 modeset_pipes &= ~BIT(pipe); 7266 7267 intel_enable_crtc(state, crtc); 7268 } 7269 7270 /* 7271 * Finally we do the plane updates/etc. for all pipes that got enabled. 7272 */ 7273 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7274 enum pipe pipe = crtc->pipe; 7275 7276 if ((update_pipes & BIT(pipe)) == 0) 7277 continue; 7278 7279 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 7280 entries, I915_MAX_PIPES, pipe)); 7281 7282 entries[pipe] = new_crtc_state->wm.skl.ddb; 7283 update_pipes &= ~BIT(pipe); 7284 7285 intel_update_crtc(state, crtc); 7286 } 7287 7288 drm_WARN_ON(&dev_priv->drm, modeset_pipes); 7289 drm_WARN_ON(&dev_priv->drm, update_pipes); 7290 } 7291 7292 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) 7293 { 7294 struct intel_atomic_state *state, *next; 7295 struct llist_node *freed; 7296 7297 freed = llist_del_all(&dev_priv->display.atomic_helper.free_list); 7298 llist_for_each_entry_safe(state, next, freed, freed) 7299 drm_atomic_state_put(&state->base); 7300 } 7301 7302 static void intel_atomic_helper_free_state_worker(struct work_struct *work) 7303 { 7304 struct drm_i915_private *dev_priv = 7305 container_of(work, typeof(*dev_priv), display.atomic_helper.free_work); 7306 7307 intel_atomic_helper_free_state(dev_priv); 7308 } 7309 7310 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) 7311 { 7312 struct wait_queue_entry wait_fence, wait_reset; 7313 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); 7314 7315 init_wait_entry(&wait_fence, 0); 7316 init_wait_entry(&wait_reset, 0); 7317 for (;;) { 7318 prepare_to_wait(&intel_state->commit_ready.wait, 7319 &wait_fence, TASK_UNINTERRUPTIBLE); 7320 prepare_to_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 7321 I915_RESET_MODESET), 7322 &wait_reset, TASK_UNINTERRUPTIBLE); 7323 7324 7325 if (i915_sw_fence_done(&intel_state->commit_ready) || 7326 test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags)) 7327 break; 7328 7329 schedule(); 7330 } 7331 finish_wait(&intel_state->commit_ready.wait, &wait_fence); 7332 finish_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 7333 I915_RESET_MODESET), 7334 &wait_reset); 7335 } 7336 7337 static void intel_atomic_cleanup_work(struct work_struct *work) 7338 { 7339 struct intel_atomic_state *state = 7340 container_of(work, struct intel_atomic_state, base.commit_work); 7341 struct drm_i915_private *i915 = to_i915(state->base.dev); 7342 struct intel_crtc_state *old_crtc_state; 7343 struct intel_crtc *crtc; 7344 int i; 7345 7346 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) 7347 intel_color_cleanup_commit(old_crtc_state); 7348 7349 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base); 7350 drm_atomic_helper_commit_cleanup_done(&state->base); 7351 drm_atomic_state_put(&state->base); 7352 7353 intel_atomic_helper_free_state(i915); 7354 } 7355 7356 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state) 7357 { 7358 struct drm_i915_private *i915 = to_i915(state->base.dev); 7359 struct intel_plane *plane; 7360 struct intel_plane_state *plane_state; 7361 int i; 7362 7363 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 7364 struct drm_framebuffer *fb = plane_state->hw.fb; 7365 int cc_plane; 7366 int ret; 7367 7368 if (!fb) 7369 continue; 7370 7371 cc_plane = intel_fb_rc_ccs_cc_plane(fb); 7372 if (cc_plane < 0) 7373 continue; 7374 7375 /* 7376 * The layout of the fast clear color value expected by HW 7377 * (the DRM ABI requiring this value to be located in fb at 7378 * offset 0 of cc plane, plane #2 previous generations or 7379 * plane #1 for flat ccs): 7380 * - 4 x 4 bytes per-channel value 7381 * (in surface type specific float/int format provided by the fb user) 7382 * - 8 bytes native color value used by the display 7383 * (converted/written by GPU during a fast clear operation using the 7384 * above per-channel values) 7385 * 7386 * The commit's FB prepare hook already ensured that FB obj is pinned and the 7387 * caller made sure that the object is synced wrt. the related color clear value 7388 * GPU write on it. 7389 */ 7390 ret = i915_gem_object_read_from_page(intel_fb_obj(fb), 7391 fb->offsets[cc_plane] + 16, 7392 &plane_state->ccval, 7393 sizeof(plane_state->ccval)); 7394 /* The above could only fail if the FB obj has an unexpected backing store type. */ 7395 drm_WARN_ON(&i915->drm, ret); 7396 } 7397 } 7398 7399 static void intel_atomic_commit_tail(struct intel_atomic_state *state) 7400 { 7401 struct drm_device *dev = state->base.dev; 7402 struct drm_i915_private *dev_priv = to_i915(dev); 7403 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 7404 struct intel_crtc *crtc; 7405 struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {}; 7406 intel_wakeref_t wakeref = 0; 7407 int i; 7408 7409 intel_atomic_commit_fence_wait(state); 7410 7411 drm_atomic_helper_wait_for_dependencies(&state->base); 7412 drm_dp_mst_atomic_wait_for_dependencies(&state->base); 7413 7414 if (state->modeset) 7415 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); 7416 7417 intel_atomic_prepare_plane_clear_colors(state); 7418 7419 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7420 new_crtc_state, i) { 7421 if (intel_crtc_needs_modeset(new_crtc_state) || 7422 intel_crtc_needs_fastset(new_crtc_state)) 7423 intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]); 7424 } 7425 7426 intel_commit_modeset_disables(state); 7427 7428 /* FIXME: Eventually get rid of our crtc->config pointer */ 7429 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7430 crtc->config = new_crtc_state; 7431 7432 if (state->modeset) { 7433 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base); 7434 7435 intel_set_cdclk_pre_plane_update(state); 7436 7437 intel_modeset_verify_disabled(dev_priv, state); 7438 } 7439 7440 intel_sagv_pre_plane_update(state); 7441 7442 /* Complete the events for pipes that have now been disabled */ 7443 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7444 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 7445 7446 /* Complete events for now disable pipes here. */ 7447 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) { 7448 spin_lock_irq(&dev->event_lock); 7449 drm_crtc_send_vblank_event(&crtc->base, 7450 new_crtc_state->uapi.event); 7451 spin_unlock_irq(&dev->event_lock); 7452 7453 new_crtc_state->uapi.event = NULL; 7454 } 7455 } 7456 7457 intel_encoders_update_prepare(state); 7458 7459 intel_dbuf_pre_plane_update(state); 7460 intel_mbus_dbox_update(state); 7461 7462 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7463 if (new_crtc_state->do_async_flip) 7464 intel_crtc_enable_flip_done(state, crtc); 7465 } 7466 7467 /* Now enable the clocks, plane, pipe, and connectors that we set up. */ 7468 dev_priv->display.funcs.display->commit_modeset_enables(state); 7469 7470 intel_encoders_update_complete(state); 7471 7472 if (state->modeset) 7473 intel_set_cdclk_post_plane_update(state); 7474 7475 intel_wait_for_vblank_workers(state); 7476 7477 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here 7478 * already, but still need the state for the delayed optimization. To 7479 * fix this: 7480 * - wrap the optimization/post_plane_update stuff into a per-crtc work. 7481 * - schedule that vblank worker _before_ calling hw_done 7482 * - at the start of commit_tail, cancel it _synchrously 7483 * - switch over to the vblank wait helper in the core after that since 7484 * we don't need out special handling any more. 7485 */ 7486 drm_atomic_helper_wait_for_flip_done(dev, &state->base); 7487 7488 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7489 if (new_crtc_state->do_async_flip) 7490 intel_crtc_disable_flip_done(state, crtc); 7491 } 7492 7493 /* 7494 * Now that the vblank has passed, we can go ahead and program the 7495 * optimal watermarks on platforms that need two-step watermark 7496 * programming. 7497 * 7498 * TODO: Move this (and other cleanup) to an async worker eventually. 7499 */ 7500 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7501 new_crtc_state, i) { 7502 /* 7503 * Gen2 reports pipe underruns whenever all planes are disabled. 7504 * So re-enable underrun reporting after some planes get enabled. 7505 * 7506 * We do this before .optimize_watermarks() so that we have a 7507 * chance of catching underruns with the intermediate watermarks 7508 * vs. the new plane configuration. 7509 */ 7510 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state)) 7511 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 7512 7513 intel_optimize_watermarks(state, crtc); 7514 } 7515 7516 intel_dbuf_post_plane_update(state); 7517 intel_psr_post_plane_update(state); 7518 7519 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7520 intel_post_plane_update(state, crtc); 7521 7522 intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]); 7523 7524 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state); 7525 7526 /* Must be done after gamma readout due to HSW split gamma vs. IPS w/a */ 7527 hsw_ips_post_update(state, crtc); 7528 7529 /* 7530 * Activate DRRS after state readout to avoid 7531 * dp_m_n vs. dp_m2_n2 confusion on BDW+. 7532 */ 7533 intel_drrs_activate(new_crtc_state); 7534 7535 /* 7536 * DSB cleanup is done in cleanup_work aligning with framebuffer 7537 * cleanup. So copy and reset the dsb structure to sync with 7538 * commit_done and later do dsb cleanup in cleanup_work. 7539 * 7540 * FIXME get rid of this funny new->old swapping 7541 */ 7542 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb); 7543 } 7544 7545 /* Underruns don't always raise interrupts, so check manually */ 7546 intel_check_cpu_fifo_underruns(dev_priv); 7547 intel_check_pch_fifo_underruns(dev_priv); 7548 7549 if (state->modeset) 7550 intel_verify_planes(state); 7551 7552 intel_sagv_post_plane_update(state); 7553 7554 drm_atomic_helper_commit_hw_done(&state->base); 7555 7556 if (state->modeset) { 7557 /* As one of the primary mmio accessors, KMS has a high 7558 * likelihood of triggering bugs in unclaimed access. After we 7559 * finish modesetting, see if an error has been flagged, and if 7560 * so enable debugging for the next modeset - and hope we catch 7561 * the culprit. 7562 */ 7563 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); 7564 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref); 7565 } 7566 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7567 7568 /* 7569 * Defer the cleanup of the old state to a separate worker to not 7570 * impede the current task (userspace for blocking modesets) that 7571 * are executed inline. For out-of-line asynchronous modesets/flips, 7572 * deferring to a new worker seems overkill, but we would place a 7573 * schedule point (cond_resched()) here anyway to keep latencies 7574 * down. 7575 */ 7576 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work); 7577 queue_work(system_highpri_wq, &state->base.commit_work); 7578 } 7579 7580 static void intel_atomic_commit_work(struct work_struct *work) 7581 { 7582 struct intel_atomic_state *state = 7583 container_of(work, struct intel_atomic_state, base.commit_work); 7584 7585 intel_atomic_commit_tail(state); 7586 } 7587 7588 static int 7589 intel_atomic_commit_ready(struct i915_sw_fence *fence, 7590 enum i915_sw_fence_notify notify) 7591 { 7592 struct intel_atomic_state *state = 7593 container_of(fence, struct intel_atomic_state, commit_ready); 7594 7595 switch (notify) { 7596 case FENCE_COMPLETE: 7597 /* we do blocking waits in the worker, nothing to do here */ 7598 break; 7599 case FENCE_FREE: 7600 { 7601 struct intel_atomic_helper *helper = 7602 &to_i915(state->base.dev)->display.atomic_helper; 7603 7604 if (llist_add(&state->freed, &helper->free_list)) 7605 schedule_work(&helper->free_work); 7606 break; 7607 } 7608 } 7609 7610 return NOTIFY_DONE; 7611 } 7612 7613 static void intel_atomic_track_fbs(struct intel_atomic_state *state) 7614 { 7615 struct intel_plane_state *old_plane_state, *new_plane_state; 7616 struct intel_plane *plane; 7617 int i; 7618 7619 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 7620 new_plane_state, i) 7621 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), 7622 to_intel_frontbuffer(new_plane_state->hw.fb), 7623 plane->frontbuffer_bit); 7624 } 7625 7626 static int intel_atomic_commit(struct drm_device *dev, 7627 struct drm_atomic_state *_state, 7628 bool nonblock) 7629 { 7630 struct intel_atomic_state *state = to_intel_atomic_state(_state); 7631 struct drm_i915_private *dev_priv = to_i915(dev); 7632 int ret = 0; 7633 7634 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 7635 7636 drm_atomic_state_get(&state->base); 7637 i915_sw_fence_init(&state->commit_ready, 7638 intel_atomic_commit_ready); 7639 7640 /* 7641 * The intel_legacy_cursor_update() fast path takes care 7642 * of avoiding the vblank waits for simple cursor 7643 * movement and flips. For cursor on/off and size changes, 7644 * we want to perform the vblank waits so that watermark 7645 * updates happen during the correct frames. Gen9+ have 7646 * double buffered watermarks and so shouldn't need this. 7647 * 7648 * Unset state->legacy_cursor_update before the call to 7649 * drm_atomic_helper_setup_commit() because otherwise 7650 * drm_atomic_helper_wait_for_flip_done() is a noop and 7651 * we get FIFO underruns because we didn't wait 7652 * for vblank. 7653 * 7654 * FIXME doing watermarks and fb cleanup from a vblank worker 7655 * (assuming we had any) would solve these problems. 7656 */ 7657 if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) { 7658 struct intel_crtc_state *new_crtc_state; 7659 struct intel_crtc *crtc; 7660 int i; 7661 7662 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7663 if (new_crtc_state->wm.need_postvbl_update || 7664 new_crtc_state->update_wm_post) 7665 state->base.legacy_cursor_update = false; 7666 } 7667 7668 ret = intel_atomic_prepare_commit(state); 7669 if (ret) { 7670 drm_dbg_atomic(&dev_priv->drm, 7671 "Preparing state failed with %i\n", ret); 7672 i915_sw_fence_commit(&state->commit_ready); 7673 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7674 return ret; 7675 } 7676 7677 ret = drm_atomic_helper_setup_commit(&state->base, nonblock); 7678 if (!ret) 7679 ret = drm_atomic_helper_swap_state(&state->base, true); 7680 if (!ret) 7681 intel_atomic_swap_global_state(state); 7682 7683 if (ret) { 7684 struct intel_crtc_state *new_crtc_state; 7685 struct intel_crtc *crtc; 7686 int i; 7687 7688 i915_sw_fence_commit(&state->commit_ready); 7689 7690 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7691 intel_color_cleanup_commit(new_crtc_state); 7692 7693 drm_atomic_helper_cleanup_planes(dev, &state->base); 7694 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7695 return ret; 7696 } 7697 intel_shared_dpll_swap_state(state); 7698 intel_atomic_track_fbs(state); 7699 7700 drm_atomic_state_get(&state->base); 7701 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work); 7702 7703 i915_sw_fence_commit(&state->commit_ready); 7704 if (nonblock && state->modeset) { 7705 queue_work(dev_priv->display.wq.modeset, &state->base.commit_work); 7706 } else if (nonblock) { 7707 queue_work(dev_priv->display.wq.flip, &state->base.commit_work); 7708 } else { 7709 if (state->modeset) 7710 flush_workqueue(dev_priv->display.wq.modeset); 7711 intel_atomic_commit_tail(state); 7712 } 7713 7714 return 0; 7715 } 7716 7717 /** 7718 * intel_plane_destroy - destroy a plane 7719 * @plane: plane to destroy 7720 * 7721 * Common destruction function for all types of planes (primary, cursor, 7722 * sprite). 7723 */ 7724 void intel_plane_destroy(struct drm_plane *plane) 7725 { 7726 drm_plane_cleanup(plane); 7727 kfree(to_intel_plane(plane)); 7728 } 7729 7730 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv) 7731 { 7732 struct intel_plane *plane; 7733 7734 for_each_intel_plane(&dev_priv->drm, plane) { 7735 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, 7736 plane->pipe); 7737 7738 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base); 7739 } 7740 } 7741 7742 7743 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 7744 struct drm_file *file) 7745 { 7746 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; 7747 struct drm_crtc *drmmode_crtc; 7748 struct intel_crtc *crtc; 7749 7750 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id); 7751 if (!drmmode_crtc) 7752 return -ENOENT; 7753 7754 crtc = to_intel_crtc(drmmode_crtc); 7755 pipe_from_crtc_id->pipe = crtc->pipe; 7756 7757 return 0; 7758 } 7759 7760 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder) 7761 { 7762 struct drm_device *dev = encoder->base.dev; 7763 struct intel_encoder *source_encoder; 7764 u32 possible_clones = 0; 7765 7766 for_each_intel_encoder(dev, source_encoder) { 7767 if (encoders_cloneable(encoder, source_encoder)) 7768 possible_clones |= drm_encoder_mask(&source_encoder->base); 7769 } 7770 7771 return possible_clones; 7772 } 7773 7774 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder) 7775 { 7776 struct drm_device *dev = encoder->base.dev; 7777 struct intel_crtc *crtc; 7778 u32 possible_crtcs = 0; 7779 7780 for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask) 7781 possible_crtcs |= drm_crtc_mask(&crtc->base); 7782 7783 return possible_crtcs; 7784 } 7785 7786 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv) 7787 { 7788 if (!IS_MOBILE(dev_priv)) 7789 return false; 7790 7791 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0) 7792 return false; 7793 7794 if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE)) 7795 return false; 7796 7797 return true; 7798 } 7799 7800 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv) 7801 { 7802 if (DISPLAY_VER(dev_priv) >= 9) 7803 return false; 7804 7805 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) 7806 return false; 7807 7808 if (HAS_PCH_LPT_H(dev_priv) && 7809 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) 7810 return false; 7811 7812 /* DDI E can't be used if DDI A requires 4 lanes */ 7813 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 7814 return false; 7815 7816 if (!dev_priv->display.vbt.int_crt_support) 7817 return false; 7818 7819 return true; 7820 } 7821 7822 static void intel_setup_outputs(struct drm_i915_private *dev_priv) 7823 { 7824 struct intel_encoder *encoder; 7825 bool dpd_is_edp = false; 7826 7827 intel_pps_unlock_regs_wa(dev_priv); 7828 7829 if (!HAS_DISPLAY(dev_priv)) 7830 return; 7831 7832 if (IS_DG2(dev_priv)) { 7833 intel_ddi_init(dev_priv, PORT_A); 7834 intel_ddi_init(dev_priv, PORT_B); 7835 intel_ddi_init(dev_priv, PORT_C); 7836 intel_ddi_init(dev_priv, PORT_D_XELPD); 7837 intel_ddi_init(dev_priv, PORT_TC1); 7838 } else if (IS_ALDERLAKE_P(dev_priv)) { 7839 intel_ddi_init(dev_priv, PORT_A); 7840 intel_ddi_init(dev_priv, PORT_B); 7841 intel_ddi_init(dev_priv, PORT_TC1); 7842 intel_ddi_init(dev_priv, PORT_TC2); 7843 intel_ddi_init(dev_priv, PORT_TC3); 7844 intel_ddi_init(dev_priv, PORT_TC4); 7845 icl_dsi_init(dev_priv); 7846 } else if (IS_ALDERLAKE_S(dev_priv)) { 7847 intel_ddi_init(dev_priv, PORT_A); 7848 intel_ddi_init(dev_priv, PORT_TC1); 7849 intel_ddi_init(dev_priv, PORT_TC2); 7850 intel_ddi_init(dev_priv, PORT_TC3); 7851 intel_ddi_init(dev_priv, PORT_TC4); 7852 } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) { 7853 intel_ddi_init(dev_priv, PORT_A); 7854 intel_ddi_init(dev_priv, PORT_B); 7855 intel_ddi_init(dev_priv, PORT_TC1); 7856 intel_ddi_init(dev_priv, PORT_TC2); 7857 } else if (DISPLAY_VER(dev_priv) >= 12) { 7858 intel_ddi_init(dev_priv, PORT_A); 7859 intel_ddi_init(dev_priv, PORT_B); 7860 intel_ddi_init(dev_priv, PORT_TC1); 7861 intel_ddi_init(dev_priv, PORT_TC2); 7862 intel_ddi_init(dev_priv, PORT_TC3); 7863 intel_ddi_init(dev_priv, PORT_TC4); 7864 intel_ddi_init(dev_priv, PORT_TC5); 7865 intel_ddi_init(dev_priv, PORT_TC6); 7866 icl_dsi_init(dev_priv); 7867 } else if (IS_JSL_EHL(dev_priv)) { 7868 intel_ddi_init(dev_priv, PORT_A); 7869 intel_ddi_init(dev_priv, PORT_B); 7870 intel_ddi_init(dev_priv, PORT_C); 7871 intel_ddi_init(dev_priv, PORT_D); 7872 icl_dsi_init(dev_priv); 7873 } else if (DISPLAY_VER(dev_priv) == 11) { 7874 intel_ddi_init(dev_priv, PORT_A); 7875 intel_ddi_init(dev_priv, PORT_B); 7876 intel_ddi_init(dev_priv, PORT_C); 7877 intel_ddi_init(dev_priv, PORT_D); 7878 intel_ddi_init(dev_priv, PORT_E); 7879 intel_ddi_init(dev_priv, PORT_F); 7880 icl_dsi_init(dev_priv); 7881 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 7882 intel_ddi_init(dev_priv, PORT_A); 7883 intel_ddi_init(dev_priv, PORT_B); 7884 intel_ddi_init(dev_priv, PORT_C); 7885 vlv_dsi_init(dev_priv); 7886 } else if (DISPLAY_VER(dev_priv) >= 9) { 7887 intel_ddi_init(dev_priv, PORT_A); 7888 intel_ddi_init(dev_priv, PORT_B); 7889 intel_ddi_init(dev_priv, PORT_C); 7890 intel_ddi_init(dev_priv, PORT_D); 7891 intel_ddi_init(dev_priv, PORT_E); 7892 } else if (HAS_DDI(dev_priv)) { 7893 u32 found; 7894 7895 if (intel_ddi_crt_present(dev_priv)) 7896 intel_crt_init(dev_priv); 7897 7898 /* Haswell uses DDI functions to detect digital outputs. */ 7899 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 7900 if (found) 7901 intel_ddi_init(dev_priv, PORT_A); 7902 7903 found = intel_de_read(dev_priv, SFUSE_STRAP); 7904 if (found & SFUSE_STRAP_DDIB_DETECTED) 7905 intel_ddi_init(dev_priv, PORT_B); 7906 if (found & SFUSE_STRAP_DDIC_DETECTED) 7907 intel_ddi_init(dev_priv, PORT_C); 7908 if (found & SFUSE_STRAP_DDID_DETECTED) 7909 intel_ddi_init(dev_priv, PORT_D); 7910 if (found & SFUSE_STRAP_DDIF_DETECTED) 7911 intel_ddi_init(dev_priv, PORT_F); 7912 } else if (HAS_PCH_SPLIT(dev_priv)) { 7913 int found; 7914 7915 /* 7916 * intel_edp_init_connector() depends on this completing first, 7917 * to prevent the registration of both eDP and LVDS and the 7918 * incorrect sharing of the PPS. 7919 */ 7920 intel_lvds_init(dev_priv); 7921 intel_crt_init(dev_priv); 7922 7923 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D); 7924 7925 if (ilk_has_edp_a(dev_priv)) 7926 g4x_dp_init(dev_priv, DP_A, PORT_A); 7927 7928 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) { 7929 /* PCH SDVOB multiplex with HDMIB */ 7930 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); 7931 if (!found) 7932 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); 7933 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED)) 7934 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B); 7935 } 7936 7937 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED) 7938 g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); 7939 7940 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED) 7941 g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D); 7942 7943 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED) 7944 g4x_dp_init(dev_priv, PCH_DP_C, PORT_C); 7945 7946 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED) 7947 g4x_dp_init(dev_priv, PCH_DP_D, PORT_D); 7948 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 7949 bool has_edp, has_port; 7950 7951 if (IS_VALLEYVIEW(dev_priv) && dev_priv->display.vbt.int_crt_support) 7952 intel_crt_init(dev_priv); 7953 7954 /* 7955 * The DP_DETECTED bit is the latched state of the DDC 7956 * SDA pin at boot. However since eDP doesn't require DDC 7957 * (no way to plug in a DP->HDMI dongle) the DDC pins for 7958 * eDP ports may have been muxed to an alternate function. 7959 * Thus we can't rely on the DP_DETECTED bit alone to detect 7960 * eDP ports. Consult the VBT as well as DP_DETECTED to 7961 * detect eDP ports. 7962 * 7963 * Sadly the straps seem to be missing sometimes even for HDMI 7964 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap 7965 * and VBT for the presence of the port. Additionally we can't 7966 * trust the port type the VBT declares as we've seen at least 7967 * HDMI ports that the VBT claim are DP or eDP. 7968 */ 7969 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B); 7970 has_port = intel_bios_is_port_present(dev_priv, PORT_B); 7971 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port) 7972 has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B); 7973 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) 7974 g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); 7975 7976 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C); 7977 has_port = intel_bios_is_port_present(dev_priv, PORT_C); 7978 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port) 7979 has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C); 7980 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) 7981 g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); 7982 7983 if (IS_CHERRYVIEW(dev_priv)) { 7984 /* 7985 * eDP not supported on port D, 7986 * so no need to worry about it 7987 */ 7988 has_port = intel_bios_is_port_present(dev_priv, PORT_D); 7989 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port) 7990 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D); 7991 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port) 7992 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D); 7993 } 7994 7995 vlv_dsi_init(dev_priv); 7996 } else if (IS_PINEVIEW(dev_priv)) { 7997 intel_lvds_init(dev_priv); 7998 intel_crt_init(dev_priv); 7999 } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) { 8000 bool found = false; 8001 8002 if (IS_MOBILE(dev_priv)) 8003 intel_lvds_init(dev_priv); 8004 8005 intel_crt_init(dev_priv); 8006 8007 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 8008 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n"); 8009 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); 8010 if (!found && IS_G4X(dev_priv)) { 8011 drm_dbg_kms(&dev_priv->drm, 8012 "probing HDMI on SDVOB\n"); 8013 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); 8014 } 8015 8016 if (!found && IS_G4X(dev_priv)) 8017 g4x_dp_init(dev_priv, DP_B, PORT_B); 8018 } 8019 8020 /* Before G4X SDVOC doesn't have its own detect register */ 8021 8022 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 8023 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n"); 8024 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); 8025 } 8026 8027 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) { 8028 8029 if (IS_G4X(dev_priv)) { 8030 drm_dbg_kms(&dev_priv->drm, 8031 "probing HDMI on SDVOC\n"); 8032 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); 8033 } 8034 if (IS_G4X(dev_priv)) 8035 g4x_dp_init(dev_priv, DP_C, PORT_C); 8036 } 8037 8038 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED)) 8039 g4x_dp_init(dev_priv, DP_D, PORT_D); 8040 8041 if (SUPPORTS_TV(dev_priv)) 8042 intel_tv_init(dev_priv); 8043 } else if (DISPLAY_VER(dev_priv) == 2) { 8044 if (IS_I85X(dev_priv)) 8045 intel_lvds_init(dev_priv); 8046 8047 intel_crt_init(dev_priv); 8048 intel_dvo_init(dev_priv); 8049 } 8050 8051 for_each_intel_encoder(&dev_priv->drm, encoder) { 8052 encoder->base.possible_crtcs = 8053 intel_encoder_possible_crtcs(encoder); 8054 encoder->base.possible_clones = 8055 intel_encoder_possible_clones(encoder); 8056 } 8057 8058 intel_init_pch_refclk(dev_priv); 8059 8060 drm_helper_move_panel_connectors_to_head(&dev_priv->drm); 8061 } 8062 8063 static int max_dotclock(struct drm_i915_private *i915) 8064 { 8065 int max_dotclock = i915->max_dotclk_freq; 8066 8067 /* icl+ might use bigjoiner */ 8068 if (DISPLAY_VER(i915) >= 11) 8069 max_dotclock *= 2; 8070 8071 return max_dotclock; 8072 } 8073 8074 static enum drm_mode_status 8075 intel_mode_valid(struct drm_device *dev, 8076 const struct drm_display_mode *mode) 8077 { 8078 struct drm_i915_private *dev_priv = to_i915(dev); 8079 int hdisplay_max, htotal_max; 8080 int vdisplay_max, vtotal_max; 8081 8082 /* 8083 * Can't reject DBLSCAN here because Xorg ddxen can add piles 8084 * of DBLSCAN modes to the output's mode list when they detect 8085 * the scaling mode property on the connector. And they don't 8086 * ask the kernel to validate those modes in any way until 8087 * modeset time at which point the client gets a protocol error. 8088 * So in order to not upset those clients we silently ignore the 8089 * DBLSCAN flag on such connectors. For other connectors we will 8090 * reject modes with the DBLSCAN flag in encoder->compute_config(). 8091 * And we always reject DBLSCAN modes in connector->mode_valid() 8092 * as we never want such modes on the connector's mode list. 8093 */ 8094 8095 if (mode->vscan > 1) 8096 return MODE_NO_VSCAN; 8097 8098 if (mode->flags & DRM_MODE_FLAG_HSKEW) 8099 return MODE_H_ILLEGAL; 8100 8101 if (mode->flags & (DRM_MODE_FLAG_CSYNC | 8102 DRM_MODE_FLAG_NCSYNC | 8103 DRM_MODE_FLAG_PCSYNC)) 8104 return MODE_HSYNC; 8105 8106 if (mode->flags & (DRM_MODE_FLAG_BCAST | 8107 DRM_MODE_FLAG_PIXMUX | 8108 DRM_MODE_FLAG_CLKDIV2)) 8109 return MODE_BAD; 8110 8111 /* 8112 * Reject clearly excessive dotclocks early to 8113 * avoid having to worry about huge integers later. 8114 */ 8115 if (mode->clock > max_dotclock(dev_priv)) 8116 return MODE_CLOCK_HIGH; 8117 8118 /* Transcoder timing limits */ 8119 if (DISPLAY_VER(dev_priv) >= 11) { 8120 hdisplay_max = 16384; 8121 vdisplay_max = 8192; 8122 htotal_max = 16384; 8123 vtotal_max = 8192; 8124 } else if (DISPLAY_VER(dev_priv) >= 9 || 8125 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 8126 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ 8127 vdisplay_max = 4096; 8128 htotal_max = 8192; 8129 vtotal_max = 8192; 8130 } else if (DISPLAY_VER(dev_priv) >= 3) { 8131 hdisplay_max = 4096; 8132 vdisplay_max = 4096; 8133 htotal_max = 8192; 8134 vtotal_max = 8192; 8135 } else { 8136 hdisplay_max = 2048; 8137 vdisplay_max = 2048; 8138 htotal_max = 4096; 8139 vtotal_max = 4096; 8140 } 8141 8142 if (mode->hdisplay > hdisplay_max || 8143 mode->hsync_start > htotal_max || 8144 mode->hsync_end > htotal_max || 8145 mode->htotal > htotal_max) 8146 return MODE_H_ILLEGAL; 8147 8148 if (mode->vdisplay > vdisplay_max || 8149 mode->vsync_start > vtotal_max || 8150 mode->vsync_end > vtotal_max || 8151 mode->vtotal > vtotal_max) 8152 return MODE_V_ILLEGAL; 8153 8154 if (DISPLAY_VER(dev_priv) >= 5) { 8155 if (mode->hdisplay < 64 || 8156 mode->htotal - mode->hdisplay < 32) 8157 return MODE_H_ILLEGAL; 8158 8159 if (mode->vtotal - mode->vdisplay < 5) 8160 return MODE_V_ILLEGAL; 8161 } else { 8162 if (mode->htotal - mode->hdisplay < 32) 8163 return MODE_H_ILLEGAL; 8164 8165 if (mode->vtotal - mode->vdisplay < 3) 8166 return MODE_V_ILLEGAL; 8167 } 8168 8169 /* 8170 * Cantiga+ cannot handle modes with a hsync front porch of 0. 8171 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. 8172 */ 8173 if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) && 8174 mode->hsync_start == mode->hdisplay) 8175 return MODE_H_ILLEGAL; 8176 8177 return MODE_OK; 8178 } 8179 8180 enum drm_mode_status 8181 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 8182 const struct drm_display_mode *mode, 8183 bool bigjoiner) 8184 { 8185 int plane_width_max, plane_height_max; 8186 8187 /* 8188 * intel_mode_valid() should be 8189 * sufficient on older platforms. 8190 */ 8191 if (DISPLAY_VER(dev_priv) < 9) 8192 return MODE_OK; 8193 8194 /* 8195 * Most people will probably want a fullscreen 8196 * plane so let's not advertize modes that are 8197 * too big for that. 8198 */ 8199 if (DISPLAY_VER(dev_priv) >= 11) { 8200 plane_width_max = 5120 << bigjoiner; 8201 plane_height_max = 4320; 8202 } else { 8203 plane_width_max = 5120; 8204 plane_height_max = 4096; 8205 } 8206 8207 if (mode->hdisplay > plane_width_max) 8208 return MODE_H_ILLEGAL; 8209 8210 if (mode->vdisplay > plane_height_max) 8211 return MODE_V_ILLEGAL; 8212 8213 return MODE_OK; 8214 } 8215 8216 static const struct drm_mode_config_funcs intel_mode_funcs = { 8217 .fb_create = intel_user_framebuffer_create, 8218 .get_format_info = intel_fb_get_format_info, 8219 .output_poll_changed = intel_fbdev_output_poll_changed, 8220 .mode_valid = intel_mode_valid, 8221 .atomic_check = intel_atomic_check, 8222 .atomic_commit = intel_atomic_commit, 8223 .atomic_state_alloc = intel_atomic_state_alloc, 8224 .atomic_state_clear = intel_atomic_state_clear, 8225 .atomic_state_free = intel_atomic_state_free, 8226 }; 8227 8228 static const struct intel_display_funcs skl_display_funcs = { 8229 .get_pipe_config = hsw_get_pipe_config, 8230 .crtc_enable = hsw_crtc_enable, 8231 .crtc_disable = hsw_crtc_disable, 8232 .commit_modeset_enables = skl_commit_modeset_enables, 8233 .get_initial_plane_config = skl_get_initial_plane_config, 8234 }; 8235 8236 static const struct intel_display_funcs ddi_display_funcs = { 8237 .get_pipe_config = hsw_get_pipe_config, 8238 .crtc_enable = hsw_crtc_enable, 8239 .crtc_disable = hsw_crtc_disable, 8240 .commit_modeset_enables = intel_commit_modeset_enables, 8241 .get_initial_plane_config = i9xx_get_initial_plane_config, 8242 }; 8243 8244 static const struct intel_display_funcs pch_split_display_funcs = { 8245 .get_pipe_config = ilk_get_pipe_config, 8246 .crtc_enable = ilk_crtc_enable, 8247 .crtc_disable = ilk_crtc_disable, 8248 .commit_modeset_enables = intel_commit_modeset_enables, 8249 .get_initial_plane_config = i9xx_get_initial_plane_config, 8250 }; 8251 8252 static const struct intel_display_funcs vlv_display_funcs = { 8253 .get_pipe_config = i9xx_get_pipe_config, 8254 .crtc_enable = valleyview_crtc_enable, 8255 .crtc_disable = i9xx_crtc_disable, 8256 .commit_modeset_enables = intel_commit_modeset_enables, 8257 .get_initial_plane_config = i9xx_get_initial_plane_config, 8258 }; 8259 8260 static const struct intel_display_funcs i9xx_display_funcs = { 8261 .get_pipe_config = i9xx_get_pipe_config, 8262 .crtc_enable = i9xx_crtc_enable, 8263 .crtc_disable = i9xx_crtc_disable, 8264 .commit_modeset_enables = intel_commit_modeset_enables, 8265 .get_initial_plane_config = i9xx_get_initial_plane_config, 8266 }; 8267 8268 /** 8269 * intel_init_display_hooks - initialize the display modesetting hooks 8270 * @dev_priv: device private 8271 */ 8272 void intel_init_display_hooks(struct drm_i915_private *dev_priv) 8273 { 8274 if (!HAS_DISPLAY(dev_priv)) 8275 return; 8276 8277 intel_color_init_hooks(dev_priv); 8278 intel_init_cdclk_hooks(dev_priv); 8279 intel_audio_hooks_init(dev_priv); 8280 8281 intel_dpll_init_clock_hook(dev_priv); 8282 8283 if (DISPLAY_VER(dev_priv) >= 9) { 8284 dev_priv->display.funcs.display = &skl_display_funcs; 8285 } else if (HAS_DDI(dev_priv)) { 8286 dev_priv->display.funcs.display = &ddi_display_funcs; 8287 } else if (HAS_PCH_SPLIT(dev_priv)) { 8288 dev_priv->display.funcs.display = &pch_split_display_funcs; 8289 } else if (IS_CHERRYVIEW(dev_priv) || 8290 IS_VALLEYVIEW(dev_priv)) { 8291 dev_priv->display.funcs.display = &vlv_display_funcs; 8292 } else { 8293 dev_priv->display.funcs.display = &i9xx_display_funcs; 8294 } 8295 8296 intel_fdi_init_hook(dev_priv); 8297 } 8298 8299 void intel_modeset_init_hw(struct drm_i915_private *i915) 8300 { 8301 struct intel_cdclk_state *cdclk_state; 8302 8303 if (!HAS_DISPLAY(i915)) 8304 return; 8305 8306 cdclk_state = to_intel_cdclk_state(i915->display.cdclk.obj.state); 8307 8308 intel_update_cdclk(i915); 8309 intel_cdclk_dump_config(i915, &i915->display.cdclk.hw, "Current CDCLK"); 8310 cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw; 8311 } 8312 8313 static int intel_initial_commit(struct drm_device *dev) 8314 { 8315 struct drm_atomic_state *state = NULL; 8316 struct drm_modeset_acquire_ctx ctx; 8317 struct intel_crtc *crtc; 8318 int ret = 0; 8319 8320 state = drm_atomic_state_alloc(dev); 8321 if (!state) 8322 return -ENOMEM; 8323 8324 drm_modeset_acquire_init(&ctx, 0); 8325 8326 retry: 8327 state->acquire_ctx = &ctx; 8328 8329 for_each_intel_crtc(dev, crtc) { 8330 struct intel_crtc_state *crtc_state = 8331 intel_atomic_get_crtc_state(state, crtc); 8332 8333 if (IS_ERR(crtc_state)) { 8334 ret = PTR_ERR(crtc_state); 8335 goto out; 8336 } 8337 8338 if (crtc_state->hw.active) { 8339 struct intel_encoder *encoder; 8340 8341 /* 8342 * We've not yet detected sink capabilities 8343 * (audio,infoframes,etc.) and thus we don't want to 8344 * force a full state recomputation yet. We want that to 8345 * happen only for the first real commit from userspace. 8346 * So preserve the inherited flag for the time being. 8347 */ 8348 crtc_state->inherited = true; 8349 8350 ret = drm_atomic_add_affected_planes(state, &crtc->base); 8351 if (ret) 8352 goto out; 8353 8354 /* 8355 * FIXME hack to force a LUT update to avoid the 8356 * plane update forcing the pipe gamma on without 8357 * having a proper LUT loaded. Remove once we 8358 * have readout for pipe gamma enable. 8359 */ 8360 crtc_state->uapi.color_mgmt_changed = true; 8361 8362 for_each_intel_encoder_mask(dev, encoder, 8363 crtc_state->uapi.encoder_mask) { 8364 if (encoder->initial_fastset_check && 8365 !encoder->initial_fastset_check(encoder, crtc_state)) { 8366 ret = drm_atomic_add_affected_connectors(state, 8367 &crtc->base); 8368 if (ret) 8369 goto out; 8370 } 8371 } 8372 } 8373 } 8374 8375 ret = drm_atomic_commit(state); 8376 8377 out: 8378 if (ret == -EDEADLK) { 8379 drm_atomic_state_clear(state); 8380 drm_modeset_backoff(&ctx); 8381 goto retry; 8382 } 8383 8384 drm_atomic_state_put(state); 8385 8386 drm_modeset_drop_locks(&ctx); 8387 drm_modeset_acquire_fini(&ctx); 8388 8389 return ret; 8390 } 8391 8392 static const struct drm_mode_config_helper_funcs intel_mode_config_funcs = { 8393 .atomic_commit_setup = drm_dp_mst_atomic_setup_commit, 8394 }; 8395 8396 static void intel_mode_config_init(struct drm_i915_private *i915) 8397 { 8398 struct drm_mode_config *mode_config = &i915->drm.mode_config; 8399 8400 drm_mode_config_init(&i915->drm); 8401 INIT_LIST_HEAD(&i915->display.global.obj_list); 8402 8403 mode_config->min_width = 0; 8404 mode_config->min_height = 0; 8405 8406 mode_config->preferred_depth = 24; 8407 mode_config->prefer_shadow = 1; 8408 8409 mode_config->funcs = &intel_mode_funcs; 8410 mode_config->helper_private = &intel_mode_config_funcs; 8411 8412 mode_config->async_page_flip = HAS_ASYNC_FLIPS(i915); 8413 8414 /* 8415 * Maximum framebuffer dimensions, chosen to match 8416 * the maximum render engine surface size on gen4+. 8417 */ 8418 if (DISPLAY_VER(i915) >= 7) { 8419 mode_config->max_width = 16384; 8420 mode_config->max_height = 16384; 8421 } else if (DISPLAY_VER(i915) >= 4) { 8422 mode_config->max_width = 8192; 8423 mode_config->max_height = 8192; 8424 } else if (DISPLAY_VER(i915) == 3) { 8425 mode_config->max_width = 4096; 8426 mode_config->max_height = 4096; 8427 } else { 8428 mode_config->max_width = 2048; 8429 mode_config->max_height = 2048; 8430 } 8431 8432 if (IS_I845G(i915) || IS_I865G(i915)) { 8433 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512; 8434 mode_config->cursor_height = 1023; 8435 } else if (IS_I830(i915) || IS_I85X(i915) || 8436 IS_I915G(i915) || IS_I915GM(i915)) { 8437 mode_config->cursor_width = 64; 8438 mode_config->cursor_height = 64; 8439 } else { 8440 mode_config->cursor_width = 256; 8441 mode_config->cursor_height = 256; 8442 } 8443 } 8444 8445 static void intel_mode_config_cleanup(struct drm_i915_private *i915) 8446 { 8447 intel_atomic_global_obj_cleanup(i915); 8448 drm_mode_config_cleanup(&i915->drm); 8449 } 8450 8451 /* part #1: call before irq install */ 8452 int intel_modeset_init_noirq(struct drm_i915_private *i915) 8453 { 8454 int ret; 8455 8456 if (i915_inject_probe_failure(i915)) 8457 return -ENODEV; 8458 8459 if (HAS_DISPLAY(i915)) { 8460 ret = drm_vblank_init(&i915->drm, 8461 INTEL_NUM_PIPES(i915)); 8462 if (ret) 8463 return ret; 8464 } 8465 8466 intel_bios_init(i915); 8467 8468 ret = intel_vga_register(i915); 8469 if (ret) 8470 goto cleanup_bios; 8471 8472 /* FIXME: completely on the wrong abstraction layer */ 8473 ret = intel_power_domains_init(i915); 8474 if (ret < 0) 8475 goto cleanup_vga; 8476 8477 intel_power_domains_init_hw(i915, false); 8478 8479 if (!HAS_DISPLAY(i915)) 8480 return 0; 8481 8482 intel_dmc_init(i915); 8483 8484 i915->display.wq.modeset = alloc_ordered_workqueue("i915_modeset", 0); 8485 i915->display.wq.flip = alloc_workqueue("i915_flip", WQ_HIGHPRI | 8486 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE); 8487 8488 intel_mode_config_init(i915); 8489 8490 ret = intel_cdclk_init(i915); 8491 if (ret) 8492 goto cleanup_vga_client_pw_domain_dmc; 8493 8494 ret = intel_color_init(i915); 8495 if (ret) 8496 goto cleanup_vga_client_pw_domain_dmc; 8497 8498 ret = intel_dbuf_init(i915); 8499 if (ret) 8500 goto cleanup_vga_client_pw_domain_dmc; 8501 8502 ret = intel_bw_init(i915); 8503 if (ret) 8504 goto cleanup_vga_client_pw_domain_dmc; 8505 8506 init_llist_head(&i915->display.atomic_helper.free_list); 8507 INIT_WORK(&i915->display.atomic_helper.free_work, 8508 intel_atomic_helper_free_state_worker); 8509 8510 intel_init_quirks(i915); 8511 8512 intel_fbc_init(i915); 8513 8514 return 0; 8515 8516 cleanup_vga_client_pw_domain_dmc: 8517 intel_dmc_fini(i915); 8518 intel_power_domains_driver_remove(i915); 8519 cleanup_vga: 8520 intel_vga_unregister(i915); 8521 cleanup_bios: 8522 intel_bios_driver_remove(i915); 8523 8524 return ret; 8525 } 8526 8527 /* part #2: call after irq install, but before gem init */ 8528 int intel_modeset_init_nogem(struct drm_i915_private *i915) 8529 { 8530 struct drm_device *dev = &i915->drm; 8531 enum pipe pipe; 8532 struct intel_crtc *crtc; 8533 int ret; 8534 8535 if (!HAS_DISPLAY(i915)) 8536 return 0; 8537 8538 intel_wm_init(i915); 8539 8540 intel_panel_sanitize_ssc(i915); 8541 8542 intel_pps_setup(i915); 8543 8544 intel_gmbus_setup(i915); 8545 8546 drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n", 8547 INTEL_NUM_PIPES(i915), 8548 INTEL_NUM_PIPES(i915) > 1 ? "s" : ""); 8549 8550 for_each_pipe(i915, pipe) { 8551 ret = intel_crtc_init(i915, pipe); 8552 if (ret) { 8553 intel_mode_config_cleanup(i915); 8554 return ret; 8555 } 8556 } 8557 8558 intel_plane_possible_crtcs_init(i915); 8559 intel_shared_dpll_init(i915); 8560 intel_fdi_pll_freq_update(i915); 8561 8562 intel_update_czclk(i915); 8563 intel_modeset_init_hw(i915); 8564 intel_dpll_update_ref_clks(i915); 8565 8566 intel_hdcp_component_init(i915); 8567 8568 if (i915->display.cdclk.max_cdclk_freq == 0) 8569 intel_update_max_cdclk(i915); 8570 8571 intel_hti_init(i915); 8572 8573 /* Just disable it once at startup */ 8574 intel_vga_disable(i915); 8575 intel_setup_outputs(i915); 8576 8577 drm_modeset_lock_all(dev); 8578 intel_modeset_setup_hw_state(i915, dev->mode_config.acquire_ctx); 8579 intel_acpi_assign_connector_fwnodes(i915); 8580 drm_modeset_unlock_all(dev); 8581 8582 for_each_intel_crtc(dev, crtc) { 8583 if (!to_intel_crtc_state(crtc->base.state)->uapi.active) 8584 continue; 8585 intel_crtc_initial_plane_config(crtc); 8586 } 8587 8588 /* 8589 * Make sure hardware watermarks really match the state we read out. 8590 * Note that we need to do this after reconstructing the BIOS fb's 8591 * since the watermark calculation done here will use pstate->fb. 8592 */ 8593 if (!HAS_GMCH(i915)) 8594 ilk_wm_sanitize(i915); 8595 8596 return 0; 8597 } 8598 8599 /* part #3: call after gem init */ 8600 int intel_modeset_init(struct drm_i915_private *i915) 8601 { 8602 int ret; 8603 8604 if (!HAS_DISPLAY(i915)) 8605 return 0; 8606 8607 /* 8608 * Force all active planes to recompute their states. So that on 8609 * mode_setcrtc after probe, all the intel_plane_state variables 8610 * are already calculated and there is no assert_plane warnings 8611 * during bootup. 8612 */ 8613 ret = intel_initial_commit(&i915->drm); 8614 if (ret) 8615 drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret); 8616 8617 intel_overlay_setup(i915); 8618 8619 ret = intel_fbdev_init(&i915->drm); 8620 if (ret) 8621 return ret; 8622 8623 /* Only enable hotplug handling once the fbdev is fully set up. */ 8624 intel_hpd_init(i915); 8625 intel_hpd_poll_disable(i915); 8626 8627 skl_watermark_ipc_init(i915); 8628 8629 return 0; 8630 } 8631 8632 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 8633 { 8634 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 8635 enum transcoder cpu_transcoder = (enum transcoder)pipe; 8636 /* 640x480@60Hz, ~25175 kHz */ 8637 struct dpll clock = { 8638 .m1 = 18, 8639 .m2 = 7, 8640 .p1 = 13, 8641 .p2 = 4, 8642 .n = 2, 8643 }; 8644 u32 dpll, fp; 8645 int i; 8646 8647 drm_WARN_ON(&dev_priv->drm, 8648 i9xx_calc_dpll_params(48000, &clock) != 25154); 8649 8650 drm_dbg_kms(&dev_priv->drm, 8651 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n", 8652 pipe_name(pipe), clock.vco, clock.dot); 8653 8654 fp = i9xx_dpll_compute_fp(&clock); 8655 dpll = DPLL_DVO_2X_MODE | 8656 DPLL_VGA_MODE_DIS | 8657 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | 8658 PLL_P2_DIVIDE_BY_4 | 8659 PLL_REF_INPUT_DREFCLK | 8660 DPLL_VCO_ENABLE; 8661 8662 intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder), 8663 HACTIVE(640 - 1) | HTOTAL(800 - 1)); 8664 intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder), 8665 HBLANK_START(640 - 1) | HBLANK_END(800 - 1)); 8666 intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder), 8667 HSYNC_START(656 - 1) | HSYNC_END(752 - 1)); 8668 intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder), 8669 VACTIVE(480 - 1) | VTOTAL(525 - 1)); 8670 intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), 8671 VBLANK_START(480 - 1) | VBLANK_END(525 - 1)); 8672 intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder), 8673 VSYNC_START(490 - 1) | VSYNC_END(492 - 1)); 8674 intel_de_write(dev_priv, PIPESRC(pipe), 8675 PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1)); 8676 8677 intel_de_write(dev_priv, FP0(pipe), fp); 8678 intel_de_write(dev_priv, FP1(pipe), fp); 8679 8680 /* 8681 * Apparently we need to have VGA mode enabled prior to changing 8682 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 8683 * dividers, even though the register value does change. 8684 */ 8685 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); 8686 intel_de_write(dev_priv, DPLL(pipe), dpll); 8687 8688 /* Wait for the clocks to stabilize. */ 8689 intel_de_posting_read(dev_priv, DPLL(pipe)); 8690 udelay(150); 8691 8692 /* The pixel multiplier can only be updated once the 8693 * DPLL is enabled and the clocks are stable. 8694 * 8695 * So write it again. 8696 */ 8697 intel_de_write(dev_priv, DPLL(pipe), dpll); 8698 8699 /* We do this three times for luck */ 8700 for (i = 0; i < 3 ; i++) { 8701 intel_de_write(dev_priv, DPLL(pipe), dpll); 8702 intel_de_posting_read(dev_priv, DPLL(pipe)); 8703 udelay(150); /* wait for warmup */ 8704 } 8705 8706 intel_de_write(dev_priv, TRANSCONF(pipe), TRANSCONF_ENABLE); 8707 intel_de_posting_read(dev_priv, TRANSCONF(pipe)); 8708 8709 intel_wait_for_pipe_scanline_moving(crtc); 8710 } 8711 8712 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 8713 { 8714 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 8715 8716 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n", 8717 pipe_name(pipe)); 8718 8719 drm_WARN_ON(&dev_priv->drm, 8720 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE); 8721 drm_WARN_ON(&dev_priv->drm, 8722 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE); 8723 drm_WARN_ON(&dev_priv->drm, 8724 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE); 8725 drm_WARN_ON(&dev_priv->drm, 8726 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK); 8727 drm_WARN_ON(&dev_priv->drm, 8728 intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK); 8729 8730 intel_de_write(dev_priv, TRANSCONF(pipe), 0); 8731 intel_de_posting_read(dev_priv, TRANSCONF(pipe)); 8732 8733 intel_wait_for_pipe_scanline_stopped(crtc); 8734 8735 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); 8736 intel_de_posting_read(dev_priv, DPLL(pipe)); 8737 } 8738 8739 void intel_display_resume(struct drm_device *dev) 8740 { 8741 struct drm_i915_private *i915 = to_i915(dev); 8742 struct drm_atomic_state *state = i915->display.restore.modeset_state; 8743 struct drm_modeset_acquire_ctx ctx; 8744 int ret; 8745 8746 if (!HAS_DISPLAY(i915)) 8747 return; 8748 8749 i915->display.restore.modeset_state = NULL; 8750 if (state) 8751 state->acquire_ctx = &ctx; 8752 8753 drm_modeset_acquire_init(&ctx, 0); 8754 8755 while (1) { 8756 ret = drm_modeset_lock_all_ctx(dev, &ctx); 8757 if (ret != -EDEADLK) 8758 break; 8759 8760 drm_modeset_backoff(&ctx); 8761 } 8762 8763 if (!ret) 8764 ret = __intel_display_resume(i915, state, &ctx); 8765 8766 skl_watermark_ipc_update(i915); 8767 drm_modeset_drop_locks(&ctx); 8768 drm_modeset_acquire_fini(&ctx); 8769 8770 if (ret) 8771 drm_err(&i915->drm, 8772 "Restoring old state failed with %i\n", ret); 8773 if (state) 8774 drm_atomic_state_put(state); 8775 } 8776 8777 static void intel_hpd_poll_fini(struct drm_i915_private *i915) 8778 { 8779 struct intel_connector *connector; 8780 struct drm_connector_list_iter conn_iter; 8781 8782 /* Kill all the work that may have been queued by hpd. */ 8783 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 8784 for_each_intel_connector_iter(connector, &conn_iter) { 8785 if (connector->modeset_retry_work.func) 8786 cancel_work_sync(&connector->modeset_retry_work); 8787 if (connector->hdcp.shim) { 8788 cancel_delayed_work_sync(&connector->hdcp.check_work); 8789 cancel_work_sync(&connector->hdcp.prop_work); 8790 } 8791 } 8792 drm_connector_list_iter_end(&conn_iter); 8793 } 8794 8795 /* part #1: call before irq uninstall */ 8796 void intel_modeset_driver_remove(struct drm_i915_private *i915) 8797 { 8798 if (!HAS_DISPLAY(i915)) 8799 return; 8800 8801 flush_workqueue(i915->display.wq.flip); 8802 flush_workqueue(i915->display.wq.modeset); 8803 8804 flush_work(&i915->display.atomic_helper.free_work); 8805 drm_WARN_ON(&i915->drm, !llist_empty(&i915->display.atomic_helper.free_list)); 8806 8807 /* 8808 * MST topology needs to be suspended so we don't have any calls to 8809 * fbdev after it's finalized. MST will be destroyed later as part of 8810 * drm_mode_config_cleanup() 8811 */ 8812 intel_dp_mst_suspend(i915); 8813 } 8814 8815 /* part #2: call after irq uninstall */ 8816 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915) 8817 { 8818 if (!HAS_DISPLAY(i915)) 8819 return; 8820 8821 /* 8822 * Due to the hpd irq storm handling the hotplug work can re-arm the 8823 * poll handlers. Hence disable polling after hpd handling is shut down. 8824 */ 8825 intel_hpd_poll_fini(i915); 8826 8827 /* poll work can call into fbdev, hence clean that up afterwards */ 8828 intel_fbdev_fini(i915); 8829 8830 intel_unregister_dsm_handler(); 8831 8832 /* flush any delayed tasks or pending work */ 8833 flush_scheduled_work(); 8834 8835 intel_hdcp_component_fini(i915); 8836 8837 intel_mode_config_cleanup(i915); 8838 8839 intel_overlay_cleanup(i915); 8840 8841 intel_gmbus_teardown(i915); 8842 8843 destroy_workqueue(i915->display.wq.flip); 8844 destroy_workqueue(i915->display.wq.modeset); 8845 8846 intel_fbc_cleanup(i915); 8847 } 8848 8849 /* part #3: call after gem init */ 8850 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915) 8851 { 8852 intel_dmc_fini(i915); 8853 8854 intel_power_domains_driver_remove(i915); 8855 8856 intel_vga_unregister(i915); 8857 8858 intel_bios_driver_remove(i915); 8859 } 8860 8861 bool intel_modeset_probe_defer(struct pci_dev *pdev) 8862 { 8863 struct drm_privacy_screen *privacy_screen; 8864 8865 /* 8866 * apple-gmux is needed on dual GPU MacBook Pro 8867 * to probe the panel if we're the inactive GPU. 8868 */ 8869 if (vga_switcheroo_client_probe_defer(pdev)) 8870 return true; 8871 8872 /* If the LCD panel has a privacy-screen, wait for it */ 8873 privacy_screen = drm_privacy_screen_get(&pdev->dev, NULL); 8874 if (IS_ERR(privacy_screen) && PTR_ERR(privacy_screen) == -EPROBE_DEFER) 8875 return true; 8876 8877 drm_privacy_screen_put(privacy_screen); 8878 8879 return false; 8880 } 8881 8882 void intel_display_driver_register(struct drm_i915_private *i915) 8883 { 8884 if (!HAS_DISPLAY(i915)) 8885 return; 8886 8887 /* Must be done after probing outputs */ 8888 intel_opregion_register(i915); 8889 intel_acpi_video_register(i915); 8890 8891 intel_audio_init(i915); 8892 8893 intel_display_debugfs_register(i915); 8894 8895 /* 8896 * Some ports require correctly set-up hpd registers for 8897 * detection to work properly (leading to ghost connected 8898 * connector status), e.g. VGA on gm45. Hence we can only set 8899 * up the initial fbdev config after hpd irqs are fully 8900 * enabled. We do it last so that the async config cannot run 8901 * before the connectors are registered. 8902 */ 8903 intel_fbdev_initial_config_async(i915); 8904 8905 /* 8906 * We need to coordinate the hotplugs with the asynchronous 8907 * fbdev configuration, for which we use the 8908 * fbdev->async_cookie. 8909 */ 8910 drm_kms_helper_poll_init(&i915->drm); 8911 } 8912 8913 void intel_display_driver_unregister(struct drm_i915_private *i915) 8914 { 8915 if (!HAS_DISPLAY(i915)) 8916 return; 8917 8918 intel_fbdev_unregister(i915); 8919 intel_audio_deinit(i915); 8920 8921 /* 8922 * After flushing the fbdev (incl. a late async config which 8923 * will have delayed queuing of a hotplug event), then flush 8924 * the hotplug events. 8925 */ 8926 drm_kms_helper_poll_fini(&i915->drm); 8927 drm_atomic_helper_shutdown(&i915->drm); 8928 8929 acpi_video_unregister(); 8930 intel_opregion_unregister(i915); 8931 } 8932 8933 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915) 8934 { 8935 return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915); 8936 } 8937