1 /*
2  * Copyright © 2006-2007 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *	Eric Anholt <eric@anholt.net>
25  */
26 
27 #include <linux/dma-resv.h>
28 #include <linux/i2c.h>
29 #include <linux/input.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/slab.h>
33 #include <linux/string_helpers.h>
34 #include <linux/vga_switcheroo.h>
35 #include <acpi/video.h>
36 
37 #include <drm/display/drm_dp_helper.h>
38 #include <drm/drm_atomic.h>
39 #include <drm/drm_atomic_helper.h>
40 #include <drm/drm_atomic_uapi.h>
41 #include <drm/drm_damage_helper.h>
42 #include <drm/drm_edid.h>
43 #include <drm/drm_fourcc.h>
44 #include <drm/drm_privacy_screen_consumer.h>
45 #include <drm/drm_probe_helper.h>
46 #include <drm/drm_rect.h>
47 
48 #include "gem/i915_gem_lmem.h"
49 #include "gem/i915_gem_object.h"
50 
51 #include "g4x_dp.h"
52 #include "g4x_hdmi.h"
53 #include "hsw_ips.h"
54 #include "i915_drv.h"
55 #include "i915_reg.h"
56 #include "i915_utils.h"
57 #include "i9xx_plane.h"
58 #include "i9xx_wm.h"
59 #include "icl_dsi.h"
60 #include "intel_acpi.h"
61 #include "intel_atomic.h"
62 #include "intel_atomic_plane.h"
63 #include "intel_audio.h"
64 #include "intel_bw.h"
65 #include "intel_cdclk.h"
66 #include "intel_clock_gating.h"
67 #include "intel_color.h"
68 #include "intel_crt.h"
69 #include "intel_crtc.h"
70 #include "intel_crtc_state_dump.h"
71 #include "intel_ddi.h"
72 #include "intel_de.h"
73 #include "intel_display_debugfs.h"
74 #include "intel_display_power.h"
75 #include "intel_display_types.h"
76 #include "intel_dmc.h"
77 #include "intel_dp.h"
78 #include "intel_dp_link_training.h"
79 #include "intel_dp_mst.h"
80 #include "intel_dpio_phy.h"
81 #include "intel_dpll.h"
82 #include "intel_dpll_mgr.h"
83 #include "intel_dpt.h"
84 #include "intel_drrs.h"
85 #include "intel_dsi.h"
86 #include "intel_dvo.h"
87 #include "intel_fb.h"
88 #include "intel_fbc.h"
89 #include "intel_fbdev.h"
90 #include "intel_fdi.h"
91 #include "intel_fifo_underrun.h"
92 #include "intel_frontbuffer.h"
93 #include "intel_gmbus.h"
94 #include "intel_hdcp.h"
95 #include "intel_hdmi.h"
96 #include "intel_hotplug.h"
97 #include "intel_hti.h"
98 #include "intel_lvds.h"
99 #include "intel_lvds_regs.h"
100 #include "intel_modeset_setup.h"
101 #include "intel_modeset_verify.h"
102 #include "intel_overlay.h"
103 #include "intel_panel.h"
104 #include "intel_pch_display.h"
105 #include "intel_pch_refclk.h"
106 #include "intel_pcode.h"
107 #include "intel_pipe_crc.h"
108 #include "intel_plane_initial.h"
109 #include "intel_pps.h"
110 #include "intel_psr.h"
111 #include "intel_quirks.h"
112 #include "intel_sdvo.h"
113 #include "intel_snps_phy.h"
114 #include "intel_tc.h"
115 #include "intel_tv.h"
116 #include "intel_vblank.h"
117 #include "intel_vdsc.h"
118 #include "intel_vdsc_regs.h"
119 #include "intel_vga.h"
120 #include "intel_vrr.h"
121 #include "intel_wm.h"
122 #include "skl_scaler.h"
123 #include "skl_universal_plane.h"
124 #include "skl_watermark.h"
125 #include "vlv_dsi.h"
126 #include "vlv_dsi_pll.h"
127 #include "vlv_dsi_regs.h"
128 #include "vlv_sideband.h"
129 
130 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
131 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
132 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
133 static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state);
134 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
135 
136 /* returns HPLL frequency in kHz */
137 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
138 {
139 	int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
140 
141 	/* Obtain SKU information */
142 	hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
143 		CCK_FUSE_HPLL_FREQ_MASK;
144 
145 	return vco_freq[hpll_freq] * 1000;
146 }
147 
148 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
149 		      const char *name, u32 reg, int ref_freq)
150 {
151 	u32 val;
152 	int divider;
153 
154 	val = vlv_cck_read(dev_priv, reg);
155 	divider = val & CCK_FREQUENCY_VALUES;
156 
157 	drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=
158 		 (divider << CCK_FREQUENCY_STATUS_SHIFT),
159 		 "%s change in progress\n", name);
160 
161 	return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
162 }
163 
164 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
165 			   const char *name, u32 reg)
166 {
167 	int hpll;
168 
169 	vlv_cck_get(dev_priv);
170 
171 	if (dev_priv->hpll_freq == 0)
172 		dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
173 
174 	hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
175 
176 	vlv_cck_put(dev_priv);
177 
178 	return hpll;
179 }
180 
181 static void intel_update_czclk(struct drm_i915_private *dev_priv)
182 {
183 	if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
184 		return;
185 
186 	dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
187 						      CCK_CZ_CLOCK_CONTROL);
188 
189 	drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",
190 		dev_priv->czclk_freq);
191 }
192 
193 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state)
194 {
195 	return (crtc_state->active_planes &
196 		~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0;
197 }
198 
199 /* WA Display #0827: Gen9:all */
200 static void
201 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
202 {
203 	if (enable)
204 		intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe),
205 			     0, DUPS1_GATING_DIS | DUPS2_GATING_DIS);
206 	else
207 		intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe),
208 			     DUPS1_GATING_DIS | DUPS2_GATING_DIS, 0);
209 }
210 
211 /* Wa_2006604312:icl,ehl */
212 static void
213 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
214 		       bool enable)
215 {
216 	if (enable)
217 		intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 0, DPFR_GATING_DIS);
218 	else
219 		intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), DPFR_GATING_DIS, 0);
220 }
221 
222 /* Wa_1604331009:icl,jsl,ehl */
223 static void
224 icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
225 		       bool enable)
226 {
227 	intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), CURSOR_GATING_DIS,
228 		     enable ? CURSOR_GATING_DIS : 0);
229 }
230 
231 static bool
232 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
233 {
234 	return crtc_state->master_transcoder != INVALID_TRANSCODER;
235 }
236 
237 static bool
238 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
239 {
240 	return crtc_state->sync_mode_slaves_mask != 0;
241 }
242 
243 bool
244 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
245 {
246 	return is_trans_port_sync_master(crtc_state) ||
247 		is_trans_port_sync_slave(crtc_state);
248 }
249 
250 static enum pipe bigjoiner_master_pipe(const struct intel_crtc_state *crtc_state)
251 {
252 	return ffs(crtc_state->bigjoiner_pipes) - 1;
253 }
254 
255 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state)
256 {
257 	if (crtc_state->bigjoiner_pipes)
258 		return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state));
259 	else
260 		return 0;
261 }
262 
263 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state)
264 {
265 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
266 
267 	return crtc_state->bigjoiner_pipes &&
268 		crtc->pipe != bigjoiner_master_pipe(crtc_state);
269 }
270 
271 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state)
272 {
273 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
274 
275 	return crtc_state->bigjoiner_pipes &&
276 		crtc->pipe == bigjoiner_master_pipe(crtc_state);
277 }
278 
279 static int intel_bigjoiner_num_pipes(const struct intel_crtc_state *crtc_state)
280 {
281 	return hweight8(crtc_state->bigjoiner_pipes);
282 }
283 
284 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state)
285 {
286 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
287 
288 	if (intel_crtc_is_bigjoiner_slave(crtc_state))
289 		return intel_crtc_for_pipe(i915, bigjoiner_master_pipe(crtc_state));
290 	else
291 		return to_intel_crtc(crtc_state->uapi.crtc);
292 }
293 
294 static void
295 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
296 {
297 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
298 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
299 
300 	if (DISPLAY_VER(dev_priv) >= 4) {
301 		enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
302 
303 		/* Wait for the Pipe State to go off */
304 		if (intel_de_wait_for_clear(dev_priv, TRANSCONF(cpu_transcoder),
305 					    TRANSCONF_STATE_ENABLE, 100))
306 			drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n");
307 	} else {
308 		intel_wait_for_pipe_scanline_stopped(crtc);
309 	}
310 }
311 
312 void assert_transcoder(struct drm_i915_private *dev_priv,
313 		       enum transcoder cpu_transcoder, bool state)
314 {
315 	bool cur_state;
316 	enum intel_display_power_domain power_domain;
317 	intel_wakeref_t wakeref;
318 
319 	/* we keep both pipes enabled on 830 */
320 	if (IS_I830(dev_priv))
321 		state = true;
322 
323 	power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
324 	wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
325 	if (wakeref) {
326 		u32 val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
327 		cur_state = !!(val & TRANSCONF_ENABLE);
328 
329 		intel_display_power_put(dev_priv, power_domain, wakeref);
330 	} else {
331 		cur_state = false;
332 	}
333 
334 	I915_STATE_WARN(cur_state != state,
335 			"transcoder %s assertion failure (expected %s, current %s)\n",
336 			transcoder_name(cpu_transcoder),
337 			str_on_off(state), str_on_off(cur_state));
338 }
339 
340 static void assert_plane(struct intel_plane *plane, bool state)
341 {
342 	enum pipe pipe;
343 	bool cur_state;
344 
345 	cur_state = plane->get_hw_state(plane, &pipe);
346 
347 	I915_STATE_WARN(cur_state != state,
348 			"%s assertion failure (expected %s, current %s)\n",
349 			plane->base.name, str_on_off(state),
350 			str_on_off(cur_state));
351 }
352 
353 #define assert_plane_enabled(p) assert_plane(p, true)
354 #define assert_plane_disabled(p) assert_plane(p, false)
355 
356 static void assert_planes_disabled(struct intel_crtc *crtc)
357 {
358 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
359 	struct intel_plane *plane;
360 
361 	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
362 		assert_plane_disabled(plane);
363 }
364 
365 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
366 			 struct intel_digital_port *dig_port,
367 			 unsigned int expected_mask)
368 {
369 	u32 port_mask;
370 	i915_reg_t dpll_reg;
371 
372 	switch (dig_port->base.port) {
373 	default:
374 		MISSING_CASE(dig_port->base.port);
375 		fallthrough;
376 	case PORT_B:
377 		port_mask = DPLL_PORTB_READY_MASK;
378 		dpll_reg = DPLL(0);
379 		break;
380 	case PORT_C:
381 		port_mask = DPLL_PORTC_READY_MASK;
382 		dpll_reg = DPLL(0);
383 		expected_mask <<= 4;
384 		break;
385 	case PORT_D:
386 		port_mask = DPLL_PORTD_READY_MASK;
387 		dpll_reg = DPIO_PHY_STATUS;
388 		break;
389 	}
390 
391 	if (intel_de_wait_for_register(dev_priv, dpll_reg,
392 				       port_mask, expected_mask, 1000))
393 		drm_WARN(&dev_priv->drm, 1,
394 			 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
395 			 dig_port->base.base.base.id, dig_port->base.base.name,
396 			 intel_de_read(dev_priv, dpll_reg) & port_mask,
397 			 expected_mask);
398 }
399 
400 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
401 {
402 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
403 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
404 	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
405 	enum pipe pipe = crtc->pipe;
406 	i915_reg_t reg;
407 	u32 val;
408 
409 	drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));
410 
411 	assert_planes_disabled(crtc);
412 
413 	/*
414 	 * A pipe without a PLL won't actually be able to drive bits from
415 	 * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
416 	 * need the check.
417 	 */
418 	if (HAS_GMCH(dev_priv)) {
419 		if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
420 			assert_dsi_pll_enabled(dev_priv);
421 		else
422 			assert_pll_enabled(dev_priv, pipe);
423 	} else {
424 		if (new_crtc_state->has_pch_encoder) {
425 			/* if driving the PCH, we need FDI enabled */
426 			assert_fdi_rx_pll_enabled(dev_priv,
427 						  intel_crtc_pch_transcoder(crtc));
428 			assert_fdi_tx_pll_enabled(dev_priv,
429 						  (enum pipe) cpu_transcoder);
430 		}
431 		/* FIXME: assert CPU port conditions for SNB+ */
432 	}
433 
434 	/* Wa_22012358565:adl-p */
435 	if (DISPLAY_VER(dev_priv) == 13)
436 		intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe),
437 			     0, PIPE_ARB_USE_PROG_SLOTS);
438 
439 	reg = TRANSCONF(cpu_transcoder);
440 	val = intel_de_read(dev_priv, reg);
441 	if (val & TRANSCONF_ENABLE) {
442 		/* we keep both pipes enabled on 830 */
443 		drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
444 		return;
445 	}
446 
447 	intel_de_write(dev_priv, reg, val | TRANSCONF_ENABLE);
448 	intel_de_posting_read(dev_priv, reg);
449 
450 	/*
451 	 * Until the pipe starts PIPEDSL reads will return a stale value,
452 	 * which causes an apparent vblank timestamp jump when PIPEDSL
453 	 * resets to its proper value. That also messes up the frame count
454 	 * when it's derived from the timestamps. So let's wait for the
455 	 * pipe to start properly before we call drm_crtc_vblank_on()
456 	 */
457 	if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
458 		intel_wait_for_pipe_scanline_moving(crtc);
459 }
460 
461 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
462 {
463 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
464 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
465 	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
466 	enum pipe pipe = crtc->pipe;
467 	i915_reg_t reg;
468 	u32 val;
469 
470 	drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));
471 
472 	/*
473 	 * Make sure planes won't keep trying to pump pixels to us,
474 	 * or we might hang the display.
475 	 */
476 	assert_planes_disabled(crtc);
477 
478 	reg = TRANSCONF(cpu_transcoder);
479 	val = intel_de_read(dev_priv, reg);
480 	if ((val & TRANSCONF_ENABLE) == 0)
481 		return;
482 
483 	/*
484 	 * Double wide has implications for planes
485 	 * so best keep it disabled when not needed.
486 	 */
487 	if (old_crtc_state->double_wide)
488 		val &= ~TRANSCONF_DOUBLE_WIDE;
489 
490 	/* Don't disable pipe or pipe PLLs if needed */
491 	if (!IS_I830(dev_priv))
492 		val &= ~TRANSCONF_ENABLE;
493 
494 	if (DISPLAY_VER(dev_priv) >= 14)
495 		intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder),
496 			     FECSTALL_DIS_DPTSTREAM_DPTTG, 0);
497 	else if (DISPLAY_VER(dev_priv) >= 12)
498 		intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder),
499 			     FECSTALL_DIS_DPTSTREAM_DPTTG, 0);
500 
501 	intel_de_write(dev_priv, reg, val);
502 	if ((val & TRANSCONF_ENABLE) == 0)
503 		intel_wait_for_pipe_off(old_crtc_state);
504 }
505 
506 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
507 {
508 	unsigned int size = 0;
509 	int i;
510 
511 	for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
512 		size += rot_info->plane[i].dst_stride * rot_info->plane[i].width;
513 
514 	return size;
515 }
516 
517 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
518 {
519 	unsigned int size = 0;
520 	int i;
521 
522 	for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) {
523 		unsigned int plane_size;
524 
525 		if (rem_info->plane[i].linear)
526 			plane_size = rem_info->plane[i].size;
527 		else
528 			plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height;
529 
530 		if (plane_size == 0)
531 			continue;
532 
533 		if (rem_info->plane_alignment)
534 			size = ALIGN(size, rem_info->plane_alignment);
535 
536 		size += plane_size;
537 	}
538 
539 	return size;
540 }
541 
542 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
543 {
544 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
545 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
546 
547 	return DISPLAY_VER(dev_priv) < 4 ||
548 		(plane->fbc &&
549 		 plane_state->view.gtt.type == I915_GTT_VIEW_NORMAL);
550 }
551 
552 /*
553  * Convert the x/y offsets into a linear offset.
554  * Only valid with 0/180 degree rotation, which is fine since linear
555  * offset is only used with linear buffers on pre-hsw and tiled buffers
556  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
557  */
558 u32 intel_fb_xy_to_linear(int x, int y,
559 			  const struct intel_plane_state *state,
560 			  int color_plane)
561 {
562 	const struct drm_framebuffer *fb = state->hw.fb;
563 	unsigned int cpp = fb->format->cpp[color_plane];
564 	unsigned int pitch = state->view.color_plane[color_plane].mapping_stride;
565 
566 	return y * pitch + x * cpp;
567 }
568 
569 /*
570  * Add the x/y offsets derived from fb->offsets[] to the user
571  * specified plane src x/y offsets. The resulting x/y offsets
572  * specify the start of scanout from the beginning of the gtt mapping.
573  */
574 void intel_add_fb_offsets(int *x, int *y,
575 			  const struct intel_plane_state *state,
576 			  int color_plane)
577 
578 {
579 	*x += state->view.color_plane[color_plane].x;
580 	*y += state->view.color_plane[color_plane].y;
581 }
582 
583 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
584 			      u32 pixel_format, u64 modifier)
585 {
586 	struct intel_crtc *crtc;
587 	struct intel_plane *plane;
588 
589 	if (!HAS_DISPLAY(dev_priv))
590 		return 0;
591 
592 	/*
593 	 * We assume the primary plane for pipe A has
594 	 * the highest stride limits of them all,
595 	 * if in case pipe A is disabled, use the first pipe from pipe_mask.
596 	 */
597 	crtc = intel_first_crtc(dev_priv);
598 	if (!crtc)
599 		return 0;
600 
601 	plane = to_intel_plane(crtc->base.primary);
602 
603 	return plane->max_stride(plane, pixel_format, modifier,
604 				 DRM_MODE_ROTATE_0);
605 }
606 
607 void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
608 			     struct intel_plane_state *plane_state,
609 			     bool visible)
610 {
611 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
612 
613 	plane_state->uapi.visible = visible;
614 
615 	if (visible)
616 		crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
617 	else
618 		crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
619 }
620 
621 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state)
622 {
623 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
624 	struct drm_plane *plane;
625 
626 	/*
627 	 * Active_planes aliases if multiple "primary" or cursor planes
628 	 * have been used on the same (or wrong) pipe. plane_mask uses
629 	 * unique ids, hence we can use that to reconstruct active_planes.
630 	 */
631 	crtc_state->enabled_planes = 0;
632 	crtc_state->active_planes = 0;
633 
634 	drm_for_each_plane_mask(plane, &dev_priv->drm,
635 				crtc_state->uapi.plane_mask) {
636 		crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id);
637 		crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
638 	}
639 }
640 
641 void intel_plane_disable_noatomic(struct intel_crtc *crtc,
642 				  struct intel_plane *plane)
643 {
644 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
645 	struct intel_crtc_state *crtc_state =
646 		to_intel_crtc_state(crtc->base.state);
647 	struct intel_plane_state *plane_state =
648 		to_intel_plane_state(plane->base.state);
649 
650 	drm_dbg_kms(&dev_priv->drm,
651 		    "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
652 		    plane->base.base.id, plane->base.name,
653 		    crtc->base.base.id, crtc->base.name);
654 
655 	intel_set_plane_visible(crtc_state, plane_state, false);
656 	intel_plane_fixup_bitmasks(crtc_state);
657 	crtc_state->data_rate[plane->id] = 0;
658 	crtc_state->data_rate_y[plane->id] = 0;
659 	crtc_state->rel_data_rate[plane->id] = 0;
660 	crtc_state->rel_data_rate_y[plane->id] = 0;
661 	crtc_state->min_cdclk[plane->id] = 0;
662 
663 	if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 &&
664 	    hsw_ips_disable(crtc_state)) {
665 		crtc_state->ips_enabled = false;
666 		intel_crtc_wait_for_next_vblank(crtc);
667 	}
668 
669 	/*
670 	 * Vblank time updates from the shadow to live plane control register
671 	 * are blocked if the memory self-refresh mode is active at that
672 	 * moment. So to make sure the plane gets truly disabled, disable
673 	 * first the self-refresh mode. The self-refresh enable bit in turn
674 	 * will be checked/applied by the HW only at the next frame start
675 	 * event which is after the vblank start event, so we need to have a
676 	 * wait-for-vblank between disabling the plane and the pipe.
677 	 */
678 	if (HAS_GMCH(dev_priv) &&
679 	    intel_set_memory_cxsr(dev_priv, false))
680 		intel_crtc_wait_for_next_vblank(crtc);
681 
682 	/*
683 	 * Gen2 reports pipe underruns whenever all planes are disabled.
684 	 * So disable underrun reporting before all the planes get disabled.
685 	 */
686 	if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes)
687 		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
688 
689 	intel_plane_disable_arm(plane, crtc_state);
690 	intel_crtc_wait_for_next_vblank(crtc);
691 }
692 
693 unsigned int
694 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
695 {
696 	int x = 0, y = 0;
697 
698 	intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
699 					  plane_state->view.color_plane[0].offset, 0);
700 
701 	return y;
702 }
703 
704 static int
705 intel_display_commit_duplicated_state(struct intel_atomic_state *state,
706 				      struct drm_modeset_acquire_ctx *ctx)
707 {
708 	struct drm_i915_private *i915 = to_i915(state->base.dev);
709 	int ret;
710 
711 	ret = drm_atomic_helper_commit_duplicated_state(&state->base, ctx);
712 
713 	drm_WARN_ON(&i915->drm, ret == -EDEADLK);
714 
715 	return ret;
716 }
717 
718 static int
719 __intel_display_resume(struct drm_i915_private *i915,
720 		       struct drm_atomic_state *state,
721 		       struct drm_modeset_acquire_ctx *ctx)
722 {
723 	struct drm_crtc_state *crtc_state;
724 	struct drm_crtc *crtc;
725 	int i;
726 
727 	intel_modeset_setup_hw_state(i915, ctx);
728 	intel_vga_redisable(i915);
729 
730 	if (!state)
731 		return 0;
732 
733 	/*
734 	 * We've duplicated the state, pointers to the old state are invalid.
735 	 *
736 	 * Don't attempt to use the old state until we commit the duplicated state.
737 	 */
738 	for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
739 		/*
740 		 * Force recalculation even if we restore
741 		 * current state. With fast modeset this may not result
742 		 * in a modeset when the state is compatible.
743 		 */
744 		crtc_state->mode_changed = true;
745 	}
746 
747 	/* ignore any reset values/BIOS leftovers in the WM registers */
748 	if (!HAS_GMCH(i915))
749 		to_intel_atomic_state(state)->skip_intermediate_wm = true;
750 
751 	return intel_display_commit_duplicated_state(to_intel_atomic_state(state), ctx);
752 }
753 
754 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
755 {
756 	return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
757 		intel_has_gpu_reset(to_gt(dev_priv)));
758 }
759 
760 void intel_display_prepare_reset(struct drm_i915_private *dev_priv)
761 {
762 	struct drm_modeset_acquire_ctx *ctx = &dev_priv->display.restore.reset_ctx;
763 	struct drm_atomic_state *state;
764 	int ret;
765 
766 	if (!HAS_DISPLAY(dev_priv))
767 		return;
768 
769 	/* reset doesn't touch the display */
770 	if (!dev_priv->params.force_reset_modeset_test &&
771 	    !gpu_reset_clobbers_display(dev_priv))
772 		return;
773 
774 	/* We have a modeset vs reset deadlock, defensively unbreak it. */
775 	set_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags);
776 	smp_mb__after_atomic();
777 	wake_up_bit(&to_gt(dev_priv)->reset.flags, I915_RESET_MODESET);
778 
779 	if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
780 		drm_dbg_kms(&dev_priv->drm,
781 			    "Modeset potentially stuck, unbreaking through wedging\n");
782 		intel_gt_set_wedged(to_gt(dev_priv));
783 	}
784 
785 	/*
786 	 * Need mode_config.mutex so that we don't
787 	 * trample ongoing ->detect() and whatnot.
788 	 */
789 	mutex_lock(&dev_priv->drm.mode_config.mutex);
790 	drm_modeset_acquire_init(ctx, 0);
791 	while (1) {
792 		ret = drm_modeset_lock_all_ctx(&dev_priv->drm, ctx);
793 		if (ret != -EDEADLK)
794 			break;
795 
796 		drm_modeset_backoff(ctx);
797 	}
798 	/*
799 	 * Disabling the crtcs gracefully seems nicer. Also the
800 	 * g33 docs say we should at least disable all the planes.
801 	 */
802 	state = drm_atomic_helper_duplicate_state(&dev_priv->drm, ctx);
803 	if (IS_ERR(state)) {
804 		ret = PTR_ERR(state);
805 		drm_err(&dev_priv->drm, "Duplicating state failed with %i\n",
806 			ret);
807 		return;
808 	}
809 
810 	ret = drm_atomic_helper_disable_all(&dev_priv->drm, ctx);
811 	if (ret) {
812 		drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
813 			ret);
814 		drm_atomic_state_put(state);
815 		return;
816 	}
817 
818 	dev_priv->display.restore.modeset_state = state;
819 	state->acquire_ctx = ctx;
820 }
821 
822 void intel_display_finish_reset(struct drm_i915_private *i915)
823 {
824 	struct drm_modeset_acquire_ctx *ctx = &i915->display.restore.reset_ctx;
825 	struct drm_atomic_state *state;
826 	int ret;
827 
828 	if (!HAS_DISPLAY(i915))
829 		return;
830 
831 	/* reset doesn't touch the display */
832 	if (!test_bit(I915_RESET_MODESET, &to_gt(i915)->reset.flags))
833 		return;
834 
835 	state = fetch_and_zero(&i915->display.restore.modeset_state);
836 	if (!state)
837 		goto unlock;
838 
839 	/* reset doesn't touch the display */
840 	if (!gpu_reset_clobbers_display(i915)) {
841 		/* for testing only restore the display */
842 		ret = intel_display_commit_duplicated_state(to_intel_atomic_state(state), ctx);
843 		if (ret)
844 			drm_err(&i915->drm,
845 				"Restoring old state failed with %i\n", ret);
846 	} else {
847 		/*
848 		 * The display has been reset as well,
849 		 * so need a full re-initialization.
850 		 */
851 		intel_pps_unlock_regs_wa(i915);
852 		intel_modeset_init_hw(i915);
853 		intel_clock_gating_init(i915);
854 		intel_hpd_init(i915);
855 
856 		ret = __intel_display_resume(i915, state, ctx);
857 		if (ret)
858 			drm_err(&i915->drm,
859 				"Restoring old state failed with %i\n", ret);
860 
861 		intel_hpd_poll_disable(i915);
862 	}
863 
864 	drm_atomic_state_put(state);
865 unlock:
866 	drm_modeset_drop_locks(ctx);
867 	drm_modeset_acquire_fini(ctx);
868 	mutex_unlock(&i915->drm.mode_config.mutex);
869 
870 	clear_bit_unlock(I915_RESET_MODESET, &to_gt(i915)->reset.flags);
871 }
872 
873 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state)
874 {
875 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
876 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
877 	enum pipe pipe = crtc->pipe;
878 	u32 tmp;
879 
880 	tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe));
881 
882 	/*
883 	 * Display WA #1153: icl
884 	 * enable hardware to bypass the alpha math
885 	 * and rounding for per-pixel values 00 and 0xff
886 	 */
887 	tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
888 	/*
889 	 * Display WA # 1605353570: icl
890 	 * Set the pixel rounding bit to 1 for allowing
891 	 * passthrough of Frame buffer pixels unmodified
892 	 * across pipe
893 	 */
894 	tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
895 
896 	/*
897 	 * Underrun recovery must always be disabled on display 13+.
898 	 * DG2 chicken bit meaning is inverted compared to other platforms.
899 	 */
900 	if (IS_DG2(dev_priv))
901 		tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2;
902 	else if (DISPLAY_VER(dev_priv) >= 13)
903 		tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP;
904 
905 	/* Wa_14010547955:dg2 */
906 	if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER))
907 		tmp |= DG2_RENDER_CCSTAG_4_3_EN;
908 
909 	intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
910 }
911 
912 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
913 {
914 	struct drm_crtc *crtc;
915 	bool cleanup_done;
916 
917 	drm_for_each_crtc(crtc, &dev_priv->drm) {
918 		struct drm_crtc_commit *commit;
919 		spin_lock(&crtc->commit_lock);
920 		commit = list_first_entry_or_null(&crtc->commit_list,
921 						  struct drm_crtc_commit, commit_entry);
922 		cleanup_done = commit ?
923 			try_wait_for_completion(&commit->cleanup_done) : true;
924 		spin_unlock(&crtc->commit_lock);
925 
926 		if (cleanup_done)
927 			continue;
928 
929 		intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc));
930 
931 		return true;
932 	}
933 
934 	return false;
935 }
936 
937 /*
938  * Finds the encoder associated with the given CRTC. This can only be
939  * used when we know that the CRTC isn't feeding multiple encoders!
940  */
941 struct intel_encoder *
942 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
943 			   const struct intel_crtc_state *crtc_state)
944 {
945 	const struct drm_connector_state *connector_state;
946 	const struct drm_connector *connector;
947 	struct intel_encoder *encoder = NULL;
948 	struct intel_crtc *master_crtc;
949 	int num_encoders = 0;
950 	int i;
951 
952 	master_crtc = intel_master_crtc(crtc_state);
953 
954 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
955 		if (connector_state->crtc != &master_crtc->base)
956 			continue;
957 
958 		encoder = to_intel_encoder(connector_state->best_encoder);
959 		num_encoders++;
960 	}
961 
962 	drm_WARN(state->base.dev, num_encoders != 1,
963 		 "%d encoders for pipe %c\n",
964 		 num_encoders, pipe_name(master_crtc->pipe));
965 
966 	return encoder;
967 }
968 
969 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
970 {
971 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
972 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
973 	const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
974 	enum pipe pipe = crtc->pipe;
975 	int width = drm_rect_width(dst);
976 	int height = drm_rect_height(dst);
977 	int x = dst->x1;
978 	int y = dst->y1;
979 
980 	if (!crtc_state->pch_pfit.enabled)
981 		return;
982 
983 	/* Force use of hard-coded filter coefficients
984 	 * as some pre-programmed values are broken,
985 	 * e.g. x201.
986 	 */
987 	if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
988 		intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
989 				  PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
990 	else
991 		intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
992 				  PF_FILTER_MED_3x3);
993 	intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
994 	intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
995 }
996 
997 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
998 {
999 	if (crtc->overlay)
1000 		(void) intel_overlay_switch_off(crtc->overlay);
1001 
1002 	/* Let userspace switch the overlay on again. In most cases userspace
1003 	 * has to recompute where to put it anyway.
1004 	 */
1005 }
1006 
1007 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
1008 {
1009 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1010 
1011 	if (!crtc_state->nv12_planes)
1012 		return false;
1013 
1014 	/* WA Display #0827: Gen9:all */
1015 	if (DISPLAY_VER(dev_priv) == 9)
1016 		return true;
1017 
1018 	return false;
1019 }
1020 
1021 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
1022 {
1023 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1024 
1025 	/* Wa_2006604312:icl,ehl */
1026 	if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11)
1027 		return true;
1028 
1029 	return false;
1030 }
1031 
1032 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state)
1033 {
1034 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1035 
1036 	/* Wa_1604331009:icl,jsl,ehl */
1037 	if (is_hdr_mode(crtc_state) &&
1038 	    crtc_state->active_planes & BIT(PLANE_CURSOR) &&
1039 	    DISPLAY_VER(dev_priv) == 11)
1040 		return true;
1041 
1042 	return false;
1043 }
1044 
1045 static void intel_async_flip_vtd_wa(struct drm_i915_private *i915,
1046 				    enum pipe pipe, bool enable)
1047 {
1048 	if (DISPLAY_VER(i915) == 9) {
1049 		/*
1050 		 * "Plane N strech max must be programmed to 11b (x1)
1051 		 *  when Async flips are enabled on that plane."
1052 		 */
1053 		intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe),
1054 			     SKL_PLANE1_STRETCH_MAX_MASK,
1055 			     enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8);
1056 	} else {
1057 		/* Also needed on HSW/BDW albeit undocumented */
1058 		intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe),
1059 			     HSW_PRI_STRETCH_MAX_MASK,
1060 			     enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8);
1061 	}
1062 }
1063 
1064 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state)
1065 {
1066 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1067 
1068 	return crtc_state->uapi.async_flip && i915_vtd_active(i915) &&
1069 		(DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915));
1070 }
1071 
1072 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
1073 			    const struct intel_crtc_state *new_crtc_state)
1074 {
1075 	return (!old_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)) &&
1076 		new_crtc_state->active_planes;
1077 }
1078 
1079 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
1080 			     const struct intel_crtc_state *new_crtc_state)
1081 {
1082 	return old_crtc_state->active_planes &&
1083 		(!new_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state));
1084 }
1085 
1086 static void intel_post_plane_update(struct intel_atomic_state *state,
1087 				    struct intel_crtc *crtc)
1088 {
1089 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1090 	const struct intel_crtc_state *old_crtc_state =
1091 		intel_atomic_get_old_crtc_state(state, crtc);
1092 	const struct intel_crtc_state *new_crtc_state =
1093 		intel_atomic_get_new_crtc_state(state, crtc);
1094 	enum pipe pipe = crtc->pipe;
1095 
1096 	intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
1097 
1098 	if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
1099 		intel_update_watermarks(dev_priv);
1100 
1101 	intel_fbc_post_update(state, crtc);
1102 
1103 	if (needs_async_flip_vtd_wa(old_crtc_state) &&
1104 	    !needs_async_flip_vtd_wa(new_crtc_state))
1105 		intel_async_flip_vtd_wa(dev_priv, pipe, false);
1106 
1107 	if (needs_nv12_wa(old_crtc_state) &&
1108 	    !needs_nv12_wa(new_crtc_state))
1109 		skl_wa_827(dev_priv, pipe, false);
1110 
1111 	if (needs_scalerclk_wa(old_crtc_state) &&
1112 	    !needs_scalerclk_wa(new_crtc_state))
1113 		icl_wa_scalerclkgating(dev_priv, pipe, false);
1114 
1115 	if (needs_cursorclk_wa(old_crtc_state) &&
1116 	    !needs_cursorclk_wa(new_crtc_state))
1117 		icl_wa_cursorclkgating(dev_priv, pipe, false);
1118 
1119 	if (intel_crtc_needs_color_update(new_crtc_state))
1120 		intel_color_post_update(new_crtc_state);
1121 }
1122 
1123 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state,
1124 					struct intel_crtc *crtc)
1125 {
1126 	const struct intel_crtc_state *crtc_state =
1127 		intel_atomic_get_new_crtc_state(state, crtc);
1128 	u8 update_planes = crtc_state->update_planes;
1129 	const struct intel_plane_state *plane_state;
1130 	struct intel_plane *plane;
1131 	int i;
1132 
1133 	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1134 		if (plane->pipe == crtc->pipe &&
1135 		    update_planes & BIT(plane->id))
1136 			plane->enable_flip_done(plane);
1137 	}
1138 }
1139 
1140 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state,
1141 					 struct intel_crtc *crtc)
1142 {
1143 	const struct intel_crtc_state *crtc_state =
1144 		intel_atomic_get_new_crtc_state(state, crtc);
1145 	u8 update_planes = crtc_state->update_planes;
1146 	const struct intel_plane_state *plane_state;
1147 	struct intel_plane *plane;
1148 	int i;
1149 
1150 	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1151 		if (plane->pipe == crtc->pipe &&
1152 		    update_planes & BIT(plane->id))
1153 			plane->disable_flip_done(plane);
1154 	}
1155 }
1156 
1157 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
1158 					     struct intel_crtc *crtc)
1159 {
1160 	const struct intel_crtc_state *old_crtc_state =
1161 		intel_atomic_get_old_crtc_state(state, crtc);
1162 	const struct intel_crtc_state *new_crtc_state =
1163 		intel_atomic_get_new_crtc_state(state, crtc);
1164 	u8 disable_async_flip_planes = old_crtc_state->async_flip_planes &
1165 				       ~new_crtc_state->async_flip_planes;
1166 	const struct intel_plane_state *old_plane_state;
1167 	struct intel_plane *plane;
1168 	bool need_vbl_wait = false;
1169 	int i;
1170 
1171 	for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
1172 		if (plane->need_async_flip_disable_wa &&
1173 		    plane->pipe == crtc->pipe &&
1174 		    disable_async_flip_planes & BIT(plane->id)) {
1175 			/*
1176 			 * Apart from the async flip bit we want to
1177 			 * preserve the old state for the plane.
1178 			 */
1179 			plane->async_flip(plane, old_crtc_state,
1180 					  old_plane_state, false);
1181 			need_vbl_wait = true;
1182 		}
1183 	}
1184 
1185 	if (need_vbl_wait)
1186 		intel_crtc_wait_for_next_vblank(crtc);
1187 }
1188 
1189 static void intel_pre_plane_update(struct intel_atomic_state *state,
1190 				   struct intel_crtc *crtc)
1191 {
1192 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1193 	const struct intel_crtc_state *old_crtc_state =
1194 		intel_atomic_get_old_crtc_state(state, crtc);
1195 	const struct intel_crtc_state *new_crtc_state =
1196 		intel_atomic_get_new_crtc_state(state, crtc);
1197 	enum pipe pipe = crtc->pipe;
1198 
1199 	intel_drrs_deactivate(old_crtc_state);
1200 
1201 	intel_psr_pre_plane_update(state, crtc);
1202 
1203 	if (hsw_ips_pre_update(state, crtc))
1204 		intel_crtc_wait_for_next_vblank(crtc);
1205 
1206 	if (intel_fbc_pre_update(state, crtc))
1207 		intel_crtc_wait_for_next_vblank(crtc);
1208 
1209 	if (!needs_async_flip_vtd_wa(old_crtc_state) &&
1210 	    needs_async_flip_vtd_wa(new_crtc_state))
1211 		intel_async_flip_vtd_wa(dev_priv, pipe, true);
1212 
1213 	/* Display WA 827 */
1214 	if (!needs_nv12_wa(old_crtc_state) &&
1215 	    needs_nv12_wa(new_crtc_state))
1216 		skl_wa_827(dev_priv, pipe, true);
1217 
1218 	/* Wa_2006604312:icl,ehl */
1219 	if (!needs_scalerclk_wa(old_crtc_state) &&
1220 	    needs_scalerclk_wa(new_crtc_state))
1221 		icl_wa_scalerclkgating(dev_priv, pipe, true);
1222 
1223 	/* Wa_1604331009:icl,jsl,ehl */
1224 	if (!needs_cursorclk_wa(old_crtc_state) &&
1225 	    needs_cursorclk_wa(new_crtc_state))
1226 		icl_wa_cursorclkgating(dev_priv, pipe, true);
1227 
1228 	/*
1229 	 * Vblank time updates from the shadow to live plane control register
1230 	 * are blocked if the memory self-refresh mode is active at that
1231 	 * moment. So to make sure the plane gets truly disabled, disable
1232 	 * first the self-refresh mode. The self-refresh enable bit in turn
1233 	 * will be checked/applied by the HW only at the next frame start
1234 	 * event which is after the vblank start event, so we need to have a
1235 	 * wait-for-vblank between disabling the plane and the pipe.
1236 	 */
1237 	if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
1238 	    new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
1239 		intel_crtc_wait_for_next_vblank(crtc);
1240 
1241 	/*
1242 	 * IVB workaround: must disable low power watermarks for at least
1243 	 * one frame before enabling scaling.  LP watermarks can be re-enabled
1244 	 * when scaling is disabled.
1245 	 *
1246 	 * WaCxSRDisabledForSpriteScaling:ivb
1247 	 */
1248 	if (old_crtc_state->hw.active &&
1249 	    new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
1250 		intel_crtc_wait_for_next_vblank(crtc);
1251 
1252 	/*
1253 	 * If we're doing a modeset we don't need to do any
1254 	 * pre-vblank watermark programming here.
1255 	 */
1256 	if (!intel_crtc_needs_modeset(new_crtc_state)) {
1257 		/*
1258 		 * For platforms that support atomic watermarks, program the
1259 		 * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
1260 		 * will be the intermediate values that are safe for both pre- and
1261 		 * post- vblank; when vblank happens, the 'active' values will be set
1262 		 * to the final 'target' values and we'll do this again to get the
1263 		 * optimal watermarks.  For gen9+ platforms, the values we program here
1264 		 * will be the final target values which will get automatically latched
1265 		 * at vblank time; no further programming will be necessary.
1266 		 *
1267 		 * If a platform hasn't been transitioned to atomic watermarks yet,
1268 		 * we'll continue to update watermarks the old way, if flags tell
1269 		 * us to.
1270 		 */
1271 		if (!intel_initial_watermarks(state, crtc))
1272 			if (new_crtc_state->update_wm_pre)
1273 				intel_update_watermarks(dev_priv);
1274 	}
1275 
1276 	/*
1277 	 * Gen2 reports pipe underruns whenever all planes are disabled.
1278 	 * So disable underrun reporting before all the planes get disabled.
1279 	 *
1280 	 * We do this after .initial_watermarks() so that we have a
1281 	 * chance of catching underruns with the intermediate watermarks
1282 	 * vs. the old plane configuration.
1283 	 */
1284 	if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state))
1285 		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1286 
1287 	/*
1288 	 * WA for platforms where async address update enable bit
1289 	 * is double buffered and only latched at start of vblank.
1290 	 */
1291 	if (old_crtc_state->async_flip_planes & ~new_crtc_state->async_flip_planes)
1292 		intel_crtc_async_flip_disable_wa(state, crtc);
1293 }
1294 
1295 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
1296 				      struct intel_crtc *crtc)
1297 {
1298 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1299 	const struct intel_crtc_state *new_crtc_state =
1300 		intel_atomic_get_new_crtc_state(state, crtc);
1301 	unsigned int update_mask = new_crtc_state->update_planes;
1302 	const struct intel_plane_state *old_plane_state;
1303 	struct intel_plane *plane;
1304 	unsigned fb_bits = 0;
1305 	int i;
1306 
1307 	intel_crtc_dpms_overlay_disable(crtc);
1308 
1309 	for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
1310 		if (crtc->pipe != plane->pipe ||
1311 		    !(update_mask & BIT(plane->id)))
1312 			continue;
1313 
1314 		intel_plane_disable_arm(plane, new_crtc_state);
1315 
1316 		if (old_plane_state->uapi.visible)
1317 			fb_bits |= plane->frontbuffer_bit;
1318 	}
1319 
1320 	intel_frontbuffer_flip(dev_priv, fb_bits);
1321 }
1322 
1323 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
1324 {
1325 	struct drm_i915_private *i915 = to_i915(state->base.dev);
1326 	struct intel_crtc_state *new_crtc_state, *old_crtc_state;
1327 	struct intel_crtc *crtc;
1328 	int i;
1329 
1330 	/*
1331 	 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits.
1332 	 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook.
1333 	 */
1334 	if (i915->display.dpll.mgr) {
1335 		for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1336 			if (intel_crtc_needs_modeset(new_crtc_state))
1337 				continue;
1338 
1339 			new_crtc_state->shared_dpll = old_crtc_state->shared_dpll;
1340 			new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state;
1341 		}
1342 	}
1343 }
1344 
1345 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
1346 					  struct intel_crtc *crtc)
1347 {
1348 	const struct intel_crtc_state *crtc_state =
1349 		intel_atomic_get_new_crtc_state(state, crtc);
1350 	const struct drm_connector_state *conn_state;
1351 	struct drm_connector *conn;
1352 	int i;
1353 
1354 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1355 		struct intel_encoder *encoder =
1356 			to_intel_encoder(conn_state->best_encoder);
1357 
1358 		if (conn_state->crtc != &crtc->base)
1359 			continue;
1360 
1361 		if (encoder->pre_pll_enable)
1362 			encoder->pre_pll_enable(state, encoder,
1363 						crtc_state, conn_state);
1364 	}
1365 }
1366 
1367 static void intel_encoders_pre_enable(struct intel_atomic_state *state,
1368 				      struct intel_crtc *crtc)
1369 {
1370 	const struct intel_crtc_state *crtc_state =
1371 		intel_atomic_get_new_crtc_state(state, crtc);
1372 	const struct drm_connector_state *conn_state;
1373 	struct drm_connector *conn;
1374 	int i;
1375 
1376 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1377 		struct intel_encoder *encoder =
1378 			to_intel_encoder(conn_state->best_encoder);
1379 
1380 		if (conn_state->crtc != &crtc->base)
1381 			continue;
1382 
1383 		if (encoder->pre_enable)
1384 			encoder->pre_enable(state, encoder,
1385 					    crtc_state, conn_state);
1386 	}
1387 }
1388 
1389 static void intel_encoders_enable(struct intel_atomic_state *state,
1390 				  struct intel_crtc *crtc)
1391 {
1392 	const struct intel_crtc_state *crtc_state =
1393 		intel_atomic_get_new_crtc_state(state, crtc);
1394 	const struct drm_connector_state *conn_state;
1395 	struct drm_connector *conn;
1396 	int i;
1397 
1398 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1399 		struct intel_encoder *encoder =
1400 			to_intel_encoder(conn_state->best_encoder);
1401 
1402 		if (conn_state->crtc != &crtc->base)
1403 			continue;
1404 
1405 		if (encoder->enable)
1406 			encoder->enable(state, encoder,
1407 					crtc_state, conn_state);
1408 		intel_opregion_notify_encoder(encoder, true);
1409 	}
1410 }
1411 
1412 static void intel_encoders_disable(struct intel_atomic_state *state,
1413 				   struct intel_crtc *crtc)
1414 {
1415 	const struct intel_crtc_state *old_crtc_state =
1416 		intel_atomic_get_old_crtc_state(state, crtc);
1417 	const struct drm_connector_state *old_conn_state;
1418 	struct drm_connector *conn;
1419 	int i;
1420 
1421 	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1422 		struct intel_encoder *encoder =
1423 			to_intel_encoder(old_conn_state->best_encoder);
1424 
1425 		if (old_conn_state->crtc != &crtc->base)
1426 			continue;
1427 
1428 		intel_opregion_notify_encoder(encoder, false);
1429 		if (encoder->disable)
1430 			encoder->disable(state, encoder,
1431 					 old_crtc_state, old_conn_state);
1432 	}
1433 }
1434 
1435 static void intel_encoders_post_disable(struct intel_atomic_state *state,
1436 					struct intel_crtc *crtc)
1437 {
1438 	const struct intel_crtc_state *old_crtc_state =
1439 		intel_atomic_get_old_crtc_state(state, crtc);
1440 	const struct drm_connector_state *old_conn_state;
1441 	struct drm_connector *conn;
1442 	int i;
1443 
1444 	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1445 		struct intel_encoder *encoder =
1446 			to_intel_encoder(old_conn_state->best_encoder);
1447 
1448 		if (old_conn_state->crtc != &crtc->base)
1449 			continue;
1450 
1451 		if (encoder->post_disable)
1452 			encoder->post_disable(state, encoder,
1453 					      old_crtc_state, old_conn_state);
1454 	}
1455 }
1456 
1457 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
1458 					    struct intel_crtc *crtc)
1459 {
1460 	const struct intel_crtc_state *old_crtc_state =
1461 		intel_atomic_get_old_crtc_state(state, crtc);
1462 	const struct drm_connector_state *old_conn_state;
1463 	struct drm_connector *conn;
1464 	int i;
1465 
1466 	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1467 		struct intel_encoder *encoder =
1468 			to_intel_encoder(old_conn_state->best_encoder);
1469 
1470 		if (old_conn_state->crtc != &crtc->base)
1471 			continue;
1472 
1473 		if (encoder->post_pll_disable)
1474 			encoder->post_pll_disable(state, encoder,
1475 						  old_crtc_state, old_conn_state);
1476 	}
1477 }
1478 
1479 static void intel_encoders_update_pipe(struct intel_atomic_state *state,
1480 				       struct intel_crtc *crtc)
1481 {
1482 	const struct intel_crtc_state *crtc_state =
1483 		intel_atomic_get_new_crtc_state(state, crtc);
1484 	const struct drm_connector_state *conn_state;
1485 	struct drm_connector *conn;
1486 	int i;
1487 
1488 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1489 		struct intel_encoder *encoder =
1490 			to_intel_encoder(conn_state->best_encoder);
1491 
1492 		if (conn_state->crtc != &crtc->base)
1493 			continue;
1494 
1495 		if (encoder->update_pipe)
1496 			encoder->update_pipe(state, encoder,
1497 					     crtc_state, conn_state);
1498 	}
1499 }
1500 
1501 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
1502 {
1503 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1504 	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1505 
1506 	plane->disable_arm(plane, crtc_state);
1507 }
1508 
1509 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1510 {
1511 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1512 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1513 
1514 	if (crtc_state->has_pch_encoder) {
1515 		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1516 					       &crtc_state->fdi_m_n);
1517 	} else if (intel_crtc_has_dp_encoder(crtc_state)) {
1518 		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1519 					       &crtc_state->dp_m_n);
1520 		intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1521 					       &crtc_state->dp_m2_n2);
1522 	}
1523 
1524 	intel_set_transcoder_timings(crtc_state);
1525 
1526 	ilk_set_pipeconf(crtc_state);
1527 }
1528 
1529 static void ilk_crtc_enable(struct intel_atomic_state *state,
1530 			    struct intel_crtc *crtc)
1531 {
1532 	const struct intel_crtc_state *new_crtc_state =
1533 		intel_atomic_get_new_crtc_state(state, crtc);
1534 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1535 	enum pipe pipe = crtc->pipe;
1536 
1537 	if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1538 		return;
1539 
1540 	/*
1541 	 * Sometimes spurious CPU pipe underruns happen during FDI
1542 	 * training, at least with VGA+HDMI cloning. Suppress them.
1543 	 *
1544 	 * On ILK we get an occasional spurious CPU pipe underruns
1545 	 * between eDP port A enable and vdd enable. Also PCH port
1546 	 * enable seems to result in the occasional CPU pipe underrun.
1547 	 *
1548 	 * Spurious PCH underruns also occur during PCH enabling.
1549 	 */
1550 	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1551 	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
1552 
1553 	ilk_configure_cpu_transcoder(new_crtc_state);
1554 
1555 	intel_set_pipe_src_size(new_crtc_state);
1556 
1557 	crtc->active = true;
1558 
1559 	intel_encoders_pre_enable(state, crtc);
1560 
1561 	if (new_crtc_state->has_pch_encoder) {
1562 		ilk_pch_pre_enable(state, crtc);
1563 	} else {
1564 		assert_fdi_tx_disabled(dev_priv, pipe);
1565 		assert_fdi_rx_disabled(dev_priv, pipe);
1566 	}
1567 
1568 	ilk_pfit_enable(new_crtc_state);
1569 
1570 	/*
1571 	 * On ILK+ LUT must be loaded before the pipe is running but with
1572 	 * clocks enabled
1573 	 */
1574 	intel_color_load_luts(new_crtc_state);
1575 	intel_color_commit_noarm(new_crtc_state);
1576 	intel_color_commit_arm(new_crtc_state);
1577 	/* update DSPCNTR to configure gamma for pipe bottom color */
1578 	intel_disable_primary_plane(new_crtc_state);
1579 
1580 	intel_initial_watermarks(state, crtc);
1581 	intel_enable_transcoder(new_crtc_state);
1582 
1583 	if (new_crtc_state->has_pch_encoder)
1584 		ilk_pch_enable(state, crtc);
1585 
1586 	intel_crtc_vblank_on(new_crtc_state);
1587 
1588 	intel_encoders_enable(state, crtc);
1589 
1590 	if (HAS_PCH_CPT(dev_priv))
1591 		intel_wait_for_pipe_scanline_moving(crtc);
1592 
1593 	/*
1594 	 * Must wait for vblank to avoid spurious PCH FIFO underruns.
1595 	 * And a second vblank wait is needed at least on ILK with
1596 	 * some interlaced HDMI modes. Let's do the double wait always
1597 	 * in case there are more corner cases we don't know about.
1598 	 */
1599 	if (new_crtc_state->has_pch_encoder) {
1600 		intel_crtc_wait_for_next_vblank(crtc);
1601 		intel_crtc_wait_for_next_vblank(crtc);
1602 	}
1603 	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
1604 	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
1605 }
1606 
1607 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
1608 					    enum pipe pipe, bool apply)
1609 {
1610 	u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe));
1611 	u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
1612 
1613 	if (apply)
1614 		val |= mask;
1615 	else
1616 		val &= ~mask;
1617 
1618 	intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
1619 }
1620 
1621 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
1622 {
1623 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1624 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1625 
1626 	intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),
1627 		       HSW_LINETIME(crtc_state->linetime) |
1628 		       HSW_IPS_LINETIME(crtc_state->ips_linetime));
1629 }
1630 
1631 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
1632 {
1633 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1634 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1635 	enum transcoder transcoder = crtc_state->cpu_transcoder;
1636 	i915_reg_t reg = DISPLAY_VER(dev_priv) >= 14 ? MTL_CHICKEN_TRANS(transcoder) :
1637 			 CHICKEN_TRANS(transcoder);
1638 
1639 	intel_de_rmw(dev_priv, reg,
1640 		     HSW_FRAME_START_DELAY_MASK,
1641 		     HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1));
1642 }
1643 
1644 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
1645 					 const struct intel_crtc_state *crtc_state)
1646 {
1647 	struct intel_crtc *master_crtc = intel_master_crtc(crtc_state);
1648 
1649 	/*
1650 	 * Enable sequence steps 1-7 on bigjoiner master
1651 	 */
1652 	if (intel_crtc_is_bigjoiner_slave(crtc_state))
1653 		intel_encoders_pre_pll_enable(state, master_crtc);
1654 
1655 	if (crtc_state->shared_dpll)
1656 		intel_enable_shared_dpll(crtc_state);
1657 
1658 	if (intel_crtc_is_bigjoiner_slave(crtc_state))
1659 		intel_encoders_pre_enable(state, master_crtc);
1660 }
1661 
1662 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1663 {
1664 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1665 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1666 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1667 
1668 	if (crtc_state->has_pch_encoder) {
1669 		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1670 					       &crtc_state->fdi_m_n);
1671 	} else if (intel_crtc_has_dp_encoder(crtc_state)) {
1672 		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1673 					       &crtc_state->dp_m_n);
1674 		intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1675 					       &crtc_state->dp_m2_n2);
1676 	}
1677 
1678 	intel_set_transcoder_timings(crtc_state);
1679 
1680 	if (cpu_transcoder != TRANSCODER_EDP)
1681 		intel_de_write(dev_priv, TRANS_MULT(cpu_transcoder),
1682 			       crtc_state->pixel_multiplier - 1);
1683 
1684 	hsw_set_frame_start_delay(crtc_state);
1685 
1686 	hsw_set_transconf(crtc_state);
1687 }
1688 
1689 static void hsw_crtc_enable(struct intel_atomic_state *state,
1690 			    struct intel_crtc *crtc)
1691 {
1692 	const struct intel_crtc_state *new_crtc_state =
1693 		intel_atomic_get_new_crtc_state(state, crtc);
1694 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1695 	enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
1696 	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1697 	bool psl_clkgate_wa;
1698 
1699 	if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1700 		return;
1701 
1702 	intel_dmc_enable_pipe(dev_priv, crtc->pipe);
1703 
1704 	if (!new_crtc_state->bigjoiner_pipes) {
1705 		intel_encoders_pre_pll_enable(state, crtc);
1706 
1707 		if (new_crtc_state->shared_dpll)
1708 			intel_enable_shared_dpll(new_crtc_state);
1709 
1710 		intel_encoders_pre_enable(state, crtc);
1711 	} else {
1712 		icl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
1713 	}
1714 
1715 	intel_dsc_enable(new_crtc_state);
1716 
1717 	if (DISPLAY_VER(dev_priv) >= 13)
1718 		intel_uncompressed_joiner_enable(new_crtc_state);
1719 
1720 	intel_set_pipe_src_size(new_crtc_state);
1721 	if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
1722 		bdw_set_pipe_misc(new_crtc_state);
1723 
1724 	if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) &&
1725 	    !transcoder_is_dsi(cpu_transcoder))
1726 		hsw_configure_cpu_transcoder(new_crtc_state);
1727 
1728 	crtc->active = true;
1729 
1730 	/* Display WA #1180: WaDisableScalarClockGating: glk */
1731 	psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 &&
1732 		new_crtc_state->pch_pfit.enabled;
1733 	if (psl_clkgate_wa)
1734 		glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
1735 
1736 	if (DISPLAY_VER(dev_priv) >= 9)
1737 		skl_pfit_enable(new_crtc_state);
1738 	else
1739 		ilk_pfit_enable(new_crtc_state);
1740 
1741 	/*
1742 	 * On ILK+ LUT must be loaded before the pipe is running but with
1743 	 * clocks enabled
1744 	 */
1745 	intel_color_load_luts(new_crtc_state);
1746 	intel_color_commit_noarm(new_crtc_state);
1747 	intel_color_commit_arm(new_crtc_state);
1748 	/* update DSPCNTR to configure gamma/csc for pipe bottom color */
1749 	if (DISPLAY_VER(dev_priv) < 9)
1750 		intel_disable_primary_plane(new_crtc_state);
1751 
1752 	hsw_set_linetime_wm(new_crtc_state);
1753 
1754 	if (DISPLAY_VER(dev_priv) >= 11)
1755 		icl_set_pipe_chicken(new_crtc_state);
1756 
1757 	intel_initial_watermarks(state, crtc);
1758 
1759 	if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
1760 		intel_crtc_vblank_on(new_crtc_state);
1761 
1762 	intel_encoders_enable(state, crtc);
1763 
1764 	if (psl_clkgate_wa) {
1765 		intel_crtc_wait_for_next_vblank(crtc);
1766 		glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
1767 	}
1768 
1769 	/* If we change the relative order between pipe/planes enabling, we need
1770 	 * to change the workaround. */
1771 	hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
1772 	if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
1773 		struct intel_crtc *wa_crtc;
1774 
1775 		wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe);
1776 
1777 		intel_crtc_wait_for_next_vblank(wa_crtc);
1778 		intel_crtc_wait_for_next_vblank(wa_crtc);
1779 	}
1780 }
1781 
1782 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
1783 {
1784 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1785 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1786 	enum pipe pipe = crtc->pipe;
1787 
1788 	/* To avoid upsetting the power well on haswell only disable the pfit if
1789 	 * it's in use. The hw state code will make sure we get this right. */
1790 	if (!old_crtc_state->pch_pfit.enabled)
1791 		return;
1792 
1793 	intel_de_write_fw(dev_priv, PF_CTL(pipe), 0);
1794 	intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0);
1795 	intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0);
1796 }
1797 
1798 static void ilk_crtc_disable(struct intel_atomic_state *state,
1799 			     struct intel_crtc *crtc)
1800 {
1801 	const struct intel_crtc_state *old_crtc_state =
1802 		intel_atomic_get_old_crtc_state(state, crtc);
1803 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1804 	enum pipe pipe = crtc->pipe;
1805 
1806 	/*
1807 	 * Sometimes spurious CPU pipe underruns happen when the
1808 	 * pipe is already disabled, but FDI RX/TX is still enabled.
1809 	 * Happens at least with VGA+HDMI cloning. Suppress them.
1810 	 */
1811 	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1812 	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
1813 
1814 	intel_encoders_disable(state, crtc);
1815 
1816 	intel_crtc_vblank_off(old_crtc_state);
1817 
1818 	intel_disable_transcoder(old_crtc_state);
1819 
1820 	ilk_pfit_disable(old_crtc_state);
1821 
1822 	if (old_crtc_state->has_pch_encoder)
1823 		ilk_pch_disable(state, crtc);
1824 
1825 	intel_encoders_post_disable(state, crtc);
1826 
1827 	if (old_crtc_state->has_pch_encoder)
1828 		ilk_pch_post_disable(state, crtc);
1829 
1830 	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
1831 	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
1832 
1833 	intel_disable_shared_dpll(old_crtc_state);
1834 }
1835 
1836 static void hsw_crtc_disable(struct intel_atomic_state *state,
1837 			     struct intel_crtc *crtc)
1838 {
1839 	const struct intel_crtc_state *old_crtc_state =
1840 		intel_atomic_get_old_crtc_state(state, crtc);
1841 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1842 
1843 	/*
1844 	 * FIXME collapse everything to one hook.
1845 	 * Need care with mst->ddi interactions.
1846 	 */
1847 	if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) {
1848 		intel_encoders_disable(state, crtc);
1849 		intel_encoders_post_disable(state, crtc);
1850 	}
1851 
1852 	intel_disable_shared_dpll(old_crtc_state);
1853 
1854 	intel_encoders_post_pll_disable(state, crtc);
1855 
1856 	intel_dmc_disable_pipe(i915, crtc->pipe);
1857 }
1858 
1859 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
1860 {
1861 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1862 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1863 
1864 	if (!crtc_state->gmch_pfit.control)
1865 		return;
1866 
1867 	/*
1868 	 * The panel fitter should only be adjusted whilst the pipe is disabled,
1869 	 * according to register description and PRM.
1870 	 */
1871 	drm_WARN_ON(&dev_priv->drm,
1872 		    intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
1873 	assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
1874 
1875 	intel_de_write(dev_priv, PFIT_PGM_RATIOS,
1876 		       crtc_state->gmch_pfit.pgm_ratios);
1877 	intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);
1878 
1879 	/* Border color in case we don't scale up to the full screen. Black by
1880 	 * default, change to something else for debugging. */
1881 	intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
1882 }
1883 
1884 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
1885 {
1886 	if (phy == PHY_NONE)
1887 		return false;
1888 	else if (IS_ALDERLAKE_S(dev_priv))
1889 		return phy <= PHY_E;
1890 	else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
1891 		return phy <= PHY_D;
1892 	else if (IS_JSL_EHL(dev_priv))
1893 		return phy <= PHY_C;
1894 	else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12))
1895 		return phy <= PHY_B;
1896 	else
1897 		/*
1898 		 * DG2 outputs labelled as "combo PHY" in the bspec use
1899 		 * SNPS PHYs with completely different programming,
1900 		 * hence we always return false here.
1901 		 */
1902 		return false;
1903 }
1904 
1905 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
1906 {
1907 	if (IS_DG2(dev_priv))
1908 		/* DG2's "TC1" output uses a SNPS PHY */
1909 		return false;
1910 	else if (IS_ALDERLAKE_P(dev_priv))
1911 		return phy >= PHY_F && phy <= PHY_I;
1912 	else if (IS_TIGERLAKE(dev_priv))
1913 		return phy >= PHY_D && phy <= PHY_I;
1914 	else if (IS_ICELAKE(dev_priv))
1915 		return phy >= PHY_C && phy <= PHY_F;
1916 	else
1917 		return false;
1918 }
1919 
1920 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy)
1921 {
1922 	if (phy == PHY_NONE)
1923 		return false;
1924 	else if (IS_DG2(dev_priv))
1925 		/*
1926 		 * All four "combo" ports and the TC1 port (PHY E) use
1927 		 * Synopsis PHYs.
1928 		 */
1929 		return phy <= PHY_E;
1930 
1931 	return false;
1932 }
1933 
1934 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
1935 {
1936 	if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD)
1937 		return PHY_D + port - PORT_D_XELPD;
1938 	else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1)
1939 		return PHY_F + port - PORT_TC1;
1940 	else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
1941 		return PHY_B + port - PORT_TC1;
1942 	else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
1943 		return PHY_C + port - PORT_TC1;
1944 	else if (IS_JSL_EHL(i915) && port == PORT_D)
1945 		return PHY_A;
1946 
1947 	return PHY_A + port - PORT_A;
1948 }
1949 
1950 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
1951 {
1952 	if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
1953 		return TC_PORT_NONE;
1954 
1955 	if (DISPLAY_VER(dev_priv) >= 12)
1956 		return TC_PORT_1 + port - PORT_TC1;
1957 	else
1958 		return TC_PORT_1 + port - PORT_C;
1959 }
1960 
1961 enum intel_display_power_domain
1962 intel_aux_power_domain(struct intel_digital_port *dig_port)
1963 {
1964 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1965 
1966 	if (intel_tc_port_in_tbt_alt_mode(dig_port))
1967 		return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch);
1968 
1969 	return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch);
1970 }
1971 
1972 static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
1973 				   struct intel_power_domain_mask *mask)
1974 {
1975 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1976 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1977 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1978 	struct drm_encoder *encoder;
1979 	enum pipe pipe = crtc->pipe;
1980 
1981 	bitmap_zero(mask->bits, POWER_DOMAIN_NUM);
1982 
1983 	if (!crtc_state->hw.active)
1984 		return;
1985 
1986 	set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits);
1987 	set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits);
1988 	if (crtc_state->pch_pfit.enabled ||
1989 	    crtc_state->pch_pfit.force_thru)
1990 		set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits);
1991 
1992 	drm_for_each_encoder_mask(encoder, &dev_priv->drm,
1993 				  crtc_state->uapi.encoder_mask) {
1994 		struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1995 
1996 		set_bit(intel_encoder->power_domain, mask->bits);
1997 	}
1998 
1999 	if (HAS_DDI(dev_priv) && crtc_state->has_audio)
2000 		set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits);
2001 
2002 	if (crtc_state->shared_dpll)
2003 		set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits);
2004 
2005 	if (crtc_state->dsc.compression_enable)
2006 		set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits);
2007 }
2008 
2009 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
2010 					  struct intel_power_domain_mask *old_domains)
2011 {
2012 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2013 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2014 	enum intel_display_power_domain domain;
2015 	struct intel_power_domain_mask domains, new_domains;
2016 
2017 	get_crtc_power_domains(crtc_state, &domains);
2018 
2019 	bitmap_andnot(new_domains.bits,
2020 		      domains.bits,
2021 		      crtc->enabled_power_domains.mask.bits,
2022 		      POWER_DOMAIN_NUM);
2023 	bitmap_andnot(old_domains->bits,
2024 		      crtc->enabled_power_domains.mask.bits,
2025 		      domains.bits,
2026 		      POWER_DOMAIN_NUM);
2027 
2028 	for_each_power_domain(domain, &new_domains)
2029 		intel_display_power_get_in_set(dev_priv,
2030 					       &crtc->enabled_power_domains,
2031 					       domain);
2032 }
2033 
2034 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
2035 					  struct intel_power_domain_mask *domains)
2036 {
2037 	intel_display_power_put_mask_in_set(to_i915(crtc->base.dev),
2038 					    &crtc->enabled_power_domains,
2039 					    domains);
2040 }
2041 
2042 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
2043 {
2044 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2045 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2046 
2047 	if (intel_crtc_has_dp_encoder(crtc_state)) {
2048 		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
2049 					       &crtc_state->dp_m_n);
2050 		intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
2051 					       &crtc_state->dp_m2_n2);
2052 	}
2053 
2054 	intel_set_transcoder_timings(crtc_state);
2055 
2056 	i9xx_set_pipeconf(crtc_state);
2057 }
2058 
2059 static void valleyview_crtc_enable(struct intel_atomic_state *state,
2060 				   struct intel_crtc *crtc)
2061 {
2062 	const struct intel_crtc_state *new_crtc_state =
2063 		intel_atomic_get_new_crtc_state(state, crtc);
2064 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2065 	enum pipe pipe = crtc->pipe;
2066 
2067 	if (drm_WARN_ON(&dev_priv->drm, crtc->active))
2068 		return;
2069 
2070 	i9xx_configure_cpu_transcoder(new_crtc_state);
2071 
2072 	intel_set_pipe_src_size(new_crtc_state);
2073 
2074 	intel_de_write(dev_priv, VLV_PIPE_MSA_MISC(pipe), 0);
2075 
2076 	if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
2077 		intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);
2078 		intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
2079 	}
2080 
2081 	crtc->active = true;
2082 
2083 	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2084 
2085 	intel_encoders_pre_pll_enable(state, crtc);
2086 
2087 	if (IS_CHERRYVIEW(dev_priv))
2088 		chv_enable_pll(new_crtc_state);
2089 	else
2090 		vlv_enable_pll(new_crtc_state);
2091 
2092 	intel_encoders_pre_enable(state, crtc);
2093 
2094 	i9xx_pfit_enable(new_crtc_state);
2095 
2096 	intel_color_load_luts(new_crtc_state);
2097 	intel_color_commit_noarm(new_crtc_state);
2098 	intel_color_commit_arm(new_crtc_state);
2099 	/* update DSPCNTR to configure gamma for pipe bottom color */
2100 	intel_disable_primary_plane(new_crtc_state);
2101 
2102 	intel_initial_watermarks(state, crtc);
2103 	intel_enable_transcoder(new_crtc_state);
2104 
2105 	intel_crtc_vblank_on(new_crtc_state);
2106 
2107 	intel_encoders_enable(state, crtc);
2108 }
2109 
2110 static void i9xx_crtc_enable(struct intel_atomic_state *state,
2111 			     struct intel_crtc *crtc)
2112 {
2113 	const struct intel_crtc_state *new_crtc_state =
2114 		intel_atomic_get_new_crtc_state(state, crtc);
2115 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2116 	enum pipe pipe = crtc->pipe;
2117 
2118 	if (drm_WARN_ON(&dev_priv->drm, crtc->active))
2119 		return;
2120 
2121 	i9xx_configure_cpu_transcoder(new_crtc_state);
2122 
2123 	intel_set_pipe_src_size(new_crtc_state);
2124 
2125 	crtc->active = true;
2126 
2127 	if (DISPLAY_VER(dev_priv) != 2)
2128 		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2129 
2130 	intel_encoders_pre_enable(state, crtc);
2131 
2132 	i9xx_enable_pll(new_crtc_state);
2133 
2134 	i9xx_pfit_enable(new_crtc_state);
2135 
2136 	intel_color_load_luts(new_crtc_state);
2137 	intel_color_commit_noarm(new_crtc_state);
2138 	intel_color_commit_arm(new_crtc_state);
2139 	/* update DSPCNTR to configure gamma for pipe bottom color */
2140 	intel_disable_primary_plane(new_crtc_state);
2141 
2142 	if (!intel_initial_watermarks(state, crtc))
2143 		intel_update_watermarks(dev_priv);
2144 	intel_enable_transcoder(new_crtc_state);
2145 
2146 	intel_crtc_vblank_on(new_crtc_state);
2147 
2148 	intel_encoders_enable(state, crtc);
2149 
2150 	/* prevents spurious underruns */
2151 	if (DISPLAY_VER(dev_priv) == 2)
2152 		intel_crtc_wait_for_next_vblank(crtc);
2153 }
2154 
2155 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
2156 {
2157 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
2158 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2159 
2160 	if (!old_crtc_state->gmch_pfit.control)
2161 		return;
2162 
2163 	assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder);
2164 
2165 	drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
2166 		    intel_de_read(dev_priv, PFIT_CONTROL));
2167 	intel_de_write(dev_priv, PFIT_CONTROL, 0);
2168 }
2169 
2170 static void i9xx_crtc_disable(struct intel_atomic_state *state,
2171 			      struct intel_crtc *crtc)
2172 {
2173 	struct intel_crtc_state *old_crtc_state =
2174 		intel_atomic_get_old_crtc_state(state, crtc);
2175 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2176 	enum pipe pipe = crtc->pipe;
2177 
2178 	/*
2179 	 * On gen2 planes are double buffered but the pipe isn't, so we must
2180 	 * wait for planes to fully turn off before disabling the pipe.
2181 	 */
2182 	if (DISPLAY_VER(dev_priv) == 2)
2183 		intel_crtc_wait_for_next_vblank(crtc);
2184 
2185 	intel_encoders_disable(state, crtc);
2186 
2187 	intel_crtc_vblank_off(old_crtc_state);
2188 
2189 	intel_disable_transcoder(old_crtc_state);
2190 
2191 	i9xx_pfit_disable(old_crtc_state);
2192 
2193 	intel_encoders_post_disable(state, crtc);
2194 
2195 	if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
2196 		if (IS_CHERRYVIEW(dev_priv))
2197 			chv_disable_pll(dev_priv, pipe);
2198 		else if (IS_VALLEYVIEW(dev_priv))
2199 			vlv_disable_pll(dev_priv, pipe);
2200 		else
2201 			i9xx_disable_pll(old_crtc_state);
2202 	}
2203 
2204 	intel_encoders_post_pll_disable(state, crtc);
2205 
2206 	if (DISPLAY_VER(dev_priv) != 2)
2207 		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
2208 
2209 	if (!dev_priv->display.funcs.wm->initial_watermarks)
2210 		intel_update_watermarks(dev_priv);
2211 
2212 	/* clock the pipe down to 640x480@60 to potentially save power */
2213 	if (IS_I830(dev_priv))
2214 		i830_enable_pipe(dev_priv, pipe);
2215 }
2216 
2217 
2218 /*
2219  * turn all crtc's off, but do not adjust state
2220  * This has to be paired with a call to intel_modeset_setup_hw_state.
2221  */
2222 int intel_display_suspend(struct drm_device *dev)
2223 {
2224 	struct drm_i915_private *dev_priv = to_i915(dev);
2225 	struct drm_atomic_state *state;
2226 	int ret;
2227 
2228 	if (!HAS_DISPLAY(dev_priv))
2229 		return 0;
2230 
2231 	state = drm_atomic_helper_suspend(dev);
2232 	ret = PTR_ERR_OR_ZERO(state);
2233 	if (ret)
2234 		drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
2235 			ret);
2236 	else
2237 		dev_priv->display.restore.modeset_state = state;
2238 	return ret;
2239 }
2240 
2241 void intel_encoder_destroy(struct drm_encoder *encoder)
2242 {
2243 	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2244 
2245 	drm_encoder_cleanup(encoder);
2246 	kfree(intel_encoder);
2247 }
2248 
2249 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
2250 {
2251 	const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2252 
2253 	/* GDG double wide on either pipe, otherwise pipe A only */
2254 	return DISPLAY_VER(dev_priv) < 4 &&
2255 		(crtc->pipe == PIPE_A || IS_I915G(dev_priv));
2256 }
2257 
2258 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
2259 {
2260 	u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
2261 	struct drm_rect src;
2262 
2263 	/*
2264 	 * We only use IF-ID interlacing. If we ever use
2265 	 * PF-ID we'll need to adjust the pixel_rate here.
2266 	 */
2267 
2268 	if (!crtc_state->pch_pfit.enabled)
2269 		return pixel_rate;
2270 
2271 	drm_rect_init(&src, 0, 0,
2272 		      drm_rect_width(&crtc_state->pipe_src) << 16,
2273 		      drm_rect_height(&crtc_state->pipe_src) << 16);
2274 
2275 	return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst,
2276 				   pixel_rate);
2277 }
2278 
2279 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode,
2280 					 const struct drm_display_mode *timings)
2281 {
2282 	mode->hdisplay = timings->crtc_hdisplay;
2283 	mode->htotal = timings->crtc_htotal;
2284 	mode->hsync_start = timings->crtc_hsync_start;
2285 	mode->hsync_end = timings->crtc_hsync_end;
2286 
2287 	mode->vdisplay = timings->crtc_vdisplay;
2288 	mode->vtotal = timings->crtc_vtotal;
2289 	mode->vsync_start = timings->crtc_vsync_start;
2290 	mode->vsync_end = timings->crtc_vsync_end;
2291 
2292 	mode->flags = timings->flags;
2293 	mode->type = DRM_MODE_TYPE_DRIVER;
2294 
2295 	mode->clock = timings->crtc_clock;
2296 
2297 	drm_mode_set_name(mode);
2298 }
2299 
2300 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
2301 {
2302 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2303 
2304 	if (HAS_GMCH(dev_priv))
2305 		/* FIXME calculate proper pipe pixel rate for GMCH pfit */
2306 		crtc_state->pixel_rate =
2307 			crtc_state->hw.pipe_mode.crtc_clock;
2308 	else
2309 		crtc_state->pixel_rate =
2310 			ilk_pipe_pixel_rate(crtc_state);
2311 }
2312 
2313 static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state *crtc_state,
2314 					   struct drm_display_mode *mode)
2315 {
2316 	int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
2317 
2318 	if (num_pipes < 2)
2319 		return;
2320 
2321 	mode->crtc_clock /= num_pipes;
2322 	mode->crtc_hdisplay /= num_pipes;
2323 	mode->crtc_hblank_start /= num_pipes;
2324 	mode->crtc_hblank_end /= num_pipes;
2325 	mode->crtc_hsync_start /= num_pipes;
2326 	mode->crtc_hsync_end /= num_pipes;
2327 	mode->crtc_htotal /= num_pipes;
2328 }
2329 
2330 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state,
2331 					  struct drm_display_mode *mode)
2332 {
2333 	int overlap = crtc_state->splitter.pixel_overlap;
2334 	int n = crtc_state->splitter.link_count;
2335 
2336 	if (!crtc_state->splitter.enable)
2337 		return;
2338 
2339 	/*
2340 	 * eDP MSO uses segment timings from EDID for transcoder
2341 	 * timings, but full mode for everything else.
2342 	 *
2343 	 * h_full = (h_segment - pixel_overlap) * link_count
2344 	 */
2345 	mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n;
2346 	mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n;
2347 	mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n;
2348 	mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n;
2349 	mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n;
2350 	mode->crtc_htotal = (mode->crtc_htotal - overlap) * n;
2351 	mode->crtc_clock *= n;
2352 }
2353 
2354 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state)
2355 {
2356 	struct drm_display_mode *mode = &crtc_state->hw.mode;
2357 	struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2358 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2359 
2360 	/*
2361 	 * Start with the adjusted_mode crtc timings, which
2362 	 * have been filled with the transcoder timings.
2363 	 */
2364 	drm_mode_copy(pipe_mode, adjusted_mode);
2365 
2366 	/* Expand MSO per-segment transcoder timings to full */
2367 	intel_splitter_adjust_timings(crtc_state, pipe_mode);
2368 
2369 	/*
2370 	 * We want the full numbers in adjusted_mode normal timings,
2371 	 * adjusted_mode crtc timings are left with the raw transcoder
2372 	 * timings.
2373 	 */
2374 	intel_mode_from_crtc_timings(adjusted_mode, pipe_mode);
2375 
2376 	/* Populate the "user" mode with full numbers */
2377 	drm_mode_copy(mode, pipe_mode);
2378 	intel_mode_from_crtc_timings(mode, mode);
2379 	mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) *
2380 		(intel_bigjoiner_num_pipes(crtc_state) ?: 1);
2381 	mode->vdisplay = drm_rect_height(&crtc_state->pipe_src);
2382 
2383 	/* Derive per-pipe timings in case bigjoiner is used */
2384 	intel_bigjoiner_adjust_timings(crtc_state, pipe_mode);
2385 	intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
2386 
2387 	intel_crtc_compute_pixel_rate(crtc_state);
2388 }
2389 
2390 void intel_encoder_get_config(struct intel_encoder *encoder,
2391 			      struct intel_crtc_state *crtc_state)
2392 {
2393 	encoder->get_config(encoder, crtc_state);
2394 
2395 	intel_crtc_readout_derived_state(crtc_state);
2396 }
2397 
2398 static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state *crtc_state)
2399 {
2400 	int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
2401 	int width, height;
2402 
2403 	if (num_pipes < 2)
2404 		return;
2405 
2406 	width = drm_rect_width(&crtc_state->pipe_src);
2407 	height = drm_rect_height(&crtc_state->pipe_src);
2408 
2409 	drm_rect_init(&crtc_state->pipe_src, 0, 0,
2410 		      width / num_pipes, height);
2411 }
2412 
2413 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state)
2414 {
2415 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2416 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2417 
2418 	intel_bigjoiner_compute_pipe_src(crtc_state);
2419 
2420 	/*
2421 	 * Pipe horizontal size must be even in:
2422 	 * - DVO ganged mode
2423 	 * - LVDS dual channel mode
2424 	 * - Double wide pipe
2425 	 */
2426 	if (drm_rect_width(&crtc_state->pipe_src) & 1) {
2427 		if (crtc_state->double_wide) {
2428 			drm_dbg_kms(&i915->drm,
2429 				    "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n",
2430 				    crtc->base.base.id, crtc->base.name);
2431 			return -EINVAL;
2432 		}
2433 
2434 		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
2435 		    intel_is_dual_link_lvds(i915)) {
2436 			drm_dbg_kms(&i915->drm,
2437 				    "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n",
2438 				    crtc->base.base.id, crtc->base.name);
2439 			return -EINVAL;
2440 		}
2441 	}
2442 
2443 	return 0;
2444 }
2445 
2446 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state)
2447 {
2448 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2449 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2450 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2451 	struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2452 	int clock_limit = i915->max_dotclk_freq;
2453 
2454 	/*
2455 	 * Start with the adjusted_mode crtc timings, which
2456 	 * have been filled with the transcoder timings.
2457 	 */
2458 	drm_mode_copy(pipe_mode, adjusted_mode);
2459 
2460 	/* Expand MSO per-segment transcoder timings to full */
2461 	intel_splitter_adjust_timings(crtc_state, pipe_mode);
2462 
2463 	/* Derive per-pipe timings in case bigjoiner is used */
2464 	intel_bigjoiner_adjust_timings(crtc_state, pipe_mode);
2465 	intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
2466 
2467 	if (DISPLAY_VER(i915) < 4) {
2468 		clock_limit = i915->display.cdclk.max_cdclk_freq * 9 / 10;
2469 
2470 		/*
2471 		 * Enable double wide mode when the dot clock
2472 		 * is > 90% of the (display) core speed.
2473 		 */
2474 		if (intel_crtc_supports_double_wide(crtc) &&
2475 		    pipe_mode->crtc_clock > clock_limit) {
2476 			clock_limit = i915->max_dotclk_freq;
2477 			crtc_state->double_wide = true;
2478 		}
2479 	}
2480 
2481 	if (pipe_mode->crtc_clock > clock_limit) {
2482 		drm_dbg_kms(&i915->drm,
2483 			    "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
2484 			    crtc->base.base.id, crtc->base.name,
2485 			    pipe_mode->crtc_clock, clock_limit,
2486 			    str_yes_no(crtc_state->double_wide));
2487 		return -EINVAL;
2488 	}
2489 
2490 	return 0;
2491 }
2492 
2493 static int intel_crtc_compute_config(struct intel_atomic_state *state,
2494 				     struct intel_crtc *crtc)
2495 {
2496 	struct intel_crtc_state *crtc_state =
2497 		intel_atomic_get_new_crtc_state(state, crtc);
2498 	int ret;
2499 
2500 	ret = intel_dpll_crtc_compute_clock(state, crtc);
2501 	if (ret)
2502 		return ret;
2503 
2504 	ret = intel_crtc_compute_pipe_src(crtc_state);
2505 	if (ret)
2506 		return ret;
2507 
2508 	ret = intel_crtc_compute_pipe_mode(crtc_state);
2509 	if (ret)
2510 		return ret;
2511 
2512 	intel_crtc_compute_pixel_rate(crtc_state);
2513 
2514 	if (crtc_state->has_pch_encoder)
2515 		return ilk_fdi_compute_config(crtc, crtc_state);
2516 
2517 	return 0;
2518 }
2519 
2520 static void
2521 intel_reduce_m_n_ratio(u32 *num, u32 *den)
2522 {
2523 	while (*num > DATA_LINK_M_N_MASK ||
2524 	       *den > DATA_LINK_M_N_MASK) {
2525 		*num >>= 1;
2526 		*den >>= 1;
2527 	}
2528 }
2529 
2530 static void compute_m_n(u32 *ret_m, u32 *ret_n,
2531 			u32 m, u32 n, u32 constant_n)
2532 {
2533 	if (constant_n)
2534 		*ret_n = constant_n;
2535 	else
2536 		*ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
2537 
2538 	*ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
2539 	intel_reduce_m_n_ratio(ret_m, ret_n);
2540 }
2541 
2542 void
2543 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
2544 		       int pixel_clock, int link_clock,
2545 		       struct intel_link_m_n *m_n,
2546 		       bool fec_enable)
2547 {
2548 	u32 data_clock = bits_per_pixel * pixel_clock;
2549 
2550 	if (fec_enable)
2551 		data_clock = intel_dp_mode_to_fec_clock(data_clock);
2552 
2553 	/*
2554 	 * Windows/BIOS uses fixed M/N values always. Follow suit.
2555 	 *
2556 	 * Also several DP dongles in particular seem to be fussy
2557 	 * about too large link M/N values. Presumably the 20bit
2558 	 * value used by Windows/BIOS is acceptable to everyone.
2559 	 */
2560 	m_n->tu = 64;
2561 	compute_m_n(&m_n->data_m, &m_n->data_n,
2562 		    data_clock, link_clock * nlanes * 8,
2563 		    0x8000000);
2564 
2565 	compute_m_n(&m_n->link_m, &m_n->link_n,
2566 		    pixel_clock, link_clock,
2567 		    0x80000);
2568 }
2569 
2570 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
2571 {
2572 	/*
2573 	 * There may be no VBT; and if the BIOS enabled SSC we can
2574 	 * just keep using it to avoid unnecessary flicker.  Whereas if the
2575 	 * BIOS isn't using it, don't assume it will work even if the VBT
2576 	 * indicates as much.
2577 	 */
2578 	if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
2579 		bool bios_lvds_use_ssc = intel_de_read(dev_priv,
2580 						       PCH_DREF_CONTROL) &
2581 			DREF_SSC1_ENABLE;
2582 
2583 		if (dev_priv->display.vbt.lvds_use_ssc != bios_lvds_use_ssc) {
2584 			drm_dbg_kms(&dev_priv->drm,
2585 				    "SSC %s by BIOS, overriding VBT which says %s\n",
2586 				    str_enabled_disabled(bios_lvds_use_ssc),
2587 				    str_enabled_disabled(dev_priv->display.vbt.lvds_use_ssc));
2588 			dev_priv->display.vbt.lvds_use_ssc = bios_lvds_use_ssc;
2589 		}
2590 	}
2591 }
2592 
2593 void intel_zero_m_n(struct intel_link_m_n *m_n)
2594 {
2595 	/* corresponds to 0 register value */
2596 	memset(m_n, 0, sizeof(*m_n));
2597 	m_n->tu = 1;
2598 }
2599 
2600 void intel_set_m_n(struct drm_i915_private *i915,
2601 		   const struct intel_link_m_n *m_n,
2602 		   i915_reg_t data_m_reg, i915_reg_t data_n_reg,
2603 		   i915_reg_t link_m_reg, i915_reg_t link_n_reg)
2604 {
2605 	intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
2606 	intel_de_write(i915, data_n_reg, m_n->data_n);
2607 	intel_de_write(i915, link_m_reg, m_n->link_m);
2608 	/*
2609 	 * On BDW+ writing LINK_N arms the double buffered update
2610 	 * of all the M/N registers, so it must be written last.
2611 	 */
2612 	intel_de_write(i915, link_n_reg, m_n->link_n);
2613 }
2614 
2615 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
2616 				    enum transcoder transcoder)
2617 {
2618 	if (IS_HASWELL(dev_priv))
2619 		return transcoder == TRANSCODER_EDP;
2620 
2621 	return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv);
2622 }
2623 
2624 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
2625 				    enum transcoder transcoder,
2626 				    const struct intel_link_m_n *m_n)
2627 {
2628 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2629 	enum pipe pipe = crtc->pipe;
2630 
2631 	if (DISPLAY_VER(dev_priv) >= 5)
2632 		intel_set_m_n(dev_priv, m_n,
2633 			      PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
2634 			      PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
2635 	else
2636 		intel_set_m_n(dev_priv, m_n,
2637 			      PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
2638 			      PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
2639 }
2640 
2641 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
2642 				    enum transcoder transcoder,
2643 				    const struct intel_link_m_n *m_n)
2644 {
2645 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2646 
2647 	if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder))
2648 		return;
2649 
2650 	intel_set_m_n(dev_priv, m_n,
2651 		      PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
2652 		      PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
2653 }
2654 
2655 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
2656 {
2657 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2658 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2659 	enum pipe pipe = crtc->pipe;
2660 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2661 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2662 	u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
2663 	int vsyncshift = 0;
2664 
2665 	/* We need to be careful not to changed the adjusted mode, for otherwise
2666 	 * the hw state checker will get angry at the mismatch. */
2667 	crtc_vdisplay = adjusted_mode->crtc_vdisplay;
2668 	crtc_vtotal = adjusted_mode->crtc_vtotal;
2669 	crtc_vblank_start = adjusted_mode->crtc_vblank_start;
2670 	crtc_vblank_end = adjusted_mode->crtc_vblank_end;
2671 
2672 	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
2673 		/* the chip adds 2 halflines automatically */
2674 		crtc_vtotal -= 1;
2675 		crtc_vblank_end -= 1;
2676 
2677 		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
2678 			vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
2679 		else
2680 			vsyncshift = adjusted_mode->crtc_hsync_start -
2681 				adjusted_mode->crtc_htotal / 2;
2682 		if (vsyncshift < 0)
2683 			vsyncshift += adjusted_mode->crtc_htotal;
2684 	}
2685 
2686 	/*
2687 	 * VBLANK_START no longer works on ADL+, instead we must use
2688 	 * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start.
2689 	 */
2690 	if (DISPLAY_VER(dev_priv) >= 13) {
2691 		intel_de_write(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder),
2692 			       crtc_vblank_start - crtc_vdisplay);
2693 
2694 		/*
2695 		 * VBLANK_START not used by hw, just clear it
2696 		 * to make it stand out in register dumps.
2697 		 */
2698 		crtc_vblank_start = 1;
2699 	}
2700 
2701 	if (DISPLAY_VER(dev_priv) > 3)
2702 		intel_de_write(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder),
2703 			       vsyncshift);
2704 
2705 	intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder),
2706 		       HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
2707 		       HTOTAL(adjusted_mode->crtc_htotal - 1));
2708 	intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
2709 		       HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
2710 		       HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
2711 	intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
2712 		       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
2713 		       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
2714 
2715 	intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
2716 		       VACTIVE(crtc_vdisplay - 1) |
2717 		       VTOTAL(crtc_vtotal - 1));
2718 	intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
2719 		       VBLANK_START(crtc_vblank_start - 1) |
2720 		       VBLANK_END(crtc_vblank_end - 1));
2721 	intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
2722 		       VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
2723 		       VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
2724 
2725 	/* Workaround: when the EDP input selection is B, the VTOTAL_B must be
2726 	 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
2727 	 * documented on the DDI_FUNC_CTL register description, EDP Input Select
2728 	 * bits. */
2729 	if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
2730 	    (pipe == PIPE_B || pipe == PIPE_C))
2731 		intel_de_write(dev_priv, TRANS_VTOTAL(pipe),
2732 			       VACTIVE(crtc_vdisplay - 1) |
2733 			       VTOTAL(crtc_vtotal - 1));
2734 }
2735 
2736 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
2737 {
2738 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2739 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2740 	int width = drm_rect_width(&crtc_state->pipe_src);
2741 	int height = drm_rect_height(&crtc_state->pipe_src);
2742 	enum pipe pipe = crtc->pipe;
2743 
2744 	/* pipesrc controls the size that is scaled from, which should
2745 	 * always be the user's requested size.
2746 	 */
2747 	intel_de_write(dev_priv, PIPESRC(pipe),
2748 		       PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));
2749 }
2750 
2751 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
2752 {
2753 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2754 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2755 
2756 	if (DISPLAY_VER(dev_priv) == 2)
2757 		return false;
2758 
2759 	if (DISPLAY_VER(dev_priv) >= 9 ||
2760 	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2761 		return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW;
2762 	else
2763 		return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK;
2764 }
2765 
2766 static void intel_get_transcoder_timings(struct intel_crtc *crtc,
2767 					 struct intel_crtc_state *pipe_config)
2768 {
2769 	struct drm_device *dev = crtc->base.dev;
2770 	struct drm_i915_private *dev_priv = to_i915(dev);
2771 	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2772 	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2773 	u32 tmp;
2774 
2775 	tmp = intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder));
2776 	adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1;
2777 	adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;
2778 
2779 	if (!transcoder_is_dsi(cpu_transcoder)) {
2780 		tmp = intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder));
2781 		adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1;
2782 		adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1;
2783 	}
2784 
2785 	tmp = intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder));
2786 	adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1;
2787 	adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;
2788 
2789 	tmp = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));
2790 	adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;
2791 	adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;
2792 
2793 	/* FIXME TGL+ DSI transcoders have this! */
2794 	if (!transcoder_is_dsi(cpu_transcoder)) {
2795 		tmp = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
2796 		adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1;
2797 		adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1;
2798 	}
2799 	tmp = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder));
2800 	adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1;
2801 	adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1;
2802 
2803 	if (intel_pipe_is_interlaced(pipe_config)) {
2804 		adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE;
2805 		adjusted_mode->crtc_vtotal += 1;
2806 		adjusted_mode->crtc_vblank_end += 1;
2807 	}
2808 
2809 	if (DISPLAY_VER(dev_priv) >= 13 && !transcoder_is_dsi(cpu_transcoder))
2810 		adjusted_mode->crtc_vblank_start =
2811 			adjusted_mode->crtc_vdisplay +
2812 			intel_de_read(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder));
2813 }
2814 
2815 static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state)
2816 {
2817 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2818 	int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
2819 	enum pipe master_pipe, pipe = crtc->pipe;
2820 	int width;
2821 
2822 	if (num_pipes < 2)
2823 		return;
2824 
2825 	master_pipe = bigjoiner_master_pipe(crtc_state);
2826 	width = drm_rect_width(&crtc_state->pipe_src);
2827 
2828 	drm_rect_translate_to(&crtc_state->pipe_src,
2829 			      (pipe - master_pipe) * width, 0);
2830 }
2831 
2832 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
2833 				    struct intel_crtc_state *pipe_config)
2834 {
2835 	struct drm_device *dev = crtc->base.dev;
2836 	struct drm_i915_private *dev_priv = to_i915(dev);
2837 	u32 tmp;
2838 
2839 	tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
2840 
2841 	drm_rect_init(&pipe_config->pipe_src, 0, 0,
2842 		      REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1,
2843 		      REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1);
2844 
2845 	intel_bigjoiner_adjust_pipe_src(pipe_config);
2846 }
2847 
2848 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
2849 {
2850 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2851 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2852 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2853 	u32 val = 0;
2854 
2855 	/*
2856 	 * - We keep both pipes enabled on 830
2857 	 * - During modeset the pipe is still disabled and must remain so
2858 	 * - During fastset the pipe is already enabled and must remain so
2859 	 */
2860 	if (IS_I830(dev_priv) || !intel_crtc_needs_modeset(crtc_state))
2861 		val |= TRANSCONF_ENABLE;
2862 
2863 	if (crtc_state->double_wide)
2864 		val |= TRANSCONF_DOUBLE_WIDE;
2865 
2866 	/* only g4x and later have fancy bpc/dither controls */
2867 	if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
2868 	    IS_CHERRYVIEW(dev_priv)) {
2869 		/* Bspec claims that we can't use dithering for 30bpp pipes. */
2870 		if (crtc_state->dither && crtc_state->pipe_bpp != 30)
2871 			val |= TRANSCONF_DITHER_EN |
2872 				TRANSCONF_DITHER_TYPE_SP;
2873 
2874 		switch (crtc_state->pipe_bpp) {
2875 		default:
2876 			/* Case prevented by intel_choose_pipe_bpp_dither. */
2877 			MISSING_CASE(crtc_state->pipe_bpp);
2878 			fallthrough;
2879 		case 18:
2880 			val |= TRANSCONF_BPC_6;
2881 			break;
2882 		case 24:
2883 			val |= TRANSCONF_BPC_8;
2884 			break;
2885 		case 30:
2886 			val |= TRANSCONF_BPC_10;
2887 			break;
2888 		}
2889 	}
2890 
2891 	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
2892 		if (DISPLAY_VER(dev_priv) < 4 ||
2893 		    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
2894 			val |= TRANSCONF_INTERLACE_W_FIELD_INDICATION;
2895 		else
2896 			val |= TRANSCONF_INTERLACE_W_SYNC_SHIFT;
2897 	} else {
2898 		val |= TRANSCONF_INTERLACE_PROGRESSIVE;
2899 	}
2900 
2901 	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
2902 	     crtc_state->limited_color_range)
2903 		val |= TRANSCONF_COLOR_RANGE_SELECT;
2904 
2905 	val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
2906 
2907 	val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
2908 
2909 	intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
2910 	intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
2911 }
2912 
2913 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
2914 {
2915 	if (IS_I830(dev_priv))
2916 		return false;
2917 
2918 	return DISPLAY_VER(dev_priv) >= 4 ||
2919 		IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
2920 }
2921 
2922 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
2923 {
2924 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2925 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2926 	u32 tmp;
2927 
2928 	if (!i9xx_has_pfit(dev_priv))
2929 		return;
2930 
2931 	tmp = intel_de_read(dev_priv, PFIT_CONTROL);
2932 	if (!(tmp & PFIT_ENABLE))
2933 		return;
2934 
2935 	/* Check whether the pfit is attached to our pipe. */
2936 	if (DISPLAY_VER(dev_priv) < 4) {
2937 		if (crtc->pipe != PIPE_B)
2938 			return;
2939 	} else {
2940 		if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
2941 			return;
2942 	}
2943 
2944 	crtc_state->gmch_pfit.control = tmp;
2945 	crtc_state->gmch_pfit.pgm_ratios =
2946 		intel_de_read(dev_priv, PFIT_PGM_RATIOS);
2947 }
2948 
2949 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
2950 			       struct intel_crtc_state *pipe_config)
2951 {
2952 	struct drm_device *dev = crtc->base.dev;
2953 	struct drm_i915_private *dev_priv = to_i915(dev);
2954 	enum pipe pipe = crtc->pipe;
2955 	struct dpll clock;
2956 	u32 mdiv;
2957 	int refclk = 100000;
2958 
2959 	/* In case of DSI, DPLL will not be used */
2960 	if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
2961 		return;
2962 
2963 	vlv_dpio_get(dev_priv);
2964 	mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
2965 	vlv_dpio_put(dev_priv);
2966 
2967 	clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
2968 	clock.m2 = mdiv & DPIO_M2DIV_MASK;
2969 	clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
2970 	clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
2971 	clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
2972 
2973 	pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
2974 }
2975 
2976 static void chv_crtc_clock_get(struct intel_crtc *crtc,
2977 			       struct intel_crtc_state *pipe_config)
2978 {
2979 	struct drm_device *dev = crtc->base.dev;
2980 	struct drm_i915_private *dev_priv = to_i915(dev);
2981 	enum pipe pipe = crtc->pipe;
2982 	enum dpio_channel port = vlv_pipe_to_channel(pipe);
2983 	struct dpll clock;
2984 	u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
2985 	int refclk = 100000;
2986 
2987 	/* In case of DSI, DPLL will not be used */
2988 	if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
2989 		return;
2990 
2991 	vlv_dpio_get(dev_priv);
2992 	cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
2993 	pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
2994 	pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
2995 	pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
2996 	pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
2997 	vlv_dpio_put(dev_priv);
2998 
2999 	clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
3000 	clock.m2 = (pll_dw0 & 0xff) << 22;
3001 	if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
3002 		clock.m2 |= pll_dw2 & 0x3fffff;
3003 	clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
3004 	clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
3005 	clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
3006 
3007 	pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
3008 }
3009 
3010 static enum intel_output_format
3011 bdw_get_pipe_misc_output_format(struct intel_crtc *crtc)
3012 {
3013 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3014 	u32 tmp;
3015 
3016 	tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe));
3017 
3018 	if (tmp & PIPE_MISC_YUV420_ENABLE) {
3019 		/* We support 4:2:0 in full blend mode only */
3020 		drm_WARN_ON(&dev_priv->drm,
3021 			    (tmp & PIPE_MISC_YUV420_MODE_FULL_BLEND) == 0);
3022 
3023 		return INTEL_OUTPUT_FORMAT_YCBCR420;
3024 	} else if (tmp & PIPE_MISC_OUTPUT_COLORSPACE_YUV) {
3025 		return INTEL_OUTPUT_FORMAT_YCBCR444;
3026 	} else {
3027 		return INTEL_OUTPUT_FORMAT_RGB;
3028 	}
3029 }
3030 
3031 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
3032 {
3033 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3034 	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
3035 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3036 	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3037 	u32 tmp;
3038 
3039 	tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
3040 
3041 	if (tmp & DISP_PIPE_GAMMA_ENABLE)
3042 		crtc_state->gamma_enable = true;
3043 
3044 	if (!HAS_GMCH(dev_priv) &&
3045 	    tmp & DISP_PIPE_CSC_ENABLE)
3046 		crtc_state->csc_enable = true;
3047 }
3048 
3049 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
3050 				 struct intel_crtc_state *pipe_config)
3051 {
3052 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3053 	enum intel_display_power_domain power_domain;
3054 	intel_wakeref_t wakeref;
3055 	u32 tmp;
3056 	bool ret;
3057 
3058 	power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
3059 	wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
3060 	if (!wakeref)
3061 		return false;
3062 
3063 	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3064 	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
3065 	pipe_config->shared_dpll = NULL;
3066 
3067 	ret = false;
3068 
3069 	tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
3070 	if (!(tmp & TRANSCONF_ENABLE))
3071 		goto out;
3072 
3073 	if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
3074 	    IS_CHERRYVIEW(dev_priv)) {
3075 		switch (tmp & TRANSCONF_BPC_MASK) {
3076 		case TRANSCONF_BPC_6:
3077 			pipe_config->pipe_bpp = 18;
3078 			break;
3079 		case TRANSCONF_BPC_8:
3080 			pipe_config->pipe_bpp = 24;
3081 			break;
3082 		case TRANSCONF_BPC_10:
3083 			pipe_config->pipe_bpp = 30;
3084 			break;
3085 		default:
3086 			MISSING_CASE(tmp);
3087 			break;
3088 		}
3089 	}
3090 
3091 	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
3092 	    (tmp & TRANSCONF_COLOR_RANGE_SELECT))
3093 		pipe_config->limited_color_range = true;
3094 
3095 	pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp);
3096 
3097 	pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
3098 
3099 	if (IS_CHERRYVIEW(dev_priv))
3100 		pipe_config->cgm_mode = intel_de_read(dev_priv,
3101 						      CGM_PIPE_MODE(crtc->pipe));
3102 
3103 	i9xx_get_pipe_color_config(pipe_config);
3104 	intel_color_get_config(pipe_config);
3105 
3106 	if (DISPLAY_VER(dev_priv) < 4)
3107 		pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE;
3108 
3109 	intel_get_transcoder_timings(crtc, pipe_config);
3110 	intel_get_pipe_src_size(crtc, pipe_config);
3111 
3112 	i9xx_get_pfit_config(pipe_config);
3113 
3114 	if (DISPLAY_VER(dev_priv) >= 4) {
3115 		/* No way to read it out on pipes B and C */
3116 		if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
3117 			tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe];
3118 		else
3119 			tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
3120 		pipe_config->pixel_multiplier =
3121 			((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
3122 			 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
3123 		pipe_config->dpll_hw_state.dpll_md = tmp;
3124 	} else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
3125 		   IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
3126 		tmp = intel_de_read(dev_priv, DPLL(crtc->pipe));
3127 		pipe_config->pixel_multiplier =
3128 			((tmp & SDVO_MULTIPLIER_MASK)
3129 			 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
3130 	} else {
3131 		/* Note that on i915G/GM the pixel multiplier is in the sdvo
3132 		 * port and will be fixed up in the encoder->get_config
3133 		 * function. */
3134 		pipe_config->pixel_multiplier = 1;
3135 	}
3136 	pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv,
3137 							DPLL(crtc->pipe));
3138 	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
3139 		pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv,
3140 							       FP0(crtc->pipe));
3141 		pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv,
3142 							       FP1(crtc->pipe));
3143 	} else {
3144 		/* Mask out read-only status bits. */
3145 		pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
3146 						     DPLL_PORTC_READY_MASK |
3147 						     DPLL_PORTB_READY_MASK);
3148 	}
3149 
3150 	if (IS_CHERRYVIEW(dev_priv))
3151 		chv_crtc_clock_get(crtc, pipe_config);
3152 	else if (IS_VALLEYVIEW(dev_priv))
3153 		vlv_crtc_clock_get(crtc, pipe_config);
3154 	else
3155 		i9xx_crtc_clock_get(crtc, pipe_config);
3156 
3157 	/*
3158 	 * Normally the dotclock is filled in by the encoder .get_config()
3159 	 * but in case the pipe is enabled w/o any ports we need a sane
3160 	 * default.
3161 	 */
3162 	pipe_config->hw.adjusted_mode.crtc_clock =
3163 		pipe_config->port_clock / pipe_config->pixel_multiplier;
3164 
3165 	ret = true;
3166 
3167 out:
3168 	intel_display_power_put(dev_priv, power_domain, wakeref);
3169 
3170 	return ret;
3171 }
3172 
3173 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
3174 {
3175 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3176 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3177 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3178 	u32 val = 0;
3179 
3180 	/*
3181 	 * - During modeset the pipe is still disabled and must remain so
3182 	 * - During fastset the pipe is already enabled and must remain so
3183 	 */
3184 	if (!intel_crtc_needs_modeset(crtc_state))
3185 		val |= TRANSCONF_ENABLE;
3186 
3187 	switch (crtc_state->pipe_bpp) {
3188 	default:
3189 		/* Case prevented by intel_choose_pipe_bpp_dither. */
3190 		MISSING_CASE(crtc_state->pipe_bpp);
3191 		fallthrough;
3192 	case 18:
3193 		val |= TRANSCONF_BPC_6;
3194 		break;
3195 	case 24:
3196 		val |= TRANSCONF_BPC_8;
3197 		break;
3198 	case 30:
3199 		val |= TRANSCONF_BPC_10;
3200 		break;
3201 	case 36:
3202 		val |= TRANSCONF_BPC_12;
3203 		break;
3204 	}
3205 
3206 	if (crtc_state->dither)
3207 		val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
3208 
3209 	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3210 		val |= TRANSCONF_INTERLACE_IF_ID_ILK;
3211 	else
3212 		val |= TRANSCONF_INTERLACE_PF_PD_ILK;
3213 
3214 	/*
3215 	 * This would end up with an odd purple hue over
3216 	 * the entire display. Make sure we don't do it.
3217 	 */
3218 	drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
3219 		    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
3220 
3221 	if (crtc_state->limited_color_range &&
3222 	    !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
3223 		val |= TRANSCONF_COLOR_RANGE_SELECT;
3224 
3225 	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
3226 		val |= TRANSCONF_OUTPUT_COLORSPACE_YUV709;
3227 
3228 	val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
3229 
3230 	val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
3231 	val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay);
3232 
3233 	intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
3234 	intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
3235 }
3236 
3237 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
3238 {
3239 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3240 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3241 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3242 	u32 val = 0;
3243 
3244 	/*
3245 	 * - During modeset the pipe is still disabled and must remain so
3246 	 * - During fastset the pipe is already enabled and must remain so
3247 	 */
3248 	if (!intel_crtc_needs_modeset(crtc_state))
3249 		val |= TRANSCONF_ENABLE;
3250 
3251 	if (IS_HASWELL(dev_priv) && crtc_state->dither)
3252 		val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
3253 
3254 	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3255 		val |= TRANSCONF_INTERLACE_IF_ID_ILK;
3256 	else
3257 		val |= TRANSCONF_INTERLACE_PF_PD_ILK;
3258 
3259 	if (IS_HASWELL(dev_priv) &&
3260 	    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
3261 		val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW;
3262 
3263 	intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
3264 	intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
3265 }
3266 
3267 static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state)
3268 {
3269 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3270 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3271 	u32 val = 0;
3272 
3273 	switch (crtc_state->pipe_bpp) {
3274 	case 18:
3275 		val |= PIPE_MISC_BPC_6;
3276 		break;
3277 	case 24:
3278 		val |= PIPE_MISC_BPC_8;
3279 		break;
3280 	case 30:
3281 		val |= PIPE_MISC_BPC_10;
3282 		break;
3283 	case 36:
3284 		/* Port output 12BPC defined for ADLP+ */
3285 		if (DISPLAY_VER(dev_priv) > 12)
3286 			val |= PIPE_MISC_BPC_12_ADLP;
3287 		break;
3288 	default:
3289 		MISSING_CASE(crtc_state->pipe_bpp);
3290 		break;
3291 	}
3292 
3293 	if (crtc_state->dither)
3294 		val |= PIPE_MISC_DITHER_ENABLE | PIPE_MISC_DITHER_TYPE_SP;
3295 
3296 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
3297 	    crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
3298 		val |= PIPE_MISC_OUTPUT_COLORSPACE_YUV;
3299 
3300 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
3301 		val |= PIPE_MISC_YUV420_ENABLE |
3302 			PIPE_MISC_YUV420_MODE_FULL_BLEND;
3303 
3304 	if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state))
3305 		val |= PIPE_MISC_HDR_MODE_PRECISION;
3306 
3307 	if (DISPLAY_VER(dev_priv) >= 12)
3308 		val |= PIPE_MISC_PIXEL_ROUNDING_TRUNC;
3309 
3310 	intel_de_write(dev_priv, PIPE_MISC(crtc->pipe), val);
3311 }
3312 
3313 int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc)
3314 {
3315 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3316 	u32 tmp;
3317 
3318 	tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe));
3319 
3320 	switch (tmp & PIPE_MISC_BPC_MASK) {
3321 	case PIPE_MISC_BPC_6:
3322 		return 18;
3323 	case PIPE_MISC_BPC_8:
3324 		return 24;
3325 	case PIPE_MISC_BPC_10:
3326 		return 30;
3327 	/*
3328 	 * PORT OUTPUT 12 BPC defined for ADLP+.
3329 	 *
3330 	 * TODO:
3331 	 * For previous platforms with DSI interface, bits 5:7
3332 	 * are used for storing pipe_bpp irrespective of dithering.
3333 	 * Since the value of 12 BPC is not defined for these bits
3334 	 * on older platforms, need to find a workaround for 12 BPC
3335 	 * MIPI DSI HW readout.
3336 	 */
3337 	case PIPE_MISC_BPC_12_ADLP:
3338 		if (DISPLAY_VER(dev_priv) > 12)
3339 			return 36;
3340 		fallthrough;
3341 	default:
3342 		MISSING_CASE(tmp);
3343 		return 0;
3344 	}
3345 }
3346 
3347 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
3348 {
3349 	/*
3350 	 * Account for spread spectrum to avoid
3351 	 * oversubscribing the link. Max center spread
3352 	 * is 2.5%; use 5% for safety's sake.
3353 	 */
3354 	u32 bps = target_clock * bpp * 21 / 20;
3355 	return DIV_ROUND_UP(bps, link_bw * 8);
3356 }
3357 
3358 void intel_get_m_n(struct drm_i915_private *i915,
3359 		   struct intel_link_m_n *m_n,
3360 		   i915_reg_t data_m_reg, i915_reg_t data_n_reg,
3361 		   i915_reg_t link_m_reg, i915_reg_t link_n_reg)
3362 {
3363 	m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK;
3364 	m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK;
3365 	m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK;
3366 	m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK;
3367 	m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1;
3368 }
3369 
3370 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
3371 				    enum transcoder transcoder,
3372 				    struct intel_link_m_n *m_n)
3373 {
3374 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3375 	enum pipe pipe = crtc->pipe;
3376 
3377 	if (DISPLAY_VER(dev_priv) >= 5)
3378 		intel_get_m_n(dev_priv, m_n,
3379 			      PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
3380 			      PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
3381 	else
3382 		intel_get_m_n(dev_priv, m_n,
3383 			      PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
3384 			      PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
3385 }
3386 
3387 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
3388 				    enum transcoder transcoder,
3389 				    struct intel_link_m_n *m_n)
3390 {
3391 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3392 
3393 	if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder))
3394 		return;
3395 
3396 	intel_get_m_n(dev_priv, m_n,
3397 		      PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
3398 		      PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
3399 }
3400 
3401 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state,
3402 				  u32 pos, u32 size)
3403 {
3404 	drm_rect_init(&crtc_state->pch_pfit.dst,
3405 		      pos >> 16, pos & 0xffff,
3406 		      size >> 16, size & 0xffff);
3407 }
3408 
3409 static void skl_get_pfit_config(struct intel_crtc_state *crtc_state)
3410 {
3411 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3412 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3413 	struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
3414 	int id = -1;
3415 	int i;
3416 
3417 	/* find scaler attached to this pipe */
3418 	for (i = 0; i < crtc->num_scalers; i++) {
3419 		u32 ctl, pos, size;
3420 
3421 		ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
3422 		if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN)
3423 			continue;
3424 
3425 		id = i;
3426 		crtc_state->pch_pfit.enabled = true;
3427 
3428 		pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i));
3429 		size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));
3430 
3431 		ilk_get_pfit_pos_size(crtc_state, pos, size);
3432 
3433 		scaler_state->scalers[i].in_use = true;
3434 		break;
3435 	}
3436 
3437 	scaler_state->scaler_id = id;
3438 	if (id >= 0)
3439 		scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
3440 	else
3441 		scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
3442 }
3443 
3444 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
3445 {
3446 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3447 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3448 	u32 ctl, pos, size;
3449 
3450 	ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
3451 	if ((ctl & PF_ENABLE) == 0)
3452 		return;
3453 
3454 	crtc_state->pch_pfit.enabled = true;
3455 
3456 	pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
3457 	size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
3458 
3459 	ilk_get_pfit_pos_size(crtc_state, pos, size);
3460 
3461 	/*
3462 	 * We currently do not free assignements of panel fitters on
3463 	 * ivb/hsw (since we don't use the higher upscaling modes which
3464 	 * differentiates them) so just WARN about this case for now.
3465 	 */
3466 	drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 7 &&
3467 		    (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe));
3468 }
3469 
3470 static bool ilk_get_pipe_config(struct intel_crtc *crtc,
3471 				struct intel_crtc_state *pipe_config)
3472 {
3473 	struct drm_device *dev = crtc->base.dev;
3474 	struct drm_i915_private *dev_priv = to_i915(dev);
3475 	enum intel_display_power_domain power_domain;
3476 	intel_wakeref_t wakeref;
3477 	u32 tmp;
3478 	bool ret;
3479 
3480 	power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
3481 	wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
3482 	if (!wakeref)
3483 		return false;
3484 
3485 	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
3486 	pipe_config->shared_dpll = NULL;
3487 
3488 	ret = false;
3489 	tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
3490 	if (!(tmp & TRANSCONF_ENABLE))
3491 		goto out;
3492 
3493 	switch (tmp & TRANSCONF_BPC_MASK) {
3494 	case TRANSCONF_BPC_6:
3495 		pipe_config->pipe_bpp = 18;
3496 		break;
3497 	case TRANSCONF_BPC_8:
3498 		pipe_config->pipe_bpp = 24;
3499 		break;
3500 	case TRANSCONF_BPC_10:
3501 		pipe_config->pipe_bpp = 30;
3502 		break;
3503 	case TRANSCONF_BPC_12:
3504 		pipe_config->pipe_bpp = 36;
3505 		break;
3506 	default:
3507 		break;
3508 	}
3509 
3510 	if (tmp & TRANSCONF_COLOR_RANGE_SELECT)
3511 		pipe_config->limited_color_range = true;
3512 
3513 	switch (tmp & TRANSCONF_OUTPUT_COLORSPACE_MASK) {
3514 	case TRANSCONF_OUTPUT_COLORSPACE_YUV601:
3515 	case TRANSCONF_OUTPUT_COLORSPACE_YUV709:
3516 		pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
3517 		break;
3518 	default:
3519 		pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3520 		break;
3521 	}
3522 
3523 	pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp);
3524 
3525 	pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
3526 
3527 	pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp);
3528 
3529 	pipe_config->csc_mode = intel_de_read(dev_priv,
3530 					      PIPE_CSC_MODE(crtc->pipe));
3531 
3532 	i9xx_get_pipe_color_config(pipe_config);
3533 	intel_color_get_config(pipe_config);
3534 
3535 	pipe_config->pixel_multiplier = 1;
3536 
3537 	ilk_pch_get_config(pipe_config);
3538 
3539 	intel_get_transcoder_timings(crtc, pipe_config);
3540 	intel_get_pipe_src_size(crtc, pipe_config);
3541 
3542 	ilk_get_pfit_config(pipe_config);
3543 
3544 	ret = true;
3545 
3546 out:
3547 	intel_display_power_put(dev_priv, power_domain, wakeref);
3548 
3549 	return ret;
3550 }
3551 
3552 static u8 bigjoiner_pipes(struct drm_i915_private *i915)
3553 {
3554 	u8 pipes;
3555 
3556 	if (DISPLAY_VER(i915) >= 12)
3557 		pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D);
3558 	else if (DISPLAY_VER(i915) >= 11)
3559 		pipes = BIT(PIPE_B) | BIT(PIPE_C);
3560 	else
3561 		pipes = 0;
3562 
3563 	return pipes & RUNTIME_INFO(i915)->pipe_mask;
3564 }
3565 
3566 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv,
3567 					   enum transcoder cpu_transcoder)
3568 {
3569 	enum intel_display_power_domain power_domain;
3570 	intel_wakeref_t wakeref;
3571 	u32 tmp = 0;
3572 
3573 	power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3574 
3575 	with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref)
3576 		tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3577 
3578 	return tmp & TRANS_DDI_FUNC_ENABLE;
3579 }
3580 
3581 static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv,
3582 				    u8 *master_pipes, u8 *slave_pipes)
3583 {
3584 	struct intel_crtc *crtc;
3585 
3586 	*master_pipes = 0;
3587 	*slave_pipes = 0;
3588 
3589 	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc,
3590 					 bigjoiner_pipes(dev_priv)) {
3591 		enum intel_display_power_domain power_domain;
3592 		enum pipe pipe = crtc->pipe;
3593 		intel_wakeref_t wakeref;
3594 
3595 		power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe);
3596 		with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) {
3597 			u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));
3598 
3599 			if (!(tmp & BIG_JOINER_ENABLE))
3600 				continue;
3601 
3602 			if (tmp & MASTER_BIG_JOINER_ENABLE)
3603 				*master_pipes |= BIT(pipe);
3604 			else
3605 				*slave_pipes |= BIT(pipe);
3606 		}
3607 
3608 		if (DISPLAY_VER(dev_priv) < 13)
3609 			continue;
3610 
3611 		power_domain = POWER_DOMAIN_PIPE(pipe);
3612 		with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) {
3613 			u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));
3614 
3615 			if (tmp & UNCOMPRESSED_JOINER_MASTER)
3616 				*master_pipes |= BIT(pipe);
3617 			if (tmp & UNCOMPRESSED_JOINER_SLAVE)
3618 				*slave_pipes |= BIT(pipe);
3619 		}
3620 	}
3621 
3622 	/* Bigjoiner pipes should always be consecutive master and slave */
3623 	drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1,
3624 		 "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n",
3625 		 *master_pipes, *slave_pipes);
3626 }
3627 
3628 static enum pipe get_bigjoiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes)
3629 {
3630 	if ((slave_pipes & BIT(pipe)) == 0)
3631 		return pipe;
3632 
3633 	/* ignore everything above our pipe */
3634 	master_pipes &= ~GENMASK(7, pipe);
3635 
3636 	/* highest remaining bit should be our master pipe */
3637 	return fls(master_pipes) - 1;
3638 }
3639 
3640 static u8 get_bigjoiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes)
3641 {
3642 	enum pipe master_pipe, next_master_pipe;
3643 
3644 	master_pipe = get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes);
3645 
3646 	if ((master_pipes & BIT(master_pipe)) == 0)
3647 		return 0;
3648 
3649 	/* ignore our master pipe and everything below it */
3650 	master_pipes &= ~GENMASK(master_pipe, 0);
3651 	/* make sure a high bit is set for the ffs() */
3652 	master_pipes |= BIT(7);
3653 	/* lowest remaining bit should be the next master pipe */
3654 	next_master_pipe = ffs(master_pipes) - 1;
3655 
3656 	return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe);
3657 }
3658 
3659 static u8 hsw_panel_transcoders(struct drm_i915_private *i915)
3660 {
3661 	u8 panel_transcoder_mask = BIT(TRANSCODER_EDP);
3662 
3663 	if (DISPLAY_VER(i915) >= 11)
3664 		panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
3665 
3666 	return panel_transcoder_mask;
3667 }
3668 
3669 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc)
3670 {
3671 	struct drm_device *dev = crtc->base.dev;
3672 	struct drm_i915_private *dev_priv = to_i915(dev);
3673 	u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv);
3674 	enum transcoder cpu_transcoder;
3675 	u8 master_pipes, slave_pipes;
3676 	u8 enabled_transcoders = 0;
3677 
3678 	/*
3679 	 * XXX: Do intel_display_power_get_if_enabled before reading this (for
3680 	 * consistency and less surprising code; it's in always on power).
3681 	 */
3682 	for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder,
3683 				       panel_transcoder_mask) {
3684 		enum intel_display_power_domain power_domain;
3685 		intel_wakeref_t wakeref;
3686 		enum pipe trans_pipe;
3687 		u32 tmp = 0;
3688 
3689 		power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3690 		with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref)
3691 			tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3692 
3693 		if (!(tmp & TRANS_DDI_FUNC_ENABLE))
3694 			continue;
3695 
3696 		switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
3697 		default:
3698 			drm_WARN(dev, 1,
3699 				 "unknown pipe linked to transcoder %s\n",
3700 				 transcoder_name(cpu_transcoder));
3701 			fallthrough;
3702 		case TRANS_DDI_EDP_INPUT_A_ONOFF:
3703 		case TRANS_DDI_EDP_INPUT_A_ON:
3704 			trans_pipe = PIPE_A;
3705 			break;
3706 		case TRANS_DDI_EDP_INPUT_B_ONOFF:
3707 			trans_pipe = PIPE_B;
3708 			break;
3709 		case TRANS_DDI_EDP_INPUT_C_ONOFF:
3710 			trans_pipe = PIPE_C;
3711 			break;
3712 		case TRANS_DDI_EDP_INPUT_D_ONOFF:
3713 			trans_pipe = PIPE_D;
3714 			break;
3715 		}
3716 
3717 		if (trans_pipe == crtc->pipe)
3718 			enabled_transcoders |= BIT(cpu_transcoder);
3719 	}
3720 
3721 	/* single pipe or bigjoiner master */
3722 	cpu_transcoder = (enum transcoder) crtc->pipe;
3723 	if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder))
3724 		enabled_transcoders |= BIT(cpu_transcoder);
3725 
3726 	/* bigjoiner slave -> consider the master pipe's transcoder as well */
3727 	enabled_bigjoiner_pipes(dev_priv, &master_pipes, &slave_pipes);
3728 	if (slave_pipes & BIT(crtc->pipe)) {
3729 		cpu_transcoder = (enum transcoder)
3730 			get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes);
3731 		if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder))
3732 			enabled_transcoders |= BIT(cpu_transcoder);
3733 	}
3734 
3735 	return enabled_transcoders;
3736 }
3737 
3738 static bool has_edp_transcoders(u8 enabled_transcoders)
3739 {
3740 	return enabled_transcoders & BIT(TRANSCODER_EDP);
3741 }
3742 
3743 static bool has_dsi_transcoders(u8 enabled_transcoders)
3744 {
3745 	return enabled_transcoders & (BIT(TRANSCODER_DSI_0) |
3746 				      BIT(TRANSCODER_DSI_1));
3747 }
3748 
3749 static bool has_pipe_transcoders(u8 enabled_transcoders)
3750 {
3751 	return enabled_transcoders & ~(BIT(TRANSCODER_EDP) |
3752 				       BIT(TRANSCODER_DSI_0) |
3753 				       BIT(TRANSCODER_DSI_1));
3754 }
3755 
3756 static void assert_enabled_transcoders(struct drm_i915_private *i915,
3757 				       u8 enabled_transcoders)
3758 {
3759 	/* Only one type of transcoder please */
3760 	drm_WARN_ON(&i915->drm,
3761 		    has_edp_transcoders(enabled_transcoders) +
3762 		    has_dsi_transcoders(enabled_transcoders) +
3763 		    has_pipe_transcoders(enabled_transcoders) > 1);
3764 
3765 	/* Only DSI transcoders can be ganged */
3766 	drm_WARN_ON(&i915->drm,
3767 		    !has_dsi_transcoders(enabled_transcoders) &&
3768 		    !is_power_of_2(enabled_transcoders));
3769 }
3770 
3771 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
3772 				     struct intel_crtc_state *pipe_config,
3773 				     struct intel_display_power_domain_set *power_domain_set)
3774 {
3775 	struct drm_device *dev = crtc->base.dev;
3776 	struct drm_i915_private *dev_priv = to_i915(dev);
3777 	unsigned long enabled_transcoders;
3778 	u32 tmp;
3779 
3780 	enabled_transcoders = hsw_enabled_transcoders(crtc);
3781 	if (!enabled_transcoders)
3782 		return false;
3783 
3784 	assert_enabled_transcoders(dev_priv, enabled_transcoders);
3785 
3786 	/*
3787 	 * With the exception of DSI we should only ever have
3788 	 * a single enabled transcoder. With DSI let's just
3789 	 * pick the first one.
3790 	 */
3791 	pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1;
3792 
3793 	if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
3794 						       POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
3795 		return false;
3796 
3797 	if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) {
3798 		tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
3799 
3800 		if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF)
3801 			pipe_config->pch_pfit.force_thru = true;
3802 	}
3803 
3804 	tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
3805 
3806 	return tmp & TRANSCONF_ENABLE;
3807 }
3808 
3809 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
3810 					 struct intel_crtc_state *pipe_config,
3811 					 struct intel_display_power_domain_set *power_domain_set)
3812 {
3813 	struct drm_device *dev = crtc->base.dev;
3814 	struct drm_i915_private *dev_priv = to_i915(dev);
3815 	enum transcoder cpu_transcoder;
3816 	enum port port;
3817 	u32 tmp;
3818 
3819 	for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
3820 		if (port == PORT_A)
3821 			cpu_transcoder = TRANSCODER_DSI_A;
3822 		else
3823 			cpu_transcoder = TRANSCODER_DSI_C;
3824 
3825 		if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
3826 							       POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
3827 			continue;
3828 
3829 		/*
3830 		 * The PLL needs to be enabled with a valid divider
3831 		 * configuration, otherwise accessing DSI registers will hang
3832 		 * the machine. See BSpec North Display Engine
3833 		 * registers/MIPI[BXT]. We can break out here early, since we
3834 		 * need the same DSI PLL to be enabled for both DSI ports.
3835 		 */
3836 		if (!bxt_dsi_pll_is_enabled(dev_priv))
3837 			break;
3838 
3839 		/* XXX: this works for video mode only */
3840 		tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
3841 		if (!(tmp & DPI_ENABLE))
3842 			continue;
3843 
3844 		tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
3845 		if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
3846 			continue;
3847 
3848 		pipe_config->cpu_transcoder = cpu_transcoder;
3849 		break;
3850 	}
3851 
3852 	return transcoder_is_dsi(pipe_config->cpu_transcoder);
3853 }
3854 
3855 static void intel_bigjoiner_get_config(struct intel_crtc_state *crtc_state)
3856 {
3857 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3858 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3859 	u8 master_pipes, slave_pipes;
3860 	enum pipe pipe = crtc->pipe;
3861 
3862 	enabled_bigjoiner_pipes(i915, &master_pipes, &slave_pipes);
3863 
3864 	if (((master_pipes | slave_pipes) & BIT(pipe)) == 0)
3865 		return;
3866 
3867 	crtc_state->bigjoiner_pipes =
3868 		BIT(get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes)) |
3869 		get_bigjoiner_slave_pipes(pipe, master_pipes, slave_pipes);
3870 }
3871 
3872 static bool hsw_get_pipe_config(struct intel_crtc *crtc,
3873 				struct intel_crtc_state *pipe_config)
3874 {
3875 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3876 	bool active;
3877 	u32 tmp;
3878 
3879 	if (!intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains,
3880 						       POWER_DOMAIN_PIPE(crtc->pipe)))
3881 		return false;
3882 
3883 	pipe_config->shared_dpll = NULL;
3884 
3885 	active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains);
3886 
3887 	if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
3888 	    bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) {
3889 		drm_WARN_ON(&dev_priv->drm, active);
3890 		active = true;
3891 	}
3892 
3893 	if (!active)
3894 		goto out;
3895 
3896 	intel_dsc_get_config(pipe_config);
3897 	intel_bigjoiner_get_config(pipe_config);
3898 
3899 	if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
3900 	    DISPLAY_VER(dev_priv) >= 11)
3901 		intel_get_transcoder_timings(crtc, pipe_config);
3902 
3903 	if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder))
3904 		intel_vrr_get_config(crtc, pipe_config);
3905 
3906 	intel_get_pipe_src_size(crtc, pipe_config);
3907 
3908 	if (IS_HASWELL(dev_priv)) {
3909 		u32 tmp = intel_de_read(dev_priv,
3910 					TRANSCONF(pipe_config->cpu_transcoder));
3911 
3912 		if (tmp & TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW)
3913 			pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
3914 		else
3915 			pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3916 	} else {
3917 		pipe_config->output_format =
3918 			bdw_get_pipe_misc_output_format(crtc);
3919 	}
3920 
3921 	pipe_config->gamma_mode = intel_de_read(dev_priv,
3922 						GAMMA_MODE(crtc->pipe));
3923 
3924 	pipe_config->csc_mode = intel_de_read(dev_priv,
3925 					      PIPE_CSC_MODE(crtc->pipe));
3926 
3927 	if (DISPLAY_VER(dev_priv) >= 9) {
3928 		tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe));
3929 
3930 		if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
3931 			pipe_config->gamma_enable = true;
3932 
3933 		if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
3934 			pipe_config->csc_enable = true;
3935 	} else {
3936 		i9xx_get_pipe_color_config(pipe_config);
3937 	}
3938 
3939 	intel_color_get_config(pipe_config);
3940 
3941 	tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));
3942 	pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
3943 	if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
3944 		pipe_config->ips_linetime =
3945 			REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
3946 
3947 	if (intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains,
3948 						      POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {
3949 		if (DISPLAY_VER(dev_priv) >= 9)
3950 			skl_get_pfit_config(pipe_config);
3951 		else
3952 			ilk_get_pfit_config(pipe_config);
3953 	}
3954 
3955 	hsw_ips_get_config(pipe_config);
3956 
3957 	if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
3958 	    !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
3959 		pipe_config->pixel_multiplier =
3960 			intel_de_read(dev_priv,
3961 				      TRANS_MULT(pipe_config->cpu_transcoder)) + 1;
3962 	} else {
3963 		pipe_config->pixel_multiplier = 1;
3964 	}
3965 
3966 	if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
3967 		tmp = intel_de_read(dev_priv, DISPLAY_VER(dev_priv) >= 14 ?
3968 				    MTL_CHICKEN_TRANS(pipe_config->cpu_transcoder) :
3969 				    CHICKEN_TRANS(pipe_config->cpu_transcoder));
3970 
3971 		pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;
3972 	} else {
3973 		/* no idea if this is correct */
3974 		pipe_config->framestart_delay = 1;
3975 	}
3976 
3977 out:
3978 	intel_display_power_put_all_in_set(dev_priv, &crtc->hw_readout_power_domains);
3979 
3980 	return active;
3981 }
3982 
3983 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
3984 {
3985 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3986 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3987 
3988 	if (!i915->display.funcs.display->get_pipe_config(crtc, crtc_state))
3989 		return false;
3990 
3991 	crtc_state->hw.active = true;
3992 
3993 	intel_crtc_readout_derived_state(crtc_state);
3994 
3995 	return true;
3996 }
3997 
3998 /* VESA 640x480x72Hz mode to set on the pipe */
3999 static const struct drm_display_mode load_detect_mode = {
4000 	DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4001 		 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4002 };
4003 
4004 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
4005 					struct drm_crtc *crtc)
4006 {
4007 	struct drm_plane *plane;
4008 	struct drm_plane_state *plane_state;
4009 	int ret, i;
4010 
4011 	ret = drm_atomic_add_affected_planes(state, crtc);
4012 	if (ret)
4013 		return ret;
4014 
4015 	for_each_new_plane_in_state(state, plane, plane_state, i) {
4016 		if (plane_state->crtc != crtc)
4017 			continue;
4018 
4019 		ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
4020 		if (ret)
4021 			return ret;
4022 
4023 		drm_atomic_set_fb_for_plane(plane_state, NULL);
4024 	}
4025 
4026 	return 0;
4027 }
4028 
4029 int intel_get_load_detect_pipe(struct drm_connector *connector,
4030 			       struct intel_load_detect_pipe *old,
4031 			       struct drm_modeset_acquire_ctx *ctx)
4032 {
4033 	struct intel_encoder *encoder =
4034 		intel_attached_encoder(to_intel_connector(connector));
4035 	struct intel_crtc *possible_crtc;
4036 	struct intel_crtc *crtc = NULL;
4037 	struct drm_device *dev = encoder->base.dev;
4038 	struct drm_i915_private *dev_priv = to_i915(dev);
4039 	struct drm_mode_config *config = &dev->mode_config;
4040 	struct drm_atomic_state *state = NULL, *restore_state = NULL;
4041 	struct drm_connector_state *connector_state;
4042 	struct intel_crtc_state *crtc_state;
4043 	int ret;
4044 
4045 	drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4046 		    connector->base.id, connector->name,
4047 		    encoder->base.base.id, encoder->base.name);
4048 
4049 	old->restore_state = NULL;
4050 
4051 	drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex));
4052 
4053 	/*
4054 	 * Algorithm gets a little messy:
4055 	 *
4056 	 *   - if the connector already has an assigned crtc, use it (but make
4057 	 *     sure it's on first)
4058 	 *
4059 	 *   - try to find the first unused crtc that can drive this connector,
4060 	 *     and use that if we find one
4061 	 */
4062 
4063 	/* See if we already have a CRTC for this connector */
4064 	if (connector->state->crtc) {
4065 		crtc = to_intel_crtc(connector->state->crtc);
4066 
4067 		ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4068 		if (ret)
4069 			goto fail;
4070 
4071 		/* Make sure the crtc and connector are running */
4072 		goto found;
4073 	}
4074 
4075 	/* Find an unused one (if possible) */
4076 	for_each_intel_crtc(dev, possible_crtc) {
4077 		if (!(encoder->base.possible_crtcs &
4078 		      drm_crtc_mask(&possible_crtc->base)))
4079 			continue;
4080 
4081 		ret = drm_modeset_lock(&possible_crtc->base.mutex, ctx);
4082 		if (ret)
4083 			goto fail;
4084 
4085 		if (possible_crtc->base.state->enable) {
4086 			drm_modeset_unlock(&possible_crtc->base.mutex);
4087 			continue;
4088 		}
4089 
4090 		crtc = possible_crtc;
4091 		break;
4092 	}
4093 
4094 	/*
4095 	 * If we didn't find an unused CRTC, don't use any.
4096 	 */
4097 	if (!crtc) {
4098 		drm_dbg_kms(&dev_priv->drm,
4099 			    "no pipe available for load-detect\n");
4100 		ret = -ENODEV;
4101 		goto fail;
4102 	}
4103 
4104 found:
4105 	state = drm_atomic_state_alloc(dev);
4106 	restore_state = drm_atomic_state_alloc(dev);
4107 	if (!state || !restore_state) {
4108 		ret = -ENOMEM;
4109 		goto fail;
4110 	}
4111 
4112 	state->acquire_ctx = ctx;
4113 	restore_state->acquire_ctx = ctx;
4114 
4115 	connector_state = drm_atomic_get_connector_state(state, connector);
4116 	if (IS_ERR(connector_state)) {
4117 		ret = PTR_ERR(connector_state);
4118 		goto fail;
4119 	}
4120 
4121 	ret = drm_atomic_set_crtc_for_connector(connector_state, &crtc->base);
4122 	if (ret)
4123 		goto fail;
4124 
4125 	crtc_state = intel_atomic_get_crtc_state(state, crtc);
4126 	if (IS_ERR(crtc_state)) {
4127 		ret = PTR_ERR(crtc_state);
4128 		goto fail;
4129 	}
4130 
4131 	crtc_state->uapi.active = true;
4132 
4133 	ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi,
4134 					   &load_detect_mode);
4135 	if (ret)
4136 		goto fail;
4137 
4138 	ret = intel_modeset_disable_planes(state, &crtc->base);
4139 	if (ret)
4140 		goto fail;
4141 
4142 	ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
4143 	if (!ret)
4144 		ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, &crtc->base));
4145 	if (!ret)
4146 		ret = drm_atomic_add_affected_planes(restore_state, &crtc->base);
4147 	if (ret) {
4148 		drm_dbg_kms(&dev_priv->drm,
4149 			    "Failed to create a copy of old state to restore: %i\n",
4150 			    ret);
4151 		goto fail;
4152 	}
4153 
4154 	ret = drm_atomic_commit(state);
4155 	if (ret) {
4156 		drm_dbg_kms(&dev_priv->drm,
4157 			    "failed to set mode on load-detect pipe\n");
4158 		goto fail;
4159 	}
4160 
4161 	old->restore_state = restore_state;
4162 	drm_atomic_state_put(state);
4163 
4164 	/* let the connector get through one full cycle before testing */
4165 	intel_crtc_wait_for_next_vblank(crtc);
4166 
4167 	return true;
4168 
4169 fail:
4170 	if (state) {
4171 		drm_atomic_state_put(state);
4172 		state = NULL;
4173 	}
4174 	if (restore_state) {
4175 		drm_atomic_state_put(restore_state);
4176 		restore_state = NULL;
4177 	}
4178 
4179 	if (ret == -EDEADLK)
4180 		return ret;
4181 
4182 	return false;
4183 }
4184 
4185 void intel_release_load_detect_pipe(struct drm_connector *connector,
4186 				    struct intel_load_detect_pipe *old,
4187 				    struct drm_modeset_acquire_ctx *ctx)
4188 {
4189 	struct intel_encoder *intel_encoder =
4190 		intel_attached_encoder(to_intel_connector(connector));
4191 	struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev);
4192 	struct drm_encoder *encoder = &intel_encoder->base;
4193 	struct drm_atomic_state *state = old->restore_state;
4194 	int ret;
4195 
4196 	drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4197 		    connector->base.id, connector->name,
4198 		    encoder->base.id, encoder->name);
4199 
4200 	if (!state)
4201 		return;
4202 
4203 	ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
4204 	if (ret)
4205 		drm_dbg_kms(&i915->drm,
4206 			    "Couldn't release load detect pipe: %i\n", ret);
4207 	drm_atomic_state_put(state);
4208 }
4209 
4210 static int i9xx_pll_refclk(struct drm_device *dev,
4211 			   const struct intel_crtc_state *pipe_config)
4212 {
4213 	struct drm_i915_private *dev_priv = to_i915(dev);
4214 	u32 dpll = pipe_config->dpll_hw_state.dpll;
4215 
4216 	if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
4217 		return dev_priv->display.vbt.lvds_ssc_freq;
4218 	else if (HAS_PCH_SPLIT(dev_priv))
4219 		return 120000;
4220 	else if (DISPLAY_VER(dev_priv) != 2)
4221 		return 96000;
4222 	else
4223 		return 48000;
4224 }
4225 
4226 /* Returns the clock of the currently programmed mode of the given pipe. */
4227 void i9xx_crtc_clock_get(struct intel_crtc *crtc,
4228 			 struct intel_crtc_state *pipe_config)
4229 {
4230 	struct drm_device *dev = crtc->base.dev;
4231 	struct drm_i915_private *dev_priv = to_i915(dev);
4232 	u32 dpll = pipe_config->dpll_hw_state.dpll;
4233 	u32 fp;
4234 	struct dpll clock;
4235 	int port_clock;
4236 	int refclk = i9xx_pll_refclk(dev, pipe_config);
4237 
4238 	if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4239 		fp = pipe_config->dpll_hw_state.fp0;
4240 	else
4241 		fp = pipe_config->dpll_hw_state.fp1;
4242 
4243 	clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4244 	if (IS_PINEVIEW(dev_priv)) {
4245 		clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4246 		clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4247 	} else {
4248 		clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4249 		clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4250 	}
4251 
4252 	if (DISPLAY_VER(dev_priv) != 2) {
4253 		if (IS_PINEVIEW(dev_priv))
4254 			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4255 				DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4256 		else
4257 			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4258 			       DPLL_FPA01_P1_POST_DIV_SHIFT);
4259 
4260 		switch (dpll & DPLL_MODE_MASK) {
4261 		case DPLLB_MODE_DAC_SERIAL:
4262 			clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4263 				5 : 10;
4264 			break;
4265 		case DPLLB_MODE_LVDS:
4266 			clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4267 				7 : 14;
4268 			break;
4269 		default:
4270 			drm_dbg_kms(&dev_priv->drm,
4271 				    "Unknown DPLL mode %08x in programmed "
4272 				    "mode\n", (int)(dpll & DPLL_MODE_MASK));
4273 			return;
4274 		}
4275 
4276 		if (IS_PINEVIEW(dev_priv))
4277 			port_clock = pnv_calc_dpll_params(refclk, &clock);
4278 		else
4279 			port_clock = i9xx_calc_dpll_params(refclk, &clock);
4280 	} else {
4281 		enum pipe lvds_pipe;
4282 
4283 		if (IS_I85X(dev_priv) &&
4284 		    intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) &&
4285 		    lvds_pipe == crtc->pipe) {
4286 			u32 lvds = intel_de_read(dev_priv, LVDS);
4287 
4288 			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4289 				       DPLL_FPA01_P1_POST_DIV_SHIFT);
4290 
4291 			if (lvds & LVDS_CLKB_POWER_UP)
4292 				clock.p2 = 7;
4293 			else
4294 				clock.p2 = 14;
4295 		} else {
4296 			if (dpll & PLL_P1_DIVIDE_BY_TWO)
4297 				clock.p1 = 2;
4298 			else {
4299 				clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4300 					    DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4301 			}
4302 			if (dpll & PLL_P2_DIVIDE_BY_4)
4303 				clock.p2 = 4;
4304 			else
4305 				clock.p2 = 2;
4306 		}
4307 
4308 		port_clock = i9xx_calc_dpll_params(refclk, &clock);
4309 	}
4310 
4311 	/*
4312 	 * This value includes pixel_multiplier. We will use
4313 	 * port_clock to compute adjusted_mode.crtc_clock in the
4314 	 * encoder's get_config() function.
4315 	 */
4316 	pipe_config->port_clock = port_clock;
4317 }
4318 
4319 int intel_dotclock_calculate(int link_freq,
4320 			     const struct intel_link_m_n *m_n)
4321 {
4322 	/*
4323 	 * The calculation for the data clock is:
4324 	 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
4325 	 * But we want to avoid losing precison if possible, so:
4326 	 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
4327 	 *
4328 	 * and the link clock is simpler:
4329 	 * link_clock = (m * link_clock) / n
4330 	 */
4331 
4332 	if (!m_n->link_n)
4333 		return 0;
4334 
4335 	return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq),
4336 				m_n->link_n);
4337 }
4338 
4339 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config)
4340 {
4341 	int dotclock;
4342 
4343 	if (intel_crtc_has_dp_encoder(pipe_config))
4344 		dotclock = intel_dotclock_calculate(pipe_config->port_clock,
4345 						    &pipe_config->dp_m_n);
4346 	else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
4347 		dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24,
4348 					     pipe_config->pipe_bpp);
4349 	else
4350 		dotclock = pipe_config->port_clock;
4351 
4352 	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
4353 	    !intel_crtc_has_dp_encoder(pipe_config))
4354 		dotclock *= 2;
4355 
4356 	if (pipe_config->pixel_multiplier)
4357 		dotclock /= pipe_config->pixel_multiplier;
4358 
4359 	return dotclock;
4360 }
4361 
4362 /* Returns the currently programmed mode of the given encoder. */
4363 struct drm_display_mode *
4364 intel_encoder_current_mode(struct intel_encoder *encoder)
4365 {
4366 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4367 	struct intel_crtc_state *crtc_state;
4368 	struct drm_display_mode *mode;
4369 	struct intel_crtc *crtc;
4370 	enum pipe pipe;
4371 
4372 	if (!encoder->get_hw_state(encoder, &pipe))
4373 		return NULL;
4374 
4375 	crtc = intel_crtc_for_pipe(dev_priv, pipe);
4376 
4377 	mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4378 	if (!mode)
4379 		return NULL;
4380 
4381 	crtc_state = intel_crtc_state_alloc(crtc);
4382 	if (!crtc_state) {
4383 		kfree(mode);
4384 		return NULL;
4385 	}
4386 
4387 	if (!intel_crtc_get_pipe_config(crtc_state)) {
4388 		kfree(crtc_state);
4389 		kfree(mode);
4390 		return NULL;
4391 	}
4392 
4393 	intel_encoder_get_config(encoder, crtc_state);
4394 
4395 	intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode);
4396 
4397 	kfree(crtc_state);
4398 
4399 	return mode;
4400 }
4401 
4402 static bool encoders_cloneable(const struct intel_encoder *a,
4403 			       const struct intel_encoder *b)
4404 {
4405 	/* masks could be asymmetric, so check both ways */
4406 	return a == b || (a->cloneable & BIT(b->type) &&
4407 			  b->cloneable & BIT(a->type));
4408 }
4409 
4410 static bool check_single_encoder_cloning(struct intel_atomic_state *state,
4411 					 struct intel_crtc *crtc,
4412 					 struct intel_encoder *encoder)
4413 {
4414 	struct intel_encoder *source_encoder;
4415 	struct drm_connector *connector;
4416 	struct drm_connector_state *connector_state;
4417 	int i;
4418 
4419 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4420 		if (connector_state->crtc != &crtc->base)
4421 			continue;
4422 
4423 		source_encoder =
4424 			to_intel_encoder(connector_state->best_encoder);
4425 		if (!encoders_cloneable(encoder, source_encoder))
4426 			return false;
4427 	}
4428 
4429 	return true;
4430 }
4431 
4432 static int icl_add_linked_planes(struct intel_atomic_state *state)
4433 {
4434 	struct intel_plane *plane, *linked;
4435 	struct intel_plane_state *plane_state, *linked_plane_state;
4436 	int i;
4437 
4438 	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4439 		linked = plane_state->planar_linked_plane;
4440 
4441 		if (!linked)
4442 			continue;
4443 
4444 		linked_plane_state = intel_atomic_get_plane_state(state, linked);
4445 		if (IS_ERR(linked_plane_state))
4446 			return PTR_ERR(linked_plane_state);
4447 
4448 		drm_WARN_ON(state->base.dev,
4449 			    linked_plane_state->planar_linked_plane != plane);
4450 		drm_WARN_ON(state->base.dev,
4451 			    linked_plane_state->planar_slave == plane_state->planar_slave);
4452 	}
4453 
4454 	return 0;
4455 }
4456 
4457 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
4458 {
4459 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4460 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4461 	struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
4462 	struct intel_plane *plane, *linked;
4463 	struct intel_plane_state *plane_state;
4464 	int i;
4465 
4466 	if (DISPLAY_VER(dev_priv) < 11)
4467 		return 0;
4468 
4469 	/*
4470 	 * Destroy all old plane links and make the slave plane invisible
4471 	 * in the crtc_state->active_planes mask.
4472 	 */
4473 	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4474 		if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
4475 			continue;
4476 
4477 		plane_state->planar_linked_plane = NULL;
4478 		if (plane_state->planar_slave && !plane_state->uapi.visible) {
4479 			crtc_state->enabled_planes &= ~BIT(plane->id);
4480 			crtc_state->active_planes &= ~BIT(plane->id);
4481 			crtc_state->update_planes |= BIT(plane->id);
4482 			crtc_state->data_rate[plane->id] = 0;
4483 			crtc_state->rel_data_rate[plane->id] = 0;
4484 		}
4485 
4486 		plane_state->planar_slave = false;
4487 	}
4488 
4489 	if (!crtc_state->nv12_planes)
4490 		return 0;
4491 
4492 	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4493 		struct intel_plane_state *linked_state = NULL;
4494 
4495 		if (plane->pipe != crtc->pipe ||
4496 		    !(crtc_state->nv12_planes & BIT(plane->id)))
4497 			continue;
4498 
4499 		for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
4500 			if (!icl_is_nv12_y_plane(dev_priv, linked->id))
4501 				continue;
4502 
4503 			if (crtc_state->active_planes & BIT(linked->id))
4504 				continue;
4505 
4506 			linked_state = intel_atomic_get_plane_state(state, linked);
4507 			if (IS_ERR(linked_state))
4508 				return PTR_ERR(linked_state);
4509 
4510 			break;
4511 		}
4512 
4513 		if (!linked_state) {
4514 			drm_dbg_kms(&dev_priv->drm,
4515 				    "Need %d free Y planes for planar YUV\n",
4516 				    hweight8(crtc_state->nv12_planes));
4517 
4518 			return -EINVAL;
4519 		}
4520 
4521 		plane_state->planar_linked_plane = linked;
4522 
4523 		linked_state->planar_slave = true;
4524 		linked_state->planar_linked_plane = plane;
4525 		crtc_state->enabled_planes |= BIT(linked->id);
4526 		crtc_state->active_planes |= BIT(linked->id);
4527 		crtc_state->update_planes |= BIT(linked->id);
4528 		crtc_state->data_rate[linked->id] =
4529 			crtc_state->data_rate_y[plane->id];
4530 		crtc_state->rel_data_rate[linked->id] =
4531 			crtc_state->rel_data_rate_y[plane->id];
4532 		drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
4533 			    linked->base.name, plane->base.name);
4534 
4535 		/* Copy parameters to slave plane */
4536 		linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
4537 		linked_state->color_ctl = plane_state->color_ctl;
4538 		linked_state->view = plane_state->view;
4539 		linked_state->decrypt = plane_state->decrypt;
4540 
4541 		intel_plane_copy_hw_state(linked_state, plane_state);
4542 		linked_state->uapi.src = plane_state->uapi.src;
4543 		linked_state->uapi.dst = plane_state->uapi.dst;
4544 
4545 		if (icl_is_hdr_plane(dev_priv, plane->id)) {
4546 			if (linked->id == PLANE_SPRITE5)
4547 				plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL;
4548 			else if (linked->id == PLANE_SPRITE4)
4549 				plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL;
4550 			else if (linked->id == PLANE_SPRITE3)
4551 				plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL;
4552 			else if (linked->id == PLANE_SPRITE2)
4553 				plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL;
4554 			else
4555 				MISSING_CASE(linked->id);
4556 		}
4557 	}
4558 
4559 	return 0;
4560 }
4561 
4562 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
4563 {
4564 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
4565 	struct intel_atomic_state *state =
4566 		to_intel_atomic_state(new_crtc_state->uapi.state);
4567 	const struct intel_crtc_state *old_crtc_state =
4568 		intel_atomic_get_old_crtc_state(state, crtc);
4569 
4570 	return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
4571 }
4572 
4573 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
4574 {
4575 	const struct drm_display_mode *pipe_mode =
4576 		&crtc_state->hw.pipe_mode;
4577 	int linetime_wm;
4578 
4579 	if (!crtc_state->hw.enable)
4580 		return 0;
4581 
4582 	linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
4583 					pipe_mode->crtc_clock);
4584 
4585 	return min(linetime_wm, 0x1ff);
4586 }
4587 
4588 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
4589 			       const struct intel_cdclk_state *cdclk_state)
4590 {
4591 	const struct drm_display_mode *pipe_mode =
4592 		&crtc_state->hw.pipe_mode;
4593 	int linetime_wm;
4594 
4595 	if (!crtc_state->hw.enable)
4596 		return 0;
4597 
4598 	linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
4599 					cdclk_state->logical.cdclk);
4600 
4601 	return min(linetime_wm, 0x1ff);
4602 }
4603 
4604 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
4605 {
4606 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4607 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4608 	const struct drm_display_mode *pipe_mode =
4609 		&crtc_state->hw.pipe_mode;
4610 	int linetime_wm;
4611 
4612 	if (!crtc_state->hw.enable)
4613 		return 0;
4614 
4615 	linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8,
4616 				   crtc_state->pixel_rate);
4617 
4618 	/* Display WA #1135: BXT:ALL GLK:ALL */
4619 	if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
4620 	    skl_watermark_ipc_enabled(dev_priv))
4621 		linetime_wm /= 2;
4622 
4623 	return min(linetime_wm, 0x1ff);
4624 }
4625 
4626 static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
4627 				   struct intel_crtc *crtc)
4628 {
4629 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4630 	struct intel_crtc_state *crtc_state =
4631 		intel_atomic_get_new_crtc_state(state, crtc);
4632 	const struct intel_cdclk_state *cdclk_state;
4633 
4634 	if (DISPLAY_VER(dev_priv) >= 9)
4635 		crtc_state->linetime = skl_linetime_wm(crtc_state);
4636 	else
4637 		crtc_state->linetime = hsw_linetime_wm(crtc_state);
4638 
4639 	if (!hsw_crtc_supports_ips(crtc))
4640 		return 0;
4641 
4642 	cdclk_state = intel_atomic_get_cdclk_state(state);
4643 	if (IS_ERR(cdclk_state))
4644 		return PTR_ERR(cdclk_state);
4645 
4646 	crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
4647 						       cdclk_state);
4648 
4649 	return 0;
4650 }
4651 
4652 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
4653 				   struct intel_crtc *crtc)
4654 {
4655 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4656 	struct intel_crtc_state *crtc_state =
4657 		intel_atomic_get_new_crtc_state(state, crtc);
4658 	int ret;
4659 
4660 	if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) &&
4661 	    intel_crtc_needs_modeset(crtc_state) &&
4662 	    !crtc_state->hw.active)
4663 		crtc_state->update_wm_post = true;
4664 
4665 	if (intel_crtc_needs_modeset(crtc_state)) {
4666 		ret = intel_dpll_crtc_get_shared_dpll(state, crtc);
4667 		if (ret)
4668 			return ret;
4669 	}
4670 
4671 	/*
4672 	 * May need to update pipe gamma enable bits
4673 	 * when C8 planes are getting enabled/disabled.
4674 	 */
4675 	if (c8_planes_changed(crtc_state))
4676 		crtc_state->uapi.color_mgmt_changed = true;
4677 
4678 	if (intel_crtc_needs_color_update(crtc_state)) {
4679 		ret = intel_color_check(crtc_state);
4680 		if (ret)
4681 			return ret;
4682 	}
4683 
4684 	ret = intel_compute_pipe_wm(state, crtc);
4685 	if (ret) {
4686 		drm_dbg_kms(&dev_priv->drm,
4687 			    "Target pipe watermarks are invalid\n");
4688 		return ret;
4689 	}
4690 
4691 	/*
4692 	 * Calculate 'intermediate' watermarks that satisfy both the
4693 	 * old state and the new state.  We can program these
4694 	 * immediately.
4695 	 */
4696 	ret = intel_compute_intermediate_wm(state, crtc);
4697 	if (ret) {
4698 		drm_dbg_kms(&dev_priv->drm,
4699 			    "No valid intermediate pipe watermarks are possible\n");
4700 		return ret;
4701 	}
4702 
4703 	if (DISPLAY_VER(dev_priv) >= 9) {
4704 		if (intel_crtc_needs_modeset(crtc_state) ||
4705 		    intel_crtc_needs_fastset(crtc_state)) {
4706 			ret = skl_update_scaler_crtc(crtc_state);
4707 			if (ret)
4708 				return ret;
4709 		}
4710 
4711 		ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state);
4712 		if (ret)
4713 			return ret;
4714 	}
4715 
4716 	if (HAS_IPS(dev_priv)) {
4717 		ret = hsw_ips_compute_config(state, crtc);
4718 		if (ret)
4719 			return ret;
4720 	}
4721 
4722 	if (DISPLAY_VER(dev_priv) >= 9 ||
4723 	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
4724 		ret = hsw_compute_linetime_wm(state, crtc);
4725 		if (ret)
4726 			return ret;
4727 
4728 	}
4729 
4730 	ret = intel_psr2_sel_fetch_update(state, crtc);
4731 	if (ret)
4732 		return ret;
4733 
4734 	return 0;
4735 }
4736 
4737 static int
4738 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
4739 		      struct intel_crtc_state *crtc_state)
4740 {
4741 	struct drm_connector *connector = conn_state->connector;
4742 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
4743 	const struct drm_display_info *info = &connector->display_info;
4744 	int bpp;
4745 
4746 	switch (conn_state->max_bpc) {
4747 	case 6 ... 7:
4748 		bpp = 6 * 3;
4749 		break;
4750 	case 8 ... 9:
4751 		bpp = 8 * 3;
4752 		break;
4753 	case 10 ... 11:
4754 		bpp = 10 * 3;
4755 		break;
4756 	case 12 ... 16:
4757 		bpp = 12 * 3;
4758 		break;
4759 	default:
4760 		MISSING_CASE(conn_state->max_bpc);
4761 		return -EINVAL;
4762 	}
4763 
4764 	if (bpp < crtc_state->pipe_bpp) {
4765 		drm_dbg_kms(&i915->drm,
4766 			    "[CONNECTOR:%d:%s] Limiting display bpp to %d "
4767 			    "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n",
4768 			    connector->base.id, connector->name,
4769 			    bpp, 3 * info->bpc,
4770 			    3 * conn_state->max_requested_bpc,
4771 			    crtc_state->pipe_bpp);
4772 
4773 		crtc_state->pipe_bpp = bpp;
4774 	}
4775 
4776 	return 0;
4777 }
4778 
4779 static int
4780 compute_baseline_pipe_bpp(struct intel_atomic_state *state,
4781 			  struct intel_crtc *crtc)
4782 {
4783 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4784 	struct intel_crtc_state *crtc_state =
4785 		intel_atomic_get_new_crtc_state(state, crtc);
4786 	struct drm_connector *connector;
4787 	struct drm_connector_state *connector_state;
4788 	int bpp, i;
4789 
4790 	if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
4791 	    IS_CHERRYVIEW(dev_priv)))
4792 		bpp = 10*3;
4793 	else if (DISPLAY_VER(dev_priv) >= 5)
4794 		bpp = 12*3;
4795 	else
4796 		bpp = 8*3;
4797 
4798 	crtc_state->pipe_bpp = bpp;
4799 
4800 	/* Clamp display bpp to connector max bpp */
4801 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4802 		int ret;
4803 
4804 		if (connector_state->crtc != &crtc->base)
4805 			continue;
4806 
4807 		ret = compute_sink_pipe_bpp(connector_state, crtc_state);
4808 		if (ret)
4809 			return ret;
4810 	}
4811 
4812 	return 0;
4813 }
4814 
4815 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
4816 {
4817 	struct drm_device *dev = state->base.dev;
4818 	struct drm_connector *connector;
4819 	struct drm_connector_list_iter conn_iter;
4820 	unsigned int used_ports = 0;
4821 	unsigned int used_mst_ports = 0;
4822 	bool ret = true;
4823 
4824 	/*
4825 	 * We're going to peek into connector->state,
4826 	 * hence connection_mutex must be held.
4827 	 */
4828 	drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
4829 
4830 	/*
4831 	 * Walk the connector list instead of the encoder
4832 	 * list to detect the problem on ddi platforms
4833 	 * where there's just one encoder per digital port.
4834 	 */
4835 	drm_connector_list_iter_begin(dev, &conn_iter);
4836 	drm_for_each_connector_iter(connector, &conn_iter) {
4837 		struct drm_connector_state *connector_state;
4838 		struct intel_encoder *encoder;
4839 
4840 		connector_state =
4841 			drm_atomic_get_new_connector_state(&state->base,
4842 							   connector);
4843 		if (!connector_state)
4844 			connector_state = connector->state;
4845 
4846 		if (!connector_state->best_encoder)
4847 			continue;
4848 
4849 		encoder = to_intel_encoder(connector_state->best_encoder);
4850 
4851 		drm_WARN_ON(dev, !connector_state->crtc);
4852 
4853 		switch (encoder->type) {
4854 		case INTEL_OUTPUT_DDI:
4855 			if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev))))
4856 				break;
4857 			fallthrough;
4858 		case INTEL_OUTPUT_DP:
4859 		case INTEL_OUTPUT_HDMI:
4860 		case INTEL_OUTPUT_EDP:
4861 			/* the same port mustn't appear more than once */
4862 			if (used_ports & BIT(encoder->port))
4863 				ret = false;
4864 
4865 			used_ports |= BIT(encoder->port);
4866 			break;
4867 		case INTEL_OUTPUT_DP_MST:
4868 			used_mst_ports |=
4869 				1 << encoder->port;
4870 			break;
4871 		default:
4872 			break;
4873 		}
4874 	}
4875 	drm_connector_list_iter_end(&conn_iter);
4876 
4877 	/* can't mix MST and SST/HDMI on the same port */
4878 	if (used_ports & used_mst_ports)
4879 		return false;
4880 
4881 	return ret;
4882 }
4883 
4884 static void
4885 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
4886 					   struct intel_crtc *crtc)
4887 {
4888 	struct intel_crtc_state *crtc_state =
4889 		intel_atomic_get_new_crtc_state(state, crtc);
4890 
4891 	WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
4892 
4893 	drm_property_replace_blob(&crtc_state->hw.degamma_lut,
4894 				  crtc_state->uapi.degamma_lut);
4895 	drm_property_replace_blob(&crtc_state->hw.gamma_lut,
4896 				  crtc_state->uapi.gamma_lut);
4897 	drm_property_replace_blob(&crtc_state->hw.ctm,
4898 				  crtc_state->uapi.ctm);
4899 }
4900 
4901 static void
4902 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state,
4903 					 struct intel_crtc *crtc)
4904 {
4905 	struct intel_crtc_state *crtc_state =
4906 		intel_atomic_get_new_crtc_state(state, crtc);
4907 
4908 	WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
4909 
4910 	crtc_state->hw.enable = crtc_state->uapi.enable;
4911 	crtc_state->hw.active = crtc_state->uapi.active;
4912 	drm_mode_copy(&crtc_state->hw.mode,
4913 		      &crtc_state->uapi.mode);
4914 	drm_mode_copy(&crtc_state->hw.adjusted_mode,
4915 		      &crtc_state->uapi.adjusted_mode);
4916 	crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
4917 
4918 	intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
4919 }
4920 
4921 static void
4922 copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state,
4923 				    struct intel_crtc *slave_crtc)
4924 {
4925 	struct intel_crtc_state *slave_crtc_state =
4926 		intel_atomic_get_new_crtc_state(state, slave_crtc);
4927 	struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state);
4928 	const struct intel_crtc_state *master_crtc_state =
4929 		intel_atomic_get_new_crtc_state(state, master_crtc);
4930 
4931 	drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut,
4932 				  master_crtc_state->hw.degamma_lut);
4933 	drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut,
4934 				  master_crtc_state->hw.gamma_lut);
4935 	drm_property_replace_blob(&slave_crtc_state->hw.ctm,
4936 				  master_crtc_state->hw.ctm);
4937 
4938 	slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed;
4939 }
4940 
4941 static int
4942 copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state,
4943 				  struct intel_crtc *slave_crtc)
4944 {
4945 	struct intel_crtc_state *slave_crtc_state =
4946 		intel_atomic_get_new_crtc_state(state, slave_crtc);
4947 	struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state);
4948 	const struct intel_crtc_state *master_crtc_state =
4949 		intel_atomic_get_new_crtc_state(state, master_crtc);
4950 	struct intel_crtc_state *saved_state;
4951 
4952 	WARN_ON(master_crtc_state->bigjoiner_pipes !=
4953 		slave_crtc_state->bigjoiner_pipes);
4954 
4955 	saved_state = kmemdup(master_crtc_state, sizeof(*saved_state), GFP_KERNEL);
4956 	if (!saved_state)
4957 		return -ENOMEM;
4958 
4959 	/* preserve some things from the slave's original crtc state */
4960 	saved_state->uapi = slave_crtc_state->uapi;
4961 	saved_state->scaler_state = slave_crtc_state->scaler_state;
4962 	saved_state->shared_dpll = slave_crtc_state->shared_dpll;
4963 	saved_state->dpll_hw_state = slave_crtc_state->dpll_hw_state;
4964 	saved_state->crc_enabled = slave_crtc_state->crc_enabled;
4965 
4966 	intel_crtc_free_hw_state(slave_crtc_state);
4967 	memcpy(slave_crtc_state, saved_state, sizeof(*slave_crtc_state));
4968 	kfree(saved_state);
4969 
4970 	/* Re-init hw state */
4971 	memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw));
4972 	slave_crtc_state->hw.enable = master_crtc_state->hw.enable;
4973 	slave_crtc_state->hw.active = master_crtc_state->hw.active;
4974 	drm_mode_copy(&slave_crtc_state->hw.mode,
4975 		      &master_crtc_state->hw.mode);
4976 	drm_mode_copy(&slave_crtc_state->hw.pipe_mode,
4977 		      &master_crtc_state->hw.pipe_mode);
4978 	drm_mode_copy(&slave_crtc_state->hw.adjusted_mode,
4979 		      &master_crtc_state->hw.adjusted_mode);
4980 	slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter;
4981 
4982 	copy_bigjoiner_crtc_state_nomodeset(state, slave_crtc);
4983 
4984 	slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed;
4985 	slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed;
4986 	slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed;
4987 
4988 	WARN_ON(master_crtc_state->bigjoiner_pipes !=
4989 		slave_crtc_state->bigjoiner_pipes);
4990 
4991 	return 0;
4992 }
4993 
4994 static int
4995 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
4996 				 struct intel_crtc *crtc)
4997 {
4998 	struct intel_crtc_state *crtc_state =
4999 		intel_atomic_get_new_crtc_state(state, crtc);
5000 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5001 	struct intel_crtc_state *saved_state;
5002 
5003 	saved_state = intel_crtc_state_alloc(crtc);
5004 	if (!saved_state)
5005 		return -ENOMEM;
5006 
5007 	/* free the old crtc_state->hw members */
5008 	intel_crtc_free_hw_state(crtc_state);
5009 
5010 	/* FIXME: before the switch to atomic started, a new pipe_config was
5011 	 * kzalloc'd. Code that depends on any field being zero should be
5012 	 * fixed, so that the crtc_state can be safely duplicated. For now,
5013 	 * only fields that are know to not cause problems are preserved. */
5014 
5015 	saved_state->uapi = crtc_state->uapi;
5016 	saved_state->inherited = crtc_state->inherited;
5017 	saved_state->scaler_state = crtc_state->scaler_state;
5018 	saved_state->shared_dpll = crtc_state->shared_dpll;
5019 	saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
5020 	memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
5021 	       sizeof(saved_state->icl_port_dplls));
5022 	saved_state->crc_enabled = crtc_state->crc_enabled;
5023 	if (IS_G4X(dev_priv) ||
5024 	    IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5025 		saved_state->wm = crtc_state->wm;
5026 
5027 	memcpy(crtc_state, saved_state, sizeof(*crtc_state));
5028 	kfree(saved_state);
5029 
5030 	intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc);
5031 
5032 	return 0;
5033 }
5034 
5035 static int
5036 intel_modeset_pipe_config(struct intel_atomic_state *state,
5037 			  struct intel_crtc *crtc)
5038 {
5039 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
5040 	struct intel_crtc_state *crtc_state =
5041 		intel_atomic_get_new_crtc_state(state, crtc);
5042 	struct drm_connector *connector;
5043 	struct drm_connector_state *connector_state;
5044 	int pipe_src_w, pipe_src_h;
5045 	int base_bpp, ret, i;
5046 	bool retry = true;
5047 
5048 	crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;
5049 
5050 	crtc_state->framestart_delay = 1;
5051 
5052 	/*
5053 	 * Sanitize sync polarity flags based on requested ones. If neither
5054 	 * positive or negative polarity is requested, treat this as meaning
5055 	 * negative polarity.
5056 	 */
5057 	if (!(crtc_state->hw.adjusted_mode.flags &
5058 	      (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
5059 		crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
5060 
5061 	if (!(crtc_state->hw.adjusted_mode.flags &
5062 	      (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
5063 		crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
5064 
5065 	ret = compute_baseline_pipe_bpp(state, crtc);
5066 	if (ret)
5067 		return ret;
5068 
5069 	base_bpp = crtc_state->pipe_bpp;
5070 
5071 	/*
5072 	 * Determine the real pipe dimensions. Note that stereo modes can
5073 	 * increase the actual pipe size due to the frame doubling and
5074 	 * insertion of additional space for blanks between the frame. This
5075 	 * is stored in the crtc timings. We use the requested mode to do this
5076 	 * computation to clearly distinguish it from the adjusted mode, which
5077 	 * can be changed by the connectors in the below retry loop.
5078 	 */
5079 	drm_mode_get_hv_timing(&crtc_state->hw.mode,
5080 			       &pipe_src_w, &pipe_src_h);
5081 	drm_rect_init(&crtc_state->pipe_src, 0, 0,
5082 		      pipe_src_w, pipe_src_h);
5083 
5084 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
5085 		struct intel_encoder *encoder =
5086 			to_intel_encoder(connector_state->best_encoder);
5087 
5088 		if (connector_state->crtc != &crtc->base)
5089 			continue;
5090 
5091 		if (!check_single_encoder_cloning(state, crtc, encoder)) {
5092 			drm_dbg_kms(&i915->drm,
5093 				    "[ENCODER:%d:%s] rejecting invalid cloning configuration\n",
5094 				    encoder->base.base.id, encoder->base.name);
5095 			return -EINVAL;
5096 		}
5097 
5098 		/*
5099 		 * Determine output_types before calling the .compute_config()
5100 		 * hooks so that the hooks can use this information safely.
5101 		 */
5102 		if (encoder->compute_output_type)
5103 			crtc_state->output_types |=
5104 				BIT(encoder->compute_output_type(encoder, crtc_state,
5105 								 connector_state));
5106 		else
5107 			crtc_state->output_types |= BIT(encoder->type);
5108 	}
5109 
5110 encoder_retry:
5111 	/* Ensure the port clock defaults are reset when retrying. */
5112 	crtc_state->port_clock = 0;
5113 	crtc_state->pixel_multiplier = 1;
5114 
5115 	/* Fill in default crtc timings, allow encoders to overwrite them. */
5116 	drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode,
5117 			      CRTC_STEREO_DOUBLE);
5118 
5119 	/* Pass our mode to the connectors and the CRTC to give them a chance to
5120 	 * adjust it according to limitations or connector properties, and also
5121 	 * a chance to reject the mode entirely.
5122 	 */
5123 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
5124 		struct intel_encoder *encoder =
5125 			to_intel_encoder(connector_state->best_encoder);
5126 
5127 		if (connector_state->crtc != &crtc->base)
5128 			continue;
5129 
5130 		ret = encoder->compute_config(encoder, crtc_state,
5131 					      connector_state);
5132 		if (ret == -EDEADLK)
5133 			return ret;
5134 		if (ret < 0) {
5135 			drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n",
5136 				    encoder->base.base.id, encoder->base.name, ret);
5137 			return ret;
5138 		}
5139 	}
5140 
5141 	/* Set default port clock if not overwritten by the encoder. Needs to be
5142 	 * done afterwards in case the encoder adjusts the mode. */
5143 	if (!crtc_state->port_clock)
5144 		crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock
5145 			* crtc_state->pixel_multiplier;
5146 
5147 	ret = intel_crtc_compute_config(state, crtc);
5148 	if (ret == -EDEADLK)
5149 		return ret;
5150 	if (ret == -EAGAIN) {
5151 		if (drm_WARN(&i915->drm, !retry,
5152 			     "[CRTC:%d:%s] loop in pipe configuration computation\n",
5153 			     crtc->base.base.id, crtc->base.name))
5154 			return -EINVAL;
5155 
5156 		drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] bw constrained, retrying\n",
5157 			    crtc->base.base.id, crtc->base.name);
5158 		retry = false;
5159 		goto encoder_retry;
5160 	}
5161 	if (ret < 0) {
5162 		drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n",
5163 			    crtc->base.base.id, crtc->base.name, ret);
5164 		return ret;
5165 	}
5166 
5167 	/* Dithering seems to not pass-through bits correctly when it should, so
5168 	 * only enable it on 6bpc panels and when its not a compliance
5169 	 * test requesting 6bpc video pattern.
5170 	 */
5171 	crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&
5172 		!crtc_state->dither_force_disable;
5173 	drm_dbg_kms(&i915->drm,
5174 		    "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
5175 		    crtc->base.base.id, crtc->base.name,
5176 		    base_bpp, crtc_state->pipe_bpp, crtc_state->dither);
5177 
5178 	return 0;
5179 }
5180 
5181 static int
5182 intel_modeset_pipe_config_late(struct intel_atomic_state *state,
5183 			       struct intel_crtc *crtc)
5184 {
5185 	struct intel_crtc_state *crtc_state =
5186 		intel_atomic_get_new_crtc_state(state, crtc);
5187 	struct drm_connector_state *conn_state;
5188 	struct drm_connector *connector;
5189 	int i;
5190 
5191 	intel_bigjoiner_adjust_pipe_src(crtc_state);
5192 
5193 	for_each_new_connector_in_state(&state->base, connector,
5194 					conn_state, i) {
5195 		struct intel_encoder *encoder =
5196 			to_intel_encoder(conn_state->best_encoder);
5197 		int ret;
5198 
5199 		if (conn_state->crtc != &crtc->base ||
5200 		    !encoder->compute_config_late)
5201 			continue;
5202 
5203 		ret = encoder->compute_config_late(encoder, crtc_state,
5204 						   conn_state);
5205 		if (ret)
5206 			return ret;
5207 	}
5208 
5209 	return 0;
5210 }
5211 
5212 bool intel_fuzzy_clock_check(int clock1, int clock2)
5213 {
5214 	int diff;
5215 
5216 	if (clock1 == clock2)
5217 		return true;
5218 
5219 	if (!clock1 || !clock2)
5220 		return false;
5221 
5222 	diff = abs(clock1 - clock2);
5223 
5224 	if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
5225 		return true;
5226 
5227 	return false;
5228 }
5229 
5230 static bool
5231 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
5232 		       const struct intel_link_m_n *m2_n2)
5233 {
5234 	return m_n->tu == m2_n2->tu &&
5235 		m_n->data_m == m2_n2->data_m &&
5236 		m_n->data_n == m2_n2->data_n &&
5237 		m_n->link_m == m2_n2->link_m &&
5238 		m_n->link_n == m2_n2->link_n;
5239 }
5240 
5241 static bool
5242 intel_compare_infoframe(const union hdmi_infoframe *a,
5243 			const union hdmi_infoframe *b)
5244 {
5245 	return memcmp(a, b, sizeof(*a)) == 0;
5246 }
5247 
5248 static bool
5249 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
5250 			 const struct drm_dp_vsc_sdp *b)
5251 {
5252 	return memcmp(a, b, sizeof(*a)) == 0;
5253 }
5254 
5255 static bool
5256 intel_compare_buffer(const u8 *a, const u8 *b, size_t len)
5257 {
5258 	return memcmp(a, b, len) == 0;
5259 }
5260 
5261 static void
5262 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
5263 			       bool fastset, const char *name,
5264 			       const union hdmi_infoframe *a,
5265 			       const union hdmi_infoframe *b)
5266 {
5267 	if (fastset) {
5268 		if (!drm_debug_enabled(DRM_UT_KMS))
5269 			return;
5270 
5271 		drm_dbg_kms(&dev_priv->drm,
5272 			    "fastset mismatch in %s infoframe\n", name);
5273 		drm_dbg_kms(&dev_priv->drm, "expected:\n");
5274 		hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
5275 		drm_dbg_kms(&dev_priv->drm, "found:\n");
5276 		hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
5277 	} else {
5278 		drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name);
5279 		drm_err(&dev_priv->drm, "expected:\n");
5280 		hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
5281 		drm_err(&dev_priv->drm, "found:\n");
5282 		hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
5283 	}
5284 }
5285 
5286 static void
5287 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
5288 				bool fastset, const char *name,
5289 				const struct drm_dp_vsc_sdp *a,
5290 				const struct drm_dp_vsc_sdp *b)
5291 {
5292 	if (fastset) {
5293 		if (!drm_debug_enabled(DRM_UT_KMS))
5294 			return;
5295 
5296 		drm_dbg_kms(&dev_priv->drm,
5297 			    "fastset mismatch in %s dp sdp\n", name);
5298 		drm_dbg_kms(&dev_priv->drm, "expected:\n");
5299 		drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
5300 		drm_dbg_kms(&dev_priv->drm, "found:\n");
5301 		drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
5302 	} else {
5303 		drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name);
5304 		drm_err(&dev_priv->drm, "expected:\n");
5305 		drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
5306 		drm_err(&dev_priv->drm, "found:\n");
5307 		drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
5308 	}
5309 }
5310 
5311 /* Returns the length up to and including the last differing byte */
5312 static size_t
5313 memcmp_diff_len(const u8 *a, const u8 *b, size_t len)
5314 {
5315 	int i;
5316 
5317 	for (i = len - 1; i >= 0; i--) {
5318 		if (a[i] != b[i])
5319 			return i + 1;
5320 	}
5321 
5322 	return 0;
5323 }
5324 
5325 static void
5326 pipe_config_buffer_mismatch(struct drm_i915_private *dev_priv,
5327 			    bool fastset, const char *name,
5328 			    const u8 *a, const u8 *b, size_t len)
5329 {
5330 	if (fastset) {
5331 		if (!drm_debug_enabled(DRM_UT_KMS))
5332 			return;
5333 
5334 		/* only dump up to the last difference */
5335 		len = memcmp_diff_len(a, b, len);
5336 
5337 		drm_dbg_kms(&dev_priv->drm,
5338 			    "fastset mismatch in %s buffer\n", name);
5339 		print_hex_dump(KERN_DEBUG, "expected: ", DUMP_PREFIX_NONE,
5340 			       16, 0, a, len, false);
5341 		print_hex_dump(KERN_DEBUG, "found: ", DUMP_PREFIX_NONE,
5342 			       16, 0, b, len, false);
5343 	} else {
5344 		/* only dump up to the last difference */
5345 		len = memcmp_diff_len(a, b, len);
5346 
5347 		drm_err(&dev_priv->drm, "mismatch in %s buffer\n", name);
5348 		print_hex_dump(KERN_ERR, "expected: ", DUMP_PREFIX_NONE,
5349 			       16, 0, a, len, false);
5350 		print_hex_dump(KERN_ERR, "found: ", DUMP_PREFIX_NONE,
5351 			       16, 0, b, len, false);
5352 	}
5353 }
5354 
5355 static void __printf(4, 5)
5356 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
5357 		     const char *name, const char *format, ...)
5358 {
5359 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
5360 	struct va_format vaf;
5361 	va_list args;
5362 
5363 	va_start(args, format);
5364 	vaf.fmt = format;
5365 	vaf.va = &args;
5366 
5367 	if (fastset)
5368 		drm_dbg_kms(&i915->drm,
5369 			    "[CRTC:%d:%s] fastset mismatch in %s %pV\n",
5370 			    crtc->base.base.id, crtc->base.name, name, &vaf);
5371 	else
5372 		drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n",
5373 			crtc->base.base.id, crtc->base.name, name, &vaf);
5374 
5375 	va_end(args);
5376 }
5377 
5378 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
5379 {
5380 	if (dev_priv->params.fastboot != -1)
5381 		return dev_priv->params.fastboot;
5382 
5383 	/* Enable fastboot by default on Skylake and newer */
5384 	if (DISPLAY_VER(dev_priv) >= 9)
5385 		return true;
5386 
5387 	/* Enable fastboot by default on VLV and CHV */
5388 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5389 		return true;
5390 
5391 	/* Disabled by default on all others */
5392 	return false;
5393 }
5394 
5395 bool
5396 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
5397 			  const struct intel_crtc_state *pipe_config,
5398 			  bool fastset)
5399 {
5400 	struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
5401 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
5402 	bool ret = true;
5403 	bool fixup_inherited = fastset &&
5404 		current_config->inherited && !pipe_config->inherited;
5405 
5406 	if (fixup_inherited && !fastboot_enabled(dev_priv)) {
5407 		drm_dbg_kms(&dev_priv->drm,
5408 			    "initial modeset and fastboot not set\n");
5409 		ret = false;
5410 	}
5411 
5412 #define PIPE_CONF_CHECK_X(name) do { \
5413 	if (current_config->name != pipe_config->name) { \
5414 		pipe_config_mismatch(fastset, crtc, __stringify(name), \
5415 				     "(expected 0x%08x, found 0x%08x)", \
5416 				     current_config->name, \
5417 				     pipe_config->name); \
5418 		ret = false; \
5419 	} \
5420 } while (0)
5421 
5422 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \
5423 	if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \
5424 		pipe_config_mismatch(fastset, crtc, __stringify(name), \
5425 				     "(expected 0x%08x, found 0x%08x)", \
5426 				     current_config->name & (mask), \
5427 				     pipe_config->name & (mask)); \
5428 		ret = false; \
5429 	} \
5430 } while (0)
5431 
5432 #define PIPE_CONF_CHECK_I(name) do { \
5433 	if (current_config->name != pipe_config->name) { \
5434 		pipe_config_mismatch(fastset, crtc, __stringify(name), \
5435 				     "(expected %i, found %i)", \
5436 				     current_config->name, \
5437 				     pipe_config->name); \
5438 		ret = false; \
5439 	} \
5440 } while (0)
5441 
5442 #define PIPE_CONF_CHECK_BOOL(name) do { \
5443 	if (current_config->name != pipe_config->name) { \
5444 		pipe_config_mismatch(fastset, crtc,  __stringify(name), \
5445 				     "(expected %s, found %s)", \
5446 				     str_yes_no(current_config->name), \
5447 				     str_yes_no(pipe_config->name)); \
5448 		ret = false; \
5449 	} \
5450 } while (0)
5451 
5452 /*
5453  * Checks state where we only read out the enabling, but not the entire
5454  * state itself (like full infoframes or ELD for audio). These states
5455  * require a full modeset on bootup to fix up.
5456  */
5457 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
5458 	if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
5459 		PIPE_CONF_CHECK_BOOL(name); \
5460 	} else { \
5461 		pipe_config_mismatch(fastset, crtc, __stringify(name), \
5462 				     "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
5463 				     str_yes_no(current_config->name), \
5464 				     str_yes_no(pipe_config->name)); \
5465 		ret = false; \
5466 	} \
5467 } while (0)
5468 
5469 #define PIPE_CONF_CHECK_P(name) do { \
5470 	if (current_config->name != pipe_config->name) { \
5471 		pipe_config_mismatch(fastset, crtc, __stringify(name), \
5472 				     "(expected %p, found %p)", \
5473 				     current_config->name, \
5474 				     pipe_config->name); \
5475 		ret = false; \
5476 	} \
5477 } while (0)
5478 
5479 #define PIPE_CONF_CHECK_M_N(name) do { \
5480 	if (!intel_compare_link_m_n(&current_config->name, \
5481 				    &pipe_config->name)) { \
5482 		pipe_config_mismatch(fastset, crtc, __stringify(name), \
5483 				     "(expected tu %i data %i/%i link %i/%i, " \
5484 				     "found tu %i, data %i/%i link %i/%i)", \
5485 				     current_config->name.tu, \
5486 				     current_config->name.data_m, \
5487 				     current_config->name.data_n, \
5488 				     current_config->name.link_m, \
5489 				     current_config->name.link_n, \
5490 				     pipe_config->name.tu, \
5491 				     pipe_config->name.data_m, \
5492 				     pipe_config->name.data_n, \
5493 				     pipe_config->name.link_m, \
5494 				     pipe_config->name.link_n); \
5495 		ret = false; \
5496 	} \
5497 } while (0)
5498 
5499 #define PIPE_CONF_CHECK_TIMINGS(name) do { \
5500 	PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
5501 	PIPE_CONF_CHECK_I(name.crtc_htotal); \
5502 	PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
5503 	PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
5504 	PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
5505 	PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
5506 	PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
5507 	PIPE_CONF_CHECK_I(name.crtc_vtotal); \
5508 	PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
5509 	PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
5510 	PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
5511 	PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
5512 } while (0)
5513 
5514 #define PIPE_CONF_CHECK_RECT(name) do { \
5515 	PIPE_CONF_CHECK_I(name.x1); \
5516 	PIPE_CONF_CHECK_I(name.x2); \
5517 	PIPE_CONF_CHECK_I(name.y1); \
5518 	PIPE_CONF_CHECK_I(name.y2); \
5519 } while (0)
5520 
5521 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
5522 	if ((current_config->name ^ pipe_config->name) & (mask)) { \
5523 		pipe_config_mismatch(fastset, crtc, __stringify(name), \
5524 				     "(%x) (expected %i, found %i)", \
5525 				     (mask), \
5526 				     current_config->name & (mask), \
5527 				     pipe_config->name & (mask)); \
5528 		ret = false; \
5529 	} \
5530 } while (0)
5531 
5532 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
5533 	if (!intel_compare_infoframe(&current_config->infoframes.name, \
5534 				     &pipe_config->infoframes.name)) { \
5535 		pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
5536 					       &current_config->infoframes.name, \
5537 					       &pipe_config->infoframes.name); \
5538 		ret = false; \
5539 	} \
5540 } while (0)
5541 
5542 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
5543 	if (!current_config->has_psr && !pipe_config->has_psr && \
5544 	    !intel_compare_dp_vsc_sdp(&current_config->infoframes.name, \
5545 				      &pipe_config->infoframes.name)) { \
5546 		pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
5547 						&current_config->infoframes.name, \
5548 						&pipe_config->infoframes.name); \
5549 		ret = false; \
5550 	} \
5551 } while (0)
5552 
5553 #define PIPE_CONF_CHECK_BUFFER(name, len) do { \
5554 	BUILD_BUG_ON(sizeof(current_config->name) != (len)); \
5555 	BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \
5556 	if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \
5557 		pipe_config_buffer_mismatch(dev_priv, fastset, __stringify(name), \
5558 					    current_config->name, \
5559 					    pipe_config->name, \
5560 					    (len)); \
5561 		ret = false; \
5562 	} \
5563 } while (0)
5564 
5565 #define PIPE_CONF_CHECK_COLOR_LUT(lut, is_pre_csc_lut) do { \
5566 	if (current_config->gamma_mode == pipe_config->gamma_mode && \
5567 	    !intel_color_lut_equal(current_config, \
5568 				   current_config->lut, pipe_config->lut, \
5569 				   is_pre_csc_lut)) {	\
5570 		pipe_config_mismatch(fastset, crtc, __stringify(lut), \
5571 				     "hw_state doesn't match sw_state"); \
5572 		ret = false; \
5573 	} \
5574 } while (0)
5575 
5576 #define PIPE_CONF_QUIRK(quirk) \
5577 	((current_config->quirks | pipe_config->quirks) & (quirk))
5578 
5579 	PIPE_CONF_CHECK_I(hw.enable);
5580 	PIPE_CONF_CHECK_I(hw.active);
5581 
5582 	PIPE_CONF_CHECK_I(cpu_transcoder);
5583 	PIPE_CONF_CHECK_I(mst_master_transcoder);
5584 
5585 	PIPE_CONF_CHECK_BOOL(has_pch_encoder);
5586 	PIPE_CONF_CHECK_I(fdi_lanes);
5587 	PIPE_CONF_CHECK_M_N(fdi_m_n);
5588 
5589 	PIPE_CONF_CHECK_I(lane_count);
5590 	PIPE_CONF_CHECK_X(lane_lat_optim_mask);
5591 
5592 	if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) {
5593 		if (!fastset || !pipe_config->seamless_m_n)
5594 			PIPE_CONF_CHECK_M_N(dp_m_n);
5595 	} else {
5596 		PIPE_CONF_CHECK_M_N(dp_m_n);
5597 		PIPE_CONF_CHECK_M_N(dp_m2_n2);
5598 	}
5599 
5600 	PIPE_CONF_CHECK_X(output_types);
5601 
5602 	PIPE_CONF_CHECK_I(framestart_delay);
5603 	PIPE_CONF_CHECK_I(msa_timing_delay);
5604 
5605 	PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode);
5606 	PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode);
5607 
5608 	PIPE_CONF_CHECK_I(pixel_multiplier);
5609 
5610 	PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5611 			      DRM_MODE_FLAG_INTERLACE);
5612 
5613 	if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
5614 		PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5615 				      DRM_MODE_FLAG_PHSYNC);
5616 		PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5617 				      DRM_MODE_FLAG_NHSYNC);
5618 		PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5619 				      DRM_MODE_FLAG_PVSYNC);
5620 		PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5621 				      DRM_MODE_FLAG_NVSYNC);
5622 	}
5623 
5624 	PIPE_CONF_CHECK_I(output_format);
5625 	PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
5626 	if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
5627 	    IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5628 		PIPE_CONF_CHECK_BOOL(limited_color_range);
5629 
5630 	PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
5631 	PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
5632 	PIPE_CONF_CHECK_BOOL(has_infoframe);
5633 	PIPE_CONF_CHECK_BOOL(fec_enable);
5634 
5635 	PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
5636 	PIPE_CONF_CHECK_BUFFER(eld, MAX_ELD_BYTES);
5637 
5638 	PIPE_CONF_CHECK_X(gmch_pfit.control);
5639 	/* pfit ratios are autocomputed by the hw on gen4+ */
5640 	if (DISPLAY_VER(dev_priv) < 4)
5641 		PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
5642 	PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
5643 
5644 	/*
5645 	 * Changing the EDP transcoder input mux
5646 	 * (A_ONOFF vs. A_ON) requires a full modeset.
5647 	 */
5648 	PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
5649 
5650 	if (!fastset) {
5651 		PIPE_CONF_CHECK_RECT(pipe_src);
5652 
5653 		PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
5654 		PIPE_CONF_CHECK_RECT(pch_pfit.dst);
5655 
5656 		PIPE_CONF_CHECK_I(scaler_state.scaler_id);
5657 		PIPE_CONF_CHECK_I(pixel_rate);
5658 
5659 		PIPE_CONF_CHECK_X(gamma_mode);
5660 		if (IS_CHERRYVIEW(dev_priv))
5661 			PIPE_CONF_CHECK_X(cgm_mode);
5662 		else
5663 			PIPE_CONF_CHECK_X(csc_mode);
5664 		PIPE_CONF_CHECK_BOOL(gamma_enable);
5665 		PIPE_CONF_CHECK_BOOL(csc_enable);
5666 
5667 		PIPE_CONF_CHECK_I(linetime);
5668 		PIPE_CONF_CHECK_I(ips_linetime);
5669 
5670 		PIPE_CONF_CHECK_COLOR_LUT(pre_csc_lut, true);
5671 		PIPE_CONF_CHECK_COLOR_LUT(post_csc_lut, false);
5672 
5673 		if (current_config->active_planes) {
5674 			PIPE_CONF_CHECK_BOOL(has_psr);
5675 			PIPE_CONF_CHECK_BOOL(has_psr2);
5676 			PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
5677 			PIPE_CONF_CHECK_I(dc3co_exitline);
5678 		}
5679 	}
5680 
5681 	PIPE_CONF_CHECK_BOOL(double_wide);
5682 
5683 	if (dev_priv->display.dpll.mgr) {
5684 		PIPE_CONF_CHECK_P(shared_dpll);
5685 
5686 		PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
5687 		PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
5688 		PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
5689 		PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
5690 		PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
5691 		PIPE_CONF_CHECK_X(dpll_hw_state.spll);
5692 		PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
5693 		PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
5694 		PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
5695 		PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
5696 		PIPE_CONF_CHECK_X(dpll_hw_state.div0);
5697 		PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
5698 		PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
5699 		PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
5700 		PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
5701 		PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
5702 		PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
5703 		PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
5704 		PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
5705 		PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
5706 		PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
5707 		PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
5708 		PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
5709 		PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
5710 		PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
5711 		PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
5712 		PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
5713 		PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
5714 		PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
5715 		PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
5716 		PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
5717 		PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
5718 	}
5719 
5720 	PIPE_CONF_CHECK_X(dsi_pll.ctrl);
5721 	PIPE_CONF_CHECK_X(dsi_pll.div);
5722 
5723 	if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
5724 		PIPE_CONF_CHECK_I(pipe_bpp);
5725 
5726 	if (!fastset || !pipe_config->seamless_m_n) {
5727 		PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
5728 		PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
5729 	}
5730 	PIPE_CONF_CHECK_I(port_clock);
5731 
5732 	PIPE_CONF_CHECK_I(min_voltage_level);
5733 
5734 	if (current_config->has_psr || pipe_config->has_psr)
5735 		PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable,
5736 					    ~intel_hdmi_infoframe_enable(DP_SDP_VSC));
5737 	else
5738 		PIPE_CONF_CHECK_X(infoframes.enable);
5739 
5740 	PIPE_CONF_CHECK_X(infoframes.gcp);
5741 	PIPE_CONF_CHECK_INFOFRAME(avi);
5742 	PIPE_CONF_CHECK_INFOFRAME(spd);
5743 	PIPE_CONF_CHECK_INFOFRAME(hdmi);
5744 	PIPE_CONF_CHECK_INFOFRAME(drm);
5745 	PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
5746 
5747 	PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
5748 	PIPE_CONF_CHECK_I(master_transcoder);
5749 	PIPE_CONF_CHECK_X(bigjoiner_pipes);
5750 
5751 	PIPE_CONF_CHECK_I(dsc.compression_enable);
5752 	PIPE_CONF_CHECK_I(dsc.dsc_split);
5753 	PIPE_CONF_CHECK_I(dsc.compressed_bpp);
5754 
5755 	PIPE_CONF_CHECK_BOOL(splitter.enable);
5756 	PIPE_CONF_CHECK_I(splitter.link_count);
5757 	PIPE_CONF_CHECK_I(splitter.pixel_overlap);
5758 
5759 	PIPE_CONF_CHECK_BOOL(vrr.enable);
5760 	PIPE_CONF_CHECK_I(vrr.vmin);
5761 	PIPE_CONF_CHECK_I(vrr.vmax);
5762 	PIPE_CONF_CHECK_I(vrr.flipline);
5763 	PIPE_CONF_CHECK_I(vrr.pipeline_full);
5764 	PIPE_CONF_CHECK_I(vrr.guardband);
5765 
5766 #undef PIPE_CONF_CHECK_X
5767 #undef PIPE_CONF_CHECK_I
5768 #undef PIPE_CONF_CHECK_BOOL
5769 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
5770 #undef PIPE_CONF_CHECK_P
5771 #undef PIPE_CONF_CHECK_FLAGS
5772 #undef PIPE_CONF_CHECK_COLOR_LUT
5773 #undef PIPE_CONF_CHECK_TIMINGS
5774 #undef PIPE_CONF_CHECK_RECT
5775 #undef PIPE_CONF_QUIRK
5776 
5777 	return ret;
5778 }
5779 
5780 static void
5781 intel_verify_planes(struct intel_atomic_state *state)
5782 {
5783 	struct intel_plane *plane;
5784 	const struct intel_plane_state *plane_state;
5785 	int i;
5786 
5787 	for_each_new_intel_plane_in_state(state, plane,
5788 					  plane_state, i)
5789 		assert_plane(plane, plane_state->planar_slave ||
5790 			     plane_state->uapi.visible);
5791 }
5792 
5793 int intel_modeset_all_pipes(struct intel_atomic_state *state,
5794 			    const char *reason)
5795 {
5796 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5797 	struct intel_crtc *crtc;
5798 
5799 	/*
5800 	 * Add all pipes to the state, and force
5801 	 * a modeset on all the active ones.
5802 	 */
5803 	for_each_intel_crtc(&dev_priv->drm, crtc) {
5804 		struct intel_crtc_state *crtc_state;
5805 		int ret;
5806 
5807 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5808 		if (IS_ERR(crtc_state))
5809 			return PTR_ERR(crtc_state);
5810 
5811 		if (!crtc_state->hw.active ||
5812 		    intel_crtc_needs_modeset(crtc_state))
5813 			continue;
5814 
5815 		drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] Full modeset due to %s\n",
5816 			    crtc->base.base.id, crtc->base.name, reason);
5817 
5818 		crtc_state->uapi.mode_changed = true;
5819 		crtc_state->update_pipe = false;
5820 
5821 		ret = drm_atomic_add_affected_connectors(&state->base,
5822 							 &crtc->base);
5823 		if (ret)
5824 			return ret;
5825 
5826 		ret = intel_dp_mst_add_topology_state_for_crtc(state, crtc);
5827 		if (ret)
5828 			return ret;
5829 
5830 		ret = intel_atomic_add_affected_planes(state, crtc);
5831 		if (ret)
5832 			return ret;
5833 
5834 		crtc_state->update_planes |= crtc_state->active_planes;
5835 		crtc_state->async_flip_planes = 0;
5836 		crtc_state->do_async_flip = false;
5837 	}
5838 
5839 	return 0;
5840 }
5841 
5842 /*
5843  * This implements the workaround described in the "notes" section of the mode
5844  * set sequence documentation. When going from no pipes or single pipe to
5845  * multiple pipes, and planes are enabled after the pipe, we need to wait at
5846  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
5847  */
5848 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
5849 {
5850 	struct intel_crtc_state *crtc_state;
5851 	struct intel_crtc *crtc;
5852 	struct intel_crtc_state *first_crtc_state = NULL;
5853 	struct intel_crtc_state *other_crtc_state = NULL;
5854 	enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
5855 	int i;
5856 
5857 	/* look at all crtc's that are going to be enabled in during modeset */
5858 	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5859 		if (!crtc_state->hw.active ||
5860 		    !intel_crtc_needs_modeset(crtc_state))
5861 			continue;
5862 
5863 		if (first_crtc_state) {
5864 			other_crtc_state = crtc_state;
5865 			break;
5866 		} else {
5867 			first_crtc_state = crtc_state;
5868 			first_pipe = crtc->pipe;
5869 		}
5870 	}
5871 
5872 	/* No workaround needed? */
5873 	if (!first_crtc_state)
5874 		return 0;
5875 
5876 	/* w/a possibly needed, check how many crtc's are already enabled. */
5877 	for_each_intel_crtc(state->base.dev, crtc) {
5878 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5879 		if (IS_ERR(crtc_state))
5880 			return PTR_ERR(crtc_state);
5881 
5882 		crtc_state->hsw_workaround_pipe = INVALID_PIPE;
5883 
5884 		if (!crtc_state->hw.active ||
5885 		    intel_crtc_needs_modeset(crtc_state))
5886 			continue;
5887 
5888 		/* 2 or more enabled crtcs means no need for w/a */
5889 		if (enabled_pipe != INVALID_PIPE)
5890 			return 0;
5891 
5892 		enabled_pipe = crtc->pipe;
5893 	}
5894 
5895 	if (enabled_pipe != INVALID_PIPE)
5896 		first_crtc_state->hsw_workaround_pipe = enabled_pipe;
5897 	else if (other_crtc_state)
5898 		other_crtc_state->hsw_workaround_pipe = first_pipe;
5899 
5900 	return 0;
5901 }
5902 
5903 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
5904 			   u8 active_pipes)
5905 {
5906 	const struct intel_crtc_state *crtc_state;
5907 	struct intel_crtc *crtc;
5908 	int i;
5909 
5910 	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5911 		if (crtc_state->hw.active)
5912 			active_pipes |= BIT(crtc->pipe);
5913 		else
5914 			active_pipes &= ~BIT(crtc->pipe);
5915 	}
5916 
5917 	return active_pipes;
5918 }
5919 
5920 static int intel_modeset_checks(struct intel_atomic_state *state)
5921 {
5922 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5923 
5924 	state->modeset = true;
5925 
5926 	if (IS_HASWELL(dev_priv))
5927 		return hsw_mode_set_planes_workaround(state);
5928 
5929 	return 0;
5930 }
5931 
5932 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
5933 				     struct intel_crtc_state *new_crtc_state)
5934 {
5935 	if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
5936 		return;
5937 
5938 	new_crtc_state->uapi.mode_changed = false;
5939 	if (!intel_crtc_needs_modeset(new_crtc_state))
5940 		new_crtc_state->update_pipe = true;
5941 }
5942 
5943 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
5944 					  struct intel_crtc *crtc,
5945 					  u8 plane_ids_mask)
5946 {
5947 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5948 	struct intel_plane *plane;
5949 
5950 	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
5951 		struct intel_plane_state *plane_state;
5952 
5953 		if ((plane_ids_mask & BIT(plane->id)) == 0)
5954 			continue;
5955 
5956 		plane_state = intel_atomic_get_plane_state(state, plane);
5957 		if (IS_ERR(plane_state))
5958 			return PTR_ERR(plane_state);
5959 	}
5960 
5961 	return 0;
5962 }
5963 
5964 int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
5965 				     struct intel_crtc *crtc)
5966 {
5967 	const struct intel_crtc_state *old_crtc_state =
5968 		intel_atomic_get_old_crtc_state(state, crtc);
5969 	const struct intel_crtc_state *new_crtc_state =
5970 		intel_atomic_get_new_crtc_state(state, crtc);
5971 
5972 	return intel_crtc_add_planes_to_state(state, crtc,
5973 					      old_crtc_state->enabled_planes |
5974 					      new_crtc_state->enabled_planes);
5975 }
5976 
5977 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
5978 {
5979 	/* See {hsw,vlv,ivb}_plane_ratio() */
5980 	return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
5981 		IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
5982 		IS_IVYBRIDGE(dev_priv);
5983 }
5984 
5985 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state,
5986 					   struct intel_crtc *crtc,
5987 					   struct intel_crtc *other)
5988 {
5989 	const struct intel_plane_state *plane_state;
5990 	struct intel_plane *plane;
5991 	u8 plane_ids = 0;
5992 	int i;
5993 
5994 	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
5995 		if (plane->pipe == crtc->pipe)
5996 			plane_ids |= BIT(plane->id);
5997 	}
5998 
5999 	return intel_crtc_add_planes_to_state(state, other, plane_ids);
6000 }
6001 
6002 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state)
6003 {
6004 	struct drm_i915_private *i915 = to_i915(state->base.dev);
6005 	const struct intel_crtc_state *crtc_state;
6006 	struct intel_crtc *crtc;
6007 	int i;
6008 
6009 	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6010 		struct intel_crtc *other;
6011 
6012 		for_each_intel_crtc_in_pipe_mask(&i915->drm, other,
6013 						 crtc_state->bigjoiner_pipes) {
6014 			int ret;
6015 
6016 			if (crtc == other)
6017 				continue;
6018 
6019 			ret = intel_crtc_add_bigjoiner_planes(state, crtc, other);
6020 			if (ret)
6021 				return ret;
6022 		}
6023 	}
6024 
6025 	return 0;
6026 }
6027 
6028 static int intel_atomic_check_planes(struct intel_atomic_state *state)
6029 {
6030 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6031 	struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6032 	struct intel_plane_state *plane_state;
6033 	struct intel_plane *plane;
6034 	struct intel_crtc *crtc;
6035 	int i, ret;
6036 
6037 	ret = icl_add_linked_planes(state);
6038 	if (ret)
6039 		return ret;
6040 
6041 	ret = intel_bigjoiner_add_affected_planes(state);
6042 	if (ret)
6043 		return ret;
6044 
6045 	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
6046 		ret = intel_plane_atomic_check(state, plane);
6047 		if (ret) {
6048 			drm_dbg_atomic(&dev_priv->drm,
6049 				       "[PLANE:%d:%s] atomic driver check failed\n",
6050 				       plane->base.base.id, plane->base.name);
6051 			return ret;
6052 		}
6053 	}
6054 
6055 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6056 					    new_crtc_state, i) {
6057 		u8 old_active_planes, new_active_planes;
6058 
6059 		ret = icl_check_nv12_planes(new_crtc_state);
6060 		if (ret)
6061 			return ret;
6062 
6063 		/*
6064 		 * On some platforms the number of active planes affects
6065 		 * the planes' minimum cdclk calculation. Add such planes
6066 		 * to the state before we compute the minimum cdclk.
6067 		 */
6068 		if (!active_planes_affects_min_cdclk(dev_priv))
6069 			continue;
6070 
6071 		old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
6072 		new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
6073 
6074 		if (hweight8(old_active_planes) == hweight8(new_active_planes))
6075 			continue;
6076 
6077 		ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
6078 		if (ret)
6079 			return ret;
6080 	}
6081 
6082 	return 0;
6083 }
6084 
6085 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
6086 {
6087 	struct intel_crtc_state *crtc_state;
6088 	struct intel_crtc *crtc;
6089 	int i;
6090 
6091 	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6092 		struct drm_i915_private *i915 = to_i915(crtc->base.dev);
6093 		int ret;
6094 
6095 		ret = intel_crtc_atomic_check(state, crtc);
6096 		if (ret) {
6097 			drm_dbg_atomic(&i915->drm,
6098 				       "[CRTC:%d:%s] atomic driver check failed\n",
6099 				       crtc->base.base.id, crtc->base.name);
6100 			return ret;
6101 		}
6102 	}
6103 
6104 	return 0;
6105 }
6106 
6107 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
6108 					       u8 transcoders)
6109 {
6110 	const struct intel_crtc_state *new_crtc_state;
6111 	struct intel_crtc *crtc;
6112 	int i;
6113 
6114 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6115 		if (new_crtc_state->hw.enable &&
6116 		    transcoders & BIT(new_crtc_state->cpu_transcoder) &&
6117 		    intel_crtc_needs_modeset(new_crtc_state))
6118 			return true;
6119 	}
6120 
6121 	return false;
6122 }
6123 
6124 static bool intel_pipes_need_modeset(struct intel_atomic_state *state,
6125 				     u8 pipes)
6126 {
6127 	const struct intel_crtc_state *new_crtc_state;
6128 	struct intel_crtc *crtc;
6129 	int i;
6130 
6131 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6132 		if (new_crtc_state->hw.enable &&
6133 		    pipes & BIT(crtc->pipe) &&
6134 		    intel_crtc_needs_modeset(new_crtc_state))
6135 			return true;
6136 	}
6137 
6138 	return false;
6139 }
6140 
6141 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state,
6142 					struct intel_crtc *master_crtc)
6143 {
6144 	struct drm_i915_private *i915 = to_i915(state->base.dev);
6145 	struct intel_crtc_state *master_crtc_state =
6146 		intel_atomic_get_new_crtc_state(state, master_crtc);
6147 	struct intel_crtc *slave_crtc;
6148 
6149 	if (!master_crtc_state->bigjoiner_pipes)
6150 		return 0;
6151 
6152 	/* sanity check */
6153 	if (drm_WARN_ON(&i915->drm,
6154 			master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state)))
6155 		return -EINVAL;
6156 
6157 	if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) {
6158 		drm_dbg_kms(&i915->drm,
6159 			    "[CRTC:%d:%s] Cannot act as big joiner master "
6160 			    "(need 0x%x as pipes, only 0x%x possible)\n",
6161 			    master_crtc->base.base.id, master_crtc->base.name,
6162 			    master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915));
6163 		return -EINVAL;
6164 	}
6165 
6166 	for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
6167 					 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) {
6168 		struct intel_crtc_state *slave_crtc_state;
6169 		int ret;
6170 
6171 		slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc);
6172 		if (IS_ERR(slave_crtc_state))
6173 			return PTR_ERR(slave_crtc_state);
6174 
6175 		/* master being enabled, slave was already configured? */
6176 		if (slave_crtc_state->uapi.enable) {
6177 			drm_dbg_kms(&i915->drm,
6178 				    "[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
6179 				    "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
6180 				    slave_crtc->base.base.id, slave_crtc->base.name,
6181 				    master_crtc->base.base.id, master_crtc->base.name);
6182 			return -EINVAL;
6183 		}
6184 
6185 		/*
6186 		 * The state copy logic assumes the master crtc gets processed
6187 		 * before the slave crtc during the main compute_config loop.
6188 		 * This works because the crtcs are created in pipe order,
6189 		 * and the hardware requires master pipe < slave pipe as well.
6190 		 * Should that change we need to rethink the logic.
6191 		 */
6192 		if (WARN_ON(drm_crtc_index(&master_crtc->base) >
6193 			    drm_crtc_index(&slave_crtc->base)))
6194 			return -EINVAL;
6195 
6196 		drm_dbg_kms(&i915->drm,
6197 			    "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n",
6198 			    slave_crtc->base.base.id, slave_crtc->base.name,
6199 			    master_crtc->base.base.id, master_crtc->base.name);
6200 
6201 		slave_crtc_state->bigjoiner_pipes =
6202 			master_crtc_state->bigjoiner_pipes;
6203 
6204 		ret = copy_bigjoiner_crtc_state_modeset(state, slave_crtc);
6205 		if (ret)
6206 			return ret;
6207 	}
6208 
6209 	return 0;
6210 }
6211 
6212 static void kill_bigjoiner_slave(struct intel_atomic_state *state,
6213 				 struct intel_crtc *master_crtc)
6214 {
6215 	struct drm_i915_private *i915 = to_i915(state->base.dev);
6216 	struct intel_crtc_state *master_crtc_state =
6217 		intel_atomic_get_new_crtc_state(state, master_crtc);
6218 	struct intel_crtc *slave_crtc;
6219 
6220 	for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
6221 					 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) {
6222 		struct intel_crtc_state *slave_crtc_state =
6223 			intel_atomic_get_new_crtc_state(state, slave_crtc);
6224 
6225 		slave_crtc_state->bigjoiner_pipes = 0;
6226 
6227 		intel_crtc_copy_uapi_to_hw_state_modeset(state, slave_crtc);
6228 	}
6229 
6230 	master_crtc_state->bigjoiner_pipes = 0;
6231 }
6232 
6233 /**
6234  * DOC: asynchronous flip implementation
6235  *
6236  * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
6237  * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
6238  * Correspondingly, support is currently added for primary plane only.
6239  *
6240  * Async flip can only change the plane surface address, so anything else
6241  * changing is rejected from the intel_async_flip_check_hw() function.
6242  * Once this check is cleared, flip done interrupt is enabled using
6243  * the intel_crtc_enable_flip_done() function.
6244  *
6245  * As soon as the surface address register is written, flip done interrupt is
6246  * generated and the requested events are sent to the usersapce in the interrupt
6247  * handler itself. The timestamp and sequence sent during the flip done event
6248  * correspond to the last vblank and have no relation to the actual time when
6249  * the flip done event was sent.
6250  */
6251 static int intel_async_flip_check_uapi(struct intel_atomic_state *state,
6252 				       struct intel_crtc *crtc)
6253 {
6254 	struct drm_i915_private *i915 = to_i915(state->base.dev);
6255 	const struct intel_crtc_state *new_crtc_state =
6256 		intel_atomic_get_new_crtc_state(state, crtc);
6257 	const struct intel_plane_state *old_plane_state;
6258 	struct intel_plane_state *new_plane_state;
6259 	struct intel_plane *plane;
6260 	int i;
6261 
6262 	if (!new_crtc_state->uapi.async_flip)
6263 		return 0;
6264 
6265 	if (!new_crtc_state->uapi.active) {
6266 		drm_dbg_kms(&i915->drm,
6267 			    "[CRTC:%d:%s] not active\n",
6268 			    crtc->base.base.id, crtc->base.name);
6269 		return -EINVAL;
6270 	}
6271 
6272 	if (intel_crtc_needs_modeset(new_crtc_state)) {
6273 		drm_dbg_kms(&i915->drm,
6274 			    "[CRTC:%d:%s] modeset required\n",
6275 			    crtc->base.base.id, crtc->base.name);
6276 		return -EINVAL;
6277 	}
6278 
6279 	for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
6280 					     new_plane_state, i) {
6281 		if (plane->pipe != crtc->pipe)
6282 			continue;
6283 
6284 		/*
6285 		 * TODO: Async flip is only supported through the page flip IOCTL
6286 		 * as of now. So support currently added for primary plane only.
6287 		 * Support for other planes on platforms on which supports
6288 		 * this(vlv/chv and icl+) should be added when async flip is
6289 		 * enabled in the atomic IOCTL path.
6290 		 */
6291 		if (!plane->async_flip) {
6292 			drm_dbg_kms(&i915->drm,
6293 				    "[PLANE:%d:%s] async flip not supported\n",
6294 				    plane->base.base.id, plane->base.name);
6295 			return -EINVAL;
6296 		}
6297 
6298 		if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) {
6299 			drm_dbg_kms(&i915->drm,
6300 				    "[PLANE:%d:%s] no old or new framebuffer\n",
6301 				    plane->base.base.id, plane->base.name);
6302 			return -EINVAL;
6303 		}
6304 	}
6305 
6306 	return 0;
6307 }
6308 
6309 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc)
6310 {
6311 	struct drm_i915_private *i915 = to_i915(state->base.dev);
6312 	const struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6313 	const struct intel_plane_state *new_plane_state, *old_plane_state;
6314 	struct intel_plane *plane;
6315 	int i;
6316 
6317 	old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
6318 	new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6319 
6320 	if (!new_crtc_state->uapi.async_flip)
6321 		return 0;
6322 
6323 	if (!new_crtc_state->hw.active) {
6324 		drm_dbg_kms(&i915->drm,
6325 			    "[CRTC:%d:%s] not active\n",
6326 			    crtc->base.base.id, crtc->base.name);
6327 		return -EINVAL;
6328 	}
6329 
6330 	if (intel_crtc_needs_modeset(new_crtc_state)) {
6331 		drm_dbg_kms(&i915->drm,
6332 			    "[CRTC:%d:%s] modeset required\n",
6333 			    crtc->base.base.id, crtc->base.name);
6334 		return -EINVAL;
6335 	}
6336 
6337 	if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
6338 		drm_dbg_kms(&i915->drm,
6339 			    "[CRTC:%d:%s] Active planes cannot be in async flip\n",
6340 			    crtc->base.base.id, crtc->base.name);
6341 		return -EINVAL;
6342 	}
6343 
6344 	for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
6345 					     new_plane_state, i) {
6346 		if (plane->pipe != crtc->pipe)
6347 			continue;
6348 
6349 		/*
6350 		 * Only async flip capable planes should be in the state
6351 		 * if we're really about to ask the hardware to perform
6352 		 * an async flip. We should never get this far otherwise.
6353 		 */
6354 		if (drm_WARN_ON(&i915->drm,
6355 				new_crtc_state->do_async_flip && !plane->async_flip))
6356 			return -EINVAL;
6357 
6358 		/*
6359 		 * Only check async flip capable planes other planes
6360 		 * may be involved in the initial commit due to
6361 		 * the wm0/ddb optimization.
6362 		 *
6363 		 * TODO maybe should track which planes actually
6364 		 * were requested to do the async flip...
6365 		 */
6366 		if (!plane->async_flip)
6367 			continue;
6368 
6369 		/*
6370 		 * FIXME: This check is kept generic for all platforms.
6371 		 * Need to verify this for all gen9 platforms to enable
6372 		 * this selectively if required.
6373 		 */
6374 		switch (new_plane_state->hw.fb->modifier) {
6375 		case I915_FORMAT_MOD_X_TILED:
6376 		case I915_FORMAT_MOD_Y_TILED:
6377 		case I915_FORMAT_MOD_Yf_TILED:
6378 		case I915_FORMAT_MOD_4_TILED:
6379 			break;
6380 		default:
6381 			drm_dbg_kms(&i915->drm,
6382 				    "[PLANE:%d:%s] Modifier does not support async flips\n",
6383 				    plane->base.base.id, plane->base.name);
6384 			return -EINVAL;
6385 		}
6386 
6387 		if (new_plane_state->hw.fb->format->num_planes > 1) {
6388 			drm_dbg_kms(&i915->drm,
6389 				    "[PLANE:%d:%s] Planar formats do not support async flips\n",
6390 				    plane->base.base.id, plane->base.name);
6391 			return -EINVAL;
6392 		}
6393 
6394 		if (old_plane_state->view.color_plane[0].mapping_stride !=
6395 		    new_plane_state->view.color_plane[0].mapping_stride) {
6396 			drm_dbg_kms(&i915->drm,
6397 				    "[PLANE:%d:%s] Stride cannot be changed in async flip\n",
6398 				    plane->base.base.id, plane->base.name);
6399 			return -EINVAL;
6400 		}
6401 
6402 		if (old_plane_state->hw.fb->modifier !=
6403 		    new_plane_state->hw.fb->modifier) {
6404 			drm_dbg_kms(&i915->drm,
6405 				    "[PLANE:%d:%s] Modifier cannot be changed in async flip\n",
6406 				    plane->base.base.id, plane->base.name);
6407 			return -EINVAL;
6408 		}
6409 
6410 		if (old_plane_state->hw.fb->format !=
6411 		    new_plane_state->hw.fb->format) {
6412 			drm_dbg_kms(&i915->drm,
6413 				    "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n",
6414 				    plane->base.base.id, plane->base.name);
6415 			return -EINVAL;
6416 		}
6417 
6418 		if (old_plane_state->hw.rotation !=
6419 		    new_plane_state->hw.rotation) {
6420 			drm_dbg_kms(&i915->drm,
6421 				    "[PLANE:%d:%s] Rotation cannot be changed in async flip\n",
6422 				    plane->base.base.id, plane->base.name);
6423 			return -EINVAL;
6424 		}
6425 
6426 		if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) ||
6427 		    !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) {
6428 			drm_dbg_kms(&i915->drm,
6429 				    "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n",
6430 				    plane->base.base.id, plane->base.name);
6431 			return -EINVAL;
6432 		}
6433 
6434 		if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
6435 			drm_dbg_kms(&i915->drm,
6436 				    "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n",
6437 				    plane->base.base.id, plane->base.name);
6438 			return -EINVAL;
6439 		}
6440 
6441 		if (old_plane_state->hw.pixel_blend_mode !=
6442 		    new_plane_state->hw.pixel_blend_mode) {
6443 			drm_dbg_kms(&i915->drm,
6444 				    "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n",
6445 				    plane->base.base.id, plane->base.name);
6446 			return -EINVAL;
6447 		}
6448 
6449 		if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
6450 			drm_dbg_kms(&i915->drm,
6451 				    "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n",
6452 				    plane->base.base.id, plane->base.name);
6453 			return -EINVAL;
6454 		}
6455 
6456 		if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
6457 			drm_dbg_kms(&i915->drm,
6458 				    "[PLANE:%d:%s] Color range cannot be changed in async flip\n",
6459 				    plane->base.base.id, plane->base.name);
6460 			return -EINVAL;
6461 		}
6462 
6463 		/* plane decryption is allow to change only in synchronous flips */
6464 		if (old_plane_state->decrypt != new_plane_state->decrypt) {
6465 			drm_dbg_kms(&i915->drm,
6466 				    "[PLANE:%d:%s] Decryption cannot be changed in async flip\n",
6467 				    plane->base.base.id, plane->base.name);
6468 			return -EINVAL;
6469 		}
6470 	}
6471 
6472 	return 0;
6473 }
6474 
6475 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state)
6476 {
6477 	struct drm_i915_private *i915 = to_i915(state->base.dev);
6478 	struct intel_crtc_state *crtc_state;
6479 	struct intel_crtc *crtc;
6480 	u8 affected_pipes = 0;
6481 	u8 modeset_pipes = 0;
6482 	int i;
6483 
6484 	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6485 		affected_pipes |= crtc_state->bigjoiner_pipes;
6486 		if (intel_crtc_needs_modeset(crtc_state))
6487 			modeset_pipes |= crtc_state->bigjoiner_pipes;
6488 	}
6489 
6490 	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) {
6491 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
6492 		if (IS_ERR(crtc_state))
6493 			return PTR_ERR(crtc_state);
6494 	}
6495 
6496 	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) {
6497 		int ret;
6498 
6499 		crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6500 
6501 		crtc_state->uapi.mode_changed = true;
6502 
6503 		ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
6504 		if (ret)
6505 			return ret;
6506 
6507 		ret = intel_atomic_add_affected_planes(state, crtc);
6508 		if (ret)
6509 			return ret;
6510 	}
6511 
6512 	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6513 		/* Kill old bigjoiner link, we may re-establish afterwards */
6514 		if (intel_crtc_needs_modeset(crtc_state) &&
6515 		    intel_crtc_is_bigjoiner_master(crtc_state))
6516 			kill_bigjoiner_slave(state, crtc);
6517 	}
6518 
6519 	return 0;
6520 }
6521 
6522 /**
6523  * intel_atomic_check - validate state object
6524  * @dev: drm device
6525  * @_state: state to validate
6526  */
6527 int intel_atomic_check(struct drm_device *dev,
6528 		       struct drm_atomic_state *_state)
6529 {
6530 	struct drm_i915_private *dev_priv = to_i915(dev);
6531 	struct intel_atomic_state *state = to_intel_atomic_state(_state);
6532 	struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6533 	struct intel_crtc *crtc;
6534 	int ret, i;
6535 	bool any_ms = false;
6536 
6537 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6538 					    new_crtc_state, i) {
6539 		if (new_crtc_state->inherited != old_crtc_state->inherited)
6540 			new_crtc_state->uapi.mode_changed = true;
6541 
6542 		if (new_crtc_state->uapi.scaling_filter !=
6543 		    old_crtc_state->uapi.scaling_filter)
6544 			new_crtc_state->uapi.mode_changed = true;
6545 	}
6546 
6547 	intel_vrr_check_modeset(state);
6548 
6549 	ret = drm_atomic_helper_check_modeset(dev, &state->base);
6550 	if (ret)
6551 		goto fail;
6552 
6553 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6554 		ret = intel_async_flip_check_uapi(state, crtc);
6555 		if (ret)
6556 			return ret;
6557 	}
6558 
6559 	ret = intel_bigjoiner_add_affected_crtcs(state);
6560 	if (ret)
6561 		goto fail;
6562 
6563 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6564 					    new_crtc_state, i) {
6565 		if (!intel_crtc_needs_modeset(new_crtc_state)) {
6566 			if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
6567 				copy_bigjoiner_crtc_state_nomodeset(state, crtc);
6568 			else
6569 				intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
6570 			continue;
6571 		}
6572 
6573 		if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) {
6574 			drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable);
6575 			continue;
6576 		}
6577 
6578 		ret = intel_crtc_prepare_cleared_state(state, crtc);
6579 		if (ret)
6580 			goto fail;
6581 
6582 		if (!new_crtc_state->hw.enable)
6583 			continue;
6584 
6585 		ret = intel_modeset_pipe_config(state, crtc);
6586 		if (ret)
6587 			goto fail;
6588 
6589 		ret = intel_atomic_check_bigjoiner(state, crtc);
6590 		if (ret)
6591 			goto fail;
6592 	}
6593 
6594 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6595 					    new_crtc_state, i) {
6596 		if (!intel_crtc_needs_modeset(new_crtc_state))
6597 			continue;
6598 
6599 		if (new_crtc_state->hw.enable) {
6600 			ret = intel_modeset_pipe_config_late(state, crtc);
6601 			if (ret)
6602 				goto fail;
6603 		}
6604 
6605 		intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
6606 	}
6607 
6608 	/**
6609 	 * Check if fastset is allowed by external dependencies like other
6610 	 * pipes and transcoders.
6611 	 *
6612 	 * Right now it only forces a fullmodeset when the MST master
6613 	 * transcoder did not changed but the pipe of the master transcoder
6614 	 * needs a fullmodeset so all slaves also needs to do a fullmodeset or
6615 	 * in case of port synced crtcs, if one of the synced crtcs
6616 	 * needs a full modeset, all other synced crtcs should be
6617 	 * forced a full modeset.
6618 	 */
6619 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6620 		if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state))
6621 			continue;
6622 
6623 		if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
6624 			enum transcoder master = new_crtc_state->mst_master_transcoder;
6625 
6626 			if (intel_cpu_transcoders_need_modeset(state, BIT(master))) {
6627 				new_crtc_state->uapi.mode_changed = true;
6628 				new_crtc_state->update_pipe = false;
6629 			}
6630 		}
6631 
6632 		if (is_trans_port_sync_mode(new_crtc_state)) {
6633 			u8 trans = new_crtc_state->sync_mode_slaves_mask;
6634 
6635 			if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
6636 				trans |= BIT(new_crtc_state->master_transcoder);
6637 
6638 			if (intel_cpu_transcoders_need_modeset(state, trans)) {
6639 				new_crtc_state->uapi.mode_changed = true;
6640 				new_crtc_state->update_pipe = false;
6641 			}
6642 		}
6643 
6644 		if (new_crtc_state->bigjoiner_pipes) {
6645 			if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) {
6646 				new_crtc_state->uapi.mode_changed = true;
6647 				new_crtc_state->update_pipe = false;
6648 			}
6649 		}
6650 	}
6651 
6652 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6653 					    new_crtc_state, i) {
6654 		if (!intel_crtc_needs_modeset(new_crtc_state))
6655 			continue;
6656 
6657 		any_ms = true;
6658 
6659 		intel_release_shared_dplls(state, crtc);
6660 	}
6661 
6662 	if (any_ms && !check_digital_port_conflicts(state)) {
6663 		drm_dbg_kms(&dev_priv->drm,
6664 			    "rejecting conflicting digital port configuration\n");
6665 		ret = -EINVAL;
6666 		goto fail;
6667 	}
6668 
6669 	ret = drm_dp_mst_atomic_check(&state->base);
6670 	if (ret)
6671 		goto fail;
6672 
6673 	ret = intel_atomic_check_planes(state);
6674 	if (ret)
6675 		goto fail;
6676 
6677 	ret = intel_compute_global_watermarks(state);
6678 	if (ret)
6679 		goto fail;
6680 
6681 	ret = intel_bw_atomic_check(state);
6682 	if (ret)
6683 		goto fail;
6684 
6685 	ret = intel_cdclk_atomic_check(state, &any_ms);
6686 	if (ret)
6687 		goto fail;
6688 
6689 	if (intel_any_crtc_needs_modeset(state))
6690 		any_ms = true;
6691 
6692 	if (any_ms) {
6693 		ret = intel_modeset_checks(state);
6694 		if (ret)
6695 			goto fail;
6696 
6697 		ret = intel_modeset_calc_cdclk(state);
6698 		if (ret)
6699 			return ret;
6700 	}
6701 
6702 	ret = intel_atomic_check_crtcs(state);
6703 	if (ret)
6704 		goto fail;
6705 
6706 	ret = intel_fbc_atomic_check(state);
6707 	if (ret)
6708 		goto fail;
6709 
6710 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6711 					    new_crtc_state, i) {
6712 		intel_color_assert_luts(new_crtc_state);
6713 
6714 		ret = intel_async_flip_check_hw(state, crtc);
6715 		if (ret)
6716 			goto fail;
6717 
6718 		/* Either full modeset or fastset (or neither), never both */
6719 		drm_WARN_ON(&dev_priv->drm,
6720 			    intel_crtc_needs_modeset(new_crtc_state) &&
6721 			    intel_crtc_needs_fastset(new_crtc_state));
6722 
6723 		if (!intel_crtc_needs_modeset(new_crtc_state) &&
6724 		    !intel_crtc_needs_fastset(new_crtc_state))
6725 			continue;
6726 
6727 		intel_crtc_state_dump(new_crtc_state, state,
6728 				      intel_crtc_needs_modeset(new_crtc_state) ?
6729 				      "modeset" : "fastset");
6730 	}
6731 
6732 	return 0;
6733 
6734  fail:
6735 	if (ret == -EDEADLK)
6736 		return ret;
6737 
6738 	/*
6739 	 * FIXME would probably be nice to know which crtc specifically
6740 	 * caused the failure, in cases where we can pinpoint it.
6741 	 */
6742 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6743 					    new_crtc_state, i)
6744 		intel_crtc_state_dump(new_crtc_state, state, "failed");
6745 
6746 	return ret;
6747 }
6748 
6749 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
6750 {
6751 	struct intel_crtc_state *crtc_state;
6752 	struct intel_crtc *crtc;
6753 	int i, ret;
6754 
6755 	ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);
6756 	if (ret < 0)
6757 		return ret;
6758 
6759 	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6760 		if (intel_crtc_needs_color_update(crtc_state))
6761 			intel_color_prepare_commit(crtc_state);
6762 	}
6763 
6764 	return 0;
6765 }
6766 
6767 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
6768 				  struct intel_crtc_state *crtc_state)
6769 {
6770 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6771 
6772 	if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes)
6773 		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
6774 
6775 	if (crtc_state->has_pch_encoder) {
6776 		enum pipe pch_transcoder =
6777 			intel_crtc_pch_transcoder(crtc);
6778 
6779 		intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
6780 	}
6781 }
6782 
6783 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
6784 			       const struct intel_crtc_state *new_crtc_state)
6785 {
6786 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6787 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6788 
6789 	/*
6790 	 * Update pipe size and adjust fitter if needed: the reason for this is
6791 	 * that in compute_mode_changes we check the native mode (not the pfit
6792 	 * mode) to see if we can flip rather than do a full mode set. In the
6793 	 * fastboot case, we'll flip, but if we don't update the pipesrc and
6794 	 * pfit state, we'll end up with a big fb scanned out into the wrong
6795 	 * sized surface.
6796 	 */
6797 	intel_set_pipe_src_size(new_crtc_state);
6798 
6799 	/* on skylake this is done by detaching scalers */
6800 	if (DISPLAY_VER(dev_priv) >= 9) {
6801 		if (new_crtc_state->pch_pfit.enabled)
6802 			skl_pfit_enable(new_crtc_state);
6803 	} else if (HAS_PCH_SPLIT(dev_priv)) {
6804 		if (new_crtc_state->pch_pfit.enabled)
6805 			ilk_pfit_enable(new_crtc_state);
6806 		else if (old_crtc_state->pch_pfit.enabled)
6807 			ilk_pfit_disable(old_crtc_state);
6808 	}
6809 
6810 	/*
6811 	 * The register is supposedly single buffered so perhaps
6812 	 * not 100% correct to do this here. But SKL+ calculate
6813 	 * this based on the adjust pixel rate so pfit changes do
6814 	 * affect it and so it must be updated for fastsets.
6815 	 * HSW/BDW only really need this here for fastboot, after
6816 	 * that the value should not change without a full modeset.
6817 	 */
6818 	if (DISPLAY_VER(dev_priv) >= 9 ||
6819 	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
6820 		hsw_set_linetime_wm(new_crtc_state);
6821 
6822 	if (new_crtc_state->seamless_m_n)
6823 		intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,
6824 					       &new_crtc_state->dp_m_n);
6825 }
6826 
6827 static void commit_pipe_pre_planes(struct intel_atomic_state *state,
6828 				   struct intel_crtc *crtc)
6829 {
6830 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6831 	const struct intel_crtc_state *old_crtc_state =
6832 		intel_atomic_get_old_crtc_state(state, crtc);
6833 	const struct intel_crtc_state *new_crtc_state =
6834 		intel_atomic_get_new_crtc_state(state, crtc);
6835 	bool modeset = intel_crtc_needs_modeset(new_crtc_state);
6836 
6837 	/*
6838 	 * During modesets pipe configuration was programmed as the
6839 	 * CRTC was enabled.
6840 	 */
6841 	if (!modeset) {
6842 		if (intel_crtc_needs_color_update(new_crtc_state))
6843 			intel_color_commit_arm(new_crtc_state);
6844 
6845 		if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
6846 			bdw_set_pipe_misc(new_crtc_state);
6847 
6848 		if (intel_crtc_needs_fastset(new_crtc_state))
6849 			intel_pipe_fastset(old_crtc_state, new_crtc_state);
6850 	}
6851 
6852 	intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
6853 
6854 	intel_atomic_update_watermarks(state, crtc);
6855 }
6856 
6857 static void commit_pipe_post_planes(struct intel_atomic_state *state,
6858 				    struct intel_crtc *crtc)
6859 {
6860 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6861 	const struct intel_crtc_state *new_crtc_state =
6862 		intel_atomic_get_new_crtc_state(state, crtc);
6863 
6864 	/*
6865 	 * Disable the scaler(s) after the plane(s) so that we don't
6866 	 * get a catastrophic underrun even if the two operations
6867 	 * end up happening in two different frames.
6868 	 */
6869 	if (DISPLAY_VER(dev_priv) >= 9 &&
6870 	    !intel_crtc_needs_modeset(new_crtc_state))
6871 		skl_detach_scalers(new_crtc_state);
6872 }
6873 
6874 static void intel_enable_crtc(struct intel_atomic_state *state,
6875 			      struct intel_crtc *crtc)
6876 {
6877 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6878 	const struct intel_crtc_state *new_crtc_state =
6879 		intel_atomic_get_new_crtc_state(state, crtc);
6880 
6881 	if (!intel_crtc_needs_modeset(new_crtc_state))
6882 		return;
6883 
6884 	intel_crtc_update_active_timings(new_crtc_state);
6885 
6886 	dev_priv->display.funcs.display->crtc_enable(state, crtc);
6887 
6888 	if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
6889 		return;
6890 
6891 	/* vblanks work again, re-enable pipe CRC. */
6892 	intel_crtc_enable_pipe_crc(crtc);
6893 }
6894 
6895 static void intel_update_crtc(struct intel_atomic_state *state,
6896 			      struct intel_crtc *crtc)
6897 {
6898 	struct drm_i915_private *i915 = to_i915(state->base.dev);
6899 	const struct intel_crtc_state *old_crtc_state =
6900 		intel_atomic_get_old_crtc_state(state, crtc);
6901 	struct intel_crtc_state *new_crtc_state =
6902 		intel_atomic_get_new_crtc_state(state, crtc);
6903 	bool modeset = intel_crtc_needs_modeset(new_crtc_state);
6904 
6905 	if (old_crtc_state->inherited ||
6906 	    intel_crtc_needs_modeset(new_crtc_state)) {
6907 		if (HAS_DPT(i915))
6908 			intel_dpt_configure(crtc);
6909 	}
6910 
6911 	if (!modeset) {
6912 		if (new_crtc_state->preload_luts &&
6913 		    intel_crtc_needs_color_update(new_crtc_state))
6914 			intel_color_load_luts(new_crtc_state);
6915 
6916 		intel_pre_plane_update(state, crtc);
6917 
6918 		if (intel_crtc_needs_fastset(new_crtc_state))
6919 			intel_encoders_update_pipe(state, crtc);
6920 
6921 		if (DISPLAY_VER(i915) >= 11 &&
6922 		    intel_crtc_needs_fastset(new_crtc_state))
6923 			icl_set_pipe_chicken(new_crtc_state);
6924 	}
6925 
6926 	intel_fbc_update(state, crtc);
6927 
6928 	drm_WARN_ON(&i915->drm, !intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF));
6929 
6930 	if (!modeset &&
6931 	    intel_crtc_needs_color_update(new_crtc_state))
6932 		intel_color_commit_noarm(new_crtc_state);
6933 
6934 	intel_crtc_planes_update_noarm(state, crtc);
6935 
6936 	/* Perform vblank evasion around commit operation */
6937 	intel_pipe_update_start(new_crtc_state);
6938 
6939 	commit_pipe_pre_planes(state, crtc);
6940 
6941 	intel_crtc_planes_update_arm(state, crtc);
6942 
6943 	commit_pipe_post_planes(state, crtc);
6944 
6945 	intel_pipe_update_end(new_crtc_state);
6946 
6947 	/*
6948 	 * We usually enable FIFO underrun interrupts as part of the
6949 	 * CRTC enable sequence during modesets.  But when we inherit a
6950 	 * valid pipe configuration from the BIOS we need to take care
6951 	 * of enabling them on the CRTC's first fastset.
6952 	 */
6953 	if (intel_crtc_needs_fastset(new_crtc_state) && !modeset &&
6954 	    old_crtc_state->inherited)
6955 		intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
6956 }
6957 
6958 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
6959 					  struct intel_crtc_state *old_crtc_state,
6960 					  struct intel_crtc_state *new_crtc_state,
6961 					  struct intel_crtc *crtc)
6962 {
6963 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6964 
6965 	/*
6966 	 * We need to disable pipe CRC before disabling the pipe,
6967 	 * or we race against vblank off.
6968 	 */
6969 	intel_crtc_disable_pipe_crc(crtc);
6970 
6971 	dev_priv->display.funcs.display->crtc_disable(state, crtc);
6972 	crtc->active = false;
6973 	intel_fbc_disable(crtc);
6974 
6975 	if (!new_crtc_state->hw.active)
6976 		intel_initial_watermarks(state, crtc);
6977 }
6978 
6979 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
6980 {
6981 	struct intel_crtc_state *new_crtc_state, *old_crtc_state;
6982 	struct intel_crtc *crtc;
6983 	u32 handled = 0;
6984 	int i;
6985 
6986 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6987 					    new_crtc_state, i) {
6988 		if (!intel_crtc_needs_modeset(new_crtc_state))
6989 			continue;
6990 
6991 		if (!old_crtc_state->hw.active)
6992 			continue;
6993 
6994 		intel_pre_plane_update(state, crtc);
6995 		intel_crtc_disable_planes(state, crtc);
6996 	}
6997 
6998 	/* Only disable port sync and MST slaves */
6999 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7000 					    new_crtc_state, i) {
7001 		if (!intel_crtc_needs_modeset(new_crtc_state))
7002 			continue;
7003 
7004 		if (!old_crtc_state->hw.active)
7005 			continue;
7006 
7007 		/* In case of Transcoder port Sync master slave CRTCs can be
7008 		 * assigned in any order and we need to make sure that
7009 		 * slave CRTCs are disabled first and then master CRTC since
7010 		 * Slave vblanks are masked till Master Vblanks.
7011 		 */
7012 		if (!is_trans_port_sync_slave(old_crtc_state) &&
7013 		    !intel_dp_mst_is_slave_trans(old_crtc_state) &&
7014 		    !intel_crtc_is_bigjoiner_slave(old_crtc_state))
7015 			continue;
7016 
7017 		intel_old_crtc_state_disables(state, old_crtc_state,
7018 					      new_crtc_state, crtc);
7019 		handled |= BIT(crtc->pipe);
7020 	}
7021 
7022 	/* Disable everything else left on */
7023 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7024 					    new_crtc_state, i) {
7025 		if (!intel_crtc_needs_modeset(new_crtc_state) ||
7026 		    (handled & BIT(crtc->pipe)))
7027 			continue;
7028 
7029 		if (!old_crtc_state->hw.active)
7030 			continue;
7031 
7032 		intel_old_crtc_state_disables(state, old_crtc_state,
7033 					      new_crtc_state, crtc);
7034 	}
7035 }
7036 
7037 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
7038 {
7039 	struct intel_crtc_state *new_crtc_state;
7040 	struct intel_crtc *crtc;
7041 	int i;
7042 
7043 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7044 		if (!new_crtc_state->hw.active)
7045 			continue;
7046 
7047 		intel_enable_crtc(state, crtc);
7048 		intel_update_crtc(state, crtc);
7049 	}
7050 }
7051 
7052 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
7053 {
7054 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7055 	struct intel_crtc *crtc;
7056 	struct intel_crtc_state *old_crtc_state, *new_crtc_state;
7057 	struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
7058 	u8 update_pipes = 0, modeset_pipes = 0;
7059 	int i;
7060 
7061 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7062 		enum pipe pipe = crtc->pipe;
7063 
7064 		if (!new_crtc_state->hw.active)
7065 			continue;
7066 
7067 		/* ignore allocations for crtc's that have been turned off. */
7068 		if (!intel_crtc_needs_modeset(new_crtc_state)) {
7069 			entries[pipe] = old_crtc_state->wm.skl.ddb;
7070 			update_pipes |= BIT(pipe);
7071 		} else {
7072 			modeset_pipes |= BIT(pipe);
7073 		}
7074 	}
7075 
7076 	/*
7077 	 * Whenever the number of active pipes changes, we need to make sure we
7078 	 * update the pipes in the right order so that their ddb allocations
7079 	 * never overlap with each other between CRTC updates. Otherwise we'll
7080 	 * cause pipe underruns and other bad stuff.
7081 	 *
7082 	 * So first lets enable all pipes that do not need a fullmodeset as
7083 	 * those don't have any external dependency.
7084 	 */
7085 	while (update_pipes) {
7086 		for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7087 						    new_crtc_state, i) {
7088 			enum pipe pipe = crtc->pipe;
7089 
7090 			if ((update_pipes & BIT(pipe)) == 0)
7091 				continue;
7092 
7093 			if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
7094 							entries, I915_MAX_PIPES, pipe))
7095 				continue;
7096 
7097 			entries[pipe] = new_crtc_state->wm.skl.ddb;
7098 			update_pipes &= ~BIT(pipe);
7099 
7100 			intel_update_crtc(state, crtc);
7101 
7102 			/*
7103 			 * If this is an already active pipe, it's DDB changed,
7104 			 * and this isn't the last pipe that needs updating
7105 			 * then we need to wait for a vblank to pass for the
7106 			 * new ddb allocation to take effect.
7107 			 */
7108 			if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
7109 						 &old_crtc_state->wm.skl.ddb) &&
7110 			    (update_pipes | modeset_pipes))
7111 				intel_crtc_wait_for_next_vblank(crtc);
7112 		}
7113 	}
7114 
7115 	update_pipes = modeset_pipes;
7116 
7117 	/*
7118 	 * Enable all pipes that needs a modeset and do not depends on other
7119 	 * pipes
7120 	 */
7121 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7122 		enum pipe pipe = crtc->pipe;
7123 
7124 		if ((modeset_pipes & BIT(pipe)) == 0)
7125 			continue;
7126 
7127 		if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
7128 		    is_trans_port_sync_master(new_crtc_state) ||
7129 		    intel_crtc_is_bigjoiner_master(new_crtc_state))
7130 			continue;
7131 
7132 		modeset_pipes &= ~BIT(pipe);
7133 
7134 		intel_enable_crtc(state, crtc);
7135 	}
7136 
7137 	/*
7138 	 * Then we enable all remaining pipes that depend on other
7139 	 * pipes: MST slaves and port sync masters, big joiner master
7140 	 */
7141 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7142 		enum pipe pipe = crtc->pipe;
7143 
7144 		if ((modeset_pipes & BIT(pipe)) == 0)
7145 			continue;
7146 
7147 		modeset_pipes &= ~BIT(pipe);
7148 
7149 		intel_enable_crtc(state, crtc);
7150 	}
7151 
7152 	/*
7153 	 * Finally we do the plane updates/etc. for all pipes that got enabled.
7154 	 */
7155 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7156 		enum pipe pipe = crtc->pipe;
7157 
7158 		if ((update_pipes & BIT(pipe)) == 0)
7159 			continue;
7160 
7161 		drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
7162 									entries, I915_MAX_PIPES, pipe));
7163 
7164 		entries[pipe] = new_crtc_state->wm.skl.ddb;
7165 		update_pipes &= ~BIT(pipe);
7166 
7167 		intel_update_crtc(state, crtc);
7168 	}
7169 
7170 	drm_WARN_ON(&dev_priv->drm, modeset_pipes);
7171 	drm_WARN_ON(&dev_priv->drm, update_pipes);
7172 }
7173 
7174 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
7175 {
7176 	struct intel_atomic_state *state, *next;
7177 	struct llist_node *freed;
7178 
7179 	freed = llist_del_all(&dev_priv->display.atomic_helper.free_list);
7180 	llist_for_each_entry_safe(state, next, freed, freed)
7181 		drm_atomic_state_put(&state->base);
7182 }
7183 
7184 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
7185 {
7186 	struct drm_i915_private *dev_priv =
7187 		container_of(work, typeof(*dev_priv), display.atomic_helper.free_work);
7188 
7189 	intel_atomic_helper_free_state(dev_priv);
7190 }
7191 
7192 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
7193 {
7194 	struct wait_queue_entry wait_fence, wait_reset;
7195 	struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
7196 
7197 	init_wait_entry(&wait_fence, 0);
7198 	init_wait_entry(&wait_reset, 0);
7199 	for (;;) {
7200 		prepare_to_wait(&intel_state->commit_ready.wait,
7201 				&wait_fence, TASK_UNINTERRUPTIBLE);
7202 		prepare_to_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags,
7203 					      I915_RESET_MODESET),
7204 				&wait_reset, TASK_UNINTERRUPTIBLE);
7205 
7206 
7207 		if (i915_sw_fence_done(&intel_state->commit_ready) ||
7208 		    test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags))
7209 			break;
7210 
7211 		schedule();
7212 	}
7213 	finish_wait(&intel_state->commit_ready.wait, &wait_fence);
7214 	finish_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags,
7215 				  I915_RESET_MODESET),
7216 		    &wait_reset);
7217 }
7218 
7219 static void intel_atomic_cleanup_work(struct work_struct *work)
7220 {
7221 	struct intel_atomic_state *state =
7222 		container_of(work, struct intel_atomic_state, base.commit_work);
7223 	struct drm_i915_private *i915 = to_i915(state->base.dev);
7224 	struct intel_crtc_state *old_crtc_state;
7225 	struct intel_crtc *crtc;
7226 	int i;
7227 
7228 	for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i)
7229 		intel_color_cleanup_commit(old_crtc_state);
7230 
7231 	drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);
7232 	drm_atomic_helper_commit_cleanup_done(&state->base);
7233 	drm_atomic_state_put(&state->base);
7234 
7235 	intel_atomic_helper_free_state(i915);
7236 }
7237 
7238 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state)
7239 {
7240 	struct drm_i915_private *i915 = to_i915(state->base.dev);
7241 	struct intel_plane *plane;
7242 	struct intel_plane_state *plane_state;
7243 	int i;
7244 
7245 	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
7246 		struct drm_framebuffer *fb = plane_state->hw.fb;
7247 		int cc_plane;
7248 		int ret;
7249 
7250 		if (!fb)
7251 			continue;
7252 
7253 		cc_plane = intel_fb_rc_ccs_cc_plane(fb);
7254 		if (cc_plane < 0)
7255 			continue;
7256 
7257 		/*
7258 		 * The layout of the fast clear color value expected by HW
7259 		 * (the DRM ABI requiring this value to be located in fb at
7260 		 * offset 0 of cc plane, plane #2 previous generations or
7261 		 * plane #1 for flat ccs):
7262 		 * - 4 x 4 bytes per-channel value
7263 		 *   (in surface type specific float/int format provided by the fb user)
7264 		 * - 8 bytes native color value used by the display
7265 		 *   (converted/written by GPU during a fast clear operation using the
7266 		 *    above per-channel values)
7267 		 *
7268 		 * The commit's FB prepare hook already ensured that FB obj is pinned and the
7269 		 * caller made sure that the object is synced wrt. the related color clear value
7270 		 * GPU write on it.
7271 		 */
7272 		ret = i915_gem_object_read_from_page(intel_fb_obj(fb),
7273 						     fb->offsets[cc_plane] + 16,
7274 						     &plane_state->ccval,
7275 						     sizeof(plane_state->ccval));
7276 		/* The above could only fail if the FB obj has an unexpected backing store type. */
7277 		drm_WARN_ON(&i915->drm, ret);
7278 	}
7279 }
7280 
7281 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
7282 {
7283 	struct drm_device *dev = state->base.dev;
7284 	struct drm_i915_private *dev_priv = to_i915(dev);
7285 	struct intel_crtc_state *new_crtc_state, *old_crtc_state;
7286 	struct intel_crtc *crtc;
7287 	struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {};
7288 	intel_wakeref_t wakeref = 0;
7289 	int i;
7290 
7291 	intel_atomic_commit_fence_wait(state);
7292 
7293 	drm_atomic_helper_wait_for_dependencies(&state->base);
7294 	drm_dp_mst_atomic_wait_for_dependencies(&state->base);
7295 
7296 	/*
7297 	 * During full modesets we write a lot of registers, wait
7298 	 * for PLLs, etc. Doing that while DC states are enabled
7299 	 * is not a good idea.
7300 	 *
7301 	 * During fastsets and other updates we also need to
7302 	 * disable DC states due to the following scenario:
7303 	 * 1. DC5 exit and PSR exit happen
7304 	 * 2. Some or all _noarm() registers are written
7305 	 * 3. Due to some long delay PSR is re-entered
7306 	 * 4. DC5 entry -> DMC saves the already written new
7307 	 *    _noarm() registers and the old not yet written
7308 	 *    _arm() registers
7309 	 * 5. DC5 exit -> DMC restores a mixture of old and
7310 	 *    new register values and arms the update
7311 	 * 6. PSR exit -> hardware latches a mixture of old and
7312 	 *    new register values -> corrupted frame, or worse
7313 	 * 7. New _arm() registers are finally written
7314 	 * 8. Hardware finally latches a complete set of new
7315 	 *    register values, and subsequent frames will be OK again
7316 	 */
7317 	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DC_OFF);
7318 
7319 	intel_atomic_prepare_plane_clear_colors(state);
7320 
7321 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7322 					    new_crtc_state, i) {
7323 		if (intel_crtc_needs_modeset(new_crtc_state) ||
7324 		    intel_crtc_needs_fastset(new_crtc_state))
7325 			intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]);
7326 	}
7327 
7328 	intel_commit_modeset_disables(state);
7329 
7330 	/* FIXME: Eventually get rid of our crtc->config pointer */
7331 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7332 		crtc->config = new_crtc_state;
7333 
7334 	if (state->modeset) {
7335 		drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
7336 
7337 		intel_set_cdclk_pre_plane_update(state);
7338 
7339 		intel_modeset_verify_disabled(dev_priv, state);
7340 	}
7341 
7342 	intel_sagv_pre_plane_update(state);
7343 
7344 	/* Complete the events for pipes that have now been disabled */
7345 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7346 		bool modeset = intel_crtc_needs_modeset(new_crtc_state);
7347 
7348 		/* Complete events for now disable pipes here. */
7349 		if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
7350 			spin_lock_irq(&dev->event_lock);
7351 			drm_crtc_send_vblank_event(&crtc->base,
7352 						   new_crtc_state->uapi.event);
7353 			spin_unlock_irq(&dev->event_lock);
7354 
7355 			new_crtc_state->uapi.event = NULL;
7356 		}
7357 	}
7358 
7359 	intel_encoders_update_prepare(state);
7360 
7361 	intel_dbuf_pre_plane_update(state);
7362 	intel_mbus_dbox_update(state);
7363 
7364 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7365 		if (new_crtc_state->do_async_flip)
7366 			intel_crtc_enable_flip_done(state, crtc);
7367 	}
7368 
7369 	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
7370 	dev_priv->display.funcs.display->commit_modeset_enables(state);
7371 
7372 	if (state->modeset)
7373 		intel_set_cdclk_post_plane_update(state);
7374 
7375 	intel_wait_for_vblank_workers(state);
7376 
7377 	/* FIXME: We should call drm_atomic_helper_commit_hw_done() here
7378 	 * already, but still need the state for the delayed optimization. To
7379 	 * fix this:
7380 	 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
7381 	 * - schedule that vblank worker _before_ calling hw_done
7382 	 * - at the start of commit_tail, cancel it _synchrously
7383 	 * - switch over to the vblank wait helper in the core after that since
7384 	 *   we don't need out special handling any more.
7385 	 */
7386 	drm_atomic_helper_wait_for_flip_done(dev, &state->base);
7387 
7388 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7389 		if (new_crtc_state->do_async_flip)
7390 			intel_crtc_disable_flip_done(state, crtc);
7391 	}
7392 
7393 	/*
7394 	 * Now that the vblank has passed, we can go ahead and program the
7395 	 * optimal watermarks on platforms that need two-step watermark
7396 	 * programming.
7397 	 *
7398 	 * TODO: Move this (and other cleanup) to an async worker eventually.
7399 	 */
7400 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7401 					    new_crtc_state, i) {
7402 		/*
7403 		 * Gen2 reports pipe underruns whenever all planes are disabled.
7404 		 * So re-enable underrun reporting after some planes get enabled.
7405 		 *
7406 		 * We do this before .optimize_watermarks() so that we have a
7407 		 * chance of catching underruns with the intermediate watermarks
7408 		 * vs. the new plane configuration.
7409 		 */
7410 		if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state))
7411 			intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
7412 
7413 		intel_optimize_watermarks(state, crtc);
7414 	}
7415 
7416 	intel_dbuf_post_plane_update(state);
7417 	intel_psr_post_plane_update(state);
7418 
7419 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7420 		intel_post_plane_update(state, crtc);
7421 
7422 		intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]);
7423 
7424 		intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
7425 
7426 		/* Must be done after gamma readout due to HSW split gamma vs. IPS w/a */
7427 		hsw_ips_post_update(state, crtc);
7428 
7429 		/*
7430 		 * Activate DRRS after state readout to avoid
7431 		 * dp_m_n vs. dp_m2_n2 confusion on BDW+.
7432 		 */
7433 		intel_drrs_activate(new_crtc_state);
7434 
7435 		/*
7436 		 * DSB cleanup is done in cleanup_work aligning with framebuffer
7437 		 * cleanup. So copy and reset the dsb structure to sync with
7438 		 * commit_done and later do dsb cleanup in cleanup_work.
7439 		 *
7440 		 * FIXME get rid of this funny new->old swapping
7441 		 */
7442 		old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb);
7443 	}
7444 
7445 	/* Underruns don't always raise interrupts, so check manually */
7446 	intel_check_cpu_fifo_underruns(dev_priv);
7447 	intel_check_pch_fifo_underruns(dev_priv);
7448 
7449 	if (state->modeset)
7450 		intel_verify_planes(state);
7451 
7452 	intel_sagv_post_plane_update(state);
7453 
7454 	drm_atomic_helper_commit_hw_done(&state->base);
7455 
7456 	if (state->modeset) {
7457 		/* As one of the primary mmio accessors, KMS has a high
7458 		 * likelihood of triggering bugs in unclaimed access. After we
7459 		 * finish modesetting, see if an error has been flagged, and if
7460 		 * so enable debugging for the next modeset - and hope we catch
7461 		 * the culprit.
7462 		 */
7463 		intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
7464 	}
7465 	intel_display_power_put(dev_priv, POWER_DOMAIN_DC_OFF, wakeref);
7466 	intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7467 
7468 	/*
7469 	 * Defer the cleanup of the old state to a separate worker to not
7470 	 * impede the current task (userspace for blocking modesets) that
7471 	 * are executed inline. For out-of-line asynchronous modesets/flips,
7472 	 * deferring to a new worker seems overkill, but we would place a
7473 	 * schedule point (cond_resched()) here anyway to keep latencies
7474 	 * down.
7475 	 */
7476 	INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
7477 	queue_work(system_highpri_wq, &state->base.commit_work);
7478 }
7479 
7480 static void intel_atomic_commit_work(struct work_struct *work)
7481 {
7482 	struct intel_atomic_state *state =
7483 		container_of(work, struct intel_atomic_state, base.commit_work);
7484 
7485 	intel_atomic_commit_tail(state);
7486 }
7487 
7488 static int
7489 intel_atomic_commit_ready(struct i915_sw_fence *fence,
7490 			  enum i915_sw_fence_notify notify)
7491 {
7492 	struct intel_atomic_state *state =
7493 		container_of(fence, struct intel_atomic_state, commit_ready);
7494 
7495 	switch (notify) {
7496 	case FENCE_COMPLETE:
7497 		/* we do blocking waits in the worker, nothing to do here */
7498 		break;
7499 	case FENCE_FREE:
7500 		{
7501 			struct intel_atomic_helper *helper =
7502 				&to_i915(state->base.dev)->display.atomic_helper;
7503 
7504 			if (llist_add(&state->freed, &helper->free_list))
7505 				schedule_work(&helper->free_work);
7506 			break;
7507 		}
7508 	}
7509 
7510 	return NOTIFY_DONE;
7511 }
7512 
7513 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
7514 {
7515 	struct intel_plane_state *old_plane_state, *new_plane_state;
7516 	struct intel_plane *plane;
7517 	int i;
7518 
7519 	for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
7520 					     new_plane_state, i)
7521 		intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
7522 					to_intel_frontbuffer(new_plane_state->hw.fb),
7523 					plane->frontbuffer_bit);
7524 }
7525 
7526 static int intel_atomic_commit(struct drm_device *dev,
7527 			       struct drm_atomic_state *_state,
7528 			       bool nonblock)
7529 {
7530 	struct intel_atomic_state *state = to_intel_atomic_state(_state);
7531 	struct drm_i915_private *dev_priv = to_i915(dev);
7532 	int ret = 0;
7533 
7534 	state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
7535 
7536 	drm_atomic_state_get(&state->base);
7537 	i915_sw_fence_init(&state->commit_ready,
7538 			   intel_atomic_commit_ready);
7539 
7540 	/*
7541 	 * The intel_legacy_cursor_update() fast path takes care
7542 	 * of avoiding the vblank waits for simple cursor
7543 	 * movement and flips. For cursor on/off and size changes,
7544 	 * we want to perform the vblank waits so that watermark
7545 	 * updates happen during the correct frames. Gen9+ have
7546 	 * double buffered watermarks and so shouldn't need this.
7547 	 *
7548 	 * Unset state->legacy_cursor_update before the call to
7549 	 * drm_atomic_helper_setup_commit() because otherwise
7550 	 * drm_atomic_helper_wait_for_flip_done() is a noop and
7551 	 * we get FIFO underruns because we didn't wait
7552 	 * for vblank.
7553 	 *
7554 	 * FIXME doing watermarks and fb cleanup from a vblank worker
7555 	 * (assuming we had any) would solve these problems.
7556 	 */
7557 	if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) {
7558 		struct intel_crtc_state *new_crtc_state;
7559 		struct intel_crtc *crtc;
7560 		int i;
7561 
7562 		for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7563 			if (new_crtc_state->wm.need_postvbl_update ||
7564 			    new_crtc_state->update_wm_post)
7565 				state->base.legacy_cursor_update = false;
7566 	}
7567 
7568 	ret = intel_atomic_prepare_commit(state);
7569 	if (ret) {
7570 		drm_dbg_atomic(&dev_priv->drm,
7571 			       "Preparing state failed with %i\n", ret);
7572 		i915_sw_fence_commit(&state->commit_ready);
7573 		intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7574 		return ret;
7575 	}
7576 
7577 	ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
7578 	if (!ret)
7579 		ret = drm_atomic_helper_swap_state(&state->base, true);
7580 	if (!ret)
7581 		intel_atomic_swap_global_state(state);
7582 
7583 	if (ret) {
7584 		struct intel_crtc_state *new_crtc_state;
7585 		struct intel_crtc *crtc;
7586 		int i;
7587 
7588 		i915_sw_fence_commit(&state->commit_ready);
7589 
7590 		for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7591 			intel_color_cleanup_commit(new_crtc_state);
7592 
7593 		drm_atomic_helper_cleanup_planes(dev, &state->base);
7594 		intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7595 		return ret;
7596 	}
7597 	intel_shared_dpll_swap_state(state);
7598 	intel_atomic_track_fbs(state);
7599 
7600 	drm_atomic_state_get(&state->base);
7601 	INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
7602 
7603 	i915_sw_fence_commit(&state->commit_ready);
7604 	if (nonblock && state->modeset) {
7605 		queue_work(dev_priv->display.wq.modeset, &state->base.commit_work);
7606 	} else if (nonblock) {
7607 		queue_work(dev_priv->display.wq.flip, &state->base.commit_work);
7608 	} else {
7609 		if (state->modeset)
7610 			flush_workqueue(dev_priv->display.wq.modeset);
7611 		intel_atomic_commit_tail(state);
7612 	}
7613 
7614 	return 0;
7615 }
7616 
7617 /**
7618  * intel_plane_destroy - destroy a plane
7619  * @plane: plane to destroy
7620  *
7621  * Common destruction function for all types of planes (primary, cursor,
7622  * sprite).
7623  */
7624 void intel_plane_destroy(struct drm_plane *plane)
7625 {
7626 	drm_plane_cleanup(plane);
7627 	kfree(to_intel_plane(plane));
7628 }
7629 
7630 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv)
7631 {
7632 	struct intel_plane *plane;
7633 
7634 	for_each_intel_plane(&dev_priv->drm, plane) {
7635 		struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv,
7636 							      plane->pipe);
7637 
7638 		plane->base.possible_crtcs = drm_crtc_mask(&crtc->base);
7639 	}
7640 }
7641 
7642 
7643 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
7644 				      struct drm_file *file)
7645 {
7646 	struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7647 	struct drm_crtc *drmmode_crtc;
7648 	struct intel_crtc *crtc;
7649 
7650 	drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
7651 	if (!drmmode_crtc)
7652 		return -ENOENT;
7653 
7654 	crtc = to_intel_crtc(drmmode_crtc);
7655 	pipe_from_crtc_id->pipe = crtc->pipe;
7656 
7657 	return 0;
7658 }
7659 
7660 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
7661 {
7662 	struct drm_device *dev = encoder->base.dev;
7663 	struct intel_encoder *source_encoder;
7664 	u32 possible_clones = 0;
7665 
7666 	for_each_intel_encoder(dev, source_encoder) {
7667 		if (encoders_cloneable(encoder, source_encoder))
7668 			possible_clones |= drm_encoder_mask(&source_encoder->base);
7669 	}
7670 
7671 	return possible_clones;
7672 }
7673 
7674 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
7675 {
7676 	struct drm_device *dev = encoder->base.dev;
7677 	struct intel_crtc *crtc;
7678 	u32 possible_crtcs = 0;
7679 
7680 	for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask)
7681 		possible_crtcs |= drm_crtc_mask(&crtc->base);
7682 
7683 	return possible_crtcs;
7684 }
7685 
7686 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
7687 {
7688 	if (!IS_MOBILE(dev_priv))
7689 		return false;
7690 
7691 	if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0)
7692 		return false;
7693 
7694 	if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))
7695 		return false;
7696 
7697 	return true;
7698 }
7699 
7700 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
7701 {
7702 	if (DISPLAY_VER(dev_priv) >= 9)
7703 		return false;
7704 
7705 	if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
7706 		return false;
7707 
7708 	if (HAS_PCH_LPT_H(dev_priv) &&
7709 	    intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
7710 		return false;
7711 
7712 	/* DDI E can't be used if DDI A requires 4 lanes */
7713 	if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
7714 		return false;
7715 
7716 	if (!dev_priv->display.vbt.int_crt_support)
7717 		return false;
7718 
7719 	return true;
7720 }
7721 
7722 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
7723 {
7724 	struct intel_encoder *encoder;
7725 	bool dpd_is_edp = false;
7726 
7727 	intel_pps_unlock_regs_wa(dev_priv);
7728 
7729 	if (!HAS_DISPLAY(dev_priv))
7730 		return;
7731 
7732 	if (IS_DG2(dev_priv)) {
7733 		intel_ddi_init(dev_priv, PORT_A);
7734 		intel_ddi_init(dev_priv, PORT_B);
7735 		intel_ddi_init(dev_priv, PORT_C);
7736 		intel_ddi_init(dev_priv, PORT_D_XELPD);
7737 		intel_ddi_init(dev_priv, PORT_TC1);
7738 	} else if (IS_ALDERLAKE_P(dev_priv)) {
7739 		intel_ddi_init(dev_priv, PORT_A);
7740 		intel_ddi_init(dev_priv, PORT_B);
7741 		intel_ddi_init(dev_priv, PORT_TC1);
7742 		intel_ddi_init(dev_priv, PORT_TC2);
7743 		intel_ddi_init(dev_priv, PORT_TC3);
7744 		intel_ddi_init(dev_priv, PORT_TC4);
7745 		icl_dsi_init(dev_priv);
7746 	} else if (IS_ALDERLAKE_S(dev_priv)) {
7747 		intel_ddi_init(dev_priv, PORT_A);
7748 		intel_ddi_init(dev_priv, PORT_TC1);
7749 		intel_ddi_init(dev_priv, PORT_TC2);
7750 		intel_ddi_init(dev_priv, PORT_TC3);
7751 		intel_ddi_init(dev_priv, PORT_TC4);
7752 	} else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
7753 		intel_ddi_init(dev_priv, PORT_A);
7754 		intel_ddi_init(dev_priv, PORT_B);
7755 		intel_ddi_init(dev_priv, PORT_TC1);
7756 		intel_ddi_init(dev_priv, PORT_TC2);
7757 	} else if (DISPLAY_VER(dev_priv) >= 12) {
7758 		intel_ddi_init(dev_priv, PORT_A);
7759 		intel_ddi_init(dev_priv, PORT_B);
7760 		intel_ddi_init(dev_priv, PORT_TC1);
7761 		intel_ddi_init(dev_priv, PORT_TC2);
7762 		intel_ddi_init(dev_priv, PORT_TC3);
7763 		intel_ddi_init(dev_priv, PORT_TC4);
7764 		intel_ddi_init(dev_priv, PORT_TC5);
7765 		intel_ddi_init(dev_priv, PORT_TC6);
7766 		icl_dsi_init(dev_priv);
7767 	} else if (IS_JSL_EHL(dev_priv)) {
7768 		intel_ddi_init(dev_priv, PORT_A);
7769 		intel_ddi_init(dev_priv, PORT_B);
7770 		intel_ddi_init(dev_priv, PORT_C);
7771 		intel_ddi_init(dev_priv, PORT_D);
7772 		icl_dsi_init(dev_priv);
7773 	} else if (DISPLAY_VER(dev_priv) == 11) {
7774 		intel_ddi_init(dev_priv, PORT_A);
7775 		intel_ddi_init(dev_priv, PORT_B);
7776 		intel_ddi_init(dev_priv, PORT_C);
7777 		intel_ddi_init(dev_priv, PORT_D);
7778 		intel_ddi_init(dev_priv, PORT_E);
7779 		intel_ddi_init(dev_priv, PORT_F);
7780 		icl_dsi_init(dev_priv);
7781 	} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
7782 		intel_ddi_init(dev_priv, PORT_A);
7783 		intel_ddi_init(dev_priv, PORT_B);
7784 		intel_ddi_init(dev_priv, PORT_C);
7785 		vlv_dsi_init(dev_priv);
7786 	} else if (DISPLAY_VER(dev_priv) >= 9) {
7787 		intel_ddi_init(dev_priv, PORT_A);
7788 		intel_ddi_init(dev_priv, PORT_B);
7789 		intel_ddi_init(dev_priv, PORT_C);
7790 		intel_ddi_init(dev_priv, PORT_D);
7791 		intel_ddi_init(dev_priv, PORT_E);
7792 	} else if (HAS_DDI(dev_priv)) {
7793 		u32 found;
7794 
7795 		if (intel_ddi_crt_present(dev_priv))
7796 			intel_crt_init(dev_priv);
7797 
7798 		/* Haswell uses DDI functions to detect digital outputs. */
7799 		found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
7800 		if (found)
7801 			intel_ddi_init(dev_priv, PORT_A);
7802 
7803 		found = intel_de_read(dev_priv, SFUSE_STRAP);
7804 		if (found & SFUSE_STRAP_DDIB_DETECTED)
7805 			intel_ddi_init(dev_priv, PORT_B);
7806 		if (found & SFUSE_STRAP_DDIC_DETECTED)
7807 			intel_ddi_init(dev_priv, PORT_C);
7808 		if (found & SFUSE_STRAP_DDID_DETECTED)
7809 			intel_ddi_init(dev_priv, PORT_D);
7810 		if (found & SFUSE_STRAP_DDIF_DETECTED)
7811 			intel_ddi_init(dev_priv, PORT_F);
7812 	} else if (HAS_PCH_SPLIT(dev_priv)) {
7813 		int found;
7814 
7815 		/*
7816 		 * intel_edp_init_connector() depends on this completing first,
7817 		 * to prevent the registration of both eDP and LVDS and the
7818 		 * incorrect sharing of the PPS.
7819 		 */
7820 		intel_lvds_init(dev_priv);
7821 		intel_crt_init(dev_priv);
7822 
7823 		dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
7824 
7825 		if (ilk_has_edp_a(dev_priv))
7826 			g4x_dp_init(dev_priv, DP_A, PORT_A);
7827 
7828 		if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) {
7829 			/* PCH SDVOB multiplex with HDMIB */
7830 			found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
7831 			if (!found)
7832 				g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
7833 			if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED))
7834 				g4x_dp_init(dev_priv, PCH_DP_B, PORT_B);
7835 		}
7836 
7837 		if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
7838 			g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
7839 
7840 		if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED)
7841 			g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
7842 
7843 		if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
7844 			g4x_dp_init(dev_priv, PCH_DP_C, PORT_C);
7845 
7846 		if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
7847 			g4x_dp_init(dev_priv, PCH_DP_D, PORT_D);
7848 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7849 		bool has_edp, has_port;
7850 
7851 		if (IS_VALLEYVIEW(dev_priv) && dev_priv->display.vbt.int_crt_support)
7852 			intel_crt_init(dev_priv);
7853 
7854 		/*
7855 		 * The DP_DETECTED bit is the latched state of the DDC
7856 		 * SDA pin at boot. However since eDP doesn't require DDC
7857 		 * (no way to plug in a DP->HDMI dongle) the DDC pins for
7858 		 * eDP ports may have been muxed to an alternate function.
7859 		 * Thus we can't rely on the DP_DETECTED bit alone to detect
7860 		 * eDP ports. Consult the VBT as well as DP_DETECTED to
7861 		 * detect eDP ports.
7862 		 *
7863 		 * Sadly the straps seem to be missing sometimes even for HDMI
7864 		 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
7865 		 * and VBT for the presence of the port. Additionally we can't
7866 		 * trust the port type the VBT declares as we've seen at least
7867 		 * HDMI ports that the VBT claim are DP or eDP.
7868 		 */
7869 		has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
7870 		has_port = intel_bios_is_port_present(dev_priv, PORT_B);
7871 		if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
7872 			has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B);
7873 		if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
7874 			g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
7875 
7876 		has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
7877 		has_port = intel_bios_is_port_present(dev_priv, PORT_C);
7878 		if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
7879 			has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C);
7880 		if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
7881 			g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
7882 
7883 		if (IS_CHERRYVIEW(dev_priv)) {
7884 			/*
7885 			 * eDP not supported on port D,
7886 			 * so no need to worry about it
7887 			 */
7888 			has_port = intel_bios_is_port_present(dev_priv, PORT_D);
7889 			if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port)
7890 				g4x_dp_init(dev_priv, CHV_DP_D, PORT_D);
7891 			if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)
7892 				g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
7893 		}
7894 
7895 		vlv_dsi_init(dev_priv);
7896 	} else if (IS_PINEVIEW(dev_priv)) {
7897 		intel_lvds_init(dev_priv);
7898 		intel_crt_init(dev_priv);
7899 	} else if (IS_DISPLAY_VER(dev_priv, 3, 4)) {
7900 		bool found = false;
7901 
7902 		if (IS_MOBILE(dev_priv))
7903 			intel_lvds_init(dev_priv);
7904 
7905 		intel_crt_init(dev_priv);
7906 
7907 		if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
7908 			drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
7909 			found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
7910 			if (!found && IS_G4X(dev_priv)) {
7911 				drm_dbg_kms(&dev_priv->drm,
7912 					    "probing HDMI on SDVOB\n");
7913 				g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
7914 			}
7915 
7916 			if (!found && IS_G4X(dev_priv))
7917 				g4x_dp_init(dev_priv, DP_B, PORT_B);
7918 		}
7919 
7920 		/* Before G4X SDVOC doesn't have its own detect register */
7921 
7922 		if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
7923 			drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");
7924 			found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
7925 		}
7926 
7927 		if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) {
7928 
7929 			if (IS_G4X(dev_priv)) {
7930 				drm_dbg_kms(&dev_priv->drm,
7931 					    "probing HDMI on SDVOC\n");
7932 				g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
7933 			}
7934 			if (IS_G4X(dev_priv))
7935 				g4x_dp_init(dev_priv, DP_C, PORT_C);
7936 		}
7937 
7938 		if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED))
7939 			g4x_dp_init(dev_priv, DP_D, PORT_D);
7940 
7941 		if (SUPPORTS_TV(dev_priv))
7942 			intel_tv_init(dev_priv);
7943 	} else if (DISPLAY_VER(dev_priv) == 2) {
7944 		if (IS_I85X(dev_priv))
7945 			intel_lvds_init(dev_priv);
7946 
7947 		intel_crt_init(dev_priv);
7948 		intel_dvo_init(dev_priv);
7949 	}
7950 
7951 	for_each_intel_encoder(&dev_priv->drm, encoder) {
7952 		encoder->base.possible_crtcs =
7953 			intel_encoder_possible_crtcs(encoder);
7954 		encoder->base.possible_clones =
7955 			intel_encoder_possible_clones(encoder);
7956 	}
7957 
7958 	intel_init_pch_refclk(dev_priv);
7959 
7960 	drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
7961 }
7962 
7963 static int max_dotclock(struct drm_i915_private *i915)
7964 {
7965 	int max_dotclock = i915->max_dotclk_freq;
7966 
7967 	/* icl+ might use bigjoiner */
7968 	if (DISPLAY_VER(i915) >= 11)
7969 		max_dotclock *= 2;
7970 
7971 	return max_dotclock;
7972 }
7973 
7974 static enum drm_mode_status
7975 intel_mode_valid(struct drm_device *dev,
7976 		 const struct drm_display_mode *mode)
7977 {
7978 	struct drm_i915_private *dev_priv = to_i915(dev);
7979 	int hdisplay_max, htotal_max;
7980 	int vdisplay_max, vtotal_max;
7981 
7982 	/*
7983 	 * Can't reject DBLSCAN here because Xorg ddxen can add piles
7984 	 * of DBLSCAN modes to the output's mode list when they detect
7985 	 * the scaling mode property on the connector. And they don't
7986 	 * ask the kernel to validate those modes in any way until
7987 	 * modeset time at which point the client gets a protocol error.
7988 	 * So in order to not upset those clients we silently ignore the
7989 	 * DBLSCAN flag on such connectors. For other connectors we will
7990 	 * reject modes with the DBLSCAN flag in encoder->compute_config().
7991 	 * And we always reject DBLSCAN modes in connector->mode_valid()
7992 	 * as we never want such modes on the connector's mode list.
7993 	 */
7994 
7995 	if (mode->vscan > 1)
7996 		return MODE_NO_VSCAN;
7997 
7998 	if (mode->flags & DRM_MODE_FLAG_HSKEW)
7999 		return MODE_H_ILLEGAL;
8000 
8001 	if (mode->flags & (DRM_MODE_FLAG_CSYNC |
8002 			   DRM_MODE_FLAG_NCSYNC |
8003 			   DRM_MODE_FLAG_PCSYNC))
8004 		return MODE_HSYNC;
8005 
8006 	if (mode->flags & (DRM_MODE_FLAG_BCAST |
8007 			   DRM_MODE_FLAG_PIXMUX |
8008 			   DRM_MODE_FLAG_CLKDIV2))
8009 		return MODE_BAD;
8010 
8011 	/*
8012 	 * Reject clearly excessive dotclocks early to
8013 	 * avoid having to worry about huge integers later.
8014 	 */
8015 	if (mode->clock > max_dotclock(dev_priv))
8016 		return MODE_CLOCK_HIGH;
8017 
8018 	/* Transcoder timing limits */
8019 	if (DISPLAY_VER(dev_priv) >= 11) {
8020 		hdisplay_max = 16384;
8021 		vdisplay_max = 8192;
8022 		htotal_max = 16384;
8023 		vtotal_max = 8192;
8024 	} else if (DISPLAY_VER(dev_priv) >= 9 ||
8025 		   IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
8026 		hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
8027 		vdisplay_max = 4096;
8028 		htotal_max = 8192;
8029 		vtotal_max = 8192;
8030 	} else if (DISPLAY_VER(dev_priv) >= 3) {
8031 		hdisplay_max = 4096;
8032 		vdisplay_max = 4096;
8033 		htotal_max = 8192;
8034 		vtotal_max = 8192;
8035 	} else {
8036 		hdisplay_max = 2048;
8037 		vdisplay_max = 2048;
8038 		htotal_max = 4096;
8039 		vtotal_max = 4096;
8040 	}
8041 
8042 	if (mode->hdisplay > hdisplay_max ||
8043 	    mode->hsync_start > htotal_max ||
8044 	    mode->hsync_end > htotal_max ||
8045 	    mode->htotal > htotal_max)
8046 		return MODE_H_ILLEGAL;
8047 
8048 	if (mode->vdisplay > vdisplay_max ||
8049 	    mode->vsync_start > vtotal_max ||
8050 	    mode->vsync_end > vtotal_max ||
8051 	    mode->vtotal > vtotal_max)
8052 		return MODE_V_ILLEGAL;
8053 
8054 	if (DISPLAY_VER(dev_priv) >= 5) {
8055 		if (mode->hdisplay < 64 ||
8056 		    mode->htotal - mode->hdisplay < 32)
8057 			return MODE_H_ILLEGAL;
8058 
8059 		if (mode->vtotal - mode->vdisplay < 5)
8060 			return MODE_V_ILLEGAL;
8061 	} else {
8062 		if (mode->htotal - mode->hdisplay < 32)
8063 			return MODE_H_ILLEGAL;
8064 
8065 		if (mode->vtotal - mode->vdisplay < 3)
8066 			return MODE_V_ILLEGAL;
8067 	}
8068 
8069 	/*
8070 	 * Cantiga+ cannot handle modes with a hsync front porch of 0.
8071 	 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
8072 	 */
8073 	if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) &&
8074 	    mode->hsync_start == mode->hdisplay)
8075 		return MODE_H_ILLEGAL;
8076 
8077 	return MODE_OK;
8078 }
8079 
8080 enum drm_mode_status
8081 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
8082 				const struct drm_display_mode *mode,
8083 				bool bigjoiner)
8084 {
8085 	int plane_width_max, plane_height_max;
8086 
8087 	/*
8088 	 * intel_mode_valid() should be
8089 	 * sufficient on older platforms.
8090 	 */
8091 	if (DISPLAY_VER(dev_priv) < 9)
8092 		return MODE_OK;
8093 
8094 	/*
8095 	 * Most people will probably want a fullscreen
8096 	 * plane so let's not advertize modes that are
8097 	 * too big for that.
8098 	 */
8099 	if (DISPLAY_VER(dev_priv) >= 11) {
8100 		plane_width_max = 5120 << bigjoiner;
8101 		plane_height_max = 4320;
8102 	} else {
8103 		plane_width_max = 5120;
8104 		plane_height_max = 4096;
8105 	}
8106 
8107 	if (mode->hdisplay > plane_width_max)
8108 		return MODE_H_ILLEGAL;
8109 
8110 	if (mode->vdisplay > plane_height_max)
8111 		return MODE_V_ILLEGAL;
8112 
8113 	return MODE_OK;
8114 }
8115 
8116 static const struct drm_mode_config_funcs intel_mode_funcs = {
8117 	.fb_create = intel_user_framebuffer_create,
8118 	.get_format_info = intel_fb_get_format_info,
8119 	.output_poll_changed = intel_fbdev_output_poll_changed,
8120 	.mode_valid = intel_mode_valid,
8121 	.atomic_check = intel_atomic_check,
8122 	.atomic_commit = intel_atomic_commit,
8123 	.atomic_state_alloc = intel_atomic_state_alloc,
8124 	.atomic_state_clear = intel_atomic_state_clear,
8125 	.atomic_state_free = intel_atomic_state_free,
8126 };
8127 
8128 static const struct intel_display_funcs skl_display_funcs = {
8129 	.get_pipe_config = hsw_get_pipe_config,
8130 	.crtc_enable = hsw_crtc_enable,
8131 	.crtc_disable = hsw_crtc_disable,
8132 	.commit_modeset_enables = skl_commit_modeset_enables,
8133 	.get_initial_plane_config = skl_get_initial_plane_config,
8134 };
8135 
8136 static const struct intel_display_funcs ddi_display_funcs = {
8137 	.get_pipe_config = hsw_get_pipe_config,
8138 	.crtc_enable = hsw_crtc_enable,
8139 	.crtc_disable = hsw_crtc_disable,
8140 	.commit_modeset_enables = intel_commit_modeset_enables,
8141 	.get_initial_plane_config = i9xx_get_initial_plane_config,
8142 };
8143 
8144 static const struct intel_display_funcs pch_split_display_funcs = {
8145 	.get_pipe_config = ilk_get_pipe_config,
8146 	.crtc_enable = ilk_crtc_enable,
8147 	.crtc_disable = ilk_crtc_disable,
8148 	.commit_modeset_enables = intel_commit_modeset_enables,
8149 	.get_initial_plane_config = i9xx_get_initial_plane_config,
8150 };
8151 
8152 static const struct intel_display_funcs vlv_display_funcs = {
8153 	.get_pipe_config = i9xx_get_pipe_config,
8154 	.crtc_enable = valleyview_crtc_enable,
8155 	.crtc_disable = i9xx_crtc_disable,
8156 	.commit_modeset_enables = intel_commit_modeset_enables,
8157 	.get_initial_plane_config = i9xx_get_initial_plane_config,
8158 };
8159 
8160 static const struct intel_display_funcs i9xx_display_funcs = {
8161 	.get_pipe_config = i9xx_get_pipe_config,
8162 	.crtc_enable = i9xx_crtc_enable,
8163 	.crtc_disable = i9xx_crtc_disable,
8164 	.commit_modeset_enables = intel_commit_modeset_enables,
8165 	.get_initial_plane_config = i9xx_get_initial_plane_config,
8166 };
8167 
8168 /**
8169  * intel_init_display_hooks - initialize the display modesetting hooks
8170  * @dev_priv: device private
8171  */
8172 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
8173 {
8174 	if (!HAS_DISPLAY(dev_priv))
8175 		return;
8176 
8177 	intel_color_init_hooks(dev_priv);
8178 	intel_init_cdclk_hooks(dev_priv);
8179 	intel_audio_hooks_init(dev_priv);
8180 
8181 	intel_dpll_init_clock_hook(dev_priv);
8182 
8183 	if (DISPLAY_VER(dev_priv) >= 9) {
8184 		dev_priv->display.funcs.display = &skl_display_funcs;
8185 	} else if (HAS_DDI(dev_priv)) {
8186 		dev_priv->display.funcs.display = &ddi_display_funcs;
8187 	} else if (HAS_PCH_SPLIT(dev_priv)) {
8188 		dev_priv->display.funcs.display = &pch_split_display_funcs;
8189 	} else if (IS_CHERRYVIEW(dev_priv) ||
8190 		   IS_VALLEYVIEW(dev_priv)) {
8191 		dev_priv->display.funcs.display = &vlv_display_funcs;
8192 	} else {
8193 		dev_priv->display.funcs.display = &i9xx_display_funcs;
8194 	}
8195 
8196 	intel_fdi_init_hook(dev_priv);
8197 }
8198 
8199 void intel_modeset_init_hw(struct drm_i915_private *i915)
8200 {
8201 	struct intel_cdclk_state *cdclk_state;
8202 
8203 	if (!HAS_DISPLAY(i915))
8204 		return;
8205 
8206 	cdclk_state = to_intel_cdclk_state(i915->display.cdclk.obj.state);
8207 
8208 	intel_update_cdclk(i915);
8209 	intel_cdclk_dump_config(i915, &i915->display.cdclk.hw, "Current CDCLK");
8210 	cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw;
8211 }
8212 
8213 static int intel_initial_commit(struct drm_device *dev)
8214 {
8215 	struct drm_atomic_state *state = NULL;
8216 	struct drm_modeset_acquire_ctx ctx;
8217 	struct intel_crtc *crtc;
8218 	int ret = 0;
8219 
8220 	state = drm_atomic_state_alloc(dev);
8221 	if (!state)
8222 		return -ENOMEM;
8223 
8224 	drm_modeset_acquire_init(&ctx, 0);
8225 
8226 retry:
8227 	state->acquire_ctx = &ctx;
8228 
8229 	for_each_intel_crtc(dev, crtc) {
8230 		struct intel_crtc_state *crtc_state =
8231 			intel_atomic_get_crtc_state(state, crtc);
8232 
8233 		if (IS_ERR(crtc_state)) {
8234 			ret = PTR_ERR(crtc_state);
8235 			goto out;
8236 		}
8237 
8238 		if (crtc_state->hw.active) {
8239 			struct intel_encoder *encoder;
8240 
8241 			/*
8242 			 * We've not yet detected sink capabilities
8243 			 * (audio,infoframes,etc.) and thus we don't want to
8244 			 * force a full state recomputation yet. We want that to
8245 			 * happen only for the first real commit from userspace.
8246 			 * So preserve the inherited flag for the time being.
8247 			 */
8248 			crtc_state->inherited = true;
8249 
8250 			ret = drm_atomic_add_affected_planes(state, &crtc->base);
8251 			if (ret)
8252 				goto out;
8253 
8254 			/*
8255 			 * FIXME hack to force a LUT update to avoid the
8256 			 * plane update forcing the pipe gamma on without
8257 			 * having a proper LUT loaded. Remove once we
8258 			 * have readout for pipe gamma enable.
8259 			 */
8260 			crtc_state->uapi.color_mgmt_changed = true;
8261 
8262 			for_each_intel_encoder_mask(dev, encoder,
8263 						    crtc_state->uapi.encoder_mask) {
8264 				if (encoder->initial_fastset_check &&
8265 				    !encoder->initial_fastset_check(encoder, crtc_state)) {
8266 					ret = drm_atomic_add_affected_connectors(state,
8267 										 &crtc->base);
8268 					if (ret)
8269 						goto out;
8270 				}
8271 			}
8272 		}
8273 	}
8274 
8275 	ret = drm_atomic_commit(state);
8276 
8277 out:
8278 	if (ret == -EDEADLK) {
8279 		drm_atomic_state_clear(state);
8280 		drm_modeset_backoff(&ctx);
8281 		goto retry;
8282 	}
8283 
8284 	drm_atomic_state_put(state);
8285 
8286 	drm_modeset_drop_locks(&ctx);
8287 	drm_modeset_acquire_fini(&ctx);
8288 
8289 	return ret;
8290 }
8291 
8292 static const struct drm_mode_config_helper_funcs intel_mode_config_funcs = {
8293 	.atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
8294 };
8295 
8296 static void intel_mode_config_init(struct drm_i915_private *i915)
8297 {
8298 	struct drm_mode_config *mode_config = &i915->drm.mode_config;
8299 
8300 	drm_mode_config_init(&i915->drm);
8301 	INIT_LIST_HEAD(&i915->display.global.obj_list);
8302 
8303 	mode_config->min_width = 0;
8304 	mode_config->min_height = 0;
8305 
8306 	mode_config->preferred_depth = 24;
8307 	mode_config->prefer_shadow = 1;
8308 
8309 	mode_config->funcs = &intel_mode_funcs;
8310 	mode_config->helper_private = &intel_mode_config_funcs;
8311 
8312 	mode_config->async_page_flip = HAS_ASYNC_FLIPS(i915);
8313 
8314 	/*
8315 	 * Maximum framebuffer dimensions, chosen to match
8316 	 * the maximum render engine surface size on gen4+.
8317 	 */
8318 	if (DISPLAY_VER(i915) >= 7) {
8319 		mode_config->max_width = 16384;
8320 		mode_config->max_height = 16384;
8321 	} else if (DISPLAY_VER(i915) >= 4) {
8322 		mode_config->max_width = 8192;
8323 		mode_config->max_height = 8192;
8324 	} else if (DISPLAY_VER(i915) == 3) {
8325 		mode_config->max_width = 4096;
8326 		mode_config->max_height = 4096;
8327 	} else {
8328 		mode_config->max_width = 2048;
8329 		mode_config->max_height = 2048;
8330 	}
8331 
8332 	if (IS_I845G(i915) || IS_I865G(i915)) {
8333 		mode_config->cursor_width = IS_I845G(i915) ? 64 : 512;
8334 		mode_config->cursor_height = 1023;
8335 	} else if (IS_I830(i915) || IS_I85X(i915) ||
8336 		   IS_I915G(i915) || IS_I915GM(i915)) {
8337 		mode_config->cursor_width = 64;
8338 		mode_config->cursor_height = 64;
8339 	} else {
8340 		mode_config->cursor_width = 256;
8341 		mode_config->cursor_height = 256;
8342 	}
8343 }
8344 
8345 static void intel_mode_config_cleanup(struct drm_i915_private *i915)
8346 {
8347 	intel_atomic_global_obj_cleanup(i915);
8348 	drm_mode_config_cleanup(&i915->drm);
8349 }
8350 
8351 /* part #1: call before irq install */
8352 int intel_modeset_init_noirq(struct drm_i915_private *i915)
8353 {
8354 	int ret;
8355 
8356 	if (i915_inject_probe_failure(i915))
8357 		return -ENODEV;
8358 
8359 	if (HAS_DISPLAY(i915)) {
8360 		ret = drm_vblank_init(&i915->drm,
8361 				      INTEL_NUM_PIPES(i915));
8362 		if (ret)
8363 			return ret;
8364 	}
8365 
8366 	intel_bios_init(i915);
8367 
8368 	ret = intel_vga_register(i915);
8369 	if (ret)
8370 		goto cleanup_bios;
8371 
8372 	/* FIXME: completely on the wrong abstraction layer */
8373 	ret = intel_power_domains_init(i915);
8374 	if (ret < 0)
8375 		goto cleanup_vga;
8376 
8377 	intel_power_domains_init_hw(i915, false);
8378 
8379 	if (!HAS_DISPLAY(i915))
8380 		return 0;
8381 
8382 	intel_dmc_init(i915);
8383 
8384 	i915->display.wq.modeset = alloc_ordered_workqueue("i915_modeset", 0);
8385 	i915->display.wq.flip = alloc_workqueue("i915_flip", WQ_HIGHPRI |
8386 						WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
8387 
8388 	intel_mode_config_init(i915);
8389 
8390 	ret = intel_cdclk_init(i915);
8391 	if (ret)
8392 		goto cleanup_vga_client_pw_domain_dmc;
8393 
8394 	ret = intel_color_init(i915);
8395 	if (ret)
8396 		goto cleanup_vga_client_pw_domain_dmc;
8397 
8398 	ret = intel_dbuf_init(i915);
8399 	if (ret)
8400 		goto cleanup_vga_client_pw_domain_dmc;
8401 
8402 	ret = intel_bw_init(i915);
8403 	if (ret)
8404 		goto cleanup_vga_client_pw_domain_dmc;
8405 
8406 	init_llist_head(&i915->display.atomic_helper.free_list);
8407 	INIT_WORK(&i915->display.atomic_helper.free_work,
8408 		  intel_atomic_helper_free_state_worker);
8409 
8410 	intel_init_quirks(i915);
8411 
8412 	intel_fbc_init(i915);
8413 
8414 	return 0;
8415 
8416 cleanup_vga_client_pw_domain_dmc:
8417 	intel_dmc_fini(i915);
8418 	intel_power_domains_driver_remove(i915);
8419 cleanup_vga:
8420 	intel_vga_unregister(i915);
8421 cleanup_bios:
8422 	intel_bios_driver_remove(i915);
8423 
8424 	return ret;
8425 }
8426 
8427 /* part #2: call after irq install, but before gem init */
8428 int intel_modeset_init_nogem(struct drm_i915_private *i915)
8429 {
8430 	struct drm_device *dev = &i915->drm;
8431 	enum pipe pipe;
8432 	struct intel_crtc *crtc;
8433 	int ret;
8434 
8435 	if (!HAS_DISPLAY(i915))
8436 		return 0;
8437 
8438 	intel_wm_init(i915);
8439 
8440 	intel_panel_sanitize_ssc(i915);
8441 
8442 	intel_pps_setup(i915);
8443 
8444 	intel_gmbus_setup(i915);
8445 
8446 	drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n",
8447 		    INTEL_NUM_PIPES(i915),
8448 		    INTEL_NUM_PIPES(i915) > 1 ? "s" : "");
8449 
8450 	for_each_pipe(i915, pipe) {
8451 		ret = intel_crtc_init(i915, pipe);
8452 		if (ret) {
8453 			intel_mode_config_cleanup(i915);
8454 			return ret;
8455 		}
8456 	}
8457 
8458 	intel_plane_possible_crtcs_init(i915);
8459 	intel_shared_dpll_init(i915);
8460 	intel_fdi_pll_freq_update(i915);
8461 
8462 	intel_update_czclk(i915);
8463 	intel_modeset_init_hw(i915);
8464 	intel_dpll_update_ref_clks(i915);
8465 
8466 	intel_hdcp_component_init(i915);
8467 
8468 	if (i915->display.cdclk.max_cdclk_freq == 0)
8469 		intel_update_max_cdclk(i915);
8470 
8471 	intel_hti_init(i915);
8472 
8473 	/* Just disable it once at startup */
8474 	intel_vga_disable(i915);
8475 	intel_setup_outputs(i915);
8476 
8477 	drm_modeset_lock_all(dev);
8478 	intel_modeset_setup_hw_state(i915, dev->mode_config.acquire_ctx);
8479 	intel_acpi_assign_connector_fwnodes(i915);
8480 	drm_modeset_unlock_all(dev);
8481 
8482 	for_each_intel_crtc(dev, crtc) {
8483 		if (!to_intel_crtc_state(crtc->base.state)->uapi.active)
8484 			continue;
8485 		intel_crtc_initial_plane_config(crtc);
8486 	}
8487 
8488 	/*
8489 	 * Make sure hardware watermarks really match the state we read out.
8490 	 * Note that we need to do this after reconstructing the BIOS fb's
8491 	 * since the watermark calculation done here will use pstate->fb.
8492 	 */
8493 	if (!HAS_GMCH(i915))
8494 		ilk_wm_sanitize(i915);
8495 
8496 	return 0;
8497 }
8498 
8499 /* part #3: call after gem init */
8500 int intel_modeset_init(struct drm_i915_private *i915)
8501 {
8502 	int ret;
8503 
8504 	if (!HAS_DISPLAY(i915))
8505 		return 0;
8506 
8507 	/*
8508 	 * Force all active planes to recompute their states. So that on
8509 	 * mode_setcrtc after probe, all the intel_plane_state variables
8510 	 * are already calculated and there is no assert_plane warnings
8511 	 * during bootup.
8512 	 */
8513 	ret = intel_initial_commit(&i915->drm);
8514 	if (ret)
8515 		drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret);
8516 
8517 	intel_overlay_setup(i915);
8518 
8519 	ret = intel_fbdev_init(&i915->drm);
8520 	if (ret)
8521 		return ret;
8522 
8523 	/* Only enable hotplug handling once the fbdev is fully set up. */
8524 	intel_hpd_init(i915);
8525 	intel_hpd_poll_disable(i915);
8526 
8527 	skl_watermark_ipc_init(i915);
8528 
8529 	return 0;
8530 }
8531 
8532 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
8533 {
8534 	struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
8535 	enum transcoder cpu_transcoder = (enum transcoder)pipe;
8536 	/* 640x480@60Hz, ~25175 kHz */
8537 	struct dpll clock = {
8538 		.m1 = 18,
8539 		.m2 = 7,
8540 		.p1 = 13,
8541 		.p2 = 4,
8542 		.n = 2,
8543 	};
8544 	u32 dpll, fp;
8545 	int i;
8546 
8547 	drm_WARN_ON(&dev_priv->drm,
8548 		    i9xx_calc_dpll_params(48000, &clock) != 25154);
8549 
8550 	drm_dbg_kms(&dev_priv->drm,
8551 		    "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
8552 		    pipe_name(pipe), clock.vco, clock.dot);
8553 
8554 	fp = i9xx_dpll_compute_fp(&clock);
8555 	dpll = DPLL_DVO_2X_MODE |
8556 		DPLL_VGA_MODE_DIS |
8557 		((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
8558 		PLL_P2_DIVIDE_BY_4 |
8559 		PLL_REF_INPUT_DREFCLK |
8560 		DPLL_VCO_ENABLE;
8561 
8562 	intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder),
8563 		       HACTIVE(640 - 1) | HTOTAL(800 - 1));
8564 	intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
8565 		       HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
8566 	intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
8567 		       HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
8568 	intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
8569 		       VACTIVE(480 - 1) | VTOTAL(525 - 1));
8570 	intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
8571 		       VBLANK_START(480 - 1) | VBLANK_END(525 - 1));
8572 	intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
8573 		       VSYNC_START(490 - 1) | VSYNC_END(492 - 1));
8574 	intel_de_write(dev_priv, PIPESRC(pipe),
8575 		       PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1));
8576 
8577 	intel_de_write(dev_priv, FP0(pipe), fp);
8578 	intel_de_write(dev_priv, FP1(pipe), fp);
8579 
8580 	/*
8581 	 * Apparently we need to have VGA mode enabled prior to changing
8582 	 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
8583 	 * dividers, even though the register value does change.
8584 	 */
8585 	intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
8586 	intel_de_write(dev_priv, DPLL(pipe), dpll);
8587 
8588 	/* Wait for the clocks to stabilize. */
8589 	intel_de_posting_read(dev_priv, DPLL(pipe));
8590 	udelay(150);
8591 
8592 	/* The pixel multiplier can only be updated once the
8593 	 * DPLL is enabled and the clocks are stable.
8594 	 *
8595 	 * So write it again.
8596 	 */
8597 	intel_de_write(dev_priv, DPLL(pipe), dpll);
8598 
8599 	/* We do this three times for luck */
8600 	for (i = 0; i < 3 ; i++) {
8601 		intel_de_write(dev_priv, DPLL(pipe), dpll);
8602 		intel_de_posting_read(dev_priv, DPLL(pipe));
8603 		udelay(150); /* wait for warmup */
8604 	}
8605 
8606 	intel_de_write(dev_priv, TRANSCONF(pipe), TRANSCONF_ENABLE);
8607 	intel_de_posting_read(dev_priv, TRANSCONF(pipe));
8608 
8609 	intel_wait_for_pipe_scanline_moving(crtc);
8610 }
8611 
8612 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
8613 {
8614 	struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
8615 
8616 	drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",
8617 		    pipe_name(pipe));
8618 
8619 	drm_WARN_ON(&dev_priv->drm,
8620 		    intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE);
8621 	drm_WARN_ON(&dev_priv->drm,
8622 		    intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE);
8623 	drm_WARN_ON(&dev_priv->drm,
8624 		    intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE);
8625 	drm_WARN_ON(&dev_priv->drm,
8626 		    intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK);
8627 	drm_WARN_ON(&dev_priv->drm,
8628 		    intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK);
8629 
8630 	intel_de_write(dev_priv, TRANSCONF(pipe), 0);
8631 	intel_de_posting_read(dev_priv, TRANSCONF(pipe));
8632 
8633 	intel_wait_for_pipe_scanline_stopped(crtc);
8634 
8635 	intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
8636 	intel_de_posting_read(dev_priv, DPLL(pipe));
8637 }
8638 
8639 void intel_display_resume(struct drm_device *dev)
8640 {
8641 	struct drm_i915_private *i915 = to_i915(dev);
8642 	struct drm_atomic_state *state = i915->display.restore.modeset_state;
8643 	struct drm_modeset_acquire_ctx ctx;
8644 	int ret;
8645 
8646 	if (!HAS_DISPLAY(i915))
8647 		return;
8648 
8649 	i915->display.restore.modeset_state = NULL;
8650 	if (state)
8651 		state->acquire_ctx = &ctx;
8652 
8653 	drm_modeset_acquire_init(&ctx, 0);
8654 
8655 	while (1) {
8656 		ret = drm_modeset_lock_all_ctx(dev, &ctx);
8657 		if (ret != -EDEADLK)
8658 			break;
8659 
8660 		drm_modeset_backoff(&ctx);
8661 	}
8662 
8663 	if (!ret)
8664 		ret = __intel_display_resume(i915, state, &ctx);
8665 
8666 	skl_watermark_ipc_update(i915);
8667 	drm_modeset_drop_locks(&ctx);
8668 	drm_modeset_acquire_fini(&ctx);
8669 
8670 	if (ret)
8671 		drm_err(&i915->drm,
8672 			"Restoring old state failed with %i\n", ret);
8673 	if (state)
8674 		drm_atomic_state_put(state);
8675 }
8676 
8677 static void intel_hpd_poll_fini(struct drm_i915_private *i915)
8678 {
8679 	struct intel_connector *connector;
8680 	struct drm_connector_list_iter conn_iter;
8681 
8682 	/* Kill all the work that may have been queued by hpd. */
8683 	drm_connector_list_iter_begin(&i915->drm, &conn_iter);
8684 	for_each_intel_connector_iter(connector, &conn_iter) {
8685 		if (connector->modeset_retry_work.func)
8686 			cancel_work_sync(&connector->modeset_retry_work);
8687 		if (connector->hdcp.shim) {
8688 			cancel_delayed_work_sync(&connector->hdcp.check_work);
8689 			cancel_work_sync(&connector->hdcp.prop_work);
8690 		}
8691 	}
8692 	drm_connector_list_iter_end(&conn_iter);
8693 }
8694 
8695 /* part #1: call before irq uninstall */
8696 void intel_modeset_driver_remove(struct drm_i915_private *i915)
8697 {
8698 	if (!HAS_DISPLAY(i915))
8699 		return;
8700 
8701 	flush_workqueue(i915->display.wq.flip);
8702 	flush_workqueue(i915->display.wq.modeset);
8703 
8704 	flush_work(&i915->display.atomic_helper.free_work);
8705 	drm_WARN_ON(&i915->drm, !llist_empty(&i915->display.atomic_helper.free_list));
8706 
8707 	/*
8708 	 * MST topology needs to be suspended so we don't have any calls to
8709 	 * fbdev after it's finalized. MST will be destroyed later as part of
8710 	 * drm_mode_config_cleanup()
8711 	 */
8712 	intel_dp_mst_suspend(i915);
8713 }
8714 
8715 /* part #2: call after irq uninstall */
8716 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915)
8717 {
8718 	if (!HAS_DISPLAY(i915))
8719 		return;
8720 
8721 	/*
8722 	 * Due to the hpd irq storm handling the hotplug work can re-arm the
8723 	 * poll handlers. Hence disable polling after hpd handling is shut down.
8724 	 */
8725 	intel_hpd_poll_fini(i915);
8726 
8727 	/* poll work can call into fbdev, hence clean that up afterwards */
8728 	intel_fbdev_fini(i915);
8729 
8730 	intel_unregister_dsm_handler();
8731 
8732 	/* flush any delayed tasks or pending work */
8733 	flush_scheduled_work();
8734 
8735 	intel_hdcp_component_fini(i915);
8736 
8737 	intel_mode_config_cleanup(i915);
8738 
8739 	intel_overlay_cleanup(i915);
8740 
8741 	intel_gmbus_teardown(i915);
8742 
8743 	destroy_workqueue(i915->display.wq.flip);
8744 	destroy_workqueue(i915->display.wq.modeset);
8745 
8746 	intel_fbc_cleanup(i915);
8747 }
8748 
8749 /* part #3: call after gem init */
8750 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915)
8751 {
8752 	intel_dmc_fini(i915);
8753 
8754 	intel_power_domains_driver_remove(i915);
8755 
8756 	intel_vga_unregister(i915);
8757 
8758 	intel_bios_driver_remove(i915);
8759 }
8760 
8761 bool intel_modeset_probe_defer(struct pci_dev *pdev)
8762 {
8763 	struct drm_privacy_screen *privacy_screen;
8764 
8765 	/*
8766 	 * apple-gmux is needed on dual GPU MacBook Pro
8767 	 * to probe the panel if we're the inactive GPU.
8768 	 */
8769 	if (vga_switcheroo_client_probe_defer(pdev))
8770 		return true;
8771 
8772 	/* If the LCD panel has a privacy-screen, wait for it */
8773 	privacy_screen = drm_privacy_screen_get(&pdev->dev, NULL);
8774 	if (IS_ERR(privacy_screen) && PTR_ERR(privacy_screen) == -EPROBE_DEFER)
8775 		return true;
8776 
8777 	drm_privacy_screen_put(privacy_screen);
8778 
8779 	return false;
8780 }
8781 
8782 void intel_display_driver_register(struct drm_i915_private *i915)
8783 {
8784 	if (!HAS_DISPLAY(i915))
8785 		return;
8786 
8787 	/* Must be done after probing outputs */
8788 	intel_opregion_register(i915);
8789 	intel_acpi_video_register(i915);
8790 
8791 	intel_audio_init(i915);
8792 
8793 	intel_display_debugfs_register(i915);
8794 
8795 	/*
8796 	 * Some ports require correctly set-up hpd registers for
8797 	 * detection to work properly (leading to ghost connected
8798 	 * connector status), e.g. VGA on gm45.  Hence we can only set
8799 	 * up the initial fbdev config after hpd irqs are fully
8800 	 * enabled. We do it last so that the async config cannot run
8801 	 * before the connectors are registered.
8802 	 */
8803 	intel_fbdev_initial_config_async(i915);
8804 
8805 	/*
8806 	 * We need to coordinate the hotplugs with the asynchronous
8807 	 * fbdev configuration, for which we use the
8808 	 * fbdev->async_cookie.
8809 	 */
8810 	drm_kms_helper_poll_init(&i915->drm);
8811 }
8812 
8813 void intel_display_driver_unregister(struct drm_i915_private *i915)
8814 {
8815 	if (!HAS_DISPLAY(i915))
8816 		return;
8817 
8818 	intel_fbdev_unregister(i915);
8819 	intel_audio_deinit(i915);
8820 
8821 	/*
8822 	 * After flushing the fbdev (incl. a late async config which
8823 	 * will have delayed queuing of a hotplug event), then flush
8824 	 * the hotplug events.
8825 	 */
8826 	drm_kms_helper_poll_fini(&i915->drm);
8827 	drm_atomic_helper_shutdown(&i915->drm);
8828 
8829 	acpi_video_unregister();
8830 	intel_opregion_unregister(i915);
8831 }
8832 
8833 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915)
8834 {
8835 	return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915);
8836 }
8837