1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <linux/dma-resv.h> 28 #include <linux/i2c.h> 29 #include <linux/input.h> 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/slab.h> 33 #include <linux/string_helpers.h> 34 35 #include <drm/display/drm_dp_helper.h> 36 #include <drm/drm_atomic.h> 37 #include <drm/drm_atomic_helper.h> 38 #include <drm/drm_atomic_uapi.h> 39 #include <drm/drm_damage_helper.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_fourcc.h> 42 #include <drm/drm_probe_helper.h> 43 #include <drm/drm_rect.h> 44 45 #include "gem/i915_gem_lmem.h" 46 #include "gem/i915_gem_object.h" 47 48 #include "g4x_dp.h" 49 #include "g4x_hdmi.h" 50 #include "hsw_ips.h" 51 #include "i915_drv.h" 52 #include "i915_reg.h" 53 #include "i915_utils.h" 54 #include "i9xx_plane.h" 55 #include "i9xx_wm.h" 56 #include "intel_atomic.h" 57 #include "intel_atomic_plane.h" 58 #include "intel_audio.h" 59 #include "intel_bw.h" 60 #include "intel_cdclk.h" 61 #include "intel_clock_gating.h" 62 #include "intel_color.h" 63 #include "intel_crt.h" 64 #include "intel_crtc.h" 65 #include "intel_crtc_state_dump.h" 66 #include "intel_ddi.h" 67 #include "intel_de.h" 68 #include "intel_display_driver.h" 69 #include "intel_display_power.h" 70 #include "intel_display_types.h" 71 #include "intel_dmc.h" 72 #include "intel_dp.h" 73 #include "intel_dp_link_training.h" 74 #include "intel_dp_mst.h" 75 #include "intel_dpio_phy.h" 76 #include "intel_dpll.h" 77 #include "intel_dpll_mgr.h" 78 #include "intel_dpt.h" 79 #include "intel_drrs.h" 80 #include "intel_dsi.h" 81 #include "intel_dvo.h" 82 #include "intel_fb.h" 83 #include "intel_fbc.h" 84 #include "intel_fbdev.h" 85 #include "intel_fdi.h" 86 #include "intel_fifo_underrun.h" 87 #include "intel_frontbuffer.h" 88 #include "intel_hdmi.h" 89 #include "intel_hotplug.h" 90 #include "intel_lvds.h" 91 #include "intel_lvds_regs.h" 92 #include "intel_modeset_setup.h" 93 #include "intel_modeset_verify.h" 94 #include "intel_overlay.h" 95 #include "intel_panel.h" 96 #include "intel_pch_display.h" 97 #include "intel_pch_refclk.h" 98 #include "intel_pcode.h" 99 #include "intel_pipe_crc.h" 100 #include "intel_plane_initial.h" 101 #include "intel_pmdemand.h" 102 #include "intel_pps.h" 103 #include "intel_psr.h" 104 #include "intel_sdvo.h" 105 #include "intel_snps_phy.h" 106 #include "intel_tc.h" 107 #include "intel_tv.h" 108 #include "intel_vblank.h" 109 #include "intel_vdsc.h" 110 #include "intel_vdsc_regs.h" 111 #include "intel_vga.h" 112 #include "intel_vrr.h" 113 #include "intel_wm.h" 114 #include "skl_scaler.h" 115 #include "skl_universal_plane.h" 116 #include "skl_watermark.h" 117 #include "vlv_dsi.h" 118 #include "vlv_dsi_pll.h" 119 #include "vlv_dsi_regs.h" 120 #include "vlv_sideband.h" 121 122 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state); 123 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state); 124 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state); 125 static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state); 126 127 /* returns HPLL frequency in kHz */ 128 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) 129 { 130 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; 131 132 /* Obtain SKU information */ 133 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & 134 CCK_FUSE_HPLL_FREQ_MASK; 135 136 return vco_freq[hpll_freq] * 1000; 137 } 138 139 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 140 const char *name, u32 reg, int ref_freq) 141 { 142 u32 val; 143 int divider; 144 145 val = vlv_cck_read(dev_priv, reg); 146 divider = val & CCK_FREQUENCY_VALUES; 147 148 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != 149 (divider << CCK_FREQUENCY_STATUS_SHIFT), 150 "%s change in progress\n", name); 151 152 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); 153 } 154 155 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 156 const char *name, u32 reg) 157 { 158 int hpll; 159 160 vlv_cck_get(dev_priv); 161 162 if (dev_priv->hpll_freq == 0) 163 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); 164 165 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); 166 167 vlv_cck_put(dev_priv); 168 169 return hpll; 170 } 171 172 void intel_update_czclk(struct drm_i915_private *dev_priv) 173 { 174 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) 175 return; 176 177 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", 178 CCK_CZ_CLOCK_CONTROL); 179 180 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", 181 dev_priv->czclk_freq); 182 } 183 184 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state) 185 { 186 return (crtc_state->active_planes & 187 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0; 188 } 189 190 /* WA Display #0827: Gen9:all */ 191 static void 192 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) 193 { 194 if (enable) 195 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 196 0, DUPS1_GATING_DIS | DUPS2_GATING_DIS); 197 else 198 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 199 DUPS1_GATING_DIS | DUPS2_GATING_DIS, 0); 200 } 201 202 /* Wa_2006604312:icl,ehl */ 203 static void 204 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 205 bool enable) 206 { 207 if (enable) 208 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 0, DPFR_GATING_DIS); 209 else 210 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), DPFR_GATING_DIS, 0); 211 } 212 213 /* Wa_1604331009:icl,jsl,ehl */ 214 static void 215 icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 216 bool enable) 217 { 218 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), CURSOR_GATING_DIS, 219 enable ? CURSOR_GATING_DIS : 0); 220 } 221 222 static bool 223 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state) 224 { 225 return crtc_state->master_transcoder != INVALID_TRANSCODER; 226 } 227 228 bool 229 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state) 230 { 231 return crtc_state->sync_mode_slaves_mask != 0; 232 } 233 234 bool 235 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state) 236 { 237 return is_trans_port_sync_master(crtc_state) || 238 is_trans_port_sync_slave(crtc_state); 239 } 240 241 static enum pipe bigjoiner_master_pipe(const struct intel_crtc_state *crtc_state) 242 { 243 return ffs(crtc_state->bigjoiner_pipes) - 1; 244 } 245 246 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state) 247 { 248 if (crtc_state->bigjoiner_pipes) 249 return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state)); 250 else 251 return 0; 252 } 253 254 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state) 255 { 256 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 257 258 return crtc_state->bigjoiner_pipes && 259 crtc->pipe != bigjoiner_master_pipe(crtc_state); 260 } 261 262 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state) 263 { 264 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 265 266 return crtc_state->bigjoiner_pipes && 267 crtc->pipe == bigjoiner_master_pipe(crtc_state); 268 } 269 270 static int intel_bigjoiner_num_pipes(const struct intel_crtc_state *crtc_state) 271 { 272 return hweight8(crtc_state->bigjoiner_pipes); 273 } 274 275 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state) 276 { 277 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 278 279 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 280 return intel_crtc_for_pipe(i915, bigjoiner_master_pipe(crtc_state)); 281 else 282 return to_intel_crtc(crtc_state->uapi.crtc); 283 } 284 285 static void 286 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) 287 { 288 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 289 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 290 291 if (DISPLAY_VER(dev_priv) >= 4) { 292 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 293 294 /* Wait for the Pipe State to go off */ 295 if (intel_de_wait_for_clear(dev_priv, TRANSCONF(cpu_transcoder), 296 TRANSCONF_STATE_ENABLE, 100)) 297 drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n"); 298 } else { 299 intel_wait_for_pipe_scanline_stopped(crtc); 300 } 301 } 302 303 void assert_transcoder(struct drm_i915_private *dev_priv, 304 enum transcoder cpu_transcoder, bool state) 305 { 306 bool cur_state; 307 enum intel_display_power_domain power_domain; 308 intel_wakeref_t wakeref; 309 310 /* we keep both pipes enabled on 830 */ 311 if (IS_I830(dev_priv)) 312 state = true; 313 314 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 315 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 316 if (wakeref) { 317 u32 val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)); 318 cur_state = !!(val & TRANSCONF_ENABLE); 319 320 intel_display_power_put(dev_priv, power_domain, wakeref); 321 } else { 322 cur_state = false; 323 } 324 325 I915_STATE_WARN(dev_priv, cur_state != state, 326 "transcoder %s assertion failure (expected %s, current %s)\n", 327 transcoder_name(cpu_transcoder), str_on_off(state), 328 str_on_off(cur_state)); 329 } 330 331 static void assert_plane(struct intel_plane *plane, bool state) 332 { 333 struct drm_i915_private *i915 = to_i915(plane->base.dev); 334 enum pipe pipe; 335 bool cur_state; 336 337 cur_state = plane->get_hw_state(plane, &pipe); 338 339 I915_STATE_WARN(i915, cur_state != state, 340 "%s assertion failure (expected %s, current %s)\n", 341 plane->base.name, str_on_off(state), 342 str_on_off(cur_state)); 343 } 344 345 #define assert_plane_enabled(p) assert_plane(p, true) 346 #define assert_plane_disabled(p) assert_plane(p, false) 347 348 static void assert_planes_disabled(struct intel_crtc *crtc) 349 { 350 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 351 struct intel_plane *plane; 352 353 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) 354 assert_plane_disabled(plane); 355 } 356 357 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 358 struct intel_digital_port *dig_port, 359 unsigned int expected_mask) 360 { 361 u32 port_mask; 362 i915_reg_t dpll_reg; 363 364 switch (dig_port->base.port) { 365 default: 366 MISSING_CASE(dig_port->base.port); 367 fallthrough; 368 case PORT_B: 369 port_mask = DPLL_PORTB_READY_MASK; 370 dpll_reg = DPLL(0); 371 break; 372 case PORT_C: 373 port_mask = DPLL_PORTC_READY_MASK; 374 dpll_reg = DPLL(0); 375 expected_mask <<= 4; 376 break; 377 case PORT_D: 378 port_mask = DPLL_PORTD_READY_MASK; 379 dpll_reg = DPIO_PHY_STATUS; 380 break; 381 } 382 383 if (intel_de_wait_for_register(dev_priv, dpll_reg, 384 port_mask, expected_mask, 1000)) 385 drm_WARN(&dev_priv->drm, 1, 386 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", 387 dig_port->base.base.base.id, dig_port->base.base.name, 388 intel_de_read(dev_priv, dpll_reg) & port_mask, 389 expected_mask); 390 } 391 392 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) 393 { 394 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 395 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 396 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 397 enum pipe pipe = crtc->pipe; 398 i915_reg_t reg; 399 u32 val; 400 401 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe)); 402 403 assert_planes_disabled(crtc); 404 405 /* 406 * A pipe without a PLL won't actually be able to drive bits from 407 * a plane. On ILK+ the pipe PLLs are integrated, so we don't 408 * need the check. 409 */ 410 if (HAS_GMCH(dev_priv)) { 411 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI)) 412 assert_dsi_pll_enabled(dev_priv); 413 else 414 assert_pll_enabled(dev_priv, pipe); 415 } else { 416 if (new_crtc_state->has_pch_encoder) { 417 /* if driving the PCH, we need FDI enabled */ 418 assert_fdi_rx_pll_enabled(dev_priv, 419 intel_crtc_pch_transcoder(crtc)); 420 assert_fdi_tx_pll_enabled(dev_priv, 421 (enum pipe) cpu_transcoder); 422 } 423 /* FIXME: assert CPU port conditions for SNB+ */ 424 } 425 426 /* Wa_22012358565:adl-p */ 427 if (DISPLAY_VER(dev_priv) == 13) 428 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe), 429 0, PIPE_ARB_USE_PROG_SLOTS); 430 431 reg = TRANSCONF(cpu_transcoder); 432 val = intel_de_read(dev_priv, reg); 433 if (val & TRANSCONF_ENABLE) { 434 /* we keep both pipes enabled on 830 */ 435 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv)); 436 return; 437 } 438 439 intel_de_write(dev_priv, reg, val | TRANSCONF_ENABLE); 440 intel_de_posting_read(dev_priv, reg); 441 442 /* 443 * Until the pipe starts PIPEDSL reads will return a stale value, 444 * which causes an apparent vblank timestamp jump when PIPEDSL 445 * resets to its proper value. That also messes up the frame count 446 * when it's derived from the timestamps. So let's wait for the 447 * pipe to start properly before we call drm_crtc_vblank_on() 448 */ 449 if (intel_crtc_max_vblank_count(new_crtc_state) == 0) 450 intel_wait_for_pipe_scanline_moving(crtc); 451 } 452 453 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) 454 { 455 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 456 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 457 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 458 enum pipe pipe = crtc->pipe; 459 i915_reg_t reg; 460 u32 val; 461 462 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe)); 463 464 /* 465 * Make sure planes won't keep trying to pump pixels to us, 466 * or we might hang the display. 467 */ 468 assert_planes_disabled(crtc); 469 470 reg = TRANSCONF(cpu_transcoder); 471 val = intel_de_read(dev_priv, reg); 472 if ((val & TRANSCONF_ENABLE) == 0) 473 return; 474 475 /* 476 * Double wide has implications for planes 477 * so best keep it disabled when not needed. 478 */ 479 if (old_crtc_state->double_wide) 480 val &= ~TRANSCONF_DOUBLE_WIDE; 481 482 /* Don't disable pipe or pipe PLLs if needed */ 483 if (!IS_I830(dev_priv)) 484 val &= ~TRANSCONF_ENABLE; 485 486 if (DISPLAY_VER(dev_priv) >= 14) 487 intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder), 488 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 489 else if (DISPLAY_VER(dev_priv) >= 12) 490 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 491 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 492 493 intel_de_write(dev_priv, reg, val); 494 if ((val & TRANSCONF_ENABLE) == 0) 495 intel_wait_for_pipe_off(old_crtc_state); 496 } 497 498 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) 499 { 500 unsigned int size = 0; 501 int i; 502 503 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) 504 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width; 505 506 return size; 507 } 508 509 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info) 510 { 511 unsigned int size = 0; 512 int i; 513 514 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) { 515 unsigned int plane_size; 516 517 if (rem_info->plane[i].linear) 518 plane_size = rem_info->plane[i].size; 519 else 520 plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height; 521 522 if (plane_size == 0) 523 continue; 524 525 if (rem_info->plane_alignment) 526 size = ALIGN(size, rem_info->plane_alignment); 527 528 size += plane_size; 529 } 530 531 return size; 532 } 533 534 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) 535 { 536 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 537 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 538 539 return DISPLAY_VER(dev_priv) < 4 || 540 (plane->fbc && 541 plane_state->view.gtt.type == I915_GTT_VIEW_NORMAL); 542 } 543 544 /* 545 * Convert the x/y offsets into a linear offset. 546 * Only valid with 0/180 degree rotation, which is fine since linear 547 * offset is only used with linear buffers on pre-hsw and tiled buffers 548 * with gen2/3, and 90/270 degree rotations isn't supported on any of them. 549 */ 550 u32 intel_fb_xy_to_linear(int x, int y, 551 const struct intel_plane_state *state, 552 int color_plane) 553 { 554 const struct drm_framebuffer *fb = state->hw.fb; 555 unsigned int cpp = fb->format->cpp[color_plane]; 556 unsigned int pitch = state->view.color_plane[color_plane].mapping_stride; 557 558 return y * pitch + x * cpp; 559 } 560 561 /* 562 * Add the x/y offsets derived from fb->offsets[] to the user 563 * specified plane src x/y offsets. The resulting x/y offsets 564 * specify the start of scanout from the beginning of the gtt mapping. 565 */ 566 void intel_add_fb_offsets(int *x, int *y, 567 const struct intel_plane_state *state, 568 int color_plane) 569 570 { 571 *x += state->view.color_plane[color_plane].x; 572 *y += state->view.color_plane[color_plane].y; 573 } 574 575 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 576 u32 pixel_format, u64 modifier) 577 { 578 struct intel_crtc *crtc; 579 struct intel_plane *plane; 580 581 if (!HAS_DISPLAY(dev_priv)) 582 return 0; 583 584 /* 585 * We assume the primary plane for pipe A has 586 * the highest stride limits of them all, 587 * if in case pipe A is disabled, use the first pipe from pipe_mask. 588 */ 589 crtc = intel_first_crtc(dev_priv); 590 if (!crtc) 591 return 0; 592 593 plane = to_intel_plane(crtc->base.primary); 594 595 return plane->max_stride(plane, pixel_format, modifier, 596 DRM_MODE_ROTATE_0); 597 } 598 599 void intel_set_plane_visible(struct intel_crtc_state *crtc_state, 600 struct intel_plane_state *plane_state, 601 bool visible) 602 { 603 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 604 605 plane_state->uapi.visible = visible; 606 607 if (visible) 608 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base); 609 else 610 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base); 611 } 612 613 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state) 614 { 615 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 616 struct drm_plane *plane; 617 618 /* 619 * Active_planes aliases if multiple "primary" or cursor planes 620 * have been used on the same (or wrong) pipe. plane_mask uses 621 * unique ids, hence we can use that to reconstruct active_planes. 622 */ 623 crtc_state->enabled_planes = 0; 624 crtc_state->active_planes = 0; 625 626 drm_for_each_plane_mask(plane, &dev_priv->drm, 627 crtc_state->uapi.plane_mask) { 628 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id); 629 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id); 630 } 631 } 632 633 void intel_plane_disable_noatomic(struct intel_crtc *crtc, 634 struct intel_plane *plane) 635 { 636 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 637 struct intel_crtc_state *crtc_state = 638 to_intel_crtc_state(crtc->base.state); 639 struct intel_plane_state *plane_state = 640 to_intel_plane_state(plane->base.state); 641 642 drm_dbg_kms(&dev_priv->drm, 643 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n", 644 plane->base.base.id, plane->base.name, 645 crtc->base.base.id, crtc->base.name); 646 647 intel_set_plane_visible(crtc_state, plane_state, false); 648 intel_plane_fixup_bitmasks(crtc_state); 649 crtc_state->data_rate[plane->id] = 0; 650 crtc_state->data_rate_y[plane->id] = 0; 651 crtc_state->rel_data_rate[plane->id] = 0; 652 crtc_state->rel_data_rate_y[plane->id] = 0; 653 crtc_state->min_cdclk[plane->id] = 0; 654 655 if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 && 656 hsw_ips_disable(crtc_state)) { 657 crtc_state->ips_enabled = false; 658 intel_crtc_wait_for_next_vblank(crtc); 659 } 660 661 /* 662 * Vblank time updates from the shadow to live plane control register 663 * are blocked if the memory self-refresh mode is active at that 664 * moment. So to make sure the plane gets truly disabled, disable 665 * first the self-refresh mode. The self-refresh enable bit in turn 666 * will be checked/applied by the HW only at the next frame start 667 * event which is after the vblank start event, so we need to have a 668 * wait-for-vblank between disabling the plane and the pipe. 669 */ 670 if (HAS_GMCH(dev_priv) && 671 intel_set_memory_cxsr(dev_priv, false)) 672 intel_crtc_wait_for_next_vblank(crtc); 673 674 /* 675 * Gen2 reports pipe underruns whenever all planes are disabled. 676 * So disable underrun reporting before all the planes get disabled. 677 */ 678 if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes) 679 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); 680 681 intel_plane_disable_arm(plane, crtc_state); 682 intel_crtc_wait_for_next_vblank(crtc); 683 } 684 685 unsigned int 686 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state) 687 { 688 int x = 0, y = 0; 689 690 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, 691 plane_state->view.color_plane[0].offset, 0); 692 693 return y; 694 } 695 696 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) 697 { 698 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 699 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 700 enum pipe pipe = crtc->pipe; 701 u32 tmp; 702 703 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe)); 704 705 /* 706 * Display WA #1153: icl 707 * enable hardware to bypass the alpha math 708 * and rounding for per-pixel values 00 and 0xff 709 */ 710 tmp |= PER_PIXEL_ALPHA_BYPASS_EN; 711 /* 712 * Display WA # 1605353570: icl 713 * Set the pixel rounding bit to 1 for allowing 714 * passthrough of Frame buffer pixels unmodified 715 * across pipe 716 */ 717 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU; 718 719 /* 720 * Underrun recovery must always be disabled on display 13+. 721 * DG2 chicken bit meaning is inverted compared to other platforms. 722 */ 723 if (IS_DG2(dev_priv)) 724 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2; 725 else if (DISPLAY_VER(dev_priv) >= 13) 726 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP; 727 728 /* Wa_14010547955:dg2 */ 729 if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER)) 730 tmp |= DG2_RENDER_CCSTAG_4_3_EN; 731 732 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp); 733 } 734 735 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) 736 { 737 struct drm_crtc *crtc; 738 bool cleanup_done; 739 740 drm_for_each_crtc(crtc, &dev_priv->drm) { 741 struct drm_crtc_commit *commit; 742 spin_lock(&crtc->commit_lock); 743 commit = list_first_entry_or_null(&crtc->commit_list, 744 struct drm_crtc_commit, commit_entry); 745 cleanup_done = commit ? 746 try_wait_for_completion(&commit->cleanup_done) : true; 747 spin_unlock(&crtc->commit_lock); 748 749 if (cleanup_done) 750 continue; 751 752 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc)); 753 754 return true; 755 } 756 757 return false; 758 } 759 760 /* 761 * Finds the encoder associated with the given CRTC. This can only be 762 * used when we know that the CRTC isn't feeding multiple encoders! 763 */ 764 struct intel_encoder * 765 intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 766 const struct intel_crtc_state *crtc_state) 767 { 768 const struct drm_connector_state *connector_state; 769 const struct drm_connector *connector; 770 struct intel_encoder *encoder = NULL; 771 struct intel_crtc *master_crtc; 772 int num_encoders = 0; 773 int i; 774 775 master_crtc = intel_master_crtc(crtc_state); 776 777 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 778 if (connector_state->crtc != &master_crtc->base) 779 continue; 780 781 encoder = to_intel_encoder(connector_state->best_encoder); 782 num_encoders++; 783 } 784 785 drm_WARN(state->base.dev, num_encoders != 1, 786 "%d encoders for pipe %c\n", 787 num_encoders, pipe_name(master_crtc->pipe)); 788 789 return encoder; 790 } 791 792 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state) 793 { 794 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 795 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 796 const struct drm_rect *dst = &crtc_state->pch_pfit.dst; 797 enum pipe pipe = crtc->pipe; 798 int width = drm_rect_width(dst); 799 int height = drm_rect_height(dst); 800 int x = dst->x1; 801 int y = dst->y1; 802 803 if (!crtc_state->pch_pfit.enabled) 804 return; 805 806 /* Force use of hard-coded filter coefficients 807 * as some pre-programmed values are broken, 808 * e.g. x201. 809 */ 810 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) 811 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 812 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe)); 813 else 814 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 815 PF_FILTER_MED_3x3); 816 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 817 PF_WIN_XPOS(x) | PF_WIN_YPOS(y)); 818 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 819 PF_WIN_XSIZE(width) | PF_WIN_YSIZE(height)); 820 } 821 822 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc) 823 { 824 if (crtc->overlay) 825 (void) intel_overlay_switch_off(crtc->overlay); 826 827 /* Let userspace switch the overlay on again. In most cases userspace 828 * has to recompute where to put it anyway. 829 */ 830 } 831 832 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state) 833 { 834 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 835 836 if (!crtc_state->nv12_planes) 837 return false; 838 839 /* WA Display #0827: Gen9:all */ 840 if (DISPLAY_VER(dev_priv) == 9) 841 return true; 842 843 return false; 844 } 845 846 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state) 847 { 848 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 849 850 /* Wa_2006604312:icl,ehl */ 851 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11) 852 return true; 853 854 return false; 855 } 856 857 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state) 858 { 859 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 860 861 /* Wa_1604331009:icl,jsl,ehl */ 862 if (is_hdr_mode(crtc_state) && 863 crtc_state->active_planes & BIT(PLANE_CURSOR) && 864 DISPLAY_VER(dev_priv) == 11) 865 return true; 866 867 return false; 868 } 869 870 static void intel_async_flip_vtd_wa(struct drm_i915_private *i915, 871 enum pipe pipe, bool enable) 872 { 873 if (DISPLAY_VER(i915) == 9) { 874 /* 875 * "Plane N strech max must be programmed to 11b (x1) 876 * when Async flips are enabled on that plane." 877 */ 878 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 879 SKL_PLANE1_STRETCH_MAX_MASK, 880 enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8); 881 } else { 882 /* Also needed on HSW/BDW albeit undocumented */ 883 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 884 HSW_PRI_STRETCH_MAX_MASK, 885 enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8); 886 } 887 } 888 889 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state) 890 { 891 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 892 893 return crtc_state->uapi.async_flip && i915_vtd_active(i915) && 894 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915)); 895 } 896 897 #define is_enabling(feature, old_crtc_state, new_crtc_state) \ 898 ((!(old_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)) && \ 899 (new_crtc_state)->feature) 900 #define is_disabling(feature, old_crtc_state, new_crtc_state) \ 901 ((old_crtc_state)->feature && \ 902 (!(new_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state))) 903 904 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state, 905 const struct intel_crtc_state *new_crtc_state) 906 { 907 return is_enabling(active_planes, old_crtc_state, new_crtc_state); 908 } 909 910 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state, 911 const struct intel_crtc_state *new_crtc_state) 912 { 913 return is_disabling(active_planes, old_crtc_state, new_crtc_state); 914 } 915 916 static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state, 917 const struct intel_crtc_state *new_crtc_state) 918 { 919 return is_enabling(vrr.enable, old_crtc_state, new_crtc_state); 920 } 921 922 static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state, 923 const struct intel_crtc_state *new_crtc_state) 924 { 925 return is_disabling(vrr.enable, old_crtc_state, new_crtc_state); 926 } 927 928 #undef is_disabling 929 #undef is_enabling 930 931 static void intel_post_plane_update(struct intel_atomic_state *state, 932 struct intel_crtc *crtc) 933 { 934 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 935 const struct intel_crtc_state *old_crtc_state = 936 intel_atomic_get_old_crtc_state(state, crtc); 937 const struct intel_crtc_state *new_crtc_state = 938 intel_atomic_get_new_crtc_state(state, crtc); 939 enum pipe pipe = crtc->pipe; 940 941 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); 942 943 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) 944 intel_update_watermarks(dev_priv); 945 946 intel_fbc_post_update(state, crtc); 947 948 if (needs_async_flip_vtd_wa(old_crtc_state) && 949 !needs_async_flip_vtd_wa(new_crtc_state)) 950 intel_async_flip_vtd_wa(dev_priv, pipe, false); 951 952 if (needs_nv12_wa(old_crtc_state) && 953 !needs_nv12_wa(new_crtc_state)) 954 skl_wa_827(dev_priv, pipe, false); 955 956 if (needs_scalerclk_wa(old_crtc_state) && 957 !needs_scalerclk_wa(new_crtc_state)) 958 icl_wa_scalerclkgating(dev_priv, pipe, false); 959 960 if (needs_cursorclk_wa(old_crtc_state) && 961 !needs_cursorclk_wa(new_crtc_state)) 962 icl_wa_cursorclkgating(dev_priv, pipe, false); 963 964 if (intel_crtc_needs_color_update(new_crtc_state)) 965 intel_color_post_update(new_crtc_state); 966 } 967 968 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state, 969 struct intel_crtc *crtc) 970 { 971 const struct intel_crtc_state *crtc_state = 972 intel_atomic_get_new_crtc_state(state, crtc); 973 u8 update_planes = crtc_state->update_planes; 974 const struct intel_plane_state __maybe_unused *plane_state; 975 struct intel_plane *plane; 976 int i; 977 978 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 979 if (plane->pipe == crtc->pipe && 980 update_planes & BIT(plane->id)) 981 plane->enable_flip_done(plane); 982 } 983 } 984 985 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state, 986 struct intel_crtc *crtc) 987 { 988 const struct intel_crtc_state *crtc_state = 989 intel_atomic_get_new_crtc_state(state, crtc); 990 u8 update_planes = crtc_state->update_planes; 991 const struct intel_plane_state __maybe_unused *plane_state; 992 struct intel_plane *plane; 993 int i; 994 995 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 996 if (plane->pipe == crtc->pipe && 997 update_planes & BIT(plane->id)) 998 plane->disable_flip_done(plane); 999 } 1000 } 1001 1002 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state, 1003 struct intel_crtc *crtc) 1004 { 1005 const struct intel_crtc_state *old_crtc_state = 1006 intel_atomic_get_old_crtc_state(state, crtc); 1007 const struct intel_crtc_state *new_crtc_state = 1008 intel_atomic_get_new_crtc_state(state, crtc); 1009 u8 disable_async_flip_planes = old_crtc_state->async_flip_planes & 1010 ~new_crtc_state->async_flip_planes; 1011 const struct intel_plane_state *old_plane_state; 1012 struct intel_plane *plane; 1013 bool need_vbl_wait = false; 1014 int i; 1015 1016 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1017 if (plane->need_async_flip_disable_wa && 1018 plane->pipe == crtc->pipe && 1019 disable_async_flip_planes & BIT(plane->id)) { 1020 /* 1021 * Apart from the async flip bit we want to 1022 * preserve the old state for the plane. 1023 */ 1024 plane->async_flip(plane, old_crtc_state, 1025 old_plane_state, false); 1026 need_vbl_wait = true; 1027 } 1028 } 1029 1030 if (need_vbl_wait) 1031 intel_crtc_wait_for_next_vblank(crtc); 1032 } 1033 1034 static void intel_pre_plane_update(struct intel_atomic_state *state, 1035 struct intel_crtc *crtc) 1036 { 1037 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1038 const struct intel_crtc_state *old_crtc_state = 1039 intel_atomic_get_old_crtc_state(state, crtc); 1040 const struct intel_crtc_state *new_crtc_state = 1041 intel_atomic_get_new_crtc_state(state, crtc); 1042 enum pipe pipe = crtc->pipe; 1043 1044 if (vrr_disabling(old_crtc_state, new_crtc_state)) { 1045 intel_vrr_disable(old_crtc_state); 1046 intel_crtc_update_active_timings(old_crtc_state, false); 1047 } 1048 1049 intel_drrs_deactivate(old_crtc_state); 1050 1051 intel_psr_pre_plane_update(state, crtc); 1052 1053 if (hsw_ips_pre_update(state, crtc)) 1054 intel_crtc_wait_for_next_vblank(crtc); 1055 1056 if (intel_fbc_pre_update(state, crtc)) 1057 intel_crtc_wait_for_next_vblank(crtc); 1058 1059 if (!needs_async_flip_vtd_wa(old_crtc_state) && 1060 needs_async_flip_vtd_wa(new_crtc_state)) 1061 intel_async_flip_vtd_wa(dev_priv, pipe, true); 1062 1063 /* Display WA 827 */ 1064 if (!needs_nv12_wa(old_crtc_state) && 1065 needs_nv12_wa(new_crtc_state)) 1066 skl_wa_827(dev_priv, pipe, true); 1067 1068 /* Wa_2006604312:icl,ehl */ 1069 if (!needs_scalerclk_wa(old_crtc_state) && 1070 needs_scalerclk_wa(new_crtc_state)) 1071 icl_wa_scalerclkgating(dev_priv, pipe, true); 1072 1073 /* Wa_1604331009:icl,jsl,ehl */ 1074 if (!needs_cursorclk_wa(old_crtc_state) && 1075 needs_cursorclk_wa(new_crtc_state)) 1076 icl_wa_cursorclkgating(dev_priv, pipe, true); 1077 1078 /* 1079 * Vblank time updates from the shadow to live plane control register 1080 * are blocked if the memory self-refresh mode is active at that 1081 * moment. So to make sure the plane gets truly disabled, disable 1082 * first the self-refresh mode. The self-refresh enable bit in turn 1083 * will be checked/applied by the HW only at the next frame start 1084 * event which is after the vblank start event, so we need to have a 1085 * wait-for-vblank between disabling the plane and the pipe. 1086 */ 1087 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active && 1088 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) 1089 intel_crtc_wait_for_next_vblank(crtc); 1090 1091 /* 1092 * IVB workaround: must disable low power watermarks for at least 1093 * one frame before enabling scaling. LP watermarks can be re-enabled 1094 * when scaling is disabled. 1095 * 1096 * WaCxSRDisabledForSpriteScaling:ivb 1097 */ 1098 if (old_crtc_state->hw.active && 1099 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv)) 1100 intel_crtc_wait_for_next_vblank(crtc); 1101 1102 /* 1103 * If we're doing a modeset we don't need to do any 1104 * pre-vblank watermark programming here. 1105 */ 1106 if (!intel_crtc_needs_modeset(new_crtc_state)) { 1107 /* 1108 * For platforms that support atomic watermarks, program the 1109 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these 1110 * will be the intermediate values that are safe for both pre- and 1111 * post- vblank; when vblank happens, the 'active' values will be set 1112 * to the final 'target' values and we'll do this again to get the 1113 * optimal watermarks. For gen9+ platforms, the values we program here 1114 * will be the final target values which will get automatically latched 1115 * at vblank time; no further programming will be necessary. 1116 * 1117 * If a platform hasn't been transitioned to atomic watermarks yet, 1118 * we'll continue to update watermarks the old way, if flags tell 1119 * us to. 1120 */ 1121 if (!intel_initial_watermarks(state, crtc)) 1122 if (new_crtc_state->update_wm_pre) 1123 intel_update_watermarks(dev_priv); 1124 } 1125 1126 /* 1127 * Gen2 reports pipe underruns whenever all planes are disabled. 1128 * So disable underrun reporting before all the planes get disabled. 1129 * 1130 * We do this after .initial_watermarks() so that we have a 1131 * chance of catching underruns with the intermediate watermarks 1132 * vs. the old plane configuration. 1133 */ 1134 if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state)) 1135 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1136 1137 /* 1138 * WA for platforms where async address update enable bit 1139 * is double buffered and only latched at start of vblank. 1140 */ 1141 if (old_crtc_state->async_flip_planes & ~new_crtc_state->async_flip_planes) 1142 intel_crtc_async_flip_disable_wa(state, crtc); 1143 } 1144 1145 static void intel_crtc_disable_planes(struct intel_atomic_state *state, 1146 struct intel_crtc *crtc) 1147 { 1148 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1149 const struct intel_crtc_state *new_crtc_state = 1150 intel_atomic_get_new_crtc_state(state, crtc); 1151 unsigned int update_mask = new_crtc_state->update_planes; 1152 const struct intel_plane_state *old_plane_state; 1153 struct intel_plane *plane; 1154 unsigned fb_bits = 0; 1155 int i; 1156 1157 intel_crtc_dpms_overlay_disable(crtc); 1158 1159 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1160 if (crtc->pipe != plane->pipe || 1161 !(update_mask & BIT(plane->id))) 1162 continue; 1163 1164 intel_plane_disable_arm(plane, new_crtc_state); 1165 1166 if (old_plane_state->uapi.visible) 1167 fb_bits |= plane->frontbuffer_bit; 1168 } 1169 1170 intel_frontbuffer_flip(dev_priv, fb_bits); 1171 } 1172 1173 static void intel_encoders_update_prepare(struct intel_atomic_state *state) 1174 { 1175 struct drm_i915_private *i915 = to_i915(state->base.dev); 1176 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 1177 struct intel_crtc *crtc; 1178 int i; 1179 1180 /* 1181 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits. 1182 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook. 1183 */ 1184 if (i915->display.dpll.mgr) { 1185 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1186 if (intel_crtc_needs_modeset(new_crtc_state)) 1187 continue; 1188 1189 new_crtc_state->shared_dpll = old_crtc_state->shared_dpll; 1190 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state; 1191 } 1192 } 1193 } 1194 1195 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state, 1196 struct intel_crtc *crtc) 1197 { 1198 const struct intel_crtc_state *crtc_state = 1199 intel_atomic_get_new_crtc_state(state, crtc); 1200 const struct drm_connector_state *conn_state; 1201 struct drm_connector *conn; 1202 int i; 1203 1204 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1205 struct intel_encoder *encoder = 1206 to_intel_encoder(conn_state->best_encoder); 1207 1208 if (conn_state->crtc != &crtc->base) 1209 continue; 1210 1211 if (encoder->pre_pll_enable) 1212 encoder->pre_pll_enable(state, encoder, 1213 crtc_state, conn_state); 1214 } 1215 } 1216 1217 static void intel_encoders_pre_enable(struct intel_atomic_state *state, 1218 struct intel_crtc *crtc) 1219 { 1220 const struct intel_crtc_state *crtc_state = 1221 intel_atomic_get_new_crtc_state(state, crtc); 1222 const struct drm_connector_state *conn_state; 1223 struct drm_connector *conn; 1224 int i; 1225 1226 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1227 struct intel_encoder *encoder = 1228 to_intel_encoder(conn_state->best_encoder); 1229 1230 if (conn_state->crtc != &crtc->base) 1231 continue; 1232 1233 if (encoder->pre_enable) 1234 encoder->pre_enable(state, encoder, 1235 crtc_state, conn_state); 1236 } 1237 } 1238 1239 static void intel_encoders_enable(struct intel_atomic_state *state, 1240 struct intel_crtc *crtc) 1241 { 1242 const struct intel_crtc_state *crtc_state = 1243 intel_atomic_get_new_crtc_state(state, crtc); 1244 const struct drm_connector_state *conn_state; 1245 struct drm_connector *conn; 1246 int i; 1247 1248 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1249 struct intel_encoder *encoder = 1250 to_intel_encoder(conn_state->best_encoder); 1251 1252 if (conn_state->crtc != &crtc->base) 1253 continue; 1254 1255 if (encoder->enable) 1256 encoder->enable(state, encoder, 1257 crtc_state, conn_state); 1258 intel_opregion_notify_encoder(encoder, true); 1259 } 1260 } 1261 1262 static void intel_encoders_disable(struct intel_atomic_state *state, 1263 struct intel_crtc *crtc) 1264 { 1265 const struct intel_crtc_state *old_crtc_state = 1266 intel_atomic_get_old_crtc_state(state, crtc); 1267 const struct drm_connector_state *old_conn_state; 1268 struct drm_connector *conn; 1269 int i; 1270 1271 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1272 struct intel_encoder *encoder = 1273 to_intel_encoder(old_conn_state->best_encoder); 1274 1275 if (old_conn_state->crtc != &crtc->base) 1276 continue; 1277 1278 intel_opregion_notify_encoder(encoder, false); 1279 if (encoder->disable) 1280 encoder->disable(state, encoder, 1281 old_crtc_state, old_conn_state); 1282 } 1283 } 1284 1285 static void intel_encoders_post_disable(struct intel_atomic_state *state, 1286 struct intel_crtc *crtc) 1287 { 1288 const struct intel_crtc_state *old_crtc_state = 1289 intel_atomic_get_old_crtc_state(state, crtc); 1290 const struct drm_connector_state *old_conn_state; 1291 struct drm_connector *conn; 1292 int i; 1293 1294 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1295 struct intel_encoder *encoder = 1296 to_intel_encoder(old_conn_state->best_encoder); 1297 1298 if (old_conn_state->crtc != &crtc->base) 1299 continue; 1300 1301 if (encoder->post_disable) 1302 encoder->post_disable(state, encoder, 1303 old_crtc_state, old_conn_state); 1304 } 1305 } 1306 1307 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state, 1308 struct intel_crtc *crtc) 1309 { 1310 const struct intel_crtc_state *old_crtc_state = 1311 intel_atomic_get_old_crtc_state(state, crtc); 1312 const struct drm_connector_state *old_conn_state; 1313 struct drm_connector *conn; 1314 int i; 1315 1316 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1317 struct intel_encoder *encoder = 1318 to_intel_encoder(old_conn_state->best_encoder); 1319 1320 if (old_conn_state->crtc != &crtc->base) 1321 continue; 1322 1323 if (encoder->post_pll_disable) 1324 encoder->post_pll_disable(state, encoder, 1325 old_crtc_state, old_conn_state); 1326 } 1327 } 1328 1329 static void intel_encoders_update_pipe(struct intel_atomic_state *state, 1330 struct intel_crtc *crtc) 1331 { 1332 const struct intel_crtc_state *crtc_state = 1333 intel_atomic_get_new_crtc_state(state, crtc); 1334 const struct drm_connector_state *conn_state; 1335 struct drm_connector *conn; 1336 int i; 1337 1338 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1339 struct intel_encoder *encoder = 1340 to_intel_encoder(conn_state->best_encoder); 1341 1342 if (conn_state->crtc != &crtc->base) 1343 continue; 1344 1345 if (encoder->update_pipe) 1346 encoder->update_pipe(state, encoder, 1347 crtc_state, conn_state); 1348 } 1349 } 1350 1351 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state) 1352 { 1353 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1354 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 1355 1356 plane->disable_arm(plane, crtc_state); 1357 } 1358 1359 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1360 { 1361 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1362 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1363 1364 if (crtc_state->has_pch_encoder) { 1365 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1366 &crtc_state->fdi_m_n); 1367 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1368 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1369 &crtc_state->dp_m_n); 1370 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1371 &crtc_state->dp_m2_n2); 1372 } 1373 1374 intel_set_transcoder_timings(crtc_state); 1375 1376 ilk_set_pipeconf(crtc_state); 1377 } 1378 1379 static void ilk_crtc_enable(struct intel_atomic_state *state, 1380 struct intel_crtc *crtc) 1381 { 1382 const struct intel_crtc_state *new_crtc_state = 1383 intel_atomic_get_new_crtc_state(state, crtc); 1384 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1385 enum pipe pipe = crtc->pipe; 1386 1387 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1388 return; 1389 1390 /* 1391 * Sometimes spurious CPU pipe underruns happen during FDI 1392 * training, at least with VGA+HDMI cloning. Suppress them. 1393 * 1394 * On ILK we get an occasional spurious CPU pipe underruns 1395 * between eDP port A enable and vdd enable. Also PCH port 1396 * enable seems to result in the occasional CPU pipe underrun. 1397 * 1398 * Spurious PCH underruns also occur during PCH enabling. 1399 */ 1400 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1401 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 1402 1403 ilk_configure_cpu_transcoder(new_crtc_state); 1404 1405 intel_set_pipe_src_size(new_crtc_state); 1406 1407 crtc->active = true; 1408 1409 intel_encoders_pre_enable(state, crtc); 1410 1411 if (new_crtc_state->has_pch_encoder) { 1412 ilk_pch_pre_enable(state, crtc); 1413 } else { 1414 assert_fdi_tx_disabled(dev_priv, pipe); 1415 assert_fdi_rx_disabled(dev_priv, pipe); 1416 } 1417 1418 ilk_pfit_enable(new_crtc_state); 1419 1420 /* 1421 * On ILK+ LUT must be loaded before the pipe is running but with 1422 * clocks enabled 1423 */ 1424 intel_color_load_luts(new_crtc_state); 1425 intel_color_commit_noarm(new_crtc_state); 1426 intel_color_commit_arm(new_crtc_state); 1427 /* update DSPCNTR to configure gamma for pipe bottom color */ 1428 intel_disable_primary_plane(new_crtc_state); 1429 1430 intel_initial_watermarks(state, crtc); 1431 intel_enable_transcoder(new_crtc_state); 1432 1433 if (new_crtc_state->has_pch_encoder) 1434 ilk_pch_enable(state, crtc); 1435 1436 intel_crtc_vblank_on(new_crtc_state); 1437 1438 intel_encoders_enable(state, crtc); 1439 1440 if (HAS_PCH_CPT(dev_priv)) 1441 intel_wait_for_pipe_scanline_moving(crtc); 1442 1443 /* 1444 * Must wait for vblank to avoid spurious PCH FIFO underruns. 1445 * And a second vblank wait is needed at least on ILK with 1446 * some interlaced HDMI modes. Let's do the double wait always 1447 * in case there are more corner cases we don't know about. 1448 */ 1449 if (new_crtc_state->has_pch_encoder) { 1450 intel_crtc_wait_for_next_vblank(crtc); 1451 intel_crtc_wait_for_next_vblank(crtc); 1452 } 1453 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1454 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 1455 } 1456 1457 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, 1458 enum pipe pipe, bool apply) 1459 { 1460 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)); 1461 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS; 1462 1463 if (apply) 1464 val |= mask; 1465 else 1466 val &= ~mask; 1467 1468 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val); 1469 } 1470 1471 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state) 1472 { 1473 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1474 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1475 1476 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe), 1477 HSW_LINETIME(crtc_state->linetime) | 1478 HSW_IPS_LINETIME(crtc_state->ips_linetime)); 1479 } 1480 1481 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) 1482 { 1483 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1484 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1485 enum transcoder transcoder = crtc_state->cpu_transcoder; 1486 i915_reg_t reg = DISPLAY_VER(dev_priv) >= 14 ? MTL_CHICKEN_TRANS(transcoder) : 1487 CHICKEN_TRANS(transcoder); 1488 1489 intel_de_rmw(dev_priv, reg, 1490 HSW_FRAME_START_DELAY_MASK, 1491 HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1)); 1492 } 1493 1494 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state, 1495 const struct intel_crtc_state *crtc_state) 1496 { 1497 struct intel_crtc *master_crtc = intel_master_crtc(crtc_state); 1498 1499 /* 1500 * Enable sequence steps 1-7 on bigjoiner master 1501 */ 1502 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1503 intel_encoders_pre_pll_enable(state, master_crtc); 1504 1505 if (crtc_state->shared_dpll) 1506 intel_enable_shared_dpll(crtc_state); 1507 1508 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1509 intel_encoders_pre_enable(state, master_crtc); 1510 } 1511 1512 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1513 { 1514 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1515 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1516 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1517 1518 if (crtc_state->has_pch_encoder) { 1519 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1520 &crtc_state->fdi_m_n); 1521 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1522 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1523 &crtc_state->dp_m_n); 1524 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1525 &crtc_state->dp_m2_n2); 1526 } 1527 1528 intel_set_transcoder_timings(crtc_state); 1529 if (HAS_VRR(dev_priv)) 1530 intel_vrr_set_transcoder_timings(crtc_state); 1531 1532 if (cpu_transcoder != TRANSCODER_EDP) 1533 intel_de_write(dev_priv, TRANS_MULT(cpu_transcoder), 1534 crtc_state->pixel_multiplier - 1); 1535 1536 hsw_set_frame_start_delay(crtc_state); 1537 1538 hsw_set_transconf(crtc_state); 1539 } 1540 1541 static void hsw_crtc_enable(struct intel_atomic_state *state, 1542 struct intel_crtc *crtc) 1543 { 1544 const struct intel_crtc_state *new_crtc_state = 1545 intel_atomic_get_new_crtc_state(state, crtc); 1546 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1547 enum pipe pipe = crtc->pipe, hsw_workaround_pipe; 1548 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 1549 bool psl_clkgate_wa; 1550 1551 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1552 return; 1553 1554 intel_dmc_enable_pipe(dev_priv, crtc->pipe); 1555 1556 if (!new_crtc_state->bigjoiner_pipes) { 1557 intel_encoders_pre_pll_enable(state, crtc); 1558 1559 if (new_crtc_state->shared_dpll) 1560 intel_enable_shared_dpll(new_crtc_state); 1561 1562 intel_encoders_pre_enable(state, crtc); 1563 } else { 1564 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state); 1565 } 1566 1567 intel_dsc_enable(new_crtc_state); 1568 1569 if (DISPLAY_VER(dev_priv) >= 13) 1570 intel_uncompressed_joiner_enable(new_crtc_state); 1571 1572 intel_set_pipe_src_size(new_crtc_state); 1573 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 1574 bdw_set_pipe_misc(new_crtc_state); 1575 1576 if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) && 1577 !transcoder_is_dsi(cpu_transcoder)) 1578 hsw_configure_cpu_transcoder(new_crtc_state); 1579 1580 crtc->active = true; 1581 1582 /* Display WA #1180: WaDisableScalarClockGating: glk */ 1583 psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 && 1584 new_crtc_state->pch_pfit.enabled; 1585 if (psl_clkgate_wa) 1586 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true); 1587 1588 if (DISPLAY_VER(dev_priv) >= 9) 1589 skl_pfit_enable(new_crtc_state); 1590 else 1591 ilk_pfit_enable(new_crtc_state); 1592 1593 /* 1594 * On ILK+ LUT must be loaded before the pipe is running but with 1595 * clocks enabled 1596 */ 1597 intel_color_load_luts(new_crtc_state); 1598 intel_color_commit_noarm(new_crtc_state); 1599 intel_color_commit_arm(new_crtc_state); 1600 /* update DSPCNTR to configure gamma/csc for pipe bottom color */ 1601 if (DISPLAY_VER(dev_priv) < 9) 1602 intel_disable_primary_plane(new_crtc_state); 1603 1604 hsw_set_linetime_wm(new_crtc_state); 1605 1606 if (DISPLAY_VER(dev_priv) >= 11) 1607 icl_set_pipe_chicken(new_crtc_state); 1608 1609 intel_initial_watermarks(state, crtc); 1610 1611 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 1612 intel_crtc_vblank_on(new_crtc_state); 1613 1614 intel_encoders_enable(state, crtc); 1615 1616 if (psl_clkgate_wa) { 1617 intel_crtc_wait_for_next_vblank(crtc); 1618 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false); 1619 } 1620 1621 /* If we change the relative order between pipe/planes enabling, we need 1622 * to change the workaround. */ 1623 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe; 1624 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { 1625 struct intel_crtc *wa_crtc; 1626 1627 wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe); 1628 1629 intel_crtc_wait_for_next_vblank(wa_crtc); 1630 intel_crtc_wait_for_next_vblank(wa_crtc); 1631 } 1632 } 1633 1634 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state) 1635 { 1636 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1637 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1638 enum pipe pipe = crtc->pipe; 1639 1640 /* To avoid upsetting the power well on haswell only disable the pfit if 1641 * it's in use. The hw state code will make sure we get this right. */ 1642 if (!old_crtc_state->pch_pfit.enabled) 1643 return; 1644 1645 intel_de_write_fw(dev_priv, PF_CTL(pipe), 0); 1646 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0); 1647 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0); 1648 } 1649 1650 static void ilk_crtc_disable(struct intel_atomic_state *state, 1651 struct intel_crtc *crtc) 1652 { 1653 const struct intel_crtc_state *old_crtc_state = 1654 intel_atomic_get_old_crtc_state(state, crtc); 1655 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1656 enum pipe pipe = crtc->pipe; 1657 1658 /* 1659 * Sometimes spurious CPU pipe underruns happen when the 1660 * pipe is already disabled, but FDI RX/TX is still enabled. 1661 * Happens at least with VGA+HDMI cloning. Suppress them. 1662 */ 1663 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1664 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 1665 1666 intel_encoders_disable(state, crtc); 1667 1668 intel_crtc_vblank_off(old_crtc_state); 1669 1670 intel_disable_transcoder(old_crtc_state); 1671 1672 ilk_pfit_disable(old_crtc_state); 1673 1674 if (old_crtc_state->has_pch_encoder) 1675 ilk_pch_disable(state, crtc); 1676 1677 intel_encoders_post_disable(state, crtc); 1678 1679 if (old_crtc_state->has_pch_encoder) 1680 ilk_pch_post_disable(state, crtc); 1681 1682 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1683 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 1684 1685 intel_disable_shared_dpll(old_crtc_state); 1686 } 1687 1688 static void hsw_crtc_disable(struct intel_atomic_state *state, 1689 struct intel_crtc *crtc) 1690 { 1691 const struct intel_crtc_state *old_crtc_state = 1692 intel_atomic_get_old_crtc_state(state, crtc); 1693 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 1694 1695 /* 1696 * FIXME collapse everything to one hook. 1697 * Need care with mst->ddi interactions. 1698 */ 1699 if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) { 1700 intel_encoders_disable(state, crtc); 1701 intel_encoders_post_disable(state, crtc); 1702 } 1703 1704 intel_disable_shared_dpll(old_crtc_state); 1705 1706 if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) { 1707 struct intel_crtc *slave_crtc; 1708 1709 intel_encoders_post_pll_disable(state, crtc); 1710 1711 intel_dmc_disable_pipe(i915, crtc->pipe); 1712 1713 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 1714 intel_crtc_bigjoiner_slave_pipes(old_crtc_state)) 1715 intel_dmc_disable_pipe(i915, slave_crtc->pipe); 1716 } 1717 } 1718 1719 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) 1720 { 1721 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1722 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1723 1724 if (!crtc_state->gmch_pfit.control) 1725 return; 1726 1727 /* 1728 * The panel fitter should only be adjusted whilst the pipe is disabled, 1729 * according to register description and PRM. 1730 */ 1731 drm_WARN_ON(&dev_priv->drm, 1732 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE); 1733 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 1734 1735 intel_de_write(dev_priv, PFIT_PGM_RATIOS, 1736 crtc_state->gmch_pfit.pgm_ratios); 1737 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control); 1738 1739 /* Border color in case we don't scale up to the full screen. Black by 1740 * default, change to something else for debugging. */ 1741 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); 1742 } 1743 1744 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) 1745 { 1746 if (phy == PHY_NONE) 1747 return false; 1748 else if (IS_ALDERLAKE_S(dev_priv)) 1749 return phy <= PHY_E; 1750 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) 1751 return phy <= PHY_D; 1752 else if (IS_JSL_EHL(dev_priv)) 1753 return phy <= PHY_C; 1754 else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12)) 1755 return phy <= PHY_B; 1756 else 1757 /* 1758 * DG2 outputs labelled as "combo PHY" in the bspec use 1759 * SNPS PHYs with completely different programming, 1760 * hence we always return false here. 1761 */ 1762 return false; 1763 } 1764 1765 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) 1766 { 1767 if (IS_DG2(dev_priv)) 1768 /* DG2's "TC1" output uses a SNPS PHY */ 1769 return false; 1770 else if (IS_ALDERLAKE_P(dev_priv) || IS_METEORLAKE(dev_priv)) 1771 return phy >= PHY_F && phy <= PHY_I; 1772 else if (IS_TIGERLAKE(dev_priv)) 1773 return phy >= PHY_D && phy <= PHY_I; 1774 else if (IS_ICELAKE(dev_priv)) 1775 return phy >= PHY_C && phy <= PHY_F; 1776 else 1777 return false; 1778 } 1779 1780 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy) 1781 { 1782 if (phy == PHY_NONE) 1783 return false; 1784 else if (IS_DG2(dev_priv)) 1785 /* 1786 * All four "combo" ports and the TC1 port (PHY E) use 1787 * Synopsis PHYs. 1788 */ 1789 return phy <= PHY_E; 1790 1791 return false; 1792 } 1793 1794 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) 1795 { 1796 if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD) 1797 return PHY_D + port - PORT_D_XELPD; 1798 else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1) 1799 return PHY_F + port - PORT_TC1; 1800 else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1) 1801 return PHY_B + port - PORT_TC1; 1802 else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1) 1803 return PHY_C + port - PORT_TC1; 1804 else if (IS_JSL_EHL(i915) && port == PORT_D) 1805 return PHY_A; 1806 1807 return PHY_A + port - PORT_A; 1808 } 1809 1810 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) 1811 { 1812 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port))) 1813 return TC_PORT_NONE; 1814 1815 if (DISPLAY_VER(dev_priv) >= 12) 1816 return TC_PORT_1 + port - PORT_TC1; 1817 else 1818 return TC_PORT_1 + port - PORT_C; 1819 } 1820 1821 enum intel_display_power_domain 1822 intel_aux_power_domain(struct intel_digital_port *dig_port) 1823 { 1824 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1825 1826 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 1827 return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch); 1828 1829 return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch); 1830 } 1831 1832 static void get_crtc_power_domains(struct intel_crtc_state *crtc_state, 1833 struct intel_power_domain_mask *mask) 1834 { 1835 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1836 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1837 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1838 struct drm_encoder *encoder; 1839 enum pipe pipe = crtc->pipe; 1840 1841 bitmap_zero(mask->bits, POWER_DOMAIN_NUM); 1842 1843 if (!crtc_state->hw.active) 1844 return; 1845 1846 set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits); 1847 set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits); 1848 if (crtc_state->pch_pfit.enabled || 1849 crtc_state->pch_pfit.force_thru) 1850 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits); 1851 1852 drm_for_each_encoder_mask(encoder, &dev_priv->drm, 1853 crtc_state->uapi.encoder_mask) { 1854 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 1855 1856 set_bit(intel_encoder->power_domain, mask->bits); 1857 } 1858 1859 if (HAS_DDI(dev_priv) && crtc_state->has_audio) 1860 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits); 1861 1862 if (crtc_state->shared_dpll) 1863 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits); 1864 1865 if (crtc_state->dsc.compression_enable) 1866 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits); 1867 } 1868 1869 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, 1870 struct intel_power_domain_mask *old_domains) 1871 { 1872 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1873 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1874 enum intel_display_power_domain domain; 1875 struct intel_power_domain_mask domains, new_domains; 1876 1877 get_crtc_power_domains(crtc_state, &domains); 1878 1879 bitmap_andnot(new_domains.bits, 1880 domains.bits, 1881 crtc->enabled_power_domains.mask.bits, 1882 POWER_DOMAIN_NUM); 1883 bitmap_andnot(old_domains->bits, 1884 crtc->enabled_power_domains.mask.bits, 1885 domains.bits, 1886 POWER_DOMAIN_NUM); 1887 1888 for_each_power_domain(domain, &new_domains) 1889 intel_display_power_get_in_set(dev_priv, 1890 &crtc->enabled_power_domains, 1891 domain); 1892 } 1893 1894 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc, 1895 struct intel_power_domain_mask *domains) 1896 { 1897 intel_display_power_put_mask_in_set(to_i915(crtc->base.dev), 1898 &crtc->enabled_power_domains, 1899 domains); 1900 } 1901 1902 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1903 { 1904 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1905 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1906 1907 if (intel_crtc_has_dp_encoder(crtc_state)) { 1908 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1909 &crtc_state->dp_m_n); 1910 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1911 &crtc_state->dp_m2_n2); 1912 } 1913 1914 intel_set_transcoder_timings(crtc_state); 1915 1916 i9xx_set_pipeconf(crtc_state); 1917 } 1918 1919 static void valleyview_crtc_enable(struct intel_atomic_state *state, 1920 struct intel_crtc *crtc) 1921 { 1922 const struct intel_crtc_state *new_crtc_state = 1923 intel_atomic_get_new_crtc_state(state, crtc); 1924 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1925 enum pipe pipe = crtc->pipe; 1926 1927 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1928 return; 1929 1930 i9xx_configure_cpu_transcoder(new_crtc_state); 1931 1932 intel_set_pipe_src_size(new_crtc_state); 1933 1934 intel_de_write(dev_priv, VLV_PIPE_MSA_MISC(pipe), 0); 1935 1936 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 1937 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY); 1938 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0); 1939 } 1940 1941 crtc->active = true; 1942 1943 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1944 1945 intel_encoders_pre_pll_enable(state, crtc); 1946 1947 if (IS_CHERRYVIEW(dev_priv)) 1948 chv_enable_pll(new_crtc_state); 1949 else 1950 vlv_enable_pll(new_crtc_state); 1951 1952 intel_encoders_pre_enable(state, crtc); 1953 1954 i9xx_pfit_enable(new_crtc_state); 1955 1956 intel_color_load_luts(new_crtc_state); 1957 intel_color_commit_noarm(new_crtc_state); 1958 intel_color_commit_arm(new_crtc_state); 1959 /* update DSPCNTR to configure gamma for pipe bottom color */ 1960 intel_disable_primary_plane(new_crtc_state); 1961 1962 intel_initial_watermarks(state, crtc); 1963 intel_enable_transcoder(new_crtc_state); 1964 1965 intel_crtc_vblank_on(new_crtc_state); 1966 1967 intel_encoders_enable(state, crtc); 1968 } 1969 1970 static void i9xx_crtc_enable(struct intel_atomic_state *state, 1971 struct intel_crtc *crtc) 1972 { 1973 const struct intel_crtc_state *new_crtc_state = 1974 intel_atomic_get_new_crtc_state(state, crtc); 1975 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1976 enum pipe pipe = crtc->pipe; 1977 1978 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1979 return; 1980 1981 i9xx_configure_cpu_transcoder(new_crtc_state); 1982 1983 intel_set_pipe_src_size(new_crtc_state); 1984 1985 crtc->active = true; 1986 1987 if (DISPLAY_VER(dev_priv) != 2) 1988 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1989 1990 intel_encoders_pre_enable(state, crtc); 1991 1992 i9xx_enable_pll(new_crtc_state); 1993 1994 i9xx_pfit_enable(new_crtc_state); 1995 1996 intel_color_load_luts(new_crtc_state); 1997 intel_color_commit_noarm(new_crtc_state); 1998 intel_color_commit_arm(new_crtc_state); 1999 /* update DSPCNTR to configure gamma for pipe bottom color */ 2000 intel_disable_primary_plane(new_crtc_state); 2001 2002 if (!intel_initial_watermarks(state, crtc)) 2003 intel_update_watermarks(dev_priv); 2004 intel_enable_transcoder(new_crtc_state); 2005 2006 intel_crtc_vblank_on(new_crtc_state); 2007 2008 intel_encoders_enable(state, crtc); 2009 2010 /* prevents spurious underruns */ 2011 if (DISPLAY_VER(dev_priv) == 2) 2012 intel_crtc_wait_for_next_vblank(crtc); 2013 } 2014 2015 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) 2016 { 2017 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 2018 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2019 2020 if (!old_crtc_state->gmch_pfit.control) 2021 return; 2022 2023 assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder); 2024 2025 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n", 2026 intel_de_read(dev_priv, PFIT_CONTROL)); 2027 intel_de_write(dev_priv, PFIT_CONTROL, 0); 2028 } 2029 2030 static void i9xx_crtc_disable(struct intel_atomic_state *state, 2031 struct intel_crtc *crtc) 2032 { 2033 struct intel_crtc_state *old_crtc_state = 2034 intel_atomic_get_old_crtc_state(state, crtc); 2035 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2036 enum pipe pipe = crtc->pipe; 2037 2038 /* 2039 * On gen2 planes are double buffered but the pipe isn't, so we must 2040 * wait for planes to fully turn off before disabling the pipe. 2041 */ 2042 if (DISPLAY_VER(dev_priv) == 2) 2043 intel_crtc_wait_for_next_vblank(crtc); 2044 2045 intel_encoders_disable(state, crtc); 2046 2047 intel_crtc_vblank_off(old_crtc_state); 2048 2049 intel_disable_transcoder(old_crtc_state); 2050 2051 i9xx_pfit_disable(old_crtc_state); 2052 2053 intel_encoders_post_disable(state, crtc); 2054 2055 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) { 2056 if (IS_CHERRYVIEW(dev_priv)) 2057 chv_disable_pll(dev_priv, pipe); 2058 else if (IS_VALLEYVIEW(dev_priv)) 2059 vlv_disable_pll(dev_priv, pipe); 2060 else 2061 i9xx_disable_pll(old_crtc_state); 2062 } 2063 2064 intel_encoders_post_pll_disable(state, crtc); 2065 2066 if (DISPLAY_VER(dev_priv) != 2) 2067 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 2068 2069 if (!dev_priv->display.funcs.wm->initial_watermarks) 2070 intel_update_watermarks(dev_priv); 2071 2072 /* clock the pipe down to 640x480@60 to potentially save power */ 2073 if (IS_I830(dev_priv)) 2074 i830_enable_pipe(dev_priv, pipe); 2075 } 2076 2077 void intel_encoder_destroy(struct drm_encoder *encoder) 2078 { 2079 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2080 2081 drm_encoder_cleanup(encoder); 2082 kfree(intel_encoder); 2083 } 2084 2085 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) 2086 { 2087 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2088 2089 /* GDG double wide on either pipe, otherwise pipe A only */ 2090 return DISPLAY_VER(dev_priv) < 4 && 2091 (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); 2092 } 2093 2094 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) 2095 { 2096 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock; 2097 struct drm_rect src; 2098 2099 /* 2100 * We only use IF-ID interlacing. If we ever use 2101 * PF-ID we'll need to adjust the pixel_rate here. 2102 */ 2103 2104 if (!crtc_state->pch_pfit.enabled) 2105 return pixel_rate; 2106 2107 drm_rect_init(&src, 0, 0, 2108 drm_rect_width(&crtc_state->pipe_src) << 16, 2109 drm_rect_height(&crtc_state->pipe_src) << 16); 2110 2111 return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst, 2112 pixel_rate); 2113 } 2114 2115 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode, 2116 const struct drm_display_mode *timings) 2117 { 2118 mode->hdisplay = timings->crtc_hdisplay; 2119 mode->htotal = timings->crtc_htotal; 2120 mode->hsync_start = timings->crtc_hsync_start; 2121 mode->hsync_end = timings->crtc_hsync_end; 2122 2123 mode->vdisplay = timings->crtc_vdisplay; 2124 mode->vtotal = timings->crtc_vtotal; 2125 mode->vsync_start = timings->crtc_vsync_start; 2126 mode->vsync_end = timings->crtc_vsync_end; 2127 2128 mode->flags = timings->flags; 2129 mode->type = DRM_MODE_TYPE_DRIVER; 2130 2131 mode->clock = timings->crtc_clock; 2132 2133 drm_mode_set_name(mode); 2134 } 2135 2136 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) 2137 { 2138 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2139 2140 if (HAS_GMCH(dev_priv)) 2141 /* FIXME calculate proper pipe pixel rate for GMCH pfit */ 2142 crtc_state->pixel_rate = 2143 crtc_state->hw.pipe_mode.crtc_clock; 2144 else 2145 crtc_state->pixel_rate = 2146 ilk_pipe_pixel_rate(crtc_state); 2147 } 2148 2149 static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state *crtc_state, 2150 struct drm_display_mode *mode) 2151 { 2152 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2153 2154 if (num_pipes < 2) 2155 return; 2156 2157 mode->crtc_clock /= num_pipes; 2158 mode->crtc_hdisplay /= num_pipes; 2159 mode->crtc_hblank_start /= num_pipes; 2160 mode->crtc_hblank_end /= num_pipes; 2161 mode->crtc_hsync_start /= num_pipes; 2162 mode->crtc_hsync_end /= num_pipes; 2163 mode->crtc_htotal /= num_pipes; 2164 } 2165 2166 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state, 2167 struct drm_display_mode *mode) 2168 { 2169 int overlap = crtc_state->splitter.pixel_overlap; 2170 int n = crtc_state->splitter.link_count; 2171 2172 if (!crtc_state->splitter.enable) 2173 return; 2174 2175 /* 2176 * eDP MSO uses segment timings from EDID for transcoder 2177 * timings, but full mode for everything else. 2178 * 2179 * h_full = (h_segment - pixel_overlap) * link_count 2180 */ 2181 mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n; 2182 mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n; 2183 mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n; 2184 mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n; 2185 mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n; 2186 mode->crtc_htotal = (mode->crtc_htotal - overlap) * n; 2187 mode->crtc_clock *= n; 2188 } 2189 2190 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state) 2191 { 2192 struct drm_display_mode *mode = &crtc_state->hw.mode; 2193 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2194 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2195 2196 /* 2197 * Start with the adjusted_mode crtc timings, which 2198 * have been filled with the transcoder timings. 2199 */ 2200 drm_mode_copy(pipe_mode, adjusted_mode); 2201 2202 /* Expand MSO per-segment transcoder timings to full */ 2203 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2204 2205 /* 2206 * We want the full numbers in adjusted_mode normal timings, 2207 * adjusted_mode crtc timings are left with the raw transcoder 2208 * timings. 2209 */ 2210 intel_mode_from_crtc_timings(adjusted_mode, pipe_mode); 2211 2212 /* Populate the "user" mode with full numbers */ 2213 drm_mode_copy(mode, pipe_mode); 2214 intel_mode_from_crtc_timings(mode, mode); 2215 mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) * 2216 (intel_bigjoiner_num_pipes(crtc_state) ?: 1); 2217 mode->vdisplay = drm_rect_height(&crtc_state->pipe_src); 2218 2219 /* Derive per-pipe timings in case bigjoiner is used */ 2220 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2221 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2222 2223 intel_crtc_compute_pixel_rate(crtc_state); 2224 } 2225 2226 void intel_encoder_get_config(struct intel_encoder *encoder, 2227 struct intel_crtc_state *crtc_state) 2228 { 2229 encoder->get_config(encoder, crtc_state); 2230 2231 intel_crtc_readout_derived_state(crtc_state); 2232 } 2233 2234 static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state *crtc_state) 2235 { 2236 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2237 int width, height; 2238 2239 if (num_pipes < 2) 2240 return; 2241 2242 width = drm_rect_width(&crtc_state->pipe_src); 2243 height = drm_rect_height(&crtc_state->pipe_src); 2244 2245 drm_rect_init(&crtc_state->pipe_src, 0, 0, 2246 width / num_pipes, height); 2247 } 2248 2249 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state) 2250 { 2251 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2252 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2253 2254 intel_bigjoiner_compute_pipe_src(crtc_state); 2255 2256 /* 2257 * Pipe horizontal size must be even in: 2258 * - DVO ganged mode 2259 * - LVDS dual channel mode 2260 * - Double wide pipe 2261 */ 2262 if (drm_rect_width(&crtc_state->pipe_src) & 1) { 2263 if (crtc_state->double_wide) { 2264 drm_dbg_kms(&i915->drm, 2265 "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n", 2266 crtc->base.base.id, crtc->base.name); 2267 return -EINVAL; 2268 } 2269 2270 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 2271 intel_is_dual_link_lvds(i915)) { 2272 drm_dbg_kms(&i915->drm, 2273 "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n", 2274 crtc->base.base.id, crtc->base.name); 2275 return -EINVAL; 2276 } 2277 } 2278 2279 return 0; 2280 } 2281 2282 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state) 2283 { 2284 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2285 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2286 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2287 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2288 int clock_limit = i915->max_dotclk_freq; 2289 2290 /* 2291 * Start with the adjusted_mode crtc timings, which 2292 * have been filled with the transcoder timings. 2293 */ 2294 drm_mode_copy(pipe_mode, adjusted_mode); 2295 2296 /* Expand MSO per-segment transcoder timings to full */ 2297 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2298 2299 /* Derive per-pipe timings in case bigjoiner is used */ 2300 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2301 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2302 2303 if (DISPLAY_VER(i915) < 4) { 2304 clock_limit = i915->display.cdclk.max_cdclk_freq * 9 / 10; 2305 2306 /* 2307 * Enable double wide mode when the dot clock 2308 * is > 90% of the (display) core speed. 2309 */ 2310 if (intel_crtc_supports_double_wide(crtc) && 2311 pipe_mode->crtc_clock > clock_limit) { 2312 clock_limit = i915->max_dotclk_freq; 2313 crtc_state->double_wide = true; 2314 } 2315 } 2316 2317 if (pipe_mode->crtc_clock > clock_limit) { 2318 drm_dbg_kms(&i915->drm, 2319 "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", 2320 crtc->base.base.id, crtc->base.name, 2321 pipe_mode->crtc_clock, clock_limit, 2322 str_yes_no(crtc_state->double_wide)); 2323 return -EINVAL; 2324 } 2325 2326 return 0; 2327 } 2328 2329 static int intel_crtc_compute_config(struct intel_atomic_state *state, 2330 struct intel_crtc *crtc) 2331 { 2332 struct intel_crtc_state *crtc_state = 2333 intel_atomic_get_new_crtc_state(state, crtc); 2334 int ret; 2335 2336 ret = intel_dpll_crtc_compute_clock(state, crtc); 2337 if (ret) 2338 return ret; 2339 2340 ret = intel_crtc_compute_pipe_src(crtc_state); 2341 if (ret) 2342 return ret; 2343 2344 ret = intel_crtc_compute_pipe_mode(crtc_state); 2345 if (ret) 2346 return ret; 2347 2348 intel_crtc_compute_pixel_rate(crtc_state); 2349 2350 if (crtc_state->has_pch_encoder) 2351 return ilk_fdi_compute_config(crtc, crtc_state); 2352 2353 return 0; 2354 } 2355 2356 static void 2357 intel_reduce_m_n_ratio(u32 *num, u32 *den) 2358 { 2359 while (*num > DATA_LINK_M_N_MASK || 2360 *den > DATA_LINK_M_N_MASK) { 2361 *num >>= 1; 2362 *den >>= 1; 2363 } 2364 } 2365 2366 static void compute_m_n(u32 *ret_m, u32 *ret_n, 2367 u32 m, u32 n, u32 constant_n) 2368 { 2369 if (constant_n) 2370 *ret_n = constant_n; 2371 else 2372 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); 2373 2374 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n); 2375 intel_reduce_m_n_ratio(ret_m, ret_n); 2376 } 2377 2378 void 2379 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes, 2380 int pixel_clock, int link_clock, 2381 struct intel_link_m_n *m_n, 2382 bool fec_enable) 2383 { 2384 u32 data_clock = bits_per_pixel * pixel_clock; 2385 2386 if (fec_enable) 2387 data_clock = intel_dp_mode_to_fec_clock(data_clock); 2388 2389 /* 2390 * Windows/BIOS uses fixed M/N values always. Follow suit. 2391 * 2392 * Also several DP dongles in particular seem to be fussy 2393 * about too large link M/N values. Presumably the 20bit 2394 * value used by Windows/BIOS is acceptable to everyone. 2395 */ 2396 m_n->tu = 64; 2397 compute_m_n(&m_n->data_m, &m_n->data_n, 2398 data_clock, link_clock * nlanes * 8, 2399 0x8000000); 2400 2401 compute_m_n(&m_n->link_m, &m_n->link_n, 2402 pixel_clock, link_clock, 2403 0x80000); 2404 } 2405 2406 void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv) 2407 { 2408 /* 2409 * There may be no VBT; and if the BIOS enabled SSC we can 2410 * just keep using it to avoid unnecessary flicker. Whereas if the 2411 * BIOS isn't using it, don't assume it will work even if the VBT 2412 * indicates as much. 2413 */ 2414 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { 2415 bool bios_lvds_use_ssc = intel_de_read(dev_priv, 2416 PCH_DREF_CONTROL) & 2417 DREF_SSC1_ENABLE; 2418 2419 if (dev_priv->display.vbt.lvds_use_ssc != bios_lvds_use_ssc) { 2420 drm_dbg_kms(&dev_priv->drm, 2421 "SSC %s by BIOS, overriding VBT which says %s\n", 2422 str_enabled_disabled(bios_lvds_use_ssc), 2423 str_enabled_disabled(dev_priv->display.vbt.lvds_use_ssc)); 2424 dev_priv->display.vbt.lvds_use_ssc = bios_lvds_use_ssc; 2425 } 2426 } 2427 } 2428 2429 void intel_zero_m_n(struct intel_link_m_n *m_n) 2430 { 2431 /* corresponds to 0 register value */ 2432 memset(m_n, 0, sizeof(*m_n)); 2433 m_n->tu = 1; 2434 } 2435 2436 void intel_set_m_n(struct drm_i915_private *i915, 2437 const struct intel_link_m_n *m_n, 2438 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 2439 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 2440 { 2441 intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); 2442 intel_de_write(i915, data_n_reg, m_n->data_n); 2443 intel_de_write(i915, link_m_reg, m_n->link_m); 2444 /* 2445 * On BDW+ writing LINK_N arms the double buffered update 2446 * of all the M/N registers, so it must be written last. 2447 */ 2448 intel_de_write(i915, link_n_reg, m_n->link_n); 2449 } 2450 2451 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, 2452 enum transcoder transcoder) 2453 { 2454 if (IS_HASWELL(dev_priv)) 2455 return transcoder == TRANSCODER_EDP; 2456 2457 return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv); 2458 } 2459 2460 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, 2461 enum transcoder transcoder, 2462 const struct intel_link_m_n *m_n) 2463 { 2464 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2465 enum pipe pipe = crtc->pipe; 2466 2467 if (DISPLAY_VER(dev_priv) >= 5) 2468 intel_set_m_n(dev_priv, m_n, 2469 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 2470 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 2471 else 2472 intel_set_m_n(dev_priv, m_n, 2473 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 2474 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 2475 } 2476 2477 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, 2478 enum transcoder transcoder, 2479 const struct intel_link_m_n *m_n) 2480 { 2481 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2482 2483 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 2484 return; 2485 2486 intel_set_m_n(dev_priv, m_n, 2487 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 2488 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 2489 } 2490 2491 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) 2492 { 2493 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2494 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2495 enum pipe pipe = crtc->pipe; 2496 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2497 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2498 u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end; 2499 int vsyncshift = 0; 2500 2501 /* We need to be careful not to changed the adjusted mode, for otherwise 2502 * the hw state checker will get angry at the mismatch. */ 2503 crtc_vdisplay = adjusted_mode->crtc_vdisplay; 2504 crtc_vtotal = adjusted_mode->crtc_vtotal; 2505 crtc_vblank_start = adjusted_mode->crtc_vblank_start; 2506 crtc_vblank_end = adjusted_mode->crtc_vblank_end; 2507 2508 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 2509 /* the chip adds 2 halflines automatically */ 2510 crtc_vtotal -= 1; 2511 crtc_vblank_end -= 1; 2512 2513 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 2514 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; 2515 else 2516 vsyncshift = adjusted_mode->crtc_hsync_start - 2517 adjusted_mode->crtc_htotal / 2; 2518 if (vsyncshift < 0) 2519 vsyncshift += adjusted_mode->crtc_htotal; 2520 } 2521 2522 /* 2523 * VBLANK_START no longer works on ADL+, instead we must use 2524 * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start. 2525 */ 2526 if (DISPLAY_VER(dev_priv) >= 13) { 2527 intel_de_write(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder), 2528 crtc_vblank_start - crtc_vdisplay); 2529 2530 /* 2531 * VBLANK_START not used by hw, just clear it 2532 * to make it stand out in register dumps. 2533 */ 2534 crtc_vblank_start = 1; 2535 } 2536 2537 if (DISPLAY_VER(dev_priv) > 3) 2538 intel_de_write(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder), 2539 vsyncshift); 2540 2541 intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder), 2542 HACTIVE(adjusted_mode->crtc_hdisplay - 1) | 2543 HTOTAL(adjusted_mode->crtc_htotal - 1)); 2544 intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder), 2545 HBLANK_START(adjusted_mode->crtc_hblank_start - 1) | 2546 HBLANK_END(adjusted_mode->crtc_hblank_end - 1)); 2547 intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder), 2548 HSYNC_START(adjusted_mode->crtc_hsync_start - 1) | 2549 HSYNC_END(adjusted_mode->crtc_hsync_end - 1)); 2550 2551 intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder), 2552 VACTIVE(crtc_vdisplay - 1) | 2553 VTOTAL(crtc_vtotal - 1)); 2554 intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), 2555 VBLANK_START(crtc_vblank_start - 1) | 2556 VBLANK_END(crtc_vblank_end - 1)); 2557 intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder), 2558 VSYNC_START(adjusted_mode->crtc_vsync_start - 1) | 2559 VSYNC_END(adjusted_mode->crtc_vsync_end - 1)); 2560 2561 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be 2562 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is 2563 * documented on the DDI_FUNC_CTL register description, EDP Input Select 2564 * bits. */ 2565 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && 2566 (pipe == PIPE_B || pipe == PIPE_C)) 2567 intel_de_write(dev_priv, TRANS_VTOTAL(pipe), 2568 VACTIVE(crtc_vdisplay - 1) | 2569 VTOTAL(crtc_vtotal - 1)); 2570 } 2571 2572 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) 2573 { 2574 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2575 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2576 int width = drm_rect_width(&crtc_state->pipe_src); 2577 int height = drm_rect_height(&crtc_state->pipe_src); 2578 enum pipe pipe = crtc->pipe; 2579 2580 /* pipesrc controls the size that is scaled from, which should 2581 * always be the user's requested size. 2582 */ 2583 intel_de_write(dev_priv, PIPESRC(pipe), 2584 PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1)); 2585 } 2586 2587 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) 2588 { 2589 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2590 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2591 2592 if (DISPLAY_VER(dev_priv) == 2) 2593 return false; 2594 2595 if (DISPLAY_VER(dev_priv) >= 9 || 2596 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2597 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW; 2598 else 2599 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK; 2600 } 2601 2602 static void intel_get_transcoder_timings(struct intel_crtc *crtc, 2603 struct intel_crtc_state *pipe_config) 2604 { 2605 struct drm_device *dev = crtc->base.dev; 2606 struct drm_i915_private *dev_priv = to_i915(dev); 2607 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 2608 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2609 u32 tmp; 2610 2611 tmp = intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder)); 2612 adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1; 2613 adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1; 2614 2615 if (!transcoder_is_dsi(cpu_transcoder)) { 2616 tmp = intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder)); 2617 adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1; 2618 adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1; 2619 } 2620 2621 tmp = intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder)); 2622 adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1; 2623 adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1; 2624 2625 tmp = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder)); 2626 adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1; 2627 adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1; 2628 2629 /* FIXME TGL+ DSI transcoders have this! */ 2630 if (!transcoder_is_dsi(cpu_transcoder)) { 2631 tmp = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder)); 2632 adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1; 2633 adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1; 2634 } 2635 tmp = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder)); 2636 adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1; 2637 adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1; 2638 2639 if (intel_pipe_is_interlaced(pipe_config)) { 2640 adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE; 2641 adjusted_mode->crtc_vtotal += 1; 2642 adjusted_mode->crtc_vblank_end += 1; 2643 } 2644 2645 if (DISPLAY_VER(dev_priv) >= 13 && !transcoder_is_dsi(cpu_transcoder)) 2646 adjusted_mode->crtc_vblank_start = 2647 adjusted_mode->crtc_vdisplay + 2648 intel_de_read(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder)); 2649 } 2650 2651 static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state) 2652 { 2653 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2654 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2655 enum pipe master_pipe, pipe = crtc->pipe; 2656 int width; 2657 2658 if (num_pipes < 2) 2659 return; 2660 2661 master_pipe = bigjoiner_master_pipe(crtc_state); 2662 width = drm_rect_width(&crtc_state->pipe_src); 2663 2664 drm_rect_translate_to(&crtc_state->pipe_src, 2665 (pipe - master_pipe) * width, 0); 2666 } 2667 2668 static void intel_get_pipe_src_size(struct intel_crtc *crtc, 2669 struct intel_crtc_state *pipe_config) 2670 { 2671 struct drm_device *dev = crtc->base.dev; 2672 struct drm_i915_private *dev_priv = to_i915(dev); 2673 u32 tmp; 2674 2675 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe)); 2676 2677 drm_rect_init(&pipe_config->pipe_src, 0, 0, 2678 REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1, 2679 REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1); 2680 2681 intel_bigjoiner_adjust_pipe_src(pipe_config); 2682 } 2683 2684 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) 2685 { 2686 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2687 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2688 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2689 u32 val = 0; 2690 2691 /* 2692 * - We keep both pipes enabled on 830 2693 * - During modeset the pipe is still disabled and must remain so 2694 * - During fastset the pipe is already enabled and must remain so 2695 */ 2696 if (IS_I830(dev_priv) || !intel_crtc_needs_modeset(crtc_state)) 2697 val |= TRANSCONF_ENABLE; 2698 2699 if (crtc_state->double_wide) 2700 val |= TRANSCONF_DOUBLE_WIDE; 2701 2702 /* only g4x and later have fancy bpc/dither controls */ 2703 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 2704 IS_CHERRYVIEW(dev_priv)) { 2705 /* Bspec claims that we can't use dithering for 30bpp pipes. */ 2706 if (crtc_state->dither && crtc_state->pipe_bpp != 30) 2707 val |= TRANSCONF_DITHER_EN | 2708 TRANSCONF_DITHER_TYPE_SP; 2709 2710 switch (crtc_state->pipe_bpp) { 2711 default: 2712 /* Case prevented by intel_choose_pipe_bpp_dither. */ 2713 MISSING_CASE(crtc_state->pipe_bpp); 2714 fallthrough; 2715 case 18: 2716 val |= TRANSCONF_BPC_6; 2717 break; 2718 case 24: 2719 val |= TRANSCONF_BPC_8; 2720 break; 2721 case 30: 2722 val |= TRANSCONF_BPC_10; 2723 break; 2724 } 2725 } 2726 2727 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 2728 if (DISPLAY_VER(dev_priv) < 4 || 2729 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 2730 val |= TRANSCONF_INTERLACE_W_FIELD_INDICATION; 2731 else 2732 val |= TRANSCONF_INTERLACE_W_SYNC_SHIFT; 2733 } else { 2734 val |= TRANSCONF_INTERLACE_PROGRESSIVE; 2735 } 2736 2737 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 2738 crtc_state->limited_color_range) 2739 val |= TRANSCONF_COLOR_RANGE_SELECT; 2740 2741 val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode); 2742 2743 if (crtc_state->wgc_enable) 2744 val |= TRANSCONF_WGC_ENABLE; 2745 2746 val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 2747 2748 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); 2749 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); 2750 } 2751 2752 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv) 2753 { 2754 if (IS_I830(dev_priv)) 2755 return false; 2756 2757 return DISPLAY_VER(dev_priv) >= 4 || 2758 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); 2759 } 2760 2761 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state) 2762 { 2763 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2764 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2765 enum pipe pipe; 2766 u32 tmp; 2767 2768 if (!i9xx_has_pfit(dev_priv)) 2769 return; 2770 2771 tmp = intel_de_read(dev_priv, PFIT_CONTROL); 2772 if (!(tmp & PFIT_ENABLE)) 2773 return; 2774 2775 /* Check whether the pfit is attached to our pipe. */ 2776 if (DISPLAY_VER(dev_priv) >= 4) 2777 pipe = REG_FIELD_GET(PFIT_PIPE_MASK, tmp); 2778 else 2779 pipe = PIPE_B; 2780 2781 if (pipe != crtc->pipe) 2782 return; 2783 2784 crtc_state->gmch_pfit.control = tmp; 2785 crtc_state->gmch_pfit.pgm_ratios = 2786 intel_de_read(dev_priv, PFIT_PGM_RATIOS); 2787 } 2788 2789 static void vlv_crtc_clock_get(struct intel_crtc *crtc, 2790 struct intel_crtc_state *pipe_config) 2791 { 2792 struct drm_device *dev = crtc->base.dev; 2793 struct drm_i915_private *dev_priv = to_i915(dev); 2794 enum pipe pipe = crtc->pipe; 2795 struct dpll clock; 2796 u32 mdiv; 2797 int refclk = 100000; 2798 2799 /* In case of DSI, DPLL will not be used */ 2800 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 2801 return; 2802 2803 vlv_dpio_get(dev_priv); 2804 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); 2805 vlv_dpio_put(dev_priv); 2806 2807 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; 2808 clock.m2 = mdiv & DPIO_M2DIV_MASK; 2809 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; 2810 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; 2811 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; 2812 2813 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); 2814 } 2815 2816 static void chv_crtc_clock_get(struct intel_crtc *crtc, 2817 struct intel_crtc_state *pipe_config) 2818 { 2819 struct drm_device *dev = crtc->base.dev; 2820 struct drm_i915_private *dev_priv = to_i915(dev); 2821 enum pipe pipe = crtc->pipe; 2822 enum dpio_channel port = vlv_pipe_to_channel(pipe); 2823 struct dpll clock; 2824 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; 2825 int refclk = 100000; 2826 2827 /* In case of DSI, DPLL will not be used */ 2828 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 2829 return; 2830 2831 vlv_dpio_get(dev_priv); 2832 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); 2833 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); 2834 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); 2835 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); 2836 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); 2837 vlv_dpio_put(dev_priv); 2838 2839 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; 2840 clock.m2 = (pll_dw0 & 0xff) << 22; 2841 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) 2842 clock.m2 |= pll_dw2 & 0x3fffff; 2843 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; 2844 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; 2845 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; 2846 2847 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); 2848 } 2849 2850 static enum intel_output_format 2851 bdw_get_pipe_misc_output_format(struct intel_crtc *crtc) 2852 { 2853 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2854 u32 tmp; 2855 2856 tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe)); 2857 2858 if (tmp & PIPE_MISC_YUV420_ENABLE) { 2859 /* We support 4:2:0 in full blend mode only */ 2860 drm_WARN_ON(&dev_priv->drm, 2861 (tmp & PIPE_MISC_YUV420_MODE_FULL_BLEND) == 0); 2862 2863 return INTEL_OUTPUT_FORMAT_YCBCR420; 2864 } else if (tmp & PIPE_MISC_OUTPUT_COLORSPACE_YUV) { 2865 return INTEL_OUTPUT_FORMAT_YCBCR444; 2866 } else { 2867 return INTEL_OUTPUT_FORMAT_RGB; 2868 } 2869 } 2870 2871 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state) 2872 { 2873 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2874 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 2875 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2876 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 2877 u32 tmp; 2878 2879 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); 2880 2881 if (tmp & DISP_PIPE_GAMMA_ENABLE) 2882 crtc_state->gamma_enable = true; 2883 2884 if (!HAS_GMCH(dev_priv) && 2885 tmp & DISP_PIPE_CSC_ENABLE) 2886 crtc_state->csc_enable = true; 2887 } 2888 2889 static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 2890 struct intel_crtc_state *pipe_config) 2891 { 2892 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2893 enum intel_display_power_domain power_domain; 2894 intel_wakeref_t wakeref; 2895 u32 tmp; 2896 bool ret; 2897 2898 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 2899 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 2900 if (!wakeref) 2901 return false; 2902 2903 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 2904 pipe_config->sink_format = pipe_config->output_format; 2905 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 2906 pipe_config->shared_dpll = NULL; 2907 2908 ret = false; 2909 2910 tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder)); 2911 if (!(tmp & TRANSCONF_ENABLE)) 2912 goto out; 2913 2914 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 2915 IS_CHERRYVIEW(dev_priv)) { 2916 switch (tmp & TRANSCONF_BPC_MASK) { 2917 case TRANSCONF_BPC_6: 2918 pipe_config->pipe_bpp = 18; 2919 break; 2920 case TRANSCONF_BPC_8: 2921 pipe_config->pipe_bpp = 24; 2922 break; 2923 case TRANSCONF_BPC_10: 2924 pipe_config->pipe_bpp = 30; 2925 break; 2926 default: 2927 MISSING_CASE(tmp); 2928 break; 2929 } 2930 } 2931 2932 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 2933 (tmp & TRANSCONF_COLOR_RANGE_SELECT)) 2934 pipe_config->limited_color_range = true; 2935 2936 pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp); 2937 2938 pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1; 2939 2940 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 2941 (tmp & TRANSCONF_WGC_ENABLE)) 2942 pipe_config->wgc_enable = true; 2943 2944 if (IS_CHERRYVIEW(dev_priv)) 2945 pipe_config->cgm_mode = intel_de_read(dev_priv, 2946 CGM_PIPE_MODE(crtc->pipe)); 2947 2948 i9xx_get_pipe_color_config(pipe_config); 2949 intel_color_get_config(pipe_config); 2950 2951 if (DISPLAY_VER(dev_priv) < 4) 2952 pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE; 2953 2954 intel_get_transcoder_timings(crtc, pipe_config); 2955 intel_get_pipe_src_size(crtc, pipe_config); 2956 2957 i9xx_get_pfit_config(pipe_config); 2958 2959 if (DISPLAY_VER(dev_priv) >= 4) { 2960 /* No way to read it out on pipes B and C */ 2961 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) 2962 tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe]; 2963 else 2964 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe)); 2965 pipe_config->pixel_multiplier = 2966 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) 2967 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; 2968 pipe_config->dpll_hw_state.dpll_md = tmp; 2969 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 2970 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 2971 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe)); 2972 pipe_config->pixel_multiplier = 2973 ((tmp & SDVO_MULTIPLIER_MASK) 2974 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; 2975 } else { 2976 /* Note that on i915G/GM the pixel multiplier is in the sdvo 2977 * port and will be fixed up in the encoder->get_config 2978 * function. */ 2979 pipe_config->pixel_multiplier = 1; 2980 } 2981 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv, 2982 DPLL(crtc->pipe)); 2983 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 2984 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv, 2985 FP0(crtc->pipe)); 2986 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv, 2987 FP1(crtc->pipe)); 2988 } else { 2989 /* Mask out read-only status bits. */ 2990 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | 2991 DPLL_PORTC_READY_MASK | 2992 DPLL_PORTB_READY_MASK); 2993 } 2994 2995 if (IS_CHERRYVIEW(dev_priv)) 2996 chv_crtc_clock_get(crtc, pipe_config); 2997 else if (IS_VALLEYVIEW(dev_priv)) 2998 vlv_crtc_clock_get(crtc, pipe_config); 2999 else 3000 i9xx_crtc_clock_get(crtc, pipe_config); 3001 3002 /* 3003 * Normally the dotclock is filled in by the encoder .get_config() 3004 * but in case the pipe is enabled w/o any ports we need a sane 3005 * default. 3006 */ 3007 pipe_config->hw.adjusted_mode.crtc_clock = 3008 pipe_config->port_clock / pipe_config->pixel_multiplier; 3009 3010 ret = true; 3011 3012 out: 3013 intel_display_power_put(dev_priv, power_domain, wakeref); 3014 3015 return ret; 3016 } 3017 3018 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) 3019 { 3020 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3021 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3022 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3023 u32 val = 0; 3024 3025 /* 3026 * - During modeset the pipe is still disabled and must remain so 3027 * - During fastset the pipe is already enabled and must remain so 3028 */ 3029 if (!intel_crtc_needs_modeset(crtc_state)) 3030 val |= TRANSCONF_ENABLE; 3031 3032 switch (crtc_state->pipe_bpp) { 3033 default: 3034 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3035 MISSING_CASE(crtc_state->pipe_bpp); 3036 fallthrough; 3037 case 18: 3038 val |= TRANSCONF_BPC_6; 3039 break; 3040 case 24: 3041 val |= TRANSCONF_BPC_8; 3042 break; 3043 case 30: 3044 val |= TRANSCONF_BPC_10; 3045 break; 3046 case 36: 3047 val |= TRANSCONF_BPC_12; 3048 break; 3049 } 3050 3051 if (crtc_state->dither) 3052 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP; 3053 3054 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3055 val |= TRANSCONF_INTERLACE_IF_ID_ILK; 3056 else 3057 val |= TRANSCONF_INTERLACE_PF_PD_ILK; 3058 3059 /* 3060 * This would end up with an odd purple hue over 3061 * the entire display. Make sure we don't do it. 3062 */ 3063 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 3064 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 3065 3066 if (crtc_state->limited_color_range && 3067 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3068 val |= TRANSCONF_COLOR_RANGE_SELECT; 3069 3070 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3071 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV709; 3072 3073 val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode); 3074 3075 val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3076 val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay); 3077 3078 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); 3079 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); 3080 } 3081 3082 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) 3083 { 3084 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3085 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3086 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3087 u32 val = 0; 3088 3089 /* 3090 * - During modeset the pipe is still disabled and must remain so 3091 * - During fastset the pipe is already enabled and must remain so 3092 */ 3093 if (!intel_crtc_needs_modeset(crtc_state)) 3094 val |= TRANSCONF_ENABLE; 3095 3096 if (IS_HASWELL(dev_priv) && crtc_state->dither) 3097 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP; 3098 3099 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3100 val |= TRANSCONF_INTERLACE_IF_ID_ILK; 3101 else 3102 val |= TRANSCONF_INTERLACE_PF_PD_ILK; 3103 3104 if (IS_HASWELL(dev_priv) && 3105 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3106 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW; 3107 3108 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); 3109 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); 3110 } 3111 3112 static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state) 3113 { 3114 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3115 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3116 u32 val = 0; 3117 3118 switch (crtc_state->pipe_bpp) { 3119 case 18: 3120 val |= PIPE_MISC_BPC_6; 3121 break; 3122 case 24: 3123 val |= PIPE_MISC_BPC_8; 3124 break; 3125 case 30: 3126 val |= PIPE_MISC_BPC_10; 3127 break; 3128 case 36: 3129 /* Port output 12BPC defined for ADLP+ */ 3130 if (DISPLAY_VER(dev_priv) > 12) 3131 val |= PIPE_MISC_BPC_12_ADLP; 3132 break; 3133 default: 3134 MISSING_CASE(crtc_state->pipe_bpp); 3135 break; 3136 } 3137 3138 if (crtc_state->dither) 3139 val |= PIPE_MISC_DITHER_ENABLE | PIPE_MISC_DITHER_TYPE_SP; 3140 3141 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 3142 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 3143 val |= PIPE_MISC_OUTPUT_COLORSPACE_YUV; 3144 3145 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 3146 val |= PIPE_MISC_YUV420_ENABLE | 3147 PIPE_MISC_YUV420_MODE_FULL_BLEND; 3148 3149 if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state)) 3150 val |= PIPE_MISC_HDR_MODE_PRECISION; 3151 3152 if (DISPLAY_VER(dev_priv) >= 12) 3153 val |= PIPE_MISC_PIXEL_ROUNDING_TRUNC; 3154 3155 /* allow PSR with sprite enabled */ 3156 if (IS_BROADWELL(dev_priv)) 3157 val |= PIPE_MISC_PSR_MASK_SPRITE_ENABLE; 3158 3159 intel_de_write(dev_priv, PIPE_MISC(crtc->pipe), val); 3160 } 3161 3162 int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc) 3163 { 3164 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3165 u32 tmp; 3166 3167 tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe)); 3168 3169 switch (tmp & PIPE_MISC_BPC_MASK) { 3170 case PIPE_MISC_BPC_6: 3171 return 18; 3172 case PIPE_MISC_BPC_8: 3173 return 24; 3174 case PIPE_MISC_BPC_10: 3175 return 30; 3176 /* 3177 * PORT OUTPUT 12 BPC defined for ADLP+. 3178 * 3179 * TODO: 3180 * For previous platforms with DSI interface, bits 5:7 3181 * are used for storing pipe_bpp irrespective of dithering. 3182 * Since the value of 12 BPC is not defined for these bits 3183 * on older platforms, need to find a workaround for 12 BPC 3184 * MIPI DSI HW readout. 3185 */ 3186 case PIPE_MISC_BPC_12_ADLP: 3187 if (DISPLAY_VER(dev_priv) > 12) 3188 return 36; 3189 fallthrough; 3190 default: 3191 MISSING_CASE(tmp); 3192 return 0; 3193 } 3194 } 3195 3196 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) 3197 { 3198 /* 3199 * Account for spread spectrum to avoid 3200 * oversubscribing the link. Max center spread 3201 * is 2.5%; use 5% for safety's sake. 3202 */ 3203 u32 bps = target_clock * bpp * 21 / 20; 3204 return DIV_ROUND_UP(bps, link_bw * 8); 3205 } 3206 3207 void intel_get_m_n(struct drm_i915_private *i915, 3208 struct intel_link_m_n *m_n, 3209 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 3210 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 3211 { 3212 m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK; 3213 m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK; 3214 m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK; 3215 m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK; 3216 m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1; 3217 } 3218 3219 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, 3220 enum transcoder transcoder, 3221 struct intel_link_m_n *m_n) 3222 { 3223 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3224 enum pipe pipe = crtc->pipe; 3225 3226 if (DISPLAY_VER(dev_priv) >= 5) 3227 intel_get_m_n(dev_priv, m_n, 3228 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 3229 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 3230 else 3231 intel_get_m_n(dev_priv, m_n, 3232 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 3233 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 3234 } 3235 3236 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, 3237 enum transcoder transcoder, 3238 struct intel_link_m_n *m_n) 3239 { 3240 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3241 3242 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 3243 return; 3244 3245 intel_get_m_n(dev_priv, m_n, 3246 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 3247 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 3248 } 3249 3250 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state) 3251 { 3252 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3253 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3254 u32 ctl, pos, size; 3255 enum pipe pipe; 3256 3257 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe)); 3258 if ((ctl & PF_ENABLE) == 0) 3259 return; 3260 3261 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) 3262 pipe = REG_FIELD_GET(PF_PIPE_SEL_MASK_IVB, ctl); 3263 else 3264 pipe = crtc->pipe; 3265 3266 crtc_state->pch_pfit.enabled = true; 3267 3268 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe)); 3269 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe)); 3270 3271 drm_rect_init(&crtc_state->pch_pfit.dst, 3272 REG_FIELD_GET(PF_WIN_XPOS_MASK, pos), 3273 REG_FIELD_GET(PF_WIN_YPOS_MASK, pos), 3274 REG_FIELD_GET(PF_WIN_XSIZE_MASK, size), 3275 REG_FIELD_GET(PF_WIN_YSIZE_MASK, size)); 3276 3277 /* 3278 * We currently do not free assignements of panel fitters on 3279 * ivb/hsw (since we don't use the higher upscaling modes which 3280 * differentiates them) so just WARN about this case for now. 3281 */ 3282 drm_WARN_ON(&dev_priv->drm, pipe != crtc->pipe); 3283 } 3284 3285 static bool ilk_get_pipe_config(struct intel_crtc *crtc, 3286 struct intel_crtc_state *pipe_config) 3287 { 3288 struct drm_device *dev = crtc->base.dev; 3289 struct drm_i915_private *dev_priv = to_i915(dev); 3290 enum intel_display_power_domain power_domain; 3291 intel_wakeref_t wakeref; 3292 u32 tmp; 3293 bool ret; 3294 3295 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3296 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3297 if (!wakeref) 3298 return false; 3299 3300 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3301 pipe_config->shared_dpll = NULL; 3302 3303 ret = false; 3304 tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder)); 3305 if (!(tmp & TRANSCONF_ENABLE)) 3306 goto out; 3307 3308 switch (tmp & TRANSCONF_BPC_MASK) { 3309 case TRANSCONF_BPC_6: 3310 pipe_config->pipe_bpp = 18; 3311 break; 3312 case TRANSCONF_BPC_8: 3313 pipe_config->pipe_bpp = 24; 3314 break; 3315 case TRANSCONF_BPC_10: 3316 pipe_config->pipe_bpp = 30; 3317 break; 3318 case TRANSCONF_BPC_12: 3319 pipe_config->pipe_bpp = 36; 3320 break; 3321 default: 3322 break; 3323 } 3324 3325 if (tmp & TRANSCONF_COLOR_RANGE_SELECT) 3326 pipe_config->limited_color_range = true; 3327 3328 switch (tmp & TRANSCONF_OUTPUT_COLORSPACE_MASK) { 3329 case TRANSCONF_OUTPUT_COLORSPACE_YUV601: 3330 case TRANSCONF_OUTPUT_COLORSPACE_YUV709: 3331 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3332 break; 3333 default: 3334 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3335 break; 3336 } 3337 3338 pipe_config->sink_format = pipe_config->output_format; 3339 3340 pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp); 3341 3342 pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1; 3343 3344 pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp); 3345 3346 pipe_config->csc_mode = intel_de_read(dev_priv, 3347 PIPE_CSC_MODE(crtc->pipe)); 3348 3349 i9xx_get_pipe_color_config(pipe_config); 3350 intel_color_get_config(pipe_config); 3351 3352 pipe_config->pixel_multiplier = 1; 3353 3354 ilk_pch_get_config(pipe_config); 3355 3356 intel_get_transcoder_timings(crtc, pipe_config); 3357 intel_get_pipe_src_size(crtc, pipe_config); 3358 3359 ilk_get_pfit_config(pipe_config); 3360 3361 ret = true; 3362 3363 out: 3364 intel_display_power_put(dev_priv, power_domain, wakeref); 3365 3366 return ret; 3367 } 3368 3369 static u8 bigjoiner_pipes(struct drm_i915_private *i915) 3370 { 3371 u8 pipes; 3372 3373 if (DISPLAY_VER(i915) >= 12) 3374 pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D); 3375 else if (DISPLAY_VER(i915) >= 11) 3376 pipes = BIT(PIPE_B) | BIT(PIPE_C); 3377 else 3378 pipes = 0; 3379 3380 return pipes & DISPLAY_RUNTIME_INFO(i915)->pipe_mask; 3381 } 3382 3383 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv, 3384 enum transcoder cpu_transcoder) 3385 { 3386 enum intel_display_power_domain power_domain; 3387 intel_wakeref_t wakeref; 3388 u32 tmp = 0; 3389 3390 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3391 3392 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3393 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3394 3395 return tmp & TRANS_DDI_FUNC_ENABLE; 3396 } 3397 3398 static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv, 3399 u8 *master_pipes, u8 *slave_pipes) 3400 { 3401 struct intel_crtc *crtc; 3402 3403 *master_pipes = 0; 3404 *slave_pipes = 0; 3405 3406 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, 3407 bigjoiner_pipes(dev_priv)) { 3408 enum intel_display_power_domain power_domain; 3409 enum pipe pipe = crtc->pipe; 3410 intel_wakeref_t wakeref; 3411 3412 power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe); 3413 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3414 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3415 3416 if (!(tmp & BIG_JOINER_ENABLE)) 3417 continue; 3418 3419 if (tmp & MASTER_BIG_JOINER_ENABLE) 3420 *master_pipes |= BIT(pipe); 3421 else 3422 *slave_pipes |= BIT(pipe); 3423 } 3424 3425 if (DISPLAY_VER(dev_priv) < 13) 3426 continue; 3427 3428 power_domain = POWER_DOMAIN_PIPE(pipe); 3429 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3430 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3431 3432 if (tmp & UNCOMPRESSED_JOINER_MASTER) 3433 *master_pipes |= BIT(pipe); 3434 if (tmp & UNCOMPRESSED_JOINER_SLAVE) 3435 *slave_pipes |= BIT(pipe); 3436 } 3437 } 3438 3439 /* Bigjoiner pipes should always be consecutive master and slave */ 3440 drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1, 3441 "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n", 3442 *master_pipes, *slave_pipes); 3443 } 3444 3445 static enum pipe get_bigjoiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3446 { 3447 if ((slave_pipes & BIT(pipe)) == 0) 3448 return pipe; 3449 3450 /* ignore everything above our pipe */ 3451 master_pipes &= ~GENMASK(7, pipe); 3452 3453 /* highest remaining bit should be our master pipe */ 3454 return fls(master_pipes) - 1; 3455 } 3456 3457 static u8 get_bigjoiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3458 { 3459 enum pipe master_pipe, next_master_pipe; 3460 3461 master_pipe = get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes); 3462 3463 if ((master_pipes & BIT(master_pipe)) == 0) 3464 return 0; 3465 3466 /* ignore our master pipe and everything below it */ 3467 master_pipes &= ~GENMASK(master_pipe, 0); 3468 /* make sure a high bit is set for the ffs() */ 3469 master_pipes |= BIT(7); 3470 /* lowest remaining bit should be the next master pipe */ 3471 next_master_pipe = ffs(master_pipes) - 1; 3472 3473 return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe); 3474 } 3475 3476 static u8 hsw_panel_transcoders(struct drm_i915_private *i915) 3477 { 3478 u8 panel_transcoder_mask = BIT(TRANSCODER_EDP); 3479 3480 if (DISPLAY_VER(i915) >= 11) 3481 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); 3482 3483 return panel_transcoder_mask; 3484 } 3485 3486 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) 3487 { 3488 struct drm_device *dev = crtc->base.dev; 3489 struct drm_i915_private *dev_priv = to_i915(dev); 3490 u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv); 3491 enum transcoder cpu_transcoder; 3492 u8 master_pipes, slave_pipes; 3493 u8 enabled_transcoders = 0; 3494 3495 /* 3496 * XXX: Do intel_display_power_get_if_enabled before reading this (for 3497 * consistency and less surprising code; it's in always on power). 3498 */ 3499 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, 3500 panel_transcoder_mask) { 3501 enum intel_display_power_domain power_domain; 3502 intel_wakeref_t wakeref; 3503 enum pipe trans_pipe; 3504 u32 tmp = 0; 3505 3506 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3507 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3508 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3509 3510 if (!(tmp & TRANS_DDI_FUNC_ENABLE)) 3511 continue; 3512 3513 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 3514 default: 3515 drm_WARN(dev, 1, 3516 "unknown pipe linked to transcoder %s\n", 3517 transcoder_name(cpu_transcoder)); 3518 fallthrough; 3519 case TRANS_DDI_EDP_INPUT_A_ONOFF: 3520 case TRANS_DDI_EDP_INPUT_A_ON: 3521 trans_pipe = PIPE_A; 3522 break; 3523 case TRANS_DDI_EDP_INPUT_B_ONOFF: 3524 trans_pipe = PIPE_B; 3525 break; 3526 case TRANS_DDI_EDP_INPUT_C_ONOFF: 3527 trans_pipe = PIPE_C; 3528 break; 3529 case TRANS_DDI_EDP_INPUT_D_ONOFF: 3530 trans_pipe = PIPE_D; 3531 break; 3532 } 3533 3534 if (trans_pipe == crtc->pipe) 3535 enabled_transcoders |= BIT(cpu_transcoder); 3536 } 3537 3538 /* single pipe or bigjoiner master */ 3539 cpu_transcoder = (enum transcoder) crtc->pipe; 3540 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 3541 enabled_transcoders |= BIT(cpu_transcoder); 3542 3543 /* bigjoiner slave -> consider the master pipe's transcoder as well */ 3544 enabled_bigjoiner_pipes(dev_priv, &master_pipes, &slave_pipes); 3545 if (slave_pipes & BIT(crtc->pipe)) { 3546 cpu_transcoder = (enum transcoder) 3547 get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes); 3548 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 3549 enabled_transcoders |= BIT(cpu_transcoder); 3550 } 3551 3552 return enabled_transcoders; 3553 } 3554 3555 static bool has_edp_transcoders(u8 enabled_transcoders) 3556 { 3557 return enabled_transcoders & BIT(TRANSCODER_EDP); 3558 } 3559 3560 static bool has_dsi_transcoders(u8 enabled_transcoders) 3561 { 3562 return enabled_transcoders & (BIT(TRANSCODER_DSI_0) | 3563 BIT(TRANSCODER_DSI_1)); 3564 } 3565 3566 static bool has_pipe_transcoders(u8 enabled_transcoders) 3567 { 3568 return enabled_transcoders & ~(BIT(TRANSCODER_EDP) | 3569 BIT(TRANSCODER_DSI_0) | 3570 BIT(TRANSCODER_DSI_1)); 3571 } 3572 3573 static void assert_enabled_transcoders(struct drm_i915_private *i915, 3574 u8 enabled_transcoders) 3575 { 3576 /* Only one type of transcoder please */ 3577 drm_WARN_ON(&i915->drm, 3578 has_edp_transcoders(enabled_transcoders) + 3579 has_dsi_transcoders(enabled_transcoders) + 3580 has_pipe_transcoders(enabled_transcoders) > 1); 3581 3582 /* Only DSI transcoders can be ganged */ 3583 drm_WARN_ON(&i915->drm, 3584 !has_dsi_transcoders(enabled_transcoders) && 3585 !is_power_of_2(enabled_transcoders)); 3586 } 3587 3588 static bool hsw_get_transcoder_state(struct intel_crtc *crtc, 3589 struct intel_crtc_state *pipe_config, 3590 struct intel_display_power_domain_set *power_domain_set) 3591 { 3592 struct drm_device *dev = crtc->base.dev; 3593 struct drm_i915_private *dev_priv = to_i915(dev); 3594 unsigned long enabled_transcoders; 3595 u32 tmp; 3596 3597 enabled_transcoders = hsw_enabled_transcoders(crtc); 3598 if (!enabled_transcoders) 3599 return false; 3600 3601 assert_enabled_transcoders(dev_priv, enabled_transcoders); 3602 3603 /* 3604 * With the exception of DSI we should only ever have 3605 * a single enabled transcoder. With DSI let's just 3606 * pick the first one. 3607 */ 3608 pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1; 3609 3610 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 3611 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) 3612 return false; 3613 3614 if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) { 3615 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); 3616 3617 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF) 3618 pipe_config->pch_pfit.force_thru = true; 3619 } 3620 3621 tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder)); 3622 3623 return tmp & TRANSCONF_ENABLE; 3624 } 3625 3626 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, 3627 struct intel_crtc_state *pipe_config, 3628 struct intel_display_power_domain_set *power_domain_set) 3629 { 3630 struct drm_device *dev = crtc->base.dev; 3631 struct drm_i915_private *dev_priv = to_i915(dev); 3632 enum transcoder cpu_transcoder; 3633 enum port port; 3634 u32 tmp; 3635 3636 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { 3637 if (port == PORT_A) 3638 cpu_transcoder = TRANSCODER_DSI_A; 3639 else 3640 cpu_transcoder = TRANSCODER_DSI_C; 3641 3642 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 3643 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) 3644 continue; 3645 3646 /* 3647 * The PLL needs to be enabled with a valid divider 3648 * configuration, otherwise accessing DSI registers will hang 3649 * the machine. See BSpec North Display Engine 3650 * registers/MIPI[BXT]. We can break out here early, since we 3651 * need the same DSI PLL to be enabled for both DSI ports. 3652 */ 3653 if (!bxt_dsi_pll_is_enabled(dev_priv)) 3654 break; 3655 3656 /* XXX: this works for video mode only */ 3657 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); 3658 if (!(tmp & DPI_ENABLE)) 3659 continue; 3660 3661 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 3662 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) 3663 continue; 3664 3665 pipe_config->cpu_transcoder = cpu_transcoder; 3666 break; 3667 } 3668 3669 return transcoder_is_dsi(pipe_config->cpu_transcoder); 3670 } 3671 3672 static void intel_bigjoiner_get_config(struct intel_crtc_state *crtc_state) 3673 { 3674 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3675 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 3676 u8 master_pipes, slave_pipes; 3677 enum pipe pipe = crtc->pipe; 3678 3679 enabled_bigjoiner_pipes(i915, &master_pipes, &slave_pipes); 3680 3681 if (((master_pipes | slave_pipes) & BIT(pipe)) == 0) 3682 return; 3683 3684 crtc_state->bigjoiner_pipes = 3685 BIT(get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes)) | 3686 get_bigjoiner_slave_pipes(pipe, master_pipes, slave_pipes); 3687 } 3688 3689 static bool hsw_get_pipe_config(struct intel_crtc *crtc, 3690 struct intel_crtc_state *pipe_config) 3691 { 3692 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3693 bool active; 3694 u32 tmp; 3695 3696 if (!intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains, 3697 POWER_DOMAIN_PIPE(crtc->pipe))) 3698 return false; 3699 3700 pipe_config->shared_dpll = NULL; 3701 3702 active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains); 3703 3704 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 3705 bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) { 3706 drm_WARN_ON(&dev_priv->drm, active); 3707 active = true; 3708 } 3709 3710 if (!active) 3711 goto out; 3712 3713 intel_dsc_get_config(pipe_config); 3714 intel_bigjoiner_get_config(pipe_config); 3715 3716 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || 3717 DISPLAY_VER(dev_priv) >= 11) 3718 intel_get_transcoder_timings(crtc, pipe_config); 3719 3720 if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder)) 3721 intel_vrr_get_config(pipe_config); 3722 3723 intel_get_pipe_src_size(crtc, pipe_config); 3724 3725 if (IS_HASWELL(dev_priv)) { 3726 u32 tmp = intel_de_read(dev_priv, 3727 TRANSCONF(pipe_config->cpu_transcoder)); 3728 3729 if (tmp & TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW) 3730 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3731 else 3732 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3733 } else { 3734 pipe_config->output_format = 3735 bdw_get_pipe_misc_output_format(crtc); 3736 } 3737 3738 pipe_config->sink_format = pipe_config->output_format; 3739 3740 pipe_config->gamma_mode = intel_de_read(dev_priv, 3741 GAMMA_MODE(crtc->pipe)); 3742 3743 pipe_config->csc_mode = intel_de_read(dev_priv, 3744 PIPE_CSC_MODE(crtc->pipe)); 3745 3746 if (DISPLAY_VER(dev_priv) >= 9) { 3747 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe)); 3748 3749 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE) 3750 pipe_config->gamma_enable = true; 3751 3752 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE) 3753 pipe_config->csc_enable = true; 3754 } else { 3755 i9xx_get_pipe_color_config(pipe_config); 3756 } 3757 3758 intel_color_get_config(pipe_config); 3759 3760 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe)); 3761 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); 3762 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 3763 pipe_config->ips_linetime = 3764 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); 3765 3766 if (intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains, 3767 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) { 3768 if (DISPLAY_VER(dev_priv) >= 9) 3769 skl_scaler_get_config(pipe_config); 3770 else 3771 ilk_get_pfit_config(pipe_config); 3772 } 3773 3774 hsw_ips_get_config(pipe_config); 3775 3776 if (pipe_config->cpu_transcoder != TRANSCODER_EDP && 3777 !transcoder_is_dsi(pipe_config->cpu_transcoder)) { 3778 pipe_config->pixel_multiplier = 3779 intel_de_read(dev_priv, 3780 TRANS_MULT(pipe_config->cpu_transcoder)) + 1; 3781 } else { 3782 pipe_config->pixel_multiplier = 1; 3783 } 3784 3785 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { 3786 tmp = intel_de_read(dev_priv, DISPLAY_VER(dev_priv) >= 14 ? 3787 MTL_CHICKEN_TRANS(pipe_config->cpu_transcoder) : 3788 CHICKEN_TRANS(pipe_config->cpu_transcoder)); 3789 3790 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1; 3791 } else { 3792 /* no idea if this is correct */ 3793 pipe_config->framestart_delay = 1; 3794 } 3795 3796 out: 3797 intel_display_power_put_all_in_set(dev_priv, &crtc->hw_readout_power_domains); 3798 3799 return active; 3800 } 3801 3802 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state) 3803 { 3804 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3805 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 3806 3807 if (!i915->display.funcs.display->get_pipe_config(crtc, crtc_state)) 3808 return false; 3809 3810 crtc_state->hw.active = true; 3811 3812 intel_crtc_readout_derived_state(crtc_state); 3813 3814 return true; 3815 } 3816 3817 static int i9xx_pll_refclk(struct drm_device *dev, 3818 const struct intel_crtc_state *pipe_config) 3819 { 3820 struct drm_i915_private *dev_priv = to_i915(dev); 3821 u32 dpll = pipe_config->dpll_hw_state.dpll; 3822 3823 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) 3824 return dev_priv->display.vbt.lvds_ssc_freq; 3825 else if (HAS_PCH_SPLIT(dev_priv)) 3826 return 120000; 3827 else if (DISPLAY_VER(dev_priv) != 2) 3828 return 96000; 3829 else 3830 return 48000; 3831 } 3832 3833 /* Returns the clock of the currently programmed mode of the given pipe. */ 3834 void i9xx_crtc_clock_get(struct intel_crtc *crtc, 3835 struct intel_crtc_state *pipe_config) 3836 { 3837 struct drm_device *dev = crtc->base.dev; 3838 struct drm_i915_private *dev_priv = to_i915(dev); 3839 u32 dpll = pipe_config->dpll_hw_state.dpll; 3840 u32 fp; 3841 struct dpll clock; 3842 int port_clock; 3843 int refclk = i9xx_pll_refclk(dev, pipe_config); 3844 3845 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 3846 fp = pipe_config->dpll_hw_state.fp0; 3847 else 3848 fp = pipe_config->dpll_hw_state.fp1; 3849 3850 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 3851 if (IS_PINEVIEW(dev_priv)) { 3852 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; 3853 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; 3854 } else { 3855 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 3856 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 3857 } 3858 3859 if (DISPLAY_VER(dev_priv) != 2) { 3860 if (IS_PINEVIEW(dev_priv)) 3861 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> 3862 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); 3863 else 3864 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> 3865 DPLL_FPA01_P1_POST_DIV_SHIFT); 3866 3867 switch (dpll & DPLL_MODE_MASK) { 3868 case DPLLB_MODE_DAC_SERIAL: 3869 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 3870 5 : 10; 3871 break; 3872 case DPLLB_MODE_LVDS: 3873 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 3874 7 : 14; 3875 break; 3876 default: 3877 drm_dbg_kms(&dev_priv->drm, 3878 "Unknown DPLL mode %08x in programmed " 3879 "mode\n", (int)(dpll & DPLL_MODE_MASK)); 3880 return; 3881 } 3882 3883 if (IS_PINEVIEW(dev_priv)) 3884 port_clock = pnv_calc_dpll_params(refclk, &clock); 3885 else 3886 port_clock = i9xx_calc_dpll_params(refclk, &clock); 3887 } else { 3888 enum pipe lvds_pipe; 3889 3890 if (IS_I85X(dev_priv) && 3891 intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) && 3892 lvds_pipe == crtc->pipe) { 3893 u32 lvds = intel_de_read(dev_priv, LVDS); 3894 3895 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 3896 DPLL_FPA01_P1_POST_DIV_SHIFT); 3897 3898 if (lvds & LVDS_CLKB_POWER_UP) 3899 clock.p2 = 7; 3900 else 3901 clock.p2 = 14; 3902 } else { 3903 if (dpll & PLL_P1_DIVIDE_BY_TWO) 3904 clock.p1 = 2; 3905 else { 3906 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 3907 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 3908 } 3909 if (dpll & PLL_P2_DIVIDE_BY_4) 3910 clock.p2 = 4; 3911 else 3912 clock.p2 = 2; 3913 } 3914 3915 port_clock = i9xx_calc_dpll_params(refclk, &clock); 3916 } 3917 3918 /* 3919 * This value includes pixel_multiplier. We will use 3920 * port_clock to compute adjusted_mode.crtc_clock in the 3921 * encoder's get_config() function. 3922 */ 3923 pipe_config->port_clock = port_clock; 3924 } 3925 3926 int intel_dotclock_calculate(int link_freq, 3927 const struct intel_link_m_n *m_n) 3928 { 3929 /* 3930 * The calculation for the data clock is: 3931 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp 3932 * But we want to avoid losing precison if possible, so: 3933 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) 3934 * 3935 * and the link clock is simpler: 3936 * link_clock = (m * link_clock) / n 3937 */ 3938 3939 if (!m_n->link_n) 3940 return 0; 3941 3942 return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq), 3943 m_n->link_n); 3944 } 3945 3946 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config) 3947 { 3948 int dotclock; 3949 3950 if (intel_crtc_has_dp_encoder(pipe_config)) 3951 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 3952 &pipe_config->dp_m_n); 3953 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) 3954 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24, 3955 pipe_config->pipe_bpp); 3956 else 3957 dotclock = pipe_config->port_clock; 3958 3959 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 3960 !intel_crtc_has_dp_encoder(pipe_config)) 3961 dotclock *= 2; 3962 3963 if (pipe_config->pixel_multiplier) 3964 dotclock /= pipe_config->pixel_multiplier; 3965 3966 return dotclock; 3967 } 3968 3969 /* Returns the currently programmed mode of the given encoder. */ 3970 struct drm_display_mode * 3971 intel_encoder_current_mode(struct intel_encoder *encoder) 3972 { 3973 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3974 struct intel_crtc_state *crtc_state; 3975 struct drm_display_mode *mode; 3976 struct intel_crtc *crtc; 3977 enum pipe pipe; 3978 3979 if (!encoder->get_hw_state(encoder, &pipe)) 3980 return NULL; 3981 3982 crtc = intel_crtc_for_pipe(dev_priv, pipe); 3983 3984 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 3985 if (!mode) 3986 return NULL; 3987 3988 crtc_state = intel_crtc_state_alloc(crtc); 3989 if (!crtc_state) { 3990 kfree(mode); 3991 return NULL; 3992 } 3993 3994 if (!intel_crtc_get_pipe_config(crtc_state)) { 3995 kfree(crtc_state); 3996 kfree(mode); 3997 return NULL; 3998 } 3999 4000 intel_encoder_get_config(encoder, crtc_state); 4001 4002 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode); 4003 4004 kfree(crtc_state); 4005 4006 return mode; 4007 } 4008 4009 static bool encoders_cloneable(const struct intel_encoder *a, 4010 const struct intel_encoder *b) 4011 { 4012 /* masks could be asymmetric, so check both ways */ 4013 return a == b || (a->cloneable & BIT(b->type) && 4014 b->cloneable & BIT(a->type)); 4015 } 4016 4017 static bool check_single_encoder_cloning(struct intel_atomic_state *state, 4018 struct intel_crtc *crtc, 4019 struct intel_encoder *encoder) 4020 { 4021 struct intel_encoder *source_encoder; 4022 struct drm_connector *connector; 4023 struct drm_connector_state *connector_state; 4024 int i; 4025 4026 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4027 if (connector_state->crtc != &crtc->base) 4028 continue; 4029 4030 source_encoder = 4031 to_intel_encoder(connector_state->best_encoder); 4032 if (!encoders_cloneable(encoder, source_encoder)) 4033 return false; 4034 } 4035 4036 return true; 4037 } 4038 4039 static int icl_add_linked_planes(struct intel_atomic_state *state) 4040 { 4041 struct intel_plane *plane, *linked; 4042 struct intel_plane_state *plane_state, *linked_plane_state; 4043 int i; 4044 4045 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4046 linked = plane_state->planar_linked_plane; 4047 4048 if (!linked) 4049 continue; 4050 4051 linked_plane_state = intel_atomic_get_plane_state(state, linked); 4052 if (IS_ERR(linked_plane_state)) 4053 return PTR_ERR(linked_plane_state); 4054 4055 drm_WARN_ON(state->base.dev, 4056 linked_plane_state->planar_linked_plane != plane); 4057 drm_WARN_ON(state->base.dev, 4058 linked_plane_state->planar_slave == plane_state->planar_slave); 4059 } 4060 4061 return 0; 4062 } 4063 4064 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state) 4065 { 4066 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4067 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4068 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 4069 struct intel_plane *plane, *linked; 4070 struct intel_plane_state *plane_state; 4071 int i; 4072 4073 if (DISPLAY_VER(dev_priv) < 11) 4074 return 0; 4075 4076 /* 4077 * Destroy all old plane links and make the slave plane invisible 4078 * in the crtc_state->active_planes mask. 4079 */ 4080 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4081 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane) 4082 continue; 4083 4084 plane_state->planar_linked_plane = NULL; 4085 if (plane_state->planar_slave && !plane_state->uapi.visible) { 4086 crtc_state->enabled_planes &= ~BIT(plane->id); 4087 crtc_state->active_planes &= ~BIT(plane->id); 4088 crtc_state->update_planes |= BIT(plane->id); 4089 crtc_state->data_rate[plane->id] = 0; 4090 crtc_state->rel_data_rate[plane->id] = 0; 4091 } 4092 4093 plane_state->planar_slave = false; 4094 } 4095 4096 if (!crtc_state->nv12_planes) 4097 return 0; 4098 4099 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4100 struct intel_plane_state *linked_state = NULL; 4101 4102 if (plane->pipe != crtc->pipe || 4103 !(crtc_state->nv12_planes & BIT(plane->id))) 4104 continue; 4105 4106 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) { 4107 if (!icl_is_nv12_y_plane(dev_priv, linked->id)) 4108 continue; 4109 4110 if (crtc_state->active_planes & BIT(linked->id)) 4111 continue; 4112 4113 linked_state = intel_atomic_get_plane_state(state, linked); 4114 if (IS_ERR(linked_state)) 4115 return PTR_ERR(linked_state); 4116 4117 break; 4118 } 4119 4120 if (!linked_state) { 4121 drm_dbg_kms(&dev_priv->drm, 4122 "Need %d free Y planes for planar YUV\n", 4123 hweight8(crtc_state->nv12_planes)); 4124 4125 return -EINVAL; 4126 } 4127 4128 plane_state->planar_linked_plane = linked; 4129 4130 linked_state->planar_slave = true; 4131 linked_state->planar_linked_plane = plane; 4132 crtc_state->enabled_planes |= BIT(linked->id); 4133 crtc_state->active_planes |= BIT(linked->id); 4134 crtc_state->update_planes |= BIT(linked->id); 4135 crtc_state->data_rate[linked->id] = 4136 crtc_state->data_rate_y[plane->id]; 4137 crtc_state->rel_data_rate[linked->id] = 4138 crtc_state->rel_data_rate_y[plane->id]; 4139 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n", 4140 linked->base.name, plane->base.name); 4141 4142 /* Copy parameters to slave plane */ 4143 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE; 4144 linked_state->color_ctl = plane_state->color_ctl; 4145 linked_state->view = plane_state->view; 4146 linked_state->decrypt = plane_state->decrypt; 4147 4148 intel_plane_copy_hw_state(linked_state, plane_state); 4149 linked_state->uapi.src = plane_state->uapi.src; 4150 linked_state->uapi.dst = plane_state->uapi.dst; 4151 4152 if (icl_is_hdr_plane(dev_priv, plane->id)) { 4153 if (linked->id == PLANE_SPRITE5) 4154 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL; 4155 else if (linked->id == PLANE_SPRITE4) 4156 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL; 4157 else if (linked->id == PLANE_SPRITE3) 4158 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL; 4159 else if (linked->id == PLANE_SPRITE2) 4160 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL; 4161 else 4162 MISSING_CASE(linked->id); 4163 } 4164 } 4165 4166 return 0; 4167 } 4168 4169 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state) 4170 { 4171 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 4172 struct intel_atomic_state *state = 4173 to_intel_atomic_state(new_crtc_state->uapi.state); 4174 const struct intel_crtc_state *old_crtc_state = 4175 intel_atomic_get_old_crtc_state(state, crtc); 4176 4177 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes; 4178 } 4179 4180 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) 4181 { 4182 const struct drm_display_mode *pipe_mode = 4183 &crtc_state->hw.pipe_mode; 4184 int linetime_wm; 4185 4186 if (!crtc_state->hw.enable) 4187 return 0; 4188 4189 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4190 pipe_mode->crtc_clock); 4191 4192 return min(linetime_wm, 0x1ff); 4193 } 4194 4195 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, 4196 const struct intel_cdclk_state *cdclk_state) 4197 { 4198 const struct drm_display_mode *pipe_mode = 4199 &crtc_state->hw.pipe_mode; 4200 int linetime_wm; 4201 4202 if (!crtc_state->hw.enable) 4203 return 0; 4204 4205 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4206 cdclk_state->logical.cdclk); 4207 4208 return min(linetime_wm, 0x1ff); 4209 } 4210 4211 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) 4212 { 4213 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4214 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4215 const struct drm_display_mode *pipe_mode = 4216 &crtc_state->hw.pipe_mode; 4217 int linetime_wm; 4218 4219 if (!crtc_state->hw.enable) 4220 return 0; 4221 4222 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8, 4223 crtc_state->pixel_rate); 4224 4225 /* Display WA #1135: BXT:ALL GLK:ALL */ 4226 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 4227 skl_watermark_ipc_enabled(dev_priv)) 4228 linetime_wm /= 2; 4229 4230 return min(linetime_wm, 0x1ff); 4231 } 4232 4233 static int hsw_compute_linetime_wm(struct intel_atomic_state *state, 4234 struct intel_crtc *crtc) 4235 { 4236 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4237 struct intel_crtc_state *crtc_state = 4238 intel_atomic_get_new_crtc_state(state, crtc); 4239 const struct intel_cdclk_state *cdclk_state; 4240 4241 if (DISPLAY_VER(dev_priv) >= 9) 4242 crtc_state->linetime = skl_linetime_wm(crtc_state); 4243 else 4244 crtc_state->linetime = hsw_linetime_wm(crtc_state); 4245 4246 if (!hsw_crtc_supports_ips(crtc)) 4247 return 0; 4248 4249 cdclk_state = intel_atomic_get_cdclk_state(state); 4250 if (IS_ERR(cdclk_state)) 4251 return PTR_ERR(cdclk_state); 4252 4253 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state, 4254 cdclk_state); 4255 4256 return 0; 4257 } 4258 4259 static int intel_crtc_atomic_check(struct intel_atomic_state *state, 4260 struct intel_crtc *crtc) 4261 { 4262 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4263 struct intel_crtc_state *crtc_state = 4264 intel_atomic_get_new_crtc_state(state, crtc); 4265 int ret; 4266 4267 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) && 4268 intel_crtc_needs_modeset(crtc_state) && 4269 !crtc_state->hw.active) 4270 crtc_state->update_wm_post = true; 4271 4272 if (intel_crtc_needs_modeset(crtc_state)) { 4273 ret = intel_dpll_crtc_get_shared_dpll(state, crtc); 4274 if (ret) 4275 return ret; 4276 } 4277 4278 /* 4279 * May need to update pipe gamma enable bits 4280 * when C8 planes are getting enabled/disabled. 4281 */ 4282 if (c8_planes_changed(crtc_state)) 4283 crtc_state->uapi.color_mgmt_changed = true; 4284 4285 if (intel_crtc_needs_color_update(crtc_state)) { 4286 ret = intel_color_check(crtc_state); 4287 if (ret) 4288 return ret; 4289 } 4290 4291 ret = intel_compute_pipe_wm(state, crtc); 4292 if (ret) { 4293 drm_dbg_kms(&dev_priv->drm, 4294 "Target pipe watermarks are invalid\n"); 4295 return ret; 4296 } 4297 4298 /* 4299 * Calculate 'intermediate' watermarks that satisfy both the 4300 * old state and the new state. We can program these 4301 * immediately. 4302 */ 4303 ret = intel_compute_intermediate_wm(state, crtc); 4304 if (ret) { 4305 drm_dbg_kms(&dev_priv->drm, 4306 "No valid intermediate pipe watermarks are possible\n"); 4307 return ret; 4308 } 4309 4310 if (DISPLAY_VER(dev_priv) >= 9) { 4311 if (intel_crtc_needs_modeset(crtc_state) || 4312 intel_crtc_needs_fastset(crtc_state)) { 4313 ret = skl_update_scaler_crtc(crtc_state); 4314 if (ret) 4315 return ret; 4316 } 4317 4318 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state); 4319 if (ret) 4320 return ret; 4321 } 4322 4323 if (HAS_IPS(dev_priv)) { 4324 ret = hsw_ips_compute_config(state, crtc); 4325 if (ret) 4326 return ret; 4327 } 4328 4329 if (DISPLAY_VER(dev_priv) >= 9 || 4330 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 4331 ret = hsw_compute_linetime_wm(state, crtc); 4332 if (ret) 4333 return ret; 4334 4335 } 4336 4337 ret = intel_psr2_sel_fetch_update(state, crtc); 4338 if (ret) 4339 return ret; 4340 4341 return 0; 4342 } 4343 4344 static int 4345 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state, 4346 struct intel_crtc_state *crtc_state) 4347 { 4348 struct drm_connector *connector = conn_state->connector; 4349 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 4350 const struct drm_display_info *info = &connector->display_info; 4351 int bpp; 4352 4353 switch (conn_state->max_bpc) { 4354 case 6 ... 7: 4355 bpp = 6 * 3; 4356 break; 4357 case 8 ... 9: 4358 bpp = 8 * 3; 4359 break; 4360 case 10 ... 11: 4361 bpp = 10 * 3; 4362 break; 4363 case 12 ... 16: 4364 bpp = 12 * 3; 4365 break; 4366 default: 4367 MISSING_CASE(conn_state->max_bpc); 4368 return -EINVAL; 4369 } 4370 4371 if (bpp < crtc_state->pipe_bpp) { 4372 drm_dbg_kms(&i915->drm, 4373 "[CONNECTOR:%d:%s] Limiting display bpp to %d " 4374 "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n", 4375 connector->base.id, connector->name, 4376 bpp, 3 * info->bpc, 4377 3 * conn_state->max_requested_bpc, 4378 crtc_state->pipe_bpp); 4379 4380 crtc_state->pipe_bpp = bpp; 4381 } 4382 4383 return 0; 4384 } 4385 4386 static int 4387 compute_baseline_pipe_bpp(struct intel_atomic_state *state, 4388 struct intel_crtc *crtc) 4389 { 4390 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4391 struct intel_crtc_state *crtc_state = 4392 intel_atomic_get_new_crtc_state(state, crtc); 4393 struct drm_connector *connector; 4394 struct drm_connector_state *connector_state; 4395 int bpp, i; 4396 4397 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 4398 IS_CHERRYVIEW(dev_priv))) 4399 bpp = 10*3; 4400 else if (DISPLAY_VER(dev_priv) >= 5) 4401 bpp = 12*3; 4402 else 4403 bpp = 8*3; 4404 4405 crtc_state->pipe_bpp = bpp; 4406 4407 /* Clamp display bpp to connector max bpp */ 4408 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4409 int ret; 4410 4411 if (connector_state->crtc != &crtc->base) 4412 continue; 4413 4414 ret = compute_sink_pipe_bpp(connector_state, crtc_state); 4415 if (ret) 4416 return ret; 4417 } 4418 4419 return 0; 4420 } 4421 4422 static bool check_digital_port_conflicts(struct intel_atomic_state *state) 4423 { 4424 struct drm_device *dev = state->base.dev; 4425 struct drm_connector *connector; 4426 struct drm_connector_list_iter conn_iter; 4427 unsigned int used_ports = 0; 4428 unsigned int used_mst_ports = 0; 4429 bool ret = true; 4430 4431 /* 4432 * We're going to peek into connector->state, 4433 * hence connection_mutex must be held. 4434 */ 4435 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex); 4436 4437 /* 4438 * Walk the connector list instead of the encoder 4439 * list to detect the problem on ddi platforms 4440 * where there's just one encoder per digital port. 4441 */ 4442 drm_connector_list_iter_begin(dev, &conn_iter); 4443 drm_for_each_connector_iter(connector, &conn_iter) { 4444 struct drm_connector_state *connector_state; 4445 struct intel_encoder *encoder; 4446 4447 connector_state = 4448 drm_atomic_get_new_connector_state(&state->base, 4449 connector); 4450 if (!connector_state) 4451 connector_state = connector->state; 4452 4453 if (!connector_state->best_encoder) 4454 continue; 4455 4456 encoder = to_intel_encoder(connector_state->best_encoder); 4457 4458 drm_WARN_ON(dev, !connector_state->crtc); 4459 4460 switch (encoder->type) { 4461 case INTEL_OUTPUT_DDI: 4462 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev)))) 4463 break; 4464 fallthrough; 4465 case INTEL_OUTPUT_DP: 4466 case INTEL_OUTPUT_HDMI: 4467 case INTEL_OUTPUT_EDP: 4468 /* the same port mustn't appear more than once */ 4469 if (used_ports & BIT(encoder->port)) 4470 ret = false; 4471 4472 used_ports |= BIT(encoder->port); 4473 break; 4474 case INTEL_OUTPUT_DP_MST: 4475 used_mst_ports |= 4476 1 << encoder->port; 4477 break; 4478 default: 4479 break; 4480 } 4481 } 4482 drm_connector_list_iter_end(&conn_iter); 4483 4484 /* can't mix MST and SST/HDMI on the same port */ 4485 if (used_ports & used_mst_ports) 4486 return false; 4487 4488 return ret; 4489 } 4490 4491 static void 4492 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state, 4493 struct intel_crtc *crtc) 4494 { 4495 struct intel_crtc_state *crtc_state = 4496 intel_atomic_get_new_crtc_state(state, crtc); 4497 4498 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 4499 4500 drm_property_replace_blob(&crtc_state->hw.degamma_lut, 4501 crtc_state->uapi.degamma_lut); 4502 drm_property_replace_blob(&crtc_state->hw.gamma_lut, 4503 crtc_state->uapi.gamma_lut); 4504 drm_property_replace_blob(&crtc_state->hw.ctm, 4505 crtc_state->uapi.ctm); 4506 } 4507 4508 static void 4509 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state, 4510 struct intel_crtc *crtc) 4511 { 4512 struct intel_crtc_state *crtc_state = 4513 intel_atomic_get_new_crtc_state(state, crtc); 4514 4515 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 4516 4517 crtc_state->hw.enable = crtc_state->uapi.enable; 4518 crtc_state->hw.active = crtc_state->uapi.active; 4519 drm_mode_copy(&crtc_state->hw.mode, 4520 &crtc_state->uapi.mode); 4521 drm_mode_copy(&crtc_state->hw.adjusted_mode, 4522 &crtc_state->uapi.adjusted_mode); 4523 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter; 4524 4525 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 4526 } 4527 4528 static void 4529 copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state, 4530 struct intel_crtc *slave_crtc) 4531 { 4532 struct intel_crtc_state *slave_crtc_state = 4533 intel_atomic_get_new_crtc_state(state, slave_crtc); 4534 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 4535 const struct intel_crtc_state *master_crtc_state = 4536 intel_atomic_get_new_crtc_state(state, master_crtc); 4537 4538 drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut, 4539 master_crtc_state->hw.degamma_lut); 4540 drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut, 4541 master_crtc_state->hw.gamma_lut); 4542 drm_property_replace_blob(&slave_crtc_state->hw.ctm, 4543 master_crtc_state->hw.ctm); 4544 4545 slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed; 4546 } 4547 4548 static int 4549 copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state, 4550 struct intel_crtc *slave_crtc) 4551 { 4552 struct intel_crtc_state *slave_crtc_state = 4553 intel_atomic_get_new_crtc_state(state, slave_crtc); 4554 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 4555 const struct intel_crtc_state *master_crtc_state = 4556 intel_atomic_get_new_crtc_state(state, master_crtc); 4557 struct intel_crtc_state *saved_state; 4558 4559 WARN_ON(master_crtc_state->bigjoiner_pipes != 4560 slave_crtc_state->bigjoiner_pipes); 4561 4562 saved_state = kmemdup(master_crtc_state, sizeof(*saved_state), GFP_KERNEL); 4563 if (!saved_state) 4564 return -ENOMEM; 4565 4566 /* preserve some things from the slave's original crtc state */ 4567 saved_state->uapi = slave_crtc_state->uapi; 4568 saved_state->scaler_state = slave_crtc_state->scaler_state; 4569 saved_state->shared_dpll = slave_crtc_state->shared_dpll; 4570 saved_state->crc_enabled = slave_crtc_state->crc_enabled; 4571 4572 intel_crtc_free_hw_state(slave_crtc_state); 4573 memcpy(slave_crtc_state, saved_state, sizeof(*slave_crtc_state)); 4574 kfree(saved_state); 4575 4576 /* Re-init hw state */ 4577 memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw)); 4578 slave_crtc_state->hw.enable = master_crtc_state->hw.enable; 4579 slave_crtc_state->hw.active = master_crtc_state->hw.active; 4580 drm_mode_copy(&slave_crtc_state->hw.mode, 4581 &master_crtc_state->hw.mode); 4582 drm_mode_copy(&slave_crtc_state->hw.pipe_mode, 4583 &master_crtc_state->hw.pipe_mode); 4584 drm_mode_copy(&slave_crtc_state->hw.adjusted_mode, 4585 &master_crtc_state->hw.adjusted_mode); 4586 slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter; 4587 4588 copy_bigjoiner_crtc_state_nomodeset(state, slave_crtc); 4589 4590 slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed; 4591 slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed; 4592 slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed; 4593 4594 WARN_ON(master_crtc_state->bigjoiner_pipes != 4595 slave_crtc_state->bigjoiner_pipes); 4596 4597 return 0; 4598 } 4599 4600 static int 4601 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state, 4602 struct intel_crtc *crtc) 4603 { 4604 struct intel_crtc_state *crtc_state = 4605 intel_atomic_get_new_crtc_state(state, crtc); 4606 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4607 struct intel_crtc_state *saved_state; 4608 4609 saved_state = intel_crtc_state_alloc(crtc); 4610 if (!saved_state) 4611 return -ENOMEM; 4612 4613 /* free the old crtc_state->hw members */ 4614 intel_crtc_free_hw_state(crtc_state); 4615 4616 /* FIXME: before the switch to atomic started, a new pipe_config was 4617 * kzalloc'd. Code that depends on any field being zero should be 4618 * fixed, so that the crtc_state can be safely duplicated. For now, 4619 * only fields that are know to not cause problems are preserved. */ 4620 4621 saved_state->uapi = crtc_state->uapi; 4622 saved_state->inherited = crtc_state->inherited; 4623 saved_state->scaler_state = crtc_state->scaler_state; 4624 saved_state->shared_dpll = crtc_state->shared_dpll; 4625 saved_state->dpll_hw_state = crtc_state->dpll_hw_state; 4626 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, 4627 sizeof(saved_state->icl_port_dplls)); 4628 saved_state->crc_enabled = crtc_state->crc_enabled; 4629 if (IS_G4X(dev_priv) || 4630 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 4631 saved_state->wm = crtc_state->wm; 4632 4633 memcpy(crtc_state, saved_state, sizeof(*crtc_state)); 4634 kfree(saved_state); 4635 4636 intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc); 4637 4638 return 0; 4639 } 4640 4641 static int 4642 intel_modeset_pipe_config(struct intel_atomic_state *state, 4643 struct intel_crtc *crtc) 4644 { 4645 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4646 struct intel_crtc_state *crtc_state = 4647 intel_atomic_get_new_crtc_state(state, crtc); 4648 struct drm_connector *connector; 4649 struct drm_connector_state *connector_state; 4650 int pipe_src_w, pipe_src_h; 4651 int base_bpp, ret, i; 4652 bool retry = true; 4653 4654 crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe; 4655 4656 crtc_state->framestart_delay = 1; 4657 4658 /* 4659 * Sanitize sync polarity flags based on requested ones. If neither 4660 * positive or negative polarity is requested, treat this as meaning 4661 * negative polarity. 4662 */ 4663 if (!(crtc_state->hw.adjusted_mode.flags & 4664 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) 4665 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; 4666 4667 if (!(crtc_state->hw.adjusted_mode.flags & 4668 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 4669 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; 4670 4671 ret = compute_baseline_pipe_bpp(state, crtc); 4672 if (ret) 4673 return ret; 4674 4675 base_bpp = crtc_state->pipe_bpp; 4676 4677 /* 4678 * Determine the real pipe dimensions. Note that stereo modes can 4679 * increase the actual pipe size due to the frame doubling and 4680 * insertion of additional space for blanks between the frame. This 4681 * is stored in the crtc timings. We use the requested mode to do this 4682 * computation to clearly distinguish it from the adjusted mode, which 4683 * can be changed by the connectors in the below retry loop. 4684 */ 4685 drm_mode_get_hv_timing(&crtc_state->hw.mode, 4686 &pipe_src_w, &pipe_src_h); 4687 drm_rect_init(&crtc_state->pipe_src, 0, 0, 4688 pipe_src_w, pipe_src_h); 4689 4690 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4691 struct intel_encoder *encoder = 4692 to_intel_encoder(connector_state->best_encoder); 4693 4694 if (connector_state->crtc != &crtc->base) 4695 continue; 4696 4697 if (!check_single_encoder_cloning(state, crtc, encoder)) { 4698 drm_dbg_kms(&i915->drm, 4699 "[ENCODER:%d:%s] rejecting invalid cloning configuration\n", 4700 encoder->base.base.id, encoder->base.name); 4701 return -EINVAL; 4702 } 4703 4704 /* 4705 * Determine output_types before calling the .compute_config() 4706 * hooks so that the hooks can use this information safely. 4707 */ 4708 if (encoder->compute_output_type) 4709 crtc_state->output_types |= 4710 BIT(encoder->compute_output_type(encoder, crtc_state, 4711 connector_state)); 4712 else 4713 crtc_state->output_types |= BIT(encoder->type); 4714 } 4715 4716 encoder_retry: 4717 /* Ensure the port clock defaults are reset when retrying. */ 4718 crtc_state->port_clock = 0; 4719 crtc_state->pixel_multiplier = 1; 4720 4721 /* Fill in default crtc timings, allow encoders to overwrite them. */ 4722 drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode, 4723 CRTC_STEREO_DOUBLE); 4724 4725 /* Pass our mode to the connectors and the CRTC to give them a chance to 4726 * adjust it according to limitations or connector properties, and also 4727 * a chance to reject the mode entirely. 4728 */ 4729 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4730 struct intel_encoder *encoder = 4731 to_intel_encoder(connector_state->best_encoder); 4732 4733 if (connector_state->crtc != &crtc->base) 4734 continue; 4735 4736 ret = encoder->compute_config(encoder, crtc_state, 4737 connector_state); 4738 if (ret == -EDEADLK) 4739 return ret; 4740 if (ret < 0) { 4741 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n", 4742 encoder->base.base.id, encoder->base.name, ret); 4743 return ret; 4744 } 4745 } 4746 4747 /* Set default port clock if not overwritten by the encoder. Needs to be 4748 * done afterwards in case the encoder adjusts the mode. */ 4749 if (!crtc_state->port_clock) 4750 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock 4751 * crtc_state->pixel_multiplier; 4752 4753 ret = intel_crtc_compute_config(state, crtc); 4754 if (ret == -EDEADLK) 4755 return ret; 4756 if (ret == -EAGAIN) { 4757 if (drm_WARN(&i915->drm, !retry, 4758 "[CRTC:%d:%s] loop in pipe configuration computation\n", 4759 crtc->base.base.id, crtc->base.name)) 4760 return -EINVAL; 4761 4762 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] bw constrained, retrying\n", 4763 crtc->base.base.id, crtc->base.name); 4764 retry = false; 4765 goto encoder_retry; 4766 } 4767 if (ret < 0) { 4768 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n", 4769 crtc->base.base.id, crtc->base.name, ret); 4770 return ret; 4771 } 4772 4773 /* Dithering seems to not pass-through bits correctly when it should, so 4774 * only enable it on 6bpc panels and when its not a compliance 4775 * test requesting 6bpc video pattern. 4776 */ 4777 crtc_state->dither = (crtc_state->pipe_bpp == 6*3) && 4778 !crtc_state->dither_force_disable; 4779 drm_dbg_kms(&i915->drm, 4780 "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n", 4781 crtc->base.base.id, crtc->base.name, 4782 base_bpp, crtc_state->pipe_bpp, crtc_state->dither); 4783 4784 return 0; 4785 } 4786 4787 static int 4788 intel_modeset_pipe_config_late(struct intel_atomic_state *state, 4789 struct intel_crtc *crtc) 4790 { 4791 struct intel_crtc_state *crtc_state = 4792 intel_atomic_get_new_crtc_state(state, crtc); 4793 struct drm_connector_state *conn_state; 4794 struct drm_connector *connector; 4795 int i; 4796 4797 intel_bigjoiner_adjust_pipe_src(crtc_state); 4798 4799 for_each_new_connector_in_state(&state->base, connector, 4800 conn_state, i) { 4801 struct intel_encoder *encoder = 4802 to_intel_encoder(conn_state->best_encoder); 4803 int ret; 4804 4805 if (conn_state->crtc != &crtc->base || 4806 !encoder->compute_config_late) 4807 continue; 4808 4809 ret = encoder->compute_config_late(encoder, crtc_state, 4810 conn_state); 4811 if (ret) 4812 return ret; 4813 } 4814 4815 return 0; 4816 } 4817 4818 bool intel_fuzzy_clock_check(int clock1, int clock2) 4819 { 4820 int diff; 4821 4822 if (clock1 == clock2) 4823 return true; 4824 4825 if (!clock1 || !clock2) 4826 return false; 4827 4828 diff = abs(clock1 - clock2); 4829 4830 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) 4831 return true; 4832 4833 return false; 4834 } 4835 4836 static bool 4837 intel_compare_link_m_n(const struct intel_link_m_n *m_n, 4838 const struct intel_link_m_n *m2_n2) 4839 { 4840 return m_n->tu == m2_n2->tu && 4841 m_n->data_m == m2_n2->data_m && 4842 m_n->data_n == m2_n2->data_n && 4843 m_n->link_m == m2_n2->link_m && 4844 m_n->link_n == m2_n2->link_n; 4845 } 4846 4847 static bool 4848 intel_compare_infoframe(const union hdmi_infoframe *a, 4849 const union hdmi_infoframe *b) 4850 { 4851 return memcmp(a, b, sizeof(*a)) == 0; 4852 } 4853 4854 static bool 4855 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a, 4856 const struct drm_dp_vsc_sdp *b) 4857 { 4858 return memcmp(a, b, sizeof(*a)) == 0; 4859 } 4860 4861 static bool 4862 intel_compare_buffer(const u8 *a, const u8 *b, size_t len) 4863 { 4864 return memcmp(a, b, len) == 0; 4865 } 4866 4867 static void 4868 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv, 4869 bool fastset, const char *name, 4870 const union hdmi_infoframe *a, 4871 const union hdmi_infoframe *b) 4872 { 4873 if (fastset) { 4874 if (!drm_debug_enabled(DRM_UT_KMS)) 4875 return; 4876 4877 drm_dbg_kms(&dev_priv->drm, 4878 "fastset requirement not met in %s infoframe\n", name); 4879 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 4880 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a); 4881 drm_dbg_kms(&dev_priv->drm, "found:\n"); 4882 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b); 4883 } else { 4884 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name); 4885 drm_err(&dev_priv->drm, "expected:\n"); 4886 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a); 4887 drm_err(&dev_priv->drm, "found:\n"); 4888 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b); 4889 } 4890 } 4891 4892 static void 4893 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv, 4894 bool fastset, const char *name, 4895 const struct drm_dp_vsc_sdp *a, 4896 const struct drm_dp_vsc_sdp *b) 4897 { 4898 if (fastset) { 4899 if (!drm_debug_enabled(DRM_UT_KMS)) 4900 return; 4901 4902 drm_dbg_kms(&dev_priv->drm, 4903 "fastset requirement not met in %s dp sdp\n", name); 4904 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 4905 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a); 4906 drm_dbg_kms(&dev_priv->drm, "found:\n"); 4907 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b); 4908 } else { 4909 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name); 4910 drm_err(&dev_priv->drm, "expected:\n"); 4911 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a); 4912 drm_err(&dev_priv->drm, "found:\n"); 4913 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b); 4914 } 4915 } 4916 4917 /* Returns the length up to and including the last differing byte */ 4918 static size_t 4919 memcmp_diff_len(const u8 *a, const u8 *b, size_t len) 4920 { 4921 int i; 4922 4923 for (i = len - 1; i >= 0; i--) { 4924 if (a[i] != b[i]) 4925 return i + 1; 4926 } 4927 4928 return 0; 4929 } 4930 4931 static void 4932 pipe_config_buffer_mismatch(struct drm_i915_private *dev_priv, 4933 bool fastset, const char *name, 4934 const u8 *a, const u8 *b, size_t len) 4935 { 4936 if (fastset) { 4937 if (!drm_debug_enabled(DRM_UT_KMS)) 4938 return; 4939 4940 /* only dump up to the last difference */ 4941 len = memcmp_diff_len(a, b, len); 4942 4943 drm_dbg_kms(&dev_priv->drm, 4944 "fastset requirement not met in %s buffer\n", name); 4945 print_hex_dump(KERN_DEBUG, "expected: ", DUMP_PREFIX_NONE, 4946 16, 0, a, len, false); 4947 print_hex_dump(KERN_DEBUG, "found: ", DUMP_PREFIX_NONE, 4948 16, 0, b, len, false); 4949 } else { 4950 /* only dump up to the last difference */ 4951 len = memcmp_diff_len(a, b, len); 4952 4953 drm_err(&dev_priv->drm, "mismatch in %s buffer\n", name); 4954 print_hex_dump(KERN_ERR, "expected: ", DUMP_PREFIX_NONE, 4955 16, 0, a, len, false); 4956 print_hex_dump(KERN_ERR, "found: ", DUMP_PREFIX_NONE, 4957 16, 0, b, len, false); 4958 } 4959 } 4960 4961 static void __printf(4, 5) 4962 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc, 4963 const char *name, const char *format, ...) 4964 { 4965 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4966 struct va_format vaf; 4967 va_list args; 4968 4969 va_start(args, format); 4970 vaf.fmt = format; 4971 vaf.va = &args; 4972 4973 if (fastset) 4974 drm_dbg_kms(&i915->drm, 4975 "[CRTC:%d:%s] fastset requirement not met in %s %pV\n", 4976 crtc->base.base.id, crtc->base.name, name, &vaf); 4977 else 4978 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n", 4979 crtc->base.base.id, crtc->base.name, name, &vaf); 4980 4981 va_end(args); 4982 } 4983 4984 static bool fastboot_enabled(struct drm_i915_private *dev_priv) 4985 { 4986 if (dev_priv->params.fastboot != -1) 4987 return dev_priv->params.fastboot; 4988 4989 /* Enable fastboot by default on Skylake and newer */ 4990 if (DISPLAY_VER(dev_priv) >= 9) 4991 return true; 4992 4993 /* Enable fastboot by default on VLV and CHV */ 4994 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 4995 return true; 4996 4997 /* Disabled by default on all others */ 4998 return false; 4999 } 5000 5001 bool 5002 intel_pipe_config_compare(const struct intel_crtc_state *current_config, 5003 const struct intel_crtc_state *pipe_config, 5004 bool fastset) 5005 { 5006 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev); 5007 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 5008 bool ret = true; 5009 bool fixup_inherited = fastset && 5010 current_config->inherited && !pipe_config->inherited; 5011 5012 if (fixup_inherited && !fastboot_enabled(dev_priv)) { 5013 drm_dbg_kms(&dev_priv->drm, 5014 "initial modeset and fastboot not set\n"); 5015 ret = false; 5016 } 5017 5018 #define PIPE_CONF_CHECK_X(name) do { \ 5019 if (current_config->name != pipe_config->name) { \ 5020 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5021 "(expected 0x%08x, found 0x%08x)", \ 5022 current_config->name, \ 5023 pipe_config->name); \ 5024 ret = false; \ 5025 } \ 5026 } while (0) 5027 5028 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \ 5029 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \ 5030 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5031 "(expected 0x%08x, found 0x%08x)", \ 5032 current_config->name & (mask), \ 5033 pipe_config->name & (mask)); \ 5034 ret = false; \ 5035 } \ 5036 } while (0) 5037 5038 #define PIPE_CONF_CHECK_I(name) do { \ 5039 if (current_config->name != pipe_config->name) { \ 5040 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5041 "(expected %i, found %i)", \ 5042 current_config->name, \ 5043 pipe_config->name); \ 5044 ret = false; \ 5045 } \ 5046 } while (0) 5047 5048 #define PIPE_CONF_CHECK_BOOL(name) do { \ 5049 if (current_config->name != pipe_config->name) { \ 5050 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5051 "(expected %s, found %s)", \ 5052 str_yes_no(current_config->name), \ 5053 str_yes_no(pipe_config->name)); \ 5054 ret = false; \ 5055 } \ 5056 } while (0) 5057 5058 /* 5059 * Checks state where we only read out the enabling, but not the entire 5060 * state itself (like full infoframes or ELD for audio). These states 5061 * require a full modeset on bootup to fix up. 5062 */ 5063 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \ 5064 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \ 5065 PIPE_CONF_CHECK_BOOL(name); \ 5066 } else { \ 5067 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5068 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \ 5069 str_yes_no(current_config->name), \ 5070 str_yes_no(pipe_config->name)); \ 5071 ret = false; \ 5072 } \ 5073 } while (0) 5074 5075 #define PIPE_CONF_CHECK_P(name) do { \ 5076 if (current_config->name != pipe_config->name) { \ 5077 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5078 "(expected %p, found %p)", \ 5079 current_config->name, \ 5080 pipe_config->name); \ 5081 ret = false; \ 5082 } \ 5083 } while (0) 5084 5085 #define PIPE_CONF_CHECK_M_N(name) do { \ 5086 if (!intel_compare_link_m_n(¤t_config->name, \ 5087 &pipe_config->name)) { \ 5088 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5089 "(expected tu %i data %i/%i link %i/%i, " \ 5090 "found tu %i, data %i/%i link %i/%i)", \ 5091 current_config->name.tu, \ 5092 current_config->name.data_m, \ 5093 current_config->name.data_n, \ 5094 current_config->name.link_m, \ 5095 current_config->name.link_n, \ 5096 pipe_config->name.tu, \ 5097 pipe_config->name.data_m, \ 5098 pipe_config->name.data_n, \ 5099 pipe_config->name.link_m, \ 5100 pipe_config->name.link_n); \ 5101 ret = false; \ 5102 } \ 5103 } while (0) 5104 5105 #define PIPE_CONF_CHECK_TIMINGS(name) do { \ 5106 PIPE_CONF_CHECK_I(name.crtc_hdisplay); \ 5107 PIPE_CONF_CHECK_I(name.crtc_htotal); \ 5108 PIPE_CONF_CHECK_I(name.crtc_hblank_start); \ 5109 PIPE_CONF_CHECK_I(name.crtc_hblank_end); \ 5110 PIPE_CONF_CHECK_I(name.crtc_hsync_start); \ 5111 PIPE_CONF_CHECK_I(name.crtc_hsync_end); \ 5112 PIPE_CONF_CHECK_I(name.crtc_vdisplay); \ 5113 PIPE_CONF_CHECK_I(name.crtc_vtotal); \ 5114 PIPE_CONF_CHECK_I(name.crtc_vblank_start); \ 5115 PIPE_CONF_CHECK_I(name.crtc_vblank_end); \ 5116 PIPE_CONF_CHECK_I(name.crtc_vsync_start); \ 5117 PIPE_CONF_CHECK_I(name.crtc_vsync_end); \ 5118 } while (0) 5119 5120 #define PIPE_CONF_CHECK_RECT(name) do { \ 5121 PIPE_CONF_CHECK_I(name.x1); \ 5122 PIPE_CONF_CHECK_I(name.x2); \ 5123 PIPE_CONF_CHECK_I(name.y1); \ 5124 PIPE_CONF_CHECK_I(name.y2); \ 5125 } while (0) 5126 5127 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \ 5128 if ((current_config->name ^ pipe_config->name) & (mask)) { \ 5129 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5130 "(%x) (expected %i, found %i)", \ 5131 (mask), \ 5132 current_config->name & (mask), \ 5133 pipe_config->name & (mask)); \ 5134 ret = false; \ 5135 } \ 5136 } while (0) 5137 5138 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \ 5139 if (!intel_compare_infoframe(¤t_config->infoframes.name, \ 5140 &pipe_config->infoframes.name)) { \ 5141 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \ 5142 ¤t_config->infoframes.name, \ 5143 &pipe_config->infoframes.name); \ 5144 ret = false; \ 5145 } \ 5146 } while (0) 5147 5148 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \ 5149 if (!current_config->has_psr && !pipe_config->has_psr && \ 5150 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \ 5151 &pipe_config->infoframes.name)) { \ 5152 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \ 5153 ¤t_config->infoframes.name, \ 5154 &pipe_config->infoframes.name); \ 5155 ret = false; \ 5156 } \ 5157 } while (0) 5158 5159 #define PIPE_CONF_CHECK_BUFFER(name, len) do { \ 5160 BUILD_BUG_ON(sizeof(current_config->name) != (len)); \ 5161 BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \ 5162 if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \ 5163 pipe_config_buffer_mismatch(dev_priv, fastset, __stringify(name), \ 5164 current_config->name, \ 5165 pipe_config->name, \ 5166 (len)); \ 5167 ret = false; \ 5168 } \ 5169 } while (0) 5170 5171 #define PIPE_CONF_CHECK_COLOR_LUT(lut, is_pre_csc_lut) do { \ 5172 if (current_config->gamma_mode == pipe_config->gamma_mode && \ 5173 !intel_color_lut_equal(current_config, \ 5174 current_config->lut, pipe_config->lut, \ 5175 is_pre_csc_lut)) { \ 5176 pipe_config_mismatch(fastset, crtc, __stringify(lut), \ 5177 "hw_state doesn't match sw_state"); \ 5178 ret = false; \ 5179 } \ 5180 } while (0) 5181 5182 #define PIPE_CONF_CHECK_CSC(name) do { \ 5183 PIPE_CONF_CHECK_X(name.preoff[0]); \ 5184 PIPE_CONF_CHECK_X(name.preoff[1]); \ 5185 PIPE_CONF_CHECK_X(name.preoff[2]); \ 5186 PIPE_CONF_CHECK_X(name.coeff[0]); \ 5187 PIPE_CONF_CHECK_X(name.coeff[1]); \ 5188 PIPE_CONF_CHECK_X(name.coeff[2]); \ 5189 PIPE_CONF_CHECK_X(name.coeff[3]); \ 5190 PIPE_CONF_CHECK_X(name.coeff[4]); \ 5191 PIPE_CONF_CHECK_X(name.coeff[5]); \ 5192 PIPE_CONF_CHECK_X(name.coeff[6]); \ 5193 PIPE_CONF_CHECK_X(name.coeff[7]); \ 5194 PIPE_CONF_CHECK_X(name.coeff[8]); \ 5195 PIPE_CONF_CHECK_X(name.postoff[0]); \ 5196 PIPE_CONF_CHECK_X(name.postoff[1]); \ 5197 PIPE_CONF_CHECK_X(name.postoff[2]); \ 5198 } while (0) 5199 5200 #define PIPE_CONF_QUIRK(quirk) \ 5201 ((current_config->quirks | pipe_config->quirks) & (quirk)) 5202 5203 PIPE_CONF_CHECK_I(hw.enable); 5204 PIPE_CONF_CHECK_I(hw.active); 5205 5206 PIPE_CONF_CHECK_I(cpu_transcoder); 5207 PIPE_CONF_CHECK_I(mst_master_transcoder); 5208 5209 PIPE_CONF_CHECK_BOOL(has_pch_encoder); 5210 PIPE_CONF_CHECK_I(fdi_lanes); 5211 PIPE_CONF_CHECK_M_N(fdi_m_n); 5212 5213 PIPE_CONF_CHECK_I(lane_count); 5214 PIPE_CONF_CHECK_X(lane_lat_optim_mask); 5215 5216 if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) { 5217 if (!fastset || !pipe_config->seamless_m_n) 5218 PIPE_CONF_CHECK_M_N(dp_m_n); 5219 } else { 5220 PIPE_CONF_CHECK_M_N(dp_m_n); 5221 PIPE_CONF_CHECK_M_N(dp_m2_n2); 5222 } 5223 5224 PIPE_CONF_CHECK_X(output_types); 5225 5226 PIPE_CONF_CHECK_I(framestart_delay); 5227 PIPE_CONF_CHECK_I(msa_timing_delay); 5228 5229 PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode); 5230 PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode); 5231 5232 PIPE_CONF_CHECK_I(pixel_multiplier); 5233 5234 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5235 DRM_MODE_FLAG_INTERLACE); 5236 5237 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { 5238 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5239 DRM_MODE_FLAG_PHSYNC); 5240 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5241 DRM_MODE_FLAG_NHSYNC); 5242 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5243 DRM_MODE_FLAG_PVSYNC); 5244 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5245 DRM_MODE_FLAG_NVSYNC); 5246 } 5247 5248 PIPE_CONF_CHECK_I(output_format); 5249 PIPE_CONF_CHECK_BOOL(has_hdmi_sink); 5250 if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || 5251 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5252 PIPE_CONF_CHECK_BOOL(limited_color_range); 5253 5254 PIPE_CONF_CHECK_BOOL(hdmi_scrambling); 5255 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio); 5256 PIPE_CONF_CHECK_BOOL(has_infoframe); 5257 PIPE_CONF_CHECK_BOOL(fec_enable); 5258 5259 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio); 5260 PIPE_CONF_CHECK_BUFFER(eld, MAX_ELD_BYTES); 5261 5262 PIPE_CONF_CHECK_X(gmch_pfit.control); 5263 /* pfit ratios are autocomputed by the hw on gen4+ */ 5264 if (DISPLAY_VER(dev_priv) < 4) 5265 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); 5266 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); 5267 5268 /* 5269 * Changing the EDP transcoder input mux 5270 * (A_ONOFF vs. A_ON) requires a full modeset. 5271 */ 5272 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru); 5273 5274 if (!fastset) { 5275 PIPE_CONF_CHECK_RECT(pipe_src); 5276 5277 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled); 5278 PIPE_CONF_CHECK_RECT(pch_pfit.dst); 5279 5280 PIPE_CONF_CHECK_I(scaler_state.scaler_id); 5281 PIPE_CONF_CHECK_I(pixel_rate); 5282 5283 PIPE_CONF_CHECK_X(gamma_mode); 5284 if (IS_CHERRYVIEW(dev_priv)) 5285 PIPE_CONF_CHECK_X(cgm_mode); 5286 else 5287 PIPE_CONF_CHECK_X(csc_mode); 5288 PIPE_CONF_CHECK_BOOL(gamma_enable); 5289 PIPE_CONF_CHECK_BOOL(csc_enable); 5290 PIPE_CONF_CHECK_BOOL(wgc_enable); 5291 5292 PIPE_CONF_CHECK_I(linetime); 5293 PIPE_CONF_CHECK_I(ips_linetime); 5294 5295 PIPE_CONF_CHECK_COLOR_LUT(pre_csc_lut, true); 5296 PIPE_CONF_CHECK_COLOR_LUT(post_csc_lut, false); 5297 5298 PIPE_CONF_CHECK_CSC(csc); 5299 PIPE_CONF_CHECK_CSC(output_csc); 5300 5301 if (current_config->active_planes) { 5302 PIPE_CONF_CHECK_BOOL(has_psr); 5303 PIPE_CONF_CHECK_BOOL(has_psr2); 5304 PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); 5305 PIPE_CONF_CHECK_I(dc3co_exitline); 5306 } 5307 } 5308 5309 PIPE_CONF_CHECK_BOOL(double_wide); 5310 5311 if (dev_priv->display.dpll.mgr) { 5312 PIPE_CONF_CHECK_P(shared_dpll); 5313 5314 PIPE_CONF_CHECK_X(dpll_hw_state.dpll); 5315 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); 5316 PIPE_CONF_CHECK_X(dpll_hw_state.fp0); 5317 PIPE_CONF_CHECK_X(dpll_hw_state.fp1); 5318 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); 5319 PIPE_CONF_CHECK_X(dpll_hw_state.spll); 5320 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); 5321 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); 5322 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); 5323 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); 5324 PIPE_CONF_CHECK_X(dpll_hw_state.div0); 5325 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); 5326 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); 5327 PIPE_CONF_CHECK_X(dpll_hw_state.pll0); 5328 PIPE_CONF_CHECK_X(dpll_hw_state.pll1); 5329 PIPE_CONF_CHECK_X(dpll_hw_state.pll2); 5330 PIPE_CONF_CHECK_X(dpll_hw_state.pll3); 5331 PIPE_CONF_CHECK_X(dpll_hw_state.pll6); 5332 PIPE_CONF_CHECK_X(dpll_hw_state.pll8); 5333 PIPE_CONF_CHECK_X(dpll_hw_state.pll9); 5334 PIPE_CONF_CHECK_X(dpll_hw_state.pll10); 5335 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); 5336 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl); 5337 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1); 5338 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl); 5339 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0); 5340 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1); 5341 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf); 5342 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock); 5343 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc); 5344 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias); 5345 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias); 5346 } 5347 5348 PIPE_CONF_CHECK_X(dsi_pll.ctrl); 5349 PIPE_CONF_CHECK_X(dsi_pll.div); 5350 5351 if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5) 5352 PIPE_CONF_CHECK_I(pipe_bpp); 5353 5354 if (!fastset || !pipe_config->seamless_m_n) { 5355 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock); 5356 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock); 5357 } 5358 PIPE_CONF_CHECK_I(port_clock); 5359 5360 PIPE_CONF_CHECK_I(min_voltage_level); 5361 5362 if (current_config->has_psr || pipe_config->has_psr) 5363 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable, 5364 ~intel_hdmi_infoframe_enable(DP_SDP_VSC)); 5365 else 5366 PIPE_CONF_CHECK_X(infoframes.enable); 5367 5368 PIPE_CONF_CHECK_X(infoframes.gcp); 5369 PIPE_CONF_CHECK_INFOFRAME(avi); 5370 PIPE_CONF_CHECK_INFOFRAME(spd); 5371 PIPE_CONF_CHECK_INFOFRAME(hdmi); 5372 PIPE_CONF_CHECK_INFOFRAME(drm); 5373 PIPE_CONF_CHECK_DP_VSC_SDP(vsc); 5374 5375 PIPE_CONF_CHECK_X(sync_mode_slaves_mask); 5376 PIPE_CONF_CHECK_I(master_transcoder); 5377 PIPE_CONF_CHECK_X(bigjoiner_pipes); 5378 5379 PIPE_CONF_CHECK_I(dsc.compression_enable); 5380 PIPE_CONF_CHECK_I(dsc.dsc_split); 5381 PIPE_CONF_CHECK_I(dsc.compressed_bpp); 5382 5383 PIPE_CONF_CHECK_BOOL(splitter.enable); 5384 PIPE_CONF_CHECK_I(splitter.link_count); 5385 PIPE_CONF_CHECK_I(splitter.pixel_overlap); 5386 5387 if (!fastset) 5388 PIPE_CONF_CHECK_BOOL(vrr.enable); 5389 PIPE_CONF_CHECK_I(vrr.vmin); 5390 PIPE_CONF_CHECK_I(vrr.vmax); 5391 PIPE_CONF_CHECK_I(vrr.flipline); 5392 PIPE_CONF_CHECK_I(vrr.pipeline_full); 5393 PIPE_CONF_CHECK_I(vrr.guardband); 5394 5395 #undef PIPE_CONF_CHECK_X 5396 #undef PIPE_CONF_CHECK_I 5397 #undef PIPE_CONF_CHECK_BOOL 5398 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE 5399 #undef PIPE_CONF_CHECK_P 5400 #undef PIPE_CONF_CHECK_FLAGS 5401 #undef PIPE_CONF_CHECK_COLOR_LUT 5402 #undef PIPE_CONF_CHECK_TIMINGS 5403 #undef PIPE_CONF_CHECK_RECT 5404 #undef PIPE_CONF_QUIRK 5405 5406 return ret; 5407 } 5408 5409 static void 5410 intel_verify_planes(struct intel_atomic_state *state) 5411 { 5412 struct intel_plane *plane; 5413 const struct intel_plane_state *plane_state; 5414 int i; 5415 5416 for_each_new_intel_plane_in_state(state, plane, 5417 plane_state, i) 5418 assert_plane(plane, plane_state->planar_slave || 5419 plane_state->uapi.visible); 5420 } 5421 5422 int intel_modeset_all_pipes(struct intel_atomic_state *state, 5423 const char *reason) 5424 { 5425 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 5426 struct intel_crtc *crtc; 5427 5428 /* 5429 * Add all pipes to the state, and force 5430 * a modeset on all the active ones. 5431 */ 5432 for_each_intel_crtc(&dev_priv->drm, crtc) { 5433 struct intel_crtc_state *crtc_state; 5434 int ret; 5435 5436 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 5437 if (IS_ERR(crtc_state)) 5438 return PTR_ERR(crtc_state); 5439 5440 if (!crtc_state->hw.active || 5441 intel_crtc_needs_modeset(crtc_state)) 5442 continue; 5443 5444 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] Full modeset due to %s\n", 5445 crtc->base.base.id, crtc->base.name, reason); 5446 5447 crtc_state->uapi.mode_changed = true; 5448 crtc_state->update_pipe = false; 5449 5450 ret = drm_atomic_add_affected_connectors(&state->base, 5451 &crtc->base); 5452 if (ret) 5453 return ret; 5454 5455 ret = intel_dp_mst_add_topology_state_for_crtc(state, crtc); 5456 if (ret) 5457 return ret; 5458 5459 ret = intel_atomic_add_affected_planes(state, crtc); 5460 if (ret) 5461 return ret; 5462 5463 crtc_state->update_planes |= crtc_state->active_planes; 5464 crtc_state->async_flip_planes = 0; 5465 crtc_state->do_async_flip = false; 5466 } 5467 5468 return 0; 5469 } 5470 5471 /* 5472 * This implements the workaround described in the "notes" section of the mode 5473 * set sequence documentation. When going from no pipes or single pipe to 5474 * multiple pipes, and planes are enabled after the pipe, we need to wait at 5475 * least 2 vblanks on the first pipe before enabling planes on the second pipe. 5476 */ 5477 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state) 5478 { 5479 struct intel_crtc_state *crtc_state; 5480 struct intel_crtc *crtc; 5481 struct intel_crtc_state *first_crtc_state = NULL; 5482 struct intel_crtc_state *other_crtc_state = NULL; 5483 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; 5484 int i; 5485 5486 /* look at all crtc's that are going to be enabled in during modeset */ 5487 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5488 if (!crtc_state->hw.active || 5489 !intel_crtc_needs_modeset(crtc_state)) 5490 continue; 5491 5492 if (first_crtc_state) { 5493 other_crtc_state = crtc_state; 5494 break; 5495 } else { 5496 first_crtc_state = crtc_state; 5497 first_pipe = crtc->pipe; 5498 } 5499 } 5500 5501 /* No workaround needed? */ 5502 if (!first_crtc_state) 5503 return 0; 5504 5505 /* w/a possibly needed, check how many crtc's are already enabled. */ 5506 for_each_intel_crtc(state->base.dev, crtc) { 5507 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 5508 if (IS_ERR(crtc_state)) 5509 return PTR_ERR(crtc_state); 5510 5511 crtc_state->hsw_workaround_pipe = INVALID_PIPE; 5512 5513 if (!crtc_state->hw.active || 5514 intel_crtc_needs_modeset(crtc_state)) 5515 continue; 5516 5517 /* 2 or more enabled crtcs means no need for w/a */ 5518 if (enabled_pipe != INVALID_PIPE) 5519 return 0; 5520 5521 enabled_pipe = crtc->pipe; 5522 } 5523 5524 if (enabled_pipe != INVALID_PIPE) 5525 first_crtc_state->hsw_workaround_pipe = enabled_pipe; 5526 else if (other_crtc_state) 5527 other_crtc_state->hsw_workaround_pipe = first_pipe; 5528 5529 return 0; 5530 } 5531 5532 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 5533 u8 active_pipes) 5534 { 5535 const struct intel_crtc_state *crtc_state; 5536 struct intel_crtc *crtc; 5537 int i; 5538 5539 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5540 if (crtc_state->hw.active) 5541 active_pipes |= BIT(crtc->pipe); 5542 else 5543 active_pipes &= ~BIT(crtc->pipe); 5544 } 5545 5546 return active_pipes; 5547 } 5548 5549 static int intel_modeset_checks(struct intel_atomic_state *state) 5550 { 5551 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 5552 5553 state->modeset = true; 5554 5555 if (IS_HASWELL(dev_priv)) 5556 return hsw_mode_set_planes_workaround(state); 5557 5558 return 0; 5559 } 5560 5561 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state, 5562 struct intel_crtc_state *new_crtc_state) 5563 { 5564 struct drm_i915_private *i915 = to_i915(old_crtc_state->uapi.crtc->dev); 5565 5566 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) { 5567 drm_dbg_kms(&i915->drm, "fastset requirement not met, forcing full modeset\n"); 5568 5569 return; 5570 } 5571 5572 new_crtc_state->uapi.mode_changed = false; 5573 if (!intel_crtc_needs_modeset(new_crtc_state)) 5574 new_crtc_state->update_pipe = true; 5575 } 5576 5577 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state, 5578 struct intel_crtc *crtc, 5579 u8 plane_ids_mask) 5580 { 5581 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 5582 struct intel_plane *plane; 5583 5584 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 5585 struct intel_plane_state *plane_state; 5586 5587 if ((plane_ids_mask & BIT(plane->id)) == 0) 5588 continue; 5589 5590 plane_state = intel_atomic_get_plane_state(state, plane); 5591 if (IS_ERR(plane_state)) 5592 return PTR_ERR(plane_state); 5593 } 5594 5595 return 0; 5596 } 5597 5598 int intel_atomic_add_affected_planes(struct intel_atomic_state *state, 5599 struct intel_crtc *crtc) 5600 { 5601 const struct intel_crtc_state *old_crtc_state = 5602 intel_atomic_get_old_crtc_state(state, crtc); 5603 const struct intel_crtc_state *new_crtc_state = 5604 intel_atomic_get_new_crtc_state(state, crtc); 5605 5606 return intel_crtc_add_planes_to_state(state, crtc, 5607 old_crtc_state->enabled_planes | 5608 new_crtc_state->enabled_planes); 5609 } 5610 5611 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv) 5612 { 5613 /* See {hsw,vlv,ivb}_plane_ratio() */ 5614 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) || 5615 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) || 5616 IS_IVYBRIDGE(dev_priv); 5617 } 5618 5619 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state, 5620 struct intel_crtc *crtc, 5621 struct intel_crtc *other) 5622 { 5623 const struct intel_plane_state __maybe_unused *plane_state; 5624 struct intel_plane *plane; 5625 u8 plane_ids = 0; 5626 int i; 5627 5628 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 5629 if (plane->pipe == crtc->pipe) 5630 plane_ids |= BIT(plane->id); 5631 } 5632 5633 return intel_crtc_add_planes_to_state(state, other, plane_ids); 5634 } 5635 5636 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state) 5637 { 5638 struct drm_i915_private *i915 = to_i915(state->base.dev); 5639 const struct intel_crtc_state *crtc_state; 5640 struct intel_crtc *crtc; 5641 int i; 5642 5643 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5644 struct intel_crtc *other; 5645 5646 for_each_intel_crtc_in_pipe_mask(&i915->drm, other, 5647 crtc_state->bigjoiner_pipes) { 5648 int ret; 5649 5650 if (crtc == other) 5651 continue; 5652 5653 ret = intel_crtc_add_bigjoiner_planes(state, crtc, other); 5654 if (ret) 5655 return ret; 5656 } 5657 } 5658 5659 return 0; 5660 } 5661 5662 static int intel_atomic_check_planes(struct intel_atomic_state *state) 5663 { 5664 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 5665 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 5666 struct intel_plane_state __maybe_unused *plane_state; 5667 struct intel_plane *plane; 5668 struct intel_crtc *crtc; 5669 int i, ret; 5670 5671 ret = icl_add_linked_planes(state); 5672 if (ret) 5673 return ret; 5674 5675 ret = intel_bigjoiner_add_affected_planes(state); 5676 if (ret) 5677 return ret; 5678 5679 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 5680 ret = intel_plane_atomic_check(state, plane); 5681 if (ret) { 5682 drm_dbg_atomic(&dev_priv->drm, 5683 "[PLANE:%d:%s] atomic driver check failed\n", 5684 plane->base.base.id, plane->base.name); 5685 return ret; 5686 } 5687 } 5688 5689 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 5690 new_crtc_state, i) { 5691 u8 old_active_planes, new_active_planes; 5692 5693 ret = icl_check_nv12_planes(new_crtc_state); 5694 if (ret) 5695 return ret; 5696 5697 /* 5698 * On some platforms the number of active planes affects 5699 * the planes' minimum cdclk calculation. Add such planes 5700 * to the state before we compute the minimum cdclk. 5701 */ 5702 if (!active_planes_affects_min_cdclk(dev_priv)) 5703 continue; 5704 5705 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 5706 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 5707 5708 if (hweight8(old_active_planes) == hweight8(new_active_planes)) 5709 continue; 5710 5711 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes); 5712 if (ret) 5713 return ret; 5714 } 5715 5716 return 0; 5717 } 5718 5719 static int intel_atomic_check_crtcs(struct intel_atomic_state *state) 5720 { 5721 struct intel_crtc_state __maybe_unused *crtc_state; 5722 struct intel_crtc *crtc; 5723 int i; 5724 5725 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5726 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 5727 int ret; 5728 5729 ret = intel_crtc_atomic_check(state, crtc); 5730 if (ret) { 5731 drm_dbg_atomic(&i915->drm, 5732 "[CRTC:%d:%s] atomic driver check failed\n", 5733 crtc->base.base.id, crtc->base.name); 5734 return ret; 5735 } 5736 } 5737 5738 return 0; 5739 } 5740 5741 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, 5742 u8 transcoders) 5743 { 5744 const struct intel_crtc_state *new_crtc_state; 5745 struct intel_crtc *crtc; 5746 int i; 5747 5748 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 5749 if (new_crtc_state->hw.enable && 5750 transcoders & BIT(new_crtc_state->cpu_transcoder) && 5751 intel_crtc_needs_modeset(new_crtc_state)) 5752 return true; 5753 } 5754 5755 return false; 5756 } 5757 5758 static bool intel_pipes_need_modeset(struct intel_atomic_state *state, 5759 u8 pipes) 5760 { 5761 const struct intel_crtc_state *new_crtc_state; 5762 struct intel_crtc *crtc; 5763 int i; 5764 5765 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 5766 if (new_crtc_state->hw.enable && 5767 pipes & BIT(crtc->pipe) && 5768 intel_crtc_needs_modeset(new_crtc_state)) 5769 return true; 5770 } 5771 5772 return false; 5773 } 5774 5775 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state, 5776 struct intel_crtc *master_crtc) 5777 { 5778 struct drm_i915_private *i915 = to_i915(state->base.dev); 5779 struct intel_crtc_state *master_crtc_state = 5780 intel_atomic_get_new_crtc_state(state, master_crtc); 5781 struct intel_crtc *slave_crtc; 5782 5783 if (!master_crtc_state->bigjoiner_pipes) 5784 return 0; 5785 5786 /* sanity check */ 5787 if (drm_WARN_ON(&i915->drm, 5788 master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state))) 5789 return -EINVAL; 5790 5791 if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) { 5792 drm_dbg_kms(&i915->drm, 5793 "[CRTC:%d:%s] Cannot act as big joiner master " 5794 "(need 0x%x as pipes, only 0x%x possible)\n", 5795 master_crtc->base.base.id, master_crtc->base.name, 5796 master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915)); 5797 return -EINVAL; 5798 } 5799 5800 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 5801 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 5802 struct intel_crtc_state *slave_crtc_state; 5803 int ret; 5804 5805 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc); 5806 if (IS_ERR(slave_crtc_state)) 5807 return PTR_ERR(slave_crtc_state); 5808 5809 /* master being enabled, slave was already configured? */ 5810 if (slave_crtc_state->uapi.enable) { 5811 drm_dbg_kms(&i915->drm, 5812 "[CRTC:%d:%s] Slave is enabled as normal CRTC, but " 5813 "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n", 5814 slave_crtc->base.base.id, slave_crtc->base.name, 5815 master_crtc->base.base.id, master_crtc->base.name); 5816 return -EINVAL; 5817 } 5818 5819 /* 5820 * The state copy logic assumes the master crtc gets processed 5821 * before the slave crtc during the main compute_config loop. 5822 * This works because the crtcs are created in pipe order, 5823 * and the hardware requires master pipe < slave pipe as well. 5824 * Should that change we need to rethink the logic. 5825 */ 5826 if (WARN_ON(drm_crtc_index(&master_crtc->base) > 5827 drm_crtc_index(&slave_crtc->base))) 5828 return -EINVAL; 5829 5830 drm_dbg_kms(&i915->drm, 5831 "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n", 5832 slave_crtc->base.base.id, slave_crtc->base.name, 5833 master_crtc->base.base.id, master_crtc->base.name); 5834 5835 slave_crtc_state->bigjoiner_pipes = 5836 master_crtc_state->bigjoiner_pipes; 5837 5838 ret = copy_bigjoiner_crtc_state_modeset(state, slave_crtc); 5839 if (ret) 5840 return ret; 5841 } 5842 5843 return 0; 5844 } 5845 5846 static void kill_bigjoiner_slave(struct intel_atomic_state *state, 5847 struct intel_crtc *master_crtc) 5848 { 5849 struct drm_i915_private *i915 = to_i915(state->base.dev); 5850 struct intel_crtc_state *master_crtc_state = 5851 intel_atomic_get_new_crtc_state(state, master_crtc); 5852 struct intel_crtc *slave_crtc; 5853 5854 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 5855 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 5856 struct intel_crtc_state *slave_crtc_state = 5857 intel_atomic_get_new_crtc_state(state, slave_crtc); 5858 5859 slave_crtc_state->bigjoiner_pipes = 0; 5860 5861 intel_crtc_copy_uapi_to_hw_state_modeset(state, slave_crtc); 5862 } 5863 5864 master_crtc_state->bigjoiner_pipes = 0; 5865 } 5866 5867 /** 5868 * DOC: asynchronous flip implementation 5869 * 5870 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC 5871 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL. 5872 * Correspondingly, support is currently added for primary plane only. 5873 * 5874 * Async flip can only change the plane surface address, so anything else 5875 * changing is rejected from the intel_async_flip_check_hw() function. 5876 * Once this check is cleared, flip done interrupt is enabled using 5877 * the intel_crtc_enable_flip_done() function. 5878 * 5879 * As soon as the surface address register is written, flip done interrupt is 5880 * generated and the requested events are sent to the usersapce in the interrupt 5881 * handler itself. The timestamp and sequence sent during the flip done event 5882 * correspond to the last vblank and have no relation to the actual time when 5883 * the flip done event was sent. 5884 */ 5885 static int intel_async_flip_check_uapi(struct intel_atomic_state *state, 5886 struct intel_crtc *crtc) 5887 { 5888 struct drm_i915_private *i915 = to_i915(state->base.dev); 5889 const struct intel_crtc_state *new_crtc_state = 5890 intel_atomic_get_new_crtc_state(state, crtc); 5891 const struct intel_plane_state *old_plane_state; 5892 struct intel_plane_state *new_plane_state; 5893 struct intel_plane *plane; 5894 int i; 5895 5896 if (!new_crtc_state->uapi.async_flip) 5897 return 0; 5898 5899 if (!new_crtc_state->uapi.active) { 5900 drm_dbg_kms(&i915->drm, 5901 "[CRTC:%d:%s] not active\n", 5902 crtc->base.base.id, crtc->base.name); 5903 return -EINVAL; 5904 } 5905 5906 if (intel_crtc_needs_modeset(new_crtc_state)) { 5907 drm_dbg_kms(&i915->drm, 5908 "[CRTC:%d:%s] modeset required\n", 5909 crtc->base.base.id, crtc->base.name); 5910 return -EINVAL; 5911 } 5912 5913 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 5914 new_plane_state, i) { 5915 if (plane->pipe != crtc->pipe) 5916 continue; 5917 5918 /* 5919 * TODO: Async flip is only supported through the page flip IOCTL 5920 * as of now. So support currently added for primary plane only. 5921 * Support for other planes on platforms on which supports 5922 * this(vlv/chv and icl+) should be added when async flip is 5923 * enabled in the atomic IOCTL path. 5924 */ 5925 if (!plane->async_flip) { 5926 drm_dbg_kms(&i915->drm, 5927 "[PLANE:%d:%s] async flip not supported\n", 5928 plane->base.base.id, plane->base.name); 5929 return -EINVAL; 5930 } 5931 5932 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) { 5933 drm_dbg_kms(&i915->drm, 5934 "[PLANE:%d:%s] no old or new framebuffer\n", 5935 plane->base.base.id, plane->base.name); 5936 return -EINVAL; 5937 } 5938 } 5939 5940 return 0; 5941 } 5942 5943 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc) 5944 { 5945 struct drm_i915_private *i915 = to_i915(state->base.dev); 5946 const struct intel_crtc_state *old_crtc_state, *new_crtc_state; 5947 const struct intel_plane_state *new_plane_state, *old_plane_state; 5948 struct intel_plane *plane; 5949 int i; 5950 5951 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 5952 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 5953 5954 if (!new_crtc_state->uapi.async_flip) 5955 return 0; 5956 5957 if (!new_crtc_state->hw.active) { 5958 drm_dbg_kms(&i915->drm, 5959 "[CRTC:%d:%s] not active\n", 5960 crtc->base.base.id, crtc->base.name); 5961 return -EINVAL; 5962 } 5963 5964 if (intel_crtc_needs_modeset(new_crtc_state)) { 5965 drm_dbg_kms(&i915->drm, 5966 "[CRTC:%d:%s] modeset required\n", 5967 crtc->base.base.id, crtc->base.name); 5968 return -EINVAL; 5969 } 5970 5971 if (old_crtc_state->active_planes != new_crtc_state->active_planes) { 5972 drm_dbg_kms(&i915->drm, 5973 "[CRTC:%d:%s] Active planes cannot be in async flip\n", 5974 crtc->base.base.id, crtc->base.name); 5975 return -EINVAL; 5976 } 5977 5978 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 5979 new_plane_state, i) { 5980 if (plane->pipe != crtc->pipe) 5981 continue; 5982 5983 /* 5984 * Only async flip capable planes should be in the state 5985 * if we're really about to ask the hardware to perform 5986 * an async flip. We should never get this far otherwise. 5987 */ 5988 if (drm_WARN_ON(&i915->drm, 5989 new_crtc_state->do_async_flip && !plane->async_flip)) 5990 return -EINVAL; 5991 5992 /* 5993 * Only check async flip capable planes other planes 5994 * may be involved in the initial commit due to 5995 * the wm0/ddb optimization. 5996 * 5997 * TODO maybe should track which planes actually 5998 * were requested to do the async flip... 5999 */ 6000 if (!plane->async_flip) 6001 continue; 6002 6003 /* 6004 * FIXME: This check is kept generic for all platforms. 6005 * Need to verify this for all gen9 platforms to enable 6006 * this selectively if required. 6007 */ 6008 switch (new_plane_state->hw.fb->modifier) { 6009 case DRM_FORMAT_MOD_LINEAR: 6010 /* 6011 * FIXME: Async on Linear buffer is supported on ICL as 6012 * but with additional alignment and fbc restrictions 6013 * need to be taken care of. These aren't applicable for 6014 * gen12+. 6015 */ 6016 if (DISPLAY_VER(i915) < 12) { 6017 drm_dbg_kms(&i915->drm, 6018 "[PLANE:%d:%s] Modifier 0x%llx does not support async flip on display ver %d\n", 6019 plane->base.base.id, plane->base.name, 6020 new_plane_state->hw.fb->modifier, DISPLAY_VER(i915)); 6021 return -EINVAL; 6022 } 6023 break; 6024 6025 case I915_FORMAT_MOD_X_TILED: 6026 case I915_FORMAT_MOD_Y_TILED: 6027 case I915_FORMAT_MOD_Yf_TILED: 6028 case I915_FORMAT_MOD_4_TILED: 6029 break; 6030 default: 6031 drm_dbg_kms(&i915->drm, 6032 "[PLANE:%d:%s] Modifier 0x%llx does not support async flip\n", 6033 plane->base.base.id, plane->base.name, 6034 new_plane_state->hw.fb->modifier); 6035 return -EINVAL; 6036 } 6037 6038 if (new_plane_state->hw.fb->format->num_planes > 1) { 6039 drm_dbg_kms(&i915->drm, 6040 "[PLANE:%d:%s] Planar formats do not support async flips\n", 6041 plane->base.base.id, plane->base.name); 6042 return -EINVAL; 6043 } 6044 6045 if (old_plane_state->view.color_plane[0].mapping_stride != 6046 new_plane_state->view.color_plane[0].mapping_stride) { 6047 drm_dbg_kms(&i915->drm, 6048 "[PLANE:%d:%s] Stride cannot be changed in async flip\n", 6049 plane->base.base.id, plane->base.name); 6050 return -EINVAL; 6051 } 6052 6053 if (old_plane_state->hw.fb->modifier != 6054 new_plane_state->hw.fb->modifier) { 6055 drm_dbg_kms(&i915->drm, 6056 "[PLANE:%d:%s] Modifier cannot be changed in async flip\n", 6057 plane->base.base.id, plane->base.name); 6058 return -EINVAL; 6059 } 6060 6061 if (old_plane_state->hw.fb->format != 6062 new_plane_state->hw.fb->format) { 6063 drm_dbg_kms(&i915->drm, 6064 "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n", 6065 plane->base.base.id, plane->base.name); 6066 return -EINVAL; 6067 } 6068 6069 if (old_plane_state->hw.rotation != 6070 new_plane_state->hw.rotation) { 6071 drm_dbg_kms(&i915->drm, 6072 "[PLANE:%d:%s] Rotation cannot be changed in async flip\n", 6073 plane->base.base.id, plane->base.name); 6074 return -EINVAL; 6075 } 6076 6077 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) || 6078 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) { 6079 drm_dbg_kms(&i915->drm, 6080 "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n", 6081 plane->base.base.id, plane->base.name); 6082 return -EINVAL; 6083 } 6084 6085 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) { 6086 drm_dbg_kms(&i915->drm, 6087 "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n", 6088 plane->base.base.id, plane->base.name); 6089 return -EINVAL; 6090 } 6091 6092 if (old_plane_state->hw.pixel_blend_mode != 6093 new_plane_state->hw.pixel_blend_mode) { 6094 drm_dbg_kms(&i915->drm, 6095 "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n", 6096 plane->base.base.id, plane->base.name); 6097 return -EINVAL; 6098 } 6099 6100 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) { 6101 drm_dbg_kms(&i915->drm, 6102 "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n", 6103 plane->base.base.id, plane->base.name); 6104 return -EINVAL; 6105 } 6106 6107 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) { 6108 drm_dbg_kms(&i915->drm, 6109 "[PLANE:%d:%s] Color range cannot be changed in async flip\n", 6110 plane->base.base.id, plane->base.name); 6111 return -EINVAL; 6112 } 6113 6114 /* plane decryption is allow to change only in synchronous flips */ 6115 if (old_plane_state->decrypt != new_plane_state->decrypt) { 6116 drm_dbg_kms(&i915->drm, 6117 "[PLANE:%d:%s] Decryption cannot be changed in async flip\n", 6118 plane->base.base.id, plane->base.name); 6119 return -EINVAL; 6120 } 6121 } 6122 6123 return 0; 6124 } 6125 6126 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state) 6127 { 6128 struct drm_i915_private *i915 = to_i915(state->base.dev); 6129 struct intel_crtc_state *crtc_state; 6130 struct intel_crtc *crtc; 6131 u8 affected_pipes = 0; 6132 u8 modeset_pipes = 0; 6133 int i; 6134 6135 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6136 affected_pipes |= crtc_state->bigjoiner_pipes; 6137 if (intel_crtc_needs_modeset(crtc_state)) 6138 modeset_pipes |= crtc_state->bigjoiner_pipes; 6139 } 6140 6141 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) { 6142 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6143 if (IS_ERR(crtc_state)) 6144 return PTR_ERR(crtc_state); 6145 } 6146 6147 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) { 6148 int ret; 6149 6150 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6151 6152 crtc_state->uapi.mode_changed = true; 6153 6154 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); 6155 if (ret) 6156 return ret; 6157 6158 ret = intel_atomic_add_affected_planes(state, crtc); 6159 if (ret) 6160 return ret; 6161 } 6162 6163 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6164 /* Kill old bigjoiner link, we may re-establish afterwards */ 6165 if (intel_crtc_needs_modeset(crtc_state) && 6166 intel_crtc_is_bigjoiner_master(crtc_state)) 6167 kill_bigjoiner_slave(state, crtc); 6168 } 6169 6170 return 0; 6171 } 6172 6173 /** 6174 * intel_atomic_check - validate state object 6175 * @dev: drm device 6176 * @_state: state to validate 6177 */ 6178 int intel_atomic_check(struct drm_device *dev, 6179 struct drm_atomic_state *_state) 6180 { 6181 struct drm_i915_private *dev_priv = to_i915(dev); 6182 struct intel_atomic_state *state = to_intel_atomic_state(_state); 6183 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6184 struct intel_crtc *crtc; 6185 int ret, i; 6186 bool any_ms = false; 6187 6188 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6189 new_crtc_state, i) { 6190 /* 6191 * crtc's state no longer considered to be inherited 6192 * after the first userspace/client initiated commit. 6193 */ 6194 if (!state->internal) 6195 new_crtc_state->inherited = false; 6196 6197 if (new_crtc_state->inherited != old_crtc_state->inherited) 6198 new_crtc_state->uapi.mode_changed = true; 6199 6200 if (new_crtc_state->uapi.scaling_filter != 6201 old_crtc_state->uapi.scaling_filter) 6202 new_crtc_state->uapi.mode_changed = true; 6203 } 6204 6205 intel_vrr_check_modeset(state); 6206 6207 ret = drm_atomic_helper_check_modeset(dev, &state->base); 6208 if (ret) 6209 goto fail; 6210 6211 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6212 ret = intel_async_flip_check_uapi(state, crtc); 6213 if (ret) 6214 return ret; 6215 } 6216 6217 ret = intel_bigjoiner_add_affected_crtcs(state); 6218 if (ret) 6219 goto fail; 6220 6221 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6222 new_crtc_state, i) { 6223 if (!intel_crtc_needs_modeset(new_crtc_state)) { 6224 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 6225 copy_bigjoiner_crtc_state_nomodeset(state, crtc); 6226 else 6227 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 6228 continue; 6229 } 6230 6231 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) { 6232 drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable); 6233 continue; 6234 } 6235 6236 ret = intel_crtc_prepare_cleared_state(state, crtc); 6237 if (ret) 6238 goto fail; 6239 6240 if (!new_crtc_state->hw.enable) 6241 continue; 6242 6243 ret = intel_modeset_pipe_config(state, crtc); 6244 if (ret) 6245 goto fail; 6246 6247 ret = intel_atomic_check_bigjoiner(state, crtc); 6248 if (ret) 6249 goto fail; 6250 } 6251 6252 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6253 new_crtc_state, i) { 6254 if (!intel_crtc_needs_modeset(new_crtc_state)) 6255 continue; 6256 6257 if (new_crtc_state->hw.enable) { 6258 ret = intel_modeset_pipe_config_late(state, crtc); 6259 if (ret) 6260 goto fail; 6261 } 6262 6263 intel_crtc_check_fastset(old_crtc_state, new_crtc_state); 6264 } 6265 6266 /** 6267 * Check if fastset is allowed by external dependencies like other 6268 * pipes and transcoders. 6269 * 6270 * Right now it only forces a fullmodeset when the MST master 6271 * transcoder did not changed but the pipe of the master transcoder 6272 * needs a fullmodeset so all slaves also needs to do a fullmodeset or 6273 * in case of port synced crtcs, if one of the synced crtcs 6274 * needs a full modeset, all other synced crtcs should be 6275 * forced a full modeset. 6276 */ 6277 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6278 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state)) 6279 continue; 6280 6281 if (intel_dp_mst_is_slave_trans(new_crtc_state)) { 6282 enum transcoder master = new_crtc_state->mst_master_transcoder; 6283 6284 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) { 6285 new_crtc_state->uapi.mode_changed = true; 6286 new_crtc_state->update_pipe = false; 6287 } 6288 } 6289 6290 if (is_trans_port_sync_mode(new_crtc_state)) { 6291 u8 trans = new_crtc_state->sync_mode_slaves_mask; 6292 6293 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER) 6294 trans |= BIT(new_crtc_state->master_transcoder); 6295 6296 if (intel_cpu_transcoders_need_modeset(state, trans)) { 6297 new_crtc_state->uapi.mode_changed = true; 6298 new_crtc_state->update_pipe = false; 6299 } 6300 } 6301 6302 if (new_crtc_state->bigjoiner_pipes) { 6303 if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) { 6304 new_crtc_state->uapi.mode_changed = true; 6305 new_crtc_state->update_pipe = false; 6306 } 6307 } 6308 } 6309 6310 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6311 new_crtc_state, i) { 6312 if (!intel_crtc_needs_modeset(new_crtc_state)) 6313 continue; 6314 6315 any_ms = true; 6316 6317 intel_release_shared_dplls(state, crtc); 6318 } 6319 6320 if (any_ms && !check_digital_port_conflicts(state)) { 6321 drm_dbg_kms(&dev_priv->drm, 6322 "rejecting conflicting digital port configuration\n"); 6323 ret = -EINVAL; 6324 goto fail; 6325 } 6326 6327 ret = drm_dp_mst_atomic_check(&state->base); 6328 if (ret) 6329 goto fail; 6330 6331 ret = intel_atomic_check_planes(state); 6332 if (ret) 6333 goto fail; 6334 6335 ret = intel_compute_global_watermarks(state); 6336 if (ret) 6337 goto fail; 6338 6339 ret = intel_bw_atomic_check(state); 6340 if (ret) 6341 goto fail; 6342 6343 ret = intel_cdclk_atomic_check(state, &any_ms); 6344 if (ret) 6345 goto fail; 6346 6347 if (intel_any_crtc_needs_modeset(state)) 6348 any_ms = true; 6349 6350 if (any_ms) { 6351 ret = intel_modeset_checks(state); 6352 if (ret) 6353 goto fail; 6354 6355 ret = intel_modeset_calc_cdclk(state); 6356 if (ret) 6357 return ret; 6358 } 6359 6360 ret = intel_pmdemand_atomic_check(state); 6361 if (ret) 6362 goto fail; 6363 6364 ret = intel_atomic_check_crtcs(state); 6365 if (ret) 6366 goto fail; 6367 6368 ret = intel_fbc_atomic_check(state); 6369 if (ret) 6370 goto fail; 6371 6372 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6373 new_crtc_state, i) { 6374 intel_color_assert_luts(new_crtc_state); 6375 6376 ret = intel_async_flip_check_hw(state, crtc); 6377 if (ret) 6378 goto fail; 6379 6380 /* Either full modeset or fastset (or neither), never both */ 6381 drm_WARN_ON(&dev_priv->drm, 6382 intel_crtc_needs_modeset(new_crtc_state) && 6383 intel_crtc_needs_fastset(new_crtc_state)); 6384 6385 if (!intel_crtc_needs_modeset(new_crtc_state) && 6386 !intel_crtc_needs_fastset(new_crtc_state)) 6387 continue; 6388 6389 intel_crtc_state_dump(new_crtc_state, state, 6390 intel_crtc_needs_modeset(new_crtc_state) ? 6391 "modeset" : "fastset"); 6392 } 6393 6394 return 0; 6395 6396 fail: 6397 if (ret == -EDEADLK) 6398 return ret; 6399 6400 /* 6401 * FIXME would probably be nice to know which crtc specifically 6402 * caused the failure, in cases where we can pinpoint it. 6403 */ 6404 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6405 new_crtc_state, i) 6406 intel_crtc_state_dump(new_crtc_state, state, "failed"); 6407 6408 return ret; 6409 } 6410 6411 static int intel_atomic_prepare_commit(struct intel_atomic_state *state) 6412 { 6413 struct intel_crtc_state *crtc_state; 6414 struct intel_crtc *crtc; 6415 int i, ret; 6416 6417 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base); 6418 if (ret < 0) 6419 return ret; 6420 6421 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6422 if (intel_crtc_needs_color_update(crtc_state)) 6423 intel_color_prepare_commit(crtc_state); 6424 } 6425 6426 return 0; 6427 } 6428 6429 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 6430 struct intel_crtc_state *crtc_state) 6431 { 6432 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6433 6434 if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes) 6435 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 6436 6437 if (crtc_state->has_pch_encoder) { 6438 enum pipe pch_transcoder = 6439 intel_crtc_pch_transcoder(crtc); 6440 6441 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true); 6442 } 6443 } 6444 6445 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, 6446 const struct intel_crtc_state *new_crtc_state) 6447 { 6448 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 6449 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6450 6451 /* 6452 * Update pipe size and adjust fitter if needed: the reason for this is 6453 * that in compute_mode_changes we check the native mode (not the pfit 6454 * mode) to see if we can flip rather than do a full mode set. In the 6455 * fastboot case, we'll flip, but if we don't update the pipesrc and 6456 * pfit state, we'll end up with a big fb scanned out into the wrong 6457 * sized surface. 6458 */ 6459 intel_set_pipe_src_size(new_crtc_state); 6460 6461 /* on skylake this is done by detaching scalers */ 6462 if (DISPLAY_VER(dev_priv) >= 9) { 6463 if (new_crtc_state->pch_pfit.enabled) 6464 skl_pfit_enable(new_crtc_state); 6465 } else if (HAS_PCH_SPLIT(dev_priv)) { 6466 if (new_crtc_state->pch_pfit.enabled) 6467 ilk_pfit_enable(new_crtc_state); 6468 else if (old_crtc_state->pch_pfit.enabled) 6469 ilk_pfit_disable(old_crtc_state); 6470 } 6471 6472 /* 6473 * The register is supposedly single buffered so perhaps 6474 * not 100% correct to do this here. But SKL+ calculate 6475 * this based on the adjust pixel rate so pfit changes do 6476 * affect it and so it must be updated for fastsets. 6477 * HSW/BDW only really need this here for fastboot, after 6478 * that the value should not change without a full modeset. 6479 */ 6480 if (DISPLAY_VER(dev_priv) >= 9 || 6481 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 6482 hsw_set_linetime_wm(new_crtc_state); 6483 6484 if (new_crtc_state->seamless_m_n) 6485 intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder, 6486 &new_crtc_state->dp_m_n); 6487 } 6488 6489 static void commit_pipe_pre_planes(struct intel_atomic_state *state, 6490 struct intel_crtc *crtc) 6491 { 6492 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6493 const struct intel_crtc_state *old_crtc_state = 6494 intel_atomic_get_old_crtc_state(state, crtc); 6495 const struct intel_crtc_state *new_crtc_state = 6496 intel_atomic_get_new_crtc_state(state, crtc); 6497 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 6498 6499 /* 6500 * During modesets pipe configuration was programmed as the 6501 * CRTC was enabled. 6502 */ 6503 if (!modeset) { 6504 if (intel_crtc_needs_color_update(new_crtc_state)) 6505 intel_color_commit_arm(new_crtc_state); 6506 6507 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 6508 bdw_set_pipe_misc(new_crtc_state); 6509 6510 if (intel_crtc_needs_fastset(new_crtc_state)) 6511 intel_pipe_fastset(old_crtc_state, new_crtc_state); 6512 } 6513 6514 intel_psr2_program_trans_man_trk_ctl(new_crtc_state); 6515 6516 intel_atomic_update_watermarks(state, crtc); 6517 } 6518 6519 static void commit_pipe_post_planes(struct intel_atomic_state *state, 6520 struct intel_crtc *crtc) 6521 { 6522 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6523 const struct intel_crtc_state *new_crtc_state = 6524 intel_atomic_get_new_crtc_state(state, crtc); 6525 6526 /* 6527 * Disable the scaler(s) after the plane(s) so that we don't 6528 * get a catastrophic underrun even if the two operations 6529 * end up happening in two different frames. 6530 */ 6531 if (DISPLAY_VER(dev_priv) >= 9 && 6532 !intel_crtc_needs_modeset(new_crtc_state)) 6533 skl_detach_scalers(new_crtc_state); 6534 } 6535 6536 static void intel_enable_crtc(struct intel_atomic_state *state, 6537 struct intel_crtc *crtc) 6538 { 6539 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6540 const struct intel_crtc_state *new_crtc_state = 6541 intel_atomic_get_new_crtc_state(state, crtc); 6542 6543 if (!intel_crtc_needs_modeset(new_crtc_state)) 6544 return; 6545 6546 /* VRR will be enable later, if required */ 6547 intel_crtc_update_active_timings(new_crtc_state, false); 6548 6549 dev_priv->display.funcs.display->crtc_enable(state, crtc); 6550 6551 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 6552 return; 6553 6554 /* vblanks work again, re-enable pipe CRC. */ 6555 intel_crtc_enable_pipe_crc(crtc); 6556 } 6557 6558 static void intel_update_crtc(struct intel_atomic_state *state, 6559 struct intel_crtc *crtc) 6560 { 6561 struct drm_i915_private *i915 = to_i915(state->base.dev); 6562 const struct intel_crtc_state *old_crtc_state = 6563 intel_atomic_get_old_crtc_state(state, crtc); 6564 struct intel_crtc_state *new_crtc_state = 6565 intel_atomic_get_new_crtc_state(state, crtc); 6566 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 6567 6568 if (old_crtc_state->inherited || 6569 intel_crtc_needs_modeset(new_crtc_state)) { 6570 if (HAS_DPT(i915)) 6571 intel_dpt_configure(crtc); 6572 } 6573 6574 if (vrr_enabling(old_crtc_state, new_crtc_state)) { 6575 intel_vrr_enable(new_crtc_state); 6576 intel_crtc_update_active_timings(new_crtc_state, 6577 new_crtc_state->vrr.enable); 6578 } 6579 6580 if (!modeset) { 6581 if (new_crtc_state->preload_luts && 6582 intel_crtc_needs_color_update(new_crtc_state)) 6583 intel_color_load_luts(new_crtc_state); 6584 6585 intel_pre_plane_update(state, crtc); 6586 6587 if (intel_crtc_needs_fastset(new_crtc_state)) 6588 intel_encoders_update_pipe(state, crtc); 6589 6590 if (DISPLAY_VER(i915) >= 11 && 6591 intel_crtc_needs_fastset(new_crtc_state)) 6592 icl_set_pipe_chicken(new_crtc_state); 6593 } 6594 6595 intel_fbc_update(state, crtc); 6596 6597 drm_WARN_ON(&i915->drm, !intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF)); 6598 6599 if (!modeset && 6600 intel_crtc_needs_color_update(new_crtc_state)) 6601 intel_color_commit_noarm(new_crtc_state); 6602 6603 intel_crtc_planes_update_noarm(state, crtc); 6604 6605 /* Perform vblank evasion around commit operation */ 6606 intel_pipe_update_start(new_crtc_state); 6607 6608 commit_pipe_pre_planes(state, crtc); 6609 6610 intel_crtc_planes_update_arm(state, crtc); 6611 6612 commit_pipe_post_planes(state, crtc); 6613 6614 intel_pipe_update_end(new_crtc_state); 6615 6616 /* 6617 * We usually enable FIFO underrun interrupts as part of the 6618 * CRTC enable sequence during modesets. But when we inherit a 6619 * valid pipe configuration from the BIOS we need to take care 6620 * of enabling them on the CRTC's first fastset. 6621 */ 6622 if (intel_crtc_needs_fastset(new_crtc_state) && !modeset && 6623 old_crtc_state->inherited) 6624 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state); 6625 } 6626 6627 static void intel_old_crtc_state_disables(struct intel_atomic_state *state, 6628 struct intel_crtc_state *old_crtc_state, 6629 struct intel_crtc_state *new_crtc_state, 6630 struct intel_crtc *crtc) 6631 { 6632 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6633 6634 /* 6635 * We need to disable pipe CRC before disabling the pipe, 6636 * or we race against vblank off. 6637 */ 6638 intel_crtc_disable_pipe_crc(crtc); 6639 6640 dev_priv->display.funcs.display->crtc_disable(state, crtc); 6641 crtc->active = false; 6642 intel_fbc_disable(crtc); 6643 6644 if (!new_crtc_state->hw.active) 6645 intel_initial_watermarks(state, crtc); 6646 } 6647 6648 static void intel_commit_modeset_disables(struct intel_atomic_state *state) 6649 { 6650 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 6651 struct intel_crtc *crtc; 6652 u32 handled = 0; 6653 int i; 6654 6655 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6656 new_crtc_state, i) { 6657 if (!intel_crtc_needs_modeset(new_crtc_state)) 6658 continue; 6659 6660 if (!old_crtc_state->hw.active) 6661 continue; 6662 6663 intel_pre_plane_update(state, crtc); 6664 intel_crtc_disable_planes(state, crtc); 6665 } 6666 6667 /* Only disable port sync and MST slaves */ 6668 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6669 new_crtc_state, i) { 6670 if (!intel_crtc_needs_modeset(new_crtc_state)) 6671 continue; 6672 6673 if (!old_crtc_state->hw.active) 6674 continue; 6675 6676 /* In case of Transcoder port Sync master slave CRTCs can be 6677 * assigned in any order and we need to make sure that 6678 * slave CRTCs are disabled first and then master CRTC since 6679 * Slave vblanks are masked till Master Vblanks. 6680 */ 6681 if (!is_trans_port_sync_slave(old_crtc_state) && 6682 !intel_dp_mst_is_slave_trans(old_crtc_state) && 6683 !intel_crtc_is_bigjoiner_slave(old_crtc_state)) 6684 continue; 6685 6686 intel_old_crtc_state_disables(state, old_crtc_state, 6687 new_crtc_state, crtc); 6688 handled |= BIT(crtc->pipe); 6689 } 6690 6691 /* Disable everything else left on */ 6692 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6693 new_crtc_state, i) { 6694 if (!intel_crtc_needs_modeset(new_crtc_state) || 6695 (handled & BIT(crtc->pipe))) 6696 continue; 6697 6698 if (!old_crtc_state->hw.active) 6699 continue; 6700 6701 intel_old_crtc_state_disables(state, old_crtc_state, 6702 new_crtc_state, crtc); 6703 } 6704 } 6705 6706 static void intel_commit_modeset_enables(struct intel_atomic_state *state) 6707 { 6708 struct intel_crtc_state *new_crtc_state; 6709 struct intel_crtc *crtc; 6710 int i; 6711 6712 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6713 if (!new_crtc_state->hw.active) 6714 continue; 6715 6716 intel_enable_crtc(state, crtc); 6717 intel_update_crtc(state, crtc); 6718 } 6719 } 6720 6721 static void skl_commit_modeset_enables(struct intel_atomic_state *state) 6722 { 6723 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6724 struct intel_crtc *crtc; 6725 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6726 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; 6727 u8 update_pipes = 0, modeset_pipes = 0; 6728 int i; 6729 6730 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6731 enum pipe pipe = crtc->pipe; 6732 6733 if (!new_crtc_state->hw.active) 6734 continue; 6735 6736 /* ignore allocations for crtc's that have been turned off. */ 6737 if (!intel_crtc_needs_modeset(new_crtc_state)) { 6738 entries[pipe] = old_crtc_state->wm.skl.ddb; 6739 update_pipes |= BIT(pipe); 6740 } else { 6741 modeset_pipes |= BIT(pipe); 6742 } 6743 } 6744 6745 /* 6746 * Whenever the number of active pipes changes, we need to make sure we 6747 * update the pipes in the right order so that their ddb allocations 6748 * never overlap with each other between CRTC updates. Otherwise we'll 6749 * cause pipe underruns and other bad stuff. 6750 * 6751 * So first lets enable all pipes that do not need a fullmodeset as 6752 * those don't have any external dependency. 6753 */ 6754 while (update_pipes) { 6755 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6756 new_crtc_state, i) { 6757 enum pipe pipe = crtc->pipe; 6758 6759 if ((update_pipes & BIT(pipe)) == 0) 6760 continue; 6761 6762 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 6763 entries, I915_MAX_PIPES, pipe)) 6764 continue; 6765 6766 entries[pipe] = new_crtc_state->wm.skl.ddb; 6767 update_pipes &= ~BIT(pipe); 6768 6769 intel_update_crtc(state, crtc); 6770 6771 /* 6772 * If this is an already active pipe, it's DDB changed, 6773 * and this isn't the last pipe that needs updating 6774 * then we need to wait for a vblank to pass for the 6775 * new ddb allocation to take effect. 6776 */ 6777 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, 6778 &old_crtc_state->wm.skl.ddb) && 6779 (update_pipes | modeset_pipes)) 6780 intel_crtc_wait_for_next_vblank(crtc); 6781 } 6782 } 6783 6784 update_pipes = modeset_pipes; 6785 6786 /* 6787 * Enable all pipes that needs a modeset and do not depends on other 6788 * pipes 6789 */ 6790 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6791 enum pipe pipe = crtc->pipe; 6792 6793 if ((modeset_pipes & BIT(pipe)) == 0) 6794 continue; 6795 6796 if (intel_dp_mst_is_slave_trans(new_crtc_state) || 6797 is_trans_port_sync_master(new_crtc_state) || 6798 intel_crtc_is_bigjoiner_master(new_crtc_state)) 6799 continue; 6800 6801 modeset_pipes &= ~BIT(pipe); 6802 6803 intel_enable_crtc(state, crtc); 6804 } 6805 6806 /* 6807 * Then we enable all remaining pipes that depend on other 6808 * pipes: MST slaves and port sync masters, big joiner master 6809 */ 6810 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6811 enum pipe pipe = crtc->pipe; 6812 6813 if ((modeset_pipes & BIT(pipe)) == 0) 6814 continue; 6815 6816 modeset_pipes &= ~BIT(pipe); 6817 6818 intel_enable_crtc(state, crtc); 6819 } 6820 6821 /* 6822 * Finally we do the plane updates/etc. for all pipes that got enabled. 6823 */ 6824 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6825 enum pipe pipe = crtc->pipe; 6826 6827 if ((update_pipes & BIT(pipe)) == 0) 6828 continue; 6829 6830 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 6831 entries, I915_MAX_PIPES, pipe)); 6832 6833 entries[pipe] = new_crtc_state->wm.skl.ddb; 6834 update_pipes &= ~BIT(pipe); 6835 6836 intel_update_crtc(state, crtc); 6837 } 6838 6839 drm_WARN_ON(&dev_priv->drm, modeset_pipes); 6840 drm_WARN_ON(&dev_priv->drm, update_pipes); 6841 } 6842 6843 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) 6844 { 6845 struct intel_atomic_state *state, *next; 6846 struct llist_node *freed; 6847 6848 freed = llist_del_all(&dev_priv->display.atomic_helper.free_list); 6849 llist_for_each_entry_safe(state, next, freed, freed) 6850 drm_atomic_state_put(&state->base); 6851 } 6852 6853 void intel_atomic_helper_free_state_worker(struct work_struct *work) 6854 { 6855 struct drm_i915_private *dev_priv = 6856 container_of(work, typeof(*dev_priv), display.atomic_helper.free_work); 6857 6858 intel_atomic_helper_free_state(dev_priv); 6859 } 6860 6861 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) 6862 { 6863 struct wait_queue_entry wait_fence, wait_reset; 6864 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); 6865 6866 init_wait_entry(&wait_fence, 0); 6867 init_wait_entry(&wait_reset, 0); 6868 for (;;) { 6869 prepare_to_wait(&intel_state->commit_ready.wait, 6870 &wait_fence, TASK_UNINTERRUPTIBLE); 6871 prepare_to_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 6872 I915_RESET_MODESET), 6873 &wait_reset, TASK_UNINTERRUPTIBLE); 6874 6875 6876 if (i915_sw_fence_done(&intel_state->commit_ready) || 6877 test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags)) 6878 break; 6879 6880 schedule(); 6881 } 6882 finish_wait(&intel_state->commit_ready.wait, &wait_fence); 6883 finish_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 6884 I915_RESET_MODESET), 6885 &wait_reset); 6886 } 6887 6888 static void intel_atomic_cleanup_work(struct work_struct *work) 6889 { 6890 struct intel_atomic_state *state = 6891 container_of(work, struct intel_atomic_state, base.commit_work); 6892 struct drm_i915_private *i915 = to_i915(state->base.dev); 6893 struct intel_crtc_state *old_crtc_state; 6894 struct intel_crtc *crtc; 6895 int i; 6896 6897 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) 6898 intel_color_cleanup_commit(old_crtc_state); 6899 6900 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base); 6901 drm_atomic_helper_commit_cleanup_done(&state->base); 6902 drm_atomic_state_put(&state->base); 6903 6904 intel_atomic_helper_free_state(i915); 6905 } 6906 6907 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state) 6908 { 6909 struct drm_i915_private *i915 = to_i915(state->base.dev); 6910 struct intel_plane *plane; 6911 struct intel_plane_state *plane_state; 6912 int i; 6913 6914 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 6915 struct drm_framebuffer *fb = plane_state->hw.fb; 6916 int cc_plane; 6917 int ret; 6918 6919 if (!fb) 6920 continue; 6921 6922 cc_plane = intel_fb_rc_ccs_cc_plane(fb); 6923 if (cc_plane < 0) 6924 continue; 6925 6926 /* 6927 * The layout of the fast clear color value expected by HW 6928 * (the DRM ABI requiring this value to be located in fb at 6929 * offset 0 of cc plane, plane #2 previous generations or 6930 * plane #1 for flat ccs): 6931 * - 4 x 4 bytes per-channel value 6932 * (in surface type specific float/int format provided by the fb user) 6933 * - 8 bytes native color value used by the display 6934 * (converted/written by GPU during a fast clear operation using the 6935 * above per-channel values) 6936 * 6937 * The commit's FB prepare hook already ensured that FB obj is pinned and the 6938 * caller made sure that the object is synced wrt. the related color clear value 6939 * GPU write on it. 6940 */ 6941 ret = i915_gem_object_read_from_page(intel_fb_obj(fb), 6942 fb->offsets[cc_plane] + 16, 6943 &plane_state->ccval, 6944 sizeof(plane_state->ccval)); 6945 /* The above could only fail if the FB obj has an unexpected backing store type. */ 6946 drm_WARN_ON(&i915->drm, ret); 6947 } 6948 } 6949 6950 static void intel_atomic_commit_tail(struct intel_atomic_state *state) 6951 { 6952 struct drm_device *dev = state->base.dev; 6953 struct drm_i915_private *dev_priv = to_i915(dev); 6954 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 6955 struct intel_crtc *crtc; 6956 struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {}; 6957 intel_wakeref_t wakeref = 0; 6958 int i; 6959 6960 intel_atomic_commit_fence_wait(state); 6961 6962 drm_atomic_helper_wait_for_dependencies(&state->base); 6963 drm_dp_mst_atomic_wait_for_dependencies(&state->base); 6964 6965 /* 6966 * During full modesets we write a lot of registers, wait 6967 * for PLLs, etc. Doing that while DC states are enabled 6968 * is not a good idea. 6969 * 6970 * During fastsets and other updates we also need to 6971 * disable DC states due to the following scenario: 6972 * 1. DC5 exit and PSR exit happen 6973 * 2. Some or all _noarm() registers are written 6974 * 3. Due to some long delay PSR is re-entered 6975 * 4. DC5 entry -> DMC saves the already written new 6976 * _noarm() registers and the old not yet written 6977 * _arm() registers 6978 * 5. DC5 exit -> DMC restores a mixture of old and 6979 * new register values and arms the update 6980 * 6. PSR exit -> hardware latches a mixture of old and 6981 * new register values -> corrupted frame, or worse 6982 * 7. New _arm() registers are finally written 6983 * 8. Hardware finally latches a complete set of new 6984 * register values, and subsequent frames will be OK again 6985 * 6986 * Also note that due to the pipe CSC hardware issues on 6987 * SKL/GLK DC states must remain off until the pipe CSC 6988 * state readout has happened. Otherwise we risk corrupting 6989 * the CSC latched register values with the readout (see 6990 * skl_read_csc() and skl_color_commit_noarm()). 6991 */ 6992 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DC_OFF); 6993 6994 intel_atomic_prepare_plane_clear_colors(state); 6995 6996 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6997 new_crtc_state, i) { 6998 if (intel_crtc_needs_modeset(new_crtc_state) || 6999 intel_crtc_needs_fastset(new_crtc_state)) 7000 intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]); 7001 } 7002 7003 intel_commit_modeset_disables(state); 7004 7005 /* FIXME: Eventually get rid of our crtc->config pointer */ 7006 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7007 crtc->config = new_crtc_state; 7008 7009 /* 7010 * In XE_LPD+ Pmdemand combines many parameters such as voltage index, 7011 * plls, cdclk frequency, QGV point selection parameter etc. Voltage 7012 * index, cdclk/ddiclk frequencies are supposed to be configured before 7013 * the cdclk config is set. 7014 */ 7015 intel_pmdemand_pre_plane_update(state); 7016 7017 if (state->modeset) { 7018 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base); 7019 7020 intel_set_cdclk_pre_plane_update(state); 7021 7022 intel_modeset_verify_disabled(dev_priv, state); 7023 } 7024 7025 intel_sagv_pre_plane_update(state); 7026 7027 /* Complete the events for pipes that have now been disabled */ 7028 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7029 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 7030 7031 /* Complete events for now disable pipes here. */ 7032 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) { 7033 spin_lock_irq(&dev->event_lock); 7034 drm_crtc_send_vblank_event(&crtc->base, 7035 new_crtc_state->uapi.event); 7036 spin_unlock_irq(&dev->event_lock); 7037 7038 new_crtc_state->uapi.event = NULL; 7039 } 7040 } 7041 7042 intel_encoders_update_prepare(state); 7043 7044 intel_dbuf_pre_plane_update(state); 7045 intel_mbus_dbox_update(state); 7046 7047 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7048 if (new_crtc_state->do_async_flip) 7049 intel_crtc_enable_flip_done(state, crtc); 7050 } 7051 7052 /* Now enable the clocks, plane, pipe, and connectors that we set up. */ 7053 dev_priv->display.funcs.display->commit_modeset_enables(state); 7054 7055 if (state->modeset) 7056 intel_set_cdclk_post_plane_update(state); 7057 7058 intel_wait_for_vblank_workers(state); 7059 7060 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here 7061 * already, but still need the state for the delayed optimization. To 7062 * fix this: 7063 * - wrap the optimization/post_plane_update stuff into a per-crtc work. 7064 * - schedule that vblank worker _before_ calling hw_done 7065 * - at the start of commit_tail, cancel it _synchrously 7066 * - switch over to the vblank wait helper in the core after that since 7067 * we don't need out special handling any more. 7068 */ 7069 drm_atomic_helper_wait_for_flip_done(dev, &state->base); 7070 7071 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7072 if (new_crtc_state->do_async_flip) 7073 intel_crtc_disable_flip_done(state, crtc); 7074 } 7075 7076 /* 7077 * Now that the vblank has passed, we can go ahead and program the 7078 * optimal watermarks on platforms that need two-step watermark 7079 * programming. 7080 * 7081 * TODO: Move this (and other cleanup) to an async worker eventually. 7082 */ 7083 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7084 new_crtc_state, i) { 7085 /* 7086 * Gen2 reports pipe underruns whenever all planes are disabled. 7087 * So re-enable underrun reporting after some planes get enabled. 7088 * 7089 * We do this before .optimize_watermarks() so that we have a 7090 * chance of catching underruns with the intermediate watermarks 7091 * vs. the new plane configuration. 7092 */ 7093 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state)) 7094 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 7095 7096 intel_optimize_watermarks(state, crtc); 7097 } 7098 7099 intel_dbuf_post_plane_update(state); 7100 intel_psr_post_plane_update(state); 7101 7102 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7103 intel_post_plane_update(state, crtc); 7104 7105 intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]); 7106 7107 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state); 7108 7109 /* Must be done after gamma readout due to HSW split gamma vs. IPS w/a */ 7110 hsw_ips_post_update(state, crtc); 7111 7112 /* 7113 * Activate DRRS after state readout to avoid 7114 * dp_m_n vs. dp_m2_n2 confusion on BDW+. 7115 */ 7116 intel_drrs_activate(new_crtc_state); 7117 7118 /* 7119 * DSB cleanup is done in cleanup_work aligning with framebuffer 7120 * cleanup. So copy and reset the dsb structure to sync with 7121 * commit_done and later do dsb cleanup in cleanup_work. 7122 * 7123 * FIXME get rid of this funny new->old swapping 7124 */ 7125 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb); 7126 } 7127 7128 /* Underruns don't always raise interrupts, so check manually */ 7129 intel_check_cpu_fifo_underruns(dev_priv); 7130 intel_check_pch_fifo_underruns(dev_priv); 7131 7132 if (state->modeset) 7133 intel_verify_planes(state); 7134 7135 intel_sagv_post_plane_update(state); 7136 intel_pmdemand_post_plane_update(state); 7137 7138 drm_atomic_helper_commit_hw_done(&state->base); 7139 7140 if (state->modeset) { 7141 /* As one of the primary mmio accessors, KMS has a high 7142 * likelihood of triggering bugs in unclaimed access. After we 7143 * finish modesetting, see if an error has been flagged, and if 7144 * so enable debugging for the next modeset - and hope we catch 7145 * the culprit. 7146 */ 7147 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); 7148 } 7149 /* 7150 * Delay re-enabling DC states by 17 ms to avoid the off->on->off 7151 * toggling overhead at and above 60 FPS. 7152 */ 7153 intel_display_power_put_async_delay(dev_priv, POWER_DOMAIN_DC_OFF, wakeref, 17); 7154 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7155 7156 /* 7157 * Defer the cleanup of the old state to a separate worker to not 7158 * impede the current task (userspace for blocking modesets) that 7159 * are executed inline. For out-of-line asynchronous modesets/flips, 7160 * deferring to a new worker seems overkill, but we would place a 7161 * schedule point (cond_resched()) here anyway to keep latencies 7162 * down. 7163 */ 7164 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work); 7165 queue_work(system_highpri_wq, &state->base.commit_work); 7166 } 7167 7168 static void intel_atomic_commit_work(struct work_struct *work) 7169 { 7170 struct intel_atomic_state *state = 7171 container_of(work, struct intel_atomic_state, base.commit_work); 7172 7173 intel_atomic_commit_tail(state); 7174 } 7175 7176 static int 7177 intel_atomic_commit_ready(struct i915_sw_fence *fence, 7178 enum i915_sw_fence_notify notify) 7179 { 7180 struct intel_atomic_state *state = 7181 container_of(fence, struct intel_atomic_state, commit_ready); 7182 7183 switch (notify) { 7184 case FENCE_COMPLETE: 7185 /* we do blocking waits in the worker, nothing to do here */ 7186 break; 7187 case FENCE_FREE: 7188 { 7189 struct drm_i915_private *i915 = to_i915(state->base.dev); 7190 struct intel_atomic_helper *helper = 7191 &i915->display.atomic_helper; 7192 7193 if (llist_add(&state->freed, &helper->free_list)) 7194 queue_work(i915->unordered_wq, &helper->free_work); 7195 break; 7196 } 7197 } 7198 7199 return NOTIFY_DONE; 7200 } 7201 7202 static void intel_atomic_track_fbs(struct intel_atomic_state *state) 7203 { 7204 struct intel_plane_state *old_plane_state, *new_plane_state; 7205 struct intel_plane *plane; 7206 int i; 7207 7208 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 7209 new_plane_state, i) 7210 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), 7211 to_intel_frontbuffer(new_plane_state->hw.fb), 7212 plane->frontbuffer_bit); 7213 } 7214 7215 int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state, 7216 bool nonblock) 7217 { 7218 struct intel_atomic_state *state = to_intel_atomic_state(_state); 7219 struct drm_i915_private *dev_priv = to_i915(dev); 7220 int ret = 0; 7221 7222 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 7223 7224 drm_atomic_state_get(&state->base); 7225 i915_sw_fence_init(&state->commit_ready, 7226 intel_atomic_commit_ready); 7227 7228 /* 7229 * The intel_legacy_cursor_update() fast path takes care 7230 * of avoiding the vblank waits for simple cursor 7231 * movement and flips. For cursor on/off and size changes, 7232 * we want to perform the vblank waits so that watermark 7233 * updates happen during the correct frames. Gen9+ have 7234 * double buffered watermarks and so shouldn't need this. 7235 * 7236 * Unset state->legacy_cursor_update before the call to 7237 * drm_atomic_helper_setup_commit() because otherwise 7238 * drm_atomic_helper_wait_for_flip_done() is a noop and 7239 * we get FIFO underruns because we didn't wait 7240 * for vblank. 7241 * 7242 * FIXME doing watermarks and fb cleanup from a vblank worker 7243 * (assuming we had any) would solve these problems. 7244 */ 7245 if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) { 7246 struct intel_crtc_state *new_crtc_state; 7247 struct intel_crtc *crtc; 7248 int i; 7249 7250 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7251 if (new_crtc_state->wm.need_postvbl_update || 7252 new_crtc_state->update_wm_post) 7253 state->base.legacy_cursor_update = false; 7254 } 7255 7256 ret = intel_atomic_prepare_commit(state); 7257 if (ret) { 7258 drm_dbg_atomic(&dev_priv->drm, 7259 "Preparing state failed with %i\n", ret); 7260 i915_sw_fence_commit(&state->commit_ready); 7261 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7262 return ret; 7263 } 7264 7265 ret = drm_atomic_helper_setup_commit(&state->base, nonblock); 7266 if (!ret) 7267 ret = drm_atomic_helper_swap_state(&state->base, true); 7268 if (!ret) 7269 intel_atomic_swap_global_state(state); 7270 7271 if (ret) { 7272 struct intel_crtc_state *new_crtc_state; 7273 struct intel_crtc *crtc; 7274 int i; 7275 7276 i915_sw_fence_commit(&state->commit_ready); 7277 7278 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7279 intel_color_cleanup_commit(new_crtc_state); 7280 7281 drm_atomic_helper_cleanup_planes(dev, &state->base); 7282 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7283 return ret; 7284 } 7285 intel_shared_dpll_swap_state(state); 7286 intel_atomic_track_fbs(state); 7287 7288 drm_atomic_state_get(&state->base); 7289 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work); 7290 7291 i915_sw_fence_commit(&state->commit_ready); 7292 if (nonblock && state->modeset) { 7293 queue_work(dev_priv->display.wq.modeset, &state->base.commit_work); 7294 } else if (nonblock) { 7295 queue_work(dev_priv->display.wq.flip, &state->base.commit_work); 7296 } else { 7297 if (state->modeset) 7298 flush_workqueue(dev_priv->display.wq.modeset); 7299 intel_atomic_commit_tail(state); 7300 } 7301 7302 return 0; 7303 } 7304 7305 /** 7306 * intel_plane_destroy - destroy a plane 7307 * @plane: plane to destroy 7308 * 7309 * Common destruction function for all types of planes (primary, cursor, 7310 * sprite). 7311 */ 7312 void intel_plane_destroy(struct drm_plane *plane) 7313 { 7314 drm_plane_cleanup(plane); 7315 kfree(to_intel_plane(plane)); 7316 } 7317 7318 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 7319 struct drm_file *file) 7320 { 7321 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; 7322 struct drm_crtc *drmmode_crtc; 7323 struct intel_crtc *crtc; 7324 7325 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id); 7326 if (!drmmode_crtc) 7327 return -ENOENT; 7328 7329 crtc = to_intel_crtc(drmmode_crtc); 7330 pipe_from_crtc_id->pipe = crtc->pipe; 7331 7332 return 0; 7333 } 7334 7335 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder) 7336 { 7337 struct drm_device *dev = encoder->base.dev; 7338 struct intel_encoder *source_encoder; 7339 u32 possible_clones = 0; 7340 7341 for_each_intel_encoder(dev, source_encoder) { 7342 if (encoders_cloneable(encoder, source_encoder)) 7343 possible_clones |= drm_encoder_mask(&source_encoder->base); 7344 } 7345 7346 return possible_clones; 7347 } 7348 7349 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder) 7350 { 7351 struct drm_device *dev = encoder->base.dev; 7352 struct intel_crtc *crtc; 7353 u32 possible_crtcs = 0; 7354 7355 for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask) 7356 possible_crtcs |= drm_crtc_mask(&crtc->base); 7357 7358 return possible_crtcs; 7359 } 7360 7361 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv) 7362 { 7363 if (!IS_MOBILE(dev_priv)) 7364 return false; 7365 7366 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0) 7367 return false; 7368 7369 if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE)) 7370 return false; 7371 7372 return true; 7373 } 7374 7375 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv) 7376 { 7377 if (DISPLAY_VER(dev_priv) >= 9) 7378 return false; 7379 7380 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) 7381 return false; 7382 7383 if (HAS_PCH_LPT_H(dev_priv) && 7384 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) 7385 return false; 7386 7387 /* DDI E can't be used if DDI A requires 4 lanes */ 7388 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 7389 return false; 7390 7391 if (!dev_priv->display.vbt.int_crt_support) 7392 return false; 7393 7394 return true; 7395 } 7396 7397 bool assert_port_valid(struct drm_i915_private *i915, enum port port) 7398 { 7399 return !drm_WARN(&i915->drm, !(DISPLAY_RUNTIME_INFO(i915)->port_mask & BIT(port)), 7400 "Platform does not support port %c\n", port_name(port)); 7401 } 7402 7403 void intel_setup_outputs(struct drm_i915_private *dev_priv) 7404 { 7405 struct intel_encoder *encoder; 7406 bool dpd_is_edp = false; 7407 7408 intel_pps_unlock_regs_wa(dev_priv); 7409 7410 if (!HAS_DISPLAY(dev_priv)) 7411 return; 7412 7413 if (HAS_DDI(dev_priv)) { 7414 if (intel_ddi_crt_present(dev_priv)) 7415 intel_crt_init(dev_priv); 7416 7417 intel_bios_for_each_encoder(dev_priv, intel_ddi_init); 7418 7419 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 7420 vlv_dsi_init(dev_priv); 7421 } else if (HAS_PCH_SPLIT(dev_priv)) { 7422 int found; 7423 7424 /* 7425 * intel_edp_init_connector() depends on this completing first, 7426 * to prevent the registration of both eDP and LVDS and the 7427 * incorrect sharing of the PPS. 7428 */ 7429 intel_lvds_init(dev_priv); 7430 intel_crt_init(dev_priv); 7431 7432 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D); 7433 7434 if (ilk_has_edp_a(dev_priv)) 7435 g4x_dp_init(dev_priv, DP_A, PORT_A); 7436 7437 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) { 7438 /* PCH SDVOB multiplex with HDMIB */ 7439 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); 7440 if (!found) 7441 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); 7442 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED)) 7443 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B); 7444 } 7445 7446 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED) 7447 g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); 7448 7449 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED) 7450 g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D); 7451 7452 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED) 7453 g4x_dp_init(dev_priv, PCH_DP_C, PORT_C); 7454 7455 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED) 7456 g4x_dp_init(dev_priv, PCH_DP_D, PORT_D); 7457 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 7458 bool has_edp, has_port; 7459 7460 if (IS_VALLEYVIEW(dev_priv) && dev_priv->display.vbt.int_crt_support) 7461 intel_crt_init(dev_priv); 7462 7463 /* 7464 * The DP_DETECTED bit is the latched state of the DDC 7465 * SDA pin at boot. However since eDP doesn't require DDC 7466 * (no way to plug in a DP->HDMI dongle) the DDC pins for 7467 * eDP ports may have been muxed to an alternate function. 7468 * Thus we can't rely on the DP_DETECTED bit alone to detect 7469 * eDP ports. Consult the VBT as well as DP_DETECTED to 7470 * detect eDP ports. 7471 * 7472 * Sadly the straps seem to be missing sometimes even for HDMI 7473 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap 7474 * and VBT for the presence of the port. Additionally we can't 7475 * trust the port type the VBT declares as we've seen at least 7476 * HDMI ports that the VBT claim are DP or eDP. 7477 */ 7478 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B); 7479 has_port = intel_bios_is_port_present(dev_priv, PORT_B); 7480 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port) 7481 has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B); 7482 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) 7483 g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); 7484 7485 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C); 7486 has_port = intel_bios_is_port_present(dev_priv, PORT_C); 7487 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port) 7488 has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C); 7489 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) 7490 g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); 7491 7492 if (IS_CHERRYVIEW(dev_priv)) { 7493 /* 7494 * eDP not supported on port D, 7495 * so no need to worry about it 7496 */ 7497 has_port = intel_bios_is_port_present(dev_priv, PORT_D); 7498 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port) 7499 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D); 7500 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port) 7501 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D); 7502 } 7503 7504 vlv_dsi_init(dev_priv); 7505 } else if (IS_PINEVIEW(dev_priv)) { 7506 intel_lvds_init(dev_priv); 7507 intel_crt_init(dev_priv); 7508 } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) { 7509 bool found = false; 7510 7511 if (IS_MOBILE(dev_priv)) 7512 intel_lvds_init(dev_priv); 7513 7514 intel_crt_init(dev_priv); 7515 7516 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 7517 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n"); 7518 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); 7519 if (!found && IS_G4X(dev_priv)) { 7520 drm_dbg_kms(&dev_priv->drm, 7521 "probing HDMI on SDVOB\n"); 7522 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); 7523 } 7524 7525 if (!found && IS_G4X(dev_priv)) 7526 g4x_dp_init(dev_priv, DP_B, PORT_B); 7527 } 7528 7529 /* Before G4X SDVOC doesn't have its own detect register */ 7530 7531 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 7532 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n"); 7533 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); 7534 } 7535 7536 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) { 7537 7538 if (IS_G4X(dev_priv)) { 7539 drm_dbg_kms(&dev_priv->drm, 7540 "probing HDMI on SDVOC\n"); 7541 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); 7542 } 7543 if (IS_G4X(dev_priv)) 7544 g4x_dp_init(dev_priv, DP_C, PORT_C); 7545 } 7546 7547 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED)) 7548 g4x_dp_init(dev_priv, DP_D, PORT_D); 7549 7550 if (SUPPORTS_TV(dev_priv)) 7551 intel_tv_init(dev_priv); 7552 } else if (DISPLAY_VER(dev_priv) == 2) { 7553 if (IS_I85X(dev_priv)) 7554 intel_lvds_init(dev_priv); 7555 7556 intel_crt_init(dev_priv); 7557 intel_dvo_init(dev_priv); 7558 } 7559 7560 for_each_intel_encoder(&dev_priv->drm, encoder) { 7561 encoder->base.possible_crtcs = 7562 intel_encoder_possible_crtcs(encoder); 7563 encoder->base.possible_clones = 7564 intel_encoder_possible_clones(encoder); 7565 } 7566 7567 intel_init_pch_refclk(dev_priv); 7568 7569 drm_helper_move_panel_connectors_to_head(&dev_priv->drm); 7570 } 7571 7572 static int max_dotclock(struct drm_i915_private *i915) 7573 { 7574 int max_dotclock = i915->max_dotclk_freq; 7575 7576 /* icl+ might use bigjoiner */ 7577 if (DISPLAY_VER(i915) >= 11) 7578 max_dotclock *= 2; 7579 7580 return max_dotclock; 7581 } 7582 7583 enum drm_mode_status intel_mode_valid(struct drm_device *dev, 7584 const struct drm_display_mode *mode) 7585 { 7586 struct drm_i915_private *dev_priv = to_i915(dev); 7587 int hdisplay_max, htotal_max; 7588 int vdisplay_max, vtotal_max; 7589 7590 /* 7591 * Can't reject DBLSCAN here because Xorg ddxen can add piles 7592 * of DBLSCAN modes to the output's mode list when they detect 7593 * the scaling mode property on the connector. And they don't 7594 * ask the kernel to validate those modes in any way until 7595 * modeset time at which point the client gets a protocol error. 7596 * So in order to not upset those clients we silently ignore the 7597 * DBLSCAN flag on such connectors. For other connectors we will 7598 * reject modes with the DBLSCAN flag in encoder->compute_config(). 7599 * And we always reject DBLSCAN modes in connector->mode_valid() 7600 * as we never want such modes on the connector's mode list. 7601 */ 7602 7603 if (mode->vscan > 1) 7604 return MODE_NO_VSCAN; 7605 7606 if (mode->flags & DRM_MODE_FLAG_HSKEW) 7607 return MODE_H_ILLEGAL; 7608 7609 if (mode->flags & (DRM_MODE_FLAG_CSYNC | 7610 DRM_MODE_FLAG_NCSYNC | 7611 DRM_MODE_FLAG_PCSYNC)) 7612 return MODE_HSYNC; 7613 7614 if (mode->flags & (DRM_MODE_FLAG_BCAST | 7615 DRM_MODE_FLAG_PIXMUX | 7616 DRM_MODE_FLAG_CLKDIV2)) 7617 return MODE_BAD; 7618 7619 /* 7620 * Reject clearly excessive dotclocks early to 7621 * avoid having to worry about huge integers later. 7622 */ 7623 if (mode->clock > max_dotclock(dev_priv)) 7624 return MODE_CLOCK_HIGH; 7625 7626 /* Transcoder timing limits */ 7627 if (DISPLAY_VER(dev_priv) >= 11) { 7628 hdisplay_max = 16384; 7629 vdisplay_max = 8192; 7630 htotal_max = 16384; 7631 vtotal_max = 8192; 7632 } else if (DISPLAY_VER(dev_priv) >= 9 || 7633 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 7634 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ 7635 vdisplay_max = 4096; 7636 htotal_max = 8192; 7637 vtotal_max = 8192; 7638 } else if (DISPLAY_VER(dev_priv) >= 3) { 7639 hdisplay_max = 4096; 7640 vdisplay_max = 4096; 7641 htotal_max = 8192; 7642 vtotal_max = 8192; 7643 } else { 7644 hdisplay_max = 2048; 7645 vdisplay_max = 2048; 7646 htotal_max = 4096; 7647 vtotal_max = 4096; 7648 } 7649 7650 if (mode->hdisplay > hdisplay_max || 7651 mode->hsync_start > htotal_max || 7652 mode->hsync_end > htotal_max || 7653 mode->htotal > htotal_max) 7654 return MODE_H_ILLEGAL; 7655 7656 if (mode->vdisplay > vdisplay_max || 7657 mode->vsync_start > vtotal_max || 7658 mode->vsync_end > vtotal_max || 7659 mode->vtotal > vtotal_max) 7660 return MODE_V_ILLEGAL; 7661 7662 if (DISPLAY_VER(dev_priv) >= 5) { 7663 if (mode->hdisplay < 64 || 7664 mode->htotal - mode->hdisplay < 32) 7665 return MODE_H_ILLEGAL; 7666 7667 if (mode->vtotal - mode->vdisplay < 5) 7668 return MODE_V_ILLEGAL; 7669 } else { 7670 if (mode->htotal - mode->hdisplay < 32) 7671 return MODE_H_ILLEGAL; 7672 7673 if (mode->vtotal - mode->vdisplay < 3) 7674 return MODE_V_ILLEGAL; 7675 } 7676 7677 /* 7678 * Cantiga+ cannot handle modes with a hsync front porch of 0. 7679 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. 7680 */ 7681 if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) && 7682 mode->hsync_start == mode->hdisplay) 7683 return MODE_H_ILLEGAL; 7684 7685 return MODE_OK; 7686 } 7687 7688 enum drm_mode_status 7689 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 7690 const struct drm_display_mode *mode, 7691 bool bigjoiner) 7692 { 7693 int plane_width_max, plane_height_max; 7694 7695 /* 7696 * intel_mode_valid() should be 7697 * sufficient on older platforms. 7698 */ 7699 if (DISPLAY_VER(dev_priv) < 9) 7700 return MODE_OK; 7701 7702 /* 7703 * Most people will probably want a fullscreen 7704 * plane so let's not advertize modes that are 7705 * too big for that. 7706 */ 7707 if (DISPLAY_VER(dev_priv) >= 11) { 7708 plane_width_max = 5120 << bigjoiner; 7709 plane_height_max = 4320; 7710 } else { 7711 plane_width_max = 5120; 7712 plane_height_max = 4096; 7713 } 7714 7715 if (mode->hdisplay > plane_width_max) 7716 return MODE_H_ILLEGAL; 7717 7718 if (mode->vdisplay > plane_height_max) 7719 return MODE_V_ILLEGAL; 7720 7721 return MODE_OK; 7722 } 7723 7724 static const struct intel_display_funcs skl_display_funcs = { 7725 .get_pipe_config = hsw_get_pipe_config, 7726 .crtc_enable = hsw_crtc_enable, 7727 .crtc_disable = hsw_crtc_disable, 7728 .commit_modeset_enables = skl_commit_modeset_enables, 7729 .get_initial_plane_config = skl_get_initial_plane_config, 7730 }; 7731 7732 static const struct intel_display_funcs ddi_display_funcs = { 7733 .get_pipe_config = hsw_get_pipe_config, 7734 .crtc_enable = hsw_crtc_enable, 7735 .crtc_disable = hsw_crtc_disable, 7736 .commit_modeset_enables = intel_commit_modeset_enables, 7737 .get_initial_plane_config = i9xx_get_initial_plane_config, 7738 }; 7739 7740 static const struct intel_display_funcs pch_split_display_funcs = { 7741 .get_pipe_config = ilk_get_pipe_config, 7742 .crtc_enable = ilk_crtc_enable, 7743 .crtc_disable = ilk_crtc_disable, 7744 .commit_modeset_enables = intel_commit_modeset_enables, 7745 .get_initial_plane_config = i9xx_get_initial_plane_config, 7746 }; 7747 7748 static const struct intel_display_funcs vlv_display_funcs = { 7749 .get_pipe_config = i9xx_get_pipe_config, 7750 .crtc_enable = valleyview_crtc_enable, 7751 .crtc_disable = i9xx_crtc_disable, 7752 .commit_modeset_enables = intel_commit_modeset_enables, 7753 .get_initial_plane_config = i9xx_get_initial_plane_config, 7754 }; 7755 7756 static const struct intel_display_funcs i9xx_display_funcs = { 7757 .get_pipe_config = i9xx_get_pipe_config, 7758 .crtc_enable = i9xx_crtc_enable, 7759 .crtc_disable = i9xx_crtc_disable, 7760 .commit_modeset_enables = intel_commit_modeset_enables, 7761 .get_initial_plane_config = i9xx_get_initial_plane_config, 7762 }; 7763 7764 /** 7765 * intel_init_display_hooks - initialize the display modesetting hooks 7766 * @dev_priv: device private 7767 */ 7768 void intel_init_display_hooks(struct drm_i915_private *dev_priv) 7769 { 7770 if (DISPLAY_VER(dev_priv) >= 9) { 7771 dev_priv->display.funcs.display = &skl_display_funcs; 7772 } else if (HAS_DDI(dev_priv)) { 7773 dev_priv->display.funcs.display = &ddi_display_funcs; 7774 } else if (HAS_PCH_SPLIT(dev_priv)) { 7775 dev_priv->display.funcs.display = &pch_split_display_funcs; 7776 } else if (IS_CHERRYVIEW(dev_priv) || 7777 IS_VALLEYVIEW(dev_priv)) { 7778 dev_priv->display.funcs.display = &vlv_display_funcs; 7779 } else { 7780 dev_priv->display.funcs.display = &i9xx_display_funcs; 7781 } 7782 } 7783 7784 int intel_initial_commit(struct drm_device *dev) 7785 { 7786 struct drm_atomic_state *state = NULL; 7787 struct drm_modeset_acquire_ctx ctx; 7788 struct intel_crtc *crtc; 7789 int ret = 0; 7790 7791 state = drm_atomic_state_alloc(dev); 7792 if (!state) 7793 return -ENOMEM; 7794 7795 drm_modeset_acquire_init(&ctx, 0); 7796 7797 state->acquire_ctx = &ctx; 7798 to_intel_atomic_state(state)->internal = true; 7799 7800 retry: 7801 for_each_intel_crtc(dev, crtc) { 7802 struct intel_crtc_state *crtc_state = 7803 intel_atomic_get_crtc_state(state, crtc); 7804 7805 if (IS_ERR(crtc_state)) { 7806 ret = PTR_ERR(crtc_state); 7807 goto out; 7808 } 7809 7810 if (crtc_state->hw.active) { 7811 struct intel_encoder *encoder; 7812 7813 ret = drm_atomic_add_affected_planes(state, &crtc->base); 7814 if (ret) 7815 goto out; 7816 7817 /* 7818 * FIXME hack to force a LUT update to avoid the 7819 * plane update forcing the pipe gamma on without 7820 * having a proper LUT loaded. Remove once we 7821 * have readout for pipe gamma enable. 7822 */ 7823 crtc_state->uapi.color_mgmt_changed = true; 7824 7825 for_each_intel_encoder_mask(dev, encoder, 7826 crtc_state->uapi.encoder_mask) { 7827 if (encoder->initial_fastset_check && 7828 !encoder->initial_fastset_check(encoder, crtc_state)) { 7829 ret = drm_atomic_add_affected_connectors(state, 7830 &crtc->base); 7831 if (ret) 7832 goto out; 7833 } 7834 } 7835 } 7836 } 7837 7838 ret = drm_atomic_commit(state); 7839 7840 out: 7841 if (ret == -EDEADLK) { 7842 drm_atomic_state_clear(state); 7843 drm_modeset_backoff(&ctx); 7844 goto retry; 7845 } 7846 7847 drm_atomic_state_put(state); 7848 7849 drm_modeset_drop_locks(&ctx); 7850 drm_modeset_acquire_fini(&ctx); 7851 7852 return ret; 7853 } 7854 7855 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 7856 { 7857 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 7858 enum transcoder cpu_transcoder = (enum transcoder)pipe; 7859 /* 640x480@60Hz, ~25175 kHz */ 7860 struct dpll clock = { 7861 .m1 = 18, 7862 .m2 = 7, 7863 .p1 = 13, 7864 .p2 = 4, 7865 .n = 2, 7866 }; 7867 u32 dpll, fp; 7868 int i; 7869 7870 drm_WARN_ON(&dev_priv->drm, 7871 i9xx_calc_dpll_params(48000, &clock) != 25154); 7872 7873 drm_dbg_kms(&dev_priv->drm, 7874 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n", 7875 pipe_name(pipe), clock.vco, clock.dot); 7876 7877 fp = i9xx_dpll_compute_fp(&clock); 7878 dpll = DPLL_DVO_2X_MODE | 7879 DPLL_VGA_MODE_DIS | 7880 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | 7881 PLL_P2_DIVIDE_BY_4 | 7882 PLL_REF_INPUT_DREFCLK | 7883 DPLL_VCO_ENABLE; 7884 7885 intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder), 7886 HACTIVE(640 - 1) | HTOTAL(800 - 1)); 7887 intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder), 7888 HBLANK_START(640 - 1) | HBLANK_END(800 - 1)); 7889 intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder), 7890 HSYNC_START(656 - 1) | HSYNC_END(752 - 1)); 7891 intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder), 7892 VACTIVE(480 - 1) | VTOTAL(525 - 1)); 7893 intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), 7894 VBLANK_START(480 - 1) | VBLANK_END(525 - 1)); 7895 intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder), 7896 VSYNC_START(490 - 1) | VSYNC_END(492 - 1)); 7897 intel_de_write(dev_priv, PIPESRC(pipe), 7898 PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1)); 7899 7900 intel_de_write(dev_priv, FP0(pipe), fp); 7901 intel_de_write(dev_priv, FP1(pipe), fp); 7902 7903 /* 7904 * Apparently we need to have VGA mode enabled prior to changing 7905 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 7906 * dividers, even though the register value does change. 7907 */ 7908 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); 7909 intel_de_write(dev_priv, DPLL(pipe), dpll); 7910 7911 /* Wait for the clocks to stabilize. */ 7912 intel_de_posting_read(dev_priv, DPLL(pipe)); 7913 udelay(150); 7914 7915 /* The pixel multiplier can only be updated once the 7916 * DPLL is enabled and the clocks are stable. 7917 * 7918 * So write it again. 7919 */ 7920 intel_de_write(dev_priv, DPLL(pipe), dpll); 7921 7922 /* We do this three times for luck */ 7923 for (i = 0; i < 3 ; i++) { 7924 intel_de_write(dev_priv, DPLL(pipe), dpll); 7925 intel_de_posting_read(dev_priv, DPLL(pipe)); 7926 udelay(150); /* wait for warmup */ 7927 } 7928 7929 intel_de_write(dev_priv, TRANSCONF(pipe), TRANSCONF_ENABLE); 7930 intel_de_posting_read(dev_priv, TRANSCONF(pipe)); 7931 7932 intel_wait_for_pipe_scanline_moving(crtc); 7933 } 7934 7935 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 7936 { 7937 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 7938 7939 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n", 7940 pipe_name(pipe)); 7941 7942 drm_WARN_ON(&dev_priv->drm, 7943 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE); 7944 drm_WARN_ON(&dev_priv->drm, 7945 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE); 7946 drm_WARN_ON(&dev_priv->drm, 7947 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE); 7948 drm_WARN_ON(&dev_priv->drm, 7949 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK); 7950 drm_WARN_ON(&dev_priv->drm, 7951 intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK); 7952 7953 intel_de_write(dev_priv, TRANSCONF(pipe), 0); 7954 intel_de_posting_read(dev_priv, TRANSCONF(pipe)); 7955 7956 intel_wait_for_pipe_scanline_stopped(crtc); 7957 7958 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); 7959 intel_de_posting_read(dev_priv, DPLL(pipe)); 7960 } 7961 7962 void intel_hpd_poll_fini(struct drm_i915_private *i915) 7963 { 7964 struct intel_connector *connector; 7965 struct drm_connector_list_iter conn_iter; 7966 7967 /* Kill all the work that may have been queued by hpd. */ 7968 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 7969 for_each_intel_connector_iter(connector, &conn_iter) { 7970 if (connector->modeset_retry_work.func) 7971 cancel_work_sync(&connector->modeset_retry_work); 7972 if (connector->hdcp.shim) { 7973 cancel_delayed_work_sync(&connector->hdcp.check_work); 7974 cancel_work_sync(&connector->hdcp.prop_work); 7975 } 7976 } 7977 drm_connector_list_iter_end(&conn_iter); 7978 } 7979 7980 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915) 7981 { 7982 return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915); 7983 } 7984