1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2019 Intel Corporation
4  */
5 
6 #ifndef __INTEL_DE_H__
7 #define __INTEL_DE_H__
8 
9 #include "i915_drv.h"
10 #include "i915_trace.h"
11 #include "intel_uncore.h"
12 
13 static inline u32
14 intel_de_read(struct drm_i915_private *i915, i915_reg_t reg)
15 {
16 	return intel_uncore_read(&i915->uncore, reg);
17 }
18 
19 static inline u8
20 intel_de_read8(struct drm_i915_private *i915, i915_reg_t reg)
21 {
22 	return intel_uncore_read8(&i915->uncore, reg);
23 }
24 
25 static inline void
26 intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg)
27 {
28 	intel_uncore_posting_read(&i915->uncore, reg);
29 }
30 
31 static inline void
32 intel_de_write(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
33 {
34 	intel_uncore_write(&i915->uncore, reg, val);
35 }
36 
37 static inline u32
38 intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, u32 clear, u32 set)
39 {
40 	return intel_uncore_rmw(&i915->uncore, reg, clear, set);
41 }
42 
43 static inline int
44 intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg,
45 			   u32 mask, u32 value, unsigned int timeout)
46 {
47 	return intel_wait_for_register(&i915->uncore, reg, mask, value, timeout);
48 }
49 
50 static inline int
51 intel_de_wait_for_register_fw(struct drm_i915_private *i915, i915_reg_t reg,
52 			      u32 mask, u32 value, unsigned int timeout)
53 {
54 	return intel_wait_for_register_fw(&i915->uncore, reg, mask, value, timeout);
55 }
56 
57 static inline int
58 __intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg,
59 			     u32 mask, u32 value,
60 			     unsigned int fast_timeout_us,
61 			     unsigned int slow_timeout_ms, u32 *out_value)
62 {
63 	return __intel_wait_for_register(&i915->uncore, reg, mask, value,
64 					 fast_timeout_us, slow_timeout_ms, out_value);
65 }
66 
67 static inline int
68 intel_de_wait_for_set(struct drm_i915_private *i915, i915_reg_t reg,
69 		      u32 mask, unsigned int timeout)
70 {
71 	return intel_de_wait_for_register(i915, reg, mask, mask, timeout);
72 }
73 
74 static inline int
75 intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t reg,
76 			u32 mask, unsigned int timeout)
77 {
78 	return intel_de_wait_for_register(i915, reg, mask, 0, timeout);
79 }
80 
81 /*
82  * Unlocked mmio-accessors, think carefully before using these.
83  *
84  * Certain architectures will die if the same cacheline is concurrently accessed
85  * by different clients (e.g. on Ivybridge). Access to registers should
86  * therefore generally be serialised, by either the dev_priv->uncore.lock or
87  * a more localised lock guarding all access to that bank of registers.
88  */
89 static inline u32
90 intel_de_read_fw(struct drm_i915_private *i915, i915_reg_t reg)
91 {
92 	u32 val;
93 
94 	val = intel_uncore_read_fw(&i915->uncore, reg);
95 	trace_i915_reg_rw(false, reg, val, sizeof(val), true);
96 
97 	return val;
98 }
99 
100 static inline void
101 intel_de_write_fw(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
102 {
103 	trace_i915_reg_rw(true, reg, val, sizeof(val), true);
104 	intel_uncore_write_fw(&i915->uncore, reg, val);
105 }
106 
107 static inline u32
108 intel_de_read_notrace(struct drm_i915_private *i915, i915_reg_t reg)
109 {
110 	return intel_uncore_read_notrace(&i915->uncore, reg);
111 }
112 
113 static inline void
114 intel_de_write_notrace(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
115 {
116 	intel_uncore_write_notrace(&i915->uncore, reg, val);
117 }
118 
119 #endif /* __INTEL_DE_H__ */
120