1379bc100SJani Nikula /* SPDX-License-Identifier: MIT */ 2379bc100SJani Nikula /* 3379bc100SJani Nikula * Copyright © 2019 Intel Corporation 4379bc100SJani Nikula */ 5379bc100SJani Nikula 6379bc100SJani Nikula #ifndef __INTEL_DDI_H__ 7379bc100SJani Nikula #define __INTEL_DDI_H__ 8379bc100SJani Nikula 9379bc100SJani Nikula #include "intel_display.h" 10*ef79fafeSVille Syrjälä #include "i915_reg.h" 11379bc100SJani Nikula 12379bc100SJani Nikula struct drm_connector_state; 13379bc100SJani Nikula struct drm_i915_private; 14379bc100SJani Nikula struct intel_connector; 15379bc100SJani Nikula struct intel_crtc; 16379bc100SJani Nikula struct intel_crtc_state; 17379bc100SJani Nikula struct intel_dp; 18379bc100SJani Nikula struct intel_dpll_hw_state; 19379bc100SJani Nikula struct intel_encoder; 200b9c9290SSean Paul enum transcoder; 21379bc100SJani Nikula 22*ef79fafeSVille Syrjälä i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 23*ef79fafeSVille Syrjälä const struct intel_crtc_state *crtc_state); 24*ef79fafeSVille Syrjälä i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 25*ef79fafeSVille Syrjälä const struct intel_crtc_state *crtc_state); 26ede9771dSVille Syrjälä void intel_ddi_fdi_post_disable(struct intel_atomic_state *state, 27ede9771dSVille Syrjälä struct intel_encoder *intel_encoder, 28379bc100SJani Nikula const struct intel_crtc_state *old_crtc_state, 29379bc100SJani Nikula const struct drm_connector_state *old_conn_state); 306a6d79deSVille Syrjälä void hsw_fdi_link_train(struct intel_encoder *encoder, 31379bc100SJani Nikula const struct intel_crtc_state *crtc_state); 32379bc100SJani Nikula void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port); 33379bc100SJani Nikula bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); 34eed22a46SVille Syrjälä void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 35eed22a46SVille Syrjälä const struct intel_crtc_state *crtc_state); 36379bc100SJani Nikula void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state); 3702a715c3SVille Syrjälä void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder, 3802a715c3SVille Syrjälä const struct intel_crtc_state *crtc_state); 39379bc100SJani Nikula void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state); 400c06fa15SGwan-gyeong Mun void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 410c06fa15SGwan-gyeong Mun const struct drm_connector_state *conn_state); 42379bc100SJani Nikula bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); 43379bc100SJani Nikula void intel_ddi_get_config(struct intel_encoder *encoder, 44379bc100SJani Nikula struct intel_crtc_state *pipe_config); 45379bc100SJani Nikula void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state, 46379bc100SJani Nikula bool state); 47379bc100SJani Nikula void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, 48379bc100SJani Nikula struct intel_crtc_state *crtc_state); 49a621860aSVille Syrjälä u32 bxt_signal_levels(struct intel_dp *intel_dp, 50a621860aSVille Syrjälä const struct intel_crtc_state *crtc_state); 51a621860aSVille Syrjälä u32 ddi_signal_levels(struct intel_dp *intel_dp, 52a621860aSVille Syrjälä const struct intel_crtc_state *crtc_state); 53379bc100SJani Nikula int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder, 540b9c9290SSean Paul enum transcoder cpu_transcoder, 55379bc100SJani Nikula bool enable); 56379bc100SJani Nikula void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder); 57379bc100SJani Nikula 58379bc100SJani Nikula #endif /* __INTEL_DDI_H__ */ 59