1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <drm/drm_scdc_helper.h> 29 30 #include "i915_drv.h" 31 #include "intel_audio.h" 32 #include "intel_combo_phy.h" 33 #include "intel_connector.h" 34 #include "intel_ddi.h" 35 #include "intel_display_types.h" 36 #include "intel_dp.h" 37 #include "intel_dp_mst.h" 38 #include "intel_dp_link_training.h" 39 #include "intel_dpio_phy.h" 40 #include "intel_dsi.h" 41 #include "intel_fifo_underrun.h" 42 #include "intel_gmbus.h" 43 #include "intel_hdcp.h" 44 #include "intel_hdmi.h" 45 #include "intel_hotplug.h" 46 #include "intel_lspcon.h" 47 #include "intel_panel.h" 48 #include "intel_psr.h" 49 #include "intel_sprite.h" 50 #include "intel_tc.h" 51 #include "intel_vdsc.h" 52 53 struct ddi_buf_trans { 54 u32 trans1; /* balance leg enable, de-emph level */ 55 u32 trans2; /* vref sel, vswing */ 56 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */ 57 }; 58 59 static const u8 index_to_dp_signal_levels[] = { 60 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 61 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 62 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 63 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 64 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 65 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 66 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 67 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 68 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 69 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 70 }; 71 72 /* HDMI/DVI modes ignore everything but the last 2 items. So we share 73 * them for both DP and FDI transports, allowing those ports to 74 * automatically adapt to HDMI connections as well 75 */ 76 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { 77 { 0x00FFFFFF, 0x0006000E, 0x0 }, 78 { 0x00D75FFF, 0x0005000A, 0x0 }, 79 { 0x00C30FFF, 0x00040006, 0x0 }, 80 { 0x80AAAFFF, 0x000B0000, 0x0 }, 81 { 0x00FFFFFF, 0x0005000A, 0x0 }, 82 { 0x00D75FFF, 0x000C0004, 0x0 }, 83 { 0x80C30FFF, 0x000B0000, 0x0 }, 84 { 0x00FFFFFF, 0x00040006, 0x0 }, 85 { 0x80D75FFF, 0x000B0000, 0x0 }, 86 }; 87 88 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { 89 { 0x00FFFFFF, 0x0007000E, 0x0 }, 90 { 0x00D75FFF, 0x000F000A, 0x0 }, 91 { 0x00C30FFF, 0x00060006, 0x0 }, 92 { 0x00AAAFFF, 0x001E0000, 0x0 }, 93 { 0x00FFFFFF, 0x000F000A, 0x0 }, 94 { 0x00D75FFF, 0x00160004, 0x0 }, 95 { 0x00C30FFF, 0x001E0000, 0x0 }, 96 { 0x00FFFFFF, 0x00060006, 0x0 }, 97 { 0x00D75FFF, 0x001E0000, 0x0 }, 98 }; 99 100 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { 101 /* Idx NT mV d T mV d db */ 102 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */ 103 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */ 104 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */ 105 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */ 106 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */ 107 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */ 108 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */ 109 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */ 110 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */ 111 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */ 112 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */ 113 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */ 114 }; 115 116 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { 117 { 0x00FFFFFF, 0x00000012, 0x0 }, 118 { 0x00EBAFFF, 0x00020011, 0x0 }, 119 { 0x00C71FFF, 0x0006000F, 0x0 }, 120 { 0x00AAAFFF, 0x000E000A, 0x0 }, 121 { 0x00FFFFFF, 0x00020011, 0x0 }, 122 { 0x00DB6FFF, 0x0005000F, 0x0 }, 123 { 0x00BEEFFF, 0x000A000C, 0x0 }, 124 { 0x00FFFFFF, 0x0005000F, 0x0 }, 125 { 0x00DB6FFF, 0x000A000C, 0x0 }, 126 }; 127 128 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { 129 { 0x00FFFFFF, 0x0007000E, 0x0 }, 130 { 0x00D75FFF, 0x000E000A, 0x0 }, 131 { 0x00BEFFFF, 0x00140006, 0x0 }, 132 { 0x80B2CFFF, 0x001B0002, 0x0 }, 133 { 0x00FFFFFF, 0x000E000A, 0x0 }, 134 { 0x00DB6FFF, 0x00160005, 0x0 }, 135 { 0x80C71FFF, 0x001A0002, 0x0 }, 136 { 0x00F7DFFF, 0x00180004, 0x0 }, 137 { 0x80D75FFF, 0x001B0002, 0x0 }, 138 }; 139 140 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { 141 { 0x00FFFFFF, 0x0001000E, 0x0 }, 142 { 0x00D75FFF, 0x0004000A, 0x0 }, 143 { 0x00C30FFF, 0x00070006, 0x0 }, 144 { 0x00AAAFFF, 0x000C0000, 0x0 }, 145 { 0x00FFFFFF, 0x0004000A, 0x0 }, 146 { 0x00D75FFF, 0x00090004, 0x0 }, 147 { 0x00C30FFF, 0x000C0000, 0x0 }, 148 { 0x00FFFFFF, 0x00070006, 0x0 }, 149 { 0x00D75FFF, 0x000C0000, 0x0 }, 150 }; 151 152 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { 153 /* Idx NT mV d T mV df db */ 154 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */ 155 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */ 156 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */ 157 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */ 158 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */ 159 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */ 160 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */ 161 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */ 162 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */ 163 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */ 164 }; 165 166 /* Skylake H and S */ 167 static const struct ddi_buf_trans skl_ddi_translations_dp[] = { 168 { 0x00002016, 0x000000A0, 0x0 }, 169 { 0x00005012, 0x0000009B, 0x0 }, 170 { 0x00007011, 0x00000088, 0x0 }, 171 { 0x80009010, 0x000000C0, 0x1 }, 172 { 0x00002016, 0x0000009B, 0x0 }, 173 { 0x00005012, 0x00000088, 0x0 }, 174 { 0x80007011, 0x000000C0, 0x1 }, 175 { 0x00002016, 0x000000DF, 0x0 }, 176 { 0x80005012, 0x000000C0, 0x1 }, 177 }; 178 179 /* Skylake U */ 180 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { 181 { 0x0000201B, 0x000000A2, 0x0 }, 182 { 0x00005012, 0x00000088, 0x0 }, 183 { 0x80007011, 0x000000CD, 0x1 }, 184 { 0x80009010, 0x000000C0, 0x1 }, 185 { 0x0000201B, 0x0000009D, 0x0 }, 186 { 0x80005012, 0x000000C0, 0x1 }, 187 { 0x80007011, 0x000000C0, 0x1 }, 188 { 0x00002016, 0x00000088, 0x0 }, 189 { 0x80005012, 0x000000C0, 0x1 }, 190 }; 191 192 /* Skylake Y */ 193 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { 194 { 0x00000018, 0x000000A2, 0x0 }, 195 { 0x00005012, 0x00000088, 0x0 }, 196 { 0x80007011, 0x000000CD, 0x3 }, 197 { 0x80009010, 0x000000C0, 0x3 }, 198 { 0x00000018, 0x0000009D, 0x0 }, 199 { 0x80005012, 0x000000C0, 0x3 }, 200 { 0x80007011, 0x000000C0, 0x3 }, 201 { 0x00000018, 0x00000088, 0x0 }, 202 { 0x80005012, 0x000000C0, 0x3 }, 203 }; 204 205 /* Kabylake H and S */ 206 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = { 207 { 0x00002016, 0x000000A0, 0x0 }, 208 { 0x00005012, 0x0000009B, 0x0 }, 209 { 0x00007011, 0x00000088, 0x0 }, 210 { 0x80009010, 0x000000C0, 0x1 }, 211 { 0x00002016, 0x0000009B, 0x0 }, 212 { 0x00005012, 0x00000088, 0x0 }, 213 { 0x80007011, 0x000000C0, 0x1 }, 214 { 0x00002016, 0x00000097, 0x0 }, 215 { 0x80005012, 0x000000C0, 0x1 }, 216 }; 217 218 /* Kabylake U */ 219 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = { 220 { 0x0000201B, 0x000000A1, 0x0 }, 221 { 0x00005012, 0x00000088, 0x0 }, 222 { 0x80007011, 0x000000CD, 0x3 }, 223 { 0x80009010, 0x000000C0, 0x3 }, 224 { 0x0000201B, 0x0000009D, 0x0 }, 225 { 0x80005012, 0x000000C0, 0x3 }, 226 { 0x80007011, 0x000000C0, 0x3 }, 227 { 0x00002016, 0x0000004F, 0x0 }, 228 { 0x80005012, 0x000000C0, 0x3 }, 229 }; 230 231 /* Kabylake Y */ 232 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = { 233 { 0x00001017, 0x000000A1, 0x0 }, 234 { 0x00005012, 0x00000088, 0x0 }, 235 { 0x80007011, 0x000000CD, 0x3 }, 236 { 0x8000800F, 0x000000C0, 0x3 }, 237 { 0x00001017, 0x0000009D, 0x0 }, 238 { 0x80005012, 0x000000C0, 0x3 }, 239 { 0x80007011, 0x000000C0, 0x3 }, 240 { 0x00001017, 0x0000004C, 0x0 }, 241 { 0x80005012, 0x000000C0, 0x3 }, 242 }; 243 244 /* 245 * Skylake/Kabylake H and S 246 * eDP 1.4 low vswing translation parameters 247 */ 248 static const struct ddi_buf_trans skl_ddi_translations_edp[] = { 249 { 0x00000018, 0x000000A8, 0x0 }, 250 { 0x00004013, 0x000000A9, 0x0 }, 251 { 0x00007011, 0x000000A2, 0x0 }, 252 { 0x00009010, 0x0000009C, 0x0 }, 253 { 0x00000018, 0x000000A9, 0x0 }, 254 { 0x00006013, 0x000000A2, 0x0 }, 255 { 0x00007011, 0x000000A6, 0x0 }, 256 { 0x00000018, 0x000000AB, 0x0 }, 257 { 0x00007013, 0x0000009F, 0x0 }, 258 { 0x00000018, 0x000000DF, 0x0 }, 259 }; 260 261 /* 262 * Skylake/Kabylake U 263 * eDP 1.4 low vswing translation parameters 264 */ 265 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = { 266 { 0x00000018, 0x000000A8, 0x0 }, 267 { 0x00004013, 0x000000A9, 0x0 }, 268 { 0x00007011, 0x000000A2, 0x0 }, 269 { 0x00009010, 0x0000009C, 0x0 }, 270 { 0x00000018, 0x000000A9, 0x0 }, 271 { 0x00006013, 0x000000A2, 0x0 }, 272 { 0x00007011, 0x000000A6, 0x0 }, 273 { 0x00002016, 0x000000AB, 0x0 }, 274 { 0x00005013, 0x0000009F, 0x0 }, 275 { 0x00000018, 0x000000DF, 0x0 }, 276 }; 277 278 /* 279 * Skylake/Kabylake Y 280 * eDP 1.4 low vswing translation parameters 281 */ 282 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = { 283 { 0x00000018, 0x000000A8, 0x0 }, 284 { 0x00004013, 0x000000AB, 0x0 }, 285 { 0x00007011, 0x000000A4, 0x0 }, 286 { 0x00009010, 0x000000DF, 0x0 }, 287 { 0x00000018, 0x000000AA, 0x0 }, 288 { 0x00006013, 0x000000A4, 0x0 }, 289 { 0x00007011, 0x0000009D, 0x0 }, 290 { 0x00000018, 0x000000A0, 0x0 }, 291 { 0x00006012, 0x000000DF, 0x0 }, 292 { 0x00000018, 0x0000008A, 0x0 }, 293 }; 294 295 /* Skylake/Kabylake U, H and S */ 296 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { 297 { 0x00000018, 0x000000AC, 0x0 }, 298 { 0x00005012, 0x0000009D, 0x0 }, 299 { 0x00007011, 0x00000088, 0x0 }, 300 { 0x00000018, 0x000000A1, 0x0 }, 301 { 0x00000018, 0x00000098, 0x0 }, 302 { 0x00004013, 0x00000088, 0x0 }, 303 { 0x80006012, 0x000000CD, 0x1 }, 304 { 0x00000018, 0x000000DF, 0x0 }, 305 { 0x80003015, 0x000000CD, 0x1 }, /* Default */ 306 { 0x80003015, 0x000000C0, 0x1 }, 307 { 0x80000018, 0x000000C0, 0x1 }, 308 }; 309 310 /* Skylake/Kabylake Y */ 311 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { 312 { 0x00000018, 0x000000A1, 0x0 }, 313 { 0x00005012, 0x000000DF, 0x0 }, 314 { 0x80007011, 0x000000CB, 0x3 }, 315 { 0x00000018, 0x000000A4, 0x0 }, 316 { 0x00000018, 0x0000009D, 0x0 }, 317 { 0x00004013, 0x00000080, 0x0 }, 318 { 0x80006013, 0x000000C0, 0x3 }, 319 { 0x00000018, 0x0000008A, 0x0 }, 320 { 0x80003015, 0x000000C0, 0x3 }, /* Default */ 321 { 0x80003015, 0x000000C0, 0x3 }, 322 { 0x80000018, 0x000000C0, 0x3 }, 323 }; 324 325 struct bxt_ddi_buf_trans { 326 u8 margin; /* swing value */ 327 u8 scale; /* scale value */ 328 u8 enable; /* scale enable */ 329 u8 deemphasis; 330 }; 331 332 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { 333 /* Idx NT mV diff db */ 334 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ 335 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */ 336 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */ 337 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */ 338 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */ 339 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */ 340 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */ 341 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */ 342 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */ 343 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */ 344 }; 345 346 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = { 347 /* Idx NT mV diff db */ 348 { 26, 0, 0, 128, }, /* 0: 200 0 */ 349 { 38, 0, 0, 112, }, /* 1: 200 1.5 */ 350 { 48, 0, 0, 96, }, /* 2: 200 4 */ 351 { 54, 0, 0, 69, }, /* 3: 200 6 */ 352 { 32, 0, 0, 128, }, /* 4: 250 0 */ 353 { 48, 0, 0, 104, }, /* 5: 250 1.5 */ 354 { 54, 0, 0, 85, }, /* 6: 250 4 */ 355 { 43, 0, 0, 128, }, /* 7: 300 0 */ 356 { 54, 0, 0, 101, }, /* 8: 300 1.5 */ 357 { 48, 0, 0, 128, }, /* 9: 300 0 */ 358 }; 359 360 /* BSpec has 2 recommended values - entries 0 and 8. 361 * Using the entry with higher vswing. 362 */ 363 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = { 364 /* Idx NT mV diff db */ 365 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ 366 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */ 367 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */ 368 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */ 369 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */ 370 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */ 371 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */ 372 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */ 373 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */ 374 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */ 375 }; 376 377 struct cnl_ddi_buf_trans { 378 u8 dw2_swing_sel; 379 u8 dw7_n_scalar; 380 u8 dw4_cursor_coeff; 381 u8 dw4_post_cursor_2; 382 u8 dw4_post_cursor_1; 383 }; 384 385 /* Voltage Swing Programming for VccIO 0.85V for DP */ 386 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = { 387 /* NT mV Trans mV db */ 388 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 389 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ 390 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ 391 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ 392 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 393 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 394 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 395 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ 396 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ 397 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 398 }; 399 400 /* Voltage Swing Programming for VccIO 0.85V for HDMI */ 401 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = { 402 /* NT mV Trans mV db */ 403 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 404 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ 405 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ 406 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */ 407 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ 408 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ 409 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 410 }; 411 412 /* Voltage Swing Programming for VccIO 0.85V for eDP */ 413 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = { 414 /* NT mV Trans mV db */ 415 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 416 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 417 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 418 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 419 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 420 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 421 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */ 422 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */ 423 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 424 }; 425 426 /* Voltage Swing Programming for VccIO 0.95V for DP */ 427 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = { 428 /* NT mV Trans mV db */ 429 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 430 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ 431 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ 432 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ 433 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 434 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 435 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 436 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ 437 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ 438 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 439 }; 440 441 /* Voltage Swing Programming for VccIO 0.95V for HDMI */ 442 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = { 443 /* NT mV Trans mV db */ 444 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 445 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 446 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 447 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 448 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 449 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 450 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ 451 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ 452 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ 453 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ 454 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 455 }; 456 457 /* Voltage Swing Programming for VccIO 0.95V for eDP */ 458 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = { 459 /* NT mV Trans mV db */ 460 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 461 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 462 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 463 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 464 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 465 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 466 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ 467 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ 468 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */ 469 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 470 }; 471 472 /* Voltage Swing Programming for VccIO 1.05V for DP */ 473 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = { 474 /* NT mV Trans mV db */ 475 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 476 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 477 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 478 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */ 479 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 480 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 481 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */ 482 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */ 483 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */ 484 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 485 }; 486 487 /* Voltage Swing Programming for VccIO 1.05V for HDMI */ 488 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = { 489 /* NT mV Trans mV db */ 490 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 491 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 492 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 493 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 494 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 495 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 496 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ 497 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ 498 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ 499 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ 500 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 501 }; 502 503 /* Voltage Swing Programming for VccIO 1.05V for eDP */ 504 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = { 505 /* NT mV Trans mV db */ 506 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 507 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 508 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 509 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 510 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 511 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 512 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ 513 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ 514 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 515 }; 516 517 /* icl_combo_phy_ddi_translations */ 518 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = { 519 /* NT mV Trans mV db */ 520 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 521 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 522 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 523 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 524 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 525 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 526 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 527 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 528 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 529 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 530 }; 531 532 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = { 533 /* NT mV Trans mV db */ 534 { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ 535 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */ 536 { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */ 537 { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */ 538 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ 539 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */ 540 { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */ 541 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ 542 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ 543 { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 544 }; 545 546 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = { 547 /* NT mV Trans mV db */ 548 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 549 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 550 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 551 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 552 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 553 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 554 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 555 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 556 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 557 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 558 }; 559 560 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = { 561 /* NT mV Trans mV db */ 562 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 563 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ 564 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ 565 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */ 566 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ 567 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ 568 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 569 }; 570 571 static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = { 572 /* NT mV Trans mV db */ 573 { 0xA, 0x33, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 574 { 0xA, 0x47, 0x36, 0x00, 0x09 }, /* 350 500 3.1 */ 575 { 0xC, 0x64, 0x30, 0x00, 0x0F }, /* 350 700 6.0 */ 576 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 350 900 8.2 */ 577 { 0xA, 0x46, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 578 { 0xC, 0x64, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 579 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 580 { 0xC, 0x61, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */ 581 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 600 900 3.5 */ 582 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 583 }; 584 585 struct icl_mg_phy_ddi_buf_trans { 586 u32 cri_txdeemph_override_11_6; 587 u32 cri_txdeemph_override_5_0; 588 u32 cri_txdeemph_override_17_12; 589 }; 590 591 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_rbr_hbr[] = { 592 /* Voltage swing pre-emphasis */ 593 { 0x18, 0x00, 0x00 }, /* 0 0 */ 594 { 0x1D, 0x00, 0x05 }, /* 0 1 */ 595 { 0x24, 0x00, 0x0C }, /* 0 2 */ 596 { 0x2B, 0x00, 0x14 }, /* 0 3 */ 597 { 0x21, 0x00, 0x00 }, /* 1 0 */ 598 { 0x2B, 0x00, 0x08 }, /* 1 1 */ 599 { 0x30, 0x00, 0x0F }, /* 1 2 */ 600 { 0x31, 0x00, 0x03 }, /* 2 0 */ 601 { 0x34, 0x00, 0x0B }, /* 2 1 */ 602 { 0x3F, 0x00, 0x00 }, /* 3 0 */ 603 }; 604 605 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hbr2_hbr3[] = { 606 /* Voltage swing pre-emphasis */ 607 { 0x18, 0x00, 0x00 }, /* 0 0 */ 608 { 0x1D, 0x00, 0x05 }, /* 0 1 */ 609 { 0x24, 0x00, 0x0C }, /* 0 2 */ 610 { 0x2B, 0x00, 0x14 }, /* 0 3 */ 611 { 0x26, 0x00, 0x00 }, /* 1 0 */ 612 { 0x2C, 0x00, 0x07 }, /* 1 1 */ 613 { 0x33, 0x00, 0x0C }, /* 1 2 */ 614 { 0x2E, 0x00, 0x00 }, /* 2 0 */ 615 { 0x36, 0x00, 0x09 }, /* 2 1 */ 616 { 0x3F, 0x00, 0x00 }, /* 3 0 */ 617 }; 618 619 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hdmi[] = { 620 /* HDMI Preset VS Pre-emph */ 621 { 0x1A, 0x0, 0x0 }, /* 1 400mV 0dB */ 622 { 0x20, 0x0, 0x0 }, /* 2 500mV 0dB */ 623 { 0x29, 0x0, 0x0 }, /* 3 650mV 0dB */ 624 { 0x32, 0x0, 0x0 }, /* 4 800mV 0dB */ 625 { 0x3F, 0x0, 0x0 }, /* 5 1000mV 0dB */ 626 { 0x3A, 0x0, 0x5 }, /* 6 Full -1.5 dB */ 627 { 0x39, 0x0, 0x6 }, /* 7 Full -1.8 dB */ 628 { 0x38, 0x0, 0x7 }, /* 8 Full -2 dB */ 629 { 0x37, 0x0, 0x8 }, /* 9 Full -2.5 dB */ 630 { 0x36, 0x0, 0x9 }, /* 10 Full -3 dB */ 631 }; 632 633 struct tgl_dkl_phy_ddi_buf_trans { 634 u32 dkl_vswing_control; 635 u32 dkl_preshoot_control; 636 u32 dkl_de_emphasis_control; 637 }; 638 639 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans[] = { 640 /* VS pre-emp Non-trans mV Pre-emph dB */ 641 { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */ 642 { 0x5, 0x0, 0x05 }, /* 0 1 400mV 3.5 dB */ 643 { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB */ 644 { 0x0, 0x0, 0x18 }, /* 0 3 400mV 9.5 dB */ 645 { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */ 646 { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 dB */ 647 { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */ 648 { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */ 649 { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */ 650 { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */ 651 }; 652 653 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans_hbr2[] = { 654 /* VS pre-emp Non-trans mV Pre-emph dB */ 655 { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */ 656 { 0x5, 0x0, 0x05 }, /* 0 1 400mV 3.5 dB */ 657 { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB */ 658 { 0x0, 0x0, 0x19 }, /* 0 3 400mV 9.5 dB */ 659 { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */ 660 { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 dB */ 661 { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */ 662 { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */ 663 { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */ 664 { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */ 665 }; 666 667 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_hdmi_ddi_trans[] = { 668 /* HDMI Preset VS Pre-emph */ 669 { 0x7, 0x0, 0x0 }, /* 1 400mV 0dB */ 670 { 0x6, 0x0, 0x0 }, /* 2 500mV 0dB */ 671 { 0x4, 0x0, 0x0 }, /* 3 650mV 0dB */ 672 { 0x2, 0x0, 0x0 }, /* 4 800mV 0dB */ 673 { 0x0, 0x0, 0x0 }, /* 5 1000mV 0dB */ 674 { 0x0, 0x0, 0x5 }, /* 6 Full -1.5 dB */ 675 { 0x0, 0x0, 0x6 }, /* 7 Full -1.8 dB */ 676 { 0x0, 0x0, 0x7 }, /* 8 Full -2 dB */ 677 { 0x0, 0x0, 0x8 }, /* 9 Full -2.5 dB */ 678 { 0x0, 0x0, 0xA }, /* 10 Full -3 dB */ 679 }; 680 681 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr[] = { 682 /* NT mV Trans mV db */ 683 { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 684 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 685 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 686 { 0x6, 0x7D, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 687 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 688 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 689 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 690 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 691 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 692 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 693 }; 694 695 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = { 696 /* NT mV Trans mV db */ 697 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 698 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 699 { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 700 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 701 { 0xA, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 702 { 0xC, 0x63, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 703 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 704 { 0xC, 0x61, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 705 { 0x6, 0x7B, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 706 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 707 }; 708 709 static const struct ddi_buf_trans * 710 bdw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) 711 { 712 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 713 714 if (dev_priv->vbt.edp.low_vswing) { 715 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp); 716 return bdw_ddi_translations_edp; 717 } else { 718 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 719 return bdw_ddi_translations_dp; 720 } 721 } 722 723 static const struct ddi_buf_trans * 724 skl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) 725 { 726 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 727 728 if (IS_SKL_ULX(dev_priv)) { 729 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); 730 return skl_y_ddi_translations_dp; 731 } else if (IS_SKL_ULT(dev_priv)) { 732 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); 733 return skl_u_ddi_translations_dp; 734 } else { 735 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); 736 return skl_ddi_translations_dp; 737 } 738 } 739 740 static const struct ddi_buf_trans * 741 kbl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) 742 { 743 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 744 745 if (IS_KBL_ULX(dev_priv) || 746 IS_CFL_ULX(dev_priv) || 747 IS_CML_ULX(dev_priv)) { 748 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp); 749 return kbl_y_ddi_translations_dp; 750 } else if (IS_KBL_ULT(dev_priv) || 751 IS_CFL_ULT(dev_priv) || 752 IS_CML_ULT(dev_priv)) { 753 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp); 754 return kbl_u_ddi_translations_dp; 755 } else { 756 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp); 757 return kbl_ddi_translations_dp; 758 } 759 } 760 761 static const struct ddi_buf_trans * 762 skl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) 763 { 764 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 765 766 if (dev_priv->vbt.edp.low_vswing) { 767 if (IS_SKL_ULX(dev_priv) || 768 IS_KBL_ULX(dev_priv) || 769 IS_CFL_ULX(dev_priv) || 770 IS_CML_ULX(dev_priv)) { 771 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); 772 return skl_y_ddi_translations_edp; 773 } else if (IS_SKL_ULT(dev_priv) || 774 IS_KBL_ULT(dev_priv) || 775 IS_CFL_ULT(dev_priv) || 776 IS_CML_ULT(dev_priv)) { 777 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); 778 return skl_u_ddi_translations_edp; 779 } else { 780 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp); 781 return skl_ddi_translations_edp; 782 } 783 } 784 785 if (IS_KABYLAKE(dev_priv) || 786 IS_COFFEELAKE(dev_priv) || 787 IS_COMETLAKE(dev_priv)) 788 return kbl_get_buf_trans_dp(encoder, n_entries); 789 else 790 return skl_get_buf_trans_dp(encoder, n_entries); 791 } 792 793 static const struct ddi_buf_trans * 794 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) 795 { 796 if (IS_SKL_ULX(dev_priv) || 797 IS_KBL_ULX(dev_priv) || 798 IS_CFL_ULX(dev_priv) || 799 IS_CML_ULX(dev_priv)) { 800 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); 801 return skl_y_ddi_translations_hdmi; 802 } else { 803 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); 804 return skl_ddi_translations_hdmi; 805 } 806 } 807 808 static int skl_buf_trans_num_entries(enum port port, int n_entries) 809 { 810 /* Only DDIA and DDIE can select the 10th register with DP */ 811 if (port == PORT_A || port == PORT_E) 812 return min(n_entries, 10); 813 else 814 return min(n_entries, 9); 815 } 816 817 static const struct ddi_buf_trans * 818 intel_ddi_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) 819 { 820 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 821 822 if (IS_KABYLAKE(dev_priv) || 823 IS_COFFEELAKE(dev_priv) || 824 IS_COMETLAKE(dev_priv)) { 825 const struct ddi_buf_trans *ddi_translations = 826 kbl_get_buf_trans_dp(encoder, n_entries); 827 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); 828 return ddi_translations; 829 } else if (IS_SKYLAKE(dev_priv)) { 830 const struct ddi_buf_trans *ddi_translations = 831 skl_get_buf_trans_dp(encoder, n_entries); 832 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); 833 return ddi_translations; 834 } else if (IS_BROADWELL(dev_priv)) { 835 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 836 return bdw_ddi_translations_dp; 837 } else if (IS_HASWELL(dev_priv)) { 838 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 839 return hsw_ddi_translations_dp; 840 } 841 842 *n_entries = 0; 843 return NULL; 844 } 845 846 static const struct ddi_buf_trans * 847 intel_ddi_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) 848 { 849 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 850 851 if (IS_GEN9_BC(dev_priv)) { 852 const struct ddi_buf_trans *ddi_translations = 853 skl_get_buf_trans_edp(encoder, n_entries); 854 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); 855 return ddi_translations; 856 } else if (IS_BROADWELL(dev_priv)) { 857 return bdw_get_buf_trans_edp(encoder, n_entries); 858 } else if (IS_HASWELL(dev_priv)) { 859 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 860 return hsw_ddi_translations_dp; 861 } 862 863 *n_entries = 0; 864 return NULL; 865 } 866 867 static const struct ddi_buf_trans * 868 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, 869 int *n_entries) 870 { 871 if (IS_BROADWELL(dev_priv)) { 872 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi); 873 return bdw_ddi_translations_fdi; 874 } else if (IS_HASWELL(dev_priv)) { 875 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi); 876 return hsw_ddi_translations_fdi; 877 } 878 879 *n_entries = 0; 880 return NULL; 881 } 882 883 static const struct ddi_buf_trans * 884 intel_ddi_get_buf_trans_hdmi(struct intel_encoder *encoder, 885 int *n_entries) 886 { 887 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 888 889 if (IS_GEN9_BC(dev_priv)) { 890 return skl_get_buf_trans_hdmi(dev_priv, n_entries); 891 } else if (IS_BROADWELL(dev_priv)) { 892 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 893 return bdw_ddi_translations_hdmi; 894 } else if (IS_HASWELL(dev_priv)) { 895 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); 896 return hsw_ddi_translations_hdmi; 897 } 898 899 *n_entries = 0; 900 return NULL; 901 } 902 903 static const struct bxt_ddi_buf_trans * 904 bxt_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) 905 { 906 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); 907 return bxt_ddi_translations_dp; 908 } 909 910 static const struct bxt_ddi_buf_trans * 911 bxt_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) 912 { 913 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 914 915 if (dev_priv->vbt.edp.low_vswing) { 916 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp); 917 return bxt_ddi_translations_edp; 918 } 919 920 return bxt_get_buf_trans_dp(encoder, n_entries); 921 } 922 923 static const struct bxt_ddi_buf_trans * 924 bxt_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries) 925 { 926 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); 927 return bxt_ddi_translations_hdmi; 928 } 929 930 static const struct cnl_ddi_buf_trans * 931 cnl_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries) 932 { 933 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 934 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 935 936 if (voltage == VOLTAGE_INFO_0_85V) { 937 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V); 938 return cnl_ddi_translations_hdmi_0_85V; 939 } else if (voltage == VOLTAGE_INFO_0_95V) { 940 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V); 941 return cnl_ddi_translations_hdmi_0_95V; 942 } else if (voltage == VOLTAGE_INFO_1_05V) { 943 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V); 944 return cnl_ddi_translations_hdmi_1_05V; 945 } else { 946 *n_entries = 1; /* shut up gcc */ 947 MISSING_CASE(voltage); 948 } 949 return NULL; 950 } 951 952 static const struct cnl_ddi_buf_trans * 953 cnl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) 954 { 955 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 956 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 957 958 if (voltage == VOLTAGE_INFO_0_85V) { 959 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V); 960 return cnl_ddi_translations_dp_0_85V; 961 } else if (voltage == VOLTAGE_INFO_0_95V) { 962 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V); 963 return cnl_ddi_translations_dp_0_95V; 964 } else if (voltage == VOLTAGE_INFO_1_05V) { 965 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V); 966 return cnl_ddi_translations_dp_1_05V; 967 } else { 968 *n_entries = 1; /* shut up gcc */ 969 MISSING_CASE(voltage); 970 } 971 return NULL; 972 } 973 974 static const struct cnl_ddi_buf_trans * 975 cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) 976 { 977 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 978 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 979 980 if (dev_priv->vbt.edp.low_vswing) { 981 if (voltage == VOLTAGE_INFO_0_85V) { 982 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V); 983 return cnl_ddi_translations_edp_0_85V; 984 } else if (voltage == VOLTAGE_INFO_0_95V) { 985 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V); 986 return cnl_ddi_translations_edp_0_95V; 987 } else if (voltage == VOLTAGE_INFO_1_05V) { 988 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V); 989 return cnl_ddi_translations_edp_1_05V; 990 } else { 991 *n_entries = 1; /* shut up gcc */ 992 MISSING_CASE(voltage); 993 } 994 return NULL; 995 } else { 996 return cnl_get_buf_trans_dp(encoder, n_entries); 997 } 998 } 999 1000 static const struct cnl_ddi_buf_trans * 1001 icl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate, 1002 int *n_entries) 1003 { 1004 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1005 1006 if (type == INTEL_OUTPUT_HDMI) { 1007 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); 1008 return icl_combo_phy_ddi_translations_hdmi; 1009 } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) { 1010 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3); 1011 return icl_combo_phy_ddi_translations_edp_hbr3; 1012 } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) { 1013 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2); 1014 return icl_combo_phy_ddi_translations_edp_hbr2; 1015 } 1016 1017 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2); 1018 return icl_combo_phy_ddi_translations_dp_hbr2; 1019 } 1020 1021 static const struct icl_mg_phy_ddi_buf_trans * 1022 icl_get_mg_buf_trans(struct intel_encoder *encoder, int type, int rate, 1023 int *n_entries) 1024 { 1025 if (type == INTEL_OUTPUT_HDMI) { 1026 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hdmi); 1027 return icl_mg_phy_ddi_translations_hdmi; 1028 } else if (rate > 270000) { 1029 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hbr2_hbr3); 1030 return icl_mg_phy_ddi_translations_hbr2_hbr3; 1031 } 1032 1033 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr); 1034 return icl_mg_phy_ddi_translations_rbr_hbr; 1035 } 1036 1037 static const struct cnl_ddi_buf_trans * 1038 ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate, 1039 int *n_entries) 1040 { 1041 if (type != INTEL_OUTPUT_HDMI && type != INTEL_OUTPUT_EDP) { 1042 *n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_dp); 1043 return ehl_combo_phy_ddi_translations_dp; 1044 } 1045 1046 return icl_get_combo_buf_trans(encoder, type, rate, n_entries); 1047 } 1048 1049 static const struct cnl_ddi_buf_trans * 1050 tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate, 1051 int *n_entries) 1052 { 1053 if (type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_EDP) { 1054 return icl_get_combo_buf_trans(encoder, type, rate, n_entries); 1055 } else if (rate > 270000) { 1056 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2); 1057 return tgl_combo_phy_ddi_translations_dp_hbr2; 1058 } 1059 1060 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr); 1061 return tgl_combo_phy_ddi_translations_dp_hbr; 1062 } 1063 1064 static const struct tgl_dkl_phy_ddi_buf_trans * 1065 tgl_get_dkl_buf_trans(struct intel_encoder *encoder, int type, int rate, 1066 int *n_entries) 1067 { 1068 if (type == INTEL_OUTPUT_HDMI) { 1069 *n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans); 1070 return tgl_dkl_phy_hdmi_ddi_trans; 1071 } else if (rate > 270000) { 1072 *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans_hbr2); 1073 return tgl_dkl_phy_dp_ddi_trans_hbr2; 1074 } 1075 1076 *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans); 1077 return tgl_dkl_phy_dp_ddi_trans; 1078 } 1079 1080 static int intel_ddi_hdmi_level(struct intel_encoder *encoder) 1081 { 1082 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1083 int n_entries, level, default_entry; 1084 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1085 1086 if (INTEL_GEN(dev_priv) >= 12) { 1087 if (intel_phy_is_combo(dev_priv, phy)) 1088 tgl_get_combo_buf_trans(encoder, INTEL_OUTPUT_HDMI, 1089 0, &n_entries); 1090 else 1091 tgl_get_dkl_buf_trans(encoder, INTEL_OUTPUT_HDMI, 0, 1092 &n_entries); 1093 default_entry = n_entries - 1; 1094 } else if (INTEL_GEN(dev_priv) == 11) { 1095 if (intel_phy_is_combo(dev_priv, phy)) 1096 icl_get_combo_buf_trans(encoder, INTEL_OUTPUT_HDMI, 1097 0, &n_entries); 1098 else 1099 icl_get_mg_buf_trans(encoder, INTEL_OUTPUT_HDMI, 0, 1100 &n_entries); 1101 default_entry = n_entries - 1; 1102 } else if (IS_CANNONLAKE(dev_priv)) { 1103 cnl_get_buf_trans_hdmi(encoder, &n_entries); 1104 default_entry = n_entries - 1; 1105 } else if (IS_GEN9_LP(dev_priv)) { 1106 bxt_get_buf_trans_hdmi(encoder, &n_entries); 1107 default_entry = n_entries - 1; 1108 } else if (IS_GEN9_BC(dev_priv)) { 1109 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); 1110 default_entry = 8; 1111 } else if (IS_BROADWELL(dev_priv)) { 1112 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); 1113 default_entry = 7; 1114 } else if (IS_HASWELL(dev_priv)) { 1115 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); 1116 default_entry = 6; 1117 } else { 1118 drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n"); 1119 return 0; 1120 } 1121 1122 if (drm_WARN_ON_ONCE(&dev_priv->drm, n_entries == 0)) 1123 return 0; 1124 1125 level = intel_bios_hdmi_level_shift(encoder); 1126 if (level < 0) 1127 level = default_entry; 1128 1129 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 1130 level = n_entries - 1; 1131 1132 return level; 1133 } 1134 1135 /* 1136 * Starting with Haswell, DDI port buffers must be programmed with correct 1137 * values in advance. This function programs the correct values for 1138 * DP/eDP/FDI use cases. 1139 */ 1140 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 1141 const struct intel_crtc_state *crtc_state) 1142 { 1143 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1144 u32 iboost_bit = 0; 1145 int i, n_entries; 1146 enum port port = encoder->port; 1147 const struct ddi_buf_trans *ddi_translations; 1148 1149 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) 1150 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv, 1151 &n_entries); 1152 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1153 ddi_translations = intel_ddi_get_buf_trans_edp(encoder, 1154 &n_entries); 1155 else 1156 ddi_translations = intel_ddi_get_buf_trans_dp(encoder, 1157 &n_entries); 1158 1159 /* If we're boosting the current, set bit 31 of trans1 */ 1160 if (IS_GEN9_BC(dev_priv) && intel_bios_dp_boost_level(encoder)) 1161 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 1162 1163 for (i = 0; i < n_entries; i++) { 1164 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 1165 ddi_translations[i].trans1 | iboost_bit); 1166 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 1167 ddi_translations[i].trans2); 1168 } 1169 } 1170 1171 /* 1172 * Starting with Haswell, DDI port buffers must be programmed with correct 1173 * values in advance. This function programs the correct values for 1174 * HDMI/DVI use cases. 1175 */ 1176 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 1177 int level) 1178 { 1179 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1180 u32 iboost_bit = 0; 1181 int n_entries; 1182 enum port port = encoder->port; 1183 const struct ddi_buf_trans *ddi_translations; 1184 1185 ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); 1186 1187 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 1188 return; 1189 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 1190 level = n_entries - 1; 1191 1192 /* If we're boosting the current, set bit 31 of trans1 */ 1193 if (IS_GEN9_BC(dev_priv) && intel_bios_hdmi_boost_level(encoder)) 1194 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 1195 1196 /* Entry 9 is for HDMI: */ 1197 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 1198 ddi_translations[level].trans1 | iboost_bit); 1199 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 1200 ddi_translations[level].trans2); 1201 } 1202 1203 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 1204 enum port port) 1205 { 1206 if (IS_BROXTON(dev_priv)) { 1207 udelay(16); 1208 return; 1209 } 1210 1211 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 1212 DDI_BUF_IS_IDLE), 8)) 1213 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", 1214 port_name(port)); 1215 } 1216 1217 static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, 1218 enum port port) 1219 { 1220 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ 1221 if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) { 1222 usleep_range(518, 1000); 1223 return; 1224 } 1225 1226 if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 1227 DDI_BUF_IS_IDLE), 500)) 1228 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", 1229 port_name(port)); 1230 } 1231 1232 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 1233 { 1234 switch (pll->info->id) { 1235 case DPLL_ID_WRPLL1: 1236 return PORT_CLK_SEL_WRPLL1; 1237 case DPLL_ID_WRPLL2: 1238 return PORT_CLK_SEL_WRPLL2; 1239 case DPLL_ID_SPLL: 1240 return PORT_CLK_SEL_SPLL; 1241 case DPLL_ID_LCPLL_810: 1242 return PORT_CLK_SEL_LCPLL_810; 1243 case DPLL_ID_LCPLL_1350: 1244 return PORT_CLK_SEL_LCPLL_1350; 1245 case DPLL_ID_LCPLL_2700: 1246 return PORT_CLK_SEL_LCPLL_2700; 1247 default: 1248 MISSING_CASE(pll->info->id); 1249 return PORT_CLK_SEL_NONE; 1250 } 1251 } 1252 1253 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 1254 const struct intel_crtc_state *crtc_state) 1255 { 1256 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1257 int clock = crtc_state->port_clock; 1258 const enum intel_dpll_id id = pll->info->id; 1259 1260 switch (id) { 1261 default: 1262 /* 1263 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 1264 * here, so do warn if this get passed in 1265 */ 1266 MISSING_CASE(id); 1267 return DDI_CLK_SEL_NONE; 1268 case DPLL_ID_ICL_TBTPLL: 1269 switch (clock) { 1270 case 162000: 1271 return DDI_CLK_SEL_TBT_162; 1272 case 270000: 1273 return DDI_CLK_SEL_TBT_270; 1274 case 540000: 1275 return DDI_CLK_SEL_TBT_540; 1276 case 810000: 1277 return DDI_CLK_SEL_TBT_810; 1278 default: 1279 MISSING_CASE(clock); 1280 return DDI_CLK_SEL_NONE; 1281 } 1282 case DPLL_ID_ICL_MGPLL1: 1283 case DPLL_ID_ICL_MGPLL2: 1284 case DPLL_ID_ICL_MGPLL3: 1285 case DPLL_ID_ICL_MGPLL4: 1286 case DPLL_ID_TGL_MGPLL5: 1287 case DPLL_ID_TGL_MGPLL6: 1288 return DDI_CLK_SEL_MG; 1289 } 1290 } 1291 1292 /* Starting with Haswell, different DDI ports can work in FDI mode for 1293 * connection to the PCH-located connectors. For this, it is necessary to train 1294 * both the DDI port and PCH receiver for the desired DDI buffer settings. 1295 * 1296 * The recommended port to work in FDI mode is DDI E, which we use here. Also, 1297 * please note that when FDI mode is active on DDI E, it shares 2 lines with 1298 * DDI A (which is used for eDP) 1299 */ 1300 1301 void hsw_fdi_link_train(struct intel_encoder *encoder, 1302 const struct intel_crtc_state *crtc_state) 1303 { 1304 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1305 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1306 u32 temp, i, rx_ctl_val, ddi_pll_sel; 1307 1308 intel_prepare_dp_ddi_buffers(encoder, crtc_state); 1309 1310 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the 1311 * mode set "sequence for CRT port" document: 1312 * - TP1 to TP2 time with the default value 1313 * - FDI delay to 90h 1314 * 1315 * WaFDIAutoLinkSetTimingOverrride:hsw 1316 */ 1317 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), 1318 FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 1319 1320 /* Enable the PCH Receiver FDI PLL */ 1321 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | 1322 FDI_RX_PLL_ENABLE | 1323 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); 1324 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 1325 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); 1326 udelay(220); 1327 1328 /* Switch from Rawclk to PCDclk */ 1329 rx_ctl_val |= FDI_PCDCLK; 1330 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 1331 1332 /* Configure Port Clock Select */ 1333 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll); 1334 intel_de_write(dev_priv, PORT_CLK_SEL(PORT_E), ddi_pll_sel); 1335 drm_WARN_ON(&dev_priv->drm, ddi_pll_sel != PORT_CLK_SEL_SPLL); 1336 1337 /* Start the training iterating through available voltages and emphasis, 1338 * testing each value twice. */ 1339 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { 1340 /* Configure DP_TP_CTL with auto-training */ 1341 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), 1342 DP_TP_CTL_FDI_AUTOTRAIN | 1343 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 1344 DP_TP_CTL_LINK_TRAIN_PAT1 | 1345 DP_TP_CTL_ENABLE); 1346 1347 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. 1348 * DDI E does not support port reversal, the functionality is 1349 * achieved on the PCH side in FDI_RX_CTL, so no need to set the 1350 * port reversal bit */ 1351 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), 1352 DDI_BUF_CTL_ENABLE | ((crtc_state->fdi_lanes - 1) << 1) | DDI_BUF_TRANS_SELECT(i / 2)); 1353 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E)); 1354 1355 udelay(600); 1356 1357 /* Program PCH FDI Receiver TU */ 1358 intel_de_write(dev_priv, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); 1359 1360 /* Enable PCH FDI Receiver with auto-training */ 1361 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; 1362 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 1363 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); 1364 1365 /* Wait for FDI receiver lane calibration */ 1366 udelay(30); 1367 1368 /* Unset FDI_RX_MISC pwrdn lanes */ 1369 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1370 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 1371 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp); 1372 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1373 1374 /* Wait for FDI auto training time */ 1375 udelay(5); 1376 1377 temp = intel_de_read(dev_priv, DP_TP_STATUS(PORT_E)); 1378 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { 1379 drm_dbg_kms(&dev_priv->drm, 1380 "FDI link training done on step %d\n", i); 1381 break; 1382 } 1383 1384 /* 1385 * Leave things enabled even if we failed to train FDI. 1386 * Results in less fireworks from the state checker. 1387 */ 1388 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) { 1389 drm_err(&dev_priv->drm, "FDI link training failed!\n"); 1390 break; 1391 } 1392 1393 rx_ctl_val &= ~FDI_RX_ENABLE; 1394 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 1395 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); 1396 1397 temp = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E)); 1398 temp &= ~DDI_BUF_CTL_ENABLE; 1399 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), temp); 1400 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E)); 1401 1402 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ 1403 temp = intel_de_read(dev_priv, DP_TP_CTL(PORT_E)); 1404 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 1405 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 1406 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp); 1407 intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E)); 1408 1409 intel_wait_ddi_buf_idle(dev_priv, PORT_E); 1410 1411 /* Reset FDI_RX_MISC pwrdn lanes */ 1412 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1413 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 1414 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 1415 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp); 1416 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1417 } 1418 1419 /* Enable normal pixel sending for FDI */ 1420 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), 1421 DP_TP_CTL_FDI_AUTOTRAIN | 1422 DP_TP_CTL_LINK_TRAIN_NORMAL | 1423 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 1424 DP_TP_CTL_ENABLE); 1425 } 1426 1427 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) 1428 { 1429 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1430 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1431 1432 intel_dp->DP = dig_port->saved_port_bits | 1433 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); 1434 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); 1435 } 1436 1437 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 1438 enum port port) 1439 { 1440 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 1441 1442 switch (val) { 1443 case DDI_CLK_SEL_NONE: 1444 return 0; 1445 case DDI_CLK_SEL_TBT_162: 1446 return 162000; 1447 case DDI_CLK_SEL_TBT_270: 1448 return 270000; 1449 case DDI_CLK_SEL_TBT_540: 1450 return 540000; 1451 case DDI_CLK_SEL_TBT_810: 1452 return 810000; 1453 default: 1454 MISSING_CASE(val); 1455 return 0; 1456 } 1457 } 1458 1459 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 1460 { 1461 int dotclock; 1462 1463 if (pipe_config->has_pch_encoder) 1464 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1465 &pipe_config->fdi_m_n); 1466 else if (intel_crtc_has_dp_encoder(pipe_config)) 1467 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1468 &pipe_config->dp_m_n); 1469 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) 1470 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp; 1471 else 1472 dotclock = pipe_config->port_clock; 1473 1474 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 1475 !intel_crtc_has_dp_encoder(pipe_config)) 1476 dotclock *= 2; 1477 1478 if (pipe_config->pixel_multiplier) 1479 dotclock /= pipe_config->pixel_multiplier; 1480 1481 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 1482 } 1483 1484 static void intel_ddi_clock_get(struct intel_encoder *encoder, 1485 struct intel_crtc_state *pipe_config) 1486 { 1487 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1488 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1489 1490 if (intel_phy_is_tc(dev_priv, phy) && 1491 intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll) == 1492 DPLL_ID_ICL_TBTPLL) 1493 pipe_config->port_clock = icl_calc_tbt_pll_link(dev_priv, 1494 encoder->port); 1495 else 1496 pipe_config->port_clock = 1497 intel_dpll_get_freq(dev_priv, pipe_config->shared_dpll); 1498 1499 ddi_dotclock_get(pipe_config); 1500 } 1501 1502 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 1503 const struct drm_connector_state *conn_state) 1504 { 1505 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1506 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1507 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1508 u32 temp; 1509 1510 if (!intel_crtc_has_dp_encoder(crtc_state)) 1511 return; 1512 1513 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 1514 1515 temp = DP_MSA_MISC_SYNC_CLOCK; 1516 1517 switch (crtc_state->pipe_bpp) { 1518 case 18: 1519 temp |= DP_MSA_MISC_6_BPC; 1520 break; 1521 case 24: 1522 temp |= DP_MSA_MISC_8_BPC; 1523 break; 1524 case 30: 1525 temp |= DP_MSA_MISC_10_BPC; 1526 break; 1527 case 36: 1528 temp |= DP_MSA_MISC_12_BPC; 1529 break; 1530 default: 1531 MISSING_CASE(crtc_state->pipe_bpp); 1532 break; 1533 } 1534 1535 /* nonsense combination */ 1536 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 1537 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 1538 1539 if (crtc_state->limited_color_range) 1540 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 1541 1542 /* 1543 * As per DP 1.2 spec section 2.3.4.3 while sending 1544 * YCBCR 444 signals we should program MSA MISC1/0 fields with 1545 * colorspace information. 1546 */ 1547 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 1548 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 1549 1550 /* 1551 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 1552 * of Color Encoding Format and Content Color Gamut] while sending 1553 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 1554 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 1555 */ 1556 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 1557 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 1558 1559 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp); 1560 } 1561 1562 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 1563 { 1564 if (master_transcoder == TRANSCODER_EDP) 1565 return 0; 1566 else 1567 return master_transcoder + 1; 1568 } 1569 1570 /* 1571 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 1572 * 1573 * Only intended to be used by intel_ddi_enable_transcoder_func() and 1574 * intel_ddi_config_transcoder_func(). 1575 */ 1576 static u32 1577 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 1578 const struct intel_crtc_state *crtc_state) 1579 { 1580 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1581 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1582 enum pipe pipe = crtc->pipe; 1583 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1584 enum port port = encoder->port; 1585 u32 temp; 1586 1587 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 1588 temp = TRANS_DDI_FUNC_ENABLE; 1589 if (INTEL_GEN(dev_priv) >= 12) 1590 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 1591 else 1592 temp |= TRANS_DDI_SELECT_PORT(port); 1593 1594 switch (crtc_state->pipe_bpp) { 1595 case 18: 1596 temp |= TRANS_DDI_BPC_6; 1597 break; 1598 case 24: 1599 temp |= TRANS_DDI_BPC_8; 1600 break; 1601 case 30: 1602 temp |= TRANS_DDI_BPC_10; 1603 break; 1604 case 36: 1605 temp |= TRANS_DDI_BPC_12; 1606 break; 1607 default: 1608 BUG(); 1609 } 1610 1611 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 1612 temp |= TRANS_DDI_PVSYNC; 1613 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 1614 temp |= TRANS_DDI_PHSYNC; 1615 1616 if (cpu_transcoder == TRANSCODER_EDP) { 1617 switch (pipe) { 1618 case PIPE_A: 1619 /* On Haswell, can only use the always-on power well for 1620 * eDP when not using the panel fitter, and when not 1621 * using motion blur mitigation (which we don't 1622 * support). */ 1623 if (crtc_state->pch_pfit.force_thru) 1624 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 1625 else 1626 temp |= TRANS_DDI_EDP_INPUT_A_ON; 1627 break; 1628 case PIPE_B: 1629 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 1630 break; 1631 case PIPE_C: 1632 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 1633 break; 1634 default: 1635 BUG(); 1636 break; 1637 } 1638 } 1639 1640 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1641 if (crtc_state->has_hdmi_sink) 1642 temp |= TRANS_DDI_MODE_SELECT_HDMI; 1643 else 1644 temp |= TRANS_DDI_MODE_SELECT_DVI; 1645 1646 if (crtc_state->hdmi_scrambling) 1647 temp |= TRANS_DDI_HDMI_SCRAMBLING; 1648 if (crtc_state->hdmi_high_tmds_clock_ratio) 1649 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 1650 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 1651 temp |= TRANS_DDI_MODE_SELECT_FDI; 1652 temp |= (crtc_state->fdi_lanes - 1) << 1; 1653 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 1654 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 1655 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 1656 1657 if (INTEL_GEN(dev_priv) >= 12) { 1658 enum transcoder master; 1659 1660 master = crtc_state->mst_master_transcoder; 1661 drm_WARN_ON(&dev_priv->drm, 1662 master == INVALID_TRANSCODER); 1663 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 1664 } 1665 } else { 1666 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 1667 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 1668 } 1669 1670 if (IS_GEN_RANGE(dev_priv, 8, 10) && 1671 crtc_state->master_transcoder != INVALID_TRANSCODER) { 1672 u8 master_select = 1673 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 1674 1675 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 1676 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 1677 } 1678 1679 return temp; 1680 } 1681 1682 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 1683 const struct intel_crtc_state *crtc_state) 1684 { 1685 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1686 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1687 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1688 1689 if (INTEL_GEN(dev_priv) >= 11) { 1690 enum transcoder master_transcoder = crtc_state->master_transcoder; 1691 u32 ctl2 = 0; 1692 1693 if (master_transcoder != INVALID_TRANSCODER) { 1694 u8 master_select = 1695 bdw_trans_port_sync_master_select(master_transcoder); 1696 1697 ctl2 |= PORT_SYNC_MODE_ENABLE | 1698 PORT_SYNC_MODE_MASTER_SELECT(master_select); 1699 } 1700 1701 intel_de_write(dev_priv, 1702 TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2); 1703 } 1704 1705 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 1706 intel_ddi_transcoder_func_reg_val_get(encoder, 1707 crtc_state)); 1708 } 1709 1710 /* 1711 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 1712 * bit. 1713 */ 1714 static void 1715 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 1716 const struct intel_crtc_state *crtc_state) 1717 { 1718 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1719 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1720 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1721 u32 ctl; 1722 1723 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 1724 ctl &= ~TRANS_DDI_FUNC_ENABLE; 1725 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 1726 } 1727 1728 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 1729 { 1730 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1731 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1732 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1733 u32 ctl; 1734 1735 if (INTEL_GEN(dev_priv) >= 11) 1736 intel_de_write(dev_priv, 1737 TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0); 1738 1739 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1740 1741 ctl &= ~TRANS_DDI_FUNC_ENABLE; 1742 1743 if (IS_GEN_RANGE(dev_priv, 8, 10)) 1744 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 1745 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 1746 1747 if (INTEL_GEN(dev_priv) >= 12) { 1748 if (!intel_dp_mst_is_master_trans(crtc_state)) { 1749 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 1750 TRANS_DDI_MODE_SELECT_MASK); 1751 } 1752 } else { 1753 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 1754 } 1755 1756 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 1757 1758 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME && 1759 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1760 drm_dbg_kms(&dev_priv->drm, 1761 "Quirk Increase DDI disabled time\n"); 1762 /* Quirk time at 100ms for reliable operation */ 1763 msleep(100); 1764 } 1765 } 1766 1767 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder, 1768 bool enable) 1769 { 1770 struct drm_device *dev = intel_encoder->base.dev; 1771 struct drm_i915_private *dev_priv = to_i915(dev); 1772 intel_wakeref_t wakeref; 1773 enum pipe pipe = 0; 1774 int ret = 0; 1775 u32 tmp; 1776 1777 wakeref = intel_display_power_get_if_enabled(dev_priv, 1778 intel_encoder->power_domain); 1779 if (drm_WARN_ON(dev, !wakeref)) 1780 return -ENXIO; 1781 1782 if (drm_WARN_ON(dev, 1783 !intel_encoder->get_hw_state(intel_encoder, &pipe))) { 1784 ret = -EIO; 1785 goto out; 1786 } 1787 1788 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe)); 1789 if (enable) 1790 tmp |= TRANS_DDI_HDCP_SIGNALLING; 1791 else 1792 tmp &= ~TRANS_DDI_HDCP_SIGNALLING; 1793 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), tmp); 1794 out: 1795 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 1796 return ret; 1797 } 1798 1799 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 1800 { 1801 struct drm_device *dev = intel_connector->base.dev; 1802 struct drm_i915_private *dev_priv = to_i915(dev); 1803 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 1804 int type = intel_connector->base.connector_type; 1805 enum port port = encoder->port; 1806 enum transcoder cpu_transcoder; 1807 intel_wakeref_t wakeref; 1808 enum pipe pipe = 0; 1809 u32 tmp; 1810 bool ret; 1811 1812 wakeref = intel_display_power_get_if_enabled(dev_priv, 1813 encoder->power_domain); 1814 if (!wakeref) 1815 return false; 1816 1817 if (!encoder->get_hw_state(encoder, &pipe)) { 1818 ret = false; 1819 goto out; 1820 } 1821 1822 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 1823 cpu_transcoder = TRANSCODER_EDP; 1824 else 1825 cpu_transcoder = (enum transcoder) pipe; 1826 1827 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1828 1829 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 1830 case TRANS_DDI_MODE_SELECT_HDMI: 1831 case TRANS_DDI_MODE_SELECT_DVI: 1832 ret = type == DRM_MODE_CONNECTOR_HDMIA; 1833 break; 1834 1835 case TRANS_DDI_MODE_SELECT_DP_SST: 1836 ret = type == DRM_MODE_CONNECTOR_eDP || 1837 type == DRM_MODE_CONNECTOR_DisplayPort; 1838 break; 1839 1840 case TRANS_DDI_MODE_SELECT_DP_MST: 1841 /* if the transcoder is in MST state then 1842 * connector isn't connected */ 1843 ret = false; 1844 break; 1845 1846 case TRANS_DDI_MODE_SELECT_FDI: 1847 ret = type == DRM_MODE_CONNECTOR_VGA; 1848 break; 1849 1850 default: 1851 ret = false; 1852 break; 1853 } 1854 1855 out: 1856 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1857 1858 return ret; 1859 } 1860 1861 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 1862 u8 *pipe_mask, bool *is_dp_mst) 1863 { 1864 struct drm_device *dev = encoder->base.dev; 1865 struct drm_i915_private *dev_priv = to_i915(dev); 1866 enum port port = encoder->port; 1867 intel_wakeref_t wakeref; 1868 enum pipe p; 1869 u32 tmp; 1870 u8 mst_pipe_mask; 1871 1872 *pipe_mask = 0; 1873 *is_dp_mst = false; 1874 1875 wakeref = intel_display_power_get_if_enabled(dev_priv, 1876 encoder->power_domain); 1877 if (!wakeref) 1878 return; 1879 1880 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 1881 if (!(tmp & DDI_BUF_CTL_ENABLE)) 1882 goto out; 1883 1884 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { 1885 tmp = intel_de_read(dev_priv, 1886 TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 1887 1888 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 1889 default: 1890 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 1891 fallthrough; 1892 case TRANS_DDI_EDP_INPUT_A_ON: 1893 case TRANS_DDI_EDP_INPUT_A_ONOFF: 1894 *pipe_mask = BIT(PIPE_A); 1895 break; 1896 case TRANS_DDI_EDP_INPUT_B_ONOFF: 1897 *pipe_mask = BIT(PIPE_B); 1898 break; 1899 case TRANS_DDI_EDP_INPUT_C_ONOFF: 1900 *pipe_mask = BIT(PIPE_C); 1901 break; 1902 } 1903 1904 goto out; 1905 } 1906 1907 mst_pipe_mask = 0; 1908 for_each_pipe(dev_priv, p) { 1909 enum transcoder cpu_transcoder = (enum transcoder)p; 1910 unsigned int port_mask, ddi_select; 1911 intel_wakeref_t trans_wakeref; 1912 1913 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 1914 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 1915 if (!trans_wakeref) 1916 continue; 1917 1918 if (INTEL_GEN(dev_priv) >= 12) { 1919 port_mask = TGL_TRANS_DDI_PORT_MASK; 1920 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 1921 } else { 1922 port_mask = TRANS_DDI_PORT_MASK; 1923 ddi_select = TRANS_DDI_SELECT_PORT(port); 1924 } 1925 1926 tmp = intel_de_read(dev_priv, 1927 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1928 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 1929 trans_wakeref); 1930 1931 if ((tmp & port_mask) != ddi_select) 1932 continue; 1933 1934 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == 1935 TRANS_DDI_MODE_SELECT_DP_MST) 1936 mst_pipe_mask |= BIT(p); 1937 1938 *pipe_mask |= BIT(p); 1939 } 1940 1941 if (!*pipe_mask) 1942 drm_dbg_kms(&dev_priv->drm, 1943 "No pipe for [ENCODER:%d:%s] found\n", 1944 encoder->base.base.id, encoder->base.name); 1945 1946 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 1947 drm_dbg_kms(&dev_priv->drm, 1948 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 1949 encoder->base.base.id, encoder->base.name, 1950 *pipe_mask); 1951 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 1952 } 1953 1954 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 1955 drm_dbg_kms(&dev_priv->drm, 1956 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", 1957 encoder->base.base.id, encoder->base.name, 1958 *pipe_mask, mst_pipe_mask); 1959 else 1960 *is_dp_mst = mst_pipe_mask; 1961 1962 out: 1963 if (*pipe_mask && IS_GEN9_LP(dev_priv)) { 1964 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 1965 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 1966 BXT_PHY_LANE_POWERDOWN_ACK | 1967 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 1968 drm_err(&dev_priv->drm, 1969 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 1970 encoder->base.base.id, encoder->base.name, tmp); 1971 } 1972 1973 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1974 } 1975 1976 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 1977 enum pipe *pipe) 1978 { 1979 u8 pipe_mask; 1980 bool is_mst; 1981 1982 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 1983 1984 if (is_mst || !pipe_mask) 1985 return false; 1986 1987 *pipe = ffs(pipe_mask) - 1; 1988 1989 return true; 1990 } 1991 1992 static enum intel_display_power_domain 1993 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port) 1994 { 1995 /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with 1996 * DC states enabled at the same time, while for driver initiated AUX 1997 * transfers we need the same AUX IOs to be powered but with DC states 1998 * disabled. Accordingly use the AUX power domain here which leaves DC 1999 * states enabled. 2000 * However, for non-A AUX ports the corresponding non-EDP transcoders 2001 * would have already enabled power well 2 and DC_OFF. This means we can 2002 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a 2003 * specific AUX_IO reference without powering up any extra wells. 2004 * Note that PSR is enabled only on Port A even though this function 2005 * returns the correct domain for other ports too. 2006 */ 2007 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A : 2008 intel_aux_power_domain(dig_port); 2009 } 2010 2011 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 2012 struct intel_crtc_state *crtc_state) 2013 { 2014 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2015 struct intel_digital_port *dig_port; 2016 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2017 2018 /* 2019 * TODO: Add support for MST encoders. Atm, the following should never 2020 * happen since fake-MST encoders don't set their get_power_domains() 2021 * hook. 2022 */ 2023 if (drm_WARN_ON(&dev_priv->drm, 2024 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 2025 return; 2026 2027 dig_port = enc_to_dig_port(encoder); 2028 2029 if (!intel_phy_is_tc(dev_priv, phy) || 2030 dig_port->tc_mode != TC_PORT_TBT_ALT) 2031 intel_display_power_get(dev_priv, 2032 dig_port->ddi_io_power_domain); 2033 2034 /* 2035 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC 2036 * ports. 2037 */ 2038 if (intel_crtc_has_dp_encoder(crtc_state) || 2039 intel_phy_is_tc(dev_priv, phy)) 2040 intel_display_power_get(dev_priv, 2041 intel_ddi_main_link_aux_domain(dig_port)); 2042 2043 /* 2044 * VDSC power is needed when DSC is enabled 2045 */ 2046 if (crtc_state->dsc.compression_enable) 2047 intel_display_power_get(dev_priv, 2048 intel_dsc_power_domain(crtc_state)); 2049 } 2050 2051 void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder, 2052 const struct intel_crtc_state *crtc_state) 2053 { 2054 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2055 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2056 enum port port = encoder->port; 2057 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2058 2059 if (cpu_transcoder != TRANSCODER_EDP) { 2060 if (INTEL_GEN(dev_priv) >= 12) 2061 intel_de_write(dev_priv, 2062 TRANS_CLK_SEL(cpu_transcoder), 2063 TGL_TRANS_CLK_SEL_PORT(port)); 2064 else 2065 intel_de_write(dev_priv, 2066 TRANS_CLK_SEL(cpu_transcoder), 2067 TRANS_CLK_SEL_PORT(port)); 2068 } 2069 } 2070 2071 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state) 2072 { 2073 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2074 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2075 2076 if (cpu_transcoder != TRANSCODER_EDP) { 2077 if (INTEL_GEN(dev_priv) >= 12) 2078 intel_de_write(dev_priv, 2079 TRANS_CLK_SEL(cpu_transcoder), 2080 TGL_TRANS_CLK_SEL_DISABLED); 2081 else 2082 intel_de_write(dev_priv, 2083 TRANS_CLK_SEL(cpu_transcoder), 2084 TRANS_CLK_SEL_DISABLED); 2085 } 2086 } 2087 2088 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 2089 enum port port, u8 iboost) 2090 { 2091 u32 tmp; 2092 2093 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 2094 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 2095 if (iboost) 2096 tmp |= iboost << BALANCE_LEG_SHIFT(port); 2097 else 2098 tmp |= BALANCE_LEG_DISABLE(port); 2099 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 2100 } 2101 2102 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 2103 int level, enum intel_output_type type) 2104 { 2105 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2106 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2107 u8 iboost; 2108 2109 if (type == INTEL_OUTPUT_HDMI) 2110 iboost = intel_bios_hdmi_boost_level(encoder); 2111 else 2112 iboost = intel_bios_dp_boost_level(encoder); 2113 2114 if (iboost == 0) { 2115 const struct ddi_buf_trans *ddi_translations; 2116 int n_entries; 2117 2118 if (type == INTEL_OUTPUT_HDMI) 2119 ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); 2120 else if (type == INTEL_OUTPUT_EDP) 2121 ddi_translations = intel_ddi_get_buf_trans_edp(encoder, 2122 &n_entries); 2123 else 2124 ddi_translations = intel_ddi_get_buf_trans_dp(encoder, 2125 &n_entries); 2126 2127 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 2128 return; 2129 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 2130 level = n_entries - 1; 2131 2132 iboost = ddi_translations[level].i_boost; 2133 } 2134 2135 /* Make sure that the requested I_boost is valid */ 2136 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 2137 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); 2138 return; 2139 } 2140 2141 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); 2142 2143 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 2144 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 2145 } 2146 2147 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, 2148 int level, enum intel_output_type type) 2149 { 2150 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2151 const struct bxt_ddi_buf_trans *ddi_translations; 2152 enum port port = encoder->port; 2153 int n_entries; 2154 2155 if (type == INTEL_OUTPUT_HDMI) 2156 ddi_translations = bxt_get_buf_trans_hdmi(encoder, &n_entries); 2157 else if (type == INTEL_OUTPUT_EDP) 2158 ddi_translations = bxt_get_buf_trans_edp(encoder, &n_entries); 2159 else 2160 ddi_translations = bxt_get_buf_trans_dp(encoder, &n_entries); 2161 2162 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 2163 return; 2164 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 2165 level = n_entries - 1; 2166 2167 bxt_ddi_phy_set_signal_level(dev_priv, port, 2168 ddi_translations[level].margin, 2169 ddi_translations[level].scale, 2170 ddi_translations[level].enable, 2171 ddi_translations[level].deemphasis); 2172 } 2173 2174 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp) 2175 { 2176 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2177 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2178 enum port port = encoder->port; 2179 enum phy phy = intel_port_to_phy(dev_priv, port); 2180 int n_entries; 2181 2182 if (INTEL_GEN(dev_priv) >= 12) { 2183 if (intel_phy_is_combo(dev_priv, phy)) 2184 tgl_get_combo_buf_trans(encoder, encoder->type, 2185 intel_dp->link_rate, &n_entries); 2186 else 2187 tgl_get_dkl_buf_trans(encoder, encoder->type, 2188 intel_dp->link_rate, &n_entries); 2189 } else if (INTEL_GEN(dev_priv) == 11) { 2190 if (IS_ELKHARTLAKE(dev_priv)) 2191 ehl_get_combo_buf_trans(encoder, encoder->type, 2192 intel_dp->link_rate, &n_entries); 2193 else if (intel_phy_is_combo(dev_priv, phy)) 2194 icl_get_combo_buf_trans(encoder, encoder->type, 2195 intel_dp->link_rate, &n_entries); 2196 else 2197 icl_get_mg_buf_trans(encoder, encoder->type, 2198 intel_dp->link_rate, &n_entries); 2199 } else if (IS_CANNONLAKE(dev_priv)) { 2200 if (encoder->type == INTEL_OUTPUT_EDP) 2201 cnl_get_buf_trans_edp(encoder, &n_entries); 2202 else 2203 cnl_get_buf_trans_dp(encoder, &n_entries); 2204 } else if (IS_GEN9_LP(dev_priv)) { 2205 if (encoder->type == INTEL_OUTPUT_EDP) 2206 bxt_get_buf_trans_edp(encoder, &n_entries); 2207 else 2208 bxt_get_buf_trans_dp(encoder, &n_entries); 2209 } else { 2210 if (encoder->type == INTEL_OUTPUT_EDP) 2211 intel_ddi_get_buf_trans_edp(encoder, &n_entries); 2212 else 2213 intel_ddi_get_buf_trans_dp(encoder, &n_entries); 2214 } 2215 2216 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 2217 n_entries = 1; 2218 if (drm_WARN_ON(&dev_priv->drm, 2219 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 2220 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 2221 2222 return index_to_dp_signal_levels[n_entries - 1] & 2223 DP_TRAIN_VOLTAGE_SWING_MASK; 2224 } 2225 2226 /* 2227 * We assume that the full set of pre-emphasis values can be 2228 * used on all DDI platforms. Should that change we need to 2229 * rethink this code. 2230 */ 2231 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 2232 { 2233 return DP_TRAIN_PRE_EMPH_LEVEL_3; 2234 } 2235 2236 static void cnl_ddi_vswing_program(struct intel_encoder *encoder, 2237 int level, enum intel_output_type type) 2238 { 2239 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2240 const struct cnl_ddi_buf_trans *ddi_translations; 2241 enum port port = encoder->port; 2242 int n_entries, ln; 2243 u32 val; 2244 2245 if (type == INTEL_OUTPUT_HDMI) 2246 ddi_translations = cnl_get_buf_trans_hdmi(encoder, &n_entries); 2247 else if (type == INTEL_OUTPUT_EDP) 2248 ddi_translations = cnl_get_buf_trans_edp(encoder, &n_entries); 2249 else 2250 ddi_translations = cnl_get_buf_trans_dp(encoder, &n_entries); 2251 2252 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 2253 return; 2254 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 2255 level = n_entries - 1; 2256 2257 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */ 2258 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 2259 val &= ~SCALING_MODE_SEL_MASK; 2260 val |= SCALING_MODE_SEL(2); 2261 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 2262 2263 /* Program PORT_TX_DW2 */ 2264 val = intel_de_read(dev_priv, CNL_PORT_TX_DW2_LN0(port)); 2265 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 2266 RCOMP_SCALAR_MASK); 2267 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); 2268 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); 2269 /* Rcomp scalar is fixed as 0x98 for every table entry */ 2270 val |= RCOMP_SCALAR(0x98); 2271 intel_de_write(dev_priv, CNL_PORT_TX_DW2_GRP(port), val); 2272 2273 /* Program PORT_TX_DW4 */ 2274 /* We cannot write to GRP. It would overrite individual loadgen */ 2275 for (ln = 0; ln < 4; ln++) { 2276 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port)); 2277 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 2278 CURSOR_COEFF_MASK); 2279 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); 2280 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); 2281 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); 2282 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val); 2283 } 2284 2285 /* Program PORT_TX_DW5 */ 2286 /* All DW5 values are fixed for every table entry */ 2287 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 2288 val &= ~RTERM_SELECT_MASK; 2289 val |= RTERM_SELECT(6); 2290 val |= TAP3_DISABLE; 2291 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 2292 2293 /* Program PORT_TX_DW7 */ 2294 val = intel_de_read(dev_priv, CNL_PORT_TX_DW7_LN0(port)); 2295 val &= ~N_SCALAR_MASK; 2296 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); 2297 intel_de_write(dev_priv, CNL_PORT_TX_DW7_GRP(port), val); 2298 } 2299 2300 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, 2301 int level, enum intel_output_type type) 2302 { 2303 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2304 enum port port = encoder->port; 2305 int width, rate, ln; 2306 u32 val; 2307 2308 if (type == INTEL_OUTPUT_HDMI) { 2309 width = 4; 2310 rate = 0; /* Rate is always < than 6GHz for HDMI */ 2311 } else { 2312 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2313 2314 width = intel_dp->lane_count; 2315 rate = intel_dp->link_rate; 2316 } 2317 2318 /* 2319 * 1. If port type is eDP or DP, 2320 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 2321 * else clear to 0b. 2322 */ 2323 val = intel_de_read(dev_priv, CNL_PORT_PCS_DW1_LN0(port)); 2324 if (type != INTEL_OUTPUT_HDMI) 2325 val |= COMMON_KEEPER_EN; 2326 else 2327 val &= ~COMMON_KEEPER_EN; 2328 intel_de_write(dev_priv, CNL_PORT_PCS_DW1_GRP(port), val); 2329 2330 /* 2. Program loadgen select */ 2331 /* 2332 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes 2333 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2334 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2335 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 2336 */ 2337 for (ln = 0; ln <= 3; ln++) { 2338 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port)); 2339 val &= ~LOADGEN_SELECT; 2340 2341 if ((rate <= 600000 && width == 4 && ln >= 1) || 2342 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { 2343 val |= LOADGEN_SELECT; 2344 } 2345 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val); 2346 } 2347 2348 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 2349 val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5); 2350 val |= SUS_CLOCK_CONFIG; 2351 intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val); 2352 2353 /* 4. Clear training enable to change swing values */ 2354 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 2355 val &= ~TX_TRAINING_EN; 2356 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 2357 2358 /* 5. Program swing and de-emphasis */ 2359 cnl_ddi_vswing_program(encoder, level, type); 2360 2361 /* 6. Set training enable to trigger update */ 2362 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 2363 val |= TX_TRAINING_EN; 2364 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 2365 } 2366 2367 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 2368 u32 level, int type, int rate) 2369 { 2370 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2371 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2372 const struct cnl_ddi_buf_trans *ddi_translations = NULL; 2373 u32 n_entries, val; 2374 int ln; 2375 2376 if (INTEL_GEN(dev_priv) >= 12) 2377 ddi_translations = tgl_get_combo_buf_trans(encoder, type, rate, 2378 &n_entries); 2379 else if (IS_ELKHARTLAKE(dev_priv)) 2380 ddi_translations = ehl_get_combo_buf_trans(encoder, type, rate, 2381 &n_entries); 2382 else 2383 ddi_translations = icl_get_combo_buf_trans(encoder, type, rate, 2384 &n_entries); 2385 if (!ddi_translations) 2386 return; 2387 2388 if (level >= n_entries) { 2389 drm_dbg_kms(&dev_priv->drm, 2390 "DDI translation not found for level %d. Using %d instead.", 2391 level, n_entries - 1); 2392 level = n_entries - 1; 2393 } 2394 2395 /* Set PORT_TX_DW5 */ 2396 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 2397 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 2398 TAP2_DISABLE | TAP3_DISABLE); 2399 val |= SCALING_MODE_SEL(0x2); 2400 val |= RTERM_SELECT(0x6); 2401 val |= TAP3_DISABLE; 2402 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 2403 2404 /* Program PORT_TX_DW2 */ 2405 val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy)); 2406 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 2407 RCOMP_SCALAR_MASK); 2408 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); 2409 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); 2410 /* Program Rcomp scalar for every table entry */ 2411 val |= RCOMP_SCALAR(0x98); 2412 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val); 2413 2414 /* Program PORT_TX_DW4 */ 2415 /* We cannot write to GRP. It would overwrite individual loadgen. */ 2416 for (ln = 0; ln <= 3; ln++) { 2417 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy)); 2418 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 2419 CURSOR_COEFF_MASK); 2420 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); 2421 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); 2422 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); 2423 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val); 2424 } 2425 2426 /* Program PORT_TX_DW7 */ 2427 val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy)); 2428 val &= ~N_SCALAR_MASK; 2429 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); 2430 intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val); 2431 } 2432 2433 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 2434 u32 level, 2435 enum intel_output_type type) 2436 { 2437 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2438 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2439 int width = 0; 2440 int rate = 0; 2441 u32 val; 2442 int ln = 0; 2443 2444 if (type == INTEL_OUTPUT_HDMI) { 2445 width = 4; 2446 /* Rate is always < than 6GHz for HDMI */ 2447 } else { 2448 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2449 2450 width = intel_dp->lane_count; 2451 rate = intel_dp->link_rate; 2452 } 2453 2454 /* 2455 * 1. If port type is eDP or DP, 2456 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 2457 * else clear to 0b. 2458 */ 2459 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy)); 2460 if (type == INTEL_OUTPUT_HDMI) 2461 val &= ~COMMON_KEEPER_EN; 2462 else 2463 val |= COMMON_KEEPER_EN; 2464 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 2465 2466 /* 2. Program loadgen select */ 2467 /* 2468 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes 2469 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2470 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2471 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 2472 */ 2473 for (ln = 0; ln <= 3; ln++) { 2474 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy)); 2475 val &= ~LOADGEN_SELECT; 2476 2477 if ((rate <= 600000 && width == 4 && ln >= 1) || 2478 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { 2479 val |= LOADGEN_SELECT; 2480 } 2481 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val); 2482 } 2483 2484 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 2485 val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); 2486 val |= SUS_CLOCK_CONFIG; 2487 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val); 2488 2489 /* 4. Clear training enable to change swing values */ 2490 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 2491 val &= ~TX_TRAINING_EN; 2492 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 2493 2494 /* 5. Program swing and de-emphasis */ 2495 icl_ddi_combo_vswing_program(encoder, level, type, rate); 2496 2497 /* 6. Set training enable to trigger update */ 2498 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 2499 val |= TX_TRAINING_EN; 2500 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 2501 } 2502 2503 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 2504 int link_clock, u32 level, 2505 enum intel_output_type type) 2506 { 2507 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2508 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 2509 const struct icl_mg_phy_ddi_buf_trans *ddi_translations; 2510 u32 n_entries, val; 2511 int ln, rate = 0; 2512 2513 if (type != INTEL_OUTPUT_HDMI) { 2514 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2515 2516 rate = intel_dp->link_rate; 2517 } 2518 2519 ddi_translations = icl_get_mg_buf_trans(encoder, type, rate, 2520 &n_entries); 2521 /* The table does not have values for level 3 and level 9. */ 2522 if (level >= n_entries || level == 3 || level == 9) { 2523 drm_dbg_kms(&dev_priv->drm, 2524 "DDI translation not found for level %d. Using %d instead.", 2525 level, n_entries - 2); 2526 level = n_entries - 2; 2527 } 2528 2529 /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */ 2530 for (ln = 0; ln < 2; ln++) { 2531 val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port)); 2532 val &= ~CRI_USE_FS32; 2533 intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), val); 2534 2535 val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port)); 2536 val &= ~CRI_USE_FS32; 2537 intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), val); 2538 } 2539 2540 /* Program MG_TX_SWINGCTRL with values from vswing table */ 2541 for (ln = 0; ln < 2; ln++) { 2542 val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port)); 2543 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; 2544 val |= CRI_TXDEEMPH_OVERRIDE_17_12( 2545 ddi_translations[level].cri_txdeemph_override_17_12); 2546 intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val); 2547 2548 val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port)); 2549 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; 2550 val |= CRI_TXDEEMPH_OVERRIDE_17_12( 2551 ddi_translations[level].cri_txdeemph_override_17_12); 2552 intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val); 2553 } 2554 2555 /* Program MG_TX_DRVCTRL with values from vswing table */ 2556 for (ln = 0; ln < 2; ln++) { 2557 val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port)); 2558 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 2559 CRI_TXDEEMPH_OVERRIDE_5_0_MASK); 2560 val |= CRI_TXDEEMPH_OVERRIDE_5_0( 2561 ddi_translations[level].cri_txdeemph_override_5_0) | 2562 CRI_TXDEEMPH_OVERRIDE_11_6( 2563 ddi_translations[level].cri_txdeemph_override_11_6) | 2564 CRI_TXDEEMPH_OVERRIDE_EN; 2565 intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val); 2566 2567 val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port)); 2568 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 2569 CRI_TXDEEMPH_OVERRIDE_5_0_MASK); 2570 val |= CRI_TXDEEMPH_OVERRIDE_5_0( 2571 ddi_translations[level].cri_txdeemph_override_5_0) | 2572 CRI_TXDEEMPH_OVERRIDE_11_6( 2573 ddi_translations[level].cri_txdeemph_override_11_6) | 2574 CRI_TXDEEMPH_OVERRIDE_EN; 2575 intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val); 2576 2577 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 2578 } 2579 2580 /* 2581 * Program MG_CLKHUB<LN, port being used> with value from frequency table 2582 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 2583 * values from table for which TX1 and TX2 enabled. 2584 */ 2585 for (ln = 0; ln < 2; ln++) { 2586 val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port)); 2587 if (link_clock < 300000) 2588 val |= CFG_LOW_RATE_LKREN_EN; 2589 else 2590 val &= ~CFG_LOW_RATE_LKREN_EN; 2591 intel_de_write(dev_priv, MG_CLKHUB(ln, tc_port), val); 2592 } 2593 2594 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 2595 for (ln = 0; ln < 2; ln++) { 2596 val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port)); 2597 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; 2598 if (link_clock <= 500000) { 2599 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; 2600 } else { 2601 val |= CFG_AMI_CK_DIV_OVERRIDE_EN | 2602 CFG_AMI_CK_DIV_OVERRIDE_VAL(1); 2603 } 2604 intel_de_write(dev_priv, MG_TX1_DCC(ln, tc_port), val); 2605 2606 val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port)); 2607 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; 2608 if (link_clock <= 500000) { 2609 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; 2610 } else { 2611 val |= CFG_AMI_CK_DIV_OVERRIDE_EN | 2612 CFG_AMI_CK_DIV_OVERRIDE_VAL(1); 2613 } 2614 intel_de_write(dev_priv, MG_TX2_DCC(ln, tc_port), val); 2615 } 2616 2617 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 2618 for (ln = 0; ln < 2; ln++) { 2619 val = intel_de_read(dev_priv, 2620 MG_TX1_PISO_READLOAD(ln, tc_port)); 2621 val |= CRI_CALCINIT; 2622 intel_de_write(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 2623 val); 2624 2625 val = intel_de_read(dev_priv, 2626 MG_TX2_PISO_READLOAD(ln, tc_port)); 2627 val |= CRI_CALCINIT; 2628 intel_de_write(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 2629 val); 2630 } 2631 } 2632 2633 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder, 2634 int link_clock, 2635 u32 level, 2636 enum intel_output_type type) 2637 { 2638 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2639 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2640 2641 if (intel_phy_is_combo(dev_priv, phy)) 2642 icl_combo_phy_ddi_vswing_sequence(encoder, level, type); 2643 else 2644 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level, 2645 type); 2646 } 2647 2648 static void 2649 tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock, 2650 u32 level, enum intel_output_type type) 2651 { 2652 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2653 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 2654 const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations; 2655 u32 n_entries, val, ln, dpcnt_mask, dpcnt_val; 2656 int rate = 0; 2657 2658 if (type == INTEL_OUTPUT_HDMI) { 2659 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2660 2661 rate = intel_dp->link_rate; 2662 } 2663 2664 ddi_translations = tgl_get_dkl_buf_trans(encoder, encoder->type, rate, 2665 &n_entries); 2666 2667 if (level >= n_entries) 2668 level = n_entries - 1; 2669 2670 dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK | 2671 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 2672 DKL_TX_VSWING_CONTROL_MASK); 2673 dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control); 2674 dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control); 2675 dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control); 2676 2677 for (ln = 0; ln < 2; ln++) { 2678 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2679 HIP_INDEX_VAL(tc_port, ln)); 2680 2681 intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0); 2682 2683 /* All the registers are RMW */ 2684 val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(tc_port)); 2685 val &= ~dpcnt_mask; 2686 val |= dpcnt_val; 2687 intel_de_write(dev_priv, DKL_TX_DPCNTL0(tc_port), val); 2688 2689 val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(tc_port)); 2690 val &= ~dpcnt_mask; 2691 val |= dpcnt_val; 2692 intel_de_write(dev_priv, DKL_TX_DPCNTL1(tc_port), val); 2693 2694 val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port)); 2695 val &= ~DKL_TX_DP20BITMODE; 2696 intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val); 2697 } 2698 } 2699 2700 static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder, 2701 int link_clock, 2702 u32 level, 2703 enum intel_output_type type) 2704 { 2705 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2706 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2707 2708 if (intel_phy_is_combo(dev_priv, phy)) 2709 icl_combo_phy_ddi_vswing_sequence(encoder, level, type); 2710 else 2711 tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level, type); 2712 } 2713 2714 static u32 translate_signal_level(struct intel_dp *intel_dp, int signal_levels) 2715 { 2716 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2717 int i; 2718 2719 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 2720 if (index_to_dp_signal_levels[i] == signal_levels) 2721 return i; 2722 } 2723 2724 drm_WARN(&i915->drm, 1, 2725 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 2726 signal_levels); 2727 2728 return 0; 2729 } 2730 2731 static u32 intel_ddi_dp_level(struct intel_dp *intel_dp) 2732 { 2733 u8 train_set = intel_dp->train_set[0]; 2734 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2735 DP_TRAIN_PRE_EMPHASIS_MASK); 2736 2737 return translate_signal_level(intel_dp, signal_levels); 2738 } 2739 2740 static void 2741 tgl_set_signal_levels(struct intel_dp *intel_dp) 2742 { 2743 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2744 int level = intel_ddi_dp_level(intel_dp); 2745 2746 tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate, 2747 level, encoder->type); 2748 } 2749 2750 static void 2751 icl_set_signal_levels(struct intel_dp *intel_dp) 2752 { 2753 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2754 int level = intel_ddi_dp_level(intel_dp); 2755 2756 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate, 2757 level, encoder->type); 2758 } 2759 2760 static void 2761 cnl_set_signal_levels(struct intel_dp *intel_dp) 2762 { 2763 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2764 int level = intel_ddi_dp_level(intel_dp); 2765 2766 cnl_ddi_vswing_sequence(encoder, level, encoder->type); 2767 } 2768 2769 static void 2770 bxt_set_signal_levels(struct intel_dp *intel_dp) 2771 { 2772 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2773 int level = intel_ddi_dp_level(intel_dp); 2774 2775 bxt_ddi_vswing_sequence(encoder, level, encoder->type); 2776 } 2777 2778 static void 2779 hsw_set_signal_levels(struct intel_dp *intel_dp) 2780 { 2781 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2782 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2783 int level = intel_ddi_dp_level(intel_dp); 2784 enum port port = encoder->port; 2785 u32 signal_levels; 2786 2787 signal_levels = DDI_BUF_TRANS_SELECT(level); 2788 2789 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 2790 signal_levels); 2791 2792 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 2793 intel_dp->DP |= signal_levels; 2794 2795 if (IS_GEN9_BC(dev_priv)) 2796 skl_ddi_set_iboost(encoder, level, encoder->type); 2797 2798 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 2799 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 2800 } 2801 2802 static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv, 2803 enum phy phy) 2804 { 2805 if (intel_phy_is_combo(dev_priv, phy)) { 2806 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 2807 } else if (intel_phy_is_tc(dev_priv, phy)) { 2808 enum tc_port tc_port = intel_port_to_tc(dev_priv, 2809 (enum port)phy); 2810 2811 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port); 2812 } 2813 2814 return 0; 2815 } 2816 2817 static void icl_map_plls_to_ports(struct intel_encoder *encoder, 2818 const struct intel_crtc_state *crtc_state) 2819 { 2820 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2821 struct intel_shared_dpll *pll = crtc_state->shared_dpll; 2822 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2823 u32 val; 2824 2825 mutex_lock(&dev_priv->dpll.lock); 2826 2827 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 2828 drm_WARN_ON(&dev_priv->drm, 2829 (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0); 2830 2831 if (intel_phy_is_combo(dev_priv, phy)) { 2832 /* 2833 * Even though this register references DDIs, note that we 2834 * want to pass the PHY rather than the port (DDI). For 2835 * ICL, port=phy in all cases so it doesn't matter, but for 2836 * EHL the bspec notes the following: 2837 * 2838 * "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA 2839 * Clock Select chooses the PLL for both DDIA and DDID and 2840 * drives port A in all cases." 2841 */ 2842 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 2843 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 2844 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 2845 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); 2846 } 2847 2848 val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 2849 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 2850 2851 mutex_unlock(&dev_priv->dpll.lock); 2852 } 2853 2854 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder) 2855 { 2856 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2857 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2858 u32 val; 2859 2860 mutex_lock(&dev_priv->dpll.lock); 2861 2862 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 2863 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 2864 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 2865 2866 mutex_unlock(&dev_priv->dpll.lock); 2867 } 2868 2869 static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv, 2870 u32 port_mask, bool ddi_clk_needed) 2871 { 2872 enum port port; 2873 u32 val; 2874 2875 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 2876 for_each_port_masked(port, port_mask) { 2877 enum phy phy = intel_port_to_phy(dev_priv, port); 2878 bool ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv, 2879 phy); 2880 2881 if (ddi_clk_needed == !ddi_clk_off) 2882 continue; 2883 2884 /* 2885 * Punt on the case now where clock is gated, but it would 2886 * be needed by the port. Something else is really broken then. 2887 */ 2888 if (drm_WARN_ON(&dev_priv->drm, ddi_clk_needed)) 2889 continue; 2890 2891 drm_notice(&dev_priv->drm, 2892 "PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2893 phy_name(phy)); 2894 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 2895 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 2896 } 2897 } 2898 2899 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2900 { 2901 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2902 u32 port_mask; 2903 bool ddi_clk_needed; 2904 2905 /* 2906 * In case of DP MST, we sanitize the primary encoder only, not the 2907 * virtual ones. 2908 */ 2909 if (encoder->type == INTEL_OUTPUT_DP_MST) 2910 return; 2911 2912 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2913 u8 pipe_mask; 2914 bool is_mst; 2915 2916 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2917 /* 2918 * In the unlikely case that BIOS enables DP in MST mode, just 2919 * warn since our MST HW readout is incomplete. 2920 */ 2921 if (drm_WARN_ON(&dev_priv->drm, is_mst)) 2922 return; 2923 } 2924 2925 port_mask = BIT(encoder->port); 2926 ddi_clk_needed = encoder->base.crtc; 2927 2928 if (encoder->type == INTEL_OUTPUT_DSI) { 2929 struct intel_encoder *other_encoder; 2930 2931 port_mask = intel_dsi_encoder_ports(encoder); 2932 /* 2933 * Sanity check that we haven't incorrectly registered another 2934 * encoder using any of the ports of this DSI encoder. 2935 */ 2936 for_each_intel_encoder(&dev_priv->drm, other_encoder) { 2937 if (other_encoder == encoder) 2938 continue; 2939 2940 if (drm_WARN_ON(&dev_priv->drm, 2941 port_mask & BIT(other_encoder->port))) 2942 return; 2943 } 2944 /* 2945 * For DSI we keep the ddi clocks gated 2946 * except during enable/disable sequence. 2947 */ 2948 ddi_clk_needed = false; 2949 } 2950 2951 icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed); 2952 } 2953 2954 static void intel_ddi_clk_select(struct intel_encoder *encoder, 2955 const struct intel_crtc_state *crtc_state) 2956 { 2957 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2958 enum port port = encoder->port; 2959 enum phy phy = intel_port_to_phy(dev_priv, port); 2960 u32 val; 2961 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 2962 2963 if (drm_WARN_ON(&dev_priv->drm, !pll)) 2964 return; 2965 2966 mutex_lock(&dev_priv->dpll.lock); 2967 2968 if (INTEL_GEN(dev_priv) >= 11) { 2969 if (!intel_phy_is_combo(dev_priv, phy)) 2970 intel_de_write(dev_priv, DDI_CLK_SEL(port), 2971 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 2972 else if (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C) 2973 /* 2974 * MG does not exist but the programming is required 2975 * to ungate DDIC and DDID 2976 */ 2977 intel_de_write(dev_priv, DDI_CLK_SEL(port), 2978 DDI_CLK_SEL_MG); 2979 } else if (IS_CANNONLAKE(dev_priv)) { 2980 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */ 2981 val = intel_de_read(dev_priv, DPCLKA_CFGCR0); 2982 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); 2983 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port); 2984 intel_de_write(dev_priv, DPCLKA_CFGCR0, val); 2985 2986 /* 2987 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI. 2988 * This step and the step before must be done with separate 2989 * register writes. 2990 */ 2991 val = intel_de_read(dev_priv, DPCLKA_CFGCR0); 2992 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); 2993 intel_de_write(dev_priv, DPCLKA_CFGCR0, val); 2994 } else if (IS_GEN9_BC(dev_priv)) { 2995 /* DDI -> PLL mapping */ 2996 val = intel_de_read(dev_priv, DPLL_CTRL2); 2997 2998 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | 2999 DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); 3000 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 3001 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 3002 3003 intel_de_write(dev_priv, DPLL_CTRL2, val); 3004 3005 } else if (INTEL_GEN(dev_priv) < 9) { 3006 intel_de_write(dev_priv, PORT_CLK_SEL(port), 3007 hsw_pll_to_ddi_pll_sel(pll)); 3008 } 3009 3010 mutex_unlock(&dev_priv->dpll.lock); 3011 } 3012 3013 static void intel_ddi_clk_disable(struct intel_encoder *encoder) 3014 { 3015 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3016 enum port port = encoder->port; 3017 enum phy phy = intel_port_to_phy(dev_priv, port); 3018 3019 if (INTEL_GEN(dev_priv) >= 11) { 3020 if (!intel_phy_is_combo(dev_priv, phy) || 3021 (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C)) 3022 intel_de_write(dev_priv, DDI_CLK_SEL(port), 3023 DDI_CLK_SEL_NONE); 3024 } else if (IS_CANNONLAKE(dev_priv)) { 3025 intel_de_write(dev_priv, DPCLKA_CFGCR0, 3026 intel_de_read(dev_priv, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port)); 3027 } else if (IS_GEN9_BC(dev_priv)) { 3028 intel_de_write(dev_priv, DPLL_CTRL2, 3029 intel_de_read(dev_priv, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port)); 3030 } else if (INTEL_GEN(dev_priv) < 9) { 3031 intel_de_write(dev_priv, PORT_CLK_SEL(port), 3032 PORT_CLK_SEL_NONE); 3033 } 3034 } 3035 3036 static void 3037 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 3038 const struct intel_crtc_state *crtc_state) 3039 { 3040 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 3041 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port); 3042 u32 ln0, ln1, pin_assignment; 3043 u8 width; 3044 3045 if (dig_port->tc_mode == TC_PORT_TBT_ALT) 3046 return; 3047 3048 if (INTEL_GEN(dev_priv) >= 12) { 3049 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 3050 HIP_INDEX_VAL(tc_port, 0x0)); 3051 ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); 3052 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 3053 HIP_INDEX_VAL(tc_port, 0x1)); 3054 ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); 3055 } else { 3056 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 3057 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 3058 } 3059 3060 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 3061 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 3062 3063 /* DPPATC */ 3064 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 3065 width = crtc_state->lane_count; 3066 3067 switch (pin_assignment) { 3068 case 0x0: 3069 drm_WARN_ON(&dev_priv->drm, 3070 dig_port->tc_mode != TC_PORT_LEGACY); 3071 if (width == 1) { 3072 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 3073 } else { 3074 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3075 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3076 } 3077 break; 3078 case 0x1: 3079 if (width == 4) { 3080 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3081 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3082 } 3083 break; 3084 case 0x2: 3085 if (width == 2) { 3086 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3087 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3088 } 3089 break; 3090 case 0x3: 3091 case 0x5: 3092 if (width == 1) { 3093 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 3094 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 3095 } else { 3096 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3097 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3098 } 3099 break; 3100 case 0x4: 3101 case 0x6: 3102 if (width == 1) { 3103 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 3104 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 3105 } else { 3106 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3107 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3108 } 3109 break; 3110 default: 3111 MISSING_CASE(pin_assignment); 3112 } 3113 3114 if (INTEL_GEN(dev_priv) >= 12) { 3115 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 3116 HIP_INDEX_VAL(tc_port, 0x0)); 3117 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0); 3118 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 3119 HIP_INDEX_VAL(tc_port, 0x1)); 3120 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1); 3121 } else { 3122 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 3123 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 3124 } 3125 } 3126 3127 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 3128 const struct intel_crtc_state *crtc_state) 3129 { 3130 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3131 3132 if (!crtc_state->fec_enable) 3133 return; 3134 3135 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0) 3136 drm_dbg_kms(&i915->drm, 3137 "Failed to set FEC_READY in the sink\n"); 3138 } 3139 3140 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 3141 const struct intel_crtc_state *crtc_state) 3142 { 3143 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3144 struct intel_dp *intel_dp; 3145 u32 val; 3146 3147 if (!crtc_state->fec_enable) 3148 return; 3149 3150 intel_dp = enc_to_intel_dp(encoder); 3151 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 3152 val |= DP_TP_CTL_FEC_ENABLE; 3153 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val); 3154 3155 if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, 3156 DP_TP_STATUS_FEC_ENABLE_LIVE, 1)) 3157 drm_err(&dev_priv->drm, 3158 "Timed out waiting for FEC Enable Status\n"); 3159 } 3160 3161 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder, 3162 const struct intel_crtc_state *crtc_state) 3163 { 3164 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3165 struct intel_dp *intel_dp; 3166 u32 val; 3167 3168 if (!crtc_state->fec_enable) 3169 return; 3170 3171 intel_dp = enc_to_intel_dp(encoder); 3172 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 3173 val &= ~DP_TP_CTL_FEC_ENABLE; 3174 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val); 3175 intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl); 3176 } 3177 3178 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 3179 struct intel_encoder *encoder, 3180 const struct intel_crtc_state *crtc_state, 3181 const struct drm_connector_state *conn_state) 3182 { 3183 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3184 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3185 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3186 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3187 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 3188 int level = intel_ddi_dp_level(intel_dp); 3189 enum transcoder transcoder = crtc_state->cpu_transcoder; 3190 3191 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, 3192 crtc_state->lane_count, is_mst); 3193 3194 intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder); 3195 intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder); 3196 3197 /* 3198 * 1. Enable Power Wells 3199 * 3200 * This was handled at the beginning of intel_atomic_commit_tail(), 3201 * before we called down into this function. 3202 */ 3203 3204 /* 2. Enable Panel Power if PPS is required */ 3205 intel_edp_panel_on(intel_dp); 3206 3207 /* 3208 * 3. For non-TBT Type-C ports, set FIA lane count 3209 * (DFLEXDPSP.DPX4TXLATC) 3210 * 3211 * This was done before tgl_ddi_pre_enable_dp by 3212 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 3213 */ 3214 3215 /* 3216 * 4. Enable the port PLL. 3217 * 3218 * The PLL enabling itself was already done before this function by 3219 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 3220 * configure the PLL to port mapping here. 3221 */ 3222 intel_ddi_clk_select(encoder, crtc_state); 3223 3224 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 3225 if (!intel_phy_is_tc(dev_priv, phy) || 3226 dig_port->tc_mode != TC_PORT_TBT_ALT) 3227 intel_display_power_get(dev_priv, 3228 dig_port->ddi_io_power_domain); 3229 3230 /* 6. Program DP_MODE */ 3231 icl_program_mg_dp_mode(dig_port, crtc_state); 3232 3233 /* 3234 * 7. The rest of the below are substeps under the bspec's "Enable and 3235 * Train Display Port" step. Note that steps that are specific to 3236 * MST will be handled by intel_mst_pre_enable_dp() before/after it 3237 * calls into this function. Also intel_mst_pre_enable_dp() only calls 3238 * us when active_mst_links==0, so any steps designated for "single 3239 * stream or multi-stream master transcoder" can just be performed 3240 * unconditionally here. 3241 */ 3242 3243 /* 3244 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 3245 * Transcoder. 3246 */ 3247 intel_ddi_enable_pipe_clock(encoder, crtc_state); 3248 3249 /* 3250 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 3251 * Transport Select 3252 */ 3253 intel_ddi_config_transcoder_func(encoder, crtc_state); 3254 3255 /* 3256 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 3257 * selected 3258 * 3259 * This will be handled by the intel_dp_start_link_train() farther 3260 * down this function. 3261 */ 3262 3263 /* 7.e Configure voltage swing and related IO settings */ 3264 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level, 3265 encoder->type); 3266 3267 /* 3268 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 3269 * the used lanes of the DDI. 3270 */ 3271 if (intel_phy_is_combo(dev_priv, phy)) { 3272 bool lane_reversal = 3273 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 3274 3275 intel_combo_phy_power_up_lanes(dev_priv, phy, false, 3276 crtc_state->lane_count, 3277 lane_reversal); 3278 } 3279 3280 /* 3281 * 7.g Configure and enable DDI_BUF_CTL 3282 * 7.h Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout 3283 * after 500 us. 3284 * 3285 * We only configure what the register value will be here. Actual 3286 * enabling happens during link training farther down. 3287 */ 3288 intel_ddi_init_dp_buf_reg(encoder); 3289 3290 if (!is_mst) 3291 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 3292 3293 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); 3294 /* 3295 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 3296 * in the FEC_CONFIGURATION register to 1 before initiating link 3297 * training 3298 */ 3299 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 3300 3301 /* 3302 * 7.i Follow DisplayPort specification training sequence (see notes for 3303 * failure handling) 3304 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 3305 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 3306 * (timeout after 800 us) 3307 */ 3308 intel_dp_start_link_train(intel_dp); 3309 3310 /* 7.k Set DP_TP_CTL link training to Normal */ 3311 if (!is_trans_port_sync_mode(crtc_state)) 3312 intel_dp_stop_link_train(intel_dp); 3313 3314 /* 7.l Configure and enable FEC if needed */ 3315 intel_ddi_enable_fec(encoder, crtc_state); 3316 intel_dsc_enable(encoder, crtc_state); 3317 } 3318 3319 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 3320 struct intel_encoder *encoder, 3321 const struct intel_crtc_state *crtc_state, 3322 const struct drm_connector_state *conn_state) 3323 { 3324 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3325 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3326 enum port port = encoder->port; 3327 enum phy phy = intel_port_to_phy(dev_priv, port); 3328 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3329 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 3330 int level = intel_ddi_dp_level(intel_dp); 3331 3332 if (INTEL_GEN(dev_priv) < 11) 3333 drm_WARN_ON(&dev_priv->drm, 3334 is_mst && (port == PORT_A || port == PORT_E)); 3335 else 3336 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 3337 3338 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, 3339 crtc_state->lane_count, is_mst); 3340 3341 intel_edp_panel_on(intel_dp); 3342 3343 intel_ddi_clk_select(encoder, crtc_state); 3344 3345 if (!intel_phy_is_tc(dev_priv, phy) || 3346 dig_port->tc_mode != TC_PORT_TBT_ALT) 3347 intel_display_power_get(dev_priv, 3348 dig_port->ddi_io_power_domain); 3349 3350 icl_program_mg_dp_mode(dig_port, crtc_state); 3351 3352 if (INTEL_GEN(dev_priv) >= 11) 3353 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, 3354 level, encoder->type); 3355 else if (IS_CANNONLAKE(dev_priv)) 3356 cnl_ddi_vswing_sequence(encoder, level, encoder->type); 3357 else if (IS_GEN9_LP(dev_priv)) 3358 bxt_ddi_vswing_sequence(encoder, level, encoder->type); 3359 else 3360 intel_prepare_dp_ddi_buffers(encoder, crtc_state); 3361 3362 if (intel_phy_is_combo(dev_priv, phy)) { 3363 bool lane_reversal = 3364 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 3365 3366 intel_combo_phy_power_up_lanes(dev_priv, phy, false, 3367 crtc_state->lane_count, 3368 lane_reversal); 3369 } 3370 3371 intel_ddi_init_dp_buf_reg(encoder); 3372 if (!is_mst) 3373 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 3374 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, 3375 true); 3376 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 3377 intel_dp_start_link_train(intel_dp); 3378 if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) && 3379 !is_trans_port_sync_mode(crtc_state)) 3380 intel_dp_stop_link_train(intel_dp); 3381 3382 intel_ddi_enable_fec(encoder, crtc_state); 3383 3384 if (!is_mst) 3385 intel_ddi_enable_pipe_clock(encoder, crtc_state); 3386 3387 intel_dsc_enable(encoder, crtc_state); 3388 } 3389 3390 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 3391 struct intel_encoder *encoder, 3392 const struct intel_crtc_state *crtc_state, 3393 const struct drm_connector_state *conn_state) 3394 { 3395 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3396 3397 if (INTEL_GEN(dev_priv) >= 12) 3398 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 3399 else 3400 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 3401 3402 /* MST will call a setting of MSA after an allocating of Virtual Channel 3403 * from MST encoder pre_enable callback. 3404 */ 3405 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3406 intel_ddi_set_dp_msa(crtc_state, conn_state); 3407 3408 intel_dp_set_m_n(crtc_state, M1_N1); 3409 } 3410 } 3411 3412 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 3413 struct intel_encoder *encoder, 3414 const struct intel_crtc_state *crtc_state, 3415 const struct drm_connector_state *conn_state) 3416 { 3417 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3418 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3419 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3420 int level = intel_ddi_hdmi_level(encoder); 3421 3422 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 3423 intel_ddi_clk_select(encoder, crtc_state); 3424 3425 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); 3426 3427 icl_program_mg_dp_mode(dig_port, crtc_state); 3428 3429 if (INTEL_GEN(dev_priv) >= 12) 3430 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, 3431 level, INTEL_OUTPUT_HDMI); 3432 else if (INTEL_GEN(dev_priv) == 11) 3433 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, 3434 level, INTEL_OUTPUT_HDMI); 3435 else if (IS_CANNONLAKE(dev_priv)) 3436 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI); 3437 else if (IS_GEN9_LP(dev_priv)) 3438 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI); 3439 else 3440 intel_prepare_hdmi_ddi_buffers(encoder, level); 3441 3442 if (IS_GEN9_BC(dev_priv)) 3443 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI); 3444 3445 intel_ddi_enable_pipe_clock(encoder, crtc_state); 3446 3447 dig_port->set_infoframes(encoder, 3448 crtc_state->has_infoframe, 3449 crtc_state, conn_state); 3450 } 3451 3452 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 3453 struct intel_encoder *encoder, 3454 const struct intel_crtc_state *crtc_state, 3455 const struct drm_connector_state *conn_state) 3456 { 3457 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3458 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3459 enum pipe pipe = crtc->pipe; 3460 3461 /* 3462 * When called from DP MST code: 3463 * - conn_state will be NULL 3464 * - encoder will be the main encoder (ie. mst->primary) 3465 * - the main connector associated with this port 3466 * won't be active or linked to a crtc 3467 * - crtc_state will be the state of the first stream to 3468 * be activated on this port, and it may not be the same 3469 * stream that will be deactivated last, but each stream 3470 * should have a state that is identical when it comes to 3471 * the DP link parameteres 3472 */ 3473 3474 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 3475 3476 if (INTEL_GEN(dev_priv) >= 11) 3477 icl_map_plls_to_ports(encoder, crtc_state); 3478 3479 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 3480 3481 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 3482 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 3483 conn_state); 3484 } else { 3485 struct intel_lspcon *lspcon = 3486 enc_to_intel_lspcon(encoder); 3487 3488 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 3489 conn_state); 3490 if (lspcon->active) { 3491 struct intel_digital_port *dig_port = 3492 enc_to_dig_port(encoder); 3493 3494 dig_port->set_infoframes(encoder, 3495 crtc_state->has_infoframe, 3496 crtc_state, conn_state); 3497 } 3498 } 3499 } 3500 3501 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 3502 const struct intel_crtc_state *crtc_state) 3503 { 3504 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3505 enum port port = encoder->port; 3506 bool wait = false; 3507 u32 val; 3508 3509 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3510 if (val & DDI_BUF_CTL_ENABLE) { 3511 val &= ~DDI_BUF_CTL_ENABLE; 3512 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 3513 wait = true; 3514 } 3515 3516 if (intel_crtc_has_dp_encoder(crtc_state)) { 3517 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3518 3519 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 3520 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 3521 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 3522 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val); 3523 } 3524 3525 /* Disable FEC in DP Sink */ 3526 intel_ddi_disable_fec_state(encoder, crtc_state); 3527 3528 if (wait) 3529 intel_wait_ddi_buf_idle(dev_priv, port); 3530 } 3531 3532 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 3533 struct intel_encoder *encoder, 3534 const struct intel_crtc_state *old_crtc_state, 3535 const struct drm_connector_state *old_conn_state) 3536 { 3537 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3538 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3539 struct intel_dp *intel_dp = &dig_port->dp; 3540 bool is_mst = intel_crtc_has_type(old_crtc_state, 3541 INTEL_OUTPUT_DP_MST); 3542 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3543 3544 if (!is_mst) 3545 intel_dp_set_infoframes(encoder, false, 3546 old_crtc_state, old_conn_state); 3547 3548 /* 3549 * Power down sink before disabling the port, otherwise we end 3550 * up getting interrupts from the sink on detecting link loss. 3551 */ 3552 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 3553 3554 if (INTEL_GEN(dev_priv) >= 12) { 3555 if (is_mst) { 3556 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 3557 u32 val; 3558 3559 val = intel_de_read(dev_priv, 3560 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3561 val &= ~(TGL_TRANS_DDI_PORT_MASK | 3562 TRANS_DDI_MODE_SELECT_MASK); 3563 intel_de_write(dev_priv, 3564 TRANS_DDI_FUNC_CTL(cpu_transcoder), 3565 val); 3566 } 3567 } else { 3568 if (!is_mst) 3569 intel_ddi_disable_pipe_clock(old_crtc_state); 3570 } 3571 3572 intel_disable_ddi_buf(encoder, old_crtc_state); 3573 3574 /* 3575 * From TGL spec: "If single stream or multi-stream master transcoder: 3576 * Configure Transcoder Clock select to direct no clock to the 3577 * transcoder" 3578 */ 3579 if (INTEL_GEN(dev_priv) >= 12) 3580 intel_ddi_disable_pipe_clock(old_crtc_state); 3581 3582 intel_edp_panel_vdd_on(intel_dp); 3583 intel_edp_panel_off(intel_dp); 3584 3585 if (!intel_phy_is_tc(dev_priv, phy) || 3586 dig_port->tc_mode != TC_PORT_TBT_ALT) 3587 intel_display_power_put_unchecked(dev_priv, 3588 dig_port->ddi_io_power_domain); 3589 3590 intel_ddi_clk_disable(encoder); 3591 } 3592 3593 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 3594 struct intel_encoder *encoder, 3595 const struct intel_crtc_state *old_crtc_state, 3596 const struct drm_connector_state *old_conn_state) 3597 { 3598 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3599 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3600 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3601 3602 dig_port->set_infoframes(encoder, false, 3603 old_crtc_state, old_conn_state); 3604 3605 intel_ddi_disable_pipe_clock(old_crtc_state); 3606 3607 intel_disable_ddi_buf(encoder, old_crtc_state); 3608 3609 intel_display_power_put_unchecked(dev_priv, 3610 dig_port->ddi_io_power_domain); 3611 3612 intel_ddi_clk_disable(encoder); 3613 3614 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3615 } 3616 3617 static void intel_ddi_post_disable(struct intel_atomic_state *state, 3618 struct intel_encoder *encoder, 3619 const struct intel_crtc_state *old_crtc_state, 3620 const struct drm_connector_state *old_conn_state) 3621 { 3622 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3623 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3624 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3625 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 3626 3627 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) { 3628 intel_crtc_vblank_off(old_crtc_state); 3629 3630 intel_disable_pipe(old_crtc_state); 3631 3632 intel_ddi_disable_transcoder_func(old_crtc_state); 3633 3634 intel_dsc_disable(old_crtc_state); 3635 3636 if (INTEL_GEN(dev_priv) >= 9) 3637 skl_scaler_disable(old_crtc_state); 3638 else 3639 ilk_pfit_disable(old_crtc_state); 3640 } 3641 3642 /* 3643 * When called from DP MST code: 3644 * - old_conn_state will be NULL 3645 * - encoder will be the main encoder (ie. mst->primary) 3646 * - the main connector associated with this port 3647 * won't be active or linked to a crtc 3648 * - old_crtc_state will be the state of the last stream to 3649 * be deactivated on this port, and it may not be the same 3650 * stream that was activated last, but each stream 3651 * should have a state that is identical when it comes to 3652 * the DP link parameteres 3653 */ 3654 3655 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3656 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 3657 old_conn_state); 3658 else 3659 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 3660 old_conn_state); 3661 3662 if (INTEL_GEN(dev_priv) >= 11) 3663 icl_unmap_plls_to_ports(encoder); 3664 3665 if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port) 3666 intel_display_power_put_unchecked(dev_priv, 3667 intel_ddi_main_link_aux_domain(dig_port)); 3668 3669 if (is_tc_port) 3670 intel_tc_port_put_link(dig_port); 3671 } 3672 3673 void intel_ddi_fdi_post_disable(struct intel_atomic_state *state, 3674 struct intel_encoder *encoder, 3675 const struct intel_crtc_state *old_crtc_state, 3676 const struct drm_connector_state *old_conn_state) 3677 { 3678 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3679 u32 val; 3680 3681 /* 3682 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable) 3683 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN, 3684 * step 13 is the correct place for it. Step 18 is where it was 3685 * originally before the BUN. 3686 */ 3687 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 3688 val &= ~FDI_RX_ENABLE; 3689 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 3690 3691 intel_disable_ddi_buf(encoder, old_crtc_state); 3692 intel_ddi_clk_disable(encoder); 3693 3694 val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); 3695 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 3696 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 3697 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val); 3698 3699 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 3700 val &= ~FDI_PCDCLK; 3701 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 3702 3703 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 3704 val &= ~FDI_RX_PLL_ENABLE; 3705 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 3706 } 3707 3708 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 3709 struct intel_encoder *encoder, 3710 const struct intel_crtc_state *crtc_state) 3711 { 3712 const struct drm_connector_state *conn_state; 3713 struct drm_connector *conn; 3714 int i; 3715 3716 if (!crtc_state->sync_mode_slaves_mask) 3717 return; 3718 3719 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 3720 struct intel_encoder *slave_encoder = 3721 to_intel_encoder(conn_state->best_encoder); 3722 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 3723 const struct intel_crtc_state *slave_crtc_state; 3724 3725 if (!slave_crtc) 3726 continue; 3727 3728 slave_crtc_state = 3729 intel_atomic_get_new_crtc_state(state, slave_crtc); 3730 3731 if (slave_crtc_state->master_transcoder != 3732 crtc_state->cpu_transcoder) 3733 continue; 3734 3735 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder)); 3736 } 3737 3738 usleep_range(200, 400); 3739 3740 intel_dp_stop_link_train(enc_to_intel_dp(encoder)); 3741 } 3742 3743 static void intel_enable_ddi_dp(struct intel_atomic_state *state, 3744 struct intel_encoder *encoder, 3745 const struct intel_crtc_state *crtc_state, 3746 const struct drm_connector_state *conn_state) 3747 { 3748 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3749 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3750 enum port port = encoder->port; 3751 3752 if (port == PORT_A && INTEL_GEN(dev_priv) < 9) 3753 intel_dp_stop_link_train(intel_dp); 3754 3755 intel_edp_backlight_on(crtc_state, conn_state); 3756 intel_psr_enable(intel_dp, crtc_state, conn_state); 3757 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3758 intel_edp_drrs_enable(intel_dp, crtc_state); 3759 3760 if (crtc_state->has_audio) 3761 intel_audio_codec_enable(encoder, crtc_state, conn_state); 3762 3763 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3764 } 3765 3766 static i915_reg_t 3767 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 3768 enum port port) 3769 { 3770 static const enum transcoder trans[] = { 3771 [PORT_A] = TRANSCODER_EDP, 3772 [PORT_B] = TRANSCODER_A, 3773 [PORT_C] = TRANSCODER_B, 3774 [PORT_D] = TRANSCODER_C, 3775 [PORT_E] = TRANSCODER_A, 3776 }; 3777 3778 drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) < 9); 3779 3780 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) 3781 port = PORT_A; 3782 3783 return CHICKEN_TRANS(trans[port]); 3784 } 3785 3786 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, 3787 struct intel_encoder *encoder, 3788 const struct intel_crtc_state *crtc_state, 3789 const struct drm_connector_state *conn_state) 3790 { 3791 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3792 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3793 struct drm_connector *connector = conn_state->connector; 3794 enum port port = encoder->port; 3795 3796 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3797 crtc_state->hdmi_high_tmds_clock_ratio, 3798 crtc_state->hdmi_scrambling)) 3799 drm_dbg_kms(&dev_priv->drm, 3800 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3801 connector->base.id, connector->name); 3802 3803 /* Display WA #1143: skl,kbl,cfl */ 3804 if (IS_GEN9_BC(dev_priv)) { 3805 /* 3806 * For some reason these chicken bits have been 3807 * stuffed into a transcoder register, event though 3808 * the bits affect a specific DDI port rather than 3809 * a specific transcoder. 3810 */ 3811 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 3812 u32 val; 3813 3814 val = intel_de_read(dev_priv, reg); 3815 3816 if (port == PORT_E) 3817 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3818 DDIE_TRAINING_OVERRIDE_VALUE; 3819 else 3820 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3821 DDI_TRAINING_OVERRIDE_VALUE; 3822 3823 intel_de_write(dev_priv, reg, val); 3824 intel_de_posting_read(dev_priv, reg); 3825 3826 udelay(1); 3827 3828 if (port == PORT_E) 3829 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3830 DDIE_TRAINING_OVERRIDE_VALUE); 3831 else 3832 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3833 DDI_TRAINING_OVERRIDE_VALUE); 3834 3835 intel_de_write(dev_priv, reg, val); 3836 } 3837 3838 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3839 * are ignored so nothing special needs to be done besides 3840 * enabling the port. 3841 */ 3842 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3843 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE); 3844 3845 if (crtc_state->has_audio) 3846 intel_audio_codec_enable(encoder, crtc_state, conn_state); 3847 } 3848 3849 static void intel_enable_ddi(struct intel_atomic_state *state, 3850 struct intel_encoder *encoder, 3851 const struct intel_crtc_state *crtc_state, 3852 const struct drm_connector_state *conn_state) 3853 { 3854 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 3855 3856 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3857 3858 intel_enable_pipe(crtc_state); 3859 3860 intel_crtc_vblank_on(crtc_state); 3861 3862 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3863 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state); 3864 else 3865 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state); 3866 3867 /* Enable hdcp if it's desired */ 3868 if (conn_state->content_protection == 3869 DRM_MODE_CONTENT_PROTECTION_DESIRED) 3870 intel_hdcp_enable(to_intel_connector(conn_state->connector), 3871 crtc_state->cpu_transcoder, 3872 (u8)conn_state->hdcp_content_type); 3873 } 3874 3875 static void intel_disable_ddi_dp(struct intel_atomic_state *state, 3876 struct intel_encoder *encoder, 3877 const struct intel_crtc_state *old_crtc_state, 3878 const struct drm_connector_state *old_conn_state) 3879 { 3880 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3881 3882 intel_dp->link_trained = false; 3883 3884 if (old_crtc_state->has_audio) 3885 intel_audio_codec_disable(encoder, 3886 old_crtc_state, old_conn_state); 3887 3888 intel_edp_drrs_disable(intel_dp, old_crtc_state); 3889 intel_psr_disable(intel_dp, old_crtc_state); 3890 intel_edp_backlight_off(old_conn_state); 3891 /* Disable the decompression in DP Sink */ 3892 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, 3893 false); 3894 } 3895 3896 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state, 3897 struct intel_encoder *encoder, 3898 const struct intel_crtc_state *old_crtc_state, 3899 const struct drm_connector_state *old_conn_state) 3900 { 3901 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3902 struct drm_connector *connector = old_conn_state->connector; 3903 3904 if (old_crtc_state->has_audio) 3905 intel_audio_codec_disable(encoder, 3906 old_crtc_state, old_conn_state); 3907 3908 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3909 false, false)) 3910 drm_dbg_kms(&i915->drm, 3911 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3912 connector->base.id, connector->name); 3913 } 3914 3915 static void intel_disable_ddi(struct intel_atomic_state *state, 3916 struct intel_encoder *encoder, 3917 const struct intel_crtc_state *old_crtc_state, 3918 const struct drm_connector_state *old_conn_state) 3919 { 3920 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3921 3922 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3923 intel_disable_ddi_hdmi(state, encoder, old_crtc_state, 3924 old_conn_state); 3925 else 3926 intel_disable_ddi_dp(state, encoder, old_crtc_state, 3927 old_conn_state); 3928 } 3929 3930 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3931 struct intel_encoder *encoder, 3932 const struct intel_crtc_state *crtc_state, 3933 const struct drm_connector_state *conn_state) 3934 { 3935 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3936 3937 intel_ddi_set_dp_msa(crtc_state, conn_state); 3938 3939 intel_psr_update(intel_dp, crtc_state, conn_state); 3940 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3941 intel_edp_drrs_enable(intel_dp, crtc_state); 3942 3943 intel_panel_update_backlight(state, encoder, crtc_state, conn_state); 3944 } 3945 3946 static void intel_ddi_update_pipe(struct intel_atomic_state *state, 3947 struct intel_encoder *encoder, 3948 const struct intel_crtc_state *crtc_state, 3949 const struct drm_connector_state *conn_state) 3950 { 3951 3952 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3953 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3954 conn_state); 3955 3956 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3957 } 3958 3959 static void 3960 intel_ddi_update_prepare(struct intel_atomic_state *state, 3961 struct intel_encoder *encoder, 3962 struct intel_crtc *crtc) 3963 { 3964 struct intel_crtc_state *crtc_state = 3965 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL; 3966 int required_lanes = crtc_state ? crtc_state->lane_count : 1; 3967 3968 drm_WARN_ON(state->base.dev, crtc && crtc->active); 3969 3970 intel_tc_port_get_link(enc_to_dig_port(encoder), 3971 required_lanes); 3972 if (crtc_state && crtc_state->hw.active) 3973 intel_update_active_dpll(state, crtc, encoder); 3974 } 3975 3976 static void 3977 intel_ddi_update_complete(struct intel_atomic_state *state, 3978 struct intel_encoder *encoder, 3979 struct intel_crtc *crtc) 3980 { 3981 intel_tc_port_put_link(enc_to_dig_port(encoder)); 3982 } 3983 3984 static void 3985 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3986 struct intel_encoder *encoder, 3987 const struct intel_crtc_state *crtc_state, 3988 const struct drm_connector_state *conn_state) 3989 { 3990 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3991 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3992 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3993 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 3994 3995 if (is_tc_port) 3996 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3997 3998 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) 3999 intel_display_power_get(dev_priv, 4000 intel_ddi_main_link_aux_domain(dig_port)); 4001 4002 if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT) 4003 /* 4004 * Program the lane count for static/dynamic connections on 4005 * Type-C ports. Skip this step for TBT. 4006 */ 4007 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 4008 else if (IS_GEN9_LP(dev_priv)) 4009 bxt_ddi_phy_set_lane_optim_mask(encoder, 4010 crtc_state->lane_lat_optim_mask); 4011 } 4012 4013 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) 4014 { 4015 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4016 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4017 enum port port = dig_port->base.port; 4018 u32 dp_tp_ctl, ddi_buf_ctl; 4019 bool wait = false; 4020 4021 dp_tp_ctl = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 4022 4023 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 4024 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 4025 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 4026 intel_de_write(dev_priv, DDI_BUF_CTL(port), 4027 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 4028 wait = true; 4029 } 4030 4031 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 4032 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1; 4033 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl); 4034 intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl); 4035 4036 if (wait) 4037 intel_wait_ddi_buf_idle(dev_priv, port); 4038 } 4039 4040 dp_tp_ctl = DP_TP_CTL_ENABLE | 4041 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; 4042 if (intel_dp->link_mst) 4043 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 4044 else { 4045 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 4046 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 4047 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4048 } 4049 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl); 4050 intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl); 4051 4052 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 4053 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 4054 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 4055 4056 intel_wait_ddi_buf_active(dev_priv, port); 4057 } 4058 4059 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 4060 u8 dp_train_pat) 4061 { 4062 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 4063 u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd); 4064 enum port port = dp_to_dig_port(intel_dp)->base.port; 4065 u32 temp; 4066 4067 temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 4068 4069 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) 4070 temp |= DP_TP_CTL_SCRAMBLE_DISABLE; 4071 else 4072 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; 4073 4074 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 4075 switch (dp_train_pat & train_pat_mask) { 4076 case DP_TRAINING_PATTERN_DISABLE: 4077 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 4078 break; 4079 case DP_TRAINING_PATTERN_1: 4080 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 4081 break; 4082 case DP_TRAINING_PATTERN_2: 4083 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 4084 break; 4085 case DP_TRAINING_PATTERN_3: 4086 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 4087 break; 4088 case DP_TRAINING_PATTERN_4: 4089 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 4090 break; 4091 } 4092 4093 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, temp); 4094 4095 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 4096 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 4097 } 4098 4099 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp) 4100 { 4101 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 4102 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4103 enum port port = encoder->port; 4104 u32 val; 4105 4106 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 4107 val &= ~DP_TP_CTL_LINK_TRAIN_MASK; 4108 val |= DP_TP_CTL_LINK_TRAIN_IDLE; 4109 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val); 4110 4111 /* 4112 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 4113 * reason we need to set idle transmission mode is to work around a HW 4114 * issue where we enable the pipe while not in idle link-training mode. 4115 * In this case there is requirement to wait for a minimum number of 4116 * idle patterns to be sent. 4117 */ 4118 if (port == PORT_A && INTEL_GEN(dev_priv) < 12) 4119 return; 4120 4121 if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, 4122 DP_TP_STATUS_IDLE_DONE, 1)) 4123 drm_err(&dev_priv->drm, 4124 "Timed out waiting for DP idle patterns\n"); 4125 } 4126 4127 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 4128 enum transcoder cpu_transcoder) 4129 { 4130 if (cpu_transcoder == TRANSCODER_EDP) 4131 return false; 4132 4133 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) 4134 return false; 4135 4136 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 4137 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 4138 } 4139 4140 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, 4141 struct intel_crtc_state *crtc_state) 4142 { 4143 if (INTEL_GEN(dev_priv) >= 12 && crtc_state->port_clock > 594000) 4144 crtc_state->min_voltage_level = 2; 4145 else if (IS_ELKHARTLAKE(dev_priv) && crtc_state->port_clock > 594000) 4146 crtc_state->min_voltage_level = 3; 4147 else if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000) 4148 crtc_state->min_voltage_level = 1; 4149 else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000) 4150 crtc_state->min_voltage_level = 2; 4151 } 4152 4153 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, 4154 enum transcoder cpu_transcoder) 4155 { 4156 u32 master_select; 4157 4158 if (INTEL_GEN(dev_priv) >= 11) { 4159 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder)); 4160 4161 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 4162 return INVALID_TRANSCODER; 4163 4164 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 4165 } else { 4166 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 4167 4168 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 4169 return INVALID_TRANSCODER; 4170 4171 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 4172 } 4173 4174 if (master_select == 0) 4175 return TRANSCODER_EDP; 4176 else 4177 return master_select - 1; 4178 } 4179 4180 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 4181 { 4182 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 4183 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 4184 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 4185 enum transcoder cpu_transcoder; 4186 4187 crtc_state->master_transcoder = 4188 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); 4189 4190 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { 4191 enum intel_display_power_domain power_domain; 4192 intel_wakeref_t trans_wakeref; 4193 4194 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 4195 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 4196 power_domain); 4197 4198 if (!trans_wakeref) 4199 continue; 4200 4201 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == 4202 crtc_state->cpu_transcoder) 4203 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 4204 4205 intel_display_power_put(dev_priv, power_domain, trans_wakeref); 4206 } 4207 4208 drm_WARN_ON(&dev_priv->drm, 4209 crtc_state->master_transcoder != INVALID_TRANSCODER && 4210 crtc_state->sync_mode_slaves_mask); 4211 } 4212 4213 void intel_ddi_get_config(struct intel_encoder *encoder, 4214 struct intel_crtc_state *pipe_config) 4215 { 4216 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4217 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); 4218 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4219 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4220 u32 temp, flags = 0; 4221 4222 /* XXX: DSI transcoder paranoia */ 4223 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 4224 return; 4225 4226 intel_dsc_get_config(encoder, pipe_config); 4227 4228 temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 4229 if (temp & TRANS_DDI_PHSYNC) 4230 flags |= DRM_MODE_FLAG_PHSYNC; 4231 else 4232 flags |= DRM_MODE_FLAG_NHSYNC; 4233 if (temp & TRANS_DDI_PVSYNC) 4234 flags |= DRM_MODE_FLAG_PVSYNC; 4235 else 4236 flags |= DRM_MODE_FLAG_NVSYNC; 4237 4238 pipe_config->hw.adjusted_mode.flags |= flags; 4239 4240 switch (temp & TRANS_DDI_BPC_MASK) { 4241 case TRANS_DDI_BPC_6: 4242 pipe_config->pipe_bpp = 18; 4243 break; 4244 case TRANS_DDI_BPC_8: 4245 pipe_config->pipe_bpp = 24; 4246 break; 4247 case TRANS_DDI_BPC_10: 4248 pipe_config->pipe_bpp = 30; 4249 break; 4250 case TRANS_DDI_BPC_12: 4251 pipe_config->pipe_bpp = 36; 4252 break; 4253 default: 4254 break; 4255 } 4256 4257 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 4258 case TRANS_DDI_MODE_SELECT_HDMI: 4259 pipe_config->has_hdmi_sink = true; 4260 4261 pipe_config->infoframes.enable |= 4262 intel_hdmi_infoframes_enabled(encoder, pipe_config); 4263 4264 if (pipe_config->infoframes.enable) 4265 pipe_config->has_infoframe = true; 4266 4267 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 4268 pipe_config->hdmi_scrambling = true; 4269 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 4270 pipe_config->hdmi_high_tmds_clock_ratio = true; 4271 fallthrough; 4272 case TRANS_DDI_MODE_SELECT_DVI: 4273 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 4274 pipe_config->lane_count = 4; 4275 break; 4276 case TRANS_DDI_MODE_SELECT_FDI: 4277 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 4278 break; 4279 case TRANS_DDI_MODE_SELECT_DP_SST: 4280 if (encoder->type == INTEL_OUTPUT_EDP) 4281 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 4282 else 4283 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 4284 pipe_config->lane_count = 4285 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4286 intel_dp_get_m_n(intel_crtc, pipe_config); 4287 4288 if (INTEL_GEN(dev_priv) >= 11) { 4289 i915_reg_t dp_tp_ctl; 4290 4291 if (IS_GEN(dev_priv, 11)) 4292 dp_tp_ctl = DP_TP_CTL(encoder->port); 4293 else 4294 dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder); 4295 4296 pipe_config->fec_enable = 4297 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE; 4298 4299 drm_dbg_kms(&dev_priv->drm, 4300 "[ENCODER:%d:%s] Fec status: %u\n", 4301 encoder->base.base.id, encoder->base.name, 4302 pipe_config->fec_enable); 4303 } 4304 4305 pipe_config->infoframes.enable |= 4306 intel_hdmi_infoframes_enabled(encoder, pipe_config); 4307 4308 break; 4309 case TRANS_DDI_MODE_SELECT_DP_MST: 4310 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 4311 pipe_config->lane_count = 4312 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4313 4314 if (INTEL_GEN(dev_priv) >= 12) 4315 pipe_config->mst_master_transcoder = 4316 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); 4317 4318 intel_dp_get_m_n(intel_crtc, pipe_config); 4319 4320 pipe_config->infoframes.enable |= 4321 intel_hdmi_infoframes_enabled(encoder, pipe_config); 4322 break; 4323 default: 4324 break; 4325 } 4326 4327 if (INTEL_GEN(dev_priv) >= 12) { 4328 enum transcoder transcoder = 4329 intel_dp_mst_is_slave_trans(pipe_config) ? 4330 pipe_config->mst_master_transcoder : 4331 pipe_config->cpu_transcoder; 4332 4333 intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder); 4334 intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder); 4335 } 4336 4337 pipe_config->has_audio = 4338 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 4339 4340 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp && 4341 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { 4342 /* 4343 * This is a big fat ugly hack. 4344 * 4345 * Some machines in UEFI boot mode provide us a VBT that has 18 4346 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 4347 * unknown we fail to light up. Yet the same BIOS boots up with 4348 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 4349 * max, not what it tells us to use. 4350 * 4351 * Note: This will still be broken if the eDP panel is not lit 4352 * up by the BIOS, and thus we can't get the mode at module 4353 * load. 4354 */ 4355 drm_dbg_kms(&dev_priv->drm, 4356 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 4357 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); 4358 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; 4359 } 4360 4361 intel_ddi_clock_get(encoder, pipe_config); 4362 4363 if (IS_GEN9_LP(dev_priv)) 4364 pipe_config->lane_lat_optim_mask = 4365 bxt_ddi_phy_get_lane_lat_optim_mask(encoder); 4366 4367 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 4368 4369 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 4370 4371 intel_read_infoframe(encoder, pipe_config, 4372 HDMI_INFOFRAME_TYPE_AVI, 4373 &pipe_config->infoframes.avi); 4374 intel_read_infoframe(encoder, pipe_config, 4375 HDMI_INFOFRAME_TYPE_SPD, 4376 &pipe_config->infoframes.spd); 4377 intel_read_infoframe(encoder, pipe_config, 4378 HDMI_INFOFRAME_TYPE_VENDOR, 4379 &pipe_config->infoframes.hdmi); 4380 intel_read_infoframe(encoder, pipe_config, 4381 HDMI_INFOFRAME_TYPE_DRM, 4382 &pipe_config->infoframes.drm); 4383 4384 if (INTEL_GEN(dev_priv) >= 8) 4385 bdw_get_trans_port_sync_config(pipe_config); 4386 4387 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 4388 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 4389 } 4390 4391 static enum intel_output_type 4392 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4393 struct intel_crtc_state *crtc_state, 4394 struct drm_connector_state *conn_state) 4395 { 4396 switch (conn_state->connector->connector_type) { 4397 case DRM_MODE_CONNECTOR_HDMIA: 4398 return INTEL_OUTPUT_HDMI; 4399 case DRM_MODE_CONNECTOR_eDP: 4400 return INTEL_OUTPUT_EDP; 4401 case DRM_MODE_CONNECTOR_DisplayPort: 4402 return INTEL_OUTPUT_DP; 4403 default: 4404 MISSING_CASE(conn_state->connector->connector_type); 4405 return INTEL_OUTPUT_UNUSED; 4406 } 4407 } 4408 4409 static int intel_ddi_compute_config(struct intel_encoder *encoder, 4410 struct intel_crtc_state *pipe_config, 4411 struct drm_connector_state *conn_state) 4412 { 4413 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4414 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4415 enum port port = encoder->port; 4416 int ret; 4417 4418 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 4419 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4420 4421 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4422 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4423 } else { 4424 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 4425 } 4426 4427 if (ret) 4428 return ret; 4429 4430 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 4431 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4432 pipe_config->pch_pfit.force_thru = 4433 pipe_config->pch_pfit.enabled || 4434 pipe_config->crc_enabled; 4435 4436 if (IS_GEN9_LP(dev_priv)) 4437 pipe_config->lane_lat_optim_mask = 4438 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4439 4440 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 4441 4442 return 0; 4443 } 4444 4445 static bool mode_equal(const struct drm_display_mode *mode1, 4446 const struct drm_display_mode *mode2) 4447 { 4448 return drm_mode_match(mode1, mode2, 4449 DRM_MODE_MATCH_TIMINGS | 4450 DRM_MODE_MATCH_FLAGS | 4451 DRM_MODE_MATCH_3D_FLAGS) && 4452 mode1->clock == mode2->clock; /* we want an exact match */ 4453 } 4454 4455 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 4456 const struct intel_link_m_n *m_n_2) 4457 { 4458 return m_n_1->tu == m_n_2->tu && 4459 m_n_1->gmch_m == m_n_2->gmch_m && 4460 m_n_1->gmch_n == m_n_2->gmch_n && 4461 m_n_1->link_m == m_n_2->link_m && 4462 m_n_1->link_n == m_n_2->link_n; 4463 } 4464 4465 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 4466 const struct intel_crtc_state *crtc_state2) 4467 { 4468 return crtc_state1->hw.active && crtc_state2->hw.active && 4469 crtc_state1->output_types == crtc_state2->output_types && 4470 crtc_state1->output_format == crtc_state2->output_format && 4471 crtc_state1->lane_count == crtc_state2->lane_count && 4472 crtc_state1->port_clock == crtc_state2->port_clock && 4473 mode_equal(&crtc_state1->hw.adjusted_mode, 4474 &crtc_state2->hw.adjusted_mode) && 4475 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 4476 } 4477 4478 static u8 4479 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4480 int tile_group_id) 4481 { 4482 struct drm_connector *connector; 4483 const struct drm_connector_state *conn_state; 4484 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 4485 struct intel_atomic_state *state = 4486 to_intel_atomic_state(ref_crtc_state->uapi.state); 4487 u8 transcoders = 0; 4488 int i; 4489 4490 /* 4491 * We don't enable port sync on BDW due to missing w/as and 4492 * due to not having adjusted the modeset sequence appropriately. 4493 */ 4494 if (INTEL_GEN(dev_priv) < 9) 4495 return 0; 4496 4497 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4498 return 0; 4499 4500 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4501 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4502 const struct intel_crtc_state *crtc_state; 4503 4504 if (!crtc) 4505 continue; 4506 4507 if (!connector->has_tile || 4508 connector->tile_group->id != 4509 tile_group_id) 4510 continue; 4511 crtc_state = intel_atomic_get_new_crtc_state(state, 4512 crtc); 4513 if (!crtcs_port_sync_compatible(ref_crtc_state, 4514 crtc_state)) 4515 continue; 4516 transcoders |= BIT(crtc_state->cpu_transcoder); 4517 } 4518 4519 return transcoders; 4520 } 4521 4522 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 4523 struct intel_crtc_state *crtc_state, 4524 struct drm_connector_state *conn_state) 4525 { 4526 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4527 struct drm_connector *connector = conn_state->connector; 4528 u8 port_sync_transcoders = 0; 4529 4530 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]", 4531 encoder->base.base.id, encoder->base.name, 4532 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4533 4534 if (connector->has_tile) 4535 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4536 connector->tile_group->id); 4537 4538 /* 4539 * EDP Transcoders cannot be ensalved 4540 * make them a master always when present 4541 */ 4542 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4543 crtc_state->master_transcoder = TRANSCODER_EDP; 4544 else 4545 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4546 4547 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4548 crtc_state->master_transcoder = INVALID_TRANSCODER; 4549 crtc_state->sync_mode_slaves_mask = 4550 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4551 } 4552 4553 return 0; 4554 } 4555 4556 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4557 { 4558 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4559 4560 intel_dp_encoder_flush_work(encoder); 4561 4562 drm_encoder_cleanup(encoder); 4563 kfree(dig_port); 4564 } 4565 4566 static const struct drm_encoder_funcs intel_ddi_funcs = { 4567 .reset = intel_dp_encoder_reset, 4568 .destroy = intel_ddi_encoder_destroy, 4569 }; 4570 4571 static struct intel_connector * 4572 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 4573 { 4574 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4575 struct intel_connector *connector; 4576 enum port port = dig_port->base.port; 4577 4578 connector = intel_connector_alloc(); 4579 if (!connector) 4580 return NULL; 4581 4582 dig_port->dp.output_reg = DDI_BUF_CTL(port); 4583 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 4584 dig_port->dp.set_link_train = intel_ddi_set_link_train; 4585 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4586 4587 if (INTEL_GEN(dev_priv) >= 12) 4588 dig_port->dp.set_signal_levels = tgl_set_signal_levels; 4589 else if (INTEL_GEN(dev_priv) >= 11) 4590 dig_port->dp.set_signal_levels = icl_set_signal_levels; 4591 else if (IS_CANNONLAKE(dev_priv)) 4592 dig_port->dp.set_signal_levels = cnl_set_signal_levels; 4593 else if (IS_GEN9_LP(dev_priv)) 4594 dig_port->dp.set_signal_levels = bxt_set_signal_levels; 4595 else 4596 dig_port->dp.set_signal_levels = hsw_set_signal_levels; 4597 4598 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 4599 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 4600 4601 if (INTEL_GEN(dev_priv) < 12) { 4602 dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port); 4603 dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port); 4604 } 4605 4606 if (!intel_dp_init_connector(dig_port, connector)) { 4607 kfree(connector); 4608 return NULL; 4609 } 4610 4611 return connector; 4612 } 4613 4614 static int modeset_pipe(struct drm_crtc *crtc, 4615 struct drm_modeset_acquire_ctx *ctx) 4616 { 4617 struct drm_atomic_state *state; 4618 struct drm_crtc_state *crtc_state; 4619 int ret; 4620 4621 state = drm_atomic_state_alloc(crtc->dev); 4622 if (!state) 4623 return -ENOMEM; 4624 4625 state->acquire_ctx = ctx; 4626 4627 crtc_state = drm_atomic_get_crtc_state(state, crtc); 4628 if (IS_ERR(crtc_state)) { 4629 ret = PTR_ERR(crtc_state); 4630 goto out; 4631 } 4632 4633 crtc_state->connectors_changed = true; 4634 4635 ret = drm_atomic_commit(state); 4636 out: 4637 drm_atomic_state_put(state); 4638 4639 return ret; 4640 } 4641 4642 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4643 struct drm_modeset_acquire_ctx *ctx) 4644 { 4645 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4646 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4647 struct intel_connector *connector = hdmi->attached_connector; 4648 struct i2c_adapter *adapter = 4649 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 4650 struct drm_connector_state *conn_state; 4651 struct intel_crtc_state *crtc_state; 4652 struct intel_crtc *crtc; 4653 u8 config; 4654 int ret; 4655 4656 if (!connector || connector->base.status != connector_status_connected) 4657 return 0; 4658 4659 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 4660 ctx); 4661 if (ret) 4662 return ret; 4663 4664 conn_state = connector->base.state; 4665 4666 crtc = to_intel_crtc(conn_state->crtc); 4667 if (!crtc) 4668 return 0; 4669 4670 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4671 if (ret) 4672 return ret; 4673 4674 crtc_state = to_intel_crtc_state(crtc->base.state); 4675 4676 drm_WARN_ON(&dev_priv->drm, 4677 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4678 4679 if (!crtc_state->hw.active) 4680 return 0; 4681 4682 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4683 !crtc_state->hdmi_scrambling) 4684 return 0; 4685 4686 if (conn_state->commit && 4687 !try_wait_for_completion(&conn_state->commit->hw_done)) 4688 return 0; 4689 4690 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 4691 if (ret < 0) { 4692 drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n", 4693 ret); 4694 return 0; 4695 } 4696 4697 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4698 crtc_state->hdmi_high_tmds_clock_ratio && 4699 !!(config & SCDC_SCRAMBLING_ENABLE) == 4700 crtc_state->hdmi_scrambling) 4701 return 0; 4702 4703 /* 4704 * HDMI 2.0 says that one should not send scrambled data 4705 * prior to configuring the sink scrambling, and that 4706 * TMDS clock/data transmission should be suspended when 4707 * changing the TMDS clock rate in the sink. So let's 4708 * just do a full modeset here, even though some sinks 4709 * would be perfectly happy if were to just reconfigure 4710 * the SCDC settings on the fly. 4711 */ 4712 return modeset_pipe(&crtc->base, ctx); 4713 } 4714 4715 static enum intel_hotplug_state 4716 intel_ddi_hotplug(struct intel_encoder *encoder, 4717 struct intel_connector *connector) 4718 { 4719 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4720 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4721 enum phy phy = intel_port_to_phy(i915, encoder->port); 4722 bool is_tc = intel_phy_is_tc(i915, phy); 4723 struct drm_modeset_acquire_ctx ctx; 4724 enum intel_hotplug_state state; 4725 int ret; 4726 4727 state = intel_encoder_hotplug(encoder, connector); 4728 4729 drm_modeset_acquire_init(&ctx, 0); 4730 4731 for (;;) { 4732 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) 4733 ret = intel_hdmi_reset_link(encoder, &ctx); 4734 else 4735 ret = intel_dp_retrain_link(encoder, &ctx); 4736 4737 if (ret == -EDEADLK) { 4738 drm_modeset_backoff(&ctx); 4739 continue; 4740 } 4741 4742 break; 4743 } 4744 4745 drm_modeset_drop_locks(&ctx); 4746 drm_modeset_acquire_fini(&ctx); 4747 drm_WARN(encoder->base.dev, ret, 4748 "Acquiring modeset locks failed with %i\n", ret); 4749 4750 /* 4751 * Unpowered type-c dongles can take some time to boot and be 4752 * responsible, so here giving some time to those dongles to power up 4753 * and then retrying the probe. 4754 * 4755 * On many platforms the HDMI live state signal is known to be 4756 * unreliable, so we can't use it to detect if a sink is connected or 4757 * not. Instead we detect if it's connected based on whether we can 4758 * read the EDID or not. That in turn has a problem during disconnect, 4759 * since the HPD interrupt may be raised before the DDC lines get 4760 * disconnected (due to how the required length of DDC vs. HPD 4761 * connector pins are specified) and so we'll still be able to get a 4762 * valid EDID. To solve this schedule another detection cycle if this 4763 * time around we didn't detect any change in the sink's connection 4764 * status. 4765 * 4766 * Type-c connectors which get their HPD signal deasserted then 4767 * reasserted, without unplugging/replugging the sink from the 4768 * connector, introduce a delay until the AUX channel communication 4769 * becomes functional. Retry the detection for 5 seconds on type-c 4770 * connectors to account for this delay. 4771 */ 4772 if (state == INTEL_HOTPLUG_UNCHANGED && 4773 connector->hotplug_retries < (is_tc ? 5 : 1) && 4774 !dig_port->dp.is_mst) 4775 state = INTEL_HOTPLUG_RETRY; 4776 4777 return state; 4778 } 4779 4780 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4781 { 4782 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4783 u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin]; 4784 4785 return intel_de_read(dev_priv, SDEISR) & bit; 4786 } 4787 4788 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4789 { 4790 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4791 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; 4792 4793 return intel_de_read(dev_priv, DEISR) & bit; 4794 } 4795 4796 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4797 { 4798 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4799 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; 4800 4801 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; 4802 } 4803 4804 static struct intel_connector * 4805 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4806 { 4807 struct intel_connector *connector; 4808 enum port port = dig_port->base.port; 4809 4810 connector = intel_connector_alloc(); 4811 if (!connector) 4812 return NULL; 4813 4814 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4815 intel_hdmi_init_connector(dig_port, connector); 4816 4817 return connector; 4818 } 4819 4820 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4821 { 4822 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4823 4824 if (dig_port->base.port != PORT_A) 4825 return false; 4826 4827 if (dig_port->saved_port_bits & DDI_A_4_LANES) 4828 return false; 4829 4830 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4831 * supported configuration 4832 */ 4833 if (IS_GEN9_LP(dev_priv)) 4834 return true; 4835 4836 /* Cannonlake: Most of SKUs don't support DDI_E, and the only 4837 * one who does also have a full A/E split called 4838 * DDI_F what makes DDI_E useless. However for this 4839 * case let's trust VBT info. 4840 */ 4841 if (IS_CANNONLAKE(dev_priv) && 4842 !intel_bios_is_port_present(dev_priv, PORT_E)) 4843 return true; 4844 4845 return false; 4846 } 4847 4848 static int 4849 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4850 { 4851 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4852 enum port port = dig_port->base.port; 4853 int max_lanes = 4; 4854 4855 if (INTEL_GEN(dev_priv) >= 11) 4856 return max_lanes; 4857 4858 if (port == PORT_A || port == PORT_E) { 4859 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4860 max_lanes = port == PORT_A ? 4 : 0; 4861 else 4862 /* Both A and E share 2 lanes */ 4863 max_lanes = 2; 4864 } 4865 4866 /* 4867 * Some BIOS might fail to set this bit on port A if eDP 4868 * wasn't lit up at boot. Force this bit set when needed 4869 * so we use the proper lane count for our calculations. 4870 */ 4871 if (intel_ddi_a_force_4_lanes(dig_port)) { 4872 drm_dbg_kms(&dev_priv->drm, 4873 "Forcing DDI_A_4_LANES for port A\n"); 4874 dig_port->saved_port_bits |= DDI_A_4_LANES; 4875 max_lanes = 4; 4876 } 4877 4878 return max_lanes; 4879 } 4880 4881 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 4882 { 4883 struct intel_digital_port *dig_port; 4884 struct intel_encoder *encoder; 4885 bool init_hdmi, init_dp, init_lspcon = false; 4886 enum phy phy = intel_port_to_phy(dev_priv, port); 4887 4888 init_hdmi = intel_bios_port_supports_dvi(dev_priv, port) || 4889 intel_bios_port_supports_hdmi(dev_priv, port); 4890 init_dp = intel_bios_port_supports_dp(dev_priv, port); 4891 4892 if (intel_bios_is_lspcon_present(dev_priv, port)) { 4893 /* 4894 * Lspcon device needs to be driven with DP connector 4895 * with special detection sequence. So make sure DP 4896 * is initialized before lspcon. 4897 */ 4898 init_dp = true; 4899 init_lspcon = true; 4900 init_hdmi = false; 4901 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", 4902 port_name(port)); 4903 } 4904 4905 if (!init_dp && !init_hdmi) { 4906 drm_dbg_kms(&dev_priv->drm, 4907 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 4908 port_name(port)); 4909 return; 4910 } 4911 4912 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 4913 if (!dig_port) 4914 return; 4915 4916 encoder = &dig_port->base; 4917 4918 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4919 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port)); 4920 4921 encoder->hotplug = intel_ddi_hotplug; 4922 encoder->compute_output_type = intel_ddi_compute_output_type; 4923 encoder->compute_config = intel_ddi_compute_config; 4924 encoder->compute_config_late = intel_ddi_compute_config_late; 4925 encoder->enable = intel_enable_ddi; 4926 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 4927 encoder->pre_enable = intel_ddi_pre_enable; 4928 encoder->disable = intel_disable_ddi; 4929 encoder->post_disable = intel_ddi_post_disable; 4930 encoder->update_pipe = intel_ddi_update_pipe; 4931 encoder->get_hw_state = intel_ddi_get_hw_state; 4932 encoder->get_config = intel_ddi_get_config; 4933 encoder->suspend = intel_dp_encoder_suspend; 4934 encoder->get_power_domains = intel_ddi_get_power_domains; 4935 4936 encoder->type = INTEL_OUTPUT_DDI; 4937 encoder->power_domain = intel_port_to_power_domain(port); 4938 encoder->port = port; 4939 encoder->cloneable = 0; 4940 encoder->pipe_mask = ~0; 4941 4942 if (INTEL_GEN(dev_priv) >= 11) 4943 dig_port->saved_port_bits = 4944 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 4945 & DDI_BUF_PORT_REVERSAL; 4946 else 4947 dig_port->saved_port_bits = 4948 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 4949 & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 4950 4951 dig_port->dp.output_reg = INVALID_MMIO_REG; 4952 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 4953 dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 4954 4955 if (intel_phy_is_tc(dev_priv, phy)) { 4956 bool is_legacy = 4957 !intel_bios_port_supports_typec_usb(dev_priv, port) && 4958 !intel_bios_port_supports_tbt(dev_priv, port); 4959 4960 intel_tc_port_init(dig_port, is_legacy); 4961 4962 encoder->update_prepare = intel_ddi_update_prepare; 4963 encoder->update_complete = intel_ddi_update_complete; 4964 } 4965 4966 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 4967 dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO + 4968 port - PORT_A; 4969 4970 if (init_dp) { 4971 if (!intel_ddi_init_dp_connector(dig_port)) 4972 goto err; 4973 4974 dig_port->hpd_pulse = intel_dp_hpd_pulse; 4975 } 4976 4977 /* In theory we don't need the encoder->type check, but leave it just in 4978 * case we have some really bad VBTs... */ 4979 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 4980 if (!intel_ddi_init_hdmi_connector(dig_port)) 4981 goto err; 4982 } 4983 4984 if (init_lspcon) { 4985 if (lspcon_init(dig_port)) 4986 /* TODO: handle hdmi info frame part */ 4987 drm_dbg_kms(&dev_priv->drm, 4988 "LSPCON init success on port %c\n", 4989 port_name(port)); 4990 else 4991 /* 4992 * LSPCON init faied, but DP init was success, so 4993 * lets try to drive as DP++ port. 4994 */ 4995 drm_err(&dev_priv->drm, 4996 "LSPCON init failed on port %c\n", 4997 port_name(port)); 4998 } 4999 5000 if (INTEL_GEN(dev_priv) >= 11) { 5001 if (intel_phy_is_tc(dev_priv, phy)) 5002 dig_port->connected = intel_tc_port_connected; 5003 else 5004 dig_port->connected = lpt_digital_port_connected; 5005 } else if (INTEL_GEN(dev_priv) >= 8) { 5006 if (port == PORT_A || IS_GEN9_LP(dev_priv)) 5007 dig_port->connected = bdw_digital_port_connected; 5008 else 5009 dig_port->connected = lpt_digital_port_connected; 5010 } else { 5011 if (port == PORT_A) 5012 dig_port->connected = hsw_digital_port_connected; 5013 else 5014 dig_port->connected = lpt_digital_port_connected; 5015 } 5016 5017 intel_infoframe_init(dig_port); 5018 5019 return; 5020 5021 err: 5022 drm_encoder_cleanup(&encoder->base); 5023 kfree(dig_port); 5024 } 5025