1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <drm/drm_privacy_screen_consumer.h> 29 #include <drm/drm_scdc_helper.h> 30 31 #include "i915_drv.h" 32 #include "intel_audio.h" 33 #include "intel_backlight.h" 34 #include "intel_combo_phy.h" 35 #include "intel_connector.h" 36 #include "intel_crtc.h" 37 #include "intel_ddi.h" 38 #include "intel_ddi_buf_trans.h" 39 #include "intel_de.h" 40 #include "intel_display_types.h" 41 #include "intel_dp.h" 42 #include "intel_dp_link_training.h" 43 #include "intel_dp_mst.h" 44 #include "intel_dpio_phy.h" 45 #include "intel_drrs.h" 46 #include "intel_dsi.h" 47 #include "intel_fdi.h" 48 #include "intel_fifo_underrun.h" 49 #include "intel_gmbus.h" 50 #include "intel_hdcp.h" 51 #include "intel_hdmi.h" 52 #include "intel_hotplug.h" 53 #include "intel_lspcon.h" 54 #include "intel_pps.h" 55 #include "intel_psr.h" 56 #include "intel_snps_phy.h" 57 #include "intel_sprite.h" 58 #include "intel_tc.h" 59 #include "intel_vdsc.h" 60 #include "intel_vrr.h" 61 #include "skl_scaler.h" 62 #include "skl_universal_plane.h" 63 64 static const u8 index_to_dp_signal_levels[] = { 65 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 66 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 67 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 68 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 69 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 70 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 71 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 72 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 73 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 74 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 75 }; 76 77 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 78 const struct intel_ddi_buf_trans *trans) 79 { 80 int level; 81 82 level = intel_bios_hdmi_level_shift(encoder); 83 if (level < 0) 84 level = trans->hdmi_default_entry; 85 86 return level; 87 } 88 89 static bool has_buf_trans_select(struct drm_i915_private *i915) 90 { 91 return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915); 92 } 93 94 static bool has_iboost(struct drm_i915_private *i915) 95 { 96 return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915); 97 } 98 99 /* 100 * Starting with Haswell, DDI port buffers must be programmed with correct 101 * values in advance. This function programs the correct values for 102 * DP/eDP/FDI use cases. 103 */ 104 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 105 const struct intel_crtc_state *crtc_state) 106 { 107 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 108 u32 iboost_bit = 0; 109 int i, n_entries; 110 enum port port = encoder->port; 111 const struct intel_ddi_buf_trans *trans; 112 113 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 114 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 115 return; 116 117 /* If we're boosting the current, set bit 31 of trans1 */ 118 if (has_iboost(dev_priv) && 119 intel_bios_encoder_dp_boost_level(encoder->devdata)) 120 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 121 122 for (i = 0; i < n_entries; i++) { 123 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 124 trans->entries[i].hsw.trans1 | iboost_bit); 125 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 126 trans->entries[i].hsw.trans2); 127 } 128 } 129 130 /* 131 * Starting with Haswell, DDI port buffers must be programmed with correct 132 * values in advance. This function programs the correct values for 133 * HDMI/DVI use cases. 134 */ 135 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 136 const struct intel_crtc_state *crtc_state) 137 { 138 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 139 int level = intel_ddi_level(encoder, crtc_state, 0); 140 u32 iboost_bit = 0; 141 int n_entries; 142 enum port port = encoder->port; 143 const struct intel_ddi_buf_trans *trans; 144 145 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 146 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 147 return; 148 149 /* If we're boosting the current, set bit 31 of trans1 */ 150 if (has_iboost(dev_priv) && 151 intel_bios_encoder_hdmi_boost_level(encoder->devdata)) 152 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 153 154 /* Entry 9 is for HDMI: */ 155 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 156 trans->entries[level].hsw.trans1 | iboost_bit); 157 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 158 trans->entries[level].hsw.trans2); 159 } 160 161 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 162 enum port port) 163 { 164 if (IS_BROXTON(dev_priv)) { 165 udelay(16); 166 return; 167 } 168 169 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 170 DDI_BUF_IS_IDLE), 8)) 171 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", 172 port_name(port)); 173 } 174 175 static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, 176 enum port port) 177 { 178 int ret; 179 180 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ 181 if (DISPLAY_VER(dev_priv) < 10) { 182 usleep_range(518, 1000); 183 return; 184 } 185 186 ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 187 DDI_BUF_IS_IDLE), IS_DG2(dev_priv) ? 1200 : 500, 10, 10); 188 189 if (ret) 190 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", 191 port_name(port)); 192 } 193 194 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 195 { 196 switch (pll->info->id) { 197 case DPLL_ID_WRPLL1: 198 return PORT_CLK_SEL_WRPLL1; 199 case DPLL_ID_WRPLL2: 200 return PORT_CLK_SEL_WRPLL2; 201 case DPLL_ID_SPLL: 202 return PORT_CLK_SEL_SPLL; 203 case DPLL_ID_LCPLL_810: 204 return PORT_CLK_SEL_LCPLL_810; 205 case DPLL_ID_LCPLL_1350: 206 return PORT_CLK_SEL_LCPLL_1350; 207 case DPLL_ID_LCPLL_2700: 208 return PORT_CLK_SEL_LCPLL_2700; 209 default: 210 MISSING_CASE(pll->info->id); 211 return PORT_CLK_SEL_NONE; 212 } 213 } 214 215 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 216 const struct intel_crtc_state *crtc_state) 217 { 218 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 219 int clock = crtc_state->port_clock; 220 const enum intel_dpll_id id = pll->info->id; 221 222 switch (id) { 223 default: 224 /* 225 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 226 * here, so do warn if this get passed in 227 */ 228 MISSING_CASE(id); 229 return DDI_CLK_SEL_NONE; 230 case DPLL_ID_ICL_TBTPLL: 231 switch (clock) { 232 case 162000: 233 return DDI_CLK_SEL_TBT_162; 234 case 270000: 235 return DDI_CLK_SEL_TBT_270; 236 case 540000: 237 return DDI_CLK_SEL_TBT_540; 238 case 810000: 239 return DDI_CLK_SEL_TBT_810; 240 default: 241 MISSING_CASE(clock); 242 return DDI_CLK_SEL_NONE; 243 } 244 case DPLL_ID_ICL_MGPLL1: 245 case DPLL_ID_ICL_MGPLL2: 246 case DPLL_ID_ICL_MGPLL3: 247 case DPLL_ID_ICL_MGPLL4: 248 case DPLL_ID_TGL_MGPLL5: 249 case DPLL_ID_TGL_MGPLL6: 250 return DDI_CLK_SEL_MG; 251 } 252 } 253 254 static u32 ddi_buf_phy_link_rate(int port_clock) 255 { 256 switch (port_clock) { 257 case 162000: 258 return DDI_BUF_PHY_LINK_RATE(0); 259 case 216000: 260 return DDI_BUF_PHY_LINK_RATE(4); 261 case 243000: 262 return DDI_BUF_PHY_LINK_RATE(5); 263 case 270000: 264 return DDI_BUF_PHY_LINK_RATE(1); 265 case 324000: 266 return DDI_BUF_PHY_LINK_RATE(6); 267 case 432000: 268 return DDI_BUF_PHY_LINK_RATE(7); 269 case 540000: 270 return DDI_BUF_PHY_LINK_RATE(2); 271 case 810000: 272 return DDI_BUF_PHY_LINK_RATE(3); 273 default: 274 MISSING_CASE(port_clock); 275 return DDI_BUF_PHY_LINK_RATE(0); 276 } 277 } 278 279 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 280 const struct intel_crtc_state *crtc_state) 281 { 282 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 283 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 284 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 285 enum phy phy = intel_port_to_phy(i915, encoder->port); 286 287 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 288 intel_dp->DP = dig_port->saved_port_bits | 289 DDI_PORT_WIDTH(crtc_state->lane_count) | 290 DDI_BUF_TRANS_SELECT(0); 291 292 if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) { 293 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 294 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 295 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 296 } 297 } 298 299 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 300 enum port port) 301 { 302 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 303 304 switch (val) { 305 case DDI_CLK_SEL_NONE: 306 return 0; 307 case DDI_CLK_SEL_TBT_162: 308 return 162000; 309 case DDI_CLK_SEL_TBT_270: 310 return 270000; 311 case DDI_CLK_SEL_TBT_540: 312 return 540000; 313 case DDI_CLK_SEL_TBT_810: 314 return 810000; 315 default: 316 MISSING_CASE(val); 317 return 0; 318 } 319 } 320 321 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 322 { 323 int dotclock; 324 325 /* CRT dotclock is determined via other means */ 326 if (pipe_config->has_pch_encoder) 327 return; 328 329 if (intel_crtc_has_dp_encoder(pipe_config)) 330 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 331 &pipe_config->dp_m_n); 332 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) 333 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp; 334 else 335 dotclock = pipe_config->port_clock; 336 337 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 338 !intel_crtc_has_dp_encoder(pipe_config)) 339 dotclock *= 2; 340 341 if (pipe_config->pixel_multiplier) 342 dotclock /= pipe_config->pixel_multiplier; 343 344 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 345 } 346 347 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 348 const struct drm_connector_state *conn_state) 349 { 350 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 351 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 352 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 353 u32 temp; 354 355 if (!intel_crtc_has_dp_encoder(crtc_state)) 356 return; 357 358 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 359 360 temp = DP_MSA_MISC_SYNC_CLOCK; 361 362 switch (crtc_state->pipe_bpp) { 363 case 18: 364 temp |= DP_MSA_MISC_6_BPC; 365 break; 366 case 24: 367 temp |= DP_MSA_MISC_8_BPC; 368 break; 369 case 30: 370 temp |= DP_MSA_MISC_10_BPC; 371 break; 372 case 36: 373 temp |= DP_MSA_MISC_12_BPC; 374 break; 375 default: 376 MISSING_CASE(crtc_state->pipe_bpp); 377 break; 378 } 379 380 /* nonsense combination */ 381 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 382 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 383 384 if (crtc_state->limited_color_range) 385 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 386 387 /* 388 * As per DP 1.2 spec section 2.3.4.3 while sending 389 * YCBCR 444 signals we should program MSA MISC1/0 fields with 390 * colorspace information. 391 */ 392 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 393 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 394 395 /* 396 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 397 * of Color Encoding Format and Content Color Gamut] while sending 398 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 399 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 400 */ 401 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 402 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 403 404 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp); 405 } 406 407 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 408 { 409 if (master_transcoder == TRANSCODER_EDP) 410 return 0; 411 else 412 return master_transcoder + 1; 413 } 414 415 static void 416 intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder, 417 const struct intel_crtc_state *crtc_state) 418 { 419 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 420 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 421 u32 val = 0; 422 423 if (intel_dp_is_uhbr(crtc_state)) 424 val = TRANS_DP2_128B132B_CHANNEL_CODING; 425 426 intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val); 427 } 428 429 /* 430 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 431 * 432 * Only intended to be used by intel_ddi_enable_transcoder_func() and 433 * intel_ddi_config_transcoder_func(). 434 */ 435 static u32 436 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 437 const struct intel_crtc_state *crtc_state) 438 { 439 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 440 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 441 enum pipe pipe = crtc->pipe; 442 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 443 enum port port = encoder->port; 444 u32 temp; 445 446 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 447 temp = TRANS_DDI_FUNC_ENABLE; 448 if (DISPLAY_VER(dev_priv) >= 12) 449 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 450 else 451 temp |= TRANS_DDI_SELECT_PORT(port); 452 453 switch (crtc_state->pipe_bpp) { 454 case 18: 455 temp |= TRANS_DDI_BPC_6; 456 break; 457 case 24: 458 temp |= TRANS_DDI_BPC_8; 459 break; 460 case 30: 461 temp |= TRANS_DDI_BPC_10; 462 break; 463 case 36: 464 temp |= TRANS_DDI_BPC_12; 465 break; 466 default: 467 BUG(); 468 } 469 470 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 471 temp |= TRANS_DDI_PVSYNC; 472 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 473 temp |= TRANS_DDI_PHSYNC; 474 475 if (cpu_transcoder == TRANSCODER_EDP) { 476 switch (pipe) { 477 case PIPE_A: 478 /* On Haswell, can only use the always-on power well for 479 * eDP when not using the panel fitter, and when not 480 * using motion blur mitigation (which we don't 481 * support). */ 482 if (crtc_state->pch_pfit.force_thru) 483 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 484 else 485 temp |= TRANS_DDI_EDP_INPUT_A_ON; 486 break; 487 case PIPE_B: 488 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 489 break; 490 case PIPE_C: 491 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 492 break; 493 default: 494 BUG(); 495 break; 496 } 497 } 498 499 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 500 if (crtc_state->has_hdmi_sink) 501 temp |= TRANS_DDI_MODE_SELECT_HDMI; 502 else 503 temp |= TRANS_DDI_MODE_SELECT_DVI; 504 505 if (crtc_state->hdmi_scrambling) 506 temp |= TRANS_DDI_HDMI_SCRAMBLING; 507 if (crtc_state->hdmi_high_tmds_clock_ratio) 508 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 509 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 510 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 511 temp |= (crtc_state->fdi_lanes - 1) << 1; 512 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 513 if (intel_dp_is_uhbr(crtc_state)) 514 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 515 else 516 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 517 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 518 519 if (DISPLAY_VER(dev_priv) >= 12) { 520 enum transcoder master; 521 522 master = crtc_state->mst_master_transcoder; 523 drm_WARN_ON(&dev_priv->drm, 524 master == INVALID_TRANSCODER); 525 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 526 } 527 } else { 528 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 529 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 530 } 531 532 if (IS_DISPLAY_VER(dev_priv, 8, 10) && 533 crtc_state->master_transcoder != INVALID_TRANSCODER) { 534 u8 master_select = 535 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 536 537 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 538 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 539 } 540 541 return temp; 542 } 543 544 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 545 const struct intel_crtc_state *crtc_state) 546 { 547 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 548 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 549 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 550 551 if (DISPLAY_VER(dev_priv) >= 11) { 552 enum transcoder master_transcoder = crtc_state->master_transcoder; 553 u32 ctl2 = 0; 554 555 if (master_transcoder != INVALID_TRANSCODER) { 556 u8 master_select = 557 bdw_trans_port_sync_master_select(master_transcoder); 558 559 ctl2 |= PORT_SYNC_MODE_ENABLE | 560 PORT_SYNC_MODE_MASTER_SELECT(master_select); 561 } 562 563 intel_de_write(dev_priv, 564 TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2); 565 } 566 567 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 568 intel_ddi_transcoder_func_reg_val_get(encoder, 569 crtc_state)); 570 } 571 572 /* 573 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 574 * bit. 575 */ 576 static void 577 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 578 const struct intel_crtc_state *crtc_state) 579 { 580 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 581 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 582 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 583 u32 ctl; 584 585 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 586 ctl &= ~TRANS_DDI_FUNC_ENABLE; 587 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 588 } 589 590 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 591 { 592 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 593 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 594 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 595 u32 ctl; 596 597 if (DISPLAY_VER(dev_priv) >= 11) 598 intel_de_write(dev_priv, 599 TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0); 600 601 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 602 603 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 604 605 ctl &= ~TRANS_DDI_FUNC_ENABLE; 606 607 if (IS_DISPLAY_VER(dev_priv, 8, 10)) 608 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 609 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 610 611 if (DISPLAY_VER(dev_priv) >= 12) { 612 if (!intel_dp_mst_is_master_trans(crtc_state)) { 613 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 614 TRANS_DDI_MODE_SELECT_MASK); 615 } 616 } else { 617 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 618 } 619 620 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 621 622 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME && 623 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 624 drm_dbg_kms(&dev_priv->drm, 625 "Quirk Increase DDI disabled time\n"); 626 /* Quirk time at 100ms for reliable operation */ 627 msleep(100); 628 } 629 } 630 631 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 632 enum transcoder cpu_transcoder, 633 bool enable, u32 hdcp_mask) 634 { 635 struct drm_device *dev = intel_encoder->base.dev; 636 struct drm_i915_private *dev_priv = to_i915(dev); 637 intel_wakeref_t wakeref; 638 int ret = 0; 639 u32 tmp; 640 641 wakeref = intel_display_power_get_if_enabled(dev_priv, 642 intel_encoder->power_domain); 643 if (drm_WARN_ON(dev, !wakeref)) 644 return -ENXIO; 645 646 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 647 if (enable) 648 tmp |= hdcp_mask; 649 else 650 tmp &= ~hdcp_mask; 651 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp); 652 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 653 return ret; 654 } 655 656 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 657 { 658 struct drm_device *dev = intel_connector->base.dev; 659 struct drm_i915_private *dev_priv = to_i915(dev); 660 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 661 int type = intel_connector->base.connector_type; 662 enum port port = encoder->port; 663 enum transcoder cpu_transcoder; 664 intel_wakeref_t wakeref; 665 enum pipe pipe = 0; 666 u32 tmp; 667 bool ret; 668 669 wakeref = intel_display_power_get_if_enabled(dev_priv, 670 encoder->power_domain); 671 if (!wakeref) 672 return false; 673 674 if (!encoder->get_hw_state(encoder, &pipe)) { 675 ret = false; 676 goto out; 677 } 678 679 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 680 cpu_transcoder = TRANSCODER_EDP; 681 else 682 cpu_transcoder = (enum transcoder) pipe; 683 684 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 685 686 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 687 case TRANS_DDI_MODE_SELECT_HDMI: 688 case TRANS_DDI_MODE_SELECT_DVI: 689 ret = type == DRM_MODE_CONNECTOR_HDMIA; 690 break; 691 692 case TRANS_DDI_MODE_SELECT_DP_SST: 693 ret = type == DRM_MODE_CONNECTOR_eDP || 694 type == DRM_MODE_CONNECTOR_DisplayPort; 695 break; 696 697 case TRANS_DDI_MODE_SELECT_DP_MST: 698 /* if the transcoder is in MST state then 699 * connector isn't connected */ 700 ret = false; 701 break; 702 703 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 704 if (HAS_DP20(dev_priv)) 705 /* 128b/132b */ 706 ret = false; 707 else 708 /* FDI */ 709 ret = type == DRM_MODE_CONNECTOR_VGA; 710 break; 711 712 default: 713 ret = false; 714 break; 715 } 716 717 out: 718 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 719 720 return ret; 721 } 722 723 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 724 u8 *pipe_mask, bool *is_dp_mst) 725 { 726 struct drm_device *dev = encoder->base.dev; 727 struct drm_i915_private *dev_priv = to_i915(dev); 728 enum port port = encoder->port; 729 intel_wakeref_t wakeref; 730 enum pipe p; 731 u32 tmp; 732 u8 mst_pipe_mask; 733 734 *pipe_mask = 0; 735 *is_dp_mst = false; 736 737 wakeref = intel_display_power_get_if_enabled(dev_priv, 738 encoder->power_domain); 739 if (!wakeref) 740 return; 741 742 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 743 if (!(tmp & DDI_BUF_CTL_ENABLE)) 744 goto out; 745 746 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { 747 tmp = intel_de_read(dev_priv, 748 TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 749 750 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 751 default: 752 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 753 fallthrough; 754 case TRANS_DDI_EDP_INPUT_A_ON: 755 case TRANS_DDI_EDP_INPUT_A_ONOFF: 756 *pipe_mask = BIT(PIPE_A); 757 break; 758 case TRANS_DDI_EDP_INPUT_B_ONOFF: 759 *pipe_mask = BIT(PIPE_B); 760 break; 761 case TRANS_DDI_EDP_INPUT_C_ONOFF: 762 *pipe_mask = BIT(PIPE_C); 763 break; 764 } 765 766 goto out; 767 } 768 769 mst_pipe_mask = 0; 770 for_each_pipe(dev_priv, p) { 771 enum transcoder cpu_transcoder = (enum transcoder)p; 772 unsigned int port_mask, ddi_select; 773 intel_wakeref_t trans_wakeref; 774 775 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 776 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 777 if (!trans_wakeref) 778 continue; 779 780 if (DISPLAY_VER(dev_priv) >= 12) { 781 port_mask = TGL_TRANS_DDI_PORT_MASK; 782 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 783 } else { 784 port_mask = TRANS_DDI_PORT_MASK; 785 ddi_select = TRANS_DDI_SELECT_PORT(port); 786 } 787 788 tmp = intel_de_read(dev_priv, 789 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 790 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 791 trans_wakeref); 792 793 if ((tmp & port_mask) != ddi_select) 794 continue; 795 796 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST || 797 (HAS_DP20(dev_priv) && 798 (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B)) 799 mst_pipe_mask |= BIT(p); 800 801 *pipe_mask |= BIT(p); 802 } 803 804 if (!*pipe_mask) 805 drm_dbg_kms(&dev_priv->drm, 806 "No pipe for [ENCODER:%d:%s] found\n", 807 encoder->base.base.id, encoder->base.name); 808 809 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 810 drm_dbg_kms(&dev_priv->drm, 811 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 812 encoder->base.base.id, encoder->base.name, 813 *pipe_mask); 814 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 815 } 816 817 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 818 drm_dbg_kms(&dev_priv->drm, 819 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", 820 encoder->base.base.id, encoder->base.name, 821 *pipe_mask, mst_pipe_mask); 822 else 823 *is_dp_mst = mst_pipe_mask; 824 825 out: 826 if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) { 827 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 828 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 829 BXT_PHY_LANE_POWERDOWN_ACK | 830 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 831 drm_err(&dev_priv->drm, 832 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 833 encoder->base.base.id, encoder->base.name, tmp); 834 } 835 836 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 837 } 838 839 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 840 enum pipe *pipe) 841 { 842 u8 pipe_mask; 843 bool is_mst; 844 845 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 846 847 if (is_mst || !pipe_mask) 848 return false; 849 850 *pipe = ffs(pipe_mask) - 1; 851 852 return true; 853 } 854 855 static enum intel_display_power_domain 856 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port) 857 { 858 /* ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 859 * DC states enabled at the same time, while for driver initiated AUX 860 * transfers we need the same AUX IOs to be powered but with DC states 861 * disabled. Accordingly use the AUX power domain here which leaves DC 862 * states enabled. 863 * However, for non-A AUX ports the corresponding non-EDP transcoders 864 * would have already enabled power well 2 and DC_OFF. This means we can 865 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a 866 * specific AUX_IO reference without powering up any extra wells. 867 * Note that PSR is enabled only on Port A even though this function 868 * returns the correct domain for other ports too. 869 */ 870 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A : 871 intel_aux_power_domain(dig_port); 872 } 873 874 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 875 struct intel_crtc_state *crtc_state) 876 { 877 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 878 struct intel_digital_port *dig_port; 879 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 880 881 /* 882 * TODO: Add support for MST encoders. Atm, the following should never 883 * happen since fake-MST encoders don't set their get_power_domains() 884 * hook. 885 */ 886 if (drm_WARN_ON(&dev_priv->drm, 887 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 888 return; 889 890 dig_port = enc_to_dig_port(encoder); 891 892 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 893 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 894 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 895 dig_port->ddi_io_power_domain); 896 } 897 898 /* 899 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC 900 * ports. 901 */ 902 if (intel_crtc_has_dp_encoder(crtc_state) || 903 intel_phy_is_tc(dev_priv, phy)) { 904 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref); 905 dig_port->aux_wakeref = 906 intel_display_power_get(dev_priv, 907 intel_ddi_main_link_aux_domain(dig_port)); 908 } 909 } 910 911 void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder, 912 const struct intel_crtc_state *crtc_state) 913 { 914 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 915 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 916 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 917 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 918 u32 val; 919 920 if (cpu_transcoder != TRANSCODER_EDP) { 921 if (DISPLAY_VER(dev_priv) >= 13) 922 val = TGL_TRANS_CLK_SEL_PORT(phy); 923 else if (DISPLAY_VER(dev_priv) >= 12) 924 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 925 else 926 val = TRANS_CLK_SEL_PORT(encoder->port); 927 928 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 929 } 930 } 931 932 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state) 933 { 934 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 935 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 936 937 if (cpu_transcoder != TRANSCODER_EDP) { 938 if (DISPLAY_VER(dev_priv) >= 12) 939 intel_de_write(dev_priv, 940 TRANS_CLK_SEL(cpu_transcoder), 941 TGL_TRANS_CLK_SEL_DISABLED); 942 else 943 intel_de_write(dev_priv, 944 TRANS_CLK_SEL(cpu_transcoder), 945 TRANS_CLK_SEL_DISABLED); 946 } 947 } 948 949 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 950 enum port port, u8 iboost) 951 { 952 u32 tmp; 953 954 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 955 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 956 if (iboost) 957 tmp |= iboost << BALANCE_LEG_SHIFT(port); 958 else 959 tmp |= BALANCE_LEG_DISABLE(port); 960 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 961 } 962 963 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 964 const struct intel_crtc_state *crtc_state, 965 int level) 966 { 967 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 968 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 969 u8 iboost; 970 971 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 972 iboost = intel_bios_encoder_hdmi_boost_level(encoder->devdata); 973 else 974 iboost = intel_bios_encoder_dp_boost_level(encoder->devdata); 975 976 if (iboost == 0) { 977 const struct intel_ddi_buf_trans *trans; 978 int n_entries; 979 980 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 981 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 982 return; 983 984 iboost = trans->entries[level].hsw.i_boost; 985 } 986 987 /* Make sure that the requested I_boost is valid */ 988 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 989 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); 990 return; 991 } 992 993 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); 994 995 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 996 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 997 } 998 999 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1000 const struct intel_crtc_state *crtc_state) 1001 { 1002 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1003 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1004 int n_entries; 1005 1006 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1007 1008 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 1009 n_entries = 1; 1010 if (drm_WARN_ON(&dev_priv->drm, 1011 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1012 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1013 1014 return index_to_dp_signal_levels[n_entries - 1] & 1015 DP_TRAIN_VOLTAGE_SWING_MASK; 1016 } 1017 1018 /* 1019 * We assume that the full set of pre-emphasis values can be 1020 * used on all DDI platforms. Should that change we need to 1021 * rethink this code. 1022 */ 1023 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1024 { 1025 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1026 } 1027 1028 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1029 int lane) 1030 { 1031 if (crtc_state->port_clock > 600000) 1032 return 0; 1033 1034 if (crtc_state->lane_count == 4) 1035 return lane >= 1 ? LOADGEN_SELECT : 0; 1036 else 1037 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1038 } 1039 1040 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1041 const struct intel_crtc_state *crtc_state) 1042 { 1043 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1044 const struct intel_ddi_buf_trans *trans; 1045 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1046 int n_entries, ln; 1047 u32 val; 1048 1049 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1050 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1051 return; 1052 1053 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1054 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1055 1056 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1057 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1058 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, 1059 intel_dp->hobl_active ? val : 0); 1060 } 1061 1062 /* Set PORT_TX_DW5 */ 1063 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1064 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1065 TAP2_DISABLE | TAP3_DISABLE); 1066 val |= SCALING_MODE_SEL(0x2); 1067 val |= RTERM_SELECT(0x6); 1068 val |= TAP3_DISABLE; 1069 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1070 1071 /* Program PORT_TX_DW2 */ 1072 for (ln = 0; ln < 4; ln++) { 1073 int level = intel_ddi_level(encoder, crtc_state, ln); 1074 1075 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy), 1076 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1077 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1078 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1079 RCOMP_SCALAR(0x98)); 1080 } 1081 1082 /* Program PORT_TX_DW4 */ 1083 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1084 for (ln = 0; ln < 4; ln++) { 1085 int level = intel_ddi_level(encoder, crtc_state, ln); 1086 1087 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1088 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1089 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1090 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1091 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1092 } 1093 1094 /* Program PORT_TX_DW7 */ 1095 for (ln = 0; ln < 4; ln++) { 1096 int level = intel_ddi_level(encoder, crtc_state, ln); 1097 1098 intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy), 1099 N_SCALAR_MASK, 1100 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1101 } 1102 } 1103 1104 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1105 const struct intel_crtc_state *crtc_state) 1106 { 1107 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1108 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1109 u32 val; 1110 int ln; 1111 1112 /* 1113 * 1. If port type is eDP or DP, 1114 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1115 * else clear to 0b. 1116 */ 1117 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); 1118 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1119 val &= ~COMMON_KEEPER_EN; 1120 else 1121 val |= COMMON_KEEPER_EN; 1122 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 1123 1124 /* 2. Program loadgen select */ 1125 /* 1126 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1127 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1128 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1129 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1130 */ 1131 for (ln = 0; ln < 4; ln++) { 1132 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1133 LOADGEN_SELECT, 1134 icl_combo_phy_loadgen_select(crtc_state, ln)); 1135 } 1136 1137 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1138 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 1139 0, SUS_CLOCK_CONFIG); 1140 1141 /* 4. Clear training enable to change swing values */ 1142 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1143 val &= ~TX_TRAINING_EN; 1144 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1145 1146 /* 5. Program swing and de-emphasis */ 1147 icl_ddi_combo_vswing_program(encoder, crtc_state); 1148 1149 /* 6. Set training enable to trigger update */ 1150 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1151 val |= TX_TRAINING_EN; 1152 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1153 } 1154 1155 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1156 const struct intel_crtc_state *crtc_state) 1157 { 1158 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1159 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 1160 const struct intel_ddi_buf_trans *trans; 1161 int n_entries, ln; 1162 1163 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1164 return; 1165 1166 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1167 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1168 return; 1169 1170 for (ln = 0; ln < 2; ln++) { 1171 intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), 1172 CRI_USE_FS32, 0); 1173 intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), 1174 CRI_USE_FS32, 0); 1175 } 1176 1177 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1178 for (ln = 0; ln < 2; ln++) { 1179 int level; 1180 1181 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1182 1183 intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), 1184 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1185 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1186 1187 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1188 1189 intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), 1190 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1191 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1192 } 1193 1194 /* Program MG_TX_DRVCTRL with values from vswing table */ 1195 for (ln = 0; ln < 2; ln++) { 1196 int level; 1197 1198 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1199 1200 intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), 1201 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1202 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1203 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1204 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1205 CRI_TXDEEMPH_OVERRIDE_EN); 1206 1207 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1208 1209 intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), 1210 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1211 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1212 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1213 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1214 CRI_TXDEEMPH_OVERRIDE_EN); 1215 1216 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1217 } 1218 1219 /* 1220 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1221 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1222 * values from table for which TX1 and TX2 enabled. 1223 */ 1224 for (ln = 0; ln < 2; ln++) { 1225 intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port), 1226 CFG_LOW_RATE_LKREN_EN, 1227 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1228 } 1229 1230 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1231 for (ln = 0; ln < 2; ln++) { 1232 intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port), 1233 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1234 CFG_AMI_CK_DIV_OVERRIDE_EN, 1235 crtc_state->port_clock > 500000 ? 1236 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1237 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1238 1239 intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port), 1240 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1241 CFG_AMI_CK_DIV_OVERRIDE_EN, 1242 crtc_state->port_clock > 500000 ? 1243 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1244 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1245 } 1246 1247 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1248 for (ln = 0; ln < 2; ln++) { 1249 intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 1250 0, CRI_CALCINIT); 1251 intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 1252 0, CRI_CALCINIT); 1253 } 1254 } 1255 1256 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1257 const struct intel_crtc_state *crtc_state) 1258 { 1259 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1260 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 1261 const struct intel_ddi_buf_trans *trans; 1262 int n_entries, ln; 1263 1264 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1265 return; 1266 1267 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1268 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1269 return; 1270 1271 for (ln = 0; ln < 2; ln++) { 1272 int level; 1273 1274 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 1275 HIP_INDEX_VAL(tc_port, ln)); 1276 1277 intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0); 1278 1279 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1280 1281 intel_de_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port), 1282 DKL_TX_PRESHOOT_COEFF_MASK | 1283 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1284 DKL_TX_VSWING_CONTROL_MASK, 1285 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1286 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1287 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1288 1289 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1290 1291 intel_de_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port), 1292 DKL_TX_PRESHOOT_COEFF_MASK | 1293 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1294 DKL_TX_VSWING_CONTROL_MASK, 1295 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1296 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1297 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1298 1299 intel_de_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port), 1300 DKL_TX_DP20BITMODE, 0); 1301 1302 if (IS_ALDERLAKE_P(dev_priv)) { 1303 u32 val; 1304 1305 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1306 if (ln == 0) { 1307 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1308 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); 1309 } else { 1310 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); 1311 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); 1312 } 1313 } else { 1314 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1315 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); 1316 } 1317 1318 intel_de_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port), 1319 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | 1320 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, 1321 val); 1322 } 1323 } 1324 } 1325 1326 static int translate_signal_level(struct intel_dp *intel_dp, 1327 u8 signal_levels) 1328 { 1329 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1330 int i; 1331 1332 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1333 if (index_to_dp_signal_levels[i] == signal_levels) 1334 return i; 1335 } 1336 1337 drm_WARN(&i915->drm, 1, 1338 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1339 signal_levels); 1340 1341 return 0; 1342 } 1343 1344 static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1345 const struct intel_crtc_state *crtc_state, 1346 int lane) 1347 { 1348 u8 train_set = intel_dp->train_set[lane]; 1349 1350 if (intel_dp_is_uhbr(crtc_state)) { 1351 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1352 } else { 1353 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1354 DP_TRAIN_PRE_EMPHASIS_MASK); 1355 1356 return translate_signal_level(intel_dp, signal_levels); 1357 } 1358 } 1359 1360 int intel_ddi_level(struct intel_encoder *encoder, 1361 const struct intel_crtc_state *crtc_state, 1362 int lane) 1363 { 1364 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1365 const struct intel_ddi_buf_trans *trans; 1366 int level, n_entries; 1367 1368 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1369 if (drm_WARN_ON_ONCE(&i915->drm, !trans)) 1370 return 0; 1371 1372 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1373 level = intel_ddi_hdmi_level(encoder, trans); 1374 else 1375 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1376 lane); 1377 1378 if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries)) 1379 level = n_entries - 1; 1380 1381 return level; 1382 } 1383 1384 static void 1385 hsw_set_signal_levels(struct intel_encoder *encoder, 1386 const struct intel_crtc_state *crtc_state) 1387 { 1388 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1389 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1390 int level = intel_ddi_level(encoder, crtc_state, 0); 1391 enum port port = encoder->port; 1392 u32 signal_levels; 1393 1394 if (has_iboost(dev_priv)) 1395 skl_ddi_set_iboost(encoder, crtc_state, level); 1396 1397 /* HDMI ignores the rest */ 1398 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1399 return; 1400 1401 signal_levels = DDI_BUF_TRANS_SELECT(level); 1402 1403 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1404 signal_levels); 1405 1406 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1407 intel_dp->DP |= signal_levels; 1408 1409 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 1410 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 1411 } 1412 1413 static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1414 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1415 { 1416 mutex_lock(&i915->dpll.lock); 1417 1418 intel_de_rmw(i915, reg, clk_sel_mask, clk_sel); 1419 1420 /* 1421 * "This step and the step before must be 1422 * done with separate register writes." 1423 */ 1424 intel_de_rmw(i915, reg, clk_off, 0); 1425 1426 mutex_unlock(&i915->dpll.lock); 1427 } 1428 1429 static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1430 u32 clk_off) 1431 { 1432 mutex_lock(&i915->dpll.lock); 1433 1434 intel_de_rmw(i915, reg, 0, clk_off); 1435 1436 mutex_unlock(&i915->dpll.lock); 1437 } 1438 1439 static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg, 1440 u32 clk_off) 1441 { 1442 return !(intel_de_read(i915, reg) & clk_off); 1443 } 1444 1445 static struct intel_shared_dpll * 1446 _icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg, 1447 u32 clk_sel_mask, u32 clk_sel_shift) 1448 { 1449 enum intel_dpll_id id; 1450 1451 id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift; 1452 1453 return intel_get_shared_dpll_by_id(i915, id); 1454 } 1455 1456 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1457 const struct intel_crtc_state *crtc_state) 1458 { 1459 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1460 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1461 enum phy phy = intel_port_to_phy(i915, encoder->port); 1462 1463 if (drm_WARN_ON(&i915->drm, !pll)) 1464 return; 1465 1466 _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1467 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1468 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1469 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1470 } 1471 1472 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1473 { 1474 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1475 enum phy phy = intel_port_to_phy(i915, encoder->port); 1476 1477 _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1478 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1479 } 1480 1481 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1482 { 1483 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1484 enum phy phy = intel_port_to_phy(i915, encoder->port); 1485 1486 return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy), 1487 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1488 } 1489 1490 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1491 { 1492 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1493 enum phy phy = intel_port_to_phy(i915, encoder->port); 1494 1495 return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy), 1496 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1497 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1498 } 1499 1500 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1501 const struct intel_crtc_state *crtc_state) 1502 { 1503 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1504 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1505 enum phy phy = intel_port_to_phy(i915, encoder->port); 1506 1507 if (drm_WARN_ON(&i915->drm, !pll)) 1508 return; 1509 1510 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1511 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1512 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1513 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1514 } 1515 1516 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1517 { 1518 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1519 enum phy phy = intel_port_to_phy(i915, encoder->port); 1520 1521 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1522 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1523 } 1524 1525 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1526 { 1527 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1528 enum phy phy = intel_port_to_phy(i915, encoder->port); 1529 1530 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1531 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1532 } 1533 1534 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1535 { 1536 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1537 enum phy phy = intel_port_to_phy(i915, encoder->port); 1538 1539 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1540 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1541 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1542 } 1543 1544 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1545 const struct intel_crtc_state *crtc_state) 1546 { 1547 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1548 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1549 enum phy phy = intel_port_to_phy(i915, encoder->port); 1550 1551 if (drm_WARN_ON(&i915->drm, !pll)) 1552 return; 1553 1554 /* 1555 * If we fail this, something went very wrong: first 2 PLLs should be 1556 * used by first 2 phys and last 2 PLLs by last phys 1557 */ 1558 if (drm_WARN_ON(&i915->drm, 1559 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1560 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1561 return; 1562 1563 _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1564 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1565 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1566 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1567 } 1568 1569 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1570 { 1571 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1572 enum phy phy = intel_port_to_phy(i915, encoder->port); 1573 1574 _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1575 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1576 } 1577 1578 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1579 { 1580 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1581 enum phy phy = intel_port_to_phy(i915, encoder->port); 1582 1583 return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy), 1584 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1585 } 1586 1587 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1588 { 1589 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1590 enum phy phy = intel_port_to_phy(i915, encoder->port); 1591 enum intel_dpll_id id; 1592 u32 val; 1593 1594 val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy)); 1595 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1596 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1597 id = val; 1598 1599 /* 1600 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1601 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1602 * bit for phy C and D. 1603 */ 1604 if (phy >= PHY_C) 1605 id += DPLL_ID_DG1_DPLL2; 1606 1607 return intel_get_shared_dpll_by_id(i915, id); 1608 } 1609 1610 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1611 const struct intel_crtc_state *crtc_state) 1612 { 1613 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1614 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1615 enum phy phy = intel_port_to_phy(i915, encoder->port); 1616 1617 if (drm_WARN_ON(&i915->drm, !pll)) 1618 return; 1619 1620 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1621 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1622 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1623 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1624 } 1625 1626 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1627 { 1628 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1629 enum phy phy = intel_port_to_phy(i915, encoder->port); 1630 1631 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1632 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1633 } 1634 1635 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1636 { 1637 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1638 enum phy phy = intel_port_to_phy(i915, encoder->port); 1639 1640 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1641 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1642 } 1643 1644 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1645 { 1646 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1647 enum phy phy = intel_port_to_phy(i915, encoder->port); 1648 1649 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1650 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1651 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1652 } 1653 1654 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1655 const struct intel_crtc_state *crtc_state) 1656 { 1657 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1658 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1659 enum port port = encoder->port; 1660 1661 if (drm_WARN_ON(&i915->drm, !pll)) 1662 return; 1663 1664 /* 1665 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1666 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1667 */ 1668 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1669 1670 icl_ddi_combo_enable_clock(encoder, crtc_state); 1671 } 1672 1673 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1674 { 1675 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1676 enum port port = encoder->port; 1677 1678 icl_ddi_combo_disable_clock(encoder); 1679 1680 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1681 } 1682 1683 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1684 { 1685 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1686 enum port port = encoder->port; 1687 u32 tmp; 1688 1689 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1690 1691 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1692 return false; 1693 1694 return icl_ddi_combo_is_clock_enabled(encoder); 1695 } 1696 1697 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1698 const struct intel_crtc_state *crtc_state) 1699 { 1700 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1701 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1702 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1703 enum port port = encoder->port; 1704 1705 if (drm_WARN_ON(&i915->drm, !pll)) 1706 return; 1707 1708 intel_de_write(i915, DDI_CLK_SEL(port), 1709 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1710 1711 mutex_lock(&i915->dpll.lock); 1712 1713 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1714 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1715 1716 mutex_unlock(&i915->dpll.lock); 1717 } 1718 1719 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1720 { 1721 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1722 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1723 enum port port = encoder->port; 1724 1725 mutex_lock(&i915->dpll.lock); 1726 1727 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1728 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1729 1730 mutex_unlock(&i915->dpll.lock); 1731 1732 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1733 } 1734 1735 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1736 { 1737 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1738 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1739 enum port port = encoder->port; 1740 u32 tmp; 1741 1742 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1743 1744 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1745 return false; 1746 1747 tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0); 1748 1749 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1750 } 1751 1752 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1753 { 1754 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1755 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1756 enum port port = encoder->port; 1757 enum intel_dpll_id id; 1758 u32 tmp; 1759 1760 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1761 1762 switch (tmp & DDI_CLK_SEL_MASK) { 1763 case DDI_CLK_SEL_TBT_162: 1764 case DDI_CLK_SEL_TBT_270: 1765 case DDI_CLK_SEL_TBT_540: 1766 case DDI_CLK_SEL_TBT_810: 1767 id = DPLL_ID_ICL_TBTPLL; 1768 break; 1769 case DDI_CLK_SEL_MG: 1770 id = icl_tc_port_to_pll_id(tc_port); 1771 break; 1772 default: 1773 MISSING_CASE(tmp); 1774 fallthrough; 1775 case DDI_CLK_SEL_NONE: 1776 return NULL; 1777 } 1778 1779 return intel_get_shared_dpll_by_id(i915, id); 1780 } 1781 1782 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1783 { 1784 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1785 enum intel_dpll_id id; 1786 1787 switch (encoder->port) { 1788 case PORT_A: 1789 id = DPLL_ID_SKL_DPLL0; 1790 break; 1791 case PORT_B: 1792 id = DPLL_ID_SKL_DPLL1; 1793 break; 1794 case PORT_C: 1795 id = DPLL_ID_SKL_DPLL2; 1796 break; 1797 default: 1798 MISSING_CASE(encoder->port); 1799 return NULL; 1800 } 1801 1802 return intel_get_shared_dpll_by_id(i915, id); 1803 } 1804 1805 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1806 const struct intel_crtc_state *crtc_state) 1807 { 1808 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1809 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1810 enum port port = encoder->port; 1811 1812 if (drm_WARN_ON(&i915->drm, !pll)) 1813 return; 1814 1815 mutex_lock(&i915->dpll.lock); 1816 1817 intel_de_rmw(i915, DPLL_CTRL2, 1818 DPLL_CTRL2_DDI_CLK_OFF(port) | 1819 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1820 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1821 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1822 1823 mutex_unlock(&i915->dpll.lock); 1824 } 1825 1826 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1827 { 1828 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1829 enum port port = encoder->port; 1830 1831 mutex_lock(&i915->dpll.lock); 1832 1833 intel_de_rmw(i915, DPLL_CTRL2, 1834 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1835 1836 mutex_unlock(&i915->dpll.lock); 1837 } 1838 1839 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1840 { 1841 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1842 enum port port = encoder->port; 1843 1844 /* 1845 * FIXME Not sure if the override affects both 1846 * the PLL selection and the CLK_OFF bit. 1847 */ 1848 return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 1849 } 1850 1851 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 1852 { 1853 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1854 enum port port = encoder->port; 1855 enum intel_dpll_id id; 1856 u32 tmp; 1857 1858 tmp = intel_de_read(i915, DPLL_CTRL2); 1859 1860 /* 1861 * FIXME Not sure if the override affects both 1862 * the PLL selection and the CLK_OFF bit. 1863 */ 1864 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 1865 return NULL; 1866 1867 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 1868 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 1869 1870 return intel_get_shared_dpll_by_id(i915, id); 1871 } 1872 1873 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 1874 const struct intel_crtc_state *crtc_state) 1875 { 1876 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1877 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1878 enum port port = encoder->port; 1879 1880 if (drm_WARN_ON(&i915->drm, !pll)) 1881 return; 1882 1883 intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 1884 } 1885 1886 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 1887 { 1888 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1889 enum port port = encoder->port; 1890 1891 intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 1892 } 1893 1894 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 1895 { 1896 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1897 enum port port = encoder->port; 1898 1899 return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 1900 } 1901 1902 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 1903 { 1904 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1905 enum port port = encoder->port; 1906 enum intel_dpll_id id; 1907 u32 tmp; 1908 1909 tmp = intel_de_read(i915, PORT_CLK_SEL(port)); 1910 1911 switch (tmp & PORT_CLK_SEL_MASK) { 1912 case PORT_CLK_SEL_WRPLL1: 1913 id = DPLL_ID_WRPLL1; 1914 break; 1915 case PORT_CLK_SEL_WRPLL2: 1916 id = DPLL_ID_WRPLL2; 1917 break; 1918 case PORT_CLK_SEL_SPLL: 1919 id = DPLL_ID_SPLL; 1920 break; 1921 case PORT_CLK_SEL_LCPLL_810: 1922 id = DPLL_ID_LCPLL_810; 1923 break; 1924 case PORT_CLK_SEL_LCPLL_1350: 1925 id = DPLL_ID_LCPLL_1350; 1926 break; 1927 case PORT_CLK_SEL_LCPLL_2700: 1928 id = DPLL_ID_LCPLL_2700; 1929 break; 1930 default: 1931 MISSING_CASE(tmp); 1932 fallthrough; 1933 case PORT_CLK_SEL_NONE: 1934 return NULL; 1935 } 1936 1937 return intel_get_shared_dpll_by_id(i915, id); 1938 } 1939 1940 void intel_ddi_enable_clock(struct intel_encoder *encoder, 1941 const struct intel_crtc_state *crtc_state) 1942 { 1943 if (encoder->enable_clock) 1944 encoder->enable_clock(encoder, crtc_state); 1945 } 1946 1947 void intel_ddi_disable_clock(struct intel_encoder *encoder) 1948 { 1949 if (encoder->disable_clock) 1950 encoder->disable_clock(encoder); 1951 } 1952 1953 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 1954 { 1955 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1956 u32 port_mask; 1957 bool ddi_clk_needed; 1958 1959 /* 1960 * In case of DP MST, we sanitize the primary encoder only, not the 1961 * virtual ones. 1962 */ 1963 if (encoder->type == INTEL_OUTPUT_DP_MST) 1964 return; 1965 1966 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 1967 u8 pipe_mask; 1968 bool is_mst; 1969 1970 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 1971 /* 1972 * In the unlikely case that BIOS enables DP in MST mode, just 1973 * warn since our MST HW readout is incomplete. 1974 */ 1975 if (drm_WARN_ON(&i915->drm, is_mst)) 1976 return; 1977 } 1978 1979 port_mask = BIT(encoder->port); 1980 ddi_clk_needed = encoder->base.crtc; 1981 1982 if (encoder->type == INTEL_OUTPUT_DSI) { 1983 struct intel_encoder *other_encoder; 1984 1985 port_mask = intel_dsi_encoder_ports(encoder); 1986 /* 1987 * Sanity check that we haven't incorrectly registered another 1988 * encoder using any of the ports of this DSI encoder. 1989 */ 1990 for_each_intel_encoder(&i915->drm, other_encoder) { 1991 if (other_encoder == encoder) 1992 continue; 1993 1994 if (drm_WARN_ON(&i915->drm, 1995 port_mask & BIT(other_encoder->port))) 1996 return; 1997 } 1998 /* 1999 * For DSI we keep the ddi clocks gated 2000 * except during enable/disable sequence. 2001 */ 2002 ddi_clk_needed = false; 2003 } 2004 2005 if (ddi_clk_needed || !encoder->is_clock_enabled || 2006 !encoder->is_clock_enabled(encoder)) 2007 return; 2008 2009 drm_notice(&i915->drm, 2010 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2011 encoder->base.base.id, encoder->base.name); 2012 2013 encoder->disable_clock(encoder); 2014 } 2015 2016 static void 2017 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2018 const struct intel_crtc_state *crtc_state) 2019 { 2020 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2021 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port); 2022 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); 2023 u32 ln0, ln1, pin_assignment; 2024 u8 width; 2025 2026 if (!intel_phy_is_tc(dev_priv, phy) || 2027 intel_tc_port_in_tbt_alt_mode(dig_port)) 2028 return; 2029 2030 if (DISPLAY_VER(dev_priv) >= 12) { 2031 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2032 HIP_INDEX_VAL(tc_port, 0x0)); 2033 ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); 2034 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2035 HIP_INDEX_VAL(tc_port, 0x1)); 2036 ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); 2037 } else { 2038 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 2039 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 2040 } 2041 2042 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2043 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2044 2045 /* DPPATC */ 2046 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 2047 width = crtc_state->lane_count; 2048 2049 switch (pin_assignment) { 2050 case 0x0: 2051 drm_WARN_ON(&dev_priv->drm, 2052 !intel_tc_port_in_legacy_mode(dig_port)); 2053 if (width == 1) { 2054 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2055 } else { 2056 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2057 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2058 } 2059 break; 2060 case 0x1: 2061 if (width == 4) { 2062 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2063 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2064 } 2065 break; 2066 case 0x2: 2067 if (width == 2) { 2068 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2069 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2070 } 2071 break; 2072 case 0x3: 2073 case 0x5: 2074 if (width == 1) { 2075 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2076 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2077 } else { 2078 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2079 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2080 } 2081 break; 2082 case 0x4: 2083 case 0x6: 2084 if (width == 1) { 2085 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2086 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2087 } else { 2088 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2089 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2090 } 2091 break; 2092 default: 2093 MISSING_CASE(pin_assignment); 2094 } 2095 2096 if (DISPLAY_VER(dev_priv) >= 12) { 2097 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2098 HIP_INDEX_VAL(tc_port, 0x0)); 2099 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0); 2100 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2101 HIP_INDEX_VAL(tc_port, 0x1)); 2102 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1); 2103 } else { 2104 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 2105 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 2106 } 2107 } 2108 2109 static enum transcoder 2110 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2111 { 2112 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2113 return crtc_state->mst_master_transcoder; 2114 else 2115 return crtc_state->cpu_transcoder; 2116 } 2117 2118 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2119 const struct intel_crtc_state *crtc_state) 2120 { 2121 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2122 2123 if (DISPLAY_VER(dev_priv) >= 12) 2124 return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state)); 2125 else 2126 return DP_TP_CTL(encoder->port); 2127 } 2128 2129 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2130 const struct intel_crtc_state *crtc_state) 2131 { 2132 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2133 2134 if (DISPLAY_VER(dev_priv) >= 12) 2135 return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state)); 2136 else 2137 return DP_TP_STATUS(encoder->port); 2138 } 2139 2140 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2141 const struct intel_crtc_state *crtc_state, 2142 bool enable) 2143 { 2144 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2145 2146 if (!crtc_state->vrr.enable) 2147 return; 2148 2149 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2150 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2151 drm_dbg_kms(&i915->drm, 2152 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2153 enabledisable(enable)); 2154 } 2155 2156 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2157 const struct intel_crtc_state *crtc_state) 2158 { 2159 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2160 2161 if (!crtc_state->fec_enable) 2162 return; 2163 2164 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0) 2165 drm_dbg_kms(&i915->drm, 2166 "Failed to set FEC_READY in the sink\n"); 2167 } 2168 2169 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2170 const struct intel_crtc_state *crtc_state) 2171 { 2172 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2173 struct intel_dp *intel_dp; 2174 u32 val; 2175 2176 if (!crtc_state->fec_enable) 2177 return; 2178 2179 intel_dp = enc_to_intel_dp(encoder); 2180 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2181 val |= DP_TP_CTL_FEC_ENABLE; 2182 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 2183 } 2184 2185 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder, 2186 const struct intel_crtc_state *crtc_state) 2187 { 2188 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2189 struct intel_dp *intel_dp; 2190 u32 val; 2191 2192 if (!crtc_state->fec_enable) 2193 return; 2194 2195 intel_dp = enc_to_intel_dp(encoder); 2196 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2197 val &= ~DP_TP_CTL_FEC_ENABLE; 2198 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 2199 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2200 } 2201 2202 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2203 const struct intel_crtc_state *crtc_state) 2204 { 2205 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2206 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2207 enum phy phy = intel_port_to_phy(i915, encoder->port); 2208 2209 if (intel_phy_is_combo(i915, phy)) { 2210 bool lane_reversal = 2211 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 2212 2213 intel_combo_phy_power_up_lanes(i915, phy, false, 2214 crtc_state->lane_count, 2215 lane_reversal); 2216 } 2217 } 2218 2219 /* Splitter enable for eDP MSO is limited to certain pipes. */ 2220 static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915) 2221 { 2222 if (IS_ALDERLAKE_P(i915)) 2223 return BIT(PIPE_A) | BIT(PIPE_B); 2224 else 2225 return BIT(PIPE_A); 2226 } 2227 2228 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2229 struct intel_crtc_state *pipe_config) 2230 { 2231 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2232 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2233 enum pipe pipe = crtc->pipe; 2234 u32 dss1; 2235 2236 if (!HAS_MSO(i915)) 2237 return; 2238 2239 dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); 2240 2241 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2242 if (!pipe_config->splitter.enable) 2243 return; 2244 2245 if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) { 2246 pipe_config->splitter.enable = false; 2247 return; 2248 } 2249 2250 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2251 default: 2252 drm_WARN(&i915->drm, true, 2253 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2254 fallthrough; 2255 case SPLITTER_CONFIGURATION_2_SEGMENT: 2256 pipe_config->splitter.link_count = 2; 2257 break; 2258 case SPLITTER_CONFIGURATION_4_SEGMENT: 2259 pipe_config->splitter.link_count = 4; 2260 break; 2261 } 2262 2263 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2264 } 2265 2266 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2267 { 2268 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2269 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2270 enum pipe pipe = crtc->pipe; 2271 u32 dss1 = 0; 2272 2273 if (!HAS_MSO(i915)) 2274 return; 2275 2276 if (crtc_state->splitter.enable) { 2277 dss1 |= SPLITTER_ENABLE; 2278 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2279 if (crtc_state->splitter.link_count == 2) 2280 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2281 else 2282 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2283 } 2284 2285 intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), 2286 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2287 OVERLAP_PIXELS_MASK, dss1); 2288 } 2289 2290 static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state, 2291 struct intel_encoder *encoder, 2292 const struct intel_crtc_state *crtc_state, 2293 const struct drm_connector_state *conn_state) 2294 { 2295 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2296 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2297 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2298 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2299 2300 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, 2301 crtc_state->lane_count); 2302 2303 /* 2304 * We only configure what the register value will be here. Actual 2305 * enabling happens during link training farther down. 2306 */ 2307 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2308 2309 /* 2310 * 1. Enable Power Wells 2311 * 2312 * This was handled at the beginning of intel_atomic_commit_tail(), 2313 * before we called down into this function. 2314 */ 2315 2316 /* 2. Enable Panel Power if PPS is required */ 2317 intel_pps_on(intel_dp); 2318 2319 /* 2320 * 3. Enable the port PLL. 2321 */ 2322 intel_ddi_enable_clock(encoder, crtc_state); 2323 2324 /* 4. Enable IO power */ 2325 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 2326 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2327 dig_port->ddi_io_power_domain); 2328 2329 /* 2330 * 5. The rest of the below are substeps under the bspec's "Enable and 2331 * Train Display Port" step. Note that steps that are specific to 2332 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2333 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2334 * us when active_mst_links==0, so any steps designated for "single 2335 * stream or multi-stream master transcoder" can just be performed 2336 * unconditionally here. 2337 */ 2338 2339 /* 2340 * 5.a Configure Transcoder Clock Select to direct the Port clock to the 2341 * Transcoder. 2342 */ 2343 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2344 2345 /* 5.b Configure transcoder for DP 2.0 128b/132b */ 2346 intel_ddi_config_transcoder_dp2(encoder, crtc_state); 2347 2348 /* 2349 * 5.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2350 * Transport Select 2351 */ 2352 intel_ddi_config_transcoder_func(encoder, crtc_state); 2353 2354 /* 2355 * 5.d Configure & enable DP_TP_CTL with link training pattern 1 2356 * selected 2357 * 2358 * This will be handled by the intel_dp_start_link_train() farther 2359 * down this function. 2360 */ 2361 2362 /* 5.e Configure voltage swing and related IO settings */ 2363 encoder->set_signal_levels(encoder, crtc_state); 2364 2365 if (!is_mst) 2366 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2367 2368 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2369 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); 2370 /* 2371 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2372 * in the FEC_CONFIGURATION register to 1 before initiating link 2373 * training 2374 */ 2375 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 2376 intel_dp_check_frl_training(intel_dp); 2377 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2378 2379 /* 2380 * 5.h Follow DisplayPort specification training sequence (see notes for 2381 * failure handling) 2382 * 5.i If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2383 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2384 * (timeout after 800 us) 2385 */ 2386 intel_dp_start_link_train(intel_dp, crtc_state); 2387 2388 /* 5.j Set DP_TP_CTL link training to Normal */ 2389 if (!is_trans_port_sync_mode(crtc_state)) 2390 intel_dp_stop_link_train(intel_dp, crtc_state); 2391 2392 /* 5.k Configure and enable FEC if needed */ 2393 intel_ddi_enable_fec(encoder, crtc_state); 2394 2395 intel_dsc_dp_pps_write(encoder, crtc_state); 2396 2397 intel_dsc_enable(crtc_state); 2398 } 2399 2400 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2401 struct intel_encoder *encoder, 2402 const struct intel_crtc_state *crtc_state, 2403 const struct drm_connector_state *conn_state) 2404 { 2405 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2406 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2407 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2408 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2409 2410 intel_dp_set_link_params(intel_dp, 2411 crtc_state->port_clock, 2412 crtc_state->lane_count); 2413 2414 /* 2415 * We only configure what the register value will be here. Actual 2416 * enabling happens during link training farther down. 2417 */ 2418 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2419 2420 /* 2421 * 1. Enable Power Wells 2422 * 2423 * This was handled at the beginning of intel_atomic_commit_tail(), 2424 * before we called down into this function. 2425 */ 2426 2427 /* 2. Enable Panel Power if PPS is required */ 2428 intel_pps_on(intel_dp); 2429 2430 /* 2431 * 3. For non-TBT Type-C ports, set FIA lane count 2432 * (DFLEXDPSP.DPX4TXLATC) 2433 * 2434 * This was done before tgl_ddi_pre_enable_dp by 2435 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2436 */ 2437 2438 /* 2439 * 4. Enable the port PLL. 2440 * 2441 * The PLL enabling itself was already done before this function by 2442 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 2443 * configure the PLL to port mapping here. 2444 */ 2445 intel_ddi_enable_clock(encoder, crtc_state); 2446 2447 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2448 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2449 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2450 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2451 dig_port->ddi_io_power_domain); 2452 } 2453 2454 /* 6. Program DP_MODE */ 2455 icl_program_mg_dp_mode(dig_port, crtc_state); 2456 2457 /* 2458 * 7. The rest of the below are substeps under the bspec's "Enable and 2459 * Train Display Port" step. Note that steps that are specific to 2460 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2461 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2462 * us when active_mst_links==0, so any steps designated for "single 2463 * stream or multi-stream master transcoder" can just be performed 2464 * unconditionally here. 2465 */ 2466 2467 /* 2468 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2469 * Transcoder. 2470 */ 2471 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2472 2473 /* 2474 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2475 * Transport Select 2476 */ 2477 intel_ddi_config_transcoder_func(encoder, crtc_state); 2478 2479 /* 2480 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2481 * selected 2482 * 2483 * This will be handled by the intel_dp_start_link_train() farther 2484 * down this function. 2485 */ 2486 2487 /* 7.e Configure voltage swing and related IO settings */ 2488 encoder->set_signal_levels(encoder, crtc_state); 2489 2490 /* 2491 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2492 * the used lanes of the DDI. 2493 */ 2494 intel_ddi_power_up_lanes(encoder, crtc_state); 2495 2496 /* 2497 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2498 */ 2499 intel_ddi_mso_configure(crtc_state); 2500 2501 if (!is_mst) 2502 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2503 2504 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2505 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); 2506 /* 2507 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2508 * in the FEC_CONFIGURATION register to 1 before initiating link 2509 * training 2510 */ 2511 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 2512 2513 intel_dp_check_frl_training(intel_dp); 2514 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2515 2516 /* 2517 * 7.i Follow DisplayPort specification training sequence (see notes for 2518 * failure handling) 2519 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2520 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2521 * (timeout after 800 us) 2522 */ 2523 intel_dp_start_link_train(intel_dp, crtc_state); 2524 2525 /* 7.k Set DP_TP_CTL link training to Normal */ 2526 if (!is_trans_port_sync_mode(crtc_state)) 2527 intel_dp_stop_link_train(intel_dp, crtc_state); 2528 2529 /* 7.l Configure and enable FEC if needed */ 2530 intel_ddi_enable_fec(encoder, crtc_state); 2531 2532 intel_dsc_dp_pps_write(encoder, crtc_state); 2533 2534 if (!crtc_state->bigjoiner) 2535 intel_dsc_enable(crtc_state); 2536 } 2537 2538 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2539 struct intel_encoder *encoder, 2540 const struct intel_crtc_state *crtc_state, 2541 const struct drm_connector_state *conn_state) 2542 { 2543 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2544 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2545 enum port port = encoder->port; 2546 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2547 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2548 2549 if (DISPLAY_VER(dev_priv) < 11) 2550 drm_WARN_ON(&dev_priv->drm, 2551 is_mst && (port == PORT_A || port == PORT_E)); 2552 else 2553 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 2554 2555 intel_dp_set_link_params(intel_dp, 2556 crtc_state->port_clock, 2557 crtc_state->lane_count); 2558 2559 /* 2560 * We only configure what the register value will be here. Actual 2561 * enabling happens during link training farther down. 2562 */ 2563 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2564 2565 intel_pps_on(intel_dp); 2566 2567 intel_ddi_enable_clock(encoder, crtc_state); 2568 2569 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2570 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2571 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2572 dig_port->ddi_io_power_domain); 2573 } 2574 2575 icl_program_mg_dp_mode(dig_port, crtc_state); 2576 2577 if (has_buf_trans_select(dev_priv)) 2578 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2579 2580 encoder->set_signal_levels(encoder, crtc_state); 2581 2582 intel_ddi_power_up_lanes(encoder, crtc_state); 2583 2584 if (!is_mst) 2585 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2586 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2587 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, 2588 true); 2589 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 2590 intel_dp_start_link_train(intel_dp, crtc_state); 2591 if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && 2592 !is_trans_port_sync_mode(crtc_state)) 2593 intel_dp_stop_link_train(intel_dp, crtc_state); 2594 2595 intel_ddi_enable_fec(encoder, crtc_state); 2596 2597 if (!is_mst) 2598 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2599 2600 intel_dsc_dp_pps_write(encoder, crtc_state); 2601 2602 if (!crtc_state->bigjoiner) 2603 intel_dsc_enable(crtc_state); 2604 } 2605 2606 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2607 struct intel_encoder *encoder, 2608 const struct intel_crtc_state *crtc_state, 2609 const struct drm_connector_state *conn_state) 2610 { 2611 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2612 2613 if (IS_DG2(dev_priv)) 2614 dg2_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2615 else if (DISPLAY_VER(dev_priv) >= 12) 2616 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2617 else 2618 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2619 2620 /* MST will call a setting of MSA after an allocating of Virtual Channel 2621 * from MST encoder pre_enable callback. 2622 */ 2623 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 2624 intel_ddi_set_dp_msa(crtc_state, conn_state); 2625 2626 intel_dp_set_m_n(crtc_state, M1_N1); 2627 } 2628 } 2629 2630 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2631 struct intel_encoder *encoder, 2632 const struct intel_crtc_state *crtc_state, 2633 const struct drm_connector_state *conn_state) 2634 { 2635 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2636 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2637 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2638 2639 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2640 intel_ddi_enable_clock(encoder, crtc_state); 2641 2642 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2643 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2644 dig_port->ddi_io_power_domain); 2645 2646 icl_program_mg_dp_mode(dig_port, crtc_state); 2647 2648 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2649 2650 dig_port->set_infoframes(encoder, 2651 crtc_state->has_infoframe, 2652 crtc_state, conn_state); 2653 } 2654 2655 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 2656 struct intel_encoder *encoder, 2657 const struct intel_crtc_state *crtc_state, 2658 const struct drm_connector_state *conn_state) 2659 { 2660 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2661 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2662 enum pipe pipe = crtc->pipe; 2663 2664 /* 2665 * When called from DP MST code: 2666 * - conn_state will be NULL 2667 * - encoder will be the main encoder (ie. mst->primary) 2668 * - the main connector associated with this port 2669 * won't be active or linked to a crtc 2670 * - crtc_state will be the state of the first stream to 2671 * be activated on this port, and it may not be the same 2672 * stream that will be deactivated last, but each stream 2673 * should have a state that is identical when it comes to 2674 * the DP link parameteres 2675 */ 2676 2677 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 2678 2679 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2680 2681 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 2682 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 2683 conn_state); 2684 } else { 2685 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2686 2687 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 2688 conn_state); 2689 2690 /* FIXME precompute everything properly */ 2691 /* FIXME how do we turn infoframes off again? */ 2692 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) 2693 dig_port->set_infoframes(encoder, 2694 crtc_state->has_infoframe, 2695 crtc_state, conn_state); 2696 } 2697 } 2698 2699 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 2700 const struct intel_crtc_state *crtc_state) 2701 { 2702 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2703 enum port port = encoder->port; 2704 bool wait = false; 2705 u32 val; 2706 2707 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2708 if (val & DDI_BUF_CTL_ENABLE) { 2709 val &= ~DDI_BUF_CTL_ENABLE; 2710 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 2711 wait = true; 2712 } 2713 2714 if (intel_crtc_has_dp_encoder(crtc_state)) { 2715 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2716 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 2717 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 2718 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 2719 } 2720 2721 /* Disable FEC in DP Sink */ 2722 intel_ddi_disable_fec_state(encoder, crtc_state); 2723 2724 if (wait) 2725 intel_wait_ddi_buf_idle(dev_priv, port); 2726 } 2727 2728 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 2729 struct intel_encoder *encoder, 2730 const struct intel_crtc_state *old_crtc_state, 2731 const struct drm_connector_state *old_conn_state) 2732 { 2733 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2734 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2735 struct intel_dp *intel_dp = &dig_port->dp; 2736 bool is_mst = intel_crtc_has_type(old_crtc_state, 2737 INTEL_OUTPUT_DP_MST); 2738 2739 if (!is_mst) 2740 intel_dp_set_infoframes(encoder, false, 2741 old_crtc_state, old_conn_state); 2742 2743 /* 2744 * Power down sink before disabling the port, otherwise we end 2745 * up getting interrupts from the sink on detecting link loss. 2746 */ 2747 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 2748 2749 if (DISPLAY_VER(dev_priv) >= 12) { 2750 if (is_mst) { 2751 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 2752 u32 val; 2753 2754 val = intel_de_read(dev_priv, 2755 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 2756 val &= ~(TGL_TRANS_DDI_PORT_MASK | 2757 TRANS_DDI_MODE_SELECT_MASK); 2758 intel_de_write(dev_priv, 2759 TRANS_DDI_FUNC_CTL(cpu_transcoder), 2760 val); 2761 } 2762 } else { 2763 if (!is_mst) 2764 intel_ddi_disable_pipe_clock(old_crtc_state); 2765 } 2766 2767 intel_disable_ddi_buf(encoder, old_crtc_state); 2768 2769 /* 2770 * From TGL spec: "If single stream or multi-stream master transcoder: 2771 * Configure Transcoder Clock select to direct no clock to the 2772 * transcoder" 2773 */ 2774 if (DISPLAY_VER(dev_priv) >= 12) 2775 intel_ddi_disable_pipe_clock(old_crtc_state); 2776 2777 intel_pps_vdd_on(intel_dp); 2778 intel_pps_off(intel_dp); 2779 2780 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 2781 intel_display_power_put(dev_priv, 2782 dig_port->ddi_io_power_domain, 2783 fetch_and_zero(&dig_port->ddi_io_wakeref)); 2784 2785 intel_ddi_disable_clock(encoder); 2786 } 2787 2788 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 2789 struct intel_encoder *encoder, 2790 const struct intel_crtc_state *old_crtc_state, 2791 const struct drm_connector_state *old_conn_state) 2792 { 2793 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2794 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2795 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2796 2797 dig_port->set_infoframes(encoder, false, 2798 old_crtc_state, old_conn_state); 2799 2800 intel_ddi_disable_pipe_clock(old_crtc_state); 2801 2802 intel_disable_ddi_buf(encoder, old_crtc_state); 2803 2804 intel_display_power_put(dev_priv, 2805 dig_port->ddi_io_power_domain, 2806 fetch_and_zero(&dig_port->ddi_io_wakeref)); 2807 2808 intel_ddi_disable_clock(encoder); 2809 2810 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 2811 } 2812 2813 static void intel_ddi_post_disable(struct intel_atomic_state *state, 2814 struct intel_encoder *encoder, 2815 const struct intel_crtc_state *old_crtc_state, 2816 const struct drm_connector_state *old_conn_state) 2817 { 2818 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2819 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2820 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2821 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 2822 2823 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) { 2824 intel_crtc_vblank_off(old_crtc_state); 2825 2826 intel_disable_transcoder(old_crtc_state); 2827 2828 intel_vrr_disable(old_crtc_state); 2829 2830 intel_ddi_disable_transcoder_func(old_crtc_state); 2831 2832 intel_dsc_disable(old_crtc_state); 2833 2834 if (DISPLAY_VER(dev_priv) >= 9) 2835 skl_scaler_disable(old_crtc_state); 2836 else 2837 ilk_pfit_disable(old_crtc_state); 2838 } 2839 2840 if (old_crtc_state->bigjoiner_linked_crtc) { 2841 struct intel_crtc *slave_crtc = 2842 old_crtc_state->bigjoiner_linked_crtc; 2843 const struct intel_crtc_state *old_slave_crtc_state = 2844 intel_atomic_get_old_crtc_state(state, slave_crtc); 2845 2846 intel_crtc_vblank_off(old_slave_crtc_state); 2847 2848 intel_dsc_disable(old_slave_crtc_state); 2849 skl_scaler_disable(old_slave_crtc_state); 2850 } 2851 2852 /* 2853 * When called from DP MST code: 2854 * - old_conn_state will be NULL 2855 * - encoder will be the main encoder (ie. mst->primary) 2856 * - the main connector associated with this port 2857 * won't be active or linked to a crtc 2858 * - old_crtc_state will be the state of the last stream to 2859 * be deactivated on this port, and it may not be the same 2860 * stream that was activated last, but each stream 2861 * should have a state that is identical when it comes to 2862 * the DP link parameteres 2863 */ 2864 2865 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 2866 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 2867 old_conn_state); 2868 else 2869 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 2870 old_conn_state); 2871 2872 if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port) 2873 intel_display_power_put(dev_priv, 2874 intel_ddi_main_link_aux_domain(dig_port), 2875 fetch_and_zero(&dig_port->aux_wakeref)); 2876 2877 if (is_tc_port) 2878 intel_tc_port_put_link(dig_port); 2879 } 2880 2881 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 2882 struct intel_encoder *encoder, 2883 const struct intel_crtc_state *crtc_state) 2884 { 2885 const struct drm_connector_state *conn_state; 2886 struct drm_connector *conn; 2887 int i; 2888 2889 if (!crtc_state->sync_mode_slaves_mask) 2890 return; 2891 2892 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 2893 struct intel_encoder *slave_encoder = 2894 to_intel_encoder(conn_state->best_encoder); 2895 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 2896 const struct intel_crtc_state *slave_crtc_state; 2897 2898 if (!slave_crtc) 2899 continue; 2900 2901 slave_crtc_state = 2902 intel_atomic_get_new_crtc_state(state, slave_crtc); 2903 2904 if (slave_crtc_state->master_transcoder != 2905 crtc_state->cpu_transcoder) 2906 continue; 2907 2908 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 2909 slave_crtc_state); 2910 } 2911 2912 usleep_range(200, 400); 2913 2914 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 2915 crtc_state); 2916 } 2917 2918 static void intel_enable_ddi_dp(struct intel_atomic_state *state, 2919 struct intel_encoder *encoder, 2920 const struct intel_crtc_state *crtc_state, 2921 const struct drm_connector_state *conn_state) 2922 { 2923 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2924 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2925 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2926 enum port port = encoder->port; 2927 2928 if (port == PORT_A && DISPLAY_VER(dev_priv) < 9) 2929 intel_dp_stop_link_train(intel_dp, crtc_state); 2930 2931 drm_connector_update_privacy_screen(conn_state); 2932 intel_edp_backlight_on(crtc_state, conn_state); 2933 2934 if (!dig_port->lspcon.active || dig_port->dp.has_hdmi_sink) 2935 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 2936 2937 intel_drrs_enable(intel_dp, crtc_state); 2938 2939 if (crtc_state->has_audio) 2940 intel_audio_codec_enable(encoder, crtc_state, conn_state); 2941 2942 trans_port_sync_stop_link_train(state, encoder, crtc_state); 2943 } 2944 2945 static i915_reg_t 2946 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 2947 enum port port) 2948 { 2949 static const enum transcoder trans[] = { 2950 [PORT_A] = TRANSCODER_EDP, 2951 [PORT_B] = TRANSCODER_A, 2952 [PORT_C] = TRANSCODER_B, 2953 [PORT_D] = TRANSCODER_C, 2954 [PORT_E] = TRANSCODER_A, 2955 }; 2956 2957 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9); 2958 2959 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) 2960 port = PORT_A; 2961 2962 return CHICKEN_TRANS(trans[port]); 2963 } 2964 2965 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, 2966 struct intel_encoder *encoder, 2967 const struct intel_crtc_state *crtc_state, 2968 const struct drm_connector_state *conn_state) 2969 { 2970 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2971 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2972 struct drm_connector *connector = conn_state->connector; 2973 enum port port = encoder->port; 2974 2975 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 2976 crtc_state->hdmi_high_tmds_clock_ratio, 2977 crtc_state->hdmi_scrambling)) 2978 drm_dbg_kms(&dev_priv->drm, 2979 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 2980 connector->base.id, connector->name); 2981 2982 if (has_buf_trans_select(dev_priv)) 2983 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 2984 2985 encoder->set_signal_levels(encoder, crtc_state); 2986 2987 /* Display WA #1143: skl,kbl,cfl */ 2988 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { 2989 /* 2990 * For some reason these chicken bits have been 2991 * stuffed into a transcoder register, event though 2992 * the bits affect a specific DDI port rather than 2993 * a specific transcoder. 2994 */ 2995 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 2996 u32 val; 2997 2998 val = intel_de_read(dev_priv, reg); 2999 3000 if (port == PORT_E) 3001 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3002 DDIE_TRAINING_OVERRIDE_VALUE; 3003 else 3004 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3005 DDI_TRAINING_OVERRIDE_VALUE; 3006 3007 intel_de_write(dev_priv, reg, val); 3008 intel_de_posting_read(dev_priv, reg); 3009 3010 udelay(1); 3011 3012 if (port == PORT_E) 3013 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3014 DDIE_TRAINING_OVERRIDE_VALUE); 3015 else 3016 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3017 DDI_TRAINING_OVERRIDE_VALUE); 3018 3019 intel_de_write(dev_priv, reg, val); 3020 } 3021 3022 intel_ddi_power_up_lanes(encoder, crtc_state); 3023 3024 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3025 * are ignored so nothing special needs to be done besides 3026 * enabling the port. 3027 * 3028 * On ADL_P the PHY link rate and lane count must be programmed but 3029 * these are both 0 for HDMI. 3030 */ 3031 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3032 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE); 3033 3034 if (crtc_state->has_audio) 3035 intel_audio_codec_enable(encoder, crtc_state, conn_state); 3036 } 3037 3038 static void intel_enable_ddi(struct intel_atomic_state *state, 3039 struct intel_encoder *encoder, 3040 const struct intel_crtc_state *crtc_state, 3041 const struct drm_connector_state *conn_state) 3042 { 3043 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 3044 3045 if (!crtc_state->bigjoiner_slave) 3046 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3047 3048 intel_vrr_enable(encoder, crtc_state); 3049 3050 intel_enable_transcoder(crtc_state); 3051 3052 intel_crtc_vblank_on(crtc_state); 3053 3054 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3055 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state); 3056 else 3057 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state); 3058 3059 /* Enable hdcp if it's desired */ 3060 if (conn_state->content_protection == 3061 DRM_MODE_CONTENT_PROTECTION_DESIRED) 3062 intel_hdcp_enable(to_intel_connector(conn_state->connector), 3063 crtc_state, 3064 (u8)conn_state->hdcp_content_type); 3065 } 3066 3067 static void intel_disable_ddi_dp(struct intel_atomic_state *state, 3068 struct intel_encoder *encoder, 3069 const struct intel_crtc_state *old_crtc_state, 3070 const struct drm_connector_state *old_conn_state) 3071 { 3072 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3073 3074 intel_dp->link_trained = false; 3075 3076 if (old_crtc_state->has_audio) 3077 intel_audio_codec_disable(encoder, 3078 old_crtc_state, old_conn_state); 3079 3080 intel_drrs_disable(intel_dp, old_crtc_state); 3081 intel_psr_disable(intel_dp, old_crtc_state); 3082 intel_edp_backlight_off(old_conn_state); 3083 /* Disable the decompression in DP Sink */ 3084 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, 3085 false); 3086 /* Disable Ignore_MSA bit in DP Sink */ 3087 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 3088 false); 3089 } 3090 3091 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state, 3092 struct intel_encoder *encoder, 3093 const struct intel_crtc_state *old_crtc_state, 3094 const struct drm_connector_state *old_conn_state) 3095 { 3096 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3097 struct drm_connector *connector = old_conn_state->connector; 3098 3099 if (old_crtc_state->has_audio) 3100 intel_audio_codec_disable(encoder, 3101 old_crtc_state, old_conn_state); 3102 3103 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3104 false, false)) 3105 drm_dbg_kms(&i915->drm, 3106 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3107 connector->base.id, connector->name); 3108 } 3109 3110 static void intel_disable_ddi(struct intel_atomic_state *state, 3111 struct intel_encoder *encoder, 3112 const struct intel_crtc_state *old_crtc_state, 3113 const struct drm_connector_state *old_conn_state) 3114 { 3115 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3116 3117 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3118 intel_disable_ddi_hdmi(state, encoder, old_crtc_state, 3119 old_conn_state); 3120 else 3121 intel_disable_ddi_dp(state, encoder, old_crtc_state, 3122 old_conn_state); 3123 } 3124 3125 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3126 struct intel_encoder *encoder, 3127 const struct intel_crtc_state *crtc_state, 3128 const struct drm_connector_state *conn_state) 3129 { 3130 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3131 3132 intel_ddi_set_dp_msa(crtc_state, conn_state); 3133 3134 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3135 intel_drrs_update(intel_dp, crtc_state); 3136 3137 intel_backlight_update(state, encoder, crtc_state, conn_state); 3138 drm_connector_update_privacy_screen(conn_state); 3139 } 3140 3141 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3142 struct intel_encoder *encoder, 3143 const struct intel_crtc_state *crtc_state, 3144 const struct drm_connector_state *conn_state) 3145 { 3146 3147 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3148 !intel_encoder_is_mst(encoder)) 3149 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3150 conn_state); 3151 3152 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3153 } 3154 3155 static void 3156 intel_ddi_update_prepare(struct intel_atomic_state *state, 3157 struct intel_encoder *encoder, 3158 struct intel_crtc *crtc) 3159 { 3160 struct intel_crtc_state *crtc_state = 3161 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL; 3162 int required_lanes = crtc_state ? crtc_state->lane_count : 1; 3163 3164 drm_WARN_ON(state->base.dev, crtc && crtc->active); 3165 3166 intel_tc_port_get_link(enc_to_dig_port(encoder), 3167 required_lanes); 3168 if (crtc_state && crtc_state->hw.active) { 3169 struct intel_crtc *slave_crtc = crtc_state->bigjoiner_linked_crtc; 3170 3171 intel_update_active_dpll(state, crtc, encoder); 3172 3173 if (slave_crtc) 3174 intel_update_active_dpll(state, slave_crtc, encoder); 3175 } 3176 } 3177 3178 static void 3179 intel_ddi_update_complete(struct intel_atomic_state *state, 3180 struct intel_encoder *encoder, 3181 struct intel_crtc *crtc) 3182 { 3183 intel_tc_port_put_link(enc_to_dig_port(encoder)); 3184 } 3185 3186 static void 3187 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3188 struct intel_encoder *encoder, 3189 const struct intel_crtc_state *crtc_state, 3190 const struct drm_connector_state *conn_state) 3191 { 3192 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3193 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3194 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3195 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 3196 3197 if (is_tc_port) 3198 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3199 3200 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) { 3201 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref); 3202 dig_port->aux_wakeref = 3203 intel_display_power_get(dev_priv, 3204 intel_ddi_main_link_aux_domain(dig_port)); 3205 } 3206 3207 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3208 /* 3209 * Program the lane count for static/dynamic connections on 3210 * Type-C ports. Skip this step for TBT. 3211 */ 3212 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3213 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3214 bxt_ddi_phy_set_lane_optim_mask(encoder, 3215 crtc_state->lane_lat_optim_mask); 3216 } 3217 3218 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3219 const struct intel_crtc_state *crtc_state) 3220 { 3221 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3222 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3223 enum port port = encoder->port; 3224 u32 dp_tp_ctl, ddi_buf_ctl; 3225 bool wait = false; 3226 3227 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3228 3229 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 3230 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3231 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 3232 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3233 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 3234 wait = true; 3235 } 3236 3237 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 3238 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1; 3239 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3240 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3241 3242 if (wait) 3243 intel_wait_ddi_buf_idle(dev_priv, port); 3244 } 3245 3246 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3247 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3248 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3249 } else { 3250 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3251 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 3252 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3253 } 3254 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3255 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3256 3257 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3258 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3259 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3260 3261 intel_wait_ddi_buf_active(dev_priv, port); 3262 } 3263 3264 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3265 const struct intel_crtc_state *crtc_state, 3266 u8 dp_train_pat) 3267 { 3268 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3269 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3270 u32 temp; 3271 3272 temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3273 3274 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3275 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3276 case DP_TRAINING_PATTERN_DISABLE: 3277 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3278 break; 3279 case DP_TRAINING_PATTERN_1: 3280 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3281 break; 3282 case DP_TRAINING_PATTERN_2: 3283 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3284 break; 3285 case DP_TRAINING_PATTERN_3: 3286 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3287 break; 3288 case DP_TRAINING_PATTERN_4: 3289 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3290 break; 3291 } 3292 3293 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp); 3294 } 3295 3296 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3297 const struct intel_crtc_state *crtc_state) 3298 { 3299 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3300 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3301 enum port port = encoder->port; 3302 u32 val; 3303 3304 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3305 val &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3306 val |= DP_TP_CTL_LINK_TRAIN_IDLE; 3307 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 3308 3309 /* 3310 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3311 * reason we need to set idle transmission mode is to work around a HW 3312 * issue where we enable the pipe while not in idle link-training mode. 3313 * In this case there is requirement to wait for a minimum number of 3314 * idle patterns to be sent. 3315 */ 3316 if (port == PORT_A && DISPLAY_VER(dev_priv) < 12) 3317 return; 3318 3319 if (intel_de_wait_for_set(dev_priv, 3320 dp_tp_status_reg(encoder, crtc_state), 3321 DP_TP_STATUS_IDLE_DONE, 1)) 3322 drm_err(&dev_priv->drm, 3323 "Timed out waiting for DP idle patterns\n"); 3324 } 3325 3326 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 3327 enum transcoder cpu_transcoder) 3328 { 3329 if (cpu_transcoder == TRANSCODER_EDP) 3330 return false; 3331 3332 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO)) 3333 return false; 3334 3335 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 3336 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3337 } 3338 3339 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, 3340 struct intel_crtc_state *crtc_state) 3341 { 3342 if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000) 3343 crtc_state->min_voltage_level = 2; 3344 else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000) 3345 crtc_state->min_voltage_level = 3; 3346 else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000) 3347 crtc_state->min_voltage_level = 1; 3348 } 3349 3350 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, 3351 enum transcoder cpu_transcoder) 3352 { 3353 u32 master_select; 3354 3355 if (DISPLAY_VER(dev_priv) >= 11) { 3356 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder)); 3357 3358 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3359 return INVALID_TRANSCODER; 3360 3361 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3362 } else { 3363 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3364 3365 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3366 return INVALID_TRANSCODER; 3367 3368 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3369 } 3370 3371 if (master_select == 0) 3372 return TRANSCODER_EDP; 3373 else 3374 return master_select - 1; 3375 } 3376 3377 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3378 { 3379 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3380 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3381 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3382 enum transcoder cpu_transcoder; 3383 3384 crtc_state->master_transcoder = 3385 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); 3386 3387 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { 3388 enum intel_display_power_domain power_domain; 3389 intel_wakeref_t trans_wakeref; 3390 3391 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3392 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 3393 power_domain); 3394 3395 if (!trans_wakeref) 3396 continue; 3397 3398 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == 3399 crtc_state->cpu_transcoder) 3400 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3401 3402 intel_display_power_put(dev_priv, power_domain, trans_wakeref); 3403 } 3404 3405 drm_WARN_ON(&dev_priv->drm, 3406 crtc_state->master_transcoder != INVALID_TRANSCODER && 3407 crtc_state->sync_mode_slaves_mask); 3408 } 3409 3410 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 3411 struct intel_crtc_state *pipe_config) 3412 { 3413 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3414 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3415 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3416 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3417 u32 temp, flags = 0; 3418 3419 temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3420 if (temp & TRANS_DDI_PHSYNC) 3421 flags |= DRM_MODE_FLAG_PHSYNC; 3422 else 3423 flags |= DRM_MODE_FLAG_NHSYNC; 3424 if (temp & TRANS_DDI_PVSYNC) 3425 flags |= DRM_MODE_FLAG_PVSYNC; 3426 else 3427 flags |= DRM_MODE_FLAG_NVSYNC; 3428 3429 pipe_config->hw.adjusted_mode.flags |= flags; 3430 3431 switch (temp & TRANS_DDI_BPC_MASK) { 3432 case TRANS_DDI_BPC_6: 3433 pipe_config->pipe_bpp = 18; 3434 break; 3435 case TRANS_DDI_BPC_8: 3436 pipe_config->pipe_bpp = 24; 3437 break; 3438 case TRANS_DDI_BPC_10: 3439 pipe_config->pipe_bpp = 30; 3440 break; 3441 case TRANS_DDI_BPC_12: 3442 pipe_config->pipe_bpp = 36; 3443 break; 3444 default: 3445 break; 3446 } 3447 3448 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 3449 case TRANS_DDI_MODE_SELECT_HDMI: 3450 pipe_config->has_hdmi_sink = true; 3451 3452 pipe_config->infoframes.enable |= 3453 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3454 3455 if (pipe_config->infoframes.enable) 3456 pipe_config->has_infoframe = true; 3457 3458 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 3459 pipe_config->hdmi_scrambling = true; 3460 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 3461 pipe_config->hdmi_high_tmds_clock_ratio = true; 3462 fallthrough; 3463 case TRANS_DDI_MODE_SELECT_DVI: 3464 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 3465 pipe_config->lane_count = 4; 3466 break; 3467 case TRANS_DDI_MODE_SELECT_DP_SST: 3468 if (encoder->type == INTEL_OUTPUT_EDP) 3469 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 3470 else 3471 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 3472 pipe_config->lane_count = 3473 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3474 intel_dp_get_m_n(crtc, pipe_config); 3475 3476 if (DISPLAY_VER(dev_priv) >= 11) { 3477 i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config); 3478 3479 pipe_config->fec_enable = 3480 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE; 3481 3482 drm_dbg_kms(&dev_priv->drm, 3483 "[ENCODER:%d:%s] Fec status: %u\n", 3484 encoder->base.base.id, encoder->base.name, 3485 pipe_config->fec_enable); 3486 } 3487 3488 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) 3489 pipe_config->infoframes.enable |= 3490 intel_lspcon_infoframes_enabled(encoder, pipe_config); 3491 else 3492 pipe_config->infoframes.enable |= 3493 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3494 break; 3495 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 3496 if (!HAS_DP20(dev_priv)) { 3497 /* FDI */ 3498 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 3499 break; 3500 } 3501 fallthrough; /* 128b/132b */ 3502 case TRANS_DDI_MODE_SELECT_DP_MST: 3503 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 3504 pipe_config->lane_count = 3505 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3506 3507 if (DISPLAY_VER(dev_priv) >= 12) 3508 pipe_config->mst_master_transcoder = 3509 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); 3510 3511 intel_dp_get_m_n(crtc, pipe_config); 3512 3513 pipe_config->infoframes.enable |= 3514 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3515 break; 3516 default: 3517 break; 3518 } 3519 } 3520 3521 static void intel_ddi_get_config(struct intel_encoder *encoder, 3522 struct intel_crtc_state *pipe_config) 3523 { 3524 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3525 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3526 3527 /* XXX: DSI transcoder paranoia */ 3528 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 3529 return; 3530 3531 intel_ddi_read_func_ctl(encoder, pipe_config); 3532 3533 intel_ddi_mso_get_config(encoder, pipe_config); 3534 3535 pipe_config->has_audio = 3536 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 3537 3538 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp && 3539 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { 3540 /* 3541 * This is a big fat ugly hack. 3542 * 3543 * Some machines in UEFI boot mode provide us a VBT that has 18 3544 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 3545 * unknown we fail to light up. Yet the same BIOS boots up with 3546 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 3547 * max, not what it tells us to use. 3548 * 3549 * Note: This will still be broken if the eDP panel is not lit 3550 * up by the BIOS, and thus we can't get the mode at module 3551 * load. 3552 */ 3553 drm_dbg_kms(&dev_priv->drm, 3554 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 3555 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); 3556 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; 3557 } 3558 3559 ddi_dotclock_get(pipe_config); 3560 3561 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3562 pipe_config->lane_lat_optim_mask = 3563 bxt_ddi_phy_get_lane_lat_optim_mask(encoder); 3564 3565 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 3566 3567 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 3568 3569 intel_read_infoframe(encoder, pipe_config, 3570 HDMI_INFOFRAME_TYPE_AVI, 3571 &pipe_config->infoframes.avi); 3572 intel_read_infoframe(encoder, pipe_config, 3573 HDMI_INFOFRAME_TYPE_SPD, 3574 &pipe_config->infoframes.spd); 3575 intel_read_infoframe(encoder, pipe_config, 3576 HDMI_INFOFRAME_TYPE_VENDOR, 3577 &pipe_config->infoframes.hdmi); 3578 intel_read_infoframe(encoder, pipe_config, 3579 HDMI_INFOFRAME_TYPE_DRM, 3580 &pipe_config->infoframes.drm); 3581 3582 if (DISPLAY_VER(dev_priv) >= 8) 3583 bdw_get_trans_port_sync_config(pipe_config); 3584 3585 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 3586 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 3587 3588 intel_psr_get_config(encoder, pipe_config); 3589 } 3590 3591 void intel_ddi_get_clock(struct intel_encoder *encoder, 3592 struct intel_crtc_state *crtc_state, 3593 struct intel_shared_dpll *pll) 3594 { 3595 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3596 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 3597 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 3598 bool pll_active; 3599 3600 if (drm_WARN_ON(&i915->drm, !pll)) 3601 return; 3602 3603 port_dpll->pll = pll; 3604 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 3605 drm_WARN_ON(&i915->drm, !pll_active); 3606 3607 icl_set_active_port_dpll(crtc_state, port_dpll_id); 3608 3609 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 3610 &crtc_state->dpll_hw_state); 3611 } 3612 3613 static void dg2_ddi_get_config(struct intel_encoder *encoder, 3614 struct intel_crtc_state *crtc_state) 3615 { 3616 intel_mpllb_readout_hw_state(encoder, &crtc_state->mpllb_state); 3617 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->mpllb_state); 3618 3619 intel_ddi_get_config(encoder, crtc_state); 3620 } 3621 3622 static void adls_ddi_get_config(struct intel_encoder *encoder, 3623 struct intel_crtc_state *crtc_state) 3624 { 3625 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 3626 intel_ddi_get_config(encoder, crtc_state); 3627 } 3628 3629 static void rkl_ddi_get_config(struct intel_encoder *encoder, 3630 struct intel_crtc_state *crtc_state) 3631 { 3632 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 3633 intel_ddi_get_config(encoder, crtc_state); 3634 } 3635 3636 static void dg1_ddi_get_config(struct intel_encoder *encoder, 3637 struct intel_crtc_state *crtc_state) 3638 { 3639 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 3640 intel_ddi_get_config(encoder, crtc_state); 3641 } 3642 3643 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 3644 struct intel_crtc_state *crtc_state) 3645 { 3646 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 3647 intel_ddi_get_config(encoder, crtc_state); 3648 } 3649 3650 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 3651 struct intel_crtc_state *crtc_state, 3652 struct intel_shared_dpll *pll) 3653 { 3654 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3655 enum icl_port_dpll_id port_dpll_id; 3656 struct icl_port_dpll *port_dpll; 3657 bool pll_active; 3658 3659 if (drm_WARN_ON(&i915->drm, !pll)) 3660 return; 3661 3662 if (intel_get_shared_dpll_id(i915, pll) == DPLL_ID_ICL_TBTPLL) 3663 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 3664 else 3665 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 3666 3667 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 3668 3669 port_dpll->pll = pll; 3670 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 3671 drm_WARN_ON(&i915->drm, !pll_active); 3672 3673 icl_set_active_port_dpll(crtc_state, port_dpll_id); 3674 3675 if (intel_get_shared_dpll_id(i915, crtc_state->shared_dpll) == DPLL_ID_ICL_TBTPLL) 3676 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port); 3677 else 3678 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 3679 &crtc_state->dpll_hw_state); 3680 } 3681 3682 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 3683 struct intel_crtc_state *crtc_state) 3684 { 3685 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 3686 intel_ddi_get_config(encoder, crtc_state); 3687 } 3688 3689 static void bxt_ddi_get_config(struct intel_encoder *encoder, 3690 struct intel_crtc_state *crtc_state) 3691 { 3692 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 3693 intel_ddi_get_config(encoder, crtc_state); 3694 } 3695 3696 static void skl_ddi_get_config(struct intel_encoder *encoder, 3697 struct intel_crtc_state *crtc_state) 3698 { 3699 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 3700 intel_ddi_get_config(encoder, crtc_state); 3701 } 3702 3703 void hsw_ddi_get_config(struct intel_encoder *encoder, 3704 struct intel_crtc_state *crtc_state) 3705 { 3706 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 3707 intel_ddi_get_config(encoder, crtc_state); 3708 } 3709 3710 static void intel_ddi_sync_state(struct intel_encoder *encoder, 3711 const struct intel_crtc_state *crtc_state) 3712 { 3713 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3714 enum phy phy = intel_port_to_phy(i915, encoder->port); 3715 3716 if (intel_phy_is_tc(i915, phy)) 3717 intel_tc_port_sanitize(enc_to_dig_port(encoder)); 3718 3719 if (crtc_state && intel_crtc_has_dp_encoder(crtc_state)) 3720 intel_dp_sync_state(encoder, crtc_state); 3721 } 3722 3723 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 3724 struct intel_crtc_state *crtc_state) 3725 { 3726 if (intel_crtc_has_dp_encoder(crtc_state)) 3727 return intel_dp_initial_fastset_check(encoder, crtc_state); 3728 3729 return true; 3730 } 3731 3732 static enum intel_output_type 3733 intel_ddi_compute_output_type(struct intel_encoder *encoder, 3734 struct intel_crtc_state *crtc_state, 3735 struct drm_connector_state *conn_state) 3736 { 3737 switch (conn_state->connector->connector_type) { 3738 case DRM_MODE_CONNECTOR_HDMIA: 3739 return INTEL_OUTPUT_HDMI; 3740 case DRM_MODE_CONNECTOR_eDP: 3741 return INTEL_OUTPUT_EDP; 3742 case DRM_MODE_CONNECTOR_DisplayPort: 3743 return INTEL_OUTPUT_DP; 3744 default: 3745 MISSING_CASE(conn_state->connector->connector_type); 3746 return INTEL_OUTPUT_UNUSED; 3747 } 3748 } 3749 3750 static int intel_ddi_compute_config(struct intel_encoder *encoder, 3751 struct intel_crtc_state *pipe_config, 3752 struct drm_connector_state *conn_state) 3753 { 3754 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3755 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3756 enum port port = encoder->port; 3757 int ret; 3758 3759 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 3760 pipe_config->cpu_transcoder = TRANSCODER_EDP; 3761 3762 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 3763 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 3764 } else { 3765 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 3766 } 3767 3768 if (ret) 3769 return ret; 3770 3771 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 3772 pipe_config->cpu_transcoder == TRANSCODER_EDP) 3773 pipe_config->pch_pfit.force_thru = 3774 pipe_config->pch_pfit.enabled || 3775 pipe_config->crc_enabled; 3776 3777 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3778 pipe_config->lane_lat_optim_mask = 3779 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 3780 3781 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 3782 3783 return 0; 3784 } 3785 3786 static bool mode_equal(const struct drm_display_mode *mode1, 3787 const struct drm_display_mode *mode2) 3788 { 3789 return drm_mode_match(mode1, mode2, 3790 DRM_MODE_MATCH_TIMINGS | 3791 DRM_MODE_MATCH_FLAGS | 3792 DRM_MODE_MATCH_3D_FLAGS) && 3793 mode1->clock == mode2->clock; /* we want an exact match */ 3794 } 3795 3796 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 3797 const struct intel_link_m_n *m_n_2) 3798 { 3799 return m_n_1->tu == m_n_2->tu && 3800 m_n_1->gmch_m == m_n_2->gmch_m && 3801 m_n_1->gmch_n == m_n_2->gmch_n && 3802 m_n_1->link_m == m_n_2->link_m && 3803 m_n_1->link_n == m_n_2->link_n; 3804 } 3805 3806 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 3807 const struct intel_crtc_state *crtc_state2) 3808 { 3809 return crtc_state1->hw.active && crtc_state2->hw.active && 3810 crtc_state1->output_types == crtc_state2->output_types && 3811 crtc_state1->output_format == crtc_state2->output_format && 3812 crtc_state1->lane_count == crtc_state2->lane_count && 3813 crtc_state1->port_clock == crtc_state2->port_clock && 3814 mode_equal(&crtc_state1->hw.adjusted_mode, 3815 &crtc_state2->hw.adjusted_mode) && 3816 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 3817 } 3818 3819 static u8 3820 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 3821 int tile_group_id) 3822 { 3823 struct drm_connector *connector; 3824 const struct drm_connector_state *conn_state; 3825 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 3826 struct intel_atomic_state *state = 3827 to_intel_atomic_state(ref_crtc_state->uapi.state); 3828 u8 transcoders = 0; 3829 int i; 3830 3831 /* 3832 * We don't enable port sync on BDW due to missing w/as and 3833 * due to not having adjusted the modeset sequence appropriately. 3834 */ 3835 if (DISPLAY_VER(dev_priv) < 9) 3836 return 0; 3837 3838 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 3839 return 0; 3840 3841 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 3842 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 3843 const struct intel_crtc_state *crtc_state; 3844 3845 if (!crtc) 3846 continue; 3847 3848 if (!connector->has_tile || 3849 connector->tile_group->id != 3850 tile_group_id) 3851 continue; 3852 crtc_state = intel_atomic_get_new_crtc_state(state, 3853 crtc); 3854 if (!crtcs_port_sync_compatible(ref_crtc_state, 3855 crtc_state)) 3856 continue; 3857 transcoders |= BIT(crtc_state->cpu_transcoder); 3858 } 3859 3860 return transcoders; 3861 } 3862 3863 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 3864 struct intel_crtc_state *crtc_state, 3865 struct drm_connector_state *conn_state) 3866 { 3867 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3868 struct drm_connector *connector = conn_state->connector; 3869 u8 port_sync_transcoders = 0; 3870 3871 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]", 3872 encoder->base.base.id, encoder->base.name, 3873 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 3874 3875 if (connector->has_tile) 3876 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 3877 connector->tile_group->id); 3878 3879 /* 3880 * EDP Transcoders cannot be ensalved 3881 * make them a master always when present 3882 */ 3883 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 3884 crtc_state->master_transcoder = TRANSCODER_EDP; 3885 else 3886 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 3887 3888 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 3889 crtc_state->master_transcoder = INVALID_TRANSCODER; 3890 crtc_state->sync_mode_slaves_mask = 3891 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 3892 } 3893 3894 return 0; 3895 } 3896 3897 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 3898 { 3899 struct drm_i915_private *i915 = to_i915(encoder->dev); 3900 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 3901 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 3902 3903 intel_dp_encoder_flush_work(encoder); 3904 if (intel_phy_is_tc(i915, phy)) 3905 intel_tc_port_flush_work(dig_port); 3906 intel_display_power_flush_work(i915); 3907 3908 drm_encoder_cleanup(encoder); 3909 kfree(dig_port->hdcp_port_data.streams); 3910 kfree(dig_port); 3911 } 3912 3913 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 3914 { 3915 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 3916 3917 intel_dp->reset_link_params = true; 3918 3919 intel_pps_encoder_reset(intel_dp); 3920 } 3921 3922 static const struct drm_encoder_funcs intel_ddi_funcs = { 3923 .reset = intel_ddi_encoder_reset, 3924 .destroy = intel_ddi_encoder_destroy, 3925 }; 3926 3927 static struct intel_connector * 3928 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 3929 { 3930 struct intel_connector *connector; 3931 enum port port = dig_port->base.port; 3932 3933 connector = intel_connector_alloc(); 3934 if (!connector) 3935 return NULL; 3936 3937 dig_port->dp.output_reg = DDI_BUF_CTL(port); 3938 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 3939 dig_port->dp.set_link_train = intel_ddi_set_link_train; 3940 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 3941 3942 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 3943 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 3944 3945 if (!intel_dp_init_connector(dig_port, connector)) { 3946 kfree(connector); 3947 return NULL; 3948 } 3949 3950 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 3951 struct drm_device *dev = dig_port->base.base.dev; 3952 struct drm_privacy_screen *privacy_screen; 3953 3954 privacy_screen = drm_privacy_screen_get(dev->dev, NULL); 3955 if (!IS_ERR(privacy_screen)) { 3956 drm_connector_attach_privacy_screen_provider(&connector->base, 3957 privacy_screen); 3958 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 3959 drm_warn(dev, "Error getting privacy-screen\n"); 3960 } 3961 } 3962 3963 return connector; 3964 } 3965 3966 static int modeset_pipe(struct drm_crtc *crtc, 3967 struct drm_modeset_acquire_ctx *ctx) 3968 { 3969 struct drm_atomic_state *state; 3970 struct drm_crtc_state *crtc_state; 3971 int ret; 3972 3973 state = drm_atomic_state_alloc(crtc->dev); 3974 if (!state) 3975 return -ENOMEM; 3976 3977 state->acquire_ctx = ctx; 3978 3979 crtc_state = drm_atomic_get_crtc_state(state, crtc); 3980 if (IS_ERR(crtc_state)) { 3981 ret = PTR_ERR(crtc_state); 3982 goto out; 3983 } 3984 3985 crtc_state->connectors_changed = true; 3986 3987 ret = drm_atomic_commit(state); 3988 out: 3989 drm_atomic_state_put(state); 3990 3991 return ret; 3992 } 3993 3994 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 3995 struct drm_modeset_acquire_ctx *ctx) 3996 { 3997 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3998 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 3999 struct intel_connector *connector = hdmi->attached_connector; 4000 struct i2c_adapter *adapter = 4001 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 4002 struct drm_connector_state *conn_state; 4003 struct intel_crtc_state *crtc_state; 4004 struct intel_crtc *crtc; 4005 u8 config; 4006 int ret; 4007 4008 if (!connector || connector->base.status != connector_status_connected) 4009 return 0; 4010 4011 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 4012 ctx); 4013 if (ret) 4014 return ret; 4015 4016 conn_state = connector->base.state; 4017 4018 crtc = to_intel_crtc(conn_state->crtc); 4019 if (!crtc) 4020 return 0; 4021 4022 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4023 if (ret) 4024 return ret; 4025 4026 crtc_state = to_intel_crtc_state(crtc->base.state); 4027 4028 drm_WARN_ON(&dev_priv->drm, 4029 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4030 4031 if (!crtc_state->hw.active) 4032 return 0; 4033 4034 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4035 !crtc_state->hdmi_scrambling) 4036 return 0; 4037 4038 if (conn_state->commit && 4039 !try_wait_for_completion(&conn_state->commit->hw_done)) 4040 return 0; 4041 4042 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 4043 if (ret < 0) { 4044 drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n", 4045 ret); 4046 return 0; 4047 } 4048 4049 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4050 crtc_state->hdmi_high_tmds_clock_ratio && 4051 !!(config & SCDC_SCRAMBLING_ENABLE) == 4052 crtc_state->hdmi_scrambling) 4053 return 0; 4054 4055 /* 4056 * HDMI 2.0 says that one should not send scrambled data 4057 * prior to configuring the sink scrambling, and that 4058 * TMDS clock/data transmission should be suspended when 4059 * changing the TMDS clock rate in the sink. So let's 4060 * just do a full modeset here, even though some sinks 4061 * would be perfectly happy if were to just reconfigure 4062 * the SCDC settings on the fly. 4063 */ 4064 return modeset_pipe(&crtc->base, ctx); 4065 } 4066 4067 static enum intel_hotplug_state 4068 intel_ddi_hotplug(struct intel_encoder *encoder, 4069 struct intel_connector *connector) 4070 { 4071 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4072 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4073 struct intel_dp *intel_dp = &dig_port->dp; 4074 enum phy phy = intel_port_to_phy(i915, encoder->port); 4075 bool is_tc = intel_phy_is_tc(i915, phy); 4076 struct drm_modeset_acquire_ctx ctx; 4077 enum intel_hotplug_state state; 4078 int ret; 4079 4080 if (intel_dp->compliance.test_active && 4081 intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) { 4082 intel_dp_phy_test(encoder); 4083 /* just do the PHY test and nothing else */ 4084 return INTEL_HOTPLUG_UNCHANGED; 4085 } 4086 4087 state = intel_encoder_hotplug(encoder, connector); 4088 4089 drm_modeset_acquire_init(&ctx, 0); 4090 4091 for (;;) { 4092 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) 4093 ret = intel_hdmi_reset_link(encoder, &ctx); 4094 else 4095 ret = intel_dp_retrain_link(encoder, &ctx); 4096 4097 if (ret == -EDEADLK) { 4098 drm_modeset_backoff(&ctx); 4099 continue; 4100 } 4101 4102 break; 4103 } 4104 4105 drm_modeset_drop_locks(&ctx); 4106 drm_modeset_acquire_fini(&ctx); 4107 drm_WARN(encoder->base.dev, ret, 4108 "Acquiring modeset locks failed with %i\n", ret); 4109 4110 /* 4111 * Unpowered type-c dongles can take some time to boot and be 4112 * responsible, so here giving some time to those dongles to power up 4113 * and then retrying the probe. 4114 * 4115 * On many platforms the HDMI live state signal is known to be 4116 * unreliable, so we can't use it to detect if a sink is connected or 4117 * not. Instead we detect if it's connected based on whether we can 4118 * read the EDID or not. That in turn has a problem during disconnect, 4119 * since the HPD interrupt may be raised before the DDC lines get 4120 * disconnected (due to how the required length of DDC vs. HPD 4121 * connector pins are specified) and so we'll still be able to get a 4122 * valid EDID. To solve this schedule another detection cycle if this 4123 * time around we didn't detect any change in the sink's connection 4124 * status. 4125 * 4126 * Type-c connectors which get their HPD signal deasserted then 4127 * reasserted, without unplugging/replugging the sink from the 4128 * connector, introduce a delay until the AUX channel communication 4129 * becomes functional. Retry the detection for 5 seconds on type-c 4130 * connectors to account for this delay. 4131 */ 4132 if (state == INTEL_HOTPLUG_UNCHANGED && 4133 connector->hotplug_retries < (is_tc ? 5 : 1) && 4134 !dig_port->dp.is_mst) 4135 state = INTEL_HOTPLUG_RETRY; 4136 4137 return state; 4138 } 4139 4140 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4141 { 4142 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4143 u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin]; 4144 4145 return intel_de_read(dev_priv, SDEISR) & bit; 4146 } 4147 4148 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4149 { 4150 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4151 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; 4152 4153 return intel_de_read(dev_priv, DEISR) & bit; 4154 } 4155 4156 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4157 { 4158 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4159 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; 4160 4161 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; 4162 } 4163 4164 static struct intel_connector * 4165 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4166 { 4167 struct intel_connector *connector; 4168 enum port port = dig_port->base.port; 4169 4170 connector = intel_connector_alloc(); 4171 if (!connector) 4172 return NULL; 4173 4174 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4175 intel_hdmi_init_connector(dig_port, connector); 4176 4177 return connector; 4178 } 4179 4180 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4181 { 4182 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4183 4184 if (dig_port->base.port != PORT_A) 4185 return false; 4186 4187 if (dig_port->saved_port_bits & DDI_A_4_LANES) 4188 return false; 4189 4190 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4191 * supported configuration 4192 */ 4193 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4194 return true; 4195 4196 return false; 4197 } 4198 4199 static int 4200 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4201 { 4202 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4203 enum port port = dig_port->base.port; 4204 int max_lanes = 4; 4205 4206 if (DISPLAY_VER(dev_priv) >= 11) 4207 return max_lanes; 4208 4209 if (port == PORT_A || port == PORT_E) { 4210 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4211 max_lanes = port == PORT_A ? 4 : 0; 4212 else 4213 /* Both A and E share 2 lanes */ 4214 max_lanes = 2; 4215 } 4216 4217 /* 4218 * Some BIOS might fail to set this bit on port A if eDP 4219 * wasn't lit up at boot. Force this bit set when needed 4220 * so we use the proper lane count for our calculations. 4221 */ 4222 if (intel_ddi_a_force_4_lanes(dig_port)) { 4223 drm_dbg_kms(&dev_priv->drm, 4224 "Forcing DDI_A_4_LANES for port A\n"); 4225 dig_port->saved_port_bits |= DDI_A_4_LANES; 4226 max_lanes = 4; 4227 } 4228 4229 return max_lanes; 4230 } 4231 4232 static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy) 4233 { 4234 return i915->hti_state & HDPORT_ENABLED && 4235 i915->hti_state & HDPORT_DDI_USED(phy); 4236 } 4237 4238 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv, 4239 enum port port) 4240 { 4241 if (port >= PORT_D_XELPD) 4242 return HPD_PORT_D + port - PORT_D_XELPD; 4243 else if (port >= PORT_TC1) 4244 return HPD_PORT_TC1 + port - PORT_TC1; 4245 else 4246 return HPD_PORT_A + port - PORT_A; 4247 } 4248 4249 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, 4250 enum port port) 4251 { 4252 if (port >= PORT_TC1) 4253 return HPD_PORT_C + port - PORT_TC1; 4254 else 4255 return HPD_PORT_A + port - PORT_A; 4256 } 4257 4258 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, 4259 enum port port) 4260 { 4261 if (port >= PORT_TC1) 4262 return HPD_PORT_TC1 + port - PORT_TC1; 4263 else 4264 return HPD_PORT_A + port - PORT_A; 4265 } 4266 4267 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, 4268 enum port port) 4269 { 4270 if (HAS_PCH_TGP(dev_priv)) 4271 return tgl_hpd_pin(dev_priv, port); 4272 4273 if (port >= PORT_TC1) 4274 return HPD_PORT_C + port - PORT_TC1; 4275 else 4276 return HPD_PORT_A + port - PORT_A; 4277 } 4278 4279 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, 4280 enum port port) 4281 { 4282 if (port >= PORT_C) 4283 return HPD_PORT_TC1 + port - PORT_C; 4284 else 4285 return HPD_PORT_A + port - PORT_A; 4286 } 4287 4288 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, 4289 enum port port) 4290 { 4291 if (port == PORT_D) 4292 return HPD_PORT_A; 4293 4294 if (HAS_PCH_MCC(dev_priv)) 4295 return icl_hpd_pin(dev_priv, port); 4296 4297 return HPD_PORT_A + port - PORT_A; 4298 } 4299 4300 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) 4301 { 4302 if (HAS_PCH_TGP(dev_priv)) 4303 return icl_hpd_pin(dev_priv, port); 4304 4305 return HPD_PORT_A + port - PORT_A; 4306 } 4307 4308 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port) 4309 { 4310 if (DISPLAY_VER(i915) >= 12) 4311 return port >= PORT_TC1; 4312 else if (DISPLAY_VER(i915) >= 11) 4313 return port >= PORT_C; 4314 else 4315 return false; 4316 } 4317 4318 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 4319 { 4320 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4321 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4322 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4323 enum phy phy = intel_port_to_phy(i915, encoder->port); 4324 4325 intel_dp_encoder_suspend(encoder); 4326 4327 if (!intel_phy_is_tc(i915, phy)) 4328 return; 4329 4330 intel_tc_port_flush_work(dig_port); 4331 } 4332 4333 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 4334 { 4335 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4336 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4337 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4338 enum phy phy = intel_port_to_phy(i915, encoder->port); 4339 4340 intel_dp_encoder_shutdown(encoder); 4341 intel_hdmi_encoder_shutdown(encoder); 4342 4343 if (!intel_phy_is_tc(i915, phy)) 4344 return; 4345 4346 intel_tc_port_flush_work(dig_port); 4347 } 4348 4349 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 4350 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 4351 4352 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 4353 { 4354 struct intel_digital_port *dig_port; 4355 struct intel_encoder *encoder; 4356 const struct intel_bios_encoder_data *devdata; 4357 bool init_hdmi, init_dp; 4358 enum phy phy = intel_port_to_phy(dev_priv, port); 4359 4360 /* 4361 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 4362 * have taken over some of the PHYs and made them unavailable to the 4363 * driver. In that case we should skip initializing the corresponding 4364 * outputs. 4365 */ 4366 if (hti_uses_phy(dev_priv, phy)) { 4367 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", 4368 port_name(port), phy_name(phy)); 4369 return; 4370 } 4371 4372 devdata = intel_bios_encoder_data_lookup(dev_priv, port); 4373 if (!devdata) { 4374 drm_dbg_kms(&dev_priv->drm, 4375 "VBT says port %c is not present\n", 4376 port_name(port)); 4377 return; 4378 } 4379 4380 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 4381 intel_bios_encoder_supports_hdmi(devdata); 4382 init_dp = intel_bios_encoder_supports_dp(devdata); 4383 4384 if (intel_bios_is_lspcon_present(dev_priv, port)) { 4385 /* 4386 * Lspcon device needs to be driven with DP connector 4387 * with special detection sequence. So make sure DP 4388 * is initialized before lspcon. 4389 */ 4390 init_dp = true; 4391 init_hdmi = false; 4392 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", 4393 port_name(port)); 4394 } 4395 4396 if (!init_dp && !init_hdmi) { 4397 drm_dbg_kms(&dev_priv->drm, 4398 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 4399 port_name(port)); 4400 return; 4401 } 4402 4403 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 4404 if (!dig_port) 4405 return; 4406 4407 encoder = &dig_port->base; 4408 encoder->devdata = devdata; 4409 4410 if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) { 4411 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4412 DRM_MODE_ENCODER_TMDS, 4413 "DDI %c/PHY %c", 4414 port_name(port - PORT_D_XELPD + PORT_D), 4415 phy_name(phy)); 4416 } else if (DISPLAY_VER(dev_priv) >= 12) { 4417 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4418 4419 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4420 DRM_MODE_ENCODER_TMDS, 4421 "DDI %s%c/PHY %s%c", 4422 port >= PORT_TC1 ? "TC" : "", 4423 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 4424 tc_port != TC_PORT_NONE ? "TC" : "", 4425 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4426 } else if (DISPLAY_VER(dev_priv) >= 11) { 4427 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4428 4429 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4430 DRM_MODE_ENCODER_TMDS, 4431 "DDI %c%s/PHY %s%c", 4432 port_name(port), 4433 port >= PORT_C ? " (TC)" : "", 4434 tc_port != TC_PORT_NONE ? "TC" : "", 4435 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4436 } else { 4437 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4438 DRM_MODE_ENCODER_TMDS, 4439 "DDI %c/PHY %c", port_name(port), phy_name(phy)); 4440 } 4441 4442 mutex_init(&dig_port->hdcp_mutex); 4443 dig_port->num_hdcp_streams = 0; 4444 4445 encoder->hotplug = intel_ddi_hotplug; 4446 encoder->compute_output_type = intel_ddi_compute_output_type; 4447 encoder->compute_config = intel_ddi_compute_config; 4448 encoder->compute_config_late = intel_ddi_compute_config_late; 4449 encoder->enable = intel_enable_ddi; 4450 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 4451 encoder->pre_enable = intel_ddi_pre_enable; 4452 encoder->disable = intel_disable_ddi; 4453 encoder->post_disable = intel_ddi_post_disable; 4454 encoder->update_pipe = intel_ddi_update_pipe; 4455 encoder->get_hw_state = intel_ddi_get_hw_state; 4456 encoder->sync_state = intel_ddi_sync_state; 4457 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 4458 encoder->suspend = intel_ddi_encoder_suspend; 4459 encoder->shutdown = intel_ddi_encoder_shutdown; 4460 encoder->get_power_domains = intel_ddi_get_power_domains; 4461 4462 encoder->type = INTEL_OUTPUT_DDI; 4463 encoder->power_domain = intel_port_to_power_domain(port); 4464 encoder->port = port; 4465 encoder->cloneable = 0; 4466 encoder->pipe_mask = ~0; 4467 4468 if (IS_DG2(dev_priv)) { 4469 encoder->enable_clock = intel_mpllb_enable; 4470 encoder->disable_clock = intel_mpllb_disable; 4471 encoder->get_config = dg2_ddi_get_config; 4472 } else if (IS_ALDERLAKE_S(dev_priv)) { 4473 encoder->enable_clock = adls_ddi_enable_clock; 4474 encoder->disable_clock = adls_ddi_disable_clock; 4475 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 4476 encoder->get_config = adls_ddi_get_config; 4477 } else if (IS_ROCKETLAKE(dev_priv)) { 4478 encoder->enable_clock = rkl_ddi_enable_clock; 4479 encoder->disable_clock = rkl_ddi_disable_clock; 4480 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 4481 encoder->get_config = rkl_ddi_get_config; 4482 } else if (IS_DG1(dev_priv)) { 4483 encoder->enable_clock = dg1_ddi_enable_clock; 4484 encoder->disable_clock = dg1_ddi_disable_clock; 4485 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 4486 encoder->get_config = dg1_ddi_get_config; 4487 } else if (IS_JSL_EHL(dev_priv)) { 4488 if (intel_ddi_is_tc(dev_priv, port)) { 4489 encoder->enable_clock = jsl_ddi_tc_enable_clock; 4490 encoder->disable_clock = jsl_ddi_tc_disable_clock; 4491 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 4492 encoder->get_config = icl_ddi_combo_get_config; 4493 } else { 4494 encoder->enable_clock = icl_ddi_combo_enable_clock; 4495 encoder->disable_clock = icl_ddi_combo_disable_clock; 4496 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 4497 encoder->get_config = icl_ddi_combo_get_config; 4498 } 4499 } else if (DISPLAY_VER(dev_priv) >= 11) { 4500 if (intel_ddi_is_tc(dev_priv, port)) { 4501 encoder->enable_clock = icl_ddi_tc_enable_clock; 4502 encoder->disable_clock = icl_ddi_tc_disable_clock; 4503 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 4504 encoder->get_config = icl_ddi_tc_get_config; 4505 } else { 4506 encoder->enable_clock = icl_ddi_combo_enable_clock; 4507 encoder->disable_clock = icl_ddi_combo_disable_clock; 4508 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 4509 encoder->get_config = icl_ddi_combo_get_config; 4510 } 4511 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 4512 /* BXT/GLK have fixed PLL->port mapping */ 4513 encoder->get_config = bxt_ddi_get_config; 4514 } else if (DISPLAY_VER(dev_priv) == 9) { 4515 encoder->enable_clock = skl_ddi_enable_clock; 4516 encoder->disable_clock = skl_ddi_disable_clock; 4517 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 4518 encoder->get_config = skl_ddi_get_config; 4519 } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 4520 encoder->enable_clock = hsw_ddi_enable_clock; 4521 encoder->disable_clock = hsw_ddi_disable_clock; 4522 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 4523 encoder->get_config = hsw_ddi_get_config; 4524 } 4525 4526 if (IS_DG2(dev_priv)) { 4527 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 4528 } else if (DISPLAY_VER(dev_priv) >= 12) { 4529 if (intel_phy_is_combo(dev_priv, phy)) 4530 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 4531 else 4532 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 4533 } else if (DISPLAY_VER(dev_priv) >= 11) { 4534 if (intel_phy_is_combo(dev_priv, phy)) 4535 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 4536 else 4537 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 4538 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 4539 encoder->set_signal_levels = bxt_ddi_phy_set_signal_levels; 4540 } else { 4541 encoder->set_signal_levels = hsw_set_signal_levels; 4542 } 4543 4544 intel_ddi_buf_trans_init(encoder); 4545 4546 if (DISPLAY_VER(dev_priv) >= 13) 4547 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port); 4548 else if (IS_DG1(dev_priv)) 4549 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); 4550 else if (IS_ROCKETLAKE(dev_priv)) 4551 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); 4552 else if (DISPLAY_VER(dev_priv) >= 12) 4553 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); 4554 else if (IS_JSL_EHL(dev_priv)) 4555 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); 4556 else if (DISPLAY_VER(dev_priv) == 11) 4557 encoder->hpd_pin = icl_hpd_pin(dev_priv, port); 4558 else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 4559 encoder->hpd_pin = skl_hpd_pin(dev_priv, port); 4560 else 4561 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 4562 4563 if (DISPLAY_VER(dev_priv) >= 11) 4564 dig_port->saved_port_bits = 4565 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 4566 & DDI_BUF_PORT_REVERSAL; 4567 else 4568 dig_port->saved_port_bits = 4569 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 4570 & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 4571 4572 if (intel_bios_is_lane_reversal_needed(dev_priv, port)) 4573 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL; 4574 4575 dig_port->dp.output_reg = INVALID_MMIO_REG; 4576 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 4577 dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 4578 4579 if (intel_phy_is_tc(dev_priv, phy)) { 4580 bool is_legacy = 4581 !intel_bios_encoder_supports_typec_usb(devdata) && 4582 !intel_bios_encoder_supports_tbt(devdata); 4583 4584 intel_tc_port_init(dig_port, is_legacy); 4585 4586 encoder->update_prepare = intel_ddi_update_prepare; 4587 encoder->update_complete = intel_ddi_update_complete; 4588 } 4589 4590 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 4591 dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO + 4592 port - PORT_A; 4593 4594 if (init_dp) { 4595 if (!intel_ddi_init_dp_connector(dig_port)) 4596 goto err; 4597 4598 dig_port->hpd_pulse = intel_dp_hpd_pulse; 4599 4600 if (dig_port->dp.mso_link_count) 4601 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv); 4602 } 4603 4604 /* In theory we don't need the encoder->type check, but leave it just in 4605 * case we have some really bad VBTs... */ 4606 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 4607 if (!intel_ddi_init_hdmi_connector(dig_port)) 4608 goto err; 4609 } 4610 4611 if (DISPLAY_VER(dev_priv) >= 11) { 4612 if (intel_phy_is_tc(dev_priv, phy)) 4613 dig_port->connected = intel_tc_port_connected; 4614 else 4615 dig_port->connected = lpt_digital_port_connected; 4616 } else if (DISPLAY_VER(dev_priv) >= 8) { 4617 if (port == PORT_A || IS_GEMINILAKE(dev_priv) || 4618 IS_BROXTON(dev_priv)) 4619 dig_port->connected = bdw_digital_port_connected; 4620 else 4621 dig_port->connected = lpt_digital_port_connected; 4622 } else { 4623 if (port == PORT_A) 4624 dig_port->connected = hsw_digital_port_connected; 4625 else 4626 dig_port->connected = lpt_digital_port_connected; 4627 } 4628 4629 intel_infoframe_init(dig_port); 4630 4631 return; 4632 4633 err: 4634 drm_encoder_cleanup(&encoder->base); 4635 kfree(dig_port); 4636 } 4637