1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <linux/string_helpers.h> 29 30 #include <drm/display/drm_scdc_helper.h> 31 #include <drm/drm_privacy_screen_consumer.h> 32 33 #include "i915_drv.h" 34 #include "i915_reg.h" 35 #include "intel_audio.h" 36 #include "intel_audio_regs.h" 37 #include "intel_backlight.h" 38 #include "intel_combo_phy.h" 39 #include "intel_combo_phy_regs.h" 40 #include "intel_connector.h" 41 #include "intel_crtc.h" 42 #include "intel_ddi.h" 43 #include "intel_ddi_buf_trans.h" 44 #include "intel_de.h" 45 #include "intel_display_power.h" 46 #include "intel_display_types.h" 47 #include "intel_dkl_phy.h" 48 #include "intel_dkl_phy_regs.h" 49 #include "intel_dp.h" 50 #include "intel_dp_link_training.h" 51 #include "intel_dp_mst.h" 52 #include "intel_dpio_phy.h" 53 #include "intel_dsi.h" 54 #include "intel_fdi.h" 55 #include "intel_fifo_underrun.h" 56 #include "intel_gmbus.h" 57 #include "intel_hdcp.h" 58 #include "intel_hdmi.h" 59 #include "intel_hotplug.h" 60 #include "intel_hti.h" 61 #include "intel_lspcon.h" 62 #include "intel_mg_phy_regs.h" 63 #include "intel_pps.h" 64 #include "intel_psr.h" 65 #include "intel_quirks.h" 66 #include "intel_snps_phy.h" 67 #include "intel_sprite.h" 68 #include "intel_tc.h" 69 #include "intel_vdsc.h" 70 #include "intel_vrr.h" 71 #include "skl_scaler.h" 72 #include "skl_universal_plane.h" 73 74 static const u8 index_to_dp_signal_levels[] = { 75 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 76 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 77 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 78 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 79 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 80 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 81 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 82 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 83 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 84 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 85 }; 86 87 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 88 const struct intel_ddi_buf_trans *trans) 89 { 90 int level; 91 92 level = intel_bios_hdmi_level_shift(encoder); 93 if (level < 0) 94 level = trans->hdmi_default_entry; 95 96 return level; 97 } 98 99 static bool has_buf_trans_select(struct drm_i915_private *i915) 100 { 101 return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915); 102 } 103 104 static bool has_iboost(struct drm_i915_private *i915) 105 { 106 return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915); 107 } 108 109 /* 110 * Starting with Haswell, DDI port buffers must be programmed with correct 111 * values in advance. This function programs the correct values for 112 * DP/eDP/FDI use cases. 113 */ 114 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 115 const struct intel_crtc_state *crtc_state) 116 { 117 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 118 u32 iboost_bit = 0; 119 int i, n_entries; 120 enum port port = encoder->port; 121 const struct intel_ddi_buf_trans *trans; 122 123 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 124 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 125 return; 126 127 /* If we're boosting the current, set bit 31 of trans1 */ 128 if (has_iboost(dev_priv) && 129 intel_bios_encoder_dp_boost_level(encoder->devdata)) 130 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 131 132 for (i = 0; i < n_entries; i++) { 133 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 134 trans->entries[i].hsw.trans1 | iboost_bit); 135 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 136 trans->entries[i].hsw.trans2); 137 } 138 } 139 140 /* 141 * Starting with Haswell, DDI port buffers must be programmed with correct 142 * values in advance. This function programs the correct values for 143 * HDMI/DVI use cases. 144 */ 145 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 146 const struct intel_crtc_state *crtc_state) 147 { 148 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 149 int level = intel_ddi_level(encoder, crtc_state, 0); 150 u32 iboost_bit = 0; 151 int n_entries; 152 enum port port = encoder->port; 153 const struct intel_ddi_buf_trans *trans; 154 155 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 156 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 157 return; 158 159 /* If we're boosting the current, set bit 31 of trans1 */ 160 if (has_iboost(dev_priv) && 161 intel_bios_encoder_hdmi_boost_level(encoder->devdata)) 162 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 163 164 /* Entry 9 is for HDMI: */ 165 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 166 trans->entries[level].hsw.trans1 | iboost_bit); 167 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 168 trans->entries[level].hsw.trans2); 169 } 170 171 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 172 enum port port) 173 { 174 if (IS_BROXTON(dev_priv)) { 175 udelay(16); 176 return; 177 } 178 179 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 180 DDI_BUF_IS_IDLE), 8)) 181 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", 182 port_name(port)); 183 } 184 185 static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, 186 enum port port) 187 { 188 enum phy phy = intel_port_to_phy(dev_priv, port); 189 int timeout_us; 190 int ret; 191 192 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ 193 if (DISPLAY_VER(dev_priv) < 10) { 194 usleep_range(518, 1000); 195 return; 196 } 197 198 if (IS_DG2(dev_priv)) { 199 timeout_us = 1200; 200 } else if (DISPLAY_VER(dev_priv) >= 12) { 201 if (intel_phy_is_tc(dev_priv, phy)) 202 timeout_us = 3000; 203 else 204 timeout_us = 1000; 205 } else { 206 timeout_us = 500; 207 } 208 209 ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 210 DDI_BUF_IS_IDLE), timeout_us, 10, 10); 211 212 if (ret) 213 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", 214 port_name(port)); 215 } 216 217 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 218 { 219 switch (pll->info->id) { 220 case DPLL_ID_WRPLL1: 221 return PORT_CLK_SEL_WRPLL1; 222 case DPLL_ID_WRPLL2: 223 return PORT_CLK_SEL_WRPLL2; 224 case DPLL_ID_SPLL: 225 return PORT_CLK_SEL_SPLL; 226 case DPLL_ID_LCPLL_810: 227 return PORT_CLK_SEL_LCPLL_810; 228 case DPLL_ID_LCPLL_1350: 229 return PORT_CLK_SEL_LCPLL_1350; 230 case DPLL_ID_LCPLL_2700: 231 return PORT_CLK_SEL_LCPLL_2700; 232 default: 233 MISSING_CASE(pll->info->id); 234 return PORT_CLK_SEL_NONE; 235 } 236 } 237 238 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 239 const struct intel_crtc_state *crtc_state) 240 { 241 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 242 int clock = crtc_state->port_clock; 243 const enum intel_dpll_id id = pll->info->id; 244 245 switch (id) { 246 default: 247 /* 248 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 249 * here, so do warn if this get passed in 250 */ 251 MISSING_CASE(id); 252 return DDI_CLK_SEL_NONE; 253 case DPLL_ID_ICL_TBTPLL: 254 switch (clock) { 255 case 162000: 256 return DDI_CLK_SEL_TBT_162; 257 case 270000: 258 return DDI_CLK_SEL_TBT_270; 259 case 540000: 260 return DDI_CLK_SEL_TBT_540; 261 case 810000: 262 return DDI_CLK_SEL_TBT_810; 263 default: 264 MISSING_CASE(clock); 265 return DDI_CLK_SEL_NONE; 266 } 267 case DPLL_ID_ICL_MGPLL1: 268 case DPLL_ID_ICL_MGPLL2: 269 case DPLL_ID_ICL_MGPLL3: 270 case DPLL_ID_ICL_MGPLL4: 271 case DPLL_ID_TGL_MGPLL5: 272 case DPLL_ID_TGL_MGPLL6: 273 return DDI_CLK_SEL_MG; 274 } 275 } 276 277 static u32 ddi_buf_phy_link_rate(int port_clock) 278 { 279 switch (port_clock) { 280 case 162000: 281 return DDI_BUF_PHY_LINK_RATE(0); 282 case 216000: 283 return DDI_BUF_PHY_LINK_RATE(4); 284 case 243000: 285 return DDI_BUF_PHY_LINK_RATE(5); 286 case 270000: 287 return DDI_BUF_PHY_LINK_RATE(1); 288 case 324000: 289 return DDI_BUF_PHY_LINK_RATE(6); 290 case 432000: 291 return DDI_BUF_PHY_LINK_RATE(7); 292 case 540000: 293 return DDI_BUF_PHY_LINK_RATE(2); 294 case 810000: 295 return DDI_BUF_PHY_LINK_RATE(3); 296 default: 297 MISSING_CASE(port_clock); 298 return DDI_BUF_PHY_LINK_RATE(0); 299 } 300 } 301 302 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 303 const struct intel_crtc_state *crtc_state) 304 { 305 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 306 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 307 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 308 enum phy phy = intel_port_to_phy(i915, encoder->port); 309 310 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 311 intel_dp->DP = dig_port->saved_port_bits | 312 DDI_PORT_WIDTH(crtc_state->lane_count) | 313 DDI_BUF_TRANS_SELECT(0); 314 315 if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) { 316 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 317 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 318 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 319 } 320 } 321 322 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 323 enum port port) 324 { 325 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 326 327 switch (val) { 328 case DDI_CLK_SEL_NONE: 329 return 0; 330 case DDI_CLK_SEL_TBT_162: 331 return 162000; 332 case DDI_CLK_SEL_TBT_270: 333 return 270000; 334 case DDI_CLK_SEL_TBT_540: 335 return 540000; 336 case DDI_CLK_SEL_TBT_810: 337 return 810000; 338 default: 339 MISSING_CASE(val); 340 return 0; 341 } 342 } 343 344 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 345 { 346 /* CRT dotclock is determined via other means */ 347 if (pipe_config->has_pch_encoder) 348 return; 349 350 pipe_config->hw.adjusted_mode.crtc_clock = 351 intel_crtc_dotclock(pipe_config); 352 } 353 354 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 355 const struct drm_connector_state *conn_state) 356 { 357 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 358 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 359 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 360 u32 temp; 361 362 if (!intel_crtc_has_dp_encoder(crtc_state)) 363 return; 364 365 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 366 367 temp = DP_MSA_MISC_SYNC_CLOCK; 368 369 switch (crtc_state->pipe_bpp) { 370 case 18: 371 temp |= DP_MSA_MISC_6_BPC; 372 break; 373 case 24: 374 temp |= DP_MSA_MISC_8_BPC; 375 break; 376 case 30: 377 temp |= DP_MSA_MISC_10_BPC; 378 break; 379 case 36: 380 temp |= DP_MSA_MISC_12_BPC; 381 break; 382 default: 383 MISSING_CASE(crtc_state->pipe_bpp); 384 break; 385 } 386 387 /* nonsense combination */ 388 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 389 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 390 391 if (crtc_state->limited_color_range) 392 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 393 394 /* 395 * As per DP 1.2 spec section 2.3.4.3 while sending 396 * YCBCR 444 signals we should program MSA MISC1/0 fields with 397 * colorspace information. 398 */ 399 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 400 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 401 402 /* 403 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 404 * of Color Encoding Format and Content Color Gamut] while sending 405 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 406 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 407 */ 408 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 409 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 410 411 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp); 412 } 413 414 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 415 { 416 if (master_transcoder == TRANSCODER_EDP) 417 return 0; 418 else 419 return master_transcoder + 1; 420 } 421 422 static void 423 intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder, 424 const struct intel_crtc_state *crtc_state) 425 { 426 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 427 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 428 u32 val = 0; 429 430 if (intel_dp_is_uhbr(crtc_state)) 431 val = TRANS_DP2_128B132B_CHANNEL_CODING; 432 433 intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val); 434 } 435 436 /* 437 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 438 * 439 * Only intended to be used by intel_ddi_enable_transcoder_func() and 440 * intel_ddi_config_transcoder_func(). 441 */ 442 static u32 443 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 444 const struct intel_crtc_state *crtc_state) 445 { 446 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 447 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 448 enum pipe pipe = crtc->pipe; 449 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 450 enum port port = encoder->port; 451 u32 temp; 452 453 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 454 temp = TRANS_DDI_FUNC_ENABLE; 455 if (DISPLAY_VER(dev_priv) >= 12) 456 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 457 else 458 temp |= TRANS_DDI_SELECT_PORT(port); 459 460 switch (crtc_state->pipe_bpp) { 461 default: 462 MISSING_CASE(crtc_state->pipe_bpp); 463 fallthrough; 464 case 18: 465 temp |= TRANS_DDI_BPC_6; 466 break; 467 case 24: 468 temp |= TRANS_DDI_BPC_8; 469 break; 470 case 30: 471 temp |= TRANS_DDI_BPC_10; 472 break; 473 case 36: 474 temp |= TRANS_DDI_BPC_12; 475 break; 476 } 477 478 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 479 temp |= TRANS_DDI_PVSYNC; 480 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 481 temp |= TRANS_DDI_PHSYNC; 482 483 if (cpu_transcoder == TRANSCODER_EDP) { 484 switch (pipe) { 485 default: 486 MISSING_CASE(pipe); 487 fallthrough; 488 case PIPE_A: 489 /* On Haswell, can only use the always-on power well for 490 * eDP when not using the panel fitter, and when not 491 * using motion blur mitigation (which we don't 492 * support). */ 493 if (crtc_state->pch_pfit.force_thru) 494 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 495 else 496 temp |= TRANS_DDI_EDP_INPUT_A_ON; 497 break; 498 case PIPE_B: 499 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 500 break; 501 case PIPE_C: 502 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 503 break; 504 } 505 } 506 507 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 508 if (crtc_state->has_hdmi_sink) 509 temp |= TRANS_DDI_MODE_SELECT_HDMI; 510 else 511 temp |= TRANS_DDI_MODE_SELECT_DVI; 512 513 if (crtc_state->hdmi_scrambling) 514 temp |= TRANS_DDI_HDMI_SCRAMBLING; 515 if (crtc_state->hdmi_high_tmds_clock_ratio) 516 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 517 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 518 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 519 temp |= (crtc_state->fdi_lanes - 1) << 1; 520 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 521 if (intel_dp_is_uhbr(crtc_state)) 522 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 523 else 524 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 525 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 526 527 if (DISPLAY_VER(dev_priv) >= 12) { 528 enum transcoder master; 529 530 master = crtc_state->mst_master_transcoder; 531 drm_WARN_ON(&dev_priv->drm, 532 master == INVALID_TRANSCODER); 533 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 534 } 535 } else { 536 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 537 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 538 } 539 540 if (IS_DISPLAY_VER(dev_priv, 8, 10) && 541 crtc_state->master_transcoder != INVALID_TRANSCODER) { 542 u8 master_select = 543 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 544 545 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 546 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 547 } 548 549 return temp; 550 } 551 552 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 553 const struct intel_crtc_state *crtc_state) 554 { 555 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 556 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 557 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 558 559 if (DISPLAY_VER(dev_priv) >= 11) { 560 enum transcoder master_transcoder = crtc_state->master_transcoder; 561 u32 ctl2 = 0; 562 563 if (master_transcoder != INVALID_TRANSCODER) { 564 u8 master_select = 565 bdw_trans_port_sync_master_select(master_transcoder); 566 567 ctl2 |= PORT_SYNC_MODE_ENABLE | 568 PORT_SYNC_MODE_MASTER_SELECT(master_select); 569 } 570 571 intel_de_write(dev_priv, 572 TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2); 573 } 574 575 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 576 intel_ddi_transcoder_func_reg_val_get(encoder, 577 crtc_state)); 578 } 579 580 /* 581 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 582 * bit. 583 */ 584 static void 585 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 586 const struct intel_crtc_state *crtc_state) 587 { 588 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 589 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 590 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 591 u32 ctl; 592 593 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 594 ctl &= ~TRANS_DDI_FUNC_ENABLE; 595 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 596 } 597 598 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 599 { 600 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 601 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 602 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 603 u32 ctl; 604 605 if (DISPLAY_VER(dev_priv) >= 11) 606 intel_de_write(dev_priv, 607 TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0); 608 609 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 610 611 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 612 613 ctl &= ~TRANS_DDI_FUNC_ENABLE; 614 615 if (IS_DISPLAY_VER(dev_priv, 8, 10)) 616 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 617 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 618 619 if (DISPLAY_VER(dev_priv) >= 12) { 620 if (!intel_dp_mst_is_master_trans(crtc_state)) { 621 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 622 TRANS_DDI_MODE_SELECT_MASK); 623 } 624 } else { 625 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 626 } 627 628 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 629 630 if (intel_has_quirk(dev_priv, QUIRK_INCREASE_DDI_DISABLED_TIME) && 631 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 632 drm_dbg_kms(&dev_priv->drm, 633 "Quirk Increase DDI disabled time\n"); 634 /* Quirk time at 100ms for reliable operation */ 635 msleep(100); 636 } 637 } 638 639 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 640 enum transcoder cpu_transcoder, 641 bool enable, u32 hdcp_mask) 642 { 643 struct drm_device *dev = intel_encoder->base.dev; 644 struct drm_i915_private *dev_priv = to_i915(dev); 645 intel_wakeref_t wakeref; 646 int ret = 0; 647 u32 tmp; 648 649 wakeref = intel_display_power_get_if_enabled(dev_priv, 650 intel_encoder->power_domain); 651 if (drm_WARN_ON(dev, !wakeref)) 652 return -ENXIO; 653 654 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 655 if (enable) 656 tmp |= hdcp_mask; 657 else 658 tmp &= ~hdcp_mask; 659 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp); 660 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 661 return ret; 662 } 663 664 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 665 { 666 struct drm_device *dev = intel_connector->base.dev; 667 struct drm_i915_private *dev_priv = to_i915(dev); 668 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 669 int type = intel_connector->base.connector_type; 670 enum port port = encoder->port; 671 enum transcoder cpu_transcoder; 672 intel_wakeref_t wakeref; 673 enum pipe pipe = 0; 674 u32 tmp; 675 bool ret; 676 677 wakeref = intel_display_power_get_if_enabled(dev_priv, 678 encoder->power_domain); 679 if (!wakeref) 680 return false; 681 682 if (!encoder->get_hw_state(encoder, &pipe)) { 683 ret = false; 684 goto out; 685 } 686 687 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 688 cpu_transcoder = TRANSCODER_EDP; 689 else 690 cpu_transcoder = (enum transcoder) pipe; 691 692 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 693 694 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 695 case TRANS_DDI_MODE_SELECT_HDMI: 696 case TRANS_DDI_MODE_SELECT_DVI: 697 ret = type == DRM_MODE_CONNECTOR_HDMIA; 698 break; 699 700 case TRANS_DDI_MODE_SELECT_DP_SST: 701 ret = type == DRM_MODE_CONNECTOR_eDP || 702 type == DRM_MODE_CONNECTOR_DisplayPort; 703 break; 704 705 case TRANS_DDI_MODE_SELECT_DP_MST: 706 /* if the transcoder is in MST state then 707 * connector isn't connected */ 708 ret = false; 709 break; 710 711 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 712 if (HAS_DP20(dev_priv)) 713 /* 128b/132b */ 714 ret = false; 715 else 716 /* FDI */ 717 ret = type == DRM_MODE_CONNECTOR_VGA; 718 break; 719 720 default: 721 ret = false; 722 break; 723 } 724 725 out: 726 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 727 728 return ret; 729 } 730 731 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 732 u8 *pipe_mask, bool *is_dp_mst) 733 { 734 struct drm_device *dev = encoder->base.dev; 735 struct drm_i915_private *dev_priv = to_i915(dev); 736 enum port port = encoder->port; 737 intel_wakeref_t wakeref; 738 enum pipe p; 739 u32 tmp; 740 u8 mst_pipe_mask; 741 742 *pipe_mask = 0; 743 *is_dp_mst = false; 744 745 wakeref = intel_display_power_get_if_enabled(dev_priv, 746 encoder->power_domain); 747 if (!wakeref) 748 return; 749 750 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 751 if (!(tmp & DDI_BUF_CTL_ENABLE)) 752 goto out; 753 754 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { 755 tmp = intel_de_read(dev_priv, 756 TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 757 758 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 759 default: 760 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 761 fallthrough; 762 case TRANS_DDI_EDP_INPUT_A_ON: 763 case TRANS_DDI_EDP_INPUT_A_ONOFF: 764 *pipe_mask = BIT(PIPE_A); 765 break; 766 case TRANS_DDI_EDP_INPUT_B_ONOFF: 767 *pipe_mask = BIT(PIPE_B); 768 break; 769 case TRANS_DDI_EDP_INPUT_C_ONOFF: 770 *pipe_mask = BIT(PIPE_C); 771 break; 772 } 773 774 goto out; 775 } 776 777 mst_pipe_mask = 0; 778 for_each_pipe(dev_priv, p) { 779 enum transcoder cpu_transcoder = (enum transcoder)p; 780 unsigned int port_mask, ddi_select; 781 intel_wakeref_t trans_wakeref; 782 783 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 784 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 785 if (!trans_wakeref) 786 continue; 787 788 if (DISPLAY_VER(dev_priv) >= 12) { 789 port_mask = TGL_TRANS_DDI_PORT_MASK; 790 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 791 } else { 792 port_mask = TRANS_DDI_PORT_MASK; 793 ddi_select = TRANS_DDI_SELECT_PORT(port); 794 } 795 796 tmp = intel_de_read(dev_priv, 797 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 798 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 799 trans_wakeref); 800 801 if ((tmp & port_mask) != ddi_select) 802 continue; 803 804 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST || 805 (HAS_DP20(dev_priv) && 806 (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B)) 807 mst_pipe_mask |= BIT(p); 808 809 *pipe_mask |= BIT(p); 810 } 811 812 if (!*pipe_mask) 813 drm_dbg_kms(&dev_priv->drm, 814 "No pipe for [ENCODER:%d:%s] found\n", 815 encoder->base.base.id, encoder->base.name); 816 817 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 818 drm_dbg_kms(&dev_priv->drm, 819 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 820 encoder->base.base.id, encoder->base.name, 821 *pipe_mask); 822 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 823 } 824 825 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 826 drm_dbg_kms(&dev_priv->drm, 827 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", 828 encoder->base.base.id, encoder->base.name, 829 *pipe_mask, mst_pipe_mask); 830 else 831 *is_dp_mst = mst_pipe_mask; 832 833 out: 834 if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) { 835 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 836 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 837 BXT_PHY_LANE_POWERDOWN_ACK | 838 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 839 drm_err(&dev_priv->drm, 840 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 841 encoder->base.base.id, encoder->base.name, tmp); 842 } 843 844 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 845 } 846 847 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 848 enum pipe *pipe) 849 { 850 u8 pipe_mask; 851 bool is_mst; 852 853 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 854 855 if (is_mst || !pipe_mask) 856 return false; 857 858 *pipe = ffs(pipe_mask) - 1; 859 860 return true; 861 } 862 863 static enum intel_display_power_domain 864 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port, 865 const struct intel_crtc_state *crtc_state) 866 { 867 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 868 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 869 870 /* 871 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 872 * DC states enabled at the same time, while for driver initiated AUX 873 * transfers we need the same AUX IOs to be powered but with DC states 874 * disabled. Accordingly use the AUX_IO_<port> power domain here which 875 * leaves DC states enabled. 876 * 877 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require 878 * AUX IO to be enabled, but all these require DC_OFF to be enabled as 879 * well, so we can acquire a wider AUX_<port> power domain reference 880 * instead of a specific AUX_IO_<port> reference without powering up any 881 * extra wells. 882 */ 883 if (intel_encoder_can_psr(&dig_port->base)) 884 return intel_display_power_aux_io_domain(i915, dig_port->aux_ch); 885 else if (DISPLAY_VER(i915) < 14 && 886 (intel_crtc_has_dp_encoder(crtc_state) || 887 intel_phy_is_tc(i915, phy))) 888 return intel_aux_power_domain(dig_port); 889 else 890 return POWER_DOMAIN_INVALID; 891 } 892 893 static void 894 main_link_aux_power_domain_get(struct intel_digital_port *dig_port, 895 const struct intel_crtc_state *crtc_state) 896 { 897 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 898 enum intel_display_power_domain domain = 899 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 900 901 drm_WARN_ON(&i915->drm, dig_port->aux_wakeref); 902 903 if (domain == POWER_DOMAIN_INVALID) 904 return; 905 906 dig_port->aux_wakeref = intel_display_power_get(i915, domain); 907 } 908 909 static void 910 main_link_aux_power_domain_put(struct intel_digital_port *dig_port, 911 const struct intel_crtc_state *crtc_state) 912 { 913 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 914 enum intel_display_power_domain domain = 915 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 916 intel_wakeref_t wf; 917 918 wf = fetch_and_zero(&dig_port->aux_wakeref); 919 if (!wf) 920 return; 921 922 intel_display_power_put(i915, domain, wf); 923 } 924 925 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 926 struct intel_crtc_state *crtc_state) 927 { 928 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 929 struct intel_digital_port *dig_port; 930 931 /* 932 * TODO: Add support for MST encoders. Atm, the following should never 933 * happen since fake-MST encoders don't set their get_power_domains() 934 * hook. 935 */ 936 if (drm_WARN_ON(&dev_priv->drm, 937 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 938 return; 939 940 dig_port = enc_to_dig_port(encoder); 941 942 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 943 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 944 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 945 dig_port->ddi_io_power_domain); 946 } 947 948 main_link_aux_power_domain_get(dig_port, crtc_state); 949 } 950 951 void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder, 952 const struct intel_crtc_state *crtc_state) 953 { 954 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 955 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 956 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 957 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 958 u32 val; 959 960 if (cpu_transcoder != TRANSCODER_EDP) { 961 if (DISPLAY_VER(dev_priv) >= 13) 962 val = TGL_TRANS_CLK_SEL_PORT(phy); 963 else if (DISPLAY_VER(dev_priv) >= 12) 964 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 965 else 966 val = TRANS_CLK_SEL_PORT(encoder->port); 967 968 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 969 } 970 } 971 972 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state) 973 { 974 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 975 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 976 977 if (cpu_transcoder != TRANSCODER_EDP) { 978 if (DISPLAY_VER(dev_priv) >= 12) 979 intel_de_write(dev_priv, 980 TRANS_CLK_SEL(cpu_transcoder), 981 TGL_TRANS_CLK_SEL_DISABLED); 982 else 983 intel_de_write(dev_priv, 984 TRANS_CLK_SEL(cpu_transcoder), 985 TRANS_CLK_SEL_DISABLED); 986 } 987 } 988 989 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 990 enum port port, u8 iboost) 991 { 992 u32 tmp; 993 994 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 995 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 996 if (iboost) 997 tmp |= iboost << BALANCE_LEG_SHIFT(port); 998 else 999 tmp |= BALANCE_LEG_DISABLE(port); 1000 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 1001 } 1002 1003 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 1004 const struct intel_crtc_state *crtc_state, 1005 int level) 1006 { 1007 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1008 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1009 u8 iboost; 1010 1011 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1012 iboost = intel_bios_encoder_hdmi_boost_level(encoder->devdata); 1013 else 1014 iboost = intel_bios_encoder_dp_boost_level(encoder->devdata); 1015 1016 if (iboost == 0) { 1017 const struct intel_ddi_buf_trans *trans; 1018 int n_entries; 1019 1020 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1021 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1022 return; 1023 1024 iboost = trans->entries[level].hsw.i_boost; 1025 } 1026 1027 /* Make sure that the requested I_boost is valid */ 1028 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 1029 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); 1030 return; 1031 } 1032 1033 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); 1034 1035 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 1036 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 1037 } 1038 1039 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1040 const struct intel_crtc_state *crtc_state) 1041 { 1042 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1043 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1044 int n_entries; 1045 1046 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1047 1048 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 1049 n_entries = 1; 1050 if (drm_WARN_ON(&dev_priv->drm, 1051 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1052 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1053 1054 return index_to_dp_signal_levels[n_entries - 1] & 1055 DP_TRAIN_VOLTAGE_SWING_MASK; 1056 } 1057 1058 /* 1059 * We assume that the full set of pre-emphasis values can be 1060 * used on all DDI platforms. Should that change we need to 1061 * rethink this code. 1062 */ 1063 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1064 { 1065 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1066 } 1067 1068 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1069 int lane) 1070 { 1071 if (crtc_state->port_clock > 600000) 1072 return 0; 1073 1074 if (crtc_state->lane_count == 4) 1075 return lane >= 1 ? LOADGEN_SELECT : 0; 1076 else 1077 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1078 } 1079 1080 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1081 const struct intel_crtc_state *crtc_state) 1082 { 1083 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1084 const struct intel_ddi_buf_trans *trans; 1085 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1086 int n_entries, ln; 1087 u32 val; 1088 1089 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1090 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1091 return; 1092 1093 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1094 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1095 1096 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1097 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1098 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, 1099 intel_dp->hobl_active ? val : 0); 1100 } 1101 1102 /* Set PORT_TX_DW5 */ 1103 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1104 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1105 TAP2_DISABLE | TAP3_DISABLE); 1106 val |= SCALING_MODE_SEL(0x2); 1107 val |= RTERM_SELECT(0x6); 1108 val |= TAP3_DISABLE; 1109 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1110 1111 /* Program PORT_TX_DW2 */ 1112 for (ln = 0; ln < 4; ln++) { 1113 int level = intel_ddi_level(encoder, crtc_state, ln); 1114 1115 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy), 1116 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1117 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1118 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1119 RCOMP_SCALAR(0x98)); 1120 } 1121 1122 /* Program PORT_TX_DW4 */ 1123 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1124 for (ln = 0; ln < 4; ln++) { 1125 int level = intel_ddi_level(encoder, crtc_state, ln); 1126 1127 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1128 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1129 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1130 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1131 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1132 } 1133 1134 /* Program PORT_TX_DW7 */ 1135 for (ln = 0; ln < 4; ln++) { 1136 int level = intel_ddi_level(encoder, crtc_state, ln); 1137 1138 intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy), 1139 N_SCALAR_MASK, 1140 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1141 } 1142 } 1143 1144 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1145 const struct intel_crtc_state *crtc_state) 1146 { 1147 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1148 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1149 u32 val; 1150 int ln; 1151 1152 /* 1153 * 1. If port type is eDP or DP, 1154 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1155 * else clear to 0b. 1156 */ 1157 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); 1158 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1159 val &= ~COMMON_KEEPER_EN; 1160 else 1161 val |= COMMON_KEEPER_EN; 1162 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 1163 1164 /* 2. Program loadgen select */ 1165 /* 1166 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1167 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1168 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1169 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1170 */ 1171 for (ln = 0; ln < 4; ln++) { 1172 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1173 LOADGEN_SELECT, 1174 icl_combo_phy_loadgen_select(crtc_state, ln)); 1175 } 1176 1177 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1178 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 1179 0, SUS_CLOCK_CONFIG); 1180 1181 /* 4. Clear training enable to change swing values */ 1182 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1183 val &= ~TX_TRAINING_EN; 1184 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1185 1186 /* 5. Program swing and de-emphasis */ 1187 icl_ddi_combo_vswing_program(encoder, crtc_state); 1188 1189 /* 6. Set training enable to trigger update */ 1190 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1191 val |= TX_TRAINING_EN; 1192 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1193 } 1194 1195 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1196 const struct intel_crtc_state *crtc_state) 1197 { 1198 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1199 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 1200 const struct intel_ddi_buf_trans *trans; 1201 int n_entries, ln; 1202 1203 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1204 return; 1205 1206 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1207 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1208 return; 1209 1210 for (ln = 0; ln < 2; ln++) { 1211 intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), 1212 CRI_USE_FS32, 0); 1213 intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), 1214 CRI_USE_FS32, 0); 1215 } 1216 1217 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1218 for (ln = 0; ln < 2; ln++) { 1219 int level; 1220 1221 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1222 1223 intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), 1224 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1225 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1226 1227 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1228 1229 intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), 1230 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1231 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1232 } 1233 1234 /* Program MG_TX_DRVCTRL with values from vswing table */ 1235 for (ln = 0; ln < 2; ln++) { 1236 int level; 1237 1238 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1239 1240 intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), 1241 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1242 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1243 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1244 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1245 CRI_TXDEEMPH_OVERRIDE_EN); 1246 1247 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1248 1249 intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), 1250 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1251 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1252 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1253 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1254 CRI_TXDEEMPH_OVERRIDE_EN); 1255 1256 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1257 } 1258 1259 /* 1260 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1261 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1262 * values from table for which TX1 and TX2 enabled. 1263 */ 1264 for (ln = 0; ln < 2; ln++) { 1265 intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port), 1266 CFG_LOW_RATE_LKREN_EN, 1267 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1268 } 1269 1270 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1271 for (ln = 0; ln < 2; ln++) { 1272 intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port), 1273 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1274 CFG_AMI_CK_DIV_OVERRIDE_EN, 1275 crtc_state->port_clock > 500000 ? 1276 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1277 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1278 1279 intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port), 1280 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1281 CFG_AMI_CK_DIV_OVERRIDE_EN, 1282 crtc_state->port_clock > 500000 ? 1283 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1284 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1285 } 1286 1287 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1288 for (ln = 0; ln < 2; ln++) { 1289 intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 1290 0, CRI_CALCINIT); 1291 intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 1292 0, CRI_CALCINIT); 1293 } 1294 } 1295 1296 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1297 const struct intel_crtc_state *crtc_state) 1298 { 1299 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1300 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 1301 const struct intel_ddi_buf_trans *trans; 1302 int n_entries, ln; 1303 1304 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1305 return; 1306 1307 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1308 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1309 return; 1310 1311 for (ln = 0; ln < 2; ln++) { 1312 int level; 1313 1314 intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); 1315 1316 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1317 1318 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln), 1319 DKL_TX_PRESHOOT_COEFF_MASK | 1320 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1321 DKL_TX_VSWING_CONTROL_MASK, 1322 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1323 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1324 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1325 1326 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1327 1328 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln), 1329 DKL_TX_PRESHOOT_COEFF_MASK | 1330 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1331 DKL_TX_VSWING_CONTROL_MASK, 1332 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1333 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1334 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1335 1336 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1337 DKL_TX_DP20BITMODE, 0); 1338 1339 if (IS_ALDERLAKE_P(dev_priv)) { 1340 u32 val; 1341 1342 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1343 if (ln == 0) { 1344 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1345 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); 1346 } else { 1347 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); 1348 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); 1349 } 1350 } else { 1351 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1352 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); 1353 } 1354 1355 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1356 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | 1357 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, 1358 val); 1359 } 1360 } 1361 } 1362 1363 static int translate_signal_level(struct intel_dp *intel_dp, 1364 u8 signal_levels) 1365 { 1366 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1367 int i; 1368 1369 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1370 if (index_to_dp_signal_levels[i] == signal_levels) 1371 return i; 1372 } 1373 1374 drm_WARN(&i915->drm, 1, 1375 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1376 signal_levels); 1377 1378 return 0; 1379 } 1380 1381 static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1382 const struct intel_crtc_state *crtc_state, 1383 int lane) 1384 { 1385 u8 train_set = intel_dp->train_set[lane]; 1386 1387 if (intel_dp_is_uhbr(crtc_state)) { 1388 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1389 } else { 1390 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1391 DP_TRAIN_PRE_EMPHASIS_MASK); 1392 1393 return translate_signal_level(intel_dp, signal_levels); 1394 } 1395 } 1396 1397 int intel_ddi_level(struct intel_encoder *encoder, 1398 const struct intel_crtc_state *crtc_state, 1399 int lane) 1400 { 1401 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1402 const struct intel_ddi_buf_trans *trans; 1403 int level, n_entries; 1404 1405 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1406 if (drm_WARN_ON_ONCE(&i915->drm, !trans)) 1407 return 0; 1408 1409 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1410 level = intel_ddi_hdmi_level(encoder, trans); 1411 else 1412 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1413 lane); 1414 1415 if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries)) 1416 level = n_entries - 1; 1417 1418 return level; 1419 } 1420 1421 static void 1422 hsw_set_signal_levels(struct intel_encoder *encoder, 1423 const struct intel_crtc_state *crtc_state) 1424 { 1425 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1426 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1427 int level = intel_ddi_level(encoder, crtc_state, 0); 1428 enum port port = encoder->port; 1429 u32 signal_levels; 1430 1431 if (has_iboost(dev_priv)) 1432 skl_ddi_set_iboost(encoder, crtc_state, level); 1433 1434 /* HDMI ignores the rest */ 1435 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1436 return; 1437 1438 signal_levels = DDI_BUF_TRANS_SELECT(level); 1439 1440 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1441 signal_levels); 1442 1443 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1444 intel_dp->DP |= signal_levels; 1445 1446 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 1447 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 1448 } 1449 1450 static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1451 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1452 { 1453 mutex_lock(&i915->display.dpll.lock); 1454 1455 intel_de_rmw(i915, reg, clk_sel_mask, clk_sel); 1456 1457 /* 1458 * "This step and the step before must be 1459 * done with separate register writes." 1460 */ 1461 intel_de_rmw(i915, reg, clk_off, 0); 1462 1463 mutex_unlock(&i915->display.dpll.lock); 1464 } 1465 1466 static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1467 u32 clk_off) 1468 { 1469 mutex_lock(&i915->display.dpll.lock); 1470 1471 intel_de_rmw(i915, reg, 0, clk_off); 1472 1473 mutex_unlock(&i915->display.dpll.lock); 1474 } 1475 1476 static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg, 1477 u32 clk_off) 1478 { 1479 return !(intel_de_read(i915, reg) & clk_off); 1480 } 1481 1482 static struct intel_shared_dpll * 1483 _icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg, 1484 u32 clk_sel_mask, u32 clk_sel_shift) 1485 { 1486 enum intel_dpll_id id; 1487 1488 id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift; 1489 1490 return intel_get_shared_dpll_by_id(i915, id); 1491 } 1492 1493 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1494 const struct intel_crtc_state *crtc_state) 1495 { 1496 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1497 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1498 enum phy phy = intel_port_to_phy(i915, encoder->port); 1499 1500 if (drm_WARN_ON(&i915->drm, !pll)) 1501 return; 1502 1503 _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1504 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1505 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1506 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1507 } 1508 1509 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1510 { 1511 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1512 enum phy phy = intel_port_to_phy(i915, encoder->port); 1513 1514 _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1515 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1516 } 1517 1518 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1519 { 1520 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1521 enum phy phy = intel_port_to_phy(i915, encoder->port); 1522 1523 return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy), 1524 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1525 } 1526 1527 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1528 { 1529 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1530 enum phy phy = intel_port_to_phy(i915, encoder->port); 1531 1532 return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy), 1533 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1534 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1535 } 1536 1537 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1538 const struct intel_crtc_state *crtc_state) 1539 { 1540 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1541 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1542 enum phy phy = intel_port_to_phy(i915, encoder->port); 1543 1544 if (drm_WARN_ON(&i915->drm, !pll)) 1545 return; 1546 1547 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1548 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1549 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1550 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1551 } 1552 1553 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1554 { 1555 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1556 enum phy phy = intel_port_to_phy(i915, encoder->port); 1557 1558 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1559 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1560 } 1561 1562 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1563 { 1564 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1565 enum phy phy = intel_port_to_phy(i915, encoder->port); 1566 1567 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1568 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1569 } 1570 1571 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1572 { 1573 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1574 enum phy phy = intel_port_to_phy(i915, encoder->port); 1575 1576 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1577 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1578 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1579 } 1580 1581 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1582 const struct intel_crtc_state *crtc_state) 1583 { 1584 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1585 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1586 enum phy phy = intel_port_to_phy(i915, encoder->port); 1587 1588 if (drm_WARN_ON(&i915->drm, !pll)) 1589 return; 1590 1591 /* 1592 * If we fail this, something went very wrong: first 2 PLLs should be 1593 * used by first 2 phys and last 2 PLLs by last phys 1594 */ 1595 if (drm_WARN_ON(&i915->drm, 1596 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1597 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1598 return; 1599 1600 _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1601 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1602 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1603 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1604 } 1605 1606 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1607 { 1608 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1609 enum phy phy = intel_port_to_phy(i915, encoder->port); 1610 1611 _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1612 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1613 } 1614 1615 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1616 { 1617 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1618 enum phy phy = intel_port_to_phy(i915, encoder->port); 1619 1620 return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy), 1621 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1622 } 1623 1624 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1625 { 1626 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1627 enum phy phy = intel_port_to_phy(i915, encoder->port); 1628 enum intel_dpll_id id; 1629 u32 val; 1630 1631 val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy)); 1632 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1633 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1634 id = val; 1635 1636 /* 1637 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1638 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1639 * bit for phy C and D. 1640 */ 1641 if (phy >= PHY_C) 1642 id += DPLL_ID_DG1_DPLL2; 1643 1644 return intel_get_shared_dpll_by_id(i915, id); 1645 } 1646 1647 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1648 const struct intel_crtc_state *crtc_state) 1649 { 1650 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1651 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1652 enum phy phy = intel_port_to_phy(i915, encoder->port); 1653 1654 if (drm_WARN_ON(&i915->drm, !pll)) 1655 return; 1656 1657 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1658 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1659 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1660 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1661 } 1662 1663 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1664 { 1665 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1666 enum phy phy = intel_port_to_phy(i915, encoder->port); 1667 1668 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1669 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1670 } 1671 1672 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1673 { 1674 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1675 enum phy phy = intel_port_to_phy(i915, encoder->port); 1676 1677 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1678 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1679 } 1680 1681 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1682 { 1683 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1684 enum phy phy = intel_port_to_phy(i915, encoder->port); 1685 1686 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1687 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1688 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1689 } 1690 1691 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1692 const struct intel_crtc_state *crtc_state) 1693 { 1694 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1695 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1696 enum port port = encoder->port; 1697 1698 if (drm_WARN_ON(&i915->drm, !pll)) 1699 return; 1700 1701 /* 1702 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1703 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1704 */ 1705 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1706 1707 icl_ddi_combo_enable_clock(encoder, crtc_state); 1708 } 1709 1710 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1711 { 1712 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1713 enum port port = encoder->port; 1714 1715 icl_ddi_combo_disable_clock(encoder); 1716 1717 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1718 } 1719 1720 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1721 { 1722 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1723 enum port port = encoder->port; 1724 u32 tmp; 1725 1726 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1727 1728 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1729 return false; 1730 1731 return icl_ddi_combo_is_clock_enabled(encoder); 1732 } 1733 1734 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1735 const struct intel_crtc_state *crtc_state) 1736 { 1737 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1738 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1739 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1740 enum port port = encoder->port; 1741 1742 if (drm_WARN_ON(&i915->drm, !pll)) 1743 return; 1744 1745 intel_de_write(i915, DDI_CLK_SEL(port), 1746 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1747 1748 mutex_lock(&i915->display.dpll.lock); 1749 1750 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1751 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1752 1753 mutex_unlock(&i915->display.dpll.lock); 1754 } 1755 1756 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1757 { 1758 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1759 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1760 enum port port = encoder->port; 1761 1762 mutex_lock(&i915->display.dpll.lock); 1763 1764 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1765 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1766 1767 mutex_unlock(&i915->display.dpll.lock); 1768 1769 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1770 } 1771 1772 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1773 { 1774 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1775 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1776 enum port port = encoder->port; 1777 u32 tmp; 1778 1779 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1780 1781 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1782 return false; 1783 1784 tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0); 1785 1786 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1787 } 1788 1789 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1790 { 1791 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1792 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1793 enum port port = encoder->port; 1794 enum intel_dpll_id id; 1795 u32 tmp; 1796 1797 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1798 1799 switch (tmp & DDI_CLK_SEL_MASK) { 1800 case DDI_CLK_SEL_TBT_162: 1801 case DDI_CLK_SEL_TBT_270: 1802 case DDI_CLK_SEL_TBT_540: 1803 case DDI_CLK_SEL_TBT_810: 1804 id = DPLL_ID_ICL_TBTPLL; 1805 break; 1806 case DDI_CLK_SEL_MG: 1807 id = icl_tc_port_to_pll_id(tc_port); 1808 break; 1809 default: 1810 MISSING_CASE(tmp); 1811 fallthrough; 1812 case DDI_CLK_SEL_NONE: 1813 return NULL; 1814 } 1815 1816 return intel_get_shared_dpll_by_id(i915, id); 1817 } 1818 1819 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1820 { 1821 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1822 enum intel_dpll_id id; 1823 1824 switch (encoder->port) { 1825 case PORT_A: 1826 id = DPLL_ID_SKL_DPLL0; 1827 break; 1828 case PORT_B: 1829 id = DPLL_ID_SKL_DPLL1; 1830 break; 1831 case PORT_C: 1832 id = DPLL_ID_SKL_DPLL2; 1833 break; 1834 default: 1835 MISSING_CASE(encoder->port); 1836 return NULL; 1837 } 1838 1839 return intel_get_shared_dpll_by_id(i915, id); 1840 } 1841 1842 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1843 const struct intel_crtc_state *crtc_state) 1844 { 1845 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1846 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1847 enum port port = encoder->port; 1848 1849 if (drm_WARN_ON(&i915->drm, !pll)) 1850 return; 1851 1852 mutex_lock(&i915->display.dpll.lock); 1853 1854 intel_de_rmw(i915, DPLL_CTRL2, 1855 DPLL_CTRL2_DDI_CLK_OFF(port) | 1856 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1857 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1858 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1859 1860 mutex_unlock(&i915->display.dpll.lock); 1861 } 1862 1863 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1864 { 1865 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1866 enum port port = encoder->port; 1867 1868 mutex_lock(&i915->display.dpll.lock); 1869 1870 intel_de_rmw(i915, DPLL_CTRL2, 1871 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1872 1873 mutex_unlock(&i915->display.dpll.lock); 1874 } 1875 1876 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1877 { 1878 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1879 enum port port = encoder->port; 1880 1881 /* 1882 * FIXME Not sure if the override affects both 1883 * the PLL selection and the CLK_OFF bit. 1884 */ 1885 return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 1886 } 1887 1888 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 1889 { 1890 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1891 enum port port = encoder->port; 1892 enum intel_dpll_id id; 1893 u32 tmp; 1894 1895 tmp = intel_de_read(i915, DPLL_CTRL2); 1896 1897 /* 1898 * FIXME Not sure if the override affects both 1899 * the PLL selection and the CLK_OFF bit. 1900 */ 1901 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 1902 return NULL; 1903 1904 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 1905 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 1906 1907 return intel_get_shared_dpll_by_id(i915, id); 1908 } 1909 1910 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 1911 const struct intel_crtc_state *crtc_state) 1912 { 1913 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1914 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1915 enum port port = encoder->port; 1916 1917 if (drm_WARN_ON(&i915->drm, !pll)) 1918 return; 1919 1920 intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 1921 } 1922 1923 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 1924 { 1925 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1926 enum port port = encoder->port; 1927 1928 intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 1929 } 1930 1931 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 1932 { 1933 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1934 enum port port = encoder->port; 1935 1936 return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 1937 } 1938 1939 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 1940 { 1941 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1942 enum port port = encoder->port; 1943 enum intel_dpll_id id; 1944 u32 tmp; 1945 1946 tmp = intel_de_read(i915, PORT_CLK_SEL(port)); 1947 1948 switch (tmp & PORT_CLK_SEL_MASK) { 1949 case PORT_CLK_SEL_WRPLL1: 1950 id = DPLL_ID_WRPLL1; 1951 break; 1952 case PORT_CLK_SEL_WRPLL2: 1953 id = DPLL_ID_WRPLL2; 1954 break; 1955 case PORT_CLK_SEL_SPLL: 1956 id = DPLL_ID_SPLL; 1957 break; 1958 case PORT_CLK_SEL_LCPLL_810: 1959 id = DPLL_ID_LCPLL_810; 1960 break; 1961 case PORT_CLK_SEL_LCPLL_1350: 1962 id = DPLL_ID_LCPLL_1350; 1963 break; 1964 case PORT_CLK_SEL_LCPLL_2700: 1965 id = DPLL_ID_LCPLL_2700; 1966 break; 1967 default: 1968 MISSING_CASE(tmp); 1969 fallthrough; 1970 case PORT_CLK_SEL_NONE: 1971 return NULL; 1972 } 1973 1974 return intel_get_shared_dpll_by_id(i915, id); 1975 } 1976 1977 void intel_ddi_enable_clock(struct intel_encoder *encoder, 1978 const struct intel_crtc_state *crtc_state) 1979 { 1980 if (encoder->enable_clock) 1981 encoder->enable_clock(encoder, crtc_state); 1982 } 1983 1984 void intel_ddi_disable_clock(struct intel_encoder *encoder) 1985 { 1986 if (encoder->disable_clock) 1987 encoder->disable_clock(encoder); 1988 } 1989 1990 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 1991 { 1992 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1993 u32 port_mask; 1994 bool ddi_clk_needed; 1995 1996 /* 1997 * In case of DP MST, we sanitize the primary encoder only, not the 1998 * virtual ones. 1999 */ 2000 if (encoder->type == INTEL_OUTPUT_DP_MST) 2001 return; 2002 2003 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2004 u8 pipe_mask; 2005 bool is_mst; 2006 2007 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2008 /* 2009 * In the unlikely case that BIOS enables DP in MST mode, just 2010 * warn since our MST HW readout is incomplete. 2011 */ 2012 if (drm_WARN_ON(&i915->drm, is_mst)) 2013 return; 2014 } 2015 2016 port_mask = BIT(encoder->port); 2017 ddi_clk_needed = encoder->base.crtc; 2018 2019 if (encoder->type == INTEL_OUTPUT_DSI) { 2020 struct intel_encoder *other_encoder; 2021 2022 port_mask = intel_dsi_encoder_ports(encoder); 2023 /* 2024 * Sanity check that we haven't incorrectly registered another 2025 * encoder using any of the ports of this DSI encoder. 2026 */ 2027 for_each_intel_encoder(&i915->drm, other_encoder) { 2028 if (other_encoder == encoder) 2029 continue; 2030 2031 if (drm_WARN_ON(&i915->drm, 2032 port_mask & BIT(other_encoder->port))) 2033 return; 2034 } 2035 /* 2036 * For DSI we keep the ddi clocks gated 2037 * except during enable/disable sequence. 2038 */ 2039 ddi_clk_needed = false; 2040 } 2041 2042 if (ddi_clk_needed || !encoder->is_clock_enabled || 2043 !encoder->is_clock_enabled(encoder)) 2044 return; 2045 2046 drm_notice(&i915->drm, 2047 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2048 encoder->base.base.id, encoder->base.name); 2049 2050 encoder->disable_clock(encoder); 2051 } 2052 2053 static void 2054 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2055 const struct intel_crtc_state *crtc_state) 2056 { 2057 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2058 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port); 2059 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); 2060 u32 ln0, ln1, pin_assignment; 2061 u8 width; 2062 2063 if (!intel_phy_is_tc(dev_priv, phy) || 2064 intel_tc_port_in_tbt_alt_mode(dig_port)) 2065 return; 2066 2067 if (DISPLAY_VER(dev_priv) >= 12) { 2068 ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)); 2069 ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)); 2070 } else { 2071 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 2072 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 2073 } 2074 2075 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2076 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2077 2078 /* DPPATC */ 2079 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 2080 width = crtc_state->lane_count; 2081 2082 switch (pin_assignment) { 2083 case 0x0: 2084 drm_WARN_ON(&dev_priv->drm, 2085 !intel_tc_port_in_legacy_mode(dig_port)); 2086 if (width == 1) { 2087 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2088 } else { 2089 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2090 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2091 } 2092 break; 2093 case 0x1: 2094 if (width == 4) { 2095 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2096 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2097 } 2098 break; 2099 case 0x2: 2100 if (width == 2) { 2101 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2102 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2103 } 2104 break; 2105 case 0x3: 2106 case 0x5: 2107 if (width == 1) { 2108 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2109 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2110 } else { 2111 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2112 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2113 } 2114 break; 2115 case 0x4: 2116 case 0x6: 2117 if (width == 1) { 2118 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2119 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2120 } else { 2121 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2122 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2123 } 2124 break; 2125 default: 2126 MISSING_CASE(pin_assignment); 2127 } 2128 2129 if (DISPLAY_VER(dev_priv) >= 12) { 2130 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0); 2131 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1); 2132 } else { 2133 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 2134 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 2135 } 2136 } 2137 2138 static enum transcoder 2139 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2140 { 2141 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2142 return crtc_state->mst_master_transcoder; 2143 else 2144 return crtc_state->cpu_transcoder; 2145 } 2146 2147 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2148 const struct intel_crtc_state *crtc_state) 2149 { 2150 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2151 2152 if (DISPLAY_VER(dev_priv) >= 12) 2153 return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state)); 2154 else 2155 return DP_TP_CTL(encoder->port); 2156 } 2157 2158 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2159 const struct intel_crtc_state *crtc_state) 2160 { 2161 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2162 2163 if (DISPLAY_VER(dev_priv) >= 12) 2164 return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state)); 2165 else 2166 return DP_TP_STATUS(encoder->port); 2167 } 2168 2169 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2170 const struct intel_crtc_state *crtc_state, 2171 bool enable) 2172 { 2173 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2174 2175 if (!crtc_state->vrr.enable) 2176 return; 2177 2178 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2179 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2180 drm_dbg_kms(&i915->drm, 2181 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2182 str_enable_disable(enable)); 2183 } 2184 2185 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2186 const struct intel_crtc_state *crtc_state) 2187 { 2188 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2189 2190 if (!crtc_state->fec_enable) 2191 return; 2192 2193 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0) 2194 drm_dbg_kms(&i915->drm, 2195 "Failed to set FEC_READY in the sink\n"); 2196 } 2197 2198 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2199 const struct intel_crtc_state *crtc_state) 2200 { 2201 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2202 struct intel_dp *intel_dp; 2203 u32 val; 2204 2205 if (!crtc_state->fec_enable) 2206 return; 2207 2208 intel_dp = enc_to_intel_dp(encoder); 2209 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2210 val |= DP_TP_CTL_FEC_ENABLE; 2211 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 2212 } 2213 2214 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder, 2215 const struct intel_crtc_state *crtc_state) 2216 { 2217 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2218 struct intel_dp *intel_dp; 2219 u32 val; 2220 2221 if (!crtc_state->fec_enable) 2222 return; 2223 2224 intel_dp = enc_to_intel_dp(encoder); 2225 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2226 val &= ~DP_TP_CTL_FEC_ENABLE; 2227 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 2228 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2229 } 2230 2231 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2232 const struct intel_crtc_state *crtc_state) 2233 { 2234 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2235 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2236 enum phy phy = intel_port_to_phy(i915, encoder->port); 2237 2238 if (intel_phy_is_combo(i915, phy)) { 2239 bool lane_reversal = 2240 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 2241 2242 intel_combo_phy_power_up_lanes(i915, phy, false, 2243 crtc_state->lane_count, 2244 lane_reversal); 2245 } 2246 } 2247 2248 /* Splitter enable for eDP MSO is limited to certain pipes. */ 2249 static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915) 2250 { 2251 if (IS_ALDERLAKE_P(i915)) 2252 return BIT(PIPE_A) | BIT(PIPE_B); 2253 else 2254 return BIT(PIPE_A); 2255 } 2256 2257 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2258 struct intel_crtc_state *pipe_config) 2259 { 2260 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2261 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2262 enum pipe pipe = crtc->pipe; 2263 u32 dss1; 2264 2265 if (!HAS_MSO(i915)) 2266 return; 2267 2268 dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); 2269 2270 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2271 if (!pipe_config->splitter.enable) 2272 return; 2273 2274 if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) { 2275 pipe_config->splitter.enable = false; 2276 return; 2277 } 2278 2279 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2280 default: 2281 drm_WARN(&i915->drm, true, 2282 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2283 fallthrough; 2284 case SPLITTER_CONFIGURATION_2_SEGMENT: 2285 pipe_config->splitter.link_count = 2; 2286 break; 2287 case SPLITTER_CONFIGURATION_4_SEGMENT: 2288 pipe_config->splitter.link_count = 4; 2289 break; 2290 } 2291 2292 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2293 } 2294 2295 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2296 { 2297 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2298 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2299 enum pipe pipe = crtc->pipe; 2300 u32 dss1 = 0; 2301 2302 if (!HAS_MSO(i915)) 2303 return; 2304 2305 if (crtc_state->splitter.enable) { 2306 dss1 |= SPLITTER_ENABLE; 2307 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2308 if (crtc_state->splitter.link_count == 2) 2309 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2310 else 2311 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2312 } 2313 2314 intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), 2315 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2316 OVERLAP_PIXELS_MASK, dss1); 2317 } 2318 2319 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2320 struct intel_encoder *encoder, 2321 const struct intel_crtc_state *crtc_state, 2322 const struct drm_connector_state *conn_state) 2323 { 2324 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2325 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2326 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2327 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2328 2329 intel_dp_set_link_params(intel_dp, 2330 crtc_state->port_clock, 2331 crtc_state->lane_count); 2332 2333 /* 2334 * We only configure what the register value will be here. Actual 2335 * enabling happens during link training farther down. 2336 */ 2337 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2338 2339 /* 2340 * 1. Enable Power Wells 2341 * 2342 * This was handled at the beginning of intel_atomic_commit_tail(), 2343 * before we called down into this function. 2344 */ 2345 2346 /* 2. Enable Panel Power if PPS is required */ 2347 intel_pps_on(intel_dp); 2348 2349 /* 2350 * 3. For non-TBT Type-C ports, set FIA lane count 2351 * (DFLEXDPSP.DPX4TXLATC) 2352 * 2353 * This was done before tgl_ddi_pre_enable_dp by 2354 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2355 */ 2356 2357 /* 2358 * 4. Enable the port PLL. 2359 * 2360 * The PLL enabling itself was already done before this function by 2361 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 2362 * configure the PLL to port mapping here. 2363 */ 2364 intel_ddi_enable_clock(encoder, crtc_state); 2365 2366 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2367 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2368 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2369 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2370 dig_port->ddi_io_power_domain); 2371 } 2372 2373 /* 6. Program DP_MODE */ 2374 icl_program_mg_dp_mode(dig_port, crtc_state); 2375 2376 /* 2377 * 7. The rest of the below are substeps under the bspec's "Enable and 2378 * Train Display Port" step. Note that steps that are specific to 2379 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2380 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2381 * us when active_mst_links==0, so any steps designated for "single 2382 * stream or multi-stream master transcoder" can just be performed 2383 * unconditionally here. 2384 */ 2385 2386 /* 2387 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2388 * Transcoder. 2389 */ 2390 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2391 2392 if (HAS_DP20(dev_priv)) 2393 intel_ddi_config_transcoder_dp2(encoder, crtc_state); 2394 2395 /* 2396 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2397 * Transport Select 2398 */ 2399 intel_ddi_config_transcoder_func(encoder, crtc_state); 2400 2401 /* 2402 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2403 * selected 2404 * 2405 * This will be handled by the intel_dp_start_link_train() farther 2406 * down this function. 2407 */ 2408 2409 /* 7.e Configure voltage swing and related IO settings */ 2410 encoder->set_signal_levels(encoder, crtc_state); 2411 2412 /* 2413 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2414 * the used lanes of the DDI. 2415 */ 2416 intel_ddi_power_up_lanes(encoder, crtc_state); 2417 2418 /* 2419 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2420 */ 2421 intel_ddi_mso_configure(crtc_state); 2422 2423 if (!is_mst) 2424 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2425 2426 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2427 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); 2428 /* 2429 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2430 * in the FEC_CONFIGURATION register to 1 before initiating link 2431 * training 2432 */ 2433 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 2434 2435 intel_dp_check_frl_training(intel_dp); 2436 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2437 2438 /* 2439 * 7.i Follow DisplayPort specification training sequence (see notes for 2440 * failure handling) 2441 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2442 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2443 * (timeout after 800 us) 2444 */ 2445 intel_dp_start_link_train(intel_dp, crtc_state); 2446 2447 /* 7.k Set DP_TP_CTL link training to Normal */ 2448 if (!is_trans_port_sync_mode(crtc_state)) 2449 intel_dp_stop_link_train(intel_dp, crtc_state); 2450 2451 /* 7.l Configure and enable FEC if needed */ 2452 intel_ddi_enable_fec(encoder, crtc_state); 2453 2454 intel_dsc_dp_pps_write(encoder, crtc_state); 2455 } 2456 2457 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2458 struct intel_encoder *encoder, 2459 const struct intel_crtc_state *crtc_state, 2460 const struct drm_connector_state *conn_state) 2461 { 2462 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2463 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2464 enum port port = encoder->port; 2465 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2466 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2467 2468 if (DISPLAY_VER(dev_priv) < 11) 2469 drm_WARN_ON(&dev_priv->drm, 2470 is_mst && (port == PORT_A || port == PORT_E)); 2471 else 2472 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 2473 2474 intel_dp_set_link_params(intel_dp, 2475 crtc_state->port_clock, 2476 crtc_state->lane_count); 2477 2478 /* 2479 * We only configure what the register value will be here. Actual 2480 * enabling happens during link training farther down. 2481 */ 2482 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2483 2484 intel_pps_on(intel_dp); 2485 2486 intel_ddi_enable_clock(encoder, crtc_state); 2487 2488 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2489 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2490 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2491 dig_port->ddi_io_power_domain); 2492 } 2493 2494 icl_program_mg_dp_mode(dig_port, crtc_state); 2495 2496 if (has_buf_trans_select(dev_priv)) 2497 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2498 2499 encoder->set_signal_levels(encoder, crtc_state); 2500 2501 intel_ddi_power_up_lanes(encoder, crtc_state); 2502 2503 if (!is_mst) 2504 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2505 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2506 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, 2507 true); 2508 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 2509 intel_dp_start_link_train(intel_dp, crtc_state); 2510 if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && 2511 !is_trans_port_sync_mode(crtc_state)) 2512 intel_dp_stop_link_train(intel_dp, crtc_state); 2513 2514 intel_ddi_enable_fec(encoder, crtc_state); 2515 2516 if (!is_mst) 2517 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2518 2519 intel_dsc_dp_pps_write(encoder, crtc_state); 2520 } 2521 2522 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2523 struct intel_encoder *encoder, 2524 const struct intel_crtc_state *crtc_state, 2525 const struct drm_connector_state *conn_state) 2526 { 2527 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2528 2529 if (DISPLAY_VER(dev_priv) >= 12) 2530 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2531 else 2532 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2533 2534 /* MST will call a setting of MSA after an allocating of Virtual Channel 2535 * from MST encoder pre_enable callback. 2536 */ 2537 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2538 intel_ddi_set_dp_msa(crtc_state, conn_state); 2539 } 2540 2541 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2542 struct intel_encoder *encoder, 2543 const struct intel_crtc_state *crtc_state, 2544 const struct drm_connector_state *conn_state) 2545 { 2546 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2547 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2548 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2549 2550 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2551 intel_ddi_enable_clock(encoder, crtc_state); 2552 2553 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2554 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2555 dig_port->ddi_io_power_domain); 2556 2557 icl_program_mg_dp_mode(dig_port, crtc_state); 2558 2559 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2560 2561 dig_port->set_infoframes(encoder, 2562 crtc_state->has_infoframe, 2563 crtc_state, conn_state); 2564 } 2565 2566 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 2567 struct intel_encoder *encoder, 2568 const struct intel_crtc_state *crtc_state, 2569 const struct drm_connector_state *conn_state) 2570 { 2571 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2572 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2573 enum pipe pipe = crtc->pipe; 2574 2575 /* 2576 * When called from DP MST code: 2577 * - conn_state will be NULL 2578 * - encoder will be the main encoder (ie. mst->primary) 2579 * - the main connector associated with this port 2580 * won't be active or linked to a crtc 2581 * - crtc_state will be the state of the first stream to 2582 * be activated on this port, and it may not be the same 2583 * stream that will be deactivated last, but each stream 2584 * should have a state that is identical when it comes to 2585 * the DP link parameteres 2586 */ 2587 2588 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 2589 2590 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2591 2592 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 2593 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 2594 conn_state); 2595 } else { 2596 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2597 2598 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 2599 conn_state); 2600 2601 /* FIXME precompute everything properly */ 2602 /* FIXME how do we turn infoframes off again? */ 2603 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) 2604 dig_port->set_infoframes(encoder, 2605 crtc_state->has_infoframe, 2606 crtc_state, conn_state); 2607 } 2608 } 2609 2610 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 2611 const struct intel_crtc_state *crtc_state) 2612 { 2613 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2614 enum port port = encoder->port; 2615 bool wait = false; 2616 u32 val; 2617 2618 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2619 if (val & DDI_BUF_CTL_ENABLE) { 2620 val &= ~DDI_BUF_CTL_ENABLE; 2621 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 2622 wait = true; 2623 } 2624 2625 if (intel_crtc_has_dp_encoder(crtc_state)) { 2626 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2627 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 2628 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 2629 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 2630 } 2631 2632 /* Disable FEC in DP Sink */ 2633 intel_ddi_disable_fec_state(encoder, crtc_state); 2634 2635 if (wait) 2636 intel_wait_ddi_buf_idle(dev_priv, port); 2637 } 2638 2639 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 2640 struct intel_encoder *encoder, 2641 const struct intel_crtc_state *old_crtc_state, 2642 const struct drm_connector_state *old_conn_state) 2643 { 2644 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2645 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2646 struct intel_dp *intel_dp = &dig_port->dp; 2647 bool is_mst = intel_crtc_has_type(old_crtc_state, 2648 INTEL_OUTPUT_DP_MST); 2649 2650 if (!is_mst) 2651 intel_dp_set_infoframes(encoder, false, 2652 old_crtc_state, old_conn_state); 2653 2654 /* 2655 * Power down sink before disabling the port, otherwise we end 2656 * up getting interrupts from the sink on detecting link loss. 2657 */ 2658 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 2659 2660 if (DISPLAY_VER(dev_priv) >= 12) { 2661 if (is_mst) { 2662 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 2663 u32 val; 2664 2665 val = intel_de_read(dev_priv, 2666 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 2667 val &= ~(TGL_TRANS_DDI_PORT_MASK | 2668 TRANS_DDI_MODE_SELECT_MASK); 2669 intel_de_write(dev_priv, 2670 TRANS_DDI_FUNC_CTL(cpu_transcoder), 2671 val); 2672 } 2673 } else { 2674 if (!is_mst) 2675 intel_ddi_disable_pipe_clock(old_crtc_state); 2676 } 2677 2678 intel_disable_ddi_buf(encoder, old_crtc_state); 2679 2680 /* 2681 * From TGL spec: "If single stream or multi-stream master transcoder: 2682 * Configure Transcoder Clock select to direct no clock to the 2683 * transcoder" 2684 */ 2685 if (DISPLAY_VER(dev_priv) >= 12) 2686 intel_ddi_disable_pipe_clock(old_crtc_state); 2687 2688 intel_pps_vdd_on(intel_dp); 2689 intel_pps_off(intel_dp); 2690 2691 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 2692 intel_display_power_put(dev_priv, 2693 dig_port->ddi_io_power_domain, 2694 fetch_and_zero(&dig_port->ddi_io_wakeref)); 2695 2696 intel_ddi_disable_clock(encoder); 2697 } 2698 2699 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 2700 struct intel_encoder *encoder, 2701 const struct intel_crtc_state *old_crtc_state, 2702 const struct drm_connector_state *old_conn_state) 2703 { 2704 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2705 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2706 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2707 2708 dig_port->set_infoframes(encoder, false, 2709 old_crtc_state, old_conn_state); 2710 2711 if (DISPLAY_VER(dev_priv) < 12) 2712 intel_ddi_disable_pipe_clock(old_crtc_state); 2713 2714 intel_disable_ddi_buf(encoder, old_crtc_state); 2715 2716 if (DISPLAY_VER(dev_priv) >= 12) 2717 intel_ddi_disable_pipe_clock(old_crtc_state); 2718 2719 intel_display_power_put(dev_priv, 2720 dig_port->ddi_io_power_domain, 2721 fetch_and_zero(&dig_port->ddi_io_wakeref)); 2722 2723 intel_ddi_disable_clock(encoder); 2724 2725 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 2726 } 2727 2728 static void intel_ddi_post_disable(struct intel_atomic_state *state, 2729 struct intel_encoder *encoder, 2730 const struct intel_crtc_state *old_crtc_state, 2731 const struct drm_connector_state *old_conn_state) 2732 { 2733 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2734 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2735 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2736 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 2737 struct intel_crtc *slave_crtc; 2738 2739 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) { 2740 intel_crtc_vblank_off(old_crtc_state); 2741 2742 intel_vrr_disable(old_crtc_state); 2743 2744 intel_disable_transcoder(old_crtc_state); 2745 2746 intel_ddi_disable_transcoder_func(old_crtc_state); 2747 2748 intel_dsc_disable(old_crtc_state); 2749 2750 if (DISPLAY_VER(dev_priv) >= 9) 2751 skl_scaler_disable(old_crtc_state); 2752 else 2753 ilk_pfit_disable(old_crtc_state); 2754 } 2755 2756 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc, 2757 intel_crtc_bigjoiner_slave_pipes(old_crtc_state)) { 2758 const struct intel_crtc_state *old_slave_crtc_state = 2759 intel_atomic_get_old_crtc_state(state, slave_crtc); 2760 2761 intel_crtc_vblank_off(old_slave_crtc_state); 2762 2763 intel_dsc_disable(old_slave_crtc_state); 2764 skl_scaler_disable(old_slave_crtc_state); 2765 } 2766 2767 /* 2768 * When called from DP MST code: 2769 * - old_conn_state will be NULL 2770 * - encoder will be the main encoder (ie. mst->primary) 2771 * - the main connector associated with this port 2772 * won't be active or linked to a crtc 2773 * - old_crtc_state will be the state of the last stream to 2774 * be deactivated on this port, and it may not be the same 2775 * stream that was activated last, but each stream 2776 * should have a state that is identical when it comes to 2777 * the DP link parameteres 2778 */ 2779 2780 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 2781 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 2782 old_conn_state); 2783 else 2784 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 2785 old_conn_state); 2786 2787 main_link_aux_power_domain_put(dig_port, old_crtc_state); 2788 2789 if (is_tc_port) 2790 intel_tc_port_put_link(dig_port); 2791 } 2792 2793 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 2794 struct intel_encoder *encoder, 2795 const struct intel_crtc_state *crtc_state) 2796 { 2797 const struct drm_connector_state *conn_state; 2798 struct drm_connector *conn; 2799 int i; 2800 2801 if (!crtc_state->sync_mode_slaves_mask) 2802 return; 2803 2804 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 2805 struct intel_encoder *slave_encoder = 2806 to_intel_encoder(conn_state->best_encoder); 2807 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 2808 const struct intel_crtc_state *slave_crtc_state; 2809 2810 if (!slave_crtc) 2811 continue; 2812 2813 slave_crtc_state = 2814 intel_atomic_get_new_crtc_state(state, slave_crtc); 2815 2816 if (slave_crtc_state->master_transcoder != 2817 crtc_state->cpu_transcoder) 2818 continue; 2819 2820 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 2821 slave_crtc_state); 2822 } 2823 2824 usleep_range(200, 400); 2825 2826 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 2827 crtc_state); 2828 } 2829 2830 static void intel_enable_ddi_dp(struct intel_atomic_state *state, 2831 struct intel_encoder *encoder, 2832 const struct intel_crtc_state *crtc_state, 2833 const struct drm_connector_state *conn_state) 2834 { 2835 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2836 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2837 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2838 enum port port = encoder->port; 2839 2840 if (port == PORT_A && DISPLAY_VER(dev_priv) < 9) 2841 intel_dp_stop_link_train(intel_dp, crtc_state); 2842 2843 drm_connector_update_privacy_screen(conn_state); 2844 intel_edp_backlight_on(crtc_state, conn_state); 2845 2846 if (!dig_port->lspcon.active || dig_port->dp.has_hdmi_sink) 2847 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 2848 2849 intel_audio_codec_enable(encoder, crtc_state, conn_state); 2850 2851 trans_port_sync_stop_link_train(state, encoder, crtc_state); 2852 } 2853 2854 static i915_reg_t 2855 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 2856 enum port port) 2857 { 2858 static const enum transcoder trans[] = { 2859 [PORT_A] = TRANSCODER_EDP, 2860 [PORT_B] = TRANSCODER_A, 2861 [PORT_C] = TRANSCODER_B, 2862 [PORT_D] = TRANSCODER_C, 2863 [PORT_E] = TRANSCODER_A, 2864 }; 2865 2866 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9); 2867 2868 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) 2869 port = PORT_A; 2870 2871 return CHICKEN_TRANS(trans[port]); 2872 } 2873 2874 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, 2875 struct intel_encoder *encoder, 2876 const struct intel_crtc_state *crtc_state, 2877 const struct drm_connector_state *conn_state) 2878 { 2879 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2880 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2881 struct drm_connector *connector = conn_state->connector; 2882 enum port port = encoder->port; 2883 enum phy phy = intel_port_to_phy(dev_priv, port); 2884 u32 buf_ctl; 2885 2886 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 2887 crtc_state->hdmi_high_tmds_clock_ratio, 2888 crtc_state->hdmi_scrambling)) 2889 drm_dbg_kms(&dev_priv->drm, 2890 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 2891 connector->base.id, connector->name); 2892 2893 if (has_buf_trans_select(dev_priv)) 2894 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 2895 2896 encoder->set_signal_levels(encoder, crtc_state); 2897 2898 /* Display WA #1143: skl,kbl,cfl */ 2899 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { 2900 /* 2901 * For some reason these chicken bits have been 2902 * stuffed into a transcoder register, event though 2903 * the bits affect a specific DDI port rather than 2904 * a specific transcoder. 2905 */ 2906 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 2907 u32 val; 2908 2909 val = intel_de_read(dev_priv, reg); 2910 2911 if (port == PORT_E) 2912 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 2913 DDIE_TRAINING_OVERRIDE_VALUE; 2914 else 2915 val |= DDI_TRAINING_OVERRIDE_ENABLE | 2916 DDI_TRAINING_OVERRIDE_VALUE; 2917 2918 intel_de_write(dev_priv, reg, val); 2919 intel_de_posting_read(dev_priv, reg); 2920 2921 udelay(1); 2922 2923 if (port == PORT_E) 2924 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 2925 DDIE_TRAINING_OVERRIDE_VALUE); 2926 else 2927 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 2928 DDI_TRAINING_OVERRIDE_VALUE); 2929 2930 intel_de_write(dev_priv, reg, val); 2931 } 2932 2933 intel_ddi_power_up_lanes(encoder, crtc_state); 2934 2935 /* In HDMI/DVI mode, the port width, and swing/emphasis values 2936 * are ignored so nothing special needs to be done besides 2937 * enabling the port. 2938 * 2939 * On ADL_P the PHY link rate and lane count must be programmed but 2940 * these are both 0 for HDMI. 2941 */ 2942 buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE; 2943 if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) { 2944 drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port)); 2945 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 2946 } 2947 intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl); 2948 2949 intel_wait_ddi_buf_active(dev_priv, port); 2950 2951 intel_audio_codec_enable(encoder, crtc_state, conn_state); 2952 } 2953 2954 static void intel_enable_ddi(struct intel_atomic_state *state, 2955 struct intel_encoder *encoder, 2956 const struct intel_crtc_state *crtc_state, 2957 const struct drm_connector_state *conn_state) 2958 { 2959 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 2960 2961 if (!intel_crtc_is_bigjoiner_slave(crtc_state)) 2962 intel_ddi_enable_transcoder_func(encoder, crtc_state); 2963 2964 /* Enable/Disable DP2.0 SDP split config before transcoder */ 2965 intel_audio_sdp_split_update(encoder, crtc_state); 2966 2967 intel_enable_transcoder(crtc_state); 2968 2969 intel_vrr_enable(encoder, crtc_state); 2970 2971 intel_crtc_vblank_on(crtc_state); 2972 2973 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 2974 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state); 2975 else 2976 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state); 2977 2978 /* Enable hdcp if it's desired */ 2979 if (conn_state->content_protection == 2980 DRM_MODE_CONTENT_PROTECTION_DESIRED) 2981 intel_hdcp_enable(to_intel_connector(conn_state->connector), 2982 crtc_state, 2983 (u8)conn_state->hdcp_content_type); 2984 } 2985 2986 static void intel_disable_ddi_dp(struct intel_atomic_state *state, 2987 struct intel_encoder *encoder, 2988 const struct intel_crtc_state *old_crtc_state, 2989 const struct drm_connector_state *old_conn_state) 2990 { 2991 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2992 2993 intel_dp->link_trained = false; 2994 2995 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 2996 2997 intel_psr_disable(intel_dp, old_crtc_state); 2998 intel_edp_backlight_off(old_conn_state); 2999 /* Disable the decompression in DP Sink */ 3000 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, 3001 false); 3002 /* Disable Ignore_MSA bit in DP Sink */ 3003 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 3004 false); 3005 } 3006 3007 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state, 3008 struct intel_encoder *encoder, 3009 const struct intel_crtc_state *old_crtc_state, 3010 const struct drm_connector_state *old_conn_state) 3011 { 3012 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3013 struct drm_connector *connector = old_conn_state->connector; 3014 3015 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 3016 3017 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3018 false, false)) 3019 drm_dbg_kms(&i915->drm, 3020 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3021 connector->base.id, connector->name); 3022 } 3023 3024 static void intel_disable_ddi(struct intel_atomic_state *state, 3025 struct intel_encoder *encoder, 3026 const struct intel_crtc_state *old_crtc_state, 3027 const struct drm_connector_state *old_conn_state) 3028 { 3029 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3030 3031 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3032 intel_disable_ddi_hdmi(state, encoder, old_crtc_state, 3033 old_conn_state); 3034 else 3035 intel_disable_ddi_dp(state, encoder, old_crtc_state, 3036 old_conn_state); 3037 } 3038 3039 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3040 struct intel_encoder *encoder, 3041 const struct intel_crtc_state *crtc_state, 3042 const struct drm_connector_state *conn_state) 3043 { 3044 intel_ddi_set_dp_msa(crtc_state, conn_state); 3045 3046 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3047 3048 intel_backlight_update(state, encoder, crtc_state, conn_state); 3049 drm_connector_update_privacy_screen(conn_state); 3050 } 3051 3052 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3053 struct intel_encoder *encoder, 3054 const struct intel_crtc_state *crtc_state, 3055 const struct drm_connector_state *conn_state) 3056 { 3057 3058 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3059 !intel_encoder_is_mst(encoder)) 3060 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3061 conn_state); 3062 3063 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3064 } 3065 3066 static void 3067 intel_ddi_update_prepare(struct intel_atomic_state *state, 3068 struct intel_encoder *encoder, 3069 struct intel_crtc *crtc) 3070 { 3071 struct drm_i915_private *i915 = to_i915(state->base.dev); 3072 struct intel_crtc_state *crtc_state = 3073 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL; 3074 int required_lanes = crtc_state ? crtc_state->lane_count : 1; 3075 3076 drm_WARN_ON(state->base.dev, crtc && crtc->active); 3077 3078 intel_tc_port_get_link(enc_to_dig_port(encoder), 3079 required_lanes); 3080 if (crtc_state && crtc_state->hw.active) { 3081 struct intel_crtc *slave_crtc; 3082 3083 intel_update_active_dpll(state, crtc, encoder); 3084 3085 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 3086 intel_crtc_bigjoiner_slave_pipes(crtc_state)) 3087 intel_update_active_dpll(state, slave_crtc, encoder); 3088 } 3089 } 3090 3091 static void 3092 intel_ddi_update_complete(struct intel_atomic_state *state, 3093 struct intel_encoder *encoder, 3094 struct intel_crtc *crtc) 3095 { 3096 intel_tc_port_put_link(enc_to_dig_port(encoder)); 3097 } 3098 3099 static void 3100 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3101 struct intel_encoder *encoder, 3102 const struct intel_crtc_state *crtc_state, 3103 const struct drm_connector_state *conn_state) 3104 { 3105 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3106 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3107 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3108 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 3109 3110 if (is_tc_port) 3111 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3112 3113 main_link_aux_power_domain_get(dig_port, crtc_state); 3114 3115 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3116 /* 3117 * Program the lane count for static/dynamic connections on 3118 * Type-C ports. Skip this step for TBT. 3119 */ 3120 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3121 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3122 bxt_ddi_phy_set_lane_optim_mask(encoder, 3123 crtc_state->lane_lat_optim_mask); 3124 } 3125 3126 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) 3127 { 3128 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3129 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 3130 int ln; 3131 3132 for (ln = 0; ln < 2; ln++) 3133 intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0); 3134 } 3135 3136 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3137 const struct intel_crtc_state *crtc_state) 3138 { 3139 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3140 struct intel_encoder *encoder = &dig_port->base; 3141 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3142 enum port port = encoder->port; 3143 u32 dp_tp_ctl, ddi_buf_ctl; 3144 bool wait = false; 3145 3146 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3147 3148 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 3149 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3150 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 3151 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3152 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 3153 wait = true; 3154 } 3155 3156 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 3157 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1; 3158 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3159 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3160 3161 if (wait) 3162 intel_wait_ddi_buf_idle(dev_priv, port); 3163 } 3164 3165 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3166 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3167 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3168 } else { 3169 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3170 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 3171 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3172 } 3173 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3174 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3175 3176 if (IS_ALDERLAKE_P(dev_priv) && 3177 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) 3178 adlp_tbt_to_dp_alt_switch_wa(encoder); 3179 3180 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3181 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3182 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3183 3184 intel_wait_ddi_buf_active(dev_priv, port); 3185 } 3186 3187 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3188 const struct intel_crtc_state *crtc_state, 3189 u8 dp_train_pat) 3190 { 3191 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3192 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3193 u32 temp; 3194 3195 temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3196 3197 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3198 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3199 case DP_TRAINING_PATTERN_DISABLE: 3200 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3201 break; 3202 case DP_TRAINING_PATTERN_1: 3203 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3204 break; 3205 case DP_TRAINING_PATTERN_2: 3206 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3207 break; 3208 case DP_TRAINING_PATTERN_3: 3209 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3210 break; 3211 case DP_TRAINING_PATTERN_4: 3212 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3213 break; 3214 } 3215 3216 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp); 3217 } 3218 3219 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3220 const struct intel_crtc_state *crtc_state) 3221 { 3222 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3223 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3224 enum port port = encoder->port; 3225 u32 val; 3226 3227 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3228 val &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3229 val |= DP_TP_CTL_LINK_TRAIN_IDLE; 3230 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 3231 3232 /* 3233 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3234 * reason we need to set idle transmission mode is to work around a HW 3235 * issue where we enable the pipe while not in idle link-training mode. 3236 * In this case there is requirement to wait for a minimum number of 3237 * idle patterns to be sent. 3238 */ 3239 if (port == PORT_A && DISPLAY_VER(dev_priv) < 12) 3240 return; 3241 3242 if (intel_de_wait_for_set(dev_priv, 3243 dp_tp_status_reg(encoder, crtc_state), 3244 DP_TP_STATUS_IDLE_DONE, 1)) 3245 drm_err(&dev_priv->drm, 3246 "Timed out waiting for DP idle patterns\n"); 3247 } 3248 3249 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 3250 enum transcoder cpu_transcoder) 3251 { 3252 if (cpu_transcoder == TRANSCODER_EDP) 3253 return false; 3254 3255 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO)) 3256 return false; 3257 3258 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 3259 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3260 } 3261 3262 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, 3263 struct intel_crtc_state *crtc_state) 3264 { 3265 if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000) 3266 crtc_state->min_voltage_level = 2; 3267 else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000) 3268 crtc_state->min_voltage_level = 3; 3269 else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000) 3270 crtc_state->min_voltage_level = 1; 3271 } 3272 3273 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, 3274 enum transcoder cpu_transcoder) 3275 { 3276 u32 master_select; 3277 3278 if (DISPLAY_VER(dev_priv) >= 11) { 3279 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder)); 3280 3281 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3282 return INVALID_TRANSCODER; 3283 3284 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3285 } else { 3286 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3287 3288 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3289 return INVALID_TRANSCODER; 3290 3291 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3292 } 3293 3294 if (master_select == 0) 3295 return TRANSCODER_EDP; 3296 else 3297 return master_select - 1; 3298 } 3299 3300 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3301 { 3302 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3303 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3304 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3305 enum transcoder cpu_transcoder; 3306 3307 crtc_state->master_transcoder = 3308 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); 3309 3310 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { 3311 enum intel_display_power_domain power_domain; 3312 intel_wakeref_t trans_wakeref; 3313 3314 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3315 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 3316 power_domain); 3317 3318 if (!trans_wakeref) 3319 continue; 3320 3321 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == 3322 crtc_state->cpu_transcoder) 3323 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3324 3325 intel_display_power_put(dev_priv, power_domain, trans_wakeref); 3326 } 3327 3328 drm_WARN_ON(&dev_priv->drm, 3329 crtc_state->master_transcoder != INVALID_TRANSCODER && 3330 crtc_state->sync_mode_slaves_mask); 3331 } 3332 3333 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 3334 struct intel_crtc_state *pipe_config) 3335 { 3336 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3337 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3338 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3339 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3340 u32 temp, flags = 0; 3341 3342 temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3343 if (temp & TRANS_DDI_PHSYNC) 3344 flags |= DRM_MODE_FLAG_PHSYNC; 3345 else 3346 flags |= DRM_MODE_FLAG_NHSYNC; 3347 if (temp & TRANS_DDI_PVSYNC) 3348 flags |= DRM_MODE_FLAG_PVSYNC; 3349 else 3350 flags |= DRM_MODE_FLAG_NVSYNC; 3351 3352 pipe_config->hw.adjusted_mode.flags |= flags; 3353 3354 switch (temp & TRANS_DDI_BPC_MASK) { 3355 case TRANS_DDI_BPC_6: 3356 pipe_config->pipe_bpp = 18; 3357 break; 3358 case TRANS_DDI_BPC_8: 3359 pipe_config->pipe_bpp = 24; 3360 break; 3361 case TRANS_DDI_BPC_10: 3362 pipe_config->pipe_bpp = 30; 3363 break; 3364 case TRANS_DDI_BPC_12: 3365 pipe_config->pipe_bpp = 36; 3366 break; 3367 default: 3368 break; 3369 } 3370 3371 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 3372 case TRANS_DDI_MODE_SELECT_HDMI: 3373 pipe_config->has_hdmi_sink = true; 3374 3375 pipe_config->infoframes.enable |= 3376 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3377 3378 if (pipe_config->infoframes.enable) 3379 pipe_config->has_infoframe = true; 3380 3381 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 3382 pipe_config->hdmi_scrambling = true; 3383 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 3384 pipe_config->hdmi_high_tmds_clock_ratio = true; 3385 fallthrough; 3386 case TRANS_DDI_MODE_SELECT_DVI: 3387 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 3388 pipe_config->lane_count = 4; 3389 break; 3390 case TRANS_DDI_MODE_SELECT_DP_SST: 3391 if (encoder->type == INTEL_OUTPUT_EDP) 3392 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 3393 else 3394 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 3395 pipe_config->lane_count = 3396 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3397 3398 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 3399 &pipe_config->dp_m_n); 3400 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, 3401 &pipe_config->dp_m2_n2); 3402 3403 if (DISPLAY_VER(dev_priv) >= 11) { 3404 i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config); 3405 3406 pipe_config->fec_enable = 3407 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE; 3408 3409 drm_dbg_kms(&dev_priv->drm, 3410 "[ENCODER:%d:%s] Fec status: %u\n", 3411 encoder->base.base.id, encoder->base.name, 3412 pipe_config->fec_enable); 3413 } 3414 3415 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) 3416 pipe_config->infoframes.enable |= 3417 intel_lspcon_infoframes_enabled(encoder, pipe_config); 3418 else 3419 pipe_config->infoframes.enable |= 3420 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3421 break; 3422 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 3423 if (!HAS_DP20(dev_priv)) { 3424 /* FDI */ 3425 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 3426 break; 3427 } 3428 fallthrough; /* 128b/132b */ 3429 case TRANS_DDI_MODE_SELECT_DP_MST: 3430 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 3431 pipe_config->lane_count = 3432 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3433 3434 if (DISPLAY_VER(dev_priv) >= 12) 3435 pipe_config->mst_master_transcoder = 3436 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); 3437 3438 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 3439 &pipe_config->dp_m_n); 3440 3441 pipe_config->infoframes.enable |= 3442 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3443 break; 3444 default: 3445 break; 3446 } 3447 } 3448 3449 static void intel_ddi_get_config(struct intel_encoder *encoder, 3450 struct intel_crtc_state *pipe_config) 3451 { 3452 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3453 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3454 3455 /* XXX: DSI transcoder paranoia */ 3456 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 3457 return; 3458 3459 intel_ddi_read_func_ctl(encoder, pipe_config); 3460 3461 intel_ddi_mso_get_config(encoder, pipe_config); 3462 3463 pipe_config->has_audio = 3464 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 3465 3466 if (encoder->type == INTEL_OUTPUT_EDP) 3467 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); 3468 3469 ddi_dotclock_get(pipe_config); 3470 3471 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3472 pipe_config->lane_lat_optim_mask = 3473 bxt_ddi_phy_get_lane_lat_optim_mask(encoder); 3474 3475 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 3476 3477 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 3478 3479 intel_read_infoframe(encoder, pipe_config, 3480 HDMI_INFOFRAME_TYPE_AVI, 3481 &pipe_config->infoframes.avi); 3482 intel_read_infoframe(encoder, pipe_config, 3483 HDMI_INFOFRAME_TYPE_SPD, 3484 &pipe_config->infoframes.spd); 3485 intel_read_infoframe(encoder, pipe_config, 3486 HDMI_INFOFRAME_TYPE_VENDOR, 3487 &pipe_config->infoframes.hdmi); 3488 intel_read_infoframe(encoder, pipe_config, 3489 HDMI_INFOFRAME_TYPE_DRM, 3490 &pipe_config->infoframes.drm); 3491 3492 if (DISPLAY_VER(dev_priv) >= 8) 3493 bdw_get_trans_port_sync_config(pipe_config); 3494 3495 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 3496 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 3497 3498 intel_psr_get_config(encoder, pipe_config); 3499 3500 intel_audio_codec_get_config(encoder, pipe_config); 3501 } 3502 3503 void intel_ddi_get_clock(struct intel_encoder *encoder, 3504 struct intel_crtc_state *crtc_state, 3505 struct intel_shared_dpll *pll) 3506 { 3507 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3508 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 3509 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 3510 bool pll_active; 3511 3512 if (drm_WARN_ON(&i915->drm, !pll)) 3513 return; 3514 3515 port_dpll->pll = pll; 3516 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 3517 drm_WARN_ON(&i915->drm, !pll_active); 3518 3519 icl_set_active_port_dpll(crtc_state, port_dpll_id); 3520 3521 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 3522 &crtc_state->dpll_hw_state); 3523 } 3524 3525 static void dg2_ddi_get_config(struct intel_encoder *encoder, 3526 struct intel_crtc_state *crtc_state) 3527 { 3528 intel_mpllb_readout_hw_state(encoder, &crtc_state->mpllb_state); 3529 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->mpllb_state); 3530 3531 intel_ddi_get_config(encoder, crtc_state); 3532 } 3533 3534 static void adls_ddi_get_config(struct intel_encoder *encoder, 3535 struct intel_crtc_state *crtc_state) 3536 { 3537 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 3538 intel_ddi_get_config(encoder, crtc_state); 3539 } 3540 3541 static void rkl_ddi_get_config(struct intel_encoder *encoder, 3542 struct intel_crtc_state *crtc_state) 3543 { 3544 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 3545 intel_ddi_get_config(encoder, crtc_state); 3546 } 3547 3548 static void dg1_ddi_get_config(struct intel_encoder *encoder, 3549 struct intel_crtc_state *crtc_state) 3550 { 3551 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 3552 intel_ddi_get_config(encoder, crtc_state); 3553 } 3554 3555 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 3556 struct intel_crtc_state *crtc_state) 3557 { 3558 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 3559 intel_ddi_get_config(encoder, crtc_state); 3560 } 3561 3562 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 3563 struct intel_crtc_state *crtc_state, 3564 struct intel_shared_dpll *pll) 3565 { 3566 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3567 enum icl_port_dpll_id port_dpll_id; 3568 struct icl_port_dpll *port_dpll; 3569 bool pll_active; 3570 3571 if (drm_WARN_ON(&i915->drm, !pll)) 3572 return; 3573 3574 if (pll->info->id == DPLL_ID_ICL_TBTPLL) 3575 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 3576 else 3577 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 3578 3579 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 3580 3581 port_dpll->pll = pll; 3582 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 3583 drm_WARN_ON(&i915->drm, !pll_active); 3584 3585 icl_set_active_port_dpll(crtc_state, port_dpll_id); 3586 3587 if (crtc_state->shared_dpll->info->id == DPLL_ID_ICL_TBTPLL) 3588 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port); 3589 else 3590 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 3591 &crtc_state->dpll_hw_state); 3592 } 3593 3594 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 3595 struct intel_crtc_state *crtc_state) 3596 { 3597 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 3598 intel_ddi_get_config(encoder, crtc_state); 3599 } 3600 3601 static void bxt_ddi_get_config(struct intel_encoder *encoder, 3602 struct intel_crtc_state *crtc_state) 3603 { 3604 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 3605 intel_ddi_get_config(encoder, crtc_state); 3606 } 3607 3608 static void skl_ddi_get_config(struct intel_encoder *encoder, 3609 struct intel_crtc_state *crtc_state) 3610 { 3611 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 3612 intel_ddi_get_config(encoder, crtc_state); 3613 } 3614 3615 void hsw_ddi_get_config(struct intel_encoder *encoder, 3616 struct intel_crtc_state *crtc_state) 3617 { 3618 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 3619 intel_ddi_get_config(encoder, crtc_state); 3620 } 3621 3622 static void intel_ddi_sync_state(struct intel_encoder *encoder, 3623 const struct intel_crtc_state *crtc_state) 3624 { 3625 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3626 enum phy phy = intel_port_to_phy(i915, encoder->port); 3627 3628 if (intel_phy_is_tc(i915, phy)) 3629 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder)); 3630 3631 if (crtc_state && intel_crtc_has_dp_encoder(crtc_state)) 3632 intel_dp_sync_state(encoder, crtc_state); 3633 } 3634 3635 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 3636 struct intel_crtc_state *crtc_state) 3637 { 3638 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3639 enum phy phy = intel_port_to_phy(i915, encoder->port); 3640 bool fastset = true; 3641 3642 if (intel_phy_is_tc(i915, phy)) { 3643 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", 3644 encoder->base.base.id, encoder->base.name); 3645 crtc_state->uapi.mode_changed = true; 3646 fastset = false; 3647 } 3648 3649 if (intel_crtc_has_dp_encoder(crtc_state) && 3650 !intel_dp_initial_fastset_check(encoder, crtc_state)) 3651 fastset = false; 3652 3653 return fastset; 3654 } 3655 3656 static enum intel_output_type 3657 intel_ddi_compute_output_type(struct intel_encoder *encoder, 3658 struct intel_crtc_state *crtc_state, 3659 struct drm_connector_state *conn_state) 3660 { 3661 switch (conn_state->connector->connector_type) { 3662 case DRM_MODE_CONNECTOR_HDMIA: 3663 return INTEL_OUTPUT_HDMI; 3664 case DRM_MODE_CONNECTOR_eDP: 3665 return INTEL_OUTPUT_EDP; 3666 case DRM_MODE_CONNECTOR_DisplayPort: 3667 return INTEL_OUTPUT_DP; 3668 default: 3669 MISSING_CASE(conn_state->connector->connector_type); 3670 return INTEL_OUTPUT_UNUSED; 3671 } 3672 } 3673 3674 static int intel_ddi_compute_config(struct intel_encoder *encoder, 3675 struct intel_crtc_state *pipe_config, 3676 struct drm_connector_state *conn_state) 3677 { 3678 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3679 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3680 enum port port = encoder->port; 3681 int ret; 3682 3683 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 3684 pipe_config->cpu_transcoder = TRANSCODER_EDP; 3685 3686 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 3687 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 3688 } else { 3689 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 3690 } 3691 3692 if (ret) 3693 return ret; 3694 3695 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 3696 pipe_config->cpu_transcoder == TRANSCODER_EDP) 3697 pipe_config->pch_pfit.force_thru = 3698 pipe_config->pch_pfit.enabled || 3699 pipe_config->crc_enabled; 3700 3701 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3702 pipe_config->lane_lat_optim_mask = 3703 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 3704 3705 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 3706 3707 return 0; 3708 } 3709 3710 static bool mode_equal(const struct drm_display_mode *mode1, 3711 const struct drm_display_mode *mode2) 3712 { 3713 return drm_mode_match(mode1, mode2, 3714 DRM_MODE_MATCH_TIMINGS | 3715 DRM_MODE_MATCH_FLAGS | 3716 DRM_MODE_MATCH_3D_FLAGS) && 3717 mode1->clock == mode2->clock; /* we want an exact match */ 3718 } 3719 3720 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 3721 const struct intel_link_m_n *m_n_2) 3722 { 3723 return m_n_1->tu == m_n_2->tu && 3724 m_n_1->data_m == m_n_2->data_m && 3725 m_n_1->data_n == m_n_2->data_n && 3726 m_n_1->link_m == m_n_2->link_m && 3727 m_n_1->link_n == m_n_2->link_n; 3728 } 3729 3730 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 3731 const struct intel_crtc_state *crtc_state2) 3732 { 3733 return crtc_state1->hw.active && crtc_state2->hw.active && 3734 crtc_state1->output_types == crtc_state2->output_types && 3735 crtc_state1->output_format == crtc_state2->output_format && 3736 crtc_state1->lane_count == crtc_state2->lane_count && 3737 crtc_state1->port_clock == crtc_state2->port_clock && 3738 mode_equal(&crtc_state1->hw.adjusted_mode, 3739 &crtc_state2->hw.adjusted_mode) && 3740 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 3741 } 3742 3743 static u8 3744 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 3745 int tile_group_id) 3746 { 3747 struct drm_connector *connector; 3748 const struct drm_connector_state *conn_state; 3749 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 3750 struct intel_atomic_state *state = 3751 to_intel_atomic_state(ref_crtc_state->uapi.state); 3752 u8 transcoders = 0; 3753 int i; 3754 3755 /* 3756 * We don't enable port sync on BDW due to missing w/as and 3757 * due to not having adjusted the modeset sequence appropriately. 3758 */ 3759 if (DISPLAY_VER(dev_priv) < 9) 3760 return 0; 3761 3762 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 3763 return 0; 3764 3765 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 3766 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 3767 const struct intel_crtc_state *crtc_state; 3768 3769 if (!crtc) 3770 continue; 3771 3772 if (!connector->has_tile || 3773 connector->tile_group->id != 3774 tile_group_id) 3775 continue; 3776 crtc_state = intel_atomic_get_new_crtc_state(state, 3777 crtc); 3778 if (!crtcs_port_sync_compatible(ref_crtc_state, 3779 crtc_state)) 3780 continue; 3781 transcoders |= BIT(crtc_state->cpu_transcoder); 3782 } 3783 3784 return transcoders; 3785 } 3786 3787 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 3788 struct intel_crtc_state *crtc_state, 3789 struct drm_connector_state *conn_state) 3790 { 3791 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3792 struct drm_connector *connector = conn_state->connector; 3793 u8 port_sync_transcoders = 0; 3794 3795 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]", 3796 encoder->base.base.id, encoder->base.name, 3797 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 3798 3799 if (connector->has_tile) 3800 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 3801 connector->tile_group->id); 3802 3803 /* 3804 * EDP Transcoders cannot be ensalved 3805 * make them a master always when present 3806 */ 3807 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 3808 crtc_state->master_transcoder = TRANSCODER_EDP; 3809 else 3810 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 3811 3812 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 3813 crtc_state->master_transcoder = INVALID_TRANSCODER; 3814 crtc_state->sync_mode_slaves_mask = 3815 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 3816 } 3817 3818 return 0; 3819 } 3820 3821 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 3822 { 3823 struct drm_i915_private *i915 = to_i915(encoder->dev); 3824 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 3825 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 3826 3827 intel_dp_encoder_flush_work(encoder); 3828 if (intel_phy_is_tc(i915, phy)) 3829 intel_tc_port_flush_work(dig_port); 3830 intel_display_power_flush_work(i915); 3831 3832 drm_encoder_cleanup(encoder); 3833 kfree(dig_port->hdcp_port_data.streams); 3834 kfree(dig_port); 3835 } 3836 3837 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 3838 { 3839 struct drm_i915_private *i915 = to_i915(encoder->dev); 3840 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 3841 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 3842 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 3843 3844 intel_dp->reset_link_params = true; 3845 3846 intel_pps_encoder_reset(intel_dp); 3847 3848 if (intel_phy_is_tc(i915, phy)) 3849 intel_tc_port_init_mode(dig_port); 3850 } 3851 3852 static const struct drm_encoder_funcs intel_ddi_funcs = { 3853 .reset = intel_ddi_encoder_reset, 3854 .destroy = intel_ddi_encoder_destroy, 3855 }; 3856 3857 static struct intel_connector * 3858 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 3859 { 3860 struct intel_connector *connector; 3861 enum port port = dig_port->base.port; 3862 3863 connector = intel_connector_alloc(); 3864 if (!connector) 3865 return NULL; 3866 3867 dig_port->dp.output_reg = DDI_BUF_CTL(port); 3868 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 3869 dig_port->dp.set_link_train = intel_ddi_set_link_train; 3870 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 3871 3872 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 3873 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 3874 3875 if (!intel_dp_init_connector(dig_port, connector)) { 3876 kfree(connector); 3877 return NULL; 3878 } 3879 3880 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 3881 struct drm_device *dev = dig_port->base.base.dev; 3882 struct drm_privacy_screen *privacy_screen; 3883 3884 privacy_screen = drm_privacy_screen_get(dev->dev, NULL); 3885 if (!IS_ERR(privacy_screen)) { 3886 drm_connector_attach_privacy_screen_provider(&connector->base, 3887 privacy_screen); 3888 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 3889 drm_warn(dev, "Error getting privacy-screen\n"); 3890 } 3891 } 3892 3893 return connector; 3894 } 3895 3896 static int modeset_pipe(struct drm_crtc *crtc, 3897 struct drm_modeset_acquire_ctx *ctx) 3898 { 3899 struct drm_atomic_state *state; 3900 struct drm_crtc_state *crtc_state; 3901 int ret; 3902 3903 state = drm_atomic_state_alloc(crtc->dev); 3904 if (!state) 3905 return -ENOMEM; 3906 3907 state->acquire_ctx = ctx; 3908 3909 crtc_state = drm_atomic_get_crtc_state(state, crtc); 3910 if (IS_ERR(crtc_state)) { 3911 ret = PTR_ERR(crtc_state); 3912 goto out; 3913 } 3914 3915 crtc_state->connectors_changed = true; 3916 3917 ret = drm_atomic_commit(state); 3918 out: 3919 drm_atomic_state_put(state); 3920 3921 return ret; 3922 } 3923 3924 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 3925 struct drm_modeset_acquire_ctx *ctx) 3926 { 3927 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3928 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 3929 struct intel_connector *connector = hdmi->attached_connector; 3930 struct i2c_adapter *adapter = 3931 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 3932 struct drm_connector_state *conn_state; 3933 struct intel_crtc_state *crtc_state; 3934 struct intel_crtc *crtc; 3935 u8 config; 3936 int ret; 3937 3938 if (!connector || connector->base.status != connector_status_connected) 3939 return 0; 3940 3941 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 3942 ctx); 3943 if (ret) 3944 return ret; 3945 3946 conn_state = connector->base.state; 3947 3948 crtc = to_intel_crtc(conn_state->crtc); 3949 if (!crtc) 3950 return 0; 3951 3952 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 3953 if (ret) 3954 return ret; 3955 3956 crtc_state = to_intel_crtc_state(crtc->base.state); 3957 3958 drm_WARN_ON(&dev_priv->drm, 3959 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 3960 3961 if (!crtc_state->hw.active) 3962 return 0; 3963 3964 if (!crtc_state->hdmi_high_tmds_clock_ratio && 3965 !crtc_state->hdmi_scrambling) 3966 return 0; 3967 3968 if (conn_state->commit && 3969 !try_wait_for_completion(&conn_state->commit->hw_done)) 3970 return 0; 3971 3972 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 3973 if (ret < 0) { 3974 drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n", 3975 ret); 3976 return 0; 3977 } 3978 3979 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 3980 crtc_state->hdmi_high_tmds_clock_ratio && 3981 !!(config & SCDC_SCRAMBLING_ENABLE) == 3982 crtc_state->hdmi_scrambling) 3983 return 0; 3984 3985 /* 3986 * HDMI 2.0 says that one should not send scrambled data 3987 * prior to configuring the sink scrambling, and that 3988 * TMDS clock/data transmission should be suspended when 3989 * changing the TMDS clock rate in the sink. So let's 3990 * just do a full modeset here, even though some sinks 3991 * would be perfectly happy if were to just reconfigure 3992 * the SCDC settings on the fly. 3993 */ 3994 return modeset_pipe(&crtc->base, ctx); 3995 } 3996 3997 static enum intel_hotplug_state 3998 intel_ddi_hotplug(struct intel_encoder *encoder, 3999 struct intel_connector *connector) 4000 { 4001 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4002 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4003 struct intel_dp *intel_dp = &dig_port->dp; 4004 enum phy phy = intel_port_to_phy(i915, encoder->port); 4005 bool is_tc = intel_phy_is_tc(i915, phy); 4006 struct drm_modeset_acquire_ctx ctx; 4007 enum intel_hotplug_state state; 4008 int ret; 4009 4010 if (intel_dp->compliance.test_active && 4011 intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) { 4012 intel_dp_phy_test(encoder); 4013 /* just do the PHY test and nothing else */ 4014 return INTEL_HOTPLUG_UNCHANGED; 4015 } 4016 4017 state = intel_encoder_hotplug(encoder, connector); 4018 4019 drm_modeset_acquire_init(&ctx, 0); 4020 4021 for (;;) { 4022 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) 4023 ret = intel_hdmi_reset_link(encoder, &ctx); 4024 else 4025 ret = intel_dp_retrain_link(encoder, &ctx); 4026 4027 if (ret == -EDEADLK) { 4028 drm_modeset_backoff(&ctx); 4029 continue; 4030 } 4031 4032 break; 4033 } 4034 4035 drm_modeset_drop_locks(&ctx); 4036 drm_modeset_acquire_fini(&ctx); 4037 drm_WARN(encoder->base.dev, ret, 4038 "Acquiring modeset locks failed with %i\n", ret); 4039 4040 /* 4041 * Unpowered type-c dongles can take some time to boot and be 4042 * responsible, so here giving some time to those dongles to power up 4043 * and then retrying the probe. 4044 * 4045 * On many platforms the HDMI live state signal is known to be 4046 * unreliable, so we can't use it to detect if a sink is connected or 4047 * not. Instead we detect if it's connected based on whether we can 4048 * read the EDID or not. That in turn has a problem during disconnect, 4049 * since the HPD interrupt may be raised before the DDC lines get 4050 * disconnected (due to how the required length of DDC vs. HPD 4051 * connector pins are specified) and so we'll still be able to get a 4052 * valid EDID. To solve this schedule another detection cycle if this 4053 * time around we didn't detect any change in the sink's connection 4054 * status. 4055 * 4056 * Type-c connectors which get their HPD signal deasserted then 4057 * reasserted, without unplugging/replugging the sink from the 4058 * connector, introduce a delay until the AUX channel communication 4059 * becomes functional. Retry the detection for 5 seconds on type-c 4060 * connectors to account for this delay. 4061 */ 4062 if (state == INTEL_HOTPLUG_UNCHANGED && 4063 connector->hotplug_retries < (is_tc ? 5 : 1) && 4064 !dig_port->dp.is_mst) 4065 state = INTEL_HOTPLUG_RETRY; 4066 4067 return state; 4068 } 4069 4070 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4071 { 4072 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4073 u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin]; 4074 4075 return intel_de_read(dev_priv, SDEISR) & bit; 4076 } 4077 4078 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4079 { 4080 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4081 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4082 4083 return intel_de_read(dev_priv, DEISR) & bit; 4084 } 4085 4086 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4087 { 4088 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4089 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4090 4091 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; 4092 } 4093 4094 static struct intel_connector * 4095 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4096 { 4097 struct intel_connector *connector; 4098 enum port port = dig_port->base.port; 4099 4100 connector = intel_connector_alloc(); 4101 if (!connector) 4102 return NULL; 4103 4104 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4105 intel_hdmi_init_connector(dig_port, connector); 4106 4107 return connector; 4108 } 4109 4110 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4111 { 4112 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4113 4114 if (dig_port->base.port != PORT_A) 4115 return false; 4116 4117 if (dig_port->saved_port_bits & DDI_A_4_LANES) 4118 return false; 4119 4120 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4121 * supported configuration 4122 */ 4123 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4124 return true; 4125 4126 return false; 4127 } 4128 4129 static int 4130 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4131 { 4132 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4133 enum port port = dig_port->base.port; 4134 int max_lanes = 4; 4135 4136 if (DISPLAY_VER(dev_priv) >= 11) 4137 return max_lanes; 4138 4139 if (port == PORT_A || port == PORT_E) { 4140 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4141 max_lanes = port == PORT_A ? 4 : 0; 4142 else 4143 /* Both A and E share 2 lanes */ 4144 max_lanes = 2; 4145 } 4146 4147 /* 4148 * Some BIOS might fail to set this bit on port A if eDP 4149 * wasn't lit up at boot. Force this bit set when needed 4150 * so we use the proper lane count for our calculations. 4151 */ 4152 if (intel_ddi_a_force_4_lanes(dig_port)) { 4153 drm_dbg_kms(&dev_priv->drm, 4154 "Forcing DDI_A_4_LANES for port A\n"); 4155 dig_port->saved_port_bits |= DDI_A_4_LANES; 4156 max_lanes = 4; 4157 } 4158 4159 return max_lanes; 4160 } 4161 4162 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv, 4163 enum port port) 4164 { 4165 if (port >= PORT_D_XELPD) 4166 return HPD_PORT_D + port - PORT_D_XELPD; 4167 else if (port >= PORT_TC1) 4168 return HPD_PORT_TC1 + port - PORT_TC1; 4169 else 4170 return HPD_PORT_A + port - PORT_A; 4171 } 4172 4173 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, 4174 enum port port) 4175 { 4176 if (port >= PORT_TC1) 4177 return HPD_PORT_C + port - PORT_TC1; 4178 else 4179 return HPD_PORT_A + port - PORT_A; 4180 } 4181 4182 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, 4183 enum port port) 4184 { 4185 if (port >= PORT_TC1) 4186 return HPD_PORT_TC1 + port - PORT_TC1; 4187 else 4188 return HPD_PORT_A + port - PORT_A; 4189 } 4190 4191 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, 4192 enum port port) 4193 { 4194 if (HAS_PCH_TGP(dev_priv)) 4195 return tgl_hpd_pin(dev_priv, port); 4196 4197 if (port >= PORT_TC1) 4198 return HPD_PORT_C + port - PORT_TC1; 4199 else 4200 return HPD_PORT_A + port - PORT_A; 4201 } 4202 4203 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, 4204 enum port port) 4205 { 4206 if (port >= PORT_C) 4207 return HPD_PORT_TC1 + port - PORT_C; 4208 else 4209 return HPD_PORT_A + port - PORT_A; 4210 } 4211 4212 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, 4213 enum port port) 4214 { 4215 if (port == PORT_D) 4216 return HPD_PORT_A; 4217 4218 if (HAS_PCH_TGP(dev_priv)) 4219 return icl_hpd_pin(dev_priv, port); 4220 4221 return HPD_PORT_A + port - PORT_A; 4222 } 4223 4224 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) 4225 { 4226 if (HAS_PCH_TGP(dev_priv)) 4227 return icl_hpd_pin(dev_priv, port); 4228 4229 return HPD_PORT_A + port - PORT_A; 4230 } 4231 4232 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port) 4233 { 4234 if (DISPLAY_VER(i915) >= 12) 4235 return port >= PORT_TC1; 4236 else if (DISPLAY_VER(i915) >= 11) 4237 return port >= PORT_C; 4238 else 4239 return false; 4240 } 4241 4242 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 4243 { 4244 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4245 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4246 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4247 enum phy phy = intel_port_to_phy(i915, encoder->port); 4248 4249 intel_dp_encoder_suspend(encoder); 4250 4251 if (!intel_phy_is_tc(i915, phy)) 4252 return; 4253 4254 intel_tc_port_flush_work(dig_port); 4255 } 4256 4257 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 4258 { 4259 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4260 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4261 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4262 enum phy phy = intel_port_to_phy(i915, encoder->port); 4263 4264 intel_dp_encoder_shutdown(encoder); 4265 intel_hdmi_encoder_shutdown(encoder); 4266 4267 if (!intel_phy_is_tc(i915, phy)) 4268 return; 4269 4270 intel_tc_port_flush_work(dig_port); 4271 } 4272 4273 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 4274 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 4275 4276 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 4277 { 4278 struct intel_digital_port *dig_port; 4279 struct intel_encoder *encoder; 4280 const struct intel_bios_encoder_data *devdata; 4281 bool init_hdmi, init_dp; 4282 enum phy phy = intel_port_to_phy(dev_priv, port); 4283 4284 /* 4285 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 4286 * have taken over some of the PHYs and made them unavailable to the 4287 * driver. In that case we should skip initializing the corresponding 4288 * outputs. 4289 */ 4290 if (intel_hti_uses_phy(dev_priv, phy)) { 4291 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", 4292 port_name(port), phy_name(phy)); 4293 return; 4294 } 4295 4296 devdata = intel_bios_encoder_data_lookup(dev_priv, port); 4297 if (!devdata) { 4298 drm_dbg_kms(&dev_priv->drm, 4299 "VBT says port %c is not present\n", 4300 port_name(port)); 4301 return; 4302 } 4303 4304 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 4305 intel_bios_encoder_supports_hdmi(devdata); 4306 init_dp = intel_bios_encoder_supports_dp(devdata); 4307 4308 if (intel_bios_is_lspcon_present(dev_priv, port)) { 4309 /* 4310 * Lspcon device needs to be driven with DP connector 4311 * with special detection sequence. So make sure DP 4312 * is initialized before lspcon. 4313 */ 4314 init_dp = true; 4315 init_hdmi = false; 4316 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", 4317 port_name(port)); 4318 } 4319 4320 if (!init_dp && !init_hdmi) { 4321 drm_dbg_kms(&dev_priv->drm, 4322 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 4323 port_name(port)); 4324 return; 4325 } 4326 4327 if (intel_phy_is_snps(dev_priv, phy) && 4328 dev_priv->display.snps.phy_failed_calibration & BIT(phy)) { 4329 drm_dbg_kms(&dev_priv->drm, 4330 "SNPS PHY %c failed to calibrate, proceeding anyway\n", 4331 phy_name(phy)); 4332 } 4333 4334 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 4335 if (!dig_port) 4336 return; 4337 4338 encoder = &dig_port->base; 4339 encoder->devdata = devdata; 4340 4341 if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) { 4342 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4343 DRM_MODE_ENCODER_TMDS, 4344 "DDI %c/PHY %c", 4345 port_name(port - PORT_D_XELPD + PORT_D), 4346 phy_name(phy)); 4347 } else if (DISPLAY_VER(dev_priv) >= 12) { 4348 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4349 4350 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4351 DRM_MODE_ENCODER_TMDS, 4352 "DDI %s%c/PHY %s%c", 4353 port >= PORT_TC1 ? "TC" : "", 4354 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 4355 tc_port != TC_PORT_NONE ? "TC" : "", 4356 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4357 } else if (DISPLAY_VER(dev_priv) >= 11) { 4358 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4359 4360 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4361 DRM_MODE_ENCODER_TMDS, 4362 "DDI %c%s/PHY %s%c", 4363 port_name(port), 4364 port >= PORT_C ? " (TC)" : "", 4365 tc_port != TC_PORT_NONE ? "TC" : "", 4366 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4367 } else { 4368 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4369 DRM_MODE_ENCODER_TMDS, 4370 "DDI %c/PHY %c", port_name(port), phy_name(phy)); 4371 } 4372 4373 mutex_init(&dig_port->hdcp_mutex); 4374 dig_port->num_hdcp_streams = 0; 4375 4376 encoder->hotplug = intel_ddi_hotplug; 4377 encoder->compute_output_type = intel_ddi_compute_output_type; 4378 encoder->compute_config = intel_ddi_compute_config; 4379 encoder->compute_config_late = intel_ddi_compute_config_late; 4380 encoder->enable = intel_enable_ddi; 4381 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 4382 encoder->pre_enable = intel_ddi_pre_enable; 4383 encoder->disable = intel_disable_ddi; 4384 encoder->post_disable = intel_ddi_post_disable; 4385 encoder->update_pipe = intel_ddi_update_pipe; 4386 encoder->get_hw_state = intel_ddi_get_hw_state; 4387 encoder->sync_state = intel_ddi_sync_state; 4388 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 4389 encoder->suspend = intel_ddi_encoder_suspend; 4390 encoder->shutdown = intel_ddi_encoder_shutdown; 4391 encoder->get_power_domains = intel_ddi_get_power_domains; 4392 4393 encoder->type = INTEL_OUTPUT_DDI; 4394 encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port); 4395 encoder->port = port; 4396 encoder->cloneable = 0; 4397 encoder->pipe_mask = ~0; 4398 4399 if (IS_DG2(dev_priv)) { 4400 encoder->enable_clock = intel_mpllb_enable; 4401 encoder->disable_clock = intel_mpllb_disable; 4402 encoder->get_config = dg2_ddi_get_config; 4403 } else if (IS_ALDERLAKE_S(dev_priv)) { 4404 encoder->enable_clock = adls_ddi_enable_clock; 4405 encoder->disable_clock = adls_ddi_disable_clock; 4406 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 4407 encoder->get_config = adls_ddi_get_config; 4408 } else if (IS_ROCKETLAKE(dev_priv)) { 4409 encoder->enable_clock = rkl_ddi_enable_clock; 4410 encoder->disable_clock = rkl_ddi_disable_clock; 4411 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 4412 encoder->get_config = rkl_ddi_get_config; 4413 } else if (IS_DG1(dev_priv)) { 4414 encoder->enable_clock = dg1_ddi_enable_clock; 4415 encoder->disable_clock = dg1_ddi_disable_clock; 4416 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 4417 encoder->get_config = dg1_ddi_get_config; 4418 } else if (IS_JSL_EHL(dev_priv)) { 4419 if (intel_ddi_is_tc(dev_priv, port)) { 4420 encoder->enable_clock = jsl_ddi_tc_enable_clock; 4421 encoder->disable_clock = jsl_ddi_tc_disable_clock; 4422 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 4423 encoder->get_config = icl_ddi_combo_get_config; 4424 } else { 4425 encoder->enable_clock = icl_ddi_combo_enable_clock; 4426 encoder->disable_clock = icl_ddi_combo_disable_clock; 4427 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 4428 encoder->get_config = icl_ddi_combo_get_config; 4429 } 4430 } else if (DISPLAY_VER(dev_priv) >= 11) { 4431 if (intel_ddi_is_tc(dev_priv, port)) { 4432 encoder->enable_clock = icl_ddi_tc_enable_clock; 4433 encoder->disable_clock = icl_ddi_tc_disable_clock; 4434 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 4435 encoder->get_config = icl_ddi_tc_get_config; 4436 } else { 4437 encoder->enable_clock = icl_ddi_combo_enable_clock; 4438 encoder->disable_clock = icl_ddi_combo_disable_clock; 4439 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 4440 encoder->get_config = icl_ddi_combo_get_config; 4441 } 4442 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 4443 /* BXT/GLK have fixed PLL->port mapping */ 4444 encoder->get_config = bxt_ddi_get_config; 4445 } else if (DISPLAY_VER(dev_priv) == 9) { 4446 encoder->enable_clock = skl_ddi_enable_clock; 4447 encoder->disable_clock = skl_ddi_disable_clock; 4448 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 4449 encoder->get_config = skl_ddi_get_config; 4450 } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 4451 encoder->enable_clock = hsw_ddi_enable_clock; 4452 encoder->disable_clock = hsw_ddi_disable_clock; 4453 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 4454 encoder->get_config = hsw_ddi_get_config; 4455 } 4456 4457 if (IS_DG2(dev_priv)) { 4458 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 4459 } else if (DISPLAY_VER(dev_priv) >= 12) { 4460 if (intel_phy_is_combo(dev_priv, phy)) 4461 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 4462 else 4463 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 4464 } else if (DISPLAY_VER(dev_priv) >= 11) { 4465 if (intel_phy_is_combo(dev_priv, phy)) 4466 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 4467 else 4468 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 4469 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 4470 encoder->set_signal_levels = bxt_ddi_phy_set_signal_levels; 4471 } else { 4472 encoder->set_signal_levels = hsw_set_signal_levels; 4473 } 4474 4475 intel_ddi_buf_trans_init(encoder); 4476 4477 if (DISPLAY_VER(dev_priv) >= 13) 4478 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port); 4479 else if (IS_DG1(dev_priv)) 4480 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); 4481 else if (IS_ROCKETLAKE(dev_priv)) 4482 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); 4483 else if (DISPLAY_VER(dev_priv) >= 12) 4484 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); 4485 else if (IS_JSL_EHL(dev_priv)) 4486 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); 4487 else if (DISPLAY_VER(dev_priv) == 11) 4488 encoder->hpd_pin = icl_hpd_pin(dev_priv, port); 4489 else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 4490 encoder->hpd_pin = skl_hpd_pin(dev_priv, port); 4491 else 4492 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 4493 4494 if (DISPLAY_VER(dev_priv) >= 11) 4495 dig_port->saved_port_bits = 4496 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 4497 & DDI_BUF_PORT_REVERSAL; 4498 else 4499 dig_port->saved_port_bits = 4500 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 4501 & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 4502 4503 if (intel_bios_is_lane_reversal_needed(dev_priv, port)) 4504 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL; 4505 4506 dig_port->dp.output_reg = INVALID_MMIO_REG; 4507 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 4508 dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 4509 4510 if (intel_phy_is_tc(dev_priv, phy)) { 4511 bool is_legacy = 4512 !intel_bios_encoder_supports_typec_usb(devdata) && 4513 !intel_bios_encoder_supports_tbt(devdata); 4514 4515 intel_tc_port_init(dig_port, is_legacy); 4516 4517 encoder->update_prepare = intel_ddi_update_prepare; 4518 encoder->update_complete = intel_ddi_update_complete; 4519 } 4520 4521 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 4522 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(dev_priv, port); 4523 4524 if (init_dp) { 4525 if (!intel_ddi_init_dp_connector(dig_port)) 4526 goto err; 4527 4528 dig_port->hpd_pulse = intel_dp_hpd_pulse; 4529 4530 if (dig_port->dp.mso_link_count) 4531 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv); 4532 } 4533 4534 /* In theory we don't need the encoder->type check, but leave it just in 4535 * case we have some really bad VBTs... */ 4536 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 4537 if (!intel_ddi_init_hdmi_connector(dig_port)) 4538 goto err; 4539 } 4540 4541 if (DISPLAY_VER(dev_priv) >= 11) { 4542 if (intel_phy_is_tc(dev_priv, phy)) 4543 dig_port->connected = intel_tc_port_connected; 4544 else 4545 dig_port->connected = lpt_digital_port_connected; 4546 } else if (DISPLAY_VER(dev_priv) >= 8) { 4547 if (port == PORT_A || IS_GEMINILAKE(dev_priv) || 4548 IS_BROXTON(dev_priv)) 4549 dig_port->connected = bdw_digital_port_connected; 4550 else 4551 dig_port->connected = lpt_digital_port_connected; 4552 } else { 4553 if (port == PORT_A) 4554 dig_port->connected = hsw_digital_port_connected; 4555 else 4556 dig_port->connected = lpt_digital_port_connected; 4557 } 4558 4559 intel_infoframe_init(dig_port); 4560 4561 return; 4562 4563 err: 4564 drm_encoder_cleanup(&encoder->base); 4565 kfree(dig_port); 4566 } 4567