1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <drm/drm_scdc_helper.h> 29 30 #include "i915_drv.h" 31 #include "intel_audio.h" 32 #include "intel_combo_phy.h" 33 #include "intel_connector.h" 34 #include "intel_ddi.h" 35 #include "intel_dp.h" 36 #include "intel_dp_link_training.h" 37 #include "intel_dpio_phy.h" 38 #include "intel_drv.h" 39 #include "intel_dsi.h" 40 #include "intel_fifo_underrun.h" 41 #include "intel_gmbus.h" 42 #include "intel_hdcp.h" 43 #include "intel_hdmi.h" 44 #include "intel_hotplug.h" 45 #include "intel_lspcon.h" 46 #include "intel_panel.h" 47 #include "intel_psr.h" 48 #include "intel_tc.h" 49 #include "intel_vdsc.h" 50 51 struct ddi_buf_trans { 52 u32 trans1; /* balance leg enable, de-emph level */ 53 u32 trans2; /* vref sel, vswing */ 54 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */ 55 }; 56 57 static const u8 index_to_dp_signal_levels[] = { 58 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 59 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 60 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 61 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 62 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 63 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 64 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 65 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 66 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 67 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 68 }; 69 70 /* HDMI/DVI modes ignore everything but the last 2 items. So we share 71 * them for both DP and FDI transports, allowing those ports to 72 * automatically adapt to HDMI connections as well 73 */ 74 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { 75 { 0x00FFFFFF, 0x0006000E, 0x0 }, 76 { 0x00D75FFF, 0x0005000A, 0x0 }, 77 { 0x00C30FFF, 0x00040006, 0x0 }, 78 { 0x80AAAFFF, 0x000B0000, 0x0 }, 79 { 0x00FFFFFF, 0x0005000A, 0x0 }, 80 { 0x00D75FFF, 0x000C0004, 0x0 }, 81 { 0x80C30FFF, 0x000B0000, 0x0 }, 82 { 0x00FFFFFF, 0x00040006, 0x0 }, 83 { 0x80D75FFF, 0x000B0000, 0x0 }, 84 }; 85 86 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { 87 { 0x00FFFFFF, 0x0007000E, 0x0 }, 88 { 0x00D75FFF, 0x000F000A, 0x0 }, 89 { 0x00C30FFF, 0x00060006, 0x0 }, 90 { 0x00AAAFFF, 0x001E0000, 0x0 }, 91 { 0x00FFFFFF, 0x000F000A, 0x0 }, 92 { 0x00D75FFF, 0x00160004, 0x0 }, 93 { 0x00C30FFF, 0x001E0000, 0x0 }, 94 { 0x00FFFFFF, 0x00060006, 0x0 }, 95 { 0x00D75FFF, 0x001E0000, 0x0 }, 96 }; 97 98 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { 99 /* Idx NT mV d T mV d db */ 100 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */ 101 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */ 102 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */ 103 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */ 104 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */ 105 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */ 106 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */ 107 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */ 108 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */ 109 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */ 110 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */ 111 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */ 112 }; 113 114 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { 115 { 0x00FFFFFF, 0x00000012, 0x0 }, 116 { 0x00EBAFFF, 0x00020011, 0x0 }, 117 { 0x00C71FFF, 0x0006000F, 0x0 }, 118 { 0x00AAAFFF, 0x000E000A, 0x0 }, 119 { 0x00FFFFFF, 0x00020011, 0x0 }, 120 { 0x00DB6FFF, 0x0005000F, 0x0 }, 121 { 0x00BEEFFF, 0x000A000C, 0x0 }, 122 { 0x00FFFFFF, 0x0005000F, 0x0 }, 123 { 0x00DB6FFF, 0x000A000C, 0x0 }, 124 }; 125 126 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { 127 { 0x00FFFFFF, 0x0007000E, 0x0 }, 128 { 0x00D75FFF, 0x000E000A, 0x0 }, 129 { 0x00BEFFFF, 0x00140006, 0x0 }, 130 { 0x80B2CFFF, 0x001B0002, 0x0 }, 131 { 0x00FFFFFF, 0x000E000A, 0x0 }, 132 { 0x00DB6FFF, 0x00160005, 0x0 }, 133 { 0x80C71FFF, 0x001A0002, 0x0 }, 134 { 0x00F7DFFF, 0x00180004, 0x0 }, 135 { 0x80D75FFF, 0x001B0002, 0x0 }, 136 }; 137 138 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { 139 { 0x00FFFFFF, 0x0001000E, 0x0 }, 140 { 0x00D75FFF, 0x0004000A, 0x0 }, 141 { 0x00C30FFF, 0x00070006, 0x0 }, 142 { 0x00AAAFFF, 0x000C0000, 0x0 }, 143 { 0x00FFFFFF, 0x0004000A, 0x0 }, 144 { 0x00D75FFF, 0x00090004, 0x0 }, 145 { 0x00C30FFF, 0x000C0000, 0x0 }, 146 { 0x00FFFFFF, 0x00070006, 0x0 }, 147 { 0x00D75FFF, 0x000C0000, 0x0 }, 148 }; 149 150 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { 151 /* Idx NT mV d T mV df db */ 152 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */ 153 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */ 154 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */ 155 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */ 156 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */ 157 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */ 158 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */ 159 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */ 160 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */ 161 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */ 162 }; 163 164 /* Skylake H and S */ 165 static const struct ddi_buf_trans skl_ddi_translations_dp[] = { 166 { 0x00002016, 0x000000A0, 0x0 }, 167 { 0x00005012, 0x0000009B, 0x0 }, 168 { 0x00007011, 0x00000088, 0x0 }, 169 { 0x80009010, 0x000000C0, 0x1 }, 170 { 0x00002016, 0x0000009B, 0x0 }, 171 { 0x00005012, 0x00000088, 0x0 }, 172 { 0x80007011, 0x000000C0, 0x1 }, 173 { 0x00002016, 0x000000DF, 0x0 }, 174 { 0x80005012, 0x000000C0, 0x1 }, 175 }; 176 177 /* Skylake U */ 178 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { 179 { 0x0000201B, 0x000000A2, 0x0 }, 180 { 0x00005012, 0x00000088, 0x0 }, 181 { 0x80007011, 0x000000CD, 0x1 }, 182 { 0x80009010, 0x000000C0, 0x1 }, 183 { 0x0000201B, 0x0000009D, 0x0 }, 184 { 0x80005012, 0x000000C0, 0x1 }, 185 { 0x80007011, 0x000000C0, 0x1 }, 186 { 0x00002016, 0x00000088, 0x0 }, 187 { 0x80005012, 0x000000C0, 0x1 }, 188 }; 189 190 /* Skylake Y */ 191 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { 192 { 0x00000018, 0x000000A2, 0x0 }, 193 { 0x00005012, 0x00000088, 0x0 }, 194 { 0x80007011, 0x000000CD, 0x3 }, 195 { 0x80009010, 0x000000C0, 0x3 }, 196 { 0x00000018, 0x0000009D, 0x0 }, 197 { 0x80005012, 0x000000C0, 0x3 }, 198 { 0x80007011, 0x000000C0, 0x3 }, 199 { 0x00000018, 0x00000088, 0x0 }, 200 { 0x80005012, 0x000000C0, 0x3 }, 201 }; 202 203 /* Kabylake H and S */ 204 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = { 205 { 0x00002016, 0x000000A0, 0x0 }, 206 { 0x00005012, 0x0000009B, 0x0 }, 207 { 0x00007011, 0x00000088, 0x0 }, 208 { 0x80009010, 0x000000C0, 0x1 }, 209 { 0x00002016, 0x0000009B, 0x0 }, 210 { 0x00005012, 0x00000088, 0x0 }, 211 { 0x80007011, 0x000000C0, 0x1 }, 212 { 0x00002016, 0x00000097, 0x0 }, 213 { 0x80005012, 0x000000C0, 0x1 }, 214 }; 215 216 /* Kabylake U */ 217 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = { 218 { 0x0000201B, 0x000000A1, 0x0 }, 219 { 0x00005012, 0x00000088, 0x0 }, 220 { 0x80007011, 0x000000CD, 0x3 }, 221 { 0x80009010, 0x000000C0, 0x3 }, 222 { 0x0000201B, 0x0000009D, 0x0 }, 223 { 0x80005012, 0x000000C0, 0x3 }, 224 { 0x80007011, 0x000000C0, 0x3 }, 225 { 0x00002016, 0x0000004F, 0x0 }, 226 { 0x80005012, 0x000000C0, 0x3 }, 227 }; 228 229 /* Kabylake Y */ 230 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = { 231 { 0x00001017, 0x000000A1, 0x0 }, 232 { 0x00005012, 0x00000088, 0x0 }, 233 { 0x80007011, 0x000000CD, 0x3 }, 234 { 0x8000800F, 0x000000C0, 0x3 }, 235 { 0x00001017, 0x0000009D, 0x0 }, 236 { 0x80005012, 0x000000C0, 0x3 }, 237 { 0x80007011, 0x000000C0, 0x3 }, 238 { 0x00001017, 0x0000004C, 0x0 }, 239 { 0x80005012, 0x000000C0, 0x3 }, 240 }; 241 242 /* 243 * Skylake/Kabylake H and S 244 * eDP 1.4 low vswing translation parameters 245 */ 246 static const struct ddi_buf_trans skl_ddi_translations_edp[] = { 247 { 0x00000018, 0x000000A8, 0x0 }, 248 { 0x00004013, 0x000000A9, 0x0 }, 249 { 0x00007011, 0x000000A2, 0x0 }, 250 { 0x00009010, 0x0000009C, 0x0 }, 251 { 0x00000018, 0x000000A9, 0x0 }, 252 { 0x00006013, 0x000000A2, 0x0 }, 253 { 0x00007011, 0x000000A6, 0x0 }, 254 { 0x00000018, 0x000000AB, 0x0 }, 255 { 0x00007013, 0x0000009F, 0x0 }, 256 { 0x00000018, 0x000000DF, 0x0 }, 257 }; 258 259 /* 260 * Skylake/Kabylake U 261 * eDP 1.4 low vswing translation parameters 262 */ 263 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = { 264 { 0x00000018, 0x000000A8, 0x0 }, 265 { 0x00004013, 0x000000A9, 0x0 }, 266 { 0x00007011, 0x000000A2, 0x0 }, 267 { 0x00009010, 0x0000009C, 0x0 }, 268 { 0x00000018, 0x000000A9, 0x0 }, 269 { 0x00006013, 0x000000A2, 0x0 }, 270 { 0x00007011, 0x000000A6, 0x0 }, 271 { 0x00002016, 0x000000AB, 0x0 }, 272 { 0x00005013, 0x0000009F, 0x0 }, 273 { 0x00000018, 0x000000DF, 0x0 }, 274 }; 275 276 /* 277 * Skylake/Kabylake Y 278 * eDP 1.4 low vswing translation parameters 279 */ 280 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = { 281 { 0x00000018, 0x000000A8, 0x0 }, 282 { 0x00004013, 0x000000AB, 0x0 }, 283 { 0x00007011, 0x000000A4, 0x0 }, 284 { 0x00009010, 0x000000DF, 0x0 }, 285 { 0x00000018, 0x000000AA, 0x0 }, 286 { 0x00006013, 0x000000A4, 0x0 }, 287 { 0x00007011, 0x0000009D, 0x0 }, 288 { 0x00000018, 0x000000A0, 0x0 }, 289 { 0x00006012, 0x000000DF, 0x0 }, 290 { 0x00000018, 0x0000008A, 0x0 }, 291 }; 292 293 /* Skylake/Kabylake U, H and S */ 294 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { 295 { 0x00000018, 0x000000AC, 0x0 }, 296 { 0x00005012, 0x0000009D, 0x0 }, 297 { 0x00007011, 0x00000088, 0x0 }, 298 { 0x00000018, 0x000000A1, 0x0 }, 299 { 0x00000018, 0x00000098, 0x0 }, 300 { 0x00004013, 0x00000088, 0x0 }, 301 { 0x80006012, 0x000000CD, 0x1 }, 302 { 0x00000018, 0x000000DF, 0x0 }, 303 { 0x80003015, 0x000000CD, 0x1 }, /* Default */ 304 { 0x80003015, 0x000000C0, 0x1 }, 305 { 0x80000018, 0x000000C0, 0x1 }, 306 }; 307 308 /* Skylake/Kabylake Y */ 309 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { 310 { 0x00000018, 0x000000A1, 0x0 }, 311 { 0x00005012, 0x000000DF, 0x0 }, 312 { 0x80007011, 0x000000CB, 0x3 }, 313 { 0x00000018, 0x000000A4, 0x0 }, 314 { 0x00000018, 0x0000009D, 0x0 }, 315 { 0x00004013, 0x00000080, 0x0 }, 316 { 0x80006013, 0x000000C0, 0x3 }, 317 { 0x00000018, 0x0000008A, 0x0 }, 318 { 0x80003015, 0x000000C0, 0x3 }, /* Default */ 319 { 0x80003015, 0x000000C0, 0x3 }, 320 { 0x80000018, 0x000000C0, 0x3 }, 321 }; 322 323 struct bxt_ddi_buf_trans { 324 u8 margin; /* swing value */ 325 u8 scale; /* scale value */ 326 u8 enable; /* scale enable */ 327 u8 deemphasis; 328 }; 329 330 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { 331 /* Idx NT mV diff db */ 332 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ 333 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */ 334 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */ 335 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */ 336 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */ 337 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */ 338 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */ 339 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */ 340 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */ 341 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */ 342 }; 343 344 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = { 345 /* Idx NT mV diff db */ 346 { 26, 0, 0, 128, }, /* 0: 200 0 */ 347 { 38, 0, 0, 112, }, /* 1: 200 1.5 */ 348 { 48, 0, 0, 96, }, /* 2: 200 4 */ 349 { 54, 0, 0, 69, }, /* 3: 200 6 */ 350 { 32, 0, 0, 128, }, /* 4: 250 0 */ 351 { 48, 0, 0, 104, }, /* 5: 250 1.5 */ 352 { 54, 0, 0, 85, }, /* 6: 250 4 */ 353 { 43, 0, 0, 128, }, /* 7: 300 0 */ 354 { 54, 0, 0, 101, }, /* 8: 300 1.5 */ 355 { 48, 0, 0, 128, }, /* 9: 300 0 */ 356 }; 357 358 /* BSpec has 2 recommended values - entries 0 and 8. 359 * Using the entry with higher vswing. 360 */ 361 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = { 362 /* Idx NT mV diff db */ 363 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ 364 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */ 365 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */ 366 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */ 367 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */ 368 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */ 369 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */ 370 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */ 371 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */ 372 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */ 373 }; 374 375 struct cnl_ddi_buf_trans { 376 u8 dw2_swing_sel; 377 u8 dw7_n_scalar; 378 u8 dw4_cursor_coeff; 379 u8 dw4_post_cursor_2; 380 u8 dw4_post_cursor_1; 381 }; 382 383 /* Voltage Swing Programming for VccIO 0.85V for DP */ 384 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = { 385 /* NT mV Trans mV db */ 386 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 387 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ 388 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ 389 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ 390 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 391 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 392 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 393 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ 394 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ 395 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 396 }; 397 398 /* Voltage Swing Programming for VccIO 0.85V for HDMI */ 399 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = { 400 /* NT mV Trans mV db */ 401 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 402 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ 403 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ 404 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */ 405 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ 406 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ 407 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 408 }; 409 410 /* Voltage Swing Programming for VccIO 0.85V for eDP */ 411 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = { 412 /* NT mV Trans mV db */ 413 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 414 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 415 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 416 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 417 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 418 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 419 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */ 420 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */ 421 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 422 }; 423 424 /* Voltage Swing Programming for VccIO 0.95V for DP */ 425 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = { 426 /* NT mV Trans mV db */ 427 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 428 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ 429 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ 430 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ 431 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 432 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 433 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 434 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ 435 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ 436 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 437 }; 438 439 /* Voltage Swing Programming for VccIO 0.95V for HDMI */ 440 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = { 441 /* NT mV Trans mV db */ 442 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 443 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 444 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 445 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 446 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 447 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 448 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ 449 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ 450 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ 451 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ 452 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 453 }; 454 455 /* Voltage Swing Programming for VccIO 0.95V for eDP */ 456 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = { 457 /* NT mV Trans mV db */ 458 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 459 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 460 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 461 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 462 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 463 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 464 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ 465 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ 466 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */ 467 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 468 }; 469 470 /* Voltage Swing Programming for VccIO 1.05V for DP */ 471 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = { 472 /* NT mV Trans mV db */ 473 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 474 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 475 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 476 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */ 477 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 478 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 479 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */ 480 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */ 481 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */ 482 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 483 }; 484 485 /* Voltage Swing Programming for VccIO 1.05V for HDMI */ 486 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = { 487 /* NT mV Trans mV db */ 488 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 489 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 490 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 491 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 492 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 493 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 494 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ 495 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ 496 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ 497 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ 498 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 499 }; 500 501 /* Voltage Swing Programming for VccIO 1.05V for eDP */ 502 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = { 503 /* NT mV Trans mV db */ 504 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 505 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 506 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 507 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 508 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 509 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 510 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ 511 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ 512 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 513 }; 514 515 /* icl_combo_phy_ddi_translations */ 516 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = { 517 /* NT mV Trans mV db */ 518 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 519 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 520 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 521 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 522 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 523 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 524 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 525 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 526 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 527 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 528 }; 529 530 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = { 531 /* NT mV Trans mV db */ 532 { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ 533 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */ 534 { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */ 535 { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */ 536 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ 537 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */ 538 { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */ 539 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ 540 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ 541 { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 542 }; 543 544 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = { 545 /* NT mV Trans mV db */ 546 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 547 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 548 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 549 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 550 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 551 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 552 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 553 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 554 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 555 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 556 }; 557 558 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = { 559 /* NT mV Trans mV db */ 560 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 561 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ 562 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ 563 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */ 564 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ 565 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ 566 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 567 }; 568 569 struct icl_mg_phy_ddi_buf_trans { 570 u32 cri_txdeemph_override_5_0; 571 u32 cri_txdeemph_override_11_6; 572 u32 cri_txdeemph_override_17_12; 573 }; 574 575 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = { 576 /* Voltage swing pre-emphasis */ 577 { 0x0, 0x1B, 0x00 }, /* 0 0 */ 578 { 0x0, 0x23, 0x08 }, /* 0 1 */ 579 { 0x0, 0x2D, 0x12 }, /* 0 2 */ 580 { 0x0, 0x00, 0x00 }, /* 0 3 */ 581 { 0x0, 0x23, 0x00 }, /* 1 0 */ 582 { 0x0, 0x2B, 0x09 }, /* 1 1 */ 583 { 0x0, 0x2E, 0x11 }, /* 1 2 */ 584 { 0x0, 0x2F, 0x00 }, /* 2 0 */ 585 { 0x0, 0x33, 0x0C }, /* 2 1 */ 586 { 0x0, 0x00, 0x00 }, /* 3 0 */ 587 }; 588 589 static const struct ddi_buf_trans * 590 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 591 { 592 if (dev_priv->vbt.edp.low_vswing) { 593 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp); 594 return bdw_ddi_translations_edp; 595 } else { 596 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 597 return bdw_ddi_translations_dp; 598 } 599 } 600 601 static const struct ddi_buf_trans * 602 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 603 { 604 if (IS_SKL_ULX(dev_priv)) { 605 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); 606 return skl_y_ddi_translations_dp; 607 } else if (IS_SKL_ULT(dev_priv)) { 608 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); 609 return skl_u_ddi_translations_dp; 610 } else { 611 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); 612 return skl_ddi_translations_dp; 613 } 614 } 615 616 static const struct ddi_buf_trans * 617 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 618 { 619 if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv)) { 620 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp); 621 return kbl_y_ddi_translations_dp; 622 } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) { 623 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp); 624 return kbl_u_ddi_translations_dp; 625 } else { 626 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp); 627 return kbl_ddi_translations_dp; 628 } 629 } 630 631 static const struct ddi_buf_trans * 632 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 633 { 634 if (dev_priv->vbt.edp.low_vswing) { 635 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || 636 IS_CFL_ULX(dev_priv)) { 637 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); 638 return skl_y_ddi_translations_edp; 639 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) || 640 IS_CFL_ULT(dev_priv)) { 641 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); 642 return skl_u_ddi_translations_edp; 643 } else { 644 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp); 645 return skl_ddi_translations_edp; 646 } 647 } 648 649 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) 650 return kbl_get_buf_trans_dp(dev_priv, n_entries); 651 else 652 return skl_get_buf_trans_dp(dev_priv, n_entries); 653 } 654 655 static const struct ddi_buf_trans * 656 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) 657 { 658 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || 659 IS_CFL_ULX(dev_priv)) { 660 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); 661 return skl_y_ddi_translations_hdmi; 662 } else { 663 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); 664 return skl_ddi_translations_hdmi; 665 } 666 } 667 668 static int skl_buf_trans_num_entries(enum port port, int n_entries) 669 { 670 /* Only DDIA and DDIE can select the 10th register with DP */ 671 if (port == PORT_A || port == PORT_E) 672 return min(n_entries, 10); 673 else 674 return min(n_entries, 9); 675 } 676 677 static const struct ddi_buf_trans * 678 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv, 679 enum port port, int *n_entries) 680 { 681 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) { 682 const struct ddi_buf_trans *ddi_translations = 683 kbl_get_buf_trans_dp(dev_priv, n_entries); 684 *n_entries = skl_buf_trans_num_entries(port, *n_entries); 685 return ddi_translations; 686 } else if (IS_SKYLAKE(dev_priv)) { 687 const struct ddi_buf_trans *ddi_translations = 688 skl_get_buf_trans_dp(dev_priv, n_entries); 689 *n_entries = skl_buf_trans_num_entries(port, *n_entries); 690 return ddi_translations; 691 } else if (IS_BROADWELL(dev_priv)) { 692 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 693 return bdw_ddi_translations_dp; 694 } else if (IS_HASWELL(dev_priv)) { 695 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 696 return hsw_ddi_translations_dp; 697 } 698 699 *n_entries = 0; 700 return NULL; 701 } 702 703 static const struct ddi_buf_trans * 704 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv, 705 enum port port, int *n_entries) 706 { 707 if (IS_GEN9_BC(dev_priv)) { 708 const struct ddi_buf_trans *ddi_translations = 709 skl_get_buf_trans_edp(dev_priv, n_entries); 710 *n_entries = skl_buf_trans_num_entries(port, *n_entries); 711 return ddi_translations; 712 } else if (IS_BROADWELL(dev_priv)) { 713 return bdw_get_buf_trans_edp(dev_priv, n_entries); 714 } else if (IS_HASWELL(dev_priv)) { 715 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 716 return hsw_ddi_translations_dp; 717 } 718 719 *n_entries = 0; 720 return NULL; 721 } 722 723 static const struct ddi_buf_trans * 724 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, 725 int *n_entries) 726 { 727 if (IS_BROADWELL(dev_priv)) { 728 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi); 729 return bdw_ddi_translations_fdi; 730 } else if (IS_HASWELL(dev_priv)) { 731 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi); 732 return hsw_ddi_translations_fdi; 733 } 734 735 *n_entries = 0; 736 return NULL; 737 } 738 739 static const struct ddi_buf_trans * 740 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, 741 int *n_entries) 742 { 743 if (IS_GEN9_BC(dev_priv)) { 744 return skl_get_buf_trans_hdmi(dev_priv, n_entries); 745 } else if (IS_BROADWELL(dev_priv)) { 746 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 747 return bdw_ddi_translations_hdmi; 748 } else if (IS_HASWELL(dev_priv)) { 749 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); 750 return hsw_ddi_translations_hdmi; 751 } 752 753 *n_entries = 0; 754 return NULL; 755 } 756 757 static const struct bxt_ddi_buf_trans * 758 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 759 { 760 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); 761 return bxt_ddi_translations_dp; 762 } 763 764 static const struct bxt_ddi_buf_trans * 765 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 766 { 767 if (dev_priv->vbt.edp.low_vswing) { 768 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp); 769 return bxt_ddi_translations_edp; 770 } 771 772 return bxt_get_buf_trans_dp(dev_priv, n_entries); 773 } 774 775 static const struct bxt_ddi_buf_trans * 776 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) 777 { 778 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); 779 return bxt_ddi_translations_hdmi; 780 } 781 782 static const struct cnl_ddi_buf_trans * 783 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) 784 { 785 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 786 787 if (voltage == VOLTAGE_INFO_0_85V) { 788 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V); 789 return cnl_ddi_translations_hdmi_0_85V; 790 } else if (voltage == VOLTAGE_INFO_0_95V) { 791 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V); 792 return cnl_ddi_translations_hdmi_0_95V; 793 } else if (voltage == VOLTAGE_INFO_1_05V) { 794 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V); 795 return cnl_ddi_translations_hdmi_1_05V; 796 } else { 797 *n_entries = 1; /* shut up gcc */ 798 MISSING_CASE(voltage); 799 } 800 return NULL; 801 } 802 803 static const struct cnl_ddi_buf_trans * 804 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 805 { 806 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 807 808 if (voltage == VOLTAGE_INFO_0_85V) { 809 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V); 810 return cnl_ddi_translations_dp_0_85V; 811 } else if (voltage == VOLTAGE_INFO_0_95V) { 812 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V); 813 return cnl_ddi_translations_dp_0_95V; 814 } else if (voltage == VOLTAGE_INFO_1_05V) { 815 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V); 816 return cnl_ddi_translations_dp_1_05V; 817 } else { 818 *n_entries = 1; /* shut up gcc */ 819 MISSING_CASE(voltage); 820 } 821 return NULL; 822 } 823 824 static const struct cnl_ddi_buf_trans * 825 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 826 { 827 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 828 829 if (dev_priv->vbt.edp.low_vswing) { 830 if (voltage == VOLTAGE_INFO_0_85V) { 831 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V); 832 return cnl_ddi_translations_edp_0_85V; 833 } else if (voltage == VOLTAGE_INFO_0_95V) { 834 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V); 835 return cnl_ddi_translations_edp_0_95V; 836 } else if (voltage == VOLTAGE_INFO_1_05V) { 837 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V); 838 return cnl_ddi_translations_edp_1_05V; 839 } else { 840 *n_entries = 1; /* shut up gcc */ 841 MISSING_CASE(voltage); 842 } 843 return NULL; 844 } else { 845 return cnl_get_buf_trans_dp(dev_priv, n_entries); 846 } 847 } 848 849 static const struct cnl_ddi_buf_trans * 850 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, 851 int *n_entries) 852 { 853 if (type == INTEL_OUTPUT_HDMI) { 854 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); 855 return icl_combo_phy_ddi_translations_hdmi; 856 } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) { 857 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3); 858 return icl_combo_phy_ddi_translations_edp_hbr3; 859 } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) { 860 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2); 861 return icl_combo_phy_ddi_translations_edp_hbr2; 862 } 863 864 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2); 865 return icl_combo_phy_ddi_translations_dp_hbr2; 866 } 867 868 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port) 869 { 870 int n_entries, level, default_entry; 871 enum phy phy = intel_port_to_phy(dev_priv, port); 872 873 level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; 874 875 if (INTEL_GEN(dev_priv) >= 11) { 876 if (intel_phy_is_combo(dev_priv, phy)) 877 icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 878 0, &n_entries); 879 else 880 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations); 881 default_entry = n_entries - 1; 882 } else if (IS_CANNONLAKE(dev_priv)) { 883 cnl_get_buf_trans_hdmi(dev_priv, &n_entries); 884 default_entry = n_entries - 1; 885 } else if (IS_GEN9_LP(dev_priv)) { 886 bxt_get_buf_trans_hdmi(dev_priv, &n_entries); 887 default_entry = n_entries - 1; 888 } else if (IS_GEN9_BC(dev_priv)) { 889 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 890 default_entry = 8; 891 } else if (IS_BROADWELL(dev_priv)) { 892 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 893 default_entry = 7; 894 } else if (IS_HASWELL(dev_priv)) { 895 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 896 default_entry = 6; 897 } else { 898 WARN(1, "ddi translation table missing\n"); 899 return 0; 900 } 901 902 /* Choose a good default if VBT is badly populated */ 903 if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries) 904 level = default_entry; 905 906 if (WARN_ON_ONCE(n_entries == 0)) 907 return 0; 908 if (WARN_ON_ONCE(level >= n_entries)) 909 level = n_entries - 1; 910 911 return level; 912 } 913 914 /* 915 * Starting with Haswell, DDI port buffers must be programmed with correct 916 * values in advance. This function programs the correct values for 917 * DP/eDP/FDI use cases. 918 */ 919 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 920 const struct intel_crtc_state *crtc_state) 921 { 922 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 923 u32 iboost_bit = 0; 924 int i, n_entries; 925 enum port port = encoder->port; 926 const struct ddi_buf_trans *ddi_translations; 927 928 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) 929 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv, 930 &n_entries); 931 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 932 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, 933 &n_entries); 934 else 935 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, 936 &n_entries); 937 938 /* If we're boosting the current, set bit 31 of trans1 */ 939 if (IS_GEN9_BC(dev_priv) && 940 dev_priv->vbt.ddi_port_info[port].dp_boost_level) 941 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 942 943 for (i = 0; i < n_entries; i++) { 944 I915_WRITE(DDI_BUF_TRANS_LO(port, i), 945 ddi_translations[i].trans1 | iboost_bit); 946 I915_WRITE(DDI_BUF_TRANS_HI(port, i), 947 ddi_translations[i].trans2); 948 } 949 } 950 951 /* 952 * Starting with Haswell, DDI port buffers must be programmed with correct 953 * values in advance. This function programs the correct values for 954 * HDMI/DVI use cases. 955 */ 956 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 957 int level) 958 { 959 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 960 u32 iboost_bit = 0; 961 int n_entries; 962 enum port port = encoder->port; 963 const struct ddi_buf_trans *ddi_translations; 964 965 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 966 967 if (WARN_ON_ONCE(!ddi_translations)) 968 return; 969 if (WARN_ON_ONCE(level >= n_entries)) 970 level = n_entries - 1; 971 972 /* If we're boosting the current, set bit 31 of trans1 */ 973 if (IS_GEN9_BC(dev_priv) && 974 dev_priv->vbt.ddi_port_info[port].hdmi_boost_level) 975 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 976 977 /* Entry 9 is for HDMI: */ 978 I915_WRITE(DDI_BUF_TRANS_LO(port, 9), 979 ddi_translations[level].trans1 | iboost_bit); 980 I915_WRITE(DDI_BUF_TRANS_HI(port, 9), 981 ddi_translations[level].trans2); 982 } 983 984 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 985 enum port port) 986 { 987 i915_reg_t reg = DDI_BUF_CTL(port); 988 int i; 989 990 for (i = 0; i < 16; i++) { 991 udelay(1); 992 if (I915_READ(reg) & DDI_BUF_IS_IDLE) 993 return; 994 } 995 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); 996 } 997 998 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 999 { 1000 switch (pll->info->id) { 1001 case DPLL_ID_WRPLL1: 1002 return PORT_CLK_SEL_WRPLL1; 1003 case DPLL_ID_WRPLL2: 1004 return PORT_CLK_SEL_WRPLL2; 1005 case DPLL_ID_SPLL: 1006 return PORT_CLK_SEL_SPLL; 1007 case DPLL_ID_LCPLL_810: 1008 return PORT_CLK_SEL_LCPLL_810; 1009 case DPLL_ID_LCPLL_1350: 1010 return PORT_CLK_SEL_LCPLL_1350; 1011 case DPLL_ID_LCPLL_2700: 1012 return PORT_CLK_SEL_LCPLL_2700; 1013 default: 1014 MISSING_CASE(pll->info->id); 1015 return PORT_CLK_SEL_NONE; 1016 } 1017 } 1018 1019 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 1020 const struct intel_crtc_state *crtc_state) 1021 { 1022 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1023 int clock = crtc_state->port_clock; 1024 const enum intel_dpll_id id = pll->info->id; 1025 1026 switch (id) { 1027 default: 1028 /* 1029 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 1030 * here, so do warn if this get passed in 1031 */ 1032 MISSING_CASE(id); 1033 return DDI_CLK_SEL_NONE; 1034 case DPLL_ID_ICL_TBTPLL: 1035 switch (clock) { 1036 case 162000: 1037 return DDI_CLK_SEL_TBT_162; 1038 case 270000: 1039 return DDI_CLK_SEL_TBT_270; 1040 case 540000: 1041 return DDI_CLK_SEL_TBT_540; 1042 case 810000: 1043 return DDI_CLK_SEL_TBT_810; 1044 default: 1045 MISSING_CASE(clock); 1046 return DDI_CLK_SEL_NONE; 1047 } 1048 case DPLL_ID_ICL_MGPLL1: 1049 case DPLL_ID_ICL_MGPLL2: 1050 case DPLL_ID_ICL_MGPLL3: 1051 case DPLL_ID_ICL_MGPLL4: 1052 return DDI_CLK_SEL_MG; 1053 } 1054 } 1055 1056 /* Starting with Haswell, different DDI ports can work in FDI mode for 1057 * connection to the PCH-located connectors. For this, it is necessary to train 1058 * both the DDI port and PCH receiver for the desired DDI buffer settings. 1059 * 1060 * The recommended port to work in FDI mode is DDI E, which we use here. Also, 1061 * please note that when FDI mode is active on DDI E, it shares 2 lines with 1062 * DDI A (which is used for eDP) 1063 */ 1064 1065 void hsw_fdi_link_train(struct intel_crtc *crtc, 1066 const struct intel_crtc_state *crtc_state) 1067 { 1068 struct drm_device *dev = crtc->base.dev; 1069 struct drm_i915_private *dev_priv = to_i915(dev); 1070 struct intel_encoder *encoder; 1071 u32 temp, i, rx_ctl_val, ddi_pll_sel; 1072 1073 for_each_encoder_on_crtc(dev, &crtc->base, encoder) { 1074 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG); 1075 intel_prepare_dp_ddi_buffers(encoder, crtc_state); 1076 } 1077 1078 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the 1079 * mode set "sequence for CRT port" document: 1080 * - TP1 to TP2 time with the default value 1081 * - FDI delay to 90h 1082 * 1083 * WaFDIAutoLinkSetTimingOverrride:hsw 1084 */ 1085 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) | 1086 FDI_RX_PWRDN_LANE0_VAL(2) | 1087 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 1088 1089 /* Enable the PCH Receiver FDI PLL */ 1090 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | 1091 FDI_RX_PLL_ENABLE | 1092 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); 1093 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 1094 POSTING_READ(FDI_RX_CTL(PIPE_A)); 1095 udelay(220); 1096 1097 /* Switch from Rawclk to PCDclk */ 1098 rx_ctl_val |= FDI_PCDCLK; 1099 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 1100 1101 /* Configure Port Clock Select */ 1102 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll); 1103 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel); 1104 WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL); 1105 1106 /* Start the training iterating through available voltages and emphasis, 1107 * testing each value twice. */ 1108 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { 1109 /* Configure DP_TP_CTL with auto-training */ 1110 I915_WRITE(DP_TP_CTL(PORT_E), 1111 DP_TP_CTL_FDI_AUTOTRAIN | 1112 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 1113 DP_TP_CTL_LINK_TRAIN_PAT1 | 1114 DP_TP_CTL_ENABLE); 1115 1116 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. 1117 * DDI E does not support port reversal, the functionality is 1118 * achieved on the PCH side in FDI_RX_CTL, so no need to set the 1119 * port reversal bit */ 1120 I915_WRITE(DDI_BUF_CTL(PORT_E), 1121 DDI_BUF_CTL_ENABLE | 1122 ((crtc_state->fdi_lanes - 1) << 1) | 1123 DDI_BUF_TRANS_SELECT(i / 2)); 1124 POSTING_READ(DDI_BUF_CTL(PORT_E)); 1125 1126 udelay(600); 1127 1128 /* Program PCH FDI Receiver TU */ 1129 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); 1130 1131 /* Enable PCH FDI Receiver with auto-training */ 1132 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; 1133 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 1134 POSTING_READ(FDI_RX_CTL(PIPE_A)); 1135 1136 /* Wait for FDI receiver lane calibration */ 1137 udelay(30); 1138 1139 /* Unset FDI_RX_MISC pwrdn lanes */ 1140 temp = I915_READ(FDI_RX_MISC(PIPE_A)); 1141 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 1142 I915_WRITE(FDI_RX_MISC(PIPE_A), temp); 1143 POSTING_READ(FDI_RX_MISC(PIPE_A)); 1144 1145 /* Wait for FDI auto training time */ 1146 udelay(5); 1147 1148 temp = I915_READ(DP_TP_STATUS(PORT_E)); 1149 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { 1150 DRM_DEBUG_KMS("FDI link training done on step %d\n", i); 1151 break; 1152 } 1153 1154 /* 1155 * Leave things enabled even if we failed to train FDI. 1156 * Results in less fireworks from the state checker. 1157 */ 1158 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) { 1159 DRM_ERROR("FDI link training failed!\n"); 1160 break; 1161 } 1162 1163 rx_ctl_val &= ~FDI_RX_ENABLE; 1164 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 1165 POSTING_READ(FDI_RX_CTL(PIPE_A)); 1166 1167 temp = I915_READ(DDI_BUF_CTL(PORT_E)); 1168 temp &= ~DDI_BUF_CTL_ENABLE; 1169 I915_WRITE(DDI_BUF_CTL(PORT_E), temp); 1170 POSTING_READ(DDI_BUF_CTL(PORT_E)); 1171 1172 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ 1173 temp = I915_READ(DP_TP_CTL(PORT_E)); 1174 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 1175 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 1176 I915_WRITE(DP_TP_CTL(PORT_E), temp); 1177 POSTING_READ(DP_TP_CTL(PORT_E)); 1178 1179 intel_wait_ddi_buf_idle(dev_priv, PORT_E); 1180 1181 /* Reset FDI_RX_MISC pwrdn lanes */ 1182 temp = I915_READ(FDI_RX_MISC(PIPE_A)); 1183 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 1184 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 1185 I915_WRITE(FDI_RX_MISC(PIPE_A), temp); 1186 POSTING_READ(FDI_RX_MISC(PIPE_A)); 1187 } 1188 1189 /* Enable normal pixel sending for FDI */ 1190 I915_WRITE(DP_TP_CTL(PORT_E), 1191 DP_TP_CTL_FDI_AUTOTRAIN | 1192 DP_TP_CTL_LINK_TRAIN_NORMAL | 1193 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 1194 DP_TP_CTL_ENABLE); 1195 } 1196 1197 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) 1198 { 1199 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1200 struct intel_digital_port *intel_dig_port = 1201 enc_to_dig_port(&encoder->base); 1202 1203 intel_dp->DP = intel_dig_port->saved_port_bits | 1204 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); 1205 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); 1206 } 1207 1208 static struct intel_encoder * 1209 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc) 1210 { 1211 struct drm_device *dev = crtc->base.dev; 1212 struct intel_encoder *encoder, *ret = NULL; 1213 int num_encoders = 0; 1214 1215 for_each_encoder_on_crtc(dev, &crtc->base, encoder) { 1216 ret = encoder; 1217 num_encoders++; 1218 } 1219 1220 if (num_encoders != 1) 1221 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, 1222 pipe_name(crtc->pipe)); 1223 1224 BUG_ON(ret == NULL); 1225 return ret; 1226 } 1227 1228 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, 1229 i915_reg_t reg) 1230 { 1231 int refclk; 1232 int n, p, r; 1233 u32 wrpll; 1234 1235 wrpll = I915_READ(reg); 1236 switch (wrpll & WRPLL_REF_MASK) { 1237 case WRPLL_REF_SPECIAL_HSW: 1238 /* 1239 * muxed-SSC for BDW. 1240 * non-SSC for non-ULT HSW. Check FUSE_STRAP3 1241 * for the non-SSC reference frequency. 1242 */ 1243 if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) { 1244 if (I915_READ(FUSE_STRAP3) & HSW_REF_CLK_SELECT) 1245 refclk = 24; 1246 else 1247 refclk = 135; 1248 break; 1249 } 1250 /* fall through */ 1251 case WRPLL_REF_PCH_SSC: 1252 /* 1253 * We could calculate spread here, but our checking 1254 * code only cares about 5% accuracy, and spread is a max of 1255 * 0.5% downspread. 1256 */ 1257 refclk = 135; 1258 break; 1259 case WRPLL_REF_LCPLL: 1260 refclk = 2700; 1261 break; 1262 default: 1263 MISSING_CASE(wrpll); 1264 return 0; 1265 } 1266 1267 r = wrpll & WRPLL_DIVIDER_REF_MASK; 1268 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; 1269 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; 1270 1271 /* Convert to KHz, p & r have a fixed point portion */ 1272 return (refclk * n * 100) / (p * r); 1273 } 1274 1275 static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state) 1276 { 1277 u32 p0, p1, p2, dco_freq; 1278 1279 p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK; 1280 p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK; 1281 1282 if (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_MODE(1)) 1283 p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; 1284 else 1285 p1 = 1; 1286 1287 1288 switch (p0) { 1289 case DPLL_CFGCR2_PDIV_1: 1290 p0 = 1; 1291 break; 1292 case DPLL_CFGCR2_PDIV_2: 1293 p0 = 2; 1294 break; 1295 case DPLL_CFGCR2_PDIV_3: 1296 p0 = 3; 1297 break; 1298 case DPLL_CFGCR2_PDIV_7: 1299 p0 = 7; 1300 break; 1301 } 1302 1303 switch (p2) { 1304 case DPLL_CFGCR2_KDIV_5: 1305 p2 = 5; 1306 break; 1307 case DPLL_CFGCR2_KDIV_2: 1308 p2 = 2; 1309 break; 1310 case DPLL_CFGCR2_KDIV_3: 1311 p2 = 3; 1312 break; 1313 case DPLL_CFGCR2_KDIV_1: 1314 p2 = 1; 1315 break; 1316 } 1317 1318 dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK) 1319 * 24 * 1000; 1320 1321 dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) 1322 * 24 * 1000) / 0x8000; 1323 1324 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0)) 1325 return 0; 1326 1327 return dco_freq / (p0 * p1 * p2 * 5); 1328 } 1329 1330 int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv, 1331 struct intel_dpll_hw_state *pll_state) 1332 { 1333 u32 p0, p1, p2, dco_freq, ref_clock; 1334 1335 p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK; 1336 p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK; 1337 1338 if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1)) 1339 p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >> 1340 DPLL_CFGCR1_QDIV_RATIO_SHIFT; 1341 else 1342 p1 = 1; 1343 1344 1345 switch (p0) { 1346 case DPLL_CFGCR1_PDIV_2: 1347 p0 = 2; 1348 break; 1349 case DPLL_CFGCR1_PDIV_3: 1350 p0 = 3; 1351 break; 1352 case DPLL_CFGCR1_PDIV_5: 1353 p0 = 5; 1354 break; 1355 case DPLL_CFGCR1_PDIV_7: 1356 p0 = 7; 1357 break; 1358 } 1359 1360 switch (p2) { 1361 case DPLL_CFGCR1_KDIV_1: 1362 p2 = 1; 1363 break; 1364 case DPLL_CFGCR1_KDIV_2: 1365 p2 = 2; 1366 break; 1367 case DPLL_CFGCR1_KDIV_3: 1368 p2 = 3; 1369 break; 1370 } 1371 1372 ref_clock = cnl_hdmi_pll_ref_clock(dev_priv); 1373 1374 dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) 1375 * ref_clock; 1376 1377 dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >> 1378 DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000; 1379 1380 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0)) 1381 return 0; 1382 1383 return dco_freq / (p0 * p1 * p2 * 5); 1384 } 1385 1386 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 1387 enum port port) 1388 { 1389 u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 1390 1391 switch (val) { 1392 case DDI_CLK_SEL_NONE: 1393 return 0; 1394 case DDI_CLK_SEL_TBT_162: 1395 return 162000; 1396 case DDI_CLK_SEL_TBT_270: 1397 return 270000; 1398 case DDI_CLK_SEL_TBT_540: 1399 return 540000; 1400 case DDI_CLK_SEL_TBT_810: 1401 return 810000; 1402 default: 1403 MISSING_CASE(val); 1404 return 0; 1405 } 1406 } 1407 1408 static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv, 1409 const struct intel_dpll_hw_state *pll_state) 1410 { 1411 u32 m1, m2_int, m2_frac, div1, div2, ref_clock; 1412 u64 tmp; 1413 1414 ref_clock = dev_priv->cdclk.hw.ref; 1415 1416 m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK; 1417 m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK; 1418 m2_frac = (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ? 1419 (pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >> 1420 MG_PLL_DIV0_FBDIV_FRAC_SHIFT : 0; 1421 1422 switch (pll_state->mg_clktop2_hsclkctl & 1423 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) { 1424 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2: 1425 div1 = 2; 1426 break; 1427 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3: 1428 div1 = 3; 1429 break; 1430 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5: 1431 div1 = 5; 1432 break; 1433 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7: 1434 div1 = 7; 1435 break; 1436 default: 1437 MISSING_CASE(pll_state->mg_clktop2_hsclkctl); 1438 return 0; 1439 } 1440 1441 div2 = (pll_state->mg_clktop2_hsclkctl & 1442 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >> 1443 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT; 1444 1445 /* div2 value of 0 is same as 1 means no div */ 1446 if (div2 == 0) 1447 div2 = 1; 1448 1449 /* 1450 * Adjust the original formula to delay the division by 2^22 in order to 1451 * minimize possible rounding errors. 1452 */ 1453 tmp = (u64)m1 * m2_int * ref_clock + 1454 (((u64)m1 * m2_frac * ref_clock) >> 22); 1455 tmp = div_u64(tmp, 5 * div1 * div2); 1456 1457 return tmp; 1458 } 1459 1460 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 1461 { 1462 int dotclock; 1463 1464 if (pipe_config->has_pch_encoder) 1465 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1466 &pipe_config->fdi_m_n); 1467 else if (intel_crtc_has_dp_encoder(pipe_config)) 1468 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1469 &pipe_config->dp_m_n); 1470 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36) 1471 dotclock = pipe_config->port_clock * 2 / 3; 1472 else 1473 dotclock = pipe_config->port_clock; 1474 1475 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 1476 !intel_crtc_has_dp_encoder(pipe_config)) 1477 dotclock *= 2; 1478 1479 if (pipe_config->pixel_multiplier) 1480 dotclock /= pipe_config->pixel_multiplier; 1481 1482 pipe_config->base.adjusted_mode.crtc_clock = dotclock; 1483 } 1484 1485 static void icl_ddi_clock_get(struct intel_encoder *encoder, 1486 struct intel_crtc_state *pipe_config) 1487 { 1488 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1489 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state; 1490 enum port port = encoder->port; 1491 enum phy phy = intel_port_to_phy(dev_priv, port); 1492 int link_clock; 1493 1494 if (intel_phy_is_combo(dev_priv, phy)) { 1495 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state); 1496 } else { 1497 enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv, 1498 pipe_config->shared_dpll); 1499 1500 if (pll_id == DPLL_ID_ICL_TBTPLL) 1501 link_clock = icl_calc_tbt_pll_link(dev_priv, port); 1502 else 1503 link_clock = icl_calc_mg_pll_link(dev_priv, pll_state); 1504 } 1505 1506 pipe_config->port_clock = link_clock; 1507 1508 ddi_dotclock_get(pipe_config); 1509 } 1510 1511 static void cnl_ddi_clock_get(struct intel_encoder *encoder, 1512 struct intel_crtc_state *pipe_config) 1513 { 1514 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1515 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state; 1516 int link_clock; 1517 1518 if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) { 1519 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state); 1520 } else { 1521 link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK; 1522 1523 switch (link_clock) { 1524 case DPLL_CFGCR0_LINK_RATE_810: 1525 link_clock = 81000; 1526 break; 1527 case DPLL_CFGCR0_LINK_RATE_1080: 1528 link_clock = 108000; 1529 break; 1530 case DPLL_CFGCR0_LINK_RATE_1350: 1531 link_clock = 135000; 1532 break; 1533 case DPLL_CFGCR0_LINK_RATE_1620: 1534 link_clock = 162000; 1535 break; 1536 case DPLL_CFGCR0_LINK_RATE_2160: 1537 link_clock = 216000; 1538 break; 1539 case DPLL_CFGCR0_LINK_RATE_2700: 1540 link_clock = 270000; 1541 break; 1542 case DPLL_CFGCR0_LINK_RATE_3240: 1543 link_clock = 324000; 1544 break; 1545 case DPLL_CFGCR0_LINK_RATE_4050: 1546 link_clock = 405000; 1547 break; 1548 default: 1549 WARN(1, "Unsupported link rate\n"); 1550 break; 1551 } 1552 link_clock *= 2; 1553 } 1554 1555 pipe_config->port_clock = link_clock; 1556 1557 ddi_dotclock_get(pipe_config); 1558 } 1559 1560 static void skl_ddi_clock_get(struct intel_encoder *encoder, 1561 struct intel_crtc_state *pipe_config) 1562 { 1563 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state; 1564 int link_clock; 1565 1566 /* 1567 * ctrl1 register is already shifted for each pll, just use 0 to get 1568 * the internal shift for each field 1569 */ 1570 if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) { 1571 link_clock = skl_calc_wrpll_link(pll_state); 1572 } else { 1573 link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0); 1574 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(0); 1575 1576 switch (link_clock) { 1577 case DPLL_CTRL1_LINK_RATE_810: 1578 link_clock = 81000; 1579 break; 1580 case DPLL_CTRL1_LINK_RATE_1080: 1581 link_clock = 108000; 1582 break; 1583 case DPLL_CTRL1_LINK_RATE_1350: 1584 link_clock = 135000; 1585 break; 1586 case DPLL_CTRL1_LINK_RATE_1620: 1587 link_clock = 162000; 1588 break; 1589 case DPLL_CTRL1_LINK_RATE_2160: 1590 link_clock = 216000; 1591 break; 1592 case DPLL_CTRL1_LINK_RATE_2700: 1593 link_clock = 270000; 1594 break; 1595 default: 1596 WARN(1, "Unsupported link rate\n"); 1597 break; 1598 } 1599 link_clock *= 2; 1600 } 1601 1602 pipe_config->port_clock = link_clock; 1603 1604 ddi_dotclock_get(pipe_config); 1605 } 1606 1607 static void hsw_ddi_clock_get(struct intel_encoder *encoder, 1608 struct intel_crtc_state *pipe_config) 1609 { 1610 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1611 int link_clock = 0; 1612 u32 val, pll; 1613 1614 val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll); 1615 switch (val & PORT_CLK_SEL_MASK) { 1616 case PORT_CLK_SEL_LCPLL_810: 1617 link_clock = 81000; 1618 break; 1619 case PORT_CLK_SEL_LCPLL_1350: 1620 link_clock = 135000; 1621 break; 1622 case PORT_CLK_SEL_LCPLL_2700: 1623 link_clock = 270000; 1624 break; 1625 case PORT_CLK_SEL_WRPLL1: 1626 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0)); 1627 break; 1628 case PORT_CLK_SEL_WRPLL2: 1629 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1)); 1630 break; 1631 case PORT_CLK_SEL_SPLL: 1632 pll = I915_READ(SPLL_CTL) & SPLL_FREQ_MASK; 1633 if (pll == SPLL_FREQ_810MHz) 1634 link_clock = 81000; 1635 else if (pll == SPLL_FREQ_1350MHz) 1636 link_clock = 135000; 1637 else if (pll == SPLL_FREQ_2700MHz) 1638 link_clock = 270000; 1639 else { 1640 WARN(1, "bad spll freq\n"); 1641 return; 1642 } 1643 break; 1644 default: 1645 WARN(1, "bad port clock sel\n"); 1646 return; 1647 } 1648 1649 pipe_config->port_clock = link_clock * 2; 1650 1651 ddi_dotclock_get(pipe_config); 1652 } 1653 1654 static int bxt_calc_pll_link(const struct intel_dpll_hw_state *pll_state) 1655 { 1656 struct dpll clock; 1657 1658 clock.m1 = 2; 1659 clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22; 1660 if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE) 1661 clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK; 1662 clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT; 1663 clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT; 1664 clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT; 1665 1666 return chv_calc_dpll_params(100000, &clock); 1667 } 1668 1669 static void bxt_ddi_clock_get(struct intel_encoder *encoder, 1670 struct intel_crtc_state *pipe_config) 1671 { 1672 pipe_config->port_clock = 1673 bxt_calc_pll_link(&pipe_config->dpll_hw_state); 1674 1675 ddi_dotclock_get(pipe_config); 1676 } 1677 1678 static void intel_ddi_clock_get(struct intel_encoder *encoder, 1679 struct intel_crtc_state *pipe_config) 1680 { 1681 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1682 1683 if (INTEL_GEN(dev_priv) >= 11) 1684 icl_ddi_clock_get(encoder, pipe_config); 1685 else if (IS_CANNONLAKE(dev_priv)) 1686 cnl_ddi_clock_get(encoder, pipe_config); 1687 else if (IS_GEN9_LP(dev_priv)) 1688 bxt_ddi_clock_get(encoder, pipe_config); 1689 else if (IS_GEN9_BC(dev_priv)) 1690 skl_ddi_clock_get(encoder, pipe_config); 1691 else if (INTEL_GEN(dev_priv) <= 8) 1692 hsw_ddi_clock_get(encoder, pipe_config); 1693 } 1694 1695 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state) 1696 { 1697 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 1698 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1699 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1700 u32 temp; 1701 1702 if (!intel_crtc_has_dp_encoder(crtc_state)) 1703 return; 1704 1705 WARN_ON(transcoder_is_dsi(cpu_transcoder)); 1706 1707 temp = TRANS_MSA_SYNC_CLK; 1708 1709 if (crtc_state->limited_color_range) 1710 temp |= TRANS_MSA_CEA_RANGE; 1711 1712 switch (crtc_state->pipe_bpp) { 1713 case 18: 1714 temp |= TRANS_MSA_6_BPC; 1715 break; 1716 case 24: 1717 temp |= TRANS_MSA_8_BPC; 1718 break; 1719 case 30: 1720 temp |= TRANS_MSA_10_BPC; 1721 break; 1722 case 36: 1723 temp |= TRANS_MSA_12_BPC; 1724 break; 1725 default: 1726 MISSING_CASE(crtc_state->pipe_bpp); 1727 break; 1728 } 1729 1730 /* 1731 * As per DP 1.2 spec section 2.3.4.3 while sending 1732 * YCBCR 444 signals we should program MSA MISC1/0 fields with 1733 * colorspace information. The output colorspace encoding is BT601. 1734 */ 1735 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 1736 temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR; 1737 /* 1738 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 1739 * of Color Encoding Format and Content Color Gamut] while sending 1740 * YCBCR 420 signals we should program MSA MISC1 fields which 1741 * indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 1742 */ 1743 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1744 temp |= TRANS_MSA_USE_VSC_SDP; 1745 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); 1746 } 1747 1748 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state, 1749 bool state) 1750 { 1751 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 1752 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1753 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1754 u32 temp; 1755 1756 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1757 if (state == true) 1758 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; 1759 else 1760 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC; 1761 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 1762 } 1763 1764 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state) 1765 { 1766 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 1767 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc); 1768 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1769 enum pipe pipe = crtc->pipe; 1770 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1771 enum port port = encoder->port; 1772 u32 temp; 1773 1774 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 1775 temp = TRANS_DDI_FUNC_ENABLE; 1776 if (INTEL_GEN(dev_priv) >= 12) 1777 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 1778 else 1779 temp |= TRANS_DDI_SELECT_PORT(port); 1780 1781 switch (crtc_state->pipe_bpp) { 1782 case 18: 1783 temp |= TRANS_DDI_BPC_6; 1784 break; 1785 case 24: 1786 temp |= TRANS_DDI_BPC_8; 1787 break; 1788 case 30: 1789 temp |= TRANS_DDI_BPC_10; 1790 break; 1791 case 36: 1792 temp |= TRANS_DDI_BPC_12; 1793 break; 1794 default: 1795 BUG(); 1796 } 1797 1798 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 1799 temp |= TRANS_DDI_PVSYNC; 1800 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 1801 temp |= TRANS_DDI_PHSYNC; 1802 1803 if (cpu_transcoder == TRANSCODER_EDP) { 1804 switch (pipe) { 1805 case PIPE_A: 1806 /* On Haswell, can only use the always-on power well for 1807 * eDP when not using the panel fitter, and when not 1808 * using motion blur mitigation (which we don't 1809 * support). */ 1810 if (crtc_state->pch_pfit.force_thru) 1811 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 1812 else 1813 temp |= TRANS_DDI_EDP_INPUT_A_ON; 1814 break; 1815 case PIPE_B: 1816 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 1817 break; 1818 case PIPE_C: 1819 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 1820 break; 1821 default: 1822 BUG(); 1823 break; 1824 } 1825 } 1826 1827 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1828 if (crtc_state->has_hdmi_sink) 1829 temp |= TRANS_DDI_MODE_SELECT_HDMI; 1830 else 1831 temp |= TRANS_DDI_MODE_SELECT_DVI; 1832 1833 if (crtc_state->hdmi_scrambling) 1834 temp |= TRANS_DDI_HDMI_SCRAMBLING; 1835 if (crtc_state->hdmi_high_tmds_clock_ratio) 1836 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 1837 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 1838 temp |= TRANS_DDI_MODE_SELECT_FDI; 1839 temp |= (crtc_state->fdi_lanes - 1) << 1; 1840 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 1841 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 1842 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 1843 } else { 1844 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 1845 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 1846 } 1847 1848 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 1849 } 1850 1851 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 1852 { 1853 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 1854 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1855 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1856 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); 1857 u32 val = I915_READ(reg); 1858 1859 if (INTEL_GEN(dev_priv) >= 12) { 1860 val &= ~(TRANS_DDI_FUNC_ENABLE | TGL_TRANS_DDI_PORT_MASK | 1861 TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 1862 } else { 1863 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | 1864 TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 1865 } 1866 I915_WRITE(reg, val); 1867 1868 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME && 1869 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1870 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n"); 1871 /* Quirk time at 100ms for reliable operation */ 1872 msleep(100); 1873 } 1874 } 1875 1876 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder, 1877 bool enable) 1878 { 1879 struct drm_device *dev = intel_encoder->base.dev; 1880 struct drm_i915_private *dev_priv = to_i915(dev); 1881 intel_wakeref_t wakeref; 1882 enum pipe pipe = 0; 1883 int ret = 0; 1884 u32 tmp; 1885 1886 wakeref = intel_display_power_get_if_enabled(dev_priv, 1887 intel_encoder->power_domain); 1888 if (WARN_ON(!wakeref)) 1889 return -ENXIO; 1890 1891 if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) { 1892 ret = -EIO; 1893 goto out; 1894 } 1895 1896 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe)); 1897 if (enable) 1898 tmp |= TRANS_DDI_HDCP_SIGNALLING; 1899 else 1900 tmp &= ~TRANS_DDI_HDCP_SIGNALLING; 1901 I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp); 1902 out: 1903 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 1904 return ret; 1905 } 1906 1907 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 1908 { 1909 struct drm_device *dev = intel_connector->base.dev; 1910 struct drm_i915_private *dev_priv = to_i915(dev); 1911 struct intel_encoder *encoder = intel_connector->encoder; 1912 int type = intel_connector->base.connector_type; 1913 enum port port = encoder->port; 1914 enum transcoder cpu_transcoder; 1915 intel_wakeref_t wakeref; 1916 enum pipe pipe = 0; 1917 u32 tmp; 1918 bool ret; 1919 1920 wakeref = intel_display_power_get_if_enabled(dev_priv, 1921 encoder->power_domain); 1922 if (!wakeref) 1923 return false; 1924 1925 if (!encoder->get_hw_state(encoder, &pipe)) { 1926 ret = false; 1927 goto out; 1928 } 1929 1930 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) 1931 cpu_transcoder = TRANSCODER_EDP; 1932 else 1933 cpu_transcoder = (enum transcoder) pipe; 1934 1935 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1936 1937 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 1938 case TRANS_DDI_MODE_SELECT_HDMI: 1939 case TRANS_DDI_MODE_SELECT_DVI: 1940 ret = type == DRM_MODE_CONNECTOR_HDMIA; 1941 break; 1942 1943 case TRANS_DDI_MODE_SELECT_DP_SST: 1944 ret = type == DRM_MODE_CONNECTOR_eDP || 1945 type == DRM_MODE_CONNECTOR_DisplayPort; 1946 break; 1947 1948 case TRANS_DDI_MODE_SELECT_DP_MST: 1949 /* if the transcoder is in MST state then 1950 * connector isn't connected */ 1951 ret = false; 1952 break; 1953 1954 case TRANS_DDI_MODE_SELECT_FDI: 1955 ret = type == DRM_MODE_CONNECTOR_VGA; 1956 break; 1957 1958 default: 1959 ret = false; 1960 break; 1961 } 1962 1963 out: 1964 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1965 1966 return ret; 1967 } 1968 1969 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 1970 u8 *pipe_mask, bool *is_dp_mst) 1971 { 1972 struct drm_device *dev = encoder->base.dev; 1973 struct drm_i915_private *dev_priv = to_i915(dev); 1974 enum port port = encoder->port; 1975 intel_wakeref_t wakeref; 1976 enum pipe p; 1977 u32 tmp; 1978 u8 mst_pipe_mask; 1979 1980 *pipe_mask = 0; 1981 *is_dp_mst = false; 1982 1983 wakeref = intel_display_power_get_if_enabled(dev_priv, 1984 encoder->power_domain); 1985 if (!wakeref) 1986 return; 1987 1988 tmp = I915_READ(DDI_BUF_CTL(port)); 1989 if (!(tmp & DDI_BUF_CTL_ENABLE)) 1990 goto out; 1991 1992 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) { 1993 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 1994 1995 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 1996 default: 1997 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 1998 /* fallthrough */ 1999 case TRANS_DDI_EDP_INPUT_A_ON: 2000 case TRANS_DDI_EDP_INPUT_A_ONOFF: 2001 *pipe_mask = BIT(PIPE_A); 2002 break; 2003 case TRANS_DDI_EDP_INPUT_B_ONOFF: 2004 *pipe_mask = BIT(PIPE_B); 2005 break; 2006 case TRANS_DDI_EDP_INPUT_C_ONOFF: 2007 *pipe_mask = BIT(PIPE_C); 2008 break; 2009 } 2010 2011 goto out; 2012 } 2013 2014 mst_pipe_mask = 0; 2015 for_each_pipe(dev_priv, p) { 2016 enum transcoder cpu_transcoder = (enum transcoder)p; 2017 unsigned int port_mask, ddi_select; 2018 2019 if (INTEL_GEN(dev_priv) >= 12) { 2020 port_mask = TGL_TRANS_DDI_PORT_MASK; 2021 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 2022 } else { 2023 port_mask = TRANS_DDI_PORT_MASK; 2024 ddi_select = TRANS_DDI_SELECT_PORT(port); 2025 } 2026 2027 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 2028 2029 if ((tmp & port_mask) != ddi_select) 2030 continue; 2031 2032 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == 2033 TRANS_DDI_MODE_SELECT_DP_MST) 2034 mst_pipe_mask |= BIT(p); 2035 2036 *pipe_mask |= BIT(p); 2037 } 2038 2039 if (!*pipe_mask) 2040 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", 2041 port_name(port)); 2042 2043 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 2044 DRM_DEBUG_KMS("Multiple pipes for non DP-MST port %c (pipe_mask %02x)\n", 2045 port_name(port), *pipe_mask); 2046 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 2047 } 2048 2049 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 2050 DRM_DEBUG_KMS("Conflicting MST and non-MST encoders for port %c (pipe_mask %02x mst_pipe_mask %02x)\n", 2051 port_name(port), *pipe_mask, mst_pipe_mask); 2052 else 2053 *is_dp_mst = mst_pipe_mask; 2054 2055 out: 2056 if (*pipe_mask && IS_GEN9_LP(dev_priv)) { 2057 tmp = I915_READ(BXT_PHY_CTL(port)); 2058 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 2059 BXT_PHY_LANE_POWERDOWN_ACK | 2060 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 2061 DRM_ERROR("Port %c enabled but PHY powered down? " 2062 "(PHY_CTL %08x)\n", port_name(port), tmp); 2063 } 2064 2065 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 2066 } 2067 2068 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 2069 enum pipe *pipe) 2070 { 2071 u8 pipe_mask; 2072 bool is_mst; 2073 2074 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2075 2076 if (is_mst || !pipe_mask) 2077 return false; 2078 2079 *pipe = ffs(pipe_mask) - 1; 2080 2081 return true; 2082 } 2083 2084 static inline enum intel_display_power_domain 2085 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port) 2086 { 2087 /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with 2088 * DC states enabled at the same time, while for driver initiated AUX 2089 * transfers we need the same AUX IOs to be powered but with DC states 2090 * disabled. Accordingly use the AUX power domain here which leaves DC 2091 * states enabled. 2092 * However, for non-A AUX ports the corresponding non-EDP transcoders 2093 * would have already enabled power well 2 and DC_OFF. This means we can 2094 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a 2095 * specific AUX_IO reference without powering up any extra wells. 2096 * Note that PSR is enabled only on Port A even though this function 2097 * returns the correct domain for other ports too. 2098 */ 2099 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A : 2100 intel_aux_power_domain(dig_port); 2101 } 2102 2103 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 2104 struct intel_crtc_state *crtc_state) 2105 { 2106 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2107 struct intel_digital_port *dig_port; 2108 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2109 2110 /* 2111 * TODO: Add support for MST encoders. Atm, the following should never 2112 * happen since fake-MST encoders don't set their get_power_domains() 2113 * hook. 2114 */ 2115 if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 2116 return; 2117 2118 dig_port = enc_to_dig_port(&encoder->base); 2119 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); 2120 2121 /* 2122 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC 2123 * ports. 2124 */ 2125 if (intel_crtc_has_dp_encoder(crtc_state) || 2126 intel_phy_is_tc(dev_priv, phy)) 2127 intel_display_power_get(dev_priv, 2128 intel_ddi_main_link_aux_domain(dig_port)); 2129 2130 /* 2131 * VDSC power is needed when DSC is enabled 2132 */ 2133 if (crtc_state->dsc_params.compression_enable) 2134 intel_display_power_get(dev_priv, 2135 intel_dsc_power_domain(crtc_state)); 2136 } 2137 2138 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state) 2139 { 2140 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 2141 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2142 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc); 2143 enum port port = encoder->port; 2144 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2145 2146 if (cpu_transcoder != TRANSCODER_EDP) { 2147 if (INTEL_GEN(dev_priv) >= 12) 2148 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 2149 TGL_TRANS_CLK_SEL_PORT(port)); 2150 else 2151 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 2152 TRANS_CLK_SEL_PORT(port)); 2153 } 2154 } 2155 2156 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state) 2157 { 2158 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); 2159 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2160 2161 if (cpu_transcoder != TRANSCODER_EDP) { 2162 if (INTEL_GEN(dev_priv) >= 12) 2163 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 2164 TGL_TRANS_CLK_SEL_DISABLED); 2165 else 2166 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 2167 TRANS_CLK_SEL_DISABLED); 2168 } 2169 } 2170 2171 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 2172 enum port port, u8 iboost) 2173 { 2174 u32 tmp; 2175 2176 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0); 2177 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 2178 if (iboost) 2179 tmp |= iboost << BALANCE_LEG_SHIFT(port); 2180 else 2181 tmp |= BALANCE_LEG_DISABLE(port); 2182 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp); 2183 } 2184 2185 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 2186 int level, enum intel_output_type type) 2187 { 2188 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); 2189 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2190 enum port port = encoder->port; 2191 u8 iboost; 2192 2193 if (type == INTEL_OUTPUT_HDMI) 2194 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level; 2195 else 2196 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level; 2197 2198 if (iboost == 0) { 2199 const struct ddi_buf_trans *ddi_translations; 2200 int n_entries; 2201 2202 if (type == INTEL_OUTPUT_HDMI) 2203 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 2204 else if (type == INTEL_OUTPUT_EDP) 2205 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries); 2206 else 2207 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries); 2208 2209 if (WARN_ON_ONCE(!ddi_translations)) 2210 return; 2211 if (WARN_ON_ONCE(level >= n_entries)) 2212 level = n_entries - 1; 2213 2214 iboost = ddi_translations[level].i_boost; 2215 } 2216 2217 /* Make sure that the requested I_boost is valid */ 2218 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 2219 DRM_ERROR("Invalid I_boost value %u\n", iboost); 2220 return; 2221 } 2222 2223 _skl_ddi_set_iboost(dev_priv, port, iboost); 2224 2225 if (port == PORT_A && intel_dig_port->max_lanes == 4) 2226 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 2227 } 2228 2229 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, 2230 int level, enum intel_output_type type) 2231 { 2232 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2233 const struct bxt_ddi_buf_trans *ddi_translations; 2234 enum port port = encoder->port; 2235 int n_entries; 2236 2237 if (type == INTEL_OUTPUT_HDMI) 2238 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries); 2239 else if (type == INTEL_OUTPUT_EDP) 2240 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries); 2241 else 2242 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries); 2243 2244 if (WARN_ON_ONCE(!ddi_translations)) 2245 return; 2246 if (WARN_ON_ONCE(level >= n_entries)) 2247 level = n_entries - 1; 2248 2249 bxt_ddi_phy_set_signal_level(dev_priv, port, 2250 ddi_translations[level].margin, 2251 ddi_translations[level].scale, 2252 ddi_translations[level].enable, 2253 ddi_translations[level].deemphasis); 2254 } 2255 2256 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder) 2257 { 2258 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2259 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2260 enum port port = encoder->port; 2261 enum phy phy = intel_port_to_phy(dev_priv, port); 2262 int n_entries; 2263 2264 if (INTEL_GEN(dev_priv) >= 11) { 2265 if (intel_phy_is_combo(dev_priv, phy)) 2266 icl_get_combo_buf_trans(dev_priv, encoder->type, 2267 intel_dp->link_rate, &n_entries); 2268 else 2269 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations); 2270 } else if (IS_CANNONLAKE(dev_priv)) { 2271 if (encoder->type == INTEL_OUTPUT_EDP) 2272 cnl_get_buf_trans_edp(dev_priv, &n_entries); 2273 else 2274 cnl_get_buf_trans_dp(dev_priv, &n_entries); 2275 } else if (IS_GEN9_LP(dev_priv)) { 2276 if (encoder->type == INTEL_OUTPUT_EDP) 2277 bxt_get_buf_trans_edp(dev_priv, &n_entries); 2278 else 2279 bxt_get_buf_trans_dp(dev_priv, &n_entries); 2280 } else { 2281 if (encoder->type == INTEL_OUTPUT_EDP) 2282 intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries); 2283 else 2284 intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries); 2285 } 2286 2287 if (WARN_ON(n_entries < 1)) 2288 n_entries = 1; 2289 if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 2290 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 2291 2292 return index_to_dp_signal_levels[n_entries - 1] & 2293 DP_TRAIN_VOLTAGE_SWING_MASK; 2294 } 2295 2296 /* 2297 * We assume that the full set of pre-emphasis values can be 2298 * used on all DDI platforms. Should that change we need to 2299 * rethink this code. 2300 */ 2301 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing) 2302 { 2303 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2304 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2305 return DP_TRAIN_PRE_EMPH_LEVEL_3; 2306 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 2307 return DP_TRAIN_PRE_EMPH_LEVEL_2; 2308 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 2309 return DP_TRAIN_PRE_EMPH_LEVEL_1; 2310 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 2311 default: 2312 return DP_TRAIN_PRE_EMPH_LEVEL_0; 2313 } 2314 } 2315 2316 static void cnl_ddi_vswing_program(struct intel_encoder *encoder, 2317 int level, enum intel_output_type type) 2318 { 2319 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2320 const struct cnl_ddi_buf_trans *ddi_translations; 2321 enum port port = encoder->port; 2322 int n_entries, ln; 2323 u32 val; 2324 2325 if (type == INTEL_OUTPUT_HDMI) 2326 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries); 2327 else if (type == INTEL_OUTPUT_EDP) 2328 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries); 2329 else 2330 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries); 2331 2332 if (WARN_ON_ONCE(!ddi_translations)) 2333 return; 2334 if (WARN_ON_ONCE(level >= n_entries)) 2335 level = n_entries - 1; 2336 2337 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */ 2338 val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); 2339 val &= ~SCALING_MODE_SEL_MASK; 2340 val |= SCALING_MODE_SEL(2); 2341 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); 2342 2343 /* Program PORT_TX_DW2 */ 2344 val = I915_READ(CNL_PORT_TX_DW2_LN0(port)); 2345 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 2346 RCOMP_SCALAR_MASK); 2347 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); 2348 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); 2349 /* Rcomp scalar is fixed as 0x98 for every table entry */ 2350 val |= RCOMP_SCALAR(0x98); 2351 I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val); 2352 2353 /* Program PORT_TX_DW4 */ 2354 /* We cannot write to GRP. It would overrite individual loadgen */ 2355 for (ln = 0; ln < 4; ln++) { 2356 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port)); 2357 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 2358 CURSOR_COEFF_MASK); 2359 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); 2360 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); 2361 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); 2362 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val); 2363 } 2364 2365 /* Program PORT_TX_DW5 */ 2366 /* All DW5 values are fixed for every table entry */ 2367 val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); 2368 val &= ~RTERM_SELECT_MASK; 2369 val |= RTERM_SELECT(6); 2370 val |= TAP3_DISABLE; 2371 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); 2372 2373 /* Program PORT_TX_DW7 */ 2374 val = I915_READ(CNL_PORT_TX_DW7_LN0(port)); 2375 val &= ~N_SCALAR_MASK; 2376 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); 2377 I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val); 2378 } 2379 2380 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, 2381 int level, enum intel_output_type type) 2382 { 2383 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2384 enum port port = encoder->port; 2385 int width, rate, ln; 2386 u32 val; 2387 2388 if (type == INTEL_OUTPUT_HDMI) { 2389 width = 4; 2390 rate = 0; /* Rate is always < than 6GHz for HDMI */ 2391 } else { 2392 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2393 2394 width = intel_dp->lane_count; 2395 rate = intel_dp->link_rate; 2396 } 2397 2398 /* 2399 * 1. If port type is eDP or DP, 2400 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 2401 * else clear to 0b. 2402 */ 2403 val = I915_READ(CNL_PORT_PCS_DW1_LN0(port)); 2404 if (type != INTEL_OUTPUT_HDMI) 2405 val |= COMMON_KEEPER_EN; 2406 else 2407 val &= ~COMMON_KEEPER_EN; 2408 I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val); 2409 2410 /* 2. Program loadgen select */ 2411 /* 2412 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes 2413 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2414 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2415 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 2416 */ 2417 for (ln = 0; ln <= 3; ln++) { 2418 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port)); 2419 val &= ~LOADGEN_SELECT; 2420 2421 if ((rate <= 600000 && width == 4 && ln >= 1) || 2422 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { 2423 val |= LOADGEN_SELECT; 2424 } 2425 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val); 2426 } 2427 2428 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 2429 val = I915_READ(CNL_PORT_CL1CM_DW5); 2430 val |= SUS_CLOCK_CONFIG; 2431 I915_WRITE(CNL_PORT_CL1CM_DW5, val); 2432 2433 /* 4. Clear training enable to change swing values */ 2434 val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); 2435 val &= ~TX_TRAINING_EN; 2436 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); 2437 2438 /* 5. Program swing and de-emphasis */ 2439 cnl_ddi_vswing_program(encoder, level, type); 2440 2441 /* 6. Set training enable to trigger update */ 2442 val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); 2443 val |= TX_TRAINING_EN; 2444 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); 2445 } 2446 2447 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, 2448 u32 level, enum phy phy, int type, 2449 int rate) 2450 { 2451 const struct cnl_ddi_buf_trans *ddi_translations = NULL; 2452 u32 n_entries, val; 2453 int ln; 2454 2455 ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate, 2456 &n_entries); 2457 if (!ddi_translations) 2458 return; 2459 2460 if (level >= n_entries) { 2461 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1); 2462 level = n_entries - 1; 2463 } 2464 2465 /* Set PORT_TX_DW5 */ 2466 val = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); 2467 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 2468 TAP2_DISABLE | TAP3_DISABLE); 2469 val |= SCALING_MODE_SEL(0x2); 2470 val |= RTERM_SELECT(0x6); 2471 val |= TAP3_DISABLE; 2472 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val); 2473 2474 /* Program PORT_TX_DW2 */ 2475 val = I915_READ(ICL_PORT_TX_DW2_LN0(phy)); 2476 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 2477 RCOMP_SCALAR_MASK); 2478 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); 2479 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); 2480 /* Program Rcomp scalar for every table entry */ 2481 val |= RCOMP_SCALAR(0x98); 2482 I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), val); 2483 2484 /* Program PORT_TX_DW4 */ 2485 /* We cannot write to GRP. It would overwrite individual loadgen. */ 2486 for (ln = 0; ln <= 3; ln++) { 2487 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy)); 2488 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 2489 CURSOR_COEFF_MASK); 2490 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); 2491 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); 2492 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); 2493 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val); 2494 } 2495 2496 /* Program PORT_TX_DW7 */ 2497 val = I915_READ(ICL_PORT_TX_DW7_LN0(phy)); 2498 val &= ~N_SCALAR_MASK; 2499 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); 2500 I915_WRITE(ICL_PORT_TX_DW7_GRP(phy), val); 2501 } 2502 2503 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 2504 u32 level, 2505 enum intel_output_type type) 2506 { 2507 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2508 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2509 int width = 0; 2510 int rate = 0; 2511 u32 val; 2512 int ln = 0; 2513 2514 if (type == INTEL_OUTPUT_HDMI) { 2515 width = 4; 2516 /* Rate is always < than 6GHz for HDMI */ 2517 } else { 2518 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2519 2520 width = intel_dp->lane_count; 2521 rate = intel_dp->link_rate; 2522 } 2523 2524 /* 2525 * 1. If port type is eDP or DP, 2526 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 2527 * else clear to 0b. 2528 */ 2529 val = I915_READ(ICL_PORT_PCS_DW1_LN0(phy)); 2530 if (type == INTEL_OUTPUT_HDMI) 2531 val &= ~COMMON_KEEPER_EN; 2532 else 2533 val |= COMMON_KEEPER_EN; 2534 I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), val); 2535 2536 /* 2. Program loadgen select */ 2537 /* 2538 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes 2539 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2540 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2541 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 2542 */ 2543 for (ln = 0; ln <= 3; ln++) { 2544 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy)); 2545 val &= ~LOADGEN_SELECT; 2546 2547 if ((rate <= 600000 && width == 4 && ln >= 1) || 2548 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { 2549 val |= LOADGEN_SELECT; 2550 } 2551 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val); 2552 } 2553 2554 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 2555 val = I915_READ(ICL_PORT_CL_DW5(phy)); 2556 val |= SUS_CLOCK_CONFIG; 2557 I915_WRITE(ICL_PORT_CL_DW5(phy), val); 2558 2559 /* 4. Clear training enable to change swing values */ 2560 val = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); 2561 val &= ~TX_TRAINING_EN; 2562 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val); 2563 2564 /* 5. Program swing and de-emphasis */ 2565 icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate); 2566 2567 /* 6. Set training enable to trigger update */ 2568 val = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); 2569 val |= TX_TRAINING_EN; 2570 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val); 2571 } 2572 2573 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 2574 int link_clock, 2575 u32 level) 2576 { 2577 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2578 enum port port = encoder->port; 2579 const struct icl_mg_phy_ddi_buf_trans *ddi_translations; 2580 u32 n_entries, val; 2581 int ln; 2582 2583 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations); 2584 ddi_translations = icl_mg_phy_ddi_translations; 2585 /* The table does not have values for level 3 and level 9. */ 2586 if (level >= n_entries || level == 3 || level == 9) { 2587 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", 2588 level, n_entries - 2); 2589 level = n_entries - 2; 2590 } 2591 2592 /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */ 2593 for (ln = 0; ln < 2; ln++) { 2594 val = I915_READ(MG_TX1_LINK_PARAMS(ln, port)); 2595 val &= ~CRI_USE_FS32; 2596 I915_WRITE(MG_TX1_LINK_PARAMS(ln, port), val); 2597 2598 val = I915_READ(MG_TX2_LINK_PARAMS(ln, port)); 2599 val &= ~CRI_USE_FS32; 2600 I915_WRITE(MG_TX2_LINK_PARAMS(ln, port), val); 2601 } 2602 2603 /* Program MG_TX_SWINGCTRL with values from vswing table */ 2604 for (ln = 0; ln < 2; ln++) { 2605 val = I915_READ(MG_TX1_SWINGCTRL(ln, port)); 2606 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; 2607 val |= CRI_TXDEEMPH_OVERRIDE_17_12( 2608 ddi_translations[level].cri_txdeemph_override_17_12); 2609 I915_WRITE(MG_TX1_SWINGCTRL(ln, port), val); 2610 2611 val = I915_READ(MG_TX2_SWINGCTRL(ln, port)); 2612 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; 2613 val |= CRI_TXDEEMPH_OVERRIDE_17_12( 2614 ddi_translations[level].cri_txdeemph_override_17_12); 2615 I915_WRITE(MG_TX2_SWINGCTRL(ln, port), val); 2616 } 2617 2618 /* Program MG_TX_DRVCTRL with values from vswing table */ 2619 for (ln = 0; ln < 2; ln++) { 2620 val = I915_READ(MG_TX1_DRVCTRL(ln, port)); 2621 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 2622 CRI_TXDEEMPH_OVERRIDE_5_0_MASK); 2623 val |= CRI_TXDEEMPH_OVERRIDE_5_0( 2624 ddi_translations[level].cri_txdeemph_override_5_0) | 2625 CRI_TXDEEMPH_OVERRIDE_11_6( 2626 ddi_translations[level].cri_txdeemph_override_11_6) | 2627 CRI_TXDEEMPH_OVERRIDE_EN; 2628 I915_WRITE(MG_TX1_DRVCTRL(ln, port), val); 2629 2630 val = I915_READ(MG_TX2_DRVCTRL(ln, port)); 2631 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 2632 CRI_TXDEEMPH_OVERRIDE_5_0_MASK); 2633 val |= CRI_TXDEEMPH_OVERRIDE_5_0( 2634 ddi_translations[level].cri_txdeemph_override_5_0) | 2635 CRI_TXDEEMPH_OVERRIDE_11_6( 2636 ddi_translations[level].cri_txdeemph_override_11_6) | 2637 CRI_TXDEEMPH_OVERRIDE_EN; 2638 I915_WRITE(MG_TX2_DRVCTRL(ln, port), val); 2639 2640 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 2641 } 2642 2643 /* 2644 * Program MG_CLKHUB<LN, port being used> with value from frequency table 2645 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 2646 * values from table for which TX1 and TX2 enabled. 2647 */ 2648 for (ln = 0; ln < 2; ln++) { 2649 val = I915_READ(MG_CLKHUB(ln, port)); 2650 if (link_clock < 300000) 2651 val |= CFG_LOW_RATE_LKREN_EN; 2652 else 2653 val &= ~CFG_LOW_RATE_LKREN_EN; 2654 I915_WRITE(MG_CLKHUB(ln, port), val); 2655 } 2656 2657 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 2658 for (ln = 0; ln < 2; ln++) { 2659 val = I915_READ(MG_TX1_DCC(ln, port)); 2660 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; 2661 if (link_clock <= 500000) { 2662 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; 2663 } else { 2664 val |= CFG_AMI_CK_DIV_OVERRIDE_EN | 2665 CFG_AMI_CK_DIV_OVERRIDE_VAL(1); 2666 } 2667 I915_WRITE(MG_TX1_DCC(ln, port), val); 2668 2669 val = I915_READ(MG_TX2_DCC(ln, port)); 2670 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; 2671 if (link_clock <= 500000) { 2672 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; 2673 } else { 2674 val |= CFG_AMI_CK_DIV_OVERRIDE_EN | 2675 CFG_AMI_CK_DIV_OVERRIDE_VAL(1); 2676 } 2677 I915_WRITE(MG_TX2_DCC(ln, port), val); 2678 } 2679 2680 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 2681 for (ln = 0; ln < 2; ln++) { 2682 val = I915_READ(MG_TX1_PISO_READLOAD(ln, port)); 2683 val |= CRI_CALCINIT; 2684 I915_WRITE(MG_TX1_PISO_READLOAD(ln, port), val); 2685 2686 val = I915_READ(MG_TX2_PISO_READLOAD(ln, port)); 2687 val |= CRI_CALCINIT; 2688 I915_WRITE(MG_TX2_PISO_READLOAD(ln, port), val); 2689 } 2690 } 2691 2692 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder, 2693 int link_clock, 2694 u32 level, 2695 enum intel_output_type type) 2696 { 2697 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2698 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2699 2700 if (intel_phy_is_combo(dev_priv, phy)) 2701 icl_combo_phy_ddi_vswing_sequence(encoder, level, type); 2702 else 2703 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level); 2704 } 2705 2706 static u32 translate_signal_level(int signal_levels) 2707 { 2708 int i; 2709 2710 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 2711 if (index_to_dp_signal_levels[i] == signal_levels) 2712 return i; 2713 } 2714 2715 WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 2716 signal_levels); 2717 2718 return 0; 2719 } 2720 2721 static u32 intel_ddi_dp_level(struct intel_dp *intel_dp) 2722 { 2723 u8 train_set = intel_dp->train_set[0]; 2724 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2725 DP_TRAIN_PRE_EMPHASIS_MASK); 2726 2727 return translate_signal_level(signal_levels); 2728 } 2729 2730 u32 bxt_signal_levels(struct intel_dp *intel_dp) 2731 { 2732 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2733 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); 2734 struct intel_encoder *encoder = &dport->base; 2735 int level = intel_ddi_dp_level(intel_dp); 2736 2737 if (INTEL_GEN(dev_priv) >= 11) 2738 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate, 2739 level, encoder->type); 2740 else if (IS_CANNONLAKE(dev_priv)) 2741 cnl_ddi_vswing_sequence(encoder, level, encoder->type); 2742 else 2743 bxt_ddi_vswing_sequence(encoder, level, encoder->type); 2744 2745 return 0; 2746 } 2747 2748 u32 ddi_signal_levels(struct intel_dp *intel_dp) 2749 { 2750 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2751 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); 2752 struct intel_encoder *encoder = &dport->base; 2753 int level = intel_ddi_dp_level(intel_dp); 2754 2755 if (IS_GEN9_BC(dev_priv)) 2756 skl_ddi_set_iboost(encoder, level, encoder->type); 2757 2758 return DDI_BUF_TRANS_SELECT(level); 2759 } 2760 2761 static inline 2762 u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv, 2763 enum phy phy) 2764 { 2765 if (intel_phy_is_combo(dev_priv, phy)) { 2766 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 2767 } else if (intel_phy_is_tc(dev_priv, phy)) { 2768 enum tc_port tc_port = intel_port_to_tc(dev_priv, 2769 (enum port)phy); 2770 2771 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port); 2772 } 2773 2774 return 0; 2775 } 2776 2777 static void icl_map_plls_to_ports(struct intel_encoder *encoder, 2778 const struct intel_crtc_state *crtc_state) 2779 { 2780 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2781 struct intel_shared_dpll *pll = crtc_state->shared_dpll; 2782 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2783 u32 val; 2784 2785 mutex_lock(&dev_priv->dpll_lock); 2786 2787 val = I915_READ(ICL_DPCLKA_CFGCR0); 2788 WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0); 2789 2790 if (intel_phy_is_combo(dev_priv, phy)) { 2791 /* 2792 * Even though this register references DDIs, note that we 2793 * want to pass the PHY rather than the port (DDI). For 2794 * ICL, port=phy in all cases so it doesn't matter, but for 2795 * EHL the bspec notes the following: 2796 * 2797 * "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA 2798 * Clock Select chooses the PLL for both DDIA and DDID and 2799 * drives port A in all cases." 2800 */ 2801 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 2802 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 2803 I915_WRITE(ICL_DPCLKA_CFGCR0, val); 2804 POSTING_READ(ICL_DPCLKA_CFGCR0); 2805 } 2806 2807 val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 2808 I915_WRITE(ICL_DPCLKA_CFGCR0, val); 2809 2810 mutex_unlock(&dev_priv->dpll_lock); 2811 } 2812 2813 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder) 2814 { 2815 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2816 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2817 u32 val; 2818 2819 mutex_lock(&dev_priv->dpll_lock); 2820 2821 val = I915_READ(ICL_DPCLKA_CFGCR0); 2822 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 2823 I915_WRITE(ICL_DPCLKA_CFGCR0, val); 2824 2825 mutex_unlock(&dev_priv->dpll_lock); 2826 } 2827 2828 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2829 { 2830 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2831 u32 val; 2832 enum port port; 2833 u32 port_mask; 2834 bool ddi_clk_needed; 2835 2836 /* 2837 * In case of DP MST, we sanitize the primary encoder only, not the 2838 * virtual ones. 2839 */ 2840 if (encoder->type == INTEL_OUTPUT_DP_MST) 2841 return; 2842 2843 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2844 u8 pipe_mask; 2845 bool is_mst; 2846 2847 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2848 /* 2849 * In the unlikely case that BIOS enables DP in MST mode, just 2850 * warn since our MST HW readout is incomplete. 2851 */ 2852 if (WARN_ON(is_mst)) 2853 return; 2854 } 2855 2856 port_mask = BIT(encoder->port); 2857 ddi_clk_needed = encoder->base.crtc; 2858 2859 if (encoder->type == INTEL_OUTPUT_DSI) { 2860 struct intel_encoder *other_encoder; 2861 2862 port_mask = intel_dsi_encoder_ports(encoder); 2863 /* 2864 * Sanity check that we haven't incorrectly registered another 2865 * encoder using any of the ports of this DSI encoder. 2866 */ 2867 for_each_intel_encoder(&dev_priv->drm, other_encoder) { 2868 if (other_encoder == encoder) 2869 continue; 2870 2871 if (WARN_ON(port_mask & BIT(other_encoder->port))) 2872 return; 2873 } 2874 /* 2875 * For DSI we keep the ddi clocks gated 2876 * except during enable/disable sequence. 2877 */ 2878 ddi_clk_needed = false; 2879 } 2880 2881 val = I915_READ(ICL_DPCLKA_CFGCR0); 2882 for_each_port_masked(port, port_mask) { 2883 enum phy phy = intel_port_to_phy(dev_priv, port); 2884 2885 bool ddi_clk_ungated = !(val & 2886 icl_dpclka_cfgcr0_clk_off(dev_priv, 2887 phy)); 2888 2889 if (ddi_clk_needed == ddi_clk_ungated) 2890 continue; 2891 2892 /* 2893 * Punt on the case now where clock is gated, but it would 2894 * be needed by the port. Something else is really broken then. 2895 */ 2896 if (WARN_ON(ddi_clk_needed)) 2897 continue; 2898 2899 DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2900 phy_name(port)); 2901 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 2902 I915_WRITE(ICL_DPCLKA_CFGCR0, val); 2903 } 2904 } 2905 2906 static void intel_ddi_clk_select(struct intel_encoder *encoder, 2907 const struct intel_crtc_state *crtc_state) 2908 { 2909 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2910 enum port port = encoder->port; 2911 enum phy phy = intel_port_to_phy(dev_priv, port); 2912 u32 val; 2913 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 2914 2915 if (WARN_ON(!pll)) 2916 return; 2917 2918 mutex_lock(&dev_priv->dpll_lock); 2919 2920 if (INTEL_GEN(dev_priv) >= 11) { 2921 if (!intel_phy_is_combo(dev_priv, phy)) 2922 I915_WRITE(DDI_CLK_SEL(port), 2923 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 2924 } else if (IS_CANNONLAKE(dev_priv)) { 2925 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */ 2926 val = I915_READ(DPCLKA_CFGCR0); 2927 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); 2928 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port); 2929 I915_WRITE(DPCLKA_CFGCR0, val); 2930 2931 /* 2932 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI. 2933 * This step and the step before must be done with separate 2934 * register writes. 2935 */ 2936 val = I915_READ(DPCLKA_CFGCR0); 2937 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); 2938 I915_WRITE(DPCLKA_CFGCR0, val); 2939 } else if (IS_GEN9_BC(dev_priv)) { 2940 /* DDI -> PLL mapping */ 2941 val = I915_READ(DPLL_CTRL2); 2942 2943 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | 2944 DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); 2945 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 2946 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 2947 2948 I915_WRITE(DPLL_CTRL2, val); 2949 2950 } else if (INTEL_GEN(dev_priv) < 9) { 2951 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 2952 } 2953 2954 mutex_unlock(&dev_priv->dpll_lock); 2955 } 2956 2957 static void intel_ddi_clk_disable(struct intel_encoder *encoder) 2958 { 2959 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2960 enum port port = encoder->port; 2961 enum phy phy = intel_port_to_phy(dev_priv, port); 2962 2963 if (INTEL_GEN(dev_priv) >= 11) { 2964 if (!intel_phy_is_combo(dev_priv, phy)) 2965 I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 2966 } else if (IS_CANNONLAKE(dev_priv)) { 2967 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) | 2968 DPCLKA_CFGCR0_DDI_CLK_OFF(port)); 2969 } else if (IS_GEN9_BC(dev_priv)) { 2970 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) | 2971 DPLL_CTRL2_DDI_CLK_OFF(port)); 2972 } else if (INTEL_GEN(dev_priv) < 9) { 2973 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 2974 } 2975 } 2976 2977 static void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port) 2978 { 2979 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2980 enum port port = dig_port->base.port; 2981 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 2982 u32 val; 2983 int ln; 2984 2985 if (tc_port == PORT_TC_NONE) 2986 return; 2987 2988 for (ln = 0; ln < 2; ln++) { 2989 val = I915_READ(MG_DP_MODE(ln, port)); 2990 val |= MG_DP_MODE_CFG_TR2PWR_GATING | 2991 MG_DP_MODE_CFG_TRPWR_GATING | 2992 MG_DP_MODE_CFG_CLNPWR_GATING | 2993 MG_DP_MODE_CFG_DIGPWR_GATING | 2994 MG_DP_MODE_CFG_GAONPWR_GATING; 2995 I915_WRITE(MG_DP_MODE(ln, port), val); 2996 } 2997 2998 val = I915_READ(MG_MISC_SUS0(tc_port)); 2999 val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) | 3000 MG_MISC_SUS0_CFG_TR2PWR_GATING | 3001 MG_MISC_SUS0_CFG_CL2PWR_GATING | 3002 MG_MISC_SUS0_CFG_GAONPWR_GATING | 3003 MG_MISC_SUS0_CFG_TRPWR_GATING | 3004 MG_MISC_SUS0_CFG_CL1PWR_GATING | 3005 MG_MISC_SUS0_CFG_DGPWR_GATING; 3006 I915_WRITE(MG_MISC_SUS0(tc_port), val); 3007 } 3008 3009 static void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port) 3010 { 3011 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 3012 enum port port = dig_port->base.port; 3013 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 3014 u32 val; 3015 int ln; 3016 3017 if (tc_port == PORT_TC_NONE) 3018 return; 3019 3020 for (ln = 0; ln < 2; ln++) { 3021 val = I915_READ(MG_DP_MODE(ln, port)); 3022 val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING | 3023 MG_DP_MODE_CFG_TRPWR_GATING | 3024 MG_DP_MODE_CFG_CLNPWR_GATING | 3025 MG_DP_MODE_CFG_DIGPWR_GATING | 3026 MG_DP_MODE_CFG_GAONPWR_GATING); 3027 I915_WRITE(MG_DP_MODE(ln, port), val); 3028 } 3029 3030 val = I915_READ(MG_MISC_SUS0(tc_port)); 3031 val &= ~(MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK | 3032 MG_MISC_SUS0_CFG_TR2PWR_GATING | 3033 MG_MISC_SUS0_CFG_CL2PWR_GATING | 3034 MG_MISC_SUS0_CFG_GAONPWR_GATING | 3035 MG_MISC_SUS0_CFG_TRPWR_GATING | 3036 MG_MISC_SUS0_CFG_CL1PWR_GATING | 3037 MG_MISC_SUS0_CFG_DGPWR_GATING); 3038 I915_WRITE(MG_MISC_SUS0(tc_port), val); 3039 } 3040 3041 static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port) 3042 { 3043 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); 3044 enum port port = intel_dig_port->base.port; 3045 u32 ln0, ln1, lane_mask; 3046 3047 if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT) 3048 return; 3049 3050 ln0 = I915_READ(MG_DP_MODE(0, port)); 3051 ln1 = I915_READ(MG_DP_MODE(1, port)); 3052 3053 switch (intel_dig_port->tc_mode) { 3054 case TC_PORT_DP_ALT: 3055 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 3056 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 3057 3058 lane_mask = intel_tc_port_get_lane_mask(intel_dig_port); 3059 3060 switch (lane_mask) { 3061 case 0x1: 3062 case 0x4: 3063 break; 3064 case 0x2: 3065 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 3066 break; 3067 case 0x3: 3068 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | 3069 MG_DP_MODE_CFG_DP_X2_MODE; 3070 break; 3071 case 0x8: 3072 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 3073 break; 3074 case 0xC: 3075 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | 3076 MG_DP_MODE_CFG_DP_X2_MODE; 3077 break; 3078 case 0xF: 3079 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | 3080 MG_DP_MODE_CFG_DP_X2_MODE; 3081 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | 3082 MG_DP_MODE_CFG_DP_X2_MODE; 3083 break; 3084 default: 3085 MISSING_CASE(lane_mask); 3086 } 3087 break; 3088 3089 case TC_PORT_LEGACY: 3090 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE; 3091 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE; 3092 break; 3093 3094 default: 3095 MISSING_CASE(intel_dig_port->tc_mode); 3096 return; 3097 } 3098 3099 I915_WRITE(MG_DP_MODE(0, port), ln0); 3100 I915_WRITE(MG_DP_MODE(1, port), ln1); 3101 } 3102 3103 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 3104 const struct intel_crtc_state *crtc_state) 3105 { 3106 if (!crtc_state->fec_enable) 3107 return; 3108 3109 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0) 3110 DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n"); 3111 } 3112 3113 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 3114 const struct intel_crtc_state *crtc_state) 3115 { 3116 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3117 enum port port = encoder->port; 3118 u32 val; 3119 3120 if (!crtc_state->fec_enable) 3121 return; 3122 3123 val = I915_READ(DP_TP_CTL(port)); 3124 val |= DP_TP_CTL_FEC_ENABLE; 3125 I915_WRITE(DP_TP_CTL(port), val); 3126 3127 if (intel_wait_for_register(&dev_priv->uncore, DP_TP_STATUS(port), 3128 DP_TP_STATUS_FEC_ENABLE_LIVE, 3129 DP_TP_STATUS_FEC_ENABLE_LIVE, 3130 1)) 3131 DRM_ERROR("Timed out waiting for FEC Enable Status\n"); 3132 } 3133 3134 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder, 3135 const struct intel_crtc_state *crtc_state) 3136 { 3137 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3138 enum port port = encoder->port; 3139 u32 val; 3140 3141 if (!crtc_state->fec_enable) 3142 return; 3143 3144 val = I915_READ(DP_TP_CTL(port)); 3145 val &= ~DP_TP_CTL_FEC_ENABLE; 3146 I915_WRITE(DP_TP_CTL(port), val); 3147 POSTING_READ(DP_TP_CTL(port)); 3148 } 3149 3150 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, 3151 const struct intel_crtc_state *crtc_state, 3152 const struct drm_connector_state *conn_state) 3153 { 3154 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 3155 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3156 enum port port = encoder->port; 3157 enum phy phy = intel_port_to_phy(dev_priv, port); 3158 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 3159 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 3160 int level = intel_ddi_dp_level(intel_dp); 3161 3162 WARN_ON(is_mst && (port == PORT_A || port == PORT_E)); 3163 3164 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, 3165 crtc_state->lane_count, is_mst); 3166 3167 intel_edp_panel_on(intel_dp); 3168 3169 intel_ddi_clk_select(encoder, crtc_state); 3170 3171 if (!intel_phy_is_tc(dev_priv, phy) || 3172 dig_port->tc_mode != TC_PORT_TBT_ALT) 3173 intel_display_power_get(dev_priv, 3174 dig_port->ddi_io_power_domain); 3175 3176 icl_program_mg_dp_mode(dig_port); 3177 icl_disable_phy_clock_gating(dig_port); 3178 3179 if (INTEL_GEN(dev_priv) >= 11) 3180 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, 3181 level, encoder->type); 3182 else if (IS_CANNONLAKE(dev_priv)) 3183 cnl_ddi_vswing_sequence(encoder, level, encoder->type); 3184 else if (IS_GEN9_LP(dev_priv)) 3185 bxt_ddi_vswing_sequence(encoder, level, encoder->type); 3186 else 3187 intel_prepare_dp_ddi_buffers(encoder, crtc_state); 3188 3189 if (intel_phy_is_combo(dev_priv, phy)) { 3190 bool lane_reversal = 3191 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 3192 3193 intel_combo_phy_power_up_lanes(dev_priv, phy, false, 3194 crtc_state->lane_count, 3195 lane_reversal); 3196 } 3197 3198 intel_ddi_init_dp_buf_reg(encoder); 3199 if (!is_mst) 3200 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 3201 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, 3202 true); 3203 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 3204 intel_dp_start_link_train(intel_dp); 3205 if (port != PORT_A || INTEL_GEN(dev_priv) >= 9) 3206 intel_dp_stop_link_train(intel_dp); 3207 3208 intel_ddi_enable_fec(encoder, crtc_state); 3209 3210 icl_enable_phy_clock_gating(dig_port); 3211 3212 if (!is_mst) 3213 intel_ddi_enable_pipe_clock(crtc_state); 3214 3215 intel_dsc_enable(encoder, crtc_state); 3216 } 3217 3218 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder, 3219 const struct intel_crtc_state *crtc_state, 3220 const struct drm_connector_state *conn_state) 3221 { 3222 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); 3223 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 3224 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3225 enum port port = encoder->port; 3226 int level = intel_ddi_hdmi_level(dev_priv, port); 3227 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 3228 3229 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 3230 intel_ddi_clk_select(encoder, crtc_state); 3231 3232 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); 3233 3234 icl_program_mg_dp_mode(dig_port); 3235 icl_disable_phy_clock_gating(dig_port); 3236 3237 if (INTEL_GEN(dev_priv) >= 11) 3238 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, 3239 level, INTEL_OUTPUT_HDMI); 3240 else if (IS_CANNONLAKE(dev_priv)) 3241 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI); 3242 else if (IS_GEN9_LP(dev_priv)) 3243 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI); 3244 else 3245 intel_prepare_hdmi_ddi_buffers(encoder, level); 3246 3247 icl_enable_phy_clock_gating(dig_port); 3248 3249 if (IS_GEN9_BC(dev_priv)) 3250 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI); 3251 3252 intel_ddi_enable_pipe_clock(crtc_state); 3253 3254 intel_dig_port->set_infoframes(encoder, 3255 crtc_state->has_infoframe, 3256 crtc_state, conn_state); 3257 } 3258 3259 static void intel_ddi_pre_enable(struct intel_encoder *encoder, 3260 const struct intel_crtc_state *crtc_state, 3261 const struct drm_connector_state *conn_state) 3262 { 3263 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 3264 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3265 enum pipe pipe = crtc->pipe; 3266 3267 /* 3268 * When called from DP MST code: 3269 * - conn_state will be NULL 3270 * - encoder will be the main encoder (ie. mst->primary) 3271 * - the main connector associated with this port 3272 * won't be active or linked to a crtc 3273 * - crtc_state will be the state of the first stream to 3274 * be activated on this port, and it may not be the same 3275 * stream that will be deactivated last, but each stream 3276 * should have a state that is identical when it comes to 3277 * the DP link parameteres 3278 */ 3279 3280 WARN_ON(crtc_state->has_pch_encoder); 3281 3282 if (INTEL_GEN(dev_priv) >= 11) 3283 icl_map_plls_to_ports(encoder, crtc_state); 3284 3285 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 3286 3287 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 3288 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state); 3289 } else { 3290 struct intel_lspcon *lspcon = 3291 enc_to_intel_lspcon(&encoder->base); 3292 3293 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state); 3294 if (lspcon->active) { 3295 struct intel_digital_port *dig_port = 3296 enc_to_dig_port(&encoder->base); 3297 3298 dig_port->set_infoframes(encoder, 3299 crtc_state->has_infoframe, 3300 crtc_state, conn_state); 3301 } 3302 } 3303 } 3304 3305 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 3306 const struct intel_crtc_state *crtc_state) 3307 { 3308 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3309 enum port port = encoder->port; 3310 bool wait = false; 3311 u32 val; 3312 3313 val = I915_READ(DDI_BUF_CTL(port)); 3314 if (val & DDI_BUF_CTL_ENABLE) { 3315 val &= ~DDI_BUF_CTL_ENABLE; 3316 I915_WRITE(DDI_BUF_CTL(port), val); 3317 wait = true; 3318 } 3319 3320 val = I915_READ(DP_TP_CTL(port)); 3321 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 3322 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 3323 I915_WRITE(DP_TP_CTL(port), val); 3324 3325 /* Disable FEC in DP Sink */ 3326 intel_ddi_disable_fec_state(encoder, crtc_state); 3327 3328 if (wait) 3329 intel_wait_ddi_buf_idle(dev_priv, port); 3330 } 3331 3332 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder, 3333 const struct intel_crtc_state *old_crtc_state, 3334 const struct drm_connector_state *old_conn_state) 3335 { 3336 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3337 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 3338 struct intel_dp *intel_dp = &dig_port->dp; 3339 bool is_mst = intel_crtc_has_type(old_crtc_state, 3340 INTEL_OUTPUT_DP_MST); 3341 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3342 3343 if (!is_mst) { 3344 intel_ddi_disable_pipe_clock(old_crtc_state); 3345 /* 3346 * Power down sink before disabling the port, otherwise we end 3347 * up getting interrupts from the sink on detecting link loss. 3348 */ 3349 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 3350 } 3351 3352 intel_disable_ddi_buf(encoder, old_crtc_state); 3353 3354 intel_edp_panel_vdd_on(intel_dp); 3355 intel_edp_panel_off(intel_dp); 3356 3357 if (!intel_phy_is_tc(dev_priv, phy) || 3358 dig_port->tc_mode != TC_PORT_TBT_ALT) 3359 intel_display_power_put_unchecked(dev_priv, 3360 dig_port->ddi_io_power_domain); 3361 3362 intel_ddi_clk_disable(encoder); 3363 } 3364 3365 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder, 3366 const struct intel_crtc_state *old_crtc_state, 3367 const struct drm_connector_state *old_conn_state) 3368 { 3369 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3370 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 3371 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3372 3373 dig_port->set_infoframes(encoder, false, 3374 old_crtc_state, old_conn_state); 3375 3376 intel_ddi_disable_pipe_clock(old_crtc_state); 3377 3378 intel_disable_ddi_buf(encoder, old_crtc_state); 3379 3380 intel_display_power_put_unchecked(dev_priv, 3381 dig_port->ddi_io_power_domain); 3382 3383 intel_ddi_clk_disable(encoder); 3384 3385 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3386 } 3387 3388 static void intel_ddi_post_disable(struct intel_encoder *encoder, 3389 const struct intel_crtc_state *old_crtc_state, 3390 const struct drm_connector_state *old_conn_state) 3391 { 3392 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3393 3394 /* 3395 * When called from DP MST code: 3396 * - old_conn_state will be NULL 3397 * - encoder will be the main encoder (ie. mst->primary) 3398 * - the main connector associated with this port 3399 * won't be active or linked to a crtc 3400 * - old_crtc_state will be the state of the last stream to 3401 * be deactivated on this port, and it may not be the same 3402 * stream that was activated last, but each stream 3403 * should have a state that is identical when it comes to 3404 * the DP link parameteres 3405 */ 3406 3407 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3408 intel_ddi_post_disable_hdmi(encoder, 3409 old_crtc_state, old_conn_state); 3410 else 3411 intel_ddi_post_disable_dp(encoder, 3412 old_crtc_state, old_conn_state); 3413 3414 if (INTEL_GEN(dev_priv) >= 11) 3415 icl_unmap_plls_to_ports(encoder); 3416 } 3417 3418 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder, 3419 const struct intel_crtc_state *old_crtc_state, 3420 const struct drm_connector_state *old_conn_state) 3421 { 3422 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3423 u32 val; 3424 3425 /* 3426 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable) 3427 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN, 3428 * step 13 is the correct place for it. Step 18 is where it was 3429 * originally before the BUN. 3430 */ 3431 val = I915_READ(FDI_RX_CTL(PIPE_A)); 3432 val &= ~FDI_RX_ENABLE; 3433 I915_WRITE(FDI_RX_CTL(PIPE_A), val); 3434 3435 intel_disable_ddi_buf(encoder, old_crtc_state); 3436 intel_ddi_clk_disable(encoder); 3437 3438 val = I915_READ(FDI_RX_MISC(PIPE_A)); 3439 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 3440 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 3441 I915_WRITE(FDI_RX_MISC(PIPE_A), val); 3442 3443 val = I915_READ(FDI_RX_CTL(PIPE_A)); 3444 val &= ~FDI_PCDCLK; 3445 I915_WRITE(FDI_RX_CTL(PIPE_A), val); 3446 3447 val = I915_READ(FDI_RX_CTL(PIPE_A)); 3448 val &= ~FDI_RX_PLL_ENABLE; 3449 I915_WRITE(FDI_RX_CTL(PIPE_A), val); 3450 } 3451 3452 static void intel_enable_ddi_dp(struct intel_encoder *encoder, 3453 const struct intel_crtc_state *crtc_state, 3454 const struct drm_connector_state *conn_state) 3455 { 3456 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3457 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 3458 enum port port = encoder->port; 3459 3460 if (port == PORT_A && INTEL_GEN(dev_priv) < 9) 3461 intel_dp_stop_link_train(intel_dp); 3462 3463 intel_edp_backlight_on(crtc_state, conn_state); 3464 intel_psr_enable(intel_dp, crtc_state); 3465 intel_dp_ycbcr_420_enable(intel_dp, crtc_state); 3466 intel_edp_drrs_enable(intel_dp, crtc_state); 3467 3468 if (crtc_state->has_audio) 3469 intel_audio_codec_enable(encoder, crtc_state, conn_state); 3470 } 3471 3472 static i915_reg_t 3473 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 3474 enum port port) 3475 { 3476 static const i915_reg_t regs[] = { 3477 [PORT_A] = CHICKEN_TRANS_EDP, 3478 [PORT_B] = CHICKEN_TRANS_A, 3479 [PORT_C] = CHICKEN_TRANS_B, 3480 [PORT_D] = CHICKEN_TRANS_C, 3481 [PORT_E] = CHICKEN_TRANS_A, 3482 }; 3483 3484 WARN_ON(INTEL_GEN(dev_priv) < 9); 3485 3486 if (WARN_ON(port < PORT_A || port > PORT_E)) 3487 port = PORT_A; 3488 3489 return regs[port]; 3490 } 3491 3492 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder, 3493 const struct intel_crtc_state *crtc_state, 3494 const struct drm_connector_state *conn_state) 3495 { 3496 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3497 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 3498 struct drm_connector *connector = conn_state->connector; 3499 enum port port = encoder->port; 3500 3501 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3502 crtc_state->hdmi_high_tmds_clock_ratio, 3503 crtc_state->hdmi_scrambling)) 3504 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3505 connector->base.id, connector->name); 3506 3507 /* Display WA #1143: skl,kbl,cfl */ 3508 if (IS_GEN9_BC(dev_priv)) { 3509 /* 3510 * For some reason these chicken bits have been 3511 * stuffed into a transcoder register, event though 3512 * the bits affect a specific DDI port rather than 3513 * a specific transcoder. 3514 */ 3515 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 3516 u32 val; 3517 3518 val = I915_READ(reg); 3519 3520 if (port == PORT_E) 3521 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3522 DDIE_TRAINING_OVERRIDE_VALUE; 3523 else 3524 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3525 DDI_TRAINING_OVERRIDE_VALUE; 3526 3527 I915_WRITE(reg, val); 3528 POSTING_READ(reg); 3529 3530 udelay(1); 3531 3532 if (port == PORT_E) 3533 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3534 DDIE_TRAINING_OVERRIDE_VALUE); 3535 else 3536 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3537 DDI_TRAINING_OVERRIDE_VALUE); 3538 3539 I915_WRITE(reg, val); 3540 } 3541 3542 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3543 * are ignored so nothing special needs to be done besides 3544 * enabling the port. 3545 */ 3546 I915_WRITE(DDI_BUF_CTL(port), 3547 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE); 3548 3549 if (crtc_state->has_audio) 3550 intel_audio_codec_enable(encoder, crtc_state, conn_state); 3551 } 3552 3553 static void intel_enable_ddi(struct intel_encoder *encoder, 3554 const struct intel_crtc_state *crtc_state, 3555 const struct drm_connector_state *conn_state) 3556 { 3557 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3558 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state); 3559 else 3560 intel_enable_ddi_dp(encoder, crtc_state, conn_state); 3561 3562 /* Enable hdcp if it's desired */ 3563 if (conn_state->content_protection == 3564 DRM_MODE_CONTENT_PROTECTION_DESIRED) 3565 intel_hdcp_enable(to_intel_connector(conn_state->connector), 3566 (u8)conn_state->hdcp_content_type); 3567 } 3568 3569 static void intel_disable_ddi_dp(struct intel_encoder *encoder, 3570 const struct intel_crtc_state *old_crtc_state, 3571 const struct drm_connector_state *old_conn_state) 3572 { 3573 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 3574 3575 intel_dp->link_trained = false; 3576 3577 if (old_crtc_state->has_audio) 3578 intel_audio_codec_disable(encoder, 3579 old_crtc_state, old_conn_state); 3580 3581 intel_edp_drrs_disable(intel_dp, old_crtc_state); 3582 intel_psr_disable(intel_dp, old_crtc_state); 3583 intel_edp_backlight_off(old_conn_state); 3584 /* Disable the decompression in DP Sink */ 3585 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, 3586 false); 3587 } 3588 3589 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder, 3590 const struct intel_crtc_state *old_crtc_state, 3591 const struct drm_connector_state *old_conn_state) 3592 { 3593 struct drm_connector *connector = old_conn_state->connector; 3594 3595 if (old_crtc_state->has_audio) 3596 intel_audio_codec_disable(encoder, 3597 old_crtc_state, old_conn_state); 3598 3599 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3600 false, false)) 3601 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3602 connector->base.id, connector->name); 3603 } 3604 3605 static void intel_disable_ddi(struct intel_encoder *encoder, 3606 const struct intel_crtc_state *old_crtc_state, 3607 const struct drm_connector_state *old_conn_state) 3608 { 3609 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3610 3611 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3612 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state); 3613 else 3614 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state); 3615 } 3616 3617 static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder, 3618 const struct intel_crtc_state *crtc_state, 3619 const struct drm_connector_state *conn_state) 3620 { 3621 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 3622 3623 intel_ddi_set_pipe_settings(crtc_state); 3624 3625 intel_psr_update(intel_dp, crtc_state); 3626 intel_edp_drrs_enable(intel_dp, crtc_state); 3627 3628 intel_panel_update_backlight(encoder, crtc_state, conn_state); 3629 } 3630 3631 static void intel_ddi_update_pipe(struct intel_encoder *encoder, 3632 const struct intel_crtc_state *crtc_state, 3633 const struct drm_connector_state *conn_state) 3634 { 3635 struct intel_connector *connector = 3636 to_intel_connector(conn_state->connector); 3637 struct intel_hdcp *hdcp = &connector->hdcp; 3638 bool content_protection_type_changed = 3639 (conn_state->hdcp_content_type != hdcp->content_type && 3640 conn_state->content_protection != 3641 DRM_MODE_CONTENT_PROTECTION_UNDESIRED); 3642 3643 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3644 intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state); 3645 3646 /* 3647 * During the HDCP encryption session if Type change is requested, 3648 * disable the HDCP and reenable it with new TYPE value. 3649 */ 3650 if (conn_state->content_protection == 3651 DRM_MODE_CONTENT_PROTECTION_UNDESIRED || 3652 content_protection_type_changed) 3653 intel_hdcp_disable(connector); 3654 3655 /* 3656 * Mark the hdcp state as DESIRED after the hdcp disable of type 3657 * change procedure. 3658 */ 3659 if (content_protection_type_changed) { 3660 mutex_lock(&hdcp->mutex); 3661 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; 3662 schedule_work(&hdcp->prop_work); 3663 mutex_unlock(&hdcp->mutex); 3664 } 3665 3666 if (conn_state->content_protection == 3667 DRM_MODE_CONTENT_PROTECTION_DESIRED || 3668 content_protection_type_changed) 3669 intel_hdcp_enable(connector, (u8)conn_state->hdcp_content_type); 3670 } 3671 3672 static void 3673 intel_ddi_update_prepare(struct intel_atomic_state *state, 3674 struct intel_encoder *encoder, 3675 struct intel_crtc *crtc) 3676 { 3677 struct intel_crtc_state *crtc_state = 3678 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL; 3679 int required_lanes = crtc_state ? crtc_state->lane_count : 1; 3680 3681 WARN_ON(crtc && crtc->active); 3682 3683 intel_tc_port_get_link(enc_to_dig_port(&encoder->base), required_lanes); 3684 if (crtc_state && crtc_state->base.active) 3685 intel_update_active_dpll(state, crtc, encoder); 3686 } 3687 3688 static void 3689 intel_ddi_update_complete(struct intel_atomic_state *state, 3690 struct intel_encoder *encoder, 3691 struct intel_crtc *crtc) 3692 { 3693 intel_tc_port_put_link(enc_to_dig_port(&encoder->base)); 3694 } 3695 3696 static void 3697 intel_ddi_pre_pll_enable(struct intel_encoder *encoder, 3698 const struct intel_crtc_state *crtc_state, 3699 const struct drm_connector_state *conn_state) 3700 { 3701 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3702 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 3703 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3704 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 3705 3706 if (is_tc_port) 3707 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3708 3709 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) 3710 intel_display_power_get(dev_priv, 3711 intel_ddi_main_link_aux_domain(dig_port)); 3712 3713 if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT) 3714 /* 3715 * Program the lane count for static/dynamic connections on 3716 * Type-C ports. Skip this step for TBT. 3717 */ 3718 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3719 else if (IS_GEN9_LP(dev_priv)) 3720 bxt_ddi_phy_set_lane_optim_mask(encoder, 3721 crtc_state->lane_lat_optim_mask); 3722 } 3723 3724 static void 3725 intel_ddi_post_pll_disable(struct intel_encoder *encoder, 3726 const struct intel_crtc_state *crtc_state, 3727 const struct drm_connector_state *conn_state) 3728 { 3729 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3730 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 3731 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3732 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 3733 3734 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) 3735 intel_display_power_put_unchecked(dev_priv, 3736 intel_ddi_main_link_aux_domain(dig_port)); 3737 3738 if (is_tc_port) 3739 intel_tc_port_put_link(dig_port); 3740 } 3741 3742 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) 3743 { 3744 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3745 struct drm_i915_private *dev_priv = 3746 to_i915(intel_dig_port->base.base.dev); 3747 enum port port = intel_dig_port->base.port; 3748 u32 val; 3749 bool wait = false; 3750 3751 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { 3752 val = I915_READ(DDI_BUF_CTL(port)); 3753 if (val & DDI_BUF_CTL_ENABLE) { 3754 val &= ~DDI_BUF_CTL_ENABLE; 3755 I915_WRITE(DDI_BUF_CTL(port), val); 3756 wait = true; 3757 } 3758 3759 val = I915_READ(DP_TP_CTL(port)); 3760 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 3761 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 3762 I915_WRITE(DP_TP_CTL(port), val); 3763 POSTING_READ(DP_TP_CTL(port)); 3764 3765 if (wait) 3766 intel_wait_ddi_buf_idle(dev_priv, port); 3767 } 3768 3769 val = DP_TP_CTL_ENABLE | 3770 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; 3771 if (intel_dp->link_mst) 3772 val |= DP_TP_CTL_MODE_MST; 3773 else { 3774 val |= DP_TP_CTL_MODE_SST; 3775 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 3776 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3777 } 3778 I915_WRITE(DP_TP_CTL(port), val); 3779 POSTING_READ(DP_TP_CTL(port)); 3780 3781 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3782 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); 3783 POSTING_READ(DDI_BUF_CTL(port)); 3784 3785 udelay(600); 3786 } 3787 3788 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 3789 enum transcoder cpu_transcoder) 3790 { 3791 if (cpu_transcoder == TRANSCODER_EDP) 3792 return false; 3793 3794 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) 3795 return false; 3796 3797 return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) & 3798 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3799 } 3800 3801 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, 3802 struct intel_crtc_state *crtc_state) 3803 { 3804 if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000) 3805 crtc_state->min_voltage_level = 1; 3806 else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000) 3807 crtc_state->min_voltage_level = 2; 3808 } 3809 3810 void intel_ddi_get_config(struct intel_encoder *encoder, 3811 struct intel_crtc_state *pipe_config) 3812 { 3813 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3814 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); 3815 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3816 u32 temp, flags = 0; 3817 3818 /* XXX: DSI transcoder paranoia */ 3819 if (WARN_ON(transcoder_is_dsi(cpu_transcoder))) 3820 return; 3821 3822 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3823 if (temp & TRANS_DDI_PHSYNC) 3824 flags |= DRM_MODE_FLAG_PHSYNC; 3825 else 3826 flags |= DRM_MODE_FLAG_NHSYNC; 3827 if (temp & TRANS_DDI_PVSYNC) 3828 flags |= DRM_MODE_FLAG_PVSYNC; 3829 else 3830 flags |= DRM_MODE_FLAG_NVSYNC; 3831 3832 pipe_config->base.adjusted_mode.flags |= flags; 3833 3834 switch (temp & TRANS_DDI_BPC_MASK) { 3835 case TRANS_DDI_BPC_6: 3836 pipe_config->pipe_bpp = 18; 3837 break; 3838 case TRANS_DDI_BPC_8: 3839 pipe_config->pipe_bpp = 24; 3840 break; 3841 case TRANS_DDI_BPC_10: 3842 pipe_config->pipe_bpp = 30; 3843 break; 3844 case TRANS_DDI_BPC_12: 3845 pipe_config->pipe_bpp = 36; 3846 break; 3847 default: 3848 break; 3849 } 3850 3851 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 3852 case TRANS_DDI_MODE_SELECT_HDMI: 3853 pipe_config->has_hdmi_sink = true; 3854 3855 pipe_config->infoframes.enable |= 3856 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3857 3858 if (pipe_config->infoframes.enable) 3859 pipe_config->has_infoframe = true; 3860 3861 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 3862 pipe_config->hdmi_scrambling = true; 3863 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 3864 pipe_config->hdmi_high_tmds_clock_ratio = true; 3865 /* fall through */ 3866 case TRANS_DDI_MODE_SELECT_DVI: 3867 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 3868 pipe_config->lane_count = 4; 3869 break; 3870 case TRANS_DDI_MODE_SELECT_FDI: 3871 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 3872 break; 3873 case TRANS_DDI_MODE_SELECT_DP_SST: 3874 if (encoder->type == INTEL_OUTPUT_EDP) 3875 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 3876 else 3877 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 3878 pipe_config->lane_count = 3879 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3880 intel_dp_get_m_n(intel_crtc, pipe_config); 3881 break; 3882 case TRANS_DDI_MODE_SELECT_DP_MST: 3883 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 3884 pipe_config->lane_count = 3885 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3886 intel_dp_get_m_n(intel_crtc, pipe_config); 3887 break; 3888 default: 3889 break; 3890 } 3891 3892 pipe_config->has_audio = 3893 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 3894 3895 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp && 3896 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { 3897 /* 3898 * This is a big fat ugly hack. 3899 * 3900 * Some machines in UEFI boot mode provide us a VBT that has 18 3901 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 3902 * unknown we fail to light up. Yet the same BIOS boots up with 3903 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 3904 * max, not what it tells us to use. 3905 * 3906 * Note: This will still be broken if the eDP panel is not lit 3907 * up by the BIOS, and thus we can't get the mode at module 3908 * load. 3909 */ 3910 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 3911 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); 3912 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; 3913 } 3914 3915 intel_ddi_clock_get(encoder, pipe_config); 3916 3917 if (IS_GEN9_LP(dev_priv)) 3918 pipe_config->lane_lat_optim_mask = 3919 bxt_ddi_phy_get_lane_lat_optim_mask(encoder); 3920 3921 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 3922 3923 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 3924 3925 intel_read_infoframe(encoder, pipe_config, 3926 HDMI_INFOFRAME_TYPE_AVI, 3927 &pipe_config->infoframes.avi); 3928 intel_read_infoframe(encoder, pipe_config, 3929 HDMI_INFOFRAME_TYPE_SPD, 3930 &pipe_config->infoframes.spd); 3931 intel_read_infoframe(encoder, pipe_config, 3932 HDMI_INFOFRAME_TYPE_VENDOR, 3933 &pipe_config->infoframes.hdmi); 3934 intel_read_infoframe(encoder, pipe_config, 3935 HDMI_INFOFRAME_TYPE_DRM, 3936 &pipe_config->infoframes.drm); 3937 } 3938 3939 static enum intel_output_type 3940 intel_ddi_compute_output_type(struct intel_encoder *encoder, 3941 struct intel_crtc_state *crtc_state, 3942 struct drm_connector_state *conn_state) 3943 { 3944 switch (conn_state->connector->connector_type) { 3945 case DRM_MODE_CONNECTOR_HDMIA: 3946 return INTEL_OUTPUT_HDMI; 3947 case DRM_MODE_CONNECTOR_eDP: 3948 return INTEL_OUTPUT_EDP; 3949 case DRM_MODE_CONNECTOR_DisplayPort: 3950 return INTEL_OUTPUT_DP; 3951 default: 3952 MISSING_CASE(conn_state->connector->connector_type); 3953 return INTEL_OUTPUT_UNUSED; 3954 } 3955 } 3956 3957 static int intel_ddi_compute_config(struct intel_encoder *encoder, 3958 struct intel_crtc_state *pipe_config, 3959 struct drm_connector_state *conn_state) 3960 { 3961 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); 3962 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3963 enum port port = encoder->port; 3964 int ret; 3965 3966 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) 3967 pipe_config->cpu_transcoder = TRANSCODER_EDP; 3968 3969 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) 3970 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 3971 else 3972 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 3973 if (ret) 3974 return ret; 3975 3976 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 3977 pipe_config->cpu_transcoder == TRANSCODER_EDP) 3978 pipe_config->pch_pfit.force_thru = 3979 pipe_config->pch_pfit.enabled || 3980 pipe_config->crc_enabled; 3981 3982 if (IS_GEN9_LP(dev_priv)) 3983 pipe_config->lane_lat_optim_mask = 3984 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 3985 3986 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 3987 3988 return 0; 3989 } 3990 3991 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 3992 { 3993 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3994 3995 intel_dp_encoder_flush_work(encoder); 3996 3997 drm_encoder_cleanup(encoder); 3998 kfree(dig_port); 3999 } 4000 4001 static const struct drm_encoder_funcs intel_ddi_funcs = { 4002 .reset = intel_dp_encoder_reset, 4003 .destroy = intel_ddi_encoder_destroy, 4004 }; 4005 4006 static struct intel_connector * 4007 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) 4008 { 4009 struct intel_connector *connector; 4010 enum port port = intel_dig_port->base.port; 4011 4012 connector = intel_connector_alloc(); 4013 if (!connector) 4014 return NULL; 4015 4016 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); 4017 intel_dig_port->dp.prepare_link_retrain = 4018 intel_ddi_prepare_link_retrain; 4019 4020 if (!intel_dp_init_connector(intel_dig_port, connector)) { 4021 kfree(connector); 4022 return NULL; 4023 } 4024 4025 return connector; 4026 } 4027 4028 static int modeset_pipe(struct drm_crtc *crtc, 4029 struct drm_modeset_acquire_ctx *ctx) 4030 { 4031 struct drm_atomic_state *state; 4032 struct drm_crtc_state *crtc_state; 4033 int ret; 4034 4035 state = drm_atomic_state_alloc(crtc->dev); 4036 if (!state) 4037 return -ENOMEM; 4038 4039 state->acquire_ctx = ctx; 4040 4041 crtc_state = drm_atomic_get_crtc_state(state, crtc); 4042 if (IS_ERR(crtc_state)) { 4043 ret = PTR_ERR(crtc_state); 4044 goto out; 4045 } 4046 4047 crtc_state->connectors_changed = true; 4048 4049 ret = drm_atomic_commit(state); 4050 out: 4051 drm_atomic_state_put(state); 4052 4053 return ret; 4054 } 4055 4056 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4057 struct drm_modeset_acquire_ctx *ctx) 4058 { 4059 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4060 struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base); 4061 struct intel_connector *connector = hdmi->attached_connector; 4062 struct i2c_adapter *adapter = 4063 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 4064 struct drm_connector_state *conn_state; 4065 struct intel_crtc_state *crtc_state; 4066 struct intel_crtc *crtc; 4067 u8 config; 4068 int ret; 4069 4070 if (!connector || connector->base.status != connector_status_connected) 4071 return 0; 4072 4073 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 4074 ctx); 4075 if (ret) 4076 return ret; 4077 4078 conn_state = connector->base.state; 4079 4080 crtc = to_intel_crtc(conn_state->crtc); 4081 if (!crtc) 4082 return 0; 4083 4084 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4085 if (ret) 4086 return ret; 4087 4088 crtc_state = to_intel_crtc_state(crtc->base.state); 4089 4090 WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4091 4092 if (!crtc_state->base.active) 4093 return 0; 4094 4095 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4096 !crtc_state->hdmi_scrambling) 4097 return 0; 4098 4099 if (conn_state->commit && 4100 !try_wait_for_completion(&conn_state->commit->hw_done)) 4101 return 0; 4102 4103 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 4104 if (ret < 0) { 4105 DRM_ERROR("Failed to read TMDS config: %d\n", ret); 4106 return 0; 4107 } 4108 4109 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4110 crtc_state->hdmi_high_tmds_clock_ratio && 4111 !!(config & SCDC_SCRAMBLING_ENABLE) == 4112 crtc_state->hdmi_scrambling) 4113 return 0; 4114 4115 /* 4116 * HDMI 2.0 says that one should not send scrambled data 4117 * prior to configuring the sink scrambling, and that 4118 * TMDS clock/data transmission should be suspended when 4119 * changing the TMDS clock rate in the sink. So let's 4120 * just do a full modeset here, even though some sinks 4121 * would be perfectly happy if were to just reconfigure 4122 * the SCDC settings on the fly. 4123 */ 4124 return modeset_pipe(&crtc->base, ctx); 4125 } 4126 4127 static enum intel_hotplug_state 4128 intel_ddi_hotplug(struct intel_encoder *encoder, 4129 struct intel_connector *connector, 4130 bool irq_received) 4131 { 4132 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 4133 struct drm_modeset_acquire_ctx ctx; 4134 enum intel_hotplug_state state; 4135 int ret; 4136 4137 state = intel_encoder_hotplug(encoder, connector, irq_received); 4138 4139 drm_modeset_acquire_init(&ctx, 0); 4140 4141 for (;;) { 4142 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) 4143 ret = intel_hdmi_reset_link(encoder, &ctx); 4144 else 4145 ret = intel_dp_retrain_link(encoder, &ctx); 4146 4147 if (ret == -EDEADLK) { 4148 drm_modeset_backoff(&ctx); 4149 continue; 4150 } 4151 4152 break; 4153 } 4154 4155 drm_modeset_drop_locks(&ctx); 4156 drm_modeset_acquire_fini(&ctx); 4157 WARN(ret, "Acquiring modeset locks failed with %i\n", ret); 4158 4159 /* 4160 * Unpowered type-c dongles can take some time to boot and be 4161 * responsible, so here giving some time to those dongles to power up 4162 * and then retrying the probe. 4163 * 4164 * On many platforms the HDMI live state signal is known to be 4165 * unreliable, so we can't use it to detect if a sink is connected or 4166 * not. Instead we detect if it's connected based on whether we can 4167 * read the EDID or not. That in turn has a problem during disconnect, 4168 * since the HPD interrupt may be raised before the DDC lines get 4169 * disconnected (due to how the required length of DDC vs. HPD 4170 * connector pins are specified) and so we'll still be able to get a 4171 * valid EDID. To solve this schedule another detection cycle if this 4172 * time around we didn't detect any change in the sink's connection 4173 * status. 4174 */ 4175 if (state == INTEL_HOTPLUG_UNCHANGED && irq_received && 4176 !dig_port->dp.is_mst) 4177 state = INTEL_HOTPLUG_RETRY; 4178 4179 return state; 4180 } 4181 4182 static struct intel_connector * 4183 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) 4184 { 4185 struct intel_connector *connector; 4186 enum port port = intel_dig_port->base.port; 4187 4188 connector = intel_connector_alloc(); 4189 if (!connector) 4190 return NULL; 4191 4192 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4193 intel_hdmi_init_connector(intel_dig_port, connector); 4194 4195 return connector; 4196 } 4197 4198 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport) 4199 { 4200 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); 4201 4202 if (dport->base.port != PORT_A) 4203 return false; 4204 4205 if (dport->saved_port_bits & DDI_A_4_LANES) 4206 return false; 4207 4208 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4209 * supported configuration 4210 */ 4211 if (IS_GEN9_LP(dev_priv)) 4212 return true; 4213 4214 /* Cannonlake: Most of SKUs don't support DDI_E, and the only 4215 * one who does also have a full A/E split called 4216 * DDI_F what makes DDI_E useless. However for this 4217 * case let's trust VBT info. 4218 */ 4219 if (IS_CANNONLAKE(dev_priv) && 4220 !intel_bios_is_port_present(dev_priv, PORT_E)) 4221 return true; 4222 4223 return false; 4224 } 4225 4226 static int 4227 intel_ddi_max_lanes(struct intel_digital_port *intel_dport) 4228 { 4229 struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev); 4230 enum port port = intel_dport->base.port; 4231 int max_lanes = 4; 4232 4233 if (INTEL_GEN(dev_priv) >= 11) 4234 return max_lanes; 4235 4236 if (port == PORT_A || port == PORT_E) { 4237 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4238 max_lanes = port == PORT_A ? 4 : 0; 4239 else 4240 /* Both A and E share 2 lanes */ 4241 max_lanes = 2; 4242 } 4243 4244 /* 4245 * Some BIOS might fail to set this bit on port A if eDP 4246 * wasn't lit up at boot. Force this bit set when needed 4247 * so we use the proper lane count for our calculations. 4248 */ 4249 if (intel_ddi_a_force_4_lanes(intel_dport)) { 4250 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n"); 4251 intel_dport->saved_port_bits |= DDI_A_4_LANES; 4252 max_lanes = 4; 4253 } 4254 4255 return max_lanes; 4256 } 4257 4258 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 4259 { 4260 struct ddi_vbt_port_info *port_info = 4261 &dev_priv->vbt.ddi_port_info[port]; 4262 struct intel_digital_port *intel_dig_port; 4263 struct intel_encoder *intel_encoder; 4264 struct drm_encoder *encoder; 4265 bool init_hdmi, init_dp, init_lspcon = false; 4266 enum pipe pipe; 4267 enum phy phy = intel_port_to_phy(dev_priv, port); 4268 4269 init_hdmi = port_info->supports_dvi || port_info->supports_hdmi; 4270 init_dp = port_info->supports_dp; 4271 4272 if (intel_bios_is_lspcon_present(dev_priv, port)) { 4273 /* 4274 * Lspcon device needs to be driven with DP connector 4275 * with special detection sequence. So make sure DP 4276 * is initialized before lspcon. 4277 */ 4278 init_dp = true; 4279 init_lspcon = true; 4280 init_hdmi = false; 4281 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port)); 4282 } 4283 4284 if (!init_dp && !init_hdmi) { 4285 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 4286 port_name(port)); 4287 return; 4288 } 4289 4290 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 4291 if (!intel_dig_port) 4292 return; 4293 4294 intel_encoder = &intel_dig_port->base; 4295 encoder = &intel_encoder->base; 4296 4297 drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs, 4298 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port)); 4299 4300 intel_encoder->hotplug = intel_ddi_hotplug; 4301 intel_encoder->compute_output_type = intel_ddi_compute_output_type; 4302 intel_encoder->compute_config = intel_ddi_compute_config; 4303 intel_encoder->enable = intel_enable_ddi; 4304 intel_encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 4305 intel_encoder->post_pll_disable = intel_ddi_post_pll_disable; 4306 intel_encoder->pre_enable = intel_ddi_pre_enable; 4307 intel_encoder->disable = intel_disable_ddi; 4308 intel_encoder->post_disable = intel_ddi_post_disable; 4309 intel_encoder->update_pipe = intel_ddi_update_pipe; 4310 intel_encoder->get_hw_state = intel_ddi_get_hw_state; 4311 intel_encoder->get_config = intel_ddi_get_config; 4312 intel_encoder->suspend = intel_dp_encoder_suspend; 4313 intel_encoder->get_power_domains = intel_ddi_get_power_domains; 4314 intel_encoder->type = INTEL_OUTPUT_DDI; 4315 intel_encoder->power_domain = intel_port_to_power_domain(port); 4316 intel_encoder->port = port; 4317 intel_encoder->cloneable = 0; 4318 for_each_pipe(dev_priv, pipe) 4319 intel_encoder->crtc_mask |= BIT(pipe); 4320 4321 if (INTEL_GEN(dev_priv) >= 11) 4322 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & 4323 DDI_BUF_PORT_REVERSAL; 4324 else 4325 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & 4326 (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 4327 intel_dig_port->dp.output_reg = INVALID_MMIO_REG; 4328 intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port); 4329 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 4330 4331 if (intel_phy_is_tc(dev_priv, phy)) { 4332 bool is_legacy = !port_info->supports_typec_usb && 4333 !port_info->supports_tbt; 4334 4335 intel_tc_port_init(intel_dig_port, is_legacy); 4336 4337 intel_encoder->update_prepare = intel_ddi_update_prepare; 4338 intel_encoder->update_complete = intel_ddi_update_complete; 4339 } 4340 4341 switch (port) { 4342 case PORT_A: 4343 intel_dig_port->ddi_io_power_domain = 4344 POWER_DOMAIN_PORT_DDI_A_IO; 4345 break; 4346 case PORT_B: 4347 intel_dig_port->ddi_io_power_domain = 4348 POWER_DOMAIN_PORT_DDI_B_IO; 4349 break; 4350 case PORT_C: 4351 intel_dig_port->ddi_io_power_domain = 4352 POWER_DOMAIN_PORT_DDI_C_IO; 4353 break; 4354 case PORT_D: 4355 intel_dig_port->ddi_io_power_domain = 4356 POWER_DOMAIN_PORT_DDI_D_IO; 4357 break; 4358 case PORT_E: 4359 intel_dig_port->ddi_io_power_domain = 4360 POWER_DOMAIN_PORT_DDI_E_IO; 4361 break; 4362 case PORT_F: 4363 intel_dig_port->ddi_io_power_domain = 4364 POWER_DOMAIN_PORT_DDI_F_IO; 4365 break; 4366 case PORT_G: 4367 intel_dig_port->ddi_io_power_domain = 4368 POWER_DOMAIN_PORT_DDI_G_IO; 4369 break; 4370 case PORT_H: 4371 intel_dig_port->ddi_io_power_domain = 4372 POWER_DOMAIN_PORT_DDI_H_IO; 4373 break; 4374 case PORT_I: 4375 intel_dig_port->ddi_io_power_domain = 4376 POWER_DOMAIN_PORT_DDI_I_IO; 4377 break; 4378 default: 4379 MISSING_CASE(port); 4380 } 4381 4382 if (init_dp) { 4383 if (!intel_ddi_init_dp_connector(intel_dig_port)) 4384 goto err; 4385 4386 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; 4387 } 4388 4389 /* In theory we don't need the encoder->type check, but leave it just in 4390 * case we have some really bad VBTs... */ 4391 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 4392 if (!intel_ddi_init_hdmi_connector(intel_dig_port)) 4393 goto err; 4394 } 4395 4396 if (init_lspcon) { 4397 if (lspcon_init(intel_dig_port)) 4398 /* TODO: handle hdmi info frame part */ 4399 DRM_DEBUG_KMS("LSPCON init success on port %c\n", 4400 port_name(port)); 4401 else 4402 /* 4403 * LSPCON init faied, but DP init was success, so 4404 * lets try to drive as DP++ port. 4405 */ 4406 DRM_ERROR("LSPCON init failed on port %c\n", 4407 port_name(port)); 4408 } 4409 4410 intel_infoframe_init(intel_dig_port); 4411 4412 return; 4413 4414 err: 4415 drm_encoder_cleanup(encoder); 4416 kfree(intel_dig_port); 4417 } 4418