1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <drm/drm_scdc_helper.h> 29 30 #include "i915_drv.h" 31 #include "intel_audio.h" 32 #include "intel_combo_phy.h" 33 #include "intel_connector.h" 34 #include "intel_ddi.h" 35 #include "intel_display_types.h" 36 #include "intel_dp.h" 37 #include "intel_dp_mst.h" 38 #include "intel_dp_link_training.h" 39 #include "intel_dpio_phy.h" 40 #include "intel_dsi.h" 41 #include "intel_fifo_underrun.h" 42 #include "intel_gmbus.h" 43 #include "intel_hdcp.h" 44 #include "intel_hdmi.h" 45 #include "intel_hotplug.h" 46 #include "intel_lspcon.h" 47 #include "intel_panel.h" 48 #include "intel_psr.h" 49 #include "intel_sprite.h" 50 #include "intel_tc.h" 51 #include "intel_vdsc.h" 52 53 struct ddi_buf_trans { 54 u32 trans1; /* balance leg enable, de-emph level */ 55 u32 trans2; /* vref sel, vswing */ 56 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */ 57 }; 58 59 static const u8 index_to_dp_signal_levels[] = { 60 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 61 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 62 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 63 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 64 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 65 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 66 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 67 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 68 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 69 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 70 }; 71 72 /* HDMI/DVI modes ignore everything but the last 2 items. So we share 73 * them for both DP and FDI transports, allowing those ports to 74 * automatically adapt to HDMI connections as well 75 */ 76 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { 77 { 0x00FFFFFF, 0x0006000E, 0x0 }, 78 { 0x00D75FFF, 0x0005000A, 0x0 }, 79 { 0x00C30FFF, 0x00040006, 0x0 }, 80 { 0x80AAAFFF, 0x000B0000, 0x0 }, 81 { 0x00FFFFFF, 0x0005000A, 0x0 }, 82 { 0x00D75FFF, 0x000C0004, 0x0 }, 83 { 0x80C30FFF, 0x000B0000, 0x0 }, 84 { 0x00FFFFFF, 0x00040006, 0x0 }, 85 { 0x80D75FFF, 0x000B0000, 0x0 }, 86 }; 87 88 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { 89 { 0x00FFFFFF, 0x0007000E, 0x0 }, 90 { 0x00D75FFF, 0x000F000A, 0x0 }, 91 { 0x00C30FFF, 0x00060006, 0x0 }, 92 { 0x00AAAFFF, 0x001E0000, 0x0 }, 93 { 0x00FFFFFF, 0x000F000A, 0x0 }, 94 { 0x00D75FFF, 0x00160004, 0x0 }, 95 { 0x00C30FFF, 0x001E0000, 0x0 }, 96 { 0x00FFFFFF, 0x00060006, 0x0 }, 97 { 0x00D75FFF, 0x001E0000, 0x0 }, 98 }; 99 100 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { 101 /* Idx NT mV d T mV d db */ 102 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */ 103 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */ 104 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */ 105 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */ 106 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */ 107 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */ 108 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */ 109 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */ 110 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */ 111 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */ 112 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */ 113 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */ 114 }; 115 116 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { 117 { 0x00FFFFFF, 0x00000012, 0x0 }, 118 { 0x00EBAFFF, 0x00020011, 0x0 }, 119 { 0x00C71FFF, 0x0006000F, 0x0 }, 120 { 0x00AAAFFF, 0x000E000A, 0x0 }, 121 { 0x00FFFFFF, 0x00020011, 0x0 }, 122 { 0x00DB6FFF, 0x0005000F, 0x0 }, 123 { 0x00BEEFFF, 0x000A000C, 0x0 }, 124 { 0x00FFFFFF, 0x0005000F, 0x0 }, 125 { 0x00DB6FFF, 0x000A000C, 0x0 }, 126 }; 127 128 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { 129 { 0x00FFFFFF, 0x0007000E, 0x0 }, 130 { 0x00D75FFF, 0x000E000A, 0x0 }, 131 { 0x00BEFFFF, 0x00140006, 0x0 }, 132 { 0x80B2CFFF, 0x001B0002, 0x0 }, 133 { 0x00FFFFFF, 0x000E000A, 0x0 }, 134 { 0x00DB6FFF, 0x00160005, 0x0 }, 135 { 0x80C71FFF, 0x001A0002, 0x0 }, 136 { 0x00F7DFFF, 0x00180004, 0x0 }, 137 { 0x80D75FFF, 0x001B0002, 0x0 }, 138 }; 139 140 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { 141 { 0x00FFFFFF, 0x0001000E, 0x0 }, 142 { 0x00D75FFF, 0x0004000A, 0x0 }, 143 { 0x00C30FFF, 0x00070006, 0x0 }, 144 { 0x00AAAFFF, 0x000C0000, 0x0 }, 145 { 0x00FFFFFF, 0x0004000A, 0x0 }, 146 { 0x00D75FFF, 0x00090004, 0x0 }, 147 { 0x00C30FFF, 0x000C0000, 0x0 }, 148 { 0x00FFFFFF, 0x00070006, 0x0 }, 149 { 0x00D75FFF, 0x000C0000, 0x0 }, 150 }; 151 152 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { 153 /* Idx NT mV d T mV df db */ 154 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */ 155 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */ 156 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */ 157 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */ 158 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */ 159 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */ 160 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */ 161 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */ 162 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */ 163 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */ 164 }; 165 166 /* Skylake H and S */ 167 static const struct ddi_buf_trans skl_ddi_translations_dp[] = { 168 { 0x00002016, 0x000000A0, 0x0 }, 169 { 0x00005012, 0x0000009B, 0x0 }, 170 { 0x00007011, 0x00000088, 0x0 }, 171 { 0x80009010, 0x000000C0, 0x1 }, 172 { 0x00002016, 0x0000009B, 0x0 }, 173 { 0x00005012, 0x00000088, 0x0 }, 174 { 0x80007011, 0x000000C0, 0x1 }, 175 { 0x00002016, 0x000000DF, 0x0 }, 176 { 0x80005012, 0x000000C0, 0x1 }, 177 }; 178 179 /* Skylake U */ 180 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { 181 { 0x0000201B, 0x000000A2, 0x0 }, 182 { 0x00005012, 0x00000088, 0x0 }, 183 { 0x80007011, 0x000000CD, 0x1 }, 184 { 0x80009010, 0x000000C0, 0x1 }, 185 { 0x0000201B, 0x0000009D, 0x0 }, 186 { 0x80005012, 0x000000C0, 0x1 }, 187 { 0x80007011, 0x000000C0, 0x1 }, 188 { 0x00002016, 0x00000088, 0x0 }, 189 { 0x80005012, 0x000000C0, 0x1 }, 190 }; 191 192 /* Skylake Y */ 193 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { 194 { 0x00000018, 0x000000A2, 0x0 }, 195 { 0x00005012, 0x00000088, 0x0 }, 196 { 0x80007011, 0x000000CD, 0x3 }, 197 { 0x80009010, 0x000000C0, 0x3 }, 198 { 0x00000018, 0x0000009D, 0x0 }, 199 { 0x80005012, 0x000000C0, 0x3 }, 200 { 0x80007011, 0x000000C0, 0x3 }, 201 { 0x00000018, 0x00000088, 0x0 }, 202 { 0x80005012, 0x000000C0, 0x3 }, 203 }; 204 205 /* Kabylake H and S */ 206 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = { 207 { 0x00002016, 0x000000A0, 0x0 }, 208 { 0x00005012, 0x0000009B, 0x0 }, 209 { 0x00007011, 0x00000088, 0x0 }, 210 { 0x80009010, 0x000000C0, 0x1 }, 211 { 0x00002016, 0x0000009B, 0x0 }, 212 { 0x00005012, 0x00000088, 0x0 }, 213 { 0x80007011, 0x000000C0, 0x1 }, 214 { 0x00002016, 0x00000097, 0x0 }, 215 { 0x80005012, 0x000000C0, 0x1 }, 216 }; 217 218 /* Kabylake U */ 219 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = { 220 { 0x0000201B, 0x000000A1, 0x0 }, 221 { 0x00005012, 0x00000088, 0x0 }, 222 { 0x80007011, 0x000000CD, 0x3 }, 223 { 0x80009010, 0x000000C0, 0x3 }, 224 { 0x0000201B, 0x0000009D, 0x0 }, 225 { 0x80005012, 0x000000C0, 0x3 }, 226 { 0x80007011, 0x000000C0, 0x3 }, 227 { 0x00002016, 0x0000004F, 0x0 }, 228 { 0x80005012, 0x000000C0, 0x3 }, 229 }; 230 231 /* Kabylake Y */ 232 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = { 233 { 0x00001017, 0x000000A1, 0x0 }, 234 { 0x00005012, 0x00000088, 0x0 }, 235 { 0x80007011, 0x000000CD, 0x3 }, 236 { 0x8000800F, 0x000000C0, 0x3 }, 237 { 0x00001017, 0x0000009D, 0x0 }, 238 { 0x80005012, 0x000000C0, 0x3 }, 239 { 0x80007011, 0x000000C0, 0x3 }, 240 { 0x00001017, 0x0000004C, 0x0 }, 241 { 0x80005012, 0x000000C0, 0x3 }, 242 }; 243 244 /* 245 * Skylake/Kabylake H and S 246 * eDP 1.4 low vswing translation parameters 247 */ 248 static const struct ddi_buf_trans skl_ddi_translations_edp[] = { 249 { 0x00000018, 0x000000A8, 0x0 }, 250 { 0x00004013, 0x000000A9, 0x0 }, 251 { 0x00007011, 0x000000A2, 0x0 }, 252 { 0x00009010, 0x0000009C, 0x0 }, 253 { 0x00000018, 0x000000A9, 0x0 }, 254 { 0x00006013, 0x000000A2, 0x0 }, 255 { 0x00007011, 0x000000A6, 0x0 }, 256 { 0x00000018, 0x000000AB, 0x0 }, 257 { 0x00007013, 0x0000009F, 0x0 }, 258 { 0x00000018, 0x000000DF, 0x0 }, 259 }; 260 261 /* 262 * Skylake/Kabylake U 263 * eDP 1.4 low vswing translation parameters 264 */ 265 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = { 266 { 0x00000018, 0x000000A8, 0x0 }, 267 { 0x00004013, 0x000000A9, 0x0 }, 268 { 0x00007011, 0x000000A2, 0x0 }, 269 { 0x00009010, 0x0000009C, 0x0 }, 270 { 0x00000018, 0x000000A9, 0x0 }, 271 { 0x00006013, 0x000000A2, 0x0 }, 272 { 0x00007011, 0x000000A6, 0x0 }, 273 { 0x00002016, 0x000000AB, 0x0 }, 274 { 0x00005013, 0x0000009F, 0x0 }, 275 { 0x00000018, 0x000000DF, 0x0 }, 276 }; 277 278 /* 279 * Skylake/Kabylake Y 280 * eDP 1.4 low vswing translation parameters 281 */ 282 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = { 283 { 0x00000018, 0x000000A8, 0x0 }, 284 { 0x00004013, 0x000000AB, 0x0 }, 285 { 0x00007011, 0x000000A4, 0x0 }, 286 { 0x00009010, 0x000000DF, 0x0 }, 287 { 0x00000018, 0x000000AA, 0x0 }, 288 { 0x00006013, 0x000000A4, 0x0 }, 289 { 0x00007011, 0x0000009D, 0x0 }, 290 { 0x00000018, 0x000000A0, 0x0 }, 291 { 0x00006012, 0x000000DF, 0x0 }, 292 { 0x00000018, 0x0000008A, 0x0 }, 293 }; 294 295 /* Skylake/Kabylake U, H and S */ 296 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { 297 { 0x00000018, 0x000000AC, 0x0 }, 298 { 0x00005012, 0x0000009D, 0x0 }, 299 { 0x00007011, 0x00000088, 0x0 }, 300 { 0x00000018, 0x000000A1, 0x0 }, 301 { 0x00000018, 0x00000098, 0x0 }, 302 { 0x00004013, 0x00000088, 0x0 }, 303 { 0x80006012, 0x000000CD, 0x1 }, 304 { 0x00000018, 0x000000DF, 0x0 }, 305 { 0x80003015, 0x000000CD, 0x1 }, /* Default */ 306 { 0x80003015, 0x000000C0, 0x1 }, 307 { 0x80000018, 0x000000C0, 0x1 }, 308 }; 309 310 /* Skylake/Kabylake Y */ 311 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { 312 { 0x00000018, 0x000000A1, 0x0 }, 313 { 0x00005012, 0x000000DF, 0x0 }, 314 { 0x80007011, 0x000000CB, 0x3 }, 315 { 0x00000018, 0x000000A4, 0x0 }, 316 { 0x00000018, 0x0000009D, 0x0 }, 317 { 0x00004013, 0x00000080, 0x0 }, 318 { 0x80006013, 0x000000C0, 0x3 }, 319 { 0x00000018, 0x0000008A, 0x0 }, 320 { 0x80003015, 0x000000C0, 0x3 }, /* Default */ 321 { 0x80003015, 0x000000C0, 0x3 }, 322 { 0x80000018, 0x000000C0, 0x3 }, 323 }; 324 325 struct bxt_ddi_buf_trans { 326 u8 margin; /* swing value */ 327 u8 scale; /* scale value */ 328 u8 enable; /* scale enable */ 329 u8 deemphasis; 330 }; 331 332 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { 333 /* Idx NT mV diff db */ 334 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ 335 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */ 336 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */ 337 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */ 338 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */ 339 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */ 340 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */ 341 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */ 342 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */ 343 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */ 344 }; 345 346 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = { 347 /* Idx NT mV diff db */ 348 { 26, 0, 0, 128, }, /* 0: 200 0 */ 349 { 38, 0, 0, 112, }, /* 1: 200 1.5 */ 350 { 48, 0, 0, 96, }, /* 2: 200 4 */ 351 { 54, 0, 0, 69, }, /* 3: 200 6 */ 352 { 32, 0, 0, 128, }, /* 4: 250 0 */ 353 { 48, 0, 0, 104, }, /* 5: 250 1.5 */ 354 { 54, 0, 0, 85, }, /* 6: 250 4 */ 355 { 43, 0, 0, 128, }, /* 7: 300 0 */ 356 { 54, 0, 0, 101, }, /* 8: 300 1.5 */ 357 { 48, 0, 0, 128, }, /* 9: 300 0 */ 358 }; 359 360 /* BSpec has 2 recommended values - entries 0 and 8. 361 * Using the entry with higher vswing. 362 */ 363 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = { 364 /* Idx NT mV diff db */ 365 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ 366 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */ 367 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */ 368 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */ 369 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */ 370 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */ 371 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */ 372 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */ 373 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */ 374 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */ 375 }; 376 377 struct cnl_ddi_buf_trans { 378 u8 dw2_swing_sel; 379 u8 dw7_n_scalar; 380 u8 dw4_cursor_coeff; 381 u8 dw4_post_cursor_2; 382 u8 dw4_post_cursor_1; 383 }; 384 385 /* Voltage Swing Programming for VccIO 0.85V for DP */ 386 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = { 387 /* NT mV Trans mV db */ 388 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 389 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ 390 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ 391 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ 392 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 393 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 394 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 395 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ 396 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ 397 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 398 }; 399 400 /* Voltage Swing Programming for VccIO 0.85V for HDMI */ 401 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = { 402 /* NT mV Trans mV db */ 403 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 404 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ 405 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ 406 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */ 407 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ 408 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ 409 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 410 }; 411 412 /* Voltage Swing Programming for VccIO 0.85V for eDP */ 413 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = { 414 /* NT mV Trans mV db */ 415 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 416 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 417 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 418 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 419 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 420 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 421 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */ 422 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */ 423 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 424 }; 425 426 /* Voltage Swing Programming for VccIO 0.95V for DP */ 427 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = { 428 /* NT mV Trans mV db */ 429 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 430 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ 431 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ 432 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ 433 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 434 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 435 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 436 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ 437 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ 438 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 439 }; 440 441 /* Voltage Swing Programming for VccIO 0.95V for HDMI */ 442 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = { 443 /* NT mV Trans mV db */ 444 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 445 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 446 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 447 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 448 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 449 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 450 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ 451 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ 452 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ 453 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ 454 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 455 }; 456 457 /* Voltage Swing Programming for VccIO 0.95V for eDP */ 458 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = { 459 /* NT mV Trans mV db */ 460 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 461 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 462 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 463 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 464 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 465 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 466 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ 467 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ 468 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */ 469 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 470 }; 471 472 /* Voltage Swing Programming for VccIO 1.05V for DP */ 473 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = { 474 /* NT mV Trans mV db */ 475 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 476 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 477 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 478 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */ 479 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 480 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 481 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */ 482 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */ 483 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */ 484 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 485 }; 486 487 /* Voltage Swing Programming for VccIO 1.05V for HDMI */ 488 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = { 489 /* NT mV Trans mV db */ 490 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 491 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 492 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 493 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 494 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 495 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 496 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ 497 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ 498 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ 499 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ 500 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 501 }; 502 503 /* Voltage Swing Programming for VccIO 1.05V for eDP */ 504 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = { 505 /* NT mV Trans mV db */ 506 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 507 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 508 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 509 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 510 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 511 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 512 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ 513 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ 514 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 515 }; 516 517 /* icl_combo_phy_ddi_translations */ 518 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = { 519 /* NT mV Trans mV db */ 520 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 521 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 522 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 523 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 524 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 525 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 526 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 527 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 528 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 529 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 530 }; 531 532 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = { 533 /* NT mV Trans mV db */ 534 { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ 535 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */ 536 { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */ 537 { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */ 538 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ 539 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */ 540 { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */ 541 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ 542 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ 543 { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 544 }; 545 546 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = { 547 /* NT mV Trans mV db */ 548 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 549 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 550 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 551 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 552 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 553 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 554 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 555 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 556 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 557 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 558 }; 559 560 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = { 561 /* NT mV Trans mV db */ 562 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 563 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ 564 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ 565 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */ 566 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ 567 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ 568 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 569 }; 570 571 static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_hbr2_hbr3[] = { 572 /* NT mV Trans mV db */ 573 { 0xA, 0x33, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 574 { 0xA, 0x47, 0x36, 0x00, 0x09 }, /* 350 500 3.1 */ 575 { 0xC, 0x64, 0x30, 0x00, 0x0F }, /* 350 700 6.0 */ 576 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 350 900 8.2 */ 577 { 0xA, 0x46, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 578 { 0xC, 0x64, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 579 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 580 { 0xC, 0x61, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */ 581 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 600 900 3.5 */ 582 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 583 }; 584 585 struct icl_mg_phy_ddi_buf_trans { 586 u32 cri_txdeemph_override_5_0; 587 u32 cri_txdeemph_override_11_6; 588 u32 cri_txdeemph_override_17_12; 589 }; 590 591 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = { 592 /* Voltage swing pre-emphasis */ 593 { 0x0, 0x1B, 0x00 }, /* 0 0 */ 594 { 0x0, 0x23, 0x08 }, /* 0 1 */ 595 { 0x0, 0x2D, 0x12 }, /* 0 2 */ 596 { 0x0, 0x00, 0x00 }, /* 0 3 */ 597 { 0x0, 0x23, 0x00 }, /* 1 0 */ 598 { 0x0, 0x2B, 0x09 }, /* 1 1 */ 599 { 0x0, 0x2E, 0x11 }, /* 1 2 */ 600 { 0x0, 0x2F, 0x00 }, /* 2 0 */ 601 { 0x0, 0x33, 0x0C }, /* 2 1 */ 602 { 0x0, 0x00, 0x00 }, /* 3 0 */ 603 }; 604 605 struct tgl_dkl_phy_ddi_buf_trans { 606 u32 dkl_vswing_control; 607 u32 dkl_preshoot_control; 608 u32 dkl_de_emphasis_control; 609 }; 610 611 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans[] = { 612 /* VS pre-emp Non-trans mV Pre-emph dB */ 613 { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */ 614 { 0x5, 0x0, 0x03 }, /* 0 1 400mV 3.5 dB */ 615 { 0x2, 0x0, 0x0b }, /* 0 2 400mV 6 dB */ 616 { 0x0, 0x0, 0x19 }, /* 0 3 400mV 9.5 dB */ 617 { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */ 618 { 0x2, 0x0, 0x03 }, /* 1 1 600mV 3.5 dB */ 619 { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */ 620 { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */ 621 { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */ 622 { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */ 623 }; 624 625 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_hdmi_ddi_trans[] = { 626 /* HDMI Preset VS Pre-emph */ 627 { 0x7, 0x0, 0x0 }, /* 1 400mV 0dB */ 628 { 0x6, 0x0, 0x0 }, /* 2 500mV 0dB */ 629 { 0x4, 0x0, 0x0 }, /* 3 650mV 0dB */ 630 { 0x2, 0x0, 0x0 }, /* 4 800mV 0dB */ 631 { 0x0, 0x0, 0x0 }, /* 5 1000mV 0dB */ 632 { 0x0, 0x0, 0x5 }, /* 6 Full -1.5 dB */ 633 { 0x0, 0x0, 0x6 }, /* 7 Full -1.8 dB */ 634 { 0x0, 0x0, 0x7 }, /* 8 Full -2 dB */ 635 { 0x0, 0x0, 0x8 }, /* 9 Full -2.5 dB */ 636 { 0x0, 0x0, 0xA }, /* 10 Full -3 dB */ 637 }; 638 639 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr[] = { 640 /* NT mV Trans mV db */ 641 { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 642 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 643 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 644 { 0x6, 0x7D, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 645 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 646 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 647 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 648 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 649 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 650 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 651 }; 652 653 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = { 654 /* NT mV Trans mV db */ 655 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 656 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 657 { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 658 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 659 { 0xA, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 660 { 0xC, 0x63, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 661 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 662 { 0xC, 0x61, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 663 { 0x6, 0x7B, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 664 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 665 }; 666 667 static const struct ddi_buf_trans * 668 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 669 { 670 if (dev_priv->vbt.edp.low_vswing) { 671 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp); 672 return bdw_ddi_translations_edp; 673 } else { 674 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 675 return bdw_ddi_translations_dp; 676 } 677 } 678 679 static const struct ddi_buf_trans * 680 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 681 { 682 if (IS_SKL_ULX(dev_priv)) { 683 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); 684 return skl_y_ddi_translations_dp; 685 } else if (IS_SKL_ULT(dev_priv)) { 686 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); 687 return skl_u_ddi_translations_dp; 688 } else { 689 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); 690 return skl_ddi_translations_dp; 691 } 692 } 693 694 static const struct ddi_buf_trans * 695 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 696 { 697 if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv)) { 698 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp); 699 return kbl_y_ddi_translations_dp; 700 } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) { 701 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp); 702 return kbl_u_ddi_translations_dp; 703 } else { 704 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp); 705 return kbl_ddi_translations_dp; 706 } 707 } 708 709 static const struct ddi_buf_trans * 710 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 711 { 712 if (dev_priv->vbt.edp.low_vswing) { 713 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || 714 IS_CFL_ULX(dev_priv)) { 715 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); 716 return skl_y_ddi_translations_edp; 717 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) || 718 IS_CFL_ULT(dev_priv)) { 719 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); 720 return skl_u_ddi_translations_edp; 721 } else { 722 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp); 723 return skl_ddi_translations_edp; 724 } 725 } 726 727 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) 728 return kbl_get_buf_trans_dp(dev_priv, n_entries); 729 else 730 return skl_get_buf_trans_dp(dev_priv, n_entries); 731 } 732 733 static const struct ddi_buf_trans * 734 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) 735 { 736 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || 737 IS_CFL_ULX(dev_priv)) { 738 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); 739 return skl_y_ddi_translations_hdmi; 740 } else { 741 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); 742 return skl_ddi_translations_hdmi; 743 } 744 } 745 746 static int skl_buf_trans_num_entries(enum port port, int n_entries) 747 { 748 /* Only DDIA and DDIE can select the 10th register with DP */ 749 if (port == PORT_A || port == PORT_E) 750 return min(n_entries, 10); 751 else 752 return min(n_entries, 9); 753 } 754 755 static const struct ddi_buf_trans * 756 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv, 757 enum port port, int *n_entries) 758 { 759 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) { 760 const struct ddi_buf_trans *ddi_translations = 761 kbl_get_buf_trans_dp(dev_priv, n_entries); 762 *n_entries = skl_buf_trans_num_entries(port, *n_entries); 763 return ddi_translations; 764 } else if (IS_SKYLAKE(dev_priv)) { 765 const struct ddi_buf_trans *ddi_translations = 766 skl_get_buf_trans_dp(dev_priv, n_entries); 767 *n_entries = skl_buf_trans_num_entries(port, *n_entries); 768 return ddi_translations; 769 } else if (IS_BROADWELL(dev_priv)) { 770 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 771 return bdw_ddi_translations_dp; 772 } else if (IS_HASWELL(dev_priv)) { 773 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 774 return hsw_ddi_translations_dp; 775 } 776 777 *n_entries = 0; 778 return NULL; 779 } 780 781 static const struct ddi_buf_trans * 782 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv, 783 enum port port, int *n_entries) 784 { 785 if (IS_GEN9_BC(dev_priv)) { 786 const struct ddi_buf_trans *ddi_translations = 787 skl_get_buf_trans_edp(dev_priv, n_entries); 788 *n_entries = skl_buf_trans_num_entries(port, *n_entries); 789 return ddi_translations; 790 } else if (IS_BROADWELL(dev_priv)) { 791 return bdw_get_buf_trans_edp(dev_priv, n_entries); 792 } else if (IS_HASWELL(dev_priv)) { 793 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 794 return hsw_ddi_translations_dp; 795 } 796 797 *n_entries = 0; 798 return NULL; 799 } 800 801 static const struct ddi_buf_trans * 802 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, 803 int *n_entries) 804 { 805 if (IS_BROADWELL(dev_priv)) { 806 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi); 807 return bdw_ddi_translations_fdi; 808 } else if (IS_HASWELL(dev_priv)) { 809 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi); 810 return hsw_ddi_translations_fdi; 811 } 812 813 *n_entries = 0; 814 return NULL; 815 } 816 817 static const struct ddi_buf_trans * 818 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, 819 int *n_entries) 820 { 821 if (IS_GEN9_BC(dev_priv)) { 822 return skl_get_buf_trans_hdmi(dev_priv, n_entries); 823 } else if (IS_BROADWELL(dev_priv)) { 824 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 825 return bdw_ddi_translations_hdmi; 826 } else if (IS_HASWELL(dev_priv)) { 827 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); 828 return hsw_ddi_translations_hdmi; 829 } 830 831 *n_entries = 0; 832 return NULL; 833 } 834 835 static const struct bxt_ddi_buf_trans * 836 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 837 { 838 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); 839 return bxt_ddi_translations_dp; 840 } 841 842 static const struct bxt_ddi_buf_trans * 843 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 844 { 845 if (dev_priv->vbt.edp.low_vswing) { 846 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp); 847 return bxt_ddi_translations_edp; 848 } 849 850 return bxt_get_buf_trans_dp(dev_priv, n_entries); 851 } 852 853 static const struct bxt_ddi_buf_trans * 854 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) 855 { 856 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); 857 return bxt_ddi_translations_hdmi; 858 } 859 860 static const struct cnl_ddi_buf_trans * 861 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) 862 { 863 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 864 865 if (voltage == VOLTAGE_INFO_0_85V) { 866 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V); 867 return cnl_ddi_translations_hdmi_0_85V; 868 } else if (voltage == VOLTAGE_INFO_0_95V) { 869 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V); 870 return cnl_ddi_translations_hdmi_0_95V; 871 } else if (voltage == VOLTAGE_INFO_1_05V) { 872 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V); 873 return cnl_ddi_translations_hdmi_1_05V; 874 } else { 875 *n_entries = 1; /* shut up gcc */ 876 MISSING_CASE(voltage); 877 } 878 return NULL; 879 } 880 881 static const struct cnl_ddi_buf_trans * 882 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 883 { 884 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 885 886 if (voltage == VOLTAGE_INFO_0_85V) { 887 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V); 888 return cnl_ddi_translations_dp_0_85V; 889 } else if (voltage == VOLTAGE_INFO_0_95V) { 890 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V); 891 return cnl_ddi_translations_dp_0_95V; 892 } else if (voltage == VOLTAGE_INFO_1_05V) { 893 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V); 894 return cnl_ddi_translations_dp_1_05V; 895 } else { 896 *n_entries = 1; /* shut up gcc */ 897 MISSING_CASE(voltage); 898 } 899 return NULL; 900 } 901 902 static const struct cnl_ddi_buf_trans * 903 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 904 { 905 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 906 907 if (dev_priv->vbt.edp.low_vswing) { 908 if (voltage == VOLTAGE_INFO_0_85V) { 909 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V); 910 return cnl_ddi_translations_edp_0_85V; 911 } else if (voltage == VOLTAGE_INFO_0_95V) { 912 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V); 913 return cnl_ddi_translations_edp_0_95V; 914 } else if (voltage == VOLTAGE_INFO_1_05V) { 915 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V); 916 return cnl_ddi_translations_edp_1_05V; 917 } else { 918 *n_entries = 1; /* shut up gcc */ 919 MISSING_CASE(voltage); 920 } 921 return NULL; 922 } else { 923 return cnl_get_buf_trans_dp(dev_priv, n_entries); 924 } 925 } 926 927 static const struct cnl_ddi_buf_trans * 928 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, 929 int *n_entries) 930 { 931 if (type == INTEL_OUTPUT_HDMI) { 932 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); 933 return icl_combo_phy_ddi_translations_hdmi; 934 } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) { 935 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3); 936 return icl_combo_phy_ddi_translations_edp_hbr3; 937 } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) { 938 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2); 939 return icl_combo_phy_ddi_translations_edp_hbr2; 940 } 941 942 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2); 943 return icl_combo_phy_ddi_translations_dp_hbr2; 944 } 945 946 static const struct cnl_ddi_buf_trans * 947 ehl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, 948 int *n_entries) 949 { 950 if (type != INTEL_OUTPUT_HDMI && type != INTEL_OUTPUT_EDP && 951 rate > 270000) { 952 *n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_hbr2_hbr3); 953 return ehl_combo_phy_ddi_translations_hbr2_hbr3; 954 } 955 956 return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries); 957 } 958 959 static const struct cnl_ddi_buf_trans * 960 tgl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, 961 int *n_entries) 962 { 963 if (type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_EDP) { 964 return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries); 965 } else if (rate > 270000) { 966 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2); 967 return tgl_combo_phy_ddi_translations_dp_hbr2; 968 } 969 970 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr); 971 return tgl_combo_phy_ddi_translations_dp_hbr; 972 } 973 974 static int intel_ddi_hdmi_level(struct intel_encoder *encoder) 975 { 976 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 977 int n_entries, level, default_entry; 978 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 979 980 if (INTEL_GEN(dev_priv) >= 12) { 981 if (intel_phy_is_combo(dev_priv, phy)) 982 tgl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 983 0, &n_entries); 984 else 985 n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans); 986 default_entry = n_entries - 1; 987 } else if (INTEL_GEN(dev_priv) == 11) { 988 if (intel_phy_is_combo(dev_priv, phy)) 989 icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 990 0, &n_entries); 991 else 992 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations); 993 default_entry = n_entries - 1; 994 } else if (IS_CANNONLAKE(dev_priv)) { 995 cnl_get_buf_trans_hdmi(dev_priv, &n_entries); 996 default_entry = n_entries - 1; 997 } else if (IS_GEN9_LP(dev_priv)) { 998 bxt_get_buf_trans_hdmi(dev_priv, &n_entries); 999 default_entry = n_entries - 1; 1000 } else if (IS_GEN9_BC(dev_priv)) { 1001 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 1002 default_entry = 8; 1003 } else if (IS_BROADWELL(dev_priv)) { 1004 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 1005 default_entry = 7; 1006 } else if (IS_HASWELL(dev_priv)) { 1007 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 1008 default_entry = 6; 1009 } else { 1010 drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n"); 1011 return 0; 1012 } 1013 1014 if (drm_WARN_ON_ONCE(&dev_priv->drm, n_entries == 0)) 1015 return 0; 1016 1017 level = intel_bios_hdmi_level_shift(encoder); 1018 if (level < 0) 1019 level = default_entry; 1020 1021 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 1022 level = n_entries - 1; 1023 1024 return level; 1025 } 1026 1027 /* 1028 * Starting with Haswell, DDI port buffers must be programmed with correct 1029 * values in advance. This function programs the correct values for 1030 * DP/eDP/FDI use cases. 1031 */ 1032 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 1033 const struct intel_crtc_state *crtc_state) 1034 { 1035 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1036 u32 iboost_bit = 0; 1037 int i, n_entries; 1038 enum port port = encoder->port; 1039 const struct ddi_buf_trans *ddi_translations; 1040 1041 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) 1042 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv, 1043 &n_entries); 1044 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1045 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, 1046 &n_entries); 1047 else 1048 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, 1049 &n_entries); 1050 1051 /* If we're boosting the current, set bit 31 of trans1 */ 1052 if (IS_GEN9_BC(dev_priv) && intel_bios_dp_boost_level(encoder)) 1053 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 1054 1055 for (i = 0; i < n_entries; i++) { 1056 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 1057 ddi_translations[i].trans1 | iboost_bit); 1058 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 1059 ddi_translations[i].trans2); 1060 } 1061 } 1062 1063 /* 1064 * Starting with Haswell, DDI port buffers must be programmed with correct 1065 * values in advance. This function programs the correct values for 1066 * HDMI/DVI use cases. 1067 */ 1068 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 1069 int level) 1070 { 1071 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1072 u32 iboost_bit = 0; 1073 int n_entries; 1074 enum port port = encoder->port; 1075 const struct ddi_buf_trans *ddi_translations; 1076 1077 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 1078 1079 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 1080 return; 1081 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 1082 level = n_entries - 1; 1083 1084 /* If we're boosting the current, set bit 31 of trans1 */ 1085 if (IS_GEN9_BC(dev_priv) && intel_bios_hdmi_boost_level(encoder)) 1086 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 1087 1088 /* Entry 9 is for HDMI: */ 1089 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 1090 ddi_translations[level].trans1 | iboost_bit); 1091 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 1092 ddi_translations[level].trans2); 1093 } 1094 1095 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 1096 enum port port) 1097 { 1098 i915_reg_t reg = DDI_BUF_CTL(port); 1099 int i; 1100 1101 for (i = 0; i < 16; i++) { 1102 udelay(1); 1103 if (intel_de_read(dev_priv, reg) & DDI_BUF_IS_IDLE) 1104 return; 1105 } 1106 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); 1107 } 1108 1109 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 1110 { 1111 switch (pll->info->id) { 1112 case DPLL_ID_WRPLL1: 1113 return PORT_CLK_SEL_WRPLL1; 1114 case DPLL_ID_WRPLL2: 1115 return PORT_CLK_SEL_WRPLL2; 1116 case DPLL_ID_SPLL: 1117 return PORT_CLK_SEL_SPLL; 1118 case DPLL_ID_LCPLL_810: 1119 return PORT_CLK_SEL_LCPLL_810; 1120 case DPLL_ID_LCPLL_1350: 1121 return PORT_CLK_SEL_LCPLL_1350; 1122 case DPLL_ID_LCPLL_2700: 1123 return PORT_CLK_SEL_LCPLL_2700; 1124 default: 1125 MISSING_CASE(pll->info->id); 1126 return PORT_CLK_SEL_NONE; 1127 } 1128 } 1129 1130 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 1131 const struct intel_crtc_state *crtc_state) 1132 { 1133 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1134 int clock = crtc_state->port_clock; 1135 const enum intel_dpll_id id = pll->info->id; 1136 1137 switch (id) { 1138 default: 1139 /* 1140 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 1141 * here, so do warn if this get passed in 1142 */ 1143 MISSING_CASE(id); 1144 return DDI_CLK_SEL_NONE; 1145 case DPLL_ID_ICL_TBTPLL: 1146 switch (clock) { 1147 case 162000: 1148 return DDI_CLK_SEL_TBT_162; 1149 case 270000: 1150 return DDI_CLK_SEL_TBT_270; 1151 case 540000: 1152 return DDI_CLK_SEL_TBT_540; 1153 case 810000: 1154 return DDI_CLK_SEL_TBT_810; 1155 default: 1156 MISSING_CASE(clock); 1157 return DDI_CLK_SEL_NONE; 1158 } 1159 case DPLL_ID_ICL_MGPLL1: 1160 case DPLL_ID_ICL_MGPLL2: 1161 case DPLL_ID_ICL_MGPLL3: 1162 case DPLL_ID_ICL_MGPLL4: 1163 case DPLL_ID_TGL_MGPLL5: 1164 case DPLL_ID_TGL_MGPLL6: 1165 return DDI_CLK_SEL_MG; 1166 } 1167 } 1168 1169 /* Starting with Haswell, different DDI ports can work in FDI mode for 1170 * connection to the PCH-located connectors. For this, it is necessary to train 1171 * both the DDI port and PCH receiver for the desired DDI buffer settings. 1172 * 1173 * The recommended port to work in FDI mode is DDI E, which we use here. Also, 1174 * please note that when FDI mode is active on DDI E, it shares 2 lines with 1175 * DDI A (which is used for eDP) 1176 */ 1177 1178 void hsw_fdi_link_train(struct intel_encoder *encoder, 1179 const struct intel_crtc_state *crtc_state) 1180 { 1181 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1182 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1183 u32 temp, i, rx_ctl_val, ddi_pll_sel; 1184 1185 intel_prepare_dp_ddi_buffers(encoder, crtc_state); 1186 1187 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the 1188 * mode set "sequence for CRT port" document: 1189 * - TP1 to TP2 time with the default value 1190 * - FDI delay to 90h 1191 * 1192 * WaFDIAutoLinkSetTimingOverrride:hsw 1193 */ 1194 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), 1195 FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 1196 1197 /* Enable the PCH Receiver FDI PLL */ 1198 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | 1199 FDI_RX_PLL_ENABLE | 1200 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); 1201 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 1202 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); 1203 udelay(220); 1204 1205 /* Switch from Rawclk to PCDclk */ 1206 rx_ctl_val |= FDI_PCDCLK; 1207 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 1208 1209 /* Configure Port Clock Select */ 1210 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll); 1211 intel_de_write(dev_priv, PORT_CLK_SEL(PORT_E), ddi_pll_sel); 1212 drm_WARN_ON(&dev_priv->drm, ddi_pll_sel != PORT_CLK_SEL_SPLL); 1213 1214 /* Start the training iterating through available voltages and emphasis, 1215 * testing each value twice. */ 1216 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { 1217 /* Configure DP_TP_CTL with auto-training */ 1218 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), 1219 DP_TP_CTL_FDI_AUTOTRAIN | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_ENABLE); 1220 1221 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. 1222 * DDI E does not support port reversal, the functionality is 1223 * achieved on the PCH side in FDI_RX_CTL, so no need to set the 1224 * port reversal bit */ 1225 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), 1226 DDI_BUF_CTL_ENABLE | ((crtc_state->fdi_lanes - 1) << 1) | DDI_BUF_TRANS_SELECT(i / 2)); 1227 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E)); 1228 1229 udelay(600); 1230 1231 /* Program PCH FDI Receiver TU */ 1232 intel_de_write(dev_priv, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); 1233 1234 /* Enable PCH FDI Receiver with auto-training */ 1235 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; 1236 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 1237 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); 1238 1239 /* Wait for FDI receiver lane calibration */ 1240 udelay(30); 1241 1242 /* Unset FDI_RX_MISC pwrdn lanes */ 1243 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1244 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 1245 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp); 1246 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1247 1248 /* Wait for FDI auto training time */ 1249 udelay(5); 1250 1251 temp = intel_de_read(dev_priv, DP_TP_STATUS(PORT_E)); 1252 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { 1253 DRM_DEBUG_KMS("FDI link training done on step %d\n", i); 1254 break; 1255 } 1256 1257 /* 1258 * Leave things enabled even if we failed to train FDI. 1259 * Results in less fireworks from the state checker. 1260 */ 1261 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) { 1262 DRM_ERROR("FDI link training failed!\n"); 1263 break; 1264 } 1265 1266 rx_ctl_val &= ~FDI_RX_ENABLE; 1267 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 1268 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); 1269 1270 temp = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E)); 1271 temp &= ~DDI_BUF_CTL_ENABLE; 1272 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), temp); 1273 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E)); 1274 1275 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ 1276 temp = intel_de_read(dev_priv, DP_TP_CTL(PORT_E)); 1277 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 1278 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 1279 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp); 1280 intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E)); 1281 1282 intel_wait_ddi_buf_idle(dev_priv, PORT_E); 1283 1284 /* Reset FDI_RX_MISC pwrdn lanes */ 1285 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1286 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 1287 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 1288 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp); 1289 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1290 } 1291 1292 /* Enable normal pixel sending for FDI */ 1293 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), 1294 DP_TP_CTL_FDI_AUTOTRAIN | DP_TP_CTL_LINK_TRAIN_NORMAL | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_ENABLE); 1295 } 1296 1297 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) 1298 { 1299 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1300 struct intel_digital_port *intel_dig_port = 1301 enc_to_dig_port(encoder); 1302 1303 intel_dp->DP = intel_dig_port->saved_port_bits | 1304 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); 1305 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); 1306 } 1307 1308 static struct intel_encoder * 1309 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc) 1310 { 1311 struct drm_device *dev = crtc->base.dev; 1312 struct intel_encoder *encoder, *ret = NULL; 1313 int num_encoders = 0; 1314 1315 for_each_encoder_on_crtc(dev, &crtc->base, encoder) { 1316 ret = encoder; 1317 num_encoders++; 1318 } 1319 1320 if (num_encoders != 1) 1321 drm_WARN(dev, 1, "%d encoders on crtc for pipe %c\n", 1322 num_encoders, 1323 pipe_name(crtc->pipe)); 1324 1325 BUG_ON(ret == NULL); 1326 return ret; 1327 } 1328 1329 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 1330 enum port port) 1331 { 1332 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 1333 1334 switch (val) { 1335 case DDI_CLK_SEL_NONE: 1336 return 0; 1337 case DDI_CLK_SEL_TBT_162: 1338 return 162000; 1339 case DDI_CLK_SEL_TBT_270: 1340 return 270000; 1341 case DDI_CLK_SEL_TBT_540: 1342 return 540000; 1343 case DDI_CLK_SEL_TBT_810: 1344 return 810000; 1345 default: 1346 MISSING_CASE(val); 1347 return 0; 1348 } 1349 } 1350 1351 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 1352 { 1353 int dotclock; 1354 1355 if (pipe_config->has_pch_encoder) 1356 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1357 &pipe_config->fdi_m_n); 1358 else if (intel_crtc_has_dp_encoder(pipe_config)) 1359 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1360 &pipe_config->dp_m_n); 1361 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) 1362 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp; 1363 else 1364 dotclock = pipe_config->port_clock; 1365 1366 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 1367 !intel_crtc_has_dp_encoder(pipe_config)) 1368 dotclock *= 2; 1369 1370 if (pipe_config->pixel_multiplier) 1371 dotclock /= pipe_config->pixel_multiplier; 1372 1373 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 1374 } 1375 1376 static void intel_ddi_clock_get(struct intel_encoder *encoder, 1377 struct intel_crtc_state *pipe_config) 1378 { 1379 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1380 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1381 1382 if (intel_phy_is_tc(dev_priv, phy) && 1383 intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll) == 1384 DPLL_ID_ICL_TBTPLL) 1385 pipe_config->port_clock = icl_calc_tbt_pll_link(dev_priv, 1386 encoder->port); 1387 else 1388 pipe_config->port_clock = 1389 intel_dpll_get_freq(dev_priv, pipe_config->shared_dpll); 1390 1391 ddi_dotclock_get(pipe_config); 1392 } 1393 1394 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 1395 const struct drm_connector_state *conn_state) 1396 { 1397 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1398 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1399 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1400 u32 temp; 1401 1402 if (!intel_crtc_has_dp_encoder(crtc_state)) 1403 return; 1404 1405 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 1406 1407 temp = DP_MSA_MISC_SYNC_CLOCK; 1408 1409 switch (crtc_state->pipe_bpp) { 1410 case 18: 1411 temp |= DP_MSA_MISC_6_BPC; 1412 break; 1413 case 24: 1414 temp |= DP_MSA_MISC_8_BPC; 1415 break; 1416 case 30: 1417 temp |= DP_MSA_MISC_10_BPC; 1418 break; 1419 case 36: 1420 temp |= DP_MSA_MISC_12_BPC; 1421 break; 1422 default: 1423 MISSING_CASE(crtc_state->pipe_bpp); 1424 break; 1425 } 1426 1427 /* nonsense combination */ 1428 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 1429 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 1430 1431 if (crtc_state->limited_color_range) 1432 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 1433 1434 /* 1435 * As per DP 1.2 spec section 2.3.4.3 while sending 1436 * YCBCR 444 signals we should program MSA MISC1/0 fields with 1437 * colorspace information. 1438 */ 1439 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 1440 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 1441 1442 /* 1443 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 1444 * of Color Encoding Format and Content Color Gamut] while sending 1445 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 1446 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 1447 */ 1448 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 1449 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 1450 1451 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp); 1452 } 1453 1454 /* 1455 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 1456 * 1457 * Only intended to be used by intel_ddi_enable_transcoder_func() and 1458 * intel_ddi_config_transcoder_func(). 1459 */ 1460 static u32 1461 intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state) 1462 { 1463 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1464 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc); 1465 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1466 enum pipe pipe = crtc->pipe; 1467 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1468 enum port port = encoder->port; 1469 u32 temp; 1470 1471 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 1472 temp = TRANS_DDI_FUNC_ENABLE; 1473 if (INTEL_GEN(dev_priv) >= 12) 1474 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 1475 else 1476 temp |= TRANS_DDI_SELECT_PORT(port); 1477 1478 switch (crtc_state->pipe_bpp) { 1479 case 18: 1480 temp |= TRANS_DDI_BPC_6; 1481 break; 1482 case 24: 1483 temp |= TRANS_DDI_BPC_8; 1484 break; 1485 case 30: 1486 temp |= TRANS_DDI_BPC_10; 1487 break; 1488 case 36: 1489 temp |= TRANS_DDI_BPC_12; 1490 break; 1491 default: 1492 BUG(); 1493 } 1494 1495 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 1496 temp |= TRANS_DDI_PVSYNC; 1497 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 1498 temp |= TRANS_DDI_PHSYNC; 1499 1500 if (cpu_transcoder == TRANSCODER_EDP) { 1501 switch (pipe) { 1502 case PIPE_A: 1503 /* On Haswell, can only use the always-on power well for 1504 * eDP when not using the panel fitter, and when not 1505 * using motion blur mitigation (which we don't 1506 * support). */ 1507 if (crtc_state->pch_pfit.force_thru) 1508 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 1509 else 1510 temp |= TRANS_DDI_EDP_INPUT_A_ON; 1511 break; 1512 case PIPE_B: 1513 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 1514 break; 1515 case PIPE_C: 1516 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 1517 break; 1518 default: 1519 BUG(); 1520 break; 1521 } 1522 } 1523 1524 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1525 if (crtc_state->has_hdmi_sink) 1526 temp |= TRANS_DDI_MODE_SELECT_HDMI; 1527 else 1528 temp |= TRANS_DDI_MODE_SELECT_DVI; 1529 1530 if (crtc_state->hdmi_scrambling) 1531 temp |= TRANS_DDI_HDMI_SCRAMBLING; 1532 if (crtc_state->hdmi_high_tmds_clock_ratio) 1533 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 1534 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 1535 temp |= TRANS_DDI_MODE_SELECT_FDI; 1536 temp |= (crtc_state->fdi_lanes - 1) << 1; 1537 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 1538 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 1539 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 1540 1541 if (INTEL_GEN(dev_priv) >= 12) { 1542 enum transcoder master; 1543 1544 master = crtc_state->mst_master_transcoder; 1545 drm_WARN_ON(&dev_priv->drm, 1546 master == INVALID_TRANSCODER); 1547 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 1548 } 1549 } else { 1550 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 1551 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 1552 } 1553 1554 return temp; 1555 } 1556 1557 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state) 1558 { 1559 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1560 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1561 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1562 u32 temp; 1563 1564 temp = intel_ddi_transcoder_func_reg_val_get(crtc_state); 1565 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 1566 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; 1567 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 1568 } 1569 1570 /* 1571 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 1572 * bit. 1573 */ 1574 static void 1575 intel_ddi_config_transcoder_func(const struct intel_crtc_state *crtc_state) 1576 { 1577 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1578 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1579 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1580 u32 temp; 1581 1582 temp = intel_ddi_transcoder_func_reg_val_get(crtc_state); 1583 temp &= ~TRANS_DDI_FUNC_ENABLE; 1584 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 1585 } 1586 1587 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 1588 { 1589 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1590 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1591 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1592 u32 val; 1593 1594 val = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1595 val &= ~TRANS_DDI_FUNC_ENABLE; 1596 1597 if (INTEL_GEN(dev_priv) >= 12) { 1598 if (!intel_dp_mst_is_master_trans(crtc_state)) { 1599 val &= ~(TGL_TRANS_DDI_PORT_MASK | 1600 TRANS_DDI_MODE_SELECT_MASK); 1601 } 1602 } else { 1603 val &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 1604 } 1605 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), val); 1606 1607 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME && 1608 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1609 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n"); 1610 /* Quirk time at 100ms for reliable operation */ 1611 msleep(100); 1612 } 1613 } 1614 1615 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder, 1616 bool enable) 1617 { 1618 struct drm_device *dev = intel_encoder->base.dev; 1619 struct drm_i915_private *dev_priv = to_i915(dev); 1620 intel_wakeref_t wakeref; 1621 enum pipe pipe = 0; 1622 int ret = 0; 1623 u32 tmp; 1624 1625 wakeref = intel_display_power_get_if_enabled(dev_priv, 1626 intel_encoder->power_domain); 1627 if (drm_WARN_ON(dev, !wakeref)) 1628 return -ENXIO; 1629 1630 if (drm_WARN_ON(dev, 1631 !intel_encoder->get_hw_state(intel_encoder, &pipe))) { 1632 ret = -EIO; 1633 goto out; 1634 } 1635 1636 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe)); 1637 if (enable) 1638 tmp |= TRANS_DDI_HDCP_SIGNALLING; 1639 else 1640 tmp &= ~TRANS_DDI_HDCP_SIGNALLING; 1641 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), tmp); 1642 out: 1643 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 1644 return ret; 1645 } 1646 1647 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 1648 { 1649 struct drm_device *dev = intel_connector->base.dev; 1650 struct drm_i915_private *dev_priv = to_i915(dev); 1651 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 1652 int type = intel_connector->base.connector_type; 1653 enum port port = encoder->port; 1654 enum transcoder cpu_transcoder; 1655 intel_wakeref_t wakeref; 1656 enum pipe pipe = 0; 1657 u32 tmp; 1658 bool ret; 1659 1660 wakeref = intel_display_power_get_if_enabled(dev_priv, 1661 encoder->power_domain); 1662 if (!wakeref) 1663 return false; 1664 1665 if (!encoder->get_hw_state(encoder, &pipe)) { 1666 ret = false; 1667 goto out; 1668 } 1669 1670 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) 1671 cpu_transcoder = TRANSCODER_EDP; 1672 else 1673 cpu_transcoder = (enum transcoder) pipe; 1674 1675 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1676 1677 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 1678 case TRANS_DDI_MODE_SELECT_HDMI: 1679 case TRANS_DDI_MODE_SELECT_DVI: 1680 ret = type == DRM_MODE_CONNECTOR_HDMIA; 1681 break; 1682 1683 case TRANS_DDI_MODE_SELECT_DP_SST: 1684 ret = type == DRM_MODE_CONNECTOR_eDP || 1685 type == DRM_MODE_CONNECTOR_DisplayPort; 1686 break; 1687 1688 case TRANS_DDI_MODE_SELECT_DP_MST: 1689 /* if the transcoder is in MST state then 1690 * connector isn't connected */ 1691 ret = false; 1692 break; 1693 1694 case TRANS_DDI_MODE_SELECT_FDI: 1695 ret = type == DRM_MODE_CONNECTOR_VGA; 1696 break; 1697 1698 default: 1699 ret = false; 1700 break; 1701 } 1702 1703 out: 1704 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1705 1706 return ret; 1707 } 1708 1709 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 1710 u8 *pipe_mask, bool *is_dp_mst) 1711 { 1712 struct drm_device *dev = encoder->base.dev; 1713 struct drm_i915_private *dev_priv = to_i915(dev); 1714 enum port port = encoder->port; 1715 intel_wakeref_t wakeref; 1716 enum pipe p; 1717 u32 tmp; 1718 u8 mst_pipe_mask; 1719 1720 *pipe_mask = 0; 1721 *is_dp_mst = false; 1722 1723 wakeref = intel_display_power_get_if_enabled(dev_priv, 1724 encoder->power_domain); 1725 if (!wakeref) 1726 return; 1727 1728 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 1729 if (!(tmp & DDI_BUF_CTL_ENABLE)) 1730 goto out; 1731 1732 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) { 1733 tmp = intel_de_read(dev_priv, 1734 TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 1735 1736 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 1737 default: 1738 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 1739 /* fallthrough */ 1740 case TRANS_DDI_EDP_INPUT_A_ON: 1741 case TRANS_DDI_EDP_INPUT_A_ONOFF: 1742 *pipe_mask = BIT(PIPE_A); 1743 break; 1744 case TRANS_DDI_EDP_INPUT_B_ONOFF: 1745 *pipe_mask = BIT(PIPE_B); 1746 break; 1747 case TRANS_DDI_EDP_INPUT_C_ONOFF: 1748 *pipe_mask = BIT(PIPE_C); 1749 break; 1750 } 1751 1752 goto out; 1753 } 1754 1755 mst_pipe_mask = 0; 1756 for_each_pipe(dev_priv, p) { 1757 enum transcoder cpu_transcoder = (enum transcoder)p; 1758 unsigned int port_mask, ddi_select; 1759 intel_wakeref_t trans_wakeref; 1760 1761 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 1762 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 1763 if (!trans_wakeref) 1764 continue; 1765 1766 if (INTEL_GEN(dev_priv) >= 12) { 1767 port_mask = TGL_TRANS_DDI_PORT_MASK; 1768 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 1769 } else { 1770 port_mask = TRANS_DDI_PORT_MASK; 1771 ddi_select = TRANS_DDI_SELECT_PORT(port); 1772 } 1773 1774 tmp = intel_de_read(dev_priv, 1775 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1776 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 1777 trans_wakeref); 1778 1779 if ((tmp & port_mask) != ddi_select) 1780 continue; 1781 1782 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == 1783 TRANS_DDI_MODE_SELECT_DP_MST) 1784 mst_pipe_mask |= BIT(p); 1785 1786 *pipe_mask |= BIT(p); 1787 } 1788 1789 if (!*pipe_mask) 1790 DRM_DEBUG_KMS("No pipe for [ENCODER:%d:%s] found\n", 1791 encoder->base.base.id, encoder->base.name); 1792 1793 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 1794 DRM_DEBUG_KMS("Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 1795 encoder->base.base.id, encoder->base.name, 1796 *pipe_mask); 1797 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 1798 } 1799 1800 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 1801 DRM_DEBUG_KMS("Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", 1802 encoder->base.base.id, encoder->base.name, 1803 *pipe_mask, mst_pipe_mask); 1804 else 1805 *is_dp_mst = mst_pipe_mask; 1806 1807 out: 1808 if (*pipe_mask && IS_GEN9_LP(dev_priv)) { 1809 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 1810 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 1811 BXT_PHY_LANE_POWERDOWN_ACK | 1812 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 1813 DRM_ERROR("[ENCODER:%d:%s] enabled but PHY powered down? " 1814 "(PHY_CTL %08x)\n", encoder->base.base.id, 1815 encoder->base.name, tmp); 1816 } 1817 1818 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1819 } 1820 1821 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 1822 enum pipe *pipe) 1823 { 1824 u8 pipe_mask; 1825 bool is_mst; 1826 1827 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 1828 1829 if (is_mst || !pipe_mask) 1830 return false; 1831 1832 *pipe = ffs(pipe_mask) - 1; 1833 1834 return true; 1835 } 1836 1837 static inline enum intel_display_power_domain 1838 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port) 1839 { 1840 /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with 1841 * DC states enabled at the same time, while for driver initiated AUX 1842 * transfers we need the same AUX IOs to be powered but with DC states 1843 * disabled. Accordingly use the AUX power domain here which leaves DC 1844 * states enabled. 1845 * However, for non-A AUX ports the corresponding non-EDP transcoders 1846 * would have already enabled power well 2 and DC_OFF. This means we can 1847 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a 1848 * specific AUX_IO reference without powering up any extra wells. 1849 * Note that PSR is enabled only on Port A even though this function 1850 * returns the correct domain for other ports too. 1851 */ 1852 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A : 1853 intel_aux_power_domain(dig_port); 1854 } 1855 1856 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 1857 struct intel_crtc_state *crtc_state) 1858 { 1859 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1860 struct intel_digital_port *dig_port; 1861 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1862 1863 /* 1864 * TODO: Add support for MST encoders. Atm, the following should never 1865 * happen since fake-MST encoders don't set their get_power_domains() 1866 * hook. 1867 */ 1868 if (drm_WARN_ON(&dev_priv->drm, 1869 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 1870 return; 1871 1872 dig_port = enc_to_dig_port(encoder); 1873 1874 if (!intel_phy_is_tc(dev_priv, phy) || 1875 dig_port->tc_mode != TC_PORT_TBT_ALT) 1876 intel_display_power_get(dev_priv, 1877 dig_port->ddi_io_power_domain); 1878 1879 /* 1880 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC 1881 * ports. 1882 */ 1883 if (intel_crtc_has_dp_encoder(crtc_state) || 1884 intel_phy_is_tc(dev_priv, phy)) 1885 intel_display_power_get(dev_priv, 1886 intel_ddi_main_link_aux_domain(dig_port)); 1887 1888 /* 1889 * VDSC power is needed when DSC is enabled 1890 */ 1891 if (crtc_state->dsc.compression_enable) 1892 intel_display_power_get(dev_priv, 1893 intel_dsc_power_domain(crtc_state)); 1894 } 1895 1896 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state) 1897 { 1898 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1899 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1900 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc); 1901 enum port port = encoder->port; 1902 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1903 1904 if (cpu_transcoder != TRANSCODER_EDP) { 1905 if (INTEL_GEN(dev_priv) >= 12) 1906 intel_de_write(dev_priv, 1907 TRANS_CLK_SEL(cpu_transcoder), 1908 TGL_TRANS_CLK_SEL_PORT(port)); 1909 else 1910 intel_de_write(dev_priv, 1911 TRANS_CLK_SEL(cpu_transcoder), 1912 TRANS_CLK_SEL_PORT(port)); 1913 } 1914 } 1915 1916 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state) 1917 { 1918 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1919 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1920 1921 if (cpu_transcoder != TRANSCODER_EDP) { 1922 if (INTEL_GEN(dev_priv) >= 12) 1923 intel_de_write(dev_priv, 1924 TRANS_CLK_SEL(cpu_transcoder), 1925 TGL_TRANS_CLK_SEL_DISABLED); 1926 else 1927 intel_de_write(dev_priv, 1928 TRANS_CLK_SEL(cpu_transcoder), 1929 TRANS_CLK_SEL_DISABLED); 1930 } 1931 } 1932 1933 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 1934 enum port port, u8 iboost) 1935 { 1936 u32 tmp; 1937 1938 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 1939 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 1940 if (iboost) 1941 tmp |= iboost << BALANCE_LEG_SHIFT(port); 1942 else 1943 tmp |= BALANCE_LEG_DISABLE(port); 1944 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 1945 } 1946 1947 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 1948 int level, enum intel_output_type type) 1949 { 1950 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 1951 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1952 enum port port = encoder->port; 1953 u8 iboost; 1954 1955 if (type == INTEL_OUTPUT_HDMI) 1956 iboost = intel_bios_hdmi_boost_level(encoder); 1957 else 1958 iboost = intel_bios_dp_boost_level(encoder); 1959 1960 if (iboost == 0) { 1961 const struct ddi_buf_trans *ddi_translations; 1962 int n_entries; 1963 1964 if (type == INTEL_OUTPUT_HDMI) 1965 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 1966 else if (type == INTEL_OUTPUT_EDP) 1967 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries); 1968 else 1969 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries); 1970 1971 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 1972 return; 1973 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 1974 level = n_entries - 1; 1975 1976 iboost = ddi_translations[level].i_boost; 1977 } 1978 1979 /* Make sure that the requested I_boost is valid */ 1980 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 1981 DRM_ERROR("Invalid I_boost value %u\n", iboost); 1982 return; 1983 } 1984 1985 _skl_ddi_set_iboost(dev_priv, port, iboost); 1986 1987 if (port == PORT_A && intel_dig_port->max_lanes == 4) 1988 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 1989 } 1990 1991 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, 1992 int level, enum intel_output_type type) 1993 { 1994 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1995 const struct bxt_ddi_buf_trans *ddi_translations; 1996 enum port port = encoder->port; 1997 int n_entries; 1998 1999 if (type == INTEL_OUTPUT_HDMI) 2000 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries); 2001 else if (type == INTEL_OUTPUT_EDP) 2002 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries); 2003 else 2004 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries); 2005 2006 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 2007 return; 2008 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 2009 level = n_entries - 1; 2010 2011 bxt_ddi_phy_set_signal_level(dev_priv, port, 2012 ddi_translations[level].margin, 2013 ddi_translations[level].scale, 2014 ddi_translations[level].enable, 2015 ddi_translations[level].deemphasis); 2016 } 2017 2018 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder) 2019 { 2020 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2021 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2022 enum port port = encoder->port; 2023 enum phy phy = intel_port_to_phy(dev_priv, port); 2024 int n_entries; 2025 2026 if (INTEL_GEN(dev_priv) >= 12) { 2027 if (intel_phy_is_combo(dev_priv, phy)) 2028 tgl_get_combo_buf_trans(dev_priv, encoder->type, 2029 intel_dp->link_rate, &n_entries); 2030 else 2031 n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans); 2032 } else if (INTEL_GEN(dev_priv) == 11) { 2033 if (IS_ELKHARTLAKE(dev_priv)) 2034 ehl_get_combo_buf_trans(dev_priv, encoder->type, 2035 intel_dp->link_rate, &n_entries); 2036 else if (intel_phy_is_combo(dev_priv, phy)) 2037 icl_get_combo_buf_trans(dev_priv, encoder->type, 2038 intel_dp->link_rate, &n_entries); 2039 else 2040 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations); 2041 } else if (IS_CANNONLAKE(dev_priv)) { 2042 if (encoder->type == INTEL_OUTPUT_EDP) 2043 cnl_get_buf_trans_edp(dev_priv, &n_entries); 2044 else 2045 cnl_get_buf_trans_dp(dev_priv, &n_entries); 2046 } else if (IS_GEN9_LP(dev_priv)) { 2047 if (encoder->type == INTEL_OUTPUT_EDP) 2048 bxt_get_buf_trans_edp(dev_priv, &n_entries); 2049 else 2050 bxt_get_buf_trans_dp(dev_priv, &n_entries); 2051 } else { 2052 if (encoder->type == INTEL_OUTPUT_EDP) 2053 intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries); 2054 else 2055 intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries); 2056 } 2057 2058 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 2059 n_entries = 1; 2060 if (drm_WARN_ON(&dev_priv->drm, 2061 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 2062 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 2063 2064 return index_to_dp_signal_levels[n_entries - 1] & 2065 DP_TRAIN_VOLTAGE_SWING_MASK; 2066 } 2067 2068 /* 2069 * We assume that the full set of pre-emphasis values can be 2070 * used on all DDI platforms. Should that change we need to 2071 * rethink this code. 2072 */ 2073 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing) 2074 { 2075 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2076 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2077 return DP_TRAIN_PRE_EMPH_LEVEL_3; 2078 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 2079 return DP_TRAIN_PRE_EMPH_LEVEL_2; 2080 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 2081 return DP_TRAIN_PRE_EMPH_LEVEL_1; 2082 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 2083 default: 2084 return DP_TRAIN_PRE_EMPH_LEVEL_0; 2085 } 2086 } 2087 2088 static void cnl_ddi_vswing_program(struct intel_encoder *encoder, 2089 int level, enum intel_output_type type) 2090 { 2091 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2092 const struct cnl_ddi_buf_trans *ddi_translations; 2093 enum port port = encoder->port; 2094 int n_entries, ln; 2095 u32 val; 2096 2097 if (type == INTEL_OUTPUT_HDMI) 2098 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries); 2099 else if (type == INTEL_OUTPUT_EDP) 2100 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries); 2101 else 2102 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries); 2103 2104 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 2105 return; 2106 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 2107 level = n_entries - 1; 2108 2109 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */ 2110 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 2111 val &= ~SCALING_MODE_SEL_MASK; 2112 val |= SCALING_MODE_SEL(2); 2113 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 2114 2115 /* Program PORT_TX_DW2 */ 2116 val = intel_de_read(dev_priv, CNL_PORT_TX_DW2_LN0(port)); 2117 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 2118 RCOMP_SCALAR_MASK); 2119 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); 2120 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); 2121 /* Rcomp scalar is fixed as 0x98 for every table entry */ 2122 val |= RCOMP_SCALAR(0x98); 2123 intel_de_write(dev_priv, CNL_PORT_TX_DW2_GRP(port), val); 2124 2125 /* Program PORT_TX_DW4 */ 2126 /* We cannot write to GRP. It would overrite individual loadgen */ 2127 for (ln = 0; ln < 4; ln++) { 2128 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port)); 2129 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 2130 CURSOR_COEFF_MASK); 2131 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); 2132 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); 2133 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); 2134 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val); 2135 } 2136 2137 /* Program PORT_TX_DW5 */ 2138 /* All DW5 values are fixed for every table entry */ 2139 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 2140 val &= ~RTERM_SELECT_MASK; 2141 val |= RTERM_SELECT(6); 2142 val |= TAP3_DISABLE; 2143 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 2144 2145 /* Program PORT_TX_DW7 */ 2146 val = intel_de_read(dev_priv, CNL_PORT_TX_DW7_LN0(port)); 2147 val &= ~N_SCALAR_MASK; 2148 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); 2149 intel_de_write(dev_priv, CNL_PORT_TX_DW7_GRP(port), val); 2150 } 2151 2152 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, 2153 int level, enum intel_output_type type) 2154 { 2155 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2156 enum port port = encoder->port; 2157 int width, rate, ln; 2158 u32 val; 2159 2160 if (type == INTEL_OUTPUT_HDMI) { 2161 width = 4; 2162 rate = 0; /* Rate is always < than 6GHz for HDMI */ 2163 } else { 2164 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2165 2166 width = intel_dp->lane_count; 2167 rate = intel_dp->link_rate; 2168 } 2169 2170 /* 2171 * 1. If port type is eDP or DP, 2172 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 2173 * else clear to 0b. 2174 */ 2175 val = intel_de_read(dev_priv, CNL_PORT_PCS_DW1_LN0(port)); 2176 if (type != INTEL_OUTPUT_HDMI) 2177 val |= COMMON_KEEPER_EN; 2178 else 2179 val &= ~COMMON_KEEPER_EN; 2180 intel_de_write(dev_priv, CNL_PORT_PCS_DW1_GRP(port), val); 2181 2182 /* 2. Program loadgen select */ 2183 /* 2184 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes 2185 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2186 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2187 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 2188 */ 2189 for (ln = 0; ln <= 3; ln++) { 2190 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port)); 2191 val &= ~LOADGEN_SELECT; 2192 2193 if ((rate <= 600000 && width == 4 && ln >= 1) || 2194 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { 2195 val |= LOADGEN_SELECT; 2196 } 2197 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val); 2198 } 2199 2200 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 2201 val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5); 2202 val |= SUS_CLOCK_CONFIG; 2203 intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val); 2204 2205 /* 4. Clear training enable to change swing values */ 2206 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 2207 val &= ~TX_TRAINING_EN; 2208 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 2209 2210 /* 5. Program swing and de-emphasis */ 2211 cnl_ddi_vswing_program(encoder, level, type); 2212 2213 /* 6. Set training enable to trigger update */ 2214 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 2215 val |= TX_TRAINING_EN; 2216 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 2217 } 2218 2219 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, 2220 u32 level, enum phy phy, int type, 2221 int rate) 2222 { 2223 const struct cnl_ddi_buf_trans *ddi_translations = NULL; 2224 u32 n_entries, val; 2225 int ln; 2226 2227 if (INTEL_GEN(dev_priv) >= 12) 2228 ddi_translations = tgl_get_combo_buf_trans(dev_priv, type, rate, 2229 &n_entries); 2230 else if (IS_ELKHARTLAKE(dev_priv)) 2231 ddi_translations = ehl_get_combo_buf_trans(dev_priv, type, rate, 2232 &n_entries); 2233 else 2234 ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate, 2235 &n_entries); 2236 if (!ddi_translations) 2237 return; 2238 2239 if (level >= n_entries) { 2240 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1); 2241 level = n_entries - 1; 2242 } 2243 2244 /* Set PORT_TX_DW5 */ 2245 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 2246 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 2247 TAP2_DISABLE | TAP3_DISABLE); 2248 val |= SCALING_MODE_SEL(0x2); 2249 val |= RTERM_SELECT(0x6); 2250 val |= TAP3_DISABLE; 2251 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 2252 2253 /* Program PORT_TX_DW2 */ 2254 val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy)); 2255 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 2256 RCOMP_SCALAR_MASK); 2257 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); 2258 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); 2259 /* Program Rcomp scalar for every table entry */ 2260 val |= RCOMP_SCALAR(0x98); 2261 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val); 2262 2263 /* Program PORT_TX_DW4 */ 2264 /* We cannot write to GRP. It would overwrite individual loadgen. */ 2265 for (ln = 0; ln <= 3; ln++) { 2266 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy)); 2267 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 2268 CURSOR_COEFF_MASK); 2269 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); 2270 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); 2271 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); 2272 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val); 2273 } 2274 2275 /* Program PORT_TX_DW7 */ 2276 val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy)); 2277 val &= ~N_SCALAR_MASK; 2278 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); 2279 intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val); 2280 } 2281 2282 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 2283 u32 level, 2284 enum intel_output_type type) 2285 { 2286 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2287 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2288 int width = 0; 2289 int rate = 0; 2290 u32 val; 2291 int ln = 0; 2292 2293 if (type == INTEL_OUTPUT_HDMI) { 2294 width = 4; 2295 /* Rate is always < than 6GHz for HDMI */ 2296 } else { 2297 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2298 2299 width = intel_dp->lane_count; 2300 rate = intel_dp->link_rate; 2301 } 2302 2303 /* 2304 * 1. If port type is eDP or DP, 2305 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 2306 * else clear to 0b. 2307 */ 2308 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy)); 2309 if (type == INTEL_OUTPUT_HDMI) 2310 val &= ~COMMON_KEEPER_EN; 2311 else 2312 val |= COMMON_KEEPER_EN; 2313 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 2314 2315 /* 2. Program loadgen select */ 2316 /* 2317 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes 2318 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2319 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2320 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 2321 */ 2322 for (ln = 0; ln <= 3; ln++) { 2323 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy)); 2324 val &= ~LOADGEN_SELECT; 2325 2326 if ((rate <= 600000 && width == 4 && ln >= 1) || 2327 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { 2328 val |= LOADGEN_SELECT; 2329 } 2330 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val); 2331 } 2332 2333 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 2334 val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); 2335 val |= SUS_CLOCK_CONFIG; 2336 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val); 2337 2338 /* 4. Clear training enable to change swing values */ 2339 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 2340 val &= ~TX_TRAINING_EN; 2341 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 2342 2343 /* 5. Program swing and de-emphasis */ 2344 icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate); 2345 2346 /* 6. Set training enable to trigger update */ 2347 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 2348 val |= TX_TRAINING_EN; 2349 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 2350 } 2351 2352 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 2353 int link_clock, 2354 u32 level) 2355 { 2356 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2357 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 2358 const struct icl_mg_phy_ddi_buf_trans *ddi_translations; 2359 u32 n_entries, val; 2360 int ln; 2361 2362 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations); 2363 ddi_translations = icl_mg_phy_ddi_translations; 2364 /* The table does not have values for level 3 and level 9. */ 2365 if (level >= n_entries || level == 3 || level == 9) { 2366 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", 2367 level, n_entries - 2); 2368 level = n_entries - 2; 2369 } 2370 2371 /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */ 2372 for (ln = 0; ln < 2; ln++) { 2373 val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port)); 2374 val &= ~CRI_USE_FS32; 2375 intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), val); 2376 2377 val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port)); 2378 val &= ~CRI_USE_FS32; 2379 intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), val); 2380 } 2381 2382 /* Program MG_TX_SWINGCTRL with values from vswing table */ 2383 for (ln = 0; ln < 2; ln++) { 2384 val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port)); 2385 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; 2386 val |= CRI_TXDEEMPH_OVERRIDE_17_12( 2387 ddi_translations[level].cri_txdeemph_override_17_12); 2388 intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val); 2389 2390 val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port)); 2391 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; 2392 val |= CRI_TXDEEMPH_OVERRIDE_17_12( 2393 ddi_translations[level].cri_txdeemph_override_17_12); 2394 intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val); 2395 } 2396 2397 /* Program MG_TX_DRVCTRL with values from vswing table */ 2398 for (ln = 0; ln < 2; ln++) { 2399 val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port)); 2400 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 2401 CRI_TXDEEMPH_OVERRIDE_5_0_MASK); 2402 val |= CRI_TXDEEMPH_OVERRIDE_5_0( 2403 ddi_translations[level].cri_txdeemph_override_5_0) | 2404 CRI_TXDEEMPH_OVERRIDE_11_6( 2405 ddi_translations[level].cri_txdeemph_override_11_6) | 2406 CRI_TXDEEMPH_OVERRIDE_EN; 2407 intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val); 2408 2409 val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port)); 2410 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 2411 CRI_TXDEEMPH_OVERRIDE_5_0_MASK); 2412 val |= CRI_TXDEEMPH_OVERRIDE_5_0( 2413 ddi_translations[level].cri_txdeemph_override_5_0) | 2414 CRI_TXDEEMPH_OVERRIDE_11_6( 2415 ddi_translations[level].cri_txdeemph_override_11_6) | 2416 CRI_TXDEEMPH_OVERRIDE_EN; 2417 intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val); 2418 2419 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 2420 } 2421 2422 /* 2423 * Program MG_CLKHUB<LN, port being used> with value from frequency table 2424 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 2425 * values from table for which TX1 and TX2 enabled. 2426 */ 2427 for (ln = 0; ln < 2; ln++) { 2428 val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port)); 2429 if (link_clock < 300000) 2430 val |= CFG_LOW_RATE_LKREN_EN; 2431 else 2432 val &= ~CFG_LOW_RATE_LKREN_EN; 2433 intel_de_write(dev_priv, MG_CLKHUB(ln, tc_port), val); 2434 } 2435 2436 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 2437 for (ln = 0; ln < 2; ln++) { 2438 val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port)); 2439 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; 2440 if (link_clock <= 500000) { 2441 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; 2442 } else { 2443 val |= CFG_AMI_CK_DIV_OVERRIDE_EN | 2444 CFG_AMI_CK_DIV_OVERRIDE_VAL(1); 2445 } 2446 intel_de_write(dev_priv, MG_TX1_DCC(ln, tc_port), val); 2447 2448 val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port)); 2449 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; 2450 if (link_clock <= 500000) { 2451 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; 2452 } else { 2453 val |= CFG_AMI_CK_DIV_OVERRIDE_EN | 2454 CFG_AMI_CK_DIV_OVERRIDE_VAL(1); 2455 } 2456 intel_de_write(dev_priv, MG_TX2_DCC(ln, tc_port), val); 2457 } 2458 2459 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 2460 for (ln = 0; ln < 2; ln++) { 2461 val = intel_de_read(dev_priv, 2462 MG_TX1_PISO_READLOAD(ln, tc_port)); 2463 val |= CRI_CALCINIT; 2464 intel_de_write(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 2465 val); 2466 2467 val = intel_de_read(dev_priv, 2468 MG_TX2_PISO_READLOAD(ln, tc_port)); 2469 val |= CRI_CALCINIT; 2470 intel_de_write(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 2471 val); 2472 } 2473 } 2474 2475 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder, 2476 int link_clock, 2477 u32 level, 2478 enum intel_output_type type) 2479 { 2480 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2481 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2482 2483 if (intel_phy_is_combo(dev_priv, phy)) 2484 icl_combo_phy_ddi_vswing_sequence(encoder, level, type); 2485 else 2486 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level); 2487 } 2488 2489 static void 2490 tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock, 2491 u32 level) 2492 { 2493 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2494 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 2495 const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations; 2496 u32 n_entries, val, ln, dpcnt_mask, dpcnt_val; 2497 2498 if (encoder->type == INTEL_OUTPUT_HDMI) { 2499 n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans); 2500 ddi_translations = tgl_dkl_phy_hdmi_ddi_trans; 2501 } else { 2502 n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans); 2503 ddi_translations = tgl_dkl_phy_dp_ddi_trans; 2504 } 2505 2506 if (level >= n_entries) 2507 level = n_entries - 1; 2508 2509 dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK | 2510 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 2511 DKL_TX_VSWING_CONTROL_MASK); 2512 dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control); 2513 dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control); 2514 dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control); 2515 2516 for (ln = 0; ln < 2; ln++) { 2517 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2518 HIP_INDEX_VAL(tc_port, ln)); 2519 2520 intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0); 2521 2522 /* All the registers are RMW */ 2523 val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(tc_port)); 2524 val &= ~dpcnt_mask; 2525 val |= dpcnt_val; 2526 intel_de_write(dev_priv, DKL_TX_DPCNTL0(tc_port), val); 2527 2528 val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(tc_port)); 2529 val &= ~dpcnt_mask; 2530 val |= dpcnt_val; 2531 intel_de_write(dev_priv, DKL_TX_DPCNTL1(tc_port), val); 2532 2533 val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port)); 2534 val &= ~DKL_TX_DP20BITMODE; 2535 intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val); 2536 } 2537 } 2538 2539 static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder, 2540 int link_clock, 2541 u32 level, 2542 enum intel_output_type type) 2543 { 2544 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2545 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2546 2547 if (intel_phy_is_combo(dev_priv, phy)) 2548 icl_combo_phy_ddi_vswing_sequence(encoder, level, type); 2549 else 2550 tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level); 2551 } 2552 2553 static u32 translate_signal_level(int signal_levels) 2554 { 2555 int i; 2556 2557 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 2558 if (index_to_dp_signal_levels[i] == signal_levels) 2559 return i; 2560 } 2561 2562 WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 2563 signal_levels); 2564 2565 return 0; 2566 } 2567 2568 static u32 intel_ddi_dp_level(struct intel_dp *intel_dp) 2569 { 2570 u8 train_set = intel_dp->train_set[0]; 2571 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2572 DP_TRAIN_PRE_EMPHASIS_MASK); 2573 2574 return translate_signal_level(signal_levels); 2575 } 2576 2577 u32 bxt_signal_levels(struct intel_dp *intel_dp) 2578 { 2579 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2580 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); 2581 struct intel_encoder *encoder = &dport->base; 2582 int level = intel_ddi_dp_level(intel_dp); 2583 2584 if (INTEL_GEN(dev_priv) >= 12) 2585 tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate, 2586 level, encoder->type); 2587 else if (INTEL_GEN(dev_priv) >= 11) 2588 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate, 2589 level, encoder->type); 2590 else if (IS_CANNONLAKE(dev_priv)) 2591 cnl_ddi_vswing_sequence(encoder, level, encoder->type); 2592 else 2593 bxt_ddi_vswing_sequence(encoder, level, encoder->type); 2594 2595 return 0; 2596 } 2597 2598 u32 ddi_signal_levels(struct intel_dp *intel_dp) 2599 { 2600 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2601 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); 2602 struct intel_encoder *encoder = &dport->base; 2603 int level = intel_ddi_dp_level(intel_dp); 2604 2605 if (IS_GEN9_BC(dev_priv)) 2606 skl_ddi_set_iboost(encoder, level, encoder->type); 2607 2608 return DDI_BUF_TRANS_SELECT(level); 2609 } 2610 2611 static inline 2612 u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv, 2613 enum phy phy) 2614 { 2615 if (intel_phy_is_combo(dev_priv, phy)) { 2616 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 2617 } else if (intel_phy_is_tc(dev_priv, phy)) { 2618 enum tc_port tc_port = intel_port_to_tc(dev_priv, 2619 (enum port)phy); 2620 2621 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port); 2622 } 2623 2624 return 0; 2625 } 2626 2627 static void icl_map_plls_to_ports(struct intel_encoder *encoder, 2628 const struct intel_crtc_state *crtc_state) 2629 { 2630 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2631 struct intel_shared_dpll *pll = crtc_state->shared_dpll; 2632 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2633 u32 val; 2634 2635 mutex_lock(&dev_priv->dpll.lock); 2636 2637 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 2638 drm_WARN_ON(&dev_priv->drm, 2639 (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0); 2640 2641 if (intel_phy_is_combo(dev_priv, phy)) { 2642 /* 2643 * Even though this register references DDIs, note that we 2644 * want to pass the PHY rather than the port (DDI). For 2645 * ICL, port=phy in all cases so it doesn't matter, but for 2646 * EHL the bspec notes the following: 2647 * 2648 * "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA 2649 * Clock Select chooses the PLL for both DDIA and DDID and 2650 * drives port A in all cases." 2651 */ 2652 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 2653 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 2654 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 2655 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); 2656 } 2657 2658 val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 2659 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 2660 2661 mutex_unlock(&dev_priv->dpll.lock); 2662 } 2663 2664 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder) 2665 { 2666 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2667 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2668 u32 val; 2669 2670 mutex_lock(&dev_priv->dpll.lock); 2671 2672 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 2673 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 2674 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 2675 2676 mutex_unlock(&dev_priv->dpll.lock); 2677 } 2678 2679 static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv, 2680 u32 port_mask, bool ddi_clk_needed) 2681 { 2682 enum port port; 2683 u32 val; 2684 2685 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 2686 for_each_port_masked(port, port_mask) { 2687 enum phy phy = intel_port_to_phy(dev_priv, port); 2688 bool ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv, 2689 phy); 2690 2691 if (ddi_clk_needed == !ddi_clk_off) 2692 continue; 2693 2694 /* 2695 * Punt on the case now where clock is gated, but it would 2696 * be needed by the port. Something else is really broken then. 2697 */ 2698 if (drm_WARN_ON(&dev_priv->drm, ddi_clk_needed)) 2699 continue; 2700 2701 DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2702 phy_name(phy)); 2703 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 2704 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 2705 } 2706 } 2707 2708 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2709 { 2710 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2711 u32 port_mask; 2712 bool ddi_clk_needed; 2713 2714 /* 2715 * In case of DP MST, we sanitize the primary encoder only, not the 2716 * virtual ones. 2717 */ 2718 if (encoder->type == INTEL_OUTPUT_DP_MST) 2719 return; 2720 2721 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2722 u8 pipe_mask; 2723 bool is_mst; 2724 2725 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2726 /* 2727 * In the unlikely case that BIOS enables DP in MST mode, just 2728 * warn since our MST HW readout is incomplete. 2729 */ 2730 if (drm_WARN_ON(&dev_priv->drm, is_mst)) 2731 return; 2732 } 2733 2734 port_mask = BIT(encoder->port); 2735 ddi_clk_needed = encoder->base.crtc; 2736 2737 if (encoder->type == INTEL_OUTPUT_DSI) { 2738 struct intel_encoder *other_encoder; 2739 2740 port_mask = intel_dsi_encoder_ports(encoder); 2741 /* 2742 * Sanity check that we haven't incorrectly registered another 2743 * encoder using any of the ports of this DSI encoder. 2744 */ 2745 for_each_intel_encoder(&dev_priv->drm, other_encoder) { 2746 if (other_encoder == encoder) 2747 continue; 2748 2749 if (drm_WARN_ON(&dev_priv->drm, 2750 port_mask & BIT(other_encoder->port))) 2751 return; 2752 } 2753 /* 2754 * For DSI we keep the ddi clocks gated 2755 * except during enable/disable sequence. 2756 */ 2757 ddi_clk_needed = false; 2758 } 2759 2760 icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed); 2761 } 2762 2763 static void intel_ddi_clk_select(struct intel_encoder *encoder, 2764 const struct intel_crtc_state *crtc_state) 2765 { 2766 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2767 enum port port = encoder->port; 2768 enum phy phy = intel_port_to_phy(dev_priv, port); 2769 u32 val; 2770 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 2771 2772 if (drm_WARN_ON(&dev_priv->drm, !pll)) 2773 return; 2774 2775 mutex_lock(&dev_priv->dpll.lock); 2776 2777 if (INTEL_GEN(dev_priv) >= 11) { 2778 if (!intel_phy_is_combo(dev_priv, phy)) 2779 intel_de_write(dev_priv, DDI_CLK_SEL(port), 2780 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 2781 else if (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C) 2782 /* 2783 * MG does not exist but the programming is required 2784 * to ungate DDIC and DDID 2785 */ 2786 intel_de_write(dev_priv, DDI_CLK_SEL(port), 2787 DDI_CLK_SEL_MG); 2788 } else if (IS_CANNONLAKE(dev_priv)) { 2789 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */ 2790 val = intel_de_read(dev_priv, DPCLKA_CFGCR0); 2791 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); 2792 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port); 2793 intel_de_write(dev_priv, DPCLKA_CFGCR0, val); 2794 2795 /* 2796 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI. 2797 * This step and the step before must be done with separate 2798 * register writes. 2799 */ 2800 val = intel_de_read(dev_priv, DPCLKA_CFGCR0); 2801 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); 2802 intel_de_write(dev_priv, DPCLKA_CFGCR0, val); 2803 } else if (IS_GEN9_BC(dev_priv)) { 2804 /* DDI -> PLL mapping */ 2805 val = intel_de_read(dev_priv, DPLL_CTRL2); 2806 2807 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | 2808 DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); 2809 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 2810 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 2811 2812 intel_de_write(dev_priv, DPLL_CTRL2, val); 2813 2814 } else if (INTEL_GEN(dev_priv) < 9) { 2815 intel_de_write(dev_priv, PORT_CLK_SEL(port), 2816 hsw_pll_to_ddi_pll_sel(pll)); 2817 } 2818 2819 mutex_unlock(&dev_priv->dpll.lock); 2820 } 2821 2822 static void intel_ddi_clk_disable(struct intel_encoder *encoder) 2823 { 2824 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2825 enum port port = encoder->port; 2826 enum phy phy = intel_port_to_phy(dev_priv, port); 2827 2828 if (INTEL_GEN(dev_priv) >= 11) { 2829 if (!intel_phy_is_combo(dev_priv, phy) || 2830 (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C)) 2831 intel_de_write(dev_priv, DDI_CLK_SEL(port), 2832 DDI_CLK_SEL_NONE); 2833 } else if (IS_CANNONLAKE(dev_priv)) { 2834 intel_de_write(dev_priv, DPCLKA_CFGCR0, 2835 intel_de_read(dev_priv, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port)); 2836 } else if (IS_GEN9_BC(dev_priv)) { 2837 intel_de_write(dev_priv, DPLL_CTRL2, 2838 intel_de_read(dev_priv, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port)); 2839 } else if (INTEL_GEN(dev_priv) < 9) { 2840 intel_de_write(dev_priv, PORT_CLK_SEL(port), 2841 PORT_CLK_SEL_NONE); 2842 } 2843 } 2844 2845 static void 2846 icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port, 2847 const struct intel_crtc_state *crtc_state) 2848 { 2849 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); 2850 enum tc_port tc_port = intel_port_to_tc(dev_priv, intel_dig_port->base.port); 2851 u32 ln0, ln1, pin_assignment; 2852 u8 width; 2853 2854 if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT) 2855 return; 2856 2857 if (INTEL_GEN(dev_priv) >= 12) { 2858 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2859 HIP_INDEX_VAL(tc_port, 0x0)); 2860 ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); 2861 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2862 HIP_INDEX_VAL(tc_port, 0x1)); 2863 ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); 2864 } else { 2865 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 2866 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 2867 } 2868 2869 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X1_MODE); 2870 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2871 2872 /* DPPATC */ 2873 pin_assignment = intel_tc_port_get_pin_assignment_mask(intel_dig_port); 2874 width = crtc_state->lane_count; 2875 2876 switch (pin_assignment) { 2877 case 0x0: 2878 drm_WARN_ON(&dev_priv->drm, 2879 intel_dig_port->tc_mode != TC_PORT_LEGACY); 2880 if (width == 1) { 2881 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2882 } else { 2883 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2884 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2885 } 2886 break; 2887 case 0x1: 2888 if (width == 4) { 2889 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2890 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2891 } 2892 break; 2893 case 0x2: 2894 if (width == 2) { 2895 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2896 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2897 } 2898 break; 2899 case 0x3: 2900 case 0x5: 2901 if (width == 1) { 2902 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2903 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2904 } else { 2905 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2906 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2907 } 2908 break; 2909 case 0x4: 2910 case 0x6: 2911 if (width == 1) { 2912 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2913 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2914 } else { 2915 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2916 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2917 } 2918 break; 2919 default: 2920 MISSING_CASE(pin_assignment); 2921 } 2922 2923 if (INTEL_GEN(dev_priv) >= 12) { 2924 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2925 HIP_INDEX_VAL(tc_port, 0x0)); 2926 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0); 2927 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2928 HIP_INDEX_VAL(tc_port, 0x1)); 2929 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1); 2930 } else { 2931 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 2932 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 2933 } 2934 } 2935 2936 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2937 const struct intel_crtc_state *crtc_state) 2938 { 2939 if (!crtc_state->fec_enable) 2940 return; 2941 2942 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0) 2943 DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n"); 2944 } 2945 2946 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2947 const struct intel_crtc_state *crtc_state) 2948 { 2949 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2950 struct intel_dp *intel_dp; 2951 u32 val; 2952 2953 if (!crtc_state->fec_enable) 2954 return; 2955 2956 intel_dp = enc_to_intel_dp(encoder); 2957 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 2958 val |= DP_TP_CTL_FEC_ENABLE; 2959 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val); 2960 2961 if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, 2962 DP_TP_STATUS_FEC_ENABLE_LIVE, 1)) 2963 DRM_ERROR("Timed out waiting for FEC Enable Status\n"); 2964 } 2965 2966 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder, 2967 const struct intel_crtc_state *crtc_state) 2968 { 2969 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2970 struct intel_dp *intel_dp; 2971 u32 val; 2972 2973 if (!crtc_state->fec_enable) 2974 return; 2975 2976 intel_dp = enc_to_intel_dp(encoder); 2977 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 2978 val &= ~DP_TP_CTL_FEC_ENABLE; 2979 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val); 2980 intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl); 2981 } 2982 2983 static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder, 2984 const struct intel_crtc_state *crtc_state, 2985 const struct drm_connector_state *conn_state) 2986 { 2987 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2988 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2989 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2990 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2991 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2992 int level = intel_ddi_dp_level(intel_dp); 2993 enum transcoder transcoder = crtc_state->cpu_transcoder; 2994 2995 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, 2996 crtc_state->lane_count, is_mst); 2997 2998 intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder); 2999 intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder); 3000 3001 /* 3002 * 1. Enable Power Wells 3003 * 3004 * This was handled at the beginning of intel_atomic_commit_tail(), 3005 * before we called down into this function. 3006 */ 3007 3008 /* 2. Enable Panel Power if PPS is required */ 3009 intel_edp_panel_on(intel_dp); 3010 3011 /* 3012 * 3. For non-TBT Type-C ports, set FIA lane count 3013 * (DFLEXDPSP.DPX4TXLATC) 3014 * 3015 * This was done before tgl_ddi_pre_enable_dp by 3016 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 3017 */ 3018 3019 /* 3020 * 4. Enable the port PLL. 3021 * 3022 * The PLL enabling itself was already done before this function by 3023 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 3024 * configure the PLL to port mapping here. 3025 */ 3026 intel_ddi_clk_select(encoder, crtc_state); 3027 3028 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 3029 if (!intel_phy_is_tc(dev_priv, phy) || 3030 dig_port->tc_mode != TC_PORT_TBT_ALT) 3031 intel_display_power_get(dev_priv, 3032 dig_port->ddi_io_power_domain); 3033 3034 /* 6. Program DP_MODE */ 3035 icl_program_mg_dp_mode(dig_port, crtc_state); 3036 3037 /* 3038 * 7. The rest of the below are substeps under the bspec's "Enable and 3039 * Train Display Port" step. Note that steps that are specific to 3040 * MST will be handled by intel_mst_pre_enable_dp() before/after it 3041 * calls into this function. Also intel_mst_pre_enable_dp() only calls 3042 * us when active_mst_links==0, so any steps designated for "single 3043 * stream or multi-stream master transcoder" can just be performed 3044 * unconditionally here. 3045 */ 3046 3047 /* 3048 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 3049 * Transcoder. 3050 */ 3051 intel_ddi_enable_pipe_clock(crtc_state); 3052 3053 /* 3054 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 3055 * Transport Select 3056 */ 3057 intel_ddi_config_transcoder_func(crtc_state); 3058 3059 /* 3060 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 3061 * selected 3062 * 3063 * This will be handled by the intel_dp_start_link_train() farther 3064 * down this function. 3065 */ 3066 3067 /* 7.e Configure voltage swing and related IO settings */ 3068 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level, 3069 encoder->type); 3070 3071 /* 3072 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 3073 * the used lanes of the DDI. 3074 */ 3075 if (intel_phy_is_combo(dev_priv, phy)) { 3076 bool lane_reversal = 3077 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 3078 3079 intel_combo_phy_power_up_lanes(dev_priv, phy, false, 3080 crtc_state->lane_count, 3081 lane_reversal); 3082 } 3083 3084 /* 3085 * 7.g Configure and enable DDI_BUF_CTL 3086 * 7.h Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout 3087 * after 500 us. 3088 * 3089 * We only configure what the register value will be here. Actual 3090 * enabling happens during link training farther down. 3091 */ 3092 intel_ddi_init_dp_buf_reg(encoder); 3093 3094 if (!is_mst) 3095 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 3096 3097 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); 3098 /* 3099 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 3100 * in the FEC_CONFIGURATION register to 1 before initiating link 3101 * training 3102 */ 3103 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 3104 3105 /* 3106 * 7.i Follow DisplayPort specification training sequence (see notes for 3107 * failure handling) 3108 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 3109 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 3110 * (timeout after 800 us) 3111 */ 3112 intel_dp_start_link_train(intel_dp); 3113 3114 /* 7.k Set DP_TP_CTL link training to Normal */ 3115 if (!is_trans_port_sync_mode(crtc_state)) 3116 intel_dp_stop_link_train(intel_dp); 3117 3118 /* 7.l Configure and enable FEC if needed */ 3119 intel_ddi_enable_fec(encoder, crtc_state); 3120 intel_dsc_enable(encoder, crtc_state); 3121 } 3122 3123 static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder, 3124 const struct intel_crtc_state *crtc_state, 3125 const struct drm_connector_state *conn_state) 3126 { 3127 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3128 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3129 enum port port = encoder->port; 3130 enum phy phy = intel_port_to_phy(dev_priv, port); 3131 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3132 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 3133 int level = intel_ddi_dp_level(intel_dp); 3134 3135 if (INTEL_GEN(dev_priv) < 11) 3136 drm_WARN_ON(&dev_priv->drm, 3137 is_mst && (port == PORT_A || port == PORT_E)); 3138 else 3139 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 3140 3141 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, 3142 crtc_state->lane_count, is_mst); 3143 3144 intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port); 3145 intel_dp->regs.dp_tp_status = DP_TP_STATUS(port); 3146 3147 intel_edp_panel_on(intel_dp); 3148 3149 intel_ddi_clk_select(encoder, crtc_state); 3150 3151 if (!intel_phy_is_tc(dev_priv, phy) || 3152 dig_port->tc_mode != TC_PORT_TBT_ALT) 3153 intel_display_power_get(dev_priv, 3154 dig_port->ddi_io_power_domain); 3155 3156 icl_program_mg_dp_mode(dig_port, crtc_state); 3157 3158 if (INTEL_GEN(dev_priv) >= 11) 3159 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, 3160 level, encoder->type); 3161 else if (IS_CANNONLAKE(dev_priv)) 3162 cnl_ddi_vswing_sequence(encoder, level, encoder->type); 3163 else if (IS_GEN9_LP(dev_priv)) 3164 bxt_ddi_vswing_sequence(encoder, level, encoder->type); 3165 else 3166 intel_prepare_dp_ddi_buffers(encoder, crtc_state); 3167 3168 if (intel_phy_is_combo(dev_priv, phy)) { 3169 bool lane_reversal = 3170 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 3171 3172 intel_combo_phy_power_up_lanes(dev_priv, phy, false, 3173 crtc_state->lane_count, 3174 lane_reversal); 3175 } 3176 3177 intel_ddi_init_dp_buf_reg(encoder); 3178 if (!is_mst) 3179 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 3180 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, 3181 true); 3182 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 3183 intel_dp_start_link_train(intel_dp); 3184 if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) && 3185 !is_trans_port_sync_mode(crtc_state)) 3186 intel_dp_stop_link_train(intel_dp); 3187 3188 intel_ddi_enable_fec(encoder, crtc_state); 3189 3190 if (!is_mst) 3191 intel_ddi_enable_pipe_clock(crtc_state); 3192 3193 intel_dsc_enable(encoder, crtc_state); 3194 } 3195 3196 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, 3197 const struct intel_crtc_state *crtc_state, 3198 const struct drm_connector_state *conn_state) 3199 { 3200 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3201 3202 if (INTEL_GEN(dev_priv) >= 12) 3203 tgl_ddi_pre_enable_dp(encoder, crtc_state, conn_state); 3204 else 3205 hsw_ddi_pre_enable_dp(encoder, crtc_state, conn_state); 3206 3207 /* MST will call a setting of MSA after an allocating of Virtual Channel 3208 * from MST encoder pre_enable callback. 3209 */ 3210 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3211 intel_ddi_set_dp_msa(crtc_state, conn_state); 3212 3213 intel_dp_set_m_n(crtc_state, M1_N1); 3214 } 3215 } 3216 3217 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder, 3218 const struct intel_crtc_state *crtc_state, 3219 const struct drm_connector_state *conn_state) 3220 { 3221 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 3222 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 3223 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3224 int level = intel_ddi_hdmi_level(encoder); 3225 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3226 3227 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 3228 intel_ddi_clk_select(encoder, crtc_state); 3229 3230 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); 3231 3232 icl_program_mg_dp_mode(dig_port, crtc_state); 3233 3234 if (INTEL_GEN(dev_priv) >= 12) 3235 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, 3236 level, INTEL_OUTPUT_HDMI); 3237 else if (INTEL_GEN(dev_priv) == 11) 3238 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, 3239 level, INTEL_OUTPUT_HDMI); 3240 else if (IS_CANNONLAKE(dev_priv)) 3241 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI); 3242 else if (IS_GEN9_LP(dev_priv)) 3243 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI); 3244 else 3245 intel_prepare_hdmi_ddi_buffers(encoder, level); 3246 3247 if (IS_GEN9_BC(dev_priv)) 3248 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI); 3249 3250 intel_ddi_enable_pipe_clock(crtc_state); 3251 3252 intel_dig_port->set_infoframes(encoder, 3253 crtc_state->has_infoframe, 3254 crtc_state, conn_state); 3255 } 3256 3257 static void intel_ddi_pre_enable(struct intel_encoder *encoder, 3258 const struct intel_crtc_state *crtc_state, 3259 const struct drm_connector_state *conn_state) 3260 { 3261 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3262 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3263 enum pipe pipe = crtc->pipe; 3264 3265 /* 3266 * When called from DP MST code: 3267 * - conn_state will be NULL 3268 * - encoder will be the main encoder (ie. mst->primary) 3269 * - the main connector associated with this port 3270 * won't be active or linked to a crtc 3271 * - crtc_state will be the state of the first stream to 3272 * be activated on this port, and it may not be the same 3273 * stream that will be deactivated last, but each stream 3274 * should have a state that is identical when it comes to 3275 * the DP link parameteres 3276 */ 3277 3278 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 3279 3280 if (INTEL_GEN(dev_priv) >= 11) 3281 icl_map_plls_to_ports(encoder, crtc_state); 3282 3283 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 3284 3285 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 3286 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state); 3287 } else { 3288 struct intel_lspcon *lspcon = 3289 enc_to_intel_lspcon(encoder); 3290 3291 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state); 3292 if (lspcon->active) { 3293 struct intel_digital_port *dig_port = 3294 enc_to_dig_port(encoder); 3295 3296 dig_port->set_infoframes(encoder, 3297 crtc_state->has_infoframe, 3298 crtc_state, conn_state); 3299 } 3300 } 3301 } 3302 3303 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 3304 const struct intel_crtc_state *crtc_state) 3305 { 3306 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3307 enum port port = encoder->port; 3308 bool wait = false; 3309 u32 val; 3310 3311 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3312 if (val & DDI_BUF_CTL_ENABLE) { 3313 val &= ~DDI_BUF_CTL_ENABLE; 3314 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 3315 wait = true; 3316 } 3317 3318 if (intel_crtc_has_dp_encoder(crtc_state)) { 3319 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3320 3321 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 3322 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 3323 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 3324 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val); 3325 } 3326 3327 /* Disable FEC in DP Sink */ 3328 intel_ddi_disable_fec_state(encoder, crtc_state); 3329 3330 if (wait) 3331 intel_wait_ddi_buf_idle(dev_priv, port); 3332 } 3333 3334 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder, 3335 const struct intel_crtc_state *old_crtc_state, 3336 const struct drm_connector_state *old_conn_state) 3337 { 3338 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3339 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3340 struct intel_dp *intel_dp = &dig_port->dp; 3341 bool is_mst = intel_crtc_has_type(old_crtc_state, 3342 INTEL_OUTPUT_DP_MST); 3343 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3344 3345 /* 3346 * Power down sink before disabling the port, otherwise we end 3347 * up getting interrupts from the sink on detecting link loss. 3348 */ 3349 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 3350 3351 if (INTEL_GEN(dev_priv) >= 12) { 3352 if (is_mst) { 3353 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 3354 u32 val; 3355 3356 val = intel_de_read(dev_priv, 3357 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3358 val &= ~(TGL_TRANS_DDI_PORT_MASK | 3359 TRANS_DDI_MODE_SELECT_MASK); 3360 intel_de_write(dev_priv, 3361 TRANS_DDI_FUNC_CTL(cpu_transcoder), 3362 val); 3363 } 3364 } else { 3365 if (!is_mst) 3366 intel_ddi_disable_pipe_clock(old_crtc_state); 3367 } 3368 3369 intel_disable_ddi_buf(encoder, old_crtc_state); 3370 3371 /* 3372 * From TGL spec: "If single stream or multi-stream master transcoder: 3373 * Configure Transcoder Clock select to direct no clock to the 3374 * transcoder" 3375 */ 3376 if (INTEL_GEN(dev_priv) >= 12) 3377 intel_ddi_disable_pipe_clock(old_crtc_state); 3378 3379 intel_edp_panel_vdd_on(intel_dp); 3380 intel_edp_panel_off(intel_dp); 3381 3382 if (!intel_phy_is_tc(dev_priv, phy) || 3383 dig_port->tc_mode != TC_PORT_TBT_ALT) 3384 intel_display_power_put_unchecked(dev_priv, 3385 dig_port->ddi_io_power_domain); 3386 3387 intel_ddi_clk_disable(encoder); 3388 } 3389 3390 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder, 3391 const struct intel_crtc_state *old_crtc_state, 3392 const struct drm_connector_state *old_conn_state) 3393 { 3394 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3395 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3396 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3397 3398 dig_port->set_infoframes(encoder, false, 3399 old_crtc_state, old_conn_state); 3400 3401 intel_ddi_disable_pipe_clock(old_crtc_state); 3402 3403 intel_disable_ddi_buf(encoder, old_crtc_state); 3404 3405 intel_display_power_put_unchecked(dev_priv, 3406 dig_port->ddi_io_power_domain); 3407 3408 intel_ddi_clk_disable(encoder); 3409 3410 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3411 } 3412 3413 static void icl_disable_transcoder_port_sync(const struct intel_crtc_state *old_crtc_state) 3414 { 3415 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 3416 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3417 3418 if (old_crtc_state->master_transcoder == INVALID_TRANSCODER) 3419 return; 3420 3421 DRM_DEBUG_KMS("Disabling Transcoder Port Sync on Slave Transcoder %s\n", 3422 transcoder_name(old_crtc_state->cpu_transcoder)); 3423 3424 intel_de_write(dev_priv, 3425 TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder), 0); 3426 } 3427 3428 static void intel_ddi_post_disable(struct intel_encoder *encoder, 3429 const struct intel_crtc_state *old_crtc_state, 3430 const struct drm_connector_state *old_conn_state) 3431 { 3432 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3433 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3434 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3435 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 3436 3437 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) { 3438 intel_crtc_vblank_off(old_crtc_state); 3439 3440 intel_disable_pipe(old_crtc_state); 3441 3442 if (INTEL_GEN(dev_priv) >= 11) 3443 icl_disable_transcoder_port_sync(old_crtc_state); 3444 3445 intel_ddi_disable_transcoder_func(old_crtc_state); 3446 3447 intel_dsc_disable(old_crtc_state); 3448 3449 if (INTEL_GEN(dev_priv) >= 9) 3450 skl_scaler_disable(old_crtc_state); 3451 else 3452 ilk_pfit_disable(old_crtc_state); 3453 } 3454 3455 /* 3456 * When called from DP MST code: 3457 * - old_conn_state will be NULL 3458 * - encoder will be the main encoder (ie. mst->primary) 3459 * - the main connector associated with this port 3460 * won't be active or linked to a crtc 3461 * - old_crtc_state will be the state of the last stream to 3462 * be deactivated on this port, and it may not be the same 3463 * stream that was activated last, but each stream 3464 * should have a state that is identical when it comes to 3465 * the DP link parameteres 3466 */ 3467 3468 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3469 intel_ddi_post_disable_hdmi(encoder, 3470 old_crtc_state, old_conn_state); 3471 else 3472 intel_ddi_post_disable_dp(encoder, 3473 old_crtc_state, old_conn_state); 3474 3475 if (INTEL_GEN(dev_priv) >= 11) 3476 icl_unmap_plls_to_ports(encoder); 3477 3478 if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port) 3479 intel_display_power_put_unchecked(dev_priv, 3480 intel_ddi_main_link_aux_domain(dig_port)); 3481 3482 if (is_tc_port) 3483 intel_tc_port_put_link(dig_port); 3484 } 3485 3486 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder, 3487 const struct intel_crtc_state *old_crtc_state, 3488 const struct drm_connector_state *old_conn_state) 3489 { 3490 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3491 u32 val; 3492 3493 /* 3494 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable) 3495 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN, 3496 * step 13 is the correct place for it. Step 18 is where it was 3497 * originally before the BUN. 3498 */ 3499 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 3500 val &= ~FDI_RX_ENABLE; 3501 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 3502 3503 intel_disable_ddi_buf(encoder, old_crtc_state); 3504 intel_ddi_clk_disable(encoder); 3505 3506 val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); 3507 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 3508 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 3509 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val); 3510 3511 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 3512 val &= ~FDI_PCDCLK; 3513 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 3514 3515 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 3516 val &= ~FDI_RX_PLL_ENABLE; 3517 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 3518 } 3519 3520 static void intel_enable_ddi_dp(struct intel_encoder *encoder, 3521 const struct intel_crtc_state *crtc_state, 3522 const struct drm_connector_state *conn_state) 3523 { 3524 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3525 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3526 enum port port = encoder->port; 3527 3528 if (port == PORT_A && INTEL_GEN(dev_priv) < 9) 3529 intel_dp_stop_link_train(intel_dp); 3530 3531 intel_edp_backlight_on(crtc_state, conn_state); 3532 intel_psr_enable(intel_dp, crtc_state); 3533 intel_dp_vsc_enable(intel_dp, crtc_state, conn_state); 3534 intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state); 3535 intel_edp_drrs_enable(intel_dp, crtc_state); 3536 3537 if (crtc_state->has_audio) 3538 intel_audio_codec_enable(encoder, crtc_state, conn_state); 3539 } 3540 3541 static i915_reg_t 3542 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 3543 enum port port) 3544 { 3545 static const enum transcoder trans[] = { 3546 [PORT_A] = TRANSCODER_EDP, 3547 [PORT_B] = TRANSCODER_A, 3548 [PORT_C] = TRANSCODER_B, 3549 [PORT_D] = TRANSCODER_C, 3550 [PORT_E] = TRANSCODER_A, 3551 }; 3552 3553 drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) < 9); 3554 3555 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) 3556 port = PORT_A; 3557 3558 return CHICKEN_TRANS(trans[port]); 3559 } 3560 3561 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder, 3562 const struct intel_crtc_state *crtc_state, 3563 const struct drm_connector_state *conn_state) 3564 { 3565 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3566 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3567 struct drm_connector *connector = conn_state->connector; 3568 enum port port = encoder->port; 3569 3570 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3571 crtc_state->hdmi_high_tmds_clock_ratio, 3572 crtc_state->hdmi_scrambling)) 3573 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to configure sink " 3574 "scrambling/TMDS bit clock ratio\n", 3575 connector->base.id, connector->name); 3576 3577 /* Display WA #1143: skl,kbl,cfl */ 3578 if (IS_GEN9_BC(dev_priv)) { 3579 /* 3580 * For some reason these chicken bits have been 3581 * stuffed into a transcoder register, event though 3582 * the bits affect a specific DDI port rather than 3583 * a specific transcoder. 3584 */ 3585 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 3586 u32 val; 3587 3588 val = intel_de_read(dev_priv, reg); 3589 3590 if (port == PORT_E) 3591 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3592 DDIE_TRAINING_OVERRIDE_VALUE; 3593 else 3594 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3595 DDI_TRAINING_OVERRIDE_VALUE; 3596 3597 intel_de_write(dev_priv, reg, val); 3598 intel_de_posting_read(dev_priv, reg); 3599 3600 udelay(1); 3601 3602 if (port == PORT_E) 3603 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3604 DDIE_TRAINING_OVERRIDE_VALUE); 3605 else 3606 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3607 DDI_TRAINING_OVERRIDE_VALUE); 3608 3609 intel_de_write(dev_priv, reg, val); 3610 } 3611 3612 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3613 * are ignored so nothing special needs to be done besides 3614 * enabling the port. 3615 */ 3616 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3617 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE); 3618 3619 if (crtc_state->has_audio) 3620 intel_audio_codec_enable(encoder, crtc_state, conn_state); 3621 } 3622 3623 static void intel_enable_ddi(struct intel_encoder *encoder, 3624 const struct intel_crtc_state *crtc_state, 3625 const struct drm_connector_state *conn_state) 3626 { 3627 WARN_ON(crtc_state->has_pch_encoder); 3628 3629 intel_enable_pipe(crtc_state); 3630 3631 intel_crtc_vblank_on(crtc_state); 3632 3633 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3634 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state); 3635 else 3636 intel_enable_ddi_dp(encoder, crtc_state, conn_state); 3637 3638 /* Enable hdcp if it's desired */ 3639 if (conn_state->content_protection == 3640 DRM_MODE_CONTENT_PROTECTION_DESIRED) 3641 intel_hdcp_enable(to_intel_connector(conn_state->connector), 3642 crtc_state->cpu_transcoder, 3643 (u8)conn_state->hdcp_content_type); 3644 } 3645 3646 static void intel_disable_ddi_dp(struct intel_encoder *encoder, 3647 const struct intel_crtc_state *old_crtc_state, 3648 const struct drm_connector_state *old_conn_state) 3649 { 3650 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3651 3652 intel_dp->link_trained = false; 3653 3654 if (old_crtc_state->has_audio) 3655 intel_audio_codec_disable(encoder, 3656 old_crtc_state, old_conn_state); 3657 3658 intel_edp_drrs_disable(intel_dp, old_crtc_state); 3659 intel_psr_disable(intel_dp, old_crtc_state); 3660 intel_edp_backlight_off(old_conn_state); 3661 /* Disable the decompression in DP Sink */ 3662 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, 3663 false); 3664 } 3665 3666 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder, 3667 const struct intel_crtc_state *old_crtc_state, 3668 const struct drm_connector_state *old_conn_state) 3669 { 3670 struct drm_connector *connector = old_conn_state->connector; 3671 3672 if (old_crtc_state->has_audio) 3673 intel_audio_codec_disable(encoder, 3674 old_crtc_state, old_conn_state); 3675 3676 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3677 false, false)) 3678 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3679 connector->base.id, connector->name); 3680 } 3681 3682 static void intel_disable_ddi(struct intel_encoder *encoder, 3683 const struct intel_crtc_state *old_crtc_state, 3684 const struct drm_connector_state *old_conn_state) 3685 { 3686 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3687 3688 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3689 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state); 3690 else 3691 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state); 3692 } 3693 3694 static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder, 3695 const struct intel_crtc_state *crtc_state, 3696 const struct drm_connector_state *conn_state) 3697 { 3698 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3699 3700 intel_ddi_set_dp_msa(crtc_state, conn_state); 3701 3702 intel_psr_update(intel_dp, crtc_state); 3703 intel_edp_drrs_enable(intel_dp, crtc_state); 3704 3705 intel_panel_update_backlight(encoder, crtc_state, conn_state); 3706 } 3707 3708 static void intel_ddi_update_pipe(struct intel_encoder *encoder, 3709 const struct intel_crtc_state *crtc_state, 3710 const struct drm_connector_state *conn_state) 3711 { 3712 3713 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3714 intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state); 3715 3716 intel_hdcp_update_pipe(encoder, crtc_state, conn_state); 3717 } 3718 3719 static void 3720 intel_ddi_update_prepare(struct intel_atomic_state *state, 3721 struct intel_encoder *encoder, 3722 struct intel_crtc *crtc) 3723 { 3724 struct intel_crtc_state *crtc_state = 3725 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL; 3726 int required_lanes = crtc_state ? crtc_state->lane_count : 1; 3727 3728 WARN_ON(crtc && crtc->active); 3729 3730 intel_tc_port_get_link(enc_to_dig_port(encoder), 3731 required_lanes); 3732 if (crtc_state && crtc_state->hw.active) 3733 intel_update_active_dpll(state, crtc, encoder); 3734 } 3735 3736 static void 3737 intel_ddi_update_complete(struct intel_atomic_state *state, 3738 struct intel_encoder *encoder, 3739 struct intel_crtc *crtc) 3740 { 3741 intel_tc_port_put_link(enc_to_dig_port(encoder)); 3742 } 3743 3744 static void 3745 intel_ddi_pre_pll_enable(struct intel_encoder *encoder, 3746 const struct intel_crtc_state *crtc_state, 3747 const struct drm_connector_state *conn_state) 3748 { 3749 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3750 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3751 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3752 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 3753 3754 if (is_tc_port) 3755 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3756 3757 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) 3758 intel_display_power_get(dev_priv, 3759 intel_ddi_main_link_aux_domain(dig_port)); 3760 3761 if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT) 3762 /* 3763 * Program the lane count for static/dynamic connections on 3764 * Type-C ports. Skip this step for TBT. 3765 */ 3766 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3767 else if (IS_GEN9_LP(dev_priv)) 3768 bxt_ddi_phy_set_lane_optim_mask(encoder, 3769 crtc_state->lane_lat_optim_mask); 3770 } 3771 3772 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) 3773 { 3774 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3775 struct drm_i915_private *dev_priv = 3776 to_i915(intel_dig_port->base.base.dev); 3777 enum port port = intel_dig_port->base.port; 3778 u32 dp_tp_ctl, ddi_buf_ctl; 3779 bool wait = false; 3780 3781 dp_tp_ctl = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 3782 3783 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 3784 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3785 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 3786 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3787 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 3788 wait = true; 3789 } 3790 3791 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 3792 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1; 3793 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl); 3794 intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl); 3795 3796 if (wait) 3797 intel_wait_ddi_buf_idle(dev_priv, port); 3798 } 3799 3800 dp_tp_ctl = DP_TP_CTL_ENABLE | 3801 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; 3802 if (intel_dp->link_mst) 3803 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3804 else { 3805 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3806 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 3807 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3808 } 3809 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl); 3810 intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl); 3811 3812 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3813 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3814 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3815 3816 udelay(600); 3817 } 3818 3819 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 3820 enum transcoder cpu_transcoder) 3821 { 3822 if (cpu_transcoder == TRANSCODER_EDP) 3823 return false; 3824 3825 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) 3826 return false; 3827 3828 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 3829 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3830 } 3831 3832 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, 3833 struct intel_crtc_state *crtc_state) 3834 { 3835 if (INTEL_GEN(dev_priv) >= 12 && crtc_state->port_clock > 594000) 3836 crtc_state->min_voltage_level = 2; 3837 else if (IS_ELKHARTLAKE(dev_priv) && crtc_state->port_clock > 594000) 3838 crtc_state->min_voltage_level = 3; 3839 else if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000) 3840 crtc_state->min_voltage_level = 1; 3841 else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000) 3842 crtc_state->min_voltage_level = 2; 3843 } 3844 3845 void intel_ddi_get_config(struct intel_encoder *encoder, 3846 struct intel_crtc_state *pipe_config) 3847 { 3848 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3849 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); 3850 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3851 u32 temp, flags = 0; 3852 3853 /* XXX: DSI transcoder paranoia */ 3854 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 3855 return; 3856 3857 intel_dsc_get_config(encoder, pipe_config); 3858 3859 temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3860 if (temp & TRANS_DDI_PHSYNC) 3861 flags |= DRM_MODE_FLAG_PHSYNC; 3862 else 3863 flags |= DRM_MODE_FLAG_NHSYNC; 3864 if (temp & TRANS_DDI_PVSYNC) 3865 flags |= DRM_MODE_FLAG_PVSYNC; 3866 else 3867 flags |= DRM_MODE_FLAG_NVSYNC; 3868 3869 pipe_config->hw.adjusted_mode.flags |= flags; 3870 3871 switch (temp & TRANS_DDI_BPC_MASK) { 3872 case TRANS_DDI_BPC_6: 3873 pipe_config->pipe_bpp = 18; 3874 break; 3875 case TRANS_DDI_BPC_8: 3876 pipe_config->pipe_bpp = 24; 3877 break; 3878 case TRANS_DDI_BPC_10: 3879 pipe_config->pipe_bpp = 30; 3880 break; 3881 case TRANS_DDI_BPC_12: 3882 pipe_config->pipe_bpp = 36; 3883 break; 3884 default: 3885 break; 3886 } 3887 3888 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 3889 case TRANS_DDI_MODE_SELECT_HDMI: 3890 pipe_config->has_hdmi_sink = true; 3891 3892 pipe_config->infoframes.enable |= 3893 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3894 3895 if (pipe_config->infoframes.enable) 3896 pipe_config->has_infoframe = true; 3897 3898 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 3899 pipe_config->hdmi_scrambling = true; 3900 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 3901 pipe_config->hdmi_high_tmds_clock_ratio = true; 3902 /* fall through */ 3903 case TRANS_DDI_MODE_SELECT_DVI: 3904 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 3905 pipe_config->lane_count = 4; 3906 break; 3907 case TRANS_DDI_MODE_SELECT_FDI: 3908 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 3909 break; 3910 case TRANS_DDI_MODE_SELECT_DP_SST: 3911 if (encoder->type == INTEL_OUTPUT_EDP) 3912 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 3913 else 3914 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 3915 pipe_config->lane_count = 3916 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3917 intel_dp_get_m_n(intel_crtc, pipe_config); 3918 3919 if (INTEL_GEN(dev_priv) >= 11) { 3920 i915_reg_t dp_tp_ctl; 3921 3922 if (IS_GEN(dev_priv, 11)) 3923 dp_tp_ctl = DP_TP_CTL(encoder->port); 3924 else 3925 dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder); 3926 3927 pipe_config->fec_enable = 3928 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE; 3929 3930 DRM_DEBUG_KMS("[ENCODER:%d:%s] Fec status: %u\n", 3931 encoder->base.base.id, encoder->base.name, 3932 pipe_config->fec_enable); 3933 } 3934 3935 break; 3936 case TRANS_DDI_MODE_SELECT_DP_MST: 3937 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 3938 pipe_config->lane_count = 3939 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3940 3941 if (INTEL_GEN(dev_priv) >= 12) 3942 pipe_config->mst_master_transcoder = 3943 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); 3944 3945 intel_dp_get_m_n(intel_crtc, pipe_config); 3946 break; 3947 default: 3948 break; 3949 } 3950 3951 pipe_config->has_audio = 3952 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 3953 3954 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp && 3955 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { 3956 /* 3957 * This is a big fat ugly hack. 3958 * 3959 * Some machines in UEFI boot mode provide us a VBT that has 18 3960 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 3961 * unknown we fail to light up. Yet the same BIOS boots up with 3962 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 3963 * max, not what it tells us to use. 3964 * 3965 * Note: This will still be broken if the eDP panel is not lit 3966 * up by the BIOS, and thus we can't get the mode at module 3967 * load. 3968 */ 3969 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 3970 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); 3971 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; 3972 } 3973 3974 intel_ddi_clock_get(encoder, pipe_config); 3975 3976 if (IS_GEN9_LP(dev_priv)) 3977 pipe_config->lane_lat_optim_mask = 3978 bxt_ddi_phy_get_lane_lat_optim_mask(encoder); 3979 3980 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 3981 3982 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 3983 3984 intel_read_infoframe(encoder, pipe_config, 3985 HDMI_INFOFRAME_TYPE_AVI, 3986 &pipe_config->infoframes.avi); 3987 intel_read_infoframe(encoder, pipe_config, 3988 HDMI_INFOFRAME_TYPE_SPD, 3989 &pipe_config->infoframes.spd); 3990 intel_read_infoframe(encoder, pipe_config, 3991 HDMI_INFOFRAME_TYPE_VENDOR, 3992 &pipe_config->infoframes.hdmi); 3993 intel_read_infoframe(encoder, pipe_config, 3994 HDMI_INFOFRAME_TYPE_DRM, 3995 &pipe_config->infoframes.drm); 3996 } 3997 3998 static enum intel_output_type 3999 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4000 struct intel_crtc_state *crtc_state, 4001 struct drm_connector_state *conn_state) 4002 { 4003 switch (conn_state->connector->connector_type) { 4004 case DRM_MODE_CONNECTOR_HDMIA: 4005 return INTEL_OUTPUT_HDMI; 4006 case DRM_MODE_CONNECTOR_eDP: 4007 return INTEL_OUTPUT_EDP; 4008 case DRM_MODE_CONNECTOR_DisplayPort: 4009 return INTEL_OUTPUT_DP; 4010 default: 4011 MISSING_CASE(conn_state->connector->connector_type); 4012 return INTEL_OUTPUT_UNUSED; 4013 } 4014 } 4015 4016 static int intel_ddi_compute_config(struct intel_encoder *encoder, 4017 struct intel_crtc_state *pipe_config, 4018 struct drm_connector_state *conn_state) 4019 { 4020 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4021 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4022 enum port port = encoder->port; 4023 int ret; 4024 4025 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) 4026 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4027 4028 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4029 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4030 } else { 4031 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 4032 } 4033 4034 if (ret) 4035 return ret; 4036 4037 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 4038 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4039 pipe_config->pch_pfit.force_thru = 4040 pipe_config->pch_pfit.enabled || 4041 pipe_config->crc_enabled; 4042 4043 if (IS_GEN9_LP(dev_priv)) 4044 pipe_config->lane_lat_optim_mask = 4045 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4046 4047 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 4048 4049 return 0; 4050 } 4051 4052 static bool mode_equal(const struct drm_display_mode *mode1, 4053 const struct drm_display_mode *mode2) 4054 { 4055 return drm_mode_match(mode1, mode2, 4056 DRM_MODE_MATCH_TIMINGS | 4057 DRM_MODE_MATCH_FLAGS | 4058 DRM_MODE_MATCH_3D_FLAGS) && 4059 mode1->clock == mode2->clock; /* we want an exact match */ 4060 } 4061 4062 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 4063 const struct intel_link_m_n *m_n_2) 4064 { 4065 return m_n_1->tu == m_n_2->tu && 4066 m_n_1->gmch_m == m_n_2->gmch_m && 4067 m_n_1->gmch_n == m_n_2->gmch_n && 4068 m_n_1->link_m == m_n_2->link_m && 4069 m_n_1->link_n == m_n_2->link_n; 4070 } 4071 4072 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 4073 const struct intel_crtc_state *crtc_state2) 4074 { 4075 return crtc_state1->hw.active && crtc_state2->hw.active && 4076 crtc_state1->output_types == crtc_state2->output_types && 4077 crtc_state1->output_format == crtc_state2->output_format && 4078 crtc_state1->lane_count == crtc_state2->lane_count && 4079 crtc_state1->port_clock == crtc_state2->port_clock && 4080 mode_equal(&crtc_state1->hw.adjusted_mode, 4081 &crtc_state2->hw.adjusted_mode) && 4082 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 4083 } 4084 4085 static u8 4086 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4087 int tile_group_id) 4088 { 4089 struct drm_connector *connector; 4090 const struct drm_connector_state *conn_state; 4091 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 4092 struct intel_atomic_state *state = 4093 to_intel_atomic_state(ref_crtc_state->uapi.state); 4094 u8 transcoders = 0; 4095 int i; 4096 4097 if (INTEL_GEN(dev_priv) < 11) 4098 return 0; 4099 4100 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4101 return 0; 4102 4103 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4104 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4105 const struct intel_crtc_state *crtc_state; 4106 4107 if (!crtc) 4108 continue; 4109 4110 if (!connector->has_tile || 4111 connector->tile_group->id != 4112 tile_group_id) 4113 continue; 4114 crtc_state = intel_atomic_get_new_crtc_state(state, 4115 crtc); 4116 if (!crtcs_port_sync_compatible(ref_crtc_state, 4117 crtc_state)) 4118 continue; 4119 transcoders |= BIT(crtc_state->cpu_transcoder); 4120 } 4121 4122 return transcoders; 4123 } 4124 4125 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 4126 struct intel_crtc_state *crtc_state, 4127 struct drm_connector_state *conn_state) 4128 { 4129 struct drm_connector *connector = conn_state->connector; 4130 u8 port_sync_transcoders = 0; 4131 4132 DRM_DEBUG_KMS("[ENCODER:%d:%s] [CRTC:%d:%s]", 4133 encoder->base.base.id, encoder->base.name, 4134 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4135 4136 if (connector->has_tile) 4137 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4138 connector->tile_group->id); 4139 4140 /* 4141 * EDP Transcoders cannot be ensalved 4142 * make them a master always when present 4143 */ 4144 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4145 crtc_state->master_transcoder = TRANSCODER_EDP; 4146 else 4147 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4148 4149 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4150 crtc_state->master_transcoder = INVALID_TRANSCODER; 4151 crtc_state->sync_mode_slaves_mask = 4152 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4153 } 4154 4155 return 0; 4156 } 4157 4158 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4159 { 4160 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4161 4162 intel_dp_encoder_flush_work(encoder); 4163 4164 drm_encoder_cleanup(encoder); 4165 kfree(dig_port); 4166 } 4167 4168 static const struct drm_encoder_funcs intel_ddi_funcs = { 4169 .reset = intel_dp_encoder_reset, 4170 .destroy = intel_ddi_encoder_destroy, 4171 }; 4172 4173 static struct intel_connector * 4174 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) 4175 { 4176 struct intel_connector *connector; 4177 enum port port = intel_dig_port->base.port; 4178 4179 connector = intel_connector_alloc(); 4180 if (!connector) 4181 return NULL; 4182 4183 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); 4184 intel_dig_port->dp.prepare_link_retrain = 4185 intel_ddi_prepare_link_retrain; 4186 4187 if (!intel_dp_init_connector(intel_dig_port, connector)) { 4188 kfree(connector); 4189 return NULL; 4190 } 4191 4192 return connector; 4193 } 4194 4195 static int modeset_pipe(struct drm_crtc *crtc, 4196 struct drm_modeset_acquire_ctx *ctx) 4197 { 4198 struct drm_atomic_state *state; 4199 struct drm_crtc_state *crtc_state; 4200 int ret; 4201 4202 state = drm_atomic_state_alloc(crtc->dev); 4203 if (!state) 4204 return -ENOMEM; 4205 4206 state->acquire_ctx = ctx; 4207 4208 crtc_state = drm_atomic_get_crtc_state(state, crtc); 4209 if (IS_ERR(crtc_state)) { 4210 ret = PTR_ERR(crtc_state); 4211 goto out; 4212 } 4213 4214 crtc_state->connectors_changed = true; 4215 4216 ret = drm_atomic_commit(state); 4217 out: 4218 drm_atomic_state_put(state); 4219 4220 return ret; 4221 } 4222 4223 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4224 struct drm_modeset_acquire_ctx *ctx) 4225 { 4226 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4227 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4228 struct intel_connector *connector = hdmi->attached_connector; 4229 struct i2c_adapter *adapter = 4230 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 4231 struct drm_connector_state *conn_state; 4232 struct intel_crtc_state *crtc_state; 4233 struct intel_crtc *crtc; 4234 u8 config; 4235 int ret; 4236 4237 if (!connector || connector->base.status != connector_status_connected) 4238 return 0; 4239 4240 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 4241 ctx); 4242 if (ret) 4243 return ret; 4244 4245 conn_state = connector->base.state; 4246 4247 crtc = to_intel_crtc(conn_state->crtc); 4248 if (!crtc) 4249 return 0; 4250 4251 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4252 if (ret) 4253 return ret; 4254 4255 crtc_state = to_intel_crtc_state(crtc->base.state); 4256 4257 drm_WARN_ON(&dev_priv->drm, 4258 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4259 4260 if (!crtc_state->hw.active) 4261 return 0; 4262 4263 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4264 !crtc_state->hdmi_scrambling) 4265 return 0; 4266 4267 if (conn_state->commit && 4268 !try_wait_for_completion(&conn_state->commit->hw_done)) 4269 return 0; 4270 4271 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 4272 if (ret < 0) { 4273 DRM_ERROR("Failed to read TMDS config: %d\n", ret); 4274 return 0; 4275 } 4276 4277 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4278 crtc_state->hdmi_high_tmds_clock_ratio && 4279 !!(config & SCDC_SCRAMBLING_ENABLE) == 4280 crtc_state->hdmi_scrambling) 4281 return 0; 4282 4283 /* 4284 * HDMI 2.0 says that one should not send scrambled data 4285 * prior to configuring the sink scrambling, and that 4286 * TMDS clock/data transmission should be suspended when 4287 * changing the TMDS clock rate in the sink. So let's 4288 * just do a full modeset here, even though some sinks 4289 * would be perfectly happy if were to just reconfigure 4290 * the SCDC settings on the fly. 4291 */ 4292 return modeset_pipe(&crtc->base, ctx); 4293 } 4294 4295 static enum intel_hotplug_state 4296 intel_ddi_hotplug(struct intel_encoder *encoder, 4297 struct intel_connector *connector, 4298 bool irq_received) 4299 { 4300 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4301 struct drm_modeset_acquire_ctx ctx; 4302 enum intel_hotplug_state state; 4303 int ret; 4304 4305 state = intel_encoder_hotplug(encoder, connector, irq_received); 4306 4307 drm_modeset_acquire_init(&ctx, 0); 4308 4309 for (;;) { 4310 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) 4311 ret = intel_hdmi_reset_link(encoder, &ctx); 4312 else 4313 ret = intel_dp_retrain_link(encoder, &ctx); 4314 4315 if (ret == -EDEADLK) { 4316 drm_modeset_backoff(&ctx); 4317 continue; 4318 } 4319 4320 break; 4321 } 4322 4323 drm_modeset_drop_locks(&ctx); 4324 drm_modeset_acquire_fini(&ctx); 4325 drm_WARN(encoder->base.dev, ret, 4326 "Acquiring modeset locks failed with %i\n", ret); 4327 4328 /* 4329 * Unpowered type-c dongles can take some time to boot and be 4330 * responsible, so here giving some time to those dongles to power up 4331 * and then retrying the probe. 4332 * 4333 * On many platforms the HDMI live state signal is known to be 4334 * unreliable, so we can't use it to detect if a sink is connected or 4335 * not. Instead we detect if it's connected based on whether we can 4336 * read the EDID or not. That in turn has a problem during disconnect, 4337 * since the HPD interrupt may be raised before the DDC lines get 4338 * disconnected (due to how the required length of DDC vs. HPD 4339 * connector pins are specified) and so we'll still be able to get a 4340 * valid EDID. To solve this schedule another detection cycle if this 4341 * time around we didn't detect any change in the sink's connection 4342 * status. 4343 */ 4344 if (state == INTEL_HOTPLUG_UNCHANGED && irq_received && 4345 !dig_port->dp.is_mst) 4346 state = INTEL_HOTPLUG_RETRY; 4347 4348 return state; 4349 } 4350 4351 static struct intel_connector * 4352 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) 4353 { 4354 struct intel_connector *connector; 4355 enum port port = intel_dig_port->base.port; 4356 4357 connector = intel_connector_alloc(); 4358 if (!connector) 4359 return NULL; 4360 4361 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4362 intel_hdmi_init_connector(intel_dig_port, connector); 4363 4364 return connector; 4365 } 4366 4367 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport) 4368 { 4369 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); 4370 4371 if (dport->base.port != PORT_A) 4372 return false; 4373 4374 if (dport->saved_port_bits & DDI_A_4_LANES) 4375 return false; 4376 4377 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4378 * supported configuration 4379 */ 4380 if (IS_GEN9_LP(dev_priv)) 4381 return true; 4382 4383 /* Cannonlake: Most of SKUs don't support DDI_E, and the only 4384 * one who does also have a full A/E split called 4385 * DDI_F what makes DDI_E useless. However for this 4386 * case let's trust VBT info. 4387 */ 4388 if (IS_CANNONLAKE(dev_priv) && 4389 !intel_bios_is_port_present(dev_priv, PORT_E)) 4390 return true; 4391 4392 return false; 4393 } 4394 4395 static int 4396 intel_ddi_max_lanes(struct intel_digital_port *intel_dport) 4397 { 4398 struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev); 4399 enum port port = intel_dport->base.port; 4400 int max_lanes = 4; 4401 4402 if (INTEL_GEN(dev_priv) >= 11) 4403 return max_lanes; 4404 4405 if (port == PORT_A || port == PORT_E) { 4406 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4407 max_lanes = port == PORT_A ? 4 : 0; 4408 else 4409 /* Both A and E share 2 lanes */ 4410 max_lanes = 2; 4411 } 4412 4413 /* 4414 * Some BIOS might fail to set this bit on port A if eDP 4415 * wasn't lit up at boot. Force this bit set when needed 4416 * so we use the proper lane count for our calculations. 4417 */ 4418 if (intel_ddi_a_force_4_lanes(intel_dport)) { 4419 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n"); 4420 intel_dport->saved_port_bits |= DDI_A_4_LANES; 4421 max_lanes = 4; 4422 } 4423 4424 return max_lanes; 4425 } 4426 4427 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 4428 { 4429 struct intel_digital_port *intel_dig_port; 4430 struct intel_encoder *encoder; 4431 bool init_hdmi, init_dp, init_lspcon = false; 4432 enum phy phy = intel_port_to_phy(dev_priv, port); 4433 4434 init_hdmi = intel_bios_port_supports_dvi(dev_priv, port) || 4435 intel_bios_port_supports_hdmi(dev_priv, port); 4436 init_dp = intel_bios_port_supports_dp(dev_priv, port); 4437 4438 if (intel_bios_is_lspcon_present(dev_priv, port)) { 4439 /* 4440 * Lspcon device needs to be driven with DP connector 4441 * with special detection sequence. So make sure DP 4442 * is initialized before lspcon. 4443 */ 4444 init_dp = true; 4445 init_lspcon = true; 4446 init_hdmi = false; 4447 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port)); 4448 } 4449 4450 if (!init_dp && !init_hdmi) { 4451 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 4452 port_name(port)); 4453 return; 4454 } 4455 4456 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 4457 if (!intel_dig_port) 4458 return; 4459 4460 encoder = &intel_dig_port->base; 4461 4462 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4463 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port)); 4464 4465 encoder->hotplug = intel_ddi_hotplug; 4466 encoder->compute_output_type = intel_ddi_compute_output_type; 4467 encoder->compute_config = intel_ddi_compute_config; 4468 encoder->compute_config_late = intel_ddi_compute_config_late; 4469 encoder->enable = intel_enable_ddi; 4470 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 4471 encoder->pre_enable = intel_ddi_pre_enable; 4472 encoder->disable = intel_disable_ddi; 4473 encoder->post_disable = intel_ddi_post_disable; 4474 encoder->update_pipe = intel_ddi_update_pipe; 4475 encoder->get_hw_state = intel_ddi_get_hw_state; 4476 encoder->get_config = intel_ddi_get_config; 4477 encoder->suspend = intel_dp_encoder_suspend; 4478 encoder->get_power_domains = intel_ddi_get_power_domains; 4479 4480 encoder->type = INTEL_OUTPUT_DDI; 4481 encoder->power_domain = intel_port_to_power_domain(port); 4482 encoder->port = port; 4483 encoder->cloneable = 0; 4484 encoder->pipe_mask = ~0; 4485 4486 if (INTEL_GEN(dev_priv) >= 11) 4487 intel_dig_port->saved_port_bits = intel_de_read(dev_priv, 4488 DDI_BUF_CTL(port)) & 4489 DDI_BUF_PORT_REVERSAL; 4490 else 4491 intel_dig_port->saved_port_bits = intel_de_read(dev_priv, 4492 DDI_BUF_CTL(port)) & 4493 (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 4494 4495 intel_dig_port->dp.output_reg = INVALID_MMIO_REG; 4496 intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port); 4497 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 4498 4499 if (intel_phy_is_tc(dev_priv, phy)) { 4500 bool is_legacy = 4501 !intel_bios_port_supports_typec_usb(dev_priv, port) && 4502 !intel_bios_port_supports_tbt(dev_priv, port); 4503 4504 intel_tc_port_init(intel_dig_port, is_legacy); 4505 4506 encoder->update_prepare = intel_ddi_update_prepare; 4507 encoder->update_complete = intel_ddi_update_complete; 4508 } 4509 4510 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 4511 intel_dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO + 4512 port - PORT_A; 4513 4514 if (init_dp) { 4515 if (!intel_ddi_init_dp_connector(intel_dig_port)) 4516 goto err; 4517 4518 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; 4519 } 4520 4521 /* In theory we don't need the encoder->type check, but leave it just in 4522 * case we have some really bad VBTs... */ 4523 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 4524 if (!intel_ddi_init_hdmi_connector(intel_dig_port)) 4525 goto err; 4526 } 4527 4528 if (init_lspcon) { 4529 if (lspcon_init(intel_dig_port)) 4530 /* TODO: handle hdmi info frame part */ 4531 DRM_DEBUG_KMS("LSPCON init success on port %c\n", 4532 port_name(port)); 4533 else 4534 /* 4535 * LSPCON init faied, but DP init was success, so 4536 * lets try to drive as DP++ port. 4537 */ 4538 DRM_ERROR("LSPCON init failed on port %c\n", 4539 port_name(port)); 4540 } 4541 4542 intel_infoframe_init(intel_dig_port); 4543 4544 return; 4545 4546 err: 4547 drm_encoder_cleanup(&encoder->base); 4548 kfree(intel_dig_port); 4549 } 4550