1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <drm/drm_scdc_helper.h> 29 30 #include "i915_drv.h" 31 #include "intel_audio.h" 32 #include "intel_combo_phy.h" 33 #include "intel_connector.h" 34 #include "intel_ddi.h" 35 #include "intel_display_types.h" 36 #include "intel_dp.h" 37 #include "intel_dp_link_training.h" 38 #include "intel_dpio_phy.h" 39 #include "intel_dsi.h" 40 #include "intel_fifo_underrun.h" 41 #include "intel_gmbus.h" 42 #include "intel_hdcp.h" 43 #include "intel_hdmi.h" 44 #include "intel_hotplug.h" 45 #include "intel_lspcon.h" 46 #include "intel_panel.h" 47 #include "intel_psr.h" 48 #include "intel_tc.h" 49 #include "intel_vdsc.h" 50 51 struct ddi_buf_trans { 52 u32 trans1; /* balance leg enable, de-emph level */ 53 u32 trans2; /* vref sel, vswing */ 54 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */ 55 }; 56 57 static const u8 index_to_dp_signal_levels[] = { 58 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 59 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 60 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 61 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 62 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 63 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 64 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 65 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 66 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 67 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 68 }; 69 70 /* HDMI/DVI modes ignore everything but the last 2 items. So we share 71 * them for both DP and FDI transports, allowing those ports to 72 * automatically adapt to HDMI connections as well 73 */ 74 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { 75 { 0x00FFFFFF, 0x0006000E, 0x0 }, 76 { 0x00D75FFF, 0x0005000A, 0x0 }, 77 { 0x00C30FFF, 0x00040006, 0x0 }, 78 { 0x80AAAFFF, 0x000B0000, 0x0 }, 79 { 0x00FFFFFF, 0x0005000A, 0x0 }, 80 { 0x00D75FFF, 0x000C0004, 0x0 }, 81 { 0x80C30FFF, 0x000B0000, 0x0 }, 82 { 0x00FFFFFF, 0x00040006, 0x0 }, 83 { 0x80D75FFF, 0x000B0000, 0x0 }, 84 }; 85 86 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { 87 { 0x00FFFFFF, 0x0007000E, 0x0 }, 88 { 0x00D75FFF, 0x000F000A, 0x0 }, 89 { 0x00C30FFF, 0x00060006, 0x0 }, 90 { 0x00AAAFFF, 0x001E0000, 0x0 }, 91 { 0x00FFFFFF, 0x000F000A, 0x0 }, 92 { 0x00D75FFF, 0x00160004, 0x0 }, 93 { 0x00C30FFF, 0x001E0000, 0x0 }, 94 { 0x00FFFFFF, 0x00060006, 0x0 }, 95 { 0x00D75FFF, 0x001E0000, 0x0 }, 96 }; 97 98 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { 99 /* Idx NT mV d T mV d db */ 100 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */ 101 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */ 102 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */ 103 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */ 104 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */ 105 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */ 106 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */ 107 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */ 108 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */ 109 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */ 110 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */ 111 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */ 112 }; 113 114 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { 115 { 0x00FFFFFF, 0x00000012, 0x0 }, 116 { 0x00EBAFFF, 0x00020011, 0x0 }, 117 { 0x00C71FFF, 0x0006000F, 0x0 }, 118 { 0x00AAAFFF, 0x000E000A, 0x0 }, 119 { 0x00FFFFFF, 0x00020011, 0x0 }, 120 { 0x00DB6FFF, 0x0005000F, 0x0 }, 121 { 0x00BEEFFF, 0x000A000C, 0x0 }, 122 { 0x00FFFFFF, 0x0005000F, 0x0 }, 123 { 0x00DB6FFF, 0x000A000C, 0x0 }, 124 }; 125 126 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { 127 { 0x00FFFFFF, 0x0007000E, 0x0 }, 128 { 0x00D75FFF, 0x000E000A, 0x0 }, 129 { 0x00BEFFFF, 0x00140006, 0x0 }, 130 { 0x80B2CFFF, 0x001B0002, 0x0 }, 131 { 0x00FFFFFF, 0x000E000A, 0x0 }, 132 { 0x00DB6FFF, 0x00160005, 0x0 }, 133 { 0x80C71FFF, 0x001A0002, 0x0 }, 134 { 0x00F7DFFF, 0x00180004, 0x0 }, 135 { 0x80D75FFF, 0x001B0002, 0x0 }, 136 }; 137 138 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { 139 { 0x00FFFFFF, 0x0001000E, 0x0 }, 140 { 0x00D75FFF, 0x0004000A, 0x0 }, 141 { 0x00C30FFF, 0x00070006, 0x0 }, 142 { 0x00AAAFFF, 0x000C0000, 0x0 }, 143 { 0x00FFFFFF, 0x0004000A, 0x0 }, 144 { 0x00D75FFF, 0x00090004, 0x0 }, 145 { 0x00C30FFF, 0x000C0000, 0x0 }, 146 { 0x00FFFFFF, 0x00070006, 0x0 }, 147 { 0x00D75FFF, 0x000C0000, 0x0 }, 148 }; 149 150 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { 151 /* Idx NT mV d T mV df db */ 152 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */ 153 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */ 154 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */ 155 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */ 156 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */ 157 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */ 158 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */ 159 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */ 160 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */ 161 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */ 162 }; 163 164 /* Skylake H and S */ 165 static const struct ddi_buf_trans skl_ddi_translations_dp[] = { 166 { 0x00002016, 0x000000A0, 0x0 }, 167 { 0x00005012, 0x0000009B, 0x0 }, 168 { 0x00007011, 0x00000088, 0x0 }, 169 { 0x80009010, 0x000000C0, 0x1 }, 170 { 0x00002016, 0x0000009B, 0x0 }, 171 { 0x00005012, 0x00000088, 0x0 }, 172 { 0x80007011, 0x000000C0, 0x1 }, 173 { 0x00002016, 0x000000DF, 0x0 }, 174 { 0x80005012, 0x000000C0, 0x1 }, 175 }; 176 177 /* Skylake U */ 178 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { 179 { 0x0000201B, 0x000000A2, 0x0 }, 180 { 0x00005012, 0x00000088, 0x0 }, 181 { 0x80007011, 0x000000CD, 0x1 }, 182 { 0x80009010, 0x000000C0, 0x1 }, 183 { 0x0000201B, 0x0000009D, 0x0 }, 184 { 0x80005012, 0x000000C0, 0x1 }, 185 { 0x80007011, 0x000000C0, 0x1 }, 186 { 0x00002016, 0x00000088, 0x0 }, 187 { 0x80005012, 0x000000C0, 0x1 }, 188 }; 189 190 /* Skylake Y */ 191 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { 192 { 0x00000018, 0x000000A2, 0x0 }, 193 { 0x00005012, 0x00000088, 0x0 }, 194 { 0x80007011, 0x000000CD, 0x3 }, 195 { 0x80009010, 0x000000C0, 0x3 }, 196 { 0x00000018, 0x0000009D, 0x0 }, 197 { 0x80005012, 0x000000C0, 0x3 }, 198 { 0x80007011, 0x000000C0, 0x3 }, 199 { 0x00000018, 0x00000088, 0x0 }, 200 { 0x80005012, 0x000000C0, 0x3 }, 201 }; 202 203 /* Kabylake H and S */ 204 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = { 205 { 0x00002016, 0x000000A0, 0x0 }, 206 { 0x00005012, 0x0000009B, 0x0 }, 207 { 0x00007011, 0x00000088, 0x0 }, 208 { 0x80009010, 0x000000C0, 0x1 }, 209 { 0x00002016, 0x0000009B, 0x0 }, 210 { 0x00005012, 0x00000088, 0x0 }, 211 { 0x80007011, 0x000000C0, 0x1 }, 212 { 0x00002016, 0x00000097, 0x0 }, 213 { 0x80005012, 0x000000C0, 0x1 }, 214 }; 215 216 /* Kabylake U */ 217 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = { 218 { 0x0000201B, 0x000000A1, 0x0 }, 219 { 0x00005012, 0x00000088, 0x0 }, 220 { 0x80007011, 0x000000CD, 0x3 }, 221 { 0x80009010, 0x000000C0, 0x3 }, 222 { 0x0000201B, 0x0000009D, 0x0 }, 223 { 0x80005012, 0x000000C0, 0x3 }, 224 { 0x80007011, 0x000000C0, 0x3 }, 225 { 0x00002016, 0x0000004F, 0x0 }, 226 { 0x80005012, 0x000000C0, 0x3 }, 227 }; 228 229 /* Kabylake Y */ 230 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = { 231 { 0x00001017, 0x000000A1, 0x0 }, 232 { 0x00005012, 0x00000088, 0x0 }, 233 { 0x80007011, 0x000000CD, 0x3 }, 234 { 0x8000800F, 0x000000C0, 0x3 }, 235 { 0x00001017, 0x0000009D, 0x0 }, 236 { 0x80005012, 0x000000C0, 0x3 }, 237 { 0x80007011, 0x000000C0, 0x3 }, 238 { 0x00001017, 0x0000004C, 0x0 }, 239 { 0x80005012, 0x000000C0, 0x3 }, 240 }; 241 242 /* 243 * Skylake/Kabylake H and S 244 * eDP 1.4 low vswing translation parameters 245 */ 246 static const struct ddi_buf_trans skl_ddi_translations_edp[] = { 247 { 0x00000018, 0x000000A8, 0x0 }, 248 { 0x00004013, 0x000000A9, 0x0 }, 249 { 0x00007011, 0x000000A2, 0x0 }, 250 { 0x00009010, 0x0000009C, 0x0 }, 251 { 0x00000018, 0x000000A9, 0x0 }, 252 { 0x00006013, 0x000000A2, 0x0 }, 253 { 0x00007011, 0x000000A6, 0x0 }, 254 { 0x00000018, 0x000000AB, 0x0 }, 255 { 0x00007013, 0x0000009F, 0x0 }, 256 { 0x00000018, 0x000000DF, 0x0 }, 257 }; 258 259 /* 260 * Skylake/Kabylake U 261 * eDP 1.4 low vswing translation parameters 262 */ 263 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = { 264 { 0x00000018, 0x000000A8, 0x0 }, 265 { 0x00004013, 0x000000A9, 0x0 }, 266 { 0x00007011, 0x000000A2, 0x0 }, 267 { 0x00009010, 0x0000009C, 0x0 }, 268 { 0x00000018, 0x000000A9, 0x0 }, 269 { 0x00006013, 0x000000A2, 0x0 }, 270 { 0x00007011, 0x000000A6, 0x0 }, 271 { 0x00002016, 0x000000AB, 0x0 }, 272 { 0x00005013, 0x0000009F, 0x0 }, 273 { 0x00000018, 0x000000DF, 0x0 }, 274 }; 275 276 /* 277 * Skylake/Kabylake Y 278 * eDP 1.4 low vswing translation parameters 279 */ 280 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = { 281 { 0x00000018, 0x000000A8, 0x0 }, 282 { 0x00004013, 0x000000AB, 0x0 }, 283 { 0x00007011, 0x000000A4, 0x0 }, 284 { 0x00009010, 0x000000DF, 0x0 }, 285 { 0x00000018, 0x000000AA, 0x0 }, 286 { 0x00006013, 0x000000A4, 0x0 }, 287 { 0x00007011, 0x0000009D, 0x0 }, 288 { 0x00000018, 0x000000A0, 0x0 }, 289 { 0x00006012, 0x000000DF, 0x0 }, 290 { 0x00000018, 0x0000008A, 0x0 }, 291 }; 292 293 /* Skylake/Kabylake U, H and S */ 294 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { 295 { 0x00000018, 0x000000AC, 0x0 }, 296 { 0x00005012, 0x0000009D, 0x0 }, 297 { 0x00007011, 0x00000088, 0x0 }, 298 { 0x00000018, 0x000000A1, 0x0 }, 299 { 0x00000018, 0x00000098, 0x0 }, 300 { 0x00004013, 0x00000088, 0x0 }, 301 { 0x80006012, 0x000000CD, 0x1 }, 302 { 0x00000018, 0x000000DF, 0x0 }, 303 { 0x80003015, 0x000000CD, 0x1 }, /* Default */ 304 { 0x80003015, 0x000000C0, 0x1 }, 305 { 0x80000018, 0x000000C0, 0x1 }, 306 }; 307 308 /* Skylake/Kabylake Y */ 309 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { 310 { 0x00000018, 0x000000A1, 0x0 }, 311 { 0x00005012, 0x000000DF, 0x0 }, 312 { 0x80007011, 0x000000CB, 0x3 }, 313 { 0x00000018, 0x000000A4, 0x0 }, 314 { 0x00000018, 0x0000009D, 0x0 }, 315 { 0x00004013, 0x00000080, 0x0 }, 316 { 0x80006013, 0x000000C0, 0x3 }, 317 { 0x00000018, 0x0000008A, 0x0 }, 318 { 0x80003015, 0x000000C0, 0x3 }, /* Default */ 319 { 0x80003015, 0x000000C0, 0x3 }, 320 { 0x80000018, 0x000000C0, 0x3 }, 321 }; 322 323 struct bxt_ddi_buf_trans { 324 u8 margin; /* swing value */ 325 u8 scale; /* scale value */ 326 u8 enable; /* scale enable */ 327 u8 deemphasis; 328 }; 329 330 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { 331 /* Idx NT mV diff db */ 332 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ 333 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */ 334 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */ 335 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */ 336 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */ 337 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */ 338 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */ 339 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */ 340 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */ 341 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */ 342 }; 343 344 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = { 345 /* Idx NT mV diff db */ 346 { 26, 0, 0, 128, }, /* 0: 200 0 */ 347 { 38, 0, 0, 112, }, /* 1: 200 1.5 */ 348 { 48, 0, 0, 96, }, /* 2: 200 4 */ 349 { 54, 0, 0, 69, }, /* 3: 200 6 */ 350 { 32, 0, 0, 128, }, /* 4: 250 0 */ 351 { 48, 0, 0, 104, }, /* 5: 250 1.5 */ 352 { 54, 0, 0, 85, }, /* 6: 250 4 */ 353 { 43, 0, 0, 128, }, /* 7: 300 0 */ 354 { 54, 0, 0, 101, }, /* 8: 300 1.5 */ 355 { 48, 0, 0, 128, }, /* 9: 300 0 */ 356 }; 357 358 /* BSpec has 2 recommended values - entries 0 and 8. 359 * Using the entry with higher vswing. 360 */ 361 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = { 362 /* Idx NT mV diff db */ 363 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ 364 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */ 365 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */ 366 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */ 367 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */ 368 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */ 369 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */ 370 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */ 371 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */ 372 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */ 373 }; 374 375 struct cnl_ddi_buf_trans { 376 u8 dw2_swing_sel; 377 u8 dw7_n_scalar; 378 u8 dw4_cursor_coeff; 379 u8 dw4_post_cursor_2; 380 u8 dw4_post_cursor_1; 381 }; 382 383 /* Voltage Swing Programming for VccIO 0.85V for DP */ 384 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = { 385 /* NT mV Trans mV db */ 386 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 387 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ 388 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ 389 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ 390 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 391 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 392 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 393 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ 394 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ 395 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 396 }; 397 398 /* Voltage Swing Programming for VccIO 0.85V for HDMI */ 399 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = { 400 /* NT mV Trans mV db */ 401 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 402 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ 403 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ 404 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */ 405 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ 406 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ 407 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 408 }; 409 410 /* Voltage Swing Programming for VccIO 0.85V for eDP */ 411 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = { 412 /* NT mV Trans mV db */ 413 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 414 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 415 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 416 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 417 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 418 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 419 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */ 420 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */ 421 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 422 }; 423 424 /* Voltage Swing Programming for VccIO 0.95V for DP */ 425 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = { 426 /* NT mV Trans mV db */ 427 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 428 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ 429 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ 430 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ 431 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 432 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 433 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 434 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ 435 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ 436 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 437 }; 438 439 /* Voltage Swing Programming for VccIO 0.95V for HDMI */ 440 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = { 441 /* NT mV Trans mV db */ 442 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 443 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 444 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 445 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 446 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 447 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 448 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ 449 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ 450 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ 451 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ 452 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 453 }; 454 455 /* Voltage Swing Programming for VccIO 0.95V for eDP */ 456 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = { 457 /* NT mV Trans mV db */ 458 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 459 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 460 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 461 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 462 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 463 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 464 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ 465 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ 466 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */ 467 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 468 }; 469 470 /* Voltage Swing Programming for VccIO 1.05V for DP */ 471 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = { 472 /* NT mV Trans mV db */ 473 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 474 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 475 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 476 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */ 477 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 478 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 479 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */ 480 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */ 481 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */ 482 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 483 }; 484 485 /* Voltage Swing Programming for VccIO 1.05V for HDMI */ 486 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = { 487 /* NT mV Trans mV db */ 488 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 489 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 490 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 491 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 492 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 493 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 494 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ 495 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ 496 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ 497 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ 498 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 499 }; 500 501 /* Voltage Swing Programming for VccIO 1.05V for eDP */ 502 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = { 503 /* NT mV Trans mV db */ 504 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 505 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 506 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 507 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 508 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 509 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 510 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ 511 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ 512 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 513 }; 514 515 /* icl_combo_phy_ddi_translations */ 516 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = { 517 /* NT mV Trans mV db */ 518 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 519 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 520 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 521 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 522 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 523 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 524 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 525 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 526 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 527 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 528 }; 529 530 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = { 531 /* NT mV Trans mV db */ 532 { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ 533 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */ 534 { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */ 535 { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */ 536 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ 537 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */ 538 { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */ 539 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ 540 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ 541 { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 542 }; 543 544 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = { 545 /* NT mV Trans mV db */ 546 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 547 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 548 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 549 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 550 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 551 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 552 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 553 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 554 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 555 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 556 }; 557 558 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = { 559 /* NT mV Trans mV db */ 560 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 561 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ 562 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ 563 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */ 564 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ 565 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ 566 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 567 }; 568 569 struct icl_mg_phy_ddi_buf_trans { 570 u32 cri_txdeemph_override_5_0; 571 u32 cri_txdeemph_override_11_6; 572 u32 cri_txdeemph_override_17_12; 573 }; 574 575 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = { 576 /* Voltage swing pre-emphasis */ 577 { 0x0, 0x1B, 0x00 }, /* 0 0 */ 578 { 0x0, 0x23, 0x08 }, /* 0 1 */ 579 { 0x0, 0x2D, 0x12 }, /* 0 2 */ 580 { 0x0, 0x00, 0x00 }, /* 0 3 */ 581 { 0x0, 0x23, 0x00 }, /* 1 0 */ 582 { 0x0, 0x2B, 0x09 }, /* 1 1 */ 583 { 0x0, 0x2E, 0x11 }, /* 1 2 */ 584 { 0x0, 0x2F, 0x00 }, /* 2 0 */ 585 { 0x0, 0x33, 0x0C }, /* 2 1 */ 586 { 0x0, 0x00, 0x00 }, /* 3 0 */ 587 }; 588 589 struct tgl_dkl_phy_ddi_buf_trans { 590 u32 dkl_vswing_control; 591 u32 dkl_preshoot_control; 592 u32 dkl_de_emphasis_control; 593 }; 594 595 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_ddi_translations[] = { 596 /* VS pre-emp Non-trans mV Pre-emph dB */ 597 { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */ 598 { 0x5, 0x0, 0x03 }, /* 0 1 400mV 3.5 dB */ 599 { 0x2, 0x0, 0x0b }, /* 0 2 400mV 6 dB */ 600 { 0x0, 0x0, 0x19 }, /* 0 3 400mV 9.5 dB */ 601 { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */ 602 { 0x2, 0x0, 0x03 }, /* 1 1 600mV 3.5 dB */ 603 { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */ 604 { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */ 605 { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */ 606 { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */ 607 }; 608 609 static const struct ddi_buf_trans * 610 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 611 { 612 if (dev_priv->vbt.edp.low_vswing) { 613 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp); 614 return bdw_ddi_translations_edp; 615 } else { 616 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 617 return bdw_ddi_translations_dp; 618 } 619 } 620 621 static const struct ddi_buf_trans * 622 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 623 { 624 if (IS_SKL_ULX(dev_priv)) { 625 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); 626 return skl_y_ddi_translations_dp; 627 } else if (IS_SKL_ULT(dev_priv)) { 628 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); 629 return skl_u_ddi_translations_dp; 630 } else { 631 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); 632 return skl_ddi_translations_dp; 633 } 634 } 635 636 static const struct ddi_buf_trans * 637 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 638 { 639 if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv)) { 640 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp); 641 return kbl_y_ddi_translations_dp; 642 } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) { 643 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp); 644 return kbl_u_ddi_translations_dp; 645 } else { 646 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp); 647 return kbl_ddi_translations_dp; 648 } 649 } 650 651 static const struct ddi_buf_trans * 652 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 653 { 654 if (dev_priv->vbt.edp.low_vswing) { 655 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || 656 IS_CFL_ULX(dev_priv)) { 657 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); 658 return skl_y_ddi_translations_edp; 659 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) || 660 IS_CFL_ULT(dev_priv)) { 661 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); 662 return skl_u_ddi_translations_edp; 663 } else { 664 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp); 665 return skl_ddi_translations_edp; 666 } 667 } 668 669 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) 670 return kbl_get_buf_trans_dp(dev_priv, n_entries); 671 else 672 return skl_get_buf_trans_dp(dev_priv, n_entries); 673 } 674 675 static const struct ddi_buf_trans * 676 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) 677 { 678 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || 679 IS_CFL_ULX(dev_priv)) { 680 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); 681 return skl_y_ddi_translations_hdmi; 682 } else { 683 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); 684 return skl_ddi_translations_hdmi; 685 } 686 } 687 688 static int skl_buf_trans_num_entries(enum port port, int n_entries) 689 { 690 /* Only DDIA and DDIE can select the 10th register with DP */ 691 if (port == PORT_A || port == PORT_E) 692 return min(n_entries, 10); 693 else 694 return min(n_entries, 9); 695 } 696 697 static const struct ddi_buf_trans * 698 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv, 699 enum port port, int *n_entries) 700 { 701 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) { 702 const struct ddi_buf_trans *ddi_translations = 703 kbl_get_buf_trans_dp(dev_priv, n_entries); 704 *n_entries = skl_buf_trans_num_entries(port, *n_entries); 705 return ddi_translations; 706 } else if (IS_SKYLAKE(dev_priv)) { 707 const struct ddi_buf_trans *ddi_translations = 708 skl_get_buf_trans_dp(dev_priv, n_entries); 709 *n_entries = skl_buf_trans_num_entries(port, *n_entries); 710 return ddi_translations; 711 } else if (IS_BROADWELL(dev_priv)) { 712 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 713 return bdw_ddi_translations_dp; 714 } else if (IS_HASWELL(dev_priv)) { 715 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 716 return hsw_ddi_translations_dp; 717 } 718 719 *n_entries = 0; 720 return NULL; 721 } 722 723 static const struct ddi_buf_trans * 724 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv, 725 enum port port, int *n_entries) 726 { 727 if (IS_GEN9_BC(dev_priv)) { 728 const struct ddi_buf_trans *ddi_translations = 729 skl_get_buf_trans_edp(dev_priv, n_entries); 730 *n_entries = skl_buf_trans_num_entries(port, *n_entries); 731 return ddi_translations; 732 } else if (IS_BROADWELL(dev_priv)) { 733 return bdw_get_buf_trans_edp(dev_priv, n_entries); 734 } else if (IS_HASWELL(dev_priv)) { 735 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 736 return hsw_ddi_translations_dp; 737 } 738 739 *n_entries = 0; 740 return NULL; 741 } 742 743 static const struct ddi_buf_trans * 744 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, 745 int *n_entries) 746 { 747 if (IS_BROADWELL(dev_priv)) { 748 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi); 749 return bdw_ddi_translations_fdi; 750 } else if (IS_HASWELL(dev_priv)) { 751 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi); 752 return hsw_ddi_translations_fdi; 753 } 754 755 *n_entries = 0; 756 return NULL; 757 } 758 759 static const struct ddi_buf_trans * 760 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, 761 int *n_entries) 762 { 763 if (IS_GEN9_BC(dev_priv)) { 764 return skl_get_buf_trans_hdmi(dev_priv, n_entries); 765 } else if (IS_BROADWELL(dev_priv)) { 766 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 767 return bdw_ddi_translations_hdmi; 768 } else if (IS_HASWELL(dev_priv)) { 769 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); 770 return hsw_ddi_translations_hdmi; 771 } 772 773 *n_entries = 0; 774 return NULL; 775 } 776 777 static const struct bxt_ddi_buf_trans * 778 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 779 { 780 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); 781 return bxt_ddi_translations_dp; 782 } 783 784 static const struct bxt_ddi_buf_trans * 785 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 786 { 787 if (dev_priv->vbt.edp.low_vswing) { 788 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp); 789 return bxt_ddi_translations_edp; 790 } 791 792 return bxt_get_buf_trans_dp(dev_priv, n_entries); 793 } 794 795 static const struct bxt_ddi_buf_trans * 796 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) 797 { 798 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); 799 return bxt_ddi_translations_hdmi; 800 } 801 802 static const struct cnl_ddi_buf_trans * 803 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) 804 { 805 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 806 807 if (voltage == VOLTAGE_INFO_0_85V) { 808 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V); 809 return cnl_ddi_translations_hdmi_0_85V; 810 } else if (voltage == VOLTAGE_INFO_0_95V) { 811 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V); 812 return cnl_ddi_translations_hdmi_0_95V; 813 } else if (voltage == VOLTAGE_INFO_1_05V) { 814 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V); 815 return cnl_ddi_translations_hdmi_1_05V; 816 } else { 817 *n_entries = 1; /* shut up gcc */ 818 MISSING_CASE(voltage); 819 } 820 return NULL; 821 } 822 823 static const struct cnl_ddi_buf_trans * 824 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 825 { 826 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 827 828 if (voltage == VOLTAGE_INFO_0_85V) { 829 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V); 830 return cnl_ddi_translations_dp_0_85V; 831 } else if (voltage == VOLTAGE_INFO_0_95V) { 832 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V); 833 return cnl_ddi_translations_dp_0_95V; 834 } else if (voltage == VOLTAGE_INFO_1_05V) { 835 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V); 836 return cnl_ddi_translations_dp_1_05V; 837 } else { 838 *n_entries = 1; /* shut up gcc */ 839 MISSING_CASE(voltage); 840 } 841 return NULL; 842 } 843 844 static const struct cnl_ddi_buf_trans * 845 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 846 { 847 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 848 849 if (dev_priv->vbt.edp.low_vswing) { 850 if (voltage == VOLTAGE_INFO_0_85V) { 851 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V); 852 return cnl_ddi_translations_edp_0_85V; 853 } else if (voltage == VOLTAGE_INFO_0_95V) { 854 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V); 855 return cnl_ddi_translations_edp_0_95V; 856 } else if (voltage == VOLTAGE_INFO_1_05V) { 857 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V); 858 return cnl_ddi_translations_edp_1_05V; 859 } else { 860 *n_entries = 1; /* shut up gcc */ 861 MISSING_CASE(voltage); 862 } 863 return NULL; 864 } else { 865 return cnl_get_buf_trans_dp(dev_priv, n_entries); 866 } 867 } 868 869 static const struct cnl_ddi_buf_trans * 870 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, 871 int *n_entries) 872 { 873 if (type == INTEL_OUTPUT_HDMI) { 874 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); 875 return icl_combo_phy_ddi_translations_hdmi; 876 } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) { 877 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3); 878 return icl_combo_phy_ddi_translations_edp_hbr3; 879 } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) { 880 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2); 881 return icl_combo_phy_ddi_translations_edp_hbr2; 882 } 883 884 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2); 885 return icl_combo_phy_ddi_translations_dp_hbr2; 886 } 887 888 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port) 889 { 890 int n_entries, level, default_entry; 891 enum phy phy = intel_port_to_phy(dev_priv, port); 892 893 level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; 894 895 if (INTEL_GEN(dev_priv) >= 12) { 896 if (intel_phy_is_combo(dev_priv, phy)) 897 icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 898 0, &n_entries); 899 else 900 n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations); 901 default_entry = n_entries - 1; 902 } else if (INTEL_GEN(dev_priv) == 11) { 903 if (intel_phy_is_combo(dev_priv, phy)) 904 icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 905 0, &n_entries); 906 else 907 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations); 908 default_entry = n_entries - 1; 909 } else if (IS_CANNONLAKE(dev_priv)) { 910 cnl_get_buf_trans_hdmi(dev_priv, &n_entries); 911 default_entry = n_entries - 1; 912 } else if (IS_GEN9_LP(dev_priv)) { 913 bxt_get_buf_trans_hdmi(dev_priv, &n_entries); 914 default_entry = n_entries - 1; 915 } else if (IS_GEN9_BC(dev_priv)) { 916 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 917 default_entry = 8; 918 } else if (IS_BROADWELL(dev_priv)) { 919 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 920 default_entry = 7; 921 } else if (IS_HASWELL(dev_priv)) { 922 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 923 default_entry = 6; 924 } else { 925 WARN(1, "ddi translation table missing\n"); 926 return 0; 927 } 928 929 /* Choose a good default if VBT is badly populated */ 930 if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries) 931 level = default_entry; 932 933 if (WARN_ON_ONCE(n_entries == 0)) 934 return 0; 935 if (WARN_ON_ONCE(level >= n_entries)) 936 level = n_entries - 1; 937 938 return level; 939 } 940 941 /* 942 * Starting with Haswell, DDI port buffers must be programmed with correct 943 * values in advance. This function programs the correct values for 944 * DP/eDP/FDI use cases. 945 */ 946 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 947 const struct intel_crtc_state *crtc_state) 948 { 949 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 950 u32 iboost_bit = 0; 951 int i, n_entries; 952 enum port port = encoder->port; 953 const struct ddi_buf_trans *ddi_translations; 954 955 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) 956 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv, 957 &n_entries); 958 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 959 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, 960 &n_entries); 961 else 962 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, 963 &n_entries); 964 965 /* If we're boosting the current, set bit 31 of trans1 */ 966 if (IS_GEN9_BC(dev_priv) && 967 dev_priv->vbt.ddi_port_info[port].dp_boost_level) 968 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 969 970 for (i = 0; i < n_entries; i++) { 971 I915_WRITE(DDI_BUF_TRANS_LO(port, i), 972 ddi_translations[i].trans1 | iboost_bit); 973 I915_WRITE(DDI_BUF_TRANS_HI(port, i), 974 ddi_translations[i].trans2); 975 } 976 } 977 978 /* 979 * Starting with Haswell, DDI port buffers must be programmed with correct 980 * values in advance. This function programs the correct values for 981 * HDMI/DVI use cases. 982 */ 983 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 984 int level) 985 { 986 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 987 u32 iboost_bit = 0; 988 int n_entries; 989 enum port port = encoder->port; 990 const struct ddi_buf_trans *ddi_translations; 991 992 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 993 994 if (WARN_ON_ONCE(!ddi_translations)) 995 return; 996 if (WARN_ON_ONCE(level >= n_entries)) 997 level = n_entries - 1; 998 999 /* If we're boosting the current, set bit 31 of trans1 */ 1000 if (IS_GEN9_BC(dev_priv) && 1001 dev_priv->vbt.ddi_port_info[port].hdmi_boost_level) 1002 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 1003 1004 /* Entry 9 is for HDMI: */ 1005 I915_WRITE(DDI_BUF_TRANS_LO(port, 9), 1006 ddi_translations[level].trans1 | iboost_bit); 1007 I915_WRITE(DDI_BUF_TRANS_HI(port, 9), 1008 ddi_translations[level].trans2); 1009 } 1010 1011 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 1012 enum port port) 1013 { 1014 i915_reg_t reg = DDI_BUF_CTL(port); 1015 int i; 1016 1017 for (i = 0; i < 16; i++) { 1018 udelay(1); 1019 if (I915_READ(reg) & DDI_BUF_IS_IDLE) 1020 return; 1021 } 1022 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); 1023 } 1024 1025 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 1026 { 1027 switch (pll->info->id) { 1028 case DPLL_ID_WRPLL1: 1029 return PORT_CLK_SEL_WRPLL1; 1030 case DPLL_ID_WRPLL2: 1031 return PORT_CLK_SEL_WRPLL2; 1032 case DPLL_ID_SPLL: 1033 return PORT_CLK_SEL_SPLL; 1034 case DPLL_ID_LCPLL_810: 1035 return PORT_CLK_SEL_LCPLL_810; 1036 case DPLL_ID_LCPLL_1350: 1037 return PORT_CLK_SEL_LCPLL_1350; 1038 case DPLL_ID_LCPLL_2700: 1039 return PORT_CLK_SEL_LCPLL_2700; 1040 default: 1041 MISSING_CASE(pll->info->id); 1042 return PORT_CLK_SEL_NONE; 1043 } 1044 } 1045 1046 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 1047 const struct intel_crtc_state *crtc_state) 1048 { 1049 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1050 int clock = crtc_state->port_clock; 1051 const enum intel_dpll_id id = pll->info->id; 1052 1053 switch (id) { 1054 default: 1055 /* 1056 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 1057 * here, so do warn if this get passed in 1058 */ 1059 MISSING_CASE(id); 1060 return DDI_CLK_SEL_NONE; 1061 case DPLL_ID_ICL_TBTPLL: 1062 switch (clock) { 1063 case 162000: 1064 return DDI_CLK_SEL_TBT_162; 1065 case 270000: 1066 return DDI_CLK_SEL_TBT_270; 1067 case 540000: 1068 return DDI_CLK_SEL_TBT_540; 1069 case 810000: 1070 return DDI_CLK_SEL_TBT_810; 1071 default: 1072 MISSING_CASE(clock); 1073 return DDI_CLK_SEL_NONE; 1074 } 1075 case DPLL_ID_ICL_MGPLL1: 1076 case DPLL_ID_ICL_MGPLL2: 1077 case DPLL_ID_ICL_MGPLL3: 1078 case DPLL_ID_ICL_MGPLL4: 1079 case DPLL_ID_TGL_MGPLL5: 1080 case DPLL_ID_TGL_MGPLL6: 1081 return DDI_CLK_SEL_MG; 1082 } 1083 } 1084 1085 /* Starting with Haswell, different DDI ports can work in FDI mode for 1086 * connection to the PCH-located connectors. For this, it is necessary to train 1087 * both the DDI port and PCH receiver for the desired DDI buffer settings. 1088 * 1089 * The recommended port to work in FDI mode is DDI E, which we use here. Also, 1090 * please note that when FDI mode is active on DDI E, it shares 2 lines with 1091 * DDI A (which is used for eDP) 1092 */ 1093 1094 void hsw_fdi_link_train(struct intel_crtc *crtc, 1095 const struct intel_crtc_state *crtc_state) 1096 { 1097 struct drm_device *dev = crtc->base.dev; 1098 struct drm_i915_private *dev_priv = to_i915(dev); 1099 struct intel_encoder *encoder; 1100 u32 temp, i, rx_ctl_val, ddi_pll_sel; 1101 1102 for_each_encoder_on_crtc(dev, &crtc->base, encoder) { 1103 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG); 1104 intel_prepare_dp_ddi_buffers(encoder, crtc_state); 1105 } 1106 1107 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the 1108 * mode set "sequence for CRT port" document: 1109 * - TP1 to TP2 time with the default value 1110 * - FDI delay to 90h 1111 * 1112 * WaFDIAutoLinkSetTimingOverrride:hsw 1113 */ 1114 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) | 1115 FDI_RX_PWRDN_LANE0_VAL(2) | 1116 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 1117 1118 /* Enable the PCH Receiver FDI PLL */ 1119 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | 1120 FDI_RX_PLL_ENABLE | 1121 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); 1122 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 1123 POSTING_READ(FDI_RX_CTL(PIPE_A)); 1124 udelay(220); 1125 1126 /* Switch from Rawclk to PCDclk */ 1127 rx_ctl_val |= FDI_PCDCLK; 1128 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 1129 1130 /* Configure Port Clock Select */ 1131 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll); 1132 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel); 1133 WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL); 1134 1135 /* Start the training iterating through available voltages and emphasis, 1136 * testing each value twice. */ 1137 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { 1138 /* Configure DP_TP_CTL with auto-training */ 1139 I915_WRITE(DP_TP_CTL(PORT_E), 1140 DP_TP_CTL_FDI_AUTOTRAIN | 1141 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 1142 DP_TP_CTL_LINK_TRAIN_PAT1 | 1143 DP_TP_CTL_ENABLE); 1144 1145 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. 1146 * DDI E does not support port reversal, the functionality is 1147 * achieved on the PCH side in FDI_RX_CTL, so no need to set the 1148 * port reversal bit */ 1149 I915_WRITE(DDI_BUF_CTL(PORT_E), 1150 DDI_BUF_CTL_ENABLE | 1151 ((crtc_state->fdi_lanes - 1) << 1) | 1152 DDI_BUF_TRANS_SELECT(i / 2)); 1153 POSTING_READ(DDI_BUF_CTL(PORT_E)); 1154 1155 udelay(600); 1156 1157 /* Program PCH FDI Receiver TU */ 1158 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); 1159 1160 /* Enable PCH FDI Receiver with auto-training */ 1161 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; 1162 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 1163 POSTING_READ(FDI_RX_CTL(PIPE_A)); 1164 1165 /* Wait for FDI receiver lane calibration */ 1166 udelay(30); 1167 1168 /* Unset FDI_RX_MISC pwrdn lanes */ 1169 temp = I915_READ(FDI_RX_MISC(PIPE_A)); 1170 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 1171 I915_WRITE(FDI_RX_MISC(PIPE_A), temp); 1172 POSTING_READ(FDI_RX_MISC(PIPE_A)); 1173 1174 /* Wait for FDI auto training time */ 1175 udelay(5); 1176 1177 temp = I915_READ(DP_TP_STATUS(PORT_E)); 1178 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { 1179 DRM_DEBUG_KMS("FDI link training done on step %d\n", i); 1180 break; 1181 } 1182 1183 /* 1184 * Leave things enabled even if we failed to train FDI. 1185 * Results in less fireworks from the state checker. 1186 */ 1187 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) { 1188 DRM_ERROR("FDI link training failed!\n"); 1189 break; 1190 } 1191 1192 rx_ctl_val &= ~FDI_RX_ENABLE; 1193 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 1194 POSTING_READ(FDI_RX_CTL(PIPE_A)); 1195 1196 temp = I915_READ(DDI_BUF_CTL(PORT_E)); 1197 temp &= ~DDI_BUF_CTL_ENABLE; 1198 I915_WRITE(DDI_BUF_CTL(PORT_E), temp); 1199 POSTING_READ(DDI_BUF_CTL(PORT_E)); 1200 1201 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ 1202 temp = I915_READ(DP_TP_CTL(PORT_E)); 1203 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 1204 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 1205 I915_WRITE(DP_TP_CTL(PORT_E), temp); 1206 POSTING_READ(DP_TP_CTL(PORT_E)); 1207 1208 intel_wait_ddi_buf_idle(dev_priv, PORT_E); 1209 1210 /* Reset FDI_RX_MISC pwrdn lanes */ 1211 temp = I915_READ(FDI_RX_MISC(PIPE_A)); 1212 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 1213 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 1214 I915_WRITE(FDI_RX_MISC(PIPE_A), temp); 1215 POSTING_READ(FDI_RX_MISC(PIPE_A)); 1216 } 1217 1218 /* Enable normal pixel sending for FDI */ 1219 I915_WRITE(DP_TP_CTL(PORT_E), 1220 DP_TP_CTL_FDI_AUTOTRAIN | 1221 DP_TP_CTL_LINK_TRAIN_NORMAL | 1222 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 1223 DP_TP_CTL_ENABLE); 1224 } 1225 1226 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) 1227 { 1228 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1229 struct intel_digital_port *intel_dig_port = 1230 enc_to_dig_port(&encoder->base); 1231 1232 intel_dp->DP = intel_dig_port->saved_port_bits | 1233 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); 1234 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); 1235 } 1236 1237 static struct intel_encoder * 1238 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc) 1239 { 1240 struct drm_device *dev = crtc->base.dev; 1241 struct intel_encoder *encoder, *ret = NULL; 1242 int num_encoders = 0; 1243 1244 for_each_encoder_on_crtc(dev, &crtc->base, encoder) { 1245 ret = encoder; 1246 num_encoders++; 1247 } 1248 1249 if (num_encoders != 1) 1250 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, 1251 pipe_name(crtc->pipe)); 1252 1253 BUG_ON(ret == NULL); 1254 return ret; 1255 } 1256 1257 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, 1258 i915_reg_t reg) 1259 { 1260 int refclk; 1261 int n, p, r; 1262 u32 wrpll; 1263 1264 wrpll = I915_READ(reg); 1265 switch (wrpll & WRPLL_REF_MASK) { 1266 case WRPLL_REF_SPECIAL_HSW: 1267 /* 1268 * muxed-SSC for BDW. 1269 * non-SSC for non-ULT HSW. Check FUSE_STRAP3 1270 * for the non-SSC reference frequency. 1271 */ 1272 if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) { 1273 if (I915_READ(FUSE_STRAP3) & HSW_REF_CLK_SELECT) 1274 refclk = 24; 1275 else 1276 refclk = 135; 1277 break; 1278 } 1279 /* fall through */ 1280 case WRPLL_REF_PCH_SSC: 1281 /* 1282 * We could calculate spread here, but our checking 1283 * code only cares about 5% accuracy, and spread is a max of 1284 * 0.5% downspread. 1285 */ 1286 refclk = 135; 1287 break; 1288 case WRPLL_REF_LCPLL: 1289 refclk = 2700; 1290 break; 1291 default: 1292 MISSING_CASE(wrpll); 1293 return 0; 1294 } 1295 1296 r = wrpll & WRPLL_DIVIDER_REF_MASK; 1297 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; 1298 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; 1299 1300 /* Convert to KHz, p & r have a fixed point portion */ 1301 return (refclk * n * 100) / (p * r); 1302 } 1303 1304 static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state) 1305 { 1306 u32 p0, p1, p2, dco_freq; 1307 1308 p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK; 1309 p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK; 1310 1311 if (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_MODE(1)) 1312 p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; 1313 else 1314 p1 = 1; 1315 1316 1317 switch (p0) { 1318 case DPLL_CFGCR2_PDIV_1: 1319 p0 = 1; 1320 break; 1321 case DPLL_CFGCR2_PDIV_2: 1322 p0 = 2; 1323 break; 1324 case DPLL_CFGCR2_PDIV_3: 1325 p0 = 3; 1326 break; 1327 case DPLL_CFGCR2_PDIV_7: 1328 p0 = 7; 1329 break; 1330 } 1331 1332 switch (p2) { 1333 case DPLL_CFGCR2_KDIV_5: 1334 p2 = 5; 1335 break; 1336 case DPLL_CFGCR2_KDIV_2: 1337 p2 = 2; 1338 break; 1339 case DPLL_CFGCR2_KDIV_3: 1340 p2 = 3; 1341 break; 1342 case DPLL_CFGCR2_KDIV_1: 1343 p2 = 1; 1344 break; 1345 } 1346 1347 dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK) 1348 * 24 * 1000; 1349 1350 dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) 1351 * 24 * 1000) / 0x8000; 1352 1353 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0)) 1354 return 0; 1355 1356 return dco_freq / (p0 * p1 * p2 * 5); 1357 } 1358 1359 int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv, 1360 struct intel_dpll_hw_state *pll_state) 1361 { 1362 u32 p0, p1, p2, dco_freq, ref_clock; 1363 1364 p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK; 1365 p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK; 1366 1367 if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1)) 1368 p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >> 1369 DPLL_CFGCR1_QDIV_RATIO_SHIFT; 1370 else 1371 p1 = 1; 1372 1373 1374 switch (p0) { 1375 case DPLL_CFGCR1_PDIV_2: 1376 p0 = 2; 1377 break; 1378 case DPLL_CFGCR1_PDIV_3: 1379 p0 = 3; 1380 break; 1381 case DPLL_CFGCR1_PDIV_5: 1382 p0 = 5; 1383 break; 1384 case DPLL_CFGCR1_PDIV_7: 1385 p0 = 7; 1386 break; 1387 } 1388 1389 switch (p2) { 1390 case DPLL_CFGCR1_KDIV_1: 1391 p2 = 1; 1392 break; 1393 case DPLL_CFGCR1_KDIV_2: 1394 p2 = 2; 1395 break; 1396 case DPLL_CFGCR1_KDIV_3: 1397 p2 = 3; 1398 break; 1399 } 1400 1401 ref_clock = cnl_hdmi_pll_ref_clock(dev_priv); 1402 1403 dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) 1404 * ref_clock; 1405 1406 dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >> 1407 DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000; 1408 1409 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0)) 1410 return 0; 1411 1412 return dco_freq / (p0 * p1 * p2 * 5); 1413 } 1414 1415 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 1416 enum port port) 1417 { 1418 u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 1419 1420 switch (val) { 1421 case DDI_CLK_SEL_NONE: 1422 return 0; 1423 case DDI_CLK_SEL_TBT_162: 1424 return 162000; 1425 case DDI_CLK_SEL_TBT_270: 1426 return 270000; 1427 case DDI_CLK_SEL_TBT_540: 1428 return 540000; 1429 case DDI_CLK_SEL_TBT_810: 1430 return 810000; 1431 default: 1432 MISSING_CASE(val); 1433 return 0; 1434 } 1435 } 1436 1437 static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv, 1438 const struct intel_dpll_hw_state *pll_state) 1439 { 1440 u32 m1, m2_int, m2_frac, div1, div2, ref_clock; 1441 u64 tmp; 1442 1443 ref_clock = dev_priv->cdclk.hw.ref; 1444 1445 if (INTEL_GEN(dev_priv) >= 12) { 1446 m1 = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK; 1447 m1 = m1 >> DKL_PLL_DIV0_FBPREDIV_SHIFT; 1448 m2_int = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBDIV_INT_MASK; 1449 1450 if (pll_state->mg_pll_bias & DKL_PLL_BIAS_FRAC_EN_H) { 1451 m2_frac = pll_state->mg_pll_bias & 1452 DKL_PLL_BIAS_FBDIV_FRAC_MASK; 1453 m2_frac = m2_frac >> DKL_PLL_BIAS_FBDIV_SHIFT; 1454 } else { 1455 m2_frac = 0; 1456 } 1457 } else { 1458 m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK; 1459 m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK; 1460 1461 if (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) { 1462 m2_frac = pll_state->mg_pll_div0 & 1463 MG_PLL_DIV0_FBDIV_FRAC_MASK; 1464 m2_frac = m2_frac >> MG_PLL_DIV0_FBDIV_FRAC_SHIFT; 1465 } else { 1466 m2_frac = 0; 1467 } 1468 } 1469 1470 switch (pll_state->mg_clktop2_hsclkctl & 1471 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) { 1472 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2: 1473 div1 = 2; 1474 break; 1475 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3: 1476 div1 = 3; 1477 break; 1478 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5: 1479 div1 = 5; 1480 break; 1481 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7: 1482 div1 = 7; 1483 break; 1484 default: 1485 MISSING_CASE(pll_state->mg_clktop2_hsclkctl); 1486 return 0; 1487 } 1488 1489 div2 = (pll_state->mg_clktop2_hsclkctl & 1490 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >> 1491 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT; 1492 1493 /* div2 value of 0 is same as 1 means no div */ 1494 if (div2 == 0) 1495 div2 = 1; 1496 1497 /* 1498 * Adjust the original formula to delay the division by 2^22 in order to 1499 * minimize possible rounding errors. 1500 */ 1501 tmp = (u64)m1 * m2_int * ref_clock + 1502 (((u64)m1 * m2_frac * ref_clock) >> 22); 1503 tmp = div_u64(tmp, 5 * div1 * div2); 1504 1505 return tmp; 1506 } 1507 1508 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 1509 { 1510 int dotclock; 1511 1512 if (pipe_config->has_pch_encoder) 1513 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1514 &pipe_config->fdi_m_n); 1515 else if (intel_crtc_has_dp_encoder(pipe_config)) 1516 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1517 &pipe_config->dp_m_n); 1518 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) 1519 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp; 1520 else 1521 dotclock = pipe_config->port_clock; 1522 1523 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 1524 !intel_crtc_has_dp_encoder(pipe_config)) 1525 dotclock *= 2; 1526 1527 if (pipe_config->pixel_multiplier) 1528 dotclock /= pipe_config->pixel_multiplier; 1529 1530 pipe_config->base.adjusted_mode.crtc_clock = dotclock; 1531 } 1532 1533 static void icl_ddi_clock_get(struct intel_encoder *encoder, 1534 struct intel_crtc_state *pipe_config) 1535 { 1536 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1537 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state; 1538 enum port port = encoder->port; 1539 enum phy phy = intel_port_to_phy(dev_priv, port); 1540 int link_clock; 1541 1542 if (intel_phy_is_combo(dev_priv, phy)) { 1543 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state); 1544 } else { 1545 enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv, 1546 pipe_config->shared_dpll); 1547 1548 if (pll_id == DPLL_ID_ICL_TBTPLL) 1549 link_clock = icl_calc_tbt_pll_link(dev_priv, port); 1550 else 1551 link_clock = icl_calc_mg_pll_link(dev_priv, pll_state); 1552 } 1553 1554 pipe_config->port_clock = link_clock; 1555 1556 ddi_dotclock_get(pipe_config); 1557 } 1558 1559 static void cnl_ddi_clock_get(struct intel_encoder *encoder, 1560 struct intel_crtc_state *pipe_config) 1561 { 1562 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1563 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state; 1564 int link_clock; 1565 1566 if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) { 1567 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state); 1568 } else { 1569 link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK; 1570 1571 switch (link_clock) { 1572 case DPLL_CFGCR0_LINK_RATE_810: 1573 link_clock = 81000; 1574 break; 1575 case DPLL_CFGCR0_LINK_RATE_1080: 1576 link_clock = 108000; 1577 break; 1578 case DPLL_CFGCR0_LINK_RATE_1350: 1579 link_clock = 135000; 1580 break; 1581 case DPLL_CFGCR0_LINK_RATE_1620: 1582 link_clock = 162000; 1583 break; 1584 case DPLL_CFGCR0_LINK_RATE_2160: 1585 link_clock = 216000; 1586 break; 1587 case DPLL_CFGCR0_LINK_RATE_2700: 1588 link_clock = 270000; 1589 break; 1590 case DPLL_CFGCR0_LINK_RATE_3240: 1591 link_clock = 324000; 1592 break; 1593 case DPLL_CFGCR0_LINK_RATE_4050: 1594 link_clock = 405000; 1595 break; 1596 default: 1597 WARN(1, "Unsupported link rate\n"); 1598 break; 1599 } 1600 link_clock *= 2; 1601 } 1602 1603 pipe_config->port_clock = link_clock; 1604 1605 ddi_dotclock_get(pipe_config); 1606 } 1607 1608 static void skl_ddi_clock_get(struct intel_encoder *encoder, 1609 struct intel_crtc_state *pipe_config) 1610 { 1611 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state; 1612 int link_clock; 1613 1614 /* 1615 * ctrl1 register is already shifted for each pll, just use 0 to get 1616 * the internal shift for each field 1617 */ 1618 if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) { 1619 link_clock = skl_calc_wrpll_link(pll_state); 1620 } else { 1621 link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0); 1622 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(0); 1623 1624 switch (link_clock) { 1625 case DPLL_CTRL1_LINK_RATE_810: 1626 link_clock = 81000; 1627 break; 1628 case DPLL_CTRL1_LINK_RATE_1080: 1629 link_clock = 108000; 1630 break; 1631 case DPLL_CTRL1_LINK_RATE_1350: 1632 link_clock = 135000; 1633 break; 1634 case DPLL_CTRL1_LINK_RATE_1620: 1635 link_clock = 162000; 1636 break; 1637 case DPLL_CTRL1_LINK_RATE_2160: 1638 link_clock = 216000; 1639 break; 1640 case DPLL_CTRL1_LINK_RATE_2700: 1641 link_clock = 270000; 1642 break; 1643 default: 1644 WARN(1, "Unsupported link rate\n"); 1645 break; 1646 } 1647 link_clock *= 2; 1648 } 1649 1650 pipe_config->port_clock = link_clock; 1651 1652 ddi_dotclock_get(pipe_config); 1653 } 1654 1655 static void hsw_ddi_clock_get(struct intel_encoder *encoder, 1656 struct intel_crtc_state *pipe_config) 1657 { 1658 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1659 int link_clock = 0; 1660 u32 val, pll; 1661 1662 val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll); 1663 switch (val & PORT_CLK_SEL_MASK) { 1664 case PORT_CLK_SEL_LCPLL_810: 1665 link_clock = 81000; 1666 break; 1667 case PORT_CLK_SEL_LCPLL_1350: 1668 link_clock = 135000; 1669 break; 1670 case PORT_CLK_SEL_LCPLL_2700: 1671 link_clock = 270000; 1672 break; 1673 case PORT_CLK_SEL_WRPLL1: 1674 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0)); 1675 break; 1676 case PORT_CLK_SEL_WRPLL2: 1677 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1)); 1678 break; 1679 case PORT_CLK_SEL_SPLL: 1680 pll = I915_READ(SPLL_CTL) & SPLL_FREQ_MASK; 1681 if (pll == SPLL_FREQ_810MHz) 1682 link_clock = 81000; 1683 else if (pll == SPLL_FREQ_1350MHz) 1684 link_clock = 135000; 1685 else if (pll == SPLL_FREQ_2700MHz) 1686 link_clock = 270000; 1687 else { 1688 WARN(1, "bad spll freq\n"); 1689 return; 1690 } 1691 break; 1692 default: 1693 WARN(1, "bad port clock sel\n"); 1694 return; 1695 } 1696 1697 pipe_config->port_clock = link_clock * 2; 1698 1699 ddi_dotclock_get(pipe_config); 1700 } 1701 1702 static int bxt_calc_pll_link(const struct intel_dpll_hw_state *pll_state) 1703 { 1704 struct dpll clock; 1705 1706 clock.m1 = 2; 1707 clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22; 1708 if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE) 1709 clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK; 1710 clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT; 1711 clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT; 1712 clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT; 1713 1714 return chv_calc_dpll_params(100000, &clock); 1715 } 1716 1717 static void bxt_ddi_clock_get(struct intel_encoder *encoder, 1718 struct intel_crtc_state *pipe_config) 1719 { 1720 pipe_config->port_clock = 1721 bxt_calc_pll_link(&pipe_config->dpll_hw_state); 1722 1723 ddi_dotclock_get(pipe_config); 1724 } 1725 1726 static void intel_ddi_clock_get(struct intel_encoder *encoder, 1727 struct intel_crtc_state *pipe_config) 1728 { 1729 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1730 1731 if (INTEL_GEN(dev_priv) >= 11) 1732 icl_ddi_clock_get(encoder, pipe_config); 1733 else if (IS_CANNONLAKE(dev_priv)) 1734 cnl_ddi_clock_get(encoder, pipe_config); 1735 else if (IS_GEN9_LP(dev_priv)) 1736 bxt_ddi_clock_get(encoder, pipe_config); 1737 else if (IS_GEN9_BC(dev_priv)) 1738 skl_ddi_clock_get(encoder, pipe_config); 1739 else if (INTEL_GEN(dev_priv) <= 8) 1740 hsw_ddi_clock_get(encoder, pipe_config); 1741 } 1742 1743 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state) 1744 { 1745 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 1746 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1747 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1748 u32 temp; 1749 1750 if (!intel_crtc_has_dp_encoder(crtc_state)) 1751 return; 1752 1753 WARN_ON(transcoder_is_dsi(cpu_transcoder)); 1754 1755 temp = TRANS_MSA_SYNC_CLK; 1756 1757 switch (crtc_state->pipe_bpp) { 1758 case 18: 1759 temp |= TRANS_MSA_6_BPC; 1760 break; 1761 case 24: 1762 temp |= TRANS_MSA_8_BPC; 1763 break; 1764 case 30: 1765 temp |= TRANS_MSA_10_BPC; 1766 break; 1767 case 36: 1768 temp |= TRANS_MSA_12_BPC; 1769 break; 1770 default: 1771 MISSING_CASE(crtc_state->pipe_bpp); 1772 break; 1773 } 1774 1775 /* nonsense combination */ 1776 WARN_ON(crtc_state->limited_color_range && 1777 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 1778 1779 if (crtc_state->limited_color_range) 1780 temp |= TRANS_MSA_CEA_RANGE; 1781 1782 /* 1783 * As per DP 1.2 spec section 2.3.4.3 while sending 1784 * YCBCR 444 signals we should program MSA MISC1/0 fields with 1785 * colorspace information. 1786 */ 1787 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 1788 temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR | 1789 TRANS_MSA_YCBCR_BT709; 1790 1791 /* 1792 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 1793 * of Color Encoding Format and Content Color Gamut] while sending 1794 * YCBCR 420 signals we should program MSA MISC1 fields which 1795 * indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 1796 */ 1797 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1798 temp |= TRANS_MSA_USE_VSC_SDP; 1799 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); 1800 } 1801 1802 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state, 1803 bool state) 1804 { 1805 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 1806 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1807 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1808 u32 temp; 1809 1810 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1811 if (state == true) 1812 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; 1813 else 1814 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC; 1815 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 1816 } 1817 1818 /* 1819 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 1820 * 1821 * Only intended to be used by intel_ddi_enable_transcoder_func() and 1822 * intel_ddi_config_transcoder_func(). 1823 */ 1824 static u32 1825 intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state) 1826 { 1827 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 1828 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc); 1829 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1830 enum pipe pipe = crtc->pipe; 1831 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1832 enum port port = encoder->port; 1833 u32 temp; 1834 1835 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 1836 temp = TRANS_DDI_FUNC_ENABLE; 1837 if (INTEL_GEN(dev_priv) >= 12) 1838 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 1839 else 1840 temp |= TRANS_DDI_SELECT_PORT(port); 1841 1842 switch (crtc_state->pipe_bpp) { 1843 case 18: 1844 temp |= TRANS_DDI_BPC_6; 1845 break; 1846 case 24: 1847 temp |= TRANS_DDI_BPC_8; 1848 break; 1849 case 30: 1850 temp |= TRANS_DDI_BPC_10; 1851 break; 1852 case 36: 1853 temp |= TRANS_DDI_BPC_12; 1854 break; 1855 default: 1856 BUG(); 1857 } 1858 1859 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 1860 temp |= TRANS_DDI_PVSYNC; 1861 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 1862 temp |= TRANS_DDI_PHSYNC; 1863 1864 if (cpu_transcoder == TRANSCODER_EDP) { 1865 switch (pipe) { 1866 case PIPE_A: 1867 /* On Haswell, can only use the always-on power well for 1868 * eDP when not using the panel fitter, and when not 1869 * using motion blur mitigation (which we don't 1870 * support). */ 1871 if (crtc_state->pch_pfit.force_thru) 1872 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 1873 else 1874 temp |= TRANS_DDI_EDP_INPUT_A_ON; 1875 break; 1876 case PIPE_B: 1877 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 1878 break; 1879 case PIPE_C: 1880 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 1881 break; 1882 default: 1883 BUG(); 1884 break; 1885 } 1886 } 1887 1888 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1889 if (crtc_state->has_hdmi_sink) 1890 temp |= TRANS_DDI_MODE_SELECT_HDMI; 1891 else 1892 temp |= TRANS_DDI_MODE_SELECT_DVI; 1893 1894 if (crtc_state->hdmi_scrambling) 1895 temp |= TRANS_DDI_HDMI_SCRAMBLING; 1896 if (crtc_state->hdmi_high_tmds_clock_ratio) 1897 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 1898 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 1899 temp |= TRANS_DDI_MODE_SELECT_FDI; 1900 temp |= (crtc_state->fdi_lanes - 1) << 1; 1901 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 1902 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 1903 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 1904 } else { 1905 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 1906 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 1907 } 1908 1909 return temp; 1910 } 1911 1912 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state) 1913 { 1914 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 1915 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1916 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1917 u32 temp; 1918 1919 temp = intel_ddi_transcoder_func_reg_val_get(crtc_state); 1920 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 1921 } 1922 1923 /* 1924 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 1925 * bit. 1926 */ 1927 static void 1928 intel_ddi_config_transcoder_func(const struct intel_crtc_state *crtc_state) 1929 { 1930 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 1931 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1932 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1933 u32 temp; 1934 1935 temp = intel_ddi_transcoder_func_reg_val_get(crtc_state); 1936 temp &= ~TRANS_DDI_FUNC_ENABLE; 1937 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 1938 } 1939 1940 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 1941 { 1942 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 1943 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1944 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1945 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); 1946 u32 val = I915_READ(reg); 1947 1948 if (INTEL_GEN(dev_priv) >= 12) { 1949 val &= ~(TRANS_DDI_FUNC_ENABLE | TGL_TRANS_DDI_PORT_MASK | 1950 TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 1951 } else { 1952 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | 1953 TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 1954 } 1955 I915_WRITE(reg, val); 1956 1957 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME && 1958 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1959 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n"); 1960 /* Quirk time at 100ms for reliable operation */ 1961 msleep(100); 1962 } 1963 } 1964 1965 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder, 1966 bool enable) 1967 { 1968 struct drm_device *dev = intel_encoder->base.dev; 1969 struct drm_i915_private *dev_priv = to_i915(dev); 1970 intel_wakeref_t wakeref; 1971 enum pipe pipe = 0; 1972 int ret = 0; 1973 u32 tmp; 1974 1975 wakeref = intel_display_power_get_if_enabled(dev_priv, 1976 intel_encoder->power_domain); 1977 if (WARN_ON(!wakeref)) 1978 return -ENXIO; 1979 1980 if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) { 1981 ret = -EIO; 1982 goto out; 1983 } 1984 1985 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe)); 1986 if (enable) 1987 tmp |= TRANS_DDI_HDCP_SIGNALLING; 1988 else 1989 tmp &= ~TRANS_DDI_HDCP_SIGNALLING; 1990 I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp); 1991 out: 1992 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 1993 return ret; 1994 } 1995 1996 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 1997 { 1998 struct drm_device *dev = intel_connector->base.dev; 1999 struct drm_i915_private *dev_priv = to_i915(dev); 2000 struct intel_encoder *encoder = intel_connector->encoder; 2001 int type = intel_connector->base.connector_type; 2002 enum port port = encoder->port; 2003 enum transcoder cpu_transcoder; 2004 intel_wakeref_t wakeref; 2005 enum pipe pipe = 0; 2006 u32 tmp; 2007 bool ret; 2008 2009 wakeref = intel_display_power_get_if_enabled(dev_priv, 2010 encoder->power_domain); 2011 if (!wakeref) 2012 return false; 2013 2014 if (!encoder->get_hw_state(encoder, &pipe)) { 2015 ret = false; 2016 goto out; 2017 } 2018 2019 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) 2020 cpu_transcoder = TRANSCODER_EDP; 2021 else 2022 cpu_transcoder = (enum transcoder) pipe; 2023 2024 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 2025 2026 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 2027 case TRANS_DDI_MODE_SELECT_HDMI: 2028 case TRANS_DDI_MODE_SELECT_DVI: 2029 ret = type == DRM_MODE_CONNECTOR_HDMIA; 2030 break; 2031 2032 case TRANS_DDI_MODE_SELECT_DP_SST: 2033 ret = type == DRM_MODE_CONNECTOR_eDP || 2034 type == DRM_MODE_CONNECTOR_DisplayPort; 2035 break; 2036 2037 case TRANS_DDI_MODE_SELECT_DP_MST: 2038 /* if the transcoder is in MST state then 2039 * connector isn't connected */ 2040 ret = false; 2041 break; 2042 2043 case TRANS_DDI_MODE_SELECT_FDI: 2044 ret = type == DRM_MODE_CONNECTOR_VGA; 2045 break; 2046 2047 default: 2048 ret = false; 2049 break; 2050 } 2051 2052 out: 2053 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 2054 2055 return ret; 2056 } 2057 2058 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 2059 u8 *pipe_mask, bool *is_dp_mst) 2060 { 2061 struct drm_device *dev = encoder->base.dev; 2062 struct drm_i915_private *dev_priv = to_i915(dev); 2063 enum port port = encoder->port; 2064 intel_wakeref_t wakeref; 2065 enum pipe p; 2066 u32 tmp; 2067 u8 mst_pipe_mask; 2068 2069 *pipe_mask = 0; 2070 *is_dp_mst = false; 2071 2072 wakeref = intel_display_power_get_if_enabled(dev_priv, 2073 encoder->power_domain); 2074 if (!wakeref) 2075 return; 2076 2077 tmp = I915_READ(DDI_BUF_CTL(port)); 2078 if (!(tmp & DDI_BUF_CTL_ENABLE)) 2079 goto out; 2080 2081 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) { 2082 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 2083 2084 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 2085 default: 2086 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 2087 /* fallthrough */ 2088 case TRANS_DDI_EDP_INPUT_A_ON: 2089 case TRANS_DDI_EDP_INPUT_A_ONOFF: 2090 *pipe_mask = BIT(PIPE_A); 2091 break; 2092 case TRANS_DDI_EDP_INPUT_B_ONOFF: 2093 *pipe_mask = BIT(PIPE_B); 2094 break; 2095 case TRANS_DDI_EDP_INPUT_C_ONOFF: 2096 *pipe_mask = BIT(PIPE_C); 2097 break; 2098 } 2099 2100 goto out; 2101 } 2102 2103 mst_pipe_mask = 0; 2104 for_each_pipe(dev_priv, p) { 2105 enum transcoder cpu_transcoder = (enum transcoder)p; 2106 unsigned int port_mask, ddi_select; 2107 intel_wakeref_t trans_wakeref; 2108 2109 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 2110 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 2111 if (!trans_wakeref) 2112 continue; 2113 2114 if (INTEL_GEN(dev_priv) >= 12) { 2115 port_mask = TGL_TRANS_DDI_PORT_MASK; 2116 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 2117 } else { 2118 port_mask = TRANS_DDI_PORT_MASK; 2119 ddi_select = TRANS_DDI_SELECT_PORT(port); 2120 } 2121 2122 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 2123 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 2124 trans_wakeref); 2125 2126 if ((tmp & port_mask) != ddi_select) 2127 continue; 2128 2129 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == 2130 TRANS_DDI_MODE_SELECT_DP_MST) 2131 mst_pipe_mask |= BIT(p); 2132 2133 *pipe_mask |= BIT(p); 2134 } 2135 2136 if (!*pipe_mask) 2137 DRM_DEBUG_KMS("No pipe for [ENCODER:%d:%s] found\n", 2138 encoder->base.base.id, encoder->base.name); 2139 2140 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 2141 DRM_DEBUG_KMS("Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 2142 encoder->base.base.id, encoder->base.name, 2143 *pipe_mask); 2144 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 2145 } 2146 2147 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 2148 DRM_DEBUG_KMS("Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", 2149 encoder->base.base.id, encoder->base.name, 2150 *pipe_mask, mst_pipe_mask); 2151 else 2152 *is_dp_mst = mst_pipe_mask; 2153 2154 out: 2155 if (*pipe_mask && IS_GEN9_LP(dev_priv)) { 2156 tmp = I915_READ(BXT_PHY_CTL(port)); 2157 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 2158 BXT_PHY_LANE_POWERDOWN_ACK | 2159 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 2160 DRM_ERROR("[ENCODER:%d:%s] enabled but PHY powered down? " 2161 "(PHY_CTL %08x)\n", encoder->base.base.id, 2162 encoder->base.name, tmp); 2163 } 2164 2165 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 2166 } 2167 2168 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 2169 enum pipe *pipe) 2170 { 2171 u8 pipe_mask; 2172 bool is_mst; 2173 2174 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2175 2176 if (is_mst || !pipe_mask) 2177 return false; 2178 2179 *pipe = ffs(pipe_mask) - 1; 2180 2181 return true; 2182 } 2183 2184 static inline enum intel_display_power_domain 2185 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port) 2186 { 2187 /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with 2188 * DC states enabled at the same time, while for driver initiated AUX 2189 * transfers we need the same AUX IOs to be powered but with DC states 2190 * disabled. Accordingly use the AUX power domain here which leaves DC 2191 * states enabled. 2192 * However, for non-A AUX ports the corresponding non-EDP transcoders 2193 * would have already enabled power well 2 and DC_OFF. This means we can 2194 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a 2195 * specific AUX_IO reference without powering up any extra wells. 2196 * Note that PSR is enabled only on Port A even though this function 2197 * returns the correct domain for other ports too. 2198 */ 2199 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A : 2200 intel_aux_power_domain(dig_port); 2201 } 2202 2203 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 2204 struct intel_crtc_state *crtc_state) 2205 { 2206 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2207 struct intel_digital_port *dig_port; 2208 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2209 2210 /* 2211 * TODO: Add support for MST encoders. Atm, the following should never 2212 * happen since fake-MST encoders don't set their get_power_domains() 2213 * hook. 2214 */ 2215 if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 2216 return; 2217 2218 dig_port = enc_to_dig_port(&encoder->base); 2219 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); 2220 2221 /* 2222 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC 2223 * ports. 2224 */ 2225 if (intel_crtc_has_dp_encoder(crtc_state) || 2226 intel_phy_is_tc(dev_priv, phy)) 2227 intel_display_power_get(dev_priv, 2228 intel_ddi_main_link_aux_domain(dig_port)); 2229 2230 /* 2231 * VDSC power is needed when DSC is enabled 2232 */ 2233 if (crtc_state->dsc_params.compression_enable) 2234 intel_display_power_get(dev_priv, 2235 intel_dsc_power_domain(crtc_state)); 2236 } 2237 2238 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state) 2239 { 2240 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 2241 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2242 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc); 2243 enum port port = encoder->port; 2244 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2245 2246 if (cpu_transcoder != TRANSCODER_EDP) { 2247 if (INTEL_GEN(dev_priv) >= 12) 2248 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 2249 TGL_TRANS_CLK_SEL_PORT(port)); 2250 else 2251 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 2252 TRANS_CLK_SEL_PORT(port)); 2253 } 2254 } 2255 2256 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state) 2257 { 2258 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); 2259 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2260 2261 if (cpu_transcoder != TRANSCODER_EDP) { 2262 if (INTEL_GEN(dev_priv) >= 12) 2263 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 2264 TGL_TRANS_CLK_SEL_DISABLED); 2265 else 2266 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 2267 TRANS_CLK_SEL_DISABLED); 2268 } 2269 } 2270 2271 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 2272 enum port port, u8 iboost) 2273 { 2274 u32 tmp; 2275 2276 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0); 2277 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 2278 if (iboost) 2279 tmp |= iboost << BALANCE_LEG_SHIFT(port); 2280 else 2281 tmp |= BALANCE_LEG_DISABLE(port); 2282 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp); 2283 } 2284 2285 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 2286 int level, enum intel_output_type type) 2287 { 2288 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); 2289 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2290 enum port port = encoder->port; 2291 u8 iboost; 2292 2293 if (type == INTEL_OUTPUT_HDMI) 2294 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level; 2295 else 2296 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level; 2297 2298 if (iboost == 0) { 2299 const struct ddi_buf_trans *ddi_translations; 2300 int n_entries; 2301 2302 if (type == INTEL_OUTPUT_HDMI) 2303 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 2304 else if (type == INTEL_OUTPUT_EDP) 2305 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries); 2306 else 2307 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries); 2308 2309 if (WARN_ON_ONCE(!ddi_translations)) 2310 return; 2311 if (WARN_ON_ONCE(level >= n_entries)) 2312 level = n_entries - 1; 2313 2314 iboost = ddi_translations[level].i_boost; 2315 } 2316 2317 /* Make sure that the requested I_boost is valid */ 2318 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 2319 DRM_ERROR("Invalid I_boost value %u\n", iboost); 2320 return; 2321 } 2322 2323 _skl_ddi_set_iboost(dev_priv, port, iboost); 2324 2325 if (port == PORT_A && intel_dig_port->max_lanes == 4) 2326 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 2327 } 2328 2329 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, 2330 int level, enum intel_output_type type) 2331 { 2332 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2333 const struct bxt_ddi_buf_trans *ddi_translations; 2334 enum port port = encoder->port; 2335 int n_entries; 2336 2337 if (type == INTEL_OUTPUT_HDMI) 2338 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries); 2339 else if (type == INTEL_OUTPUT_EDP) 2340 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries); 2341 else 2342 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries); 2343 2344 if (WARN_ON_ONCE(!ddi_translations)) 2345 return; 2346 if (WARN_ON_ONCE(level >= n_entries)) 2347 level = n_entries - 1; 2348 2349 bxt_ddi_phy_set_signal_level(dev_priv, port, 2350 ddi_translations[level].margin, 2351 ddi_translations[level].scale, 2352 ddi_translations[level].enable, 2353 ddi_translations[level].deemphasis); 2354 } 2355 2356 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder) 2357 { 2358 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2359 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2360 enum port port = encoder->port; 2361 enum phy phy = intel_port_to_phy(dev_priv, port); 2362 int n_entries; 2363 2364 if (INTEL_GEN(dev_priv) >= 12) { 2365 if (intel_phy_is_combo(dev_priv, phy)) 2366 icl_get_combo_buf_trans(dev_priv, encoder->type, 2367 intel_dp->link_rate, &n_entries); 2368 else 2369 n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations); 2370 } else if (INTEL_GEN(dev_priv) == 11) { 2371 if (intel_phy_is_combo(dev_priv, phy)) 2372 icl_get_combo_buf_trans(dev_priv, encoder->type, 2373 intel_dp->link_rate, &n_entries); 2374 else 2375 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations); 2376 } else if (IS_CANNONLAKE(dev_priv)) { 2377 if (encoder->type == INTEL_OUTPUT_EDP) 2378 cnl_get_buf_trans_edp(dev_priv, &n_entries); 2379 else 2380 cnl_get_buf_trans_dp(dev_priv, &n_entries); 2381 } else if (IS_GEN9_LP(dev_priv)) { 2382 if (encoder->type == INTEL_OUTPUT_EDP) 2383 bxt_get_buf_trans_edp(dev_priv, &n_entries); 2384 else 2385 bxt_get_buf_trans_dp(dev_priv, &n_entries); 2386 } else { 2387 if (encoder->type == INTEL_OUTPUT_EDP) 2388 intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries); 2389 else 2390 intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries); 2391 } 2392 2393 if (WARN_ON(n_entries < 1)) 2394 n_entries = 1; 2395 if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 2396 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 2397 2398 return index_to_dp_signal_levels[n_entries - 1] & 2399 DP_TRAIN_VOLTAGE_SWING_MASK; 2400 } 2401 2402 /* 2403 * We assume that the full set of pre-emphasis values can be 2404 * used on all DDI platforms. Should that change we need to 2405 * rethink this code. 2406 */ 2407 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing) 2408 { 2409 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2410 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2411 return DP_TRAIN_PRE_EMPH_LEVEL_3; 2412 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 2413 return DP_TRAIN_PRE_EMPH_LEVEL_2; 2414 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 2415 return DP_TRAIN_PRE_EMPH_LEVEL_1; 2416 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 2417 default: 2418 return DP_TRAIN_PRE_EMPH_LEVEL_0; 2419 } 2420 } 2421 2422 static void cnl_ddi_vswing_program(struct intel_encoder *encoder, 2423 int level, enum intel_output_type type) 2424 { 2425 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2426 const struct cnl_ddi_buf_trans *ddi_translations; 2427 enum port port = encoder->port; 2428 int n_entries, ln; 2429 u32 val; 2430 2431 if (type == INTEL_OUTPUT_HDMI) 2432 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries); 2433 else if (type == INTEL_OUTPUT_EDP) 2434 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries); 2435 else 2436 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries); 2437 2438 if (WARN_ON_ONCE(!ddi_translations)) 2439 return; 2440 if (WARN_ON_ONCE(level >= n_entries)) 2441 level = n_entries - 1; 2442 2443 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */ 2444 val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); 2445 val &= ~SCALING_MODE_SEL_MASK; 2446 val |= SCALING_MODE_SEL(2); 2447 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); 2448 2449 /* Program PORT_TX_DW2 */ 2450 val = I915_READ(CNL_PORT_TX_DW2_LN0(port)); 2451 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 2452 RCOMP_SCALAR_MASK); 2453 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); 2454 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); 2455 /* Rcomp scalar is fixed as 0x98 for every table entry */ 2456 val |= RCOMP_SCALAR(0x98); 2457 I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val); 2458 2459 /* Program PORT_TX_DW4 */ 2460 /* We cannot write to GRP. It would overrite individual loadgen */ 2461 for (ln = 0; ln < 4; ln++) { 2462 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port)); 2463 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 2464 CURSOR_COEFF_MASK); 2465 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); 2466 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); 2467 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); 2468 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val); 2469 } 2470 2471 /* Program PORT_TX_DW5 */ 2472 /* All DW5 values are fixed for every table entry */ 2473 val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); 2474 val &= ~RTERM_SELECT_MASK; 2475 val |= RTERM_SELECT(6); 2476 val |= TAP3_DISABLE; 2477 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); 2478 2479 /* Program PORT_TX_DW7 */ 2480 val = I915_READ(CNL_PORT_TX_DW7_LN0(port)); 2481 val &= ~N_SCALAR_MASK; 2482 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); 2483 I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val); 2484 } 2485 2486 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, 2487 int level, enum intel_output_type type) 2488 { 2489 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2490 enum port port = encoder->port; 2491 int width, rate, ln; 2492 u32 val; 2493 2494 if (type == INTEL_OUTPUT_HDMI) { 2495 width = 4; 2496 rate = 0; /* Rate is always < than 6GHz for HDMI */ 2497 } else { 2498 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2499 2500 width = intel_dp->lane_count; 2501 rate = intel_dp->link_rate; 2502 } 2503 2504 /* 2505 * 1. If port type is eDP or DP, 2506 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 2507 * else clear to 0b. 2508 */ 2509 val = I915_READ(CNL_PORT_PCS_DW1_LN0(port)); 2510 if (type != INTEL_OUTPUT_HDMI) 2511 val |= COMMON_KEEPER_EN; 2512 else 2513 val &= ~COMMON_KEEPER_EN; 2514 I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val); 2515 2516 /* 2. Program loadgen select */ 2517 /* 2518 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes 2519 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2520 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2521 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 2522 */ 2523 for (ln = 0; ln <= 3; ln++) { 2524 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port)); 2525 val &= ~LOADGEN_SELECT; 2526 2527 if ((rate <= 600000 && width == 4 && ln >= 1) || 2528 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { 2529 val |= LOADGEN_SELECT; 2530 } 2531 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val); 2532 } 2533 2534 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 2535 val = I915_READ(CNL_PORT_CL1CM_DW5); 2536 val |= SUS_CLOCK_CONFIG; 2537 I915_WRITE(CNL_PORT_CL1CM_DW5, val); 2538 2539 /* 4. Clear training enable to change swing values */ 2540 val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); 2541 val &= ~TX_TRAINING_EN; 2542 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); 2543 2544 /* 5. Program swing and de-emphasis */ 2545 cnl_ddi_vswing_program(encoder, level, type); 2546 2547 /* 6. Set training enable to trigger update */ 2548 val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); 2549 val |= TX_TRAINING_EN; 2550 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); 2551 } 2552 2553 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, 2554 u32 level, enum phy phy, int type, 2555 int rate) 2556 { 2557 const struct cnl_ddi_buf_trans *ddi_translations = NULL; 2558 u32 n_entries, val; 2559 int ln; 2560 2561 ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate, 2562 &n_entries); 2563 if (!ddi_translations) 2564 return; 2565 2566 if (level >= n_entries) { 2567 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1); 2568 level = n_entries - 1; 2569 } 2570 2571 /* Set PORT_TX_DW5 */ 2572 val = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); 2573 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 2574 TAP2_DISABLE | TAP3_DISABLE); 2575 val |= SCALING_MODE_SEL(0x2); 2576 val |= RTERM_SELECT(0x6); 2577 val |= TAP3_DISABLE; 2578 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val); 2579 2580 /* Program PORT_TX_DW2 */ 2581 val = I915_READ(ICL_PORT_TX_DW2_LN0(phy)); 2582 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 2583 RCOMP_SCALAR_MASK); 2584 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); 2585 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); 2586 /* Program Rcomp scalar for every table entry */ 2587 val |= RCOMP_SCALAR(0x98); 2588 I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), val); 2589 2590 /* Program PORT_TX_DW4 */ 2591 /* We cannot write to GRP. It would overwrite individual loadgen. */ 2592 for (ln = 0; ln <= 3; ln++) { 2593 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy)); 2594 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 2595 CURSOR_COEFF_MASK); 2596 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); 2597 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); 2598 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); 2599 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val); 2600 } 2601 2602 /* Program PORT_TX_DW7 */ 2603 val = I915_READ(ICL_PORT_TX_DW7_LN0(phy)); 2604 val &= ~N_SCALAR_MASK; 2605 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); 2606 I915_WRITE(ICL_PORT_TX_DW7_GRP(phy), val); 2607 } 2608 2609 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 2610 u32 level, 2611 enum intel_output_type type) 2612 { 2613 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2614 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2615 int width = 0; 2616 int rate = 0; 2617 u32 val; 2618 int ln = 0; 2619 2620 if (type == INTEL_OUTPUT_HDMI) { 2621 width = 4; 2622 /* Rate is always < than 6GHz for HDMI */ 2623 } else { 2624 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2625 2626 width = intel_dp->lane_count; 2627 rate = intel_dp->link_rate; 2628 } 2629 2630 /* 2631 * 1. If port type is eDP or DP, 2632 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 2633 * else clear to 0b. 2634 */ 2635 val = I915_READ(ICL_PORT_PCS_DW1_LN0(phy)); 2636 if (type == INTEL_OUTPUT_HDMI) 2637 val &= ~COMMON_KEEPER_EN; 2638 else 2639 val |= COMMON_KEEPER_EN; 2640 I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), val); 2641 2642 /* 2. Program loadgen select */ 2643 /* 2644 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes 2645 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2646 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2647 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 2648 */ 2649 for (ln = 0; ln <= 3; ln++) { 2650 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy)); 2651 val &= ~LOADGEN_SELECT; 2652 2653 if ((rate <= 600000 && width == 4 && ln >= 1) || 2654 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { 2655 val |= LOADGEN_SELECT; 2656 } 2657 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val); 2658 } 2659 2660 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 2661 val = I915_READ(ICL_PORT_CL_DW5(phy)); 2662 val |= SUS_CLOCK_CONFIG; 2663 I915_WRITE(ICL_PORT_CL_DW5(phy), val); 2664 2665 /* 4. Clear training enable to change swing values */ 2666 val = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); 2667 val &= ~TX_TRAINING_EN; 2668 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val); 2669 2670 /* 5. Program swing and de-emphasis */ 2671 icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate); 2672 2673 /* 6. Set training enable to trigger update */ 2674 val = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); 2675 val |= TX_TRAINING_EN; 2676 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val); 2677 } 2678 2679 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 2680 int link_clock, 2681 u32 level) 2682 { 2683 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2684 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 2685 const struct icl_mg_phy_ddi_buf_trans *ddi_translations; 2686 u32 n_entries, val; 2687 int ln; 2688 2689 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations); 2690 ddi_translations = icl_mg_phy_ddi_translations; 2691 /* The table does not have values for level 3 and level 9. */ 2692 if (level >= n_entries || level == 3 || level == 9) { 2693 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", 2694 level, n_entries - 2); 2695 level = n_entries - 2; 2696 } 2697 2698 /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */ 2699 for (ln = 0; ln < 2; ln++) { 2700 val = I915_READ(MG_TX1_LINK_PARAMS(ln, tc_port)); 2701 val &= ~CRI_USE_FS32; 2702 I915_WRITE(MG_TX1_LINK_PARAMS(ln, tc_port), val); 2703 2704 val = I915_READ(MG_TX2_LINK_PARAMS(ln, tc_port)); 2705 val &= ~CRI_USE_FS32; 2706 I915_WRITE(MG_TX2_LINK_PARAMS(ln, tc_port), val); 2707 } 2708 2709 /* Program MG_TX_SWINGCTRL with values from vswing table */ 2710 for (ln = 0; ln < 2; ln++) { 2711 val = I915_READ(MG_TX1_SWINGCTRL(ln, tc_port)); 2712 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; 2713 val |= CRI_TXDEEMPH_OVERRIDE_17_12( 2714 ddi_translations[level].cri_txdeemph_override_17_12); 2715 I915_WRITE(MG_TX1_SWINGCTRL(ln, tc_port), val); 2716 2717 val = I915_READ(MG_TX2_SWINGCTRL(ln, tc_port)); 2718 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; 2719 val |= CRI_TXDEEMPH_OVERRIDE_17_12( 2720 ddi_translations[level].cri_txdeemph_override_17_12); 2721 I915_WRITE(MG_TX2_SWINGCTRL(ln, tc_port), val); 2722 } 2723 2724 /* Program MG_TX_DRVCTRL with values from vswing table */ 2725 for (ln = 0; ln < 2; ln++) { 2726 val = I915_READ(MG_TX1_DRVCTRL(ln, tc_port)); 2727 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 2728 CRI_TXDEEMPH_OVERRIDE_5_0_MASK); 2729 val |= CRI_TXDEEMPH_OVERRIDE_5_0( 2730 ddi_translations[level].cri_txdeemph_override_5_0) | 2731 CRI_TXDEEMPH_OVERRIDE_11_6( 2732 ddi_translations[level].cri_txdeemph_override_11_6) | 2733 CRI_TXDEEMPH_OVERRIDE_EN; 2734 I915_WRITE(MG_TX1_DRVCTRL(ln, tc_port), val); 2735 2736 val = I915_READ(MG_TX2_DRVCTRL(ln, tc_port)); 2737 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 2738 CRI_TXDEEMPH_OVERRIDE_5_0_MASK); 2739 val |= CRI_TXDEEMPH_OVERRIDE_5_0( 2740 ddi_translations[level].cri_txdeemph_override_5_0) | 2741 CRI_TXDEEMPH_OVERRIDE_11_6( 2742 ddi_translations[level].cri_txdeemph_override_11_6) | 2743 CRI_TXDEEMPH_OVERRIDE_EN; 2744 I915_WRITE(MG_TX2_DRVCTRL(ln, tc_port), val); 2745 2746 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 2747 } 2748 2749 /* 2750 * Program MG_CLKHUB<LN, port being used> with value from frequency table 2751 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 2752 * values from table for which TX1 and TX2 enabled. 2753 */ 2754 for (ln = 0; ln < 2; ln++) { 2755 val = I915_READ(MG_CLKHUB(ln, tc_port)); 2756 if (link_clock < 300000) 2757 val |= CFG_LOW_RATE_LKREN_EN; 2758 else 2759 val &= ~CFG_LOW_RATE_LKREN_EN; 2760 I915_WRITE(MG_CLKHUB(ln, tc_port), val); 2761 } 2762 2763 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 2764 for (ln = 0; ln < 2; ln++) { 2765 val = I915_READ(MG_TX1_DCC(ln, tc_port)); 2766 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; 2767 if (link_clock <= 500000) { 2768 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; 2769 } else { 2770 val |= CFG_AMI_CK_DIV_OVERRIDE_EN | 2771 CFG_AMI_CK_DIV_OVERRIDE_VAL(1); 2772 } 2773 I915_WRITE(MG_TX1_DCC(ln, tc_port), val); 2774 2775 val = I915_READ(MG_TX2_DCC(ln, tc_port)); 2776 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; 2777 if (link_clock <= 500000) { 2778 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; 2779 } else { 2780 val |= CFG_AMI_CK_DIV_OVERRIDE_EN | 2781 CFG_AMI_CK_DIV_OVERRIDE_VAL(1); 2782 } 2783 I915_WRITE(MG_TX2_DCC(ln, tc_port), val); 2784 } 2785 2786 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 2787 for (ln = 0; ln < 2; ln++) { 2788 val = I915_READ(MG_TX1_PISO_READLOAD(ln, tc_port)); 2789 val |= CRI_CALCINIT; 2790 I915_WRITE(MG_TX1_PISO_READLOAD(ln, tc_port), val); 2791 2792 val = I915_READ(MG_TX2_PISO_READLOAD(ln, tc_port)); 2793 val |= CRI_CALCINIT; 2794 I915_WRITE(MG_TX2_PISO_READLOAD(ln, tc_port), val); 2795 } 2796 } 2797 2798 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder, 2799 int link_clock, 2800 u32 level, 2801 enum intel_output_type type) 2802 { 2803 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2804 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2805 2806 if (intel_phy_is_combo(dev_priv, phy)) 2807 icl_combo_phy_ddi_vswing_sequence(encoder, level, type); 2808 else 2809 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level); 2810 } 2811 2812 static void 2813 tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock, 2814 u32 level) 2815 { 2816 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2817 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 2818 const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations; 2819 u32 n_entries, val, ln, dpcnt_mask, dpcnt_val; 2820 2821 n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations); 2822 ddi_translations = tgl_dkl_phy_ddi_translations; 2823 2824 if (level >= n_entries) 2825 level = n_entries - 1; 2826 2827 dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK | 2828 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 2829 DKL_TX_VSWING_CONTROL_MASK); 2830 dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control); 2831 dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control); 2832 dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control); 2833 2834 for (ln = 0; ln < 2; ln++) { 2835 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln)); 2836 2837 /* All the registers are RMW */ 2838 val = I915_READ(DKL_TX_DPCNTL0(tc_port)); 2839 val &= ~dpcnt_mask; 2840 val |= dpcnt_val; 2841 I915_WRITE(DKL_TX_DPCNTL0(tc_port), val); 2842 2843 val = I915_READ(DKL_TX_DPCNTL1(tc_port)); 2844 val &= ~dpcnt_mask; 2845 val |= dpcnt_val; 2846 I915_WRITE(DKL_TX_DPCNTL1(tc_port), val); 2847 2848 val = I915_READ(DKL_TX_DPCNTL2(tc_port)); 2849 val &= ~DKL_TX_DP20BITMODE; 2850 I915_WRITE(DKL_TX_DPCNTL2(tc_port), val); 2851 } 2852 } 2853 2854 static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder, 2855 int link_clock, 2856 u32 level, 2857 enum intel_output_type type) 2858 { 2859 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2860 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2861 2862 if (intel_phy_is_combo(dev_priv, phy)) 2863 icl_combo_phy_ddi_vswing_sequence(encoder, level, type); 2864 else 2865 tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level); 2866 } 2867 2868 static u32 translate_signal_level(int signal_levels) 2869 { 2870 int i; 2871 2872 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 2873 if (index_to_dp_signal_levels[i] == signal_levels) 2874 return i; 2875 } 2876 2877 WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 2878 signal_levels); 2879 2880 return 0; 2881 } 2882 2883 static u32 intel_ddi_dp_level(struct intel_dp *intel_dp) 2884 { 2885 u8 train_set = intel_dp->train_set[0]; 2886 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2887 DP_TRAIN_PRE_EMPHASIS_MASK); 2888 2889 return translate_signal_level(signal_levels); 2890 } 2891 2892 u32 bxt_signal_levels(struct intel_dp *intel_dp) 2893 { 2894 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2895 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); 2896 struct intel_encoder *encoder = &dport->base; 2897 int level = intel_ddi_dp_level(intel_dp); 2898 2899 if (INTEL_GEN(dev_priv) >= 12) 2900 tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate, 2901 level, encoder->type); 2902 else if (INTEL_GEN(dev_priv) >= 11) 2903 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate, 2904 level, encoder->type); 2905 else if (IS_CANNONLAKE(dev_priv)) 2906 cnl_ddi_vswing_sequence(encoder, level, encoder->type); 2907 else 2908 bxt_ddi_vswing_sequence(encoder, level, encoder->type); 2909 2910 return 0; 2911 } 2912 2913 u32 ddi_signal_levels(struct intel_dp *intel_dp) 2914 { 2915 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2916 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); 2917 struct intel_encoder *encoder = &dport->base; 2918 int level = intel_ddi_dp_level(intel_dp); 2919 2920 if (IS_GEN9_BC(dev_priv)) 2921 skl_ddi_set_iboost(encoder, level, encoder->type); 2922 2923 return DDI_BUF_TRANS_SELECT(level); 2924 } 2925 2926 static inline 2927 u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv, 2928 enum phy phy) 2929 { 2930 if (intel_phy_is_combo(dev_priv, phy)) { 2931 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 2932 } else if (intel_phy_is_tc(dev_priv, phy)) { 2933 enum tc_port tc_port = intel_port_to_tc(dev_priv, 2934 (enum port)phy); 2935 2936 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port); 2937 } 2938 2939 return 0; 2940 } 2941 2942 static void icl_map_plls_to_ports(struct intel_encoder *encoder, 2943 const struct intel_crtc_state *crtc_state) 2944 { 2945 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2946 struct intel_shared_dpll *pll = crtc_state->shared_dpll; 2947 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2948 u32 val; 2949 2950 mutex_lock(&dev_priv->dpll_lock); 2951 2952 val = I915_READ(ICL_DPCLKA_CFGCR0); 2953 WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0); 2954 2955 if (intel_phy_is_combo(dev_priv, phy)) { 2956 /* 2957 * Even though this register references DDIs, note that we 2958 * want to pass the PHY rather than the port (DDI). For 2959 * ICL, port=phy in all cases so it doesn't matter, but for 2960 * EHL the bspec notes the following: 2961 * 2962 * "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA 2963 * Clock Select chooses the PLL for both DDIA and DDID and 2964 * drives port A in all cases." 2965 */ 2966 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 2967 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 2968 I915_WRITE(ICL_DPCLKA_CFGCR0, val); 2969 POSTING_READ(ICL_DPCLKA_CFGCR0); 2970 } 2971 2972 val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 2973 I915_WRITE(ICL_DPCLKA_CFGCR0, val); 2974 2975 mutex_unlock(&dev_priv->dpll_lock); 2976 } 2977 2978 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder) 2979 { 2980 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2981 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2982 u32 val; 2983 2984 mutex_lock(&dev_priv->dpll_lock); 2985 2986 val = I915_READ(ICL_DPCLKA_CFGCR0); 2987 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 2988 I915_WRITE(ICL_DPCLKA_CFGCR0, val); 2989 2990 mutex_unlock(&dev_priv->dpll_lock); 2991 } 2992 2993 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2994 { 2995 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2996 u32 val; 2997 enum port port; 2998 u32 port_mask; 2999 bool ddi_clk_needed; 3000 3001 /* 3002 * In case of DP MST, we sanitize the primary encoder only, not the 3003 * virtual ones. 3004 */ 3005 if (encoder->type == INTEL_OUTPUT_DP_MST) 3006 return; 3007 3008 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 3009 u8 pipe_mask; 3010 bool is_mst; 3011 3012 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 3013 /* 3014 * In the unlikely case that BIOS enables DP in MST mode, just 3015 * warn since our MST HW readout is incomplete. 3016 */ 3017 if (WARN_ON(is_mst)) 3018 return; 3019 } 3020 3021 port_mask = BIT(encoder->port); 3022 ddi_clk_needed = encoder->base.crtc; 3023 3024 if (encoder->type == INTEL_OUTPUT_DSI) { 3025 struct intel_encoder *other_encoder; 3026 3027 port_mask = intel_dsi_encoder_ports(encoder); 3028 /* 3029 * Sanity check that we haven't incorrectly registered another 3030 * encoder using any of the ports of this DSI encoder. 3031 */ 3032 for_each_intel_encoder(&dev_priv->drm, other_encoder) { 3033 if (other_encoder == encoder) 3034 continue; 3035 3036 if (WARN_ON(port_mask & BIT(other_encoder->port))) 3037 return; 3038 } 3039 /* 3040 * For DSI we keep the ddi clocks gated 3041 * except during enable/disable sequence. 3042 */ 3043 ddi_clk_needed = false; 3044 } 3045 3046 val = I915_READ(ICL_DPCLKA_CFGCR0); 3047 for_each_port_masked(port, port_mask) { 3048 enum phy phy = intel_port_to_phy(dev_priv, port); 3049 3050 bool ddi_clk_ungated = !(val & 3051 icl_dpclka_cfgcr0_clk_off(dev_priv, 3052 phy)); 3053 3054 if (ddi_clk_needed == ddi_clk_ungated) 3055 continue; 3056 3057 /* 3058 * Punt on the case now where clock is gated, but it would 3059 * be needed by the port. Something else is really broken then. 3060 */ 3061 if (WARN_ON(ddi_clk_needed)) 3062 continue; 3063 3064 DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n", 3065 phy_name(port)); 3066 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 3067 I915_WRITE(ICL_DPCLKA_CFGCR0, val); 3068 } 3069 } 3070 3071 static void intel_ddi_clk_select(struct intel_encoder *encoder, 3072 const struct intel_crtc_state *crtc_state) 3073 { 3074 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3075 enum port port = encoder->port; 3076 enum phy phy = intel_port_to_phy(dev_priv, port); 3077 u32 val; 3078 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 3079 3080 if (WARN_ON(!pll)) 3081 return; 3082 3083 mutex_lock(&dev_priv->dpll_lock); 3084 3085 if (INTEL_GEN(dev_priv) >= 11) { 3086 if (!intel_phy_is_combo(dev_priv, phy)) 3087 I915_WRITE(DDI_CLK_SEL(port), 3088 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 3089 else if (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C) 3090 /* 3091 * MG does not exist but the programming is required 3092 * to ungate DDIC and DDID 3093 */ 3094 I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 3095 } else if (IS_CANNONLAKE(dev_priv)) { 3096 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */ 3097 val = I915_READ(DPCLKA_CFGCR0); 3098 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); 3099 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port); 3100 I915_WRITE(DPCLKA_CFGCR0, val); 3101 3102 /* 3103 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI. 3104 * This step and the step before must be done with separate 3105 * register writes. 3106 */ 3107 val = I915_READ(DPCLKA_CFGCR0); 3108 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); 3109 I915_WRITE(DPCLKA_CFGCR0, val); 3110 } else if (IS_GEN9_BC(dev_priv)) { 3111 /* DDI -> PLL mapping */ 3112 val = I915_READ(DPLL_CTRL2); 3113 3114 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | 3115 DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); 3116 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 3117 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 3118 3119 I915_WRITE(DPLL_CTRL2, val); 3120 3121 } else if (INTEL_GEN(dev_priv) < 9) { 3122 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 3123 } 3124 3125 mutex_unlock(&dev_priv->dpll_lock); 3126 } 3127 3128 static void intel_ddi_clk_disable(struct intel_encoder *encoder) 3129 { 3130 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3131 enum port port = encoder->port; 3132 enum phy phy = intel_port_to_phy(dev_priv, port); 3133 3134 if (INTEL_GEN(dev_priv) >= 11) { 3135 if (!intel_phy_is_combo(dev_priv, phy) || 3136 (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C)) 3137 I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 3138 } else if (IS_CANNONLAKE(dev_priv)) { 3139 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) | 3140 DPCLKA_CFGCR0_DDI_CLK_OFF(port)); 3141 } else if (IS_GEN9_BC(dev_priv)) { 3142 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) | 3143 DPLL_CTRL2_DDI_CLK_OFF(port)); 3144 } else if (INTEL_GEN(dev_priv) < 9) { 3145 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 3146 } 3147 } 3148 3149 static void 3150 icl_phy_set_clock_gating(struct intel_digital_port *dig_port, bool enable) 3151 { 3152 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 3153 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port); 3154 u32 val, bits; 3155 int ln; 3156 3157 if (tc_port == PORT_TC_NONE) 3158 return; 3159 3160 bits = MG_DP_MODE_CFG_TR2PWR_GATING | MG_DP_MODE_CFG_TRPWR_GATING | 3161 MG_DP_MODE_CFG_CLNPWR_GATING | MG_DP_MODE_CFG_DIGPWR_GATING | 3162 MG_DP_MODE_CFG_GAONPWR_GATING; 3163 3164 for (ln = 0; ln < 2; ln++) { 3165 if (INTEL_GEN(dev_priv) >= 12) { 3166 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln)); 3167 val = I915_READ(DKL_DP_MODE(tc_port)); 3168 } else { 3169 val = I915_READ(MG_DP_MODE(ln, tc_port)); 3170 } 3171 3172 if (enable) 3173 val |= bits; 3174 else 3175 val &= ~bits; 3176 3177 if (INTEL_GEN(dev_priv) >= 12) 3178 I915_WRITE(DKL_DP_MODE(tc_port), val); 3179 else 3180 I915_WRITE(MG_DP_MODE(ln, tc_port), val); 3181 } 3182 3183 if (INTEL_GEN(dev_priv) == 11) { 3184 bits = MG_MISC_SUS0_CFG_TR2PWR_GATING | 3185 MG_MISC_SUS0_CFG_CL2PWR_GATING | 3186 MG_MISC_SUS0_CFG_GAONPWR_GATING | 3187 MG_MISC_SUS0_CFG_TRPWR_GATING | 3188 MG_MISC_SUS0_CFG_CL1PWR_GATING | 3189 MG_MISC_SUS0_CFG_DGPWR_GATING; 3190 3191 val = I915_READ(MG_MISC_SUS0(tc_port)); 3192 if (enable) 3193 val |= (bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3)); 3194 else 3195 val &= ~(bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK); 3196 I915_WRITE(MG_MISC_SUS0(tc_port), val); 3197 } 3198 } 3199 3200 static void 3201 icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port, 3202 const struct intel_crtc_state *crtc_state) 3203 { 3204 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); 3205 enum tc_port tc_port = intel_port_to_tc(dev_priv, intel_dig_port->base.port); 3206 u32 ln0, ln1, pin_assignment; 3207 u8 width; 3208 3209 if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT) 3210 return; 3211 3212 if (INTEL_GEN(dev_priv) >= 12) { 3213 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x0)); 3214 ln0 = I915_READ(DKL_DP_MODE(tc_port)); 3215 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x1)); 3216 ln1 = I915_READ(DKL_DP_MODE(tc_port)); 3217 } else { 3218 ln0 = I915_READ(MG_DP_MODE(0, tc_port)); 3219 ln1 = I915_READ(MG_DP_MODE(1, tc_port)); 3220 } 3221 3222 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X1_MODE); 3223 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 3224 3225 /* DPPATC */ 3226 pin_assignment = intel_tc_port_get_pin_assignment_mask(intel_dig_port); 3227 width = crtc_state->lane_count; 3228 3229 switch (pin_assignment) { 3230 case 0x0: 3231 WARN_ON(intel_dig_port->tc_mode != TC_PORT_LEGACY); 3232 if (width == 1) { 3233 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 3234 } else { 3235 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3236 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3237 } 3238 break; 3239 case 0x1: 3240 if (width == 4) { 3241 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3242 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3243 } 3244 break; 3245 case 0x2: 3246 if (width == 2) { 3247 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3248 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3249 } 3250 break; 3251 case 0x3: 3252 case 0x5: 3253 if (width == 1) { 3254 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 3255 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 3256 } else { 3257 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3258 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3259 } 3260 break; 3261 case 0x4: 3262 case 0x6: 3263 if (width == 1) { 3264 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 3265 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 3266 } else { 3267 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3268 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3269 } 3270 break; 3271 default: 3272 MISSING_CASE(pin_assignment); 3273 } 3274 3275 if (INTEL_GEN(dev_priv) >= 12) { 3276 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x0)); 3277 I915_WRITE(DKL_DP_MODE(tc_port), ln0); 3278 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x1)); 3279 I915_WRITE(DKL_DP_MODE(tc_port), ln1); 3280 } else { 3281 I915_WRITE(MG_DP_MODE(0, tc_port), ln0); 3282 I915_WRITE(MG_DP_MODE(1, tc_port), ln1); 3283 } 3284 } 3285 3286 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 3287 const struct intel_crtc_state *crtc_state) 3288 { 3289 if (!crtc_state->fec_enable) 3290 return; 3291 3292 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0) 3293 DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n"); 3294 } 3295 3296 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 3297 const struct intel_crtc_state *crtc_state) 3298 { 3299 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3300 struct intel_dp *intel_dp; 3301 u32 val; 3302 3303 if (!crtc_state->fec_enable) 3304 return; 3305 3306 intel_dp = enc_to_intel_dp(&encoder->base); 3307 val = I915_READ(intel_dp->regs.dp_tp_ctl); 3308 val |= DP_TP_CTL_FEC_ENABLE; 3309 I915_WRITE(intel_dp->regs.dp_tp_ctl, val); 3310 3311 if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, 3312 DP_TP_STATUS_FEC_ENABLE_LIVE, 1)) 3313 DRM_ERROR("Timed out waiting for FEC Enable Status\n"); 3314 } 3315 3316 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder, 3317 const struct intel_crtc_state *crtc_state) 3318 { 3319 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3320 struct intel_dp *intel_dp; 3321 u32 val; 3322 3323 if (!crtc_state->fec_enable) 3324 return; 3325 3326 intel_dp = enc_to_intel_dp(&encoder->base); 3327 val = I915_READ(intel_dp->regs.dp_tp_ctl); 3328 val &= ~DP_TP_CTL_FEC_ENABLE; 3329 I915_WRITE(intel_dp->regs.dp_tp_ctl, val); 3330 POSTING_READ(intel_dp->regs.dp_tp_ctl); 3331 } 3332 3333 static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder, 3334 const struct intel_crtc_state *crtc_state, 3335 const struct drm_connector_state *conn_state) 3336 { 3337 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 3338 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3339 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3340 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 3341 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 3342 int level = intel_ddi_dp_level(intel_dp); 3343 enum transcoder transcoder = crtc_state->cpu_transcoder; 3344 3345 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, 3346 crtc_state->lane_count, is_mst); 3347 3348 intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder); 3349 intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder); 3350 3351 /* 1.a got on intel_atomic_commit_tail() */ 3352 3353 /* 2. */ 3354 intel_edp_panel_on(intel_dp); 3355 3356 /* 3357 * 1.b, 3. and 4.a is done before tgl_ddi_pre_enable_dp() by: 3358 * haswell_crtc_enable()->intel_encoders_pre_pll_enable() and 3359 * haswell_crtc_enable()->intel_enable_shared_dpll() 3360 */ 3361 3362 /* 4.b */ 3363 intel_ddi_clk_select(encoder, crtc_state); 3364 3365 /* 5. */ 3366 if (!intel_phy_is_tc(dev_priv, phy) || 3367 dig_port->tc_mode != TC_PORT_TBT_ALT) 3368 intel_display_power_get(dev_priv, 3369 dig_port->ddi_io_power_domain); 3370 3371 /* 6. */ 3372 icl_program_mg_dp_mode(dig_port, crtc_state); 3373 3374 /* 3375 * 7.a - Steps in this function should only be executed over MST 3376 * master, what will be taken in care by MST hook 3377 * intel_mst_pre_enable_dp() 3378 */ 3379 intel_ddi_enable_pipe_clock(crtc_state); 3380 3381 /* 7.b */ 3382 intel_ddi_config_transcoder_func(crtc_state); 3383 3384 /* 7.d */ 3385 icl_phy_set_clock_gating(dig_port, false); 3386 3387 /* 7.e */ 3388 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level, 3389 encoder->type); 3390 3391 /* 7.f */ 3392 if (intel_phy_is_combo(dev_priv, phy)) { 3393 bool lane_reversal = 3394 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 3395 3396 intel_combo_phy_power_up_lanes(dev_priv, phy, false, 3397 crtc_state->lane_count, 3398 lane_reversal); 3399 } 3400 3401 /* 7.g */ 3402 intel_ddi_init_dp_buf_reg(encoder); 3403 3404 if (!is_mst) 3405 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 3406 3407 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); 3408 /* 3409 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 3410 * in the FEC_CONFIGURATION register to 1 before initiating link 3411 * training 3412 */ 3413 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 3414 /* 7.c, 7.h, 7.i, 7.j */ 3415 intel_dp_start_link_train(intel_dp); 3416 3417 /* 7.k */ 3418 intel_dp_stop_link_train(intel_dp); 3419 3420 /* 3421 * TODO: enable clock gating 3422 * 3423 * It is not written in DP enabling sequence but "PHY Clockgating 3424 * programming" states that clock gating should be enabled after the 3425 * link training but doing so causes all the following trainings to fail 3426 * so not enabling it for now. 3427 */ 3428 3429 /* 7.l */ 3430 intel_ddi_enable_fec(encoder, crtc_state); 3431 intel_dsc_enable(encoder, crtc_state); 3432 } 3433 3434 static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder, 3435 const struct intel_crtc_state *crtc_state, 3436 const struct drm_connector_state *conn_state) 3437 { 3438 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 3439 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3440 enum port port = encoder->port; 3441 enum phy phy = intel_port_to_phy(dev_priv, port); 3442 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 3443 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 3444 int level = intel_ddi_dp_level(intel_dp); 3445 3446 WARN_ON(is_mst && (port == PORT_A || port == PORT_E)); 3447 3448 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, 3449 crtc_state->lane_count, is_mst); 3450 3451 intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port); 3452 intel_dp->regs.dp_tp_status = DP_TP_STATUS(port); 3453 3454 intel_edp_panel_on(intel_dp); 3455 3456 intel_ddi_clk_select(encoder, crtc_state); 3457 3458 if (!intel_phy_is_tc(dev_priv, phy) || 3459 dig_port->tc_mode != TC_PORT_TBT_ALT) 3460 intel_display_power_get(dev_priv, 3461 dig_port->ddi_io_power_domain); 3462 3463 icl_program_mg_dp_mode(dig_port, crtc_state); 3464 icl_phy_set_clock_gating(dig_port, false); 3465 3466 if (INTEL_GEN(dev_priv) >= 11) 3467 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, 3468 level, encoder->type); 3469 else if (IS_CANNONLAKE(dev_priv)) 3470 cnl_ddi_vswing_sequence(encoder, level, encoder->type); 3471 else if (IS_GEN9_LP(dev_priv)) 3472 bxt_ddi_vswing_sequence(encoder, level, encoder->type); 3473 else 3474 intel_prepare_dp_ddi_buffers(encoder, crtc_state); 3475 3476 if (intel_phy_is_combo(dev_priv, phy)) { 3477 bool lane_reversal = 3478 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 3479 3480 intel_combo_phy_power_up_lanes(dev_priv, phy, false, 3481 crtc_state->lane_count, 3482 lane_reversal); 3483 } 3484 3485 intel_ddi_init_dp_buf_reg(encoder); 3486 if (!is_mst) 3487 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 3488 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, 3489 true); 3490 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 3491 intel_dp_start_link_train(intel_dp); 3492 if (port != PORT_A || INTEL_GEN(dev_priv) >= 9) 3493 intel_dp_stop_link_train(intel_dp); 3494 3495 intel_ddi_enable_fec(encoder, crtc_state); 3496 3497 icl_phy_set_clock_gating(dig_port, true); 3498 3499 if (!is_mst) 3500 intel_ddi_enable_pipe_clock(crtc_state); 3501 3502 intel_dsc_enable(encoder, crtc_state); 3503 } 3504 3505 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, 3506 const struct intel_crtc_state *crtc_state, 3507 const struct drm_connector_state *conn_state) 3508 { 3509 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3510 3511 if (INTEL_GEN(dev_priv) >= 12) 3512 tgl_ddi_pre_enable_dp(encoder, crtc_state, conn_state); 3513 else 3514 hsw_ddi_pre_enable_dp(encoder, crtc_state, conn_state); 3515 } 3516 3517 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder, 3518 const struct intel_crtc_state *crtc_state, 3519 const struct drm_connector_state *conn_state) 3520 { 3521 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); 3522 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 3523 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3524 enum port port = encoder->port; 3525 int level = intel_ddi_hdmi_level(dev_priv, port); 3526 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 3527 3528 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 3529 intel_ddi_clk_select(encoder, crtc_state); 3530 3531 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); 3532 3533 icl_program_mg_dp_mode(dig_port, crtc_state); 3534 icl_phy_set_clock_gating(dig_port, false); 3535 3536 if (INTEL_GEN(dev_priv) >= 12) 3537 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, 3538 level, INTEL_OUTPUT_HDMI); 3539 else if (INTEL_GEN(dev_priv) == 11) 3540 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, 3541 level, INTEL_OUTPUT_HDMI); 3542 else if (IS_CANNONLAKE(dev_priv)) 3543 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI); 3544 else if (IS_GEN9_LP(dev_priv)) 3545 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI); 3546 else 3547 intel_prepare_hdmi_ddi_buffers(encoder, level); 3548 3549 icl_phy_set_clock_gating(dig_port, true); 3550 3551 if (IS_GEN9_BC(dev_priv)) 3552 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI); 3553 3554 intel_ddi_enable_pipe_clock(crtc_state); 3555 3556 intel_dig_port->set_infoframes(encoder, 3557 crtc_state->has_infoframe, 3558 crtc_state, conn_state); 3559 } 3560 3561 static void intel_ddi_pre_enable(struct intel_encoder *encoder, 3562 const struct intel_crtc_state *crtc_state, 3563 const struct drm_connector_state *conn_state) 3564 { 3565 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 3566 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3567 enum pipe pipe = crtc->pipe; 3568 3569 /* 3570 * When called from DP MST code: 3571 * - conn_state will be NULL 3572 * - encoder will be the main encoder (ie. mst->primary) 3573 * - the main connector associated with this port 3574 * won't be active or linked to a crtc 3575 * - crtc_state will be the state of the first stream to 3576 * be activated on this port, and it may not be the same 3577 * stream that will be deactivated last, but each stream 3578 * should have a state that is identical when it comes to 3579 * the DP link parameteres 3580 */ 3581 3582 WARN_ON(crtc_state->has_pch_encoder); 3583 3584 if (INTEL_GEN(dev_priv) >= 11) 3585 icl_map_plls_to_ports(encoder, crtc_state); 3586 3587 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 3588 3589 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 3590 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state); 3591 } else { 3592 struct intel_lspcon *lspcon = 3593 enc_to_intel_lspcon(&encoder->base); 3594 3595 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state); 3596 if (lspcon->active) { 3597 struct intel_digital_port *dig_port = 3598 enc_to_dig_port(&encoder->base); 3599 3600 dig_port->set_infoframes(encoder, 3601 crtc_state->has_infoframe, 3602 crtc_state, conn_state); 3603 } 3604 } 3605 } 3606 3607 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 3608 const struct intel_crtc_state *crtc_state) 3609 { 3610 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3611 enum port port = encoder->port; 3612 bool wait = false; 3613 u32 val; 3614 3615 val = I915_READ(DDI_BUF_CTL(port)); 3616 if (val & DDI_BUF_CTL_ENABLE) { 3617 val &= ~DDI_BUF_CTL_ENABLE; 3618 I915_WRITE(DDI_BUF_CTL(port), val); 3619 wait = true; 3620 } 3621 3622 if (intel_crtc_has_dp_encoder(crtc_state)) { 3623 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 3624 3625 val = I915_READ(intel_dp->regs.dp_tp_ctl); 3626 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 3627 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 3628 I915_WRITE(intel_dp->regs.dp_tp_ctl, val); 3629 } 3630 3631 /* Disable FEC in DP Sink */ 3632 intel_ddi_disable_fec_state(encoder, crtc_state); 3633 3634 if (wait) 3635 intel_wait_ddi_buf_idle(dev_priv, port); 3636 } 3637 3638 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder, 3639 const struct intel_crtc_state *old_crtc_state, 3640 const struct drm_connector_state *old_conn_state) 3641 { 3642 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3643 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 3644 struct intel_dp *intel_dp = &dig_port->dp; 3645 bool is_mst = intel_crtc_has_type(old_crtc_state, 3646 INTEL_OUTPUT_DP_MST); 3647 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3648 3649 if (!is_mst) { 3650 intel_ddi_disable_pipe_clock(old_crtc_state); 3651 /* 3652 * Power down sink before disabling the port, otherwise we end 3653 * up getting interrupts from the sink on detecting link loss. 3654 */ 3655 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 3656 } 3657 3658 intel_disable_ddi_buf(encoder, old_crtc_state); 3659 3660 intel_edp_panel_vdd_on(intel_dp); 3661 intel_edp_panel_off(intel_dp); 3662 3663 if (!intel_phy_is_tc(dev_priv, phy) || 3664 dig_port->tc_mode != TC_PORT_TBT_ALT) 3665 intel_display_power_put_unchecked(dev_priv, 3666 dig_port->ddi_io_power_domain); 3667 3668 intel_ddi_clk_disable(encoder); 3669 } 3670 3671 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder, 3672 const struct intel_crtc_state *old_crtc_state, 3673 const struct drm_connector_state *old_conn_state) 3674 { 3675 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3676 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 3677 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3678 3679 dig_port->set_infoframes(encoder, false, 3680 old_crtc_state, old_conn_state); 3681 3682 intel_ddi_disable_pipe_clock(old_crtc_state); 3683 3684 intel_disable_ddi_buf(encoder, old_crtc_state); 3685 3686 intel_display_power_put_unchecked(dev_priv, 3687 dig_port->ddi_io_power_domain); 3688 3689 intel_ddi_clk_disable(encoder); 3690 3691 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3692 } 3693 3694 static void intel_ddi_post_disable(struct intel_encoder *encoder, 3695 const struct intel_crtc_state *old_crtc_state, 3696 const struct drm_connector_state *old_conn_state) 3697 { 3698 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3699 3700 /* 3701 * When called from DP MST code: 3702 * - old_conn_state will be NULL 3703 * - encoder will be the main encoder (ie. mst->primary) 3704 * - the main connector associated with this port 3705 * won't be active or linked to a crtc 3706 * - old_crtc_state will be the state of the last stream to 3707 * be deactivated on this port, and it may not be the same 3708 * stream that was activated last, but each stream 3709 * should have a state that is identical when it comes to 3710 * the DP link parameteres 3711 */ 3712 3713 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3714 intel_ddi_post_disable_hdmi(encoder, 3715 old_crtc_state, old_conn_state); 3716 else 3717 intel_ddi_post_disable_dp(encoder, 3718 old_crtc_state, old_conn_state); 3719 3720 if (INTEL_GEN(dev_priv) >= 11) 3721 icl_unmap_plls_to_ports(encoder); 3722 } 3723 3724 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder, 3725 const struct intel_crtc_state *old_crtc_state, 3726 const struct drm_connector_state *old_conn_state) 3727 { 3728 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3729 u32 val; 3730 3731 /* 3732 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable) 3733 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN, 3734 * step 13 is the correct place for it. Step 18 is where it was 3735 * originally before the BUN. 3736 */ 3737 val = I915_READ(FDI_RX_CTL(PIPE_A)); 3738 val &= ~FDI_RX_ENABLE; 3739 I915_WRITE(FDI_RX_CTL(PIPE_A), val); 3740 3741 intel_disable_ddi_buf(encoder, old_crtc_state); 3742 intel_ddi_clk_disable(encoder); 3743 3744 val = I915_READ(FDI_RX_MISC(PIPE_A)); 3745 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 3746 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 3747 I915_WRITE(FDI_RX_MISC(PIPE_A), val); 3748 3749 val = I915_READ(FDI_RX_CTL(PIPE_A)); 3750 val &= ~FDI_PCDCLK; 3751 I915_WRITE(FDI_RX_CTL(PIPE_A), val); 3752 3753 val = I915_READ(FDI_RX_CTL(PIPE_A)); 3754 val &= ~FDI_RX_PLL_ENABLE; 3755 I915_WRITE(FDI_RX_CTL(PIPE_A), val); 3756 } 3757 3758 static void intel_enable_ddi_dp(struct intel_encoder *encoder, 3759 const struct intel_crtc_state *crtc_state, 3760 const struct drm_connector_state *conn_state) 3761 { 3762 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3763 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 3764 enum port port = encoder->port; 3765 3766 if (port == PORT_A && INTEL_GEN(dev_priv) < 9) 3767 intel_dp_stop_link_train(intel_dp); 3768 3769 intel_edp_backlight_on(crtc_state, conn_state); 3770 intel_psr_enable(intel_dp, crtc_state); 3771 intel_dp_ycbcr_420_enable(intel_dp, crtc_state); 3772 intel_edp_drrs_enable(intel_dp, crtc_state); 3773 3774 if (crtc_state->has_audio) 3775 intel_audio_codec_enable(encoder, crtc_state, conn_state); 3776 } 3777 3778 static i915_reg_t 3779 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 3780 enum port port) 3781 { 3782 static const i915_reg_t regs[] = { 3783 [PORT_A] = CHICKEN_TRANS_EDP, 3784 [PORT_B] = CHICKEN_TRANS_A, 3785 [PORT_C] = CHICKEN_TRANS_B, 3786 [PORT_D] = CHICKEN_TRANS_C, 3787 [PORT_E] = CHICKEN_TRANS_A, 3788 }; 3789 3790 WARN_ON(INTEL_GEN(dev_priv) < 9); 3791 3792 if (WARN_ON(port < PORT_A || port > PORT_E)) 3793 port = PORT_A; 3794 3795 return regs[port]; 3796 } 3797 3798 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder, 3799 const struct intel_crtc_state *crtc_state, 3800 const struct drm_connector_state *conn_state) 3801 { 3802 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3803 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 3804 struct drm_connector *connector = conn_state->connector; 3805 enum port port = encoder->port; 3806 3807 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3808 crtc_state->hdmi_high_tmds_clock_ratio, 3809 crtc_state->hdmi_scrambling)) 3810 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3811 connector->base.id, connector->name); 3812 3813 /* Display WA #1143: skl,kbl,cfl */ 3814 if (IS_GEN9_BC(dev_priv)) { 3815 /* 3816 * For some reason these chicken bits have been 3817 * stuffed into a transcoder register, event though 3818 * the bits affect a specific DDI port rather than 3819 * a specific transcoder. 3820 */ 3821 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 3822 u32 val; 3823 3824 val = I915_READ(reg); 3825 3826 if (port == PORT_E) 3827 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3828 DDIE_TRAINING_OVERRIDE_VALUE; 3829 else 3830 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3831 DDI_TRAINING_OVERRIDE_VALUE; 3832 3833 I915_WRITE(reg, val); 3834 POSTING_READ(reg); 3835 3836 udelay(1); 3837 3838 if (port == PORT_E) 3839 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3840 DDIE_TRAINING_OVERRIDE_VALUE); 3841 else 3842 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3843 DDI_TRAINING_OVERRIDE_VALUE); 3844 3845 I915_WRITE(reg, val); 3846 } 3847 3848 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3849 * are ignored so nothing special needs to be done besides 3850 * enabling the port. 3851 */ 3852 I915_WRITE(DDI_BUF_CTL(port), 3853 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE); 3854 3855 if (crtc_state->has_audio) 3856 intel_audio_codec_enable(encoder, crtc_state, conn_state); 3857 } 3858 3859 static void intel_enable_ddi(struct intel_encoder *encoder, 3860 const struct intel_crtc_state *crtc_state, 3861 const struct drm_connector_state *conn_state) 3862 { 3863 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3864 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state); 3865 else 3866 intel_enable_ddi_dp(encoder, crtc_state, conn_state); 3867 3868 /* Enable hdcp if it's desired */ 3869 if (conn_state->content_protection == 3870 DRM_MODE_CONTENT_PROTECTION_DESIRED) 3871 intel_hdcp_enable(to_intel_connector(conn_state->connector), 3872 (u8)conn_state->hdcp_content_type); 3873 } 3874 3875 static void intel_disable_ddi_dp(struct intel_encoder *encoder, 3876 const struct intel_crtc_state *old_crtc_state, 3877 const struct drm_connector_state *old_conn_state) 3878 { 3879 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 3880 3881 intel_dp->link_trained = false; 3882 3883 if (old_crtc_state->has_audio) 3884 intel_audio_codec_disable(encoder, 3885 old_crtc_state, old_conn_state); 3886 3887 intel_edp_drrs_disable(intel_dp, old_crtc_state); 3888 intel_psr_disable(intel_dp, old_crtc_state); 3889 intel_edp_backlight_off(old_conn_state); 3890 /* Disable the decompression in DP Sink */ 3891 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, 3892 false); 3893 } 3894 3895 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder, 3896 const struct intel_crtc_state *old_crtc_state, 3897 const struct drm_connector_state *old_conn_state) 3898 { 3899 struct drm_connector *connector = old_conn_state->connector; 3900 3901 if (old_crtc_state->has_audio) 3902 intel_audio_codec_disable(encoder, 3903 old_crtc_state, old_conn_state); 3904 3905 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3906 false, false)) 3907 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3908 connector->base.id, connector->name); 3909 } 3910 3911 static void intel_disable_ddi(struct intel_encoder *encoder, 3912 const struct intel_crtc_state *old_crtc_state, 3913 const struct drm_connector_state *old_conn_state) 3914 { 3915 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3916 3917 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3918 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state); 3919 else 3920 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state); 3921 } 3922 3923 static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder, 3924 const struct intel_crtc_state *crtc_state, 3925 const struct drm_connector_state *conn_state) 3926 { 3927 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 3928 3929 intel_ddi_set_pipe_settings(crtc_state); 3930 3931 intel_psr_update(intel_dp, crtc_state); 3932 intel_edp_drrs_enable(intel_dp, crtc_state); 3933 3934 intel_panel_update_backlight(encoder, crtc_state, conn_state); 3935 } 3936 3937 static void intel_ddi_update_pipe(struct intel_encoder *encoder, 3938 const struct intel_crtc_state *crtc_state, 3939 const struct drm_connector_state *conn_state) 3940 { 3941 struct intel_connector *connector = 3942 to_intel_connector(conn_state->connector); 3943 struct intel_hdcp *hdcp = &connector->hdcp; 3944 bool content_protection_type_changed = 3945 (conn_state->hdcp_content_type != hdcp->content_type && 3946 conn_state->content_protection != 3947 DRM_MODE_CONTENT_PROTECTION_UNDESIRED); 3948 3949 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3950 intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state); 3951 3952 /* 3953 * During the HDCP encryption session if Type change is requested, 3954 * disable the HDCP and reenable it with new TYPE value. 3955 */ 3956 if (conn_state->content_protection == 3957 DRM_MODE_CONTENT_PROTECTION_UNDESIRED || 3958 content_protection_type_changed) 3959 intel_hdcp_disable(connector); 3960 3961 /* 3962 * Mark the hdcp state as DESIRED after the hdcp disable of type 3963 * change procedure. 3964 */ 3965 if (content_protection_type_changed) { 3966 mutex_lock(&hdcp->mutex); 3967 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; 3968 schedule_work(&hdcp->prop_work); 3969 mutex_unlock(&hdcp->mutex); 3970 } 3971 3972 if (conn_state->content_protection == 3973 DRM_MODE_CONTENT_PROTECTION_DESIRED || 3974 content_protection_type_changed) 3975 intel_hdcp_enable(connector, (u8)conn_state->hdcp_content_type); 3976 } 3977 3978 static void 3979 intel_ddi_update_prepare(struct intel_atomic_state *state, 3980 struct intel_encoder *encoder, 3981 struct intel_crtc *crtc) 3982 { 3983 struct intel_crtc_state *crtc_state = 3984 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL; 3985 int required_lanes = crtc_state ? crtc_state->lane_count : 1; 3986 3987 WARN_ON(crtc && crtc->active); 3988 3989 intel_tc_port_get_link(enc_to_dig_port(&encoder->base), required_lanes); 3990 if (crtc_state && crtc_state->base.active) 3991 intel_update_active_dpll(state, crtc, encoder); 3992 } 3993 3994 static void 3995 intel_ddi_update_complete(struct intel_atomic_state *state, 3996 struct intel_encoder *encoder, 3997 struct intel_crtc *crtc) 3998 { 3999 intel_tc_port_put_link(enc_to_dig_port(&encoder->base)); 4000 } 4001 4002 static void 4003 intel_ddi_pre_pll_enable(struct intel_encoder *encoder, 4004 const struct intel_crtc_state *crtc_state, 4005 const struct drm_connector_state *conn_state) 4006 { 4007 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4008 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 4009 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 4010 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 4011 4012 if (is_tc_port) 4013 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 4014 4015 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) 4016 intel_display_power_get(dev_priv, 4017 intel_ddi_main_link_aux_domain(dig_port)); 4018 4019 if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT) 4020 /* 4021 * Program the lane count for static/dynamic connections on 4022 * Type-C ports. Skip this step for TBT. 4023 */ 4024 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 4025 else if (IS_GEN9_LP(dev_priv)) 4026 bxt_ddi_phy_set_lane_optim_mask(encoder, 4027 crtc_state->lane_lat_optim_mask); 4028 } 4029 4030 static void 4031 intel_ddi_post_pll_disable(struct intel_encoder *encoder, 4032 const struct intel_crtc_state *crtc_state, 4033 const struct drm_connector_state *conn_state) 4034 { 4035 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4036 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 4037 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 4038 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 4039 4040 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) 4041 intel_display_power_put_unchecked(dev_priv, 4042 intel_ddi_main_link_aux_domain(dig_port)); 4043 4044 if (is_tc_port) 4045 intel_tc_port_put_link(dig_port); 4046 } 4047 4048 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) 4049 { 4050 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 4051 struct drm_i915_private *dev_priv = 4052 to_i915(intel_dig_port->base.base.dev); 4053 enum port port = intel_dig_port->base.port; 4054 u32 val; 4055 bool wait = false; 4056 4057 if (I915_READ(intel_dp->regs.dp_tp_ctl) & DP_TP_CTL_ENABLE) { 4058 val = I915_READ(DDI_BUF_CTL(port)); 4059 if (val & DDI_BUF_CTL_ENABLE) { 4060 val &= ~DDI_BUF_CTL_ENABLE; 4061 I915_WRITE(DDI_BUF_CTL(port), val); 4062 wait = true; 4063 } 4064 4065 val = I915_READ(intel_dp->regs.dp_tp_ctl); 4066 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 4067 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 4068 I915_WRITE(intel_dp->regs.dp_tp_ctl, val); 4069 POSTING_READ(intel_dp->regs.dp_tp_ctl); 4070 4071 if (wait) 4072 intel_wait_ddi_buf_idle(dev_priv, port); 4073 } 4074 4075 val = DP_TP_CTL_ENABLE | 4076 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; 4077 if (intel_dp->link_mst) 4078 val |= DP_TP_CTL_MODE_MST; 4079 else { 4080 val |= DP_TP_CTL_MODE_SST; 4081 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 4082 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4083 } 4084 I915_WRITE(intel_dp->regs.dp_tp_ctl, val); 4085 POSTING_READ(intel_dp->regs.dp_tp_ctl); 4086 4087 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 4088 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); 4089 POSTING_READ(DDI_BUF_CTL(port)); 4090 4091 udelay(600); 4092 } 4093 4094 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 4095 enum transcoder cpu_transcoder) 4096 { 4097 if (cpu_transcoder == TRANSCODER_EDP) 4098 return false; 4099 4100 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) 4101 return false; 4102 4103 return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) & 4104 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 4105 } 4106 4107 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, 4108 struct intel_crtc_state *crtc_state) 4109 { 4110 if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000) 4111 crtc_state->min_voltage_level = 1; 4112 else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000) 4113 crtc_state->min_voltage_level = 2; 4114 } 4115 4116 void intel_ddi_get_config(struct intel_encoder *encoder, 4117 struct intel_crtc_state *pipe_config) 4118 { 4119 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4120 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); 4121 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4122 u32 temp, flags = 0; 4123 4124 /* XXX: DSI transcoder paranoia */ 4125 if (WARN_ON(transcoder_is_dsi(cpu_transcoder))) 4126 return; 4127 4128 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 4129 if (temp & TRANS_DDI_PHSYNC) 4130 flags |= DRM_MODE_FLAG_PHSYNC; 4131 else 4132 flags |= DRM_MODE_FLAG_NHSYNC; 4133 if (temp & TRANS_DDI_PVSYNC) 4134 flags |= DRM_MODE_FLAG_PVSYNC; 4135 else 4136 flags |= DRM_MODE_FLAG_NVSYNC; 4137 4138 pipe_config->base.adjusted_mode.flags |= flags; 4139 4140 switch (temp & TRANS_DDI_BPC_MASK) { 4141 case TRANS_DDI_BPC_6: 4142 pipe_config->pipe_bpp = 18; 4143 break; 4144 case TRANS_DDI_BPC_8: 4145 pipe_config->pipe_bpp = 24; 4146 break; 4147 case TRANS_DDI_BPC_10: 4148 pipe_config->pipe_bpp = 30; 4149 break; 4150 case TRANS_DDI_BPC_12: 4151 pipe_config->pipe_bpp = 36; 4152 break; 4153 default: 4154 break; 4155 } 4156 4157 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 4158 case TRANS_DDI_MODE_SELECT_HDMI: 4159 pipe_config->has_hdmi_sink = true; 4160 4161 pipe_config->infoframes.enable |= 4162 intel_hdmi_infoframes_enabled(encoder, pipe_config); 4163 4164 if (pipe_config->infoframes.enable) 4165 pipe_config->has_infoframe = true; 4166 4167 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 4168 pipe_config->hdmi_scrambling = true; 4169 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 4170 pipe_config->hdmi_high_tmds_clock_ratio = true; 4171 /* fall through */ 4172 case TRANS_DDI_MODE_SELECT_DVI: 4173 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 4174 pipe_config->lane_count = 4; 4175 break; 4176 case TRANS_DDI_MODE_SELECT_FDI: 4177 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 4178 break; 4179 case TRANS_DDI_MODE_SELECT_DP_SST: 4180 if (encoder->type == INTEL_OUTPUT_EDP) 4181 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 4182 else 4183 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 4184 pipe_config->lane_count = 4185 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4186 intel_dp_get_m_n(intel_crtc, pipe_config); 4187 4188 if (INTEL_GEN(dev_priv) >= 11) { 4189 i915_reg_t dp_tp_ctl; 4190 4191 if (IS_GEN(dev_priv, 11)) 4192 dp_tp_ctl = DP_TP_CTL(encoder->port); 4193 else 4194 dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder); 4195 4196 pipe_config->fec_enable = 4197 I915_READ(dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE; 4198 4199 DRM_DEBUG_KMS("[ENCODER:%d:%s] Fec status: %u\n", 4200 encoder->base.base.id, encoder->base.name, 4201 pipe_config->fec_enable); 4202 } 4203 4204 break; 4205 case TRANS_DDI_MODE_SELECT_DP_MST: 4206 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 4207 pipe_config->lane_count = 4208 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4209 intel_dp_get_m_n(intel_crtc, pipe_config); 4210 break; 4211 default: 4212 break; 4213 } 4214 4215 pipe_config->has_audio = 4216 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 4217 4218 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp && 4219 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { 4220 /* 4221 * This is a big fat ugly hack. 4222 * 4223 * Some machines in UEFI boot mode provide us a VBT that has 18 4224 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 4225 * unknown we fail to light up. Yet the same BIOS boots up with 4226 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 4227 * max, not what it tells us to use. 4228 * 4229 * Note: This will still be broken if the eDP panel is not lit 4230 * up by the BIOS, and thus we can't get the mode at module 4231 * load. 4232 */ 4233 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 4234 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); 4235 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; 4236 } 4237 4238 intel_ddi_clock_get(encoder, pipe_config); 4239 4240 if (IS_GEN9_LP(dev_priv)) 4241 pipe_config->lane_lat_optim_mask = 4242 bxt_ddi_phy_get_lane_lat_optim_mask(encoder); 4243 4244 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 4245 4246 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 4247 4248 intel_read_infoframe(encoder, pipe_config, 4249 HDMI_INFOFRAME_TYPE_AVI, 4250 &pipe_config->infoframes.avi); 4251 intel_read_infoframe(encoder, pipe_config, 4252 HDMI_INFOFRAME_TYPE_SPD, 4253 &pipe_config->infoframes.spd); 4254 intel_read_infoframe(encoder, pipe_config, 4255 HDMI_INFOFRAME_TYPE_VENDOR, 4256 &pipe_config->infoframes.hdmi); 4257 intel_read_infoframe(encoder, pipe_config, 4258 HDMI_INFOFRAME_TYPE_DRM, 4259 &pipe_config->infoframes.drm); 4260 } 4261 4262 static enum intel_output_type 4263 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4264 struct intel_crtc_state *crtc_state, 4265 struct drm_connector_state *conn_state) 4266 { 4267 switch (conn_state->connector->connector_type) { 4268 case DRM_MODE_CONNECTOR_HDMIA: 4269 return INTEL_OUTPUT_HDMI; 4270 case DRM_MODE_CONNECTOR_eDP: 4271 return INTEL_OUTPUT_EDP; 4272 case DRM_MODE_CONNECTOR_DisplayPort: 4273 return INTEL_OUTPUT_DP; 4274 default: 4275 MISSING_CASE(conn_state->connector->connector_type); 4276 return INTEL_OUTPUT_UNUSED; 4277 } 4278 } 4279 4280 static int intel_ddi_compute_config(struct intel_encoder *encoder, 4281 struct intel_crtc_state *pipe_config, 4282 struct drm_connector_state *conn_state) 4283 { 4284 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); 4285 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4286 enum port port = encoder->port; 4287 int ret; 4288 4289 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) 4290 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4291 4292 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) 4293 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4294 else 4295 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 4296 if (ret) 4297 return ret; 4298 4299 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 4300 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4301 pipe_config->pch_pfit.force_thru = 4302 pipe_config->pch_pfit.enabled || 4303 pipe_config->crc_enabled; 4304 4305 if (IS_GEN9_LP(dev_priv)) 4306 pipe_config->lane_lat_optim_mask = 4307 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4308 4309 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 4310 4311 return 0; 4312 } 4313 4314 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4315 { 4316 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4317 4318 intel_dp_encoder_flush_work(encoder); 4319 4320 drm_encoder_cleanup(encoder); 4321 kfree(dig_port); 4322 } 4323 4324 static const struct drm_encoder_funcs intel_ddi_funcs = { 4325 .reset = intel_dp_encoder_reset, 4326 .destroy = intel_ddi_encoder_destroy, 4327 }; 4328 4329 static struct intel_connector * 4330 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) 4331 { 4332 struct intel_connector *connector; 4333 enum port port = intel_dig_port->base.port; 4334 4335 connector = intel_connector_alloc(); 4336 if (!connector) 4337 return NULL; 4338 4339 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); 4340 intel_dig_port->dp.prepare_link_retrain = 4341 intel_ddi_prepare_link_retrain; 4342 4343 if (!intel_dp_init_connector(intel_dig_port, connector)) { 4344 kfree(connector); 4345 return NULL; 4346 } 4347 4348 return connector; 4349 } 4350 4351 static int modeset_pipe(struct drm_crtc *crtc, 4352 struct drm_modeset_acquire_ctx *ctx) 4353 { 4354 struct drm_atomic_state *state; 4355 struct drm_crtc_state *crtc_state; 4356 int ret; 4357 4358 state = drm_atomic_state_alloc(crtc->dev); 4359 if (!state) 4360 return -ENOMEM; 4361 4362 state->acquire_ctx = ctx; 4363 4364 crtc_state = drm_atomic_get_crtc_state(state, crtc); 4365 if (IS_ERR(crtc_state)) { 4366 ret = PTR_ERR(crtc_state); 4367 goto out; 4368 } 4369 4370 crtc_state->connectors_changed = true; 4371 4372 ret = drm_atomic_commit(state); 4373 out: 4374 drm_atomic_state_put(state); 4375 4376 return ret; 4377 } 4378 4379 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4380 struct drm_modeset_acquire_ctx *ctx) 4381 { 4382 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4383 struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base); 4384 struct intel_connector *connector = hdmi->attached_connector; 4385 struct i2c_adapter *adapter = 4386 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 4387 struct drm_connector_state *conn_state; 4388 struct intel_crtc_state *crtc_state; 4389 struct intel_crtc *crtc; 4390 u8 config; 4391 int ret; 4392 4393 if (!connector || connector->base.status != connector_status_connected) 4394 return 0; 4395 4396 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 4397 ctx); 4398 if (ret) 4399 return ret; 4400 4401 conn_state = connector->base.state; 4402 4403 crtc = to_intel_crtc(conn_state->crtc); 4404 if (!crtc) 4405 return 0; 4406 4407 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4408 if (ret) 4409 return ret; 4410 4411 crtc_state = to_intel_crtc_state(crtc->base.state); 4412 4413 WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4414 4415 if (!crtc_state->base.active) 4416 return 0; 4417 4418 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4419 !crtc_state->hdmi_scrambling) 4420 return 0; 4421 4422 if (conn_state->commit && 4423 !try_wait_for_completion(&conn_state->commit->hw_done)) 4424 return 0; 4425 4426 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 4427 if (ret < 0) { 4428 DRM_ERROR("Failed to read TMDS config: %d\n", ret); 4429 return 0; 4430 } 4431 4432 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4433 crtc_state->hdmi_high_tmds_clock_ratio && 4434 !!(config & SCDC_SCRAMBLING_ENABLE) == 4435 crtc_state->hdmi_scrambling) 4436 return 0; 4437 4438 /* 4439 * HDMI 2.0 says that one should not send scrambled data 4440 * prior to configuring the sink scrambling, and that 4441 * TMDS clock/data transmission should be suspended when 4442 * changing the TMDS clock rate in the sink. So let's 4443 * just do a full modeset here, even though some sinks 4444 * would be perfectly happy if were to just reconfigure 4445 * the SCDC settings on the fly. 4446 */ 4447 return modeset_pipe(&crtc->base, ctx); 4448 } 4449 4450 static enum intel_hotplug_state 4451 intel_ddi_hotplug(struct intel_encoder *encoder, 4452 struct intel_connector *connector, 4453 bool irq_received) 4454 { 4455 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 4456 struct drm_modeset_acquire_ctx ctx; 4457 enum intel_hotplug_state state; 4458 int ret; 4459 4460 state = intel_encoder_hotplug(encoder, connector, irq_received); 4461 4462 drm_modeset_acquire_init(&ctx, 0); 4463 4464 for (;;) { 4465 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) 4466 ret = intel_hdmi_reset_link(encoder, &ctx); 4467 else 4468 ret = intel_dp_retrain_link(encoder, &ctx); 4469 4470 if (ret == -EDEADLK) { 4471 drm_modeset_backoff(&ctx); 4472 continue; 4473 } 4474 4475 break; 4476 } 4477 4478 drm_modeset_drop_locks(&ctx); 4479 drm_modeset_acquire_fini(&ctx); 4480 WARN(ret, "Acquiring modeset locks failed with %i\n", ret); 4481 4482 /* 4483 * Unpowered type-c dongles can take some time to boot and be 4484 * responsible, so here giving some time to those dongles to power up 4485 * and then retrying the probe. 4486 * 4487 * On many platforms the HDMI live state signal is known to be 4488 * unreliable, so we can't use it to detect if a sink is connected or 4489 * not. Instead we detect if it's connected based on whether we can 4490 * read the EDID or not. That in turn has a problem during disconnect, 4491 * since the HPD interrupt may be raised before the DDC lines get 4492 * disconnected (due to how the required length of DDC vs. HPD 4493 * connector pins are specified) and so we'll still be able to get a 4494 * valid EDID. To solve this schedule another detection cycle if this 4495 * time around we didn't detect any change in the sink's connection 4496 * status. 4497 */ 4498 if (state == INTEL_HOTPLUG_UNCHANGED && irq_received && 4499 !dig_port->dp.is_mst) 4500 state = INTEL_HOTPLUG_RETRY; 4501 4502 return state; 4503 } 4504 4505 static struct intel_connector * 4506 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) 4507 { 4508 struct intel_connector *connector; 4509 enum port port = intel_dig_port->base.port; 4510 4511 connector = intel_connector_alloc(); 4512 if (!connector) 4513 return NULL; 4514 4515 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4516 intel_hdmi_init_connector(intel_dig_port, connector); 4517 4518 return connector; 4519 } 4520 4521 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport) 4522 { 4523 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); 4524 4525 if (dport->base.port != PORT_A) 4526 return false; 4527 4528 if (dport->saved_port_bits & DDI_A_4_LANES) 4529 return false; 4530 4531 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4532 * supported configuration 4533 */ 4534 if (IS_GEN9_LP(dev_priv)) 4535 return true; 4536 4537 /* Cannonlake: Most of SKUs don't support DDI_E, and the only 4538 * one who does also have a full A/E split called 4539 * DDI_F what makes DDI_E useless. However for this 4540 * case let's trust VBT info. 4541 */ 4542 if (IS_CANNONLAKE(dev_priv) && 4543 !intel_bios_is_port_present(dev_priv, PORT_E)) 4544 return true; 4545 4546 return false; 4547 } 4548 4549 static int 4550 intel_ddi_max_lanes(struct intel_digital_port *intel_dport) 4551 { 4552 struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev); 4553 enum port port = intel_dport->base.port; 4554 int max_lanes = 4; 4555 4556 if (INTEL_GEN(dev_priv) >= 11) 4557 return max_lanes; 4558 4559 if (port == PORT_A || port == PORT_E) { 4560 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4561 max_lanes = port == PORT_A ? 4 : 0; 4562 else 4563 /* Both A and E share 2 lanes */ 4564 max_lanes = 2; 4565 } 4566 4567 /* 4568 * Some BIOS might fail to set this bit on port A if eDP 4569 * wasn't lit up at boot. Force this bit set when needed 4570 * so we use the proper lane count for our calculations. 4571 */ 4572 if (intel_ddi_a_force_4_lanes(intel_dport)) { 4573 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n"); 4574 intel_dport->saved_port_bits |= DDI_A_4_LANES; 4575 max_lanes = 4; 4576 } 4577 4578 return max_lanes; 4579 } 4580 4581 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 4582 { 4583 struct ddi_vbt_port_info *port_info = 4584 &dev_priv->vbt.ddi_port_info[port]; 4585 struct intel_digital_port *intel_dig_port; 4586 struct intel_encoder *intel_encoder; 4587 struct drm_encoder *encoder; 4588 bool init_hdmi, init_dp, init_lspcon = false; 4589 enum pipe pipe; 4590 enum phy phy = intel_port_to_phy(dev_priv, port); 4591 4592 init_hdmi = port_info->supports_dvi || port_info->supports_hdmi; 4593 init_dp = port_info->supports_dp; 4594 4595 if (intel_bios_is_lspcon_present(dev_priv, port)) { 4596 /* 4597 * Lspcon device needs to be driven with DP connector 4598 * with special detection sequence. So make sure DP 4599 * is initialized before lspcon. 4600 */ 4601 init_dp = true; 4602 init_lspcon = true; 4603 init_hdmi = false; 4604 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port)); 4605 } 4606 4607 if (!init_dp && !init_hdmi) { 4608 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 4609 port_name(port)); 4610 return; 4611 } 4612 4613 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 4614 if (!intel_dig_port) 4615 return; 4616 4617 intel_encoder = &intel_dig_port->base; 4618 encoder = &intel_encoder->base; 4619 4620 drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs, 4621 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port)); 4622 4623 intel_encoder->hotplug = intel_ddi_hotplug; 4624 intel_encoder->compute_output_type = intel_ddi_compute_output_type; 4625 intel_encoder->compute_config = intel_ddi_compute_config; 4626 intel_encoder->enable = intel_enable_ddi; 4627 intel_encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 4628 intel_encoder->post_pll_disable = intel_ddi_post_pll_disable; 4629 intel_encoder->pre_enable = intel_ddi_pre_enable; 4630 intel_encoder->disable = intel_disable_ddi; 4631 intel_encoder->post_disable = intel_ddi_post_disable; 4632 intel_encoder->update_pipe = intel_ddi_update_pipe; 4633 intel_encoder->get_hw_state = intel_ddi_get_hw_state; 4634 intel_encoder->get_config = intel_ddi_get_config; 4635 intel_encoder->suspend = intel_dp_encoder_suspend; 4636 intel_encoder->get_power_domains = intel_ddi_get_power_domains; 4637 intel_encoder->type = INTEL_OUTPUT_DDI; 4638 intel_encoder->power_domain = intel_port_to_power_domain(port); 4639 intel_encoder->port = port; 4640 intel_encoder->cloneable = 0; 4641 for_each_pipe(dev_priv, pipe) 4642 intel_encoder->crtc_mask |= BIT(pipe); 4643 4644 if (INTEL_GEN(dev_priv) >= 11) 4645 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & 4646 DDI_BUF_PORT_REVERSAL; 4647 else 4648 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & 4649 (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 4650 intel_dig_port->dp.output_reg = INVALID_MMIO_REG; 4651 intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port); 4652 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 4653 4654 if (intel_phy_is_tc(dev_priv, phy)) { 4655 bool is_legacy = !port_info->supports_typec_usb && 4656 !port_info->supports_tbt; 4657 4658 intel_tc_port_init(intel_dig_port, is_legacy); 4659 4660 intel_encoder->update_prepare = intel_ddi_update_prepare; 4661 intel_encoder->update_complete = intel_ddi_update_complete; 4662 } 4663 4664 switch (port) { 4665 case PORT_A: 4666 intel_dig_port->ddi_io_power_domain = 4667 POWER_DOMAIN_PORT_DDI_A_IO; 4668 break; 4669 case PORT_B: 4670 intel_dig_port->ddi_io_power_domain = 4671 POWER_DOMAIN_PORT_DDI_B_IO; 4672 break; 4673 case PORT_C: 4674 intel_dig_port->ddi_io_power_domain = 4675 POWER_DOMAIN_PORT_DDI_C_IO; 4676 break; 4677 case PORT_D: 4678 intel_dig_port->ddi_io_power_domain = 4679 POWER_DOMAIN_PORT_DDI_D_IO; 4680 break; 4681 case PORT_E: 4682 intel_dig_port->ddi_io_power_domain = 4683 POWER_DOMAIN_PORT_DDI_E_IO; 4684 break; 4685 case PORT_F: 4686 intel_dig_port->ddi_io_power_domain = 4687 POWER_DOMAIN_PORT_DDI_F_IO; 4688 break; 4689 case PORT_G: 4690 intel_dig_port->ddi_io_power_domain = 4691 POWER_DOMAIN_PORT_DDI_G_IO; 4692 break; 4693 case PORT_H: 4694 intel_dig_port->ddi_io_power_domain = 4695 POWER_DOMAIN_PORT_DDI_H_IO; 4696 break; 4697 case PORT_I: 4698 intel_dig_port->ddi_io_power_domain = 4699 POWER_DOMAIN_PORT_DDI_I_IO; 4700 break; 4701 default: 4702 MISSING_CASE(port); 4703 } 4704 4705 if (init_dp) { 4706 if (!intel_ddi_init_dp_connector(intel_dig_port)) 4707 goto err; 4708 4709 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; 4710 } 4711 4712 /* In theory we don't need the encoder->type check, but leave it just in 4713 * case we have some really bad VBTs... */ 4714 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 4715 if (!intel_ddi_init_hdmi_connector(intel_dig_port)) 4716 goto err; 4717 } 4718 4719 if (init_lspcon) { 4720 if (lspcon_init(intel_dig_port)) 4721 /* TODO: handle hdmi info frame part */ 4722 DRM_DEBUG_KMS("LSPCON init success on port %c\n", 4723 port_name(port)); 4724 else 4725 /* 4726 * LSPCON init faied, but DP init was success, so 4727 * lets try to drive as DP++ port. 4728 */ 4729 DRM_ERROR("LSPCON init failed on port %c\n", 4730 port_name(port)); 4731 } 4732 4733 intel_infoframe_init(intel_dig_port); 4734 4735 return; 4736 4737 err: 4738 drm_encoder_cleanup(encoder); 4739 kfree(intel_dig_port); 4740 } 4741