1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <drm/drm_scdc_helper.h> 29 30 #include "i915_drv.h" 31 #include "intel_audio.h" 32 #include "intel_combo_phy.h" 33 #include "intel_connector.h" 34 #include "intel_ddi.h" 35 #include "intel_display_types.h" 36 #include "intel_dp.h" 37 #include "intel_dp_link_training.h" 38 #include "intel_dpio_phy.h" 39 #include "intel_dsi.h" 40 #include "intel_fifo_underrun.h" 41 #include "intel_gmbus.h" 42 #include "intel_hdcp.h" 43 #include "intel_hdmi.h" 44 #include "intel_hotplug.h" 45 #include "intel_lspcon.h" 46 #include "intel_panel.h" 47 #include "intel_psr.h" 48 #include "intel_sprite.h" 49 #include "intel_tc.h" 50 #include "intel_vdsc.h" 51 52 struct ddi_buf_trans { 53 u32 trans1; /* balance leg enable, de-emph level */ 54 u32 trans2; /* vref sel, vswing */ 55 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */ 56 }; 57 58 static const u8 index_to_dp_signal_levels[] = { 59 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 60 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 61 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 62 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 63 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 64 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 65 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 66 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 67 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 68 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 69 }; 70 71 /* HDMI/DVI modes ignore everything but the last 2 items. So we share 72 * them for both DP and FDI transports, allowing those ports to 73 * automatically adapt to HDMI connections as well 74 */ 75 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { 76 { 0x00FFFFFF, 0x0006000E, 0x0 }, 77 { 0x00D75FFF, 0x0005000A, 0x0 }, 78 { 0x00C30FFF, 0x00040006, 0x0 }, 79 { 0x80AAAFFF, 0x000B0000, 0x0 }, 80 { 0x00FFFFFF, 0x0005000A, 0x0 }, 81 { 0x00D75FFF, 0x000C0004, 0x0 }, 82 { 0x80C30FFF, 0x000B0000, 0x0 }, 83 { 0x00FFFFFF, 0x00040006, 0x0 }, 84 { 0x80D75FFF, 0x000B0000, 0x0 }, 85 }; 86 87 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { 88 { 0x00FFFFFF, 0x0007000E, 0x0 }, 89 { 0x00D75FFF, 0x000F000A, 0x0 }, 90 { 0x00C30FFF, 0x00060006, 0x0 }, 91 { 0x00AAAFFF, 0x001E0000, 0x0 }, 92 { 0x00FFFFFF, 0x000F000A, 0x0 }, 93 { 0x00D75FFF, 0x00160004, 0x0 }, 94 { 0x00C30FFF, 0x001E0000, 0x0 }, 95 { 0x00FFFFFF, 0x00060006, 0x0 }, 96 { 0x00D75FFF, 0x001E0000, 0x0 }, 97 }; 98 99 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { 100 /* Idx NT mV d T mV d db */ 101 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */ 102 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */ 103 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */ 104 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */ 105 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */ 106 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */ 107 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */ 108 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */ 109 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */ 110 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */ 111 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */ 112 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */ 113 }; 114 115 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { 116 { 0x00FFFFFF, 0x00000012, 0x0 }, 117 { 0x00EBAFFF, 0x00020011, 0x0 }, 118 { 0x00C71FFF, 0x0006000F, 0x0 }, 119 { 0x00AAAFFF, 0x000E000A, 0x0 }, 120 { 0x00FFFFFF, 0x00020011, 0x0 }, 121 { 0x00DB6FFF, 0x0005000F, 0x0 }, 122 { 0x00BEEFFF, 0x000A000C, 0x0 }, 123 { 0x00FFFFFF, 0x0005000F, 0x0 }, 124 { 0x00DB6FFF, 0x000A000C, 0x0 }, 125 }; 126 127 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { 128 { 0x00FFFFFF, 0x0007000E, 0x0 }, 129 { 0x00D75FFF, 0x000E000A, 0x0 }, 130 { 0x00BEFFFF, 0x00140006, 0x0 }, 131 { 0x80B2CFFF, 0x001B0002, 0x0 }, 132 { 0x00FFFFFF, 0x000E000A, 0x0 }, 133 { 0x00DB6FFF, 0x00160005, 0x0 }, 134 { 0x80C71FFF, 0x001A0002, 0x0 }, 135 { 0x00F7DFFF, 0x00180004, 0x0 }, 136 { 0x80D75FFF, 0x001B0002, 0x0 }, 137 }; 138 139 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { 140 { 0x00FFFFFF, 0x0001000E, 0x0 }, 141 { 0x00D75FFF, 0x0004000A, 0x0 }, 142 { 0x00C30FFF, 0x00070006, 0x0 }, 143 { 0x00AAAFFF, 0x000C0000, 0x0 }, 144 { 0x00FFFFFF, 0x0004000A, 0x0 }, 145 { 0x00D75FFF, 0x00090004, 0x0 }, 146 { 0x00C30FFF, 0x000C0000, 0x0 }, 147 { 0x00FFFFFF, 0x00070006, 0x0 }, 148 { 0x00D75FFF, 0x000C0000, 0x0 }, 149 }; 150 151 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { 152 /* Idx NT mV d T mV df db */ 153 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */ 154 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */ 155 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */ 156 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */ 157 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */ 158 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */ 159 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */ 160 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */ 161 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */ 162 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */ 163 }; 164 165 /* Skylake H and S */ 166 static const struct ddi_buf_trans skl_ddi_translations_dp[] = { 167 { 0x00002016, 0x000000A0, 0x0 }, 168 { 0x00005012, 0x0000009B, 0x0 }, 169 { 0x00007011, 0x00000088, 0x0 }, 170 { 0x80009010, 0x000000C0, 0x1 }, 171 { 0x00002016, 0x0000009B, 0x0 }, 172 { 0x00005012, 0x00000088, 0x0 }, 173 { 0x80007011, 0x000000C0, 0x1 }, 174 { 0x00002016, 0x000000DF, 0x0 }, 175 { 0x80005012, 0x000000C0, 0x1 }, 176 }; 177 178 /* Skylake U */ 179 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { 180 { 0x0000201B, 0x000000A2, 0x0 }, 181 { 0x00005012, 0x00000088, 0x0 }, 182 { 0x80007011, 0x000000CD, 0x1 }, 183 { 0x80009010, 0x000000C0, 0x1 }, 184 { 0x0000201B, 0x0000009D, 0x0 }, 185 { 0x80005012, 0x000000C0, 0x1 }, 186 { 0x80007011, 0x000000C0, 0x1 }, 187 { 0x00002016, 0x00000088, 0x0 }, 188 { 0x80005012, 0x000000C0, 0x1 }, 189 }; 190 191 /* Skylake Y */ 192 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { 193 { 0x00000018, 0x000000A2, 0x0 }, 194 { 0x00005012, 0x00000088, 0x0 }, 195 { 0x80007011, 0x000000CD, 0x3 }, 196 { 0x80009010, 0x000000C0, 0x3 }, 197 { 0x00000018, 0x0000009D, 0x0 }, 198 { 0x80005012, 0x000000C0, 0x3 }, 199 { 0x80007011, 0x000000C0, 0x3 }, 200 { 0x00000018, 0x00000088, 0x0 }, 201 { 0x80005012, 0x000000C0, 0x3 }, 202 }; 203 204 /* Kabylake H and S */ 205 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = { 206 { 0x00002016, 0x000000A0, 0x0 }, 207 { 0x00005012, 0x0000009B, 0x0 }, 208 { 0x00007011, 0x00000088, 0x0 }, 209 { 0x80009010, 0x000000C0, 0x1 }, 210 { 0x00002016, 0x0000009B, 0x0 }, 211 { 0x00005012, 0x00000088, 0x0 }, 212 { 0x80007011, 0x000000C0, 0x1 }, 213 { 0x00002016, 0x00000097, 0x0 }, 214 { 0x80005012, 0x000000C0, 0x1 }, 215 }; 216 217 /* Kabylake U */ 218 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = { 219 { 0x0000201B, 0x000000A1, 0x0 }, 220 { 0x00005012, 0x00000088, 0x0 }, 221 { 0x80007011, 0x000000CD, 0x3 }, 222 { 0x80009010, 0x000000C0, 0x3 }, 223 { 0x0000201B, 0x0000009D, 0x0 }, 224 { 0x80005012, 0x000000C0, 0x3 }, 225 { 0x80007011, 0x000000C0, 0x3 }, 226 { 0x00002016, 0x0000004F, 0x0 }, 227 { 0x80005012, 0x000000C0, 0x3 }, 228 }; 229 230 /* Kabylake Y */ 231 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = { 232 { 0x00001017, 0x000000A1, 0x0 }, 233 { 0x00005012, 0x00000088, 0x0 }, 234 { 0x80007011, 0x000000CD, 0x3 }, 235 { 0x8000800F, 0x000000C0, 0x3 }, 236 { 0x00001017, 0x0000009D, 0x0 }, 237 { 0x80005012, 0x000000C0, 0x3 }, 238 { 0x80007011, 0x000000C0, 0x3 }, 239 { 0x00001017, 0x0000004C, 0x0 }, 240 { 0x80005012, 0x000000C0, 0x3 }, 241 }; 242 243 /* 244 * Skylake/Kabylake H and S 245 * eDP 1.4 low vswing translation parameters 246 */ 247 static const struct ddi_buf_trans skl_ddi_translations_edp[] = { 248 { 0x00000018, 0x000000A8, 0x0 }, 249 { 0x00004013, 0x000000A9, 0x0 }, 250 { 0x00007011, 0x000000A2, 0x0 }, 251 { 0x00009010, 0x0000009C, 0x0 }, 252 { 0x00000018, 0x000000A9, 0x0 }, 253 { 0x00006013, 0x000000A2, 0x0 }, 254 { 0x00007011, 0x000000A6, 0x0 }, 255 { 0x00000018, 0x000000AB, 0x0 }, 256 { 0x00007013, 0x0000009F, 0x0 }, 257 { 0x00000018, 0x000000DF, 0x0 }, 258 }; 259 260 /* 261 * Skylake/Kabylake U 262 * eDP 1.4 low vswing translation parameters 263 */ 264 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = { 265 { 0x00000018, 0x000000A8, 0x0 }, 266 { 0x00004013, 0x000000A9, 0x0 }, 267 { 0x00007011, 0x000000A2, 0x0 }, 268 { 0x00009010, 0x0000009C, 0x0 }, 269 { 0x00000018, 0x000000A9, 0x0 }, 270 { 0x00006013, 0x000000A2, 0x0 }, 271 { 0x00007011, 0x000000A6, 0x0 }, 272 { 0x00002016, 0x000000AB, 0x0 }, 273 { 0x00005013, 0x0000009F, 0x0 }, 274 { 0x00000018, 0x000000DF, 0x0 }, 275 }; 276 277 /* 278 * Skylake/Kabylake Y 279 * eDP 1.4 low vswing translation parameters 280 */ 281 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = { 282 { 0x00000018, 0x000000A8, 0x0 }, 283 { 0x00004013, 0x000000AB, 0x0 }, 284 { 0x00007011, 0x000000A4, 0x0 }, 285 { 0x00009010, 0x000000DF, 0x0 }, 286 { 0x00000018, 0x000000AA, 0x0 }, 287 { 0x00006013, 0x000000A4, 0x0 }, 288 { 0x00007011, 0x0000009D, 0x0 }, 289 { 0x00000018, 0x000000A0, 0x0 }, 290 { 0x00006012, 0x000000DF, 0x0 }, 291 { 0x00000018, 0x0000008A, 0x0 }, 292 }; 293 294 /* Skylake/Kabylake U, H and S */ 295 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { 296 { 0x00000018, 0x000000AC, 0x0 }, 297 { 0x00005012, 0x0000009D, 0x0 }, 298 { 0x00007011, 0x00000088, 0x0 }, 299 { 0x00000018, 0x000000A1, 0x0 }, 300 { 0x00000018, 0x00000098, 0x0 }, 301 { 0x00004013, 0x00000088, 0x0 }, 302 { 0x80006012, 0x000000CD, 0x1 }, 303 { 0x00000018, 0x000000DF, 0x0 }, 304 { 0x80003015, 0x000000CD, 0x1 }, /* Default */ 305 { 0x80003015, 0x000000C0, 0x1 }, 306 { 0x80000018, 0x000000C0, 0x1 }, 307 }; 308 309 /* Skylake/Kabylake Y */ 310 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { 311 { 0x00000018, 0x000000A1, 0x0 }, 312 { 0x00005012, 0x000000DF, 0x0 }, 313 { 0x80007011, 0x000000CB, 0x3 }, 314 { 0x00000018, 0x000000A4, 0x0 }, 315 { 0x00000018, 0x0000009D, 0x0 }, 316 { 0x00004013, 0x00000080, 0x0 }, 317 { 0x80006013, 0x000000C0, 0x3 }, 318 { 0x00000018, 0x0000008A, 0x0 }, 319 { 0x80003015, 0x000000C0, 0x3 }, /* Default */ 320 { 0x80003015, 0x000000C0, 0x3 }, 321 { 0x80000018, 0x000000C0, 0x3 }, 322 }; 323 324 struct bxt_ddi_buf_trans { 325 u8 margin; /* swing value */ 326 u8 scale; /* scale value */ 327 u8 enable; /* scale enable */ 328 u8 deemphasis; 329 }; 330 331 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { 332 /* Idx NT mV diff db */ 333 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ 334 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */ 335 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */ 336 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */ 337 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */ 338 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */ 339 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */ 340 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */ 341 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */ 342 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */ 343 }; 344 345 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = { 346 /* Idx NT mV diff db */ 347 { 26, 0, 0, 128, }, /* 0: 200 0 */ 348 { 38, 0, 0, 112, }, /* 1: 200 1.5 */ 349 { 48, 0, 0, 96, }, /* 2: 200 4 */ 350 { 54, 0, 0, 69, }, /* 3: 200 6 */ 351 { 32, 0, 0, 128, }, /* 4: 250 0 */ 352 { 48, 0, 0, 104, }, /* 5: 250 1.5 */ 353 { 54, 0, 0, 85, }, /* 6: 250 4 */ 354 { 43, 0, 0, 128, }, /* 7: 300 0 */ 355 { 54, 0, 0, 101, }, /* 8: 300 1.5 */ 356 { 48, 0, 0, 128, }, /* 9: 300 0 */ 357 }; 358 359 /* BSpec has 2 recommended values - entries 0 and 8. 360 * Using the entry with higher vswing. 361 */ 362 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = { 363 /* Idx NT mV diff db */ 364 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ 365 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */ 366 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */ 367 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */ 368 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */ 369 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */ 370 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */ 371 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */ 372 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */ 373 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */ 374 }; 375 376 struct cnl_ddi_buf_trans { 377 u8 dw2_swing_sel; 378 u8 dw7_n_scalar; 379 u8 dw4_cursor_coeff; 380 u8 dw4_post_cursor_2; 381 u8 dw4_post_cursor_1; 382 }; 383 384 /* Voltage Swing Programming for VccIO 0.85V for DP */ 385 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = { 386 /* NT mV Trans mV db */ 387 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 388 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ 389 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ 390 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ 391 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 392 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 393 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 394 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ 395 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ 396 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 397 }; 398 399 /* Voltage Swing Programming for VccIO 0.85V for HDMI */ 400 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = { 401 /* NT mV Trans mV db */ 402 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 403 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ 404 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ 405 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */ 406 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ 407 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ 408 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 409 }; 410 411 /* Voltage Swing Programming for VccIO 0.85V for eDP */ 412 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = { 413 /* NT mV Trans mV db */ 414 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 415 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 416 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 417 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 418 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 419 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 420 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */ 421 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */ 422 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 423 }; 424 425 /* Voltage Swing Programming for VccIO 0.95V for DP */ 426 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = { 427 /* NT mV Trans mV db */ 428 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 429 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ 430 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ 431 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ 432 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 433 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 434 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 435 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ 436 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ 437 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 438 }; 439 440 /* Voltage Swing Programming for VccIO 0.95V for HDMI */ 441 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = { 442 /* NT mV Trans mV db */ 443 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 444 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 445 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 446 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 447 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 448 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 449 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ 450 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ 451 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ 452 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ 453 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 454 }; 455 456 /* Voltage Swing Programming for VccIO 0.95V for eDP */ 457 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = { 458 /* NT mV Trans mV db */ 459 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 460 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 461 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 462 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 463 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 464 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 465 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ 466 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ 467 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */ 468 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 469 }; 470 471 /* Voltage Swing Programming for VccIO 1.05V for DP */ 472 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = { 473 /* NT mV Trans mV db */ 474 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 475 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 476 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 477 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */ 478 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 479 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 480 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */ 481 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */ 482 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */ 483 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 484 }; 485 486 /* Voltage Swing Programming for VccIO 1.05V for HDMI */ 487 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = { 488 /* NT mV Trans mV db */ 489 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 490 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 491 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 492 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 493 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 494 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 495 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ 496 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ 497 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ 498 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ 499 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 500 }; 501 502 /* Voltage Swing Programming for VccIO 1.05V for eDP */ 503 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = { 504 /* NT mV Trans mV db */ 505 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 506 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 507 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 508 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 509 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 510 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 511 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ 512 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ 513 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 514 }; 515 516 /* icl_combo_phy_ddi_translations */ 517 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = { 518 /* NT mV Trans mV db */ 519 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 520 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 521 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 522 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 523 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 524 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 525 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 526 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 527 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 528 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 529 }; 530 531 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = { 532 /* NT mV Trans mV db */ 533 { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ 534 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */ 535 { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */ 536 { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */ 537 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ 538 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */ 539 { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */ 540 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ 541 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ 542 { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 543 }; 544 545 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = { 546 /* NT mV Trans mV db */ 547 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 548 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 549 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 550 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 551 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 552 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 553 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 554 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 555 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 556 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 557 }; 558 559 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = { 560 /* NT mV Trans mV db */ 561 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 562 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ 563 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ 564 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */ 565 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ 566 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ 567 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 568 }; 569 570 struct icl_mg_phy_ddi_buf_trans { 571 u32 cri_txdeemph_override_5_0; 572 u32 cri_txdeemph_override_11_6; 573 u32 cri_txdeemph_override_17_12; 574 }; 575 576 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = { 577 /* Voltage swing pre-emphasis */ 578 { 0x0, 0x1B, 0x00 }, /* 0 0 */ 579 { 0x0, 0x23, 0x08 }, /* 0 1 */ 580 { 0x0, 0x2D, 0x12 }, /* 0 2 */ 581 { 0x0, 0x00, 0x00 }, /* 0 3 */ 582 { 0x0, 0x23, 0x00 }, /* 1 0 */ 583 { 0x0, 0x2B, 0x09 }, /* 1 1 */ 584 { 0x0, 0x2E, 0x11 }, /* 1 2 */ 585 { 0x0, 0x2F, 0x00 }, /* 2 0 */ 586 { 0x0, 0x33, 0x0C }, /* 2 1 */ 587 { 0x0, 0x00, 0x00 }, /* 3 0 */ 588 }; 589 590 struct tgl_dkl_phy_ddi_buf_trans { 591 u32 dkl_vswing_control; 592 u32 dkl_preshoot_control; 593 u32 dkl_de_emphasis_control; 594 }; 595 596 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans[] = { 597 /* VS pre-emp Non-trans mV Pre-emph dB */ 598 { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */ 599 { 0x5, 0x0, 0x03 }, /* 0 1 400mV 3.5 dB */ 600 { 0x2, 0x0, 0x0b }, /* 0 2 400mV 6 dB */ 601 { 0x0, 0x0, 0x19 }, /* 0 3 400mV 9.5 dB */ 602 { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */ 603 { 0x2, 0x0, 0x03 }, /* 1 1 600mV 3.5 dB */ 604 { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */ 605 { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */ 606 { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */ 607 { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */ 608 }; 609 610 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_hdmi_ddi_trans[] = { 611 /* HDMI Preset VS Pre-emph */ 612 { 0x7, 0x0, 0x0 }, /* 1 400mV 0dB */ 613 { 0x6, 0x0, 0x0 }, /* 2 500mV 0dB */ 614 { 0x4, 0x0, 0x0 }, /* 3 650mV 0dB */ 615 { 0x2, 0x0, 0x0 }, /* 4 800mV 0dB */ 616 { 0x0, 0x0, 0x0 }, /* 5 1000mV 0dB */ 617 { 0x0, 0x0, 0x5 }, /* 6 Full -1.5 dB */ 618 { 0x0, 0x0, 0x6 }, /* 7 Full -1.8 dB */ 619 { 0x0, 0x0, 0x7 }, /* 8 Full -2 dB */ 620 { 0x0, 0x0, 0x8 }, /* 9 Full -2.5 dB */ 621 { 0x0, 0x0, 0xA }, /* 10 Full -3 dB */ 622 }; 623 624 static const struct ddi_buf_trans * 625 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 626 { 627 if (dev_priv->vbt.edp.low_vswing) { 628 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp); 629 return bdw_ddi_translations_edp; 630 } else { 631 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 632 return bdw_ddi_translations_dp; 633 } 634 } 635 636 static const struct ddi_buf_trans * 637 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 638 { 639 if (IS_SKL_ULX(dev_priv)) { 640 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); 641 return skl_y_ddi_translations_dp; 642 } else if (IS_SKL_ULT(dev_priv)) { 643 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); 644 return skl_u_ddi_translations_dp; 645 } else { 646 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); 647 return skl_ddi_translations_dp; 648 } 649 } 650 651 static const struct ddi_buf_trans * 652 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 653 { 654 if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv)) { 655 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp); 656 return kbl_y_ddi_translations_dp; 657 } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) { 658 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp); 659 return kbl_u_ddi_translations_dp; 660 } else { 661 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp); 662 return kbl_ddi_translations_dp; 663 } 664 } 665 666 static const struct ddi_buf_trans * 667 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 668 { 669 if (dev_priv->vbt.edp.low_vswing) { 670 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || 671 IS_CFL_ULX(dev_priv)) { 672 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); 673 return skl_y_ddi_translations_edp; 674 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) || 675 IS_CFL_ULT(dev_priv)) { 676 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); 677 return skl_u_ddi_translations_edp; 678 } else { 679 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp); 680 return skl_ddi_translations_edp; 681 } 682 } 683 684 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) 685 return kbl_get_buf_trans_dp(dev_priv, n_entries); 686 else 687 return skl_get_buf_trans_dp(dev_priv, n_entries); 688 } 689 690 static const struct ddi_buf_trans * 691 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) 692 { 693 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || 694 IS_CFL_ULX(dev_priv)) { 695 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); 696 return skl_y_ddi_translations_hdmi; 697 } else { 698 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); 699 return skl_ddi_translations_hdmi; 700 } 701 } 702 703 static int skl_buf_trans_num_entries(enum port port, int n_entries) 704 { 705 /* Only DDIA and DDIE can select the 10th register with DP */ 706 if (port == PORT_A || port == PORT_E) 707 return min(n_entries, 10); 708 else 709 return min(n_entries, 9); 710 } 711 712 static const struct ddi_buf_trans * 713 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv, 714 enum port port, int *n_entries) 715 { 716 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) { 717 const struct ddi_buf_trans *ddi_translations = 718 kbl_get_buf_trans_dp(dev_priv, n_entries); 719 *n_entries = skl_buf_trans_num_entries(port, *n_entries); 720 return ddi_translations; 721 } else if (IS_SKYLAKE(dev_priv)) { 722 const struct ddi_buf_trans *ddi_translations = 723 skl_get_buf_trans_dp(dev_priv, n_entries); 724 *n_entries = skl_buf_trans_num_entries(port, *n_entries); 725 return ddi_translations; 726 } else if (IS_BROADWELL(dev_priv)) { 727 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 728 return bdw_ddi_translations_dp; 729 } else if (IS_HASWELL(dev_priv)) { 730 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 731 return hsw_ddi_translations_dp; 732 } 733 734 *n_entries = 0; 735 return NULL; 736 } 737 738 static const struct ddi_buf_trans * 739 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv, 740 enum port port, int *n_entries) 741 { 742 if (IS_GEN9_BC(dev_priv)) { 743 const struct ddi_buf_trans *ddi_translations = 744 skl_get_buf_trans_edp(dev_priv, n_entries); 745 *n_entries = skl_buf_trans_num_entries(port, *n_entries); 746 return ddi_translations; 747 } else if (IS_BROADWELL(dev_priv)) { 748 return bdw_get_buf_trans_edp(dev_priv, n_entries); 749 } else if (IS_HASWELL(dev_priv)) { 750 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 751 return hsw_ddi_translations_dp; 752 } 753 754 *n_entries = 0; 755 return NULL; 756 } 757 758 static const struct ddi_buf_trans * 759 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, 760 int *n_entries) 761 { 762 if (IS_BROADWELL(dev_priv)) { 763 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi); 764 return bdw_ddi_translations_fdi; 765 } else if (IS_HASWELL(dev_priv)) { 766 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi); 767 return hsw_ddi_translations_fdi; 768 } 769 770 *n_entries = 0; 771 return NULL; 772 } 773 774 static const struct ddi_buf_trans * 775 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, 776 int *n_entries) 777 { 778 if (IS_GEN9_BC(dev_priv)) { 779 return skl_get_buf_trans_hdmi(dev_priv, n_entries); 780 } else if (IS_BROADWELL(dev_priv)) { 781 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 782 return bdw_ddi_translations_hdmi; 783 } else if (IS_HASWELL(dev_priv)) { 784 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); 785 return hsw_ddi_translations_hdmi; 786 } 787 788 *n_entries = 0; 789 return NULL; 790 } 791 792 static const struct bxt_ddi_buf_trans * 793 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 794 { 795 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); 796 return bxt_ddi_translations_dp; 797 } 798 799 static const struct bxt_ddi_buf_trans * 800 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 801 { 802 if (dev_priv->vbt.edp.low_vswing) { 803 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp); 804 return bxt_ddi_translations_edp; 805 } 806 807 return bxt_get_buf_trans_dp(dev_priv, n_entries); 808 } 809 810 static const struct bxt_ddi_buf_trans * 811 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) 812 { 813 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); 814 return bxt_ddi_translations_hdmi; 815 } 816 817 static const struct cnl_ddi_buf_trans * 818 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) 819 { 820 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 821 822 if (voltage == VOLTAGE_INFO_0_85V) { 823 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V); 824 return cnl_ddi_translations_hdmi_0_85V; 825 } else if (voltage == VOLTAGE_INFO_0_95V) { 826 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V); 827 return cnl_ddi_translations_hdmi_0_95V; 828 } else if (voltage == VOLTAGE_INFO_1_05V) { 829 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V); 830 return cnl_ddi_translations_hdmi_1_05V; 831 } else { 832 *n_entries = 1; /* shut up gcc */ 833 MISSING_CASE(voltage); 834 } 835 return NULL; 836 } 837 838 static const struct cnl_ddi_buf_trans * 839 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 840 { 841 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 842 843 if (voltage == VOLTAGE_INFO_0_85V) { 844 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V); 845 return cnl_ddi_translations_dp_0_85V; 846 } else if (voltage == VOLTAGE_INFO_0_95V) { 847 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V); 848 return cnl_ddi_translations_dp_0_95V; 849 } else if (voltage == VOLTAGE_INFO_1_05V) { 850 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V); 851 return cnl_ddi_translations_dp_1_05V; 852 } else { 853 *n_entries = 1; /* shut up gcc */ 854 MISSING_CASE(voltage); 855 } 856 return NULL; 857 } 858 859 static const struct cnl_ddi_buf_trans * 860 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 861 { 862 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 863 864 if (dev_priv->vbt.edp.low_vswing) { 865 if (voltage == VOLTAGE_INFO_0_85V) { 866 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V); 867 return cnl_ddi_translations_edp_0_85V; 868 } else if (voltage == VOLTAGE_INFO_0_95V) { 869 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V); 870 return cnl_ddi_translations_edp_0_95V; 871 } else if (voltage == VOLTAGE_INFO_1_05V) { 872 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V); 873 return cnl_ddi_translations_edp_1_05V; 874 } else { 875 *n_entries = 1; /* shut up gcc */ 876 MISSING_CASE(voltage); 877 } 878 return NULL; 879 } else { 880 return cnl_get_buf_trans_dp(dev_priv, n_entries); 881 } 882 } 883 884 static const struct cnl_ddi_buf_trans * 885 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, 886 int *n_entries) 887 { 888 if (type == INTEL_OUTPUT_HDMI) { 889 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); 890 return icl_combo_phy_ddi_translations_hdmi; 891 } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) { 892 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3); 893 return icl_combo_phy_ddi_translations_edp_hbr3; 894 } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) { 895 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2); 896 return icl_combo_phy_ddi_translations_edp_hbr2; 897 } 898 899 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2); 900 return icl_combo_phy_ddi_translations_dp_hbr2; 901 } 902 903 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port) 904 { 905 struct ddi_vbt_port_info *port_info = &dev_priv->vbt.ddi_port_info[port]; 906 int n_entries, level, default_entry; 907 enum phy phy = intel_port_to_phy(dev_priv, port); 908 909 if (INTEL_GEN(dev_priv) >= 12) { 910 if (intel_phy_is_combo(dev_priv, phy)) 911 icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 912 0, &n_entries); 913 else 914 n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans); 915 default_entry = n_entries - 1; 916 } else if (INTEL_GEN(dev_priv) == 11) { 917 if (intel_phy_is_combo(dev_priv, phy)) 918 icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 919 0, &n_entries); 920 else 921 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations); 922 default_entry = n_entries - 1; 923 } else if (IS_CANNONLAKE(dev_priv)) { 924 cnl_get_buf_trans_hdmi(dev_priv, &n_entries); 925 default_entry = n_entries - 1; 926 } else if (IS_GEN9_LP(dev_priv)) { 927 bxt_get_buf_trans_hdmi(dev_priv, &n_entries); 928 default_entry = n_entries - 1; 929 } else if (IS_GEN9_BC(dev_priv)) { 930 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 931 default_entry = 8; 932 } else if (IS_BROADWELL(dev_priv)) { 933 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 934 default_entry = 7; 935 } else if (IS_HASWELL(dev_priv)) { 936 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 937 default_entry = 6; 938 } else { 939 WARN(1, "ddi translation table missing\n"); 940 return 0; 941 } 942 943 if (WARN_ON_ONCE(n_entries == 0)) 944 return 0; 945 946 if (port_info->hdmi_level_shift_set) 947 level = port_info->hdmi_level_shift; 948 else 949 level = default_entry; 950 951 if (WARN_ON_ONCE(level >= n_entries)) 952 level = n_entries - 1; 953 954 return level; 955 } 956 957 /* 958 * Starting with Haswell, DDI port buffers must be programmed with correct 959 * values in advance. This function programs the correct values for 960 * DP/eDP/FDI use cases. 961 */ 962 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 963 const struct intel_crtc_state *crtc_state) 964 { 965 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 966 u32 iboost_bit = 0; 967 int i, n_entries; 968 enum port port = encoder->port; 969 const struct ddi_buf_trans *ddi_translations; 970 971 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) 972 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv, 973 &n_entries); 974 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 975 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, 976 &n_entries); 977 else 978 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, 979 &n_entries); 980 981 /* If we're boosting the current, set bit 31 of trans1 */ 982 if (IS_GEN9_BC(dev_priv) && 983 dev_priv->vbt.ddi_port_info[port].dp_boost_level) 984 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 985 986 for (i = 0; i < n_entries; i++) { 987 I915_WRITE(DDI_BUF_TRANS_LO(port, i), 988 ddi_translations[i].trans1 | iboost_bit); 989 I915_WRITE(DDI_BUF_TRANS_HI(port, i), 990 ddi_translations[i].trans2); 991 } 992 } 993 994 /* 995 * Starting with Haswell, DDI port buffers must be programmed with correct 996 * values in advance. This function programs the correct values for 997 * HDMI/DVI use cases. 998 */ 999 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 1000 int level) 1001 { 1002 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1003 u32 iboost_bit = 0; 1004 int n_entries; 1005 enum port port = encoder->port; 1006 const struct ddi_buf_trans *ddi_translations; 1007 1008 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 1009 1010 if (WARN_ON_ONCE(!ddi_translations)) 1011 return; 1012 if (WARN_ON_ONCE(level >= n_entries)) 1013 level = n_entries - 1; 1014 1015 /* If we're boosting the current, set bit 31 of trans1 */ 1016 if (IS_GEN9_BC(dev_priv) && 1017 dev_priv->vbt.ddi_port_info[port].hdmi_boost_level) 1018 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 1019 1020 /* Entry 9 is for HDMI: */ 1021 I915_WRITE(DDI_BUF_TRANS_LO(port, 9), 1022 ddi_translations[level].trans1 | iboost_bit); 1023 I915_WRITE(DDI_BUF_TRANS_HI(port, 9), 1024 ddi_translations[level].trans2); 1025 } 1026 1027 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 1028 enum port port) 1029 { 1030 i915_reg_t reg = DDI_BUF_CTL(port); 1031 int i; 1032 1033 for (i = 0; i < 16; i++) { 1034 udelay(1); 1035 if (I915_READ(reg) & DDI_BUF_IS_IDLE) 1036 return; 1037 } 1038 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); 1039 } 1040 1041 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 1042 { 1043 switch (pll->info->id) { 1044 case DPLL_ID_WRPLL1: 1045 return PORT_CLK_SEL_WRPLL1; 1046 case DPLL_ID_WRPLL2: 1047 return PORT_CLK_SEL_WRPLL2; 1048 case DPLL_ID_SPLL: 1049 return PORT_CLK_SEL_SPLL; 1050 case DPLL_ID_LCPLL_810: 1051 return PORT_CLK_SEL_LCPLL_810; 1052 case DPLL_ID_LCPLL_1350: 1053 return PORT_CLK_SEL_LCPLL_1350; 1054 case DPLL_ID_LCPLL_2700: 1055 return PORT_CLK_SEL_LCPLL_2700; 1056 default: 1057 MISSING_CASE(pll->info->id); 1058 return PORT_CLK_SEL_NONE; 1059 } 1060 } 1061 1062 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 1063 const struct intel_crtc_state *crtc_state) 1064 { 1065 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1066 int clock = crtc_state->port_clock; 1067 const enum intel_dpll_id id = pll->info->id; 1068 1069 switch (id) { 1070 default: 1071 /* 1072 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 1073 * here, so do warn if this get passed in 1074 */ 1075 MISSING_CASE(id); 1076 return DDI_CLK_SEL_NONE; 1077 case DPLL_ID_ICL_TBTPLL: 1078 switch (clock) { 1079 case 162000: 1080 return DDI_CLK_SEL_TBT_162; 1081 case 270000: 1082 return DDI_CLK_SEL_TBT_270; 1083 case 540000: 1084 return DDI_CLK_SEL_TBT_540; 1085 case 810000: 1086 return DDI_CLK_SEL_TBT_810; 1087 default: 1088 MISSING_CASE(clock); 1089 return DDI_CLK_SEL_NONE; 1090 } 1091 case DPLL_ID_ICL_MGPLL1: 1092 case DPLL_ID_ICL_MGPLL2: 1093 case DPLL_ID_ICL_MGPLL3: 1094 case DPLL_ID_ICL_MGPLL4: 1095 case DPLL_ID_TGL_MGPLL5: 1096 case DPLL_ID_TGL_MGPLL6: 1097 return DDI_CLK_SEL_MG; 1098 } 1099 } 1100 1101 /* Starting with Haswell, different DDI ports can work in FDI mode for 1102 * connection to the PCH-located connectors. For this, it is necessary to train 1103 * both the DDI port and PCH receiver for the desired DDI buffer settings. 1104 * 1105 * The recommended port to work in FDI mode is DDI E, which we use here. Also, 1106 * please note that when FDI mode is active on DDI E, it shares 2 lines with 1107 * DDI A (which is used for eDP) 1108 */ 1109 1110 void hsw_fdi_link_train(struct intel_encoder *encoder, 1111 const struct intel_crtc_state *crtc_state) 1112 { 1113 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1114 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1115 u32 temp, i, rx_ctl_val, ddi_pll_sel; 1116 1117 intel_prepare_dp_ddi_buffers(encoder, crtc_state); 1118 1119 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the 1120 * mode set "sequence for CRT port" document: 1121 * - TP1 to TP2 time with the default value 1122 * - FDI delay to 90h 1123 * 1124 * WaFDIAutoLinkSetTimingOverrride:hsw 1125 */ 1126 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) | 1127 FDI_RX_PWRDN_LANE0_VAL(2) | 1128 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 1129 1130 /* Enable the PCH Receiver FDI PLL */ 1131 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | 1132 FDI_RX_PLL_ENABLE | 1133 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); 1134 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 1135 POSTING_READ(FDI_RX_CTL(PIPE_A)); 1136 udelay(220); 1137 1138 /* Switch from Rawclk to PCDclk */ 1139 rx_ctl_val |= FDI_PCDCLK; 1140 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 1141 1142 /* Configure Port Clock Select */ 1143 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll); 1144 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel); 1145 WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL); 1146 1147 /* Start the training iterating through available voltages and emphasis, 1148 * testing each value twice. */ 1149 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { 1150 /* Configure DP_TP_CTL with auto-training */ 1151 I915_WRITE(DP_TP_CTL(PORT_E), 1152 DP_TP_CTL_FDI_AUTOTRAIN | 1153 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 1154 DP_TP_CTL_LINK_TRAIN_PAT1 | 1155 DP_TP_CTL_ENABLE); 1156 1157 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. 1158 * DDI E does not support port reversal, the functionality is 1159 * achieved on the PCH side in FDI_RX_CTL, so no need to set the 1160 * port reversal bit */ 1161 I915_WRITE(DDI_BUF_CTL(PORT_E), 1162 DDI_BUF_CTL_ENABLE | 1163 ((crtc_state->fdi_lanes - 1) << 1) | 1164 DDI_BUF_TRANS_SELECT(i / 2)); 1165 POSTING_READ(DDI_BUF_CTL(PORT_E)); 1166 1167 udelay(600); 1168 1169 /* Program PCH FDI Receiver TU */ 1170 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); 1171 1172 /* Enable PCH FDI Receiver with auto-training */ 1173 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; 1174 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 1175 POSTING_READ(FDI_RX_CTL(PIPE_A)); 1176 1177 /* Wait for FDI receiver lane calibration */ 1178 udelay(30); 1179 1180 /* Unset FDI_RX_MISC pwrdn lanes */ 1181 temp = I915_READ(FDI_RX_MISC(PIPE_A)); 1182 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 1183 I915_WRITE(FDI_RX_MISC(PIPE_A), temp); 1184 POSTING_READ(FDI_RX_MISC(PIPE_A)); 1185 1186 /* Wait for FDI auto training time */ 1187 udelay(5); 1188 1189 temp = I915_READ(DP_TP_STATUS(PORT_E)); 1190 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { 1191 DRM_DEBUG_KMS("FDI link training done on step %d\n", i); 1192 break; 1193 } 1194 1195 /* 1196 * Leave things enabled even if we failed to train FDI. 1197 * Results in less fireworks from the state checker. 1198 */ 1199 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) { 1200 DRM_ERROR("FDI link training failed!\n"); 1201 break; 1202 } 1203 1204 rx_ctl_val &= ~FDI_RX_ENABLE; 1205 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 1206 POSTING_READ(FDI_RX_CTL(PIPE_A)); 1207 1208 temp = I915_READ(DDI_BUF_CTL(PORT_E)); 1209 temp &= ~DDI_BUF_CTL_ENABLE; 1210 I915_WRITE(DDI_BUF_CTL(PORT_E), temp); 1211 POSTING_READ(DDI_BUF_CTL(PORT_E)); 1212 1213 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ 1214 temp = I915_READ(DP_TP_CTL(PORT_E)); 1215 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 1216 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 1217 I915_WRITE(DP_TP_CTL(PORT_E), temp); 1218 POSTING_READ(DP_TP_CTL(PORT_E)); 1219 1220 intel_wait_ddi_buf_idle(dev_priv, PORT_E); 1221 1222 /* Reset FDI_RX_MISC pwrdn lanes */ 1223 temp = I915_READ(FDI_RX_MISC(PIPE_A)); 1224 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 1225 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 1226 I915_WRITE(FDI_RX_MISC(PIPE_A), temp); 1227 POSTING_READ(FDI_RX_MISC(PIPE_A)); 1228 } 1229 1230 /* Enable normal pixel sending for FDI */ 1231 I915_WRITE(DP_TP_CTL(PORT_E), 1232 DP_TP_CTL_FDI_AUTOTRAIN | 1233 DP_TP_CTL_LINK_TRAIN_NORMAL | 1234 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 1235 DP_TP_CTL_ENABLE); 1236 } 1237 1238 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) 1239 { 1240 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1241 struct intel_digital_port *intel_dig_port = 1242 enc_to_dig_port(&encoder->base); 1243 1244 intel_dp->DP = intel_dig_port->saved_port_bits | 1245 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); 1246 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); 1247 } 1248 1249 static struct intel_encoder * 1250 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc) 1251 { 1252 struct drm_device *dev = crtc->base.dev; 1253 struct intel_encoder *encoder, *ret = NULL; 1254 int num_encoders = 0; 1255 1256 for_each_encoder_on_crtc(dev, &crtc->base, encoder) { 1257 ret = encoder; 1258 num_encoders++; 1259 } 1260 1261 if (num_encoders != 1) 1262 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, 1263 pipe_name(crtc->pipe)); 1264 1265 BUG_ON(ret == NULL); 1266 return ret; 1267 } 1268 1269 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, 1270 i915_reg_t reg) 1271 { 1272 int refclk; 1273 int n, p, r; 1274 u32 wrpll; 1275 1276 wrpll = I915_READ(reg); 1277 switch (wrpll & WRPLL_REF_MASK) { 1278 case WRPLL_REF_SPECIAL_HSW: 1279 /* 1280 * muxed-SSC for BDW. 1281 * non-SSC for non-ULT HSW. Check FUSE_STRAP3 1282 * for the non-SSC reference frequency. 1283 */ 1284 if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) { 1285 if (I915_READ(FUSE_STRAP3) & HSW_REF_CLK_SELECT) 1286 refclk = 24; 1287 else 1288 refclk = 135; 1289 break; 1290 } 1291 /* fall through */ 1292 case WRPLL_REF_PCH_SSC: 1293 /* 1294 * We could calculate spread here, but our checking 1295 * code only cares about 5% accuracy, and spread is a max of 1296 * 0.5% downspread. 1297 */ 1298 refclk = 135; 1299 break; 1300 case WRPLL_REF_LCPLL: 1301 refclk = 2700; 1302 break; 1303 default: 1304 MISSING_CASE(wrpll); 1305 return 0; 1306 } 1307 1308 r = wrpll & WRPLL_DIVIDER_REF_MASK; 1309 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; 1310 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; 1311 1312 /* Convert to KHz, p & r have a fixed point portion */ 1313 return (refclk * n * 100) / (p * r); 1314 } 1315 1316 static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state) 1317 { 1318 u32 p0, p1, p2, dco_freq; 1319 1320 p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK; 1321 p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK; 1322 1323 if (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_MODE(1)) 1324 p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; 1325 else 1326 p1 = 1; 1327 1328 1329 switch (p0) { 1330 case DPLL_CFGCR2_PDIV_1: 1331 p0 = 1; 1332 break; 1333 case DPLL_CFGCR2_PDIV_2: 1334 p0 = 2; 1335 break; 1336 case DPLL_CFGCR2_PDIV_3: 1337 p0 = 3; 1338 break; 1339 case DPLL_CFGCR2_PDIV_7: 1340 p0 = 7; 1341 break; 1342 } 1343 1344 switch (p2) { 1345 case DPLL_CFGCR2_KDIV_5: 1346 p2 = 5; 1347 break; 1348 case DPLL_CFGCR2_KDIV_2: 1349 p2 = 2; 1350 break; 1351 case DPLL_CFGCR2_KDIV_3: 1352 p2 = 3; 1353 break; 1354 case DPLL_CFGCR2_KDIV_1: 1355 p2 = 1; 1356 break; 1357 } 1358 1359 dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK) 1360 * 24 * 1000; 1361 1362 dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) 1363 * 24 * 1000) / 0x8000; 1364 1365 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0)) 1366 return 0; 1367 1368 return dco_freq / (p0 * p1 * p2 * 5); 1369 } 1370 1371 int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv, 1372 struct intel_dpll_hw_state *pll_state) 1373 { 1374 u32 p0, p1, p2, dco_freq, ref_clock; 1375 1376 p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK; 1377 p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK; 1378 1379 if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1)) 1380 p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >> 1381 DPLL_CFGCR1_QDIV_RATIO_SHIFT; 1382 else 1383 p1 = 1; 1384 1385 1386 switch (p0) { 1387 case DPLL_CFGCR1_PDIV_2: 1388 p0 = 2; 1389 break; 1390 case DPLL_CFGCR1_PDIV_3: 1391 p0 = 3; 1392 break; 1393 case DPLL_CFGCR1_PDIV_5: 1394 p0 = 5; 1395 break; 1396 case DPLL_CFGCR1_PDIV_7: 1397 p0 = 7; 1398 break; 1399 } 1400 1401 switch (p2) { 1402 case DPLL_CFGCR1_KDIV_1: 1403 p2 = 1; 1404 break; 1405 case DPLL_CFGCR1_KDIV_2: 1406 p2 = 2; 1407 break; 1408 case DPLL_CFGCR1_KDIV_3: 1409 p2 = 3; 1410 break; 1411 } 1412 1413 ref_clock = cnl_hdmi_pll_ref_clock(dev_priv); 1414 1415 dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) 1416 * ref_clock; 1417 1418 dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >> 1419 DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000; 1420 1421 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0)) 1422 return 0; 1423 1424 return dco_freq / (p0 * p1 * p2 * 5); 1425 } 1426 1427 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 1428 enum port port) 1429 { 1430 u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 1431 1432 switch (val) { 1433 case DDI_CLK_SEL_NONE: 1434 return 0; 1435 case DDI_CLK_SEL_TBT_162: 1436 return 162000; 1437 case DDI_CLK_SEL_TBT_270: 1438 return 270000; 1439 case DDI_CLK_SEL_TBT_540: 1440 return 540000; 1441 case DDI_CLK_SEL_TBT_810: 1442 return 810000; 1443 default: 1444 MISSING_CASE(val); 1445 return 0; 1446 } 1447 } 1448 1449 static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv, 1450 const struct intel_dpll_hw_state *pll_state) 1451 { 1452 u32 m1, m2_int, m2_frac, div1, div2, ref_clock; 1453 u64 tmp; 1454 1455 ref_clock = dev_priv->cdclk.hw.ref; 1456 1457 if (INTEL_GEN(dev_priv) >= 12) { 1458 m1 = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK; 1459 m1 = m1 >> DKL_PLL_DIV0_FBPREDIV_SHIFT; 1460 m2_int = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBDIV_INT_MASK; 1461 1462 if (pll_state->mg_pll_bias & DKL_PLL_BIAS_FRAC_EN_H) { 1463 m2_frac = pll_state->mg_pll_bias & 1464 DKL_PLL_BIAS_FBDIV_FRAC_MASK; 1465 m2_frac = m2_frac >> DKL_PLL_BIAS_FBDIV_SHIFT; 1466 } else { 1467 m2_frac = 0; 1468 } 1469 } else { 1470 m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK; 1471 m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK; 1472 1473 if (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) { 1474 m2_frac = pll_state->mg_pll_div0 & 1475 MG_PLL_DIV0_FBDIV_FRAC_MASK; 1476 m2_frac = m2_frac >> MG_PLL_DIV0_FBDIV_FRAC_SHIFT; 1477 } else { 1478 m2_frac = 0; 1479 } 1480 } 1481 1482 switch (pll_state->mg_clktop2_hsclkctl & 1483 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) { 1484 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2: 1485 div1 = 2; 1486 break; 1487 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3: 1488 div1 = 3; 1489 break; 1490 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5: 1491 div1 = 5; 1492 break; 1493 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7: 1494 div1 = 7; 1495 break; 1496 default: 1497 MISSING_CASE(pll_state->mg_clktop2_hsclkctl); 1498 return 0; 1499 } 1500 1501 div2 = (pll_state->mg_clktop2_hsclkctl & 1502 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >> 1503 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT; 1504 1505 /* div2 value of 0 is same as 1 means no div */ 1506 if (div2 == 0) 1507 div2 = 1; 1508 1509 /* 1510 * Adjust the original formula to delay the division by 2^22 in order to 1511 * minimize possible rounding errors. 1512 */ 1513 tmp = (u64)m1 * m2_int * ref_clock + 1514 (((u64)m1 * m2_frac * ref_clock) >> 22); 1515 tmp = div_u64(tmp, 5 * div1 * div2); 1516 1517 return tmp; 1518 } 1519 1520 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 1521 { 1522 int dotclock; 1523 1524 if (pipe_config->has_pch_encoder) 1525 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1526 &pipe_config->fdi_m_n); 1527 else if (intel_crtc_has_dp_encoder(pipe_config)) 1528 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1529 &pipe_config->dp_m_n); 1530 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) 1531 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp; 1532 else 1533 dotclock = pipe_config->port_clock; 1534 1535 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 1536 !intel_crtc_has_dp_encoder(pipe_config)) 1537 dotclock *= 2; 1538 1539 if (pipe_config->pixel_multiplier) 1540 dotclock /= pipe_config->pixel_multiplier; 1541 1542 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 1543 } 1544 1545 static void icl_ddi_clock_get(struct intel_encoder *encoder, 1546 struct intel_crtc_state *pipe_config) 1547 { 1548 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1549 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state; 1550 enum port port = encoder->port; 1551 enum phy phy = intel_port_to_phy(dev_priv, port); 1552 int link_clock; 1553 1554 if (intel_phy_is_combo(dev_priv, phy)) { 1555 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state); 1556 } else { 1557 enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv, 1558 pipe_config->shared_dpll); 1559 1560 if (pll_id == DPLL_ID_ICL_TBTPLL) 1561 link_clock = icl_calc_tbt_pll_link(dev_priv, port); 1562 else 1563 link_clock = icl_calc_mg_pll_link(dev_priv, pll_state); 1564 } 1565 1566 pipe_config->port_clock = link_clock; 1567 1568 ddi_dotclock_get(pipe_config); 1569 } 1570 1571 static void cnl_ddi_clock_get(struct intel_encoder *encoder, 1572 struct intel_crtc_state *pipe_config) 1573 { 1574 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1575 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state; 1576 int link_clock; 1577 1578 if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) { 1579 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state); 1580 } else { 1581 link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK; 1582 1583 switch (link_clock) { 1584 case DPLL_CFGCR0_LINK_RATE_810: 1585 link_clock = 81000; 1586 break; 1587 case DPLL_CFGCR0_LINK_RATE_1080: 1588 link_clock = 108000; 1589 break; 1590 case DPLL_CFGCR0_LINK_RATE_1350: 1591 link_clock = 135000; 1592 break; 1593 case DPLL_CFGCR0_LINK_RATE_1620: 1594 link_clock = 162000; 1595 break; 1596 case DPLL_CFGCR0_LINK_RATE_2160: 1597 link_clock = 216000; 1598 break; 1599 case DPLL_CFGCR0_LINK_RATE_2700: 1600 link_clock = 270000; 1601 break; 1602 case DPLL_CFGCR0_LINK_RATE_3240: 1603 link_clock = 324000; 1604 break; 1605 case DPLL_CFGCR0_LINK_RATE_4050: 1606 link_clock = 405000; 1607 break; 1608 default: 1609 WARN(1, "Unsupported link rate\n"); 1610 break; 1611 } 1612 link_clock *= 2; 1613 } 1614 1615 pipe_config->port_clock = link_clock; 1616 1617 ddi_dotclock_get(pipe_config); 1618 } 1619 1620 static void skl_ddi_clock_get(struct intel_encoder *encoder, 1621 struct intel_crtc_state *pipe_config) 1622 { 1623 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state; 1624 int link_clock; 1625 1626 /* 1627 * ctrl1 register is already shifted for each pll, just use 0 to get 1628 * the internal shift for each field 1629 */ 1630 if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) { 1631 link_clock = skl_calc_wrpll_link(pll_state); 1632 } else { 1633 link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0); 1634 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(0); 1635 1636 switch (link_clock) { 1637 case DPLL_CTRL1_LINK_RATE_810: 1638 link_clock = 81000; 1639 break; 1640 case DPLL_CTRL1_LINK_RATE_1080: 1641 link_clock = 108000; 1642 break; 1643 case DPLL_CTRL1_LINK_RATE_1350: 1644 link_clock = 135000; 1645 break; 1646 case DPLL_CTRL1_LINK_RATE_1620: 1647 link_clock = 162000; 1648 break; 1649 case DPLL_CTRL1_LINK_RATE_2160: 1650 link_clock = 216000; 1651 break; 1652 case DPLL_CTRL1_LINK_RATE_2700: 1653 link_clock = 270000; 1654 break; 1655 default: 1656 WARN(1, "Unsupported link rate\n"); 1657 break; 1658 } 1659 link_clock *= 2; 1660 } 1661 1662 pipe_config->port_clock = link_clock; 1663 1664 ddi_dotclock_get(pipe_config); 1665 } 1666 1667 static void hsw_ddi_clock_get(struct intel_encoder *encoder, 1668 struct intel_crtc_state *pipe_config) 1669 { 1670 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1671 int link_clock = 0; 1672 u32 val, pll; 1673 1674 val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll); 1675 switch (val & PORT_CLK_SEL_MASK) { 1676 case PORT_CLK_SEL_LCPLL_810: 1677 link_clock = 81000; 1678 break; 1679 case PORT_CLK_SEL_LCPLL_1350: 1680 link_clock = 135000; 1681 break; 1682 case PORT_CLK_SEL_LCPLL_2700: 1683 link_clock = 270000; 1684 break; 1685 case PORT_CLK_SEL_WRPLL1: 1686 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0)); 1687 break; 1688 case PORT_CLK_SEL_WRPLL2: 1689 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1)); 1690 break; 1691 case PORT_CLK_SEL_SPLL: 1692 pll = I915_READ(SPLL_CTL) & SPLL_FREQ_MASK; 1693 if (pll == SPLL_FREQ_810MHz) 1694 link_clock = 81000; 1695 else if (pll == SPLL_FREQ_1350MHz) 1696 link_clock = 135000; 1697 else if (pll == SPLL_FREQ_2700MHz) 1698 link_clock = 270000; 1699 else { 1700 WARN(1, "bad spll freq\n"); 1701 return; 1702 } 1703 break; 1704 default: 1705 WARN(1, "bad port clock sel\n"); 1706 return; 1707 } 1708 1709 pipe_config->port_clock = link_clock * 2; 1710 1711 ddi_dotclock_get(pipe_config); 1712 } 1713 1714 static int bxt_calc_pll_link(const struct intel_dpll_hw_state *pll_state) 1715 { 1716 struct dpll clock; 1717 1718 clock.m1 = 2; 1719 clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22; 1720 if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE) 1721 clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK; 1722 clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT; 1723 clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT; 1724 clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT; 1725 1726 return chv_calc_dpll_params(100000, &clock); 1727 } 1728 1729 static void bxt_ddi_clock_get(struct intel_encoder *encoder, 1730 struct intel_crtc_state *pipe_config) 1731 { 1732 pipe_config->port_clock = 1733 bxt_calc_pll_link(&pipe_config->dpll_hw_state); 1734 1735 ddi_dotclock_get(pipe_config); 1736 } 1737 1738 static void intel_ddi_clock_get(struct intel_encoder *encoder, 1739 struct intel_crtc_state *pipe_config) 1740 { 1741 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1742 1743 if (INTEL_GEN(dev_priv) >= 11) 1744 icl_ddi_clock_get(encoder, pipe_config); 1745 else if (IS_CANNONLAKE(dev_priv)) 1746 cnl_ddi_clock_get(encoder, pipe_config); 1747 else if (IS_GEN9_LP(dev_priv)) 1748 bxt_ddi_clock_get(encoder, pipe_config); 1749 else if (IS_GEN9_BC(dev_priv)) 1750 skl_ddi_clock_get(encoder, pipe_config); 1751 else if (INTEL_GEN(dev_priv) <= 8) 1752 hsw_ddi_clock_get(encoder, pipe_config); 1753 } 1754 1755 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 1756 const struct drm_connector_state *conn_state) 1757 { 1758 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1759 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1760 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1761 u32 temp; 1762 1763 if (!intel_crtc_has_dp_encoder(crtc_state)) 1764 return; 1765 1766 WARN_ON(transcoder_is_dsi(cpu_transcoder)); 1767 1768 temp = DP_MSA_MISC_SYNC_CLOCK; 1769 1770 switch (crtc_state->pipe_bpp) { 1771 case 18: 1772 temp |= DP_MSA_MISC_6_BPC; 1773 break; 1774 case 24: 1775 temp |= DP_MSA_MISC_8_BPC; 1776 break; 1777 case 30: 1778 temp |= DP_MSA_MISC_10_BPC; 1779 break; 1780 case 36: 1781 temp |= DP_MSA_MISC_12_BPC; 1782 break; 1783 default: 1784 MISSING_CASE(crtc_state->pipe_bpp); 1785 break; 1786 } 1787 1788 /* nonsense combination */ 1789 WARN_ON(crtc_state->limited_color_range && 1790 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 1791 1792 if (crtc_state->limited_color_range) 1793 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 1794 1795 /* 1796 * As per DP 1.2 spec section 2.3.4.3 while sending 1797 * YCBCR 444 signals we should program MSA MISC1/0 fields with 1798 * colorspace information. 1799 */ 1800 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 1801 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 1802 1803 /* 1804 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 1805 * of Color Encoding Format and Content Color Gamut] while sending 1806 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 1807 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 1808 */ 1809 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 1810 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 1811 1812 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); 1813 } 1814 1815 /* 1816 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 1817 * 1818 * Only intended to be used by intel_ddi_enable_transcoder_func() and 1819 * intel_ddi_config_transcoder_func(). 1820 */ 1821 static u32 1822 intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state) 1823 { 1824 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1825 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc); 1826 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1827 enum pipe pipe = crtc->pipe; 1828 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1829 enum port port = encoder->port; 1830 u32 temp; 1831 1832 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 1833 temp = TRANS_DDI_FUNC_ENABLE; 1834 if (INTEL_GEN(dev_priv) >= 12) 1835 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 1836 else 1837 temp |= TRANS_DDI_SELECT_PORT(port); 1838 1839 switch (crtc_state->pipe_bpp) { 1840 case 18: 1841 temp |= TRANS_DDI_BPC_6; 1842 break; 1843 case 24: 1844 temp |= TRANS_DDI_BPC_8; 1845 break; 1846 case 30: 1847 temp |= TRANS_DDI_BPC_10; 1848 break; 1849 case 36: 1850 temp |= TRANS_DDI_BPC_12; 1851 break; 1852 default: 1853 BUG(); 1854 } 1855 1856 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 1857 temp |= TRANS_DDI_PVSYNC; 1858 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 1859 temp |= TRANS_DDI_PHSYNC; 1860 1861 if (cpu_transcoder == TRANSCODER_EDP) { 1862 switch (pipe) { 1863 case PIPE_A: 1864 /* On Haswell, can only use the always-on power well for 1865 * eDP when not using the panel fitter, and when not 1866 * using motion blur mitigation (which we don't 1867 * support). */ 1868 if (crtc_state->pch_pfit.force_thru) 1869 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 1870 else 1871 temp |= TRANS_DDI_EDP_INPUT_A_ON; 1872 break; 1873 case PIPE_B: 1874 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 1875 break; 1876 case PIPE_C: 1877 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 1878 break; 1879 default: 1880 BUG(); 1881 break; 1882 } 1883 } 1884 1885 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1886 if (crtc_state->has_hdmi_sink) 1887 temp |= TRANS_DDI_MODE_SELECT_HDMI; 1888 else 1889 temp |= TRANS_DDI_MODE_SELECT_DVI; 1890 1891 if (crtc_state->hdmi_scrambling) 1892 temp |= TRANS_DDI_HDMI_SCRAMBLING; 1893 if (crtc_state->hdmi_high_tmds_clock_ratio) 1894 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 1895 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 1896 temp |= TRANS_DDI_MODE_SELECT_FDI; 1897 temp |= (crtc_state->fdi_lanes - 1) << 1; 1898 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 1899 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 1900 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 1901 1902 if (INTEL_GEN(dev_priv) >= 12) 1903 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(crtc_state->cpu_transcoder); 1904 } else { 1905 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 1906 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 1907 } 1908 1909 return temp; 1910 } 1911 1912 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state) 1913 { 1914 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1915 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1916 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1917 u32 temp; 1918 1919 temp = intel_ddi_transcoder_func_reg_val_get(crtc_state); 1920 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 1921 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; 1922 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 1923 } 1924 1925 /* 1926 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 1927 * bit. 1928 */ 1929 static void 1930 intel_ddi_config_transcoder_func(const struct intel_crtc_state *crtc_state) 1931 { 1932 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1933 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1934 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1935 u32 temp; 1936 1937 temp = intel_ddi_transcoder_func_reg_val_get(crtc_state); 1938 temp &= ~TRANS_DDI_FUNC_ENABLE; 1939 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 1940 } 1941 1942 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 1943 { 1944 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1945 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1946 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1947 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); 1948 u32 val = I915_READ(reg); 1949 1950 if (INTEL_GEN(dev_priv) >= 12) { 1951 val &= ~(TRANS_DDI_FUNC_ENABLE | TGL_TRANS_DDI_PORT_MASK | 1952 TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 1953 } else { 1954 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | 1955 TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 1956 } 1957 I915_WRITE(reg, val); 1958 1959 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME && 1960 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1961 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n"); 1962 /* Quirk time at 100ms for reliable operation */ 1963 msleep(100); 1964 } 1965 } 1966 1967 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder, 1968 bool enable) 1969 { 1970 struct drm_device *dev = intel_encoder->base.dev; 1971 struct drm_i915_private *dev_priv = to_i915(dev); 1972 intel_wakeref_t wakeref; 1973 enum pipe pipe = 0; 1974 int ret = 0; 1975 u32 tmp; 1976 1977 wakeref = intel_display_power_get_if_enabled(dev_priv, 1978 intel_encoder->power_domain); 1979 if (WARN_ON(!wakeref)) 1980 return -ENXIO; 1981 1982 if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) { 1983 ret = -EIO; 1984 goto out; 1985 } 1986 1987 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe)); 1988 if (enable) 1989 tmp |= TRANS_DDI_HDCP_SIGNALLING; 1990 else 1991 tmp &= ~TRANS_DDI_HDCP_SIGNALLING; 1992 I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp); 1993 out: 1994 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 1995 return ret; 1996 } 1997 1998 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 1999 { 2000 struct drm_device *dev = intel_connector->base.dev; 2001 struct drm_i915_private *dev_priv = to_i915(dev); 2002 struct intel_encoder *encoder = intel_connector->encoder; 2003 int type = intel_connector->base.connector_type; 2004 enum port port = encoder->port; 2005 enum transcoder cpu_transcoder; 2006 intel_wakeref_t wakeref; 2007 enum pipe pipe = 0; 2008 u32 tmp; 2009 bool ret; 2010 2011 wakeref = intel_display_power_get_if_enabled(dev_priv, 2012 encoder->power_domain); 2013 if (!wakeref) 2014 return false; 2015 2016 if (!encoder->get_hw_state(encoder, &pipe)) { 2017 ret = false; 2018 goto out; 2019 } 2020 2021 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) 2022 cpu_transcoder = TRANSCODER_EDP; 2023 else 2024 cpu_transcoder = (enum transcoder) pipe; 2025 2026 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 2027 2028 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 2029 case TRANS_DDI_MODE_SELECT_HDMI: 2030 case TRANS_DDI_MODE_SELECT_DVI: 2031 ret = type == DRM_MODE_CONNECTOR_HDMIA; 2032 break; 2033 2034 case TRANS_DDI_MODE_SELECT_DP_SST: 2035 ret = type == DRM_MODE_CONNECTOR_eDP || 2036 type == DRM_MODE_CONNECTOR_DisplayPort; 2037 break; 2038 2039 case TRANS_DDI_MODE_SELECT_DP_MST: 2040 /* if the transcoder is in MST state then 2041 * connector isn't connected */ 2042 ret = false; 2043 break; 2044 2045 case TRANS_DDI_MODE_SELECT_FDI: 2046 ret = type == DRM_MODE_CONNECTOR_VGA; 2047 break; 2048 2049 default: 2050 ret = false; 2051 break; 2052 } 2053 2054 out: 2055 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 2056 2057 return ret; 2058 } 2059 2060 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 2061 u8 *pipe_mask, bool *is_dp_mst) 2062 { 2063 struct drm_device *dev = encoder->base.dev; 2064 struct drm_i915_private *dev_priv = to_i915(dev); 2065 enum port port = encoder->port; 2066 intel_wakeref_t wakeref; 2067 enum pipe p; 2068 u32 tmp; 2069 u8 mst_pipe_mask; 2070 2071 *pipe_mask = 0; 2072 *is_dp_mst = false; 2073 2074 wakeref = intel_display_power_get_if_enabled(dev_priv, 2075 encoder->power_domain); 2076 if (!wakeref) 2077 return; 2078 2079 tmp = I915_READ(DDI_BUF_CTL(port)); 2080 if (!(tmp & DDI_BUF_CTL_ENABLE)) 2081 goto out; 2082 2083 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) { 2084 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 2085 2086 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 2087 default: 2088 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 2089 /* fallthrough */ 2090 case TRANS_DDI_EDP_INPUT_A_ON: 2091 case TRANS_DDI_EDP_INPUT_A_ONOFF: 2092 *pipe_mask = BIT(PIPE_A); 2093 break; 2094 case TRANS_DDI_EDP_INPUT_B_ONOFF: 2095 *pipe_mask = BIT(PIPE_B); 2096 break; 2097 case TRANS_DDI_EDP_INPUT_C_ONOFF: 2098 *pipe_mask = BIT(PIPE_C); 2099 break; 2100 } 2101 2102 goto out; 2103 } 2104 2105 mst_pipe_mask = 0; 2106 for_each_pipe(dev_priv, p) { 2107 enum transcoder cpu_transcoder = (enum transcoder)p; 2108 unsigned int port_mask, ddi_select; 2109 intel_wakeref_t trans_wakeref; 2110 2111 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 2112 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 2113 if (!trans_wakeref) 2114 continue; 2115 2116 if (INTEL_GEN(dev_priv) >= 12) { 2117 port_mask = TGL_TRANS_DDI_PORT_MASK; 2118 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 2119 } else { 2120 port_mask = TRANS_DDI_PORT_MASK; 2121 ddi_select = TRANS_DDI_SELECT_PORT(port); 2122 } 2123 2124 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 2125 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 2126 trans_wakeref); 2127 2128 if ((tmp & port_mask) != ddi_select) 2129 continue; 2130 2131 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == 2132 TRANS_DDI_MODE_SELECT_DP_MST) 2133 mst_pipe_mask |= BIT(p); 2134 2135 *pipe_mask |= BIT(p); 2136 } 2137 2138 if (!*pipe_mask) 2139 DRM_DEBUG_KMS("No pipe for [ENCODER:%d:%s] found\n", 2140 encoder->base.base.id, encoder->base.name); 2141 2142 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 2143 DRM_DEBUG_KMS("Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 2144 encoder->base.base.id, encoder->base.name, 2145 *pipe_mask); 2146 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 2147 } 2148 2149 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 2150 DRM_DEBUG_KMS("Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", 2151 encoder->base.base.id, encoder->base.name, 2152 *pipe_mask, mst_pipe_mask); 2153 else 2154 *is_dp_mst = mst_pipe_mask; 2155 2156 out: 2157 if (*pipe_mask && IS_GEN9_LP(dev_priv)) { 2158 tmp = I915_READ(BXT_PHY_CTL(port)); 2159 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 2160 BXT_PHY_LANE_POWERDOWN_ACK | 2161 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 2162 DRM_ERROR("[ENCODER:%d:%s] enabled but PHY powered down? " 2163 "(PHY_CTL %08x)\n", encoder->base.base.id, 2164 encoder->base.name, tmp); 2165 } 2166 2167 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 2168 } 2169 2170 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 2171 enum pipe *pipe) 2172 { 2173 u8 pipe_mask; 2174 bool is_mst; 2175 2176 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2177 2178 if (is_mst || !pipe_mask) 2179 return false; 2180 2181 *pipe = ffs(pipe_mask) - 1; 2182 2183 return true; 2184 } 2185 2186 static inline enum intel_display_power_domain 2187 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port) 2188 { 2189 /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with 2190 * DC states enabled at the same time, while for driver initiated AUX 2191 * transfers we need the same AUX IOs to be powered but with DC states 2192 * disabled. Accordingly use the AUX power domain here which leaves DC 2193 * states enabled. 2194 * However, for non-A AUX ports the corresponding non-EDP transcoders 2195 * would have already enabled power well 2 and DC_OFF. This means we can 2196 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a 2197 * specific AUX_IO reference without powering up any extra wells. 2198 * Note that PSR is enabled only on Port A even though this function 2199 * returns the correct domain for other ports too. 2200 */ 2201 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A : 2202 intel_aux_power_domain(dig_port); 2203 } 2204 2205 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 2206 struct intel_crtc_state *crtc_state) 2207 { 2208 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2209 struct intel_digital_port *dig_port; 2210 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2211 2212 /* 2213 * TODO: Add support for MST encoders. Atm, the following should never 2214 * happen since fake-MST encoders don't set their get_power_domains() 2215 * hook. 2216 */ 2217 if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 2218 return; 2219 2220 dig_port = enc_to_dig_port(&encoder->base); 2221 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); 2222 2223 /* 2224 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC 2225 * ports. 2226 */ 2227 if (intel_crtc_has_dp_encoder(crtc_state) || 2228 intel_phy_is_tc(dev_priv, phy)) 2229 intel_display_power_get(dev_priv, 2230 intel_ddi_main_link_aux_domain(dig_port)); 2231 2232 /* 2233 * VDSC power is needed when DSC is enabled 2234 */ 2235 if (crtc_state->dsc.compression_enable) 2236 intel_display_power_get(dev_priv, 2237 intel_dsc_power_domain(crtc_state)); 2238 } 2239 2240 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state) 2241 { 2242 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2243 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2244 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc); 2245 enum port port = encoder->port; 2246 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2247 2248 if (cpu_transcoder != TRANSCODER_EDP) { 2249 if (INTEL_GEN(dev_priv) >= 12) 2250 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 2251 TGL_TRANS_CLK_SEL_PORT(port)); 2252 else 2253 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 2254 TRANS_CLK_SEL_PORT(port)); 2255 } 2256 } 2257 2258 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state) 2259 { 2260 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2261 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2262 2263 if (cpu_transcoder != TRANSCODER_EDP) { 2264 if (INTEL_GEN(dev_priv) >= 12) 2265 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 2266 TGL_TRANS_CLK_SEL_DISABLED); 2267 else 2268 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 2269 TRANS_CLK_SEL_DISABLED); 2270 } 2271 } 2272 2273 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 2274 enum port port, u8 iboost) 2275 { 2276 u32 tmp; 2277 2278 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0); 2279 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 2280 if (iboost) 2281 tmp |= iboost << BALANCE_LEG_SHIFT(port); 2282 else 2283 tmp |= BALANCE_LEG_DISABLE(port); 2284 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp); 2285 } 2286 2287 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 2288 int level, enum intel_output_type type) 2289 { 2290 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); 2291 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2292 enum port port = encoder->port; 2293 u8 iboost; 2294 2295 if (type == INTEL_OUTPUT_HDMI) 2296 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level; 2297 else 2298 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level; 2299 2300 if (iboost == 0) { 2301 const struct ddi_buf_trans *ddi_translations; 2302 int n_entries; 2303 2304 if (type == INTEL_OUTPUT_HDMI) 2305 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 2306 else if (type == INTEL_OUTPUT_EDP) 2307 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries); 2308 else 2309 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries); 2310 2311 if (WARN_ON_ONCE(!ddi_translations)) 2312 return; 2313 if (WARN_ON_ONCE(level >= n_entries)) 2314 level = n_entries - 1; 2315 2316 iboost = ddi_translations[level].i_boost; 2317 } 2318 2319 /* Make sure that the requested I_boost is valid */ 2320 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 2321 DRM_ERROR("Invalid I_boost value %u\n", iboost); 2322 return; 2323 } 2324 2325 _skl_ddi_set_iboost(dev_priv, port, iboost); 2326 2327 if (port == PORT_A && intel_dig_port->max_lanes == 4) 2328 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 2329 } 2330 2331 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, 2332 int level, enum intel_output_type type) 2333 { 2334 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2335 const struct bxt_ddi_buf_trans *ddi_translations; 2336 enum port port = encoder->port; 2337 int n_entries; 2338 2339 if (type == INTEL_OUTPUT_HDMI) 2340 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries); 2341 else if (type == INTEL_OUTPUT_EDP) 2342 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries); 2343 else 2344 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries); 2345 2346 if (WARN_ON_ONCE(!ddi_translations)) 2347 return; 2348 if (WARN_ON_ONCE(level >= n_entries)) 2349 level = n_entries - 1; 2350 2351 bxt_ddi_phy_set_signal_level(dev_priv, port, 2352 ddi_translations[level].margin, 2353 ddi_translations[level].scale, 2354 ddi_translations[level].enable, 2355 ddi_translations[level].deemphasis); 2356 } 2357 2358 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder) 2359 { 2360 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2361 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2362 enum port port = encoder->port; 2363 enum phy phy = intel_port_to_phy(dev_priv, port); 2364 int n_entries; 2365 2366 if (INTEL_GEN(dev_priv) >= 12) { 2367 if (intel_phy_is_combo(dev_priv, phy)) 2368 icl_get_combo_buf_trans(dev_priv, encoder->type, 2369 intel_dp->link_rate, &n_entries); 2370 else 2371 n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans); 2372 } else if (INTEL_GEN(dev_priv) == 11) { 2373 if (intel_phy_is_combo(dev_priv, phy)) 2374 icl_get_combo_buf_trans(dev_priv, encoder->type, 2375 intel_dp->link_rate, &n_entries); 2376 else 2377 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations); 2378 } else if (IS_CANNONLAKE(dev_priv)) { 2379 if (encoder->type == INTEL_OUTPUT_EDP) 2380 cnl_get_buf_trans_edp(dev_priv, &n_entries); 2381 else 2382 cnl_get_buf_trans_dp(dev_priv, &n_entries); 2383 } else if (IS_GEN9_LP(dev_priv)) { 2384 if (encoder->type == INTEL_OUTPUT_EDP) 2385 bxt_get_buf_trans_edp(dev_priv, &n_entries); 2386 else 2387 bxt_get_buf_trans_dp(dev_priv, &n_entries); 2388 } else { 2389 if (encoder->type == INTEL_OUTPUT_EDP) 2390 intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries); 2391 else 2392 intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries); 2393 } 2394 2395 if (WARN_ON(n_entries < 1)) 2396 n_entries = 1; 2397 if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 2398 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 2399 2400 return index_to_dp_signal_levels[n_entries - 1] & 2401 DP_TRAIN_VOLTAGE_SWING_MASK; 2402 } 2403 2404 /* 2405 * We assume that the full set of pre-emphasis values can be 2406 * used on all DDI platforms. Should that change we need to 2407 * rethink this code. 2408 */ 2409 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing) 2410 { 2411 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2412 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2413 return DP_TRAIN_PRE_EMPH_LEVEL_3; 2414 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 2415 return DP_TRAIN_PRE_EMPH_LEVEL_2; 2416 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 2417 return DP_TRAIN_PRE_EMPH_LEVEL_1; 2418 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 2419 default: 2420 return DP_TRAIN_PRE_EMPH_LEVEL_0; 2421 } 2422 } 2423 2424 static void cnl_ddi_vswing_program(struct intel_encoder *encoder, 2425 int level, enum intel_output_type type) 2426 { 2427 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2428 const struct cnl_ddi_buf_trans *ddi_translations; 2429 enum port port = encoder->port; 2430 int n_entries, ln; 2431 u32 val; 2432 2433 if (type == INTEL_OUTPUT_HDMI) 2434 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries); 2435 else if (type == INTEL_OUTPUT_EDP) 2436 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries); 2437 else 2438 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries); 2439 2440 if (WARN_ON_ONCE(!ddi_translations)) 2441 return; 2442 if (WARN_ON_ONCE(level >= n_entries)) 2443 level = n_entries - 1; 2444 2445 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */ 2446 val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); 2447 val &= ~SCALING_MODE_SEL_MASK; 2448 val |= SCALING_MODE_SEL(2); 2449 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); 2450 2451 /* Program PORT_TX_DW2 */ 2452 val = I915_READ(CNL_PORT_TX_DW2_LN0(port)); 2453 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 2454 RCOMP_SCALAR_MASK); 2455 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); 2456 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); 2457 /* Rcomp scalar is fixed as 0x98 for every table entry */ 2458 val |= RCOMP_SCALAR(0x98); 2459 I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val); 2460 2461 /* Program PORT_TX_DW4 */ 2462 /* We cannot write to GRP. It would overrite individual loadgen */ 2463 for (ln = 0; ln < 4; ln++) { 2464 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port)); 2465 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 2466 CURSOR_COEFF_MASK); 2467 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); 2468 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); 2469 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); 2470 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val); 2471 } 2472 2473 /* Program PORT_TX_DW5 */ 2474 /* All DW5 values are fixed for every table entry */ 2475 val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); 2476 val &= ~RTERM_SELECT_MASK; 2477 val |= RTERM_SELECT(6); 2478 val |= TAP3_DISABLE; 2479 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); 2480 2481 /* Program PORT_TX_DW7 */ 2482 val = I915_READ(CNL_PORT_TX_DW7_LN0(port)); 2483 val &= ~N_SCALAR_MASK; 2484 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); 2485 I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val); 2486 } 2487 2488 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, 2489 int level, enum intel_output_type type) 2490 { 2491 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2492 enum port port = encoder->port; 2493 int width, rate, ln; 2494 u32 val; 2495 2496 if (type == INTEL_OUTPUT_HDMI) { 2497 width = 4; 2498 rate = 0; /* Rate is always < than 6GHz for HDMI */ 2499 } else { 2500 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2501 2502 width = intel_dp->lane_count; 2503 rate = intel_dp->link_rate; 2504 } 2505 2506 /* 2507 * 1. If port type is eDP or DP, 2508 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 2509 * else clear to 0b. 2510 */ 2511 val = I915_READ(CNL_PORT_PCS_DW1_LN0(port)); 2512 if (type != INTEL_OUTPUT_HDMI) 2513 val |= COMMON_KEEPER_EN; 2514 else 2515 val &= ~COMMON_KEEPER_EN; 2516 I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val); 2517 2518 /* 2. Program loadgen select */ 2519 /* 2520 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes 2521 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2522 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2523 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 2524 */ 2525 for (ln = 0; ln <= 3; ln++) { 2526 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port)); 2527 val &= ~LOADGEN_SELECT; 2528 2529 if ((rate <= 600000 && width == 4 && ln >= 1) || 2530 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { 2531 val |= LOADGEN_SELECT; 2532 } 2533 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val); 2534 } 2535 2536 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 2537 val = I915_READ(CNL_PORT_CL1CM_DW5); 2538 val |= SUS_CLOCK_CONFIG; 2539 I915_WRITE(CNL_PORT_CL1CM_DW5, val); 2540 2541 /* 4. Clear training enable to change swing values */ 2542 val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); 2543 val &= ~TX_TRAINING_EN; 2544 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); 2545 2546 /* 5. Program swing and de-emphasis */ 2547 cnl_ddi_vswing_program(encoder, level, type); 2548 2549 /* 6. Set training enable to trigger update */ 2550 val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); 2551 val |= TX_TRAINING_EN; 2552 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); 2553 } 2554 2555 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, 2556 u32 level, enum phy phy, int type, 2557 int rate) 2558 { 2559 const struct cnl_ddi_buf_trans *ddi_translations = NULL; 2560 u32 n_entries, val; 2561 int ln; 2562 2563 ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate, 2564 &n_entries); 2565 if (!ddi_translations) 2566 return; 2567 2568 if (level >= n_entries) { 2569 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1); 2570 level = n_entries - 1; 2571 } 2572 2573 /* Set PORT_TX_DW5 */ 2574 val = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); 2575 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 2576 TAP2_DISABLE | TAP3_DISABLE); 2577 val |= SCALING_MODE_SEL(0x2); 2578 val |= RTERM_SELECT(0x6); 2579 val |= TAP3_DISABLE; 2580 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val); 2581 2582 /* Program PORT_TX_DW2 */ 2583 val = I915_READ(ICL_PORT_TX_DW2_LN0(phy)); 2584 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 2585 RCOMP_SCALAR_MASK); 2586 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); 2587 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); 2588 /* Program Rcomp scalar for every table entry */ 2589 val |= RCOMP_SCALAR(0x98); 2590 I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), val); 2591 2592 /* Program PORT_TX_DW4 */ 2593 /* We cannot write to GRP. It would overwrite individual loadgen. */ 2594 for (ln = 0; ln <= 3; ln++) { 2595 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy)); 2596 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 2597 CURSOR_COEFF_MASK); 2598 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); 2599 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); 2600 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); 2601 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val); 2602 } 2603 2604 /* Program PORT_TX_DW7 */ 2605 val = I915_READ(ICL_PORT_TX_DW7_LN0(phy)); 2606 val &= ~N_SCALAR_MASK; 2607 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); 2608 I915_WRITE(ICL_PORT_TX_DW7_GRP(phy), val); 2609 } 2610 2611 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 2612 u32 level, 2613 enum intel_output_type type) 2614 { 2615 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2616 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2617 int width = 0; 2618 int rate = 0; 2619 u32 val; 2620 int ln = 0; 2621 2622 if (type == INTEL_OUTPUT_HDMI) { 2623 width = 4; 2624 /* Rate is always < than 6GHz for HDMI */ 2625 } else { 2626 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2627 2628 width = intel_dp->lane_count; 2629 rate = intel_dp->link_rate; 2630 } 2631 2632 /* 2633 * 1. If port type is eDP or DP, 2634 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 2635 * else clear to 0b. 2636 */ 2637 val = I915_READ(ICL_PORT_PCS_DW1_LN0(phy)); 2638 if (type == INTEL_OUTPUT_HDMI) 2639 val &= ~COMMON_KEEPER_EN; 2640 else 2641 val |= COMMON_KEEPER_EN; 2642 I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), val); 2643 2644 /* 2. Program loadgen select */ 2645 /* 2646 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes 2647 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2648 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2649 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 2650 */ 2651 for (ln = 0; ln <= 3; ln++) { 2652 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy)); 2653 val &= ~LOADGEN_SELECT; 2654 2655 if ((rate <= 600000 && width == 4 && ln >= 1) || 2656 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { 2657 val |= LOADGEN_SELECT; 2658 } 2659 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val); 2660 } 2661 2662 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 2663 val = I915_READ(ICL_PORT_CL_DW5(phy)); 2664 val |= SUS_CLOCK_CONFIG; 2665 I915_WRITE(ICL_PORT_CL_DW5(phy), val); 2666 2667 /* 4. Clear training enable to change swing values */ 2668 val = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); 2669 val &= ~TX_TRAINING_EN; 2670 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val); 2671 2672 /* 5. Program swing and de-emphasis */ 2673 icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate); 2674 2675 /* 6. Set training enable to trigger update */ 2676 val = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); 2677 val |= TX_TRAINING_EN; 2678 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val); 2679 } 2680 2681 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 2682 int link_clock, 2683 u32 level) 2684 { 2685 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2686 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 2687 const struct icl_mg_phy_ddi_buf_trans *ddi_translations; 2688 u32 n_entries, val; 2689 int ln; 2690 2691 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations); 2692 ddi_translations = icl_mg_phy_ddi_translations; 2693 /* The table does not have values for level 3 and level 9. */ 2694 if (level >= n_entries || level == 3 || level == 9) { 2695 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", 2696 level, n_entries - 2); 2697 level = n_entries - 2; 2698 } 2699 2700 /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */ 2701 for (ln = 0; ln < 2; ln++) { 2702 val = I915_READ(MG_TX1_LINK_PARAMS(ln, tc_port)); 2703 val &= ~CRI_USE_FS32; 2704 I915_WRITE(MG_TX1_LINK_PARAMS(ln, tc_port), val); 2705 2706 val = I915_READ(MG_TX2_LINK_PARAMS(ln, tc_port)); 2707 val &= ~CRI_USE_FS32; 2708 I915_WRITE(MG_TX2_LINK_PARAMS(ln, tc_port), val); 2709 } 2710 2711 /* Program MG_TX_SWINGCTRL with values from vswing table */ 2712 for (ln = 0; ln < 2; ln++) { 2713 val = I915_READ(MG_TX1_SWINGCTRL(ln, tc_port)); 2714 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; 2715 val |= CRI_TXDEEMPH_OVERRIDE_17_12( 2716 ddi_translations[level].cri_txdeemph_override_17_12); 2717 I915_WRITE(MG_TX1_SWINGCTRL(ln, tc_port), val); 2718 2719 val = I915_READ(MG_TX2_SWINGCTRL(ln, tc_port)); 2720 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; 2721 val |= CRI_TXDEEMPH_OVERRIDE_17_12( 2722 ddi_translations[level].cri_txdeemph_override_17_12); 2723 I915_WRITE(MG_TX2_SWINGCTRL(ln, tc_port), val); 2724 } 2725 2726 /* Program MG_TX_DRVCTRL with values from vswing table */ 2727 for (ln = 0; ln < 2; ln++) { 2728 val = I915_READ(MG_TX1_DRVCTRL(ln, tc_port)); 2729 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 2730 CRI_TXDEEMPH_OVERRIDE_5_0_MASK); 2731 val |= CRI_TXDEEMPH_OVERRIDE_5_0( 2732 ddi_translations[level].cri_txdeemph_override_5_0) | 2733 CRI_TXDEEMPH_OVERRIDE_11_6( 2734 ddi_translations[level].cri_txdeemph_override_11_6) | 2735 CRI_TXDEEMPH_OVERRIDE_EN; 2736 I915_WRITE(MG_TX1_DRVCTRL(ln, tc_port), val); 2737 2738 val = I915_READ(MG_TX2_DRVCTRL(ln, tc_port)); 2739 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 2740 CRI_TXDEEMPH_OVERRIDE_5_0_MASK); 2741 val |= CRI_TXDEEMPH_OVERRIDE_5_0( 2742 ddi_translations[level].cri_txdeemph_override_5_0) | 2743 CRI_TXDEEMPH_OVERRIDE_11_6( 2744 ddi_translations[level].cri_txdeemph_override_11_6) | 2745 CRI_TXDEEMPH_OVERRIDE_EN; 2746 I915_WRITE(MG_TX2_DRVCTRL(ln, tc_port), val); 2747 2748 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 2749 } 2750 2751 /* 2752 * Program MG_CLKHUB<LN, port being used> with value from frequency table 2753 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 2754 * values from table for which TX1 and TX2 enabled. 2755 */ 2756 for (ln = 0; ln < 2; ln++) { 2757 val = I915_READ(MG_CLKHUB(ln, tc_port)); 2758 if (link_clock < 300000) 2759 val |= CFG_LOW_RATE_LKREN_EN; 2760 else 2761 val &= ~CFG_LOW_RATE_LKREN_EN; 2762 I915_WRITE(MG_CLKHUB(ln, tc_port), val); 2763 } 2764 2765 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 2766 for (ln = 0; ln < 2; ln++) { 2767 val = I915_READ(MG_TX1_DCC(ln, tc_port)); 2768 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; 2769 if (link_clock <= 500000) { 2770 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; 2771 } else { 2772 val |= CFG_AMI_CK_DIV_OVERRIDE_EN | 2773 CFG_AMI_CK_DIV_OVERRIDE_VAL(1); 2774 } 2775 I915_WRITE(MG_TX1_DCC(ln, tc_port), val); 2776 2777 val = I915_READ(MG_TX2_DCC(ln, tc_port)); 2778 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; 2779 if (link_clock <= 500000) { 2780 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; 2781 } else { 2782 val |= CFG_AMI_CK_DIV_OVERRIDE_EN | 2783 CFG_AMI_CK_DIV_OVERRIDE_VAL(1); 2784 } 2785 I915_WRITE(MG_TX2_DCC(ln, tc_port), val); 2786 } 2787 2788 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 2789 for (ln = 0; ln < 2; ln++) { 2790 val = I915_READ(MG_TX1_PISO_READLOAD(ln, tc_port)); 2791 val |= CRI_CALCINIT; 2792 I915_WRITE(MG_TX1_PISO_READLOAD(ln, tc_port), val); 2793 2794 val = I915_READ(MG_TX2_PISO_READLOAD(ln, tc_port)); 2795 val |= CRI_CALCINIT; 2796 I915_WRITE(MG_TX2_PISO_READLOAD(ln, tc_port), val); 2797 } 2798 } 2799 2800 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder, 2801 int link_clock, 2802 u32 level, 2803 enum intel_output_type type) 2804 { 2805 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2806 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2807 2808 if (intel_phy_is_combo(dev_priv, phy)) 2809 icl_combo_phy_ddi_vswing_sequence(encoder, level, type); 2810 else 2811 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level); 2812 } 2813 2814 static void 2815 tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock, 2816 u32 level) 2817 { 2818 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2819 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 2820 const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations; 2821 u32 n_entries, val, ln, dpcnt_mask, dpcnt_val; 2822 2823 if (encoder->type == INTEL_OUTPUT_HDMI) { 2824 n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans); 2825 ddi_translations = tgl_dkl_phy_hdmi_ddi_trans; 2826 } else { 2827 n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans); 2828 ddi_translations = tgl_dkl_phy_dp_ddi_trans; 2829 } 2830 2831 if (level >= n_entries) 2832 level = n_entries - 1; 2833 2834 dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK | 2835 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 2836 DKL_TX_VSWING_CONTROL_MASK); 2837 dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control); 2838 dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control); 2839 dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control); 2840 2841 for (ln = 0; ln < 2; ln++) { 2842 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln)); 2843 2844 I915_WRITE(DKL_TX_PMD_LANE_SUS(tc_port), 0); 2845 2846 /* All the registers are RMW */ 2847 val = I915_READ(DKL_TX_DPCNTL0(tc_port)); 2848 val &= ~dpcnt_mask; 2849 val |= dpcnt_val; 2850 I915_WRITE(DKL_TX_DPCNTL0(tc_port), val); 2851 2852 val = I915_READ(DKL_TX_DPCNTL1(tc_port)); 2853 val &= ~dpcnt_mask; 2854 val |= dpcnt_val; 2855 I915_WRITE(DKL_TX_DPCNTL1(tc_port), val); 2856 2857 val = I915_READ(DKL_TX_DPCNTL2(tc_port)); 2858 val &= ~DKL_TX_DP20BITMODE; 2859 I915_WRITE(DKL_TX_DPCNTL2(tc_port), val); 2860 } 2861 } 2862 2863 static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder, 2864 int link_clock, 2865 u32 level, 2866 enum intel_output_type type) 2867 { 2868 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2869 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2870 2871 if (intel_phy_is_combo(dev_priv, phy)) 2872 icl_combo_phy_ddi_vswing_sequence(encoder, level, type); 2873 else 2874 tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level); 2875 } 2876 2877 static u32 translate_signal_level(int signal_levels) 2878 { 2879 int i; 2880 2881 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 2882 if (index_to_dp_signal_levels[i] == signal_levels) 2883 return i; 2884 } 2885 2886 WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 2887 signal_levels); 2888 2889 return 0; 2890 } 2891 2892 static u32 intel_ddi_dp_level(struct intel_dp *intel_dp) 2893 { 2894 u8 train_set = intel_dp->train_set[0]; 2895 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2896 DP_TRAIN_PRE_EMPHASIS_MASK); 2897 2898 return translate_signal_level(signal_levels); 2899 } 2900 2901 u32 bxt_signal_levels(struct intel_dp *intel_dp) 2902 { 2903 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2904 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); 2905 struct intel_encoder *encoder = &dport->base; 2906 int level = intel_ddi_dp_level(intel_dp); 2907 2908 if (INTEL_GEN(dev_priv) >= 12) 2909 tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate, 2910 level, encoder->type); 2911 else if (INTEL_GEN(dev_priv) >= 11) 2912 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate, 2913 level, encoder->type); 2914 else if (IS_CANNONLAKE(dev_priv)) 2915 cnl_ddi_vswing_sequence(encoder, level, encoder->type); 2916 else 2917 bxt_ddi_vswing_sequence(encoder, level, encoder->type); 2918 2919 return 0; 2920 } 2921 2922 u32 ddi_signal_levels(struct intel_dp *intel_dp) 2923 { 2924 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2925 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); 2926 struct intel_encoder *encoder = &dport->base; 2927 int level = intel_ddi_dp_level(intel_dp); 2928 2929 if (IS_GEN9_BC(dev_priv)) 2930 skl_ddi_set_iboost(encoder, level, encoder->type); 2931 2932 return DDI_BUF_TRANS_SELECT(level); 2933 } 2934 2935 static inline 2936 u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv, 2937 enum phy phy) 2938 { 2939 if (intel_phy_is_combo(dev_priv, phy)) { 2940 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 2941 } else if (intel_phy_is_tc(dev_priv, phy)) { 2942 enum tc_port tc_port = intel_port_to_tc(dev_priv, 2943 (enum port)phy); 2944 2945 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port); 2946 } 2947 2948 return 0; 2949 } 2950 2951 static void icl_map_plls_to_ports(struct intel_encoder *encoder, 2952 const struct intel_crtc_state *crtc_state) 2953 { 2954 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2955 struct intel_shared_dpll *pll = crtc_state->shared_dpll; 2956 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2957 u32 val; 2958 2959 mutex_lock(&dev_priv->dpll_lock); 2960 2961 val = I915_READ(ICL_DPCLKA_CFGCR0); 2962 WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0); 2963 2964 if (intel_phy_is_combo(dev_priv, phy)) { 2965 /* 2966 * Even though this register references DDIs, note that we 2967 * want to pass the PHY rather than the port (DDI). For 2968 * ICL, port=phy in all cases so it doesn't matter, but for 2969 * EHL the bspec notes the following: 2970 * 2971 * "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA 2972 * Clock Select chooses the PLL for both DDIA and DDID and 2973 * drives port A in all cases." 2974 */ 2975 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 2976 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 2977 I915_WRITE(ICL_DPCLKA_CFGCR0, val); 2978 POSTING_READ(ICL_DPCLKA_CFGCR0); 2979 } 2980 2981 val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 2982 I915_WRITE(ICL_DPCLKA_CFGCR0, val); 2983 2984 mutex_unlock(&dev_priv->dpll_lock); 2985 } 2986 2987 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder) 2988 { 2989 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2990 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2991 u32 val; 2992 2993 mutex_lock(&dev_priv->dpll_lock); 2994 2995 val = I915_READ(ICL_DPCLKA_CFGCR0); 2996 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 2997 I915_WRITE(ICL_DPCLKA_CFGCR0, val); 2998 2999 mutex_unlock(&dev_priv->dpll_lock); 3000 } 3001 3002 static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv, 3003 u32 port_mask, bool ddi_clk_needed) 3004 { 3005 enum port port; 3006 u32 val; 3007 3008 val = I915_READ(ICL_DPCLKA_CFGCR0); 3009 for_each_port_masked(port, port_mask) { 3010 enum phy phy = intel_port_to_phy(dev_priv, port); 3011 bool ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv, 3012 phy); 3013 3014 if (ddi_clk_needed == !ddi_clk_off) 3015 continue; 3016 3017 /* 3018 * Punt on the case now where clock is gated, but it would 3019 * be needed by the port. Something else is really broken then. 3020 */ 3021 if (WARN_ON(ddi_clk_needed)) 3022 continue; 3023 3024 DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n", 3025 phy_name(phy)); 3026 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 3027 I915_WRITE(ICL_DPCLKA_CFGCR0, val); 3028 } 3029 } 3030 3031 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 3032 { 3033 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3034 u32 port_mask; 3035 bool ddi_clk_needed; 3036 3037 /* 3038 * In case of DP MST, we sanitize the primary encoder only, not the 3039 * virtual ones. 3040 */ 3041 if (encoder->type == INTEL_OUTPUT_DP_MST) 3042 return; 3043 3044 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 3045 u8 pipe_mask; 3046 bool is_mst; 3047 3048 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 3049 /* 3050 * In the unlikely case that BIOS enables DP in MST mode, just 3051 * warn since our MST HW readout is incomplete. 3052 */ 3053 if (WARN_ON(is_mst)) 3054 return; 3055 } 3056 3057 port_mask = BIT(encoder->port); 3058 ddi_clk_needed = encoder->base.crtc; 3059 3060 if (encoder->type == INTEL_OUTPUT_DSI) { 3061 struct intel_encoder *other_encoder; 3062 3063 port_mask = intel_dsi_encoder_ports(encoder); 3064 /* 3065 * Sanity check that we haven't incorrectly registered another 3066 * encoder using any of the ports of this DSI encoder. 3067 */ 3068 for_each_intel_encoder(&dev_priv->drm, other_encoder) { 3069 if (other_encoder == encoder) 3070 continue; 3071 3072 if (WARN_ON(port_mask & BIT(other_encoder->port))) 3073 return; 3074 } 3075 /* 3076 * For DSI we keep the ddi clocks gated 3077 * except during enable/disable sequence. 3078 */ 3079 ddi_clk_needed = false; 3080 } 3081 3082 icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed); 3083 } 3084 3085 static void intel_ddi_clk_select(struct intel_encoder *encoder, 3086 const struct intel_crtc_state *crtc_state) 3087 { 3088 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3089 enum port port = encoder->port; 3090 enum phy phy = intel_port_to_phy(dev_priv, port); 3091 u32 val; 3092 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 3093 3094 if (WARN_ON(!pll)) 3095 return; 3096 3097 mutex_lock(&dev_priv->dpll_lock); 3098 3099 if (INTEL_GEN(dev_priv) >= 11) { 3100 if (!intel_phy_is_combo(dev_priv, phy)) 3101 I915_WRITE(DDI_CLK_SEL(port), 3102 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 3103 else if (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C) 3104 /* 3105 * MG does not exist but the programming is required 3106 * to ungate DDIC and DDID 3107 */ 3108 I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 3109 } else if (IS_CANNONLAKE(dev_priv)) { 3110 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */ 3111 val = I915_READ(DPCLKA_CFGCR0); 3112 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); 3113 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port); 3114 I915_WRITE(DPCLKA_CFGCR0, val); 3115 3116 /* 3117 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI. 3118 * This step and the step before must be done with separate 3119 * register writes. 3120 */ 3121 val = I915_READ(DPCLKA_CFGCR0); 3122 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); 3123 I915_WRITE(DPCLKA_CFGCR0, val); 3124 } else if (IS_GEN9_BC(dev_priv)) { 3125 /* DDI -> PLL mapping */ 3126 val = I915_READ(DPLL_CTRL2); 3127 3128 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | 3129 DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); 3130 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 3131 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 3132 3133 I915_WRITE(DPLL_CTRL2, val); 3134 3135 } else if (INTEL_GEN(dev_priv) < 9) { 3136 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 3137 } 3138 3139 mutex_unlock(&dev_priv->dpll_lock); 3140 } 3141 3142 static void intel_ddi_clk_disable(struct intel_encoder *encoder) 3143 { 3144 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3145 enum port port = encoder->port; 3146 enum phy phy = intel_port_to_phy(dev_priv, port); 3147 3148 if (INTEL_GEN(dev_priv) >= 11) { 3149 if (!intel_phy_is_combo(dev_priv, phy) || 3150 (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C)) 3151 I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 3152 } else if (IS_CANNONLAKE(dev_priv)) { 3153 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) | 3154 DPCLKA_CFGCR0_DDI_CLK_OFF(port)); 3155 } else if (IS_GEN9_BC(dev_priv)) { 3156 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) | 3157 DPLL_CTRL2_DDI_CLK_OFF(port)); 3158 } else if (INTEL_GEN(dev_priv) < 9) { 3159 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 3160 } 3161 } 3162 3163 static void 3164 icl_phy_set_clock_gating(struct intel_digital_port *dig_port, bool enable) 3165 { 3166 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 3167 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port); 3168 u32 val, bits; 3169 int ln; 3170 3171 if (tc_port == PORT_TC_NONE) 3172 return; 3173 3174 bits = MG_DP_MODE_CFG_TR2PWR_GATING | MG_DP_MODE_CFG_TRPWR_GATING | 3175 MG_DP_MODE_CFG_CLNPWR_GATING | MG_DP_MODE_CFG_DIGPWR_GATING | 3176 MG_DP_MODE_CFG_GAONPWR_GATING; 3177 3178 for (ln = 0; ln < 2; ln++) { 3179 if (INTEL_GEN(dev_priv) >= 12) { 3180 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln)); 3181 val = I915_READ(DKL_DP_MODE(tc_port)); 3182 } else { 3183 val = I915_READ(MG_DP_MODE(ln, tc_port)); 3184 } 3185 3186 if (enable) 3187 val |= bits; 3188 else 3189 val &= ~bits; 3190 3191 if (INTEL_GEN(dev_priv) >= 12) 3192 I915_WRITE(DKL_DP_MODE(tc_port), val); 3193 else 3194 I915_WRITE(MG_DP_MODE(ln, tc_port), val); 3195 } 3196 3197 if (INTEL_GEN(dev_priv) == 11) { 3198 bits = MG_MISC_SUS0_CFG_TR2PWR_GATING | 3199 MG_MISC_SUS0_CFG_CL2PWR_GATING | 3200 MG_MISC_SUS0_CFG_GAONPWR_GATING | 3201 MG_MISC_SUS0_CFG_TRPWR_GATING | 3202 MG_MISC_SUS0_CFG_CL1PWR_GATING | 3203 MG_MISC_SUS0_CFG_DGPWR_GATING; 3204 3205 val = I915_READ(MG_MISC_SUS0(tc_port)); 3206 if (enable) 3207 val |= (bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3)); 3208 else 3209 val &= ~(bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK); 3210 I915_WRITE(MG_MISC_SUS0(tc_port), val); 3211 } 3212 } 3213 3214 static void 3215 icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port, 3216 const struct intel_crtc_state *crtc_state) 3217 { 3218 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); 3219 enum tc_port tc_port = intel_port_to_tc(dev_priv, intel_dig_port->base.port); 3220 u32 ln0, ln1, pin_assignment; 3221 u8 width; 3222 3223 if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT) 3224 return; 3225 3226 if (INTEL_GEN(dev_priv) >= 12) { 3227 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x0)); 3228 ln0 = I915_READ(DKL_DP_MODE(tc_port)); 3229 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x1)); 3230 ln1 = I915_READ(DKL_DP_MODE(tc_port)); 3231 } else { 3232 ln0 = I915_READ(MG_DP_MODE(0, tc_port)); 3233 ln1 = I915_READ(MG_DP_MODE(1, tc_port)); 3234 } 3235 3236 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X1_MODE); 3237 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 3238 3239 /* DPPATC */ 3240 pin_assignment = intel_tc_port_get_pin_assignment_mask(intel_dig_port); 3241 width = crtc_state->lane_count; 3242 3243 switch (pin_assignment) { 3244 case 0x0: 3245 WARN_ON(intel_dig_port->tc_mode != TC_PORT_LEGACY); 3246 if (width == 1) { 3247 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 3248 } else { 3249 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3250 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3251 } 3252 break; 3253 case 0x1: 3254 if (width == 4) { 3255 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3256 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3257 } 3258 break; 3259 case 0x2: 3260 if (width == 2) { 3261 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3262 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3263 } 3264 break; 3265 case 0x3: 3266 case 0x5: 3267 if (width == 1) { 3268 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 3269 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 3270 } else { 3271 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3272 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3273 } 3274 break; 3275 case 0x4: 3276 case 0x6: 3277 if (width == 1) { 3278 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 3279 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 3280 } else { 3281 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3282 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3283 } 3284 break; 3285 default: 3286 MISSING_CASE(pin_assignment); 3287 } 3288 3289 if (INTEL_GEN(dev_priv) >= 12) { 3290 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x0)); 3291 I915_WRITE(DKL_DP_MODE(tc_port), ln0); 3292 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x1)); 3293 I915_WRITE(DKL_DP_MODE(tc_port), ln1); 3294 } else { 3295 I915_WRITE(MG_DP_MODE(0, tc_port), ln0); 3296 I915_WRITE(MG_DP_MODE(1, tc_port), ln1); 3297 } 3298 } 3299 3300 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 3301 const struct intel_crtc_state *crtc_state) 3302 { 3303 if (!crtc_state->fec_enable) 3304 return; 3305 3306 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0) 3307 DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n"); 3308 } 3309 3310 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 3311 const struct intel_crtc_state *crtc_state) 3312 { 3313 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3314 struct intel_dp *intel_dp; 3315 u32 val; 3316 3317 if (!crtc_state->fec_enable) 3318 return; 3319 3320 intel_dp = enc_to_intel_dp(&encoder->base); 3321 val = I915_READ(intel_dp->regs.dp_tp_ctl); 3322 val |= DP_TP_CTL_FEC_ENABLE; 3323 I915_WRITE(intel_dp->regs.dp_tp_ctl, val); 3324 3325 if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, 3326 DP_TP_STATUS_FEC_ENABLE_LIVE, 1)) 3327 DRM_ERROR("Timed out waiting for FEC Enable Status\n"); 3328 } 3329 3330 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder, 3331 const struct intel_crtc_state *crtc_state) 3332 { 3333 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3334 struct intel_dp *intel_dp; 3335 u32 val; 3336 3337 if (!crtc_state->fec_enable) 3338 return; 3339 3340 intel_dp = enc_to_intel_dp(&encoder->base); 3341 val = I915_READ(intel_dp->regs.dp_tp_ctl); 3342 val &= ~DP_TP_CTL_FEC_ENABLE; 3343 I915_WRITE(intel_dp->regs.dp_tp_ctl, val); 3344 POSTING_READ(intel_dp->regs.dp_tp_ctl); 3345 } 3346 3347 static void 3348 tgl_clear_psr2_transcoder_exitline(const struct intel_crtc_state *cstate) 3349 { 3350 struct drm_i915_private *dev_priv = to_i915(cstate->uapi.crtc->dev); 3351 u32 val; 3352 3353 if (!cstate->dc3co_exitline) 3354 return; 3355 3356 val = I915_READ(EXITLINE(cstate->cpu_transcoder)); 3357 val &= ~(EXITLINE_MASK | EXITLINE_ENABLE); 3358 I915_WRITE(EXITLINE(cstate->cpu_transcoder), val); 3359 } 3360 3361 static void 3362 tgl_set_psr2_transcoder_exitline(const struct intel_crtc_state *cstate) 3363 { 3364 u32 val, exit_scanlines; 3365 struct drm_i915_private *dev_priv = to_i915(cstate->uapi.crtc->dev); 3366 3367 if (!cstate->dc3co_exitline) 3368 return; 3369 3370 exit_scanlines = cstate->dc3co_exitline; 3371 exit_scanlines <<= EXITLINE_SHIFT; 3372 val = I915_READ(EXITLINE(cstate->cpu_transcoder)); 3373 val &= ~(EXITLINE_MASK | EXITLINE_ENABLE); 3374 val |= exit_scanlines; 3375 val |= EXITLINE_ENABLE; 3376 I915_WRITE(EXITLINE(cstate->cpu_transcoder), val); 3377 } 3378 3379 static void tgl_dc3co_exitline_compute_config(struct intel_encoder *encoder, 3380 struct intel_crtc_state *cstate) 3381 { 3382 u32 exit_scanlines; 3383 struct drm_i915_private *dev_priv = to_i915(cstate->uapi.crtc->dev); 3384 u32 crtc_vdisplay = cstate->hw.adjusted_mode.crtc_vdisplay; 3385 3386 cstate->dc3co_exitline = 0; 3387 3388 if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)) 3389 return; 3390 3391 /* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/ 3392 if (to_intel_crtc(cstate->uapi.crtc)->pipe != PIPE_A || 3393 encoder->port != PORT_A) 3394 return; 3395 3396 if (!cstate->has_psr2 || !cstate->hw.active) 3397 return; 3398 3399 /* 3400 * DC3CO Exit time 200us B.Spec 49196 3401 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1 3402 */ 3403 exit_scanlines = 3404 intel_usecs_to_scanlines(&cstate->hw.adjusted_mode, 200) + 1; 3405 3406 if (WARN_ON(exit_scanlines > crtc_vdisplay)) 3407 return; 3408 3409 cstate->dc3co_exitline = crtc_vdisplay - exit_scanlines; 3410 DRM_DEBUG_KMS("DC3CO exit scanlines %d\n", cstate->dc3co_exitline); 3411 } 3412 3413 static void tgl_dc3co_exitline_get_config(struct intel_crtc_state *crtc_state) 3414 { 3415 u32 val; 3416 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3417 3418 if (INTEL_GEN(dev_priv) < 12) 3419 return; 3420 3421 val = I915_READ(EXITLINE(crtc_state->cpu_transcoder)); 3422 3423 if (val & EXITLINE_ENABLE) 3424 crtc_state->dc3co_exitline = val & EXITLINE_MASK; 3425 } 3426 3427 static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder, 3428 const struct intel_crtc_state *crtc_state, 3429 const struct drm_connector_state *conn_state) 3430 { 3431 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 3432 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3433 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3434 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 3435 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 3436 int level = intel_ddi_dp_level(intel_dp); 3437 enum transcoder transcoder = crtc_state->cpu_transcoder; 3438 3439 tgl_set_psr2_transcoder_exitline(crtc_state); 3440 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, 3441 crtc_state->lane_count, is_mst); 3442 3443 intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder); 3444 intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder); 3445 3446 /* 3447 * 1. Enable Power Wells 3448 * 3449 * This was handled at the beginning of intel_atomic_commit_tail(), 3450 * before we called down into this function. 3451 */ 3452 3453 /* 2. Enable Panel Power if PPS is required */ 3454 intel_edp_panel_on(intel_dp); 3455 3456 /* 3457 * 3. For non-TBT Type-C ports, set FIA lane count 3458 * (DFLEXDPSP.DPX4TXLATC) 3459 * 3460 * This was done before tgl_ddi_pre_enable_dp by 3461 * haswell_crtc_enable()->intel_encoders_pre_pll_enable(). 3462 */ 3463 3464 /* 3465 * 4. Enable the port PLL. 3466 * 3467 * The PLL enabling itself was already done before this function by 3468 * haswell_crtc_enable()->intel_enable_shared_dpll(). We need only 3469 * configure the PLL to port mapping here. 3470 */ 3471 intel_ddi_clk_select(encoder, crtc_state); 3472 3473 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 3474 if (!intel_phy_is_tc(dev_priv, phy) || 3475 dig_port->tc_mode != TC_PORT_TBT_ALT) 3476 intel_display_power_get(dev_priv, 3477 dig_port->ddi_io_power_domain); 3478 3479 /* 6. Program DP_MODE */ 3480 icl_program_mg_dp_mode(dig_port, crtc_state); 3481 3482 /* 3483 * 7. The rest of the below are substeps under the bspec's "Enable and 3484 * Train Display Port" step. Note that steps that are specific to 3485 * MST will be handled by intel_mst_pre_enable_dp() before/after it 3486 * calls into this function. Also intel_mst_pre_enable_dp() only calls 3487 * us when active_mst_links==0, so any steps designated for "single 3488 * stream or multi-stream master transcoder" can just be performed 3489 * unconditionally here. 3490 */ 3491 3492 /* 3493 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 3494 * Transcoder. 3495 */ 3496 intel_ddi_enable_pipe_clock(crtc_state); 3497 3498 /* 3499 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 3500 * Transport Select 3501 */ 3502 intel_ddi_config_transcoder_func(crtc_state); 3503 3504 /* 3505 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 3506 * selected 3507 * 3508 * This will be handled by the intel_dp_start_link_train() farther 3509 * down this function. 3510 */ 3511 3512 /* 3513 * 7.d Type C with DP alternate or fixed/legacy/static connection - 3514 * Disable PHY clock gating per Type-C DDI Buffer page 3515 */ 3516 icl_phy_set_clock_gating(dig_port, false); 3517 3518 /* 7.e Configure voltage swing and related IO settings */ 3519 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level, 3520 encoder->type); 3521 3522 /* 3523 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 3524 * the used lanes of the DDI. 3525 */ 3526 if (intel_phy_is_combo(dev_priv, phy)) { 3527 bool lane_reversal = 3528 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 3529 3530 intel_combo_phy_power_up_lanes(dev_priv, phy, false, 3531 crtc_state->lane_count, 3532 lane_reversal); 3533 } 3534 3535 /* 3536 * 7.g Configure and enable DDI_BUF_CTL 3537 * 7.h Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout 3538 * after 500 us. 3539 * 3540 * We only configure what the register value will be here. Actual 3541 * enabling happens during link training farther down. 3542 */ 3543 intel_ddi_init_dp_buf_reg(encoder); 3544 3545 if (!is_mst) 3546 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 3547 3548 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); 3549 /* 3550 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 3551 * in the FEC_CONFIGURATION register to 1 before initiating link 3552 * training 3553 */ 3554 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 3555 3556 /* 3557 * 7.i Follow DisplayPort specification training sequence (see notes for 3558 * failure handling) 3559 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 3560 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 3561 * (timeout after 800 us) 3562 */ 3563 intel_dp_start_link_train(intel_dp); 3564 3565 /* 7.k Set DP_TP_CTL link training to Normal */ 3566 if (!is_trans_port_sync_mode(crtc_state)) 3567 intel_dp_stop_link_train(intel_dp); 3568 3569 /* 3570 * TODO: enable clock gating 3571 * 3572 * It is not written in DP enabling sequence but "PHY Clockgating 3573 * programming" states that clock gating should be enabled after the 3574 * link training but doing so causes all the following trainings to fail 3575 * so not enabling it for now. 3576 */ 3577 3578 /* 7.l Configure and enable FEC if needed */ 3579 intel_ddi_enable_fec(encoder, crtc_state); 3580 intel_dsc_enable(encoder, crtc_state); 3581 } 3582 3583 static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder, 3584 const struct intel_crtc_state *crtc_state, 3585 const struct drm_connector_state *conn_state) 3586 { 3587 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 3588 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3589 enum port port = encoder->port; 3590 enum phy phy = intel_port_to_phy(dev_priv, port); 3591 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 3592 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 3593 int level = intel_ddi_dp_level(intel_dp); 3594 3595 WARN_ON(is_mst && (port == PORT_A || port == PORT_E)); 3596 3597 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, 3598 crtc_state->lane_count, is_mst); 3599 3600 intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port); 3601 intel_dp->regs.dp_tp_status = DP_TP_STATUS(port); 3602 3603 intel_edp_panel_on(intel_dp); 3604 3605 intel_ddi_clk_select(encoder, crtc_state); 3606 3607 if (!intel_phy_is_tc(dev_priv, phy) || 3608 dig_port->tc_mode != TC_PORT_TBT_ALT) 3609 intel_display_power_get(dev_priv, 3610 dig_port->ddi_io_power_domain); 3611 3612 icl_program_mg_dp_mode(dig_port, crtc_state); 3613 icl_phy_set_clock_gating(dig_port, false); 3614 3615 if (INTEL_GEN(dev_priv) >= 11) 3616 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, 3617 level, encoder->type); 3618 else if (IS_CANNONLAKE(dev_priv)) 3619 cnl_ddi_vswing_sequence(encoder, level, encoder->type); 3620 else if (IS_GEN9_LP(dev_priv)) 3621 bxt_ddi_vswing_sequence(encoder, level, encoder->type); 3622 else 3623 intel_prepare_dp_ddi_buffers(encoder, crtc_state); 3624 3625 if (intel_phy_is_combo(dev_priv, phy)) { 3626 bool lane_reversal = 3627 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 3628 3629 intel_combo_phy_power_up_lanes(dev_priv, phy, false, 3630 crtc_state->lane_count, 3631 lane_reversal); 3632 } 3633 3634 intel_ddi_init_dp_buf_reg(encoder); 3635 if (!is_mst) 3636 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 3637 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, 3638 true); 3639 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 3640 intel_dp_start_link_train(intel_dp); 3641 if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) && 3642 !is_trans_port_sync_mode(crtc_state)) 3643 intel_dp_stop_link_train(intel_dp); 3644 3645 intel_ddi_enable_fec(encoder, crtc_state); 3646 3647 icl_phy_set_clock_gating(dig_port, true); 3648 3649 if (!is_mst) 3650 intel_ddi_enable_pipe_clock(crtc_state); 3651 3652 intel_dsc_enable(encoder, crtc_state); 3653 } 3654 3655 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, 3656 const struct intel_crtc_state *crtc_state, 3657 const struct drm_connector_state *conn_state) 3658 { 3659 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3660 3661 if (INTEL_GEN(dev_priv) >= 12) 3662 tgl_ddi_pre_enable_dp(encoder, crtc_state, conn_state); 3663 else 3664 hsw_ddi_pre_enable_dp(encoder, crtc_state, conn_state); 3665 3666 /* MST will call a setting of MSA after an allocating of Virtual Channel 3667 * from MST encoder pre_enable callback. 3668 */ 3669 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 3670 intel_ddi_set_dp_msa(crtc_state, conn_state); 3671 } 3672 3673 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder, 3674 const struct intel_crtc_state *crtc_state, 3675 const struct drm_connector_state *conn_state) 3676 { 3677 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); 3678 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 3679 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3680 enum port port = encoder->port; 3681 int level = intel_ddi_hdmi_level(dev_priv, port); 3682 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 3683 3684 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 3685 intel_ddi_clk_select(encoder, crtc_state); 3686 3687 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); 3688 3689 icl_program_mg_dp_mode(dig_port, crtc_state); 3690 icl_phy_set_clock_gating(dig_port, false); 3691 3692 if (INTEL_GEN(dev_priv) >= 12) 3693 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, 3694 level, INTEL_OUTPUT_HDMI); 3695 else if (INTEL_GEN(dev_priv) == 11) 3696 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, 3697 level, INTEL_OUTPUT_HDMI); 3698 else if (IS_CANNONLAKE(dev_priv)) 3699 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI); 3700 else if (IS_GEN9_LP(dev_priv)) 3701 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI); 3702 else 3703 intel_prepare_hdmi_ddi_buffers(encoder, level); 3704 3705 icl_phy_set_clock_gating(dig_port, true); 3706 3707 if (IS_GEN9_BC(dev_priv)) 3708 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI); 3709 3710 intel_ddi_enable_pipe_clock(crtc_state); 3711 3712 intel_dig_port->set_infoframes(encoder, 3713 crtc_state->has_infoframe, 3714 crtc_state, conn_state); 3715 } 3716 3717 static void intel_ddi_pre_enable(struct intel_encoder *encoder, 3718 const struct intel_crtc_state *crtc_state, 3719 const struct drm_connector_state *conn_state) 3720 { 3721 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3722 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3723 enum pipe pipe = crtc->pipe; 3724 3725 /* 3726 * When called from DP MST code: 3727 * - conn_state will be NULL 3728 * - encoder will be the main encoder (ie. mst->primary) 3729 * - the main connector associated with this port 3730 * won't be active or linked to a crtc 3731 * - crtc_state will be the state of the first stream to 3732 * be activated on this port, and it may not be the same 3733 * stream that will be deactivated last, but each stream 3734 * should have a state that is identical when it comes to 3735 * the DP link parameteres 3736 */ 3737 3738 WARN_ON(crtc_state->has_pch_encoder); 3739 3740 if (INTEL_GEN(dev_priv) >= 11) 3741 icl_map_plls_to_ports(encoder, crtc_state); 3742 3743 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 3744 3745 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 3746 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state); 3747 } else { 3748 struct intel_lspcon *lspcon = 3749 enc_to_intel_lspcon(&encoder->base); 3750 3751 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state); 3752 if (lspcon->active) { 3753 struct intel_digital_port *dig_port = 3754 enc_to_dig_port(&encoder->base); 3755 3756 dig_port->set_infoframes(encoder, 3757 crtc_state->has_infoframe, 3758 crtc_state, conn_state); 3759 } 3760 } 3761 } 3762 3763 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 3764 const struct intel_crtc_state *crtc_state) 3765 { 3766 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3767 enum port port = encoder->port; 3768 bool wait = false; 3769 u32 val; 3770 3771 val = I915_READ(DDI_BUF_CTL(port)); 3772 if (val & DDI_BUF_CTL_ENABLE) { 3773 val &= ~DDI_BUF_CTL_ENABLE; 3774 I915_WRITE(DDI_BUF_CTL(port), val); 3775 wait = true; 3776 } 3777 3778 if (intel_crtc_has_dp_encoder(crtc_state)) { 3779 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 3780 3781 val = I915_READ(intel_dp->regs.dp_tp_ctl); 3782 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 3783 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 3784 I915_WRITE(intel_dp->regs.dp_tp_ctl, val); 3785 } 3786 3787 /* Disable FEC in DP Sink */ 3788 intel_ddi_disable_fec_state(encoder, crtc_state); 3789 3790 if (wait) 3791 intel_wait_ddi_buf_idle(dev_priv, port); 3792 } 3793 3794 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder, 3795 const struct intel_crtc_state *old_crtc_state, 3796 const struct drm_connector_state *old_conn_state) 3797 { 3798 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3799 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 3800 struct intel_dp *intel_dp = &dig_port->dp; 3801 bool is_mst = intel_crtc_has_type(old_crtc_state, 3802 INTEL_OUTPUT_DP_MST); 3803 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3804 3805 /* 3806 * Power down sink before disabling the port, otherwise we end 3807 * up getting interrupts from the sink on detecting link loss. 3808 */ 3809 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 3810 3811 if (INTEL_GEN(dev_priv) < 12 && !is_mst) 3812 intel_ddi_disable_pipe_clock(old_crtc_state); 3813 3814 intel_disable_ddi_buf(encoder, old_crtc_state); 3815 3816 /* 3817 * From TGL spec: "If single stream or multi-stream master transcoder: 3818 * Configure Transcoder Clock select to direct no clock to the 3819 * transcoder" 3820 */ 3821 if (INTEL_GEN(dev_priv) >= 12) 3822 intel_ddi_disable_pipe_clock(old_crtc_state); 3823 3824 intel_edp_panel_vdd_on(intel_dp); 3825 intel_edp_panel_off(intel_dp); 3826 3827 if (!intel_phy_is_tc(dev_priv, phy) || 3828 dig_port->tc_mode != TC_PORT_TBT_ALT) 3829 intel_display_power_put_unchecked(dev_priv, 3830 dig_port->ddi_io_power_domain); 3831 3832 intel_ddi_clk_disable(encoder); 3833 tgl_clear_psr2_transcoder_exitline(old_crtc_state); 3834 } 3835 3836 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder, 3837 const struct intel_crtc_state *old_crtc_state, 3838 const struct drm_connector_state *old_conn_state) 3839 { 3840 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3841 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 3842 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3843 3844 dig_port->set_infoframes(encoder, false, 3845 old_crtc_state, old_conn_state); 3846 3847 intel_ddi_disable_pipe_clock(old_crtc_state); 3848 3849 intel_disable_ddi_buf(encoder, old_crtc_state); 3850 3851 intel_display_power_put_unchecked(dev_priv, 3852 dig_port->ddi_io_power_domain); 3853 3854 intel_ddi_clk_disable(encoder); 3855 3856 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3857 } 3858 3859 static void icl_disable_transcoder_port_sync(const struct intel_crtc_state *old_crtc_state) 3860 { 3861 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 3862 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3863 i915_reg_t reg; 3864 u32 trans_ddi_func_ctl2_val; 3865 3866 if (old_crtc_state->master_transcoder == INVALID_TRANSCODER) 3867 return; 3868 3869 DRM_DEBUG_KMS("Disabling Transcoder Port Sync on Slave Transcoder %s\n", 3870 transcoder_name(old_crtc_state->cpu_transcoder)); 3871 3872 reg = TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder); 3873 trans_ddi_func_ctl2_val = ~(PORT_SYNC_MODE_ENABLE | 3874 PORT_SYNC_MODE_MASTER_SELECT_MASK); 3875 I915_WRITE(reg, trans_ddi_func_ctl2_val); 3876 } 3877 3878 static void intel_ddi_post_disable(struct intel_encoder *encoder, 3879 const struct intel_crtc_state *old_crtc_state, 3880 const struct drm_connector_state *old_conn_state) 3881 { 3882 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3883 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 3884 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3885 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 3886 3887 intel_crtc_vblank_off(old_crtc_state); 3888 3889 intel_disable_pipe(old_crtc_state); 3890 3891 if (INTEL_GEN(dev_priv) >= 11) 3892 icl_disable_transcoder_port_sync(old_crtc_state); 3893 3894 intel_ddi_disable_transcoder_func(old_crtc_state); 3895 3896 intel_dsc_disable(old_crtc_state); 3897 3898 if (INTEL_GEN(dev_priv) >= 9) 3899 skylake_scaler_disable(old_crtc_state); 3900 else 3901 ironlake_pfit_disable(old_crtc_state); 3902 3903 /* 3904 * When called from DP MST code: 3905 * - old_conn_state will be NULL 3906 * - encoder will be the main encoder (ie. mst->primary) 3907 * - the main connector associated with this port 3908 * won't be active or linked to a crtc 3909 * - old_crtc_state will be the state of the last stream to 3910 * be deactivated on this port, and it may not be the same 3911 * stream that was activated last, but each stream 3912 * should have a state that is identical when it comes to 3913 * the DP link parameteres 3914 */ 3915 3916 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3917 intel_ddi_post_disable_hdmi(encoder, 3918 old_crtc_state, old_conn_state); 3919 else 3920 intel_ddi_post_disable_dp(encoder, 3921 old_crtc_state, old_conn_state); 3922 3923 if (INTEL_GEN(dev_priv) >= 11) 3924 icl_unmap_plls_to_ports(encoder); 3925 3926 if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port) 3927 intel_display_power_put_unchecked(dev_priv, 3928 intel_ddi_main_link_aux_domain(dig_port)); 3929 3930 if (is_tc_port) 3931 intel_tc_port_put_link(dig_port); 3932 } 3933 3934 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder, 3935 const struct intel_crtc_state *old_crtc_state, 3936 const struct drm_connector_state *old_conn_state) 3937 { 3938 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3939 u32 val; 3940 3941 /* 3942 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable) 3943 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN, 3944 * step 13 is the correct place for it. Step 18 is where it was 3945 * originally before the BUN. 3946 */ 3947 val = I915_READ(FDI_RX_CTL(PIPE_A)); 3948 val &= ~FDI_RX_ENABLE; 3949 I915_WRITE(FDI_RX_CTL(PIPE_A), val); 3950 3951 intel_disable_ddi_buf(encoder, old_crtc_state); 3952 intel_ddi_clk_disable(encoder); 3953 3954 val = I915_READ(FDI_RX_MISC(PIPE_A)); 3955 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 3956 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 3957 I915_WRITE(FDI_RX_MISC(PIPE_A), val); 3958 3959 val = I915_READ(FDI_RX_CTL(PIPE_A)); 3960 val &= ~FDI_PCDCLK; 3961 I915_WRITE(FDI_RX_CTL(PIPE_A), val); 3962 3963 val = I915_READ(FDI_RX_CTL(PIPE_A)); 3964 val &= ~FDI_RX_PLL_ENABLE; 3965 I915_WRITE(FDI_RX_CTL(PIPE_A), val); 3966 } 3967 3968 static void intel_enable_ddi_dp(struct intel_encoder *encoder, 3969 const struct intel_crtc_state *crtc_state, 3970 const struct drm_connector_state *conn_state) 3971 { 3972 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3973 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 3974 enum port port = encoder->port; 3975 3976 if (port == PORT_A && INTEL_GEN(dev_priv) < 9) 3977 intel_dp_stop_link_train(intel_dp); 3978 3979 intel_edp_backlight_on(crtc_state, conn_state); 3980 intel_psr_enable(intel_dp, crtc_state); 3981 intel_dp_vsc_enable(intel_dp, crtc_state, conn_state); 3982 intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state); 3983 intel_edp_drrs_enable(intel_dp, crtc_state); 3984 3985 if (crtc_state->has_audio) 3986 intel_audio_codec_enable(encoder, crtc_state, conn_state); 3987 } 3988 3989 static i915_reg_t 3990 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 3991 enum port port) 3992 { 3993 static const enum transcoder trans[] = { 3994 [PORT_A] = TRANSCODER_EDP, 3995 [PORT_B] = TRANSCODER_A, 3996 [PORT_C] = TRANSCODER_B, 3997 [PORT_D] = TRANSCODER_C, 3998 [PORT_E] = TRANSCODER_A, 3999 }; 4000 4001 WARN_ON(INTEL_GEN(dev_priv) < 9); 4002 4003 if (WARN_ON(port < PORT_A || port > PORT_E)) 4004 port = PORT_A; 4005 4006 return CHICKEN_TRANS(trans[port]); 4007 } 4008 4009 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder, 4010 const struct intel_crtc_state *crtc_state, 4011 const struct drm_connector_state *conn_state) 4012 { 4013 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4014 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 4015 struct drm_connector *connector = conn_state->connector; 4016 enum port port = encoder->port; 4017 4018 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 4019 crtc_state->hdmi_high_tmds_clock_ratio, 4020 crtc_state->hdmi_scrambling)) 4021 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 4022 connector->base.id, connector->name); 4023 4024 /* Display WA #1143: skl,kbl,cfl */ 4025 if (IS_GEN9_BC(dev_priv)) { 4026 /* 4027 * For some reason these chicken bits have been 4028 * stuffed into a transcoder register, event though 4029 * the bits affect a specific DDI port rather than 4030 * a specific transcoder. 4031 */ 4032 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 4033 u32 val; 4034 4035 val = I915_READ(reg); 4036 4037 if (port == PORT_E) 4038 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 4039 DDIE_TRAINING_OVERRIDE_VALUE; 4040 else 4041 val |= DDI_TRAINING_OVERRIDE_ENABLE | 4042 DDI_TRAINING_OVERRIDE_VALUE; 4043 4044 I915_WRITE(reg, val); 4045 POSTING_READ(reg); 4046 4047 udelay(1); 4048 4049 if (port == PORT_E) 4050 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 4051 DDIE_TRAINING_OVERRIDE_VALUE); 4052 else 4053 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 4054 DDI_TRAINING_OVERRIDE_VALUE); 4055 4056 I915_WRITE(reg, val); 4057 } 4058 4059 /* In HDMI/DVI mode, the port width, and swing/emphasis values 4060 * are ignored so nothing special needs to be done besides 4061 * enabling the port. 4062 */ 4063 I915_WRITE(DDI_BUF_CTL(port), 4064 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE); 4065 4066 if (crtc_state->has_audio) 4067 intel_audio_codec_enable(encoder, crtc_state, conn_state); 4068 } 4069 4070 static void intel_enable_ddi(struct intel_encoder *encoder, 4071 const struct intel_crtc_state *crtc_state, 4072 const struct drm_connector_state *conn_state) 4073 { 4074 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 4075 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state); 4076 else 4077 intel_enable_ddi_dp(encoder, crtc_state, conn_state); 4078 4079 /* Enable hdcp if it's desired */ 4080 if (conn_state->content_protection == 4081 DRM_MODE_CONTENT_PROTECTION_DESIRED) 4082 intel_hdcp_enable(to_intel_connector(conn_state->connector), 4083 crtc_state->cpu_transcoder, 4084 (u8)conn_state->hdcp_content_type); 4085 } 4086 4087 static void intel_disable_ddi_dp(struct intel_encoder *encoder, 4088 const struct intel_crtc_state *old_crtc_state, 4089 const struct drm_connector_state *old_conn_state) 4090 { 4091 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 4092 4093 intel_dp->link_trained = false; 4094 4095 if (old_crtc_state->has_audio) 4096 intel_audio_codec_disable(encoder, 4097 old_crtc_state, old_conn_state); 4098 4099 intel_edp_drrs_disable(intel_dp, old_crtc_state); 4100 intel_psr_disable(intel_dp, old_crtc_state); 4101 intel_edp_backlight_off(old_conn_state); 4102 /* Disable the decompression in DP Sink */ 4103 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, 4104 false); 4105 } 4106 4107 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder, 4108 const struct intel_crtc_state *old_crtc_state, 4109 const struct drm_connector_state *old_conn_state) 4110 { 4111 struct drm_connector *connector = old_conn_state->connector; 4112 4113 if (old_crtc_state->has_audio) 4114 intel_audio_codec_disable(encoder, 4115 old_crtc_state, old_conn_state); 4116 4117 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 4118 false, false)) 4119 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 4120 connector->base.id, connector->name); 4121 } 4122 4123 static void intel_disable_ddi(struct intel_encoder *encoder, 4124 const struct intel_crtc_state *old_crtc_state, 4125 const struct drm_connector_state *old_conn_state) 4126 { 4127 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 4128 4129 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 4130 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state); 4131 else 4132 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state); 4133 } 4134 4135 static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder, 4136 const struct intel_crtc_state *crtc_state, 4137 const struct drm_connector_state *conn_state) 4138 { 4139 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 4140 4141 intel_ddi_set_dp_msa(crtc_state, conn_state); 4142 4143 intel_psr_update(intel_dp, crtc_state); 4144 intel_edp_drrs_enable(intel_dp, crtc_state); 4145 4146 intel_panel_update_backlight(encoder, crtc_state, conn_state); 4147 } 4148 4149 static void intel_ddi_update_pipe(struct intel_encoder *encoder, 4150 const struct intel_crtc_state *crtc_state, 4151 const struct drm_connector_state *conn_state) 4152 { 4153 struct intel_connector *connector = 4154 to_intel_connector(conn_state->connector); 4155 struct intel_hdcp *hdcp = &connector->hdcp; 4156 bool content_protection_type_changed = 4157 (conn_state->hdcp_content_type != hdcp->content_type && 4158 conn_state->content_protection != 4159 DRM_MODE_CONTENT_PROTECTION_UNDESIRED); 4160 4161 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 4162 intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state); 4163 4164 /* 4165 * During the HDCP encryption session if Type change is requested, 4166 * disable the HDCP and reenable it with new TYPE value. 4167 */ 4168 if (conn_state->content_protection == 4169 DRM_MODE_CONTENT_PROTECTION_UNDESIRED || 4170 content_protection_type_changed) 4171 intel_hdcp_disable(connector); 4172 4173 /* 4174 * Mark the hdcp state as DESIRED after the hdcp disable of type 4175 * change procedure. 4176 */ 4177 if (content_protection_type_changed) { 4178 mutex_lock(&hdcp->mutex); 4179 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; 4180 schedule_work(&hdcp->prop_work); 4181 mutex_unlock(&hdcp->mutex); 4182 } 4183 4184 if (conn_state->content_protection == 4185 DRM_MODE_CONTENT_PROTECTION_DESIRED || 4186 content_protection_type_changed) 4187 intel_hdcp_enable(connector, 4188 crtc_state->cpu_transcoder, 4189 (u8)conn_state->hdcp_content_type); 4190 } 4191 4192 static void 4193 intel_ddi_update_prepare(struct intel_atomic_state *state, 4194 struct intel_encoder *encoder, 4195 struct intel_crtc *crtc) 4196 { 4197 struct intel_crtc_state *crtc_state = 4198 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL; 4199 int required_lanes = crtc_state ? crtc_state->lane_count : 1; 4200 4201 WARN_ON(crtc && crtc->active); 4202 4203 intel_tc_port_get_link(enc_to_dig_port(&encoder->base), required_lanes); 4204 if (crtc_state && crtc_state->hw.active) 4205 intel_update_active_dpll(state, crtc, encoder); 4206 } 4207 4208 static void 4209 intel_ddi_update_complete(struct intel_atomic_state *state, 4210 struct intel_encoder *encoder, 4211 struct intel_crtc *crtc) 4212 { 4213 intel_tc_port_put_link(enc_to_dig_port(&encoder->base)); 4214 } 4215 4216 static void 4217 intel_ddi_pre_pll_enable(struct intel_encoder *encoder, 4218 const struct intel_crtc_state *crtc_state, 4219 const struct drm_connector_state *conn_state) 4220 { 4221 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4222 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 4223 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 4224 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 4225 4226 if (is_tc_port) 4227 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 4228 4229 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) 4230 intel_display_power_get(dev_priv, 4231 intel_ddi_main_link_aux_domain(dig_port)); 4232 4233 if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT) 4234 /* 4235 * Program the lane count for static/dynamic connections on 4236 * Type-C ports. Skip this step for TBT. 4237 */ 4238 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 4239 else if (IS_GEN9_LP(dev_priv)) 4240 bxt_ddi_phy_set_lane_optim_mask(encoder, 4241 crtc_state->lane_lat_optim_mask); 4242 } 4243 4244 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) 4245 { 4246 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 4247 struct drm_i915_private *dev_priv = 4248 to_i915(intel_dig_port->base.base.dev); 4249 enum port port = intel_dig_port->base.port; 4250 u32 dp_tp_ctl, ddi_buf_ctl; 4251 bool wait = false; 4252 4253 dp_tp_ctl = I915_READ(intel_dp->regs.dp_tp_ctl); 4254 4255 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 4256 ddi_buf_ctl = I915_READ(DDI_BUF_CTL(port)); 4257 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 4258 I915_WRITE(DDI_BUF_CTL(port), 4259 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 4260 wait = true; 4261 } 4262 4263 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 4264 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1; 4265 I915_WRITE(intel_dp->regs.dp_tp_ctl, dp_tp_ctl); 4266 POSTING_READ(intel_dp->regs.dp_tp_ctl); 4267 4268 if (wait) 4269 intel_wait_ddi_buf_idle(dev_priv, port); 4270 } 4271 4272 dp_tp_ctl = DP_TP_CTL_ENABLE | 4273 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; 4274 if (intel_dp->link_mst) 4275 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 4276 else { 4277 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 4278 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 4279 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4280 } 4281 I915_WRITE(intel_dp->regs.dp_tp_ctl, dp_tp_ctl); 4282 POSTING_READ(intel_dp->regs.dp_tp_ctl); 4283 4284 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 4285 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); 4286 POSTING_READ(DDI_BUF_CTL(port)); 4287 4288 udelay(600); 4289 } 4290 4291 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 4292 enum transcoder cpu_transcoder) 4293 { 4294 if (cpu_transcoder == TRANSCODER_EDP) 4295 return false; 4296 4297 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) 4298 return false; 4299 4300 return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) & 4301 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 4302 } 4303 4304 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, 4305 struct intel_crtc_state *crtc_state) 4306 { 4307 if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000) 4308 crtc_state->min_voltage_level = 1; 4309 else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000) 4310 crtc_state->min_voltage_level = 2; 4311 } 4312 4313 void intel_ddi_get_config(struct intel_encoder *encoder, 4314 struct intel_crtc_state *pipe_config) 4315 { 4316 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4317 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); 4318 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4319 u32 temp, flags = 0; 4320 4321 /* XXX: DSI transcoder paranoia */ 4322 if (WARN_ON(transcoder_is_dsi(cpu_transcoder))) 4323 return; 4324 4325 intel_dsc_get_config(encoder, pipe_config); 4326 4327 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 4328 if (temp & TRANS_DDI_PHSYNC) 4329 flags |= DRM_MODE_FLAG_PHSYNC; 4330 else 4331 flags |= DRM_MODE_FLAG_NHSYNC; 4332 if (temp & TRANS_DDI_PVSYNC) 4333 flags |= DRM_MODE_FLAG_PVSYNC; 4334 else 4335 flags |= DRM_MODE_FLAG_NVSYNC; 4336 4337 pipe_config->hw.adjusted_mode.flags |= flags; 4338 4339 switch (temp & TRANS_DDI_BPC_MASK) { 4340 case TRANS_DDI_BPC_6: 4341 pipe_config->pipe_bpp = 18; 4342 break; 4343 case TRANS_DDI_BPC_8: 4344 pipe_config->pipe_bpp = 24; 4345 break; 4346 case TRANS_DDI_BPC_10: 4347 pipe_config->pipe_bpp = 30; 4348 break; 4349 case TRANS_DDI_BPC_12: 4350 pipe_config->pipe_bpp = 36; 4351 break; 4352 default: 4353 break; 4354 } 4355 4356 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 4357 case TRANS_DDI_MODE_SELECT_HDMI: 4358 pipe_config->has_hdmi_sink = true; 4359 4360 pipe_config->infoframes.enable |= 4361 intel_hdmi_infoframes_enabled(encoder, pipe_config); 4362 4363 if (pipe_config->infoframes.enable) 4364 pipe_config->has_infoframe = true; 4365 4366 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 4367 pipe_config->hdmi_scrambling = true; 4368 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 4369 pipe_config->hdmi_high_tmds_clock_ratio = true; 4370 /* fall through */ 4371 case TRANS_DDI_MODE_SELECT_DVI: 4372 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 4373 pipe_config->lane_count = 4; 4374 break; 4375 case TRANS_DDI_MODE_SELECT_FDI: 4376 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 4377 break; 4378 case TRANS_DDI_MODE_SELECT_DP_SST: 4379 if (encoder->type == INTEL_OUTPUT_EDP) 4380 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 4381 else 4382 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 4383 pipe_config->lane_count = 4384 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4385 intel_dp_get_m_n(intel_crtc, pipe_config); 4386 4387 if (INTEL_GEN(dev_priv) >= 11) { 4388 i915_reg_t dp_tp_ctl; 4389 4390 if (IS_GEN(dev_priv, 11)) 4391 dp_tp_ctl = DP_TP_CTL(encoder->port); 4392 else 4393 dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder); 4394 4395 pipe_config->fec_enable = 4396 I915_READ(dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE; 4397 4398 DRM_DEBUG_KMS("[ENCODER:%d:%s] Fec status: %u\n", 4399 encoder->base.base.id, encoder->base.name, 4400 pipe_config->fec_enable); 4401 } 4402 4403 break; 4404 case TRANS_DDI_MODE_SELECT_DP_MST: 4405 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 4406 pipe_config->lane_count = 4407 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4408 intel_dp_get_m_n(intel_crtc, pipe_config); 4409 break; 4410 default: 4411 break; 4412 } 4413 4414 if (encoder->type == INTEL_OUTPUT_EDP) 4415 tgl_dc3co_exitline_get_config(pipe_config); 4416 4417 pipe_config->has_audio = 4418 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 4419 4420 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp && 4421 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { 4422 /* 4423 * This is a big fat ugly hack. 4424 * 4425 * Some machines in UEFI boot mode provide us a VBT that has 18 4426 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 4427 * unknown we fail to light up. Yet the same BIOS boots up with 4428 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 4429 * max, not what it tells us to use. 4430 * 4431 * Note: This will still be broken if the eDP panel is not lit 4432 * up by the BIOS, and thus we can't get the mode at module 4433 * load. 4434 */ 4435 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 4436 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); 4437 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; 4438 } 4439 4440 intel_ddi_clock_get(encoder, pipe_config); 4441 4442 if (IS_GEN9_LP(dev_priv)) 4443 pipe_config->lane_lat_optim_mask = 4444 bxt_ddi_phy_get_lane_lat_optim_mask(encoder); 4445 4446 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 4447 4448 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 4449 4450 intel_read_infoframe(encoder, pipe_config, 4451 HDMI_INFOFRAME_TYPE_AVI, 4452 &pipe_config->infoframes.avi); 4453 intel_read_infoframe(encoder, pipe_config, 4454 HDMI_INFOFRAME_TYPE_SPD, 4455 &pipe_config->infoframes.spd); 4456 intel_read_infoframe(encoder, pipe_config, 4457 HDMI_INFOFRAME_TYPE_VENDOR, 4458 &pipe_config->infoframes.hdmi); 4459 intel_read_infoframe(encoder, pipe_config, 4460 HDMI_INFOFRAME_TYPE_DRM, 4461 &pipe_config->infoframes.drm); 4462 } 4463 4464 static enum intel_output_type 4465 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4466 struct intel_crtc_state *crtc_state, 4467 struct drm_connector_state *conn_state) 4468 { 4469 switch (conn_state->connector->connector_type) { 4470 case DRM_MODE_CONNECTOR_HDMIA: 4471 return INTEL_OUTPUT_HDMI; 4472 case DRM_MODE_CONNECTOR_eDP: 4473 return INTEL_OUTPUT_EDP; 4474 case DRM_MODE_CONNECTOR_DisplayPort: 4475 return INTEL_OUTPUT_DP; 4476 default: 4477 MISSING_CASE(conn_state->connector->connector_type); 4478 return INTEL_OUTPUT_UNUSED; 4479 } 4480 } 4481 4482 static int intel_ddi_compute_config(struct intel_encoder *encoder, 4483 struct intel_crtc_state *pipe_config, 4484 struct drm_connector_state *conn_state) 4485 { 4486 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4487 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4488 enum port port = encoder->port; 4489 int ret; 4490 4491 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) 4492 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4493 4494 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4495 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4496 } else { 4497 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 4498 tgl_dc3co_exitline_compute_config(encoder, pipe_config); 4499 } 4500 4501 if (ret) 4502 return ret; 4503 4504 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 4505 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4506 pipe_config->pch_pfit.force_thru = 4507 pipe_config->pch_pfit.enabled || 4508 pipe_config->crc_enabled; 4509 4510 if (IS_GEN9_LP(dev_priv)) 4511 pipe_config->lane_lat_optim_mask = 4512 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4513 4514 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 4515 4516 return 0; 4517 } 4518 4519 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4520 { 4521 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4522 4523 intel_dp_encoder_flush_work(encoder); 4524 4525 drm_encoder_cleanup(encoder); 4526 kfree(dig_port); 4527 } 4528 4529 static const struct drm_encoder_funcs intel_ddi_funcs = { 4530 .reset = intel_dp_encoder_reset, 4531 .destroy = intel_ddi_encoder_destroy, 4532 }; 4533 4534 static struct intel_connector * 4535 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) 4536 { 4537 struct intel_connector *connector; 4538 enum port port = intel_dig_port->base.port; 4539 4540 connector = intel_connector_alloc(); 4541 if (!connector) 4542 return NULL; 4543 4544 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); 4545 intel_dig_port->dp.prepare_link_retrain = 4546 intel_ddi_prepare_link_retrain; 4547 4548 if (!intel_dp_init_connector(intel_dig_port, connector)) { 4549 kfree(connector); 4550 return NULL; 4551 } 4552 4553 return connector; 4554 } 4555 4556 static int modeset_pipe(struct drm_crtc *crtc, 4557 struct drm_modeset_acquire_ctx *ctx) 4558 { 4559 struct drm_atomic_state *state; 4560 struct drm_crtc_state *crtc_state; 4561 int ret; 4562 4563 state = drm_atomic_state_alloc(crtc->dev); 4564 if (!state) 4565 return -ENOMEM; 4566 4567 state->acquire_ctx = ctx; 4568 4569 crtc_state = drm_atomic_get_crtc_state(state, crtc); 4570 if (IS_ERR(crtc_state)) { 4571 ret = PTR_ERR(crtc_state); 4572 goto out; 4573 } 4574 4575 crtc_state->connectors_changed = true; 4576 4577 ret = drm_atomic_commit(state); 4578 out: 4579 drm_atomic_state_put(state); 4580 4581 return ret; 4582 } 4583 4584 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4585 struct drm_modeset_acquire_ctx *ctx) 4586 { 4587 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4588 struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base); 4589 struct intel_connector *connector = hdmi->attached_connector; 4590 struct i2c_adapter *adapter = 4591 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 4592 struct drm_connector_state *conn_state; 4593 struct intel_crtc_state *crtc_state; 4594 struct intel_crtc *crtc; 4595 u8 config; 4596 int ret; 4597 4598 if (!connector || connector->base.status != connector_status_connected) 4599 return 0; 4600 4601 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 4602 ctx); 4603 if (ret) 4604 return ret; 4605 4606 conn_state = connector->base.state; 4607 4608 crtc = to_intel_crtc(conn_state->crtc); 4609 if (!crtc) 4610 return 0; 4611 4612 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4613 if (ret) 4614 return ret; 4615 4616 crtc_state = to_intel_crtc_state(crtc->base.state); 4617 4618 WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4619 4620 if (!crtc_state->hw.active) 4621 return 0; 4622 4623 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4624 !crtc_state->hdmi_scrambling) 4625 return 0; 4626 4627 if (conn_state->commit && 4628 !try_wait_for_completion(&conn_state->commit->hw_done)) 4629 return 0; 4630 4631 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 4632 if (ret < 0) { 4633 DRM_ERROR("Failed to read TMDS config: %d\n", ret); 4634 return 0; 4635 } 4636 4637 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4638 crtc_state->hdmi_high_tmds_clock_ratio && 4639 !!(config & SCDC_SCRAMBLING_ENABLE) == 4640 crtc_state->hdmi_scrambling) 4641 return 0; 4642 4643 /* 4644 * HDMI 2.0 says that one should not send scrambled data 4645 * prior to configuring the sink scrambling, and that 4646 * TMDS clock/data transmission should be suspended when 4647 * changing the TMDS clock rate in the sink. So let's 4648 * just do a full modeset here, even though some sinks 4649 * would be perfectly happy if were to just reconfigure 4650 * the SCDC settings on the fly. 4651 */ 4652 return modeset_pipe(&crtc->base, ctx); 4653 } 4654 4655 static enum intel_hotplug_state 4656 intel_ddi_hotplug(struct intel_encoder *encoder, 4657 struct intel_connector *connector, 4658 bool irq_received) 4659 { 4660 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 4661 struct drm_modeset_acquire_ctx ctx; 4662 enum intel_hotplug_state state; 4663 int ret; 4664 4665 state = intel_encoder_hotplug(encoder, connector, irq_received); 4666 4667 drm_modeset_acquire_init(&ctx, 0); 4668 4669 for (;;) { 4670 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) 4671 ret = intel_hdmi_reset_link(encoder, &ctx); 4672 else 4673 ret = intel_dp_retrain_link(encoder, &ctx); 4674 4675 if (ret == -EDEADLK) { 4676 drm_modeset_backoff(&ctx); 4677 continue; 4678 } 4679 4680 break; 4681 } 4682 4683 drm_modeset_drop_locks(&ctx); 4684 drm_modeset_acquire_fini(&ctx); 4685 WARN(ret, "Acquiring modeset locks failed with %i\n", ret); 4686 4687 /* 4688 * Unpowered type-c dongles can take some time to boot and be 4689 * responsible, so here giving some time to those dongles to power up 4690 * and then retrying the probe. 4691 * 4692 * On many platforms the HDMI live state signal is known to be 4693 * unreliable, so we can't use it to detect if a sink is connected or 4694 * not. Instead we detect if it's connected based on whether we can 4695 * read the EDID or not. That in turn has a problem during disconnect, 4696 * since the HPD interrupt may be raised before the DDC lines get 4697 * disconnected (due to how the required length of DDC vs. HPD 4698 * connector pins are specified) and so we'll still be able to get a 4699 * valid EDID. To solve this schedule another detection cycle if this 4700 * time around we didn't detect any change in the sink's connection 4701 * status. 4702 */ 4703 if (state == INTEL_HOTPLUG_UNCHANGED && irq_received && 4704 !dig_port->dp.is_mst) 4705 state = INTEL_HOTPLUG_RETRY; 4706 4707 return state; 4708 } 4709 4710 static struct intel_connector * 4711 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) 4712 { 4713 struct intel_connector *connector; 4714 enum port port = intel_dig_port->base.port; 4715 4716 connector = intel_connector_alloc(); 4717 if (!connector) 4718 return NULL; 4719 4720 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4721 intel_hdmi_init_connector(intel_dig_port, connector); 4722 4723 return connector; 4724 } 4725 4726 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport) 4727 { 4728 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); 4729 4730 if (dport->base.port != PORT_A) 4731 return false; 4732 4733 if (dport->saved_port_bits & DDI_A_4_LANES) 4734 return false; 4735 4736 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4737 * supported configuration 4738 */ 4739 if (IS_GEN9_LP(dev_priv)) 4740 return true; 4741 4742 /* Cannonlake: Most of SKUs don't support DDI_E, and the only 4743 * one who does also have a full A/E split called 4744 * DDI_F what makes DDI_E useless. However for this 4745 * case let's trust VBT info. 4746 */ 4747 if (IS_CANNONLAKE(dev_priv) && 4748 !intel_bios_is_port_present(dev_priv, PORT_E)) 4749 return true; 4750 4751 return false; 4752 } 4753 4754 static int 4755 intel_ddi_max_lanes(struct intel_digital_port *intel_dport) 4756 { 4757 struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev); 4758 enum port port = intel_dport->base.port; 4759 int max_lanes = 4; 4760 4761 if (INTEL_GEN(dev_priv) >= 11) 4762 return max_lanes; 4763 4764 if (port == PORT_A || port == PORT_E) { 4765 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4766 max_lanes = port == PORT_A ? 4 : 0; 4767 else 4768 /* Both A and E share 2 lanes */ 4769 max_lanes = 2; 4770 } 4771 4772 /* 4773 * Some BIOS might fail to set this bit on port A if eDP 4774 * wasn't lit up at boot. Force this bit set when needed 4775 * so we use the proper lane count for our calculations. 4776 */ 4777 if (intel_ddi_a_force_4_lanes(intel_dport)) { 4778 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n"); 4779 intel_dport->saved_port_bits |= DDI_A_4_LANES; 4780 max_lanes = 4; 4781 } 4782 4783 return max_lanes; 4784 } 4785 4786 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 4787 { 4788 struct ddi_vbt_port_info *port_info = 4789 &dev_priv->vbt.ddi_port_info[port]; 4790 struct intel_digital_port *intel_dig_port; 4791 struct intel_encoder *encoder; 4792 bool init_hdmi, init_dp, init_lspcon = false; 4793 enum phy phy = intel_port_to_phy(dev_priv, port); 4794 4795 init_hdmi = port_info->supports_dvi || port_info->supports_hdmi; 4796 init_dp = port_info->supports_dp; 4797 4798 if (intel_bios_is_lspcon_present(dev_priv, port)) { 4799 /* 4800 * Lspcon device needs to be driven with DP connector 4801 * with special detection sequence. So make sure DP 4802 * is initialized before lspcon. 4803 */ 4804 init_dp = true; 4805 init_lspcon = true; 4806 init_hdmi = false; 4807 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port)); 4808 } 4809 4810 if (!init_dp && !init_hdmi) { 4811 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 4812 port_name(port)); 4813 return; 4814 } 4815 4816 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 4817 if (!intel_dig_port) 4818 return; 4819 4820 encoder = &intel_dig_port->base; 4821 4822 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4823 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port)); 4824 4825 encoder->hotplug = intel_ddi_hotplug; 4826 encoder->compute_output_type = intel_ddi_compute_output_type; 4827 encoder->compute_config = intel_ddi_compute_config; 4828 encoder->enable = intel_enable_ddi; 4829 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 4830 encoder->pre_enable = intel_ddi_pre_enable; 4831 encoder->disable = intel_disable_ddi; 4832 encoder->post_disable = intel_ddi_post_disable; 4833 encoder->update_pipe = intel_ddi_update_pipe; 4834 encoder->get_hw_state = intel_ddi_get_hw_state; 4835 encoder->get_config = intel_ddi_get_config; 4836 encoder->suspend = intel_dp_encoder_suspend; 4837 encoder->get_power_domains = intel_ddi_get_power_domains; 4838 4839 encoder->type = INTEL_OUTPUT_DDI; 4840 encoder->power_domain = intel_port_to_power_domain(port); 4841 encoder->port = port; 4842 encoder->cloneable = 0; 4843 encoder->pipe_mask = ~0; 4844 4845 if (INTEL_GEN(dev_priv) >= 11) 4846 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & 4847 DDI_BUF_PORT_REVERSAL; 4848 else 4849 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & 4850 (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 4851 4852 intel_dig_port->dp.output_reg = INVALID_MMIO_REG; 4853 intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port); 4854 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 4855 4856 if (intel_phy_is_tc(dev_priv, phy)) { 4857 bool is_legacy = !port_info->supports_typec_usb && 4858 !port_info->supports_tbt; 4859 4860 intel_tc_port_init(intel_dig_port, is_legacy); 4861 4862 encoder->update_prepare = intel_ddi_update_prepare; 4863 encoder->update_complete = intel_ddi_update_complete; 4864 } 4865 4866 WARN_ON(port > PORT_I); 4867 intel_dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO + 4868 port - PORT_A; 4869 4870 if (init_dp) { 4871 if (!intel_ddi_init_dp_connector(intel_dig_port)) 4872 goto err; 4873 4874 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; 4875 } 4876 4877 /* In theory we don't need the encoder->type check, but leave it just in 4878 * case we have some really bad VBTs... */ 4879 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 4880 if (!intel_ddi_init_hdmi_connector(intel_dig_port)) 4881 goto err; 4882 } 4883 4884 if (init_lspcon) { 4885 if (lspcon_init(intel_dig_port)) 4886 /* TODO: handle hdmi info frame part */ 4887 DRM_DEBUG_KMS("LSPCON init success on port %c\n", 4888 port_name(port)); 4889 else 4890 /* 4891 * LSPCON init faied, but DP init was success, so 4892 * lets try to drive as DP++ port. 4893 */ 4894 DRM_ERROR("LSPCON init failed on port %c\n", 4895 port_name(port)); 4896 } 4897 4898 intel_infoframe_init(intel_dig_port); 4899 4900 return; 4901 4902 err: 4903 drm_encoder_cleanup(&encoder->base); 4904 kfree(intel_dig_port); 4905 } 4906