1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <drm/drm_scdc_helper.h> 29 30 #include "i915_drv.h" 31 #include "i915_trace.h" 32 #include "intel_audio.h" 33 #include "intel_combo_phy.h" 34 #include "intel_connector.h" 35 #include "intel_ddi.h" 36 #include "intel_display_types.h" 37 #include "intel_dp.h" 38 #include "intel_dp_mst.h" 39 #include "intel_dp_link_training.h" 40 #include "intel_dpio_phy.h" 41 #include "intel_dsi.h" 42 #include "intel_fifo_underrun.h" 43 #include "intel_gmbus.h" 44 #include "intel_hdcp.h" 45 #include "intel_hdmi.h" 46 #include "intel_hotplug.h" 47 #include "intel_lspcon.h" 48 #include "intel_panel.h" 49 #include "intel_psr.h" 50 #include "intel_sprite.h" 51 #include "intel_tc.h" 52 #include "intel_vdsc.h" 53 54 struct ddi_buf_trans { 55 u32 trans1; /* balance leg enable, de-emph level */ 56 u32 trans2; /* vref sel, vswing */ 57 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */ 58 }; 59 60 static const u8 index_to_dp_signal_levels[] = { 61 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 62 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 63 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 64 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 65 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 66 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 67 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 68 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 69 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 70 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 71 }; 72 73 /* HDMI/DVI modes ignore everything but the last 2 items. So we share 74 * them for both DP and FDI transports, allowing those ports to 75 * automatically adapt to HDMI connections as well 76 */ 77 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { 78 { 0x00FFFFFF, 0x0006000E, 0x0 }, 79 { 0x00D75FFF, 0x0005000A, 0x0 }, 80 { 0x00C30FFF, 0x00040006, 0x0 }, 81 { 0x80AAAFFF, 0x000B0000, 0x0 }, 82 { 0x00FFFFFF, 0x0005000A, 0x0 }, 83 { 0x00D75FFF, 0x000C0004, 0x0 }, 84 { 0x80C30FFF, 0x000B0000, 0x0 }, 85 { 0x00FFFFFF, 0x00040006, 0x0 }, 86 { 0x80D75FFF, 0x000B0000, 0x0 }, 87 }; 88 89 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { 90 { 0x00FFFFFF, 0x0007000E, 0x0 }, 91 { 0x00D75FFF, 0x000F000A, 0x0 }, 92 { 0x00C30FFF, 0x00060006, 0x0 }, 93 { 0x00AAAFFF, 0x001E0000, 0x0 }, 94 { 0x00FFFFFF, 0x000F000A, 0x0 }, 95 { 0x00D75FFF, 0x00160004, 0x0 }, 96 { 0x00C30FFF, 0x001E0000, 0x0 }, 97 { 0x00FFFFFF, 0x00060006, 0x0 }, 98 { 0x00D75FFF, 0x001E0000, 0x0 }, 99 }; 100 101 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { 102 /* Idx NT mV d T mV d db */ 103 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */ 104 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */ 105 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */ 106 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */ 107 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */ 108 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */ 109 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */ 110 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */ 111 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */ 112 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */ 113 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */ 114 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */ 115 }; 116 117 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { 118 { 0x00FFFFFF, 0x00000012, 0x0 }, 119 { 0x00EBAFFF, 0x00020011, 0x0 }, 120 { 0x00C71FFF, 0x0006000F, 0x0 }, 121 { 0x00AAAFFF, 0x000E000A, 0x0 }, 122 { 0x00FFFFFF, 0x00020011, 0x0 }, 123 { 0x00DB6FFF, 0x0005000F, 0x0 }, 124 { 0x00BEEFFF, 0x000A000C, 0x0 }, 125 { 0x00FFFFFF, 0x0005000F, 0x0 }, 126 { 0x00DB6FFF, 0x000A000C, 0x0 }, 127 }; 128 129 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { 130 { 0x00FFFFFF, 0x0007000E, 0x0 }, 131 { 0x00D75FFF, 0x000E000A, 0x0 }, 132 { 0x00BEFFFF, 0x00140006, 0x0 }, 133 { 0x80B2CFFF, 0x001B0002, 0x0 }, 134 { 0x00FFFFFF, 0x000E000A, 0x0 }, 135 { 0x00DB6FFF, 0x00160005, 0x0 }, 136 { 0x80C71FFF, 0x001A0002, 0x0 }, 137 { 0x00F7DFFF, 0x00180004, 0x0 }, 138 { 0x80D75FFF, 0x001B0002, 0x0 }, 139 }; 140 141 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { 142 { 0x00FFFFFF, 0x0001000E, 0x0 }, 143 { 0x00D75FFF, 0x0004000A, 0x0 }, 144 { 0x00C30FFF, 0x00070006, 0x0 }, 145 { 0x00AAAFFF, 0x000C0000, 0x0 }, 146 { 0x00FFFFFF, 0x0004000A, 0x0 }, 147 { 0x00D75FFF, 0x00090004, 0x0 }, 148 { 0x00C30FFF, 0x000C0000, 0x0 }, 149 { 0x00FFFFFF, 0x00070006, 0x0 }, 150 { 0x00D75FFF, 0x000C0000, 0x0 }, 151 }; 152 153 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { 154 /* Idx NT mV d T mV df db */ 155 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */ 156 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */ 157 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */ 158 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */ 159 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */ 160 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */ 161 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */ 162 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */ 163 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */ 164 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */ 165 }; 166 167 /* Skylake H and S */ 168 static const struct ddi_buf_trans skl_ddi_translations_dp[] = { 169 { 0x00002016, 0x000000A0, 0x0 }, 170 { 0x00005012, 0x0000009B, 0x0 }, 171 { 0x00007011, 0x00000088, 0x0 }, 172 { 0x80009010, 0x000000C0, 0x1 }, 173 { 0x00002016, 0x0000009B, 0x0 }, 174 { 0x00005012, 0x00000088, 0x0 }, 175 { 0x80007011, 0x000000C0, 0x1 }, 176 { 0x00002016, 0x000000DF, 0x0 }, 177 { 0x80005012, 0x000000C0, 0x1 }, 178 }; 179 180 /* Skylake U */ 181 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { 182 { 0x0000201B, 0x000000A2, 0x0 }, 183 { 0x00005012, 0x00000088, 0x0 }, 184 { 0x80007011, 0x000000CD, 0x1 }, 185 { 0x80009010, 0x000000C0, 0x1 }, 186 { 0x0000201B, 0x0000009D, 0x0 }, 187 { 0x80005012, 0x000000C0, 0x1 }, 188 { 0x80007011, 0x000000C0, 0x1 }, 189 { 0x00002016, 0x00000088, 0x0 }, 190 { 0x80005012, 0x000000C0, 0x1 }, 191 }; 192 193 /* Skylake Y */ 194 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { 195 { 0x00000018, 0x000000A2, 0x0 }, 196 { 0x00005012, 0x00000088, 0x0 }, 197 { 0x80007011, 0x000000CD, 0x3 }, 198 { 0x80009010, 0x000000C0, 0x3 }, 199 { 0x00000018, 0x0000009D, 0x0 }, 200 { 0x80005012, 0x000000C0, 0x3 }, 201 { 0x80007011, 0x000000C0, 0x3 }, 202 { 0x00000018, 0x00000088, 0x0 }, 203 { 0x80005012, 0x000000C0, 0x3 }, 204 }; 205 206 /* Kabylake H and S */ 207 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = { 208 { 0x00002016, 0x000000A0, 0x0 }, 209 { 0x00005012, 0x0000009B, 0x0 }, 210 { 0x00007011, 0x00000088, 0x0 }, 211 { 0x80009010, 0x000000C0, 0x1 }, 212 { 0x00002016, 0x0000009B, 0x0 }, 213 { 0x00005012, 0x00000088, 0x0 }, 214 { 0x80007011, 0x000000C0, 0x1 }, 215 { 0x00002016, 0x00000097, 0x0 }, 216 { 0x80005012, 0x000000C0, 0x1 }, 217 }; 218 219 /* Kabylake U */ 220 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = { 221 { 0x0000201B, 0x000000A1, 0x0 }, 222 { 0x00005012, 0x00000088, 0x0 }, 223 { 0x80007011, 0x000000CD, 0x3 }, 224 { 0x80009010, 0x000000C0, 0x3 }, 225 { 0x0000201B, 0x0000009D, 0x0 }, 226 { 0x80005012, 0x000000C0, 0x3 }, 227 { 0x80007011, 0x000000C0, 0x3 }, 228 { 0x00002016, 0x0000004F, 0x0 }, 229 { 0x80005012, 0x000000C0, 0x3 }, 230 }; 231 232 /* Kabylake Y */ 233 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = { 234 { 0x00001017, 0x000000A1, 0x0 }, 235 { 0x00005012, 0x00000088, 0x0 }, 236 { 0x80007011, 0x000000CD, 0x3 }, 237 { 0x8000800F, 0x000000C0, 0x3 }, 238 { 0x00001017, 0x0000009D, 0x0 }, 239 { 0x80005012, 0x000000C0, 0x3 }, 240 { 0x80007011, 0x000000C0, 0x3 }, 241 { 0x00001017, 0x0000004C, 0x0 }, 242 { 0x80005012, 0x000000C0, 0x3 }, 243 }; 244 245 /* 246 * Skylake/Kabylake H and S 247 * eDP 1.4 low vswing translation parameters 248 */ 249 static const struct ddi_buf_trans skl_ddi_translations_edp[] = { 250 { 0x00000018, 0x000000A8, 0x0 }, 251 { 0x00004013, 0x000000A9, 0x0 }, 252 { 0x00007011, 0x000000A2, 0x0 }, 253 { 0x00009010, 0x0000009C, 0x0 }, 254 { 0x00000018, 0x000000A9, 0x0 }, 255 { 0x00006013, 0x000000A2, 0x0 }, 256 { 0x00007011, 0x000000A6, 0x0 }, 257 { 0x00000018, 0x000000AB, 0x0 }, 258 { 0x00007013, 0x0000009F, 0x0 }, 259 { 0x00000018, 0x000000DF, 0x0 }, 260 }; 261 262 /* 263 * Skylake/Kabylake U 264 * eDP 1.4 low vswing translation parameters 265 */ 266 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = { 267 { 0x00000018, 0x000000A8, 0x0 }, 268 { 0x00004013, 0x000000A9, 0x0 }, 269 { 0x00007011, 0x000000A2, 0x0 }, 270 { 0x00009010, 0x0000009C, 0x0 }, 271 { 0x00000018, 0x000000A9, 0x0 }, 272 { 0x00006013, 0x000000A2, 0x0 }, 273 { 0x00007011, 0x000000A6, 0x0 }, 274 { 0x00002016, 0x000000AB, 0x0 }, 275 { 0x00005013, 0x0000009F, 0x0 }, 276 { 0x00000018, 0x000000DF, 0x0 }, 277 }; 278 279 /* 280 * Skylake/Kabylake Y 281 * eDP 1.4 low vswing translation parameters 282 */ 283 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = { 284 { 0x00000018, 0x000000A8, 0x0 }, 285 { 0x00004013, 0x000000AB, 0x0 }, 286 { 0x00007011, 0x000000A4, 0x0 }, 287 { 0x00009010, 0x000000DF, 0x0 }, 288 { 0x00000018, 0x000000AA, 0x0 }, 289 { 0x00006013, 0x000000A4, 0x0 }, 290 { 0x00007011, 0x0000009D, 0x0 }, 291 { 0x00000018, 0x000000A0, 0x0 }, 292 { 0x00006012, 0x000000DF, 0x0 }, 293 { 0x00000018, 0x0000008A, 0x0 }, 294 }; 295 296 /* Skylake/Kabylake U, H and S */ 297 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { 298 { 0x00000018, 0x000000AC, 0x0 }, 299 { 0x00005012, 0x0000009D, 0x0 }, 300 { 0x00007011, 0x00000088, 0x0 }, 301 { 0x00000018, 0x000000A1, 0x0 }, 302 { 0x00000018, 0x00000098, 0x0 }, 303 { 0x00004013, 0x00000088, 0x0 }, 304 { 0x80006012, 0x000000CD, 0x1 }, 305 { 0x00000018, 0x000000DF, 0x0 }, 306 { 0x80003015, 0x000000CD, 0x1 }, /* Default */ 307 { 0x80003015, 0x000000C0, 0x1 }, 308 { 0x80000018, 0x000000C0, 0x1 }, 309 }; 310 311 /* Skylake/Kabylake Y */ 312 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { 313 { 0x00000018, 0x000000A1, 0x0 }, 314 { 0x00005012, 0x000000DF, 0x0 }, 315 { 0x80007011, 0x000000CB, 0x3 }, 316 { 0x00000018, 0x000000A4, 0x0 }, 317 { 0x00000018, 0x0000009D, 0x0 }, 318 { 0x00004013, 0x00000080, 0x0 }, 319 { 0x80006013, 0x000000C0, 0x3 }, 320 { 0x00000018, 0x0000008A, 0x0 }, 321 { 0x80003015, 0x000000C0, 0x3 }, /* Default */ 322 { 0x80003015, 0x000000C0, 0x3 }, 323 { 0x80000018, 0x000000C0, 0x3 }, 324 }; 325 326 struct bxt_ddi_buf_trans { 327 u8 margin; /* swing value */ 328 u8 scale; /* scale value */ 329 u8 enable; /* scale enable */ 330 u8 deemphasis; 331 }; 332 333 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { 334 /* Idx NT mV diff db */ 335 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ 336 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */ 337 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */ 338 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */ 339 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */ 340 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */ 341 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */ 342 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */ 343 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */ 344 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */ 345 }; 346 347 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = { 348 /* Idx NT mV diff db */ 349 { 26, 0, 0, 128, }, /* 0: 200 0 */ 350 { 38, 0, 0, 112, }, /* 1: 200 1.5 */ 351 { 48, 0, 0, 96, }, /* 2: 200 4 */ 352 { 54, 0, 0, 69, }, /* 3: 200 6 */ 353 { 32, 0, 0, 128, }, /* 4: 250 0 */ 354 { 48, 0, 0, 104, }, /* 5: 250 1.5 */ 355 { 54, 0, 0, 85, }, /* 6: 250 4 */ 356 { 43, 0, 0, 128, }, /* 7: 300 0 */ 357 { 54, 0, 0, 101, }, /* 8: 300 1.5 */ 358 { 48, 0, 0, 128, }, /* 9: 300 0 */ 359 }; 360 361 /* BSpec has 2 recommended values - entries 0 and 8. 362 * Using the entry with higher vswing. 363 */ 364 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = { 365 /* Idx NT mV diff db */ 366 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ 367 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */ 368 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */ 369 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */ 370 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */ 371 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */ 372 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */ 373 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */ 374 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */ 375 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */ 376 }; 377 378 struct cnl_ddi_buf_trans { 379 u8 dw2_swing_sel; 380 u8 dw7_n_scalar; 381 u8 dw4_cursor_coeff; 382 u8 dw4_post_cursor_2; 383 u8 dw4_post_cursor_1; 384 }; 385 386 /* Voltage Swing Programming for VccIO 0.85V for DP */ 387 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = { 388 /* NT mV Trans mV db */ 389 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 390 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ 391 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ 392 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ 393 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 394 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 395 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 396 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ 397 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ 398 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 399 }; 400 401 /* Voltage Swing Programming for VccIO 0.85V for HDMI */ 402 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = { 403 /* NT mV Trans mV db */ 404 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 405 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ 406 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ 407 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */ 408 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ 409 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ 410 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 411 }; 412 413 /* Voltage Swing Programming for VccIO 0.85V for eDP */ 414 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = { 415 /* NT mV Trans mV db */ 416 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 417 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 418 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 419 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 420 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 421 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 422 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */ 423 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */ 424 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 425 }; 426 427 /* Voltage Swing Programming for VccIO 0.95V for DP */ 428 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = { 429 /* NT mV Trans mV db */ 430 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 431 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ 432 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ 433 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ 434 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 435 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 436 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 437 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ 438 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ 439 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 440 }; 441 442 /* Voltage Swing Programming for VccIO 0.95V for HDMI */ 443 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = { 444 /* NT mV Trans mV db */ 445 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 446 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 447 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 448 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 449 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 450 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 451 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ 452 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ 453 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ 454 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ 455 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 456 }; 457 458 /* Voltage Swing Programming for VccIO 0.95V for eDP */ 459 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = { 460 /* NT mV Trans mV db */ 461 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 462 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 463 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 464 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 465 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 466 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 467 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ 468 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ 469 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */ 470 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 471 }; 472 473 /* Voltage Swing Programming for VccIO 1.05V for DP */ 474 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = { 475 /* NT mV Trans mV db */ 476 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 477 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 478 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 479 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */ 480 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 481 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 482 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */ 483 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */ 484 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */ 485 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 486 }; 487 488 /* Voltage Swing Programming for VccIO 1.05V for HDMI */ 489 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = { 490 /* NT mV Trans mV db */ 491 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 492 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 493 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 494 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 495 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 496 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 497 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ 498 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ 499 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ 500 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ 501 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 502 }; 503 504 /* Voltage Swing Programming for VccIO 1.05V for eDP */ 505 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = { 506 /* NT mV Trans mV db */ 507 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 508 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 509 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 510 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 511 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 512 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 513 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ 514 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ 515 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 516 }; 517 518 /* icl_combo_phy_ddi_translations */ 519 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = { 520 /* NT mV Trans mV db */ 521 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 522 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 523 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 524 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 525 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 526 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 527 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 528 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 529 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 530 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 531 }; 532 533 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = { 534 /* NT mV Trans mV db */ 535 { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ 536 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */ 537 { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */ 538 { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */ 539 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ 540 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */ 541 { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */ 542 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ 543 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ 544 { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 545 }; 546 547 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = { 548 /* NT mV Trans mV db */ 549 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 550 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 551 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 552 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 553 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 554 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 555 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 556 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 557 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 558 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 559 }; 560 561 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = { 562 /* NT mV Trans mV db */ 563 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 564 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ 565 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ 566 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */ 567 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ 568 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ 569 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 570 }; 571 572 static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = { 573 /* NT mV Trans mV db */ 574 { 0xA, 0x33, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 575 { 0xA, 0x47, 0x36, 0x00, 0x09 }, /* 350 500 3.1 */ 576 { 0xC, 0x64, 0x34, 0x00, 0x0B }, /* 350 700 6.0 */ 577 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 350 900 8.2 */ 578 { 0xA, 0x46, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 579 { 0xC, 0x64, 0x38, 0x00, 0x07 }, /* 500 700 2.9 */ 580 { 0x6, 0x7F, 0x32, 0x00, 0x0D }, /* 500 900 5.1 */ 581 { 0xC, 0x61, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */ 582 { 0x6, 0x7F, 0x38, 0x00, 0x07 }, /* 600 900 3.5 */ 583 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 584 }; 585 586 static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr[] = { 587 /* NT mV Trans mV db */ 588 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ 589 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */ 590 { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */ 591 { 0xA, 0x35, 0x36, 0x00, 0x09 }, /* 200 350 4.9 */ 592 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ 593 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */ 594 { 0xA, 0x35, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */ 595 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ 596 { 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ 597 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 598 }; 599 600 static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2[] = { 601 /* NT mV Trans mV db */ 602 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ 603 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 250 1.9 */ 604 { 0x1, 0x7F, 0x3D, 0x00, 0x02 }, /* 200 300 3.5 */ 605 { 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 200 350 4.9 */ 606 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ 607 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 300 1.6 */ 608 { 0xA, 0x35, 0x3A, 0x00, 0x05 }, /* 250 350 2.9 */ 609 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ 610 { 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ 611 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 612 }; 613 614 static const struct cnl_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_rbr_hbr[] = { 615 /* NT mV Trans mV db */ 616 { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 617 { 0xA, 0x48, 0x35, 0x00, 0x0A }, /* 350 500 3.1 */ 618 { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 619 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 350 900 8.2 */ 620 { 0xA, 0x43, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 621 { 0xC, 0x60, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 622 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 623 { 0xC, 0x60, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */ 624 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 600 900 3.5 */ 625 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 626 }; 627 628 static const struct cnl_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_hbr2_hbr3[] = { 629 /* NT mV Trans mV db */ 630 { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 631 { 0xA, 0x48, 0x35, 0x00, 0x0A }, /* 350 500 3.1 */ 632 { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 633 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 350 900 8.2 */ 634 { 0xA, 0x43, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 635 { 0xC, 0x60, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 636 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 637 { 0xC, 0x58, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */ 638 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 639 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 640 }; 641 642 struct icl_mg_phy_ddi_buf_trans { 643 u32 cri_txdeemph_override_11_6; 644 u32 cri_txdeemph_override_5_0; 645 u32 cri_txdeemph_override_17_12; 646 }; 647 648 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_rbr_hbr[] = { 649 /* Voltage swing pre-emphasis */ 650 { 0x18, 0x00, 0x00 }, /* 0 0 */ 651 { 0x1D, 0x00, 0x05 }, /* 0 1 */ 652 { 0x24, 0x00, 0x0C }, /* 0 2 */ 653 { 0x2B, 0x00, 0x14 }, /* 0 3 */ 654 { 0x21, 0x00, 0x00 }, /* 1 0 */ 655 { 0x2B, 0x00, 0x08 }, /* 1 1 */ 656 { 0x30, 0x00, 0x0F }, /* 1 2 */ 657 { 0x31, 0x00, 0x03 }, /* 2 0 */ 658 { 0x34, 0x00, 0x0B }, /* 2 1 */ 659 { 0x3F, 0x00, 0x00 }, /* 3 0 */ 660 }; 661 662 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hbr2_hbr3[] = { 663 /* Voltage swing pre-emphasis */ 664 { 0x18, 0x00, 0x00 }, /* 0 0 */ 665 { 0x1D, 0x00, 0x05 }, /* 0 1 */ 666 { 0x24, 0x00, 0x0C }, /* 0 2 */ 667 { 0x2B, 0x00, 0x14 }, /* 0 3 */ 668 { 0x26, 0x00, 0x00 }, /* 1 0 */ 669 { 0x2C, 0x00, 0x07 }, /* 1 1 */ 670 { 0x33, 0x00, 0x0C }, /* 1 2 */ 671 { 0x2E, 0x00, 0x00 }, /* 2 0 */ 672 { 0x36, 0x00, 0x09 }, /* 2 1 */ 673 { 0x3F, 0x00, 0x00 }, /* 3 0 */ 674 }; 675 676 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hdmi[] = { 677 /* HDMI Preset VS Pre-emph */ 678 { 0x1A, 0x0, 0x0 }, /* 1 400mV 0dB */ 679 { 0x20, 0x0, 0x0 }, /* 2 500mV 0dB */ 680 { 0x29, 0x0, 0x0 }, /* 3 650mV 0dB */ 681 { 0x32, 0x0, 0x0 }, /* 4 800mV 0dB */ 682 { 0x3F, 0x0, 0x0 }, /* 5 1000mV 0dB */ 683 { 0x3A, 0x0, 0x5 }, /* 6 Full -1.5 dB */ 684 { 0x39, 0x0, 0x6 }, /* 7 Full -1.8 dB */ 685 { 0x38, 0x0, 0x7 }, /* 8 Full -2 dB */ 686 { 0x37, 0x0, 0x8 }, /* 9 Full -2.5 dB */ 687 { 0x36, 0x0, 0x9 }, /* 10 Full -3 dB */ 688 }; 689 690 struct tgl_dkl_phy_ddi_buf_trans { 691 u32 dkl_vswing_control; 692 u32 dkl_preshoot_control; 693 u32 dkl_de_emphasis_control; 694 }; 695 696 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans[] = { 697 /* VS pre-emp Non-trans mV Pre-emph dB */ 698 { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */ 699 { 0x5, 0x0, 0x05 }, /* 0 1 400mV 3.5 dB */ 700 { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB */ 701 { 0x0, 0x0, 0x18 }, /* 0 3 400mV 9.5 dB */ 702 { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */ 703 { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 dB */ 704 { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */ 705 { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */ 706 { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */ 707 { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */ 708 }; 709 710 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans_hbr2[] = { 711 /* VS pre-emp Non-trans mV Pre-emph dB */ 712 { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */ 713 { 0x5, 0x0, 0x05 }, /* 0 1 400mV 3.5 dB */ 714 { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB */ 715 { 0x0, 0x0, 0x19 }, /* 0 3 400mV 9.5 dB */ 716 { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */ 717 { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 dB */ 718 { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */ 719 { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */ 720 { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */ 721 { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */ 722 }; 723 724 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_hdmi_ddi_trans[] = { 725 /* HDMI Preset VS Pre-emph */ 726 { 0x7, 0x0, 0x0 }, /* 1 400mV 0dB */ 727 { 0x6, 0x0, 0x0 }, /* 2 500mV 0dB */ 728 { 0x4, 0x0, 0x0 }, /* 3 650mV 0dB */ 729 { 0x2, 0x0, 0x0 }, /* 4 800mV 0dB */ 730 { 0x0, 0x0, 0x0 }, /* 5 1000mV 0dB */ 731 { 0x0, 0x0, 0x5 }, /* 6 Full -1.5 dB */ 732 { 0x0, 0x0, 0x6 }, /* 7 Full -1.8 dB */ 733 { 0x0, 0x0, 0x7 }, /* 8 Full -2 dB */ 734 { 0x0, 0x0, 0x8 }, /* 9 Full -2.5 dB */ 735 { 0x0, 0x0, 0xA }, /* 10 Full -3 dB */ 736 }; 737 738 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr[] = { 739 /* NT mV Trans mV db */ 740 { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 741 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 742 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 743 { 0x6, 0x7D, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 744 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 745 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 746 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 747 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 748 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 749 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 750 }; 751 752 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = { 753 /* NT mV Trans mV db */ 754 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 755 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 756 { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 757 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 758 { 0xA, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 759 { 0xC, 0x63, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 760 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 761 { 0xC, 0x61, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 762 { 0x6, 0x7B, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 763 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 764 }; 765 766 static const struct cnl_ddi_buf_trans tgl_uy_combo_phy_ddi_translations_dp_hbr2[] = { 767 /* NT mV Trans mV db */ 768 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 769 { 0xA, 0x4F, 0x36, 0x00, 0x09 }, /* 350 500 3.1 */ 770 { 0xC, 0x60, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ 771 { 0xC, 0x7F, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ 772 { 0xC, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 773 { 0xC, 0x6F, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 774 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 500 900 5.1 */ 775 { 0x6, 0x60, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 776 { 0x6, 0x7F, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ 777 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 778 }; 779 780 /* 781 * Cloned the HOBL entry to comply with the voltage and pre-emphasis entries 782 * that DisplayPort specification requires 783 */ 784 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = { 785 /* VS pre-emp */ 786 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 0 */ 787 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 1 */ 788 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 2 */ 789 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 3 */ 790 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1 0 */ 791 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1 1 */ 792 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1 2 */ 793 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 2 0 */ 794 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 2 1 */ 795 }; 796 797 static const struct cnl_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr[] = { 798 /* NT mV Trans mV db */ 799 { 0xA, 0x2F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 800 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 801 { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 802 { 0x6, 0x7D, 0x2A, 0x00, 0x15 }, /* 350 900 8.2 */ 803 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 804 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 805 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 806 { 0xC, 0x6E, 0x3E, 0x00, 0x01 }, /* 650 700 0.6 */ 807 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 808 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 809 }; 810 811 static const struct cnl_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr2_hbr3[] = { 812 /* NT mV Trans mV db */ 813 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 814 { 0xA, 0x50, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ 815 { 0xC, 0x61, 0x33, 0x00, 0x0C }, /* 350 700 6.0 */ 816 { 0x6, 0x7F, 0x2E, 0x00, 0x11 }, /* 350 900 8.2 */ 817 { 0xA, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 818 { 0xC, 0x5F, 0x38, 0x00, 0x07 }, /* 500 700 2.9 */ 819 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 820 { 0xC, 0x5F, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */ 821 { 0x6, 0x7E, 0x36, 0x00, 0x09 }, /* 600 900 3.5 */ 822 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 823 }; 824 825 static bool is_hobl_buf_trans(const struct cnl_ddi_buf_trans *table) 826 { 827 return table == tgl_combo_phy_ddi_translations_edp_hbr2_hobl; 828 } 829 830 static const struct ddi_buf_trans * 831 bdw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) 832 { 833 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 834 835 if (dev_priv->vbt.edp.low_vswing) { 836 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp); 837 return bdw_ddi_translations_edp; 838 } else { 839 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 840 return bdw_ddi_translations_dp; 841 } 842 } 843 844 static const struct ddi_buf_trans * 845 skl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) 846 { 847 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 848 849 if (IS_SKL_ULX(dev_priv)) { 850 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); 851 return skl_y_ddi_translations_dp; 852 } else if (IS_SKL_ULT(dev_priv)) { 853 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); 854 return skl_u_ddi_translations_dp; 855 } else { 856 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); 857 return skl_ddi_translations_dp; 858 } 859 } 860 861 static const struct ddi_buf_trans * 862 kbl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) 863 { 864 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 865 866 if (IS_KBL_ULX(dev_priv) || 867 IS_CFL_ULX(dev_priv) || 868 IS_CML_ULX(dev_priv)) { 869 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp); 870 return kbl_y_ddi_translations_dp; 871 } else if (IS_KBL_ULT(dev_priv) || 872 IS_CFL_ULT(dev_priv) || 873 IS_CML_ULT(dev_priv)) { 874 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp); 875 return kbl_u_ddi_translations_dp; 876 } else { 877 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp); 878 return kbl_ddi_translations_dp; 879 } 880 } 881 882 static const struct ddi_buf_trans * 883 skl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) 884 { 885 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 886 887 if (dev_priv->vbt.edp.low_vswing) { 888 if (IS_SKL_ULX(dev_priv) || 889 IS_KBL_ULX(dev_priv) || 890 IS_CFL_ULX(dev_priv) || 891 IS_CML_ULX(dev_priv)) { 892 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); 893 return skl_y_ddi_translations_edp; 894 } else if (IS_SKL_ULT(dev_priv) || 895 IS_KBL_ULT(dev_priv) || 896 IS_CFL_ULT(dev_priv) || 897 IS_CML_ULT(dev_priv)) { 898 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); 899 return skl_u_ddi_translations_edp; 900 } else { 901 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp); 902 return skl_ddi_translations_edp; 903 } 904 } 905 906 if (IS_KABYLAKE(dev_priv) || 907 IS_COFFEELAKE(dev_priv) || 908 IS_COMETLAKE(dev_priv)) 909 return kbl_get_buf_trans_dp(encoder, n_entries); 910 else 911 return skl_get_buf_trans_dp(encoder, n_entries); 912 } 913 914 static const struct ddi_buf_trans * 915 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) 916 { 917 if (IS_SKL_ULX(dev_priv) || 918 IS_KBL_ULX(dev_priv) || 919 IS_CFL_ULX(dev_priv) || 920 IS_CML_ULX(dev_priv)) { 921 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); 922 return skl_y_ddi_translations_hdmi; 923 } else { 924 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); 925 return skl_ddi_translations_hdmi; 926 } 927 } 928 929 static int skl_buf_trans_num_entries(enum port port, int n_entries) 930 { 931 /* Only DDIA and DDIE can select the 10th register with DP */ 932 if (port == PORT_A || port == PORT_E) 933 return min(n_entries, 10); 934 else 935 return min(n_entries, 9); 936 } 937 938 static const struct ddi_buf_trans * 939 intel_ddi_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) 940 { 941 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 942 943 if (IS_KABYLAKE(dev_priv) || 944 IS_COFFEELAKE(dev_priv) || 945 IS_COMETLAKE(dev_priv)) { 946 const struct ddi_buf_trans *ddi_translations = 947 kbl_get_buf_trans_dp(encoder, n_entries); 948 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); 949 return ddi_translations; 950 } else if (IS_SKYLAKE(dev_priv)) { 951 const struct ddi_buf_trans *ddi_translations = 952 skl_get_buf_trans_dp(encoder, n_entries); 953 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); 954 return ddi_translations; 955 } else if (IS_BROADWELL(dev_priv)) { 956 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 957 return bdw_ddi_translations_dp; 958 } else if (IS_HASWELL(dev_priv)) { 959 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 960 return hsw_ddi_translations_dp; 961 } 962 963 *n_entries = 0; 964 return NULL; 965 } 966 967 static const struct ddi_buf_trans * 968 intel_ddi_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) 969 { 970 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 971 972 if (IS_GEN9_BC(dev_priv)) { 973 const struct ddi_buf_trans *ddi_translations = 974 skl_get_buf_trans_edp(encoder, n_entries); 975 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); 976 return ddi_translations; 977 } else if (IS_BROADWELL(dev_priv)) { 978 return bdw_get_buf_trans_edp(encoder, n_entries); 979 } else if (IS_HASWELL(dev_priv)) { 980 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 981 return hsw_ddi_translations_dp; 982 } 983 984 *n_entries = 0; 985 return NULL; 986 } 987 988 static const struct ddi_buf_trans * 989 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, 990 int *n_entries) 991 { 992 if (IS_BROADWELL(dev_priv)) { 993 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi); 994 return bdw_ddi_translations_fdi; 995 } else if (IS_HASWELL(dev_priv)) { 996 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi); 997 return hsw_ddi_translations_fdi; 998 } 999 1000 *n_entries = 0; 1001 return NULL; 1002 } 1003 1004 static const struct ddi_buf_trans * 1005 intel_ddi_get_buf_trans_hdmi(struct intel_encoder *encoder, 1006 int *n_entries) 1007 { 1008 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1009 1010 if (IS_GEN9_BC(dev_priv)) { 1011 return skl_get_buf_trans_hdmi(dev_priv, n_entries); 1012 } else if (IS_BROADWELL(dev_priv)) { 1013 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 1014 return bdw_ddi_translations_hdmi; 1015 } else if (IS_HASWELL(dev_priv)) { 1016 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); 1017 return hsw_ddi_translations_hdmi; 1018 } 1019 1020 *n_entries = 0; 1021 return NULL; 1022 } 1023 1024 static const struct bxt_ddi_buf_trans * 1025 bxt_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) 1026 { 1027 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); 1028 return bxt_ddi_translations_dp; 1029 } 1030 1031 static const struct bxt_ddi_buf_trans * 1032 bxt_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) 1033 { 1034 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1035 1036 if (dev_priv->vbt.edp.low_vswing) { 1037 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp); 1038 return bxt_ddi_translations_edp; 1039 } 1040 1041 return bxt_get_buf_trans_dp(encoder, n_entries); 1042 } 1043 1044 static const struct bxt_ddi_buf_trans * 1045 bxt_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries) 1046 { 1047 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); 1048 return bxt_ddi_translations_hdmi; 1049 } 1050 1051 static const struct cnl_ddi_buf_trans * 1052 cnl_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries) 1053 { 1054 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1055 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 1056 1057 if (voltage == VOLTAGE_INFO_0_85V) { 1058 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V); 1059 return cnl_ddi_translations_hdmi_0_85V; 1060 } else if (voltage == VOLTAGE_INFO_0_95V) { 1061 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V); 1062 return cnl_ddi_translations_hdmi_0_95V; 1063 } else if (voltage == VOLTAGE_INFO_1_05V) { 1064 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V); 1065 return cnl_ddi_translations_hdmi_1_05V; 1066 } else { 1067 *n_entries = 1; /* shut up gcc */ 1068 MISSING_CASE(voltage); 1069 } 1070 return NULL; 1071 } 1072 1073 static const struct cnl_ddi_buf_trans * 1074 cnl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) 1075 { 1076 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1077 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 1078 1079 if (voltage == VOLTAGE_INFO_0_85V) { 1080 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V); 1081 return cnl_ddi_translations_dp_0_85V; 1082 } else if (voltage == VOLTAGE_INFO_0_95V) { 1083 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V); 1084 return cnl_ddi_translations_dp_0_95V; 1085 } else if (voltage == VOLTAGE_INFO_1_05V) { 1086 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V); 1087 return cnl_ddi_translations_dp_1_05V; 1088 } else { 1089 *n_entries = 1; /* shut up gcc */ 1090 MISSING_CASE(voltage); 1091 } 1092 return NULL; 1093 } 1094 1095 static const struct cnl_ddi_buf_trans * 1096 cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) 1097 { 1098 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1099 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 1100 1101 if (dev_priv->vbt.edp.low_vswing) { 1102 if (voltage == VOLTAGE_INFO_0_85V) { 1103 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V); 1104 return cnl_ddi_translations_edp_0_85V; 1105 } else if (voltage == VOLTAGE_INFO_0_95V) { 1106 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V); 1107 return cnl_ddi_translations_edp_0_95V; 1108 } else if (voltage == VOLTAGE_INFO_1_05V) { 1109 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V); 1110 return cnl_ddi_translations_edp_1_05V; 1111 } else { 1112 *n_entries = 1; /* shut up gcc */ 1113 MISSING_CASE(voltage); 1114 } 1115 return NULL; 1116 } else { 1117 return cnl_get_buf_trans_dp(encoder, n_entries); 1118 } 1119 } 1120 1121 static const struct cnl_ddi_buf_trans * 1122 icl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, 1123 const struct intel_crtc_state *crtc_state, 1124 int *n_entries) 1125 { 1126 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); 1127 return icl_combo_phy_ddi_translations_hdmi; 1128 } 1129 1130 static const struct cnl_ddi_buf_trans * 1131 icl_get_combo_buf_trans_dp(struct intel_encoder *encoder, 1132 const struct intel_crtc_state *crtc_state, 1133 int *n_entries) 1134 { 1135 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2); 1136 return icl_combo_phy_ddi_translations_dp_hbr2; 1137 } 1138 1139 static const struct cnl_ddi_buf_trans * 1140 icl_get_combo_buf_trans_edp(struct intel_encoder *encoder, 1141 const struct intel_crtc_state *crtc_state, 1142 int *n_entries) 1143 { 1144 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1145 1146 if (crtc_state->port_clock > 540000) { 1147 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3); 1148 return icl_combo_phy_ddi_translations_edp_hbr3; 1149 } else if (dev_priv->vbt.edp.low_vswing) { 1150 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2); 1151 return icl_combo_phy_ddi_translations_edp_hbr2; 1152 } else if (IS_DG1(dev_priv) && crtc_state->port_clock > 270000) { 1153 *n_entries = ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_hbr2_hbr3); 1154 return dg1_combo_phy_ddi_translations_dp_hbr2_hbr3; 1155 } else if (IS_DG1(dev_priv)) { 1156 *n_entries = ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_rbr_hbr); 1157 return dg1_combo_phy_ddi_translations_dp_rbr_hbr; 1158 } 1159 1160 return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1161 } 1162 1163 static const struct cnl_ddi_buf_trans * 1164 icl_get_combo_buf_trans(struct intel_encoder *encoder, 1165 const struct intel_crtc_state *crtc_state, 1166 int *n_entries) 1167 { 1168 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1169 return icl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); 1170 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1171 return icl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); 1172 else 1173 return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1174 } 1175 1176 static const struct icl_mg_phy_ddi_buf_trans * 1177 icl_get_mg_buf_trans_hdmi(struct intel_encoder *encoder, 1178 const struct intel_crtc_state *crtc_state, 1179 int *n_entries) 1180 { 1181 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hdmi); 1182 return icl_mg_phy_ddi_translations_hdmi; 1183 } 1184 1185 static const struct icl_mg_phy_ddi_buf_trans * 1186 icl_get_mg_buf_trans_dp(struct intel_encoder *encoder, 1187 const struct intel_crtc_state *crtc_state, 1188 int *n_entries) 1189 { 1190 if (crtc_state->port_clock > 270000) { 1191 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hbr2_hbr3); 1192 return icl_mg_phy_ddi_translations_hbr2_hbr3; 1193 } else { 1194 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr); 1195 return icl_mg_phy_ddi_translations_rbr_hbr; 1196 } 1197 } 1198 1199 static const struct icl_mg_phy_ddi_buf_trans * 1200 icl_get_mg_buf_trans(struct intel_encoder *encoder, 1201 const struct intel_crtc_state *crtc_state, 1202 int *n_entries) 1203 { 1204 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1205 return icl_get_mg_buf_trans_hdmi(encoder, crtc_state, n_entries); 1206 else 1207 return icl_get_mg_buf_trans_dp(encoder, crtc_state, n_entries); 1208 } 1209 1210 static const struct cnl_ddi_buf_trans * 1211 ehl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, 1212 const struct intel_crtc_state *crtc_state, 1213 int *n_entries) 1214 { 1215 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); 1216 return icl_combo_phy_ddi_translations_hdmi; 1217 } 1218 1219 static const struct cnl_ddi_buf_trans * 1220 ehl_get_combo_buf_trans_dp(struct intel_encoder *encoder, 1221 const struct intel_crtc_state *crtc_state, 1222 int *n_entries) 1223 { 1224 *n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_dp); 1225 return ehl_combo_phy_ddi_translations_dp; 1226 } 1227 1228 static const struct cnl_ddi_buf_trans * 1229 ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder, 1230 const struct intel_crtc_state *crtc_state, 1231 int *n_entries) 1232 { 1233 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1234 1235 if (dev_priv->vbt.edp.low_vswing) { 1236 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2); 1237 return icl_combo_phy_ddi_translations_edp_hbr2; 1238 } 1239 1240 return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1241 } 1242 1243 static const struct cnl_ddi_buf_trans * 1244 ehl_get_combo_buf_trans(struct intel_encoder *encoder, 1245 const struct intel_crtc_state *crtc_state, 1246 int *n_entries) 1247 { 1248 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1249 return ehl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); 1250 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1251 return ehl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); 1252 else 1253 return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1254 } 1255 1256 static const struct cnl_ddi_buf_trans * 1257 jsl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, 1258 const struct intel_crtc_state *crtc_state, 1259 int *n_entries) 1260 { 1261 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); 1262 return icl_combo_phy_ddi_translations_hdmi; 1263 } 1264 1265 static const struct cnl_ddi_buf_trans * 1266 jsl_get_combo_buf_trans_dp(struct intel_encoder *encoder, 1267 const struct intel_crtc_state *crtc_state, 1268 int *n_entries) 1269 { 1270 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2); 1271 return icl_combo_phy_ddi_translations_dp_hbr2; 1272 } 1273 1274 static const struct cnl_ddi_buf_trans * 1275 jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder, 1276 const struct intel_crtc_state *crtc_state, 1277 int *n_entries) 1278 { 1279 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1280 1281 if (dev_priv->vbt.edp.low_vswing) { 1282 if (crtc_state->port_clock > 270000) { 1283 *n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr2); 1284 return jsl_combo_phy_ddi_translations_edp_hbr2; 1285 } else { 1286 *n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr); 1287 return jsl_combo_phy_ddi_translations_edp_hbr; 1288 } 1289 } 1290 1291 return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1292 } 1293 1294 static const struct cnl_ddi_buf_trans * 1295 jsl_get_combo_buf_trans(struct intel_encoder *encoder, 1296 const struct intel_crtc_state *crtc_state, 1297 int *n_entries) 1298 { 1299 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1300 return jsl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); 1301 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1302 return jsl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); 1303 else 1304 return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1305 } 1306 1307 static const struct cnl_ddi_buf_trans * 1308 tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, 1309 const struct intel_crtc_state *crtc_state, 1310 int *n_entries) 1311 { 1312 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); 1313 return icl_combo_phy_ddi_translations_hdmi; 1314 } 1315 1316 static const struct cnl_ddi_buf_trans * 1317 tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, 1318 const struct intel_crtc_state *crtc_state, 1319 int *n_entries) 1320 { 1321 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1322 1323 if (crtc_state->port_clock > 270000) { 1324 if (IS_ROCKETLAKE(dev_priv)) { 1325 *n_entries = ARRAY_SIZE(rkl_combo_phy_ddi_translations_dp_hbr2_hbr3); 1326 return rkl_combo_phy_ddi_translations_dp_hbr2_hbr3; 1327 } else if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) { 1328 *n_entries = ARRAY_SIZE(tgl_uy_combo_phy_ddi_translations_dp_hbr2); 1329 return tgl_uy_combo_phy_ddi_translations_dp_hbr2; 1330 } else { 1331 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2); 1332 return tgl_combo_phy_ddi_translations_dp_hbr2; 1333 } 1334 } else { 1335 if (IS_ROCKETLAKE(dev_priv)) { 1336 *n_entries = ARRAY_SIZE(rkl_combo_phy_ddi_translations_dp_hbr); 1337 return rkl_combo_phy_ddi_translations_dp_hbr; 1338 } else { 1339 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr); 1340 return tgl_combo_phy_ddi_translations_dp_hbr; 1341 } 1342 } 1343 } 1344 1345 static const struct cnl_ddi_buf_trans * 1346 tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder, 1347 const struct intel_crtc_state *crtc_state, 1348 int *n_entries) 1349 { 1350 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1351 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1352 1353 if (crtc_state->port_clock > 540000) { 1354 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3); 1355 return icl_combo_phy_ddi_translations_edp_hbr3; 1356 } else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) { 1357 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl); 1358 return tgl_combo_phy_ddi_translations_edp_hbr2_hobl; 1359 } else if (dev_priv->vbt.edp.low_vswing) { 1360 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2); 1361 return icl_combo_phy_ddi_translations_edp_hbr2; 1362 } 1363 1364 return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1365 } 1366 1367 static const struct cnl_ddi_buf_trans * 1368 tgl_get_combo_buf_trans(struct intel_encoder *encoder, 1369 const struct intel_crtc_state *crtc_state, 1370 int *n_entries) 1371 { 1372 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1373 return tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); 1374 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1375 return tgl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); 1376 else 1377 return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1378 } 1379 1380 static const struct tgl_dkl_phy_ddi_buf_trans * 1381 tgl_get_dkl_buf_trans_hdmi(struct intel_encoder *encoder, 1382 const struct intel_crtc_state *crtc_state, 1383 int *n_entries) 1384 { 1385 *n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans); 1386 return tgl_dkl_phy_hdmi_ddi_trans; 1387 } 1388 1389 static const struct tgl_dkl_phy_ddi_buf_trans * 1390 tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder, 1391 const struct intel_crtc_state *crtc_state, 1392 int *n_entries) 1393 { 1394 if (crtc_state->port_clock > 270000) { 1395 *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans_hbr2); 1396 return tgl_dkl_phy_dp_ddi_trans_hbr2; 1397 } else { 1398 *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans); 1399 return tgl_dkl_phy_dp_ddi_trans; 1400 } 1401 } 1402 1403 static const struct tgl_dkl_phy_ddi_buf_trans * 1404 tgl_get_dkl_buf_trans(struct intel_encoder *encoder, 1405 const struct intel_crtc_state *crtc_state, 1406 int *n_entries) 1407 { 1408 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1409 return tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, n_entries); 1410 else 1411 return tgl_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries); 1412 } 1413 1414 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 1415 const struct intel_crtc_state *crtc_state) 1416 { 1417 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1418 int n_entries, level, default_entry; 1419 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1420 1421 if (INTEL_GEN(dev_priv) >= 12) { 1422 if (intel_phy_is_combo(dev_priv, phy)) 1423 tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries); 1424 else 1425 tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, &n_entries); 1426 default_entry = n_entries - 1; 1427 } else if (INTEL_GEN(dev_priv) == 11) { 1428 if (intel_phy_is_combo(dev_priv, phy)) 1429 icl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries); 1430 else 1431 icl_get_mg_buf_trans_hdmi(encoder, crtc_state, &n_entries); 1432 default_entry = n_entries - 1; 1433 } else if (IS_CANNONLAKE(dev_priv)) { 1434 cnl_get_buf_trans_hdmi(encoder, &n_entries); 1435 default_entry = n_entries - 1; 1436 } else if (IS_GEN9_LP(dev_priv)) { 1437 bxt_get_buf_trans_hdmi(encoder, &n_entries); 1438 default_entry = n_entries - 1; 1439 } else if (IS_GEN9_BC(dev_priv)) { 1440 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); 1441 default_entry = 8; 1442 } else if (IS_BROADWELL(dev_priv)) { 1443 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); 1444 default_entry = 7; 1445 } else if (IS_HASWELL(dev_priv)) { 1446 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); 1447 default_entry = 6; 1448 } else { 1449 drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n"); 1450 return 0; 1451 } 1452 1453 if (drm_WARN_ON_ONCE(&dev_priv->drm, n_entries == 0)) 1454 return 0; 1455 1456 level = intel_bios_hdmi_level_shift(encoder); 1457 if (level < 0) 1458 level = default_entry; 1459 1460 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 1461 level = n_entries - 1; 1462 1463 return level; 1464 } 1465 1466 /* 1467 * Starting with Haswell, DDI port buffers must be programmed with correct 1468 * values in advance. This function programs the correct values for 1469 * DP/eDP/FDI use cases. 1470 */ 1471 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 1472 const struct intel_crtc_state *crtc_state) 1473 { 1474 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1475 u32 iboost_bit = 0; 1476 int i, n_entries; 1477 enum port port = encoder->port; 1478 const struct ddi_buf_trans *ddi_translations; 1479 1480 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) 1481 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv, 1482 &n_entries); 1483 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1484 ddi_translations = intel_ddi_get_buf_trans_edp(encoder, 1485 &n_entries); 1486 else 1487 ddi_translations = intel_ddi_get_buf_trans_dp(encoder, 1488 &n_entries); 1489 1490 /* If we're boosting the current, set bit 31 of trans1 */ 1491 if (IS_GEN9_BC(dev_priv) && intel_bios_dp_boost_level(encoder)) 1492 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 1493 1494 for (i = 0; i < n_entries; i++) { 1495 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 1496 ddi_translations[i].trans1 | iboost_bit); 1497 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 1498 ddi_translations[i].trans2); 1499 } 1500 } 1501 1502 /* 1503 * Starting with Haswell, DDI port buffers must be programmed with correct 1504 * values in advance. This function programs the correct values for 1505 * HDMI/DVI use cases. 1506 */ 1507 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 1508 int level) 1509 { 1510 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1511 u32 iboost_bit = 0; 1512 int n_entries; 1513 enum port port = encoder->port; 1514 const struct ddi_buf_trans *ddi_translations; 1515 1516 ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); 1517 1518 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 1519 return; 1520 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 1521 level = n_entries - 1; 1522 1523 /* If we're boosting the current, set bit 31 of trans1 */ 1524 if (IS_GEN9_BC(dev_priv) && intel_bios_hdmi_boost_level(encoder)) 1525 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 1526 1527 /* Entry 9 is for HDMI: */ 1528 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 1529 ddi_translations[level].trans1 | iboost_bit); 1530 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 1531 ddi_translations[level].trans2); 1532 } 1533 1534 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 1535 enum port port) 1536 { 1537 if (IS_BROXTON(dev_priv)) { 1538 udelay(16); 1539 return; 1540 } 1541 1542 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 1543 DDI_BUF_IS_IDLE), 8)) 1544 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", 1545 port_name(port)); 1546 } 1547 1548 static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, 1549 enum port port) 1550 { 1551 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ 1552 if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) { 1553 usleep_range(518, 1000); 1554 return; 1555 } 1556 1557 if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 1558 DDI_BUF_IS_IDLE), 500)) 1559 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", 1560 port_name(port)); 1561 } 1562 1563 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 1564 { 1565 switch (pll->info->id) { 1566 case DPLL_ID_WRPLL1: 1567 return PORT_CLK_SEL_WRPLL1; 1568 case DPLL_ID_WRPLL2: 1569 return PORT_CLK_SEL_WRPLL2; 1570 case DPLL_ID_SPLL: 1571 return PORT_CLK_SEL_SPLL; 1572 case DPLL_ID_LCPLL_810: 1573 return PORT_CLK_SEL_LCPLL_810; 1574 case DPLL_ID_LCPLL_1350: 1575 return PORT_CLK_SEL_LCPLL_1350; 1576 case DPLL_ID_LCPLL_2700: 1577 return PORT_CLK_SEL_LCPLL_2700; 1578 default: 1579 MISSING_CASE(pll->info->id); 1580 return PORT_CLK_SEL_NONE; 1581 } 1582 } 1583 1584 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 1585 const struct intel_crtc_state *crtc_state) 1586 { 1587 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1588 int clock = crtc_state->port_clock; 1589 const enum intel_dpll_id id = pll->info->id; 1590 1591 switch (id) { 1592 default: 1593 /* 1594 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 1595 * here, so do warn if this get passed in 1596 */ 1597 MISSING_CASE(id); 1598 return DDI_CLK_SEL_NONE; 1599 case DPLL_ID_ICL_TBTPLL: 1600 switch (clock) { 1601 case 162000: 1602 return DDI_CLK_SEL_TBT_162; 1603 case 270000: 1604 return DDI_CLK_SEL_TBT_270; 1605 case 540000: 1606 return DDI_CLK_SEL_TBT_540; 1607 case 810000: 1608 return DDI_CLK_SEL_TBT_810; 1609 default: 1610 MISSING_CASE(clock); 1611 return DDI_CLK_SEL_NONE; 1612 } 1613 case DPLL_ID_ICL_MGPLL1: 1614 case DPLL_ID_ICL_MGPLL2: 1615 case DPLL_ID_ICL_MGPLL3: 1616 case DPLL_ID_ICL_MGPLL4: 1617 case DPLL_ID_TGL_MGPLL5: 1618 case DPLL_ID_TGL_MGPLL6: 1619 return DDI_CLK_SEL_MG; 1620 } 1621 } 1622 1623 /* Starting with Haswell, different DDI ports can work in FDI mode for 1624 * connection to the PCH-located connectors. For this, it is necessary to train 1625 * both the DDI port and PCH receiver for the desired DDI buffer settings. 1626 * 1627 * The recommended port to work in FDI mode is DDI E, which we use here. Also, 1628 * please note that when FDI mode is active on DDI E, it shares 2 lines with 1629 * DDI A (which is used for eDP) 1630 */ 1631 1632 void hsw_fdi_link_train(struct intel_encoder *encoder, 1633 const struct intel_crtc_state *crtc_state) 1634 { 1635 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1636 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1637 u32 temp, i, rx_ctl_val, ddi_pll_sel; 1638 1639 intel_prepare_dp_ddi_buffers(encoder, crtc_state); 1640 1641 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the 1642 * mode set "sequence for CRT port" document: 1643 * - TP1 to TP2 time with the default value 1644 * - FDI delay to 90h 1645 * 1646 * WaFDIAutoLinkSetTimingOverrride:hsw 1647 */ 1648 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), 1649 FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 1650 1651 /* Enable the PCH Receiver FDI PLL */ 1652 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | 1653 FDI_RX_PLL_ENABLE | 1654 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); 1655 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 1656 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); 1657 udelay(220); 1658 1659 /* Switch from Rawclk to PCDclk */ 1660 rx_ctl_val |= FDI_PCDCLK; 1661 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 1662 1663 /* Configure Port Clock Select */ 1664 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll); 1665 intel_de_write(dev_priv, PORT_CLK_SEL(PORT_E), ddi_pll_sel); 1666 drm_WARN_ON(&dev_priv->drm, ddi_pll_sel != PORT_CLK_SEL_SPLL); 1667 1668 /* Start the training iterating through available voltages and emphasis, 1669 * testing each value twice. */ 1670 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { 1671 /* Configure DP_TP_CTL with auto-training */ 1672 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), 1673 DP_TP_CTL_FDI_AUTOTRAIN | 1674 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 1675 DP_TP_CTL_LINK_TRAIN_PAT1 | 1676 DP_TP_CTL_ENABLE); 1677 1678 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. 1679 * DDI E does not support port reversal, the functionality is 1680 * achieved on the PCH side in FDI_RX_CTL, so no need to set the 1681 * port reversal bit */ 1682 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), 1683 DDI_BUF_CTL_ENABLE | ((crtc_state->fdi_lanes - 1) << 1) | DDI_BUF_TRANS_SELECT(i / 2)); 1684 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E)); 1685 1686 udelay(600); 1687 1688 /* Program PCH FDI Receiver TU */ 1689 intel_de_write(dev_priv, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); 1690 1691 /* Enable PCH FDI Receiver with auto-training */ 1692 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; 1693 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 1694 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); 1695 1696 /* Wait for FDI receiver lane calibration */ 1697 udelay(30); 1698 1699 /* Unset FDI_RX_MISC pwrdn lanes */ 1700 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1701 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 1702 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp); 1703 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1704 1705 /* Wait for FDI auto training time */ 1706 udelay(5); 1707 1708 temp = intel_de_read(dev_priv, DP_TP_STATUS(PORT_E)); 1709 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { 1710 drm_dbg_kms(&dev_priv->drm, 1711 "FDI link training done on step %d\n", i); 1712 break; 1713 } 1714 1715 /* 1716 * Leave things enabled even if we failed to train FDI. 1717 * Results in less fireworks from the state checker. 1718 */ 1719 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) { 1720 drm_err(&dev_priv->drm, "FDI link training failed!\n"); 1721 break; 1722 } 1723 1724 rx_ctl_val &= ~FDI_RX_ENABLE; 1725 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 1726 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); 1727 1728 temp = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E)); 1729 temp &= ~DDI_BUF_CTL_ENABLE; 1730 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), temp); 1731 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E)); 1732 1733 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ 1734 temp = intel_de_read(dev_priv, DP_TP_CTL(PORT_E)); 1735 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 1736 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 1737 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp); 1738 intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E)); 1739 1740 intel_wait_ddi_buf_idle(dev_priv, PORT_E); 1741 1742 /* Reset FDI_RX_MISC pwrdn lanes */ 1743 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1744 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 1745 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 1746 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp); 1747 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1748 } 1749 1750 /* Enable normal pixel sending for FDI */ 1751 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), 1752 DP_TP_CTL_FDI_AUTOTRAIN | 1753 DP_TP_CTL_LINK_TRAIN_NORMAL | 1754 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 1755 DP_TP_CTL_ENABLE); 1756 } 1757 1758 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 1759 const struct intel_crtc_state *crtc_state) 1760 { 1761 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1762 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1763 1764 intel_dp->DP = dig_port->saved_port_bits | 1765 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); 1766 intel_dp->DP |= DDI_PORT_WIDTH(crtc_state->lane_count); 1767 } 1768 1769 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 1770 enum port port) 1771 { 1772 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 1773 1774 switch (val) { 1775 case DDI_CLK_SEL_NONE: 1776 return 0; 1777 case DDI_CLK_SEL_TBT_162: 1778 return 162000; 1779 case DDI_CLK_SEL_TBT_270: 1780 return 270000; 1781 case DDI_CLK_SEL_TBT_540: 1782 return 540000; 1783 case DDI_CLK_SEL_TBT_810: 1784 return 810000; 1785 default: 1786 MISSING_CASE(val); 1787 return 0; 1788 } 1789 } 1790 1791 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 1792 { 1793 int dotclock; 1794 1795 if (pipe_config->has_pch_encoder) 1796 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1797 &pipe_config->fdi_m_n); 1798 else if (intel_crtc_has_dp_encoder(pipe_config)) 1799 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1800 &pipe_config->dp_m_n); 1801 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) 1802 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp; 1803 else 1804 dotclock = pipe_config->port_clock; 1805 1806 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 1807 !intel_crtc_has_dp_encoder(pipe_config)) 1808 dotclock *= 2; 1809 1810 if (pipe_config->pixel_multiplier) 1811 dotclock /= pipe_config->pixel_multiplier; 1812 1813 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 1814 } 1815 1816 static void intel_ddi_clock_get(struct intel_encoder *encoder, 1817 struct intel_crtc_state *pipe_config) 1818 { 1819 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1820 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1821 1822 if (intel_phy_is_tc(dev_priv, phy) && 1823 intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll) == 1824 DPLL_ID_ICL_TBTPLL) 1825 pipe_config->port_clock = icl_calc_tbt_pll_link(dev_priv, 1826 encoder->port); 1827 else 1828 pipe_config->port_clock = 1829 intel_dpll_get_freq(dev_priv, pipe_config->shared_dpll, 1830 &pipe_config->dpll_hw_state); 1831 1832 ddi_dotclock_get(pipe_config); 1833 } 1834 1835 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 1836 const struct drm_connector_state *conn_state) 1837 { 1838 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1839 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1840 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1841 u32 temp; 1842 1843 if (!intel_crtc_has_dp_encoder(crtc_state)) 1844 return; 1845 1846 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 1847 1848 temp = DP_MSA_MISC_SYNC_CLOCK; 1849 1850 switch (crtc_state->pipe_bpp) { 1851 case 18: 1852 temp |= DP_MSA_MISC_6_BPC; 1853 break; 1854 case 24: 1855 temp |= DP_MSA_MISC_8_BPC; 1856 break; 1857 case 30: 1858 temp |= DP_MSA_MISC_10_BPC; 1859 break; 1860 case 36: 1861 temp |= DP_MSA_MISC_12_BPC; 1862 break; 1863 default: 1864 MISSING_CASE(crtc_state->pipe_bpp); 1865 break; 1866 } 1867 1868 /* nonsense combination */ 1869 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 1870 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 1871 1872 if (crtc_state->limited_color_range) 1873 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 1874 1875 /* 1876 * As per DP 1.2 spec section 2.3.4.3 while sending 1877 * YCBCR 444 signals we should program MSA MISC1/0 fields with 1878 * colorspace information. 1879 */ 1880 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 1881 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 1882 1883 /* 1884 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 1885 * of Color Encoding Format and Content Color Gamut] while sending 1886 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 1887 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 1888 */ 1889 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 1890 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 1891 1892 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp); 1893 } 1894 1895 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 1896 { 1897 if (master_transcoder == TRANSCODER_EDP) 1898 return 0; 1899 else 1900 return master_transcoder + 1; 1901 } 1902 1903 /* 1904 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 1905 * 1906 * Only intended to be used by intel_ddi_enable_transcoder_func() and 1907 * intel_ddi_config_transcoder_func(). 1908 */ 1909 static u32 1910 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 1911 const struct intel_crtc_state *crtc_state) 1912 { 1913 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1914 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1915 enum pipe pipe = crtc->pipe; 1916 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1917 enum port port = encoder->port; 1918 u32 temp; 1919 1920 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 1921 temp = TRANS_DDI_FUNC_ENABLE; 1922 if (INTEL_GEN(dev_priv) >= 12) 1923 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 1924 else 1925 temp |= TRANS_DDI_SELECT_PORT(port); 1926 1927 switch (crtc_state->pipe_bpp) { 1928 case 18: 1929 temp |= TRANS_DDI_BPC_6; 1930 break; 1931 case 24: 1932 temp |= TRANS_DDI_BPC_8; 1933 break; 1934 case 30: 1935 temp |= TRANS_DDI_BPC_10; 1936 break; 1937 case 36: 1938 temp |= TRANS_DDI_BPC_12; 1939 break; 1940 default: 1941 BUG(); 1942 } 1943 1944 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 1945 temp |= TRANS_DDI_PVSYNC; 1946 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 1947 temp |= TRANS_DDI_PHSYNC; 1948 1949 if (cpu_transcoder == TRANSCODER_EDP) { 1950 switch (pipe) { 1951 case PIPE_A: 1952 /* On Haswell, can only use the always-on power well for 1953 * eDP when not using the panel fitter, and when not 1954 * using motion blur mitigation (which we don't 1955 * support). */ 1956 if (crtc_state->pch_pfit.force_thru) 1957 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 1958 else 1959 temp |= TRANS_DDI_EDP_INPUT_A_ON; 1960 break; 1961 case PIPE_B: 1962 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 1963 break; 1964 case PIPE_C: 1965 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 1966 break; 1967 default: 1968 BUG(); 1969 break; 1970 } 1971 } 1972 1973 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1974 if (crtc_state->has_hdmi_sink) 1975 temp |= TRANS_DDI_MODE_SELECT_HDMI; 1976 else 1977 temp |= TRANS_DDI_MODE_SELECT_DVI; 1978 1979 if (crtc_state->hdmi_scrambling) 1980 temp |= TRANS_DDI_HDMI_SCRAMBLING; 1981 if (crtc_state->hdmi_high_tmds_clock_ratio) 1982 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 1983 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 1984 temp |= TRANS_DDI_MODE_SELECT_FDI; 1985 temp |= (crtc_state->fdi_lanes - 1) << 1; 1986 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 1987 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 1988 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 1989 1990 if (INTEL_GEN(dev_priv) >= 12) { 1991 enum transcoder master; 1992 1993 master = crtc_state->mst_master_transcoder; 1994 drm_WARN_ON(&dev_priv->drm, 1995 master == INVALID_TRANSCODER); 1996 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 1997 } 1998 } else { 1999 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 2000 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 2001 } 2002 2003 if (IS_GEN_RANGE(dev_priv, 8, 10) && 2004 crtc_state->master_transcoder != INVALID_TRANSCODER) { 2005 u8 master_select = 2006 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 2007 2008 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 2009 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 2010 } 2011 2012 return temp; 2013 } 2014 2015 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 2016 const struct intel_crtc_state *crtc_state) 2017 { 2018 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2019 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2020 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2021 2022 if (INTEL_GEN(dev_priv) >= 11) { 2023 enum transcoder master_transcoder = crtc_state->master_transcoder; 2024 u32 ctl2 = 0; 2025 2026 if (master_transcoder != INVALID_TRANSCODER) { 2027 u8 master_select = 2028 bdw_trans_port_sync_master_select(master_transcoder); 2029 2030 ctl2 |= PORT_SYNC_MODE_ENABLE | 2031 PORT_SYNC_MODE_MASTER_SELECT(master_select); 2032 } 2033 2034 intel_de_write(dev_priv, 2035 TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2); 2036 } 2037 2038 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 2039 intel_ddi_transcoder_func_reg_val_get(encoder, 2040 crtc_state)); 2041 } 2042 2043 /* 2044 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 2045 * bit. 2046 */ 2047 static void 2048 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 2049 const struct intel_crtc_state *crtc_state) 2050 { 2051 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2052 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2053 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2054 u32 ctl; 2055 2056 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 2057 ctl &= ~TRANS_DDI_FUNC_ENABLE; 2058 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 2059 } 2060 2061 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 2062 { 2063 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2064 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2065 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2066 u32 ctl; 2067 2068 if (INTEL_GEN(dev_priv) >= 11) 2069 intel_de_write(dev_priv, 2070 TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0); 2071 2072 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 2073 2074 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 2075 2076 ctl &= ~TRANS_DDI_FUNC_ENABLE; 2077 2078 if (IS_GEN_RANGE(dev_priv, 8, 10)) 2079 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 2080 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 2081 2082 if (INTEL_GEN(dev_priv) >= 12) { 2083 if (!intel_dp_mst_is_master_trans(crtc_state)) { 2084 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 2085 TRANS_DDI_MODE_SELECT_MASK); 2086 } 2087 } else { 2088 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 2089 } 2090 2091 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 2092 2093 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME && 2094 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 2095 drm_dbg_kms(&dev_priv->drm, 2096 "Quirk Increase DDI disabled time\n"); 2097 /* Quirk time at 100ms for reliable operation */ 2098 msleep(100); 2099 } 2100 } 2101 2102 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder, 2103 enum transcoder cpu_transcoder, 2104 bool enable) 2105 { 2106 struct drm_device *dev = intel_encoder->base.dev; 2107 struct drm_i915_private *dev_priv = to_i915(dev); 2108 intel_wakeref_t wakeref; 2109 int ret = 0; 2110 u32 tmp; 2111 2112 wakeref = intel_display_power_get_if_enabled(dev_priv, 2113 intel_encoder->power_domain); 2114 if (drm_WARN_ON(dev, !wakeref)) 2115 return -ENXIO; 2116 2117 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 2118 if (enable) 2119 tmp |= TRANS_DDI_HDCP_SIGNALLING; 2120 else 2121 tmp &= ~TRANS_DDI_HDCP_SIGNALLING; 2122 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp); 2123 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 2124 return ret; 2125 } 2126 2127 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 2128 { 2129 struct drm_device *dev = intel_connector->base.dev; 2130 struct drm_i915_private *dev_priv = to_i915(dev); 2131 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 2132 int type = intel_connector->base.connector_type; 2133 enum port port = encoder->port; 2134 enum transcoder cpu_transcoder; 2135 intel_wakeref_t wakeref; 2136 enum pipe pipe = 0; 2137 u32 tmp; 2138 bool ret; 2139 2140 wakeref = intel_display_power_get_if_enabled(dev_priv, 2141 encoder->power_domain); 2142 if (!wakeref) 2143 return false; 2144 2145 if (!encoder->get_hw_state(encoder, &pipe)) { 2146 ret = false; 2147 goto out; 2148 } 2149 2150 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 2151 cpu_transcoder = TRANSCODER_EDP; 2152 else 2153 cpu_transcoder = (enum transcoder) pipe; 2154 2155 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 2156 2157 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 2158 case TRANS_DDI_MODE_SELECT_HDMI: 2159 case TRANS_DDI_MODE_SELECT_DVI: 2160 ret = type == DRM_MODE_CONNECTOR_HDMIA; 2161 break; 2162 2163 case TRANS_DDI_MODE_SELECT_DP_SST: 2164 ret = type == DRM_MODE_CONNECTOR_eDP || 2165 type == DRM_MODE_CONNECTOR_DisplayPort; 2166 break; 2167 2168 case TRANS_DDI_MODE_SELECT_DP_MST: 2169 /* if the transcoder is in MST state then 2170 * connector isn't connected */ 2171 ret = false; 2172 break; 2173 2174 case TRANS_DDI_MODE_SELECT_FDI: 2175 ret = type == DRM_MODE_CONNECTOR_VGA; 2176 break; 2177 2178 default: 2179 ret = false; 2180 break; 2181 } 2182 2183 out: 2184 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 2185 2186 return ret; 2187 } 2188 2189 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 2190 u8 *pipe_mask, bool *is_dp_mst) 2191 { 2192 struct drm_device *dev = encoder->base.dev; 2193 struct drm_i915_private *dev_priv = to_i915(dev); 2194 enum port port = encoder->port; 2195 intel_wakeref_t wakeref; 2196 enum pipe p; 2197 u32 tmp; 2198 u8 mst_pipe_mask; 2199 2200 *pipe_mask = 0; 2201 *is_dp_mst = false; 2202 2203 wakeref = intel_display_power_get_if_enabled(dev_priv, 2204 encoder->power_domain); 2205 if (!wakeref) 2206 return; 2207 2208 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2209 if (!(tmp & DDI_BUF_CTL_ENABLE)) 2210 goto out; 2211 2212 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { 2213 tmp = intel_de_read(dev_priv, 2214 TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 2215 2216 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 2217 default: 2218 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 2219 fallthrough; 2220 case TRANS_DDI_EDP_INPUT_A_ON: 2221 case TRANS_DDI_EDP_INPUT_A_ONOFF: 2222 *pipe_mask = BIT(PIPE_A); 2223 break; 2224 case TRANS_DDI_EDP_INPUT_B_ONOFF: 2225 *pipe_mask = BIT(PIPE_B); 2226 break; 2227 case TRANS_DDI_EDP_INPUT_C_ONOFF: 2228 *pipe_mask = BIT(PIPE_C); 2229 break; 2230 } 2231 2232 goto out; 2233 } 2234 2235 mst_pipe_mask = 0; 2236 for_each_pipe(dev_priv, p) { 2237 enum transcoder cpu_transcoder = (enum transcoder)p; 2238 unsigned int port_mask, ddi_select; 2239 intel_wakeref_t trans_wakeref; 2240 2241 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 2242 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 2243 if (!trans_wakeref) 2244 continue; 2245 2246 if (INTEL_GEN(dev_priv) >= 12) { 2247 port_mask = TGL_TRANS_DDI_PORT_MASK; 2248 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 2249 } else { 2250 port_mask = TRANS_DDI_PORT_MASK; 2251 ddi_select = TRANS_DDI_SELECT_PORT(port); 2252 } 2253 2254 tmp = intel_de_read(dev_priv, 2255 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 2256 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 2257 trans_wakeref); 2258 2259 if ((tmp & port_mask) != ddi_select) 2260 continue; 2261 2262 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == 2263 TRANS_DDI_MODE_SELECT_DP_MST) 2264 mst_pipe_mask |= BIT(p); 2265 2266 *pipe_mask |= BIT(p); 2267 } 2268 2269 if (!*pipe_mask) 2270 drm_dbg_kms(&dev_priv->drm, 2271 "No pipe for [ENCODER:%d:%s] found\n", 2272 encoder->base.base.id, encoder->base.name); 2273 2274 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 2275 drm_dbg_kms(&dev_priv->drm, 2276 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 2277 encoder->base.base.id, encoder->base.name, 2278 *pipe_mask); 2279 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 2280 } 2281 2282 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 2283 drm_dbg_kms(&dev_priv->drm, 2284 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", 2285 encoder->base.base.id, encoder->base.name, 2286 *pipe_mask, mst_pipe_mask); 2287 else 2288 *is_dp_mst = mst_pipe_mask; 2289 2290 out: 2291 if (*pipe_mask && IS_GEN9_LP(dev_priv)) { 2292 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 2293 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 2294 BXT_PHY_LANE_POWERDOWN_ACK | 2295 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 2296 drm_err(&dev_priv->drm, 2297 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 2298 encoder->base.base.id, encoder->base.name, tmp); 2299 } 2300 2301 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 2302 } 2303 2304 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 2305 enum pipe *pipe) 2306 { 2307 u8 pipe_mask; 2308 bool is_mst; 2309 2310 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2311 2312 if (is_mst || !pipe_mask) 2313 return false; 2314 2315 *pipe = ffs(pipe_mask) - 1; 2316 2317 return true; 2318 } 2319 2320 static enum intel_display_power_domain 2321 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port) 2322 { 2323 /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with 2324 * DC states enabled at the same time, while for driver initiated AUX 2325 * transfers we need the same AUX IOs to be powered but with DC states 2326 * disabled. Accordingly use the AUX power domain here which leaves DC 2327 * states enabled. 2328 * However, for non-A AUX ports the corresponding non-EDP transcoders 2329 * would have already enabled power well 2 and DC_OFF. This means we can 2330 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a 2331 * specific AUX_IO reference without powering up any extra wells. 2332 * Note that PSR is enabled only on Port A even though this function 2333 * returns the correct domain for other ports too. 2334 */ 2335 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A : 2336 intel_aux_power_domain(dig_port); 2337 } 2338 2339 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 2340 struct intel_crtc_state *crtc_state) 2341 { 2342 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2343 struct intel_digital_port *dig_port; 2344 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2345 2346 /* 2347 * TODO: Add support for MST encoders. Atm, the following should never 2348 * happen since fake-MST encoders don't set their get_power_domains() 2349 * hook. 2350 */ 2351 if (drm_WARN_ON(&dev_priv->drm, 2352 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 2353 return; 2354 2355 dig_port = enc_to_dig_port(encoder); 2356 2357 if (!intel_phy_is_tc(dev_priv, phy) || 2358 dig_port->tc_mode != TC_PORT_TBT_ALT) { 2359 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2360 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2361 dig_port->ddi_io_power_domain); 2362 } 2363 2364 /* 2365 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC 2366 * ports. 2367 */ 2368 if (intel_crtc_has_dp_encoder(crtc_state) || 2369 intel_phy_is_tc(dev_priv, phy)) { 2370 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref); 2371 dig_port->aux_wakeref = 2372 intel_display_power_get(dev_priv, 2373 intel_ddi_main_link_aux_domain(dig_port)); 2374 } 2375 } 2376 2377 void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder, 2378 const struct intel_crtc_state *crtc_state) 2379 { 2380 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2381 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2382 enum port port = encoder->port; 2383 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2384 2385 if (cpu_transcoder != TRANSCODER_EDP) { 2386 if (INTEL_GEN(dev_priv) >= 12) 2387 intel_de_write(dev_priv, 2388 TRANS_CLK_SEL(cpu_transcoder), 2389 TGL_TRANS_CLK_SEL_PORT(port)); 2390 else 2391 intel_de_write(dev_priv, 2392 TRANS_CLK_SEL(cpu_transcoder), 2393 TRANS_CLK_SEL_PORT(port)); 2394 } 2395 } 2396 2397 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state) 2398 { 2399 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2400 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2401 2402 if (cpu_transcoder != TRANSCODER_EDP) { 2403 if (INTEL_GEN(dev_priv) >= 12) 2404 intel_de_write(dev_priv, 2405 TRANS_CLK_SEL(cpu_transcoder), 2406 TGL_TRANS_CLK_SEL_DISABLED); 2407 else 2408 intel_de_write(dev_priv, 2409 TRANS_CLK_SEL(cpu_transcoder), 2410 TRANS_CLK_SEL_DISABLED); 2411 } 2412 } 2413 2414 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 2415 enum port port, u8 iboost) 2416 { 2417 u32 tmp; 2418 2419 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 2420 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 2421 if (iboost) 2422 tmp |= iboost << BALANCE_LEG_SHIFT(port); 2423 else 2424 tmp |= BALANCE_LEG_DISABLE(port); 2425 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 2426 } 2427 2428 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 2429 const struct intel_crtc_state *crtc_state, 2430 int level) 2431 { 2432 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2433 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2434 u8 iboost; 2435 2436 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 2437 iboost = intel_bios_hdmi_boost_level(encoder); 2438 else 2439 iboost = intel_bios_dp_boost_level(encoder); 2440 2441 if (iboost == 0) { 2442 const struct ddi_buf_trans *ddi_translations; 2443 int n_entries; 2444 2445 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 2446 ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); 2447 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 2448 ddi_translations = intel_ddi_get_buf_trans_edp(encoder, &n_entries); 2449 else 2450 ddi_translations = intel_ddi_get_buf_trans_dp(encoder, &n_entries); 2451 2452 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 2453 return; 2454 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 2455 level = n_entries - 1; 2456 2457 iboost = ddi_translations[level].i_boost; 2458 } 2459 2460 /* Make sure that the requested I_boost is valid */ 2461 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 2462 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); 2463 return; 2464 } 2465 2466 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); 2467 2468 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 2469 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 2470 } 2471 2472 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, 2473 const struct intel_crtc_state *crtc_state, 2474 int level) 2475 { 2476 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2477 const struct bxt_ddi_buf_trans *ddi_translations; 2478 enum port port = encoder->port; 2479 int n_entries; 2480 2481 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 2482 ddi_translations = bxt_get_buf_trans_hdmi(encoder, &n_entries); 2483 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 2484 ddi_translations = bxt_get_buf_trans_edp(encoder, &n_entries); 2485 else 2486 ddi_translations = bxt_get_buf_trans_dp(encoder, &n_entries); 2487 2488 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 2489 return; 2490 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 2491 level = n_entries - 1; 2492 2493 bxt_ddi_phy_set_signal_level(dev_priv, port, 2494 ddi_translations[level].margin, 2495 ddi_translations[level].scale, 2496 ddi_translations[level].enable, 2497 ddi_translations[level].deemphasis); 2498 } 2499 2500 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 2501 const struct intel_crtc_state *crtc_state) 2502 { 2503 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2504 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2505 enum port port = encoder->port; 2506 enum phy phy = intel_port_to_phy(dev_priv, port); 2507 int n_entries; 2508 2509 if (INTEL_GEN(dev_priv) >= 12) { 2510 if (intel_phy_is_combo(dev_priv, phy)) 2511 tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries); 2512 else 2513 tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries); 2514 } else if (INTEL_GEN(dev_priv) == 11) { 2515 if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)) 2516 jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries); 2517 else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) 2518 ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries); 2519 else if (intel_phy_is_combo(dev_priv, phy)) 2520 icl_get_combo_buf_trans(encoder, crtc_state, &n_entries); 2521 else 2522 icl_get_mg_buf_trans(encoder, crtc_state, &n_entries); 2523 } else if (IS_CANNONLAKE(dev_priv)) { 2524 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 2525 cnl_get_buf_trans_edp(encoder, &n_entries); 2526 else 2527 cnl_get_buf_trans_dp(encoder, &n_entries); 2528 } else if (IS_GEN9_LP(dev_priv)) { 2529 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 2530 bxt_get_buf_trans_edp(encoder, &n_entries); 2531 else 2532 bxt_get_buf_trans_dp(encoder, &n_entries); 2533 } else { 2534 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 2535 intel_ddi_get_buf_trans_edp(encoder, &n_entries); 2536 else 2537 intel_ddi_get_buf_trans_dp(encoder, &n_entries); 2538 } 2539 2540 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 2541 n_entries = 1; 2542 if (drm_WARN_ON(&dev_priv->drm, 2543 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 2544 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 2545 2546 return index_to_dp_signal_levels[n_entries - 1] & 2547 DP_TRAIN_VOLTAGE_SWING_MASK; 2548 } 2549 2550 /* 2551 * We assume that the full set of pre-emphasis values can be 2552 * used on all DDI platforms. Should that change we need to 2553 * rethink this code. 2554 */ 2555 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 2556 { 2557 return DP_TRAIN_PRE_EMPH_LEVEL_3; 2558 } 2559 2560 static void cnl_ddi_vswing_program(struct intel_encoder *encoder, 2561 const struct intel_crtc_state *crtc_state, 2562 int level) 2563 { 2564 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2565 const struct cnl_ddi_buf_trans *ddi_translations; 2566 enum port port = encoder->port; 2567 int n_entries, ln; 2568 u32 val; 2569 2570 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 2571 ddi_translations = cnl_get_buf_trans_hdmi(encoder, &n_entries); 2572 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 2573 ddi_translations = cnl_get_buf_trans_edp(encoder, &n_entries); 2574 else 2575 ddi_translations = cnl_get_buf_trans_dp(encoder, &n_entries); 2576 2577 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 2578 return; 2579 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 2580 level = n_entries - 1; 2581 2582 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */ 2583 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 2584 val &= ~SCALING_MODE_SEL_MASK; 2585 val |= SCALING_MODE_SEL(2); 2586 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 2587 2588 /* Program PORT_TX_DW2 */ 2589 val = intel_de_read(dev_priv, CNL_PORT_TX_DW2_LN0(port)); 2590 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 2591 RCOMP_SCALAR_MASK); 2592 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); 2593 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); 2594 /* Rcomp scalar is fixed as 0x98 for every table entry */ 2595 val |= RCOMP_SCALAR(0x98); 2596 intel_de_write(dev_priv, CNL_PORT_TX_DW2_GRP(port), val); 2597 2598 /* Program PORT_TX_DW4 */ 2599 /* We cannot write to GRP. It would overrite individual loadgen */ 2600 for (ln = 0; ln < 4; ln++) { 2601 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port)); 2602 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 2603 CURSOR_COEFF_MASK); 2604 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); 2605 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); 2606 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); 2607 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val); 2608 } 2609 2610 /* Program PORT_TX_DW5 */ 2611 /* All DW5 values are fixed for every table entry */ 2612 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 2613 val &= ~RTERM_SELECT_MASK; 2614 val |= RTERM_SELECT(6); 2615 val |= TAP3_DISABLE; 2616 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 2617 2618 /* Program PORT_TX_DW7 */ 2619 val = intel_de_read(dev_priv, CNL_PORT_TX_DW7_LN0(port)); 2620 val &= ~N_SCALAR_MASK; 2621 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); 2622 intel_de_write(dev_priv, CNL_PORT_TX_DW7_GRP(port), val); 2623 } 2624 2625 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, 2626 const struct intel_crtc_state *crtc_state, 2627 int level) 2628 { 2629 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2630 enum port port = encoder->port; 2631 int width, rate, ln; 2632 u32 val; 2633 2634 width = crtc_state->lane_count; 2635 rate = crtc_state->port_clock; 2636 2637 /* 2638 * 1. If port type is eDP or DP, 2639 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 2640 * else clear to 0b. 2641 */ 2642 val = intel_de_read(dev_priv, CNL_PORT_PCS_DW1_LN0(port)); 2643 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 2644 val &= ~COMMON_KEEPER_EN; 2645 else 2646 val |= COMMON_KEEPER_EN; 2647 intel_de_write(dev_priv, CNL_PORT_PCS_DW1_GRP(port), val); 2648 2649 /* 2. Program loadgen select */ 2650 /* 2651 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes 2652 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2653 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2654 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 2655 */ 2656 for (ln = 0; ln <= 3; ln++) { 2657 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port)); 2658 val &= ~LOADGEN_SELECT; 2659 2660 if ((rate <= 600000 && width == 4 && ln >= 1) || 2661 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { 2662 val |= LOADGEN_SELECT; 2663 } 2664 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val); 2665 } 2666 2667 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 2668 val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5); 2669 val |= SUS_CLOCK_CONFIG; 2670 intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val); 2671 2672 /* 4. Clear training enable to change swing values */ 2673 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 2674 val &= ~TX_TRAINING_EN; 2675 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 2676 2677 /* 5. Program swing and de-emphasis */ 2678 cnl_ddi_vswing_program(encoder, crtc_state, level); 2679 2680 /* 6. Set training enable to trigger update */ 2681 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 2682 val |= TX_TRAINING_EN; 2683 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 2684 } 2685 2686 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 2687 const struct intel_crtc_state *crtc_state, 2688 int level) 2689 { 2690 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2691 const struct cnl_ddi_buf_trans *ddi_translations; 2692 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2693 int n_entries, ln; 2694 u32 val; 2695 2696 if (INTEL_GEN(dev_priv) >= 12) 2697 ddi_translations = tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries); 2698 else if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)) 2699 ddi_translations = jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries); 2700 else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) 2701 ddi_translations = ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries); 2702 else 2703 ddi_translations = icl_get_combo_buf_trans(encoder, crtc_state, &n_entries); 2704 if (!ddi_translations) 2705 return; 2706 2707 if (level >= n_entries) { 2708 drm_dbg_kms(&dev_priv->drm, 2709 "DDI translation not found for level %d. Using %d instead.", 2710 level, n_entries - 1); 2711 level = n_entries - 1; 2712 } 2713 2714 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 2715 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2716 2717 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 2718 intel_dp->hobl_active = is_hobl_buf_trans(ddi_translations); 2719 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, 2720 intel_dp->hobl_active ? val : 0); 2721 } 2722 2723 /* Set PORT_TX_DW5 */ 2724 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 2725 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 2726 TAP2_DISABLE | TAP3_DISABLE); 2727 val |= SCALING_MODE_SEL(0x2); 2728 val |= RTERM_SELECT(0x6); 2729 val |= TAP3_DISABLE; 2730 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 2731 2732 /* Program PORT_TX_DW2 */ 2733 val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy)); 2734 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 2735 RCOMP_SCALAR_MASK); 2736 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); 2737 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); 2738 /* Program Rcomp scalar for every table entry */ 2739 val |= RCOMP_SCALAR(0x98); 2740 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val); 2741 2742 /* Program PORT_TX_DW4 */ 2743 /* We cannot write to GRP. It would overwrite individual loadgen. */ 2744 for (ln = 0; ln <= 3; ln++) { 2745 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy)); 2746 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 2747 CURSOR_COEFF_MASK); 2748 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); 2749 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); 2750 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); 2751 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val); 2752 } 2753 2754 /* Program PORT_TX_DW7 */ 2755 val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy)); 2756 val &= ~N_SCALAR_MASK; 2757 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); 2758 intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val); 2759 } 2760 2761 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 2762 const struct intel_crtc_state *crtc_state, 2763 int level) 2764 { 2765 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2766 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2767 int width, rate, ln; 2768 u32 val; 2769 2770 width = crtc_state->lane_count; 2771 rate = crtc_state->port_clock; 2772 2773 /* 2774 * 1. If port type is eDP or DP, 2775 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 2776 * else clear to 0b. 2777 */ 2778 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy)); 2779 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 2780 val &= ~COMMON_KEEPER_EN; 2781 else 2782 val |= COMMON_KEEPER_EN; 2783 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 2784 2785 /* 2. Program loadgen select */ 2786 /* 2787 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes 2788 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2789 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2790 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 2791 */ 2792 for (ln = 0; ln <= 3; ln++) { 2793 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy)); 2794 val &= ~LOADGEN_SELECT; 2795 2796 if ((rate <= 600000 && width == 4 && ln >= 1) || 2797 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { 2798 val |= LOADGEN_SELECT; 2799 } 2800 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val); 2801 } 2802 2803 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 2804 val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); 2805 val |= SUS_CLOCK_CONFIG; 2806 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val); 2807 2808 /* 4. Clear training enable to change swing values */ 2809 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 2810 val &= ~TX_TRAINING_EN; 2811 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 2812 2813 /* 5. Program swing and de-emphasis */ 2814 icl_ddi_combo_vswing_program(encoder, crtc_state, level); 2815 2816 /* 6. Set training enable to trigger update */ 2817 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 2818 val |= TX_TRAINING_EN; 2819 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 2820 } 2821 2822 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 2823 const struct intel_crtc_state *crtc_state, 2824 int level) 2825 { 2826 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2827 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 2828 const struct icl_mg_phy_ddi_buf_trans *ddi_translations; 2829 int n_entries, ln; 2830 u32 val; 2831 2832 ddi_translations = icl_get_mg_buf_trans(encoder, crtc_state, &n_entries); 2833 /* The table does not have values for level 3 and level 9. */ 2834 if (level >= n_entries || level == 3 || level == 9) { 2835 drm_dbg_kms(&dev_priv->drm, 2836 "DDI translation not found for level %d. Using %d instead.", 2837 level, n_entries - 2); 2838 level = n_entries - 2; 2839 } 2840 2841 /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */ 2842 for (ln = 0; ln < 2; ln++) { 2843 val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port)); 2844 val &= ~CRI_USE_FS32; 2845 intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), val); 2846 2847 val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port)); 2848 val &= ~CRI_USE_FS32; 2849 intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), val); 2850 } 2851 2852 /* Program MG_TX_SWINGCTRL with values from vswing table */ 2853 for (ln = 0; ln < 2; ln++) { 2854 val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port)); 2855 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; 2856 val |= CRI_TXDEEMPH_OVERRIDE_17_12( 2857 ddi_translations[level].cri_txdeemph_override_17_12); 2858 intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val); 2859 2860 val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port)); 2861 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; 2862 val |= CRI_TXDEEMPH_OVERRIDE_17_12( 2863 ddi_translations[level].cri_txdeemph_override_17_12); 2864 intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val); 2865 } 2866 2867 /* Program MG_TX_DRVCTRL with values from vswing table */ 2868 for (ln = 0; ln < 2; ln++) { 2869 val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port)); 2870 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 2871 CRI_TXDEEMPH_OVERRIDE_5_0_MASK); 2872 val |= CRI_TXDEEMPH_OVERRIDE_5_0( 2873 ddi_translations[level].cri_txdeemph_override_5_0) | 2874 CRI_TXDEEMPH_OVERRIDE_11_6( 2875 ddi_translations[level].cri_txdeemph_override_11_6) | 2876 CRI_TXDEEMPH_OVERRIDE_EN; 2877 intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val); 2878 2879 val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port)); 2880 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 2881 CRI_TXDEEMPH_OVERRIDE_5_0_MASK); 2882 val |= CRI_TXDEEMPH_OVERRIDE_5_0( 2883 ddi_translations[level].cri_txdeemph_override_5_0) | 2884 CRI_TXDEEMPH_OVERRIDE_11_6( 2885 ddi_translations[level].cri_txdeemph_override_11_6) | 2886 CRI_TXDEEMPH_OVERRIDE_EN; 2887 intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val); 2888 2889 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 2890 } 2891 2892 /* 2893 * Program MG_CLKHUB<LN, port being used> with value from frequency table 2894 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 2895 * values from table for which TX1 and TX2 enabled. 2896 */ 2897 for (ln = 0; ln < 2; ln++) { 2898 val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port)); 2899 if (crtc_state->port_clock < 300000) 2900 val |= CFG_LOW_RATE_LKREN_EN; 2901 else 2902 val &= ~CFG_LOW_RATE_LKREN_EN; 2903 intel_de_write(dev_priv, MG_CLKHUB(ln, tc_port), val); 2904 } 2905 2906 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 2907 for (ln = 0; ln < 2; ln++) { 2908 val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port)); 2909 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; 2910 if (crtc_state->port_clock <= 500000) { 2911 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; 2912 } else { 2913 val |= CFG_AMI_CK_DIV_OVERRIDE_EN | 2914 CFG_AMI_CK_DIV_OVERRIDE_VAL(1); 2915 } 2916 intel_de_write(dev_priv, MG_TX1_DCC(ln, tc_port), val); 2917 2918 val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port)); 2919 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; 2920 if (crtc_state->port_clock <= 500000) { 2921 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; 2922 } else { 2923 val |= CFG_AMI_CK_DIV_OVERRIDE_EN | 2924 CFG_AMI_CK_DIV_OVERRIDE_VAL(1); 2925 } 2926 intel_de_write(dev_priv, MG_TX2_DCC(ln, tc_port), val); 2927 } 2928 2929 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 2930 for (ln = 0; ln < 2; ln++) { 2931 val = intel_de_read(dev_priv, 2932 MG_TX1_PISO_READLOAD(ln, tc_port)); 2933 val |= CRI_CALCINIT; 2934 intel_de_write(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 2935 val); 2936 2937 val = intel_de_read(dev_priv, 2938 MG_TX2_PISO_READLOAD(ln, tc_port)); 2939 val |= CRI_CALCINIT; 2940 intel_de_write(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 2941 val); 2942 } 2943 } 2944 2945 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder, 2946 const struct intel_crtc_state *crtc_state, 2947 int level) 2948 { 2949 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2950 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2951 2952 if (intel_phy_is_combo(dev_priv, phy)) 2953 icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level); 2954 else 2955 icl_mg_phy_ddi_vswing_sequence(encoder, crtc_state, level); 2956 } 2957 2958 static void 2959 tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 2960 const struct intel_crtc_state *crtc_state, 2961 int level) 2962 { 2963 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2964 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 2965 const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations; 2966 u32 val, dpcnt_mask, dpcnt_val; 2967 int n_entries, ln; 2968 2969 ddi_translations = tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries); 2970 2971 if (level >= n_entries) 2972 level = n_entries - 1; 2973 2974 dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK | 2975 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 2976 DKL_TX_VSWING_CONTROL_MASK); 2977 dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control); 2978 dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control); 2979 dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control); 2980 2981 for (ln = 0; ln < 2; ln++) { 2982 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2983 HIP_INDEX_VAL(tc_port, ln)); 2984 2985 intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0); 2986 2987 /* All the registers are RMW */ 2988 val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(tc_port)); 2989 val &= ~dpcnt_mask; 2990 val |= dpcnt_val; 2991 intel_de_write(dev_priv, DKL_TX_DPCNTL0(tc_port), val); 2992 2993 val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(tc_port)); 2994 val &= ~dpcnt_mask; 2995 val |= dpcnt_val; 2996 intel_de_write(dev_priv, DKL_TX_DPCNTL1(tc_port), val); 2997 2998 val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port)); 2999 val &= ~DKL_TX_DP20BITMODE; 3000 intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val); 3001 } 3002 } 3003 3004 static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder, 3005 const struct intel_crtc_state *crtc_state, 3006 int level) 3007 { 3008 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3009 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3010 3011 if (intel_phy_is_combo(dev_priv, phy)) 3012 icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level); 3013 else 3014 tgl_dkl_phy_ddi_vswing_sequence(encoder, crtc_state, level); 3015 } 3016 3017 static int translate_signal_level(struct intel_dp *intel_dp, 3018 u8 signal_levels) 3019 { 3020 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3021 int i; 3022 3023 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 3024 if (index_to_dp_signal_levels[i] == signal_levels) 3025 return i; 3026 } 3027 3028 drm_WARN(&i915->drm, 1, 3029 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 3030 signal_levels); 3031 3032 return 0; 3033 } 3034 3035 static int intel_ddi_dp_level(struct intel_dp *intel_dp) 3036 { 3037 u8 train_set = intel_dp->train_set[0]; 3038 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 3039 DP_TRAIN_PRE_EMPHASIS_MASK); 3040 3041 return translate_signal_level(intel_dp, signal_levels); 3042 } 3043 3044 static void 3045 tgl_set_signal_levels(struct intel_dp *intel_dp, 3046 const struct intel_crtc_state *crtc_state) 3047 { 3048 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3049 int level = intel_ddi_dp_level(intel_dp); 3050 3051 tgl_ddi_vswing_sequence(encoder, crtc_state, level); 3052 } 3053 3054 static void 3055 icl_set_signal_levels(struct intel_dp *intel_dp, 3056 const struct intel_crtc_state *crtc_state) 3057 { 3058 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3059 int level = intel_ddi_dp_level(intel_dp); 3060 3061 icl_ddi_vswing_sequence(encoder, crtc_state, level); 3062 } 3063 3064 static void 3065 cnl_set_signal_levels(struct intel_dp *intel_dp, 3066 const struct intel_crtc_state *crtc_state) 3067 { 3068 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3069 int level = intel_ddi_dp_level(intel_dp); 3070 3071 cnl_ddi_vswing_sequence(encoder, crtc_state, level); 3072 } 3073 3074 static void 3075 bxt_set_signal_levels(struct intel_dp *intel_dp, 3076 const struct intel_crtc_state *crtc_state) 3077 { 3078 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3079 int level = intel_ddi_dp_level(intel_dp); 3080 3081 bxt_ddi_vswing_sequence(encoder, crtc_state, level); 3082 } 3083 3084 static void 3085 hsw_set_signal_levels(struct intel_dp *intel_dp, 3086 const struct intel_crtc_state *crtc_state) 3087 { 3088 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3089 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3090 int level = intel_ddi_dp_level(intel_dp); 3091 enum port port = encoder->port; 3092 u32 signal_levels; 3093 3094 signal_levels = DDI_BUF_TRANS_SELECT(level); 3095 3096 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 3097 signal_levels); 3098 3099 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 3100 intel_dp->DP |= signal_levels; 3101 3102 if (IS_GEN9_BC(dev_priv)) 3103 skl_ddi_set_iboost(encoder, crtc_state, level); 3104 3105 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3106 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3107 } 3108 3109 static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv, 3110 enum phy phy) 3111 { 3112 if (IS_ROCKETLAKE(dev_priv)) { 3113 return RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 3114 } else if (intel_phy_is_combo(dev_priv, phy)) { 3115 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 3116 } else if (intel_phy_is_tc(dev_priv, phy)) { 3117 enum tc_port tc_port = intel_port_to_tc(dev_priv, 3118 (enum port)phy); 3119 3120 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port); 3121 } 3122 3123 return 0; 3124 } 3125 3126 static void dg1_map_plls_to_ports(struct intel_encoder *encoder, 3127 const struct intel_crtc_state *crtc_state) 3128 { 3129 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3130 struct intel_shared_dpll *pll = crtc_state->shared_dpll; 3131 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3132 u32 val; 3133 3134 /* 3135 * If we fail this, something went very wrong: first 2 PLLs should be 3136 * used by first 2 phys and last 2 PLLs by last phys 3137 */ 3138 if (drm_WARN_ON(&dev_priv->drm, 3139 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 3140 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 3141 return; 3142 3143 mutex_lock(&dev_priv->dpll.lock); 3144 3145 val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy)); 3146 drm_WARN_ON(&dev_priv->drm, 3147 (val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)) == 0); 3148 3149 val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 3150 val |= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 3151 intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val); 3152 intel_de_posting_read(dev_priv, DG1_DPCLKA_CFGCR0(phy)); 3153 3154 val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 3155 intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val); 3156 3157 mutex_unlock(&dev_priv->dpll.lock); 3158 } 3159 3160 static void icl_map_plls_to_ports(struct intel_encoder *encoder, 3161 const struct intel_crtc_state *crtc_state) 3162 { 3163 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3164 struct intel_shared_dpll *pll = crtc_state->shared_dpll; 3165 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3166 u32 val; 3167 3168 mutex_lock(&dev_priv->dpll.lock); 3169 3170 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 3171 drm_WARN_ON(&dev_priv->drm, 3172 (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0); 3173 3174 if (intel_phy_is_combo(dev_priv, phy)) { 3175 u32 mask, sel; 3176 3177 if (IS_ROCKETLAKE(dev_priv)) { 3178 mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 3179 sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 3180 } else { 3181 mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 3182 sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 3183 } 3184 3185 /* 3186 * Even though this register references DDIs, note that we 3187 * want to pass the PHY rather than the port (DDI). For 3188 * ICL, port=phy in all cases so it doesn't matter, but for 3189 * EHL the bspec notes the following: 3190 * 3191 * "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA 3192 * Clock Select chooses the PLL for both DDIA and DDID and 3193 * drives port A in all cases." 3194 */ 3195 val &= ~mask; 3196 val |= sel; 3197 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 3198 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); 3199 } 3200 3201 val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 3202 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 3203 3204 mutex_unlock(&dev_priv->dpll.lock); 3205 } 3206 3207 static void dg1_unmap_plls_to_ports(struct intel_encoder *encoder) 3208 { 3209 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3210 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3211 3212 mutex_lock(&dev_priv->dpll.lock); 3213 3214 intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), 0, 3215 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 3216 3217 mutex_unlock(&dev_priv->dpll.lock); 3218 } 3219 3220 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder) 3221 { 3222 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3223 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3224 u32 val; 3225 3226 mutex_lock(&dev_priv->dpll.lock); 3227 3228 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 3229 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 3230 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 3231 3232 mutex_unlock(&dev_priv->dpll.lock); 3233 } 3234 3235 static void dg1_sanitize_port_clk_off(struct drm_i915_private *dev_priv, 3236 u32 port_mask, bool ddi_clk_needed) 3237 { 3238 enum port port; 3239 u32 val; 3240 3241 for_each_port_masked(port, port_mask) { 3242 enum phy phy = intel_port_to_phy(dev_priv, port); 3243 bool ddi_clk_off; 3244 3245 val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy)); 3246 ddi_clk_off = val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 3247 3248 if (ddi_clk_needed == !ddi_clk_off) 3249 continue; 3250 3251 /* 3252 * Punt on the case now where clock is gated, but it would 3253 * be needed by the port. Something else is really broken then. 3254 */ 3255 if (drm_WARN_ON(&dev_priv->drm, ddi_clk_needed)) 3256 continue; 3257 3258 drm_notice(&dev_priv->drm, 3259 "PHY %c is disabled with an ungated DDI clock, gate it\n", 3260 phy_name(phy)); 3261 val |= DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 3262 intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val); 3263 } 3264 } 3265 3266 static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv, 3267 u32 port_mask, bool ddi_clk_needed) 3268 { 3269 enum port port; 3270 u32 val; 3271 3272 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 3273 for_each_port_masked(port, port_mask) { 3274 enum phy phy = intel_port_to_phy(dev_priv, port); 3275 bool ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv, 3276 phy); 3277 3278 if (ddi_clk_needed == !ddi_clk_off) 3279 continue; 3280 3281 /* 3282 * Punt on the case now where clock is gated, but it would 3283 * be needed by the port. Something else is really broken then. 3284 */ 3285 if (drm_WARN_ON(&dev_priv->drm, ddi_clk_needed)) 3286 continue; 3287 3288 drm_notice(&dev_priv->drm, 3289 "PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n", 3290 phy_name(phy)); 3291 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 3292 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 3293 } 3294 } 3295 3296 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 3297 { 3298 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3299 u32 port_mask; 3300 bool ddi_clk_needed; 3301 3302 /* 3303 * In case of DP MST, we sanitize the primary encoder only, not the 3304 * virtual ones. 3305 */ 3306 if (encoder->type == INTEL_OUTPUT_DP_MST) 3307 return; 3308 3309 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 3310 u8 pipe_mask; 3311 bool is_mst; 3312 3313 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 3314 /* 3315 * In the unlikely case that BIOS enables DP in MST mode, just 3316 * warn since our MST HW readout is incomplete. 3317 */ 3318 if (drm_WARN_ON(&dev_priv->drm, is_mst)) 3319 return; 3320 } 3321 3322 port_mask = BIT(encoder->port); 3323 ddi_clk_needed = encoder->base.crtc; 3324 3325 if (encoder->type == INTEL_OUTPUT_DSI) { 3326 struct intel_encoder *other_encoder; 3327 3328 port_mask = intel_dsi_encoder_ports(encoder); 3329 /* 3330 * Sanity check that we haven't incorrectly registered another 3331 * encoder using any of the ports of this DSI encoder. 3332 */ 3333 for_each_intel_encoder(&dev_priv->drm, other_encoder) { 3334 if (other_encoder == encoder) 3335 continue; 3336 3337 if (drm_WARN_ON(&dev_priv->drm, 3338 port_mask & BIT(other_encoder->port))) 3339 return; 3340 } 3341 /* 3342 * For DSI we keep the ddi clocks gated 3343 * except during enable/disable sequence. 3344 */ 3345 ddi_clk_needed = false; 3346 } 3347 3348 if (IS_DG1(dev_priv)) 3349 dg1_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed); 3350 else 3351 icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed); 3352 } 3353 3354 static void intel_ddi_clk_select(struct intel_encoder *encoder, 3355 const struct intel_crtc_state *crtc_state) 3356 { 3357 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3358 enum port port = encoder->port; 3359 enum phy phy = intel_port_to_phy(dev_priv, port); 3360 u32 val; 3361 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 3362 3363 if (drm_WARN_ON(&dev_priv->drm, !pll)) 3364 return; 3365 3366 mutex_lock(&dev_priv->dpll.lock); 3367 3368 if (INTEL_GEN(dev_priv) >= 11) { 3369 if (!intel_phy_is_combo(dev_priv, phy)) 3370 intel_de_write(dev_priv, DDI_CLK_SEL(port), 3371 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 3372 else if (IS_JSL_EHL(dev_priv) && port >= PORT_C) 3373 /* 3374 * MG does not exist but the programming is required 3375 * to ungate DDIC and DDID 3376 */ 3377 intel_de_write(dev_priv, DDI_CLK_SEL(port), 3378 DDI_CLK_SEL_MG); 3379 } else if (IS_CANNONLAKE(dev_priv)) { 3380 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */ 3381 val = intel_de_read(dev_priv, DPCLKA_CFGCR0); 3382 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); 3383 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port); 3384 intel_de_write(dev_priv, DPCLKA_CFGCR0, val); 3385 3386 /* 3387 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI. 3388 * This step and the step before must be done with separate 3389 * register writes. 3390 */ 3391 val = intel_de_read(dev_priv, DPCLKA_CFGCR0); 3392 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); 3393 intel_de_write(dev_priv, DPCLKA_CFGCR0, val); 3394 } else if (IS_GEN9_BC(dev_priv)) { 3395 /* DDI -> PLL mapping */ 3396 val = intel_de_read(dev_priv, DPLL_CTRL2); 3397 3398 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | 3399 DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); 3400 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 3401 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 3402 3403 intel_de_write(dev_priv, DPLL_CTRL2, val); 3404 3405 } else if (INTEL_GEN(dev_priv) < 9) { 3406 intel_de_write(dev_priv, PORT_CLK_SEL(port), 3407 hsw_pll_to_ddi_pll_sel(pll)); 3408 } 3409 3410 mutex_unlock(&dev_priv->dpll.lock); 3411 } 3412 3413 static void intel_ddi_clk_disable(struct intel_encoder *encoder) 3414 { 3415 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3416 enum port port = encoder->port; 3417 enum phy phy = intel_port_to_phy(dev_priv, port); 3418 3419 if (INTEL_GEN(dev_priv) >= 11) { 3420 if (!intel_phy_is_combo(dev_priv, phy) || 3421 (IS_JSL_EHL(dev_priv) && port >= PORT_C)) 3422 intel_de_write(dev_priv, DDI_CLK_SEL(port), 3423 DDI_CLK_SEL_NONE); 3424 } else if (IS_CANNONLAKE(dev_priv)) { 3425 intel_de_write(dev_priv, DPCLKA_CFGCR0, 3426 intel_de_read(dev_priv, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port)); 3427 } else if (IS_GEN9_BC(dev_priv)) { 3428 intel_de_write(dev_priv, DPLL_CTRL2, 3429 intel_de_read(dev_priv, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port)); 3430 } else if (INTEL_GEN(dev_priv) < 9) { 3431 intel_de_write(dev_priv, PORT_CLK_SEL(port), 3432 PORT_CLK_SEL_NONE); 3433 } 3434 } 3435 3436 static void 3437 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 3438 const struct intel_crtc_state *crtc_state) 3439 { 3440 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 3441 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port); 3442 u32 ln0, ln1, pin_assignment; 3443 u8 width; 3444 3445 if (dig_port->tc_mode == TC_PORT_TBT_ALT) 3446 return; 3447 3448 if (INTEL_GEN(dev_priv) >= 12) { 3449 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 3450 HIP_INDEX_VAL(tc_port, 0x0)); 3451 ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); 3452 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 3453 HIP_INDEX_VAL(tc_port, 0x1)); 3454 ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); 3455 } else { 3456 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 3457 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 3458 } 3459 3460 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 3461 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 3462 3463 /* DPPATC */ 3464 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 3465 width = crtc_state->lane_count; 3466 3467 switch (pin_assignment) { 3468 case 0x0: 3469 drm_WARN_ON(&dev_priv->drm, 3470 dig_port->tc_mode != TC_PORT_LEGACY); 3471 if (width == 1) { 3472 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 3473 } else { 3474 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3475 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3476 } 3477 break; 3478 case 0x1: 3479 if (width == 4) { 3480 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3481 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3482 } 3483 break; 3484 case 0x2: 3485 if (width == 2) { 3486 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3487 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3488 } 3489 break; 3490 case 0x3: 3491 case 0x5: 3492 if (width == 1) { 3493 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 3494 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 3495 } else { 3496 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3497 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3498 } 3499 break; 3500 case 0x4: 3501 case 0x6: 3502 if (width == 1) { 3503 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 3504 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 3505 } else { 3506 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3507 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3508 } 3509 break; 3510 default: 3511 MISSING_CASE(pin_assignment); 3512 } 3513 3514 if (INTEL_GEN(dev_priv) >= 12) { 3515 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 3516 HIP_INDEX_VAL(tc_port, 0x0)); 3517 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0); 3518 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 3519 HIP_INDEX_VAL(tc_port, 0x1)); 3520 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1); 3521 } else { 3522 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 3523 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 3524 } 3525 } 3526 3527 static enum transcoder 3528 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 3529 { 3530 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 3531 return crtc_state->mst_master_transcoder; 3532 else 3533 return crtc_state->cpu_transcoder; 3534 } 3535 3536 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 3537 const struct intel_crtc_state *crtc_state) 3538 { 3539 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3540 3541 if (INTEL_GEN(dev_priv) >= 12) 3542 return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state)); 3543 else 3544 return DP_TP_CTL(encoder->port); 3545 } 3546 3547 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 3548 const struct intel_crtc_state *crtc_state) 3549 { 3550 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3551 3552 if (INTEL_GEN(dev_priv) >= 12) 3553 return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state)); 3554 else 3555 return DP_TP_STATUS(encoder->port); 3556 } 3557 3558 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 3559 const struct intel_crtc_state *crtc_state) 3560 { 3561 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3562 3563 if (!crtc_state->fec_enable) 3564 return; 3565 3566 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0) 3567 drm_dbg_kms(&i915->drm, 3568 "Failed to set FEC_READY in the sink\n"); 3569 } 3570 3571 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 3572 const struct intel_crtc_state *crtc_state) 3573 { 3574 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3575 struct intel_dp *intel_dp; 3576 u32 val; 3577 3578 if (!crtc_state->fec_enable) 3579 return; 3580 3581 intel_dp = enc_to_intel_dp(encoder); 3582 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3583 val |= DP_TP_CTL_FEC_ENABLE; 3584 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 3585 } 3586 3587 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder, 3588 const struct intel_crtc_state *crtc_state) 3589 { 3590 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3591 struct intel_dp *intel_dp; 3592 u32 val; 3593 3594 if (!crtc_state->fec_enable) 3595 return; 3596 3597 intel_dp = enc_to_intel_dp(encoder); 3598 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3599 val &= ~DP_TP_CTL_FEC_ENABLE; 3600 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 3601 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3602 } 3603 3604 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 3605 struct intel_encoder *encoder, 3606 const struct intel_crtc_state *crtc_state, 3607 const struct drm_connector_state *conn_state) 3608 { 3609 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3610 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3611 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3612 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3613 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 3614 int level = intel_ddi_dp_level(intel_dp); 3615 3616 intel_dp_set_link_params(intel_dp, 3617 crtc_state->port_clock, 3618 crtc_state->lane_count); 3619 3620 /* 3621 * 1. Enable Power Wells 3622 * 3623 * This was handled at the beginning of intel_atomic_commit_tail(), 3624 * before we called down into this function. 3625 */ 3626 3627 /* 2. Enable Panel Power if PPS is required */ 3628 intel_edp_panel_on(intel_dp); 3629 3630 /* 3631 * 3. For non-TBT Type-C ports, set FIA lane count 3632 * (DFLEXDPSP.DPX4TXLATC) 3633 * 3634 * This was done before tgl_ddi_pre_enable_dp by 3635 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 3636 */ 3637 3638 /* 3639 * 4. Enable the port PLL. 3640 * 3641 * The PLL enabling itself was already done before this function by 3642 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 3643 * configure the PLL to port mapping here. 3644 */ 3645 intel_ddi_clk_select(encoder, crtc_state); 3646 3647 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 3648 if (!intel_phy_is_tc(dev_priv, phy) || 3649 dig_port->tc_mode != TC_PORT_TBT_ALT) { 3650 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 3651 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 3652 dig_port->ddi_io_power_domain); 3653 } 3654 3655 /* 6. Program DP_MODE */ 3656 icl_program_mg_dp_mode(dig_port, crtc_state); 3657 3658 /* 3659 * 7. The rest of the below are substeps under the bspec's "Enable and 3660 * Train Display Port" step. Note that steps that are specific to 3661 * MST will be handled by intel_mst_pre_enable_dp() before/after it 3662 * calls into this function. Also intel_mst_pre_enable_dp() only calls 3663 * us when active_mst_links==0, so any steps designated for "single 3664 * stream or multi-stream master transcoder" can just be performed 3665 * unconditionally here. 3666 */ 3667 3668 /* 3669 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 3670 * Transcoder. 3671 */ 3672 intel_ddi_enable_pipe_clock(encoder, crtc_state); 3673 3674 /* 3675 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 3676 * Transport Select 3677 */ 3678 intel_ddi_config_transcoder_func(encoder, crtc_state); 3679 3680 /* 3681 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 3682 * selected 3683 * 3684 * This will be handled by the intel_dp_start_link_train() farther 3685 * down this function. 3686 */ 3687 3688 /* 7.e Configure voltage swing and related IO settings */ 3689 tgl_ddi_vswing_sequence(encoder, crtc_state, level); 3690 3691 /* 3692 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 3693 * the used lanes of the DDI. 3694 */ 3695 if (intel_phy_is_combo(dev_priv, phy)) { 3696 bool lane_reversal = 3697 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 3698 3699 intel_combo_phy_power_up_lanes(dev_priv, phy, false, 3700 crtc_state->lane_count, 3701 lane_reversal); 3702 } 3703 3704 /* 3705 * 7.g Configure and enable DDI_BUF_CTL 3706 * 7.h Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout 3707 * after 500 us. 3708 * 3709 * We only configure what the register value will be here. Actual 3710 * enabling happens during link training farther down. 3711 */ 3712 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 3713 3714 if (!is_mst) 3715 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 3716 3717 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 3718 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); 3719 /* 3720 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 3721 * in the FEC_CONFIGURATION register to 1 before initiating link 3722 * training 3723 */ 3724 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 3725 3726 intel_dp_check_frl_training(intel_dp); 3727 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 3728 3729 /* 3730 * 7.i Follow DisplayPort specification training sequence (see notes for 3731 * failure handling) 3732 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 3733 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 3734 * (timeout after 800 us) 3735 */ 3736 intel_dp_start_link_train(intel_dp, crtc_state); 3737 3738 /* 7.k Set DP_TP_CTL link training to Normal */ 3739 if (!is_trans_port_sync_mode(crtc_state)) 3740 intel_dp_stop_link_train(intel_dp, crtc_state); 3741 3742 /* 7.l Configure and enable FEC if needed */ 3743 intel_ddi_enable_fec(encoder, crtc_state); 3744 if (!crtc_state->bigjoiner) 3745 intel_dsc_enable(encoder, crtc_state); 3746 } 3747 3748 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 3749 struct intel_encoder *encoder, 3750 const struct intel_crtc_state *crtc_state, 3751 const struct drm_connector_state *conn_state) 3752 { 3753 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3754 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3755 enum port port = encoder->port; 3756 enum phy phy = intel_port_to_phy(dev_priv, port); 3757 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3758 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 3759 int level = intel_ddi_dp_level(intel_dp); 3760 3761 if (INTEL_GEN(dev_priv) < 11) 3762 drm_WARN_ON(&dev_priv->drm, 3763 is_mst && (port == PORT_A || port == PORT_E)); 3764 else 3765 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 3766 3767 intel_dp_set_link_params(intel_dp, 3768 crtc_state->port_clock, 3769 crtc_state->lane_count); 3770 3771 intel_edp_panel_on(intel_dp); 3772 3773 intel_ddi_clk_select(encoder, crtc_state); 3774 3775 if (!intel_phy_is_tc(dev_priv, phy) || 3776 dig_port->tc_mode != TC_PORT_TBT_ALT) { 3777 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 3778 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 3779 dig_port->ddi_io_power_domain); 3780 } 3781 3782 icl_program_mg_dp_mode(dig_port, crtc_state); 3783 3784 if (INTEL_GEN(dev_priv) >= 11) 3785 icl_ddi_vswing_sequence(encoder, crtc_state, level); 3786 else if (IS_CANNONLAKE(dev_priv)) 3787 cnl_ddi_vswing_sequence(encoder, crtc_state, level); 3788 else if (IS_GEN9_LP(dev_priv)) 3789 bxt_ddi_vswing_sequence(encoder, crtc_state, level); 3790 else 3791 intel_prepare_dp_ddi_buffers(encoder, crtc_state); 3792 3793 if (intel_phy_is_combo(dev_priv, phy)) { 3794 bool lane_reversal = 3795 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 3796 3797 intel_combo_phy_power_up_lanes(dev_priv, phy, false, 3798 crtc_state->lane_count, 3799 lane_reversal); 3800 } 3801 3802 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 3803 if (!is_mst) 3804 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 3805 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 3806 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, 3807 true); 3808 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 3809 intel_dp_start_link_train(intel_dp, crtc_state); 3810 if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) && 3811 !is_trans_port_sync_mode(crtc_state)) 3812 intel_dp_stop_link_train(intel_dp, crtc_state); 3813 3814 intel_ddi_enable_fec(encoder, crtc_state); 3815 3816 if (!is_mst) 3817 intel_ddi_enable_pipe_clock(encoder, crtc_state); 3818 3819 if (!crtc_state->bigjoiner) 3820 intel_dsc_enable(encoder, crtc_state); 3821 } 3822 3823 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 3824 struct intel_encoder *encoder, 3825 const struct intel_crtc_state *crtc_state, 3826 const struct drm_connector_state *conn_state) 3827 { 3828 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3829 3830 if (INTEL_GEN(dev_priv) >= 12) 3831 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 3832 else 3833 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 3834 3835 /* MST will call a setting of MSA after an allocating of Virtual Channel 3836 * from MST encoder pre_enable callback. 3837 */ 3838 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3839 intel_ddi_set_dp_msa(crtc_state, conn_state); 3840 3841 intel_dp_set_m_n(crtc_state, M1_N1); 3842 } 3843 } 3844 3845 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 3846 struct intel_encoder *encoder, 3847 const struct intel_crtc_state *crtc_state, 3848 const struct drm_connector_state *conn_state) 3849 { 3850 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3851 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3852 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3853 int level = intel_ddi_hdmi_level(encoder, crtc_state); 3854 3855 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 3856 intel_ddi_clk_select(encoder, crtc_state); 3857 3858 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 3859 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 3860 dig_port->ddi_io_power_domain); 3861 3862 icl_program_mg_dp_mode(dig_port, crtc_state); 3863 3864 if (INTEL_GEN(dev_priv) >= 12) 3865 tgl_ddi_vswing_sequence(encoder, crtc_state, level); 3866 else if (INTEL_GEN(dev_priv) == 11) 3867 icl_ddi_vswing_sequence(encoder, crtc_state, level); 3868 else if (IS_CANNONLAKE(dev_priv)) 3869 cnl_ddi_vswing_sequence(encoder, crtc_state, level); 3870 else if (IS_GEN9_LP(dev_priv)) 3871 bxt_ddi_vswing_sequence(encoder, crtc_state, level); 3872 else 3873 intel_prepare_hdmi_ddi_buffers(encoder, level); 3874 3875 if (IS_GEN9_BC(dev_priv)) 3876 skl_ddi_set_iboost(encoder, crtc_state, level); 3877 3878 intel_ddi_enable_pipe_clock(encoder, crtc_state); 3879 3880 dig_port->set_infoframes(encoder, 3881 crtc_state->has_infoframe, 3882 crtc_state, conn_state); 3883 } 3884 3885 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 3886 struct intel_encoder *encoder, 3887 const struct intel_crtc_state *crtc_state, 3888 const struct drm_connector_state *conn_state) 3889 { 3890 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3891 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3892 enum pipe pipe = crtc->pipe; 3893 3894 /* 3895 * When called from DP MST code: 3896 * - conn_state will be NULL 3897 * - encoder will be the main encoder (ie. mst->primary) 3898 * - the main connector associated with this port 3899 * won't be active or linked to a crtc 3900 * - crtc_state will be the state of the first stream to 3901 * be activated on this port, and it may not be the same 3902 * stream that will be deactivated last, but each stream 3903 * should have a state that is identical when it comes to 3904 * the DP link parameteres 3905 */ 3906 3907 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 3908 3909 if (IS_DG1(dev_priv)) 3910 dg1_map_plls_to_ports(encoder, crtc_state); 3911 else if (INTEL_GEN(dev_priv) >= 11) 3912 icl_map_plls_to_ports(encoder, crtc_state); 3913 3914 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 3915 3916 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 3917 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 3918 conn_state); 3919 } else { 3920 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3921 3922 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 3923 conn_state); 3924 3925 /* FIXME precompute everything properly */ 3926 /* FIXME how do we turn infoframes off again? */ 3927 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) 3928 dig_port->set_infoframes(encoder, 3929 crtc_state->has_infoframe, 3930 crtc_state, conn_state); 3931 } 3932 } 3933 3934 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 3935 const struct intel_crtc_state *crtc_state) 3936 { 3937 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3938 enum port port = encoder->port; 3939 bool wait = false; 3940 u32 val; 3941 3942 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3943 if (val & DDI_BUF_CTL_ENABLE) { 3944 val &= ~DDI_BUF_CTL_ENABLE; 3945 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 3946 wait = true; 3947 } 3948 3949 if (intel_crtc_has_dp_encoder(crtc_state)) { 3950 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3951 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 3952 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 3953 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 3954 } 3955 3956 /* Disable FEC in DP Sink */ 3957 intel_ddi_disable_fec_state(encoder, crtc_state); 3958 3959 if (wait) 3960 intel_wait_ddi_buf_idle(dev_priv, port); 3961 } 3962 3963 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 3964 struct intel_encoder *encoder, 3965 const struct intel_crtc_state *old_crtc_state, 3966 const struct drm_connector_state *old_conn_state) 3967 { 3968 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3969 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3970 struct intel_dp *intel_dp = &dig_port->dp; 3971 bool is_mst = intel_crtc_has_type(old_crtc_state, 3972 INTEL_OUTPUT_DP_MST); 3973 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3974 3975 if (!is_mst) 3976 intel_dp_set_infoframes(encoder, false, 3977 old_crtc_state, old_conn_state); 3978 3979 /* 3980 * Power down sink before disabling the port, otherwise we end 3981 * up getting interrupts from the sink on detecting link loss. 3982 */ 3983 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 3984 3985 if (INTEL_GEN(dev_priv) >= 12) { 3986 if (is_mst) { 3987 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 3988 u32 val; 3989 3990 val = intel_de_read(dev_priv, 3991 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3992 val &= ~(TGL_TRANS_DDI_PORT_MASK | 3993 TRANS_DDI_MODE_SELECT_MASK); 3994 intel_de_write(dev_priv, 3995 TRANS_DDI_FUNC_CTL(cpu_transcoder), 3996 val); 3997 } 3998 } else { 3999 if (!is_mst) 4000 intel_ddi_disable_pipe_clock(old_crtc_state); 4001 } 4002 4003 intel_disable_ddi_buf(encoder, old_crtc_state); 4004 4005 /* 4006 * From TGL spec: "If single stream or multi-stream master transcoder: 4007 * Configure Transcoder Clock select to direct no clock to the 4008 * transcoder" 4009 */ 4010 if (INTEL_GEN(dev_priv) >= 12) 4011 intel_ddi_disable_pipe_clock(old_crtc_state); 4012 4013 intel_edp_panel_vdd_on(intel_dp); 4014 intel_edp_panel_off(intel_dp); 4015 4016 if (!intel_phy_is_tc(dev_priv, phy) || 4017 dig_port->tc_mode != TC_PORT_TBT_ALT) 4018 intel_display_power_put(dev_priv, 4019 dig_port->ddi_io_power_domain, 4020 fetch_and_zero(&dig_port->ddi_io_wakeref)); 4021 4022 intel_ddi_clk_disable(encoder); 4023 } 4024 4025 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 4026 struct intel_encoder *encoder, 4027 const struct intel_crtc_state *old_crtc_state, 4028 const struct drm_connector_state *old_conn_state) 4029 { 4030 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4031 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4032 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 4033 4034 dig_port->set_infoframes(encoder, false, 4035 old_crtc_state, old_conn_state); 4036 4037 intel_ddi_disable_pipe_clock(old_crtc_state); 4038 4039 intel_disable_ddi_buf(encoder, old_crtc_state); 4040 4041 intel_display_power_put(dev_priv, 4042 dig_port->ddi_io_power_domain, 4043 fetch_and_zero(&dig_port->ddi_io_wakeref)); 4044 4045 intel_ddi_clk_disable(encoder); 4046 4047 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 4048 } 4049 4050 static void intel_ddi_post_disable(struct intel_atomic_state *state, 4051 struct intel_encoder *encoder, 4052 const struct intel_crtc_state *old_crtc_state, 4053 const struct drm_connector_state *old_conn_state) 4054 { 4055 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4056 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4057 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 4058 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 4059 4060 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) { 4061 intel_crtc_vblank_off(old_crtc_state); 4062 4063 intel_disable_pipe(old_crtc_state); 4064 4065 intel_ddi_disable_transcoder_func(old_crtc_state); 4066 4067 intel_dsc_disable(old_crtc_state); 4068 4069 if (INTEL_GEN(dev_priv) >= 9) 4070 skl_scaler_disable(old_crtc_state); 4071 else 4072 ilk_pfit_disable(old_crtc_state); 4073 } 4074 4075 if (old_crtc_state->bigjoiner_linked_crtc) { 4076 struct intel_atomic_state *state = 4077 to_intel_atomic_state(old_crtc_state->uapi.state); 4078 struct intel_crtc *slave = 4079 old_crtc_state->bigjoiner_linked_crtc; 4080 const struct intel_crtc_state *old_slave_crtc_state = 4081 intel_atomic_get_old_crtc_state(state, slave); 4082 4083 intel_crtc_vblank_off(old_slave_crtc_state); 4084 trace_intel_pipe_disable(slave); 4085 4086 intel_dsc_disable(old_slave_crtc_state); 4087 skl_scaler_disable(old_slave_crtc_state); 4088 } 4089 4090 /* 4091 * When called from DP MST code: 4092 * - old_conn_state will be NULL 4093 * - encoder will be the main encoder (ie. mst->primary) 4094 * - the main connector associated with this port 4095 * won't be active or linked to a crtc 4096 * - old_crtc_state will be the state of the last stream to 4097 * be deactivated on this port, and it may not be the same 4098 * stream that was activated last, but each stream 4099 * should have a state that is identical when it comes to 4100 * the DP link parameteres 4101 */ 4102 4103 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 4104 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 4105 old_conn_state); 4106 else 4107 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 4108 old_conn_state); 4109 4110 if (IS_DG1(dev_priv)) 4111 dg1_unmap_plls_to_ports(encoder); 4112 else if (INTEL_GEN(dev_priv) >= 11) 4113 icl_unmap_plls_to_ports(encoder); 4114 4115 if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port) 4116 intel_display_power_put(dev_priv, 4117 intel_ddi_main_link_aux_domain(dig_port), 4118 fetch_and_zero(&dig_port->aux_wakeref)); 4119 4120 if (is_tc_port) 4121 intel_tc_port_put_link(dig_port); 4122 } 4123 4124 void intel_ddi_fdi_post_disable(struct intel_atomic_state *state, 4125 struct intel_encoder *encoder, 4126 const struct intel_crtc_state *old_crtc_state, 4127 const struct drm_connector_state *old_conn_state) 4128 { 4129 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4130 u32 val; 4131 4132 /* 4133 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable) 4134 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN, 4135 * step 13 is the correct place for it. Step 18 is where it was 4136 * originally before the BUN. 4137 */ 4138 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 4139 val &= ~FDI_RX_ENABLE; 4140 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 4141 4142 intel_disable_ddi_buf(encoder, old_crtc_state); 4143 intel_ddi_clk_disable(encoder); 4144 4145 val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); 4146 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 4147 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 4148 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val); 4149 4150 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 4151 val &= ~FDI_PCDCLK; 4152 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 4153 4154 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 4155 val &= ~FDI_RX_PLL_ENABLE; 4156 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 4157 } 4158 4159 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 4160 struct intel_encoder *encoder, 4161 const struct intel_crtc_state *crtc_state) 4162 { 4163 const struct drm_connector_state *conn_state; 4164 struct drm_connector *conn; 4165 int i; 4166 4167 if (!crtc_state->sync_mode_slaves_mask) 4168 return; 4169 4170 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 4171 struct intel_encoder *slave_encoder = 4172 to_intel_encoder(conn_state->best_encoder); 4173 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 4174 const struct intel_crtc_state *slave_crtc_state; 4175 4176 if (!slave_crtc) 4177 continue; 4178 4179 slave_crtc_state = 4180 intel_atomic_get_new_crtc_state(state, slave_crtc); 4181 4182 if (slave_crtc_state->master_transcoder != 4183 crtc_state->cpu_transcoder) 4184 continue; 4185 4186 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 4187 slave_crtc_state); 4188 } 4189 4190 usleep_range(200, 400); 4191 4192 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 4193 crtc_state); 4194 } 4195 4196 static void intel_enable_ddi_dp(struct intel_atomic_state *state, 4197 struct intel_encoder *encoder, 4198 const struct intel_crtc_state *crtc_state, 4199 const struct drm_connector_state *conn_state) 4200 { 4201 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4202 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4203 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4204 enum port port = encoder->port; 4205 4206 if (port == PORT_A && INTEL_GEN(dev_priv) < 9) 4207 intel_dp_stop_link_train(intel_dp, crtc_state); 4208 4209 intel_edp_backlight_on(crtc_state, conn_state); 4210 intel_psr_enable(intel_dp, crtc_state, conn_state); 4211 4212 if (!dig_port->lspcon.active || dig_port->dp.has_hdmi_sink) 4213 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 4214 4215 intel_edp_drrs_enable(intel_dp, crtc_state); 4216 4217 if (crtc_state->has_audio) 4218 intel_audio_codec_enable(encoder, crtc_state, conn_state); 4219 4220 trans_port_sync_stop_link_train(state, encoder, crtc_state); 4221 } 4222 4223 static i915_reg_t 4224 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 4225 enum port port) 4226 { 4227 static const enum transcoder trans[] = { 4228 [PORT_A] = TRANSCODER_EDP, 4229 [PORT_B] = TRANSCODER_A, 4230 [PORT_C] = TRANSCODER_B, 4231 [PORT_D] = TRANSCODER_C, 4232 [PORT_E] = TRANSCODER_A, 4233 }; 4234 4235 drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) < 9); 4236 4237 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) 4238 port = PORT_A; 4239 4240 return CHICKEN_TRANS(trans[port]); 4241 } 4242 4243 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, 4244 struct intel_encoder *encoder, 4245 const struct intel_crtc_state *crtc_state, 4246 const struct drm_connector_state *conn_state) 4247 { 4248 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4249 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4250 struct drm_connector *connector = conn_state->connector; 4251 enum port port = encoder->port; 4252 4253 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 4254 crtc_state->hdmi_high_tmds_clock_ratio, 4255 crtc_state->hdmi_scrambling)) 4256 drm_dbg_kms(&dev_priv->drm, 4257 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 4258 connector->base.id, connector->name); 4259 4260 /* Display WA #1143: skl,kbl,cfl */ 4261 if (IS_GEN9_BC(dev_priv)) { 4262 /* 4263 * For some reason these chicken bits have been 4264 * stuffed into a transcoder register, event though 4265 * the bits affect a specific DDI port rather than 4266 * a specific transcoder. 4267 */ 4268 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 4269 u32 val; 4270 4271 val = intel_de_read(dev_priv, reg); 4272 4273 if (port == PORT_E) 4274 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 4275 DDIE_TRAINING_OVERRIDE_VALUE; 4276 else 4277 val |= DDI_TRAINING_OVERRIDE_ENABLE | 4278 DDI_TRAINING_OVERRIDE_VALUE; 4279 4280 intel_de_write(dev_priv, reg, val); 4281 intel_de_posting_read(dev_priv, reg); 4282 4283 udelay(1); 4284 4285 if (port == PORT_E) 4286 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 4287 DDIE_TRAINING_OVERRIDE_VALUE); 4288 else 4289 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 4290 DDI_TRAINING_OVERRIDE_VALUE); 4291 4292 intel_de_write(dev_priv, reg, val); 4293 } 4294 4295 /* In HDMI/DVI mode, the port width, and swing/emphasis values 4296 * are ignored so nothing special needs to be done besides 4297 * enabling the port. 4298 */ 4299 intel_de_write(dev_priv, DDI_BUF_CTL(port), 4300 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE); 4301 4302 if (crtc_state->has_audio) 4303 intel_audio_codec_enable(encoder, crtc_state, conn_state); 4304 } 4305 4306 static void intel_enable_ddi(struct intel_atomic_state *state, 4307 struct intel_encoder *encoder, 4308 const struct intel_crtc_state *crtc_state, 4309 const struct drm_connector_state *conn_state) 4310 { 4311 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 4312 4313 if (!crtc_state->bigjoiner_slave) 4314 intel_ddi_enable_transcoder_func(encoder, crtc_state); 4315 4316 intel_enable_pipe(crtc_state); 4317 4318 intel_crtc_vblank_on(crtc_state); 4319 4320 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 4321 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state); 4322 else 4323 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state); 4324 4325 /* Enable hdcp if it's desired */ 4326 if (conn_state->content_protection == 4327 DRM_MODE_CONTENT_PROTECTION_DESIRED) 4328 intel_hdcp_enable(to_intel_connector(conn_state->connector), 4329 crtc_state->cpu_transcoder, 4330 (u8)conn_state->hdcp_content_type); 4331 } 4332 4333 static void intel_disable_ddi_dp(struct intel_atomic_state *state, 4334 struct intel_encoder *encoder, 4335 const struct intel_crtc_state *old_crtc_state, 4336 const struct drm_connector_state *old_conn_state) 4337 { 4338 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4339 4340 intel_dp->link_trained = false; 4341 4342 if (old_crtc_state->has_audio) 4343 intel_audio_codec_disable(encoder, 4344 old_crtc_state, old_conn_state); 4345 4346 intel_edp_drrs_disable(intel_dp, old_crtc_state); 4347 intel_psr_disable(intel_dp, old_crtc_state); 4348 intel_edp_backlight_off(old_conn_state); 4349 /* Disable the decompression in DP Sink */ 4350 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, 4351 false); 4352 } 4353 4354 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state, 4355 struct intel_encoder *encoder, 4356 const struct intel_crtc_state *old_crtc_state, 4357 const struct drm_connector_state *old_conn_state) 4358 { 4359 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4360 struct drm_connector *connector = old_conn_state->connector; 4361 4362 if (old_crtc_state->has_audio) 4363 intel_audio_codec_disable(encoder, 4364 old_crtc_state, old_conn_state); 4365 4366 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 4367 false, false)) 4368 drm_dbg_kms(&i915->drm, 4369 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 4370 connector->base.id, connector->name); 4371 } 4372 4373 static void intel_disable_ddi(struct intel_atomic_state *state, 4374 struct intel_encoder *encoder, 4375 const struct intel_crtc_state *old_crtc_state, 4376 const struct drm_connector_state *old_conn_state) 4377 { 4378 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 4379 4380 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 4381 intel_disable_ddi_hdmi(state, encoder, old_crtc_state, 4382 old_conn_state); 4383 else 4384 intel_disable_ddi_dp(state, encoder, old_crtc_state, 4385 old_conn_state); 4386 } 4387 4388 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 4389 struct intel_encoder *encoder, 4390 const struct intel_crtc_state *crtc_state, 4391 const struct drm_connector_state *conn_state) 4392 { 4393 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4394 4395 intel_ddi_set_dp_msa(crtc_state, conn_state); 4396 4397 intel_psr_update(intel_dp, crtc_state, conn_state); 4398 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 4399 intel_edp_drrs_update(intel_dp, crtc_state); 4400 4401 intel_panel_update_backlight(state, encoder, crtc_state, conn_state); 4402 } 4403 4404 void intel_ddi_update_pipe(struct intel_atomic_state *state, 4405 struct intel_encoder *encoder, 4406 const struct intel_crtc_state *crtc_state, 4407 const struct drm_connector_state *conn_state) 4408 { 4409 4410 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 4411 !intel_encoder_is_mst(encoder)) 4412 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 4413 conn_state); 4414 4415 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 4416 } 4417 4418 static void 4419 intel_ddi_update_prepare(struct intel_atomic_state *state, 4420 struct intel_encoder *encoder, 4421 struct intel_crtc *crtc) 4422 { 4423 struct intel_crtc_state *crtc_state = 4424 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL; 4425 int required_lanes = crtc_state ? crtc_state->lane_count : 1; 4426 4427 drm_WARN_ON(state->base.dev, crtc && crtc->active); 4428 4429 intel_tc_port_get_link(enc_to_dig_port(encoder), 4430 required_lanes); 4431 if (crtc_state && crtc_state->hw.active) 4432 intel_update_active_dpll(state, crtc, encoder); 4433 } 4434 4435 static void 4436 intel_ddi_update_complete(struct intel_atomic_state *state, 4437 struct intel_encoder *encoder, 4438 struct intel_crtc *crtc) 4439 { 4440 intel_tc_port_put_link(enc_to_dig_port(encoder)); 4441 } 4442 4443 static void 4444 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 4445 struct intel_encoder *encoder, 4446 const struct intel_crtc_state *crtc_state, 4447 const struct drm_connector_state *conn_state) 4448 { 4449 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4450 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4451 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 4452 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 4453 4454 if (is_tc_port) 4455 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 4456 4457 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) { 4458 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref); 4459 dig_port->aux_wakeref = 4460 intel_display_power_get(dev_priv, 4461 intel_ddi_main_link_aux_domain(dig_port)); 4462 } 4463 4464 if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT) 4465 /* 4466 * Program the lane count for static/dynamic connections on 4467 * Type-C ports. Skip this step for TBT. 4468 */ 4469 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 4470 else if (IS_GEN9_LP(dev_priv)) 4471 bxt_ddi_phy_set_lane_optim_mask(encoder, 4472 crtc_state->lane_lat_optim_mask); 4473 } 4474 4475 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 4476 const struct intel_crtc_state *crtc_state) 4477 { 4478 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 4479 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4480 enum port port = encoder->port; 4481 u32 dp_tp_ctl, ddi_buf_ctl; 4482 bool wait = false; 4483 4484 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 4485 4486 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 4487 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 4488 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 4489 intel_de_write(dev_priv, DDI_BUF_CTL(port), 4490 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 4491 wait = true; 4492 } 4493 4494 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 4495 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1; 4496 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 4497 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 4498 4499 if (wait) 4500 intel_wait_ddi_buf_idle(dev_priv, port); 4501 } 4502 4503 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 4504 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 4505 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 4506 } else { 4507 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 4508 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 4509 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4510 } 4511 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 4512 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 4513 4514 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 4515 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 4516 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 4517 4518 intel_wait_ddi_buf_active(dev_priv, port); 4519 } 4520 4521 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 4522 const struct intel_crtc_state *crtc_state, 4523 u8 dp_train_pat) 4524 { 4525 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 4526 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4527 u32 temp; 4528 4529 temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 4530 4531 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 4532 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 4533 case DP_TRAINING_PATTERN_DISABLE: 4534 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 4535 break; 4536 case DP_TRAINING_PATTERN_1: 4537 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 4538 break; 4539 case DP_TRAINING_PATTERN_2: 4540 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 4541 break; 4542 case DP_TRAINING_PATTERN_3: 4543 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 4544 break; 4545 case DP_TRAINING_PATTERN_4: 4546 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 4547 break; 4548 } 4549 4550 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp); 4551 } 4552 4553 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 4554 const struct intel_crtc_state *crtc_state) 4555 { 4556 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 4557 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4558 enum port port = encoder->port; 4559 u32 val; 4560 4561 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 4562 val &= ~DP_TP_CTL_LINK_TRAIN_MASK; 4563 val |= DP_TP_CTL_LINK_TRAIN_IDLE; 4564 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 4565 4566 /* 4567 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 4568 * reason we need to set idle transmission mode is to work around a HW 4569 * issue where we enable the pipe while not in idle link-training mode. 4570 * In this case there is requirement to wait for a minimum number of 4571 * idle patterns to be sent. 4572 */ 4573 if (port == PORT_A && INTEL_GEN(dev_priv) < 12) 4574 return; 4575 4576 if (intel_de_wait_for_set(dev_priv, 4577 dp_tp_status_reg(encoder, crtc_state), 4578 DP_TP_STATUS_IDLE_DONE, 1)) 4579 drm_err(&dev_priv->drm, 4580 "Timed out waiting for DP idle patterns\n"); 4581 } 4582 4583 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 4584 enum transcoder cpu_transcoder) 4585 { 4586 if (cpu_transcoder == TRANSCODER_EDP) 4587 return false; 4588 4589 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) 4590 return false; 4591 4592 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 4593 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 4594 } 4595 4596 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, 4597 struct intel_crtc_state *crtc_state) 4598 { 4599 if (INTEL_GEN(dev_priv) >= 12 && crtc_state->port_clock > 594000) 4600 crtc_state->min_voltage_level = 2; 4601 else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000) 4602 crtc_state->min_voltage_level = 3; 4603 else if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000) 4604 crtc_state->min_voltage_level = 1; 4605 else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000) 4606 crtc_state->min_voltage_level = 2; 4607 } 4608 4609 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, 4610 enum transcoder cpu_transcoder) 4611 { 4612 u32 master_select; 4613 4614 if (INTEL_GEN(dev_priv) >= 11) { 4615 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder)); 4616 4617 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 4618 return INVALID_TRANSCODER; 4619 4620 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 4621 } else { 4622 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 4623 4624 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 4625 return INVALID_TRANSCODER; 4626 4627 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 4628 } 4629 4630 if (master_select == 0) 4631 return TRANSCODER_EDP; 4632 else 4633 return master_select - 1; 4634 } 4635 4636 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 4637 { 4638 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 4639 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 4640 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 4641 enum transcoder cpu_transcoder; 4642 4643 crtc_state->master_transcoder = 4644 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); 4645 4646 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { 4647 enum intel_display_power_domain power_domain; 4648 intel_wakeref_t trans_wakeref; 4649 4650 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 4651 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 4652 power_domain); 4653 4654 if (!trans_wakeref) 4655 continue; 4656 4657 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == 4658 crtc_state->cpu_transcoder) 4659 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 4660 4661 intel_display_power_put(dev_priv, power_domain, trans_wakeref); 4662 } 4663 4664 drm_WARN_ON(&dev_priv->drm, 4665 crtc_state->master_transcoder != INVALID_TRANSCODER && 4666 crtc_state->sync_mode_slaves_mask); 4667 } 4668 4669 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 4670 struct intel_crtc_state *pipe_config) 4671 { 4672 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4673 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); 4674 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4675 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4676 u32 temp, flags = 0; 4677 4678 temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 4679 if (temp & TRANS_DDI_PHSYNC) 4680 flags |= DRM_MODE_FLAG_PHSYNC; 4681 else 4682 flags |= DRM_MODE_FLAG_NHSYNC; 4683 if (temp & TRANS_DDI_PVSYNC) 4684 flags |= DRM_MODE_FLAG_PVSYNC; 4685 else 4686 flags |= DRM_MODE_FLAG_NVSYNC; 4687 4688 pipe_config->hw.adjusted_mode.flags |= flags; 4689 4690 switch (temp & TRANS_DDI_BPC_MASK) { 4691 case TRANS_DDI_BPC_6: 4692 pipe_config->pipe_bpp = 18; 4693 break; 4694 case TRANS_DDI_BPC_8: 4695 pipe_config->pipe_bpp = 24; 4696 break; 4697 case TRANS_DDI_BPC_10: 4698 pipe_config->pipe_bpp = 30; 4699 break; 4700 case TRANS_DDI_BPC_12: 4701 pipe_config->pipe_bpp = 36; 4702 break; 4703 default: 4704 break; 4705 } 4706 4707 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 4708 case TRANS_DDI_MODE_SELECT_HDMI: 4709 pipe_config->has_hdmi_sink = true; 4710 4711 pipe_config->infoframes.enable |= 4712 intel_hdmi_infoframes_enabled(encoder, pipe_config); 4713 4714 if (pipe_config->infoframes.enable) 4715 pipe_config->has_infoframe = true; 4716 4717 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 4718 pipe_config->hdmi_scrambling = true; 4719 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 4720 pipe_config->hdmi_high_tmds_clock_ratio = true; 4721 fallthrough; 4722 case TRANS_DDI_MODE_SELECT_DVI: 4723 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 4724 pipe_config->lane_count = 4; 4725 break; 4726 case TRANS_DDI_MODE_SELECT_FDI: 4727 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 4728 break; 4729 case TRANS_DDI_MODE_SELECT_DP_SST: 4730 if (encoder->type == INTEL_OUTPUT_EDP) 4731 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 4732 else 4733 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 4734 pipe_config->lane_count = 4735 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4736 intel_dp_get_m_n(intel_crtc, pipe_config); 4737 4738 if (INTEL_GEN(dev_priv) >= 11) { 4739 i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config); 4740 4741 pipe_config->fec_enable = 4742 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE; 4743 4744 drm_dbg_kms(&dev_priv->drm, 4745 "[ENCODER:%d:%s] Fec status: %u\n", 4746 encoder->base.base.id, encoder->base.name, 4747 pipe_config->fec_enable); 4748 } 4749 4750 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) 4751 pipe_config->infoframes.enable |= 4752 intel_lspcon_infoframes_enabled(encoder, pipe_config); 4753 else 4754 pipe_config->infoframes.enable |= 4755 intel_hdmi_infoframes_enabled(encoder, pipe_config); 4756 break; 4757 case TRANS_DDI_MODE_SELECT_DP_MST: 4758 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 4759 pipe_config->lane_count = 4760 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4761 4762 if (INTEL_GEN(dev_priv) >= 12) 4763 pipe_config->mst_master_transcoder = 4764 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); 4765 4766 intel_dp_get_m_n(intel_crtc, pipe_config); 4767 4768 pipe_config->infoframes.enable |= 4769 intel_hdmi_infoframes_enabled(encoder, pipe_config); 4770 break; 4771 default: 4772 break; 4773 } 4774 } 4775 4776 void intel_ddi_get_config(struct intel_encoder *encoder, 4777 struct intel_crtc_state *pipe_config) 4778 { 4779 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4780 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4781 4782 /* XXX: DSI transcoder paranoia */ 4783 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 4784 return; 4785 4786 if (pipe_config->bigjoiner_slave) { 4787 /* read out pipe settings from master */ 4788 enum transcoder save = pipe_config->cpu_transcoder; 4789 4790 /* Our own transcoder needs to be disabled when reading it in intel_ddi_read_func_ctl() */ 4791 WARN_ON(pipe_config->output_types); 4792 pipe_config->cpu_transcoder = (enum transcoder)pipe_config->bigjoiner_linked_crtc->pipe; 4793 intel_ddi_read_func_ctl(encoder, pipe_config); 4794 pipe_config->cpu_transcoder = save; 4795 } else { 4796 intel_ddi_read_func_ctl(encoder, pipe_config); 4797 } 4798 4799 pipe_config->has_audio = 4800 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 4801 4802 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp && 4803 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { 4804 /* 4805 * This is a big fat ugly hack. 4806 * 4807 * Some machines in UEFI boot mode provide us a VBT that has 18 4808 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 4809 * unknown we fail to light up. Yet the same BIOS boots up with 4810 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 4811 * max, not what it tells us to use. 4812 * 4813 * Note: This will still be broken if the eDP panel is not lit 4814 * up by the BIOS, and thus we can't get the mode at module 4815 * load. 4816 */ 4817 drm_dbg_kms(&dev_priv->drm, 4818 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 4819 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); 4820 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; 4821 } 4822 4823 if (!pipe_config->bigjoiner_slave) 4824 intel_ddi_clock_get(encoder, pipe_config); 4825 4826 if (IS_GEN9_LP(dev_priv)) 4827 pipe_config->lane_lat_optim_mask = 4828 bxt_ddi_phy_get_lane_lat_optim_mask(encoder); 4829 4830 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 4831 4832 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 4833 4834 intel_read_infoframe(encoder, pipe_config, 4835 HDMI_INFOFRAME_TYPE_AVI, 4836 &pipe_config->infoframes.avi); 4837 intel_read_infoframe(encoder, pipe_config, 4838 HDMI_INFOFRAME_TYPE_SPD, 4839 &pipe_config->infoframes.spd); 4840 intel_read_infoframe(encoder, pipe_config, 4841 HDMI_INFOFRAME_TYPE_VENDOR, 4842 &pipe_config->infoframes.hdmi); 4843 intel_read_infoframe(encoder, pipe_config, 4844 HDMI_INFOFRAME_TYPE_DRM, 4845 &pipe_config->infoframes.drm); 4846 4847 if (INTEL_GEN(dev_priv) >= 8) 4848 bdw_get_trans_port_sync_config(pipe_config); 4849 4850 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 4851 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 4852 } 4853 4854 static void intel_ddi_sync_state(struct intel_encoder *encoder, 4855 const struct intel_crtc_state *crtc_state) 4856 { 4857 if (intel_crtc_has_dp_encoder(crtc_state)) 4858 intel_dp_sync_state(encoder, crtc_state); 4859 } 4860 4861 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 4862 struct intel_crtc_state *crtc_state) 4863 { 4864 if (intel_crtc_has_dp_encoder(crtc_state)) 4865 return intel_dp_initial_fastset_check(encoder, crtc_state); 4866 4867 return true; 4868 } 4869 4870 static enum intel_output_type 4871 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4872 struct intel_crtc_state *crtc_state, 4873 struct drm_connector_state *conn_state) 4874 { 4875 switch (conn_state->connector->connector_type) { 4876 case DRM_MODE_CONNECTOR_HDMIA: 4877 return INTEL_OUTPUT_HDMI; 4878 case DRM_MODE_CONNECTOR_eDP: 4879 return INTEL_OUTPUT_EDP; 4880 case DRM_MODE_CONNECTOR_DisplayPort: 4881 return INTEL_OUTPUT_DP; 4882 default: 4883 MISSING_CASE(conn_state->connector->connector_type); 4884 return INTEL_OUTPUT_UNUSED; 4885 } 4886 } 4887 4888 static int intel_ddi_compute_config(struct intel_encoder *encoder, 4889 struct intel_crtc_state *pipe_config, 4890 struct drm_connector_state *conn_state) 4891 { 4892 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4893 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4894 enum port port = encoder->port; 4895 int ret; 4896 4897 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 4898 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4899 4900 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4901 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4902 } else { 4903 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 4904 } 4905 4906 if (ret) 4907 return ret; 4908 4909 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 4910 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4911 pipe_config->pch_pfit.force_thru = 4912 pipe_config->pch_pfit.enabled || 4913 pipe_config->crc_enabled; 4914 4915 if (IS_GEN9_LP(dev_priv)) 4916 pipe_config->lane_lat_optim_mask = 4917 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4918 4919 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 4920 4921 return 0; 4922 } 4923 4924 static bool mode_equal(const struct drm_display_mode *mode1, 4925 const struct drm_display_mode *mode2) 4926 { 4927 return drm_mode_match(mode1, mode2, 4928 DRM_MODE_MATCH_TIMINGS | 4929 DRM_MODE_MATCH_FLAGS | 4930 DRM_MODE_MATCH_3D_FLAGS) && 4931 mode1->clock == mode2->clock; /* we want an exact match */ 4932 } 4933 4934 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 4935 const struct intel_link_m_n *m_n_2) 4936 { 4937 return m_n_1->tu == m_n_2->tu && 4938 m_n_1->gmch_m == m_n_2->gmch_m && 4939 m_n_1->gmch_n == m_n_2->gmch_n && 4940 m_n_1->link_m == m_n_2->link_m && 4941 m_n_1->link_n == m_n_2->link_n; 4942 } 4943 4944 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 4945 const struct intel_crtc_state *crtc_state2) 4946 { 4947 return crtc_state1->hw.active && crtc_state2->hw.active && 4948 crtc_state1->output_types == crtc_state2->output_types && 4949 crtc_state1->output_format == crtc_state2->output_format && 4950 crtc_state1->lane_count == crtc_state2->lane_count && 4951 crtc_state1->port_clock == crtc_state2->port_clock && 4952 mode_equal(&crtc_state1->hw.adjusted_mode, 4953 &crtc_state2->hw.adjusted_mode) && 4954 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 4955 } 4956 4957 static u8 4958 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4959 int tile_group_id) 4960 { 4961 struct drm_connector *connector; 4962 const struct drm_connector_state *conn_state; 4963 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 4964 struct intel_atomic_state *state = 4965 to_intel_atomic_state(ref_crtc_state->uapi.state); 4966 u8 transcoders = 0; 4967 int i; 4968 4969 /* 4970 * We don't enable port sync on BDW due to missing w/as and 4971 * due to not having adjusted the modeset sequence appropriately. 4972 */ 4973 if (INTEL_GEN(dev_priv) < 9) 4974 return 0; 4975 4976 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4977 return 0; 4978 4979 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4980 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4981 const struct intel_crtc_state *crtc_state; 4982 4983 if (!crtc) 4984 continue; 4985 4986 if (!connector->has_tile || 4987 connector->tile_group->id != 4988 tile_group_id) 4989 continue; 4990 crtc_state = intel_atomic_get_new_crtc_state(state, 4991 crtc); 4992 if (!crtcs_port_sync_compatible(ref_crtc_state, 4993 crtc_state)) 4994 continue; 4995 transcoders |= BIT(crtc_state->cpu_transcoder); 4996 } 4997 4998 return transcoders; 4999 } 5000 5001 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 5002 struct intel_crtc_state *crtc_state, 5003 struct drm_connector_state *conn_state) 5004 { 5005 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 5006 struct drm_connector *connector = conn_state->connector; 5007 u8 port_sync_transcoders = 0; 5008 5009 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]", 5010 encoder->base.base.id, encoder->base.name, 5011 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 5012 5013 if (connector->has_tile) 5014 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 5015 connector->tile_group->id); 5016 5017 /* 5018 * EDP Transcoders cannot be ensalved 5019 * make them a master always when present 5020 */ 5021 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 5022 crtc_state->master_transcoder = TRANSCODER_EDP; 5023 else 5024 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 5025 5026 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 5027 crtc_state->master_transcoder = INVALID_TRANSCODER; 5028 crtc_state->sync_mode_slaves_mask = 5029 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 5030 } 5031 5032 return 0; 5033 } 5034 5035 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 5036 { 5037 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 5038 5039 intel_dp_encoder_flush_work(encoder); 5040 5041 drm_encoder_cleanup(encoder); 5042 kfree(dig_port); 5043 } 5044 5045 static const struct drm_encoder_funcs intel_ddi_funcs = { 5046 .reset = intel_dp_encoder_reset, 5047 .destroy = intel_ddi_encoder_destroy, 5048 }; 5049 5050 static struct intel_connector * 5051 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 5052 { 5053 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 5054 struct intel_connector *connector; 5055 enum port port = dig_port->base.port; 5056 5057 connector = intel_connector_alloc(); 5058 if (!connector) 5059 return NULL; 5060 5061 dig_port->dp.output_reg = DDI_BUF_CTL(port); 5062 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 5063 dig_port->dp.set_link_train = intel_ddi_set_link_train; 5064 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 5065 5066 if (INTEL_GEN(dev_priv) >= 12) 5067 dig_port->dp.set_signal_levels = tgl_set_signal_levels; 5068 else if (INTEL_GEN(dev_priv) >= 11) 5069 dig_port->dp.set_signal_levels = icl_set_signal_levels; 5070 else if (IS_CANNONLAKE(dev_priv)) 5071 dig_port->dp.set_signal_levels = cnl_set_signal_levels; 5072 else if (IS_GEN9_LP(dev_priv)) 5073 dig_port->dp.set_signal_levels = bxt_set_signal_levels; 5074 else 5075 dig_port->dp.set_signal_levels = hsw_set_signal_levels; 5076 5077 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 5078 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 5079 5080 if (!intel_dp_init_connector(dig_port, connector)) { 5081 kfree(connector); 5082 return NULL; 5083 } 5084 5085 return connector; 5086 } 5087 5088 static int modeset_pipe(struct drm_crtc *crtc, 5089 struct drm_modeset_acquire_ctx *ctx) 5090 { 5091 struct drm_atomic_state *state; 5092 struct drm_crtc_state *crtc_state; 5093 int ret; 5094 5095 state = drm_atomic_state_alloc(crtc->dev); 5096 if (!state) 5097 return -ENOMEM; 5098 5099 state->acquire_ctx = ctx; 5100 5101 crtc_state = drm_atomic_get_crtc_state(state, crtc); 5102 if (IS_ERR(crtc_state)) { 5103 ret = PTR_ERR(crtc_state); 5104 goto out; 5105 } 5106 5107 crtc_state->connectors_changed = true; 5108 5109 ret = drm_atomic_commit(state); 5110 out: 5111 drm_atomic_state_put(state); 5112 5113 return ret; 5114 } 5115 5116 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 5117 struct drm_modeset_acquire_ctx *ctx) 5118 { 5119 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 5120 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 5121 struct intel_connector *connector = hdmi->attached_connector; 5122 struct i2c_adapter *adapter = 5123 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 5124 struct drm_connector_state *conn_state; 5125 struct intel_crtc_state *crtc_state; 5126 struct intel_crtc *crtc; 5127 u8 config; 5128 int ret; 5129 5130 if (!connector || connector->base.status != connector_status_connected) 5131 return 0; 5132 5133 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 5134 ctx); 5135 if (ret) 5136 return ret; 5137 5138 conn_state = connector->base.state; 5139 5140 crtc = to_intel_crtc(conn_state->crtc); 5141 if (!crtc) 5142 return 0; 5143 5144 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 5145 if (ret) 5146 return ret; 5147 5148 crtc_state = to_intel_crtc_state(crtc->base.state); 5149 5150 drm_WARN_ON(&dev_priv->drm, 5151 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 5152 5153 if (!crtc_state->hw.active) 5154 return 0; 5155 5156 if (!crtc_state->hdmi_high_tmds_clock_ratio && 5157 !crtc_state->hdmi_scrambling) 5158 return 0; 5159 5160 if (conn_state->commit && 5161 !try_wait_for_completion(&conn_state->commit->hw_done)) 5162 return 0; 5163 5164 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 5165 if (ret < 0) { 5166 drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n", 5167 ret); 5168 return 0; 5169 } 5170 5171 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 5172 crtc_state->hdmi_high_tmds_clock_ratio && 5173 !!(config & SCDC_SCRAMBLING_ENABLE) == 5174 crtc_state->hdmi_scrambling) 5175 return 0; 5176 5177 /* 5178 * HDMI 2.0 says that one should not send scrambled data 5179 * prior to configuring the sink scrambling, and that 5180 * TMDS clock/data transmission should be suspended when 5181 * changing the TMDS clock rate in the sink. So let's 5182 * just do a full modeset here, even though some sinks 5183 * would be perfectly happy if were to just reconfigure 5184 * the SCDC settings on the fly. 5185 */ 5186 return modeset_pipe(&crtc->base, ctx); 5187 } 5188 5189 static enum intel_hotplug_state 5190 intel_ddi_hotplug(struct intel_encoder *encoder, 5191 struct intel_connector *connector) 5192 { 5193 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 5194 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5195 enum phy phy = intel_port_to_phy(i915, encoder->port); 5196 bool is_tc = intel_phy_is_tc(i915, phy); 5197 struct drm_modeset_acquire_ctx ctx; 5198 enum intel_hotplug_state state; 5199 int ret; 5200 5201 state = intel_encoder_hotplug(encoder, connector); 5202 5203 drm_modeset_acquire_init(&ctx, 0); 5204 5205 for (;;) { 5206 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) 5207 ret = intel_hdmi_reset_link(encoder, &ctx); 5208 else 5209 ret = intel_dp_retrain_link(encoder, &ctx); 5210 5211 if (ret == -EDEADLK) { 5212 drm_modeset_backoff(&ctx); 5213 continue; 5214 } 5215 5216 break; 5217 } 5218 5219 drm_modeset_drop_locks(&ctx); 5220 drm_modeset_acquire_fini(&ctx); 5221 drm_WARN(encoder->base.dev, ret, 5222 "Acquiring modeset locks failed with %i\n", ret); 5223 5224 /* 5225 * Unpowered type-c dongles can take some time to boot and be 5226 * responsible, so here giving some time to those dongles to power up 5227 * and then retrying the probe. 5228 * 5229 * On many platforms the HDMI live state signal is known to be 5230 * unreliable, so we can't use it to detect if a sink is connected or 5231 * not. Instead we detect if it's connected based on whether we can 5232 * read the EDID or not. That in turn has a problem during disconnect, 5233 * since the HPD interrupt may be raised before the DDC lines get 5234 * disconnected (due to how the required length of DDC vs. HPD 5235 * connector pins are specified) and so we'll still be able to get a 5236 * valid EDID. To solve this schedule another detection cycle if this 5237 * time around we didn't detect any change in the sink's connection 5238 * status. 5239 * 5240 * Type-c connectors which get their HPD signal deasserted then 5241 * reasserted, without unplugging/replugging the sink from the 5242 * connector, introduce a delay until the AUX channel communication 5243 * becomes functional. Retry the detection for 5 seconds on type-c 5244 * connectors to account for this delay. 5245 */ 5246 if (state == INTEL_HOTPLUG_UNCHANGED && 5247 connector->hotplug_retries < (is_tc ? 5 : 1) && 5248 !dig_port->dp.is_mst) 5249 state = INTEL_HOTPLUG_RETRY; 5250 5251 return state; 5252 } 5253 5254 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 5255 { 5256 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 5257 u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin]; 5258 5259 return intel_de_read(dev_priv, SDEISR) & bit; 5260 } 5261 5262 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 5263 { 5264 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 5265 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; 5266 5267 return intel_de_read(dev_priv, DEISR) & bit; 5268 } 5269 5270 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 5271 { 5272 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 5273 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; 5274 5275 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; 5276 } 5277 5278 static struct intel_connector * 5279 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 5280 { 5281 struct intel_connector *connector; 5282 enum port port = dig_port->base.port; 5283 5284 connector = intel_connector_alloc(); 5285 if (!connector) 5286 return NULL; 5287 5288 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 5289 intel_hdmi_init_connector(dig_port, connector); 5290 5291 return connector; 5292 } 5293 5294 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 5295 { 5296 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 5297 5298 if (dig_port->base.port != PORT_A) 5299 return false; 5300 5301 if (dig_port->saved_port_bits & DDI_A_4_LANES) 5302 return false; 5303 5304 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 5305 * supported configuration 5306 */ 5307 if (IS_GEN9_LP(dev_priv)) 5308 return true; 5309 5310 /* Cannonlake: Most of SKUs don't support DDI_E, and the only 5311 * one who does also have a full A/E split called 5312 * DDI_F what makes DDI_E useless. However for this 5313 * case let's trust VBT info. 5314 */ 5315 if (IS_CANNONLAKE(dev_priv) && 5316 !intel_bios_is_port_present(dev_priv, PORT_E)) 5317 return true; 5318 5319 return false; 5320 } 5321 5322 static int 5323 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 5324 { 5325 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 5326 enum port port = dig_port->base.port; 5327 int max_lanes = 4; 5328 5329 if (INTEL_GEN(dev_priv) >= 11) 5330 return max_lanes; 5331 5332 if (port == PORT_A || port == PORT_E) { 5333 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 5334 max_lanes = port == PORT_A ? 4 : 0; 5335 else 5336 /* Both A and E share 2 lanes */ 5337 max_lanes = 2; 5338 } 5339 5340 /* 5341 * Some BIOS might fail to set this bit on port A if eDP 5342 * wasn't lit up at boot. Force this bit set when needed 5343 * so we use the proper lane count for our calculations. 5344 */ 5345 if (intel_ddi_a_force_4_lanes(dig_port)) { 5346 drm_dbg_kms(&dev_priv->drm, 5347 "Forcing DDI_A_4_LANES for port A\n"); 5348 dig_port->saved_port_bits |= DDI_A_4_LANES; 5349 max_lanes = 4; 5350 } 5351 5352 return max_lanes; 5353 } 5354 5355 static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy) 5356 { 5357 return i915->hti_state & HDPORT_ENABLED && 5358 i915->hti_state & HDPORT_DDI_USED(phy); 5359 } 5360 5361 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, 5362 enum port port) 5363 { 5364 if (port >= PORT_TC1) 5365 return HPD_PORT_C + port - PORT_TC1; 5366 else 5367 return HPD_PORT_A + port - PORT_A; 5368 } 5369 5370 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, 5371 enum port port) 5372 { 5373 if (port >= PORT_TC1) 5374 return HPD_PORT_TC1 + port - PORT_TC1; 5375 else 5376 return HPD_PORT_A + port - PORT_A; 5377 } 5378 5379 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, 5380 enum port port) 5381 { 5382 if (HAS_PCH_TGP(dev_priv)) 5383 return tgl_hpd_pin(dev_priv, port); 5384 5385 if (port >= PORT_TC1) 5386 return HPD_PORT_C + port - PORT_TC1; 5387 else 5388 return HPD_PORT_A + port - PORT_A; 5389 } 5390 5391 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, 5392 enum port port) 5393 { 5394 if (port >= PORT_C) 5395 return HPD_PORT_TC1 + port - PORT_C; 5396 else 5397 return HPD_PORT_A + port - PORT_A; 5398 } 5399 5400 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, 5401 enum port port) 5402 { 5403 if (port == PORT_D) 5404 return HPD_PORT_A; 5405 5406 if (HAS_PCH_MCC(dev_priv)) 5407 return icl_hpd_pin(dev_priv, port); 5408 5409 return HPD_PORT_A + port - PORT_A; 5410 } 5411 5412 static enum hpd_pin cnl_hpd_pin(struct drm_i915_private *dev_priv, 5413 enum port port) 5414 { 5415 if (port == PORT_F) 5416 return HPD_PORT_E; 5417 5418 return HPD_PORT_A + port - PORT_A; 5419 } 5420 5421 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 5422 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 5423 5424 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 5425 { 5426 struct intel_digital_port *dig_port; 5427 struct intel_encoder *encoder; 5428 bool init_hdmi, init_dp; 5429 enum phy phy = intel_port_to_phy(dev_priv, port); 5430 5431 /* 5432 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 5433 * have taken over some of the PHYs and made them unavailable to the 5434 * driver. In that case we should skip initializing the corresponding 5435 * outputs. 5436 */ 5437 if (hti_uses_phy(dev_priv, phy)) { 5438 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", 5439 port_name(port), phy_name(phy)); 5440 return; 5441 } 5442 5443 init_hdmi = intel_bios_port_supports_dvi(dev_priv, port) || 5444 intel_bios_port_supports_hdmi(dev_priv, port); 5445 init_dp = intel_bios_port_supports_dp(dev_priv, port); 5446 5447 if (intel_bios_is_lspcon_present(dev_priv, port)) { 5448 /* 5449 * Lspcon device needs to be driven with DP connector 5450 * with special detection sequence. So make sure DP 5451 * is initialized before lspcon. 5452 */ 5453 init_dp = true; 5454 init_hdmi = false; 5455 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", 5456 port_name(port)); 5457 } 5458 5459 if (!init_dp && !init_hdmi) { 5460 drm_dbg_kms(&dev_priv->drm, 5461 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 5462 port_name(port)); 5463 return; 5464 } 5465 5466 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 5467 if (!dig_port) 5468 return; 5469 5470 encoder = &dig_port->base; 5471 5472 if (INTEL_GEN(dev_priv) >= 12) { 5473 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 5474 5475 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 5476 DRM_MODE_ENCODER_TMDS, 5477 "DDI %s%c/PHY %s%c", 5478 port >= PORT_TC1 ? "TC" : "", 5479 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 5480 tc_port != TC_PORT_NONE ? "TC" : "", 5481 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5482 } else if (INTEL_GEN(dev_priv) >= 11) { 5483 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 5484 5485 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 5486 DRM_MODE_ENCODER_TMDS, 5487 "DDI %c%s/PHY %s%c", 5488 port_name(port), 5489 port >= PORT_C ? " (TC)" : "", 5490 tc_port != TC_PORT_NONE ? "TC" : "", 5491 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5492 } else { 5493 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 5494 DRM_MODE_ENCODER_TMDS, 5495 "DDI %c/PHY %c", port_name(port), phy_name(phy)); 5496 } 5497 5498 mutex_init(&dig_port->hdcp_mutex); 5499 dig_port->num_hdcp_streams = 0; 5500 5501 encoder->hotplug = intel_ddi_hotplug; 5502 encoder->compute_output_type = intel_ddi_compute_output_type; 5503 encoder->compute_config = intel_ddi_compute_config; 5504 encoder->compute_config_late = intel_ddi_compute_config_late; 5505 encoder->enable = intel_enable_ddi; 5506 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 5507 encoder->pre_enable = intel_ddi_pre_enable; 5508 encoder->disable = intel_disable_ddi; 5509 encoder->post_disable = intel_ddi_post_disable; 5510 encoder->update_pipe = intel_ddi_update_pipe; 5511 encoder->get_hw_state = intel_ddi_get_hw_state; 5512 encoder->get_config = intel_ddi_get_config; 5513 encoder->sync_state = intel_ddi_sync_state; 5514 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 5515 encoder->suspend = intel_dp_encoder_suspend; 5516 encoder->shutdown = intel_dp_encoder_shutdown; 5517 encoder->get_power_domains = intel_ddi_get_power_domains; 5518 5519 encoder->type = INTEL_OUTPUT_DDI; 5520 encoder->power_domain = intel_port_to_power_domain(port); 5521 encoder->port = port; 5522 encoder->cloneable = 0; 5523 encoder->pipe_mask = ~0; 5524 5525 if (IS_DG1(dev_priv)) 5526 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); 5527 else if (IS_ROCKETLAKE(dev_priv)) 5528 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); 5529 else if (INTEL_GEN(dev_priv) >= 12) 5530 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); 5531 else if (IS_JSL_EHL(dev_priv)) 5532 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); 5533 else if (IS_GEN(dev_priv, 11)) 5534 encoder->hpd_pin = icl_hpd_pin(dev_priv, port); 5535 else if (IS_GEN(dev_priv, 10)) 5536 encoder->hpd_pin = cnl_hpd_pin(dev_priv, port); 5537 else 5538 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 5539 5540 if (INTEL_GEN(dev_priv) >= 11) 5541 dig_port->saved_port_bits = 5542 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 5543 & DDI_BUF_PORT_REVERSAL; 5544 else 5545 dig_port->saved_port_bits = 5546 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 5547 & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 5548 5549 dig_port->dp.output_reg = INVALID_MMIO_REG; 5550 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 5551 dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 5552 5553 if (intel_phy_is_tc(dev_priv, phy)) { 5554 bool is_legacy = 5555 !intel_bios_port_supports_typec_usb(dev_priv, port) && 5556 !intel_bios_port_supports_tbt(dev_priv, port); 5557 5558 intel_tc_port_init(dig_port, is_legacy); 5559 5560 encoder->update_prepare = intel_ddi_update_prepare; 5561 encoder->update_complete = intel_ddi_update_complete; 5562 } 5563 5564 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 5565 dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO + 5566 port - PORT_A; 5567 5568 if (init_dp) { 5569 if (!intel_ddi_init_dp_connector(dig_port)) 5570 goto err; 5571 5572 dig_port->hpd_pulse = intel_dp_hpd_pulse; 5573 } 5574 5575 /* In theory we don't need the encoder->type check, but leave it just in 5576 * case we have some really bad VBTs... */ 5577 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 5578 if (!intel_ddi_init_hdmi_connector(dig_port)) 5579 goto err; 5580 } 5581 5582 if (INTEL_GEN(dev_priv) >= 11) { 5583 if (intel_phy_is_tc(dev_priv, phy)) 5584 dig_port->connected = intel_tc_port_connected; 5585 else 5586 dig_port->connected = lpt_digital_port_connected; 5587 } else if (INTEL_GEN(dev_priv) >= 8) { 5588 if (port == PORT_A || IS_GEN9_LP(dev_priv)) 5589 dig_port->connected = bdw_digital_port_connected; 5590 else 5591 dig_port->connected = lpt_digital_port_connected; 5592 } else { 5593 if (port == PORT_A) 5594 dig_port->connected = hsw_digital_port_connected; 5595 else 5596 dig_port->connected = lpt_digital_port_connected; 5597 } 5598 5599 intel_infoframe_init(dig_port); 5600 5601 return; 5602 5603 err: 5604 drm_encoder_cleanup(&encoder->base); 5605 kfree(dig_port); 5606 } 5607