1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <drm/drm_privacy_screen_consumer.h> 29 #include <drm/drm_scdc_helper.h> 30 31 #include "i915_drv.h" 32 #include "intel_audio.h" 33 #include "intel_backlight.h" 34 #include "intel_combo_phy.h" 35 #include "intel_connector.h" 36 #include "intel_crtc.h" 37 #include "intel_ddi.h" 38 #include "intel_ddi_buf_trans.h" 39 #include "intel_de.h" 40 #include "intel_display_types.h" 41 #include "intel_dp.h" 42 #include "intel_dp_link_training.h" 43 #include "intel_dp_mst.h" 44 #include "intel_dpio_phy.h" 45 #include "intel_drrs.h" 46 #include "intel_dsi.h" 47 #include "intel_fdi.h" 48 #include "intel_fifo_underrun.h" 49 #include "intel_gmbus.h" 50 #include "intel_hdcp.h" 51 #include "intel_hdmi.h" 52 #include "intel_hotplug.h" 53 #include "intel_lspcon.h" 54 #include "intel_pps.h" 55 #include "intel_psr.h" 56 #include "intel_snps_phy.h" 57 #include "intel_sprite.h" 58 #include "intel_tc.h" 59 #include "intel_vdsc.h" 60 #include "intel_vrr.h" 61 #include "skl_scaler.h" 62 #include "skl_universal_plane.h" 63 64 static const u8 index_to_dp_signal_levels[] = { 65 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 66 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 67 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 68 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 69 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 70 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 71 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 72 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 73 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 74 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 75 }; 76 77 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 78 const struct intel_ddi_buf_trans *trans) 79 { 80 int level; 81 82 level = intel_bios_hdmi_level_shift(encoder); 83 if (level < 0) 84 level = trans->hdmi_default_entry; 85 86 return level; 87 } 88 89 static bool has_buf_trans_select(struct drm_i915_private *i915) 90 { 91 return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915); 92 } 93 94 static bool has_iboost(struct drm_i915_private *i915) 95 { 96 return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915); 97 } 98 99 /* 100 * Starting with Haswell, DDI port buffers must be programmed with correct 101 * values in advance. This function programs the correct values for 102 * DP/eDP/FDI use cases. 103 */ 104 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 105 const struct intel_crtc_state *crtc_state) 106 { 107 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 108 u32 iboost_bit = 0; 109 int i, n_entries; 110 enum port port = encoder->port; 111 const struct intel_ddi_buf_trans *trans; 112 113 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 114 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 115 return; 116 117 /* If we're boosting the current, set bit 31 of trans1 */ 118 if (has_iboost(dev_priv) && 119 intel_bios_encoder_dp_boost_level(encoder->devdata)) 120 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 121 122 for (i = 0; i < n_entries; i++) { 123 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 124 trans->entries[i].hsw.trans1 | iboost_bit); 125 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 126 trans->entries[i].hsw.trans2); 127 } 128 } 129 130 /* 131 * Starting with Haswell, DDI port buffers must be programmed with correct 132 * values in advance. This function programs the correct values for 133 * HDMI/DVI use cases. 134 */ 135 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 136 const struct intel_crtc_state *crtc_state) 137 { 138 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 139 int level = intel_ddi_level(encoder, crtc_state, 0); 140 u32 iboost_bit = 0; 141 int n_entries; 142 enum port port = encoder->port; 143 const struct intel_ddi_buf_trans *trans; 144 145 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 146 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 147 return; 148 149 /* If we're boosting the current, set bit 31 of trans1 */ 150 if (has_iboost(dev_priv) && 151 intel_bios_encoder_hdmi_boost_level(encoder->devdata)) 152 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 153 154 /* Entry 9 is for HDMI: */ 155 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 156 trans->entries[level].hsw.trans1 | iboost_bit); 157 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 158 trans->entries[level].hsw.trans2); 159 } 160 161 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 162 enum port port) 163 { 164 if (IS_BROXTON(dev_priv)) { 165 udelay(16); 166 return; 167 } 168 169 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 170 DDI_BUF_IS_IDLE), 8)) 171 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", 172 port_name(port)); 173 } 174 175 static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, 176 enum port port) 177 { 178 int ret; 179 180 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ 181 if (DISPLAY_VER(dev_priv) < 10) { 182 usleep_range(518, 1000); 183 return; 184 } 185 186 ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 187 DDI_BUF_IS_IDLE), IS_DG2(dev_priv) ? 1200 : 500, 10, 10); 188 189 if (ret) 190 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", 191 port_name(port)); 192 } 193 194 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 195 { 196 switch (pll->info->id) { 197 case DPLL_ID_WRPLL1: 198 return PORT_CLK_SEL_WRPLL1; 199 case DPLL_ID_WRPLL2: 200 return PORT_CLK_SEL_WRPLL2; 201 case DPLL_ID_SPLL: 202 return PORT_CLK_SEL_SPLL; 203 case DPLL_ID_LCPLL_810: 204 return PORT_CLK_SEL_LCPLL_810; 205 case DPLL_ID_LCPLL_1350: 206 return PORT_CLK_SEL_LCPLL_1350; 207 case DPLL_ID_LCPLL_2700: 208 return PORT_CLK_SEL_LCPLL_2700; 209 default: 210 MISSING_CASE(pll->info->id); 211 return PORT_CLK_SEL_NONE; 212 } 213 } 214 215 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 216 const struct intel_crtc_state *crtc_state) 217 { 218 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 219 int clock = crtc_state->port_clock; 220 const enum intel_dpll_id id = pll->info->id; 221 222 switch (id) { 223 default: 224 /* 225 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 226 * here, so do warn if this get passed in 227 */ 228 MISSING_CASE(id); 229 return DDI_CLK_SEL_NONE; 230 case DPLL_ID_ICL_TBTPLL: 231 switch (clock) { 232 case 162000: 233 return DDI_CLK_SEL_TBT_162; 234 case 270000: 235 return DDI_CLK_SEL_TBT_270; 236 case 540000: 237 return DDI_CLK_SEL_TBT_540; 238 case 810000: 239 return DDI_CLK_SEL_TBT_810; 240 default: 241 MISSING_CASE(clock); 242 return DDI_CLK_SEL_NONE; 243 } 244 case DPLL_ID_ICL_MGPLL1: 245 case DPLL_ID_ICL_MGPLL2: 246 case DPLL_ID_ICL_MGPLL3: 247 case DPLL_ID_ICL_MGPLL4: 248 case DPLL_ID_TGL_MGPLL5: 249 case DPLL_ID_TGL_MGPLL6: 250 return DDI_CLK_SEL_MG; 251 } 252 } 253 254 static u32 ddi_buf_phy_link_rate(int port_clock) 255 { 256 switch (port_clock) { 257 case 162000: 258 return DDI_BUF_PHY_LINK_RATE(0); 259 case 216000: 260 return DDI_BUF_PHY_LINK_RATE(4); 261 case 243000: 262 return DDI_BUF_PHY_LINK_RATE(5); 263 case 270000: 264 return DDI_BUF_PHY_LINK_RATE(1); 265 case 324000: 266 return DDI_BUF_PHY_LINK_RATE(6); 267 case 432000: 268 return DDI_BUF_PHY_LINK_RATE(7); 269 case 540000: 270 return DDI_BUF_PHY_LINK_RATE(2); 271 case 810000: 272 return DDI_BUF_PHY_LINK_RATE(3); 273 default: 274 MISSING_CASE(port_clock); 275 return DDI_BUF_PHY_LINK_RATE(0); 276 } 277 } 278 279 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 280 const struct intel_crtc_state *crtc_state) 281 { 282 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 283 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 284 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 285 enum phy phy = intel_port_to_phy(i915, encoder->port); 286 287 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 288 intel_dp->DP = dig_port->saved_port_bits | 289 DDI_PORT_WIDTH(crtc_state->lane_count) | 290 DDI_BUF_TRANS_SELECT(0); 291 292 if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) { 293 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 294 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 295 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 296 } 297 } 298 299 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 300 enum port port) 301 { 302 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 303 304 switch (val) { 305 case DDI_CLK_SEL_NONE: 306 return 0; 307 case DDI_CLK_SEL_TBT_162: 308 return 162000; 309 case DDI_CLK_SEL_TBT_270: 310 return 270000; 311 case DDI_CLK_SEL_TBT_540: 312 return 540000; 313 case DDI_CLK_SEL_TBT_810: 314 return 810000; 315 default: 316 MISSING_CASE(val); 317 return 0; 318 } 319 } 320 321 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 322 { 323 int dotclock; 324 325 /* CRT dotclock is determined via other means */ 326 if (pipe_config->has_pch_encoder) 327 return; 328 329 if (intel_crtc_has_dp_encoder(pipe_config)) 330 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 331 &pipe_config->dp_m_n); 332 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) 333 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp; 334 else 335 dotclock = pipe_config->port_clock; 336 337 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 338 !intel_crtc_has_dp_encoder(pipe_config)) 339 dotclock *= 2; 340 341 if (pipe_config->pixel_multiplier) 342 dotclock /= pipe_config->pixel_multiplier; 343 344 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 345 } 346 347 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 348 const struct drm_connector_state *conn_state) 349 { 350 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 351 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 352 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 353 u32 temp; 354 355 if (!intel_crtc_has_dp_encoder(crtc_state)) 356 return; 357 358 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 359 360 temp = DP_MSA_MISC_SYNC_CLOCK; 361 362 switch (crtc_state->pipe_bpp) { 363 case 18: 364 temp |= DP_MSA_MISC_6_BPC; 365 break; 366 case 24: 367 temp |= DP_MSA_MISC_8_BPC; 368 break; 369 case 30: 370 temp |= DP_MSA_MISC_10_BPC; 371 break; 372 case 36: 373 temp |= DP_MSA_MISC_12_BPC; 374 break; 375 default: 376 MISSING_CASE(crtc_state->pipe_bpp); 377 break; 378 } 379 380 /* nonsense combination */ 381 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 382 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 383 384 if (crtc_state->limited_color_range) 385 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 386 387 /* 388 * As per DP 1.2 spec section 2.3.4.3 while sending 389 * YCBCR 444 signals we should program MSA MISC1/0 fields with 390 * colorspace information. 391 */ 392 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 393 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 394 395 /* 396 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 397 * of Color Encoding Format and Content Color Gamut] while sending 398 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 399 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 400 */ 401 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 402 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 403 404 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp); 405 } 406 407 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 408 { 409 if (master_transcoder == TRANSCODER_EDP) 410 return 0; 411 else 412 return master_transcoder + 1; 413 } 414 415 static void 416 intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder, 417 const struct intel_crtc_state *crtc_state) 418 { 419 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 420 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 421 u32 val = 0; 422 423 if (intel_dp_is_uhbr(crtc_state)) 424 val = TRANS_DP2_128B132B_CHANNEL_CODING; 425 426 intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val); 427 } 428 429 /* 430 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 431 * 432 * Only intended to be used by intel_ddi_enable_transcoder_func() and 433 * intel_ddi_config_transcoder_func(). 434 */ 435 static u32 436 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 437 const struct intel_crtc_state *crtc_state) 438 { 439 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 440 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 441 enum pipe pipe = crtc->pipe; 442 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 443 enum port port = encoder->port; 444 u32 temp; 445 446 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 447 temp = TRANS_DDI_FUNC_ENABLE; 448 if (DISPLAY_VER(dev_priv) >= 12) 449 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 450 else 451 temp |= TRANS_DDI_SELECT_PORT(port); 452 453 switch (crtc_state->pipe_bpp) { 454 case 18: 455 temp |= TRANS_DDI_BPC_6; 456 break; 457 case 24: 458 temp |= TRANS_DDI_BPC_8; 459 break; 460 case 30: 461 temp |= TRANS_DDI_BPC_10; 462 break; 463 case 36: 464 temp |= TRANS_DDI_BPC_12; 465 break; 466 default: 467 BUG(); 468 } 469 470 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 471 temp |= TRANS_DDI_PVSYNC; 472 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 473 temp |= TRANS_DDI_PHSYNC; 474 475 if (cpu_transcoder == TRANSCODER_EDP) { 476 switch (pipe) { 477 case PIPE_A: 478 /* On Haswell, can only use the always-on power well for 479 * eDP when not using the panel fitter, and when not 480 * using motion blur mitigation (which we don't 481 * support). */ 482 if (crtc_state->pch_pfit.force_thru) 483 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 484 else 485 temp |= TRANS_DDI_EDP_INPUT_A_ON; 486 break; 487 case PIPE_B: 488 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 489 break; 490 case PIPE_C: 491 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 492 break; 493 default: 494 BUG(); 495 break; 496 } 497 } 498 499 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 500 if (crtc_state->has_hdmi_sink) 501 temp |= TRANS_DDI_MODE_SELECT_HDMI; 502 else 503 temp |= TRANS_DDI_MODE_SELECT_DVI; 504 505 if (crtc_state->hdmi_scrambling) 506 temp |= TRANS_DDI_HDMI_SCRAMBLING; 507 if (crtc_state->hdmi_high_tmds_clock_ratio) 508 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 509 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 510 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 511 temp |= (crtc_state->fdi_lanes - 1) << 1; 512 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 513 if (intel_dp_is_uhbr(crtc_state)) 514 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 515 else 516 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 517 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 518 519 if (DISPLAY_VER(dev_priv) >= 12) { 520 enum transcoder master; 521 522 master = crtc_state->mst_master_transcoder; 523 drm_WARN_ON(&dev_priv->drm, 524 master == INVALID_TRANSCODER); 525 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 526 } 527 } else { 528 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 529 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 530 } 531 532 if (IS_DISPLAY_VER(dev_priv, 8, 10) && 533 crtc_state->master_transcoder != INVALID_TRANSCODER) { 534 u8 master_select = 535 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 536 537 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 538 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 539 } 540 541 return temp; 542 } 543 544 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 545 const struct intel_crtc_state *crtc_state) 546 { 547 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 548 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 549 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 550 551 if (DISPLAY_VER(dev_priv) >= 11) { 552 enum transcoder master_transcoder = crtc_state->master_transcoder; 553 u32 ctl2 = 0; 554 555 if (master_transcoder != INVALID_TRANSCODER) { 556 u8 master_select = 557 bdw_trans_port_sync_master_select(master_transcoder); 558 559 ctl2 |= PORT_SYNC_MODE_ENABLE | 560 PORT_SYNC_MODE_MASTER_SELECT(master_select); 561 } 562 563 intel_de_write(dev_priv, 564 TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2); 565 } 566 567 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 568 intel_ddi_transcoder_func_reg_val_get(encoder, 569 crtc_state)); 570 } 571 572 /* 573 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 574 * bit. 575 */ 576 static void 577 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 578 const struct intel_crtc_state *crtc_state) 579 { 580 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 581 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 582 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 583 u32 ctl; 584 585 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 586 ctl &= ~TRANS_DDI_FUNC_ENABLE; 587 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 588 } 589 590 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 591 { 592 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 593 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 594 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 595 u32 ctl; 596 597 if (DISPLAY_VER(dev_priv) >= 11) 598 intel_de_write(dev_priv, 599 TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0); 600 601 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 602 603 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 604 605 ctl &= ~TRANS_DDI_FUNC_ENABLE; 606 607 if (IS_DISPLAY_VER(dev_priv, 8, 10)) 608 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 609 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 610 611 if (DISPLAY_VER(dev_priv) >= 12) { 612 if (!intel_dp_mst_is_master_trans(crtc_state)) { 613 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 614 TRANS_DDI_MODE_SELECT_MASK); 615 } 616 } else { 617 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 618 } 619 620 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 621 622 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME && 623 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 624 drm_dbg_kms(&dev_priv->drm, 625 "Quirk Increase DDI disabled time\n"); 626 /* Quirk time at 100ms for reliable operation */ 627 msleep(100); 628 } 629 } 630 631 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 632 enum transcoder cpu_transcoder, 633 bool enable, u32 hdcp_mask) 634 { 635 struct drm_device *dev = intel_encoder->base.dev; 636 struct drm_i915_private *dev_priv = to_i915(dev); 637 intel_wakeref_t wakeref; 638 int ret = 0; 639 u32 tmp; 640 641 wakeref = intel_display_power_get_if_enabled(dev_priv, 642 intel_encoder->power_domain); 643 if (drm_WARN_ON(dev, !wakeref)) 644 return -ENXIO; 645 646 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 647 if (enable) 648 tmp |= hdcp_mask; 649 else 650 tmp &= ~hdcp_mask; 651 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp); 652 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 653 return ret; 654 } 655 656 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 657 { 658 struct drm_device *dev = intel_connector->base.dev; 659 struct drm_i915_private *dev_priv = to_i915(dev); 660 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 661 int type = intel_connector->base.connector_type; 662 enum port port = encoder->port; 663 enum transcoder cpu_transcoder; 664 intel_wakeref_t wakeref; 665 enum pipe pipe = 0; 666 u32 tmp; 667 bool ret; 668 669 wakeref = intel_display_power_get_if_enabled(dev_priv, 670 encoder->power_domain); 671 if (!wakeref) 672 return false; 673 674 if (!encoder->get_hw_state(encoder, &pipe)) { 675 ret = false; 676 goto out; 677 } 678 679 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 680 cpu_transcoder = TRANSCODER_EDP; 681 else 682 cpu_transcoder = (enum transcoder) pipe; 683 684 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 685 686 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 687 case TRANS_DDI_MODE_SELECT_HDMI: 688 case TRANS_DDI_MODE_SELECT_DVI: 689 ret = type == DRM_MODE_CONNECTOR_HDMIA; 690 break; 691 692 case TRANS_DDI_MODE_SELECT_DP_SST: 693 ret = type == DRM_MODE_CONNECTOR_eDP || 694 type == DRM_MODE_CONNECTOR_DisplayPort; 695 break; 696 697 case TRANS_DDI_MODE_SELECT_DP_MST: 698 /* if the transcoder is in MST state then 699 * connector isn't connected */ 700 ret = false; 701 break; 702 703 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 704 if (HAS_DP20(dev_priv)) 705 /* 128b/132b */ 706 ret = false; 707 else 708 /* FDI */ 709 ret = type == DRM_MODE_CONNECTOR_VGA; 710 break; 711 712 default: 713 ret = false; 714 break; 715 } 716 717 out: 718 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 719 720 return ret; 721 } 722 723 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 724 u8 *pipe_mask, bool *is_dp_mst) 725 { 726 struct drm_device *dev = encoder->base.dev; 727 struct drm_i915_private *dev_priv = to_i915(dev); 728 enum port port = encoder->port; 729 intel_wakeref_t wakeref; 730 enum pipe p; 731 u32 tmp; 732 u8 mst_pipe_mask; 733 734 *pipe_mask = 0; 735 *is_dp_mst = false; 736 737 wakeref = intel_display_power_get_if_enabled(dev_priv, 738 encoder->power_domain); 739 if (!wakeref) 740 return; 741 742 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 743 if (!(tmp & DDI_BUF_CTL_ENABLE)) 744 goto out; 745 746 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { 747 tmp = intel_de_read(dev_priv, 748 TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 749 750 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 751 default: 752 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 753 fallthrough; 754 case TRANS_DDI_EDP_INPUT_A_ON: 755 case TRANS_DDI_EDP_INPUT_A_ONOFF: 756 *pipe_mask = BIT(PIPE_A); 757 break; 758 case TRANS_DDI_EDP_INPUT_B_ONOFF: 759 *pipe_mask = BIT(PIPE_B); 760 break; 761 case TRANS_DDI_EDP_INPUT_C_ONOFF: 762 *pipe_mask = BIT(PIPE_C); 763 break; 764 } 765 766 goto out; 767 } 768 769 mst_pipe_mask = 0; 770 for_each_pipe(dev_priv, p) { 771 enum transcoder cpu_transcoder = (enum transcoder)p; 772 unsigned int port_mask, ddi_select; 773 intel_wakeref_t trans_wakeref; 774 775 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 776 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 777 if (!trans_wakeref) 778 continue; 779 780 if (DISPLAY_VER(dev_priv) >= 12) { 781 port_mask = TGL_TRANS_DDI_PORT_MASK; 782 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 783 } else { 784 port_mask = TRANS_DDI_PORT_MASK; 785 ddi_select = TRANS_DDI_SELECT_PORT(port); 786 } 787 788 tmp = intel_de_read(dev_priv, 789 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 790 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 791 trans_wakeref); 792 793 if ((tmp & port_mask) != ddi_select) 794 continue; 795 796 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST || 797 (HAS_DP20(dev_priv) && 798 (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B)) 799 mst_pipe_mask |= BIT(p); 800 801 *pipe_mask |= BIT(p); 802 } 803 804 if (!*pipe_mask) 805 drm_dbg_kms(&dev_priv->drm, 806 "No pipe for [ENCODER:%d:%s] found\n", 807 encoder->base.base.id, encoder->base.name); 808 809 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 810 drm_dbg_kms(&dev_priv->drm, 811 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 812 encoder->base.base.id, encoder->base.name, 813 *pipe_mask); 814 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 815 } 816 817 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 818 drm_dbg_kms(&dev_priv->drm, 819 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", 820 encoder->base.base.id, encoder->base.name, 821 *pipe_mask, mst_pipe_mask); 822 else 823 *is_dp_mst = mst_pipe_mask; 824 825 out: 826 if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) { 827 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 828 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 829 BXT_PHY_LANE_POWERDOWN_ACK | 830 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 831 drm_err(&dev_priv->drm, 832 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 833 encoder->base.base.id, encoder->base.name, tmp); 834 } 835 836 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 837 } 838 839 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 840 enum pipe *pipe) 841 { 842 u8 pipe_mask; 843 bool is_mst; 844 845 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 846 847 if (is_mst || !pipe_mask) 848 return false; 849 850 *pipe = ffs(pipe_mask) - 1; 851 852 return true; 853 } 854 855 static enum intel_display_power_domain 856 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port) 857 { 858 /* ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 859 * DC states enabled at the same time, while for driver initiated AUX 860 * transfers we need the same AUX IOs to be powered but with DC states 861 * disabled. Accordingly use the AUX power domain here which leaves DC 862 * states enabled. 863 * However, for non-A AUX ports the corresponding non-EDP transcoders 864 * would have already enabled power well 2 and DC_OFF. This means we can 865 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a 866 * specific AUX_IO reference without powering up any extra wells. 867 * Note that PSR is enabled only on Port A even though this function 868 * returns the correct domain for other ports too. 869 */ 870 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A : 871 intel_aux_power_domain(dig_port); 872 } 873 874 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 875 struct intel_crtc_state *crtc_state) 876 { 877 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 878 struct intel_digital_port *dig_port; 879 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 880 881 /* 882 * TODO: Add support for MST encoders. Atm, the following should never 883 * happen since fake-MST encoders don't set their get_power_domains() 884 * hook. 885 */ 886 if (drm_WARN_ON(&dev_priv->drm, 887 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 888 return; 889 890 dig_port = enc_to_dig_port(encoder); 891 892 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 893 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 894 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 895 dig_port->ddi_io_power_domain); 896 } 897 898 /* 899 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC 900 * ports. 901 */ 902 if (intel_crtc_has_dp_encoder(crtc_state) || 903 intel_phy_is_tc(dev_priv, phy)) { 904 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref); 905 dig_port->aux_wakeref = 906 intel_display_power_get(dev_priv, 907 intel_ddi_main_link_aux_domain(dig_port)); 908 } 909 } 910 911 void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder, 912 const struct intel_crtc_state *crtc_state) 913 { 914 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 915 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 916 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 917 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 918 u32 val; 919 920 if (cpu_transcoder != TRANSCODER_EDP) { 921 if (DISPLAY_VER(dev_priv) >= 13) 922 val = TGL_TRANS_CLK_SEL_PORT(phy); 923 else if (DISPLAY_VER(dev_priv) >= 12) 924 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 925 else 926 val = TRANS_CLK_SEL_PORT(encoder->port); 927 928 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 929 } 930 } 931 932 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state) 933 { 934 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 935 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 936 937 if (cpu_transcoder != TRANSCODER_EDP) { 938 if (DISPLAY_VER(dev_priv) >= 12) 939 intel_de_write(dev_priv, 940 TRANS_CLK_SEL(cpu_transcoder), 941 TGL_TRANS_CLK_SEL_DISABLED); 942 else 943 intel_de_write(dev_priv, 944 TRANS_CLK_SEL(cpu_transcoder), 945 TRANS_CLK_SEL_DISABLED); 946 } 947 } 948 949 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 950 enum port port, u8 iboost) 951 { 952 u32 tmp; 953 954 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 955 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 956 if (iboost) 957 tmp |= iboost << BALANCE_LEG_SHIFT(port); 958 else 959 tmp |= BALANCE_LEG_DISABLE(port); 960 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 961 } 962 963 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 964 const struct intel_crtc_state *crtc_state, 965 int level) 966 { 967 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 968 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 969 u8 iboost; 970 971 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 972 iboost = intel_bios_encoder_hdmi_boost_level(encoder->devdata); 973 else 974 iboost = intel_bios_encoder_dp_boost_level(encoder->devdata); 975 976 if (iboost == 0) { 977 const struct intel_ddi_buf_trans *trans; 978 int n_entries; 979 980 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 981 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 982 return; 983 984 iboost = trans->entries[level].hsw.i_boost; 985 } 986 987 /* Make sure that the requested I_boost is valid */ 988 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 989 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); 990 return; 991 } 992 993 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); 994 995 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 996 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 997 } 998 999 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1000 const struct intel_crtc_state *crtc_state) 1001 { 1002 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1003 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1004 int n_entries; 1005 1006 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1007 1008 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 1009 n_entries = 1; 1010 if (drm_WARN_ON(&dev_priv->drm, 1011 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1012 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1013 1014 return index_to_dp_signal_levels[n_entries - 1] & 1015 DP_TRAIN_VOLTAGE_SWING_MASK; 1016 } 1017 1018 /* 1019 * We assume that the full set of pre-emphasis values can be 1020 * used on all DDI platforms. Should that change we need to 1021 * rethink this code. 1022 */ 1023 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1024 { 1025 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1026 } 1027 1028 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1029 int lane) 1030 { 1031 if (crtc_state->port_clock > 600000) 1032 return 0; 1033 1034 if (crtc_state->lane_count == 4) 1035 return lane >= 1 ? LOADGEN_SELECT : 0; 1036 else 1037 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1038 } 1039 1040 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1041 const struct intel_crtc_state *crtc_state) 1042 { 1043 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1044 const struct intel_ddi_buf_trans *trans; 1045 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1046 int n_entries, ln; 1047 u32 val; 1048 1049 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1050 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1051 return; 1052 1053 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1054 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1055 1056 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1057 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1058 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, 1059 intel_dp->hobl_active ? val : 0); 1060 } 1061 1062 /* Set PORT_TX_DW5 */ 1063 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1064 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1065 TAP2_DISABLE | TAP3_DISABLE); 1066 val |= SCALING_MODE_SEL(0x2); 1067 val |= RTERM_SELECT(0x6); 1068 val |= TAP3_DISABLE; 1069 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1070 1071 /* Program PORT_TX_DW2 */ 1072 for (ln = 0; ln < 4; ln++) { 1073 int level = intel_ddi_level(encoder, crtc_state, ln); 1074 1075 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy), 1076 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1077 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1078 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1079 RCOMP_SCALAR(0x98)); 1080 } 1081 1082 /* Program PORT_TX_DW4 */ 1083 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1084 for (ln = 0; ln < 4; ln++) { 1085 int level = intel_ddi_level(encoder, crtc_state, ln); 1086 1087 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1088 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1089 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1090 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1091 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1092 } 1093 1094 /* Program PORT_TX_DW7 */ 1095 for (ln = 0; ln < 4; ln++) { 1096 int level = intel_ddi_level(encoder, crtc_state, ln); 1097 1098 intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy), 1099 N_SCALAR_MASK, 1100 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1101 } 1102 } 1103 1104 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1105 const struct intel_crtc_state *crtc_state) 1106 { 1107 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1108 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1109 u32 val; 1110 int ln; 1111 1112 /* 1113 * 1. If port type is eDP or DP, 1114 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1115 * else clear to 0b. 1116 */ 1117 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); 1118 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1119 val &= ~COMMON_KEEPER_EN; 1120 else 1121 val |= COMMON_KEEPER_EN; 1122 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 1123 1124 /* 2. Program loadgen select */ 1125 /* 1126 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1127 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1128 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1129 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1130 */ 1131 for (ln = 0; ln < 4; ln++) { 1132 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1133 LOADGEN_SELECT, 1134 icl_combo_phy_loadgen_select(crtc_state, ln)); 1135 } 1136 1137 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1138 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 1139 0, SUS_CLOCK_CONFIG); 1140 1141 /* 4. Clear training enable to change swing values */ 1142 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1143 val &= ~TX_TRAINING_EN; 1144 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1145 1146 /* 5. Program swing and de-emphasis */ 1147 icl_ddi_combo_vswing_program(encoder, crtc_state); 1148 1149 /* 6. Set training enable to trigger update */ 1150 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1151 val |= TX_TRAINING_EN; 1152 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1153 } 1154 1155 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1156 const struct intel_crtc_state *crtc_state) 1157 { 1158 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1159 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 1160 const struct intel_ddi_buf_trans *trans; 1161 int n_entries, ln; 1162 1163 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1164 return; 1165 1166 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1167 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1168 return; 1169 1170 for (ln = 0; ln < 2; ln++) { 1171 intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), 1172 CRI_USE_FS32, 0); 1173 intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), 1174 CRI_USE_FS32, 0); 1175 } 1176 1177 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1178 for (ln = 0; ln < 2; ln++) { 1179 int level; 1180 1181 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1182 1183 intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), 1184 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1185 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1186 1187 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1188 1189 intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), 1190 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1191 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1192 } 1193 1194 /* Program MG_TX_DRVCTRL with values from vswing table */ 1195 for (ln = 0; ln < 2; ln++) { 1196 int level; 1197 1198 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1199 1200 intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), 1201 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1202 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1203 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1204 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1205 CRI_TXDEEMPH_OVERRIDE_EN); 1206 1207 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1208 1209 intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), 1210 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1211 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1212 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1213 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1214 CRI_TXDEEMPH_OVERRIDE_EN); 1215 1216 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1217 } 1218 1219 /* 1220 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1221 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1222 * values from table for which TX1 and TX2 enabled. 1223 */ 1224 for (ln = 0; ln < 2; ln++) { 1225 intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port), 1226 CFG_LOW_RATE_LKREN_EN, 1227 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1228 } 1229 1230 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1231 for (ln = 0; ln < 2; ln++) { 1232 intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port), 1233 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1234 CFG_AMI_CK_DIV_OVERRIDE_EN, 1235 crtc_state->port_clock > 500000 ? 1236 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1237 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1238 1239 intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port), 1240 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1241 CFG_AMI_CK_DIV_OVERRIDE_EN, 1242 crtc_state->port_clock > 500000 ? 1243 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1244 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1245 } 1246 1247 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1248 for (ln = 0; ln < 2; ln++) { 1249 intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 1250 0, CRI_CALCINIT); 1251 intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 1252 0, CRI_CALCINIT); 1253 } 1254 } 1255 1256 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1257 const struct intel_crtc_state *crtc_state) 1258 { 1259 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1260 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 1261 const struct intel_ddi_buf_trans *trans; 1262 int n_entries, ln; 1263 1264 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1265 return; 1266 1267 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1268 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1269 return; 1270 1271 for (ln = 0; ln < 2; ln++) { 1272 int level; 1273 1274 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 1275 HIP_INDEX_VAL(tc_port, ln)); 1276 1277 intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0); 1278 1279 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1280 1281 intel_de_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port), 1282 DKL_TX_PRESHOOT_COEFF_MASK | 1283 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1284 DKL_TX_VSWING_CONTROL_MASK, 1285 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1286 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1287 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1288 1289 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1290 1291 intel_de_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port), 1292 DKL_TX_PRESHOOT_COEFF_MASK | 1293 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1294 DKL_TX_VSWING_CONTROL_MASK, 1295 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1296 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1297 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1298 1299 intel_de_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port), 1300 DKL_TX_DP20BITMODE, 0); 1301 } 1302 } 1303 1304 static int translate_signal_level(struct intel_dp *intel_dp, 1305 u8 signal_levels) 1306 { 1307 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1308 int i; 1309 1310 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1311 if (index_to_dp_signal_levels[i] == signal_levels) 1312 return i; 1313 } 1314 1315 drm_WARN(&i915->drm, 1, 1316 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1317 signal_levels); 1318 1319 return 0; 1320 } 1321 1322 static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1323 const struct intel_crtc_state *crtc_state, 1324 int lane) 1325 { 1326 u8 train_set = intel_dp->train_set[lane]; 1327 1328 if (intel_dp_is_uhbr(crtc_state)) { 1329 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1330 } else { 1331 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1332 DP_TRAIN_PRE_EMPHASIS_MASK); 1333 1334 return translate_signal_level(intel_dp, signal_levels); 1335 } 1336 } 1337 1338 int intel_ddi_level(struct intel_encoder *encoder, 1339 const struct intel_crtc_state *crtc_state, 1340 int lane) 1341 { 1342 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1343 const struct intel_ddi_buf_trans *trans; 1344 int level, n_entries; 1345 1346 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1347 if (drm_WARN_ON_ONCE(&i915->drm, !trans)) 1348 return 0; 1349 1350 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1351 level = intel_ddi_hdmi_level(encoder, trans); 1352 else 1353 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1354 lane); 1355 1356 if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries)) 1357 level = n_entries - 1; 1358 1359 return level; 1360 } 1361 1362 static void 1363 hsw_set_signal_levels(struct intel_encoder *encoder, 1364 const struct intel_crtc_state *crtc_state) 1365 { 1366 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1367 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1368 int level = intel_ddi_level(encoder, crtc_state, 0); 1369 enum port port = encoder->port; 1370 u32 signal_levels; 1371 1372 if (has_iboost(dev_priv)) 1373 skl_ddi_set_iboost(encoder, crtc_state, level); 1374 1375 /* HDMI ignores the rest */ 1376 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1377 return; 1378 1379 signal_levels = DDI_BUF_TRANS_SELECT(level); 1380 1381 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1382 signal_levels); 1383 1384 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1385 intel_dp->DP |= signal_levels; 1386 1387 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 1388 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 1389 } 1390 1391 static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1392 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1393 { 1394 mutex_lock(&i915->dpll.lock); 1395 1396 intel_de_rmw(i915, reg, clk_sel_mask, clk_sel); 1397 1398 /* 1399 * "This step and the step before must be 1400 * done with separate register writes." 1401 */ 1402 intel_de_rmw(i915, reg, clk_off, 0); 1403 1404 mutex_unlock(&i915->dpll.lock); 1405 } 1406 1407 static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1408 u32 clk_off) 1409 { 1410 mutex_lock(&i915->dpll.lock); 1411 1412 intel_de_rmw(i915, reg, 0, clk_off); 1413 1414 mutex_unlock(&i915->dpll.lock); 1415 } 1416 1417 static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg, 1418 u32 clk_off) 1419 { 1420 return !(intel_de_read(i915, reg) & clk_off); 1421 } 1422 1423 static struct intel_shared_dpll * 1424 _icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg, 1425 u32 clk_sel_mask, u32 clk_sel_shift) 1426 { 1427 enum intel_dpll_id id; 1428 1429 id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift; 1430 1431 return intel_get_shared_dpll_by_id(i915, id); 1432 } 1433 1434 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1435 const struct intel_crtc_state *crtc_state) 1436 { 1437 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1438 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1439 enum phy phy = intel_port_to_phy(i915, encoder->port); 1440 1441 if (drm_WARN_ON(&i915->drm, !pll)) 1442 return; 1443 1444 _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1445 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1446 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1447 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1448 } 1449 1450 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1451 { 1452 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1453 enum phy phy = intel_port_to_phy(i915, encoder->port); 1454 1455 _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1456 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1457 } 1458 1459 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1460 { 1461 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1462 enum phy phy = intel_port_to_phy(i915, encoder->port); 1463 1464 return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy), 1465 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1466 } 1467 1468 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1469 { 1470 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1471 enum phy phy = intel_port_to_phy(i915, encoder->port); 1472 1473 return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy), 1474 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1475 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1476 } 1477 1478 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1479 const struct intel_crtc_state *crtc_state) 1480 { 1481 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1482 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1483 enum phy phy = intel_port_to_phy(i915, encoder->port); 1484 1485 if (drm_WARN_ON(&i915->drm, !pll)) 1486 return; 1487 1488 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1489 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1490 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1491 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1492 } 1493 1494 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1495 { 1496 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1497 enum phy phy = intel_port_to_phy(i915, encoder->port); 1498 1499 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1500 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1501 } 1502 1503 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1504 { 1505 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1506 enum phy phy = intel_port_to_phy(i915, encoder->port); 1507 1508 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1509 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1510 } 1511 1512 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1513 { 1514 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1515 enum phy phy = intel_port_to_phy(i915, encoder->port); 1516 1517 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1518 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1519 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1520 } 1521 1522 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1523 const struct intel_crtc_state *crtc_state) 1524 { 1525 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1526 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1527 enum phy phy = intel_port_to_phy(i915, encoder->port); 1528 1529 if (drm_WARN_ON(&i915->drm, !pll)) 1530 return; 1531 1532 /* 1533 * If we fail this, something went very wrong: first 2 PLLs should be 1534 * used by first 2 phys and last 2 PLLs by last phys 1535 */ 1536 if (drm_WARN_ON(&i915->drm, 1537 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1538 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1539 return; 1540 1541 _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1542 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1543 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1544 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1545 } 1546 1547 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1548 { 1549 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1550 enum phy phy = intel_port_to_phy(i915, encoder->port); 1551 1552 _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1553 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1554 } 1555 1556 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1557 { 1558 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1559 enum phy phy = intel_port_to_phy(i915, encoder->port); 1560 1561 return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy), 1562 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1563 } 1564 1565 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1566 { 1567 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1568 enum phy phy = intel_port_to_phy(i915, encoder->port); 1569 enum intel_dpll_id id; 1570 u32 val; 1571 1572 val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy)); 1573 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1574 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1575 id = val; 1576 1577 /* 1578 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1579 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1580 * bit for phy C and D. 1581 */ 1582 if (phy >= PHY_C) 1583 id += DPLL_ID_DG1_DPLL2; 1584 1585 return intel_get_shared_dpll_by_id(i915, id); 1586 } 1587 1588 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1589 const struct intel_crtc_state *crtc_state) 1590 { 1591 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1592 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1593 enum phy phy = intel_port_to_phy(i915, encoder->port); 1594 1595 if (drm_WARN_ON(&i915->drm, !pll)) 1596 return; 1597 1598 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1599 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1600 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1601 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1602 } 1603 1604 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1605 { 1606 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1607 enum phy phy = intel_port_to_phy(i915, encoder->port); 1608 1609 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1610 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1611 } 1612 1613 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1614 { 1615 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1616 enum phy phy = intel_port_to_phy(i915, encoder->port); 1617 1618 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1619 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1620 } 1621 1622 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1623 { 1624 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1625 enum phy phy = intel_port_to_phy(i915, encoder->port); 1626 1627 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1628 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1629 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1630 } 1631 1632 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1633 const struct intel_crtc_state *crtc_state) 1634 { 1635 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1636 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1637 enum port port = encoder->port; 1638 1639 if (drm_WARN_ON(&i915->drm, !pll)) 1640 return; 1641 1642 /* 1643 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1644 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1645 */ 1646 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1647 1648 icl_ddi_combo_enable_clock(encoder, crtc_state); 1649 } 1650 1651 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1652 { 1653 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1654 enum port port = encoder->port; 1655 1656 icl_ddi_combo_disable_clock(encoder); 1657 1658 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1659 } 1660 1661 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1662 { 1663 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1664 enum port port = encoder->port; 1665 u32 tmp; 1666 1667 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1668 1669 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1670 return false; 1671 1672 return icl_ddi_combo_is_clock_enabled(encoder); 1673 } 1674 1675 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1676 const struct intel_crtc_state *crtc_state) 1677 { 1678 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1679 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1680 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1681 enum port port = encoder->port; 1682 1683 if (drm_WARN_ON(&i915->drm, !pll)) 1684 return; 1685 1686 intel_de_write(i915, DDI_CLK_SEL(port), 1687 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1688 1689 mutex_lock(&i915->dpll.lock); 1690 1691 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1692 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1693 1694 mutex_unlock(&i915->dpll.lock); 1695 } 1696 1697 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1698 { 1699 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1700 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1701 enum port port = encoder->port; 1702 1703 mutex_lock(&i915->dpll.lock); 1704 1705 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1706 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1707 1708 mutex_unlock(&i915->dpll.lock); 1709 1710 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1711 } 1712 1713 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1714 { 1715 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1716 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1717 enum port port = encoder->port; 1718 u32 tmp; 1719 1720 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1721 1722 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1723 return false; 1724 1725 tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0); 1726 1727 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1728 } 1729 1730 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1731 { 1732 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1733 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1734 enum port port = encoder->port; 1735 enum intel_dpll_id id; 1736 u32 tmp; 1737 1738 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1739 1740 switch (tmp & DDI_CLK_SEL_MASK) { 1741 case DDI_CLK_SEL_TBT_162: 1742 case DDI_CLK_SEL_TBT_270: 1743 case DDI_CLK_SEL_TBT_540: 1744 case DDI_CLK_SEL_TBT_810: 1745 id = DPLL_ID_ICL_TBTPLL; 1746 break; 1747 case DDI_CLK_SEL_MG: 1748 id = icl_tc_port_to_pll_id(tc_port); 1749 break; 1750 default: 1751 MISSING_CASE(tmp); 1752 fallthrough; 1753 case DDI_CLK_SEL_NONE: 1754 return NULL; 1755 } 1756 1757 return intel_get_shared_dpll_by_id(i915, id); 1758 } 1759 1760 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1761 { 1762 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1763 enum intel_dpll_id id; 1764 1765 switch (encoder->port) { 1766 case PORT_A: 1767 id = DPLL_ID_SKL_DPLL0; 1768 break; 1769 case PORT_B: 1770 id = DPLL_ID_SKL_DPLL1; 1771 break; 1772 case PORT_C: 1773 id = DPLL_ID_SKL_DPLL2; 1774 break; 1775 default: 1776 MISSING_CASE(encoder->port); 1777 return NULL; 1778 } 1779 1780 return intel_get_shared_dpll_by_id(i915, id); 1781 } 1782 1783 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1784 const struct intel_crtc_state *crtc_state) 1785 { 1786 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1787 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1788 enum port port = encoder->port; 1789 1790 if (drm_WARN_ON(&i915->drm, !pll)) 1791 return; 1792 1793 mutex_lock(&i915->dpll.lock); 1794 1795 intel_de_rmw(i915, DPLL_CTRL2, 1796 DPLL_CTRL2_DDI_CLK_OFF(port) | 1797 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1798 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1799 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1800 1801 mutex_unlock(&i915->dpll.lock); 1802 } 1803 1804 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1805 { 1806 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1807 enum port port = encoder->port; 1808 1809 mutex_lock(&i915->dpll.lock); 1810 1811 intel_de_rmw(i915, DPLL_CTRL2, 1812 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1813 1814 mutex_unlock(&i915->dpll.lock); 1815 } 1816 1817 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1818 { 1819 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1820 enum port port = encoder->port; 1821 1822 /* 1823 * FIXME Not sure if the override affects both 1824 * the PLL selection and the CLK_OFF bit. 1825 */ 1826 return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 1827 } 1828 1829 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 1830 { 1831 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1832 enum port port = encoder->port; 1833 enum intel_dpll_id id; 1834 u32 tmp; 1835 1836 tmp = intel_de_read(i915, DPLL_CTRL2); 1837 1838 /* 1839 * FIXME Not sure if the override affects both 1840 * the PLL selection and the CLK_OFF bit. 1841 */ 1842 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 1843 return NULL; 1844 1845 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 1846 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 1847 1848 return intel_get_shared_dpll_by_id(i915, id); 1849 } 1850 1851 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 1852 const struct intel_crtc_state *crtc_state) 1853 { 1854 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1855 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1856 enum port port = encoder->port; 1857 1858 if (drm_WARN_ON(&i915->drm, !pll)) 1859 return; 1860 1861 intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 1862 } 1863 1864 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 1865 { 1866 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1867 enum port port = encoder->port; 1868 1869 intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 1870 } 1871 1872 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 1873 { 1874 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1875 enum port port = encoder->port; 1876 1877 return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 1878 } 1879 1880 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 1881 { 1882 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1883 enum port port = encoder->port; 1884 enum intel_dpll_id id; 1885 u32 tmp; 1886 1887 tmp = intel_de_read(i915, PORT_CLK_SEL(port)); 1888 1889 switch (tmp & PORT_CLK_SEL_MASK) { 1890 case PORT_CLK_SEL_WRPLL1: 1891 id = DPLL_ID_WRPLL1; 1892 break; 1893 case PORT_CLK_SEL_WRPLL2: 1894 id = DPLL_ID_WRPLL2; 1895 break; 1896 case PORT_CLK_SEL_SPLL: 1897 id = DPLL_ID_SPLL; 1898 break; 1899 case PORT_CLK_SEL_LCPLL_810: 1900 id = DPLL_ID_LCPLL_810; 1901 break; 1902 case PORT_CLK_SEL_LCPLL_1350: 1903 id = DPLL_ID_LCPLL_1350; 1904 break; 1905 case PORT_CLK_SEL_LCPLL_2700: 1906 id = DPLL_ID_LCPLL_2700; 1907 break; 1908 default: 1909 MISSING_CASE(tmp); 1910 fallthrough; 1911 case PORT_CLK_SEL_NONE: 1912 return NULL; 1913 } 1914 1915 return intel_get_shared_dpll_by_id(i915, id); 1916 } 1917 1918 void intel_ddi_enable_clock(struct intel_encoder *encoder, 1919 const struct intel_crtc_state *crtc_state) 1920 { 1921 if (encoder->enable_clock) 1922 encoder->enable_clock(encoder, crtc_state); 1923 } 1924 1925 void intel_ddi_disable_clock(struct intel_encoder *encoder) 1926 { 1927 if (encoder->disable_clock) 1928 encoder->disable_clock(encoder); 1929 } 1930 1931 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 1932 { 1933 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1934 u32 port_mask; 1935 bool ddi_clk_needed; 1936 1937 /* 1938 * In case of DP MST, we sanitize the primary encoder only, not the 1939 * virtual ones. 1940 */ 1941 if (encoder->type == INTEL_OUTPUT_DP_MST) 1942 return; 1943 1944 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 1945 u8 pipe_mask; 1946 bool is_mst; 1947 1948 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 1949 /* 1950 * In the unlikely case that BIOS enables DP in MST mode, just 1951 * warn since our MST HW readout is incomplete. 1952 */ 1953 if (drm_WARN_ON(&i915->drm, is_mst)) 1954 return; 1955 } 1956 1957 port_mask = BIT(encoder->port); 1958 ddi_clk_needed = encoder->base.crtc; 1959 1960 if (encoder->type == INTEL_OUTPUT_DSI) { 1961 struct intel_encoder *other_encoder; 1962 1963 port_mask = intel_dsi_encoder_ports(encoder); 1964 /* 1965 * Sanity check that we haven't incorrectly registered another 1966 * encoder using any of the ports of this DSI encoder. 1967 */ 1968 for_each_intel_encoder(&i915->drm, other_encoder) { 1969 if (other_encoder == encoder) 1970 continue; 1971 1972 if (drm_WARN_ON(&i915->drm, 1973 port_mask & BIT(other_encoder->port))) 1974 return; 1975 } 1976 /* 1977 * For DSI we keep the ddi clocks gated 1978 * except during enable/disable sequence. 1979 */ 1980 ddi_clk_needed = false; 1981 } 1982 1983 if (ddi_clk_needed || !encoder->is_clock_enabled || 1984 !encoder->is_clock_enabled(encoder)) 1985 return; 1986 1987 drm_notice(&i915->drm, 1988 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 1989 encoder->base.base.id, encoder->base.name); 1990 1991 encoder->disable_clock(encoder); 1992 } 1993 1994 static void 1995 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 1996 const struct intel_crtc_state *crtc_state) 1997 { 1998 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 1999 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port); 2000 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); 2001 u32 ln0, ln1, pin_assignment; 2002 u8 width; 2003 2004 if (!intel_phy_is_tc(dev_priv, phy) || 2005 intel_tc_port_in_tbt_alt_mode(dig_port)) 2006 return; 2007 2008 if (DISPLAY_VER(dev_priv) >= 12) { 2009 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2010 HIP_INDEX_VAL(tc_port, 0x0)); 2011 ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); 2012 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2013 HIP_INDEX_VAL(tc_port, 0x1)); 2014 ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); 2015 } else { 2016 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 2017 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 2018 } 2019 2020 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2021 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2022 2023 /* DPPATC */ 2024 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 2025 width = crtc_state->lane_count; 2026 2027 switch (pin_assignment) { 2028 case 0x0: 2029 drm_WARN_ON(&dev_priv->drm, 2030 !intel_tc_port_in_legacy_mode(dig_port)); 2031 if (width == 1) { 2032 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2033 } else { 2034 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2035 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2036 } 2037 break; 2038 case 0x1: 2039 if (width == 4) { 2040 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2041 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2042 } 2043 break; 2044 case 0x2: 2045 if (width == 2) { 2046 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2047 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2048 } 2049 break; 2050 case 0x3: 2051 case 0x5: 2052 if (width == 1) { 2053 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2054 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2055 } else { 2056 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2057 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2058 } 2059 break; 2060 case 0x4: 2061 case 0x6: 2062 if (width == 1) { 2063 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2064 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2065 } else { 2066 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2067 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2068 } 2069 break; 2070 default: 2071 MISSING_CASE(pin_assignment); 2072 } 2073 2074 if (DISPLAY_VER(dev_priv) >= 12) { 2075 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2076 HIP_INDEX_VAL(tc_port, 0x0)); 2077 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0); 2078 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2079 HIP_INDEX_VAL(tc_port, 0x1)); 2080 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1); 2081 } else { 2082 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 2083 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 2084 } 2085 } 2086 2087 static enum transcoder 2088 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2089 { 2090 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2091 return crtc_state->mst_master_transcoder; 2092 else 2093 return crtc_state->cpu_transcoder; 2094 } 2095 2096 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2097 const struct intel_crtc_state *crtc_state) 2098 { 2099 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2100 2101 if (DISPLAY_VER(dev_priv) >= 12) 2102 return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state)); 2103 else 2104 return DP_TP_CTL(encoder->port); 2105 } 2106 2107 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2108 const struct intel_crtc_state *crtc_state) 2109 { 2110 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2111 2112 if (DISPLAY_VER(dev_priv) >= 12) 2113 return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state)); 2114 else 2115 return DP_TP_STATUS(encoder->port); 2116 } 2117 2118 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2119 const struct intel_crtc_state *crtc_state, 2120 bool enable) 2121 { 2122 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2123 2124 if (!crtc_state->vrr.enable) 2125 return; 2126 2127 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2128 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2129 drm_dbg_kms(&i915->drm, 2130 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2131 enabledisable(enable)); 2132 } 2133 2134 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2135 const struct intel_crtc_state *crtc_state) 2136 { 2137 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2138 2139 if (!crtc_state->fec_enable) 2140 return; 2141 2142 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0) 2143 drm_dbg_kms(&i915->drm, 2144 "Failed to set FEC_READY in the sink\n"); 2145 } 2146 2147 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2148 const struct intel_crtc_state *crtc_state) 2149 { 2150 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2151 struct intel_dp *intel_dp; 2152 u32 val; 2153 2154 if (!crtc_state->fec_enable) 2155 return; 2156 2157 intel_dp = enc_to_intel_dp(encoder); 2158 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2159 val |= DP_TP_CTL_FEC_ENABLE; 2160 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 2161 } 2162 2163 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder, 2164 const struct intel_crtc_state *crtc_state) 2165 { 2166 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2167 struct intel_dp *intel_dp; 2168 u32 val; 2169 2170 if (!crtc_state->fec_enable) 2171 return; 2172 2173 intel_dp = enc_to_intel_dp(encoder); 2174 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2175 val &= ~DP_TP_CTL_FEC_ENABLE; 2176 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 2177 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2178 } 2179 2180 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2181 const struct intel_crtc_state *crtc_state) 2182 { 2183 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2184 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2185 enum phy phy = intel_port_to_phy(i915, encoder->port); 2186 2187 if (intel_phy_is_combo(i915, phy)) { 2188 bool lane_reversal = 2189 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 2190 2191 intel_combo_phy_power_up_lanes(i915, phy, false, 2192 crtc_state->lane_count, 2193 lane_reversal); 2194 } 2195 } 2196 2197 /* Splitter enable for eDP MSO is limited to certain pipes. */ 2198 static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915) 2199 { 2200 if (IS_ALDERLAKE_P(i915)) 2201 return BIT(PIPE_A) | BIT(PIPE_B); 2202 else 2203 return BIT(PIPE_A); 2204 } 2205 2206 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2207 struct intel_crtc_state *pipe_config) 2208 { 2209 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2210 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2211 enum pipe pipe = crtc->pipe; 2212 u32 dss1; 2213 2214 if (!HAS_MSO(i915)) 2215 return; 2216 2217 dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); 2218 2219 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2220 if (!pipe_config->splitter.enable) 2221 return; 2222 2223 if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) { 2224 pipe_config->splitter.enable = false; 2225 return; 2226 } 2227 2228 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2229 default: 2230 drm_WARN(&i915->drm, true, 2231 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2232 fallthrough; 2233 case SPLITTER_CONFIGURATION_2_SEGMENT: 2234 pipe_config->splitter.link_count = 2; 2235 break; 2236 case SPLITTER_CONFIGURATION_4_SEGMENT: 2237 pipe_config->splitter.link_count = 4; 2238 break; 2239 } 2240 2241 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2242 } 2243 2244 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2245 { 2246 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2247 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2248 enum pipe pipe = crtc->pipe; 2249 u32 dss1 = 0; 2250 2251 if (!HAS_MSO(i915)) 2252 return; 2253 2254 if (crtc_state->splitter.enable) { 2255 dss1 |= SPLITTER_ENABLE; 2256 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2257 if (crtc_state->splitter.link_count == 2) 2258 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2259 else 2260 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2261 } 2262 2263 intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), 2264 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2265 OVERLAP_PIXELS_MASK, dss1); 2266 } 2267 2268 static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state, 2269 struct intel_encoder *encoder, 2270 const struct intel_crtc_state *crtc_state, 2271 const struct drm_connector_state *conn_state) 2272 { 2273 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2274 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2275 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2276 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2277 2278 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, 2279 crtc_state->lane_count); 2280 2281 /* 2282 * We only configure what the register value will be here. Actual 2283 * enabling happens during link training farther down. 2284 */ 2285 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2286 2287 /* 2288 * 1. Enable Power Wells 2289 * 2290 * This was handled at the beginning of intel_atomic_commit_tail(), 2291 * before we called down into this function. 2292 */ 2293 2294 /* 2. Enable Panel Power if PPS is required */ 2295 intel_pps_on(intel_dp); 2296 2297 /* 2298 * 3. Enable the port PLL. 2299 */ 2300 intel_ddi_enable_clock(encoder, crtc_state); 2301 2302 /* 4. Enable IO power */ 2303 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 2304 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2305 dig_port->ddi_io_power_domain); 2306 2307 /* 2308 * 5. The rest of the below are substeps under the bspec's "Enable and 2309 * Train Display Port" step. Note that steps that are specific to 2310 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2311 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2312 * us when active_mst_links==0, so any steps designated for "single 2313 * stream or multi-stream master transcoder" can just be performed 2314 * unconditionally here. 2315 */ 2316 2317 /* 2318 * 5.a Configure Transcoder Clock Select to direct the Port clock to the 2319 * Transcoder. 2320 */ 2321 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2322 2323 /* 5.b Configure transcoder for DP 2.0 128b/132b */ 2324 intel_ddi_config_transcoder_dp2(encoder, crtc_state); 2325 2326 /* 2327 * 5.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2328 * Transport Select 2329 */ 2330 intel_ddi_config_transcoder_func(encoder, crtc_state); 2331 2332 /* 2333 * 5.d Configure & enable DP_TP_CTL with link training pattern 1 2334 * selected 2335 * 2336 * This will be handled by the intel_dp_start_link_train() farther 2337 * down this function. 2338 */ 2339 2340 /* 5.e Configure voltage swing and related IO settings */ 2341 encoder->set_signal_levels(encoder, crtc_state); 2342 2343 if (!is_mst) 2344 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2345 2346 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2347 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); 2348 /* 2349 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2350 * in the FEC_CONFIGURATION register to 1 before initiating link 2351 * training 2352 */ 2353 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 2354 intel_dp_check_frl_training(intel_dp); 2355 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2356 2357 /* 2358 * 5.h Follow DisplayPort specification training sequence (see notes for 2359 * failure handling) 2360 * 5.i If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2361 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2362 * (timeout after 800 us) 2363 */ 2364 intel_dp_start_link_train(intel_dp, crtc_state); 2365 2366 /* 5.j Set DP_TP_CTL link training to Normal */ 2367 if (!is_trans_port_sync_mode(crtc_state)) 2368 intel_dp_stop_link_train(intel_dp, crtc_state); 2369 2370 /* 5.k Configure and enable FEC if needed */ 2371 intel_ddi_enable_fec(encoder, crtc_state); 2372 2373 intel_dsc_dp_pps_write(encoder, crtc_state); 2374 2375 intel_dsc_enable(crtc_state); 2376 } 2377 2378 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2379 struct intel_encoder *encoder, 2380 const struct intel_crtc_state *crtc_state, 2381 const struct drm_connector_state *conn_state) 2382 { 2383 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2384 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2385 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2386 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2387 2388 intel_dp_set_link_params(intel_dp, 2389 crtc_state->port_clock, 2390 crtc_state->lane_count); 2391 2392 /* 2393 * We only configure what the register value will be here. Actual 2394 * enabling happens during link training farther down. 2395 */ 2396 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2397 2398 /* 2399 * 1. Enable Power Wells 2400 * 2401 * This was handled at the beginning of intel_atomic_commit_tail(), 2402 * before we called down into this function. 2403 */ 2404 2405 /* 2. Enable Panel Power if PPS is required */ 2406 intel_pps_on(intel_dp); 2407 2408 /* 2409 * 3. For non-TBT Type-C ports, set FIA lane count 2410 * (DFLEXDPSP.DPX4TXLATC) 2411 * 2412 * This was done before tgl_ddi_pre_enable_dp by 2413 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2414 */ 2415 2416 /* 2417 * 4. Enable the port PLL. 2418 * 2419 * The PLL enabling itself was already done before this function by 2420 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 2421 * configure the PLL to port mapping here. 2422 */ 2423 intel_ddi_enable_clock(encoder, crtc_state); 2424 2425 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2426 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2427 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2428 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2429 dig_port->ddi_io_power_domain); 2430 } 2431 2432 /* 6. Program DP_MODE */ 2433 icl_program_mg_dp_mode(dig_port, crtc_state); 2434 2435 /* 2436 * 7. The rest of the below are substeps under the bspec's "Enable and 2437 * Train Display Port" step. Note that steps that are specific to 2438 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2439 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2440 * us when active_mst_links==0, so any steps designated for "single 2441 * stream or multi-stream master transcoder" can just be performed 2442 * unconditionally here. 2443 */ 2444 2445 /* 2446 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2447 * Transcoder. 2448 */ 2449 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2450 2451 /* 2452 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2453 * Transport Select 2454 */ 2455 intel_ddi_config_transcoder_func(encoder, crtc_state); 2456 2457 /* 2458 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2459 * selected 2460 * 2461 * This will be handled by the intel_dp_start_link_train() farther 2462 * down this function. 2463 */ 2464 2465 /* 7.e Configure voltage swing and related IO settings */ 2466 encoder->set_signal_levels(encoder, crtc_state); 2467 2468 /* 2469 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2470 * the used lanes of the DDI. 2471 */ 2472 intel_ddi_power_up_lanes(encoder, crtc_state); 2473 2474 /* 2475 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2476 */ 2477 intel_ddi_mso_configure(crtc_state); 2478 2479 if (!is_mst) 2480 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2481 2482 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2483 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); 2484 /* 2485 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2486 * in the FEC_CONFIGURATION register to 1 before initiating link 2487 * training 2488 */ 2489 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 2490 2491 intel_dp_check_frl_training(intel_dp); 2492 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2493 2494 /* 2495 * 7.i Follow DisplayPort specification training sequence (see notes for 2496 * failure handling) 2497 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2498 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2499 * (timeout after 800 us) 2500 */ 2501 intel_dp_start_link_train(intel_dp, crtc_state); 2502 2503 /* 7.k Set DP_TP_CTL link training to Normal */ 2504 if (!is_trans_port_sync_mode(crtc_state)) 2505 intel_dp_stop_link_train(intel_dp, crtc_state); 2506 2507 /* 7.l Configure and enable FEC if needed */ 2508 intel_ddi_enable_fec(encoder, crtc_state); 2509 2510 intel_dsc_dp_pps_write(encoder, crtc_state); 2511 2512 if (!crtc_state->bigjoiner) 2513 intel_dsc_enable(crtc_state); 2514 } 2515 2516 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2517 struct intel_encoder *encoder, 2518 const struct intel_crtc_state *crtc_state, 2519 const struct drm_connector_state *conn_state) 2520 { 2521 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2522 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2523 enum port port = encoder->port; 2524 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2525 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2526 2527 if (DISPLAY_VER(dev_priv) < 11) 2528 drm_WARN_ON(&dev_priv->drm, 2529 is_mst && (port == PORT_A || port == PORT_E)); 2530 else 2531 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 2532 2533 intel_dp_set_link_params(intel_dp, 2534 crtc_state->port_clock, 2535 crtc_state->lane_count); 2536 2537 /* 2538 * We only configure what the register value will be here. Actual 2539 * enabling happens during link training farther down. 2540 */ 2541 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2542 2543 intel_pps_on(intel_dp); 2544 2545 intel_ddi_enable_clock(encoder, crtc_state); 2546 2547 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2548 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2549 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2550 dig_port->ddi_io_power_domain); 2551 } 2552 2553 icl_program_mg_dp_mode(dig_port, crtc_state); 2554 2555 if (has_buf_trans_select(dev_priv)) 2556 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2557 2558 encoder->set_signal_levels(encoder, crtc_state); 2559 2560 intel_ddi_power_up_lanes(encoder, crtc_state); 2561 2562 if (!is_mst) 2563 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2564 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2565 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, 2566 true); 2567 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 2568 intel_dp_start_link_train(intel_dp, crtc_state); 2569 if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && 2570 !is_trans_port_sync_mode(crtc_state)) 2571 intel_dp_stop_link_train(intel_dp, crtc_state); 2572 2573 intel_ddi_enable_fec(encoder, crtc_state); 2574 2575 if (!is_mst) 2576 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2577 2578 intel_dsc_dp_pps_write(encoder, crtc_state); 2579 2580 if (!crtc_state->bigjoiner) 2581 intel_dsc_enable(crtc_state); 2582 } 2583 2584 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2585 struct intel_encoder *encoder, 2586 const struct intel_crtc_state *crtc_state, 2587 const struct drm_connector_state *conn_state) 2588 { 2589 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2590 2591 if (IS_DG2(dev_priv)) 2592 dg2_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2593 else if (DISPLAY_VER(dev_priv) >= 12) 2594 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2595 else 2596 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2597 2598 /* MST will call a setting of MSA after an allocating of Virtual Channel 2599 * from MST encoder pre_enable callback. 2600 */ 2601 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 2602 intel_ddi_set_dp_msa(crtc_state, conn_state); 2603 2604 intel_dp_set_m_n(crtc_state, M1_N1); 2605 } 2606 } 2607 2608 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2609 struct intel_encoder *encoder, 2610 const struct intel_crtc_state *crtc_state, 2611 const struct drm_connector_state *conn_state) 2612 { 2613 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2614 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2615 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2616 2617 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2618 intel_ddi_enable_clock(encoder, crtc_state); 2619 2620 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2621 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2622 dig_port->ddi_io_power_domain); 2623 2624 icl_program_mg_dp_mode(dig_port, crtc_state); 2625 2626 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2627 2628 dig_port->set_infoframes(encoder, 2629 crtc_state->has_infoframe, 2630 crtc_state, conn_state); 2631 } 2632 2633 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 2634 struct intel_encoder *encoder, 2635 const struct intel_crtc_state *crtc_state, 2636 const struct drm_connector_state *conn_state) 2637 { 2638 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2639 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2640 enum pipe pipe = crtc->pipe; 2641 2642 /* 2643 * When called from DP MST code: 2644 * - conn_state will be NULL 2645 * - encoder will be the main encoder (ie. mst->primary) 2646 * - the main connector associated with this port 2647 * won't be active or linked to a crtc 2648 * - crtc_state will be the state of the first stream to 2649 * be activated on this port, and it may not be the same 2650 * stream that will be deactivated last, but each stream 2651 * should have a state that is identical when it comes to 2652 * the DP link parameteres 2653 */ 2654 2655 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 2656 2657 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2658 2659 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 2660 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 2661 conn_state); 2662 } else { 2663 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2664 2665 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 2666 conn_state); 2667 2668 /* FIXME precompute everything properly */ 2669 /* FIXME how do we turn infoframes off again? */ 2670 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) 2671 dig_port->set_infoframes(encoder, 2672 crtc_state->has_infoframe, 2673 crtc_state, conn_state); 2674 } 2675 } 2676 2677 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 2678 const struct intel_crtc_state *crtc_state) 2679 { 2680 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2681 enum port port = encoder->port; 2682 bool wait = false; 2683 u32 val; 2684 2685 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2686 if (val & DDI_BUF_CTL_ENABLE) { 2687 val &= ~DDI_BUF_CTL_ENABLE; 2688 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 2689 wait = true; 2690 } 2691 2692 if (intel_crtc_has_dp_encoder(crtc_state)) { 2693 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2694 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 2695 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 2696 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 2697 } 2698 2699 /* Disable FEC in DP Sink */ 2700 intel_ddi_disable_fec_state(encoder, crtc_state); 2701 2702 if (wait) 2703 intel_wait_ddi_buf_idle(dev_priv, port); 2704 } 2705 2706 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 2707 struct intel_encoder *encoder, 2708 const struct intel_crtc_state *old_crtc_state, 2709 const struct drm_connector_state *old_conn_state) 2710 { 2711 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2712 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2713 struct intel_dp *intel_dp = &dig_port->dp; 2714 bool is_mst = intel_crtc_has_type(old_crtc_state, 2715 INTEL_OUTPUT_DP_MST); 2716 2717 if (!is_mst) 2718 intel_dp_set_infoframes(encoder, false, 2719 old_crtc_state, old_conn_state); 2720 2721 /* 2722 * Power down sink before disabling the port, otherwise we end 2723 * up getting interrupts from the sink on detecting link loss. 2724 */ 2725 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 2726 2727 if (DISPLAY_VER(dev_priv) >= 12) { 2728 if (is_mst) { 2729 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 2730 u32 val; 2731 2732 val = intel_de_read(dev_priv, 2733 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 2734 val &= ~(TGL_TRANS_DDI_PORT_MASK | 2735 TRANS_DDI_MODE_SELECT_MASK); 2736 intel_de_write(dev_priv, 2737 TRANS_DDI_FUNC_CTL(cpu_transcoder), 2738 val); 2739 } 2740 } else { 2741 if (!is_mst) 2742 intel_ddi_disable_pipe_clock(old_crtc_state); 2743 } 2744 2745 intel_disable_ddi_buf(encoder, old_crtc_state); 2746 2747 /* 2748 * From TGL spec: "If single stream or multi-stream master transcoder: 2749 * Configure Transcoder Clock select to direct no clock to the 2750 * transcoder" 2751 */ 2752 if (DISPLAY_VER(dev_priv) >= 12) 2753 intel_ddi_disable_pipe_clock(old_crtc_state); 2754 2755 intel_pps_vdd_on(intel_dp); 2756 intel_pps_off(intel_dp); 2757 2758 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 2759 intel_display_power_put(dev_priv, 2760 dig_port->ddi_io_power_domain, 2761 fetch_and_zero(&dig_port->ddi_io_wakeref)); 2762 2763 intel_ddi_disable_clock(encoder); 2764 } 2765 2766 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 2767 struct intel_encoder *encoder, 2768 const struct intel_crtc_state *old_crtc_state, 2769 const struct drm_connector_state *old_conn_state) 2770 { 2771 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2772 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2773 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2774 2775 dig_port->set_infoframes(encoder, false, 2776 old_crtc_state, old_conn_state); 2777 2778 intel_ddi_disable_pipe_clock(old_crtc_state); 2779 2780 intel_disable_ddi_buf(encoder, old_crtc_state); 2781 2782 intel_display_power_put(dev_priv, 2783 dig_port->ddi_io_power_domain, 2784 fetch_and_zero(&dig_port->ddi_io_wakeref)); 2785 2786 intel_ddi_disable_clock(encoder); 2787 2788 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 2789 } 2790 2791 static void intel_ddi_post_disable(struct intel_atomic_state *state, 2792 struct intel_encoder *encoder, 2793 const struct intel_crtc_state *old_crtc_state, 2794 const struct drm_connector_state *old_conn_state) 2795 { 2796 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2797 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2798 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2799 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 2800 2801 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) { 2802 intel_crtc_vblank_off(old_crtc_state); 2803 2804 intel_disable_transcoder(old_crtc_state); 2805 2806 intel_vrr_disable(old_crtc_state); 2807 2808 intel_ddi_disable_transcoder_func(old_crtc_state); 2809 2810 intel_dsc_disable(old_crtc_state); 2811 2812 if (DISPLAY_VER(dev_priv) >= 9) 2813 skl_scaler_disable(old_crtc_state); 2814 else 2815 ilk_pfit_disable(old_crtc_state); 2816 } 2817 2818 if (old_crtc_state->bigjoiner_linked_crtc) { 2819 struct intel_crtc *slave_crtc = 2820 old_crtc_state->bigjoiner_linked_crtc; 2821 const struct intel_crtc_state *old_slave_crtc_state = 2822 intel_atomic_get_old_crtc_state(state, slave_crtc); 2823 2824 intel_crtc_vblank_off(old_slave_crtc_state); 2825 2826 intel_dsc_disable(old_slave_crtc_state); 2827 skl_scaler_disable(old_slave_crtc_state); 2828 } 2829 2830 /* 2831 * When called from DP MST code: 2832 * - old_conn_state will be NULL 2833 * - encoder will be the main encoder (ie. mst->primary) 2834 * - the main connector associated with this port 2835 * won't be active or linked to a crtc 2836 * - old_crtc_state will be the state of the last stream to 2837 * be deactivated on this port, and it may not be the same 2838 * stream that was activated last, but each stream 2839 * should have a state that is identical when it comes to 2840 * the DP link parameteres 2841 */ 2842 2843 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 2844 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 2845 old_conn_state); 2846 else 2847 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 2848 old_conn_state); 2849 2850 if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port) 2851 intel_display_power_put(dev_priv, 2852 intel_ddi_main_link_aux_domain(dig_port), 2853 fetch_and_zero(&dig_port->aux_wakeref)); 2854 2855 if (is_tc_port) 2856 intel_tc_port_put_link(dig_port); 2857 } 2858 2859 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 2860 struct intel_encoder *encoder, 2861 const struct intel_crtc_state *crtc_state) 2862 { 2863 const struct drm_connector_state *conn_state; 2864 struct drm_connector *conn; 2865 int i; 2866 2867 if (!crtc_state->sync_mode_slaves_mask) 2868 return; 2869 2870 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 2871 struct intel_encoder *slave_encoder = 2872 to_intel_encoder(conn_state->best_encoder); 2873 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 2874 const struct intel_crtc_state *slave_crtc_state; 2875 2876 if (!slave_crtc) 2877 continue; 2878 2879 slave_crtc_state = 2880 intel_atomic_get_new_crtc_state(state, slave_crtc); 2881 2882 if (slave_crtc_state->master_transcoder != 2883 crtc_state->cpu_transcoder) 2884 continue; 2885 2886 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 2887 slave_crtc_state); 2888 } 2889 2890 usleep_range(200, 400); 2891 2892 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 2893 crtc_state); 2894 } 2895 2896 static void intel_enable_ddi_dp(struct intel_atomic_state *state, 2897 struct intel_encoder *encoder, 2898 const struct intel_crtc_state *crtc_state, 2899 const struct drm_connector_state *conn_state) 2900 { 2901 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2902 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2903 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2904 enum port port = encoder->port; 2905 2906 if (port == PORT_A && DISPLAY_VER(dev_priv) < 9) 2907 intel_dp_stop_link_train(intel_dp, crtc_state); 2908 2909 drm_connector_update_privacy_screen(conn_state); 2910 intel_edp_backlight_on(crtc_state, conn_state); 2911 2912 if (!dig_port->lspcon.active || dig_port->dp.has_hdmi_sink) 2913 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 2914 2915 intel_drrs_enable(intel_dp, crtc_state); 2916 2917 if (crtc_state->has_audio) 2918 intel_audio_codec_enable(encoder, crtc_state, conn_state); 2919 2920 trans_port_sync_stop_link_train(state, encoder, crtc_state); 2921 } 2922 2923 static i915_reg_t 2924 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 2925 enum port port) 2926 { 2927 static const enum transcoder trans[] = { 2928 [PORT_A] = TRANSCODER_EDP, 2929 [PORT_B] = TRANSCODER_A, 2930 [PORT_C] = TRANSCODER_B, 2931 [PORT_D] = TRANSCODER_C, 2932 [PORT_E] = TRANSCODER_A, 2933 }; 2934 2935 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9); 2936 2937 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) 2938 port = PORT_A; 2939 2940 return CHICKEN_TRANS(trans[port]); 2941 } 2942 2943 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, 2944 struct intel_encoder *encoder, 2945 const struct intel_crtc_state *crtc_state, 2946 const struct drm_connector_state *conn_state) 2947 { 2948 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2949 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2950 struct drm_connector *connector = conn_state->connector; 2951 enum port port = encoder->port; 2952 2953 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 2954 crtc_state->hdmi_high_tmds_clock_ratio, 2955 crtc_state->hdmi_scrambling)) 2956 drm_dbg_kms(&dev_priv->drm, 2957 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 2958 connector->base.id, connector->name); 2959 2960 if (has_buf_trans_select(dev_priv)) 2961 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 2962 2963 encoder->set_signal_levels(encoder, crtc_state); 2964 2965 /* Display WA #1143: skl,kbl,cfl */ 2966 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { 2967 /* 2968 * For some reason these chicken bits have been 2969 * stuffed into a transcoder register, event though 2970 * the bits affect a specific DDI port rather than 2971 * a specific transcoder. 2972 */ 2973 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 2974 u32 val; 2975 2976 val = intel_de_read(dev_priv, reg); 2977 2978 if (port == PORT_E) 2979 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 2980 DDIE_TRAINING_OVERRIDE_VALUE; 2981 else 2982 val |= DDI_TRAINING_OVERRIDE_ENABLE | 2983 DDI_TRAINING_OVERRIDE_VALUE; 2984 2985 intel_de_write(dev_priv, reg, val); 2986 intel_de_posting_read(dev_priv, reg); 2987 2988 udelay(1); 2989 2990 if (port == PORT_E) 2991 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 2992 DDIE_TRAINING_OVERRIDE_VALUE); 2993 else 2994 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 2995 DDI_TRAINING_OVERRIDE_VALUE); 2996 2997 intel_de_write(dev_priv, reg, val); 2998 } 2999 3000 intel_ddi_power_up_lanes(encoder, crtc_state); 3001 3002 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3003 * are ignored so nothing special needs to be done besides 3004 * enabling the port. 3005 * 3006 * On ADL_P the PHY link rate and lane count must be programmed but 3007 * these are both 0 for HDMI. 3008 */ 3009 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3010 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE); 3011 3012 if (crtc_state->has_audio) 3013 intel_audio_codec_enable(encoder, crtc_state, conn_state); 3014 } 3015 3016 static void intel_enable_ddi(struct intel_atomic_state *state, 3017 struct intel_encoder *encoder, 3018 const struct intel_crtc_state *crtc_state, 3019 const struct drm_connector_state *conn_state) 3020 { 3021 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 3022 3023 if (!crtc_state->bigjoiner_slave) 3024 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3025 3026 intel_vrr_enable(encoder, crtc_state); 3027 3028 intel_enable_transcoder(crtc_state); 3029 3030 intel_crtc_vblank_on(crtc_state); 3031 3032 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3033 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state); 3034 else 3035 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state); 3036 3037 /* Enable hdcp if it's desired */ 3038 if (conn_state->content_protection == 3039 DRM_MODE_CONTENT_PROTECTION_DESIRED) 3040 intel_hdcp_enable(to_intel_connector(conn_state->connector), 3041 crtc_state, 3042 (u8)conn_state->hdcp_content_type); 3043 } 3044 3045 static void intel_disable_ddi_dp(struct intel_atomic_state *state, 3046 struct intel_encoder *encoder, 3047 const struct intel_crtc_state *old_crtc_state, 3048 const struct drm_connector_state *old_conn_state) 3049 { 3050 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3051 3052 intel_dp->link_trained = false; 3053 3054 if (old_crtc_state->has_audio) 3055 intel_audio_codec_disable(encoder, 3056 old_crtc_state, old_conn_state); 3057 3058 intel_drrs_disable(intel_dp, old_crtc_state); 3059 intel_psr_disable(intel_dp, old_crtc_state); 3060 intel_edp_backlight_off(old_conn_state); 3061 /* Disable the decompression in DP Sink */ 3062 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, 3063 false); 3064 /* Disable Ignore_MSA bit in DP Sink */ 3065 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 3066 false); 3067 } 3068 3069 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state, 3070 struct intel_encoder *encoder, 3071 const struct intel_crtc_state *old_crtc_state, 3072 const struct drm_connector_state *old_conn_state) 3073 { 3074 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3075 struct drm_connector *connector = old_conn_state->connector; 3076 3077 if (old_crtc_state->has_audio) 3078 intel_audio_codec_disable(encoder, 3079 old_crtc_state, old_conn_state); 3080 3081 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3082 false, false)) 3083 drm_dbg_kms(&i915->drm, 3084 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3085 connector->base.id, connector->name); 3086 } 3087 3088 static void intel_disable_ddi(struct intel_atomic_state *state, 3089 struct intel_encoder *encoder, 3090 const struct intel_crtc_state *old_crtc_state, 3091 const struct drm_connector_state *old_conn_state) 3092 { 3093 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3094 3095 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3096 intel_disable_ddi_hdmi(state, encoder, old_crtc_state, 3097 old_conn_state); 3098 else 3099 intel_disable_ddi_dp(state, encoder, old_crtc_state, 3100 old_conn_state); 3101 } 3102 3103 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3104 struct intel_encoder *encoder, 3105 const struct intel_crtc_state *crtc_state, 3106 const struct drm_connector_state *conn_state) 3107 { 3108 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3109 3110 intel_ddi_set_dp_msa(crtc_state, conn_state); 3111 3112 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3113 intel_drrs_update(intel_dp, crtc_state); 3114 3115 intel_backlight_update(state, encoder, crtc_state, conn_state); 3116 drm_connector_update_privacy_screen(conn_state); 3117 } 3118 3119 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3120 struct intel_encoder *encoder, 3121 const struct intel_crtc_state *crtc_state, 3122 const struct drm_connector_state *conn_state) 3123 { 3124 3125 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3126 !intel_encoder_is_mst(encoder)) 3127 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3128 conn_state); 3129 3130 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3131 } 3132 3133 static void 3134 intel_ddi_update_prepare(struct intel_atomic_state *state, 3135 struct intel_encoder *encoder, 3136 struct intel_crtc *crtc) 3137 { 3138 struct intel_crtc_state *crtc_state = 3139 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL; 3140 int required_lanes = crtc_state ? crtc_state->lane_count : 1; 3141 3142 drm_WARN_ON(state->base.dev, crtc && crtc->active); 3143 3144 intel_tc_port_get_link(enc_to_dig_port(encoder), 3145 required_lanes); 3146 if (crtc_state && crtc_state->hw.active) { 3147 struct intel_crtc *slave_crtc = crtc_state->bigjoiner_linked_crtc; 3148 3149 intel_update_active_dpll(state, crtc, encoder); 3150 3151 if (slave_crtc) 3152 intel_update_active_dpll(state, slave_crtc, encoder); 3153 } 3154 } 3155 3156 static void 3157 intel_ddi_update_complete(struct intel_atomic_state *state, 3158 struct intel_encoder *encoder, 3159 struct intel_crtc *crtc) 3160 { 3161 intel_tc_port_put_link(enc_to_dig_port(encoder)); 3162 } 3163 3164 static void 3165 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3166 struct intel_encoder *encoder, 3167 const struct intel_crtc_state *crtc_state, 3168 const struct drm_connector_state *conn_state) 3169 { 3170 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3171 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3172 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3173 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 3174 3175 if (is_tc_port) 3176 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3177 3178 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) { 3179 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref); 3180 dig_port->aux_wakeref = 3181 intel_display_power_get(dev_priv, 3182 intel_ddi_main_link_aux_domain(dig_port)); 3183 } 3184 3185 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3186 /* 3187 * Program the lane count for static/dynamic connections on 3188 * Type-C ports. Skip this step for TBT. 3189 */ 3190 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3191 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3192 bxt_ddi_phy_set_lane_optim_mask(encoder, 3193 crtc_state->lane_lat_optim_mask); 3194 } 3195 3196 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3197 const struct intel_crtc_state *crtc_state) 3198 { 3199 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3200 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3201 enum port port = encoder->port; 3202 u32 dp_tp_ctl, ddi_buf_ctl; 3203 bool wait = false; 3204 3205 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3206 3207 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 3208 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3209 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 3210 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3211 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 3212 wait = true; 3213 } 3214 3215 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 3216 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1; 3217 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3218 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3219 3220 if (wait) 3221 intel_wait_ddi_buf_idle(dev_priv, port); 3222 } 3223 3224 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3225 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3226 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3227 } else { 3228 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3229 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 3230 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3231 } 3232 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3233 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3234 3235 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3236 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3237 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3238 3239 intel_wait_ddi_buf_active(dev_priv, port); 3240 } 3241 3242 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3243 const struct intel_crtc_state *crtc_state, 3244 u8 dp_train_pat) 3245 { 3246 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3247 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3248 u32 temp; 3249 3250 temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3251 3252 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3253 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3254 case DP_TRAINING_PATTERN_DISABLE: 3255 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3256 break; 3257 case DP_TRAINING_PATTERN_1: 3258 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3259 break; 3260 case DP_TRAINING_PATTERN_2: 3261 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3262 break; 3263 case DP_TRAINING_PATTERN_3: 3264 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3265 break; 3266 case DP_TRAINING_PATTERN_4: 3267 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3268 break; 3269 } 3270 3271 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp); 3272 } 3273 3274 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3275 const struct intel_crtc_state *crtc_state) 3276 { 3277 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3278 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3279 enum port port = encoder->port; 3280 u32 val; 3281 3282 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3283 val &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3284 val |= DP_TP_CTL_LINK_TRAIN_IDLE; 3285 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 3286 3287 /* 3288 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3289 * reason we need to set idle transmission mode is to work around a HW 3290 * issue where we enable the pipe while not in idle link-training mode. 3291 * In this case there is requirement to wait for a minimum number of 3292 * idle patterns to be sent. 3293 */ 3294 if (port == PORT_A && DISPLAY_VER(dev_priv) < 12) 3295 return; 3296 3297 if (intel_de_wait_for_set(dev_priv, 3298 dp_tp_status_reg(encoder, crtc_state), 3299 DP_TP_STATUS_IDLE_DONE, 1)) 3300 drm_err(&dev_priv->drm, 3301 "Timed out waiting for DP idle patterns\n"); 3302 } 3303 3304 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 3305 enum transcoder cpu_transcoder) 3306 { 3307 if (cpu_transcoder == TRANSCODER_EDP) 3308 return false; 3309 3310 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO)) 3311 return false; 3312 3313 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 3314 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3315 } 3316 3317 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, 3318 struct intel_crtc_state *crtc_state) 3319 { 3320 if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000) 3321 crtc_state->min_voltage_level = 2; 3322 else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000) 3323 crtc_state->min_voltage_level = 3; 3324 else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000) 3325 crtc_state->min_voltage_level = 1; 3326 } 3327 3328 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, 3329 enum transcoder cpu_transcoder) 3330 { 3331 u32 master_select; 3332 3333 if (DISPLAY_VER(dev_priv) >= 11) { 3334 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder)); 3335 3336 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3337 return INVALID_TRANSCODER; 3338 3339 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3340 } else { 3341 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3342 3343 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3344 return INVALID_TRANSCODER; 3345 3346 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3347 } 3348 3349 if (master_select == 0) 3350 return TRANSCODER_EDP; 3351 else 3352 return master_select - 1; 3353 } 3354 3355 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3356 { 3357 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3358 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3359 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3360 enum transcoder cpu_transcoder; 3361 3362 crtc_state->master_transcoder = 3363 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); 3364 3365 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { 3366 enum intel_display_power_domain power_domain; 3367 intel_wakeref_t trans_wakeref; 3368 3369 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3370 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 3371 power_domain); 3372 3373 if (!trans_wakeref) 3374 continue; 3375 3376 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == 3377 crtc_state->cpu_transcoder) 3378 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3379 3380 intel_display_power_put(dev_priv, power_domain, trans_wakeref); 3381 } 3382 3383 drm_WARN_ON(&dev_priv->drm, 3384 crtc_state->master_transcoder != INVALID_TRANSCODER && 3385 crtc_state->sync_mode_slaves_mask); 3386 } 3387 3388 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 3389 struct intel_crtc_state *pipe_config) 3390 { 3391 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3392 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3393 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3394 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3395 u32 temp, flags = 0; 3396 3397 temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3398 if (temp & TRANS_DDI_PHSYNC) 3399 flags |= DRM_MODE_FLAG_PHSYNC; 3400 else 3401 flags |= DRM_MODE_FLAG_NHSYNC; 3402 if (temp & TRANS_DDI_PVSYNC) 3403 flags |= DRM_MODE_FLAG_PVSYNC; 3404 else 3405 flags |= DRM_MODE_FLAG_NVSYNC; 3406 3407 pipe_config->hw.adjusted_mode.flags |= flags; 3408 3409 switch (temp & TRANS_DDI_BPC_MASK) { 3410 case TRANS_DDI_BPC_6: 3411 pipe_config->pipe_bpp = 18; 3412 break; 3413 case TRANS_DDI_BPC_8: 3414 pipe_config->pipe_bpp = 24; 3415 break; 3416 case TRANS_DDI_BPC_10: 3417 pipe_config->pipe_bpp = 30; 3418 break; 3419 case TRANS_DDI_BPC_12: 3420 pipe_config->pipe_bpp = 36; 3421 break; 3422 default: 3423 break; 3424 } 3425 3426 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 3427 case TRANS_DDI_MODE_SELECT_HDMI: 3428 pipe_config->has_hdmi_sink = true; 3429 3430 pipe_config->infoframes.enable |= 3431 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3432 3433 if (pipe_config->infoframes.enable) 3434 pipe_config->has_infoframe = true; 3435 3436 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 3437 pipe_config->hdmi_scrambling = true; 3438 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 3439 pipe_config->hdmi_high_tmds_clock_ratio = true; 3440 fallthrough; 3441 case TRANS_DDI_MODE_SELECT_DVI: 3442 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 3443 pipe_config->lane_count = 4; 3444 break; 3445 case TRANS_DDI_MODE_SELECT_DP_SST: 3446 if (encoder->type == INTEL_OUTPUT_EDP) 3447 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 3448 else 3449 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 3450 pipe_config->lane_count = 3451 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3452 intel_dp_get_m_n(crtc, pipe_config); 3453 3454 if (DISPLAY_VER(dev_priv) >= 11) { 3455 i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config); 3456 3457 pipe_config->fec_enable = 3458 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE; 3459 3460 drm_dbg_kms(&dev_priv->drm, 3461 "[ENCODER:%d:%s] Fec status: %u\n", 3462 encoder->base.base.id, encoder->base.name, 3463 pipe_config->fec_enable); 3464 } 3465 3466 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) 3467 pipe_config->infoframes.enable |= 3468 intel_lspcon_infoframes_enabled(encoder, pipe_config); 3469 else 3470 pipe_config->infoframes.enable |= 3471 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3472 break; 3473 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 3474 if (!HAS_DP20(dev_priv)) { 3475 /* FDI */ 3476 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 3477 break; 3478 } 3479 fallthrough; /* 128b/132b */ 3480 case TRANS_DDI_MODE_SELECT_DP_MST: 3481 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 3482 pipe_config->lane_count = 3483 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3484 3485 if (DISPLAY_VER(dev_priv) >= 12) 3486 pipe_config->mst_master_transcoder = 3487 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); 3488 3489 intel_dp_get_m_n(crtc, pipe_config); 3490 3491 pipe_config->infoframes.enable |= 3492 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3493 break; 3494 default: 3495 break; 3496 } 3497 } 3498 3499 static void intel_ddi_get_config(struct intel_encoder *encoder, 3500 struct intel_crtc_state *pipe_config) 3501 { 3502 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3503 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3504 3505 /* XXX: DSI transcoder paranoia */ 3506 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 3507 return; 3508 3509 intel_ddi_read_func_ctl(encoder, pipe_config); 3510 3511 intel_ddi_mso_get_config(encoder, pipe_config); 3512 3513 pipe_config->has_audio = 3514 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 3515 3516 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp && 3517 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { 3518 /* 3519 * This is a big fat ugly hack. 3520 * 3521 * Some machines in UEFI boot mode provide us a VBT that has 18 3522 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 3523 * unknown we fail to light up. Yet the same BIOS boots up with 3524 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 3525 * max, not what it tells us to use. 3526 * 3527 * Note: This will still be broken if the eDP panel is not lit 3528 * up by the BIOS, and thus we can't get the mode at module 3529 * load. 3530 */ 3531 drm_dbg_kms(&dev_priv->drm, 3532 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 3533 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); 3534 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; 3535 } 3536 3537 ddi_dotclock_get(pipe_config); 3538 3539 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3540 pipe_config->lane_lat_optim_mask = 3541 bxt_ddi_phy_get_lane_lat_optim_mask(encoder); 3542 3543 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 3544 3545 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 3546 3547 intel_read_infoframe(encoder, pipe_config, 3548 HDMI_INFOFRAME_TYPE_AVI, 3549 &pipe_config->infoframes.avi); 3550 intel_read_infoframe(encoder, pipe_config, 3551 HDMI_INFOFRAME_TYPE_SPD, 3552 &pipe_config->infoframes.spd); 3553 intel_read_infoframe(encoder, pipe_config, 3554 HDMI_INFOFRAME_TYPE_VENDOR, 3555 &pipe_config->infoframes.hdmi); 3556 intel_read_infoframe(encoder, pipe_config, 3557 HDMI_INFOFRAME_TYPE_DRM, 3558 &pipe_config->infoframes.drm); 3559 3560 if (DISPLAY_VER(dev_priv) >= 8) 3561 bdw_get_trans_port_sync_config(pipe_config); 3562 3563 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 3564 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 3565 3566 intel_psr_get_config(encoder, pipe_config); 3567 } 3568 3569 void intel_ddi_get_clock(struct intel_encoder *encoder, 3570 struct intel_crtc_state *crtc_state, 3571 struct intel_shared_dpll *pll) 3572 { 3573 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3574 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 3575 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 3576 bool pll_active; 3577 3578 if (drm_WARN_ON(&i915->drm, !pll)) 3579 return; 3580 3581 port_dpll->pll = pll; 3582 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 3583 drm_WARN_ON(&i915->drm, !pll_active); 3584 3585 icl_set_active_port_dpll(crtc_state, port_dpll_id); 3586 3587 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 3588 &crtc_state->dpll_hw_state); 3589 } 3590 3591 static void dg2_ddi_get_config(struct intel_encoder *encoder, 3592 struct intel_crtc_state *crtc_state) 3593 { 3594 intel_mpllb_readout_hw_state(encoder, &crtc_state->mpllb_state); 3595 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->mpllb_state); 3596 3597 intel_ddi_get_config(encoder, crtc_state); 3598 } 3599 3600 static void adls_ddi_get_config(struct intel_encoder *encoder, 3601 struct intel_crtc_state *crtc_state) 3602 { 3603 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 3604 intel_ddi_get_config(encoder, crtc_state); 3605 } 3606 3607 static void rkl_ddi_get_config(struct intel_encoder *encoder, 3608 struct intel_crtc_state *crtc_state) 3609 { 3610 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 3611 intel_ddi_get_config(encoder, crtc_state); 3612 } 3613 3614 static void dg1_ddi_get_config(struct intel_encoder *encoder, 3615 struct intel_crtc_state *crtc_state) 3616 { 3617 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 3618 intel_ddi_get_config(encoder, crtc_state); 3619 } 3620 3621 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 3622 struct intel_crtc_state *crtc_state) 3623 { 3624 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 3625 intel_ddi_get_config(encoder, crtc_state); 3626 } 3627 3628 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 3629 struct intel_crtc_state *crtc_state, 3630 struct intel_shared_dpll *pll) 3631 { 3632 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3633 enum icl_port_dpll_id port_dpll_id; 3634 struct icl_port_dpll *port_dpll; 3635 bool pll_active; 3636 3637 if (drm_WARN_ON(&i915->drm, !pll)) 3638 return; 3639 3640 if (intel_get_shared_dpll_id(i915, pll) == DPLL_ID_ICL_TBTPLL) 3641 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 3642 else 3643 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 3644 3645 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 3646 3647 port_dpll->pll = pll; 3648 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 3649 drm_WARN_ON(&i915->drm, !pll_active); 3650 3651 icl_set_active_port_dpll(crtc_state, port_dpll_id); 3652 3653 if (intel_get_shared_dpll_id(i915, crtc_state->shared_dpll) == DPLL_ID_ICL_TBTPLL) 3654 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port); 3655 else 3656 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 3657 &crtc_state->dpll_hw_state); 3658 } 3659 3660 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 3661 struct intel_crtc_state *crtc_state) 3662 { 3663 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 3664 intel_ddi_get_config(encoder, crtc_state); 3665 } 3666 3667 static void bxt_ddi_get_config(struct intel_encoder *encoder, 3668 struct intel_crtc_state *crtc_state) 3669 { 3670 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 3671 intel_ddi_get_config(encoder, crtc_state); 3672 } 3673 3674 static void skl_ddi_get_config(struct intel_encoder *encoder, 3675 struct intel_crtc_state *crtc_state) 3676 { 3677 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 3678 intel_ddi_get_config(encoder, crtc_state); 3679 } 3680 3681 void hsw_ddi_get_config(struct intel_encoder *encoder, 3682 struct intel_crtc_state *crtc_state) 3683 { 3684 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 3685 intel_ddi_get_config(encoder, crtc_state); 3686 } 3687 3688 static void intel_ddi_sync_state(struct intel_encoder *encoder, 3689 const struct intel_crtc_state *crtc_state) 3690 { 3691 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3692 enum phy phy = intel_port_to_phy(i915, encoder->port); 3693 3694 if (intel_phy_is_tc(i915, phy)) 3695 intel_tc_port_sanitize(enc_to_dig_port(encoder)); 3696 3697 if (crtc_state && intel_crtc_has_dp_encoder(crtc_state)) 3698 intel_dp_sync_state(encoder, crtc_state); 3699 } 3700 3701 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 3702 struct intel_crtc_state *crtc_state) 3703 { 3704 if (intel_crtc_has_dp_encoder(crtc_state)) 3705 return intel_dp_initial_fastset_check(encoder, crtc_state); 3706 3707 return true; 3708 } 3709 3710 static enum intel_output_type 3711 intel_ddi_compute_output_type(struct intel_encoder *encoder, 3712 struct intel_crtc_state *crtc_state, 3713 struct drm_connector_state *conn_state) 3714 { 3715 switch (conn_state->connector->connector_type) { 3716 case DRM_MODE_CONNECTOR_HDMIA: 3717 return INTEL_OUTPUT_HDMI; 3718 case DRM_MODE_CONNECTOR_eDP: 3719 return INTEL_OUTPUT_EDP; 3720 case DRM_MODE_CONNECTOR_DisplayPort: 3721 return INTEL_OUTPUT_DP; 3722 default: 3723 MISSING_CASE(conn_state->connector->connector_type); 3724 return INTEL_OUTPUT_UNUSED; 3725 } 3726 } 3727 3728 static int intel_ddi_compute_config(struct intel_encoder *encoder, 3729 struct intel_crtc_state *pipe_config, 3730 struct drm_connector_state *conn_state) 3731 { 3732 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3733 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3734 enum port port = encoder->port; 3735 int ret; 3736 3737 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 3738 pipe_config->cpu_transcoder = TRANSCODER_EDP; 3739 3740 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 3741 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 3742 } else { 3743 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 3744 } 3745 3746 if (ret) 3747 return ret; 3748 3749 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 3750 pipe_config->cpu_transcoder == TRANSCODER_EDP) 3751 pipe_config->pch_pfit.force_thru = 3752 pipe_config->pch_pfit.enabled || 3753 pipe_config->crc_enabled; 3754 3755 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3756 pipe_config->lane_lat_optim_mask = 3757 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 3758 3759 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 3760 3761 return 0; 3762 } 3763 3764 static bool mode_equal(const struct drm_display_mode *mode1, 3765 const struct drm_display_mode *mode2) 3766 { 3767 return drm_mode_match(mode1, mode2, 3768 DRM_MODE_MATCH_TIMINGS | 3769 DRM_MODE_MATCH_FLAGS | 3770 DRM_MODE_MATCH_3D_FLAGS) && 3771 mode1->clock == mode2->clock; /* we want an exact match */ 3772 } 3773 3774 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 3775 const struct intel_link_m_n *m_n_2) 3776 { 3777 return m_n_1->tu == m_n_2->tu && 3778 m_n_1->gmch_m == m_n_2->gmch_m && 3779 m_n_1->gmch_n == m_n_2->gmch_n && 3780 m_n_1->link_m == m_n_2->link_m && 3781 m_n_1->link_n == m_n_2->link_n; 3782 } 3783 3784 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 3785 const struct intel_crtc_state *crtc_state2) 3786 { 3787 return crtc_state1->hw.active && crtc_state2->hw.active && 3788 crtc_state1->output_types == crtc_state2->output_types && 3789 crtc_state1->output_format == crtc_state2->output_format && 3790 crtc_state1->lane_count == crtc_state2->lane_count && 3791 crtc_state1->port_clock == crtc_state2->port_clock && 3792 mode_equal(&crtc_state1->hw.adjusted_mode, 3793 &crtc_state2->hw.adjusted_mode) && 3794 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 3795 } 3796 3797 static u8 3798 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 3799 int tile_group_id) 3800 { 3801 struct drm_connector *connector; 3802 const struct drm_connector_state *conn_state; 3803 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 3804 struct intel_atomic_state *state = 3805 to_intel_atomic_state(ref_crtc_state->uapi.state); 3806 u8 transcoders = 0; 3807 int i; 3808 3809 /* 3810 * We don't enable port sync on BDW due to missing w/as and 3811 * due to not having adjusted the modeset sequence appropriately. 3812 */ 3813 if (DISPLAY_VER(dev_priv) < 9) 3814 return 0; 3815 3816 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 3817 return 0; 3818 3819 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 3820 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 3821 const struct intel_crtc_state *crtc_state; 3822 3823 if (!crtc) 3824 continue; 3825 3826 if (!connector->has_tile || 3827 connector->tile_group->id != 3828 tile_group_id) 3829 continue; 3830 crtc_state = intel_atomic_get_new_crtc_state(state, 3831 crtc); 3832 if (!crtcs_port_sync_compatible(ref_crtc_state, 3833 crtc_state)) 3834 continue; 3835 transcoders |= BIT(crtc_state->cpu_transcoder); 3836 } 3837 3838 return transcoders; 3839 } 3840 3841 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 3842 struct intel_crtc_state *crtc_state, 3843 struct drm_connector_state *conn_state) 3844 { 3845 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3846 struct drm_connector *connector = conn_state->connector; 3847 u8 port_sync_transcoders = 0; 3848 3849 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]", 3850 encoder->base.base.id, encoder->base.name, 3851 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 3852 3853 if (connector->has_tile) 3854 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 3855 connector->tile_group->id); 3856 3857 /* 3858 * EDP Transcoders cannot be ensalved 3859 * make them a master always when present 3860 */ 3861 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 3862 crtc_state->master_transcoder = TRANSCODER_EDP; 3863 else 3864 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 3865 3866 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 3867 crtc_state->master_transcoder = INVALID_TRANSCODER; 3868 crtc_state->sync_mode_slaves_mask = 3869 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 3870 } 3871 3872 return 0; 3873 } 3874 3875 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 3876 { 3877 struct drm_i915_private *i915 = to_i915(encoder->dev); 3878 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 3879 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 3880 3881 intel_dp_encoder_flush_work(encoder); 3882 if (intel_phy_is_tc(i915, phy)) 3883 intel_tc_port_flush_work(dig_port); 3884 intel_display_power_flush_work(i915); 3885 3886 drm_encoder_cleanup(encoder); 3887 kfree(dig_port->hdcp_port_data.streams); 3888 kfree(dig_port); 3889 } 3890 3891 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 3892 { 3893 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 3894 3895 intel_dp->reset_link_params = true; 3896 3897 intel_pps_encoder_reset(intel_dp); 3898 } 3899 3900 static const struct drm_encoder_funcs intel_ddi_funcs = { 3901 .reset = intel_ddi_encoder_reset, 3902 .destroy = intel_ddi_encoder_destroy, 3903 }; 3904 3905 static struct intel_connector * 3906 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 3907 { 3908 struct intel_connector *connector; 3909 enum port port = dig_port->base.port; 3910 3911 connector = intel_connector_alloc(); 3912 if (!connector) 3913 return NULL; 3914 3915 dig_port->dp.output_reg = DDI_BUF_CTL(port); 3916 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 3917 dig_port->dp.set_link_train = intel_ddi_set_link_train; 3918 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 3919 3920 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 3921 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 3922 3923 if (!intel_dp_init_connector(dig_port, connector)) { 3924 kfree(connector); 3925 return NULL; 3926 } 3927 3928 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 3929 struct drm_device *dev = dig_port->base.base.dev; 3930 struct drm_privacy_screen *privacy_screen; 3931 3932 privacy_screen = drm_privacy_screen_get(dev->dev, NULL); 3933 if (!IS_ERR(privacy_screen)) { 3934 drm_connector_attach_privacy_screen_provider(&connector->base, 3935 privacy_screen); 3936 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 3937 drm_warn(dev, "Error getting privacy-screen\n"); 3938 } 3939 } 3940 3941 return connector; 3942 } 3943 3944 static int modeset_pipe(struct drm_crtc *crtc, 3945 struct drm_modeset_acquire_ctx *ctx) 3946 { 3947 struct drm_atomic_state *state; 3948 struct drm_crtc_state *crtc_state; 3949 int ret; 3950 3951 state = drm_atomic_state_alloc(crtc->dev); 3952 if (!state) 3953 return -ENOMEM; 3954 3955 state->acquire_ctx = ctx; 3956 3957 crtc_state = drm_atomic_get_crtc_state(state, crtc); 3958 if (IS_ERR(crtc_state)) { 3959 ret = PTR_ERR(crtc_state); 3960 goto out; 3961 } 3962 3963 crtc_state->connectors_changed = true; 3964 3965 ret = drm_atomic_commit(state); 3966 out: 3967 drm_atomic_state_put(state); 3968 3969 return ret; 3970 } 3971 3972 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 3973 struct drm_modeset_acquire_ctx *ctx) 3974 { 3975 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3976 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 3977 struct intel_connector *connector = hdmi->attached_connector; 3978 struct i2c_adapter *adapter = 3979 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 3980 struct drm_connector_state *conn_state; 3981 struct intel_crtc_state *crtc_state; 3982 struct intel_crtc *crtc; 3983 u8 config; 3984 int ret; 3985 3986 if (!connector || connector->base.status != connector_status_connected) 3987 return 0; 3988 3989 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 3990 ctx); 3991 if (ret) 3992 return ret; 3993 3994 conn_state = connector->base.state; 3995 3996 crtc = to_intel_crtc(conn_state->crtc); 3997 if (!crtc) 3998 return 0; 3999 4000 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4001 if (ret) 4002 return ret; 4003 4004 crtc_state = to_intel_crtc_state(crtc->base.state); 4005 4006 drm_WARN_ON(&dev_priv->drm, 4007 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4008 4009 if (!crtc_state->hw.active) 4010 return 0; 4011 4012 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4013 !crtc_state->hdmi_scrambling) 4014 return 0; 4015 4016 if (conn_state->commit && 4017 !try_wait_for_completion(&conn_state->commit->hw_done)) 4018 return 0; 4019 4020 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 4021 if (ret < 0) { 4022 drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n", 4023 ret); 4024 return 0; 4025 } 4026 4027 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4028 crtc_state->hdmi_high_tmds_clock_ratio && 4029 !!(config & SCDC_SCRAMBLING_ENABLE) == 4030 crtc_state->hdmi_scrambling) 4031 return 0; 4032 4033 /* 4034 * HDMI 2.0 says that one should not send scrambled data 4035 * prior to configuring the sink scrambling, and that 4036 * TMDS clock/data transmission should be suspended when 4037 * changing the TMDS clock rate in the sink. So let's 4038 * just do a full modeset here, even though some sinks 4039 * would be perfectly happy if were to just reconfigure 4040 * the SCDC settings on the fly. 4041 */ 4042 return modeset_pipe(&crtc->base, ctx); 4043 } 4044 4045 static enum intel_hotplug_state 4046 intel_ddi_hotplug(struct intel_encoder *encoder, 4047 struct intel_connector *connector) 4048 { 4049 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4050 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4051 struct intel_dp *intel_dp = &dig_port->dp; 4052 enum phy phy = intel_port_to_phy(i915, encoder->port); 4053 bool is_tc = intel_phy_is_tc(i915, phy); 4054 struct drm_modeset_acquire_ctx ctx; 4055 enum intel_hotplug_state state; 4056 int ret; 4057 4058 if (intel_dp->compliance.test_active && 4059 intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) { 4060 intel_dp_phy_test(encoder); 4061 /* just do the PHY test and nothing else */ 4062 return INTEL_HOTPLUG_UNCHANGED; 4063 } 4064 4065 state = intel_encoder_hotplug(encoder, connector); 4066 4067 drm_modeset_acquire_init(&ctx, 0); 4068 4069 for (;;) { 4070 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) 4071 ret = intel_hdmi_reset_link(encoder, &ctx); 4072 else 4073 ret = intel_dp_retrain_link(encoder, &ctx); 4074 4075 if (ret == -EDEADLK) { 4076 drm_modeset_backoff(&ctx); 4077 continue; 4078 } 4079 4080 break; 4081 } 4082 4083 drm_modeset_drop_locks(&ctx); 4084 drm_modeset_acquire_fini(&ctx); 4085 drm_WARN(encoder->base.dev, ret, 4086 "Acquiring modeset locks failed with %i\n", ret); 4087 4088 /* 4089 * Unpowered type-c dongles can take some time to boot and be 4090 * responsible, so here giving some time to those dongles to power up 4091 * and then retrying the probe. 4092 * 4093 * On many platforms the HDMI live state signal is known to be 4094 * unreliable, so we can't use it to detect if a sink is connected or 4095 * not. Instead we detect if it's connected based on whether we can 4096 * read the EDID or not. That in turn has a problem during disconnect, 4097 * since the HPD interrupt may be raised before the DDC lines get 4098 * disconnected (due to how the required length of DDC vs. HPD 4099 * connector pins are specified) and so we'll still be able to get a 4100 * valid EDID. To solve this schedule another detection cycle if this 4101 * time around we didn't detect any change in the sink's connection 4102 * status. 4103 * 4104 * Type-c connectors which get their HPD signal deasserted then 4105 * reasserted, without unplugging/replugging the sink from the 4106 * connector, introduce a delay until the AUX channel communication 4107 * becomes functional. Retry the detection for 5 seconds on type-c 4108 * connectors to account for this delay. 4109 */ 4110 if (state == INTEL_HOTPLUG_UNCHANGED && 4111 connector->hotplug_retries < (is_tc ? 5 : 1) && 4112 !dig_port->dp.is_mst) 4113 state = INTEL_HOTPLUG_RETRY; 4114 4115 return state; 4116 } 4117 4118 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4119 { 4120 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4121 u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin]; 4122 4123 return intel_de_read(dev_priv, SDEISR) & bit; 4124 } 4125 4126 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4127 { 4128 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4129 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; 4130 4131 return intel_de_read(dev_priv, DEISR) & bit; 4132 } 4133 4134 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4135 { 4136 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4137 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; 4138 4139 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; 4140 } 4141 4142 static struct intel_connector * 4143 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4144 { 4145 struct intel_connector *connector; 4146 enum port port = dig_port->base.port; 4147 4148 connector = intel_connector_alloc(); 4149 if (!connector) 4150 return NULL; 4151 4152 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4153 intel_hdmi_init_connector(dig_port, connector); 4154 4155 return connector; 4156 } 4157 4158 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4159 { 4160 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4161 4162 if (dig_port->base.port != PORT_A) 4163 return false; 4164 4165 if (dig_port->saved_port_bits & DDI_A_4_LANES) 4166 return false; 4167 4168 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4169 * supported configuration 4170 */ 4171 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4172 return true; 4173 4174 return false; 4175 } 4176 4177 static int 4178 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4179 { 4180 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4181 enum port port = dig_port->base.port; 4182 int max_lanes = 4; 4183 4184 if (DISPLAY_VER(dev_priv) >= 11) 4185 return max_lanes; 4186 4187 if (port == PORT_A || port == PORT_E) { 4188 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4189 max_lanes = port == PORT_A ? 4 : 0; 4190 else 4191 /* Both A and E share 2 lanes */ 4192 max_lanes = 2; 4193 } 4194 4195 /* 4196 * Some BIOS might fail to set this bit on port A if eDP 4197 * wasn't lit up at boot. Force this bit set when needed 4198 * so we use the proper lane count for our calculations. 4199 */ 4200 if (intel_ddi_a_force_4_lanes(dig_port)) { 4201 drm_dbg_kms(&dev_priv->drm, 4202 "Forcing DDI_A_4_LANES for port A\n"); 4203 dig_port->saved_port_bits |= DDI_A_4_LANES; 4204 max_lanes = 4; 4205 } 4206 4207 return max_lanes; 4208 } 4209 4210 static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy) 4211 { 4212 return i915->hti_state & HDPORT_ENABLED && 4213 i915->hti_state & HDPORT_DDI_USED(phy); 4214 } 4215 4216 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv, 4217 enum port port) 4218 { 4219 if (port >= PORT_D_XELPD) 4220 return HPD_PORT_D + port - PORT_D_XELPD; 4221 else if (port >= PORT_TC1) 4222 return HPD_PORT_TC1 + port - PORT_TC1; 4223 else 4224 return HPD_PORT_A + port - PORT_A; 4225 } 4226 4227 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, 4228 enum port port) 4229 { 4230 if (port >= PORT_TC1) 4231 return HPD_PORT_C + port - PORT_TC1; 4232 else 4233 return HPD_PORT_A + port - PORT_A; 4234 } 4235 4236 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, 4237 enum port port) 4238 { 4239 if (port >= PORT_TC1) 4240 return HPD_PORT_TC1 + port - PORT_TC1; 4241 else 4242 return HPD_PORT_A + port - PORT_A; 4243 } 4244 4245 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, 4246 enum port port) 4247 { 4248 if (HAS_PCH_TGP(dev_priv)) 4249 return tgl_hpd_pin(dev_priv, port); 4250 4251 if (port >= PORT_TC1) 4252 return HPD_PORT_C + port - PORT_TC1; 4253 else 4254 return HPD_PORT_A + port - PORT_A; 4255 } 4256 4257 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, 4258 enum port port) 4259 { 4260 if (port >= PORT_C) 4261 return HPD_PORT_TC1 + port - PORT_C; 4262 else 4263 return HPD_PORT_A + port - PORT_A; 4264 } 4265 4266 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, 4267 enum port port) 4268 { 4269 if (port == PORT_D) 4270 return HPD_PORT_A; 4271 4272 if (HAS_PCH_MCC(dev_priv)) 4273 return icl_hpd_pin(dev_priv, port); 4274 4275 return HPD_PORT_A + port - PORT_A; 4276 } 4277 4278 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) 4279 { 4280 if (HAS_PCH_TGP(dev_priv)) 4281 return icl_hpd_pin(dev_priv, port); 4282 4283 return HPD_PORT_A + port - PORT_A; 4284 } 4285 4286 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port) 4287 { 4288 if (DISPLAY_VER(i915) >= 12) 4289 return port >= PORT_TC1; 4290 else if (DISPLAY_VER(i915) >= 11) 4291 return port >= PORT_C; 4292 else 4293 return false; 4294 } 4295 4296 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 4297 { 4298 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4299 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4300 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4301 enum phy phy = intel_port_to_phy(i915, encoder->port); 4302 4303 intel_dp_encoder_suspend(encoder); 4304 4305 if (!intel_phy_is_tc(i915, phy)) 4306 return; 4307 4308 intel_tc_port_flush_work(dig_port); 4309 } 4310 4311 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 4312 { 4313 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4314 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4315 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4316 enum phy phy = intel_port_to_phy(i915, encoder->port); 4317 4318 intel_dp_encoder_shutdown(encoder); 4319 intel_hdmi_encoder_shutdown(encoder); 4320 4321 if (!intel_phy_is_tc(i915, phy)) 4322 return; 4323 4324 intel_tc_port_flush_work(dig_port); 4325 } 4326 4327 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 4328 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 4329 4330 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 4331 { 4332 struct intel_digital_port *dig_port; 4333 struct intel_encoder *encoder; 4334 const struct intel_bios_encoder_data *devdata; 4335 bool init_hdmi, init_dp; 4336 enum phy phy = intel_port_to_phy(dev_priv, port); 4337 4338 /* 4339 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 4340 * have taken over some of the PHYs and made them unavailable to the 4341 * driver. In that case we should skip initializing the corresponding 4342 * outputs. 4343 */ 4344 if (hti_uses_phy(dev_priv, phy)) { 4345 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", 4346 port_name(port), phy_name(phy)); 4347 return; 4348 } 4349 4350 devdata = intel_bios_encoder_data_lookup(dev_priv, port); 4351 if (!devdata) { 4352 drm_dbg_kms(&dev_priv->drm, 4353 "VBT says port %c is not present\n", 4354 port_name(port)); 4355 return; 4356 } 4357 4358 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 4359 intel_bios_encoder_supports_hdmi(devdata); 4360 init_dp = intel_bios_encoder_supports_dp(devdata); 4361 4362 if (intel_bios_is_lspcon_present(dev_priv, port)) { 4363 /* 4364 * Lspcon device needs to be driven with DP connector 4365 * with special detection sequence. So make sure DP 4366 * is initialized before lspcon. 4367 */ 4368 init_dp = true; 4369 init_hdmi = false; 4370 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", 4371 port_name(port)); 4372 } 4373 4374 if (!init_dp && !init_hdmi) { 4375 drm_dbg_kms(&dev_priv->drm, 4376 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 4377 port_name(port)); 4378 return; 4379 } 4380 4381 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 4382 if (!dig_port) 4383 return; 4384 4385 encoder = &dig_port->base; 4386 encoder->devdata = devdata; 4387 4388 if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) { 4389 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4390 DRM_MODE_ENCODER_TMDS, 4391 "DDI %c/PHY %c", 4392 port_name(port - PORT_D_XELPD + PORT_D), 4393 phy_name(phy)); 4394 } else if (DISPLAY_VER(dev_priv) >= 12) { 4395 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4396 4397 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4398 DRM_MODE_ENCODER_TMDS, 4399 "DDI %s%c/PHY %s%c", 4400 port >= PORT_TC1 ? "TC" : "", 4401 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 4402 tc_port != TC_PORT_NONE ? "TC" : "", 4403 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4404 } else if (DISPLAY_VER(dev_priv) >= 11) { 4405 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4406 4407 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4408 DRM_MODE_ENCODER_TMDS, 4409 "DDI %c%s/PHY %s%c", 4410 port_name(port), 4411 port >= PORT_C ? " (TC)" : "", 4412 tc_port != TC_PORT_NONE ? "TC" : "", 4413 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4414 } else { 4415 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4416 DRM_MODE_ENCODER_TMDS, 4417 "DDI %c/PHY %c", port_name(port), phy_name(phy)); 4418 } 4419 4420 mutex_init(&dig_port->hdcp_mutex); 4421 dig_port->num_hdcp_streams = 0; 4422 4423 encoder->hotplug = intel_ddi_hotplug; 4424 encoder->compute_output_type = intel_ddi_compute_output_type; 4425 encoder->compute_config = intel_ddi_compute_config; 4426 encoder->compute_config_late = intel_ddi_compute_config_late; 4427 encoder->enable = intel_enable_ddi; 4428 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 4429 encoder->pre_enable = intel_ddi_pre_enable; 4430 encoder->disable = intel_disable_ddi; 4431 encoder->post_disable = intel_ddi_post_disable; 4432 encoder->update_pipe = intel_ddi_update_pipe; 4433 encoder->get_hw_state = intel_ddi_get_hw_state; 4434 encoder->sync_state = intel_ddi_sync_state; 4435 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 4436 encoder->suspend = intel_ddi_encoder_suspend; 4437 encoder->shutdown = intel_ddi_encoder_shutdown; 4438 encoder->get_power_domains = intel_ddi_get_power_domains; 4439 4440 encoder->type = INTEL_OUTPUT_DDI; 4441 encoder->power_domain = intel_port_to_power_domain(port); 4442 encoder->port = port; 4443 encoder->cloneable = 0; 4444 encoder->pipe_mask = ~0; 4445 4446 if (IS_DG2(dev_priv)) { 4447 encoder->enable_clock = intel_mpllb_enable; 4448 encoder->disable_clock = intel_mpllb_disable; 4449 encoder->get_config = dg2_ddi_get_config; 4450 } else if (IS_ALDERLAKE_S(dev_priv)) { 4451 encoder->enable_clock = adls_ddi_enable_clock; 4452 encoder->disable_clock = adls_ddi_disable_clock; 4453 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 4454 encoder->get_config = adls_ddi_get_config; 4455 } else if (IS_ROCKETLAKE(dev_priv)) { 4456 encoder->enable_clock = rkl_ddi_enable_clock; 4457 encoder->disable_clock = rkl_ddi_disable_clock; 4458 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 4459 encoder->get_config = rkl_ddi_get_config; 4460 } else if (IS_DG1(dev_priv)) { 4461 encoder->enable_clock = dg1_ddi_enable_clock; 4462 encoder->disable_clock = dg1_ddi_disable_clock; 4463 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 4464 encoder->get_config = dg1_ddi_get_config; 4465 } else if (IS_JSL_EHL(dev_priv)) { 4466 if (intel_ddi_is_tc(dev_priv, port)) { 4467 encoder->enable_clock = jsl_ddi_tc_enable_clock; 4468 encoder->disable_clock = jsl_ddi_tc_disable_clock; 4469 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 4470 encoder->get_config = icl_ddi_combo_get_config; 4471 } else { 4472 encoder->enable_clock = icl_ddi_combo_enable_clock; 4473 encoder->disable_clock = icl_ddi_combo_disable_clock; 4474 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 4475 encoder->get_config = icl_ddi_combo_get_config; 4476 } 4477 } else if (DISPLAY_VER(dev_priv) >= 11) { 4478 if (intel_ddi_is_tc(dev_priv, port)) { 4479 encoder->enable_clock = icl_ddi_tc_enable_clock; 4480 encoder->disable_clock = icl_ddi_tc_disable_clock; 4481 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 4482 encoder->get_config = icl_ddi_tc_get_config; 4483 } else { 4484 encoder->enable_clock = icl_ddi_combo_enable_clock; 4485 encoder->disable_clock = icl_ddi_combo_disable_clock; 4486 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 4487 encoder->get_config = icl_ddi_combo_get_config; 4488 } 4489 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 4490 /* BXT/GLK have fixed PLL->port mapping */ 4491 encoder->get_config = bxt_ddi_get_config; 4492 } else if (DISPLAY_VER(dev_priv) == 9) { 4493 encoder->enable_clock = skl_ddi_enable_clock; 4494 encoder->disable_clock = skl_ddi_disable_clock; 4495 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 4496 encoder->get_config = skl_ddi_get_config; 4497 } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 4498 encoder->enable_clock = hsw_ddi_enable_clock; 4499 encoder->disable_clock = hsw_ddi_disable_clock; 4500 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 4501 encoder->get_config = hsw_ddi_get_config; 4502 } 4503 4504 if (IS_DG2(dev_priv)) { 4505 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 4506 } else if (DISPLAY_VER(dev_priv) >= 12) { 4507 if (intel_phy_is_combo(dev_priv, phy)) 4508 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 4509 else 4510 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 4511 } else if (DISPLAY_VER(dev_priv) >= 11) { 4512 if (intel_phy_is_combo(dev_priv, phy)) 4513 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 4514 else 4515 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 4516 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 4517 encoder->set_signal_levels = bxt_ddi_phy_set_signal_levels; 4518 } else { 4519 encoder->set_signal_levels = hsw_set_signal_levels; 4520 } 4521 4522 intel_ddi_buf_trans_init(encoder); 4523 4524 if (DISPLAY_VER(dev_priv) >= 13) 4525 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port); 4526 else if (IS_DG1(dev_priv)) 4527 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); 4528 else if (IS_ROCKETLAKE(dev_priv)) 4529 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); 4530 else if (DISPLAY_VER(dev_priv) >= 12) 4531 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); 4532 else if (IS_JSL_EHL(dev_priv)) 4533 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); 4534 else if (DISPLAY_VER(dev_priv) == 11) 4535 encoder->hpd_pin = icl_hpd_pin(dev_priv, port); 4536 else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 4537 encoder->hpd_pin = skl_hpd_pin(dev_priv, port); 4538 else 4539 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 4540 4541 if (DISPLAY_VER(dev_priv) >= 11) 4542 dig_port->saved_port_bits = 4543 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 4544 & DDI_BUF_PORT_REVERSAL; 4545 else 4546 dig_port->saved_port_bits = 4547 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 4548 & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 4549 4550 if (intel_bios_is_lane_reversal_needed(dev_priv, port)) 4551 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL; 4552 4553 dig_port->dp.output_reg = INVALID_MMIO_REG; 4554 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 4555 dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 4556 4557 if (intel_phy_is_tc(dev_priv, phy)) { 4558 bool is_legacy = 4559 !intel_bios_encoder_supports_typec_usb(devdata) && 4560 !intel_bios_encoder_supports_tbt(devdata); 4561 4562 intel_tc_port_init(dig_port, is_legacy); 4563 4564 encoder->update_prepare = intel_ddi_update_prepare; 4565 encoder->update_complete = intel_ddi_update_complete; 4566 } 4567 4568 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 4569 dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO + 4570 port - PORT_A; 4571 4572 if (init_dp) { 4573 if (!intel_ddi_init_dp_connector(dig_port)) 4574 goto err; 4575 4576 dig_port->hpd_pulse = intel_dp_hpd_pulse; 4577 4578 if (dig_port->dp.mso_link_count) 4579 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv); 4580 } 4581 4582 /* In theory we don't need the encoder->type check, but leave it just in 4583 * case we have some really bad VBTs... */ 4584 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 4585 if (!intel_ddi_init_hdmi_connector(dig_port)) 4586 goto err; 4587 } 4588 4589 if (DISPLAY_VER(dev_priv) >= 11) { 4590 if (intel_phy_is_tc(dev_priv, phy)) 4591 dig_port->connected = intel_tc_port_connected; 4592 else 4593 dig_port->connected = lpt_digital_port_connected; 4594 } else if (DISPLAY_VER(dev_priv) >= 8) { 4595 if (port == PORT_A || IS_GEMINILAKE(dev_priv) || 4596 IS_BROXTON(dev_priv)) 4597 dig_port->connected = bdw_digital_port_connected; 4598 else 4599 dig_port->connected = lpt_digital_port_connected; 4600 } else { 4601 if (port == PORT_A) 4602 dig_port->connected = hsw_digital_port_connected; 4603 else 4604 dig_port->connected = lpt_digital_port_connected; 4605 } 4606 4607 intel_infoframe_init(dig_port); 4608 4609 return; 4610 4611 err: 4612 drm_encoder_cleanup(&encoder->base); 4613 kfree(dig_port); 4614 } 4615