1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <linux/string_helpers.h> 29 30 #include <drm/display/drm_scdc_helper.h> 31 #include <drm/drm_privacy_screen_consumer.h> 32 33 #include "i915_drv.h" 34 #include "i915_reg.h" 35 #include "intel_audio.h" 36 #include "intel_audio_regs.h" 37 #include "intel_backlight.h" 38 #include "intel_combo_phy.h" 39 #include "intel_combo_phy_regs.h" 40 #include "intel_connector.h" 41 #include "intel_crtc.h" 42 #include "intel_ddi.h" 43 #include "intel_ddi_buf_trans.h" 44 #include "intel_de.h" 45 #include "intel_display_power.h" 46 #include "intel_display_types.h" 47 #include "intel_dkl_phy.h" 48 #include "intel_dkl_phy_regs.h" 49 #include "intel_dp.h" 50 #include "intel_dp_aux.h" 51 #include "intel_dp_link_training.h" 52 #include "intel_dp_mst.h" 53 #include "intel_dpio_phy.h" 54 #include "intel_dsi.h" 55 #include "intel_fdi.h" 56 #include "intel_fifo_underrun.h" 57 #include "intel_gmbus.h" 58 #include "intel_hdcp.h" 59 #include "intel_hdmi.h" 60 #include "intel_hotplug.h" 61 #include "intel_hti.h" 62 #include "intel_lspcon.h" 63 #include "intel_mg_phy_regs.h" 64 #include "intel_pps.h" 65 #include "intel_psr.h" 66 #include "intel_quirks.h" 67 #include "intel_snps_phy.h" 68 #include "intel_tc.h" 69 #include "intel_vdsc.h" 70 #include "intel_vdsc_regs.h" 71 #include "intel_vrr.h" 72 #include "skl_scaler.h" 73 #include "skl_universal_plane.h" 74 75 static const u8 index_to_dp_signal_levels[] = { 76 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 77 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 78 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 79 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 80 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 81 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 82 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 83 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 84 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 85 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 86 }; 87 88 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 89 const struct intel_ddi_buf_trans *trans) 90 { 91 int level; 92 93 level = intel_bios_hdmi_level_shift(encoder->devdata); 94 if (level < 0) 95 level = trans->hdmi_default_entry; 96 97 return level; 98 } 99 100 static bool has_buf_trans_select(struct drm_i915_private *i915) 101 { 102 return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915); 103 } 104 105 static bool has_iboost(struct drm_i915_private *i915) 106 { 107 return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915); 108 } 109 110 /* 111 * Starting with Haswell, DDI port buffers must be programmed with correct 112 * values in advance. This function programs the correct values for 113 * DP/eDP/FDI use cases. 114 */ 115 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 116 const struct intel_crtc_state *crtc_state) 117 { 118 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 119 u32 iboost_bit = 0; 120 int i, n_entries; 121 enum port port = encoder->port; 122 const struct intel_ddi_buf_trans *trans; 123 124 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 125 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 126 return; 127 128 /* If we're boosting the current, set bit 31 of trans1 */ 129 if (has_iboost(dev_priv) && 130 intel_bios_dp_boost_level(encoder->devdata)) 131 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 132 133 for (i = 0; i < n_entries; i++) { 134 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 135 trans->entries[i].hsw.trans1 | iboost_bit); 136 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 137 trans->entries[i].hsw.trans2); 138 } 139 } 140 141 /* 142 * Starting with Haswell, DDI port buffers must be programmed with correct 143 * values in advance. This function programs the correct values for 144 * HDMI/DVI use cases. 145 */ 146 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 147 const struct intel_crtc_state *crtc_state) 148 { 149 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 150 int level = intel_ddi_level(encoder, crtc_state, 0); 151 u32 iboost_bit = 0; 152 int n_entries; 153 enum port port = encoder->port; 154 const struct intel_ddi_buf_trans *trans; 155 156 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 157 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 158 return; 159 160 /* If we're boosting the current, set bit 31 of trans1 */ 161 if (has_iboost(dev_priv) && 162 intel_bios_hdmi_boost_level(encoder->devdata)) 163 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 164 165 /* Entry 9 is for HDMI: */ 166 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 167 trans->entries[level].hsw.trans1 | iboost_bit); 168 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 169 trans->entries[level].hsw.trans2); 170 } 171 172 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 173 enum port port) 174 { 175 if (IS_BROXTON(dev_priv)) { 176 udelay(16); 177 return; 178 } 179 180 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 181 DDI_BUF_IS_IDLE), 8)) 182 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", 183 port_name(port)); 184 } 185 186 static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, 187 enum port port) 188 { 189 enum phy phy = intel_port_to_phy(dev_priv, port); 190 int timeout_us; 191 int ret; 192 193 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ 194 if (DISPLAY_VER(dev_priv) < 10) { 195 usleep_range(518, 1000); 196 return; 197 } 198 199 if (IS_DG2(dev_priv)) { 200 timeout_us = 1200; 201 } else if (DISPLAY_VER(dev_priv) >= 12) { 202 if (intel_phy_is_tc(dev_priv, phy)) 203 timeout_us = 3000; 204 else 205 timeout_us = 1000; 206 } else { 207 timeout_us = 500; 208 } 209 210 ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 211 DDI_BUF_IS_IDLE), timeout_us, 10, 10); 212 213 if (ret) 214 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", 215 port_name(port)); 216 } 217 218 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 219 { 220 switch (pll->info->id) { 221 case DPLL_ID_WRPLL1: 222 return PORT_CLK_SEL_WRPLL1; 223 case DPLL_ID_WRPLL2: 224 return PORT_CLK_SEL_WRPLL2; 225 case DPLL_ID_SPLL: 226 return PORT_CLK_SEL_SPLL; 227 case DPLL_ID_LCPLL_810: 228 return PORT_CLK_SEL_LCPLL_810; 229 case DPLL_ID_LCPLL_1350: 230 return PORT_CLK_SEL_LCPLL_1350; 231 case DPLL_ID_LCPLL_2700: 232 return PORT_CLK_SEL_LCPLL_2700; 233 default: 234 MISSING_CASE(pll->info->id); 235 return PORT_CLK_SEL_NONE; 236 } 237 } 238 239 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 240 const struct intel_crtc_state *crtc_state) 241 { 242 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 243 int clock = crtc_state->port_clock; 244 const enum intel_dpll_id id = pll->info->id; 245 246 switch (id) { 247 default: 248 /* 249 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 250 * here, so do warn if this get passed in 251 */ 252 MISSING_CASE(id); 253 return DDI_CLK_SEL_NONE; 254 case DPLL_ID_ICL_TBTPLL: 255 switch (clock) { 256 case 162000: 257 return DDI_CLK_SEL_TBT_162; 258 case 270000: 259 return DDI_CLK_SEL_TBT_270; 260 case 540000: 261 return DDI_CLK_SEL_TBT_540; 262 case 810000: 263 return DDI_CLK_SEL_TBT_810; 264 default: 265 MISSING_CASE(clock); 266 return DDI_CLK_SEL_NONE; 267 } 268 case DPLL_ID_ICL_MGPLL1: 269 case DPLL_ID_ICL_MGPLL2: 270 case DPLL_ID_ICL_MGPLL3: 271 case DPLL_ID_ICL_MGPLL4: 272 case DPLL_ID_TGL_MGPLL5: 273 case DPLL_ID_TGL_MGPLL6: 274 return DDI_CLK_SEL_MG; 275 } 276 } 277 278 static u32 ddi_buf_phy_link_rate(int port_clock) 279 { 280 switch (port_clock) { 281 case 162000: 282 return DDI_BUF_PHY_LINK_RATE(0); 283 case 216000: 284 return DDI_BUF_PHY_LINK_RATE(4); 285 case 243000: 286 return DDI_BUF_PHY_LINK_RATE(5); 287 case 270000: 288 return DDI_BUF_PHY_LINK_RATE(1); 289 case 324000: 290 return DDI_BUF_PHY_LINK_RATE(6); 291 case 432000: 292 return DDI_BUF_PHY_LINK_RATE(7); 293 case 540000: 294 return DDI_BUF_PHY_LINK_RATE(2); 295 case 810000: 296 return DDI_BUF_PHY_LINK_RATE(3); 297 default: 298 MISSING_CASE(port_clock); 299 return DDI_BUF_PHY_LINK_RATE(0); 300 } 301 } 302 303 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 304 const struct intel_crtc_state *crtc_state) 305 { 306 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 307 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 308 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 309 enum phy phy = intel_port_to_phy(i915, encoder->port); 310 311 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 312 intel_dp->DP = dig_port->saved_port_bits | 313 DDI_PORT_WIDTH(crtc_state->lane_count) | 314 DDI_BUF_TRANS_SELECT(0); 315 316 if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) { 317 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 318 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 319 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 320 } 321 } 322 323 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 324 enum port port) 325 { 326 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 327 328 switch (val) { 329 case DDI_CLK_SEL_NONE: 330 return 0; 331 case DDI_CLK_SEL_TBT_162: 332 return 162000; 333 case DDI_CLK_SEL_TBT_270: 334 return 270000; 335 case DDI_CLK_SEL_TBT_540: 336 return 540000; 337 case DDI_CLK_SEL_TBT_810: 338 return 810000; 339 default: 340 MISSING_CASE(val); 341 return 0; 342 } 343 } 344 345 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 346 { 347 /* CRT dotclock is determined via other means */ 348 if (pipe_config->has_pch_encoder) 349 return; 350 351 pipe_config->hw.adjusted_mode.crtc_clock = 352 intel_crtc_dotclock(pipe_config); 353 } 354 355 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 356 const struct drm_connector_state *conn_state) 357 { 358 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 359 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 360 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 361 u32 temp; 362 363 if (!intel_crtc_has_dp_encoder(crtc_state)) 364 return; 365 366 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 367 368 temp = DP_MSA_MISC_SYNC_CLOCK; 369 370 switch (crtc_state->pipe_bpp) { 371 case 18: 372 temp |= DP_MSA_MISC_6_BPC; 373 break; 374 case 24: 375 temp |= DP_MSA_MISC_8_BPC; 376 break; 377 case 30: 378 temp |= DP_MSA_MISC_10_BPC; 379 break; 380 case 36: 381 temp |= DP_MSA_MISC_12_BPC; 382 break; 383 default: 384 MISSING_CASE(crtc_state->pipe_bpp); 385 break; 386 } 387 388 /* nonsense combination */ 389 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 390 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 391 392 if (crtc_state->limited_color_range) 393 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 394 395 /* 396 * As per DP 1.2 spec section 2.3.4.3 while sending 397 * YCBCR 444 signals we should program MSA MISC1/0 fields with 398 * colorspace information. 399 */ 400 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 401 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 402 403 /* 404 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 405 * of Color Encoding Format and Content Color Gamut] while sending 406 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 407 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 408 */ 409 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 410 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 411 412 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp); 413 } 414 415 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 416 { 417 if (master_transcoder == TRANSCODER_EDP) 418 return 0; 419 else 420 return master_transcoder + 1; 421 } 422 423 static void 424 intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder, 425 const struct intel_crtc_state *crtc_state) 426 { 427 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 428 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 429 u32 val = 0; 430 431 if (intel_dp_is_uhbr(crtc_state)) 432 val = TRANS_DP2_128B132B_CHANNEL_CODING; 433 434 intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val); 435 } 436 437 /* 438 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 439 * 440 * Only intended to be used by intel_ddi_enable_transcoder_func() and 441 * intel_ddi_config_transcoder_func(). 442 */ 443 static u32 444 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 445 const struct intel_crtc_state *crtc_state) 446 { 447 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 448 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 449 enum pipe pipe = crtc->pipe; 450 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 451 enum port port = encoder->port; 452 u32 temp; 453 454 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 455 temp = TRANS_DDI_FUNC_ENABLE; 456 if (DISPLAY_VER(dev_priv) >= 12) 457 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 458 else 459 temp |= TRANS_DDI_SELECT_PORT(port); 460 461 switch (crtc_state->pipe_bpp) { 462 default: 463 MISSING_CASE(crtc_state->pipe_bpp); 464 fallthrough; 465 case 18: 466 temp |= TRANS_DDI_BPC_6; 467 break; 468 case 24: 469 temp |= TRANS_DDI_BPC_8; 470 break; 471 case 30: 472 temp |= TRANS_DDI_BPC_10; 473 break; 474 case 36: 475 temp |= TRANS_DDI_BPC_12; 476 break; 477 } 478 479 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 480 temp |= TRANS_DDI_PVSYNC; 481 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 482 temp |= TRANS_DDI_PHSYNC; 483 484 if (cpu_transcoder == TRANSCODER_EDP) { 485 switch (pipe) { 486 default: 487 MISSING_CASE(pipe); 488 fallthrough; 489 case PIPE_A: 490 /* On Haswell, can only use the always-on power well for 491 * eDP when not using the panel fitter, and when not 492 * using motion blur mitigation (which we don't 493 * support). */ 494 if (crtc_state->pch_pfit.force_thru) 495 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 496 else 497 temp |= TRANS_DDI_EDP_INPUT_A_ON; 498 break; 499 case PIPE_B: 500 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 501 break; 502 case PIPE_C: 503 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 504 break; 505 } 506 } 507 508 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 509 if (crtc_state->has_hdmi_sink) 510 temp |= TRANS_DDI_MODE_SELECT_HDMI; 511 else 512 temp |= TRANS_DDI_MODE_SELECT_DVI; 513 514 if (crtc_state->hdmi_scrambling) 515 temp |= TRANS_DDI_HDMI_SCRAMBLING; 516 if (crtc_state->hdmi_high_tmds_clock_ratio) 517 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 518 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 519 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 520 temp |= (crtc_state->fdi_lanes - 1) << 1; 521 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 522 if (intel_dp_is_uhbr(crtc_state)) 523 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 524 else 525 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 526 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 527 528 if (DISPLAY_VER(dev_priv) >= 12) { 529 enum transcoder master; 530 531 master = crtc_state->mst_master_transcoder; 532 drm_WARN_ON(&dev_priv->drm, 533 master == INVALID_TRANSCODER); 534 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 535 } 536 } else { 537 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 538 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 539 } 540 541 if (IS_DISPLAY_VER(dev_priv, 8, 10) && 542 crtc_state->master_transcoder != INVALID_TRANSCODER) { 543 u8 master_select = 544 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 545 546 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 547 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 548 } 549 550 return temp; 551 } 552 553 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 554 const struct intel_crtc_state *crtc_state) 555 { 556 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 557 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 558 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 559 560 if (DISPLAY_VER(dev_priv) >= 11) { 561 enum transcoder master_transcoder = crtc_state->master_transcoder; 562 u32 ctl2 = 0; 563 564 if (master_transcoder != INVALID_TRANSCODER) { 565 u8 master_select = 566 bdw_trans_port_sync_master_select(master_transcoder); 567 568 ctl2 |= PORT_SYNC_MODE_ENABLE | 569 PORT_SYNC_MODE_MASTER_SELECT(master_select); 570 } 571 572 intel_de_write(dev_priv, 573 TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2); 574 } 575 576 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 577 intel_ddi_transcoder_func_reg_val_get(encoder, 578 crtc_state)); 579 } 580 581 /* 582 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 583 * bit. 584 */ 585 static void 586 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 587 const struct intel_crtc_state *crtc_state) 588 { 589 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 590 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 591 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 592 u32 ctl; 593 594 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 595 ctl &= ~TRANS_DDI_FUNC_ENABLE; 596 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 597 } 598 599 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 600 { 601 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 602 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 603 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 604 u32 ctl; 605 606 if (DISPLAY_VER(dev_priv) >= 11) 607 intel_de_write(dev_priv, 608 TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0); 609 610 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 611 612 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 613 614 ctl &= ~TRANS_DDI_FUNC_ENABLE; 615 616 if (IS_DISPLAY_VER(dev_priv, 8, 10)) 617 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 618 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 619 620 if (DISPLAY_VER(dev_priv) >= 12) { 621 if (!intel_dp_mst_is_master_trans(crtc_state)) { 622 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 623 TRANS_DDI_MODE_SELECT_MASK); 624 } 625 } else { 626 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 627 } 628 629 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 630 631 if (intel_has_quirk(dev_priv, QUIRK_INCREASE_DDI_DISABLED_TIME) && 632 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 633 drm_dbg_kms(&dev_priv->drm, 634 "Quirk Increase DDI disabled time\n"); 635 /* Quirk time at 100ms for reliable operation */ 636 msleep(100); 637 } 638 } 639 640 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 641 enum transcoder cpu_transcoder, 642 bool enable, u32 hdcp_mask) 643 { 644 struct drm_device *dev = intel_encoder->base.dev; 645 struct drm_i915_private *dev_priv = to_i915(dev); 646 intel_wakeref_t wakeref; 647 int ret = 0; 648 649 wakeref = intel_display_power_get_if_enabled(dev_priv, 650 intel_encoder->power_domain); 651 if (drm_WARN_ON(dev, !wakeref)) 652 return -ENXIO; 653 654 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 655 hdcp_mask, enable ? hdcp_mask : 0); 656 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 657 return ret; 658 } 659 660 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 661 { 662 struct drm_device *dev = intel_connector->base.dev; 663 struct drm_i915_private *dev_priv = to_i915(dev); 664 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 665 int type = intel_connector->base.connector_type; 666 enum port port = encoder->port; 667 enum transcoder cpu_transcoder; 668 intel_wakeref_t wakeref; 669 enum pipe pipe = 0; 670 u32 tmp; 671 bool ret; 672 673 wakeref = intel_display_power_get_if_enabled(dev_priv, 674 encoder->power_domain); 675 if (!wakeref) 676 return false; 677 678 if (!encoder->get_hw_state(encoder, &pipe)) { 679 ret = false; 680 goto out; 681 } 682 683 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 684 cpu_transcoder = TRANSCODER_EDP; 685 else 686 cpu_transcoder = (enum transcoder) pipe; 687 688 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 689 690 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 691 case TRANS_DDI_MODE_SELECT_HDMI: 692 case TRANS_DDI_MODE_SELECT_DVI: 693 ret = type == DRM_MODE_CONNECTOR_HDMIA; 694 break; 695 696 case TRANS_DDI_MODE_SELECT_DP_SST: 697 ret = type == DRM_MODE_CONNECTOR_eDP || 698 type == DRM_MODE_CONNECTOR_DisplayPort; 699 break; 700 701 case TRANS_DDI_MODE_SELECT_DP_MST: 702 /* if the transcoder is in MST state then 703 * connector isn't connected */ 704 ret = false; 705 break; 706 707 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 708 if (HAS_DP20(dev_priv)) 709 /* 128b/132b */ 710 ret = false; 711 else 712 /* FDI */ 713 ret = type == DRM_MODE_CONNECTOR_VGA; 714 break; 715 716 default: 717 ret = false; 718 break; 719 } 720 721 out: 722 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 723 724 return ret; 725 } 726 727 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 728 u8 *pipe_mask, bool *is_dp_mst) 729 { 730 struct drm_device *dev = encoder->base.dev; 731 struct drm_i915_private *dev_priv = to_i915(dev); 732 enum port port = encoder->port; 733 intel_wakeref_t wakeref; 734 enum pipe p; 735 u32 tmp; 736 u8 mst_pipe_mask; 737 738 *pipe_mask = 0; 739 *is_dp_mst = false; 740 741 wakeref = intel_display_power_get_if_enabled(dev_priv, 742 encoder->power_domain); 743 if (!wakeref) 744 return; 745 746 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 747 if (!(tmp & DDI_BUF_CTL_ENABLE)) 748 goto out; 749 750 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { 751 tmp = intel_de_read(dev_priv, 752 TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 753 754 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 755 default: 756 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 757 fallthrough; 758 case TRANS_DDI_EDP_INPUT_A_ON: 759 case TRANS_DDI_EDP_INPUT_A_ONOFF: 760 *pipe_mask = BIT(PIPE_A); 761 break; 762 case TRANS_DDI_EDP_INPUT_B_ONOFF: 763 *pipe_mask = BIT(PIPE_B); 764 break; 765 case TRANS_DDI_EDP_INPUT_C_ONOFF: 766 *pipe_mask = BIT(PIPE_C); 767 break; 768 } 769 770 goto out; 771 } 772 773 mst_pipe_mask = 0; 774 for_each_pipe(dev_priv, p) { 775 enum transcoder cpu_transcoder = (enum transcoder)p; 776 unsigned int port_mask, ddi_select; 777 intel_wakeref_t trans_wakeref; 778 779 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 780 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 781 if (!trans_wakeref) 782 continue; 783 784 if (DISPLAY_VER(dev_priv) >= 12) { 785 port_mask = TGL_TRANS_DDI_PORT_MASK; 786 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 787 } else { 788 port_mask = TRANS_DDI_PORT_MASK; 789 ddi_select = TRANS_DDI_SELECT_PORT(port); 790 } 791 792 tmp = intel_de_read(dev_priv, 793 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 794 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 795 trans_wakeref); 796 797 if ((tmp & port_mask) != ddi_select) 798 continue; 799 800 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST || 801 (HAS_DP20(dev_priv) && 802 (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B)) 803 mst_pipe_mask |= BIT(p); 804 805 *pipe_mask |= BIT(p); 806 } 807 808 if (!*pipe_mask) 809 drm_dbg_kms(&dev_priv->drm, 810 "No pipe for [ENCODER:%d:%s] found\n", 811 encoder->base.base.id, encoder->base.name); 812 813 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 814 drm_dbg_kms(&dev_priv->drm, 815 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 816 encoder->base.base.id, encoder->base.name, 817 *pipe_mask); 818 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 819 } 820 821 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 822 drm_dbg_kms(&dev_priv->drm, 823 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", 824 encoder->base.base.id, encoder->base.name, 825 *pipe_mask, mst_pipe_mask); 826 else 827 *is_dp_mst = mst_pipe_mask; 828 829 out: 830 if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) { 831 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 832 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 833 BXT_PHY_LANE_POWERDOWN_ACK | 834 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 835 drm_err(&dev_priv->drm, 836 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 837 encoder->base.base.id, encoder->base.name, tmp); 838 } 839 840 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 841 } 842 843 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 844 enum pipe *pipe) 845 { 846 u8 pipe_mask; 847 bool is_mst; 848 849 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 850 851 if (is_mst || !pipe_mask) 852 return false; 853 854 *pipe = ffs(pipe_mask) - 1; 855 856 return true; 857 } 858 859 static enum intel_display_power_domain 860 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port, 861 const struct intel_crtc_state *crtc_state) 862 { 863 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 864 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 865 866 /* 867 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 868 * DC states enabled at the same time, while for driver initiated AUX 869 * transfers we need the same AUX IOs to be powered but with DC states 870 * disabled. Accordingly use the AUX_IO_<port> power domain here which 871 * leaves DC states enabled. 872 * 873 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require 874 * AUX IO to be enabled, but all these require DC_OFF to be enabled as 875 * well, so we can acquire a wider AUX_<port> power domain reference 876 * instead of a specific AUX_IO_<port> reference without powering up any 877 * extra wells. 878 */ 879 if (intel_encoder_can_psr(&dig_port->base)) 880 return intel_display_power_aux_io_domain(i915, dig_port->aux_ch); 881 else if (DISPLAY_VER(i915) < 14 && 882 (intel_crtc_has_dp_encoder(crtc_state) || 883 intel_phy_is_tc(i915, phy))) 884 return intel_aux_power_domain(dig_port); 885 else 886 return POWER_DOMAIN_INVALID; 887 } 888 889 static void 890 main_link_aux_power_domain_get(struct intel_digital_port *dig_port, 891 const struct intel_crtc_state *crtc_state) 892 { 893 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 894 enum intel_display_power_domain domain = 895 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 896 897 drm_WARN_ON(&i915->drm, dig_port->aux_wakeref); 898 899 if (domain == POWER_DOMAIN_INVALID) 900 return; 901 902 dig_port->aux_wakeref = intel_display_power_get(i915, domain); 903 } 904 905 static void 906 main_link_aux_power_domain_put(struct intel_digital_port *dig_port, 907 const struct intel_crtc_state *crtc_state) 908 { 909 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 910 enum intel_display_power_domain domain = 911 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 912 intel_wakeref_t wf; 913 914 wf = fetch_and_zero(&dig_port->aux_wakeref); 915 if (!wf) 916 return; 917 918 intel_display_power_put(i915, domain, wf); 919 } 920 921 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 922 struct intel_crtc_state *crtc_state) 923 { 924 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 925 struct intel_digital_port *dig_port; 926 927 /* 928 * TODO: Add support for MST encoders. Atm, the following should never 929 * happen since fake-MST encoders don't set their get_power_domains() 930 * hook. 931 */ 932 if (drm_WARN_ON(&dev_priv->drm, 933 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 934 return; 935 936 dig_port = enc_to_dig_port(encoder); 937 938 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 939 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 940 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 941 dig_port->ddi_io_power_domain); 942 } 943 944 main_link_aux_power_domain_get(dig_port, crtc_state); 945 } 946 947 void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder, 948 const struct intel_crtc_state *crtc_state) 949 { 950 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 951 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 952 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 953 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 954 u32 val; 955 956 if (cpu_transcoder == TRANSCODER_EDP) 957 return; 958 959 if (DISPLAY_VER(dev_priv) >= 13) 960 val = TGL_TRANS_CLK_SEL_PORT(phy); 961 else if (DISPLAY_VER(dev_priv) >= 12) 962 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 963 else 964 val = TRANS_CLK_SEL_PORT(encoder->port); 965 966 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 967 } 968 969 void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state) 970 { 971 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 972 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 973 u32 val; 974 975 if (cpu_transcoder == TRANSCODER_EDP) 976 return; 977 978 if (DISPLAY_VER(dev_priv) >= 12) 979 val = TGL_TRANS_CLK_SEL_DISABLED; 980 else 981 val = TRANS_CLK_SEL_DISABLED; 982 983 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 984 } 985 986 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 987 enum port port, u8 iboost) 988 { 989 u32 tmp; 990 991 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 992 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 993 if (iboost) 994 tmp |= iboost << BALANCE_LEG_SHIFT(port); 995 else 996 tmp |= BALANCE_LEG_DISABLE(port); 997 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 998 } 999 1000 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 1001 const struct intel_crtc_state *crtc_state, 1002 int level) 1003 { 1004 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1005 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1006 u8 iboost; 1007 1008 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1009 iboost = intel_bios_hdmi_boost_level(encoder->devdata); 1010 else 1011 iboost = intel_bios_dp_boost_level(encoder->devdata); 1012 1013 if (iboost == 0) { 1014 const struct intel_ddi_buf_trans *trans; 1015 int n_entries; 1016 1017 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1018 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1019 return; 1020 1021 iboost = trans->entries[level].hsw.i_boost; 1022 } 1023 1024 /* Make sure that the requested I_boost is valid */ 1025 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 1026 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); 1027 return; 1028 } 1029 1030 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); 1031 1032 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 1033 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 1034 } 1035 1036 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1037 const struct intel_crtc_state *crtc_state) 1038 { 1039 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1040 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1041 int n_entries; 1042 1043 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1044 1045 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 1046 n_entries = 1; 1047 if (drm_WARN_ON(&dev_priv->drm, 1048 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1049 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1050 1051 return index_to_dp_signal_levels[n_entries - 1] & 1052 DP_TRAIN_VOLTAGE_SWING_MASK; 1053 } 1054 1055 /* 1056 * We assume that the full set of pre-emphasis values can be 1057 * used on all DDI platforms. Should that change we need to 1058 * rethink this code. 1059 */ 1060 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1061 { 1062 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1063 } 1064 1065 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1066 int lane) 1067 { 1068 if (crtc_state->port_clock > 600000) 1069 return 0; 1070 1071 if (crtc_state->lane_count == 4) 1072 return lane >= 1 ? LOADGEN_SELECT : 0; 1073 else 1074 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1075 } 1076 1077 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1078 const struct intel_crtc_state *crtc_state) 1079 { 1080 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1081 const struct intel_ddi_buf_trans *trans; 1082 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1083 int n_entries, ln; 1084 u32 val; 1085 1086 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1087 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1088 return; 1089 1090 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1091 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1092 1093 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1094 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1095 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, 1096 intel_dp->hobl_active ? val : 0); 1097 } 1098 1099 /* Set PORT_TX_DW5 */ 1100 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1101 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1102 TAP2_DISABLE | TAP3_DISABLE); 1103 val |= SCALING_MODE_SEL(0x2); 1104 val |= RTERM_SELECT(0x6); 1105 val |= TAP3_DISABLE; 1106 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1107 1108 /* Program PORT_TX_DW2 */ 1109 for (ln = 0; ln < 4; ln++) { 1110 int level = intel_ddi_level(encoder, crtc_state, ln); 1111 1112 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy), 1113 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1114 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1115 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1116 RCOMP_SCALAR(0x98)); 1117 } 1118 1119 /* Program PORT_TX_DW4 */ 1120 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1121 for (ln = 0; ln < 4; ln++) { 1122 int level = intel_ddi_level(encoder, crtc_state, ln); 1123 1124 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1125 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1126 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1127 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1128 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1129 } 1130 1131 /* Program PORT_TX_DW7 */ 1132 for (ln = 0; ln < 4; ln++) { 1133 int level = intel_ddi_level(encoder, crtc_state, ln); 1134 1135 intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy), 1136 N_SCALAR_MASK, 1137 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1138 } 1139 } 1140 1141 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1142 const struct intel_crtc_state *crtc_state) 1143 { 1144 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1145 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1146 u32 val; 1147 int ln; 1148 1149 /* 1150 * 1. If port type is eDP or DP, 1151 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1152 * else clear to 0b. 1153 */ 1154 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); 1155 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1156 val &= ~COMMON_KEEPER_EN; 1157 else 1158 val |= COMMON_KEEPER_EN; 1159 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 1160 1161 /* 2. Program loadgen select */ 1162 /* 1163 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1164 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1165 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1166 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1167 */ 1168 for (ln = 0; ln < 4; ln++) { 1169 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1170 LOADGEN_SELECT, 1171 icl_combo_phy_loadgen_select(crtc_state, ln)); 1172 } 1173 1174 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1175 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 1176 0, SUS_CLOCK_CONFIG); 1177 1178 /* 4. Clear training enable to change swing values */ 1179 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1180 val &= ~TX_TRAINING_EN; 1181 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1182 1183 /* 5. Program swing and de-emphasis */ 1184 icl_ddi_combo_vswing_program(encoder, crtc_state); 1185 1186 /* 6. Set training enable to trigger update */ 1187 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1188 val |= TX_TRAINING_EN; 1189 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1190 } 1191 1192 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1193 const struct intel_crtc_state *crtc_state) 1194 { 1195 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1196 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 1197 const struct intel_ddi_buf_trans *trans; 1198 int n_entries, ln; 1199 1200 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1201 return; 1202 1203 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1204 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1205 return; 1206 1207 for (ln = 0; ln < 2; ln++) { 1208 intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), 1209 CRI_USE_FS32, 0); 1210 intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), 1211 CRI_USE_FS32, 0); 1212 } 1213 1214 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1215 for (ln = 0; ln < 2; ln++) { 1216 int level; 1217 1218 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1219 1220 intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), 1221 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1222 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1223 1224 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1225 1226 intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), 1227 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1228 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1229 } 1230 1231 /* Program MG_TX_DRVCTRL with values from vswing table */ 1232 for (ln = 0; ln < 2; ln++) { 1233 int level; 1234 1235 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1236 1237 intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), 1238 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1239 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1240 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1241 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1242 CRI_TXDEEMPH_OVERRIDE_EN); 1243 1244 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1245 1246 intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), 1247 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1248 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1249 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1250 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1251 CRI_TXDEEMPH_OVERRIDE_EN); 1252 1253 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1254 } 1255 1256 /* 1257 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1258 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1259 * values from table for which TX1 and TX2 enabled. 1260 */ 1261 for (ln = 0; ln < 2; ln++) { 1262 intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port), 1263 CFG_LOW_RATE_LKREN_EN, 1264 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1265 } 1266 1267 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1268 for (ln = 0; ln < 2; ln++) { 1269 intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port), 1270 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1271 CFG_AMI_CK_DIV_OVERRIDE_EN, 1272 crtc_state->port_clock > 500000 ? 1273 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1274 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1275 1276 intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port), 1277 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1278 CFG_AMI_CK_DIV_OVERRIDE_EN, 1279 crtc_state->port_clock > 500000 ? 1280 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1281 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1282 } 1283 1284 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1285 for (ln = 0; ln < 2; ln++) { 1286 intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 1287 0, CRI_CALCINIT); 1288 intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 1289 0, CRI_CALCINIT); 1290 } 1291 } 1292 1293 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1294 const struct intel_crtc_state *crtc_state) 1295 { 1296 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1297 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 1298 const struct intel_ddi_buf_trans *trans; 1299 int n_entries, ln; 1300 1301 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1302 return; 1303 1304 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1305 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1306 return; 1307 1308 for (ln = 0; ln < 2; ln++) { 1309 int level; 1310 1311 intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); 1312 1313 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1314 1315 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln), 1316 DKL_TX_PRESHOOT_COEFF_MASK | 1317 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1318 DKL_TX_VSWING_CONTROL_MASK, 1319 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1320 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1321 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1322 1323 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1324 1325 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln), 1326 DKL_TX_PRESHOOT_COEFF_MASK | 1327 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1328 DKL_TX_VSWING_CONTROL_MASK, 1329 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1330 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1331 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1332 1333 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1334 DKL_TX_DP20BITMODE, 0); 1335 1336 if (IS_ALDERLAKE_P(dev_priv)) { 1337 u32 val; 1338 1339 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1340 if (ln == 0) { 1341 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1342 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); 1343 } else { 1344 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); 1345 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); 1346 } 1347 } else { 1348 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1349 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); 1350 } 1351 1352 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1353 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | 1354 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, 1355 val); 1356 } 1357 } 1358 } 1359 1360 static int translate_signal_level(struct intel_dp *intel_dp, 1361 u8 signal_levels) 1362 { 1363 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1364 int i; 1365 1366 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1367 if (index_to_dp_signal_levels[i] == signal_levels) 1368 return i; 1369 } 1370 1371 drm_WARN(&i915->drm, 1, 1372 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1373 signal_levels); 1374 1375 return 0; 1376 } 1377 1378 static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1379 const struct intel_crtc_state *crtc_state, 1380 int lane) 1381 { 1382 u8 train_set = intel_dp->train_set[lane]; 1383 1384 if (intel_dp_is_uhbr(crtc_state)) { 1385 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1386 } else { 1387 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1388 DP_TRAIN_PRE_EMPHASIS_MASK); 1389 1390 return translate_signal_level(intel_dp, signal_levels); 1391 } 1392 } 1393 1394 int intel_ddi_level(struct intel_encoder *encoder, 1395 const struct intel_crtc_state *crtc_state, 1396 int lane) 1397 { 1398 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1399 const struct intel_ddi_buf_trans *trans; 1400 int level, n_entries; 1401 1402 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1403 if (drm_WARN_ON_ONCE(&i915->drm, !trans)) 1404 return 0; 1405 1406 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1407 level = intel_ddi_hdmi_level(encoder, trans); 1408 else 1409 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1410 lane); 1411 1412 if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries)) 1413 level = n_entries - 1; 1414 1415 return level; 1416 } 1417 1418 static void 1419 hsw_set_signal_levels(struct intel_encoder *encoder, 1420 const struct intel_crtc_state *crtc_state) 1421 { 1422 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1423 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1424 int level = intel_ddi_level(encoder, crtc_state, 0); 1425 enum port port = encoder->port; 1426 u32 signal_levels; 1427 1428 if (has_iboost(dev_priv)) 1429 skl_ddi_set_iboost(encoder, crtc_state, level); 1430 1431 /* HDMI ignores the rest */ 1432 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1433 return; 1434 1435 signal_levels = DDI_BUF_TRANS_SELECT(level); 1436 1437 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1438 signal_levels); 1439 1440 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1441 intel_dp->DP |= signal_levels; 1442 1443 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 1444 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 1445 } 1446 1447 static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1448 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1449 { 1450 mutex_lock(&i915->display.dpll.lock); 1451 1452 intel_de_rmw(i915, reg, clk_sel_mask, clk_sel); 1453 1454 /* 1455 * "This step and the step before must be 1456 * done with separate register writes." 1457 */ 1458 intel_de_rmw(i915, reg, clk_off, 0); 1459 1460 mutex_unlock(&i915->display.dpll.lock); 1461 } 1462 1463 static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1464 u32 clk_off) 1465 { 1466 mutex_lock(&i915->display.dpll.lock); 1467 1468 intel_de_rmw(i915, reg, 0, clk_off); 1469 1470 mutex_unlock(&i915->display.dpll.lock); 1471 } 1472 1473 static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg, 1474 u32 clk_off) 1475 { 1476 return !(intel_de_read(i915, reg) & clk_off); 1477 } 1478 1479 static struct intel_shared_dpll * 1480 _icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg, 1481 u32 clk_sel_mask, u32 clk_sel_shift) 1482 { 1483 enum intel_dpll_id id; 1484 1485 id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift; 1486 1487 return intel_get_shared_dpll_by_id(i915, id); 1488 } 1489 1490 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1491 const struct intel_crtc_state *crtc_state) 1492 { 1493 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1494 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1495 enum phy phy = intel_port_to_phy(i915, encoder->port); 1496 1497 if (drm_WARN_ON(&i915->drm, !pll)) 1498 return; 1499 1500 _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1501 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1502 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1503 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1504 } 1505 1506 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1507 { 1508 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1509 enum phy phy = intel_port_to_phy(i915, encoder->port); 1510 1511 _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1512 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1513 } 1514 1515 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1516 { 1517 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1518 enum phy phy = intel_port_to_phy(i915, encoder->port); 1519 1520 return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy), 1521 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1522 } 1523 1524 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1525 { 1526 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1527 enum phy phy = intel_port_to_phy(i915, encoder->port); 1528 1529 return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy), 1530 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1531 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1532 } 1533 1534 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1535 const struct intel_crtc_state *crtc_state) 1536 { 1537 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1538 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1539 enum phy phy = intel_port_to_phy(i915, encoder->port); 1540 1541 if (drm_WARN_ON(&i915->drm, !pll)) 1542 return; 1543 1544 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1545 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1546 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1547 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1548 } 1549 1550 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1551 { 1552 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1553 enum phy phy = intel_port_to_phy(i915, encoder->port); 1554 1555 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1556 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1557 } 1558 1559 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1560 { 1561 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1562 enum phy phy = intel_port_to_phy(i915, encoder->port); 1563 1564 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1565 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1566 } 1567 1568 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1569 { 1570 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1571 enum phy phy = intel_port_to_phy(i915, encoder->port); 1572 1573 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1574 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1575 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1576 } 1577 1578 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1579 const struct intel_crtc_state *crtc_state) 1580 { 1581 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1582 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1583 enum phy phy = intel_port_to_phy(i915, encoder->port); 1584 1585 if (drm_WARN_ON(&i915->drm, !pll)) 1586 return; 1587 1588 /* 1589 * If we fail this, something went very wrong: first 2 PLLs should be 1590 * used by first 2 phys and last 2 PLLs by last phys 1591 */ 1592 if (drm_WARN_ON(&i915->drm, 1593 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1594 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1595 return; 1596 1597 _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1598 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1599 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1600 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1601 } 1602 1603 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1604 { 1605 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1606 enum phy phy = intel_port_to_phy(i915, encoder->port); 1607 1608 _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1609 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1610 } 1611 1612 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1613 { 1614 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1615 enum phy phy = intel_port_to_phy(i915, encoder->port); 1616 1617 return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy), 1618 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1619 } 1620 1621 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1622 { 1623 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1624 enum phy phy = intel_port_to_phy(i915, encoder->port); 1625 enum intel_dpll_id id; 1626 u32 val; 1627 1628 val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy)); 1629 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1630 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1631 id = val; 1632 1633 /* 1634 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1635 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1636 * bit for phy C and D. 1637 */ 1638 if (phy >= PHY_C) 1639 id += DPLL_ID_DG1_DPLL2; 1640 1641 return intel_get_shared_dpll_by_id(i915, id); 1642 } 1643 1644 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1645 const struct intel_crtc_state *crtc_state) 1646 { 1647 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1648 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1649 enum phy phy = intel_port_to_phy(i915, encoder->port); 1650 1651 if (drm_WARN_ON(&i915->drm, !pll)) 1652 return; 1653 1654 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1655 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1656 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1657 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1658 } 1659 1660 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1661 { 1662 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1663 enum phy phy = intel_port_to_phy(i915, encoder->port); 1664 1665 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1666 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1667 } 1668 1669 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1670 { 1671 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1672 enum phy phy = intel_port_to_phy(i915, encoder->port); 1673 1674 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1675 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1676 } 1677 1678 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1679 { 1680 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1681 enum phy phy = intel_port_to_phy(i915, encoder->port); 1682 1683 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1684 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1685 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1686 } 1687 1688 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1689 const struct intel_crtc_state *crtc_state) 1690 { 1691 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1692 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1693 enum port port = encoder->port; 1694 1695 if (drm_WARN_ON(&i915->drm, !pll)) 1696 return; 1697 1698 /* 1699 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1700 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1701 */ 1702 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1703 1704 icl_ddi_combo_enable_clock(encoder, crtc_state); 1705 } 1706 1707 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1708 { 1709 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1710 enum port port = encoder->port; 1711 1712 icl_ddi_combo_disable_clock(encoder); 1713 1714 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1715 } 1716 1717 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1718 { 1719 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1720 enum port port = encoder->port; 1721 u32 tmp; 1722 1723 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1724 1725 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1726 return false; 1727 1728 return icl_ddi_combo_is_clock_enabled(encoder); 1729 } 1730 1731 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1732 const struct intel_crtc_state *crtc_state) 1733 { 1734 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1735 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1736 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1737 enum port port = encoder->port; 1738 1739 if (drm_WARN_ON(&i915->drm, !pll)) 1740 return; 1741 1742 intel_de_write(i915, DDI_CLK_SEL(port), 1743 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1744 1745 mutex_lock(&i915->display.dpll.lock); 1746 1747 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1748 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1749 1750 mutex_unlock(&i915->display.dpll.lock); 1751 } 1752 1753 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1754 { 1755 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1756 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1757 enum port port = encoder->port; 1758 1759 mutex_lock(&i915->display.dpll.lock); 1760 1761 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1762 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1763 1764 mutex_unlock(&i915->display.dpll.lock); 1765 1766 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1767 } 1768 1769 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1770 { 1771 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1772 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1773 enum port port = encoder->port; 1774 u32 tmp; 1775 1776 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1777 1778 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1779 return false; 1780 1781 tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0); 1782 1783 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1784 } 1785 1786 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1787 { 1788 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1789 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1790 enum port port = encoder->port; 1791 enum intel_dpll_id id; 1792 u32 tmp; 1793 1794 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1795 1796 switch (tmp & DDI_CLK_SEL_MASK) { 1797 case DDI_CLK_SEL_TBT_162: 1798 case DDI_CLK_SEL_TBT_270: 1799 case DDI_CLK_SEL_TBT_540: 1800 case DDI_CLK_SEL_TBT_810: 1801 id = DPLL_ID_ICL_TBTPLL; 1802 break; 1803 case DDI_CLK_SEL_MG: 1804 id = icl_tc_port_to_pll_id(tc_port); 1805 break; 1806 default: 1807 MISSING_CASE(tmp); 1808 fallthrough; 1809 case DDI_CLK_SEL_NONE: 1810 return NULL; 1811 } 1812 1813 return intel_get_shared_dpll_by_id(i915, id); 1814 } 1815 1816 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1817 { 1818 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1819 enum intel_dpll_id id; 1820 1821 switch (encoder->port) { 1822 case PORT_A: 1823 id = DPLL_ID_SKL_DPLL0; 1824 break; 1825 case PORT_B: 1826 id = DPLL_ID_SKL_DPLL1; 1827 break; 1828 case PORT_C: 1829 id = DPLL_ID_SKL_DPLL2; 1830 break; 1831 default: 1832 MISSING_CASE(encoder->port); 1833 return NULL; 1834 } 1835 1836 return intel_get_shared_dpll_by_id(i915, id); 1837 } 1838 1839 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1840 const struct intel_crtc_state *crtc_state) 1841 { 1842 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1843 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1844 enum port port = encoder->port; 1845 1846 if (drm_WARN_ON(&i915->drm, !pll)) 1847 return; 1848 1849 mutex_lock(&i915->display.dpll.lock); 1850 1851 intel_de_rmw(i915, DPLL_CTRL2, 1852 DPLL_CTRL2_DDI_CLK_OFF(port) | 1853 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1854 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1855 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1856 1857 mutex_unlock(&i915->display.dpll.lock); 1858 } 1859 1860 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1861 { 1862 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1863 enum port port = encoder->port; 1864 1865 mutex_lock(&i915->display.dpll.lock); 1866 1867 intel_de_rmw(i915, DPLL_CTRL2, 1868 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1869 1870 mutex_unlock(&i915->display.dpll.lock); 1871 } 1872 1873 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1874 { 1875 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1876 enum port port = encoder->port; 1877 1878 /* 1879 * FIXME Not sure if the override affects both 1880 * the PLL selection and the CLK_OFF bit. 1881 */ 1882 return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 1883 } 1884 1885 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 1886 { 1887 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1888 enum port port = encoder->port; 1889 enum intel_dpll_id id; 1890 u32 tmp; 1891 1892 tmp = intel_de_read(i915, DPLL_CTRL2); 1893 1894 /* 1895 * FIXME Not sure if the override affects both 1896 * the PLL selection and the CLK_OFF bit. 1897 */ 1898 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 1899 return NULL; 1900 1901 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 1902 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 1903 1904 return intel_get_shared_dpll_by_id(i915, id); 1905 } 1906 1907 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 1908 const struct intel_crtc_state *crtc_state) 1909 { 1910 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1911 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1912 enum port port = encoder->port; 1913 1914 if (drm_WARN_ON(&i915->drm, !pll)) 1915 return; 1916 1917 intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 1918 } 1919 1920 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 1921 { 1922 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1923 enum port port = encoder->port; 1924 1925 intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 1926 } 1927 1928 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 1929 { 1930 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1931 enum port port = encoder->port; 1932 1933 return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 1934 } 1935 1936 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 1937 { 1938 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1939 enum port port = encoder->port; 1940 enum intel_dpll_id id; 1941 u32 tmp; 1942 1943 tmp = intel_de_read(i915, PORT_CLK_SEL(port)); 1944 1945 switch (tmp & PORT_CLK_SEL_MASK) { 1946 case PORT_CLK_SEL_WRPLL1: 1947 id = DPLL_ID_WRPLL1; 1948 break; 1949 case PORT_CLK_SEL_WRPLL2: 1950 id = DPLL_ID_WRPLL2; 1951 break; 1952 case PORT_CLK_SEL_SPLL: 1953 id = DPLL_ID_SPLL; 1954 break; 1955 case PORT_CLK_SEL_LCPLL_810: 1956 id = DPLL_ID_LCPLL_810; 1957 break; 1958 case PORT_CLK_SEL_LCPLL_1350: 1959 id = DPLL_ID_LCPLL_1350; 1960 break; 1961 case PORT_CLK_SEL_LCPLL_2700: 1962 id = DPLL_ID_LCPLL_2700; 1963 break; 1964 default: 1965 MISSING_CASE(tmp); 1966 fallthrough; 1967 case PORT_CLK_SEL_NONE: 1968 return NULL; 1969 } 1970 1971 return intel_get_shared_dpll_by_id(i915, id); 1972 } 1973 1974 void intel_ddi_enable_clock(struct intel_encoder *encoder, 1975 const struct intel_crtc_state *crtc_state) 1976 { 1977 if (encoder->enable_clock) 1978 encoder->enable_clock(encoder, crtc_state); 1979 } 1980 1981 void intel_ddi_disable_clock(struct intel_encoder *encoder) 1982 { 1983 if (encoder->disable_clock) 1984 encoder->disable_clock(encoder); 1985 } 1986 1987 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 1988 { 1989 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1990 u32 port_mask; 1991 bool ddi_clk_needed; 1992 1993 /* 1994 * In case of DP MST, we sanitize the primary encoder only, not the 1995 * virtual ones. 1996 */ 1997 if (encoder->type == INTEL_OUTPUT_DP_MST) 1998 return; 1999 2000 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2001 u8 pipe_mask; 2002 bool is_mst; 2003 2004 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2005 /* 2006 * In the unlikely case that BIOS enables DP in MST mode, just 2007 * warn since our MST HW readout is incomplete. 2008 */ 2009 if (drm_WARN_ON(&i915->drm, is_mst)) 2010 return; 2011 } 2012 2013 port_mask = BIT(encoder->port); 2014 ddi_clk_needed = encoder->base.crtc; 2015 2016 if (encoder->type == INTEL_OUTPUT_DSI) { 2017 struct intel_encoder *other_encoder; 2018 2019 port_mask = intel_dsi_encoder_ports(encoder); 2020 /* 2021 * Sanity check that we haven't incorrectly registered another 2022 * encoder using any of the ports of this DSI encoder. 2023 */ 2024 for_each_intel_encoder(&i915->drm, other_encoder) { 2025 if (other_encoder == encoder) 2026 continue; 2027 2028 if (drm_WARN_ON(&i915->drm, 2029 port_mask & BIT(other_encoder->port))) 2030 return; 2031 } 2032 /* 2033 * For DSI we keep the ddi clocks gated 2034 * except during enable/disable sequence. 2035 */ 2036 ddi_clk_needed = false; 2037 } 2038 2039 if (ddi_clk_needed || !encoder->is_clock_enabled || 2040 !encoder->is_clock_enabled(encoder)) 2041 return; 2042 2043 drm_notice(&i915->drm, 2044 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2045 encoder->base.base.id, encoder->base.name); 2046 2047 encoder->disable_clock(encoder); 2048 } 2049 2050 static void 2051 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2052 const struct intel_crtc_state *crtc_state) 2053 { 2054 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2055 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port); 2056 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); 2057 u32 ln0, ln1, pin_assignment; 2058 u8 width; 2059 2060 if (!intel_phy_is_tc(dev_priv, phy) || 2061 intel_tc_port_in_tbt_alt_mode(dig_port)) 2062 return; 2063 2064 if (DISPLAY_VER(dev_priv) >= 12) { 2065 ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)); 2066 ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)); 2067 } else { 2068 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 2069 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 2070 } 2071 2072 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2073 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2074 2075 /* DPPATC */ 2076 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 2077 width = crtc_state->lane_count; 2078 2079 switch (pin_assignment) { 2080 case 0x0: 2081 drm_WARN_ON(&dev_priv->drm, 2082 !intel_tc_port_in_legacy_mode(dig_port)); 2083 if (width == 1) { 2084 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2085 } else { 2086 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2087 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2088 } 2089 break; 2090 case 0x1: 2091 if (width == 4) { 2092 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2093 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2094 } 2095 break; 2096 case 0x2: 2097 if (width == 2) { 2098 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2099 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2100 } 2101 break; 2102 case 0x3: 2103 case 0x5: 2104 if (width == 1) { 2105 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2106 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2107 } else { 2108 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2109 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2110 } 2111 break; 2112 case 0x4: 2113 case 0x6: 2114 if (width == 1) { 2115 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2116 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2117 } else { 2118 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2119 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2120 } 2121 break; 2122 default: 2123 MISSING_CASE(pin_assignment); 2124 } 2125 2126 if (DISPLAY_VER(dev_priv) >= 12) { 2127 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0); 2128 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1); 2129 } else { 2130 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 2131 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 2132 } 2133 } 2134 2135 static enum transcoder 2136 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2137 { 2138 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2139 return crtc_state->mst_master_transcoder; 2140 else 2141 return crtc_state->cpu_transcoder; 2142 } 2143 2144 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2145 const struct intel_crtc_state *crtc_state) 2146 { 2147 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2148 2149 if (DISPLAY_VER(dev_priv) >= 12) 2150 return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state)); 2151 else 2152 return DP_TP_CTL(encoder->port); 2153 } 2154 2155 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2156 const struct intel_crtc_state *crtc_state) 2157 { 2158 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2159 2160 if (DISPLAY_VER(dev_priv) >= 12) 2161 return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state)); 2162 else 2163 return DP_TP_STATUS(encoder->port); 2164 } 2165 2166 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2167 const struct intel_crtc_state *crtc_state, 2168 bool enable) 2169 { 2170 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2171 2172 if (!crtc_state->vrr.enable) 2173 return; 2174 2175 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2176 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2177 drm_dbg_kms(&i915->drm, 2178 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2179 str_enable_disable(enable)); 2180 } 2181 2182 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2183 const struct intel_crtc_state *crtc_state) 2184 { 2185 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2186 2187 if (!crtc_state->fec_enable) 2188 return; 2189 2190 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0) 2191 drm_dbg_kms(&i915->drm, 2192 "Failed to set FEC_READY in the sink\n"); 2193 } 2194 2195 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2196 const struct intel_crtc_state *crtc_state) 2197 { 2198 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2199 struct intel_dp *intel_dp; 2200 2201 if (!crtc_state->fec_enable) 2202 return; 2203 2204 intel_dp = enc_to_intel_dp(encoder); 2205 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2206 0, DP_TP_CTL_FEC_ENABLE); 2207 } 2208 2209 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder, 2210 const struct intel_crtc_state *crtc_state) 2211 { 2212 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2213 struct intel_dp *intel_dp; 2214 2215 if (!crtc_state->fec_enable) 2216 return; 2217 2218 intel_dp = enc_to_intel_dp(encoder); 2219 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2220 DP_TP_CTL_FEC_ENABLE, 0); 2221 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2222 } 2223 2224 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2225 const struct intel_crtc_state *crtc_state) 2226 { 2227 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2228 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2229 enum phy phy = intel_port_to_phy(i915, encoder->port); 2230 2231 if (intel_phy_is_combo(i915, phy)) { 2232 bool lane_reversal = 2233 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 2234 2235 intel_combo_phy_power_up_lanes(i915, phy, false, 2236 crtc_state->lane_count, 2237 lane_reversal); 2238 } 2239 } 2240 2241 /* Splitter enable for eDP MSO is limited to certain pipes. */ 2242 static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915) 2243 { 2244 if (IS_ALDERLAKE_P(i915)) 2245 return BIT(PIPE_A) | BIT(PIPE_B); 2246 else 2247 return BIT(PIPE_A); 2248 } 2249 2250 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2251 struct intel_crtc_state *pipe_config) 2252 { 2253 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2254 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2255 enum pipe pipe = crtc->pipe; 2256 u32 dss1; 2257 2258 if (!HAS_MSO(i915)) 2259 return; 2260 2261 dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); 2262 2263 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2264 if (!pipe_config->splitter.enable) 2265 return; 2266 2267 if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) { 2268 pipe_config->splitter.enable = false; 2269 return; 2270 } 2271 2272 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2273 default: 2274 drm_WARN(&i915->drm, true, 2275 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2276 fallthrough; 2277 case SPLITTER_CONFIGURATION_2_SEGMENT: 2278 pipe_config->splitter.link_count = 2; 2279 break; 2280 case SPLITTER_CONFIGURATION_4_SEGMENT: 2281 pipe_config->splitter.link_count = 4; 2282 break; 2283 } 2284 2285 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2286 } 2287 2288 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2289 { 2290 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2291 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2292 enum pipe pipe = crtc->pipe; 2293 u32 dss1 = 0; 2294 2295 if (!HAS_MSO(i915)) 2296 return; 2297 2298 if (crtc_state->splitter.enable) { 2299 dss1 |= SPLITTER_ENABLE; 2300 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2301 if (crtc_state->splitter.link_count == 2) 2302 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2303 else 2304 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2305 } 2306 2307 intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), 2308 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2309 OVERLAP_PIXELS_MASK, dss1); 2310 } 2311 2312 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2313 struct intel_encoder *encoder, 2314 const struct intel_crtc_state *crtc_state, 2315 const struct drm_connector_state *conn_state) 2316 { 2317 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2318 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2319 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2320 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2321 2322 intel_dp_set_link_params(intel_dp, 2323 crtc_state->port_clock, 2324 crtc_state->lane_count); 2325 2326 /* 2327 * We only configure what the register value will be here. Actual 2328 * enabling happens during link training farther down. 2329 */ 2330 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2331 2332 /* 2333 * 1. Enable Power Wells 2334 * 2335 * This was handled at the beginning of intel_atomic_commit_tail(), 2336 * before we called down into this function. 2337 */ 2338 2339 /* 2. Enable Panel Power if PPS is required */ 2340 intel_pps_on(intel_dp); 2341 2342 /* 2343 * 3. For non-TBT Type-C ports, set FIA lane count 2344 * (DFLEXDPSP.DPX4TXLATC) 2345 * 2346 * This was done before tgl_ddi_pre_enable_dp by 2347 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2348 */ 2349 2350 /* 2351 * 4. Enable the port PLL. 2352 * 2353 * The PLL enabling itself was already done before this function by 2354 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 2355 * configure the PLL to port mapping here. 2356 */ 2357 intel_ddi_enable_clock(encoder, crtc_state); 2358 2359 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2360 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2361 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2362 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2363 dig_port->ddi_io_power_domain); 2364 } 2365 2366 /* 6. Program DP_MODE */ 2367 icl_program_mg_dp_mode(dig_port, crtc_state); 2368 2369 /* 2370 * 7. The rest of the below are substeps under the bspec's "Enable and 2371 * Train Display Port" step. Note that steps that are specific to 2372 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2373 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2374 * us when active_mst_links==0, so any steps designated for "single 2375 * stream or multi-stream master transcoder" can just be performed 2376 * unconditionally here. 2377 */ 2378 2379 /* 2380 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2381 * Transcoder. 2382 */ 2383 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2384 2385 if (HAS_DP20(dev_priv)) 2386 intel_ddi_config_transcoder_dp2(encoder, crtc_state); 2387 2388 /* 2389 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2390 * Transport Select 2391 */ 2392 intel_ddi_config_transcoder_func(encoder, crtc_state); 2393 2394 /* 2395 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2396 * selected 2397 * 2398 * This will be handled by the intel_dp_start_link_train() farther 2399 * down this function. 2400 */ 2401 2402 /* 7.e Configure voltage swing and related IO settings */ 2403 encoder->set_signal_levels(encoder, crtc_state); 2404 2405 /* 2406 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2407 * the used lanes of the DDI. 2408 */ 2409 intel_ddi_power_up_lanes(encoder, crtc_state); 2410 2411 /* 2412 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2413 */ 2414 intel_ddi_mso_configure(crtc_state); 2415 2416 if (!is_mst) 2417 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2418 2419 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2420 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); 2421 /* 2422 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2423 * in the FEC_CONFIGURATION register to 1 before initiating link 2424 * training 2425 */ 2426 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 2427 2428 intel_dp_check_frl_training(intel_dp); 2429 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2430 2431 /* 2432 * 7.i Follow DisplayPort specification training sequence (see notes for 2433 * failure handling) 2434 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2435 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2436 * (timeout after 800 us) 2437 */ 2438 intel_dp_start_link_train(intel_dp, crtc_state); 2439 2440 /* 7.k Set DP_TP_CTL link training to Normal */ 2441 if (!is_trans_port_sync_mode(crtc_state)) 2442 intel_dp_stop_link_train(intel_dp, crtc_state); 2443 2444 /* 7.l Configure and enable FEC if needed */ 2445 intel_ddi_enable_fec(encoder, crtc_state); 2446 2447 intel_dsc_dp_pps_write(encoder, crtc_state); 2448 } 2449 2450 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2451 struct intel_encoder *encoder, 2452 const struct intel_crtc_state *crtc_state, 2453 const struct drm_connector_state *conn_state) 2454 { 2455 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2456 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2457 enum port port = encoder->port; 2458 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2459 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2460 2461 if (DISPLAY_VER(dev_priv) < 11) 2462 drm_WARN_ON(&dev_priv->drm, 2463 is_mst && (port == PORT_A || port == PORT_E)); 2464 else 2465 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 2466 2467 intel_dp_set_link_params(intel_dp, 2468 crtc_state->port_clock, 2469 crtc_state->lane_count); 2470 2471 /* 2472 * We only configure what the register value will be here. Actual 2473 * enabling happens during link training farther down. 2474 */ 2475 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2476 2477 intel_pps_on(intel_dp); 2478 2479 intel_ddi_enable_clock(encoder, crtc_state); 2480 2481 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2482 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2483 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2484 dig_port->ddi_io_power_domain); 2485 } 2486 2487 icl_program_mg_dp_mode(dig_port, crtc_state); 2488 2489 if (has_buf_trans_select(dev_priv)) 2490 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2491 2492 encoder->set_signal_levels(encoder, crtc_state); 2493 2494 intel_ddi_power_up_lanes(encoder, crtc_state); 2495 2496 if (!is_mst) 2497 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2498 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2499 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, 2500 true); 2501 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 2502 intel_dp_start_link_train(intel_dp, crtc_state); 2503 if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && 2504 !is_trans_port_sync_mode(crtc_state)) 2505 intel_dp_stop_link_train(intel_dp, crtc_state); 2506 2507 intel_ddi_enable_fec(encoder, crtc_state); 2508 2509 if (!is_mst) 2510 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2511 2512 intel_dsc_dp_pps_write(encoder, crtc_state); 2513 } 2514 2515 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2516 struct intel_encoder *encoder, 2517 const struct intel_crtc_state *crtc_state, 2518 const struct drm_connector_state *conn_state) 2519 { 2520 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2521 2522 if (HAS_DP20(dev_priv)) 2523 intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder), 2524 crtc_state); 2525 2526 if (DISPLAY_VER(dev_priv) >= 12) 2527 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2528 else 2529 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2530 2531 /* MST will call a setting of MSA after an allocating of Virtual Channel 2532 * from MST encoder pre_enable callback. 2533 */ 2534 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2535 intel_ddi_set_dp_msa(crtc_state, conn_state); 2536 } 2537 2538 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2539 struct intel_encoder *encoder, 2540 const struct intel_crtc_state *crtc_state, 2541 const struct drm_connector_state *conn_state) 2542 { 2543 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2544 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2545 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2546 2547 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2548 intel_ddi_enable_clock(encoder, crtc_state); 2549 2550 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2551 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2552 dig_port->ddi_io_power_domain); 2553 2554 icl_program_mg_dp_mode(dig_port, crtc_state); 2555 2556 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2557 2558 dig_port->set_infoframes(encoder, 2559 crtc_state->has_infoframe, 2560 crtc_state, conn_state); 2561 } 2562 2563 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 2564 struct intel_encoder *encoder, 2565 const struct intel_crtc_state *crtc_state, 2566 const struct drm_connector_state *conn_state) 2567 { 2568 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2569 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2570 enum pipe pipe = crtc->pipe; 2571 2572 /* 2573 * When called from DP MST code: 2574 * - conn_state will be NULL 2575 * - encoder will be the main encoder (ie. mst->primary) 2576 * - the main connector associated with this port 2577 * won't be active or linked to a crtc 2578 * - crtc_state will be the state of the first stream to 2579 * be activated on this port, and it may not be the same 2580 * stream that will be deactivated last, but each stream 2581 * should have a state that is identical when it comes to 2582 * the DP link parameteres 2583 */ 2584 2585 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 2586 2587 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2588 2589 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 2590 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 2591 conn_state); 2592 } else { 2593 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2594 2595 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 2596 conn_state); 2597 2598 /* FIXME precompute everything properly */ 2599 /* FIXME how do we turn infoframes off again? */ 2600 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) 2601 dig_port->set_infoframes(encoder, 2602 crtc_state->has_infoframe, 2603 crtc_state, conn_state); 2604 } 2605 } 2606 2607 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 2608 const struct intel_crtc_state *crtc_state) 2609 { 2610 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2611 enum port port = encoder->port; 2612 bool wait = false; 2613 u32 val; 2614 2615 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2616 if (val & DDI_BUF_CTL_ENABLE) { 2617 val &= ~DDI_BUF_CTL_ENABLE; 2618 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 2619 wait = true; 2620 } 2621 2622 if (intel_crtc_has_dp_encoder(crtc_state)) 2623 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2624 DP_TP_CTL_ENABLE, 0); 2625 2626 /* Disable FEC in DP Sink */ 2627 intel_ddi_disable_fec_state(encoder, crtc_state); 2628 2629 if (wait) 2630 intel_wait_ddi_buf_idle(dev_priv, port); 2631 } 2632 2633 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 2634 struct intel_encoder *encoder, 2635 const struct intel_crtc_state *old_crtc_state, 2636 const struct drm_connector_state *old_conn_state) 2637 { 2638 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2639 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2640 struct intel_dp *intel_dp = &dig_port->dp; 2641 bool is_mst = intel_crtc_has_type(old_crtc_state, 2642 INTEL_OUTPUT_DP_MST); 2643 2644 if (!is_mst) 2645 intel_dp_set_infoframes(encoder, false, 2646 old_crtc_state, old_conn_state); 2647 2648 /* 2649 * Power down sink before disabling the port, otherwise we end 2650 * up getting interrupts from the sink on detecting link loss. 2651 */ 2652 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 2653 2654 if (DISPLAY_VER(dev_priv) >= 12) { 2655 if (is_mst) { 2656 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 2657 2658 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 2659 TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK, 2660 0); 2661 } 2662 } else { 2663 if (!is_mst) 2664 intel_ddi_disable_transcoder_clock(old_crtc_state); 2665 } 2666 2667 intel_disable_ddi_buf(encoder, old_crtc_state); 2668 2669 /* 2670 * From TGL spec: "If single stream or multi-stream master transcoder: 2671 * Configure Transcoder Clock select to direct no clock to the 2672 * transcoder" 2673 */ 2674 if (DISPLAY_VER(dev_priv) >= 12) 2675 intel_ddi_disable_transcoder_clock(old_crtc_state); 2676 2677 intel_pps_vdd_on(intel_dp); 2678 intel_pps_off(intel_dp); 2679 2680 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 2681 intel_display_power_put(dev_priv, 2682 dig_port->ddi_io_power_domain, 2683 fetch_and_zero(&dig_port->ddi_io_wakeref)); 2684 2685 intel_ddi_disable_clock(encoder); 2686 } 2687 2688 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 2689 struct intel_encoder *encoder, 2690 const struct intel_crtc_state *old_crtc_state, 2691 const struct drm_connector_state *old_conn_state) 2692 { 2693 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2694 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2695 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2696 2697 dig_port->set_infoframes(encoder, false, 2698 old_crtc_state, old_conn_state); 2699 2700 if (DISPLAY_VER(dev_priv) < 12) 2701 intel_ddi_disable_transcoder_clock(old_crtc_state); 2702 2703 intel_disable_ddi_buf(encoder, old_crtc_state); 2704 2705 if (DISPLAY_VER(dev_priv) >= 12) 2706 intel_ddi_disable_transcoder_clock(old_crtc_state); 2707 2708 intel_display_power_put(dev_priv, 2709 dig_port->ddi_io_power_domain, 2710 fetch_and_zero(&dig_port->ddi_io_wakeref)); 2711 2712 intel_ddi_disable_clock(encoder); 2713 2714 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 2715 } 2716 2717 static void intel_ddi_post_disable(struct intel_atomic_state *state, 2718 struct intel_encoder *encoder, 2719 const struct intel_crtc_state *old_crtc_state, 2720 const struct drm_connector_state *old_conn_state) 2721 { 2722 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2723 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2724 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2725 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 2726 struct intel_crtc *slave_crtc; 2727 2728 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) { 2729 intel_crtc_vblank_off(old_crtc_state); 2730 2731 intel_vrr_disable(old_crtc_state); 2732 2733 intel_disable_transcoder(old_crtc_state); 2734 2735 intel_ddi_disable_transcoder_func(old_crtc_state); 2736 2737 intel_dsc_disable(old_crtc_state); 2738 2739 if (DISPLAY_VER(dev_priv) >= 9) 2740 skl_scaler_disable(old_crtc_state); 2741 else 2742 ilk_pfit_disable(old_crtc_state); 2743 } 2744 2745 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc, 2746 intel_crtc_bigjoiner_slave_pipes(old_crtc_state)) { 2747 const struct intel_crtc_state *old_slave_crtc_state = 2748 intel_atomic_get_old_crtc_state(state, slave_crtc); 2749 2750 intel_crtc_vblank_off(old_slave_crtc_state); 2751 2752 intel_dsc_disable(old_slave_crtc_state); 2753 skl_scaler_disable(old_slave_crtc_state); 2754 } 2755 2756 /* 2757 * When called from DP MST code: 2758 * - old_conn_state will be NULL 2759 * - encoder will be the main encoder (ie. mst->primary) 2760 * - the main connector associated with this port 2761 * won't be active or linked to a crtc 2762 * - old_crtc_state will be the state of the last stream to 2763 * be deactivated on this port, and it may not be the same 2764 * stream that was activated last, but each stream 2765 * should have a state that is identical when it comes to 2766 * the DP link parameteres 2767 */ 2768 2769 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 2770 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 2771 old_conn_state); 2772 else 2773 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 2774 old_conn_state); 2775 2776 main_link_aux_power_domain_put(dig_port, old_crtc_state); 2777 2778 if (is_tc_port) 2779 intel_tc_port_put_link(dig_port); 2780 } 2781 2782 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 2783 struct intel_encoder *encoder, 2784 const struct intel_crtc_state *crtc_state) 2785 { 2786 const struct drm_connector_state *conn_state; 2787 struct drm_connector *conn; 2788 int i; 2789 2790 if (!crtc_state->sync_mode_slaves_mask) 2791 return; 2792 2793 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 2794 struct intel_encoder *slave_encoder = 2795 to_intel_encoder(conn_state->best_encoder); 2796 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 2797 const struct intel_crtc_state *slave_crtc_state; 2798 2799 if (!slave_crtc) 2800 continue; 2801 2802 slave_crtc_state = 2803 intel_atomic_get_new_crtc_state(state, slave_crtc); 2804 2805 if (slave_crtc_state->master_transcoder != 2806 crtc_state->cpu_transcoder) 2807 continue; 2808 2809 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 2810 slave_crtc_state); 2811 } 2812 2813 usleep_range(200, 400); 2814 2815 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 2816 crtc_state); 2817 } 2818 2819 static void intel_enable_ddi_dp(struct intel_atomic_state *state, 2820 struct intel_encoder *encoder, 2821 const struct intel_crtc_state *crtc_state, 2822 const struct drm_connector_state *conn_state) 2823 { 2824 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2825 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2826 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2827 enum port port = encoder->port; 2828 2829 if (port == PORT_A && DISPLAY_VER(dev_priv) < 9) 2830 intel_dp_stop_link_train(intel_dp, crtc_state); 2831 2832 drm_connector_update_privacy_screen(conn_state); 2833 intel_edp_backlight_on(crtc_state, conn_state); 2834 2835 if (!dig_port->lspcon.active || dig_port->dp.has_hdmi_sink) 2836 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 2837 2838 intel_audio_codec_enable(encoder, crtc_state, conn_state); 2839 2840 trans_port_sync_stop_link_train(state, encoder, crtc_state); 2841 } 2842 2843 static i915_reg_t 2844 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 2845 enum port port) 2846 { 2847 static const enum transcoder trans[] = { 2848 [PORT_A] = TRANSCODER_EDP, 2849 [PORT_B] = TRANSCODER_A, 2850 [PORT_C] = TRANSCODER_B, 2851 [PORT_D] = TRANSCODER_C, 2852 [PORT_E] = TRANSCODER_A, 2853 }; 2854 2855 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9); 2856 2857 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) 2858 port = PORT_A; 2859 2860 return CHICKEN_TRANS(trans[port]); 2861 } 2862 2863 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, 2864 struct intel_encoder *encoder, 2865 const struct intel_crtc_state *crtc_state, 2866 const struct drm_connector_state *conn_state) 2867 { 2868 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2869 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2870 struct drm_connector *connector = conn_state->connector; 2871 enum port port = encoder->port; 2872 enum phy phy = intel_port_to_phy(dev_priv, port); 2873 u32 buf_ctl; 2874 2875 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 2876 crtc_state->hdmi_high_tmds_clock_ratio, 2877 crtc_state->hdmi_scrambling)) 2878 drm_dbg_kms(&dev_priv->drm, 2879 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 2880 connector->base.id, connector->name); 2881 2882 if (has_buf_trans_select(dev_priv)) 2883 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 2884 2885 encoder->set_signal_levels(encoder, crtc_state); 2886 2887 /* Display WA #1143: skl,kbl,cfl */ 2888 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { 2889 /* 2890 * For some reason these chicken bits have been 2891 * stuffed into a transcoder register, event though 2892 * the bits affect a specific DDI port rather than 2893 * a specific transcoder. 2894 */ 2895 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 2896 u32 val; 2897 2898 val = intel_de_read(dev_priv, reg); 2899 2900 if (port == PORT_E) 2901 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 2902 DDIE_TRAINING_OVERRIDE_VALUE; 2903 else 2904 val |= DDI_TRAINING_OVERRIDE_ENABLE | 2905 DDI_TRAINING_OVERRIDE_VALUE; 2906 2907 intel_de_write(dev_priv, reg, val); 2908 intel_de_posting_read(dev_priv, reg); 2909 2910 udelay(1); 2911 2912 if (port == PORT_E) 2913 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 2914 DDIE_TRAINING_OVERRIDE_VALUE); 2915 else 2916 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 2917 DDI_TRAINING_OVERRIDE_VALUE); 2918 2919 intel_de_write(dev_priv, reg, val); 2920 } 2921 2922 intel_ddi_power_up_lanes(encoder, crtc_state); 2923 2924 /* In HDMI/DVI mode, the port width, and swing/emphasis values 2925 * are ignored so nothing special needs to be done besides 2926 * enabling the port. 2927 * 2928 * On ADL_P the PHY link rate and lane count must be programmed but 2929 * these are both 0 for HDMI. 2930 */ 2931 buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE; 2932 if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) { 2933 drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port)); 2934 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 2935 } 2936 intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl); 2937 2938 intel_wait_ddi_buf_active(dev_priv, port); 2939 2940 intel_audio_codec_enable(encoder, crtc_state, conn_state); 2941 } 2942 2943 static void intel_enable_ddi(struct intel_atomic_state *state, 2944 struct intel_encoder *encoder, 2945 const struct intel_crtc_state *crtc_state, 2946 const struct drm_connector_state *conn_state) 2947 { 2948 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 2949 2950 if (!intel_crtc_is_bigjoiner_slave(crtc_state)) 2951 intel_ddi_enable_transcoder_func(encoder, crtc_state); 2952 2953 /* Enable/Disable DP2.0 SDP split config before transcoder */ 2954 intel_audio_sdp_split_update(encoder, crtc_state); 2955 2956 intel_enable_transcoder(crtc_state); 2957 2958 intel_vrr_enable(encoder, crtc_state); 2959 2960 intel_crtc_vblank_on(crtc_state); 2961 2962 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 2963 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state); 2964 else 2965 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state); 2966 2967 /* Enable hdcp if it's desired */ 2968 if (conn_state->content_protection == 2969 DRM_MODE_CONTENT_PROTECTION_DESIRED) 2970 intel_hdcp_enable(to_intel_connector(conn_state->connector), 2971 crtc_state, 2972 (u8)conn_state->hdcp_content_type); 2973 } 2974 2975 static void intel_disable_ddi_dp(struct intel_atomic_state *state, 2976 struct intel_encoder *encoder, 2977 const struct intel_crtc_state *old_crtc_state, 2978 const struct drm_connector_state *old_conn_state) 2979 { 2980 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2981 2982 intel_dp->link_trained = false; 2983 2984 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 2985 2986 intel_psr_disable(intel_dp, old_crtc_state); 2987 intel_edp_backlight_off(old_conn_state); 2988 /* Disable the decompression in DP Sink */ 2989 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, 2990 false); 2991 /* Disable Ignore_MSA bit in DP Sink */ 2992 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 2993 false); 2994 } 2995 2996 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state, 2997 struct intel_encoder *encoder, 2998 const struct intel_crtc_state *old_crtc_state, 2999 const struct drm_connector_state *old_conn_state) 3000 { 3001 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3002 struct drm_connector *connector = old_conn_state->connector; 3003 3004 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 3005 3006 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3007 false, false)) 3008 drm_dbg_kms(&i915->drm, 3009 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3010 connector->base.id, connector->name); 3011 } 3012 3013 static void intel_disable_ddi(struct intel_atomic_state *state, 3014 struct intel_encoder *encoder, 3015 const struct intel_crtc_state *old_crtc_state, 3016 const struct drm_connector_state *old_conn_state) 3017 { 3018 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3019 3020 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3021 intel_disable_ddi_hdmi(state, encoder, old_crtc_state, 3022 old_conn_state); 3023 else 3024 intel_disable_ddi_dp(state, encoder, old_crtc_state, 3025 old_conn_state); 3026 } 3027 3028 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3029 struct intel_encoder *encoder, 3030 const struct intel_crtc_state *crtc_state, 3031 const struct drm_connector_state *conn_state) 3032 { 3033 intel_ddi_set_dp_msa(crtc_state, conn_state); 3034 3035 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3036 3037 intel_backlight_update(state, encoder, crtc_state, conn_state); 3038 drm_connector_update_privacy_screen(conn_state); 3039 } 3040 3041 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3042 struct intel_encoder *encoder, 3043 const struct intel_crtc_state *crtc_state, 3044 const struct drm_connector_state *conn_state) 3045 { 3046 3047 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3048 !intel_encoder_is_mst(encoder)) 3049 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3050 conn_state); 3051 3052 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3053 } 3054 3055 static void 3056 intel_ddi_update_prepare(struct intel_atomic_state *state, 3057 struct intel_encoder *encoder, 3058 struct intel_crtc *crtc) 3059 { 3060 struct drm_i915_private *i915 = to_i915(state->base.dev); 3061 struct intel_crtc_state *crtc_state = 3062 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL; 3063 int required_lanes = crtc_state ? crtc_state->lane_count : 1; 3064 3065 drm_WARN_ON(state->base.dev, crtc && crtc->active); 3066 3067 intel_tc_port_get_link(enc_to_dig_port(encoder), 3068 required_lanes); 3069 if (crtc_state && crtc_state->hw.active) { 3070 struct intel_crtc *slave_crtc; 3071 3072 intel_update_active_dpll(state, crtc, encoder); 3073 3074 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 3075 intel_crtc_bigjoiner_slave_pipes(crtc_state)) 3076 intel_update_active_dpll(state, slave_crtc, encoder); 3077 } 3078 } 3079 3080 static void 3081 intel_ddi_update_complete(struct intel_atomic_state *state, 3082 struct intel_encoder *encoder, 3083 struct intel_crtc *crtc) 3084 { 3085 intel_tc_port_put_link(enc_to_dig_port(encoder)); 3086 } 3087 3088 static void 3089 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3090 struct intel_encoder *encoder, 3091 const struct intel_crtc_state *crtc_state, 3092 const struct drm_connector_state *conn_state) 3093 { 3094 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3095 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3096 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3097 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 3098 3099 if (is_tc_port) 3100 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3101 3102 main_link_aux_power_domain_get(dig_port, crtc_state); 3103 3104 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3105 /* 3106 * Program the lane count for static/dynamic connections on 3107 * Type-C ports. Skip this step for TBT. 3108 */ 3109 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3110 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3111 bxt_ddi_phy_set_lane_optim_mask(encoder, 3112 crtc_state->lane_lat_optim_mask); 3113 } 3114 3115 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) 3116 { 3117 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3118 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 3119 int ln; 3120 3121 for (ln = 0; ln < 2; ln++) 3122 intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0); 3123 } 3124 3125 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3126 const struct intel_crtc_state *crtc_state) 3127 { 3128 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3129 struct intel_encoder *encoder = &dig_port->base; 3130 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3131 enum port port = encoder->port; 3132 u32 dp_tp_ctl, ddi_buf_ctl; 3133 bool wait = false; 3134 3135 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3136 3137 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 3138 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3139 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 3140 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3141 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 3142 wait = true; 3143 } 3144 3145 dp_tp_ctl &= ~DP_TP_CTL_ENABLE; 3146 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3147 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3148 3149 if (wait) 3150 intel_wait_ddi_buf_idle(dev_priv, port); 3151 } 3152 3153 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3154 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3155 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3156 } else { 3157 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3158 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 3159 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3160 } 3161 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3162 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3163 3164 if (IS_ALDERLAKE_P(dev_priv) && 3165 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) 3166 adlp_tbt_to_dp_alt_switch_wa(encoder); 3167 3168 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3169 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3170 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3171 3172 intel_wait_ddi_buf_active(dev_priv, port); 3173 } 3174 3175 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3176 const struct intel_crtc_state *crtc_state, 3177 u8 dp_train_pat) 3178 { 3179 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3180 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3181 u32 temp; 3182 3183 temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3184 3185 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3186 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3187 case DP_TRAINING_PATTERN_DISABLE: 3188 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3189 break; 3190 case DP_TRAINING_PATTERN_1: 3191 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3192 break; 3193 case DP_TRAINING_PATTERN_2: 3194 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3195 break; 3196 case DP_TRAINING_PATTERN_3: 3197 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3198 break; 3199 case DP_TRAINING_PATTERN_4: 3200 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3201 break; 3202 } 3203 3204 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp); 3205 } 3206 3207 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3208 const struct intel_crtc_state *crtc_state) 3209 { 3210 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3211 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3212 enum port port = encoder->port; 3213 3214 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 3215 DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE); 3216 3217 /* 3218 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3219 * reason we need to set idle transmission mode is to work around a HW 3220 * issue where we enable the pipe while not in idle link-training mode. 3221 * In this case there is requirement to wait for a minimum number of 3222 * idle patterns to be sent. 3223 */ 3224 if (port == PORT_A && DISPLAY_VER(dev_priv) < 12) 3225 return; 3226 3227 if (intel_de_wait_for_set(dev_priv, 3228 dp_tp_status_reg(encoder, crtc_state), 3229 DP_TP_STATUS_IDLE_DONE, 1)) 3230 drm_err(&dev_priv->drm, 3231 "Timed out waiting for DP idle patterns\n"); 3232 } 3233 3234 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 3235 enum transcoder cpu_transcoder) 3236 { 3237 if (cpu_transcoder == TRANSCODER_EDP) 3238 return false; 3239 3240 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO)) 3241 return false; 3242 3243 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 3244 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3245 } 3246 3247 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, 3248 struct intel_crtc_state *crtc_state) 3249 { 3250 if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000) 3251 crtc_state->min_voltage_level = 2; 3252 else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000) 3253 crtc_state->min_voltage_level = 3; 3254 else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000) 3255 crtc_state->min_voltage_level = 1; 3256 } 3257 3258 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, 3259 enum transcoder cpu_transcoder) 3260 { 3261 u32 master_select; 3262 3263 if (DISPLAY_VER(dev_priv) >= 11) { 3264 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder)); 3265 3266 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3267 return INVALID_TRANSCODER; 3268 3269 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3270 } else { 3271 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3272 3273 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3274 return INVALID_TRANSCODER; 3275 3276 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3277 } 3278 3279 if (master_select == 0) 3280 return TRANSCODER_EDP; 3281 else 3282 return master_select - 1; 3283 } 3284 3285 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3286 { 3287 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3288 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3289 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3290 enum transcoder cpu_transcoder; 3291 3292 crtc_state->master_transcoder = 3293 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); 3294 3295 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { 3296 enum intel_display_power_domain power_domain; 3297 intel_wakeref_t trans_wakeref; 3298 3299 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3300 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 3301 power_domain); 3302 3303 if (!trans_wakeref) 3304 continue; 3305 3306 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == 3307 crtc_state->cpu_transcoder) 3308 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3309 3310 intel_display_power_put(dev_priv, power_domain, trans_wakeref); 3311 } 3312 3313 drm_WARN_ON(&dev_priv->drm, 3314 crtc_state->master_transcoder != INVALID_TRANSCODER && 3315 crtc_state->sync_mode_slaves_mask); 3316 } 3317 3318 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 3319 struct intel_crtc_state *pipe_config) 3320 { 3321 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3322 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3323 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3324 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3325 u32 temp, flags = 0; 3326 3327 temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3328 if (temp & TRANS_DDI_PHSYNC) 3329 flags |= DRM_MODE_FLAG_PHSYNC; 3330 else 3331 flags |= DRM_MODE_FLAG_NHSYNC; 3332 if (temp & TRANS_DDI_PVSYNC) 3333 flags |= DRM_MODE_FLAG_PVSYNC; 3334 else 3335 flags |= DRM_MODE_FLAG_NVSYNC; 3336 3337 pipe_config->hw.adjusted_mode.flags |= flags; 3338 3339 switch (temp & TRANS_DDI_BPC_MASK) { 3340 case TRANS_DDI_BPC_6: 3341 pipe_config->pipe_bpp = 18; 3342 break; 3343 case TRANS_DDI_BPC_8: 3344 pipe_config->pipe_bpp = 24; 3345 break; 3346 case TRANS_DDI_BPC_10: 3347 pipe_config->pipe_bpp = 30; 3348 break; 3349 case TRANS_DDI_BPC_12: 3350 pipe_config->pipe_bpp = 36; 3351 break; 3352 default: 3353 break; 3354 } 3355 3356 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 3357 case TRANS_DDI_MODE_SELECT_HDMI: 3358 pipe_config->has_hdmi_sink = true; 3359 3360 pipe_config->infoframes.enable |= 3361 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3362 3363 if (pipe_config->infoframes.enable) 3364 pipe_config->has_infoframe = true; 3365 3366 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 3367 pipe_config->hdmi_scrambling = true; 3368 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 3369 pipe_config->hdmi_high_tmds_clock_ratio = true; 3370 fallthrough; 3371 case TRANS_DDI_MODE_SELECT_DVI: 3372 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 3373 pipe_config->lane_count = 4; 3374 break; 3375 case TRANS_DDI_MODE_SELECT_DP_SST: 3376 if (encoder->type == INTEL_OUTPUT_EDP) 3377 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 3378 else 3379 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 3380 pipe_config->lane_count = 3381 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3382 3383 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 3384 &pipe_config->dp_m_n); 3385 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, 3386 &pipe_config->dp_m2_n2); 3387 3388 if (DISPLAY_VER(dev_priv) >= 11) { 3389 i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config); 3390 3391 pipe_config->fec_enable = 3392 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE; 3393 3394 drm_dbg_kms(&dev_priv->drm, 3395 "[ENCODER:%d:%s] Fec status: %u\n", 3396 encoder->base.base.id, encoder->base.name, 3397 pipe_config->fec_enable); 3398 } 3399 3400 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) 3401 pipe_config->infoframes.enable |= 3402 intel_lspcon_infoframes_enabled(encoder, pipe_config); 3403 else 3404 pipe_config->infoframes.enable |= 3405 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3406 break; 3407 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 3408 if (!HAS_DP20(dev_priv)) { 3409 /* FDI */ 3410 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 3411 break; 3412 } 3413 fallthrough; /* 128b/132b */ 3414 case TRANS_DDI_MODE_SELECT_DP_MST: 3415 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 3416 pipe_config->lane_count = 3417 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3418 3419 if (DISPLAY_VER(dev_priv) >= 12) 3420 pipe_config->mst_master_transcoder = 3421 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); 3422 3423 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 3424 &pipe_config->dp_m_n); 3425 3426 pipe_config->infoframes.enable |= 3427 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3428 break; 3429 default: 3430 break; 3431 } 3432 } 3433 3434 static void intel_ddi_get_config(struct intel_encoder *encoder, 3435 struct intel_crtc_state *pipe_config) 3436 { 3437 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3438 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3439 3440 /* XXX: DSI transcoder paranoia */ 3441 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 3442 return; 3443 3444 intel_ddi_read_func_ctl(encoder, pipe_config); 3445 3446 intel_ddi_mso_get_config(encoder, pipe_config); 3447 3448 pipe_config->has_audio = 3449 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 3450 3451 if (encoder->type == INTEL_OUTPUT_EDP) 3452 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); 3453 3454 ddi_dotclock_get(pipe_config); 3455 3456 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3457 pipe_config->lane_lat_optim_mask = 3458 bxt_ddi_phy_get_lane_lat_optim_mask(encoder); 3459 3460 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 3461 3462 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 3463 3464 intel_read_infoframe(encoder, pipe_config, 3465 HDMI_INFOFRAME_TYPE_AVI, 3466 &pipe_config->infoframes.avi); 3467 intel_read_infoframe(encoder, pipe_config, 3468 HDMI_INFOFRAME_TYPE_SPD, 3469 &pipe_config->infoframes.spd); 3470 intel_read_infoframe(encoder, pipe_config, 3471 HDMI_INFOFRAME_TYPE_VENDOR, 3472 &pipe_config->infoframes.hdmi); 3473 intel_read_infoframe(encoder, pipe_config, 3474 HDMI_INFOFRAME_TYPE_DRM, 3475 &pipe_config->infoframes.drm); 3476 3477 if (DISPLAY_VER(dev_priv) >= 8) 3478 bdw_get_trans_port_sync_config(pipe_config); 3479 3480 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 3481 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 3482 3483 intel_psr_get_config(encoder, pipe_config); 3484 3485 intel_audio_codec_get_config(encoder, pipe_config); 3486 } 3487 3488 void intel_ddi_get_clock(struct intel_encoder *encoder, 3489 struct intel_crtc_state *crtc_state, 3490 struct intel_shared_dpll *pll) 3491 { 3492 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3493 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 3494 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 3495 bool pll_active; 3496 3497 if (drm_WARN_ON(&i915->drm, !pll)) 3498 return; 3499 3500 port_dpll->pll = pll; 3501 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 3502 drm_WARN_ON(&i915->drm, !pll_active); 3503 3504 icl_set_active_port_dpll(crtc_state, port_dpll_id); 3505 3506 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 3507 &crtc_state->dpll_hw_state); 3508 } 3509 3510 static void dg2_ddi_get_config(struct intel_encoder *encoder, 3511 struct intel_crtc_state *crtc_state) 3512 { 3513 intel_mpllb_readout_hw_state(encoder, &crtc_state->mpllb_state); 3514 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->mpllb_state); 3515 3516 intel_ddi_get_config(encoder, crtc_state); 3517 } 3518 3519 static void adls_ddi_get_config(struct intel_encoder *encoder, 3520 struct intel_crtc_state *crtc_state) 3521 { 3522 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 3523 intel_ddi_get_config(encoder, crtc_state); 3524 } 3525 3526 static void rkl_ddi_get_config(struct intel_encoder *encoder, 3527 struct intel_crtc_state *crtc_state) 3528 { 3529 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 3530 intel_ddi_get_config(encoder, crtc_state); 3531 } 3532 3533 static void dg1_ddi_get_config(struct intel_encoder *encoder, 3534 struct intel_crtc_state *crtc_state) 3535 { 3536 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 3537 intel_ddi_get_config(encoder, crtc_state); 3538 } 3539 3540 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 3541 struct intel_crtc_state *crtc_state) 3542 { 3543 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 3544 intel_ddi_get_config(encoder, crtc_state); 3545 } 3546 3547 static bool icl_ddi_tc_pll_is_tbt(const struct intel_shared_dpll *pll) 3548 { 3549 return pll->info->id == DPLL_ID_ICL_TBTPLL; 3550 } 3551 3552 static enum icl_port_dpll_id 3553 icl_ddi_tc_port_pll_type(struct intel_encoder *encoder, 3554 const struct intel_crtc_state *crtc_state) 3555 { 3556 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3557 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 3558 3559 if (drm_WARN_ON(&i915->drm, !pll)) 3560 return ICL_PORT_DPLL_DEFAULT; 3561 3562 if (icl_ddi_tc_pll_is_tbt(pll)) 3563 return ICL_PORT_DPLL_DEFAULT; 3564 else 3565 return ICL_PORT_DPLL_MG_PHY; 3566 } 3567 3568 enum icl_port_dpll_id 3569 intel_ddi_port_pll_type(struct intel_encoder *encoder, 3570 const struct intel_crtc_state *crtc_state) 3571 { 3572 if (!encoder->port_pll_type) 3573 return ICL_PORT_DPLL_DEFAULT; 3574 3575 return encoder->port_pll_type(encoder, crtc_state); 3576 } 3577 3578 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 3579 struct intel_crtc_state *crtc_state, 3580 struct intel_shared_dpll *pll) 3581 { 3582 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3583 enum icl_port_dpll_id port_dpll_id; 3584 struct icl_port_dpll *port_dpll; 3585 bool pll_active; 3586 3587 if (drm_WARN_ON(&i915->drm, !pll)) 3588 return; 3589 3590 if (icl_ddi_tc_pll_is_tbt(pll)) 3591 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 3592 else 3593 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 3594 3595 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 3596 3597 port_dpll->pll = pll; 3598 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 3599 drm_WARN_ON(&i915->drm, !pll_active); 3600 3601 icl_set_active_port_dpll(crtc_state, port_dpll_id); 3602 3603 if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll)) 3604 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port); 3605 else 3606 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 3607 &crtc_state->dpll_hw_state); 3608 } 3609 3610 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 3611 struct intel_crtc_state *crtc_state) 3612 { 3613 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 3614 intel_ddi_get_config(encoder, crtc_state); 3615 } 3616 3617 static void bxt_ddi_get_config(struct intel_encoder *encoder, 3618 struct intel_crtc_state *crtc_state) 3619 { 3620 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 3621 intel_ddi_get_config(encoder, crtc_state); 3622 } 3623 3624 static void skl_ddi_get_config(struct intel_encoder *encoder, 3625 struct intel_crtc_state *crtc_state) 3626 { 3627 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 3628 intel_ddi_get_config(encoder, crtc_state); 3629 } 3630 3631 void hsw_ddi_get_config(struct intel_encoder *encoder, 3632 struct intel_crtc_state *crtc_state) 3633 { 3634 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 3635 intel_ddi_get_config(encoder, crtc_state); 3636 } 3637 3638 static void intel_ddi_sync_state(struct intel_encoder *encoder, 3639 const struct intel_crtc_state *crtc_state) 3640 { 3641 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3642 enum phy phy = intel_port_to_phy(i915, encoder->port); 3643 3644 if (intel_phy_is_tc(i915, phy)) 3645 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder), 3646 crtc_state); 3647 3648 if (crtc_state && intel_crtc_has_dp_encoder(crtc_state)) 3649 intel_dp_sync_state(encoder, crtc_state); 3650 } 3651 3652 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 3653 struct intel_crtc_state *crtc_state) 3654 { 3655 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3656 enum phy phy = intel_port_to_phy(i915, encoder->port); 3657 bool fastset = true; 3658 3659 if (intel_phy_is_tc(i915, phy)) { 3660 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", 3661 encoder->base.base.id, encoder->base.name); 3662 crtc_state->uapi.mode_changed = true; 3663 fastset = false; 3664 } 3665 3666 if (intel_crtc_has_dp_encoder(crtc_state) && 3667 !intel_dp_initial_fastset_check(encoder, crtc_state)) 3668 fastset = false; 3669 3670 return fastset; 3671 } 3672 3673 static enum intel_output_type 3674 intel_ddi_compute_output_type(struct intel_encoder *encoder, 3675 struct intel_crtc_state *crtc_state, 3676 struct drm_connector_state *conn_state) 3677 { 3678 switch (conn_state->connector->connector_type) { 3679 case DRM_MODE_CONNECTOR_HDMIA: 3680 return INTEL_OUTPUT_HDMI; 3681 case DRM_MODE_CONNECTOR_eDP: 3682 return INTEL_OUTPUT_EDP; 3683 case DRM_MODE_CONNECTOR_DisplayPort: 3684 return INTEL_OUTPUT_DP; 3685 default: 3686 MISSING_CASE(conn_state->connector->connector_type); 3687 return INTEL_OUTPUT_UNUSED; 3688 } 3689 } 3690 3691 static int intel_ddi_compute_config(struct intel_encoder *encoder, 3692 struct intel_crtc_state *pipe_config, 3693 struct drm_connector_state *conn_state) 3694 { 3695 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3696 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3697 enum port port = encoder->port; 3698 int ret; 3699 3700 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 3701 pipe_config->cpu_transcoder = TRANSCODER_EDP; 3702 3703 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 3704 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 3705 } else { 3706 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 3707 } 3708 3709 if (ret) 3710 return ret; 3711 3712 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 3713 pipe_config->cpu_transcoder == TRANSCODER_EDP) 3714 pipe_config->pch_pfit.force_thru = 3715 pipe_config->pch_pfit.enabled || 3716 pipe_config->crc_enabled; 3717 3718 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3719 pipe_config->lane_lat_optim_mask = 3720 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 3721 3722 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 3723 3724 return 0; 3725 } 3726 3727 static bool mode_equal(const struct drm_display_mode *mode1, 3728 const struct drm_display_mode *mode2) 3729 { 3730 return drm_mode_match(mode1, mode2, 3731 DRM_MODE_MATCH_TIMINGS | 3732 DRM_MODE_MATCH_FLAGS | 3733 DRM_MODE_MATCH_3D_FLAGS) && 3734 mode1->clock == mode2->clock; /* we want an exact match */ 3735 } 3736 3737 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 3738 const struct intel_link_m_n *m_n_2) 3739 { 3740 return m_n_1->tu == m_n_2->tu && 3741 m_n_1->data_m == m_n_2->data_m && 3742 m_n_1->data_n == m_n_2->data_n && 3743 m_n_1->link_m == m_n_2->link_m && 3744 m_n_1->link_n == m_n_2->link_n; 3745 } 3746 3747 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 3748 const struct intel_crtc_state *crtc_state2) 3749 { 3750 return crtc_state1->hw.active && crtc_state2->hw.active && 3751 crtc_state1->output_types == crtc_state2->output_types && 3752 crtc_state1->output_format == crtc_state2->output_format && 3753 crtc_state1->lane_count == crtc_state2->lane_count && 3754 crtc_state1->port_clock == crtc_state2->port_clock && 3755 mode_equal(&crtc_state1->hw.adjusted_mode, 3756 &crtc_state2->hw.adjusted_mode) && 3757 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 3758 } 3759 3760 static u8 3761 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 3762 int tile_group_id) 3763 { 3764 struct drm_connector *connector; 3765 const struct drm_connector_state *conn_state; 3766 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 3767 struct intel_atomic_state *state = 3768 to_intel_atomic_state(ref_crtc_state->uapi.state); 3769 u8 transcoders = 0; 3770 int i; 3771 3772 /* 3773 * We don't enable port sync on BDW due to missing w/as and 3774 * due to not having adjusted the modeset sequence appropriately. 3775 */ 3776 if (DISPLAY_VER(dev_priv) < 9) 3777 return 0; 3778 3779 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 3780 return 0; 3781 3782 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 3783 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 3784 const struct intel_crtc_state *crtc_state; 3785 3786 if (!crtc) 3787 continue; 3788 3789 if (!connector->has_tile || 3790 connector->tile_group->id != 3791 tile_group_id) 3792 continue; 3793 crtc_state = intel_atomic_get_new_crtc_state(state, 3794 crtc); 3795 if (!crtcs_port_sync_compatible(ref_crtc_state, 3796 crtc_state)) 3797 continue; 3798 transcoders |= BIT(crtc_state->cpu_transcoder); 3799 } 3800 3801 return transcoders; 3802 } 3803 3804 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 3805 struct intel_crtc_state *crtc_state, 3806 struct drm_connector_state *conn_state) 3807 { 3808 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3809 struct drm_connector *connector = conn_state->connector; 3810 u8 port_sync_transcoders = 0; 3811 3812 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]", 3813 encoder->base.base.id, encoder->base.name, 3814 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 3815 3816 if (connector->has_tile) 3817 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 3818 connector->tile_group->id); 3819 3820 /* 3821 * EDP Transcoders cannot be ensalved 3822 * make them a master always when present 3823 */ 3824 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 3825 crtc_state->master_transcoder = TRANSCODER_EDP; 3826 else 3827 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 3828 3829 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 3830 crtc_state->master_transcoder = INVALID_TRANSCODER; 3831 crtc_state->sync_mode_slaves_mask = 3832 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 3833 } 3834 3835 return 0; 3836 } 3837 3838 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 3839 { 3840 struct drm_i915_private *i915 = to_i915(encoder->dev); 3841 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 3842 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 3843 3844 intel_dp_encoder_flush_work(encoder); 3845 if (intel_phy_is_tc(i915, phy)) 3846 intel_tc_port_flush_work(dig_port); 3847 intel_display_power_flush_work(i915); 3848 3849 drm_encoder_cleanup(encoder); 3850 kfree(dig_port->hdcp_port_data.streams); 3851 kfree(dig_port); 3852 } 3853 3854 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 3855 { 3856 struct drm_i915_private *i915 = to_i915(encoder->dev); 3857 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 3858 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 3859 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 3860 3861 intel_dp->reset_link_params = true; 3862 3863 intel_pps_encoder_reset(intel_dp); 3864 3865 if (intel_phy_is_tc(i915, phy)) 3866 intel_tc_port_init_mode(dig_port); 3867 } 3868 3869 static const struct drm_encoder_funcs intel_ddi_funcs = { 3870 .reset = intel_ddi_encoder_reset, 3871 .destroy = intel_ddi_encoder_destroy, 3872 }; 3873 3874 static struct intel_connector * 3875 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 3876 { 3877 struct intel_connector *connector; 3878 enum port port = dig_port->base.port; 3879 3880 connector = intel_connector_alloc(); 3881 if (!connector) 3882 return NULL; 3883 3884 dig_port->dp.output_reg = DDI_BUF_CTL(port); 3885 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 3886 dig_port->dp.set_link_train = intel_ddi_set_link_train; 3887 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 3888 3889 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 3890 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 3891 3892 if (!intel_dp_init_connector(dig_port, connector)) { 3893 kfree(connector); 3894 return NULL; 3895 } 3896 3897 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 3898 struct drm_device *dev = dig_port->base.base.dev; 3899 struct drm_privacy_screen *privacy_screen; 3900 3901 privacy_screen = drm_privacy_screen_get(dev->dev, NULL); 3902 if (!IS_ERR(privacy_screen)) { 3903 drm_connector_attach_privacy_screen_provider(&connector->base, 3904 privacy_screen); 3905 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 3906 drm_warn(dev, "Error getting privacy-screen\n"); 3907 } 3908 } 3909 3910 return connector; 3911 } 3912 3913 static int modeset_pipe(struct drm_crtc *crtc, 3914 struct drm_modeset_acquire_ctx *ctx) 3915 { 3916 struct drm_atomic_state *state; 3917 struct drm_crtc_state *crtc_state; 3918 int ret; 3919 3920 state = drm_atomic_state_alloc(crtc->dev); 3921 if (!state) 3922 return -ENOMEM; 3923 3924 state->acquire_ctx = ctx; 3925 3926 crtc_state = drm_atomic_get_crtc_state(state, crtc); 3927 if (IS_ERR(crtc_state)) { 3928 ret = PTR_ERR(crtc_state); 3929 goto out; 3930 } 3931 3932 crtc_state->connectors_changed = true; 3933 3934 ret = drm_atomic_commit(state); 3935 out: 3936 drm_atomic_state_put(state); 3937 3938 return ret; 3939 } 3940 3941 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 3942 struct drm_modeset_acquire_ctx *ctx) 3943 { 3944 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3945 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 3946 struct intel_connector *connector = hdmi->attached_connector; 3947 struct i2c_adapter *adapter = 3948 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 3949 struct drm_connector_state *conn_state; 3950 struct intel_crtc_state *crtc_state; 3951 struct intel_crtc *crtc; 3952 u8 config; 3953 int ret; 3954 3955 if (!connector || connector->base.status != connector_status_connected) 3956 return 0; 3957 3958 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 3959 ctx); 3960 if (ret) 3961 return ret; 3962 3963 conn_state = connector->base.state; 3964 3965 crtc = to_intel_crtc(conn_state->crtc); 3966 if (!crtc) 3967 return 0; 3968 3969 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 3970 if (ret) 3971 return ret; 3972 3973 crtc_state = to_intel_crtc_state(crtc->base.state); 3974 3975 drm_WARN_ON(&dev_priv->drm, 3976 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 3977 3978 if (!crtc_state->hw.active) 3979 return 0; 3980 3981 if (!crtc_state->hdmi_high_tmds_clock_ratio && 3982 !crtc_state->hdmi_scrambling) 3983 return 0; 3984 3985 if (conn_state->commit && 3986 !try_wait_for_completion(&conn_state->commit->hw_done)) 3987 return 0; 3988 3989 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 3990 if (ret < 0) { 3991 drm_err(&dev_priv->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", 3992 connector->base.base.id, connector->base.name, ret); 3993 return 0; 3994 } 3995 3996 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 3997 crtc_state->hdmi_high_tmds_clock_ratio && 3998 !!(config & SCDC_SCRAMBLING_ENABLE) == 3999 crtc_state->hdmi_scrambling) 4000 return 0; 4001 4002 /* 4003 * HDMI 2.0 says that one should not send scrambled data 4004 * prior to configuring the sink scrambling, and that 4005 * TMDS clock/data transmission should be suspended when 4006 * changing the TMDS clock rate in the sink. So let's 4007 * just do a full modeset here, even though some sinks 4008 * would be perfectly happy if were to just reconfigure 4009 * the SCDC settings on the fly. 4010 */ 4011 return modeset_pipe(&crtc->base, ctx); 4012 } 4013 4014 static enum intel_hotplug_state 4015 intel_ddi_hotplug(struct intel_encoder *encoder, 4016 struct intel_connector *connector) 4017 { 4018 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4019 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4020 struct intel_dp *intel_dp = &dig_port->dp; 4021 enum phy phy = intel_port_to_phy(i915, encoder->port); 4022 bool is_tc = intel_phy_is_tc(i915, phy); 4023 struct drm_modeset_acquire_ctx ctx; 4024 enum intel_hotplug_state state; 4025 int ret; 4026 4027 if (intel_dp->compliance.test_active && 4028 intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) { 4029 intel_dp_phy_test(encoder); 4030 /* just do the PHY test and nothing else */ 4031 return INTEL_HOTPLUG_UNCHANGED; 4032 } 4033 4034 state = intel_encoder_hotplug(encoder, connector); 4035 4036 drm_modeset_acquire_init(&ctx, 0); 4037 4038 for (;;) { 4039 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) 4040 ret = intel_hdmi_reset_link(encoder, &ctx); 4041 else 4042 ret = intel_dp_retrain_link(encoder, &ctx); 4043 4044 if (ret == -EDEADLK) { 4045 drm_modeset_backoff(&ctx); 4046 continue; 4047 } 4048 4049 break; 4050 } 4051 4052 drm_modeset_drop_locks(&ctx); 4053 drm_modeset_acquire_fini(&ctx); 4054 drm_WARN(encoder->base.dev, ret, 4055 "Acquiring modeset locks failed with %i\n", ret); 4056 4057 /* 4058 * Unpowered type-c dongles can take some time to boot and be 4059 * responsible, so here giving some time to those dongles to power up 4060 * and then retrying the probe. 4061 * 4062 * On many platforms the HDMI live state signal is known to be 4063 * unreliable, so we can't use it to detect if a sink is connected or 4064 * not. Instead we detect if it's connected based on whether we can 4065 * read the EDID or not. That in turn has a problem during disconnect, 4066 * since the HPD interrupt may be raised before the DDC lines get 4067 * disconnected (due to how the required length of DDC vs. HPD 4068 * connector pins are specified) and so we'll still be able to get a 4069 * valid EDID. To solve this schedule another detection cycle if this 4070 * time around we didn't detect any change in the sink's connection 4071 * status. 4072 * 4073 * Type-c connectors which get their HPD signal deasserted then 4074 * reasserted, without unplugging/replugging the sink from the 4075 * connector, introduce a delay until the AUX channel communication 4076 * becomes functional. Retry the detection for 5 seconds on type-c 4077 * connectors to account for this delay. 4078 */ 4079 if (state == INTEL_HOTPLUG_UNCHANGED && 4080 connector->hotplug_retries < (is_tc ? 5 : 1) && 4081 !dig_port->dp.is_mst) 4082 state = INTEL_HOTPLUG_RETRY; 4083 4084 return state; 4085 } 4086 4087 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4088 { 4089 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4090 u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin]; 4091 4092 return intel_de_read(dev_priv, SDEISR) & bit; 4093 } 4094 4095 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4096 { 4097 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4098 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4099 4100 return intel_de_read(dev_priv, DEISR) & bit; 4101 } 4102 4103 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4104 { 4105 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4106 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4107 4108 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; 4109 } 4110 4111 static struct intel_connector * 4112 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4113 { 4114 struct intel_connector *connector; 4115 enum port port = dig_port->base.port; 4116 4117 connector = intel_connector_alloc(); 4118 if (!connector) 4119 return NULL; 4120 4121 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4122 intel_hdmi_init_connector(dig_port, connector); 4123 4124 return connector; 4125 } 4126 4127 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4128 { 4129 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4130 4131 if (dig_port->base.port != PORT_A) 4132 return false; 4133 4134 if (dig_port->saved_port_bits & DDI_A_4_LANES) 4135 return false; 4136 4137 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4138 * supported configuration 4139 */ 4140 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4141 return true; 4142 4143 return false; 4144 } 4145 4146 static int 4147 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4148 { 4149 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4150 enum port port = dig_port->base.port; 4151 int max_lanes = 4; 4152 4153 if (DISPLAY_VER(dev_priv) >= 11) 4154 return max_lanes; 4155 4156 if (port == PORT_A || port == PORT_E) { 4157 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4158 max_lanes = port == PORT_A ? 4 : 0; 4159 else 4160 /* Both A and E share 2 lanes */ 4161 max_lanes = 2; 4162 } 4163 4164 /* 4165 * Some BIOS might fail to set this bit on port A if eDP 4166 * wasn't lit up at boot. Force this bit set when needed 4167 * so we use the proper lane count for our calculations. 4168 */ 4169 if (intel_ddi_a_force_4_lanes(dig_port)) { 4170 drm_dbg_kms(&dev_priv->drm, 4171 "Forcing DDI_A_4_LANES for port A\n"); 4172 dig_port->saved_port_bits |= DDI_A_4_LANES; 4173 max_lanes = 4; 4174 } 4175 4176 return max_lanes; 4177 } 4178 4179 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv, 4180 enum port port) 4181 { 4182 if (port >= PORT_D_XELPD) 4183 return HPD_PORT_D + port - PORT_D_XELPD; 4184 else if (port >= PORT_TC1) 4185 return HPD_PORT_TC1 + port - PORT_TC1; 4186 else 4187 return HPD_PORT_A + port - PORT_A; 4188 } 4189 4190 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, 4191 enum port port) 4192 { 4193 if (port >= PORT_TC1) 4194 return HPD_PORT_C + port - PORT_TC1; 4195 else 4196 return HPD_PORT_A + port - PORT_A; 4197 } 4198 4199 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, 4200 enum port port) 4201 { 4202 if (port >= PORT_TC1) 4203 return HPD_PORT_TC1 + port - PORT_TC1; 4204 else 4205 return HPD_PORT_A + port - PORT_A; 4206 } 4207 4208 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, 4209 enum port port) 4210 { 4211 if (HAS_PCH_TGP(dev_priv)) 4212 return tgl_hpd_pin(dev_priv, port); 4213 4214 if (port >= PORT_TC1) 4215 return HPD_PORT_C + port - PORT_TC1; 4216 else 4217 return HPD_PORT_A + port - PORT_A; 4218 } 4219 4220 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, 4221 enum port port) 4222 { 4223 if (port >= PORT_C) 4224 return HPD_PORT_TC1 + port - PORT_C; 4225 else 4226 return HPD_PORT_A + port - PORT_A; 4227 } 4228 4229 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, 4230 enum port port) 4231 { 4232 if (port == PORT_D) 4233 return HPD_PORT_A; 4234 4235 if (HAS_PCH_TGP(dev_priv)) 4236 return icl_hpd_pin(dev_priv, port); 4237 4238 return HPD_PORT_A + port - PORT_A; 4239 } 4240 4241 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) 4242 { 4243 if (HAS_PCH_TGP(dev_priv)) 4244 return icl_hpd_pin(dev_priv, port); 4245 4246 return HPD_PORT_A + port - PORT_A; 4247 } 4248 4249 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port) 4250 { 4251 if (DISPLAY_VER(i915) >= 12) 4252 return port >= PORT_TC1; 4253 else if (DISPLAY_VER(i915) >= 11) 4254 return port >= PORT_C; 4255 else 4256 return false; 4257 } 4258 4259 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 4260 { 4261 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4262 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4263 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4264 enum phy phy = intel_port_to_phy(i915, encoder->port); 4265 4266 intel_dp_encoder_suspend(encoder); 4267 4268 if (!intel_phy_is_tc(i915, phy)) 4269 return; 4270 4271 intel_tc_port_flush_work(dig_port); 4272 } 4273 4274 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 4275 { 4276 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4277 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4278 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4279 enum phy phy = intel_port_to_phy(i915, encoder->port); 4280 4281 intel_dp_encoder_shutdown(encoder); 4282 intel_hdmi_encoder_shutdown(encoder); 4283 4284 if (!intel_phy_is_tc(i915, phy)) 4285 return; 4286 4287 intel_tc_port_flush_work(dig_port); 4288 } 4289 4290 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 4291 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 4292 4293 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 4294 { 4295 struct intel_digital_port *dig_port; 4296 struct intel_encoder *encoder; 4297 const struct intel_bios_encoder_data *devdata; 4298 bool init_hdmi, init_dp; 4299 enum phy phy = intel_port_to_phy(dev_priv, port); 4300 4301 /* 4302 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 4303 * have taken over some of the PHYs and made them unavailable to the 4304 * driver. In that case we should skip initializing the corresponding 4305 * outputs. 4306 */ 4307 if (intel_hti_uses_phy(dev_priv, phy)) { 4308 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", 4309 port_name(port), phy_name(phy)); 4310 return; 4311 } 4312 4313 devdata = intel_bios_encoder_data_lookup(dev_priv, port); 4314 if (!devdata) { 4315 drm_dbg_kms(&dev_priv->drm, 4316 "VBT says port %c is not present\n", 4317 port_name(port)); 4318 return; 4319 } 4320 4321 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 4322 intel_bios_encoder_supports_hdmi(devdata); 4323 init_dp = intel_bios_encoder_supports_dp(devdata); 4324 4325 if (intel_bios_encoder_is_lspcon(devdata)) { 4326 /* 4327 * Lspcon device needs to be driven with DP connector 4328 * with special detection sequence. So make sure DP 4329 * is initialized before lspcon. 4330 */ 4331 init_dp = true; 4332 init_hdmi = false; 4333 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", 4334 port_name(port)); 4335 } 4336 4337 if (!init_dp && !init_hdmi) { 4338 drm_dbg_kms(&dev_priv->drm, 4339 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 4340 port_name(port)); 4341 return; 4342 } 4343 4344 if (intel_phy_is_snps(dev_priv, phy) && 4345 dev_priv->display.snps.phy_failed_calibration & BIT(phy)) { 4346 drm_dbg_kms(&dev_priv->drm, 4347 "SNPS PHY %c failed to calibrate, proceeding anyway\n", 4348 phy_name(phy)); 4349 } 4350 4351 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 4352 if (!dig_port) 4353 return; 4354 4355 encoder = &dig_port->base; 4356 encoder->devdata = devdata; 4357 4358 if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) { 4359 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4360 DRM_MODE_ENCODER_TMDS, 4361 "DDI %c/PHY %c", 4362 port_name(port - PORT_D_XELPD + PORT_D), 4363 phy_name(phy)); 4364 } else if (DISPLAY_VER(dev_priv) >= 12) { 4365 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4366 4367 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4368 DRM_MODE_ENCODER_TMDS, 4369 "DDI %s%c/PHY %s%c", 4370 port >= PORT_TC1 ? "TC" : "", 4371 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 4372 tc_port != TC_PORT_NONE ? "TC" : "", 4373 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4374 } else if (DISPLAY_VER(dev_priv) >= 11) { 4375 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4376 4377 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4378 DRM_MODE_ENCODER_TMDS, 4379 "DDI %c%s/PHY %s%c", 4380 port_name(port), 4381 port >= PORT_C ? " (TC)" : "", 4382 tc_port != TC_PORT_NONE ? "TC" : "", 4383 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4384 } else { 4385 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4386 DRM_MODE_ENCODER_TMDS, 4387 "DDI %c/PHY %c", port_name(port), phy_name(phy)); 4388 } 4389 4390 mutex_init(&dig_port->hdcp_mutex); 4391 dig_port->num_hdcp_streams = 0; 4392 4393 encoder->hotplug = intel_ddi_hotplug; 4394 encoder->compute_output_type = intel_ddi_compute_output_type; 4395 encoder->compute_config = intel_ddi_compute_config; 4396 encoder->compute_config_late = intel_ddi_compute_config_late; 4397 encoder->enable = intel_enable_ddi; 4398 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 4399 encoder->pre_enable = intel_ddi_pre_enable; 4400 encoder->disable = intel_disable_ddi; 4401 encoder->post_disable = intel_ddi_post_disable; 4402 encoder->update_pipe = intel_ddi_update_pipe; 4403 encoder->get_hw_state = intel_ddi_get_hw_state; 4404 encoder->sync_state = intel_ddi_sync_state; 4405 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 4406 encoder->suspend = intel_ddi_encoder_suspend; 4407 encoder->shutdown = intel_ddi_encoder_shutdown; 4408 encoder->get_power_domains = intel_ddi_get_power_domains; 4409 4410 encoder->type = INTEL_OUTPUT_DDI; 4411 encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port); 4412 encoder->port = port; 4413 encoder->cloneable = 0; 4414 encoder->pipe_mask = ~0; 4415 4416 if (IS_DG2(dev_priv)) { 4417 encoder->enable_clock = intel_mpllb_enable; 4418 encoder->disable_clock = intel_mpllb_disable; 4419 encoder->get_config = dg2_ddi_get_config; 4420 } else if (IS_ALDERLAKE_S(dev_priv)) { 4421 encoder->enable_clock = adls_ddi_enable_clock; 4422 encoder->disable_clock = adls_ddi_disable_clock; 4423 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 4424 encoder->get_config = adls_ddi_get_config; 4425 } else if (IS_ROCKETLAKE(dev_priv)) { 4426 encoder->enable_clock = rkl_ddi_enable_clock; 4427 encoder->disable_clock = rkl_ddi_disable_clock; 4428 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 4429 encoder->get_config = rkl_ddi_get_config; 4430 } else if (IS_DG1(dev_priv)) { 4431 encoder->enable_clock = dg1_ddi_enable_clock; 4432 encoder->disable_clock = dg1_ddi_disable_clock; 4433 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 4434 encoder->get_config = dg1_ddi_get_config; 4435 } else if (IS_JSL_EHL(dev_priv)) { 4436 if (intel_ddi_is_tc(dev_priv, port)) { 4437 encoder->enable_clock = jsl_ddi_tc_enable_clock; 4438 encoder->disable_clock = jsl_ddi_tc_disable_clock; 4439 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 4440 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 4441 encoder->get_config = icl_ddi_combo_get_config; 4442 } else { 4443 encoder->enable_clock = icl_ddi_combo_enable_clock; 4444 encoder->disable_clock = icl_ddi_combo_disable_clock; 4445 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 4446 encoder->get_config = icl_ddi_combo_get_config; 4447 } 4448 } else if (DISPLAY_VER(dev_priv) >= 11) { 4449 if (intel_ddi_is_tc(dev_priv, port)) { 4450 encoder->enable_clock = icl_ddi_tc_enable_clock; 4451 encoder->disable_clock = icl_ddi_tc_disable_clock; 4452 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 4453 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 4454 encoder->get_config = icl_ddi_tc_get_config; 4455 } else { 4456 encoder->enable_clock = icl_ddi_combo_enable_clock; 4457 encoder->disable_clock = icl_ddi_combo_disable_clock; 4458 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 4459 encoder->get_config = icl_ddi_combo_get_config; 4460 } 4461 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 4462 /* BXT/GLK have fixed PLL->port mapping */ 4463 encoder->get_config = bxt_ddi_get_config; 4464 } else if (DISPLAY_VER(dev_priv) == 9) { 4465 encoder->enable_clock = skl_ddi_enable_clock; 4466 encoder->disable_clock = skl_ddi_disable_clock; 4467 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 4468 encoder->get_config = skl_ddi_get_config; 4469 } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 4470 encoder->enable_clock = hsw_ddi_enable_clock; 4471 encoder->disable_clock = hsw_ddi_disable_clock; 4472 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 4473 encoder->get_config = hsw_ddi_get_config; 4474 } 4475 4476 if (IS_DG2(dev_priv)) { 4477 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 4478 } else if (DISPLAY_VER(dev_priv) >= 12) { 4479 if (intel_phy_is_combo(dev_priv, phy)) 4480 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 4481 else 4482 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 4483 } else if (DISPLAY_VER(dev_priv) >= 11) { 4484 if (intel_phy_is_combo(dev_priv, phy)) 4485 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 4486 else 4487 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 4488 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 4489 encoder->set_signal_levels = bxt_ddi_phy_set_signal_levels; 4490 } else { 4491 encoder->set_signal_levels = hsw_set_signal_levels; 4492 } 4493 4494 intel_ddi_buf_trans_init(encoder); 4495 4496 if (DISPLAY_VER(dev_priv) >= 13) 4497 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port); 4498 else if (IS_DG1(dev_priv)) 4499 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); 4500 else if (IS_ROCKETLAKE(dev_priv)) 4501 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); 4502 else if (DISPLAY_VER(dev_priv) >= 12) 4503 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); 4504 else if (IS_JSL_EHL(dev_priv)) 4505 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); 4506 else if (DISPLAY_VER(dev_priv) == 11) 4507 encoder->hpd_pin = icl_hpd_pin(dev_priv, port); 4508 else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 4509 encoder->hpd_pin = skl_hpd_pin(dev_priv, port); 4510 else 4511 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 4512 4513 if (DISPLAY_VER(dev_priv) >= 11) 4514 dig_port->saved_port_bits = 4515 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 4516 & DDI_BUF_PORT_REVERSAL; 4517 else 4518 dig_port->saved_port_bits = 4519 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 4520 & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 4521 4522 if (intel_bios_encoder_lane_reversal(devdata)) 4523 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL; 4524 4525 dig_port->dp.output_reg = INVALID_MMIO_REG; 4526 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 4527 dig_port->aux_ch = intel_dp_aux_ch(encoder); 4528 4529 if (intel_phy_is_tc(dev_priv, phy)) { 4530 bool is_legacy = 4531 !intel_bios_encoder_supports_typec_usb(devdata) && 4532 !intel_bios_encoder_supports_tbt(devdata); 4533 4534 if (!is_legacy && init_hdmi) { 4535 is_legacy = !init_dp; 4536 4537 drm_dbg_kms(&dev_priv->drm, 4538 "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n", 4539 port_name(port), 4540 str_yes_no(init_dp), 4541 is_legacy ? "legacy" : "non-legacy"); 4542 } 4543 4544 intel_tc_port_init(dig_port, is_legacy); 4545 4546 encoder->update_prepare = intel_ddi_update_prepare; 4547 encoder->update_complete = intel_ddi_update_complete; 4548 } 4549 4550 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 4551 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(dev_priv, port); 4552 4553 if (DISPLAY_VER(dev_priv) >= 11) { 4554 if (intel_phy_is_tc(dev_priv, phy)) 4555 dig_port->connected = intel_tc_port_connected; 4556 else 4557 dig_port->connected = lpt_digital_port_connected; 4558 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 4559 dig_port->connected = bdw_digital_port_connected; 4560 } else if (DISPLAY_VER(dev_priv) == 9) { 4561 dig_port->connected = lpt_digital_port_connected; 4562 } else if (IS_BROADWELL(dev_priv)) { 4563 if (port == PORT_A) 4564 dig_port->connected = bdw_digital_port_connected; 4565 else 4566 dig_port->connected = lpt_digital_port_connected; 4567 } else if (IS_HASWELL(dev_priv)) { 4568 if (port == PORT_A) 4569 dig_port->connected = hsw_digital_port_connected; 4570 else 4571 dig_port->connected = lpt_digital_port_connected; 4572 } 4573 4574 intel_infoframe_init(dig_port); 4575 4576 if (init_dp) { 4577 if (!intel_ddi_init_dp_connector(dig_port)) 4578 goto err; 4579 4580 dig_port->hpd_pulse = intel_dp_hpd_pulse; 4581 4582 if (dig_port->dp.mso_link_count) 4583 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv); 4584 } 4585 4586 /* 4587 * In theory we don't need the encoder->type check, 4588 * but leave it just in case we have some really bad VBTs... 4589 */ 4590 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 4591 if (!intel_ddi_init_hdmi_connector(dig_port)) 4592 goto err; 4593 } 4594 4595 return; 4596 4597 err: 4598 drm_encoder_cleanup(&encoder->base); 4599 kfree(dig_port); 4600 } 4601