1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <linux/string_helpers.h> 29 30 #include <drm/display/drm_scdc_helper.h> 31 #include <drm/drm_privacy_screen_consumer.h> 32 33 #include "i915_drv.h" 34 #include "intel_audio.h" 35 #include "intel_audio_regs.h" 36 #include "intel_backlight.h" 37 #include "intel_combo_phy.h" 38 #include "intel_combo_phy_regs.h" 39 #include "intel_connector.h" 40 #include "intel_crtc.h" 41 #include "intel_ddi.h" 42 #include "intel_ddi_buf_trans.h" 43 #include "intel_de.h" 44 #include "intel_display_power.h" 45 #include "intel_display_types.h" 46 #include "intel_dkl_phy.h" 47 #include "intel_dkl_phy_regs.h" 48 #include "intel_dp.h" 49 #include "intel_dp_link_training.h" 50 #include "intel_dp_mst.h" 51 #include "intel_dpio_phy.h" 52 #include "intel_dsi.h" 53 #include "intel_fdi.h" 54 #include "intel_fifo_underrun.h" 55 #include "intel_gmbus.h" 56 #include "intel_hdcp.h" 57 #include "intel_hdmi.h" 58 #include "intel_hotplug.h" 59 #include "intel_lspcon.h" 60 #include "intel_mg_phy_regs.h" 61 #include "intel_pps.h" 62 #include "intel_psr.h" 63 #include "intel_quirks.h" 64 #include "intel_snps_phy.h" 65 #include "intel_sprite.h" 66 #include "intel_tc.h" 67 #include "intel_vdsc.h" 68 #include "intel_vrr.h" 69 #include "skl_scaler.h" 70 #include "skl_universal_plane.h" 71 72 static const u8 index_to_dp_signal_levels[] = { 73 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 74 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 75 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 76 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 77 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 78 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 79 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 80 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 81 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 82 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 83 }; 84 85 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 86 const struct intel_ddi_buf_trans *trans) 87 { 88 int level; 89 90 level = intel_bios_hdmi_level_shift(encoder); 91 if (level < 0) 92 level = trans->hdmi_default_entry; 93 94 return level; 95 } 96 97 static bool has_buf_trans_select(struct drm_i915_private *i915) 98 { 99 return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915); 100 } 101 102 static bool has_iboost(struct drm_i915_private *i915) 103 { 104 return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915); 105 } 106 107 /* 108 * Starting with Haswell, DDI port buffers must be programmed with correct 109 * values in advance. This function programs the correct values for 110 * DP/eDP/FDI use cases. 111 */ 112 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 113 const struct intel_crtc_state *crtc_state) 114 { 115 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 116 u32 iboost_bit = 0; 117 int i, n_entries; 118 enum port port = encoder->port; 119 const struct intel_ddi_buf_trans *trans; 120 121 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 122 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 123 return; 124 125 /* If we're boosting the current, set bit 31 of trans1 */ 126 if (has_iboost(dev_priv) && 127 intel_bios_encoder_dp_boost_level(encoder->devdata)) 128 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 129 130 for (i = 0; i < n_entries; i++) { 131 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 132 trans->entries[i].hsw.trans1 | iboost_bit); 133 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 134 trans->entries[i].hsw.trans2); 135 } 136 } 137 138 /* 139 * Starting with Haswell, DDI port buffers must be programmed with correct 140 * values in advance. This function programs the correct values for 141 * HDMI/DVI use cases. 142 */ 143 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 144 const struct intel_crtc_state *crtc_state) 145 { 146 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 147 int level = intel_ddi_level(encoder, crtc_state, 0); 148 u32 iboost_bit = 0; 149 int n_entries; 150 enum port port = encoder->port; 151 const struct intel_ddi_buf_trans *trans; 152 153 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 154 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 155 return; 156 157 /* If we're boosting the current, set bit 31 of trans1 */ 158 if (has_iboost(dev_priv) && 159 intel_bios_encoder_hdmi_boost_level(encoder->devdata)) 160 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 161 162 /* Entry 9 is for HDMI: */ 163 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 164 trans->entries[level].hsw.trans1 | iboost_bit); 165 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 166 trans->entries[level].hsw.trans2); 167 } 168 169 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 170 enum port port) 171 { 172 if (IS_BROXTON(dev_priv)) { 173 udelay(16); 174 return; 175 } 176 177 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 178 DDI_BUF_IS_IDLE), 8)) 179 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", 180 port_name(port)); 181 } 182 183 static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, 184 enum port port) 185 { 186 int ret; 187 188 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ 189 if (DISPLAY_VER(dev_priv) < 10) { 190 usleep_range(518, 1000); 191 return; 192 } 193 194 ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 195 DDI_BUF_IS_IDLE), IS_DG2(dev_priv) ? 1200 : 500, 10, 10); 196 197 if (ret) 198 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", 199 port_name(port)); 200 } 201 202 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 203 { 204 switch (pll->info->id) { 205 case DPLL_ID_WRPLL1: 206 return PORT_CLK_SEL_WRPLL1; 207 case DPLL_ID_WRPLL2: 208 return PORT_CLK_SEL_WRPLL2; 209 case DPLL_ID_SPLL: 210 return PORT_CLK_SEL_SPLL; 211 case DPLL_ID_LCPLL_810: 212 return PORT_CLK_SEL_LCPLL_810; 213 case DPLL_ID_LCPLL_1350: 214 return PORT_CLK_SEL_LCPLL_1350; 215 case DPLL_ID_LCPLL_2700: 216 return PORT_CLK_SEL_LCPLL_2700; 217 default: 218 MISSING_CASE(pll->info->id); 219 return PORT_CLK_SEL_NONE; 220 } 221 } 222 223 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 224 const struct intel_crtc_state *crtc_state) 225 { 226 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 227 int clock = crtc_state->port_clock; 228 const enum intel_dpll_id id = pll->info->id; 229 230 switch (id) { 231 default: 232 /* 233 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 234 * here, so do warn if this get passed in 235 */ 236 MISSING_CASE(id); 237 return DDI_CLK_SEL_NONE; 238 case DPLL_ID_ICL_TBTPLL: 239 switch (clock) { 240 case 162000: 241 return DDI_CLK_SEL_TBT_162; 242 case 270000: 243 return DDI_CLK_SEL_TBT_270; 244 case 540000: 245 return DDI_CLK_SEL_TBT_540; 246 case 810000: 247 return DDI_CLK_SEL_TBT_810; 248 default: 249 MISSING_CASE(clock); 250 return DDI_CLK_SEL_NONE; 251 } 252 case DPLL_ID_ICL_MGPLL1: 253 case DPLL_ID_ICL_MGPLL2: 254 case DPLL_ID_ICL_MGPLL3: 255 case DPLL_ID_ICL_MGPLL4: 256 case DPLL_ID_TGL_MGPLL5: 257 case DPLL_ID_TGL_MGPLL6: 258 return DDI_CLK_SEL_MG; 259 } 260 } 261 262 static u32 ddi_buf_phy_link_rate(int port_clock) 263 { 264 switch (port_clock) { 265 case 162000: 266 return DDI_BUF_PHY_LINK_RATE(0); 267 case 216000: 268 return DDI_BUF_PHY_LINK_RATE(4); 269 case 243000: 270 return DDI_BUF_PHY_LINK_RATE(5); 271 case 270000: 272 return DDI_BUF_PHY_LINK_RATE(1); 273 case 324000: 274 return DDI_BUF_PHY_LINK_RATE(6); 275 case 432000: 276 return DDI_BUF_PHY_LINK_RATE(7); 277 case 540000: 278 return DDI_BUF_PHY_LINK_RATE(2); 279 case 810000: 280 return DDI_BUF_PHY_LINK_RATE(3); 281 default: 282 MISSING_CASE(port_clock); 283 return DDI_BUF_PHY_LINK_RATE(0); 284 } 285 } 286 287 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 288 const struct intel_crtc_state *crtc_state) 289 { 290 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 291 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 292 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 293 enum phy phy = intel_port_to_phy(i915, encoder->port); 294 295 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 296 intel_dp->DP = dig_port->saved_port_bits | 297 DDI_PORT_WIDTH(crtc_state->lane_count) | 298 DDI_BUF_TRANS_SELECT(0); 299 300 if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) { 301 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 302 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 303 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 304 } 305 } 306 307 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 308 enum port port) 309 { 310 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 311 312 switch (val) { 313 case DDI_CLK_SEL_NONE: 314 return 0; 315 case DDI_CLK_SEL_TBT_162: 316 return 162000; 317 case DDI_CLK_SEL_TBT_270: 318 return 270000; 319 case DDI_CLK_SEL_TBT_540: 320 return 540000; 321 case DDI_CLK_SEL_TBT_810: 322 return 810000; 323 default: 324 MISSING_CASE(val); 325 return 0; 326 } 327 } 328 329 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 330 { 331 /* CRT dotclock is determined via other means */ 332 if (pipe_config->has_pch_encoder) 333 return; 334 335 pipe_config->hw.adjusted_mode.crtc_clock = 336 intel_crtc_dotclock(pipe_config); 337 } 338 339 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 340 const struct drm_connector_state *conn_state) 341 { 342 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 343 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 344 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 345 u32 temp; 346 347 if (!intel_crtc_has_dp_encoder(crtc_state)) 348 return; 349 350 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 351 352 temp = DP_MSA_MISC_SYNC_CLOCK; 353 354 switch (crtc_state->pipe_bpp) { 355 case 18: 356 temp |= DP_MSA_MISC_6_BPC; 357 break; 358 case 24: 359 temp |= DP_MSA_MISC_8_BPC; 360 break; 361 case 30: 362 temp |= DP_MSA_MISC_10_BPC; 363 break; 364 case 36: 365 temp |= DP_MSA_MISC_12_BPC; 366 break; 367 default: 368 MISSING_CASE(crtc_state->pipe_bpp); 369 break; 370 } 371 372 /* nonsense combination */ 373 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 374 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 375 376 if (crtc_state->limited_color_range) 377 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 378 379 /* 380 * As per DP 1.2 spec section 2.3.4.3 while sending 381 * YCBCR 444 signals we should program MSA MISC1/0 fields with 382 * colorspace information. 383 */ 384 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 385 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 386 387 /* 388 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 389 * of Color Encoding Format and Content Color Gamut] while sending 390 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 391 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 392 */ 393 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 394 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 395 396 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp); 397 } 398 399 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 400 { 401 if (master_transcoder == TRANSCODER_EDP) 402 return 0; 403 else 404 return master_transcoder + 1; 405 } 406 407 static void 408 intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder, 409 const struct intel_crtc_state *crtc_state) 410 { 411 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 412 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 413 u32 val = 0; 414 415 if (intel_dp_is_uhbr(crtc_state)) 416 val = TRANS_DP2_128B132B_CHANNEL_CODING; 417 418 intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val); 419 } 420 421 /* 422 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 423 * 424 * Only intended to be used by intel_ddi_enable_transcoder_func() and 425 * intel_ddi_config_transcoder_func(). 426 */ 427 static u32 428 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 429 const struct intel_crtc_state *crtc_state) 430 { 431 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 432 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 433 enum pipe pipe = crtc->pipe; 434 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 435 enum port port = encoder->port; 436 u32 temp; 437 438 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 439 temp = TRANS_DDI_FUNC_ENABLE; 440 if (DISPLAY_VER(dev_priv) >= 12) 441 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 442 else 443 temp |= TRANS_DDI_SELECT_PORT(port); 444 445 switch (crtc_state->pipe_bpp) { 446 default: 447 MISSING_CASE(crtc_state->pipe_bpp); 448 fallthrough; 449 case 18: 450 temp |= TRANS_DDI_BPC_6; 451 break; 452 case 24: 453 temp |= TRANS_DDI_BPC_8; 454 break; 455 case 30: 456 temp |= TRANS_DDI_BPC_10; 457 break; 458 case 36: 459 temp |= TRANS_DDI_BPC_12; 460 break; 461 } 462 463 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 464 temp |= TRANS_DDI_PVSYNC; 465 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 466 temp |= TRANS_DDI_PHSYNC; 467 468 if (cpu_transcoder == TRANSCODER_EDP) { 469 switch (pipe) { 470 default: 471 MISSING_CASE(pipe); 472 fallthrough; 473 case PIPE_A: 474 /* On Haswell, can only use the always-on power well for 475 * eDP when not using the panel fitter, and when not 476 * using motion blur mitigation (which we don't 477 * support). */ 478 if (crtc_state->pch_pfit.force_thru) 479 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 480 else 481 temp |= TRANS_DDI_EDP_INPUT_A_ON; 482 break; 483 case PIPE_B: 484 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 485 break; 486 case PIPE_C: 487 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 488 break; 489 } 490 } 491 492 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 493 if (crtc_state->has_hdmi_sink) 494 temp |= TRANS_DDI_MODE_SELECT_HDMI; 495 else 496 temp |= TRANS_DDI_MODE_SELECT_DVI; 497 498 if (crtc_state->hdmi_scrambling) 499 temp |= TRANS_DDI_HDMI_SCRAMBLING; 500 if (crtc_state->hdmi_high_tmds_clock_ratio) 501 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 502 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 503 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 504 temp |= (crtc_state->fdi_lanes - 1) << 1; 505 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 506 if (intel_dp_is_uhbr(crtc_state)) 507 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 508 else 509 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 510 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 511 512 if (DISPLAY_VER(dev_priv) >= 12) { 513 enum transcoder master; 514 515 master = crtc_state->mst_master_transcoder; 516 drm_WARN_ON(&dev_priv->drm, 517 master == INVALID_TRANSCODER); 518 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 519 } 520 } else { 521 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 522 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 523 } 524 525 if (IS_DISPLAY_VER(dev_priv, 8, 10) && 526 crtc_state->master_transcoder != INVALID_TRANSCODER) { 527 u8 master_select = 528 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 529 530 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 531 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 532 } 533 534 return temp; 535 } 536 537 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 538 const struct intel_crtc_state *crtc_state) 539 { 540 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 541 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 542 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 543 544 if (DISPLAY_VER(dev_priv) >= 11) { 545 enum transcoder master_transcoder = crtc_state->master_transcoder; 546 u32 ctl2 = 0; 547 548 if (master_transcoder != INVALID_TRANSCODER) { 549 u8 master_select = 550 bdw_trans_port_sync_master_select(master_transcoder); 551 552 ctl2 |= PORT_SYNC_MODE_ENABLE | 553 PORT_SYNC_MODE_MASTER_SELECT(master_select); 554 } 555 556 intel_de_write(dev_priv, 557 TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2); 558 } 559 560 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 561 intel_ddi_transcoder_func_reg_val_get(encoder, 562 crtc_state)); 563 } 564 565 /* 566 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 567 * bit. 568 */ 569 static void 570 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 571 const struct intel_crtc_state *crtc_state) 572 { 573 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 574 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 575 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 576 u32 ctl; 577 578 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 579 ctl &= ~TRANS_DDI_FUNC_ENABLE; 580 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 581 } 582 583 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 584 { 585 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 586 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 587 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 588 u32 ctl; 589 590 if (DISPLAY_VER(dev_priv) >= 11) 591 intel_de_write(dev_priv, 592 TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0); 593 594 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 595 596 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 597 598 ctl &= ~TRANS_DDI_FUNC_ENABLE; 599 600 if (IS_DISPLAY_VER(dev_priv, 8, 10)) 601 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 602 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 603 604 if (DISPLAY_VER(dev_priv) >= 12) { 605 if (!intel_dp_mst_is_master_trans(crtc_state)) { 606 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 607 TRANS_DDI_MODE_SELECT_MASK); 608 } 609 } else { 610 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 611 } 612 613 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 614 615 if (intel_has_quirk(dev_priv, QUIRK_INCREASE_DDI_DISABLED_TIME) && 616 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 617 drm_dbg_kms(&dev_priv->drm, 618 "Quirk Increase DDI disabled time\n"); 619 /* Quirk time at 100ms for reliable operation */ 620 msleep(100); 621 } 622 } 623 624 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 625 enum transcoder cpu_transcoder, 626 bool enable, u32 hdcp_mask) 627 { 628 struct drm_device *dev = intel_encoder->base.dev; 629 struct drm_i915_private *dev_priv = to_i915(dev); 630 intel_wakeref_t wakeref; 631 int ret = 0; 632 u32 tmp; 633 634 wakeref = intel_display_power_get_if_enabled(dev_priv, 635 intel_encoder->power_domain); 636 if (drm_WARN_ON(dev, !wakeref)) 637 return -ENXIO; 638 639 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 640 if (enable) 641 tmp |= hdcp_mask; 642 else 643 tmp &= ~hdcp_mask; 644 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp); 645 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 646 return ret; 647 } 648 649 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 650 { 651 struct drm_device *dev = intel_connector->base.dev; 652 struct drm_i915_private *dev_priv = to_i915(dev); 653 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 654 int type = intel_connector->base.connector_type; 655 enum port port = encoder->port; 656 enum transcoder cpu_transcoder; 657 intel_wakeref_t wakeref; 658 enum pipe pipe = 0; 659 u32 tmp; 660 bool ret; 661 662 wakeref = intel_display_power_get_if_enabled(dev_priv, 663 encoder->power_domain); 664 if (!wakeref) 665 return false; 666 667 if (!encoder->get_hw_state(encoder, &pipe)) { 668 ret = false; 669 goto out; 670 } 671 672 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 673 cpu_transcoder = TRANSCODER_EDP; 674 else 675 cpu_transcoder = (enum transcoder) pipe; 676 677 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 678 679 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 680 case TRANS_DDI_MODE_SELECT_HDMI: 681 case TRANS_DDI_MODE_SELECT_DVI: 682 ret = type == DRM_MODE_CONNECTOR_HDMIA; 683 break; 684 685 case TRANS_DDI_MODE_SELECT_DP_SST: 686 ret = type == DRM_MODE_CONNECTOR_eDP || 687 type == DRM_MODE_CONNECTOR_DisplayPort; 688 break; 689 690 case TRANS_DDI_MODE_SELECT_DP_MST: 691 /* if the transcoder is in MST state then 692 * connector isn't connected */ 693 ret = false; 694 break; 695 696 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 697 if (HAS_DP20(dev_priv)) 698 /* 128b/132b */ 699 ret = false; 700 else 701 /* FDI */ 702 ret = type == DRM_MODE_CONNECTOR_VGA; 703 break; 704 705 default: 706 ret = false; 707 break; 708 } 709 710 out: 711 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 712 713 return ret; 714 } 715 716 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 717 u8 *pipe_mask, bool *is_dp_mst) 718 { 719 struct drm_device *dev = encoder->base.dev; 720 struct drm_i915_private *dev_priv = to_i915(dev); 721 enum port port = encoder->port; 722 intel_wakeref_t wakeref; 723 enum pipe p; 724 u32 tmp; 725 u8 mst_pipe_mask; 726 727 *pipe_mask = 0; 728 *is_dp_mst = false; 729 730 wakeref = intel_display_power_get_if_enabled(dev_priv, 731 encoder->power_domain); 732 if (!wakeref) 733 return; 734 735 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 736 if (!(tmp & DDI_BUF_CTL_ENABLE)) 737 goto out; 738 739 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { 740 tmp = intel_de_read(dev_priv, 741 TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 742 743 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 744 default: 745 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 746 fallthrough; 747 case TRANS_DDI_EDP_INPUT_A_ON: 748 case TRANS_DDI_EDP_INPUT_A_ONOFF: 749 *pipe_mask = BIT(PIPE_A); 750 break; 751 case TRANS_DDI_EDP_INPUT_B_ONOFF: 752 *pipe_mask = BIT(PIPE_B); 753 break; 754 case TRANS_DDI_EDP_INPUT_C_ONOFF: 755 *pipe_mask = BIT(PIPE_C); 756 break; 757 } 758 759 goto out; 760 } 761 762 mst_pipe_mask = 0; 763 for_each_pipe(dev_priv, p) { 764 enum transcoder cpu_transcoder = (enum transcoder)p; 765 unsigned int port_mask, ddi_select; 766 intel_wakeref_t trans_wakeref; 767 768 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 769 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 770 if (!trans_wakeref) 771 continue; 772 773 if (DISPLAY_VER(dev_priv) >= 12) { 774 port_mask = TGL_TRANS_DDI_PORT_MASK; 775 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 776 } else { 777 port_mask = TRANS_DDI_PORT_MASK; 778 ddi_select = TRANS_DDI_SELECT_PORT(port); 779 } 780 781 tmp = intel_de_read(dev_priv, 782 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 783 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 784 trans_wakeref); 785 786 if ((tmp & port_mask) != ddi_select) 787 continue; 788 789 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST || 790 (HAS_DP20(dev_priv) && 791 (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B)) 792 mst_pipe_mask |= BIT(p); 793 794 *pipe_mask |= BIT(p); 795 } 796 797 if (!*pipe_mask) 798 drm_dbg_kms(&dev_priv->drm, 799 "No pipe for [ENCODER:%d:%s] found\n", 800 encoder->base.base.id, encoder->base.name); 801 802 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 803 drm_dbg_kms(&dev_priv->drm, 804 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 805 encoder->base.base.id, encoder->base.name, 806 *pipe_mask); 807 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 808 } 809 810 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 811 drm_dbg_kms(&dev_priv->drm, 812 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", 813 encoder->base.base.id, encoder->base.name, 814 *pipe_mask, mst_pipe_mask); 815 else 816 *is_dp_mst = mst_pipe_mask; 817 818 out: 819 if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) { 820 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 821 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 822 BXT_PHY_LANE_POWERDOWN_ACK | 823 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 824 drm_err(&dev_priv->drm, 825 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 826 encoder->base.base.id, encoder->base.name, tmp); 827 } 828 829 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 830 } 831 832 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 833 enum pipe *pipe) 834 { 835 u8 pipe_mask; 836 bool is_mst; 837 838 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 839 840 if (is_mst || !pipe_mask) 841 return false; 842 843 *pipe = ffs(pipe_mask) - 1; 844 845 return true; 846 } 847 848 static enum intel_display_power_domain 849 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port) 850 { 851 /* ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 852 * DC states enabled at the same time, while for driver initiated AUX 853 * transfers we need the same AUX IOs to be powered but with DC states 854 * disabled. Accordingly use the AUX power domain here which leaves DC 855 * states enabled. 856 * However, for non-A AUX ports the corresponding non-EDP transcoders 857 * would have already enabled power well 2 and DC_OFF. This means we can 858 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a 859 * specific AUX_IO reference without powering up any extra wells. 860 * Note that PSR is enabled only on Port A even though this function 861 * returns the correct domain for other ports too. 862 */ 863 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A : 864 intel_aux_power_domain(dig_port); 865 } 866 867 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 868 struct intel_crtc_state *crtc_state) 869 { 870 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 871 struct intel_digital_port *dig_port; 872 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 873 874 /* 875 * TODO: Add support for MST encoders. Atm, the following should never 876 * happen since fake-MST encoders don't set their get_power_domains() 877 * hook. 878 */ 879 if (drm_WARN_ON(&dev_priv->drm, 880 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 881 return; 882 883 dig_port = enc_to_dig_port(encoder); 884 885 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 886 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 887 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 888 dig_port->ddi_io_power_domain); 889 } 890 891 /* 892 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC 893 * ports. 894 */ 895 if (intel_crtc_has_dp_encoder(crtc_state) || 896 intel_phy_is_tc(dev_priv, phy)) { 897 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref); 898 dig_port->aux_wakeref = 899 intel_display_power_get(dev_priv, 900 intel_ddi_main_link_aux_domain(dig_port)); 901 } 902 } 903 904 void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder, 905 const struct intel_crtc_state *crtc_state) 906 { 907 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 908 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 909 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 910 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 911 u32 val; 912 913 if (cpu_transcoder != TRANSCODER_EDP) { 914 if (DISPLAY_VER(dev_priv) >= 13) 915 val = TGL_TRANS_CLK_SEL_PORT(phy); 916 else if (DISPLAY_VER(dev_priv) >= 12) 917 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 918 else 919 val = TRANS_CLK_SEL_PORT(encoder->port); 920 921 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 922 } 923 } 924 925 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state) 926 { 927 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 928 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 929 930 if (cpu_transcoder != TRANSCODER_EDP) { 931 if (DISPLAY_VER(dev_priv) >= 12) 932 intel_de_write(dev_priv, 933 TRANS_CLK_SEL(cpu_transcoder), 934 TGL_TRANS_CLK_SEL_DISABLED); 935 else 936 intel_de_write(dev_priv, 937 TRANS_CLK_SEL(cpu_transcoder), 938 TRANS_CLK_SEL_DISABLED); 939 } 940 } 941 942 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 943 enum port port, u8 iboost) 944 { 945 u32 tmp; 946 947 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 948 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 949 if (iboost) 950 tmp |= iboost << BALANCE_LEG_SHIFT(port); 951 else 952 tmp |= BALANCE_LEG_DISABLE(port); 953 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 954 } 955 956 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 957 const struct intel_crtc_state *crtc_state, 958 int level) 959 { 960 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 961 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 962 u8 iboost; 963 964 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 965 iboost = intel_bios_encoder_hdmi_boost_level(encoder->devdata); 966 else 967 iboost = intel_bios_encoder_dp_boost_level(encoder->devdata); 968 969 if (iboost == 0) { 970 const struct intel_ddi_buf_trans *trans; 971 int n_entries; 972 973 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 974 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 975 return; 976 977 iboost = trans->entries[level].hsw.i_boost; 978 } 979 980 /* Make sure that the requested I_boost is valid */ 981 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 982 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); 983 return; 984 } 985 986 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); 987 988 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 989 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 990 } 991 992 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 993 const struct intel_crtc_state *crtc_state) 994 { 995 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 996 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 997 int n_entries; 998 999 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1000 1001 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 1002 n_entries = 1; 1003 if (drm_WARN_ON(&dev_priv->drm, 1004 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1005 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1006 1007 return index_to_dp_signal_levels[n_entries - 1] & 1008 DP_TRAIN_VOLTAGE_SWING_MASK; 1009 } 1010 1011 /* 1012 * We assume that the full set of pre-emphasis values can be 1013 * used on all DDI platforms. Should that change we need to 1014 * rethink this code. 1015 */ 1016 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1017 { 1018 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1019 } 1020 1021 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1022 int lane) 1023 { 1024 if (crtc_state->port_clock > 600000) 1025 return 0; 1026 1027 if (crtc_state->lane_count == 4) 1028 return lane >= 1 ? LOADGEN_SELECT : 0; 1029 else 1030 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1031 } 1032 1033 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1034 const struct intel_crtc_state *crtc_state) 1035 { 1036 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1037 const struct intel_ddi_buf_trans *trans; 1038 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1039 int n_entries, ln; 1040 u32 val; 1041 1042 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1043 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1044 return; 1045 1046 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1047 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1048 1049 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1050 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1051 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, 1052 intel_dp->hobl_active ? val : 0); 1053 } 1054 1055 /* Set PORT_TX_DW5 */ 1056 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1057 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1058 TAP2_DISABLE | TAP3_DISABLE); 1059 val |= SCALING_MODE_SEL(0x2); 1060 val |= RTERM_SELECT(0x6); 1061 val |= TAP3_DISABLE; 1062 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1063 1064 /* Program PORT_TX_DW2 */ 1065 for (ln = 0; ln < 4; ln++) { 1066 int level = intel_ddi_level(encoder, crtc_state, ln); 1067 1068 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy), 1069 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1070 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1071 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1072 RCOMP_SCALAR(0x98)); 1073 } 1074 1075 /* Program PORT_TX_DW4 */ 1076 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1077 for (ln = 0; ln < 4; ln++) { 1078 int level = intel_ddi_level(encoder, crtc_state, ln); 1079 1080 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1081 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1082 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1083 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1084 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1085 } 1086 1087 /* Program PORT_TX_DW7 */ 1088 for (ln = 0; ln < 4; ln++) { 1089 int level = intel_ddi_level(encoder, crtc_state, ln); 1090 1091 intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy), 1092 N_SCALAR_MASK, 1093 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1094 } 1095 } 1096 1097 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1098 const struct intel_crtc_state *crtc_state) 1099 { 1100 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1101 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1102 u32 val; 1103 int ln; 1104 1105 /* 1106 * 1. If port type is eDP or DP, 1107 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1108 * else clear to 0b. 1109 */ 1110 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); 1111 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1112 val &= ~COMMON_KEEPER_EN; 1113 else 1114 val |= COMMON_KEEPER_EN; 1115 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 1116 1117 /* 2. Program loadgen select */ 1118 /* 1119 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1120 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1121 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1122 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1123 */ 1124 for (ln = 0; ln < 4; ln++) { 1125 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1126 LOADGEN_SELECT, 1127 icl_combo_phy_loadgen_select(crtc_state, ln)); 1128 } 1129 1130 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1131 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 1132 0, SUS_CLOCK_CONFIG); 1133 1134 /* 4. Clear training enable to change swing values */ 1135 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1136 val &= ~TX_TRAINING_EN; 1137 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1138 1139 /* 5. Program swing and de-emphasis */ 1140 icl_ddi_combo_vswing_program(encoder, crtc_state); 1141 1142 /* 6. Set training enable to trigger update */ 1143 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1144 val |= TX_TRAINING_EN; 1145 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1146 } 1147 1148 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1149 const struct intel_crtc_state *crtc_state) 1150 { 1151 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1152 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 1153 const struct intel_ddi_buf_trans *trans; 1154 int n_entries, ln; 1155 1156 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1157 return; 1158 1159 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1160 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1161 return; 1162 1163 for (ln = 0; ln < 2; ln++) { 1164 intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), 1165 CRI_USE_FS32, 0); 1166 intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), 1167 CRI_USE_FS32, 0); 1168 } 1169 1170 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1171 for (ln = 0; ln < 2; ln++) { 1172 int level; 1173 1174 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1175 1176 intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), 1177 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1178 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1179 1180 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1181 1182 intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), 1183 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1184 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1185 } 1186 1187 /* Program MG_TX_DRVCTRL with values from vswing table */ 1188 for (ln = 0; ln < 2; ln++) { 1189 int level; 1190 1191 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1192 1193 intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), 1194 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1195 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1196 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1197 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1198 CRI_TXDEEMPH_OVERRIDE_EN); 1199 1200 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1201 1202 intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), 1203 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1204 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1205 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1206 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1207 CRI_TXDEEMPH_OVERRIDE_EN); 1208 1209 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1210 } 1211 1212 /* 1213 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1214 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1215 * values from table for which TX1 and TX2 enabled. 1216 */ 1217 for (ln = 0; ln < 2; ln++) { 1218 intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port), 1219 CFG_LOW_RATE_LKREN_EN, 1220 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1221 } 1222 1223 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1224 for (ln = 0; ln < 2; ln++) { 1225 intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port), 1226 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1227 CFG_AMI_CK_DIV_OVERRIDE_EN, 1228 crtc_state->port_clock > 500000 ? 1229 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1230 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1231 1232 intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port), 1233 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1234 CFG_AMI_CK_DIV_OVERRIDE_EN, 1235 crtc_state->port_clock > 500000 ? 1236 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1237 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1238 } 1239 1240 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1241 for (ln = 0; ln < 2; ln++) { 1242 intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 1243 0, CRI_CALCINIT); 1244 intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 1245 0, CRI_CALCINIT); 1246 } 1247 } 1248 1249 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1250 const struct intel_crtc_state *crtc_state) 1251 { 1252 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1253 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 1254 const struct intel_ddi_buf_trans *trans; 1255 int n_entries, ln; 1256 1257 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1258 return; 1259 1260 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1261 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1262 return; 1263 1264 for (ln = 0; ln < 2; ln++) { 1265 int level; 1266 1267 intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); 1268 1269 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1270 1271 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln), 1272 DKL_TX_PRESHOOT_COEFF_MASK | 1273 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1274 DKL_TX_VSWING_CONTROL_MASK, 1275 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1276 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1277 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1278 1279 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1280 1281 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln), 1282 DKL_TX_PRESHOOT_COEFF_MASK | 1283 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1284 DKL_TX_VSWING_CONTROL_MASK, 1285 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1286 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1287 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1288 1289 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1290 DKL_TX_DP20BITMODE, 0); 1291 1292 if (IS_ALDERLAKE_P(dev_priv)) { 1293 u32 val; 1294 1295 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1296 if (ln == 0) { 1297 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1298 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); 1299 } else { 1300 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); 1301 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); 1302 } 1303 } else { 1304 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1305 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); 1306 } 1307 1308 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1309 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | 1310 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, 1311 val); 1312 } 1313 } 1314 } 1315 1316 static int translate_signal_level(struct intel_dp *intel_dp, 1317 u8 signal_levels) 1318 { 1319 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1320 int i; 1321 1322 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1323 if (index_to_dp_signal_levels[i] == signal_levels) 1324 return i; 1325 } 1326 1327 drm_WARN(&i915->drm, 1, 1328 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1329 signal_levels); 1330 1331 return 0; 1332 } 1333 1334 static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1335 const struct intel_crtc_state *crtc_state, 1336 int lane) 1337 { 1338 u8 train_set = intel_dp->train_set[lane]; 1339 1340 if (intel_dp_is_uhbr(crtc_state)) { 1341 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1342 } else { 1343 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1344 DP_TRAIN_PRE_EMPHASIS_MASK); 1345 1346 return translate_signal_level(intel_dp, signal_levels); 1347 } 1348 } 1349 1350 int intel_ddi_level(struct intel_encoder *encoder, 1351 const struct intel_crtc_state *crtc_state, 1352 int lane) 1353 { 1354 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1355 const struct intel_ddi_buf_trans *trans; 1356 int level, n_entries; 1357 1358 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1359 if (drm_WARN_ON_ONCE(&i915->drm, !trans)) 1360 return 0; 1361 1362 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1363 level = intel_ddi_hdmi_level(encoder, trans); 1364 else 1365 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1366 lane); 1367 1368 if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries)) 1369 level = n_entries - 1; 1370 1371 return level; 1372 } 1373 1374 static void 1375 hsw_set_signal_levels(struct intel_encoder *encoder, 1376 const struct intel_crtc_state *crtc_state) 1377 { 1378 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1379 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1380 int level = intel_ddi_level(encoder, crtc_state, 0); 1381 enum port port = encoder->port; 1382 u32 signal_levels; 1383 1384 if (has_iboost(dev_priv)) 1385 skl_ddi_set_iboost(encoder, crtc_state, level); 1386 1387 /* HDMI ignores the rest */ 1388 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1389 return; 1390 1391 signal_levels = DDI_BUF_TRANS_SELECT(level); 1392 1393 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1394 signal_levels); 1395 1396 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1397 intel_dp->DP |= signal_levels; 1398 1399 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 1400 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 1401 } 1402 1403 static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1404 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1405 { 1406 mutex_lock(&i915->display.dpll.lock); 1407 1408 intel_de_rmw(i915, reg, clk_sel_mask, clk_sel); 1409 1410 /* 1411 * "This step and the step before must be 1412 * done with separate register writes." 1413 */ 1414 intel_de_rmw(i915, reg, clk_off, 0); 1415 1416 mutex_unlock(&i915->display.dpll.lock); 1417 } 1418 1419 static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1420 u32 clk_off) 1421 { 1422 mutex_lock(&i915->display.dpll.lock); 1423 1424 intel_de_rmw(i915, reg, 0, clk_off); 1425 1426 mutex_unlock(&i915->display.dpll.lock); 1427 } 1428 1429 static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg, 1430 u32 clk_off) 1431 { 1432 return !(intel_de_read(i915, reg) & clk_off); 1433 } 1434 1435 static struct intel_shared_dpll * 1436 _icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg, 1437 u32 clk_sel_mask, u32 clk_sel_shift) 1438 { 1439 enum intel_dpll_id id; 1440 1441 id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift; 1442 1443 return intel_get_shared_dpll_by_id(i915, id); 1444 } 1445 1446 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1447 const struct intel_crtc_state *crtc_state) 1448 { 1449 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1450 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1451 enum phy phy = intel_port_to_phy(i915, encoder->port); 1452 1453 if (drm_WARN_ON(&i915->drm, !pll)) 1454 return; 1455 1456 _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1457 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1458 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1459 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1460 } 1461 1462 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1463 { 1464 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1465 enum phy phy = intel_port_to_phy(i915, encoder->port); 1466 1467 _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1468 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1469 } 1470 1471 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1472 { 1473 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1474 enum phy phy = intel_port_to_phy(i915, encoder->port); 1475 1476 return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy), 1477 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1478 } 1479 1480 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1481 { 1482 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1483 enum phy phy = intel_port_to_phy(i915, encoder->port); 1484 1485 return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy), 1486 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1487 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1488 } 1489 1490 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1491 const struct intel_crtc_state *crtc_state) 1492 { 1493 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1494 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1495 enum phy phy = intel_port_to_phy(i915, encoder->port); 1496 1497 if (drm_WARN_ON(&i915->drm, !pll)) 1498 return; 1499 1500 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1501 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1502 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1503 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1504 } 1505 1506 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1507 { 1508 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1509 enum phy phy = intel_port_to_phy(i915, encoder->port); 1510 1511 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1512 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1513 } 1514 1515 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1516 { 1517 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1518 enum phy phy = intel_port_to_phy(i915, encoder->port); 1519 1520 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1521 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1522 } 1523 1524 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1525 { 1526 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1527 enum phy phy = intel_port_to_phy(i915, encoder->port); 1528 1529 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1530 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1531 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1532 } 1533 1534 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1535 const struct intel_crtc_state *crtc_state) 1536 { 1537 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1538 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1539 enum phy phy = intel_port_to_phy(i915, encoder->port); 1540 1541 if (drm_WARN_ON(&i915->drm, !pll)) 1542 return; 1543 1544 /* 1545 * If we fail this, something went very wrong: first 2 PLLs should be 1546 * used by first 2 phys and last 2 PLLs by last phys 1547 */ 1548 if (drm_WARN_ON(&i915->drm, 1549 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1550 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1551 return; 1552 1553 _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1554 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1555 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1556 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1557 } 1558 1559 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1560 { 1561 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1562 enum phy phy = intel_port_to_phy(i915, encoder->port); 1563 1564 _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1565 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1566 } 1567 1568 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1569 { 1570 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1571 enum phy phy = intel_port_to_phy(i915, encoder->port); 1572 1573 return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy), 1574 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1575 } 1576 1577 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1578 { 1579 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1580 enum phy phy = intel_port_to_phy(i915, encoder->port); 1581 enum intel_dpll_id id; 1582 u32 val; 1583 1584 val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy)); 1585 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1586 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1587 id = val; 1588 1589 /* 1590 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1591 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1592 * bit for phy C and D. 1593 */ 1594 if (phy >= PHY_C) 1595 id += DPLL_ID_DG1_DPLL2; 1596 1597 return intel_get_shared_dpll_by_id(i915, id); 1598 } 1599 1600 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1601 const struct intel_crtc_state *crtc_state) 1602 { 1603 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1604 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1605 enum phy phy = intel_port_to_phy(i915, encoder->port); 1606 1607 if (drm_WARN_ON(&i915->drm, !pll)) 1608 return; 1609 1610 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1611 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1612 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1613 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1614 } 1615 1616 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1617 { 1618 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1619 enum phy phy = intel_port_to_phy(i915, encoder->port); 1620 1621 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1622 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1623 } 1624 1625 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1626 { 1627 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1628 enum phy phy = intel_port_to_phy(i915, encoder->port); 1629 1630 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1631 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1632 } 1633 1634 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1635 { 1636 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1637 enum phy phy = intel_port_to_phy(i915, encoder->port); 1638 1639 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1640 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1641 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1642 } 1643 1644 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1645 const struct intel_crtc_state *crtc_state) 1646 { 1647 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1648 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1649 enum port port = encoder->port; 1650 1651 if (drm_WARN_ON(&i915->drm, !pll)) 1652 return; 1653 1654 /* 1655 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1656 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1657 */ 1658 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1659 1660 icl_ddi_combo_enable_clock(encoder, crtc_state); 1661 } 1662 1663 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1664 { 1665 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1666 enum port port = encoder->port; 1667 1668 icl_ddi_combo_disable_clock(encoder); 1669 1670 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1671 } 1672 1673 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1674 { 1675 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1676 enum port port = encoder->port; 1677 u32 tmp; 1678 1679 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1680 1681 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1682 return false; 1683 1684 return icl_ddi_combo_is_clock_enabled(encoder); 1685 } 1686 1687 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1688 const struct intel_crtc_state *crtc_state) 1689 { 1690 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1691 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1692 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1693 enum port port = encoder->port; 1694 1695 if (drm_WARN_ON(&i915->drm, !pll)) 1696 return; 1697 1698 intel_de_write(i915, DDI_CLK_SEL(port), 1699 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1700 1701 mutex_lock(&i915->display.dpll.lock); 1702 1703 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1704 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1705 1706 mutex_unlock(&i915->display.dpll.lock); 1707 } 1708 1709 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1710 { 1711 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1712 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1713 enum port port = encoder->port; 1714 1715 mutex_lock(&i915->display.dpll.lock); 1716 1717 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1718 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1719 1720 mutex_unlock(&i915->display.dpll.lock); 1721 1722 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1723 } 1724 1725 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1726 { 1727 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1728 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1729 enum port port = encoder->port; 1730 u32 tmp; 1731 1732 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1733 1734 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1735 return false; 1736 1737 tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0); 1738 1739 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1740 } 1741 1742 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1743 { 1744 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1745 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1746 enum port port = encoder->port; 1747 enum intel_dpll_id id; 1748 u32 tmp; 1749 1750 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1751 1752 switch (tmp & DDI_CLK_SEL_MASK) { 1753 case DDI_CLK_SEL_TBT_162: 1754 case DDI_CLK_SEL_TBT_270: 1755 case DDI_CLK_SEL_TBT_540: 1756 case DDI_CLK_SEL_TBT_810: 1757 id = DPLL_ID_ICL_TBTPLL; 1758 break; 1759 case DDI_CLK_SEL_MG: 1760 id = icl_tc_port_to_pll_id(tc_port); 1761 break; 1762 default: 1763 MISSING_CASE(tmp); 1764 fallthrough; 1765 case DDI_CLK_SEL_NONE: 1766 return NULL; 1767 } 1768 1769 return intel_get_shared_dpll_by_id(i915, id); 1770 } 1771 1772 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1773 { 1774 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1775 enum intel_dpll_id id; 1776 1777 switch (encoder->port) { 1778 case PORT_A: 1779 id = DPLL_ID_SKL_DPLL0; 1780 break; 1781 case PORT_B: 1782 id = DPLL_ID_SKL_DPLL1; 1783 break; 1784 case PORT_C: 1785 id = DPLL_ID_SKL_DPLL2; 1786 break; 1787 default: 1788 MISSING_CASE(encoder->port); 1789 return NULL; 1790 } 1791 1792 return intel_get_shared_dpll_by_id(i915, id); 1793 } 1794 1795 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1796 const struct intel_crtc_state *crtc_state) 1797 { 1798 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1799 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1800 enum port port = encoder->port; 1801 1802 if (drm_WARN_ON(&i915->drm, !pll)) 1803 return; 1804 1805 mutex_lock(&i915->display.dpll.lock); 1806 1807 intel_de_rmw(i915, DPLL_CTRL2, 1808 DPLL_CTRL2_DDI_CLK_OFF(port) | 1809 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1810 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1811 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1812 1813 mutex_unlock(&i915->display.dpll.lock); 1814 } 1815 1816 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1817 { 1818 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1819 enum port port = encoder->port; 1820 1821 mutex_lock(&i915->display.dpll.lock); 1822 1823 intel_de_rmw(i915, DPLL_CTRL2, 1824 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1825 1826 mutex_unlock(&i915->display.dpll.lock); 1827 } 1828 1829 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1830 { 1831 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1832 enum port port = encoder->port; 1833 1834 /* 1835 * FIXME Not sure if the override affects both 1836 * the PLL selection and the CLK_OFF bit. 1837 */ 1838 return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 1839 } 1840 1841 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 1842 { 1843 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1844 enum port port = encoder->port; 1845 enum intel_dpll_id id; 1846 u32 tmp; 1847 1848 tmp = intel_de_read(i915, DPLL_CTRL2); 1849 1850 /* 1851 * FIXME Not sure if the override affects both 1852 * the PLL selection and the CLK_OFF bit. 1853 */ 1854 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 1855 return NULL; 1856 1857 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 1858 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 1859 1860 return intel_get_shared_dpll_by_id(i915, id); 1861 } 1862 1863 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 1864 const struct intel_crtc_state *crtc_state) 1865 { 1866 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1867 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1868 enum port port = encoder->port; 1869 1870 if (drm_WARN_ON(&i915->drm, !pll)) 1871 return; 1872 1873 intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 1874 } 1875 1876 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 1877 { 1878 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1879 enum port port = encoder->port; 1880 1881 intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 1882 } 1883 1884 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 1885 { 1886 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1887 enum port port = encoder->port; 1888 1889 return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 1890 } 1891 1892 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 1893 { 1894 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1895 enum port port = encoder->port; 1896 enum intel_dpll_id id; 1897 u32 tmp; 1898 1899 tmp = intel_de_read(i915, PORT_CLK_SEL(port)); 1900 1901 switch (tmp & PORT_CLK_SEL_MASK) { 1902 case PORT_CLK_SEL_WRPLL1: 1903 id = DPLL_ID_WRPLL1; 1904 break; 1905 case PORT_CLK_SEL_WRPLL2: 1906 id = DPLL_ID_WRPLL2; 1907 break; 1908 case PORT_CLK_SEL_SPLL: 1909 id = DPLL_ID_SPLL; 1910 break; 1911 case PORT_CLK_SEL_LCPLL_810: 1912 id = DPLL_ID_LCPLL_810; 1913 break; 1914 case PORT_CLK_SEL_LCPLL_1350: 1915 id = DPLL_ID_LCPLL_1350; 1916 break; 1917 case PORT_CLK_SEL_LCPLL_2700: 1918 id = DPLL_ID_LCPLL_2700; 1919 break; 1920 default: 1921 MISSING_CASE(tmp); 1922 fallthrough; 1923 case PORT_CLK_SEL_NONE: 1924 return NULL; 1925 } 1926 1927 return intel_get_shared_dpll_by_id(i915, id); 1928 } 1929 1930 void intel_ddi_enable_clock(struct intel_encoder *encoder, 1931 const struct intel_crtc_state *crtc_state) 1932 { 1933 if (encoder->enable_clock) 1934 encoder->enable_clock(encoder, crtc_state); 1935 } 1936 1937 void intel_ddi_disable_clock(struct intel_encoder *encoder) 1938 { 1939 if (encoder->disable_clock) 1940 encoder->disable_clock(encoder); 1941 } 1942 1943 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 1944 { 1945 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1946 u32 port_mask; 1947 bool ddi_clk_needed; 1948 1949 /* 1950 * In case of DP MST, we sanitize the primary encoder only, not the 1951 * virtual ones. 1952 */ 1953 if (encoder->type == INTEL_OUTPUT_DP_MST) 1954 return; 1955 1956 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 1957 u8 pipe_mask; 1958 bool is_mst; 1959 1960 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 1961 /* 1962 * In the unlikely case that BIOS enables DP in MST mode, just 1963 * warn since our MST HW readout is incomplete. 1964 */ 1965 if (drm_WARN_ON(&i915->drm, is_mst)) 1966 return; 1967 } 1968 1969 port_mask = BIT(encoder->port); 1970 ddi_clk_needed = encoder->base.crtc; 1971 1972 if (encoder->type == INTEL_OUTPUT_DSI) { 1973 struct intel_encoder *other_encoder; 1974 1975 port_mask = intel_dsi_encoder_ports(encoder); 1976 /* 1977 * Sanity check that we haven't incorrectly registered another 1978 * encoder using any of the ports of this DSI encoder. 1979 */ 1980 for_each_intel_encoder(&i915->drm, other_encoder) { 1981 if (other_encoder == encoder) 1982 continue; 1983 1984 if (drm_WARN_ON(&i915->drm, 1985 port_mask & BIT(other_encoder->port))) 1986 return; 1987 } 1988 /* 1989 * For DSI we keep the ddi clocks gated 1990 * except during enable/disable sequence. 1991 */ 1992 ddi_clk_needed = false; 1993 } 1994 1995 if (ddi_clk_needed || !encoder->is_clock_enabled || 1996 !encoder->is_clock_enabled(encoder)) 1997 return; 1998 1999 drm_notice(&i915->drm, 2000 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2001 encoder->base.base.id, encoder->base.name); 2002 2003 encoder->disable_clock(encoder); 2004 } 2005 2006 static void 2007 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2008 const struct intel_crtc_state *crtc_state) 2009 { 2010 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2011 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port); 2012 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); 2013 u32 ln0, ln1, pin_assignment; 2014 u8 width; 2015 2016 if (!intel_phy_is_tc(dev_priv, phy) || 2017 intel_tc_port_in_tbt_alt_mode(dig_port)) 2018 return; 2019 2020 if (DISPLAY_VER(dev_priv) >= 12) { 2021 ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)); 2022 ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)); 2023 } else { 2024 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 2025 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 2026 } 2027 2028 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2029 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2030 2031 /* DPPATC */ 2032 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 2033 width = crtc_state->lane_count; 2034 2035 switch (pin_assignment) { 2036 case 0x0: 2037 drm_WARN_ON(&dev_priv->drm, 2038 !intel_tc_port_in_legacy_mode(dig_port)); 2039 if (width == 1) { 2040 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2041 } else { 2042 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2043 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2044 } 2045 break; 2046 case 0x1: 2047 if (width == 4) { 2048 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2049 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2050 } 2051 break; 2052 case 0x2: 2053 if (width == 2) { 2054 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2055 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2056 } 2057 break; 2058 case 0x3: 2059 case 0x5: 2060 if (width == 1) { 2061 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2062 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2063 } else { 2064 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2065 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2066 } 2067 break; 2068 case 0x4: 2069 case 0x6: 2070 if (width == 1) { 2071 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2072 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2073 } else { 2074 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2075 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2076 } 2077 break; 2078 default: 2079 MISSING_CASE(pin_assignment); 2080 } 2081 2082 if (DISPLAY_VER(dev_priv) >= 12) { 2083 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0); 2084 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1); 2085 } else { 2086 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 2087 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 2088 } 2089 } 2090 2091 static enum transcoder 2092 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2093 { 2094 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2095 return crtc_state->mst_master_transcoder; 2096 else 2097 return crtc_state->cpu_transcoder; 2098 } 2099 2100 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2101 const struct intel_crtc_state *crtc_state) 2102 { 2103 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2104 2105 if (DISPLAY_VER(dev_priv) >= 12) 2106 return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state)); 2107 else 2108 return DP_TP_CTL(encoder->port); 2109 } 2110 2111 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2112 const struct intel_crtc_state *crtc_state) 2113 { 2114 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2115 2116 if (DISPLAY_VER(dev_priv) >= 12) 2117 return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state)); 2118 else 2119 return DP_TP_STATUS(encoder->port); 2120 } 2121 2122 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2123 const struct intel_crtc_state *crtc_state, 2124 bool enable) 2125 { 2126 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2127 2128 if (!crtc_state->vrr.enable) 2129 return; 2130 2131 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2132 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2133 drm_dbg_kms(&i915->drm, 2134 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2135 str_enable_disable(enable)); 2136 } 2137 2138 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2139 const struct intel_crtc_state *crtc_state) 2140 { 2141 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2142 2143 if (!crtc_state->fec_enable) 2144 return; 2145 2146 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0) 2147 drm_dbg_kms(&i915->drm, 2148 "Failed to set FEC_READY in the sink\n"); 2149 } 2150 2151 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2152 const struct intel_crtc_state *crtc_state) 2153 { 2154 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2155 struct intel_dp *intel_dp; 2156 u32 val; 2157 2158 if (!crtc_state->fec_enable) 2159 return; 2160 2161 intel_dp = enc_to_intel_dp(encoder); 2162 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2163 val |= DP_TP_CTL_FEC_ENABLE; 2164 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 2165 } 2166 2167 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder, 2168 const struct intel_crtc_state *crtc_state) 2169 { 2170 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2171 struct intel_dp *intel_dp; 2172 u32 val; 2173 2174 if (!crtc_state->fec_enable) 2175 return; 2176 2177 intel_dp = enc_to_intel_dp(encoder); 2178 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2179 val &= ~DP_TP_CTL_FEC_ENABLE; 2180 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 2181 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2182 } 2183 2184 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2185 const struct intel_crtc_state *crtc_state) 2186 { 2187 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2188 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2189 enum phy phy = intel_port_to_phy(i915, encoder->port); 2190 2191 if (intel_phy_is_combo(i915, phy)) { 2192 bool lane_reversal = 2193 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 2194 2195 intel_combo_phy_power_up_lanes(i915, phy, false, 2196 crtc_state->lane_count, 2197 lane_reversal); 2198 } 2199 } 2200 2201 /* Splitter enable for eDP MSO is limited to certain pipes. */ 2202 static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915) 2203 { 2204 if (IS_ALDERLAKE_P(i915)) 2205 return BIT(PIPE_A) | BIT(PIPE_B); 2206 else 2207 return BIT(PIPE_A); 2208 } 2209 2210 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2211 struct intel_crtc_state *pipe_config) 2212 { 2213 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2214 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2215 enum pipe pipe = crtc->pipe; 2216 u32 dss1; 2217 2218 if (!HAS_MSO(i915)) 2219 return; 2220 2221 dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); 2222 2223 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2224 if (!pipe_config->splitter.enable) 2225 return; 2226 2227 if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) { 2228 pipe_config->splitter.enable = false; 2229 return; 2230 } 2231 2232 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2233 default: 2234 drm_WARN(&i915->drm, true, 2235 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2236 fallthrough; 2237 case SPLITTER_CONFIGURATION_2_SEGMENT: 2238 pipe_config->splitter.link_count = 2; 2239 break; 2240 case SPLITTER_CONFIGURATION_4_SEGMENT: 2241 pipe_config->splitter.link_count = 4; 2242 break; 2243 } 2244 2245 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2246 } 2247 2248 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2249 { 2250 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2251 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2252 enum pipe pipe = crtc->pipe; 2253 u32 dss1 = 0; 2254 2255 if (!HAS_MSO(i915)) 2256 return; 2257 2258 if (crtc_state->splitter.enable) { 2259 dss1 |= SPLITTER_ENABLE; 2260 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2261 if (crtc_state->splitter.link_count == 2) 2262 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2263 else 2264 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2265 } 2266 2267 intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), 2268 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2269 OVERLAP_PIXELS_MASK, dss1); 2270 } 2271 2272 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2273 struct intel_encoder *encoder, 2274 const struct intel_crtc_state *crtc_state, 2275 const struct drm_connector_state *conn_state) 2276 { 2277 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2278 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2279 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2280 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2281 2282 intel_dp_set_link_params(intel_dp, 2283 crtc_state->port_clock, 2284 crtc_state->lane_count); 2285 2286 /* 2287 * We only configure what the register value will be here. Actual 2288 * enabling happens during link training farther down. 2289 */ 2290 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2291 2292 /* 2293 * 1. Enable Power Wells 2294 * 2295 * This was handled at the beginning of intel_atomic_commit_tail(), 2296 * before we called down into this function. 2297 */ 2298 2299 /* 2. Enable Panel Power if PPS is required */ 2300 intel_pps_on(intel_dp); 2301 2302 /* 2303 * 3. For non-TBT Type-C ports, set FIA lane count 2304 * (DFLEXDPSP.DPX4TXLATC) 2305 * 2306 * This was done before tgl_ddi_pre_enable_dp by 2307 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2308 */ 2309 2310 /* 2311 * 4. Enable the port PLL. 2312 * 2313 * The PLL enabling itself was already done before this function by 2314 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 2315 * configure the PLL to port mapping here. 2316 */ 2317 intel_ddi_enable_clock(encoder, crtc_state); 2318 2319 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2320 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2321 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2322 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2323 dig_port->ddi_io_power_domain); 2324 } 2325 2326 /* 6. Program DP_MODE */ 2327 icl_program_mg_dp_mode(dig_port, crtc_state); 2328 2329 /* 2330 * 7. The rest of the below are substeps under the bspec's "Enable and 2331 * Train Display Port" step. Note that steps that are specific to 2332 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2333 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2334 * us when active_mst_links==0, so any steps designated for "single 2335 * stream or multi-stream master transcoder" can just be performed 2336 * unconditionally here. 2337 */ 2338 2339 /* 2340 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2341 * Transcoder. 2342 */ 2343 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2344 2345 if (HAS_DP20(dev_priv)) 2346 intel_ddi_config_transcoder_dp2(encoder, crtc_state); 2347 2348 /* 2349 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2350 * Transport Select 2351 */ 2352 intel_ddi_config_transcoder_func(encoder, crtc_state); 2353 2354 /* 2355 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2356 * selected 2357 * 2358 * This will be handled by the intel_dp_start_link_train() farther 2359 * down this function. 2360 */ 2361 2362 /* 7.e Configure voltage swing and related IO settings */ 2363 encoder->set_signal_levels(encoder, crtc_state); 2364 2365 /* 2366 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2367 * the used lanes of the DDI. 2368 */ 2369 intel_ddi_power_up_lanes(encoder, crtc_state); 2370 2371 /* 2372 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2373 */ 2374 intel_ddi_mso_configure(crtc_state); 2375 2376 if (!is_mst) 2377 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2378 2379 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2380 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); 2381 /* 2382 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2383 * in the FEC_CONFIGURATION register to 1 before initiating link 2384 * training 2385 */ 2386 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 2387 2388 intel_dp_check_frl_training(intel_dp); 2389 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2390 2391 /* 2392 * 7.i Follow DisplayPort specification training sequence (see notes for 2393 * failure handling) 2394 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2395 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2396 * (timeout after 800 us) 2397 */ 2398 intel_dp_start_link_train(intel_dp, crtc_state); 2399 2400 /* 7.k Set DP_TP_CTL link training to Normal */ 2401 if (!is_trans_port_sync_mode(crtc_state)) 2402 intel_dp_stop_link_train(intel_dp, crtc_state); 2403 2404 /* 7.l Configure and enable FEC if needed */ 2405 intel_ddi_enable_fec(encoder, crtc_state); 2406 2407 intel_dsc_dp_pps_write(encoder, crtc_state); 2408 } 2409 2410 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2411 struct intel_encoder *encoder, 2412 const struct intel_crtc_state *crtc_state, 2413 const struct drm_connector_state *conn_state) 2414 { 2415 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2416 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2417 enum port port = encoder->port; 2418 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2419 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2420 2421 if (DISPLAY_VER(dev_priv) < 11) 2422 drm_WARN_ON(&dev_priv->drm, 2423 is_mst && (port == PORT_A || port == PORT_E)); 2424 else 2425 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 2426 2427 intel_dp_set_link_params(intel_dp, 2428 crtc_state->port_clock, 2429 crtc_state->lane_count); 2430 2431 /* 2432 * We only configure what the register value will be here. Actual 2433 * enabling happens during link training farther down. 2434 */ 2435 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2436 2437 intel_pps_on(intel_dp); 2438 2439 intel_ddi_enable_clock(encoder, crtc_state); 2440 2441 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2442 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2443 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2444 dig_port->ddi_io_power_domain); 2445 } 2446 2447 icl_program_mg_dp_mode(dig_port, crtc_state); 2448 2449 if (has_buf_trans_select(dev_priv)) 2450 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2451 2452 encoder->set_signal_levels(encoder, crtc_state); 2453 2454 intel_ddi_power_up_lanes(encoder, crtc_state); 2455 2456 if (!is_mst) 2457 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2458 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2459 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, 2460 true); 2461 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 2462 intel_dp_start_link_train(intel_dp, crtc_state); 2463 if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && 2464 !is_trans_port_sync_mode(crtc_state)) 2465 intel_dp_stop_link_train(intel_dp, crtc_state); 2466 2467 intel_ddi_enable_fec(encoder, crtc_state); 2468 2469 if (!is_mst) 2470 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2471 2472 intel_dsc_dp_pps_write(encoder, crtc_state); 2473 } 2474 2475 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2476 struct intel_encoder *encoder, 2477 const struct intel_crtc_state *crtc_state, 2478 const struct drm_connector_state *conn_state) 2479 { 2480 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2481 2482 if (DISPLAY_VER(dev_priv) >= 12) 2483 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2484 else 2485 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2486 2487 /* MST will call a setting of MSA after an allocating of Virtual Channel 2488 * from MST encoder pre_enable callback. 2489 */ 2490 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2491 intel_ddi_set_dp_msa(crtc_state, conn_state); 2492 } 2493 2494 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2495 struct intel_encoder *encoder, 2496 const struct intel_crtc_state *crtc_state, 2497 const struct drm_connector_state *conn_state) 2498 { 2499 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2500 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2501 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2502 2503 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2504 intel_ddi_enable_clock(encoder, crtc_state); 2505 2506 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2507 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2508 dig_port->ddi_io_power_domain); 2509 2510 icl_program_mg_dp_mode(dig_port, crtc_state); 2511 2512 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2513 2514 dig_port->set_infoframes(encoder, 2515 crtc_state->has_infoframe, 2516 crtc_state, conn_state); 2517 } 2518 2519 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 2520 struct intel_encoder *encoder, 2521 const struct intel_crtc_state *crtc_state, 2522 const struct drm_connector_state *conn_state) 2523 { 2524 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2525 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2526 enum pipe pipe = crtc->pipe; 2527 2528 /* 2529 * When called from DP MST code: 2530 * - conn_state will be NULL 2531 * - encoder will be the main encoder (ie. mst->primary) 2532 * - the main connector associated with this port 2533 * won't be active or linked to a crtc 2534 * - crtc_state will be the state of the first stream to 2535 * be activated on this port, and it may not be the same 2536 * stream that will be deactivated last, but each stream 2537 * should have a state that is identical when it comes to 2538 * the DP link parameteres 2539 */ 2540 2541 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 2542 2543 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2544 2545 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 2546 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 2547 conn_state); 2548 } else { 2549 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2550 2551 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 2552 conn_state); 2553 2554 /* FIXME precompute everything properly */ 2555 /* FIXME how do we turn infoframes off again? */ 2556 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) 2557 dig_port->set_infoframes(encoder, 2558 crtc_state->has_infoframe, 2559 crtc_state, conn_state); 2560 } 2561 } 2562 2563 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 2564 const struct intel_crtc_state *crtc_state) 2565 { 2566 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2567 enum port port = encoder->port; 2568 bool wait = false; 2569 u32 val; 2570 2571 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2572 if (val & DDI_BUF_CTL_ENABLE) { 2573 val &= ~DDI_BUF_CTL_ENABLE; 2574 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 2575 wait = true; 2576 } 2577 2578 if (intel_crtc_has_dp_encoder(crtc_state)) { 2579 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2580 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 2581 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 2582 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 2583 } 2584 2585 /* Disable FEC in DP Sink */ 2586 intel_ddi_disable_fec_state(encoder, crtc_state); 2587 2588 if (wait) 2589 intel_wait_ddi_buf_idle(dev_priv, port); 2590 } 2591 2592 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 2593 struct intel_encoder *encoder, 2594 const struct intel_crtc_state *old_crtc_state, 2595 const struct drm_connector_state *old_conn_state) 2596 { 2597 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2598 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2599 struct intel_dp *intel_dp = &dig_port->dp; 2600 bool is_mst = intel_crtc_has_type(old_crtc_state, 2601 INTEL_OUTPUT_DP_MST); 2602 2603 if (!is_mst) 2604 intel_dp_set_infoframes(encoder, false, 2605 old_crtc_state, old_conn_state); 2606 2607 /* 2608 * Power down sink before disabling the port, otherwise we end 2609 * up getting interrupts from the sink on detecting link loss. 2610 */ 2611 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 2612 2613 if (DISPLAY_VER(dev_priv) >= 12) { 2614 if (is_mst) { 2615 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 2616 u32 val; 2617 2618 val = intel_de_read(dev_priv, 2619 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 2620 val &= ~(TGL_TRANS_DDI_PORT_MASK | 2621 TRANS_DDI_MODE_SELECT_MASK); 2622 intel_de_write(dev_priv, 2623 TRANS_DDI_FUNC_CTL(cpu_transcoder), 2624 val); 2625 } 2626 } else { 2627 if (!is_mst) 2628 intel_ddi_disable_pipe_clock(old_crtc_state); 2629 } 2630 2631 intel_disable_ddi_buf(encoder, old_crtc_state); 2632 2633 /* 2634 * From TGL spec: "If single stream or multi-stream master transcoder: 2635 * Configure Transcoder Clock select to direct no clock to the 2636 * transcoder" 2637 */ 2638 if (DISPLAY_VER(dev_priv) >= 12) 2639 intel_ddi_disable_pipe_clock(old_crtc_state); 2640 2641 intel_pps_vdd_on(intel_dp); 2642 intel_pps_off(intel_dp); 2643 2644 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 2645 intel_display_power_put(dev_priv, 2646 dig_port->ddi_io_power_domain, 2647 fetch_and_zero(&dig_port->ddi_io_wakeref)); 2648 2649 intel_ddi_disable_clock(encoder); 2650 } 2651 2652 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 2653 struct intel_encoder *encoder, 2654 const struct intel_crtc_state *old_crtc_state, 2655 const struct drm_connector_state *old_conn_state) 2656 { 2657 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2658 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2659 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2660 2661 dig_port->set_infoframes(encoder, false, 2662 old_crtc_state, old_conn_state); 2663 2664 if (DISPLAY_VER(dev_priv) < 12) 2665 intel_ddi_disable_pipe_clock(old_crtc_state); 2666 2667 intel_disable_ddi_buf(encoder, old_crtc_state); 2668 2669 if (DISPLAY_VER(dev_priv) >= 12) 2670 intel_ddi_disable_pipe_clock(old_crtc_state); 2671 2672 intel_display_power_put(dev_priv, 2673 dig_port->ddi_io_power_domain, 2674 fetch_and_zero(&dig_port->ddi_io_wakeref)); 2675 2676 intel_ddi_disable_clock(encoder); 2677 2678 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 2679 } 2680 2681 static void intel_ddi_post_disable(struct intel_atomic_state *state, 2682 struct intel_encoder *encoder, 2683 const struct intel_crtc_state *old_crtc_state, 2684 const struct drm_connector_state *old_conn_state) 2685 { 2686 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2687 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2688 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2689 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 2690 struct intel_crtc *slave_crtc; 2691 2692 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) { 2693 intel_crtc_vblank_off(old_crtc_state); 2694 2695 intel_disable_transcoder(old_crtc_state); 2696 2697 intel_vrr_disable(old_crtc_state); 2698 2699 intel_ddi_disable_transcoder_func(old_crtc_state); 2700 2701 intel_dsc_disable(old_crtc_state); 2702 2703 if (DISPLAY_VER(dev_priv) >= 9) 2704 skl_scaler_disable(old_crtc_state); 2705 else 2706 ilk_pfit_disable(old_crtc_state); 2707 } 2708 2709 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc, 2710 intel_crtc_bigjoiner_slave_pipes(old_crtc_state)) { 2711 const struct intel_crtc_state *old_slave_crtc_state = 2712 intel_atomic_get_old_crtc_state(state, slave_crtc); 2713 2714 intel_crtc_vblank_off(old_slave_crtc_state); 2715 2716 intel_dsc_disable(old_slave_crtc_state); 2717 skl_scaler_disable(old_slave_crtc_state); 2718 } 2719 2720 /* 2721 * When called from DP MST code: 2722 * - old_conn_state will be NULL 2723 * - encoder will be the main encoder (ie. mst->primary) 2724 * - the main connector associated with this port 2725 * won't be active or linked to a crtc 2726 * - old_crtc_state will be the state of the last stream to 2727 * be deactivated on this port, and it may not be the same 2728 * stream that was activated last, but each stream 2729 * should have a state that is identical when it comes to 2730 * the DP link parameteres 2731 */ 2732 2733 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 2734 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 2735 old_conn_state); 2736 else 2737 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 2738 old_conn_state); 2739 2740 if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port) 2741 intel_display_power_put(dev_priv, 2742 intel_ddi_main_link_aux_domain(dig_port), 2743 fetch_and_zero(&dig_port->aux_wakeref)); 2744 2745 if (is_tc_port) 2746 intel_tc_port_put_link(dig_port); 2747 } 2748 2749 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 2750 struct intel_encoder *encoder, 2751 const struct intel_crtc_state *crtc_state) 2752 { 2753 const struct drm_connector_state *conn_state; 2754 struct drm_connector *conn; 2755 int i; 2756 2757 if (!crtc_state->sync_mode_slaves_mask) 2758 return; 2759 2760 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 2761 struct intel_encoder *slave_encoder = 2762 to_intel_encoder(conn_state->best_encoder); 2763 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 2764 const struct intel_crtc_state *slave_crtc_state; 2765 2766 if (!slave_crtc) 2767 continue; 2768 2769 slave_crtc_state = 2770 intel_atomic_get_new_crtc_state(state, slave_crtc); 2771 2772 if (slave_crtc_state->master_transcoder != 2773 crtc_state->cpu_transcoder) 2774 continue; 2775 2776 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 2777 slave_crtc_state); 2778 } 2779 2780 usleep_range(200, 400); 2781 2782 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 2783 crtc_state); 2784 } 2785 2786 static void intel_enable_ddi_dp(struct intel_atomic_state *state, 2787 struct intel_encoder *encoder, 2788 const struct intel_crtc_state *crtc_state, 2789 const struct drm_connector_state *conn_state) 2790 { 2791 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2792 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2793 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2794 enum port port = encoder->port; 2795 2796 if (port == PORT_A && DISPLAY_VER(dev_priv) < 9) 2797 intel_dp_stop_link_train(intel_dp, crtc_state); 2798 2799 drm_connector_update_privacy_screen(conn_state); 2800 intel_edp_backlight_on(crtc_state, conn_state); 2801 2802 if (!dig_port->lspcon.active || dig_port->dp.has_hdmi_sink) 2803 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 2804 2805 intel_audio_codec_enable(encoder, crtc_state, conn_state); 2806 2807 trans_port_sync_stop_link_train(state, encoder, crtc_state); 2808 } 2809 2810 static i915_reg_t 2811 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 2812 enum port port) 2813 { 2814 static const enum transcoder trans[] = { 2815 [PORT_A] = TRANSCODER_EDP, 2816 [PORT_B] = TRANSCODER_A, 2817 [PORT_C] = TRANSCODER_B, 2818 [PORT_D] = TRANSCODER_C, 2819 [PORT_E] = TRANSCODER_A, 2820 }; 2821 2822 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9); 2823 2824 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) 2825 port = PORT_A; 2826 2827 return CHICKEN_TRANS(trans[port]); 2828 } 2829 2830 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, 2831 struct intel_encoder *encoder, 2832 const struct intel_crtc_state *crtc_state, 2833 const struct drm_connector_state *conn_state) 2834 { 2835 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2836 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2837 struct drm_connector *connector = conn_state->connector; 2838 enum port port = encoder->port; 2839 enum phy phy = intel_port_to_phy(dev_priv, port); 2840 u32 buf_ctl; 2841 2842 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 2843 crtc_state->hdmi_high_tmds_clock_ratio, 2844 crtc_state->hdmi_scrambling)) 2845 drm_dbg_kms(&dev_priv->drm, 2846 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 2847 connector->base.id, connector->name); 2848 2849 if (has_buf_trans_select(dev_priv)) 2850 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 2851 2852 encoder->set_signal_levels(encoder, crtc_state); 2853 2854 /* Display WA #1143: skl,kbl,cfl */ 2855 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { 2856 /* 2857 * For some reason these chicken bits have been 2858 * stuffed into a transcoder register, event though 2859 * the bits affect a specific DDI port rather than 2860 * a specific transcoder. 2861 */ 2862 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 2863 u32 val; 2864 2865 val = intel_de_read(dev_priv, reg); 2866 2867 if (port == PORT_E) 2868 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 2869 DDIE_TRAINING_OVERRIDE_VALUE; 2870 else 2871 val |= DDI_TRAINING_OVERRIDE_ENABLE | 2872 DDI_TRAINING_OVERRIDE_VALUE; 2873 2874 intel_de_write(dev_priv, reg, val); 2875 intel_de_posting_read(dev_priv, reg); 2876 2877 udelay(1); 2878 2879 if (port == PORT_E) 2880 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 2881 DDIE_TRAINING_OVERRIDE_VALUE); 2882 else 2883 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 2884 DDI_TRAINING_OVERRIDE_VALUE); 2885 2886 intel_de_write(dev_priv, reg, val); 2887 } 2888 2889 intel_ddi_power_up_lanes(encoder, crtc_state); 2890 2891 /* In HDMI/DVI mode, the port width, and swing/emphasis values 2892 * are ignored so nothing special needs to be done besides 2893 * enabling the port. 2894 * 2895 * On ADL_P the PHY link rate and lane count must be programmed but 2896 * these are both 0 for HDMI. 2897 */ 2898 buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE; 2899 if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) { 2900 drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port)); 2901 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 2902 } 2903 intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl); 2904 2905 intel_audio_codec_enable(encoder, crtc_state, conn_state); 2906 } 2907 2908 static void intel_enable_ddi(struct intel_atomic_state *state, 2909 struct intel_encoder *encoder, 2910 const struct intel_crtc_state *crtc_state, 2911 const struct drm_connector_state *conn_state) 2912 { 2913 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 2914 2915 if (!intel_crtc_is_bigjoiner_slave(crtc_state)) 2916 intel_ddi_enable_transcoder_func(encoder, crtc_state); 2917 2918 intel_vrr_enable(encoder, crtc_state); 2919 2920 intel_enable_transcoder(crtc_state); 2921 2922 intel_crtc_vblank_on(crtc_state); 2923 2924 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 2925 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state); 2926 else 2927 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state); 2928 2929 /* Enable hdcp if it's desired */ 2930 if (conn_state->content_protection == 2931 DRM_MODE_CONTENT_PROTECTION_DESIRED) 2932 intel_hdcp_enable(to_intel_connector(conn_state->connector), 2933 crtc_state, 2934 (u8)conn_state->hdcp_content_type); 2935 } 2936 2937 static void intel_disable_ddi_dp(struct intel_atomic_state *state, 2938 struct intel_encoder *encoder, 2939 const struct intel_crtc_state *old_crtc_state, 2940 const struct drm_connector_state *old_conn_state) 2941 { 2942 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2943 2944 intel_dp->link_trained = false; 2945 2946 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 2947 2948 intel_psr_disable(intel_dp, old_crtc_state); 2949 intel_edp_backlight_off(old_conn_state); 2950 /* Disable the decompression in DP Sink */ 2951 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, 2952 false); 2953 /* Disable Ignore_MSA bit in DP Sink */ 2954 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 2955 false); 2956 } 2957 2958 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state, 2959 struct intel_encoder *encoder, 2960 const struct intel_crtc_state *old_crtc_state, 2961 const struct drm_connector_state *old_conn_state) 2962 { 2963 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2964 struct drm_connector *connector = old_conn_state->connector; 2965 2966 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 2967 2968 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 2969 false, false)) 2970 drm_dbg_kms(&i915->drm, 2971 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 2972 connector->base.id, connector->name); 2973 } 2974 2975 static void intel_disable_ddi(struct intel_atomic_state *state, 2976 struct intel_encoder *encoder, 2977 const struct intel_crtc_state *old_crtc_state, 2978 const struct drm_connector_state *old_conn_state) 2979 { 2980 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 2981 2982 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 2983 intel_disable_ddi_hdmi(state, encoder, old_crtc_state, 2984 old_conn_state); 2985 else 2986 intel_disable_ddi_dp(state, encoder, old_crtc_state, 2987 old_conn_state); 2988 } 2989 2990 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 2991 struct intel_encoder *encoder, 2992 const struct intel_crtc_state *crtc_state, 2993 const struct drm_connector_state *conn_state) 2994 { 2995 intel_ddi_set_dp_msa(crtc_state, conn_state); 2996 2997 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 2998 2999 intel_backlight_update(state, encoder, crtc_state, conn_state); 3000 drm_connector_update_privacy_screen(conn_state); 3001 } 3002 3003 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3004 struct intel_encoder *encoder, 3005 const struct intel_crtc_state *crtc_state, 3006 const struct drm_connector_state *conn_state) 3007 { 3008 3009 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3010 !intel_encoder_is_mst(encoder)) 3011 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3012 conn_state); 3013 3014 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3015 } 3016 3017 static void 3018 intel_ddi_update_prepare(struct intel_atomic_state *state, 3019 struct intel_encoder *encoder, 3020 struct intel_crtc *crtc) 3021 { 3022 struct drm_i915_private *i915 = to_i915(state->base.dev); 3023 struct intel_crtc_state *crtc_state = 3024 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL; 3025 int required_lanes = crtc_state ? crtc_state->lane_count : 1; 3026 3027 drm_WARN_ON(state->base.dev, crtc && crtc->active); 3028 3029 intel_tc_port_get_link(enc_to_dig_port(encoder), 3030 required_lanes); 3031 if (crtc_state && crtc_state->hw.active) { 3032 struct intel_crtc *slave_crtc; 3033 3034 intel_update_active_dpll(state, crtc, encoder); 3035 3036 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 3037 intel_crtc_bigjoiner_slave_pipes(crtc_state)) 3038 intel_update_active_dpll(state, slave_crtc, encoder); 3039 } 3040 } 3041 3042 static void 3043 intel_ddi_update_complete(struct intel_atomic_state *state, 3044 struct intel_encoder *encoder, 3045 struct intel_crtc *crtc) 3046 { 3047 intel_tc_port_put_link(enc_to_dig_port(encoder)); 3048 } 3049 3050 static void 3051 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3052 struct intel_encoder *encoder, 3053 const struct intel_crtc_state *crtc_state, 3054 const struct drm_connector_state *conn_state) 3055 { 3056 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3057 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3058 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3059 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 3060 3061 if (is_tc_port) 3062 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3063 3064 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) { 3065 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref); 3066 dig_port->aux_wakeref = 3067 intel_display_power_get(dev_priv, 3068 intel_ddi_main_link_aux_domain(dig_port)); 3069 } 3070 3071 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3072 /* 3073 * Program the lane count for static/dynamic connections on 3074 * Type-C ports. Skip this step for TBT. 3075 */ 3076 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3077 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3078 bxt_ddi_phy_set_lane_optim_mask(encoder, 3079 crtc_state->lane_lat_optim_mask); 3080 } 3081 3082 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) 3083 { 3084 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3085 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 3086 int ln; 3087 3088 for (ln = 0; ln < 2; ln++) 3089 intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0); 3090 } 3091 3092 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3093 const struct intel_crtc_state *crtc_state) 3094 { 3095 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3096 struct intel_encoder *encoder = &dig_port->base; 3097 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3098 enum port port = encoder->port; 3099 u32 dp_tp_ctl, ddi_buf_ctl; 3100 bool wait = false; 3101 3102 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3103 3104 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 3105 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3106 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 3107 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3108 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 3109 wait = true; 3110 } 3111 3112 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 3113 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1; 3114 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3115 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3116 3117 if (wait) 3118 intel_wait_ddi_buf_idle(dev_priv, port); 3119 } 3120 3121 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3122 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3123 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3124 } else { 3125 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3126 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 3127 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3128 } 3129 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3130 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3131 3132 if (IS_ALDERLAKE_P(dev_priv) && 3133 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) 3134 adlp_tbt_to_dp_alt_switch_wa(encoder); 3135 3136 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3137 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3138 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3139 3140 intel_wait_ddi_buf_active(dev_priv, port); 3141 } 3142 3143 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3144 const struct intel_crtc_state *crtc_state, 3145 u8 dp_train_pat) 3146 { 3147 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3148 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3149 u32 temp; 3150 3151 temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3152 3153 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3154 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3155 case DP_TRAINING_PATTERN_DISABLE: 3156 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3157 break; 3158 case DP_TRAINING_PATTERN_1: 3159 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3160 break; 3161 case DP_TRAINING_PATTERN_2: 3162 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3163 break; 3164 case DP_TRAINING_PATTERN_3: 3165 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3166 break; 3167 case DP_TRAINING_PATTERN_4: 3168 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3169 break; 3170 } 3171 3172 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp); 3173 } 3174 3175 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3176 const struct intel_crtc_state *crtc_state) 3177 { 3178 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3179 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3180 enum port port = encoder->port; 3181 u32 val; 3182 3183 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3184 val &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3185 val |= DP_TP_CTL_LINK_TRAIN_IDLE; 3186 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 3187 3188 /* 3189 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3190 * reason we need to set idle transmission mode is to work around a HW 3191 * issue where we enable the pipe while not in idle link-training mode. 3192 * In this case there is requirement to wait for a minimum number of 3193 * idle patterns to be sent. 3194 */ 3195 if (port == PORT_A && DISPLAY_VER(dev_priv) < 12) 3196 return; 3197 3198 if (intel_de_wait_for_set(dev_priv, 3199 dp_tp_status_reg(encoder, crtc_state), 3200 DP_TP_STATUS_IDLE_DONE, 1)) 3201 drm_err(&dev_priv->drm, 3202 "Timed out waiting for DP idle patterns\n"); 3203 } 3204 3205 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 3206 enum transcoder cpu_transcoder) 3207 { 3208 if (cpu_transcoder == TRANSCODER_EDP) 3209 return false; 3210 3211 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO)) 3212 return false; 3213 3214 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 3215 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3216 } 3217 3218 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, 3219 struct intel_crtc_state *crtc_state) 3220 { 3221 if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000) 3222 crtc_state->min_voltage_level = 2; 3223 else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000) 3224 crtc_state->min_voltage_level = 3; 3225 else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000) 3226 crtc_state->min_voltage_level = 1; 3227 } 3228 3229 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, 3230 enum transcoder cpu_transcoder) 3231 { 3232 u32 master_select; 3233 3234 if (DISPLAY_VER(dev_priv) >= 11) { 3235 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder)); 3236 3237 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3238 return INVALID_TRANSCODER; 3239 3240 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3241 } else { 3242 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3243 3244 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3245 return INVALID_TRANSCODER; 3246 3247 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3248 } 3249 3250 if (master_select == 0) 3251 return TRANSCODER_EDP; 3252 else 3253 return master_select - 1; 3254 } 3255 3256 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3257 { 3258 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3259 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3260 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3261 enum transcoder cpu_transcoder; 3262 3263 crtc_state->master_transcoder = 3264 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); 3265 3266 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { 3267 enum intel_display_power_domain power_domain; 3268 intel_wakeref_t trans_wakeref; 3269 3270 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3271 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 3272 power_domain); 3273 3274 if (!trans_wakeref) 3275 continue; 3276 3277 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == 3278 crtc_state->cpu_transcoder) 3279 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3280 3281 intel_display_power_put(dev_priv, power_domain, trans_wakeref); 3282 } 3283 3284 drm_WARN_ON(&dev_priv->drm, 3285 crtc_state->master_transcoder != INVALID_TRANSCODER && 3286 crtc_state->sync_mode_slaves_mask); 3287 } 3288 3289 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 3290 struct intel_crtc_state *pipe_config) 3291 { 3292 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3293 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3294 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3295 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3296 u32 temp, flags = 0; 3297 3298 temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3299 if (temp & TRANS_DDI_PHSYNC) 3300 flags |= DRM_MODE_FLAG_PHSYNC; 3301 else 3302 flags |= DRM_MODE_FLAG_NHSYNC; 3303 if (temp & TRANS_DDI_PVSYNC) 3304 flags |= DRM_MODE_FLAG_PVSYNC; 3305 else 3306 flags |= DRM_MODE_FLAG_NVSYNC; 3307 3308 pipe_config->hw.adjusted_mode.flags |= flags; 3309 3310 switch (temp & TRANS_DDI_BPC_MASK) { 3311 case TRANS_DDI_BPC_6: 3312 pipe_config->pipe_bpp = 18; 3313 break; 3314 case TRANS_DDI_BPC_8: 3315 pipe_config->pipe_bpp = 24; 3316 break; 3317 case TRANS_DDI_BPC_10: 3318 pipe_config->pipe_bpp = 30; 3319 break; 3320 case TRANS_DDI_BPC_12: 3321 pipe_config->pipe_bpp = 36; 3322 break; 3323 default: 3324 break; 3325 } 3326 3327 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 3328 case TRANS_DDI_MODE_SELECT_HDMI: 3329 pipe_config->has_hdmi_sink = true; 3330 3331 pipe_config->infoframes.enable |= 3332 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3333 3334 if (pipe_config->infoframes.enable) 3335 pipe_config->has_infoframe = true; 3336 3337 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 3338 pipe_config->hdmi_scrambling = true; 3339 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 3340 pipe_config->hdmi_high_tmds_clock_ratio = true; 3341 fallthrough; 3342 case TRANS_DDI_MODE_SELECT_DVI: 3343 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 3344 pipe_config->lane_count = 4; 3345 break; 3346 case TRANS_DDI_MODE_SELECT_DP_SST: 3347 if (encoder->type == INTEL_OUTPUT_EDP) 3348 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 3349 else 3350 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 3351 pipe_config->lane_count = 3352 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3353 3354 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 3355 &pipe_config->dp_m_n); 3356 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, 3357 &pipe_config->dp_m2_n2); 3358 3359 if (DISPLAY_VER(dev_priv) >= 11) { 3360 i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config); 3361 3362 pipe_config->fec_enable = 3363 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE; 3364 3365 drm_dbg_kms(&dev_priv->drm, 3366 "[ENCODER:%d:%s] Fec status: %u\n", 3367 encoder->base.base.id, encoder->base.name, 3368 pipe_config->fec_enable); 3369 } 3370 3371 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) 3372 pipe_config->infoframes.enable |= 3373 intel_lspcon_infoframes_enabled(encoder, pipe_config); 3374 else 3375 pipe_config->infoframes.enable |= 3376 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3377 break; 3378 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 3379 if (!HAS_DP20(dev_priv)) { 3380 /* FDI */ 3381 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 3382 break; 3383 } 3384 fallthrough; /* 128b/132b */ 3385 case TRANS_DDI_MODE_SELECT_DP_MST: 3386 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 3387 pipe_config->lane_count = 3388 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3389 3390 if (DISPLAY_VER(dev_priv) >= 12) 3391 pipe_config->mst_master_transcoder = 3392 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); 3393 3394 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 3395 &pipe_config->dp_m_n); 3396 3397 pipe_config->infoframes.enable |= 3398 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3399 break; 3400 default: 3401 break; 3402 } 3403 } 3404 3405 static void intel_ddi_get_config(struct intel_encoder *encoder, 3406 struct intel_crtc_state *pipe_config) 3407 { 3408 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3409 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3410 3411 /* XXX: DSI transcoder paranoia */ 3412 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 3413 return; 3414 3415 intel_ddi_read_func_ctl(encoder, pipe_config); 3416 3417 intel_ddi_mso_get_config(encoder, pipe_config); 3418 3419 pipe_config->has_audio = 3420 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 3421 3422 if (encoder->type == INTEL_OUTPUT_EDP) 3423 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); 3424 3425 ddi_dotclock_get(pipe_config); 3426 3427 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3428 pipe_config->lane_lat_optim_mask = 3429 bxt_ddi_phy_get_lane_lat_optim_mask(encoder); 3430 3431 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 3432 3433 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 3434 3435 intel_read_infoframe(encoder, pipe_config, 3436 HDMI_INFOFRAME_TYPE_AVI, 3437 &pipe_config->infoframes.avi); 3438 intel_read_infoframe(encoder, pipe_config, 3439 HDMI_INFOFRAME_TYPE_SPD, 3440 &pipe_config->infoframes.spd); 3441 intel_read_infoframe(encoder, pipe_config, 3442 HDMI_INFOFRAME_TYPE_VENDOR, 3443 &pipe_config->infoframes.hdmi); 3444 intel_read_infoframe(encoder, pipe_config, 3445 HDMI_INFOFRAME_TYPE_DRM, 3446 &pipe_config->infoframes.drm); 3447 3448 if (DISPLAY_VER(dev_priv) >= 8) 3449 bdw_get_trans_port_sync_config(pipe_config); 3450 3451 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 3452 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 3453 3454 intel_psr_get_config(encoder, pipe_config); 3455 } 3456 3457 void intel_ddi_get_clock(struct intel_encoder *encoder, 3458 struct intel_crtc_state *crtc_state, 3459 struct intel_shared_dpll *pll) 3460 { 3461 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3462 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 3463 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 3464 bool pll_active; 3465 3466 if (drm_WARN_ON(&i915->drm, !pll)) 3467 return; 3468 3469 port_dpll->pll = pll; 3470 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 3471 drm_WARN_ON(&i915->drm, !pll_active); 3472 3473 icl_set_active_port_dpll(crtc_state, port_dpll_id); 3474 3475 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 3476 &crtc_state->dpll_hw_state); 3477 } 3478 3479 static void dg2_ddi_get_config(struct intel_encoder *encoder, 3480 struct intel_crtc_state *crtc_state) 3481 { 3482 intel_mpllb_readout_hw_state(encoder, &crtc_state->mpllb_state); 3483 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->mpllb_state); 3484 3485 intel_ddi_get_config(encoder, crtc_state); 3486 } 3487 3488 static void adls_ddi_get_config(struct intel_encoder *encoder, 3489 struct intel_crtc_state *crtc_state) 3490 { 3491 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 3492 intel_ddi_get_config(encoder, crtc_state); 3493 } 3494 3495 static void rkl_ddi_get_config(struct intel_encoder *encoder, 3496 struct intel_crtc_state *crtc_state) 3497 { 3498 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 3499 intel_ddi_get_config(encoder, crtc_state); 3500 } 3501 3502 static void dg1_ddi_get_config(struct intel_encoder *encoder, 3503 struct intel_crtc_state *crtc_state) 3504 { 3505 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 3506 intel_ddi_get_config(encoder, crtc_state); 3507 } 3508 3509 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 3510 struct intel_crtc_state *crtc_state) 3511 { 3512 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 3513 intel_ddi_get_config(encoder, crtc_state); 3514 } 3515 3516 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 3517 struct intel_crtc_state *crtc_state, 3518 struct intel_shared_dpll *pll) 3519 { 3520 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3521 enum icl_port_dpll_id port_dpll_id; 3522 struct icl_port_dpll *port_dpll; 3523 bool pll_active; 3524 3525 if (drm_WARN_ON(&i915->drm, !pll)) 3526 return; 3527 3528 if (pll->info->id == DPLL_ID_ICL_TBTPLL) 3529 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 3530 else 3531 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 3532 3533 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 3534 3535 port_dpll->pll = pll; 3536 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 3537 drm_WARN_ON(&i915->drm, !pll_active); 3538 3539 icl_set_active_port_dpll(crtc_state, port_dpll_id); 3540 3541 if (crtc_state->shared_dpll->info->id == DPLL_ID_ICL_TBTPLL) 3542 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port); 3543 else 3544 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 3545 &crtc_state->dpll_hw_state); 3546 } 3547 3548 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 3549 struct intel_crtc_state *crtc_state) 3550 { 3551 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 3552 intel_ddi_get_config(encoder, crtc_state); 3553 } 3554 3555 static void bxt_ddi_get_config(struct intel_encoder *encoder, 3556 struct intel_crtc_state *crtc_state) 3557 { 3558 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 3559 intel_ddi_get_config(encoder, crtc_state); 3560 } 3561 3562 static void skl_ddi_get_config(struct intel_encoder *encoder, 3563 struct intel_crtc_state *crtc_state) 3564 { 3565 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 3566 intel_ddi_get_config(encoder, crtc_state); 3567 } 3568 3569 void hsw_ddi_get_config(struct intel_encoder *encoder, 3570 struct intel_crtc_state *crtc_state) 3571 { 3572 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 3573 intel_ddi_get_config(encoder, crtc_state); 3574 } 3575 3576 static void intel_ddi_sync_state(struct intel_encoder *encoder, 3577 const struct intel_crtc_state *crtc_state) 3578 { 3579 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3580 enum phy phy = intel_port_to_phy(i915, encoder->port); 3581 3582 if (intel_phy_is_tc(i915, phy)) 3583 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder)); 3584 3585 if (crtc_state && intel_crtc_has_dp_encoder(crtc_state)) 3586 intel_dp_sync_state(encoder, crtc_state); 3587 } 3588 3589 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 3590 struct intel_crtc_state *crtc_state) 3591 { 3592 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3593 enum phy phy = intel_port_to_phy(i915, encoder->port); 3594 bool fastset = true; 3595 3596 if (intel_phy_is_tc(i915, phy)) { 3597 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", 3598 encoder->base.base.id, encoder->base.name); 3599 crtc_state->uapi.mode_changed = true; 3600 fastset = false; 3601 } 3602 3603 if (intel_crtc_has_dp_encoder(crtc_state) && 3604 !intel_dp_initial_fastset_check(encoder, crtc_state)) 3605 fastset = false; 3606 3607 return fastset; 3608 } 3609 3610 static enum intel_output_type 3611 intel_ddi_compute_output_type(struct intel_encoder *encoder, 3612 struct intel_crtc_state *crtc_state, 3613 struct drm_connector_state *conn_state) 3614 { 3615 switch (conn_state->connector->connector_type) { 3616 case DRM_MODE_CONNECTOR_HDMIA: 3617 return INTEL_OUTPUT_HDMI; 3618 case DRM_MODE_CONNECTOR_eDP: 3619 return INTEL_OUTPUT_EDP; 3620 case DRM_MODE_CONNECTOR_DisplayPort: 3621 return INTEL_OUTPUT_DP; 3622 default: 3623 MISSING_CASE(conn_state->connector->connector_type); 3624 return INTEL_OUTPUT_UNUSED; 3625 } 3626 } 3627 3628 static int intel_ddi_compute_config(struct intel_encoder *encoder, 3629 struct intel_crtc_state *pipe_config, 3630 struct drm_connector_state *conn_state) 3631 { 3632 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3633 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3634 enum port port = encoder->port; 3635 int ret; 3636 3637 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 3638 pipe_config->cpu_transcoder = TRANSCODER_EDP; 3639 3640 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 3641 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 3642 } else { 3643 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 3644 } 3645 3646 if (ret) 3647 return ret; 3648 3649 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 3650 pipe_config->cpu_transcoder == TRANSCODER_EDP) 3651 pipe_config->pch_pfit.force_thru = 3652 pipe_config->pch_pfit.enabled || 3653 pipe_config->crc_enabled; 3654 3655 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3656 pipe_config->lane_lat_optim_mask = 3657 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 3658 3659 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 3660 3661 return 0; 3662 } 3663 3664 static bool mode_equal(const struct drm_display_mode *mode1, 3665 const struct drm_display_mode *mode2) 3666 { 3667 return drm_mode_match(mode1, mode2, 3668 DRM_MODE_MATCH_TIMINGS | 3669 DRM_MODE_MATCH_FLAGS | 3670 DRM_MODE_MATCH_3D_FLAGS) && 3671 mode1->clock == mode2->clock; /* we want an exact match */ 3672 } 3673 3674 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 3675 const struct intel_link_m_n *m_n_2) 3676 { 3677 return m_n_1->tu == m_n_2->tu && 3678 m_n_1->data_m == m_n_2->data_m && 3679 m_n_1->data_n == m_n_2->data_n && 3680 m_n_1->link_m == m_n_2->link_m && 3681 m_n_1->link_n == m_n_2->link_n; 3682 } 3683 3684 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 3685 const struct intel_crtc_state *crtc_state2) 3686 { 3687 return crtc_state1->hw.active && crtc_state2->hw.active && 3688 crtc_state1->output_types == crtc_state2->output_types && 3689 crtc_state1->output_format == crtc_state2->output_format && 3690 crtc_state1->lane_count == crtc_state2->lane_count && 3691 crtc_state1->port_clock == crtc_state2->port_clock && 3692 mode_equal(&crtc_state1->hw.adjusted_mode, 3693 &crtc_state2->hw.adjusted_mode) && 3694 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 3695 } 3696 3697 static u8 3698 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 3699 int tile_group_id) 3700 { 3701 struct drm_connector *connector; 3702 const struct drm_connector_state *conn_state; 3703 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 3704 struct intel_atomic_state *state = 3705 to_intel_atomic_state(ref_crtc_state->uapi.state); 3706 u8 transcoders = 0; 3707 int i; 3708 3709 /* 3710 * We don't enable port sync on BDW due to missing w/as and 3711 * due to not having adjusted the modeset sequence appropriately. 3712 */ 3713 if (DISPLAY_VER(dev_priv) < 9) 3714 return 0; 3715 3716 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 3717 return 0; 3718 3719 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 3720 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 3721 const struct intel_crtc_state *crtc_state; 3722 3723 if (!crtc) 3724 continue; 3725 3726 if (!connector->has_tile || 3727 connector->tile_group->id != 3728 tile_group_id) 3729 continue; 3730 crtc_state = intel_atomic_get_new_crtc_state(state, 3731 crtc); 3732 if (!crtcs_port_sync_compatible(ref_crtc_state, 3733 crtc_state)) 3734 continue; 3735 transcoders |= BIT(crtc_state->cpu_transcoder); 3736 } 3737 3738 return transcoders; 3739 } 3740 3741 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 3742 struct intel_crtc_state *crtc_state, 3743 struct drm_connector_state *conn_state) 3744 { 3745 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3746 struct drm_connector *connector = conn_state->connector; 3747 u8 port_sync_transcoders = 0; 3748 3749 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]", 3750 encoder->base.base.id, encoder->base.name, 3751 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 3752 3753 if (connector->has_tile) 3754 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 3755 connector->tile_group->id); 3756 3757 /* 3758 * EDP Transcoders cannot be ensalved 3759 * make them a master always when present 3760 */ 3761 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 3762 crtc_state->master_transcoder = TRANSCODER_EDP; 3763 else 3764 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 3765 3766 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 3767 crtc_state->master_transcoder = INVALID_TRANSCODER; 3768 crtc_state->sync_mode_slaves_mask = 3769 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 3770 } 3771 3772 return 0; 3773 } 3774 3775 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 3776 { 3777 struct drm_i915_private *i915 = to_i915(encoder->dev); 3778 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 3779 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 3780 3781 intel_dp_encoder_flush_work(encoder); 3782 if (intel_phy_is_tc(i915, phy)) 3783 intel_tc_port_flush_work(dig_port); 3784 intel_display_power_flush_work(i915); 3785 3786 drm_encoder_cleanup(encoder); 3787 kfree(dig_port->hdcp_port_data.streams); 3788 kfree(dig_port); 3789 } 3790 3791 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 3792 { 3793 struct drm_i915_private *i915 = to_i915(encoder->dev); 3794 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 3795 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 3796 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 3797 3798 intel_dp->reset_link_params = true; 3799 3800 intel_pps_encoder_reset(intel_dp); 3801 3802 if (intel_phy_is_tc(i915, phy)) 3803 intel_tc_port_init_mode(dig_port); 3804 } 3805 3806 static const struct drm_encoder_funcs intel_ddi_funcs = { 3807 .reset = intel_ddi_encoder_reset, 3808 .destroy = intel_ddi_encoder_destroy, 3809 }; 3810 3811 static struct intel_connector * 3812 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 3813 { 3814 struct intel_connector *connector; 3815 enum port port = dig_port->base.port; 3816 3817 connector = intel_connector_alloc(); 3818 if (!connector) 3819 return NULL; 3820 3821 dig_port->dp.output_reg = DDI_BUF_CTL(port); 3822 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 3823 dig_port->dp.set_link_train = intel_ddi_set_link_train; 3824 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 3825 3826 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 3827 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 3828 3829 if (!intel_dp_init_connector(dig_port, connector)) { 3830 kfree(connector); 3831 return NULL; 3832 } 3833 3834 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 3835 struct drm_device *dev = dig_port->base.base.dev; 3836 struct drm_privacy_screen *privacy_screen; 3837 3838 privacy_screen = drm_privacy_screen_get(dev->dev, NULL); 3839 if (!IS_ERR(privacy_screen)) { 3840 drm_connector_attach_privacy_screen_provider(&connector->base, 3841 privacy_screen); 3842 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 3843 drm_warn(dev, "Error getting privacy-screen\n"); 3844 } 3845 } 3846 3847 return connector; 3848 } 3849 3850 static int modeset_pipe(struct drm_crtc *crtc, 3851 struct drm_modeset_acquire_ctx *ctx) 3852 { 3853 struct drm_atomic_state *state; 3854 struct drm_crtc_state *crtc_state; 3855 int ret; 3856 3857 state = drm_atomic_state_alloc(crtc->dev); 3858 if (!state) 3859 return -ENOMEM; 3860 3861 state->acquire_ctx = ctx; 3862 3863 crtc_state = drm_atomic_get_crtc_state(state, crtc); 3864 if (IS_ERR(crtc_state)) { 3865 ret = PTR_ERR(crtc_state); 3866 goto out; 3867 } 3868 3869 crtc_state->connectors_changed = true; 3870 3871 ret = drm_atomic_commit(state); 3872 out: 3873 drm_atomic_state_put(state); 3874 3875 return ret; 3876 } 3877 3878 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 3879 struct drm_modeset_acquire_ctx *ctx) 3880 { 3881 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3882 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 3883 struct intel_connector *connector = hdmi->attached_connector; 3884 struct i2c_adapter *adapter = 3885 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 3886 struct drm_connector_state *conn_state; 3887 struct intel_crtc_state *crtc_state; 3888 struct intel_crtc *crtc; 3889 u8 config; 3890 int ret; 3891 3892 if (!connector || connector->base.status != connector_status_connected) 3893 return 0; 3894 3895 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 3896 ctx); 3897 if (ret) 3898 return ret; 3899 3900 conn_state = connector->base.state; 3901 3902 crtc = to_intel_crtc(conn_state->crtc); 3903 if (!crtc) 3904 return 0; 3905 3906 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 3907 if (ret) 3908 return ret; 3909 3910 crtc_state = to_intel_crtc_state(crtc->base.state); 3911 3912 drm_WARN_ON(&dev_priv->drm, 3913 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 3914 3915 if (!crtc_state->hw.active) 3916 return 0; 3917 3918 if (!crtc_state->hdmi_high_tmds_clock_ratio && 3919 !crtc_state->hdmi_scrambling) 3920 return 0; 3921 3922 if (conn_state->commit && 3923 !try_wait_for_completion(&conn_state->commit->hw_done)) 3924 return 0; 3925 3926 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 3927 if (ret < 0) { 3928 drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n", 3929 ret); 3930 return 0; 3931 } 3932 3933 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 3934 crtc_state->hdmi_high_tmds_clock_ratio && 3935 !!(config & SCDC_SCRAMBLING_ENABLE) == 3936 crtc_state->hdmi_scrambling) 3937 return 0; 3938 3939 /* 3940 * HDMI 2.0 says that one should not send scrambled data 3941 * prior to configuring the sink scrambling, and that 3942 * TMDS clock/data transmission should be suspended when 3943 * changing the TMDS clock rate in the sink. So let's 3944 * just do a full modeset here, even though some sinks 3945 * would be perfectly happy if were to just reconfigure 3946 * the SCDC settings on the fly. 3947 */ 3948 return modeset_pipe(&crtc->base, ctx); 3949 } 3950 3951 static enum intel_hotplug_state 3952 intel_ddi_hotplug(struct intel_encoder *encoder, 3953 struct intel_connector *connector) 3954 { 3955 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3956 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3957 struct intel_dp *intel_dp = &dig_port->dp; 3958 enum phy phy = intel_port_to_phy(i915, encoder->port); 3959 bool is_tc = intel_phy_is_tc(i915, phy); 3960 struct drm_modeset_acquire_ctx ctx; 3961 enum intel_hotplug_state state; 3962 int ret; 3963 3964 if (intel_dp->compliance.test_active && 3965 intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) { 3966 intel_dp_phy_test(encoder); 3967 /* just do the PHY test and nothing else */ 3968 return INTEL_HOTPLUG_UNCHANGED; 3969 } 3970 3971 state = intel_encoder_hotplug(encoder, connector); 3972 3973 drm_modeset_acquire_init(&ctx, 0); 3974 3975 for (;;) { 3976 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) 3977 ret = intel_hdmi_reset_link(encoder, &ctx); 3978 else 3979 ret = intel_dp_retrain_link(encoder, &ctx); 3980 3981 if (ret == -EDEADLK) { 3982 drm_modeset_backoff(&ctx); 3983 continue; 3984 } 3985 3986 break; 3987 } 3988 3989 drm_modeset_drop_locks(&ctx); 3990 drm_modeset_acquire_fini(&ctx); 3991 drm_WARN(encoder->base.dev, ret, 3992 "Acquiring modeset locks failed with %i\n", ret); 3993 3994 /* 3995 * Unpowered type-c dongles can take some time to boot and be 3996 * responsible, so here giving some time to those dongles to power up 3997 * and then retrying the probe. 3998 * 3999 * On many platforms the HDMI live state signal is known to be 4000 * unreliable, so we can't use it to detect if a sink is connected or 4001 * not. Instead we detect if it's connected based on whether we can 4002 * read the EDID or not. That in turn has a problem during disconnect, 4003 * since the HPD interrupt may be raised before the DDC lines get 4004 * disconnected (due to how the required length of DDC vs. HPD 4005 * connector pins are specified) and so we'll still be able to get a 4006 * valid EDID. To solve this schedule another detection cycle if this 4007 * time around we didn't detect any change in the sink's connection 4008 * status. 4009 * 4010 * Type-c connectors which get their HPD signal deasserted then 4011 * reasserted, without unplugging/replugging the sink from the 4012 * connector, introduce a delay until the AUX channel communication 4013 * becomes functional. Retry the detection for 5 seconds on type-c 4014 * connectors to account for this delay. 4015 */ 4016 if (state == INTEL_HOTPLUG_UNCHANGED && 4017 connector->hotplug_retries < (is_tc ? 5 : 1) && 4018 !dig_port->dp.is_mst) 4019 state = INTEL_HOTPLUG_RETRY; 4020 4021 return state; 4022 } 4023 4024 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4025 { 4026 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4027 u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin]; 4028 4029 return intel_de_read(dev_priv, SDEISR) & bit; 4030 } 4031 4032 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4033 { 4034 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4035 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4036 4037 return intel_de_read(dev_priv, DEISR) & bit; 4038 } 4039 4040 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4041 { 4042 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4043 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4044 4045 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; 4046 } 4047 4048 static struct intel_connector * 4049 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4050 { 4051 struct intel_connector *connector; 4052 enum port port = dig_port->base.port; 4053 4054 connector = intel_connector_alloc(); 4055 if (!connector) 4056 return NULL; 4057 4058 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4059 intel_hdmi_init_connector(dig_port, connector); 4060 4061 return connector; 4062 } 4063 4064 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4065 { 4066 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4067 4068 if (dig_port->base.port != PORT_A) 4069 return false; 4070 4071 if (dig_port->saved_port_bits & DDI_A_4_LANES) 4072 return false; 4073 4074 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4075 * supported configuration 4076 */ 4077 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4078 return true; 4079 4080 return false; 4081 } 4082 4083 static int 4084 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4085 { 4086 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4087 enum port port = dig_port->base.port; 4088 int max_lanes = 4; 4089 4090 if (DISPLAY_VER(dev_priv) >= 11) 4091 return max_lanes; 4092 4093 if (port == PORT_A || port == PORT_E) { 4094 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4095 max_lanes = port == PORT_A ? 4 : 0; 4096 else 4097 /* Both A and E share 2 lanes */ 4098 max_lanes = 2; 4099 } 4100 4101 /* 4102 * Some BIOS might fail to set this bit on port A if eDP 4103 * wasn't lit up at boot. Force this bit set when needed 4104 * so we use the proper lane count for our calculations. 4105 */ 4106 if (intel_ddi_a_force_4_lanes(dig_port)) { 4107 drm_dbg_kms(&dev_priv->drm, 4108 "Forcing DDI_A_4_LANES for port A\n"); 4109 dig_port->saved_port_bits |= DDI_A_4_LANES; 4110 max_lanes = 4; 4111 } 4112 4113 return max_lanes; 4114 } 4115 4116 static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy) 4117 { 4118 return i915->hti_state & HDPORT_ENABLED && 4119 i915->hti_state & HDPORT_DDI_USED(phy); 4120 } 4121 4122 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv, 4123 enum port port) 4124 { 4125 if (port >= PORT_D_XELPD) 4126 return HPD_PORT_D + port - PORT_D_XELPD; 4127 else if (port >= PORT_TC1) 4128 return HPD_PORT_TC1 + port - PORT_TC1; 4129 else 4130 return HPD_PORT_A + port - PORT_A; 4131 } 4132 4133 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, 4134 enum port port) 4135 { 4136 if (port >= PORT_TC1) 4137 return HPD_PORT_C + port - PORT_TC1; 4138 else 4139 return HPD_PORT_A + port - PORT_A; 4140 } 4141 4142 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, 4143 enum port port) 4144 { 4145 if (port >= PORT_TC1) 4146 return HPD_PORT_TC1 + port - PORT_TC1; 4147 else 4148 return HPD_PORT_A + port - PORT_A; 4149 } 4150 4151 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, 4152 enum port port) 4153 { 4154 if (HAS_PCH_TGP(dev_priv)) 4155 return tgl_hpd_pin(dev_priv, port); 4156 4157 if (port >= PORT_TC1) 4158 return HPD_PORT_C + port - PORT_TC1; 4159 else 4160 return HPD_PORT_A + port - PORT_A; 4161 } 4162 4163 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, 4164 enum port port) 4165 { 4166 if (port >= PORT_C) 4167 return HPD_PORT_TC1 + port - PORT_C; 4168 else 4169 return HPD_PORT_A + port - PORT_A; 4170 } 4171 4172 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, 4173 enum port port) 4174 { 4175 if (port == PORT_D) 4176 return HPD_PORT_A; 4177 4178 if (HAS_PCH_TGP(dev_priv)) 4179 return icl_hpd_pin(dev_priv, port); 4180 4181 return HPD_PORT_A + port - PORT_A; 4182 } 4183 4184 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) 4185 { 4186 if (HAS_PCH_TGP(dev_priv)) 4187 return icl_hpd_pin(dev_priv, port); 4188 4189 return HPD_PORT_A + port - PORT_A; 4190 } 4191 4192 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port) 4193 { 4194 if (DISPLAY_VER(i915) >= 12) 4195 return port >= PORT_TC1; 4196 else if (DISPLAY_VER(i915) >= 11) 4197 return port >= PORT_C; 4198 else 4199 return false; 4200 } 4201 4202 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 4203 { 4204 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4205 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4206 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4207 enum phy phy = intel_port_to_phy(i915, encoder->port); 4208 4209 intel_dp_encoder_suspend(encoder); 4210 4211 if (!intel_phy_is_tc(i915, phy)) 4212 return; 4213 4214 intel_tc_port_flush_work(dig_port); 4215 } 4216 4217 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 4218 { 4219 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4220 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4221 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4222 enum phy phy = intel_port_to_phy(i915, encoder->port); 4223 4224 intel_dp_encoder_shutdown(encoder); 4225 intel_hdmi_encoder_shutdown(encoder); 4226 4227 if (!intel_phy_is_tc(i915, phy)) 4228 return; 4229 4230 intel_tc_port_flush_work(dig_port); 4231 } 4232 4233 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 4234 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 4235 4236 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 4237 { 4238 struct intel_digital_port *dig_port; 4239 struct intel_encoder *encoder; 4240 const struct intel_bios_encoder_data *devdata; 4241 bool init_hdmi, init_dp; 4242 enum phy phy = intel_port_to_phy(dev_priv, port); 4243 4244 /* 4245 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 4246 * have taken over some of the PHYs and made them unavailable to the 4247 * driver. In that case we should skip initializing the corresponding 4248 * outputs. 4249 */ 4250 if (hti_uses_phy(dev_priv, phy)) { 4251 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", 4252 port_name(port), phy_name(phy)); 4253 return; 4254 } 4255 4256 devdata = intel_bios_encoder_data_lookup(dev_priv, port); 4257 if (!devdata) { 4258 drm_dbg_kms(&dev_priv->drm, 4259 "VBT says port %c is not present\n", 4260 port_name(port)); 4261 return; 4262 } 4263 4264 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 4265 intel_bios_encoder_supports_hdmi(devdata); 4266 init_dp = intel_bios_encoder_supports_dp(devdata); 4267 4268 if (intel_bios_is_lspcon_present(dev_priv, port)) { 4269 /* 4270 * Lspcon device needs to be driven with DP connector 4271 * with special detection sequence. So make sure DP 4272 * is initialized before lspcon. 4273 */ 4274 init_dp = true; 4275 init_hdmi = false; 4276 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", 4277 port_name(port)); 4278 } 4279 4280 if (!init_dp && !init_hdmi) { 4281 drm_dbg_kms(&dev_priv->drm, 4282 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 4283 port_name(port)); 4284 return; 4285 } 4286 4287 if (intel_phy_is_snps(dev_priv, phy) && 4288 dev_priv->snps_phy_failed_calibration & BIT(phy)) { 4289 drm_dbg_kms(&dev_priv->drm, 4290 "SNPS PHY %c failed to calibrate, proceeding anyway\n", 4291 phy_name(phy)); 4292 } 4293 4294 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 4295 if (!dig_port) 4296 return; 4297 4298 encoder = &dig_port->base; 4299 encoder->devdata = devdata; 4300 4301 if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) { 4302 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4303 DRM_MODE_ENCODER_TMDS, 4304 "DDI %c/PHY %c", 4305 port_name(port - PORT_D_XELPD + PORT_D), 4306 phy_name(phy)); 4307 } else if (DISPLAY_VER(dev_priv) >= 12) { 4308 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4309 4310 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4311 DRM_MODE_ENCODER_TMDS, 4312 "DDI %s%c/PHY %s%c", 4313 port >= PORT_TC1 ? "TC" : "", 4314 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 4315 tc_port != TC_PORT_NONE ? "TC" : "", 4316 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4317 } else if (DISPLAY_VER(dev_priv) >= 11) { 4318 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4319 4320 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4321 DRM_MODE_ENCODER_TMDS, 4322 "DDI %c%s/PHY %s%c", 4323 port_name(port), 4324 port >= PORT_C ? " (TC)" : "", 4325 tc_port != TC_PORT_NONE ? "TC" : "", 4326 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4327 } else { 4328 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4329 DRM_MODE_ENCODER_TMDS, 4330 "DDI %c/PHY %c", port_name(port), phy_name(phy)); 4331 } 4332 4333 mutex_init(&dig_port->hdcp_mutex); 4334 dig_port->num_hdcp_streams = 0; 4335 4336 encoder->hotplug = intel_ddi_hotplug; 4337 encoder->compute_output_type = intel_ddi_compute_output_type; 4338 encoder->compute_config = intel_ddi_compute_config; 4339 encoder->compute_config_late = intel_ddi_compute_config_late; 4340 encoder->enable = intel_enable_ddi; 4341 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 4342 encoder->pre_enable = intel_ddi_pre_enable; 4343 encoder->disable = intel_disable_ddi; 4344 encoder->post_disable = intel_ddi_post_disable; 4345 encoder->update_pipe = intel_ddi_update_pipe; 4346 encoder->get_hw_state = intel_ddi_get_hw_state; 4347 encoder->sync_state = intel_ddi_sync_state; 4348 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 4349 encoder->suspend = intel_ddi_encoder_suspend; 4350 encoder->shutdown = intel_ddi_encoder_shutdown; 4351 encoder->get_power_domains = intel_ddi_get_power_domains; 4352 4353 encoder->type = INTEL_OUTPUT_DDI; 4354 encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port); 4355 encoder->port = port; 4356 encoder->cloneable = 0; 4357 encoder->pipe_mask = ~0; 4358 4359 if (IS_DG2(dev_priv)) { 4360 encoder->enable_clock = intel_mpllb_enable; 4361 encoder->disable_clock = intel_mpllb_disable; 4362 encoder->get_config = dg2_ddi_get_config; 4363 } else if (IS_ALDERLAKE_S(dev_priv)) { 4364 encoder->enable_clock = adls_ddi_enable_clock; 4365 encoder->disable_clock = adls_ddi_disable_clock; 4366 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 4367 encoder->get_config = adls_ddi_get_config; 4368 } else if (IS_ROCKETLAKE(dev_priv)) { 4369 encoder->enable_clock = rkl_ddi_enable_clock; 4370 encoder->disable_clock = rkl_ddi_disable_clock; 4371 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 4372 encoder->get_config = rkl_ddi_get_config; 4373 } else if (IS_DG1(dev_priv)) { 4374 encoder->enable_clock = dg1_ddi_enable_clock; 4375 encoder->disable_clock = dg1_ddi_disable_clock; 4376 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 4377 encoder->get_config = dg1_ddi_get_config; 4378 } else if (IS_JSL_EHL(dev_priv)) { 4379 if (intel_ddi_is_tc(dev_priv, port)) { 4380 encoder->enable_clock = jsl_ddi_tc_enable_clock; 4381 encoder->disable_clock = jsl_ddi_tc_disable_clock; 4382 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 4383 encoder->get_config = icl_ddi_combo_get_config; 4384 } else { 4385 encoder->enable_clock = icl_ddi_combo_enable_clock; 4386 encoder->disable_clock = icl_ddi_combo_disable_clock; 4387 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 4388 encoder->get_config = icl_ddi_combo_get_config; 4389 } 4390 } else if (DISPLAY_VER(dev_priv) >= 11) { 4391 if (intel_ddi_is_tc(dev_priv, port)) { 4392 encoder->enable_clock = icl_ddi_tc_enable_clock; 4393 encoder->disable_clock = icl_ddi_tc_disable_clock; 4394 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 4395 encoder->get_config = icl_ddi_tc_get_config; 4396 } else { 4397 encoder->enable_clock = icl_ddi_combo_enable_clock; 4398 encoder->disable_clock = icl_ddi_combo_disable_clock; 4399 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 4400 encoder->get_config = icl_ddi_combo_get_config; 4401 } 4402 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 4403 /* BXT/GLK have fixed PLL->port mapping */ 4404 encoder->get_config = bxt_ddi_get_config; 4405 } else if (DISPLAY_VER(dev_priv) == 9) { 4406 encoder->enable_clock = skl_ddi_enable_clock; 4407 encoder->disable_clock = skl_ddi_disable_clock; 4408 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 4409 encoder->get_config = skl_ddi_get_config; 4410 } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 4411 encoder->enable_clock = hsw_ddi_enable_clock; 4412 encoder->disable_clock = hsw_ddi_disable_clock; 4413 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 4414 encoder->get_config = hsw_ddi_get_config; 4415 } 4416 4417 if (IS_DG2(dev_priv)) { 4418 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 4419 } else if (DISPLAY_VER(dev_priv) >= 12) { 4420 if (intel_phy_is_combo(dev_priv, phy)) 4421 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 4422 else 4423 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 4424 } else if (DISPLAY_VER(dev_priv) >= 11) { 4425 if (intel_phy_is_combo(dev_priv, phy)) 4426 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 4427 else 4428 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 4429 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 4430 encoder->set_signal_levels = bxt_ddi_phy_set_signal_levels; 4431 } else { 4432 encoder->set_signal_levels = hsw_set_signal_levels; 4433 } 4434 4435 intel_ddi_buf_trans_init(encoder); 4436 4437 if (DISPLAY_VER(dev_priv) >= 13) 4438 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port); 4439 else if (IS_DG1(dev_priv)) 4440 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); 4441 else if (IS_ROCKETLAKE(dev_priv)) 4442 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); 4443 else if (DISPLAY_VER(dev_priv) >= 12) 4444 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); 4445 else if (IS_JSL_EHL(dev_priv)) 4446 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); 4447 else if (DISPLAY_VER(dev_priv) == 11) 4448 encoder->hpd_pin = icl_hpd_pin(dev_priv, port); 4449 else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 4450 encoder->hpd_pin = skl_hpd_pin(dev_priv, port); 4451 else 4452 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 4453 4454 if (DISPLAY_VER(dev_priv) >= 11) 4455 dig_port->saved_port_bits = 4456 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 4457 & DDI_BUF_PORT_REVERSAL; 4458 else 4459 dig_port->saved_port_bits = 4460 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 4461 & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 4462 4463 if (intel_bios_is_lane_reversal_needed(dev_priv, port)) 4464 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL; 4465 4466 dig_port->dp.output_reg = INVALID_MMIO_REG; 4467 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 4468 dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 4469 4470 if (intel_phy_is_tc(dev_priv, phy)) { 4471 bool is_legacy = 4472 !intel_bios_encoder_supports_typec_usb(devdata) && 4473 !intel_bios_encoder_supports_tbt(devdata); 4474 4475 intel_tc_port_init(dig_port, is_legacy); 4476 4477 encoder->update_prepare = intel_ddi_update_prepare; 4478 encoder->update_complete = intel_ddi_update_complete; 4479 } 4480 4481 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 4482 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(dev_priv, port); 4483 4484 if (init_dp) { 4485 if (!intel_ddi_init_dp_connector(dig_port)) 4486 goto err; 4487 4488 dig_port->hpd_pulse = intel_dp_hpd_pulse; 4489 4490 if (dig_port->dp.mso_link_count) 4491 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv); 4492 } 4493 4494 /* In theory we don't need the encoder->type check, but leave it just in 4495 * case we have some really bad VBTs... */ 4496 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 4497 if (!intel_ddi_init_hdmi_connector(dig_port)) 4498 goto err; 4499 } 4500 4501 if (DISPLAY_VER(dev_priv) >= 11) { 4502 if (intel_phy_is_tc(dev_priv, phy)) 4503 dig_port->connected = intel_tc_port_connected; 4504 else 4505 dig_port->connected = lpt_digital_port_connected; 4506 } else if (DISPLAY_VER(dev_priv) >= 8) { 4507 if (port == PORT_A || IS_GEMINILAKE(dev_priv) || 4508 IS_BROXTON(dev_priv)) 4509 dig_port->connected = bdw_digital_port_connected; 4510 else 4511 dig_port->connected = lpt_digital_port_connected; 4512 } else { 4513 if (port == PORT_A) 4514 dig_port->connected = hsw_digital_port_connected; 4515 else 4516 dig_port->connected = lpt_digital_port_connected; 4517 } 4518 4519 intel_infoframe_init(dig_port); 4520 4521 return; 4522 4523 err: 4524 drm_encoder_cleanup(&encoder->base); 4525 kfree(dig_port); 4526 } 4527