1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <linux/string_helpers.h> 29 30 #include <drm/drm_privacy_screen_consumer.h> 31 #include <drm/drm_scdc_helper.h> 32 33 #include "i915_drv.h" 34 #include "intel_audio.h" 35 #include "intel_backlight.h" 36 #include "intel_combo_phy.h" 37 #include "intel_combo_phy_regs.h" 38 #include "intel_connector.h" 39 #include "intel_crtc.h" 40 #include "intel_ddi.h" 41 #include "intel_ddi_buf_trans.h" 42 #include "intel_de.h" 43 #include "intel_display_types.h" 44 #include "intel_dp.h" 45 #include "intel_dp_link_training.h" 46 #include "intel_dp_mst.h" 47 #include "intel_dpio_phy.h" 48 #include "intel_dsi.h" 49 #include "intel_fdi.h" 50 #include "intel_fifo_underrun.h" 51 #include "intel_gmbus.h" 52 #include "intel_hdcp.h" 53 #include "intel_hdmi.h" 54 #include "intel_hotplug.h" 55 #include "intel_lspcon.h" 56 #include "intel_pps.h" 57 #include "intel_psr.h" 58 #include "intel_snps_phy.h" 59 #include "intel_sprite.h" 60 #include "intel_tc.h" 61 #include "intel_tc_phy_regs.h" 62 #include "intel_vdsc.h" 63 #include "intel_vrr.h" 64 #include "skl_scaler.h" 65 #include "skl_universal_plane.h" 66 67 static const u8 index_to_dp_signal_levels[] = { 68 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 69 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 70 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 71 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 72 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 73 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 74 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 75 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 76 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 77 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 78 }; 79 80 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 81 const struct intel_ddi_buf_trans *trans) 82 { 83 int level; 84 85 level = intel_bios_hdmi_level_shift(encoder); 86 if (level < 0) 87 level = trans->hdmi_default_entry; 88 89 return level; 90 } 91 92 static bool has_buf_trans_select(struct drm_i915_private *i915) 93 { 94 return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915); 95 } 96 97 static bool has_iboost(struct drm_i915_private *i915) 98 { 99 return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915); 100 } 101 102 /* 103 * Starting with Haswell, DDI port buffers must be programmed with correct 104 * values in advance. This function programs the correct values for 105 * DP/eDP/FDI use cases. 106 */ 107 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 108 const struct intel_crtc_state *crtc_state) 109 { 110 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 111 u32 iboost_bit = 0; 112 int i, n_entries; 113 enum port port = encoder->port; 114 const struct intel_ddi_buf_trans *trans; 115 116 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 117 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 118 return; 119 120 /* If we're boosting the current, set bit 31 of trans1 */ 121 if (has_iboost(dev_priv) && 122 intel_bios_encoder_dp_boost_level(encoder->devdata)) 123 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 124 125 for (i = 0; i < n_entries; i++) { 126 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 127 trans->entries[i].hsw.trans1 | iboost_bit); 128 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 129 trans->entries[i].hsw.trans2); 130 } 131 } 132 133 /* 134 * Starting with Haswell, DDI port buffers must be programmed with correct 135 * values in advance. This function programs the correct values for 136 * HDMI/DVI use cases. 137 */ 138 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 139 const struct intel_crtc_state *crtc_state) 140 { 141 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 142 int level = intel_ddi_level(encoder, crtc_state, 0); 143 u32 iboost_bit = 0; 144 int n_entries; 145 enum port port = encoder->port; 146 const struct intel_ddi_buf_trans *trans; 147 148 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 149 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 150 return; 151 152 /* If we're boosting the current, set bit 31 of trans1 */ 153 if (has_iboost(dev_priv) && 154 intel_bios_encoder_hdmi_boost_level(encoder->devdata)) 155 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 156 157 /* Entry 9 is for HDMI: */ 158 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 159 trans->entries[level].hsw.trans1 | iboost_bit); 160 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 161 trans->entries[level].hsw.trans2); 162 } 163 164 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 165 enum port port) 166 { 167 if (IS_BROXTON(dev_priv)) { 168 udelay(16); 169 return; 170 } 171 172 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 173 DDI_BUF_IS_IDLE), 8)) 174 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", 175 port_name(port)); 176 } 177 178 static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, 179 enum port port) 180 { 181 int ret; 182 183 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ 184 if (DISPLAY_VER(dev_priv) < 10) { 185 usleep_range(518, 1000); 186 return; 187 } 188 189 ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 190 DDI_BUF_IS_IDLE), IS_DG2(dev_priv) ? 1200 : 500, 10, 10); 191 192 if (ret) 193 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", 194 port_name(port)); 195 } 196 197 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 198 { 199 switch (pll->info->id) { 200 case DPLL_ID_WRPLL1: 201 return PORT_CLK_SEL_WRPLL1; 202 case DPLL_ID_WRPLL2: 203 return PORT_CLK_SEL_WRPLL2; 204 case DPLL_ID_SPLL: 205 return PORT_CLK_SEL_SPLL; 206 case DPLL_ID_LCPLL_810: 207 return PORT_CLK_SEL_LCPLL_810; 208 case DPLL_ID_LCPLL_1350: 209 return PORT_CLK_SEL_LCPLL_1350; 210 case DPLL_ID_LCPLL_2700: 211 return PORT_CLK_SEL_LCPLL_2700; 212 default: 213 MISSING_CASE(pll->info->id); 214 return PORT_CLK_SEL_NONE; 215 } 216 } 217 218 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 219 const struct intel_crtc_state *crtc_state) 220 { 221 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 222 int clock = crtc_state->port_clock; 223 const enum intel_dpll_id id = pll->info->id; 224 225 switch (id) { 226 default: 227 /* 228 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 229 * here, so do warn if this get passed in 230 */ 231 MISSING_CASE(id); 232 return DDI_CLK_SEL_NONE; 233 case DPLL_ID_ICL_TBTPLL: 234 switch (clock) { 235 case 162000: 236 return DDI_CLK_SEL_TBT_162; 237 case 270000: 238 return DDI_CLK_SEL_TBT_270; 239 case 540000: 240 return DDI_CLK_SEL_TBT_540; 241 case 810000: 242 return DDI_CLK_SEL_TBT_810; 243 default: 244 MISSING_CASE(clock); 245 return DDI_CLK_SEL_NONE; 246 } 247 case DPLL_ID_ICL_MGPLL1: 248 case DPLL_ID_ICL_MGPLL2: 249 case DPLL_ID_ICL_MGPLL3: 250 case DPLL_ID_ICL_MGPLL4: 251 case DPLL_ID_TGL_MGPLL5: 252 case DPLL_ID_TGL_MGPLL6: 253 return DDI_CLK_SEL_MG; 254 } 255 } 256 257 static u32 ddi_buf_phy_link_rate(int port_clock) 258 { 259 switch (port_clock) { 260 case 162000: 261 return DDI_BUF_PHY_LINK_RATE(0); 262 case 216000: 263 return DDI_BUF_PHY_LINK_RATE(4); 264 case 243000: 265 return DDI_BUF_PHY_LINK_RATE(5); 266 case 270000: 267 return DDI_BUF_PHY_LINK_RATE(1); 268 case 324000: 269 return DDI_BUF_PHY_LINK_RATE(6); 270 case 432000: 271 return DDI_BUF_PHY_LINK_RATE(7); 272 case 540000: 273 return DDI_BUF_PHY_LINK_RATE(2); 274 case 810000: 275 return DDI_BUF_PHY_LINK_RATE(3); 276 default: 277 MISSING_CASE(port_clock); 278 return DDI_BUF_PHY_LINK_RATE(0); 279 } 280 } 281 282 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 283 const struct intel_crtc_state *crtc_state) 284 { 285 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 286 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 287 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 288 enum phy phy = intel_port_to_phy(i915, encoder->port); 289 290 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 291 intel_dp->DP = dig_port->saved_port_bits | 292 DDI_PORT_WIDTH(crtc_state->lane_count) | 293 DDI_BUF_TRANS_SELECT(0); 294 295 if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) { 296 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 297 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 298 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 299 } 300 } 301 302 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 303 enum port port) 304 { 305 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 306 307 switch (val) { 308 case DDI_CLK_SEL_NONE: 309 return 0; 310 case DDI_CLK_SEL_TBT_162: 311 return 162000; 312 case DDI_CLK_SEL_TBT_270: 313 return 270000; 314 case DDI_CLK_SEL_TBT_540: 315 return 540000; 316 case DDI_CLK_SEL_TBT_810: 317 return 810000; 318 default: 319 MISSING_CASE(val); 320 return 0; 321 } 322 } 323 324 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 325 { 326 int dotclock; 327 328 /* CRT dotclock is determined via other means */ 329 if (pipe_config->has_pch_encoder) 330 return; 331 332 if (intel_crtc_has_dp_encoder(pipe_config)) 333 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 334 &pipe_config->dp_m_n); 335 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) 336 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp; 337 else 338 dotclock = pipe_config->port_clock; 339 340 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 341 !intel_crtc_has_dp_encoder(pipe_config)) 342 dotclock *= 2; 343 344 if (pipe_config->pixel_multiplier) 345 dotclock /= pipe_config->pixel_multiplier; 346 347 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 348 } 349 350 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 351 const struct drm_connector_state *conn_state) 352 { 353 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 354 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 355 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 356 u32 temp; 357 358 if (!intel_crtc_has_dp_encoder(crtc_state)) 359 return; 360 361 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 362 363 temp = DP_MSA_MISC_SYNC_CLOCK; 364 365 switch (crtc_state->pipe_bpp) { 366 case 18: 367 temp |= DP_MSA_MISC_6_BPC; 368 break; 369 case 24: 370 temp |= DP_MSA_MISC_8_BPC; 371 break; 372 case 30: 373 temp |= DP_MSA_MISC_10_BPC; 374 break; 375 case 36: 376 temp |= DP_MSA_MISC_12_BPC; 377 break; 378 default: 379 MISSING_CASE(crtc_state->pipe_bpp); 380 break; 381 } 382 383 /* nonsense combination */ 384 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 385 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 386 387 if (crtc_state->limited_color_range) 388 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 389 390 /* 391 * As per DP 1.2 spec section 2.3.4.3 while sending 392 * YCBCR 444 signals we should program MSA MISC1/0 fields with 393 * colorspace information. 394 */ 395 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 396 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 397 398 /* 399 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 400 * of Color Encoding Format and Content Color Gamut] while sending 401 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 402 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 403 */ 404 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 405 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 406 407 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp); 408 } 409 410 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 411 { 412 if (master_transcoder == TRANSCODER_EDP) 413 return 0; 414 else 415 return master_transcoder + 1; 416 } 417 418 static void 419 intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder, 420 const struct intel_crtc_state *crtc_state) 421 { 422 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 423 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 424 u32 val = 0; 425 426 if (intel_dp_is_uhbr(crtc_state)) 427 val = TRANS_DP2_128B132B_CHANNEL_CODING; 428 429 intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val); 430 } 431 432 /* 433 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 434 * 435 * Only intended to be used by intel_ddi_enable_transcoder_func() and 436 * intel_ddi_config_transcoder_func(). 437 */ 438 static u32 439 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 440 const struct intel_crtc_state *crtc_state) 441 { 442 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 443 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 444 enum pipe pipe = crtc->pipe; 445 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 446 enum port port = encoder->port; 447 u32 temp; 448 449 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 450 temp = TRANS_DDI_FUNC_ENABLE; 451 if (DISPLAY_VER(dev_priv) >= 12) 452 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 453 else 454 temp |= TRANS_DDI_SELECT_PORT(port); 455 456 switch (crtc_state->pipe_bpp) { 457 case 18: 458 temp |= TRANS_DDI_BPC_6; 459 break; 460 case 24: 461 temp |= TRANS_DDI_BPC_8; 462 break; 463 case 30: 464 temp |= TRANS_DDI_BPC_10; 465 break; 466 case 36: 467 temp |= TRANS_DDI_BPC_12; 468 break; 469 default: 470 BUG(); 471 } 472 473 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 474 temp |= TRANS_DDI_PVSYNC; 475 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 476 temp |= TRANS_DDI_PHSYNC; 477 478 if (cpu_transcoder == TRANSCODER_EDP) { 479 switch (pipe) { 480 case PIPE_A: 481 /* On Haswell, can only use the always-on power well for 482 * eDP when not using the panel fitter, and when not 483 * using motion blur mitigation (which we don't 484 * support). */ 485 if (crtc_state->pch_pfit.force_thru) 486 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 487 else 488 temp |= TRANS_DDI_EDP_INPUT_A_ON; 489 break; 490 case PIPE_B: 491 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 492 break; 493 case PIPE_C: 494 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 495 break; 496 default: 497 BUG(); 498 break; 499 } 500 } 501 502 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 503 if (crtc_state->has_hdmi_sink) 504 temp |= TRANS_DDI_MODE_SELECT_HDMI; 505 else 506 temp |= TRANS_DDI_MODE_SELECT_DVI; 507 508 if (crtc_state->hdmi_scrambling) 509 temp |= TRANS_DDI_HDMI_SCRAMBLING; 510 if (crtc_state->hdmi_high_tmds_clock_ratio) 511 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 512 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 513 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 514 temp |= (crtc_state->fdi_lanes - 1) << 1; 515 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 516 if (intel_dp_is_uhbr(crtc_state)) 517 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 518 else 519 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 520 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 521 522 if (DISPLAY_VER(dev_priv) >= 12) { 523 enum transcoder master; 524 525 master = crtc_state->mst_master_transcoder; 526 drm_WARN_ON(&dev_priv->drm, 527 master == INVALID_TRANSCODER); 528 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 529 } 530 } else { 531 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 532 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 533 } 534 535 if (IS_DISPLAY_VER(dev_priv, 8, 10) && 536 crtc_state->master_transcoder != INVALID_TRANSCODER) { 537 u8 master_select = 538 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 539 540 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 541 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 542 } 543 544 return temp; 545 } 546 547 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 548 const struct intel_crtc_state *crtc_state) 549 { 550 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 551 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 552 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 553 554 if (DISPLAY_VER(dev_priv) >= 11) { 555 enum transcoder master_transcoder = crtc_state->master_transcoder; 556 u32 ctl2 = 0; 557 558 if (master_transcoder != INVALID_TRANSCODER) { 559 u8 master_select = 560 bdw_trans_port_sync_master_select(master_transcoder); 561 562 ctl2 |= PORT_SYNC_MODE_ENABLE | 563 PORT_SYNC_MODE_MASTER_SELECT(master_select); 564 } 565 566 intel_de_write(dev_priv, 567 TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2); 568 } 569 570 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 571 intel_ddi_transcoder_func_reg_val_get(encoder, 572 crtc_state)); 573 } 574 575 /* 576 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 577 * bit. 578 */ 579 static void 580 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 581 const struct intel_crtc_state *crtc_state) 582 { 583 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 584 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 585 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 586 u32 ctl; 587 588 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 589 ctl &= ~TRANS_DDI_FUNC_ENABLE; 590 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 591 } 592 593 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 594 { 595 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 596 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 597 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 598 u32 ctl; 599 600 if (DISPLAY_VER(dev_priv) >= 11) 601 intel_de_write(dev_priv, 602 TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0); 603 604 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 605 606 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 607 608 ctl &= ~TRANS_DDI_FUNC_ENABLE; 609 610 if (IS_DISPLAY_VER(dev_priv, 8, 10)) 611 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 612 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 613 614 if (DISPLAY_VER(dev_priv) >= 12) { 615 if (!intel_dp_mst_is_master_trans(crtc_state)) { 616 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 617 TRANS_DDI_MODE_SELECT_MASK); 618 } 619 } else { 620 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 621 } 622 623 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 624 625 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME && 626 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 627 drm_dbg_kms(&dev_priv->drm, 628 "Quirk Increase DDI disabled time\n"); 629 /* Quirk time at 100ms for reliable operation */ 630 msleep(100); 631 } 632 } 633 634 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 635 enum transcoder cpu_transcoder, 636 bool enable, u32 hdcp_mask) 637 { 638 struct drm_device *dev = intel_encoder->base.dev; 639 struct drm_i915_private *dev_priv = to_i915(dev); 640 intel_wakeref_t wakeref; 641 int ret = 0; 642 u32 tmp; 643 644 wakeref = intel_display_power_get_if_enabled(dev_priv, 645 intel_encoder->power_domain); 646 if (drm_WARN_ON(dev, !wakeref)) 647 return -ENXIO; 648 649 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 650 if (enable) 651 tmp |= hdcp_mask; 652 else 653 tmp &= ~hdcp_mask; 654 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp); 655 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 656 return ret; 657 } 658 659 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 660 { 661 struct drm_device *dev = intel_connector->base.dev; 662 struct drm_i915_private *dev_priv = to_i915(dev); 663 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 664 int type = intel_connector->base.connector_type; 665 enum port port = encoder->port; 666 enum transcoder cpu_transcoder; 667 intel_wakeref_t wakeref; 668 enum pipe pipe = 0; 669 u32 tmp; 670 bool ret; 671 672 wakeref = intel_display_power_get_if_enabled(dev_priv, 673 encoder->power_domain); 674 if (!wakeref) 675 return false; 676 677 if (!encoder->get_hw_state(encoder, &pipe)) { 678 ret = false; 679 goto out; 680 } 681 682 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 683 cpu_transcoder = TRANSCODER_EDP; 684 else 685 cpu_transcoder = (enum transcoder) pipe; 686 687 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 688 689 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 690 case TRANS_DDI_MODE_SELECT_HDMI: 691 case TRANS_DDI_MODE_SELECT_DVI: 692 ret = type == DRM_MODE_CONNECTOR_HDMIA; 693 break; 694 695 case TRANS_DDI_MODE_SELECT_DP_SST: 696 ret = type == DRM_MODE_CONNECTOR_eDP || 697 type == DRM_MODE_CONNECTOR_DisplayPort; 698 break; 699 700 case TRANS_DDI_MODE_SELECT_DP_MST: 701 /* if the transcoder is in MST state then 702 * connector isn't connected */ 703 ret = false; 704 break; 705 706 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 707 if (HAS_DP20(dev_priv)) 708 /* 128b/132b */ 709 ret = false; 710 else 711 /* FDI */ 712 ret = type == DRM_MODE_CONNECTOR_VGA; 713 break; 714 715 default: 716 ret = false; 717 break; 718 } 719 720 out: 721 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 722 723 return ret; 724 } 725 726 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 727 u8 *pipe_mask, bool *is_dp_mst) 728 { 729 struct drm_device *dev = encoder->base.dev; 730 struct drm_i915_private *dev_priv = to_i915(dev); 731 enum port port = encoder->port; 732 intel_wakeref_t wakeref; 733 enum pipe p; 734 u32 tmp; 735 u8 mst_pipe_mask; 736 737 *pipe_mask = 0; 738 *is_dp_mst = false; 739 740 wakeref = intel_display_power_get_if_enabled(dev_priv, 741 encoder->power_domain); 742 if (!wakeref) 743 return; 744 745 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 746 if (!(tmp & DDI_BUF_CTL_ENABLE)) 747 goto out; 748 749 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { 750 tmp = intel_de_read(dev_priv, 751 TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 752 753 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 754 default: 755 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 756 fallthrough; 757 case TRANS_DDI_EDP_INPUT_A_ON: 758 case TRANS_DDI_EDP_INPUT_A_ONOFF: 759 *pipe_mask = BIT(PIPE_A); 760 break; 761 case TRANS_DDI_EDP_INPUT_B_ONOFF: 762 *pipe_mask = BIT(PIPE_B); 763 break; 764 case TRANS_DDI_EDP_INPUT_C_ONOFF: 765 *pipe_mask = BIT(PIPE_C); 766 break; 767 } 768 769 goto out; 770 } 771 772 mst_pipe_mask = 0; 773 for_each_pipe(dev_priv, p) { 774 enum transcoder cpu_transcoder = (enum transcoder)p; 775 unsigned int port_mask, ddi_select; 776 intel_wakeref_t trans_wakeref; 777 778 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 779 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 780 if (!trans_wakeref) 781 continue; 782 783 if (DISPLAY_VER(dev_priv) >= 12) { 784 port_mask = TGL_TRANS_DDI_PORT_MASK; 785 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 786 } else { 787 port_mask = TRANS_DDI_PORT_MASK; 788 ddi_select = TRANS_DDI_SELECT_PORT(port); 789 } 790 791 tmp = intel_de_read(dev_priv, 792 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 793 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 794 trans_wakeref); 795 796 if ((tmp & port_mask) != ddi_select) 797 continue; 798 799 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST || 800 (HAS_DP20(dev_priv) && 801 (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B)) 802 mst_pipe_mask |= BIT(p); 803 804 *pipe_mask |= BIT(p); 805 } 806 807 if (!*pipe_mask) 808 drm_dbg_kms(&dev_priv->drm, 809 "No pipe for [ENCODER:%d:%s] found\n", 810 encoder->base.base.id, encoder->base.name); 811 812 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 813 drm_dbg_kms(&dev_priv->drm, 814 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 815 encoder->base.base.id, encoder->base.name, 816 *pipe_mask); 817 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 818 } 819 820 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 821 drm_dbg_kms(&dev_priv->drm, 822 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", 823 encoder->base.base.id, encoder->base.name, 824 *pipe_mask, mst_pipe_mask); 825 else 826 *is_dp_mst = mst_pipe_mask; 827 828 out: 829 if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) { 830 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 831 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 832 BXT_PHY_LANE_POWERDOWN_ACK | 833 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 834 drm_err(&dev_priv->drm, 835 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 836 encoder->base.base.id, encoder->base.name, tmp); 837 } 838 839 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 840 } 841 842 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 843 enum pipe *pipe) 844 { 845 u8 pipe_mask; 846 bool is_mst; 847 848 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 849 850 if (is_mst || !pipe_mask) 851 return false; 852 853 *pipe = ffs(pipe_mask) - 1; 854 855 return true; 856 } 857 858 static enum intel_display_power_domain 859 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port) 860 { 861 /* ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 862 * DC states enabled at the same time, while for driver initiated AUX 863 * transfers we need the same AUX IOs to be powered but with DC states 864 * disabled. Accordingly use the AUX power domain here which leaves DC 865 * states enabled. 866 * However, for non-A AUX ports the corresponding non-EDP transcoders 867 * would have already enabled power well 2 and DC_OFF. This means we can 868 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a 869 * specific AUX_IO reference without powering up any extra wells. 870 * Note that PSR is enabled only on Port A even though this function 871 * returns the correct domain for other ports too. 872 */ 873 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A : 874 intel_aux_power_domain(dig_port); 875 } 876 877 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 878 struct intel_crtc_state *crtc_state) 879 { 880 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 881 struct intel_digital_port *dig_port; 882 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 883 884 /* 885 * TODO: Add support for MST encoders. Atm, the following should never 886 * happen since fake-MST encoders don't set their get_power_domains() 887 * hook. 888 */ 889 if (drm_WARN_ON(&dev_priv->drm, 890 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 891 return; 892 893 dig_port = enc_to_dig_port(encoder); 894 895 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 896 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 897 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 898 dig_port->ddi_io_power_domain); 899 } 900 901 /* 902 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC 903 * ports. 904 */ 905 if (intel_crtc_has_dp_encoder(crtc_state) || 906 intel_phy_is_tc(dev_priv, phy)) { 907 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref); 908 dig_port->aux_wakeref = 909 intel_display_power_get(dev_priv, 910 intel_ddi_main_link_aux_domain(dig_port)); 911 } 912 } 913 914 void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder, 915 const struct intel_crtc_state *crtc_state) 916 { 917 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 918 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 919 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 920 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 921 u32 val; 922 923 if (cpu_transcoder != TRANSCODER_EDP) { 924 if (DISPLAY_VER(dev_priv) >= 13) 925 val = TGL_TRANS_CLK_SEL_PORT(phy); 926 else if (DISPLAY_VER(dev_priv) >= 12) 927 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 928 else 929 val = TRANS_CLK_SEL_PORT(encoder->port); 930 931 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 932 } 933 } 934 935 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state) 936 { 937 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 938 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 939 940 if (cpu_transcoder != TRANSCODER_EDP) { 941 if (DISPLAY_VER(dev_priv) >= 12) 942 intel_de_write(dev_priv, 943 TRANS_CLK_SEL(cpu_transcoder), 944 TGL_TRANS_CLK_SEL_DISABLED); 945 else 946 intel_de_write(dev_priv, 947 TRANS_CLK_SEL(cpu_transcoder), 948 TRANS_CLK_SEL_DISABLED); 949 } 950 } 951 952 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 953 enum port port, u8 iboost) 954 { 955 u32 tmp; 956 957 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 958 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 959 if (iboost) 960 tmp |= iboost << BALANCE_LEG_SHIFT(port); 961 else 962 tmp |= BALANCE_LEG_DISABLE(port); 963 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 964 } 965 966 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 967 const struct intel_crtc_state *crtc_state, 968 int level) 969 { 970 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 971 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 972 u8 iboost; 973 974 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 975 iboost = intel_bios_encoder_hdmi_boost_level(encoder->devdata); 976 else 977 iboost = intel_bios_encoder_dp_boost_level(encoder->devdata); 978 979 if (iboost == 0) { 980 const struct intel_ddi_buf_trans *trans; 981 int n_entries; 982 983 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 984 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 985 return; 986 987 iboost = trans->entries[level].hsw.i_boost; 988 } 989 990 /* Make sure that the requested I_boost is valid */ 991 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 992 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); 993 return; 994 } 995 996 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); 997 998 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 999 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 1000 } 1001 1002 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1003 const struct intel_crtc_state *crtc_state) 1004 { 1005 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1006 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1007 int n_entries; 1008 1009 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1010 1011 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 1012 n_entries = 1; 1013 if (drm_WARN_ON(&dev_priv->drm, 1014 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1015 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1016 1017 return index_to_dp_signal_levels[n_entries - 1] & 1018 DP_TRAIN_VOLTAGE_SWING_MASK; 1019 } 1020 1021 /* 1022 * We assume that the full set of pre-emphasis values can be 1023 * used on all DDI platforms. Should that change we need to 1024 * rethink this code. 1025 */ 1026 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1027 { 1028 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1029 } 1030 1031 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1032 int lane) 1033 { 1034 if (crtc_state->port_clock > 600000) 1035 return 0; 1036 1037 if (crtc_state->lane_count == 4) 1038 return lane >= 1 ? LOADGEN_SELECT : 0; 1039 else 1040 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1041 } 1042 1043 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1044 const struct intel_crtc_state *crtc_state) 1045 { 1046 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1047 const struct intel_ddi_buf_trans *trans; 1048 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1049 int n_entries, ln; 1050 u32 val; 1051 1052 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1053 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1054 return; 1055 1056 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1057 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1058 1059 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1060 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1061 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, 1062 intel_dp->hobl_active ? val : 0); 1063 } 1064 1065 /* Set PORT_TX_DW5 */ 1066 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1067 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1068 TAP2_DISABLE | TAP3_DISABLE); 1069 val |= SCALING_MODE_SEL(0x2); 1070 val |= RTERM_SELECT(0x6); 1071 val |= TAP3_DISABLE; 1072 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1073 1074 /* Program PORT_TX_DW2 */ 1075 for (ln = 0; ln < 4; ln++) { 1076 int level = intel_ddi_level(encoder, crtc_state, ln); 1077 1078 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy), 1079 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1080 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1081 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1082 RCOMP_SCALAR(0x98)); 1083 } 1084 1085 /* Program PORT_TX_DW4 */ 1086 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1087 for (ln = 0; ln < 4; ln++) { 1088 int level = intel_ddi_level(encoder, crtc_state, ln); 1089 1090 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1091 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1092 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1093 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1094 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1095 } 1096 1097 /* Program PORT_TX_DW7 */ 1098 for (ln = 0; ln < 4; ln++) { 1099 int level = intel_ddi_level(encoder, crtc_state, ln); 1100 1101 intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy), 1102 N_SCALAR_MASK, 1103 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1104 } 1105 } 1106 1107 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1108 const struct intel_crtc_state *crtc_state) 1109 { 1110 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1111 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1112 u32 val; 1113 int ln; 1114 1115 /* 1116 * 1. If port type is eDP or DP, 1117 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1118 * else clear to 0b. 1119 */ 1120 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); 1121 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1122 val &= ~COMMON_KEEPER_EN; 1123 else 1124 val |= COMMON_KEEPER_EN; 1125 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 1126 1127 /* 2. Program loadgen select */ 1128 /* 1129 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1130 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1131 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1132 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1133 */ 1134 for (ln = 0; ln < 4; ln++) { 1135 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1136 LOADGEN_SELECT, 1137 icl_combo_phy_loadgen_select(crtc_state, ln)); 1138 } 1139 1140 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1141 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 1142 0, SUS_CLOCK_CONFIG); 1143 1144 /* 4. Clear training enable to change swing values */ 1145 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1146 val &= ~TX_TRAINING_EN; 1147 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1148 1149 /* 5. Program swing and de-emphasis */ 1150 icl_ddi_combo_vswing_program(encoder, crtc_state); 1151 1152 /* 6. Set training enable to trigger update */ 1153 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1154 val |= TX_TRAINING_EN; 1155 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1156 } 1157 1158 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1159 const struct intel_crtc_state *crtc_state) 1160 { 1161 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1162 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 1163 const struct intel_ddi_buf_trans *trans; 1164 int n_entries, ln; 1165 1166 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1167 return; 1168 1169 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1170 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1171 return; 1172 1173 for (ln = 0; ln < 2; ln++) { 1174 intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), 1175 CRI_USE_FS32, 0); 1176 intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), 1177 CRI_USE_FS32, 0); 1178 } 1179 1180 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1181 for (ln = 0; ln < 2; ln++) { 1182 int level; 1183 1184 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1185 1186 intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), 1187 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1188 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1189 1190 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1191 1192 intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), 1193 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1194 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1195 } 1196 1197 /* Program MG_TX_DRVCTRL with values from vswing table */ 1198 for (ln = 0; ln < 2; ln++) { 1199 int level; 1200 1201 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1202 1203 intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), 1204 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1205 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1206 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1207 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1208 CRI_TXDEEMPH_OVERRIDE_EN); 1209 1210 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1211 1212 intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), 1213 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1214 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1215 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1216 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1217 CRI_TXDEEMPH_OVERRIDE_EN); 1218 1219 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1220 } 1221 1222 /* 1223 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1224 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1225 * values from table for which TX1 and TX2 enabled. 1226 */ 1227 for (ln = 0; ln < 2; ln++) { 1228 intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port), 1229 CFG_LOW_RATE_LKREN_EN, 1230 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1231 } 1232 1233 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1234 for (ln = 0; ln < 2; ln++) { 1235 intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port), 1236 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1237 CFG_AMI_CK_DIV_OVERRIDE_EN, 1238 crtc_state->port_clock > 500000 ? 1239 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1240 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1241 1242 intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port), 1243 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1244 CFG_AMI_CK_DIV_OVERRIDE_EN, 1245 crtc_state->port_clock > 500000 ? 1246 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1247 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1248 } 1249 1250 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1251 for (ln = 0; ln < 2; ln++) { 1252 intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 1253 0, CRI_CALCINIT); 1254 intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 1255 0, CRI_CALCINIT); 1256 } 1257 } 1258 1259 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1260 const struct intel_crtc_state *crtc_state) 1261 { 1262 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1263 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 1264 const struct intel_ddi_buf_trans *trans; 1265 int n_entries, ln; 1266 1267 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1268 return; 1269 1270 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1271 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1272 return; 1273 1274 for (ln = 0; ln < 2; ln++) { 1275 int level; 1276 1277 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 1278 HIP_INDEX_VAL(tc_port, ln)); 1279 1280 intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0); 1281 1282 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1283 1284 intel_de_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port), 1285 DKL_TX_PRESHOOT_COEFF_MASK | 1286 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1287 DKL_TX_VSWING_CONTROL_MASK, 1288 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1289 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1290 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1291 1292 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1293 1294 intel_de_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port), 1295 DKL_TX_PRESHOOT_COEFF_MASK | 1296 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1297 DKL_TX_VSWING_CONTROL_MASK, 1298 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1299 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1300 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1301 1302 intel_de_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port), 1303 DKL_TX_DP20BITMODE, 0); 1304 1305 if (IS_ALDERLAKE_P(dev_priv)) { 1306 u32 val; 1307 1308 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1309 if (ln == 0) { 1310 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1311 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); 1312 } else { 1313 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); 1314 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); 1315 } 1316 } else { 1317 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1318 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); 1319 } 1320 1321 intel_de_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port), 1322 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | 1323 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, 1324 val); 1325 } 1326 } 1327 } 1328 1329 static int translate_signal_level(struct intel_dp *intel_dp, 1330 u8 signal_levels) 1331 { 1332 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1333 int i; 1334 1335 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1336 if (index_to_dp_signal_levels[i] == signal_levels) 1337 return i; 1338 } 1339 1340 drm_WARN(&i915->drm, 1, 1341 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1342 signal_levels); 1343 1344 return 0; 1345 } 1346 1347 static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1348 const struct intel_crtc_state *crtc_state, 1349 int lane) 1350 { 1351 u8 train_set = intel_dp->train_set[lane]; 1352 1353 if (intel_dp_is_uhbr(crtc_state)) { 1354 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1355 } else { 1356 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1357 DP_TRAIN_PRE_EMPHASIS_MASK); 1358 1359 return translate_signal_level(intel_dp, signal_levels); 1360 } 1361 } 1362 1363 int intel_ddi_level(struct intel_encoder *encoder, 1364 const struct intel_crtc_state *crtc_state, 1365 int lane) 1366 { 1367 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1368 const struct intel_ddi_buf_trans *trans; 1369 int level, n_entries; 1370 1371 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1372 if (drm_WARN_ON_ONCE(&i915->drm, !trans)) 1373 return 0; 1374 1375 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1376 level = intel_ddi_hdmi_level(encoder, trans); 1377 else 1378 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1379 lane); 1380 1381 if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries)) 1382 level = n_entries - 1; 1383 1384 return level; 1385 } 1386 1387 static void 1388 hsw_set_signal_levels(struct intel_encoder *encoder, 1389 const struct intel_crtc_state *crtc_state) 1390 { 1391 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1392 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1393 int level = intel_ddi_level(encoder, crtc_state, 0); 1394 enum port port = encoder->port; 1395 u32 signal_levels; 1396 1397 if (has_iboost(dev_priv)) 1398 skl_ddi_set_iboost(encoder, crtc_state, level); 1399 1400 /* HDMI ignores the rest */ 1401 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1402 return; 1403 1404 signal_levels = DDI_BUF_TRANS_SELECT(level); 1405 1406 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1407 signal_levels); 1408 1409 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1410 intel_dp->DP |= signal_levels; 1411 1412 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 1413 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 1414 } 1415 1416 static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1417 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1418 { 1419 mutex_lock(&i915->dpll.lock); 1420 1421 intel_de_rmw(i915, reg, clk_sel_mask, clk_sel); 1422 1423 /* 1424 * "This step and the step before must be 1425 * done with separate register writes." 1426 */ 1427 intel_de_rmw(i915, reg, clk_off, 0); 1428 1429 mutex_unlock(&i915->dpll.lock); 1430 } 1431 1432 static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1433 u32 clk_off) 1434 { 1435 mutex_lock(&i915->dpll.lock); 1436 1437 intel_de_rmw(i915, reg, 0, clk_off); 1438 1439 mutex_unlock(&i915->dpll.lock); 1440 } 1441 1442 static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg, 1443 u32 clk_off) 1444 { 1445 return !(intel_de_read(i915, reg) & clk_off); 1446 } 1447 1448 static struct intel_shared_dpll * 1449 _icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg, 1450 u32 clk_sel_mask, u32 clk_sel_shift) 1451 { 1452 enum intel_dpll_id id; 1453 1454 id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift; 1455 1456 return intel_get_shared_dpll_by_id(i915, id); 1457 } 1458 1459 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1460 const struct intel_crtc_state *crtc_state) 1461 { 1462 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1463 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1464 enum phy phy = intel_port_to_phy(i915, encoder->port); 1465 1466 if (drm_WARN_ON(&i915->drm, !pll)) 1467 return; 1468 1469 _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1470 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1471 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1472 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1473 } 1474 1475 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1476 { 1477 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1478 enum phy phy = intel_port_to_phy(i915, encoder->port); 1479 1480 _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1481 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1482 } 1483 1484 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1485 { 1486 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1487 enum phy phy = intel_port_to_phy(i915, encoder->port); 1488 1489 return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy), 1490 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1491 } 1492 1493 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1494 { 1495 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1496 enum phy phy = intel_port_to_phy(i915, encoder->port); 1497 1498 return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy), 1499 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1500 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1501 } 1502 1503 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1504 const struct intel_crtc_state *crtc_state) 1505 { 1506 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1507 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1508 enum phy phy = intel_port_to_phy(i915, encoder->port); 1509 1510 if (drm_WARN_ON(&i915->drm, !pll)) 1511 return; 1512 1513 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1514 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1515 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1516 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1517 } 1518 1519 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1520 { 1521 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1522 enum phy phy = intel_port_to_phy(i915, encoder->port); 1523 1524 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1525 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1526 } 1527 1528 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1529 { 1530 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1531 enum phy phy = intel_port_to_phy(i915, encoder->port); 1532 1533 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1534 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1535 } 1536 1537 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1538 { 1539 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1540 enum phy phy = intel_port_to_phy(i915, encoder->port); 1541 1542 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1543 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1544 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1545 } 1546 1547 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1548 const struct intel_crtc_state *crtc_state) 1549 { 1550 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1551 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1552 enum phy phy = intel_port_to_phy(i915, encoder->port); 1553 1554 if (drm_WARN_ON(&i915->drm, !pll)) 1555 return; 1556 1557 /* 1558 * If we fail this, something went very wrong: first 2 PLLs should be 1559 * used by first 2 phys and last 2 PLLs by last phys 1560 */ 1561 if (drm_WARN_ON(&i915->drm, 1562 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1563 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1564 return; 1565 1566 _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1567 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1568 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1569 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1570 } 1571 1572 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1573 { 1574 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1575 enum phy phy = intel_port_to_phy(i915, encoder->port); 1576 1577 _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1578 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1579 } 1580 1581 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1582 { 1583 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1584 enum phy phy = intel_port_to_phy(i915, encoder->port); 1585 1586 return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy), 1587 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1588 } 1589 1590 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1591 { 1592 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1593 enum phy phy = intel_port_to_phy(i915, encoder->port); 1594 enum intel_dpll_id id; 1595 u32 val; 1596 1597 val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy)); 1598 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1599 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1600 id = val; 1601 1602 /* 1603 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1604 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1605 * bit for phy C and D. 1606 */ 1607 if (phy >= PHY_C) 1608 id += DPLL_ID_DG1_DPLL2; 1609 1610 return intel_get_shared_dpll_by_id(i915, id); 1611 } 1612 1613 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1614 const struct intel_crtc_state *crtc_state) 1615 { 1616 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1617 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1618 enum phy phy = intel_port_to_phy(i915, encoder->port); 1619 1620 if (drm_WARN_ON(&i915->drm, !pll)) 1621 return; 1622 1623 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1624 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1625 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1626 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1627 } 1628 1629 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1630 { 1631 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1632 enum phy phy = intel_port_to_phy(i915, encoder->port); 1633 1634 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1635 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1636 } 1637 1638 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1639 { 1640 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1641 enum phy phy = intel_port_to_phy(i915, encoder->port); 1642 1643 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1644 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1645 } 1646 1647 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1648 { 1649 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1650 enum phy phy = intel_port_to_phy(i915, encoder->port); 1651 1652 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1653 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1654 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1655 } 1656 1657 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1658 const struct intel_crtc_state *crtc_state) 1659 { 1660 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1661 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1662 enum port port = encoder->port; 1663 1664 if (drm_WARN_ON(&i915->drm, !pll)) 1665 return; 1666 1667 /* 1668 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1669 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1670 */ 1671 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1672 1673 icl_ddi_combo_enable_clock(encoder, crtc_state); 1674 } 1675 1676 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1677 { 1678 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1679 enum port port = encoder->port; 1680 1681 icl_ddi_combo_disable_clock(encoder); 1682 1683 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1684 } 1685 1686 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1687 { 1688 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1689 enum port port = encoder->port; 1690 u32 tmp; 1691 1692 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1693 1694 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1695 return false; 1696 1697 return icl_ddi_combo_is_clock_enabled(encoder); 1698 } 1699 1700 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1701 const struct intel_crtc_state *crtc_state) 1702 { 1703 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1704 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1705 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1706 enum port port = encoder->port; 1707 1708 if (drm_WARN_ON(&i915->drm, !pll)) 1709 return; 1710 1711 intel_de_write(i915, DDI_CLK_SEL(port), 1712 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1713 1714 mutex_lock(&i915->dpll.lock); 1715 1716 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1717 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1718 1719 mutex_unlock(&i915->dpll.lock); 1720 } 1721 1722 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1723 { 1724 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1725 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1726 enum port port = encoder->port; 1727 1728 mutex_lock(&i915->dpll.lock); 1729 1730 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1731 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1732 1733 mutex_unlock(&i915->dpll.lock); 1734 1735 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1736 } 1737 1738 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1739 { 1740 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1741 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1742 enum port port = encoder->port; 1743 u32 tmp; 1744 1745 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1746 1747 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1748 return false; 1749 1750 tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0); 1751 1752 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1753 } 1754 1755 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1756 { 1757 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1758 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1759 enum port port = encoder->port; 1760 enum intel_dpll_id id; 1761 u32 tmp; 1762 1763 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1764 1765 switch (tmp & DDI_CLK_SEL_MASK) { 1766 case DDI_CLK_SEL_TBT_162: 1767 case DDI_CLK_SEL_TBT_270: 1768 case DDI_CLK_SEL_TBT_540: 1769 case DDI_CLK_SEL_TBT_810: 1770 id = DPLL_ID_ICL_TBTPLL; 1771 break; 1772 case DDI_CLK_SEL_MG: 1773 id = icl_tc_port_to_pll_id(tc_port); 1774 break; 1775 default: 1776 MISSING_CASE(tmp); 1777 fallthrough; 1778 case DDI_CLK_SEL_NONE: 1779 return NULL; 1780 } 1781 1782 return intel_get_shared_dpll_by_id(i915, id); 1783 } 1784 1785 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1786 { 1787 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1788 enum intel_dpll_id id; 1789 1790 switch (encoder->port) { 1791 case PORT_A: 1792 id = DPLL_ID_SKL_DPLL0; 1793 break; 1794 case PORT_B: 1795 id = DPLL_ID_SKL_DPLL1; 1796 break; 1797 case PORT_C: 1798 id = DPLL_ID_SKL_DPLL2; 1799 break; 1800 default: 1801 MISSING_CASE(encoder->port); 1802 return NULL; 1803 } 1804 1805 return intel_get_shared_dpll_by_id(i915, id); 1806 } 1807 1808 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1809 const struct intel_crtc_state *crtc_state) 1810 { 1811 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1812 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1813 enum port port = encoder->port; 1814 1815 if (drm_WARN_ON(&i915->drm, !pll)) 1816 return; 1817 1818 mutex_lock(&i915->dpll.lock); 1819 1820 intel_de_rmw(i915, DPLL_CTRL2, 1821 DPLL_CTRL2_DDI_CLK_OFF(port) | 1822 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1823 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1824 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1825 1826 mutex_unlock(&i915->dpll.lock); 1827 } 1828 1829 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1830 { 1831 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1832 enum port port = encoder->port; 1833 1834 mutex_lock(&i915->dpll.lock); 1835 1836 intel_de_rmw(i915, DPLL_CTRL2, 1837 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1838 1839 mutex_unlock(&i915->dpll.lock); 1840 } 1841 1842 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1843 { 1844 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1845 enum port port = encoder->port; 1846 1847 /* 1848 * FIXME Not sure if the override affects both 1849 * the PLL selection and the CLK_OFF bit. 1850 */ 1851 return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 1852 } 1853 1854 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 1855 { 1856 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1857 enum port port = encoder->port; 1858 enum intel_dpll_id id; 1859 u32 tmp; 1860 1861 tmp = intel_de_read(i915, DPLL_CTRL2); 1862 1863 /* 1864 * FIXME Not sure if the override affects both 1865 * the PLL selection and the CLK_OFF bit. 1866 */ 1867 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 1868 return NULL; 1869 1870 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 1871 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 1872 1873 return intel_get_shared_dpll_by_id(i915, id); 1874 } 1875 1876 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 1877 const struct intel_crtc_state *crtc_state) 1878 { 1879 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1880 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1881 enum port port = encoder->port; 1882 1883 if (drm_WARN_ON(&i915->drm, !pll)) 1884 return; 1885 1886 intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 1887 } 1888 1889 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 1890 { 1891 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1892 enum port port = encoder->port; 1893 1894 intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 1895 } 1896 1897 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 1898 { 1899 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1900 enum port port = encoder->port; 1901 1902 return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 1903 } 1904 1905 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 1906 { 1907 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1908 enum port port = encoder->port; 1909 enum intel_dpll_id id; 1910 u32 tmp; 1911 1912 tmp = intel_de_read(i915, PORT_CLK_SEL(port)); 1913 1914 switch (tmp & PORT_CLK_SEL_MASK) { 1915 case PORT_CLK_SEL_WRPLL1: 1916 id = DPLL_ID_WRPLL1; 1917 break; 1918 case PORT_CLK_SEL_WRPLL2: 1919 id = DPLL_ID_WRPLL2; 1920 break; 1921 case PORT_CLK_SEL_SPLL: 1922 id = DPLL_ID_SPLL; 1923 break; 1924 case PORT_CLK_SEL_LCPLL_810: 1925 id = DPLL_ID_LCPLL_810; 1926 break; 1927 case PORT_CLK_SEL_LCPLL_1350: 1928 id = DPLL_ID_LCPLL_1350; 1929 break; 1930 case PORT_CLK_SEL_LCPLL_2700: 1931 id = DPLL_ID_LCPLL_2700; 1932 break; 1933 default: 1934 MISSING_CASE(tmp); 1935 fallthrough; 1936 case PORT_CLK_SEL_NONE: 1937 return NULL; 1938 } 1939 1940 return intel_get_shared_dpll_by_id(i915, id); 1941 } 1942 1943 void intel_ddi_enable_clock(struct intel_encoder *encoder, 1944 const struct intel_crtc_state *crtc_state) 1945 { 1946 if (encoder->enable_clock) 1947 encoder->enable_clock(encoder, crtc_state); 1948 } 1949 1950 void intel_ddi_disable_clock(struct intel_encoder *encoder) 1951 { 1952 if (encoder->disable_clock) 1953 encoder->disable_clock(encoder); 1954 } 1955 1956 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 1957 { 1958 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1959 u32 port_mask; 1960 bool ddi_clk_needed; 1961 1962 /* 1963 * In case of DP MST, we sanitize the primary encoder only, not the 1964 * virtual ones. 1965 */ 1966 if (encoder->type == INTEL_OUTPUT_DP_MST) 1967 return; 1968 1969 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 1970 u8 pipe_mask; 1971 bool is_mst; 1972 1973 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 1974 /* 1975 * In the unlikely case that BIOS enables DP in MST mode, just 1976 * warn since our MST HW readout is incomplete. 1977 */ 1978 if (drm_WARN_ON(&i915->drm, is_mst)) 1979 return; 1980 } 1981 1982 port_mask = BIT(encoder->port); 1983 ddi_clk_needed = encoder->base.crtc; 1984 1985 if (encoder->type == INTEL_OUTPUT_DSI) { 1986 struct intel_encoder *other_encoder; 1987 1988 port_mask = intel_dsi_encoder_ports(encoder); 1989 /* 1990 * Sanity check that we haven't incorrectly registered another 1991 * encoder using any of the ports of this DSI encoder. 1992 */ 1993 for_each_intel_encoder(&i915->drm, other_encoder) { 1994 if (other_encoder == encoder) 1995 continue; 1996 1997 if (drm_WARN_ON(&i915->drm, 1998 port_mask & BIT(other_encoder->port))) 1999 return; 2000 } 2001 /* 2002 * For DSI we keep the ddi clocks gated 2003 * except during enable/disable sequence. 2004 */ 2005 ddi_clk_needed = false; 2006 } 2007 2008 if (ddi_clk_needed || !encoder->is_clock_enabled || 2009 !encoder->is_clock_enabled(encoder)) 2010 return; 2011 2012 drm_notice(&i915->drm, 2013 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2014 encoder->base.base.id, encoder->base.name); 2015 2016 encoder->disable_clock(encoder); 2017 } 2018 2019 static void 2020 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2021 const struct intel_crtc_state *crtc_state) 2022 { 2023 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2024 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port); 2025 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); 2026 u32 ln0, ln1, pin_assignment; 2027 u8 width; 2028 2029 if (!intel_phy_is_tc(dev_priv, phy) || 2030 intel_tc_port_in_tbt_alt_mode(dig_port)) 2031 return; 2032 2033 if (DISPLAY_VER(dev_priv) >= 12) { 2034 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2035 HIP_INDEX_VAL(tc_port, 0x0)); 2036 ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); 2037 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2038 HIP_INDEX_VAL(tc_port, 0x1)); 2039 ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); 2040 } else { 2041 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 2042 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 2043 } 2044 2045 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2046 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2047 2048 /* DPPATC */ 2049 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 2050 width = crtc_state->lane_count; 2051 2052 switch (pin_assignment) { 2053 case 0x0: 2054 drm_WARN_ON(&dev_priv->drm, 2055 !intel_tc_port_in_legacy_mode(dig_port)); 2056 if (width == 1) { 2057 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2058 } else { 2059 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2060 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2061 } 2062 break; 2063 case 0x1: 2064 if (width == 4) { 2065 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2066 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2067 } 2068 break; 2069 case 0x2: 2070 if (width == 2) { 2071 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2072 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2073 } 2074 break; 2075 case 0x3: 2076 case 0x5: 2077 if (width == 1) { 2078 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2079 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2080 } else { 2081 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2082 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2083 } 2084 break; 2085 case 0x4: 2086 case 0x6: 2087 if (width == 1) { 2088 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2089 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2090 } else { 2091 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2092 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2093 } 2094 break; 2095 default: 2096 MISSING_CASE(pin_assignment); 2097 } 2098 2099 if (DISPLAY_VER(dev_priv) >= 12) { 2100 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2101 HIP_INDEX_VAL(tc_port, 0x0)); 2102 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0); 2103 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2104 HIP_INDEX_VAL(tc_port, 0x1)); 2105 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1); 2106 } else { 2107 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 2108 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 2109 } 2110 } 2111 2112 static enum transcoder 2113 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2114 { 2115 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2116 return crtc_state->mst_master_transcoder; 2117 else 2118 return crtc_state->cpu_transcoder; 2119 } 2120 2121 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2122 const struct intel_crtc_state *crtc_state) 2123 { 2124 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2125 2126 if (DISPLAY_VER(dev_priv) >= 12) 2127 return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state)); 2128 else 2129 return DP_TP_CTL(encoder->port); 2130 } 2131 2132 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2133 const struct intel_crtc_state *crtc_state) 2134 { 2135 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2136 2137 if (DISPLAY_VER(dev_priv) >= 12) 2138 return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state)); 2139 else 2140 return DP_TP_STATUS(encoder->port); 2141 } 2142 2143 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2144 const struct intel_crtc_state *crtc_state, 2145 bool enable) 2146 { 2147 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2148 2149 if (!crtc_state->vrr.enable) 2150 return; 2151 2152 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2153 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2154 drm_dbg_kms(&i915->drm, 2155 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2156 str_enable_disable(enable)); 2157 } 2158 2159 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2160 const struct intel_crtc_state *crtc_state) 2161 { 2162 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2163 2164 if (!crtc_state->fec_enable) 2165 return; 2166 2167 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0) 2168 drm_dbg_kms(&i915->drm, 2169 "Failed to set FEC_READY in the sink\n"); 2170 } 2171 2172 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2173 const struct intel_crtc_state *crtc_state) 2174 { 2175 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2176 struct intel_dp *intel_dp; 2177 u32 val; 2178 2179 if (!crtc_state->fec_enable) 2180 return; 2181 2182 intel_dp = enc_to_intel_dp(encoder); 2183 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2184 val |= DP_TP_CTL_FEC_ENABLE; 2185 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 2186 } 2187 2188 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder, 2189 const struct intel_crtc_state *crtc_state) 2190 { 2191 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2192 struct intel_dp *intel_dp; 2193 u32 val; 2194 2195 if (!crtc_state->fec_enable) 2196 return; 2197 2198 intel_dp = enc_to_intel_dp(encoder); 2199 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2200 val &= ~DP_TP_CTL_FEC_ENABLE; 2201 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 2202 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2203 } 2204 2205 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2206 const struct intel_crtc_state *crtc_state) 2207 { 2208 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2209 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2210 enum phy phy = intel_port_to_phy(i915, encoder->port); 2211 2212 if (intel_phy_is_combo(i915, phy)) { 2213 bool lane_reversal = 2214 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 2215 2216 intel_combo_phy_power_up_lanes(i915, phy, false, 2217 crtc_state->lane_count, 2218 lane_reversal); 2219 } 2220 } 2221 2222 /* Splitter enable for eDP MSO is limited to certain pipes. */ 2223 static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915) 2224 { 2225 if (IS_ALDERLAKE_P(i915)) 2226 return BIT(PIPE_A) | BIT(PIPE_B); 2227 else 2228 return BIT(PIPE_A); 2229 } 2230 2231 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2232 struct intel_crtc_state *pipe_config) 2233 { 2234 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2235 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2236 enum pipe pipe = crtc->pipe; 2237 u32 dss1; 2238 2239 if (!HAS_MSO(i915)) 2240 return; 2241 2242 dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); 2243 2244 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2245 if (!pipe_config->splitter.enable) 2246 return; 2247 2248 if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) { 2249 pipe_config->splitter.enable = false; 2250 return; 2251 } 2252 2253 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2254 default: 2255 drm_WARN(&i915->drm, true, 2256 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2257 fallthrough; 2258 case SPLITTER_CONFIGURATION_2_SEGMENT: 2259 pipe_config->splitter.link_count = 2; 2260 break; 2261 case SPLITTER_CONFIGURATION_4_SEGMENT: 2262 pipe_config->splitter.link_count = 4; 2263 break; 2264 } 2265 2266 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2267 } 2268 2269 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2270 { 2271 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2272 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2273 enum pipe pipe = crtc->pipe; 2274 u32 dss1 = 0; 2275 2276 if (!HAS_MSO(i915)) 2277 return; 2278 2279 if (crtc_state->splitter.enable) { 2280 dss1 |= SPLITTER_ENABLE; 2281 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2282 if (crtc_state->splitter.link_count == 2) 2283 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2284 else 2285 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2286 } 2287 2288 intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), 2289 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2290 OVERLAP_PIXELS_MASK, dss1); 2291 } 2292 2293 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2294 struct intel_encoder *encoder, 2295 const struct intel_crtc_state *crtc_state, 2296 const struct drm_connector_state *conn_state) 2297 { 2298 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2299 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2300 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2301 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2302 2303 intel_dp_set_link_params(intel_dp, 2304 crtc_state->port_clock, 2305 crtc_state->lane_count); 2306 2307 /* 2308 * We only configure what the register value will be here. Actual 2309 * enabling happens during link training farther down. 2310 */ 2311 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2312 2313 /* 2314 * 1. Enable Power Wells 2315 * 2316 * This was handled at the beginning of intel_atomic_commit_tail(), 2317 * before we called down into this function. 2318 */ 2319 2320 /* 2. Enable Panel Power if PPS is required */ 2321 intel_pps_on(intel_dp); 2322 2323 /* 2324 * 3. For non-TBT Type-C ports, set FIA lane count 2325 * (DFLEXDPSP.DPX4TXLATC) 2326 * 2327 * This was done before tgl_ddi_pre_enable_dp by 2328 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2329 */ 2330 2331 /* 2332 * 4. Enable the port PLL. 2333 * 2334 * The PLL enabling itself was already done before this function by 2335 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 2336 * configure the PLL to port mapping here. 2337 */ 2338 intel_ddi_enable_clock(encoder, crtc_state); 2339 2340 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2341 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2342 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2343 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2344 dig_port->ddi_io_power_domain); 2345 } 2346 2347 /* 6. Program DP_MODE */ 2348 icl_program_mg_dp_mode(dig_port, crtc_state); 2349 2350 /* 2351 * 7. The rest of the below are substeps under the bspec's "Enable and 2352 * Train Display Port" step. Note that steps that are specific to 2353 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2354 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2355 * us when active_mst_links==0, so any steps designated for "single 2356 * stream or multi-stream master transcoder" can just be performed 2357 * unconditionally here. 2358 */ 2359 2360 /* 2361 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2362 * Transcoder. 2363 */ 2364 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2365 2366 if (HAS_DP20(dev_priv)) 2367 intel_ddi_config_transcoder_dp2(encoder, crtc_state); 2368 2369 /* 2370 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2371 * Transport Select 2372 */ 2373 intel_ddi_config_transcoder_func(encoder, crtc_state); 2374 2375 /* 2376 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2377 * selected 2378 * 2379 * This will be handled by the intel_dp_start_link_train() farther 2380 * down this function. 2381 */ 2382 2383 /* 7.e Configure voltage swing and related IO settings */ 2384 encoder->set_signal_levels(encoder, crtc_state); 2385 2386 /* 2387 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2388 * the used lanes of the DDI. 2389 */ 2390 intel_ddi_power_up_lanes(encoder, crtc_state); 2391 2392 /* 2393 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2394 */ 2395 intel_ddi_mso_configure(crtc_state); 2396 2397 if (!is_mst) 2398 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2399 2400 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2401 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); 2402 /* 2403 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2404 * in the FEC_CONFIGURATION register to 1 before initiating link 2405 * training 2406 */ 2407 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 2408 2409 intel_dp_check_frl_training(intel_dp); 2410 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2411 2412 /* 2413 * 7.i Follow DisplayPort specification training sequence (see notes for 2414 * failure handling) 2415 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2416 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2417 * (timeout after 800 us) 2418 */ 2419 intel_dp_start_link_train(intel_dp, crtc_state); 2420 2421 /* 7.k Set DP_TP_CTL link training to Normal */ 2422 if (!is_trans_port_sync_mode(crtc_state)) 2423 intel_dp_stop_link_train(intel_dp, crtc_state); 2424 2425 /* 7.l Configure and enable FEC if needed */ 2426 intel_ddi_enable_fec(encoder, crtc_state); 2427 2428 intel_dsc_dp_pps_write(encoder, crtc_state); 2429 } 2430 2431 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2432 struct intel_encoder *encoder, 2433 const struct intel_crtc_state *crtc_state, 2434 const struct drm_connector_state *conn_state) 2435 { 2436 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2437 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2438 enum port port = encoder->port; 2439 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2440 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2441 2442 if (DISPLAY_VER(dev_priv) < 11) 2443 drm_WARN_ON(&dev_priv->drm, 2444 is_mst && (port == PORT_A || port == PORT_E)); 2445 else 2446 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 2447 2448 intel_dp_set_link_params(intel_dp, 2449 crtc_state->port_clock, 2450 crtc_state->lane_count); 2451 2452 /* 2453 * We only configure what the register value will be here. Actual 2454 * enabling happens during link training farther down. 2455 */ 2456 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2457 2458 intel_pps_on(intel_dp); 2459 2460 intel_ddi_enable_clock(encoder, crtc_state); 2461 2462 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2463 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2464 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2465 dig_port->ddi_io_power_domain); 2466 } 2467 2468 icl_program_mg_dp_mode(dig_port, crtc_state); 2469 2470 if (has_buf_trans_select(dev_priv)) 2471 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2472 2473 encoder->set_signal_levels(encoder, crtc_state); 2474 2475 intel_ddi_power_up_lanes(encoder, crtc_state); 2476 2477 if (!is_mst) 2478 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2479 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2480 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, 2481 true); 2482 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 2483 intel_dp_start_link_train(intel_dp, crtc_state); 2484 if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && 2485 !is_trans_port_sync_mode(crtc_state)) 2486 intel_dp_stop_link_train(intel_dp, crtc_state); 2487 2488 intel_ddi_enable_fec(encoder, crtc_state); 2489 2490 if (!is_mst) 2491 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2492 2493 intel_dsc_dp_pps_write(encoder, crtc_state); 2494 } 2495 2496 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2497 struct intel_encoder *encoder, 2498 const struct intel_crtc_state *crtc_state, 2499 const struct drm_connector_state *conn_state) 2500 { 2501 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2502 2503 if (DISPLAY_VER(dev_priv) >= 12) 2504 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2505 else 2506 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2507 2508 /* MST will call a setting of MSA after an allocating of Virtual Channel 2509 * from MST encoder pre_enable callback. 2510 */ 2511 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2512 intel_ddi_set_dp_msa(crtc_state, conn_state); 2513 } 2514 2515 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2516 struct intel_encoder *encoder, 2517 const struct intel_crtc_state *crtc_state, 2518 const struct drm_connector_state *conn_state) 2519 { 2520 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2521 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2522 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2523 2524 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2525 intel_ddi_enable_clock(encoder, crtc_state); 2526 2527 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2528 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2529 dig_port->ddi_io_power_domain); 2530 2531 icl_program_mg_dp_mode(dig_port, crtc_state); 2532 2533 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2534 2535 dig_port->set_infoframes(encoder, 2536 crtc_state->has_infoframe, 2537 crtc_state, conn_state); 2538 } 2539 2540 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 2541 struct intel_encoder *encoder, 2542 const struct intel_crtc_state *crtc_state, 2543 const struct drm_connector_state *conn_state) 2544 { 2545 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2546 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2547 enum pipe pipe = crtc->pipe; 2548 2549 /* 2550 * When called from DP MST code: 2551 * - conn_state will be NULL 2552 * - encoder will be the main encoder (ie. mst->primary) 2553 * - the main connector associated with this port 2554 * won't be active or linked to a crtc 2555 * - crtc_state will be the state of the first stream to 2556 * be activated on this port, and it may not be the same 2557 * stream that will be deactivated last, but each stream 2558 * should have a state that is identical when it comes to 2559 * the DP link parameteres 2560 */ 2561 2562 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 2563 2564 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2565 2566 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 2567 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 2568 conn_state); 2569 } else { 2570 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2571 2572 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 2573 conn_state); 2574 2575 /* FIXME precompute everything properly */ 2576 /* FIXME how do we turn infoframes off again? */ 2577 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) 2578 dig_port->set_infoframes(encoder, 2579 crtc_state->has_infoframe, 2580 crtc_state, conn_state); 2581 } 2582 } 2583 2584 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 2585 const struct intel_crtc_state *crtc_state) 2586 { 2587 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2588 enum port port = encoder->port; 2589 bool wait = false; 2590 u32 val; 2591 2592 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2593 if (val & DDI_BUF_CTL_ENABLE) { 2594 val &= ~DDI_BUF_CTL_ENABLE; 2595 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 2596 wait = true; 2597 } 2598 2599 if (intel_crtc_has_dp_encoder(crtc_state)) { 2600 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2601 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 2602 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 2603 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 2604 } 2605 2606 /* Disable FEC in DP Sink */ 2607 intel_ddi_disable_fec_state(encoder, crtc_state); 2608 2609 if (wait) 2610 intel_wait_ddi_buf_idle(dev_priv, port); 2611 } 2612 2613 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 2614 struct intel_encoder *encoder, 2615 const struct intel_crtc_state *old_crtc_state, 2616 const struct drm_connector_state *old_conn_state) 2617 { 2618 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2619 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2620 struct intel_dp *intel_dp = &dig_port->dp; 2621 bool is_mst = intel_crtc_has_type(old_crtc_state, 2622 INTEL_OUTPUT_DP_MST); 2623 2624 if (!is_mst) 2625 intel_dp_set_infoframes(encoder, false, 2626 old_crtc_state, old_conn_state); 2627 2628 /* 2629 * Power down sink before disabling the port, otherwise we end 2630 * up getting interrupts from the sink on detecting link loss. 2631 */ 2632 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 2633 2634 if (DISPLAY_VER(dev_priv) >= 12) { 2635 if (is_mst) { 2636 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 2637 u32 val; 2638 2639 val = intel_de_read(dev_priv, 2640 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 2641 val &= ~(TGL_TRANS_DDI_PORT_MASK | 2642 TRANS_DDI_MODE_SELECT_MASK); 2643 intel_de_write(dev_priv, 2644 TRANS_DDI_FUNC_CTL(cpu_transcoder), 2645 val); 2646 } 2647 } else { 2648 if (!is_mst) 2649 intel_ddi_disable_pipe_clock(old_crtc_state); 2650 } 2651 2652 intel_disable_ddi_buf(encoder, old_crtc_state); 2653 2654 /* 2655 * From TGL spec: "If single stream or multi-stream master transcoder: 2656 * Configure Transcoder Clock select to direct no clock to the 2657 * transcoder" 2658 */ 2659 if (DISPLAY_VER(dev_priv) >= 12) 2660 intel_ddi_disable_pipe_clock(old_crtc_state); 2661 2662 intel_pps_vdd_on(intel_dp); 2663 intel_pps_off(intel_dp); 2664 2665 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 2666 intel_display_power_put(dev_priv, 2667 dig_port->ddi_io_power_domain, 2668 fetch_and_zero(&dig_port->ddi_io_wakeref)); 2669 2670 intel_ddi_disable_clock(encoder); 2671 } 2672 2673 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 2674 struct intel_encoder *encoder, 2675 const struct intel_crtc_state *old_crtc_state, 2676 const struct drm_connector_state *old_conn_state) 2677 { 2678 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2679 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2680 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2681 2682 dig_port->set_infoframes(encoder, false, 2683 old_crtc_state, old_conn_state); 2684 2685 intel_ddi_disable_pipe_clock(old_crtc_state); 2686 2687 intel_disable_ddi_buf(encoder, old_crtc_state); 2688 2689 intel_display_power_put(dev_priv, 2690 dig_port->ddi_io_power_domain, 2691 fetch_and_zero(&dig_port->ddi_io_wakeref)); 2692 2693 intel_ddi_disable_clock(encoder); 2694 2695 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 2696 } 2697 2698 static void intel_ddi_post_disable(struct intel_atomic_state *state, 2699 struct intel_encoder *encoder, 2700 const struct intel_crtc_state *old_crtc_state, 2701 const struct drm_connector_state *old_conn_state) 2702 { 2703 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2704 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2705 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2706 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 2707 struct intel_crtc *slave_crtc; 2708 2709 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) { 2710 intel_crtc_vblank_off(old_crtc_state); 2711 2712 intel_disable_transcoder(old_crtc_state); 2713 2714 intel_vrr_disable(old_crtc_state); 2715 2716 intel_ddi_disable_transcoder_func(old_crtc_state); 2717 2718 intel_dsc_disable(old_crtc_state); 2719 2720 if (DISPLAY_VER(dev_priv) >= 9) 2721 skl_scaler_disable(old_crtc_state); 2722 else 2723 ilk_pfit_disable(old_crtc_state); 2724 } 2725 2726 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc, 2727 intel_crtc_bigjoiner_slave_pipes(old_crtc_state)) { 2728 const struct intel_crtc_state *old_slave_crtc_state = 2729 intel_atomic_get_old_crtc_state(state, slave_crtc); 2730 2731 intel_crtc_vblank_off(old_slave_crtc_state); 2732 2733 intel_dsc_disable(old_slave_crtc_state); 2734 skl_scaler_disable(old_slave_crtc_state); 2735 } 2736 2737 /* 2738 * When called from DP MST code: 2739 * - old_conn_state will be NULL 2740 * - encoder will be the main encoder (ie. mst->primary) 2741 * - the main connector associated with this port 2742 * won't be active or linked to a crtc 2743 * - old_crtc_state will be the state of the last stream to 2744 * be deactivated on this port, and it may not be the same 2745 * stream that was activated last, but each stream 2746 * should have a state that is identical when it comes to 2747 * the DP link parameteres 2748 */ 2749 2750 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 2751 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 2752 old_conn_state); 2753 else 2754 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 2755 old_conn_state); 2756 2757 if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port) 2758 intel_display_power_put(dev_priv, 2759 intel_ddi_main_link_aux_domain(dig_port), 2760 fetch_and_zero(&dig_port->aux_wakeref)); 2761 2762 if (is_tc_port) 2763 intel_tc_port_put_link(dig_port); 2764 } 2765 2766 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 2767 struct intel_encoder *encoder, 2768 const struct intel_crtc_state *crtc_state) 2769 { 2770 const struct drm_connector_state *conn_state; 2771 struct drm_connector *conn; 2772 int i; 2773 2774 if (!crtc_state->sync_mode_slaves_mask) 2775 return; 2776 2777 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 2778 struct intel_encoder *slave_encoder = 2779 to_intel_encoder(conn_state->best_encoder); 2780 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 2781 const struct intel_crtc_state *slave_crtc_state; 2782 2783 if (!slave_crtc) 2784 continue; 2785 2786 slave_crtc_state = 2787 intel_atomic_get_new_crtc_state(state, slave_crtc); 2788 2789 if (slave_crtc_state->master_transcoder != 2790 crtc_state->cpu_transcoder) 2791 continue; 2792 2793 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 2794 slave_crtc_state); 2795 } 2796 2797 usleep_range(200, 400); 2798 2799 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 2800 crtc_state); 2801 } 2802 2803 static void intel_enable_ddi_dp(struct intel_atomic_state *state, 2804 struct intel_encoder *encoder, 2805 const struct intel_crtc_state *crtc_state, 2806 const struct drm_connector_state *conn_state) 2807 { 2808 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2809 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2810 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2811 enum port port = encoder->port; 2812 2813 if (port == PORT_A && DISPLAY_VER(dev_priv) < 9) 2814 intel_dp_stop_link_train(intel_dp, crtc_state); 2815 2816 drm_connector_update_privacy_screen(conn_state); 2817 intel_edp_backlight_on(crtc_state, conn_state); 2818 2819 if (!dig_port->lspcon.active || dig_port->dp.has_hdmi_sink) 2820 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 2821 2822 intel_audio_codec_enable(encoder, crtc_state, conn_state); 2823 2824 trans_port_sync_stop_link_train(state, encoder, crtc_state); 2825 } 2826 2827 static i915_reg_t 2828 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 2829 enum port port) 2830 { 2831 static const enum transcoder trans[] = { 2832 [PORT_A] = TRANSCODER_EDP, 2833 [PORT_B] = TRANSCODER_A, 2834 [PORT_C] = TRANSCODER_B, 2835 [PORT_D] = TRANSCODER_C, 2836 [PORT_E] = TRANSCODER_A, 2837 }; 2838 2839 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9); 2840 2841 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) 2842 port = PORT_A; 2843 2844 return CHICKEN_TRANS(trans[port]); 2845 } 2846 2847 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, 2848 struct intel_encoder *encoder, 2849 const struct intel_crtc_state *crtc_state, 2850 const struct drm_connector_state *conn_state) 2851 { 2852 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2853 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2854 struct drm_connector *connector = conn_state->connector; 2855 enum port port = encoder->port; 2856 2857 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 2858 crtc_state->hdmi_high_tmds_clock_ratio, 2859 crtc_state->hdmi_scrambling)) 2860 drm_dbg_kms(&dev_priv->drm, 2861 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 2862 connector->base.id, connector->name); 2863 2864 if (has_buf_trans_select(dev_priv)) 2865 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 2866 2867 encoder->set_signal_levels(encoder, crtc_state); 2868 2869 /* Display WA #1143: skl,kbl,cfl */ 2870 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { 2871 /* 2872 * For some reason these chicken bits have been 2873 * stuffed into a transcoder register, event though 2874 * the bits affect a specific DDI port rather than 2875 * a specific transcoder. 2876 */ 2877 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 2878 u32 val; 2879 2880 val = intel_de_read(dev_priv, reg); 2881 2882 if (port == PORT_E) 2883 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 2884 DDIE_TRAINING_OVERRIDE_VALUE; 2885 else 2886 val |= DDI_TRAINING_OVERRIDE_ENABLE | 2887 DDI_TRAINING_OVERRIDE_VALUE; 2888 2889 intel_de_write(dev_priv, reg, val); 2890 intel_de_posting_read(dev_priv, reg); 2891 2892 udelay(1); 2893 2894 if (port == PORT_E) 2895 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 2896 DDIE_TRAINING_OVERRIDE_VALUE); 2897 else 2898 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 2899 DDI_TRAINING_OVERRIDE_VALUE); 2900 2901 intel_de_write(dev_priv, reg, val); 2902 } 2903 2904 intel_ddi_power_up_lanes(encoder, crtc_state); 2905 2906 /* In HDMI/DVI mode, the port width, and swing/emphasis values 2907 * are ignored so nothing special needs to be done besides 2908 * enabling the port. 2909 * 2910 * On ADL_P the PHY link rate and lane count must be programmed but 2911 * these are both 0 for HDMI. 2912 */ 2913 intel_de_write(dev_priv, DDI_BUF_CTL(port), 2914 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE); 2915 2916 intel_audio_codec_enable(encoder, crtc_state, conn_state); 2917 } 2918 2919 static void intel_enable_ddi(struct intel_atomic_state *state, 2920 struct intel_encoder *encoder, 2921 const struct intel_crtc_state *crtc_state, 2922 const struct drm_connector_state *conn_state) 2923 { 2924 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 2925 2926 if (!intel_crtc_is_bigjoiner_slave(crtc_state)) 2927 intel_ddi_enable_transcoder_func(encoder, crtc_state); 2928 2929 intel_vrr_enable(encoder, crtc_state); 2930 2931 intel_enable_transcoder(crtc_state); 2932 2933 intel_crtc_vblank_on(crtc_state); 2934 2935 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 2936 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state); 2937 else 2938 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state); 2939 2940 /* Enable hdcp if it's desired */ 2941 if (conn_state->content_protection == 2942 DRM_MODE_CONTENT_PROTECTION_DESIRED) 2943 intel_hdcp_enable(to_intel_connector(conn_state->connector), 2944 crtc_state, 2945 (u8)conn_state->hdcp_content_type); 2946 } 2947 2948 static void intel_disable_ddi_dp(struct intel_atomic_state *state, 2949 struct intel_encoder *encoder, 2950 const struct intel_crtc_state *old_crtc_state, 2951 const struct drm_connector_state *old_conn_state) 2952 { 2953 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2954 2955 intel_dp->link_trained = false; 2956 2957 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 2958 2959 intel_psr_disable(intel_dp, old_crtc_state); 2960 intel_edp_backlight_off(old_conn_state); 2961 /* Disable the decompression in DP Sink */ 2962 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, 2963 false); 2964 /* Disable Ignore_MSA bit in DP Sink */ 2965 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 2966 false); 2967 } 2968 2969 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state, 2970 struct intel_encoder *encoder, 2971 const struct intel_crtc_state *old_crtc_state, 2972 const struct drm_connector_state *old_conn_state) 2973 { 2974 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2975 struct drm_connector *connector = old_conn_state->connector; 2976 2977 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 2978 2979 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 2980 false, false)) 2981 drm_dbg_kms(&i915->drm, 2982 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 2983 connector->base.id, connector->name); 2984 } 2985 2986 static void intel_disable_ddi(struct intel_atomic_state *state, 2987 struct intel_encoder *encoder, 2988 const struct intel_crtc_state *old_crtc_state, 2989 const struct drm_connector_state *old_conn_state) 2990 { 2991 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 2992 2993 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 2994 intel_disable_ddi_hdmi(state, encoder, old_crtc_state, 2995 old_conn_state); 2996 else 2997 intel_disable_ddi_dp(state, encoder, old_crtc_state, 2998 old_conn_state); 2999 } 3000 3001 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3002 struct intel_encoder *encoder, 3003 const struct intel_crtc_state *crtc_state, 3004 const struct drm_connector_state *conn_state) 3005 { 3006 intel_ddi_set_dp_msa(crtc_state, conn_state); 3007 3008 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3009 3010 intel_backlight_update(state, encoder, crtc_state, conn_state); 3011 drm_connector_update_privacy_screen(conn_state); 3012 } 3013 3014 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3015 struct intel_encoder *encoder, 3016 const struct intel_crtc_state *crtc_state, 3017 const struct drm_connector_state *conn_state) 3018 { 3019 3020 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3021 !intel_encoder_is_mst(encoder)) 3022 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3023 conn_state); 3024 3025 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3026 } 3027 3028 static void 3029 intel_ddi_update_prepare(struct intel_atomic_state *state, 3030 struct intel_encoder *encoder, 3031 struct intel_crtc *crtc) 3032 { 3033 struct drm_i915_private *i915 = to_i915(state->base.dev); 3034 struct intel_crtc_state *crtc_state = 3035 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL; 3036 int required_lanes = crtc_state ? crtc_state->lane_count : 1; 3037 3038 drm_WARN_ON(state->base.dev, crtc && crtc->active); 3039 3040 intel_tc_port_get_link(enc_to_dig_port(encoder), 3041 required_lanes); 3042 if (crtc_state && crtc_state->hw.active) { 3043 struct intel_crtc *slave_crtc; 3044 3045 intel_update_active_dpll(state, crtc, encoder); 3046 3047 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 3048 intel_crtc_bigjoiner_slave_pipes(crtc_state)) 3049 intel_update_active_dpll(state, slave_crtc, encoder); 3050 } 3051 } 3052 3053 static void 3054 intel_ddi_update_complete(struct intel_atomic_state *state, 3055 struct intel_encoder *encoder, 3056 struct intel_crtc *crtc) 3057 { 3058 intel_tc_port_put_link(enc_to_dig_port(encoder)); 3059 } 3060 3061 static void 3062 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3063 struct intel_encoder *encoder, 3064 const struct intel_crtc_state *crtc_state, 3065 const struct drm_connector_state *conn_state) 3066 { 3067 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3068 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3069 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3070 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 3071 3072 if (is_tc_port) 3073 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3074 3075 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) { 3076 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref); 3077 dig_port->aux_wakeref = 3078 intel_display_power_get(dev_priv, 3079 intel_ddi_main_link_aux_domain(dig_port)); 3080 } 3081 3082 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3083 /* 3084 * Program the lane count for static/dynamic connections on 3085 * Type-C ports. Skip this step for TBT. 3086 */ 3087 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3088 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3089 bxt_ddi_phy_set_lane_optim_mask(encoder, 3090 crtc_state->lane_lat_optim_mask); 3091 } 3092 3093 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) 3094 { 3095 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3096 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 3097 int ln; 3098 3099 for (ln = 0; ln < 2; ln++) { 3100 intel_de_write(i915, HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln)); 3101 intel_de_rmw(i915, DKL_PCS_DW5(tc_port), DKL_PCS_DW5_CORE_SOFTRESET, 0); 3102 } 3103 } 3104 3105 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3106 const struct intel_crtc_state *crtc_state) 3107 { 3108 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3109 struct intel_encoder *encoder = &dig_port->base; 3110 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3111 enum port port = encoder->port; 3112 u32 dp_tp_ctl, ddi_buf_ctl; 3113 bool wait = false; 3114 3115 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3116 3117 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 3118 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3119 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 3120 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3121 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 3122 wait = true; 3123 } 3124 3125 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 3126 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1; 3127 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3128 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3129 3130 if (wait) 3131 intel_wait_ddi_buf_idle(dev_priv, port); 3132 } 3133 3134 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3135 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3136 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3137 } else { 3138 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3139 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 3140 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3141 } 3142 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3143 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3144 3145 if (IS_ALDERLAKE_P(dev_priv) && 3146 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) 3147 adlp_tbt_to_dp_alt_switch_wa(encoder); 3148 3149 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3150 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3151 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3152 3153 intel_wait_ddi_buf_active(dev_priv, port); 3154 } 3155 3156 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3157 const struct intel_crtc_state *crtc_state, 3158 u8 dp_train_pat) 3159 { 3160 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3161 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3162 u32 temp; 3163 3164 temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3165 3166 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3167 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3168 case DP_TRAINING_PATTERN_DISABLE: 3169 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3170 break; 3171 case DP_TRAINING_PATTERN_1: 3172 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3173 break; 3174 case DP_TRAINING_PATTERN_2: 3175 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3176 break; 3177 case DP_TRAINING_PATTERN_3: 3178 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3179 break; 3180 case DP_TRAINING_PATTERN_4: 3181 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3182 break; 3183 } 3184 3185 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp); 3186 } 3187 3188 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3189 const struct intel_crtc_state *crtc_state) 3190 { 3191 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3192 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3193 enum port port = encoder->port; 3194 u32 val; 3195 3196 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3197 val &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3198 val |= DP_TP_CTL_LINK_TRAIN_IDLE; 3199 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 3200 3201 /* 3202 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3203 * reason we need to set idle transmission mode is to work around a HW 3204 * issue where we enable the pipe while not in idle link-training mode. 3205 * In this case there is requirement to wait for a minimum number of 3206 * idle patterns to be sent. 3207 */ 3208 if (port == PORT_A && DISPLAY_VER(dev_priv) < 12) 3209 return; 3210 3211 if (intel_de_wait_for_set(dev_priv, 3212 dp_tp_status_reg(encoder, crtc_state), 3213 DP_TP_STATUS_IDLE_DONE, 1)) 3214 drm_err(&dev_priv->drm, 3215 "Timed out waiting for DP idle patterns\n"); 3216 } 3217 3218 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 3219 enum transcoder cpu_transcoder) 3220 { 3221 if (cpu_transcoder == TRANSCODER_EDP) 3222 return false; 3223 3224 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO)) 3225 return false; 3226 3227 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 3228 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3229 } 3230 3231 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, 3232 struct intel_crtc_state *crtc_state) 3233 { 3234 if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000) 3235 crtc_state->min_voltage_level = 2; 3236 else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000) 3237 crtc_state->min_voltage_level = 3; 3238 else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000) 3239 crtc_state->min_voltage_level = 1; 3240 } 3241 3242 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, 3243 enum transcoder cpu_transcoder) 3244 { 3245 u32 master_select; 3246 3247 if (DISPLAY_VER(dev_priv) >= 11) { 3248 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder)); 3249 3250 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3251 return INVALID_TRANSCODER; 3252 3253 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3254 } else { 3255 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3256 3257 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3258 return INVALID_TRANSCODER; 3259 3260 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3261 } 3262 3263 if (master_select == 0) 3264 return TRANSCODER_EDP; 3265 else 3266 return master_select - 1; 3267 } 3268 3269 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3270 { 3271 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3272 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3273 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3274 enum transcoder cpu_transcoder; 3275 3276 crtc_state->master_transcoder = 3277 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); 3278 3279 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { 3280 enum intel_display_power_domain power_domain; 3281 intel_wakeref_t trans_wakeref; 3282 3283 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3284 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 3285 power_domain); 3286 3287 if (!trans_wakeref) 3288 continue; 3289 3290 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == 3291 crtc_state->cpu_transcoder) 3292 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3293 3294 intel_display_power_put(dev_priv, power_domain, trans_wakeref); 3295 } 3296 3297 drm_WARN_ON(&dev_priv->drm, 3298 crtc_state->master_transcoder != INVALID_TRANSCODER && 3299 crtc_state->sync_mode_slaves_mask); 3300 } 3301 3302 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 3303 struct intel_crtc_state *pipe_config) 3304 { 3305 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3306 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3307 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3308 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3309 u32 temp, flags = 0; 3310 3311 temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3312 if (temp & TRANS_DDI_PHSYNC) 3313 flags |= DRM_MODE_FLAG_PHSYNC; 3314 else 3315 flags |= DRM_MODE_FLAG_NHSYNC; 3316 if (temp & TRANS_DDI_PVSYNC) 3317 flags |= DRM_MODE_FLAG_PVSYNC; 3318 else 3319 flags |= DRM_MODE_FLAG_NVSYNC; 3320 3321 pipe_config->hw.adjusted_mode.flags |= flags; 3322 3323 switch (temp & TRANS_DDI_BPC_MASK) { 3324 case TRANS_DDI_BPC_6: 3325 pipe_config->pipe_bpp = 18; 3326 break; 3327 case TRANS_DDI_BPC_8: 3328 pipe_config->pipe_bpp = 24; 3329 break; 3330 case TRANS_DDI_BPC_10: 3331 pipe_config->pipe_bpp = 30; 3332 break; 3333 case TRANS_DDI_BPC_12: 3334 pipe_config->pipe_bpp = 36; 3335 break; 3336 default: 3337 break; 3338 } 3339 3340 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 3341 case TRANS_DDI_MODE_SELECT_HDMI: 3342 pipe_config->has_hdmi_sink = true; 3343 3344 pipe_config->infoframes.enable |= 3345 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3346 3347 if (pipe_config->infoframes.enable) 3348 pipe_config->has_infoframe = true; 3349 3350 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 3351 pipe_config->hdmi_scrambling = true; 3352 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 3353 pipe_config->hdmi_high_tmds_clock_ratio = true; 3354 fallthrough; 3355 case TRANS_DDI_MODE_SELECT_DVI: 3356 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 3357 pipe_config->lane_count = 4; 3358 break; 3359 case TRANS_DDI_MODE_SELECT_DP_SST: 3360 if (encoder->type == INTEL_OUTPUT_EDP) 3361 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 3362 else 3363 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 3364 pipe_config->lane_count = 3365 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3366 3367 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 3368 &pipe_config->dp_m_n); 3369 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, 3370 &pipe_config->dp_m2_n2); 3371 3372 if (DISPLAY_VER(dev_priv) >= 11) { 3373 i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config); 3374 3375 pipe_config->fec_enable = 3376 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE; 3377 3378 drm_dbg_kms(&dev_priv->drm, 3379 "[ENCODER:%d:%s] Fec status: %u\n", 3380 encoder->base.base.id, encoder->base.name, 3381 pipe_config->fec_enable); 3382 } 3383 3384 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) 3385 pipe_config->infoframes.enable |= 3386 intel_lspcon_infoframes_enabled(encoder, pipe_config); 3387 else 3388 pipe_config->infoframes.enable |= 3389 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3390 break; 3391 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 3392 if (!HAS_DP20(dev_priv)) { 3393 /* FDI */ 3394 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 3395 break; 3396 } 3397 fallthrough; /* 128b/132b */ 3398 case TRANS_DDI_MODE_SELECT_DP_MST: 3399 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 3400 pipe_config->lane_count = 3401 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3402 3403 if (DISPLAY_VER(dev_priv) >= 12) 3404 pipe_config->mst_master_transcoder = 3405 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); 3406 3407 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 3408 &pipe_config->dp_m_n); 3409 3410 pipe_config->infoframes.enable |= 3411 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3412 break; 3413 default: 3414 break; 3415 } 3416 } 3417 3418 static void intel_ddi_get_config(struct intel_encoder *encoder, 3419 struct intel_crtc_state *pipe_config) 3420 { 3421 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3422 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3423 3424 /* XXX: DSI transcoder paranoia */ 3425 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 3426 return; 3427 3428 intel_ddi_read_func_ctl(encoder, pipe_config); 3429 3430 intel_ddi_mso_get_config(encoder, pipe_config); 3431 3432 pipe_config->has_audio = 3433 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 3434 3435 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp && 3436 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { 3437 /* 3438 * This is a big fat ugly hack. 3439 * 3440 * Some machines in UEFI boot mode provide us a VBT that has 18 3441 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 3442 * unknown we fail to light up. Yet the same BIOS boots up with 3443 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 3444 * max, not what it tells us to use. 3445 * 3446 * Note: This will still be broken if the eDP panel is not lit 3447 * up by the BIOS, and thus we can't get the mode at module 3448 * load. 3449 */ 3450 drm_dbg_kms(&dev_priv->drm, 3451 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 3452 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); 3453 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; 3454 } 3455 3456 ddi_dotclock_get(pipe_config); 3457 3458 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3459 pipe_config->lane_lat_optim_mask = 3460 bxt_ddi_phy_get_lane_lat_optim_mask(encoder); 3461 3462 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 3463 3464 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 3465 3466 intel_read_infoframe(encoder, pipe_config, 3467 HDMI_INFOFRAME_TYPE_AVI, 3468 &pipe_config->infoframes.avi); 3469 intel_read_infoframe(encoder, pipe_config, 3470 HDMI_INFOFRAME_TYPE_SPD, 3471 &pipe_config->infoframes.spd); 3472 intel_read_infoframe(encoder, pipe_config, 3473 HDMI_INFOFRAME_TYPE_VENDOR, 3474 &pipe_config->infoframes.hdmi); 3475 intel_read_infoframe(encoder, pipe_config, 3476 HDMI_INFOFRAME_TYPE_DRM, 3477 &pipe_config->infoframes.drm); 3478 3479 if (DISPLAY_VER(dev_priv) >= 8) 3480 bdw_get_trans_port_sync_config(pipe_config); 3481 3482 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 3483 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 3484 3485 intel_psr_get_config(encoder, pipe_config); 3486 } 3487 3488 void intel_ddi_get_clock(struct intel_encoder *encoder, 3489 struct intel_crtc_state *crtc_state, 3490 struct intel_shared_dpll *pll) 3491 { 3492 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3493 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 3494 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 3495 bool pll_active; 3496 3497 if (drm_WARN_ON(&i915->drm, !pll)) 3498 return; 3499 3500 port_dpll->pll = pll; 3501 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 3502 drm_WARN_ON(&i915->drm, !pll_active); 3503 3504 icl_set_active_port_dpll(crtc_state, port_dpll_id); 3505 3506 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 3507 &crtc_state->dpll_hw_state); 3508 } 3509 3510 static void dg2_ddi_get_config(struct intel_encoder *encoder, 3511 struct intel_crtc_state *crtc_state) 3512 { 3513 intel_mpllb_readout_hw_state(encoder, &crtc_state->mpllb_state); 3514 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->mpllb_state); 3515 3516 intel_ddi_get_config(encoder, crtc_state); 3517 } 3518 3519 static void adls_ddi_get_config(struct intel_encoder *encoder, 3520 struct intel_crtc_state *crtc_state) 3521 { 3522 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 3523 intel_ddi_get_config(encoder, crtc_state); 3524 } 3525 3526 static void rkl_ddi_get_config(struct intel_encoder *encoder, 3527 struct intel_crtc_state *crtc_state) 3528 { 3529 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 3530 intel_ddi_get_config(encoder, crtc_state); 3531 } 3532 3533 static void dg1_ddi_get_config(struct intel_encoder *encoder, 3534 struct intel_crtc_state *crtc_state) 3535 { 3536 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 3537 intel_ddi_get_config(encoder, crtc_state); 3538 } 3539 3540 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 3541 struct intel_crtc_state *crtc_state) 3542 { 3543 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 3544 intel_ddi_get_config(encoder, crtc_state); 3545 } 3546 3547 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 3548 struct intel_crtc_state *crtc_state, 3549 struct intel_shared_dpll *pll) 3550 { 3551 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3552 enum icl_port_dpll_id port_dpll_id; 3553 struct icl_port_dpll *port_dpll; 3554 bool pll_active; 3555 3556 if (drm_WARN_ON(&i915->drm, !pll)) 3557 return; 3558 3559 if (intel_get_shared_dpll_id(i915, pll) == DPLL_ID_ICL_TBTPLL) 3560 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 3561 else 3562 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 3563 3564 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 3565 3566 port_dpll->pll = pll; 3567 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 3568 drm_WARN_ON(&i915->drm, !pll_active); 3569 3570 icl_set_active_port_dpll(crtc_state, port_dpll_id); 3571 3572 if (intel_get_shared_dpll_id(i915, crtc_state->shared_dpll) == DPLL_ID_ICL_TBTPLL) 3573 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port); 3574 else 3575 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 3576 &crtc_state->dpll_hw_state); 3577 } 3578 3579 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 3580 struct intel_crtc_state *crtc_state) 3581 { 3582 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 3583 intel_ddi_get_config(encoder, crtc_state); 3584 } 3585 3586 static void bxt_ddi_get_config(struct intel_encoder *encoder, 3587 struct intel_crtc_state *crtc_state) 3588 { 3589 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 3590 intel_ddi_get_config(encoder, crtc_state); 3591 } 3592 3593 static void skl_ddi_get_config(struct intel_encoder *encoder, 3594 struct intel_crtc_state *crtc_state) 3595 { 3596 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 3597 intel_ddi_get_config(encoder, crtc_state); 3598 } 3599 3600 void hsw_ddi_get_config(struct intel_encoder *encoder, 3601 struct intel_crtc_state *crtc_state) 3602 { 3603 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 3604 intel_ddi_get_config(encoder, crtc_state); 3605 } 3606 3607 static void intel_ddi_sync_state(struct intel_encoder *encoder, 3608 const struct intel_crtc_state *crtc_state) 3609 { 3610 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3611 enum phy phy = intel_port_to_phy(i915, encoder->port); 3612 3613 if (intel_phy_is_tc(i915, phy)) 3614 intel_tc_port_sanitize(enc_to_dig_port(encoder)); 3615 3616 if (crtc_state && intel_crtc_has_dp_encoder(crtc_state)) 3617 intel_dp_sync_state(encoder, crtc_state); 3618 } 3619 3620 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 3621 struct intel_crtc_state *crtc_state) 3622 { 3623 if (intel_crtc_has_dp_encoder(crtc_state)) 3624 return intel_dp_initial_fastset_check(encoder, crtc_state); 3625 3626 return true; 3627 } 3628 3629 static enum intel_output_type 3630 intel_ddi_compute_output_type(struct intel_encoder *encoder, 3631 struct intel_crtc_state *crtc_state, 3632 struct drm_connector_state *conn_state) 3633 { 3634 switch (conn_state->connector->connector_type) { 3635 case DRM_MODE_CONNECTOR_HDMIA: 3636 return INTEL_OUTPUT_HDMI; 3637 case DRM_MODE_CONNECTOR_eDP: 3638 return INTEL_OUTPUT_EDP; 3639 case DRM_MODE_CONNECTOR_DisplayPort: 3640 return INTEL_OUTPUT_DP; 3641 default: 3642 MISSING_CASE(conn_state->connector->connector_type); 3643 return INTEL_OUTPUT_UNUSED; 3644 } 3645 } 3646 3647 static int intel_ddi_compute_config(struct intel_encoder *encoder, 3648 struct intel_crtc_state *pipe_config, 3649 struct drm_connector_state *conn_state) 3650 { 3651 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3652 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3653 enum port port = encoder->port; 3654 int ret; 3655 3656 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 3657 pipe_config->cpu_transcoder = TRANSCODER_EDP; 3658 3659 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 3660 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 3661 } else { 3662 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 3663 } 3664 3665 if (ret) 3666 return ret; 3667 3668 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 3669 pipe_config->cpu_transcoder == TRANSCODER_EDP) 3670 pipe_config->pch_pfit.force_thru = 3671 pipe_config->pch_pfit.enabled || 3672 pipe_config->crc_enabled; 3673 3674 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3675 pipe_config->lane_lat_optim_mask = 3676 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 3677 3678 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 3679 3680 return 0; 3681 } 3682 3683 static bool mode_equal(const struct drm_display_mode *mode1, 3684 const struct drm_display_mode *mode2) 3685 { 3686 return drm_mode_match(mode1, mode2, 3687 DRM_MODE_MATCH_TIMINGS | 3688 DRM_MODE_MATCH_FLAGS | 3689 DRM_MODE_MATCH_3D_FLAGS) && 3690 mode1->clock == mode2->clock; /* we want an exact match */ 3691 } 3692 3693 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 3694 const struct intel_link_m_n *m_n_2) 3695 { 3696 return m_n_1->tu == m_n_2->tu && 3697 m_n_1->data_m == m_n_2->data_m && 3698 m_n_1->data_n == m_n_2->data_n && 3699 m_n_1->link_m == m_n_2->link_m && 3700 m_n_1->link_n == m_n_2->link_n; 3701 } 3702 3703 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 3704 const struct intel_crtc_state *crtc_state2) 3705 { 3706 return crtc_state1->hw.active && crtc_state2->hw.active && 3707 crtc_state1->output_types == crtc_state2->output_types && 3708 crtc_state1->output_format == crtc_state2->output_format && 3709 crtc_state1->lane_count == crtc_state2->lane_count && 3710 crtc_state1->port_clock == crtc_state2->port_clock && 3711 mode_equal(&crtc_state1->hw.adjusted_mode, 3712 &crtc_state2->hw.adjusted_mode) && 3713 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 3714 } 3715 3716 static u8 3717 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 3718 int tile_group_id) 3719 { 3720 struct drm_connector *connector; 3721 const struct drm_connector_state *conn_state; 3722 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 3723 struct intel_atomic_state *state = 3724 to_intel_atomic_state(ref_crtc_state->uapi.state); 3725 u8 transcoders = 0; 3726 int i; 3727 3728 /* 3729 * We don't enable port sync on BDW due to missing w/as and 3730 * due to not having adjusted the modeset sequence appropriately. 3731 */ 3732 if (DISPLAY_VER(dev_priv) < 9) 3733 return 0; 3734 3735 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 3736 return 0; 3737 3738 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 3739 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 3740 const struct intel_crtc_state *crtc_state; 3741 3742 if (!crtc) 3743 continue; 3744 3745 if (!connector->has_tile || 3746 connector->tile_group->id != 3747 tile_group_id) 3748 continue; 3749 crtc_state = intel_atomic_get_new_crtc_state(state, 3750 crtc); 3751 if (!crtcs_port_sync_compatible(ref_crtc_state, 3752 crtc_state)) 3753 continue; 3754 transcoders |= BIT(crtc_state->cpu_transcoder); 3755 } 3756 3757 return transcoders; 3758 } 3759 3760 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 3761 struct intel_crtc_state *crtc_state, 3762 struct drm_connector_state *conn_state) 3763 { 3764 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3765 struct drm_connector *connector = conn_state->connector; 3766 u8 port_sync_transcoders = 0; 3767 3768 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]", 3769 encoder->base.base.id, encoder->base.name, 3770 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 3771 3772 if (connector->has_tile) 3773 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 3774 connector->tile_group->id); 3775 3776 /* 3777 * EDP Transcoders cannot be ensalved 3778 * make them a master always when present 3779 */ 3780 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 3781 crtc_state->master_transcoder = TRANSCODER_EDP; 3782 else 3783 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 3784 3785 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 3786 crtc_state->master_transcoder = INVALID_TRANSCODER; 3787 crtc_state->sync_mode_slaves_mask = 3788 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 3789 } 3790 3791 return 0; 3792 } 3793 3794 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 3795 { 3796 struct drm_i915_private *i915 = to_i915(encoder->dev); 3797 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 3798 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 3799 3800 intel_dp_encoder_flush_work(encoder); 3801 if (intel_phy_is_tc(i915, phy)) 3802 intel_tc_port_flush_work(dig_port); 3803 intel_display_power_flush_work(i915); 3804 3805 drm_encoder_cleanup(encoder); 3806 kfree(dig_port->hdcp_port_data.streams); 3807 kfree(dig_port); 3808 } 3809 3810 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 3811 { 3812 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 3813 3814 intel_dp->reset_link_params = true; 3815 3816 intel_pps_encoder_reset(intel_dp); 3817 } 3818 3819 static const struct drm_encoder_funcs intel_ddi_funcs = { 3820 .reset = intel_ddi_encoder_reset, 3821 .destroy = intel_ddi_encoder_destroy, 3822 }; 3823 3824 static struct intel_connector * 3825 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 3826 { 3827 struct intel_connector *connector; 3828 enum port port = dig_port->base.port; 3829 3830 connector = intel_connector_alloc(); 3831 if (!connector) 3832 return NULL; 3833 3834 dig_port->dp.output_reg = DDI_BUF_CTL(port); 3835 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 3836 dig_port->dp.set_link_train = intel_ddi_set_link_train; 3837 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 3838 3839 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 3840 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 3841 3842 if (!intel_dp_init_connector(dig_port, connector)) { 3843 kfree(connector); 3844 return NULL; 3845 } 3846 3847 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 3848 struct drm_device *dev = dig_port->base.base.dev; 3849 struct drm_privacy_screen *privacy_screen; 3850 3851 privacy_screen = drm_privacy_screen_get(dev->dev, NULL); 3852 if (!IS_ERR(privacy_screen)) { 3853 drm_connector_attach_privacy_screen_provider(&connector->base, 3854 privacy_screen); 3855 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 3856 drm_warn(dev, "Error getting privacy-screen\n"); 3857 } 3858 } 3859 3860 return connector; 3861 } 3862 3863 static int modeset_pipe(struct drm_crtc *crtc, 3864 struct drm_modeset_acquire_ctx *ctx) 3865 { 3866 struct drm_atomic_state *state; 3867 struct drm_crtc_state *crtc_state; 3868 int ret; 3869 3870 state = drm_atomic_state_alloc(crtc->dev); 3871 if (!state) 3872 return -ENOMEM; 3873 3874 state->acquire_ctx = ctx; 3875 3876 crtc_state = drm_atomic_get_crtc_state(state, crtc); 3877 if (IS_ERR(crtc_state)) { 3878 ret = PTR_ERR(crtc_state); 3879 goto out; 3880 } 3881 3882 crtc_state->connectors_changed = true; 3883 3884 ret = drm_atomic_commit(state); 3885 out: 3886 drm_atomic_state_put(state); 3887 3888 return ret; 3889 } 3890 3891 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 3892 struct drm_modeset_acquire_ctx *ctx) 3893 { 3894 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3895 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 3896 struct intel_connector *connector = hdmi->attached_connector; 3897 struct i2c_adapter *adapter = 3898 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 3899 struct drm_connector_state *conn_state; 3900 struct intel_crtc_state *crtc_state; 3901 struct intel_crtc *crtc; 3902 u8 config; 3903 int ret; 3904 3905 if (!connector || connector->base.status != connector_status_connected) 3906 return 0; 3907 3908 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 3909 ctx); 3910 if (ret) 3911 return ret; 3912 3913 conn_state = connector->base.state; 3914 3915 crtc = to_intel_crtc(conn_state->crtc); 3916 if (!crtc) 3917 return 0; 3918 3919 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 3920 if (ret) 3921 return ret; 3922 3923 crtc_state = to_intel_crtc_state(crtc->base.state); 3924 3925 drm_WARN_ON(&dev_priv->drm, 3926 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 3927 3928 if (!crtc_state->hw.active) 3929 return 0; 3930 3931 if (!crtc_state->hdmi_high_tmds_clock_ratio && 3932 !crtc_state->hdmi_scrambling) 3933 return 0; 3934 3935 if (conn_state->commit && 3936 !try_wait_for_completion(&conn_state->commit->hw_done)) 3937 return 0; 3938 3939 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 3940 if (ret < 0) { 3941 drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n", 3942 ret); 3943 return 0; 3944 } 3945 3946 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 3947 crtc_state->hdmi_high_tmds_clock_ratio && 3948 !!(config & SCDC_SCRAMBLING_ENABLE) == 3949 crtc_state->hdmi_scrambling) 3950 return 0; 3951 3952 /* 3953 * HDMI 2.0 says that one should not send scrambled data 3954 * prior to configuring the sink scrambling, and that 3955 * TMDS clock/data transmission should be suspended when 3956 * changing the TMDS clock rate in the sink. So let's 3957 * just do a full modeset here, even though some sinks 3958 * would be perfectly happy if were to just reconfigure 3959 * the SCDC settings on the fly. 3960 */ 3961 return modeset_pipe(&crtc->base, ctx); 3962 } 3963 3964 static enum intel_hotplug_state 3965 intel_ddi_hotplug(struct intel_encoder *encoder, 3966 struct intel_connector *connector) 3967 { 3968 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3969 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3970 struct intel_dp *intel_dp = &dig_port->dp; 3971 enum phy phy = intel_port_to_phy(i915, encoder->port); 3972 bool is_tc = intel_phy_is_tc(i915, phy); 3973 struct drm_modeset_acquire_ctx ctx; 3974 enum intel_hotplug_state state; 3975 int ret; 3976 3977 if (intel_dp->compliance.test_active && 3978 intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) { 3979 intel_dp_phy_test(encoder); 3980 /* just do the PHY test and nothing else */ 3981 return INTEL_HOTPLUG_UNCHANGED; 3982 } 3983 3984 state = intel_encoder_hotplug(encoder, connector); 3985 3986 drm_modeset_acquire_init(&ctx, 0); 3987 3988 for (;;) { 3989 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) 3990 ret = intel_hdmi_reset_link(encoder, &ctx); 3991 else 3992 ret = intel_dp_retrain_link(encoder, &ctx); 3993 3994 if (ret == -EDEADLK) { 3995 drm_modeset_backoff(&ctx); 3996 continue; 3997 } 3998 3999 break; 4000 } 4001 4002 drm_modeset_drop_locks(&ctx); 4003 drm_modeset_acquire_fini(&ctx); 4004 drm_WARN(encoder->base.dev, ret, 4005 "Acquiring modeset locks failed with %i\n", ret); 4006 4007 /* 4008 * Unpowered type-c dongles can take some time to boot and be 4009 * responsible, so here giving some time to those dongles to power up 4010 * and then retrying the probe. 4011 * 4012 * On many platforms the HDMI live state signal is known to be 4013 * unreliable, so we can't use it to detect if a sink is connected or 4014 * not. Instead we detect if it's connected based on whether we can 4015 * read the EDID or not. That in turn has a problem during disconnect, 4016 * since the HPD interrupt may be raised before the DDC lines get 4017 * disconnected (due to how the required length of DDC vs. HPD 4018 * connector pins are specified) and so we'll still be able to get a 4019 * valid EDID. To solve this schedule another detection cycle if this 4020 * time around we didn't detect any change in the sink's connection 4021 * status. 4022 * 4023 * Type-c connectors which get their HPD signal deasserted then 4024 * reasserted, without unplugging/replugging the sink from the 4025 * connector, introduce a delay until the AUX channel communication 4026 * becomes functional. Retry the detection for 5 seconds on type-c 4027 * connectors to account for this delay. 4028 */ 4029 if (state == INTEL_HOTPLUG_UNCHANGED && 4030 connector->hotplug_retries < (is_tc ? 5 : 1) && 4031 !dig_port->dp.is_mst) 4032 state = INTEL_HOTPLUG_RETRY; 4033 4034 return state; 4035 } 4036 4037 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4038 { 4039 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4040 u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin]; 4041 4042 return intel_de_read(dev_priv, SDEISR) & bit; 4043 } 4044 4045 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4046 { 4047 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4048 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; 4049 4050 return intel_de_read(dev_priv, DEISR) & bit; 4051 } 4052 4053 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4054 { 4055 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4056 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; 4057 4058 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; 4059 } 4060 4061 static struct intel_connector * 4062 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4063 { 4064 struct intel_connector *connector; 4065 enum port port = dig_port->base.port; 4066 4067 connector = intel_connector_alloc(); 4068 if (!connector) 4069 return NULL; 4070 4071 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4072 intel_hdmi_init_connector(dig_port, connector); 4073 4074 return connector; 4075 } 4076 4077 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4078 { 4079 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4080 4081 if (dig_port->base.port != PORT_A) 4082 return false; 4083 4084 if (dig_port->saved_port_bits & DDI_A_4_LANES) 4085 return false; 4086 4087 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4088 * supported configuration 4089 */ 4090 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4091 return true; 4092 4093 return false; 4094 } 4095 4096 static int 4097 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4098 { 4099 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4100 enum port port = dig_port->base.port; 4101 int max_lanes = 4; 4102 4103 if (DISPLAY_VER(dev_priv) >= 11) 4104 return max_lanes; 4105 4106 if (port == PORT_A || port == PORT_E) { 4107 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4108 max_lanes = port == PORT_A ? 4 : 0; 4109 else 4110 /* Both A and E share 2 lanes */ 4111 max_lanes = 2; 4112 } 4113 4114 /* 4115 * Some BIOS might fail to set this bit on port A if eDP 4116 * wasn't lit up at boot. Force this bit set when needed 4117 * so we use the proper lane count for our calculations. 4118 */ 4119 if (intel_ddi_a_force_4_lanes(dig_port)) { 4120 drm_dbg_kms(&dev_priv->drm, 4121 "Forcing DDI_A_4_LANES for port A\n"); 4122 dig_port->saved_port_bits |= DDI_A_4_LANES; 4123 max_lanes = 4; 4124 } 4125 4126 return max_lanes; 4127 } 4128 4129 static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy) 4130 { 4131 return i915->hti_state & HDPORT_ENABLED && 4132 i915->hti_state & HDPORT_DDI_USED(phy); 4133 } 4134 4135 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv, 4136 enum port port) 4137 { 4138 if (port >= PORT_D_XELPD) 4139 return HPD_PORT_D + port - PORT_D_XELPD; 4140 else if (port >= PORT_TC1) 4141 return HPD_PORT_TC1 + port - PORT_TC1; 4142 else 4143 return HPD_PORT_A + port - PORT_A; 4144 } 4145 4146 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, 4147 enum port port) 4148 { 4149 if (port >= PORT_TC1) 4150 return HPD_PORT_C + port - PORT_TC1; 4151 else 4152 return HPD_PORT_A + port - PORT_A; 4153 } 4154 4155 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, 4156 enum port port) 4157 { 4158 if (port >= PORT_TC1) 4159 return HPD_PORT_TC1 + port - PORT_TC1; 4160 else 4161 return HPD_PORT_A + port - PORT_A; 4162 } 4163 4164 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, 4165 enum port port) 4166 { 4167 if (HAS_PCH_TGP(dev_priv)) 4168 return tgl_hpd_pin(dev_priv, port); 4169 4170 if (port >= PORT_TC1) 4171 return HPD_PORT_C + port - PORT_TC1; 4172 else 4173 return HPD_PORT_A + port - PORT_A; 4174 } 4175 4176 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, 4177 enum port port) 4178 { 4179 if (port >= PORT_C) 4180 return HPD_PORT_TC1 + port - PORT_C; 4181 else 4182 return HPD_PORT_A + port - PORT_A; 4183 } 4184 4185 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, 4186 enum port port) 4187 { 4188 if (port == PORT_D) 4189 return HPD_PORT_A; 4190 4191 if (HAS_PCH_MCC(dev_priv)) 4192 return icl_hpd_pin(dev_priv, port); 4193 4194 return HPD_PORT_A + port - PORT_A; 4195 } 4196 4197 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) 4198 { 4199 if (HAS_PCH_TGP(dev_priv)) 4200 return icl_hpd_pin(dev_priv, port); 4201 4202 return HPD_PORT_A + port - PORT_A; 4203 } 4204 4205 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port) 4206 { 4207 if (DISPLAY_VER(i915) >= 12) 4208 return port >= PORT_TC1; 4209 else if (DISPLAY_VER(i915) >= 11) 4210 return port >= PORT_C; 4211 else 4212 return false; 4213 } 4214 4215 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 4216 { 4217 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4218 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4219 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4220 enum phy phy = intel_port_to_phy(i915, encoder->port); 4221 4222 intel_dp_encoder_suspend(encoder); 4223 4224 if (!intel_phy_is_tc(i915, phy)) 4225 return; 4226 4227 intel_tc_port_flush_work(dig_port); 4228 } 4229 4230 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 4231 { 4232 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4233 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4234 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4235 enum phy phy = intel_port_to_phy(i915, encoder->port); 4236 4237 intel_dp_encoder_shutdown(encoder); 4238 intel_hdmi_encoder_shutdown(encoder); 4239 4240 if (!intel_phy_is_tc(i915, phy)) 4241 return; 4242 4243 intel_tc_port_flush_work(dig_port); 4244 } 4245 4246 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 4247 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 4248 4249 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 4250 { 4251 struct intel_digital_port *dig_port; 4252 struct intel_encoder *encoder; 4253 const struct intel_bios_encoder_data *devdata; 4254 bool init_hdmi, init_dp; 4255 enum phy phy = intel_port_to_phy(dev_priv, port); 4256 4257 /* 4258 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 4259 * have taken over some of the PHYs and made them unavailable to the 4260 * driver. In that case we should skip initializing the corresponding 4261 * outputs. 4262 */ 4263 if (hti_uses_phy(dev_priv, phy)) { 4264 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", 4265 port_name(port), phy_name(phy)); 4266 return; 4267 } 4268 4269 devdata = intel_bios_encoder_data_lookup(dev_priv, port); 4270 if (!devdata) { 4271 drm_dbg_kms(&dev_priv->drm, 4272 "VBT says port %c is not present\n", 4273 port_name(port)); 4274 return; 4275 } 4276 4277 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 4278 intel_bios_encoder_supports_hdmi(devdata); 4279 init_dp = intel_bios_encoder_supports_dp(devdata); 4280 4281 if (intel_bios_is_lspcon_present(dev_priv, port)) { 4282 /* 4283 * Lspcon device needs to be driven with DP connector 4284 * with special detection sequence. So make sure DP 4285 * is initialized before lspcon. 4286 */ 4287 init_dp = true; 4288 init_hdmi = false; 4289 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", 4290 port_name(port)); 4291 } 4292 4293 if (!init_dp && !init_hdmi) { 4294 drm_dbg_kms(&dev_priv->drm, 4295 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 4296 port_name(port)); 4297 return; 4298 } 4299 4300 if (intel_phy_is_snps(dev_priv, phy) && 4301 dev_priv->snps_phy_failed_calibration & BIT(phy)) { 4302 drm_dbg_kms(&dev_priv->drm, 4303 "SNPS PHY %c failed to calibrate, proceeding anyway\n", 4304 phy_name(phy)); 4305 } 4306 4307 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 4308 if (!dig_port) 4309 return; 4310 4311 encoder = &dig_port->base; 4312 encoder->devdata = devdata; 4313 4314 if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) { 4315 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4316 DRM_MODE_ENCODER_TMDS, 4317 "DDI %c/PHY %c", 4318 port_name(port - PORT_D_XELPD + PORT_D), 4319 phy_name(phy)); 4320 } else if (DISPLAY_VER(dev_priv) >= 12) { 4321 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4322 4323 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4324 DRM_MODE_ENCODER_TMDS, 4325 "DDI %s%c/PHY %s%c", 4326 port >= PORT_TC1 ? "TC" : "", 4327 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 4328 tc_port != TC_PORT_NONE ? "TC" : "", 4329 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4330 } else if (DISPLAY_VER(dev_priv) >= 11) { 4331 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4332 4333 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4334 DRM_MODE_ENCODER_TMDS, 4335 "DDI %c%s/PHY %s%c", 4336 port_name(port), 4337 port >= PORT_C ? " (TC)" : "", 4338 tc_port != TC_PORT_NONE ? "TC" : "", 4339 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4340 } else { 4341 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4342 DRM_MODE_ENCODER_TMDS, 4343 "DDI %c/PHY %c", port_name(port), phy_name(phy)); 4344 } 4345 4346 mutex_init(&dig_port->hdcp_mutex); 4347 dig_port->num_hdcp_streams = 0; 4348 4349 encoder->hotplug = intel_ddi_hotplug; 4350 encoder->compute_output_type = intel_ddi_compute_output_type; 4351 encoder->compute_config = intel_ddi_compute_config; 4352 encoder->compute_config_late = intel_ddi_compute_config_late; 4353 encoder->enable = intel_enable_ddi; 4354 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 4355 encoder->pre_enable = intel_ddi_pre_enable; 4356 encoder->disable = intel_disable_ddi; 4357 encoder->post_disable = intel_ddi_post_disable; 4358 encoder->update_pipe = intel_ddi_update_pipe; 4359 encoder->get_hw_state = intel_ddi_get_hw_state; 4360 encoder->sync_state = intel_ddi_sync_state; 4361 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 4362 encoder->suspend = intel_ddi_encoder_suspend; 4363 encoder->shutdown = intel_ddi_encoder_shutdown; 4364 encoder->get_power_domains = intel_ddi_get_power_domains; 4365 4366 encoder->type = INTEL_OUTPUT_DDI; 4367 encoder->power_domain = intel_port_to_power_domain(port); 4368 encoder->port = port; 4369 encoder->cloneable = 0; 4370 encoder->pipe_mask = ~0; 4371 4372 if (IS_DG2(dev_priv)) { 4373 encoder->enable_clock = intel_mpllb_enable; 4374 encoder->disable_clock = intel_mpllb_disable; 4375 encoder->get_config = dg2_ddi_get_config; 4376 } else if (IS_ALDERLAKE_S(dev_priv)) { 4377 encoder->enable_clock = adls_ddi_enable_clock; 4378 encoder->disable_clock = adls_ddi_disable_clock; 4379 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 4380 encoder->get_config = adls_ddi_get_config; 4381 } else if (IS_ROCKETLAKE(dev_priv)) { 4382 encoder->enable_clock = rkl_ddi_enable_clock; 4383 encoder->disable_clock = rkl_ddi_disable_clock; 4384 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 4385 encoder->get_config = rkl_ddi_get_config; 4386 } else if (IS_DG1(dev_priv)) { 4387 encoder->enable_clock = dg1_ddi_enable_clock; 4388 encoder->disable_clock = dg1_ddi_disable_clock; 4389 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 4390 encoder->get_config = dg1_ddi_get_config; 4391 } else if (IS_JSL_EHL(dev_priv)) { 4392 if (intel_ddi_is_tc(dev_priv, port)) { 4393 encoder->enable_clock = jsl_ddi_tc_enable_clock; 4394 encoder->disable_clock = jsl_ddi_tc_disable_clock; 4395 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 4396 encoder->get_config = icl_ddi_combo_get_config; 4397 } else { 4398 encoder->enable_clock = icl_ddi_combo_enable_clock; 4399 encoder->disable_clock = icl_ddi_combo_disable_clock; 4400 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 4401 encoder->get_config = icl_ddi_combo_get_config; 4402 } 4403 } else if (DISPLAY_VER(dev_priv) >= 11) { 4404 if (intel_ddi_is_tc(dev_priv, port)) { 4405 encoder->enable_clock = icl_ddi_tc_enable_clock; 4406 encoder->disable_clock = icl_ddi_tc_disable_clock; 4407 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 4408 encoder->get_config = icl_ddi_tc_get_config; 4409 } else { 4410 encoder->enable_clock = icl_ddi_combo_enable_clock; 4411 encoder->disable_clock = icl_ddi_combo_disable_clock; 4412 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 4413 encoder->get_config = icl_ddi_combo_get_config; 4414 } 4415 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 4416 /* BXT/GLK have fixed PLL->port mapping */ 4417 encoder->get_config = bxt_ddi_get_config; 4418 } else if (DISPLAY_VER(dev_priv) == 9) { 4419 encoder->enable_clock = skl_ddi_enable_clock; 4420 encoder->disable_clock = skl_ddi_disable_clock; 4421 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 4422 encoder->get_config = skl_ddi_get_config; 4423 } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 4424 encoder->enable_clock = hsw_ddi_enable_clock; 4425 encoder->disable_clock = hsw_ddi_disable_clock; 4426 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 4427 encoder->get_config = hsw_ddi_get_config; 4428 } 4429 4430 if (IS_DG2(dev_priv)) { 4431 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 4432 } else if (DISPLAY_VER(dev_priv) >= 12) { 4433 if (intel_phy_is_combo(dev_priv, phy)) 4434 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 4435 else 4436 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 4437 } else if (DISPLAY_VER(dev_priv) >= 11) { 4438 if (intel_phy_is_combo(dev_priv, phy)) 4439 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 4440 else 4441 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 4442 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 4443 encoder->set_signal_levels = bxt_ddi_phy_set_signal_levels; 4444 } else { 4445 encoder->set_signal_levels = hsw_set_signal_levels; 4446 } 4447 4448 intel_ddi_buf_trans_init(encoder); 4449 4450 if (DISPLAY_VER(dev_priv) >= 13) 4451 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port); 4452 else if (IS_DG1(dev_priv)) 4453 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); 4454 else if (IS_ROCKETLAKE(dev_priv)) 4455 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); 4456 else if (DISPLAY_VER(dev_priv) >= 12) 4457 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); 4458 else if (IS_JSL_EHL(dev_priv)) 4459 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); 4460 else if (DISPLAY_VER(dev_priv) == 11) 4461 encoder->hpd_pin = icl_hpd_pin(dev_priv, port); 4462 else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 4463 encoder->hpd_pin = skl_hpd_pin(dev_priv, port); 4464 else 4465 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 4466 4467 if (DISPLAY_VER(dev_priv) >= 11) 4468 dig_port->saved_port_bits = 4469 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 4470 & DDI_BUF_PORT_REVERSAL; 4471 else 4472 dig_port->saved_port_bits = 4473 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 4474 & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 4475 4476 if (intel_bios_is_lane_reversal_needed(dev_priv, port)) 4477 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL; 4478 4479 dig_port->dp.output_reg = INVALID_MMIO_REG; 4480 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 4481 dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 4482 4483 if (intel_phy_is_tc(dev_priv, phy)) { 4484 bool is_legacy = 4485 !intel_bios_encoder_supports_typec_usb(devdata) && 4486 !intel_bios_encoder_supports_tbt(devdata); 4487 4488 intel_tc_port_init(dig_port, is_legacy); 4489 4490 encoder->update_prepare = intel_ddi_update_prepare; 4491 encoder->update_complete = intel_ddi_update_complete; 4492 } 4493 4494 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 4495 dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO + 4496 port - PORT_A; 4497 4498 if (init_dp) { 4499 if (!intel_ddi_init_dp_connector(dig_port)) 4500 goto err; 4501 4502 dig_port->hpd_pulse = intel_dp_hpd_pulse; 4503 4504 if (dig_port->dp.mso_link_count) 4505 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv); 4506 } 4507 4508 /* In theory we don't need the encoder->type check, but leave it just in 4509 * case we have some really bad VBTs... */ 4510 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 4511 if (!intel_ddi_init_hdmi_connector(dig_port)) 4512 goto err; 4513 } 4514 4515 if (DISPLAY_VER(dev_priv) >= 11) { 4516 if (intel_phy_is_tc(dev_priv, phy)) 4517 dig_port->connected = intel_tc_port_connected; 4518 else 4519 dig_port->connected = lpt_digital_port_connected; 4520 } else if (DISPLAY_VER(dev_priv) >= 8) { 4521 if (port == PORT_A || IS_GEMINILAKE(dev_priv) || 4522 IS_BROXTON(dev_priv)) 4523 dig_port->connected = bdw_digital_port_connected; 4524 else 4525 dig_port->connected = lpt_digital_port_connected; 4526 } else { 4527 if (port == PORT_A) 4528 dig_port->connected = hsw_digital_port_connected; 4529 else 4530 dig_port->connected = lpt_digital_port_connected; 4531 } 4532 4533 intel_infoframe_init(dig_port); 4534 4535 return; 4536 4537 err: 4538 drm_encoder_cleanup(&encoder->base); 4539 kfree(dig_port); 4540 } 4541