1 /*
2  * Copyright © 2012 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Authors:
24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
25  *
26  */
27 
28 #include <drm/drm_scdc_helper.h>
29 
30 #include "i915_drv.h"
31 #include "intel_audio.h"
32 #include "intel_combo_phy.h"
33 #include "intel_connector.h"
34 #include "intel_ddi.h"
35 #include "intel_display_types.h"
36 #include "intel_dp.h"
37 #include "intel_dp_link_training.h"
38 #include "intel_dpio_phy.h"
39 #include "intel_dsi.h"
40 #include "intel_fifo_underrun.h"
41 #include "intel_gmbus.h"
42 #include "intel_hdcp.h"
43 #include "intel_hdmi.h"
44 #include "intel_hotplug.h"
45 #include "intel_lspcon.h"
46 #include "intel_panel.h"
47 #include "intel_psr.h"
48 #include "intel_tc.h"
49 #include "intel_vdsc.h"
50 
51 struct ddi_buf_trans {
52 	u32 trans1;	/* balance leg enable, de-emph level */
53 	u32 trans2;	/* vref sel, vswing */
54 	u8 i_boost;	/* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
55 };
56 
57 static const u8 index_to_dp_signal_levels[] = {
58 	[0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
59 	[1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
60 	[2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
61 	[3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
62 	[4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
63 	[5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
64 	[6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
65 	[7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
66 	[8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
67 	[9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
68 };
69 
70 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
71  * them for both DP and FDI transports, allowing those ports to
72  * automatically adapt to HDMI connections as well
73  */
74 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
75 	{ 0x00FFFFFF, 0x0006000E, 0x0 },
76 	{ 0x00D75FFF, 0x0005000A, 0x0 },
77 	{ 0x00C30FFF, 0x00040006, 0x0 },
78 	{ 0x80AAAFFF, 0x000B0000, 0x0 },
79 	{ 0x00FFFFFF, 0x0005000A, 0x0 },
80 	{ 0x00D75FFF, 0x000C0004, 0x0 },
81 	{ 0x80C30FFF, 0x000B0000, 0x0 },
82 	{ 0x00FFFFFF, 0x00040006, 0x0 },
83 	{ 0x80D75FFF, 0x000B0000, 0x0 },
84 };
85 
86 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
87 	{ 0x00FFFFFF, 0x0007000E, 0x0 },
88 	{ 0x00D75FFF, 0x000F000A, 0x0 },
89 	{ 0x00C30FFF, 0x00060006, 0x0 },
90 	{ 0x00AAAFFF, 0x001E0000, 0x0 },
91 	{ 0x00FFFFFF, 0x000F000A, 0x0 },
92 	{ 0x00D75FFF, 0x00160004, 0x0 },
93 	{ 0x00C30FFF, 0x001E0000, 0x0 },
94 	{ 0x00FFFFFF, 0x00060006, 0x0 },
95 	{ 0x00D75FFF, 0x001E0000, 0x0 },
96 };
97 
98 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
99 					/* Idx	NT mV d	T mV d	db	*/
100 	{ 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:	400	400	0	*/
101 	{ 0x00E79FFF, 0x000E000C, 0x0 },/* 1:	400	500	2	*/
102 	{ 0x00D75FFF, 0x0005000A, 0x0 },/* 2:	400	600	3.5	*/
103 	{ 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:	600	600	0	*/
104 	{ 0x00E79FFF, 0x001D0007, 0x0 },/* 4:	600	750	2	*/
105 	{ 0x00D75FFF, 0x000C0004, 0x0 },/* 5:	600	900	3.5	*/
106 	{ 0x00FFFFFF, 0x00040006, 0x0 },/* 6:	800	800	0	*/
107 	{ 0x80E79FFF, 0x00030002, 0x0 },/* 7:	800	1000	2	*/
108 	{ 0x00FFFFFF, 0x00140005, 0x0 },/* 8:	850	850	0	*/
109 	{ 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:	900	900	0	*/
110 	{ 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:	950	950	0	*/
111 	{ 0x80FFFFFF, 0x00030002, 0x0 },/* 11:	1000	1000	0	*/
112 };
113 
114 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
115 	{ 0x00FFFFFF, 0x00000012, 0x0 },
116 	{ 0x00EBAFFF, 0x00020011, 0x0 },
117 	{ 0x00C71FFF, 0x0006000F, 0x0 },
118 	{ 0x00AAAFFF, 0x000E000A, 0x0 },
119 	{ 0x00FFFFFF, 0x00020011, 0x0 },
120 	{ 0x00DB6FFF, 0x0005000F, 0x0 },
121 	{ 0x00BEEFFF, 0x000A000C, 0x0 },
122 	{ 0x00FFFFFF, 0x0005000F, 0x0 },
123 	{ 0x00DB6FFF, 0x000A000C, 0x0 },
124 };
125 
126 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
127 	{ 0x00FFFFFF, 0x0007000E, 0x0 },
128 	{ 0x00D75FFF, 0x000E000A, 0x0 },
129 	{ 0x00BEFFFF, 0x00140006, 0x0 },
130 	{ 0x80B2CFFF, 0x001B0002, 0x0 },
131 	{ 0x00FFFFFF, 0x000E000A, 0x0 },
132 	{ 0x00DB6FFF, 0x00160005, 0x0 },
133 	{ 0x80C71FFF, 0x001A0002, 0x0 },
134 	{ 0x00F7DFFF, 0x00180004, 0x0 },
135 	{ 0x80D75FFF, 0x001B0002, 0x0 },
136 };
137 
138 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
139 	{ 0x00FFFFFF, 0x0001000E, 0x0 },
140 	{ 0x00D75FFF, 0x0004000A, 0x0 },
141 	{ 0x00C30FFF, 0x00070006, 0x0 },
142 	{ 0x00AAAFFF, 0x000C0000, 0x0 },
143 	{ 0x00FFFFFF, 0x0004000A, 0x0 },
144 	{ 0x00D75FFF, 0x00090004, 0x0 },
145 	{ 0x00C30FFF, 0x000C0000, 0x0 },
146 	{ 0x00FFFFFF, 0x00070006, 0x0 },
147 	{ 0x00D75FFF, 0x000C0000, 0x0 },
148 };
149 
150 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
151 					/* Idx	NT mV d	T mV df	db	*/
152 	{ 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:	400	400	0	*/
153 	{ 0x00D75FFF, 0x000E000A, 0x0 },/* 1:	400	600	3.5	*/
154 	{ 0x00BEFFFF, 0x00140006, 0x0 },/* 2:	400	800	6	*/
155 	{ 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:	450	450	0	*/
156 	{ 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:	600	600	0	*/
157 	{ 0x00D7FFFF, 0x00140006, 0x0 },/* 5:	600	800	2.5	*/
158 	{ 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:	600	1000	4.5	*/
159 	{ 0x00FFFFFF, 0x00140006, 0x0 },/* 7:	800	800	0	*/
160 	{ 0x80E79FFF, 0x001B0002, 0x0 },/* 8:	800	1000	2	*/
161 	{ 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:	1000	1000	0	*/
162 };
163 
164 /* Skylake H and S */
165 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
166 	{ 0x00002016, 0x000000A0, 0x0 },
167 	{ 0x00005012, 0x0000009B, 0x0 },
168 	{ 0x00007011, 0x00000088, 0x0 },
169 	{ 0x80009010, 0x000000C0, 0x1 },
170 	{ 0x00002016, 0x0000009B, 0x0 },
171 	{ 0x00005012, 0x00000088, 0x0 },
172 	{ 0x80007011, 0x000000C0, 0x1 },
173 	{ 0x00002016, 0x000000DF, 0x0 },
174 	{ 0x80005012, 0x000000C0, 0x1 },
175 };
176 
177 /* Skylake U */
178 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
179 	{ 0x0000201B, 0x000000A2, 0x0 },
180 	{ 0x00005012, 0x00000088, 0x0 },
181 	{ 0x80007011, 0x000000CD, 0x1 },
182 	{ 0x80009010, 0x000000C0, 0x1 },
183 	{ 0x0000201B, 0x0000009D, 0x0 },
184 	{ 0x80005012, 0x000000C0, 0x1 },
185 	{ 0x80007011, 0x000000C0, 0x1 },
186 	{ 0x00002016, 0x00000088, 0x0 },
187 	{ 0x80005012, 0x000000C0, 0x1 },
188 };
189 
190 /* Skylake Y */
191 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
192 	{ 0x00000018, 0x000000A2, 0x0 },
193 	{ 0x00005012, 0x00000088, 0x0 },
194 	{ 0x80007011, 0x000000CD, 0x3 },
195 	{ 0x80009010, 0x000000C0, 0x3 },
196 	{ 0x00000018, 0x0000009D, 0x0 },
197 	{ 0x80005012, 0x000000C0, 0x3 },
198 	{ 0x80007011, 0x000000C0, 0x3 },
199 	{ 0x00000018, 0x00000088, 0x0 },
200 	{ 0x80005012, 0x000000C0, 0x3 },
201 };
202 
203 /* Kabylake H and S */
204 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
205 	{ 0x00002016, 0x000000A0, 0x0 },
206 	{ 0x00005012, 0x0000009B, 0x0 },
207 	{ 0x00007011, 0x00000088, 0x0 },
208 	{ 0x80009010, 0x000000C0, 0x1 },
209 	{ 0x00002016, 0x0000009B, 0x0 },
210 	{ 0x00005012, 0x00000088, 0x0 },
211 	{ 0x80007011, 0x000000C0, 0x1 },
212 	{ 0x00002016, 0x00000097, 0x0 },
213 	{ 0x80005012, 0x000000C0, 0x1 },
214 };
215 
216 /* Kabylake U */
217 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
218 	{ 0x0000201B, 0x000000A1, 0x0 },
219 	{ 0x00005012, 0x00000088, 0x0 },
220 	{ 0x80007011, 0x000000CD, 0x3 },
221 	{ 0x80009010, 0x000000C0, 0x3 },
222 	{ 0x0000201B, 0x0000009D, 0x0 },
223 	{ 0x80005012, 0x000000C0, 0x3 },
224 	{ 0x80007011, 0x000000C0, 0x3 },
225 	{ 0x00002016, 0x0000004F, 0x0 },
226 	{ 0x80005012, 0x000000C0, 0x3 },
227 };
228 
229 /* Kabylake Y */
230 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
231 	{ 0x00001017, 0x000000A1, 0x0 },
232 	{ 0x00005012, 0x00000088, 0x0 },
233 	{ 0x80007011, 0x000000CD, 0x3 },
234 	{ 0x8000800F, 0x000000C0, 0x3 },
235 	{ 0x00001017, 0x0000009D, 0x0 },
236 	{ 0x80005012, 0x000000C0, 0x3 },
237 	{ 0x80007011, 0x000000C0, 0x3 },
238 	{ 0x00001017, 0x0000004C, 0x0 },
239 	{ 0x80005012, 0x000000C0, 0x3 },
240 };
241 
242 /*
243  * Skylake/Kabylake H and S
244  * eDP 1.4 low vswing translation parameters
245  */
246 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
247 	{ 0x00000018, 0x000000A8, 0x0 },
248 	{ 0x00004013, 0x000000A9, 0x0 },
249 	{ 0x00007011, 0x000000A2, 0x0 },
250 	{ 0x00009010, 0x0000009C, 0x0 },
251 	{ 0x00000018, 0x000000A9, 0x0 },
252 	{ 0x00006013, 0x000000A2, 0x0 },
253 	{ 0x00007011, 0x000000A6, 0x0 },
254 	{ 0x00000018, 0x000000AB, 0x0 },
255 	{ 0x00007013, 0x0000009F, 0x0 },
256 	{ 0x00000018, 0x000000DF, 0x0 },
257 };
258 
259 /*
260  * Skylake/Kabylake U
261  * eDP 1.4 low vswing translation parameters
262  */
263 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
264 	{ 0x00000018, 0x000000A8, 0x0 },
265 	{ 0x00004013, 0x000000A9, 0x0 },
266 	{ 0x00007011, 0x000000A2, 0x0 },
267 	{ 0x00009010, 0x0000009C, 0x0 },
268 	{ 0x00000018, 0x000000A9, 0x0 },
269 	{ 0x00006013, 0x000000A2, 0x0 },
270 	{ 0x00007011, 0x000000A6, 0x0 },
271 	{ 0x00002016, 0x000000AB, 0x0 },
272 	{ 0x00005013, 0x0000009F, 0x0 },
273 	{ 0x00000018, 0x000000DF, 0x0 },
274 };
275 
276 /*
277  * Skylake/Kabylake Y
278  * eDP 1.4 low vswing translation parameters
279  */
280 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
281 	{ 0x00000018, 0x000000A8, 0x0 },
282 	{ 0x00004013, 0x000000AB, 0x0 },
283 	{ 0x00007011, 0x000000A4, 0x0 },
284 	{ 0x00009010, 0x000000DF, 0x0 },
285 	{ 0x00000018, 0x000000AA, 0x0 },
286 	{ 0x00006013, 0x000000A4, 0x0 },
287 	{ 0x00007011, 0x0000009D, 0x0 },
288 	{ 0x00000018, 0x000000A0, 0x0 },
289 	{ 0x00006012, 0x000000DF, 0x0 },
290 	{ 0x00000018, 0x0000008A, 0x0 },
291 };
292 
293 /* Skylake/Kabylake U, H and S */
294 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
295 	{ 0x00000018, 0x000000AC, 0x0 },
296 	{ 0x00005012, 0x0000009D, 0x0 },
297 	{ 0x00007011, 0x00000088, 0x0 },
298 	{ 0x00000018, 0x000000A1, 0x0 },
299 	{ 0x00000018, 0x00000098, 0x0 },
300 	{ 0x00004013, 0x00000088, 0x0 },
301 	{ 0x80006012, 0x000000CD, 0x1 },
302 	{ 0x00000018, 0x000000DF, 0x0 },
303 	{ 0x80003015, 0x000000CD, 0x1 },	/* Default */
304 	{ 0x80003015, 0x000000C0, 0x1 },
305 	{ 0x80000018, 0x000000C0, 0x1 },
306 };
307 
308 /* Skylake/Kabylake Y */
309 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
310 	{ 0x00000018, 0x000000A1, 0x0 },
311 	{ 0x00005012, 0x000000DF, 0x0 },
312 	{ 0x80007011, 0x000000CB, 0x3 },
313 	{ 0x00000018, 0x000000A4, 0x0 },
314 	{ 0x00000018, 0x0000009D, 0x0 },
315 	{ 0x00004013, 0x00000080, 0x0 },
316 	{ 0x80006013, 0x000000C0, 0x3 },
317 	{ 0x00000018, 0x0000008A, 0x0 },
318 	{ 0x80003015, 0x000000C0, 0x3 },	/* Default */
319 	{ 0x80003015, 0x000000C0, 0x3 },
320 	{ 0x80000018, 0x000000C0, 0x3 },
321 };
322 
323 struct bxt_ddi_buf_trans {
324 	u8 margin;	/* swing value */
325 	u8 scale;	/* scale value */
326 	u8 enable;	/* scale enable */
327 	u8 deemphasis;
328 };
329 
330 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
331 					/* Idx	NT mV diff	db  */
332 	{ 52,  0x9A, 0, 128, },	/* 0:	400		0   */
333 	{ 78,  0x9A, 0, 85,  },	/* 1:	400		3.5 */
334 	{ 104, 0x9A, 0, 64,  },	/* 2:	400		6   */
335 	{ 154, 0x9A, 0, 43,  },	/* 3:	400		9.5 */
336 	{ 77,  0x9A, 0, 128, },	/* 4:	600		0   */
337 	{ 116, 0x9A, 0, 85,  },	/* 5:	600		3.5 */
338 	{ 154, 0x9A, 0, 64,  },	/* 6:	600		6   */
339 	{ 102, 0x9A, 0, 128, },	/* 7:	800		0   */
340 	{ 154, 0x9A, 0, 85,  },	/* 8:	800		3.5 */
341 	{ 154, 0x9A, 1, 128, },	/* 9:	1200		0   */
342 };
343 
344 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
345 					/* Idx	NT mV diff	db  */
346 	{ 26, 0, 0, 128, },	/* 0:	200		0   */
347 	{ 38, 0, 0, 112, },	/* 1:	200		1.5 */
348 	{ 48, 0, 0, 96,  },	/* 2:	200		4   */
349 	{ 54, 0, 0, 69,  },	/* 3:	200		6   */
350 	{ 32, 0, 0, 128, },	/* 4:	250		0   */
351 	{ 48, 0, 0, 104, },	/* 5:	250		1.5 */
352 	{ 54, 0, 0, 85,  },	/* 6:	250		4   */
353 	{ 43, 0, 0, 128, },	/* 7:	300		0   */
354 	{ 54, 0, 0, 101, },	/* 8:	300		1.5 */
355 	{ 48, 0, 0, 128, },	/* 9:	300		0   */
356 };
357 
358 /* BSpec has 2 recommended values - entries 0 and 8.
359  * Using the entry with higher vswing.
360  */
361 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
362 					/* Idx	NT mV diff	db  */
363 	{ 52,  0x9A, 0, 128, },	/* 0:	400		0   */
364 	{ 52,  0x9A, 0, 85,  },	/* 1:	400		3.5 */
365 	{ 52,  0x9A, 0, 64,  },	/* 2:	400		6   */
366 	{ 42,  0x9A, 0, 43,  },	/* 3:	400		9.5 */
367 	{ 77,  0x9A, 0, 128, },	/* 4:	600		0   */
368 	{ 77,  0x9A, 0, 85,  },	/* 5:	600		3.5 */
369 	{ 77,  0x9A, 0, 64,  },	/* 6:	600		6   */
370 	{ 102, 0x9A, 0, 128, },	/* 7:	800		0   */
371 	{ 102, 0x9A, 0, 85,  },	/* 8:	800		3.5 */
372 	{ 154, 0x9A, 1, 128, },	/* 9:	1200		0   */
373 };
374 
375 struct cnl_ddi_buf_trans {
376 	u8 dw2_swing_sel;
377 	u8 dw7_n_scalar;
378 	u8 dw4_cursor_coeff;
379 	u8 dw4_post_cursor_2;
380 	u8 dw4_post_cursor_1;
381 };
382 
383 /* Voltage Swing Programming for VccIO 0.85V for DP */
384 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
385 						/* NT mV Trans mV db    */
386 	{ 0xA, 0x5D, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
387 	{ 0xA, 0x6A, 0x38, 0x00, 0x07 },	/* 350   500      3.1   */
388 	{ 0xB, 0x7A, 0x32, 0x00, 0x0D },	/* 350   700      6.0   */
389 	{ 0x6, 0x7C, 0x2D, 0x00, 0x12 },	/* 350   900      8.2   */
390 	{ 0xA, 0x69, 0x3F, 0x00, 0x00 },	/* 500   500      0.0   */
391 	{ 0xB, 0x7A, 0x36, 0x00, 0x09 },	/* 500   700      2.9   */
392 	{ 0x6, 0x7C, 0x30, 0x00, 0x0F },	/* 500   900      5.1   */
393 	{ 0xB, 0x7D, 0x3C, 0x00, 0x03 },	/* 650   725      0.9   */
394 	{ 0x6, 0x7C, 0x34, 0x00, 0x0B },	/* 600   900      3.5   */
395 	{ 0x6, 0x7B, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */
396 };
397 
398 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
399 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
400 						/* NT mV Trans mV db    */
401 	{ 0xA, 0x60, 0x3F, 0x00, 0x00 },	/* 450   450      0.0   */
402 	{ 0xB, 0x73, 0x36, 0x00, 0x09 },	/* 450   650      3.2   */
403 	{ 0x6, 0x7F, 0x31, 0x00, 0x0E },	/* 450   850      5.5   */
404 	{ 0xB, 0x73, 0x3F, 0x00, 0x00 },	/* 650   650      0.0   */
405 	{ 0x6, 0x7F, 0x37, 0x00, 0x08 },	/* 650   850      2.3   */
406 	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 850   850      0.0   */
407 	{ 0x6, 0x7F, 0x35, 0x00, 0x0A },	/* 600   850      3.0   */
408 };
409 
410 /* Voltage Swing Programming for VccIO 0.85V for eDP */
411 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
412 						/* NT mV Trans mV db    */
413 	{ 0xA, 0x66, 0x3A, 0x00, 0x05 },	/* 384   500      2.3   */
414 	{ 0x0, 0x7F, 0x38, 0x00, 0x07 },	/* 153   200      2.3   */
415 	{ 0x8, 0x7F, 0x38, 0x00, 0x07 },	/* 192   250      2.3   */
416 	{ 0x1, 0x7F, 0x38, 0x00, 0x07 },	/* 230   300      2.3   */
417 	{ 0x9, 0x7F, 0x38, 0x00, 0x07 },	/* 269   350      2.3   */
418 	{ 0xA, 0x66, 0x3C, 0x00, 0x03 },	/* 446   500      1.0   */
419 	{ 0xB, 0x70, 0x3C, 0x00, 0x03 },	/* 460   600      2.3   */
420 	{ 0xC, 0x75, 0x3C, 0x00, 0x03 },	/* 537   700      2.3   */
421 	{ 0x2, 0x7F, 0x3F, 0x00, 0x00 },	/* 400   400      0.0   */
422 };
423 
424 /* Voltage Swing Programming for VccIO 0.95V for DP */
425 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
426 						/* NT mV Trans mV db    */
427 	{ 0xA, 0x5D, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
428 	{ 0xA, 0x6A, 0x38, 0x00, 0x07 },	/* 350   500      3.1   */
429 	{ 0xB, 0x7A, 0x32, 0x00, 0x0D },	/* 350   700      6.0   */
430 	{ 0x6, 0x7C, 0x2D, 0x00, 0x12 },	/* 350   900      8.2   */
431 	{ 0xA, 0x69, 0x3F, 0x00, 0x00 },	/* 500   500      0.0   */
432 	{ 0xB, 0x7A, 0x36, 0x00, 0x09 },	/* 500   700      2.9   */
433 	{ 0x6, 0x7C, 0x30, 0x00, 0x0F },	/* 500   900      5.1   */
434 	{ 0xB, 0x7D, 0x3C, 0x00, 0x03 },	/* 650   725      0.9   */
435 	{ 0x6, 0x7C, 0x34, 0x00, 0x0B },	/* 600   900      3.5   */
436 	{ 0x6, 0x7B, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */
437 };
438 
439 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
440 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
441 						/* NT mV Trans mV db    */
442 	{ 0xA, 0x5C, 0x3F, 0x00, 0x00 },	/* 400   400      0.0   */
443 	{ 0xB, 0x69, 0x37, 0x00, 0x08 },	/* 400   600      3.5   */
444 	{ 0x5, 0x76, 0x31, 0x00, 0x0E },	/* 400   800      6.0   */
445 	{ 0xA, 0x5E, 0x3F, 0x00, 0x00 },	/* 450   450      0.0   */
446 	{ 0xB, 0x69, 0x3F, 0x00, 0x00 },	/* 600   600      0.0   */
447 	{ 0xB, 0x79, 0x35, 0x00, 0x0A },	/* 600   850      3.0   */
448 	{ 0x6, 0x7D, 0x32, 0x00, 0x0D },	/* 600   1000     4.4   */
449 	{ 0x5, 0x76, 0x3F, 0x00, 0x00 },	/* 800   800      0.0   */
450 	{ 0x6, 0x7D, 0x39, 0x00, 0x06 },	/* 800   1000     1.9   */
451 	{ 0x6, 0x7F, 0x39, 0x00, 0x06 },	/* 850   1050     1.8   */
452 	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 1050  1050     0.0   */
453 };
454 
455 /* Voltage Swing Programming for VccIO 0.95V for eDP */
456 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
457 						/* NT mV Trans mV db    */
458 	{ 0xA, 0x61, 0x3A, 0x00, 0x05 },	/* 384   500      2.3   */
459 	{ 0x0, 0x7F, 0x38, 0x00, 0x07 },	/* 153   200      2.3   */
460 	{ 0x8, 0x7F, 0x38, 0x00, 0x07 },	/* 192   250      2.3   */
461 	{ 0x1, 0x7F, 0x38, 0x00, 0x07 },	/* 230   300      2.3   */
462 	{ 0x9, 0x7F, 0x38, 0x00, 0x07 },	/* 269   350      2.3   */
463 	{ 0xA, 0x61, 0x3C, 0x00, 0x03 },	/* 446   500      1.0   */
464 	{ 0xB, 0x68, 0x39, 0x00, 0x06 },	/* 460   600      2.3   */
465 	{ 0xC, 0x6E, 0x39, 0x00, 0x06 },	/* 537   700      2.3   */
466 	{ 0x4, 0x7F, 0x3A, 0x00, 0x05 },	/* 460   600      2.3   */
467 	{ 0x2, 0x7F, 0x3F, 0x00, 0x00 },	/* 400   400      0.0   */
468 };
469 
470 /* Voltage Swing Programming for VccIO 1.05V for DP */
471 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
472 						/* NT mV Trans mV db    */
473 	{ 0xA, 0x58, 0x3F, 0x00, 0x00 },	/* 400   400      0.0   */
474 	{ 0xB, 0x64, 0x37, 0x00, 0x08 },	/* 400   600      3.5   */
475 	{ 0x5, 0x70, 0x31, 0x00, 0x0E },	/* 400   800      6.0   */
476 	{ 0x6, 0x7F, 0x2C, 0x00, 0x13 },	/* 400   1050     8.4   */
477 	{ 0xB, 0x64, 0x3F, 0x00, 0x00 },	/* 600   600      0.0   */
478 	{ 0x5, 0x73, 0x35, 0x00, 0x0A },	/* 600   850      3.0   */
479 	{ 0x6, 0x7F, 0x30, 0x00, 0x0F },	/* 550   1050     5.6   */
480 	{ 0x5, 0x76, 0x3E, 0x00, 0x01 },	/* 850   900      0.5   */
481 	{ 0x6, 0x7F, 0x36, 0x00, 0x09 },	/* 750   1050     2.9   */
482 	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 1050  1050     0.0   */
483 };
484 
485 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
486 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
487 						/* NT mV Trans mV db    */
488 	{ 0xA, 0x58, 0x3F, 0x00, 0x00 },	/* 400   400      0.0   */
489 	{ 0xB, 0x64, 0x37, 0x00, 0x08 },	/* 400   600      3.5   */
490 	{ 0x5, 0x70, 0x31, 0x00, 0x0E },	/* 400   800      6.0   */
491 	{ 0xA, 0x5B, 0x3F, 0x00, 0x00 },	/* 450   450      0.0   */
492 	{ 0xB, 0x64, 0x3F, 0x00, 0x00 },	/* 600   600      0.0   */
493 	{ 0x5, 0x73, 0x35, 0x00, 0x0A },	/* 600   850      3.0   */
494 	{ 0x6, 0x7C, 0x32, 0x00, 0x0D },	/* 600   1000     4.4   */
495 	{ 0x5, 0x70, 0x3F, 0x00, 0x00 },	/* 800   800      0.0   */
496 	{ 0x6, 0x7C, 0x39, 0x00, 0x06 },	/* 800   1000     1.9   */
497 	{ 0x6, 0x7F, 0x39, 0x00, 0x06 },	/* 850   1050     1.8   */
498 	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 1050  1050     0.0   */
499 };
500 
501 /* Voltage Swing Programming for VccIO 1.05V for eDP */
502 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
503 						/* NT mV Trans mV db    */
504 	{ 0xA, 0x5E, 0x3A, 0x00, 0x05 },	/* 384   500      2.3   */
505 	{ 0x0, 0x7F, 0x38, 0x00, 0x07 },	/* 153   200      2.3   */
506 	{ 0x8, 0x7F, 0x38, 0x00, 0x07 },	/* 192   250      2.3   */
507 	{ 0x1, 0x7F, 0x38, 0x00, 0x07 },	/* 230   300      2.3   */
508 	{ 0x9, 0x7F, 0x38, 0x00, 0x07 },	/* 269   350      2.3   */
509 	{ 0xA, 0x5E, 0x3C, 0x00, 0x03 },	/* 446   500      1.0   */
510 	{ 0xB, 0x64, 0x39, 0x00, 0x06 },	/* 460   600      2.3   */
511 	{ 0xE, 0x6A, 0x39, 0x00, 0x06 },	/* 537   700      2.3   */
512 	{ 0x2, 0x7F, 0x3F, 0x00, 0x00 },	/* 400   400      0.0   */
513 };
514 
515 /* icl_combo_phy_ddi_translations */
516 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
517 						/* NT mV Trans mV db    */
518 	{ 0xA, 0x35, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
519 	{ 0xA, 0x4F, 0x37, 0x00, 0x08 },	/* 350   500      3.1   */
520 	{ 0xC, 0x71, 0x2F, 0x00, 0x10 },	/* 350   700      6.0   */
521 	{ 0x6, 0x7F, 0x2B, 0x00, 0x14 },	/* 350   900      8.2   */
522 	{ 0xA, 0x4C, 0x3F, 0x00, 0x00 },	/* 500   500      0.0   */
523 	{ 0xC, 0x73, 0x34, 0x00, 0x0B },	/* 500   700      2.9   */
524 	{ 0x6, 0x7F, 0x2F, 0x00, 0x10 },	/* 500   900      5.1   */
525 	{ 0xC, 0x6C, 0x3C, 0x00, 0x03 },	/* 650   700      0.6   */
526 	{ 0x6, 0x7F, 0x35, 0x00, 0x0A },	/* 600   900      3.5   */
527 	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */
528 };
529 
530 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
531 						/* NT mV Trans mV db    */
532 	{ 0x0, 0x7F, 0x3F, 0x00, 0x00 },	/* 200   200      0.0   */
533 	{ 0x8, 0x7F, 0x38, 0x00, 0x07 },	/* 200   250      1.9   */
534 	{ 0x1, 0x7F, 0x33, 0x00, 0x0C },	/* 200   300      3.5   */
535 	{ 0x9, 0x7F, 0x31, 0x00, 0x0E },	/* 200   350      4.9   */
536 	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 250   250      0.0   */
537 	{ 0x1, 0x7F, 0x38, 0x00, 0x07 },	/* 250   300      1.6   */
538 	{ 0x9, 0x7F, 0x35, 0x00, 0x0A },	/* 250   350      2.9   */
539 	{ 0x1, 0x7F, 0x3F, 0x00, 0x00 },	/* 300   300      0.0   */
540 	{ 0x9, 0x7F, 0x38, 0x00, 0x07 },	/* 300   350      1.3   */
541 	{ 0x9, 0x7F, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
542 };
543 
544 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
545 						/* NT mV Trans mV db    */
546 	{ 0xA, 0x35, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
547 	{ 0xA, 0x4F, 0x37, 0x00, 0x08 },	/* 350   500      3.1   */
548 	{ 0xC, 0x71, 0x2F, 0x00, 0x10 },	/* 350   700      6.0   */
549 	{ 0x6, 0x7F, 0x2B, 0x00, 0x14 },	/* 350   900      8.2   */
550 	{ 0xA, 0x4C, 0x3F, 0x00, 0x00 },	/* 500   500      0.0   */
551 	{ 0xC, 0x73, 0x34, 0x00, 0x0B },	/* 500   700      2.9   */
552 	{ 0x6, 0x7F, 0x2F, 0x00, 0x10 },	/* 500   900      5.1   */
553 	{ 0xC, 0x6C, 0x3C, 0x00, 0x03 },	/* 650   700      0.6   */
554 	{ 0x6, 0x7F, 0x35, 0x00, 0x0A },	/* 600   900      3.5   */
555 	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */
556 };
557 
558 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
559 						/* NT mV Trans mV db    */
560 	{ 0xA, 0x60, 0x3F, 0x00, 0x00 },	/* 450   450      0.0   */
561 	{ 0xB, 0x73, 0x36, 0x00, 0x09 },	/* 450   650      3.2   */
562 	{ 0x6, 0x7F, 0x31, 0x00, 0x0E },	/* 450   850      5.5   */
563 	{ 0xB, 0x73, 0x3F, 0x00, 0x00 },	/* 650   650      0.0   ALS */
564 	{ 0x6, 0x7F, 0x37, 0x00, 0x08 },	/* 650   850      2.3   */
565 	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 850   850      0.0   */
566 	{ 0x6, 0x7F, 0x35, 0x00, 0x0A },	/* 600   850      3.0   */
567 };
568 
569 struct icl_mg_phy_ddi_buf_trans {
570 	u32 cri_txdeemph_override_5_0;
571 	u32 cri_txdeemph_override_11_6;
572 	u32 cri_txdeemph_override_17_12;
573 };
574 
575 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
576 				/* Voltage swing  pre-emphasis */
577 	{ 0x0, 0x1B, 0x00 },	/* 0              0   */
578 	{ 0x0, 0x23, 0x08 },	/* 0              1   */
579 	{ 0x0, 0x2D, 0x12 },	/* 0              2   */
580 	{ 0x0, 0x00, 0x00 },	/* 0              3   */
581 	{ 0x0, 0x23, 0x00 },	/* 1              0   */
582 	{ 0x0, 0x2B, 0x09 },	/* 1              1   */
583 	{ 0x0, 0x2E, 0x11 },	/* 1              2   */
584 	{ 0x0, 0x2F, 0x00 },	/* 2              0   */
585 	{ 0x0, 0x33, 0x0C },	/* 2              1   */
586 	{ 0x0, 0x00, 0x00 },	/* 3              0   */
587 };
588 
589 static const struct ddi_buf_trans *
590 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
591 {
592 	if (dev_priv->vbt.edp.low_vswing) {
593 		*n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
594 		return bdw_ddi_translations_edp;
595 	} else {
596 		*n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
597 		return bdw_ddi_translations_dp;
598 	}
599 }
600 
601 static const struct ddi_buf_trans *
602 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
603 {
604 	if (IS_SKL_ULX(dev_priv)) {
605 		*n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
606 		return skl_y_ddi_translations_dp;
607 	} else if (IS_SKL_ULT(dev_priv)) {
608 		*n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
609 		return skl_u_ddi_translations_dp;
610 	} else {
611 		*n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
612 		return skl_ddi_translations_dp;
613 	}
614 }
615 
616 static const struct ddi_buf_trans *
617 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
618 {
619 	if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv)) {
620 		*n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
621 		return kbl_y_ddi_translations_dp;
622 	} else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
623 		*n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
624 		return kbl_u_ddi_translations_dp;
625 	} else {
626 		*n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
627 		return kbl_ddi_translations_dp;
628 	}
629 }
630 
631 static const struct ddi_buf_trans *
632 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
633 {
634 	if (dev_priv->vbt.edp.low_vswing) {
635 		if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
636 		    IS_CFL_ULX(dev_priv)) {
637 			*n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
638 			return skl_y_ddi_translations_edp;
639 		} else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
640 			   IS_CFL_ULT(dev_priv)) {
641 			*n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
642 			return skl_u_ddi_translations_edp;
643 		} else {
644 			*n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
645 			return skl_ddi_translations_edp;
646 		}
647 	}
648 
649 	if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
650 		return kbl_get_buf_trans_dp(dev_priv, n_entries);
651 	else
652 		return skl_get_buf_trans_dp(dev_priv, n_entries);
653 }
654 
655 static const struct ddi_buf_trans *
656 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
657 {
658 	if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
659 	    IS_CFL_ULX(dev_priv)) {
660 		*n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
661 		return skl_y_ddi_translations_hdmi;
662 	} else {
663 		*n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
664 		return skl_ddi_translations_hdmi;
665 	}
666 }
667 
668 static int skl_buf_trans_num_entries(enum port port, int n_entries)
669 {
670 	/* Only DDIA and DDIE can select the 10th register with DP */
671 	if (port == PORT_A || port == PORT_E)
672 		return min(n_entries, 10);
673 	else
674 		return min(n_entries, 9);
675 }
676 
677 static const struct ddi_buf_trans *
678 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
679 			   enum port port, int *n_entries)
680 {
681 	if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
682 		const struct ddi_buf_trans *ddi_translations =
683 			kbl_get_buf_trans_dp(dev_priv, n_entries);
684 		*n_entries = skl_buf_trans_num_entries(port, *n_entries);
685 		return ddi_translations;
686 	} else if (IS_SKYLAKE(dev_priv)) {
687 		const struct ddi_buf_trans *ddi_translations =
688 			skl_get_buf_trans_dp(dev_priv, n_entries);
689 		*n_entries = skl_buf_trans_num_entries(port, *n_entries);
690 		return ddi_translations;
691 	} else if (IS_BROADWELL(dev_priv)) {
692 		*n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
693 		return  bdw_ddi_translations_dp;
694 	} else if (IS_HASWELL(dev_priv)) {
695 		*n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
696 		return hsw_ddi_translations_dp;
697 	}
698 
699 	*n_entries = 0;
700 	return NULL;
701 }
702 
703 static const struct ddi_buf_trans *
704 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
705 			    enum port port, int *n_entries)
706 {
707 	if (IS_GEN9_BC(dev_priv)) {
708 		const struct ddi_buf_trans *ddi_translations =
709 			skl_get_buf_trans_edp(dev_priv, n_entries);
710 		*n_entries = skl_buf_trans_num_entries(port, *n_entries);
711 		return ddi_translations;
712 	} else if (IS_BROADWELL(dev_priv)) {
713 		return bdw_get_buf_trans_edp(dev_priv, n_entries);
714 	} else if (IS_HASWELL(dev_priv)) {
715 		*n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
716 		return hsw_ddi_translations_dp;
717 	}
718 
719 	*n_entries = 0;
720 	return NULL;
721 }
722 
723 static const struct ddi_buf_trans *
724 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
725 			    int *n_entries)
726 {
727 	if (IS_BROADWELL(dev_priv)) {
728 		*n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
729 		return bdw_ddi_translations_fdi;
730 	} else if (IS_HASWELL(dev_priv)) {
731 		*n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
732 		return hsw_ddi_translations_fdi;
733 	}
734 
735 	*n_entries = 0;
736 	return NULL;
737 }
738 
739 static const struct ddi_buf_trans *
740 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
741 			     int *n_entries)
742 {
743 	if (IS_GEN9_BC(dev_priv)) {
744 		return skl_get_buf_trans_hdmi(dev_priv, n_entries);
745 	} else if (IS_BROADWELL(dev_priv)) {
746 		*n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
747 		return bdw_ddi_translations_hdmi;
748 	} else if (IS_HASWELL(dev_priv)) {
749 		*n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
750 		return hsw_ddi_translations_hdmi;
751 	}
752 
753 	*n_entries = 0;
754 	return NULL;
755 }
756 
757 static const struct bxt_ddi_buf_trans *
758 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
759 {
760 	*n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
761 	return bxt_ddi_translations_dp;
762 }
763 
764 static const struct bxt_ddi_buf_trans *
765 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
766 {
767 	if (dev_priv->vbt.edp.low_vswing) {
768 		*n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
769 		return bxt_ddi_translations_edp;
770 	}
771 
772 	return bxt_get_buf_trans_dp(dev_priv, n_entries);
773 }
774 
775 static const struct bxt_ddi_buf_trans *
776 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
777 {
778 	*n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
779 	return bxt_ddi_translations_hdmi;
780 }
781 
782 static const struct cnl_ddi_buf_trans *
783 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
784 {
785 	u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
786 
787 	if (voltage == VOLTAGE_INFO_0_85V) {
788 		*n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
789 		return cnl_ddi_translations_hdmi_0_85V;
790 	} else if (voltage == VOLTAGE_INFO_0_95V) {
791 		*n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
792 		return cnl_ddi_translations_hdmi_0_95V;
793 	} else if (voltage == VOLTAGE_INFO_1_05V) {
794 		*n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
795 		return cnl_ddi_translations_hdmi_1_05V;
796 	} else {
797 		*n_entries = 1; /* shut up gcc */
798 		MISSING_CASE(voltage);
799 	}
800 	return NULL;
801 }
802 
803 static const struct cnl_ddi_buf_trans *
804 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
805 {
806 	u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
807 
808 	if (voltage == VOLTAGE_INFO_0_85V) {
809 		*n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
810 		return cnl_ddi_translations_dp_0_85V;
811 	} else if (voltage == VOLTAGE_INFO_0_95V) {
812 		*n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
813 		return cnl_ddi_translations_dp_0_95V;
814 	} else if (voltage == VOLTAGE_INFO_1_05V) {
815 		*n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
816 		return cnl_ddi_translations_dp_1_05V;
817 	} else {
818 		*n_entries = 1; /* shut up gcc */
819 		MISSING_CASE(voltage);
820 	}
821 	return NULL;
822 }
823 
824 static const struct cnl_ddi_buf_trans *
825 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
826 {
827 	u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
828 
829 	if (dev_priv->vbt.edp.low_vswing) {
830 		if (voltage == VOLTAGE_INFO_0_85V) {
831 			*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
832 			return cnl_ddi_translations_edp_0_85V;
833 		} else if (voltage == VOLTAGE_INFO_0_95V) {
834 			*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
835 			return cnl_ddi_translations_edp_0_95V;
836 		} else if (voltage == VOLTAGE_INFO_1_05V) {
837 			*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
838 			return cnl_ddi_translations_edp_1_05V;
839 		} else {
840 			*n_entries = 1; /* shut up gcc */
841 			MISSING_CASE(voltage);
842 		}
843 		return NULL;
844 	} else {
845 		return cnl_get_buf_trans_dp(dev_priv, n_entries);
846 	}
847 }
848 
849 static const struct cnl_ddi_buf_trans *
850 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
851 			int *n_entries)
852 {
853 	if (type == INTEL_OUTPUT_HDMI) {
854 		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
855 		return icl_combo_phy_ddi_translations_hdmi;
856 	} else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
857 		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
858 		return icl_combo_phy_ddi_translations_edp_hbr3;
859 	} else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
860 		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
861 		return icl_combo_phy_ddi_translations_edp_hbr2;
862 	}
863 
864 	*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
865 	return icl_combo_phy_ddi_translations_dp_hbr2;
866 }
867 
868 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
869 {
870 	int n_entries, level, default_entry;
871 	enum phy phy = intel_port_to_phy(dev_priv, port);
872 
873 	level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
874 
875 	if (INTEL_GEN(dev_priv) >= 11) {
876 		if (intel_phy_is_combo(dev_priv, phy))
877 			icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
878 						0, &n_entries);
879 		else
880 			n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
881 		default_entry = n_entries - 1;
882 	} else if (IS_CANNONLAKE(dev_priv)) {
883 		cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
884 		default_entry = n_entries - 1;
885 	} else if (IS_GEN9_LP(dev_priv)) {
886 		bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
887 		default_entry = n_entries - 1;
888 	} else if (IS_GEN9_BC(dev_priv)) {
889 		intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
890 		default_entry = 8;
891 	} else if (IS_BROADWELL(dev_priv)) {
892 		intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
893 		default_entry = 7;
894 	} else if (IS_HASWELL(dev_priv)) {
895 		intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
896 		default_entry = 6;
897 	} else {
898 		WARN(1, "ddi translation table missing\n");
899 		return 0;
900 	}
901 
902 	/* Choose a good default if VBT is badly populated */
903 	if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
904 		level = default_entry;
905 
906 	if (WARN_ON_ONCE(n_entries == 0))
907 		return 0;
908 	if (WARN_ON_ONCE(level >= n_entries))
909 		level = n_entries - 1;
910 
911 	return level;
912 }
913 
914 /*
915  * Starting with Haswell, DDI port buffers must be programmed with correct
916  * values in advance. This function programs the correct values for
917  * DP/eDP/FDI use cases.
918  */
919 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
920 					 const struct intel_crtc_state *crtc_state)
921 {
922 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
923 	u32 iboost_bit = 0;
924 	int i, n_entries;
925 	enum port port = encoder->port;
926 	const struct ddi_buf_trans *ddi_translations;
927 
928 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
929 		ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
930 							       &n_entries);
931 	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
932 		ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
933 							       &n_entries);
934 	else
935 		ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
936 							      &n_entries);
937 
938 	/* If we're boosting the current, set bit 31 of trans1 */
939 	if (IS_GEN9_BC(dev_priv) &&
940 	    dev_priv->vbt.ddi_port_info[port].dp_boost_level)
941 		iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
942 
943 	for (i = 0; i < n_entries; i++) {
944 		I915_WRITE(DDI_BUF_TRANS_LO(port, i),
945 			   ddi_translations[i].trans1 | iboost_bit);
946 		I915_WRITE(DDI_BUF_TRANS_HI(port, i),
947 			   ddi_translations[i].trans2);
948 	}
949 }
950 
951 /*
952  * Starting with Haswell, DDI port buffers must be programmed with correct
953  * values in advance. This function programs the correct values for
954  * HDMI/DVI use cases.
955  */
956 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
957 					   int level)
958 {
959 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
960 	u32 iboost_bit = 0;
961 	int n_entries;
962 	enum port port = encoder->port;
963 	const struct ddi_buf_trans *ddi_translations;
964 
965 	ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
966 
967 	if (WARN_ON_ONCE(!ddi_translations))
968 		return;
969 	if (WARN_ON_ONCE(level >= n_entries))
970 		level = n_entries - 1;
971 
972 	/* If we're boosting the current, set bit 31 of trans1 */
973 	if (IS_GEN9_BC(dev_priv) &&
974 	    dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
975 		iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
976 
977 	/* Entry 9 is for HDMI: */
978 	I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
979 		   ddi_translations[level].trans1 | iboost_bit);
980 	I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
981 		   ddi_translations[level].trans2);
982 }
983 
984 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
985 				    enum port port)
986 {
987 	i915_reg_t reg = DDI_BUF_CTL(port);
988 	int i;
989 
990 	for (i = 0; i < 16; i++) {
991 		udelay(1);
992 		if (I915_READ(reg) & DDI_BUF_IS_IDLE)
993 			return;
994 	}
995 	DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
996 }
997 
998 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
999 {
1000 	switch (pll->info->id) {
1001 	case DPLL_ID_WRPLL1:
1002 		return PORT_CLK_SEL_WRPLL1;
1003 	case DPLL_ID_WRPLL2:
1004 		return PORT_CLK_SEL_WRPLL2;
1005 	case DPLL_ID_SPLL:
1006 		return PORT_CLK_SEL_SPLL;
1007 	case DPLL_ID_LCPLL_810:
1008 		return PORT_CLK_SEL_LCPLL_810;
1009 	case DPLL_ID_LCPLL_1350:
1010 		return PORT_CLK_SEL_LCPLL_1350;
1011 	case DPLL_ID_LCPLL_2700:
1012 		return PORT_CLK_SEL_LCPLL_2700;
1013 	default:
1014 		MISSING_CASE(pll->info->id);
1015 		return PORT_CLK_SEL_NONE;
1016 	}
1017 }
1018 
1019 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
1020 				  const struct intel_crtc_state *crtc_state)
1021 {
1022 	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1023 	int clock = crtc_state->port_clock;
1024 	const enum intel_dpll_id id = pll->info->id;
1025 
1026 	switch (id) {
1027 	default:
1028 		/*
1029 		 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
1030 		 * here, so do warn if this get passed in
1031 		 */
1032 		MISSING_CASE(id);
1033 		return DDI_CLK_SEL_NONE;
1034 	case DPLL_ID_ICL_TBTPLL:
1035 		switch (clock) {
1036 		case 162000:
1037 			return DDI_CLK_SEL_TBT_162;
1038 		case 270000:
1039 			return DDI_CLK_SEL_TBT_270;
1040 		case 540000:
1041 			return DDI_CLK_SEL_TBT_540;
1042 		case 810000:
1043 			return DDI_CLK_SEL_TBT_810;
1044 		default:
1045 			MISSING_CASE(clock);
1046 			return DDI_CLK_SEL_NONE;
1047 		}
1048 	case DPLL_ID_ICL_MGPLL1:
1049 	case DPLL_ID_ICL_MGPLL2:
1050 	case DPLL_ID_ICL_MGPLL3:
1051 	case DPLL_ID_ICL_MGPLL4:
1052 		return DDI_CLK_SEL_MG;
1053 	}
1054 }
1055 
1056 /* Starting with Haswell, different DDI ports can work in FDI mode for
1057  * connection to the PCH-located connectors. For this, it is necessary to train
1058  * both the DDI port and PCH receiver for the desired DDI buffer settings.
1059  *
1060  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1061  * please note that when FDI mode is active on DDI E, it shares 2 lines with
1062  * DDI A (which is used for eDP)
1063  */
1064 
1065 void hsw_fdi_link_train(struct intel_crtc *crtc,
1066 			const struct intel_crtc_state *crtc_state)
1067 {
1068 	struct drm_device *dev = crtc->base.dev;
1069 	struct drm_i915_private *dev_priv = to_i915(dev);
1070 	struct intel_encoder *encoder;
1071 	u32 temp, i, rx_ctl_val, ddi_pll_sel;
1072 
1073 	for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1074 		WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
1075 		intel_prepare_dp_ddi_buffers(encoder, crtc_state);
1076 	}
1077 
1078 	/* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1079 	 * mode set "sequence for CRT port" document:
1080 	 * - TP1 to TP2 time with the default value
1081 	 * - FDI delay to 90h
1082 	 *
1083 	 * WaFDIAutoLinkSetTimingOverrride:hsw
1084 	 */
1085 	I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
1086 				  FDI_RX_PWRDN_LANE0_VAL(2) |
1087 				  FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1088 
1089 	/* Enable the PCH Receiver FDI PLL */
1090 	rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1091 		     FDI_RX_PLL_ENABLE |
1092 		     FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1093 	I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1094 	POSTING_READ(FDI_RX_CTL(PIPE_A));
1095 	udelay(220);
1096 
1097 	/* Switch from Rawclk to PCDclk */
1098 	rx_ctl_val |= FDI_PCDCLK;
1099 	I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1100 
1101 	/* Configure Port Clock Select */
1102 	ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
1103 	I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1104 	WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
1105 
1106 	/* Start the training iterating through available voltages and emphasis,
1107 	 * testing each value twice. */
1108 	for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
1109 		/* Configure DP_TP_CTL with auto-training */
1110 		I915_WRITE(DP_TP_CTL(PORT_E),
1111 					DP_TP_CTL_FDI_AUTOTRAIN |
1112 					DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1113 					DP_TP_CTL_LINK_TRAIN_PAT1 |
1114 					DP_TP_CTL_ENABLE);
1115 
1116 		/* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1117 		 * DDI E does not support port reversal, the functionality is
1118 		 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1119 		 * port reversal bit */
1120 		I915_WRITE(DDI_BUF_CTL(PORT_E),
1121 			   DDI_BUF_CTL_ENABLE |
1122 			   ((crtc_state->fdi_lanes - 1) << 1) |
1123 			   DDI_BUF_TRANS_SELECT(i / 2));
1124 		POSTING_READ(DDI_BUF_CTL(PORT_E));
1125 
1126 		udelay(600);
1127 
1128 		/* Program PCH FDI Receiver TU */
1129 		I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1130 
1131 		/* Enable PCH FDI Receiver with auto-training */
1132 		rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1133 		I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1134 		POSTING_READ(FDI_RX_CTL(PIPE_A));
1135 
1136 		/* Wait for FDI receiver lane calibration */
1137 		udelay(30);
1138 
1139 		/* Unset FDI_RX_MISC pwrdn lanes */
1140 		temp = I915_READ(FDI_RX_MISC(PIPE_A));
1141 		temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1142 		I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1143 		POSTING_READ(FDI_RX_MISC(PIPE_A));
1144 
1145 		/* Wait for FDI auto training time */
1146 		udelay(5);
1147 
1148 		temp = I915_READ(DP_TP_STATUS(PORT_E));
1149 		if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1150 			DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
1151 			break;
1152 		}
1153 
1154 		/*
1155 		 * Leave things enabled even if we failed to train FDI.
1156 		 * Results in less fireworks from the state checker.
1157 		 */
1158 		if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1159 			DRM_ERROR("FDI link training failed!\n");
1160 			break;
1161 		}
1162 
1163 		rx_ctl_val &= ~FDI_RX_ENABLE;
1164 		I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1165 		POSTING_READ(FDI_RX_CTL(PIPE_A));
1166 
1167 		temp = I915_READ(DDI_BUF_CTL(PORT_E));
1168 		temp &= ~DDI_BUF_CTL_ENABLE;
1169 		I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1170 		POSTING_READ(DDI_BUF_CTL(PORT_E));
1171 
1172 		/* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1173 		temp = I915_READ(DP_TP_CTL(PORT_E));
1174 		temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1175 		temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1176 		I915_WRITE(DP_TP_CTL(PORT_E), temp);
1177 		POSTING_READ(DP_TP_CTL(PORT_E));
1178 
1179 		intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1180 
1181 		/* Reset FDI_RX_MISC pwrdn lanes */
1182 		temp = I915_READ(FDI_RX_MISC(PIPE_A));
1183 		temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1184 		temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1185 		I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1186 		POSTING_READ(FDI_RX_MISC(PIPE_A));
1187 	}
1188 
1189 	/* Enable normal pixel sending for FDI */
1190 	I915_WRITE(DP_TP_CTL(PORT_E),
1191 		   DP_TP_CTL_FDI_AUTOTRAIN |
1192 		   DP_TP_CTL_LINK_TRAIN_NORMAL |
1193 		   DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1194 		   DP_TP_CTL_ENABLE);
1195 }
1196 
1197 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1198 {
1199 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1200 	struct intel_digital_port *intel_dig_port =
1201 		enc_to_dig_port(&encoder->base);
1202 
1203 	intel_dp->DP = intel_dig_port->saved_port_bits |
1204 		DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1205 	intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1206 }
1207 
1208 static struct intel_encoder *
1209 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
1210 {
1211 	struct drm_device *dev = crtc->base.dev;
1212 	struct intel_encoder *encoder, *ret = NULL;
1213 	int num_encoders = 0;
1214 
1215 	for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1216 		ret = encoder;
1217 		num_encoders++;
1218 	}
1219 
1220 	if (num_encoders != 1)
1221 		WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
1222 		     pipe_name(crtc->pipe));
1223 
1224 	BUG_ON(ret == NULL);
1225 	return ret;
1226 }
1227 
1228 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1229 				   i915_reg_t reg)
1230 {
1231 	int refclk;
1232 	int n, p, r;
1233 	u32 wrpll;
1234 
1235 	wrpll = I915_READ(reg);
1236 	switch (wrpll & WRPLL_REF_MASK) {
1237 	case WRPLL_REF_SPECIAL_HSW:
1238 		/*
1239 		 * muxed-SSC for BDW.
1240 		 * non-SSC for non-ULT HSW. Check FUSE_STRAP3
1241 		 * for the non-SSC reference frequency.
1242 		 */
1243 		if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) {
1244 			if (I915_READ(FUSE_STRAP3) & HSW_REF_CLK_SELECT)
1245 				refclk = 24;
1246 			else
1247 				refclk = 135;
1248 			break;
1249 		}
1250 		/* fall through */
1251 	case WRPLL_REF_PCH_SSC:
1252 		/*
1253 		 * We could calculate spread here, but our checking
1254 		 * code only cares about 5% accuracy, and spread is a max of
1255 		 * 0.5% downspread.
1256 		 */
1257 		refclk = 135;
1258 		break;
1259 	case WRPLL_REF_LCPLL:
1260 		refclk = 2700;
1261 		break;
1262 	default:
1263 		MISSING_CASE(wrpll);
1264 		return 0;
1265 	}
1266 
1267 	r = wrpll & WRPLL_DIVIDER_REF_MASK;
1268 	p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1269 	n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1270 
1271 	/* Convert to KHz, p & r have a fixed point portion */
1272 	return (refclk * n * 100) / (p * r);
1273 }
1274 
1275 static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state)
1276 {
1277 	u32 p0, p1, p2, dco_freq;
1278 
1279 	p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
1280 	p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK;
1281 
1282 	if (pll_state->cfgcr2 &  DPLL_CFGCR2_QDIV_MODE(1))
1283 		p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1284 	else
1285 		p1 = 1;
1286 
1287 
1288 	switch (p0) {
1289 	case DPLL_CFGCR2_PDIV_1:
1290 		p0 = 1;
1291 		break;
1292 	case DPLL_CFGCR2_PDIV_2:
1293 		p0 = 2;
1294 		break;
1295 	case DPLL_CFGCR2_PDIV_3:
1296 		p0 = 3;
1297 		break;
1298 	case DPLL_CFGCR2_PDIV_7:
1299 		p0 = 7;
1300 		break;
1301 	}
1302 
1303 	switch (p2) {
1304 	case DPLL_CFGCR2_KDIV_5:
1305 		p2 = 5;
1306 		break;
1307 	case DPLL_CFGCR2_KDIV_2:
1308 		p2 = 2;
1309 		break;
1310 	case DPLL_CFGCR2_KDIV_3:
1311 		p2 = 3;
1312 		break;
1313 	case DPLL_CFGCR2_KDIV_1:
1314 		p2 = 1;
1315 		break;
1316 	}
1317 
1318 	dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK)
1319 		* 24 * 1000;
1320 
1321 	dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9)
1322 		     * 24 * 1000) / 0x8000;
1323 
1324 	if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1325 		return 0;
1326 
1327 	return dco_freq / (p0 * p1 * p2 * 5);
1328 }
1329 
1330 int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1331 			struct intel_dpll_hw_state *pll_state)
1332 {
1333 	u32 p0, p1, p2, dco_freq, ref_clock;
1334 
1335 	p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1336 	p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1337 
1338 	if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1339 		p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1340 			DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1341 	else
1342 		p1 = 1;
1343 
1344 
1345 	switch (p0) {
1346 	case DPLL_CFGCR1_PDIV_2:
1347 		p0 = 2;
1348 		break;
1349 	case DPLL_CFGCR1_PDIV_3:
1350 		p0 = 3;
1351 		break;
1352 	case DPLL_CFGCR1_PDIV_5:
1353 		p0 = 5;
1354 		break;
1355 	case DPLL_CFGCR1_PDIV_7:
1356 		p0 = 7;
1357 		break;
1358 	}
1359 
1360 	switch (p2) {
1361 	case DPLL_CFGCR1_KDIV_1:
1362 		p2 = 1;
1363 		break;
1364 	case DPLL_CFGCR1_KDIV_2:
1365 		p2 = 2;
1366 		break;
1367 	case DPLL_CFGCR1_KDIV_3:
1368 		p2 = 3;
1369 		break;
1370 	}
1371 
1372 	ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
1373 
1374 	dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK)
1375 		* ref_clock;
1376 
1377 	dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1378 		      DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
1379 
1380 	if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1381 		return 0;
1382 
1383 	return dco_freq / (p0 * p1 * p2 * 5);
1384 }
1385 
1386 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1387 				 enum port port)
1388 {
1389 	u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1390 
1391 	switch (val) {
1392 	case DDI_CLK_SEL_NONE:
1393 		return 0;
1394 	case DDI_CLK_SEL_TBT_162:
1395 		return 162000;
1396 	case DDI_CLK_SEL_TBT_270:
1397 		return 270000;
1398 	case DDI_CLK_SEL_TBT_540:
1399 		return 540000;
1400 	case DDI_CLK_SEL_TBT_810:
1401 		return 810000;
1402 	default:
1403 		MISSING_CASE(val);
1404 		return 0;
1405 	}
1406 }
1407 
1408 static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
1409 				const struct intel_dpll_hw_state *pll_state)
1410 {
1411 	u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
1412 	u64 tmp;
1413 
1414 	ref_clock = dev_priv->cdclk.hw.ref;
1415 
1416 	m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK;
1417 	m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
1418 	m2_frac = (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ?
1419 		(pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >>
1420 		MG_PLL_DIV0_FBDIV_FRAC_SHIFT : 0;
1421 
1422 	switch (pll_state->mg_clktop2_hsclkctl &
1423 		MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
1424 	case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
1425 		div1 = 2;
1426 		break;
1427 	case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
1428 		div1 = 3;
1429 		break;
1430 	case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
1431 		div1 = 5;
1432 		break;
1433 	case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
1434 		div1 = 7;
1435 		break;
1436 	default:
1437 		MISSING_CASE(pll_state->mg_clktop2_hsclkctl);
1438 		return 0;
1439 	}
1440 
1441 	div2 = (pll_state->mg_clktop2_hsclkctl &
1442 		MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
1443 		MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
1444 
1445 	/* div2 value of 0 is same as 1 means no div */
1446 	if (div2 == 0)
1447 		div2 = 1;
1448 
1449 	/*
1450 	 * Adjust the original formula to delay the division by 2^22 in order to
1451 	 * minimize possible rounding errors.
1452 	 */
1453 	tmp = (u64)m1 * m2_int * ref_clock +
1454 	      (((u64)m1 * m2_frac * ref_clock) >> 22);
1455 	tmp = div_u64(tmp, 5 * div1 * div2);
1456 
1457 	return tmp;
1458 }
1459 
1460 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1461 {
1462 	int dotclock;
1463 
1464 	if (pipe_config->has_pch_encoder)
1465 		dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1466 						    &pipe_config->fdi_m_n);
1467 	else if (intel_crtc_has_dp_encoder(pipe_config))
1468 		dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1469 						    &pipe_config->dp_m_n);
1470 	else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
1471 		dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;
1472 	else
1473 		dotclock = pipe_config->port_clock;
1474 
1475 	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
1476 	    !intel_crtc_has_dp_encoder(pipe_config))
1477 		dotclock *= 2;
1478 
1479 	if (pipe_config->pixel_multiplier)
1480 		dotclock /= pipe_config->pixel_multiplier;
1481 
1482 	pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1483 }
1484 
1485 static void icl_ddi_clock_get(struct intel_encoder *encoder,
1486 			      struct intel_crtc_state *pipe_config)
1487 {
1488 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1489 	struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1490 	enum port port = encoder->port;
1491 	enum phy phy = intel_port_to_phy(dev_priv, port);
1492 	int link_clock;
1493 
1494 	if (intel_phy_is_combo(dev_priv, phy)) {
1495 		link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
1496 	} else {
1497 		enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv,
1498 						pipe_config->shared_dpll);
1499 
1500 		if (pll_id == DPLL_ID_ICL_TBTPLL)
1501 			link_clock = icl_calc_tbt_pll_link(dev_priv, port);
1502 		else
1503 			link_clock = icl_calc_mg_pll_link(dev_priv, pll_state);
1504 	}
1505 
1506 	pipe_config->port_clock = link_clock;
1507 
1508 	ddi_dotclock_get(pipe_config);
1509 }
1510 
1511 static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1512 			      struct intel_crtc_state *pipe_config)
1513 {
1514 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1515 	struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1516 	int link_clock;
1517 
1518 	if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1519 		link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
1520 	} else {
1521 		link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1522 
1523 		switch (link_clock) {
1524 		case DPLL_CFGCR0_LINK_RATE_810:
1525 			link_clock = 81000;
1526 			break;
1527 		case DPLL_CFGCR0_LINK_RATE_1080:
1528 			link_clock = 108000;
1529 			break;
1530 		case DPLL_CFGCR0_LINK_RATE_1350:
1531 			link_clock = 135000;
1532 			break;
1533 		case DPLL_CFGCR0_LINK_RATE_1620:
1534 			link_clock = 162000;
1535 			break;
1536 		case DPLL_CFGCR0_LINK_RATE_2160:
1537 			link_clock = 216000;
1538 			break;
1539 		case DPLL_CFGCR0_LINK_RATE_2700:
1540 			link_clock = 270000;
1541 			break;
1542 		case DPLL_CFGCR0_LINK_RATE_3240:
1543 			link_clock = 324000;
1544 			break;
1545 		case DPLL_CFGCR0_LINK_RATE_4050:
1546 			link_clock = 405000;
1547 			break;
1548 		default:
1549 			WARN(1, "Unsupported link rate\n");
1550 			break;
1551 		}
1552 		link_clock *= 2;
1553 	}
1554 
1555 	pipe_config->port_clock = link_clock;
1556 
1557 	ddi_dotclock_get(pipe_config);
1558 }
1559 
1560 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1561 			      struct intel_crtc_state *pipe_config)
1562 {
1563 	struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1564 	int link_clock;
1565 
1566 	/*
1567 	 * ctrl1 register is already shifted for each pll, just use 0 to get
1568 	 * the internal shift for each field
1569 	 */
1570 	if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) {
1571 		link_clock = skl_calc_wrpll_link(pll_state);
1572 	} else {
1573 		link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0);
1574 		link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(0);
1575 
1576 		switch (link_clock) {
1577 		case DPLL_CTRL1_LINK_RATE_810:
1578 			link_clock = 81000;
1579 			break;
1580 		case DPLL_CTRL1_LINK_RATE_1080:
1581 			link_clock = 108000;
1582 			break;
1583 		case DPLL_CTRL1_LINK_RATE_1350:
1584 			link_clock = 135000;
1585 			break;
1586 		case DPLL_CTRL1_LINK_RATE_1620:
1587 			link_clock = 162000;
1588 			break;
1589 		case DPLL_CTRL1_LINK_RATE_2160:
1590 			link_clock = 216000;
1591 			break;
1592 		case DPLL_CTRL1_LINK_RATE_2700:
1593 			link_clock = 270000;
1594 			break;
1595 		default:
1596 			WARN(1, "Unsupported link rate\n");
1597 			break;
1598 		}
1599 		link_clock *= 2;
1600 	}
1601 
1602 	pipe_config->port_clock = link_clock;
1603 
1604 	ddi_dotclock_get(pipe_config);
1605 }
1606 
1607 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1608 			      struct intel_crtc_state *pipe_config)
1609 {
1610 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1611 	int link_clock = 0;
1612 	u32 val, pll;
1613 
1614 	val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1615 	switch (val & PORT_CLK_SEL_MASK) {
1616 	case PORT_CLK_SEL_LCPLL_810:
1617 		link_clock = 81000;
1618 		break;
1619 	case PORT_CLK_SEL_LCPLL_1350:
1620 		link_clock = 135000;
1621 		break;
1622 	case PORT_CLK_SEL_LCPLL_2700:
1623 		link_clock = 270000;
1624 		break;
1625 	case PORT_CLK_SEL_WRPLL1:
1626 		link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1627 		break;
1628 	case PORT_CLK_SEL_WRPLL2:
1629 		link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1630 		break;
1631 	case PORT_CLK_SEL_SPLL:
1632 		pll = I915_READ(SPLL_CTL) & SPLL_FREQ_MASK;
1633 		if (pll == SPLL_FREQ_810MHz)
1634 			link_clock = 81000;
1635 		else if (pll == SPLL_FREQ_1350MHz)
1636 			link_clock = 135000;
1637 		else if (pll == SPLL_FREQ_2700MHz)
1638 			link_clock = 270000;
1639 		else {
1640 			WARN(1, "bad spll freq\n");
1641 			return;
1642 		}
1643 		break;
1644 	default:
1645 		WARN(1, "bad port clock sel\n");
1646 		return;
1647 	}
1648 
1649 	pipe_config->port_clock = link_clock * 2;
1650 
1651 	ddi_dotclock_get(pipe_config);
1652 }
1653 
1654 static int bxt_calc_pll_link(const struct intel_dpll_hw_state *pll_state)
1655 {
1656 	struct dpll clock;
1657 
1658 	clock.m1 = 2;
1659 	clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22;
1660 	if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1661 		clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK;
1662 	clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1663 	clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1664 	clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1665 
1666 	return chv_calc_dpll_params(100000, &clock);
1667 }
1668 
1669 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1670 			      struct intel_crtc_state *pipe_config)
1671 {
1672 	pipe_config->port_clock =
1673 		bxt_calc_pll_link(&pipe_config->dpll_hw_state);
1674 
1675 	ddi_dotclock_get(pipe_config);
1676 }
1677 
1678 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1679 				struct intel_crtc_state *pipe_config)
1680 {
1681 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1682 
1683 	if (INTEL_GEN(dev_priv) >= 11)
1684 		icl_ddi_clock_get(encoder, pipe_config);
1685 	else if (IS_CANNONLAKE(dev_priv))
1686 		cnl_ddi_clock_get(encoder, pipe_config);
1687 	else if (IS_GEN9_LP(dev_priv))
1688 		bxt_ddi_clock_get(encoder, pipe_config);
1689 	else if (IS_GEN9_BC(dev_priv))
1690 		skl_ddi_clock_get(encoder, pipe_config);
1691 	else if (INTEL_GEN(dev_priv) <= 8)
1692 		hsw_ddi_clock_get(encoder, pipe_config);
1693 }
1694 
1695 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
1696 {
1697 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1698 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1699 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1700 	u32 temp;
1701 
1702 	if (!intel_crtc_has_dp_encoder(crtc_state))
1703 		return;
1704 
1705 	WARN_ON(transcoder_is_dsi(cpu_transcoder));
1706 
1707 	temp = TRANS_MSA_SYNC_CLK;
1708 
1709 	if (crtc_state->limited_color_range)
1710 		temp |= TRANS_MSA_CEA_RANGE;
1711 
1712 	switch (crtc_state->pipe_bpp) {
1713 	case 18:
1714 		temp |= TRANS_MSA_6_BPC;
1715 		break;
1716 	case 24:
1717 		temp |= TRANS_MSA_8_BPC;
1718 		break;
1719 	case 30:
1720 		temp |= TRANS_MSA_10_BPC;
1721 		break;
1722 	case 36:
1723 		temp |= TRANS_MSA_12_BPC;
1724 		break;
1725 	default:
1726 		MISSING_CASE(crtc_state->pipe_bpp);
1727 		break;
1728 	}
1729 
1730 	/*
1731 	 * As per DP 1.2 spec section 2.3.4.3 while sending
1732 	 * YCBCR 444 signals we should program MSA MISC1/0 fields with
1733 	 * colorspace information. The output colorspace encoding is BT601.
1734 	 */
1735 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1736 		temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR;
1737 	/*
1738 	 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
1739 	 * of Color Encoding Format and Content Color Gamut] while sending
1740 	 * YCBCR 420 signals we should program MSA MISC1 fields which
1741 	 * indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
1742 	 */
1743 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1744 		temp |= TRANS_MSA_USE_VSC_SDP;
1745 	I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1746 }
1747 
1748 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1749 				    bool state)
1750 {
1751 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1752 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1753 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1754 	u32 temp;
1755 
1756 	temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1757 	if (state == true)
1758 		temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1759 	else
1760 		temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1761 	I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1762 }
1763 
1764 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1765 {
1766 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1767 	struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1768 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1769 	enum pipe pipe = crtc->pipe;
1770 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1771 	enum port port = encoder->port;
1772 	u32 temp;
1773 
1774 	/* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1775 	temp = TRANS_DDI_FUNC_ENABLE;
1776 	if (INTEL_GEN(dev_priv) >= 12)
1777 		temp |= TGL_TRANS_DDI_SELECT_PORT(port);
1778 	else
1779 		temp |= TRANS_DDI_SELECT_PORT(port);
1780 
1781 	switch (crtc_state->pipe_bpp) {
1782 	case 18:
1783 		temp |= TRANS_DDI_BPC_6;
1784 		break;
1785 	case 24:
1786 		temp |= TRANS_DDI_BPC_8;
1787 		break;
1788 	case 30:
1789 		temp |= TRANS_DDI_BPC_10;
1790 		break;
1791 	case 36:
1792 		temp |= TRANS_DDI_BPC_12;
1793 		break;
1794 	default:
1795 		BUG();
1796 	}
1797 
1798 	if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1799 		temp |= TRANS_DDI_PVSYNC;
1800 	if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1801 		temp |= TRANS_DDI_PHSYNC;
1802 
1803 	if (cpu_transcoder == TRANSCODER_EDP) {
1804 		switch (pipe) {
1805 		case PIPE_A:
1806 			/* On Haswell, can only use the always-on power well for
1807 			 * eDP when not using the panel fitter, and when not
1808 			 * using motion blur mitigation (which we don't
1809 			 * support). */
1810 			if (crtc_state->pch_pfit.force_thru)
1811 				temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1812 			else
1813 				temp |= TRANS_DDI_EDP_INPUT_A_ON;
1814 			break;
1815 		case PIPE_B:
1816 			temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1817 			break;
1818 		case PIPE_C:
1819 			temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1820 			break;
1821 		default:
1822 			BUG();
1823 			break;
1824 		}
1825 	}
1826 
1827 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1828 		if (crtc_state->has_hdmi_sink)
1829 			temp |= TRANS_DDI_MODE_SELECT_HDMI;
1830 		else
1831 			temp |= TRANS_DDI_MODE_SELECT_DVI;
1832 
1833 		if (crtc_state->hdmi_scrambling)
1834 			temp |= TRANS_DDI_HDMI_SCRAMBLING;
1835 		if (crtc_state->hdmi_high_tmds_clock_ratio)
1836 			temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1837 	} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1838 		temp |= TRANS_DDI_MODE_SELECT_FDI;
1839 		temp |= (crtc_state->fdi_lanes - 1) << 1;
1840 	} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1841 		temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1842 		temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1843 	} else {
1844 		temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1845 		temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1846 	}
1847 
1848 	I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1849 }
1850 
1851 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
1852 {
1853 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1854 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1855 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1856 	i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1857 	u32 val = I915_READ(reg);
1858 
1859 	if (INTEL_GEN(dev_priv) >= 12) {
1860 		val &= ~(TRANS_DDI_FUNC_ENABLE | TGL_TRANS_DDI_PORT_MASK |
1861 			 TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1862 	} else {
1863 		val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK |
1864 			 TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1865 	}
1866 	I915_WRITE(reg, val);
1867 
1868 	if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1869 	    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1870 		DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1871 		/* Quirk time at 100ms for reliable operation */
1872 		msleep(100);
1873 	}
1874 }
1875 
1876 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1877 				     bool enable)
1878 {
1879 	struct drm_device *dev = intel_encoder->base.dev;
1880 	struct drm_i915_private *dev_priv = to_i915(dev);
1881 	intel_wakeref_t wakeref;
1882 	enum pipe pipe = 0;
1883 	int ret = 0;
1884 	u32 tmp;
1885 
1886 	wakeref = intel_display_power_get_if_enabled(dev_priv,
1887 						     intel_encoder->power_domain);
1888 	if (WARN_ON(!wakeref))
1889 		return -ENXIO;
1890 
1891 	if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1892 		ret = -EIO;
1893 		goto out;
1894 	}
1895 
1896 	tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1897 	if (enable)
1898 		tmp |= TRANS_DDI_HDCP_SIGNALLING;
1899 	else
1900 		tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1901 	I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1902 out:
1903 	intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
1904 	return ret;
1905 }
1906 
1907 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1908 {
1909 	struct drm_device *dev = intel_connector->base.dev;
1910 	struct drm_i915_private *dev_priv = to_i915(dev);
1911 	struct intel_encoder *encoder = intel_connector->encoder;
1912 	int type = intel_connector->base.connector_type;
1913 	enum port port = encoder->port;
1914 	enum transcoder cpu_transcoder;
1915 	intel_wakeref_t wakeref;
1916 	enum pipe pipe = 0;
1917 	u32 tmp;
1918 	bool ret;
1919 
1920 	wakeref = intel_display_power_get_if_enabled(dev_priv,
1921 						     encoder->power_domain);
1922 	if (!wakeref)
1923 		return false;
1924 
1925 	if (!encoder->get_hw_state(encoder, &pipe)) {
1926 		ret = false;
1927 		goto out;
1928 	}
1929 
1930 	if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
1931 		cpu_transcoder = TRANSCODER_EDP;
1932 	else
1933 		cpu_transcoder = (enum transcoder) pipe;
1934 
1935 	tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1936 
1937 	switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1938 	case TRANS_DDI_MODE_SELECT_HDMI:
1939 	case TRANS_DDI_MODE_SELECT_DVI:
1940 		ret = type == DRM_MODE_CONNECTOR_HDMIA;
1941 		break;
1942 
1943 	case TRANS_DDI_MODE_SELECT_DP_SST:
1944 		ret = type == DRM_MODE_CONNECTOR_eDP ||
1945 		      type == DRM_MODE_CONNECTOR_DisplayPort;
1946 		break;
1947 
1948 	case TRANS_DDI_MODE_SELECT_DP_MST:
1949 		/* if the transcoder is in MST state then
1950 		 * connector isn't connected */
1951 		ret = false;
1952 		break;
1953 
1954 	case TRANS_DDI_MODE_SELECT_FDI:
1955 		ret = type == DRM_MODE_CONNECTOR_VGA;
1956 		break;
1957 
1958 	default:
1959 		ret = false;
1960 		break;
1961 	}
1962 
1963 out:
1964 	intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1965 
1966 	return ret;
1967 }
1968 
1969 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
1970 					u8 *pipe_mask, bool *is_dp_mst)
1971 {
1972 	struct drm_device *dev = encoder->base.dev;
1973 	struct drm_i915_private *dev_priv = to_i915(dev);
1974 	enum port port = encoder->port;
1975 	intel_wakeref_t wakeref;
1976 	enum pipe p;
1977 	u32 tmp;
1978 	u8 mst_pipe_mask;
1979 
1980 	*pipe_mask = 0;
1981 	*is_dp_mst = false;
1982 
1983 	wakeref = intel_display_power_get_if_enabled(dev_priv,
1984 						     encoder->power_domain);
1985 	if (!wakeref)
1986 		return;
1987 
1988 	tmp = I915_READ(DDI_BUF_CTL(port));
1989 	if (!(tmp & DDI_BUF_CTL_ENABLE))
1990 		goto out;
1991 
1992 	if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) {
1993 		tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1994 
1995 		switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1996 		default:
1997 			MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
1998 			/* fallthrough */
1999 		case TRANS_DDI_EDP_INPUT_A_ON:
2000 		case TRANS_DDI_EDP_INPUT_A_ONOFF:
2001 			*pipe_mask = BIT(PIPE_A);
2002 			break;
2003 		case TRANS_DDI_EDP_INPUT_B_ONOFF:
2004 			*pipe_mask = BIT(PIPE_B);
2005 			break;
2006 		case TRANS_DDI_EDP_INPUT_C_ONOFF:
2007 			*pipe_mask = BIT(PIPE_C);
2008 			break;
2009 		}
2010 
2011 		goto out;
2012 	}
2013 
2014 	mst_pipe_mask = 0;
2015 	for_each_pipe(dev_priv, p) {
2016 		enum transcoder cpu_transcoder = (enum transcoder)p;
2017 		unsigned int port_mask, ddi_select;
2018 		intel_wakeref_t trans_wakeref;
2019 
2020 		trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
2021 								   POWER_DOMAIN_TRANSCODER(cpu_transcoder));
2022 		if (!trans_wakeref)
2023 			continue;
2024 
2025 		if (INTEL_GEN(dev_priv) >= 12) {
2026 			port_mask = TGL_TRANS_DDI_PORT_MASK;
2027 			ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
2028 		} else {
2029 			port_mask = TRANS_DDI_PORT_MASK;
2030 			ddi_select = TRANS_DDI_SELECT_PORT(port);
2031 		}
2032 
2033 		tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2034 		intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
2035 					trans_wakeref);
2036 
2037 		if ((tmp & port_mask) != ddi_select)
2038 			continue;
2039 
2040 		if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
2041 		    TRANS_DDI_MODE_SELECT_DP_MST)
2042 			mst_pipe_mask |= BIT(p);
2043 
2044 		*pipe_mask |= BIT(p);
2045 	}
2046 
2047 	if (!*pipe_mask)
2048 		DRM_DEBUG_KMS("No pipe for ddi port %c found\n",
2049 			      port_name(port));
2050 
2051 	if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
2052 		DRM_DEBUG_KMS("Multiple pipes for non DP-MST port %c (pipe_mask %02x)\n",
2053 			      port_name(port), *pipe_mask);
2054 		*pipe_mask = BIT(ffs(*pipe_mask) - 1);
2055 	}
2056 
2057 	if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
2058 		DRM_DEBUG_KMS("Conflicting MST and non-MST encoders for port %c (pipe_mask %02x mst_pipe_mask %02x)\n",
2059 			      port_name(port), *pipe_mask, mst_pipe_mask);
2060 	else
2061 		*is_dp_mst = mst_pipe_mask;
2062 
2063 out:
2064 	if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
2065 		tmp = I915_READ(BXT_PHY_CTL(port));
2066 		if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2067 			    BXT_PHY_LANE_POWERDOWN_ACK |
2068 			    BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
2069 			DRM_ERROR("Port %c enabled but PHY powered down? "
2070 				  "(PHY_CTL %08x)\n", port_name(port), tmp);
2071 	}
2072 
2073 	intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
2074 }
2075 
2076 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2077 			    enum pipe *pipe)
2078 {
2079 	u8 pipe_mask;
2080 	bool is_mst;
2081 
2082 	intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2083 
2084 	if (is_mst || !pipe_mask)
2085 		return false;
2086 
2087 	*pipe = ffs(pipe_mask) - 1;
2088 
2089 	return true;
2090 }
2091 
2092 static inline enum intel_display_power_domain
2093 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
2094 {
2095 	/* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
2096 	 * DC states enabled at the same time, while for driver initiated AUX
2097 	 * transfers we need the same AUX IOs to be powered but with DC states
2098 	 * disabled. Accordingly use the AUX power domain here which leaves DC
2099 	 * states enabled.
2100 	 * However, for non-A AUX ports the corresponding non-EDP transcoders
2101 	 * would have already enabled power well 2 and DC_OFF. This means we can
2102 	 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2103 	 * specific AUX_IO reference without powering up any extra wells.
2104 	 * Note that PSR is enabled only on Port A even though this function
2105 	 * returns the correct domain for other ports too.
2106 	 */
2107 	return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
2108 					      intel_aux_power_domain(dig_port);
2109 }
2110 
2111 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
2112 					struct intel_crtc_state *crtc_state)
2113 {
2114 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2115 	struct intel_digital_port *dig_port;
2116 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2117 
2118 	/*
2119 	 * TODO: Add support for MST encoders. Atm, the following should never
2120 	 * happen since fake-MST encoders don't set their get_power_domains()
2121 	 * hook.
2122 	 */
2123 	if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
2124 		return;
2125 
2126 	dig_port = enc_to_dig_port(&encoder->base);
2127 	intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2128 
2129 	/*
2130 	 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
2131 	 * ports.
2132 	 */
2133 	if (intel_crtc_has_dp_encoder(crtc_state) ||
2134 	    intel_phy_is_tc(dev_priv, phy))
2135 		intel_display_power_get(dev_priv,
2136 					intel_ddi_main_link_aux_domain(dig_port));
2137 
2138 	/*
2139 	 * VDSC power is needed when DSC is enabled
2140 	 */
2141 	if (crtc_state->dsc_params.compression_enable)
2142 		intel_display_power_get(dev_priv,
2143 					intel_dsc_power_domain(crtc_state));
2144 }
2145 
2146 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
2147 {
2148 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2149 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2150 	struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
2151 	enum port port = encoder->port;
2152 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2153 
2154 	if (cpu_transcoder != TRANSCODER_EDP) {
2155 		if (INTEL_GEN(dev_priv) >= 12)
2156 			I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2157 				   TGL_TRANS_CLK_SEL_PORT(port));
2158 		else
2159 			I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2160 				   TRANS_CLK_SEL_PORT(port));
2161 	}
2162 }
2163 
2164 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
2165 {
2166 	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2167 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2168 
2169 	if (cpu_transcoder != TRANSCODER_EDP) {
2170 		if (INTEL_GEN(dev_priv) >= 12)
2171 			I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2172 				   TGL_TRANS_CLK_SEL_DISABLED);
2173 		else
2174 			I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2175 				   TRANS_CLK_SEL_DISABLED);
2176 	}
2177 }
2178 
2179 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2180 				enum port port, u8 iboost)
2181 {
2182 	u32 tmp;
2183 
2184 	tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
2185 	tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2186 	if (iboost)
2187 		tmp |= iboost << BALANCE_LEG_SHIFT(port);
2188 	else
2189 		tmp |= BALANCE_LEG_DISABLE(port);
2190 	I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
2191 }
2192 
2193 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2194 			       int level, enum intel_output_type type)
2195 {
2196 	struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2197 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2198 	enum port port = encoder->port;
2199 	u8 iboost;
2200 
2201 	if (type == INTEL_OUTPUT_HDMI)
2202 		iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2203 	else
2204 		iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2205 
2206 	if (iboost == 0) {
2207 		const struct ddi_buf_trans *ddi_translations;
2208 		int n_entries;
2209 
2210 		if (type == INTEL_OUTPUT_HDMI)
2211 			ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2212 		else if (type == INTEL_OUTPUT_EDP)
2213 			ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2214 		else
2215 			ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2216 
2217 		if (WARN_ON_ONCE(!ddi_translations))
2218 			return;
2219 		if (WARN_ON_ONCE(level >= n_entries))
2220 			level = n_entries - 1;
2221 
2222 		iboost = ddi_translations[level].i_boost;
2223 	}
2224 
2225 	/* Make sure that the requested I_boost is valid */
2226 	if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2227 		DRM_ERROR("Invalid I_boost value %u\n", iboost);
2228 		return;
2229 	}
2230 
2231 	_skl_ddi_set_iboost(dev_priv, port, iboost);
2232 
2233 	if (port == PORT_A && intel_dig_port->max_lanes == 4)
2234 		_skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
2235 }
2236 
2237 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2238 				    int level, enum intel_output_type type)
2239 {
2240 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2241 	const struct bxt_ddi_buf_trans *ddi_translations;
2242 	enum port port = encoder->port;
2243 	int n_entries;
2244 
2245 	if (type == INTEL_OUTPUT_HDMI)
2246 		ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2247 	else if (type == INTEL_OUTPUT_EDP)
2248 		ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2249 	else
2250 		ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
2251 
2252 	if (WARN_ON_ONCE(!ddi_translations))
2253 		return;
2254 	if (WARN_ON_ONCE(level >= n_entries))
2255 		level = n_entries - 1;
2256 
2257 	bxt_ddi_phy_set_signal_level(dev_priv, port,
2258 				     ddi_translations[level].margin,
2259 				     ddi_translations[level].scale,
2260 				     ddi_translations[level].enable,
2261 				     ddi_translations[level].deemphasis);
2262 }
2263 
2264 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2265 {
2266 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2267 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2268 	enum port port = encoder->port;
2269 	enum phy phy = intel_port_to_phy(dev_priv, port);
2270 	int n_entries;
2271 
2272 	if (INTEL_GEN(dev_priv) >= 11) {
2273 		if (intel_phy_is_combo(dev_priv, phy))
2274 			icl_get_combo_buf_trans(dev_priv, encoder->type,
2275 						intel_dp->link_rate, &n_entries);
2276 		else
2277 			n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2278 	} else if (IS_CANNONLAKE(dev_priv)) {
2279 		if (encoder->type == INTEL_OUTPUT_EDP)
2280 			cnl_get_buf_trans_edp(dev_priv, &n_entries);
2281 		else
2282 			cnl_get_buf_trans_dp(dev_priv, &n_entries);
2283 	} else if (IS_GEN9_LP(dev_priv)) {
2284 		if (encoder->type == INTEL_OUTPUT_EDP)
2285 			bxt_get_buf_trans_edp(dev_priv, &n_entries);
2286 		else
2287 			bxt_get_buf_trans_dp(dev_priv, &n_entries);
2288 	} else {
2289 		if (encoder->type == INTEL_OUTPUT_EDP)
2290 			intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2291 		else
2292 			intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2293 	}
2294 
2295 	if (WARN_ON(n_entries < 1))
2296 		n_entries = 1;
2297 	if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2298 		n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2299 
2300 	return index_to_dp_signal_levels[n_entries - 1] &
2301 		DP_TRAIN_VOLTAGE_SWING_MASK;
2302 }
2303 
2304 /*
2305  * We assume that the full set of pre-emphasis values can be
2306  * used on all DDI platforms. Should that change we need to
2307  * rethink this code.
2308  */
2309 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2310 {
2311 	switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2312 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2313 		return DP_TRAIN_PRE_EMPH_LEVEL_3;
2314 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2315 		return DP_TRAIN_PRE_EMPH_LEVEL_2;
2316 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2317 		return DP_TRAIN_PRE_EMPH_LEVEL_1;
2318 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2319 	default:
2320 		return DP_TRAIN_PRE_EMPH_LEVEL_0;
2321 	}
2322 }
2323 
2324 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2325 				   int level, enum intel_output_type type)
2326 {
2327 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2328 	const struct cnl_ddi_buf_trans *ddi_translations;
2329 	enum port port = encoder->port;
2330 	int n_entries, ln;
2331 	u32 val;
2332 
2333 	if (type == INTEL_OUTPUT_HDMI)
2334 		ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
2335 	else if (type == INTEL_OUTPUT_EDP)
2336 		ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
2337 	else
2338 		ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
2339 
2340 	if (WARN_ON_ONCE(!ddi_translations))
2341 		return;
2342 	if (WARN_ON_ONCE(level >= n_entries))
2343 		level = n_entries - 1;
2344 
2345 	/* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2346 	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2347 	val &= ~SCALING_MODE_SEL_MASK;
2348 	val |= SCALING_MODE_SEL(2);
2349 	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2350 
2351 	/* Program PORT_TX_DW2 */
2352 	val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
2353 	val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2354 		 RCOMP_SCALAR_MASK);
2355 	val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2356 	val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2357 	/* Rcomp scalar is fixed as 0x98 for every table entry */
2358 	val |= RCOMP_SCALAR(0x98);
2359 	I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
2360 
2361 	/* Program PORT_TX_DW4 */
2362 	/* We cannot write to GRP. It would overrite individual loadgen */
2363 	for (ln = 0; ln < 4; ln++) {
2364 		val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
2365 		val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2366 			 CURSOR_COEFF_MASK);
2367 		val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2368 		val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2369 		val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2370 		I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
2371 	}
2372 
2373 	/* Program PORT_TX_DW5 */
2374 	/* All DW5 values are fixed for every table entry */
2375 	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2376 	val &= ~RTERM_SELECT_MASK;
2377 	val |= RTERM_SELECT(6);
2378 	val |= TAP3_DISABLE;
2379 	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2380 
2381 	/* Program PORT_TX_DW7 */
2382 	val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
2383 	val &= ~N_SCALAR_MASK;
2384 	val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2385 	I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2386 }
2387 
2388 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2389 				    int level, enum intel_output_type type)
2390 {
2391 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2392 	enum port port = encoder->port;
2393 	int width, rate, ln;
2394 	u32 val;
2395 
2396 	if (type == INTEL_OUTPUT_HDMI) {
2397 		width = 4;
2398 		rate = 0; /* Rate is always < than 6GHz for HDMI */
2399 	} else {
2400 		struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2401 
2402 		width = intel_dp->lane_count;
2403 		rate = intel_dp->link_rate;
2404 	}
2405 
2406 	/*
2407 	 * 1. If port type is eDP or DP,
2408 	 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2409 	 * else clear to 0b.
2410 	 */
2411 	val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
2412 	if (type != INTEL_OUTPUT_HDMI)
2413 		val |= COMMON_KEEPER_EN;
2414 	else
2415 		val &= ~COMMON_KEEPER_EN;
2416 	I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2417 
2418 	/* 2. Program loadgen select */
2419 	/*
2420 	 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2421 	 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2422 	 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2423 	 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2424 	 */
2425 	for (ln = 0; ln <= 3; ln++) {
2426 		val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
2427 		val &= ~LOADGEN_SELECT;
2428 
2429 		if ((rate <= 600000 && width == 4 && ln >= 1)  ||
2430 		    (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2431 			val |= LOADGEN_SELECT;
2432 		}
2433 		I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
2434 	}
2435 
2436 	/* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2437 	val = I915_READ(CNL_PORT_CL1CM_DW5);
2438 	val |= SUS_CLOCK_CONFIG;
2439 	I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2440 
2441 	/* 4. Clear training enable to change swing values */
2442 	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2443 	val &= ~TX_TRAINING_EN;
2444 	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2445 
2446 	/* 5. Program swing and de-emphasis */
2447 	cnl_ddi_vswing_program(encoder, level, type);
2448 
2449 	/* 6. Set training enable to trigger update */
2450 	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2451 	val |= TX_TRAINING_EN;
2452 	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2453 }
2454 
2455 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2456 					u32 level, enum phy phy, int type,
2457 					int rate)
2458 {
2459 	const struct cnl_ddi_buf_trans *ddi_translations = NULL;
2460 	u32 n_entries, val;
2461 	int ln;
2462 
2463 	ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate,
2464 						   &n_entries);
2465 	if (!ddi_translations)
2466 		return;
2467 
2468 	if (level >= n_entries) {
2469 		DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2470 		level = n_entries - 1;
2471 	}
2472 
2473 	/* Set PORT_TX_DW5 */
2474 	val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
2475 	val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
2476 		  TAP2_DISABLE | TAP3_DISABLE);
2477 	val |= SCALING_MODE_SEL(0x2);
2478 	val |= RTERM_SELECT(0x6);
2479 	val |= TAP3_DISABLE;
2480 	I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
2481 
2482 	/* Program PORT_TX_DW2 */
2483 	val = I915_READ(ICL_PORT_TX_DW2_LN0(phy));
2484 	val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2485 		 RCOMP_SCALAR_MASK);
2486 	val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2487 	val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2488 	/* Program Rcomp scalar for every table entry */
2489 	val |= RCOMP_SCALAR(0x98);
2490 	I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), val);
2491 
2492 	/* Program PORT_TX_DW4 */
2493 	/* We cannot write to GRP. It would overwrite individual loadgen. */
2494 	for (ln = 0; ln <= 3; ln++) {
2495 		val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy));
2496 		val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2497 			 CURSOR_COEFF_MASK);
2498 		val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2499 		val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2500 		val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2501 		I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val);
2502 	}
2503 
2504 	/* Program PORT_TX_DW7 */
2505 	val = I915_READ(ICL_PORT_TX_DW7_LN0(phy));
2506 	val &= ~N_SCALAR_MASK;
2507 	val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2508 	I915_WRITE(ICL_PORT_TX_DW7_GRP(phy), val);
2509 }
2510 
2511 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2512 					      u32 level,
2513 					      enum intel_output_type type)
2514 {
2515 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2516 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2517 	int width = 0;
2518 	int rate = 0;
2519 	u32 val;
2520 	int ln = 0;
2521 
2522 	if (type == INTEL_OUTPUT_HDMI) {
2523 		width = 4;
2524 		/* Rate is always < than 6GHz for HDMI */
2525 	} else {
2526 		struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2527 
2528 		width = intel_dp->lane_count;
2529 		rate = intel_dp->link_rate;
2530 	}
2531 
2532 	/*
2533 	 * 1. If port type is eDP or DP,
2534 	 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2535 	 * else clear to 0b.
2536 	 */
2537 	val = I915_READ(ICL_PORT_PCS_DW1_LN0(phy));
2538 	if (type == INTEL_OUTPUT_HDMI)
2539 		val &= ~COMMON_KEEPER_EN;
2540 	else
2541 		val |= COMMON_KEEPER_EN;
2542 	I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), val);
2543 
2544 	/* 2. Program loadgen select */
2545 	/*
2546 	 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2547 	 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2548 	 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2549 	 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2550 	 */
2551 	for (ln = 0; ln <= 3; ln++) {
2552 		val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy));
2553 		val &= ~LOADGEN_SELECT;
2554 
2555 		if ((rate <= 600000 && width == 4 && ln >= 1) ||
2556 		    (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2557 			val |= LOADGEN_SELECT;
2558 		}
2559 		I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val);
2560 	}
2561 
2562 	/* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2563 	val = I915_READ(ICL_PORT_CL_DW5(phy));
2564 	val |= SUS_CLOCK_CONFIG;
2565 	I915_WRITE(ICL_PORT_CL_DW5(phy), val);
2566 
2567 	/* 4. Clear training enable to change swing values */
2568 	val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
2569 	val &= ~TX_TRAINING_EN;
2570 	I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
2571 
2572 	/* 5. Program swing and de-emphasis */
2573 	icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate);
2574 
2575 	/* 6. Set training enable to trigger update */
2576 	val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
2577 	val |= TX_TRAINING_EN;
2578 	I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
2579 }
2580 
2581 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2582 					   int link_clock,
2583 					   u32 level)
2584 {
2585 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2586 	enum port port = encoder->port;
2587 	const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2588 	u32 n_entries, val;
2589 	int ln;
2590 
2591 	n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2592 	ddi_translations = icl_mg_phy_ddi_translations;
2593 	/* The table does not have values for level 3 and level 9. */
2594 	if (level >= n_entries || level == 3 || level == 9) {
2595 		DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",
2596 			      level, n_entries - 2);
2597 		level = n_entries - 2;
2598 	}
2599 
2600 	/* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2601 	for (ln = 0; ln < 2; ln++) {
2602 		val = I915_READ(MG_TX1_LINK_PARAMS(ln, port));
2603 		val &= ~CRI_USE_FS32;
2604 		I915_WRITE(MG_TX1_LINK_PARAMS(ln, port), val);
2605 
2606 		val = I915_READ(MG_TX2_LINK_PARAMS(ln, port));
2607 		val &= ~CRI_USE_FS32;
2608 		I915_WRITE(MG_TX2_LINK_PARAMS(ln, port), val);
2609 	}
2610 
2611 	/* Program MG_TX_SWINGCTRL with values from vswing table */
2612 	for (ln = 0; ln < 2; ln++) {
2613 		val = I915_READ(MG_TX1_SWINGCTRL(ln, port));
2614 		val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2615 		val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2616 			ddi_translations[level].cri_txdeemph_override_17_12);
2617 		I915_WRITE(MG_TX1_SWINGCTRL(ln, port), val);
2618 
2619 		val = I915_READ(MG_TX2_SWINGCTRL(ln, port));
2620 		val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2621 		val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2622 			ddi_translations[level].cri_txdeemph_override_17_12);
2623 		I915_WRITE(MG_TX2_SWINGCTRL(ln, port), val);
2624 	}
2625 
2626 	/* Program MG_TX_DRVCTRL with values from vswing table */
2627 	for (ln = 0; ln < 2; ln++) {
2628 		val = I915_READ(MG_TX1_DRVCTRL(ln, port));
2629 		val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2630 			 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2631 		val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2632 			ddi_translations[level].cri_txdeemph_override_5_0) |
2633 			CRI_TXDEEMPH_OVERRIDE_11_6(
2634 				ddi_translations[level].cri_txdeemph_override_11_6) |
2635 			CRI_TXDEEMPH_OVERRIDE_EN;
2636 		I915_WRITE(MG_TX1_DRVCTRL(ln, port), val);
2637 
2638 		val = I915_READ(MG_TX2_DRVCTRL(ln, port));
2639 		val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2640 			 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2641 		val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2642 			ddi_translations[level].cri_txdeemph_override_5_0) |
2643 			CRI_TXDEEMPH_OVERRIDE_11_6(
2644 				ddi_translations[level].cri_txdeemph_override_11_6) |
2645 			CRI_TXDEEMPH_OVERRIDE_EN;
2646 		I915_WRITE(MG_TX2_DRVCTRL(ln, port), val);
2647 
2648 		/* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2649 	}
2650 
2651 	/*
2652 	 * Program MG_CLKHUB<LN, port being used> with value from frequency table
2653 	 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2654 	 * values from table for which TX1 and TX2 enabled.
2655 	 */
2656 	for (ln = 0; ln < 2; ln++) {
2657 		val = I915_READ(MG_CLKHUB(ln, port));
2658 		if (link_clock < 300000)
2659 			val |= CFG_LOW_RATE_LKREN_EN;
2660 		else
2661 			val &= ~CFG_LOW_RATE_LKREN_EN;
2662 		I915_WRITE(MG_CLKHUB(ln, port), val);
2663 	}
2664 
2665 	/* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2666 	for (ln = 0; ln < 2; ln++) {
2667 		val = I915_READ(MG_TX1_DCC(ln, port));
2668 		val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2669 		if (link_clock <= 500000) {
2670 			val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2671 		} else {
2672 			val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2673 				CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2674 		}
2675 		I915_WRITE(MG_TX1_DCC(ln, port), val);
2676 
2677 		val = I915_READ(MG_TX2_DCC(ln, port));
2678 		val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2679 		if (link_clock <= 500000) {
2680 			val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2681 		} else {
2682 			val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2683 				CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2684 		}
2685 		I915_WRITE(MG_TX2_DCC(ln, port), val);
2686 	}
2687 
2688 	/* Program MG_TX_PISO_READLOAD with values from vswing table */
2689 	for (ln = 0; ln < 2; ln++) {
2690 		val = I915_READ(MG_TX1_PISO_READLOAD(ln, port));
2691 		val |= CRI_CALCINIT;
2692 		I915_WRITE(MG_TX1_PISO_READLOAD(ln, port), val);
2693 
2694 		val = I915_READ(MG_TX2_PISO_READLOAD(ln, port));
2695 		val |= CRI_CALCINIT;
2696 		I915_WRITE(MG_TX2_PISO_READLOAD(ln, port), val);
2697 	}
2698 }
2699 
2700 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2701 				    int link_clock,
2702 				    u32 level,
2703 				    enum intel_output_type type)
2704 {
2705 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2706 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2707 
2708 	if (intel_phy_is_combo(dev_priv, phy))
2709 		icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2710 	else
2711 		icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
2712 }
2713 
2714 static u32 translate_signal_level(int signal_levels)
2715 {
2716 	int i;
2717 
2718 	for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2719 		if (index_to_dp_signal_levels[i] == signal_levels)
2720 			return i;
2721 	}
2722 
2723 	WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2724 	     signal_levels);
2725 
2726 	return 0;
2727 }
2728 
2729 static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
2730 {
2731 	u8 train_set = intel_dp->train_set[0];
2732 	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2733 					 DP_TRAIN_PRE_EMPHASIS_MASK);
2734 
2735 	return translate_signal_level(signal_levels);
2736 }
2737 
2738 u32 bxt_signal_levels(struct intel_dp *intel_dp)
2739 {
2740 	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2741 	struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2742 	struct intel_encoder *encoder = &dport->base;
2743 	int level = intel_ddi_dp_level(intel_dp);
2744 
2745 	if (INTEL_GEN(dev_priv) >= 11)
2746 		icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2747 					level, encoder->type);
2748 	else if (IS_CANNONLAKE(dev_priv))
2749 		cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2750 	else
2751 		bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2752 
2753 	return 0;
2754 }
2755 
2756 u32 ddi_signal_levels(struct intel_dp *intel_dp)
2757 {
2758 	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2759 	struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2760 	struct intel_encoder *encoder = &dport->base;
2761 	int level = intel_ddi_dp_level(intel_dp);
2762 
2763 	if (IS_GEN9_BC(dev_priv))
2764 		skl_ddi_set_iboost(encoder, level, encoder->type);
2765 
2766 	return DDI_BUF_TRANS_SELECT(level);
2767 }
2768 
2769 static inline
2770 u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2771 			      enum phy phy)
2772 {
2773 	if (intel_phy_is_combo(dev_priv, phy)) {
2774 		return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
2775 	} else if (intel_phy_is_tc(dev_priv, phy)) {
2776 		enum tc_port tc_port = intel_port_to_tc(dev_priv,
2777 							(enum port)phy);
2778 
2779 		return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2780 	}
2781 
2782 	return 0;
2783 }
2784 
2785 static void icl_map_plls_to_ports(struct intel_encoder *encoder,
2786 				  const struct intel_crtc_state *crtc_state)
2787 {
2788 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2789 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2790 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2791 	u32 val;
2792 
2793 	mutex_lock(&dev_priv->dpll_lock);
2794 
2795 	val = I915_READ(ICL_DPCLKA_CFGCR0);
2796 	WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
2797 
2798 	if (intel_phy_is_combo(dev_priv, phy)) {
2799 		/*
2800 		 * Even though this register references DDIs, note that we
2801 		 * want to pass the PHY rather than the port (DDI).  For
2802 		 * ICL, port=phy in all cases so it doesn't matter, but for
2803 		 * EHL the bspec notes the following:
2804 		 *
2805 		 *   "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
2806 		 *   Clock Select chooses the PLL for both DDIA and DDID and
2807 		 *   drives port A in all cases."
2808 		 */
2809 		val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
2810 		val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
2811 		I915_WRITE(ICL_DPCLKA_CFGCR0, val);
2812 		POSTING_READ(ICL_DPCLKA_CFGCR0);
2813 	}
2814 
2815 	val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2816 	I915_WRITE(ICL_DPCLKA_CFGCR0, val);
2817 
2818 	mutex_unlock(&dev_priv->dpll_lock);
2819 }
2820 
2821 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
2822 {
2823 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2824 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2825 	u32 val;
2826 
2827 	mutex_lock(&dev_priv->dpll_lock);
2828 
2829 	val = I915_READ(ICL_DPCLKA_CFGCR0);
2830 	val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2831 	I915_WRITE(ICL_DPCLKA_CFGCR0, val);
2832 
2833 	mutex_unlock(&dev_priv->dpll_lock);
2834 }
2835 
2836 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2837 {
2838 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2839 	u32 val;
2840 	enum port port;
2841 	u32 port_mask;
2842 	bool ddi_clk_needed;
2843 
2844 	/*
2845 	 * In case of DP MST, we sanitize the primary encoder only, not the
2846 	 * virtual ones.
2847 	 */
2848 	if (encoder->type == INTEL_OUTPUT_DP_MST)
2849 		return;
2850 
2851 	if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2852 		u8 pipe_mask;
2853 		bool is_mst;
2854 
2855 		intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2856 		/*
2857 		 * In the unlikely case that BIOS enables DP in MST mode, just
2858 		 * warn since our MST HW readout is incomplete.
2859 		 */
2860 		if (WARN_ON(is_mst))
2861 			return;
2862 	}
2863 
2864 	port_mask = BIT(encoder->port);
2865 	ddi_clk_needed = encoder->base.crtc;
2866 
2867 	if (encoder->type == INTEL_OUTPUT_DSI) {
2868 		struct intel_encoder *other_encoder;
2869 
2870 		port_mask = intel_dsi_encoder_ports(encoder);
2871 		/*
2872 		 * Sanity check that we haven't incorrectly registered another
2873 		 * encoder using any of the ports of this DSI encoder.
2874 		 */
2875 		for_each_intel_encoder(&dev_priv->drm, other_encoder) {
2876 			if (other_encoder == encoder)
2877 				continue;
2878 
2879 			if (WARN_ON(port_mask & BIT(other_encoder->port)))
2880 				return;
2881 		}
2882 		/*
2883 		 * For DSI we keep the ddi clocks gated
2884 		 * except during enable/disable sequence.
2885 		 */
2886 		ddi_clk_needed = false;
2887 	}
2888 
2889 	val = I915_READ(ICL_DPCLKA_CFGCR0);
2890 	for_each_port_masked(port, port_mask) {
2891 		enum phy phy = intel_port_to_phy(dev_priv, port);
2892 
2893 		bool ddi_clk_ungated = !(val &
2894 					 icl_dpclka_cfgcr0_clk_off(dev_priv,
2895 								   phy));
2896 
2897 		if (ddi_clk_needed == ddi_clk_ungated)
2898 			continue;
2899 
2900 		/*
2901 		 * Punt on the case now where clock is gated, but it would
2902 		 * be needed by the port. Something else is really broken then.
2903 		 */
2904 		if (WARN_ON(ddi_clk_needed))
2905 			continue;
2906 
2907 		DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2908 			 phy_name(port));
2909 		val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2910 		I915_WRITE(ICL_DPCLKA_CFGCR0, val);
2911 	}
2912 }
2913 
2914 static void intel_ddi_clk_select(struct intel_encoder *encoder,
2915 				 const struct intel_crtc_state *crtc_state)
2916 {
2917 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2918 	enum port port = encoder->port;
2919 	enum phy phy = intel_port_to_phy(dev_priv, port);
2920 	u32 val;
2921 	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2922 
2923 	if (WARN_ON(!pll))
2924 		return;
2925 
2926 	mutex_lock(&dev_priv->dpll_lock);
2927 
2928 	if (INTEL_GEN(dev_priv) >= 11) {
2929 		if (!intel_phy_is_combo(dev_priv, phy))
2930 			I915_WRITE(DDI_CLK_SEL(port),
2931 				   icl_pll_to_ddi_clk_sel(encoder, crtc_state));
2932 		else if (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C)
2933 			/*
2934 			 * MG does not exist but the programming is required
2935 			 * to ungate DDIC and DDID
2936 			 */
2937 			I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_MG);
2938 	} else if (IS_CANNONLAKE(dev_priv)) {
2939 		/* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2940 		val = I915_READ(DPCLKA_CFGCR0);
2941 		val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2942 		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2943 		I915_WRITE(DPCLKA_CFGCR0, val);
2944 
2945 		/*
2946 		 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2947 		 * This step and the step before must be done with separate
2948 		 * register writes.
2949 		 */
2950 		val = I915_READ(DPCLKA_CFGCR0);
2951 		val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2952 		I915_WRITE(DPCLKA_CFGCR0, val);
2953 	} else if (IS_GEN9_BC(dev_priv)) {
2954 		/* DDI -> PLL mapping  */
2955 		val = I915_READ(DPLL_CTRL2);
2956 
2957 		val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2958 			 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2959 		val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
2960 			DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2961 
2962 		I915_WRITE(DPLL_CTRL2, val);
2963 
2964 	} else if (INTEL_GEN(dev_priv) < 9) {
2965 		I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
2966 	}
2967 
2968 	mutex_unlock(&dev_priv->dpll_lock);
2969 }
2970 
2971 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2972 {
2973 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2974 	enum port port = encoder->port;
2975 	enum phy phy = intel_port_to_phy(dev_priv, port);
2976 
2977 	if (INTEL_GEN(dev_priv) >= 11) {
2978 		if (!intel_phy_is_combo(dev_priv, phy) ||
2979 		    (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C))
2980 			I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
2981 	} else if (IS_CANNONLAKE(dev_priv)) {
2982 		I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2983 			   DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2984 	} else if (IS_GEN9_BC(dev_priv)) {
2985 		I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
2986 			   DPLL_CTRL2_DDI_CLK_OFF(port));
2987 	} else if (INTEL_GEN(dev_priv) < 9) {
2988 		I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2989 	}
2990 }
2991 
2992 static void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
2993 {
2994 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2995 	enum port port = dig_port->base.port;
2996 	enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2997 	u32 val;
2998 	int ln;
2999 
3000 	if (tc_port == PORT_TC_NONE)
3001 		return;
3002 
3003 	for (ln = 0; ln < 2; ln++) {
3004 		val = I915_READ(MG_DP_MODE(ln, port));
3005 		val |= MG_DP_MODE_CFG_TR2PWR_GATING |
3006 		       MG_DP_MODE_CFG_TRPWR_GATING |
3007 		       MG_DP_MODE_CFG_CLNPWR_GATING |
3008 		       MG_DP_MODE_CFG_DIGPWR_GATING |
3009 		       MG_DP_MODE_CFG_GAONPWR_GATING;
3010 		I915_WRITE(MG_DP_MODE(ln, port), val);
3011 	}
3012 
3013 	val = I915_READ(MG_MISC_SUS0(tc_port));
3014 	val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) |
3015 	       MG_MISC_SUS0_CFG_TR2PWR_GATING |
3016 	       MG_MISC_SUS0_CFG_CL2PWR_GATING |
3017 	       MG_MISC_SUS0_CFG_GAONPWR_GATING |
3018 	       MG_MISC_SUS0_CFG_TRPWR_GATING |
3019 	       MG_MISC_SUS0_CFG_CL1PWR_GATING |
3020 	       MG_MISC_SUS0_CFG_DGPWR_GATING;
3021 	I915_WRITE(MG_MISC_SUS0(tc_port), val);
3022 }
3023 
3024 static void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
3025 {
3026 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3027 	enum port port = dig_port->base.port;
3028 	enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
3029 	u32 val;
3030 	int ln;
3031 
3032 	if (tc_port == PORT_TC_NONE)
3033 		return;
3034 
3035 	for (ln = 0; ln < 2; ln++) {
3036 		val = I915_READ(MG_DP_MODE(ln, port));
3037 		val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
3038 			 MG_DP_MODE_CFG_TRPWR_GATING |
3039 			 MG_DP_MODE_CFG_CLNPWR_GATING |
3040 			 MG_DP_MODE_CFG_DIGPWR_GATING |
3041 			 MG_DP_MODE_CFG_GAONPWR_GATING);
3042 		I915_WRITE(MG_DP_MODE(ln, port), val);
3043 	}
3044 
3045 	val = I915_READ(MG_MISC_SUS0(tc_port));
3046 	val &= ~(MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK |
3047 		 MG_MISC_SUS0_CFG_TR2PWR_GATING |
3048 		 MG_MISC_SUS0_CFG_CL2PWR_GATING |
3049 		 MG_MISC_SUS0_CFG_GAONPWR_GATING |
3050 		 MG_MISC_SUS0_CFG_TRPWR_GATING |
3051 		 MG_MISC_SUS0_CFG_CL1PWR_GATING |
3052 		 MG_MISC_SUS0_CFG_DGPWR_GATING);
3053 	I915_WRITE(MG_MISC_SUS0(tc_port), val);
3054 }
3055 
3056 static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
3057 {
3058 	struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3059 	enum port port = intel_dig_port->base.port;
3060 	u32 ln0, ln1, lane_mask;
3061 
3062 	if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
3063 		return;
3064 
3065 	ln0 = I915_READ(MG_DP_MODE(0, port));
3066 	ln1 = I915_READ(MG_DP_MODE(1, port));
3067 
3068 	switch (intel_dig_port->tc_mode) {
3069 	case TC_PORT_DP_ALT:
3070 		ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3071 		ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3072 
3073 		lane_mask = intel_tc_port_get_lane_mask(intel_dig_port);
3074 
3075 		switch (lane_mask) {
3076 		case 0x1:
3077 		case 0x4:
3078 			break;
3079 		case 0x2:
3080 			ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3081 			break;
3082 		case 0x3:
3083 			ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3084 			       MG_DP_MODE_CFG_DP_X2_MODE;
3085 			break;
3086 		case 0x8:
3087 			ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3088 			break;
3089 		case 0xC:
3090 			ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3091 			       MG_DP_MODE_CFG_DP_X2_MODE;
3092 			break;
3093 		case 0xF:
3094 			ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3095 			       MG_DP_MODE_CFG_DP_X2_MODE;
3096 			ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3097 			       MG_DP_MODE_CFG_DP_X2_MODE;
3098 			break;
3099 		default:
3100 			MISSING_CASE(lane_mask);
3101 		}
3102 		break;
3103 
3104 	case TC_PORT_LEGACY:
3105 		ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3106 		ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3107 		break;
3108 
3109 	default:
3110 		MISSING_CASE(intel_dig_port->tc_mode);
3111 		return;
3112 	}
3113 
3114 	I915_WRITE(MG_DP_MODE(0, port), ln0);
3115 	I915_WRITE(MG_DP_MODE(1, port), ln1);
3116 }
3117 
3118 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
3119 					const struct intel_crtc_state *crtc_state)
3120 {
3121 	if (!crtc_state->fec_enable)
3122 		return;
3123 
3124 	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
3125 		DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
3126 }
3127 
3128 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
3129 				 const struct intel_crtc_state *crtc_state)
3130 {
3131 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3132 	enum port port = encoder->port;
3133 	u32 val;
3134 
3135 	if (!crtc_state->fec_enable)
3136 		return;
3137 
3138 	val = I915_READ(DP_TP_CTL(port));
3139 	val |= DP_TP_CTL_FEC_ENABLE;
3140 	I915_WRITE(DP_TP_CTL(port), val);
3141 
3142 	if (intel_de_wait_for_set(dev_priv, DP_TP_STATUS(port),
3143 				  DP_TP_STATUS_FEC_ENABLE_LIVE, 1))
3144 		DRM_ERROR("Timed out waiting for FEC Enable Status\n");
3145 }
3146 
3147 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
3148 					const struct intel_crtc_state *crtc_state)
3149 {
3150 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3151 	enum port port = encoder->port;
3152 	u32 val;
3153 
3154 	if (!crtc_state->fec_enable)
3155 		return;
3156 
3157 	val = I915_READ(DP_TP_CTL(port));
3158 	val &= ~DP_TP_CTL_FEC_ENABLE;
3159 	I915_WRITE(DP_TP_CTL(port), val);
3160 	POSTING_READ(DP_TP_CTL(port));
3161 }
3162 
3163 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
3164 				    const struct intel_crtc_state *crtc_state,
3165 				    const struct drm_connector_state *conn_state)
3166 {
3167 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3168 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3169 	enum port port = encoder->port;
3170 	enum phy phy = intel_port_to_phy(dev_priv, port);
3171 	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3172 	bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3173 	int level = intel_ddi_dp_level(intel_dp);
3174 
3175 	WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
3176 
3177 	intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3178 				 crtc_state->lane_count, is_mst);
3179 
3180 	intel_edp_panel_on(intel_dp);
3181 
3182 	intel_ddi_clk_select(encoder, crtc_state);
3183 
3184 	if (!intel_phy_is_tc(dev_priv, phy) ||
3185 	    dig_port->tc_mode != TC_PORT_TBT_ALT)
3186 		intel_display_power_get(dev_priv,
3187 					dig_port->ddi_io_power_domain);
3188 
3189 	icl_program_mg_dp_mode(dig_port);
3190 	icl_disable_phy_clock_gating(dig_port);
3191 
3192 	if (INTEL_GEN(dev_priv) >= 11)
3193 		icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3194 					level, encoder->type);
3195 	else if (IS_CANNONLAKE(dev_priv))
3196 		cnl_ddi_vswing_sequence(encoder, level, encoder->type);
3197 	else if (IS_GEN9_LP(dev_priv))
3198 		bxt_ddi_vswing_sequence(encoder, level, encoder->type);
3199 	else
3200 		intel_prepare_dp_ddi_buffers(encoder, crtc_state);
3201 
3202 	if (intel_phy_is_combo(dev_priv, phy)) {
3203 		bool lane_reversal =
3204 			dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3205 
3206 		intel_combo_phy_power_up_lanes(dev_priv, phy, false,
3207 					       crtc_state->lane_count,
3208 					       lane_reversal);
3209 	}
3210 
3211 	intel_ddi_init_dp_buf_reg(encoder);
3212 	if (!is_mst)
3213 		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3214 	intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3215 					      true);
3216 	intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3217 	intel_dp_start_link_train(intel_dp);
3218 	if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
3219 		intel_dp_stop_link_train(intel_dp);
3220 
3221 	intel_ddi_enable_fec(encoder, crtc_state);
3222 
3223 	icl_enable_phy_clock_gating(dig_port);
3224 
3225 	if (!is_mst)
3226 		intel_ddi_enable_pipe_clock(crtc_state);
3227 
3228 	intel_dsc_enable(encoder, crtc_state);
3229 }
3230 
3231 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
3232 				      const struct intel_crtc_state *crtc_state,
3233 				      const struct drm_connector_state *conn_state)
3234 {
3235 	struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
3236 	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
3237 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3238 	enum port port = encoder->port;
3239 	int level = intel_ddi_hdmi_level(dev_priv, port);
3240 	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3241 
3242 	intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
3243 	intel_ddi_clk_select(encoder, crtc_state);
3244 
3245 	intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3246 
3247 	icl_program_mg_dp_mode(dig_port);
3248 	icl_disable_phy_clock_gating(dig_port);
3249 
3250 	if (INTEL_GEN(dev_priv) >= 11)
3251 		icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3252 					level, INTEL_OUTPUT_HDMI);
3253 	else if (IS_CANNONLAKE(dev_priv))
3254 		cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3255 	else if (IS_GEN9_LP(dev_priv))
3256 		bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3257 	else
3258 		intel_prepare_hdmi_ddi_buffers(encoder, level);
3259 
3260 	icl_enable_phy_clock_gating(dig_port);
3261 
3262 	if (IS_GEN9_BC(dev_priv))
3263 		skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
3264 
3265 	intel_ddi_enable_pipe_clock(crtc_state);
3266 
3267 	intel_dig_port->set_infoframes(encoder,
3268 				       crtc_state->has_infoframe,
3269 				       crtc_state, conn_state);
3270 }
3271 
3272 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
3273 				 const struct intel_crtc_state *crtc_state,
3274 				 const struct drm_connector_state *conn_state)
3275 {
3276 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3277 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3278 	enum pipe pipe = crtc->pipe;
3279 
3280 	/*
3281 	 * When called from DP MST code:
3282 	 * - conn_state will be NULL
3283 	 * - encoder will be the main encoder (ie. mst->primary)
3284 	 * - the main connector associated with this port
3285 	 *   won't be active or linked to a crtc
3286 	 * - crtc_state will be the state of the first stream to
3287 	 *   be activated on this port, and it may not be the same
3288 	 *   stream that will be deactivated last, but each stream
3289 	 *   should have a state that is identical when it comes to
3290 	 *   the DP link parameteres
3291 	 */
3292 
3293 	WARN_ON(crtc_state->has_pch_encoder);
3294 
3295 	if (INTEL_GEN(dev_priv) >= 11)
3296 		icl_map_plls_to_ports(encoder, crtc_state);
3297 
3298 	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3299 
3300 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3301 		intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
3302 	} else {
3303 		struct intel_lspcon *lspcon =
3304 				enc_to_intel_lspcon(&encoder->base);
3305 
3306 		intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3307 		if (lspcon->active) {
3308 			struct intel_digital_port *dig_port =
3309 					enc_to_dig_port(&encoder->base);
3310 
3311 			dig_port->set_infoframes(encoder,
3312 						 crtc_state->has_infoframe,
3313 						 crtc_state, conn_state);
3314 		}
3315 	}
3316 }
3317 
3318 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
3319 				  const struct intel_crtc_state *crtc_state)
3320 {
3321 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3322 	enum port port = encoder->port;
3323 	bool wait = false;
3324 	u32 val;
3325 
3326 	val = I915_READ(DDI_BUF_CTL(port));
3327 	if (val & DDI_BUF_CTL_ENABLE) {
3328 		val &= ~DDI_BUF_CTL_ENABLE;
3329 		I915_WRITE(DDI_BUF_CTL(port), val);
3330 		wait = true;
3331 	}
3332 
3333 	val = I915_READ(DP_TP_CTL(port));
3334 	val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3335 	val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3336 	I915_WRITE(DP_TP_CTL(port), val);
3337 
3338 	/* Disable FEC in DP Sink */
3339 	intel_ddi_disable_fec_state(encoder, crtc_state);
3340 
3341 	if (wait)
3342 		intel_wait_ddi_buf_idle(dev_priv, port);
3343 }
3344 
3345 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
3346 				      const struct intel_crtc_state *old_crtc_state,
3347 				      const struct drm_connector_state *old_conn_state)
3348 {
3349 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3350 	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3351 	struct intel_dp *intel_dp = &dig_port->dp;
3352 	bool is_mst = intel_crtc_has_type(old_crtc_state,
3353 					  INTEL_OUTPUT_DP_MST);
3354 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3355 
3356 	if (!is_mst) {
3357 		intel_ddi_disable_pipe_clock(old_crtc_state);
3358 		/*
3359 		 * Power down sink before disabling the port, otherwise we end
3360 		 * up getting interrupts from the sink on detecting link loss.
3361 		 */
3362 		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3363 	}
3364 
3365 	intel_disable_ddi_buf(encoder, old_crtc_state);
3366 
3367 	intel_edp_panel_vdd_on(intel_dp);
3368 	intel_edp_panel_off(intel_dp);
3369 
3370 	if (!intel_phy_is_tc(dev_priv, phy) ||
3371 	    dig_port->tc_mode != TC_PORT_TBT_ALT)
3372 		intel_display_power_put_unchecked(dev_priv,
3373 						  dig_port->ddi_io_power_domain);
3374 
3375 	intel_ddi_clk_disable(encoder);
3376 }
3377 
3378 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
3379 					const struct intel_crtc_state *old_crtc_state,
3380 					const struct drm_connector_state *old_conn_state)
3381 {
3382 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3383 	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3384 	struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3385 
3386 	dig_port->set_infoframes(encoder, false,
3387 				 old_crtc_state, old_conn_state);
3388 
3389 	intel_ddi_disable_pipe_clock(old_crtc_state);
3390 
3391 	intel_disable_ddi_buf(encoder, old_crtc_state);
3392 
3393 	intel_display_power_put_unchecked(dev_priv,
3394 					  dig_port->ddi_io_power_domain);
3395 
3396 	intel_ddi_clk_disable(encoder);
3397 
3398 	intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3399 }
3400 
3401 static void intel_ddi_post_disable(struct intel_encoder *encoder,
3402 				   const struct intel_crtc_state *old_crtc_state,
3403 				   const struct drm_connector_state *old_conn_state)
3404 {
3405 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3406 
3407 	/*
3408 	 * When called from DP MST code:
3409 	 * - old_conn_state will be NULL
3410 	 * - encoder will be the main encoder (ie. mst->primary)
3411 	 * - the main connector associated with this port
3412 	 *   won't be active or linked to a crtc
3413 	 * - old_crtc_state will be the state of the last stream to
3414 	 *   be deactivated on this port, and it may not be the same
3415 	 *   stream that was activated last, but each stream
3416 	 *   should have a state that is identical when it comes to
3417 	 *   the DP link parameteres
3418 	 */
3419 
3420 	if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3421 		intel_ddi_post_disable_hdmi(encoder,
3422 					    old_crtc_state, old_conn_state);
3423 	else
3424 		intel_ddi_post_disable_dp(encoder,
3425 					  old_crtc_state, old_conn_state);
3426 
3427 	if (INTEL_GEN(dev_priv) >= 11)
3428 		icl_unmap_plls_to_ports(encoder);
3429 }
3430 
3431 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
3432 				const struct intel_crtc_state *old_crtc_state,
3433 				const struct drm_connector_state *old_conn_state)
3434 {
3435 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3436 	u32 val;
3437 
3438 	/*
3439 	 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3440 	 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3441 	 * step 13 is the correct place for it. Step 18 is where it was
3442 	 * originally before the BUN.
3443 	 */
3444 	val = I915_READ(FDI_RX_CTL(PIPE_A));
3445 	val &= ~FDI_RX_ENABLE;
3446 	I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3447 
3448 	intel_disable_ddi_buf(encoder, old_crtc_state);
3449 	intel_ddi_clk_disable(encoder);
3450 
3451 	val = I915_READ(FDI_RX_MISC(PIPE_A));
3452 	val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3453 	val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3454 	I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3455 
3456 	val = I915_READ(FDI_RX_CTL(PIPE_A));
3457 	val &= ~FDI_PCDCLK;
3458 	I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3459 
3460 	val = I915_READ(FDI_RX_CTL(PIPE_A));
3461 	val &= ~FDI_RX_PLL_ENABLE;
3462 	I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3463 }
3464 
3465 static void intel_enable_ddi_dp(struct intel_encoder *encoder,
3466 				const struct intel_crtc_state *crtc_state,
3467 				const struct drm_connector_state *conn_state)
3468 {
3469 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3470 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3471 	enum port port = encoder->port;
3472 
3473 	if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3474 		intel_dp_stop_link_train(intel_dp);
3475 
3476 	intel_edp_backlight_on(crtc_state, conn_state);
3477 	intel_psr_enable(intel_dp, crtc_state);
3478 	intel_dp_ycbcr_420_enable(intel_dp, crtc_state);
3479 	intel_edp_drrs_enable(intel_dp, crtc_state);
3480 
3481 	if (crtc_state->has_audio)
3482 		intel_audio_codec_enable(encoder, crtc_state, conn_state);
3483 }
3484 
3485 static i915_reg_t
3486 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3487 			       enum port port)
3488 {
3489 	static const i915_reg_t regs[] = {
3490 		[PORT_A] = CHICKEN_TRANS_EDP,
3491 		[PORT_B] = CHICKEN_TRANS_A,
3492 		[PORT_C] = CHICKEN_TRANS_B,
3493 		[PORT_D] = CHICKEN_TRANS_C,
3494 		[PORT_E] = CHICKEN_TRANS_A,
3495 	};
3496 
3497 	WARN_ON(INTEL_GEN(dev_priv) < 9);
3498 
3499 	if (WARN_ON(port < PORT_A || port > PORT_E))
3500 		port = PORT_A;
3501 
3502 	return regs[port];
3503 }
3504 
3505 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
3506 				  const struct intel_crtc_state *crtc_state,
3507 				  const struct drm_connector_state *conn_state)
3508 {
3509 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3510 	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3511 	struct drm_connector *connector = conn_state->connector;
3512 	enum port port = encoder->port;
3513 
3514 	if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3515 					       crtc_state->hdmi_high_tmds_clock_ratio,
3516 					       crtc_state->hdmi_scrambling))
3517 		DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3518 			  connector->base.id, connector->name);
3519 
3520 	/* Display WA #1143: skl,kbl,cfl */
3521 	if (IS_GEN9_BC(dev_priv)) {
3522 		/*
3523 		 * For some reason these chicken bits have been
3524 		 * stuffed into a transcoder register, event though
3525 		 * the bits affect a specific DDI port rather than
3526 		 * a specific transcoder.
3527 		 */
3528 		i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
3529 		u32 val;
3530 
3531 		val = I915_READ(reg);
3532 
3533 		if (port == PORT_E)
3534 			val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3535 				DDIE_TRAINING_OVERRIDE_VALUE;
3536 		else
3537 			val |= DDI_TRAINING_OVERRIDE_ENABLE |
3538 				DDI_TRAINING_OVERRIDE_VALUE;
3539 
3540 		I915_WRITE(reg, val);
3541 		POSTING_READ(reg);
3542 
3543 		udelay(1);
3544 
3545 		if (port == PORT_E)
3546 			val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3547 				 DDIE_TRAINING_OVERRIDE_VALUE);
3548 		else
3549 			val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3550 				 DDI_TRAINING_OVERRIDE_VALUE);
3551 
3552 		I915_WRITE(reg, val);
3553 	}
3554 
3555 	/* In HDMI/DVI mode, the port width, and swing/emphasis values
3556 	 * are ignored so nothing special needs to be done besides
3557 	 * enabling the port.
3558 	 */
3559 	I915_WRITE(DDI_BUF_CTL(port),
3560 		   dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
3561 
3562 	if (crtc_state->has_audio)
3563 		intel_audio_codec_enable(encoder, crtc_state, conn_state);
3564 }
3565 
3566 static void intel_enable_ddi(struct intel_encoder *encoder,
3567 			     const struct intel_crtc_state *crtc_state,
3568 			     const struct drm_connector_state *conn_state)
3569 {
3570 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3571 		intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
3572 	else
3573 		intel_enable_ddi_dp(encoder, crtc_state, conn_state);
3574 
3575 	/* Enable hdcp if it's desired */
3576 	if (conn_state->content_protection ==
3577 	    DRM_MODE_CONTENT_PROTECTION_DESIRED)
3578 		intel_hdcp_enable(to_intel_connector(conn_state->connector),
3579 				  (u8)conn_state->hdcp_content_type);
3580 }
3581 
3582 static void intel_disable_ddi_dp(struct intel_encoder *encoder,
3583 				 const struct intel_crtc_state *old_crtc_state,
3584 				 const struct drm_connector_state *old_conn_state)
3585 {
3586 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3587 
3588 	intel_dp->link_trained = false;
3589 
3590 	if (old_crtc_state->has_audio)
3591 		intel_audio_codec_disable(encoder,
3592 					  old_crtc_state, old_conn_state);
3593 
3594 	intel_edp_drrs_disable(intel_dp, old_crtc_state);
3595 	intel_psr_disable(intel_dp, old_crtc_state);
3596 	intel_edp_backlight_off(old_conn_state);
3597 	/* Disable the decompression in DP Sink */
3598 	intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3599 					      false);
3600 }
3601 
3602 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
3603 				   const struct intel_crtc_state *old_crtc_state,
3604 				   const struct drm_connector_state *old_conn_state)
3605 {
3606 	struct drm_connector *connector = old_conn_state->connector;
3607 
3608 	if (old_crtc_state->has_audio)
3609 		intel_audio_codec_disable(encoder,
3610 					  old_crtc_state, old_conn_state);
3611 
3612 	if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3613 					       false, false))
3614 		DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3615 			      connector->base.id, connector->name);
3616 }
3617 
3618 static void intel_disable_ddi(struct intel_encoder *encoder,
3619 			      const struct intel_crtc_state *old_crtc_state,
3620 			      const struct drm_connector_state *old_conn_state)
3621 {
3622 	intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3623 
3624 	if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3625 		intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
3626 	else
3627 		intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
3628 }
3629 
3630 static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder,
3631 				     const struct intel_crtc_state *crtc_state,
3632 				     const struct drm_connector_state *conn_state)
3633 {
3634 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3635 
3636 	intel_ddi_set_pipe_settings(crtc_state);
3637 
3638 	intel_psr_update(intel_dp, crtc_state);
3639 	intel_edp_drrs_enable(intel_dp, crtc_state);
3640 
3641 	intel_panel_update_backlight(encoder, crtc_state, conn_state);
3642 }
3643 
3644 static void intel_ddi_update_pipe(struct intel_encoder *encoder,
3645 				  const struct intel_crtc_state *crtc_state,
3646 				  const struct drm_connector_state *conn_state)
3647 {
3648 	struct intel_connector *connector =
3649 				to_intel_connector(conn_state->connector);
3650 	struct intel_hdcp *hdcp = &connector->hdcp;
3651 	bool content_protection_type_changed =
3652 			(conn_state->hdcp_content_type != hdcp->content_type &&
3653 			 conn_state->content_protection !=
3654 			 DRM_MODE_CONTENT_PROTECTION_UNDESIRED);
3655 
3656 	if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3657 		intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
3658 
3659 	/*
3660 	 * During the HDCP encryption session if Type change is requested,
3661 	 * disable the HDCP and reenable it with new TYPE value.
3662 	 */
3663 	if (conn_state->content_protection ==
3664 	    DRM_MODE_CONTENT_PROTECTION_UNDESIRED ||
3665 	    content_protection_type_changed)
3666 		intel_hdcp_disable(connector);
3667 
3668 	/*
3669 	 * Mark the hdcp state as DESIRED after the hdcp disable of type
3670 	 * change procedure.
3671 	 */
3672 	if (content_protection_type_changed) {
3673 		mutex_lock(&hdcp->mutex);
3674 		hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
3675 		schedule_work(&hdcp->prop_work);
3676 		mutex_unlock(&hdcp->mutex);
3677 	}
3678 
3679 	if (conn_state->content_protection ==
3680 	    DRM_MODE_CONTENT_PROTECTION_DESIRED ||
3681 	    content_protection_type_changed)
3682 		intel_hdcp_enable(connector, (u8)conn_state->hdcp_content_type);
3683 }
3684 
3685 static void
3686 intel_ddi_update_prepare(struct intel_atomic_state *state,
3687 			 struct intel_encoder *encoder,
3688 			 struct intel_crtc *crtc)
3689 {
3690 	struct intel_crtc_state *crtc_state =
3691 		crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL;
3692 	int required_lanes = crtc_state ? crtc_state->lane_count : 1;
3693 
3694 	WARN_ON(crtc && crtc->active);
3695 
3696 	intel_tc_port_get_link(enc_to_dig_port(&encoder->base), required_lanes);
3697 	if (crtc_state && crtc_state->base.active)
3698 		intel_update_active_dpll(state, crtc, encoder);
3699 }
3700 
3701 static void
3702 intel_ddi_update_complete(struct intel_atomic_state *state,
3703 			  struct intel_encoder *encoder,
3704 			  struct intel_crtc *crtc)
3705 {
3706 	intel_tc_port_put_link(enc_to_dig_port(&encoder->base));
3707 }
3708 
3709 static void
3710 intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
3711 			 const struct intel_crtc_state *crtc_state,
3712 			 const struct drm_connector_state *conn_state)
3713 {
3714 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3715 	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3716 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3717 	bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
3718 
3719 	if (is_tc_port)
3720 		intel_tc_port_get_link(dig_port, crtc_state->lane_count);
3721 
3722 	if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
3723 		intel_display_power_get(dev_priv,
3724 					intel_ddi_main_link_aux_domain(dig_port));
3725 
3726 	if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT)
3727 		/*
3728 		 * Program the lane count for static/dynamic connections on
3729 		 * Type-C ports.  Skip this step for TBT.
3730 		 */
3731 		intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
3732 	else if (IS_GEN9_LP(dev_priv))
3733 		bxt_ddi_phy_set_lane_optim_mask(encoder,
3734 						crtc_state->lane_lat_optim_mask);
3735 }
3736 
3737 static void
3738 intel_ddi_post_pll_disable(struct intel_encoder *encoder,
3739 			   const struct intel_crtc_state *crtc_state,
3740 			   const struct drm_connector_state *conn_state)
3741 {
3742 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3743 	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3744 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3745 	bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
3746 
3747 	if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
3748 		intel_display_power_put_unchecked(dev_priv,
3749 						  intel_ddi_main_link_aux_domain(dig_port));
3750 
3751 	if (is_tc_port)
3752 		intel_tc_port_put_link(dig_port);
3753 }
3754 
3755 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
3756 {
3757 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3758 	struct drm_i915_private *dev_priv =
3759 		to_i915(intel_dig_port->base.base.dev);
3760 	enum port port = intel_dig_port->base.port;
3761 	u32 val;
3762 	bool wait = false;
3763 
3764 	if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
3765 		val = I915_READ(DDI_BUF_CTL(port));
3766 		if (val & DDI_BUF_CTL_ENABLE) {
3767 			val &= ~DDI_BUF_CTL_ENABLE;
3768 			I915_WRITE(DDI_BUF_CTL(port), val);
3769 			wait = true;
3770 		}
3771 
3772 		val = I915_READ(DP_TP_CTL(port));
3773 		val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3774 		val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3775 		I915_WRITE(DP_TP_CTL(port), val);
3776 		POSTING_READ(DP_TP_CTL(port));
3777 
3778 		if (wait)
3779 			intel_wait_ddi_buf_idle(dev_priv, port);
3780 	}
3781 
3782 	val = DP_TP_CTL_ENABLE |
3783 	      DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
3784 	if (intel_dp->link_mst)
3785 		val |= DP_TP_CTL_MODE_MST;
3786 	else {
3787 		val |= DP_TP_CTL_MODE_SST;
3788 		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3789 			val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3790 	}
3791 	I915_WRITE(DP_TP_CTL(port), val);
3792 	POSTING_READ(DP_TP_CTL(port));
3793 
3794 	intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3795 	I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3796 	POSTING_READ(DDI_BUF_CTL(port));
3797 
3798 	udelay(600);
3799 }
3800 
3801 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3802 				       enum transcoder cpu_transcoder)
3803 {
3804 	if (cpu_transcoder == TRANSCODER_EDP)
3805 		return false;
3806 
3807 	if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
3808 		return false;
3809 
3810 	return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
3811 		AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3812 }
3813 
3814 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3815 					 struct intel_crtc_state *crtc_state)
3816 {
3817 	if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
3818 		crtc_state->min_voltage_level = 1;
3819 	else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
3820 		crtc_state->min_voltage_level = 2;
3821 }
3822 
3823 void intel_ddi_get_config(struct intel_encoder *encoder,
3824 			  struct intel_crtc_state *pipe_config)
3825 {
3826 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3827 	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
3828 	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3829 	u32 temp, flags = 0;
3830 
3831 	/* XXX: DSI transcoder paranoia */
3832 	if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
3833 		return;
3834 
3835 	temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3836 	if (temp & TRANS_DDI_PHSYNC)
3837 		flags |= DRM_MODE_FLAG_PHSYNC;
3838 	else
3839 		flags |= DRM_MODE_FLAG_NHSYNC;
3840 	if (temp & TRANS_DDI_PVSYNC)
3841 		flags |= DRM_MODE_FLAG_PVSYNC;
3842 	else
3843 		flags |= DRM_MODE_FLAG_NVSYNC;
3844 
3845 	pipe_config->base.adjusted_mode.flags |= flags;
3846 
3847 	switch (temp & TRANS_DDI_BPC_MASK) {
3848 	case TRANS_DDI_BPC_6:
3849 		pipe_config->pipe_bpp = 18;
3850 		break;
3851 	case TRANS_DDI_BPC_8:
3852 		pipe_config->pipe_bpp = 24;
3853 		break;
3854 	case TRANS_DDI_BPC_10:
3855 		pipe_config->pipe_bpp = 30;
3856 		break;
3857 	case TRANS_DDI_BPC_12:
3858 		pipe_config->pipe_bpp = 36;
3859 		break;
3860 	default:
3861 		break;
3862 	}
3863 
3864 	switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3865 	case TRANS_DDI_MODE_SELECT_HDMI:
3866 		pipe_config->has_hdmi_sink = true;
3867 
3868 		pipe_config->infoframes.enable |=
3869 			intel_hdmi_infoframes_enabled(encoder, pipe_config);
3870 
3871 		if (pipe_config->infoframes.enable)
3872 			pipe_config->has_infoframe = true;
3873 
3874 		if (temp & TRANS_DDI_HDMI_SCRAMBLING)
3875 			pipe_config->hdmi_scrambling = true;
3876 		if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3877 			pipe_config->hdmi_high_tmds_clock_ratio = true;
3878 		/* fall through */
3879 	case TRANS_DDI_MODE_SELECT_DVI:
3880 		pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
3881 		pipe_config->lane_count = 4;
3882 		break;
3883 	case TRANS_DDI_MODE_SELECT_FDI:
3884 		pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
3885 		break;
3886 	case TRANS_DDI_MODE_SELECT_DP_SST:
3887 		if (encoder->type == INTEL_OUTPUT_EDP)
3888 			pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3889 		else
3890 			pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3891 		pipe_config->lane_count =
3892 			((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3893 		intel_dp_get_m_n(intel_crtc, pipe_config);
3894 		break;
3895 	case TRANS_DDI_MODE_SELECT_DP_MST:
3896 		pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
3897 		pipe_config->lane_count =
3898 			((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3899 		intel_dp_get_m_n(intel_crtc, pipe_config);
3900 		break;
3901 	default:
3902 		break;
3903 	}
3904 
3905 	pipe_config->has_audio =
3906 		intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
3907 
3908 	if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3909 	    pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3910 		/*
3911 		 * This is a big fat ugly hack.
3912 		 *
3913 		 * Some machines in UEFI boot mode provide us a VBT that has 18
3914 		 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3915 		 * unknown we fail to light up. Yet the same BIOS boots up with
3916 		 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3917 		 * max, not what it tells us to use.
3918 		 *
3919 		 * Note: This will still be broken if the eDP panel is not lit
3920 		 * up by the BIOS, and thus we can't get the mode at module
3921 		 * load.
3922 		 */
3923 		DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3924 			      pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3925 		dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3926 	}
3927 
3928 	intel_ddi_clock_get(encoder, pipe_config);
3929 
3930 	if (IS_GEN9_LP(dev_priv))
3931 		pipe_config->lane_lat_optim_mask =
3932 			bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
3933 
3934 	intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3935 
3936 	intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
3937 
3938 	intel_read_infoframe(encoder, pipe_config,
3939 			     HDMI_INFOFRAME_TYPE_AVI,
3940 			     &pipe_config->infoframes.avi);
3941 	intel_read_infoframe(encoder, pipe_config,
3942 			     HDMI_INFOFRAME_TYPE_SPD,
3943 			     &pipe_config->infoframes.spd);
3944 	intel_read_infoframe(encoder, pipe_config,
3945 			     HDMI_INFOFRAME_TYPE_VENDOR,
3946 			     &pipe_config->infoframes.hdmi);
3947 	intel_read_infoframe(encoder, pipe_config,
3948 			     HDMI_INFOFRAME_TYPE_DRM,
3949 			     &pipe_config->infoframes.drm);
3950 }
3951 
3952 static enum intel_output_type
3953 intel_ddi_compute_output_type(struct intel_encoder *encoder,
3954 			      struct intel_crtc_state *crtc_state,
3955 			      struct drm_connector_state *conn_state)
3956 {
3957 	switch (conn_state->connector->connector_type) {
3958 	case DRM_MODE_CONNECTOR_HDMIA:
3959 		return INTEL_OUTPUT_HDMI;
3960 	case DRM_MODE_CONNECTOR_eDP:
3961 		return INTEL_OUTPUT_EDP;
3962 	case DRM_MODE_CONNECTOR_DisplayPort:
3963 		return INTEL_OUTPUT_DP;
3964 	default:
3965 		MISSING_CASE(conn_state->connector->connector_type);
3966 		return INTEL_OUTPUT_UNUSED;
3967 	}
3968 }
3969 
3970 static int intel_ddi_compute_config(struct intel_encoder *encoder,
3971 				    struct intel_crtc_state *pipe_config,
3972 				    struct drm_connector_state *conn_state)
3973 {
3974 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3975 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3976 	enum port port = encoder->port;
3977 	int ret;
3978 
3979 	if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
3980 		pipe_config->cpu_transcoder = TRANSCODER_EDP;
3981 
3982 	if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
3983 		ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
3984 	else
3985 		ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
3986 	if (ret)
3987 		return ret;
3988 
3989 	if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
3990 	    pipe_config->cpu_transcoder == TRANSCODER_EDP)
3991 		pipe_config->pch_pfit.force_thru =
3992 			pipe_config->pch_pfit.enabled ||
3993 			pipe_config->crc_enabled;
3994 
3995 	if (IS_GEN9_LP(dev_priv))
3996 		pipe_config->lane_lat_optim_mask =
3997 			bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
3998 
3999 	intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
4000 
4001 	return 0;
4002 }
4003 
4004 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
4005 {
4006 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4007 
4008 	intel_dp_encoder_flush_work(encoder);
4009 
4010 	drm_encoder_cleanup(encoder);
4011 	kfree(dig_port);
4012 }
4013 
4014 static const struct drm_encoder_funcs intel_ddi_funcs = {
4015 	.reset = intel_dp_encoder_reset,
4016 	.destroy = intel_ddi_encoder_destroy,
4017 };
4018 
4019 static struct intel_connector *
4020 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
4021 {
4022 	struct intel_connector *connector;
4023 	enum port port = intel_dig_port->base.port;
4024 
4025 	connector = intel_connector_alloc();
4026 	if (!connector)
4027 		return NULL;
4028 
4029 	intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
4030 	intel_dig_port->dp.prepare_link_retrain =
4031 		intel_ddi_prepare_link_retrain;
4032 
4033 	if (!intel_dp_init_connector(intel_dig_port, connector)) {
4034 		kfree(connector);
4035 		return NULL;
4036 	}
4037 
4038 	return connector;
4039 }
4040 
4041 static int modeset_pipe(struct drm_crtc *crtc,
4042 			struct drm_modeset_acquire_ctx *ctx)
4043 {
4044 	struct drm_atomic_state *state;
4045 	struct drm_crtc_state *crtc_state;
4046 	int ret;
4047 
4048 	state = drm_atomic_state_alloc(crtc->dev);
4049 	if (!state)
4050 		return -ENOMEM;
4051 
4052 	state->acquire_ctx = ctx;
4053 
4054 	crtc_state = drm_atomic_get_crtc_state(state, crtc);
4055 	if (IS_ERR(crtc_state)) {
4056 		ret = PTR_ERR(crtc_state);
4057 		goto out;
4058 	}
4059 
4060 	crtc_state->connectors_changed = true;
4061 
4062 	ret = drm_atomic_commit(state);
4063 out:
4064 	drm_atomic_state_put(state);
4065 
4066 	return ret;
4067 }
4068 
4069 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
4070 				 struct drm_modeset_acquire_ctx *ctx)
4071 {
4072 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4073 	struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
4074 	struct intel_connector *connector = hdmi->attached_connector;
4075 	struct i2c_adapter *adapter =
4076 		intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
4077 	struct drm_connector_state *conn_state;
4078 	struct intel_crtc_state *crtc_state;
4079 	struct intel_crtc *crtc;
4080 	u8 config;
4081 	int ret;
4082 
4083 	if (!connector || connector->base.status != connector_status_connected)
4084 		return 0;
4085 
4086 	ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4087 			       ctx);
4088 	if (ret)
4089 		return ret;
4090 
4091 	conn_state = connector->base.state;
4092 
4093 	crtc = to_intel_crtc(conn_state->crtc);
4094 	if (!crtc)
4095 		return 0;
4096 
4097 	ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4098 	if (ret)
4099 		return ret;
4100 
4101 	crtc_state = to_intel_crtc_state(crtc->base.state);
4102 
4103 	WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4104 
4105 	if (!crtc_state->base.active)
4106 		return 0;
4107 
4108 	if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4109 	    !crtc_state->hdmi_scrambling)
4110 		return 0;
4111 
4112 	if (conn_state->commit &&
4113 	    !try_wait_for_completion(&conn_state->commit->hw_done))
4114 		return 0;
4115 
4116 	ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4117 	if (ret < 0) {
4118 		DRM_ERROR("Failed to read TMDS config: %d\n", ret);
4119 		return 0;
4120 	}
4121 
4122 	if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4123 	    crtc_state->hdmi_high_tmds_clock_ratio &&
4124 	    !!(config & SCDC_SCRAMBLING_ENABLE) ==
4125 	    crtc_state->hdmi_scrambling)
4126 		return 0;
4127 
4128 	/*
4129 	 * HDMI 2.0 says that one should not send scrambled data
4130 	 * prior to configuring the sink scrambling, and that
4131 	 * TMDS clock/data transmission should be suspended when
4132 	 * changing the TMDS clock rate in the sink. So let's
4133 	 * just do a full modeset here, even though some sinks
4134 	 * would be perfectly happy if were to just reconfigure
4135 	 * the SCDC settings on the fly.
4136 	 */
4137 	return modeset_pipe(&crtc->base, ctx);
4138 }
4139 
4140 static enum intel_hotplug_state
4141 intel_ddi_hotplug(struct intel_encoder *encoder,
4142 		  struct intel_connector *connector,
4143 		  bool irq_received)
4144 {
4145 	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
4146 	struct drm_modeset_acquire_ctx ctx;
4147 	enum intel_hotplug_state state;
4148 	int ret;
4149 
4150 	state = intel_encoder_hotplug(encoder, connector, irq_received);
4151 
4152 	drm_modeset_acquire_init(&ctx, 0);
4153 
4154 	for (;;) {
4155 		if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4156 			ret = intel_hdmi_reset_link(encoder, &ctx);
4157 		else
4158 			ret = intel_dp_retrain_link(encoder, &ctx);
4159 
4160 		if (ret == -EDEADLK) {
4161 			drm_modeset_backoff(&ctx);
4162 			continue;
4163 		}
4164 
4165 		break;
4166 	}
4167 
4168 	drm_modeset_drop_locks(&ctx);
4169 	drm_modeset_acquire_fini(&ctx);
4170 	WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4171 
4172 	/*
4173 	 * Unpowered type-c dongles can take some time to boot and be
4174 	 * responsible, so here giving some time to those dongles to power up
4175 	 * and then retrying the probe.
4176 	 *
4177 	 * On many platforms the HDMI live state signal is known to be
4178 	 * unreliable, so we can't use it to detect if a sink is connected or
4179 	 * not. Instead we detect if it's connected based on whether we can
4180 	 * read the EDID or not. That in turn has a problem during disconnect,
4181 	 * since the HPD interrupt may be raised before the DDC lines get
4182 	 * disconnected (due to how the required length of DDC vs. HPD
4183 	 * connector pins are specified) and so we'll still be able to get a
4184 	 * valid EDID. To solve this schedule another detection cycle if this
4185 	 * time around we didn't detect any change in the sink's connection
4186 	 * status.
4187 	 */
4188 	if (state == INTEL_HOTPLUG_UNCHANGED && irq_received &&
4189 	    !dig_port->dp.is_mst)
4190 		state = INTEL_HOTPLUG_RETRY;
4191 
4192 	return state;
4193 }
4194 
4195 static struct intel_connector *
4196 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
4197 {
4198 	struct intel_connector *connector;
4199 	enum port port = intel_dig_port->base.port;
4200 
4201 	connector = intel_connector_alloc();
4202 	if (!connector)
4203 		return NULL;
4204 
4205 	intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4206 	intel_hdmi_init_connector(intel_dig_port, connector);
4207 
4208 	return connector;
4209 }
4210 
4211 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
4212 {
4213 	struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
4214 
4215 	if (dport->base.port != PORT_A)
4216 		return false;
4217 
4218 	if (dport->saved_port_bits & DDI_A_4_LANES)
4219 		return false;
4220 
4221 	/* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4222 	 *                     supported configuration
4223 	 */
4224 	if (IS_GEN9_LP(dev_priv))
4225 		return true;
4226 
4227 	/* Cannonlake: Most of SKUs don't support DDI_E, and the only
4228 	 *             one who does also have a full A/E split called
4229 	 *             DDI_F what makes DDI_E useless. However for this
4230 	 *             case let's trust VBT info.
4231 	 */
4232 	if (IS_CANNONLAKE(dev_priv) &&
4233 	    !intel_bios_is_port_present(dev_priv, PORT_E))
4234 		return true;
4235 
4236 	return false;
4237 }
4238 
4239 static int
4240 intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
4241 {
4242 	struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
4243 	enum port port = intel_dport->base.port;
4244 	int max_lanes = 4;
4245 
4246 	if (INTEL_GEN(dev_priv) >= 11)
4247 		return max_lanes;
4248 
4249 	if (port == PORT_A || port == PORT_E) {
4250 		if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4251 			max_lanes = port == PORT_A ? 4 : 0;
4252 		else
4253 			/* Both A and E share 2 lanes */
4254 			max_lanes = 2;
4255 	}
4256 
4257 	/*
4258 	 * Some BIOS might fail to set this bit on port A if eDP
4259 	 * wasn't lit up at boot.  Force this bit set when needed
4260 	 * so we use the proper lane count for our calculations.
4261 	 */
4262 	if (intel_ddi_a_force_4_lanes(intel_dport)) {
4263 		DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
4264 		intel_dport->saved_port_bits |= DDI_A_4_LANES;
4265 		max_lanes = 4;
4266 	}
4267 
4268 	return max_lanes;
4269 }
4270 
4271 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
4272 {
4273 	struct ddi_vbt_port_info *port_info =
4274 		&dev_priv->vbt.ddi_port_info[port];
4275 	struct intel_digital_port *intel_dig_port;
4276 	struct intel_encoder *intel_encoder;
4277 	struct drm_encoder *encoder;
4278 	bool init_hdmi, init_dp, init_lspcon = false;
4279 	enum pipe pipe;
4280 	enum phy phy = intel_port_to_phy(dev_priv, port);
4281 
4282 	init_hdmi = port_info->supports_dvi || port_info->supports_hdmi;
4283 	init_dp = port_info->supports_dp;
4284 
4285 	if (intel_bios_is_lspcon_present(dev_priv, port)) {
4286 		/*
4287 		 * Lspcon device needs to be driven with DP connector
4288 		 * with special detection sequence. So make sure DP
4289 		 * is initialized before lspcon.
4290 		 */
4291 		init_dp = true;
4292 		init_lspcon = true;
4293 		init_hdmi = false;
4294 		DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
4295 	}
4296 
4297 	if (!init_dp && !init_hdmi) {
4298 		DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4299 			      port_name(port));
4300 		return;
4301 	}
4302 
4303 	intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4304 	if (!intel_dig_port)
4305 		return;
4306 
4307 	intel_encoder = &intel_dig_port->base;
4308 	encoder = &intel_encoder->base;
4309 
4310 	drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
4311 			 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
4312 
4313 	intel_encoder->hotplug = intel_ddi_hotplug;
4314 	intel_encoder->compute_output_type = intel_ddi_compute_output_type;
4315 	intel_encoder->compute_config = intel_ddi_compute_config;
4316 	intel_encoder->enable = intel_enable_ddi;
4317 	intel_encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4318 	intel_encoder->post_pll_disable = intel_ddi_post_pll_disable;
4319 	intel_encoder->pre_enable = intel_ddi_pre_enable;
4320 	intel_encoder->disable = intel_disable_ddi;
4321 	intel_encoder->post_disable = intel_ddi_post_disable;
4322 	intel_encoder->update_pipe = intel_ddi_update_pipe;
4323 	intel_encoder->get_hw_state = intel_ddi_get_hw_state;
4324 	intel_encoder->get_config = intel_ddi_get_config;
4325 	intel_encoder->suspend = intel_dp_encoder_suspend;
4326 	intel_encoder->get_power_domains = intel_ddi_get_power_domains;
4327 	intel_encoder->type = INTEL_OUTPUT_DDI;
4328 	intel_encoder->power_domain = intel_port_to_power_domain(port);
4329 	intel_encoder->port = port;
4330 	intel_encoder->cloneable = 0;
4331 	for_each_pipe(dev_priv, pipe)
4332 		intel_encoder->crtc_mask |= BIT(pipe);
4333 
4334 	if (INTEL_GEN(dev_priv) >= 11)
4335 		intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4336 			DDI_BUF_PORT_REVERSAL;
4337 	else
4338 		intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4339 			(DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
4340 	intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
4341 	intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
4342 	intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
4343 
4344 	if (intel_phy_is_tc(dev_priv, phy)) {
4345 		bool is_legacy = !port_info->supports_typec_usb &&
4346 				 !port_info->supports_tbt;
4347 
4348 		intel_tc_port_init(intel_dig_port, is_legacy);
4349 
4350 		intel_encoder->update_prepare = intel_ddi_update_prepare;
4351 		intel_encoder->update_complete = intel_ddi_update_complete;
4352 	}
4353 
4354 	switch (port) {
4355 	case PORT_A:
4356 		intel_dig_port->ddi_io_power_domain =
4357 			POWER_DOMAIN_PORT_DDI_A_IO;
4358 		break;
4359 	case PORT_B:
4360 		intel_dig_port->ddi_io_power_domain =
4361 			POWER_DOMAIN_PORT_DDI_B_IO;
4362 		break;
4363 	case PORT_C:
4364 		intel_dig_port->ddi_io_power_domain =
4365 			POWER_DOMAIN_PORT_DDI_C_IO;
4366 		break;
4367 	case PORT_D:
4368 		intel_dig_port->ddi_io_power_domain =
4369 			POWER_DOMAIN_PORT_DDI_D_IO;
4370 		break;
4371 	case PORT_E:
4372 		intel_dig_port->ddi_io_power_domain =
4373 			POWER_DOMAIN_PORT_DDI_E_IO;
4374 		break;
4375 	case PORT_F:
4376 		intel_dig_port->ddi_io_power_domain =
4377 			POWER_DOMAIN_PORT_DDI_F_IO;
4378 		break;
4379 	case PORT_G:
4380 		intel_dig_port->ddi_io_power_domain =
4381 			POWER_DOMAIN_PORT_DDI_G_IO;
4382 		break;
4383 	case PORT_H:
4384 		intel_dig_port->ddi_io_power_domain =
4385 			POWER_DOMAIN_PORT_DDI_H_IO;
4386 		break;
4387 	case PORT_I:
4388 		intel_dig_port->ddi_io_power_domain =
4389 			POWER_DOMAIN_PORT_DDI_I_IO;
4390 		break;
4391 	default:
4392 		MISSING_CASE(port);
4393 	}
4394 
4395 	if (init_dp) {
4396 		if (!intel_ddi_init_dp_connector(intel_dig_port))
4397 			goto err;
4398 
4399 		intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4400 	}
4401 
4402 	/* In theory we don't need the encoder->type check, but leave it just in
4403 	 * case we have some really bad VBTs... */
4404 	if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4405 		if (!intel_ddi_init_hdmi_connector(intel_dig_port))
4406 			goto err;
4407 	}
4408 
4409 	if (init_lspcon) {
4410 		if (lspcon_init(intel_dig_port))
4411 			/* TODO: handle hdmi info frame part */
4412 			DRM_DEBUG_KMS("LSPCON init success on port %c\n",
4413 				port_name(port));
4414 		else
4415 			/*
4416 			 * LSPCON init faied, but DP init was success, so
4417 			 * lets try to drive as DP++ port.
4418 			 */
4419 			DRM_ERROR("LSPCON init failed on port %c\n",
4420 				port_name(port));
4421 	}
4422 
4423 	intel_infoframe_init(intel_dig_port);
4424 
4425 	return;
4426 
4427 err:
4428 	drm_encoder_cleanup(encoder);
4429 	kfree(intel_dig_port);
4430 }
4431