1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <drm/drm_scdc_helper.h> 29 30 #include "i915_drv.h" 31 #include "intel_audio.h" 32 #include "intel_combo_phy.h" 33 #include "intel_connector.h" 34 #include "intel_crtc.h" 35 #include "intel_ddi.h" 36 #include "intel_ddi_buf_trans.h" 37 #include "intel_de.h" 38 #include "intel_display_types.h" 39 #include "intel_dp.h" 40 #include "intel_dp_link_training.h" 41 #include "intel_dp_mst.h" 42 #include "intel_dpio_phy.h" 43 #include "intel_dsi.h" 44 #include "intel_fdi.h" 45 #include "intel_fifo_underrun.h" 46 #include "intel_gmbus.h" 47 #include "intel_hdcp.h" 48 #include "intel_hdmi.h" 49 #include "intel_hotplug.h" 50 #include "intel_lspcon.h" 51 #include "intel_panel.h" 52 #include "intel_pps.h" 53 #include "intel_psr.h" 54 #include "intel_sprite.h" 55 #include "intel_tc.h" 56 #include "intel_vdsc.h" 57 #include "intel_vrr.h" 58 #include "skl_scaler.h" 59 #include "skl_universal_plane.h" 60 61 static const u8 index_to_dp_signal_levels[] = { 62 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 63 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 64 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 65 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 66 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 67 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 68 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 69 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 70 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 71 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 72 }; 73 74 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 75 const struct intel_crtc_state *crtc_state) 76 { 77 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 78 int n_entries, level, default_entry; 79 80 n_entries = intel_ddi_hdmi_num_entries(encoder, crtc_state, &default_entry); 81 if (n_entries == 0) 82 return 0; 83 level = intel_bios_hdmi_level_shift(encoder); 84 if (level < 0) 85 level = default_entry; 86 87 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 88 level = n_entries - 1; 89 90 return level; 91 } 92 93 /* 94 * Starting with Haswell, DDI port buffers must be programmed with correct 95 * values in advance. This function programs the correct values for 96 * DP/eDP/FDI use cases. 97 */ 98 void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 99 const struct intel_crtc_state *crtc_state) 100 { 101 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 102 u32 iboost_bit = 0; 103 int i, n_entries; 104 enum port port = encoder->port; 105 const struct ddi_buf_trans *ddi_translations; 106 107 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) 108 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv, 109 &n_entries); 110 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 111 ddi_translations = intel_ddi_get_buf_trans_edp(encoder, 112 &n_entries); 113 else 114 ddi_translations = intel_ddi_get_buf_trans_dp(encoder, 115 &n_entries); 116 117 /* If we're boosting the current, set bit 31 of trans1 */ 118 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) && 119 intel_bios_encoder_dp_boost_level(encoder->devdata)) 120 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 121 122 for (i = 0; i < n_entries; i++) { 123 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 124 ddi_translations[i].trans1 | iboost_bit); 125 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 126 ddi_translations[i].trans2); 127 } 128 } 129 130 /* 131 * Starting with Haswell, DDI port buffers must be programmed with correct 132 * values in advance. This function programs the correct values for 133 * HDMI/DVI use cases. 134 */ 135 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 136 int level) 137 { 138 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 139 u32 iboost_bit = 0; 140 int n_entries; 141 enum port port = encoder->port; 142 const struct ddi_buf_trans *ddi_translations; 143 144 ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); 145 146 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 147 return; 148 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 149 level = n_entries - 1; 150 151 /* If we're boosting the current, set bit 31 of trans1 */ 152 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) && 153 intel_bios_encoder_hdmi_boost_level(encoder->devdata)) 154 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 155 156 /* Entry 9 is for HDMI: */ 157 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 158 ddi_translations[level].trans1 | iboost_bit); 159 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 160 ddi_translations[level].trans2); 161 } 162 163 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 164 enum port port) 165 { 166 if (IS_BROXTON(dev_priv)) { 167 udelay(16); 168 return; 169 } 170 171 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 172 DDI_BUF_IS_IDLE), 8)) 173 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", 174 port_name(port)); 175 } 176 177 static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, 178 enum port port) 179 { 180 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ 181 if (DISPLAY_VER(dev_priv) < 10) { 182 usleep_range(518, 1000); 183 return; 184 } 185 186 if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 187 DDI_BUF_IS_IDLE), 500)) 188 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", 189 port_name(port)); 190 } 191 192 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 193 { 194 switch (pll->info->id) { 195 case DPLL_ID_WRPLL1: 196 return PORT_CLK_SEL_WRPLL1; 197 case DPLL_ID_WRPLL2: 198 return PORT_CLK_SEL_WRPLL2; 199 case DPLL_ID_SPLL: 200 return PORT_CLK_SEL_SPLL; 201 case DPLL_ID_LCPLL_810: 202 return PORT_CLK_SEL_LCPLL_810; 203 case DPLL_ID_LCPLL_1350: 204 return PORT_CLK_SEL_LCPLL_1350; 205 case DPLL_ID_LCPLL_2700: 206 return PORT_CLK_SEL_LCPLL_2700; 207 default: 208 MISSING_CASE(pll->info->id); 209 return PORT_CLK_SEL_NONE; 210 } 211 } 212 213 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 214 const struct intel_crtc_state *crtc_state) 215 { 216 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 217 int clock = crtc_state->port_clock; 218 const enum intel_dpll_id id = pll->info->id; 219 220 switch (id) { 221 default: 222 /* 223 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 224 * here, so do warn if this get passed in 225 */ 226 MISSING_CASE(id); 227 return DDI_CLK_SEL_NONE; 228 case DPLL_ID_ICL_TBTPLL: 229 switch (clock) { 230 case 162000: 231 return DDI_CLK_SEL_TBT_162; 232 case 270000: 233 return DDI_CLK_SEL_TBT_270; 234 case 540000: 235 return DDI_CLK_SEL_TBT_540; 236 case 810000: 237 return DDI_CLK_SEL_TBT_810; 238 default: 239 MISSING_CASE(clock); 240 return DDI_CLK_SEL_NONE; 241 } 242 case DPLL_ID_ICL_MGPLL1: 243 case DPLL_ID_ICL_MGPLL2: 244 case DPLL_ID_ICL_MGPLL3: 245 case DPLL_ID_ICL_MGPLL4: 246 case DPLL_ID_TGL_MGPLL5: 247 case DPLL_ID_TGL_MGPLL6: 248 return DDI_CLK_SEL_MG; 249 } 250 } 251 252 static u32 ddi_buf_phy_link_rate(int port_clock) 253 { 254 switch (port_clock) { 255 case 162000: 256 return DDI_BUF_PHY_LINK_RATE(0); 257 case 216000: 258 return DDI_BUF_PHY_LINK_RATE(4); 259 case 243000: 260 return DDI_BUF_PHY_LINK_RATE(5); 261 case 270000: 262 return DDI_BUF_PHY_LINK_RATE(1); 263 case 324000: 264 return DDI_BUF_PHY_LINK_RATE(6); 265 case 432000: 266 return DDI_BUF_PHY_LINK_RATE(7); 267 case 540000: 268 return DDI_BUF_PHY_LINK_RATE(2); 269 case 810000: 270 return DDI_BUF_PHY_LINK_RATE(3); 271 default: 272 MISSING_CASE(port_clock); 273 return DDI_BUF_PHY_LINK_RATE(0); 274 } 275 } 276 277 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 278 const struct intel_crtc_state *crtc_state) 279 { 280 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 281 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 282 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 283 enum phy phy = intel_port_to_phy(i915, encoder->port); 284 285 intel_dp->DP = dig_port->saved_port_bits | 286 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); 287 intel_dp->DP |= DDI_PORT_WIDTH(crtc_state->lane_count); 288 289 if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) { 290 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 291 if (dig_port->tc_mode != TC_PORT_TBT_ALT) 292 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 293 } 294 } 295 296 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 297 enum port port) 298 { 299 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 300 301 switch (val) { 302 case DDI_CLK_SEL_NONE: 303 return 0; 304 case DDI_CLK_SEL_TBT_162: 305 return 162000; 306 case DDI_CLK_SEL_TBT_270: 307 return 270000; 308 case DDI_CLK_SEL_TBT_540: 309 return 540000; 310 case DDI_CLK_SEL_TBT_810: 311 return 810000; 312 default: 313 MISSING_CASE(val); 314 return 0; 315 } 316 } 317 318 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 319 { 320 int dotclock; 321 322 if (pipe_config->has_pch_encoder) 323 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 324 &pipe_config->fdi_m_n); 325 else if (intel_crtc_has_dp_encoder(pipe_config)) 326 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 327 &pipe_config->dp_m_n); 328 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) 329 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp; 330 else 331 dotclock = pipe_config->port_clock; 332 333 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 334 !intel_crtc_has_dp_encoder(pipe_config)) 335 dotclock *= 2; 336 337 if (pipe_config->pixel_multiplier) 338 dotclock /= pipe_config->pixel_multiplier; 339 340 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 341 } 342 343 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 344 const struct drm_connector_state *conn_state) 345 { 346 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 347 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 348 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 349 u32 temp; 350 351 if (!intel_crtc_has_dp_encoder(crtc_state)) 352 return; 353 354 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 355 356 temp = DP_MSA_MISC_SYNC_CLOCK; 357 358 switch (crtc_state->pipe_bpp) { 359 case 18: 360 temp |= DP_MSA_MISC_6_BPC; 361 break; 362 case 24: 363 temp |= DP_MSA_MISC_8_BPC; 364 break; 365 case 30: 366 temp |= DP_MSA_MISC_10_BPC; 367 break; 368 case 36: 369 temp |= DP_MSA_MISC_12_BPC; 370 break; 371 default: 372 MISSING_CASE(crtc_state->pipe_bpp); 373 break; 374 } 375 376 /* nonsense combination */ 377 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 378 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 379 380 if (crtc_state->limited_color_range) 381 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 382 383 /* 384 * As per DP 1.2 spec section 2.3.4.3 while sending 385 * YCBCR 444 signals we should program MSA MISC1/0 fields with 386 * colorspace information. 387 */ 388 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 389 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 390 391 /* 392 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 393 * of Color Encoding Format and Content Color Gamut] while sending 394 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 395 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 396 */ 397 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 398 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 399 400 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp); 401 } 402 403 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 404 { 405 if (master_transcoder == TRANSCODER_EDP) 406 return 0; 407 else 408 return master_transcoder + 1; 409 } 410 411 /* 412 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 413 * 414 * Only intended to be used by intel_ddi_enable_transcoder_func() and 415 * intel_ddi_config_transcoder_func(). 416 */ 417 static u32 418 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 419 const struct intel_crtc_state *crtc_state) 420 { 421 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 422 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 423 enum pipe pipe = crtc->pipe; 424 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 425 enum port port = encoder->port; 426 u32 temp; 427 428 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 429 temp = TRANS_DDI_FUNC_ENABLE; 430 if (DISPLAY_VER(dev_priv) >= 12) 431 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 432 else 433 temp |= TRANS_DDI_SELECT_PORT(port); 434 435 switch (crtc_state->pipe_bpp) { 436 case 18: 437 temp |= TRANS_DDI_BPC_6; 438 break; 439 case 24: 440 temp |= TRANS_DDI_BPC_8; 441 break; 442 case 30: 443 temp |= TRANS_DDI_BPC_10; 444 break; 445 case 36: 446 temp |= TRANS_DDI_BPC_12; 447 break; 448 default: 449 BUG(); 450 } 451 452 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 453 temp |= TRANS_DDI_PVSYNC; 454 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 455 temp |= TRANS_DDI_PHSYNC; 456 457 if (cpu_transcoder == TRANSCODER_EDP) { 458 switch (pipe) { 459 case PIPE_A: 460 /* On Haswell, can only use the always-on power well for 461 * eDP when not using the panel fitter, and when not 462 * using motion blur mitigation (which we don't 463 * support). */ 464 if (crtc_state->pch_pfit.force_thru) 465 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 466 else 467 temp |= TRANS_DDI_EDP_INPUT_A_ON; 468 break; 469 case PIPE_B: 470 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 471 break; 472 case PIPE_C: 473 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 474 break; 475 default: 476 BUG(); 477 break; 478 } 479 } 480 481 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 482 if (crtc_state->has_hdmi_sink) 483 temp |= TRANS_DDI_MODE_SELECT_HDMI; 484 else 485 temp |= TRANS_DDI_MODE_SELECT_DVI; 486 487 if (crtc_state->hdmi_scrambling) 488 temp |= TRANS_DDI_HDMI_SCRAMBLING; 489 if (crtc_state->hdmi_high_tmds_clock_ratio) 490 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 491 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 492 temp |= TRANS_DDI_MODE_SELECT_FDI; 493 temp |= (crtc_state->fdi_lanes - 1) << 1; 494 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 495 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 496 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 497 498 if (DISPLAY_VER(dev_priv) >= 12) { 499 enum transcoder master; 500 501 master = crtc_state->mst_master_transcoder; 502 drm_WARN_ON(&dev_priv->drm, 503 master == INVALID_TRANSCODER); 504 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 505 } 506 } else { 507 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 508 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 509 } 510 511 if (IS_DISPLAY_VER(dev_priv, 8, 10) && 512 crtc_state->master_transcoder != INVALID_TRANSCODER) { 513 u8 master_select = 514 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 515 516 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 517 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 518 } 519 520 return temp; 521 } 522 523 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 524 const struct intel_crtc_state *crtc_state) 525 { 526 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 527 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 528 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 529 530 if (DISPLAY_VER(dev_priv) >= 11) { 531 enum transcoder master_transcoder = crtc_state->master_transcoder; 532 u32 ctl2 = 0; 533 534 if (master_transcoder != INVALID_TRANSCODER) { 535 u8 master_select = 536 bdw_trans_port_sync_master_select(master_transcoder); 537 538 ctl2 |= PORT_SYNC_MODE_ENABLE | 539 PORT_SYNC_MODE_MASTER_SELECT(master_select); 540 } 541 542 intel_de_write(dev_priv, 543 TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2); 544 } 545 546 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 547 intel_ddi_transcoder_func_reg_val_get(encoder, 548 crtc_state)); 549 } 550 551 /* 552 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 553 * bit. 554 */ 555 static void 556 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 557 const struct intel_crtc_state *crtc_state) 558 { 559 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 560 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 561 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 562 u32 ctl; 563 564 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 565 ctl &= ~TRANS_DDI_FUNC_ENABLE; 566 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 567 } 568 569 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 570 { 571 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 572 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 573 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 574 u32 ctl; 575 576 if (DISPLAY_VER(dev_priv) >= 11) 577 intel_de_write(dev_priv, 578 TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0); 579 580 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 581 582 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 583 584 ctl &= ~TRANS_DDI_FUNC_ENABLE; 585 586 if (IS_DISPLAY_VER(dev_priv, 8, 10)) 587 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 588 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 589 590 if (DISPLAY_VER(dev_priv) >= 12) { 591 if (!intel_dp_mst_is_master_trans(crtc_state)) { 592 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 593 TRANS_DDI_MODE_SELECT_MASK); 594 } 595 } else { 596 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 597 } 598 599 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 600 601 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME && 602 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 603 drm_dbg_kms(&dev_priv->drm, 604 "Quirk Increase DDI disabled time\n"); 605 /* Quirk time at 100ms for reliable operation */ 606 msleep(100); 607 } 608 } 609 610 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 611 enum transcoder cpu_transcoder, 612 bool enable, u32 hdcp_mask) 613 { 614 struct drm_device *dev = intel_encoder->base.dev; 615 struct drm_i915_private *dev_priv = to_i915(dev); 616 intel_wakeref_t wakeref; 617 int ret = 0; 618 u32 tmp; 619 620 wakeref = intel_display_power_get_if_enabled(dev_priv, 621 intel_encoder->power_domain); 622 if (drm_WARN_ON(dev, !wakeref)) 623 return -ENXIO; 624 625 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 626 if (enable) 627 tmp |= hdcp_mask; 628 else 629 tmp &= ~hdcp_mask; 630 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp); 631 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 632 return ret; 633 } 634 635 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 636 { 637 struct drm_device *dev = intel_connector->base.dev; 638 struct drm_i915_private *dev_priv = to_i915(dev); 639 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 640 int type = intel_connector->base.connector_type; 641 enum port port = encoder->port; 642 enum transcoder cpu_transcoder; 643 intel_wakeref_t wakeref; 644 enum pipe pipe = 0; 645 u32 tmp; 646 bool ret; 647 648 wakeref = intel_display_power_get_if_enabled(dev_priv, 649 encoder->power_domain); 650 if (!wakeref) 651 return false; 652 653 if (!encoder->get_hw_state(encoder, &pipe)) { 654 ret = false; 655 goto out; 656 } 657 658 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 659 cpu_transcoder = TRANSCODER_EDP; 660 else 661 cpu_transcoder = (enum transcoder) pipe; 662 663 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 664 665 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 666 case TRANS_DDI_MODE_SELECT_HDMI: 667 case TRANS_DDI_MODE_SELECT_DVI: 668 ret = type == DRM_MODE_CONNECTOR_HDMIA; 669 break; 670 671 case TRANS_DDI_MODE_SELECT_DP_SST: 672 ret = type == DRM_MODE_CONNECTOR_eDP || 673 type == DRM_MODE_CONNECTOR_DisplayPort; 674 break; 675 676 case TRANS_DDI_MODE_SELECT_DP_MST: 677 /* if the transcoder is in MST state then 678 * connector isn't connected */ 679 ret = false; 680 break; 681 682 case TRANS_DDI_MODE_SELECT_FDI: 683 ret = type == DRM_MODE_CONNECTOR_VGA; 684 break; 685 686 default: 687 ret = false; 688 break; 689 } 690 691 out: 692 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 693 694 return ret; 695 } 696 697 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 698 u8 *pipe_mask, bool *is_dp_mst) 699 { 700 struct drm_device *dev = encoder->base.dev; 701 struct drm_i915_private *dev_priv = to_i915(dev); 702 enum port port = encoder->port; 703 intel_wakeref_t wakeref; 704 enum pipe p; 705 u32 tmp; 706 u8 mst_pipe_mask; 707 708 *pipe_mask = 0; 709 *is_dp_mst = false; 710 711 wakeref = intel_display_power_get_if_enabled(dev_priv, 712 encoder->power_domain); 713 if (!wakeref) 714 return; 715 716 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 717 if (!(tmp & DDI_BUF_CTL_ENABLE)) 718 goto out; 719 720 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { 721 tmp = intel_de_read(dev_priv, 722 TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 723 724 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 725 default: 726 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 727 fallthrough; 728 case TRANS_DDI_EDP_INPUT_A_ON: 729 case TRANS_DDI_EDP_INPUT_A_ONOFF: 730 *pipe_mask = BIT(PIPE_A); 731 break; 732 case TRANS_DDI_EDP_INPUT_B_ONOFF: 733 *pipe_mask = BIT(PIPE_B); 734 break; 735 case TRANS_DDI_EDP_INPUT_C_ONOFF: 736 *pipe_mask = BIT(PIPE_C); 737 break; 738 } 739 740 goto out; 741 } 742 743 mst_pipe_mask = 0; 744 for_each_pipe(dev_priv, p) { 745 enum transcoder cpu_transcoder = (enum transcoder)p; 746 unsigned int port_mask, ddi_select; 747 intel_wakeref_t trans_wakeref; 748 749 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 750 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 751 if (!trans_wakeref) 752 continue; 753 754 if (DISPLAY_VER(dev_priv) >= 12) { 755 port_mask = TGL_TRANS_DDI_PORT_MASK; 756 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 757 } else { 758 port_mask = TRANS_DDI_PORT_MASK; 759 ddi_select = TRANS_DDI_SELECT_PORT(port); 760 } 761 762 tmp = intel_de_read(dev_priv, 763 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 764 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 765 trans_wakeref); 766 767 if ((tmp & port_mask) != ddi_select) 768 continue; 769 770 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == 771 TRANS_DDI_MODE_SELECT_DP_MST) 772 mst_pipe_mask |= BIT(p); 773 774 *pipe_mask |= BIT(p); 775 } 776 777 if (!*pipe_mask) 778 drm_dbg_kms(&dev_priv->drm, 779 "No pipe for [ENCODER:%d:%s] found\n", 780 encoder->base.base.id, encoder->base.name); 781 782 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 783 drm_dbg_kms(&dev_priv->drm, 784 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 785 encoder->base.base.id, encoder->base.name, 786 *pipe_mask); 787 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 788 } 789 790 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 791 drm_dbg_kms(&dev_priv->drm, 792 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", 793 encoder->base.base.id, encoder->base.name, 794 *pipe_mask, mst_pipe_mask); 795 else 796 *is_dp_mst = mst_pipe_mask; 797 798 out: 799 if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) { 800 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 801 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 802 BXT_PHY_LANE_POWERDOWN_ACK | 803 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 804 drm_err(&dev_priv->drm, 805 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 806 encoder->base.base.id, encoder->base.name, tmp); 807 } 808 809 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 810 } 811 812 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 813 enum pipe *pipe) 814 { 815 u8 pipe_mask; 816 bool is_mst; 817 818 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 819 820 if (is_mst || !pipe_mask) 821 return false; 822 823 *pipe = ffs(pipe_mask) - 1; 824 825 return true; 826 } 827 828 static enum intel_display_power_domain 829 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port) 830 { 831 /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with 832 * DC states enabled at the same time, while for driver initiated AUX 833 * transfers we need the same AUX IOs to be powered but with DC states 834 * disabled. Accordingly use the AUX power domain here which leaves DC 835 * states enabled. 836 * However, for non-A AUX ports the corresponding non-EDP transcoders 837 * would have already enabled power well 2 and DC_OFF. This means we can 838 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a 839 * specific AUX_IO reference without powering up any extra wells. 840 * Note that PSR is enabled only on Port A even though this function 841 * returns the correct domain for other ports too. 842 */ 843 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A : 844 intel_aux_power_domain(dig_port); 845 } 846 847 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 848 struct intel_crtc_state *crtc_state) 849 { 850 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 851 struct intel_digital_port *dig_port; 852 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 853 854 /* 855 * TODO: Add support for MST encoders. Atm, the following should never 856 * happen since fake-MST encoders don't set their get_power_domains() 857 * hook. 858 */ 859 if (drm_WARN_ON(&dev_priv->drm, 860 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 861 return; 862 863 dig_port = enc_to_dig_port(encoder); 864 865 if (!intel_phy_is_tc(dev_priv, phy) || 866 dig_port->tc_mode != TC_PORT_TBT_ALT) { 867 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 868 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 869 dig_port->ddi_io_power_domain); 870 } 871 872 /* 873 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC 874 * ports. 875 */ 876 if (intel_crtc_has_dp_encoder(crtc_state) || 877 intel_phy_is_tc(dev_priv, phy)) { 878 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref); 879 dig_port->aux_wakeref = 880 intel_display_power_get(dev_priv, 881 intel_ddi_main_link_aux_domain(dig_port)); 882 } 883 } 884 885 void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder, 886 const struct intel_crtc_state *crtc_state) 887 { 888 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 889 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 890 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 891 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 892 u32 val; 893 894 if (cpu_transcoder != TRANSCODER_EDP) { 895 if (DISPLAY_VER(dev_priv) >= 13) 896 val = TGL_TRANS_CLK_SEL_PORT(phy); 897 else if (DISPLAY_VER(dev_priv) >= 12) 898 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 899 else 900 val = TRANS_CLK_SEL_PORT(encoder->port); 901 902 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 903 } 904 } 905 906 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state) 907 { 908 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 909 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 910 911 if (cpu_transcoder != TRANSCODER_EDP) { 912 if (DISPLAY_VER(dev_priv) >= 12) 913 intel_de_write(dev_priv, 914 TRANS_CLK_SEL(cpu_transcoder), 915 TGL_TRANS_CLK_SEL_DISABLED); 916 else 917 intel_de_write(dev_priv, 918 TRANS_CLK_SEL(cpu_transcoder), 919 TRANS_CLK_SEL_DISABLED); 920 } 921 } 922 923 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 924 enum port port, u8 iboost) 925 { 926 u32 tmp; 927 928 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 929 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 930 if (iboost) 931 tmp |= iboost << BALANCE_LEG_SHIFT(port); 932 else 933 tmp |= BALANCE_LEG_DISABLE(port); 934 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 935 } 936 937 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 938 const struct intel_crtc_state *crtc_state, 939 int level) 940 { 941 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 942 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 943 u8 iboost; 944 945 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 946 iboost = intel_bios_encoder_hdmi_boost_level(encoder->devdata); 947 else 948 iboost = intel_bios_encoder_dp_boost_level(encoder->devdata); 949 950 if (iboost == 0) { 951 const struct ddi_buf_trans *ddi_translations; 952 int n_entries; 953 954 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 955 ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); 956 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 957 ddi_translations = intel_ddi_get_buf_trans_edp(encoder, &n_entries); 958 else 959 ddi_translations = intel_ddi_get_buf_trans_dp(encoder, &n_entries); 960 961 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 962 return; 963 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 964 level = n_entries - 1; 965 966 iboost = ddi_translations[level].i_boost; 967 } 968 969 /* Make sure that the requested I_boost is valid */ 970 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 971 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); 972 return; 973 } 974 975 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); 976 977 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 978 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 979 } 980 981 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, 982 const struct intel_crtc_state *crtc_state, 983 int level) 984 { 985 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 986 const struct bxt_ddi_buf_trans *ddi_translations; 987 enum port port = encoder->port; 988 int n_entries; 989 990 ddi_translations = bxt_get_buf_trans(encoder, crtc_state, &n_entries); 991 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 992 return; 993 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 994 level = n_entries - 1; 995 996 bxt_ddi_phy_set_signal_level(dev_priv, port, 997 ddi_translations[level].margin, 998 ddi_translations[level].scale, 999 ddi_translations[level].enable, 1000 ddi_translations[level].deemphasis); 1001 } 1002 1003 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1004 const struct intel_crtc_state *crtc_state) 1005 { 1006 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1007 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1008 enum port port = encoder->port; 1009 enum phy phy = intel_port_to_phy(dev_priv, port); 1010 int n_entries; 1011 1012 if (DISPLAY_VER(dev_priv) >= 12) { 1013 if (intel_phy_is_combo(dev_priv, phy)) 1014 tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries); 1015 else if (IS_ALDERLAKE_P(dev_priv)) 1016 adlp_get_dkl_buf_trans(encoder, crtc_state, &n_entries); 1017 else 1018 tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries); 1019 } else if (DISPLAY_VER(dev_priv) == 11) { 1020 if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)) 1021 jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries); 1022 else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) 1023 ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries); 1024 else if (intel_phy_is_combo(dev_priv, phy)) 1025 icl_get_combo_buf_trans(encoder, crtc_state, &n_entries); 1026 else 1027 icl_get_mg_buf_trans(encoder, crtc_state, &n_entries); 1028 } else if (IS_CANNONLAKE(dev_priv)) { 1029 cnl_get_buf_trans(encoder, crtc_state, &n_entries); 1030 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 1031 bxt_get_buf_trans(encoder, crtc_state, &n_entries); 1032 } else { 1033 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1034 intel_ddi_get_buf_trans_edp(encoder, &n_entries); 1035 else 1036 intel_ddi_get_buf_trans_dp(encoder, &n_entries); 1037 } 1038 1039 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 1040 n_entries = 1; 1041 if (drm_WARN_ON(&dev_priv->drm, 1042 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1043 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1044 1045 return index_to_dp_signal_levels[n_entries - 1] & 1046 DP_TRAIN_VOLTAGE_SWING_MASK; 1047 } 1048 1049 /* 1050 * We assume that the full set of pre-emphasis values can be 1051 * used on all DDI platforms. Should that change we need to 1052 * rethink this code. 1053 */ 1054 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1055 { 1056 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1057 } 1058 1059 static void cnl_ddi_vswing_program(struct intel_encoder *encoder, 1060 const struct intel_crtc_state *crtc_state, 1061 int level) 1062 { 1063 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1064 const struct cnl_ddi_buf_trans *ddi_translations; 1065 enum port port = encoder->port; 1066 int n_entries, ln; 1067 u32 val; 1068 1069 ddi_translations = cnl_get_buf_trans(encoder, crtc_state, &n_entries); 1070 1071 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 1072 return; 1073 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 1074 level = n_entries - 1; 1075 1076 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */ 1077 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 1078 val &= ~SCALING_MODE_SEL_MASK; 1079 val |= SCALING_MODE_SEL(2); 1080 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 1081 1082 /* Program PORT_TX_DW2 */ 1083 val = intel_de_read(dev_priv, CNL_PORT_TX_DW2_LN0(port)); 1084 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 1085 RCOMP_SCALAR_MASK); 1086 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); 1087 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); 1088 /* Rcomp scalar is fixed as 0x98 for every table entry */ 1089 val |= RCOMP_SCALAR(0x98); 1090 intel_de_write(dev_priv, CNL_PORT_TX_DW2_GRP(port), val); 1091 1092 /* Program PORT_TX_DW4 */ 1093 /* We cannot write to GRP. It would overrite individual loadgen */ 1094 for (ln = 0; ln < 4; ln++) { 1095 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port)); 1096 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 1097 CURSOR_COEFF_MASK); 1098 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); 1099 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); 1100 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); 1101 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val); 1102 } 1103 1104 /* Program PORT_TX_DW5 */ 1105 /* All DW5 values are fixed for every table entry */ 1106 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 1107 val &= ~RTERM_SELECT_MASK; 1108 val |= RTERM_SELECT(6); 1109 val |= TAP3_DISABLE; 1110 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 1111 1112 /* Program PORT_TX_DW7 */ 1113 val = intel_de_read(dev_priv, CNL_PORT_TX_DW7_LN0(port)); 1114 val &= ~N_SCALAR_MASK; 1115 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); 1116 intel_de_write(dev_priv, CNL_PORT_TX_DW7_GRP(port), val); 1117 } 1118 1119 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, 1120 const struct intel_crtc_state *crtc_state, 1121 int level) 1122 { 1123 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1124 enum port port = encoder->port; 1125 int width, rate, ln; 1126 u32 val; 1127 1128 width = crtc_state->lane_count; 1129 rate = crtc_state->port_clock; 1130 1131 /* 1132 * 1. If port type is eDP or DP, 1133 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1134 * else clear to 0b. 1135 */ 1136 val = intel_de_read(dev_priv, CNL_PORT_PCS_DW1_LN0(port)); 1137 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1138 val &= ~COMMON_KEEPER_EN; 1139 else 1140 val |= COMMON_KEEPER_EN; 1141 intel_de_write(dev_priv, CNL_PORT_PCS_DW1_GRP(port), val); 1142 1143 /* 2. Program loadgen select */ 1144 /* 1145 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes 1146 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1147 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1148 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1149 */ 1150 for (ln = 0; ln <= 3; ln++) { 1151 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port)); 1152 val &= ~LOADGEN_SELECT; 1153 1154 if ((rate <= 600000 && width == 4 && ln >= 1) || 1155 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { 1156 val |= LOADGEN_SELECT; 1157 } 1158 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val); 1159 } 1160 1161 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1162 val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5); 1163 val |= SUS_CLOCK_CONFIG; 1164 intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val); 1165 1166 /* 4. Clear training enable to change swing values */ 1167 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 1168 val &= ~TX_TRAINING_EN; 1169 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 1170 1171 /* 5. Program swing and de-emphasis */ 1172 cnl_ddi_vswing_program(encoder, crtc_state, level); 1173 1174 /* 6. Set training enable to trigger update */ 1175 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 1176 val |= TX_TRAINING_EN; 1177 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 1178 } 1179 1180 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1181 const struct intel_crtc_state *crtc_state, 1182 int level) 1183 { 1184 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1185 const struct cnl_ddi_buf_trans *ddi_translations; 1186 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1187 int n_entries, ln; 1188 u32 val; 1189 1190 if (DISPLAY_VER(dev_priv) >= 12) 1191 ddi_translations = tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries); 1192 else if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)) 1193 ddi_translations = jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries); 1194 else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) 1195 ddi_translations = ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries); 1196 else 1197 ddi_translations = icl_get_combo_buf_trans(encoder, crtc_state, &n_entries); 1198 1199 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 1200 return; 1201 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 1202 level = n_entries - 1; 1203 1204 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1205 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1206 1207 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1208 intel_dp->hobl_active = is_hobl_buf_trans(ddi_translations); 1209 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, 1210 intel_dp->hobl_active ? val : 0); 1211 } 1212 1213 /* Set PORT_TX_DW5 */ 1214 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 1215 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1216 TAP2_DISABLE | TAP3_DISABLE); 1217 val |= SCALING_MODE_SEL(0x2); 1218 val |= RTERM_SELECT(0x6); 1219 val |= TAP3_DISABLE; 1220 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1221 1222 /* Program PORT_TX_DW2 */ 1223 val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy)); 1224 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 1225 RCOMP_SCALAR_MASK); 1226 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); 1227 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); 1228 /* Program Rcomp scalar for every table entry */ 1229 val |= RCOMP_SCALAR(0x98); 1230 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val); 1231 1232 /* Program PORT_TX_DW4 */ 1233 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1234 for (ln = 0; ln <= 3; ln++) { 1235 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy)); 1236 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 1237 CURSOR_COEFF_MASK); 1238 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); 1239 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); 1240 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); 1241 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val); 1242 } 1243 1244 /* Program PORT_TX_DW7 */ 1245 val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy)); 1246 val &= ~N_SCALAR_MASK; 1247 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); 1248 intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val); 1249 } 1250 1251 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 1252 const struct intel_crtc_state *crtc_state, 1253 int level) 1254 { 1255 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1256 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1257 int width, rate, ln; 1258 u32 val; 1259 1260 width = crtc_state->lane_count; 1261 rate = crtc_state->port_clock; 1262 1263 /* 1264 * 1. If port type is eDP or DP, 1265 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1266 * else clear to 0b. 1267 */ 1268 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy)); 1269 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1270 val &= ~COMMON_KEEPER_EN; 1271 else 1272 val |= COMMON_KEEPER_EN; 1273 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 1274 1275 /* 2. Program loadgen select */ 1276 /* 1277 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes 1278 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1279 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1280 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1281 */ 1282 for (ln = 0; ln <= 3; ln++) { 1283 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy)); 1284 val &= ~LOADGEN_SELECT; 1285 1286 if ((rate <= 600000 && width == 4 && ln >= 1) || 1287 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { 1288 val |= LOADGEN_SELECT; 1289 } 1290 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val); 1291 } 1292 1293 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1294 val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); 1295 val |= SUS_CLOCK_CONFIG; 1296 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val); 1297 1298 /* 4. Clear training enable to change swing values */ 1299 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 1300 val &= ~TX_TRAINING_EN; 1301 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1302 1303 /* 5. Program swing and de-emphasis */ 1304 icl_ddi_combo_vswing_program(encoder, crtc_state, level); 1305 1306 /* 6. Set training enable to trigger update */ 1307 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 1308 val |= TX_TRAINING_EN; 1309 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1310 } 1311 1312 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 1313 const struct intel_crtc_state *crtc_state, 1314 int level) 1315 { 1316 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1317 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 1318 const struct icl_mg_phy_ddi_buf_trans *ddi_translations; 1319 int n_entries, ln; 1320 u32 val; 1321 1322 if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT) 1323 return; 1324 1325 ddi_translations = icl_get_mg_buf_trans(encoder, crtc_state, &n_entries); 1326 1327 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 1328 return; 1329 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 1330 level = n_entries - 1; 1331 1332 /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */ 1333 for (ln = 0; ln < 2; ln++) { 1334 val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port)); 1335 val &= ~CRI_USE_FS32; 1336 intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), val); 1337 1338 val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port)); 1339 val &= ~CRI_USE_FS32; 1340 intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), val); 1341 } 1342 1343 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1344 for (ln = 0; ln < 2; ln++) { 1345 val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port)); 1346 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; 1347 val |= CRI_TXDEEMPH_OVERRIDE_17_12( 1348 ddi_translations[level].cri_txdeemph_override_17_12); 1349 intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val); 1350 1351 val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port)); 1352 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; 1353 val |= CRI_TXDEEMPH_OVERRIDE_17_12( 1354 ddi_translations[level].cri_txdeemph_override_17_12); 1355 intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val); 1356 } 1357 1358 /* Program MG_TX_DRVCTRL with values from vswing table */ 1359 for (ln = 0; ln < 2; ln++) { 1360 val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port)); 1361 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1362 CRI_TXDEEMPH_OVERRIDE_5_0_MASK); 1363 val |= CRI_TXDEEMPH_OVERRIDE_5_0( 1364 ddi_translations[level].cri_txdeemph_override_5_0) | 1365 CRI_TXDEEMPH_OVERRIDE_11_6( 1366 ddi_translations[level].cri_txdeemph_override_11_6) | 1367 CRI_TXDEEMPH_OVERRIDE_EN; 1368 intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val); 1369 1370 val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port)); 1371 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1372 CRI_TXDEEMPH_OVERRIDE_5_0_MASK); 1373 val |= CRI_TXDEEMPH_OVERRIDE_5_0( 1374 ddi_translations[level].cri_txdeemph_override_5_0) | 1375 CRI_TXDEEMPH_OVERRIDE_11_6( 1376 ddi_translations[level].cri_txdeemph_override_11_6) | 1377 CRI_TXDEEMPH_OVERRIDE_EN; 1378 intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val); 1379 1380 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1381 } 1382 1383 /* 1384 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1385 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1386 * values from table for which TX1 and TX2 enabled. 1387 */ 1388 for (ln = 0; ln < 2; ln++) { 1389 val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port)); 1390 if (crtc_state->port_clock < 300000) 1391 val |= CFG_LOW_RATE_LKREN_EN; 1392 else 1393 val &= ~CFG_LOW_RATE_LKREN_EN; 1394 intel_de_write(dev_priv, MG_CLKHUB(ln, tc_port), val); 1395 } 1396 1397 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1398 for (ln = 0; ln < 2; ln++) { 1399 val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port)); 1400 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; 1401 if (crtc_state->port_clock <= 500000) { 1402 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; 1403 } else { 1404 val |= CFG_AMI_CK_DIV_OVERRIDE_EN | 1405 CFG_AMI_CK_DIV_OVERRIDE_VAL(1); 1406 } 1407 intel_de_write(dev_priv, MG_TX1_DCC(ln, tc_port), val); 1408 1409 val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port)); 1410 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; 1411 if (crtc_state->port_clock <= 500000) { 1412 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; 1413 } else { 1414 val |= CFG_AMI_CK_DIV_OVERRIDE_EN | 1415 CFG_AMI_CK_DIV_OVERRIDE_VAL(1); 1416 } 1417 intel_de_write(dev_priv, MG_TX2_DCC(ln, tc_port), val); 1418 } 1419 1420 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1421 for (ln = 0; ln < 2; ln++) { 1422 val = intel_de_read(dev_priv, 1423 MG_TX1_PISO_READLOAD(ln, tc_port)); 1424 val |= CRI_CALCINIT; 1425 intel_de_write(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 1426 val); 1427 1428 val = intel_de_read(dev_priv, 1429 MG_TX2_PISO_READLOAD(ln, tc_port)); 1430 val |= CRI_CALCINIT; 1431 intel_de_write(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 1432 val); 1433 } 1434 } 1435 1436 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder, 1437 const struct intel_crtc_state *crtc_state, 1438 int level) 1439 { 1440 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1441 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1442 1443 if (intel_phy_is_combo(dev_priv, phy)) 1444 icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level); 1445 else 1446 icl_mg_phy_ddi_vswing_sequence(encoder, crtc_state, level); 1447 } 1448 1449 static void 1450 tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 1451 const struct intel_crtc_state *crtc_state, 1452 int level) 1453 { 1454 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1455 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 1456 const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations; 1457 u32 val, dpcnt_mask, dpcnt_val; 1458 int n_entries, ln; 1459 1460 if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT) 1461 return; 1462 1463 if (IS_ALDERLAKE_P(dev_priv)) 1464 ddi_translations = adlp_get_dkl_buf_trans(encoder, crtc_state, &n_entries); 1465 else 1466 ddi_translations = tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries); 1467 1468 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 1469 return; 1470 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 1471 level = n_entries - 1; 1472 1473 dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK | 1474 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1475 DKL_TX_VSWING_CONTROL_MASK); 1476 dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control); 1477 dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control); 1478 dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control); 1479 1480 for (ln = 0; ln < 2; ln++) { 1481 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 1482 HIP_INDEX_VAL(tc_port, ln)); 1483 1484 intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0); 1485 1486 /* All the registers are RMW */ 1487 val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(tc_port)); 1488 val &= ~dpcnt_mask; 1489 val |= dpcnt_val; 1490 intel_de_write(dev_priv, DKL_TX_DPCNTL0(tc_port), val); 1491 1492 val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(tc_port)); 1493 val &= ~dpcnt_mask; 1494 val |= dpcnt_val; 1495 intel_de_write(dev_priv, DKL_TX_DPCNTL1(tc_port), val); 1496 1497 val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port)); 1498 val &= ~DKL_TX_DP20BITMODE; 1499 intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val); 1500 1501 if ((intel_crtc_has_dp_encoder(crtc_state) && 1502 crtc_state->port_clock == 162000) || 1503 (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 1504 crtc_state->port_clock == 594000)) 1505 val |= DKL_TX_LOADGEN_SHARING_PMD_DISABLE; 1506 else 1507 val &= ~DKL_TX_LOADGEN_SHARING_PMD_DISABLE; 1508 } 1509 } 1510 1511 static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder, 1512 const struct intel_crtc_state *crtc_state, 1513 int level) 1514 { 1515 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1516 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1517 1518 if (intel_phy_is_combo(dev_priv, phy)) 1519 icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level); 1520 else 1521 tgl_dkl_phy_ddi_vswing_sequence(encoder, crtc_state, level); 1522 } 1523 1524 static int translate_signal_level(struct intel_dp *intel_dp, 1525 u8 signal_levels) 1526 { 1527 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1528 int i; 1529 1530 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1531 if (index_to_dp_signal_levels[i] == signal_levels) 1532 return i; 1533 } 1534 1535 drm_WARN(&i915->drm, 1, 1536 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1537 signal_levels); 1538 1539 return 0; 1540 } 1541 1542 static int intel_ddi_dp_level(struct intel_dp *intel_dp) 1543 { 1544 u8 train_set = intel_dp->train_set[0]; 1545 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1546 DP_TRAIN_PRE_EMPHASIS_MASK); 1547 1548 return translate_signal_level(intel_dp, signal_levels); 1549 } 1550 1551 static void 1552 tgl_set_signal_levels(struct intel_dp *intel_dp, 1553 const struct intel_crtc_state *crtc_state) 1554 { 1555 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1556 int level = intel_ddi_dp_level(intel_dp); 1557 1558 tgl_ddi_vswing_sequence(encoder, crtc_state, level); 1559 } 1560 1561 static void 1562 icl_set_signal_levels(struct intel_dp *intel_dp, 1563 const struct intel_crtc_state *crtc_state) 1564 { 1565 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1566 int level = intel_ddi_dp_level(intel_dp); 1567 1568 icl_ddi_vswing_sequence(encoder, crtc_state, level); 1569 } 1570 1571 static void 1572 cnl_set_signal_levels(struct intel_dp *intel_dp, 1573 const struct intel_crtc_state *crtc_state) 1574 { 1575 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1576 int level = intel_ddi_dp_level(intel_dp); 1577 1578 cnl_ddi_vswing_sequence(encoder, crtc_state, level); 1579 } 1580 1581 static void 1582 bxt_set_signal_levels(struct intel_dp *intel_dp, 1583 const struct intel_crtc_state *crtc_state) 1584 { 1585 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1586 int level = intel_ddi_dp_level(intel_dp); 1587 1588 bxt_ddi_vswing_sequence(encoder, crtc_state, level); 1589 } 1590 1591 static void 1592 hsw_set_signal_levels(struct intel_dp *intel_dp, 1593 const struct intel_crtc_state *crtc_state) 1594 { 1595 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1596 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1597 int level = intel_ddi_dp_level(intel_dp); 1598 enum port port = encoder->port; 1599 u32 signal_levels; 1600 1601 signal_levels = DDI_BUF_TRANS_SELECT(level); 1602 1603 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1604 signal_levels); 1605 1606 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1607 intel_dp->DP |= signal_levels; 1608 1609 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 1610 skl_ddi_set_iboost(encoder, crtc_state, level); 1611 1612 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 1613 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 1614 } 1615 1616 static void _cnl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1617 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1618 { 1619 mutex_lock(&i915->dpll.lock); 1620 1621 intel_de_rmw(i915, reg, clk_sel_mask, clk_sel); 1622 1623 /* 1624 * "This step and the step before must be 1625 * done with separate register writes." 1626 */ 1627 intel_de_rmw(i915, reg, clk_off, 0); 1628 1629 mutex_unlock(&i915->dpll.lock); 1630 } 1631 1632 static void _cnl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1633 u32 clk_off) 1634 { 1635 mutex_lock(&i915->dpll.lock); 1636 1637 intel_de_rmw(i915, reg, 0, clk_off); 1638 1639 mutex_unlock(&i915->dpll.lock); 1640 } 1641 1642 static bool _cnl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg, 1643 u32 clk_off) 1644 { 1645 return !(intel_de_read(i915, reg) & clk_off); 1646 } 1647 1648 static struct intel_shared_dpll * 1649 _cnl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg, 1650 u32 clk_sel_mask, u32 clk_sel_shift) 1651 { 1652 enum intel_dpll_id id; 1653 1654 id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift; 1655 1656 return intel_get_shared_dpll_by_id(i915, id); 1657 } 1658 1659 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1660 const struct intel_crtc_state *crtc_state) 1661 { 1662 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1663 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1664 enum phy phy = intel_port_to_phy(i915, encoder->port); 1665 1666 if (drm_WARN_ON(&i915->drm, !pll)) 1667 return; 1668 1669 _cnl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1670 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1671 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1672 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1673 } 1674 1675 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1676 { 1677 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1678 enum phy phy = intel_port_to_phy(i915, encoder->port); 1679 1680 _cnl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1681 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1682 } 1683 1684 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1685 { 1686 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1687 enum phy phy = intel_port_to_phy(i915, encoder->port); 1688 1689 return _cnl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy), 1690 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1691 } 1692 1693 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1694 { 1695 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1696 enum phy phy = intel_port_to_phy(i915, encoder->port); 1697 1698 return _cnl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy), 1699 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1700 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1701 } 1702 1703 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1704 const struct intel_crtc_state *crtc_state) 1705 { 1706 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1707 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1708 enum phy phy = intel_port_to_phy(i915, encoder->port); 1709 1710 if (drm_WARN_ON(&i915->drm, !pll)) 1711 return; 1712 1713 _cnl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1714 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1715 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1716 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1717 } 1718 1719 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1720 { 1721 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1722 enum phy phy = intel_port_to_phy(i915, encoder->port); 1723 1724 _cnl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1725 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1726 } 1727 1728 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1729 { 1730 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1731 enum phy phy = intel_port_to_phy(i915, encoder->port); 1732 1733 return _cnl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1734 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1735 } 1736 1737 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1738 { 1739 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1740 enum phy phy = intel_port_to_phy(i915, encoder->port); 1741 1742 return _cnl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1743 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1744 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1745 } 1746 1747 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1748 const struct intel_crtc_state *crtc_state) 1749 { 1750 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1751 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1752 enum phy phy = intel_port_to_phy(i915, encoder->port); 1753 1754 if (drm_WARN_ON(&i915->drm, !pll)) 1755 return; 1756 1757 /* 1758 * If we fail this, something went very wrong: first 2 PLLs should be 1759 * used by first 2 phys and last 2 PLLs by last phys 1760 */ 1761 if (drm_WARN_ON(&i915->drm, 1762 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1763 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1764 return; 1765 1766 _cnl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1767 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1768 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1769 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1770 } 1771 1772 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1773 { 1774 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1775 enum phy phy = intel_port_to_phy(i915, encoder->port); 1776 1777 _cnl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1778 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1779 } 1780 1781 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1782 { 1783 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1784 enum phy phy = intel_port_to_phy(i915, encoder->port); 1785 1786 return _cnl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy), 1787 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1788 } 1789 1790 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1791 { 1792 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1793 enum phy phy = intel_port_to_phy(i915, encoder->port); 1794 enum intel_dpll_id id; 1795 u32 val; 1796 1797 val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy)); 1798 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1799 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1800 id = val; 1801 1802 /* 1803 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1804 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1805 * bit for phy C and D. 1806 */ 1807 if (phy >= PHY_C) 1808 id += DPLL_ID_DG1_DPLL2; 1809 1810 return intel_get_shared_dpll_by_id(i915, id); 1811 } 1812 1813 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1814 const struct intel_crtc_state *crtc_state) 1815 { 1816 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1817 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1818 enum phy phy = intel_port_to_phy(i915, encoder->port); 1819 1820 if (drm_WARN_ON(&i915->drm, !pll)) 1821 return; 1822 1823 _cnl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1824 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1825 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1826 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1827 } 1828 1829 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1830 { 1831 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1832 enum phy phy = intel_port_to_phy(i915, encoder->port); 1833 1834 _cnl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1835 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1836 } 1837 1838 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1839 { 1840 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1841 enum phy phy = intel_port_to_phy(i915, encoder->port); 1842 1843 return _cnl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1844 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1845 } 1846 1847 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1848 { 1849 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1850 enum phy phy = intel_port_to_phy(i915, encoder->port); 1851 1852 return _cnl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1853 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1854 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1855 } 1856 1857 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1858 const struct intel_crtc_state *crtc_state) 1859 { 1860 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1861 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1862 enum port port = encoder->port; 1863 1864 if (drm_WARN_ON(&i915->drm, !pll)) 1865 return; 1866 1867 /* 1868 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1869 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1870 */ 1871 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1872 1873 icl_ddi_combo_enable_clock(encoder, crtc_state); 1874 } 1875 1876 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1877 { 1878 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1879 enum port port = encoder->port; 1880 1881 icl_ddi_combo_disable_clock(encoder); 1882 1883 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1884 } 1885 1886 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1887 { 1888 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1889 enum port port = encoder->port; 1890 u32 tmp; 1891 1892 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1893 1894 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1895 return false; 1896 1897 return icl_ddi_combo_is_clock_enabled(encoder); 1898 } 1899 1900 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1901 const struct intel_crtc_state *crtc_state) 1902 { 1903 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1904 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1905 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1906 enum port port = encoder->port; 1907 1908 if (drm_WARN_ON(&i915->drm, !pll)) 1909 return; 1910 1911 intel_de_write(i915, DDI_CLK_SEL(port), 1912 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1913 1914 mutex_lock(&i915->dpll.lock); 1915 1916 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1917 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1918 1919 mutex_unlock(&i915->dpll.lock); 1920 } 1921 1922 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1923 { 1924 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1925 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1926 enum port port = encoder->port; 1927 1928 mutex_lock(&i915->dpll.lock); 1929 1930 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1931 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1932 1933 mutex_unlock(&i915->dpll.lock); 1934 1935 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1936 } 1937 1938 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1939 { 1940 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1941 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1942 enum port port = encoder->port; 1943 u32 tmp; 1944 1945 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1946 1947 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1948 return false; 1949 1950 tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0); 1951 1952 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1953 } 1954 1955 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1956 { 1957 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1958 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1959 enum port port = encoder->port; 1960 enum intel_dpll_id id; 1961 u32 tmp; 1962 1963 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1964 1965 switch (tmp & DDI_CLK_SEL_MASK) { 1966 case DDI_CLK_SEL_TBT_162: 1967 case DDI_CLK_SEL_TBT_270: 1968 case DDI_CLK_SEL_TBT_540: 1969 case DDI_CLK_SEL_TBT_810: 1970 id = DPLL_ID_ICL_TBTPLL; 1971 break; 1972 case DDI_CLK_SEL_MG: 1973 id = icl_tc_port_to_pll_id(tc_port); 1974 break; 1975 default: 1976 MISSING_CASE(tmp); 1977 fallthrough; 1978 case DDI_CLK_SEL_NONE: 1979 return NULL; 1980 } 1981 1982 return intel_get_shared_dpll_by_id(i915, id); 1983 } 1984 1985 static void cnl_ddi_enable_clock(struct intel_encoder *encoder, 1986 const struct intel_crtc_state *crtc_state) 1987 { 1988 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1989 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1990 enum port port = encoder->port; 1991 1992 if (drm_WARN_ON(&i915->drm, !pll)) 1993 return; 1994 1995 _cnl_ddi_enable_clock(i915, DPCLKA_CFGCR0, 1996 DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port), 1997 DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port), 1998 DPCLKA_CFGCR0_DDI_CLK_OFF(port)); 1999 } 2000 2001 static void cnl_ddi_disable_clock(struct intel_encoder *encoder) 2002 { 2003 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2004 enum port port = encoder->port; 2005 2006 _cnl_ddi_disable_clock(i915, DPCLKA_CFGCR0, 2007 DPCLKA_CFGCR0_DDI_CLK_OFF(port)); 2008 } 2009 2010 static bool cnl_ddi_is_clock_enabled(struct intel_encoder *encoder) 2011 { 2012 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2013 enum port port = encoder->port; 2014 2015 return _cnl_ddi_is_clock_enabled(i915, DPCLKA_CFGCR0, 2016 DPCLKA_CFGCR0_DDI_CLK_OFF(port)); 2017 } 2018 2019 static struct intel_shared_dpll *cnl_ddi_get_pll(struct intel_encoder *encoder) 2020 { 2021 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2022 enum port port = encoder->port; 2023 2024 return _cnl_ddi_get_pll(i915, DPCLKA_CFGCR0, 2025 DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port), 2026 DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)); 2027 } 2028 2029 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 2030 { 2031 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2032 enum intel_dpll_id id; 2033 2034 switch (encoder->port) { 2035 case PORT_A: 2036 id = DPLL_ID_SKL_DPLL0; 2037 break; 2038 case PORT_B: 2039 id = DPLL_ID_SKL_DPLL1; 2040 break; 2041 case PORT_C: 2042 id = DPLL_ID_SKL_DPLL2; 2043 break; 2044 default: 2045 MISSING_CASE(encoder->port); 2046 return NULL; 2047 } 2048 2049 return intel_get_shared_dpll_by_id(i915, id); 2050 } 2051 2052 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 2053 const struct intel_crtc_state *crtc_state) 2054 { 2055 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2056 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 2057 enum port port = encoder->port; 2058 2059 if (drm_WARN_ON(&i915->drm, !pll)) 2060 return; 2061 2062 mutex_lock(&i915->dpll.lock); 2063 2064 intel_de_rmw(i915, DPLL_CTRL2, 2065 DPLL_CTRL2_DDI_CLK_OFF(port) | 2066 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 2067 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 2068 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 2069 2070 mutex_unlock(&i915->dpll.lock); 2071 } 2072 2073 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 2074 { 2075 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2076 enum port port = encoder->port; 2077 2078 mutex_lock(&i915->dpll.lock); 2079 2080 intel_de_rmw(i915, DPLL_CTRL2, 2081 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 2082 2083 mutex_unlock(&i915->dpll.lock); 2084 } 2085 2086 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 2087 { 2088 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2089 enum port port = encoder->port; 2090 2091 /* 2092 * FIXME Not sure if the override affects both 2093 * the PLL selection and the CLK_OFF bit. 2094 */ 2095 return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 2096 } 2097 2098 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 2099 { 2100 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2101 enum port port = encoder->port; 2102 enum intel_dpll_id id; 2103 u32 tmp; 2104 2105 tmp = intel_de_read(i915, DPLL_CTRL2); 2106 2107 /* 2108 * FIXME Not sure if the override affects both 2109 * the PLL selection and the CLK_OFF bit. 2110 */ 2111 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 2112 return NULL; 2113 2114 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 2115 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 2116 2117 return intel_get_shared_dpll_by_id(i915, id); 2118 } 2119 2120 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 2121 const struct intel_crtc_state *crtc_state) 2122 { 2123 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2124 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 2125 enum port port = encoder->port; 2126 2127 if (drm_WARN_ON(&i915->drm, !pll)) 2128 return; 2129 2130 intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 2131 } 2132 2133 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 2134 { 2135 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2136 enum port port = encoder->port; 2137 2138 intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 2139 } 2140 2141 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 2142 { 2143 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2144 enum port port = encoder->port; 2145 2146 return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 2147 } 2148 2149 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 2150 { 2151 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2152 enum port port = encoder->port; 2153 enum intel_dpll_id id; 2154 u32 tmp; 2155 2156 tmp = intel_de_read(i915, PORT_CLK_SEL(port)); 2157 2158 switch (tmp & PORT_CLK_SEL_MASK) { 2159 case PORT_CLK_SEL_WRPLL1: 2160 id = DPLL_ID_WRPLL1; 2161 break; 2162 case PORT_CLK_SEL_WRPLL2: 2163 id = DPLL_ID_WRPLL2; 2164 break; 2165 case PORT_CLK_SEL_SPLL: 2166 id = DPLL_ID_SPLL; 2167 break; 2168 case PORT_CLK_SEL_LCPLL_810: 2169 id = DPLL_ID_LCPLL_810; 2170 break; 2171 case PORT_CLK_SEL_LCPLL_1350: 2172 id = DPLL_ID_LCPLL_1350; 2173 break; 2174 case PORT_CLK_SEL_LCPLL_2700: 2175 id = DPLL_ID_LCPLL_2700; 2176 break; 2177 default: 2178 MISSING_CASE(tmp); 2179 fallthrough; 2180 case PORT_CLK_SEL_NONE: 2181 return NULL; 2182 } 2183 2184 return intel_get_shared_dpll_by_id(i915, id); 2185 } 2186 2187 void intel_ddi_enable_clock(struct intel_encoder *encoder, 2188 const struct intel_crtc_state *crtc_state) 2189 { 2190 if (encoder->enable_clock) 2191 encoder->enable_clock(encoder, crtc_state); 2192 } 2193 2194 static void intel_ddi_disable_clock(struct intel_encoder *encoder) 2195 { 2196 if (encoder->disable_clock) 2197 encoder->disable_clock(encoder); 2198 } 2199 2200 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2201 { 2202 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2203 u32 port_mask; 2204 bool ddi_clk_needed; 2205 2206 /* 2207 * In case of DP MST, we sanitize the primary encoder only, not the 2208 * virtual ones. 2209 */ 2210 if (encoder->type == INTEL_OUTPUT_DP_MST) 2211 return; 2212 2213 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2214 u8 pipe_mask; 2215 bool is_mst; 2216 2217 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2218 /* 2219 * In the unlikely case that BIOS enables DP in MST mode, just 2220 * warn since our MST HW readout is incomplete. 2221 */ 2222 if (drm_WARN_ON(&i915->drm, is_mst)) 2223 return; 2224 } 2225 2226 port_mask = BIT(encoder->port); 2227 ddi_clk_needed = encoder->base.crtc; 2228 2229 if (encoder->type == INTEL_OUTPUT_DSI) { 2230 struct intel_encoder *other_encoder; 2231 2232 port_mask = intel_dsi_encoder_ports(encoder); 2233 /* 2234 * Sanity check that we haven't incorrectly registered another 2235 * encoder using any of the ports of this DSI encoder. 2236 */ 2237 for_each_intel_encoder(&i915->drm, other_encoder) { 2238 if (other_encoder == encoder) 2239 continue; 2240 2241 if (drm_WARN_ON(&i915->drm, 2242 port_mask & BIT(other_encoder->port))) 2243 return; 2244 } 2245 /* 2246 * For DSI we keep the ddi clocks gated 2247 * except during enable/disable sequence. 2248 */ 2249 ddi_clk_needed = false; 2250 } 2251 2252 if (ddi_clk_needed || !encoder->disable_clock || 2253 !encoder->is_clock_enabled(encoder)) 2254 return; 2255 2256 drm_notice(&i915->drm, 2257 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2258 encoder->base.base.id, encoder->base.name); 2259 2260 encoder->disable_clock(encoder); 2261 } 2262 2263 static void 2264 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2265 const struct intel_crtc_state *crtc_state) 2266 { 2267 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2268 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port); 2269 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); 2270 u32 ln0, ln1, pin_assignment; 2271 u8 width; 2272 2273 if (!intel_phy_is_tc(dev_priv, phy) || 2274 dig_port->tc_mode == TC_PORT_TBT_ALT) 2275 return; 2276 2277 if (DISPLAY_VER(dev_priv) >= 12) { 2278 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2279 HIP_INDEX_VAL(tc_port, 0x0)); 2280 ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); 2281 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2282 HIP_INDEX_VAL(tc_port, 0x1)); 2283 ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); 2284 } else { 2285 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 2286 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 2287 } 2288 2289 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2290 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2291 2292 /* DPPATC */ 2293 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 2294 width = crtc_state->lane_count; 2295 2296 switch (pin_assignment) { 2297 case 0x0: 2298 drm_WARN_ON(&dev_priv->drm, 2299 dig_port->tc_mode != TC_PORT_LEGACY); 2300 if (width == 1) { 2301 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2302 } else { 2303 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2304 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2305 } 2306 break; 2307 case 0x1: 2308 if (width == 4) { 2309 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2310 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2311 } 2312 break; 2313 case 0x2: 2314 if (width == 2) { 2315 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2316 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2317 } 2318 break; 2319 case 0x3: 2320 case 0x5: 2321 if (width == 1) { 2322 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2323 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2324 } else { 2325 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2326 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2327 } 2328 break; 2329 case 0x4: 2330 case 0x6: 2331 if (width == 1) { 2332 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2333 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2334 } else { 2335 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2336 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2337 } 2338 break; 2339 default: 2340 MISSING_CASE(pin_assignment); 2341 } 2342 2343 if (DISPLAY_VER(dev_priv) >= 12) { 2344 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2345 HIP_INDEX_VAL(tc_port, 0x0)); 2346 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0); 2347 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2348 HIP_INDEX_VAL(tc_port, 0x1)); 2349 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1); 2350 } else { 2351 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 2352 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 2353 } 2354 } 2355 2356 static enum transcoder 2357 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2358 { 2359 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2360 return crtc_state->mst_master_transcoder; 2361 else 2362 return crtc_state->cpu_transcoder; 2363 } 2364 2365 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2366 const struct intel_crtc_state *crtc_state) 2367 { 2368 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2369 2370 if (DISPLAY_VER(dev_priv) >= 12) 2371 return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state)); 2372 else 2373 return DP_TP_CTL(encoder->port); 2374 } 2375 2376 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2377 const struct intel_crtc_state *crtc_state) 2378 { 2379 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2380 2381 if (DISPLAY_VER(dev_priv) >= 12) 2382 return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state)); 2383 else 2384 return DP_TP_STATUS(encoder->port); 2385 } 2386 2387 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2388 const struct intel_crtc_state *crtc_state, 2389 bool enable) 2390 { 2391 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2392 2393 if (!crtc_state->vrr.enable) 2394 return; 2395 2396 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2397 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2398 drm_dbg_kms(&i915->drm, 2399 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2400 enabledisable(enable)); 2401 } 2402 2403 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2404 const struct intel_crtc_state *crtc_state) 2405 { 2406 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2407 2408 if (!crtc_state->fec_enable) 2409 return; 2410 2411 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0) 2412 drm_dbg_kms(&i915->drm, 2413 "Failed to set FEC_READY in the sink\n"); 2414 } 2415 2416 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2417 const struct intel_crtc_state *crtc_state) 2418 { 2419 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2420 struct intel_dp *intel_dp; 2421 u32 val; 2422 2423 if (!crtc_state->fec_enable) 2424 return; 2425 2426 intel_dp = enc_to_intel_dp(encoder); 2427 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2428 val |= DP_TP_CTL_FEC_ENABLE; 2429 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 2430 } 2431 2432 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder, 2433 const struct intel_crtc_state *crtc_state) 2434 { 2435 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2436 struct intel_dp *intel_dp; 2437 u32 val; 2438 2439 if (!crtc_state->fec_enable) 2440 return; 2441 2442 intel_dp = enc_to_intel_dp(encoder); 2443 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2444 val &= ~DP_TP_CTL_FEC_ENABLE; 2445 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 2446 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2447 } 2448 2449 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2450 const struct intel_crtc_state *crtc_state) 2451 { 2452 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2453 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2454 enum phy phy = intel_port_to_phy(i915, encoder->port); 2455 2456 if (intel_phy_is_combo(i915, phy)) { 2457 bool lane_reversal = 2458 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 2459 2460 intel_combo_phy_power_up_lanes(i915, phy, false, 2461 crtc_state->lane_count, 2462 lane_reversal); 2463 } 2464 } 2465 2466 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2467 struct intel_crtc_state *pipe_config) 2468 { 2469 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2470 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2471 enum pipe pipe = crtc->pipe; 2472 u32 dss1; 2473 2474 if (!HAS_MSO(i915)) 2475 return; 2476 2477 dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); 2478 2479 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2480 if (!pipe_config->splitter.enable) 2481 return; 2482 2483 /* Splitter enable is supported for pipe A only. */ 2484 if (drm_WARN_ON(&i915->drm, pipe != PIPE_A)) { 2485 pipe_config->splitter.enable = false; 2486 return; 2487 } 2488 2489 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2490 default: 2491 drm_WARN(&i915->drm, true, 2492 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2493 fallthrough; 2494 case SPLITTER_CONFIGURATION_2_SEGMENT: 2495 pipe_config->splitter.link_count = 2; 2496 break; 2497 case SPLITTER_CONFIGURATION_4_SEGMENT: 2498 pipe_config->splitter.link_count = 4; 2499 break; 2500 } 2501 2502 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2503 } 2504 2505 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2506 { 2507 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2508 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2509 enum pipe pipe = crtc->pipe; 2510 u32 dss1 = 0; 2511 2512 if (!HAS_MSO(i915)) 2513 return; 2514 2515 if (crtc_state->splitter.enable) { 2516 /* Splitter enable is supported for pipe A only. */ 2517 if (drm_WARN_ON(&i915->drm, pipe != PIPE_A)) 2518 return; 2519 2520 dss1 |= SPLITTER_ENABLE; 2521 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2522 if (crtc_state->splitter.link_count == 2) 2523 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2524 else 2525 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2526 } 2527 2528 intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), 2529 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2530 OVERLAP_PIXELS_MASK, dss1); 2531 } 2532 2533 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2534 struct intel_encoder *encoder, 2535 const struct intel_crtc_state *crtc_state, 2536 const struct drm_connector_state *conn_state) 2537 { 2538 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2539 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2540 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2541 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2542 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2543 int level = intel_ddi_dp_level(intel_dp); 2544 2545 intel_dp_set_link_params(intel_dp, 2546 crtc_state->port_clock, 2547 crtc_state->lane_count); 2548 2549 /* 2550 * 1. Enable Power Wells 2551 * 2552 * This was handled at the beginning of intel_atomic_commit_tail(), 2553 * before we called down into this function. 2554 */ 2555 2556 /* 2. Enable Panel Power if PPS is required */ 2557 intel_pps_on(intel_dp); 2558 2559 /* 2560 * 3. For non-TBT Type-C ports, set FIA lane count 2561 * (DFLEXDPSP.DPX4TXLATC) 2562 * 2563 * This was done before tgl_ddi_pre_enable_dp by 2564 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2565 */ 2566 2567 /* 2568 * 4. Enable the port PLL. 2569 * 2570 * The PLL enabling itself was already done before this function by 2571 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 2572 * configure the PLL to port mapping here. 2573 */ 2574 intel_ddi_enable_clock(encoder, crtc_state); 2575 2576 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2577 if (!intel_phy_is_tc(dev_priv, phy) || 2578 dig_port->tc_mode != TC_PORT_TBT_ALT) { 2579 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2580 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2581 dig_port->ddi_io_power_domain); 2582 } 2583 2584 /* 6. Program DP_MODE */ 2585 icl_program_mg_dp_mode(dig_port, crtc_state); 2586 2587 /* 2588 * 7. The rest of the below are substeps under the bspec's "Enable and 2589 * Train Display Port" step. Note that steps that are specific to 2590 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2591 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2592 * us when active_mst_links==0, so any steps designated for "single 2593 * stream or multi-stream master transcoder" can just be performed 2594 * unconditionally here. 2595 */ 2596 2597 /* 2598 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2599 * Transcoder. 2600 */ 2601 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2602 2603 /* 2604 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2605 * Transport Select 2606 */ 2607 intel_ddi_config_transcoder_func(encoder, crtc_state); 2608 2609 /* 2610 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2611 * selected 2612 * 2613 * This will be handled by the intel_dp_start_link_train() farther 2614 * down this function. 2615 */ 2616 2617 /* 7.e Configure voltage swing and related IO settings */ 2618 tgl_ddi_vswing_sequence(encoder, crtc_state, level); 2619 2620 /* 2621 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2622 * the used lanes of the DDI. 2623 */ 2624 intel_ddi_power_up_lanes(encoder, crtc_state); 2625 2626 /* 2627 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2628 */ 2629 intel_ddi_mso_configure(crtc_state); 2630 2631 /* 2632 * 7.g Configure and enable DDI_BUF_CTL 2633 * 7.h Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout 2634 * after 500 us. 2635 * 2636 * We only configure what the register value will be here. Actual 2637 * enabling happens during link training farther down. 2638 */ 2639 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2640 2641 if (!is_mst) 2642 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2643 2644 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2645 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); 2646 /* 2647 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2648 * in the FEC_CONFIGURATION register to 1 before initiating link 2649 * training 2650 */ 2651 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 2652 2653 intel_dp_check_frl_training(intel_dp); 2654 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2655 2656 /* 2657 * 7.i Follow DisplayPort specification training sequence (see notes for 2658 * failure handling) 2659 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2660 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2661 * (timeout after 800 us) 2662 */ 2663 intel_dp_start_link_train(intel_dp, crtc_state); 2664 2665 /* 7.k Set DP_TP_CTL link training to Normal */ 2666 if (!is_trans_port_sync_mode(crtc_state)) 2667 intel_dp_stop_link_train(intel_dp, crtc_state); 2668 2669 /* 7.l Configure and enable FEC if needed */ 2670 intel_ddi_enable_fec(encoder, crtc_state); 2671 if (!crtc_state->bigjoiner) 2672 intel_dsc_enable(encoder, crtc_state); 2673 } 2674 2675 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2676 struct intel_encoder *encoder, 2677 const struct intel_crtc_state *crtc_state, 2678 const struct drm_connector_state *conn_state) 2679 { 2680 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2681 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2682 enum port port = encoder->port; 2683 enum phy phy = intel_port_to_phy(dev_priv, port); 2684 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2685 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2686 int level = intel_ddi_dp_level(intel_dp); 2687 2688 if (DISPLAY_VER(dev_priv) < 11) 2689 drm_WARN_ON(&dev_priv->drm, 2690 is_mst && (port == PORT_A || port == PORT_E)); 2691 else 2692 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 2693 2694 intel_dp_set_link_params(intel_dp, 2695 crtc_state->port_clock, 2696 crtc_state->lane_count); 2697 2698 intel_pps_on(intel_dp); 2699 2700 intel_ddi_enable_clock(encoder, crtc_state); 2701 2702 if (!intel_phy_is_tc(dev_priv, phy) || 2703 dig_port->tc_mode != TC_PORT_TBT_ALT) { 2704 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2705 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2706 dig_port->ddi_io_power_domain); 2707 } 2708 2709 icl_program_mg_dp_mode(dig_port, crtc_state); 2710 2711 if (DISPLAY_VER(dev_priv) >= 11) 2712 icl_ddi_vswing_sequence(encoder, crtc_state, level); 2713 else if (IS_CANNONLAKE(dev_priv)) 2714 cnl_ddi_vswing_sequence(encoder, crtc_state, level); 2715 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 2716 bxt_ddi_vswing_sequence(encoder, crtc_state, level); 2717 else 2718 intel_prepare_dp_ddi_buffers(encoder, crtc_state); 2719 2720 intel_ddi_power_up_lanes(encoder, crtc_state); 2721 2722 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2723 if (!is_mst) 2724 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2725 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2726 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, 2727 true); 2728 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 2729 intel_dp_start_link_train(intel_dp, crtc_state); 2730 if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && 2731 !is_trans_port_sync_mode(crtc_state)) 2732 intel_dp_stop_link_train(intel_dp, crtc_state); 2733 2734 intel_ddi_enable_fec(encoder, crtc_state); 2735 2736 if (!is_mst) 2737 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2738 2739 if (!crtc_state->bigjoiner) 2740 intel_dsc_enable(encoder, crtc_state); 2741 } 2742 2743 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2744 struct intel_encoder *encoder, 2745 const struct intel_crtc_state *crtc_state, 2746 const struct drm_connector_state *conn_state) 2747 { 2748 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2749 2750 if (DISPLAY_VER(dev_priv) >= 12) 2751 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2752 else 2753 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2754 2755 /* MST will call a setting of MSA after an allocating of Virtual Channel 2756 * from MST encoder pre_enable callback. 2757 */ 2758 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 2759 intel_ddi_set_dp_msa(crtc_state, conn_state); 2760 2761 intel_dp_set_m_n(crtc_state, M1_N1); 2762 } 2763 } 2764 2765 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2766 struct intel_encoder *encoder, 2767 const struct intel_crtc_state *crtc_state, 2768 const struct drm_connector_state *conn_state) 2769 { 2770 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2771 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2772 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2773 2774 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2775 intel_ddi_enable_clock(encoder, crtc_state); 2776 2777 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2778 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2779 dig_port->ddi_io_power_domain); 2780 2781 icl_program_mg_dp_mode(dig_port, crtc_state); 2782 2783 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2784 2785 dig_port->set_infoframes(encoder, 2786 crtc_state->has_infoframe, 2787 crtc_state, conn_state); 2788 } 2789 2790 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 2791 struct intel_encoder *encoder, 2792 const struct intel_crtc_state *crtc_state, 2793 const struct drm_connector_state *conn_state) 2794 { 2795 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2796 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2797 enum pipe pipe = crtc->pipe; 2798 2799 /* 2800 * When called from DP MST code: 2801 * - conn_state will be NULL 2802 * - encoder will be the main encoder (ie. mst->primary) 2803 * - the main connector associated with this port 2804 * won't be active or linked to a crtc 2805 * - crtc_state will be the state of the first stream to 2806 * be activated on this port, and it may not be the same 2807 * stream that will be deactivated last, but each stream 2808 * should have a state that is identical when it comes to 2809 * the DP link parameteres 2810 */ 2811 2812 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 2813 2814 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2815 2816 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 2817 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 2818 conn_state); 2819 } else { 2820 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2821 2822 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 2823 conn_state); 2824 2825 /* FIXME precompute everything properly */ 2826 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) 2827 dig_port->set_infoframes(encoder, 2828 crtc_state->has_infoframe, 2829 crtc_state, conn_state); 2830 } 2831 } 2832 2833 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 2834 const struct intel_crtc_state *crtc_state) 2835 { 2836 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2837 enum port port = encoder->port; 2838 bool wait = false; 2839 u32 val; 2840 2841 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2842 if (val & DDI_BUF_CTL_ENABLE) { 2843 val &= ~DDI_BUF_CTL_ENABLE; 2844 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 2845 wait = true; 2846 } 2847 2848 if (intel_crtc_has_dp_encoder(crtc_state)) { 2849 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2850 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 2851 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 2852 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 2853 } 2854 2855 /* Disable FEC in DP Sink */ 2856 intel_ddi_disable_fec_state(encoder, crtc_state); 2857 2858 if (wait) 2859 intel_wait_ddi_buf_idle(dev_priv, port); 2860 } 2861 2862 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 2863 struct intel_encoder *encoder, 2864 const struct intel_crtc_state *old_crtc_state, 2865 const struct drm_connector_state *old_conn_state) 2866 { 2867 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2868 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2869 struct intel_dp *intel_dp = &dig_port->dp; 2870 bool is_mst = intel_crtc_has_type(old_crtc_state, 2871 INTEL_OUTPUT_DP_MST); 2872 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2873 2874 if (!is_mst) 2875 intel_dp_set_infoframes(encoder, false, 2876 old_crtc_state, old_conn_state); 2877 2878 /* 2879 * Power down sink before disabling the port, otherwise we end 2880 * up getting interrupts from the sink on detecting link loss. 2881 */ 2882 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 2883 2884 if (DISPLAY_VER(dev_priv) >= 12) { 2885 if (is_mst) { 2886 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 2887 u32 val; 2888 2889 val = intel_de_read(dev_priv, 2890 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 2891 val &= ~(TGL_TRANS_DDI_PORT_MASK | 2892 TRANS_DDI_MODE_SELECT_MASK); 2893 intel_de_write(dev_priv, 2894 TRANS_DDI_FUNC_CTL(cpu_transcoder), 2895 val); 2896 } 2897 } else { 2898 if (!is_mst) 2899 intel_ddi_disable_pipe_clock(old_crtc_state); 2900 } 2901 2902 intel_disable_ddi_buf(encoder, old_crtc_state); 2903 2904 /* 2905 * From TGL spec: "If single stream or multi-stream master transcoder: 2906 * Configure Transcoder Clock select to direct no clock to the 2907 * transcoder" 2908 */ 2909 if (DISPLAY_VER(dev_priv) >= 12) 2910 intel_ddi_disable_pipe_clock(old_crtc_state); 2911 2912 intel_pps_vdd_on(intel_dp); 2913 intel_pps_off(intel_dp); 2914 2915 if (!intel_phy_is_tc(dev_priv, phy) || 2916 dig_port->tc_mode != TC_PORT_TBT_ALT) 2917 intel_display_power_put(dev_priv, 2918 dig_port->ddi_io_power_domain, 2919 fetch_and_zero(&dig_port->ddi_io_wakeref)); 2920 2921 intel_ddi_disable_clock(encoder); 2922 } 2923 2924 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 2925 struct intel_encoder *encoder, 2926 const struct intel_crtc_state *old_crtc_state, 2927 const struct drm_connector_state *old_conn_state) 2928 { 2929 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2930 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2931 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2932 2933 dig_port->set_infoframes(encoder, false, 2934 old_crtc_state, old_conn_state); 2935 2936 intel_ddi_disable_pipe_clock(old_crtc_state); 2937 2938 intel_disable_ddi_buf(encoder, old_crtc_state); 2939 2940 intel_display_power_put(dev_priv, 2941 dig_port->ddi_io_power_domain, 2942 fetch_and_zero(&dig_port->ddi_io_wakeref)); 2943 2944 intel_ddi_disable_clock(encoder); 2945 2946 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 2947 } 2948 2949 static void intel_ddi_post_disable(struct intel_atomic_state *state, 2950 struct intel_encoder *encoder, 2951 const struct intel_crtc_state *old_crtc_state, 2952 const struct drm_connector_state *old_conn_state) 2953 { 2954 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2955 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2956 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2957 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 2958 2959 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) { 2960 intel_crtc_vblank_off(old_crtc_state); 2961 2962 intel_disable_pipe(old_crtc_state); 2963 2964 intel_vrr_disable(old_crtc_state); 2965 2966 intel_ddi_disable_transcoder_func(old_crtc_state); 2967 2968 intel_dsc_disable(old_crtc_state); 2969 2970 if (DISPLAY_VER(dev_priv) >= 9) 2971 skl_scaler_disable(old_crtc_state); 2972 else 2973 ilk_pfit_disable(old_crtc_state); 2974 } 2975 2976 if (old_crtc_state->bigjoiner_linked_crtc) { 2977 struct intel_atomic_state *state = 2978 to_intel_atomic_state(old_crtc_state->uapi.state); 2979 struct intel_crtc *slave = 2980 old_crtc_state->bigjoiner_linked_crtc; 2981 const struct intel_crtc_state *old_slave_crtc_state = 2982 intel_atomic_get_old_crtc_state(state, slave); 2983 2984 intel_crtc_vblank_off(old_slave_crtc_state); 2985 2986 intel_dsc_disable(old_slave_crtc_state); 2987 skl_scaler_disable(old_slave_crtc_state); 2988 } 2989 2990 /* 2991 * When called from DP MST code: 2992 * - old_conn_state will be NULL 2993 * - encoder will be the main encoder (ie. mst->primary) 2994 * - the main connector associated with this port 2995 * won't be active or linked to a crtc 2996 * - old_crtc_state will be the state of the last stream to 2997 * be deactivated on this port, and it may not be the same 2998 * stream that was activated last, but each stream 2999 * should have a state that is identical when it comes to 3000 * the DP link parameteres 3001 */ 3002 3003 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3004 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 3005 old_conn_state); 3006 else 3007 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 3008 old_conn_state); 3009 3010 if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port) 3011 intel_display_power_put(dev_priv, 3012 intel_ddi_main_link_aux_domain(dig_port), 3013 fetch_and_zero(&dig_port->aux_wakeref)); 3014 3015 if (is_tc_port) 3016 intel_tc_port_put_link(dig_port); 3017 } 3018 3019 void intel_ddi_fdi_post_disable(struct intel_atomic_state *state, 3020 struct intel_encoder *encoder, 3021 const struct intel_crtc_state *old_crtc_state, 3022 const struct drm_connector_state *old_conn_state) 3023 { 3024 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3025 u32 val; 3026 3027 /* 3028 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable) 3029 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN, 3030 * step 13 is the correct place for it. Step 18 is where it was 3031 * originally before the BUN. 3032 */ 3033 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 3034 val &= ~FDI_RX_ENABLE; 3035 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 3036 3037 intel_disable_ddi_buf(encoder, old_crtc_state); 3038 intel_ddi_disable_clock(encoder); 3039 3040 val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); 3041 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 3042 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 3043 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val); 3044 3045 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 3046 val &= ~FDI_PCDCLK; 3047 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 3048 3049 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 3050 val &= ~FDI_RX_PLL_ENABLE; 3051 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 3052 } 3053 3054 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 3055 struct intel_encoder *encoder, 3056 const struct intel_crtc_state *crtc_state) 3057 { 3058 const struct drm_connector_state *conn_state; 3059 struct drm_connector *conn; 3060 int i; 3061 3062 if (!crtc_state->sync_mode_slaves_mask) 3063 return; 3064 3065 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 3066 struct intel_encoder *slave_encoder = 3067 to_intel_encoder(conn_state->best_encoder); 3068 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 3069 const struct intel_crtc_state *slave_crtc_state; 3070 3071 if (!slave_crtc) 3072 continue; 3073 3074 slave_crtc_state = 3075 intel_atomic_get_new_crtc_state(state, slave_crtc); 3076 3077 if (slave_crtc_state->master_transcoder != 3078 crtc_state->cpu_transcoder) 3079 continue; 3080 3081 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 3082 slave_crtc_state); 3083 } 3084 3085 usleep_range(200, 400); 3086 3087 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 3088 crtc_state); 3089 } 3090 3091 static void intel_enable_ddi_dp(struct intel_atomic_state *state, 3092 struct intel_encoder *encoder, 3093 const struct intel_crtc_state *crtc_state, 3094 const struct drm_connector_state *conn_state) 3095 { 3096 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3097 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3098 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3099 enum port port = encoder->port; 3100 3101 if (port == PORT_A && DISPLAY_VER(dev_priv) < 9) 3102 intel_dp_stop_link_train(intel_dp, crtc_state); 3103 3104 intel_edp_backlight_on(crtc_state, conn_state); 3105 intel_psr_enable(intel_dp, crtc_state, conn_state); 3106 3107 if (!dig_port->lspcon.active || dig_port->dp.has_hdmi_sink) 3108 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3109 3110 intel_edp_drrs_enable(intel_dp, crtc_state); 3111 3112 if (crtc_state->has_audio) 3113 intel_audio_codec_enable(encoder, crtc_state, conn_state); 3114 3115 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3116 } 3117 3118 static i915_reg_t 3119 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 3120 enum port port) 3121 { 3122 static const enum transcoder trans[] = { 3123 [PORT_A] = TRANSCODER_EDP, 3124 [PORT_B] = TRANSCODER_A, 3125 [PORT_C] = TRANSCODER_B, 3126 [PORT_D] = TRANSCODER_C, 3127 [PORT_E] = TRANSCODER_A, 3128 }; 3129 3130 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9); 3131 3132 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) 3133 port = PORT_A; 3134 3135 return CHICKEN_TRANS(trans[port]); 3136 } 3137 3138 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, 3139 struct intel_encoder *encoder, 3140 const struct intel_crtc_state *crtc_state, 3141 const struct drm_connector_state *conn_state) 3142 { 3143 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3144 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3145 struct drm_connector *connector = conn_state->connector; 3146 int level = intel_ddi_hdmi_level(encoder, crtc_state); 3147 enum port port = encoder->port; 3148 3149 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3150 crtc_state->hdmi_high_tmds_clock_ratio, 3151 crtc_state->hdmi_scrambling)) 3152 drm_dbg_kms(&dev_priv->drm, 3153 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3154 connector->base.id, connector->name); 3155 3156 if (DISPLAY_VER(dev_priv) >= 12) 3157 tgl_ddi_vswing_sequence(encoder, crtc_state, level); 3158 else if (DISPLAY_VER(dev_priv) == 11) 3159 icl_ddi_vswing_sequence(encoder, crtc_state, level); 3160 else if (IS_CANNONLAKE(dev_priv)) 3161 cnl_ddi_vswing_sequence(encoder, crtc_state, level); 3162 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3163 bxt_ddi_vswing_sequence(encoder, crtc_state, level); 3164 else 3165 intel_prepare_hdmi_ddi_buffers(encoder, level); 3166 3167 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 3168 skl_ddi_set_iboost(encoder, crtc_state, level); 3169 3170 /* Display WA #1143: skl,kbl,cfl */ 3171 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { 3172 /* 3173 * For some reason these chicken bits have been 3174 * stuffed into a transcoder register, event though 3175 * the bits affect a specific DDI port rather than 3176 * a specific transcoder. 3177 */ 3178 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 3179 u32 val; 3180 3181 val = intel_de_read(dev_priv, reg); 3182 3183 if (port == PORT_E) 3184 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3185 DDIE_TRAINING_OVERRIDE_VALUE; 3186 else 3187 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3188 DDI_TRAINING_OVERRIDE_VALUE; 3189 3190 intel_de_write(dev_priv, reg, val); 3191 intel_de_posting_read(dev_priv, reg); 3192 3193 udelay(1); 3194 3195 if (port == PORT_E) 3196 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3197 DDIE_TRAINING_OVERRIDE_VALUE); 3198 else 3199 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3200 DDI_TRAINING_OVERRIDE_VALUE); 3201 3202 intel_de_write(dev_priv, reg, val); 3203 } 3204 3205 intel_ddi_power_up_lanes(encoder, crtc_state); 3206 3207 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3208 * are ignored so nothing special needs to be done besides 3209 * enabling the port. 3210 * 3211 * On ADL_P the PHY link rate and lane count must be programmed but 3212 * these are both 0 for HDMI. 3213 */ 3214 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3215 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE); 3216 3217 if (crtc_state->has_audio) 3218 intel_audio_codec_enable(encoder, crtc_state, conn_state); 3219 } 3220 3221 static void intel_enable_ddi(struct intel_atomic_state *state, 3222 struct intel_encoder *encoder, 3223 const struct intel_crtc_state *crtc_state, 3224 const struct drm_connector_state *conn_state) 3225 { 3226 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 3227 3228 if (!crtc_state->bigjoiner_slave) 3229 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3230 3231 intel_vrr_enable(encoder, crtc_state); 3232 3233 intel_enable_pipe(crtc_state); 3234 3235 intel_crtc_vblank_on(crtc_state); 3236 3237 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3238 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state); 3239 else 3240 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state); 3241 3242 /* Enable hdcp if it's desired */ 3243 if (conn_state->content_protection == 3244 DRM_MODE_CONTENT_PROTECTION_DESIRED) 3245 intel_hdcp_enable(to_intel_connector(conn_state->connector), 3246 crtc_state, 3247 (u8)conn_state->hdcp_content_type); 3248 } 3249 3250 static void intel_disable_ddi_dp(struct intel_atomic_state *state, 3251 struct intel_encoder *encoder, 3252 const struct intel_crtc_state *old_crtc_state, 3253 const struct drm_connector_state *old_conn_state) 3254 { 3255 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3256 3257 intel_dp->link_trained = false; 3258 3259 if (old_crtc_state->has_audio) 3260 intel_audio_codec_disable(encoder, 3261 old_crtc_state, old_conn_state); 3262 3263 intel_edp_drrs_disable(intel_dp, old_crtc_state); 3264 intel_psr_disable(intel_dp, old_crtc_state); 3265 intel_edp_backlight_off(old_conn_state); 3266 /* Disable the decompression in DP Sink */ 3267 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, 3268 false); 3269 /* Disable Ignore_MSA bit in DP Sink */ 3270 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 3271 false); 3272 } 3273 3274 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state, 3275 struct intel_encoder *encoder, 3276 const struct intel_crtc_state *old_crtc_state, 3277 const struct drm_connector_state *old_conn_state) 3278 { 3279 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3280 struct drm_connector *connector = old_conn_state->connector; 3281 3282 if (old_crtc_state->has_audio) 3283 intel_audio_codec_disable(encoder, 3284 old_crtc_state, old_conn_state); 3285 3286 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3287 false, false)) 3288 drm_dbg_kms(&i915->drm, 3289 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3290 connector->base.id, connector->name); 3291 } 3292 3293 static void intel_disable_ddi(struct intel_atomic_state *state, 3294 struct intel_encoder *encoder, 3295 const struct intel_crtc_state *old_crtc_state, 3296 const struct drm_connector_state *old_conn_state) 3297 { 3298 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3299 3300 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3301 intel_disable_ddi_hdmi(state, encoder, old_crtc_state, 3302 old_conn_state); 3303 else 3304 intel_disable_ddi_dp(state, encoder, old_crtc_state, 3305 old_conn_state); 3306 } 3307 3308 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3309 struct intel_encoder *encoder, 3310 const struct intel_crtc_state *crtc_state, 3311 const struct drm_connector_state *conn_state) 3312 { 3313 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3314 3315 intel_ddi_set_dp_msa(crtc_state, conn_state); 3316 3317 intel_psr_update(intel_dp, crtc_state, conn_state); 3318 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3319 intel_edp_drrs_update(intel_dp, crtc_state); 3320 3321 intel_panel_update_backlight(state, encoder, crtc_state, conn_state); 3322 } 3323 3324 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3325 struct intel_encoder *encoder, 3326 const struct intel_crtc_state *crtc_state, 3327 const struct drm_connector_state *conn_state) 3328 { 3329 3330 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3331 !intel_encoder_is_mst(encoder)) 3332 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3333 conn_state); 3334 3335 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3336 } 3337 3338 static void 3339 intel_ddi_update_prepare(struct intel_atomic_state *state, 3340 struct intel_encoder *encoder, 3341 struct intel_crtc *crtc) 3342 { 3343 struct intel_crtc_state *crtc_state = 3344 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL; 3345 int required_lanes = crtc_state ? crtc_state->lane_count : 1; 3346 3347 drm_WARN_ON(state->base.dev, crtc && crtc->active); 3348 3349 intel_tc_port_get_link(enc_to_dig_port(encoder), 3350 required_lanes); 3351 if (crtc_state && crtc_state->hw.active) 3352 intel_update_active_dpll(state, crtc, encoder); 3353 } 3354 3355 static void 3356 intel_ddi_update_complete(struct intel_atomic_state *state, 3357 struct intel_encoder *encoder, 3358 struct intel_crtc *crtc) 3359 { 3360 intel_tc_port_put_link(enc_to_dig_port(encoder)); 3361 } 3362 3363 static void 3364 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3365 struct intel_encoder *encoder, 3366 const struct intel_crtc_state *crtc_state, 3367 const struct drm_connector_state *conn_state) 3368 { 3369 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3370 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3371 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3372 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 3373 3374 if (is_tc_port) 3375 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3376 3377 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) { 3378 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref); 3379 dig_port->aux_wakeref = 3380 intel_display_power_get(dev_priv, 3381 intel_ddi_main_link_aux_domain(dig_port)); 3382 } 3383 3384 if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT) 3385 /* 3386 * Program the lane count for static/dynamic connections on 3387 * Type-C ports. Skip this step for TBT. 3388 */ 3389 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3390 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3391 bxt_ddi_phy_set_lane_optim_mask(encoder, 3392 crtc_state->lane_lat_optim_mask); 3393 } 3394 3395 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3396 const struct intel_crtc_state *crtc_state) 3397 { 3398 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3399 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3400 enum port port = encoder->port; 3401 u32 dp_tp_ctl, ddi_buf_ctl; 3402 bool wait = false; 3403 3404 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3405 3406 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 3407 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3408 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 3409 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3410 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 3411 wait = true; 3412 } 3413 3414 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 3415 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1; 3416 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3417 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3418 3419 if (wait) 3420 intel_wait_ddi_buf_idle(dev_priv, port); 3421 } 3422 3423 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3424 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3425 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3426 } else { 3427 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3428 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 3429 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3430 } 3431 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3432 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3433 3434 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3435 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3436 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3437 3438 intel_wait_ddi_buf_active(dev_priv, port); 3439 } 3440 3441 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3442 const struct intel_crtc_state *crtc_state, 3443 u8 dp_train_pat) 3444 { 3445 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3446 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3447 u32 temp; 3448 3449 temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3450 3451 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3452 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3453 case DP_TRAINING_PATTERN_DISABLE: 3454 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3455 break; 3456 case DP_TRAINING_PATTERN_1: 3457 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3458 break; 3459 case DP_TRAINING_PATTERN_2: 3460 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3461 break; 3462 case DP_TRAINING_PATTERN_3: 3463 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3464 break; 3465 case DP_TRAINING_PATTERN_4: 3466 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3467 break; 3468 } 3469 3470 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp); 3471 } 3472 3473 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3474 const struct intel_crtc_state *crtc_state) 3475 { 3476 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3477 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3478 enum port port = encoder->port; 3479 u32 val; 3480 3481 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3482 val &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3483 val |= DP_TP_CTL_LINK_TRAIN_IDLE; 3484 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 3485 3486 /* 3487 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3488 * reason we need to set idle transmission mode is to work around a HW 3489 * issue where we enable the pipe while not in idle link-training mode. 3490 * In this case there is requirement to wait for a minimum number of 3491 * idle patterns to be sent. 3492 */ 3493 if (port == PORT_A && DISPLAY_VER(dev_priv) < 12) 3494 return; 3495 3496 if (intel_de_wait_for_set(dev_priv, 3497 dp_tp_status_reg(encoder, crtc_state), 3498 DP_TP_STATUS_IDLE_DONE, 1)) 3499 drm_err(&dev_priv->drm, 3500 "Timed out waiting for DP idle patterns\n"); 3501 } 3502 3503 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 3504 enum transcoder cpu_transcoder) 3505 { 3506 if (cpu_transcoder == TRANSCODER_EDP) 3507 return false; 3508 3509 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) 3510 return false; 3511 3512 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 3513 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3514 } 3515 3516 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, 3517 struct intel_crtc_state *crtc_state) 3518 { 3519 if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000) 3520 crtc_state->min_voltage_level = 2; 3521 else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000) 3522 crtc_state->min_voltage_level = 3; 3523 else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000) 3524 crtc_state->min_voltage_level = 1; 3525 else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000) 3526 crtc_state->min_voltage_level = 2; 3527 } 3528 3529 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, 3530 enum transcoder cpu_transcoder) 3531 { 3532 u32 master_select; 3533 3534 if (DISPLAY_VER(dev_priv) >= 11) { 3535 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder)); 3536 3537 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3538 return INVALID_TRANSCODER; 3539 3540 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3541 } else { 3542 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3543 3544 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3545 return INVALID_TRANSCODER; 3546 3547 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3548 } 3549 3550 if (master_select == 0) 3551 return TRANSCODER_EDP; 3552 else 3553 return master_select - 1; 3554 } 3555 3556 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3557 { 3558 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3559 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3560 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3561 enum transcoder cpu_transcoder; 3562 3563 crtc_state->master_transcoder = 3564 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); 3565 3566 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { 3567 enum intel_display_power_domain power_domain; 3568 intel_wakeref_t trans_wakeref; 3569 3570 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3571 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 3572 power_domain); 3573 3574 if (!trans_wakeref) 3575 continue; 3576 3577 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == 3578 crtc_state->cpu_transcoder) 3579 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3580 3581 intel_display_power_put(dev_priv, power_domain, trans_wakeref); 3582 } 3583 3584 drm_WARN_ON(&dev_priv->drm, 3585 crtc_state->master_transcoder != INVALID_TRANSCODER && 3586 crtc_state->sync_mode_slaves_mask); 3587 } 3588 3589 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 3590 struct intel_crtc_state *pipe_config) 3591 { 3592 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3593 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); 3594 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3595 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3596 u32 temp, flags = 0; 3597 3598 temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3599 if (temp & TRANS_DDI_PHSYNC) 3600 flags |= DRM_MODE_FLAG_PHSYNC; 3601 else 3602 flags |= DRM_MODE_FLAG_NHSYNC; 3603 if (temp & TRANS_DDI_PVSYNC) 3604 flags |= DRM_MODE_FLAG_PVSYNC; 3605 else 3606 flags |= DRM_MODE_FLAG_NVSYNC; 3607 3608 pipe_config->hw.adjusted_mode.flags |= flags; 3609 3610 switch (temp & TRANS_DDI_BPC_MASK) { 3611 case TRANS_DDI_BPC_6: 3612 pipe_config->pipe_bpp = 18; 3613 break; 3614 case TRANS_DDI_BPC_8: 3615 pipe_config->pipe_bpp = 24; 3616 break; 3617 case TRANS_DDI_BPC_10: 3618 pipe_config->pipe_bpp = 30; 3619 break; 3620 case TRANS_DDI_BPC_12: 3621 pipe_config->pipe_bpp = 36; 3622 break; 3623 default: 3624 break; 3625 } 3626 3627 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 3628 case TRANS_DDI_MODE_SELECT_HDMI: 3629 pipe_config->has_hdmi_sink = true; 3630 3631 pipe_config->infoframes.enable |= 3632 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3633 3634 if (pipe_config->infoframes.enable) 3635 pipe_config->has_infoframe = true; 3636 3637 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 3638 pipe_config->hdmi_scrambling = true; 3639 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 3640 pipe_config->hdmi_high_tmds_clock_ratio = true; 3641 fallthrough; 3642 case TRANS_DDI_MODE_SELECT_DVI: 3643 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 3644 pipe_config->lane_count = 4; 3645 break; 3646 case TRANS_DDI_MODE_SELECT_FDI: 3647 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 3648 break; 3649 case TRANS_DDI_MODE_SELECT_DP_SST: 3650 if (encoder->type == INTEL_OUTPUT_EDP) 3651 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 3652 else 3653 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 3654 pipe_config->lane_count = 3655 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3656 intel_dp_get_m_n(intel_crtc, pipe_config); 3657 3658 if (DISPLAY_VER(dev_priv) >= 11) { 3659 i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config); 3660 3661 pipe_config->fec_enable = 3662 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE; 3663 3664 drm_dbg_kms(&dev_priv->drm, 3665 "[ENCODER:%d:%s] Fec status: %u\n", 3666 encoder->base.base.id, encoder->base.name, 3667 pipe_config->fec_enable); 3668 } 3669 3670 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) 3671 pipe_config->infoframes.enable |= 3672 intel_lspcon_infoframes_enabled(encoder, pipe_config); 3673 else 3674 pipe_config->infoframes.enable |= 3675 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3676 break; 3677 case TRANS_DDI_MODE_SELECT_DP_MST: 3678 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 3679 pipe_config->lane_count = 3680 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3681 3682 if (DISPLAY_VER(dev_priv) >= 12) 3683 pipe_config->mst_master_transcoder = 3684 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); 3685 3686 intel_dp_get_m_n(intel_crtc, pipe_config); 3687 3688 pipe_config->infoframes.enable |= 3689 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3690 break; 3691 default: 3692 break; 3693 } 3694 } 3695 3696 static void intel_ddi_get_config(struct intel_encoder *encoder, 3697 struct intel_crtc_state *pipe_config) 3698 { 3699 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3700 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3701 3702 /* XXX: DSI transcoder paranoia */ 3703 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 3704 return; 3705 3706 if (pipe_config->bigjoiner_slave) { 3707 /* read out pipe settings from master */ 3708 enum transcoder save = pipe_config->cpu_transcoder; 3709 3710 /* Our own transcoder needs to be disabled when reading it in intel_ddi_read_func_ctl() */ 3711 WARN_ON(pipe_config->output_types); 3712 pipe_config->cpu_transcoder = (enum transcoder)pipe_config->bigjoiner_linked_crtc->pipe; 3713 intel_ddi_read_func_ctl(encoder, pipe_config); 3714 pipe_config->cpu_transcoder = save; 3715 } else { 3716 intel_ddi_read_func_ctl(encoder, pipe_config); 3717 } 3718 3719 intel_ddi_mso_get_config(encoder, pipe_config); 3720 3721 pipe_config->has_audio = 3722 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 3723 3724 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp && 3725 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { 3726 /* 3727 * This is a big fat ugly hack. 3728 * 3729 * Some machines in UEFI boot mode provide us a VBT that has 18 3730 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 3731 * unknown we fail to light up. Yet the same BIOS boots up with 3732 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 3733 * max, not what it tells us to use. 3734 * 3735 * Note: This will still be broken if the eDP panel is not lit 3736 * up by the BIOS, and thus we can't get the mode at module 3737 * load. 3738 */ 3739 drm_dbg_kms(&dev_priv->drm, 3740 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 3741 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); 3742 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; 3743 } 3744 3745 if (!pipe_config->bigjoiner_slave) 3746 ddi_dotclock_get(pipe_config); 3747 3748 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3749 pipe_config->lane_lat_optim_mask = 3750 bxt_ddi_phy_get_lane_lat_optim_mask(encoder); 3751 3752 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 3753 3754 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 3755 3756 intel_read_infoframe(encoder, pipe_config, 3757 HDMI_INFOFRAME_TYPE_AVI, 3758 &pipe_config->infoframes.avi); 3759 intel_read_infoframe(encoder, pipe_config, 3760 HDMI_INFOFRAME_TYPE_SPD, 3761 &pipe_config->infoframes.spd); 3762 intel_read_infoframe(encoder, pipe_config, 3763 HDMI_INFOFRAME_TYPE_VENDOR, 3764 &pipe_config->infoframes.hdmi); 3765 intel_read_infoframe(encoder, pipe_config, 3766 HDMI_INFOFRAME_TYPE_DRM, 3767 &pipe_config->infoframes.drm); 3768 3769 if (DISPLAY_VER(dev_priv) >= 8) 3770 bdw_get_trans_port_sync_config(pipe_config); 3771 3772 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 3773 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 3774 3775 intel_psr_get_config(encoder, pipe_config); 3776 } 3777 3778 void intel_ddi_get_clock(struct intel_encoder *encoder, 3779 struct intel_crtc_state *crtc_state, 3780 struct intel_shared_dpll *pll) 3781 { 3782 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3783 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 3784 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 3785 bool pll_active; 3786 3787 if (drm_WARN_ON(&i915->drm, !pll)) 3788 return; 3789 3790 port_dpll->pll = pll; 3791 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 3792 drm_WARN_ON(&i915->drm, !pll_active); 3793 3794 icl_set_active_port_dpll(crtc_state, port_dpll_id); 3795 3796 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 3797 &crtc_state->dpll_hw_state); 3798 } 3799 3800 static void adls_ddi_get_config(struct intel_encoder *encoder, 3801 struct intel_crtc_state *crtc_state) 3802 { 3803 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 3804 intel_ddi_get_config(encoder, crtc_state); 3805 } 3806 3807 static void rkl_ddi_get_config(struct intel_encoder *encoder, 3808 struct intel_crtc_state *crtc_state) 3809 { 3810 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 3811 intel_ddi_get_config(encoder, crtc_state); 3812 } 3813 3814 static void dg1_ddi_get_config(struct intel_encoder *encoder, 3815 struct intel_crtc_state *crtc_state) 3816 { 3817 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 3818 intel_ddi_get_config(encoder, crtc_state); 3819 } 3820 3821 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 3822 struct intel_crtc_state *crtc_state) 3823 { 3824 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 3825 intel_ddi_get_config(encoder, crtc_state); 3826 } 3827 3828 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 3829 struct intel_crtc_state *crtc_state, 3830 struct intel_shared_dpll *pll) 3831 { 3832 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3833 enum icl_port_dpll_id port_dpll_id; 3834 struct icl_port_dpll *port_dpll; 3835 bool pll_active; 3836 3837 if (drm_WARN_ON(&i915->drm, !pll)) 3838 return; 3839 3840 if (intel_get_shared_dpll_id(i915, pll) == DPLL_ID_ICL_TBTPLL) 3841 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 3842 else 3843 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 3844 3845 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 3846 3847 port_dpll->pll = pll; 3848 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 3849 drm_WARN_ON(&i915->drm, !pll_active); 3850 3851 icl_set_active_port_dpll(crtc_state, port_dpll_id); 3852 3853 if (intel_get_shared_dpll_id(i915, crtc_state->shared_dpll) == DPLL_ID_ICL_TBTPLL) 3854 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port); 3855 else 3856 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 3857 &crtc_state->dpll_hw_state); 3858 } 3859 3860 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 3861 struct intel_crtc_state *crtc_state) 3862 { 3863 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 3864 intel_ddi_get_config(encoder, crtc_state); 3865 } 3866 3867 static void cnl_ddi_get_config(struct intel_encoder *encoder, 3868 struct intel_crtc_state *crtc_state) 3869 { 3870 intel_ddi_get_clock(encoder, crtc_state, cnl_ddi_get_pll(encoder)); 3871 intel_ddi_get_config(encoder, crtc_state); 3872 } 3873 3874 static void bxt_ddi_get_config(struct intel_encoder *encoder, 3875 struct intel_crtc_state *crtc_state) 3876 { 3877 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 3878 intel_ddi_get_config(encoder, crtc_state); 3879 } 3880 3881 static void skl_ddi_get_config(struct intel_encoder *encoder, 3882 struct intel_crtc_state *crtc_state) 3883 { 3884 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 3885 intel_ddi_get_config(encoder, crtc_state); 3886 } 3887 3888 void hsw_ddi_get_config(struct intel_encoder *encoder, 3889 struct intel_crtc_state *crtc_state) 3890 { 3891 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 3892 intel_ddi_get_config(encoder, crtc_state); 3893 } 3894 3895 static void intel_ddi_sync_state(struct intel_encoder *encoder, 3896 const struct intel_crtc_state *crtc_state) 3897 { 3898 if (intel_crtc_has_dp_encoder(crtc_state)) 3899 intel_dp_sync_state(encoder, crtc_state); 3900 } 3901 3902 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 3903 struct intel_crtc_state *crtc_state) 3904 { 3905 if (intel_crtc_has_dp_encoder(crtc_state)) 3906 return intel_dp_initial_fastset_check(encoder, crtc_state); 3907 3908 return true; 3909 } 3910 3911 static enum intel_output_type 3912 intel_ddi_compute_output_type(struct intel_encoder *encoder, 3913 struct intel_crtc_state *crtc_state, 3914 struct drm_connector_state *conn_state) 3915 { 3916 switch (conn_state->connector->connector_type) { 3917 case DRM_MODE_CONNECTOR_HDMIA: 3918 return INTEL_OUTPUT_HDMI; 3919 case DRM_MODE_CONNECTOR_eDP: 3920 return INTEL_OUTPUT_EDP; 3921 case DRM_MODE_CONNECTOR_DisplayPort: 3922 return INTEL_OUTPUT_DP; 3923 default: 3924 MISSING_CASE(conn_state->connector->connector_type); 3925 return INTEL_OUTPUT_UNUSED; 3926 } 3927 } 3928 3929 static int intel_ddi_compute_config(struct intel_encoder *encoder, 3930 struct intel_crtc_state *pipe_config, 3931 struct drm_connector_state *conn_state) 3932 { 3933 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3934 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3935 enum port port = encoder->port; 3936 int ret; 3937 3938 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 3939 pipe_config->cpu_transcoder = TRANSCODER_EDP; 3940 3941 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 3942 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 3943 } else { 3944 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 3945 } 3946 3947 if (ret) 3948 return ret; 3949 3950 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 3951 pipe_config->cpu_transcoder == TRANSCODER_EDP) 3952 pipe_config->pch_pfit.force_thru = 3953 pipe_config->pch_pfit.enabled || 3954 pipe_config->crc_enabled; 3955 3956 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3957 pipe_config->lane_lat_optim_mask = 3958 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 3959 3960 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 3961 3962 return 0; 3963 } 3964 3965 static bool mode_equal(const struct drm_display_mode *mode1, 3966 const struct drm_display_mode *mode2) 3967 { 3968 return drm_mode_match(mode1, mode2, 3969 DRM_MODE_MATCH_TIMINGS | 3970 DRM_MODE_MATCH_FLAGS | 3971 DRM_MODE_MATCH_3D_FLAGS) && 3972 mode1->clock == mode2->clock; /* we want an exact match */ 3973 } 3974 3975 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 3976 const struct intel_link_m_n *m_n_2) 3977 { 3978 return m_n_1->tu == m_n_2->tu && 3979 m_n_1->gmch_m == m_n_2->gmch_m && 3980 m_n_1->gmch_n == m_n_2->gmch_n && 3981 m_n_1->link_m == m_n_2->link_m && 3982 m_n_1->link_n == m_n_2->link_n; 3983 } 3984 3985 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 3986 const struct intel_crtc_state *crtc_state2) 3987 { 3988 return crtc_state1->hw.active && crtc_state2->hw.active && 3989 crtc_state1->output_types == crtc_state2->output_types && 3990 crtc_state1->output_format == crtc_state2->output_format && 3991 crtc_state1->lane_count == crtc_state2->lane_count && 3992 crtc_state1->port_clock == crtc_state2->port_clock && 3993 mode_equal(&crtc_state1->hw.adjusted_mode, 3994 &crtc_state2->hw.adjusted_mode) && 3995 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 3996 } 3997 3998 static u8 3999 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4000 int tile_group_id) 4001 { 4002 struct drm_connector *connector; 4003 const struct drm_connector_state *conn_state; 4004 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 4005 struct intel_atomic_state *state = 4006 to_intel_atomic_state(ref_crtc_state->uapi.state); 4007 u8 transcoders = 0; 4008 int i; 4009 4010 /* 4011 * We don't enable port sync on BDW due to missing w/as and 4012 * due to not having adjusted the modeset sequence appropriately. 4013 */ 4014 if (DISPLAY_VER(dev_priv) < 9) 4015 return 0; 4016 4017 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4018 return 0; 4019 4020 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4021 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4022 const struct intel_crtc_state *crtc_state; 4023 4024 if (!crtc) 4025 continue; 4026 4027 if (!connector->has_tile || 4028 connector->tile_group->id != 4029 tile_group_id) 4030 continue; 4031 crtc_state = intel_atomic_get_new_crtc_state(state, 4032 crtc); 4033 if (!crtcs_port_sync_compatible(ref_crtc_state, 4034 crtc_state)) 4035 continue; 4036 transcoders |= BIT(crtc_state->cpu_transcoder); 4037 } 4038 4039 return transcoders; 4040 } 4041 4042 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 4043 struct intel_crtc_state *crtc_state, 4044 struct drm_connector_state *conn_state) 4045 { 4046 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4047 struct drm_connector *connector = conn_state->connector; 4048 u8 port_sync_transcoders = 0; 4049 4050 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]", 4051 encoder->base.base.id, encoder->base.name, 4052 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4053 4054 if (connector->has_tile) 4055 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4056 connector->tile_group->id); 4057 4058 /* 4059 * EDP Transcoders cannot be ensalved 4060 * make them a master always when present 4061 */ 4062 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4063 crtc_state->master_transcoder = TRANSCODER_EDP; 4064 else 4065 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4066 4067 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4068 crtc_state->master_transcoder = INVALID_TRANSCODER; 4069 crtc_state->sync_mode_slaves_mask = 4070 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4071 } 4072 4073 return 0; 4074 } 4075 4076 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4077 { 4078 struct drm_i915_private *i915 = to_i915(encoder->dev); 4079 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4080 4081 intel_dp_encoder_flush_work(encoder); 4082 intel_display_power_flush_work(i915); 4083 4084 drm_encoder_cleanup(encoder); 4085 if (dig_port) 4086 kfree(dig_port->hdcp_port_data.streams); 4087 kfree(dig_port); 4088 } 4089 4090 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 4091 { 4092 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 4093 4094 intel_dp->reset_link_params = true; 4095 4096 intel_pps_encoder_reset(intel_dp); 4097 } 4098 4099 static const struct drm_encoder_funcs intel_ddi_funcs = { 4100 .reset = intel_ddi_encoder_reset, 4101 .destroy = intel_ddi_encoder_destroy, 4102 }; 4103 4104 static struct intel_connector * 4105 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 4106 { 4107 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4108 struct intel_connector *connector; 4109 enum port port = dig_port->base.port; 4110 4111 connector = intel_connector_alloc(); 4112 if (!connector) 4113 return NULL; 4114 4115 dig_port->dp.output_reg = DDI_BUF_CTL(port); 4116 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 4117 dig_port->dp.set_link_train = intel_ddi_set_link_train; 4118 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4119 4120 if (DISPLAY_VER(dev_priv) >= 12) 4121 dig_port->dp.set_signal_levels = tgl_set_signal_levels; 4122 else if (DISPLAY_VER(dev_priv) >= 11) 4123 dig_port->dp.set_signal_levels = icl_set_signal_levels; 4124 else if (IS_CANNONLAKE(dev_priv)) 4125 dig_port->dp.set_signal_levels = cnl_set_signal_levels; 4126 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4127 dig_port->dp.set_signal_levels = bxt_set_signal_levels; 4128 else 4129 dig_port->dp.set_signal_levels = hsw_set_signal_levels; 4130 4131 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 4132 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 4133 4134 if (!intel_dp_init_connector(dig_port, connector)) { 4135 kfree(connector); 4136 return NULL; 4137 } 4138 4139 return connector; 4140 } 4141 4142 static int modeset_pipe(struct drm_crtc *crtc, 4143 struct drm_modeset_acquire_ctx *ctx) 4144 { 4145 struct drm_atomic_state *state; 4146 struct drm_crtc_state *crtc_state; 4147 int ret; 4148 4149 state = drm_atomic_state_alloc(crtc->dev); 4150 if (!state) 4151 return -ENOMEM; 4152 4153 state->acquire_ctx = ctx; 4154 4155 crtc_state = drm_atomic_get_crtc_state(state, crtc); 4156 if (IS_ERR(crtc_state)) { 4157 ret = PTR_ERR(crtc_state); 4158 goto out; 4159 } 4160 4161 crtc_state->connectors_changed = true; 4162 4163 ret = drm_atomic_commit(state); 4164 out: 4165 drm_atomic_state_put(state); 4166 4167 return ret; 4168 } 4169 4170 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4171 struct drm_modeset_acquire_ctx *ctx) 4172 { 4173 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4174 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4175 struct intel_connector *connector = hdmi->attached_connector; 4176 struct i2c_adapter *adapter = 4177 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 4178 struct drm_connector_state *conn_state; 4179 struct intel_crtc_state *crtc_state; 4180 struct intel_crtc *crtc; 4181 u8 config; 4182 int ret; 4183 4184 if (!connector || connector->base.status != connector_status_connected) 4185 return 0; 4186 4187 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 4188 ctx); 4189 if (ret) 4190 return ret; 4191 4192 conn_state = connector->base.state; 4193 4194 crtc = to_intel_crtc(conn_state->crtc); 4195 if (!crtc) 4196 return 0; 4197 4198 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4199 if (ret) 4200 return ret; 4201 4202 crtc_state = to_intel_crtc_state(crtc->base.state); 4203 4204 drm_WARN_ON(&dev_priv->drm, 4205 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4206 4207 if (!crtc_state->hw.active) 4208 return 0; 4209 4210 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4211 !crtc_state->hdmi_scrambling) 4212 return 0; 4213 4214 if (conn_state->commit && 4215 !try_wait_for_completion(&conn_state->commit->hw_done)) 4216 return 0; 4217 4218 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 4219 if (ret < 0) { 4220 drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n", 4221 ret); 4222 return 0; 4223 } 4224 4225 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4226 crtc_state->hdmi_high_tmds_clock_ratio && 4227 !!(config & SCDC_SCRAMBLING_ENABLE) == 4228 crtc_state->hdmi_scrambling) 4229 return 0; 4230 4231 /* 4232 * HDMI 2.0 says that one should not send scrambled data 4233 * prior to configuring the sink scrambling, and that 4234 * TMDS clock/data transmission should be suspended when 4235 * changing the TMDS clock rate in the sink. So let's 4236 * just do a full modeset here, even though some sinks 4237 * would be perfectly happy if were to just reconfigure 4238 * the SCDC settings on the fly. 4239 */ 4240 return modeset_pipe(&crtc->base, ctx); 4241 } 4242 4243 static enum intel_hotplug_state 4244 intel_ddi_hotplug(struct intel_encoder *encoder, 4245 struct intel_connector *connector) 4246 { 4247 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4248 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4249 struct intel_dp *intel_dp = &dig_port->dp; 4250 enum phy phy = intel_port_to_phy(i915, encoder->port); 4251 bool is_tc = intel_phy_is_tc(i915, phy); 4252 struct drm_modeset_acquire_ctx ctx; 4253 enum intel_hotplug_state state; 4254 int ret; 4255 4256 if (intel_dp->compliance.test_active && 4257 intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) { 4258 intel_dp_phy_test(encoder); 4259 /* just do the PHY test and nothing else */ 4260 return INTEL_HOTPLUG_UNCHANGED; 4261 } 4262 4263 state = intel_encoder_hotplug(encoder, connector); 4264 4265 drm_modeset_acquire_init(&ctx, 0); 4266 4267 for (;;) { 4268 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) 4269 ret = intel_hdmi_reset_link(encoder, &ctx); 4270 else 4271 ret = intel_dp_retrain_link(encoder, &ctx); 4272 4273 if (ret == -EDEADLK) { 4274 drm_modeset_backoff(&ctx); 4275 continue; 4276 } 4277 4278 break; 4279 } 4280 4281 drm_modeset_drop_locks(&ctx); 4282 drm_modeset_acquire_fini(&ctx); 4283 drm_WARN(encoder->base.dev, ret, 4284 "Acquiring modeset locks failed with %i\n", ret); 4285 4286 /* 4287 * Unpowered type-c dongles can take some time to boot and be 4288 * responsible, so here giving some time to those dongles to power up 4289 * and then retrying the probe. 4290 * 4291 * On many platforms the HDMI live state signal is known to be 4292 * unreliable, so we can't use it to detect if a sink is connected or 4293 * not. Instead we detect if it's connected based on whether we can 4294 * read the EDID or not. That in turn has a problem during disconnect, 4295 * since the HPD interrupt may be raised before the DDC lines get 4296 * disconnected (due to how the required length of DDC vs. HPD 4297 * connector pins are specified) and so we'll still be able to get a 4298 * valid EDID. To solve this schedule another detection cycle if this 4299 * time around we didn't detect any change in the sink's connection 4300 * status. 4301 * 4302 * Type-c connectors which get their HPD signal deasserted then 4303 * reasserted, without unplugging/replugging the sink from the 4304 * connector, introduce a delay until the AUX channel communication 4305 * becomes functional. Retry the detection for 5 seconds on type-c 4306 * connectors to account for this delay. 4307 */ 4308 if (state == INTEL_HOTPLUG_UNCHANGED && 4309 connector->hotplug_retries < (is_tc ? 5 : 1) && 4310 !dig_port->dp.is_mst) 4311 state = INTEL_HOTPLUG_RETRY; 4312 4313 return state; 4314 } 4315 4316 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4317 { 4318 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4319 u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin]; 4320 4321 return intel_de_read(dev_priv, SDEISR) & bit; 4322 } 4323 4324 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4325 { 4326 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4327 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; 4328 4329 return intel_de_read(dev_priv, DEISR) & bit; 4330 } 4331 4332 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4333 { 4334 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4335 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; 4336 4337 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; 4338 } 4339 4340 static struct intel_connector * 4341 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4342 { 4343 struct intel_connector *connector; 4344 enum port port = dig_port->base.port; 4345 4346 connector = intel_connector_alloc(); 4347 if (!connector) 4348 return NULL; 4349 4350 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4351 intel_hdmi_init_connector(dig_port, connector); 4352 4353 return connector; 4354 } 4355 4356 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4357 { 4358 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4359 4360 if (dig_port->base.port != PORT_A) 4361 return false; 4362 4363 if (dig_port->saved_port_bits & DDI_A_4_LANES) 4364 return false; 4365 4366 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4367 * supported configuration 4368 */ 4369 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4370 return true; 4371 4372 /* Cannonlake: Most of SKUs don't support DDI_E, and the only 4373 * one who does also have a full A/E split called 4374 * DDI_F what makes DDI_E useless. However for this 4375 * case let's trust VBT info. 4376 */ 4377 if (IS_CANNONLAKE(dev_priv) && 4378 !intel_bios_is_port_present(dev_priv, PORT_E)) 4379 return true; 4380 4381 return false; 4382 } 4383 4384 static int 4385 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4386 { 4387 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4388 enum port port = dig_port->base.port; 4389 int max_lanes = 4; 4390 4391 if (DISPLAY_VER(dev_priv) >= 11) 4392 return max_lanes; 4393 4394 if (port == PORT_A || port == PORT_E) { 4395 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4396 max_lanes = port == PORT_A ? 4 : 0; 4397 else 4398 /* Both A and E share 2 lanes */ 4399 max_lanes = 2; 4400 } 4401 4402 /* 4403 * Some BIOS might fail to set this bit on port A if eDP 4404 * wasn't lit up at boot. Force this bit set when needed 4405 * so we use the proper lane count for our calculations. 4406 */ 4407 if (intel_ddi_a_force_4_lanes(dig_port)) { 4408 drm_dbg_kms(&dev_priv->drm, 4409 "Forcing DDI_A_4_LANES for port A\n"); 4410 dig_port->saved_port_bits |= DDI_A_4_LANES; 4411 max_lanes = 4; 4412 } 4413 4414 return max_lanes; 4415 } 4416 4417 static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy) 4418 { 4419 return i915->hti_state & HDPORT_ENABLED && 4420 i915->hti_state & HDPORT_DDI_USED(phy); 4421 } 4422 4423 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv, 4424 enum port port) 4425 { 4426 if (port >= PORT_D_XELPD) 4427 return HPD_PORT_D + port - PORT_D_XELPD; 4428 else if (port >= PORT_TC1) 4429 return HPD_PORT_TC1 + port - PORT_TC1; 4430 else 4431 return HPD_PORT_A + port - PORT_A; 4432 } 4433 4434 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, 4435 enum port port) 4436 { 4437 if (port >= PORT_TC1) 4438 return HPD_PORT_C + port - PORT_TC1; 4439 else 4440 return HPD_PORT_A + port - PORT_A; 4441 } 4442 4443 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, 4444 enum port port) 4445 { 4446 if (port >= PORT_TC1) 4447 return HPD_PORT_TC1 + port - PORT_TC1; 4448 else 4449 return HPD_PORT_A + port - PORT_A; 4450 } 4451 4452 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, 4453 enum port port) 4454 { 4455 if (HAS_PCH_TGP(dev_priv)) 4456 return tgl_hpd_pin(dev_priv, port); 4457 4458 if (port >= PORT_TC1) 4459 return HPD_PORT_C + port - PORT_TC1; 4460 else 4461 return HPD_PORT_A + port - PORT_A; 4462 } 4463 4464 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, 4465 enum port port) 4466 { 4467 if (port >= PORT_C) 4468 return HPD_PORT_TC1 + port - PORT_C; 4469 else 4470 return HPD_PORT_A + port - PORT_A; 4471 } 4472 4473 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, 4474 enum port port) 4475 { 4476 if (port == PORT_D) 4477 return HPD_PORT_A; 4478 4479 if (HAS_PCH_MCC(dev_priv)) 4480 return icl_hpd_pin(dev_priv, port); 4481 4482 return HPD_PORT_A + port - PORT_A; 4483 } 4484 4485 static enum hpd_pin cnl_hpd_pin(struct drm_i915_private *dev_priv, 4486 enum port port) 4487 { 4488 if (port == PORT_F) 4489 return HPD_PORT_E; 4490 4491 return HPD_PORT_A + port - PORT_A; 4492 } 4493 4494 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) 4495 { 4496 if (HAS_PCH_TGP(dev_priv)) 4497 return icl_hpd_pin(dev_priv, port); 4498 4499 return HPD_PORT_A + port - PORT_A; 4500 } 4501 4502 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port) 4503 { 4504 if (DISPLAY_VER(i915) >= 12) 4505 return port >= PORT_TC1; 4506 else if (DISPLAY_VER(i915) >= 11) 4507 return port >= PORT_C; 4508 else 4509 return false; 4510 } 4511 4512 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 4513 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 4514 4515 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 4516 { 4517 struct intel_digital_port *dig_port; 4518 struct intel_encoder *encoder; 4519 const struct intel_bios_encoder_data *devdata; 4520 bool init_hdmi, init_dp; 4521 enum phy phy = intel_port_to_phy(dev_priv, port); 4522 4523 /* 4524 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 4525 * have taken over some of the PHYs and made them unavailable to the 4526 * driver. In that case we should skip initializing the corresponding 4527 * outputs. 4528 */ 4529 if (hti_uses_phy(dev_priv, phy)) { 4530 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", 4531 port_name(port), phy_name(phy)); 4532 return; 4533 } 4534 4535 devdata = intel_bios_encoder_data_lookup(dev_priv, port); 4536 if (!devdata) { 4537 drm_dbg_kms(&dev_priv->drm, 4538 "VBT says port %c is not present\n", 4539 port_name(port)); 4540 return; 4541 } 4542 4543 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 4544 intel_bios_encoder_supports_hdmi(devdata); 4545 init_dp = intel_bios_encoder_supports_dp(devdata); 4546 4547 if (intel_bios_is_lspcon_present(dev_priv, port)) { 4548 /* 4549 * Lspcon device needs to be driven with DP connector 4550 * with special detection sequence. So make sure DP 4551 * is initialized before lspcon. 4552 */ 4553 init_dp = true; 4554 init_hdmi = false; 4555 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", 4556 port_name(port)); 4557 } 4558 4559 if (!init_dp && !init_hdmi) { 4560 drm_dbg_kms(&dev_priv->drm, 4561 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 4562 port_name(port)); 4563 return; 4564 } 4565 4566 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 4567 if (!dig_port) 4568 return; 4569 4570 encoder = &dig_port->base; 4571 encoder->devdata = devdata; 4572 4573 if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) { 4574 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4575 DRM_MODE_ENCODER_TMDS, 4576 "DDI %c/PHY %c", 4577 port_name(port - PORT_D_XELPD + PORT_D), 4578 phy_name(phy)); 4579 } else if (DISPLAY_VER(dev_priv) >= 12) { 4580 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4581 4582 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4583 DRM_MODE_ENCODER_TMDS, 4584 "DDI %s%c/PHY %s%c", 4585 port >= PORT_TC1 ? "TC" : "", 4586 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 4587 tc_port != TC_PORT_NONE ? "TC" : "", 4588 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4589 } else if (DISPLAY_VER(dev_priv) >= 11) { 4590 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4591 4592 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4593 DRM_MODE_ENCODER_TMDS, 4594 "DDI %c%s/PHY %s%c", 4595 port_name(port), 4596 port >= PORT_C ? " (TC)" : "", 4597 tc_port != TC_PORT_NONE ? "TC" : "", 4598 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4599 } else { 4600 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4601 DRM_MODE_ENCODER_TMDS, 4602 "DDI %c/PHY %c", port_name(port), phy_name(phy)); 4603 } 4604 4605 mutex_init(&dig_port->hdcp_mutex); 4606 dig_port->num_hdcp_streams = 0; 4607 4608 encoder->hotplug = intel_ddi_hotplug; 4609 encoder->compute_output_type = intel_ddi_compute_output_type; 4610 encoder->compute_config = intel_ddi_compute_config; 4611 encoder->compute_config_late = intel_ddi_compute_config_late; 4612 encoder->enable = intel_enable_ddi; 4613 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 4614 encoder->pre_enable = intel_ddi_pre_enable; 4615 encoder->disable = intel_disable_ddi; 4616 encoder->post_disable = intel_ddi_post_disable; 4617 encoder->update_pipe = intel_ddi_update_pipe; 4618 encoder->get_hw_state = intel_ddi_get_hw_state; 4619 encoder->sync_state = intel_ddi_sync_state; 4620 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 4621 encoder->suspend = intel_dp_encoder_suspend; 4622 encoder->shutdown = intel_dp_encoder_shutdown; 4623 encoder->get_power_domains = intel_ddi_get_power_domains; 4624 4625 encoder->type = INTEL_OUTPUT_DDI; 4626 encoder->power_domain = intel_port_to_power_domain(port); 4627 encoder->port = port; 4628 encoder->cloneable = 0; 4629 encoder->pipe_mask = ~0; 4630 4631 if (IS_ALDERLAKE_S(dev_priv)) { 4632 encoder->enable_clock = adls_ddi_enable_clock; 4633 encoder->disable_clock = adls_ddi_disable_clock; 4634 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 4635 encoder->get_config = adls_ddi_get_config; 4636 } else if (IS_ROCKETLAKE(dev_priv)) { 4637 encoder->enable_clock = rkl_ddi_enable_clock; 4638 encoder->disable_clock = rkl_ddi_disable_clock; 4639 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 4640 encoder->get_config = rkl_ddi_get_config; 4641 } else if (IS_DG1(dev_priv)) { 4642 encoder->enable_clock = dg1_ddi_enable_clock; 4643 encoder->disable_clock = dg1_ddi_disable_clock; 4644 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 4645 encoder->get_config = dg1_ddi_get_config; 4646 } else if (IS_JSL_EHL(dev_priv)) { 4647 if (intel_ddi_is_tc(dev_priv, port)) { 4648 encoder->enable_clock = jsl_ddi_tc_enable_clock; 4649 encoder->disable_clock = jsl_ddi_tc_disable_clock; 4650 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 4651 encoder->get_config = icl_ddi_combo_get_config; 4652 } else { 4653 encoder->enable_clock = icl_ddi_combo_enable_clock; 4654 encoder->disable_clock = icl_ddi_combo_disable_clock; 4655 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 4656 encoder->get_config = icl_ddi_combo_get_config; 4657 } 4658 } else if (DISPLAY_VER(dev_priv) >= 11) { 4659 if (intel_ddi_is_tc(dev_priv, port)) { 4660 encoder->enable_clock = icl_ddi_tc_enable_clock; 4661 encoder->disable_clock = icl_ddi_tc_disable_clock; 4662 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 4663 encoder->get_config = icl_ddi_tc_get_config; 4664 } else { 4665 encoder->enable_clock = icl_ddi_combo_enable_clock; 4666 encoder->disable_clock = icl_ddi_combo_disable_clock; 4667 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 4668 encoder->get_config = icl_ddi_combo_get_config; 4669 } 4670 } else if (IS_CANNONLAKE(dev_priv)) { 4671 encoder->enable_clock = cnl_ddi_enable_clock; 4672 encoder->disable_clock = cnl_ddi_disable_clock; 4673 encoder->is_clock_enabled = cnl_ddi_is_clock_enabled; 4674 encoder->get_config = cnl_ddi_get_config; 4675 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 4676 /* BXT/GLK have fixed PLL->port mapping */ 4677 encoder->get_config = bxt_ddi_get_config; 4678 } else if (DISPLAY_VER(dev_priv) == 9) { 4679 encoder->enable_clock = skl_ddi_enable_clock; 4680 encoder->disable_clock = skl_ddi_disable_clock; 4681 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 4682 encoder->get_config = skl_ddi_get_config; 4683 } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 4684 encoder->enable_clock = hsw_ddi_enable_clock; 4685 encoder->disable_clock = hsw_ddi_disable_clock; 4686 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 4687 encoder->get_config = hsw_ddi_get_config; 4688 } 4689 4690 if (DISPLAY_VER(dev_priv) >= 13) 4691 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port); 4692 else if (IS_DG1(dev_priv)) 4693 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); 4694 else if (IS_ROCKETLAKE(dev_priv)) 4695 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); 4696 else if (DISPLAY_VER(dev_priv) >= 12) 4697 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); 4698 else if (IS_JSL_EHL(dev_priv)) 4699 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); 4700 else if (DISPLAY_VER(dev_priv) == 11) 4701 encoder->hpd_pin = icl_hpd_pin(dev_priv, port); 4702 else if (IS_CANNONLAKE(dev_priv)) 4703 encoder->hpd_pin = cnl_hpd_pin(dev_priv, port); 4704 else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 4705 encoder->hpd_pin = skl_hpd_pin(dev_priv, port); 4706 else 4707 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 4708 4709 if (DISPLAY_VER(dev_priv) >= 11) 4710 dig_port->saved_port_bits = 4711 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 4712 & DDI_BUF_PORT_REVERSAL; 4713 else 4714 dig_port->saved_port_bits = 4715 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 4716 & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 4717 4718 if (intel_bios_is_lane_reversal_needed(dev_priv, port)) 4719 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL; 4720 4721 dig_port->dp.output_reg = INVALID_MMIO_REG; 4722 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 4723 dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 4724 4725 if (intel_phy_is_tc(dev_priv, phy)) { 4726 bool is_legacy = 4727 !intel_bios_encoder_supports_typec_usb(devdata) && 4728 !intel_bios_encoder_supports_tbt(devdata); 4729 4730 intel_tc_port_init(dig_port, is_legacy); 4731 4732 encoder->update_prepare = intel_ddi_update_prepare; 4733 encoder->update_complete = intel_ddi_update_complete; 4734 } 4735 4736 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 4737 dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO + 4738 port - PORT_A; 4739 4740 if (init_dp) { 4741 if (!intel_ddi_init_dp_connector(dig_port)) 4742 goto err; 4743 4744 dig_port->hpd_pulse = intel_dp_hpd_pulse; 4745 4746 /* Splitter enable for eDP MSO is limited to certain pipes. */ 4747 if (dig_port->dp.mso_link_count) { 4748 encoder->pipe_mask = BIT(PIPE_A); 4749 if (IS_ALDERLAKE_P(dev_priv)) 4750 encoder->pipe_mask |= BIT(PIPE_B); 4751 } 4752 } 4753 4754 /* In theory we don't need the encoder->type check, but leave it just in 4755 * case we have some really bad VBTs... */ 4756 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 4757 if (!intel_ddi_init_hdmi_connector(dig_port)) 4758 goto err; 4759 } 4760 4761 if (DISPLAY_VER(dev_priv) >= 11) { 4762 if (intel_phy_is_tc(dev_priv, phy)) 4763 dig_port->connected = intel_tc_port_connected; 4764 else 4765 dig_port->connected = lpt_digital_port_connected; 4766 } else if (DISPLAY_VER(dev_priv) >= 8) { 4767 if (port == PORT_A || IS_GEMINILAKE(dev_priv) || 4768 IS_BROXTON(dev_priv)) 4769 dig_port->connected = bdw_digital_port_connected; 4770 else 4771 dig_port->connected = lpt_digital_port_connected; 4772 } else { 4773 if (port == PORT_A) 4774 dig_port->connected = hsw_digital_port_connected; 4775 else 4776 dig_port->connected = lpt_digital_port_connected; 4777 } 4778 4779 intel_infoframe_init(dig_port); 4780 4781 return; 4782 4783 err: 4784 drm_encoder_cleanup(&encoder->base); 4785 kfree(dig_port); 4786 } 4787