1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <linux/string_helpers.h> 29 30 #include <drm/display/drm_scdc_helper.h> 31 #include <drm/drm_privacy_screen_consumer.h> 32 33 #include "i915_drv.h" 34 #include "i915_reg.h" 35 #include "intel_audio.h" 36 #include "intel_audio_regs.h" 37 #include "intel_backlight.h" 38 #include "intel_combo_phy.h" 39 #include "intel_combo_phy_regs.h" 40 #include "intel_connector.h" 41 #include "intel_crtc.h" 42 #include "intel_ddi.h" 43 #include "intel_ddi_buf_trans.h" 44 #include "intel_de.h" 45 #include "intel_display_power.h" 46 #include "intel_display_types.h" 47 #include "intel_dkl_phy.h" 48 #include "intel_dkl_phy_regs.h" 49 #include "intel_dp.h" 50 #include "intel_dp_link_training.h" 51 #include "intel_dp_mst.h" 52 #include "intel_dpio_phy.h" 53 #include "intel_dsi.h" 54 #include "intel_fdi.h" 55 #include "intel_fifo_underrun.h" 56 #include "intel_gmbus.h" 57 #include "intel_hdcp.h" 58 #include "intel_hdmi.h" 59 #include "intel_hotplug.h" 60 #include "intel_hti.h" 61 #include "intel_lspcon.h" 62 #include "intel_mg_phy_regs.h" 63 #include "intel_pps.h" 64 #include "intel_psr.h" 65 #include "intel_quirks.h" 66 #include "intel_snps_phy.h" 67 #include "intel_sprite.h" 68 #include "intel_tc.h" 69 #include "intel_vdsc.h" 70 #include "intel_vrr.h" 71 #include "skl_scaler.h" 72 #include "skl_universal_plane.h" 73 74 static const u8 index_to_dp_signal_levels[] = { 75 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 76 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 77 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 78 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 79 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 80 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 81 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 82 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 83 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 84 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 85 }; 86 87 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 88 const struct intel_ddi_buf_trans *trans) 89 { 90 int level; 91 92 level = intel_bios_hdmi_level_shift(encoder); 93 if (level < 0) 94 level = trans->hdmi_default_entry; 95 96 return level; 97 } 98 99 static bool has_buf_trans_select(struct drm_i915_private *i915) 100 { 101 return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915); 102 } 103 104 static bool has_iboost(struct drm_i915_private *i915) 105 { 106 return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915); 107 } 108 109 /* 110 * Starting with Haswell, DDI port buffers must be programmed with correct 111 * values in advance. This function programs the correct values for 112 * DP/eDP/FDI use cases. 113 */ 114 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 115 const struct intel_crtc_state *crtc_state) 116 { 117 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 118 u32 iboost_bit = 0; 119 int i, n_entries; 120 enum port port = encoder->port; 121 const struct intel_ddi_buf_trans *trans; 122 123 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 124 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 125 return; 126 127 /* If we're boosting the current, set bit 31 of trans1 */ 128 if (has_iboost(dev_priv) && 129 intel_bios_encoder_dp_boost_level(encoder->devdata)) 130 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 131 132 for (i = 0; i < n_entries; i++) { 133 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 134 trans->entries[i].hsw.trans1 | iboost_bit); 135 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 136 trans->entries[i].hsw.trans2); 137 } 138 } 139 140 /* 141 * Starting with Haswell, DDI port buffers must be programmed with correct 142 * values in advance. This function programs the correct values for 143 * HDMI/DVI use cases. 144 */ 145 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 146 const struct intel_crtc_state *crtc_state) 147 { 148 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 149 int level = intel_ddi_level(encoder, crtc_state, 0); 150 u32 iboost_bit = 0; 151 int n_entries; 152 enum port port = encoder->port; 153 const struct intel_ddi_buf_trans *trans; 154 155 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 156 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 157 return; 158 159 /* If we're boosting the current, set bit 31 of trans1 */ 160 if (has_iboost(dev_priv) && 161 intel_bios_encoder_hdmi_boost_level(encoder->devdata)) 162 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 163 164 /* Entry 9 is for HDMI: */ 165 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 166 trans->entries[level].hsw.trans1 | iboost_bit); 167 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 168 trans->entries[level].hsw.trans2); 169 } 170 171 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 172 enum port port) 173 { 174 if (IS_BROXTON(dev_priv)) { 175 udelay(16); 176 return; 177 } 178 179 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 180 DDI_BUF_IS_IDLE), 8)) 181 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", 182 port_name(port)); 183 } 184 185 static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, 186 enum port port) 187 { 188 int ret; 189 190 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ 191 if (DISPLAY_VER(dev_priv) < 10) { 192 usleep_range(518, 1000); 193 return; 194 } 195 196 ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 197 DDI_BUF_IS_IDLE), IS_DG2(dev_priv) ? 1200 : 500, 10, 10); 198 199 if (ret) 200 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", 201 port_name(port)); 202 } 203 204 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 205 { 206 switch (pll->info->id) { 207 case DPLL_ID_WRPLL1: 208 return PORT_CLK_SEL_WRPLL1; 209 case DPLL_ID_WRPLL2: 210 return PORT_CLK_SEL_WRPLL2; 211 case DPLL_ID_SPLL: 212 return PORT_CLK_SEL_SPLL; 213 case DPLL_ID_LCPLL_810: 214 return PORT_CLK_SEL_LCPLL_810; 215 case DPLL_ID_LCPLL_1350: 216 return PORT_CLK_SEL_LCPLL_1350; 217 case DPLL_ID_LCPLL_2700: 218 return PORT_CLK_SEL_LCPLL_2700; 219 default: 220 MISSING_CASE(pll->info->id); 221 return PORT_CLK_SEL_NONE; 222 } 223 } 224 225 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 226 const struct intel_crtc_state *crtc_state) 227 { 228 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 229 int clock = crtc_state->port_clock; 230 const enum intel_dpll_id id = pll->info->id; 231 232 switch (id) { 233 default: 234 /* 235 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 236 * here, so do warn if this get passed in 237 */ 238 MISSING_CASE(id); 239 return DDI_CLK_SEL_NONE; 240 case DPLL_ID_ICL_TBTPLL: 241 switch (clock) { 242 case 162000: 243 return DDI_CLK_SEL_TBT_162; 244 case 270000: 245 return DDI_CLK_SEL_TBT_270; 246 case 540000: 247 return DDI_CLK_SEL_TBT_540; 248 case 810000: 249 return DDI_CLK_SEL_TBT_810; 250 default: 251 MISSING_CASE(clock); 252 return DDI_CLK_SEL_NONE; 253 } 254 case DPLL_ID_ICL_MGPLL1: 255 case DPLL_ID_ICL_MGPLL2: 256 case DPLL_ID_ICL_MGPLL3: 257 case DPLL_ID_ICL_MGPLL4: 258 case DPLL_ID_TGL_MGPLL5: 259 case DPLL_ID_TGL_MGPLL6: 260 return DDI_CLK_SEL_MG; 261 } 262 } 263 264 static u32 ddi_buf_phy_link_rate(int port_clock) 265 { 266 switch (port_clock) { 267 case 162000: 268 return DDI_BUF_PHY_LINK_RATE(0); 269 case 216000: 270 return DDI_BUF_PHY_LINK_RATE(4); 271 case 243000: 272 return DDI_BUF_PHY_LINK_RATE(5); 273 case 270000: 274 return DDI_BUF_PHY_LINK_RATE(1); 275 case 324000: 276 return DDI_BUF_PHY_LINK_RATE(6); 277 case 432000: 278 return DDI_BUF_PHY_LINK_RATE(7); 279 case 540000: 280 return DDI_BUF_PHY_LINK_RATE(2); 281 case 810000: 282 return DDI_BUF_PHY_LINK_RATE(3); 283 default: 284 MISSING_CASE(port_clock); 285 return DDI_BUF_PHY_LINK_RATE(0); 286 } 287 } 288 289 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 290 const struct intel_crtc_state *crtc_state) 291 { 292 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 293 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 294 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 295 enum phy phy = intel_port_to_phy(i915, encoder->port); 296 297 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 298 intel_dp->DP = dig_port->saved_port_bits | 299 DDI_PORT_WIDTH(crtc_state->lane_count) | 300 DDI_BUF_TRANS_SELECT(0); 301 302 if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) { 303 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 304 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 305 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 306 } 307 } 308 309 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 310 enum port port) 311 { 312 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 313 314 switch (val) { 315 case DDI_CLK_SEL_NONE: 316 return 0; 317 case DDI_CLK_SEL_TBT_162: 318 return 162000; 319 case DDI_CLK_SEL_TBT_270: 320 return 270000; 321 case DDI_CLK_SEL_TBT_540: 322 return 540000; 323 case DDI_CLK_SEL_TBT_810: 324 return 810000; 325 default: 326 MISSING_CASE(val); 327 return 0; 328 } 329 } 330 331 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 332 { 333 /* CRT dotclock is determined via other means */ 334 if (pipe_config->has_pch_encoder) 335 return; 336 337 pipe_config->hw.adjusted_mode.crtc_clock = 338 intel_crtc_dotclock(pipe_config); 339 } 340 341 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 342 const struct drm_connector_state *conn_state) 343 { 344 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 345 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 346 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 347 u32 temp; 348 349 if (!intel_crtc_has_dp_encoder(crtc_state)) 350 return; 351 352 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 353 354 temp = DP_MSA_MISC_SYNC_CLOCK; 355 356 switch (crtc_state->pipe_bpp) { 357 case 18: 358 temp |= DP_MSA_MISC_6_BPC; 359 break; 360 case 24: 361 temp |= DP_MSA_MISC_8_BPC; 362 break; 363 case 30: 364 temp |= DP_MSA_MISC_10_BPC; 365 break; 366 case 36: 367 temp |= DP_MSA_MISC_12_BPC; 368 break; 369 default: 370 MISSING_CASE(crtc_state->pipe_bpp); 371 break; 372 } 373 374 /* nonsense combination */ 375 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 376 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 377 378 if (crtc_state->limited_color_range) 379 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 380 381 /* 382 * As per DP 1.2 spec section 2.3.4.3 while sending 383 * YCBCR 444 signals we should program MSA MISC1/0 fields with 384 * colorspace information. 385 */ 386 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 387 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 388 389 /* 390 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 391 * of Color Encoding Format and Content Color Gamut] while sending 392 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 393 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 394 */ 395 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 396 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 397 398 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp); 399 } 400 401 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 402 { 403 if (master_transcoder == TRANSCODER_EDP) 404 return 0; 405 else 406 return master_transcoder + 1; 407 } 408 409 static void 410 intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder, 411 const struct intel_crtc_state *crtc_state) 412 { 413 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 414 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 415 u32 val = 0; 416 417 if (intel_dp_is_uhbr(crtc_state)) 418 val = TRANS_DP2_128B132B_CHANNEL_CODING; 419 420 intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val); 421 } 422 423 /* 424 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 425 * 426 * Only intended to be used by intel_ddi_enable_transcoder_func() and 427 * intel_ddi_config_transcoder_func(). 428 */ 429 static u32 430 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 431 const struct intel_crtc_state *crtc_state) 432 { 433 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 434 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 435 enum pipe pipe = crtc->pipe; 436 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 437 enum port port = encoder->port; 438 u32 temp; 439 440 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 441 temp = TRANS_DDI_FUNC_ENABLE; 442 if (DISPLAY_VER(dev_priv) >= 12) 443 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 444 else 445 temp |= TRANS_DDI_SELECT_PORT(port); 446 447 switch (crtc_state->pipe_bpp) { 448 default: 449 MISSING_CASE(crtc_state->pipe_bpp); 450 fallthrough; 451 case 18: 452 temp |= TRANS_DDI_BPC_6; 453 break; 454 case 24: 455 temp |= TRANS_DDI_BPC_8; 456 break; 457 case 30: 458 temp |= TRANS_DDI_BPC_10; 459 break; 460 case 36: 461 temp |= TRANS_DDI_BPC_12; 462 break; 463 } 464 465 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 466 temp |= TRANS_DDI_PVSYNC; 467 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 468 temp |= TRANS_DDI_PHSYNC; 469 470 if (cpu_transcoder == TRANSCODER_EDP) { 471 switch (pipe) { 472 default: 473 MISSING_CASE(pipe); 474 fallthrough; 475 case PIPE_A: 476 /* On Haswell, can only use the always-on power well for 477 * eDP when not using the panel fitter, and when not 478 * using motion blur mitigation (which we don't 479 * support). */ 480 if (crtc_state->pch_pfit.force_thru) 481 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 482 else 483 temp |= TRANS_DDI_EDP_INPUT_A_ON; 484 break; 485 case PIPE_B: 486 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 487 break; 488 case PIPE_C: 489 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 490 break; 491 } 492 } 493 494 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 495 if (crtc_state->has_hdmi_sink) 496 temp |= TRANS_DDI_MODE_SELECT_HDMI; 497 else 498 temp |= TRANS_DDI_MODE_SELECT_DVI; 499 500 if (crtc_state->hdmi_scrambling) 501 temp |= TRANS_DDI_HDMI_SCRAMBLING; 502 if (crtc_state->hdmi_high_tmds_clock_ratio) 503 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 504 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 505 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 506 temp |= (crtc_state->fdi_lanes - 1) << 1; 507 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 508 if (intel_dp_is_uhbr(crtc_state)) 509 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 510 else 511 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 512 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 513 514 if (DISPLAY_VER(dev_priv) >= 12) { 515 enum transcoder master; 516 517 master = crtc_state->mst_master_transcoder; 518 drm_WARN_ON(&dev_priv->drm, 519 master == INVALID_TRANSCODER); 520 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 521 } 522 } else { 523 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 524 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 525 } 526 527 if (IS_DISPLAY_VER(dev_priv, 8, 10) && 528 crtc_state->master_transcoder != INVALID_TRANSCODER) { 529 u8 master_select = 530 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 531 532 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 533 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 534 } 535 536 return temp; 537 } 538 539 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 540 const struct intel_crtc_state *crtc_state) 541 { 542 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 543 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 544 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 545 546 if (DISPLAY_VER(dev_priv) >= 11) { 547 enum transcoder master_transcoder = crtc_state->master_transcoder; 548 u32 ctl2 = 0; 549 550 if (master_transcoder != INVALID_TRANSCODER) { 551 u8 master_select = 552 bdw_trans_port_sync_master_select(master_transcoder); 553 554 ctl2 |= PORT_SYNC_MODE_ENABLE | 555 PORT_SYNC_MODE_MASTER_SELECT(master_select); 556 } 557 558 intel_de_write(dev_priv, 559 TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2); 560 } 561 562 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 563 intel_ddi_transcoder_func_reg_val_get(encoder, 564 crtc_state)); 565 } 566 567 /* 568 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 569 * bit. 570 */ 571 static void 572 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 573 const struct intel_crtc_state *crtc_state) 574 { 575 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 576 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 577 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 578 u32 ctl; 579 580 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 581 ctl &= ~TRANS_DDI_FUNC_ENABLE; 582 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 583 } 584 585 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 586 { 587 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 588 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 589 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 590 u32 ctl; 591 592 if (DISPLAY_VER(dev_priv) >= 11) 593 intel_de_write(dev_priv, 594 TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0); 595 596 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 597 598 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 599 600 ctl &= ~TRANS_DDI_FUNC_ENABLE; 601 602 if (IS_DISPLAY_VER(dev_priv, 8, 10)) 603 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 604 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 605 606 if (DISPLAY_VER(dev_priv) >= 12) { 607 if (!intel_dp_mst_is_master_trans(crtc_state)) { 608 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 609 TRANS_DDI_MODE_SELECT_MASK); 610 } 611 } else { 612 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 613 } 614 615 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 616 617 if (intel_has_quirk(dev_priv, QUIRK_INCREASE_DDI_DISABLED_TIME) && 618 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 619 drm_dbg_kms(&dev_priv->drm, 620 "Quirk Increase DDI disabled time\n"); 621 /* Quirk time at 100ms for reliable operation */ 622 msleep(100); 623 } 624 } 625 626 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 627 enum transcoder cpu_transcoder, 628 bool enable, u32 hdcp_mask) 629 { 630 struct drm_device *dev = intel_encoder->base.dev; 631 struct drm_i915_private *dev_priv = to_i915(dev); 632 intel_wakeref_t wakeref; 633 int ret = 0; 634 u32 tmp; 635 636 wakeref = intel_display_power_get_if_enabled(dev_priv, 637 intel_encoder->power_domain); 638 if (drm_WARN_ON(dev, !wakeref)) 639 return -ENXIO; 640 641 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 642 if (enable) 643 tmp |= hdcp_mask; 644 else 645 tmp &= ~hdcp_mask; 646 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp); 647 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 648 return ret; 649 } 650 651 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 652 { 653 struct drm_device *dev = intel_connector->base.dev; 654 struct drm_i915_private *dev_priv = to_i915(dev); 655 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 656 int type = intel_connector->base.connector_type; 657 enum port port = encoder->port; 658 enum transcoder cpu_transcoder; 659 intel_wakeref_t wakeref; 660 enum pipe pipe = 0; 661 u32 tmp; 662 bool ret; 663 664 wakeref = intel_display_power_get_if_enabled(dev_priv, 665 encoder->power_domain); 666 if (!wakeref) 667 return false; 668 669 if (!encoder->get_hw_state(encoder, &pipe)) { 670 ret = false; 671 goto out; 672 } 673 674 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 675 cpu_transcoder = TRANSCODER_EDP; 676 else 677 cpu_transcoder = (enum transcoder) pipe; 678 679 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 680 681 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 682 case TRANS_DDI_MODE_SELECT_HDMI: 683 case TRANS_DDI_MODE_SELECT_DVI: 684 ret = type == DRM_MODE_CONNECTOR_HDMIA; 685 break; 686 687 case TRANS_DDI_MODE_SELECT_DP_SST: 688 ret = type == DRM_MODE_CONNECTOR_eDP || 689 type == DRM_MODE_CONNECTOR_DisplayPort; 690 break; 691 692 case TRANS_DDI_MODE_SELECT_DP_MST: 693 /* if the transcoder is in MST state then 694 * connector isn't connected */ 695 ret = false; 696 break; 697 698 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 699 if (HAS_DP20(dev_priv)) 700 /* 128b/132b */ 701 ret = false; 702 else 703 /* FDI */ 704 ret = type == DRM_MODE_CONNECTOR_VGA; 705 break; 706 707 default: 708 ret = false; 709 break; 710 } 711 712 out: 713 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 714 715 return ret; 716 } 717 718 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 719 u8 *pipe_mask, bool *is_dp_mst) 720 { 721 struct drm_device *dev = encoder->base.dev; 722 struct drm_i915_private *dev_priv = to_i915(dev); 723 enum port port = encoder->port; 724 intel_wakeref_t wakeref; 725 enum pipe p; 726 u32 tmp; 727 u8 mst_pipe_mask; 728 729 *pipe_mask = 0; 730 *is_dp_mst = false; 731 732 wakeref = intel_display_power_get_if_enabled(dev_priv, 733 encoder->power_domain); 734 if (!wakeref) 735 return; 736 737 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 738 if (!(tmp & DDI_BUF_CTL_ENABLE)) 739 goto out; 740 741 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { 742 tmp = intel_de_read(dev_priv, 743 TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 744 745 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 746 default: 747 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 748 fallthrough; 749 case TRANS_DDI_EDP_INPUT_A_ON: 750 case TRANS_DDI_EDP_INPUT_A_ONOFF: 751 *pipe_mask = BIT(PIPE_A); 752 break; 753 case TRANS_DDI_EDP_INPUT_B_ONOFF: 754 *pipe_mask = BIT(PIPE_B); 755 break; 756 case TRANS_DDI_EDP_INPUT_C_ONOFF: 757 *pipe_mask = BIT(PIPE_C); 758 break; 759 } 760 761 goto out; 762 } 763 764 mst_pipe_mask = 0; 765 for_each_pipe(dev_priv, p) { 766 enum transcoder cpu_transcoder = (enum transcoder)p; 767 unsigned int port_mask, ddi_select; 768 intel_wakeref_t trans_wakeref; 769 770 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 771 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 772 if (!trans_wakeref) 773 continue; 774 775 if (DISPLAY_VER(dev_priv) >= 12) { 776 port_mask = TGL_TRANS_DDI_PORT_MASK; 777 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 778 } else { 779 port_mask = TRANS_DDI_PORT_MASK; 780 ddi_select = TRANS_DDI_SELECT_PORT(port); 781 } 782 783 tmp = intel_de_read(dev_priv, 784 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 785 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 786 trans_wakeref); 787 788 if ((tmp & port_mask) != ddi_select) 789 continue; 790 791 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST || 792 (HAS_DP20(dev_priv) && 793 (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B)) 794 mst_pipe_mask |= BIT(p); 795 796 *pipe_mask |= BIT(p); 797 } 798 799 if (!*pipe_mask) 800 drm_dbg_kms(&dev_priv->drm, 801 "No pipe for [ENCODER:%d:%s] found\n", 802 encoder->base.base.id, encoder->base.name); 803 804 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 805 drm_dbg_kms(&dev_priv->drm, 806 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 807 encoder->base.base.id, encoder->base.name, 808 *pipe_mask); 809 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 810 } 811 812 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 813 drm_dbg_kms(&dev_priv->drm, 814 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", 815 encoder->base.base.id, encoder->base.name, 816 *pipe_mask, mst_pipe_mask); 817 else 818 *is_dp_mst = mst_pipe_mask; 819 820 out: 821 if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) { 822 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 823 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 824 BXT_PHY_LANE_POWERDOWN_ACK | 825 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 826 drm_err(&dev_priv->drm, 827 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 828 encoder->base.base.id, encoder->base.name, tmp); 829 } 830 831 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 832 } 833 834 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 835 enum pipe *pipe) 836 { 837 u8 pipe_mask; 838 bool is_mst; 839 840 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 841 842 if (is_mst || !pipe_mask) 843 return false; 844 845 *pipe = ffs(pipe_mask) - 1; 846 847 return true; 848 } 849 850 static enum intel_display_power_domain 851 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port, 852 const struct intel_crtc_state *crtc_state) 853 { 854 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 855 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 856 857 /* 858 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 859 * DC states enabled at the same time, while for driver initiated AUX 860 * transfers we need the same AUX IOs to be powered but with DC states 861 * disabled. Accordingly use the AUX_IO_<port> power domain here which 862 * leaves DC states enabled. 863 * 864 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require 865 * AUX IO to be enabled, but all these require DC_OFF to be enabled as 866 * well, so we can acquire a wider AUX_<port> power domain reference 867 * instead of a specific AUX_IO_<port> reference without powering up any 868 * extra wells. 869 */ 870 if (intel_encoder_can_psr(&dig_port->base)) 871 return intel_display_power_aux_io_domain(i915, dig_port->aux_ch); 872 else if (DISPLAY_VER(i915) < 14 && 873 (intel_crtc_has_dp_encoder(crtc_state) || 874 intel_phy_is_tc(i915, phy))) 875 return intel_aux_power_domain(dig_port); 876 else 877 return POWER_DOMAIN_INVALID; 878 } 879 880 static void 881 main_link_aux_power_domain_get(struct intel_digital_port *dig_port, 882 const struct intel_crtc_state *crtc_state) 883 { 884 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 885 enum intel_display_power_domain domain = 886 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 887 888 drm_WARN_ON(&i915->drm, dig_port->aux_wakeref); 889 890 if (domain == POWER_DOMAIN_INVALID) 891 return; 892 893 dig_port->aux_wakeref = intel_display_power_get(i915, domain); 894 } 895 896 static void 897 main_link_aux_power_domain_put(struct intel_digital_port *dig_port, 898 const struct intel_crtc_state *crtc_state) 899 { 900 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 901 enum intel_display_power_domain domain = 902 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 903 intel_wakeref_t wf; 904 905 wf = fetch_and_zero(&dig_port->aux_wakeref); 906 if (!wf) 907 return; 908 909 intel_display_power_put(i915, domain, wf); 910 } 911 912 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 913 struct intel_crtc_state *crtc_state) 914 { 915 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 916 struct intel_digital_port *dig_port; 917 918 /* 919 * TODO: Add support for MST encoders. Atm, the following should never 920 * happen since fake-MST encoders don't set their get_power_domains() 921 * hook. 922 */ 923 if (drm_WARN_ON(&dev_priv->drm, 924 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 925 return; 926 927 dig_port = enc_to_dig_port(encoder); 928 929 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 930 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 931 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 932 dig_port->ddi_io_power_domain); 933 } 934 935 main_link_aux_power_domain_get(dig_port, crtc_state); 936 } 937 938 void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder, 939 const struct intel_crtc_state *crtc_state) 940 { 941 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 942 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 943 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 944 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 945 u32 val; 946 947 if (cpu_transcoder != TRANSCODER_EDP) { 948 if (DISPLAY_VER(dev_priv) >= 13) 949 val = TGL_TRANS_CLK_SEL_PORT(phy); 950 else if (DISPLAY_VER(dev_priv) >= 12) 951 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 952 else 953 val = TRANS_CLK_SEL_PORT(encoder->port); 954 955 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 956 } 957 } 958 959 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state) 960 { 961 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 962 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 963 964 if (cpu_transcoder != TRANSCODER_EDP) { 965 if (DISPLAY_VER(dev_priv) >= 12) 966 intel_de_write(dev_priv, 967 TRANS_CLK_SEL(cpu_transcoder), 968 TGL_TRANS_CLK_SEL_DISABLED); 969 else 970 intel_de_write(dev_priv, 971 TRANS_CLK_SEL(cpu_transcoder), 972 TRANS_CLK_SEL_DISABLED); 973 } 974 } 975 976 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 977 enum port port, u8 iboost) 978 { 979 u32 tmp; 980 981 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 982 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 983 if (iboost) 984 tmp |= iboost << BALANCE_LEG_SHIFT(port); 985 else 986 tmp |= BALANCE_LEG_DISABLE(port); 987 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 988 } 989 990 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 991 const struct intel_crtc_state *crtc_state, 992 int level) 993 { 994 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 995 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 996 u8 iboost; 997 998 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 999 iboost = intel_bios_encoder_hdmi_boost_level(encoder->devdata); 1000 else 1001 iboost = intel_bios_encoder_dp_boost_level(encoder->devdata); 1002 1003 if (iboost == 0) { 1004 const struct intel_ddi_buf_trans *trans; 1005 int n_entries; 1006 1007 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1008 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1009 return; 1010 1011 iboost = trans->entries[level].hsw.i_boost; 1012 } 1013 1014 /* Make sure that the requested I_boost is valid */ 1015 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 1016 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); 1017 return; 1018 } 1019 1020 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); 1021 1022 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 1023 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 1024 } 1025 1026 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1027 const struct intel_crtc_state *crtc_state) 1028 { 1029 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1030 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1031 int n_entries; 1032 1033 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1034 1035 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 1036 n_entries = 1; 1037 if (drm_WARN_ON(&dev_priv->drm, 1038 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1039 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1040 1041 return index_to_dp_signal_levels[n_entries - 1] & 1042 DP_TRAIN_VOLTAGE_SWING_MASK; 1043 } 1044 1045 /* 1046 * We assume that the full set of pre-emphasis values can be 1047 * used on all DDI platforms. Should that change we need to 1048 * rethink this code. 1049 */ 1050 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1051 { 1052 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1053 } 1054 1055 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1056 int lane) 1057 { 1058 if (crtc_state->port_clock > 600000) 1059 return 0; 1060 1061 if (crtc_state->lane_count == 4) 1062 return lane >= 1 ? LOADGEN_SELECT : 0; 1063 else 1064 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1065 } 1066 1067 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1068 const struct intel_crtc_state *crtc_state) 1069 { 1070 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1071 const struct intel_ddi_buf_trans *trans; 1072 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1073 int n_entries, ln; 1074 u32 val; 1075 1076 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1077 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1078 return; 1079 1080 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1081 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1082 1083 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1084 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1085 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, 1086 intel_dp->hobl_active ? val : 0); 1087 } 1088 1089 /* Set PORT_TX_DW5 */ 1090 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1091 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1092 TAP2_DISABLE | TAP3_DISABLE); 1093 val |= SCALING_MODE_SEL(0x2); 1094 val |= RTERM_SELECT(0x6); 1095 val |= TAP3_DISABLE; 1096 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1097 1098 /* Program PORT_TX_DW2 */ 1099 for (ln = 0; ln < 4; ln++) { 1100 int level = intel_ddi_level(encoder, crtc_state, ln); 1101 1102 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy), 1103 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1104 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1105 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1106 RCOMP_SCALAR(0x98)); 1107 } 1108 1109 /* Program PORT_TX_DW4 */ 1110 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1111 for (ln = 0; ln < 4; ln++) { 1112 int level = intel_ddi_level(encoder, crtc_state, ln); 1113 1114 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1115 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1116 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1117 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1118 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1119 } 1120 1121 /* Program PORT_TX_DW7 */ 1122 for (ln = 0; ln < 4; ln++) { 1123 int level = intel_ddi_level(encoder, crtc_state, ln); 1124 1125 intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy), 1126 N_SCALAR_MASK, 1127 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1128 } 1129 } 1130 1131 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1132 const struct intel_crtc_state *crtc_state) 1133 { 1134 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1135 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1136 u32 val; 1137 int ln; 1138 1139 /* 1140 * 1. If port type is eDP or DP, 1141 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1142 * else clear to 0b. 1143 */ 1144 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); 1145 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1146 val &= ~COMMON_KEEPER_EN; 1147 else 1148 val |= COMMON_KEEPER_EN; 1149 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 1150 1151 /* 2. Program loadgen select */ 1152 /* 1153 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1154 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1155 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1156 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1157 */ 1158 for (ln = 0; ln < 4; ln++) { 1159 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1160 LOADGEN_SELECT, 1161 icl_combo_phy_loadgen_select(crtc_state, ln)); 1162 } 1163 1164 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1165 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 1166 0, SUS_CLOCK_CONFIG); 1167 1168 /* 4. Clear training enable to change swing values */ 1169 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1170 val &= ~TX_TRAINING_EN; 1171 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1172 1173 /* 5. Program swing and de-emphasis */ 1174 icl_ddi_combo_vswing_program(encoder, crtc_state); 1175 1176 /* 6. Set training enable to trigger update */ 1177 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1178 val |= TX_TRAINING_EN; 1179 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1180 } 1181 1182 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1183 const struct intel_crtc_state *crtc_state) 1184 { 1185 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1186 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 1187 const struct intel_ddi_buf_trans *trans; 1188 int n_entries, ln; 1189 1190 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1191 return; 1192 1193 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1194 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1195 return; 1196 1197 for (ln = 0; ln < 2; ln++) { 1198 intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), 1199 CRI_USE_FS32, 0); 1200 intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), 1201 CRI_USE_FS32, 0); 1202 } 1203 1204 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1205 for (ln = 0; ln < 2; ln++) { 1206 int level; 1207 1208 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1209 1210 intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), 1211 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1212 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1213 1214 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1215 1216 intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), 1217 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1218 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1219 } 1220 1221 /* Program MG_TX_DRVCTRL with values from vswing table */ 1222 for (ln = 0; ln < 2; ln++) { 1223 int level; 1224 1225 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1226 1227 intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), 1228 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1229 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1230 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1231 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1232 CRI_TXDEEMPH_OVERRIDE_EN); 1233 1234 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1235 1236 intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), 1237 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1238 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1239 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1240 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1241 CRI_TXDEEMPH_OVERRIDE_EN); 1242 1243 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1244 } 1245 1246 /* 1247 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1248 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1249 * values from table for which TX1 and TX2 enabled. 1250 */ 1251 for (ln = 0; ln < 2; ln++) { 1252 intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port), 1253 CFG_LOW_RATE_LKREN_EN, 1254 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1255 } 1256 1257 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1258 for (ln = 0; ln < 2; ln++) { 1259 intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port), 1260 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1261 CFG_AMI_CK_DIV_OVERRIDE_EN, 1262 crtc_state->port_clock > 500000 ? 1263 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1264 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1265 1266 intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port), 1267 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1268 CFG_AMI_CK_DIV_OVERRIDE_EN, 1269 crtc_state->port_clock > 500000 ? 1270 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1271 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1272 } 1273 1274 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1275 for (ln = 0; ln < 2; ln++) { 1276 intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 1277 0, CRI_CALCINIT); 1278 intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 1279 0, CRI_CALCINIT); 1280 } 1281 } 1282 1283 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1284 const struct intel_crtc_state *crtc_state) 1285 { 1286 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1287 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 1288 const struct intel_ddi_buf_trans *trans; 1289 int n_entries, ln; 1290 1291 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1292 return; 1293 1294 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1295 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1296 return; 1297 1298 for (ln = 0; ln < 2; ln++) { 1299 int level; 1300 1301 intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); 1302 1303 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1304 1305 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln), 1306 DKL_TX_PRESHOOT_COEFF_MASK | 1307 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1308 DKL_TX_VSWING_CONTROL_MASK, 1309 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1310 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1311 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1312 1313 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1314 1315 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln), 1316 DKL_TX_PRESHOOT_COEFF_MASK | 1317 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1318 DKL_TX_VSWING_CONTROL_MASK, 1319 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1320 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1321 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1322 1323 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1324 DKL_TX_DP20BITMODE, 0); 1325 1326 if (IS_ALDERLAKE_P(dev_priv)) { 1327 u32 val; 1328 1329 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1330 if (ln == 0) { 1331 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1332 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); 1333 } else { 1334 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); 1335 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); 1336 } 1337 } else { 1338 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1339 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); 1340 } 1341 1342 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1343 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | 1344 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, 1345 val); 1346 } 1347 } 1348 } 1349 1350 static int translate_signal_level(struct intel_dp *intel_dp, 1351 u8 signal_levels) 1352 { 1353 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1354 int i; 1355 1356 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1357 if (index_to_dp_signal_levels[i] == signal_levels) 1358 return i; 1359 } 1360 1361 drm_WARN(&i915->drm, 1, 1362 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1363 signal_levels); 1364 1365 return 0; 1366 } 1367 1368 static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1369 const struct intel_crtc_state *crtc_state, 1370 int lane) 1371 { 1372 u8 train_set = intel_dp->train_set[lane]; 1373 1374 if (intel_dp_is_uhbr(crtc_state)) { 1375 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1376 } else { 1377 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1378 DP_TRAIN_PRE_EMPHASIS_MASK); 1379 1380 return translate_signal_level(intel_dp, signal_levels); 1381 } 1382 } 1383 1384 int intel_ddi_level(struct intel_encoder *encoder, 1385 const struct intel_crtc_state *crtc_state, 1386 int lane) 1387 { 1388 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1389 const struct intel_ddi_buf_trans *trans; 1390 int level, n_entries; 1391 1392 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1393 if (drm_WARN_ON_ONCE(&i915->drm, !trans)) 1394 return 0; 1395 1396 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1397 level = intel_ddi_hdmi_level(encoder, trans); 1398 else 1399 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1400 lane); 1401 1402 if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries)) 1403 level = n_entries - 1; 1404 1405 return level; 1406 } 1407 1408 static void 1409 hsw_set_signal_levels(struct intel_encoder *encoder, 1410 const struct intel_crtc_state *crtc_state) 1411 { 1412 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1413 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1414 int level = intel_ddi_level(encoder, crtc_state, 0); 1415 enum port port = encoder->port; 1416 u32 signal_levels; 1417 1418 if (has_iboost(dev_priv)) 1419 skl_ddi_set_iboost(encoder, crtc_state, level); 1420 1421 /* HDMI ignores the rest */ 1422 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1423 return; 1424 1425 signal_levels = DDI_BUF_TRANS_SELECT(level); 1426 1427 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1428 signal_levels); 1429 1430 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1431 intel_dp->DP |= signal_levels; 1432 1433 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 1434 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 1435 } 1436 1437 static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1438 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1439 { 1440 mutex_lock(&i915->display.dpll.lock); 1441 1442 intel_de_rmw(i915, reg, clk_sel_mask, clk_sel); 1443 1444 /* 1445 * "This step and the step before must be 1446 * done with separate register writes." 1447 */ 1448 intel_de_rmw(i915, reg, clk_off, 0); 1449 1450 mutex_unlock(&i915->display.dpll.lock); 1451 } 1452 1453 static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1454 u32 clk_off) 1455 { 1456 mutex_lock(&i915->display.dpll.lock); 1457 1458 intel_de_rmw(i915, reg, 0, clk_off); 1459 1460 mutex_unlock(&i915->display.dpll.lock); 1461 } 1462 1463 static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg, 1464 u32 clk_off) 1465 { 1466 return !(intel_de_read(i915, reg) & clk_off); 1467 } 1468 1469 static struct intel_shared_dpll * 1470 _icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg, 1471 u32 clk_sel_mask, u32 clk_sel_shift) 1472 { 1473 enum intel_dpll_id id; 1474 1475 id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift; 1476 1477 return intel_get_shared_dpll_by_id(i915, id); 1478 } 1479 1480 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1481 const struct intel_crtc_state *crtc_state) 1482 { 1483 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1484 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1485 enum phy phy = intel_port_to_phy(i915, encoder->port); 1486 1487 if (drm_WARN_ON(&i915->drm, !pll)) 1488 return; 1489 1490 _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1491 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1492 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1493 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1494 } 1495 1496 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1497 { 1498 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1499 enum phy phy = intel_port_to_phy(i915, encoder->port); 1500 1501 _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1502 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1503 } 1504 1505 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1506 { 1507 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1508 enum phy phy = intel_port_to_phy(i915, encoder->port); 1509 1510 return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy), 1511 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1512 } 1513 1514 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1515 { 1516 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1517 enum phy phy = intel_port_to_phy(i915, encoder->port); 1518 1519 return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy), 1520 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1521 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1522 } 1523 1524 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1525 const struct intel_crtc_state *crtc_state) 1526 { 1527 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1528 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1529 enum phy phy = intel_port_to_phy(i915, encoder->port); 1530 1531 if (drm_WARN_ON(&i915->drm, !pll)) 1532 return; 1533 1534 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1535 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1536 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1537 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1538 } 1539 1540 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1541 { 1542 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1543 enum phy phy = intel_port_to_phy(i915, encoder->port); 1544 1545 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1546 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1547 } 1548 1549 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1550 { 1551 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1552 enum phy phy = intel_port_to_phy(i915, encoder->port); 1553 1554 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1555 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1556 } 1557 1558 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1559 { 1560 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1561 enum phy phy = intel_port_to_phy(i915, encoder->port); 1562 1563 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1564 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1565 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1566 } 1567 1568 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1569 const struct intel_crtc_state *crtc_state) 1570 { 1571 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1572 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1573 enum phy phy = intel_port_to_phy(i915, encoder->port); 1574 1575 if (drm_WARN_ON(&i915->drm, !pll)) 1576 return; 1577 1578 /* 1579 * If we fail this, something went very wrong: first 2 PLLs should be 1580 * used by first 2 phys and last 2 PLLs by last phys 1581 */ 1582 if (drm_WARN_ON(&i915->drm, 1583 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1584 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1585 return; 1586 1587 _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1588 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1589 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1590 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1591 } 1592 1593 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1594 { 1595 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1596 enum phy phy = intel_port_to_phy(i915, encoder->port); 1597 1598 _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1599 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1600 } 1601 1602 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1603 { 1604 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1605 enum phy phy = intel_port_to_phy(i915, encoder->port); 1606 1607 return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy), 1608 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1609 } 1610 1611 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1612 { 1613 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1614 enum phy phy = intel_port_to_phy(i915, encoder->port); 1615 enum intel_dpll_id id; 1616 u32 val; 1617 1618 val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy)); 1619 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1620 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1621 id = val; 1622 1623 /* 1624 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1625 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1626 * bit for phy C and D. 1627 */ 1628 if (phy >= PHY_C) 1629 id += DPLL_ID_DG1_DPLL2; 1630 1631 return intel_get_shared_dpll_by_id(i915, id); 1632 } 1633 1634 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1635 const struct intel_crtc_state *crtc_state) 1636 { 1637 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1638 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1639 enum phy phy = intel_port_to_phy(i915, encoder->port); 1640 1641 if (drm_WARN_ON(&i915->drm, !pll)) 1642 return; 1643 1644 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1645 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1646 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1647 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1648 } 1649 1650 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1651 { 1652 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1653 enum phy phy = intel_port_to_phy(i915, encoder->port); 1654 1655 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1656 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1657 } 1658 1659 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1660 { 1661 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1662 enum phy phy = intel_port_to_phy(i915, encoder->port); 1663 1664 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1665 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1666 } 1667 1668 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1669 { 1670 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1671 enum phy phy = intel_port_to_phy(i915, encoder->port); 1672 1673 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1674 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1675 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1676 } 1677 1678 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1679 const struct intel_crtc_state *crtc_state) 1680 { 1681 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1682 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1683 enum port port = encoder->port; 1684 1685 if (drm_WARN_ON(&i915->drm, !pll)) 1686 return; 1687 1688 /* 1689 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1690 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1691 */ 1692 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1693 1694 icl_ddi_combo_enable_clock(encoder, crtc_state); 1695 } 1696 1697 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1698 { 1699 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1700 enum port port = encoder->port; 1701 1702 icl_ddi_combo_disable_clock(encoder); 1703 1704 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1705 } 1706 1707 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1708 { 1709 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1710 enum port port = encoder->port; 1711 u32 tmp; 1712 1713 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1714 1715 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1716 return false; 1717 1718 return icl_ddi_combo_is_clock_enabled(encoder); 1719 } 1720 1721 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1722 const struct intel_crtc_state *crtc_state) 1723 { 1724 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1725 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1726 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1727 enum port port = encoder->port; 1728 1729 if (drm_WARN_ON(&i915->drm, !pll)) 1730 return; 1731 1732 intel_de_write(i915, DDI_CLK_SEL(port), 1733 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1734 1735 mutex_lock(&i915->display.dpll.lock); 1736 1737 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1738 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1739 1740 mutex_unlock(&i915->display.dpll.lock); 1741 } 1742 1743 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1744 { 1745 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1746 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1747 enum port port = encoder->port; 1748 1749 mutex_lock(&i915->display.dpll.lock); 1750 1751 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1752 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1753 1754 mutex_unlock(&i915->display.dpll.lock); 1755 1756 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1757 } 1758 1759 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1760 { 1761 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1762 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1763 enum port port = encoder->port; 1764 u32 tmp; 1765 1766 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1767 1768 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1769 return false; 1770 1771 tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0); 1772 1773 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1774 } 1775 1776 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1777 { 1778 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1779 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1780 enum port port = encoder->port; 1781 enum intel_dpll_id id; 1782 u32 tmp; 1783 1784 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1785 1786 switch (tmp & DDI_CLK_SEL_MASK) { 1787 case DDI_CLK_SEL_TBT_162: 1788 case DDI_CLK_SEL_TBT_270: 1789 case DDI_CLK_SEL_TBT_540: 1790 case DDI_CLK_SEL_TBT_810: 1791 id = DPLL_ID_ICL_TBTPLL; 1792 break; 1793 case DDI_CLK_SEL_MG: 1794 id = icl_tc_port_to_pll_id(tc_port); 1795 break; 1796 default: 1797 MISSING_CASE(tmp); 1798 fallthrough; 1799 case DDI_CLK_SEL_NONE: 1800 return NULL; 1801 } 1802 1803 return intel_get_shared_dpll_by_id(i915, id); 1804 } 1805 1806 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1807 { 1808 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1809 enum intel_dpll_id id; 1810 1811 switch (encoder->port) { 1812 case PORT_A: 1813 id = DPLL_ID_SKL_DPLL0; 1814 break; 1815 case PORT_B: 1816 id = DPLL_ID_SKL_DPLL1; 1817 break; 1818 case PORT_C: 1819 id = DPLL_ID_SKL_DPLL2; 1820 break; 1821 default: 1822 MISSING_CASE(encoder->port); 1823 return NULL; 1824 } 1825 1826 return intel_get_shared_dpll_by_id(i915, id); 1827 } 1828 1829 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1830 const struct intel_crtc_state *crtc_state) 1831 { 1832 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1833 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1834 enum port port = encoder->port; 1835 1836 if (drm_WARN_ON(&i915->drm, !pll)) 1837 return; 1838 1839 mutex_lock(&i915->display.dpll.lock); 1840 1841 intel_de_rmw(i915, DPLL_CTRL2, 1842 DPLL_CTRL2_DDI_CLK_OFF(port) | 1843 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1844 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1845 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1846 1847 mutex_unlock(&i915->display.dpll.lock); 1848 } 1849 1850 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1851 { 1852 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1853 enum port port = encoder->port; 1854 1855 mutex_lock(&i915->display.dpll.lock); 1856 1857 intel_de_rmw(i915, DPLL_CTRL2, 1858 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1859 1860 mutex_unlock(&i915->display.dpll.lock); 1861 } 1862 1863 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1864 { 1865 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1866 enum port port = encoder->port; 1867 1868 /* 1869 * FIXME Not sure if the override affects both 1870 * the PLL selection and the CLK_OFF bit. 1871 */ 1872 return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 1873 } 1874 1875 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 1876 { 1877 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1878 enum port port = encoder->port; 1879 enum intel_dpll_id id; 1880 u32 tmp; 1881 1882 tmp = intel_de_read(i915, DPLL_CTRL2); 1883 1884 /* 1885 * FIXME Not sure if the override affects both 1886 * the PLL selection and the CLK_OFF bit. 1887 */ 1888 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 1889 return NULL; 1890 1891 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 1892 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 1893 1894 return intel_get_shared_dpll_by_id(i915, id); 1895 } 1896 1897 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 1898 const struct intel_crtc_state *crtc_state) 1899 { 1900 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1901 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1902 enum port port = encoder->port; 1903 1904 if (drm_WARN_ON(&i915->drm, !pll)) 1905 return; 1906 1907 intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 1908 } 1909 1910 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 1911 { 1912 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1913 enum port port = encoder->port; 1914 1915 intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 1916 } 1917 1918 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 1919 { 1920 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1921 enum port port = encoder->port; 1922 1923 return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 1924 } 1925 1926 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 1927 { 1928 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1929 enum port port = encoder->port; 1930 enum intel_dpll_id id; 1931 u32 tmp; 1932 1933 tmp = intel_de_read(i915, PORT_CLK_SEL(port)); 1934 1935 switch (tmp & PORT_CLK_SEL_MASK) { 1936 case PORT_CLK_SEL_WRPLL1: 1937 id = DPLL_ID_WRPLL1; 1938 break; 1939 case PORT_CLK_SEL_WRPLL2: 1940 id = DPLL_ID_WRPLL2; 1941 break; 1942 case PORT_CLK_SEL_SPLL: 1943 id = DPLL_ID_SPLL; 1944 break; 1945 case PORT_CLK_SEL_LCPLL_810: 1946 id = DPLL_ID_LCPLL_810; 1947 break; 1948 case PORT_CLK_SEL_LCPLL_1350: 1949 id = DPLL_ID_LCPLL_1350; 1950 break; 1951 case PORT_CLK_SEL_LCPLL_2700: 1952 id = DPLL_ID_LCPLL_2700; 1953 break; 1954 default: 1955 MISSING_CASE(tmp); 1956 fallthrough; 1957 case PORT_CLK_SEL_NONE: 1958 return NULL; 1959 } 1960 1961 return intel_get_shared_dpll_by_id(i915, id); 1962 } 1963 1964 void intel_ddi_enable_clock(struct intel_encoder *encoder, 1965 const struct intel_crtc_state *crtc_state) 1966 { 1967 if (encoder->enable_clock) 1968 encoder->enable_clock(encoder, crtc_state); 1969 } 1970 1971 void intel_ddi_disable_clock(struct intel_encoder *encoder) 1972 { 1973 if (encoder->disable_clock) 1974 encoder->disable_clock(encoder); 1975 } 1976 1977 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 1978 { 1979 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1980 u32 port_mask; 1981 bool ddi_clk_needed; 1982 1983 /* 1984 * In case of DP MST, we sanitize the primary encoder only, not the 1985 * virtual ones. 1986 */ 1987 if (encoder->type == INTEL_OUTPUT_DP_MST) 1988 return; 1989 1990 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 1991 u8 pipe_mask; 1992 bool is_mst; 1993 1994 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 1995 /* 1996 * In the unlikely case that BIOS enables DP in MST mode, just 1997 * warn since our MST HW readout is incomplete. 1998 */ 1999 if (drm_WARN_ON(&i915->drm, is_mst)) 2000 return; 2001 } 2002 2003 port_mask = BIT(encoder->port); 2004 ddi_clk_needed = encoder->base.crtc; 2005 2006 if (encoder->type == INTEL_OUTPUT_DSI) { 2007 struct intel_encoder *other_encoder; 2008 2009 port_mask = intel_dsi_encoder_ports(encoder); 2010 /* 2011 * Sanity check that we haven't incorrectly registered another 2012 * encoder using any of the ports of this DSI encoder. 2013 */ 2014 for_each_intel_encoder(&i915->drm, other_encoder) { 2015 if (other_encoder == encoder) 2016 continue; 2017 2018 if (drm_WARN_ON(&i915->drm, 2019 port_mask & BIT(other_encoder->port))) 2020 return; 2021 } 2022 /* 2023 * For DSI we keep the ddi clocks gated 2024 * except during enable/disable sequence. 2025 */ 2026 ddi_clk_needed = false; 2027 } 2028 2029 if (ddi_clk_needed || !encoder->is_clock_enabled || 2030 !encoder->is_clock_enabled(encoder)) 2031 return; 2032 2033 drm_notice(&i915->drm, 2034 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2035 encoder->base.base.id, encoder->base.name); 2036 2037 encoder->disable_clock(encoder); 2038 } 2039 2040 static void 2041 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2042 const struct intel_crtc_state *crtc_state) 2043 { 2044 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2045 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port); 2046 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); 2047 u32 ln0, ln1, pin_assignment; 2048 u8 width; 2049 2050 if (!intel_phy_is_tc(dev_priv, phy) || 2051 intel_tc_port_in_tbt_alt_mode(dig_port)) 2052 return; 2053 2054 if (DISPLAY_VER(dev_priv) >= 12) { 2055 ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)); 2056 ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)); 2057 } else { 2058 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 2059 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 2060 } 2061 2062 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2063 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2064 2065 /* DPPATC */ 2066 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 2067 width = crtc_state->lane_count; 2068 2069 switch (pin_assignment) { 2070 case 0x0: 2071 drm_WARN_ON(&dev_priv->drm, 2072 !intel_tc_port_in_legacy_mode(dig_port)); 2073 if (width == 1) { 2074 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2075 } else { 2076 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2077 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2078 } 2079 break; 2080 case 0x1: 2081 if (width == 4) { 2082 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2083 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2084 } 2085 break; 2086 case 0x2: 2087 if (width == 2) { 2088 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2089 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2090 } 2091 break; 2092 case 0x3: 2093 case 0x5: 2094 if (width == 1) { 2095 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2096 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2097 } else { 2098 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2099 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2100 } 2101 break; 2102 case 0x4: 2103 case 0x6: 2104 if (width == 1) { 2105 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2106 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2107 } else { 2108 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2109 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2110 } 2111 break; 2112 default: 2113 MISSING_CASE(pin_assignment); 2114 } 2115 2116 if (DISPLAY_VER(dev_priv) >= 12) { 2117 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0); 2118 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1); 2119 } else { 2120 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 2121 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 2122 } 2123 } 2124 2125 static enum transcoder 2126 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2127 { 2128 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2129 return crtc_state->mst_master_transcoder; 2130 else 2131 return crtc_state->cpu_transcoder; 2132 } 2133 2134 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2135 const struct intel_crtc_state *crtc_state) 2136 { 2137 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2138 2139 if (DISPLAY_VER(dev_priv) >= 12) 2140 return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state)); 2141 else 2142 return DP_TP_CTL(encoder->port); 2143 } 2144 2145 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2146 const struct intel_crtc_state *crtc_state) 2147 { 2148 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2149 2150 if (DISPLAY_VER(dev_priv) >= 12) 2151 return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state)); 2152 else 2153 return DP_TP_STATUS(encoder->port); 2154 } 2155 2156 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2157 const struct intel_crtc_state *crtc_state, 2158 bool enable) 2159 { 2160 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2161 2162 if (!crtc_state->vrr.enable) 2163 return; 2164 2165 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2166 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2167 drm_dbg_kms(&i915->drm, 2168 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2169 str_enable_disable(enable)); 2170 } 2171 2172 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2173 const struct intel_crtc_state *crtc_state) 2174 { 2175 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2176 2177 if (!crtc_state->fec_enable) 2178 return; 2179 2180 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0) 2181 drm_dbg_kms(&i915->drm, 2182 "Failed to set FEC_READY in the sink\n"); 2183 } 2184 2185 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2186 const struct intel_crtc_state *crtc_state) 2187 { 2188 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2189 struct intel_dp *intel_dp; 2190 u32 val; 2191 2192 if (!crtc_state->fec_enable) 2193 return; 2194 2195 intel_dp = enc_to_intel_dp(encoder); 2196 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2197 val |= DP_TP_CTL_FEC_ENABLE; 2198 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 2199 } 2200 2201 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder, 2202 const struct intel_crtc_state *crtc_state) 2203 { 2204 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2205 struct intel_dp *intel_dp; 2206 u32 val; 2207 2208 if (!crtc_state->fec_enable) 2209 return; 2210 2211 intel_dp = enc_to_intel_dp(encoder); 2212 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2213 val &= ~DP_TP_CTL_FEC_ENABLE; 2214 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 2215 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2216 } 2217 2218 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2219 const struct intel_crtc_state *crtc_state) 2220 { 2221 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2222 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2223 enum phy phy = intel_port_to_phy(i915, encoder->port); 2224 2225 if (intel_phy_is_combo(i915, phy)) { 2226 bool lane_reversal = 2227 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 2228 2229 intel_combo_phy_power_up_lanes(i915, phy, false, 2230 crtc_state->lane_count, 2231 lane_reversal); 2232 } 2233 } 2234 2235 /* Splitter enable for eDP MSO is limited to certain pipes. */ 2236 static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915) 2237 { 2238 if (IS_ALDERLAKE_P(i915)) 2239 return BIT(PIPE_A) | BIT(PIPE_B); 2240 else 2241 return BIT(PIPE_A); 2242 } 2243 2244 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2245 struct intel_crtc_state *pipe_config) 2246 { 2247 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2248 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2249 enum pipe pipe = crtc->pipe; 2250 u32 dss1; 2251 2252 if (!HAS_MSO(i915)) 2253 return; 2254 2255 dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); 2256 2257 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2258 if (!pipe_config->splitter.enable) 2259 return; 2260 2261 if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) { 2262 pipe_config->splitter.enable = false; 2263 return; 2264 } 2265 2266 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2267 default: 2268 drm_WARN(&i915->drm, true, 2269 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2270 fallthrough; 2271 case SPLITTER_CONFIGURATION_2_SEGMENT: 2272 pipe_config->splitter.link_count = 2; 2273 break; 2274 case SPLITTER_CONFIGURATION_4_SEGMENT: 2275 pipe_config->splitter.link_count = 4; 2276 break; 2277 } 2278 2279 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2280 } 2281 2282 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2283 { 2284 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2285 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2286 enum pipe pipe = crtc->pipe; 2287 u32 dss1 = 0; 2288 2289 if (!HAS_MSO(i915)) 2290 return; 2291 2292 if (crtc_state->splitter.enable) { 2293 dss1 |= SPLITTER_ENABLE; 2294 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2295 if (crtc_state->splitter.link_count == 2) 2296 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2297 else 2298 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2299 } 2300 2301 intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), 2302 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2303 OVERLAP_PIXELS_MASK, dss1); 2304 } 2305 2306 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2307 struct intel_encoder *encoder, 2308 const struct intel_crtc_state *crtc_state, 2309 const struct drm_connector_state *conn_state) 2310 { 2311 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2312 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2313 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2314 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2315 2316 intel_dp_set_link_params(intel_dp, 2317 crtc_state->port_clock, 2318 crtc_state->lane_count); 2319 2320 /* 2321 * We only configure what the register value will be here. Actual 2322 * enabling happens during link training farther down. 2323 */ 2324 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2325 2326 /* 2327 * 1. Enable Power Wells 2328 * 2329 * This was handled at the beginning of intel_atomic_commit_tail(), 2330 * before we called down into this function. 2331 */ 2332 2333 /* 2. Enable Panel Power if PPS is required */ 2334 intel_pps_on(intel_dp); 2335 2336 /* 2337 * 3. For non-TBT Type-C ports, set FIA lane count 2338 * (DFLEXDPSP.DPX4TXLATC) 2339 * 2340 * This was done before tgl_ddi_pre_enable_dp by 2341 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2342 */ 2343 2344 /* 2345 * 4. Enable the port PLL. 2346 * 2347 * The PLL enabling itself was already done before this function by 2348 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 2349 * configure the PLL to port mapping here. 2350 */ 2351 intel_ddi_enable_clock(encoder, crtc_state); 2352 2353 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2354 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2355 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2356 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2357 dig_port->ddi_io_power_domain); 2358 } 2359 2360 /* 6. Program DP_MODE */ 2361 icl_program_mg_dp_mode(dig_port, crtc_state); 2362 2363 /* 2364 * 7. The rest of the below are substeps under the bspec's "Enable and 2365 * Train Display Port" step. Note that steps that are specific to 2366 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2367 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2368 * us when active_mst_links==0, so any steps designated for "single 2369 * stream or multi-stream master transcoder" can just be performed 2370 * unconditionally here. 2371 */ 2372 2373 /* 2374 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2375 * Transcoder. 2376 */ 2377 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2378 2379 if (HAS_DP20(dev_priv)) 2380 intel_ddi_config_transcoder_dp2(encoder, crtc_state); 2381 2382 /* 2383 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2384 * Transport Select 2385 */ 2386 intel_ddi_config_transcoder_func(encoder, crtc_state); 2387 2388 /* 2389 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2390 * selected 2391 * 2392 * This will be handled by the intel_dp_start_link_train() farther 2393 * down this function. 2394 */ 2395 2396 /* 7.e Configure voltage swing and related IO settings */ 2397 encoder->set_signal_levels(encoder, crtc_state); 2398 2399 /* 2400 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2401 * the used lanes of the DDI. 2402 */ 2403 intel_ddi_power_up_lanes(encoder, crtc_state); 2404 2405 /* 2406 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2407 */ 2408 intel_ddi_mso_configure(crtc_state); 2409 2410 if (!is_mst) 2411 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2412 2413 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2414 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); 2415 /* 2416 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2417 * in the FEC_CONFIGURATION register to 1 before initiating link 2418 * training 2419 */ 2420 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 2421 2422 intel_dp_check_frl_training(intel_dp); 2423 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2424 2425 /* 2426 * 7.i Follow DisplayPort specification training sequence (see notes for 2427 * failure handling) 2428 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2429 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2430 * (timeout after 800 us) 2431 */ 2432 intel_dp_start_link_train(intel_dp, crtc_state); 2433 2434 /* 7.k Set DP_TP_CTL link training to Normal */ 2435 if (!is_trans_port_sync_mode(crtc_state)) 2436 intel_dp_stop_link_train(intel_dp, crtc_state); 2437 2438 /* 7.l Configure and enable FEC if needed */ 2439 intel_ddi_enable_fec(encoder, crtc_state); 2440 2441 intel_dsc_dp_pps_write(encoder, crtc_state); 2442 } 2443 2444 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2445 struct intel_encoder *encoder, 2446 const struct intel_crtc_state *crtc_state, 2447 const struct drm_connector_state *conn_state) 2448 { 2449 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2450 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2451 enum port port = encoder->port; 2452 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2453 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2454 2455 if (DISPLAY_VER(dev_priv) < 11) 2456 drm_WARN_ON(&dev_priv->drm, 2457 is_mst && (port == PORT_A || port == PORT_E)); 2458 else 2459 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 2460 2461 intel_dp_set_link_params(intel_dp, 2462 crtc_state->port_clock, 2463 crtc_state->lane_count); 2464 2465 /* 2466 * We only configure what the register value will be here. Actual 2467 * enabling happens during link training farther down. 2468 */ 2469 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2470 2471 intel_pps_on(intel_dp); 2472 2473 intel_ddi_enable_clock(encoder, crtc_state); 2474 2475 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2476 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2477 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2478 dig_port->ddi_io_power_domain); 2479 } 2480 2481 icl_program_mg_dp_mode(dig_port, crtc_state); 2482 2483 if (has_buf_trans_select(dev_priv)) 2484 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2485 2486 encoder->set_signal_levels(encoder, crtc_state); 2487 2488 intel_ddi_power_up_lanes(encoder, crtc_state); 2489 2490 if (!is_mst) 2491 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2492 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2493 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, 2494 true); 2495 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 2496 intel_dp_start_link_train(intel_dp, crtc_state); 2497 if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && 2498 !is_trans_port_sync_mode(crtc_state)) 2499 intel_dp_stop_link_train(intel_dp, crtc_state); 2500 2501 intel_ddi_enable_fec(encoder, crtc_state); 2502 2503 if (!is_mst) 2504 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2505 2506 intel_dsc_dp_pps_write(encoder, crtc_state); 2507 } 2508 2509 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2510 struct intel_encoder *encoder, 2511 const struct intel_crtc_state *crtc_state, 2512 const struct drm_connector_state *conn_state) 2513 { 2514 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2515 2516 if (DISPLAY_VER(dev_priv) >= 12) 2517 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2518 else 2519 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2520 2521 /* MST will call a setting of MSA after an allocating of Virtual Channel 2522 * from MST encoder pre_enable callback. 2523 */ 2524 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2525 intel_ddi_set_dp_msa(crtc_state, conn_state); 2526 } 2527 2528 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2529 struct intel_encoder *encoder, 2530 const struct intel_crtc_state *crtc_state, 2531 const struct drm_connector_state *conn_state) 2532 { 2533 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2534 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2535 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2536 2537 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2538 intel_ddi_enable_clock(encoder, crtc_state); 2539 2540 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2541 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2542 dig_port->ddi_io_power_domain); 2543 2544 icl_program_mg_dp_mode(dig_port, crtc_state); 2545 2546 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2547 2548 dig_port->set_infoframes(encoder, 2549 crtc_state->has_infoframe, 2550 crtc_state, conn_state); 2551 } 2552 2553 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 2554 struct intel_encoder *encoder, 2555 const struct intel_crtc_state *crtc_state, 2556 const struct drm_connector_state *conn_state) 2557 { 2558 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2559 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2560 enum pipe pipe = crtc->pipe; 2561 2562 /* 2563 * When called from DP MST code: 2564 * - conn_state will be NULL 2565 * - encoder will be the main encoder (ie. mst->primary) 2566 * - the main connector associated with this port 2567 * won't be active or linked to a crtc 2568 * - crtc_state will be the state of the first stream to 2569 * be activated on this port, and it may not be the same 2570 * stream that will be deactivated last, but each stream 2571 * should have a state that is identical when it comes to 2572 * the DP link parameteres 2573 */ 2574 2575 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 2576 2577 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2578 2579 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 2580 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 2581 conn_state); 2582 } else { 2583 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2584 2585 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 2586 conn_state); 2587 2588 /* FIXME precompute everything properly */ 2589 /* FIXME how do we turn infoframes off again? */ 2590 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) 2591 dig_port->set_infoframes(encoder, 2592 crtc_state->has_infoframe, 2593 crtc_state, conn_state); 2594 } 2595 } 2596 2597 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 2598 const struct intel_crtc_state *crtc_state) 2599 { 2600 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2601 enum port port = encoder->port; 2602 bool wait = false; 2603 u32 val; 2604 2605 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2606 if (val & DDI_BUF_CTL_ENABLE) { 2607 val &= ~DDI_BUF_CTL_ENABLE; 2608 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 2609 wait = true; 2610 } 2611 2612 if (intel_crtc_has_dp_encoder(crtc_state)) { 2613 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2614 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 2615 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 2616 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 2617 } 2618 2619 /* Disable FEC in DP Sink */ 2620 intel_ddi_disable_fec_state(encoder, crtc_state); 2621 2622 if (wait) 2623 intel_wait_ddi_buf_idle(dev_priv, port); 2624 } 2625 2626 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 2627 struct intel_encoder *encoder, 2628 const struct intel_crtc_state *old_crtc_state, 2629 const struct drm_connector_state *old_conn_state) 2630 { 2631 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2632 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2633 struct intel_dp *intel_dp = &dig_port->dp; 2634 bool is_mst = intel_crtc_has_type(old_crtc_state, 2635 INTEL_OUTPUT_DP_MST); 2636 2637 if (!is_mst) 2638 intel_dp_set_infoframes(encoder, false, 2639 old_crtc_state, old_conn_state); 2640 2641 /* 2642 * Power down sink before disabling the port, otherwise we end 2643 * up getting interrupts from the sink on detecting link loss. 2644 */ 2645 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 2646 2647 if (DISPLAY_VER(dev_priv) >= 12) { 2648 if (is_mst) { 2649 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 2650 u32 val; 2651 2652 val = intel_de_read(dev_priv, 2653 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 2654 val &= ~(TGL_TRANS_DDI_PORT_MASK | 2655 TRANS_DDI_MODE_SELECT_MASK); 2656 intel_de_write(dev_priv, 2657 TRANS_DDI_FUNC_CTL(cpu_transcoder), 2658 val); 2659 } 2660 } else { 2661 if (!is_mst) 2662 intel_ddi_disable_pipe_clock(old_crtc_state); 2663 } 2664 2665 intel_disable_ddi_buf(encoder, old_crtc_state); 2666 2667 /* 2668 * From TGL spec: "If single stream or multi-stream master transcoder: 2669 * Configure Transcoder Clock select to direct no clock to the 2670 * transcoder" 2671 */ 2672 if (DISPLAY_VER(dev_priv) >= 12) 2673 intel_ddi_disable_pipe_clock(old_crtc_state); 2674 2675 intel_pps_vdd_on(intel_dp); 2676 intel_pps_off(intel_dp); 2677 2678 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 2679 intel_display_power_put(dev_priv, 2680 dig_port->ddi_io_power_domain, 2681 fetch_and_zero(&dig_port->ddi_io_wakeref)); 2682 2683 intel_ddi_disable_clock(encoder); 2684 } 2685 2686 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 2687 struct intel_encoder *encoder, 2688 const struct intel_crtc_state *old_crtc_state, 2689 const struct drm_connector_state *old_conn_state) 2690 { 2691 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2692 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2693 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2694 2695 dig_port->set_infoframes(encoder, false, 2696 old_crtc_state, old_conn_state); 2697 2698 if (DISPLAY_VER(dev_priv) < 12) 2699 intel_ddi_disable_pipe_clock(old_crtc_state); 2700 2701 intel_disable_ddi_buf(encoder, old_crtc_state); 2702 2703 if (DISPLAY_VER(dev_priv) >= 12) 2704 intel_ddi_disable_pipe_clock(old_crtc_state); 2705 2706 intel_display_power_put(dev_priv, 2707 dig_port->ddi_io_power_domain, 2708 fetch_and_zero(&dig_port->ddi_io_wakeref)); 2709 2710 intel_ddi_disable_clock(encoder); 2711 2712 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 2713 } 2714 2715 static void intel_ddi_post_disable(struct intel_atomic_state *state, 2716 struct intel_encoder *encoder, 2717 const struct intel_crtc_state *old_crtc_state, 2718 const struct drm_connector_state *old_conn_state) 2719 { 2720 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2721 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2722 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2723 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 2724 struct intel_crtc *slave_crtc; 2725 2726 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) { 2727 intel_crtc_vblank_off(old_crtc_state); 2728 2729 intel_disable_transcoder(old_crtc_state); 2730 2731 intel_vrr_disable(old_crtc_state); 2732 2733 intel_ddi_disable_transcoder_func(old_crtc_state); 2734 2735 intel_dsc_disable(old_crtc_state); 2736 2737 if (DISPLAY_VER(dev_priv) >= 9) 2738 skl_scaler_disable(old_crtc_state); 2739 else 2740 ilk_pfit_disable(old_crtc_state); 2741 } 2742 2743 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc, 2744 intel_crtc_bigjoiner_slave_pipes(old_crtc_state)) { 2745 const struct intel_crtc_state *old_slave_crtc_state = 2746 intel_atomic_get_old_crtc_state(state, slave_crtc); 2747 2748 intel_crtc_vblank_off(old_slave_crtc_state); 2749 2750 intel_dsc_disable(old_slave_crtc_state); 2751 skl_scaler_disable(old_slave_crtc_state); 2752 } 2753 2754 /* 2755 * When called from DP MST code: 2756 * - old_conn_state will be NULL 2757 * - encoder will be the main encoder (ie. mst->primary) 2758 * - the main connector associated with this port 2759 * won't be active or linked to a crtc 2760 * - old_crtc_state will be the state of the last stream to 2761 * be deactivated on this port, and it may not be the same 2762 * stream that was activated last, but each stream 2763 * should have a state that is identical when it comes to 2764 * the DP link parameteres 2765 */ 2766 2767 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 2768 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 2769 old_conn_state); 2770 else 2771 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 2772 old_conn_state); 2773 2774 main_link_aux_power_domain_put(dig_port, old_crtc_state); 2775 2776 if (is_tc_port) 2777 intel_tc_port_put_link(dig_port); 2778 } 2779 2780 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 2781 struct intel_encoder *encoder, 2782 const struct intel_crtc_state *crtc_state) 2783 { 2784 const struct drm_connector_state *conn_state; 2785 struct drm_connector *conn; 2786 int i; 2787 2788 if (!crtc_state->sync_mode_slaves_mask) 2789 return; 2790 2791 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 2792 struct intel_encoder *slave_encoder = 2793 to_intel_encoder(conn_state->best_encoder); 2794 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 2795 const struct intel_crtc_state *slave_crtc_state; 2796 2797 if (!slave_crtc) 2798 continue; 2799 2800 slave_crtc_state = 2801 intel_atomic_get_new_crtc_state(state, slave_crtc); 2802 2803 if (slave_crtc_state->master_transcoder != 2804 crtc_state->cpu_transcoder) 2805 continue; 2806 2807 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 2808 slave_crtc_state); 2809 } 2810 2811 usleep_range(200, 400); 2812 2813 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 2814 crtc_state); 2815 } 2816 2817 static void intel_enable_ddi_dp(struct intel_atomic_state *state, 2818 struct intel_encoder *encoder, 2819 const struct intel_crtc_state *crtc_state, 2820 const struct drm_connector_state *conn_state) 2821 { 2822 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2823 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2824 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2825 enum port port = encoder->port; 2826 2827 if (port == PORT_A && DISPLAY_VER(dev_priv) < 9) 2828 intel_dp_stop_link_train(intel_dp, crtc_state); 2829 2830 drm_connector_update_privacy_screen(conn_state); 2831 intel_edp_backlight_on(crtc_state, conn_state); 2832 2833 if (!dig_port->lspcon.active || dig_port->dp.has_hdmi_sink) 2834 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 2835 2836 intel_audio_codec_enable(encoder, crtc_state, conn_state); 2837 2838 trans_port_sync_stop_link_train(state, encoder, crtc_state); 2839 } 2840 2841 static i915_reg_t 2842 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 2843 enum port port) 2844 { 2845 static const enum transcoder trans[] = { 2846 [PORT_A] = TRANSCODER_EDP, 2847 [PORT_B] = TRANSCODER_A, 2848 [PORT_C] = TRANSCODER_B, 2849 [PORT_D] = TRANSCODER_C, 2850 [PORT_E] = TRANSCODER_A, 2851 }; 2852 2853 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9); 2854 2855 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) 2856 port = PORT_A; 2857 2858 return CHICKEN_TRANS(trans[port]); 2859 } 2860 2861 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, 2862 struct intel_encoder *encoder, 2863 const struct intel_crtc_state *crtc_state, 2864 const struct drm_connector_state *conn_state) 2865 { 2866 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2867 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2868 struct drm_connector *connector = conn_state->connector; 2869 enum port port = encoder->port; 2870 enum phy phy = intel_port_to_phy(dev_priv, port); 2871 u32 buf_ctl; 2872 2873 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 2874 crtc_state->hdmi_high_tmds_clock_ratio, 2875 crtc_state->hdmi_scrambling)) 2876 drm_dbg_kms(&dev_priv->drm, 2877 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 2878 connector->base.id, connector->name); 2879 2880 if (has_buf_trans_select(dev_priv)) 2881 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 2882 2883 encoder->set_signal_levels(encoder, crtc_state); 2884 2885 /* Display WA #1143: skl,kbl,cfl */ 2886 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { 2887 /* 2888 * For some reason these chicken bits have been 2889 * stuffed into a transcoder register, event though 2890 * the bits affect a specific DDI port rather than 2891 * a specific transcoder. 2892 */ 2893 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 2894 u32 val; 2895 2896 val = intel_de_read(dev_priv, reg); 2897 2898 if (port == PORT_E) 2899 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 2900 DDIE_TRAINING_OVERRIDE_VALUE; 2901 else 2902 val |= DDI_TRAINING_OVERRIDE_ENABLE | 2903 DDI_TRAINING_OVERRIDE_VALUE; 2904 2905 intel_de_write(dev_priv, reg, val); 2906 intel_de_posting_read(dev_priv, reg); 2907 2908 udelay(1); 2909 2910 if (port == PORT_E) 2911 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 2912 DDIE_TRAINING_OVERRIDE_VALUE); 2913 else 2914 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 2915 DDI_TRAINING_OVERRIDE_VALUE); 2916 2917 intel_de_write(dev_priv, reg, val); 2918 } 2919 2920 intel_ddi_power_up_lanes(encoder, crtc_state); 2921 2922 /* In HDMI/DVI mode, the port width, and swing/emphasis values 2923 * are ignored so nothing special needs to be done besides 2924 * enabling the port. 2925 * 2926 * On ADL_P the PHY link rate and lane count must be programmed but 2927 * these are both 0 for HDMI. 2928 */ 2929 buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE; 2930 if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) { 2931 drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port)); 2932 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 2933 } 2934 intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl); 2935 2936 intel_audio_codec_enable(encoder, crtc_state, conn_state); 2937 } 2938 2939 static void intel_enable_ddi(struct intel_atomic_state *state, 2940 struct intel_encoder *encoder, 2941 const struct intel_crtc_state *crtc_state, 2942 const struct drm_connector_state *conn_state) 2943 { 2944 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 2945 2946 if (!intel_crtc_is_bigjoiner_slave(crtc_state)) 2947 intel_ddi_enable_transcoder_func(encoder, crtc_state); 2948 2949 intel_vrr_enable(encoder, crtc_state); 2950 2951 intel_enable_transcoder(crtc_state); 2952 2953 intel_crtc_vblank_on(crtc_state); 2954 2955 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 2956 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state); 2957 else 2958 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state); 2959 2960 /* Enable hdcp if it's desired */ 2961 if (conn_state->content_protection == 2962 DRM_MODE_CONTENT_PROTECTION_DESIRED) 2963 intel_hdcp_enable(to_intel_connector(conn_state->connector), 2964 crtc_state, 2965 (u8)conn_state->hdcp_content_type); 2966 } 2967 2968 static void intel_disable_ddi_dp(struct intel_atomic_state *state, 2969 struct intel_encoder *encoder, 2970 const struct intel_crtc_state *old_crtc_state, 2971 const struct drm_connector_state *old_conn_state) 2972 { 2973 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2974 2975 intel_dp->link_trained = false; 2976 2977 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 2978 2979 intel_psr_disable(intel_dp, old_crtc_state); 2980 intel_edp_backlight_off(old_conn_state); 2981 /* Disable the decompression in DP Sink */ 2982 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, 2983 false); 2984 /* Disable Ignore_MSA bit in DP Sink */ 2985 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 2986 false); 2987 } 2988 2989 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state, 2990 struct intel_encoder *encoder, 2991 const struct intel_crtc_state *old_crtc_state, 2992 const struct drm_connector_state *old_conn_state) 2993 { 2994 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2995 struct drm_connector *connector = old_conn_state->connector; 2996 2997 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 2998 2999 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3000 false, false)) 3001 drm_dbg_kms(&i915->drm, 3002 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3003 connector->base.id, connector->name); 3004 } 3005 3006 static void intel_disable_ddi(struct intel_atomic_state *state, 3007 struct intel_encoder *encoder, 3008 const struct intel_crtc_state *old_crtc_state, 3009 const struct drm_connector_state *old_conn_state) 3010 { 3011 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3012 3013 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3014 intel_disable_ddi_hdmi(state, encoder, old_crtc_state, 3015 old_conn_state); 3016 else 3017 intel_disable_ddi_dp(state, encoder, old_crtc_state, 3018 old_conn_state); 3019 } 3020 3021 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3022 struct intel_encoder *encoder, 3023 const struct intel_crtc_state *crtc_state, 3024 const struct drm_connector_state *conn_state) 3025 { 3026 intel_ddi_set_dp_msa(crtc_state, conn_state); 3027 3028 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3029 3030 intel_backlight_update(state, encoder, crtc_state, conn_state); 3031 drm_connector_update_privacy_screen(conn_state); 3032 } 3033 3034 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3035 struct intel_encoder *encoder, 3036 const struct intel_crtc_state *crtc_state, 3037 const struct drm_connector_state *conn_state) 3038 { 3039 3040 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3041 !intel_encoder_is_mst(encoder)) 3042 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3043 conn_state); 3044 3045 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3046 } 3047 3048 static void 3049 intel_ddi_update_prepare(struct intel_atomic_state *state, 3050 struct intel_encoder *encoder, 3051 struct intel_crtc *crtc) 3052 { 3053 struct drm_i915_private *i915 = to_i915(state->base.dev); 3054 struct intel_crtc_state *crtc_state = 3055 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL; 3056 int required_lanes = crtc_state ? crtc_state->lane_count : 1; 3057 3058 drm_WARN_ON(state->base.dev, crtc && crtc->active); 3059 3060 intel_tc_port_get_link(enc_to_dig_port(encoder), 3061 required_lanes); 3062 if (crtc_state && crtc_state->hw.active) { 3063 struct intel_crtc *slave_crtc; 3064 3065 intel_update_active_dpll(state, crtc, encoder); 3066 3067 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 3068 intel_crtc_bigjoiner_slave_pipes(crtc_state)) 3069 intel_update_active_dpll(state, slave_crtc, encoder); 3070 } 3071 } 3072 3073 static void 3074 intel_ddi_update_complete(struct intel_atomic_state *state, 3075 struct intel_encoder *encoder, 3076 struct intel_crtc *crtc) 3077 { 3078 intel_tc_port_put_link(enc_to_dig_port(encoder)); 3079 } 3080 3081 static void 3082 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3083 struct intel_encoder *encoder, 3084 const struct intel_crtc_state *crtc_state, 3085 const struct drm_connector_state *conn_state) 3086 { 3087 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3088 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3089 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3090 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 3091 3092 if (is_tc_port) 3093 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3094 3095 main_link_aux_power_domain_get(dig_port, crtc_state); 3096 3097 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3098 /* 3099 * Program the lane count for static/dynamic connections on 3100 * Type-C ports. Skip this step for TBT. 3101 */ 3102 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3103 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3104 bxt_ddi_phy_set_lane_optim_mask(encoder, 3105 crtc_state->lane_lat_optim_mask); 3106 } 3107 3108 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) 3109 { 3110 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3111 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 3112 int ln; 3113 3114 for (ln = 0; ln < 2; ln++) 3115 intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0); 3116 } 3117 3118 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3119 const struct intel_crtc_state *crtc_state) 3120 { 3121 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3122 struct intel_encoder *encoder = &dig_port->base; 3123 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3124 enum port port = encoder->port; 3125 u32 dp_tp_ctl, ddi_buf_ctl; 3126 bool wait = false; 3127 3128 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3129 3130 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 3131 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3132 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 3133 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3134 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 3135 wait = true; 3136 } 3137 3138 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 3139 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1; 3140 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3141 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3142 3143 if (wait) 3144 intel_wait_ddi_buf_idle(dev_priv, port); 3145 } 3146 3147 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3148 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3149 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3150 } else { 3151 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3152 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 3153 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3154 } 3155 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3156 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3157 3158 if (IS_ALDERLAKE_P(dev_priv) && 3159 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) 3160 adlp_tbt_to_dp_alt_switch_wa(encoder); 3161 3162 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3163 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3164 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3165 3166 intel_wait_ddi_buf_active(dev_priv, port); 3167 } 3168 3169 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3170 const struct intel_crtc_state *crtc_state, 3171 u8 dp_train_pat) 3172 { 3173 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3174 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3175 u32 temp; 3176 3177 temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3178 3179 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3180 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3181 case DP_TRAINING_PATTERN_DISABLE: 3182 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3183 break; 3184 case DP_TRAINING_PATTERN_1: 3185 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3186 break; 3187 case DP_TRAINING_PATTERN_2: 3188 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3189 break; 3190 case DP_TRAINING_PATTERN_3: 3191 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3192 break; 3193 case DP_TRAINING_PATTERN_4: 3194 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3195 break; 3196 } 3197 3198 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp); 3199 } 3200 3201 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3202 const struct intel_crtc_state *crtc_state) 3203 { 3204 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3205 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3206 enum port port = encoder->port; 3207 u32 val; 3208 3209 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3210 val &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3211 val |= DP_TP_CTL_LINK_TRAIN_IDLE; 3212 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 3213 3214 /* 3215 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3216 * reason we need to set idle transmission mode is to work around a HW 3217 * issue where we enable the pipe while not in idle link-training mode. 3218 * In this case there is requirement to wait for a minimum number of 3219 * idle patterns to be sent. 3220 */ 3221 if (port == PORT_A && DISPLAY_VER(dev_priv) < 12) 3222 return; 3223 3224 if (intel_de_wait_for_set(dev_priv, 3225 dp_tp_status_reg(encoder, crtc_state), 3226 DP_TP_STATUS_IDLE_DONE, 1)) 3227 drm_err(&dev_priv->drm, 3228 "Timed out waiting for DP idle patterns\n"); 3229 } 3230 3231 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 3232 enum transcoder cpu_transcoder) 3233 { 3234 if (cpu_transcoder == TRANSCODER_EDP) 3235 return false; 3236 3237 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO)) 3238 return false; 3239 3240 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 3241 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3242 } 3243 3244 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, 3245 struct intel_crtc_state *crtc_state) 3246 { 3247 if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000) 3248 crtc_state->min_voltage_level = 2; 3249 else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000) 3250 crtc_state->min_voltage_level = 3; 3251 else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000) 3252 crtc_state->min_voltage_level = 1; 3253 } 3254 3255 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, 3256 enum transcoder cpu_transcoder) 3257 { 3258 u32 master_select; 3259 3260 if (DISPLAY_VER(dev_priv) >= 11) { 3261 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder)); 3262 3263 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3264 return INVALID_TRANSCODER; 3265 3266 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3267 } else { 3268 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3269 3270 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3271 return INVALID_TRANSCODER; 3272 3273 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3274 } 3275 3276 if (master_select == 0) 3277 return TRANSCODER_EDP; 3278 else 3279 return master_select - 1; 3280 } 3281 3282 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3283 { 3284 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3285 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3286 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3287 enum transcoder cpu_transcoder; 3288 3289 crtc_state->master_transcoder = 3290 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); 3291 3292 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { 3293 enum intel_display_power_domain power_domain; 3294 intel_wakeref_t trans_wakeref; 3295 3296 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3297 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 3298 power_domain); 3299 3300 if (!trans_wakeref) 3301 continue; 3302 3303 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == 3304 crtc_state->cpu_transcoder) 3305 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3306 3307 intel_display_power_put(dev_priv, power_domain, trans_wakeref); 3308 } 3309 3310 drm_WARN_ON(&dev_priv->drm, 3311 crtc_state->master_transcoder != INVALID_TRANSCODER && 3312 crtc_state->sync_mode_slaves_mask); 3313 } 3314 3315 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 3316 struct intel_crtc_state *pipe_config) 3317 { 3318 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3319 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3320 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3321 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3322 u32 temp, flags = 0; 3323 3324 temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3325 if (temp & TRANS_DDI_PHSYNC) 3326 flags |= DRM_MODE_FLAG_PHSYNC; 3327 else 3328 flags |= DRM_MODE_FLAG_NHSYNC; 3329 if (temp & TRANS_DDI_PVSYNC) 3330 flags |= DRM_MODE_FLAG_PVSYNC; 3331 else 3332 flags |= DRM_MODE_FLAG_NVSYNC; 3333 3334 pipe_config->hw.adjusted_mode.flags |= flags; 3335 3336 switch (temp & TRANS_DDI_BPC_MASK) { 3337 case TRANS_DDI_BPC_6: 3338 pipe_config->pipe_bpp = 18; 3339 break; 3340 case TRANS_DDI_BPC_8: 3341 pipe_config->pipe_bpp = 24; 3342 break; 3343 case TRANS_DDI_BPC_10: 3344 pipe_config->pipe_bpp = 30; 3345 break; 3346 case TRANS_DDI_BPC_12: 3347 pipe_config->pipe_bpp = 36; 3348 break; 3349 default: 3350 break; 3351 } 3352 3353 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 3354 case TRANS_DDI_MODE_SELECT_HDMI: 3355 pipe_config->has_hdmi_sink = true; 3356 3357 pipe_config->infoframes.enable |= 3358 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3359 3360 if (pipe_config->infoframes.enable) 3361 pipe_config->has_infoframe = true; 3362 3363 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 3364 pipe_config->hdmi_scrambling = true; 3365 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 3366 pipe_config->hdmi_high_tmds_clock_ratio = true; 3367 fallthrough; 3368 case TRANS_DDI_MODE_SELECT_DVI: 3369 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 3370 pipe_config->lane_count = 4; 3371 break; 3372 case TRANS_DDI_MODE_SELECT_DP_SST: 3373 if (encoder->type == INTEL_OUTPUT_EDP) 3374 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 3375 else 3376 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 3377 pipe_config->lane_count = 3378 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3379 3380 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 3381 &pipe_config->dp_m_n); 3382 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, 3383 &pipe_config->dp_m2_n2); 3384 3385 if (DISPLAY_VER(dev_priv) >= 11) { 3386 i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config); 3387 3388 pipe_config->fec_enable = 3389 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE; 3390 3391 drm_dbg_kms(&dev_priv->drm, 3392 "[ENCODER:%d:%s] Fec status: %u\n", 3393 encoder->base.base.id, encoder->base.name, 3394 pipe_config->fec_enable); 3395 } 3396 3397 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) 3398 pipe_config->infoframes.enable |= 3399 intel_lspcon_infoframes_enabled(encoder, pipe_config); 3400 else 3401 pipe_config->infoframes.enable |= 3402 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3403 break; 3404 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 3405 if (!HAS_DP20(dev_priv)) { 3406 /* FDI */ 3407 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 3408 break; 3409 } 3410 fallthrough; /* 128b/132b */ 3411 case TRANS_DDI_MODE_SELECT_DP_MST: 3412 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 3413 pipe_config->lane_count = 3414 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3415 3416 if (DISPLAY_VER(dev_priv) >= 12) 3417 pipe_config->mst_master_transcoder = 3418 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); 3419 3420 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 3421 &pipe_config->dp_m_n); 3422 3423 pipe_config->infoframes.enable |= 3424 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3425 break; 3426 default: 3427 break; 3428 } 3429 } 3430 3431 static void intel_ddi_get_config(struct intel_encoder *encoder, 3432 struct intel_crtc_state *pipe_config) 3433 { 3434 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3435 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3436 3437 /* XXX: DSI transcoder paranoia */ 3438 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 3439 return; 3440 3441 intel_ddi_read_func_ctl(encoder, pipe_config); 3442 3443 intel_ddi_mso_get_config(encoder, pipe_config); 3444 3445 pipe_config->has_audio = 3446 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 3447 3448 if (encoder->type == INTEL_OUTPUT_EDP) 3449 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); 3450 3451 ddi_dotclock_get(pipe_config); 3452 3453 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3454 pipe_config->lane_lat_optim_mask = 3455 bxt_ddi_phy_get_lane_lat_optim_mask(encoder); 3456 3457 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 3458 3459 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 3460 3461 intel_read_infoframe(encoder, pipe_config, 3462 HDMI_INFOFRAME_TYPE_AVI, 3463 &pipe_config->infoframes.avi); 3464 intel_read_infoframe(encoder, pipe_config, 3465 HDMI_INFOFRAME_TYPE_SPD, 3466 &pipe_config->infoframes.spd); 3467 intel_read_infoframe(encoder, pipe_config, 3468 HDMI_INFOFRAME_TYPE_VENDOR, 3469 &pipe_config->infoframes.hdmi); 3470 intel_read_infoframe(encoder, pipe_config, 3471 HDMI_INFOFRAME_TYPE_DRM, 3472 &pipe_config->infoframes.drm); 3473 3474 if (DISPLAY_VER(dev_priv) >= 8) 3475 bdw_get_trans_port_sync_config(pipe_config); 3476 3477 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 3478 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 3479 3480 intel_psr_get_config(encoder, pipe_config); 3481 } 3482 3483 void intel_ddi_get_clock(struct intel_encoder *encoder, 3484 struct intel_crtc_state *crtc_state, 3485 struct intel_shared_dpll *pll) 3486 { 3487 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3488 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 3489 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 3490 bool pll_active; 3491 3492 if (drm_WARN_ON(&i915->drm, !pll)) 3493 return; 3494 3495 port_dpll->pll = pll; 3496 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 3497 drm_WARN_ON(&i915->drm, !pll_active); 3498 3499 icl_set_active_port_dpll(crtc_state, port_dpll_id); 3500 3501 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 3502 &crtc_state->dpll_hw_state); 3503 } 3504 3505 static void dg2_ddi_get_config(struct intel_encoder *encoder, 3506 struct intel_crtc_state *crtc_state) 3507 { 3508 intel_mpllb_readout_hw_state(encoder, &crtc_state->mpllb_state); 3509 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->mpllb_state); 3510 3511 intel_ddi_get_config(encoder, crtc_state); 3512 } 3513 3514 static void adls_ddi_get_config(struct intel_encoder *encoder, 3515 struct intel_crtc_state *crtc_state) 3516 { 3517 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 3518 intel_ddi_get_config(encoder, crtc_state); 3519 } 3520 3521 static void rkl_ddi_get_config(struct intel_encoder *encoder, 3522 struct intel_crtc_state *crtc_state) 3523 { 3524 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 3525 intel_ddi_get_config(encoder, crtc_state); 3526 } 3527 3528 static void dg1_ddi_get_config(struct intel_encoder *encoder, 3529 struct intel_crtc_state *crtc_state) 3530 { 3531 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 3532 intel_ddi_get_config(encoder, crtc_state); 3533 } 3534 3535 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 3536 struct intel_crtc_state *crtc_state) 3537 { 3538 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 3539 intel_ddi_get_config(encoder, crtc_state); 3540 } 3541 3542 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 3543 struct intel_crtc_state *crtc_state, 3544 struct intel_shared_dpll *pll) 3545 { 3546 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3547 enum icl_port_dpll_id port_dpll_id; 3548 struct icl_port_dpll *port_dpll; 3549 bool pll_active; 3550 3551 if (drm_WARN_ON(&i915->drm, !pll)) 3552 return; 3553 3554 if (pll->info->id == DPLL_ID_ICL_TBTPLL) 3555 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 3556 else 3557 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 3558 3559 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 3560 3561 port_dpll->pll = pll; 3562 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 3563 drm_WARN_ON(&i915->drm, !pll_active); 3564 3565 icl_set_active_port_dpll(crtc_state, port_dpll_id); 3566 3567 if (crtc_state->shared_dpll->info->id == DPLL_ID_ICL_TBTPLL) 3568 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port); 3569 else 3570 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 3571 &crtc_state->dpll_hw_state); 3572 } 3573 3574 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 3575 struct intel_crtc_state *crtc_state) 3576 { 3577 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 3578 intel_ddi_get_config(encoder, crtc_state); 3579 } 3580 3581 static void bxt_ddi_get_config(struct intel_encoder *encoder, 3582 struct intel_crtc_state *crtc_state) 3583 { 3584 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 3585 intel_ddi_get_config(encoder, crtc_state); 3586 } 3587 3588 static void skl_ddi_get_config(struct intel_encoder *encoder, 3589 struct intel_crtc_state *crtc_state) 3590 { 3591 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 3592 intel_ddi_get_config(encoder, crtc_state); 3593 } 3594 3595 void hsw_ddi_get_config(struct intel_encoder *encoder, 3596 struct intel_crtc_state *crtc_state) 3597 { 3598 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 3599 intel_ddi_get_config(encoder, crtc_state); 3600 } 3601 3602 static void intel_ddi_sync_state(struct intel_encoder *encoder, 3603 const struct intel_crtc_state *crtc_state) 3604 { 3605 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3606 enum phy phy = intel_port_to_phy(i915, encoder->port); 3607 3608 if (intel_phy_is_tc(i915, phy)) 3609 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder)); 3610 3611 if (crtc_state && intel_crtc_has_dp_encoder(crtc_state)) 3612 intel_dp_sync_state(encoder, crtc_state); 3613 } 3614 3615 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 3616 struct intel_crtc_state *crtc_state) 3617 { 3618 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3619 enum phy phy = intel_port_to_phy(i915, encoder->port); 3620 bool fastset = true; 3621 3622 if (intel_phy_is_tc(i915, phy)) { 3623 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", 3624 encoder->base.base.id, encoder->base.name); 3625 crtc_state->uapi.mode_changed = true; 3626 fastset = false; 3627 } 3628 3629 if (intel_crtc_has_dp_encoder(crtc_state) && 3630 !intel_dp_initial_fastset_check(encoder, crtc_state)) 3631 fastset = false; 3632 3633 return fastset; 3634 } 3635 3636 static enum intel_output_type 3637 intel_ddi_compute_output_type(struct intel_encoder *encoder, 3638 struct intel_crtc_state *crtc_state, 3639 struct drm_connector_state *conn_state) 3640 { 3641 switch (conn_state->connector->connector_type) { 3642 case DRM_MODE_CONNECTOR_HDMIA: 3643 return INTEL_OUTPUT_HDMI; 3644 case DRM_MODE_CONNECTOR_eDP: 3645 return INTEL_OUTPUT_EDP; 3646 case DRM_MODE_CONNECTOR_DisplayPort: 3647 return INTEL_OUTPUT_DP; 3648 default: 3649 MISSING_CASE(conn_state->connector->connector_type); 3650 return INTEL_OUTPUT_UNUSED; 3651 } 3652 } 3653 3654 static int intel_ddi_compute_config(struct intel_encoder *encoder, 3655 struct intel_crtc_state *pipe_config, 3656 struct drm_connector_state *conn_state) 3657 { 3658 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3659 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3660 enum port port = encoder->port; 3661 int ret; 3662 3663 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 3664 pipe_config->cpu_transcoder = TRANSCODER_EDP; 3665 3666 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 3667 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 3668 } else { 3669 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 3670 } 3671 3672 if (ret) 3673 return ret; 3674 3675 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 3676 pipe_config->cpu_transcoder == TRANSCODER_EDP) 3677 pipe_config->pch_pfit.force_thru = 3678 pipe_config->pch_pfit.enabled || 3679 pipe_config->crc_enabled; 3680 3681 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3682 pipe_config->lane_lat_optim_mask = 3683 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 3684 3685 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 3686 3687 return 0; 3688 } 3689 3690 static bool mode_equal(const struct drm_display_mode *mode1, 3691 const struct drm_display_mode *mode2) 3692 { 3693 return drm_mode_match(mode1, mode2, 3694 DRM_MODE_MATCH_TIMINGS | 3695 DRM_MODE_MATCH_FLAGS | 3696 DRM_MODE_MATCH_3D_FLAGS) && 3697 mode1->clock == mode2->clock; /* we want an exact match */ 3698 } 3699 3700 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 3701 const struct intel_link_m_n *m_n_2) 3702 { 3703 return m_n_1->tu == m_n_2->tu && 3704 m_n_1->data_m == m_n_2->data_m && 3705 m_n_1->data_n == m_n_2->data_n && 3706 m_n_1->link_m == m_n_2->link_m && 3707 m_n_1->link_n == m_n_2->link_n; 3708 } 3709 3710 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 3711 const struct intel_crtc_state *crtc_state2) 3712 { 3713 return crtc_state1->hw.active && crtc_state2->hw.active && 3714 crtc_state1->output_types == crtc_state2->output_types && 3715 crtc_state1->output_format == crtc_state2->output_format && 3716 crtc_state1->lane_count == crtc_state2->lane_count && 3717 crtc_state1->port_clock == crtc_state2->port_clock && 3718 mode_equal(&crtc_state1->hw.adjusted_mode, 3719 &crtc_state2->hw.adjusted_mode) && 3720 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 3721 } 3722 3723 static u8 3724 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 3725 int tile_group_id) 3726 { 3727 struct drm_connector *connector; 3728 const struct drm_connector_state *conn_state; 3729 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 3730 struct intel_atomic_state *state = 3731 to_intel_atomic_state(ref_crtc_state->uapi.state); 3732 u8 transcoders = 0; 3733 int i; 3734 3735 /* 3736 * We don't enable port sync on BDW due to missing w/as and 3737 * due to not having adjusted the modeset sequence appropriately. 3738 */ 3739 if (DISPLAY_VER(dev_priv) < 9) 3740 return 0; 3741 3742 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 3743 return 0; 3744 3745 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 3746 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 3747 const struct intel_crtc_state *crtc_state; 3748 3749 if (!crtc) 3750 continue; 3751 3752 if (!connector->has_tile || 3753 connector->tile_group->id != 3754 tile_group_id) 3755 continue; 3756 crtc_state = intel_atomic_get_new_crtc_state(state, 3757 crtc); 3758 if (!crtcs_port_sync_compatible(ref_crtc_state, 3759 crtc_state)) 3760 continue; 3761 transcoders |= BIT(crtc_state->cpu_transcoder); 3762 } 3763 3764 return transcoders; 3765 } 3766 3767 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 3768 struct intel_crtc_state *crtc_state, 3769 struct drm_connector_state *conn_state) 3770 { 3771 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3772 struct drm_connector *connector = conn_state->connector; 3773 u8 port_sync_transcoders = 0; 3774 3775 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]", 3776 encoder->base.base.id, encoder->base.name, 3777 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 3778 3779 if (connector->has_tile) 3780 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 3781 connector->tile_group->id); 3782 3783 /* 3784 * EDP Transcoders cannot be ensalved 3785 * make them a master always when present 3786 */ 3787 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 3788 crtc_state->master_transcoder = TRANSCODER_EDP; 3789 else 3790 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 3791 3792 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 3793 crtc_state->master_transcoder = INVALID_TRANSCODER; 3794 crtc_state->sync_mode_slaves_mask = 3795 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 3796 } 3797 3798 return 0; 3799 } 3800 3801 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 3802 { 3803 struct drm_i915_private *i915 = to_i915(encoder->dev); 3804 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 3805 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 3806 3807 intel_dp_encoder_flush_work(encoder); 3808 if (intel_phy_is_tc(i915, phy)) 3809 intel_tc_port_flush_work(dig_port); 3810 intel_display_power_flush_work(i915); 3811 3812 drm_encoder_cleanup(encoder); 3813 kfree(dig_port->hdcp_port_data.streams); 3814 kfree(dig_port); 3815 } 3816 3817 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 3818 { 3819 struct drm_i915_private *i915 = to_i915(encoder->dev); 3820 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 3821 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 3822 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 3823 3824 intel_dp->reset_link_params = true; 3825 3826 intel_pps_encoder_reset(intel_dp); 3827 3828 if (intel_phy_is_tc(i915, phy)) 3829 intel_tc_port_init_mode(dig_port); 3830 } 3831 3832 static const struct drm_encoder_funcs intel_ddi_funcs = { 3833 .reset = intel_ddi_encoder_reset, 3834 .destroy = intel_ddi_encoder_destroy, 3835 }; 3836 3837 static struct intel_connector * 3838 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 3839 { 3840 struct intel_connector *connector; 3841 enum port port = dig_port->base.port; 3842 3843 connector = intel_connector_alloc(); 3844 if (!connector) 3845 return NULL; 3846 3847 dig_port->dp.output_reg = DDI_BUF_CTL(port); 3848 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 3849 dig_port->dp.set_link_train = intel_ddi_set_link_train; 3850 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 3851 3852 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 3853 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 3854 3855 if (!intel_dp_init_connector(dig_port, connector)) { 3856 kfree(connector); 3857 return NULL; 3858 } 3859 3860 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 3861 struct drm_device *dev = dig_port->base.base.dev; 3862 struct drm_privacy_screen *privacy_screen; 3863 3864 privacy_screen = drm_privacy_screen_get(dev->dev, NULL); 3865 if (!IS_ERR(privacy_screen)) { 3866 drm_connector_attach_privacy_screen_provider(&connector->base, 3867 privacy_screen); 3868 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 3869 drm_warn(dev, "Error getting privacy-screen\n"); 3870 } 3871 } 3872 3873 return connector; 3874 } 3875 3876 static int modeset_pipe(struct drm_crtc *crtc, 3877 struct drm_modeset_acquire_ctx *ctx) 3878 { 3879 struct drm_atomic_state *state; 3880 struct drm_crtc_state *crtc_state; 3881 int ret; 3882 3883 state = drm_atomic_state_alloc(crtc->dev); 3884 if (!state) 3885 return -ENOMEM; 3886 3887 state->acquire_ctx = ctx; 3888 3889 crtc_state = drm_atomic_get_crtc_state(state, crtc); 3890 if (IS_ERR(crtc_state)) { 3891 ret = PTR_ERR(crtc_state); 3892 goto out; 3893 } 3894 3895 crtc_state->connectors_changed = true; 3896 3897 ret = drm_atomic_commit(state); 3898 out: 3899 drm_atomic_state_put(state); 3900 3901 return ret; 3902 } 3903 3904 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 3905 struct drm_modeset_acquire_ctx *ctx) 3906 { 3907 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3908 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 3909 struct intel_connector *connector = hdmi->attached_connector; 3910 struct i2c_adapter *adapter = 3911 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 3912 struct drm_connector_state *conn_state; 3913 struct intel_crtc_state *crtc_state; 3914 struct intel_crtc *crtc; 3915 u8 config; 3916 int ret; 3917 3918 if (!connector || connector->base.status != connector_status_connected) 3919 return 0; 3920 3921 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 3922 ctx); 3923 if (ret) 3924 return ret; 3925 3926 conn_state = connector->base.state; 3927 3928 crtc = to_intel_crtc(conn_state->crtc); 3929 if (!crtc) 3930 return 0; 3931 3932 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 3933 if (ret) 3934 return ret; 3935 3936 crtc_state = to_intel_crtc_state(crtc->base.state); 3937 3938 drm_WARN_ON(&dev_priv->drm, 3939 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 3940 3941 if (!crtc_state->hw.active) 3942 return 0; 3943 3944 if (!crtc_state->hdmi_high_tmds_clock_ratio && 3945 !crtc_state->hdmi_scrambling) 3946 return 0; 3947 3948 if (conn_state->commit && 3949 !try_wait_for_completion(&conn_state->commit->hw_done)) 3950 return 0; 3951 3952 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 3953 if (ret < 0) { 3954 drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n", 3955 ret); 3956 return 0; 3957 } 3958 3959 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 3960 crtc_state->hdmi_high_tmds_clock_ratio && 3961 !!(config & SCDC_SCRAMBLING_ENABLE) == 3962 crtc_state->hdmi_scrambling) 3963 return 0; 3964 3965 /* 3966 * HDMI 2.0 says that one should not send scrambled data 3967 * prior to configuring the sink scrambling, and that 3968 * TMDS clock/data transmission should be suspended when 3969 * changing the TMDS clock rate in the sink. So let's 3970 * just do a full modeset here, even though some sinks 3971 * would be perfectly happy if were to just reconfigure 3972 * the SCDC settings on the fly. 3973 */ 3974 return modeset_pipe(&crtc->base, ctx); 3975 } 3976 3977 static enum intel_hotplug_state 3978 intel_ddi_hotplug(struct intel_encoder *encoder, 3979 struct intel_connector *connector) 3980 { 3981 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3982 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3983 struct intel_dp *intel_dp = &dig_port->dp; 3984 enum phy phy = intel_port_to_phy(i915, encoder->port); 3985 bool is_tc = intel_phy_is_tc(i915, phy); 3986 struct drm_modeset_acquire_ctx ctx; 3987 enum intel_hotplug_state state; 3988 int ret; 3989 3990 if (intel_dp->compliance.test_active && 3991 intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) { 3992 intel_dp_phy_test(encoder); 3993 /* just do the PHY test and nothing else */ 3994 return INTEL_HOTPLUG_UNCHANGED; 3995 } 3996 3997 state = intel_encoder_hotplug(encoder, connector); 3998 3999 drm_modeset_acquire_init(&ctx, 0); 4000 4001 for (;;) { 4002 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) 4003 ret = intel_hdmi_reset_link(encoder, &ctx); 4004 else 4005 ret = intel_dp_retrain_link(encoder, &ctx); 4006 4007 if (ret == -EDEADLK) { 4008 drm_modeset_backoff(&ctx); 4009 continue; 4010 } 4011 4012 break; 4013 } 4014 4015 drm_modeset_drop_locks(&ctx); 4016 drm_modeset_acquire_fini(&ctx); 4017 drm_WARN(encoder->base.dev, ret, 4018 "Acquiring modeset locks failed with %i\n", ret); 4019 4020 /* 4021 * Unpowered type-c dongles can take some time to boot and be 4022 * responsible, so here giving some time to those dongles to power up 4023 * and then retrying the probe. 4024 * 4025 * On many platforms the HDMI live state signal is known to be 4026 * unreliable, so we can't use it to detect if a sink is connected or 4027 * not. Instead we detect if it's connected based on whether we can 4028 * read the EDID or not. That in turn has a problem during disconnect, 4029 * since the HPD interrupt may be raised before the DDC lines get 4030 * disconnected (due to how the required length of DDC vs. HPD 4031 * connector pins are specified) and so we'll still be able to get a 4032 * valid EDID. To solve this schedule another detection cycle if this 4033 * time around we didn't detect any change in the sink's connection 4034 * status. 4035 * 4036 * Type-c connectors which get their HPD signal deasserted then 4037 * reasserted, without unplugging/replugging the sink from the 4038 * connector, introduce a delay until the AUX channel communication 4039 * becomes functional. Retry the detection for 5 seconds on type-c 4040 * connectors to account for this delay. 4041 */ 4042 if (state == INTEL_HOTPLUG_UNCHANGED && 4043 connector->hotplug_retries < (is_tc ? 5 : 1) && 4044 !dig_port->dp.is_mst) 4045 state = INTEL_HOTPLUG_RETRY; 4046 4047 return state; 4048 } 4049 4050 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4051 { 4052 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4053 u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin]; 4054 4055 return intel_de_read(dev_priv, SDEISR) & bit; 4056 } 4057 4058 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4059 { 4060 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4061 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4062 4063 return intel_de_read(dev_priv, DEISR) & bit; 4064 } 4065 4066 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4067 { 4068 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4069 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4070 4071 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; 4072 } 4073 4074 static struct intel_connector * 4075 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4076 { 4077 struct intel_connector *connector; 4078 enum port port = dig_port->base.port; 4079 4080 connector = intel_connector_alloc(); 4081 if (!connector) 4082 return NULL; 4083 4084 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4085 intel_hdmi_init_connector(dig_port, connector); 4086 4087 return connector; 4088 } 4089 4090 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4091 { 4092 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4093 4094 if (dig_port->base.port != PORT_A) 4095 return false; 4096 4097 if (dig_port->saved_port_bits & DDI_A_4_LANES) 4098 return false; 4099 4100 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4101 * supported configuration 4102 */ 4103 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4104 return true; 4105 4106 return false; 4107 } 4108 4109 static int 4110 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4111 { 4112 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4113 enum port port = dig_port->base.port; 4114 int max_lanes = 4; 4115 4116 if (DISPLAY_VER(dev_priv) >= 11) 4117 return max_lanes; 4118 4119 if (port == PORT_A || port == PORT_E) { 4120 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4121 max_lanes = port == PORT_A ? 4 : 0; 4122 else 4123 /* Both A and E share 2 lanes */ 4124 max_lanes = 2; 4125 } 4126 4127 /* 4128 * Some BIOS might fail to set this bit on port A if eDP 4129 * wasn't lit up at boot. Force this bit set when needed 4130 * so we use the proper lane count for our calculations. 4131 */ 4132 if (intel_ddi_a_force_4_lanes(dig_port)) { 4133 drm_dbg_kms(&dev_priv->drm, 4134 "Forcing DDI_A_4_LANES for port A\n"); 4135 dig_port->saved_port_bits |= DDI_A_4_LANES; 4136 max_lanes = 4; 4137 } 4138 4139 return max_lanes; 4140 } 4141 4142 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv, 4143 enum port port) 4144 { 4145 if (port >= PORT_D_XELPD) 4146 return HPD_PORT_D + port - PORT_D_XELPD; 4147 else if (port >= PORT_TC1) 4148 return HPD_PORT_TC1 + port - PORT_TC1; 4149 else 4150 return HPD_PORT_A + port - PORT_A; 4151 } 4152 4153 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, 4154 enum port port) 4155 { 4156 if (port >= PORT_TC1) 4157 return HPD_PORT_C + port - PORT_TC1; 4158 else 4159 return HPD_PORT_A + port - PORT_A; 4160 } 4161 4162 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, 4163 enum port port) 4164 { 4165 if (port >= PORT_TC1) 4166 return HPD_PORT_TC1 + port - PORT_TC1; 4167 else 4168 return HPD_PORT_A + port - PORT_A; 4169 } 4170 4171 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, 4172 enum port port) 4173 { 4174 if (HAS_PCH_TGP(dev_priv)) 4175 return tgl_hpd_pin(dev_priv, port); 4176 4177 if (port >= PORT_TC1) 4178 return HPD_PORT_C + port - PORT_TC1; 4179 else 4180 return HPD_PORT_A + port - PORT_A; 4181 } 4182 4183 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, 4184 enum port port) 4185 { 4186 if (port >= PORT_C) 4187 return HPD_PORT_TC1 + port - PORT_C; 4188 else 4189 return HPD_PORT_A + port - PORT_A; 4190 } 4191 4192 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, 4193 enum port port) 4194 { 4195 if (port == PORT_D) 4196 return HPD_PORT_A; 4197 4198 if (HAS_PCH_TGP(dev_priv)) 4199 return icl_hpd_pin(dev_priv, port); 4200 4201 return HPD_PORT_A + port - PORT_A; 4202 } 4203 4204 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) 4205 { 4206 if (HAS_PCH_TGP(dev_priv)) 4207 return icl_hpd_pin(dev_priv, port); 4208 4209 return HPD_PORT_A + port - PORT_A; 4210 } 4211 4212 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port) 4213 { 4214 if (DISPLAY_VER(i915) >= 12) 4215 return port >= PORT_TC1; 4216 else if (DISPLAY_VER(i915) >= 11) 4217 return port >= PORT_C; 4218 else 4219 return false; 4220 } 4221 4222 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 4223 { 4224 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4225 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4226 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4227 enum phy phy = intel_port_to_phy(i915, encoder->port); 4228 4229 intel_dp_encoder_suspend(encoder); 4230 4231 if (!intel_phy_is_tc(i915, phy)) 4232 return; 4233 4234 intel_tc_port_flush_work(dig_port); 4235 } 4236 4237 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 4238 { 4239 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4240 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4241 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4242 enum phy phy = intel_port_to_phy(i915, encoder->port); 4243 4244 intel_dp_encoder_shutdown(encoder); 4245 intel_hdmi_encoder_shutdown(encoder); 4246 4247 if (!intel_phy_is_tc(i915, phy)) 4248 return; 4249 4250 intel_tc_port_flush_work(dig_port); 4251 } 4252 4253 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 4254 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 4255 4256 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 4257 { 4258 struct intel_digital_port *dig_port; 4259 struct intel_encoder *encoder; 4260 const struct intel_bios_encoder_data *devdata; 4261 bool init_hdmi, init_dp; 4262 enum phy phy = intel_port_to_phy(dev_priv, port); 4263 4264 /* 4265 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 4266 * have taken over some of the PHYs and made them unavailable to the 4267 * driver. In that case we should skip initializing the corresponding 4268 * outputs. 4269 */ 4270 if (intel_hti_uses_phy(dev_priv, phy)) { 4271 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", 4272 port_name(port), phy_name(phy)); 4273 return; 4274 } 4275 4276 devdata = intel_bios_encoder_data_lookup(dev_priv, port); 4277 if (!devdata) { 4278 drm_dbg_kms(&dev_priv->drm, 4279 "VBT says port %c is not present\n", 4280 port_name(port)); 4281 return; 4282 } 4283 4284 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 4285 intel_bios_encoder_supports_hdmi(devdata); 4286 init_dp = intel_bios_encoder_supports_dp(devdata); 4287 4288 if (intel_bios_is_lspcon_present(dev_priv, port)) { 4289 /* 4290 * Lspcon device needs to be driven with DP connector 4291 * with special detection sequence. So make sure DP 4292 * is initialized before lspcon. 4293 */ 4294 init_dp = true; 4295 init_hdmi = false; 4296 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", 4297 port_name(port)); 4298 } 4299 4300 if (!init_dp && !init_hdmi) { 4301 drm_dbg_kms(&dev_priv->drm, 4302 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 4303 port_name(port)); 4304 return; 4305 } 4306 4307 if (intel_phy_is_snps(dev_priv, phy) && 4308 dev_priv->snps_phy_failed_calibration & BIT(phy)) { 4309 drm_dbg_kms(&dev_priv->drm, 4310 "SNPS PHY %c failed to calibrate, proceeding anyway\n", 4311 phy_name(phy)); 4312 } 4313 4314 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 4315 if (!dig_port) 4316 return; 4317 4318 encoder = &dig_port->base; 4319 encoder->devdata = devdata; 4320 4321 if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) { 4322 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4323 DRM_MODE_ENCODER_TMDS, 4324 "DDI %c/PHY %c", 4325 port_name(port - PORT_D_XELPD + PORT_D), 4326 phy_name(phy)); 4327 } else if (DISPLAY_VER(dev_priv) >= 12) { 4328 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4329 4330 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4331 DRM_MODE_ENCODER_TMDS, 4332 "DDI %s%c/PHY %s%c", 4333 port >= PORT_TC1 ? "TC" : "", 4334 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 4335 tc_port != TC_PORT_NONE ? "TC" : "", 4336 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4337 } else if (DISPLAY_VER(dev_priv) >= 11) { 4338 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4339 4340 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4341 DRM_MODE_ENCODER_TMDS, 4342 "DDI %c%s/PHY %s%c", 4343 port_name(port), 4344 port >= PORT_C ? " (TC)" : "", 4345 tc_port != TC_PORT_NONE ? "TC" : "", 4346 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4347 } else { 4348 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4349 DRM_MODE_ENCODER_TMDS, 4350 "DDI %c/PHY %c", port_name(port), phy_name(phy)); 4351 } 4352 4353 mutex_init(&dig_port->hdcp_mutex); 4354 dig_port->num_hdcp_streams = 0; 4355 4356 encoder->hotplug = intel_ddi_hotplug; 4357 encoder->compute_output_type = intel_ddi_compute_output_type; 4358 encoder->compute_config = intel_ddi_compute_config; 4359 encoder->compute_config_late = intel_ddi_compute_config_late; 4360 encoder->enable = intel_enable_ddi; 4361 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 4362 encoder->pre_enable = intel_ddi_pre_enable; 4363 encoder->disable = intel_disable_ddi; 4364 encoder->post_disable = intel_ddi_post_disable; 4365 encoder->update_pipe = intel_ddi_update_pipe; 4366 encoder->get_hw_state = intel_ddi_get_hw_state; 4367 encoder->sync_state = intel_ddi_sync_state; 4368 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 4369 encoder->suspend = intel_ddi_encoder_suspend; 4370 encoder->shutdown = intel_ddi_encoder_shutdown; 4371 encoder->get_power_domains = intel_ddi_get_power_domains; 4372 4373 encoder->type = INTEL_OUTPUT_DDI; 4374 encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port); 4375 encoder->port = port; 4376 encoder->cloneable = 0; 4377 encoder->pipe_mask = ~0; 4378 4379 if (IS_DG2(dev_priv)) { 4380 encoder->enable_clock = intel_mpllb_enable; 4381 encoder->disable_clock = intel_mpllb_disable; 4382 encoder->get_config = dg2_ddi_get_config; 4383 } else if (IS_ALDERLAKE_S(dev_priv)) { 4384 encoder->enable_clock = adls_ddi_enable_clock; 4385 encoder->disable_clock = adls_ddi_disable_clock; 4386 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 4387 encoder->get_config = adls_ddi_get_config; 4388 } else if (IS_ROCKETLAKE(dev_priv)) { 4389 encoder->enable_clock = rkl_ddi_enable_clock; 4390 encoder->disable_clock = rkl_ddi_disable_clock; 4391 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 4392 encoder->get_config = rkl_ddi_get_config; 4393 } else if (IS_DG1(dev_priv)) { 4394 encoder->enable_clock = dg1_ddi_enable_clock; 4395 encoder->disable_clock = dg1_ddi_disable_clock; 4396 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 4397 encoder->get_config = dg1_ddi_get_config; 4398 } else if (IS_JSL_EHL(dev_priv)) { 4399 if (intel_ddi_is_tc(dev_priv, port)) { 4400 encoder->enable_clock = jsl_ddi_tc_enable_clock; 4401 encoder->disable_clock = jsl_ddi_tc_disable_clock; 4402 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 4403 encoder->get_config = icl_ddi_combo_get_config; 4404 } else { 4405 encoder->enable_clock = icl_ddi_combo_enable_clock; 4406 encoder->disable_clock = icl_ddi_combo_disable_clock; 4407 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 4408 encoder->get_config = icl_ddi_combo_get_config; 4409 } 4410 } else if (DISPLAY_VER(dev_priv) >= 11) { 4411 if (intel_ddi_is_tc(dev_priv, port)) { 4412 encoder->enable_clock = icl_ddi_tc_enable_clock; 4413 encoder->disable_clock = icl_ddi_tc_disable_clock; 4414 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 4415 encoder->get_config = icl_ddi_tc_get_config; 4416 } else { 4417 encoder->enable_clock = icl_ddi_combo_enable_clock; 4418 encoder->disable_clock = icl_ddi_combo_disable_clock; 4419 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 4420 encoder->get_config = icl_ddi_combo_get_config; 4421 } 4422 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 4423 /* BXT/GLK have fixed PLL->port mapping */ 4424 encoder->get_config = bxt_ddi_get_config; 4425 } else if (DISPLAY_VER(dev_priv) == 9) { 4426 encoder->enable_clock = skl_ddi_enable_clock; 4427 encoder->disable_clock = skl_ddi_disable_clock; 4428 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 4429 encoder->get_config = skl_ddi_get_config; 4430 } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 4431 encoder->enable_clock = hsw_ddi_enable_clock; 4432 encoder->disable_clock = hsw_ddi_disable_clock; 4433 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 4434 encoder->get_config = hsw_ddi_get_config; 4435 } 4436 4437 if (IS_DG2(dev_priv)) { 4438 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 4439 } else if (DISPLAY_VER(dev_priv) >= 12) { 4440 if (intel_phy_is_combo(dev_priv, phy)) 4441 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 4442 else 4443 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 4444 } else if (DISPLAY_VER(dev_priv) >= 11) { 4445 if (intel_phy_is_combo(dev_priv, phy)) 4446 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 4447 else 4448 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 4449 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 4450 encoder->set_signal_levels = bxt_ddi_phy_set_signal_levels; 4451 } else { 4452 encoder->set_signal_levels = hsw_set_signal_levels; 4453 } 4454 4455 intel_ddi_buf_trans_init(encoder); 4456 4457 if (DISPLAY_VER(dev_priv) >= 13) 4458 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port); 4459 else if (IS_DG1(dev_priv)) 4460 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); 4461 else if (IS_ROCKETLAKE(dev_priv)) 4462 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); 4463 else if (DISPLAY_VER(dev_priv) >= 12) 4464 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); 4465 else if (IS_JSL_EHL(dev_priv)) 4466 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); 4467 else if (DISPLAY_VER(dev_priv) == 11) 4468 encoder->hpd_pin = icl_hpd_pin(dev_priv, port); 4469 else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 4470 encoder->hpd_pin = skl_hpd_pin(dev_priv, port); 4471 else 4472 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 4473 4474 if (DISPLAY_VER(dev_priv) >= 11) 4475 dig_port->saved_port_bits = 4476 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 4477 & DDI_BUF_PORT_REVERSAL; 4478 else 4479 dig_port->saved_port_bits = 4480 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 4481 & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 4482 4483 if (intel_bios_is_lane_reversal_needed(dev_priv, port)) 4484 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL; 4485 4486 dig_port->dp.output_reg = INVALID_MMIO_REG; 4487 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 4488 dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 4489 4490 if (intel_phy_is_tc(dev_priv, phy)) { 4491 bool is_legacy = 4492 !intel_bios_encoder_supports_typec_usb(devdata) && 4493 !intel_bios_encoder_supports_tbt(devdata); 4494 4495 intel_tc_port_init(dig_port, is_legacy); 4496 4497 encoder->update_prepare = intel_ddi_update_prepare; 4498 encoder->update_complete = intel_ddi_update_complete; 4499 } 4500 4501 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 4502 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(dev_priv, port); 4503 4504 if (init_dp) { 4505 if (!intel_ddi_init_dp_connector(dig_port)) 4506 goto err; 4507 4508 dig_port->hpd_pulse = intel_dp_hpd_pulse; 4509 4510 if (dig_port->dp.mso_link_count) 4511 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv); 4512 } 4513 4514 /* In theory we don't need the encoder->type check, but leave it just in 4515 * case we have some really bad VBTs... */ 4516 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 4517 if (!intel_ddi_init_hdmi_connector(dig_port)) 4518 goto err; 4519 } 4520 4521 if (DISPLAY_VER(dev_priv) >= 11) { 4522 if (intel_phy_is_tc(dev_priv, phy)) 4523 dig_port->connected = intel_tc_port_connected; 4524 else 4525 dig_port->connected = lpt_digital_port_connected; 4526 } else if (DISPLAY_VER(dev_priv) >= 8) { 4527 if (port == PORT_A || IS_GEMINILAKE(dev_priv) || 4528 IS_BROXTON(dev_priv)) 4529 dig_port->connected = bdw_digital_port_connected; 4530 else 4531 dig_port->connected = lpt_digital_port_connected; 4532 } else { 4533 if (port == PORT_A) 4534 dig_port->connected = hsw_digital_port_connected; 4535 else 4536 dig_port->connected = lpt_digital_port_connected; 4537 } 4538 4539 intel_infoframe_init(dig_port); 4540 4541 return; 4542 4543 err: 4544 drm_encoder_cleanup(&encoder->base); 4545 kfree(dig_port); 4546 } 4547