1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <linux/string_helpers.h> 29 30 #include <drm/display/drm_scdc_helper.h> 31 #include <drm/drm_privacy_screen_consumer.h> 32 33 #include "i915_drv.h" 34 #include "i915_reg.h" 35 #include "intel_audio.h" 36 #include "intel_audio_regs.h" 37 #include "intel_backlight.h" 38 #include "intel_combo_phy.h" 39 #include "intel_combo_phy_regs.h" 40 #include "intel_connector.h" 41 #include "intel_crtc.h" 42 #include "intel_ddi.h" 43 #include "intel_ddi_buf_trans.h" 44 #include "intel_de.h" 45 #include "intel_display_power.h" 46 #include "intel_display_types.h" 47 #include "intel_dkl_phy.h" 48 #include "intel_dkl_phy_regs.h" 49 #include "intel_dp.h" 50 #include "intel_dp_aux.h" 51 #include "intel_dp_link_training.h" 52 #include "intel_dp_mst.h" 53 #include "intel_dpio_phy.h" 54 #include "intel_dsi.h" 55 #include "intel_fdi.h" 56 #include "intel_fifo_underrun.h" 57 #include "intel_gmbus.h" 58 #include "intel_hdcp.h" 59 #include "intel_hdmi.h" 60 #include "intel_hotplug.h" 61 #include "intel_hti.h" 62 #include "intel_lspcon.h" 63 #include "intel_mg_phy_regs.h" 64 #include "intel_pps.h" 65 #include "intel_psr.h" 66 #include "intel_quirks.h" 67 #include "intel_snps_phy.h" 68 #include "intel_sprite.h" 69 #include "intel_tc.h" 70 #include "intel_vdsc.h" 71 #include "intel_vdsc_regs.h" 72 #include "intel_vrr.h" 73 #include "skl_scaler.h" 74 #include "skl_universal_plane.h" 75 76 static const u8 index_to_dp_signal_levels[] = { 77 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 78 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 79 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 80 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 81 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 82 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 83 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 84 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 85 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 86 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 87 }; 88 89 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 90 const struct intel_ddi_buf_trans *trans) 91 { 92 int level; 93 94 level = intel_bios_hdmi_level_shift(encoder->devdata); 95 if (level < 0) 96 level = trans->hdmi_default_entry; 97 98 return level; 99 } 100 101 static bool has_buf_trans_select(struct drm_i915_private *i915) 102 { 103 return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915); 104 } 105 106 static bool has_iboost(struct drm_i915_private *i915) 107 { 108 return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915); 109 } 110 111 /* 112 * Starting with Haswell, DDI port buffers must be programmed with correct 113 * values in advance. This function programs the correct values for 114 * DP/eDP/FDI use cases. 115 */ 116 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 117 const struct intel_crtc_state *crtc_state) 118 { 119 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 120 u32 iboost_bit = 0; 121 int i, n_entries; 122 enum port port = encoder->port; 123 const struct intel_ddi_buf_trans *trans; 124 125 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 126 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 127 return; 128 129 /* If we're boosting the current, set bit 31 of trans1 */ 130 if (has_iboost(dev_priv) && 131 intel_bios_dp_boost_level(encoder->devdata)) 132 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 133 134 for (i = 0; i < n_entries; i++) { 135 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 136 trans->entries[i].hsw.trans1 | iboost_bit); 137 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 138 trans->entries[i].hsw.trans2); 139 } 140 } 141 142 /* 143 * Starting with Haswell, DDI port buffers must be programmed with correct 144 * values in advance. This function programs the correct values for 145 * HDMI/DVI use cases. 146 */ 147 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 148 const struct intel_crtc_state *crtc_state) 149 { 150 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 151 int level = intel_ddi_level(encoder, crtc_state, 0); 152 u32 iboost_bit = 0; 153 int n_entries; 154 enum port port = encoder->port; 155 const struct intel_ddi_buf_trans *trans; 156 157 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 158 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 159 return; 160 161 /* If we're boosting the current, set bit 31 of trans1 */ 162 if (has_iboost(dev_priv) && 163 intel_bios_hdmi_boost_level(encoder->devdata)) 164 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 165 166 /* Entry 9 is for HDMI: */ 167 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 168 trans->entries[level].hsw.trans1 | iboost_bit); 169 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 170 trans->entries[level].hsw.trans2); 171 } 172 173 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 174 enum port port) 175 { 176 if (IS_BROXTON(dev_priv)) { 177 udelay(16); 178 return; 179 } 180 181 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 182 DDI_BUF_IS_IDLE), 8)) 183 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", 184 port_name(port)); 185 } 186 187 static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, 188 enum port port) 189 { 190 enum phy phy = intel_port_to_phy(dev_priv, port); 191 int timeout_us; 192 int ret; 193 194 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ 195 if (DISPLAY_VER(dev_priv) < 10) { 196 usleep_range(518, 1000); 197 return; 198 } 199 200 if (IS_DG2(dev_priv)) { 201 timeout_us = 1200; 202 } else if (DISPLAY_VER(dev_priv) >= 12) { 203 if (intel_phy_is_tc(dev_priv, phy)) 204 timeout_us = 3000; 205 else 206 timeout_us = 1000; 207 } else { 208 timeout_us = 500; 209 } 210 211 ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 212 DDI_BUF_IS_IDLE), timeout_us, 10, 10); 213 214 if (ret) 215 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", 216 port_name(port)); 217 } 218 219 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 220 { 221 switch (pll->info->id) { 222 case DPLL_ID_WRPLL1: 223 return PORT_CLK_SEL_WRPLL1; 224 case DPLL_ID_WRPLL2: 225 return PORT_CLK_SEL_WRPLL2; 226 case DPLL_ID_SPLL: 227 return PORT_CLK_SEL_SPLL; 228 case DPLL_ID_LCPLL_810: 229 return PORT_CLK_SEL_LCPLL_810; 230 case DPLL_ID_LCPLL_1350: 231 return PORT_CLK_SEL_LCPLL_1350; 232 case DPLL_ID_LCPLL_2700: 233 return PORT_CLK_SEL_LCPLL_2700; 234 default: 235 MISSING_CASE(pll->info->id); 236 return PORT_CLK_SEL_NONE; 237 } 238 } 239 240 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 241 const struct intel_crtc_state *crtc_state) 242 { 243 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 244 int clock = crtc_state->port_clock; 245 const enum intel_dpll_id id = pll->info->id; 246 247 switch (id) { 248 default: 249 /* 250 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 251 * here, so do warn if this get passed in 252 */ 253 MISSING_CASE(id); 254 return DDI_CLK_SEL_NONE; 255 case DPLL_ID_ICL_TBTPLL: 256 switch (clock) { 257 case 162000: 258 return DDI_CLK_SEL_TBT_162; 259 case 270000: 260 return DDI_CLK_SEL_TBT_270; 261 case 540000: 262 return DDI_CLK_SEL_TBT_540; 263 case 810000: 264 return DDI_CLK_SEL_TBT_810; 265 default: 266 MISSING_CASE(clock); 267 return DDI_CLK_SEL_NONE; 268 } 269 case DPLL_ID_ICL_MGPLL1: 270 case DPLL_ID_ICL_MGPLL2: 271 case DPLL_ID_ICL_MGPLL3: 272 case DPLL_ID_ICL_MGPLL4: 273 case DPLL_ID_TGL_MGPLL5: 274 case DPLL_ID_TGL_MGPLL6: 275 return DDI_CLK_SEL_MG; 276 } 277 } 278 279 static u32 ddi_buf_phy_link_rate(int port_clock) 280 { 281 switch (port_clock) { 282 case 162000: 283 return DDI_BUF_PHY_LINK_RATE(0); 284 case 216000: 285 return DDI_BUF_PHY_LINK_RATE(4); 286 case 243000: 287 return DDI_BUF_PHY_LINK_RATE(5); 288 case 270000: 289 return DDI_BUF_PHY_LINK_RATE(1); 290 case 324000: 291 return DDI_BUF_PHY_LINK_RATE(6); 292 case 432000: 293 return DDI_BUF_PHY_LINK_RATE(7); 294 case 540000: 295 return DDI_BUF_PHY_LINK_RATE(2); 296 case 810000: 297 return DDI_BUF_PHY_LINK_RATE(3); 298 default: 299 MISSING_CASE(port_clock); 300 return DDI_BUF_PHY_LINK_RATE(0); 301 } 302 } 303 304 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 305 const struct intel_crtc_state *crtc_state) 306 { 307 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 308 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 309 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 310 enum phy phy = intel_port_to_phy(i915, encoder->port); 311 312 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 313 intel_dp->DP = dig_port->saved_port_bits | 314 DDI_PORT_WIDTH(crtc_state->lane_count) | 315 DDI_BUF_TRANS_SELECT(0); 316 317 if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) { 318 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 319 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 320 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 321 } 322 } 323 324 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 325 enum port port) 326 { 327 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 328 329 switch (val) { 330 case DDI_CLK_SEL_NONE: 331 return 0; 332 case DDI_CLK_SEL_TBT_162: 333 return 162000; 334 case DDI_CLK_SEL_TBT_270: 335 return 270000; 336 case DDI_CLK_SEL_TBT_540: 337 return 540000; 338 case DDI_CLK_SEL_TBT_810: 339 return 810000; 340 default: 341 MISSING_CASE(val); 342 return 0; 343 } 344 } 345 346 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 347 { 348 /* CRT dotclock is determined via other means */ 349 if (pipe_config->has_pch_encoder) 350 return; 351 352 pipe_config->hw.adjusted_mode.crtc_clock = 353 intel_crtc_dotclock(pipe_config); 354 } 355 356 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 357 const struct drm_connector_state *conn_state) 358 { 359 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 360 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 361 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 362 u32 temp; 363 364 if (!intel_crtc_has_dp_encoder(crtc_state)) 365 return; 366 367 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 368 369 temp = DP_MSA_MISC_SYNC_CLOCK; 370 371 switch (crtc_state->pipe_bpp) { 372 case 18: 373 temp |= DP_MSA_MISC_6_BPC; 374 break; 375 case 24: 376 temp |= DP_MSA_MISC_8_BPC; 377 break; 378 case 30: 379 temp |= DP_MSA_MISC_10_BPC; 380 break; 381 case 36: 382 temp |= DP_MSA_MISC_12_BPC; 383 break; 384 default: 385 MISSING_CASE(crtc_state->pipe_bpp); 386 break; 387 } 388 389 /* nonsense combination */ 390 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 391 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 392 393 if (crtc_state->limited_color_range) 394 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 395 396 /* 397 * As per DP 1.2 spec section 2.3.4.3 while sending 398 * YCBCR 444 signals we should program MSA MISC1/0 fields with 399 * colorspace information. 400 */ 401 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 402 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 403 404 /* 405 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 406 * of Color Encoding Format and Content Color Gamut] while sending 407 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 408 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 409 */ 410 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 411 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 412 413 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp); 414 } 415 416 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 417 { 418 if (master_transcoder == TRANSCODER_EDP) 419 return 0; 420 else 421 return master_transcoder + 1; 422 } 423 424 static void 425 intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder, 426 const struct intel_crtc_state *crtc_state) 427 { 428 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 429 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 430 u32 val = 0; 431 432 if (intel_dp_is_uhbr(crtc_state)) 433 val = TRANS_DP2_128B132B_CHANNEL_CODING; 434 435 intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val); 436 } 437 438 /* 439 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 440 * 441 * Only intended to be used by intel_ddi_enable_transcoder_func() and 442 * intel_ddi_config_transcoder_func(). 443 */ 444 static u32 445 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 446 const struct intel_crtc_state *crtc_state) 447 { 448 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 449 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 450 enum pipe pipe = crtc->pipe; 451 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 452 enum port port = encoder->port; 453 u32 temp; 454 455 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 456 temp = TRANS_DDI_FUNC_ENABLE; 457 if (DISPLAY_VER(dev_priv) >= 12) 458 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 459 else 460 temp |= TRANS_DDI_SELECT_PORT(port); 461 462 switch (crtc_state->pipe_bpp) { 463 default: 464 MISSING_CASE(crtc_state->pipe_bpp); 465 fallthrough; 466 case 18: 467 temp |= TRANS_DDI_BPC_6; 468 break; 469 case 24: 470 temp |= TRANS_DDI_BPC_8; 471 break; 472 case 30: 473 temp |= TRANS_DDI_BPC_10; 474 break; 475 case 36: 476 temp |= TRANS_DDI_BPC_12; 477 break; 478 } 479 480 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 481 temp |= TRANS_DDI_PVSYNC; 482 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 483 temp |= TRANS_DDI_PHSYNC; 484 485 if (cpu_transcoder == TRANSCODER_EDP) { 486 switch (pipe) { 487 default: 488 MISSING_CASE(pipe); 489 fallthrough; 490 case PIPE_A: 491 /* On Haswell, can only use the always-on power well for 492 * eDP when not using the panel fitter, and when not 493 * using motion blur mitigation (which we don't 494 * support). */ 495 if (crtc_state->pch_pfit.force_thru) 496 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 497 else 498 temp |= TRANS_DDI_EDP_INPUT_A_ON; 499 break; 500 case PIPE_B: 501 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 502 break; 503 case PIPE_C: 504 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 505 break; 506 } 507 } 508 509 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 510 if (crtc_state->has_hdmi_sink) 511 temp |= TRANS_DDI_MODE_SELECT_HDMI; 512 else 513 temp |= TRANS_DDI_MODE_SELECT_DVI; 514 515 if (crtc_state->hdmi_scrambling) 516 temp |= TRANS_DDI_HDMI_SCRAMBLING; 517 if (crtc_state->hdmi_high_tmds_clock_ratio) 518 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 519 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 520 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 521 temp |= (crtc_state->fdi_lanes - 1) << 1; 522 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 523 if (intel_dp_is_uhbr(crtc_state)) 524 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 525 else 526 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 527 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 528 529 if (DISPLAY_VER(dev_priv) >= 12) { 530 enum transcoder master; 531 532 master = crtc_state->mst_master_transcoder; 533 drm_WARN_ON(&dev_priv->drm, 534 master == INVALID_TRANSCODER); 535 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 536 } 537 } else { 538 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 539 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 540 } 541 542 if (IS_DISPLAY_VER(dev_priv, 8, 10) && 543 crtc_state->master_transcoder != INVALID_TRANSCODER) { 544 u8 master_select = 545 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 546 547 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 548 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 549 } 550 551 return temp; 552 } 553 554 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 555 const struct intel_crtc_state *crtc_state) 556 { 557 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 558 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 559 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 560 561 if (DISPLAY_VER(dev_priv) >= 11) { 562 enum transcoder master_transcoder = crtc_state->master_transcoder; 563 u32 ctl2 = 0; 564 565 if (master_transcoder != INVALID_TRANSCODER) { 566 u8 master_select = 567 bdw_trans_port_sync_master_select(master_transcoder); 568 569 ctl2 |= PORT_SYNC_MODE_ENABLE | 570 PORT_SYNC_MODE_MASTER_SELECT(master_select); 571 } 572 573 intel_de_write(dev_priv, 574 TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2); 575 } 576 577 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 578 intel_ddi_transcoder_func_reg_val_get(encoder, 579 crtc_state)); 580 } 581 582 /* 583 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 584 * bit. 585 */ 586 static void 587 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 588 const struct intel_crtc_state *crtc_state) 589 { 590 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 591 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 592 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 593 u32 ctl; 594 595 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 596 ctl &= ~TRANS_DDI_FUNC_ENABLE; 597 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 598 } 599 600 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 601 { 602 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 603 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 604 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 605 u32 ctl; 606 607 if (DISPLAY_VER(dev_priv) >= 11) 608 intel_de_write(dev_priv, 609 TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0); 610 611 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 612 613 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 614 615 ctl &= ~TRANS_DDI_FUNC_ENABLE; 616 617 if (IS_DISPLAY_VER(dev_priv, 8, 10)) 618 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 619 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 620 621 if (DISPLAY_VER(dev_priv) >= 12) { 622 if (!intel_dp_mst_is_master_trans(crtc_state)) { 623 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 624 TRANS_DDI_MODE_SELECT_MASK); 625 } 626 } else { 627 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 628 } 629 630 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 631 632 if (intel_has_quirk(dev_priv, QUIRK_INCREASE_DDI_DISABLED_TIME) && 633 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 634 drm_dbg_kms(&dev_priv->drm, 635 "Quirk Increase DDI disabled time\n"); 636 /* Quirk time at 100ms for reliable operation */ 637 msleep(100); 638 } 639 } 640 641 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 642 enum transcoder cpu_transcoder, 643 bool enable, u32 hdcp_mask) 644 { 645 struct drm_device *dev = intel_encoder->base.dev; 646 struct drm_i915_private *dev_priv = to_i915(dev); 647 intel_wakeref_t wakeref; 648 int ret = 0; 649 650 wakeref = intel_display_power_get_if_enabled(dev_priv, 651 intel_encoder->power_domain); 652 if (drm_WARN_ON(dev, !wakeref)) 653 return -ENXIO; 654 655 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 656 hdcp_mask, enable ? hdcp_mask : 0); 657 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 658 return ret; 659 } 660 661 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 662 { 663 struct drm_device *dev = intel_connector->base.dev; 664 struct drm_i915_private *dev_priv = to_i915(dev); 665 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 666 int type = intel_connector->base.connector_type; 667 enum port port = encoder->port; 668 enum transcoder cpu_transcoder; 669 intel_wakeref_t wakeref; 670 enum pipe pipe = 0; 671 u32 tmp; 672 bool ret; 673 674 wakeref = intel_display_power_get_if_enabled(dev_priv, 675 encoder->power_domain); 676 if (!wakeref) 677 return false; 678 679 if (!encoder->get_hw_state(encoder, &pipe)) { 680 ret = false; 681 goto out; 682 } 683 684 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 685 cpu_transcoder = TRANSCODER_EDP; 686 else 687 cpu_transcoder = (enum transcoder) pipe; 688 689 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 690 691 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 692 case TRANS_DDI_MODE_SELECT_HDMI: 693 case TRANS_DDI_MODE_SELECT_DVI: 694 ret = type == DRM_MODE_CONNECTOR_HDMIA; 695 break; 696 697 case TRANS_DDI_MODE_SELECT_DP_SST: 698 ret = type == DRM_MODE_CONNECTOR_eDP || 699 type == DRM_MODE_CONNECTOR_DisplayPort; 700 break; 701 702 case TRANS_DDI_MODE_SELECT_DP_MST: 703 /* if the transcoder is in MST state then 704 * connector isn't connected */ 705 ret = false; 706 break; 707 708 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 709 if (HAS_DP20(dev_priv)) 710 /* 128b/132b */ 711 ret = false; 712 else 713 /* FDI */ 714 ret = type == DRM_MODE_CONNECTOR_VGA; 715 break; 716 717 default: 718 ret = false; 719 break; 720 } 721 722 out: 723 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 724 725 return ret; 726 } 727 728 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 729 u8 *pipe_mask, bool *is_dp_mst) 730 { 731 struct drm_device *dev = encoder->base.dev; 732 struct drm_i915_private *dev_priv = to_i915(dev); 733 enum port port = encoder->port; 734 intel_wakeref_t wakeref; 735 enum pipe p; 736 u32 tmp; 737 u8 mst_pipe_mask; 738 739 *pipe_mask = 0; 740 *is_dp_mst = false; 741 742 wakeref = intel_display_power_get_if_enabled(dev_priv, 743 encoder->power_domain); 744 if (!wakeref) 745 return; 746 747 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 748 if (!(tmp & DDI_BUF_CTL_ENABLE)) 749 goto out; 750 751 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { 752 tmp = intel_de_read(dev_priv, 753 TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 754 755 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 756 default: 757 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 758 fallthrough; 759 case TRANS_DDI_EDP_INPUT_A_ON: 760 case TRANS_DDI_EDP_INPUT_A_ONOFF: 761 *pipe_mask = BIT(PIPE_A); 762 break; 763 case TRANS_DDI_EDP_INPUT_B_ONOFF: 764 *pipe_mask = BIT(PIPE_B); 765 break; 766 case TRANS_DDI_EDP_INPUT_C_ONOFF: 767 *pipe_mask = BIT(PIPE_C); 768 break; 769 } 770 771 goto out; 772 } 773 774 mst_pipe_mask = 0; 775 for_each_pipe(dev_priv, p) { 776 enum transcoder cpu_transcoder = (enum transcoder)p; 777 unsigned int port_mask, ddi_select; 778 intel_wakeref_t trans_wakeref; 779 780 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 781 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 782 if (!trans_wakeref) 783 continue; 784 785 if (DISPLAY_VER(dev_priv) >= 12) { 786 port_mask = TGL_TRANS_DDI_PORT_MASK; 787 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 788 } else { 789 port_mask = TRANS_DDI_PORT_MASK; 790 ddi_select = TRANS_DDI_SELECT_PORT(port); 791 } 792 793 tmp = intel_de_read(dev_priv, 794 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 795 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 796 trans_wakeref); 797 798 if ((tmp & port_mask) != ddi_select) 799 continue; 800 801 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST || 802 (HAS_DP20(dev_priv) && 803 (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B)) 804 mst_pipe_mask |= BIT(p); 805 806 *pipe_mask |= BIT(p); 807 } 808 809 if (!*pipe_mask) 810 drm_dbg_kms(&dev_priv->drm, 811 "No pipe for [ENCODER:%d:%s] found\n", 812 encoder->base.base.id, encoder->base.name); 813 814 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 815 drm_dbg_kms(&dev_priv->drm, 816 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 817 encoder->base.base.id, encoder->base.name, 818 *pipe_mask); 819 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 820 } 821 822 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 823 drm_dbg_kms(&dev_priv->drm, 824 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", 825 encoder->base.base.id, encoder->base.name, 826 *pipe_mask, mst_pipe_mask); 827 else 828 *is_dp_mst = mst_pipe_mask; 829 830 out: 831 if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) { 832 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 833 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 834 BXT_PHY_LANE_POWERDOWN_ACK | 835 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 836 drm_err(&dev_priv->drm, 837 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 838 encoder->base.base.id, encoder->base.name, tmp); 839 } 840 841 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 842 } 843 844 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 845 enum pipe *pipe) 846 { 847 u8 pipe_mask; 848 bool is_mst; 849 850 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 851 852 if (is_mst || !pipe_mask) 853 return false; 854 855 *pipe = ffs(pipe_mask) - 1; 856 857 return true; 858 } 859 860 static enum intel_display_power_domain 861 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port, 862 const struct intel_crtc_state *crtc_state) 863 { 864 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 865 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 866 867 /* 868 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 869 * DC states enabled at the same time, while for driver initiated AUX 870 * transfers we need the same AUX IOs to be powered but with DC states 871 * disabled. Accordingly use the AUX_IO_<port> power domain here which 872 * leaves DC states enabled. 873 * 874 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require 875 * AUX IO to be enabled, but all these require DC_OFF to be enabled as 876 * well, so we can acquire a wider AUX_<port> power domain reference 877 * instead of a specific AUX_IO_<port> reference without powering up any 878 * extra wells. 879 */ 880 if (intel_encoder_can_psr(&dig_port->base)) 881 return intel_display_power_aux_io_domain(i915, dig_port->aux_ch); 882 else if (DISPLAY_VER(i915) < 14 && 883 (intel_crtc_has_dp_encoder(crtc_state) || 884 intel_phy_is_tc(i915, phy))) 885 return intel_aux_power_domain(dig_port); 886 else 887 return POWER_DOMAIN_INVALID; 888 } 889 890 static void 891 main_link_aux_power_domain_get(struct intel_digital_port *dig_port, 892 const struct intel_crtc_state *crtc_state) 893 { 894 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 895 enum intel_display_power_domain domain = 896 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 897 898 drm_WARN_ON(&i915->drm, dig_port->aux_wakeref); 899 900 if (domain == POWER_DOMAIN_INVALID) 901 return; 902 903 dig_port->aux_wakeref = intel_display_power_get(i915, domain); 904 } 905 906 static void 907 main_link_aux_power_domain_put(struct intel_digital_port *dig_port, 908 const struct intel_crtc_state *crtc_state) 909 { 910 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 911 enum intel_display_power_domain domain = 912 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 913 intel_wakeref_t wf; 914 915 wf = fetch_and_zero(&dig_port->aux_wakeref); 916 if (!wf) 917 return; 918 919 intel_display_power_put(i915, domain, wf); 920 } 921 922 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 923 struct intel_crtc_state *crtc_state) 924 { 925 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 926 struct intel_digital_port *dig_port; 927 928 /* 929 * TODO: Add support for MST encoders. Atm, the following should never 930 * happen since fake-MST encoders don't set their get_power_domains() 931 * hook. 932 */ 933 if (drm_WARN_ON(&dev_priv->drm, 934 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 935 return; 936 937 dig_port = enc_to_dig_port(encoder); 938 939 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 940 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 941 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 942 dig_port->ddi_io_power_domain); 943 } 944 945 main_link_aux_power_domain_get(dig_port, crtc_state); 946 } 947 948 void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder, 949 const struct intel_crtc_state *crtc_state) 950 { 951 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 952 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 953 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 954 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 955 u32 val; 956 957 if (cpu_transcoder == TRANSCODER_EDP) 958 return; 959 960 if (DISPLAY_VER(dev_priv) >= 13) 961 val = TGL_TRANS_CLK_SEL_PORT(phy); 962 else if (DISPLAY_VER(dev_priv) >= 12) 963 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 964 else 965 val = TRANS_CLK_SEL_PORT(encoder->port); 966 967 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 968 } 969 970 void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state) 971 { 972 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 973 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 974 u32 val; 975 976 if (cpu_transcoder == TRANSCODER_EDP) 977 return; 978 979 if (DISPLAY_VER(dev_priv) >= 12) 980 val = TGL_TRANS_CLK_SEL_DISABLED; 981 else 982 val = TRANS_CLK_SEL_DISABLED; 983 984 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 985 } 986 987 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 988 enum port port, u8 iboost) 989 { 990 u32 tmp; 991 992 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 993 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 994 if (iboost) 995 tmp |= iboost << BALANCE_LEG_SHIFT(port); 996 else 997 tmp |= BALANCE_LEG_DISABLE(port); 998 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 999 } 1000 1001 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 1002 const struct intel_crtc_state *crtc_state, 1003 int level) 1004 { 1005 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1006 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1007 u8 iboost; 1008 1009 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1010 iboost = intel_bios_hdmi_boost_level(encoder->devdata); 1011 else 1012 iboost = intel_bios_dp_boost_level(encoder->devdata); 1013 1014 if (iboost == 0) { 1015 const struct intel_ddi_buf_trans *trans; 1016 int n_entries; 1017 1018 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1019 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1020 return; 1021 1022 iboost = trans->entries[level].hsw.i_boost; 1023 } 1024 1025 /* Make sure that the requested I_boost is valid */ 1026 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 1027 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); 1028 return; 1029 } 1030 1031 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); 1032 1033 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 1034 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 1035 } 1036 1037 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1038 const struct intel_crtc_state *crtc_state) 1039 { 1040 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1041 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1042 int n_entries; 1043 1044 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1045 1046 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 1047 n_entries = 1; 1048 if (drm_WARN_ON(&dev_priv->drm, 1049 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1050 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1051 1052 return index_to_dp_signal_levels[n_entries - 1] & 1053 DP_TRAIN_VOLTAGE_SWING_MASK; 1054 } 1055 1056 /* 1057 * We assume that the full set of pre-emphasis values can be 1058 * used on all DDI platforms. Should that change we need to 1059 * rethink this code. 1060 */ 1061 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1062 { 1063 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1064 } 1065 1066 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1067 int lane) 1068 { 1069 if (crtc_state->port_clock > 600000) 1070 return 0; 1071 1072 if (crtc_state->lane_count == 4) 1073 return lane >= 1 ? LOADGEN_SELECT : 0; 1074 else 1075 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1076 } 1077 1078 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1079 const struct intel_crtc_state *crtc_state) 1080 { 1081 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1082 const struct intel_ddi_buf_trans *trans; 1083 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1084 int n_entries, ln; 1085 u32 val; 1086 1087 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1088 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1089 return; 1090 1091 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1092 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1093 1094 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1095 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1096 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, 1097 intel_dp->hobl_active ? val : 0); 1098 } 1099 1100 /* Set PORT_TX_DW5 */ 1101 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1102 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1103 TAP2_DISABLE | TAP3_DISABLE); 1104 val |= SCALING_MODE_SEL(0x2); 1105 val |= RTERM_SELECT(0x6); 1106 val |= TAP3_DISABLE; 1107 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1108 1109 /* Program PORT_TX_DW2 */ 1110 for (ln = 0; ln < 4; ln++) { 1111 int level = intel_ddi_level(encoder, crtc_state, ln); 1112 1113 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy), 1114 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1115 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1116 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1117 RCOMP_SCALAR(0x98)); 1118 } 1119 1120 /* Program PORT_TX_DW4 */ 1121 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1122 for (ln = 0; ln < 4; ln++) { 1123 int level = intel_ddi_level(encoder, crtc_state, ln); 1124 1125 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1126 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1127 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1128 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1129 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1130 } 1131 1132 /* Program PORT_TX_DW7 */ 1133 for (ln = 0; ln < 4; ln++) { 1134 int level = intel_ddi_level(encoder, crtc_state, ln); 1135 1136 intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy), 1137 N_SCALAR_MASK, 1138 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1139 } 1140 } 1141 1142 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1143 const struct intel_crtc_state *crtc_state) 1144 { 1145 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1146 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1147 u32 val; 1148 int ln; 1149 1150 /* 1151 * 1. If port type is eDP or DP, 1152 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1153 * else clear to 0b. 1154 */ 1155 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); 1156 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1157 val &= ~COMMON_KEEPER_EN; 1158 else 1159 val |= COMMON_KEEPER_EN; 1160 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 1161 1162 /* 2. Program loadgen select */ 1163 /* 1164 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1165 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1166 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1167 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1168 */ 1169 for (ln = 0; ln < 4; ln++) { 1170 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1171 LOADGEN_SELECT, 1172 icl_combo_phy_loadgen_select(crtc_state, ln)); 1173 } 1174 1175 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1176 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 1177 0, SUS_CLOCK_CONFIG); 1178 1179 /* 4. Clear training enable to change swing values */ 1180 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1181 val &= ~TX_TRAINING_EN; 1182 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1183 1184 /* 5. Program swing and de-emphasis */ 1185 icl_ddi_combo_vswing_program(encoder, crtc_state); 1186 1187 /* 6. Set training enable to trigger update */ 1188 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1189 val |= TX_TRAINING_EN; 1190 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1191 } 1192 1193 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1194 const struct intel_crtc_state *crtc_state) 1195 { 1196 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1197 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 1198 const struct intel_ddi_buf_trans *trans; 1199 int n_entries, ln; 1200 1201 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1202 return; 1203 1204 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1205 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1206 return; 1207 1208 for (ln = 0; ln < 2; ln++) { 1209 intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), 1210 CRI_USE_FS32, 0); 1211 intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), 1212 CRI_USE_FS32, 0); 1213 } 1214 1215 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1216 for (ln = 0; ln < 2; ln++) { 1217 int level; 1218 1219 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1220 1221 intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), 1222 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1223 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1224 1225 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1226 1227 intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), 1228 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1229 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1230 } 1231 1232 /* Program MG_TX_DRVCTRL with values from vswing table */ 1233 for (ln = 0; ln < 2; ln++) { 1234 int level; 1235 1236 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1237 1238 intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), 1239 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1240 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1241 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1242 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1243 CRI_TXDEEMPH_OVERRIDE_EN); 1244 1245 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1246 1247 intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), 1248 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1249 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1250 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1251 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1252 CRI_TXDEEMPH_OVERRIDE_EN); 1253 1254 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1255 } 1256 1257 /* 1258 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1259 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1260 * values from table for which TX1 and TX2 enabled. 1261 */ 1262 for (ln = 0; ln < 2; ln++) { 1263 intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port), 1264 CFG_LOW_RATE_LKREN_EN, 1265 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1266 } 1267 1268 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1269 for (ln = 0; ln < 2; ln++) { 1270 intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port), 1271 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1272 CFG_AMI_CK_DIV_OVERRIDE_EN, 1273 crtc_state->port_clock > 500000 ? 1274 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1275 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1276 1277 intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port), 1278 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1279 CFG_AMI_CK_DIV_OVERRIDE_EN, 1280 crtc_state->port_clock > 500000 ? 1281 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1282 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1283 } 1284 1285 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1286 for (ln = 0; ln < 2; ln++) { 1287 intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 1288 0, CRI_CALCINIT); 1289 intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 1290 0, CRI_CALCINIT); 1291 } 1292 } 1293 1294 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1295 const struct intel_crtc_state *crtc_state) 1296 { 1297 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1298 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 1299 const struct intel_ddi_buf_trans *trans; 1300 int n_entries, ln; 1301 1302 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1303 return; 1304 1305 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1306 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1307 return; 1308 1309 for (ln = 0; ln < 2; ln++) { 1310 int level; 1311 1312 intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); 1313 1314 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1315 1316 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln), 1317 DKL_TX_PRESHOOT_COEFF_MASK | 1318 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1319 DKL_TX_VSWING_CONTROL_MASK, 1320 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1321 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1322 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1323 1324 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1325 1326 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln), 1327 DKL_TX_PRESHOOT_COEFF_MASK | 1328 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1329 DKL_TX_VSWING_CONTROL_MASK, 1330 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1331 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1332 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1333 1334 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1335 DKL_TX_DP20BITMODE, 0); 1336 1337 if (IS_ALDERLAKE_P(dev_priv)) { 1338 u32 val; 1339 1340 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1341 if (ln == 0) { 1342 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1343 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); 1344 } else { 1345 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); 1346 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); 1347 } 1348 } else { 1349 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1350 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); 1351 } 1352 1353 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1354 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | 1355 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, 1356 val); 1357 } 1358 } 1359 } 1360 1361 static int translate_signal_level(struct intel_dp *intel_dp, 1362 u8 signal_levels) 1363 { 1364 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1365 int i; 1366 1367 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1368 if (index_to_dp_signal_levels[i] == signal_levels) 1369 return i; 1370 } 1371 1372 drm_WARN(&i915->drm, 1, 1373 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1374 signal_levels); 1375 1376 return 0; 1377 } 1378 1379 static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1380 const struct intel_crtc_state *crtc_state, 1381 int lane) 1382 { 1383 u8 train_set = intel_dp->train_set[lane]; 1384 1385 if (intel_dp_is_uhbr(crtc_state)) { 1386 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1387 } else { 1388 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1389 DP_TRAIN_PRE_EMPHASIS_MASK); 1390 1391 return translate_signal_level(intel_dp, signal_levels); 1392 } 1393 } 1394 1395 int intel_ddi_level(struct intel_encoder *encoder, 1396 const struct intel_crtc_state *crtc_state, 1397 int lane) 1398 { 1399 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1400 const struct intel_ddi_buf_trans *trans; 1401 int level, n_entries; 1402 1403 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1404 if (drm_WARN_ON_ONCE(&i915->drm, !trans)) 1405 return 0; 1406 1407 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1408 level = intel_ddi_hdmi_level(encoder, trans); 1409 else 1410 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1411 lane); 1412 1413 if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries)) 1414 level = n_entries - 1; 1415 1416 return level; 1417 } 1418 1419 static void 1420 hsw_set_signal_levels(struct intel_encoder *encoder, 1421 const struct intel_crtc_state *crtc_state) 1422 { 1423 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1424 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1425 int level = intel_ddi_level(encoder, crtc_state, 0); 1426 enum port port = encoder->port; 1427 u32 signal_levels; 1428 1429 if (has_iboost(dev_priv)) 1430 skl_ddi_set_iboost(encoder, crtc_state, level); 1431 1432 /* HDMI ignores the rest */ 1433 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1434 return; 1435 1436 signal_levels = DDI_BUF_TRANS_SELECT(level); 1437 1438 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1439 signal_levels); 1440 1441 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1442 intel_dp->DP |= signal_levels; 1443 1444 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 1445 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 1446 } 1447 1448 static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1449 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1450 { 1451 mutex_lock(&i915->display.dpll.lock); 1452 1453 intel_de_rmw(i915, reg, clk_sel_mask, clk_sel); 1454 1455 /* 1456 * "This step and the step before must be 1457 * done with separate register writes." 1458 */ 1459 intel_de_rmw(i915, reg, clk_off, 0); 1460 1461 mutex_unlock(&i915->display.dpll.lock); 1462 } 1463 1464 static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1465 u32 clk_off) 1466 { 1467 mutex_lock(&i915->display.dpll.lock); 1468 1469 intel_de_rmw(i915, reg, 0, clk_off); 1470 1471 mutex_unlock(&i915->display.dpll.lock); 1472 } 1473 1474 static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg, 1475 u32 clk_off) 1476 { 1477 return !(intel_de_read(i915, reg) & clk_off); 1478 } 1479 1480 static struct intel_shared_dpll * 1481 _icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg, 1482 u32 clk_sel_mask, u32 clk_sel_shift) 1483 { 1484 enum intel_dpll_id id; 1485 1486 id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift; 1487 1488 return intel_get_shared_dpll_by_id(i915, id); 1489 } 1490 1491 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1492 const struct intel_crtc_state *crtc_state) 1493 { 1494 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1495 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1496 enum phy phy = intel_port_to_phy(i915, encoder->port); 1497 1498 if (drm_WARN_ON(&i915->drm, !pll)) 1499 return; 1500 1501 _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1502 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1503 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1504 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1505 } 1506 1507 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1508 { 1509 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1510 enum phy phy = intel_port_to_phy(i915, encoder->port); 1511 1512 _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1513 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1514 } 1515 1516 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1517 { 1518 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1519 enum phy phy = intel_port_to_phy(i915, encoder->port); 1520 1521 return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy), 1522 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1523 } 1524 1525 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1526 { 1527 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1528 enum phy phy = intel_port_to_phy(i915, encoder->port); 1529 1530 return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy), 1531 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1532 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1533 } 1534 1535 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1536 const struct intel_crtc_state *crtc_state) 1537 { 1538 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1539 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1540 enum phy phy = intel_port_to_phy(i915, encoder->port); 1541 1542 if (drm_WARN_ON(&i915->drm, !pll)) 1543 return; 1544 1545 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1546 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1547 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1548 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1549 } 1550 1551 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1552 { 1553 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1554 enum phy phy = intel_port_to_phy(i915, encoder->port); 1555 1556 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1557 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1558 } 1559 1560 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1561 { 1562 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1563 enum phy phy = intel_port_to_phy(i915, encoder->port); 1564 1565 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1566 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1567 } 1568 1569 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1570 { 1571 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1572 enum phy phy = intel_port_to_phy(i915, encoder->port); 1573 1574 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1575 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1576 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1577 } 1578 1579 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1580 const struct intel_crtc_state *crtc_state) 1581 { 1582 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1583 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1584 enum phy phy = intel_port_to_phy(i915, encoder->port); 1585 1586 if (drm_WARN_ON(&i915->drm, !pll)) 1587 return; 1588 1589 /* 1590 * If we fail this, something went very wrong: first 2 PLLs should be 1591 * used by first 2 phys and last 2 PLLs by last phys 1592 */ 1593 if (drm_WARN_ON(&i915->drm, 1594 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1595 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1596 return; 1597 1598 _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1599 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1600 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1601 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1602 } 1603 1604 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1605 { 1606 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1607 enum phy phy = intel_port_to_phy(i915, encoder->port); 1608 1609 _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1610 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1611 } 1612 1613 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1614 { 1615 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1616 enum phy phy = intel_port_to_phy(i915, encoder->port); 1617 1618 return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy), 1619 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1620 } 1621 1622 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1623 { 1624 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1625 enum phy phy = intel_port_to_phy(i915, encoder->port); 1626 enum intel_dpll_id id; 1627 u32 val; 1628 1629 val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy)); 1630 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1631 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1632 id = val; 1633 1634 /* 1635 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1636 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1637 * bit for phy C and D. 1638 */ 1639 if (phy >= PHY_C) 1640 id += DPLL_ID_DG1_DPLL2; 1641 1642 return intel_get_shared_dpll_by_id(i915, id); 1643 } 1644 1645 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1646 const struct intel_crtc_state *crtc_state) 1647 { 1648 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1649 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1650 enum phy phy = intel_port_to_phy(i915, encoder->port); 1651 1652 if (drm_WARN_ON(&i915->drm, !pll)) 1653 return; 1654 1655 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1656 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1657 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1658 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1659 } 1660 1661 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1662 { 1663 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1664 enum phy phy = intel_port_to_phy(i915, encoder->port); 1665 1666 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1667 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1668 } 1669 1670 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1671 { 1672 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1673 enum phy phy = intel_port_to_phy(i915, encoder->port); 1674 1675 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1676 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1677 } 1678 1679 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1680 { 1681 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1682 enum phy phy = intel_port_to_phy(i915, encoder->port); 1683 1684 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1685 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1686 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1687 } 1688 1689 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1690 const struct intel_crtc_state *crtc_state) 1691 { 1692 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1693 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1694 enum port port = encoder->port; 1695 1696 if (drm_WARN_ON(&i915->drm, !pll)) 1697 return; 1698 1699 /* 1700 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1701 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1702 */ 1703 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1704 1705 icl_ddi_combo_enable_clock(encoder, crtc_state); 1706 } 1707 1708 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1709 { 1710 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1711 enum port port = encoder->port; 1712 1713 icl_ddi_combo_disable_clock(encoder); 1714 1715 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1716 } 1717 1718 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1719 { 1720 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1721 enum port port = encoder->port; 1722 u32 tmp; 1723 1724 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1725 1726 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1727 return false; 1728 1729 return icl_ddi_combo_is_clock_enabled(encoder); 1730 } 1731 1732 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1733 const struct intel_crtc_state *crtc_state) 1734 { 1735 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1736 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1737 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1738 enum port port = encoder->port; 1739 1740 if (drm_WARN_ON(&i915->drm, !pll)) 1741 return; 1742 1743 intel_de_write(i915, DDI_CLK_SEL(port), 1744 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1745 1746 mutex_lock(&i915->display.dpll.lock); 1747 1748 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1749 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1750 1751 mutex_unlock(&i915->display.dpll.lock); 1752 } 1753 1754 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1755 { 1756 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1757 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1758 enum port port = encoder->port; 1759 1760 mutex_lock(&i915->display.dpll.lock); 1761 1762 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1763 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1764 1765 mutex_unlock(&i915->display.dpll.lock); 1766 1767 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1768 } 1769 1770 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1771 { 1772 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1773 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1774 enum port port = encoder->port; 1775 u32 tmp; 1776 1777 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1778 1779 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1780 return false; 1781 1782 tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0); 1783 1784 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1785 } 1786 1787 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1788 { 1789 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1790 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1791 enum port port = encoder->port; 1792 enum intel_dpll_id id; 1793 u32 tmp; 1794 1795 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1796 1797 switch (tmp & DDI_CLK_SEL_MASK) { 1798 case DDI_CLK_SEL_TBT_162: 1799 case DDI_CLK_SEL_TBT_270: 1800 case DDI_CLK_SEL_TBT_540: 1801 case DDI_CLK_SEL_TBT_810: 1802 id = DPLL_ID_ICL_TBTPLL; 1803 break; 1804 case DDI_CLK_SEL_MG: 1805 id = icl_tc_port_to_pll_id(tc_port); 1806 break; 1807 default: 1808 MISSING_CASE(tmp); 1809 fallthrough; 1810 case DDI_CLK_SEL_NONE: 1811 return NULL; 1812 } 1813 1814 return intel_get_shared_dpll_by_id(i915, id); 1815 } 1816 1817 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1818 { 1819 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1820 enum intel_dpll_id id; 1821 1822 switch (encoder->port) { 1823 case PORT_A: 1824 id = DPLL_ID_SKL_DPLL0; 1825 break; 1826 case PORT_B: 1827 id = DPLL_ID_SKL_DPLL1; 1828 break; 1829 case PORT_C: 1830 id = DPLL_ID_SKL_DPLL2; 1831 break; 1832 default: 1833 MISSING_CASE(encoder->port); 1834 return NULL; 1835 } 1836 1837 return intel_get_shared_dpll_by_id(i915, id); 1838 } 1839 1840 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1841 const struct intel_crtc_state *crtc_state) 1842 { 1843 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1844 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1845 enum port port = encoder->port; 1846 1847 if (drm_WARN_ON(&i915->drm, !pll)) 1848 return; 1849 1850 mutex_lock(&i915->display.dpll.lock); 1851 1852 intel_de_rmw(i915, DPLL_CTRL2, 1853 DPLL_CTRL2_DDI_CLK_OFF(port) | 1854 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1855 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1856 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1857 1858 mutex_unlock(&i915->display.dpll.lock); 1859 } 1860 1861 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1862 { 1863 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1864 enum port port = encoder->port; 1865 1866 mutex_lock(&i915->display.dpll.lock); 1867 1868 intel_de_rmw(i915, DPLL_CTRL2, 1869 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1870 1871 mutex_unlock(&i915->display.dpll.lock); 1872 } 1873 1874 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1875 { 1876 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1877 enum port port = encoder->port; 1878 1879 /* 1880 * FIXME Not sure if the override affects both 1881 * the PLL selection and the CLK_OFF bit. 1882 */ 1883 return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 1884 } 1885 1886 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 1887 { 1888 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1889 enum port port = encoder->port; 1890 enum intel_dpll_id id; 1891 u32 tmp; 1892 1893 tmp = intel_de_read(i915, DPLL_CTRL2); 1894 1895 /* 1896 * FIXME Not sure if the override affects both 1897 * the PLL selection and the CLK_OFF bit. 1898 */ 1899 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 1900 return NULL; 1901 1902 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 1903 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 1904 1905 return intel_get_shared_dpll_by_id(i915, id); 1906 } 1907 1908 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 1909 const struct intel_crtc_state *crtc_state) 1910 { 1911 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1912 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1913 enum port port = encoder->port; 1914 1915 if (drm_WARN_ON(&i915->drm, !pll)) 1916 return; 1917 1918 intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 1919 } 1920 1921 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 1922 { 1923 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1924 enum port port = encoder->port; 1925 1926 intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 1927 } 1928 1929 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 1930 { 1931 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1932 enum port port = encoder->port; 1933 1934 return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 1935 } 1936 1937 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 1938 { 1939 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1940 enum port port = encoder->port; 1941 enum intel_dpll_id id; 1942 u32 tmp; 1943 1944 tmp = intel_de_read(i915, PORT_CLK_SEL(port)); 1945 1946 switch (tmp & PORT_CLK_SEL_MASK) { 1947 case PORT_CLK_SEL_WRPLL1: 1948 id = DPLL_ID_WRPLL1; 1949 break; 1950 case PORT_CLK_SEL_WRPLL2: 1951 id = DPLL_ID_WRPLL2; 1952 break; 1953 case PORT_CLK_SEL_SPLL: 1954 id = DPLL_ID_SPLL; 1955 break; 1956 case PORT_CLK_SEL_LCPLL_810: 1957 id = DPLL_ID_LCPLL_810; 1958 break; 1959 case PORT_CLK_SEL_LCPLL_1350: 1960 id = DPLL_ID_LCPLL_1350; 1961 break; 1962 case PORT_CLK_SEL_LCPLL_2700: 1963 id = DPLL_ID_LCPLL_2700; 1964 break; 1965 default: 1966 MISSING_CASE(tmp); 1967 fallthrough; 1968 case PORT_CLK_SEL_NONE: 1969 return NULL; 1970 } 1971 1972 return intel_get_shared_dpll_by_id(i915, id); 1973 } 1974 1975 void intel_ddi_enable_clock(struct intel_encoder *encoder, 1976 const struct intel_crtc_state *crtc_state) 1977 { 1978 if (encoder->enable_clock) 1979 encoder->enable_clock(encoder, crtc_state); 1980 } 1981 1982 void intel_ddi_disable_clock(struct intel_encoder *encoder) 1983 { 1984 if (encoder->disable_clock) 1985 encoder->disable_clock(encoder); 1986 } 1987 1988 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 1989 { 1990 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1991 u32 port_mask; 1992 bool ddi_clk_needed; 1993 1994 /* 1995 * In case of DP MST, we sanitize the primary encoder only, not the 1996 * virtual ones. 1997 */ 1998 if (encoder->type == INTEL_OUTPUT_DP_MST) 1999 return; 2000 2001 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2002 u8 pipe_mask; 2003 bool is_mst; 2004 2005 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2006 /* 2007 * In the unlikely case that BIOS enables DP in MST mode, just 2008 * warn since our MST HW readout is incomplete. 2009 */ 2010 if (drm_WARN_ON(&i915->drm, is_mst)) 2011 return; 2012 } 2013 2014 port_mask = BIT(encoder->port); 2015 ddi_clk_needed = encoder->base.crtc; 2016 2017 if (encoder->type == INTEL_OUTPUT_DSI) { 2018 struct intel_encoder *other_encoder; 2019 2020 port_mask = intel_dsi_encoder_ports(encoder); 2021 /* 2022 * Sanity check that we haven't incorrectly registered another 2023 * encoder using any of the ports of this DSI encoder. 2024 */ 2025 for_each_intel_encoder(&i915->drm, other_encoder) { 2026 if (other_encoder == encoder) 2027 continue; 2028 2029 if (drm_WARN_ON(&i915->drm, 2030 port_mask & BIT(other_encoder->port))) 2031 return; 2032 } 2033 /* 2034 * For DSI we keep the ddi clocks gated 2035 * except during enable/disable sequence. 2036 */ 2037 ddi_clk_needed = false; 2038 } 2039 2040 if (ddi_clk_needed || !encoder->is_clock_enabled || 2041 !encoder->is_clock_enabled(encoder)) 2042 return; 2043 2044 drm_notice(&i915->drm, 2045 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2046 encoder->base.base.id, encoder->base.name); 2047 2048 encoder->disable_clock(encoder); 2049 } 2050 2051 static void 2052 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2053 const struct intel_crtc_state *crtc_state) 2054 { 2055 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2056 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port); 2057 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); 2058 u32 ln0, ln1, pin_assignment; 2059 u8 width; 2060 2061 if (!intel_phy_is_tc(dev_priv, phy) || 2062 intel_tc_port_in_tbt_alt_mode(dig_port)) 2063 return; 2064 2065 if (DISPLAY_VER(dev_priv) >= 12) { 2066 ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)); 2067 ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)); 2068 } else { 2069 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 2070 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 2071 } 2072 2073 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2074 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2075 2076 /* DPPATC */ 2077 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 2078 width = crtc_state->lane_count; 2079 2080 switch (pin_assignment) { 2081 case 0x0: 2082 drm_WARN_ON(&dev_priv->drm, 2083 !intel_tc_port_in_legacy_mode(dig_port)); 2084 if (width == 1) { 2085 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2086 } else { 2087 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2088 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2089 } 2090 break; 2091 case 0x1: 2092 if (width == 4) { 2093 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2094 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2095 } 2096 break; 2097 case 0x2: 2098 if (width == 2) { 2099 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2100 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2101 } 2102 break; 2103 case 0x3: 2104 case 0x5: 2105 if (width == 1) { 2106 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2107 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2108 } else { 2109 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2110 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2111 } 2112 break; 2113 case 0x4: 2114 case 0x6: 2115 if (width == 1) { 2116 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2117 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2118 } else { 2119 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2120 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2121 } 2122 break; 2123 default: 2124 MISSING_CASE(pin_assignment); 2125 } 2126 2127 if (DISPLAY_VER(dev_priv) >= 12) { 2128 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0); 2129 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1); 2130 } else { 2131 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 2132 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 2133 } 2134 } 2135 2136 static enum transcoder 2137 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2138 { 2139 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2140 return crtc_state->mst_master_transcoder; 2141 else 2142 return crtc_state->cpu_transcoder; 2143 } 2144 2145 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2146 const struct intel_crtc_state *crtc_state) 2147 { 2148 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2149 2150 if (DISPLAY_VER(dev_priv) >= 12) 2151 return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state)); 2152 else 2153 return DP_TP_CTL(encoder->port); 2154 } 2155 2156 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2157 const struct intel_crtc_state *crtc_state) 2158 { 2159 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2160 2161 if (DISPLAY_VER(dev_priv) >= 12) 2162 return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state)); 2163 else 2164 return DP_TP_STATUS(encoder->port); 2165 } 2166 2167 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2168 const struct intel_crtc_state *crtc_state, 2169 bool enable) 2170 { 2171 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2172 2173 if (!crtc_state->vrr.enable) 2174 return; 2175 2176 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2177 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2178 drm_dbg_kms(&i915->drm, 2179 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2180 str_enable_disable(enable)); 2181 } 2182 2183 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2184 const struct intel_crtc_state *crtc_state) 2185 { 2186 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2187 2188 if (!crtc_state->fec_enable) 2189 return; 2190 2191 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0) 2192 drm_dbg_kms(&i915->drm, 2193 "Failed to set FEC_READY in the sink\n"); 2194 } 2195 2196 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2197 const struct intel_crtc_state *crtc_state) 2198 { 2199 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2200 struct intel_dp *intel_dp; 2201 2202 if (!crtc_state->fec_enable) 2203 return; 2204 2205 intel_dp = enc_to_intel_dp(encoder); 2206 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2207 0, DP_TP_CTL_FEC_ENABLE); 2208 } 2209 2210 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder, 2211 const struct intel_crtc_state *crtc_state) 2212 { 2213 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2214 struct intel_dp *intel_dp; 2215 2216 if (!crtc_state->fec_enable) 2217 return; 2218 2219 intel_dp = enc_to_intel_dp(encoder); 2220 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2221 DP_TP_CTL_FEC_ENABLE, 0); 2222 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2223 } 2224 2225 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2226 const struct intel_crtc_state *crtc_state) 2227 { 2228 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2229 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2230 enum phy phy = intel_port_to_phy(i915, encoder->port); 2231 2232 if (intel_phy_is_combo(i915, phy)) { 2233 bool lane_reversal = 2234 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 2235 2236 intel_combo_phy_power_up_lanes(i915, phy, false, 2237 crtc_state->lane_count, 2238 lane_reversal); 2239 } 2240 } 2241 2242 /* Splitter enable for eDP MSO is limited to certain pipes. */ 2243 static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915) 2244 { 2245 if (IS_ALDERLAKE_P(i915)) 2246 return BIT(PIPE_A) | BIT(PIPE_B); 2247 else 2248 return BIT(PIPE_A); 2249 } 2250 2251 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2252 struct intel_crtc_state *pipe_config) 2253 { 2254 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2255 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2256 enum pipe pipe = crtc->pipe; 2257 u32 dss1; 2258 2259 if (!HAS_MSO(i915)) 2260 return; 2261 2262 dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); 2263 2264 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2265 if (!pipe_config->splitter.enable) 2266 return; 2267 2268 if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) { 2269 pipe_config->splitter.enable = false; 2270 return; 2271 } 2272 2273 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2274 default: 2275 drm_WARN(&i915->drm, true, 2276 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2277 fallthrough; 2278 case SPLITTER_CONFIGURATION_2_SEGMENT: 2279 pipe_config->splitter.link_count = 2; 2280 break; 2281 case SPLITTER_CONFIGURATION_4_SEGMENT: 2282 pipe_config->splitter.link_count = 4; 2283 break; 2284 } 2285 2286 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2287 } 2288 2289 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2290 { 2291 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2292 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2293 enum pipe pipe = crtc->pipe; 2294 u32 dss1 = 0; 2295 2296 if (!HAS_MSO(i915)) 2297 return; 2298 2299 if (crtc_state->splitter.enable) { 2300 dss1 |= SPLITTER_ENABLE; 2301 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2302 if (crtc_state->splitter.link_count == 2) 2303 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2304 else 2305 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2306 } 2307 2308 intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), 2309 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2310 OVERLAP_PIXELS_MASK, dss1); 2311 } 2312 2313 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2314 struct intel_encoder *encoder, 2315 const struct intel_crtc_state *crtc_state, 2316 const struct drm_connector_state *conn_state) 2317 { 2318 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2319 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2320 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2321 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2322 2323 intel_dp_set_link_params(intel_dp, 2324 crtc_state->port_clock, 2325 crtc_state->lane_count); 2326 2327 /* 2328 * We only configure what the register value will be here. Actual 2329 * enabling happens during link training farther down. 2330 */ 2331 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2332 2333 /* 2334 * 1. Enable Power Wells 2335 * 2336 * This was handled at the beginning of intel_atomic_commit_tail(), 2337 * before we called down into this function. 2338 */ 2339 2340 /* 2. Enable Panel Power if PPS is required */ 2341 intel_pps_on(intel_dp); 2342 2343 /* 2344 * 3. For non-TBT Type-C ports, set FIA lane count 2345 * (DFLEXDPSP.DPX4TXLATC) 2346 * 2347 * This was done before tgl_ddi_pre_enable_dp by 2348 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2349 */ 2350 2351 /* 2352 * 4. Enable the port PLL. 2353 * 2354 * The PLL enabling itself was already done before this function by 2355 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 2356 * configure the PLL to port mapping here. 2357 */ 2358 intel_ddi_enable_clock(encoder, crtc_state); 2359 2360 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2361 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2362 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2363 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2364 dig_port->ddi_io_power_domain); 2365 } 2366 2367 /* 6. Program DP_MODE */ 2368 icl_program_mg_dp_mode(dig_port, crtc_state); 2369 2370 /* 2371 * 7. The rest of the below are substeps under the bspec's "Enable and 2372 * Train Display Port" step. Note that steps that are specific to 2373 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2374 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2375 * us when active_mst_links==0, so any steps designated for "single 2376 * stream or multi-stream master transcoder" can just be performed 2377 * unconditionally here. 2378 */ 2379 2380 /* 2381 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2382 * Transcoder. 2383 */ 2384 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2385 2386 if (HAS_DP20(dev_priv)) 2387 intel_ddi_config_transcoder_dp2(encoder, crtc_state); 2388 2389 /* 2390 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2391 * Transport Select 2392 */ 2393 intel_ddi_config_transcoder_func(encoder, crtc_state); 2394 2395 /* 2396 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2397 * selected 2398 * 2399 * This will be handled by the intel_dp_start_link_train() farther 2400 * down this function. 2401 */ 2402 2403 /* 7.e Configure voltage swing and related IO settings */ 2404 encoder->set_signal_levels(encoder, crtc_state); 2405 2406 /* 2407 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2408 * the used lanes of the DDI. 2409 */ 2410 intel_ddi_power_up_lanes(encoder, crtc_state); 2411 2412 /* 2413 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2414 */ 2415 intel_ddi_mso_configure(crtc_state); 2416 2417 if (!is_mst) 2418 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2419 2420 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2421 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); 2422 /* 2423 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2424 * in the FEC_CONFIGURATION register to 1 before initiating link 2425 * training 2426 */ 2427 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 2428 2429 intel_dp_check_frl_training(intel_dp); 2430 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2431 2432 /* 2433 * 7.i Follow DisplayPort specification training sequence (see notes for 2434 * failure handling) 2435 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2436 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2437 * (timeout after 800 us) 2438 */ 2439 intel_dp_start_link_train(intel_dp, crtc_state); 2440 2441 /* 7.k Set DP_TP_CTL link training to Normal */ 2442 if (!is_trans_port_sync_mode(crtc_state)) 2443 intel_dp_stop_link_train(intel_dp, crtc_state); 2444 2445 /* 7.l Configure and enable FEC if needed */ 2446 intel_ddi_enable_fec(encoder, crtc_state); 2447 2448 intel_dsc_dp_pps_write(encoder, crtc_state); 2449 } 2450 2451 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2452 struct intel_encoder *encoder, 2453 const struct intel_crtc_state *crtc_state, 2454 const struct drm_connector_state *conn_state) 2455 { 2456 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2457 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2458 enum port port = encoder->port; 2459 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2460 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2461 2462 if (DISPLAY_VER(dev_priv) < 11) 2463 drm_WARN_ON(&dev_priv->drm, 2464 is_mst && (port == PORT_A || port == PORT_E)); 2465 else 2466 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 2467 2468 intel_dp_set_link_params(intel_dp, 2469 crtc_state->port_clock, 2470 crtc_state->lane_count); 2471 2472 /* 2473 * We only configure what the register value will be here. Actual 2474 * enabling happens during link training farther down. 2475 */ 2476 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2477 2478 intel_pps_on(intel_dp); 2479 2480 intel_ddi_enable_clock(encoder, crtc_state); 2481 2482 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2483 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2484 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2485 dig_port->ddi_io_power_domain); 2486 } 2487 2488 icl_program_mg_dp_mode(dig_port, crtc_state); 2489 2490 if (has_buf_trans_select(dev_priv)) 2491 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2492 2493 encoder->set_signal_levels(encoder, crtc_state); 2494 2495 intel_ddi_power_up_lanes(encoder, crtc_state); 2496 2497 if (!is_mst) 2498 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2499 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2500 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, 2501 true); 2502 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 2503 intel_dp_start_link_train(intel_dp, crtc_state); 2504 if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && 2505 !is_trans_port_sync_mode(crtc_state)) 2506 intel_dp_stop_link_train(intel_dp, crtc_state); 2507 2508 intel_ddi_enable_fec(encoder, crtc_state); 2509 2510 if (!is_mst) 2511 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2512 2513 intel_dsc_dp_pps_write(encoder, crtc_state); 2514 } 2515 2516 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2517 struct intel_encoder *encoder, 2518 const struct intel_crtc_state *crtc_state, 2519 const struct drm_connector_state *conn_state) 2520 { 2521 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2522 2523 if (DISPLAY_VER(dev_priv) >= 12) 2524 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2525 else 2526 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2527 2528 /* MST will call a setting of MSA after an allocating of Virtual Channel 2529 * from MST encoder pre_enable callback. 2530 */ 2531 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2532 intel_ddi_set_dp_msa(crtc_state, conn_state); 2533 } 2534 2535 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2536 struct intel_encoder *encoder, 2537 const struct intel_crtc_state *crtc_state, 2538 const struct drm_connector_state *conn_state) 2539 { 2540 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2541 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2542 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2543 2544 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2545 intel_ddi_enable_clock(encoder, crtc_state); 2546 2547 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2548 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2549 dig_port->ddi_io_power_domain); 2550 2551 icl_program_mg_dp_mode(dig_port, crtc_state); 2552 2553 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2554 2555 dig_port->set_infoframes(encoder, 2556 crtc_state->has_infoframe, 2557 crtc_state, conn_state); 2558 } 2559 2560 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 2561 struct intel_encoder *encoder, 2562 const struct intel_crtc_state *crtc_state, 2563 const struct drm_connector_state *conn_state) 2564 { 2565 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2566 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2567 enum pipe pipe = crtc->pipe; 2568 2569 /* 2570 * When called from DP MST code: 2571 * - conn_state will be NULL 2572 * - encoder will be the main encoder (ie. mst->primary) 2573 * - the main connector associated with this port 2574 * won't be active or linked to a crtc 2575 * - crtc_state will be the state of the first stream to 2576 * be activated on this port, and it may not be the same 2577 * stream that will be deactivated last, but each stream 2578 * should have a state that is identical when it comes to 2579 * the DP link parameteres 2580 */ 2581 2582 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 2583 2584 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2585 2586 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 2587 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 2588 conn_state); 2589 } else { 2590 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2591 2592 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 2593 conn_state); 2594 2595 /* FIXME precompute everything properly */ 2596 /* FIXME how do we turn infoframes off again? */ 2597 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) 2598 dig_port->set_infoframes(encoder, 2599 crtc_state->has_infoframe, 2600 crtc_state, conn_state); 2601 } 2602 } 2603 2604 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 2605 const struct intel_crtc_state *crtc_state) 2606 { 2607 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2608 enum port port = encoder->port; 2609 bool wait = false; 2610 u32 val; 2611 2612 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2613 if (val & DDI_BUF_CTL_ENABLE) { 2614 val &= ~DDI_BUF_CTL_ENABLE; 2615 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 2616 wait = true; 2617 } 2618 2619 if (intel_crtc_has_dp_encoder(crtc_state)) 2620 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2621 DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK, 2622 DP_TP_CTL_LINK_TRAIN_PAT1); 2623 2624 /* Disable FEC in DP Sink */ 2625 intel_ddi_disable_fec_state(encoder, crtc_state); 2626 2627 if (wait) 2628 intel_wait_ddi_buf_idle(dev_priv, port); 2629 } 2630 2631 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 2632 struct intel_encoder *encoder, 2633 const struct intel_crtc_state *old_crtc_state, 2634 const struct drm_connector_state *old_conn_state) 2635 { 2636 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2637 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2638 struct intel_dp *intel_dp = &dig_port->dp; 2639 bool is_mst = intel_crtc_has_type(old_crtc_state, 2640 INTEL_OUTPUT_DP_MST); 2641 2642 if (!is_mst) 2643 intel_dp_set_infoframes(encoder, false, 2644 old_crtc_state, old_conn_state); 2645 2646 /* 2647 * Power down sink before disabling the port, otherwise we end 2648 * up getting interrupts from the sink on detecting link loss. 2649 */ 2650 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 2651 2652 if (DISPLAY_VER(dev_priv) >= 12) { 2653 if (is_mst) { 2654 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 2655 2656 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 2657 TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK, 2658 0); 2659 } 2660 } else { 2661 if (!is_mst) 2662 intel_ddi_disable_transcoder_clock(old_crtc_state); 2663 } 2664 2665 intel_disable_ddi_buf(encoder, old_crtc_state); 2666 2667 /* 2668 * From TGL spec: "If single stream or multi-stream master transcoder: 2669 * Configure Transcoder Clock select to direct no clock to the 2670 * transcoder" 2671 */ 2672 if (DISPLAY_VER(dev_priv) >= 12) 2673 intel_ddi_disable_transcoder_clock(old_crtc_state); 2674 2675 intel_pps_vdd_on(intel_dp); 2676 intel_pps_off(intel_dp); 2677 2678 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 2679 intel_display_power_put(dev_priv, 2680 dig_port->ddi_io_power_domain, 2681 fetch_and_zero(&dig_port->ddi_io_wakeref)); 2682 2683 intel_ddi_disable_clock(encoder); 2684 } 2685 2686 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 2687 struct intel_encoder *encoder, 2688 const struct intel_crtc_state *old_crtc_state, 2689 const struct drm_connector_state *old_conn_state) 2690 { 2691 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2692 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2693 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2694 2695 dig_port->set_infoframes(encoder, false, 2696 old_crtc_state, old_conn_state); 2697 2698 if (DISPLAY_VER(dev_priv) < 12) 2699 intel_ddi_disable_transcoder_clock(old_crtc_state); 2700 2701 intel_disable_ddi_buf(encoder, old_crtc_state); 2702 2703 if (DISPLAY_VER(dev_priv) >= 12) 2704 intel_ddi_disable_transcoder_clock(old_crtc_state); 2705 2706 intel_display_power_put(dev_priv, 2707 dig_port->ddi_io_power_domain, 2708 fetch_and_zero(&dig_port->ddi_io_wakeref)); 2709 2710 intel_ddi_disable_clock(encoder); 2711 2712 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 2713 } 2714 2715 static void intel_ddi_post_disable(struct intel_atomic_state *state, 2716 struct intel_encoder *encoder, 2717 const struct intel_crtc_state *old_crtc_state, 2718 const struct drm_connector_state *old_conn_state) 2719 { 2720 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2721 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2722 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2723 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 2724 struct intel_crtc *slave_crtc; 2725 2726 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) { 2727 intel_crtc_vblank_off(old_crtc_state); 2728 2729 intel_vrr_disable(old_crtc_state); 2730 2731 intel_disable_transcoder(old_crtc_state); 2732 2733 intel_ddi_disable_transcoder_func(old_crtc_state); 2734 2735 intel_dsc_disable(old_crtc_state); 2736 2737 if (DISPLAY_VER(dev_priv) >= 9) 2738 skl_scaler_disable(old_crtc_state); 2739 else 2740 ilk_pfit_disable(old_crtc_state); 2741 } 2742 2743 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc, 2744 intel_crtc_bigjoiner_slave_pipes(old_crtc_state)) { 2745 const struct intel_crtc_state *old_slave_crtc_state = 2746 intel_atomic_get_old_crtc_state(state, slave_crtc); 2747 2748 intel_crtc_vblank_off(old_slave_crtc_state); 2749 2750 intel_dsc_disable(old_slave_crtc_state); 2751 skl_scaler_disable(old_slave_crtc_state); 2752 } 2753 2754 /* 2755 * When called from DP MST code: 2756 * - old_conn_state will be NULL 2757 * - encoder will be the main encoder (ie. mst->primary) 2758 * - the main connector associated with this port 2759 * won't be active or linked to a crtc 2760 * - old_crtc_state will be the state of the last stream to 2761 * be deactivated on this port, and it may not be the same 2762 * stream that was activated last, but each stream 2763 * should have a state that is identical when it comes to 2764 * the DP link parameteres 2765 */ 2766 2767 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 2768 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 2769 old_conn_state); 2770 else 2771 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 2772 old_conn_state); 2773 2774 main_link_aux_power_domain_put(dig_port, old_crtc_state); 2775 2776 if (is_tc_port) 2777 intel_tc_port_put_link(dig_port); 2778 } 2779 2780 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 2781 struct intel_encoder *encoder, 2782 const struct intel_crtc_state *crtc_state) 2783 { 2784 const struct drm_connector_state *conn_state; 2785 struct drm_connector *conn; 2786 int i; 2787 2788 if (!crtc_state->sync_mode_slaves_mask) 2789 return; 2790 2791 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 2792 struct intel_encoder *slave_encoder = 2793 to_intel_encoder(conn_state->best_encoder); 2794 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 2795 const struct intel_crtc_state *slave_crtc_state; 2796 2797 if (!slave_crtc) 2798 continue; 2799 2800 slave_crtc_state = 2801 intel_atomic_get_new_crtc_state(state, slave_crtc); 2802 2803 if (slave_crtc_state->master_transcoder != 2804 crtc_state->cpu_transcoder) 2805 continue; 2806 2807 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 2808 slave_crtc_state); 2809 } 2810 2811 usleep_range(200, 400); 2812 2813 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 2814 crtc_state); 2815 } 2816 2817 static void intel_enable_ddi_dp(struct intel_atomic_state *state, 2818 struct intel_encoder *encoder, 2819 const struct intel_crtc_state *crtc_state, 2820 const struct drm_connector_state *conn_state) 2821 { 2822 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2823 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2824 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2825 enum port port = encoder->port; 2826 2827 if (port == PORT_A && DISPLAY_VER(dev_priv) < 9) 2828 intel_dp_stop_link_train(intel_dp, crtc_state); 2829 2830 drm_connector_update_privacy_screen(conn_state); 2831 intel_edp_backlight_on(crtc_state, conn_state); 2832 2833 if (!dig_port->lspcon.active || dig_port->dp.has_hdmi_sink) 2834 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 2835 2836 intel_audio_codec_enable(encoder, crtc_state, conn_state); 2837 2838 trans_port_sync_stop_link_train(state, encoder, crtc_state); 2839 } 2840 2841 static i915_reg_t 2842 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 2843 enum port port) 2844 { 2845 static const enum transcoder trans[] = { 2846 [PORT_A] = TRANSCODER_EDP, 2847 [PORT_B] = TRANSCODER_A, 2848 [PORT_C] = TRANSCODER_B, 2849 [PORT_D] = TRANSCODER_C, 2850 [PORT_E] = TRANSCODER_A, 2851 }; 2852 2853 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9); 2854 2855 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) 2856 port = PORT_A; 2857 2858 return CHICKEN_TRANS(trans[port]); 2859 } 2860 2861 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, 2862 struct intel_encoder *encoder, 2863 const struct intel_crtc_state *crtc_state, 2864 const struct drm_connector_state *conn_state) 2865 { 2866 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2867 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2868 struct drm_connector *connector = conn_state->connector; 2869 enum port port = encoder->port; 2870 enum phy phy = intel_port_to_phy(dev_priv, port); 2871 u32 buf_ctl; 2872 2873 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 2874 crtc_state->hdmi_high_tmds_clock_ratio, 2875 crtc_state->hdmi_scrambling)) 2876 drm_dbg_kms(&dev_priv->drm, 2877 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 2878 connector->base.id, connector->name); 2879 2880 if (has_buf_trans_select(dev_priv)) 2881 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 2882 2883 encoder->set_signal_levels(encoder, crtc_state); 2884 2885 /* Display WA #1143: skl,kbl,cfl */ 2886 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { 2887 /* 2888 * For some reason these chicken bits have been 2889 * stuffed into a transcoder register, event though 2890 * the bits affect a specific DDI port rather than 2891 * a specific transcoder. 2892 */ 2893 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 2894 u32 val; 2895 2896 val = intel_de_read(dev_priv, reg); 2897 2898 if (port == PORT_E) 2899 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 2900 DDIE_TRAINING_OVERRIDE_VALUE; 2901 else 2902 val |= DDI_TRAINING_OVERRIDE_ENABLE | 2903 DDI_TRAINING_OVERRIDE_VALUE; 2904 2905 intel_de_write(dev_priv, reg, val); 2906 intel_de_posting_read(dev_priv, reg); 2907 2908 udelay(1); 2909 2910 if (port == PORT_E) 2911 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 2912 DDIE_TRAINING_OVERRIDE_VALUE); 2913 else 2914 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 2915 DDI_TRAINING_OVERRIDE_VALUE); 2916 2917 intel_de_write(dev_priv, reg, val); 2918 } 2919 2920 intel_ddi_power_up_lanes(encoder, crtc_state); 2921 2922 /* In HDMI/DVI mode, the port width, and swing/emphasis values 2923 * are ignored so nothing special needs to be done besides 2924 * enabling the port. 2925 * 2926 * On ADL_P the PHY link rate and lane count must be programmed but 2927 * these are both 0 for HDMI. 2928 */ 2929 buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE; 2930 if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) { 2931 drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port)); 2932 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 2933 } 2934 intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl); 2935 2936 intel_wait_ddi_buf_active(dev_priv, port); 2937 2938 intel_audio_codec_enable(encoder, crtc_state, conn_state); 2939 } 2940 2941 static void intel_enable_ddi(struct intel_atomic_state *state, 2942 struct intel_encoder *encoder, 2943 const struct intel_crtc_state *crtc_state, 2944 const struct drm_connector_state *conn_state) 2945 { 2946 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 2947 2948 if (!intel_crtc_is_bigjoiner_slave(crtc_state)) 2949 intel_ddi_enable_transcoder_func(encoder, crtc_state); 2950 2951 /* Enable/Disable DP2.0 SDP split config before transcoder */ 2952 intel_audio_sdp_split_update(encoder, crtc_state); 2953 2954 intel_enable_transcoder(crtc_state); 2955 2956 intel_vrr_enable(encoder, crtc_state); 2957 2958 intel_crtc_vblank_on(crtc_state); 2959 2960 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 2961 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state); 2962 else 2963 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state); 2964 2965 /* Enable hdcp if it's desired */ 2966 if (conn_state->content_protection == 2967 DRM_MODE_CONTENT_PROTECTION_DESIRED) 2968 intel_hdcp_enable(to_intel_connector(conn_state->connector), 2969 crtc_state, 2970 (u8)conn_state->hdcp_content_type); 2971 } 2972 2973 static void intel_disable_ddi_dp(struct intel_atomic_state *state, 2974 struct intel_encoder *encoder, 2975 const struct intel_crtc_state *old_crtc_state, 2976 const struct drm_connector_state *old_conn_state) 2977 { 2978 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2979 2980 intel_dp->link_trained = false; 2981 2982 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 2983 2984 intel_psr_disable(intel_dp, old_crtc_state); 2985 intel_edp_backlight_off(old_conn_state); 2986 /* Disable the decompression in DP Sink */ 2987 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, 2988 false); 2989 /* Disable Ignore_MSA bit in DP Sink */ 2990 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 2991 false); 2992 } 2993 2994 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state, 2995 struct intel_encoder *encoder, 2996 const struct intel_crtc_state *old_crtc_state, 2997 const struct drm_connector_state *old_conn_state) 2998 { 2999 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3000 struct drm_connector *connector = old_conn_state->connector; 3001 3002 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 3003 3004 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3005 false, false)) 3006 drm_dbg_kms(&i915->drm, 3007 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3008 connector->base.id, connector->name); 3009 } 3010 3011 static void intel_disable_ddi(struct intel_atomic_state *state, 3012 struct intel_encoder *encoder, 3013 const struct intel_crtc_state *old_crtc_state, 3014 const struct drm_connector_state *old_conn_state) 3015 { 3016 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3017 3018 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3019 intel_disable_ddi_hdmi(state, encoder, old_crtc_state, 3020 old_conn_state); 3021 else 3022 intel_disable_ddi_dp(state, encoder, old_crtc_state, 3023 old_conn_state); 3024 } 3025 3026 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3027 struct intel_encoder *encoder, 3028 const struct intel_crtc_state *crtc_state, 3029 const struct drm_connector_state *conn_state) 3030 { 3031 intel_ddi_set_dp_msa(crtc_state, conn_state); 3032 3033 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3034 3035 intel_backlight_update(state, encoder, crtc_state, conn_state); 3036 drm_connector_update_privacy_screen(conn_state); 3037 } 3038 3039 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3040 struct intel_encoder *encoder, 3041 const struct intel_crtc_state *crtc_state, 3042 const struct drm_connector_state *conn_state) 3043 { 3044 3045 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3046 !intel_encoder_is_mst(encoder)) 3047 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3048 conn_state); 3049 3050 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3051 } 3052 3053 static void 3054 intel_ddi_update_prepare(struct intel_atomic_state *state, 3055 struct intel_encoder *encoder, 3056 struct intel_crtc *crtc) 3057 { 3058 struct drm_i915_private *i915 = to_i915(state->base.dev); 3059 struct intel_crtc_state *crtc_state = 3060 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL; 3061 int required_lanes = crtc_state ? crtc_state->lane_count : 1; 3062 3063 drm_WARN_ON(state->base.dev, crtc && crtc->active); 3064 3065 intel_tc_port_get_link(enc_to_dig_port(encoder), 3066 required_lanes); 3067 if (crtc_state && crtc_state->hw.active) { 3068 struct intel_crtc *slave_crtc; 3069 3070 intel_update_active_dpll(state, crtc, encoder); 3071 3072 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 3073 intel_crtc_bigjoiner_slave_pipes(crtc_state)) 3074 intel_update_active_dpll(state, slave_crtc, encoder); 3075 } 3076 } 3077 3078 static void 3079 intel_ddi_update_complete(struct intel_atomic_state *state, 3080 struct intel_encoder *encoder, 3081 struct intel_crtc *crtc) 3082 { 3083 intel_tc_port_put_link(enc_to_dig_port(encoder)); 3084 } 3085 3086 static void 3087 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3088 struct intel_encoder *encoder, 3089 const struct intel_crtc_state *crtc_state, 3090 const struct drm_connector_state *conn_state) 3091 { 3092 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3093 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3094 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3095 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 3096 3097 if (is_tc_port) 3098 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3099 3100 main_link_aux_power_domain_get(dig_port, crtc_state); 3101 3102 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3103 /* 3104 * Program the lane count for static/dynamic connections on 3105 * Type-C ports. Skip this step for TBT. 3106 */ 3107 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3108 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3109 bxt_ddi_phy_set_lane_optim_mask(encoder, 3110 crtc_state->lane_lat_optim_mask); 3111 } 3112 3113 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) 3114 { 3115 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3116 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 3117 int ln; 3118 3119 for (ln = 0; ln < 2; ln++) 3120 intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0); 3121 } 3122 3123 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3124 const struct intel_crtc_state *crtc_state) 3125 { 3126 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3127 struct intel_encoder *encoder = &dig_port->base; 3128 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3129 enum port port = encoder->port; 3130 u32 dp_tp_ctl, ddi_buf_ctl; 3131 bool wait = false; 3132 3133 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3134 3135 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 3136 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3137 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 3138 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3139 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 3140 wait = true; 3141 } 3142 3143 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 3144 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1; 3145 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3146 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3147 3148 if (wait) 3149 intel_wait_ddi_buf_idle(dev_priv, port); 3150 } 3151 3152 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3153 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3154 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3155 } else { 3156 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3157 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 3158 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3159 } 3160 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3161 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3162 3163 if (IS_ALDERLAKE_P(dev_priv) && 3164 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) 3165 adlp_tbt_to_dp_alt_switch_wa(encoder); 3166 3167 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3168 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3169 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3170 3171 intel_wait_ddi_buf_active(dev_priv, port); 3172 } 3173 3174 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3175 const struct intel_crtc_state *crtc_state, 3176 u8 dp_train_pat) 3177 { 3178 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3179 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3180 u32 temp; 3181 3182 temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3183 3184 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3185 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3186 case DP_TRAINING_PATTERN_DISABLE: 3187 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3188 break; 3189 case DP_TRAINING_PATTERN_1: 3190 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3191 break; 3192 case DP_TRAINING_PATTERN_2: 3193 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3194 break; 3195 case DP_TRAINING_PATTERN_3: 3196 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3197 break; 3198 case DP_TRAINING_PATTERN_4: 3199 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3200 break; 3201 } 3202 3203 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp); 3204 } 3205 3206 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3207 const struct intel_crtc_state *crtc_state) 3208 { 3209 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3210 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3211 enum port port = encoder->port; 3212 3213 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 3214 DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE); 3215 3216 /* 3217 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3218 * reason we need to set idle transmission mode is to work around a HW 3219 * issue where we enable the pipe while not in idle link-training mode. 3220 * In this case there is requirement to wait for a minimum number of 3221 * idle patterns to be sent. 3222 */ 3223 if (port == PORT_A && DISPLAY_VER(dev_priv) < 12) 3224 return; 3225 3226 if (intel_de_wait_for_set(dev_priv, 3227 dp_tp_status_reg(encoder, crtc_state), 3228 DP_TP_STATUS_IDLE_DONE, 1)) 3229 drm_err(&dev_priv->drm, 3230 "Timed out waiting for DP idle patterns\n"); 3231 } 3232 3233 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 3234 enum transcoder cpu_transcoder) 3235 { 3236 if (cpu_transcoder == TRANSCODER_EDP) 3237 return false; 3238 3239 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO)) 3240 return false; 3241 3242 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 3243 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3244 } 3245 3246 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, 3247 struct intel_crtc_state *crtc_state) 3248 { 3249 if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000) 3250 crtc_state->min_voltage_level = 2; 3251 else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000) 3252 crtc_state->min_voltage_level = 3; 3253 else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000) 3254 crtc_state->min_voltage_level = 1; 3255 } 3256 3257 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, 3258 enum transcoder cpu_transcoder) 3259 { 3260 u32 master_select; 3261 3262 if (DISPLAY_VER(dev_priv) >= 11) { 3263 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder)); 3264 3265 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3266 return INVALID_TRANSCODER; 3267 3268 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3269 } else { 3270 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3271 3272 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3273 return INVALID_TRANSCODER; 3274 3275 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3276 } 3277 3278 if (master_select == 0) 3279 return TRANSCODER_EDP; 3280 else 3281 return master_select - 1; 3282 } 3283 3284 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3285 { 3286 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3287 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3288 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3289 enum transcoder cpu_transcoder; 3290 3291 crtc_state->master_transcoder = 3292 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); 3293 3294 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { 3295 enum intel_display_power_domain power_domain; 3296 intel_wakeref_t trans_wakeref; 3297 3298 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3299 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 3300 power_domain); 3301 3302 if (!trans_wakeref) 3303 continue; 3304 3305 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == 3306 crtc_state->cpu_transcoder) 3307 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3308 3309 intel_display_power_put(dev_priv, power_domain, trans_wakeref); 3310 } 3311 3312 drm_WARN_ON(&dev_priv->drm, 3313 crtc_state->master_transcoder != INVALID_TRANSCODER && 3314 crtc_state->sync_mode_slaves_mask); 3315 } 3316 3317 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 3318 struct intel_crtc_state *pipe_config) 3319 { 3320 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3321 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3322 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3323 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3324 u32 temp, flags = 0; 3325 3326 temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3327 if (temp & TRANS_DDI_PHSYNC) 3328 flags |= DRM_MODE_FLAG_PHSYNC; 3329 else 3330 flags |= DRM_MODE_FLAG_NHSYNC; 3331 if (temp & TRANS_DDI_PVSYNC) 3332 flags |= DRM_MODE_FLAG_PVSYNC; 3333 else 3334 flags |= DRM_MODE_FLAG_NVSYNC; 3335 3336 pipe_config->hw.adjusted_mode.flags |= flags; 3337 3338 switch (temp & TRANS_DDI_BPC_MASK) { 3339 case TRANS_DDI_BPC_6: 3340 pipe_config->pipe_bpp = 18; 3341 break; 3342 case TRANS_DDI_BPC_8: 3343 pipe_config->pipe_bpp = 24; 3344 break; 3345 case TRANS_DDI_BPC_10: 3346 pipe_config->pipe_bpp = 30; 3347 break; 3348 case TRANS_DDI_BPC_12: 3349 pipe_config->pipe_bpp = 36; 3350 break; 3351 default: 3352 break; 3353 } 3354 3355 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 3356 case TRANS_DDI_MODE_SELECT_HDMI: 3357 pipe_config->has_hdmi_sink = true; 3358 3359 pipe_config->infoframes.enable |= 3360 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3361 3362 if (pipe_config->infoframes.enable) 3363 pipe_config->has_infoframe = true; 3364 3365 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 3366 pipe_config->hdmi_scrambling = true; 3367 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 3368 pipe_config->hdmi_high_tmds_clock_ratio = true; 3369 fallthrough; 3370 case TRANS_DDI_MODE_SELECT_DVI: 3371 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 3372 pipe_config->lane_count = 4; 3373 break; 3374 case TRANS_DDI_MODE_SELECT_DP_SST: 3375 if (encoder->type == INTEL_OUTPUT_EDP) 3376 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 3377 else 3378 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 3379 pipe_config->lane_count = 3380 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3381 3382 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 3383 &pipe_config->dp_m_n); 3384 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, 3385 &pipe_config->dp_m2_n2); 3386 3387 if (DISPLAY_VER(dev_priv) >= 11) { 3388 i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config); 3389 3390 pipe_config->fec_enable = 3391 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE; 3392 3393 drm_dbg_kms(&dev_priv->drm, 3394 "[ENCODER:%d:%s] Fec status: %u\n", 3395 encoder->base.base.id, encoder->base.name, 3396 pipe_config->fec_enable); 3397 } 3398 3399 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) 3400 pipe_config->infoframes.enable |= 3401 intel_lspcon_infoframes_enabled(encoder, pipe_config); 3402 else 3403 pipe_config->infoframes.enable |= 3404 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3405 break; 3406 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 3407 if (!HAS_DP20(dev_priv)) { 3408 /* FDI */ 3409 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 3410 break; 3411 } 3412 fallthrough; /* 128b/132b */ 3413 case TRANS_DDI_MODE_SELECT_DP_MST: 3414 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 3415 pipe_config->lane_count = 3416 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3417 3418 if (DISPLAY_VER(dev_priv) >= 12) 3419 pipe_config->mst_master_transcoder = 3420 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); 3421 3422 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 3423 &pipe_config->dp_m_n); 3424 3425 pipe_config->infoframes.enable |= 3426 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3427 break; 3428 default: 3429 break; 3430 } 3431 } 3432 3433 static void intel_ddi_get_config(struct intel_encoder *encoder, 3434 struct intel_crtc_state *pipe_config) 3435 { 3436 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3437 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3438 3439 /* XXX: DSI transcoder paranoia */ 3440 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 3441 return; 3442 3443 intel_ddi_read_func_ctl(encoder, pipe_config); 3444 3445 intel_ddi_mso_get_config(encoder, pipe_config); 3446 3447 pipe_config->has_audio = 3448 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 3449 3450 if (encoder->type == INTEL_OUTPUT_EDP) 3451 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); 3452 3453 ddi_dotclock_get(pipe_config); 3454 3455 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3456 pipe_config->lane_lat_optim_mask = 3457 bxt_ddi_phy_get_lane_lat_optim_mask(encoder); 3458 3459 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 3460 3461 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 3462 3463 intel_read_infoframe(encoder, pipe_config, 3464 HDMI_INFOFRAME_TYPE_AVI, 3465 &pipe_config->infoframes.avi); 3466 intel_read_infoframe(encoder, pipe_config, 3467 HDMI_INFOFRAME_TYPE_SPD, 3468 &pipe_config->infoframes.spd); 3469 intel_read_infoframe(encoder, pipe_config, 3470 HDMI_INFOFRAME_TYPE_VENDOR, 3471 &pipe_config->infoframes.hdmi); 3472 intel_read_infoframe(encoder, pipe_config, 3473 HDMI_INFOFRAME_TYPE_DRM, 3474 &pipe_config->infoframes.drm); 3475 3476 if (DISPLAY_VER(dev_priv) >= 8) 3477 bdw_get_trans_port_sync_config(pipe_config); 3478 3479 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 3480 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 3481 3482 intel_psr_get_config(encoder, pipe_config); 3483 3484 intel_audio_codec_get_config(encoder, pipe_config); 3485 } 3486 3487 void intel_ddi_get_clock(struct intel_encoder *encoder, 3488 struct intel_crtc_state *crtc_state, 3489 struct intel_shared_dpll *pll) 3490 { 3491 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3492 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 3493 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 3494 bool pll_active; 3495 3496 if (drm_WARN_ON(&i915->drm, !pll)) 3497 return; 3498 3499 port_dpll->pll = pll; 3500 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 3501 drm_WARN_ON(&i915->drm, !pll_active); 3502 3503 icl_set_active_port_dpll(crtc_state, port_dpll_id); 3504 3505 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 3506 &crtc_state->dpll_hw_state); 3507 } 3508 3509 static void dg2_ddi_get_config(struct intel_encoder *encoder, 3510 struct intel_crtc_state *crtc_state) 3511 { 3512 intel_mpllb_readout_hw_state(encoder, &crtc_state->mpllb_state); 3513 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->mpllb_state); 3514 3515 intel_ddi_get_config(encoder, crtc_state); 3516 } 3517 3518 static void adls_ddi_get_config(struct intel_encoder *encoder, 3519 struct intel_crtc_state *crtc_state) 3520 { 3521 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 3522 intel_ddi_get_config(encoder, crtc_state); 3523 } 3524 3525 static void rkl_ddi_get_config(struct intel_encoder *encoder, 3526 struct intel_crtc_state *crtc_state) 3527 { 3528 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 3529 intel_ddi_get_config(encoder, crtc_state); 3530 } 3531 3532 static void dg1_ddi_get_config(struct intel_encoder *encoder, 3533 struct intel_crtc_state *crtc_state) 3534 { 3535 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 3536 intel_ddi_get_config(encoder, crtc_state); 3537 } 3538 3539 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 3540 struct intel_crtc_state *crtc_state) 3541 { 3542 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 3543 intel_ddi_get_config(encoder, crtc_state); 3544 } 3545 3546 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 3547 struct intel_crtc_state *crtc_state, 3548 struct intel_shared_dpll *pll) 3549 { 3550 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3551 enum icl_port_dpll_id port_dpll_id; 3552 struct icl_port_dpll *port_dpll; 3553 bool pll_active; 3554 3555 if (drm_WARN_ON(&i915->drm, !pll)) 3556 return; 3557 3558 if (pll->info->id == DPLL_ID_ICL_TBTPLL) 3559 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 3560 else 3561 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 3562 3563 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 3564 3565 port_dpll->pll = pll; 3566 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 3567 drm_WARN_ON(&i915->drm, !pll_active); 3568 3569 icl_set_active_port_dpll(crtc_state, port_dpll_id); 3570 3571 if (crtc_state->shared_dpll->info->id == DPLL_ID_ICL_TBTPLL) 3572 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port); 3573 else 3574 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 3575 &crtc_state->dpll_hw_state); 3576 } 3577 3578 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 3579 struct intel_crtc_state *crtc_state) 3580 { 3581 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 3582 intel_ddi_get_config(encoder, crtc_state); 3583 } 3584 3585 static void bxt_ddi_get_config(struct intel_encoder *encoder, 3586 struct intel_crtc_state *crtc_state) 3587 { 3588 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 3589 intel_ddi_get_config(encoder, crtc_state); 3590 } 3591 3592 static void skl_ddi_get_config(struct intel_encoder *encoder, 3593 struct intel_crtc_state *crtc_state) 3594 { 3595 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 3596 intel_ddi_get_config(encoder, crtc_state); 3597 } 3598 3599 void hsw_ddi_get_config(struct intel_encoder *encoder, 3600 struct intel_crtc_state *crtc_state) 3601 { 3602 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 3603 intel_ddi_get_config(encoder, crtc_state); 3604 } 3605 3606 static void intel_ddi_sync_state(struct intel_encoder *encoder, 3607 const struct intel_crtc_state *crtc_state) 3608 { 3609 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3610 enum phy phy = intel_port_to_phy(i915, encoder->port); 3611 3612 if (intel_phy_is_tc(i915, phy)) 3613 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder)); 3614 3615 if (crtc_state && intel_crtc_has_dp_encoder(crtc_state)) 3616 intel_dp_sync_state(encoder, crtc_state); 3617 } 3618 3619 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 3620 struct intel_crtc_state *crtc_state) 3621 { 3622 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3623 enum phy phy = intel_port_to_phy(i915, encoder->port); 3624 bool fastset = true; 3625 3626 if (intel_phy_is_tc(i915, phy)) { 3627 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", 3628 encoder->base.base.id, encoder->base.name); 3629 crtc_state->uapi.mode_changed = true; 3630 fastset = false; 3631 } 3632 3633 if (intel_crtc_has_dp_encoder(crtc_state) && 3634 !intel_dp_initial_fastset_check(encoder, crtc_state)) 3635 fastset = false; 3636 3637 return fastset; 3638 } 3639 3640 static enum intel_output_type 3641 intel_ddi_compute_output_type(struct intel_encoder *encoder, 3642 struct intel_crtc_state *crtc_state, 3643 struct drm_connector_state *conn_state) 3644 { 3645 switch (conn_state->connector->connector_type) { 3646 case DRM_MODE_CONNECTOR_HDMIA: 3647 return INTEL_OUTPUT_HDMI; 3648 case DRM_MODE_CONNECTOR_eDP: 3649 return INTEL_OUTPUT_EDP; 3650 case DRM_MODE_CONNECTOR_DisplayPort: 3651 return INTEL_OUTPUT_DP; 3652 default: 3653 MISSING_CASE(conn_state->connector->connector_type); 3654 return INTEL_OUTPUT_UNUSED; 3655 } 3656 } 3657 3658 static int intel_ddi_compute_config(struct intel_encoder *encoder, 3659 struct intel_crtc_state *pipe_config, 3660 struct drm_connector_state *conn_state) 3661 { 3662 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3663 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3664 enum port port = encoder->port; 3665 int ret; 3666 3667 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 3668 pipe_config->cpu_transcoder = TRANSCODER_EDP; 3669 3670 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 3671 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 3672 } else { 3673 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 3674 } 3675 3676 if (ret) 3677 return ret; 3678 3679 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 3680 pipe_config->cpu_transcoder == TRANSCODER_EDP) 3681 pipe_config->pch_pfit.force_thru = 3682 pipe_config->pch_pfit.enabled || 3683 pipe_config->crc_enabled; 3684 3685 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3686 pipe_config->lane_lat_optim_mask = 3687 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 3688 3689 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 3690 3691 return 0; 3692 } 3693 3694 static bool mode_equal(const struct drm_display_mode *mode1, 3695 const struct drm_display_mode *mode2) 3696 { 3697 return drm_mode_match(mode1, mode2, 3698 DRM_MODE_MATCH_TIMINGS | 3699 DRM_MODE_MATCH_FLAGS | 3700 DRM_MODE_MATCH_3D_FLAGS) && 3701 mode1->clock == mode2->clock; /* we want an exact match */ 3702 } 3703 3704 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 3705 const struct intel_link_m_n *m_n_2) 3706 { 3707 return m_n_1->tu == m_n_2->tu && 3708 m_n_1->data_m == m_n_2->data_m && 3709 m_n_1->data_n == m_n_2->data_n && 3710 m_n_1->link_m == m_n_2->link_m && 3711 m_n_1->link_n == m_n_2->link_n; 3712 } 3713 3714 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 3715 const struct intel_crtc_state *crtc_state2) 3716 { 3717 return crtc_state1->hw.active && crtc_state2->hw.active && 3718 crtc_state1->output_types == crtc_state2->output_types && 3719 crtc_state1->output_format == crtc_state2->output_format && 3720 crtc_state1->lane_count == crtc_state2->lane_count && 3721 crtc_state1->port_clock == crtc_state2->port_clock && 3722 mode_equal(&crtc_state1->hw.adjusted_mode, 3723 &crtc_state2->hw.adjusted_mode) && 3724 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 3725 } 3726 3727 static u8 3728 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 3729 int tile_group_id) 3730 { 3731 struct drm_connector *connector; 3732 const struct drm_connector_state *conn_state; 3733 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 3734 struct intel_atomic_state *state = 3735 to_intel_atomic_state(ref_crtc_state->uapi.state); 3736 u8 transcoders = 0; 3737 int i; 3738 3739 /* 3740 * We don't enable port sync on BDW due to missing w/as and 3741 * due to not having adjusted the modeset sequence appropriately. 3742 */ 3743 if (DISPLAY_VER(dev_priv) < 9) 3744 return 0; 3745 3746 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 3747 return 0; 3748 3749 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 3750 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 3751 const struct intel_crtc_state *crtc_state; 3752 3753 if (!crtc) 3754 continue; 3755 3756 if (!connector->has_tile || 3757 connector->tile_group->id != 3758 tile_group_id) 3759 continue; 3760 crtc_state = intel_atomic_get_new_crtc_state(state, 3761 crtc); 3762 if (!crtcs_port_sync_compatible(ref_crtc_state, 3763 crtc_state)) 3764 continue; 3765 transcoders |= BIT(crtc_state->cpu_transcoder); 3766 } 3767 3768 return transcoders; 3769 } 3770 3771 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 3772 struct intel_crtc_state *crtc_state, 3773 struct drm_connector_state *conn_state) 3774 { 3775 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3776 struct drm_connector *connector = conn_state->connector; 3777 u8 port_sync_transcoders = 0; 3778 3779 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]", 3780 encoder->base.base.id, encoder->base.name, 3781 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 3782 3783 if (connector->has_tile) 3784 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 3785 connector->tile_group->id); 3786 3787 /* 3788 * EDP Transcoders cannot be ensalved 3789 * make them a master always when present 3790 */ 3791 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 3792 crtc_state->master_transcoder = TRANSCODER_EDP; 3793 else 3794 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 3795 3796 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 3797 crtc_state->master_transcoder = INVALID_TRANSCODER; 3798 crtc_state->sync_mode_slaves_mask = 3799 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 3800 } 3801 3802 return 0; 3803 } 3804 3805 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 3806 { 3807 struct drm_i915_private *i915 = to_i915(encoder->dev); 3808 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 3809 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 3810 3811 intel_dp_encoder_flush_work(encoder); 3812 if (intel_phy_is_tc(i915, phy)) 3813 intel_tc_port_flush_work(dig_port); 3814 intel_display_power_flush_work(i915); 3815 3816 drm_encoder_cleanup(encoder); 3817 kfree(dig_port->hdcp_port_data.streams); 3818 kfree(dig_port); 3819 } 3820 3821 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 3822 { 3823 struct drm_i915_private *i915 = to_i915(encoder->dev); 3824 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 3825 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 3826 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 3827 3828 intel_dp->reset_link_params = true; 3829 3830 intel_pps_encoder_reset(intel_dp); 3831 3832 if (intel_phy_is_tc(i915, phy)) 3833 intel_tc_port_init_mode(dig_port); 3834 } 3835 3836 static const struct drm_encoder_funcs intel_ddi_funcs = { 3837 .reset = intel_ddi_encoder_reset, 3838 .destroy = intel_ddi_encoder_destroy, 3839 }; 3840 3841 static struct intel_connector * 3842 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 3843 { 3844 struct intel_connector *connector; 3845 enum port port = dig_port->base.port; 3846 3847 connector = intel_connector_alloc(); 3848 if (!connector) 3849 return NULL; 3850 3851 dig_port->dp.output_reg = DDI_BUF_CTL(port); 3852 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 3853 dig_port->dp.set_link_train = intel_ddi_set_link_train; 3854 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 3855 3856 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 3857 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 3858 3859 if (!intel_dp_init_connector(dig_port, connector)) { 3860 kfree(connector); 3861 return NULL; 3862 } 3863 3864 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 3865 struct drm_device *dev = dig_port->base.base.dev; 3866 struct drm_privacy_screen *privacy_screen; 3867 3868 privacy_screen = drm_privacy_screen_get(dev->dev, NULL); 3869 if (!IS_ERR(privacy_screen)) { 3870 drm_connector_attach_privacy_screen_provider(&connector->base, 3871 privacy_screen); 3872 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 3873 drm_warn(dev, "Error getting privacy-screen\n"); 3874 } 3875 } 3876 3877 return connector; 3878 } 3879 3880 static int modeset_pipe(struct drm_crtc *crtc, 3881 struct drm_modeset_acquire_ctx *ctx) 3882 { 3883 struct drm_atomic_state *state; 3884 struct drm_crtc_state *crtc_state; 3885 int ret; 3886 3887 state = drm_atomic_state_alloc(crtc->dev); 3888 if (!state) 3889 return -ENOMEM; 3890 3891 state->acquire_ctx = ctx; 3892 3893 crtc_state = drm_atomic_get_crtc_state(state, crtc); 3894 if (IS_ERR(crtc_state)) { 3895 ret = PTR_ERR(crtc_state); 3896 goto out; 3897 } 3898 3899 crtc_state->connectors_changed = true; 3900 3901 ret = drm_atomic_commit(state); 3902 out: 3903 drm_atomic_state_put(state); 3904 3905 return ret; 3906 } 3907 3908 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 3909 struct drm_modeset_acquire_ctx *ctx) 3910 { 3911 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3912 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 3913 struct intel_connector *connector = hdmi->attached_connector; 3914 struct i2c_adapter *adapter = 3915 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 3916 struct drm_connector_state *conn_state; 3917 struct intel_crtc_state *crtc_state; 3918 struct intel_crtc *crtc; 3919 u8 config; 3920 int ret; 3921 3922 if (!connector || connector->base.status != connector_status_connected) 3923 return 0; 3924 3925 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 3926 ctx); 3927 if (ret) 3928 return ret; 3929 3930 conn_state = connector->base.state; 3931 3932 crtc = to_intel_crtc(conn_state->crtc); 3933 if (!crtc) 3934 return 0; 3935 3936 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 3937 if (ret) 3938 return ret; 3939 3940 crtc_state = to_intel_crtc_state(crtc->base.state); 3941 3942 drm_WARN_ON(&dev_priv->drm, 3943 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 3944 3945 if (!crtc_state->hw.active) 3946 return 0; 3947 3948 if (!crtc_state->hdmi_high_tmds_clock_ratio && 3949 !crtc_state->hdmi_scrambling) 3950 return 0; 3951 3952 if (conn_state->commit && 3953 !try_wait_for_completion(&conn_state->commit->hw_done)) 3954 return 0; 3955 3956 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 3957 if (ret < 0) { 3958 drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n", 3959 ret); 3960 return 0; 3961 } 3962 3963 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 3964 crtc_state->hdmi_high_tmds_clock_ratio && 3965 !!(config & SCDC_SCRAMBLING_ENABLE) == 3966 crtc_state->hdmi_scrambling) 3967 return 0; 3968 3969 /* 3970 * HDMI 2.0 says that one should not send scrambled data 3971 * prior to configuring the sink scrambling, and that 3972 * TMDS clock/data transmission should be suspended when 3973 * changing the TMDS clock rate in the sink. So let's 3974 * just do a full modeset here, even though some sinks 3975 * would be perfectly happy if were to just reconfigure 3976 * the SCDC settings on the fly. 3977 */ 3978 return modeset_pipe(&crtc->base, ctx); 3979 } 3980 3981 static enum intel_hotplug_state 3982 intel_ddi_hotplug(struct intel_encoder *encoder, 3983 struct intel_connector *connector) 3984 { 3985 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3986 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3987 struct intel_dp *intel_dp = &dig_port->dp; 3988 enum phy phy = intel_port_to_phy(i915, encoder->port); 3989 bool is_tc = intel_phy_is_tc(i915, phy); 3990 struct drm_modeset_acquire_ctx ctx; 3991 enum intel_hotplug_state state; 3992 int ret; 3993 3994 if (intel_dp->compliance.test_active && 3995 intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) { 3996 intel_dp_phy_test(encoder); 3997 /* just do the PHY test and nothing else */ 3998 return INTEL_HOTPLUG_UNCHANGED; 3999 } 4000 4001 state = intel_encoder_hotplug(encoder, connector); 4002 4003 drm_modeset_acquire_init(&ctx, 0); 4004 4005 for (;;) { 4006 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) 4007 ret = intel_hdmi_reset_link(encoder, &ctx); 4008 else 4009 ret = intel_dp_retrain_link(encoder, &ctx); 4010 4011 if (ret == -EDEADLK) { 4012 drm_modeset_backoff(&ctx); 4013 continue; 4014 } 4015 4016 break; 4017 } 4018 4019 drm_modeset_drop_locks(&ctx); 4020 drm_modeset_acquire_fini(&ctx); 4021 drm_WARN(encoder->base.dev, ret, 4022 "Acquiring modeset locks failed with %i\n", ret); 4023 4024 /* 4025 * Unpowered type-c dongles can take some time to boot and be 4026 * responsible, so here giving some time to those dongles to power up 4027 * and then retrying the probe. 4028 * 4029 * On many platforms the HDMI live state signal is known to be 4030 * unreliable, so we can't use it to detect if a sink is connected or 4031 * not. Instead we detect if it's connected based on whether we can 4032 * read the EDID or not. That in turn has a problem during disconnect, 4033 * since the HPD interrupt may be raised before the DDC lines get 4034 * disconnected (due to how the required length of DDC vs. HPD 4035 * connector pins are specified) and so we'll still be able to get a 4036 * valid EDID. To solve this schedule another detection cycle if this 4037 * time around we didn't detect any change in the sink's connection 4038 * status. 4039 * 4040 * Type-c connectors which get their HPD signal deasserted then 4041 * reasserted, without unplugging/replugging the sink from the 4042 * connector, introduce a delay until the AUX channel communication 4043 * becomes functional. Retry the detection for 5 seconds on type-c 4044 * connectors to account for this delay. 4045 */ 4046 if (state == INTEL_HOTPLUG_UNCHANGED && 4047 connector->hotplug_retries < (is_tc ? 5 : 1) && 4048 !dig_port->dp.is_mst) 4049 state = INTEL_HOTPLUG_RETRY; 4050 4051 return state; 4052 } 4053 4054 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4055 { 4056 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4057 u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin]; 4058 4059 return intel_de_read(dev_priv, SDEISR) & bit; 4060 } 4061 4062 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4063 { 4064 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4065 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4066 4067 return intel_de_read(dev_priv, DEISR) & bit; 4068 } 4069 4070 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4071 { 4072 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4073 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4074 4075 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; 4076 } 4077 4078 static struct intel_connector * 4079 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4080 { 4081 struct intel_connector *connector; 4082 enum port port = dig_port->base.port; 4083 4084 connector = intel_connector_alloc(); 4085 if (!connector) 4086 return NULL; 4087 4088 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4089 intel_hdmi_init_connector(dig_port, connector); 4090 4091 return connector; 4092 } 4093 4094 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4095 { 4096 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4097 4098 if (dig_port->base.port != PORT_A) 4099 return false; 4100 4101 if (dig_port->saved_port_bits & DDI_A_4_LANES) 4102 return false; 4103 4104 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4105 * supported configuration 4106 */ 4107 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4108 return true; 4109 4110 return false; 4111 } 4112 4113 static int 4114 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4115 { 4116 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4117 enum port port = dig_port->base.port; 4118 int max_lanes = 4; 4119 4120 if (DISPLAY_VER(dev_priv) >= 11) 4121 return max_lanes; 4122 4123 if (port == PORT_A || port == PORT_E) { 4124 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4125 max_lanes = port == PORT_A ? 4 : 0; 4126 else 4127 /* Both A and E share 2 lanes */ 4128 max_lanes = 2; 4129 } 4130 4131 /* 4132 * Some BIOS might fail to set this bit on port A if eDP 4133 * wasn't lit up at boot. Force this bit set when needed 4134 * so we use the proper lane count for our calculations. 4135 */ 4136 if (intel_ddi_a_force_4_lanes(dig_port)) { 4137 drm_dbg_kms(&dev_priv->drm, 4138 "Forcing DDI_A_4_LANES for port A\n"); 4139 dig_port->saved_port_bits |= DDI_A_4_LANES; 4140 max_lanes = 4; 4141 } 4142 4143 return max_lanes; 4144 } 4145 4146 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv, 4147 enum port port) 4148 { 4149 if (port >= PORT_D_XELPD) 4150 return HPD_PORT_D + port - PORT_D_XELPD; 4151 else if (port >= PORT_TC1) 4152 return HPD_PORT_TC1 + port - PORT_TC1; 4153 else 4154 return HPD_PORT_A + port - PORT_A; 4155 } 4156 4157 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, 4158 enum port port) 4159 { 4160 if (port >= PORT_TC1) 4161 return HPD_PORT_C + port - PORT_TC1; 4162 else 4163 return HPD_PORT_A + port - PORT_A; 4164 } 4165 4166 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, 4167 enum port port) 4168 { 4169 if (port >= PORT_TC1) 4170 return HPD_PORT_TC1 + port - PORT_TC1; 4171 else 4172 return HPD_PORT_A + port - PORT_A; 4173 } 4174 4175 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, 4176 enum port port) 4177 { 4178 if (HAS_PCH_TGP(dev_priv)) 4179 return tgl_hpd_pin(dev_priv, port); 4180 4181 if (port >= PORT_TC1) 4182 return HPD_PORT_C + port - PORT_TC1; 4183 else 4184 return HPD_PORT_A + port - PORT_A; 4185 } 4186 4187 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, 4188 enum port port) 4189 { 4190 if (port >= PORT_C) 4191 return HPD_PORT_TC1 + port - PORT_C; 4192 else 4193 return HPD_PORT_A + port - PORT_A; 4194 } 4195 4196 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, 4197 enum port port) 4198 { 4199 if (port == PORT_D) 4200 return HPD_PORT_A; 4201 4202 if (HAS_PCH_TGP(dev_priv)) 4203 return icl_hpd_pin(dev_priv, port); 4204 4205 return HPD_PORT_A + port - PORT_A; 4206 } 4207 4208 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) 4209 { 4210 if (HAS_PCH_TGP(dev_priv)) 4211 return icl_hpd_pin(dev_priv, port); 4212 4213 return HPD_PORT_A + port - PORT_A; 4214 } 4215 4216 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port) 4217 { 4218 if (DISPLAY_VER(i915) >= 12) 4219 return port >= PORT_TC1; 4220 else if (DISPLAY_VER(i915) >= 11) 4221 return port >= PORT_C; 4222 else 4223 return false; 4224 } 4225 4226 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 4227 { 4228 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4229 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4230 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4231 enum phy phy = intel_port_to_phy(i915, encoder->port); 4232 4233 intel_dp_encoder_suspend(encoder); 4234 4235 if (!intel_phy_is_tc(i915, phy)) 4236 return; 4237 4238 intel_tc_port_flush_work(dig_port); 4239 } 4240 4241 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 4242 { 4243 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4244 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4245 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4246 enum phy phy = intel_port_to_phy(i915, encoder->port); 4247 4248 intel_dp_encoder_shutdown(encoder); 4249 intel_hdmi_encoder_shutdown(encoder); 4250 4251 if (!intel_phy_is_tc(i915, phy)) 4252 return; 4253 4254 intel_tc_port_flush_work(dig_port); 4255 } 4256 4257 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 4258 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 4259 4260 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 4261 { 4262 struct intel_digital_port *dig_port; 4263 struct intel_encoder *encoder; 4264 const struct intel_bios_encoder_data *devdata; 4265 bool init_hdmi, init_dp; 4266 enum phy phy = intel_port_to_phy(dev_priv, port); 4267 4268 /* 4269 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 4270 * have taken over some of the PHYs and made them unavailable to the 4271 * driver. In that case we should skip initializing the corresponding 4272 * outputs. 4273 */ 4274 if (intel_hti_uses_phy(dev_priv, phy)) { 4275 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", 4276 port_name(port), phy_name(phy)); 4277 return; 4278 } 4279 4280 devdata = intel_bios_encoder_data_lookup(dev_priv, port); 4281 if (!devdata) { 4282 drm_dbg_kms(&dev_priv->drm, 4283 "VBT says port %c is not present\n", 4284 port_name(port)); 4285 return; 4286 } 4287 4288 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 4289 intel_bios_encoder_supports_hdmi(devdata); 4290 init_dp = intel_bios_encoder_supports_dp(devdata); 4291 4292 if (intel_bios_encoder_is_lspcon(devdata)) { 4293 /* 4294 * Lspcon device needs to be driven with DP connector 4295 * with special detection sequence. So make sure DP 4296 * is initialized before lspcon. 4297 */ 4298 init_dp = true; 4299 init_hdmi = false; 4300 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", 4301 port_name(port)); 4302 } 4303 4304 if (!init_dp && !init_hdmi) { 4305 drm_dbg_kms(&dev_priv->drm, 4306 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 4307 port_name(port)); 4308 return; 4309 } 4310 4311 if (intel_phy_is_snps(dev_priv, phy) && 4312 dev_priv->display.snps.phy_failed_calibration & BIT(phy)) { 4313 drm_dbg_kms(&dev_priv->drm, 4314 "SNPS PHY %c failed to calibrate, proceeding anyway\n", 4315 phy_name(phy)); 4316 } 4317 4318 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 4319 if (!dig_port) 4320 return; 4321 4322 encoder = &dig_port->base; 4323 encoder->devdata = devdata; 4324 4325 if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) { 4326 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4327 DRM_MODE_ENCODER_TMDS, 4328 "DDI %c/PHY %c", 4329 port_name(port - PORT_D_XELPD + PORT_D), 4330 phy_name(phy)); 4331 } else if (DISPLAY_VER(dev_priv) >= 12) { 4332 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4333 4334 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4335 DRM_MODE_ENCODER_TMDS, 4336 "DDI %s%c/PHY %s%c", 4337 port >= PORT_TC1 ? "TC" : "", 4338 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 4339 tc_port != TC_PORT_NONE ? "TC" : "", 4340 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4341 } else if (DISPLAY_VER(dev_priv) >= 11) { 4342 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4343 4344 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4345 DRM_MODE_ENCODER_TMDS, 4346 "DDI %c%s/PHY %s%c", 4347 port_name(port), 4348 port >= PORT_C ? " (TC)" : "", 4349 tc_port != TC_PORT_NONE ? "TC" : "", 4350 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4351 } else { 4352 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4353 DRM_MODE_ENCODER_TMDS, 4354 "DDI %c/PHY %c", port_name(port), phy_name(phy)); 4355 } 4356 4357 mutex_init(&dig_port->hdcp_mutex); 4358 dig_port->num_hdcp_streams = 0; 4359 4360 encoder->hotplug = intel_ddi_hotplug; 4361 encoder->compute_output_type = intel_ddi_compute_output_type; 4362 encoder->compute_config = intel_ddi_compute_config; 4363 encoder->compute_config_late = intel_ddi_compute_config_late; 4364 encoder->enable = intel_enable_ddi; 4365 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 4366 encoder->pre_enable = intel_ddi_pre_enable; 4367 encoder->disable = intel_disable_ddi; 4368 encoder->post_disable = intel_ddi_post_disable; 4369 encoder->update_pipe = intel_ddi_update_pipe; 4370 encoder->get_hw_state = intel_ddi_get_hw_state; 4371 encoder->sync_state = intel_ddi_sync_state; 4372 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 4373 encoder->suspend = intel_ddi_encoder_suspend; 4374 encoder->shutdown = intel_ddi_encoder_shutdown; 4375 encoder->get_power_domains = intel_ddi_get_power_domains; 4376 4377 encoder->type = INTEL_OUTPUT_DDI; 4378 encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port); 4379 encoder->port = port; 4380 encoder->cloneable = 0; 4381 encoder->pipe_mask = ~0; 4382 4383 if (IS_DG2(dev_priv)) { 4384 encoder->enable_clock = intel_mpllb_enable; 4385 encoder->disable_clock = intel_mpllb_disable; 4386 encoder->get_config = dg2_ddi_get_config; 4387 } else if (IS_ALDERLAKE_S(dev_priv)) { 4388 encoder->enable_clock = adls_ddi_enable_clock; 4389 encoder->disable_clock = adls_ddi_disable_clock; 4390 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 4391 encoder->get_config = adls_ddi_get_config; 4392 } else if (IS_ROCKETLAKE(dev_priv)) { 4393 encoder->enable_clock = rkl_ddi_enable_clock; 4394 encoder->disable_clock = rkl_ddi_disable_clock; 4395 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 4396 encoder->get_config = rkl_ddi_get_config; 4397 } else if (IS_DG1(dev_priv)) { 4398 encoder->enable_clock = dg1_ddi_enable_clock; 4399 encoder->disable_clock = dg1_ddi_disable_clock; 4400 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 4401 encoder->get_config = dg1_ddi_get_config; 4402 } else if (IS_JSL_EHL(dev_priv)) { 4403 if (intel_ddi_is_tc(dev_priv, port)) { 4404 encoder->enable_clock = jsl_ddi_tc_enable_clock; 4405 encoder->disable_clock = jsl_ddi_tc_disable_clock; 4406 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 4407 encoder->get_config = icl_ddi_combo_get_config; 4408 } else { 4409 encoder->enable_clock = icl_ddi_combo_enable_clock; 4410 encoder->disable_clock = icl_ddi_combo_disable_clock; 4411 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 4412 encoder->get_config = icl_ddi_combo_get_config; 4413 } 4414 } else if (DISPLAY_VER(dev_priv) >= 11) { 4415 if (intel_ddi_is_tc(dev_priv, port)) { 4416 encoder->enable_clock = icl_ddi_tc_enable_clock; 4417 encoder->disable_clock = icl_ddi_tc_disable_clock; 4418 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 4419 encoder->get_config = icl_ddi_tc_get_config; 4420 } else { 4421 encoder->enable_clock = icl_ddi_combo_enable_clock; 4422 encoder->disable_clock = icl_ddi_combo_disable_clock; 4423 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 4424 encoder->get_config = icl_ddi_combo_get_config; 4425 } 4426 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 4427 /* BXT/GLK have fixed PLL->port mapping */ 4428 encoder->get_config = bxt_ddi_get_config; 4429 } else if (DISPLAY_VER(dev_priv) == 9) { 4430 encoder->enable_clock = skl_ddi_enable_clock; 4431 encoder->disable_clock = skl_ddi_disable_clock; 4432 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 4433 encoder->get_config = skl_ddi_get_config; 4434 } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 4435 encoder->enable_clock = hsw_ddi_enable_clock; 4436 encoder->disable_clock = hsw_ddi_disable_clock; 4437 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 4438 encoder->get_config = hsw_ddi_get_config; 4439 } 4440 4441 if (IS_DG2(dev_priv)) { 4442 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 4443 } else if (DISPLAY_VER(dev_priv) >= 12) { 4444 if (intel_phy_is_combo(dev_priv, phy)) 4445 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 4446 else 4447 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 4448 } else if (DISPLAY_VER(dev_priv) >= 11) { 4449 if (intel_phy_is_combo(dev_priv, phy)) 4450 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 4451 else 4452 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 4453 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 4454 encoder->set_signal_levels = bxt_ddi_phy_set_signal_levels; 4455 } else { 4456 encoder->set_signal_levels = hsw_set_signal_levels; 4457 } 4458 4459 intel_ddi_buf_trans_init(encoder); 4460 4461 if (DISPLAY_VER(dev_priv) >= 13) 4462 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port); 4463 else if (IS_DG1(dev_priv)) 4464 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); 4465 else if (IS_ROCKETLAKE(dev_priv)) 4466 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); 4467 else if (DISPLAY_VER(dev_priv) >= 12) 4468 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); 4469 else if (IS_JSL_EHL(dev_priv)) 4470 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); 4471 else if (DISPLAY_VER(dev_priv) == 11) 4472 encoder->hpd_pin = icl_hpd_pin(dev_priv, port); 4473 else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 4474 encoder->hpd_pin = skl_hpd_pin(dev_priv, port); 4475 else 4476 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 4477 4478 if (DISPLAY_VER(dev_priv) >= 11) 4479 dig_port->saved_port_bits = 4480 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 4481 & DDI_BUF_PORT_REVERSAL; 4482 else 4483 dig_port->saved_port_bits = 4484 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 4485 & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 4486 4487 if (intel_bios_encoder_lane_reversal(devdata)) 4488 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL; 4489 4490 dig_port->dp.output_reg = INVALID_MMIO_REG; 4491 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 4492 dig_port->aux_ch = intel_dp_aux_ch(encoder); 4493 4494 if (intel_phy_is_tc(dev_priv, phy)) { 4495 bool is_legacy = 4496 !intel_bios_encoder_supports_typec_usb(devdata) && 4497 !intel_bios_encoder_supports_tbt(devdata); 4498 4499 intel_tc_port_init(dig_port, is_legacy); 4500 4501 encoder->update_prepare = intel_ddi_update_prepare; 4502 encoder->update_complete = intel_ddi_update_complete; 4503 } 4504 4505 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 4506 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(dev_priv, port); 4507 4508 if (DISPLAY_VER(dev_priv) >= 11) { 4509 if (intel_phy_is_tc(dev_priv, phy)) 4510 dig_port->connected = intel_tc_port_connected; 4511 else 4512 dig_port->connected = lpt_digital_port_connected; 4513 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 4514 dig_port->connected = bdw_digital_port_connected; 4515 } else if (DISPLAY_VER(dev_priv) == 9) { 4516 dig_port->connected = lpt_digital_port_connected; 4517 } else if (IS_BROADWELL(dev_priv)) { 4518 if (port == PORT_A) 4519 dig_port->connected = bdw_digital_port_connected; 4520 else 4521 dig_port->connected = lpt_digital_port_connected; 4522 } else if (IS_HASWELL(dev_priv)) { 4523 if (port == PORT_A) 4524 dig_port->connected = hsw_digital_port_connected; 4525 else 4526 dig_port->connected = lpt_digital_port_connected; 4527 } 4528 4529 intel_infoframe_init(dig_port); 4530 4531 if (init_dp) { 4532 if (!intel_ddi_init_dp_connector(dig_port)) 4533 goto err; 4534 4535 dig_port->hpd_pulse = intel_dp_hpd_pulse; 4536 4537 if (dig_port->dp.mso_link_count) 4538 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv); 4539 } 4540 4541 /* 4542 * In theory we don't need the encoder->type check, 4543 * but leave it just in case we have some really bad VBTs... 4544 */ 4545 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 4546 if (!intel_ddi_init_hdmi_connector(dig_port)) 4547 goto err; 4548 } 4549 4550 return; 4551 4552 err: 4553 drm_encoder_cleanup(&encoder->base); 4554 kfree(dig_port); 4555 } 4556