1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <drm/drm_scdc_helper.h> 29 30 #include "i915_drv.h" 31 #include "intel_audio.h" 32 #include "intel_combo_phy.h" 33 #include "intel_connector.h" 34 #include "intel_ddi.h" 35 #include "intel_display_types.h" 36 #include "intel_dp.h" 37 #include "intel_dp_mst.h" 38 #include "intel_dp_link_training.h" 39 #include "intel_dpio_phy.h" 40 #include "intel_dsi.h" 41 #include "intel_fifo_underrun.h" 42 #include "intel_gmbus.h" 43 #include "intel_hdcp.h" 44 #include "intel_hdmi.h" 45 #include "intel_hotplug.h" 46 #include "intel_lspcon.h" 47 #include "intel_panel.h" 48 #include "intel_psr.h" 49 #include "intel_sprite.h" 50 #include "intel_tc.h" 51 #include "intel_vdsc.h" 52 53 struct ddi_buf_trans { 54 u32 trans1; /* balance leg enable, de-emph level */ 55 u32 trans2; /* vref sel, vswing */ 56 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */ 57 }; 58 59 static const u8 index_to_dp_signal_levels[] = { 60 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 61 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 62 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 63 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 64 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 65 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 66 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 67 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 68 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 69 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 70 }; 71 72 /* HDMI/DVI modes ignore everything but the last 2 items. So we share 73 * them for both DP and FDI transports, allowing those ports to 74 * automatically adapt to HDMI connections as well 75 */ 76 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { 77 { 0x00FFFFFF, 0x0006000E, 0x0 }, 78 { 0x00D75FFF, 0x0005000A, 0x0 }, 79 { 0x00C30FFF, 0x00040006, 0x0 }, 80 { 0x80AAAFFF, 0x000B0000, 0x0 }, 81 { 0x00FFFFFF, 0x0005000A, 0x0 }, 82 { 0x00D75FFF, 0x000C0004, 0x0 }, 83 { 0x80C30FFF, 0x000B0000, 0x0 }, 84 { 0x00FFFFFF, 0x00040006, 0x0 }, 85 { 0x80D75FFF, 0x000B0000, 0x0 }, 86 }; 87 88 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { 89 { 0x00FFFFFF, 0x0007000E, 0x0 }, 90 { 0x00D75FFF, 0x000F000A, 0x0 }, 91 { 0x00C30FFF, 0x00060006, 0x0 }, 92 { 0x00AAAFFF, 0x001E0000, 0x0 }, 93 { 0x00FFFFFF, 0x000F000A, 0x0 }, 94 { 0x00D75FFF, 0x00160004, 0x0 }, 95 { 0x00C30FFF, 0x001E0000, 0x0 }, 96 { 0x00FFFFFF, 0x00060006, 0x0 }, 97 { 0x00D75FFF, 0x001E0000, 0x0 }, 98 }; 99 100 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { 101 /* Idx NT mV d T mV d db */ 102 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */ 103 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */ 104 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */ 105 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */ 106 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */ 107 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */ 108 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */ 109 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */ 110 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */ 111 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */ 112 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */ 113 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */ 114 }; 115 116 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { 117 { 0x00FFFFFF, 0x00000012, 0x0 }, 118 { 0x00EBAFFF, 0x00020011, 0x0 }, 119 { 0x00C71FFF, 0x0006000F, 0x0 }, 120 { 0x00AAAFFF, 0x000E000A, 0x0 }, 121 { 0x00FFFFFF, 0x00020011, 0x0 }, 122 { 0x00DB6FFF, 0x0005000F, 0x0 }, 123 { 0x00BEEFFF, 0x000A000C, 0x0 }, 124 { 0x00FFFFFF, 0x0005000F, 0x0 }, 125 { 0x00DB6FFF, 0x000A000C, 0x0 }, 126 }; 127 128 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { 129 { 0x00FFFFFF, 0x0007000E, 0x0 }, 130 { 0x00D75FFF, 0x000E000A, 0x0 }, 131 { 0x00BEFFFF, 0x00140006, 0x0 }, 132 { 0x80B2CFFF, 0x001B0002, 0x0 }, 133 { 0x00FFFFFF, 0x000E000A, 0x0 }, 134 { 0x00DB6FFF, 0x00160005, 0x0 }, 135 { 0x80C71FFF, 0x001A0002, 0x0 }, 136 { 0x00F7DFFF, 0x00180004, 0x0 }, 137 { 0x80D75FFF, 0x001B0002, 0x0 }, 138 }; 139 140 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { 141 { 0x00FFFFFF, 0x0001000E, 0x0 }, 142 { 0x00D75FFF, 0x0004000A, 0x0 }, 143 { 0x00C30FFF, 0x00070006, 0x0 }, 144 { 0x00AAAFFF, 0x000C0000, 0x0 }, 145 { 0x00FFFFFF, 0x0004000A, 0x0 }, 146 { 0x00D75FFF, 0x00090004, 0x0 }, 147 { 0x00C30FFF, 0x000C0000, 0x0 }, 148 { 0x00FFFFFF, 0x00070006, 0x0 }, 149 { 0x00D75FFF, 0x000C0000, 0x0 }, 150 }; 151 152 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { 153 /* Idx NT mV d T mV df db */ 154 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */ 155 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */ 156 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */ 157 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */ 158 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */ 159 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */ 160 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */ 161 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */ 162 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */ 163 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */ 164 }; 165 166 /* Skylake H and S */ 167 static const struct ddi_buf_trans skl_ddi_translations_dp[] = { 168 { 0x00002016, 0x000000A0, 0x0 }, 169 { 0x00005012, 0x0000009B, 0x0 }, 170 { 0x00007011, 0x00000088, 0x0 }, 171 { 0x80009010, 0x000000C0, 0x1 }, 172 { 0x00002016, 0x0000009B, 0x0 }, 173 { 0x00005012, 0x00000088, 0x0 }, 174 { 0x80007011, 0x000000C0, 0x1 }, 175 { 0x00002016, 0x000000DF, 0x0 }, 176 { 0x80005012, 0x000000C0, 0x1 }, 177 }; 178 179 /* Skylake U */ 180 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { 181 { 0x0000201B, 0x000000A2, 0x0 }, 182 { 0x00005012, 0x00000088, 0x0 }, 183 { 0x80007011, 0x000000CD, 0x1 }, 184 { 0x80009010, 0x000000C0, 0x1 }, 185 { 0x0000201B, 0x0000009D, 0x0 }, 186 { 0x80005012, 0x000000C0, 0x1 }, 187 { 0x80007011, 0x000000C0, 0x1 }, 188 { 0x00002016, 0x00000088, 0x0 }, 189 { 0x80005012, 0x000000C0, 0x1 }, 190 }; 191 192 /* Skylake Y */ 193 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { 194 { 0x00000018, 0x000000A2, 0x0 }, 195 { 0x00005012, 0x00000088, 0x0 }, 196 { 0x80007011, 0x000000CD, 0x3 }, 197 { 0x80009010, 0x000000C0, 0x3 }, 198 { 0x00000018, 0x0000009D, 0x0 }, 199 { 0x80005012, 0x000000C0, 0x3 }, 200 { 0x80007011, 0x000000C0, 0x3 }, 201 { 0x00000018, 0x00000088, 0x0 }, 202 { 0x80005012, 0x000000C0, 0x3 }, 203 }; 204 205 /* Kabylake H and S */ 206 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = { 207 { 0x00002016, 0x000000A0, 0x0 }, 208 { 0x00005012, 0x0000009B, 0x0 }, 209 { 0x00007011, 0x00000088, 0x0 }, 210 { 0x80009010, 0x000000C0, 0x1 }, 211 { 0x00002016, 0x0000009B, 0x0 }, 212 { 0x00005012, 0x00000088, 0x0 }, 213 { 0x80007011, 0x000000C0, 0x1 }, 214 { 0x00002016, 0x00000097, 0x0 }, 215 { 0x80005012, 0x000000C0, 0x1 }, 216 }; 217 218 /* Kabylake U */ 219 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = { 220 { 0x0000201B, 0x000000A1, 0x0 }, 221 { 0x00005012, 0x00000088, 0x0 }, 222 { 0x80007011, 0x000000CD, 0x3 }, 223 { 0x80009010, 0x000000C0, 0x3 }, 224 { 0x0000201B, 0x0000009D, 0x0 }, 225 { 0x80005012, 0x000000C0, 0x3 }, 226 { 0x80007011, 0x000000C0, 0x3 }, 227 { 0x00002016, 0x0000004F, 0x0 }, 228 { 0x80005012, 0x000000C0, 0x3 }, 229 }; 230 231 /* Kabylake Y */ 232 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = { 233 { 0x00001017, 0x000000A1, 0x0 }, 234 { 0x00005012, 0x00000088, 0x0 }, 235 { 0x80007011, 0x000000CD, 0x3 }, 236 { 0x8000800F, 0x000000C0, 0x3 }, 237 { 0x00001017, 0x0000009D, 0x0 }, 238 { 0x80005012, 0x000000C0, 0x3 }, 239 { 0x80007011, 0x000000C0, 0x3 }, 240 { 0x00001017, 0x0000004C, 0x0 }, 241 { 0x80005012, 0x000000C0, 0x3 }, 242 }; 243 244 /* 245 * Skylake/Kabylake H and S 246 * eDP 1.4 low vswing translation parameters 247 */ 248 static const struct ddi_buf_trans skl_ddi_translations_edp[] = { 249 { 0x00000018, 0x000000A8, 0x0 }, 250 { 0x00004013, 0x000000A9, 0x0 }, 251 { 0x00007011, 0x000000A2, 0x0 }, 252 { 0x00009010, 0x0000009C, 0x0 }, 253 { 0x00000018, 0x000000A9, 0x0 }, 254 { 0x00006013, 0x000000A2, 0x0 }, 255 { 0x00007011, 0x000000A6, 0x0 }, 256 { 0x00000018, 0x000000AB, 0x0 }, 257 { 0x00007013, 0x0000009F, 0x0 }, 258 { 0x00000018, 0x000000DF, 0x0 }, 259 }; 260 261 /* 262 * Skylake/Kabylake U 263 * eDP 1.4 low vswing translation parameters 264 */ 265 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = { 266 { 0x00000018, 0x000000A8, 0x0 }, 267 { 0x00004013, 0x000000A9, 0x0 }, 268 { 0x00007011, 0x000000A2, 0x0 }, 269 { 0x00009010, 0x0000009C, 0x0 }, 270 { 0x00000018, 0x000000A9, 0x0 }, 271 { 0x00006013, 0x000000A2, 0x0 }, 272 { 0x00007011, 0x000000A6, 0x0 }, 273 { 0x00002016, 0x000000AB, 0x0 }, 274 { 0x00005013, 0x0000009F, 0x0 }, 275 { 0x00000018, 0x000000DF, 0x0 }, 276 }; 277 278 /* 279 * Skylake/Kabylake Y 280 * eDP 1.4 low vswing translation parameters 281 */ 282 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = { 283 { 0x00000018, 0x000000A8, 0x0 }, 284 { 0x00004013, 0x000000AB, 0x0 }, 285 { 0x00007011, 0x000000A4, 0x0 }, 286 { 0x00009010, 0x000000DF, 0x0 }, 287 { 0x00000018, 0x000000AA, 0x0 }, 288 { 0x00006013, 0x000000A4, 0x0 }, 289 { 0x00007011, 0x0000009D, 0x0 }, 290 { 0x00000018, 0x000000A0, 0x0 }, 291 { 0x00006012, 0x000000DF, 0x0 }, 292 { 0x00000018, 0x0000008A, 0x0 }, 293 }; 294 295 /* Skylake/Kabylake U, H and S */ 296 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { 297 { 0x00000018, 0x000000AC, 0x0 }, 298 { 0x00005012, 0x0000009D, 0x0 }, 299 { 0x00007011, 0x00000088, 0x0 }, 300 { 0x00000018, 0x000000A1, 0x0 }, 301 { 0x00000018, 0x00000098, 0x0 }, 302 { 0x00004013, 0x00000088, 0x0 }, 303 { 0x80006012, 0x000000CD, 0x1 }, 304 { 0x00000018, 0x000000DF, 0x0 }, 305 { 0x80003015, 0x000000CD, 0x1 }, /* Default */ 306 { 0x80003015, 0x000000C0, 0x1 }, 307 { 0x80000018, 0x000000C0, 0x1 }, 308 }; 309 310 /* Skylake/Kabylake Y */ 311 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { 312 { 0x00000018, 0x000000A1, 0x0 }, 313 { 0x00005012, 0x000000DF, 0x0 }, 314 { 0x80007011, 0x000000CB, 0x3 }, 315 { 0x00000018, 0x000000A4, 0x0 }, 316 { 0x00000018, 0x0000009D, 0x0 }, 317 { 0x00004013, 0x00000080, 0x0 }, 318 { 0x80006013, 0x000000C0, 0x3 }, 319 { 0x00000018, 0x0000008A, 0x0 }, 320 { 0x80003015, 0x000000C0, 0x3 }, /* Default */ 321 { 0x80003015, 0x000000C0, 0x3 }, 322 { 0x80000018, 0x000000C0, 0x3 }, 323 }; 324 325 struct bxt_ddi_buf_trans { 326 u8 margin; /* swing value */ 327 u8 scale; /* scale value */ 328 u8 enable; /* scale enable */ 329 u8 deemphasis; 330 }; 331 332 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { 333 /* Idx NT mV diff db */ 334 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ 335 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */ 336 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */ 337 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */ 338 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */ 339 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */ 340 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */ 341 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */ 342 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */ 343 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */ 344 }; 345 346 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = { 347 /* Idx NT mV diff db */ 348 { 26, 0, 0, 128, }, /* 0: 200 0 */ 349 { 38, 0, 0, 112, }, /* 1: 200 1.5 */ 350 { 48, 0, 0, 96, }, /* 2: 200 4 */ 351 { 54, 0, 0, 69, }, /* 3: 200 6 */ 352 { 32, 0, 0, 128, }, /* 4: 250 0 */ 353 { 48, 0, 0, 104, }, /* 5: 250 1.5 */ 354 { 54, 0, 0, 85, }, /* 6: 250 4 */ 355 { 43, 0, 0, 128, }, /* 7: 300 0 */ 356 { 54, 0, 0, 101, }, /* 8: 300 1.5 */ 357 { 48, 0, 0, 128, }, /* 9: 300 0 */ 358 }; 359 360 /* BSpec has 2 recommended values - entries 0 and 8. 361 * Using the entry with higher vswing. 362 */ 363 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = { 364 /* Idx NT mV diff db */ 365 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ 366 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */ 367 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */ 368 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */ 369 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */ 370 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */ 371 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */ 372 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */ 373 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */ 374 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */ 375 }; 376 377 struct cnl_ddi_buf_trans { 378 u8 dw2_swing_sel; 379 u8 dw7_n_scalar; 380 u8 dw4_cursor_coeff; 381 u8 dw4_post_cursor_2; 382 u8 dw4_post_cursor_1; 383 }; 384 385 /* Voltage Swing Programming for VccIO 0.85V for DP */ 386 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = { 387 /* NT mV Trans mV db */ 388 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 389 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ 390 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ 391 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ 392 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 393 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 394 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 395 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ 396 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ 397 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 398 }; 399 400 /* Voltage Swing Programming for VccIO 0.85V for HDMI */ 401 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = { 402 /* NT mV Trans mV db */ 403 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 404 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ 405 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ 406 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */ 407 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ 408 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ 409 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 410 }; 411 412 /* Voltage Swing Programming for VccIO 0.85V for eDP */ 413 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = { 414 /* NT mV Trans mV db */ 415 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 416 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 417 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 418 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 419 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 420 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 421 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */ 422 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */ 423 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 424 }; 425 426 /* Voltage Swing Programming for VccIO 0.95V for DP */ 427 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = { 428 /* NT mV Trans mV db */ 429 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 430 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ 431 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ 432 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ 433 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 434 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 435 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 436 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ 437 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ 438 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 439 }; 440 441 /* Voltage Swing Programming for VccIO 0.95V for HDMI */ 442 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = { 443 /* NT mV Trans mV db */ 444 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 445 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 446 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 447 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 448 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 449 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 450 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ 451 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ 452 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ 453 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ 454 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 455 }; 456 457 /* Voltage Swing Programming for VccIO 0.95V for eDP */ 458 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = { 459 /* NT mV Trans mV db */ 460 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 461 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 462 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 463 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 464 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 465 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 466 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ 467 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ 468 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */ 469 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 470 }; 471 472 /* Voltage Swing Programming for VccIO 1.05V for DP */ 473 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = { 474 /* NT mV Trans mV db */ 475 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 476 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 477 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 478 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */ 479 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 480 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 481 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */ 482 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */ 483 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */ 484 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 485 }; 486 487 /* Voltage Swing Programming for VccIO 1.05V for HDMI */ 488 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = { 489 /* NT mV Trans mV db */ 490 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 491 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 492 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 493 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 494 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 495 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 496 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ 497 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ 498 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ 499 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ 500 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 501 }; 502 503 /* Voltage Swing Programming for VccIO 1.05V for eDP */ 504 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = { 505 /* NT mV Trans mV db */ 506 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 507 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 508 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 509 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 510 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 511 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 512 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ 513 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ 514 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 515 }; 516 517 /* icl_combo_phy_ddi_translations */ 518 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = { 519 /* NT mV Trans mV db */ 520 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 521 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 522 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 523 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 524 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 525 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 526 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 527 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 528 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 529 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 530 }; 531 532 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = { 533 /* NT mV Trans mV db */ 534 { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ 535 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */ 536 { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */ 537 { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */ 538 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ 539 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */ 540 { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */ 541 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ 542 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ 543 { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 544 }; 545 546 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = { 547 /* NT mV Trans mV db */ 548 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 549 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 550 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 551 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 552 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 553 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 554 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 555 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 556 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 557 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 558 }; 559 560 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = { 561 /* NT mV Trans mV db */ 562 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 563 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ 564 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ 565 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */ 566 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ 567 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ 568 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 569 }; 570 571 static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = { 572 /* NT mV Trans mV db */ 573 { 0xA, 0x33, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 574 { 0xA, 0x47, 0x36, 0x00, 0x09 }, /* 350 500 3.1 */ 575 { 0xC, 0x64, 0x34, 0x00, 0x0B }, /* 350 700 6.0 */ 576 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 350 900 8.2 */ 577 { 0xA, 0x46, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 578 { 0xC, 0x64, 0x38, 0x00, 0x07 }, /* 500 700 2.9 */ 579 { 0x6, 0x7F, 0x32, 0x00, 0x0D }, /* 500 900 5.1 */ 580 { 0xC, 0x61, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */ 581 { 0x6, 0x7F, 0x38, 0x00, 0x07 }, /* 600 900 3.5 */ 582 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 583 }; 584 585 struct icl_mg_phy_ddi_buf_trans { 586 u32 cri_txdeemph_override_11_6; 587 u32 cri_txdeemph_override_5_0; 588 u32 cri_txdeemph_override_17_12; 589 }; 590 591 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_rbr_hbr[] = { 592 /* Voltage swing pre-emphasis */ 593 { 0x18, 0x00, 0x00 }, /* 0 0 */ 594 { 0x1D, 0x00, 0x05 }, /* 0 1 */ 595 { 0x24, 0x00, 0x0C }, /* 0 2 */ 596 { 0x2B, 0x00, 0x14 }, /* 0 3 */ 597 { 0x21, 0x00, 0x00 }, /* 1 0 */ 598 { 0x2B, 0x00, 0x08 }, /* 1 1 */ 599 { 0x30, 0x00, 0x0F }, /* 1 2 */ 600 { 0x31, 0x00, 0x03 }, /* 2 0 */ 601 { 0x34, 0x00, 0x0B }, /* 2 1 */ 602 { 0x3F, 0x00, 0x00 }, /* 3 0 */ 603 }; 604 605 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hbr2_hbr3[] = { 606 /* Voltage swing pre-emphasis */ 607 { 0x18, 0x00, 0x00 }, /* 0 0 */ 608 { 0x1D, 0x00, 0x05 }, /* 0 1 */ 609 { 0x24, 0x00, 0x0C }, /* 0 2 */ 610 { 0x2B, 0x00, 0x14 }, /* 0 3 */ 611 { 0x26, 0x00, 0x00 }, /* 1 0 */ 612 { 0x2C, 0x00, 0x07 }, /* 1 1 */ 613 { 0x33, 0x00, 0x0C }, /* 1 2 */ 614 { 0x2E, 0x00, 0x00 }, /* 2 0 */ 615 { 0x36, 0x00, 0x09 }, /* 2 1 */ 616 { 0x3F, 0x00, 0x00 }, /* 3 0 */ 617 }; 618 619 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hdmi[] = { 620 /* HDMI Preset VS Pre-emph */ 621 { 0x1A, 0x0, 0x0 }, /* 1 400mV 0dB */ 622 { 0x20, 0x0, 0x0 }, /* 2 500mV 0dB */ 623 { 0x29, 0x0, 0x0 }, /* 3 650mV 0dB */ 624 { 0x32, 0x0, 0x0 }, /* 4 800mV 0dB */ 625 { 0x3F, 0x0, 0x0 }, /* 5 1000mV 0dB */ 626 { 0x3A, 0x0, 0x5 }, /* 6 Full -1.5 dB */ 627 { 0x39, 0x0, 0x6 }, /* 7 Full -1.8 dB */ 628 { 0x38, 0x0, 0x7 }, /* 8 Full -2 dB */ 629 { 0x37, 0x0, 0x8 }, /* 9 Full -2.5 dB */ 630 { 0x36, 0x0, 0x9 }, /* 10 Full -3 dB */ 631 }; 632 633 struct tgl_dkl_phy_ddi_buf_trans { 634 u32 dkl_vswing_control; 635 u32 dkl_preshoot_control; 636 u32 dkl_de_emphasis_control; 637 }; 638 639 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans[] = { 640 /* VS pre-emp Non-trans mV Pre-emph dB */ 641 { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */ 642 { 0x5, 0x0, 0x05 }, /* 0 1 400mV 3.5 dB */ 643 { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB */ 644 { 0x0, 0x0, 0x18 }, /* 0 3 400mV 9.5 dB */ 645 { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */ 646 { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 dB */ 647 { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */ 648 { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */ 649 { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */ 650 { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */ 651 }; 652 653 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans_hbr2[] = { 654 /* VS pre-emp Non-trans mV Pre-emph dB */ 655 { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */ 656 { 0x5, 0x0, 0x05 }, /* 0 1 400mV 3.5 dB */ 657 { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB */ 658 { 0x0, 0x0, 0x19 }, /* 0 3 400mV 9.5 dB */ 659 { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */ 660 { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 dB */ 661 { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */ 662 { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */ 663 { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */ 664 { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */ 665 }; 666 667 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_hdmi_ddi_trans[] = { 668 /* HDMI Preset VS Pre-emph */ 669 { 0x7, 0x0, 0x0 }, /* 1 400mV 0dB */ 670 { 0x6, 0x0, 0x0 }, /* 2 500mV 0dB */ 671 { 0x4, 0x0, 0x0 }, /* 3 650mV 0dB */ 672 { 0x2, 0x0, 0x0 }, /* 4 800mV 0dB */ 673 { 0x0, 0x0, 0x0 }, /* 5 1000mV 0dB */ 674 { 0x0, 0x0, 0x5 }, /* 6 Full -1.5 dB */ 675 { 0x0, 0x0, 0x6 }, /* 7 Full -1.8 dB */ 676 { 0x0, 0x0, 0x7 }, /* 8 Full -2 dB */ 677 { 0x0, 0x0, 0x8 }, /* 9 Full -2.5 dB */ 678 { 0x0, 0x0, 0xA }, /* 10 Full -3 dB */ 679 }; 680 681 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr[] = { 682 /* NT mV Trans mV db */ 683 { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 684 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 685 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 686 { 0x6, 0x7D, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 687 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 688 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 689 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 690 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 691 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 692 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 693 }; 694 695 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = { 696 /* NT mV Trans mV db */ 697 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 698 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 699 { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 700 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 701 { 0xA, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 702 { 0xC, 0x63, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 703 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 704 { 0xC, 0x61, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 705 { 0x6, 0x7B, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 706 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 707 }; 708 709 static const struct cnl_ddi_buf_trans tgl_uy_combo_phy_ddi_translations_dp_hbr2[] = { 710 /* NT mV Trans mV db */ 711 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 712 { 0xA, 0x4F, 0x36, 0x00, 0x09 }, /* 350 500 3.1 */ 713 { 0xC, 0x60, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ 714 { 0xC, 0x7F, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ 715 { 0xC, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 716 { 0xC, 0x6F, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 717 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 500 900 5.1 */ 718 { 0x6, 0x60, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 719 { 0x6, 0x7F, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ 720 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 721 }; 722 723 /* 724 * Cloned the HOBL entry to comply with the voltage and pre-emphasis entries 725 * that DisplayPort specification requires 726 */ 727 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = { 728 /* VS pre-emp */ 729 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 0 */ 730 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 1 */ 731 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 2 */ 732 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 3 */ 733 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1 0 */ 734 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1 1 */ 735 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1 2 */ 736 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 2 0 */ 737 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 2 1 */ 738 }; 739 740 static bool is_hobl_buf_trans(const struct cnl_ddi_buf_trans *table) 741 { 742 return table == tgl_combo_phy_ddi_translations_edp_hbr2_hobl; 743 } 744 745 static const struct ddi_buf_trans * 746 bdw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) 747 { 748 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 749 750 if (dev_priv->vbt.edp.low_vswing) { 751 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp); 752 return bdw_ddi_translations_edp; 753 } else { 754 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 755 return bdw_ddi_translations_dp; 756 } 757 } 758 759 static const struct ddi_buf_trans * 760 skl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) 761 { 762 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 763 764 if (IS_SKL_ULX(dev_priv)) { 765 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); 766 return skl_y_ddi_translations_dp; 767 } else if (IS_SKL_ULT(dev_priv)) { 768 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); 769 return skl_u_ddi_translations_dp; 770 } else { 771 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); 772 return skl_ddi_translations_dp; 773 } 774 } 775 776 static const struct ddi_buf_trans * 777 kbl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) 778 { 779 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 780 781 if (IS_KBL_ULX(dev_priv) || 782 IS_CFL_ULX(dev_priv) || 783 IS_CML_ULX(dev_priv)) { 784 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp); 785 return kbl_y_ddi_translations_dp; 786 } else if (IS_KBL_ULT(dev_priv) || 787 IS_CFL_ULT(dev_priv) || 788 IS_CML_ULT(dev_priv)) { 789 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp); 790 return kbl_u_ddi_translations_dp; 791 } else { 792 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp); 793 return kbl_ddi_translations_dp; 794 } 795 } 796 797 static const struct ddi_buf_trans * 798 skl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) 799 { 800 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 801 802 if (dev_priv->vbt.edp.low_vswing) { 803 if (IS_SKL_ULX(dev_priv) || 804 IS_KBL_ULX(dev_priv) || 805 IS_CFL_ULX(dev_priv) || 806 IS_CML_ULX(dev_priv)) { 807 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); 808 return skl_y_ddi_translations_edp; 809 } else if (IS_SKL_ULT(dev_priv) || 810 IS_KBL_ULT(dev_priv) || 811 IS_CFL_ULT(dev_priv) || 812 IS_CML_ULT(dev_priv)) { 813 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); 814 return skl_u_ddi_translations_edp; 815 } else { 816 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp); 817 return skl_ddi_translations_edp; 818 } 819 } 820 821 if (IS_KABYLAKE(dev_priv) || 822 IS_COFFEELAKE(dev_priv) || 823 IS_COMETLAKE(dev_priv)) 824 return kbl_get_buf_trans_dp(encoder, n_entries); 825 else 826 return skl_get_buf_trans_dp(encoder, n_entries); 827 } 828 829 static const struct ddi_buf_trans * 830 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) 831 { 832 if (IS_SKL_ULX(dev_priv) || 833 IS_KBL_ULX(dev_priv) || 834 IS_CFL_ULX(dev_priv) || 835 IS_CML_ULX(dev_priv)) { 836 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); 837 return skl_y_ddi_translations_hdmi; 838 } else { 839 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); 840 return skl_ddi_translations_hdmi; 841 } 842 } 843 844 static int skl_buf_trans_num_entries(enum port port, int n_entries) 845 { 846 /* Only DDIA and DDIE can select the 10th register with DP */ 847 if (port == PORT_A || port == PORT_E) 848 return min(n_entries, 10); 849 else 850 return min(n_entries, 9); 851 } 852 853 static const struct ddi_buf_trans * 854 intel_ddi_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) 855 { 856 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 857 858 if (IS_KABYLAKE(dev_priv) || 859 IS_COFFEELAKE(dev_priv) || 860 IS_COMETLAKE(dev_priv)) { 861 const struct ddi_buf_trans *ddi_translations = 862 kbl_get_buf_trans_dp(encoder, n_entries); 863 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); 864 return ddi_translations; 865 } else if (IS_SKYLAKE(dev_priv)) { 866 const struct ddi_buf_trans *ddi_translations = 867 skl_get_buf_trans_dp(encoder, n_entries); 868 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); 869 return ddi_translations; 870 } else if (IS_BROADWELL(dev_priv)) { 871 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 872 return bdw_ddi_translations_dp; 873 } else if (IS_HASWELL(dev_priv)) { 874 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 875 return hsw_ddi_translations_dp; 876 } 877 878 *n_entries = 0; 879 return NULL; 880 } 881 882 static const struct ddi_buf_trans * 883 intel_ddi_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) 884 { 885 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 886 887 if (IS_GEN9_BC(dev_priv)) { 888 const struct ddi_buf_trans *ddi_translations = 889 skl_get_buf_trans_edp(encoder, n_entries); 890 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); 891 return ddi_translations; 892 } else if (IS_BROADWELL(dev_priv)) { 893 return bdw_get_buf_trans_edp(encoder, n_entries); 894 } else if (IS_HASWELL(dev_priv)) { 895 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 896 return hsw_ddi_translations_dp; 897 } 898 899 *n_entries = 0; 900 return NULL; 901 } 902 903 static const struct ddi_buf_trans * 904 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, 905 int *n_entries) 906 { 907 if (IS_BROADWELL(dev_priv)) { 908 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi); 909 return bdw_ddi_translations_fdi; 910 } else if (IS_HASWELL(dev_priv)) { 911 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi); 912 return hsw_ddi_translations_fdi; 913 } 914 915 *n_entries = 0; 916 return NULL; 917 } 918 919 static const struct ddi_buf_trans * 920 intel_ddi_get_buf_trans_hdmi(struct intel_encoder *encoder, 921 int *n_entries) 922 { 923 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 924 925 if (IS_GEN9_BC(dev_priv)) { 926 return skl_get_buf_trans_hdmi(dev_priv, n_entries); 927 } else if (IS_BROADWELL(dev_priv)) { 928 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 929 return bdw_ddi_translations_hdmi; 930 } else if (IS_HASWELL(dev_priv)) { 931 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); 932 return hsw_ddi_translations_hdmi; 933 } 934 935 *n_entries = 0; 936 return NULL; 937 } 938 939 static const struct bxt_ddi_buf_trans * 940 bxt_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) 941 { 942 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); 943 return bxt_ddi_translations_dp; 944 } 945 946 static const struct bxt_ddi_buf_trans * 947 bxt_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) 948 { 949 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 950 951 if (dev_priv->vbt.edp.low_vswing) { 952 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp); 953 return bxt_ddi_translations_edp; 954 } 955 956 return bxt_get_buf_trans_dp(encoder, n_entries); 957 } 958 959 static const struct bxt_ddi_buf_trans * 960 bxt_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries) 961 { 962 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); 963 return bxt_ddi_translations_hdmi; 964 } 965 966 static const struct cnl_ddi_buf_trans * 967 cnl_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries) 968 { 969 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 970 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 971 972 if (voltage == VOLTAGE_INFO_0_85V) { 973 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V); 974 return cnl_ddi_translations_hdmi_0_85V; 975 } else if (voltage == VOLTAGE_INFO_0_95V) { 976 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V); 977 return cnl_ddi_translations_hdmi_0_95V; 978 } else if (voltage == VOLTAGE_INFO_1_05V) { 979 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V); 980 return cnl_ddi_translations_hdmi_1_05V; 981 } else { 982 *n_entries = 1; /* shut up gcc */ 983 MISSING_CASE(voltage); 984 } 985 return NULL; 986 } 987 988 static const struct cnl_ddi_buf_trans * 989 cnl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) 990 { 991 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 992 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 993 994 if (voltage == VOLTAGE_INFO_0_85V) { 995 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V); 996 return cnl_ddi_translations_dp_0_85V; 997 } else if (voltage == VOLTAGE_INFO_0_95V) { 998 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V); 999 return cnl_ddi_translations_dp_0_95V; 1000 } else if (voltage == VOLTAGE_INFO_1_05V) { 1001 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V); 1002 return cnl_ddi_translations_dp_1_05V; 1003 } else { 1004 *n_entries = 1; /* shut up gcc */ 1005 MISSING_CASE(voltage); 1006 } 1007 return NULL; 1008 } 1009 1010 static const struct cnl_ddi_buf_trans * 1011 cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) 1012 { 1013 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1014 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 1015 1016 if (dev_priv->vbt.edp.low_vswing) { 1017 if (voltage == VOLTAGE_INFO_0_85V) { 1018 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V); 1019 return cnl_ddi_translations_edp_0_85V; 1020 } else if (voltage == VOLTAGE_INFO_0_95V) { 1021 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V); 1022 return cnl_ddi_translations_edp_0_95V; 1023 } else if (voltage == VOLTAGE_INFO_1_05V) { 1024 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V); 1025 return cnl_ddi_translations_edp_1_05V; 1026 } else { 1027 *n_entries = 1; /* shut up gcc */ 1028 MISSING_CASE(voltage); 1029 } 1030 return NULL; 1031 } else { 1032 return cnl_get_buf_trans_dp(encoder, n_entries); 1033 } 1034 } 1035 1036 static const struct cnl_ddi_buf_trans * 1037 icl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, 1038 const struct intel_crtc_state *crtc_state, 1039 int *n_entries) 1040 { 1041 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); 1042 return icl_combo_phy_ddi_translations_hdmi; 1043 } 1044 1045 static const struct cnl_ddi_buf_trans * 1046 icl_get_combo_buf_trans_dp(struct intel_encoder *encoder, 1047 const struct intel_crtc_state *crtc_state, 1048 int *n_entries) 1049 { 1050 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2); 1051 return icl_combo_phy_ddi_translations_dp_hbr2; 1052 } 1053 1054 static const struct cnl_ddi_buf_trans * 1055 icl_get_combo_buf_trans_edp(struct intel_encoder *encoder, 1056 const struct intel_crtc_state *crtc_state, 1057 int *n_entries) 1058 { 1059 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1060 1061 if (crtc_state->port_clock > 540000) { 1062 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3); 1063 return icl_combo_phy_ddi_translations_edp_hbr3; 1064 } else if (dev_priv->vbt.edp.low_vswing) { 1065 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2); 1066 return icl_combo_phy_ddi_translations_edp_hbr2; 1067 } 1068 1069 return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1070 } 1071 1072 static const struct cnl_ddi_buf_trans * 1073 icl_get_combo_buf_trans(struct intel_encoder *encoder, 1074 const struct intel_crtc_state *crtc_state, 1075 int *n_entries) 1076 { 1077 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1078 return icl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); 1079 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1080 return icl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); 1081 else 1082 return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1083 } 1084 1085 static const struct icl_mg_phy_ddi_buf_trans * 1086 icl_get_mg_buf_trans_hdmi(struct intel_encoder *encoder, 1087 const struct intel_crtc_state *crtc_state, 1088 int *n_entries) 1089 { 1090 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hdmi); 1091 return icl_mg_phy_ddi_translations_hdmi; 1092 } 1093 1094 static const struct icl_mg_phy_ddi_buf_trans * 1095 icl_get_mg_buf_trans_dp(struct intel_encoder *encoder, 1096 const struct intel_crtc_state *crtc_state, 1097 int *n_entries) 1098 { 1099 if (crtc_state->port_clock > 270000) { 1100 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hbr2_hbr3); 1101 return icl_mg_phy_ddi_translations_hbr2_hbr3; 1102 } else { 1103 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr); 1104 return icl_mg_phy_ddi_translations_rbr_hbr; 1105 } 1106 } 1107 1108 static const struct icl_mg_phy_ddi_buf_trans * 1109 icl_get_mg_buf_trans(struct intel_encoder *encoder, 1110 const struct intel_crtc_state *crtc_state, 1111 int *n_entries) 1112 { 1113 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1114 return icl_get_mg_buf_trans_hdmi(encoder, crtc_state, n_entries); 1115 else 1116 return icl_get_mg_buf_trans_dp(encoder, crtc_state, n_entries); 1117 } 1118 1119 static const struct cnl_ddi_buf_trans * 1120 ehl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, 1121 const struct intel_crtc_state *crtc_state, 1122 int *n_entries) 1123 { 1124 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); 1125 return icl_combo_phy_ddi_translations_hdmi; 1126 } 1127 1128 static const struct cnl_ddi_buf_trans * 1129 ehl_get_combo_buf_trans_dp(struct intel_encoder *encoder, 1130 const struct intel_crtc_state *crtc_state, 1131 int *n_entries) 1132 { 1133 *n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_dp); 1134 return ehl_combo_phy_ddi_translations_dp; 1135 } 1136 1137 static const struct cnl_ddi_buf_trans * 1138 ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder, 1139 const struct intel_crtc_state *crtc_state, 1140 int *n_entries) 1141 { 1142 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1143 1144 if (dev_priv->vbt.edp.low_vswing) { 1145 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2); 1146 return icl_combo_phy_ddi_translations_edp_hbr2; 1147 } 1148 1149 return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1150 } 1151 1152 static const struct cnl_ddi_buf_trans * 1153 ehl_get_combo_buf_trans(struct intel_encoder *encoder, 1154 const struct intel_crtc_state *crtc_state, 1155 int *n_entries) 1156 { 1157 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1158 return ehl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); 1159 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1160 return ehl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); 1161 else 1162 return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1163 } 1164 1165 static const struct cnl_ddi_buf_trans * 1166 tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, 1167 const struct intel_crtc_state *crtc_state, 1168 int *n_entries) 1169 { 1170 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); 1171 return icl_combo_phy_ddi_translations_hdmi; 1172 } 1173 1174 static const struct cnl_ddi_buf_trans * 1175 tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, 1176 const struct intel_crtc_state *crtc_state, 1177 int *n_entries) 1178 { 1179 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1180 1181 if (crtc_state->port_clock > 270000) { 1182 if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) { 1183 *n_entries = ARRAY_SIZE(tgl_uy_combo_phy_ddi_translations_dp_hbr2); 1184 return tgl_uy_combo_phy_ddi_translations_dp_hbr2; 1185 } else { 1186 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2); 1187 return tgl_combo_phy_ddi_translations_dp_hbr2; 1188 } 1189 } else { 1190 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr); 1191 return tgl_combo_phy_ddi_translations_dp_hbr; 1192 } 1193 } 1194 1195 static const struct cnl_ddi_buf_trans * 1196 tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder, 1197 const struct intel_crtc_state *crtc_state, 1198 int *n_entries) 1199 { 1200 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1201 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1202 1203 if (crtc_state->port_clock > 540000) { 1204 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3); 1205 return icl_combo_phy_ddi_translations_edp_hbr3; 1206 } else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) { 1207 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl); 1208 return tgl_combo_phy_ddi_translations_edp_hbr2_hobl; 1209 } else if (dev_priv->vbt.edp.low_vswing) { 1210 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2); 1211 return icl_combo_phy_ddi_translations_edp_hbr2; 1212 } 1213 1214 return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1215 } 1216 1217 static const struct cnl_ddi_buf_trans * 1218 tgl_get_combo_buf_trans(struct intel_encoder *encoder, 1219 const struct intel_crtc_state *crtc_state, 1220 int *n_entries) 1221 { 1222 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1223 return tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); 1224 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1225 return tgl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); 1226 else 1227 return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1228 } 1229 1230 static const struct tgl_dkl_phy_ddi_buf_trans * 1231 tgl_get_dkl_buf_trans_hdmi(struct intel_encoder *encoder, 1232 const struct intel_crtc_state *crtc_state, 1233 int *n_entries) 1234 { 1235 *n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans); 1236 return tgl_dkl_phy_hdmi_ddi_trans; 1237 } 1238 1239 static const struct tgl_dkl_phy_ddi_buf_trans * 1240 tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder, 1241 const struct intel_crtc_state *crtc_state, 1242 int *n_entries) 1243 { 1244 if (crtc_state->port_clock > 270000) { 1245 *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans_hbr2); 1246 return tgl_dkl_phy_dp_ddi_trans_hbr2; 1247 } else { 1248 *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans); 1249 return tgl_dkl_phy_dp_ddi_trans; 1250 } 1251 } 1252 1253 static const struct tgl_dkl_phy_ddi_buf_trans * 1254 tgl_get_dkl_buf_trans(struct intel_encoder *encoder, 1255 const struct intel_crtc_state *crtc_state, 1256 int *n_entries) 1257 { 1258 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1259 return tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, n_entries); 1260 else 1261 return tgl_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries); 1262 } 1263 1264 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 1265 const struct intel_crtc_state *crtc_state) 1266 { 1267 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1268 int n_entries, level, default_entry; 1269 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1270 1271 if (INTEL_GEN(dev_priv) >= 12) { 1272 if (intel_phy_is_combo(dev_priv, phy)) 1273 tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries); 1274 else 1275 tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, &n_entries); 1276 default_entry = n_entries - 1; 1277 } else if (INTEL_GEN(dev_priv) == 11) { 1278 if (intel_phy_is_combo(dev_priv, phy)) 1279 icl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries); 1280 else 1281 icl_get_mg_buf_trans_hdmi(encoder, crtc_state, &n_entries); 1282 default_entry = n_entries - 1; 1283 } else if (IS_CANNONLAKE(dev_priv)) { 1284 cnl_get_buf_trans_hdmi(encoder, &n_entries); 1285 default_entry = n_entries - 1; 1286 } else if (IS_GEN9_LP(dev_priv)) { 1287 bxt_get_buf_trans_hdmi(encoder, &n_entries); 1288 default_entry = n_entries - 1; 1289 } else if (IS_GEN9_BC(dev_priv)) { 1290 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); 1291 default_entry = 8; 1292 } else if (IS_BROADWELL(dev_priv)) { 1293 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); 1294 default_entry = 7; 1295 } else if (IS_HASWELL(dev_priv)) { 1296 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); 1297 default_entry = 6; 1298 } else { 1299 drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n"); 1300 return 0; 1301 } 1302 1303 if (drm_WARN_ON_ONCE(&dev_priv->drm, n_entries == 0)) 1304 return 0; 1305 1306 level = intel_bios_hdmi_level_shift(encoder); 1307 if (level < 0) 1308 level = default_entry; 1309 1310 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 1311 level = n_entries - 1; 1312 1313 return level; 1314 } 1315 1316 /* 1317 * Starting with Haswell, DDI port buffers must be programmed with correct 1318 * values in advance. This function programs the correct values for 1319 * DP/eDP/FDI use cases. 1320 */ 1321 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 1322 const struct intel_crtc_state *crtc_state) 1323 { 1324 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1325 u32 iboost_bit = 0; 1326 int i, n_entries; 1327 enum port port = encoder->port; 1328 const struct ddi_buf_trans *ddi_translations; 1329 1330 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) 1331 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv, 1332 &n_entries); 1333 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1334 ddi_translations = intel_ddi_get_buf_trans_edp(encoder, 1335 &n_entries); 1336 else 1337 ddi_translations = intel_ddi_get_buf_trans_dp(encoder, 1338 &n_entries); 1339 1340 /* If we're boosting the current, set bit 31 of trans1 */ 1341 if (IS_GEN9_BC(dev_priv) && intel_bios_dp_boost_level(encoder)) 1342 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 1343 1344 for (i = 0; i < n_entries; i++) { 1345 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 1346 ddi_translations[i].trans1 | iboost_bit); 1347 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 1348 ddi_translations[i].trans2); 1349 } 1350 } 1351 1352 /* 1353 * Starting with Haswell, DDI port buffers must be programmed with correct 1354 * values in advance. This function programs the correct values for 1355 * HDMI/DVI use cases. 1356 */ 1357 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 1358 int level) 1359 { 1360 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1361 u32 iboost_bit = 0; 1362 int n_entries; 1363 enum port port = encoder->port; 1364 const struct ddi_buf_trans *ddi_translations; 1365 1366 ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); 1367 1368 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 1369 return; 1370 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 1371 level = n_entries - 1; 1372 1373 /* If we're boosting the current, set bit 31 of trans1 */ 1374 if (IS_GEN9_BC(dev_priv) && intel_bios_hdmi_boost_level(encoder)) 1375 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 1376 1377 /* Entry 9 is for HDMI: */ 1378 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 1379 ddi_translations[level].trans1 | iboost_bit); 1380 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 1381 ddi_translations[level].trans2); 1382 } 1383 1384 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 1385 enum port port) 1386 { 1387 if (IS_BROXTON(dev_priv)) { 1388 udelay(16); 1389 return; 1390 } 1391 1392 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 1393 DDI_BUF_IS_IDLE), 8)) 1394 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", 1395 port_name(port)); 1396 } 1397 1398 static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, 1399 enum port port) 1400 { 1401 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ 1402 if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) { 1403 usleep_range(518, 1000); 1404 return; 1405 } 1406 1407 if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 1408 DDI_BUF_IS_IDLE), 500)) 1409 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", 1410 port_name(port)); 1411 } 1412 1413 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 1414 { 1415 switch (pll->info->id) { 1416 case DPLL_ID_WRPLL1: 1417 return PORT_CLK_SEL_WRPLL1; 1418 case DPLL_ID_WRPLL2: 1419 return PORT_CLK_SEL_WRPLL2; 1420 case DPLL_ID_SPLL: 1421 return PORT_CLK_SEL_SPLL; 1422 case DPLL_ID_LCPLL_810: 1423 return PORT_CLK_SEL_LCPLL_810; 1424 case DPLL_ID_LCPLL_1350: 1425 return PORT_CLK_SEL_LCPLL_1350; 1426 case DPLL_ID_LCPLL_2700: 1427 return PORT_CLK_SEL_LCPLL_2700; 1428 default: 1429 MISSING_CASE(pll->info->id); 1430 return PORT_CLK_SEL_NONE; 1431 } 1432 } 1433 1434 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 1435 const struct intel_crtc_state *crtc_state) 1436 { 1437 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1438 int clock = crtc_state->port_clock; 1439 const enum intel_dpll_id id = pll->info->id; 1440 1441 switch (id) { 1442 default: 1443 /* 1444 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 1445 * here, so do warn if this get passed in 1446 */ 1447 MISSING_CASE(id); 1448 return DDI_CLK_SEL_NONE; 1449 case DPLL_ID_ICL_TBTPLL: 1450 switch (clock) { 1451 case 162000: 1452 return DDI_CLK_SEL_TBT_162; 1453 case 270000: 1454 return DDI_CLK_SEL_TBT_270; 1455 case 540000: 1456 return DDI_CLK_SEL_TBT_540; 1457 case 810000: 1458 return DDI_CLK_SEL_TBT_810; 1459 default: 1460 MISSING_CASE(clock); 1461 return DDI_CLK_SEL_NONE; 1462 } 1463 case DPLL_ID_ICL_MGPLL1: 1464 case DPLL_ID_ICL_MGPLL2: 1465 case DPLL_ID_ICL_MGPLL3: 1466 case DPLL_ID_ICL_MGPLL4: 1467 case DPLL_ID_TGL_MGPLL5: 1468 case DPLL_ID_TGL_MGPLL6: 1469 return DDI_CLK_SEL_MG; 1470 } 1471 } 1472 1473 /* Starting with Haswell, different DDI ports can work in FDI mode for 1474 * connection to the PCH-located connectors. For this, it is necessary to train 1475 * both the DDI port and PCH receiver for the desired DDI buffer settings. 1476 * 1477 * The recommended port to work in FDI mode is DDI E, which we use here. Also, 1478 * please note that when FDI mode is active on DDI E, it shares 2 lines with 1479 * DDI A (which is used for eDP) 1480 */ 1481 1482 void hsw_fdi_link_train(struct intel_encoder *encoder, 1483 const struct intel_crtc_state *crtc_state) 1484 { 1485 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1486 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1487 u32 temp, i, rx_ctl_val, ddi_pll_sel; 1488 1489 intel_prepare_dp_ddi_buffers(encoder, crtc_state); 1490 1491 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the 1492 * mode set "sequence for CRT port" document: 1493 * - TP1 to TP2 time with the default value 1494 * - FDI delay to 90h 1495 * 1496 * WaFDIAutoLinkSetTimingOverrride:hsw 1497 */ 1498 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), 1499 FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 1500 1501 /* Enable the PCH Receiver FDI PLL */ 1502 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | 1503 FDI_RX_PLL_ENABLE | 1504 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); 1505 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 1506 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); 1507 udelay(220); 1508 1509 /* Switch from Rawclk to PCDclk */ 1510 rx_ctl_val |= FDI_PCDCLK; 1511 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 1512 1513 /* Configure Port Clock Select */ 1514 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll); 1515 intel_de_write(dev_priv, PORT_CLK_SEL(PORT_E), ddi_pll_sel); 1516 drm_WARN_ON(&dev_priv->drm, ddi_pll_sel != PORT_CLK_SEL_SPLL); 1517 1518 /* Start the training iterating through available voltages and emphasis, 1519 * testing each value twice. */ 1520 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { 1521 /* Configure DP_TP_CTL with auto-training */ 1522 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), 1523 DP_TP_CTL_FDI_AUTOTRAIN | 1524 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 1525 DP_TP_CTL_LINK_TRAIN_PAT1 | 1526 DP_TP_CTL_ENABLE); 1527 1528 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. 1529 * DDI E does not support port reversal, the functionality is 1530 * achieved on the PCH side in FDI_RX_CTL, so no need to set the 1531 * port reversal bit */ 1532 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), 1533 DDI_BUF_CTL_ENABLE | ((crtc_state->fdi_lanes - 1) << 1) | DDI_BUF_TRANS_SELECT(i / 2)); 1534 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E)); 1535 1536 udelay(600); 1537 1538 /* Program PCH FDI Receiver TU */ 1539 intel_de_write(dev_priv, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); 1540 1541 /* Enable PCH FDI Receiver with auto-training */ 1542 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; 1543 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 1544 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); 1545 1546 /* Wait for FDI receiver lane calibration */ 1547 udelay(30); 1548 1549 /* Unset FDI_RX_MISC pwrdn lanes */ 1550 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1551 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 1552 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp); 1553 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1554 1555 /* Wait for FDI auto training time */ 1556 udelay(5); 1557 1558 temp = intel_de_read(dev_priv, DP_TP_STATUS(PORT_E)); 1559 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { 1560 drm_dbg_kms(&dev_priv->drm, 1561 "FDI link training done on step %d\n", i); 1562 break; 1563 } 1564 1565 /* 1566 * Leave things enabled even if we failed to train FDI. 1567 * Results in less fireworks from the state checker. 1568 */ 1569 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) { 1570 drm_err(&dev_priv->drm, "FDI link training failed!\n"); 1571 break; 1572 } 1573 1574 rx_ctl_val &= ~FDI_RX_ENABLE; 1575 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 1576 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); 1577 1578 temp = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E)); 1579 temp &= ~DDI_BUF_CTL_ENABLE; 1580 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), temp); 1581 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E)); 1582 1583 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ 1584 temp = intel_de_read(dev_priv, DP_TP_CTL(PORT_E)); 1585 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 1586 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 1587 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp); 1588 intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E)); 1589 1590 intel_wait_ddi_buf_idle(dev_priv, PORT_E); 1591 1592 /* Reset FDI_RX_MISC pwrdn lanes */ 1593 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1594 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 1595 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 1596 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp); 1597 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1598 } 1599 1600 /* Enable normal pixel sending for FDI */ 1601 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), 1602 DP_TP_CTL_FDI_AUTOTRAIN | 1603 DP_TP_CTL_LINK_TRAIN_NORMAL | 1604 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 1605 DP_TP_CTL_ENABLE); 1606 } 1607 1608 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 1609 const struct intel_crtc_state *crtc_state) 1610 { 1611 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1612 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1613 1614 intel_dp->DP = dig_port->saved_port_bits | 1615 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); 1616 intel_dp->DP |= DDI_PORT_WIDTH(crtc_state->lane_count); 1617 } 1618 1619 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 1620 enum port port) 1621 { 1622 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 1623 1624 switch (val) { 1625 case DDI_CLK_SEL_NONE: 1626 return 0; 1627 case DDI_CLK_SEL_TBT_162: 1628 return 162000; 1629 case DDI_CLK_SEL_TBT_270: 1630 return 270000; 1631 case DDI_CLK_SEL_TBT_540: 1632 return 540000; 1633 case DDI_CLK_SEL_TBT_810: 1634 return 810000; 1635 default: 1636 MISSING_CASE(val); 1637 return 0; 1638 } 1639 } 1640 1641 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 1642 { 1643 int dotclock; 1644 1645 if (pipe_config->has_pch_encoder) 1646 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1647 &pipe_config->fdi_m_n); 1648 else if (intel_crtc_has_dp_encoder(pipe_config)) 1649 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1650 &pipe_config->dp_m_n); 1651 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) 1652 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp; 1653 else 1654 dotclock = pipe_config->port_clock; 1655 1656 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 1657 !intel_crtc_has_dp_encoder(pipe_config)) 1658 dotclock *= 2; 1659 1660 if (pipe_config->pixel_multiplier) 1661 dotclock /= pipe_config->pixel_multiplier; 1662 1663 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 1664 } 1665 1666 static void intel_ddi_clock_get(struct intel_encoder *encoder, 1667 struct intel_crtc_state *pipe_config) 1668 { 1669 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1670 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1671 1672 if (intel_phy_is_tc(dev_priv, phy) && 1673 intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll) == 1674 DPLL_ID_ICL_TBTPLL) 1675 pipe_config->port_clock = icl_calc_tbt_pll_link(dev_priv, 1676 encoder->port); 1677 else 1678 pipe_config->port_clock = 1679 intel_dpll_get_freq(dev_priv, pipe_config->shared_dpll); 1680 1681 ddi_dotclock_get(pipe_config); 1682 } 1683 1684 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 1685 const struct drm_connector_state *conn_state) 1686 { 1687 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1688 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1689 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1690 u32 temp; 1691 1692 if (!intel_crtc_has_dp_encoder(crtc_state)) 1693 return; 1694 1695 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 1696 1697 temp = DP_MSA_MISC_SYNC_CLOCK; 1698 1699 switch (crtc_state->pipe_bpp) { 1700 case 18: 1701 temp |= DP_MSA_MISC_6_BPC; 1702 break; 1703 case 24: 1704 temp |= DP_MSA_MISC_8_BPC; 1705 break; 1706 case 30: 1707 temp |= DP_MSA_MISC_10_BPC; 1708 break; 1709 case 36: 1710 temp |= DP_MSA_MISC_12_BPC; 1711 break; 1712 default: 1713 MISSING_CASE(crtc_state->pipe_bpp); 1714 break; 1715 } 1716 1717 /* nonsense combination */ 1718 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 1719 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 1720 1721 if (crtc_state->limited_color_range) 1722 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 1723 1724 /* 1725 * As per DP 1.2 spec section 2.3.4.3 while sending 1726 * YCBCR 444 signals we should program MSA MISC1/0 fields with 1727 * colorspace information. 1728 */ 1729 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 1730 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 1731 1732 /* 1733 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 1734 * of Color Encoding Format and Content Color Gamut] while sending 1735 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 1736 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 1737 */ 1738 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 1739 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 1740 1741 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp); 1742 } 1743 1744 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 1745 { 1746 if (master_transcoder == TRANSCODER_EDP) 1747 return 0; 1748 else 1749 return master_transcoder + 1; 1750 } 1751 1752 /* 1753 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 1754 * 1755 * Only intended to be used by intel_ddi_enable_transcoder_func() and 1756 * intel_ddi_config_transcoder_func(). 1757 */ 1758 static u32 1759 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 1760 const struct intel_crtc_state *crtc_state) 1761 { 1762 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1763 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1764 enum pipe pipe = crtc->pipe; 1765 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1766 enum port port = encoder->port; 1767 u32 temp; 1768 1769 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 1770 temp = TRANS_DDI_FUNC_ENABLE; 1771 if (INTEL_GEN(dev_priv) >= 12) 1772 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 1773 else 1774 temp |= TRANS_DDI_SELECT_PORT(port); 1775 1776 switch (crtc_state->pipe_bpp) { 1777 case 18: 1778 temp |= TRANS_DDI_BPC_6; 1779 break; 1780 case 24: 1781 temp |= TRANS_DDI_BPC_8; 1782 break; 1783 case 30: 1784 temp |= TRANS_DDI_BPC_10; 1785 break; 1786 case 36: 1787 temp |= TRANS_DDI_BPC_12; 1788 break; 1789 default: 1790 BUG(); 1791 } 1792 1793 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 1794 temp |= TRANS_DDI_PVSYNC; 1795 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 1796 temp |= TRANS_DDI_PHSYNC; 1797 1798 if (cpu_transcoder == TRANSCODER_EDP) { 1799 switch (pipe) { 1800 case PIPE_A: 1801 /* On Haswell, can only use the always-on power well for 1802 * eDP when not using the panel fitter, and when not 1803 * using motion blur mitigation (which we don't 1804 * support). */ 1805 if (crtc_state->pch_pfit.force_thru) 1806 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 1807 else 1808 temp |= TRANS_DDI_EDP_INPUT_A_ON; 1809 break; 1810 case PIPE_B: 1811 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 1812 break; 1813 case PIPE_C: 1814 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 1815 break; 1816 default: 1817 BUG(); 1818 break; 1819 } 1820 } 1821 1822 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1823 if (crtc_state->has_hdmi_sink) 1824 temp |= TRANS_DDI_MODE_SELECT_HDMI; 1825 else 1826 temp |= TRANS_DDI_MODE_SELECT_DVI; 1827 1828 if (crtc_state->hdmi_scrambling) 1829 temp |= TRANS_DDI_HDMI_SCRAMBLING; 1830 if (crtc_state->hdmi_high_tmds_clock_ratio) 1831 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 1832 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 1833 temp |= TRANS_DDI_MODE_SELECT_FDI; 1834 temp |= (crtc_state->fdi_lanes - 1) << 1; 1835 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 1836 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 1837 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 1838 1839 if (INTEL_GEN(dev_priv) >= 12) { 1840 enum transcoder master; 1841 1842 master = crtc_state->mst_master_transcoder; 1843 drm_WARN_ON(&dev_priv->drm, 1844 master == INVALID_TRANSCODER); 1845 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 1846 } 1847 } else { 1848 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 1849 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 1850 } 1851 1852 if (IS_GEN_RANGE(dev_priv, 8, 10) && 1853 crtc_state->master_transcoder != INVALID_TRANSCODER) { 1854 u8 master_select = 1855 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 1856 1857 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 1858 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 1859 } 1860 1861 return temp; 1862 } 1863 1864 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 1865 const struct intel_crtc_state *crtc_state) 1866 { 1867 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1868 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1869 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1870 1871 if (INTEL_GEN(dev_priv) >= 11) { 1872 enum transcoder master_transcoder = crtc_state->master_transcoder; 1873 u32 ctl2 = 0; 1874 1875 if (master_transcoder != INVALID_TRANSCODER) { 1876 u8 master_select = 1877 bdw_trans_port_sync_master_select(master_transcoder); 1878 1879 ctl2 |= PORT_SYNC_MODE_ENABLE | 1880 PORT_SYNC_MODE_MASTER_SELECT(master_select); 1881 } 1882 1883 intel_de_write(dev_priv, 1884 TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2); 1885 } 1886 1887 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 1888 intel_ddi_transcoder_func_reg_val_get(encoder, 1889 crtc_state)); 1890 } 1891 1892 /* 1893 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 1894 * bit. 1895 */ 1896 static void 1897 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 1898 const struct intel_crtc_state *crtc_state) 1899 { 1900 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1901 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1902 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1903 u32 ctl; 1904 1905 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 1906 ctl &= ~TRANS_DDI_FUNC_ENABLE; 1907 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 1908 } 1909 1910 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 1911 { 1912 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1913 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1914 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1915 u32 ctl; 1916 1917 if (INTEL_GEN(dev_priv) >= 11) 1918 intel_de_write(dev_priv, 1919 TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0); 1920 1921 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1922 1923 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 1924 1925 ctl &= ~TRANS_DDI_FUNC_ENABLE; 1926 1927 if (IS_GEN_RANGE(dev_priv, 8, 10)) 1928 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 1929 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 1930 1931 if (INTEL_GEN(dev_priv) >= 12) { 1932 if (!intel_dp_mst_is_master_trans(crtc_state)) { 1933 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 1934 TRANS_DDI_MODE_SELECT_MASK); 1935 } 1936 } else { 1937 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 1938 } 1939 1940 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 1941 1942 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME && 1943 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1944 drm_dbg_kms(&dev_priv->drm, 1945 "Quirk Increase DDI disabled time\n"); 1946 /* Quirk time at 100ms for reliable operation */ 1947 msleep(100); 1948 } 1949 } 1950 1951 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder, 1952 enum transcoder cpu_transcoder, 1953 bool enable) 1954 { 1955 struct drm_device *dev = intel_encoder->base.dev; 1956 struct drm_i915_private *dev_priv = to_i915(dev); 1957 intel_wakeref_t wakeref; 1958 int ret = 0; 1959 u32 tmp; 1960 1961 wakeref = intel_display_power_get_if_enabled(dev_priv, 1962 intel_encoder->power_domain); 1963 if (drm_WARN_ON(dev, !wakeref)) 1964 return -ENXIO; 1965 1966 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1967 if (enable) 1968 tmp |= TRANS_DDI_HDCP_SIGNALLING; 1969 else 1970 tmp &= ~TRANS_DDI_HDCP_SIGNALLING; 1971 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp); 1972 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 1973 return ret; 1974 } 1975 1976 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 1977 { 1978 struct drm_device *dev = intel_connector->base.dev; 1979 struct drm_i915_private *dev_priv = to_i915(dev); 1980 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 1981 int type = intel_connector->base.connector_type; 1982 enum port port = encoder->port; 1983 enum transcoder cpu_transcoder; 1984 intel_wakeref_t wakeref; 1985 enum pipe pipe = 0; 1986 u32 tmp; 1987 bool ret; 1988 1989 wakeref = intel_display_power_get_if_enabled(dev_priv, 1990 encoder->power_domain); 1991 if (!wakeref) 1992 return false; 1993 1994 if (!encoder->get_hw_state(encoder, &pipe)) { 1995 ret = false; 1996 goto out; 1997 } 1998 1999 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 2000 cpu_transcoder = TRANSCODER_EDP; 2001 else 2002 cpu_transcoder = (enum transcoder) pipe; 2003 2004 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 2005 2006 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 2007 case TRANS_DDI_MODE_SELECT_HDMI: 2008 case TRANS_DDI_MODE_SELECT_DVI: 2009 ret = type == DRM_MODE_CONNECTOR_HDMIA; 2010 break; 2011 2012 case TRANS_DDI_MODE_SELECT_DP_SST: 2013 ret = type == DRM_MODE_CONNECTOR_eDP || 2014 type == DRM_MODE_CONNECTOR_DisplayPort; 2015 break; 2016 2017 case TRANS_DDI_MODE_SELECT_DP_MST: 2018 /* if the transcoder is in MST state then 2019 * connector isn't connected */ 2020 ret = false; 2021 break; 2022 2023 case TRANS_DDI_MODE_SELECT_FDI: 2024 ret = type == DRM_MODE_CONNECTOR_VGA; 2025 break; 2026 2027 default: 2028 ret = false; 2029 break; 2030 } 2031 2032 out: 2033 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 2034 2035 return ret; 2036 } 2037 2038 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 2039 u8 *pipe_mask, bool *is_dp_mst) 2040 { 2041 struct drm_device *dev = encoder->base.dev; 2042 struct drm_i915_private *dev_priv = to_i915(dev); 2043 enum port port = encoder->port; 2044 intel_wakeref_t wakeref; 2045 enum pipe p; 2046 u32 tmp; 2047 u8 mst_pipe_mask; 2048 2049 *pipe_mask = 0; 2050 *is_dp_mst = false; 2051 2052 wakeref = intel_display_power_get_if_enabled(dev_priv, 2053 encoder->power_domain); 2054 if (!wakeref) 2055 return; 2056 2057 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2058 if (!(tmp & DDI_BUF_CTL_ENABLE)) 2059 goto out; 2060 2061 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { 2062 tmp = intel_de_read(dev_priv, 2063 TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 2064 2065 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 2066 default: 2067 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 2068 fallthrough; 2069 case TRANS_DDI_EDP_INPUT_A_ON: 2070 case TRANS_DDI_EDP_INPUT_A_ONOFF: 2071 *pipe_mask = BIT(PIPE_A); 2072 break; 2073 case TRANS_DDI_EDP_INPUT_B_ONOFF: 2074 *pipe_mask = BIT(PIPE_B); 2075 break; 2076 case TRANS_DDI_EDP_INPUT_C_ONOFF: 2077 *pipe_mask = BIT(PIPE_C); 2078 break; 2079 } 2080 2081 goto out; 2082 } 2083 2084 mst_pipe_mask = 0; 2085 for_each_pipe(dev_priv, p) { 2086 enum transcoder cpu_transcoder = (enum transcoder)p; 2087 unsigned int port_mask, ddi_select; 2088 intel_wakeref_t trans_wakeref; 2089 2090 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 2091 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 2092 if (!trans_wakeref) 2093 continue; 2094 2095 if (INTEL_GEN(dev_priv) >= 12) { 2096 port_mask = TGL_TRANS_DDI_PORT_MASK; 2097 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 2098 } else { 2099 port_mask = TRANS_DDI_PORT_MASK; 2100 ddi_select = TRANS_DDI_SELECT_PORT(port); 2101 } 2102 2103 tmp = intel_de_read(dev_priv, 2104 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 2105 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 2106 trans_wakeref); 2107 2108 if ((tmp & port_mask) != ddi_select) 2109 continue; 2110 2111 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == 2112 TRANS_DDI_MODE_SELECT_DP_MST) 2113 mst_pipe_mask |= BIT(p); 2114 2115 *pipe_mask |= BIT(p); 2116 } 2117 2118 if (!*pipe_mask) 2119 drm_dbg_kms(&dev_priv->drm, 2120 "No pipe for [ENCODER:%d:%s] found\n", 2121 encoder->base.base.id, encoder->base.name); 2122 2123 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 2124 drm_dbg_kms(&dev_priv->drm, 2125 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 2126 encoder->base.base.id, encoder->base.name, 2127 *pipe_mask); 2128 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 2129 } 2130 2131 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 2132 drm_dbg_kms(&dev_priv->drm, 2133 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", 2134 encoder->base.base.id, encoder->base.name, 2135 *pipe_mask, mst_pipe_mask); 2136 else 2137 *is_dp_mst = mst_pipe_mask; 2138 2139 out: 2140 if (*pipe_mask && IS_GEN9_LP(dev_priv)) { 2141 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 2142 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 2143 BXT_PHY_LANE_POWERDOWN_ACK | 2144 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 2145 drm_err(&dev_priv->drm, 2146 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 2147 encoder->base.base.id, encoder->base.name, tmp); 2148 } 2149 2150 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 2151 } 2152 2153 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 2154 enum pipe *pipe) 2155 { 2156 u8 pipe_mask; 2157 bool is_mst; 2158 2159 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2160 2161 if (is_mst || !pipe_mask) 2162 return false; 2163 2164 *pipe = ffs(pipe_mask) - 1; 2165 2166 return true; 2167 } 2168 2169 static enum intel_display_power_domain 2170 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port) 2171 { 2172 /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with 2173 * DC states enabled at the same time, while for driver initiated AUX 2174 * transfers we need the same AUX IOs to be powered but with DC states 2175 * disabled. Accordingly use the AUX power domain here which leaves DC 2176 * states enabled. 2177 * However, for non-A AUX ports the corresponding non-EDP transcoders 2178 * would have already enabled power well 2 and DC_OFF. This means we can 2179 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a 2180 * specific AUX_IO reference without powering up any extra wells. 2181 * Note that PSR is enabled only on Port A even though this function 2182 * returns the correct domain for other ports too. 2183 */ 2184 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A : 2185 intel_aux_power_domain(dig_port); 2186 } 2187 2188 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 2189 struct intel_crtc_state *crtc_state) 2190 { 2191 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2192 struct intel_digital_port *dig_port; 2193 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2194 2195 /* 2196 * TODO: Add support for MST encoders. Atm, the following should never 2197 * happen since fake-MST encoders don't set their get_power_domains() 2198 * hook. 2199 */ 2200 if (drm_WARN_ON(&dev_priv->drm, 2201 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 2202 return; 2203 2204 dig_port = enc_to_dig_port(encoder); 2205 2206 if (!intel_phy_is_tc(dev_priv, phy) || 2207 dig_port->tc_mode != TC_PORT_TBT_ALT) 2208 intel_display_power_get(dev_priv, 2209 dig_port->ddi_io_power_domain); 2210 2211 /* 2212 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC 2213 * ports. 2214 */ 2215 if (intel_crtc_has_dp_encoder(crtc_state) || 2216 intel_phy_is_tc(dev_priv, phy)) 2217 intel_display_power_get(dev_priv, 2218 intel_ddi_main_link_aux_domain(dig_port)); 2219 2220 /* 2221 * VDSC power is needed when DSC is enabled 2222 */ 2223 if (crtc_state->dsc.compression_enable) 2224 intel_display_power_get(dev_priv, 2225 intel_dsc_power_domain(crtc_state)); 2226 } 2227 2228 void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder, 2229 const struct intel_crtc_state *crtc_state) 2230 { 2231 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2232 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2233 enum port port = encoder->port; 2234 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2235 2236 if (cpu_transcoder != TRANSCODER_EDP) { 2237 if (INTEL_GEN(dev_priv) >= 12) 2238 intel_de_write(dev_priv, 2239 TRANS_CLK_SEL(cpu_transcoder), 2240 TGL_TRANS_CLK_SEL_PORT(port)); 2241 else 2242 intel_de_write(dev_priv, 2243 TRANS_CLK_SEL(cpu_transcoder), 2244 TRANS_CLK_SEL_PORT(port)); 2245 } 2246 } 2247 2248 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state) 2249 { 2250 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2251 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2252 2253 if (cpu_transcoder != TRANSCODER_EDP) { 2254 if (INTEL_GEN(dev_priv) >= 12) 2255 intel_de_write(dev_priv, 2256 TRANS_CLK_SEL(cpu_transcoder), 2257 TGL_TRANS_CLK_SEL_DISABLED); 2258 else 2259 intel_de_write(dev_priv, 2260 TRANS_CLK_SEL(cpu_transcoder), 2261 TRANS_CLK_SEL_DISABLED); 2262 } 2263 } 2264 2265 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 2266 enum port port, u8 iboost) 2267 { 2268 u32 tmp; 2269 2270 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 2271 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 2272 if (iboost) 2273 tmp |= iboost << BALANCE_LEG_SHIFT(port); 2274 else 2275 tmp |= BALANCE_LEG_DISABLE(port); 2276 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 2277 } 2278 2279 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 2280 const struct intel_crtc_state *crtc_state, 2281 int level) 2282 { 2283 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2284 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2285 u8 iboost; 2286 2287 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 2288 iboost = intel_bios_hdmi_boost_level(encoder); 2289 else 2290 iboost = intel_bios_dp_boost_level(encoder); 2291 2292 if (iboost == 0) { 2293 const struct ddi_buf_trans *ddi_translations; 2294 int n_entries; 2295 2296 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 2297 ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); 2298 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 2299 ddi_translations = intel_ddi_get_buf_trans_edp(encoder, &n_entries); 2300 else 2301 ddi_translations = intel_ddi_get_buf_trans_dp(encoder, &n_entries); 2302 2303 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 2304 return; 2305 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 2306 level = n_entries - 1; 2307 2308 iboost = ddi_translations[level].i_boost; 2309 } 2310 2311 /* Make sure that the requested I_boost is valid */ 2312 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 2313 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); 2314 return; 2315 } 2316 2317 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); 2318 2319 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 2320 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 2321 } 2322 2323 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, 2324 const struct intel_crtc_state *crtc_state, 2325 int level) 2326 { 2327 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2328 const struct bxt_ddi_buf_trans *ddi_translations; 2329 enum port port = encoder->port; 2330 int n_entries; 2331 2332 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 2333 ddi_translations = bxt_get_buf_trans_hdmi(encoder, &n_entries); 2334 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 2335 ddi_translations = bxt_get_buf_trans_edp(encoder, &n_entries); 2336 else 2337 ddi_translations = bxt_get_buf_trans_dp(encoder, &n_entries); 2338 2339 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 2340 return; 2341 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 2342 level = n_entries - 1; 2343 2344 bxt_ddi_phy_set_signal_level(dev_priv, port, 2345 ddi_translations[level].margin, 2346 ddi_translations[level].scale, 2347 ddi_translations[level].enable, 2348 ddi_translations[level].deemphasis); 2349 } 2350 2351 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 2352 const struct intel_crtc_state *crtc_state) 2353 { 2354 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2355 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2356 enum port port = encoder->port; 2357 enum phy phy = intel_port_to_phy(dev_priv, port); 2358 int n_entries; 2359 2360 if (INTEL_GEN(dev_priv) >= 12) { 2361 if (intel_phy_is_combo(dev_priv, phy)) 2362 tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries); 2363 else 2364 tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries); 2365 } else if (INTEL_GEN(dev_priv) == 11) { 2366 if (IS_JSL_EHL(dev_priv)) 2367 ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries); 2368 else if (intel_phy_is_combo(dev_priv, phy)) 2369 icl_get_combo_buf_trans(encoder, crtc_state, &n_entries); 2370 else 2371 icl_get_mg_buf_trans(encoder, crtc_state, &n_entries); 2372 } else if (IS_CANNONLAKE(dev_priv)) { 2373 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 2374 cnl_get_buf_trans_edp(encoder, &n_entries); 2375 else 2376 cnl_get_buf_trans_dp(encoder, &n_entries); 2377 } else if (IS_GEN9_LP(dev_priv)) { 2378 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 2379 bxt_get_buf_trans_edp(encoder, &n_entries); 2380 else 2381 bxt_get_buf_trans_dp(encoder, &n_entries); 2382 } else { 2383 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 2384 intel_ddi_get_buf_trans_edp(encoder, &n_entries); 2385 else 2386 intel_ddi_get_buf_trans_dp(encoder, &n_entries); 2387 } 2388 2389 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 2390 n_entries = 1; 2391 if (drm_WARN_ON(&dev_priv->drm, 2392 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 2393 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 2394 2395 return index_to_dp_signal_levels[n_entries - 1] & 2396 DP_TRAIN_VOLTAGE_SWING_MASK; 2397 } 2398 2399 /* 2400 * We assume that the full set of pre-emphasis values can be 2401 * used on all DDI platforms. Should that change we need to 2402 * rethink this code. 2403 */ 2404 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 2405 { 2406 return DP_TRAIN_PRE_EMPH_LEVEL_3; 2407 } 2408 2409 static void cnl_ddi_vswing_program(struct intel_encoder *encoder, 2410 const struct intel_crtc_state *crtc_state, 2411 int level) 2412 { 2413 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2414 const struct cnl_ddi_buf_trans *ddi_translations; 2415 enum port port = encoder->port; 2416 int n_entries, ln; 2417 u32 val; 2418 2419 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 2420 ddi_translations = cnl_get_buf_trans_hdmi(encoder, &n_entries); 2421 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 2422 ddi_translations = cnl_get_buf_trans_edp(encoder, &n_entries); 2423 else 2424 ddi_translations = cnl_get_buf_trans_dp(encoder, &n_entries); 2425 2426 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 2427 return; 2428 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 2429 level = n_entries - 1; 2430 2431 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */ 2432 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 2433 val &= ~SCALING_MODE_SEL_MASK; 2434 val |= SCALING_MODE_SEL(2); 2435 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 2436 2437 /* Program PORT_TX_DW2 */ 2438 val = intel_de_read(dev_priv, CNL_PORT_TX_DW2_LN0(port)); 2439 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 2440 RCOMP_SCALAR_MASK); 2441 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); 2442 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); 2443 /* Rcomp scalar is fixed as 0x98 for every table entry */ 2444 val |= RCOMP_SCALAR(0x98); 2445 intel_de_write(dev_priv, CNL_PORT_TX_DW2_GRP(port), val); 2446 2447 /* Program PORT_TX_DW4 */ 2448 /* We cannot write to GRP. It would overrite individual loadgen */ 2449 for (ln = 0; ln < 4; ln++) { 2450 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port)); 2451 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 2452 CURSOR_COEFF_MASK); 2453 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); 2454 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); 2455 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); 2456 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val); 2457 } 2458 2459 /* Program PORT_TX_DW5 */ 2460 /* All DW5 values are fixed for every table entry */ 2461 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 2462 val &= ~RTERM_SELECT_MASK; 2463 val |= RTERM_SELECT(6); 2464 val |= TAP3_DISABLE; 2465 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 2466 2467 /* Program PORT_TX_DW7 */ 2468 val = intel_de_read(dev_priv, CNL_PORT_TX_DW7_LN0(port)); 2469 val &= ~N_SCALAR_MASK; 2470 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); 2471 intel_de_write(dev_priv, CNL_PORT_TX_DW7_GRP(port), val); 2472 } 2473 2474 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, 2475 const struct intel_crtc_state *crtc_state, 2476 int level) 2477 { 2478 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2479 enum port port = encoder->port; 2480 int width, rate, ln; 2481 u32 val; 2482 2483 width = crtc_state->lane_count; 2484 rate = crtc_state->port_clock; 2485 2486 /* 2487 * 1. If port type is eDP or DP, 2488 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 2489 * else clear to 0b. 2490 */ 2491 val = intel_de_read(dev_priv, CNL_PORT_PCS_DW1_LN0(port)); 2492 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 2493 val &= ~COMMON_KEEPER_EN; 2494 else 2495 val |= COMMON_KEEPER_EN; 2496 intel_de_write(dev_priv, CNL_PORT_PCS_DW1_GRP(port), val); 2497 2498 /* 2. Program loadgen select */ 2499 /* 2500 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes 2501 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2502 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2503 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 2504 */ 2505 for (ln = 0; ln <= 3; ln++) { 2506 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port)); 2507 val &= ~LOADGEN_SELECT; 2508 2509 if ((rate <= 600000 && width == 4 && ln >= 1) || 2510 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { 2511 val |= LOADGEN_SELECT; 2512 } 2513 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val); 2514 } 2515 2516 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 2517 val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5); 2518 val |= SUS_CLOCK_CONFIG; 2519 intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val); 2520 2521 /* 4. Clear training enable to change swing values */ 2522 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 2523 val &= ~TX_TRAINING_EN; 2524 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 2525 2526 /* 5. Program swing and de-emphasis */ 2527 cnl_ddi_vswing_program(encoder, crtc_state, level); 2528 2529 /* 6. Set training enable to trigger update */ 2530 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 2531 val |= TX_TRAINING_EN; 2532 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 2533 } 2534 2535 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 2536 const struct intel_crtc_state *crtc_state, 2537 int level) 2538 { 2539 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2540 const struct cnl_ddi_buf_trans *ddi_translations; 2541 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2542 int n_entries, ln; 2543 u32 val; 2544 2545 if (INTEL_GEN(dev_priv) >= 12) 2546 ddi_translations = tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries); 2547 else if (IS_JSL_EHL(dev_priv)) 2548 ddi_translations = ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries); 2549 else 2550 ddi_translations = icl_get_combo_buf_trans(encoder, crtc_state, &n_entries); 2551 if (!ddi_translations) 2552 return; 2553 2554 if (level >= n_entries) { 2555 drm_dbg_kms(&dev_priv->drm, 2556 "DDI translation not found for level %d. Using %d instead.", 2557 level, n_entries - 1); 2558 level = n_entries - 1; 2559 } 2560 2561 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 2562 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2563 2564 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 2565 intel_dp->hobl_active = is_hobl_buf_trans(ddi_translations); 2566 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, 2567 intel_dp->hobl_active ? val : 0); 2568 } 2569 2570 /* Set PORT_TX_DW5 */ 2571 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 2572 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 2573 TAP2_DISABLE | TAP3_DISABLE); 2574 val |= SCALING_MODE_SEL(0x2); 2575 val |= RTERM_SELECT(0x6); 2576 val |= TAP3_DISABLE; 2577 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 2578 2579 /* Program PORT_TX_DW2 */ 2580 val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy)); 2581 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 2582 RCOMP_SCALAR_MASK); 2583 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); 2584 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); 2585 /* Program Rcomp scalar for every table entry */ 2586 val |= RCOMP_SCALAR(0x98); 2587 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val); 2588 2589 /* Program PORT_TX_DW4 */ 2590 /* We cannot write to GRP. It would overwrite individual loadgen. */ 2591 for (ln = 0; ln <= 3; ln++) { 2592 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy)); 2593 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 2594 CURSOR_COEFF_MASK); 2595 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); 2596 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); 2597 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); 2598 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val); 2599 } 2600 2601 /* Program PORT_TX_DW7 */ 2602 val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy)); 2603 val &= ~N_SCALAR_MASK; 2604 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); 2605 intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val); 2606 } 2607 2608 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 2609 const struct intel_crtc_state *crtc_state, 2610 int level) 2611 { 2612 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2613 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2614 int width, rate, ln; 2615 u32 val; 2616 2617 width = crtc_state->lane_count; 2618 rate = crtc_state->port_clock; 2619 2620 /* 2621 * 1. If port type is eDP or DP, 2622 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 2623 * else clear to 0b. 2624 */ 2625 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy)); 2626 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 2627 val &= ~COMMON_KEEPER_EN; 2628 else 2629 val |= COMMON_KEEPER_EN; 2630 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 2631 2632 /* 2. Program loadgen select */ 2633 /* 2634 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes 2635 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2636 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2637 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 2638 */ 2639 for (ln = 0; ln <= 3; ln++) { 2640 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy)); 2641 val &= ~LOADGEN_SELECT; 2642 2643 if ((rate <= 600000 && width == 4 && ln >= 1) || 2644 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { 2645 val |= LOADGEN_SELECT; 2646 } 2647 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val); 2648 } 2649 2650 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 2651 val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); 2652 val |= SUS_CLOCK_CONFIG; 2653 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val); 2654 2655 /* 4. Clear training enable to change swing values */ 2656 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 2657 val &= ~TX_TRAINING_EN; 2658 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 2659 2660 /* 5. Program swing and de-emphasis */ 2661 icl_ddi_combo_vswing_program(encoder, crtc_state, level); 2662 2663 /* 6. Set training enable to trigger update */ 2664 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 2665 val |= TX_TRAINING_EN; 2666 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 2667 } 2668 2669 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 2670 const struct intel_crtc_state *crtc_state, 2671 int level) 2672 { 2673 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2674 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 2675 const struct icl_mg_phy_ddi_buf_trans *ddi_translations; 2676 int n_entries, ln; 2677 u32 val; 2678 2679 ddi_translations = icl_get_mg_buf_trans(encoder, crtc_state, &n_entries); 2680 /* The table does not have values for level 3 and level 9. */ 2681 if (level >= n_entries || level == 3 || level == 9) { 2682 drm_dbg_kms(&dev_priv->drm, 2683 "DDI translation not found for level %d. Using %d instead.", 2684 level, n_entries - 2); 2685 level = n_entries - 2; 2686 } 2687 2688 /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */ 2689 for (ln = 0; ln < 2; ln++) { 2690 val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port)); 2691 val &= ~CRI_USE_FS32; 2692 intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), val); 2693 2694 val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port)); 2695 val &= ~CRI_USE_FS32; 2696 intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), val); 2697 } 2698 2699 /* Program MG_TX_SWINGCTRL with values from vswing table */ 2700 for (ln = 0; ln < 2; ln++) { 2701 val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port)); 2702 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; 2703 val |= CRI_TXDEEMPH_OVERRIDE_17_12( 2704 ddi_translations[level].cri_txdeemph_override_17_12); 2705 intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val); 2706 2707 val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port)); 2708 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; 2709 val |= CRI_TXDEEMPH_OVERRIDE_17_12( 2710 ddi_translations[level].cri_txdeemph_override_17_12); 2711 intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val); 2712 } 2713 2714 /* Program MG_TX_DRVCTRL with values from vswing table */ 2715 for (ln = 0; ln < 2; ln++) { 2716 val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port)); 2717 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 2718 CRI_TXDEEMPH_OVERRIDE_5_0_MASK); 2719 val |= CRI_TXDEEMPH_OVERRIDE_5_0( 2720 ddi_translations[level].cri_txdeemph_override_5_0) | 2721 CRI_TXDEEMPH_OVERRIDE_11_6( 2722 ddi_translations[level].cri_txdeemph_override_11_6) | 2723 CRI_TXDEEMPH_OVERRIDE_EN; 2724 intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val); 2725 2726 val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port)); 2727 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 2728 CRI_TXDEEMPH_OVERRIDE_5_0_MASK); 2729 val |= CRI_TXDEEMPH_OVERRIDE_5_0( 2730 ddi_translations[level].cri_txdeemph_override_5_0) | 2731 CRI_TXDEEMPH_OVERRIDE_11_6( 2732 ddi_translations[level].cri_txdeemph_override_11_6) | 2733 CRI_TXDEEMPH_OVERRIDE_EN; 2734 intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val); 2735 2736 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 2737 } 2738 2739 /* 2740 * Program MG_CLKHUB<LN, port being used> with value from frequency table 2741 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 2742 * values from table for which TX1 and TX2 enabled. 2743 */ 2744 for (ln = 0; ln < 2; ln++) { 2745 val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port)); 2746 if (crtc_state->port_clock < 300000) 2747 val |= CFG_LOW_RATE_LKREN_EN; 2748 else 2749 val &= ~CFG_LOW_RATE_LKREN_EN; 2750 intel_de_write(dev_priv, MG_CLKHUB(ln, tc_port), val); 2751 } 2752 2753 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 2754 for (ln = 0; ln < 2; ln++) { 2755 val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port)); 2756 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; 2757 if (crtc_state->port_clock <= 500000) { 2758 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; 2759 } else { 2760 val |= CFG_AMI_CK_DIV_OVERRIDE_EN | 2761 CFG_AMI_CK_DIV_OVERRIDE_VAL(1); 2762 } 2763 intel_de_write(dev_priv, MG_TX1_DCC(ln, tc_port), val); 2764 2765 val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port)); 2766 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; 2767 if (crtc_state->port_clock <= 500000) { 2768 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; 2769 } else { 2770 val |= CFG_AMI_CK_DIV_OVERRIDE_EN | 2771 CFG_AMI_CK_DIV_OVERRIDE_VAL(1); 2772 } 2773 intel_de_write(dev_priv, MG_TX2_DCC(ln, tc_port), val); 2774 } 2775 2776 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 2777 for (ln = 0; ln < 2; ln++) { 2778 val = intel_de_read(dev_priv, 2779 MG_TX1_PISO_READLOAD(ln, tc_port)); 2780 val |= CRI_CALCINIT; 2781 intel_de_write(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 2782 val); 2783 2784 val = intel_de_read(dev_priv, 2785 MG_TX2_PISO_READLOAD(ln, tc_port)); 2786 val |= CRI_CALCINIT; 2787 intel_de_write(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 2788 val); 2789 } 2790 } 2791 2792 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder, 2793 const struct intel_crtc_state *crtc_state, 2794 int level) 2795 { 2796 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2797 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2798 2799 if (intel_phy_is_combo(dev_priv, phy)) 2800 icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level); 2801 else 2802 icl_mg_phy_ddi_vswing_sequence(encoder, crtc_state, level); 2803 } 2804 2805 static void 2806 tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 2807 const struct intel_crtc_state *crtc_state, 2808 int level) 2809 { 2810 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2811 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 2812 const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations; 2813 u32 val, dpcnt_mask, dpcnt_val; 2814 int n_entries, ln; 2815 2816 ddi_translations = tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries); 2817 2818 if (level >= n_entries) 2819 level = n_entries - 1; 2820 2821 dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK | 2822 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 2823 DKL_TX_VSWING_CONTROL_MASK); 2824 dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control); 2825 dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control); 2826 dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control); 2827 2828 for (ln = 0; ln < 2; ln++) { 2829 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2830 HIP_INDEX_VAL(tc_port, ln)); 2831 2832 intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0); 2833 2834 /* All the registers are RMW */ 2835 val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(tc_port)); 2836 val &= ~dpcnt_mask; 2837 val |= dpcnt_val; 2838 intel_de_write(dev_priv, DKL_TX_DPCNTL0(tc_port), val); 2839 2840 val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(tc_port)); 2841 val &= ~dpcnt_mask; 2842 val |= dpcnt_val; 2843 intel_de_write(dev_priv, DKL_TX_DPCNTL1(tc_port), val); 2844 2845 val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port)); 2846 val &= ~DKL_TX_DP20BITMODE; 2847 intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val); 2848 } 2849 } 2850 2851 static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder, 2852 const struct intel_crtc_state *crtc_state, 2853 int level) 2854 { 2855 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2856 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2857 2858 if (intel_phy_is_combo(dev_priv, phy)) 2859 icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level); 2860 else 2861 tgl_dkl_phy_ddi_vswing_sequence(encoder, crtc_state, level); 2862 } 2863 2864 static int translate_signal_level(struct intel_dp *intel_dp, 2865 u8 signal_levels) 2866 { 2867 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2868 int i; 2869 2870 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 2871 if (index_to_dp_signal_levels[i] == signal_levels) 2872 return i; 2873 } 2874 2875 drm_WARN(&i915->drm, 1, 2876 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 2877 signal_levels); 2878 2879 return 0; 2880 } 2881 2882 static int intel_ddi_dp_level(struct intel_dp *intel_dp) 2883 { 2884 u8 train_set = intel_dp->train_set[0]; 2885 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2886 DP_TRAIN_PRE_EMPHASIS_MASK); 2887 2888 return translate_signal_level(intel_dp, signal_levels); 2889 } 2890 2891 static void 2892 tgl_set_signal_levels(struct intel_dp *intel_dp, 2893 const struct intel_crtc_state *crtc_state) 2894 { 2895 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2896 int level = intel_ddi_dp_level(intel_dp); 2897 2898 tgl_ddi_vswing_sequence(encoder, crtc_state, level); 2899 } 2900 2901 static void 2902 icl_set_signal_levels(struct intel_dp *intel_dp, 2903 const struct intel_crtc_state *crtc_state) 2904 { 2905 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2906 int level = intel_ddi_dp_level(intel_dp); 2907 2908 icl_ddi_vswing_sequence(encoder, crtc_state, level); 2909 } 2910 2911 static void 2912 cnl_set_signal_levels(struct intel_dp *intel_dp, 2913 const struct intel_crtc_state *crtc_state) 2914 { 2915 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2916 int level = intel_ddi_dp_level(intel_dp); 2917 2918 cnl_ddi_vswing_sequence(encoder, crtc_state, level); 2919 } 2920 2921 static void 2922 bxt_set_signal_levels(struct intel_dp *intel_dp, 2923 const struct intel_crtc_state *crtc_state) 2924 { 2925 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2926 int level = intel_ddi_dp_level(intel_dp); 2927 2928 bxt_ddi_vswing_sequence(encoder, crtc_state, level); 2929 } 2930 2931 static void 2932 hsw_set_signal_levels(struct intel_dp *intel_dp, 2933 const struct intel_crtc_state *crtc_state) 2934 { 2935 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2936 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2937 int level = intel_ddi_dp_level(intel_dp); 2938 enum port port = encoder->port; 2939 u32 signal_levels; 2940 2941 signal_levels = DDI_BUF_TRANS_SELECT(level); 2942 2943 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 2944 signal_levels); 2945 2946 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 2947 intel_dp->DP |= signal_levels; 2948 2949 if (IS_GEN9_BC(dev_priv)) 2950 skl_ddi_set_iboost(encoder, crtc_state, level); 2951 2952 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 2953 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 2954 } 2955 2956 static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv, 2957 enum phy phy) 2958 { 2959 if (IS_ROCKETLAKE(dev_priv)) { 2960 return RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 2961 } else if (intel_phy_is_combo(dev_priv, phy)) { 2962 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 2963 } else if (intel_phy_is_tc(dev_priv, phy)) { 2964 enum tc_port tc_port = intel_port_to_tc(dev_priv, 2965 (enum port)phy); 2966 2967 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port); 2968 } 2969 2970 return 0; 2971 } 2972 2973 static void icl_map_plls_to_ports(struct intel_encoder *encoder, 2974 const struct intel_crtc_state *crtc_state) 2975 { 2976 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2977 struct intel_shared_dpll *pll = crtc_state->shared_dpll; 2978 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2979 u32 val; 2980 2981 mutex_lock(&dev_priv->dpll.lock); 2982 2983 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 2984 drm_WARN_ON(&dev_priv->drm, 2985 (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0); 2986 2987 if (intel_phy_is_combo(dev_priv, phy)) { 2988 u32 mask, sel; 2989 2990 if (IS_ROCKETLAKE(dev_priv)) { 2991 mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 2992 sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 2993 } else { 2994 mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 2995 sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 2996 } 2997 2998 /* 2999 * Even though this register references DDIs, note that we 3000 * want to pass the PHY rather than the port (DDI). For 3001 * ICL, port=phy in all cases so it doesn't matter, but for 3002 * EHL the bspec notes the following: 3003 * 3004 * "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA 3005 * Clock Select chooses the PLL for both DDIA and DDID and 3006 * drives port A in all cases." 3007 */ 3008 val &= ~mask; 3009 val |= sel; 3010 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 3011 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); 3012 } 3013 3014 val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 3015 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 3016 3017 mutex_unlock(&dev_priv->dpll.lock); 3018 } 3019 3020 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder) 3021 { 3022 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3023 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3024 u32 val; 3025 3026 mutex_lock(&dev_priv->dpll.lock); 3027 3028 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 3029 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 3030 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 3031 3032 mutex_unlock(&dev_priv->dpll.lock); 3033 } 3034 3035 static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv, 3036 u32 port_mask, bool ddi_clk_needed) 3037 { 3038 enum port port; 3039 u32 val; 3040 3041 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 3042 for_each_port_masked(port, port_mask) { 3043 enum phy phy = intel_port_to_phy(dev_priv, port); 3044 bool ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv, 3045 phy); 3046 3047 if (ddi_clk_needed == !ddi_clk_off) 3048 continue; 3049 3050 /* 3051 * Punt on the case now where clock is gated, but it would 3052 * be needed by the port. Something else is really broken then. 3053 */ 3054 if (drm_WARN_ON(&dev_priv->drm, ddi_clk_needed)) 3055 continue; 3056 3057 drm_notice(&dev_priv->drm, 3058 "PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n", 3059 phy_name(phy)); 3060 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 3061 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 3062 } 3063 } 3064 3065 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 3066 { 3067 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3068 u32 port_mask; 3069 bool ddi_clk_needed; 3070 3071 /* 3072 * In case of DP MST, we sanitize the primary encoder only, not the 3073 * virtual ones. 3074 */ 3075 if (encoder->type == INTEL_OUTPUT_DP_MST) 3076 return; 3077 3078 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 3079 u8 pipe_mask; 3080 bool is_mst; 3081 3082 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 3083 /* 3084 * In the unlikely case that BIOS enables DP in MST mode, just 3085 * warn since our MST HW readout is incomplete. 3086 */ 3087 if (drm_WARN_ON(&dev_priv->drm, is_mst)) 3088 return; 3089 } 3090 3091 port_mask = BIT(encoder->port); 3092 ddi_clk_needed = encoder->base.crtc; 3093 3094 if (encoder->type == INTEL_OUTPUT_DSI) { 3095 struct intel_encoder *other_encoder; 3096 3097 port_mask = intel_dsi_encoder_ports(encoder); 3098 /* 3099 * Sanity check that we haven't incorrectly registered another 3100 * encoder using any of the ports of this DSI encoder. 3101 */ 3102 for_each_intel_encoder(&dev_priv->drm, other_encoder) { 3103 if (other_encoder == encoder) 3104 continue; 3105 3106 if (drm_WARN_ON(&dev_priv->drm, 3107 port_mask & BIT(other_encoder->port))) 3108 return; 3109 } 3110 /* 3111 * For DSI we keep the ddi clocks gated 3112 * except during enable/disable sequence. 3113 */ 3114 ddi_clk_needed = false; 3115 } 3116 3117 icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed); 3118 } 3119 3120 static void intel_ddi_clk_select(struct intel_encoder *encoder, 3121 const struct intel_crtc_state *crtc_state) 3122 { 3123 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3124 enum port port = encoder->port; 3125 enum phy phy = intel_port_to_phy(dev_priv, port); 3126 u32 val; 3127 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 3128 3129 if (drm_WARN_ON(&dev_priv->drm, !pll)) 3130 return; 3131 3132 mutex_lock(&dev_priv->dpll.lock); 3133 3134 if (INTEL_GEN(dev_priv) >= 11) { 3135 if (!intel_phy_is_combo(dev_priv, phy)) 3136 intel_de_write(dev_priv, DDI_CLK_SEL(port), 3137 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 3138 else if (IS_JSL_EHL(dev_priv) && port >= PORT_C) 3139 /* 3140 * MG does not exist but the programming is required 3141 * to ungate DDIC and DDID 3142 */ 3143 intel_de_write(dev_priv, DDI_CLK_SEL(port), 3144 DDI_CLK_SEL_MG); 3145 } else if (IS_CANNONLAKE(dev_priv)) { 3146 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */ 3147 val = intel_de_read(dev_priv, DPCLKA_CFGCR0); 3148 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); 3149 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port); 3150 intel_de_write(dev_priv, DPCLKA_CFGCR0, val); 3151 3152 /* 3153 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI. 3154 * This step and the step before must be done with separate 3155 * register writes. 3156 */ 3157 val = intel_de_read(dev_priv, DPCLKA_CFGCR0); 3158 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); 3159 intel_de_write(dev_priv, DPCLKA_CFGCR0, val); 3160 } else if (IS_GEN9_BC(dev_priv)) { 3161 /* DDI -> PLL mapping */ 3162 val = intel_de_read(dev_priv, DPLL_CTRL2); 3163 3164 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | 3165 DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); 3166 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 3167 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 3168 3169 intel_de_write(dev_priv, DPLL_CTRL2, val); 3170 3171 } else if (INTEL_GEN(dev_priv) < 9) { 3172 intel_de_write(dev_priv, PORT_CLK_SEL(port), 3173 hsw_pll_to_ddi_pll_sel(pll)); 3174 } 3175 3176 mutex_unlock(&dev_priv->dpll.lock); 3177 } 3178 3179 static void intel_ddi_clk_disable(struct intel_encoder *encoder) 3180 { 3181 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3182 enum port port = encoder->port; 3183 enum phy phy = intel_port_to_phy(dev_priv, port); 3184 3185 if (INTEL_GEN(dev_priv) >= 11) { 3186 if (!intel_phy_is_combo(dev_priv, phy) || 3187 (IS_JSL_EHL(dev_priv) && port >= PORT_C)) 3188 intel_de_write(dev_priv, DDI_CLK_SEL(port), 3189 DDI_CLK_SEL_NONE); 3190 } else if (IS_CANNONLAKE(dev_priv)) { 3191 intel_de_write(dev_priv, DPCLKA_CFGCR0, 3192 intel_de_read(dev_priv, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port)); 3193 } else if (IS_GEN9_BC(dev_priv)) { 3194 intel_de_write(dev_priv, DPLL_CTRL2, 3195 intel_de_read(dev_priv, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port)); 3196 } else if (INTEL_GEN(dev_priv) < 9) { 3197 intel_de_write(dev_priv, PORT_CLK_SEL(port), 3198 PORT_CLK_SEL_NONE); 3199 } 3200 } 3201 3202 static void 3203 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 3204 const struct intel_crtc_state *crtc_state) 3205 { 3206 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 3207 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port); 3208 u32 ln0, ln1, pin_assignment; 3209 u8 width; 3210 3211 if (dig_port->tc_mode == TC_PORT_TBT_ALT) 3212 return; 3213 3214 if (INTEL_GEN(dev_priv) >= 12) { 3215 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 3216 HIP_INDEX_VAL(tc_port, 0x0)); 3217 ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); 3218 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 3219 HIP_INDEX_VAL(tc_port, 0x1)); 3220 ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); 3221 } else { 3222 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 3223 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 3224 } 3225 3226 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 3227 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 3228 3229 /* DPPATC */ 3230 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 3231 width = crtc_state->lane_count; 3232 3233 switch (pin_assignment) { 3234 case 0x0: 3235 drm_WARN_ON(&dev_priv->drm, 3236 dig_port->tc_mode != TC_PORT_LEGACY); 3237 if (width == 1) { 3238 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 3239 } else { 3240 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3241 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3242 } 3243 break; 3244 case 0x1: 3245 if (width == 4) { 3246 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3247 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3248 } 3249 break; 3250 case 0x2: 3251 if (width == 2) { 3252 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3253 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3254 } 3255 break; 3256 case 0x3: 3257 case 0x5: 3258 if (width == 1) { 3259 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 3260 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 3261 } else { 3262 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3263 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3264 } 3265 break; 3266 case 0x4: 3267 case 0x6: 3268 if (width == 1) { 3269 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 3270 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 3271 } else { 3272 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3273 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3274 } 3275 break; 3276 default: 3277 MISSING_CASE(pin_assignment); 3278 } 3279 3280 if (INTEL_GEN(dev_priv) >= 12) { 3281 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 3282 HIP_INDEX_VAL(tc_port, 0x0)); 3283 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0); 3284 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 3285 HIP_INDEX_VAL(tc_port, 0x1)); 3286 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1); 3287 } else { 3288 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 3289 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 3290 } 3291 } 3292 3293 static enum transcoder 3294 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 3295 { 3296 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 3297 return crtc_state->mst_master_transcoder; 3298 else 3299 return crtc_state->cpu_transcoder; 3300 } 3301 3302 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 3303 const struct intel_crtc_state *crtc_state) 3304 { 3305 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3306 3307 if (INTEL_GEN(dev_priv) >= 12) 3308 return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state)); 3309 else 3310 return DP_TP_CTL(encoder->port); 3311 } 3312 3313 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 3314 const struct intel_crtc_state *crtc_state) 3315 { 3316 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3317 3318 if (INTEL_GEN(dev_priv) >= 12) 3319 return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state)); 3320 else 3321 return DP_TP_STATUS(encoder->port); 3322 } 3323 3324 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 3325 const struct intel_crtc_state *crtc_state) 3326 { 3327 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3328 3329 if (!crtc_state->fec_enable) 3330 return; 3331 3332 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0) 3333 drm_dbg_kms(&i915->drm, 3334 "Failed to set FEC_READY in the sink\n"); 3335 } 3336 3337 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 3338 const struct intel_crtc_state *crtc_state) 3339 { 3340 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3341 struct intel_dp *intel_dp; 3342 u32 val; 3343 3344 if (!crtc_state->fec_enable) 3345 return; 3346 3347 intel_dp = enc_to_intel_dp(encoder); 3348 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3349 val |= DP_TP_CTL_FEC_ENABLE; 3350 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 3351 3352 if (intel_de_wait_for_set(dev_priv, 3353 dp_tp_status_reg(encoder, crtc_state), 3354 DP_TP_STATUS_FEC_ENABLE_LIVE, 1)) 3355 drm_err(&dev_priv->drm, 3356 "Timed out waiting for FEC Enable Status\n"); 3357 } 3358 3359 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder, 3360 const struct intel_crtc_state *crtc_state) 3361 { 3362 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3363 struct intel_dp *intel_dp; 3364 u32 val; 3365 3366 if (!crtc_state->fec_enable) 3367 return; 3368 3369 intel_dp = enc_to_intel_dp(encoder); 3370 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3371 val &= ~DP_TP_CTL_FEC_ENABLE; 3372 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 3373 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3374 } 3375 3376 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 3377 struct intel_encoder *encoder, 3378 const struct intel_crtc_state *crtc_state, 3379 const struct drm_connector_state *conn_state) 3380 { 3381 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3382 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3383 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3384 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3385 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 3386 int level = intel_ddi_dp_level(intel_dp); 3387 3388 intel_dp_set_link_params(intel_dp, 3389 crtc_state->port_clock, 3390 crtc_state->lane_count); 3391 3392 /* 3393 * 1. Enable Power Wells 3394 * 3395 * This was handled at the beginning of intel_atomic_commit_tail(), 3396 * before we called down into this function. 3397 */ 3398 3399 /* 2. Enable Panel Power if PPS is required */ 3400 intel_edp_panel_on(intel_dp); 3401 3402 /* 3403 * 3. For non-TBT Type-C ports, set FIA lane count 3404 * (DFLEXDPSP.DPX4TXLATC) 3405 * 3406 * This was done before tgl_ddi_pre_enable_dp by 3407 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 3408 */ 3409 3410 /* 3411 * 4. Enable the port PLL. 3412 * 3413 * The PLL enabling itself was already done before this function by 3414 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 3415 * configure the PLL to port mapping here. 3416 */ 3417 intel_ddi_clk_select(encoder, crtc_state); 3418 3419 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 3420 if (!intel_phy_is_tc(dev_priv, phy) || 3421 dig_port->tc_mode != TC_PORT_TBT_ALT) 3422 intel_display_power_get(dev_priv, 3423 dig_port->ddi_io_power_domain); 3424 3425 /* 6. Program DP_MODE */ 3426 icl_program_mg_dp_mode(dig_port, crtc_state); 3427 3428 /* 3429 * 7. The rest of the below are substeps under the bspec's "Enable and 3430 * Train Display Port" step. Note that steps that are specific to 3431 * MST will be handled by intel_mst_pre_enable_dp() before/after it 3432 * calls into this function. Also intel_mst_pre_enable_dp() only calls 3433 * us when active_mst_links==0, so any steps designated for "single 3434 * stream or multi-stream master transcoder" can just be performed 3435 * unconditionally here. 3436 */ 3437 3438 /* 3439 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 3440 * Transcoder. 3441 */ 3442 intel_ddi_enable_pipe_clock(encoder, crtc_state); 3443 3444 /* 3445 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 3446 * Transport Select 3447 */ 3448 intel_ddi_config_transcoder_func(encoder, crtc_state); 3449 3450 /* 3451 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 3452 * selected 3453 * 3454 * This will be handled by the intel_dp_start_link_train() farther 3455 * down this function. 3456 */ 3457 3458 /* 7.e Configure voltage swing and related IO settings */ 3459 tgl_ddi_vswing_sequence(encoder, crtc_state, level); 3460 3461 /* 3462 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 3463 * the used lanes of the DDI. 3464 */ 3465 if (intel_phy_is_combo(dev_priv, phy)) { 3466 bool lane_reversal = 3467 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 3468 3469 intel_combo_phy_power_up_lanes(dev_priv, phy, false, 3470 crtc_state->lane_count, 3471 lane_reversal); 3472 } 3473 3474 /* 3475 * 7.g Configure and enable DDI_BUF_CTL 3476 * 7.h Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout 3477 * after 500 us. 3478 * 3479 * We only configure what the register value will be here. Actual 3480 * enabling happens during link training farther down. 3481 */ 3482 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 3483 3484 if (!is_mst) 3485 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 3486 3487 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); 3488 /* 3489 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 3490 * in the FEC_CONFIGURATION register to 1 before initiating link 3491 * training 3492 */ 3493 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 3494 3495 /* 3496 * 7.i Follow DisplayPort specification training sequence (see notes for 3497 * failure handling) 3498 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 3499 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 3500 * (timeout after 800 us) 3501 */ 3502 intel_dp_start_link_train(intel_dp, crtc_state); 3503 3504 /* 7.k Set DP_TP_CTL link training to Normal */ 3505 if (!is_trans_port_sync_mode(crtc_state)) 3506 intel_dp_stop_link_train(intel_dp, crtc_state); 3507 3508 /* 7.l Configure and enable FEC if needed */ 3509 intel_ddi_enable_fec(encoder, crtc_state); 3510 intel_dsc_enable(encoder, crtc_state); 3511 } 3512 3513 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 3514 struct intel_encoder *encoder, 3515 const struct intel_crtc_state *crtc_state, 3516 const struct drm_connector_state *conn_state) 3517 { 3518 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3519 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3520 enum port port = encoder->port; 3521 enum phy phy = intel_port_to_phy(dev_priv, port); 3522 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3523 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 3524 int level = intel_ddi_dp_level(intel_dp); 3525 3526 if (INTEL_GEN(dev_priv) < 11) 3527 drm_WARN_ON(&dev_priv->drm, 3528 is_mst && (port == PORT_A || port == PORT_E)); 3529 else 3530 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 3531 3532 intel_dp_set_link_params(intel_dp, 3533 crtc_state->port_clock, 3534 crtc_state->lane_count); 3535 3536 intel_edp_panel_on(intel_dp); 3537 3538 intel_ddi_clk_select(encoder, crtc_state); 3539 3540 if (!intel_phy_is_tc(dev_priv, phy) || 3541 dig_port->tc_mode != TC_PORT_TBT_ALT) 3542 intel_display_power_get(dev_priv, 3543 dig_port->ddi_io_power_domain); 3544 3545 icl_program_mg_dp_mode(dig_port, crtc_state); 3546 3547 if (INTEL_GEN(dev_priv) >= 11) 3548 icl_ddi_vswing_sequence(encoder, crtc_state, level); 3549 else if (IS_CANNONLAKE(dev_priv)) 3550 cnl_ddi_vswing_sequence(encoder, crtc_state, level); 3551 else if (IS_GEN9_LP(dev_priv)) 3552 bxt_ddi_vswing_sequence(encoder, crtc_state, level); 3553 else 3554 intel_prepare_dp_ddi_buffers(encoder, crtc_state); 3555 3556 if (intel_phy_is_combo(dev_priv, phy)) { 3557 bool lane_reversal = 3558 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 3559 3560 intel_combo_phy_power_up_lanes(dev_priv, phy, false, 3561 crtc_state->lane_count, 3562 lane_reversal); 3563 } 3564 3565 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 3566 if (!is_mst) 3567 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 3568 intel_dp_configure_protocol_converter(intel_dp); 3569 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, 3570 true); 3571 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 3572 intel_dp_start_link_train(intel_dp, crtc_state); 3573 if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) && 3574 !is_trans_port_sync_mode(crtc_state)) 3575 intel_dp_stop_link_train(intel_dp, crtc_state); 3576 3577 intel_ddi_enable_fec(encoder, crtc_state); 3578 3579 if (!is_mst) 3580 intel_ddi_enable_pipe_clock(encoder, crtc_state); 3581 3582 intel_dsc_enable(encoder, crtc_state); 3583 } 3584 3585 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 3586 struct intel_encoder *encoder, 3587 const struct intel_crtc_state *crtc_state, 3588 const struct drm_connector_state *conn_state) 3589 { 3590 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3591 3592 if (INTEL_GEN(dev_priv) >= 12) 3593 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 3594 else 3595 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 3596 3597 /* MST will call a setting of MSA after an allocating of Virtual Channel 3598 * from MST encoder pre_enable callback. 3599 */ 3600 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3601 intel_ddi_set_dp_msa(crtc_state, conn_state); 3602 3603 intel_dp_set_m_n(crtc_state, M1_N1); 3604 } 3605 } 3606 3607 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 3608 struct intel_encoder *encoder, 3609 const struct intel_crtc_state *crtc_state, 3610 const struct drm_connector_state *conn_state) 3611 { 3612 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3613 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3614 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3615 int level = intel_ddi_hdmi_level(encoder, crtc_state); 3616 3617 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 3618 intel_ddi_clk_select(encoder, crtc_state); 3619 3620 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); 3621 3622 icl_program_mg_dp_mode(dig_port, crtc_state); 3623 3624 if (INTEL_GEN(dev_priv) >= 12) 3625 tgl_ddi_vswing_sequence(encoder, crtc_state, level); 3626 else if (INTEL_GEN(dev_priv) == 11) 3627 icl_ddi_vswing_sequence(encoder, crtc_state, level); 3628 else if (IS_CANNONLAKE(dev_priv)) 3629 cnl_ddi_vswing_sequence(encoder, crtc_state, level); 3630 else if (IS_GEN9_LP(dev_priv)) 3631 bxt_ddi_vswing_sequence(encoder, crtc_state, level); 3632 else 3633 intel_prepare_hdmi_ddi_buffers(encoder, level); 3634 3635 if (IS_GEN9_BC(dev_priv)) 3636 skl_ddi_set_iboost(encoder, crtc_state, level); 3637 3638 intel_ddi_enable_pipe_clock(encoder, crtc_state); 3639 3640 dig_port->set_infoframes(encoder, 3641 crtc_state->has_infoframe, 3642 crtc_state, conn_state); 3643 } 3644 3645 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 3646 struct intel_encoder *encoder, 3647 const struct intel_crtc_state *crtc_state, 3648 const struct drm_connector_state *conn_state) 3649 { 3650 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3651 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3652 enum pipe pipe = crtc->pipe; 3653 3654 /* 3655 * When called from DP MST code: 3656 * - conn_state will be NULL 3657 * - encoder will be the main encoder (ie. mst->primary) 3658 * - the main connector associated with this port 3659 * won't be active or linked to a crtc 3660 * - crtc_state will be the state of the first stream to 3661 * be activated on this port, and it may not be the same 3662 * stream that will be deactivated last, but each stream 3663 * should have a state that is identical when it comes to 3664 * the DP link parameteres 3665 */ 3666 3667 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 3668 3669 if (INTEL_GEN(dev_priv) >= 11) 3670 icl_map_plls_to_ports(encoder, crtc_state); 3671 3672 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 3673 3674 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 3675 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 3676 conn_state); 3677 } else { 3678 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3679 3680 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 3681 conn_state); 3682 3683 /* FIXME precompute everything properly */ 3684 /* FIXME how do we turn infoframes off again? */ 3685 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) 3686 dig_port->set_infoframes(encoder, 3687 crtc_state->has_infoframe, 3688 crtc_state, conn_state); 3689 } 3690 } 3691 3692 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 3693 const struct intel_crtc_state *crtc_state) 3694 { 3695 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3696 enum port port = encoder->port; 3697 bool wait = false; 3698 u32 val; 3699 3700 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3701 if (val & DDI_BUF_CTL_ENABLE) { 3702 val &= ~DDI_BUF_CTL_ENABLE; 3703 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 3704 wait = true; 3705 } 3706 3707 if (intel_crtc_has_dp_encoder(crtc_state)) { 3708 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3709 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 3710 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 3711 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 3712 } 3713 3714 /* Disable FEC in DP Sink */ 3715 intel_ddi_disable_fec_state(encoder, crtc_state); 3716 3717 if (wait) 3718 intel_wait_ddi_buf_idle(dev_priv, port); 3719 } 3720 3721 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 3722 struct intel_encoder *encoder, 3723 const struct intel_crtc_state *old_crtc_state, 3724 const struct drm_connector_state *old_conn_state) 3725 { 3726 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3727 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3728 struct intel_dp *intel_dp = &dig_port->dp; 3729 bool is_mst = intel_crtc_has_type(old_crtc_state, 3730 INTEL_OUTPUT_DP_MST); 3731 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3732 3733 if (!is_mst) 3734 intel_dp_set_infoframes(encoder, false, 3735 old_crtc_state, old_conn_state); 3736 3737 /* 3738 * Power down sink before disabling the port, otherwise we end 3739 * up getting interrupts from the sink on detecting link loss. 3740 */ 3741 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 3742 3743 if (INTEL_GEN(dev_priv) >= 12) { 3744 if (is_mst) { 3745 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 3746 u32 val; 3747 3748 val = intel_de_read(dev_priv, 3749 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3750 val &= ~(TGL_TRANS_DDI_PORT_MASK | 3751 TRANS_DDI_MODE_SELECT_MASK); 3752 intel_de_write(dev_priv, 3753 TRANS_DDI_FUNC_CTL(cpu_transcoder), 3754 val); 3755 } 3756 } else { 3757 if (!is_mst) 3758 intel_ddi_disable_pipe_clock(old_crtc_state); 3759 } 3760 3761 intel_disable_ddi_buf(encoder, old_crtc_state); 3762 3763 /* 3764 * From TGL spec: "If single stream or multi-stream master transcoder: 3765 * Configure Transcoder Clock select to direct no clock to the 3766 * transcoder" 3767 */ 3768 if (INTEL_GEN(dev_priv) >= 12) 3769 intel_ddi_disable_pipe_clock(old_crtc_state); 3770 3771 intel_edp_panel_vdd_on(intel_dp); 3772 intel_edp_panel_off(intel_dp); 3773 3774 if (!intel_phy_is_tc(dev_priv, phy) || 3775 dig_port->tc_mode != TC_PORT_TBT_ALT) 3776 intel_display_power_put_unchecked(dev_priv, 3777 dig_port->ddi_io_power_domain); 3778 3779 intel_ddi_clk_disable(encoder); 3780 } 3781 3782 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 3783 struct intel_encoder *encoder, 3784 const struct intel_crtc_state *old_crtc_state, 3785 const struct drm_connector_state *old_conn_state) 3786 { 3787 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3788 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3789 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3790 3791 dig_port->set_infoframes(encoder, false, 3792 old_crtc_state, old_conn_state); 3793 3794 intel_ddi_disable_pipe_clock(old_crtc_state); 3795 3796 intel_disable_ddi_buf(encoder, old_crtc_state); 3797 3798 intel_display_power_put_unchecked(dev_priv, 3799 dig_port->ddi_io_power_domain); 3800 3801 intel_ddi_clk_disable(encoder); 3802 3803 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3804 } 3805 3806 static void intel_ddi_post_disable(struct intel_atomic_state *state, 3807 struct intel_encoder *encoder, 3808 const struct intel_crtc_state *old_crtc_state, 3809 const struct drm_connector_state *old_conn_state) 3810 { 3811 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3812 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3813 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3814 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 3815 3816 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) { 3817 intel_crtc_vblank_off(old_crtc_state); 3818 3819 intel_disable_pipe(old_crtc_state); 3820 3821 intel_ddi_disable_transcoder_func(old_crtc_state); 3822 3823 intel_dsc_disable(old_crtc_state); 3824 3825 if (INTEL_GEN(dev_priv) >= 9) 3826 skl_scaler_disable(old_crtc_state); 3827 else 3828 ilk_pfit_disable(old_crtc_state); 3829 } 3830 3831 /* 3832 * When called from DP MST code: 3833 * - old_conn_state will be NULL 3834 * - encoder will be the main encoder (ie. mst->primary) 3835 * - the main connector associated with this port 3836 * won't be active or linked to a crtc 3837 * - old_crtc_state will be the state of the last stream to 3838 * be deactivated on this port, and it may not be the same 3839 * stream that was activated last, but each stream 3840 * should have a state that is identical when it comes to 3841 * the DP link parameteres 3842 */ 3843 3844 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3845 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 3846 old_conn_state); 3847 else 3848 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 3849 old_conn_state); 3850 3851 if (INTEL_GEN(dev_priv) >= 11) 3852 icl_unmap_plls_to_ports(encoder); 3853 3854 if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port) 3855 intel_display_power_put_unchecked(dev_priv, 3856 intel_ddi_main_link_aux_domain(dig_port)); 3857 3858 if (is_tc_port) 3859 intel_tc_port_put_link(dig_port); 3860 } 3861 3862 void intel_ddi_fdi_post_disable(struct intel_atomic_state *state, 3863 struct intel_encoder *encoder, 3864 const struct intel_crtc_state *old_crtc_state, 3865 const struct drm_connector_state *old_conn_state) 3866 { 3867 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3868 u32 val; 3869 3870 /* 3871 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable) 3872 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN, 3873 * step 13 is the correct place for it. Step 18 is where it was 3874 * originally before the BUN. 3875 */ 3876 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 3877 val &= ~FDI_RX_ENABLE; 3878 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 3879 3880 intel_disable_ddi_buf(encoder, old_crtc_state); 3881 intel_ddi_clk_disable(encoder); 3882 3883 val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); 3884 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 3885 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 3886 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val); 3887 3888 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 3889 val &= ~FDI_PCDCLK; 3890 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 3891 3892 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 3893 val &= ~FDI_RX_PLL_ENABLE; 3894 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 3895 } 3896 3897 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 3898 struct intel_encoder *encoder, 3899 const struct intel_crtc_state *crtc_state) 3900 { 3901 const struct drm_connector_state *conn_state; 3902 struct drm_connector *conn; 3903 int i; 3904 3905 if (!crtc_state->sync_mode_slaves_mask) 3906 return; 3907 3908 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 3909 struct intel_encoder *slave_encoder = 3910 to_intel_encoder(conn_state->best_encoder); 3911 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 3912 const struct intel_crtc_state *slave_crtc_state; 3913 3914 if (!slave_crtc) 3915 continue; 3916 3917 slave_crtc_state = 3918 intel_atomic_get_new_crtc_state(state, slave_crtc); 3919 3920 if (slave_crtc_state->master_transcoder != 3921 crtc_state->cpu_transcoder) 3922 continue; 3923 3924 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 3925 slave_crtc_state); 3926 } 3927 3928 usleep_range(200, 400); 3929 3930 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 3931 crtc_state); 3932 } 3933 3934 static void intel_enable_ddi_dp(struct intel_atomic_state *state, 3935 struct intel_encoder *encoder, 3936 const struct intel_crtc_state *crtc_state, 3937 const struct drm_connector_state *conn_state) 3938 { 3939 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3940 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3941 enum port port = encoder->port; 3942 3943 if (port == PORT_A && INTEL_GEN(dev_priv) < 9) 3944 intel_dp_stop_link_train(intel_dp, crtc_state); 3945 3946 intel_edp_backlight_on(crtc_state, conn_state); 3947 intel_psr_enable(intel_dp, crtc_state, conn_state); 3948 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3949 intel_edp_drrs_enable(intel_dp, crtc_state); 3950 3951 if (crtc_state->has_audio) 3952 intel_audio_codec_enable(encoder, crtc_state, conn_state); 3953 3954 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3955 } 3956 3957 static i915_reg_t 3958 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 3959 enum port port) 3960 { 3961 static const enum transcoder trans[] = { 3962 [PORT_A] = TRANSCODER_EDP, 3963 [PORT_B] = TRANSCODER_A, 3964 [PORT_C] = TRANSCODER_B, 3965 [PORT_D] = TRANSCODER_C, 3966 [PORT_E] = TRANSCODER_A, 3967 }; 3968 3969 drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) < 9); 3970 3971 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) 3972 port = PORT_A; 3973 3974 return CHICKEN_TRANS(trans[port]); 3975 } 3976 3977 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, 3978 struct intel_encoder *encoder, 3979 const struct intel_crtc_state *crtc_state, 3980 const struct drm_connector_state *conn_state) 3981 { 3982 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3983 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3984 struct drm_connector *connector = conn_state->connector; 3985 enum port port = encoder->port; 3986 3987 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3988 crtc_state->hdmi_high_tmds_clock_ratio, 3989 crtc_state->hdmi_scrambling)) 3990 drm_dbg_kms(&dev_priv->drm, 3991 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3992 connector->base.id, connector->name); 3993 3994 /* Display WA #1143: skl,kbl,cfl */ 3995 if (IS_GEN9_BC(dev_priv)) { 3996 /* 3997 * For some reason these chicken bits have been 3998 * stuffed into a transcoder register, event though 3999 * the bits affect a specific DDI port rather than 4000 * a specific transcoder. 4001 */ 4002 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 4003 u32 val; 4004 4005 val = intel_de_read(dev_priv, reg); 4006 4007 if (port == PORT_E) 4008 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 4009 DDIE_TRAINING_OVERRIDE_VALUE; 4010 else 4011 val |= DDI_TRAINING_OVERRIDE_ENABLE | 4012 DDI_TRAINING_OVERRIDE_VALUE; 4013 4014 intel_de_write(dev_priv, reg, val); 4015 intel_de_posting_read(dev_priv, reg); 4016 4017 udelay(1); 4018 4019 if (port == PORT_E) 4020 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 4021 DDIE_TRAINING_OVERRIDE_VALUE); 4022 else 4023 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 4024 DDI_TRAINING_OVERRIDE_VALUE); 4025 4026 intel_de_write(dev_priv, reg, val); 4027 } 4028 4029 /* In HDMI/DVI mode, the port width, and swing/emphasis values 4030 * are ignored so nothing special needs to be done besides 4031 * enabling the port. 4032 */ 4033 intel_de_write(dev_priv, DDI_BUF_CTL(port), 4034 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE); 4035 4036 if (crtc_state->has_audio) 4037 intel_audio_codec_enable(encoder, crtc_state, conn_state); 4038 } 4039 4040 static void intel_enable_ddi(struct intel_atomic_state *state, 4041 struct intel_encoder *encoder, 4042 const struct intel_crtc_state *crtc_state, 4043 const struct drm_connector_state *conn_state) 4044 { 4045 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 4046 4047 intel_ddi_enable_transcoder_func(encoder, crtc_state); 4048 4049 intel_enable_pipe(crtc_state); 4050 4051 intel_crtc_vblank_on(crtc_state); 4052 4053 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 4054 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state); 4055 else 4056 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state); 4057 4058 /* Enable hdcp if it's desired */ 4059 if (conn_state->content_protection == 4060 DRM_MODE_CONTENT_PROTECTION_DESIRED) 4061 intel_hdcp_enable(to_intel_connector(conn_state->connector), 4062 crtc_state->cpu_transcoder, 4063 (u8)conn_state->hdcp_content_type); 4064 } 4065 4066 static void intel_disable_ddi_dp(struct intel_atomic_state *state, 4067 struct intel_encoder *encoder, 4068 const struct intel_crtc_state *old_crtc_state, 4069 const struct drm_connector_state *old_conn_state) 4070 { 4071 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4072 4073 intel_dp->link_trained = false; 4074 4075 if (old_crtc_state->has_audio) 4076 intel_audio_codec_disable(encoder, 4077 old_crtc_state, old_conn_state); 4078 4079 intel_edp_drrs_disable(intel_dp, old_crtc_state); 4080 intel_psr_disable(intel_dp, old_crtc_state); 4081 intel_edp_backlight_off(old_conn_state); 4082 /* Disable the decompression in DP Sink */ 4083 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, 4084 false); 4085 } 4086 4087 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state, 4088 struct intel_encoder *encoder, 4089 const struct intel_crtc_state *old_crtc_state, 4090 const struct drm_connector_state *old_conn_state) 4091 { 4092 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4093 struct drm_connector *connector = old_conn_state->connector; 4094 4095 if (old_crtc_state->has_audio) 4096 intel_audio_codec_disable(encoder, 4097 old_crtc_state, old_conn_state); 4098 4099 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 4100 false, false)) 4101 drm_dbg_kms(&i915->drm, 4102 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 4103 connector->base.id, connector->name); 4104 } 4105 4106 static void intel_disable_ddi(struct intel_atomic_state *state, 4107 struct intel_encoder *encoder, 4108 const struct intel_crtc_state *old_crtc_state, 4109 const struct drm_connector_state *old_conn_state) 4110 { 4111 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 4112 4113 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 4114 intel_disable_ddi_hdmi(state, encoder, old_crtc_state, 4115 old_conn_state); 4116 else 4117 intel_disable_ddi_dp(state, encoder, old_crtc_state, 4118 old_conn_state); 4119 } 4120 4121 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 4122 struct intel_encoder *encoder, 4123 const struct intel_crtc_state *crtc_state, 4124 const struct drm_connector_state *conn_state) 4125 { 4126 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4127 4128 intel_ddi_set_dp_msa(crtc_state, conn_state); 4129 4130 intel_psr_update(intel_dp, crtc_state, conn_state); 4131 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 4132 intel_edp_drrs_update(intel_dp, crtc_state); 4133 4134 intel_panel_update_backlight(state, encoder, crtc_state, conn_state); 4135 } 4136 4137 void intel_ddi_update_pipe(struct intel_atomic_state *state, 4138 struct intel_encoder *encoder, 4139 const struct intel_crtc_state *crtc_state, 4140 const struct drm_connector_state *conn_state) 4141 { 4142 4143 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 4144 !intel_encoder_is_mst(encoder)) 4145 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 4146 conn_state); 4147 4148 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 4149 } 4150 4151 static void 4152 intel_ddi_update_prepare(struct intel_atomic_state *state, 4153 struct intel_encoder *encoder, 4154 struct intel_crtc *crtc) 4155 { 4156 struct intel_crtc_state *crtc_state = 4157 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL; 4158 int required_lanes = crtc_state ? crtc_state->lane_count : 1; 4159 4160 drm_WARN_ON(state->base.dev, crtc && crtc->active); 4161 4162 intel_tc_port_get_link(enc_to_dig_port(encoder), 4163 required_lanes); 4164 if (crtc_state && crtc_state->hw.active) 4165 intel_update_active_dpll(state, crtc, encoder); 4166 } 4167 4168 static void 4169 intel_ddi_update_complete(struct intel_atomic_state *state, 4170 struct intel_encoder *encoder, 4171 struct intel_crtc *crtc) 4172 { 4173 intel_tc_port_put_link(enc_to_dig_port(encoder)); 4174 } 4175 4176 static void 4177 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 4178 struct intel_encoder *encoder, 4179 const struct intel_crtc_state *crtc_state, 4180 const struct drm_connector_state *conn_state) 4181 { 4182 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4183 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4184 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 4185 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 4186 4187 if (is_tc_port) 4188 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 4189 4190 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) 4191 intel_display_power_get(dev_priv, 4192 intel_ddi_main_link_aux_domain(dig_port)); 4193 4194 if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT) 4195 /* 4196 * Program the lane count for static/dynamic connections on 4197 * Type-C ports. Skip this step for TBT. 4198 */ 4199 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 4200 else if (IS_GEN9_LP(dev_priv)) 4201 bxt_ddi_phy_set_lane_optim_mask(encoder, 4202 crtc_state->lane_lat_optim_mask); 4203 } 4204 4205 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 4206 const struct intel_crtc_state *crtc_state) 4207 { 4208 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 4209 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4210 enum port port = encoder->port; 4211 u32 dp_tp_ctl, ddi_buf_ctl; 4212 bool wait = false; 4213 4214 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 4215 4216 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 4217 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 4218 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 4219 intel_de_write(dev_priv, DDI_BUF_CTL(port), 4220 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 4221 wait = true; 4222 } 4223 4224 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 4225 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1; 4226 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 4227 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 4228 4229 if (wait) 4230 intel_wait_ddi_buf_idle(dev_priv, port); 4231 } 4232 4233 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 4234 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 4235 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 4236 } else { 4237 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 4238 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 4239 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4240 } 4241 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 4242 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 4243 4244 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 4245 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 4246 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 4247 4248 intel_wait_ddi_buf_active(dev_priv, port); 4249 } 4250 4251 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 4252 const struct intel_crtc_state *crtc_state, 4253 u8 dp_train_pat) 4254 { 4255 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 4256 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4257 u32 temp; 4258 4259 temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 4260 4261 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 4262 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 4263 case DP_TRAINING_PATTERN_DISABLE: 4264 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 4265 break; 4266 case DP_TRAINING_PATTERN_1: 4267 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 4268 break; 4269 case DP_TRAINING_PATTERN_2: 4270 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 4271 break; 4272 case DP_TRAINING_PATTERN_3: 4273 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 4274 break; 4275 case DP_TRAINING_PATTERN_4: 4276 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 4277 break; 4278 } 4279 4280 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp); 4281 } 4282 4283 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 4284 const struct intel_crtc_state *crtc_state) 4285 { 4286 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 4287 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4288 enum port port = encoder->port; 4289 u32 val; 4290 4291 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 4292 val &= ~DP_TP_CTL_LINK_TRAIN_MASK; 4293 val |= DP_TP_CTL_LINK_TRAIN_IDLE; 4294 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 4295 4296 /* 4297 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 4298 * reason we need to set idle transmission mode is to work around a HW 4299 * issue where we enable the pipe while not in idle link-training mode. 4300 * In this case there is requirement to wait for a minimum number of 4301 * idle patterns to be sent. 4302 */ 4303 if (port == PORT_A && INTEL_GEN(dev_priv) < 12) 4304 return; 4305 4306 if (intel_de_wait_for_set(dev_priv, 4307 dp_tp_status_reg(encoder, crtc_state), 4308 DP_TP_STATUS_IDLE_DONE, 1)) 4309 drm_err(&dev_priv->drm, 4310 "Timed out waiting for DP idle patterns\n"); 4311 } 4312 4313 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 4314 enum transcoder cpu_transcoder) 4315 { 4316 if (cpu_transcoder == TRANSCODER_EDP) 4317 return false; 4318 4319 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) 4320 return false; 4321 4322 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 4323 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 4324 } 4325 4326 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, 4327 struct intel_crtc_state *crtc_state) 4328 { 4329 if (INTEL_GEN(dev_priv) >= 12 && crtc_state->port_clock > 594000) 4330 crtc_state->min_voltage_level = 2; 4331 else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000) 4332 crtc_state->min_voltage_level = 3; 4333 else if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000) 4334 crtc_state->min_voltage_level = 1; 4335 else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000) 4336 crtc_state->min_voltage_level = 2; 4337 } 4338 4339 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, 4340 enum transcoder cpu_transcoder) 4341 { 4342 u32 master_select; 4343 4344 if (INTEL_GEN(dev_priv) >= 11) { 4345 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder)); 4346 4347 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 4348 return INVALID_TRANSCODER; 4349 4350 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 4351 } else { 4352 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 4353 4354 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 4355 return INVALID_TRANSCODER; 4356 4357 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 4358 } 4359 4360 if (master_select == 0) 4361 return TRANSCODER_EDP; 4362 else 4363 return master_select - 1; 4364 } 4365 4366 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 4367 { 4368 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 4369 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 4370 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 4371 enum transcoder cpu_transcoder; 4372 4373 crtc_state->master_transcoder = 4374 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); 4375 4376 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { 4377 enum intel_display_power_domain power_domain; 4378 intel_wakeref_t trans_wakeref; 4379 4380 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 4381 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 4382 power_domain); 4383 4384 if (!trans_wakeref) 4385 continue; 4386 4387 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == 4388 crtc_state->cpu_transcoder) 4389 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 4390 4391 intel_display_power_put(dev_priv, power_domain, trans_wakeref); 4392 } 4393 4394 drm_WARN_ON(&dev_priv->drm, 4395 crtc_state->master_transcoder != INVALID_TRANSCODER && 4396 crtc_state->sync_mode_slaves_mask); 4397 } 4398 4399 void intel_ddi_get_config(struct intel_encoder *encoder, 4400 struct intel_crtc_state *pipe_config) 4401 { 4402 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4403 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); 4404 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4405 u32 temp, flags = 0; 4406 4407 /* XXX: DSI transcoder paranoia */ 4408 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 4409 return; 4410 4411 intel_dsc_get_config(encoder, pipe_config); 4412 4413 temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 4414 if (temp & TRANS_DDI_PHSYNC) 4415 flags |= DRM_MODE_FLAG_PHSYNC; 4416 else 4417 flags |= DRM_MODE_FLAG_NHSYNC; 4418 if (temp & TRANS_DDI_PVSYNC) 4419 flags |= DRM_MODE_FLAG_PVSYNC; 4420 else 4421 flags |= DRM_MODE_FLAG_NVSYNC; 4422 4423 pipe_config->hw.adjusted_mode.flags |= flags; 4424 4425 switch (temp & TRANS_DDI_BPC_MASK) { 4426 case TRANS_DDI_BPC_6: 4427 pipe_config->pipe_bpp = 18; 4428 break; 4429 case TRANS_DDI_BPC_8: 4430 pipe_config->pipe_bpp = 24; 4431 break; 4432 case TRANS_DDI_BPC_10: 4433 pipe_config->pipe_bpp = 30; 4434 break; 4435 case TRANS_DDI_BPC_12: 4436 pipe_config->pipe_bpp = 36; 4437 break; 4438 default: 4439 break; 4440 } 4441 4442 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 4443 case TRANS_DDI_MODE_SELECT_HDMI: 4444 pipe_config->has_hdmi_sink = true; 4445 4446 pipe_config->infoframes.enable |= 4447 intel_hdmi_infoframes_enabled(encoder, pipe_config); 4448 4449 if (pipe_config->infoframes.enable) 4450 pipe_config->has_infoframe = true; 4451 4452 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 4453 pipe_config->hdmi_scrambling = true; 4454 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 4455 pipe_config->hdmi_high_tmds_clock_ratio = true; 4456 fallthrough; 4457 case TRANS_DDI_MODE_SELECT_DVI: 4458 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 4459 pipe_config->lane_count = 4; 4460 break; 4461 case TRANS_DDI_MODE_SELECT_FDI: 4462 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 4463 break; 4464 case TRANS_DDI_MODE_SELECT_DP_SST: 4465 if (encoder->type == INTEL_OUTPUT_EDP) 4466 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 4467 else 4468 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 4469 pipe_config->lane_count = 4470 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4471 intel_dp_get_m_n(intel_crtc, pipe_config); 4472 4473 if (INTEL_GEN(dev_priv) >= 11) { 4474 i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config); 4475 4476 pipe_config->fec_enable = 4477 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE; 4478 4479 drm_dbg_kms(&dev_priv->drm, 4480 "[ENCODER:%d:%s] Fec status: %u\n", 4481 encoder->base.base.id, encoder->base.name, 4482 pipe_config->fec_enable); 4483 } 4484 4485 pipe_config->infoframes.enable |= 4486 intel_hdmi_infoframes_enabled(encoder, pipe_config); 4487 4488 break; 4489 case TRANS_DDI_MODE_SELECT_DP_MST: 4490 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 4491 pipe_config->lane_count = 4492 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4493 4494 if (INTEL_GEN(dev_priv) >= 12) 4495 pipe_config->mst_master_transcoder = 4496 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); 4497 4498 intel_dp_get_m_n(intel_crtc, pipe_config); 4499 4500 pipe_config->infoframes.enable |= 4501 intel_hdmi_infoframes_enabled(encoder, pipe_config); 4502 break; 4503 default: 4504 break; 4505 } 4506 4507 pipe_config->has_audio = 4508 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 4509 4510 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp && 4511 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { 4512 /* 4513 * This is a big fat ugly hack. 4514 * 4515 * Some machines in UEFI boot mode provide us a VBT that has 18 4516 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 4517 * unknown we fail to light up. Yet the same BIOS boots up with 4518 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 4519 * max, not what it tells us to use. 4520 * 4521 * Note: This will still be broken if the eDP panel is not lit 4522 * up by the BIOS, and thus we can't get the mode at module 4523 * load. 4524 */ 4525 drm_dbg_kms(&dev_priv->drm, 4526 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 4527 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); 4528 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; 4529 } 4530 4531 intel_ddi_clock_get(encoder, pipe_config); 4532 4533 if (IS_GEN9_LP(dev_priv)) 4534 pipe_config->lane_lat_optim_mask = 4535 bxt_ddi_phy_get_lane_lat_optim_mask(encoder); 4536 4537 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 4538 4539 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 4540 4541 intel_read_infoframe(encoder, pipe_config, 4542 HDMI_INFOFRAME_TYPE_AVI, 4543 &pipe_config->infoframes.avi); 4544 intel_read_infoframe(encoder, pipe_config, 4545 HDMI_INFOFRAME_TYPE_SPD, 4546 &pipe_config->infoframes.spd); 4547 intel_read_infoframe(encoder, pipe_config, 4548 HDMI_INFOFRAME_TYPE_VENDOR, 4549 &pipe_config->infoframes.hdmi); 4550 intel_read_infoframe(encoder, pipe_config, 4551 HDMI_INFOFRAME_TYPE_DRM, 4552 &pipe_config->infoframes.drm); 4553 4554 if (INTEL_GEN(dev_priv) >= 8) 4555 bdw_get_trans_port_sync_config(pipe_config); 4556 4557 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 4558 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 4559 } 4560 4561 static void intel_ddi_sync_state(struct intel_encoder *encoder, 4562 const struct intel_crtc_state *crtc_state) 4563 { 4564 if (intel_crtc_has_dp_encoder(crtc_state)) 4565 intel_dp_sync_state(encoder, crtc_state); 4566 } 4567 4568 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 4569 struct intel_crtc_state *crtc_state) 4570 { 4571 if (intel_crtc_has_dp_encoder(crtc_state)) 4572 return intel_dp_initial_fastset_check(encoder, crtc_state); 4573 4574 return true; 4575 } 4576 4577 static enum intel_output_type 4578 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4579 struct intel_crtc_state *crtc_state, 4580 struct drm_connector_state *conn_state) 4581 { 4582 switch (conn_state->connector->connector_type) { 4583 case DRM_MODE_CONNECTOR_HDMIA: 4584 return INTEL_OUTPUT_HDMI; 4585 case DRM_MODE_CONNECTOR_eDP: 4586 return INTEL_OUTPUT_EDP; 4587 case DRM_MODE_CONNECTOR_DisplayPort: 4588 return INTEL_OUTPUT_DP; 4589 default: 4590 MISSING_CASE(conn_state->connector->connector_type); 4591 return INTEL_OUTPUT_UNUSED; 4592 } 4593 } 4594 4595 static int intel_ddi_compute_config(struct intel_encoder *encoder, 4596 struct intel_crtc_state *pipe_config, 4597 struct drm_connector_state *conn_state) 4598 { 4599 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4600 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4601 enum port port = encoder->port; 4602 int ret; 4603 4604 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 4605 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4606 4607 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4608 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4609 } else { 4610 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 4611 } 4612 4613 if (ret) 4614 return ret; 4615 4616 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 4617 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4618 pipe_config->pch_pfit.force_thru = 4619 pipe_config->pch_pfit.enabled || 4620 pipe_config->crc_enabled; 4621 4622 if (IS_GEN9_LP(dev_priv)) 4623 pipe_config->lane_lat_optim_mask = 4624 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4625 4626 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 4627 4628 return 0; 4629 } 4630 4631 static bool mode_equal(const struct drm_display_mode *mode1, 4632 const struct drm_display_mode *mode2) 4633 { 4634 return drm_mode_match(mode1, mode2, 4635 DRM_MODE_MATCH_TIMINGS | 4636 DRM_MODE_MATCH_FLAGS | 4637 DRM_MODE_MATCH_3D_FLAGS) && 4638 mode1->clock == mode2->clock; /* we want an exact match */ 4639 } 4640 4641 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 4642 const struct intel_link_m_n *m_n_2) 4643 { 4644 return m_n_1->tu == m_n_2->tu && 4645 m_n_1->gmch_m == m_n_2->gmch_m && 4646 m_n_1->gmch_n == m_n_2->gmch_n && 4647 m_n_1->link_m == m_n_2->link_m && 4648 m_n_1->link_n == m_n_2->link_n; 4649 } 4650 4651 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 4652 const struct intel_crtc_state *crtc_state2) 4653 { 4654 return crtc_state1->hw.active && crtc_state2->hw.active && 4655 crtc_state1->output_types == crtc_state2->output_types && 4656 crtc_state1->output_format == crtc_state2->output_format && 4657 crtc_state1->lane_count == crtc_state2->lane_count && 4658 crtc_state1->port_clock == crtc_state2->port_clock && 4659 mode_equal(&crtc_state1->hw.adjusted_mode, 4660 &crtc_state2->hw.adjusted_mode) && 4661 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 4662 } 4663 4664 static u8 4665 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4666 int tile_group_id) 4667 { 4668 struct drm_connector *connector; 4669 const struct drm_connector_state *conn_state; 4670 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 4671 struct intel_atomic_state *state = 4672 to_intel_atomic_state(ref_crtc_state->uapi.state); 4673 u8 transcoders = 0; 4674 int i; 4675 4676 /* 4677 * We don't enable port sync on BDW due to missing w/as and 4678 * due to not having adjusted the modeset sequence appropriately. 4679 */ 4680 if (INTEL_GEN(dev_priv) < 9) 4681 return 0; 4682 4683 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4684 return 0; 4685 4686 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4687 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4688 const struct intel_crtc_state *crtc_state; 4689 4690 if (!crtc) 4691 continue; 4692 4693 if (!connector->has_tile || 4694 connector->tile_group->id != 4695 tile_group_id) 4696 continue; 4697 crtc_state = intel_atomic_get_new_crtc_state(state, 4698 crtc); 4699 if (!crtcs_port_sync_compatible(ref_crtc_state, 4700 crtc_state)) 4701 continue; 4702 transcoders |= BIT(crtc_state->cpu_transcoder); 4703 } 4704 4705 return transcoders; 4706 } 4707 4708 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 4709 struct intel_crtc_state *crtc_state, 4710 struct drm_connector_state *conn_state) 4711 { 4712 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4713 struct drm_connector *connector = conn_state->connector; 4714 u8 port_sync_transcoders = 0; 4715 4716 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]", 4717 encoder->base.base.id, encoder->base.name, 4718 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4719 4720 if (connector->has_tile) 4721 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4722 connector->tile_group->id); 4723 4724 /* 4725 * EDP Transcoders cannot be ensalved 4726 * make them a master always when present 4727 */ 4728 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4729 crtc_state->master_transcoder = TRANSCODER_EDP; 4730 else 4731 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4732 4733 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4734 crtc_state->master_transcoder = INVALID_TRANSCODER; 4735 crtc_state->sync_mode_slaves_mask = 4736 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4737 } 4738 4739 return 0; 4740 } 4741 4742 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4743 { 4744 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4745 4746 intel_dp_encoder_flush_work(encoder); 4747 4748 drm_encoder_cleanup(encoder); 4749 kfree(dig_port); 4750 } 4751 4752 static const struct drm_encoder_funcs intel_ddi_funcs = { 4753 .reset = intel_dp_encoder_reset, 4754 .destroy = intel_ddi_encoder_destroy, 4755 }; 4756 4757 static struct intel_connector * 4758 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 4759 { 4760 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4761 struct intel_connector *connector; 4762 enum port port = dig_port->base.port; 4763 4764 connector = intel_connector_alloc(); 4765 if (!connector) 4766 return NULL; 4767 4768 dig_port->dp.output_reg = DDI_BUF_CTL(port); 4769 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 4770 dig_port->dp.set_link_train = intel_ddi_set_link_train; 4771 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4772 4773 if (INTEL_GEN(dev_priv) >= 12) 4774 dig_port->dp.set_signal_levels = tgl_set_signal_levels; 4775 else if (INTEL_GEN(dev_priv) >= 11) 4776 dig_port->dp.set_signal_levels = icl_set_signal_levels; 4777 else if (IS_CANNONLAKE(dev_priv)) 4778 dig_port->dp.set_signal_levels = cnl_set_signal_levels; 4779 else if (IS_GEN9_LP(dev_priv)) 4780 dig_port->dp.set_signal_levels = bxt_set_signal_levels; 4781 else 4782 dig_port->dp.set_signal_levels = hsw_set_signal_levels; 4783 4784 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 4785 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 4786 4787 if (!intel_dp_init_connector(dig_port, connector)) { 4788 kfree(connector); 4789 return NULL; 4790 } 4791 4792 return connector; 4793 } 4794 4795 static int modeset_pipe(struct drm_crtc *crtc, 4796 struct drm_modeset_acquire_ctx *ctx) 4797 { 4798 struct drm_atomic_state *state; 4799 struct drm_crtc_state *crtc_state; 4800 int ret; 4801 4802 state = drm_atomic_state_alloc(crtc->dev); 4803 if (!state) 4804 return -ENOMEM; 4805 4806 state->acquire_ctx = ctx; 4807 4808 crtc_state = drm_atomic_get_crtc_state(state, crtc); 4809 if (IS_ERR(crtc_state)) { 4810 ret = PTR_ERR(crtc_state); 4811 goto out; 4812 } 4813 4814 crtc_state->connectors_changed = true; 4815 4816 ret = drm_atomic_commit(state); 4817 out: 4818 drm_atomic_state_put(state); 4819 4820 return ret; 4821 } 4822 4823 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4824 struct drm_modeset_acquire_ctx *ctx) 4825 { 4826 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4827 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4828 struct intel_connector *connector = hdmi->attached_connector; 4829 struct i2c_adapter *adapter = 4830 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 4831 struct drm_connector_state *conn_state; 4832 struct intel_crtc_state *crtc_state; 4833 struct intel_crtc *crtc; 4834 u8 config; 4835 int ret; 4836 4837 if (!connector || connector->base.status != connector_status_connected) 4838 return 0; 4839 4840 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 4841 ctx); 4842 if (ret) 4843 return ret; 4844 4845 conn_state = connector->base.state; 4846 4847 crtc = to_intel_crtc(conn_state->crtc); 4848 if (!crtc) 4849 return 0; 4850 4851 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4852 if (ret) 4853 return ret; 4854 4855 crtc_state = to_intel_crtc_state(crtc->base.state); 4856 4857 drm_WARN_ON(&dev_priv->drm, 4858 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4859 4860 if (!crtc_state->hw.active) 4861 return 0; 4862 4863 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4864 !crtc_state->hdmi_scrambling) 4865 return 0; 4866 4867 if (conn_state->commit && 4868 !try_wait_for_completion(&conn_state->commit->hw_done)) 4869 return 0; 4870 4871 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 4872 if (ret < 0) { 4873 drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n", 4874 ret); 4875 return 0; 4876 } 4877 4878 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4879 crtc_state->hdmi_high_tmds_clock_ratio && 4880 !!(config & SCDC_SCRAMBLING_ENABLE) == 4881 crtc_state->hdmi_scrambling) 4882 return 0; 4883 4884 /* 4885 * HDMI 2.0 says that one should not send scrambled data 4886 * prior to configuring the sink scrambling, and that 4887 * TMDS clock/data transmission should be suspended when 4888 * changing the TMDS clock rate in the sink. So let's 4889 * just do a full modeset here, even though some sinks 4890 * would be perfectly happy if were to just reconfigure 4891 * the SCDC settings on the fly. 4892 */ 4893 return modeset_pipe(&crtc->base, ctx); 4894 } 4895 4896 static enum intel_hotplug_state 4897 intel_ddi_hotplug(struct intel_encoder *encoder, 4898 struct intel_connector *connector) 4899 { 4900 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4901 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4902 enum phy phy = intel_port_to_phy(i915, encoder->port); 4903 bool is_tc = intel_phy_is_tc(i915, phy); 4904 struct drm_modeset_acquire_ctx ctx; 4905 enum intel_hotplug_state state; 4906 int ret; 4907 4908 state = intel_encoder_hotplug(encoder, connector); 4909 4910 drm_modeset_acquire_init(&ctx, 0); 4911 4912 for (;;) { 4913 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) 4914 ret = intel_hdmi_reset_link(encoder, &ctx); 4915 else 4916 ret = intel_dp_retrain_link(encoder, &ctx); 4917 4918 if (ret == -EDEADLK) { 4919 drm_modeset_backoff(&ctx); 4920 continue; 4921 } 4922 4923 break; 4924 } 4925 4926 drm_modeset_drop_locks(&ctx); 4927 drm_modeset_acquire_fini(&ctx); 4928 drm_WARN(encoder->base.dev, ret, 4929 "Acquiring modeset locks failed with %i\n", ret); 4930 4931 /* 4932 * Unpowered type-c dongles can take some time to boot and be 4933 * responsible, so here giving some time to those dongles to power up 4934 * and then retrying the probe. 4935 * 4936 * On many platforms the HDMI live state signal is known to be 4937 * unreliable, so we can't use it to detect if a sink is connected or 4938 * not. Instead we detect if it's connected based on whether we can 4939 * read the EDID or not. That in turn has a problem during disconnect, 4940 * since the HPD interrupt may be raised before the DDC lines get 4941 * disconnected (due to how the required length of DDC vs. HPD 4942 * connector pins are specified) and so we'll still be able to get a 4943 * valid EDID. To solve this schedule another detection cycle if this 4944 * time around we didn't detect any change in the sink's connection 4945 * status. 4946 * 4947 * Type-c connectors which get their HPD signal deasserted then 4948 * reasserted, without unplugging/replugging the sink from the 4949 * connector, introduce a delay until the AUX channel communication 4950 * becomes functional. Retry the detection for 5 seconds on type-c 4951 * connectors to account for this delay. 4952 */ 4953 if (state == INTEL_HOTPLUG_UNCHANGED && 4954 connector->hotplug_retries < (is_tc ? 5 : 1) && 4955 !dig_port->dp.is_mst) 4956 state = INTEL_HOTPLUG_RETRY; 4957 4958 return state; 4959 } 4960 4961 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4962 { 4963 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4964 u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin]; 4965 4966 return intel_de_read(dev_priv, SDEISR) & bit; 4967 } 4968 4969 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4970 { 4971 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4972 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; 4973 4974 return intel_de_read(dev_priv, DEISR) & bit; 4975 } 4976 4977 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4978 { 4979 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4980 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; 4981 4982 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; 4983 } 4984 4985 static struct intel_connector * 4986 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4987 { 4988 struct intel_connector *connector; 4989 enum port port = dig_port->base.port; 4990 4991 connector = intel_connector_alloc(); 4992 if (!connector) 4993 return NULL; 4994 4995 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4996 intel_hdmi_init_connector(dig_port, connector); 4997 4998 return connector; 4999 } 5000 5001 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 5002 { 5003 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 5004 5005 if (dig_port->base.port != PORT_A) 5006 return false; 5007 5008 if (dig_port->saved_port_bits & DDI_A_4_LANES) 5009 return false; 5010 5011 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 5012 * supported configuration 5013 */ 5014 if (IS_GEN9_LP(dev_priv)) 5015 return true; 5016 5017 /* Cannonlake: Most of SKUs don't support DDI_E, and the only 5018 * one who does also have a full A/E split called 5019 * DDI_F what makes DDI_E useless. However for this 5020 * case let's trust VBT info. 5021 */ 5022 if (IS_CANNONLAKE(dev_priv) && 5023 !intel_bios_is_port_present(dev_priv, PORT_E)) 5024 return true; 5025 5026 return false; 5027 } 5028 5029 static int 5030 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 5031 { 5032 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 5033 enum port port = dig_port->base.port; 5034 int max_lanes = 4; 5035 5036 if (INTEL_GEN(dev_priv) >= 11) 5037 return max_lanes; 5038 5039 if (port == PORT_A || port == PORT_E) { 5040 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 5041 max_lanes = port == PORT_A ? 4 : 0; 5042 else 5043 /* Both A and E share 2 lanes */ 5044 max_lanes = 2; 5045 } 5046 5047 /* 5048 * Some BIOS might fail to set this bit on port A if eDP 5049 * wasn't lit up at boot. Force this bit set when needed 5050 * so we use the proper lane count for our calculations. 5051 */ 5052 if (intel_ddi_a_force_4_lanes(dig_port)) { 5053 drm_dbg_kms(&dev_priv->drm, 5054 "Forcing DDI_A_4_LANES for port A\n"); 5055 dig_port->saved_port_bits |= DDI_A_4_LANES; 5056 max_lanes = 4; 5057 } 5058 5059 return max_lanes; 5060 } 5061 5062 static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy) 5063 { 5064 return i915->hti_state & HDPORT_ENABLED && 5065 (i915->hti_state & HDPORT_PHY_USED_DP(phy) || 5066 i915->hti_state & HDPORT_PHY_USED_HDMI(phy)); 5067 } 5068 5069 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, 5070 enum port port) 5071 { 5072 if (port >= PORT_TC1) 5073 return HPD_PORT_C + port - PORT_TC1; 5074 else 5075 return HPD_PORT_A + port - PORT_A; 5076 } 5077 5078 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, 5079 enum port port) 5080 { 5081 if (port >= PORT_TC1) 5082 return HPD_PORT_TC1 + port - PORT_TC1; 5083 else 5084 return HPD_PORT_A + port - PORT_A; 5085 } 5086 5087 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, 5088 enum port port) 5089 { 5090 if (HAS_PCH_TGP(dev_priv)) 5091 return tgl_hpd_pin(dev_priv, port); 5092 5093 if (port >= PORT_TC1) 5094 return HPD_PORT_C + port - PORT_TC1; 5095 else 5096 return HPD_PORT_A + port - PORT_A; 5097 } 5098 5099 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, 5100 enum port port) 5101 { 5102 if (port >= PORT_C) 5103 return HPD_PORT_TC1 + port - PORT_C; 5104 else 5105 return HPD_PORT_A + port - PORT_A; 5106 } 5107 5108 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, 5109 enum port port) 5110 { 5111 if (port == PORT_D) 5112 return HPD_PORT_A; 5113 5114 if (HAS_PCH_MCC(dev_priv)) 5115 return icl_hpd_pin(dev_priv, port); 5116 5117 return HPD_PORT_A + port - PORT_A; 5118 } 5119 5120 static enum hpd_pin cnl_hpd_pin(struct drm_i915_private *dev_priv, 5121 enum port port) 5122 { 5123 if (port == PORT_F) 5124 return HPD_PORT_E; 5125 5126 return HPD_PORT_A + port - PORT_A; 5127 } 5128 5129 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 5130 { 5131 struct intel_digital_port *dig_port; 5132 struct intel_encoder *encoder; 5133 bool init_hdmi, init_dp; 5134 enum phy phy = intel_port_to_phy(dev_priv, port); 5135 5136 /* 5137 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 5138 * have taken over some of the PHYs and made them unavailable to the 5139 * driver. In that case we should skip initializing the corresponding 5140 * outputs. 5141 */ 5142 if (hti_uses_phy(dev_priv, phy)) { 5143 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", 5144 port_name(port), phy_name(phy)); 5145 return; 5146 } 5147 5148 init_hdmi = intel_bios_port_supports_dvi(dev_priv, port) || 5149 intel_bios_port_supports_hdmi(dev_priv, port); 5150 init_dp = intel_bios_port_supports_dp(dev_priv, port); 5151 5152 if (intel_bios_is_lspcon_present(dev_priv, port)) { 5153 /* 5154 * Lspcon device needs to be driven with DP connector 5155 * with special detection sequence. So make sure DP 5156 * is initialized before lspcon. 5157 */ 5158 init_dp = true; 5159 init_hdmi = false; 5160 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", 5161 port_name(port)); 5162 } 5163 5164 if (!init_dp && !init_hdmi) { 5165 drm_dbg_kms(&dev_priv->drm, 5166 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 5167 port_name(port)); 5168 return; 5169 } 5170 5171 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 5172 if (!dig_port) 5173 return; 5174 5175 encoder = &dig_port->base; 5176 5177 if (INTEL_GEN(dev_priv) >= 12) { 5178 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 5179 5180 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 5181 DRM_MODE_ENCODER_TMDS, 5182 "DDI %s%c/PHY %s%c", 5183 port >= PORT_TC1 ? "TC" : "", 5184 port >= PORT_TC1 ? port_name(port) : port - PORT_TC1 + '1', 5185 tc_port != TC_PORT_NONE ? "TC" : "", 5186 tc_port != TC_PORT_NONE ? phy_name(phy) : tc_port - TC_PORT_1 + '1'); 5187 } else if (INTEL_GEN(dev_priv) >= 11) { 5188 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 5189 5190 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 5191 DRM_MODE_ENCODER_TMDS, 5192 "DDI %c%s/PHY %s%c", 5193 port_name(port), 5194 port >= PORT_C ? " (TC)" : "", 5195 tc_port != TC_PORT_NONE ? "TC" : "", 5196 tc_port != TC_PORT_NONE ? phy_name(phy) : tc_port - TC_PORT_1 + '1'); 5197 } else { 5198 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 5199 DRM_MODE_ENCODER_TMDS, 5200 "DDI %c/PHY %c", port_name(port), phy_name(phy)); 5201 } 5202 5203 mutex_init(&dig_port->hdcp_mutex); 5204 dig_port->num_hdcp_streams = 0; 5205 5206 encoder->hotplug = intel_ddi_hotplug; 5207 encoder->compute_output_type = intel_ddi_compute_output_type; 5208 encoder->compute_config = intel_ddi_compute_config; 5209 encoder->compute_config_late = intel_ddi_compute_config_late; 5210 encoder->enable = intel_enable_ddi; 5211 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 5212 encoder->pre_enable = intel_ddi_pre_enable; 5213 encoder->disable = intel_disable_ddi; 5214 encoder->post_disable = intel_ddi_post_disable; 5215 encoder->update_pipe = intel_ddi_update_pipe; 5216 encoder->get_hw_state = intel_ddi_get_hw_state; 5217 encoder->get_config = intel_ddi_get_config; 5218 encoder->sync_state = intel_ddi_sync_state; 5219 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 5220 encoder->suspend = intel_dp_encoder_suspend; 5221 encoder->shutdown = intel_dp_encoder_shutdown; 5222 encoder->get_power_domains = intel_ddi_get_power_domains; 5223 5224 encoder->type = INTEL_OUTPUT_DDI; 5225 encoder->power_domain = intel_port_to_power_domain(port); 5226 encoder->port = port; 5227 encoder->cloneable = 0; 5228 encoder->pipe_mask = ~0; 5229 5230 if (IS_DG1(dev_priv)) 5231 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); 5232 else if (IS_ROCKETLAKE(dev_priv)) 5233 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); 5234 else if (INTEL_GEN(dev_priv) >= 12) 5235 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); 5236 else if (IS_JSL_EHL(dev_priv)) 5237 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); 5238 else if (IS_GEN(dev_priv, 11)) 5239 encoder->hpd_pin = icl_hpd_pin(dev_priv, port); 5240 else if (IS_GEN(dev_priv, 10)) 5241 encoder->hpd_pin = cnl_hpd_pin(dev_priv, port); 5242 else 5243 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 5244 5245 if (INTEL_GEN(dev_priv) >= 11) 5246 dig_port->saved_port_bits = 5247 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 5248 & DDI_BUF_PORT_REVERSAL; 5249 else 5250 dig_port->saved_port_bits = 5251 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 5252 & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 5253 5254 dig_port->dp.output_reg = INVALID_MMIO_REG; 5255 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 5256 dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 5257 5258 if (intel_phy_is_tc(dev_priv, phy)) { 5259 bool is_legacy = 5260 !intel_bios_port_supports_typec_usb(dev_priv, port) && 5261 !intel_bios_port_supports_tbt(dev_priv, port); 5262 5263 intel_tc_port_init(dig_port, is_legacy); 5264 5265 encoder->update_prepare = intel_ddi_update_prepare; 5266 encoder->update_complete = intel_ddi_update_complete; 5267 } 5268 5269 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 5270 dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO + 5271 port - PORT_A; 5272 5273 if (init_dp) { 5274 if (!intel_ddi_init_dp_connector(dig_port)) 5275 goto err; 5276 5277 dig_port->hpd_pulse = intel_dp_hpd_pulse; 5278 } 5279 5280 /* In theory we don't need the encoder->type check, but leave it just in 5281 * case we have some really bad VBTs... */ 5282 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 5283 if (!intel_ddi_init_hdmi_connector(dig_port)) 5284 goto err; 5285 } 5286 5287 if (INTEL_GEN(dev_priv) >= 11) { 5288 if (intel_phy_is_tc(dev_priv, phy)) 5289 dig_port->connected = intel_tc_port_connected; 5290 else 5291 dig_port->connected = lpt_digital_port_connected; 5292 } else if (INTEL_GEN(dev_priv) >= 8) { 5293 if (port == PORT_A || IS_GEN9_LP(dev_priv)) 5294 dig_port->connected = bdw_digital_port_connected; 5295 else 5296 dig_port->connected = lpt_digital_port_connected; 5297 } else { 5298 if (port == PORT_A) 5299 dig_port->connected = hsw_digital_port_connected; 5300 else 5301 dig_port->connected = lpt_digital_port_connected; 5302 } 5303 5304 intel_infoframe_init(dig_port); 5305 5306 return; 5307 5308 err: 5309 drm_encoder_cleanup(&encoder->base); 5310 kfree(dig_port); 5311 } 5312