1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <drm/drm_scdc_helper.h> 29 30 #include "i915_drv.h" 31 #include "intel_audio.h" 32 #include "intel_combo_phy.h" 33 #include "intel_connector.h" 34 #include "intel_crtc.h" 35 #include "intel_ddi.h" 36 #include "intel_ddi_buf_trans.h" 37 #include "intel_de.h" 38 #include "intel_display_types.h" 39 #include "intel_dp.h" 40 #include "intel_dp_link_training.h" 41 #include "intel_dp_mst.h" 42 #include "intel_dpio_phy.h" 43 #include "intel_dsi.h" 44 #include "intel_fdi.h" 45 #include "intel_fifo_underrun.h" 46 #include "intel_gmbus.h" 47 #include "intel_hdcp.h" 48 #include "intel_hdmi.h" 49 #include "intel_hotplug.h" 50 #include "intel_lspcon.h" 51 #include "intel_panel.h" 52 #include "intel_pps.h" 53 #include "intel_psr.h" 54 #include "intel_sprite.h" 55 #include "intel_tc.h" 56 #include "intel_vdsc.h" 57 #include "intel_vrr.h" 58 #include "skl_scaler.h" 59 #include "skl_universal_plane.h" 60 61 static const u8 index_to_dp_signal_levels[] = { 62 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 63 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 64 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 65 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 66 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 67 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 68 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 69 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 70 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 71 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 72 }; 73 74 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 75 const struct intel_crtc_state *crtc_state) 76 { 77 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 78 int n_entries, level, default_entry; 79 80 n_entries = intel_ddi_hdmi_num_entries(encoder, crtc_state, &default_entry); 81 if (n_entries == 0) 82 return 0; 83 level = intel_bios_hdmi_level_shift(encoder); 84 if (level < 0) 85 level = default_entry; 86 87 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 88 level = n_entries - 1; 89 90 return level; 91 } 92 93 /* 94 * Starting with Haswell, DDI port buffers must be programmed with correct 95 * values in advance. This function programs the correct values for 96 * DP/eDP/FDI use cases. 97 */ 98 void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 99 const struct intel_crtc_state *crtc_state) 100 { 101 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 102 u32 iboost_bit = 0; 103 int i, n_entries; 104 enum port port = encoder->port; 105 const struct ddi_buf_trans *ddi_translations; 106 107 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) 108 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv, 109 &n_entries); 110 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 111 ddi_translations = intel_ddi_get_buf_trans_edp(encoder, 112 &n_entries); 113 else 114 ddi_translations = intel_ddi_get_buf_trans_dp(encoder, 115 &n_entries); 116 117 /* If we're boosting the current, set bit 31 of trans1 */ 118 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) && 119 intel_bios_encoder_dp_boost_level(encoder->devdata)) 120 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 121 122 for (i = 0; i < n_entries; i++) { 123 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 124 ddi_translations[i].trans1 | iboost_bit); 125 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 126 ddi_translations[i].trans2); 127 } 128 } 129 130 /* 131 * Starting with Haswell, DDI port buffers must be programmed with correct 132 * values in advance. This function programs the correct values for 133 * HDMI/DVI use cases. 134 */ 135 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 136 int level) 137 { 138 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 139 u32 iboost_bit = 0; 140 int n_entries; 141 enum port port = encoder->port; 142 const struct ddi_buf_trans *ddi_translations; 143 144 ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); 145 146 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 147 return; 148 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 149 level = n_entries - 1; 150 151 /* If we're boosting the current, set bit 31 of trans1 */ 152 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) && 153 intel_bios_encoder_hdmi_boost_level(encoder->devdata)) 154 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 155 156 /* Entry 9 is for HDMI: */ 157 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 158 ddi_translations[level].trans1 | iboost_bit); 159 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 160 ddi_translations[level].trans2); 161 } 162 163 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 164 enum port port) 165 { 166 if (IS_BROXTON(dev_priv)) { 167 udelay(16); 168 return; 169 } 170 171 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 172 DDI_BUF_IS_IDLE), 8)) 173 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", 174 port_name(port)); 175 } 176 177 static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, 178 enum port port) 179 { 180 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ 181 if (DISPLAY_VER(dev_priv) < 10) { 182 usleep_range(518, 1000); 183 return; 184 } 185 186 if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 187 DDI_BUF_IS_IDLE), 500)) 188 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", 189 port_name(port)); 190 } 191 192 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 193 { 194 switch (pll->info->id) { 195 case DPLL_ID_WRPLL1: 196 return PORT_CLK_SEL_WRPLL1; 197 case DPLL_ID_WRPLL2: 198 return PORT_CLK_SEL_WRPLL2; 199 case DPLL_ID_SPLL: 200 return PORT_CLK_SEL_SPLL; 201 case DPLL_ID_LCPLL_810: 202 return PORT_CLK_SEL_LCPLL_810; 203 case DPLL_ID_LCPLL_1350: 204 return PORT_CLK_SEL_LCPLL_1350; 205 case DPLL_ID_LCPLL_2700: 206 return PORT_CLK_SEL_LCPLL_2700; 207 default: 208 MISSING_CASE(pll->info->id); 209 return PORT_CLK_SEL_NONE; 210 } 211 } 212 213 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 214 const struct intel_crtc_state *crtc_state) 215 { 216 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 217 int clock = crtc_state->port_clock; 218 const enum intel_dpll_id id = pll->info->id; 219 220 switch (id) { 221 default: 222 /* 223 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 224 * here, so do warn if this get passed in 225 */ 226 MISSING_CASE(id); 227 return DDI_CLK_SEL_NONE; 228 case DPLL_ID_ICL_TBTPLL: 229 switch (clock) { 230 case 162000: 231 return DDI_CLK_SEL_TBT_162; 232 case 270000: 233 return DDI_CLK_SEL_TBT_270; 234 case 540000: 235 return DDI_CLK_SEL_TBT_540; 236 case 810000: 237 return DDI_CLK_SEL_TBT_810; 238 default: 239 MISSING_CASE(clock); 240 return DDI_CLK_SEL_NONE; 241 } 242 case DPLL_ID_ICL_MGPLL1: 243 case DPLL_ID_ICL_MGPLL2: 244 case DPLL_ID_ICL_MGPLL3: 245 case DPLL_ID_ICL_MGPLL4: 246 case DPLL_ID_TGL_MGPLL5: 247 case DPLL_ID_TGL_MGPLL6: 248 return DDI_CLK_SEL_MG; 249 } 250 } 251 252 static u32 ddi_buf_phy_link_rate(int port_clock) 253 { 254 switch (port_clock) { 255 case 162000: 256 return DDI_BUF_PHY_LINK_RATE(0); 257 case 216000: 258 return DDI_BUF_PHY_LINK_RATE(4); 259 case 243000: 260 return DDI_BUF_PHY_LINK_RATE(5); 261 case 270000: 262 return DDI_BUF_PHY_LINK_RATE(1); 263 case 324000: 264 return DDI_BUF_PHY_LINK_RATE(6); 265 case 432000: 266 return DDI_BUF_PHY_LINK_RATE(7); 267 case 540000: 268 return DDI_BUF_PHY_LINK_RATE(2); 269 case 810000: 270 return DDI_BUF_PHY_LINK_RATE(3); 271 default: 272 MISSING_CASE(port_clock); 273 return DDI_BUF_PHY_LINK_RATE(0); 274 } 275 } 276 277 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 278 const struct intel_crtc_state *crtc_state) 279 { 280 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 281 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 282 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 283 enum phy phy = intel_port_to_phy(i915, encoder->port); 284 285 intel_dp->DP = dig_port->saved_port_bits | 286 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); 287 intel_dp->DP |= DDI_PORT_WIDTH(crtc_state->lane_count); 288 289 if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) { 290 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 291 if (dig_port->tc_mode != TC_PORT_TBT_ALT) 292 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 293 } 294 } 295 296 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 297 enum port port) 298 { 299 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 300 301 switch (val) { 302 case DDI_CLK_SEL_NONE: 303 return 0; 304 case DDI_CLK_SEL_TBT_162: 305 return 162000; 306 case DDI_CLK_SEL_TBT_270: 307 return 270000; 308 case DDI_CLK_SEL_TBT_540: 309 return 540000; 310 case DDI_CLK_SEL_TBT_810: 311 return 810000; 312 default: 313 MISSING_CASE(val); 314 return 0; 315 } 316 } 317 318 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 319 { 320 int dotclock; 321 322 if (pipe_config->has_pch_encoder) 323 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 324 &pipe_config->fdi_m_n); 325 else if (intel_crtc_has_dp_encoder(pipe_config)) 326 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 327 &pipe_config->dp_m_n); 328 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) 329 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp; 330 else 331 dotclock = pipe_config->port_clock; 332 333 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 334 !intel_crtc_has_dp_encoder(pipe_config)) 335 dotclock *= 2; 336 337 if (pipe_config->pixel_multiplier) 338 dotclock /= pipe_config->pixel_multiplier; 339 340 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 341 } 342 343 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 344 const struct drm_connector_state *conn_state) 345 { 346 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 347 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 348 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 349 u32 temp; 350 351 if (!intel_crtc_has_dp_encoder(crtc_state)) 352 return; 353 354 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 355 356 temp = DP_MSA_MISC_SYNC_CLOCK; 357 358 switch (crtc_state->pipe_bpp) { 359 case 18: 360 temp |= DP_MSA_MISC_6_BPC; 361 break; 362 case 24: 363 temp |= DP_MSA_MISC_8_BPC; 364 break; 365 case 30: 366 temp |= DP_MSA_MISC_10_BPC; 367 break; 368 case 36: 369 temp |= DP_MSA_MISC_12_BPC; 370 break; 371 default: 372 MISSING_CASE(crtc_state->pipe_bpp); 373 break; 374 } 375 376 /* nonsense combination */ 377 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 378 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 379 380 if (crtc_state->limited_color_range) 381 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 382 383 /* 384 * As per DP 1.2 spec section 2.3.4.3 while sending 385 * YCBCR 444 signals we should program MSA MISC1/0 fields with 386 * colorspace information. 387 */ 388 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 389 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 390 391 /* 392 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 393 * of Color Encoding Format and Content Color Gamut] while sending 394 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 395 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 396 */ 397 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 398 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 399 400 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp); 401 } 402 403 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 404 { 405 if (master_transcoder == TRANSCODER_EDP) 406 return 0; 407 else 408 return master_transcoder + 1; 409 } 410 411 /* 412 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 413 * 414 * Only intended to be used by intel_ddi_enable_transcoder_func() and 415 * intel_ddi_config_transcoder_func(). 416 */ 417 static u32 418 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 419 const struct intel_crtc_state *crtc_state) 420 { 421 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 422 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 423 enum pipe pipe = crtc->pipe; 424 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 425 enum port port = encoder->port; 426 u32 temp; 427 428 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 429 temp = TRANS_DDI_FUNC_ENABLE; 430 if (DISPLAY_VER(dev_priv) >= 12) 431 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 432 else 433 temp |= TRANS_DDI_SELECT_PORT(port); 434 435 switch (crtc_state->pipe_bpp) { 436 case 18: 437 temp |= TRANS_DDI_BPC_6; 438 break; 439 case 24: 440 temp |= TRANS_DDI_BPC_8; 441 break; 442 case 30: 443 temp |= TRANS_DDI_BPC_10; 444 break; 445 case 36: 446 temp |= TRANS_DDI_BPC_12; 447 break; 448 default: 449 BUG(); 450 } 451 452 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 453 temp |= TRANS_DDI_PVSYNC; 454 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 455 temp |= TRANS_DDI_PHSYNC; 456 457 if (cpu_transcoder == TRANSCODER_EDP) { 458 switch (pipe) { 459 case PIPE_A: 460 /* On Haswell, can only use the always-on power well for 461 * eDP when not using the panel fitter, and when not 462 * using motion blur mitigation (which we don't 463 * support). */ 464 if (crtc_state->pch_pfit.force_thru) 465 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 466 else 467 temp |= TRANS_DDI_EDP_INPUT_A_ON; 468 break; 469 case PIPE_B: 470 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 471 break; 472 case PIPE_C: 473 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 474 break; 475 default: 476 BUG(); 477 break; 478 } 479 } 480 481 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 482 if (crtc_state->has_hdmi_sink) 483 temp |= TRANS_DDI_MODE_SELECT_HDMI; 484 else 485 temp |= TRANS_DDI_MODE_SELECT_DVI; 486 487 if (crtc_state->hdmi_scrambling) 488 temp |= TRANS_DDI_HDMI_SCRAMBLING; 489 if (crtc_state->hdmi_high_tmds_clock_ratio) 490 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 491 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 492 temp |= TRANS_DDI_MODE_SELECT_FDI; 493 temp |= (crtc_state->fdi_lanes - 1) << 1; 494 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 495 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 496 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 497 498 if (DISPLAY_VER(dev_priv) >= 12) { 499 enum transcoder master; 500 501 master = crtc_state->mst_master_transcoder; 502 drm_WARN_ON(&dev_priv->drm, 503 master == INVALID_TRANSCODER); 504 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 505 } 506 } else { 507 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 508 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 509 } 510 511 if (IS_DISPLAY_VER(dev_priv, 8, 10) && 512 crtc_state->master_transcoder != INVALID_TRANSCODER) { 513 u8 master_select = 514 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 515 516 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 517 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 518 } 519 520 return temp; 521 } 522 523 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 524 const struct intel_crtc_state *crtc_state) 525 { 526 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 527 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 528 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 529 530 if (DISPLAY_VER(dev_priv) >= 11) { 531 enum transcoder master_transcoder = crtc_state->master_transcoder; 532 u32 ctl2 = 0; 533 534 if (master_transcoder != INVALID_TRANSCODER) { 535 u8 master_select = 536 bdw_trans_port_sync_master_select(master_transcoder); 537 538 ctl2 |= PORT_SYNC_MODE_ENABLE | 539 PORT_SYNC_MODE_MASTER_SELECT(master_select); 540 } 541 542 intel_de_write(dev_priv, 543 TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2); 544 } 545 546 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 547 intel_ddi_transcoder_func_reg_val_get(encoder, 548 crtc_state)); 549 } 550 551 /* 552 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 553 * bit. 554 */ 555 static void 556 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 557 const struct intel_crtc_state *crtc_state) 558 { 559 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 560 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 561 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 562 u32 ctl; 563 564 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 565 ctl &= ~TRANS_DDI_FUNC_ENABLE; 566 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 567 } 568 569 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 570 { 571 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 572 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 573 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 574 u32 ctl; 575 576 if (DISPLAY_VER(dev_priv) >= 11) 577 intel_de_write(dev_priv, 578 TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0); 579 580 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 581 582 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 583 584 ctl &= ~TRANS_DDI_FUNC_ENABLE; 585 586 if (IS_DISPLAY_VER(dev_priv, 8, 10)) 587 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 588 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 589 590 if (DISPLAY_VER(dev_priv) >= 12) { 591 if (!intel_dp_mst_is_master_trans(crtc_state)) { 592 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 593 TRANS_DDI_MODE_SELECT_MASK); 594 } 595 } else { 596 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 597 } 598 599 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 600 601 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME && 602 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 603 drm_dbg_kms(&dev_priv->drm, 604 "Quirk Increase DDI disabled time\n"); 605 /* Quirk time at 100ms for reliable operation */ 606 msleep(100); 607 } 608 } 609 610 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 611 enum transcoder cpu_transcoder, 612 bool enable, u32 hdcp_mask) 613 { 614 struct drm_device *dev = intel_encoder->base.dev; 615 struct drm_i915_private *dev_priv = to_i915(dev); 616 intel_wakeref_t wakeref; 617 int ret = 0; 618 u32 tmp; 619 620 wakeref = intel_display_power_get_if_enabled(dev_priv, 621 intel_encoder->power_domain); 622 if (drm_WARN_ON(dev, !wakeref)) 623 return -ENXIO; 624 625 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 626 if (enable) 627 tmp |= hdcp_mask; 628 else 629 tmp &= ~hdcp_mask; 630 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp); 631 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 632 return ret; 633 } 634 635 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 636 { 637 struct drm_device *dev = intel_connector->base.dev; 638 struct drm_i915_private *dev_priv = to_i915(dev); 639 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 640 int type = intel_connector->base.connector_type; 641 enum port port = encoder->port; 642 enum transcoder cpu_transcoder; 643 intel_wakeref_t wakeref; 644 enum pipe pipe = 0; 645 u32 tmp; 646 bool ret; 647 648 wakeref = intel_display_power_get_if_enabled(dev_priv, 649 encoder->power_domain); 650 if (!wakeref) 651 return false; 652 653 if (!encoder->get_hw_state(encoder, &pipe)) { 654 ret = false; 655 goto out; 656 } 657 658 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 659 cpu_transcoder = TRANSCODER_EDP; 660 else 661 cpu_transcoder = (enum transcoder) pipe; 662 663 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 664 665 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 666 case TRANS_DDI_MODE_SELECT_HDMI: 667 case TRANS_DDI_MODE_SELECT_DVI: 668 ret = type == DRM_MODE_CONNECTOR_HDMIA; 669 break; 670 671 case TRANS_DDI_MODE_SELECT_DP_SST: 672 ret = type == DRM_MODE_CONNECTOR_eDP || 673 type == DRM_MODE_CONNECTOR_DisplayPort; 674 break; 675 676 case TRANS_DDI_MODE_SELECT_DP_MST: 677 /* if the transcoder is in MST state then 678 * connector isn't connected */ 679 ret = false; 680 break; 681 682 case TRANS_DDI_MODE_SELECT_FDI: 683 ret = type == DRM_MODE_CONNECTOR_VGA; 684 break; 685 686 default: 687 ret = false; 688 break; 689 } 690 691 out: 692 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 693 694 return ret; 695 } 696 697 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 698 u8 *pipe_mask, bool *is_dp_mst) 699 { 700 struct drm_device *dev = encoder->base.dev; 701 struct drm_i915_private *dev_priv = to_i915(dev); 702 enum port port = encoder->port; 703 intel_wakeref_t wakeref; 704 enum pipe p; 705 u32 tmp; 706 u8 mst_pipe_mask; 707 708 *pipe_mask = 0; 709 *is_dp_mst = false; 710 711 wakeref = intel_display_power_get_if_enabled(dev_priv, 712 encoder->power_domain); 713 if (!wakeref) 714 return; 715 716 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 717 if (!(tmp & DDI_BUF_CTL_ENABLE)) 718 goto out; 719 720 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { 721 tmp = intel_de_read(dev_priv, 722 TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 723 724 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 725 default: 726 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 727 fallthrough; 728 case TRANS_DDI_EDP_INPUT_A_ON: 729 case TRANS_DDI_EDP_INPUT_A_ONOFF: 730 *pipe_mask = BIT(PIPE_A); 731 break; 732 case TRANS_DDI_EDP_INPUT_B_ONOFF: 733 *pipe_mask = BIT(PIPE_B); 734 break; 735 case TRANS_DDI_EDP_INPUT_C_ONOFF: 736 *pipe_mask = BIT(PIPE_C); 737 break; 738 } 739 740 goto out; 741 } 742 743 mst_pipe_mask = 0; 744 for_each_pipe(dev_priv, p) { 745 enum transcoder cpu_transcoder = (enum transcoder)p; 746 unsigned int port_mask, ddi_select; 747 intel_wakeref_t trans_wakeref; 748 749 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 750 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 751 if (!trans_wakeref) 752 continue; 753 754 if (DISPLAY_VER(dev_priv) >= 12) { 755 port_mask = TGL_TRANS_DDI_PORT_MASK; 756 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 757 } else { 758 port_mask = TRANS_DDI_PORT_MASK; 759 ddi_select = TRANS_DDI_SELECT_PORT(port); 760 } 761 762 tmp = intel_de_read(dev_priv, 763 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 764 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 765 trans_wakeref); 766 767 if ((tmp & port_mask) != ddi_select) 768 continue; 769 770 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == 771 TRANS_DDI_MODE_SELECT_DP_MST) 772 mst_pipe_mask |= BIT(p); 773 774 *pipe_mask |= BIT(p); 775 } 776 777 if (!*pipe_mask) 778 drm_dbg_kms(&dev_priv->drm, 779 "No pipe for [ENCODER:%d:%s] found\n", 780 encoder->base.base.id, encoder->base.name); 781 782 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 783 drm_dbg_kms(&dev_priv->drm, 784 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 785 encoder->base.base.id, encoder->base.name, 786 *pipe_mask); 787 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 788 } 789 790 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 791 drm_dbg_kms(&dev_priv->drm, 792 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", 793 encoder->base.base.id, encoder->base.name, 794 *pipe_mask, mst_pipe_mask); 795 else 796 *is_dp_mst = mst_pipe_mask; 797 798 out: 799 if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) { 800 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 801 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 802 BXT_PHY_LANE_POWERDOWN_ACK | 803 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 804 drm_err(&dev_priv->drm, 805 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 806 encoder->base.base.id, encoder->base.name, tmp); 807 } 808 809 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 810 } 811 812 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 813 enum pipe *pipe) 814 { 815 u8 pipe_mask; 816 bool is_mst; 817 818 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 819 820 if (is_mst || !pipe_mask) 821 return false; 822 823 *pipe = ffs(pipe_mask) - 1; 824 825 return true; 826 } 827 828 static enum intel_display_power_domain 829 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port) 830 { 831 /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with 832 * DC states enabled at the same time, while for driver initiated AUX 833 * transfers we need the same AUX IOs to be powered but with DC states 834 * disabled. Accordingly use the AUX power domain here which leaves DC 835 * states enabled. 836 * However, for non-A AUX ports the corresponding non-EDP transcoders 837 * would have already enabled power well 2 and DC_OFF. This means we can 838 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a 839 * specific AUX_IO reference without powering up any extra wells. 840 * Note that PSR is enabled only on Port A even though this function 841 * returns the correct domain for other ports too. 842 */ 843 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A : 844 intel_aux_power_domain(dig_port); 845 } 846 847 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 848 struct intel_crtc_state *crtc_state) 849 { 850 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 851 struct intel_digital_port *dig_port; 852 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 853 854 /* 855 * TODO: Add support for MST encoders. Atm, the following should never 856 * happen since fake-MST encoders don't set their get_power_domains() 857 * hook. 858 */ 859 if (drm_WARN_ON(&dev_priv->drm, 860 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 861 return; 862 863 dig_port = enc_to_dig_port(encoder); 864 865 if (!intel_phy_is_tc(dev_priv, phy) || 866 dig_port->tc_mode != TC_PORT_TBT_ALT) { 867 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 868 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 869 dig_port->ddi_io_power_domain); 870 } 871 872 /* 873 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC 874 * ports. 875 */ 876 if (intel_crtc_has_dp_encoder(crtc_state) || 877 intel_phy_is_tc(dev_priv, phy)) { 878 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref); 879 dig_port->aux_wakeref = 880 intel_display_power_get(dev_priv, 881 intel_ddi_main_link_aux_domain(dig_port)); 882 } 883 } 884 885 void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder, 886 const struct intel_crtc_state *crtc_state) 887 { 888 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 889 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 890 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 891 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 892 u32 val; 893 894 if (cpu_transcoder != TRANSCODER_EDP) { 895 if (DISPLAY_VER(dev_priv) >= 13) 896 val = TGL_TRANS_CLK_SEL_PORT(phy); 897 else if (DISPLAY_VER(dev_priv) >= 12) 898 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 899 else 900 val = TRANS_CLK_SEL_PORT(encoder->port); 901 902 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 903 } 904 } 905 906 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state) 907 { 908 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 909 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 910 911 if (cpu_transcoder != TRANSCODER_EDP) { 912 if (DISPLAY_VER(dev_priv) >= 12) 913 intel_de_write(dev_priv, 914 TRANS_CLK_SEL(cpu_transcoder), 915 TGL_TRANS_CLK_SEL_DISABLED); 916 else 917 intel_de_write(dev_priv, 918 TRANS_CLK_SEL(cpu_transcoder), 919 TRANS_CLK_SEL_DISABLED); 920 } 921 } 922 923 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 924 enum port port, u8 iboost) 925 { 926 u32 tmp; 927 928 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 929 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 930 if (iboost) 931 tmp |= iboost << BALANCE_LEG_SHIFT(port); 932 else 933 tmp |= BALANCE_LEG_DISABLE(port); 934 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 935 } 936 937 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 938 const struct intel_crtc_state *crtc_state, 939 int level) 940 { 941 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 942 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 943 u8 iboost; 944 945 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 946 iboost = intel_bios_encoder_hdmi_boost_level(encoder->devdata); 947 else 948 iboost = intel_bios_encoder_dp_boost_level(encoder->devdata); 949 950 if (iboost == 0) { 951 const struct ddi_buf_trans *ddi_translations; 952 int n_entries; 953 954 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 955 ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); 956 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 957 ddi_translations = intel_ddi_get_buf_trans_edp(encoder, &n_entries); 958 else 959 ddi_translations = intel_ddi_get_buf_trans_dp(encoder, &n_entries); 960 961 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 962 return; 963 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 964 level = n_entries - 1; 965 966 iboost = ddi_translations[level].i_boost; 967 } 968 969 /* Make sure that the requested I_boost is valid */ 970 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 971 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); 972 return; 973 } 974 975 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); 976 977 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 978 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 979 } 980 981 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, 982 const struct intel_crtc_state *crtc_state, 983 int level) 984 { 985 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 986 const struct bxt_ddi_buf_trans *ddi_translations; 987 enum port port = encoder->port; 988 int n_entries; 989 990 ddi_translations = bxt_get_buf_trans(encoder, crtc_state, &n_entries); 991 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 992 return; 993 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 994 level = n_entries - 1; 995 996 bxt_ddi_phy_set_signal_level(dev_priv, port, 997 ddi_translations[level].margin, 998 ddi_translations[level].scale, 999 ddi_translations[level].enable, 1000 ddi_translations[level].deemphasis); 1001 } 1002 1003 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1004 const struct intel_crtc_state *crtc_state) 1005 { 1006 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1007 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1008 enum port port = encoder->port; 1009 enum phy phy = intel_port_to_phy(dev_priv, port); 1010 int n_entries; 1011 1012 if (DISPLAY_VER(dev_priv) >= 12) { 1013 if (intel_phy_is_combo(dev_priv, phy)) 1014 tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries); 1015 else if (IS_ALDERLAKE_P(dev_priv)) 1016 adlp_get_dkl_buf_trans(encoder, crtc_state, &n_entries); 1017 else 1018 tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries); 1019 } else if (DISPLAY_VER(dev_priv) == 11) { 1020 if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)) 1021 jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries); 1022 else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) 1023 ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries); 1024 else if (intel_phy_is_combo(dev_priv, phy)) 1025 icl_get_combo_buf_trans(encoder, crtc_state, &n_entries); 1026 else 1027 icl_get_mg_buf_trans(encoder, crtc_state, &n_entries); 1028 } else if (IS_CANNONLAKE(dev_priv)) { 1029 cnl_get_buf_trans(encoder, crtc_state, &n_entries); 1030 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 1031 bxt_get_buf_trans(encoder, crtc_state, &n_entries); 1032 } else { 1033 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1034 intel_ddi_get_buf_trans_edp(encoder, &n_entries); 1035 else 1036 intel_ddi_get_buf_trans_dp(encoder, &n_entries); 1037 } 1038 1039 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 1040 n_entries = 1; 1041 if (drm_WARN_ON(&dev_priv->drm, 1042 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1043 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1044 1045 return index_to_dp_signal_levels[n_entries - 1] & 1046 DP_TRAIN_VOLTAGE_SWING_MASK; 1047 } 1048 1049 /* 1050 * We assume that the full set of pre-emphasis values can be 1051 * used on all DDI platforms. Should that change we need to 1052 * rethink this code. 1053 */ 1054 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1055 { 1056 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1057 } 1058 1059 static void cnl_ddi_vswing_program(struct intel_encoder *encoder, 1060 const struct intel_crtc_state *crtc_state, 1061 int level) 1062 { 1063 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1064 const struct cnl_ddi_buf_trans *ddi_translations; 1065 enum port port = encoder->port; 1066 int n_entries, ln; 1067 u32 val; 1068 1069 ddi_translations = cnl_get_buf_trans(encoder, crtc_state, &n_entries); 1070 1071 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 1072 return; 1073 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 1074 level = n_entries - 1; 1075 1076 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */ 1077 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 1078 val &= ~SCALING_MODE_SEL_MASK; 1079 val |= SCALING_MODE_SEL(2); 1080 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 1081 1082 /* Program PORT_TX_DW2 */ 1083 val = intel_de_read(dev_priv, CNL_PORT_TX_DW2_LN0(port)); 1084 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 1085 RCOMP_SCALAR_MASK); 1086 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); 1087 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); 1088 /* Rcomp scalar is fixed as 0x98 for every table entry */ 1089 val |= RCOMP_SCALAR(0x98); 1090 intel_de_write(dev_priv, CNL_PORT_TX_DW2_GRP(port), val); 1091 1092 /* Program PORT_TX_DW4 */ 1093 /* We cannot write to GRP. It would overrite individual loadgen */ 1094 for (ln = 0; ln < 4; ln++) { 1095 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port)); 1096 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 1097 CURSOR_COEFF_MASK); 1098 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); 1099 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); 1100 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); 1101 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val); 1102 } 1103 1104 /* Program PORT_TX_DW5 */ 1105 /* All DW5 values are fixed for every table entry */ 1106 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 1107 val &= ~RTERM_SELECT_MASK; 1108 val |= RTERM_SELECT(6); 1109 val |= TAP3_DISABLE; 1110 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 1111 1112 /* Program PORT_TX_DW7 */ 1113 val = intel_de_read(dev_priv, CNL_PORT_TX_DW7_LN0(port)); 1114 val &= ~N_SCALAR_MASK; 1115 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); 1116 intel_de_write(dev_priv, CNL_PORT_TX_DW7_GRP(port), val); 1117 } 1118 1119 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, 1120 const struct intel_crtc_state *crtc_state, 1121 int level) 1122 { 1123 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1124 enum port port = encoder->port; 1125 int width, rate, ln; 1126 u32 val; 1127 1128 width = crtc_state->lane_count; 1129 rate = crtc_state->port_clock; 1130 1131 /* 1132 * 1. If port type is eDP or DP, 1133 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1134 * else clear to 0b. 1135 */ 1136 val = intel_de_read(dev_priv, CNL_PORT_PCS_DW1_LN0(port)); 1137 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1138 val &= ~COMMON_KEEPER_EN; 1139 else 1140 val |= COMMON_KEEPER_EN; 1141 intel_de_write(dev_priv, CNL_PORT_PCS_DW1_GRP(port), val); 1142 1143 /* 2. Program loadgen select */ 1144 /* 1145 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes 1146 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1147 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1148 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1149 */ 1150 for (ln = 0; ln <= 3; ln++) { 1151 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port)); 1152 val &= ~LOADGEN_SELECT; 1153 1154 if ((rate <= 600000 && width == 4 && ln >= 1) || 1155 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { 1156 val |= LOADGEN_SELECT; 1157 } 1158 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val); 1159 } 1160 1161 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1162 val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5); 1163 val |= SUS_CLOCK_CONFIG; 1164 intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val); 1165 1166 /* 4. Clear training enable to change swing values */ 1167 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 1168 val &= ~TX_TRAINING_EN; 1169 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 1170 1171 /* 5. Program swing and de-emphasis */ 1172 cnl_ddi_vswing_program(encoder, crtc_state, level); 1173 1174 /* 6. Set training enable to trigger update */ 1175 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 1176 val |= TX_TRAINING_EN; 1177 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 1178 } 1179 1180 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1181 const struct intel_crtc_state *crtc_state, 1182 int level) 1183 { 1184 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1185 const struct cnl_ddi_buf_trans *ddi_translations; 1186 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1187 int n_entries, ln; 1188 u32 val; 1189 1190 if (DISPLAY_VER(dev_priv) >= 12) 1191 ddi_translations = tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries); 1192 else if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)) 1193 ddi_translations = jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries); 1194 else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) 1195 ddi_translations = ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries); 1196 else 1197 ddi_translations = icl_get_combo_buf_trans(encoder, crtc_state, &n_entries); 1198 1199 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 1200 return; 1201 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 1202 level = n_entries - 1; 1203 1204 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1205 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1206 1207 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1208 intel_dp->hobl_active = is_hobl_buf_trans(ddi_translations); 1209 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, 1210 intel_dp->hobl_active ? val : 0); 1211 } 1212 1213 /* Set PORT_TX_DW5 */ 1214 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 1215 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1216 TAP2_DISABLE | TAP3_DISABLE); 1217 val |= SCALING_MODE_SEL(0x2); 1218 val |= RTERM_SELECT(0x6); 1219 val |= TAP3_DISABLE; 1220 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1221 1222 /* Program PORT_TX_DW2 */ 1223 val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy)); 1224 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 1225 RCOMP_SCALAR_MASK); 1226 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); 1227 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); 1228 /* Program Rcomp scalar for every table entry */ 1229 val |= RCOMP_SCALAR(0x98); 1230 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val); 1231 1232 /* Program PORT_TX_DW4 */ 1233 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1234 for (ln = 0; ln <= 3; ln++) { 1235 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy)); 1236 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 1237 CURSOR_COEFF_MASK); 1238 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); 1239 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); 1240 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); 1241 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val); 1242 } 1243 1244 /* Program PORT_TX_DW7 */ 1245 val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy)); 1246 val &= ~N_SCALAR_MASK; 1247 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); 1248 intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val); 1249 } 1250 1251 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 1252 const struct intel_crtc_state *crtc_state, 1253 int level) 1254 { 1255 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1256 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1257 int width, rate, ln; 1258 u32 val; 1259 1260 width = crtc_state->lane_count; 1261 rate = crtc_state->port_clock; 1262 1263 /* 1264 * 1. If port type is eDP or DP, 1265 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1266 * else clear to 0b. 1267 */ 1268 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy)); 1269 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1270 val &= ~COMMON_KEEPER_EN; 1271 else 1272 val |= COMMON_KEEPER_EN; 1273 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 1274 1275 /* 2. Program loadgen select */ 1276 /* 1277 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes 1278 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1279 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1280 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1281 */ 1282 for (ln = 0; ln <= 3; ln++) { 1283 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy)); 1284 val &= ~LOADGEN_SELECT; 1285 1286 if ((rate <= 600000 && width == 4 && ln >= 1) || 1287 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { 1288 val |= LOADGEN_SELECT; 1289 } 1290 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val); 1291 } 1292 1293 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1294 val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); 1295 val |= SUS_CLOCK_CONFIG; 1296 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val); 1297 1298 /* 4. Clear training enable to change swing values */ 1299 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 1300 val &= ~TX_TRAINING_EN; 1301 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1302 1303 /* 5. Program swing and de-emphasis */ 1304 icl_ddi_combo_vswing_program(encoder, crtc_state, level); 1305 1306 /* 6. Set training enable to trigger update */ 1307 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 1308 val |= TX_TRAINING_EN; 1309 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1310 } 1311 1312 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 1313 const struct intel_crtc_state *crtc_state, 1314 int level) 1315 { 1316 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1317 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 1318 const struct icl_mg_phy_ddi_buf_trans *ddi_translations; 1319 int n_entries, ln; 1320 u32 val; 1321 1322 if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT) 1323 return; 1324 1325 ddi_translations = icl_get_mg_buf_trans(encoder, crtc_state, &n_entries); 1326 1327 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 1328 return; 1329 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 1330 level = n_entries - 1; 1331 1332 /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */ 1333 for (ln = 0; ln < 2; ln++) { 1334 val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port)); 1335 val &= ~CRI_USE_FS32; 1336 intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), val); 1337 1338 val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port)); 1339 val &= ~CRI_USE_FS32; 1340 intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), val); 1341 } 1342 1343 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1344 for (ln = 0; ln < 2; ln++) { 1345 val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port)); 1346 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; 1347 val |= CRI_TXDEEMPH_OVERRIDE_17_12( 1348 ddi_translations[level].cri_txdeemph_override_17_12); 1349 intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val); 1350 1351 val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port)); 1352 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; 1353 val |= CRI_TXDEEMPH_OVERRIDE_17_12( 1354 ddi_translations[level].cri_txdeemph_override_17_12); 1355 intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val); 1356 } 1357 1358 /* Program MG_TX_DRVCTRL with values from vswing table */ 1359 for (ln = 0; ln < 2; ln++) { 1360 val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port)); 1361 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1362 CRI_TXDEEMPH_OVERRIDE_5_0_MASK); 1363 val |= CRI_TXDEEMPH_OVERRIDE_5_0( 1364 ddi_translations[level].cri_txdeemph_override_5_0) | 1365 CRI_TXDEEMPH_OVERRIDE_11_6( 1366 ddi_translations[level].cri_txdeemph_override_11_6) | 1367 CRI_TXDEEMPH_OVERRIDE_EN; 1368 intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val); 1369 1370 val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port)); 1371 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1372 CRI_TXDEEMPH_OVERRIDE_5_0_MASK); 1373 val |= CRI_TXDEEMPH_OVERRIDE_5_0( 1374 ddi_translations[level].cri_txdeemph_override_5_0) | 1375 CRI_TXDEEMPH_OVERRIDE_11_6( 1376 ddi_translations[level].cri_txdeemph_override_11_6) | 1377 CRI_TXDEEMPH_OVERRIDE_EN; 1378 intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val); 1379 1380 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1381 } 1382 1383 /* 1384 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1385 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1386 * values from table for which TX1 and TX2 enabled. 1387 */ 1388 for (ln = 0; ln < 2; ln++) { 1389 val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port)); 1390 if (crtc_state->port_clock < 300000) 1391 val |= CFG_LOW_RATE_LKREN_EN; 1392 else 1393 val &= ~CFG_LOW_RATE_LKREN_EN; 1394 intel_de_write(dev_priv, MG_CLKHUB(ln, tc_port), val); 1395 } 1396 1397 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1398 for (ln = 0; ln < 2; ln++) { 1399 val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port)); 1400 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; 1401 if (crtc_state->port_clock <= 500000) { 1402 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; 1403 } else { 1404 val |= CFG_AMI_CK_DIV_OVERRIDE_EN | 1405 CFG_AMI_CK_DIV_OVERRIDE_VAL(1); 1406 } 1407 intel_de_write(dev_priv, MG_TX1_DCC(ln, tc_port), val); 1408 1409 val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port)); 1410 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; 1411 if (crtc_state->port_clock <= 500000) { 1412 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; 1413 } else { 1414 val |= CFG_AMI_CK_DIV_OVERRIDE_EN | 1415 CFG_AMI_CK_DIV_OVERRIDE_VAL(1); 1416 } 1417 intel_de_write(dev_priv, MG_TX2_DCC(ln, tc_port), val); 1418 } 1419 1420 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1421 for (ln = 0; ln < 2; ln++) { 1422 val = intel_de_read(dev_priv, 1423 MG_TX1_PISO_READLOAD(ln, tc_port)); 1424 val |= CRI_CALCINIT; 1425 intel_de_write(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 1426 val); 1427 1428 val = intel_de_read(dev_priv, 1429 MG_TX2_PISO_READLOAD(ln, tc_port)); 1430 val |= CRI_CALCINIT; 1431 intel_de_write(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 1432 val); 1433 } 1434 } 1435 1436 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder, 1437 const struct intel_crtc_state *crtc_state, 1438 int level) 1439 { 1440 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1441 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1442 1443 if (intel_phy_is_combo(dev_priv, phy)) 1444 icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level); 1445 else 1446 icl_mg_phy_ddi_vswing_sequence(encoder, crtc_state, level); 1447 } 1448 1449 static void 1450 tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 1451 const struct intel_crtc_state *crtc_state, 1452 int level) 1453 { 1454 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1455 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 1456 const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations; 1457 u32 val, dpcnt_mask, dpcnt_val; 1458 int n_entries, ln; 1459 1460 if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT) 1461 return; 1462 1463 if (IS_ALDERLAKE_P(dev_priv)) 1464 ddi_translations = adlp_get_dkl_buf_trans(encoder, crtc_state, &n_entries); 1465 else 1466 ddi_translations = tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries); 1467 1468 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 1469 return; 1470 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 1471 level = n_entries - 1; 1472 1473 dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK | 1474 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1475 DKL_TX_VSWING_CONTROL_MASK); 1476 dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control); 1477 dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control); 1478 dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control); 1479 1480 for (ln = 0; ln < 2; ln++) { 1481 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 1482 HIP_INDEX_VAL(tc_port, ln)); 1483 1484 intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0); 1485 1486 /* All the registers are RMW */ 1487 val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(tc_port)); 1488 val &= ~dpcnt_mask; 1489 val |= dpcnt_val; 1490 intel_de_write(dev_priv, DKL_TX_DPCNTL0(tc_port), val); 1491 1492 val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(tc_port)); 1493 val &= ~dpcnt_mask; 1494 val |= dpcnt_val; 1495 intel_de_write(dev_priv, DKL_TX_DPCNTL1(tc_port), val); 1496 1497 val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port)); 1498 val &= ~DKL_TX_DP20BITMODE; 1499 intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val); 1500 1501 if ((intel_crtc_has_dp_encoder(crtc_state) && 1502 crtc_state->port_clock == 162000) || 1503 (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 1504 crtc_state->port_clock == 594000)) 1505 val |= DKL_TX_LOADGEN_SHARING_PMD_DISABLE; 1506 else 1507 val &= ~DKL_TX_LOADGEN_SHARING_PMD_DISABLE; 1508 } 1509 } 1510 1511 static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder, 1512 const struct intel_crtc_state *crtc_state, 1513 int level) 1514 { 1515 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1516 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1517 1518 if (intel_phy_is_combo(dev_priv, phy)) 1519 icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level); 1520 else 1521 tgl_dkl_phy_ddi_vswing_sequence(encoder, crtc_state, level); 1522 } 1523 1524 static int translate_signal_level(struct intel_dp *intel_dp, 1525 u8 signal_levels) 1526 { 1527 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1528 int i; 1529 1530 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1531 if (index_to_dp_signal_levels[i] == signal_levels) 1532 return i; 1533 } 1534 1535 drm_WARN(&i915->drm, 1, 1536 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1537 signal_levels); 1538 1539 return 0; 1540 } 1541 1542 static int intel_ddi_dp_level(struct intel_dp *intel_dp) 1543 { 1544 u8 train_set = intel_dp->train_set[0]; 1545 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1546 DP_TRAIN_PRE_EMPHASIS_MASK); 1547 1548 return translate_signal_level(intel_dp, signal_levels); 1549 } 1550 1551 static void 1552 tgl_set_signal_levels(struct intel_dp *intel_dp, 1553 const struct intel_crtc_state *crtc_state) 1554 { 1555 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1556 int level = intel_ddi_dp_level(intel_dp); 1557 1558 tgl_ddi_vswing_sequence(encoder, crtc_state, level); 1559 } 1560 1561 static void 1562 icl_set_signal_levels(struct intel_dp *intel_dp, 1563 const struct intel_crtc_state *crtc_state) 1564 { 1565 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1566 int level = intel_ddi_dp_level(intel_dp); 1567 1568 icl_ddi_vswing_sequence(encoder, crtc_state, level); 1569 } 1570 1571 static void 1572 cnl_set_signal_levels(struct intel_dp *intel_dp, 1573 const struct intel_crtc_state *crtc_state) 1574 { 1575 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1576 int level = intel_ddi_dp_level(intel_dp); 1577 1578 cnl_ddi_vswing_sequence(encoder, crtc_state, level); 1579 } 1580 1581 static void 1582 bxt_set_signal_levels(struct intel_dp *intel_dp, 1583 const struct intel_crtc_state *crtc_state) 1584 { 1585 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1586 int level = intel_ddi_dp_level(intel_dp); 1587 1588 bxt_ddi_vswing_sequence(encoder, crtc_state, level); 1589 } 1590 1591 static void 1592 hsw_set_signal_levels(struct intel_dp *intel_dp, 1593 const struct intel_crtc_state *crtc_state) 1594 { 1595 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1596 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1597 int level = intel_ddi_dp_level(intel_dp); 1598 enum port port = encoder->port; 1599 u32 signal_levels; 1600 1601 signal_levels = DDI_BUF_TRANS_SELECT(level); 1602 1603 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1604 signal_levels); 1605 1606 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1607 intel_dp->DP |= signal_levels; 1608 1609 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 1610 skl_ddi_set_iboost(encoder, crtc_state, level); 1611 1612 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 1613 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 1614 } 1615 1616 static void _cnl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1617 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1618 { 1619 mutex_lock(&i915->dpll.lock); 1620 1621 intel_de_rmw(i915, reg, clk_sel_mask, clk_sel); 1622 1623 /* 1624 * "This step and the step before must be 1625 * done with separate register writes." 1626 */ 1627 intel_de_rmw(i915, reg, clk_off, 0); 1628 1629 mutex_unlock(&i915->dpll.lock); 1630 } 1631 1632 static void _cnl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1633 u32 clk_off) 1634 { 1635 mutex_lock(&i915->dpll.lock); 1636 1637 intel_de_rmw(i915, reg, 0, clk_off); 1638 1639 mutex_unlock(&i915->dpll.lock); 1640 } 1641 1642 static bool _cnl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg, 1643 u32 clk_off) 1644 { 1645 return !(intel_de_read(i915, reg) & clk_off); 1646 } 1647 1648 static struct intel_shared_dpll * 1649 _cnl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg, 1650 u32 clk_sel_mask, u32 clk_sel_shift) 1651 { 1652 enum intel_dpll_id id; 1653 1654 id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift; 1655 1656 return intel_get_shared_dpll_by_id(i915, id); 1657 } 1658 1659 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1660 const struct intel_crtc_state *crtc_state) 1661 { 1662 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1663 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1664 enum phy phy = intel_port_to_phy(i915, encoder->port); 1665 1666 if (drm_WARN_ON(&i915->drm, !pll)) 1667 return; 1668 1669 _cnl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1670 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1671 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1672 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1673 } 1674 1675 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1676 { 1677 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1678 enum phy phy = intel_port_to_phy(i915, encoder->port); 1679 1680 _cnl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1681 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1682 } 1683 1684 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1685 { 1686 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1687 enum phy phy = intel_port_to_phy(i915, encoder->port); 1688 1689 return _cnl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy), 1690 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1691 } 1692 1693 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1694 { 1695 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1696 enum phy phy = intel_port_to_phy(i915, encoder->port); 1697 1698 return _cnl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy), 1699 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1700 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1701 } 1702 1703 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1704 const struct intel_crtc_state *crtc_state) 1705 { 1706 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1707 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1708 enum phy phy = intel_port_to_phy(i915, encoder->port); 1709 1710 if (drm_WARN_ON(&i915->drm, !pll)) 1711 return; 1712 1713 _cnl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1714 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1715 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1716 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1717 } 1718 1719 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1720 { 1721 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1722 enum phy phy = intel_port_to_phy(i915, encoder->port); 1723 1724 _cnl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1725 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1726 } 1727 1728 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1729 { 1730 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1731 enum phy phy = intel_port_to_phy(i915, encoder->port); 1732 1733 return _cnl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1734 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1735 } 1736 1737 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1738 { 1739 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1740 enum phy phy = intel_port_to_phy(i915, encoder->port); 1741 1742 return _cnl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1743 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1744 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1745 } 1746 1747 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1748 const struct intel_crtc_state *crtc_state) 1749 { 1750 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1751 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1752 enum phy phy = intel_port_to_phy(i915, encoder->port); 1753 1754 if (drm_WARN_ON(&i915->drm, !pll)) 1755 return; 1756 1757 /* 1758 * If we fail this, something went very wrong: first 2 PLLs should be 1759 * used by first 2 phys and last 2 PLLs by last phys 1760 */ 1761 if (drm_WARN_ON(&i915->drm, 1762 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1763 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1764 return; 1765 1766 _cnl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1767 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1768 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1769 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1770 } 1771 1772 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1773 { 1774 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1775 enum phy phy = intel_port_to_phy(i915, encoder->port); 1776 1777 _cnl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1778 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1779 } 1780 1781 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1782 { 1783 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1784 enum phy phy = intel_port_to_phy(i915, encoder->port); 1785 1786 return _cnl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy), 1787 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1788 } 1789 1790 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1791 { 1792 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1793 enum phy phy = intel_port_to_phy(i915, encoder->port); 1794 1795 return _cnl_ddi_get_pll(i915, DG1_DPCLKA_CFGCR0(phy), 1796 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1797 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1798 } 1799 1800 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1801 const struct intel_crtc_state *crtc_state) 1802 { 1803 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1804 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1805 enum phy phy = intel_port_to_phy(i915, encoder->port); 1806 1807 if (drm_WARN_ON(&i915->drm, !pll)) 1808 return; 1809 1810 _cnl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1811 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1812 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1813 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1814 } 1815 1816 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1817 { 1818 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1819 enum phy phy = intel_port_to_phy(i915, encoder->port); 1820 1821 _cnl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1822 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1823 } 1824 1825 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1826 { 1827 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1828 enum phy phy = intel_port_to_phy(i915, encoder->port); 1829 1830 return _cnl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1831 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1832 } 1833 1834 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1835 { 1836 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1837 enum phy phy = intel_port_to_phy(i915, encoder->port); 1838 1839 return _cnl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1840 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1841 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1842 } 1843 1844 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1845 const struct intel_crtc_state *crtc_state) 1846 { 1847 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1848 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1849 enum port port = encoder->port; 1850 1851 if (drm_WARN_ON(&i915->drm, !pll)) 1852 return; 1853 1854 /* 1855 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1856 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1857 */ 1858 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1859 1860 icl_ddi_combo_enable_clock(encoder, crtc_state); 1861 } 1862 1863 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1864 { 1865 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1866 enum port port = encoder->port; 1867 1868 icl_ddi_combo_disable_clock(encoder); 1869 1870 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1871 } 1872 1873 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1874 { 1875 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1876 enum port port = encoder->port; 1877 u32 tmp; 1878 1879 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1880 1881 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1882 return false; 1883 1884 return icl_ddi_combo_is_clock_enabled(encoder); 1885 } 1886 1887 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1888 const struct intel_crtc_state *crtc_state) 1889 { 1890 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1891 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1892 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1893 enum port port = encoder->port; 1894 1895 if (drm_WARN_ON(&i915->drm, !pll)) 1896 return; 1897 1898 intel_de_write(i915, DDI_CLK_SEL(port), 1899 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1900 1901 mutex_lock(&i915->dpll.lock); 1902 1903 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1904 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1905 1906 mutex_unlock(&i915->dpll.lock); 1907 } 1908 1909 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1910 { 1911 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1912 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1913 enum port port = encoder->port; 1914 1915 mutex_lock(&i915->dpll.lock); 1916 1917 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1918 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1919 1920 mutex_unlock(&i915->dpll.lock); 1921 1922 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1923 } 1924 1925 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1926 { 1927 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1928 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1929 enum port port = encoder->port; 1930 u32 tmp; 1931 1932 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1933 1934 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1935 return false; 1936 1937 tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0); 1938 1939 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1940 } 1941 1942 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1943 { 1944 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1945 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1946 enum port port = encoder->port; 1947 enum intel_dpll_id id; 1948 u32 tmp; 1949 1950 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1951 1952 switch (tmp & DDI_CLK_SEL_MASK) { 1953 case DDI_CLK_SEL_TBT_162: 1954 case DDI_CLK_SEL_TBT_270: 1955 case DDI_CLK_SEL_TBT_540: 1956 case DDI_CLK_SEL_TBT_810: 1957 id = DPLL_ID_ICL_TBTPLL; 1958 break; 1959 case DDI_CLK_SEL_MG: 1960 id = icl_tc_port_to_pll_id(tc_port); 1961 break; 1962 default: 1963 MISSING_CASE(tmp); 1964 fallthrough; 1965 case DDI_CLK_SEL_NONE: 1966 return NULL; 1967 } 1968 1969 return intel_get_shared_dpll_by_id(i915, id); 1970 } 1971 1972 static void cnl_ddi_enable_clock(struct intel_encoder *encoder, 1973 const struct intel_crtc_state *crtc_state) 1974 { 1975 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1976 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1977 enum port port = encoder->port; 1978 1979 if (drm_WARN_ON(&i915->drm, !pll)) 1980 return; 1981 1982 _cnl_ddi_enable_clock(i915, DPCLKA_CFGCR0, 1983 DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port), 1984 DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port), 1985 DPCLKA_CFGCR0_DDI_CLK_OFF(port)); 1986 } 1987 1988 static void cnl_ddi_disable_clock(struct intel_encoder *encoder) 1989 { 1990 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1991 enum port port = encoder->port; 1992 1993 _cnl_ddi_disable_clock(i915, DPCLKA_CFGCR0, 1994 DPCLKA_CFGCR0_DDI_CLK_OFF(port)); 1995 } 1996 1997 static bool cnl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1998 { 1999 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2000 enum port port = encoder->port; 2001 2002 return _cnl_ddi_is_clock_enabled(i915, DPCLKA_CFGCR0, 2003 DPCLKA_CFGCR0_DDI_CLK_OFF(port)); 2004 } 2005 2006 static struct intel_shared_dpll *cnl_ddi_get_pll(struct intel_encoder *encoder) 2007 { 2008 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2009 enum port port = encoder->port; 2010 2011 return _cnl_ddi_get_pll(i915, DPCLKA_CFGCR0, 2012 DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port), 2013 DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)); 2014 } 2015 2016 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 2017 { 2018 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2019 enum intel_dpll_id id; 2020 2021 switch (encoder->port) { 2022 case PORT_A: 2023 id = DPLL_ID_SKL_DPLL0; 2024 break; 2025 case PORT_B: 2026 id = DPLL_ID_SKL_DPLL1; 2027 break; 2028 case PORT_C: 2029 id = DPLL_ID_SKL_DPLL2; 2030 break; 2031 default: 2032 MISSING_CASE(encoder->port); 2033 return NULL; 2034 } 2035 2036 return intel_get_shared_dpll_by_id(i915, id); 2037 } 2038 2039 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 2040 const struct intel_crtc_state *crtc_state) 2041 { 2042 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2043 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 2044 enum port port = encoder->port; 2045 2046 if (drm_WARN_ON(&i915->drm, !pll)) 2047 return; 2048 2049 mutex_lock(&i915->dpll.lock); 2050 2051 intel_de_rmw(i915, DPLL_CTRL2, 2052 DPLL_CTRL2_DDI_CLK_OFF(port) | 2053 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 2054 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 2055 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 2056 2057 mutex_unlock(&i915->dpll.lock); 2058 } 2059 2060 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 2061 { 2062 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2063 enum port port = encoder->port; 2064 2065 mutex_lock(&i915->dpll.lock); 2066 2067 intel_de_rmw(i915, DPLL_CTRL2, 2068 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 2069 2070 mutex_unlock(&i915->dpll.lock); 2071 } 2072 2073 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 2074 { 2075 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2076 enum port port = encoder->port; 2077 2078 /* 2079 * FIXME Not sure if the override affects both 2080 * the PLL selection and the CLK_OFF bit. 2081 */ 2082 return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 2083 } 2084 2085 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 2086 { 2087 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2088 enum port port = encoder->port; 2089 enum intel_dpll_id id; 2090 u32 tmp; 2091 2092 tmp = intel_de_read(i915, DPLL_CTRL2); 2093 2094 /* 2095 * FIXME Not sure if the override affects both 2096 * the PLL selection and the CLK_OFF bit. 2097 */ 2098 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 2099 return NULL; 2100 2101 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 2102 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 2103 2104 return intel_get_shared_dpll_by_id(i915, id); 2105 } 2106 2107 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 2108 const struct intel_crtc_state *crtc_state) 2109 { 2110 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2111 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 2112 enum port port = encoder->port; 2113 2114 if (drm_WARN_ON(&i915->drm, !pll)) 2115 return; 2116 2117 intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 2118 } 2119 2120 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 2121 { 2122 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2123 enum port port = encoder->port; 2124 2125 intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 2126 } 2127 2128 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 2129 { 2130 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2131 enum port port = encoder->port; 2132 2133 return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 2134 } 2135 2136 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 2137 { 2138 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2139 enum port port = encoder->port; 2140 enum intel_dpll_id id; 2141 u32 tmp; 2142 2143 tmp = intel_de_read(i915, PORT_CLK_SEL(port)); 2144 2145 switch (tmp & PORT_CLK_SEL_MASK) { 2146 case PORT_CLK_SEL_WRPLL1: 2147 id = DPLL_ID_WRPLL1; 2148 break; 2149 case PORT_CLK_SEL_WRPLL2: 2150 id = DPLL_ID_WRPLL2; 2151 break; 2152 case PORT_CLK_SEL_SPLL: 2153 id = DPLL_ID_SPLL; 2154 break; 2155 case PORT_CLK_SEL_LCPLL_810: 2156 id = DPLL_ID_LCPLL_810; 2157 break; 2158 case PORT_CLK_SEL_LCPLL_1350: 2159 id = DPLL_ID_LCPLL_1350; 2160 break; 2161 case PORT_CLK_SEL_LCPLL_2700: 2162 id = DPLL_ID_LCPLL_2700; 2163 break; 2164 default: 2165 MISSING_CASE(tmp); 2166 fallthrough; 2167 case PORT_CLK_SEL_NONE: 2168 return NULL; 2169 } 2170 2171 return intel_get_shared_dpll_by_id(i915, id); 2172 } 2173 2174 void intel_ddi_enable_clock(struct intel_encoder *encoder, 2175 const struct intel_crtc_state *crtc_state) 2176 { 2177 if (encoder->enable_clock) 2178 encoder->enable_clock(encoder, crtc_state); 2179 } 2180 2181 static void intel_ddi_disable_clock(struct intel_encoder *encoder) 2182 { 2183 if (encoder->disable_clock) 2184 encoder->disable_clock(encoder); 2185 } 2186 2187 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2188 { 2189 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2190 u32 port_mask; 2191 bool ddi_clk_needed; 2192 2193 /* 2194 * In case of DP MST, we sanitize the primary encoder only, not the 2195 * virtual ones. 2196 */ 2197 if (encoder->type == INTEL_OUTPUT_DP_MST) 2198 return; 2199 2200 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2201 u8 pipe_mask; 2202 bool is_mst; 2203 2204 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2205 /* 2206 * In the unlikely case that BIOS enables DP in MST mode, just 2207 * warn since our MST HW readout is incomplete. 2208 */ 2209 if (drm_WARN_ON(&i915->drm, is_mst)) 2210 return; 2211 } 2212 2213 port_mask = BIT(encoder->port); 2214 ddi_clk_needed = encoder->base.crtc; 2215 2216 if (encoder->type == INTEL_OUTPUT_DSI) { 2217 struct intel_encoder *other_encoder; 2218 2219 port_mask = intel_dsi_encoder_ports(encoder); 2220 /* 2221 * Sanity check that we haven't incorrectly registered another 2222 * encoder using any of the ports of this DSI encoder. 2223 */ 2224 for_each_intel_encoder(&i915->drm, other_encoder) { 2225 if (other_encoder == encoder) 2226 continue; 2227 2228 if (drm_WARN_ON(&i915->drm, 2229 port_mask & BIT(other_encoder->port))) 2230 return; 2231 } 2232 /* 2233 * For DSI we keep the ddi clocks gated 2234 * except during enable/disable sequence. 2235 */ 2236 ddi_clk_needed = false; 2237 } 2238 2239 if (ddi_clk_needed || !encoder->disable_clock || 2240 !encoder->is_clock_enabled(encoder)) 2241 return; 2242 2243 drm_notice(&i915->drm, 2244 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2245 encoder->base.base.id, encoder->base.name); 2246 2247 encoder->disable_clock(encoder); 2248 } 2249 2250 static void 2251 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2252 const struct intel_crtc_state *crtc_state) 2253 { 2254 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2255 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port); 2256 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); 2257 u32 ln0, ln1, pin_assignment; 2258 u8 width; 2259 2260 if (!intel_phy_is_tc(dev_priv, phy) || 2261 dig_port->tc_mode == TC_PORT_TBT_ALT) 2262 return; 2263 2264 if (DISPLAY_VER(dev_priv) >= 12) { 2265 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2266 HIP_INDEX_VAL(tc_port, 0x0)); 2267 ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); 2268 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2269 HIP_INDEX_VAL(tc_port, 0x1)); 2270 ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); 2271 } else { 2272 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 2273 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 2274 } 2275 2276 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2277 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2278 2279 /* DPPATC */ 2280 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 2281 width = crtc_state->lane_count; 2282 2283 switch (pin_assignment) { 2284 case 0x0: 2285 drm_WARN_ON(&dev_priv->drm, 2286 dig_port->tc_mode != TC_PORT_LEGACY); 2287 if (width == 1) { 2288 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2289 } else { 2290 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2291 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2292 } 2293 break; 2294 case 0x1: 2295 if (width == 4) { 2296 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2297 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2298 } 2299 break; 2300 case 0x2: 2301 if (width == 2) { 2302 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2303 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2304 } 2305 break; 2306 case 0x3: 2307 case 0x5: 2308 if (width == 1) { 2309 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2310 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2311 } else { 2312 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2313 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2314 } 2315 break; 2316 case 0x4: 2317 case 0x6: 2318 if (width == 1) { 2319 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2320 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2321 } else { 2322 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2323 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2324 } 2325 break; 2326 default: 2327 MISSING_CASE(pin_assignment); 2328 } 2329 2330 if (DISPLAY_VER(dev_priv) >= 12) { 2331 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2332 HIP_INDEX_VAL(tc_port, 0x0)); 2333 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0); 2334 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2335 HIP_INDEX_VAL(tc_port, 0x1)); 2336 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1); 2337 } else { 2338 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 2339 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 2340 } 2341 } 2342 2343 static enum transcoder 2344 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2345 { 2346 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2347 return crtc_state->mst_master_transcoder; 2348 else 2349 return crtc_state->cpu_transcoder; 2350 } 2351 2352 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2353 const struct intel_crtc_state *crtc_state) 2354 { 2355 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2356 2357 if (DISPLAY_VER(dev_priv) >= 12) 2358 return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state)); 2359 else 2360 return DP_TP_CTL(encoder->port); 2361 } 2362 2363 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2364 const struct intel_crtc_state *crtc_state) 2365 { 2366 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2367 2368 if (DISPLAY_VER(dev_priv) >= 12) 2369 return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state)); 2370 else 2371 return DP_TP_STATUS(encoder->port); 2372 } 2373 2374 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2375 const struct intel_crtc_state *crtc_state, 2376 bool enable) 2377 { 2378 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2379 2380 if (!crtc_state->vrr.enable) 2381 return; 2382 2383 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2384 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2385 drm_dbg_kms(&i915->drm, 2386 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2387 enabledisable(enable)); 2388 } 2389 2390 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2391 const struct intel_crtc_state *crtc_state) 2392 { 2393 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2394 2395 if (!crtc_state->fec_enable) 2396 return; 2397 2398 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0) 2399 drm_dbg_kms(&i915->drm, 2400 "Failed to set FEC_READY in the sink\n"); 2401 } 2402 2403 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2404 const struct intel_crtc_state *crtc_state) 2405 { 2406 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2407 struct intel_dp *intel_dp; 2408 u32 val; 2409 2410 if (!crtc_state->fec_enable) 2411 return; 2412 2413 intel_dp = enc_to_intel_dp(encoder); 2414 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2415 val |= DP_TP_CTL_FEC_ENABLE; 2416 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 2417 } 2418 2419 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder, 2420 const struct intel_crtc_state *crtc_state) 2421 { 2422 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2423 struct intel_dp *intel_dp; 2424 u32 val; 2425 2426 if (!crtc_state->fec_enable) 2427 return; 2428 2429 intel_dp = enc_to_intel_dp(encoder); 2430 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2431 val &= ~DP_TP_CTL_FEC_ENABLE; 2432 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 2433 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2434 } 2435 2436 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2437 const struct intel_crtc_state *crtc_state) 2438 { 2439 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2440 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2441 enum phy phy = intel_port_to_phy(i915, encoder->port); 2442 2443 if (intel_phy_is_combo(i915, phy)) { 2444 bool lane_reversal = 2445 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 2446 2447 intel_combo_phy_power_up_lanes(i915, phy, false, 2448 crtc_state->lane_count, 2449 lane_reversal); 2450 } 2451 } 2452 2453 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2454 struct intel_crtc_state *pipe_config) 2455 { 2456 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2457 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2458 enum pipe pipe = crtc->pipe; 2459 u32 dss1; 2460 2461 if (!HAS_MSO(i915)) 2462 return; 2463 2464 dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); 2465 2466 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2467 if (!pipe_config->splitter.enable) 2468 return; 2469 2470 /* Splitter enable is supported for pipe A only. */ 2471 if (drm_WARN_ON(&i915->drm, pipe != PIPE_A)) { 2472 pipe_config->splitter.enable = false; 2473 return; 2474 } 2475 2476 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2477 default: 2478 drm_WARN(&i915->drm, true, 2479 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2480 fallthrough; 2481 case SPLITTER_CONFIGURATION_2_SEGMENT: 2482 pipe_config->splitter.link_count = 2; 2483 break; 2484 case SPLITTER_CONFIGURATION_4_SEGMENT: 2485 pipe_config->splitter.link_count = 4; 2486 break; 2487 } 2488 2489 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2490 } 2491 2492 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2493 { 2494 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2495 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2496 enum pipe pipe = crtc->pipe; 2497 u32 dss1 = 0; 2498 2499 if (!HAS_MSO(i915)) 2500 return; 2501 2502 if (crtc_state->splitter.enable) { 2503 /* Splitter enable is supported for pipe A only. */ 2504 if (drm_WARN_ON(&i915->drm, pipe != PIPE_A)) 2505 return; 2506 2507 dss1 |= SPLITTER_ENABLE; 2508 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2509 if (crtc_state->splitter.link_count == 2) 2510 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2511 else 2512 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2513 } 2514 2515 intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), 2516 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2517 OVERLAP_PIXELS_MASK, dss1); 2518 } 2519 2520 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2521 struct intel_encoder *encoder, 2522 const struct intel_crtc_state *crtc_state, 2523 const struct drm_connector_state *conn_state) 2524 { 2525 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2526 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2527 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2528 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2529 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2530 int level = intel_ddi_dp_level(intel_dp); 2531 2532 intel_dp_set_link_params(intel_dp, 2533 crtc_state->port_clock, 2534 crtc_state->lane_count); 2535 2536 /* 2537 * 1. Enable Power Wells 2538 * 2539 * This was handled at the beginning of intel_atomic_commit_tail(), 2540 * before we called down into this function. 2541 */ 2542 2543 /* 2. Enable Panel Power if PPS is required */ 2544 intel_pps_on(intel_dp); 2545 2546 /* 2547 * 3. For non-TBT Type-C ports, set FIA lane count 2548 * (DFLEXDPSP.DPX4TXLATC) 2549 * 2550 * This was done before tgl_ddi_pre_enable_dp by 2551 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2552 */ 2553 2554 /* 2555 * 4. Enable the port PLL. 2556 * 2557 * The PLL enabling itself was already done before this function by 2558 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 2559 * configure the PLL to port mapping here. 2560 */ 2561 intel_ddi_enable_clock(encoder, crtc_state); 2562 2563 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2564 if (!intel_phy_is_tc(dev_priv, phy) || 2565 dig_port->tc_mode != TC_PORT_TBT_ALT) { 2566 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2567 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2568 dig_port->ddi_io_power_domain); 2569 } 2570 2571 /* 6. Program DP_MODE */ 2572 icl_program_mg_dp_mode(dig_port, crtc_state); 2573 2574 /* 2575 * 7. The rest of the below are substeps under the bspec's "Enable and 2576 * Train Display Port" step. Note that steps that are specific to 2577 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2578 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2579 * us when active_mst_links==0, so any steps designated for "single 2580 * stream or multi-stream master transcoder" can just be performed 2581 * unconditionally here. 2582 */ 2583 2584 /* 2585 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2586 * Transcoder. 2587 */ 2588 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2589 2590 /* 2591 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2592 * Transport Select 2593 */ 2594 intel_ddi_config_transcoder_func(encoder, crtc_state); 2595 2596 /* 2597 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2598 * selected 2599 * 2600 * This will be handled by the intel_dp_start_link_train() farther 2601 * down this function. 2602 */ 2603 2604 /* 7.e Configure voltage swing and related IO settings */ 2605 tgl_ddi_vswing_sequence(encoder, crtc_state, level); 2606 2607 /* 2608 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2609 * the used lanes of the DDI. 2610 */ 2611 intel_ddi_power_up_lanes(encoder, crtc_state); 2612 2613 /* 2614 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2615 */ 2616 intel_ddi_mso_configure(crtc_state); 2617 2618 /* 2619 * 7.g Configure and enable DDI_BUF_CTL 2620 * 7.h Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout 2621 * after 500 us. 2622 * 2623 * We only configure what the register value will be here. Actual 2624 * enabling happens during link training farther down. 2625 */ 2626 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2627 2628 if (!is_mst) 2629 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2630 2631 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2632 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); 2633 /* 2634 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2635 * in the FEC_CONFIGURATION register to 1 before initiating link 2636 * training 2637 */ 2638 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 2639 2640 intel_dp_check_frl_training(intel_dp); 2641 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2642 2643 /* 2644 * 7.i Follow DisplayPort specification training sequence (see notes for 2645 * failure handling) 2646 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2647 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2648 * (timeout after 800 us) 2649 */ 2650 intel_dp_start_link_train(intel_dp, crtc_state); 2651 2652 /* 7.k Set DP_TP_CTL link training to Normal */ 2653 if (!is_trans_port_sync_mode(crtc_state)) 2654 intel_dp_stop_link_train(intel_dp, crtc_state); 2655 2656 /* 7.l Configure and enable FEC if needed */ 2657 intel_ddi_enable_fec(encoder, crtc_state); 2658 if (!crtc_state->bigjoiner) 2659 intel_dsc_enable(encoder, crtc_state); 2660 } 2661 2662 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2663 struct intel_encoder *encoder, 2664 const struct intel_crtc_state *crtc_state, 2665 const struct drm_connector_state *conn_state) 2666 { 2667 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2668 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2669 enum port port = encoder->port; 2670 enum phy phy = intel_port_to_phy(dev_priv, port); 2671 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2672 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2673 int level = intel_ddi_dp_level(intel_dp); 2674 2675 if (DISPLAY_VER(dev_priv) < 11) 2676 drm_WARN_ON(&dev_priv->drm, 2677 is_mst && (port == PORT_A || port == PORT_E)); 2678 else 2679 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 2680 2681 intel_dp_set_link_params(intel_dp, 2682 crtc_state->port_clock, 2683 crtc_state->lane_count); 2684 2685 intel_pps_on(intel_dp); 2686 2687 intel_ddi_enable_clock(encoder, crtc_state); 2688 2689 if (!intel_phy_is_tc(dev_priv, phy) || 2690 dig_port->tc_mode != TC_PORT_TBT_ALT) { 2691 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2692 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2693 dig_port->ddi_io_power_domain); 2694 } 2695 2696 icl_program_mg_dp_mode(dig_port, crtc_state); 2697 2698 if (DISPLAY_VER(dev_priv) >= 11) 2699 icl_ddi_vswing_sequence(encoder, crtc_state, level); 2700 else if (IS_CANNONLAKE(dev_priv)) 2701 cnl_ddi_vswing_sequence(encoder, crtc_state, level); 2702 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 2703 bxt_ddi_vswing_sequence(encoder, crtc_state, level); 2704 else 2705 intel_prepare_dp_ddi_buffers(encoder, crtc_state); 2706 2707 intel_ddi_power_up_lanes(encoder, crtc_state); 2708 2709 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2710 if (!is_mst) 2711 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2712 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2713 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, 2714 true); 2715 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 2716 intel_dp_start_link_train(intel_dp, crtc_state); 2717 if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && 2718 !is_trans_port_sync_mode(crtc_state)) 2719 intel_dp_stop_link_train(intel_dp, crtc_state); 2720 2721 intel_ddi_enable_fec(encoder, crtc_state); 2722 2723 if (!is_mst) 2724 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2725 2726 if (!crtc_state->bigjoiner) 2727 intel_dsc_enable(encoder, crtc_state); 2728 } 2729 2730 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2731 struct intel_encoder *encoder, 2732 const struct intel_crtc_state *crtc_state, 2733 const struct drm_connector_state *conn_state) 2734 { 2735 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2736 2737 if (DISPLAY_VER(dev_priv) >= 12) 2738 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2739 else 2740 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2741 2742 /* MST will call a setting of MSA after an allocating of Virtual Channel 2743 * from MST encoder pre_enable callback. 2744 */ 2745 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 2746 intel_ddi_set_dp_msa(crtc_state, conn_state); 2747 2748 intel_dp_set_m_n(crtc_state, M1_N1); 2749 } 2750 } 2751 2752 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2753 struct intel_encoder *encoder, 2754 const struct intel_crtc_state *crtc_state, 2755 const struct drm_connector_state *conn_state) 2756 { 2757 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2758 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2759 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2760 2761 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2762 intel_ddi_enable_clock(encoder, crtc_state); 2763 2764 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2765 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2766 dig_port->ddi_io_power_domain); 2767 2768 icl_program_mg_dp_mode(dig_port, crtc_state); 2769 2770 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2771 2772 dig_port->set_infoframes(encoder, 2773 crtc_state->has_infoframe, 2774 crtc_state, conn_state); 2775 } 2776 2777 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 2778 struct intel_encoder *encoder, 2779 const struct intel_crtc_state *crtc_state, 2780 const struct drm_connector_state *conn_state) 2781 { 2782 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2783 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2784 enum pipe pipe = crtc->pipe; 2785 2786 /* 2787 * When called from DP MST code: 2788 * - conn_state will be NULL 2789 * - encoder will be the main encoder (ie. mst->primary) 2790 * - the main connector associated with this port 2791 * won't be active or linked to a crtc 2792 * - crtc_state will be the state of the first stream to 2793 * be activated on this port, and it may not be the same 2794 * stream that will be deactivated last, but each stream 2795 * should have a state that is identical when it comes to 2796 * the DP link parameteres 2797 */ 2798 2799 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 2800 2801 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2802 2803 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 2804 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 2805 conn_state); 2806 } else { 2807 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2808 2809 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 2810 conn_state); 2811 2812 /* FIXME precompute everything properly */ 2813 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) 2814 dig_port->set_infoframes(encoder, 2815 crtc_state->has_infoframe, 2816 crtc_state, conn_state); 2817 } 2818 } 2819 2820 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 2821 const struct intel_crtc_state *crtc_state) 2822 { 2823 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2824 enum port port = encoder->port; 2825 bool wait = false; 2826 u32 val; 2827 2828 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2829 if (val & DDI_BUF_CTL_ENABLE) { 2830 val &= ~DDI_BUF_CTL_ENABLE; 2831 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 2832 wait = true; 2833 } 2834 2835 if (intel_crtc_has_dp_encoder(crtc_state)) { 2836 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2837 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 2838 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 2839 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 2840 } 2841 2842 /* Disable FEC in DP Sink */ 2843 intel_ddi_disable_fec_state(encoder, crtc_state); 2844 2845 if (wait) 2846 intel_wait_ddi_buf_idle(dev_priv, port); 2847 } 2848 2849 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 2850 struct intel_encoder *encoder, 2851 const struct intel_crtc_state *old_crtc_state, 2852 const struct drm_connector_state *old_conn_state) 2853 { 2854 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2855 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2856 struct intel_dp *intel_dp = &dig_port->dp; 2857 bool is_mst = intel_crtc_has_type(old_crtc_state, 2858 INTEL_OUTPUT_DP_MST); 2859 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2860 2861 if (!is_mst) 2862 intel_dp_set_infoframes(encoder, false, 2863 old_crtc_state, old_conn_state); 2864 2865 /* 2866 * Power down sink before disabling the port, otherwise we end 2867 * up getting interrupts from the sink on detecting link loss. 2868 */ 2869 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 2870 2871 if (DISPLAY_VER(dev_priv) >= 12) { 2872 if (is_mst) { 2873 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 2874 u32 val; 2875 2876 val = intel_de_read(dev_priv, 2877 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 2878 val &= ~(TGL_TRANS_DDI_PORT_MASK | 2879 TRANS_DDI_MODE_SELECT_MASK); 2880 intel_de_write(dev_priv, 2881 TRANS_DDI_FUNC_CTL(cpu_transcoder), 2882 val); 2883 } 2884 } else { 2885 if (!is_mst) 2886 intel_ddi_disable_pipe_clock(old_crtc_state); 2887 } 2888 2889 intel_disable_ddi_buf(encoder, old_crtc_state); 2890 2891 /* 2892 * From TGL spec: "If single stream or multi-stream master transcoder: 2893 * Configure Transcoder Clock select to direct no clock to the 2894 * transcoder" 2895 */ 2896 if (DISPLAY_VER(dev_priv) >= 12) 2897 intel_ddi_disable_pipe_clock(old_crtc_state); 2898 2899 intel_pps_vdd_on(intel_dp); 2900 intel_pps_off(intel_dp); 2901 2902 if (!intel_phy_is_tc(dev_priv, phy) || 2903 dig_port->tc_mode != TC_PORT_TBT_ALT) 2904 intel_display_power_put(dev_priv, 2905 dig_port->ddi_io_power_domain, 2906 fetch_and_zero(&dig_port->ddi_io_wakeref)); 2907 2908 intel_ddi_disable_clock(encoder); 2909 } 2910 2911 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 2912 struct intel_encoder *encoder, 2913 const struct intel_crtc_state *old_crtc_state, 2914 const struct drm_connector_state *old_conn_state) 2915 { 2916 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2917 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2918 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2919 2920 dig_port->set_infoframes(encoder, false, 2921 old_crtc_state, old_conn_state); 2922 2923 intel_ddi_disable_pipe_clock(old_crtc_state); 2924 2925 intel_disable_ddi_buf(encoder, old_crtc_state); 2926 2927 intel_display_power_put(dev_priv, 2928 dig_port->ddi_io_power_domain, 2929 fetch_and_zero(&dig_port->ddi_io_wakeref)); 2930 2931 intel_ddi_disable_clock(encoder); 2932 2933 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 2934 } 2935 2936 static void intel_ddi_post_disable(struct intel_atomic_state *state, 2937 struct intel_encoder *encoder, 2938 const struct intel_crtc_state *old_crtc_state, 2939 const struct drm_connector_state *old_conn_state) 2940 { 2941 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2942 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2943 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2944 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 2945 2946 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) { 2947 intel_crtc_vblank_off(old_crtc_state); 2948 2949 intel_disable_pipe(old_crtc_state); 2950 2951 intel_vrr_disable(old_crtc_state); 2952 2953 intel_ddi_disable_transcoder_func(old_crtc_state); 2954 2955 intel_dsc_disable(old_crtc_state); 2956 2957 if (DISPLAY_VER(dev_priv) >= 9) 2958 skl_scaler_disable(old_crtc_state); 2959 else 2960 ilk_pfit_disable(old_crtc_state); 2961 } 2962 2963 if (old_crtc_state->bigjoiner_linked_crtc) { 2964 struct intel_atomic_state *state = 2965 to_intel_atomic_state(old_crtc_state->uapi.state); 2966 struct intel_crtc *slave = 2967 old_crtc_state->bigjoiner_linked_crtc; 2968 const struct intel_crtc_state *old_slave_crtc_state = 2969 intel_atomic_get_old_crtc_state(state, slave); 2970 2971 intel_crtc_vblank_off(old_slave_crtc_state); 2972 2973 intel_dsc_disable(old_slave_crtc_state); 2974 skl_scaler_disable(old_slave_crtc_state); 2975 } 2976 2977 /* 2978 * When called from DP MST code: 2979 * - old_conn_state will be NULL 2980 * - encoder will be the main encoder (ie. mst->primary) 2981 * - the main connector associated with this port 2982 * won't be active or linked to a crtc 2983 * - old_crtc_state will be the state of the last stream to 2984 * be deactivated on this port, and it may not be the same 2985 * stream that was activated last, but each stream 2986 * should have a state that is identical when it comes to 2987 * the DP link parameteres 2988 */ 2989 2990 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 2991 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 2992 old_conn_state); 2993 else 2994 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 2995 old_conn_state); 2996 2997 if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port) 2998 intel_display_power_put(dev_priv, 2999 intel_ddi_main_link_aux_domain(dig_port), 3000 fetch_and_zero(&dig_port->aux_wakeref)); 3001 3002 if (is_tc_port) 3003 intel_tc_port_put_link(dig_port); 3004 } 3005 3006 void intel_ddi_fdi_post_disable(struct intel_atomic_state *state, 3007 struct intel_encoder *encoder, 3008 const struct intel_crtc_state *old_crtc_state, 3009 const struct drm_connector_state *old_conn_state) 3010 { 3011 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3012 u32 val; 3013 3014 /* 3015 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable) 3016 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN, 3017 * step 13 is the correct place for it. Step 18 is where it was 3018 * originally before the BUN. 3019 */ 3020 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 3021 val &= ~FDI_RX_ENABLE; 3022 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 3023 3024 intel_disable_ddi_buf(encoder, old_crtc_state); 3025 intel_ddi_disable_clock(encoder); 3026 3027 val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); 3028 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 3029 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 3030 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val); 3031 3032 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 3033 val &= ~FDI_PCDCLK; 3034 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 3035 3036 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 3037 val &= ~FDI_RX_PLL_ENABLE; 3038 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 3039 } 3040 3041 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 3042 struct intel_encoder *encoder, 3043 const struct intel_crtc_state *crtc_state) 3044 { 3045 const struct drm_connector_state *conn_state; 3046 struct drm_connector *conn; 3047 int i; 3048 3049 if (!crtc_state->sync_mode_slaves_mask) 3050 return; 3051 3052 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 3053 struct intel_encoder *slave_encoder = 3054 to_intel_encoder(conn_state->best_encoder); 3055 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 3056 const struct intel_crtc_state *slave_crtc_state; 3057 3058 if (!slave_crtc) 3059 continue; 3060 3061 slave_crtc_state = 3062 intel_atomic_get_new_crtc_state(state, slave_crtc); 3063 3064 if (slave_crtc_state->master_transcoder != 3065 crtc_state->cpu_transcoder) 3066 continue; 3067 3068 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 3069 slave_crtc_state); 3070 } 3071 3072 usleep_range(200, 400); 3073 3074 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 3075 crtc_state); 3076 } 3077 3078 static void intel_enable_ddi_dp(struct intel_atomic_state *state, 3079 struct intel_encoder *encoder, 3080 const struct intel_crtc_state *crtc_state, 3081 const struct drm_connector_state *conn_state) 3082 { 3083 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3084 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3085 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3086 enum port port = encoder->port; 3087 3088 if (port == PORT_A && DISPLAY_VER(dev_priv) < 9) 3089 intel_dp_stop_link_train(intel_dp, crtc_state); 3090 3091 intel_edp_backlight_on(crtc_state, conn_state); 3092 intel_psr_enable(intel_dp, crtc_state, conn_state); 3093 3094 if (!dig_port->lspcon.active || dig_port->dp.has_hdmi_sink) 3095 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3096 3097 intel_edp_drrs_enable(intel_dp, crtc_state); 3098 3099 if (crtc_state->has_audio) 3100 intel_audio_codec_enable(encoder, crtc_state, conn_state); 3101 3102 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3103 } 3104 3105 static i915_reg_t 3106 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 3107 enum port port) 3108 { 3109 static const enum transcoder trans[] = { 3110 [PORT_A] = TRANSCODER_EDP, 3111 [PORT_B] = TRANSCODER_A, 3112 [PORT_C] = TRANSCODER_B, 3113 [PORT_D] = TRANSCODER_C, 3114 [PORT_E] = TRANSCODER_A, 3115 }; 3116 3117 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9); 3118 3119 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) 3120 port = PORT_A; 3121 3122 return CHICKEN_TRANS(trans[port]); 3123 } 3124 3125 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, 3126 struct intel_encoder *encoder, 3127 const struct intel_crtc_state *crtc_state, 3128 const struct drm_connector_state *conn_state) 3129 { 3130 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3131 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3132 struct drm_connector *connector = conn_state->connector; 3133 int level = intel_ddi_hdmi_level(encoder, crtc_state); 3134 enum port port = encoder->port; 3135 3136 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3137 crtc_state->hdmi_high_tmds_clock_ratio, 3138 crtc_state->hdmi_scrambling)) 3139 drm_dbg_kms(&dev_priv->drm, 3140 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3141 connector->base.id, connector->name); 3142 3143 if (DISPLAY_VER(dev_priv) >= 12) 3144 tgl_ddi_vswing_sequence(encoder, crtc_state, level); 3145 else if (DISPLAY_VER(dev_priv) == 11) 3146 icl_ddi_vswing_sequence(encoder, crtc_state, level); 3147 else if (IS_CANNONLAKE(dev_priv)) 3148 cnl_ddi_vswing_sequence(encoder, crtc_state, level); 3149 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3150 bxt_ddi_vswing_sequence(encoder, crtc_state, level); 3151 else 3152 intel_prepare_hdmi_ddi_buffers(encoder, level); 3153 3154 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 3155 skl_ddi_set_iboost(encoder, crtc_state, level); 3156 3157 /* Display WA #1143: skl,kbl,cfl */ 3158 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { 3159 /* 3160 * For some reason these chicken bits have been 3161 * stuffed into a transcoder register, event though 3162 * the bits affect a specific DDI port rather than 3163 * a specific transcoder. 3164 */ 3165 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 3166 u32 val; 3167 3168 val = intel_de_read(dev_priv, reg); 3169 3170 if (port == PORT_E) 3171 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3172 DDIE_TRAINING_OVERRIDE_VALUE; 3173 else 3174 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3175 DDI_TRAINING_OVERRIDE_VALUE; 3176 3177 intel_de_write(dev_priv, reg, val); 3178 intel_de_posting_read(dev_priv, reg); 3179 3180 udelay(1); 3181 3182 if (port == PORT_E) 3183 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3184 DDIE_TRAINING_OVERRIDE_VALUE); 3185 else 3186 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3187 DDI_TRAINING_OVERRIDE_VALUE); 3188 3189 intel_de_write(dev_priv, reg, val); 3190 } 3191 3192 intel_ddi_power_up_lanes(encoder, crtc_state); 3193 3194 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3195 * are ignored so nothing special needs to be done besides 3196 * enabling the port. 3197 * 3198 * On ADL_P the PHY link rate and lane count must be programmed but 3199 * these are both 0 for HDMI. 3200 */ 3201 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3202 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE); 3203 3204 if (crtc_state->has_audio) 3205 intel_audio_codec_enable(encoder, crtc_state, conn_state); 3206 } 3207 3208 static void intel_enable_ddi(struct intel_atomic_state *state, 3209 struct intel_encoder *encoder, 3210 const struct intel_crtc_state *crtc_state, 3211 const struct drm_connector_state *conn_state) 3212 { 3213 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 3214 3215 if (!crtc_state->bigjoiner_slave) 3216 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3217 3218 intel_vrr_enable(encoder, crtc_state); 3219 3220 intel_enable_pipe(crtc_state); 3221 3222 intel_crtc_vblank_on(crtc_state); 3223 3224 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3225 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state); 3226 else 3227 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state); 3228 3229 /* Enable hdcp if it's desired */ 3230 if (conn_state->content_protection == 3231 DRM_MODE_CONTENT_PROTECTION_DESIRED) 3232 intel_hdcp_enable(to_intel_connector(conn_state->connector), 3233 crtc_state, 3234 (u8)conn_state->hdcp_content_type); 3235 } 3236 3237 static void intel_disable_ddi_dp(struct intel_atomic_state *state, 3238 struct intel_encoder *encoder, 3239 const struct intel_crtc_state *old_crtc_state, 3240 const struct drm_connector_state *old_conn_state) 3241 { 3242 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3243 3244 intel_dp->link_trained = false; 3245 3246 if (old_crtc_state->has_audio) 3247 intel_audio_codec_disable(encoder, 3248 old_crtc_state, old_conn_state); 3249 3250 intel_edp_drrs_disable(intel_dp, old_crtc_state); 3251 intel_psr_disable(intel_dp, old_crtc_state); 3252 intel_edp_backlight_off(old_conn_state); 3253 /* Disable the decompression in DP Sink */ 3254 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, 3255 false); 3256 /* Disable Ignore_MSA bit in DP Sink */ 3257 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 3258 false); 3259 } 3260 3261 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state, 3262 struct intel_encoder *encoder, 3263 const struct intel_crtc_state *old_crtc_state, 3264 const struct drm_connector_state *old_conn_state) 3265 { 3266 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3267 struct drm_connector *connector = old_conn_state->connector; 3268 3269 if (old_crtc_state->has_audio) 3270 intel_audio_codec_disable(encoder, 3271 old_crtc_state, old_conn_state); 3272 3273 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3274 false, false)) 3275 drm_dbg_kms(&i915->drm, 3276 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3277 connector->base.id, connector->name); 3278 } 3279 3280 static void intel_disable_ddi(struct intel_atomic_state *state, 3281 struct intel_encoder *encoder, 3282 const struct intel_crtc_state *old_crtc_state, 3283 const struct drm_connector_state *old_conn_state) 3284 { 3285 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3286 3287 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3288 intel_disable_ddi_hdmi(state, encoder, old_crtc_state, 3289 old_conn_state); 3290 else 3291 intel_disable_ddi_dp(state, encoder, old_crtc_state, 3292 old_conn_state); 3293 } 3294 3295 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3296 struct intel_encoder *encoder, 3297 const struct intel_crtc_state *crtc_state, 3298 const struct drm_connector_state *conn_state) 3299 { 3300 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3301 3302 intel_ddi_set_dp_msa(crtc_state, conn_state); 3303 3304 intel_psr_update(intel_dp, crtc_state, conn_state); 3305 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3306 intel_edp_drrs_update(intel_dp, crtc_state); 3307 3308 intel_panel_update_backlight(state, encoder, crtc_state, conn_state); 3309 } 3310 3311 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3312 struct intel_encoder *encoder, 3313 const struct intel_crtc_state *crtc_state, 3314 const struct drm_connector_state *conn_state) 3315 { 3316 3317 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3318 !intel_encoder_is_mst(encoder)) 3319 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3320 conn_state); 3321 3322 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3323 } 3324 3325 static void 3326 intel_ddi_update_prepare(struct intel_atomic_state *state, 3327 struct intel_encoder *encoder, 3328 struct intel_crtc *crtc) 3329 { 3330 struct intel_crtc_state *crtc_state = 3331 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL; 3332 int required_lanes = crtc_state ? crtc_state->lane_count : 1; 3333 3334 drm_WARN_ON(state->base.dev, crtc && crtc->active); 3335 3336 intel_tc_port_get_link(enc_to_dig_port(encoder), 3337 required_lanes); 3338 if (crtc_state && crtc_state->hw.active) 3339 intel_update_active_dpll(state, crtc, encoder); 3340 } 3341 3342 static void 3343 intel_ddi_update_complete(struct intel_atomic_state *state, 3344 struct intel_encoder *encoder, 3345 struct intel_crtc *crtc) 3346 { 3347 intel_tc_port_put_link(enc_to_dig_port(encoder)); 3348 } 3349 3350 static void 3351 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3352 struct intel_encoder *encoder, 3353 const struct intel_crtc_state *crtc_state, 3354 const struct drm_connector_state *conn_state) 3355 { 3356 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3357 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3358 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3359 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 3360 3361 if (is_tc_port) 3362 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3363 3364 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) { 3365 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref); 3366 dig_port->aux_wakeref = 3367 intel_display_power_get(dev_priv, 3368 intel_ddi_main_link_aux_domain(dig_port)); 3369 } 3370 3371 if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT) 3372 /* 3373 * Program the lane count for static/dynamic connections on 3374 * Type-C ports. Skip this step for TBT. 3375 */ 3376 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3377 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3378 bxt_ddi_phy_set_lane_optim_mask(encoder, 3379 crtc_state->lane_lat_optim_mask); 3380 } 3381 3382 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3383 const struct intel_crtc_state *crtc_state) 3384 { 3385 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3386 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3387 enum port port = encoder->port; 3388 u32 dp_tp_ctl, ddi_buf_ctl; 3389 bool wait = false; 3390 3391 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3392 3393 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 3394 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3395 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 3396 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3397 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 3398 wait = true; 3399 } 3400 3401 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 3402 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1; 3403 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3404 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3405 3406 if (wait) 3407 intel_wait_ddi_buf_idle(dev_priv, port); 3408 } 3409 3410 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3411 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3412 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3413 } else { 3414 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3415 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 3416 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3417 } 3418 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3419 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3420 3421 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3422 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3423 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3424 3425 intel_wait_ddi_buf_active(dev_priv, port); 3426 } 3427 3428 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3429 const struct intel_crtc_state *crtc_state, 3430 u8 dp_train_pat) 3431 { 3432 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3433 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3434 u32 temp; 3435 3436 temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3437 3438 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3439 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3440 case DP_TRAINING_PATTERN_DISABLE: 3441 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3442 break; 3443 case DP_TRAINING_PATTERN_1: 3444 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3445 break; 3446 case DP_TRAINING_PATTERN_2: 3447 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3448 break; 3449 case DP_TRAINING_PATTERN_3: 3450 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3451 break; 3452 case DP_TRAINING_PATTERN_4: 3453 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3454 break; 3455 } 3456 3457 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp); 3458 } 3459 3460 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3461 const struct intel_crtc_state *crtc_state) 3462 { 3463 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3464 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3465 enum port port = encoder->port; 3466 u32 val; 3467 3468 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3469 val &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3470 val |= DP_TP_CTL_LINK_TRAIN_IDLE; 3471 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 3472 3473 /* 3474 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3475 * reason we need to set idle transmission mode is to work around a HW 3476 * issue where we enable the pipe while not in idle link-training mode. 3477 * In this case there is requirement to wait for a minimum number of 3478 * idle patterns to be sent. 3479 */ 3480 if (port == PORT_A && DISPLAY_VER(dev_priv) < 12) 3481 return; 3482 3483 if (intel_de_wait_for_set(dev_priv, 3484 dp_tp_status_reg(encoder, crtc_state), 3485 DP_TP_STATUS_IDLE_DONE, 1)) 3486 drm_err(&dev_priv->drm, 3487 "Timed out waiting for DP idle patterns\n"); 3488 } 3489 3490 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 3491 enum transcoder cpu_transcoder) 3492 { 3493 if (cpu_transcoder == TRANSCODER_EDP) 3494 return false; 3495 3496 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) 3497 return false; 3498 3499 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 3500 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3501 } 3502 3503 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, 3504 struct intel_crtc_state *crtc_state) 3505 { 3506 if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000) 3507 crtc_state->min_voltage_level = 2; 3508 else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000) 3509 crtc_state->min_voltage_level = 3; 3510 else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000) 3511 crtc_state->min_voltage_level = 1; 3512 else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000) 3513 crtc_state->min_voltage_level = 2; 3514 } 3515 3516 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, 3517 enum transcoder cpu_transcoder) 3518 { 3519 u32 master_select; 3520 3521 if (DISPLAY_VER(dev_priv) >= 11) { 3522 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder)); 3523 3524 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3525 return INVALID_TRANSCODER; 3526 3527 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3528 } else { 3529 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3530 3531 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3532 return INVALID_TRANSCODER; 3533 3534 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3535 } 3536 3537 if (master_select == 0) 3538 return TRANSCODER_EDP; 3539 else 3540 return master_select - 1; 3541 } 3542 3543 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3544 { 3545 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3546 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3547 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3548 enum transcoder cpu_transcoder; 3549 3550 crtc_state->master_transcoder = 3551 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); 3552 3553 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { 3554 enum intel_display_power_domain power_domain; 3555 intel_wakeref_t trans_wakeref; 3556 3557 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3558 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 3559 power_domain); 3560 3561 if (!trans_wakeref) 3562 continue; 3563 3564 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == 3565 crtc_state->cpu_transcoder) 3566 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3567 3568 intel_display_power_put(dev_priv, power_domain, trans_wakeref); 3569 } 3570 3571 drm_WARN_ON(&dev_priv->drm, 3572 crtc_state->master_transcoder != INVALID_TRANSCODER && 3573 crtc_state->sync_mode_slaves_mask); 3574 } 3575 3576 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 3577 struct intel_crtc_state *pipe_config) 3578 { 3579 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3580 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); 3581 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3582 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3583 u32 temp, flags = 0; 3584 3585 temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3586 if (temp & TRANS_DDI_PHSYNC) 3587 flags |= DRM_MODE_FLAG_PHSYNC; 3588 else 3589 flags |= DRM_MODE_FLAG_NHSYNC; 3590 if (temp & TRANS_DDI_PVSYNC) 3591 flags |= DRM_MODE_FLAG_PVSYNC; 3592 else 3593 flags |= DRM_MODE_FLAG_NVSYNC; 3594 3595 pipe_config->hw.adjusted_mode.flags |= flags; 3596 3597 switch (temp & TRANS_DDI_BPC_MASK) { 3598 case TRANS_DDI_BPC_6: 3599 pipe_config->pipe_bpp = 18; 3600 break; 3601 case TRANS_DDI_BPC_8: 3602 pipe_config->pipe_bpp = 24; 3603 break; 3604 case TRANS_DDI_BPC_10: 3605 pipe_config->pipe_bpp = 30; 3606 break; 3607 case TRANS_DDI_BPC_12: 3608 pipe_config->pipe_bpp = 36; 3609 break; 3610 default: 3611 break; 3612 } 3613 3614 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 3615 case TRANS_DDI_MODE_SELECT_HDMI: 3616 pipe_config->has_hdmi_sink = true; 3617 3618 pipe_config->infoframes.enable |= 3619 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3620 3621 if (pipe_config->infoframes.enable) 3622 pipe_config->has_infoframe = true; 3623 3624 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 3625 pipe_config->hdmi_scrambling = true; 3626 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 3627 pipe_config->hdmi_high_tmds_clock_ratio = true; 3628 fallthrough; 3629 case TRANS_DDI_MODE_SELECT_DVI: 3630 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 3631 pipe_config->lane_count = 4; 3632 break; 3633 case TRANS_DDI_MODE_SELECT_FDI: 3634 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 3635 break; 3636 case TRANS_DDI_MODE_SELECT_DP_SST: 3637 if (encoder->type == INTEL_OUTPUT_EDP) 3638 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 3639 else 3640 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 3641 pipe_config->lane_count = 3642 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3643 intel_dp_get_m_n(intel_crtc, pipe_config); 3644 3645 if (DISPLAY_VER(dev_priv) >= 11) { 3646 i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config); 3647 3648 pipe_config->fec_enable = 3649 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE; 3650 3651 drm_dbg_kms(&dev_priv->drm, 3652 "[ENCODER:%d:%s] Fec status: %u\n", 3653 encoder->base.base.id, encoder->base.name, 3654 pipe_config->fec_enable); 3655 } 3656 3657 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) 3658 pipe_config->infoframes.enable |= 3659 intel_lspcon_infoframes_enabled(encoder, pipe_config); 3660 else 3661 pipe_config->infoframes.enable |= 3662 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3663 break; 3664 case TRANS_DDI_MODE_SELECT_DP_MST: 3665 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 3666 pipe_config->lane_count = 3667 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3668 3669 if (DISPLAY_VER(dev_priv) >= 12) 3670 pipe_config->mst_master_transcoder = 3671 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); 3672 3673 intel_dp_get_m_n(intel_crtc, pipe_config); 3674 3675 pipe_config->infoframes.enable |= 3676 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3677 break; 3678 default: 3679 break; 3680 } 3681 } 3682 3683 static void intel_ddi_get_config(struct intel_encoder *encoder, 3684 struct intel_crtc_state *pipe_config) 3685 { 3686 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3687 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3688 3689 /* XXX: DSI transcoder paranoia */ 3690 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 3691 return; 3692 3693 if (pipe_config->bigjoiner_slave) { 3694 /* read out pipe settings from master */ 3695 enum transcoder save = pipe_config->cpu_transcoder; 3696 3697 /* Our own transcoder needs to be disabled when reading it in intel_ddi_read_func_ctl() */ 3698 WARN_ON(pipe_config->output_types); 3699 pipe_config->cpu_transcoder = (enum transcoder)pipe_config->bigjoiner_linked_crtc->pipe; 3700 intel_ddi_read_func_ctl(encoder, pipe_config); 3701 pipe_config->cpu_transcoder = save; 3702 } else { 3703 intel_ddi_read_func_ctl(encoder, pipe_config); 3704 } 3705 3706 intel_ddi_mso_get_config(encoder, pipe_config); 3707 3708 pipe_config->has_audio = 3709 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 3710 3711 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp && 3712 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { 3713 /* 3714 * This is a big fat ugly hack. 3715 * 3716 * Some machines in UEFI boot mode provide us a VBT that has 18 3717 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 3718 * unknown we fail to light up. Yet the same BIOS boots up with 3719 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 3720 * max, not what it tells us to use. 3721 * 3722 * Note: This will still be broken if the eDP panel is not lit 3723 * up by the BIOS, and thus we can't get the mode at module 3724 * load. 3725 */ 3726 drm_dbg_kms(&dev_priv->drm, 3727 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 3728 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); 3729 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; 3730 } 3731 3732 if (!pipe_config->bigjoiner_slave) 3733 ddi_dotclock_get(pipe_config); 3734 3735 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3736 pipe_config->lane_lat_optim_mask = 3737 bxt_ddi_phy_get_lane_lat_optim_mask(encoder); 3738 3739 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 3740 3741 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 3742 3743 intel_read_infoframe(encoder, pipe_config, 3744 HDMI_INFOFRAME_TYPE_AVI, 3745 &pipe_config->infoframes.avi); 3746 intel_read_infoframe(encoder, pipe_config, 3747 HDMI_INFOFRAME_TYPE_SPD, 3748 &pipe_config->infoframes.spd); 3749 intel_read_infoframe(encoder, pipe_config, 3750 HDMI_INFOFRAME_TYPE_VENDOR, 3751 &pipe_config->infoframes.hdmi); 3752 intel_read_infoframe(encoder, pipe_config, 3753 HDMI_INFOFRAME_TYPE_DRM, 3754 &pipe_config->infoframes.drm); 3755 3756 if (DISPLAY_VER(dev_priv) >= 8) 3757 bdw_get_trans_port_sync_config(pipe_config); 3758 3759 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 3760 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 3761 3762 intel_psr_get_config(encoder, pipe_config); 3763 } 3764 3765 void intel_ddi_get_clock(struct intel_encoder *encoder, 3766 struct intel_crtc_state *crtc_state, 3767 struct intel_shared_dpll *pll) 3768 { 3769 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3770 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 3771 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 3772 bool pll_active; 3773 3774 if (drm_WARN_ON(&i915->drm, !pll)) 3775 return; 3776 3777 port_dpll->pll = pll; 3778 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 3779 drm_WARN_ON(&i915->drm, !pll_active); 3780 3781 icl_set_active_port_dpll(crtc_state, port_dpll_id); 3782 3783 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 3784 &crtc_state->dpll_hw_state); 3785 } 3786 3787 static void adls_ddi_get_config(struct intel_encoder *encoder, 3788 struct intel_crtc_state *crtc_state) 3789 { 3790 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 3791 intel_ddi_get_config(encoder, crtc_state); 3792 } 3793 3794 static void rkl_ddi_get_config(struct intel_encoder *encoder, 3795 struct intel_crtc_state *crtc_state) 3796 { 3797 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 3798 intel_ddi_get_config(encoder, crtc_state); 3799 } 3800 3801 static void dg1_ddi_get_config(struct intel_encoder *encoder, 3802 struct intel_crtc_state *crtc_state) 3803 { 3804 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 3805 intel_ddi_get_config(encoder, crtc_state); 3806 } 3807 3808 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 3809 struct intel_crtc_state *crtc_state) 3810 { 3811 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 3812 intel_ddi_get_config(encoder, crtc_state); 3813 } 3814 3815 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 3816 struct intel_crtc_state *crtc_state, 3817 struct intel_shared_dpll *pll) 3818 { 3819 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3820 enum icl_port_dpll_id port_dpll_id; 3821 struct icl_port_dpll *port_dpll; 3822 bool pll_active; 3823 3824 if (drm_WARN_ON(&i915->drm, !pll)) 3825 return; 3826 3827 if (intel_get_shared_dpll_id(i915, pll) == DPLL_ID_ICL_TBTPLL) 3828 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 3829 else 3830 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 3831 3832 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 3833 3834 port_dpll->pll = pll; 3835 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 3836 drm_WARN_ON(&i915->drm, !pll_active); 3837 3838 icl_set_active_port_dpll(crtc_state, port_dpll_id); 3839 3840 if (intel_get_shared_dpll_id(i915, crtc_state->shared_dpll) == DPLL_ID_ICL_TBTPLL) 3841 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port); 3842 else 3843 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 3844 &crtc_state->dpll_hw_state); 3845 } 3846 3847 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 3848 struct intel_crtc_state *crtc_state) 3849 { 3850 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 3851 intel_ddi_get_config(encoder, crtc_state); 3852 } 3853 3854 static void cnl_ddi_get_config(struct intel_encoder *encoder, 3855 struct intel_crtc_state *crtc_state) 3856 { 3857 intel_ddi_get_clock(encoder, crtc_state, cnl_ddi_get_pll(encoder)); 3858 intel_ddi_get_config(encoder, crtc_state); 3859 } 3860 3861 static void bxt_ddi_get_config(struct intel_encoder *encoder, 3862 struct intel_crtc_state *crtc_state) 3863 { 3864 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 3865 intel_ddi_get_config(encoder, crtc_state); 3866 } 3867 3868 static void skl_ddi_get_config(struct intel_encoder *encoder, 3869 struct intel_crtc_state *crtc_state) 3870 { 3871 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 3872 intel_ddi_get_config(encoder, crtc_state); 3873 } 3874 3875 void hsw_ddi_get_config(struct intel_encoder *encoder, 3876 struct intel_crtc_state *crtc_state) 3877 { 3878 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 3879 intel_ddi_get_config(encoder, crtc_state); 3880 } 3881 3882 static void intel_ddi_sync_state(struct intel_encoder *encoder, 3883 const struct intel_crtc_state *crtc_state) 3884 { 3885 if (intel_crtc_has_dp_encoder(crtc_state)) 3886 intel_dp_sync_state(encoder, crtc_state); 3887 } 3888 3889 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 3890 struct intel_crtc_state *crtc_state) 3891 { 3892 if (intel_crtc_has_dp_encoder(crtc_state)) 3893 return intel_dp_initial_fastset_check(encoder, crtc_state); 3894 3895 return true; 3896 } 3897 3898 static enum intel_output_type 3899 intel_ddi_compute_output_type(struct intel_encoder *encoder, 3900 struct intel_crtc_state *crtc_state, 3901 struct drm_connector_state *conn_state) 3902 { 3903 switch (conn_state->connector->connector_type) { 3904 case DRM_MODE_CONNECTOR_HDMIA: 3905 return INTEL_OUTPUT_HDMI; 3906 case DRM_MODE_CONNECTOR_eDP: 3907 return INTEL_OUTPUT_EDP; 3908 case DRM_MODE_CONNECTOR_DisplayPort: 3909 return INTEL_OUTPUT_DP; 3910 default: 3911 MISSING_CASE(conn_state->connector->connector_type); 3912 return INTEL_OUTPUT_UNUSED; 3913 } 3914 } 3915 3916 static int intel_ddi_compute_config(struct intel_encoder *encoder, 3917 struct intel_crtc_state *pipe_config, 3918 struct drm_connector_state *conn_state) 3919 { 3920 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3921 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3922 enum port port = encoder->port; 3923 int ret; 3924 3925 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 3926 pipe_config->cpu_transcoder = TRANSCODER_EDP; 3927 3928 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 3929 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 3930 } else { 3931 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 3932 } 3933 3934 if (ret) 3935 return ret; 3936 3937 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 3938 pipe_config->cpu_transcoder == TRANSCODER_EDP) 3939 pipe_config->pch_pfit.force_thru = 3940 pipe_config->pch_pfit.enabled || 3941 pipe_config->crc_enabled; 3942 3943 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3944 pipe_config->lane_lat_optim_mask = 3945 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 3946 3947 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 3948 3949 return 0; 3950 } 3951 3952 static bool mode_equal(const struct drm_display_mode *mode1, 3953 const struct drm_display_mode *mode2) 3954 { 3955 return drm_mode_match(mode1, mode2, 3956 DRM_MODE_MATCH_TIMINGS | 3957 DRM_MODE_MATCH_FLAGS | 3958 DRM_MODE_MATCH_3D_FLAGS) && 3959 mode1->clock == mode2->clock; /* we want an exact match */ 3960 } 3961 3962 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 3963 const struct intel_link_m_n *m_n_2) 3964 { 3965 return m_n_1->tu == m_n_2->tu && 3966 m_n_1->gmch_m == m_n_2->gmch_m && 3967 m_n_1->gmch_n == m_n_2->gmch_n && 3968 m_n_1->link_m == m_n_2->link_m && 3969 m_n_1->link_n == m_n_2->link_n; 3970 } 3971 3972 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 3973 const struct intel_crtc_state *crtc_state2) 3974 { 3975 return crtc_state1->hw.active && crtc_state2->hw.active && 3976 crtc_state1->output_types == crtc_state2->output_types && 3977 crtc_state1->output_format == crtc_state2->output_format && 3978 crtc_state1->lane_count == crtc_state2->lane_count && 3979 crtc_state1->port_clock == crtc_state2->port_clock && 3980 mode_equal(&crtc_state1->hw.adjusted_mode, 3981 &crtc_state2->hw.adjusted_mode) && 3982 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 3983 } 3984 3985 static u8 3986 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 3987 int tile_group_id) 3988 { 3989 struct drm_connector *connector; 3990 const struct drm_connector_state *conn_state; 3991 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 3992 struct intel_atomic_state *state = 3993 to_intel_atomic_state(ref_crtc_state->uapi.state); 3994 u8 transcoders = 0; 3995 int i; 3996 3997 /* 3998 * We don't enable port sync on BDW due to missing w/as and 3999 * due to not having adjusted the modeset sequence appropriately. 4000 */ 4001 if (DISPLAY_VER(dev_priv) < 9) 4002 return 0; 4003 4004 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4005 return 0; 4006 4007 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4008 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4009 const struct intel_crtc_state *crtc_state; 4010 4011 if (!crtc) 4012 continue; 4013 4014 if (!connector->has_tile || 4015 connector->tile_group->id != 4016 tile_group_id) 4017 continue; 4018 crtc_state = intel_atomic_get_new_crtc_state(state, 4019 crtc); 4020 if (!crtcs_port_sync_compatible(ref_crtc_state, 4021 crtc_state)) 4022 continue; 4023 transcoders |= BIT(crtc_state->cpu_transcoder); 4024 } 4025 4026 return transcoders; 4027 } 4028 4029 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 4030 struct intel_crtc_state *crtc_state, 4031 struct drm_connector_state *conn_state) 4032 { 4033 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4034 struct drm_connector *connector = conn_state->connector; 4035 u8 port_sync_transcoders = 0; 4036 4037 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]", 4038 encoder->base.base.id, encoder->base.name, 4039 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4040 4041 if (connector->has_tile) 4042 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4043 connector->tile_group->id); 4044 4045 /* 4046 * EDP Transcoders cannot be ensalved 4047 * make them a master always when present 4048 */ 4049 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4050 crtc_state->master_transcoder = TRANSCODER_EDP; 4051 else 4052 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4053 4054 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4055 crtc_state->master_transcoder = INVALID_TRANSCODER; 4056 crtc_state->sync_mode_slaves_mask = 4057 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4058 } 4059 4060 return 0; 4061 } 4062 4063 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4064 { 4065 struct drm_i915_private *i915 = to_i915(encoder->dev); 4066 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4067 4068 intel_dp_encoder_flush_work(encoder); 4069 intel_display_power_flush_work(i915); 4070 4071 drm_encoder_cleanup(encoder); 4072 if (dig_port) 4073 kfree(dig_port->hdcp_port_data.streams); 4074 kfree(dig_port); 4075 } 4076 4077 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 4078 { 4079 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 4080 4081 intel_dp->reset_link_params = true; 4082 4083 intel_pps_encoder_reset(intel_dp); 4084 } 4085 4086 static const struct drm_encoder_funcs intel_ddi_funcs = { 4087 .reset = intel_ddi_encoder_reset, 4088 .destroy = intel_ddi_encoder_destroy, 4089 }; 4090 4091 static struct intel_connector * 4092 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 4093 { 4094 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4095 struct intel_connector *connector; 4096 enum port port = dig_port->base.port; 4097 4098 connector = intel_connector_alloc(); 4099 if (!connector) 4100 return NULL; 4101 4102 dig_port->dp.output_reg = DDI_BUF_CTL(port); 4103 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 4104 dig_port->dp.set_link_train = intel_ddi_set_link_train; 4105 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4106 4107 if (DISPLAY_VER(dev_priv) >= 12) 4108 dig_port->dp.set_signal_levels = tgl_set_signal_levels; 4109 else if (DISPLAY_VER(dev_priv) >= 11) 4110 dig_port->dp.set_signal_levels = icl_set_signal_levels; 4111 else if (IS_CANNONLAKE(dev_priv)) 4112 dig_port->dp.set_signal_levels = cnl_set_signal_levels; 4113 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4114 dig_port->dp.set_signal_levels = bxt_set_signal_levels; 4115 else 4116 dig_port->dp.set_signal_levels = hsw_set_signal_levels; 4117 4118 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 4119 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 4120 4121 if (!intel_dp_init_connector(dig_port, connector)) { 4122 kfree(connector); 4123 return NULL; 4124 } 4125 4126 return connector; 4127 } 4128 4129 static int modeset_pipe(struct drm_crtc *crtc, 4130 struct drm_modeset_acquire_ctx *ctx) 4131 { 4132 struct drm_atomic_state *state; 4133 struct drm_crtc_state *crtc_state; 4134 int ret; 4135 4136 state = drm_atomic_state_alloc(crtc->dev); 4137 if (!state) 4138 return -ENOMEM; 4139 4140 state->acquire_ctx = ctx; 4141 4142 crtc_state = drm_atomic_get_crtc_state(state, crtc); 4143 if (IS_ERR(crtc_state)) { 4144 ret = PTR_ERR(crtc_state); 4145 goto out; 4146 } 4147 4148 crtc_state->connectors_changed = true; 4149 4150 ret = drm_atomic_commit(state); 4151 out: 4152 drm_atomic_state_put(state); 4153 4154 return ret; 4155 } 4156 4157 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4158 struct drm_modeset_acquire_ctx *ctx) 4159 { 4160 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4161 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4162 struct intel_connector *connector = hdmi->attached_connector; 4163 struct i2c_adapter *adapter = 4164 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 4165 struct drm_connector_state *conn_state; 4166 struct intel_crtc_state *crtc_state; 4167 struct intel_crtc *crtc; 4168 u8 config; 4169 int ret; 4170 4171 if (!connector || connector->base.status != connector_status_connected) 4172 return 0; 4173 4174 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 4175 ctx); 4176 if (ret) 4177 return ret; 4178 4179 conn_state = connector->base.state; 4180 4181 crtc = to_intel_crtc(conn_state->crtc); 4182 if (!crtc) 4183 return 0; 4184 4185 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4186 if (ret) 4187 return ret; 4188 4189 crtc_state = to_intel_crtc_state(crtc->base.state); 4190 4191 drm_WARN_ON(&dev_priv->drm, 4192 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4193 4194 if (!crtc_state->hw.active) 4195 return 0; 4196 4197 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4198 !crtc_state->hdmi_scrambling) 4199 return 0; 4200 4201 if (conn_state->commit && 4202 !try_wait_for_completion(&conn_state->commit->hw_done)) 4203 return 0; 4204 4205 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 4206 if (ret < 0) { 4207 drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n", 4208 ret); 4209 return 0; 4210 } 4211 4212 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4213 crtc_state->hdmi_high_tmds_clock_ratio && 4214 !!(config & SCDC_SCRAMBLING_ENABLE) == 4215 crtc_state->hdmi_scrambling) 4216 return 0; 4217 4218 /* 4219 * HDMI 2.0 says that one should not send scrambled data 4220 * prior to configuring the sink scrambling, and that 4221 * TMDS clock/data transmission should be suspended when 4222 * changing the TMDS clock rate in the sink. So let's 4223 * just do a full modeset here, even though some sinks 4224 * would be perfectly happy if were to just reconfigure 4225 * the SCDC settings on the fly. 4226 */ 4227 return modeset_pipe(&crtc->base, ctx); 4228 } 4229 4230 static enum intel_hotplug_state 4231 intel_ddi_hotplug(struct intel_encoder *encoder, 4232 struct intel_connector *connector) 4233 { 4234 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4235 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4236 struct intel_dp *intel_dp = &dig_port->dp; 4237 enum phy phy = intel_port_to_phy(i915, encoder->port); 4238 bool is_tc = intel_phy_is_tc(i915, phy); 4239 struct drm_modeset_acquire_ctx ctx; 4240 enum intel_hotplug_state state; 4241 int ret; 4242 4243 if (intel_dp->compliance.test_active && 4244 intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) { 4245 intel_dp_phy_test(encoder); 4246 /* just do the PHY test and nothing else */ 4247 return INTEL_HOTPLUG_UNCHANGED; 4248 } 4249 4250 state = intel_encoder_hotplug(encoder, connector); 4251 4252 drm_modeset_acquire_init(&ctx, 0); 4253 4254 for (;;) { 4255 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) 4256 ret = intel_hdmi_reset_link(encoder, &ctx); 4257 else 4258 ret = intel_dp_retrain_link(encoder, &ctx); 4259 4260 if (ret == -EDEADLK) { 4261 drm_modeset_backoff(&ctx); 4262 continue; 4263 } 4264 4265 break; 4266 } 4267 4268 drm_modeset_drop_locks(&ctx); 4269 drm_modeset_acquire_fini(&ctx); 4270 drm_WARN(encoder->base.dev, ret, 4271 "Acquiring modeset locks failed with %i\n", ret); 4272 4273 /* 4274 * Unpowered type-c dongles can take some time to boot and be 4275 * responsible, so here giving some time to those dongles to power up 4276 * and then retrying the probe. 4277 * 4278 * On many platforms the HDMI live state signal is known to be 4279 * unreliable, so we can't use it to detect if a sink is connected or 4280 * not. Instead we detect if it's connected based on whether we can 4281 * read the EDID or not. That in turn has a problem during disconnect, 4282 * since the HPD interrupt may be raised before the DDC lines get 4283 * disconnected (due to how the required length of DDC vs. HPD 4284 * connector pins are specified) and so we'll still be able to get a 4285 * valid EDID. To solve this schedule another detection cycle if this 4286 * time around we didn't detect any change in the sink's connection 4287 * status. 4288 * 4289 * Type-c connectors which get their HPD signal deasserted then 4290 * reasserted, without unplugging/replugging the sink from the 4291 * connector, introduce a delay until the AUX channel communication 4292 * becomes functional. Retry the detection for 5 seconds on type-c 4293 * connectors to account for this delay. 4294 */ 4295 if (state == INTEL_HOTPLUG_UNCHANGED && 4296 connector->hotplug_retries < (is_tc ? 5 : 1) && 4297 !dig_port->dp.is_mst) 4298 state = INTEL_HOTPLUG_RETRY; 4299 4300 return state; 4301 } 4302 4303 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4304 { 4305 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4306 u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin]; 4307 4308 return intel_de_read(dev_priv, SDEISR) & bit; 4309 } 4310 4311 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4312 { 4313 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4314 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; 4315 4316 return intel_de_read(dev_priv, DEISR) & bit; 4317 } 4318 4319 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4320 { 4321 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4322 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; 4323 4324 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; 4325 } 4326 4327 static struct intel_connector * 4328 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4329 { 4330 struct intel_connector *connector; 4331 enum port port = dig_port->base.port; 4332 4333 connector = intel_connector_alloc(); 4334 if (!connector) 4335 return NULL; 4336 4337 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4338 intel_hdmi_init_connector(dig_port, connector); 4339 4340 return connector; 4341 } 4342 4343 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4344 { 4345 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4346 4347 if (dig_port->base.port != PORT_A) 4348 return false; 4349 4350 if (dig_port->saved_port_bits & DDI_A_4_LANES) 4351 return false; 4352 4353 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4354 * supported configuration 4355 */ 4356 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4357 return true; 4358 4359 /* Cannonlake: Most of SKUs don't support DDI_E, and the only 4360 * one who does also have a full A/E split called 4361 * DDI_F what makes DDI_E useless. However for this 4362 * case let's trust VBT info. 4363 */ 4364 if (IS_CANNONLAKE(dev_priv) && 4365 !intel_bios_is_port_present(dev_priv, PORT_E)) 4366 return true; 4367 4368 return false; 4369 } 4370 4371 static int 4372 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4373 { 4374 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4375 enum port port = dig_port->base.port; 4376 int max_lanes = 4; 4377 4378 if (DISPLAY_VER(dev_priv) >= 11) 4379 return max_lanes; 4380 4381 if (port == PORT_A || port == PORT_E) { 4382 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4383 max_lanes = port == PORT_A ? 4 : 0; 4384 else 4385 /* Both A and E share 2 lanes */ 4386 max_lanes = 2; 4387 } 4388 4389 /* 4390 * Some BIOS might fail to set this bit on port A if eDP 4391 * wasn't lit up at boot. Force this bit set when needed 4392 * so we use the proper lane count for our calculations. 4393 */ 4394 if (intel_ddi_a_force_4_lanes(dig_port)) { 4395 drm_dbg_kms(&dev_priv->drm, 4396 "Forcing DDI_A_4_LANES for port A\n"); 4397 dig_port->saved_port_bits |= DDI_A_4_LANES; 4398 max_lanes = 4; 4399 } 4400 4401 return max_lanes; 4402 } 4403 4404 static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy) 4405 { 4406 return i915->hti_state & HDPORT_ENABLED && 4407 i915->hti_state & HDPORT_DDI_USED(phy); 4408 } 4409 4410 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv, 4411 enum port port) 4412 { 4413 if (port >= PORT_D_XELPD) 4414 return HPD_PORT_D + port - PORT_D_XELPD; 4415 else if (port >= PORT_TC1) 4416 return HPD_PORT_TC1 + port - PORT_TC1; 4417 else 4418 return HPD_PORT_A + port - PORT_A; 4419 } 4420 4421 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, 4422 enum port port) 4423 { 4424 if (port >= PORT_TC1) 4425 return HPD_PORT_C + port - PORT_TC1; 4426 else 4427 return HPD_PORT_A + port - PORT_A; 4428 } 4429 4430 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, 4431 enum port port) 4432 { 4433 if (port >= PORT_TC1) 4434 return HPD_PORT_TC1 + port - PORT_TC1; 4435 else 4436 return HPD_PORT_A + port - PORT_A; 4437 } 4438 4439 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, 4440 enum port port) 4441 { 4442 if (HAS_PCH_TGP(dev_priv)) 4443 return tgl_hpd_pin(dev_priv, port); 4444 4445 if (port >= PORT_TC1) 4446 return HPD_PORT_C + port - PORT_TC1; 4447 else 4448 return HPD_PORT_A + port - PORT_A; 4449 } 4450 4451 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, 4452 enum port port) 4453 { 4454 if (port >= PORT_C) 4455 return HPD_PORT_TC1 + port - PORT_C; 4456 else 4457 return HPD_PORT_A + port - PORT_A; 4458 } 4459 4460 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, 4461 enum port port) 4462 { 4463 if (port == PORT_D) 4464 return HPD_PORT_A; 4465 4466 if (HAS_PCH_MCC(dev_priv)) 4467 return icl_hpd_pin(dev_priv, port); 4468 4469 return HPD_PORT_A + port - PORT_A; 4470 } 4471 4472 static enum hpd_pin cnl_hpd_pin(struct drm_i915_private *dev_priv, 4473 enum port port) 4474 { 4475 if (port == PORT_F) 4476 return HPD_PORT_E; 4477 4478 return HPD_PORT_A + port - PORT_A; 4479 } 4480 4481 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) 4482 { 4483 if (HAS_PCH_TGP(dev_priv)) 4484 return icl_hpd_pin(dev_priv, port); 4485 4486 return HPD_PORT_A + port - PORT_A; 4487 } 4488 4489 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port) 4490 { 4491 if (DISPLAY_VER(i915) >= 12) 4492 return port >= PORT_TC1; 4493 else if (DISPLAY_VER(i915) >= 11) 4494 return port >= PORT_C; 4495 else 4496 return false; 4497 } 4498 4499 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 4500 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 4501 4502 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 4503 { 4504 struct intel_digital_port *dig_port; 4505 struct intel_encoder *encoder; 4506 const struct intel_bios_encoder_data *devdata; 4507 bool init_hdmi, init_dp; 4508 enum phy phy = intel_port_to_phy(dev_priv, port); 4509 4510 /* 4511 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 4512 * have taken over some of the PHYs and made them unavailable to the 4513 * driver. In that case we should skip initializing the corresponding 4514 * outputs. 4515 */ 4516 if (hti_uses_phy(dev_priv, phy)) { 4517 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", 4518 port_name(port), phy_name(phy)); 4519 return; 4520 } 4521 4522 devdata = intel_bios_encoder_data_lookup(dev_priv, port); 4523 if (!devdata) { 4524 drm_dbg_kms(&dev_priv->drm, 4525 "VBT says port %c is not present\n", 4526 port_name(port)); 4527 return; 4528 } 4529 4530 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 4531 intel_bios_encoder_supports_hdmi(devdata); 4532 init_dp = intel_bios_encoder_supports_dp(devdata); 4533 4534 if (intel_bios_is_lspcon_present(dev_priv, port)) { 4535 /* 4536 * Lspcon device needs to be driven with DP connector 4537 * with special detection sequence. So make sure DP 4538 * is initialized before lspcon. 4539 */ 4540 init_dp = true; 4541 init_hdmi = false; 4542 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", 4543 port_name(port)); 4544 } 4545 4546 if (!init_dp && !init_hdmi) { 4547 drm_dbg_kms(&dev_priv->drm, 4548 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 4549 port_name(port)); 4550 return; 4551 } 4552 4553 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 4554 if (!dig_port) 4555 return; 4556 4557 encoder = &dig_port->base; 4558 encoder->devdata = devdata; 4559 4560 if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) { 4561 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4562 DRM_MODE_ENCODER_TMDS, 4563 "DDI %c/PHY %c", 4564 port_name(port - PORT_D_XELPD + PORT_D), 4565 phy_name(phy)); 4566 } else if (DISPLAY_VER(dev_priv) >= 12) { 4567 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4568 4569 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4570 DRM_MODE_ENCODER_TMDS, 4571 "DDI %s%c/PHY %s%c", 4572 port >= PORT_TC1 ? "TC" : "", 4573 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 4574 tc_port != TC_PORT_NONE ? "TC" : "", 4575 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4576 } else if (DISPLAY_VER(dev_priv) >= 11) { 4577 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4578 4579 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4580 DRM_MODE_ENCODER_TMDS, 4581 "DDI %c%s/PHY %s%c", 4582 port_name(port), 4583 port >= PORT_C ? " (TC)" : "", 4584 tc_port != TC_PORT_NONE ? "TC" : "", 4585 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4586 } else { 4587 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4588 DRM_MODE_ENCODER_TMDS, 4589 "DDI %c/PHY %c", port_name(port), phy_name(phy)); 4590 } 4591 4592 mutex_init(&dig_port->hdcp_mutex); 4593 dig_port->num_hdcp_streams = 0; 4594 4595 encoder->hotplug = intel_ddi_hotplug; 4596 encoder->compute_output_type = intel_ddi_compute_output_type; 4597 encoder->compute_config = intel_ddi_compute_config; 4598 encoder->compute_config_late = intel_ddi_compute_config_late; 4599 encoder->enable = intel_enable_ddi; 4600 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 4601 encoder->pre_enable = intel_ddi_pre_enable; 4602 encoder->disable = intel_disable_ddi; 4603 encoder->post_disable = intel_ddi_post_disable; 4604 encoder->update_pipe = intel_ddi_update_pipe; 4605 encoder->get_hw_state = intel_ddi_get_hw_state; 4606 encoder->sync_state = intel_ddi_sync_state; 4607 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 4608 encoder->suspend = intel_dp_encoder_suspend; 4609 encoder->shutdown = intel_dp_encoder_shutdown; 4610 encoder->get_power_domains = intel_ddi_get_power_domains; 4611 4612 encoder->type = INTEL_OUTPUT_DDI; 4613 encoder->power_domain = intel_port_to_power_domain(port); 4614 encoder->port = port; 4615 encoder->cloneable = 0; 4616 encoder->pipe_mask = ~0; 4617 4618 if (IS_ALDERLAKE_S(dev_priv)) { 4619 encoder->enable_clock = adls_ddi_enable_clock; 4620 encoder->disable_clock = adls_ddi_disable_clock; 4621 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 4622 encoder->get_config = adls_ddi_get_config; 4623 } else if (IS_ROCKETLAKE(dev_priv)) { 4624 encoder->enable_clock = rkl_ddi_enable_clock; 4625 encoder->disable_clock = rkl_ddi_disable_clock; 4626 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 4627 encoder->get_config = rkl_ddi_get_config; 4628 } else if (IS_DG1(dev_priv)) { 4629 encoder->enable_clock = dg1_ddi_enable_clock; 4630 encoder->disable_clock = dg1_ddi_disable_clock; 4631 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 4632 encoder->get_config = dg1_ddi_get_config; 4633 } else if (IS_JSL_EHL(dev_priv)) { 4634 if (intel_ddi_is_tc(dev_priv, port)) { 4635 encoder->enable_clock = jsl_ddi_tc_enable_clock; 4636 encoder->disable_clock = jsl_ddi_tc_disable_clock; 4637 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 4638 encoder->get_config = icl_ddi_combo_get_config; 4639 } else { 4640 encoder->enable_clock = icl_ddi_combo_enable_clock; 4641 encoder->disable_clock = icl_ddi_combo_disable_clock; 4642 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 4643 encoder->get_config = icl_ddi_combo_get_config; 4644 } 4645 } else if (DISPLAY_VER(dev_priv) >= 11) { 4646 if (intel_ddi_is_tc(dev_priv, port)) { 4647 encoder->enable_clock = icl_ddi_tc_enable_clock; 4648 encoder->disable_clock = icl_ddi_tc_disable_clock; 4649 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 4650 encoder->get_config = icl_ddi_tc_get_config; 4651 } else { 4652 encoder->enable_clock = icl_ddi_combo_enable_clock; 4653 encoder->disable_clock = icl_ddi_combo_disable_clock; 4654 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 4655 encoder->get_config = icl_ddi_combo_get_config; 4656 } 4657 } else if (IS_CANNONLAKE(dev_priv)) { 4658 encoder->enable_clock = cnl_ddi_enable_clock; 4659 encoder->disable_clock = cnl_ddi_disable_clock; 4660 encoder->is_clock_enabled = cnl_ddi_is_clock_enabled; 4661 encoder->get_config = cnl_ddi_get_config; 4662 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 4663 /* BXT/GLK have fixed PLL->port mapping */ 4664 encoder->get_config = bxt_ddi_get_config; 4665 } else if (DISPLAY_VER(dev_priv) == 9) { 4666 encoder->enable_clock = skl_ddi_enable_clock; 4667 encoder->disable_clock = skl_ddi_disable_clock; 4668 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 4669 encoder->get_config = skl_ddi_get_config; 4670 } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 4671 encoder->enable_clock = hsw_ddi_enable_clock; 4672 encoder->disable_clock = hsw_ddi_disable_clock; 4673 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 4674 encoder->get_config = hsw_ddi_get_config; 4675 } 4676 4677 if (DISPLAY_VER(dev_priv) >= 13) 4678 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port); 4679 else if (IS_DG1(dev_priv)) 4680 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); 4681 else if (IS_ROCKETLAKE(dev_priv)) 4682 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); 4683 else if (DISPLAY_VER(dev_priv) >= 12) 4684 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); 4685 else if (IS_JSL_EHL(dev_priv)) 4686 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); 4687 else if (DISPLAY_VER(dev_priv) == 11) 4688 encoder->hpd_pin = icl_hpd_pin(dev_priv, port); 4689 else if (IS_CANNONLAKE(dev_priv)) 4690 encoder->hpd_pin = cnl_hpd_pin(dev_priv, port); 4691 else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 4692 encoder->hpd_pin = skl_hpd_pin(dev_priv, port); 4693 else 4694 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 4695 4696 if (DISPLAY_VER(dev_priv) >= 11) 4697 dig_port->saved_port_bits = 4698 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 4699 & DDI_BUF_PORT_REVERSAL; 4700 else 4701 dig_port->saved_port_bits = 4702 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 4703 & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 4704 4705 if (intel_bios_is_lane_reversal_needed(dev_priv, port)) 4706 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL; 4707 4708 dig_port->dp.output_reg = INVALID_MMIO_REG; 4709 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 4710 dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 4711 4712 if (intel_phy_is_tc(dev_priv, phy)) { 4713 bool is_legacy = 4714 !intel_bios_encoder_supports_typec_usb(devdata) && 4715 !intel_bios_encoder_supports_tbt(devdata); 4716 4717 intel_tc_port_init(dig_port, is_legacy); 4718 4719 encoder->update_prepare = intel_ddi_update_prepare; 4720 encoder->update_complete = intel_ddi_update_complete; 4721 } 4722 4723 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 4724 dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO + 4725 port - PORT_A; 4726 4727 if (init_dp) { 4728 if (!intel_ddi_init_dp_connector(dig_port)) 4729 goto err; 4730 4731 dig_port->hpd_pulse = intel_dp_hpd_pulse; 4732 4733 /* Splitter enable for eDP MSO is limited to certain pipes. */ 4734 if (dig_port->dp.mso_link_count) { 4735 encoder->pipe_mask = BIT(PIPE_A); 4736 if (IS_ALDERLAKE_P(dev_priv)) 4737 encoder->pipe_mask |= BIT(PIPE_B); 4738 } 4739 } 4740 4741 /* In theory we don't need the encoder->type check, but leave it just in 4742 * case we have some really bad VBTs... */ 4743 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 4744 if (!intel_ddi_init_hdmi_connector(dig_port)) 4745 goto err; 4746 } 4747 4748 if (DISPLAY_VER(dev_priv) >= 11) { 4749 if (intel_phy_is_tc(dev_priv, phy)) 4750 dig_port->connected = intel_tc_port_connected; 4751 else 4752 dig_port->connected = lpt_digital_port_connected; 4753 } else if (DISPLAY_VER(dev_priv) >= 8) { 4754 if (port == PORT_A || IS_GEMINILAKE(dev_priv) || 4755 IS_BROXTON(dev_priv)) 4756 dig_port->connected = bdw_digital_port_connected; 4757 else 4758 dig_port->connected = lpt_digital_port_connected; 4759 } else { 4760 if (port == PORT_A) 4761 dig_port->connected = hsw_digital_port_connected; 4762 else 4763 dig_port->connected = lpt_digital_port_connected; 4764 } 4765 4766 intel_infoframe_init(dig_port); 4767 4768 return; 4769 4770 err: 4771 drm_encoder_cleanup(&encoder->base); 4772 kfree(dig_port); 4773 } 4774