1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <drm/drm_scdc_helper.h> 29 30 #include "i915_drv.h" 31 #include "intel_audio.h" 32 #include "intel_combo_phy.h" 33 #include "intel_connector.h" 34 #include "intel_ddi.h" 35 #include "intel_display_types.h" 36 #include "intel_dp.h" 37 #include "intel_dp_mst.h" 38 #include "intel_dp_link_training.h" 39 #include "intel_dpio_phy.h" 40 #include "intel_dsi.h" 41 #include "intel_fifo_underrun.h" 42 #include "intel_gmbus.h" 43 #include "intel_hdcp.h" 44 #include "intel_hdmi.h" 45 #include "intel_hotplug.h" 46 #include "intel_lspcon.h" 47 #include "intel_panel.h" 48 #include "intel_psr.h" 49 #include "intel_sprite.h" 50 #include "intel_tc.h" 51 #include "intel_vdsc.h" 52 53 struct ddi_buf_trans { 54 u32 trans1; /* balance leg enable, de-emph level */ 55 u32 trans2; /* vref sel, vswing */ 56 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */ 57 }; 58 59 static const u8 index_to_dp_signal_levels[] = { 60 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 61 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 62 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 63 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 64 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 65 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 66 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 67 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 68 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 69 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 70 }; 71 72 /* HDMI/DVI modes ignore everything but the last 2 items. So we share 73 * them for both DP and FDI transports, allowing those ports to 74 * automatically adapt to HDMI connections as well 75 */ 76 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { 77 { 0x00FFFFFF, 0x0006000E, 0x0 }, 78 { 0x00D75FFF, 0x0005000A, 0x0 }, 79 { 0x00C30FFF, 0x00040006, 0x0 }, 80 { 0x80AAAFFF, 0x000B0000, 0x0 }, 81 { 0x00FFFFFF, 0x0005000A, 0x0 }, 82 { 0x00D75FFF, 0x000C0004, 0x0 }, 83 { 0x80C30FFF, 0x000B0000, 0x0 }, 84 { 0x00FFFFFF, 0x00040006, 0x0 }, 85 { 0x80D75FFF, 0x000B0000, 0x0 }, 86 }; 87 88 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { 89 { 0x00FFFFFF, 0x0007000E, 0x0 }, 90 { 0x00D75FFF, 0x000F000A, 0x0 }, 91 { 0x00C30FFF, 0x00060006, 0x0 }, 92 { 0x00AAAFFF, 0x001E0000, 0x0 }, 93 { 0x00FFFFFF, 0x000F000A, 0x0 }, 94 { 0x00D75FFF, 0x00160004, 0x0 }, 95 { 0x00C30FFF, 0x001E0000, 0x0 }, 96 { 0x00FFFFFF, 0x00060006, 0x0 }, 97 { 0x00D75FFF, 0x001E0000, 0x0 }, 98 }; 99 100 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { 101 /* Idx NT mV d T mV d db */ 102 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */ 103 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */ 104 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */ 105 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */ 106 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */ 107 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */ 108 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */ 109 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */ 110 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */ 111 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */ 112 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */ 113 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */ 114 }; 115 116 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { 117 { 0x00FFFFFF, 0x00000012, 0x0 }, 118 { 0x00EBAFFF, 0x00020011, 0x0 }, 119 { 0x00C71FFF, 0x0006000F, 0x0 }, 120 { 0x00AAAFFF, 0x000E000A, 0x0 }, 121 { 0x00FFFFFF, 0x00020011, 0x0 }, 122 { 0x00DB6FFF, 0x0005000F, 0x0 }, 123 { 0x00BEEFFF, 0x000A000C, 0x0 }, 124 { 0x00FFFFFF, 0x0005000F, 0x0 }, 125 { 0x00DB6FFF, 0x000A000C, 0x0 }, 126 }; 127 128 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { 129 { 0x00FFFFFF, 0x0007000E, 0x0 }, 130 { 0x00D75FFF, 0x000E000A, 0x0 }, 131 { 0x00BEFFFF, 0x00140006, 0x0 }, 132 { 0x80B2CFFF, 0x001B0002, 0x0 }, 133 { 0x00FFFFFF, 0x000E000A, 0x0 }, 134 { 0x00DB6FFF, 0x00160005, 0x0 }, 135 { 0x80C71FFF, 0x001A0002, 0x0 }, 136 { 0x00F7DFFF, 0x00180004, 0x0 }, 137 { 0x80D75FFF, 0x001B0002, 0x0 }, 138 }; 139 140 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { 141 { 0x00FFFFFF, 0x0001000E, 0x0 }, 142 { 0x00D75FFF, 0x0004000A, 0x0 }, 143 { 0x00C30FFF, 0x00070006, 0x0 }, 144 { 0x00AAAFFF, 0x000C0000, 0x0 }, 145 { 0x00FFFFFF, 0x0004000A, 0x0 }, 146 { 0x00D75FFF, 0x00090004, 0x0 }, 147 { 0x00C30FFF, 0x000C0000, 0x0 }, 148 { 0x00FFFFFF, 0x00070006, 0x0 }, 149 { 0x00D75FFF, 0x000C0000, 0x0 }, 150 }; 151 152 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { 153 /* Idx NT mV d T mV df db */ 154 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */ 155 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */ 156 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */ 157 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */ 158 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */ 159 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */ 160 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */ 161 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */ 162 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */ 163 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */ 164 }; 165 166 /* Skylake H and S */ 167 static const struct ddi_buf_trans skl_ddi_translations_dp[] = { 168 { 0x00002016, 0x000000A0, 0x0 }, 169 { 0x00005012, 0x0000009B, 0x0 }, 170 { 0x00007011, 0x00000088, 0x0 }, 171 { 0x80009010, 0x000000C0, 0x1 }, 172 { 0x00002016, 0x0000009B, 0x0 }, 173 { 0x00005012, 0x00000088, 0x0 }, 174 { 0x80007011, 0x000000C0, 0x1 }, 175 { 0x00002016, 0x000000DF, 0x0 }, 176 { 0x80005012, 0x000000C0, 0x1 }, 177 }; 178 179 /* Skylake U */ 180 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { 181 { 0x0000201B, 0x000000A2, 0x0 }, 182 { 0x00005012, 0x00000088, 0x0 }, 183 { 0x80007011, 0x000000CD, 0x1 }, 184 { 0x80009010, 0x000000C0, 0x1 }, 185 { 0x0000201B, 0x0000009D, 0x0 }, 186 { 0x80005012, 0x000000C0, 0x1 }, 187 { 0x80007011, 0x000000C0, 0x1 }, 188 { 0x00002016, 0x00000088, 0x0 }, 189 { 0x80005012, 0x000000C0, 0x1 }, 190 }; 191 192 /* Skylake Y */ 193 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { 194 { 0x00000018, 0x000000A2, 0x0 }, 195 { 0x00005012, 0x00000088, 0x0 }, 196 { 0x80007011, 0x000000CD, 0x3 }, 197 { 0x80009010, 0x000000C0, 0x3 }, 198 { 0x00000018, 0x0000009D, 0x0 }, 199 { 0x80005012, 0x000000C0, 0x3 }, 200 { 0x80007011, 0x000000C0, 0x3 }, 201 { 0x00000018, 0x00000088, 0x0 }, 202 { 0x80005012, 0x000000C0, 0x3 }, 203 }; 204 205 /* Kabylake H and S */ 206 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = { 207 { 0x00002016, 0x000000A0, 0x0 }, 208 { 0x00005012, 0x0000009B, 0x0 }, 209 { 0x00007011, 0x00000088, 0x0 }, 210 { 0x80009010, 0x000000C0, 0x1 }, 211 { 0x00002016, 0x0000009B, 0x0 }, 212 { 0x00005012, 0x00000088, 0x0 }, 213 { 0x80007011, 0x000000C0, 0x1 }, 214 { 0x00002016, 0x00000097, 0x0 }, 215 { 0x80005012, 0x000000C0, 0x1 }, 216 }; 217 218 /* Kabylake U */ 219 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = { 220 { 0x0000201B, 0x000000A1, 0x0 }, 221 { 0x00005012, 0x00000088, 0x0 }, 222 { 0x80007011, 0x000000CD, 0x3 }, 223 { 0x80009010, 0x000000C0, 0x3 }, 224 { 0x0000201B, 0x0000009D, 0x0 }, 225 { 0x80005012, 0x000000C0, 0x3 }, 226 { 0x80007011, 0x000000C0, 0x3 }, 227 { 0x00002016, 0x0000004F, 0x0 }, 228 { 0x80005012, 0x000000C0, 0x3 }, 229 }; 230 231 /* Kabylake Y */ 232 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = { 233 { 0x00001017, 0x000000A1, 0x0 }, 234 { 0x00005012, 0x00000088, 0x0 }, 235 { 0x80007011, 0x000000CD, 0x3 }, 236 { 0x8000800F, 0x000000C0, 0x3 }, 237 { 0x00001017, 0x0000009D, 0x0 }, 238 { 0x80005012, 0x000000C0, 0x3 }, 239 { 0x80007011, 0x000000C0, 0x3 }, 240 { 0x00001017, 0x0000004C, 0x0 }, 241 { 0x80005012, 0x000000C0, 0x3 }, 242 }; 243 244 /* 245 * Skylake/Kabylake H and S 246 * eDP 1.4 low vswing translation parameters 247 */ 248 static const struct ddi_buf_trans skl_ddi_translations_edp[] = { 249 { 0x00000018, 0x000000A8, 0x0 }, 250 { 0x00004013, 0x000000A9, 0x0 }, 251 { 0x00007011, 0x000000A2, 0x0 }, 252 { 0x00009010, 0x0000009C, 0x0 }, 253 { 0x00000018, 0x000000A9, 0x0 }, 254 { 0x00006013, 0x000000A2, 0x0 }, 255 { 0x00007011, 0x000000A6, 0x0 }, 256 { 0x00000018, 0x000000AB, 0x0 }, 257 { 0x00007013, 0x0000009F, 0x0 }, 258 { 0x00000018, 0x000000DF, 0x0 }, 259 }; 260 261 /* 262 * Skylake/Kabylake U 263 * eDP 1.4 low vswing translation parameters 264 */ 265 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = { 266 { 0x00000018, 0x000000A8, 0x0 }, 267 { 0x00004013, 0x000000A9, 0x0 }, 268 { 0x00007011, 0x000000A2, 0x0 }, 269 { 0x00009010, 0x0000009C, 0x0 }, 270 { 0x00000018, 0x000000A9, 0x0 }, 271 { 0x00006013, 0x000000A2, 0x0 }, 272 { 0x00007011, 0x000000A6, 0x0 }, 273 { 0x00002016, 0x000000AB, 0x0 }, 274 { 0x00005013, 0x0000009F, 0x0 }, 275 { 0x00000018, 0x000000DF, 0x0 }, 276 }; 277 278 /* 279 * Skylake/Kabylake Y 280 * eDP 1.4 low vswing translation parameters 281 */ 282 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = { 283 { 0x00000018, 0x000000A8, 0x0 }, 284 { 0x00004013, 0x000000AB, 0x0 }, 285 { 0x00007011, 0x000000A4, 0x0 }, 286 { 0x00009010, 0x000000DF, 0x0 }, 287 { 0x00000018, 0x000000AA, 0x0 }, 288 { 0x00006013, 0x000000A4, 0x0 }, 289 { 0x00007011, 0x0000009D, 0x0 }, 290 { 0x00000018, 0x000000A0, 0x0 }, 291 { 0x00006012, 0x000000DF, 0x0 }, 292 { 0x00000018, 0x0000008A, 0x0 }, 293 }; 294 295 /* Skylake/Kabylake U, H and S */ 296 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { 297 { 0x00000018, 0x000000AC, 0x0 }, 298 { 0x00005012, 0x0000009D, 0x0 }, 299 { 0x00007011, 0x00000088, 0x0 }, 300 { 0x00000018, 0x000000A1, 0x0 }, 301 { 0x00000018, 0x00000098, 0x0 }, 302 { 0x00004013, 0x00000088, 0x0 }, 303 { 0x80006012, 0x000000CD, 0x1 }, 304 { 0x00000018, 0x000000DF, 0x0 }, 305 { 0x80003015, 0x000000CD, 0x1 }, /* Default */ 306 { 0x80003015, 0x000000C0, 0x1 }, 307 { 0x80000018, 0x000000C0, 0x1 }, 308 }; 309 310 /* Skylake/Kabylake Y */ 311 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { 312 { 0x00000018, 0x000000A1, 0x0 }, 313 { 0x00005012, 0x000000DF, 0x0 }, 314 { 0x80007011, 0x000000CB, 0x3 }, 315 { 0x00000018, 0x000000A4, 0x0 }, 316 { 0x00000018, 0x0000009D, 0x0 }, 317 { 0x00004013, 0x00000080, 0x0 }, 318 { 0x80006013, 0x000000C0, 0x3 }, 319 { 0x00000018, 0x0000008A, 0x0 }, 320 { 0x80003015, 0x000000C0, 0x3 }, /* Default */ 321 { 0x80003015, 0x000000C0, 0x3 }, 322 { 0x80000018, 0x000000C0, 0x3 }, 323 }; 324 325 struct bxt_ddi_buf_trans { 326 u8 margin; /* swing value */ 327 u8 scale; /* scale value */ 328 u8 enable; /* scale enable */ 329 u8 deemphasis; 330 }; 331 332 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { 333 /* Idx NT mV diff db */ 334 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ 335 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */ 336 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */ 337 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */ 338 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */ 339 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */ 340 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */ 341 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */ 342 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */ 343 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */ 344 }; 345 346 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = { 347 /* Idx NT mV diff db */ 348 { 26, 0, 0, 128, }, /* 0: 200 0 */ 349 { 38, 0, 0, 112, }, /* 1: 200 1.5 */ 350 { 48, 0, 0, 96, }, /* 2: 200 4 */ 351 { 54, 0, 0, 69, }, /* 3: 200 6 */ 352 { 32, 0, 0, 128, }, /* 4: 250 0 */ 353 { 48, 0, 0, 104, }, /* 5: 250 1.5 */ 354 { 54, 0, 0, 85, }, /* 6: 250 4 */ 355 { 43, 0, 0, 128, }, /* 7: 300 0 */ 356 { 54, 0, 0, 101, }, /* 8: 300 1.5 */ 357 { 48, 0, 0, 128, }, /* 9: 300 0 */ 358 }; 359 360 /* BSpec has 2 recommended values - entries 0 and 8. 361 * Using the entry with higher vswing. 362 */ 363 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = { 364 /* Idx NT mV diff db */ 365 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ 366 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */ 367 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */ 368 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */ 369 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */ 370 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */ 371 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */ 372 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */ 373 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */ 374 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */ 375 }; 376 377 struct cnl_ddi_buf_trans { 378 u8 dw2_swing_sel; 379 u8 dw7_n_scalar; 380 u8 dw4_cursor_coeff; 381 u8 dw4_post_cursor_2; 382 u8 dw4_post_cursor_1; 383 }; 384 385 /* Voltage Swing Programming for VccIO 0.85V for DP */ 386 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = { 387 /* NT mV Trans mV db */ 388 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 389 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ 390 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ 391 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ 392 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 393 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 394 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 395 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ 396 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ 397 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 398 }; 399 400 /* Voltage Swing Programming for VccIO 0.85V for HDMI */ 401 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = { 402 /* NT mV Trans mV db */ 403 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 404 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ 405 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ 406 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */ 407 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ 408 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ 409 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 410 }; 411 412 /* Voltage Swing Programming for VccIO 0.85V for eDP */ 413 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = { 414 /* NT mV Trans mV db */ 415 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 416 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 417 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 418 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 419 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 420 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 421 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */ 422 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */ 423 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 424 }; 425 426 /* Voltage Swing Programming for VccIO 0.95V for DP */ 427 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = { 428 /* NT mV Trans mV db */ 429 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 430 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ 431 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ 432 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ 433 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 434 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 435 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 436 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ 437 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ 438 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 439 }; 440 441 /* Voltage Swing Programming for VccIO 0.95V for HDMI */ 442 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = { 443 /* NT mV Trans mV db */ 444 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 445 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 446 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 447 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 448 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 449 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 450 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ 451 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ 452 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ 453 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ 454 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 455 }; 456 457 /* Voltage Swing Programming for VccIO 0.95V for eDP */ 458 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = { 459 /* NT mV Trans mV db */ 460 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 461 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 462 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 463 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 464 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 465 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 466 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ 467 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ 468 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */ 469 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 470 }; 471 472 /* Voltage Swing Programming for VccIO 1.05V for DP */ 473 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = { 474 /* NT mV Trans mV db */ 475 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 476 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 477 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 478 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */ 479 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 480 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 481 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */ 482 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */ 483 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */ 484 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 485 }; 486 487 /* Voltage Swing Programming for VccIO 1.05V for HDMI */ 488 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = { 489 /* NT mV Trans mV db */ 490 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 491 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 492 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 493 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 494 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 495 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 496 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ 497 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ 498 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ 499 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ 500 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 501 }; 502 503 /* Voltage Swing Programming for VccIO 1.05V for eDP */ 504 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = { 505 /* NT mV Trans mV db */ 506 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 507 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 508 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 509 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 510 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 511 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 512 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ 513 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ 514 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 515 }; 516 517 /* icl_combo_phy_ddi_translations */ 518 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = { 519 /* NT mV Trans mV db */ 520 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 521 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 522 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 523 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 524 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 525 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 526 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 527 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 528 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 529 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 530 }; 531 532 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = { 533 /* NT mV Trans mV db */ 534 { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ 535 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */ 536 { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */ 537 { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */ 538 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ 539 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */ 540 { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */ 541 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ 542 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ 543 { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 544 }; 545 546 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = { 547 /* NT mV Trans mV db */ 548 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 549 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 550 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 551 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 552 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 553 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 554 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 555 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 556 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 557 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 558 }; 559 560 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = { 561 /* NT mV Trans mV db */ 562 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 563 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ 564 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ 565 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */ 566 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ 567 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ 568 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 569 }; 570 571 static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = { 572 /* NT mV Trans mV db */ 573 { 0xA, 0x33, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 574 { 0xA, 0x47, 0x36, 0x00, 0x09 }, /* 350 500 3.1 */ 575 { 0xC, 0x64, 0x30, 0x00, 0x0F }, /* 350 700 6.0 */ 576 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 350 900 8.2 */ 577 { 0xA, 0x46, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 578 { 0xC, 0x64, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 579 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 580 { 0xC, 0x61, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */ 581 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 600 900 3.5 */ 582 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 583 }; 584 585 struct icl_mg_phy_ddi_buf_trans { 586 u32 cri_txdeemph_override_11_6; 587 u32 cri_txdeemph_override_5_0; 588 u32 cri_txdeemph_override_17_12; 589 }; 590 591 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_rbr_hbr[] = { 592 /* Voltage swing pre-emphasis */ 593 { 0x18, 0x00, 0x00 }, /* 0 0 */ 594 { 0x1D, 0x00, 0x05 }, /* 0 1 */ 595 { 0x24, 0x00, 0x0C }, /* 0 2 */ 596 { 0x2B, 0x00, 0x14 }, /* 0 3 */ 597 { 0x21, 0x00, 0x00 }, /* 1 0 */ 598 { 0x2B, 0x00, 0x08 }, /* 1 1 */ 599 { 0x30, 0x00, 0x0F }, /* 1 2 */ 600 { 0x31, 0x00, 0x03 }, /* 2 0 */ 601 { 0x34, 0x00, 0x0B }, /* 2 1 */ 602 { 0x3F, 0x00, 0x00 }, /* 3 0 */ 603 }; 604 605 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hbr2_hbr3[] = { 606 /* Voltage swing pre-emphasis */ 607 { 0x18, 0x00, 0x00 }, /* 0 0 */ 608 { 0x1D, 0x00, 0x05 }, /* 0 1 */ 609 { 0x24, 0x00, 0x0C }, /* 0 2 */ 610 { 0x2B, 0x00, 0x14 }, /* 0 3 */ 611 { 0x26, 0x00, 0x00 }, /* 1 0 */ 612 { 0x2C, 0x00, 0x07 }, /* 1 1 */ 613 { 0x33, 0x00, 0x0C }, /* 1 2 */ 614 { 0x2E, 0x00, 0x00 }, /* 2 0 */ 615 { 0x36, 0x00, 0x09 }, /* 2 1 */ 616 { 0x3F, 0x00, 0x00 }, /* 3 0 */ 617 }; 618 619 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hdmi[] = { 620 /* HDMI Preset VS Pre-emph */ 621 { 0x1A, 0x0, 0x0 }, /* 1 400mV 0dB */ 622 { 0x20, 0x0, 0x0 }, /* 2 500mV 0dB */ 623 { 0x29, 0x0, 0x0 }, /* 3 650mV 0dB */ 624 { 0x32, 0x0, 0x0 }, /* 4 800mV 0dB */ 625 { 0x3F, 0x0, 0x0 }, /* 5 1000mV 0dB */ 626 { 0x3A, 0x0, 0x5 }, /* 6 Full -1.5 dB */ 627 { 0x39, 0x0, 0x6 }, /* 7 Full -1.8 dB */ 628 { 0x38, 0x0, 0x7 }, /* 8 Full -2 dB */ 629 { 0x37, 0x0, 0x8 }, /* 9 Full -2.5 dB */ 630 { 0x36, 0x0, 0x9 }, /* 10 Full -3 dB */ 631 }; 632 633 struct tgl_dkl_phy_ddi_buf_trans { 634 u32 dkl_vswing_control; 635 u32 dkl_preshoot_control; 636 u32 dkl_de_emphasis_control; 637 }; 638 639 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans[] = { 640 /* VS pre-emp Non-trans mV Pre-emph dB */ 641 { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */ 642 { 0x5, 0x0, 0x03 }, /* 0 1 400mV 3.5 dB */ 643 { 0x2, 0x0, 0x0b }, /* 0 2 400mV 6 dB */ 644 { 0x0, 0x0, 0x19 }, /* 0 3 400mV 9.5 dB */ 645 { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */ 646 { 0x2, 0x0, 0x03 }, /* 1 1 600mV 3.5 dB */ 647 { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */ 648 { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */ 649 { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */ 650 { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */ 651 }; 652 653 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_hdmi_ddi_trans[] = { 654 /* HDMI Preset VS Pre-emph */ 655 { 0x7, 0x0, 0x0 }, /* 1 400mV 0dB */ 656 { 0x6, 0x0, 0x0 }, /* 2 500mV 0dB */ 657 { 0x4, 0x0, 0x0 }, /* 3 650mV 0dB */ 658 { 0x2, 0x0, 0x0 }, /* 4 800mV 0dB */ 659 { 0x0, 0x0, 0x0 }, /* 5 1000mV 0dB */ 660 { 0x0, 0x0, 0x5 }, /* 6 Full -1.5 dB */ 661 { 0x0, 0x0, 0x6 }, /* 7 Full -1.8 dB */ 662 { 0x0, 0x0, 0x7 }, /* 8 Full -2 dB */ 663 { 0x0, 0x0, 0x8 }, /* 9 Full -2.5 dB */ 664 { 0x0, 0x0, 0xA }, /* 10 Full -3 dB */ 665 }; 666 667 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr[] = { 668 /* NT mV Trans mV db */ 669 { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 670 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 671 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 672 { 0x6, 0x7D, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 673 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 674 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 675 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 676 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 677 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 678 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 679 }; 680 681 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = { 682 /* NT mV Trans mV db */ 683 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 684 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 685 { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 686 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 687 { 0xA, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 688 { 0xC, 0x63, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 689 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 690 { 0xC, 0x61, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 691 { 0x6, 0x7B, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 692 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 693 }; 694 695 static const struct ddi_buf_trans * 696 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 697 { 698 if (dev_priv->vbt.edp.low_vswing) { 699 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp); 700 return bdw_ddi_translations_edp; 701 } else { 702 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 703 return bdw_ddi_translations_dp; 704 } 705 } 706 707 static const struct ddi_buf_trans * 708 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 709 { 710 if (IS_SKL_ULX(dev_priv)) { 711 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); 712 return skl_y_ddi_translations_dp; 713 } else if (IS_SKL_ULT(dev_priv)) { 714 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); 715 return skl_u_ddi_translations_dp; 716 } else { 717 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); 718 return skl_ddi_translations_dp; 719 } 720 } 721 722 static const struct ddi_buf_trans * 723 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 724 { 725 if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv)) { 726 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp); 727 return kbl_y_ddi_translations_dp; 728 } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) { 729 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp); 730 return kbl_u_ddi_translations_dp; 731 } else { 732 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp); 733 return kbl_ddi_translations_dp; 734 } 735 } 736 737 static const struct ddi_buf_trans * 738 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 739 { 740 if (dev_priv->vbt.edp.low_vswing) { 741 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || 742 IS_CFL_ULX(dev_priv)) { 743 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); 744 return skl_y_ddi_translations_edp; 745 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) || 746 IS_CFL_ULT(dev_priv)) { 747 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); 748 return skl_u_ddi_translations_edp; 749 } else { 750 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp); 751 return skl_ddi_translations_edp; 752 } 753 } 754 755 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) 756 return kbl_get_buf_trans_dp(dev_priv, n_entries); 757 else 758 return skl_get_buf_trans_dp(dev_priv, n_entries); 759 } 760 761 static const struct ddi_buf_trans * 762 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) 763 { 764 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || 765 IS_CFL_ULX(dev_priv)) { 766 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); 767 return skl_y_ddi_translations_hdmi; 768 } else { 769 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); 770 return skl_ddi_translations_hdmi; 771 } 772 } 773 774 static int skl_buf_trans_num_entries(enum port port, int n_entries) 775 { 776 /* Only DDIA and DDIE can select the 10th register with DP */ 777 if (port == PORT_A || port == PORT_E) 778 return min(n_entries, 10); 779 else 780 return min(n_entries, 9); 781 } 782 783 static const struct ddi_buf_trans * 784 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv, 785 enum port port, int *n_entries) 786 { 787 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) { 788 const struct ddi_buf_trans *ddi_translations = 789 kbl_get_buf_trans_dp(dev_priv, n_entries); 790 *n_entries = skl_buf_trans_num_entries(port, *n_entries); 791 return ddi_translations; 792 } else if (IS_SKYLAKE(dev_priv)) { 793 const struct ddi_buf_trans *ddi_translations = 794 skl_get_buf_trans_dp(dev_priv, n_entries); 795 *n_entries = skl_buf_trans_num_entries(port, *n_entries); 796 return ddi_translations; 797 } else if (IS_BROADWELL(dev_priv)) { 798 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 799 return bdw_ddi_translations_dp; 800 } else if (IS_HASWELL(dev_priv)) { 801 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 802 return hsw_ddi_translations_dp; 803 } 804 805 *n_entries = 0; 806 return NULL; 807 } 808 809 static const struct ddi_buf_trans * 810 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv, 811 enum port port, int *n_entries) 812 { 813 if (IS_GEN9_BC(dev_priv)) { 814 const struct ddi_buf_trans *ddi_translations = 815 skl_get_buf_trans_edp(dev_priv, n_entries); 816 *n_entries = skl_buf_trans_num_entries(port, *n_entries); 817 return ddi_translations; 818 } else if (IS_BROADWELL(dev_priv)) { 819 return bdw_get_buf_trans_edp(dev_priv, n_entries); 820 } else if (IS_HASWELL(dev_priv)) { 821 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 822 return hsw_ddi_translations_dp; 823 } 824 825 *n_entries = 0; 826 return NULL; 827 } 828 829 static const struct ddi_buf_trans * 830 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, 831 int *n_entries) 832 { 833 if (IS_BROADWELL(dev_priv)) { 834 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi); 835 return bdw_ddi_translations_fdi; 836 } else if (IS_HASWELL(dev_priv)) { 837 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi); 838 return hsw_ddi_translations_fdi; 839 } 840 841 *n_entries = 0; 842 return NULL; 843 } 844 845 static const struct ddi_buf_trans * 846 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, 847 int *n_entries) 848 { 849 if (IS_GEN9_BC(dev_priv)) { 850 return skl_get_buf_trans_hdmi(dev_priv, n_entries); 851 } else if (IS_BROADWELL(dev_priv)) { 852 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 853 return bdw_ddi_translations_hdmi; 854 } else if (IS_HASWELL(dev_priv)) { 855 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); 856 return hsw_ddi_translations_hdmi; 857 } 858 859 *n_entries = 0; 860 return NULL; 861 } 862 863 static const struct bxt_ddi_buf_trans * 864 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 865 { 866 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); 867 return bxt_ddi_translations_dp; 868 } 869 870 static const struct bxt_ddi_buf_trans * 871 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 872 { 873 if (dev_priv->vbt.edp.low_vswing) { 874 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp); 875 return bxt_ddi_translations_edp; 876 } 877 878 return bxt_get_buf_trans_dp(dev_priv, n_entries); 879 } 880 881 static const struct bxt_ddi_buf_trans * 882 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) 883 { 884 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); 885 return bxt_ddi_translations_hdmi; 886 } 887 888 static const struct cnl_ddi_buf_trans * 889 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) 890 { 891 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 892 893 if (voltage == VOLTAGE_INFO_0_85V) { 894 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V); 895 return cnl_ddi_translations_hdmi_0_85V; 896 } else if (voltage == VOLTAGE_INFO_0_95V) { 897 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V); 898 return cnl_ddi_translations_hdmi_0_95V; 899 } else if (voltage == VOLTAGE_INFO_1_05V) { 900 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V); 901 return cnl_ddi_translations_hdmi_1_05V; 902 } else { 903 *n_entries = 1; /* shut up gcc */ 904 MISSING_CASE(voltage); 905 } 906 return NULL; 907 } 908 909 static const struct cnl_ddi_buf_trans * 910 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 911 { 912 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 913 914 if (voltage == VOLTAGE_INFO_0_85V) { 915 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V); 916 return cnl_ddi_translations_dp_0_85V; 917 } else if (voltage == VOLTAGE_INFO_0_95V) { 918 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V); 919 return cnl_ddi_translations_dp_0_95V; 920 } else if (voltage == VOLTAGE_INFO_1_05V) { 921 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V); 922 return cnl_ddi_translations_dp_1_05V; 923 } else { 924 *n_entries = 1; /* shut up gcc */ 925 MISSING_CASE(voltage); 926 } 927 return NULL; 928 } 929 930 static const struct cnl_ddi_buf_trans * 931 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 932 { 933 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 934 935 if (dev_priv->vbt.edp.low_vswing) { 936 if (voltage == VOLTAGE_INFO_0_85V) { 937 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V); 938 return cnl_ddi_translations_edp_0_85V; 939 } else if (voltage == VOLTAGE_INFO_0_95V) { 940 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V); 941 return cnl_ddi_translations_edp_0_95V; 942 } else if (voltage == VOLTAGE_INFO_1_05V) { 943 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V); 944 return cnl_ddi_translations_edp_1_05V; 945 } else { 946 *n_entries = 1; /* shut up gcc */ 947 MISSING_CASE(voltage); 948 } 949 return NULL; 950 } else { 951 return cnl_get_buf_trans_dp(dev_priv, n_entries); 952 } 953 } 954 955 static const struct cnl_ddi_buf_trans * 956 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, 957 int *n_entries) 958 { 959 if (type == INTEL_OUTPUT_HDMI) { 960 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); 961 return icl_combo_phy_ddi_translations_hdmi; 962 } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) { 963 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3); 964 return icl_combo_phy_ddi_translations_edp_hbr3; 965 } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) { 966 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2); 967 return icl_combo_phy_ddi_translations_edp_hbr2; 968 } 969 970 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2); 971 return icl_combo_phy_ddi_translations_dp_hbr2; 972 } 973 974 static const struct icl_mg_phy_ddi_buf_trans * 975 icl_get_mg_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, 976 int *n_entries) 977 { 978 if (type == INTEL_OUTPUT_HDMI) { 979 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hdmi); 980 return icl_mg_phy_ddi_translations_hdmi; 981 } else if (rate > 270000) { 982 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hbr2_hbr3); 983 return icl_mg_phy_ddi_translations_hbr2_hbr3; 984 } 985 986 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr); 987 return icl_mg_phy_ddi_translations_rbr_hbr; 988 } 989 990 static const struct cnl_ddi_buf_trans * 991 ehl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, 992 int *n_entries) 993 { 994 if (type != INTEL_OUTPUT_HDMI && type != INTEL_OUTPUT_EDP) { 995 *n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_dp); 996 return ehl_combo_phy_ddi_translations_dp; 997 } 998 999 return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries); 1000 } 1001 1002 static const struct cnl_ddi_buf_trans * 1003 tgl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, 1004 int *n_entries) 1005 { 1006 if (type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_EDP) { 1007 return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries); 1008 } else if (rate > 270000) { 1009 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2); 1010 return tgl_combo_phy_ddi_translations_dp_hbr2; 1011 } 1012 1013 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr); 1014 return tgl_combo_phy_ddi_translations_dp_hbr; 1015 } 1016 1017 static int intel_ddi_hdmi_level(struct intel_encoder *encoder) 1018 { 1019 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1020 int n_entries, level, default_entry; 1021 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1022 1023 if (INTEL_GEN(dev_priv) >= 12) { 1024 if (intel_phy_is_combo(dev_priv, phy)) 1025 tgl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 1026 0, &n_entries); 1027 else 1028 n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans); 1029 default_entry = n_entries - 1; 1030 } else if (INTEL_GEN(dev_priv) == 11) { 1031 if (intel_phy_is_combo(dev_priv, phy)) 1032 icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 1033 0, &n_entries); 1034 else 1035 icl_get_mg_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 0, 1036 &n_entries); 1037 default_entry = n_entries - 1; 1038 } else if (IS_CANNONLAKE(dev_priv)) { 1039 cnl_get_buf_trans_hdmi(dev_priv, &n_entries); 1040 default_entry = n_entries - 1; 1041 } else if (IS_GEN9_LP(dev_priv)) { 1042 bxt_get_buf_trans_hdmi(dev_priv, &n_entries); 1043 default_entry = n_entries - 1; 1044 } else if (IS_GEN9_BC(dev_priv)) { 1045 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 1046 default_entry = 8; 1047 } else if (IS_BROADWELL(dev_priv)) { 1048 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 1049 default_entry = 7; 1050 } else if (IS_HASWELL(dev_priv)) { 1051 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 1052 default_entry = 6; 1053 } else { 1054 drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n"); 1055 return 0; 1056 } 1057 1058 if (drm_WARN_ON_ONCE(&dev_priv->drm, n_entries == 0)) 1059 return 0; 1060 1061 level = intel_bios_hdmi_level_shift(encoder); 1062 if (level < 0) 1063 level = default_entry; 1064 1065 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 1066 level = n_entries - 1; 1067 1068 return level; 1069 } 1070 1071 /* 1072 * Starting with Haswell, DDI port buffers must be programmed with correct 1073 * values in advance. This function programs the correct values for 1074 * DP/eDP/FDI use cases. 1075 */ 1076 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 1077 const struct intel_crtc_state *crtc_state) 1078 { 1079 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1080 u32 iboost_bit = 0; 1081 int i, n_entries; 1082 enum port port = encoder->port; 1083 const struct ddi_buf_trans *ddi_translations; 1084 1085 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) 1086 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv, 1087 &n_entries); 1088 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1089 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, 1090 &n_entries); 1091 else 1092 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, 1093 &n_entries); 1094 1095 /* If we're boosting the current, set bit 31 of trans1 */ 1096 if (IS_GEN9_BC(dev_priv) && intel_bios_dp_boost_level(encoder)) 1097 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 1098 1099 for (i = 0; i < n_entries; i++) { 1100 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 1101 ddi_translations[i].trans1 | iboost_bit); 1102 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 1103 ddi_translations[i].trans2); 1104 } 1105 } 1106 1107 /* 1108 * Starting with Haswell, DDI port buffers must be programmed with correct 1109 * values in advance. This function programs the correct values for 1110 * HDMI/DVI use cases. 1111 */ 1112 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 1113 int level) 1114 { 1115 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1116 u32 iboost_bit = 0; 1117 int n_entries; 1118 enum port port = encoder->port; 1119 const struct ddi_buf_trans *ddi_translations; 1120 1121 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 1122 1123 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 1124 return; 1125 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 1126 level = n_entries - 1; 1127 1128 /* If we're boosting the current, set bit 31 of trans1 */ 1129 if (IS_GEN9_BC(dev_priv) && intel_bios_hdmi_boost_level(encoder)) 1130 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 1131 1132 /* Entry 9 is for HDMI: */ 1133 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 1134 ddi_translations[level].trans1 | iboost_bit); 1135 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 1136 ddi_translations[level].trans2); 1137 } 1138 1139 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 1140 enum port port) 1141 { 1142 i915_reg_t reg = DDI_BUF_CTL(port); 1143 int i; 1144 1145 for (i = 0; i < 16; i++) { 1146 udelay(1); 1147 if (intel_de_read(dev_priv, reg) & DDI_BUF_IS_IDLE) 1148 return; 1149 } 1150 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n", 1151 port_name(port)); 1152 } 1153 1154 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 1155 { 1156 switch (pll->info->id) { 1157 case DPLL_ID_WRPLL1: 1158 return PORT_CLK_SEL_WRPLL1; 1159 case DPLL_ID_WRPLL2: 1160 return PORT_CLK_SEL_WRPLL2; 1161 case DPLL_ID_SPLL: 1162 return PORT_CLK_SEL_SPLL; 1163 case DPLL_ID_LCPLL_810: 1164 return PORT_CLK_SEL_LCPLL_810; 1165 case DPLL_ID_LCPLL_1350: 1166 return PORT_CLK_SEL_LCPLL_1350; 1167 case DPLL_ID_LCPLL_2700: 1168 return PORT_CLK_SEL_LCPLL_2700; 1169 default: 1170 MISSING_CASE(pll->info->id); 1171 return PORT_CLK_SEL_NONE; 1172 } 1173 } 1174 1175 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 1176 const struct intel_crtc_state *crtc_state) 1177 { 1178 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1179 int clock = crtc_state->port_clock; 1180 const enum intel_dpll_id id = pll->info->id; 1181 1182 switch (id) { 1183 default: 1184 /* 1185 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 1186 * here, so do warn if this get passed in 1187 */ 1188 MISSING_CASE(id); 1189 return DDI_CLK_SEL_NONE; 1190 case DPLL_ID_ICL_TBTPLL: 1191 switch (clock) { 1192 case 162000: 1193 return DDI_CLK_SEL_TBT_162; 1194 case 270000: 1195 return DDI_CLK_SEL_TBT_270; 1196 case 540000: 1197 return DDI_CLK_SEL_TBT_540; 1198 case 810000: 1199 return DDI_CLK_SEL_TBT_810; 1200 default: 1201 MISSING_CASE(clock); 1202 return DDI_CLK_SEL_NONE; 1203 } 1204 case DPLL_ID_ICL_MGPLL1: 1205 case DPLL_ID_ICL_MGPLL2: 1206 case DPLL_ID_ICL_MGPLL3: 1207 case DPLL_ID_ICL_MGPLL4: 1208 case DPLL_ID_TGL_MGPLL5: 1209 case DPLL_ID_TGL_MGPLL6: 1210 return DDI_CLK_SEL_MG; 1211 } 1212 } 1213 1214 /* Starting with Haswell, different DDI ports can work in FDI mode for 1215 * connection to the PCH-located connectors. For this, it is necessary to train 1216 * both the DDI port and PCH receiver for the desired DDI buffer settings. 1217 * 1218 * The recommended port to work in FDI mode is DDI E, which we use here. Also, 1219 * please note that when FDI mode is active on DDI E, it shares 2 lines with 1220 * DDI A (which is used for eDP) 1221 */ 1222 1223 void hsw_fdi_link_train(struct intel_encoder *encoder, 1224 const struct intel_crtc_state *crtc_state) 1225 { 1226 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1227 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1228 u32 temp, i, rx_ctl_val, ddi_pll_sel; 1229 1230 intel_prepare_dp_ddi_buffers(encoder, crtc_state); 1231 1232 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the 1233 * mode set "sequence for CRT port" document: 1234 * - TP1 to TP2 time with the default value 1235 * - FDI delay to 90h 1236 * 1237 * WaFDIAutoLinkSetTimingOverrride:hsw 1238 */ 1239 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), 1240 FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 1241 1242 /* Enable the PCH Receiver FDI PLL */ 1243 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | 1244 FDI_RX_PLL_ENABLE | 1245 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); 1246 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 1247 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); 1248 udelay(220); 1249 1250 /* Switch from Rawclk to PCDclk */ 1251 rx_ctl_val |= FDI_PCDCLK; 1252 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 1253 1254 /* Configure Port Clock Select */ 1255 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll); 1256 intel_de_write(dev_priv, PORT_CLK_SEL(PORT_E), ddi_pll_sel); 1257 drm_WARN_ON(&dev_priv->drm, ddi_pll_sel != PORT_CLK_SEL_SPLL); 1258 1259 /* Start the training iterating through available voltages and emphasis, 1260 * testing each value twice. */ 1261 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { 1262 /* Configure DP_TP_CTL with auto-training */ 1263 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), 1264 DP_TP_CTL_FDI_AUTOTRAIN | 1265 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 1266 DP_TP_CTL_LINK_TRAIN_PAT1 | 1267 DP_TP_CTL_ENABLE); 1268 1269 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. 1270 * DDI E does not support port reversal, the functionality is 1271 * achieved on the PCH side in FDI_RX_CTL, so no need to set the 1272 * port reversal bit */ 1273 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), 1274 DDI_BUF_CTL_ENABLE | ((crtc_state->fdi_lanes - 1) << 1) | DDI_BUF_TRANS_SELECT(i / 2)); 1275 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E)); 1276 1277 udelay(600); 1278 1279 /* Program PCH FDI Receiver TU */ 1280 intel_de_write(dev_priv, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); 1281 1282 /* Enable PCH FDI Receiver with auto-training */ 1283 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; 1284 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 1285 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); 1286 1287 /* Wait for FDI receiver lane calibration */ 1288 udelay(30); 1289 1290 /* Unset FDI_RX_MISC pwrdn lanes */ 1291 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1292 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 1293 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp); 1294 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1295 1296 /* Wait for FDI auto training time */ 1297 udelay(5); 1298 1299 temp = intel_de_read(dev_priv, DP_TP_STATUS(PORT_E)); 1300 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { 1301 drm_dbg_kms(&dev_priv->drm, 1302 "FDI link training done on step %d\n", i); 1303 break; 1304 } 1305 1306 /* 1307 * Leave things enabled even if we failed to train FDI. 1308 * Results in less fireworks from the state checker. 1309 */ 1310 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) { 1311 drm_err(&dev_priv->drm, "FDI link training failed!\n"); 1312 break; 1313 } 1314 1315 rx_ctl_val &= ~FDI_RX_ENABLE; 1316 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 1317 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); 1318 1319 temp = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E)); 1320 temp &= ~DDI_BUF_CTL_ENABLE; 1321 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), temp); 1322 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E)); 1323 1324 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ 1325 temp = intel_de_read(dev_priv, DP_TP_CTL(PORT_E)); 1326 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 1327 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 1328 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp); 1329 intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E)); 1330 1331 intel_wait_ddi_buf_idle(dev_priv, PORT_E); 1332 1333 /* Reset FDI_RX_MISC pwrdn lanes */ 1334 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1335 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 1336 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 1337 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp); 1338 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1339 } 1340 1341 /* Enable normal pixel sending for FDI */ 1342 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), 1343 DP_TP_CTL_FDI_AUTOTRAIN | 1344 DP_TP_CTL_LINK_TRAIN_NORMAL | 1345 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 1346 DP_TP_CTL_ENABLE); 1347 } 1348 1349 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) 1350 { 1351 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1352 struct intel_digital_port *intel_dig_port = 1353 enc_to_dig_port(encoder); 1354 1355 intel_dp->DP = intel_dig_port->saved_port_bits | 1356 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); 1357 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); 1358 } 1359 1360 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 1361 enum port port) 1362 { 1363 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 1364 1365 switch (val) { 1366 case DDI_CLK_SEL_NONE: 1367 return 0; 1368 case DDI_CLK_SEL_TBT_162: 1369 return 162000; 1370 case DDI_CLK_SEL_TBT_270: 1371 return 270000; 1372 case DDI_CLK_SEL_TBT_540: 1373 return 540000; 1374 case DDI_CLK_SEL_TBT_810: 1375 return 810000; 1376 default: 1377 MISSING_CASE(val); 1378 return 0; 1379 } 1380 } 1381 1382 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 1383 { 1384 int dotclock; 1385 1386 if (pipe_config->has_pch_encoder) 1387 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1388 &pipe_config->fdi_m_n); 1389 else if (intel_crtc_has_dp_encoder(pipe_config)) 1390 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1391 &pipe_config->dp_m_n); 1392 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) 1393 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp; 1394 else 1395 dotclock = pipe_config->port_clock; 1396 1397 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 1398 !intel_crtc_has_dp_encoder(pipe_config)) 1399 dotclock *= 2; 1400 1401 if (pipe_config->pixel_multiplier) 1402 dotclock /= pipe_config->pixel_multiplier; 1403 1404 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 1405 } 1406 1407 static void intel_ddi_clock_get(struct intel_encoder *encoder, 1408 struct intel_crtc_state *pipe_config) 1409 { 1410 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1411 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1412 1413 if (intel_phy_is_tc(dev_priv, phy) && 1414 intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll) == 1415 DPLL_ID_ICL_TBTPLL) 1416 pipe_config->port_clock = icl_calc_tbt_pll_link(dev_priv, 1417 encoder->port); 1418 else 1419 pipe_config->port_clock = 1420 intel_dpll_get_freq(dev_priv, pipe_config->shared_dpll); 1421 1422 ddi_dotclock_get(pipe_config); 1423 } 1424 1425 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 1426 const struct drm_connector_state *conn_state) 1427 { 1428 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1429 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1430 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1431 u32 temp; 1432 1433 if (!intel_crtc_has_dp_encoder(crtc_state)) 1434 return; 1435 1436 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 1437 1438 temp = DP_MSA_MISC_SYNC_CLOCK; 1439 1440 switch (crtc_state->pipe_bpp) { 1441 case 18: 1442 temp |= DP_MSA_MISC_6_BPC; 1443 break; 1444 case 24: 1445 temp |= DP_MSA_MISC_8_BPC; 1446 break; 1447 case 30: 1448 temp |= DP_MSA_MISC_10_BPC; 1449 break; 1450 case 36: 1451 temp |= DP_MSA_MISC_12_BPC; 1452 break; 1453 default: 1454 MISSING_CASE(crtc_state->pipe_bpp); 1455 break; 1456 } 1457 1458 /* nonsense combination */ 1459 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 1460 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 1461 1462 if (crtc_state->limited_color_range) 1463 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 1464 1465 /* 1466 * As per DP 1.2 spec section 2.3.4.3 while sending 1467 * YCBCR 444 signals we should program MSA MISC1/0 fields with 1468 * colorspace information. 1469 */ 1470 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 1471 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 1472 1473 /* 1474 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 1475 * of Color Encoding Format and Content Color Gamut] while sending 1476 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 1477 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 1478 */ 1479 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 1480 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 1481 1482 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp); 1483 } 1484 1485 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 1486 { 1487 if (master_transcoder == TRANSCODER_EDP) 1488 return 0; 1489 else 1490 return master_transcoder + 1; 1491 } 1492 1493 /* 1494 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 1495 * 1496 * Only intended to be used by intel_ddi_enable_transcoder_func() and 1497 * intel_ddi_config_transcoder_func(). 1498 */ 1499 static u32 1500 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 1501 const struct intel_crtc_state *crtc_state) 1502 { 1503 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1504 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1505 enum pipe pipe = crtc->pipe; 1506 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1507 enum port port = encoder->port; 1508 u32 temp; 1509 1510 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 1511 temp = TRANS_DDI_FUNC_ENABLE; 1512 if (INTEL_GEN(dev_priv) >= 12) 1513 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 1514 else 1515 temp |= TRANS_DDI_SELECT_PORT(port); 1516 1517 switch (crtc_state->pipe_bpp) { 1518 case 18: 1519 temp |= TRANS_DDI_BPC_6; 1520 break; 1521 case 24: 1522 temp |= TRANS_DDI_BPC_8; 1523 break; 1524 case 30: 1525 temp |= TRANS_DDI_BPC_10; 1526 break; 1527 case 36: 1528 temp |= TRANS_DDI_BPC_12; 1529 break; 1530 default: 1531 BUG(); 1532 } 1533 1534 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 1535 temp |= TRANS_DDI_PVSYNC; 1536 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 1537 temp |= TRANS_DDI_PHSYNC; 1538 1539 if (cpu_transcoder == TRANSCODER_EDP) { 1540 switch (pipe) { 1541 case PIPE_A: 1542 /* On Haswell, can only use the always-on power well for 1543 * eDP when not using the panel fitter, and when not 1544 * using motion blur mitigation (which we don't 1545 * support). */ 1546 if (crtc_state->pch_pfit.force_thru) 1547 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 1548 else 1549 temp |= TRANS_DDI_EDP_INPUT_A_ON; 1550 break; 1551 case PIPE_B: 1552 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 1553 break; 1554 case PIPE_C: 1555 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 1556 break; 1557 default: 1558 BUG(); 1559 break; 1560 } 1561 } 1562 1563 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1564 if (crtc_state->has_hdmi_sink) 1565 temp |= TRANS_DDI_MODE_SELECT_HDMI; 1566 else 1567 temp |= TRANS_DDI_MODE_SELECT_DVI; 1568 1569 if (crtc_state->hdmi_scrambling) 1570 temp |= TRANS_DDI_HDMI_SCRAMBLING; 1571 if (crtc_state->hdmi_high_tmds_clock_ratio) 1572 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 1573 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 1574 temp |= TRANS_DDI_MODE_SELECT_FDI; 1575 temp |= (crtc_state->fdi_lanes - 1) << 1; 1576 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 1577 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 1578 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 1579 1580 if (INTEL_GEN(dev_priv) >= 12) { 1581 enum transcoder master; 1582 1583 master = crtc_state->mst_master_transcoder; 1584 drm_WARN_ON(&dev_priv->drm, 1585 master == INVALID_TRANSCODER); 1586 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 1587 } 1588 } else { 1589 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 1590 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 1591 } 1592 1593 if (IS_GEN_RANGE(dev_priv, 8, 10) && 1594 crtc_state->master_transcoder != INVALID_TRANSCODER) { 1595 u8 master_select = 1596 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 1597 1598 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 1599 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 1600 } 1601 1602 return temp; 1603 } 1604 1605 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 1606 const struct intel_crtc_state *crtc_state) 1607 { 1608 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1609 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1610 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1611 u32 ctl; 1612 1613 if (INTEL_GEN(dev_priv) >= 11) { 1614 enum transcoder master_transcoder = crtc_state->master_transcoder; 1615 u32 ctl2 = 0; 1616 1617 if (master_transcoder != INVALID_TRANSCODER) { 1618 u8 master_select = 1619 bdw_trans_port_sync_master_select(master_transcoder); 1620 1621 ctl2 |= PORT_SYNC_MODE_ENABLE | 1622 PORT_SYNC_MODE_MASTER_SELECT(master_select); 1623 } 1624 1625 intel_de_write(dev_priv, 1626 TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2); 1627 } 1628 1629 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 1630 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 1631 ctl |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; 1632 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 1633 } 1634 1635 /* 1636 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 1637 * bit. 1638 */ 1639 static void 1640 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 1641 const struct intel_crtc_state *crtc_state) 1642 { 1643 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1644 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1645 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1646 u32 ctl; 1647 1648 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 1649 ctl &= ~TRANS_DDI_FUNC_ENABLE; 1650 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 1651 } 1652 1653 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 1654 { 1655 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1656 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1657 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1658 u32 ctl; 1659 1660 if (INTEL_GEN(dev_priv) >= 11) 1661 intel_de_write(dev_priv, 1662 TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0); 1663 1664 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1665 1666 ctl &= ~TRANS_DDI_FUNC_ENABLE; 1667 1668 if (IS_GEN_RANGE(dev_priv, 8, 10)) 1669 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 1670 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 1671 1672 if (INTEL_GEN(dev_priv) >= 12) { 1673 if (!intel_dp_mst_is_master_trans(crtc_state)) { 1674 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 1675 TRANS_DDI_MODE_SELECT_MASK); 1676 } 1677 } else { 1678 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 1679 } 1680 1681 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 1682 1683 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME && 1684 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1685 drm_dbg_kms(&dev_priv->drm, 1686 "Quirk Increase DDI disabled time\n"); 1687 /* Quirk time at 100ms for reliable operation */ 1688 msleep(100); 1689 } 1690 } 1691 1692 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder, 1693 bool enable) 1694 { 1695 struct drm_device *dev = intel_encoder->base.dev; 1696 struct drm_i915_private *dev_priv = to_i915(dev); 1697 intel_wakeref_t wakeref; 1698 enum pipe pipe = 0; 1699 int ret = 0; 1700 u32 tmp; 1701 1702 wakeref = intel_display_power_get_if_enabled(dev_priv, 1703 intel_encoder->power_domain); 1704 if (drm_WARN_ON(dev, !wakeref)) 1705 return -ENXIO; 1706 1707 if (drm_WARN_ON(dev, 1708 !intel_encoder->get_hw_state(intel_encoder, &pipe))) { 1709 ret = -EIO; 1710 goto out; 1711 } 1712 1713 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe)); 1714 if (enable) 1715 tmp |= TRANS_DDI_HDCP_SIGNALLING; 1716 else 1717 tmp &= ~TRANS_DDI_HDCP_SIGNALLING; 1718 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), tmp); 1719 out: 1720 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 1721 return ret; 1722 } 1723 1724 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 1725 { 1726 struct drm_device *dev = intel_connector->base.dev; 1727 struct drm_i915_private *dev_priv = to_i915(dev); 1728 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 1729 int type = intel_connector->base.connector_type; 1730 enum port port = encoder->port; 1731 enum transcoder cpu_transcoder; 1732 intel_wakeref_t wakeref; 1733 enum pipe pipe = 0; 1734 u32 tmp; 1735 bool ret; 1736 1737 wakeref = intel_display_power_get_if_enabled(dev_priv, 1738 encoder->power_domain); 1739 if (!wakeref) 1740 return false; 1741 1742 if (!encoder->get_hw_state(encoder, &pipe)) { 1743 ret = false; 1744 goto out; 1745 } 1746 1747 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 1748 cpu_transcoder = TRANSCODER_EDP; 1749 else 1750 cpu_transcoder = (enum transcoder) pipe; 1751 1752 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1753 1754 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 1755 case TRANS_DDI_MODE_SELECT_HDMI: 1756 case TRANS_DDI_MODE_SELECT_DVI: 1757 ret = type == DRM_MODE_CONNECTOR_HDMIA; 1758 break; 1759 1760 case TRANS_DDI_MODE_SELECT_DP_SST: 1761 ret = type == DRM_MODE_CONNECTOR_eDP || 1762 type == DRM_MODE_CONNECTOR_DisplayPort; 1763 break; 1764 1765 case TRANS_DDI_MODE_SELECT_DP_MST: 1766 /* if the transcoder is in MST state then 1767 * connector isn't connected */ 1768 ret = false; 1769 break; 1770 1771 case TRANS_DDI_MODE_SELECT_FDI: 1772 ret = type == DRM_MODE_CONNECTOR_VGA; 1773 break; 1774 1775 default: 1776 ret = false; 1777 break; 1778 } 1779 1780 out: 1781 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1782 1783 return ret; 1784 } 1785 1786 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 1787 u8 *pipe_mask, bool *is_dp_mst) 1788 { 1789 struct drm_device *dev = encoder->base.dev; 1790 struct drm_i915_private *dev_priv = to_i915(dev); 1791 enum port port = encoder->port; 1792 intel_wakeref_t wakeref; 1793 enum pipe p; 1794 u32 tmp; 1795 u8 mst_pipe_mask; 1796 1797 *pipe_mask = 0; 1798 *is_dp_mst = false; 1799 1800 wakeref = intel_display_power_get_if_enabled(dev_priv, 1801 encoder->power_domain); 1802 if (!wakeref) 1803 return; 1804 1805 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 1806 if (!(tmp & DDI_BUF_CTL_ENABLE)) 1807 goto out; 1808 1809 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { 1810 tmp = intel_de_read(dev_priv, 1811 TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 1812 1813 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 1814 default: 1815 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 1816 /* fallthrough */ 1817 case TRANS_DDI_EDP_INPUT_A_ON: 1818 case TRANS_DDI_EDP_INPUT_A_ONOFF: 1819 *pipe_mask = BIT(PIPE_A); 1820 break; 1821 case TRANS_DDI_EDP_INPUT_B_ONOFF: 1822 *pipe_mask = BIT(PIPE_B); 1823 break; 1824 case TRANS_DDI_EDP_INPUT_C_ONOFF: 1825 *pipe_mask = BIT(PIPE_C); 1826 break; 1827 } 1828 1829 goto out; 1830 } 1831 1832 mst_pipe_mask = 0; 1833 for_each_pipe(dev_priv, p) { 1834 enum transcoder cpu_transcoder = (enum transcoder)p; 1835 unsigned int port_mask, ddi_select; 1836 intel_wakeref_t trans_wakeref; 1837 1838 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 1839 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 1840 if (!trans_wakeref) 1841 continue; 1842 1843 if (INTEL_GEN(dev_priv) >= 12) { 1844 port_mask = TGL_TRANS_DDI_PORT_MASK; 1845 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 1846 } else { 1847 port_mask = TRANS_DDI_PORT_MASK; 1848 ddi_select = TRANS_DDI_SELECT_PORT(port); 1849 } 1850 1851 tmp = intel_de_read(dev_priv, 1852 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1853 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 1854 trans_wakeref); 1855 1856 if ((tmp & port_mask) != ddi_select) 1857 continue; 1858 1859 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == 1860 TRANS_DDI_MODE_SELECT_DP_MST) 1861 mst_pipe_mask |= BIT(p); 1862 1863 *pipe_mask |= BIT(p); 1864 } 1865 1866 if (!*pipe_mask) 1867 drm_dbg_kms(&dev_priv->drm, 1868 "No pipe for [ENCODER:%d:%s] found\n", 1869 encoder->base.base.id, encoder->base.name); 1870 1871 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 1872 drm_dbg_kms(&dev_priv->drm, 1873 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 1874 encoder->base.base.id, encoder->base.name, 1875 *pipe_mask); 1876 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 1877 } 1878 1879 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 1880 drm_dbg_kms(&dev_priv->drm, 1881 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", 1882 encoder->base.base.id, encoder->base.name, 1883 *pipe_mask, mst_pipe_mask); 1884 else 1885 *is_dp_mst = mst_pipe_mask; 1886 1887 out: 1888 if (*pipe_mask && IS_GEN9_LP(dev_priv)) { 1889 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 1890 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 1891 BXT_PHY_LANE_POWERDOWN_ACK | 1892 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 1893 drm_err(&dev_priv->drm, 1894 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 1895 encoder->base.base.id, encoder->base.name, tmp); 1896 } 1897 1898 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1899 } 1900 1901 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 1902 enum pipe *pipe) 1903 { 1904 u8 pipe_mask; 1905 bool is_mst; 1906 1907 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 1908 1909 if (is_mst || !pipe_mask) 1910 return false; 1911 1912 *pipe = ffs(pipe_mask) - 1; 1913 1914 return true; 1915 } 1916 1917 static enum intel_display_power_domain 1918 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port) 1919 { 1920 /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with 1921 * DC states enabled at the same time, while for driver initiated AUX 1922 * transfers we need the same AUX IOs to be powered but with DC states 1923 * disabled. Accordingly use the AUX power domain here which leaves DC 1924 * states enabled. 1925 * However, for non-A AUX ports the corresponding non-EDP transcoders 1926 * would have already enabled power well 2 and DC_OFF. This means we can 1927 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a 1928 * specific AUX_IO reference without powering up any extra wells. 1929 * Note that PSR is enabled only on Port A even though this function 1930 * returns the correct domain for other ports too. 1931 */ 1932 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A : 1933 intel_aux_power_domain(dig_port); 1934 } 1935 1936 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 1937 struct intel_crtc_state *crtc_state) 1938 { 1939 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1940 struct intel_digital_port *dig_port; 1941 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1942 1943 /* 1944 * TODO: Add support for MST encoders. Atm, the following should never 1945 * happen since fake-MST encoders don't set their get_power_domains() 1946 * hook. 1947 */ 1948 if (drm_WARN_ON(&dev_priv->drm, 1949 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 1950 return; 1951 1952 dig_port = enc_to_dig_port(encoder); 1953 1954 if (!intel_phy_is_tc(dev_priv, phy) || 1955 dig_port->tc_mode != TC_PORT_TBT_ALT) 1956 intel_display_power_get(dev_priv, 1957 dig_port->ddi_io_power_domain); 1958 1959 /* 1960 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC 1961 * ports. 1962 */ 1963 if (intel_crtc_has_dp_encoder(crtc_state) || 1964 intel_phy_is_tc(dev_priv, phy)) 1965 intel_display_power_get(dev_priv, 1966 intel_ddi_main_link_aux_domain(dig_port)); 1967 1968 /* 1969 * VDSC power is needed when DSC is enabled 1970 */ 1971 if (crtc_state->dsc.compression_enable) 1972 intel_display_power_get(dev_priv, 1973 intel_dsc_power_domain(crtc_state)); 1974 } 1975 1976 void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder, 1977 const struct intel_crtc_state *crtc_state) 1978 { 1979 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1980 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1981 enum port port = encoder->port; 1982 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1983 1984 if (cpu_transcoder != TRANSCODER_EDP) { 1985 if (INTEL_GEN(dev_priv) >= 12) 1986 intel_de_write(dev_priv, 1987 TRANS_CLK_SEL(cpu_transcoder), 1988 TGL_TRANS_CLK_SEL_PORT(port)); 1989 else 1990 intel_de_write(dev_priv, 1991 TRANS_CLK_SEL(cpu_transcoder), 1992 TRANS_CLK_SEL_PORT(port)); 1993 } 1994 } 1995 1996 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state) 1997 { 1998 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1999 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2000 2001 if (cpu_transcoder != TRANSCODER_EDP) { 2002 if (INTEL_GEN(dev_priv) >= 12) 2003 intel_de_write(dev_priv, 2004 TRANS_CLK_SEL(cpu_transcoder), 2005 TGL_TRANS_CLK_SEL_DISABLED); 2006 else 2007 intel_de_write(dev_priv, 2008 TRANS_CLK_SEL(cpu_transcoder), 2009 TRANS_CLK_SEL_DISABLED); 2010 } 2011 } 2012 2013 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 2014 enum port port, u8 iboost) 2015 { 2016 u32 tmp; 2017 2018 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 2019 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 2020 if (iboost) 2021 tmp |= iboost << BALANCE_LEG_SHIFT(port); 2022 else 2023 tmp |= BALANCE_LEG_DISABLE(port); 2024 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 2025 } 2026 2027 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 2028 int level, enum intel_output_type type) 2029 { 2030 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 2031 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2032 enum port port = encoder->port; 2033 u8 iboost; 2034 2035 if (type == INTEL_OUTPUT_HDMI) 2036 iboost = intel_bios_hdmi_boost_level(encoder); 2037 else 2038 iboost = intel_bios_dp_boost_level(encoder); 2039 2040 if (iboost == 0) { 2041 const struct ddi_buf_trans *ddi_translations; 2042 int n_entries; 2043 2044 if (type == INTEL_OUTPUT_HDMI) 2045 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 2046 else if (type == INTEL_OUTPUT_EDP) 2047 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries); 2048 else 2049 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries); 2050 2051 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 2052 return; 2053 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 2054 level = n_entries - 1; 2055 2056 iboost = ddi_translations[level].i_boost; 2057 } 2058 2059 /* Make sure that the requested I_boost is valid */ 2060 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 2061 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); 2062 return; 2063 } 2064 2065 _skl_ddi_set_iboost(dev_priv, port, iboost); 2066 2067 if (port == PORT_A && intel_dig_port->max_lanes == 4) 2068 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 2069 } 2070 2071 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, 2072 int level, enum intel_output_type type) 2073 { 2074 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2075 const struct bxt_ddi_buf_trans *ddi_translations; 2076 enum port port = encoder->port; 2077 int n_entries; 2078 2079 if (type == INTEL_OUTPUT_HDMI) 2080 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries); 2081 else if (type == INTEL_OUTPUT_EDP) 2082 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries); 2083 else 2084 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries); 2085 2086 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 2087 return; 2088 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 2089 level = n_entries - 1; 2090 2091 bxt_ddi_phy_set_signal_level(dev_priv, port, 2092 ddi_translations[level].margin, 2093 ddi_translations[level].scale, 2094 ddi_translations[level].enable, 2095 ddi_translations[level].deemphasis); 2096 } 2097 2098 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder) 2099 { 2100 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2101 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2102 enum port port = encoder->port; 2103 enum phy phy = intel_port_to_phy(dev_priv, port); 2104 int n_entries; 2105 2106 if (INTEL_GEN(dev_priv) >= 12) { 2107 if (intel_phy_is_combo(dev_priv, phy)) 2108 tgl_get_combo_buf_trans(dev_priv, encoder->type, 2109 intel_dp->link_rate, &n_entries); 2110 else 2111 n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans); 2112 } else if (INTEL_GEN(dev_priv) == 11) { 2113 if (IS_ELKHARTLAKE(dev_priv)) 2114 ehl_get_combo_buf_trans(dev_priv, encoder->type, 2115 intel_dp->link_rate, &n_entries); 2116 else if (intel_phy_is_combo(dev_priv, phy)) 2117 icl_get_combo_buf_trans(dev_priv, encoder->type, 2118 intel_dp->link_rate, &n_entries); 2119 else 2120 icl_get_mg_buf_trans(dev_priv, encoder->type, 2121 intel_dp->link_rate, &n_entries); 2122 } else if (IS_CANNONLAKE(dev_priv)) { 2123 if (encoder->type == INTEL_OUTPUT_EDP) 2124 cnl_get_buf_trans_edp(dev_priv, &n_entries); 2125 else 2126 cnl_get_buf_trans_dp(dev_priv, &n_entries); 2127 } else if (IS_GEN9_LP(dev_priv)) { 2128 if (encoder->type == INTEL_OUTPUT_EDP) 2129 bxt_get_buf_trans_edp(dev_priv, &n_entries); 2130 else 2131 bxt_get_buf_trans_dp(dev_priv, &n_entries); 2132 } else { 2133 if (encoder->type == INTEL_OUTPUT_EDP) 2134 intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries); 2135 else 2136 intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries); 2137 } 2138 2139 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 2140 n_entries = 1; 2141 if (drm_WARN_ON(&dev_priv->drm, 2142 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 2143 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 2144 2145 return index_to_dp_signal_levels[n_entries - 1] & 2146 DP_TRAIN_VOLTAGE_SWING_MASK; 2147 } 2148 2149 /* 2150 * We assume that the full set of pre-emphasis values can be 2151 * used on all DDI platforms. Should that change we need to 2152 * rethink this code. 2153 */ 2154 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing) 2155 { 2156 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2157 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2158 return DP_TRAIN_PRE_EMPH_LEVEL_3; 2159 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 2160 return DP_TRAIN_PRE_EMPH_LEVEL_2; 2161 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 2162 return DP_TRAIN_PRE_EMPH_LEVEL_1; 2163 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 2164 default: 2165 return DP_TRAIN_PRE_EMPH_LEVEL_0; 2166 } 2167 } 2168 2169 static void cnl_ddi_vswing_program(struct intel_encoder *encoder, 2170 int level, enum intel_output_type type) 2171 { 2172 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2173 const struct cnl_ddi_buf_trans *ddi_translations; 2174 enum port port = encoder->port; 2175 int n_entries, ln; 2176 u32 val; 2177 2178 if (type == INTEL_OUTPUT_HDMI) 2179 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries); 2180 else if (type == INTEL_OUTPUT_EDP) 2181 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries); 2182 else 2183 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries); 2184 2185 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 2186 return; 2187 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 2188 level = n_entries - 1; 2189 2190 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */ 2191 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 2192 val &= ~SCALING_MODE_SEL_MASK; 2193 val |= SCALING_MODE_SEL(2); 2194 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 2195 2196 /* Program PORT_TX_DW2 */ 2197 val = intel_de_read(dev_priv, CNL_PORT_TX_DW2_LN0(port)); 2198 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 2199 RCOMP_SCALAR_MASK); 2200 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); 2201 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); 2202 /* Rcomp scalar is fixed as 0x98 for every table entry */ 2203 val |= RCOMP_SCALAR(0x98); 2204 intel_de_write(dev_priv, CNL_PORT_TX_DW2_GRP(port), val); 2205 2206 /* Program PORT_TX_DW4 */ 2207 /* We cannot write to GRP. It would overrite individual loadgen */ 2208 for (ln = 0; ln < 4; ln++) { 2209 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port)); 2210 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 2211 CURSOR_COEFF_MASK); 2212 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); 2213 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); 2214 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); 2215 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val); 2216 } 2217 2218 /* Program PORT_TX_DW5 */ 2219 /* All DW5 values are fixed for every table entry */ 2220 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 2221 val &= ~RTERM_SELECT_MASK; 2222 val |= RTERM_SELECT(6); 2223 val |= TAP3_DISABLE; 2224 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 2225 2226 /* Program PORT_TX_DW7 */ 2227 val = intel_de_read(dev_priv, CNL_PORT_TX_DW7_LN0(port)); 2228 val &= ~N_SCALAR_MASK; 2229 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); 2230 intel_de_write(dev_priv, CNL_PORT_TX_DW7_GRP(port), val); 2231 } 2232 2233 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, 2234 int level, enum intel_output_type type) 2235 { 2236 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2237 enum port port = encoder->port; 2238 int width, rate, ln; 2239 u32 val; 2240 2241 if (type == INTEL_OUTPUT_HDMI) { 2242 width = 4; 2243 rate = 0; /* Rate is always < than 6GHz for HDMI */ 2244 } else { 2245 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2246 2247 width = intel_dp->lane_count; 2248 rate = intel_dp->link_rate; 2249 } 2250 2251 /* 2252 * 1. If port type is eDP or DP, 2253 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 2254 * else clear to 0b. 2255 */ 2256 val = intel_de_read(dev_priv, CNL_PORT_PCS_DW1_LN0(port)); 2257 if (type != INTEL_OUTPUT_HDMI) 2258 val |= COMMON_KEEPER_EN; 2259 else 2260 val &= ~COMMON_KEEPER_EN; 2261 intel_de_write(dev_priv, CNL_PORT_PCS_DW1_GRP(port), val); 2262 2263 /* 2. Program loadgen select */ 2264 /* 2265 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes 2266 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2267 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2268 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 2269 */ 2270 for (ln = 0; ln <= 3; ln++) { 2271 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port)); 2272 val &= ~LOADGEN_SELECT; 2273 2274 if ((rate <= 600000 && width == 4 && ln >= 1) || 2275 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { 2276 val |= LOADGEN_SELECT; 2277 } 2278 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val); 2279 } 2280 2281 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 2282 val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5); 2283 val |= SUS_CLOCK_CONFIG; 2284 intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val); 2285 2286 /* 4. Clear training enable to change swing values */ 2287 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 2288 val &= ~TX_TRAINING_EN; 2289 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 2290 2291 /* 5. Program swing and de-emphasis */ 2292 cnl_ddi_vswing_program(encoder, level, type); 2293 2294 /* 6. Set training enable to trigger update */ 2295 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 2296 val |= TX_TRAINING_EN; 2297 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 2298 } 2299 2300 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, 2301 u32 level, enum phy phy, int type, 2302 int rate) 2303 { 2304 const struct cnl_ddi_buf_trans *ddi_translations = NULL; 2305 u32 n_entries, val; 2306 int ln; 2307 2308 if (INTEL_GEN(dev_priv) >= 12) 2309 ddi_translations = tgl_get_combo_buf_trans(dev_priv, type, rate, 2310 &n_entries); 2311 else if (IS_ELKHARTLAKE(dev_priv)) 2312 ddi_translations = ehl_get_combo_buf_trans(dev_priv, type, rate, 2313 &n_entries); 2314 else 2315 ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate, 2316 &n_entries); 2317 if (!ddi_translations) 2318 return; 2319 2320 if (level >= n_entries) { 2321 drm_dbg_kms(&dev_priv->drm, 2322 "DDI translation not found for level %d. Using %d instead.", 2323 level, n_entries - 1); 2324 level = n_entries - 1; 2325 } 2326 2327 /* Set PORT_TX_DW5 */ 2328 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 2329 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 2330 TAP2_DISABLE | TAP3_DISABLE); 2331 val |= SCALING_MODE_SEL(0x2); 2332 val |= RTERM_SELECT(0x6); 2333 val |= TAP3_DISABLE; 2334 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 2335 2336 /* Program PORT_TX_DW2 */ 2337 val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy)); 2338 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 2339 RCOMP_SCALAR_MASK); 2340 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); 2341 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); 2342 /* Program Rcomp scalar for every table entry */ 2343 val |= RCOMP_SCALAR(0x98); 2344 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val); 2345 2346 /* Program PORT_TX_DW4 */ 2347 /* We cannot write to GRP. It would overwrite individual loadgen. */ 2348 for (ln = 0; ln <= 3; ln++) { 2349 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy)); 2350 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 2351 CURSOR_COEFF_MASK); 2352 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); 2353 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); 2354 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); 2355 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val); 2356 } 2357 2358 /* Program PORT_TX_DW7 */ 2359 val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy)); 2360 val &= ~N_SCALAR_MASK; 2361 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); 2362 intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val); 2363 } 2364 2365 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 2366 u32 level, 2367 enum intel_output_type type) 2368 { 2369 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2370 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2371 int width = 0; 2372 int rate = 0; 2373 u32 val; 2374 int ln = 0; 2375 2376 if (type == INTEL_OUTPUT_HDMI) { 2377 width = 4; 2378 /* Rate is always < than 6GHz for HDMI */ 2379 } else { 2380 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2381 2382 width = intel_dp->lane_count; 2383 rate = intel_dp->link_rate; 2384 } 2385 2386 /* 2387 * 1. If port type is eDP or DP, 2388 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 2389 * else clear to 0b. 2390 */ 2391 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy)); 2392 if (type == INTEL_OUTPUT_HDMI) 2393 val &= ~COMMON_KEEPER_EN; 2394 else 2395 val |= COMMON_KEEPER_EN; 2396 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 2397 2398 /* 2. Program loadgen select */ 2399 /* 2400 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes 2401 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2402 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2403 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 2404 */ 2405 for (ln = 0; ln <= 3; ln++) { 2406 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy)); 2407 val &= ~LOADGEN_SELECT; 2408 2409 if ((rate <= 600000 && width == 4 && ln >= 1) || 2410 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { 2411 val |= LOADGEN_SELECT; 2412 } 2413 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val); 2414 } 2415 2416 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 2417 val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); 2418 val |= SUS_CLOCK_CONFIG; 2419 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val); 2420 2421 /* 4. Clear training enable to change swing values */ 2422 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 2423 val &= ~TX_TRAINING_EN; 2424 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 2425 2426 /* 5. Program swing and de-emphasis */ 2427 icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate); 2428 2429 /* 6. Set training enable to trigger update */ 2430 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 2431 val |= TX_TRAINING_EN; 2432 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 2433 } 2434 2435 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 2436 int link_clock, u32 level, 2437 enum intel_output_type type) 2438 { 2439 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2440 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 2441 const struct icl_mg_phy_ddi_buf_trans *ddi_translations; 2442 u32 n_entries, val; 2443 int ln, rate = 0; 2444 2445 if (type != INTEL_OUTPUT_HDMI) { 2446 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2447 2448 rate = intel_dp->link_rate; 2449 } 2450 2451 ddi_translations = icl_get_mg_buf_trans(dev_priv, type, rate, 2452 &n_entries); 2453 /* The table does not have values for level 3 and level 9. */ 2454 if (level >= n_entries || level == 3 || level == 9) { 2455 drm_dbg_kms(&dev_priv->drm, 2456 "DDI translation not found for level %d. Using %d instead.", 2457 level, n_entries - 2); 2458 level = n_entries - 2; 2459 } 2460 2461 /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */ 2462 for (ln = 0; ln < 2; ln++) { 2463 val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port)); 2464 val &= ~CRI_USE_FS32; 2465 intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), val); 2466 2467 val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port)); 2468 val &= ~CRI_USE_FS32; 2469 intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), val); 2470 } 2471 2472 /* Program MG_TX_SWINGCTRL with values from vswing table */ 2473 for (ln = 0; ln < 2; ln++) { 2474 val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port)); 2475 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; 2476 val |= CRI_TXDEEMPH_OVERRIDE_17_12( 2477 ddi_translations[level].cri_txdeemph_override_17_12); 2478 intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val); 2479 2480 val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port)); 2481 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; 2482 val |= CRI_TXDEEMPH_OVERRIDE_17_12( 2483 ddi_translations[level].cri_txdeemph_override_17_12); 2484 intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val); 2485 } 2486 2487 /* Program MG_TX_DRVCTRL with values from vswing table */ 2488 for (ln = 0; ln < 2; ln++) { 2489 val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port)); 2490 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 2491 CRI_TXDEEMPH_OVERRIDE_5_0_MASK); 2492 val |= CRI_TXDEEMPH_OVERRIDE_5_0( 2493 ddi_translations[level].cri_txdeemph_override_5_0) | 2494 CRI_TXDEEMPH_OVERRIDE_11_6( 2495 ddi_translations[level].cri_txdeemph_override_11_6) | 2496 CRI_TXDEEMPH_OVERRIDE_EN; 2497 intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val); 2498 2499 val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port)); 2500 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 2501 CRI_TXDEEMPH_OVERRIDE_5_0_MASK); 2502 val |= CRI_TXDEEMPH_OVERRIDE_5_0( 2503 ddi_translations[level].cri_txdeemph_override_5_0) | 2504 CRI_TXDEEMPH_OVERRIDE_11_6( 2505 ddi_translations[level].cri_txdeemph_override_11_6) | 2506 CRI_TXDEEMPH_OVERRIDE_EN; 2507 intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val); 2508 2509 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 2510 } 2511 2512 /* 2513 * Program MG_CLKHUB<LN, port being used> with value from frequency table 2514 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 2515 * values from table for which TX1 and TX2 enabled. 2516 */ 2517 for (ln = 0; ln < 2; ln++) { 2518 val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port)); 2519 if (link_clock < 300000) 2520 val |= CFG_LOW_RATE_LKREN_EN; 2521 else 2522 val &= ~CFG_LOW_RATE_LKREN_EN; 2523 intel_de_write(dev_priv, MG_CLKHUB(ln, tc_port), val); 2524 } 2525 2526 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 2527 for (ln = 0; ln < 2; ln++) { 2528 val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port)); 2529 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; 2530 if (link_clock <= 500000) { 2531 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; 2532 } else { 2533 val |= CFG_AMI_CK_DIV_OVERRIDE_EN | 2534 CFG_AMI_CK_DIV_OVERRIDE_VAL(1); 2535 } 2536 intel_de_write(dev_priv, MG_TX1_DCC(ln, tc_port), val); 2537 2538 val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port)); 2539 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; 2540 if (link_clock <= 500000) { 2541 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; 2542 } else { 2543 val |= CFG_AMI_CK_DIV_OVERRIDE_EN | 2544 CFG_AMI_CK_DIV_OVERRIDE_VAL(1); 2545 } 2546 intel_de_write(dev_priv, MG_TX2_DCC(ln, tc_port), val); 2547 } 2548 2549 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 2550 for (ln = 0; ln < 2; ln++) { 2551 val = intel_de_read(dev_priv, 2552 MG_TX1_PISO_READLOAD(ln, tc_port)); 2553 val |= CRI_CALCINIT; 2554 intel_de_write(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 2555 val); 2556 2557 val = intel_de_read(dev_priv, 2558 MG_TX2_PISO_READLOAD(ln, tc_port)); 2559 val |= CRI_CALCINIT; 2560 intel_de_write(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 2561 val); 2562 } 2563 } 2564 2565 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder, 2566 int link_clock, 2567 u32 level, 2568 enum intel_output_type type) 2569 { 2570 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2571 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2572 2573 if (intel_phy_is_combo(dev_priv, phy)) 2574 icl_combo_phy_ddi_vswing_sequence(encoder, level, type); 2575 else 2576 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level, 2577 type); 2578 } 2579 2580 static void 2581 tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock, 2582 u32 level, enum intel_output_type type) 2583 { 2584 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2585 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 2586 const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations; 2587 u32 n_entries, val, ln, dpcnt_mask, dpcnt_val; 2588 2589 if (type == INTEL_OUTPUT_HDMI) { 2590 n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans); 2591 ddi_translations = tgl_dkl_phy_hdmi_ddi_trans; 2592 } else { 2593 n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans); 2594 ddi_translations = tgl_dkl_phy_dp_ddi_trans; 2595 } 2596 2597 if (level >= n_entries) 2598 level = n_entries - 1; 2599 2600 dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK | 2601 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 2602 DKL_TX_VSWING_CONTROL_MASK); 2603 dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control); 2604 dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control); 2605 dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control); 2606 2607 for (ln = 0; ln < 2; ln++) { 2608 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2609 HIP_INDEX_VAL(tc_port, ln)); 2610 2611 intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0); 2612 2613 /* All the registers are RMW */ 2614 val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(tc_port)); 2615 val &= ~dpcnt_mask; 2616 val |= dpcnt_val; 2617 intel_de_write(dev_priv, DKL_TX_DPCNTL0(tc_port), val); 2618 2619 val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(tc_port)); 2620 val &= ~dpcnt_mask; 2621 val |= dpcnt_val; 2622 intel_de_write(dev_priv, DKL_TX_DPCNTL1(tc_port), val); 2623 2624 val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port)); 2625 val &= ~DKL_TX_DP20BITMODE; 2626 intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val); 2627 } 2628 } 2629 2630 static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder, 2631 int link_clock, 2632 u32 level, 2633 enum intel_output_type type) 2634 { 2635 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2636 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2637 2638 if (intel_phy_is_combo(dev_priv, phy)) 2639 icl_combo_phy_ddi_vswing_sequence(encoder, level, type); 2640 else 2641 tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level, type); 2642 } 2643 2644 static u32 translate_signal_level(struct intel_dp *intel_dp, int signal_levels) 2645 { 2646 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2647 int i; 2648 2649 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 2650 if (index_to_dp_signal_levels[i] == signal_levels) 2651 return i; 2652 } 2653 2654 drm_WARN(&i915->drm, 1, 2655 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 2656 signal_levels); 2657 2658 return 0; 2659 } 2660 2661 static u32 intel_ddi_dp_level(struct intel_dp *intel_dp) 2662 { 2663 u8 train_set = intel_dp->train_set[0]; 2664 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2665 DP_TRAIN_PRE_EMPHASIS_MASK); 2666 2667 return translate_signal_level(intel_dp, signal_levels); 2668 } 2669 2670 static void 2671 tgl_set_signal_levels(struct intel_dp *intel_dp) 2672 { 2673 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2674 int level = intel_ddi_dp_level(intel_dp); 2675 2676 tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate, 2677 level, encoder->type); 2678 } 2679 2680 static void 2681 icl_set_signal_levels(struct intel_dp *intel_dp) 2682 { 2683 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2684 int level = intel_ddi_dp_level(intel_dp); 2685 2686 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate, 2687 level, encoder->type); 2688 } 2689 2690 static void 2691 cnl_set_signal_levels(struct intel_dp *intel_dp) 2692 { 2693 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2694 int level = intel_ddi_dp_level(intel_dp); 2695 2696 cnl_ddi_vswing_sequence(encoder, level, encoder->type); 2697 } 2698 2699 static void 2700 bxt_set_signal_levels(struct intel_dp *intel_dp) 2701 { 2702 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2703 int level = intel_ddi_dp_level(intel_dp); 2704 2705 bxt_ddi_vswing_sequence(encoder, level, encoder->type); 2706 } 2707 2708 static void 2709 hsw_set_signal_levels(struct intel_dp *intel_dp) 2710 { 2711 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2712 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2713 int level = intel_ddi_dp_level(intel_dp); 2714 enum port port = encoder->port; 2715 u32 signal_levels; 2716 2717 signal_levels = DDI_BUF_TRANS_SELECT(level); 2718 2719 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 2720 signal_levels); 2721 2722 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 2723 intel_dp->DP |= signal_levels; 2724 2725 if (IS_GEN9_BC(dev_priv)) 2726 skl_ddi_set_iboost(encoder, level, encoder->type); 2727 2728 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 2729 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 2730 } 2731 2732 static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv, 2733 enum phy phy) 2734 { 2735 if (intel_phy_is_combo(dev_priv, phy)) { 2736 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 2737 } else if (intel_phy_is_tc(dev_priv, phy)) { 2738 enum tc_port tc_port = intel_port_to_tc(dev_priv, 2739 (enum port)phy); 2740 2741 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port); 2742 } 2743 2744 return 0; 2745 } 2746 2747 static void icl_map_plls_to_ports(struct intel_encoder *encoder, 2748 const struct intel_crtc_state *crtc_state) 2749 { 2750 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2751 struct intel_shared_dpll *pll = crtc_state->shared_dpll; 2752 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2753 u32 val; 2754 2755 mutex_lock(&dev_priv->dpll.lock); 2756 2757 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 2758 drm_WARN_ON(&dev_priv->drm, 2759 (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0); 2760 2761 if (intel_phy_is_combo(dev_priv, phy)) { 2762 /* 2763 * Even though this register references DDIs, note that we 2764 * want to pass the PHY rather than the port (DDI). For 2765 * ICL, port=phy in all cases so it doesn't matter, but for 2766 * EHL the bspec notes the following: 2767 * 2768 * "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA 2769 * Clock Select chooses the PLL for both DDIA and DDID and 2770 * drives port A in all cases." 2771 */ 2772 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 2773 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 2774 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 2775 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); 2776 } 2777 2778 val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 2779 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 2780 2781 mutex_unlock(&dev_priv->dpll.lock); 2782 } 2783 2784 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder) 2785 { 2786 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2787 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2788 u32 val; 2789 2790 mutex_lock(&dev_priv->dpll.lock); 2791 2792 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 2793 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 2794 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 2795 2796 mutex_unlock(&dev_priv->dpll.lock); 2797 } 2798 2799 static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv, 2800 u32 port_mask, bool ddi_clk_needed) 2801 { 2802 enum port port; 2803 u32 val; 2804 2805 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 2806 for_each_port_masked(port, port_mask) { 2807 enum phy phy = intel_port_to_phy(dev_priv, port); 2808 bool ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv, 2809 phy); 2810 2811 if (ddi_clk_needed == !ddi_clk_off) 2812 continue; 2813 2814 /* 2815 * Punt on the case now where clock is gated, but it would 2816 * be needed by the port. Something else is really broken then. 2817 */ 2818 if (drm_WARN_ON(&dev_priv->drm, ddi_clk_needed)) 2819 continue; 2820 2821 drm_notice(&dev_priv->drm, 2822 "PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2823 phy_name(phy)); 2824 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 2825 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 2826 } 2827 } 2828 2829 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2830 { 2831 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2832 u32 port_mask; 2833 bool ddi_clk_needed; 2834 2835 /* 2836 * In case of DP MST, we sanitize the primary encoder only, not the 2837 * virtual ones. 2838 */ 2839 if (encoder->type == INTEL_OUTPUT_DP_MST) 2840 return; 2841 2842 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2843 u8 pipe_mask; 2844 bool is_mst; 2845 2846 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2847 /* 2848 * In the unlikely case that BIOS enables DP in MST mode, just 2849 * warn since our MST HW readout is incomplete. 2850 */ 2851 if (drm_WARN_ON(&dev_priv->drm, is_mst)) 2852 return; 2853 } 2854 2855 port_mask = BIT(encoder->port); 2856 ddi_clk_needed = encoder->base.crtc; 2857 2858 if (encoder->type == INTEL_OUTPUT_DSI) { 2859 struct intel_encoder *other_encoder; 2860 2861 port_mask = intel_dsi_encoder_ports(encoder); 2862 /* 2863 * Sanity check that we haven't incorrectly registered another 2864 * encoder using any of the ports of this DSI encoder. 2865 */ 2866 for_each_intel_encoder(&dev_priv->drm, other_encoder) { 2867 if (other_encoder == encoder) 2868 continue; 2869 2870 if (drm_WARN_ON(&dev_priv->drm, 2871 port_mask & BIT(other_encoder->port))) 2872 return; 2873 } 2874 /* 2875 * For DSI we keep the ddi clocks gated 2876 * except during enable/disable sequence. 2877 */ 2878 ddi_clk_needed = false; 2879 } 2880 2881 icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed); 2882 } 2883 2884 static void intel_ddi_clk_select(struct intel_encoder *encoder, 2885 const struct intel_crtc_state *crtc_state) 2886 { 2887 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2888 enum port port = encoder->port; 2889 enum phy phy = intel_port_to_phy(dev_priv, port); 2890 u32 val; 2891 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 2892 2893 if (drm_WARN_ON(&dev_priv->drm, !pll)) 2894 return; 2895 2896 mutex_lock(&dev_priv->dpll.lock); 2897 2898 if (INTEL_GEN(dev_priv) >= 11) { 2899 if (!intel_phy_is_combo(dev_priv, phy)) 2900 intel_de_write(dev_priv, DDI_CLK_SEL(port), 2901 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 2902 else if (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C) 2903 /* 2904 * MG does not exist but the programming is required 2905 * to ungate DDIC and DDID 2906 */ 2907 intel_de_write(dev_priv, DDI_CLK_SEL(port), 2908 DDI_CLK_SEL_MG); 2909 } else if (IS_CANNONLAKE(dev_priv)) { 2910 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */ 2911 val = intel_de_read(dev_priv, DPCLKA_CFGCR0); 2912 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); 2913 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port); 2914 intel_de_write(dev_priv, DPCLKA_CFGCR0, val); 2915 2916 /* 2917 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI. 2918 * This step and the step before must be done with separate 2919 * register writes. 2920 */ 2921 val = intel_de_read(dev_priv, DPCLKA_CFGCR0); 2922 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); 2923 intel_de_write(dev_priv, DPCLKA_CFGCR0, val); 2924 } else if (IS_GEN9_BC(dev_priv)) { 2925 /* DDI -> PLL mapping */ 2926 val = intel_de_read(dev_priv, DPLL_CTRL2); 2927 2928 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | 2929 DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); 2930 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 2931 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 2932 2933 intel_de_write(dev_priv, DPLL_CTRL2, val); 2934 2935 } else if (INTEL_GEN(dev_priv) < 9) { 2936 intel_de_write(dev_priv, PORT_CLK_SEL(port), 2937 hsw_pll_to_ddi_pll_sel(pll)); 2938 } 2939 2940 mutex_unlock(&dev_priv->dpll.lock); 2941 } 2942 2943 static void intel_ddi_clk_disable(struct intel_encoder *encoder) 2944 { 2945 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2946 enum port port = encoder->port; 2947 enum phy phy = intel_port_to_phy(dev_priv, port); 2948 2949 if (INTEL_GEN(dev_priv) >= 11) { 2950 if (!intel_phy_is_combo(dev_priv, phy) || 2951 (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C)) 2952 intel_de_write(dev_priv, DDI_CLK_SEL(port), 2953 DDI_CLK_SEL_NONE); 2954 } else if (IS_CANNONLAKE(dev_priv)) { 2955 intel_de_write(dev_priv, DPCLKA_CFGCR0, 2956 intel_de_read(dev_priv, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port)); 2957 } else if (IS_GEN9_BC(dev_priv)) { 2958 intel_de_write(dev_priv, DPLL_CTRL2, 2959 intel_de_read(dev_priv, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port)); 2960 } else if (INTEL_GEN(dev_priv) < 9) { 2961 intel_de_write(dev_priv, PORT_CLK_SEL(port), 2962 PORT_CLK_SEL_NONE); 2963 } 2964 } 2965 2966 static void 2967 icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port, 2968 const struct intel_crtc_state *crtc_state) 2969 { 2970 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); 2971 enum tc_port tc_port = intel_port_to_tc(dev_priv, intel_dig_port->base.port); 2972 u32 ln0, ln1, pin_assignment; 2973 u8 width; 2974 2975 if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT) 2976 return; 2977 2978 if (INTEL_GEN(dev_priv) >= 12) { 2979 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2980 HIP_INDEX_VAL(tc_port, 0x0)); 2981 ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); 2982 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2983 HIP_INDEX_VAL(tc_port, 0x1)); 2984 ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); 2985 } else { 2986 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 2987 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 2988 } 2989 2990 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2991 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2992 2993 /* DPPATC */ 2994 pin_assignment = intel_tc_port_get_pin_assignment_mask(intel_dig_port); 2995 width = crtc_state->lane_count; 2996 2997 switch (pin_assignment) { 2998 case 0x0: 2999 drm_WARN_ON(&dev_priv->drm, 3000 intel_dig_port->tc_mode != TC_PORT_LEGACY); 3001 if (width == 1) { 3002 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 3003 } else { 3004 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3005 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3006 } 3007 break; 3008 case 0x1: 3009 if (width == 4) { 3010 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3011 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3012 } 3013 break; 3014 case 0x2: 3015 if (width == 2) { 3016 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3017 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3018 } 3019 break; 3020 case 0x3: 3021 case 0x5: 3022 if (width == 1) { 3023 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 3024 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 3025 } else { 3026 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3027 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3028 } 3029 break; 3030 case 0x4: 3031 case 0x6: 3032 if (width == 1) { 3033 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 3034 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 3035 } else { 3036 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3037 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3038 } 3039 break; 3040 default: 3041 MISSING_CASE(pin_assignment); 3042 } 3043 3044 if (INTEL_GEN(dev_priv) >= 12) { 3045 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 3046 HIP_INDEX_VAL(tc_port, 0x0)); 3047 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0); 3048 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 3049 HIP_INDEX_VAL(tc_port, 0x1)); 3050 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1); 3051 } else { 3052 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 3053 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 3054 } 3055 } 3056 3057 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 3058 const struct intel_crtc_state *crtc_state) 3059 { 3060 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3061 3062 if (!crtc_state->fec_enable) 3063 return; 3064 3065 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0) 3066 drm_dbg_kms(&i915->drm, 3067 "Failed to set FEC_READY in the sink\n"); 3068 } 3069 3070 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 3071 const struct intel_crtc_state *crtc_state) 3072 { 3073 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3074 struct intel_dp *intel_dp; 3075 u32 val; 3076 3077 if (!crtc_state->fec_enable) 3078 return; 3079 3080 intel_dp = enc_to_intel_dp(encoder); 3081 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 3082 val |= DP_TP_CTL_FEC_ENABLE; 3083 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val); 3084 3085 if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, 3086 DP_TP_STATUS_FEC_ENABLE_LIVE, 1)) 3087 drm_err(&dev_priv->drm, 3088 "Timed out waiting for FEC Enable Status\n"); 3089 } 3090 3091 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder, 3092 const struct intel_crtc_state *crtc_state) 3093 { 3094 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3095 struct intel_dp *intel_dp; 3096 u32 val; 3097 3098 if (!crtc_state->fec_enable) 3099 return; 3100 3101 intel_dp = enc_to_intel_dp(encoder); 3102 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 3103 val &= ~DP_TP_CTL_FEC_ENABLE; 3104 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val); 3105 intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl); 3106 } 3107 3108 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 3109 struct intel_encoder *encoder, 3110 const struct intel_crtc_state *crtc_state, 3111 const struct drm_connector_state *conn_state) 3112 { 3113 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3114 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3115 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3116 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3117 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 3118 int level = intel_ddi_dp_level(intel_dp); 3119 enum transcoder transcoder = crtc_state->cpu_transcoder; 3120 3121 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, 3122 crtc_state->lane_count, is_mst); 3123 3124 intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder); 3125 intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder); 3126 3127 /* 3128 * 1. Enable Power Wells 3129 * 3130 * This was handled at the beginning of intel_atomic_commit_tail(), 3131 * before we called down into this function. 3132 */ 3133 3134 /* 2. Enable Panel Power if PPS is required */ 3135 intel_edp_panel_on(intel_dp); 3136 3137 /* 3138 * 3. For non-TBT Type-C ports, set FIA lane count 3139 * (DFLEXDPSP.DPX4TXLATC) 3140 * 3141 * This was done before tgl_ddi_pre_enable_dp by 3142 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 3143 */ 3144 3145 /* 3146 * 4. Enable the port PLL. 3147 * 3148 * The PLL enabling itself was already done before this function by 3149 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 3150 * configure the PLL to port mapping here. 3151 */ 3152 intel_ddi_clk_select(encoder, crtc_state); 3153 3154 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 3155 if (!intel_phy_is_tc(dev_priv, phy) || 3156 dig_port->tc_mode != TC_PORT_TBT_ALT) 3157 intel_display_power_get(dev_priv, 3158 dig_port->ddi_io_power_domain); 3159 3160 /* 6. Program DP_MODE */ 3161 icl_program_mg_dp_mode(dig_port, crtc_state); 3162 3163 /* 3164 * 7. The rest of the below are substeps under the bspec's "Enable and 3165 * Train Display Port" step. Note that steps that are specific to 3166 * MST will be handled by intel_mst_pre_enable_dp() before/after it 3167 * calls into this function. Also intel_mst_pre_enable_dp() only calls 3168 * us when active_mst_links==0, so any steps designated for "single 3169 * stream or multi-stream master transcoder" can just be performed 3170 * unconditionally here. 3171 */ 3172 3173 /* 3174 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 3175 * Transcoder. 3176 */ 3177 intel_ddi_enable_pipe_clock(encoder, crtc_state); 3178 3179 /* 3180 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 3181 * Transport Select 3182 */ 3183 intel_ddi_config_transcoder_func(encoder, crtc_state); 3184 3185 /* 3186 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 3187 * selected 3188 * 3189 * This will be handled by the intel_dp_start_link_train() farther 3190 * down this function. 3191 */ 3192 3193 /* 7.e Configure voltage swing and related IO settings */ 3194 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level, 3195 encoder->type); 3196 3197 /* 3198 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 3199 * the used lanes of the DDI. 3200 */ 3201 if (intel_phy_is_combo(dev_priv, phy)) { 3202 bool lane_reversal = 3203 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 3204 3205 intel_combo_phy_power_up_lanes(dev_priv, phy, false, 3206 crtc_state->lane_count, 3207 lane_reversal); 3208 } 3209 3210 /* 3211 * 7.g Configure and enable DDI_BUF_CTL 3212 * 7.h Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout 3213 * after 500 us. 3214 * 3215 * We only configure what the register value will be here. Actual 3216 * enabling happens during link training farther down. 3217 */ 3218 intel_ddi_init_dp_buf_reg(encoder); 3219 3220 if (!is_mst) 3221 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 3222 3223 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); 3224 /* 3225 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 3226 * in the FEC_CONFIGURATION register to 1 before initiating link 3227 * training 3228 */ 3229 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 3230 3231 /* 3232 * 7.i Follow DisplayPort specification training sequence (see notes for 3233 * failure handling) 3234 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 3235 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 3236 * (timeout after 800 us) 3237 */ 3238 intel_dp_start_link_train(intel_dp); 3239 3240 /* 7.k Set DP_TP_CTL link training to Normal */ 3241 if (!is_trans_port_sync_mode(crtc_state)) 3242 intel_dp_stop_link_train(intel_dp); 3243 3244 /* 7.l Configure and enable FEC if needed */ 3245 intel_ddi_enable_fec(encoder, crtc_state); 3246 intel_dsc_enable(encoder, crtc_state); 3247 } 3248 3249 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 3250 struct intel_encoder *encoder, 3251 const struct intel_crtc_state *crtc_state, 3252 const struct drm_connector_state *conn_state) 3253 { 3254 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3255 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3256 enum port port = encoder->port; 3257 enum phy phy = intel_port_to_phy(dev_priv, port); 3258 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3259 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 3260 int level = intel_ddi_dp_level(intel_dp); 3261 3262 if (INTEL_GEN(dev_priv) < 11) 3263 drm_WARN_ON(&dev_priv->drm, 3264 is_mst && (port == PORT_A || port == PORT_E)); 3265 else 3266 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 3267 3268 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, 3269 crtc_state->lane_count, is_mst); 3270 3271 intel_edp_panel_on(intel_dp); 3272 3273 intel_ddi_clk_select(encoder, crtc_state); 3274 3275 if (!intel_phy_is_tc(dev_priv, phy) || 3276 dig_port->tc_mode != TC_PORT_TBT_ALT) 3277 intel_display_power_get(dev_priv, 3278 dig_port->ddi_io_power_domain); 3279 3280 icl_program_mg_dp_mode(dig_port, crtc_state); 3281 3282 if (INTEL_GEN(dev_priv) >= 11) 3283 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, 3284 level, encoder->type); 3285 else if (IS_CANNONLAKE(dev_priv)) 3286 cnl_ddi_vswing_sequence(encoder, level, encoder->type); 3287 else if (IS_GEN9_LP(dev_priv)) 3288 bxt_ddi_vswing_sequence(encoder, level, encoder->type); 3289 else 3290 intel_prepare_dp_ddi_buffers(encoder, crtc_state); 3291 3292 if (intel_phy_is_combo(dev_priv, phy)) { 3293 bool lane_reversal = 3294 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 3295 3296 intel_combo_phy_power_up_lanes(dev_priv, phy, false, 3297 crtc_state->lane_count, 3298 lane_reversal); 3299 } 3300 3301 intel_ddi_init_dp_buf_reg(encoder); 3302 if (!is_mst) 3303 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 3304 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, 3305 true); 3306 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 3307 intel_dp_start_link_train(intel_dp); 3308 if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) && 3309 !is_trans_port_sync_mode(crtc_state)) 3310 intel_dp_stop_link_train(intel_dp); 3311 3312 intel_ddi_enable_fec(encoder, crtc_state); 3313 3314 if (!is_mst) 3315 intel_ddi_enable_pipe_clock(encoder, crtc_state); 3316 3317 intel_dsc_enable(encoder, crtc_state); 3318 } 3319 3320 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 3321 struct intel_encoder *encoder, 3322 const struct intel_crtc_state *crtc_state, 3323 const struct drm_connector_state *conn_state) 3324 { 3325 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3326 3327 if (INTEL_GEN(dev_priv) >= 12) 3328 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 3329 else 3330 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 3331 3332 /* MST will call a setting of MSA after an allocating of Virtual Channel 3333 * from MST encoder pre_enable callback. 3334 */ 3335 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3336 intel_ddi_set_dp_msa(crtc_state, conn_state); 3337 3338 intel_dp_set_m_n(crtc_state, M1_N1); 3339 } 3340 } 3341 3342 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 3343 struct intel_encoder *encoder, 3344 const struct intel_crtc_state *crtc_state, 3345 const struct drm_connector_state *conn_state) 3346 { 3347 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 3348 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 3349 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3350 int level = intel_ddi_hdmi_level(encoder); 3351 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3352 3353 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 3354 intel_ddi_clk_select(encoder, crtc_state); 3355 3356 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); 3357 3358 icl_program_mg_dp_mode(dig_port, crtc_state); 3359 3360 if (INTEL_GEN(dev_priv) >= 12) 3361 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, 3362 level, INTEL_OUTPUT_HDMI); 3363 else if (INTEL_GEN(dev_priv) == 11) 3364 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, 3365 level, INTEL_OUTPUT_HDMI); 3366 else if (IS_CANNONLAKE(dev_priv)) 3367 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI); 3368 else if (IS_GEN9_LP(dev_priv)) 3369 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI); 3370 else 3371 intel_prepare_hdmi_ddi_buffers(encoder, level); 3372 3373 if (IS_GEN9_BC(dev_priv)) 3374 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI); 3375 3376 intel_ddi_enable_pipe_clock(encoder, crtc_state); 3377 3378 intel_dig_port->set_infoframes(encoder, 3379 crtc_state->has_infoframe, 3380 crtc_state, conn_state); 3381 } 3382 3383 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 3384 struct intel_encoder *encoder, 3385 const struct intel_crtc_state *crtc_state, 3386 const struct drm_connector_state *conn_state) 3387 { 3388 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3389 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3390 enum pipe pipe = crtc->pipe; 3391 3392 /* 3393 * When called from DP MST code: 3394 * - conn_state will be NULL 3395 * - encoder will be the main encoder (ie. mst->primary) 3396 * - the main connector associated with this port 3397 * won't be active or linked to a crtc 3398 * - crtc_state will be the state of the first stream to 3399 * be activated on this port, and it may not be the same 3400 * stream that will be deactivated last, but each stream 3401 * should have a state that is identical when it comes to 3402 * the DP link parameteres 3403 */ 3404 3405 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 3406 3407 if (INTEL_GEN(dev_priv) >= 11) 3408 icl_map_plls_to_ports(encoder, crtc_state); 3409 3410 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 3411 3412 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 3413 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 3414 conn_state); 3415 } else { 3416 struct intel_lspcon *lspcon = 3417 enc_to_intel_lspcon(encoder); 3418 3419 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 3420 conn_state); 3421 if (lspcon->active) { 3422 struct intel_digital_port *dig_port = 3423 enc_to_dig_port(encoder); 3424 3425 dig_port->set_infoframes(encoder, 3426 crtc_state->has_infoframe, 3427 crtc_state, conn_state); 3428 } 3429 } 3430 } 3431 3432 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 3433 const struct intel_crtc_state *crtc_state) 3434 { 3435 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3436 enum port port = encoder->port; 3437 bool wait = false; 3438 u32 val; 3439 3440 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3441 if (val & DDI_BUF_CTL_ENABLE) { 3442 val &= ~DDI_BUF_CTL_ENABLE; 3443 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 3444 wait = true; 3445 } 3446 3447 if (intel_crtc_has_dp_encoder(crtc_state)) { 3448 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3449 3450 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 3451 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 3452 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 3453 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val); 3454 } 3455 3456 /* Disable FEC in DP Sink */ 3457 intel_ddi_disable_fec_state(encoder, crtc_state); 3458 3459 if (wait) 3460 intel_wait_ddi_buf_idle(dev_priv, port); 3461 } 3462 3463 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 3464 struct intel_encoder *encoder, 3465 const struct intel_crtc_state *old_crtc_state, 3466 const struct drm_connector_state *old_conn_state) 3467 { 3468 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3469 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3470 struct intel_dp *intel_dp = &dig_port->dp; 3471 bool is_mst = intel_crtc_has_type(old_crtc_state, 3472 INTEL_OUTPUT_DP_MST); 3473 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3474 3475 if (!is_mst) 3476 intel_dp_set_infoframes(encoder, false, 3477 old_crtc_state, old_conn_state); 3478 3479 /* 3480 * Power down sink before disabling the port, otherwise we end 3481 * up getting interrupts from the sink on detecting link loss. 3482 */ 3483 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 3484 3485 if (INTEL_GEN(dev_priv) >= 12) { 3486 if (is_mst) { 3487 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 3488 u32 val; 3489 3490 val = intel_de_read(dev_priv, 3491 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3492 val &= ~(TGL_TRANS_DDI_PORT_MASK | 3493 TRANS_DDI_MODE_SELECT_MASK); 3494 intel_de_write(dev_priv, 3495 TRANS_DDI_FUNC_CTL(cpu_transcoder), 3496 val); 3497 } 3498 } else { 3499 if (!is_mst) 3500 intel_ddi_disable_pipe_clock(old_crtc_state); 3501 } 3502 3503 intel_disable_ddi_buf(encoder, old_crtc_state); 3504 3505 /* 3506 * From TGL spec: "If single stream or multi-stream master transcoder: 3507 * Configure Transcoder Clock select to direct no clock to the 3508 * transcoder" 3509 */ 3510 if (INTEL_GEN(dev_priv) >= 12) 3511 intel_ddi_disable_pipe_clock(old_crtc_state); 3512 3513 intel_edp_panel_vdd_on(intel_dp); 3514 intel_edp_panel_off(intel_dp); 3515 3516 if (!intel_phy_is_tc(dev_priv, phy) || 3517 dig_port->tc_mode != TC_PORT_TBT_ALT) 3518 intel_display_power_put_unchecked(dev_priv, 3519 dig_port->ddi_io_power_domain); 3520 3521 intel_ddi_clk_disable(encoder); 3522 } 3523 3524 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 3525 struct intel_encoder *encoder, 3526 const struct intel_crtc_state *old_crtc_state, 3527 const struct drm_connector_state *old_conn_state) 3528 { 3529 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3530 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3531 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3532 3533 dig_port->set_infoframes(encoder, false, 3534 old_crtc_state, old_conn_state); 3535 3536 intel_ddi_disable_pipe_clock(old_crtc_state); 3537 3538 intel_disable_ddi_buf(encoder, old_crtc_state); 3539 3540 intel_display_power_put_unchecked(dev_priv, 3541 dig_port->ddi_io_power_domain); 3542 3543 intel_ddi_clk_disable(encoder); 3544 3545 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3546 } 3547 3548 static void intel_ddi_post_disable(struct intel_atomic_state *state, 3549 struct intel_encoder *encoder, 3550 const struct intel_crtc_state *old_crtc_state, 3551 const struct drm_connector_state *old_conn_state) 3552 { 3553 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3554 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3555 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3556 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 3557 3558 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) { 3559 intel_crtc_vblank_off(old_crtc_state); 3560 3561 intel_disable_pipe(old_crtc_state); 3562 3563 intel_ddi_disable_transcoder_func(old_crtc_state); 3564 3565 intel_dsc_disable(old_crtc_state); 3566 3567 if (INTEL_GEN(dev_priv) >= 9) 3568 skl_scaler_disable(old_crtc_state); 3569 else 3570 ilk_pfit_disable(old_crtc_state); 3571 } 3572 3573 /* 3574 * When called from DP MST code: 3575 * - old_conn_state will be NULL 3576 * - encoder will be the main encoder (ie. mst->primary) 3577 * - the main connector associated with this port 3578 * won't be active or linked to a crtc 3579 * - old_crtc_state will be the state of the last stream to 3580 * be deactivated on this port, and it may not be the same 3581 * stream that was activated last, but each stream 3582 * should have a state that is identical when it comes to 3583 * the DP link parameteres 3584 */ 3585 3586 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3587 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 3588 old_conn_state); 3589 else 3590 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 3591 old_conn_state); 3592 3593 if (INTEL_GEN(dev_priv) >= 11) 3594 icl_unmap_plls_to_ports(encoder); 3595 3596 if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port) 3597 intel_display_power_put_unchecked(dev_priv, 3598 intel_ddi_main_link_aux_domain(dig_port)); 3599 3600 if (is_tc_port) 3601 intel_tc_port_put_link(dig_port); 3602 } 3603 3604 void intel_ddi_fdi_post_disable(struct intel_atomic_state *state, 3605 struct intel_encoder *encoder, 3606 const struct intel_crtc_state *old_crtc_state, 3607 const struct drm_connector_state *old_conn_state) 3608 { 3609 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3610 u32 val; 3611 3612 /* 3613 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable) 3614 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN, 3615 * step 13 is the correct place for it. Step 18 is where it was 3616 * originally before the BUN. 3617 */ 3618 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 3619 val &= ~FDI_RX_ENABLE; 3620 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 3621 3622 intel_disable_ddi_buf(encoder, old_crtc_state); 3623 intel_ddi_clk_disable(encoder); 3624 3625 val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); 3626 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 3627 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 3628 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val); 3629 3630 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 3631 val &= ~FDI_PCDCLK; 3632 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 3633 3634 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 3635 val &= ~FDI_RX_PLL_ENABLE; 3636 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 3637 } 3638 3639 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 3640 struct intel_encoder *encoder, 3641 const struct intel_crtc_state *crtc_state) 3642 { 3643 const struct drm_connector_state *conn_state; 3644 struct drm_connector *conn; 3645 int i; 3646 3647 if (!crtc_state->sync_mode_slaves_mask) 3648 return; 3649 3650 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 3651 struct intel_encoder *slave_encoder = 3652 to_intel_encoder(conn_state->best_encoder); 3653 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 3654 const struct intel_crtc_state *slave_crtc_state; 3655 3656 if (!slave_crtc) 3657 continue; 3658 3659 slave_crtc_state = 3660 intel_atomic_get_new_crtc_state(state, slave_crtc); 3661 3662 if (slave_crtc_state->master_transcoder != 3663 crtc_state->cpu_transcoder) 3664 continue; 3665 3666 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder)); 3667 } 3668 3669 usleep_range(200, 400); 3670 3671 intel_dp_stop_link_train(enc_to_intel_dp(encoder)); 3672 } 3673 3674 static void intel_enable_ddi_dp(struct intel_atomic_state *state, 3675 struct intel_encoder *encoder, 3676 const struct intel_crtc_state *crtc_state, 3677 const struct drm_connector_state *conn_state) 3678 { 3679 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3680 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3681 enum port port = encoder->port; 3682 3683 if (port == PORT_A && INTEL_GEN(dev_priv) < 9) 3684 intel_dp_stop_link_train(intel_dp); 3685 3686 intel_edp_backlight_on(crtc_state, conn_state); 3687 intel_psr_enable(intel_dp, crtc_state, conn_state); 3688 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3689 intel_edp_drrs_enable(intel_dp, crtc_state); 3690 3691 if (crtc_state->has_audio) 3692 intel_audio_codec_enable(encoder, crtc_state, conn_state); 3693 3694 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3695 } 3696 3697 static i915_reg_t 3698 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 3699 enum port port) 3700 { 3701 static const enum transcoder trans[] = { 3702 [PORT_A] = TRANSCODER_EDP, 3703 [PORT_B] = TRANSCODER_A, 3704 [PORT_C] = TRANSCODER_B, 3705 [PORT_D] = TRANSCODER_C, 3706 [PORT_E] = TRANSCODER_A, 3707 }; 3708 3709 drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) < 9); 3710 3711 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) 3712 port = PORT_A; 3713 3714 return CHICKEN_TRANS(trans[port]); 3715 } 3716 3717 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, 3718 struct intel_encoder *encoder, 3719 const struct intel_crtc_state *crtc_state, 3720 const struct drm_connector_state *conn_state) 3721 { 3722 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3723 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3724 struct drm_connector *connector = conn_state->connector; 3725 enum port port = encoder->port; 3726 3727 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3728 crtc_state->hdmi_high_tmds_clock_ratio, 3729 crtc_state->hdmi_scrambling)) 3730 drm_dbg_kms(&dev_priv->drm, 3731 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3732 connector->base.id, connector->name); 3733 3734 /* Display WA #1143: skl,kbl,cfl */ 3735 if (IS_GEN9_BC(dev_priv)) { 3736 /* 3737 * For some reason these chicken bits have been 3738 * stuffed into a transcoder register, event though 3739 * the bits affect a specific DDI port rather than 3740 * a specific transcoder. 3741 */ 3742 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 3743 u32 val; 3744 3745 val = intel_de_read(dev_priv, reg); 3746 3747 if (port == PORT_E) 3748 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3749 DDIE_TRAINING_OVERRIDE_VALUE; 3750 else 3751 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3752 DDI_TRAINING_OVERRIDE_VALUE; 3753 3754 intel_de_write(dev_priv, reg, val); 3755 intel_de_posting_read(dev_priv, reg); 3756 3757 udelay(1); 3758 3759 if (port == PORT_E) 3760 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3761 DDIE_TRAINING_OVERRIDE_VALUE); 3762 else 3763 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3764 DDI_TRAINING_OVERRIDE_VALUE); 3765 3766 intel_de_write(dev_priv, reg, val); 3767 } 3768 3769 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3770 * are ignored so nothing special needs to be done besides 3771 * enabling the port. 3772 */ 3773 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3774 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE); 3775 3776 if (crtc_state->has_audio) 3777 intel_audio_codec_enable(encoder, crtc_state, conn_state); 3778 } 3779 3780 static void intel_enable_ddi(struct intel_atomic_state *state, 3781 struct intel_encoder *encoder, 3782 const struct intel_crtc_state *crtc_state, 3783 const struct drm_connector_state *conn_state) 3784 { 3785 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 3786 3787 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3788 3789 intel_enable_pipe(crtc_state); 3790 3791 intel_crtc_vblank_on(crtc_state); 3792 3793 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3794 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state); 3795 else 3796 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state); 3797 3798 /* Enable hdcp if it's desired */ 3799 if (conn_state->content_protection == 3800 DRM_MODE_CONTENT_PROTECTION_DESIRED) 3801 intel_hdcp_enable(to_intel_connector(conn_state->connector), 3802 crtc_state->cpu_transcoder, 3803 (u8)conn_state->hdcp_content_type); 3804 } 3805 3806 static void intel_disable_ddi_dp(struct intel_atomic_state *state, 3807 struct intel_encoder *encoder, 3808 const struct intel_crtc_state *old_crtc_state, 3809 const struct drm_connector_state *old_conn_state) 3810 { 3811 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3812 3813 intel_dp->link_trained = false; 3814 3815 if (old_crtc_state->has_audio) 3816 intel_audio_codec_disable(encoder, 3817 old_crtc_state, old_conn_state); 3818 3819 intel_edp_drrs_disable(intel_dp, old_crtc_state); 3820 intel_psr_disable(intel_dp, old_crtc_state); 3821 intel_edp_backlight_off(old_conn_state); 3822 /* Disable the decompression in DP Sink */ 3823 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, 3824 false); 3825 } 3826 3827 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state, 3828 struct intel_encoder *encoder, 3829 const struct intel_crtc_state *old_crtc_state, 3830 const struct drm_connector_state *old_conn_state) 3831 { 3832 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3833 struct drm_connector *connector = old_conn_state->connector; 3834 3835 if (old_crtc_state->has_audio) 3836 intel_audio_codec_disable(encoder, 3837 old_crtc_state, old_conn_state); 3838 3839 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3840 false, false)) 3841 drm_dbg_kms(&i915->drm, 3842 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3843 connector->base.id, connector->name); 3844 } 3845 3846 static void intel_disable_ddi(struct intel_atomic_state *state, 3847 struct intel_encoder *encoder, 3848 const struct intel_crtc_state *old_crtc_state, 3849 const struct drm_connector_state *old_conn_state) 3850 { 3851 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3852 3853 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3854 intel_disable_ddi_hdmi(state, encoder, old_crtc_state, 3855 old_conn_state); 3856 else 3857 intel_disable_ddi_dp(state, encoder, old_crtc_state, 3858 old_conn_state); 3859 } 3860 3861 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3862 struct intel_encoder *encoder, 3863 const struct intel_crtc_state *crtc_state, 3864 const struct drm_connector_state *conn_state) 3865 { 3866 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3867 3868 intel_ddi_set_dp_msa(crtc_state, conn_state); 3869 3870 intel_psr_update(intel_dp, crtc_state, conn_state); 3871 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3872 intel_edp_drrs_enable(intel_dp, crtc_state); 3873 3874 intel_panel_update_backlight(state, encoder, crtc_state, conn_state); 3875 } 3876 3877 static void intel_ddi_update_pipe(struct intel_atomic_state *state, 3878 struct intel_encoder *encoder, 3879 const struct intel_crtc_state *crtc_state, 3880 const struct drm_connector_state *conn_state) 3881 { 3882 3883 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3884 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3885 conn_state); 3886 3887 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3888 } 3889 3890 static void 3891 intel_ddi_update_prepare(struct intel_atomic_state *state, 3892 struct intel_encoder *encoder, 3893 struct intel_crtc *crtc) 3894 { 3895 struct intel_crtc_state *crtc_state = 3896 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL; 3897 int required_lanes = crtc_state ? crtc_state->lane_count : 1; 3898 3899 drm_WARN_ON(state->base.dev, crtc && crtc->active); 3900 3901 intel_tc_port_get_link(enc_to_dig_port(encoder), 3902 required_lanes); 3903 if (crtc_state && crtc_state->hw.active) 3904 intel_update_active_dpll(state, crtc, encoder); 3905 } 3906 3907 static void 3908 intel_ddi_update_complete(struct intel_atomic_state *state, 3909 struct intel_encoder *encoder, 3910 struct intel_crtc *crtc) 3911 { 3912 intel_tc_port_put_link(enc_to_dig_port(encoder)); 3913 } 3914 3915 static void 3916 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3917 struct intel_encoder *encoder, 3918 const struct intel_crtc_state *crtc_state, 3919 const struct drm_connector_state *conn_state) 3920 { 3921 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3922 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3923 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3924 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 3925 3926 if (is_tc_port) 3927 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3928 3929 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) 3930 intel_display_power_get(dev_priv, 3931 intel_ddi_main_link_aux_domain(dig_port)); 3932 3933 if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT) 3934 /* 3935 * Program the lane count for static/dynamic connections on 3936 * Type-C ports. Skip this step for TBT. 3937 */ 3938 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3939 else if (IS_GEN9_LP(dev_priv)) 3940 bxt_ddi_phy_set_lane_optim_mask(encoder, 3941 crtc_state->lane_lat_optim_mask); 3942 } 3943 3944 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) 3945 { 3946 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3947 struct drm_i915_private *dev_priv = 3948 to_i915(intel_dig_port->base.base.dev); 3949 enum port port = intel_dig_port->base.port; 3950 u32 dp_tp_ctl, ddi_buf_ctl; 3951 bool wait = false; 3952 3953 dp_tp_ctl = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 3954 3955 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 3956 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3957 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 3958 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3959 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 3960 wait = true; 3961 } 3962 3963 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 3964 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1; 3965 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl); 3966 intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl); 3967 3968 if (wait) 3969 intel_wait_ddi_buf_idle(dev_priv, port); 3970 } 3971 3972 dp_tp_ctl = DP_TP_CTL_ENABLE | 3973 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; 3974 if (intel_dp->link_mst) 3975 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3976 else { 3977 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3978 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 3979 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3980 } 3981 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl); 3982 intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl); 3983 3984 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3985 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3986 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3987 3988 udelay(600); 3989 } 3990 3991 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3992 u8 dp_train_pat) 3993 { 3994 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 3995 u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd); 3996 enum port port = dp_to_dig_port(intel_dp)->base.port; 3997 u32 temp; 3998 3999 temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 4000 4001 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) 4002 temp |= DP_TP_CTL_SCRAMBLE_DISABLE; 4003 else 4004 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; 4005 4006 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 4007 switch (dp_train_pat & train_pat_mask) { 4008 case DP_TRAINING_PATTERN_DISABLE: 4009 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 4010 break; 4011 case DP_TRAINING_PATTERN_1: 4012 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 4013 break; 4014 case DP_TRAINING_PATTERN_2: 4015 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 4016 break; 4017 case DP_TRAINING_PATTERN_3: 4018 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 4019 break; 4020 case DP_TRAINING_PATTERN_4: 4021 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 4022 break; 4023 } 4024 4025 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, temp); 4026 4027 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 4028 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 4029 } 4030 4031 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp) 4032 { 4033 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 4034 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4035 enum port port = encoder->port; 4036 u32 val; 4037 4038 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 4039 val &= ~DP_TP_CTL_LINK_TRAIN_MASK; 4040 val |= DP_TP_CTL_LINK_TRAIN_IDLE; 4041 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val); 4042 4043 /* 4044 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 4045 * reason we need to set idle transmission mode is to work around a HW 4046 * issue where we enable the pipe while not in idle link-training mode. 4047 * In this case there is requirement to wait for a minimum number of 4048 * idle patterns to be sent. 4049 */ 4050 if (port == PORT_A && INTEL_GEN(dev_priv) < 12) 4051 return; 4052 4053 if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, 4054 DP_TP_STATUS_IDLE_DONE, 1)) 4055 drm_err(&dev_priv->drm, 4056 "Timed out waiting for DP idle patterns\n"); 4057 } 4058 4059 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 4060 enum transcoder cpu_transcoder) 4061 { 4062 if (cpu_transcoder == TRANSCODER_EDP) 4063 return false; 4064 4065 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) 4066 return false; 4067 4068 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 4069 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 4070 } 4071 4072 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, 4073 struct intel_crtc_state *crtc_state) 4074 { 4075 if (INTEL_GEN(dev_priv) >= 12 && crtc_state->port_clock > 594000) 4076 crtc_state->min_voltage_level = 2; 4077 else if (IS_ELKHARTLAKE(dev_priv) && crtc_state->port_clock > 594000) 4078 crtc_state->min_voltage_level = 3; 4079 else if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000) 4080 crtc_state->min_voltage_level = 1; 4081 else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000) 4082 crtc_state->min_voltage_level = 2; 4083 } 4084 4085 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, 4086 enum transcoder cpu_transcoder) 4087 { 4088 u32 master_select; 4089 4090 if (INTEL_GEN(dev_priv) >= 11) { 4091 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder)); 4092 4093 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 4094 return INVALID_TRANSCODER; 4095 4096 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 4097 } else { 4098 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 4099 4100 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 4101 return INVALID_TRANSCODER; 4102 4103 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 4104 } 4105 4106 if (master_select == 0) 4107 return TRANSCODER_EDP; 4108 else 4109 return master_select - 1; 4110 } 4111 4112 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 4113 { 4114 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 4115 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 4116 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 4117 enum transcoder cpu_transcoder; 4118 4119 crtc_state->master_transcoder = 4120 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); 4121 4122 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { 4123 enum intel_display_power_domain power_domain; 4124 intel_wakeref_t trans_wakeref; 4125 4126 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 4127 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 4128 power_domain); 4129 4130 if (!trans_wakeref) 4131 continue; 4132 4133 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == 4134 crtc_state->cpu_transcoder) 4135 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 4136 4137 intel_display_power_put(dev_priv, power_domain, trans_wakeref); 4138 } 4139 4140 drm_WARN_ON(&dev_priv->drm, 4141 crtc_state->master_transcoder != INVALID_TRANSCODER && 4142 crtc_state->sync_mode_slaves_mask); 4143 } 4144 4145 void intel_ddi_get_config(struct intel_encoder *encoder, 4146 struct intel_crtc_state *pipe_config) 4147 { 4148 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4149 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); 4150 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4151 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4152 u32 temp, flags = 0; 4153 4154 /* XXX: DSI transcoder paranoia */ 4155 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 4156 return; 4157 4158 if (INTEL_GEN(dev_priv) >= 12) { 4159 intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(cpu_transcoder); 4160 intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(cpu_transcoder); 4161 } 4162 4163 intel_dsc_get_config(encoder, pipe_config); 4164 4165 temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 4166 if (temp & TRANS_DDI_PHSYNC) 4167 flags |= DRM_MODE_FLAG_PHSYNC; 4168 else 4169 flags |= DRM_MODE_FLAG_NHSYNC; 4170 if (temp & TRANS_DDI_PVSYNC) 4171 flags |= DRM_MODE_FLAG_PVSYNC; 4172 else 4173 flags |= DRM_MODE_FLAG_NVSYNC; 4174 4175 pipe_config->hw.adjusted_mode.flags |= flags; 4176 4177 switch (temp & TRANS_DDI_BPC_MASK) { 4178 case TRANS_DDI_BPC_6: 4179 pipe_config->pipe_bpp = 18; 4180 break; 4181 case TRANS_DDI_BPC_8: 4182 pipe_config->pipe_bpp = 24; 4183 break; 4184 case TRANS_DDI_BPC_10: 4185 pipe_config->pipe_bpp = 30; 4186 break; 4187 case TRANS_DDI_BPC_12: 4188 pipe_config->pipe_bpp = 36; 4189 break; 4190 default: 4191 break; 4192 } 4193 4194 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 4195 case TRANS_DDI_MODE_SELECT_HDMI: 4196 pipe_config->has_hdmi_sink = true; 4197 4198 pipe_config->infoframes.enable |= 4199 intel_hdmi_infoframes_enabled(encoder, pipe_config); 4200 4201 if (pipe_config->infoframes.enable) 4202 pipe_config->has_infoframe = true; 4203 4204 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 4205 pipe_config->hdmi_scrambling = true; 4206 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 4207 pipe_config->hdmi_high_tmds_clock_ratio = true; 4208 /* fall through */ 4209 case TRANS_DDI_MODE_SELECT_DVI: 4210 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 4211 pipe_config->lane_count = 4; 4212 break; 4213 case TRANS_DDI_MODE_SELECT_FDI: 4214 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 4215 break; 4216 case TRANS_DDI_MODE_SELECT_DP_SST: 4217 if (encoder->type == INTEL_OUTPUT_EDP) 4218 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 4219 else 4220 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 4221 pipe_config->lane_count = 4222 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4223 intel_dp_get_m_n(intel_crtc, pipe_config); 4224 4225 if (INTEL_GEN(dev_priv) >= 11) { 4226 i915_reg_t dp_tp_ctl; 4227 4228 if (IS_GEN(dev_priv, 11)) 4229 dp_tp_ctl = DP_TP_CTL(encoder->port); 4230 else 4231 dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder); 4232 4233 pipe_config->fec_enable = 4234 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE; 4235 4236 drm_dbg_kms(&dev_priv->drm, 4237 "[ENCODER:%d:%s] Fec status: %u\n", 4238 encoder->base.base.id, encoder->base.name, 4239 pipe_config->fec_enable); 4240 } 4241 4242 pipe_config->infoframes.enable |= 4243 intel_hdmi_infoframes_enabled(encoder, pipe_config); 4244 4245 break; 4246 case TRANS_DDI_MODE_SELECT_DP_MST: 4247 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 4248 pipe_config->lane_count = 4249 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4250 4251 if (INTEL_GEN(dev_priv) >= 12) 4252 pipe_config->mst_master_transcoder = 4253 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); 4254 4255 intel_dp_get_m_n(intel_crtc, pipe_config); 4256 4257 pipe_config->infoframes.enable |= 4258 intel_hdmi_infoframes_enabled(encoder, pipe_config); 4259 break; 4260 default: 4261 break; 4262 } 4263 4264 pipe_config->has_audio = 4265 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 4266 4267 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp && 4268 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { 4269 /* 4270 * This is a big fat ugly hack. 4271 * 4272 * Some machines in UEFI boot mode provide us a VBT that has 18 4273 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 4274 * unknown we fail to light up. Yet the same BIOS boots up with 4275 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 4276 * max, not what it tells us to use. 4277 * 4278 * Note: This will still be broken if the eDP panel is not lit 4279 * up by the BIOS, and thus we can't get the mode at module 4280 * load. 4281 */ 4282 drm_dbg_kms(&dev_priv->drm, 4283 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 4284 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); 4285 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; 4286 } 4287 4288 intel_ddi_clock_get(encoder, pipe_config); 4289 4290 if (IS_GEN9_LP(dev_priv)) 4291 pipe_config->lane_lat_optim_mask = 4292 bxt_ddi_phy_get_lane_lat_optim_mask(encoder); 4293 4294 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 4295 4296 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 4297 4298 intel_read_infoframe(encoder, pipe_config, 4299 HDMI_INFOFRAME_TYPE_AVI, 4300 &pipe_config->infoframes.avi); 4301 intel_read_infoframe(encoder, pipe_config, 4302 HDMI_INFOFRAME_TYPE_SPD, 4303 &pipe_config->infoframes.spd); 4304 intel_read_infoframe(encoder, pipe_config, 4305 HDMI_INFOFRAME_TYPE_VENDOR, 4306 &pipe_config->infoframes.hdmi); 4307 intel_read_infoframe(encoder, pipe_config, 4308 HDMI_INFOFRAME_TYPE_DRM, 4309 &pipe_config->infoframes.drm); 4310 4311 if (INTEL_GEN(dev_priv) >= 8) 4312 bdw_get_trans_port_sync_config(pipe_config); 4313 4314 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 4315 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 4316 } 4317 4318 static enum intel_output_type 4319 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4320 struct intel_crtc_state *crtc_state, 4321 struct drm_connector_state *conn_state) 4322 { 4323 switch (conn_state->connector->connector_type) { 4324 case DRM_MODE_CONNECTOR_HDMIA: 4325 return INTEL_OUTPUT_HDMI; 4326 case DRM_MODE_CONNECTOR_eDP: 4327 return INTEL_OUTPUT_EDP; 4328 case DRM_MODE_CONNECTOR_DisplayPort: 4329 return INTEL_OUTPUT_DP; 4330 default: 4331 MISSING_CASE(conn_state->connector->connector_type); 4332 return INTEL_OUTPUT_UNUSED; 4333 } 4334 } 4335 4336 static int intel_ddi_compute_config(struct intel_encoder *encoder, 4337 struct intel_crtc_state *pipe_config, 4338 struct drm_connector_state *conn_state) 4339 { 4340 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4341 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4342 enum port port = encoder->port; 4343 int ret; 4344 4345 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 4346 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4347 4348 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4349 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4350 } else { 4351 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 4352 } 4353 4354 if (ret) 4355 return ret; 4356 4357 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 4358 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4359 pipe_config->pch_pfit.force_thru = 4360 pipe_config->pch_pfit.enabled || 4361 pipe_config->crc_enabled; 4362 4363 if (IS_GEN9_LP(dev_priv)) 4364 pipe_config->lane_lat_optim_mask = 4365 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4366 4367 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 4368 4369 return 0; 4370 } 4371 4372 static bool mode_equal(const struct drm_display_mode *mode1, 4373 const struct drm_display_mode *mode2) 4374 { 4375 return drm_mode_match(mode1, mode2, 4376 DRM_MODE_MATCH_TIMINGS | 4377 DRM_MODE_MATCH_FLAGS | 4378 DRM_MODE_MATCH_3D_FLAGS) && 4379 mode1->clock == mode2->clock; /* we want an exact match */ 4380 } 4381 4382 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 4383 const struct intel_link_m_n *m_n_2) 4384 { 4385 return m_n_1->tu == m_n_2->tu && 4386 m_n_1->gmch_m == m_n_2->gmch_m && 4387 m_n_1->gmch_n == m_n_2->gmch_n && 4388 m_n_1->link_m == m_n_2->link_m && 4389 m_n_1->link_n == m_n_2->link_n; 4390 } 4391 4392 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 4393 const struct intel_crtc_state *crtc_state2) 4394 { 4395 return crtc_state1->hw.active && crtc_state2->hw.active && 4396 crtc_state1->output_types == crtc_state2->output_types && 4397 crtc_state1->output_format == crtc_state2->output_format && 4398 crtc_state1->lane_count == crtc_state2->lane_count && 4399 crtc_state1->port_clock == crtc_state2->port_clock && 4400 mode_equal(&crtc_state1->hw.adjusted_mode, 4401 &crtc_state2->hw.adjusted_mode) && 4402 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 4403 } 4404 4405 static u8 4406 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4407 int tile_group_id) 4408 { 4409 struct drm_connector *connector; 4410 const struct drm_connector_state *conn_state; 4411 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 4412 struct intel_atomic_state *state = 4413 to_intel_atomic_state(ref_crtc_state->uapi.state); 4414 u8 transcoders = 0; 4415 int i; 4416 4417 /* 4418 * We don't enable port sync on BDW due to missing w/as and 4419 * due to not having adjusted the modeset sequence appropriately. 4420 */ 4421 if (INTEL_GEN(dev_priv) < 9) 4422 return 0; 4423 4424 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4425 return 0; 4426 4427 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4428 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4429 const struct intel_crtc_state *crtc_state; 4430 4431 if (!crtc) 4432 continue; 4433 4434 if (!connector->has_tile || 4435 connector->tile_group->id != 4436 tile_group_id) 4437 continue; 4438 crtc_state = intel_atomic_get_new_crtc_state(state, 4439 crtc); 4440 if (!crtcs_port_sync_compatible(ref_crtc_state, 4441 crtc_state)) 4442 continue; 4443 transcoders |= BIT(crtc_state->cpu_transcoder); 4444 } 4445 4446 return transcoders; 4447 } 4448 4449 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 4450 struct intel_crtc_state *crtc_state, 4451 struct drm_connector_state *conn_state) 4452 { 4453 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4454 struct drm_connector *connector = conn_state->connector; 4455 u8 port_sync_transcoders = 0; 4456 4457 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]", 4458 encoder->base.base.id, encoder->base.name, 4459 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4460 4461 if (connector->has_tile) 4462 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4463 connector->tile_group->id); 4464 4465 /* 4466 * EDP Transcoders cannot be ensalved 4467 * make them a master always when present 4468 */ 4469 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4470 crtc_state->master_transcoder = TRANSCODER_EDP; 4471 else 4472 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4473 4474 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4475 crtc_state->master_transcoder = INVALID_TRANSCODER; 4476 crtc_state->sync_mode_slaves_mask = 4477 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4478 } 4479 4480 return 0; 4481 } 4482 4483 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4484 { 4485 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4486 4487 intel_dp_encoder_flush_work(encoder); 4488 4489 drm_encoder_cleanup(encoder); 4490 kfree(dig_port); 4491 } 4492 4493 static const struct drm_encoder_funcs intel_ddi_funcs = { 4494 .reset = intel_dp_encoder_reset, 4495 .destroy = intel_ddi_encoder_destroy, 4496 }; 4497 4498 static struct intel_connector * 4499 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) 4500 { 4501 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); 4502 struct intel_connector *connector; 4503 enum port port = intel_dig_port->base.port; 4504 4505 connector = intel_connector_alloc(); 4506 if (!connector) 4507 return NULL; 4508 4509 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); 4510 intel_dig_port->dp.prepare_link_retrain = 4511 intel_ddi_prepare_link_retrain; 4512 intel_dig_port->dp.set_link_train = intel_ddi_set_link_train; 4513 intel_dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4514 4515 if (INTEL_GEN(dev_priv) >= 12) 4516 intel_dig_port->dp.set_signal_levels = tgl_set_signal_levels; 4517 else if (INTEL_GEN(dev_priv) >= 11) 4518 intel_dig_port->dp.set_signal_levels = icl_set_signal_levels; 4519 else if (IS_CANNONLAKE(dev_priv)) 4520 intel_dig_port->dp.set_signal_levels = cnl_set_signal_levels; 4521 else if (IS_GEN9_LP(dev_priv)) 4522 intel_dig_port->dp.set_signal_levels = bxt_set_signal_levels; 4523 else 4524 intel_dig_port->dp.set_signal_levels = hsw_set_signal_levels; 4525 4526 if (INTEL_GEN(dev_priv) < 12) { 4527 intel_dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port); 4528 intel_dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port); 4529 } 4530 4531 if (!intel_dp_init_connector(intel_dig_port, connector)) { 4532 kfree(connector); 4533 return NULL; 4534 } 4535 4536 return connector; 4537 } 4538 4539 static int modeset_pipe(struct drm_crtc *crtc, 4540 struct drm_modeset_acquire_ctx *ctx) 4541 { 4542 struct drm_atomic_state *state; 4543 struct drm_crtc_state *crtc_state; 4544 int ret; 4545 4546 state = drm_atomic_state_alloc(crtc->dev); 4547 if (!state) 4548 return -ENOMEM; 4549 4550 state->acquire_ctx = ctx; 4551 4552 crtc_state = drm_atomic_get_crtc_state(state, crtc); 4553 if (IS_ERR(crtc_state)) { 4554 ret = PTR_ERR(crtc_state); 4555 goto out; 4556 } 4557 4558 crtc_state->connectors_changed = true; 4559 4560 ret = drm_atomic_commit(state); 4561 out: 4562 drm_atomic_state_put(state); 4563 4564 return ret; 4565 } 4566 4567 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4568 struct drm_modeset_acquire_ctx *ctx) 4569 { 4570 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4571 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4572 struct intel_connector *connector = hdmi->attached_connector; 4573 struct i2c_adapter *adapter = 4574 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 4575 struct drm_connector_state *conn_state; 4576 struct intel_crtc_state *crtc_state; 4577 struct intel_crtc *crtc; 4578 u8 config; 4579 int ret; 4580 4581 if (!connector || connector->base.status != connector_status_connected) 4582 return 0; 4583 4584 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 4585 ctx); 4586 if (ret) 4587 return ret; 4588 4589 conn_state = connector->base.state; 4590 4591 crtc = to_intel_crtc(conn_state->crtc); 4592 if (!crtc) 4593 return 0; 4594 4595 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4596 if (ret) 4597 return ret; 4598 4599 crtc_state = to_intel_crtc_state(crtc->base.state); 4600 4601 drm_WARN_ON(&dev_priv->drm, 4602 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4603 4604 if (!crtc_state->hw.active) 4605 return 0; 4606 4607 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4608 !crtc_state->hdmi_scrambling) 4609 return 0; 4610 4611 if (conn_state->commit && 4612 !try_wait_for_completion(&conn_state->commit->hw_done)) 4613 return 0; 4614 4615 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 4616 if (ret < 0) { 4617 drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n", 4618 ret); 4619 return 0; 4620 } 4621 4622 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4623 crtc_state->hdmi_high_tmds_clock_ratio && 4624 !!(config & SCDC_SCRAMBLING_ENABLE) == 4625 crtc_state->hdmi_scrambling) 4626 return 0; 4627 4628 /* 4629 * HDMI 2.0 says that one should not send scrambled data 4630 * prior to configuring the sink scrambling, and that 4631 * TMDS clock/data transmission should be suspended when 4632 * changing the TMDS clock rate in the sink. So let's 4633 * just do a full modeset here, even though some sinks 4634 * would be perfectly happy if were to just reconfigure 4635 * the SCDC settings on the fly. 4636 */ 4637 return modeset_pipe(&crtc->base, ctx); 4638 } 4639 4640 static enum intel_hotplug_state 4641 intel_ddi_hotplug(struct intel_encoder *encoder, 4642 struct intel_connector *connector) 4643 { 4644 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4645 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4646 enum phy phy = intel_port_to_phy(i915, encoder->port); 4647 bool is_tc = intel_phy_is_tc(i915, phy); 4648 struct drm_modeset_acquire_ctx ctx; 4649 enum intel_hotplug_state state; 4650 int ret; 4651 4652 state = intel_encoder_hotplug(encoder, connector); 4653 4654 drm_modeset_acquire_init(&ctx, 0); 4655 4656 for (;;) { 4657 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) 4658 ret = intel_hdmi_reset_link(encoder, &ctx); 4659 else 4660 ret = intel_dp_retrain_link(encoder, &ctx); 4661 4662 if (ret == -EDEADLK) { 4663 drm_modeset_backoff(&ctx); 4664 continue; 4665 } 4666 4667 break; 4668 } 4669 4670 drm_modeset_drop_locks(&ctx); 4671 drm_modeset_acquire_fini(&ctx); 4672 drm_WARN(encoder->base.dev, ret, 4673 "Acquiring modeset locks failed with %i\n", ret); 4674 4675 /* 4676 * Unpowered type-c dongles can take some time to boot and be 4677 * responsible, so here giving some time to those dongles to power up 4678 * and then retrying the probe. 4679 * 4680 * On many platforms the HDMI live state signal is known to be 4681 * unreliable, so we can't use it to detect if a sink is connected or 4682 * not. Instead we detect if it's connected based on whether we can 4683 * read the EDID or not. That in turn has a problem during disconnect, 4684 * since the HPD interrupt may be raised before the DDC lines get 4685 * disconnected (due to how the required length of DDC vs. HPD 4686 * connector pins are specified) and so we'll still be able to get a 4687 * valid EDID. To solve this schedule another detection cycle if this 4688 * time around we didn't detect any change in the sink's connection 4689 * status. 4690 * 4691 * Type-c connectors which get their HPD signal deasserted then 4692 * reasserted, without unplugging/replugging the sink from the 4693 * connector, introduce a delay until the AUX channel communication 4694 * becomes functional. Retry the detection for 5 seconds on type-c 4695 * connectors to account for this delay. 4696 */ 4697 if (state == INTEL_HOTPLUG_UNCHANGED && 4698 connector->hotplug_retries < (is_tc ? 5 : 1) && 4699 !dig_port->dp.is_mst) 4700 state = INTEL_HOTPLUG_RETRY; 4701 4702 return state; 4703 } 4704 4705 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4706 { 4707 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4708 u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin]; 4709 4710 return intel_de_read(dev_priv, SDEISR) & bit; 4711 } 4712 4713 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4714 { 4715 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4716 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; 4717 4718 return intel_de_read(dev_priv, DEISR) & bit; 4719 } 4720 4721 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4722 { 4723 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4724 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; 4725 4726 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; 4727 } 4728 4729 static struct intel_connector * 4730 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) 4731 { 4732 struct intel_connector *connector; 4733 enum port port = intel_dig_port->base.port; 4734 4735 connector = intel_connector_alloc(); 4736 if (!connector) 4737 return NULL; 4738 4739 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4740 intel_hdmi_init_connector(intel_dig_port, connector); 4741 4742 return connector; 4743 } 4744 4745 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport) 4746 { 4747 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); 4748 4749 if (dport->base.port != PORT_A) 4750 return false; 4751 4752 if (dport->saved_port_bits & DDI_A_4_LANES) 4753 return false; 4754 4755 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4756 * supported configuration 4757 */ 4758 if (IS_GEN9_LP(dev_priv)) 4759 return true; 4760 4761 /* Cannonlake: Most of SKUs don't support DDI_E, and the only 4762 * one who does also have a full A/E split called 4763 * DDI_F what makes DDI_E useless. However for this 4764 * case let's trust VBT info. 4765 */ 4766 if (IS_CANNONLAKE(dev_priv) && 4767 !intel_bios_is_port_present(dev_priv, PORT_E)) 4768 return true; 4769 4770 return false; 4771 } 4772 4773 static int 4774 intel_ddi_max_lanes(struct intel_digital_port *intel_dport) 4775 { 4776 struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev); 4777 enum port port = intel_dport->base.port; 4778 int max_lanes = 4; 4779 4780 if (INTEL_GEN(dev_priv) >= 11) 4781 return max_lanes; 4782 4783 if (port == PORT_A || port == PORT_E) { 4784 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4785 max_lanes = port == PORT_A ? 4 : 0; 4786 else 4787 /* Both A and E share 2 lanes */ 4788 max_lanes = 2; 4789 } 4790 4791 /* 4792 * Some BIOS might fail to set this bit on port A if eDP 4793 * wasn't lit up at boot. Force this bit set when needed 4794 * so we use the proper lane count for our calculations. 4795 */ 4796 if (intel_ddi_a_force_4_lanes(intel_dport)) { 4797 drm_dbg_kms(&dev_priv->drm, 4798 "Forcing DDI_A_4_LANES for port A\n"); 4799 intel_dport->saved_port_bits |= DDI_A_4_LANES; 4800 max_lanes = 4; 4801 } 4802 4803 return max_lanes; 4804 } 4805 4806 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 4807 { 4808 struct intel_digital_port *intel_dig_port; 4809 struct intel_encoder *encoder; 4810 bool init_hdmi, init_dp, init_lspcon = false; 4811 enum phy phy = intel_port_to_phy(dev_priv, port); 4812 4813 init_hdmi = intel_bios_port_supports_dvi(dev_priv, port) || 4814 intel_bios_port_supports_hdmi(dev_priv, port); 4815 init_dp = intel_bios_port_supports_dp(dev_priv, port); 4816 4817 if (intel_bios_is_lspcon_present(dev_priv, port)) { 4818 /* 4819 * Lspcon device needs to be driven with DP connector 4820 * with special detection sequence. So make sure DP 4821 * is initialized before lspcon. 4822 */ 4823 init_dp = true; 4824 init_lspcon = true; 4825 init_hdmi = false; 4826 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", 4827 port_name(port)); 4828 } 4829 4830 if (!init_dp && !init_hdmi) { 4831 drm_dbg_kms(&dev_priv->drm, 4832 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 4833 port_name(port)); 4834 return; 4835 } 4836 4837 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 4838 if (!intel_dig_port) 4839 return; 4840 4841 encoder = &intel_dig_port->base; 4842 4843 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4844 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port)); 4845 4846 encoder->hotplug = intel_ddi_hotplug; 4847 encoder->compute_output_type = intel_ddi_compute_output_type; 4848 encoder->compute_config = intel_ddi_compute_config; 4849 encoder->compute_config_late = intel_ddi_compute_config_late; 4850 encoder->enable = intel_enable_ddi; 4851 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 4852 encoder->pre_enable = intel_ddi_pre_enable; 4853 encoder->disable = intel_disable_ddi; 4854 encoder->post_disable = intel_ddi_post_disable; 4855 encoder->update_pipe = intel_ddi_update_pipe; 4856 encoder->get_hw_state = intel_ddi_get_hw_state; 4857 encoder->get_config = intel_ddi_get_config; 4858 encoder->suspend = intel_dp_encoder_suspend; 4859 encoder->get_power_domains = intel_ddi_get_power_domains; 4860 4861 encoder->type = INTEL_OUTPUT_DDI; 4862 encoder->power_domain = intel_port_to_power_domain(port); 4863 encoder->port = port; 4864 encoder->cloneable = 0; 4865 encoder->pipe_mask = ~0; 4866 4867 if (INTEL_GEN(dev_priv) >= 11) 4868 intel_dig_port->saved_port_bits = intel_de_read(dev_priv, 4869 DDI_BUF_CTL(port)) & 4870 DDI_BUF_PORT_REVERSAL; 4871 else 4872 intel_dig_port->saved_port_bits = intel_de_read(dev_priv, 4873 DDI_BUF_CTL(port)) & 4874 (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 4875 4876 intel_dig_port->dp.output_reg = INVALID_MMIO_REG; 4877 intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port); 4878 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 4879 4880 if (intel_phy_is_tc(dev_priv, phy)) { 4881 bool is_legacy = 4882 !intel_bios_port_supports_typec_usb(dev_priv, port) && 4883 !intel_bios_port_supports_tbt(dev_priv, port); 4884 4885 intel_tc_port_init(intel_dig_port, is_legacy); 4886 4887 encoder->update_prepare = intel_ddi_update_prepare; 4888 encoder->update_complete = intel_ddi_update_complete; 4889 } 4890 4891 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 4892 intel_dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO + 4893 port - PORT_A; 4894 4895 if (init_dp) { 4896 if (!intel_ddi_init_dp_connector(intel_dig_port)) 4897 goto err; 4898 4899 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; 4900 } 4901 4902 /* In theory we don't need the encoder->type check, but leave it just in 4903 * case we have some really bad VBTs... */ 4904 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 4905 if (!intel_ddi_init_hdmi_connector(intel_dig_port)) 4906 goto err; 4907 } 4908 4909 if (init_lspcon) { 4910 if (lspcon_init(intel_dig_port)) 4911 /* TODO: handle hdmi info frame part */ 4912 drm_dbg_kms(&dev_priv->drm, 4913 "LSPCON init success on port %c\n", 4914 port_name(port)); 4915 else 4916 /* 4917 * LSPCON init faied, but DP init was success, so 4918 * lets try to drive as DP++ port. 4919 */ 4920 drm_err(&dev_priv->drm, 4921 "LSPCON init failed on port %c\n", 4922 port_name(port)); 4923 } 4924 4925 if (INTEL_GEN(dev_priv) >= 11) { 4926 if (intel_phy_is_tc(dev_priv, phy)) 4927 intel_dig_port->connected = intel_tc_port_connected; 4928 else 4929 intel_dig_port->connected = lpt_digital_port_connected; 4930 } else if (INTEL_GEN(dev_priv) >= 8) { 4931 if (port == PORT_A || IS_GEN9_LP(dev_priv)) 4932 intel_dig_port->connected = bdw_digital_port_connected; 4933 else 4934 intel_dig_port->connected = lpt_digital_port_connected; 4935 } else { 4936 if (port == PORT_A) 4937 intel_dig_port->connected = hsw_digital_port_connected; 4938 else 4939 intel_dig_port->connected = lpt_digital_port_connected; 4940 } 4941 4942 intel_infoframe_init(intel_dig_port); 4943 4944 return; 4945 4946 err: 4947 drm_encoder_cleanup(&encoder->base); 4948 kfree(intel_dig_port); 4949 } 4950